2006.280.08:36:52.07:Log Opened: Mark IV Field System Version 9.7.7 2006.280.08:36:52.07:location,TSUKUB32,-140.09,36.10,61.0 2006.280.08:36:52.07:horizon1,0.,5.,360. 2006.280.08:36:52.08:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.280.08:36:52.08:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.280.08:36:52.08:drivev11,330,270,no 2006.280.08:36:52.09:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.280.08:36:52.09:drivev13,15.000,268,10.000,10.000,10.000 2006.280.08:36:52.10:drivev21,330,270,no 2006.280.08:36:52.10:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.280.08:36:52.15:drivev23,15.000,268,10.000,10.000,10.000 2006.280.08:36:52.15:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.280.08:36:52.16:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.280.08:36:52.16:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.280.08:36:52.16:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.280.08:36:52.17:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.280.08:36:52.17:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.280.08:36:52.17:time,-0.364,101.533,rate 2006.280.08:36:52.18:flagr,200 2006.280.08:36:52.18:proc=k06281ts 2006.280.08:36:52.18:" k06281 2006 tsukub32 t ts 2006.280.08:36:52.23:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.280.08:36:52.24:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.280.08:36:52.24:" 108 tsukub32 14 17400 2006.280.08:36:52.24:" drudg version 050216 compiled under fs 9.7.07 2006.280.08:36:52.25:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.280.08:36:52.25:!2006.281.06:29:50 2006.281.06:29:50.02:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.281.06:29:50.04:!2006.281.07:19:50 2006.281.07:19:50.00:unstow 2006.281.07:19:50.00&unstow/antenna=e 2006.281.07:19:50.00&unstow/!+10s 2006.281.07:19:50.00&unstow/antenna=m2 2006.281.07:20:02.01:scan_name=281-0730,k06281,60 2006.281.07:20:02.01:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.281.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.281.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.281.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.281.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.281.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.281.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.281.07:20:03.14:ready_k5 2006.281.07:20:03.14&ready_k5/obsinfo=st 2006.281.07:20:03.14&ready_k5/autoobs=1 2006.281.07:20:03.14&ready_k5/autoobs=2 2006.281.07:20:03.14&ready_k5/autoobs=3 2006.281.07:20:03.14&ready_k5/autoobs=4 2006.281.07:20:03.14&ready_k5/obsinfo 2006.281.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.281.07:20:03.14#flagr#flagr/antenna,new-source 2006.281.07:20:06.91/autoobs//k5ts1/ autoobs started! 2006.281.07:20:10.46/autoobs//k5ts2/ autoobs started! 2006.281.07:20:14.15/autoobs//k5ts3/ autoobs started! 2006.281.07:20:17.79/autoobs//k5ts4/ autoobs started! 2006.281.07:20:17.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:20:17.82:4f8m12a=1 2006.281.07:20:17.82&4f8m12a/xlog=on 2006.281.07:20:17.82&4f8m12a/echo=on 2006.281.07:20:17.82&4f8m12a/pcalon 2006.281.07:20:17.82&4f8m12a/"tpicd=stop 2006.281.07:20:17.82&4f8m12a/vc4f8 2006.281.07:20:17.82&4f8m12a/ifd4f 2006.281.07:20:17.82&4f8m12a/"form=m,16.000,1:2 2006.281.07:20:17.82&4f8m12a/"tpicd 2006.281.07:20:17.82&4f8m12a/echo=off 2006.281.07:20:17.82&4f8m12a/xlog=off 2006.281.07:20:17.82$4f8m12a/echo=on 2006.281.07:20:17.82$4f8m12a/pcalon 2006.281.07:20:17.82&pcalon/"no phase cal control is implemented here 2006.281.07:20:17.82$pcalon/"no phase cal control is implemented here 2006.281.07:20:17.82$4f8m12a/"tpicd=stop 2006.281.07:20:17.82$4f8m12a/vc4f8 2006.281.07:20:17.82&vc4f8/valo=1,532.99 2006.281.07:20:17.82&vc4f8/va=1,7 2006.281.07:20:17.82&vc4f8/valo=2,572.99 2006.281.07:20:17.82&vc4f8/va=2,6 2006.281.07:20:17.82&vc4f8/valo=3,672.99 2006.281.07:20:17.82&vc4f8/va=3,6 2006.281.07:20:17.82&vc4f8/valo=4,832.99 2006.281.07:20:17.82&vc4f8/va=4,6 2006.281.07:20:17.82&vc4f8/valo=5,652.99 2006.281.07:20:17.82&vc4f8/va=5,7 2006.281.07:20:17.82&vc4f8/valo=6,772.99 2006.281.07:20:17.82&vc4f8/va=6,6 2006.281.07:20:17.82&vc4f8/valo=7,832.99 2006.281.07:20:17.82&vc4f8/va=7,6 2006.281.07:20:17.82&vc4f8/valo=8,852.99 2006.281.07:20:17.82&vc4f8/va=8,6 2006.281.07:20:17.82&vc4f8/vblo=1,632.99 2006.281.07:20:17.82&vc4f8/vb=1,4 2006.281.07:20:17.82&vc4f8/vblo=2,640.99 2006.281.07:20:17.82&vc4f8/vb=2,5 2006.281.07:20:17.82&vc4f8/vblo=3,656.99 2006.281.07:20:17.82&vc4f8/vb=3,4 2006.281.07:20:17.82&vc4f8/vblo=4,712.99 2006.281.07:20:17.82&vc4f8/vb=4,4 2006.281.07:20:17.82&vc4f8/vblo=5,744.99 2006.281.07:20:17.82&vc4f8/vb=5,4 2006.281.07:20:17.82&vc4f8/vblo=6,752.99 2006.281.07:20:17.82&vc4f8/vb=6,4 2006.281.07:20:17.82&vc4f8/vabw=wide 2006.281.07:20:17.83&vc4f8/vbbw=wide 2006.281.07:20:17.83$vc4f8/valo=1,532.99 2006.281.07:20:17.84#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:20:17.84#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:20:17.84#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:17.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:17.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:17.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:17.84#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:20:17.84#ibcon#first serial, iclass 20, count 0 2006.281.07:20:17.84#ibcon#enter sib2, iclass 20, count 0 2006.281.07:20:17.84#ibcon#flushed, iclass 20, count 0 2006.281.07:20:17.84#ibcon#about to write, iclass 20, count 0 2006.281.07:20:17.84#ibcon#wrote, iclass 20, count 0 2006.281.07:20:17.84#ibcon#about to read 3, iclass 20, count 0 2006.281.07:20:17.85#ibcon#read 3, iclass 20, count 0 2006.281.07:20:17.89#ibcon#about to read 4, iclass 20, count 0 2006.281.07:20:17.89#ibcon#read 4, iclass 20, count 0 2006.281.07:20:17.89#ibcon#about to read 5, iclass 20, count 0 2006.281.07:20:17.89#ibcon#read 5, iclass 20, count 0 2006.281.07:20:17.89#ibcon#about to read 6, iclass 20, count 0 2006.281.07:20:17.89#ibcon#read 6, iclass 20, count 0 2006.281.07:20:17.89#ibcon#end of sib2, iclass 20, count 0 2006.281.07:20:17.89#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:20:17.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:20:17.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:20:17.89#ibcon#*before write, iclass 20, count 0 2006.281.07:20:17.89#ibcon#enter sib2, iclass 20, count 0 2006.281.07:20:17.89#ibcon#flushed, iclass 20, count 0 2006.281.07:20:17.89#ibcon#about to write, iclass 20, count 0 2006.281.07:20:17.89#ibcon#wrote, iclass 20, count 0 2006.281.07:20:17.89#ibcon#about to read 3, iclass 20, count 0 2006.281.07:20:17.94#ibcon#read 3, iclass 20, count 0 2006.281.07:20:17.94#ibcon#about to read 4, iclass 20, count 0 2006.281.07:20:17.94#ibcon#read 4, iclass 20, count 0 2006.281.07:20:17.94#ibcon#about to read 5, iclass 20, count 0 2006.281.07:20:17.94#ibcon#read 5, iclass 20, count 0 2006.281.07:20:17.94#ibcon#about to read 6, iclass 20, count 0 2006.281.07:20:17.94#ibcon#read 6, iclass 20, count 0 2006.281.07:20:17.94#ibcon#end of sib2, iclass 20, count 0 2006.281.07:20:17.94#ibcon#*after write, iclass 20, count 0 2006.281.07:20:17.94#ibcon#*before return 0, iclass 20, count 0 2006.281.07:20:17.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:17.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:17.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:20:17.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:20:17.94$vc4f8/va=1,7 2006.281.07:20:17.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:20:17.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:20:17.94#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:17.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:17.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:17.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:17.94#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:20:17.94#ibcon#first serial, iclass 22, count 2 2006.281.07:20:17.94#ibcon#enter sib2, iclass 22, count 2 2006.281.07:20:17.94#ibcon#flushed, iclass 22, count 2 2006.281.07:20:17.94#ibcon#about to write, iclass 22, count 2 2006.281.07:20:17.94#ibcon#wrote, iclass 22, count 2 2006.281.07:20:17.94#ibcon#about to read 3, iclass 22, count 2 2006.281.07:20:17.96#ibcon#read 3, iclass 22, count 2 2006.281.07:20:17.96#ibcon#about to read 4, iclass 22, count 2 2006.281.07:20:17.96#ibcon#read 4, iclass 22, count 2 2006.281.07:20:17.96#ibcon#about to read 5, iclass 22, count 2 2006.281.07:20:17.96#ibcon#read 5, iclass 22, count 2 2006.281.07:20:17.96#ibcon#about to read 6, iclass 22, count 2 2006.281.07:20:17.96#ibcon#read 6, iclass 22, count 2 2006.281.07:20:17.96#ibcon#end of sib2, iclass 22, count 2 2006.281.07:20:17.96#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:20:17.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:20:17.96#ibcon#[25=AT01-07\r\n] 2006.281.07:20:17.96#ibcon#*before write, iclass 22, count 2 2006.281.07:20:17.96#ibcon#enter sib2, iclass 22, count 2 2006.281.07:20:17.96#ibcon#flushed, iclass 22, count 2 2006.281.07:20:17.96#ibcon#about to write, iclass 22, count 2 2006.281.07:20:17.96#ibcon#wrote, iclass 22, count 2 2006.281.07:20:17.96#ibcon#about to read 3, iclass 22, count 2 2006.281.07:20:17.99#ibcon#read 3, iclass 22, count 2 2006.281.07:20:18.00#ibcon#about to read 4, iclass 22, count 2 2006.281.07:20:18.00#ibcon#read 4, iclass 22, count 2 2006.281.07:20:18.00#ibcon#about to read 5, iclass 22, count 2 2006.281.07:20:18.00#ibcon#read 5, iclass 22, count 2 2006.281.07:20:18.00#ibcon#about to read 6, iclass 22, count 2 2006.281.07:20:18.00#ibcon#read 6, iclass 22, count 2 2006.281.07:20:18.00#ibcon#end of sib2, iclass 22, count 2 2006.281.07:20:18.00#ibcon#*after write, iclass 22, count 2 2006.281.07:20:18.00#ibcon#*before return 0, iclass 22, count 2 2006.281.07:20:18.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:18.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:18.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:20:18.00#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:18.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:18.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:18.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:18.12#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:20:18.12#ibcon#first serial, iclass 22, count 0 2006.281.07:20:18.12#ibcon#enter sib2, iclass 22, count 0 2006.281.07:20:18.12#ibcon#flushed, iclass 22, count 0 2006.281.07:20:18.12#ibcon#about to write, iclass 22, count 0 2006.281.07:20:18.12#ibcon#wrote, iclass 22, count 0 2006.281.07:20:18.12#ibcon#about to read 3, iclass 22, count 0 2006.281.07:20:18.14#ibcon#read 3, iclass 22, count 0 2006.281.07:20:18.14#ibcon#about to read 4, iclass 22, count 0 2006.281.07:20:18.14#ibcon#read 4, iclass 22, count 0 2006.281.07:20:18.14#ibcon#about to read 5, iclass 22, count 0 2006.281.07:20:18.14#ibcon#read 5, iclass 22, count 0 2006.281.07:20:18.14#ibcon#about to read 6, iclass 22, count 0 2006.281.07:20:18.14#ibcon#read 6, iclass 22, count 0 2006.281.07:20:18.14#ibcon#end of sib2, iclass 22, count 0 2006.281.07:20:18.14#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:20:18.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:20:18.14#ibcon#[25=USB\r\n] 2006.281.07:20:18.14#ibcon#*before write, iclass 22, count 0 2006.281.07:20:18.14#ibcon#enter sib2, iclass 22, count 0 2006.281.07:20:18.14#ibcon#flushed, iclass 22, count 0 2006.281.07:20:18.14#ibcon#about to write, iclass 22, count 0 2006.281.07:20:18.14#ibcon#wrote, iclass 22, count 0 2006.281.07:20:18.14#ibcon#about to read 3, iclass 22, count 0 2006.281.07:20:18.17#ibcon#read 3, iclass 22, count 0 2006.281.07:20:18.17#ibcon#about to read 4, iclass 22, count 0 2006.281.07:20:18.17#ibcon#read 4, iclass 22, count 0 2006.281.07:20:18.17#ibcon#about to read 5, iclass 22, count 0 2006.281.07:20:18.17#ibcon#read 5, iclass 22, count 0 2006.281.07:20:18.17#ibcon#about to read 6, iclass 22, count 0 2006.281.07:20:18.17#ibcon#read 6, iclass 22, count 0 2006.281.07:20:18.17#ibcon#end of sib2, iclass 22, count 0 2006.281.07:20:18.17#ibcon#*after write, iclass 22, count 0 2006.281.07:20:18.17#ibcon#*before return 0, iclass 22, count 0 2006.281.07:20:18.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:18.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:18.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:20:18.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:20:18.17$vc4f8/valo=2,572.99 2006.281.07:20:18.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:20:18.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:20:18.17#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:18.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:18.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:18.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:18.17#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:20:18.17#ibcon#first serial, iclass 24, count 0 2006.281.07:20:18.17#ibcon#enter sib2, iclass 24, count 0 2006.281.07:20:18.17#ibcon#flushed, iclass 24, count 0 2006.281.07:20:18.17#ibcon#about to write, iclass 24, count 0 2006.281.07:20:18.17#ibcon#wrote, iclass 24, count 0 2006.281.07:20:18.17#ibcon#about to read 3, iclass 24, count 0 2006.281.07:20:18.19#ibcon#read 3, iclass 24, count 0 2006.281.07:20:18.19#ibcon#about to read 4, iclass 24, count 0 2006.281.07:20:18.19#ibcon#read 4, iclass 24, count 0 2006.281.07:20:18.19#ibcon#about to read 5, iclass 24, count 0 2006.281.07:20:18.19#ibcon#read 5, iclass 24, count 0 2006.281.07:20:18.19#ibcon#about to read 6, iclass 24, count 0 2006.281.07:20:18.19#ibcon#read 6, iclass 24, count 0 2006.281.07:20:18.19#ibcon#end of sib2, iclass 24, count 0 2006.281.07:20:18.19#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:20:18.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:20:18.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:20:18.19#ibcon#*before write, iclass 24, count 0 2006.281.07:20:18.20#ibcon#enter sib2, iclass 24, count 0 2006.281.07:20:18.20#ibcon#flushed, iclass 24, count 0 2006.281.07:20:18.20#ibcon#about to write, iclass 24, count 0 2006.281.07:20:18.20#ibcon#wrote, iclass 24, count 0 2006.281.07:20:18.20#ibcon#about to read 3, iclass 24, count 0 2006.281.07:20:18.24#ibcon#read 3, iclass 24, count 0 2006.281.07:20:18.24#ibcon#about to read 4, iclass 24, count 0 2006.281.07:20:18.24#ibcon#read 4, iclass 24, count 0 2006.281.07:20:18.24#ibcon#about to read 5, iclass 24, count 0 2006.281.07:20:18.24#ibcon#read 5, iclass 24, count 0 2006.281.07:20:18.24#ibcon#about to read 6, iclass 24, count 0 2006.281.07:20:18.24#ibcon#read 6, iclass 24, count 0 2006.281.07:20:18.24#ibcon#end of sib2, iclass 24, count 0 2006.281.07:20:18.24#ibcon#*after write, iclass 24, count 0 2006.281.07:20:18.24#ibcon#*before return 0, iclass 24, count 0 2006.281.07:20:18.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:18.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:18.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:20:18.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:20:18.24$vc4f8/va=2,6 2006.281.07:20:18.24#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:20:18.24#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:20:18.24#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:18.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:18.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:18.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:18.29#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:20:18.29#ibcon#first serial, iclass 26, count 2 2006.281.07:20:18.29#ibcon#enter sib2, iclass 26, count 2 2006.281.07:20:18.29#ibcon#flushed, iclass 26, count 2 2006.281.07:20:18.29#ibcon#about to write, iclass 26, count 2 2006.281.07:20:18.29#ibcon#wrote, iclass 26, count 2 2006.281.07:20:18.29#ibcon#about to read 3, iclass 26, count 2 2006.281.07:20:18.31#ibcon#read 3, iclass 26, count 2 2006.281.07:20:18.31#ibcon#about to read 4, iclass 26, count 2 2006.281.07:20:18.31#ibcon#read 4, iclass 26, count 2 2006.281.07:20:18.31#ibcon#about to read 5, iclass 26, count 2 2006.281.07:20:18.31#ibcon#read 5, iclass 26, count 2 2006.281.07:20:18.31#ibcon#about to read 6, iclass 26, count 2 2006.281.07:20:18.31#ibcon#read 6, iclass 26, count 2 2006.281.07:20:18.31#ibcon#end of sib2, iclass 26, count 2 2006.281.07:20:18.31#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:20:18.31#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:20:18.31#ibcon#[25=AT02-06\r\n] 2006.281.07:20:18.31#ibcon#*before write, iclass 26, count 2 2006.281.07:20:18.31#ibcon#enter sib2, iclass 26, count 2 2006.281.07:20:18.31#ibcon#flushed, iclass 26, count 2 2006.281.07:20:18.31#ibcon#about to write, iclass 26, count 2 2006.281.07:20:18.31#ibcon#wrote, iclass 26, count 2 2006.281.07:20:18.31#ibcon#about to read 3, iclass 26, count 2 2006.281.07:20:18.34#ibcon#read 3, iclass 26, count 2 2006.281.07:20:18.34#ibcon#about to read 4, iclass 26, count 2 2006.281.07:20:18.34#ibcon#read 4, iclass 26, count 2 2006.281.07:20:18.34#ibcon#about to read 5, iclass 26, count 2 2006.281.07:20:18.34#ibcon#read 5, iclass 26, count 2 2006.281.07:20:18.34#ibcon#about to read 6, iclass 26, count 2 2006.281.07:20:18.34#ibcon#read 6, iclass 26, count 2 2006.281.07:20:18.34#ibcon#end of sib2, iclass 26, count 2 2006.281.07:20:18.34#ibcon#*after write, iclass 26, count 2 2006.281.07:20:18.34#ibcon#*before return 0, iclass 26, count 2 2006.281.07:20:18.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:18.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:18.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:20:18.34#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:18.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:18.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:18.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:18.46#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:20:18.46#ibcon#first serial, iclass 26, count 0 2006.281.07:20:18.46#ibcon#enter sib2, iclass 26, count 0 2006.281.07:20:18.46#ibcon#flushed, iclass 26, count 0 2006.281.07:20:18.46#ibcon#about to write, iclass 26, count 0 2006.281.07:20:18.46#ibcon#wrote, iclass 26, count 0 2006.281.07:20:18.46#ibcon#about to read 3, iclass 26, count 0 2006.281.07:20:18.48#ibcon#read 3, iclass 26, count 0 2006.281.07:20:18.48#ibcon#about to read 4, iclass 26, count 0 2006.281.07:20:18.48#ibcon#read 4, iclass 26, count 0 2006.281.07:20:18.48#ibcon#about to read 5, iclass 26, count 0 2006.281.07:20:18.48#ibcon#read 5, iclass 26, count 0 2006.281.07:20:18.48#ibcon#about to read 6, iclass 26, count 0 2006.281.07:20:18.48#ibcon#read 6, iclass 26, count 0 2006.281.07:20:18.48#ibcon#end of sib2, iclass 26, count 0 2006.281.07:20:18.48#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:20:18.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:20:18.48#ibcon#[25=USB\r\n] 2006.281.07:20:18.48#ibcon#*before write, iclass 26, count 0 2006.281.07:20:18.48#ibcon#enter sib2, iclass 26, count 0 2006.281.07:20:18.48#ibcon#flushed, iclass 26, count 0 2006.281.07:20:18.48#ibcon#about to write, iclass 26, count 0 2006.281.07:20:18.48#ibcon#wrote, iclass 26, count 0 2006.281.07:20:18.48#ibcon#about to read 3, iclass 26, count 0 2006.281.07:20:18.51#ibcon#read 3, iclass 26, count 0 2006.281.07:20:18.51#ibcon#about to read 4, iclass 26, count 0 2006.281.07:20:18.51#ibcon#read 4, iclass 26, count 0 2006.281.07:20:18.51#ibcon#about to read 5, iclass 26, count 0 2006.281.07:20:18.51#ibcon#read 5, iclass 26, count 0 2006.281.07:20:18.51#ibcon#about to read 6, iclass 26, count 0 2006.281.07:20:18.51#ibcon#read 6, iclass 26, count 0 2006.281.07:20:18.51#ibcon#end of sib2, iclass 26, count 0 2006.281.07:20:18.51#ibcon#*after write, iclass 26, count 0 2006.281.07:20:18.51#ibcon#*before return 0, iclass 26, count 0 2006.281.07:20:18.51#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:18.51#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:18.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:20:18.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:20:18.51$vc4f8/valo=3,672.99 2006.281.07:20:18.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:20:18.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:20:18.51#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:18.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:18.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:18.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:18.51#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:20:18.51#ibcon#first serial, iclass 28, count 0 2006.281.07:20:18.51#ibcon#enter sib2, iclass 28, count 0 2006.281.07:20:18.51#ibcon#flushed, iclass 28, count 0 2006.281.07:20:18.51#ibcon#about to write, iclass 28, count 0 2006.281.07:20:18.51#ibcon#wrote, iclass 28, count 0 2006.281.07:20:18.51#ibcon#about to read 3, iclass 28, count 0 2006.281.07:20:18.53#ibcon#read 3, iclass 28, count 0 2006.281.07:20:18.53#ibcon#about to read 4, iclass 28, count 0 2006.281.07:20:18.53#ibcon#read 4, iclass 28, count 0 2006.281.07:20:18.53#ibcon#about to read 5, iclass 28, count 0 2006.281.07:20:18.53#ibcon#read 5, iclass 28, count 0 2006.281.07:20:18.53#ibcon#about to read 6, iclass 28, count 0 2006.281.07:20:18.53#ibcon#read 6, iclass 28, count 0 2006.281.07:20:18.53#ibcon#end of sib2, iclass 28, count 0 2006.281.07:20:18.53#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:20:18.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:20:18.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:20:18.53#ibcon#*before write, iclass 28, count 0 2006.281.07:20:18.53#ibcon#enter sib2, iclass 28, count 0 2006.281.07:20:18.53#ibcon#flushed, iclass 28, count 0 2006.281.07:20:18.53#ibcon#about to write, iclass 28, count 0 2006.281.07:20:18.53#ibcon#wrote, iclass 28, count 0 2006.281.07:20:18.53#ibcon#about to read 3, iclass 28, count 0 2006.281.07:20:18.57#ibcon#read 3, iclass 28, count 0 2006.281.07:20:18.57#ibcon#about to read 4, iclass 28, count 0 2006.281.07:20:18.57#ibcon#read 4, iclass 28, count 0 2006.281.07:20:18.57#ibcon#about to read 5, iclass 28, count 0 2006.281.07:20:18.57#ibcon#read 5, iclass 28, count 0 2006.281.07:20:18.57#ibcon#about to read 6, iclass 28, count 0 2006.281.07:20:18.57#ibcon#read 6, iclass 28, count 0 2006.281.07:20:18.57#ibcon#end of sib2, iclass 28, count 0 2006.281.07:20:18.57#ibcon#*after write, iclass 28, count 0 2006.281.07:20:18.57#ibcon#*before return 0, iclass 28, count 0 2006.281.07:20:18.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:18.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:18.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:20:18.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:20:18.59$vc4f8/va=3,6 2006.281.07:20:18.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:20:18.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:20:18.59#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:18.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:18.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:18.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:18.62#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:20:18.62#ibcon#first serial, iclass 30, count 2 2006.281.07:20:18.62#ibcon#enter sib2, iclass 30, count 2 2006.281.07:20:18.62#ibcon#flushed, iclass 30, count 2 2006.281.07:20:18.62#ibcon#about to write, iclass 30, count 2 2006.281.07:20:18.62#ibcon#wrote, iclass 30, count 2 2006.281.07:20:18.62#ibcon#about to read 3, iclass 30, count 2 2006.281.07:20:18.65#ibcon#read 3, iclass 30, count 2 2006.281.07:20:18.65#ibcon#about to read 4, iclass 30, count 2 2006.281.07:20:18.65#ibcon#read 4, iclass 30, count 2 2006.281.07:20:18.65#ibcon#about to read 5, iclass 30, count 2 2006.281.07:20:18.65#ibcon#read 5, iclass 30, count 2 2006.281.07:20:18.65#ibcon#about to read 6, iclass 30, count 2 2006.281.07:20:18.65#ibcon#read 6, iclass 30, count 2 2006.281.07:20:18.65#ibcon#end of sib2, iclass 30, count 2 2006.281.07:20:18.65#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:20:18.65#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:20:18.65#ibcon#[25=AT03-06\r\n] 2006.281.07:20:18.65#ibcon#*before write, iclass 30, count 2 2006.281.07:20:18.65#ibcon#enter sib2, iclass 30, count 2 2006.281.07:20:18.65#ibcon#flushed, iclass 30, count 2 2006.281.07:20:18.65#ibcon#about to write, iclass 30, count 2 2006.281.07:20:18.65#ibcon#wrote, iclass 30, count 2 2006.281.07:20:18.65#ibcon#about to read 3, iclass 30, count 2 2006.281.07:20:18.68#ibcon#read 3, iclass 30, count 2 2006.281.07:20:18.68#ibcon#about to read 4, iclass 30, count 2 2006.281.07:20:18.68#ibcon#read 4, iclass 30, count 2 2006.281.07:20:18.68#ibcon#about to read 5, iclass 30, count 2 2006.281.07:20:18.68#ibcon#read 5, iclass 30, count 2 2006.281.07:20:18.68#ibcon#about to read 6, iclass 30, count 2 2006.281.07:20:18.68#ibcon#read 6, iclass 30, count 2 2006.281.07:20:18.68#ibcon#end of sib2, iclass 30, count 2 2006.281.07:20:18.68#ibcon#*after write, iclass 30, count 2 2006.281.07:20:18.68#ibcon#*before return 0, iclass 30, count 2 2006.281.07:20:18.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:18.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:18.68#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:20:18.68#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:18.68#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:18.80#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:18.80#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:18.80#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:20:18.80#ibcon#first serial, iclass 30, count 0 2006.281.07:20:18.80#ibcon#enter sib2, iclass 30, count 0 2006.281.07:20:18.80#ibcon#flushed, iclass 30, count 0 2006.281.07:20:18.80#ibcon#about to write, iclass 30, count 0 2006.281.07:20:18.80#ibcon#wrote, iclass 30, count 0 2006.281.07:20:18.80#ibcon#about to read 3, iclass 30, count 0 2006.281.07:20:18.82#ibcon#read 3, iclass 30, count 0 2006.281.07:20:18.82#ibcon#about to read 4, iclass 30, count 0 2006.281.07:20:18.82#ibcon#read 4, iclass 30, count 0 2006.281.07:20:18.82#ibcon#about to read 5, iclass 30, count 0 2006.281.07:20:18.82#ibcon#read 5, iclass 30, count 0 2006.281.07:20:18.82#ibcon#about to read 6, iclass 30, count 0 2006.281.07:20:18.82#ibcon#read 6, iclass 30, count 0 2006.281.07:20:18.82#ibcon#end of sib2, iclass 30, count 0 2006.281.07:20:18.82#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:20:18.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:20:18.82#ibcon#[25=USB\r\n] 2006.281.07:20:18.82#ibcon#*before write, iclass 30, count 0 2006.281.07:20:18.82#ibcon#enter sib2, iclass 30, count 0 2006.281.07:20:18.82#ibcon#flushed, iclass 30, count 0 2006.281.07:20:18.82#ibcon#about to write, iclass 30, count 0 2006.281.07:20:18.82#ibcon#wrote, iclass 30, count 0 2006.281.07:20:18.82#ibcon#about to read 3, iclass 30, count 0 2006.281.07:20:18.85#ibcon#read 3, iclass 30, count 0 2006.281.07:20:18.85#ibcon#about to read 4, iclass 30, count 0 2006.281.07:20:18.85#ibcon#read 4, iclass 30, count 0 2006.281.07:20:18.85#ibcon#about to read 5, iclass 30, count 0 2006.281.07:20:18.85#ibcon#read 5, iclass 30, count 0 2006.281.07:20:18.85#ibcon#about to read 6, iclass 30, count 0 2006.281.07:20:18.85#ibcon#read 6, iclass 30, count 0 2006.281.07:20:18.85#ibcon#end of sib2, iclass 30, count 0 2006.281.07:20:18.85#ibcon#*after write, iclass 30, count 0 2006.281.07:20:18.85#ibcon#*before return 0, iclass 30, count 0 2006.281.07:20:18.85#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:18.85#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:18.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:20:18.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:20:18.85$vc4f8/valo=4,832.99 2006.281.07:20:18.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:20:18.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:20:18.85#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:18.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:18.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:18.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:18.85#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:20:18.85#ibcon#first serial, iclass 32, count 0 2006.281.07:20:18.85#ibcon#enter sib2, iclass 32, count 0 2006.281.07:20:18.85#ibcon#flushed, iclass 32, count 0 2006.281.07:20:18.85#ibcon#about to write, iclass 32, count 0 2006.281.07:20:18.85#ibcon#wrote, iclass 32, count 0 2006.281.07:20:18.85#ibcon#about to read 3, iclass 32, count 0 2006.281.07:20:18.87#ibcon#read 3, iclass 32, count 0 2006.281.07:20:18.87#ibcon#about to read 4, iclass 32, count 0 2006.281.07:20:18.87#ibcon#read 4, iclass 32, count 0 2006.281.07:20:18.87#ibcon#about to read 5, iclass 32, count 0 2006.281.07:20:18.87#ibcon#read 5, iclass 32, count 0 2006.281.07:20:18.87#ibcon#about to read 6, iclass 32, count 0 2006.281.07:20:18.87#ibcon#read 6, iclass 32, count 0 2006.281.07:20:18.87#ibcon#end of sib2, iclass 32, count 0 2006.281.07:20:18.87#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:20:18.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:20:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:20:18.87#ibcon#*before write, iclass 32, count 0 2006.281.07:20:18.87#ibcon#enter sib2, iclass 32, count 0 2006.281.07:20:18.87#ibcon#flushed, iclass 32, count 0 2006.281.07:20:18.87#ibcon#about to write, iclass 32, count 0 2006.281.07:20:18.87#ibcon#wrote, iclass 32, count 0 2006.281.07:20:18.87#ibcon#about to read 3, iclass 32, count 0 2006.281.07:20:18.91#ibcon#read 3, iclass 32, count 0 2006.281.07:20:18.91#ibcon#about to read 4, iclass 32, count 0 2006.281.07:20:18.91#ibcon#read 4, iclass 32, count 0 2006.281.07:20:18.91#ibcon#about to read 5, iclass 32, count 0 2006.281.07:20:18.91#ibcon#read 5, iclass 32, count 0 2006.281.07:20:18.91#ibcon#about to read 6, iclass 32, count 0 2006.281.07:20:18.91#ibcon#read 6, iclass 32, count 0 2006.281.07:20:18.91#ibcon#end of sib2, iclass 32, count 0 2006.281.07:20:18.91#ibcon#*after write, iclass 32, count 0 2006.281.07:20:18.91#ibcon#*before return 0, iclass 32, count 0 2006.281.07:20:18.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:18.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:18.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:20:18.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:20:18.91$vc4f8/va=4,6 2006.281.07:20:18.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:20:18.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:20:18.91#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:18.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:18.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:18.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:18.97#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:20:18.97#ibcon#first serial, iclass 34, count 2 2006.281.07:20:18.97#ibcon#enter sib2, iclass 34, count 2 2006.281.07:20:18.97#ibcon#flushed, iclass 34, count 2 2006.281.07:20:18.97#ibcon#about to write, iclass 34, count 2 2006.281.07:20:18.97#ibcon#wrote, iclass 34, count 2 2006.281.07:20:18.97#ibcon#about to read 3, iclass 34, count 2 2006.281.07:20:18.99#ibcon#read 3, iclass 34, count 2 2006.281.07:20:18.99#ibcon#about to read 4, iclass 34, count 2 2006.281.07:20:18.99#ibcon#read 4, iclass 34, count 2 2006.281.07:20:18.99#ibcon#about to read 5, iclass 34, count 2 2006.281.07:20:18.99#ibcon#read 5, iclass 34, count 2 2006.281.07:20:18.99#ibcon#about to read 6, iclass 34, count 2 2006.281.07:20:18.99#ibcon#read 6, iclass 34, count 2 2006.281.07:20:18.99#ibcon#end of sib2, iclass 34, count 2 2006.281.07:20:18.99#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:20:18.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:20:18.99#ibcon#[25=AT04-06\r\n] 2006.281.07:20:18.99#ibcon#*before write, iclass 34, count 2 2006.281.07:20:18.99#ibcon#enter sib2, iclass 34, count 2 2006.281.07:20:18.99#ibcon#flushed, iclass 34, count 2 2006.281.07:20:18.99#ibcon#about to write, iclass 34, count 2 2006.281.07:20:18.99#ibcon#wrote, iclass 34, count 2 2006.281.07:20:18.99#ibcon#about to read 3, iclass 34, count 2 2006.281.07:20:19.02#ibcon#read 3, iclass 34, count 2 2006.281.07:20:19.02#ibcon#about to read 4, iclass 34, count 2 2006.281.07:20:19.02#ibcon#read 4, iclass 34, count 2 2006.281.07:20:19.02#ibcon#about to read 5, iclass 34, count 2 2006.281.07:20:19.02#ibcon#read 5, iclass 34, count 2 2006.281.07:20:19.02#ibcon#about to read 6, iclass 34, count 2 2006.281.07:20:19.02#ibcon#read 6, iclass 34, count 2 2006.281.07:20:19.02#ibcon#end of sib2, iclass 34, count 2 2006.281.07:20:19.02#ibcon#*after write, iclass 34, count 2 2006.281.07:20:19.02#ibcon#*before return 0, iclass 34, count 2 2006.281.07:20:19.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:19.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:19.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:20:19.02#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:19.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:19.14#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:19.14#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:19.14#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:20:19.14#ibcon#first serial, iclass 34, count 0 2006.281.07:20:19.14#ibcon#enter sib2, iclass 34, count 0 2006.281.07:20:19.14#ibcon#flushed, iclass 34, count 0 2006.281.07:20:19.14#ibcon#about to write, iclass 34, count 0 2006.281.07:20:19.14#ibcon#wrote, iclass 34, count 0 2006.281.07:20:19.14#ibcon#about to read 3, iclass 34, count 0 2006.281.07:20:19.16#ibcon#read 3, iclass 34, count 0 2006.281.07:20:19.16#ibcon#about to read 4, iclass 34, count 0 2006.281.07:20:19.16#ibcon#read 4, iclass 34, count 0 2006.281.07:20:19.16#ibcon#about to read 5, iclass 34, count 0 2006.281.07:20:19.16#ibcon#read 5, iclass 34, count 0 2006.281.07:20:19.16#ibcon#about to read 6, iclass 34, count 0 2006.281.07:20:19.16#ibcon#read 6, iclass 34, count 0 2006.281.07:20:19.16#ibcon#end of sib2, iclass 34, count 0 2006.281.07:20:19.16#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:20:19.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:20:19.16#ibcon#[25=USB\r\n] 2006.281.07:20:19.16#ibcon#*before write, iclass 34, count 0 2006.281.07:20:19.16#ibcon#enter sib2, iclass 34, count 0 2006.281.07:20:19.16#ibcon#flushed, iclass 34, count 0 2006.281.07:20:19.16#ibcon#about to write, iclass 34, count 0 2006.281.07:20:19.16#ibcon#wrote, iclass 34, count 0 2006.281.07:20:19.16#ibcon#about to read 3, iclass 34, count 0 2006.281.07:20:19.19#ibcon#read 3, iclass 34, count 0 2006.281.07:20:19.19#ibcon#about to read 4, iclass 34, count 0 2006.281.07:20:19.19#ibcon#read 4, iclass 34, count 0 2006.281.07:20:19.19#ibcon#about to read 5, iclass 34, count 0 2006.281.07:20:19.19#ibcon#read 5, iclass 34, count 0 2006.281.07:20:19.19#ibcon#about to read 6, iclass 34, count 0 2006.281.07:20:19.19#ibcon#read 6, iclass 34, count 0 2006.281.07:20:19.19#ibcon#end of sib2, iclass 34, count 0 2006.281.07:20:19.19#ibcon#*after write, iclass 34, count 0 2006.281.07:20:19.19#ibcon#*before return 0, iclass 34, count 0 2006.281.07:20:19.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:19.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:19.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:20:19.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:20:19.19$vc4f8/valo=5,652.99 2006.281.07:20:19.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:20:19.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:20:19.19#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:19.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:19.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:19.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:19.19#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:20:19.19#ibcon#first serial, iclass 36, count 0 2006.281.07:20:19.19#ibcon#enter sib2, iclass 36, count 0 2006.281.07:20:19.19#ibcon#flushed, iclass 36, count 0 2006.281.07:20:19.19#ibcon#about to write, iclass 36, count 0 2006.281.07:20:19.19#ibcon#wrote, iclass 36, count 0 2006.281.07:20:19.19#ibcon#about to read 3, iclass 36, count 0 2006.281.07:20:19.21#ibcon#read 3, iclass 36, count 0 2006.281.07:20:19.21#ibcon#about to read 4, iclass 36, count 0 2006.281.07:20:19.21#ibcon#read 4, iclass 36, count 0 2006.281.07:20:19.21#ibcon#about to read 5, iclass 36, count 0 2006.281.07:20:19.21#ibcon#read 5, iclass 36, count 0 2006.281.07:20:19.21#ibcon#about to read 6, iclass 36, count 0 2006.281.07:20:19.21#ibcon#read 6, iclass 36, count 0 2006.281.07:20:19.21#ibcon#end of sib2, iclass 36, count 0 2006.281.07:20:19.21#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:20:19.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:20:19.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:20:19.21#ibcon#*before write, iclass 36, count 0 2006.281.07:20:19.21#ibcon#enter sib2, iclass 36, count 0 2006.281.07:20:19.21#ibcon#flushed, iclass 36, count 0 2006.281.07:20:19.21#ibcon#about to write, iclass 36, count 0 2006.281.07:20:19.21#ibcon#wrote, iclass 36, count 0 2006.281.07:20:19.21#ibcon#about to read 3, iclass 36, count 0 2006.281.07:20:19.25#ibcon#read 3, iclass 36, count 0 2006.281.07:20:19.25#ibcon#about to read 4, iclass 36, count 0 2006.281.07:20:19.25#ibcon#read 4, iclass 36, count 0 2006.281.07:20:19.25#ibcon#about to read 5, iclass 36, count 0 2006.281.07:20:19.25#ibcon#read 5, iclass 36, count 0 2006.281.07:20:19.25#ibcon#about to read 6, iclass 36, count 0 2006.281.07:20:19.25#ibcon#read 6, iclass 36, count 0 2006.281.07:20:19.25#ibcon#end of sib2, iclass 36, count 0 2006.281.07:20:19.25#ibcon#*after write, iclass 36, count 0 2006.281.07:20:19.25#ibcon#*before return 0, iclass 36, count 0 2006.281.07:20:19.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:19.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:19.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:20:19.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:20:19.25$vc4f8/va=5,7 2006.281.07:20:19.25#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:20:19.25#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:20:19.25#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:19.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:19.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:19.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:19.31#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:20:19.31#ibcon#first serial, iclass 38, count 2 2006.281.07:20:19.31#ibcon#enter sib2, iclass 38, count 2 2006.281.07:20:19.31#ibcon#flushed, iclass 38, count 2 2006.281.07:20:19.31#ibcon#about to write, iclass 38, count 2 2006.281.07:20:19.31#ibcon#wrote, iclass 38, count 2 2006.281.07:20:19.31#ibcon#about to read 3, iclass 38, count 2 2006.281.07:20:19.33#ibcon#read 3, iclass 38, count 2 2006.281.07:20:19.33#ibcon#about to read 4, iclass 38, count 2 2006.281.07:20:19.33#ibcon#read 4, iclass 38, count 2 2006.281.07:20:19.33#ibcon#about to read 5, iclass 38, count 2 2006.281.07:20:19.33#ibcon#read 5, iclass 38, count 2 2006.281.07:20:19.33#ibcon#about to read 6, iclass 38, count 2 2006.281.07:20:19.33#ibcon#read 6, iclass 38, count 2 2006.281.07:20:19.33#ibcon#end of sib2, iclass 38, count 2 2006.281.07:20:19.33#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:20:19.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:20:19.33#ibcon#[25=AT05-07\r\n] 2006.281.07:20:19.33#ibcon#*before write, iclass 38, count 2 2006.281.07:20:19.33#ibcon#enter sib2, iclass 38, count 2 2006.281.07:20:19.33#ibcon#flushed, iclass 38, count 2 2006.281.07:20:19.33#ibcon#about to write, iclass 38, count 2 2006.281.07:20:19.33#ibcon#wrote, iclass 38, count 2 2006.281.07:20:19.33#ibcon#about to read 3, iclass 38, count 2 2006.281.07:20:19.36#ibcon#read 3, iclass 38, count 2 2006.281.07:20:19.36#ibcon#about to read 4, iclass 38, count 2 2006.281.07:20:19.36#ibcon#read 4, iclass 38, count 2 2006.281.07:20:19.36#ibcon#about to read 5, iclass 38, count 2 2006.281.07:20:19.36#ibcon#read 5, iclass 38, count 2 2006.281.07:20:19.36#ibcon#about to read 6, iclass 38, count 2 2006.281.07:20:19.36#ibcon#read 6, iclass 38, count 2 2006.281.07:20:19.36#ibcon#end of sib2, iclass 38, count 2 2006.281.07:20:19.36#ibcon#*after write, iclass 38, count 2 2006.281.07:20:19.36#ibcon#*before return 0, iclass 38, count 2 2006.281.07:20:19.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:19.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:19.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:20:19.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:19.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:19.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:19.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:19.48#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:20:19.48#ibcon#first serial, iclass 38, count 0 2006.281.07:20:19.48#ibcon#enter sib2, iclass 38, count 0 2006.281.07:20:19.48#ibcon#flushed, iclass 38, count 0 2006.281.07:20:19.48#ibcon#about to write, iclass 38, count 0 2006.281.07:20:19.48#ibcon#wrote, iclass 38, count 0 2006.281.07:20:19.48#ibcon#about to read 3, iclass 38, count 0 2006.281.07:20:19.50#ibcon#read 3, iclass 38, count 0 2006.281.07:20:19.50#ibcon#about to read 4, iclass 38, count 0 2006.281.07:20:19.50#ibcon#read 4, iclass 38, count 0 2006.281.07:20:19.50#ibcon#about to read 5, iclass 38, count 0 2006.281.07:20:19.50#ibcon#read 5, iclass 38, count 0 2006.281.07:20:19.50#ibcon#about to read 6, iclass 38, count 0 2006.281.07:20:19.50#ibcon#read 6, iclass 38, count 0 2006.281.07:20:19.50#ibcon#end of sib2, iclass 38, count 0 2006.281.07:20:19.50#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:20:19.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:20:19.50#ibcon#[25=USB\r\n] 2006.281.07:20:19.50#ibcon#*before write, iclass 38, count 0 2006.281.07:20:19.50#ibcon#enter sib2, iclass 38, count 0 2006.281.07:20:19.50#ibcon#flushed, iclass 38, count 0 2006.281.07:20:19.50#ibcon#about to write, iclass 38, count 0 2006.281.07:20:19.50#ibcon#wrote, iclass 38, count 0 2006.281.07:20:19.50#ibcon#about to read 3, iclass 38, count 0 2006.281.07:20:19.53#ibcon#read 3, iclass 38, count 0 2006.281.07:20:19.53#ibcon#about to read 4, iclass 38, count 0 2006.281.07:20:19.53#ibcon#read 4, iclass 38, count 0 2006.281.07:20:19.53#ibcon#about to read 5, iclass 38, count 0 2006.281.07:20:19.53#ibcon#read 5, iclass 38, count 0 2006.281.07:20:19.53#ibcon#about to read 6, iclass 38, count 0 2006.281.07:20:19.53#ibcon#read 6, iclass 38, count 0 2006.281.07:20:19.53#ibcon#end of sib2, iclass 38, count 0 2006.281.07:20:19.53#ibcon#*after write, iclass 38, count 0 2006.281.07:20:19.53#ibcon#*before return 0, iclass 38, count 0 2006.281.07:20:19.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:19.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:19.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:20:19.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:20:19.53$vc4f8/valo=6,772.99 2006.281.07:20:19.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:20:19.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:20:19.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:19.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:19.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:19.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:19.53#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:20:19.53#ibcon#first serial, iclass 40, count 0 2006.281.07:20:19.53#ibcon#enter sib2, iclass 40, count 0 2006.281.07:20:19.53#ibcon#flushed, iclass 40, count 0 2006.281.07:20:19.53#ibcon#about to write, iclass 40, count 0 2006.281.07:20:19.53#ibcon#wrote, iclass 40, count 0 2006.281.07:20:19.53#ibcon#about to read 3, iclass 40, count 0 2006.281.07:20:19.55#ibcon#read 3, iclass 40, count 0 2006.281.07:20:19.55#ibcon#about to read 4, iclass 40, count 0 2006.281.07:20:19.55#ibcon#read 4, iclass 40, count 0 2006.281.07:20:19.55#ibcon#about to read 5, iclass 40, count 0 2006.281.07:20:19.55#ibcon#read 5, iclass 40, count 0 2006.281.07:20:19.55#ibcon#about to read 6, iclass 40, count 0 2006.281.07:20:19.55#ibcon#read 6, iclass 40, count 0 2006.281.07:20:19.55#ibcon#end of sib2, iclass 40, count 0 2006.281.07:20:19.55#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:20:19.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:20:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:20:19.57#ibcon#*before write, iclass 40, count 0 2006.281.07:20:19.57#ibcon#enter sib2, iclass 40, count 0 2006.281.07:20:19.57#ibcon#flushed, iclass 40, count 0 2006.281.07:20:19.57#ibcon#about to write, iclass 40, count 0 2006.281.07:20:19.57#ibcon#wrote, iclass 40, count 0 2006.281.07:20:19.57#ibcon#about to read 3, iclass 40, count 0 2006.281.07:20:19.61#ibcon#read 3, iclass 40, count 0 2006.281.07:20:19.61#ibcon#about to read 4, iclass 40, count 0 2006.281.07:20:19.61#ibcon#read 4, iclass 40, count 0 2006.281.07:20:19.61#ibcon#about to read 5, iclass 40, count 0 2006.281.07:20:19.61#ibcon#read 5, iclass 40, count 0 2006.281.07:20:19.61#ibcon#about to read 6, iclass 40, count 0 2006.281.07:20:19.61#ibcon#read 6, iclass 40, count 0 2006.281.07:20:19.61#ibcon#end of sib2, iclass 40, count 0 2006.281.07:20:19.61#ibcon#*after write, iclass 40, count 0 2006.281.07:20:19.61#ibcon#*before return 0, iclass 40, count 0 2006.281.07:20:19.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:19.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:19.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:20:19.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:20:19.61$vc4f8/va=6,6 2006.281.07:20:19.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:20:19.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:20:19.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:19.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:19.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:19.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:19.65#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:20:19.65#ibcon#first serial, iclass 4, count 2 2006.281.07:20:19.65#ibcon#enter sib2, iclass 4, count 2 2006.281.07:20:19.65#ibcon#flushed, iclass 4, count 2 2006.281.07:20:19.65#ibcon#about to write, iclass 4, count 2 2006.281.07:20:19.65#ibcon#wrote, iclass 4, count 2 2006.281.07:20:19.65#ibcon#about to read 3, iclass 4, count 2 2006.281.07:20:19.67#ibcon#read 3, iclass 4, count 2 2006.281.07:20:19.67#ibcon#about to read 4, iclass 4, count 2 2006.281.07:20:19.67#ibcon#read 4, iclass 4, count 2 2006.281.07:20:19.67#ibcon#about to read 5, iclass 4, count 2 2006.281.07:20:19.67#ibcon#read 5, iclass 4, count 2 2006.281.07:20:19.67#ibcon#about to read 6, iclass 4, count 2 2006.281.07:20:19.67#ibcon#read 6, iclass 4, count 2 2006.281.07:20:19.67#ibcon#end of sib2, iclass 4, count 2 2006.281.07:20:19.67#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:20:19.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:20:19.67#ibcon#[25=AT06-06\r\n] 2006.281.07:20:19.67#ibcon#*before write, iclass 4, count 2 2006.281.07:20:19.67#ibcon#enter sib2, iclass 4, count 2 2006.281.07:20:19.67#ibcon#flushed, iclass 4, count 2 2006.281.07:20:19.67#ibcon#about to write, iclass 4, count 2 2006.281.07:20:19.67#ibcon#wrote, iclass 4, count 2 2006.281.07:20:19.67#ibcon#about to read 3, iclass 4, count 2 2006.281.07:20:19.70#ibcon#read 3, iclass 4, count 2 2006.281.07:20:19.70#ibcon#about to read 4, iclass 4, count 2 2006.281.07:20:19.70#ibcon#read 4, iclass 4, count 2 2006.281.07:20:19.70#ibcon#about to read 5, iclass 4, count 2 2006.281.07:20:19.70#ibcon#read 5, iclass 4, count 2 2006.281.07:20:19.70#ibcon#about to read 6, iclass 4, count 2 2006.281.07:20:19.70#ibcon#read 6, iclass 4, count 2 2006.281.07:20:19.70#ibcon#end of sib2, iclass 4, count 2 2006.281.07:20:19.70#ibcon#*after write, iclass 4, count 2 2006.281.07:20:19.70#ibcon#*before return 0, iclass 4, count 2 2006.281.07:20:19.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:19.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:19.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:20:19.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:19.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:20:19.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:20:19.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:20:19.82#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:20:19.82#ibcon#first serial, iclass 4, count 0 2006.281.07:20:19.82#ibcon#enter sib2, iclass 4, count 0 2006.281.07:20:19.82#ibcon#flushed, iclass 4, count 0 2006.281.07:20:19.82#ibcon#about to write, iclass 4, count 0 2006.281.07:20:19.82#ibcon#wrote, iclass 4, count 0 2006.281.07:20:19.82#ibcon#about to read 3, iclass 4, count 0 2006.281.07:20:19.84#ibcon#read 3, iclass 4, count 0 2006.281.07:20:19.84#ibcon#about to read 4, iclass 4, count 0 2006.281.07:20:19.84#ibcon#read 4, iclass 4, count 0 2006.281.07:20:19.84#ibcon#about to read 5, iclass 4, count 0 2006.281.07:20:19.84#ibcon#read 5, iclass 4, count 0 2006.281.07:20:19.84#ibcon#about to read 6, iclass 4, count 0 2006.281.07:20:19.84#ibcon#read 6, iclass 4, count 0 2006.281.07:20:19.84#ibcon#end of sib2, iclass 4, count 0 2006.281.07:20:19.84#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:20:19.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:20:19.84#ibcon#[25=USB\r\n] 2006.281.07:20:19.84#ibcon#*before write, iclass 4, count 0 2006.281.07:20:19.84#ibcon#enter sib2, iclass 4, count 0 2006.281.07:20:19.84#ibcon#flushed, iclass 4, count 0 2006.281.07:20:19.84#ibcon#about to write, iclass 4, count 0 2006.281.07:20:19.84#ibcon#wrote, iclass 4, count 0 2006.281.07:20:19.84#ibcon#about to read 3, iclass 4, count 0 2006.281.07:20:19.87#ibcon#read 3, iclass 4, count 0 2006.281.07:20:19.87#ibcon#about to read 4, iclass 4, count 0 2006.281.07:20:19.87#ibcon#read 4, iclass 4, count 0 2006.281.07:20:19.87#ibcon#about to read 5, iclass 4, count 0 2006.281.07:20:19.87#ibcon#read 5, iclass 4, count 0 2006.281.07:20:19.87#ibcon#about to read 6, iclass 4, count 0 2006.281.07:20:19.87#ibcon#read 6, iclass 4, count 0 2006.281.07:20:19.87#ibcon#end of sib2, iclass 4, count 0 2006.281.07:20:19.87#ibcon#*after write, iclass 4, count 0 2006.281.07:20:19.87#ibcon#*before return 0, iclass 4, count 0 2006.281.07:20:19.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:20:19.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:20:19.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:20:19.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:20:19.87$vc4f8/valo=7,832.99 2006.281.07:20:19.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:20:19.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:20:19.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:19.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:20:19.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:20:19.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:20:19.87#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:20:19.87#ibcon#first serial, iclass 6, count 0 2006.281.07:20:19.87#ibcon#enter sib2, iclass 6, count 0 2006.281.07:20:19.87#ibcon#flushed, iclass 6, count 0 2006.281.07:20:19.87#ibcon#about to write, iclass 6, count 0 2006.281.07:20:19.87#ibcon#wrote, iclass 6, count 0 2006.281.07:20:19.87#ibcon#about to read 3, iclass 6, count 0 2006.281.07:20:19.89#ibcon#read 3, iclass 6, count 0 2006.281.07:20:19.89#ibcon#about to read 4, iclass 6, count 0 2006.281.07:20:19.89#ibcon#read 4, iclass 6, count 0 2006.281.07:20:19.89#ibcon#about to read 5, iclass 6, count 0 2006.281.07:20:19.89#ibcon#read 5, iclass 6, count 0 2006.281.07:20:19.89#ibcon#about to read 6, iclass 6, count 0 2006.281.07:20:19.89#ibcon#read 6, iclass 6, count 0 2006.281.07:20:19.89#ibcon#end of sib2, iclass 6, count 0 2006.281.07:20:19.89#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:20:19.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:20:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:20:19.89#ibcon#*before write, iclass 6, count 0 2006.281.07:20:19.89#ibcon#enter sib2, iclass 6, count 0 2006.281.07:20:19.89#ibcon#flushed, iclass 6, count 0 2006.281.07:20:19.89#ibcon#about to write, iclass 6, count 0 2006.281.07:20:19.89#ibcon#wrote, iclass 6, count 0 2006.281.07:20:19.89#ibcon#about to read 3, iclass 6, count 0 2006.281.07:20:19.93#ibcon#read 3, iclass 6, count 0 2006.281.07:20:19.93#ibcon#about to read 4, iclass 6, count 0 2006.281.07:20:19.93#ibcon#read 4, iclass 6, count 0 2006.281.07:20:19.93#ibcon#about to read 5, iclass 6, count 0 2006.281.07:20:19.93#ibcon#read 5, iclass 6, count 0 2006.281.07:20:19.93#ibcon#about to read 6, iclass 6, count 0 2006.281.07:20:19.93#ibcon#read 6, iclass 6, count 0 2006.281.07:20:19.93#ibcon#end of sib2, iclass 6, count 0 2006.281.07:20:19.93#ibcon#*after write, iclass 6, count 0 2006.281.07:20:19.93#ibcon#*before return 0, iclass 6, count 0 2006.281.07:20:19.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:20:19.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:20:19.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:20:19.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:20:19.93$vc4f8/va=7,6 2006.281.07:20:19.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.07:20:19.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.07:20:19.93#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:19.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:20:19.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:20:19.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:20:19.99#ibcon#enter wrdev, iclass 10, count 2 2006.281.07:20:19.99#ibcon#first serial, iclass 10, count 2 2006.281.07:20:19.99#ibcon#enter sib2, iclass 10, count 2 2006.281.07:20:19.99#ibcon#flushed, iclass 10, count 2 2006.281.07:20:19.99#ibcon#about to write, iclass 10, count 2 2006.281.07:20:19.99#ibcon#wrote, iclass 10, count 2 2006.281.07:20:19.99#ibcon#about to read 3, iclass 10, count 2 2006.281.07:20:20.01#ibcon#read 3, iclass 10, count 2 2006.281.07:20:20.01#ibcon#about to read 4, iclass 10, count 2 2006.281.07:20:20.01#ibcon#read 4, iclass 10, count 2 2006.281.07:20:20.01#ibcon#about to read 5, iclass 10, count 2 2006.281.07:20:20.01#ibcon#read 5, iclass 10, count 2 2006.281.07:20:20.01#ibcon#about to read 6, iclass 10, count 2 2006.281.07:20:20.01#ibcon#read 6, iclass 10, count 2 2006.281.07:20:20.01#ibcon#end of sib2, iclass 10, count 2 2006.281.07:20:20.01#ibcon#*mode == 0, iclass 10, count 2 2006.281.07:20:20.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.07:20:20.01#ibcon#[25=AT07-06\r\n] 2006.281.07:20:20.01#ibcon#*before write, iclass 10, count 2 2006.281.07:20:20.01#ibcon#enter sib2, iclass 10, count 2 2006.281.07:20:20.01#ibcon#flushed, iclass 10, count 2 2006.281.07:20:20.01#ibcon#about to write, iclass 10, count 2 2006.281.07:20:20.01#ibcon#wrote, iclass 10, count 2 2006.281.07:20:20.01#ibcon#about to read 3, iclass 10, count 2 2006.281.07:20:20.04#ibcon#read 3, iclass 10, count 2 2006.281.07:20:20.04#ibcon#about to read 4, iclass 10, count 2 2006.281.07:20:20.04#ibcon#read 4, iclass 10, count 2 2006.281.07:20:20.04#ibcon#about to read 5, iclass 10, count 2 2006.281.07:20:20.04#ibcon#read 5, iclass 10, count 2 2006.281.07:20:20.04#ibcon#about to read 6, iclass 10, count 2 2006.281.07:20:20.04#ibcon#read 6, iclass 10, count 2 2006.281.07:20:20.04#ibcon#end of sib2, iclass 10, count 2 2006.281.07:20:20.04#ibcon#*after write, iclass 10, count 2 2006.281.07:20:20.04#ibcon#*before return 0, iclass 10, count 2 2006.281.07:20:20.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:20:20.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:20:20.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.07:20:20.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:20.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:20:20.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:20:20.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:20:20.16#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:20:20.16#ibcon#first serial, iclass 10, count 0 2006.281.07:20:20.16#ibcon#enter sib2, iclass 10, count 0 2006.281.07:20:20.16#ibcon#flushed, iclass 10, count 0 2006.281.07:20:20.16#ibcon#about to write, iclass 10, count 0 2006.281.07:20:20.16#ibcon#wrote, iclass 10, count 0 2006.281.07:20:20.16#ibcon#about to read 3, iclass 10, count 0 2006.281.07:20:20.18#ibcon#read 3, iclass 10, count 0 2006.281.07:20:20.18#ibcon#about to read 4, iclass 10, count 0 2006.281.07:20:20.18#ibcon#read 4, iclass 10, count 0 2006.281.07:20:20.18#ibcon#about to read 5, iclass 10, count 0 2006.281.07:20:20.18#ibcon#read 5, iclass 10, count 0 2006.281.07:20:20.18#ibcon#about to read 6, iclass 10, count 0 2006.281.07:20:20.18#ibcon#read 6, iclass 10, count 0 2006.281.07:20:20.18#ibcon#end of sib2, iclass 10, count 0 2006.281.07:20:20.18#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:20:20.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:20:20.18#ibcon#[25=USB\r\n] 2006.281.07:20:20.18#ibcon#*before write, iclass 10, count 0 2006.281.07:20:20.18#ibcon#enter sib2, iclass 10, count 0 2006.281.07:20:20.18#ibcon#flushed, iclass 10, count 0 2006.281.07:20:20.18#ibcon#about to write, iclass 10, count 0 2006.281.07:20:20.18#ibcon#wrote, iclass 10, count 0 2006.281.07:20:20.18#ibcon#about to read 3, iclass 10, count 0 2006.281.07:20:20.21#ibcon#read 3, iclass 10, count 0 2006.281.07:20:20.21#ibcon#about to read 4, iclass 10, count 0 2006.281.07:20:20.21#ibcon#read 4, iclass 10, count 0 2006.281.07:20:20.21#ibcon#about to read 5, iclass 10, count 0 2006.281.07:20:20.21#ibcon#read 5, iclass 10, count 0 2006.281.07:20:20.21#ibcon#about to read 6, iclass 10, count 0 2006.281.07:20:20.21#ibcon#read 6, iclass 10, count 0 2006.281.07:20:20.21#ibcon#end of sib2, iclass 10, count 0 2006.281.07:20:20.21#ibcon#*after write, iclass 10, count 0 2006.281.07:20:20.21#ibcon#*before return 0, iclass 10, count 0 2006.281.07:20:20.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:20:20.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:20:20.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:20:20.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:20:20.21$vc4f8/valo=8,852.99 2006.281.07:20:20.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.07:20:20.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.07:20:20.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:20.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:20:20.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:20:20.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:20:20.21#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:20:20.21#ibcon#first serial, iclass 12, count 0 2006.281.07:20:20.21#ibcon#enter sib2, iclass 12, count 0 2006.281.07:20:20.21#ibcon#flushed, iclass 12, count 0 2006.281.07:20:20.21#ibcon#about to write, iclass 12, count 0 2006.281.07:20:20.21#ibcon#wrote, iclass 12, count 0 2006.281.07:20:20.21#ibcon#about to read 3, iclass 12, count 0 2006.281.07:20:20.23#ibcon#read 3, iclass 12, count 0 2006.281.07:20:20.23#ibcon#about to read 4, iclass 12, count 0 2006.281.07:20:20.23#ibcon#read 4, iclass 12, count 0 2006.281.07:20:20.23#ibcon#about to read 5, iclass 12, count 0 2006.281.07:20:20.23#ibcon#read 5, iclass 12, count 0 2006.281.07:20:20.23#ibcon#about to read 6, iclass 12, count 0 2006.281.07:20:20.23#ibcon#read 6, iclass 12, count 0 2006.281.07:20:20.23#ibcon#end of sib2, iclass 12, count 0 2006.281.07:20:20.23#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:20:20.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:20:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:20:20.23#ibcon#*before write, iclass 12, count 0 2006.281.07:20:20.23#ibcon#enter sib2, iclass 12, count 0 2006.281.07:20:20.23#ibcon#flushed, iclass 12, count 0 2006.281.07:20:20.23#ibcon#about to write, iclass 12, count 0 2006.281.07:20:20.23#ibcon#wrote, iclass 12, count 0 2006.281.07:20:20.23#ibcon#about to read 3, iclass 12, count 0 2006.281.07:20:20.27#ibcon#read 3, iclass 12, count 0 2006.281.07:20:20.27#ibcon#about to read 4, iclass 12, count 0 2006.281.07:20:20.27#ibcon#read 4, iclass 12, count 0 2006.281.07:20:20.27#ibcon#about to read 5, iclass 12, count 0 2006.281.07:20:20.27#ibcon#read 5, iclass 12, count 0 2006.281.07:20:20.27#ibcon#about to read 6, iclass 12, count 0 2006.281.07:20:20.27#ibcon#read 6, iclass 12, count 0 2006.281.07:20:20.27#ibcon#end of sib2, iclass 12, count 0 2006.281.07:20:20.27#ibcon#*after write, iclass 12, count 0 2006.281.07:20:20.27#ibcon#*before return 0, iclass 12, count 0 2006.281.07:20:20.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:20:20.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:20:20.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:20:20.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:20:20.27$vc4f8/va=8,6 2006.281.07:20:20.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.07:20:20.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.07:20:20.28#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:20.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:20:20.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:20:20.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:20:20.33#ibcon#enter wrdev, iclass 14, count 2 2006.281.07:20:20.33#ibcon#first serial, iclass 14, count 2 2006.281.07:20:20.33#ibcon#enter sib2, iclass 14, count 2 2006.281.07:20:20.33#ibcon#flushed, iclass 14, count 2 2006.281.07:20:20.33#ibcon#about to write, iclass 14, count 2 2006.281.07:20:20.33#ibcon#wrote, iclass 14, count 2 2006.281.07:20:20.33#ibcon#about to read 3, iclass 14, count 2 2006.281.07:20:20.35#ibcon#read 3, iclass 14, count 2 2006.281.07:20:20.35#ibcon#about to read 4, iclass 14, count 2 2006.281.07:20:20.35#ibcon#read 4, iclass 14, count 2 2006.281.07:20:20.35#ibcon#about to read 5, iclass 14, count 2 2006.281.07:20:20.35#ibcon#read 5, iclass 14, count 2 2006.281.07:20:20.35#ibcon#about to read 6, iclass 14, count 2 2006.281.07:20:20.35#ibcon#read 6, iclass 14, count 2 2006.281.07:20:20.35#ibcon#end of sib2, iclass 14, count 2 2006.281.07:20:20.35#ibcon#*mode == 0, iclass 14, count 2 2006.281.07:20:20.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.07:20:20.35#ibcon#[25=AT08-06\r\n] 2006.281.07:20:20.35#ibcon#*before write, iclass 14, count 2 2006.281.07:20:20.35#ibcon#enter sib2, iclass 14, count 2 2006.281.07:20:20.35#ibcon#flushed, iclass 14, count 2 2006.281.07:20:20.35#ibcon#about to write, iclass 14, count 2 2006.281.07:20:20.35#ibcon#wrote, iclass 14, count 2 2006.281.07:20:20.35#ibcon#about to read 3, iclass 14, count 2 2006.281.07:20:20.38#ibcon#read 3, iclass 14, count 2 2006.281.07:20:20.38#ibcon#about to read 4, iclass 14, count 2 2006.281.07:20:20.38#ibcon#read 4, iclass 14, count 2 2006.281.07:20:20.38#ibcon#about to read 5, iclass 14, count 2 2006.281.07:20:20.38#ibcon#read 5, iclass 14, count 2 2006.281.07:20:20.38#ibcon#about to read 6, iclass 14, count 2 2006.281.07:20:20.38#ibcon#read 6, iclass 14, count 2 2006.281.07:20:20.38#ibcon#end of sib2, iclass 14, count 2 2006.281.07:20:20.38#ibcon#*after write, iclass 14, count 2 2006.281.07:20:20.38#ibcon#*before return 0, iclass 14, count 2 2006.281.07:20:20.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:20:20.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:20:20.38#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.07:20:20.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:20.38#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:20:20.50#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:20:20.50#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:20:20.50#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:20:20.50#ibcon#first serial, iclass 14, count 0 2006.281.07:20:20.50#ibcon#enter sib2, iclass 14, count 0 2006.281.07:20:20.50#ibcon#flushed, iclass 14, count 0 2006.281.07:20:20.50#ibcon#about to write, iclass 14, count 0 2006.281.07:20:20.50#ibcon#wrote, iclass 14, count 0 2006.281.07:20:20.50#ibcon#about to read 3, iclass 14, count 0 2006.281.07:20:20.52#ibcon#read 3, iclass 14, count 0 2006.281.07:20:20.52#ibcon#about to read 4, iclass 14, count 0 2006.281.07:20:20.52#ibcon#read 4, iclass 14, count 0 2006.281.07:20:20.52#ibcon#about to read 5, iclass 14, count 0 2006.281.07:20:20.52#ibcon#read 5, iclass 14, count 0 2006.281.07:20:20.52#ibcon#about to read 6, iclass 14, count 0 2006.281.07:20:20.52#ibcon#read 6, iclass 14, count 0 2006.281.07:20:20.52#ibcon#end of sib2, iclass 14, count 0 2006.281.07:20:20.52#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:20:20.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:20:20.52#ibcon#[25=USB\r\n] 2006.281.07:20:20.52#ibcon#*before write, iclass 14, count 0 2006.281.07:20:20.52#ibcon#enter sib2, iclass 14, count 0 2006.281.07:20:20.52#ibcon#flushed, iclass 14, count 0 2006.281.07:20:20.52#ibcon#about to write, iclass 14, count 0 2006.281.07:20:20.52#ibcon#wrote, iclass 14, count 0 2006.281.07:20:20.52#ibcon#about to read 3, iclass 14, count 0 2006.281.07:20:20.55#ibcon#read 3, iclass 14, count 0 2006.281.07:20:20.55#ibcon#about to read 4, iclass 14, count 0 2006.281.07:20:20.55#ibcon#read 4, iclass 14, count 0 2006.281.07:20:20.55#ibcon#about to read 5, iclass 14, count 0 2006.281.07:20:20.55#ibcon#read 5, iclass 14, count 0 2006.281.07:20:20.55#ibcon#about to read 6, iclass 14, count 0 2006.281.07:20:20.55#ibcon#read 6, iclass 14, count 0 2006.281.07:20:20.55#ibcon#end of sib2, iclass 14, count 0 2006.281.07:20:20.55#ibcon#*after write, iclass 14, count 0 2006.281.07:20:20.56#ibcon#*before return 0, iclass 14, count 0 2006.281.07:20:20.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:20:20.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:20:20.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:20:20.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:20:20.56$vc4f8/vblo=1,632.99 2006.281.07:20:20.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:20:20.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:20:20.56#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:20.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:20:20.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:20:20.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:20:20.56#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:20:20.56#ibcon#first serial, iclass 16, count 0 2006.281.07:20:20.56#ibcon#enter sib2, iclass 16, count 0 2006.281.07:20:20.56#ibcon#flushed, iclass 16, count 0 2006.281.07:20:20.56#ibcon#about to write, iclass 16, count 0 2006.281.07:20:20.56#ibcon#wrote, iclass 16, count 0 2006.281.07:20:20.56#ibcon#about to read 3, iclass 16, count 0 2006.281.07:20:20.57#ibcon#read 3, iclass 16, count 0 2006.281.07:20:20.57#ibcon#about to read 4, iclass 16, count 0 2006.281.07:20:20.57#ibcon#read 4, iclass 16, count 0 2006.281.07:20:20.57#ibcon#about to read 5, iclass 16, count 0 2006.281.07:20:20.57#ibcon#read 5, iclass 16, count 0 2006.281.07:20:20.57#ibcon#about to read 6, iclass 16, count 0 2006.281.07:20:20.58#ibcon#read 6, iclass 16, count 0 2006.281.07:20:20.58#ibcon#end of sib2, iclass 16, count 0 2006.281.07:20:20.58#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:20:20.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:20:20.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:20:20.58#ibcon#*before write, iclass 16, count 0 2006.281.07:20:20.58#ibcon#enter sib2, iclass 16, count 0 2006.281.07:20:20.58#ibcon#flushed, iclass 16, count 0 2006.281.07:20:20.58#ibcon#about to write, iclass 16, count 0 2006.281.07:20:20.58#ibcon#wrote, iclass 16, count 0 2006.281.07:20:20.58#ibcon#about to read 3, iclass 16, count 0 2006.281.07:20:20.62#ibcon#read 3, iclass 16, count 0 2006.281.07:20:20.62#ibcon#about to read 4, iclass 16, count 0 2006.281.07:20:20.62#ibcon#read 4, iclass 16, count 0 2006.281.07:20:20.62#ibcon#about to read 5, iclass 16, count 0 2006.281.07:20:20.62#ibcon#read 5, iclass 16, count 0 2006.281.07:20:20.62#ibcon#about to read 6, iclass 16, count 0 2006.281.07:20:20.62#ibcon#read 6, iclass 16, count 0 2006.281.07:20:20.62#ibcon#end of sib2, iclass 16, count 0 2006.281.07:20:20.62#ibcon#*after write, iclass 16, count 0 2006.281.07:20:20.62#ibcon#*before return 0, iclass 16, count 0 2006.281.07:20:20.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:20:20.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:20:20.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:20:20.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:20:20.62$vc4f8/vb=1,4 2006.281.07:20:20.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.07:20:20.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.07:20:20.62#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:20.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:20:20.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:20:20.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:20:20.62#ibcon#enter wrdev, iclass 18, count 2 2006.281.07:20:20.62#ibcon#first serial, iclass 18, count 2 2006.281.07:20:20.62#ibcon#enter sib2, iclass 18, count 2 2006.281.07:20:20.62#ibcon#flushed, iclass 18, count 2 2006.281.07:20:20.62#ibcon#about to write, iclass 18, count 2 2006.281.07:20:20.62#ibcon#wrote, iclass 18, count 2 2006.281.07:20:20.62#ibcon#about to read 3, iclass 18, count 2 2006.281.07:20:20.64#ibcon#read 3, iclass 18, count 2 2006.281.07:20:20.64#ibcon#about to read 4, iclass 18, count 2 2006.281.07:20:20.64#ibcon#read 4, iclass 18, count 2 2006.281.07:20:20.64#ibcon#about to read 5, iclass 18, count 2 2006.281.07:20:20.64#ibcon#read 5, iclass 18, count 2 2006.281.07:20:20.64#ibcon#about to read 6, iclass 18, count 2 2006.281.07:20:20.64#ibcon#read 6, iclass 18, count 2 2006.281.07:20:20.64#ibcon#end of sib2, iclass 18, count 2 2006.281.07:20:20.64#ibcon#*mode == 0, iclass 18, count 2 2006.281.07:20:20.64#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.07:20:20.64#ibcon#[27=AT01-04\r\n] 2006.281.07:20:20.64#ibcon#*before write, iclass 18, count 2 2006.281.07:20:20.64#ibcon#enter sib2, iclass 18, count 2 2006.281.07:20:20.64#ibcon#flushed, iclass 18, count 2 2006.281.07:20:20.64#ibcon#about to write, iclass 18, count 2 2006.281.07:20:20.64#ibcon#wrote, iclass 18, count 2 2006.281.07:20:20.64#ibcon#about to read 3, iclass 18, count 2 2006.281.07:20:20.67#ibcon#read 3, iclass 18, count 2 2006.281.07:20:20.67#ibcon#about to read 4, iclass 18, count 2 2006.281.07:20:20.67#ibcon#read 4, iclass 18, count 2 2006.281.07:20:20.67#ibcon#about to read 5, iclass 18, count 2 2006.281.07:20:20.67#ibcon#read 5, iclass 18, count 2 2006.281.07:20:20.67#ibcon#about to read 6, iclass 18, count 2 2006.281.07:20:20.67#ibcon#read 6, iclass 18, count 2 2006.281.07:20:20.67#ibcon#end of sib2, iclass 18, count 2 2006.281.07:20:20.67#ibcon#*after write, iclass 18, count 2 2006.281.07:20:20.67#ibcon#*before return 0, iclass 18, count 2 2006.281.07:20:20.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:20:20.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:20:20.67#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.07:20:20.67#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:20.67#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:20:20.79#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:20:20.79#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:20:20.79#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:20:20.79#ibcon#first serial, iclass 18, count 0 2006.281.07:20:20.79#ibcon#enter sib2, iclass 18, count 0 2006.281.07:20:20.79#ibcon#flushed, iclass 18, count 0 2006.281.07:20:20.79#ibcon#about to write, iclass 18, count 0 2006.281.07:20:20.79#ibcon#wrote, iclass 18, count 0 2006.281.07:20:20.79#ibcon#about to read 3, iclass 18, count 0 2006.281.07:20:20.81#ibcon#read 3, iclass 18, count 0 2006.281.07:20:20.81#ibcon#about to read 4, iclass 18, count 0 2006.281.07:20:20.81#ibcon#read 4, iclass 18, count 0 2006.281.07:20:20.81#ibcon#about to read 5, iclass 18, count 0 2006.281.07:20:20.81#ibcon#read 5, iclass 18, count 0 2006.281.07:20:20.81#ibcon#about to read 6, iclass 18, count 0 2006.281.07:20:20.81#ibcon#read 6, iclass 18, count 0 2006.281.07:20:20.81#ibcon#end of sib2, iclass 18, count 0 2006.281.07:20:20.81#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:20:20.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:20:20.81#ibcon#[27=USB\r\n] 2006.281.07:20:20.81#ibcon#*before write, iclass 18, count 0 2006.281.07:20:20.81#ibcon#enter sib2, iclass 18, count 0 2006.281.07:20:20.81#ibcon#flushed, iclass 18, count 0 2006.281.07:20:20.81#ibcon#about to write, iclass 18, count 0 2006.281.07:20:20.81#ibcon#wrote, iclass 18, count 0 2006.281.07:20:20.81#ibcon#about to read 3, iclass 18, count 0 2006.281.07:20:20.85#ibcon#read 3, iclass 18, count 0 2006.281.07:20:20.85#ibcon#about to read 4, iclass 18, count 0 2006.281.07:20:20.85#ibcon#read 4, iclass 18, count 0 2006.281.07:20:20.85#ibcon#about to read 5, iclass 18, count 0 2006.281.07:20:20.85#ibcon#read 5, iclass 18, count 0 2006.281.07:20:20.85#ibcon#about to read 6, iclass 18, count 0 2006.281.07:20:20.85#ibcon#read 6, iclass 18, count 0 2006.281.07:20:20.85#ibcon#end of sib2, iclass 18, count 0 2006.281.07:20:20.85#ibcon#*after write, iclass 18, count 0 2006.281.07:20:20.85#ibcon#*before return 0, iclass 18, count 0 2006.281.07:20:20.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:20:20.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:20:20.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:20:20.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:20:20.85$vc4f8/vblo=2,640.99 2006.281.07:20:20.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:20:20.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:20:20.85#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:20.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:20.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:20.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:20.85#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:20:20.85#ibcon#first serial, iclass 20, count 0 2006.281.07:20:20.85#ibcon#enter sib2, iclass 20, count 0 2006.281.07:20:20.85#ibcon#flushed, iclass 20, count 0 2006.281.07:20:20.85#ibcon#about to write, iclass 20, count 0 2006.281.07:20:20.85#ibcon#wrote, iclass 20, count 0 2006.281.07:20:20.85#ibcon#about to read 3, iclass 20, count 0 2006.281.07:20:20.86#ibcon#read 3, iclass 20, count 0 2006.281.07:20:20.86#ibcon#about to read 4, iclass 20, count 0 2006.281.07:20:20.86#ibcon#read 4, iclass 20, count 0 2006.281.07:20:20.86#ibcon#about to read 5, iclass 20, count 0 2006.281.07:20:20.86#ibcon#read 5, iclass 20, count 0 2006.281.07:20:20.86#ibcon#about to read 6, iclass 20, count 0 2006.281.07:20:20.86#ibcon#read 6, iclass 20, count 0 2006.281.07:20:20.86#ibcon#end of sib2, iclass 20, count 0 2006.281.07:20:20.86#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:20:20.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:20:20.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:20:20.86#ibcon#*before write, iclass 20, count 0 2006.281.07:20:20.86#ibcon#enter sib2, iclass 20, count 0 2006.281.07:20:20.86#ibcon#flushed, iclass 20, count 0 2006.281.07:20:20.86#ibcon#about to write, iclass 20, count 0 2006.281.07:20:20.86#ibcon#wrote, iclass 20, count 0 2006.281.07:20:20.86#ibcon#about to read 3, iclass 20, count 0 2006.281.07:20:20.90#ibcon#read 3, iclass 20, count 0 2006.281.07:20:20.90#ibcon#about to read 4, iclass 20, count 0 2006.281.07:20:20.90#ibcon#read 4, iclass 20, count 0 2006.281.07:20:20.90#ibcon#about to read 5, iclass 20, count 0 2006.281.07:20:20.90#ibcon#read 5, iclass 20, count 0 2006.281.07:20:20.90#ibcon#about to read 6, iclass 20, count 0 2006.281.07:20:20.90#ibcon#read 6, iclass 20, count 0 2006.281.07:20:20.90#ibcon#end of sib2, iclass 20, count 0 2006.281.07:20:20.90#ibcon#*after write, iclass 20, count 0 2006.281.07:20:20.90#ibcon#*before return 0, iclass 20, count 0 2006.281.07:20:20.90#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:20.90#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:20:20.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:20:20.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:20:20.90$vc4f8/vb=2,5 2006.281.07:20:20.90#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:20:20.90#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:20:20.90#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:20.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:20.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:20.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:20.97#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:20:20.97#ibcon#first serial, iclass 22, count 2 2006.281.07:20:20.97#ibcon#enter sib2, iclass 22, count 2 2006.281.07:20:20.97#ibcon#flushed, iclass 22, count 2 2006.281.07:20:20.97#ibcon#about to write, iclass 22, count 2 2006.281.07:20:20.97#ibcon#wrote, iclass 22, count 2 2006.281.07:20:20.97#ibcon#about to read 3, iclass 22, count 2 2006.281.07:20:20.99#ibcon#read 3, iclass 22, count 2 2006.281.07:20:20.99#ibcon#about to read 4, iclass 22, count 2 2006.281.07:20:20.99#ibcon#read 4, iclass 22, count 2 2006.281.07:20:20.99#ibcon#about to read 5, iclass 22, count 2 2006.281.07:20:20.99#ibcon#read 5, iclass 22, count 2 2006.281.07:20:20.99#ibcon#about to read 6, iclass 22, count 2 2006.281.07:20:20.99#ibcon#read 6, iclass 22, count 2 2006.281.07:20:20.99#ibcon#end of sib2, iclass 22, count 2 2006.281.07:20:20.99#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:20:20.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:20:20.99#ibcon#[27=AT02-05\r\n] 2006.281.07:20:20.99#ibcon#*before write, iclass 22, count 2 2006.281.07:20:20.99#ibcon#enter sib2, iclass 22, count 2 2006.281.07:20:20.99#ibcon#flushed, iclass 22, count 2 2006.281.07:20:20.99#ibcon#about to write, iclass 22, count 2 2006.281.07:20:20.99#ibcon#wrote, iclass 22, count 2 2006.281.07:20:20.99#ibcon#about to read 3, iclass 22, count 2 2006.281.07:20:21.02#ibcon#read 3, iclass 22, count 2 2006.281.07:20:21.02#ibcon#about to read 4, iclass 22, count 2 2006.281.07:20:21.02#ibcon#read 4, iclass 22, count 2 2006.281.07:20:21.02#ibcon#about to read 5, iclass 22, count 2 2006.281.07:20:21.02#ibcon#read 5, iclass 22, count 2 2006.281.07:20:21.02#ibcon#about to read 6, iclass 22, count 2 2006.281.07:20:21.02#ibcon#read 6, iclass 22, count 2 2006.281.07:20:21.02#ibcon#end of sib2, iclass 22, count 2 2006.281.07:20:21.02#ibcon#*after write, iclass 22, count 2 2006.281.07:20:21.02#ibcon#*before return 0, iclass 22, count 2 2006.281.07:20:21.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:21.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:20:21.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:20:21.02#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:21.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:21.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:21.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:21.14#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:20:21.14#ibcon#first serial, iclass 22, count 0 2006.281.07:20:21.14#ibcon#enter sib2, iclass 22, count 0 2006.281.07:20:21.14#ibcon#flushed, iclass 22, count 0 2006.281.07:20:21.14#ibcon#about to write, iclass 22, count 0 2006.281.07:20:21.14#ibcon#wrote, iclass 22, count 0 2006.281.07:20:21.14#ibcon#about to read 3, iclass 22, count 0 2006.281.07:20:21.16#ibcon#read 3, iclass 22, count 0 2006.281.07:20:21.16#ibcon#about to read 4, iclass 22, count 0 2006.281.07:20:21.16#ibcon#read 4, iclass 22, count 0 2006.281.07:20:21.16#ibcon#about to read 5, iclass 22, count 0 2006.281.07:20:21.16#ibcon#read 5, iclass 22, count 0 2006.281.07:20:21.16#ibcon#about to read 6, iclass 22, count 0 2006.281.07:20:21.16#ibcon#read 6, iclass 22, count 0 2006.281.07:20:21.16#ibcon#end of sib2, iclass 22, count 0 2006.281.07:20:21.16#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:20:21.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:20:21.16#ibcon#[27=USB\r\n] 2006.281.07:20:21.16#ibcon#*before write, iclass 22, count 0 2006.281.07:20:21.16#ibcon#enter sib2, iclass 22, count 0 2006.281.07:20:21.16#ibcon#flushed, iclass 22, count 0 2006.281.07:20:21.16#ibcon#about to write, iclass 22, count 0 2006.281.07:20:21.16#ibcon#wrote, iclass 22, count 0 2006.281.07:20:21.16#ibcon#about to read 3, iclass 22, count 0 2006.281.07:20:21.19#ibcon#read 3, iclass 22, count 0 2006.281.07:20:21.19#ibcon#about to read 4, iclass 22, count 0 2006.281.07:20:21.19#ibcon#read 4, iclass 22, count 0 2006.281.07:20:21.19#ibcon#about to read 5, iclass 22, count 0 2006.281.07:20:21.19#ibcon#read 5, iclass 22, count 0 2006.281.07:20:21.19#ibcon#about to read 6, iclass 22, count 0 2006.281.07:20:21.19#ibcon#read 6, iclass 22, count 0 2006.281.07:20:21.19#ibcon#end of sib2, iclass 22, count 0 2006.281.07:20:21.19#ibcon#*after write, iclass 22, count 0 2006.281.07:20:21.19#ibcon#*before return 0, iclass 22, count 0 2006.281.07:20:21.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:21.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:20:21.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:20:21.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:20:21.19$vc4f8/vblo=3,656.99 2006.281.07:20:21.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:20:21.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:20:21.19#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:21.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:21.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:21.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:21.19#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:20:21.19#ibcon#first serial, iclass 24, count 0 2006.281.07:20:21.19#ibcon#enter sib2, iclass 24, count 0 2006.281.07:20:21.19#ibcon#flushed, iclass 24, count 0 2006.281.07:20:21.19#ibcon#about to write, iclass 24, count 0 2006.281.07:20:21.19#ibcon#wrote, iclass 24, count 0 2006.281.07:20:21.19#ibcon#about to read 3, iclass 24, count 0 2006.281.07:20:21.21#ibcon#read 3, iclass 24, count 0 2006.281.07:20:21.21#ibcon#about to read 4, iclass 24, count 0 2006.281.07:20:21.21#ibcon#read 4, iclass 24, count 0 2006.281.07:20:21.21#ibcon#about to read 5, iclass 24, count 0 2006.281.07:20:21.21#ibcon#read 5, iclass 24, count 0 2006.281.07:20:21.21#ibcon#about to read 6, iclass 24, count 0 2006.281.07:20:21.21#ibcon#read 6, iclass 24, count 0 2006.281.07:20:21.21#ibcon#end of sib2, iclass 24, count 0 2006.281.07:20:21.21#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:20:21.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:20:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:20:21.21#ibcon#*before write, iclass 24, count 0 2006.281.07:20:21.21#ibcon#enter sib2, iclass 24, count 0 2006.281.07:20:21.21#ibcon#flushed, iclass 24, count 0 2006.281.07:20:21.21#ibcon#about to write, iclass 24, count 0 2006.281.07:20:21.21#ibcon#wrote, iclass 24, count 0 2006.281.07:20:21.21#ibcon#about to read 3, iclass 24, count 0 2006.281.07:20:21.25#ibcon#read 3, iclass 24, count 0 2006.281.07:20:21.25#ibcon#about to read 4, iclass 24, count 0 2006.281.07:20:21.25#ibcon#read 4, iclass 24, count 0 2006.281.07:20:21.25#ibcon#about to read 5, iclass 24, count 0 2006.281.07:20:21.25#ibcon#read 5, iclass 24, count 0 2006.281.07:20:21.25#ibcon#about to read 6, iclass 24, count 0 2006.281.07:20:21.25#ibcon#read 6, iclass 24, count 0 2006.281.07:20:21.25#ibcon#end of sib2, iclass 24, count 0 2006.281.07:20:21.25#ibcon#*after write, iclass 24, count 0 2006.281.07:20:21.25#ibcon#*before return 0, iclass 24, count 0 2006.281.07:20:21.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:21.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:20:21.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:20:21.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:20:21.25$vc4f8/vb=3,4 2006.281.07:20:21.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:20:21.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:20:21.25#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:21.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:21.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:21.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:21.31#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:20:21.31#ibcon#first serial, iclass 26, count 2 2006.281.07:20:21.31#ibcon#enter sib2, iclass 26, count 2 2006.281.07:20:21.31#ibcon#flushed, iclass 26, count 2 2006.281.07:20:21.31#ibcon#about to write, iclass 26, count 2 2006.281.07:20:21.31#ibcon#wrote, iclass 26, count 2 2006.281.07:20:21.31#ibcon#about to read 3, iclass 26, count 2 2006.281.07:20:21.33#ibcon#read 3, iclass 26, count 2 2006.281.07:20:21.33#ibcon#about to read 4, iclass 26, count 2 2006.281.07:20:21.33#ibcon#read 4, iclass 26, count 2 2006.281.07:20:21.33#ibcon#about to read 5, iclass 26, count 2 2006.281.07:20:21.33#ibcon#read 5, iclass 26, count 2 2006.281.07:20:21.33#ibcon#about to read 6, iclass 26, count 2 2006.281.07:20:21.33#ibcon#read 6, iclass 26, count 2 2006.281.07:20:21.33#ibcon#end of sib2, iclass 26, count 2 2006.281.07:20:21.33#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:20:21.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:20:21.33#ibcon#[27=AT03-04\r\n] 2006.281.07:20:21.33#ibcon#*before write, iclass 26, count 2 2006.281.07:20:21.33#ibcon#enter sib2, iclass 26, count 2 2006.281.07:20:21.33#ibcon#flushed, iclass 26, count 2 2006.281.07:20:21.33#ibcon#about to write, iclass 26, count 2 2006.281.07:20:21.33#ibcon#wrote, iclass 26, count 2 2006.281.07:20:21.33#ibcon#about to read 3, iclass 26, count 2 2006.281.07:20:21.36#ibcon#read 3, iclass 26, count 2 2006.281.07:20:21.36#ibcon#about to read 4, iclass 26, count 2 2006.281.07:20:21.36#ibcon#read 4, iclass 26, count 2 2006.281.07:20:21.36#ibcon#about to read 5, iclass 26, count 2 2006.281.07:20:21.36#ibcon#read 5, iclass 26, count 2 2006.281.07:20:21.36#ibcon#about to read 6, iclass 26, count 2 2006.281.07:20:21.36#ibcon#read 6, iclass 26, count 2 2006.281.07:20:21.36#ibcon#end of sib2, iclass 26, count 2 2006.281.07:20:21.36#ibcon#*after write, iclass 26, count 2 2006.281.07:20:21.36#ibcon#*before return 0, iclass 26, count 2 2006.281.07:20:21.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:21.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:20:21.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:20:21.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:21.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:21.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:21.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:21.48#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:20:21.48#ibcon#first serial, iclass 26, count 0 2006.281.07:20:21.48#ibcon#enter sib2, iclass 26, count 0 2006.281.07:20:21.48#ibcon#flushed, iclass 26, count 0 2006.281.07:20:21.48#ibcon#about to write, iclass 26, count 0 2006.281.07:20:21.48#ibcon#wrote, iclass 26, count 0 2006.281.07:20:21.48#ibcon#about to read 3, iclass 26, count 0 2006.281.07:20:21.50#ibcon#read 3, iclass 26, count 0 2006.281.07:20:21.50#ibcon#about to read 4, iclass 26, count 0 2006.281.07:20:21.50#ibcon#read 4, iclass 26, count 0 2006.281.07:20:21.50#ibcon#about to read 5, iclass 26, count 0 2006.281.07:20:21.50#ibcon#read 5, iclass 26, count 0 2006.281.07:20:21.50#ibcon#about to read 6, iclass 26, count 0 2006.281.07:20:21.50#ibcon#read 6, iclass 26, count 0 2006.281.07:20:21.50#ibcon#end of sib2, iclass 26, count 0 2006.281.07:20:21.50#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:20:21.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:20:21.50#ibcon#[27=USB\r\n] 2006.281.07:20:21.50#ibcon#*before write, iclass 26, count 0 2006.281.07:20:21.50#ibcon#enter sib2, iclass 26, count 0 2006.281.07:20:21.50#ibcon#flushed, iclass 26, count 0 2006.281.07:20:21.50#ibcon#about to write, iclass 26, count 0 2006.281.07:20:21.50#ibcon#wrote, iclass 26, count 0 2006.281.07:20:21.50#ibcon#about to read 3, iclass 26, count 0 2006.281.07:20:21.53#ibcon#read 3, iclass 26, count 0 2006.281.07:20:21.53#ibcon#about to read 4, iclass 26, count 0 2006.281.07:20:21.53#ibcon#read 4, iclass 26, count 0 2006.281.07:20:21.53#ibcon#about to read 5, iclass 26, count 0 2006.281.07:20:21.53#ibcon#read 5, iclass 26, count 0 2006.281.07:20:21.53#ibcon#about to read 6, iclass 26, count 0 2006.281.07:20:21.53#ibcon#read 6, iclass 26, count 0 2006.281.07:20:21.53#ibcon#end of sib2, iclass 26, count 0 2006.281.07:20:21.53#ibcon#*after write, iclass 26, count 0 2006.281.07:20:21.53#ibcon#*before return 0, iclass 26, count 0 2006.281.07:20:21.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:21.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:20:21.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:20:21.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:20:21.53$vc4f8/vblo=4,712.99 2006.281.07:20:21.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:20:21.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:20:21.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:21.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:21.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:21.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:21.53#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:20:21.53#ibcon#first serial, iclass 28, count 0 2006.281.07:20:21.53#ibcon#enter sib2, iclass 28, count 0 2006.281.07:20:21.53#ibcon#flushed, iclass 28, count 0 2006.281.07:20:21.53#ibcon#about to write, iclass 28, count 0 2006.281.07:20:21.53#ibcon#wrote, iclass 28, count 0 2006.281.07:20:21.53#ibcon#about to read 3, iclass 28, count 0 2006.281.07:20:21.55#ibcon#read 3, iclass 28, count 0 2006.281.07:20:21.55#ibcon#about to read 4, iclass 28, count 0 2006.281.07:20:21.55#ibcon#read 4, iclass 28, count 0 2006.281.07:20:21.55#ibcon#about to read 5, iclass 28, count 0 2006.281.07:20:21.55#ibcon#read 5, iclass 28, count 0 2006.281.07:20:21.55#ibcon#about to read 6, iclass 28, count 0 2006.281.07:20:21.55#ibcon#read 6, iclass 28, count 0 2006.281.07:20:21.55#ibcon#end of sib2, iclass 28, count 0 2006.281.07:20:21.55#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:20:21.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:20:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:20:21.57#ibcon#*before write, iclass 28, count 0 2006.281.07:20:21.57#ibcon#enter sib2, iclass 28, count 0 2006.281.07:20:21.57#ibcon#flushed, iclass 28, count 0 2006.281.07:20:21.57#ibcon#about to write, iclass 28, count 0 2006.281.07:20:21.57#ibcon#wrote, iclass 28, count 0 2006.281.07:20:21.57#ibcon#about to read 3, iclass 28, count 0 2006.281.07:20:21.61#ibcon#read 3, iclass 28, count 0 2006.281.07:20:21.61#ibcon#about to read 4, iclass 28, count 0 2006.281.07:20:21.61#ibcon#read 4, iclass 28, count 0 2006.281.07:20:21.61#ibcon#about to read 5, iclass 28, count 0 2006.281.07:20:21.61#ibcon#read 5, iclass 28, count 0 2006.281.07:20:21.61#ibcon#about to read 6, iclass 28, count 0 2006.281.07:20:21.61#ibcon#read 6, iclass 28, count 0 2006.281.07:20:21.61#ibcon#end of sib2, iclass 28, count 0 2006.281.07:20:21.61#ibcon#*after write, iclass 28, count 0 2006.281.07:20:21.61#ibcon#*before return 0, iclass 28, count 0 2006.281.07:20:21.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:21.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:20:21.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:20:21.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:20:21.61$vc4f8/vb=4,4 2006.281.07:20:21.61#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:20:21.61#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:20:21.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:21.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:21.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:21.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:21.65#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:20:21.65#ibcon#first serial, iclass 30, count 2 2006.281.07:20:21.65#ibcon#enter sib2, iclass 30, count 2 2006.281.07:20:21.65#ibcon#flushed, iclass 30, count 2 2006.281.07:20:21.65#ibcon#about to write, iclass 30, count 2 2006.281.07:20:21.65#ibcon#wrote, iclass 30, count 2 2006.281.07:20:21.65#ibcon#about to read 3, iclass 30, count 2 2006.281.07:20:21.67#ibcon#read 3, iclass 30, count 2 2006.281.07:20:21.67#ibcon#about to read 4, iclass 30, count 2 2006.281.07:20:21.67#ibcon#read 4, iclass 30, count 2 2006.281.07:20:21.67#ibcon#about to read 5, iclass 30, count 2 2006.281.07:20:21.67#ibcon#read 5, iclass 30, count 2 2006.281.07:20:21.67#ibcon#about to read 6, iclass 30, count 2 2006.281.07:20:21.67#ibcon#read 6, iclass 30, count 2 2006.281.07:20:21.67#ibcon#end of sib2, iclass 30, count 2 2006.281.07:20:21.67#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:20:21.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:20:21.67#ibcon#[27=AT04-04\r\n] 2006.281.07:20:21.67#ibcon#*before write, iclass 30, count 2 2006.281.07:20:21.67#ibcon#enter sib2, iclass 30, count 2 2006.281.07:20:21.67#ibcon#flushed, iclass 30, count 2 2006.281.07:20:21.67#ibcon#about to write, iclass 30, count 2 2006.281.07:20:21.67#ibcon#wrote, iclass 30, count 2 2006.281.07:20:21.67#ibcon#about to read 3, iclass 30, count 2 2006.281.07:20:21.70#ibcon#read 3, iclass 30, count 2 2006.281.07:20:21.70#ibcon#about to read 4, iclass 30, count 2 2006.281.07:20:21.70#ibcon#read 4, iclass 30, count 2 2006.281.07:20:21.70#ibcon#about to read 5, iclass 30, count 2 2006.281.07:20:21.70#ibcon#read 5, iclass 30, count 2 2006.281.07:20:21.70#ibcon#about to read 6, iclass 30, count 2 2006.281.07:20:21.70#ibcon#read 6, iclass 30, count 2 2006.281.07:20:21.70#ibcon#end of sib2, iclass 30, count 2 2006.281.07:20:21.70#ibcon#*after write, iclass 30, count 2 2006.281.07:20:21.70#ibcon#*before return 0, iclass 30, count 2 2006.281.07:20:21.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:21.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:20:21.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:20:21.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:21.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:21.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:21.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:21.82#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:20:21.82#ibcon#first serial, iclass 30, count 0 2006.281.07:20:21.82#ibcon#enter sib2, iclass 30, count 0 2006.281.07:20:21.82#ibcon#flushed, iclass 30, count 0 2006.281.07:20:21.82#ibcon#about to write, iclass 30, count 0 2006.281.07:20:21.82#ibcon#wrote, iclass 30, count 0 2006.281.07:20:21.82#ibcon#about to read 3, iclass 30, count 0 2006.281.07:20:21.84#ibcon#read 3, iclass 30, count 0 2006.281.07:20:21.84#ibcon#about to read 4, iclass 30, count 0 2006.281.07:20:21.84#ibcon#read 4, iclass 30, count 0 2006.281.07:20:21.84#ibcon#about to read 5, iclass 30, count 0 2006.281.07:20:21.84#ibcon#read 5, iclass 30, count 0 2006.281.07:20:21.84#ibcon#about to read 6, iclass 30, count 0 2006.281.07:20:21.84#ibcon#read 6, iclass 30, count 0 2006.281.07:20:21.84#ibcon#end of sib2, iclass 30, count 0 2006.281.07:20:21.84#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:20:21.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:20:21.84#ibcon#[27=USB\r\n] 2006.281.07:20:21.84#ibcon#*before write, iclass 30, count 0 2006.281.07:20:21.84#ibcon#enter sib2, iclass 30, count 0 2006.281.07:20:21.84#ibcon#flushed, iclass 30, count 0 2006.281.07:20:21.84#ibcon#about to write, iclass 30, count 0 2006.281.07:20:21.84#ibcon#wrote, iclass 30, count 0 2006.281.07:20:21.84#ibcon#about to read 3, iclass 30, count 0 2006.281.07:20:21.87#ibcon#read 3, iclass 30, count 0 2006.281.07:20:21.87#ibcon#about to read 4, iclass 30, count 0 2006.281.07:20:21.87#ibcon#read 4, iclass 30, count 0 2006.281.07:20:21.87#ibcon#about to read 5, iclass 30, count 0 2006.281.07:20:21.87#ibcon#read 5, iclass 30, count 0 2006.281.07:20:21.87#ibcon#about to read 6, iclass 30, count 0 2006.281.07:20:21.87#ibcon#read 6, iclass 30, count 0 2006.281.07:20:21.87#ibcon#end of sib2, iclass 30, count 0 2006.281.07:20:21.87#ibcon#*after write, iclass 30, count 0 2006.281.07:20:21.87#ibcon#*before return 0, iclass 30, count 0 2006.281.07:20:21.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:21.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:20:21.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:20:21.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:20:21.87$vc4f8/vblo=5,744.99 2006.281.07:20:21.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:20:21.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:20:21.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:21.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:21.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:21.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:21.87#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:20:21.87#ibcon#first serial, iclass 32, count 0 2006.281.07:20:21.87#ibcon#enter sib2, iclass 32, count 0 2006.281.07:20:21.87#ibcon#flushed, iclass 32, count 0 2006.281.07:20:21.87#ibcon#about to write, iclass 32, count 0 2006.281.07:20:21.87#ibcon#wrote, iclass 32, count 0 2006.281.07:20:21.87#ibcon#about to read 3, iclass 32, count 0 2006.281.07:20:21.89#ibcon#read 3, iclass 32, count 0 2006.281.07:20:21.89#ibcon#about to read 4, iclass 32, count 0 2006.281.07:20:21.89#ibcon#read 4, iclass 32, count 0 2006.281.07:20:21.89#ibcon#about to read 5, iclass 32, count 0 2006.281.07:20:21.89#ibcon#read 5, iclass 32, count 0 2006.281.07:20:21.89#ibcon#about to read 6, iclass 32, count 0 2006.281.07:20:21.89#ibcon#read 6, iclass 32, count 0 2006.281.07:20:21.89#ibcon#end of sib2, iclass 32, count 0 2006.281.07:20:21.89#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:20:21.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:20:21.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:20:21.89#ibcon#*before write, iclass 32, count 0 2006.281.07:20:21.89#ibcon#enter sib2, iclass 32, count 0 2006.281.07:20:21.89#ibcon#flushed, iclass 32, count 0 2006.281.07:20:21.89#ibcon#about to write, iclass 32, count 0 2006.281.07:20:21.89#ibcon#wrote, iclass 32, count 0 2006.281.07:20:21.89#ibcon#about to read 3, iclass 32, count 0 2006.281.07:20:21.93#ibcon#read 3, iclass 32, count 0 2006.281.07:20:21.93#ibcon#about to read 4, iclass 32, count 0 2006.281.07:20:21.93#ibcon#read 4, iclass 32, count 0 2006.281.07:20:21.93#ibcon#about to read 5, iclass 32, count 0 2006.281.07:20:21.93#ibcon#read 5, iclass 32, count 0 2006.281.07:20:21.93#ibcon#about to read 6, iclass 32, count 0 2006.281.07:20:21.93#ibcon#read 6, iclass 32, count 0 2006.281.07:20:21.93#ibcon#end of sib2, iclass 32, count 0 2006.281.07:20:21.93#ibcon#*after write, iclass 32, count 0 2006.281.07:20:21.93#ibcon#*before return 0, iclass 32, count 0 2006.281.07:20:21.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:21.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:20:21.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:20:21.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:20:21.93$vc4f8/vb=5,4 2006.281.07:20:21.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:20:21.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:20:21.93#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:21.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:21.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:21.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:21.99#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:20:21.99#ibcon#first serial, iclass 34, count 2 2006.281.07:20:21.99#ibcon#enter sib2, iclass 34, count 2 2006.281.07:20:21.99#ibcon#flushed, iclass 34, count 2 2006.281.07:20:21.99#ibcon#about to write, iclass 34, count 2 2006.281.07:20:21.99#ibcon#wrote, iclass 34, count 2 2006.281.07:20:21.99#ibcon#about to read 3, iclass 34, count 2 2006.281.07:20:22.01#ibcon#read 3, iclass 34, count 2 2006.281.07:20:22.01#ibcon#about to read 4, iclass 34, count 2 2006.281.07:20:22.01#ibcon#read 4, iclass 34, count 2 2006.281.07:20:22.01#ibcon#about to read 5, iclass 34, count 2 2006.281.07:20:22.01#ibcon#read 5, iclass 34, count 2 2006.281.07:20:22.01#ibcon#about to read 6, iclass 34, count 2 2006.281.07:20:22.01#ibcon#read 6, iclass 34, count 2 2006.281.07:20:22.01#ibcon#end of sib2, iclass 34, count 2 2006.281.07:20:22.01#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:20:22.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:20:22.01#ibcon#[27=AT05-04\r\n] 2006.281.07:20:22.01#ibcon#*before write, iclass 34, count 2 2006.281.07:20:22.01#ibcon#enter sib2, iclass 34, count 2 2006.281.07:20:22.01#ibcon#flushed, iclass 34, count 2 2006.281.07:20:22.01#ibcon#about to write, iclass 34, count 2 2006.281.07:20:22.01#ibcon#wrote, iclass 34, count 2 2006.281.07:20:22.01#ibcon#about to read 3, iclass 34, count 2 2006.281.07:20:22.04#ibcon#read 3, iclass 34, count 2 2006.281.07:20:22.04#ibcon#about to read 4, iclass 34, count 2 2006.281.07:20:22.04#ibcon#read 4, iclass 34, count 2 2006.281.07:20:22.04#ibcon#about to read 5, iclass 34, count 2 2006.281.07:20:22.04#ibcon#read 5, iclass 34, count 2 2006.281.07:20:22.04#ibcon#about to read 6, iclass 34, count 2 2006.281.07:20:22.04#ibcon#read 6, iclass 34, count 2 2006.281.07:20:22.04#ibcon#end of sib2, iclass 34, count 2 2006.281.07:20:22.04#ibcon#*after write, iclass 34, count 2 2006.281.07:20:22.04#ibcon#*before return 0, iclass 34, count 2 2006.281.07:20:22.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:22.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:20:22.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:20:22.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:22.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:22.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:22.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:22.16#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:20:22.16#ibcon#first serial, iclass 34, count 0 2006.281.07:20:22.16#ibcon#enter sib2, iclass 34, count 0 2006.281.07:20:22.16#ibcon#flushed, iclass 34, count 0 2006.281.07:20:22.16#ibcon#about to write, iclass 34, count 0 2006.281.07:20:22.16#ibcon#wrote, iclass 34, count 0 2006.281.07:20:22.16#ibcon#about to read 3, iclass 34, count 0 2006.281.07:20:22.18#ibcon#read 3, iclass 34, count 0 2006.281.07:20:22.18#ibcon#about to read 4, iclass 34, count 0 2006.281.07:20:22.18#ibcon#read 4, iclass 34, count 0 2006.281.07:20:22.18#ibcon#about to read 5, iclass 34, count 0 2006.281.07:20:22.18#ibcon#read 5, iclass 34, count 0 2006.281.07:20:22.18#ibcon#about to read 6, iclass 34, count 0 2006.281.07:20:22.18#ibcon#read 6, iclass 34, count 0 2006.281.07:20:22.18#ibcon#end of sib2, iclass 34, count 0 2006.281.07:20:22.18#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:20:22.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:20:22.18#ibcon#[27=USB\r\n] 2006.281.07:20:22.18#ibcon#*before write, iclass 34, count 0 2006.281.07:20:22.18#ibcon#enter sib2, iclass 34, count 0 2006.281.07:20:22.18#ibcon#flushed, iclass 34, count 0 2006.281.07:20:22.18#ibcon#about to write, iclass 34, count 0 2006.281.07:20:22.18#ibcon#wrote, iclass 34, count 0 2006.281.07:20:22.18#ibcon#about to read 3, iclass 34, count 0 2006.281.07:20:22.21#ibcon#read 3, iclass 34, count 0 2006.281.07:20:22.21#ibcon#about to read 4, iclass 34, count 0 2006.281.07:20:22.21#ibcon#read 4, iclass 34, count 0 2006.281.07:20:22.21#ibcon#about to read 5, iclass 34, count 0 2006.281.07:20:22.21#ibcon#read 5, iclass 34, count 0 2006.281.07:20:22.21#ibcon#about to read 6, iclass 34, count 0 2006.281.07:20:22.21#ibcon#read 6, iclass 34, count 0 2006.281.07:20:22.21#ibcon#end of sib2, iclass 34, count 0 2006.281.07:20:22.21#ibcon#*after write, iclass 34, count 0 2006.281.07:20:22.21#ibcon#*before return 0, iclass 34, count 0 2006.281.07:20:22.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:22.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:20:22.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:20:22.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:20:22.21$vc4f8/vblo=6,752.99 2006.281.07:20:22.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:20:22.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:20:22.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:20:22.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:22.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:22.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:22.21#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:20:22.21#ibcon#first serial, iclass 36, count 0 2006.281.07:20:22.21#ibcon#enter sib2, iclass 36, count 0 2006.281.07:20:22.21#ibcon#flushed, iclass 36, count 0 2006.281.07:20:22.21#ibcon#about to write, iclass 36, count 0 2006.281.07:20:22.21#ibcon#wrote, iclass 36, count 0 2006.281.07:20:22.21#ibcon#about to read 3, iclass 36, count 0 2006.281.07:20:22.23#ibcon#read 3, iclass 36, count 0 2006.281.07:20:22.23#ibcon#about to read 4, iclass 36, count 0 2006.281.07:20:22.23#ibcon#read 4, iclass 36, count 0 2006.281.07:20:22.23#ibcon#about to read 5, iclass 36, count 0 2006.281.07:20:22.23#ibcon#read 5, iclass 36, count 0 2006.281.07:20:22.23#ibcon#about to read 6, iclass 36, count 0 2006.281.07:20:22.23#ibcon#read 6, iclass 36, count 0 2006.281.07:20:22.23#ibcon#end of sib2, iclass 36, count 0 2006.281.07:20:22.23#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:20:22.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:20:22.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:20:22.23#ibcon#*before write, iclass 36, count 0 2006.281.07:20:22.23#ibcon#enter sib2, iclass 36, count 0 2006.281.07:20:22.23#ibcon#flushed, iclass 36, count 0 2006.281.07:20:22.23#ibcon#about to write, iclass 36, count 0 2006.281.07:20:22.23#ibcon#wrote, iclass 36, count 0 2006.281.07:20:22.23#ibcon#about to read 3, iclass 36, count 0 2006.281.07:20:22.27#ibcon#read 3, iclass 36, count 0 2006.281.07:20:22.27#ibcon#about to read 4, iclass 36, count 0 2006.281.07:20:22.27#ibcon#read 4, iclass 36, count 0 2006.281.07:20:22.27#ibcon#about to read 5, iclass 36, count 0 2006.281.07:20:22.27#ibcon#read 5, iclass 36, count 0 2006.281.07:20:22.27#ibcon#about to read 6, iclass 36, count 0 2006.281.07:20:22.27#ibcon#read 6, iclass 36, count 0 2006.281.07:20:22.27#ibcon#end of sib2, iclass 36, count 0 2006.281.07:20:22.27#ibcon#*after write, iclass 36, count 0 2006.281.07:20:22.27#ibcon#*before return 0, iclass 36, count 0 2006.281.07:20:22.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:22.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:20:22.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:20:22.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:20:22.27$vc4f8/vb=6,4 2006.281.07:20:22.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:20:22.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:20:22.27#ibcon#ireg 11 cls_cnt 2 2006.281.07:20:22.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:22.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:22.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:22.33#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:20:22.33#ibcon#first serial, iclass 38, count 2 2006.281.07:20:22.33#ibcon#enter sib2, iclass 38, count 2 2006.281.07:20:22.33#ibcon#flushed, iclass 38, count 2 2006.281.07:20:22.33#ibcon#about to write, iclass 38, count 2 2006.281.07:20:22.33#ibcon#wrote, iclass 38, count 2 2006.281.07:20:22.33#ibcon#about to read 3, iclass 38, count 2 2006.281.07:20:22.35#ibcon#read 3, iclass 38, count 2 2006.281.07:20:22.35#ibcon#about to read 4, iclass 38, count 2 2006.281.07:20:22.35#ibcon#read 4, iclass 38, count 2 2006.281.07:20:22.35#ibcon#about to read 5, iclass 38, count 2 2006.281.07:20:22.35#ibcon#read 5, iclass 38, count 2 2006.281.07:20:22.35#ibcon#about to read 6, iclass 38, count 2 2006.281.07:20:22.35#ibcon#read 6, iclass 38, count 2 2006.281.07:20:22.35#ibcon#end of sib2, iclass 38, count 2 2006.281.07:20:22.35#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:20:22.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:20:22.35#ibcon#[27=AT06-04\r\n] 2006.281.07:20:22.35#ibcon#*before write, iclass 38, count 2 2006.281.07:20:22.35#ibcon#enter sib2, iclass 38, count 2 2006.281.07:20:22.35#ibcon#flushed, iclass 38, count 2 2006.281.07:20:22.35#ibcon#about to write, iclass 38, count 2 2006.281.07:20:22.35#ibcon#wrote, iclass 38, count 2 2006.281.07:20:22.35#ibcon#about to read 3, iclass 38, count 2 2006.281.07:20:22.38#ibcon#read 3, iclass 38, count 2 2006.281.07:20:22.38#ibcon#about to read 4, iclass 38, count 2 2006.281.07:20:22.38#ibcon#read 4, iclass 38, count 2 2006.281.07:20:22.38#ibcon#about to read 5, iclass 38, count 2 2006.281.07:20:22.38#ibcon#read 5, iclass 38, count 2 2006.281.07:20:22.38#ibcon#about to read 6, iclass 38, count 2 2006.281.07:20:22.38#ibcon#read 6, iclass 38, count 2 2006.281.07:20:22.38#ibcon#end of sib2, iclass 38, count 2 2006.281.07:20:22.38#ibcon#*after write, iclass 38, count 2 2006.281.07:20:22.38#ibcon#*before return 0, iclass 38, count 2 2006.281.07:20:22.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:22.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:20:22.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:20:22.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:20:22.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:22.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:22.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:22.50#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:20:22.50#ibcon#first serial, iclass 38, count 0 2006.281.07:20:22.50#ibcon#enter sib2, iclass 38, count 0 2006.281.07:20:22.50#ibcon#flushed, iclass 38, count 0 2006.281.07:20:22.50#ibcon#about to write, iclass 38, count 0 2006.281.07:20:22.50#ibcon#wrote, iclass 38, count 0 2006.281.07:20:22.50#ibcon#about to read 3, iclass 38, count 0 2006.281.07:20:22.52#ibcon#read 3, iclass 38, count 0 2006.281.07:20:22.52#ibcon#about to read 4, iclass 38, count 0 2006.281.07:20:22.52#ibcon#read 4, iclass 38, count 0 2006.281.07:20:22.52#ibcon#about to read 5, iclass 38, count 0 2006.281.07:20:22.52#ibcon#read 5, iclass 38, count 0 2006.281.07:20:22.52#ibcon#about to read 6, iclass 38, count 0 2006.281.07:20:22.52#ibcon#read 6, iclass 38, count 0 2006.281.07:20:22.52#ibcon#end of sib2, iclass 38, count 0 2006.281.07:20:22.52#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:20:22.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:20:22.52#ibcon#[27=USB\r\n] 2006.281.07:20:22.52#ibcon#*before write, iclass 38, count 0 2006.281.07:20:22.52#ibcon#enter sib2, iclass 38, count 0 2006.281.07:20:22.52#ibcon#flushed, iclass 38, count 0 2006.281.07:20:22.52#ibcon#about to write, iclass 38, count 0 2006.281.07:20:22.52#ibcon#wrote, iclass 38, count 0 2006.281.07:20:22.52#ibcon#about to read 3, iclass 38, count 0 2006.281.07:20:22.55#ibcon#read 3, iclass 38, count 0 2006.281.07:20:22.55#ibcon#about to read 4, iclass 38, count 0 2006.281.07:20:22.55#ibcon#read 4, iclass 38, count 0 2006.281.07:20:22.55#ibcon#about to read 5, iclass 38, count 0 2006.281.07:20:22.55#ibcon#read 5, iclass 38, count 0 2006.281.07:20:22.55#ibcon#about to read 6, iclass 38, count 0 2006.281.07:20:22.55#ibcon#read 6, iclass 38, count 0 2006.281.07:20:22.55#ibcon#end of sib2, iclass 38, count 0 2006.281.07:20:22.55#ibcon#*after write, iclass 38, count 0 2006.281.07:20:22.55#ibcon#*before return 0, iclass 38, count 0 2006.281.07:20:22.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:22.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:20:22.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:20:22.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:20:22.55$vc4f8/vabw=wide 2006.281.07:20:22.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:20:22.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:20:22.55#ibcon#ireg 8 cls_cnt 0 2006.281.07:20:22.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:22.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:22.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:22.55#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:20:22.55#ibcon#first serial, iclass 40, count 0 2006.281.07:20:22.55#ibcon#enter sib2, iclass 40, count 0 2006.281.07:20:22.55#ibcon#flushed, iclass 40, count 0 2006.281.07:20:22.55#ibcon#about to write, iclass 40, count 0 2006.281.07:20:22.55#ibcon#wrote, iclass 40, count 0 2006.281.07:20:22.55#ibcon#about to read 3, iclass 40, count 0 2006.281.07:20:22.57#ibcon#read 3, iclass 40, count 0 2006.281.07:20:22.57#ibcon#about to read 4, iclass 40, count 0 2006.281.07:20:22.57#ibcon#read 4, iclass 40, count 0 2006.281.07:20:22.57#ibcon#about to read 5, iclass 40, count 0 2006.281.07:20:22.57#ibcon#read 5, iclass 40, count 0 2006.281.07:20:22.57#ibcon#about to read 6, iclass 40, count 0 2006.281.07:20:22.57#ibcon#read 6, iclass 40, count 0 2006.281.07:20:22.57#ibcon#end of sib2, iclass 40, count 0 2006.281.07:20:22.57#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:20:22.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:20:22.59#ibcon#[25=BW32\r\n] 2006.281.07:20:22.59#ibcon#*before write, iclass 40, count 0 2006.281.07:20:22.59#ibcon#enter sib2, iclass 40, count 0 2006.281.07:20:22.59#ibcon#flushed, iclass 40, count 0 2006.281.07:20:22.59#ibcon#about to write, iclass 40, count 0 2006.281.07:20:22.59#ibcon#wrote, iclass 40, count 0 2006.281.07:20:22.59#ibcon#about to read 3, iclass 40, count 0 2006.281.07:20:22.62#ibcon#read 3, iclass 40, count 0 2006.281.07:20:22.62#ibcon#about to read 4, iclass 40, count 0 2006.281.07:20:22.62#ibcon#read 4, iclass 40, count 0 2006.281.07:20:22.62#ibcon#about to read 5, iclass 40, count 0 2006.281.07:20:22.62#ibcon#read 5, iclass 40, count 0 2006.281.07:20:22.62#ibcon#about to read 6, iclass 40, count 0 2006.281.07:20:22.62#ibcon#read 6, iclass 40, count 0 2006.281.07:20:22.62#ibcon#end of sib2, iclass 40, count 0 2006.281.07:20:22.62#ibcon#*after write, iclass 40, count 0 2006.281.07:20:22.62#ibcon#*before return 0, iclass 40, count 0 2006.281.07:20:22.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:22.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:20:22.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:20:22.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:20:22.62$vc4f8/vbbw=wide 2006.281.07:20:22.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:20:22.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:20:22.62#ibcon#ireg 8 cls_cnt 0 2006.281.07:20:22.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:20:22.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:20:22.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:20:22.67#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:20:22.67#ibcon#first serial, iclass 4, count 0 2006.281.07:20:22.67#ibcon#enter sib2, iclass 4, count 0 2006.281.07:20:22.67#ibcon#flushed, iclass 4, count 0 2006.281.07:20:22.67#ibcon#about to write, iclass 4, count 0 2006.281.07:20:22.67#ibcon#wrote, iclass 4, count 0 2006.281.07:20:22.67#ibcon#about to read 3, iclass 4, count 0 2006.281.07:20:22.69#ibcon#read 3, iclass 4, count 0 2006.281.07:20:22.69#ibcon#about to read 4, iclass 4, count 0 2006.281.07:20:22.69#ibcon#read 4, iclass 4, count 0 2006.281.07:20:22.69#ibcon#about to read 5, iclass 4, count 0 2006.281.07:20:22.69#ibcon#read 5, iclass 4, count 0 2006.281.07:20:22.69#ibcon#about to read 6, iclass 4, count 0 2006.281.07:20:22.69#ibcon#read 6, iclass 4, count 0 2006.281.07:20:22.69#ibcon#end of sib2, iclass 4, count 0 2006.281.07:20:22.69#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:20:22.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:20:22.69#ibcon#[27=BW32\r\n] 2006.281.07:20:22.69#ibcon#*before write, iclass 4, count 0 2006.281.07:20:22.69#ibcon#enter sib2, iclass 4, count 0 2006.281.07:20:22.69#ibcon#flushed, iclass 4, count 0 2006.281.07:20:22.69#ibcon#about to write, iclass 4, count 0 2006.281.07:20:22.69#ibcon#wrote, iclass 4, count 0 2006.281.07:20:22.69#ibcon#about to read 3, iclass 4, count 0 2006.281.07:20:22.72#ibcon#read 3, iclass 4, count 0 2006.281.07:20:22.72#ibcon#about to read 4, iclass 4, count 0 2006.281.07:20:22.72#ibcon#read 4, iclass 4, count 0 2006.281.07:20:22.72#ibcon#about to read 5, iclass 4, count 0 2006.281.07:20:22.72#ibcon#read 5, iclass 4, count 0 2006.281.07:20:22.72#ibcon#about to read 6, iclass 4, count 0 2006.281.07:20:22.72#ibcon#read 6, iclass 4, count 0 2006.281.07:20:22.72#ibcon#end of sib2, iclass 4, count 0 2006.281.07:20:22.72#ibcon#*after write, iclass 4, count 0 2006.281.07:20:22.72#ibcon#*before return 0, iclass 4, count 0 2006.281.07:20:22.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:20:22.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:20:22.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:20:22.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:20:22.72$4f8m12a/ifd4f 2006.281.07:20:22.72&ifd4f/lo= 2006.281.07:20:22.72&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:20:22.72&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:20:22.72&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:20:22.72&ifd4f/patch= 2006.281.07:20:22.72&ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:20:22.72&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:20:22.72&ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:20:22.72$ifd4f/lo= 2006.281.07:20:22.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:20:22.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:20:22.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:20:22.72$ifd4f/patch= 2006.281.07:20:22.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:20:22.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:20:22.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:20:22.72$4f8m12a/"form=m,16.000,1:2 2006.281.07:20:22.72$4f8m12a/"tpicd 2006.281.07:20:22.72$4f8m12a/echo=off 2006.281.07:20:22.72$4f8m12a/xlog=off 2006.281.07:20:22.72:!2006.281.07:29:50 2006.281.07:20:36.14#trakl#Source acquired 2006.281.07:20:38.14#flagr#flagr/antenna,acquired 2006.281.07:21:45.14#trakl#Off source 2006.281.07:21:45.14?ERROR st -7 Antenna off-source! 2006.281.07:21:45.14#trakl#az 319.087 el 39.396 azerr*cos(el) -0.0027 elerr -0.0302 2006.281.07:21:47.14#flagr#flagr/antenna,off-source 2006.281.07:21:55.14#trakl#Source re-acquired 2006.281.07:21:56.14#trakl#Off source 2006.281.07:21:56.14?ERROR st -7 Antenna off-source! 2006.281.07:21:56.14#trakl#az 319.092 el 39.372 azerr*cos(el) -0.0050 elerr 0.0161 2006.281.07:22:03.14#trakl#Source re-acquired 2006.281.07:22:05.14#trakl#Off source 2006.281.07:22:05.14?ERROR st -7 Antenna off-source! 2006.281.07:22:05.14#trakl#az 319.095 el 39.352 azerr*cos(el) -0.0076 elerr -0.0230 2006.281.07:22:11.14#trakl#Source re-acquired 2006.281.07:22:11.14#flagr#flagr/antenna,re-acquired 2006.281.07:22:27.14#trakl#Off source 2006.281.07:22:27.14?ERROR st -7 Antenna off-source! 2006.281.07:22:27.14#trakl#az 319.103 el 39.303 azerr*cos(el) -0.0015 elerr 0.0186 2006.281.07:22:29.14#flagr#flagr/antenna,off-source 2006.281.07:22:33.14#trakl#Source re-acquired 2006.281.07:22:35.14#flagr#flagr/antenna,re-acquired 2006.281.07:22:38.14#trakl#Off source 2006.281.07:22:38.14?ERROR st -7 Antenna off-source! 2006.281.07:22:38.14#trakl#az 319.107 el 39.279 azerr*cos(el) -0.0047 elerr -0.0191 2006.281.07:22:38.14#flagr#flagr/antenna,off-source 2006.281.07:22:44.14#trakl#Source re-acquired 2006.281.07:22:44.14#flagr#flagr/antenna,re-acquired 2006.281.07:23:05.14#trakl#Off source 2006.281.07:23:05.14?ERROR st -7 Antenna off-source! 2006.281.07:23:05.14#trakl#az 319.117 el 39.219 azerr*cos(el) -0.0032 elerr -0.0194 2006.281.07:23:05.14#flagr#flagr/antenna,off-source 2006.281.07:23:17.14#trakl#Source re-acquired 2006.281.07:23:17.14#flagr#flagr/antenna,re-acquired 2006.281.07:23:48.14#trakl#Off source 2006.281.07:23:48.14?ERROR st -7 Antenna off-source! 2006.281.07:23:48.14#trakl#az 319.134 el 39.124 azerr*cos(el) -0.0035 elerr 0.0275 2006.281.07:23:50.13#flagr#flagr/antenna,off-source 2006.281.07:23:58.13#trakl#Source re-acquired 2006.281.07:23:59.13#trakl#Off source 2006.281.07:23:59.13?ERROR st -7 Antenna off-source! 2006.281.07:23:59.13#trakl#az 319.138 el 39.100 azerr*cos(el) 0.0025 elerr 0.0218 2006.281.07:24:06.13#trakl#Source re-acquired 2006.281.07:24:08.13#trakl#Off source 2006.281.07:24:08.13?ERROR st -7 Antenna off-source! 2006.281.07:24:08.13#trakl#az 319.141 el 39.080 azerr*cos(el) -0.0033 elerr -0.0193 2006.281.07:24:14.13#trakl#Source re-acquired 2006.281.07:24:14.13#flagr#flagr/antenna,re-acquired 2006.281.07:24:57.13#trakl#Off source 2006.281.07:24:57.13?ERROR st -7 Antenna off-source! 2006.281.07:24:57.13#trakl#az 319.160 el 38.972 azerr*cos(el) -0.0003 elerr -0.0242 2006.281.07:24:59.13#flagr#flagr/antenna,off-source 2006.281.07:25:03.13#trakl#Source re-acquired 2006.281.07:25:05.13#flagr#flagr/antenna,re-acquired 2006.281.07:25:51.14#trakl#Off source 2006.281.07:25:51.14?ERROR st -7 Antenna off-source! 2006.281.07:25:51.14#trakl#az 319.182 el 38.853 azerr*cos(el) 0.0032 elerr -0.0191 2006.281.07:25:53.14#flagr#flagr/antenna,off-source 2006.281.07:25:57.14#trakl#Source re-acquired 2006.281.07:25:59.14#flagr#flagr/antenna,re-acquired 2006.281.07:26:35.14#trakl#Off source 2006.281.07:26:35.14?ERROR st -7 Antenna off-source! 2006.281.07:26:35.14#trakl#az 319.200 el 38.756 azerr*cos(el) 0.0009 elerr 0.0170 2006.281.07:26:35.14#flagr#flagr/antenna,off-source 2006.281.07:26:41.14#trakl#Source re-acquired 2006.281.07:26:41.14#flagr#flagr/antenna,re-acquired 2006.281.07:26:43.14#trakl#Off source 2006.281.07:26:43.14?ERROR st -7 Antenna off-source! 2006.281.07:26:43.14#trakl#az 319.203 el 38.738 azerr*cos(el) -0.0008 elerr 0.0256 2006.281.07:26:44.14#flagr#flagr/antenna,off-source 2006.281.07:26:50.14#trakl#Source re-acquired 2006.281.07:26:50.14#flagr#flagr/antenna,re-acquired 2006.281.07:26:58.14#trakl#Off source 2006.281.07:26:58.14?ERROR st -7 Antenna off-source! 2006.281.07:26:58.14#trakl#az 319.209 el 38.705 azerr*cos(el) -0.0064 elerr -0.0233 2006.281.07:26:59.14#flagr#flagr/antenna,off-source 2006.281.07:27:04.14#trakl#Source re-acquired 2006.281.07:27:05.14#flagr#flagr/antenna,re-acquired 2006.281.07:27:54.14#trakl#Off source 2006.281.07:27:54.14?ERROR st -7 Antenna off-source! 2006.281.07:27:54.14#trakl#az 319.233 el 38.582 azerr*cos(el) 0.0238 elerr 0.0011 2006.281.07:27:56.14#flagr#flagr/antenna,off-source 2006.281.07:28:00.14#trakl#Source re-acquired 2006.281.07:28:02.14#flagr#flagr/antenna,re-acquired 2006.281.07:28:47.14#trakl#Off source 2006.281.07:28:47.14?ERROR st -7 Antenna off-source! 2006.281.07:28:47.14#trakl#az 319.255 el 38.465 azerr*cos(el) -0.0095 elerr 0.0338 2006.281.07:28:47.15#flagr#flagr/antenna,off-source 2006.281.07:29:02.14#trakl#Off source 2006.281.07:29:02.14?ERROR st -7 Antenna off-source! 2006.281.07:29:02.14#trakl#az 319.262 el 38.432 azerr*cos(el) 0.0011 elerr -0.0211 2006.281.07:29:09.14#trakl#Source re-acquired 2006.281.07:29:11.14#trakl#Off source 2006.281.07:29:11.14?ERROR st -7 Antenna off-source! 2006.281.07:29:11.14#trakl#az 319.265 el 38.412 azerr*cos(el) -0.0019 elerr 0.0307 2006.281.07:29:25.14#trakl#Source re-acquired 2006.281.07:29:26.14#flagr#flagr/antenna,re-acquired 2006.281.07:29:50.00:preob 2006.281.07:29:50.00&preob/onsource 2006.281.07:29:51.14/onsource/TRACKING 2006.281.07:29:51.14:!2006.281.07:30:00 2006.281.07:29:53.14#trakl#Off source 2006.281.07:29:53.14?ERROR st -7 Antenna off-source! 2006.281.07:29:53.14#trakl#az 319.284 el 38.320 azerr*cos(el) 0.0010 elerr -0.0168 2006.281.07:29:55.14#flagr#flagr/antenna,off-source 2006.281.07:29:59.14#trakl#Source re-acquired 2006.281.07:30:00.00:data_valid=on 2006.281.07:30:00.00:midob 2006.281.07:30:00.00&midob/onsource 2006.281.07:30:00.00&midob/wx 2006.281.07:30:00.00&midob/cable 2006.281.07:30:00.00&midob/va 2006.281.07:30:00.00&midob/valo 2006.281.07:30:00.00&midob/vb 2006.281.07:30:00.00&midob/vblo 2006.281.07:30:00.00&midob/vabw 2006.281.07:30:00.00&midob/vbbw 2006.281.07:30:00.00&midob/"form 2006.281.07:30:00.00&midob/xfe 2006.281.07:30:00.00&midob/ifatt 2006.281.07:30:00.00&midob/clockoff 2006.281.07:30:00.00&midob/sy=logmail 2006.281.07:30:00.00&midob/"sy=run setcl adapt & 2006.281.07:30:00.14/onsource/TRACKING 2006.281.07:30:00.14/wx/21.59,1001.1,49 2006.281.07:30:00.27/cable/+6.4838E-03 2006.281.07:30:01.14#flagr#flagr/antenna,re-acquired 2006.281.07:30:01.36/va/01,07,usb,yes,32,34 2006.281.07:30:01.36/va/02,06,usb,yes,30,31 2006.281.07:30:01.36/va/03,06,usb,yes,28,28 2006.281.07:30:01.36/va/04,06,usb,yes,31,33 2006.281.07:30:01.36/va/05,07,usb,yes,29,30 2006.281.07:30:01.36/va/06,06,usb,yes,28,27 2006.281.07:30:01.36/va/07,06,usb,yes,28,28 2006.281.07:30:01.36/va/08,06,usb,yes,30,30 2006.281.07:30:01.59/valo/01,532.99,yes,locked 2006.281.07:30:01.59/valo/02,572.99,yes,locked 2006.281.07:30:01.59/valo/03,672.99,yes,locked 2006.281.07:30:01.59/valo/04,832.99,yes,locked 2006.281.07:30:01.59/valo/05,652.99,yes,locked 2006.281.07:30:01.59/valo/06,772.99,yes,locked 2006.281.07:30:01.59/valo/07,832.99,yes,locked 2006.281.07:30:01.59/valo/08,852.99,yes,locked 2006.281.07:30:02.68/vb/01,04,usb,yes,30,29 2006.281.07:30:02.68/vb/02,05,usb,yes,28,29 2006.281.07:30:02.68/vb/03,04,usb,yes,28,32 2006.281.07:30:02.68/vb/04,04,usb,yes,29,29 2006.281.07:30:02.68/vb/05,04,usb,yes,27,31 2006.281.07:30:02.68/vb/06,04,usb,yes,28,31 2006.281.07:30:02.68/vb/07,04,usb,yes,31,31 2006.281.07:30:02.68/vb/08,04,usb,yes,28,31 2006.281.07:30:02.91/vblo/01,632.99,yes,locked 2006.281.07:30:02.91/vblo/02,640.99,yes,locked 2006.281.07:30:02.91/vblo/03,656.99,yes,locked 2006.281.07:30:02.91/vblo/04,712.99,yes,locked 2006.281.07:30:02.91/vblo/05,744.99,yes,locked 2006.281.07:30:02.91/vblo/06,752.99,yes,locked 2006.281.07:30:02.91/vblo/07,734.99,yes,locked 2006.281.07:30:02.91/vblo/08,744.99,yes,locked 2006.281.07:30:03.06/vabw/8 2006.281.07:30:03.21/vbbw/8 2006.281.07:30:03.30/xfe/off,on,12.0 2006.281.07:30:03.67/ifatt/23,28,28,28 2006.281.07:30:03.67&clockoff/"gps-fmout=1p 2006.281.07:30:03.67&clockoff/fmout-gps=1p 2006.281.07:30:04.07/fmout-gps/S +3.13E-07 2006.281.07:30:04.09:!2006.281.07:31:00 2006.281.07:30:37.14#trakl#Off source 2006.281.07:30:37.14?ERROR st -7 Antenna off-source! 2006.281.07:30:37.14#trakl#az 319.303 el 38.223 azerr*cos(el) -0.0001 elerr -0.0180 2006.281.07:30:38.14#flagr#flagr/antenna,off-source 2006.281.07:30:52.14#trakl#Off source 2006.281.07:30:52.14?ERROR st -7 Antenna off-source! 2006.281.07:30:52.14#trakl#az 319.310 el 38.190 azerr*cos(el) 0.0001 elerr -0.0110 2006.281.07:30:53.14#trakl#Source re-acquired 2006.281.07:30:53.14#flagr#flagr/antenna,re-acquired 2006.281.07:31:00.01:data_valid=off 2006.281.07:31:00.01:postob 2006.281.07:31:00.01&postob/cable 2006.281.07:31:00.02&postob/wx 2006.281.07:31:00.02&postob/clockoff 2006.281.07:31:00.10/cable/+6.4870E-03 2006.281.07:31:00.10/wx/21.53,1001.0,48 2006.281.07:31:01.08/fmout-gps/S +3.12E-07 2006.281.07:31:01.08:scan_name=281-0733,k06281,60 2006.281.07:31:01.08:source=0133+476,013658.59,475129.1,2000.0,cw 2006.281.07:31:01.15#flagr#flagr/antenna,new-source 2006.281.07:31:02.14:checkk5 2006.281.07:31:02.14&checkk5/chk_autoobs=1 2006.281.07:31:02.14&checkk5/chk_autoobs=2 2006.281.07:31:02.15&checkk5/chk_autoobs=3 2006.281.07:31:02.15&checkk5/chk_autoobs=4 2006.281.07:31:02.15&checkk5/chk_obsdata=1 2006.281.07:31:02.16&checkk5/chk_obsdata=2 2006.281.07:31:02.16&checkk5/chk_obsdata=3 2006.281.07:31:02.16&checkk5/chk_obsdata=4 2006.281.07:31:02.17&checkk5/k5log=1 2006.281.07:31:02.17&checkk5/k5log=2 2006.281.07:31:02.17&checkk5/k5log=3 2006.281.07:31:02.22&checkk5/k5log=4 2006.281.07:31:02.22&checkk5/obsinfo 2006.281.07:31:02.62/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:31:03.07/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:31:03.52/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:31:03.97/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:31:04.40/chk_obsdata//k5ts1/T2810730??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:31:04.80/chk_obsdata//k5ts2/T2810730??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:31:05.21/chk_obsdata//k5ts3/T2810730??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:31:05.84/chk_obsdata//k5ts4/T2810730??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:31:06.70/k5log//k5ts1_log_newline 2006.281.07:31:07.49/k5log//k5ts2_log_newline 2006.281.07:31:08.35/k5log//k5ts3_log_newline 2006.281.07:31:09.11/k5log//k5ts4_log_newline 2006.281.07:31:09.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:31:09.14:4f8m12a=1 2006.281.07:31:09.14$4f8m12a/echo=on 2006.281.07:31:09.14$4f8m12a/pcalon 2006.281.07:31:09.14$pcalon/"no phase cal control is implemented here 2006.281.07:31:09.14$4f8m12a/"tpicd=stop 2006.281.07:31:09.14$4f8m12a/vc4f8 2006.281.07:31:09.14$vc4f8/valo=1,532.99 2006.281.07:31:09.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:31:09.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:31:09.15#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:09.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:09.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:09.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:09.15#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:31:09.15#ibcon#first serial, iclass 19, count 0 2006.281.07:31:09.15#ibcon#enter sib2, iclass 19, count 0 2006.281.07:31:09.15#ibcon#flushed, iclass 19, count 0 2006.281.07:31:09.15#ibcon#about to write, iclass 19, count 0 2006.281.07:31:09.15#ibcon#wrote, iclass 19, count 0 2006.281.07:31:09.15#ibcon#about to read 3, iclass 19, count 0 2006.281.07:31:09.17#ibcon#read 3, iclass 19, count 0 2006.281.07:31:09.17#ibcon#about to read 4, iclass 19, count 0 2006.281.07:31:09.17#ibcon#read 4, iclass 19, count 0 2006.281.07:31:09.17#ibcon#about to read 5, iclass 19, count 0 2006.281.07:31:09.17#ibcon#read 5, iclass 19, count 0 2006.281.07:31:09.17#ibcon#about to read 6, iclass 19, count 0 2006.281.07:31:09.17#ibcon#read 6, iclass 19, count 0 2006.281.07:31:09.17#ibcon#end of sib2, iclass 19, count 0 2006.281.07:31:09.17#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:31:09.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:31:09.17#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:31:09.17#ibcon#*before write, iclass 19, count 0 2006.281.07:31:09.17#ibcon#enter sib2, iclass 19, count 0 2006.281.07:31:09.17#ibcon#flushed, iclass 19, count 0 2006.281.07:31:09.17#ibcon#about to write, iclass 19, count 0 2006.281.07:31:09.17#ibcon#wrote, iclass 19, count 0 2006.281.07:31:09.17#ibcon#about to read 3, iclass 19, count 0 2006.281.07:31:09.22#ibcon#read 3, iclass 19, count 0 2006.281.07:31:09.22#ibcon#about to read 4, iclass 19, count 0 2006.281.07:31:09.22#ibcon#read 4, iclass 19, count 0 2006.281.07:31:09.22#ibcon#about to read 5, iclass 19, count 0 2006.281.07:31:09.22#ibcon#read 5, iclass 19, count 0 2006.281.07:31:09.22#ibcon#about to read 6, iclass 19, count 0 2006.281.07:31:09.22#ibcon#read 6, iclass 19, count 0 2006.281.07:31:09.22#ibcon#end of sib2, iclass 19, count 0 2006.281.07:31:09.22#ibcon#*after write, iclass 19, count 0 2006.281.07:31:09.22#ibcon#*before return 0, iclass 19, count 0 2006.281.07:31:09.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:09.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:09.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:31:09.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:31:09.22$vc4f8/va=1,7 2006.281.07:31:09.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:31:09.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:31:09.22#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:09.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:09.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:09.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:09.22#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:31:09.22#ibcon#first serial, iclass 21, count 2 2006.281.07:31:09.22#ibcon#enter sib2, iclass 21, count 2 2006.281.07:31:09.22#ibcon#flushed, iclass 21, count 2 2006.281.07:31:09.22#ibcon#about to write, iclass 21, count 2 2006.281.07:31:09.22#ibcon#wrote, iclass 21, count 2 2006.281.07:31:09.22#ibcon#about to read 3, iclass 21, count 2 2006.281.07:31:09.24#ibcon#read 3, iclass 21, count 2 2006.281.07:31:09.24#ibcon#about to read 4, iclass 21, count 2 2006.281.07:31:09.24#ibcon#read 4, iclass 21, count 2 2006.281.07:31:09.24#ibcon#about to read 5, iclass 21, count 2 2006.281.07:31:09.24#ibcon#read 5, iclass 21, count 2 2006.281.07:31:09.24#ibcon#about to read 6, iclass 21, count 2 2006.281.07:31:09.24#ibcon#read 6, iclass 21, count 2 2006.281.07:31:09.24#ibcon#end of sib2, iclass 21, count 2 2006.281.07:31:09.24#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:31:09.24#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:31:09.24#ibcon#[25=AT01-07\r\n] 2006.281.07:31:09.24#ibcon#*before write, iclass 21, count 2 2006.281.07:31:09.24#ibcon#enter sib2, iclass 21, count 2 2006.281.07:31:09.24#ibcon#flushed, iclass 21, count 2 2006.281.07:31:09.24#ibcon#about to write, iclass 21, count 2 2006.281.07:31:09.24#ibcon#wrote, iclass 21, count 2 2006.281.07:31:09.24#ibcon#about to read 3, iclass 21, count 2 2006.281.07:31:09.27#ibcon#read 3, iclass 21, count 2 2006.281.07:31:09.27#ibcon#about to read 4, iclass 21, count 2 2006.281.07:31:09.27#ibcon#read 4, iclass 21, count 2 2006.281.07:31:09.27#ibcon#about to read 5, iclass 21, count 2 2006.281.07:31:09.27#ibcon#read 5, iclass 21, count 2 2006.281.07:31:09.27#ibcon#about to read 6, iclass 21, count 2 2006.281.07:31:09.27#ibcon#read 6, iclass 21, count 2 2006.281.07:31:09.27#ibcon#end of sib2, iclass 21, count 2 2006.281.07:31:09.27#ibcon#*after write, iclass 21, count 2 2006.281.07:31:09.27#ibcon#*before return 0, iclass 21, count 2 2006.281.07:31:09.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:09.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:09.27#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:31:09.27#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:09.27#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:09.39#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:09.39#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:09.39#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:31:09.39#ibcon#first serial, iclass 21, count 0 2006.281.07:31:09.39#ibcon#enter sib2, iclass 21, count 0 2006.281.07:31:09.39#ibcon#flushed, iclass 21, count 0 2006.281.07:31:09.39#ibcon#about to write, iclass 21, count 0 2006.281.07:31:09.39#ibcon#wrote, iclass 21, count 0 2006.281.07:31:09.39#ibcon#about to read 3, iclass 21, count 0 2006.281.07:31:09.41#ibcon#read 3, iclass 21, count 0 2006.281.07:31:09.41#ibcon#about to read 4, iclass 21, count 0 2006.281.07:31:09.41#ibcon#read 4, iclass 21, count 0 2006.281.07:31:09.41#ibcon#about to read 5, iclass 21, count 0 2006.281.07:31:09.41#ibcon#read 5, iclass 21, count 0 2006.281.07:31:09.41#ibcon#about to read 6, iclass 21, count 0 2006.281.07:31:09.41#ibcon#read 6, iclass 21, count 0 2006.281.07:31:09.41#ibcon#end of sib2, iclass 21, count 0 2006.281.07:31:09.41#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:31:09.41#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:31:09.41#ibcon#[25=USB\r\n] 2006.281.07:31:09.41#ibcon#*before write, iclass 21, count 0 2006.281.07:31:09.41#ibcon#enter sib2, iclass 21, count 0 2006.281.07:31:09.41#ibcon#flushed, iclass 21, count 0 2006.281.07:31:09.41#ibcon#about to write, iclass 21, count 0 2006.281.07:31:09.41#ibcon#wrote, iclass 21, count 0 2006.281.07:31:09.41#ibcon#about to read 3, iclass 21, count 0 2006.281.07:31:09.44#ibcon#read 3, iclass 21, count 0 2006.281.07:31:09.44#ibcon#about to read 4, iclass 21, count 0 2006.281.07:31:09.44#ibcon#read 4, iclass 21, count 0 2006.281.07:31:09.44#ibcon#about to read 5, iclass 21, count 0 2006.281.07:31:09.44#ibcon#read 5, iclass 21, count 0 2006.281.07:31:09.44#ibcon#about to read 6, iclass 21, count 0 2006.281.07:31:09.44#ibcon#read 6, iclass 21, count 0 2006.281.07:31:09.44#ibcon#end of sib2, iclass 21, count 0 2006.281.07:31:09.44#ibcon#*after write, iclass 21, count 0 2006.281.07:31:09.44#ibcon#*before return 0, iclass 21, count 0 2006.281.07:31:09.44#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:09.44#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:09.44#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:31:09.44#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:31:09.44$vc4f8/valo=2,572.99 2006.281.07:31:09.44#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:31:09.44#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:31:09.44#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:09.44#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:09.44#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:09.44#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:09.44#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:31:09.44#ibcon#first serial, iclass 23, count 0 2006.281.07:31:09.44#ibcon#enter sib2, iclass 23, count 0 2006.281.07:31:09.44#ibcon#flushed, iclass 23, count 0 2006.281.07:31:09.44#ibcon#about to write, iclass 23, count 0 2006.281.07:31:09.44#ibcon#wrote, iclass 23, count 0 2006.281.07:31:09.44#ibcon#about to read 3, iclass 23, count 0 2006.281.07:31:09.46#ibcon#read 3, iclass 23, count 0 2006.281.07:31:09.46#ibcon#about to read 4, iclass 23, count 0 2006.281.07:31:09.46#ibcon#read 4, iclass 23, count 0 2006.281.07:31:09.46#ibcon#about to read 5, iclass 23, count 0 2006.281.07:31:09.46#ibcon#read 5, iclass 23, count 0 2006.281.07:31:09.46#ibcon#about to read 6, iclass 23, count 0 2006.281.07:31:09.46#ibcon#read 6, iclass 23, count 0 2006.281.07:31:09.46#ibcon#end of sib2, iclass 23, count 0 2006.281.07:31:09.46#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:31:09.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:31:09.46#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:31:09.46#ibcon#*before write, iclass 23, count 0 2006.281.07:31:09.46#ibcon#enter sib2, iclass 23, count 0 2006.281.07:31:09.46#ibcon#flushed, iclass 23, count 0 2006.281.07:31:09.46#ibcon#about to write, iclass 23, count 0 2006.281.07:31:09.46#ibcon#wrote, iclass 23, count 0 2006.281.07:31:09.46#ibcon#about to read 3, iclass 23, count 0 2006.281.07:31:09.50#ibcon#read 3, iclass 23, count 0 2006.281.07:31:09.50#ibcon#about to read 4, iclass 23, count 0 2006.281.07:31:09.50#ibcon#read 4, iclass 23, count 0 2006.281.07:31:09.50#ibcon#about to read 5, iclass 23, count 0 2006.281.07:31:09.50#ibcon#read 5, iclass 23, count 0 2006.281.07:31:09.50#ibcon#about to read 6, iclass 23, count 0 2006.281.07:31:09.50#ibcon#read 6, iclass 23, count 0 2006.281.07:31:09.50#ibcon#end of sib2, iclass 23, count 0 2006.281.07:31:09.50#ibcon#*after write, iclass 23, count 0 2006.281.07:31:09.50#ibcon#*before return 0, iclass 23, count 0 2006.281.07:31:09.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:09.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:09.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:31:09.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:31:09.50$vc4f8/va=2,6 2006.281.07:31:09.50#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:31:09.50#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:31:09.50#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:09.50#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:09.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:09.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:09.56#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:31:09.56#ibcon#first serial, iclass 25, count 2 2006.281.07:31:09.56#ibcon#enter sib2, iclass 25, count 2 2006.281.07:31:09.56#ibcon#flushed, iclass 25, count 2 2006.281.07:31:09.56#ibcon#about to write, iclass 25, count 2 2006.281.07:31:09.56#ibcon#wrote, iclass 25, count 2 2006.281.07:31:09.56#ibcon#about to read 3, iclass 25, count 2 2006.281.07:31:09.58#ibcon#read 3, iclass 25, count 2 2006.281.07:31:09.58#ibcon#about to read 4, iclass 25, count 2 2006.281.07:31:09.58#ibcon#read 4, iclass 25, count 2 2006.281.07:31:09.58#ibcon#about to read 5, iclass 25, count 2 2006.281.07:31:09.58#ibcon#read 5, iclass 25, count 2 2006.281.07:31:09.58#ibcon#about to read 6, iclass 25, count 2 2006.281.07:31:09.58#ibcon#read 6, iclass 25, count 2 2006.281.07:31:09.58#ibcon#end of sib2, iclass 25, count 2 2006.281.07:31:09.58#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:31:09.58#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:31:09.58#ibcon#[25=AT02-06\r\n] 2006.281.07:31:09.58#ibcon#*before write, iclass 25, count 2 2006.281.07:31:09.58#ibcon#enter sib2, iclass 25, count 2 2006.281.07:31:09.58#ibcon#flushed, iclass 25, count 2 2006.281.07:31:09.58#ibcon#about to write, iclass 25, count 2 2006.281.07:31:09.58#ibcon#wrote, iclass 25, count 2 2006.281.07:31:09.58#ibcon#about to read 3, iclass 25, count 2 2006.281.07:31:09.62#ibcon#read 3, iclass 25, count 2 2006.281.07:31:09.62#ibcon#about to read 4, iclass 25, count 2 2006.281.07:31:09.62#ibcon#read 4, iclass 25, count 2 2006.281.07:31:09.62#ibcon#about to read 5, iclass 25, count 2 2006.281.07:31:09.62#ibcon#read 5, iclass 25, count 2 2006.281.07:31:09.62#ibcon#about to read 6, iclass 25, count 2 2006.281.07:31:09.62#ibcon#read 6, iclass 25, count 2 2006.281.07:31:09.62#ibcon#end of sib2, iclass 25, count 2 2006.281.07:31:09.62#ibcon#*after write, iclass 25, count 2 2006.281.07:31:09.62#ibcon#*before return 0, iclass 25, count 2 2006.281.07:31:09.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:09.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:09.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:31:09.62#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:09.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:09.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:09.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:09.74#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:31:09.74#ibcon#first serial, iclass 25, count 0 2006.281.07:31:09.74#ibcon#enter sib2, iclass 25, count 0 2006.281.07:31:09.74#ibcon#flushed, iclass 25, count 0 2006.281.07:31:09.74#ibcon#about to write, iclass 25, count 0 2006.281.07:31:09.74#ibcon#wrote, iclass 25, count 0 2006.281.07:31:09.74#ibcon#about to read 3, iclass 25, count 0 2006.281.07:31:09.76#ibcon#read 3, iclass 25, count 0 2006.281.07:31:09.76#ibcon#about to read 4, iclass 25, count 0 2006.281.07:31:09.76#ibcon#read 4, iclass 25, count 0 2006.281.07:31:09.76#ibcon#about to read 5, iclass 25, count 0 2006.281.07:31:09.76#ibcon#read 5, iclass 25, count 0 2006.281.07:31:09.76#ibcon#about to read 6, iclass 25, count 0 2006.281.07:31:09.76#ibcon#read 6, iclass 25, count 0 2006.281.07:31:09.76#ibcon#end of sib2, iclass 25, count 0 2006.281.07:31:09.76#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:31:09.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:31:09.76#ibcon#[25=USB\r\n] 2006.281.07:31:09.76#ibcon#*before write, iclass 25, count 0 2006.281.07:31:09.76#ibcon#enter sib2, iclass 25, count 0 2006.281.07:31:09.76#ibcon#flushed, iclass 25, count 0 2006.281.07:31:09.76#ibcon#about to write, iclass 25, count 0 2006.281.07:31:09.76#ibcon#wrote, iclass 25, count 0 2006.281.07:31:09.76#ibcon#about to read 3, iclass 25, count 0 2006.281.07:31:09.79#ibcon#read 3, iclass 25, count 0 2006.281.07:31:09.79#ibcon#about to read 4, iclass 25, count 0 2006.281.07:31:09.79#ibcon#read 4, iclass 25, count 0 2006.281.07:31:09.79#ibcon#about to read 5, iclass 25, count 0 2006.281.07:31:09.79#ibcon#read 5, iclass 25, count 0 2006.281.07:31:09.79#ibcon#about to read 6, iclass 25, count 0 2006.281.07:31:09.79#ibcon#read 6, iclass 25, count 0 2006.281.07:31:09.79#ibcon#end of sib2, iclass 25, count 0 2006.281.07:31:09.79#ibcon#*after write, iclass 25, count 0 2006.281.07:31:09.79#ibcon#*before return 0, iclass 25, count 0 2006.281.07:31:09.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:09.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:09.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:31:09.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:31:09.79$vc4f8/valo=3,672.99 2006.281.07:31:09.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:31:09.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:31:09.79#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:09.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:09.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:09.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:09.79#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:31:09.79#ibcon#first serial, iclass 27, count 0 2006.281.07:31:09.79#ibcon#enter sib2, iclass 27, count 0 2006.281.07:31:09.79#ibcon#flushed, iclass 27, count 0 2006.281.07:31:09.79#ibcon#about to write, iclass 27, count 0 2006.281.07:31:09.79#ibcon#wrote, iclass 27, count 0 2006.281.07:31:09.79#ibcon#about to read 3, iclass 27, count 0 2006.281.07:31:09.81#ibcon#read 3, iclass 27, count 0 2006.281.07:31:09.81#ibcon#about to read 4, iclass 27, count 0 2006.281.07:31:09.81#ibcon#read 4, iclass 27, count 0 2006.281.07:31:09.81#ibcon#about to read 5, iclass 27, count 0 2006.281.07:31:09.81#ibcon#read 5, iclass 27, count 0 2006.281.07:31:09.81#ibcon#about to read 6, iclass 27, count 0 2006.281.07:31:09.81#ibcon#read 6, iclass 27, count 0 2006.281.07:31:09.81#ibcon#end of sib2, iclass 27, count 0 2006.281.07:31:09.81#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:31:09.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:31:09.81#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:31:09.81#ibcon#*before write, iclass 27, count 0 2006.281.07:31:09.81#ibcon#enter sib2, iclass 27, count 0 2006.281.07:31:09.81#ibcon#flushed, iclass 27, count 0 2006.281.07:31:09.81#ibcon#about to write, iclass 27, count 0 2006.281.07:31:09.81#ibcon#wrote, iclass 27, count 0 2006.281.07:31:09.81#ibcon#about to read 3, iclass 27, count 0 2006.281.07:31:09.85#ibcon#read 3, iclass 27, count 0 2006.281.07:31:09.85#ibcon#about to read 4, iclass 27, count 0 2006.281.07:31:09.85#ibcon#read 4, iclass 27, count 0 2006.281.07:31:09.85#ibcon#about to read 5, iclass 27, count 0 2006.281.07:31:09.85#ibcon#read 5, iclass 27, count 0 2006.281.07:31:09.85#ibcon#about to read 6, iclass 27, count 0 2006.281.07:31:09.85#ibcon#read 6, iclass 27, count 0 2006.281.07:31:09.85#ibcon#end of sib2, iclass 27, count 0 2006.281.07:31:09.85#ibcon#*after write, iclass 27, count 0 2006.281.07:31:09.85#ibcon#*before return 0, iclass 27, count 0 2006.281.07:31:09.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:09.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:09.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:31:09.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:31:09.85$vc4f8/va=3,6 2006.281.07:31:09.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:31:09.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:31:09.86#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:09.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:09.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:09.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:09.91#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:31:09.91#ibcon#first serial, iclass 29, count 2 2006.281.07:31:09.91#ibcon#enter sib2, iclass 29, count 2 2006.281.07:31:09.91#ibcon#flushed, iclass 29, count 2 2006.281.07:31:09.91#ibcon#about to write, iclass 29, count 2 2006.281.07:31:09.91#ibcon#wrote, iclass 29, count 2 2006.281.07:31:09.91#ibcon#about to read 3, iclass 29, count 2 2006.281.07:31:09.93#ibcon#read 3, iclass 29, count 2 2006.281.07:31:09.93#ibcon#about to read 4, iclass 29, count 2 2006.281.07:31:09.93#ibcon#read 4, iclass 29, count 2 2006.281.07:31:09.93#ibcon#about to read 5, iclass 29, count 2 2006.281.07:31:09.93#ibcon#read 5, iclass 29, count 2 2006.281.07:31:09.93#ibcon#about to read 6, iclass 29, count 2 2006.281.07:31:09.93#ibcon#read 6, iclass 29, count 2 2006.281.07:31:09.93#ibcon#end of sib2, iclass 29, count 2 2006.281.07:31:09.93#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:31:09.93#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:31:09.93#ibcon#[25=AT03-06\r\n] 2006.281.07:31:09.93#ibcon#*before write, iclass 29, count 2 2006.281.07:31:09.93#ibcon#enter sib2, iclass 29, count 2 2006.281.07:31:09.93#ibcon#flushed, iclass 29, count 2 2006.281.07:31:09.93#ibcon#about to write, iclass 29, count 2 2006.281.07:31:09.93#ibcon#wrote, iclass 29, count 2 2006.281.07:31:09.93#ibcon#about to read 3, iclass 29, count 2 2006.281.07:31:09.96#ibcon#read 3, iclass 29, count 2 2006.281.07:31:09.96#ibcon#about to read 4, iclass 29, count 2 2006.281.07:31:09.96#ibcon#read 4, iclass 29, count 2 2006.281.07:31:09.96#ibcon#about to read 5, iclass 29, count 2 2006.281.07:31:09.96#ibcon#read 5, iclass 29, count 2 2006.281.07:31:09.96#ibcon#about to read 6, iclass 29, count 2 2006.281.07:31:09.96#ibcon#read 6, iclass 29, count 2 2006.281.07:31:09.96#ibcon#end of sib2, iclass 29, count 2 2006.281.07:31:09.96#ibcon#*after write, iclass 29, count 2 2006.281.07:31:09.96#ibcon#*before return 0, iclass 29, count 2 2006.281.07:31:09.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:09.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:09.96#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:31:09.96#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:09.96#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:10.08#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:10.08#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:10.08#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:31:10.08#ibcon#first serial, iclass 29, count 0 2006.281.07:31:10.08#ibcon#enter sib2, iclass 29, count 0 2006.281.07:31:10.08#ibcon#flushed, iclass 29, count 0 2006.281.07:31:10.08#ibcon#about to write, iclass 29, count 0 2006.281.07:31:10.08#ibcon#wrote, iclass 29, count 0 2006.281.07:31:10.08#ibcon#about to read 3, iclass 29, count 0 2006.281.07:31:10.10#ibcon#read 3, iclass 29, count 0 2006.281.07:31:10.10#ibcon#about to read 4, iclass 29, count 0 2006.281.07:31:10.10#ibcon#read 4, iclass 29, count 0 2006.281.07:31:10.10#ibcon#about to read 5, iclass 29, count 0 2006.281.07:31:10.10#ibcon#read 5, iclass 29, count 0 2006.281.07:31:10.10#ibcon#about to read 6, iclass 29, count 0 2006.281.07:31:10.10#ibcon#read 6, iclass 29, count 0 2006.281.07:31:10.10#ibcon#end of sib2, iclass 29, count 0 2006.281.07:31:10.10#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:31:10.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:31:10.10#ibcon#[25=USB\r\n] 2006.281.07:31:10.10#ibcon#*before write, iclass 29, count 0 2006.281.07:31:10.10#ibcon#enter sib2, iclass 29, count 0 2006.281.07:31:10.10#ibcon#flushed, iclass 29, count 0 2006.281.07:31:10.10#ibcon#about to write, iclass 29, count 0 2006.281.07:31:10.10#ibcon#wrote, iclass 29, count 0 2006.281.07:31:10.10#ibcon#about to read 3, iclass 29, count 0 2006.281.07:31:10.13#ibcon#read 3, iclass 29, count 0 2006.281.07:31:10.13#ibcon#about to read 4, iclass 29, count 0 2006.281.07:31:10.13#ibcon#read 4, iclass 29, count 0 2006.281.07:31:10.13#ibcon#about to read 5, iclass 29, count 0 2006.281.07:31:10.13#ibcon#read 5, iclass 29, count 0 2006.281.07:31:10.13#ibcon#about to read 6, iclass 29, count 0 2006.281.07:31:10.13#ibcon#read 6, iclass 29, count 0 2006.281.07:31:10.13#ibcon#end of sib2, iclass 29, count 0 2006.281.07:31:10.13#ibcon#*after write, iclass 29, count 0 2006.281.07:31:10.13#ibcon#*before return 0, iclass 29, count 0 2006.281.07:31:10.13#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:10.13#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:10.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:31:10.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:31:10.13$vc4f8/valo=4,832.99 2006.281.07:31:10.13#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:31:10.13#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:31:10.13#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:10.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:10.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:10.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:10.13#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:31:10.13#ibcon#first serial, iclass 31, count 0 2006.281.07:31:10.13#ibcon#enter sib2, iclass 31, count 0 2006.281.07:31:10.13#ibcon#flushed, iclass 31, count 0 2006.281.07:31:10.13#ibcon#about to write, iclass 31, count 0 2006.281.07:31:10.13#ibcon#wrote, iclass 31, count 0 2006.281.07:31:10.13#ibcon#about to read 3, iclass 31, count 0 2006.281.07:31:10.15#ibcon#read 3, iclass 31, count 0 2006.281.07:31:10.15#ibcon#about to read 4, iclass 31, count 0 2006.281.07:31:10.15#ibcon#read 4, iclass 31, count 0 2006.281.07:31:10.15#ibcon#about to read 5, iclass 31, count 0 2006.281.07:31:10.15#ibcon#read 5, iclass 31, count 0 2006.281.07:31:10.15#ibcon#about to read 6, iclass 31, count 0 2006.281.07:31:10.15#ibcon#read 6, iclass 31, count 0 2006.281.07:31:10.15#ibcon#end of sib2, iclass 31, count 0 2006.281.07:31:10.15#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:31:10.15#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:31:10.15#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:31:10.15#ibcon#*before write, iclass 31, count 0 2006.281.07:31:10.15#ibcon#enter sib2, iclass 31, count 0 2006.281.07:31:10.15#ibcon#flushed, iclass 31, count 0 2006.281.07:31:10.15#ibcon#about to write, iclass 31, count 0 2006.281.07:31:10.15#ibcon#wrote, iclass 31, count 0 2006.281.07:31:10.15#ibcon#about to read 3, iclass 31, count 0 2006.281.07:31:10.20#ibcon#read 3, iclass 31, count 0 2006.281.07:31:10.20#ibcon#about to read 4, iclass 31, count 0 2006.281.07:31:10.20#ibcon#read 4, iclass 31, count 0 2006.281.07:31:10.20#ibcon#about to read 5, iclass 31, count 0 2006.281.07:31:10.20#ibcon#read 5, iclass 31, count 0 2006.281.07:31:10.20#ibcon#about to read 6, iclass 31, count 0 2006.281.07:31:10.20#ibcon#read 6, iclass 31, count 0 2006.281.07:31:10.20#ibcon#end of sib2, iclass 31, count 0 2006.281.07:31:10.20#ibcon#*after write, iclass 31, count 0 2006.281.07:31:10.20#ibcon#*before return 0, iclass 31, count 0 2006.281.07:31:10.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:10.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:10.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:31:10.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:31:10.20$vc4f8/va=4,6 2006.281.07:31:10.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:31:10.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:31:10.20#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:10.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:10.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:10.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:10.25#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:31:10.25#ibcon#first serial, iclass 33, count 2 2006.281.07:31:10.25#ibcon#enter sib2, iclass 33, count 2 2006.281.07:31:10.25#ibcon#flushed, iclass 33, count 2 2006.281.07:31:10.25#ibcon#about to write, iclass 33, count 2 2006.281.07:31:10.25#ibcon#wrote, iclass 33, count 2 2006.281.07:31:10.25#ibcon#about to read 3, iclass 33, count 2 2006.281.07:31:10.27#ibcon#read 3, iclass 33, count 2 2006.281.07:31:10.27#ibcon#about to read 4, iclass 33, count 2 2006.281.07:31:10.27#ibcon#read 4, iclass 33, count 2 2006.281.07:31:10.27#ibcon#about to read 5, iclass 33, count 2 2006.281.07:31:10.27#ibcon#read 5, iclass 33, count 2 2006.281.07:31:10.27#ibcon#about to read 6, iclass 33, count 2 2006.281.07:31:10.27#ibcon#read 6, iclass 33, count 2 2006.281.07:31:10.27#ibcon#end of sib2, iclass 33, count 2 2006.281.07:31:10.27#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:31:10.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:31:10.27#ibcon#[25=AT04-06\r\n] 2006.281.07:31:10.27#ibcon#*before write, iclass 33, count 2 2006.281.07:31:10.27#ibcon#enter sib2, iclass 33, count 2 2006.281.07:31:10.27#ibcon#flushed, iclass 33, count 2 2006.281.07:31:10.27#ibcon#about to write, iclass 33, count 2 2006.281.07:31:10.27#ibcon#wrote, iclass 33, count 2 2006.281.07:31:10.27#ibcon#about to read 3, iclass 33, count 2 2006.281.07:31:10.30#ibcon#read 3, iclass 33, count 2 2006.281.07:31:10.30#ibcon#about to read 4, iclass 33, count 2 2006.281.07:31:10.30#ibcon#read 4, iclass 33, count 2 2006.281.07:31:10.30#ibcon#about to read 5, iclass 33, count 2 2006.281.07:31:10.30#ibcon#read 5, iclass 33, count 2 2006.281.07:31:10.30#ibcon#about to read 6, iclass 33, count 2 2006.281.07:31:10.30#ibcon#read 6, iclass 33, count 2 2006.281.07:31:10.30#ibcon#end of sib2, iclass 33, count 2 2006.281.07:31:10.30#ibcon#*after write, iclass 33, count 2 2006.281.07:31:10.30#ibcon#*before return 0, iclass 33, count 2 2006.281.07:31:10.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:10.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:10.30#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:31:10.30#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:10.30#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:10.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:10.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:10.42#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:31:10.42#ibcon#first serial, iclass 33, count 0 2006.281.07:31:10.42#ibcon#enter sib2, iclass 33, count 0 2006.281.07:31:10.42#ibcon#flushed, iclass 33, count 0 2006.281.07:31:10.42#ibcon#about to write, iclass 33, count 0 2006.281.07:31:10.42#ibcon#wrote, iclass 33, count 0 2006.281.07:31:10.42#ibcon#about to read 3, iclass 33, count 0 2006.281.07:31:10.44#ibcon#read 3, iclass 33, count 0 2006.281.07:31:10.44#ibcon#about to read 4, iclass 33, count 0 2006.281.07:31:10.44#ibcon#read 4, iclass 33, count 0 2006.281.07:31:10.44#ibcon#about to read 5, iclass 33, count 0 2006.281.07:31:10.44#ibcon#read 5, iclass 33, count 0 2006.281.07:31:10.44#ibcon#about to read 6, iclass 33, count 0 2006.281.07:31:10.44#ibcon#read 6, iclass 33, count 0 2006.281.07:31:10.44#ibcon#end of sib2, iclass 33, count 0 2006.281.07:31:10.44#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:31:10.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:31:10.44#ibcon#[25=USB\r\n] 2006.281.07:31:10.44#ibcon#*before write, iclass 33, count 0 2006.281.07:31:10.44#ibcon#enter sib2, iclass 33, count 0 2006.281.07:31:10.44#ibcon#flushed, iclass 33, count 0 2006.281.07:31:10.44#ibcon#about to write, iclass 33, count 0 2006.281.07:31:10.44#ibcon#wrote, iclass 33, count 0 2006.281.07:31:10.44#ibcon#about to read 3, iclass 33, count 0 2006.281.07:31:10.47#ibcon#read 3, iclass 33, count 0 2006.281.07:31:10.47#ibcon#about to read 4, iclass 33, count 0 2006.281.07:31:10.47#ibcon#read 4, iclass 33, count 0 2006.281.07:31:10.47#ibcon#about to read 5, iclass 33, count 0 2006.281.07:31:10.47#ibcon#read 5, iclass 33, count 0 2006.281.07:31:10.47#ibcon#about to read 6, iclass 33, count 0 2006.281.07:31:10.47#ibcon#read 6, iclass 33, count 0 2006.281.07:31:10.47#ibcon#end of sib2, iclass 33, count 0 2006.281.07:31:10.47#ibcon#*after write, iclass 33, count 0 2006.281.07:31:10.47#ibcon#*before return 0, iclass 33, count 0 2006.281.07:31:10.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:10.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:10.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:31:10.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:31:10.47$vc4f8/valo=5,652.99 2006.281.07:31:10.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:31:10.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:31:10.47#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:10.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:10.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:10.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:10.47#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:31:10.47#ibcon#first serial, iclass 35, count 0 2006.281.07:31:10.47#ibcon#enter sib2, iclass 35, count 0 2006.281.07:31:10.47#ibcon#flushed, iclass 35, count 0 2006.281.07:31:10.47#ibcon#about to write, iclass 35, count 0 2006.281.07:31:10.47#ibcon#wrote, iclass 35, count 0 2006.281.07:31:10.47#ibcon#about to read 3, iclass 35, count 0 2006.281.07:31:10.49#ibcon#read 3, iclass 35, count 0 2006.281.07:31:10.49#ibcon#about to read 4, iclass 35, count 0 2006.281.07:31:10.49#ibcon#read 4, iclass 35, count 0 2006.281.07:31:10.49#ibcon#about to read 5, iclass 35, count 0 2006.281.07:31:10.49#ibcon#read 5, iclass 35, count 0 2006.281.07:31:10.49#ibcon#about to read 6, iclass 35, count 0 2006.281.07:31:10.49#ibcon#read 6, iclass 35, count 0 2006.281.07:31:10.49#ibcon#end of sib2, iclass 35, count 0 2006.281.07:31:10.49#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:31:10.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:31:10.49#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:31:10.49#ibcon#*before write, iclass 35, count 0 2006.281.07:31:10.49#ibcon#enter sib2, iclass 35, count 0 2006.281.07:31:10.49#ibcon#flushed, iclass 35, count 0 2006.281.07:31:10.49#ibcon#about to write, iclass 35, count 0 2006.281.07:31:10.49#ibcon#wrote, iclass 35, count 0 2006.281.07:31:10.49#ibcon#about to read 3, iclass 35, count 0 2006.281.07:31:10.53#ibcon#read 3, iclass 35, count 0 2006.281.07:31:10.53#ibcon#about to read 4, iclass 35, count 0 2006.281.07:31:10.53#ibcon#read 4, iclass 35, count 0 2006.281.07:31:10.53#ibcon#about to read 5, iclass 35, count 0 2006.281.07:31:10.53#ibcon#read 5, iclass 35, count 0 2006.281.07:31:10.53#ibcon#about to read 6, iclass 35, count 0 2006.281.07:31:10.53#ibcon#read 6, iclass 35, count 0 2006.281.07:31:10.53#ibcon#end of sib2, iclass 35, count 0 2006.281.07:31:10.53#ibcon#*after write, iclass 35, count 0 2006.281.07:31:10.53#ibcon#*before return 0, iclass 35, count 0 2006.281.07:31:10.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:10.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:10.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:31:10.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:31:10.53$vc4f8/va=5,7 2006.281.07:31:10.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:31:10.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:31:10.53#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:10.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:10.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:10.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:10.59#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:31:10.59#ibcon#first serial, iclass 37, count 2 2006.281.07:31:10.59#ibcon#enter sib2, iclass 37, count 2 2006.281.07:31:10.59#ibcon#flushed, iclass 37, count 2 2006.281.07:31:10.59#ibcon#about to write, iclass 37, count 2 2006.281.07:31:10.59#ibcon#wrote, iclass 37, count 2 2006.281.07:31:10.59#ibcon#about to read 3, iclass 37, count 2 2006.281.07:31:10.61#ibcon#read 3, iclass 37, count 2 2006.281.07:31:10.61#ibcon#about to read 4, iclass 37, count 2 2006.281.07:31:10.61#ibcon#read 4, iclass 37, count 2 2006.281.07:31:10.61#ibcon#about to read 5, iclass 37, count 2 2006.281.07:31:10.61#ibcon#read 5, iclass 37, count 2 2006.281.07:31:10.61#ibcon#about to read 6, iclass 37, count 2 2006.281.07:31:10.61#ibcon#read 6, iclass 37, count 2 2006.281.07:31:10.61#ibcon#end of sib2, iclass 37, count 2 2006.281.07:31:10.61#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:31:10.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:31:10.61#ibcon#[25=AT05-07\r\n] 2006.281.07:31:10.61#ibcon#*before write, iclass 37, count 2 2006.281.07:31:10.61#ibcon#enter sib2, iclass 37, count 2 2006.281.07:31:10.61#ibcon#flushed, iclass 37, count 2 2006.281.07:31:10.61#ibcon#about to write, iclass 37, count 2 2006.281.07:31:10.61#ibcon#wrote, iclass 37, count 2 2006.281.07:31:10.61#ibcon#about to read 3, iclass 37, count 2 2006.281.07:31:10.64#ibcon#read 3, iclass 37, count 2 2006.281.07:31:10.64#ibcon#about to read 4, iclass 37, count 2 2006.281.07:31:10.64#ibcon#read 4, iclass 37, count 2 2006.281.07:31:10.64#ibcon#about to read 5, iclass 37, count 2 2006.281.07:31:10.64#ibcon#read 5, iclass 37, count 2 2006.281.07:31:10.64#ibcon#about to read 6, iclass 37, count 2 2006.281.07:31:10.64#ibcon#read 6, iclass 37, count 2 2006.281.07:31:10.64#ibcon#end of sib2, iclass 37, count 2 2006.281.07:31:10.64#ibcon#*after write, iclass 37, count 2 2006.281.07:31:10.64#ibcon#*before return 0, iclass 37, count 2 2006.281.07:31:10.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:10.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:10.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:31:10.64#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:10.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:10.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:10.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:10.76#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:31:10.76#ibcon#first serial, iclass 37, count 0 2006.281.07:31:10.76#ibcon#enter sib2, iclass 37, count 0 2006.281.07:31:10.76#ibcon#flushed, iclass 37, count 0 2006.281.07:31:10.76#ibcon#about to write, iclass 37, count 0 2006.281.07:31:10.76#ibcon#wrote, iclass 37, count 0 2006.281.07:31:10.76#ibcon#about to read 3, iclass 37, count 0 2006.281.07:31:10.78#ibcon#read 3, iclass 37, count 0 2006.281.07:31:10.78#ibcon#about to read 4, iclass 37, count 0 2006.281.07:31:10.78#ibcon#read 4, iclass 37, count 0 2006.281.07:31:10.78#ibcon#about to read 5, iclass 37, count 0 2006.281.07:31:10.78#ibcon#read 5, iclass 37, count 0 2006.281.07:31:10.78#ibcon#about to read 6, iclass 37, count 0 2006.281.07:31:10.78#ibcon#read 6, iclass 37, count 0 2006.281.07:31:10.78#ibcon#end of sib2, iclass 37, count 0 2006.281.07:31:10.78#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:31:10.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:31:10.78#ibcon#[25=USB\r\n] 2006.281.07:31:10.78#ibcon#*before write, iclass 37, count 0 2006.281.07:31:10.78#ibcon#enter sib2, iclass 37, count 0 2006.281.07:31:10.78#ibcon#flushed, iclass 37, count 0 2006.281.07:31:10.78#ibcon#about to write, iclass 37, count 0 2006.281.07:31:10.78#ibcon#wrote, iclass 37, count 0 2006.281.07:31:10.78#ibcon#about to read 3, iclass 37, count 0 2006.281.07:31:10.81#ibcon#read 3, iclass 37, count 0 2006.281.07:31:10.81#ibcon#about to read 4, iclass 37, count 0 2006.281.07:31:10.81#ibcon#read 4, iclass 37, count 0 2006.281.07:31:10.81#ibcon#about to read 5, iclass 37, count 0 2006.281.07:31:10.81#ibcon#read 5, iclass 37, count 0 2006.281.07:31:10.81#ibcon#about to read 6, iclass 37, count 0 2006.281.07:31:10.81#ibcon#read 6, iclass 37, count 0 2006.281.07:31:10.81#ibcon#end of sib2, iclass 37, count 0 2006.281.07:31:10.81#ibcon#*after write, iclass 37, count 0 2006.281.07:31:10.81#ibcon#*before return 0, iclass 37, count 0 2006.281.07:31:10.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:10.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:10.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:31:10.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:31:10.81$vc4f8/valo=6,772.99 2006.281.07:31:10.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:31:10.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:31:10.81#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:10.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:10.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:10.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:10.81#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:31:10.81#ibcon#first serial, iclass 39, count 0 2006.281.07:31:10.81#ibcon#enter sib2, iclass 39, count 0 2006.281.07:31:10.81#ibcon#flushed, iclass 39, count 0 2006.281.07:31:10.81#ibcon#about to write, iclass 39, count 0 2006.281.07:31:10.81#ibcon#wrote, iclass 39, count 0 2006.281.07:31:10.81#ibcon#about to read 3, iclass 39, count 0 2006.281.07:31:10.83#ibcon#read 3, iclass 39, count 0 2006.281.07:31:10.83#ibcon#about to read 4, iclass 39, count 0 2006.281.07:31:10.83#ibcon#read 4, iclass 39, count 0 2006.281.07:31:10.83#ibcon#about to read 5, iclass 39, count 0 2006.281.07:31:10.83#ibcon#read 5, iclass 39, count 0 2006.281.07:31:10.83#ibcon#about to read 6, iclass 39, count 0 2006.281.07:31:10.83#ibcon#read 6, iclass 39, count 0 2006.281.07:31:10.83#ibcon#end of sib2, iclass 39, count 0 2006.281.07:31:10.83#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:31:10.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:31:10.83#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:31:10.83#ibcon#*before write, iclass 39, count 0 2006.281.07:31:10.83#ibcon#enter sib2, iclass 39, count 0 2006.281.07:31:10.83#ibcon#flushed, iclass 39, count 0 2006.281.07:31:10.83#ibcon#about to write, iclass 39, count 0 2006.281.07:31:10.83#ibcon#wrote, iclass 39, count 0 2006.281.07:31:10.83#ibcon#about to read 3, iclass 39, count 0 2006.281.07:31:10.87#ibcon#read 3, iclass 39, count 0 2006.281.07:31:10.87#ibcon#about to read 4, iclass 39, count 0 2006.281.07:31:10.87#ibcon#read 4, iclass 39, count 0 2006.281.07:31:10.87#ibcon#about to read 5, iclass 39, count 0 2006.281.07:31:10.87#ibcon#read 5, iclass 39, count 0 2006.281.07:31:10.87#ibcon#about to read 6, iclass 39, count 0 2006.281.07:31:10.87#ibcon#read 6, iclass 39, count 0 2006.281.07:31:10.87#ibcon#end of sib2, iclass 39, count 0 2006.281.07:31:10.87#ibcon#*after write, iclass 39, count 0 2006.281.07:31:10.87#ibcon#*before return 0, iclass 39, count 0 2006.281.07:31:10.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:10.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:10.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:31:10.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:31:10.87$vc4f8/va=6,6 2006.281.07:31:10.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:31:10.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:31:10.88#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:10.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:10.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:10.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:10.93#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:31:10.93#ibcon#first serial, iclass 3, count 2 2006.281.07:31:10.93#ibcon#enter sib2, iclass 3, count 2 2006.281.07:31:10.93#ibcon#flushed, iclass 3, count 2 2006.281.07:31:10.93#ibcon#about to write, iclass 3, count 2 2006.281.07:31:10.93#ibcon#wrote, iclass 3, count 2 2006.281.07:31:10.93#ibcon#about to read 3, iclass 3, count 2 2006.281.07:31:10.95#ibcon#read 3, iclass 3, count 2 2006.281.07:31:10.95#ibcon#about to read 4, iclass 3, count 2 2006.281.07:31:10.95#ibcon#read 4, iclass 3, count 2 2006.281.07:31:10.95#ibcon#about to read 5, iclass 3, count 2 2006.281.07:31:10.95#ibcon#read 5, iclass 3, count 2 2006.281.07:31:10.95#ibcon#about to read 6, iclass 3, count 2 2006.281.07:31:10.95#ibcon#read 6, iclass 3, count 2 2006.281.07:31:10.95#ibcon#end of sib2, iclass 3, count 2 2006.281.07:31:10.95#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:31:10.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:31:10.95#ibcon#[25=AT06-06\r\n] 2006.281.07:31:10.95#ibcon#*before write, iclass 3, count 2 2006.281.07:31:10.95#ibcon#enter sib2, iclass 3, count 2 2006.281.07:31:10.95#ibcon#flushed, iclass 3, count 2 2006.281.07:31:10.95#ibcon#about to write, iclass 3, count 2 2006.281.07:31:10.95#ibcon#wrote, iclass 3, count 2 2006.281.07:31:10.95#ibcon#about to read 3, iclass 3, count 2 2006.281.07:31:10.98#ibcon#read 3, iclass 3, count 2 2006.281.07:31:10.98#ibcon#about to read 4, iclass 3, count 2 2006.281.07:31:10.98#ibcon#read 4, iclass 3, count 2 2006.281.07:31:10.98#ibcon#about to read 5, iclass 3, count 2 2006.281.07:31:10.98#ibcon#read 5, iclass 3, count 2 2006.281.07:31:10.98#ibcon#about to read 6, iclass 3, count 2 2006.281.07:31:10.98#ibcon#read 6, iclass 3, count 2 2006.281.07:31:10.98#ibcon#end of sib2, iclass 3, count 2 2006.281.07:31:10.98#ibcon#*after write, iclass 3, count 2 2006.281.07:31:10.98#ibcon#*before return 0, iclass 3, count 2 2006.281.07:31:10.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:10.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:10.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:31:10.98#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:10.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:31:11.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:31:11.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:31:11.10#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:31:11.10#ibcon#first serial, iclass 3, count 0 2006.281.07:31:11.10#ibcon#enter sib2, iclass 3, count 0 2006.281.07:31:11.10#ibcon#flushed, iclass 3, count 0 2006.281.07:31:11.10#ibcon#about to write, iclass 3, count 0 2006.281.07:31:11.10#ibcon#wrote, iclass 3, count 0 2006.281.07:31:11.10#ibcon#about to read 3, iclass 3, count 0 2006.281.07:31:11.12#ibcon#read 3, iclass 3, count 0 2006.281.07:31:11.12#ibcon#about to read 4, iclass 3, count 0 2006.281.07:31:11.12#ibcon#read 4, iclass 3, count 0 2006.281.07:31:11.12#ibcon#about to read 5, iclass 3, count 0 2006.281.07:31:11.12#ibcon#read 5, iclass 3, count 0 2006.281.07:31:11.12#ibcon#about to read 6, iclass 3, count 0 2006.281.07:31:11.12#ibcon#read 6, iclass 3, count 0 2006.281.07:31:11.12#ibcon#end of sib2, iclass 3, count 0 2006.281.07:31:11.12#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:31:11.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:31:11.12#ibcon#[25=USB\r\n] 2006.281.07:31:11.12#ibcon#*before write, iclass 3, count 0 2006.281.07:31:11.12#ibcon#enter sib2, iclass 3, count 0 2006.281.07:31:11.12#ibcon#flushed, iclass 3, count 0 2006.281.07:31:11.12#ibcon#about to write, iclass 3, count 0 2006.281.07:31:11.12#ibcon#wrote, iclass 3, count 0 2006.281.07:31:11.12#ibcon#about to read 3, iclass 3, count 0 2006.281.07:31:11.15#ibcon#read 3, iclass 3, count 0 2006.281.07:31:11.15#ibcon#about to read 4, iclass 3, count 0 2006.281.07:31:11.15#ibcon#read 4, iclass 3, count 0 2006.281.07:31:11.15#ibcon#about to read 5, iclass 3, count 0 2006.281.07:31:11.15#ibcon#read 5, iclass 3, count 0 2006.281.07:31:11.15#ibcon#about to read 6, iclass 3, count 0 2006.281.07:31:11.15#ibcon#read 6, iclass 3, count 0 2006.281.07:31:11.15#ibcon#end of sib2, iclass 3, count 0 2006.281.07:31:11.15#ibcon#*after write, iclass 3, count 0 2006.281.07:31:11.15#ibcon#*before return 0, iclass 3, count 0 2006.281.07:31:11.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:31:11.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:31:11.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:31:11.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:31:11.15$vc4f8/valo=7,832.99 2006.281.07:31:11.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:31:11.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:31:11.15#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:11.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:31:11.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:31:11.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:31:11.15#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:31:11.15#ibcon#first serial, iclass 5, count 0 2006.281.07:31:11.15#ibcon#enter sib2, iclass 5, count 0 2006.281.07:31:11.15#ibcon#flushed, iclass 5, count 0 2006.281.07:31:11.15#ibcon#about to write, iclass 5, count 0 2006.281.07:31:11.15#ibcon#wrote, iclass 5, count 0 2006.281.07:31:11.15#ibcon#about to read 3, iclass 5, count 0 2006.281.07:31:11.17#ibcon#read 3, iclass 5, count 0 2006.281.07:31:11.17#ibcon#about to read 4, iclass 5, count 0 2006.281.07:31:11.17#ibcon#read 4, iclass 5, count 0 2006.281.07:31:11.17#ibcon#about to read 5, iclass 5, count 0 2006.281.07:31:11.17#ibcon#read 5, iclass 5, count 0 2006.281.07:31:11.17#ibcon#about to read 6, iclass 5, count 0 2006.281.07:31:11.17#ibcon#read 6, iclass 5, count 0 2006.281.07:31:11.17#ibcon#end of sib2, iclass 5, count 0 2006.281.07:31:11.17#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:31:11.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:31:11.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:31:11.17#ibcon#*before write, iclass 5, count 0 2006.281.07:31:11.17#ibcon#enter sib2, iclass 5, count 0 2006.281.07:31:11.17#ibcon#flushed, iclass 5, count 0 2006.281.07:31:11.17#ibcon#about to write, iclass 5, count 0 2006.281.07:31:11.17#ibcon#wrote, iclass 5, count 0 2006.281.07:31:11.17#ibcon#about to read 3, iclass 5, count 0 2006.281.07:31:11.22#ibcon#read 3, iclass 5, count 0 2006.281.07:31:11.22#ibcon#about to read 4, iclass 5, count 0 2006.281.07:31:11.22#ibcon#read 4, iclass 5, count 0 2006.281.07:31:11.22#ibcon#about to read 5, iclass 5, count 0 2006.281.07:31:11.22#ibcon#read 5, iclass 5, count 0 2006.281.07:31:11.22#ibcon#about to read 6, iclass 5, count 0 2006.281.07:31:11.22#ibcon#read 6, iclass 5, count 0 2006.281.07:31:11.22#ibcon#end of sib2, iclass 5, count 0 2006.281.07:31:11.22#ibcon#*after write, iclass 5, count 0 2006.281.07:31:11.22#ibcon#*before return 0, iclass 5, count 0 2006.281.07:31:11.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:31:11.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:31:11.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:31:11.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:31:11.22$vc4f8/va=7,6 2006.281.07:31:11.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:31:11.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:31:11.22#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:11.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:31:11.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:31:11.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:31:11.27#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:31:11.27#ibcon#first serial, iclass 7, count 2 2006.281.07:31:11.27#ibcon#enter sib2, iclass 7, count 2 2006.281.07:31:11.27#ibcon#flushed, iclass 7, count 2 2006.281.07:31:11.27#ibcon#about to write, iclass 7, count 2 2006.281.07:31:11.27#ibcon#wrote, iclass 7, count 2 2006.281.07:31:11.27#ibcon#about to read 3, iclass 7, count 2 2006.281.07:31:11.29#ibcon#read 3, iclass 7, count 2 2006.281.07:31:11.29#ibcon#about to read 4, iclass 7, count 2 2006.281.07:31:11.29#ibcon#read 4, iclass 7, count 2 2006.281.07:31:11.29#ibcon#about to read 5, iclass 7, count 2 2006.281.07:31:11.29#ibcon#read 5, iclass 7, count 2 2006.281.07:31:11.29#ibcon#about to read 6, iclass 7, count 2 2006.281.07:31:11.29#ibcon#read 6, iclass 7, count 2 2006.281.07:31:11.29#ibcon#end of sib2, iclass 7, count 2 2006.281.07:31:11.29#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:31:11.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:31:11.29#ibcon#[25=AT07-06\r\n] 2006.281.07:31:11.29#ibcon#*before write, iclass 7, count 2 2006.281.07:31:11.29#ibcon#enter sib2, iclass 7, count 2 2006.281.07:31:11.29#ibcon#flushed, iclass 7, count 2 2006.281.07:31:11.29#ibcon#about to write, iclass 7, count 2 2006.281.07:31:11.29#ibcon#wrote, iclass 7, count 2 2006.281.07:31:11.29#ibcon#about to read 3, iclass 7, count 2 2006.281.07:31:11.32#ibcon#read 3, iclass 7, count 2 2006.281.07:31:11.32#ibcon#about to read 4, iclass 7, count 2 2006.281.07:31:11.32#ibcon#read 4, iclass 7, count 2 2006.281.07:31:11.32#ibcon#about to read 5, iclass 7, count 2 2006.281.07:31:11.32#ibcon#read 5, iclass 7, count 2 2006.281.07:31:11.32#ibcon#about to read 6, iclass 7, count 2 2006.281.07:31:11.32#ibcon#read 6, iclass 7, count 2 2006.281.07:31:11.32#ibcon#end of sib2, iclass 7, count 2 2006.281.07:31:11.32#ibcon#*after write, iclass 7, count 2 2006.281.07:31:11.32#ibcon#*before return 0, iclass 7, count 2 2006.281.07:31:11.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:31:11.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:31:11.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:31:11.32#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:11.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:31:11.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:31:11.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:31:11.44#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:31:11.44#ibcon#first serial, iclass 7, count 0 2006.281.07:31:11.44#ibcon#enter sib2, iclass 7, count 0 2006.281.07:31:11.44#ibcon#flushed, iclass 7, count 0 2006.281.07:31:11.44#ibcon#about to write, iclass 7, count 0 2006.281.07:31:11.44#ibcon#wrote, iclass 7, count 0 2006.281.07:31:11.44#ibcon#about to read 3, iclass 7, count 0 2006.281.07:31:11.46#ibcon#read 3, iclass 7, count 0 2006.281.07:31:11.46#ibcon#about to read 4, iclass 7, count 0 2006.281.07:31:11.46#ibcon#read 4, iclass 7, count 0 2006.281.07:31:11.46#ibcon#about to read 5, iclass 7, count 0 2006.281.07:31:11.46#ibcon#read 5, iclass 7, count 0 2006.281.07:31:11.46#ibcon#about to read 6, iclass 7, count 0 2006.281.07:31:11.46#ibcon#read 6, iclass 7, count 0 2006.281.07:31:11.46#ibcon#end of sib2, iclass 7, count 0 2006.281.07:31:11.46#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:31:11.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:31:11.46#ibcon#[25=USB\r\n] 2006.281.07:31:11.46#ibcon#*before write, iclass 7, count 0 2006.281.07:31:11.46#ibcon#enter sib2, iclass 7, count 0 2006.281.07:31:11.46#ibcon#flushed, iclass 7, count 0 2006.281.07:31:11.46#ibcon#about to write, iclass 7, count 0 2006.281.07:31:11.46#ibcon#wrote, iclass 7, count 0 2006.281.07:31:11.46#ibcon#about to read 3, iclass 7, count 0 2006.281.07:31:11.49#ibcon#read 3, iclass 7, count 0 2006.281.07:31:11.49#ibcon#about to read 4, iclass 7, count 0 2006.281.07:31:11.49#ibcon#read 4, iclass 7, count 0 2006.281.07:31:11.49#ibcon#about to read 5, iclass 7, count 0 2006.281.07:31:11.49#ibcon#read 5, iclass 7, count 0 2006.281.07:31:11.49#ibcon#about to read 6, iclass 7, count 0 2006.281.07:31:11.49#ibcon#read 6, iclass 7, count 0 2006.281.07:31:11.49#ibcon#end of sib2, iclass 7, count 0 2006.281.07:31:11.49#ibcon#*after write, iclass 7, count 0 2006.281.07:31:11.49#ibcon#*before return 0, iclass 7, count 0 2006.281.07:31:11.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:31:11.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:31:11.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:31:11.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:31:11.49$vc4f8/valo=8,852.99 2006.281.07:31:11.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:31:11.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:31:11.49#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:11.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:31:11.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:31:11.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:31:11.49#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:31:11.49#ibcon#first serial, iclass 11, count 0 2006.281.07:31:11.49#ibcon#enter sib2, iclass 11, count 0 2006.281.07:31:11.49#ibcon#flushed, iclass 11, count 0 2006.281.07:31:11.49#ibcon#about to write, iclass 11, count 0 2006.281.07:31:11.49#ibcon#wrote, iclass 11, count 0 2006.281.07:31:11.49#ibcon#about to read 3, iclass 11, count 0 2006.281.07:31:11.51#ibcon#read 3, iclass 11, count 0 2006.281.07:31:11.51#ibcon#about to read 4, iclass 11, count 0 2006.281.07:31:11.51#ibcon#read 4, iclass 11, count 0 2006.281.07:31:11.51#ibcon#about to read 5, iclass 11, count 0 2006.281.07:31:11.51#ibcon#read 5, iclass 11, count 0 2006.281.07:31:11.51#ibcon#about to read 6, iclass 11, count 0 2006.281.07:31:11.51#ibcon#read 6, iclass 11, count 0 2006.281.07:31:11.51#ibcon#end of sib2, iclass 11, count 0 2006.281.07:31:11.51#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:31:11.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:31:11.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:31:11.51#ibcon#*before write, iclass 11, count 0 2006.281.07:31:11.51#ibcon#enter sib2, iclass 11, count 0 2006.281.07:31:11.51#ibcon#flushed, iclass 11, count 0 2006.281.07:31:11.51#ibcon#about to write, iclass 11, count 0 2006.281.07:31:11.51#ibcon#wrote, iclass 11, count 0 2006.281.07:31:11.51#ibcon#about to read 3, iclass 11, count 0 2006.281.07:31:11.55#ibcon#read 3, iclass 11, count 0 2006.281.07:31:11.55#ibcon#about to read 4, iclass 11, count 0 2006.281.07:31:11.55#ibcon#read 4, iclass 11, count 0 2006.281.07:31:11.55#ibcon#about to read 5, iclass 11, count 0 2006.281.07:31:11.55#ibcon#read 5, iclass 11, count 0 2006.281.07:31:11.55#ibcon#about to read 6, iclass 11, count 0 2006.281.07:31:11.55#ibcon#read 6, iclass 11, count 0 2006.281.07:31:11.55#ibcon#end of sib2, iclass 11, count 0 2006.281.07:31:11.55#ibcon#*after write, iclass 11, count 0 2006.281.07:31:11.55#ibcon#*before return 0, iclass 11, count 0 2006.281.07:31:11.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:31:11.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:31:11.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:31:11.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:31:11.55$vc4f8/va=8,6 2006.281.07:31:11.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:31:11.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:31:11.55#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:11.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:31:11.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:31:11.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:31:11.61#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:31:11.61#ibcon#first serial, iclass 13, count 2 2006.281.07:31:11.61#ibcon#enter sib2, iclass 13, count 2 2006.281.07:31:11.61#ibcon#flushed, iclass 13, count 2 2006.281.07:31:11.61#ibcon#about to write, iclass 13, count 2 2006.281.07:31:11.61#ibcon#wrote, iclass 13, count 2 2006.281.07:31:11.61#ibcon#about to read 3, iclass 13, count 2 2006.281.07:31:11.63#ibcon#read 3, iclass 13, count 2 2006.281.07:31:11.63#ibcon#about to read 4, iclass 13, count 2 2006.281.07:31:11.63#ibcon#read 4, iclass 13, count 2 2006.281.07:31:11.63#ibcon#about to read 5, iclass 13, count 2 2006.281.07:31:11.63#ibcon#read 5, iclass 13, count 2 2006.281.07:31:11.63#ibcon#about to read 6, iclass 13, count 2 2006.281.07:31:11.63#ibcon#read 6, iclass 13, count 2 2006.281.07:31:11.63#ibcon#end of sib2, iclass 13, count 2 2006.281.07:31:11.63#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:31:11.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:31:11.63#ibcon#[25=AT08-06\r\n] 2006.281.07:31:11.63#ibcon#*before write, iclass 13, count 2 2006.281.07:31:11.63#ibcon#enter sib2, iclass 13, count 2 2006.281.07:31:11.63#ibcon#flushed, iclass 13, count 2 2006.281.07:31:11.63#ibcon#about to write, iclass 13, count 2 2006.281.07:31:11.63#ibcon#wrote, iclass 13, count 2 2006.281.07:31:11.63#ibcon#about to read 3, iclass 13, count 2 2006.281.07:31:11.66#ibcon#read 3, iclass 13, count 2 2006.281.07:31:11.66#ibcon#about to read 4, iclass 13, count 2 2006.281.07:31:11.66#ibcon#read 4, iclass 13, count 2 2006.281.07:31:11.66#ibcon#about to read 5, iclass 13, count 2 2006.281.07:31:11.66#ibcon#read 5, iclass 13, count 2 2006.281.07:31:11.66#ibcon#about to read 6, iclass 13, count 2 2006.281.07:31:11.66#ibcon#read 6, iclass 13, count 2 2006.281.07:31:11.66#ibcon#end of sib2, iclass 13, count 2 2006.281.07:31:11.66#ibcon#*after write, iclass 13, count 2 2006.281.07:31:11.66#ibcon#*before return 0, iclass 13, count 2 2006.281.07:31:11.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:31:11.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:31:11.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:31:11.66#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:11.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:31:11.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:31:11.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:31:11.78#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:31:11.78#ibcon#first serial, iclass 13, count 0 2006.281.07:31:11.78#ibcon#enter sib2, iclass 13, count 0 2006.281.07:31:11.78#ibcon#flushed, iclass 13, count 0 2006.281.07:31:11.78#ibcon#about to write, iclass 13, count 0 2006.281.07:31:11.78#ibcon#wrote, iclass 13, count 0 2006.281.07:31:11.78#ibcon#about to read 3, iclass 13, count 0 2006.281.07:31:11.80#ibcon#read 3, iclass 13, count 0 2006.281.07:31:11.80#ibcon#about to read 4, iclass 13, count 0 2006.281.07:31:11.80#ibcon#read 4, iclass 13, count 0 2006.281.07:31:11.80#ibcon#about to read 5, iclass 13, count 0 2006.281.07:31:11.80#ibcon#read 5, iclass 13, count 0 2006.281.07:31:11.80#ibcon#about to read 6, iclass 13, count 0 2006.281.07:31:11.80#ibcon#read 6, iclass 13, count 0 2006.281.07:31:11.80#ibcon#end of sib2, iclass 13, count 0 2006.281.07:31:11.80#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:31:11.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:31:11.80#ibcon#[25=USB\r\n] 2006.281.07:31:11.80#ibcon#*before write, iclass 13, count 0 2006.281.07:31:11.80#ibcon#enter sib2, iclass 13, count 0 2006.281.07:31:11.80#ibcon#flushed, iclass 13, count 0 2006.281.07:31:11.80#ibcon#about to write, iclass 13, count 0 2006.281.07:31:11.80#ibcon#wrote, iclass 13, count 0 2006.281.07:31:11.80#ibcon#about to read 3, iclass 13, count 0 2006.281.07:31:11.83#ibcon#read 3, iclass 13, count 0 2006.281.07:31:11.83#ibcon#about to read 4, iclass 13, count 0 2006.281.07:31:11.83#ibcon#read 4, iclass 13, count 0 2006.281.07:31:11.83#ibcon#about to read 5, iclass 13, count 0 2006.281.07:31:11.83#ibcon#read 5, iclass 13, count 0 2006.281.07:31:11.83#ibcon#about to read 6, iclass 13, count 0 2006.281.07:31:11.83#ibcon#read 6, iclass 13, count 0 2006.281.07:31:11.83#ibcon#end of sib2, iclass 13, count 0 2006.281.07:31:11.83#ibcon#*after write, iclass 13, count 0 2006.281.07:31:11.83#ibcon#*before return 0, iclass 13, count 0 2006.281.07:31:11.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:31:11.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:31:11.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:31:11.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:31:11.83$vc4f8/vblo=1,632.99 2006.281.07:31:11.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:31:11.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:31:11.83#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:11.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:31:11.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:31:11.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:31:11.83#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:31:11.83#ibcon#first serial, iclass 15, count 0 2006.281.07:31:11.83#ibcon#enter sib2, iclass 15, count 0 2006.281.07:31:11.83#ibcon#flushed, iclass 15, count 0 2006.281.07:31:11.83#ibcon#about to write, iclass 15, count 0 2006.281.07:31:11.83#ibcon#wrote, iclass 15, count 0 2006.281.07:31:11.83#ibcon#about to read 3, iclass 15, count 0 2006.281.07:31:11.85#ibcon#read 3, iclass 15, count 0 2006.281.07:31:11.85#ibcon#about to read 4, iclass 15, count 0 2006.281.07:31:11.85#ibcon#read 4, iclass 15, count 0 2006.281.07:31:11.85#ibcon#about to read 5, iclass 15, count 0 2006.281.07:31:11.85#ibcon#read 5, iclass 15, count 0 2006.281.07:31:11.85#ibcon#about to read 6, iclass 15, count 0 2006.281.07:31:11.85#ibcon#read 6, iclass 15, count 0 2006.281.07:31:11.85#ibcon#end of sib2, iclass 15, count 0 2006.281.07:31:11.85#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:31:11.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:31:11.87#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:31:11.87#ibcon#*before write, iclass 15, count 0 2006.281.07:31:11.87#ibcon#enter sib2, iclass 15, count 0 2006.281.07:31:11.87#ibcon#flushed, iclass 15, count 0 2006.281.07:31:11.87#ibcon#about to write, iclass 15, count 0 2006.281.07:31:11.87#ibcon#wrote, iclass 15, count 0 2006.281.07:31:11.87#ibcon#about to read 3, iclass 15, count 0 2006.281.07:31:11.91#ibcon#read 3, iclass 15, count 0 2006.281.07:31:11.91#ibcon#about to read 4, iclass 15, count 0 2006.281.07:31:11.91#ibcon#read 4, iclass 15, count 0 2006.281.07:31:11.91#ibcon#about to read 5, iclass 15, count 0 2006.281.07:31:11.91#ibcon#read 5, iclass 15, count 0 2006.281.07:31:11.91#ibcon#about to read 6, iclass 15, count 0 2006.281.07:31:11.91#ibcon#read 6, iclass 15, count 0 2006.281.07:31:11.91#ibcon#end of sib2, iclass 15, count 0 2006.281.07:31:11.91#ibcon#*after write, iclass 15, count 0 2006.281.07:31:11.91#ibcon#*before return 0, iclass 15, count 0 2006.281.07:31:11.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:31:11.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:31:11.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:31:11.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:31:11.91$vc4f8/vb=1,4 2006.281.07:31:11.91#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:31:11.91#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:31:11.91#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:11.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:31:11.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:31:11.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:31:11.91#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:31:11.91#ibcon#first serial, iclass 17, count 2 2006.281.07:31:11.91#ibcon#enter sib2, iclass 17, count 2 2006.281.07:31:11.91#ibcon#flushed, iclass 17, count 2 2006.281.07:31:11.91#ibcon#about to write, iclass 17, count 2 2006.281.07:31:11.91#ibcon#wrote, iclass 17, count 2 2006.281.07:31:11.91#ibcon#about to read 3, iclass 17, count 2 2006.281.07:31:11.93#ibcon#read 3, iclass 17, count 2 2006.281.07:31:11.93#ibcon#about to read 4, iclass 17, count 2 2006.281.07:31:11.93#ibcon#read 4, iclass 17, count 2 2006.281.07:31:11.93#ibcon#about to read 5, iclass 17, count 2 2006.281.07:31:11.93#ibcon#read 5, iclass 17, count 2 2006.281.07:31:11.93#ibcon#about to read 6, iclass 17, count 2 2006.281.07:31:11.93#ibcon#read 6, iclass 17, count 2 2006.281.07:31:11.93#ibcon#end of sib2, iclass 17, count 2 2006.281.07:31:11.93#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:31:11.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:31:11.93#ibcon#[27=AT01-04\r\n] 2006.281.07:31:11.93#ibcon#*before write, iclass 17, count 2 2006.281.07:31:11.93#ibcon#enter sib2, iclass 17, count 2 2006.281.07:31:11.93#ibcon#flushed, iclass 17, count 2 2006.281.07:31:11.93#ibcon#about to write, iclass 17, count 2 2006.281.07:31:11.93#ibcon#wrote, iclass 17, count 2 2006.281.07:31:11.93#ibcon#about to read 3, iclass 17, count 2 2006.281.07:31:11.96#ibcon#read 3, iclass 17, count 2 2006.281.07:31:11.96#ibcon#about to read 4, iclass 17, count 2 2006.281.07:31:11.96#ibcon#read 4, iclass 17, count 2 2006.281.07:31:11.96#ibcon#about to read 5, iclass 17, count 2 2006.281.07:31:11.96#ibcon#read 5, iclass 17, count 2 2006.281.07:31:11.96#ibcon#about to read 6, iclass 17, count 2 2006.281.07:31:11.96#ibcon#read 6, iclass 17, count 2 2006.281.07:31:11.96#ibcon#end of sib2, iclass 17, count 2 2006.281.07:31:11.96#ibcon#*after write, iclass 17, count 2 2006.281.07:31:11.96#ibcon#*before return 0, iclass 17, count 2 2006.281.07:31:11.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:31:11.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:31:11.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:31:11.96#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:11.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:31:12.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:31:12.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:31:12.08#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:31:12.08#ibcon#first serial, iclass 17, count 0 2006.281.07:31:12.08#ibcon#enter sib2, iclass 17, count 0 2006.281.07:31:12.08#ibcon#flushed, iclass 17, count 0 2006.281.07:31:12.08#ibcon#about to write, iclass 17, count 0 2006.281.07:31:12.08#ibcon#wrote, iclass 17, count 0 2006.281.07:31:12.08#ibcon#about to read 3, iclass 17, count 0 2006.281.07:31:12.10#ibcon#read 3, iclass 17, count 0 2006.281.07:31:12.10#ibcon#about to read 4, iclass 17, count 0 2006.281.07:31:12.10#ibcon#read 4, iclass 17, count 0 2006.281.07:31:12.10#ibcon#about to read 5, iclass 17, count 0 2006.281.07:31:12.10#ibcon#read 5, iclass 17, count 0 2006.281.07:31:12.10#ibcon#about to read 6, iclass 17, count 0 2006.281.07:31:12.10#ibcon#read 6, iclass 17, count 0 2006.281.07:31:12.10#ibcon#end of sib2, iclass 17, count 0 2006.281.07:31:12.10#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:31:12.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:31:12.10#ibcon#[27=USB\r\n] 2006.281.07:31:12.10#ibcon#*before write, iclass 17, count 0 2006.281.07:31:12.10#ibcon#enter sib2, iclass 17, count 0 2006.281.07:31:12.10#ibcon#flushed, iclass 17, count 0 2006.281.07:31:12.10#ibcon#about to write, iclass 17, count 0 2006.281.07:31:12.10#ibcon#wrote, iclass 17, count 0 2006.281.07:31:12.10#ibcon#about to read 3, iclass 17, count 0 2006.281.07:31:12.13#ibcon#read 3, iclass 17, count 0 2006.281.07:31:12.13#ibcon#about to read 4, iclass 17, count 0 2006.281.07:31:12.13#ibcon#read 4, iclass 17, count 0 2006.281.07:31:12.13#ibcon#about to read 5, iclass 17, count 0 2006.281.07:31:12.13#ibcon#read 5, iclass 17, count 0 2006.281.07:31:12.13#ibcon#about to read 6, iclass 17, count 0 2006.281.07:31:12.13#ibcon#read 6, iclass 17, count 0 2006.281.07:31:12.13#ibcon#end of sib2, iclass 17, count 0 2006.281.07:31:12.13#ibcon#*after write, iclass 17, count 0 2006.281.07:31:12.13#ibcon#*before return 0, iclass 17, count 0 2006.281.07:31:12.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:31:12.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:31:12.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:31:12.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:31:12.13$vc4f8/vblo=2,640.99 2006.281.07:31:12.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:31:12.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:31:12.13#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:12.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:12.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:12.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:12.13#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:31:12.13#ibcon#first serial, iclass 19, count 0 2006.281.07:31:12.13#ibcon#enter sib2, iclass 19, count 0 2006.281.07:31:12.13#ibcon#flushed, iclass 19, count 0 2006.281.07:31:12.13#ibcon#about to write, iclass 19, count 0 2006.281.07:31:12.13#ibcon#wrote, iclass 19, count 0 2006.281.07:31:12.13#ibcon#about to read 3, iclass 19, count 0 2006.281.07:31:12.15#ibcon#read 3, iclass 19, count 0 2006.281.07:31:12.15#ibcon#about to read 4, iclass 19, count 0 2006.281.07:31:12.15#ibcon#read 4, iclass 19, count 0 2006.281.07:31:12.15#ibcon#about to read 5, iclass 19, count 0 2006.281.07:31:12.15#ibcon#read 5, iclass 19, count 0 2006.281.07:31:12.15#ibcon#about to read 6, iclass 19, count 0 2006.281.07:31:12.15#ibcon#read 6, iclass 19, count 0 2006.281.07:31:12.15#ibcon#end of sib2, iclass 19, count 0 2006.281.07:31:12.15#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:31:12.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:31:12.15#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:31:12.15#ibcon#*before write, iclass 19, count 0 2006.281.07:31:12.15#ibcon#enter sib2, iclass 19, count 0 2006.281.07:31:12.15#ibcon#flushed, iclass 19, count 0 2006.281.07:31:12.15#ibcon#about to write, iclass 19, count 0 2006.281.07:31:12.15#ibcon#wrote, iclass 19, count 0 2006.281.07:31:12.15#ibcon#about to read 3, iclass 19, count 0 2006.281.07:31:12.19#ibcon#read 3, iclass 19, count 0 2006.281.07:31:12.19#ibcon#about to read 4, iclass 19, count 0 2006.281.07:31:12.19#ibcon#read 4, iclass 19, count 0 2006.281.07:31:12.19#ibcon#about to read 5, iclass 19, count 0 2006.281.07:31:12.19#ibcon#read 5, iclass 19, count 0 2006.281.07:31:12.19#ibcon#about to read 6, iclass 19, count 0 2006.281.07:31:12.19#ibcon#read 6, iclass 19, count 0 2006.281.07:31:12.19#ibcon#end of sib2, iclass 19, count 0 2006.281.07:31:12.19#ibcon#*after write, iclass 19, count 0 2006.281.07:31:12.19#ibcon#*before return 0, iclass 19, count 0 2006.281.07:31:12.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:12.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:31:12.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:31:12.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:31:12.19$vc4f8/vb=2,5 2006.281.07:31:12.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:31:12.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:31:12.19#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:12.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:12.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:12.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:12.25#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:31:12.25#ibcon#first serial, iclass 21, count 2 2006.281.07:31:12.25#ibcon#enter sib2, iclass 21, count 2 2006.281.07:31:12.25#ibcon#flushed, iclass 21, count 2 2006.281.07:31:12.25#ibcon#about to write, iclass 21, count 2 2006.281.07:31:12.25#ibcon#wrote, iclass 21, count 2 2006.281.07:31:12.25#ibcon#about to read 3, iclass 21, count 2 2006.281.07:31:12.27#ibcon#read 3, iclass 21, count 2 2006.281.07:31:12.27#ibcon#about to read 4, iclass 21, count 2 2006.281.07:31:12.27#ibcon#read 4, iclass 21, count 2 2006.281.07:31:12.27#ibcon#about to read 5, iclass 21, count 2 2006.281.07:31:12.27#ibcon#read 5, iclass 21, count 2 2006.281.07:31:12.27#ibcon#about to read 6, iclass 21, count 2 2006.281.07:31:12.27#ibcon#read 6, iclass 21, count 2 2006.281.07:31:12.27#ibcon#end of sib2, iclass 21, count 2 2006.281.07:31:12.27#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:31:12.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:31:12.27#ibcon#[27=AT02-05\r\n] 2006.281.07:31:12.27#ibcon#*before write, iclass 21, count 2 2006.281.07:31:12.27#ibcon#enter sib2, iclass 21, count 2 2006.281.07:31:12.27#ibcon#flushed, iclass 21, count 2 2006.281.07:31:12.27#ibcon#about to write, iclass 21, count 2 2006.281.07:31:12.27#ibcon#wrote, iclass 21, count 2 2006.281.07:31:12.27#ibcon#about to read 3, iclass 21, count 2 2006.281.07:31:12.30#ibcon#read 3, iclass 21, count 2 2006.281.07:31:12.30#ibcon#about to read 4, iclass 21, count 2 2006.281.07:31:12.30#ibcon#read 4, iclass 21, count 2 2006.281.07:31:12.30#ibcon#about to read 5, iclass 21, count 2 2006.281.07:31:12.30#ibcon#read 5, iclass 21, count 2 2006.281.07:31:12.30#ibcon#about to read 6, iclass 21, count 2 2006.281.07:31:12.30#ibcon#read 6, iclass 21, count 2 2006.281.07:31:12.30#ibcon#end of sib2, iclass 21, count 2 2006.281.07:31:12.30#ibcon#*after write, iclass 21, count 2 2006.281.07:31:12.30#ibcon#*before return 0, iclass 21, count 2 2006.281.07:31:12.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:12.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:31:12.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:31:12.30#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:12.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:12.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:12.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:12.42#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:31:12.42#ibcon#first serial, iclass 21, count 0 2006.281.07:31:12.42#ibcon#enter sib2, iclass 21, count 0 2006.281.07:31:12.42#ibcon#flushed, iclass 21, count 0 2006.281.07:31:12.42#ibcon#about to write, iclass 21, count 0 2006.281.07:31:12.42#ibcon#wrote, iclass 21, count 0 2006.281.07:31:12.42#ibcon#about to read 3, iclass 21, count 0 2006.281.07:31:12.44#ibcon#read 3, iclass 21, count 0 2006.281.07:31:12.44#ibcon#about to read 4, iclass 21, count 0 2006.281.07:31:12.44#ibcon#read 4, iclass 21, count 0 2006.281.07:31:12.44#ibcon#about to read 5, iclass 21, count 0 2006.281.07:31:12.44#ibcon#read 5, iclass 21, count 0 2006.281.07:31:12.44#ibcon#about to read 6, iclass 21, count 0 2006.281.07:31:12.44#ibcon#read 6, iclass 21, count 0 2006.281.07:31:12.44#ibcon#end of sib2, iclass 21, count 0 2006.281.07:31:12.44#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:31:12.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:31:12.44#ibcon#[27=USB\r\n] 2006.281.07:31:12.44#ibcon#*before write, iclass 21, count 0 2006.281.07:31:12.44#ibcon#enter sib2, iclass 21, count 0 2006.281.07:31:12.44#ibcon#flushed, iclass 21, count 0 2006.281.07:31:12.44#ibcon#about to write, iclass 21, count 0 2006.281.07:31:12.44#ibcon#wrote, iclass 21, count 0 2006.281.07:31:12.44#ibcon#about to read 3, iclass 21, count 0 2006.281.07:31:12.47#ibcon#read 3, iclass 21, count 0 2006.281.07:31:12.47#ibcon#about to read 4, iclass 21, count 0 2006.281.07:31:12.47#ibcon#read 4, iclass 21, count 0 2006.281.07:31:12.47#ibcon#about to read 5, iclass 21, count 0 2006.281.07:31:12.47#ibcon#read 5, iclass 21, count 0 2006.281.07:31:12.47#ibcon#about to read 6, iclass 21, count 0 2006.281.07:31:12.47#ibcon#read 6, iclass 21, count 0 2006.281.07:31:12.47#ibcon#end of sib2, iclass 21, count 0 2006.281.07:31:12.47#ibcon#*after write, iclass 21, count 0 2006.281.07:31:12.47#ibcon#*before return 0, iclass 21, count 0 2006.281.07:31:12.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:12.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:31:12.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:31:12.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:31:12.47$vc4f8/vblo=3,656.99 2006.281.07:31:12.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:31:12.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:31:12.47#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:12.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:12.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:12.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:12.47#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:31:12.47#ibcon#first serial, iclass 23, count 0 2006.281.07:31:12.47#ibcon#enter sib2, iclass 23, count 0 2006.281.07:31:12.47#ibcon#flushed, iclass 23, count 0 2006.281.07:31:12.47#ibcon#about to write, iclass 23, count 0 2006.281.07:31:12.47#ibcon#wrote, iclass 23, count 0 2006.281.07:31:12.47#ibcon#about to read 3, iclass 23, count 0 2006.281.07:31:12.49#ibcon#read 3, iclass 23, count 0 2006.281.07:31:12.49#ibcon#about to read 4, iclass 23, count 0 2006.281.07:31:12.49#ibcon#read 4, iclass 23, count 0 2006.281.07:31:12.49#ibcon#about to read 5, iclass 23, count 0 2006.281.07:31:12.49#ibcon#read 5, iclass 23, count 0 2006.281.07:31:12.49#ibcon#about to read 6, iclass 23, count 0 2006.281.07:31:12.49#ibcon#read 6, iclass 23, count 0 2006.281.07:31:12.49#ibcon#end of sib2, iclass 23, count 0 2006.281.07:31:12.49#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:31:12.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:31:12.49#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:31:12.49#ibcon#*before write, iclass 23, count 0 2006.281.07:31:12.49#ibcon#enter sib2, iclass 23, count 0 2006.281.07:31:12.49#ibcon#flushed, iclass 23, count 0 2006.281.07:31:12.49#ibcon#about to write, iclass 23, count 0 2006.281.07:31:12.49#ibcon#wrote, iclass 23, count 0 2006.281.07:31:12.49#ibcon#about to read 3, iclass 23, count 0 2006.281.07:31:12.53#ibcon#read 3, iclass 23, count 0 2006.281.07:31:12.53#ibcon#about to read 4, iclass 23, count 0 2006.281.07:31:12.53#ibcon#read 4, iclass 23, count 0 2006.281.07:31:12.53#ibcon#about to read 5, iclass 23, count 0 2006.281.07:31:12.53#ibcon#read 5, iclass 23, count 0 2006.281.07:31:12.53#ibcon#about to read 6, iclass 23, count 0 2006.281.07:31:12.53#ibcon#read 6, iclass 23, count 0 2006.281.07:31:12.53#ibcon#end of sib2, iclass 23, count 0 2006.281.07:31:12.53#ibcon#*after write, iclass 23, count 0 2006.281.07:31:12.53#ibcon#*before return 0, iclass 23, count 0 2006.281.07:31:12.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:12.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:31:12.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:31:12.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:31:12.53$vc4f8/vb=3,4 2006.281.07:31:12.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:31:12.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:31:12.53#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:12.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:12.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:12.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:12.59#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:31:12.59#ibcon#first serial, iclass 25, count 2 2006.281.07:31:12.59#ibcon#enter sib2, iclass 25, count 2 2006.281.07:31:12.59#ibcon#flushed, iclass 25, count 2 2006.281.07:31:12.59#ibcon#about to write, iclass 25, count 2 2006.281.07:31:12.59#ibcon#wrote, iclass 25, count 2 2006.281.07:31:12.59#ibcon#about to read 3, iclass 25, count 2 2006.281.07:31:12.61#ibcon#read 3, iclass 25, count 2 2006.281.07:31:12.61#ibcon#about to read 4, iclass 25, count 2 2006.281.07:31:12.61#ibcon#read 4, iclass 25, count 2 2006.281.07:31:12.61#ibcon#about to read 5, iclass 25, count 2 2006.281.07:31:12.61#ibcon#read 5, iclass 25, count 2 2006.281.07:31:12.61#ibcon#about to read 6, iclass 25, count 2 2006.281.07:31:12.61#ibcon#read 6, iclass 25, count 2 2006.281.07:31:12.61#ibcon#end of sib2, iclass 25, count 2 2006.281.07:31:12.61#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:31:12.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:31:12.61#ibcon#[27=AT03-04\r\n] 2006.281.07:31:12.61#ibcon#*before write, iclass 25, count 2 2006.281.07:31:12.61#ibcon#enter sib2, iclass 25, count 2 2006.281.07:31:12.61#ibcon#flushed, iclass 25, count 2 2006.281.07:31:12.61#ibcon#about to write, iclass 25, count 2 2006.281.07:31:12.61#ibcon#wrote, iclass 25, count 2 2006.281.07:31:12.61#ibcon#about to read 3, iclass 25, count 2 2006.281.07:31:12.64#ibcon#read 3, iclass 25, count 2 2006.281.07:31:12.64#ibcon#about to read 4, iclass 25, count 2 2006.281.07:31:12.64#ibcon#read 4, iclass 25, count 2 2006.281.07:31:12.64#ibcon#about to read 5, iclass 25, count 2 2006.281.07:31:12.64#ibcon#read 5, iclass 25, count 2 2006.281.07:31:12.64#ibcon#about to read 6, iclass 25, count 2 2006.281.07:31:12.64#ibcon#read 6, iclass 25, count 2 2006.281.07:31:12.64#ibcon#end of sib2, iclass 25, count 2 2006.281.07:31:12.64#ibcon#*after write, iclass 25, count 2 2006.281.07:31:12.64#ibcon#*before return 0, iclass 25, count 2 2006.281.07:31:12.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:12.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:31:12.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:31:12.64#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:12.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:12.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:12.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:12.76#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:31:12.76#ibcon#first serial, iclass 25, count 0 2006.281.07:31:12.76#ibcon#enter sib2, iclass 25, count 0 2006.281.07:31:12.76#ibcon#flushed, iclass 25, count 0 2006.281.07:31:12.76#ibcon#about to write, iclass 25, count 0 2006.281.07:31:12.76#ibcon#wrote, iclass 25, count 0 2006.281.07:31:12.76#ibcon#about to read 3, iclass 25, count 0 2006.281.07:31:12.78#ibcon#read 3, iclass 25, count 0 2006.281.07:31:12.78#ibcon#about to read 4, iclass 25, count 0 2006.281.07:31:12.78#ibcon#read 4, iclass 25, count 0 2006.281.07:31:12.78#ibcon#about to read 5, iclass 25, count 0 2006.281.07:31:12.78#ibcon#read 5, iclass 25, count 0 2006.281.07:31:12.78#ibcon#about to read 6, iclass 25, count 0 2006.281.07:31:12.78#ibcon#read 6, iclass 25, count 0 2006.281.07:31:12.78#ibcon#end of sib2, iclass 25, count 0 2006.281.07:31:12.78#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:31:12.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:31:12.78#ibcon#[27=USB\r\n] 2006.281.07:31:12.78#ibcon#*before write, iclass 25, count 0 2006.281.07:31:12.78#ibcon#enter sib2, iclass 25, count 0 2006.281.07:31:12.78#ibcon#flushed, iclass 25, count 0 2006.281.07:31:12.78#ibcon#about to write, iclass 25, count 0 2006.281.07:31:12.78#ibcon#wrote, iclass 25, count 0 2006.281.07:31:12.78#ibcon#about to read 3, iclass 25, count 0 2006.281.07:31:12.81#ibcon#read 3, iclass 25, count 0 2006.281.07:31:12.81#ibcon#about to read 4, iclass 25, count 0 2006.281.07:31:12.81#ibcon#read 4, iclass 25, count 0 2006.281.07:31:12.81#ibcon#about to read 5, iclass 25, count 0 2006.281.07:31:12.81#ibcon#read 5, iclass 25, count 0 2006.281.07:31:12.81#ibcon#about to read 6, iclass 25, count 0 2006.281.07:31:12.81#ibcon#read 6, iclass 25, count 0 2006.281.07:31:12.81#ibcon#end of sib2, iclass 25, count 0 2006.281.07:31:12.81#ibcon#*after write, iclass 25, count 0 2006.281.07:31:12.81#ibcon#*before return 0, iclass 25, count 0 2006.281.07:31:12.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:12.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:31:12.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:31:12.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:31:12.81$vc4f8/vblo=4,712.99 2006.281.07:31:12.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:31:12.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:31:12.81#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:12.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:12.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:12.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:12.81#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:31:12.81#ibcon#first serial, iclass 27, count 0 2006.281.07:31:12.81#ibcon#enter sib2, iclass 27, count 0 2006.281.07:31:12.81#ibcon#flushed, iclass 27, count 0 2006.281.07:31:12.81#ibcon#about to write, iclass 27, count 0 2006.281.07:31:12.81#ibcon#wrote, iclass 27, count 0 2006.281.07:31:12.81#ibcon#about to read 3, iclass 27, count 0 2006.281.07:31:12.83#ibcon#read 3, iclass 27, count 0 2006.281.07:31:12.83#ibcon#about to read 4, iclass 27, count 0 2006.281.07:31:12.83#ibcon#read 4, iclass 27, count 0 2006.281.07:31:12.83#ibcon#about to read 5, iclass 27, count 0 2006.281.07:31:12.83#ibcon#read 5, iclass 27, count 0 2006.281.07:31:12.83#ibcon#about to read 6, iclass 27, count 0 2006.281.07:31:12.83#ibcon#read 6, iclass 27, count 0 2006.281.07:31:12.83#ibcon#end of sib2, iclass 27, count 0 2006.281.07:31:12.83#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:31:12.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:31:12.83#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:31:12.83#ibcon#*before write, iclass 27, count 0 2006.281.07:31:12.83#ibcon#enter sib2, iclass 27, count 0 2006.281.07:31:12.83#ibcon#flushed, iclass 27, count 0 2006.281.07:31:12.83#ibcon#about to write, iclass 27, count 0 2006.281.07:31:12.83#ibcon#wrote, iclass 27, count 0 2006.281.07:31:12.83#ibcon#about to read 3, iclass 27, count 0 2006.281.07:31:12.87#ibcon#read 3, iclass 27, count 0 2006.281.07:31:12.87#ibcon#about to read 4, iclass 27, count 0 2006.281.07:31:12.87#ibcon#read 4, iclass 27, count 0 2006.281.07:31:12.87#ibcon#about to read 5, iclass 27, count 0 2006.281.07:31:12.87#ibcon#read 5, iclass 27, count 0 2006.281.07:31:12.87#ibcon#about to read 6, iclass 27, count 0 2006.281.07:31:12.87#ibcon#read 6, iclass 27, count 0 2006.281.07:31:12.87#ibcon#end of sib2, iclass 27, count 0 2006.281.07:31:12.87#ibcon#*after write, iclass 27, count 0 2006.281.07:31:12.87#ibcon#*before return 0, iclass 27, count 0 2006.281.07:31:12.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:12.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:31:12.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:31:12.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:31:12.87$vc4f8/vb=4,4 2006.281.07:31:12.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:31:12.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:31:12.88#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:12.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:12.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:12.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:12.93#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:31:12.93#ibcon#first serial, iclass 29, count 2 2006.281.07:31:12.93#ibcon#enter sib2, iclass 29, count 2 2006.281.07:31:12.93#ibcon#flushed, iclass 29, count 2 2006.281.07:31:12.93#ibcon#about to write, iclass 29, count 2 2006.281.07:31:12.93#ibcon#wrote, iclass 29, count 2 2006.281.07:31:12.93#ibcon#about to read 3, iclass 29, count 2 2006.281.07:31:12.95#ibcon#read 3, iclass 29, count 2 2006.281.07:31:12.95#ibcon#about to read 4, iclass 29, count 2 2006.281.07:31:12.95#ibcon#read 4, iclass 29, count 2 2006.281.07:31:12.95#ibcon#about to read 5, iclass 29, count 2 2006.281.07:31:12.95#ibcon#read 5, iclass 29, count 2 2006.281.07:31:12.95#ibcon#about to read 6, iclass 29, count 2 2006.281.07:31:12.95#ibcon#read 6, iclass 29, count 2 2006.281.07:31:12.95#ibcon#end of sib2, iclass 29, count 2 2006.281.07:31:12.95#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:31:12.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:31:12.95#ibcon#[27=AT04-04\r\n] 2006.281.07:31:12.95#ibcon#*before write, iclass 29, count 2 2006.281.07:31:12.95#ibcon#enter sib2, iclass 29, count 2 2006.281.07:31:12.95#ibcon#flushed, iclass 29, count 2 2006.281.07:31:12.95#ibcon#about to write, iclass 29, count 2 2006.281.07:31:12.95#ibcon#wrote, iclass 29, count 2 2006.281.07:31:12.95#ibcon#about to read 3, iclass 29, count 2 2006.281.07:31:12.98#ibcon#read 3, iclass 29, count 2 2006.281.07:31:12.98#ibcon#about to read 4, iclass 29, count 2 2006.281.07:31:12.98#ibcon#read 4, iclass 29, count 2 2006.281.07:31:12.98#ibcon#about to read 5, iclass 29, count 2 2006.281.07:31:12.98#ibcon#read 5, iclass 29, count 2 2006.281.07:31:12.98#ibcon#about to read 6, iclass 29, count 2 2006.281.07:31:12.98#ibcon#read 6, iclass 29, count 2 2006.281.07:31:12.98#ibcon#end of sib2, iclass 29, count 2 2006.281.07:31:12.98#ibcon#*after write, iclass 29, count 2 2006.281.07:31:12.98#ibcon#*before return 0, iclass 29, count 2 2006.281.07:31:12.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:12.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:31:12.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:31:12.98#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:12.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:13.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:13.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:13.10#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:31:13.10#ibcon#first serial, iclass 29, count 0 2006.281.07:31:13.10#ibcon#enter sib2, iclass 29, count 0 2006.281.07:31:13.10#ibcon#flushed, iclass 29, count 0 2006.281.07:31:13.10#ibcon#about to write, iclass 29, count 0 2006.281.07:31:13.10#ibcon#wrote, iclass 29, count 0 2006.281.07:31:13.10#ibcon#about to read 3, iclass 29, count 0 2006.281.07:31:13.12#ibcon#read 3, iclass 29, count 0 2006.281.07:31:13.12#ibcon#about to read 4, iclass 29, count 0 2006.281.07:31:13.12#ibcon#read 4, iclass 29, count 0 2006.281.07:31:13.12#ibcon#about to read 5, iclass 29, count 0 2006.281.07:31:13.12#ibcon#read 5, iclass 29, count 0 2006.281.07:31:13.12#ibcon#about to read 6, iclass 29, count 0 2006.281.07:31:13.12#ibcon#read 6, iclass 29, count 0 2006.281.07:31:13.12#ibcon#end of sib2, iclass 29, count 0 2006.281.07:31:13.12#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:31:13.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:31:13.12#ibcon#[27=USB\r\n] 2006.281.07:31:13.12#ibcon#*before write, iclass 29, count 0 2006.281.07:31:13.12#ibcon#enter sib2, iclass 29, count 0 2006.281.07:31:13.12#ibcon#flushed, iclass 29, count 0 2006.281.07:31:13.12#ibcon#about to write, iclass 29, count 0 2006.281.07:31:13.12#ibcon#wrote, iclass 29, count 0 2006.281.07:31:13.12#ibcon#about to read 3, iclass 29, count 0 2006.281.07:31:13.15#ibcon#read 3, iclass 29, count 0 2006.281.07:31:13.15#ibcon#about to read 4, iclass 29, count 0 2006.281.07:31:13.15#ibcon#read 4, iclass 29, count 0 2006.281.07:31:13.15#ibcon#about to read 5, iclass 29, count 0 2006.281.07:31:13.15#ibcon#read 5, iclass 29, count 0 2006.281.07:31:13.15#ibcon#about to read 6, iclass 29, count 0 2006.281.07:31:13.15#ibcon#read 6, iclass 29, count 0 2006.281.07:31:13.15#ibcon#end of sib2, iclass 29, count 0 2006.281.07:31:13.15#ibcon#*after write, iclass 29, count 0 2006.281.07:31:13.15#ibcon#*before return 0, iclass 29, count 0 2006.281.07:31:13.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:13.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:31:13.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:31:13.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:31:13.15$vc4f8/vblo=5,744.99 2006.281.07:31:13.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:31:13.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:31:13.15#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:13.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:13.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:13.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:13.15#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:31:13.15#ibcon#first serial, iclass 31, count 0 2006.281.07:31:13.15#ibcon#enter sib2, iclass 31, count 0 2006.281.07:31:13.15#ibcon#flushed, iclass 31, count 0 2006.281.07:31:13.15#ibcon#about to write, iclass 31, count 0 2006.281.07:31:13.15#ibcon#wrote, iclass 31, count 0 2006.281.07:31:13.15#ibcon#about to read 3, iclass 31, count 0 2006.281.07:31:13.17#ibcon#read 3, iclass 31, count 0 2006.281.07:31:13.17#ibcon#about to read 4, iclass 31, count 0 2006.281.07:31:13.17#ibcon#read 4, iclass 31, count 0 2006.281.07:31:13.17#ibcon#about to read 5, iclass 31, count 0 2006.281.07:31:13.17#ibcon#read 5, iclass 31, count 0 2006.281.07:31:13.17#ibcon#about to read 6, iclass 31, count 0 2006.281.07:31:13.17#ibcon#read 6, iclass 31, count 0 2006.281.07:31:13.17#ibcon#end of sib2, iclass 31, count 0 2006.281.07:31:13.17#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:31:13.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:31:13.19#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:31:13.19#ibcon#*before write, iclass 31, count 0 2006.281.07:31:13.19#ibcon#enter sib2, iclass 31, count 0 2006.281.07:31:13.19#ibcon#flushed, iclass 31, count 0 2006.281.07:31:13.19#ibcon#about to write, iclass 31, count 0 2006.281.07:31:13.19#ibcon#wrote, iclass 31, count 0 2006.281.07:31:13.19#ibcon#about to read 3, iclass 31, count 0 2006.281.07:31:13.23#ibcon#read 3, iclass 31, count 0 2006.281.07:31:13.23#ibcon#about to read 4, iclass 31, count 0 2006.281.07:31:13.23#ibcon#read 4, iclass 31, count 0 2006.281.07:31:13.23#ibcon#about to read 5, iclass 31, count 0 2006.281.07:31:13.23#ibcon#read 5, iclass 31, count 0 2006.281.07:31:13.23#ibcon#about to read 6, iclass 31, count 0 2006.281.07:31:13.23#ibcon#read 6, iclass 31, count 0 2006.281.07:31:13.23#ibcon#end of sib2, iclass 31, count 0 2006.281.07:31:13.23#ibcon#*after write, iclass 31, count 0 2006.281.07:31:13.23#ibcon#*before return 0, iclass 31, count 0 2006.281.07:31:13.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:13.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:31:13.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:31:13.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:31:13.23$vc4f8/vb=5,4 2006.281.07:31:13.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:31:13.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:31:13.23#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:13.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:13.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:13.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:13.27#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:31:13.27#ibcon#first serial, iclass 33, count 2 2006.281.07:31:13.27#ibcon#enter sib2, iclass 33, count 2 2006.281.07:31:13.27#ibcon#flushed, iclass 33, count 2 2006.281.07:31:13.27#ibcon#about to write, iclass 33, count 2 2006.281.07:31:13.27#ibcon#wrote, iclass 33, count 2 2006.281.07:31:13.27#ibcon#about to read 3, iclass 33, count 2 2006.281.07:31:13.29#ibcon#read 3, iclass 33, count 2 2006.281.07:31:13.29#ibcon#about to read 4, iclass 33, count 2 2006.281.07:31:13.29#ibcon#read 4, iclass 33, count 2 2006.281.07:31:13.29#ibcon#about to read 5, iclass 33, count 2 2006.281.07:31:13.29#ibcon#read 5, iclass 33, count 2 2006.281.07:31:13.29#ibcon#about to read 6, iclass 33, count 2 2006.281.07:31:13.29#ibcon#read 6, iclass 33, count 2 2006.281.07:31:13.29#ibcon#end of sib2, iclass 33, count 2 2006.281.07:31:13.29#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:31:13.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:31:13.29#ibcon#[27=AT05-04\r\n] 2006.281.07:31:13.29#ibcon#*before write, iclass 33, count 2 2006.281.07:31:13.29#ibcon#enter sib2, iclass 33, count 2 2006.281.07:31:13.29#ibcon#flushed, iclass 33, count 2 2006.281.07:31:13.29#ibcon#about to write, iclass 33, count 2 2006.281.07:31:13.29#ibcon#wrote, iclass 33, count 2 2006.281.07:31:13.29#ibcon#about to read 3, iclass 33, count 2 2006.281.07:31:13.32#ibcon#read 3, iclass 33, count 2 2006.281.07:31:13.32#ibcon#about to read 4, iclass 33, count 2 2006.281.07:31:13.32#ibcon#read 4, iclass 33, count 2 2006.281.07:31:13.32#ibcon#about to read 5, iclass 33, count 2 2006.281.07:31:13.32#ibcon#read 5, iclass 33, count 2 2006.281.07:31:13.32#ibcon#about to read 6, iclass 33, count 2 2006.281.07:31:13.32#ibcon#read 6, iclass 33, count 2 2006.281.07:31:13.32#ibcon#end of sib2, iclass 33, count 2 2006.281.07:31:13.32#ibcon#*after write, iclass 33, count 2 2006.281.07:31:13.32#ibcon#*before return 0, iclass 33, count 2 2006.281.07:31:13.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:13.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:31:13.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:31:13.32#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:13.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:13.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:13.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:13.44#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:31:13.44#ibcon#first serial, iclass 33, count 0 2006.281.07:31:13.44#ibcon#enter sib2, iclass 33, count 0 2006.281.07:31:13.44#ibcon#flushed, iclass 33, count 0 2006.281.07:31:13.44#ibcon#about to write, iclass 33, count 0 2006.281.07:31:13.44#ibcon#wrote, iclass 33, count 0 2006.281.07:31:13.44#ibcon#about to read 3, iclass 33, count 0 2006.281.07:31:13.46#ibcon#read 3, iclass 33, count 0 2006.281.07:31:13.46#ibcon#about to read 4, iclass 33, count 0 2006.281.07:31:13.46#ibcon#read 4, iclass 33, count 0 2006.281.07:31:13.46#ibcon#about to read 5, iclass 33, count 0 2006.281.07:31:13.46#ibcon#read 5, iclass 33, count 0 2006.281.07:31:13.46#ibcon#about to read 6, iclass 33, count 0 2006.281.07:31:13.46#ibcon#read 6, iclass 33, count 0 2006.281.07:31:13.46#ibcon#end of sib2, iclass 33, count 0 2006.281.07:31:13.46#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:31:13.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:31:13.46#ibcon#[27=USB\r\n] 2006.281.07:31:13.46#ibcon#*before write, iclass 33, count 0 2006.281.07:31:13.46#ibcon#enter sib2, iclass 33, count 0 2006.281.07:31:13.46#ibcon#flushed, iclass 33, count 0 2006.281.07:31:13.46#ibcon#about to write, iclass 33, count 0 2006.281.07:31:13.46#ibcon#wrote, iclass 33, count 0 2006.281.07:31:13.46#ibcon#about to read 3, iclass 33, count 0 2006.281.07:31:13.49#ibcon#read 3, iclass 33, count 0 2006.281.07:31:13.49#ibcon#about to read 4, iclass 33, count 0 2006.281.07:31:13.49#ibcon#read 4, iclass 33, count 0 2006.281.07:31:13.49#ibcon#about to read 5, iclass 33, count 0 2006.281.07:31:13.49#ibcon#read 5, iclass 33, count 0 2006.281.07:31:13.49#ibcon#about to read 6, iclass 33, count 0 2006.281.07:31:13.49#ibcon#read 6, iclass 33, count 0 2006.281.07:31:13.49#ibcon#end of sib2, iclass 33, count 0 2006.281.07:31:13.49#ibcon#*after write, iclass 33, count 0 2006.281.07:31:13.49#ibcon#*before return 0, iclass 33, count 0 2006.281.07:31:13.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:13.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:31:13.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:31:13.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:31:13.49$vc4f8/vblo=6,752.99 2006.281.07:31:13.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:31:13.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:31:13.49#ibcon#ireg 17 cls_cnt 0 2006.281.07:31:13.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:13.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:13.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:13.49#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:31:13.49#ibcon#first serial, iclass 35, count 0 2006.281.07:31:13.49#ibcon#enter sib2, iclass 35, count 0 2006.281.07:31:13.49#ibcon#flushed, iclass 35, count 0 2006.281.07:31:13.49#ibcon#about to write, iclass 35, count 0 2006.281.07:31:13.49#ibcon#wrote, iclass 35, count 0 2006.281.07:31:13.49#ibcon#about to read 3, iclass 35, count 0 2006.281.07:31:13.51#ibcon#read 3, iclass 35, count 0 2006.281.07:31:13.51#ibcon#about to read 4, iclass 35, count 0 2006.281.07:31:13.51#ibcon#read 4, iclass 35, count 0 2006.281.07:31:13.51#ibcon#about to read 5, iclass 35, count 0 2006.281.07:31:13.51#ibcon#read 5, iclass 35, count 0 2006.281.07:31:13.51#ibcon#about to read 6, iclass 35, count 0 2006.281.07:31:13.51#ibcon#read 6, iclass 35, count 0 2006.281.07:31:13.51#ibcon#end of sib2, iclass 35, count 0 2006.281.07:31:13.51#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:31:13.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:31:13.51#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:31:13.51#ibcon#*before write, iclass 35, count 0 2006.281.07:31:13.51#ibcon#enter sib2, iclass 35, count 0 2006.281.07:31:13.51#ibcon#flushed, iclass 35, count 0 2006.281.07:31:13.51#ibcon#about to write, iclass 35, count 0 2006.281.07:31:13.51#ibcon#wrote, iclass 35, count 0 2006.281.07:31:13.51#ibcon#about to read 3, iclass 35, count 0 2006.281.07:31:13.55#ibcon#read 3, iclass 35, count 0 2006.281.07:31:13.55#ibcon#about to read 4, iclass 35, count 0 2006.281.07:31:13.55#ibcon#read 4, iclass 35, count 0 2006.281.07:31:13.55#ibcon#about to read 5, iclass 35, count 0 2006.281.07:31:13.55#ibcon#read 5, iclass 35, count 0 2006.281.07:31:13.55#ibcon#about to read 6, iclass 35, count 0 2006.281.07:31:13.55#ibcon#read 6, iclass 35, count 0 2006.281.07:31:13.55#ibcon#end of sib2, iclass 35, count 0 2006.281.07:31:13.55#ibcon#*after write, iclass 35, count 0 2006.281.07:31:13.55#ibcon#*before return 0, iclass 35, count 0 2006.281.07:31:13.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:13.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:31:13.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:31:13.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:31:13.55$vc4f8/vb=6,4 2006.281.07:31:13.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:31:13.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:31:13.55#ibcon#ireg 11 cls_cnt 2 2006.281.07:31:13.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:13.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:13.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:13.61#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:31:13.61#ibcon#first serial, iclass 37, count 2 2006.281.07:31:13.61#ibcon#enter sib2, iclass 37, count 2 2006.281.07:31:13.61#ibcon#flushed, iclass 37, count 2 2006.281.07:31:13.61#ibcon#about to write, iclass 37, count 2 2006.281.07:31:13.61#ibcon#wrote, iclass 37, count 2 2006.281.07:31:13.61#ibcon#about to read 3, iclass 37, count 2 2006.281.07:31:13.63#ibcon#read 3, iclass 37, count 2 2006.281.07:31:13.63#ibcon#about to read 4, iclass 37, count 2 2006.281.07:31:13.63#ibcon#read 4, iclass 37, count 2 2006.281.07:31:13.63#ibcon#about to read 5, iclass 37, count 2 2006.281.07:31:13.63#ibcon#read 5, iclass 37, count 2 2006.281.07:31:13.63#ibcon#about to read 6, iclass 37, count 2 2006.281.07:31:13.63#ibcon#read 6, iclass 37, count 2 2006.281.07:31:13.63#ibcon#end of sib2, iclass 37, count 2 2006.281.07:31:13.63#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:31:13.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:31:13.63#ibcon#[27=AT06-04\r\n] 2006.281.07:31:13.63#ibcon#*before write, iclass 37, count 2 2006.281.07:31:13.63#ibcon#enter sib2, iclass 37, count 2 2006.281.07:31:13.63#ibcon#flushed, iclass 37, count 2 2006.281.07:31:13.63#ibcon#about to write, iclass 37, count 2 2006.281.07:31:13.63#ibcon#wrote, iclass 37, count 2 2006.281.07:31:13.63#ibcon#about to read 3, iclass 37, count 2 2006.281.07:31:13.66#ibcon#read 3, iclass 37, count 2 2006.281.07:31:13.66#ibcon#about to read 4, iclass 37, count 2 2006.281.07:31:13.66#ibcon#read 4, iclass 37, count 2 2006.281.07:31:13.66#ibcon#about to read 5, iclass 37, count 2 2006.281.07:31:13.66#ibcon#read 5, iclass 37, count 2 2006.281.07:31:13.66#ibcon#about to read 6, iclass 37, count 2 2006.281.07:31:13.66#ibcon#read 6, iclass 37, count 2 2006.281.07:31:13.66#ibcon#end of sib2, iclass 37, count 2 2006.281.07:31:13.66#ibcon#*after write, iclass 37, count 2 2006.281.07:31:13.66#ibcon#*before return 0, iclass 37, count 2 2006.281.07:31:13.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:13.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:31:13.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:31:13.66#ibcon#ireg 7 cls_cnt 0 2006.281.07:31:13.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:13.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:13.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:13.78#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:31:13.78#ibcon#first serial, iclass 37, count 0 2006.281.07:31:13.78#ibcon#enter sib2, iclass 37, count 0 2006.281.07:31:13.78#ibcon#flushed, iclass 37, count 0 2006.281.07:31:13.78#ibcon#about to write, iclass 37, count 0 2006.281.07:31:13.78#ibcon#wrote, iclass 37, count 0 2006.281.07:31:13.78#ibcon#about to read 3, iclass 37, count 0 2006.281.07:31:13.80#ibcon#read 3, iclass 37, count 0 2006.281.07:31:13.80#ibcon#about to read 4, iclass 37, count 0 2006.281.07:31:13.80#ibcon#read 4, iclass 37, count 0 2006.281.07:31:13.80#ibcon#about to read 5, iclass 37, count 0 2006.281.07:31:13.80#ibcon#read 5, iclass 37, count 0 2006.281.07:31:13.80#ibcon#about to read 6, iclass 37, count 0 2006.281.07:31:13.80#ibcon#read 6, iclass 37, count 0 2006.281.07:31:13.80#ibcon#end of sib2, iclass 37, count 0 2006.281.07:31:13.80#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:31:13.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:31:13.80#ibcon#[27=USB\r\n] 2006.281.07:31:13.80#ibcon#*before write, iclass 37, count 0 2006.281.07:31:13.80#ibcon#enter sib2, iclass 37, count 0 2006.281.07:31:13.80#ibcon#flushed, iclass 37, count 0 2006.281.07:31:13.80#ibcon#about to write, iclass 37, count 0 2006.281.07:31:13.80#ibcon#wrote, iclass 37, count 0 2006.281.07:31:13.80#ibcon#about to read 3, iclass 37, count 0 2006.281.07:31:13.83#ibcon#read 3, iclass 37, count 0 2006.281.07:31:13.83#ibcon#about to read 4, iclass 37, count 0 2006.281.07:31:13.83#ibcon#read 4, iclass 37, count 0 2006.281.07:31:13.83#ibcon#about to read 5, iclass 37, count 0 2006.281.07:31:13.83#ibcon#read 5, iclass 37, count 0 2006.281.07:31:13.83#ibcon#about to read 6, iclass 37, count 0 2006.281.07:31:13.83#ibcon#read 6, iclass 37, count 0 2006.281.07:31:13.83#ibcon#end of sib2, iclass 37, count 0 2006.281.07:31:13.83#ibcon#*after write, iclass 37, count 0 2006.281.07:31:13.83#ibcon#*before return 0, iclass 37, count 0 2006.281.07:31:13.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:13.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:31:13.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:31:13.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:31:13.83$vc4f8/vabw=wide 2006.281.07:31:13.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:31:13.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:31:13.83#ibcon#ireg 8 cls_cnt 0 2006.281.07:31:13.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:13.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:13.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:13.83#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:31:13.83#ibcon#first serial, iclass 39, count 0 2006.281.07:31:13.83#ibcon#enter sib2, iclass 39, count 0 2006.281.07:31:13.83#ibcon#flushed, iclass 39, count 0 2006.281.07:31:13.83#ibcon#about to write, iclass 39, count 0 2006.281.07:31:13.83#ibcon#wrote, iclass 39, count 0 2006.281.07:31:13.83#ibcon#about to read 3, iclass 39, count 0 2006.281.07:31:13.85#ibcon#read 3, iclass 39, count 0 2006.281.07:31:13.85#ibcon#about to read 4, iclass 39, count 0 2006.281.07:31:13.85#ibcon#read 4, iclass 39, count 0 2006.281.07:31:13.85#ibcon#about to read 5, iclass 39, count 0 2006.281.07:31:13.85#ibcon#read 5, iclass 39, count 0 2006.281.07:31:13.85#ibcon#about to read 6, iclass 39, count 0 2006.281.07:31:13.85#ibcon#read 6, iclass 39, count 0 2006.281.07:31:13.85#ibcon#end of sib2, iclass 39, count 0 2006.281.07:31:13.85#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:31:13.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:31:13.85#ibcon#[25=BW32\r\n] 2006.281.07:31:13.85#ibcon#*before write, iclass 39, count 0 2006.281.07:31:13.85#ibcon#enter sib2, iclass 39, count 0 2006.281.07:31:13.85#ibcon#flushed, iclass 39, count 0 2006.281.07:31:13.85#ibcon#about to write, iclass 39, count 0 2006.281.07:31:13.85#ibcon#wrote, iclass 39, count 0 2006.281.07:31:13.85#ibcon#about to read 3, iclass 39, count 0 2006.281.07:31:13.88#ibcon#read 3, iclass 39, count 0 2006.281.07:31:13.88#ibcon#about to read 4, iclass 39, count 0 2006.281.07:31:13.88#ibcon#read 4, iclass 39, count 0 2006.281.07:31:13.88#ibcon#about to read 5, iclass 39, count 0 2006.281.07:31:13.88#ibcon#read 5, iclass 39, count 0 2006.281.07:31:13.88#ibcon#about to read 6, iclass 39, count 0 2006.281.07:31:13.88#ibcon#read 6, iclass 39, count 0 2006.281.07:31:13.88#ibcon#end of sib2, iclass 39, count 0 2006.281.07:31:13.88#ibcon#*after write, iclass 39, count 0 2006.281.07:31:13.88#ibcon#*before return 0, iclass 39, count 0 2006.281.07:31:13.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:13.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:31:13.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:31:13.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:31:13.88$vc4f8/vbbw=wide 2006.281.07:31:13.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.07:31:13.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.07:31:13.90#ibcon#ireg 8 cls_cnt 0 2006.281.07:31:13.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:31:13.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:31:13.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:31:13.95#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:31:13.95#ibcon#first serial, iclass 3, count 0 2006.281.07:31:13.95#ibcon#enter sib2, iclass 3, count 0 2006.281.07:31:13.95#ibcon#flushed, iclass 3, count 0 2006.281.07:31:13.95#ibcon#about to write, iclass 3, count 0 2006.281.07:31:13.95#ibcon#wrote, iclass 3, count 0 2006.281.07:31:13.95#ibcon#about to read 3, iclass 3, count 0 2006.281.07:31:13.97#ibcon#read 3, iclass 3, count 0 2006.281.07:31:13.97#ibcon#about to read 4, iclass 3, count 0 2006.281.07:31:13.97#ibcon#read 4, iclass 3, count 0 2006.281.07:31:13.97#ibcon#about to read 5, iclass 3, count 0 2006.281.07:31:13.97#ibcon#read 5, iclass 3, count 0 2006.281.07:31:13.97#ibcon#about to read 6, iclass 3, count 0 2006.281.07:31:13.97#ibcon#read 6, iclass 3, count 0 2006.281.07:31:13.97#ibcon#end of sib2, iclass 3, count 0 2006.281.07:31:13.97#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:31:13.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:31:13.97#ibcon#[27=BW32\r\n] 2006.281.07:31:13.97#ibcon#*before write, iclass 3, count 0 2006.281.07:31:13.97#ibcon#enter sib2, iclass 3, count 0 2006.281.07:31:13.97#ibcon#flushed, iclass 3, count 0 2006.281.07:31:13.97#ibcon#about to write, iclass 3, count 0 2006.281.07:31:13.97#ibcon#wrote, iclass 3, count 0 2006.281.07:31:13.97#ibcon#about to read 3, iclass 3, count 0 2006.281.07:31:14.00#ibcon#read 3, iclass 3, count 0 2006.281.07:31:14.00#ibcon#about to read 4, iclass 3, count 0 2006.281.07:31:14.00#ibcon#read 4, iclass 3, count 0 2006.281.07:31:14.00#ibcon#about to read 5, iclass 3, count 0 2006.281.07:31:14.00#ibcon#read 5, iclass 3, count 0 2006.281.07:31:14.00#ibcon#about to read 6, iclass 3, count 0 2006.281.07:31:14.00#ibcon#read 6, iclass 3, count 0 2006.281.07:31:14.00#ibcon#end of sib2, iclass 3, count 0 2006.281.07:31:14.00#ibcon#*after write, iclass 3, count 0 2006.281.07:31:14.00#ibcon#*before return 0, iclass 3, count 0 2006.281.07:31:14.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:31:14.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:31:14.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:31:14.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:31:14.00$4f8m12a/ifd4f 2006.281.07:31:14.00$ifd4f/lo= 2006.281.07:31:14.00$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:31:14.00$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:31:14.01$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:31:14.01$ifd4f/patch= 2006.281.07:31:14.01$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:31:14.01$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:31:14.01$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:31:14.01$4f8m12a/"form=m,16.000,1:2 2006.281.07:31:14.01$4f8m12a/"tpicd 2006.281.07:31:14.01$4f8m12a/echo=off 2006.281.07:31:14.01$4f8m12a/xlog=off 2006.281.07:31:14.01:!2006.281.07:33:20 2006.281.07:31:39.14#trakl#Source acquired 2006.281.07:31:40.14#flagr#flagr/antenna,acquired 2006.281.07:32:09.14#trakl#Off source 2006.281.07:32:09.14?ERROR st -7 Antenna off-source! 2006.281.07:32:09.14#trakl#az 38.661 el 12.329 azerr*cos(el) 0.0175 elerr -0.0031 2006.281.07:32:10.14#flagr#flagr/antenna,off-source 2006.281.07:32:15.14#trakl#Source re-acquired 2006.281.07:32:16.13#flagr#flagr/antenna,re-acquired 2006.281.07:32:22.13#trakl#Off source 2006.281.07:32:22.13?ERROR st -7 Antenna off-source! 2006.281.07:32:22.13#trakl#az 38.686 el 12.356 azerr*cos(el) -0.0035 elerr 0.0206 2006.281.07:32:22.13#flagr#flagr/antenna,off-source 2006.281.07:32:29.13#trakl#Source re-acquired 2006.281.07:32:31.13#flagr#flagr/antenna,re-acquired 2006.281.07:33:14.13#trakl#Off source 2006.281.07:33:14.13?ERROR st -7 Antenna off-source! 2006.281.07:33:14.13#trakl#az 38.784 el 12.465 azerr*cos(el) -0.0103 elerr 0.0195 2006.281.07:33:16.13#flagr#flagr/antenna,off-source 2006.281.07:33:20.00:preob 2006.281.07:33:20.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:33:20.13?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:33:20.13/onsource/SLEWING 2006.281.07:33:20.13:!2006.281.07:33:30 2006.281.07:33:22.13#trakl#Source re-acquired 2006.281.07:33:24.13#flagr#flagr/antenna,re-acquired 2006.281.07:33:30.00:data_valid=on 2006.281.07:33:30.00:midob 2006.281.07:33:31.13/onsource/TRACKING 2006.281.07:33:31.13/wx/21.41,1001.0,49 2006.281.07:33:31.27/cable/+6.4838E-03 2006.281.07:33:32.36/va/01,07,usb,yes,36,38 2006.281.07:33:32.36/va/02,06,usb,yes,34,35 2006.281.07:33:32.36/va/03,06,usb,yes,32,32 2006.281.07:33:32.36/va/04,06,usb,yes,35,37 2006.281.07:33:32.36/va/05,07,usb,yes,32,34 2006.281.07:33:32.36/va/06,06,usb,yes,31,31 2006.281.07:33:32.36/va/07,06,usb,yes,32,32 2006.281.07:33:32.36/va/08,06,usb,yes,34,34 2006.281.07:33:32.59/valo/01,532.99,yes,locked 2006.281.07:33:32.59/valo/02,572.99,yes,locked 2006.281.07:33:32.59/valo/03,672.99,yes,locked 2006.281.07:33:32.59/valo/04,832.99,yes,locked 2006.281.07:33:32.59/valo/05,652.99,yes,locked 2006.281.07:33:32.59/valo/06,772.99,yes,locked 2006.281.07:33:32.59/valo/07,832.99,yes,locked 2006.281.07:33:32.59/valo/08,852.99,yes,locked 2006.281.07:33:33.68/vb/01,04,usb,yes,32,31 2006.281.07:33:33.68/vb/02,05,usb,yes,30,31 2006.281.07:33:33.68/vb/03,04,usb,yes,30,35 2006.281.07:33:33.68/vb/04,04,usb,yes,32,32 2006.281.07:33:33.68/vb/05,04,usb,yes,29,34 2006.281.07:33:33.68/vb/06,04,usb,yes,30,34 2006.281.07:33:33.68/vb/07,04,usb,yes,33,33 2006.281.07:33:33.68/vb/08,04,usb,yes,30,34 2006.281.07:33:33.91/vblo/01,632.99,yes,locked 2006.281.07:33:33.91/vblo/02,640.99,yes,locked 2006.281.07:33:33.91/vblo/03,656.99,yes,locked 2006.281.07:33:33.91/vblo/04,712.99,yes,locked 2006.281.07:33:33.91/vblo/05,744.99,yes,locked 2006.281.07:33:33.91/vblo/06,752.99,yes,locked 2006.281.07:33:33.91/vblo/07,734.99,yes,locked 2006.281.07:33:33.91/vblo/08,744.99,yes,locked 2006.281.07:33:34.06/vabw/8 2006.281.07:33:34.21/vbbw/8 2006.281.07:33:34.30/xfe/off,on,12.0 2006.281.07:33:34.69/ifatt/23,28,28,28 2006.281.07:33:35.08/fmout-gps/S +3.11E-07 2006.281.07:33:35.10:!2006.281.07:34:30 2006.281.07:34:30.00:data_valid=off 2006.281.07:34:30.00:postob 2006.281.07:34:30.23/cable/+6.4841E-03 2006.281.07:34:30.23/wx/21.37,1001.0,49 2006.281.07:34:31.08/fmout-gps/S +3.10E-07 2006.281.07:34:31.08:scan_name=281-0735,k06281,60 2006.281.07:34:31.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.281.07:34:31.14#flagr#flagr/antenna,new-source 2006.281.07:34:32.14:checkk5 2006.281.07:34:32.58/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:34:33.00/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:34:33.41/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:34:33.80/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:34:34.26/chk_obsdata//k5ts1/T2810733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:34:34.67/chk_obsdata//k5ts2/T2810733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:34:35.10/chk_obsdata//k5ts3/T2810733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:34:35.55/chk_obsdata//k5ts4/T2810733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:34:36.38/k5log//k5ts1_log_newline 2006.281.07:34:37.18/k5log//k5ts2_log_newline 2006.281.07:34:38.14/k5log//k5ts3_log_newline 2006.281.07:34:38.94/k5log//k5ts4_log_newline 2006.281.07:34:38.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:34:38.96:4f8m12a=1 2006.281.07:34:38.96$4f8m12a/echo=on 2006.281.07:34:38.96$4f8m12a/pcalon 2006.281.07:34:38.96$pcalon/"no phase cal control is implemented here 2006.281.07:34:38.96$4f8m12a/"tpicd=stop 2006.281.07:34:38.96$4f8m12a/vc4f8 2006.281.07:34:38.96$vc4f8/valo=1,532.99 2006.281.07:34:38.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:34:38.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:34:38.96#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:38.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:38.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:38.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:38.96#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:34:38.96#ibcon#first serial, iclass 26, count 0 2006.281.07:34:38.96#ibcon#enter sib2, iclass 26, count 0 2006.281.07:34:38.96#ibcon#flushed, iclass 26, count 0 2006.281.07:34:38.96#ibcon#about to write, iclass 26, count 0 2006.281.07:34:38.96#ibcon#wrote, iclass 26, count 0 2006.281.07:34:38.96#ibcon#about to read 3, iclass 26, count 0 2006.281.07:34:38.98#ibcon#read 3, iclass 26, count 0 2006.281.07:34:38.98#ibcon#about to read 4, iclass 26, count 0 2006.281.07:34:38.98#ibcon#read 4, iclass 26, count 0 2006.281.07:34:38.98#ibcon#about to read 5, iclass 26, count 0 2006.281.07:34:38.98#ibcon#read 5, iclass 26, count 0 2006.281.07:34:38.98#ibcon#about to read 6, iclass 26, count 0 2006.281.07:34:38.98#ibcon#read 6, iclass 26, count 0 2006.281.07:34:38.98#ibcon#end of sib2, iclass 26, count 0 2006.281.07:34:38.98#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:34:38.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:34:38.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:34:38.98#ibcon#*before write, iclass 26, count 0 2006.281.07:34:38.98#ibcon#enter sib2, iclass 26, count 0 2006.281.07:34:38.98#ibcon#flushed, iclass 26, count 0 2006.281.07:34:38.98#ibcon#about to write, iclass 26, count 0 2006.281.07:34:38.98#ibcon#wrote, iclass 26, count 0 2006.281.07:34:38.98#ibcon#about to read 3, iclass 26, count 0 2006.281.07:34:39.03#ibcon#read 3, iclass 26, count 0 2006.281.07:34:39.03#ibcon#about to read 4, iclass 26, count 0 2006.281.07:34:39.03#ibcon#read 4, iclass 26, count 0 2006.281.07:34:39.03#ibcon#about to read 5, iclass 26, count 0 2006.281.07:34:39.03#ibcon#read 5, iclass 26, count 0 2006.281.07:34:39.03#ibcon#about to read 6, iclass 26, count 0 2006.281.07:34:39.03#ibcon#read 6, iclass 26, count 0 2006.281.07:34:39.03#ibcon#end of sib2, iclass 26, count 0 2006.281.07:34:39.03#ibcon#*after write, iclass 26, count 0 2006.281.07:34:39.03#ibcon#*before return 0, iclass 26, count 0 2006.281.07:34:39.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:39.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:39.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:34:39.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:34:39.03$vc4f8/va=1,7 2006.281.07:34:39.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:34:39.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:34:39.03#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:39.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:39.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:39.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:39.03#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:34:39.03#ibcon#first serial, iclass 28, count 2 2006.281.07:34:39.03#ibcon#enter sib2, iclass 28, count 2 2006.281.07:34:39.03#ibcon#flushed, iclass 28, count 2 2006.281.07:34:39.03#ibcon#about to write, iclass 28, count 2 2006.281.07:34:39.03#ibcon#wrote, iclass 28, count 2 2006.281.07:34:39.03#ibcon#about to read 3, iclass 28, count 2 2006.281.07:34:39.05#ibcon#read 3, iclass 28, count 2 2006.281.07:34:39.05#ibcon#about to read 4, iclass 28, count 2 2006.281.07:34:39.05#ibcon#read 4, iclass 28, count 2 2006.281.07:34:39.05#ibcon#about to read 5, iclass 28, count 2 2006.281.07:34:39.05#ibcon#read 5, iclass 28, count 2 2006.281.07:34:39.05#ibcon#about to read 6, iclass 28, count 2 2006.281.07:34:39.05#ibcon#read 6, iclass 28, count 2 2006.281.07:34:39.05#ibcon#end of sib2, iclass 28, count 2 2006.281.07:34:39.05#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:34:39.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:34:39.05#ibcon#[25=AT01-07\r\n] 2006.281.07:34:39.05#ibcon#*before write, iclass 28, count 2 2006.281.07:34:39.05#ibcon#enter sib2, iclass 28, count 2 2006.281.07:34:39.05#ibcon#flushed, iclass 28, count 2 2006.281.07:34:39.05#ibcon#about to write, iclass 28, count 2 2006.281.07:34:39.05#ibcon#wrote, iclass 28, count 2 2006.281.07:34:39.05#ibcon#about to read 3, iclass 28, count 2 2006.281.07:34:39.08#ibcon#read 3, iclass 28, count 2 2006.281.07:34:39.08#ibcon#about to read 4, iclass 28, count 2 2006.281.07:34:39.08#ibcon#read 4, iclass 28, count 2 2006.281.07:34:39.08#ibcon#about to read 5, iclass 28, count 2 2006.281.07:34:39.08#ibcon#read 5, iclass 28, count 2 2006.281.07:34:39.08#ibcon#about to read 6, iclass 28, count 2 2006.281.07:34:39.08#ibcon#read 6, iclass 28, count 2 2006.281.07:34:39.08#ibcon#end of sib2, iclass 28, count 2 2006.281.07:34:39.08#ibcon#*after write, iclass 28, count 2 2006.281.07:34:39.08#ibcon#*before return 0, iclass 28, count 2 2006.281.07:34:39.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:39.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:39.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:34:39.08#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:39.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:39.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:39.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:39.20#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:34:39.20#ibcon#first serial, iclass 28, count 0 2006.281.07:34:39.20#ibcon#enter sib2, iclass 28, count 0 2006.281.07:34:39.20#ibcon#flushed, iclass 28, count 0 2006.281.07:34:39.20#ibcon#about to write, iclass 28, count 0 2006.281.07:34:39.20#ibcon#wrote, iclass 28, count 0 2006.281.07:34:39.20#ibcon#about to read 3, iclass 28, count 0 2006.281.07:34:39.22#ibcon#read 3, iclass 28, count 0 2006.281.07:34:39.22#ibcon#about to read 4, iclass 28, count 0 2006.281.07:34:39.22#ibcon#read 4, iclass 28, count 0 2006.281.07:34:39.22#ibcon#about to read 5, iclass 28, count 0 2006.281.07:34:39.22#ibcon#read 5, iclass 28, count 0 2006.281.07:34:39.22#ibcon#about to read 6, iclass 28, count 0 2006.281.07:34:39.22#ibcon#read 6, iclass 28, count 0 2006.281.07:34:39.22#ibcon#end of sib2, iclass 28, count 0 2006.281.07:34:39.22#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:34:39.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:34:39.22#ibcon#[25=USB\r\n] 2006.281.07:34:39.22#ibcon#*before write, iclass 28, count 0 2006.281.07:34:39.22#ibcon#enter sib2, iclass 28, count 0 2006.281.07:34:39.22#ibcon#flushed, iclass 28, count 0 2006.281.07:34:39.22#ibcon#about to write, iclass 28, count 0 2006.281.07:34:39.22#ibcon#wrote, iclass 28, count 0 2006.281.07:34:39.22#ibcon#about to read 3, iclass 28, count 0 2006.281.07:34:39.25#ibcon#read 3, iclass 28, count 0 2006.281.07:34:39.25#ibcon#about to read 4, iclass 28, count 0 2006.281.07:34:39.25#ibcon#read 4, iclass 28, count 0 2006.281.07:34:39.25#ibcon#about to read 5, iclass 28, count 0 2006.281.07:34:39.25#ibcon#read 5, iclass 28, count 0 2006.281.07:34:39.25#ibcon#about to read 6, iclass 28, count 0 2006.281.07:34:39.25#ibcon#read 6, iclass 28, count 0 2006.281.07:34:39.25#ibcon#end of sib2, iclass 28, count 0 2006.281.07:34:39.25#ibcon#*after write, iclass 28, count 0 2006.281.07:34:39.25#ibcon#*before return 0, iclass 28, count 0 2006.281.07:34:39.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:39.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:39.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:34:39.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:34:39.25$vc4f8/valo=2,572.99 2006.281.07:34:39.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:34:39.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:34:39.25#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:39.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:39.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:39.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:39.25#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:34:39.25#ibcon#first serial, iclass 30, count 0 2006.281.07:34:39.25#ibcon#enter sib2, iclass 30, count 0 2006.281.07:34:39.25#ibcon#flushed, iclass 30, count 0 2006.281.07:34:39.25#ibcon#about to write, iclass 30, count 0 2006.281.07:34:39.25#ibcon#wrote, iclass 30, count 0 2006.281.07:34:39.25#ibcon#about to read 3, iclass 30, count 0 2006.281.07:34:39.27#ibcon#read 3, iclass 30, count 0 2006.281.07:34:39.27#ibcon#about to read 4, iclass 30, count 0 2006.281.07:34:39.27#ibcon#read 4, iclass 30, count 0 2006.281.07:34:39.27#ibcon#about to read 5, iclass 30, count 0 2006.281.07:34:39.27#ibcon#read 5, iclass 30, count 0 2006.281.07:34:39.27#ibcon#about to read 6, iclass 30, count 0 2006.281.07:34:39.27#ibcon#read 6, iclass 30, count 0 2006.281.07:34:39.27#ibcon#end of sib2, iclass 30, count 0 2006.281.07:34:39.27#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:34:39.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:34:39.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:34:39.27#ibcon#*before write, iclass 30, count 0 2006.281.07:34:39.27#ibcon#enter sib2, iclass 30, count 0 2006.281.07:34:39.27#ibcon#flushed, iclass 30, count 0 2006.281.07:34:39.27#ibcon#about to write, iclass 30, count 0 2006.281.07:34:39.27#ibcon#wrote, iclass 30, count 0 2006.281.07:34:39.27#ibcon#about to read 3, iclass 30, count 0 2006.281.07:34:39.31#ibcon#read 3, iclass 30, count 0 2006.281.07:34:39.31#ibcon#about to read 4, iclass 30, count 0 2006.281.07:34:39.31#ibcon#read 4, iclass 30, count 0 2006.281.07:34:39.31#ibcon#about to read 5, iclass 30, count 0 2006.281.07:34:39.31#ibcon#read 5, iclass 30, count 0 2006.281.07:34:39.31#ibcon#about to read 6, iclass 30, count 0 2006.281.07:34:39.31#ibcon#read 6, iclass 30, count 0 2006.281.07:34:39.31#ibcon#end of sib2, iclass 30, count 0 2006.281.07:34:39.31#ibcon#*after write, iclass 30, count 0 2006.281.07:34:39.31#ibcon#*before return 0, iclass 30, count 0 2006.281.07:34:39.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:39.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:39.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:34:39.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:34:39.31$vc4f8/va=2,6 2006.281.07:34:39.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:34:39.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:34:39.31#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:39.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:39.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:39.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:39.37#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:34:39.37#ibcon#first serial, iclass 32, count 2 2006.281.07:34:39.37#ibcon#enter sib2, iclass 32, count 2 2006.281.07:34:39.37#ibcon#flushed, iclass 32, count 2 2006.281.07:34:39.37#ibcon#about to write, iclass 32, count 2 2006.281.07:34:39.37#ibcon#wrote, iclass 32, count 2 2006.281.07:34:39.37#ibcon#about to read 3, iclass 32, count 2 2006.281.07:34:39.39#ibcon#read 3, iclass 32, count 2 2006.281.07:34:39.39#ibcon#about to read 4, iclass 32, count 2 2006.281.07:34:39.39#ibcon#read 4, iclass 32, count 2 2006.281.07:34:39.39#ibcon#about to read 5, iclass 32, count 2 2006.281.07:34:39.39#ibcon#read 5, iclass 32, count 2 2006.281.07:34:39.39#ibcon#about to read 6, iclass 32, count 2 2006.281.07:34:39.39#ibcon#read 6, iclass 32, count 2 2006.281.07:34:39.39#ibcon#end of sib2, iclass 32, count 2 2006.281.07:34:39.39#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:34:39.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:34:39.39#ibcon#[25=AT02-06\r\n] 2006.281.07:34:39.39#ibcon#*before write, iclass 32, count 2 2006.281.07:34:39.39#ibcon#enter sib2, iclass 32, count 2 2006.281.07:34:39.39#ibcon#flushed, iclass 32, count 2 2006.281.07:34:39.39#ibcon#about to write, iclass 32, count 2 2006.281.07:34:39.39#ibcon#wrote, iclass 32, count 2 2006.281.07:34:39.39#ibcon#about to read 3, iclass 32, count 2 2006.281.07:34:39.42#ibcon#read 3, iclass 32, count 2 2006.281.07:34:39.42#ibcon#about to read 4, iclass 32, count 2 2006.281.07:34:39.42#ibcon#read 4, iclass 32, count 2 2006.281.07:34:39.42#ibcon#about to read 5, iclass 32, count 2 2006.281.07:34:39.42#ibcon#read 5, iclass 32, count 2 2006.281.07:34:39.42#ibcon#about to read 6, iclass 32, count 2 2006.281.07:34:39.42#ibcon#read 6, iclass 32, count 2 2006.281.07:34:39.42#ibcon#end of sib2, iclass 32, count 2 2006.281.07:34:39.42#ibcon#*after write, iclass 32, count 2 2006.281.07:34:39.42#ibcon#*before return 0, iclass 32, count 2 2006.281.07:34:39.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:39.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:39.42#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:34:39.42#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:39.42#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:39.54#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:39.54#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:39.54#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:34:39.54#ibcon#first serial, iclass 32, count 0 2006.281.07:34:39.54#ibcon#enter sib2, iclass 32, count 0 2006.281.07:34:39.54#ibcon#flushed, iclass 32, count 0 2006.281.07:34:39.54#ibcon#about to write, iclass 32, count 0 2006.281.07:34:39.54#ibcon#wrote, iclass 32, count 0 2006.281.07:34:39.54#ibcon#about to read 3, iclass 32, count 0 2006.281.07:34:39.56#ibcon#read 3, iclass 32, count 0 2006.281.07:34:39.56#ibcon#about to read 4, iclass 32, count 0 2006.281.07:34:39.56#ibcon#read 4, iclass 32, count 0 2006.281.07:34:39.56#ibcon#about to read 5, iclass 32, count 0 2006.281.07:34:39.56#ibcon#read 5, iclass 32, count 0 2006.281.07:34:39.56#ibcon#about to read 6, iclass 32, count 0 2006.281.07:34:39.56#ibcon#read 6, iclass 32, count 0 2006.281.07:34:39.56#ibcon#end of sib2, iclass 32, count 0 2006.281.07:34:39.56#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:34:39.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:34:39.56#ibcon#[25=USB\r\n] 2006.281.07:34:39.56#ibcon#*before write, iclass 32, count 0 2006.281.07:34:39.56#ibcon#enter sib2, iclass 32, count 0 2006.281.07:34:39.56#ibcon#flushed, iclass 32, count 0 2006.281.07:34:39.56#ibcon#about to write, iclass 32, count 0 2006.281.07:34:39.56#ibcon#wrote, iclass 32, count 0 2006.281.07:34:39.56#ibcon#about to read 3, iclass 32, count 0 2006.281.07:34:39.59#ibcon#read 3, iclass 32, count 0 2006.281.07:34:39.59#ibcon#about to read 4, iclass 32, count 0 2006.281.07:34:39.59#ibcon#read 4, iclass 32, count 0 2006.281.07:34:39.59#ibcon#about to read 5, iclass 32, count 0 2006.281.07:34:39.59#ibcon#read 5, iclass 32, count 0 2006.281.07:34:39.59#ibcon#about to read 6, iclass 32, count 0 2006.281.07:34:39.59#ibcon#read 6, iclass 32, count 0 2006.281.07:34:39.59#ibcon#end of sib2, iclass 32, count 0 2006.281.07:34:39.59#ibcon#*after write, iclass 32, count 0 2006.281.07:34:39.59#ibcon#*before return 0, iclass 32, count 0 2006.281.07:34:39.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:39.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:39.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:34:39.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:34:39.59$vc4f8/valo=3,672.99 2006.281.07:34:39.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:34:39.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:34:39.59#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:39.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:39.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:39.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:39.59#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:34:39.59#ibcon#first serial, iclass 34, count 0 2006.281.07:34:39.59#ibcon#enter sib2, iclass 34, count 0 2006.281.07:34:39.59#ibcon#flushed, iclass 34, count 0 2006.281.07:34:39.59#ibcon#about to write, iclass 34, count 0 2006.281.07:34:39.59#ibcon#wrote, iclass 34, count 0 2006.281.07:34:39.59#ibcon#about to read 3, iclass 34, count 0 2006.281.07:34:39.61#ibcon#read 3, iclass 34, count 0 2006.281.07:34:39.61#ibcon#about to read 4, iclass 34, count 0 2006.281.07:34:39.61#ibcon#read 4, iclass 34, count 0 2006.281.07:34:39.61#ibcon#about to read 5, iclass 34, count 0 2006.281.07:34:39.61#ibcon#read 5, iclass 34, count 0 2006.281.07:34:39.61#ibcon#about to read 6, iclass 34, count 0 2006.281.07:34:39.61#ibcon#read 6, iclass 34, count 0 2006.281.07:34:39.61#ibcon#end of sib2, iclass 34, count 0 2006.281.07:34:39.61#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:34:39.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:34:39.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:34:39.61#ibcon#*before write, iclass 34, count 0 2006.281.07:34:39.61#ibcon#enter sib2, iclass 34, count 0 2006.281.07:34:39.61#ibcon#flushed, iclass 34, count 0 2006.281.07:34:39.61#ibcon#about to write, iclass 34, count 0 2006.281.07:34:39.61#ibcon#wrote, iclass 34, count 0 2006.281.07:34:39.61#ibcon#about to read 3, iclass 34, count 0 2006.281.07:34:39.65#ibcon#read 3, iclass 34, count 0 2006.281.07:34:39.65#ibcon#about to read 4, iclass 34, count 0 2006.281.07:34:39.65#ibcon#read 4, iclass 34, count 0 2006.281.07:34:39.65#ibcon#about to read 5, iclass 34, count 0 2006.281.07:34:39.65#ibcon#read 5, iclass 34, count 0 2006.281.07:34:39.65#ibcon#about to read 6, iclass 34, count 0 2006.281.07:34:39.65#ibcon#read 6, iclass 34, count 0 2006.281.07:34:39.65#ibcon#end of sib2, iclass 34, count 0 2006.281.07:34:39.65#ibcon#*after write, iclass 34, count 0 2006.281.07:34:39.65#ibcon#*before return 0, iclass 34, count 0 2006.281.07:34:39.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:39.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:39.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:34:39.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:34:39.65$vc4f8/va=3,6 2006.281.07:34:39.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:34:39.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:34:39.65#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:39.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:39.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:39.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:39.71#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:34:39.71#ibcon#first serial, iclass 36, count 2 2006.281.07:34:39.71#ibcon#enter sib2, iclass 36, count 2 2006.281.07:34:39.71#ibcon#flushed, iclass 36, count 2 2006.281.07:34:39.71#ibcon#about to write, iclass 36, count 2 2006.281.07:34:39.71#ibcon#wrote, iclass 36, count 2 2006.281.07:34:39.71#ibcon#about to read 3, iclass 36, count 2 2006.281.07:34:39.73#ibcon#read 3, iclass 36, count 2 2006.281.07:34:39.73#ibcon#about to read 4, iclass 36, count 2 2006.281.07:34:39.73#ibcon#read 4, iclass 36, count 2 2006.281.07:34:39.73#ibcon#about to read 5, iclass 36, count 2 2006.281.07:34:39.73#ibcon#read 5, iclass 36, count 2 2006.281.07:34:39.73#ibcon#about to read 6, iclass 36, count 2 2006.281.07:34:39.73#ibcon#read 6, iclass 36, count 2 2006.281.07:34:39.73#ibcon#end of sib2, iclass 36, count 2 2006.281.07:34:39.73#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:34:39.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:34:39.73#ibcon#[25=AT03-06\r\n] 2006.281.07:34:39.73#ibcon#*before write, iclass 36, count 2 2006.281.07:34:39.73#ibcon#enter sib2, iclass 36, count 2 2006.281.07:34:39.73#ibcon#flushed, iclass 36, count 2 2006.281.07:34:39.73#ibcon#about to write, iclass 36, count 2 2006.281.07:34:39.73#ibcon#wrote, iclass 36, count 2 2006.281.07:34:39.73#ibcon#about to read 3, iclass 36, count 2 2006.281.07:34:39.76#ibcon#read 3, iclass 36, count 2 2006.281.07:34:39.76#ibcon#about to read 4, iclass 36, count 2 2006.281.07:34:39.76#ibcon#read 4, iclass 36, count 2 2006.281.07:34:39.76#ibcon#about to read 5, iclass 36, count 2 2006.281.07:34:39.76#ibcon#read 5, iclass 36, count 2 2006.281.07:34:39.76#ibcon#about to read 6, iclass 36, count 2 2006.281.07:34:39.76#ibcon#read 6, iclass 36, count 2 2006.281.07:34:39.76#ibcon#end of sib2, iclass 36, count 2 2006.281.07:34:39.76#ibcon#*after write, iclass 36, count 2 2006.281.07:34:39.76#ibcon#*before return 0, iclass 36, count 2 2006.281.07:34:39.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:39.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:39.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:34:39.76#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:39.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:39.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:39.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:39.88#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:34:39.88#ibcon#first serial, iclass 36, count 0 2006.281.07:34:39.88#ibcon#enter sib2, iclass 36, count 0 2006.281.07:34:39.88#ibcon#flushed, iclass 36, count 0 2006.281.07:34:39.88#ibcon#about to write, iclass 36, count 0 2006.281.07:34:39.88#ibcon#wrote, iclass 36, count 0 2006.281.07:34:39.88#ibcon#about to read 3, iclass 36, count 0 2006.281.07:34:39.90#ibcon#read 3, iclass 36, count 0 2006.281.07:34:39.90#ibcon#about to read 4, iclass 36, count 0 2006.281.07:34:39.90#ibcon#read 4, iclass 36, count 0 2006.281.07:34:39.90#ibcon#about to read 5, iclass 36, count 0 2006.281.07:34:39.90#ibcon#read 5, iclass 36, count 0 2006.281.07:34:39.90#ibcon#about to read 6, iclass 36, count 0 2006.281.07:34:39.90#ibcon#read 6, iclass 36, count 0 2006.281.07:34:39.90#ibcon#end of sib2, iclass 36, count 0 2006.281.07:34:39.90#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:34:39.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:34:39.90#ibcon#[25=USB\r\n] 2006.281.07:34:39.90#ibcon#*before write, iclass 36, count 0 2006.281.07:34:39.90#ibcon#enter sib2, iclass 36, count 0 2006.281.07:34:39.90#ibcon#flushed, iclass 36, count 0 2006.281.07:34:39.90#ibcon#about to write, iclass 36, count 0 2006.281.07:34:39.90#ibcon#wrote, iclass 36, count 0 2006.281.07:34:39.90#ibcon#about to read 3, iclass 36, count 0 2006.281.07:34:39.93#ibcon#read 3, iclass 36, count 0 2006.281.07:34:39.93#ibcon#about to read 4, iclass 36, count 0 2006.281.07:34:39.93#ibcon#read 4, iclass 36, count 0 2006.281.07:34:39.93#ibcon#about to read 5, iclass 36, count 0 2006.281.07:34:39.93#ibcon#read 5, iclass 36, count 0 2006.281.07:34:39.93#ibcon#about to read 6, iclass 36, count 0 2006.281.07:34:39.93#ibcon#read 6, iclass 36, count 0 2006.281.07:34:39.93#ibcon#end of sib2, iclass 36, count 0 2006.281.07:34:39.93#ibcon#*after write, iclass 36, count 0 2006.281.07:34:39.93#ibcon#*before return 0, iclass 36, count 0 2006.281.07:34:39.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:39.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:39.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:34:39.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:34:39.93$vc4f8/valo=4,832.99 2006.281.07:34:39.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:34:39.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:34:39.93#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:39.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:39.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:39.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:39.93#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:34:39.93#ibcon#first serial, iclass 38, count 0 2006.281.07:34:39.93#ibcon#enter sib2, iclass 38, count 0 2006.281.07:34:39.93#ibcon#flushed, iclass 38, count 0 2006.281.07:34:39.93#ibcon#about to write, iclass 38, count 0 2006.281.07:34:39.93#ibcon#wrote, iclass 38, count 0 2006.281.07:34:39.93#ibcon#about to read 3, iclass 38, count 0 2006.281.07:34:39.95#ibcon#read 3, iclass 38, count 0 2006.281.07:34:39.95#ibcon#about to read 4, iclass 38, count 0 2006.281.07:34:39.95#ibcon#read 4, iclass 38, count 0 2006.281.07:34:39.95#ibcon#about to read 5, iclass 38, count 0 2006.281.07:34:39.95#ibcon#read 5, iclass 38, count 0 2006.281.07:34:39.95#ibcon#about to read 6, iclass 38, count 0 2006.281.07:34:39.95#ibcon#read 6, iclass 38, count 0 2006.281.07:34:39.95#ibcon#end of sib2, iclass 38, count 0 2006.281.07:34:39.95#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:34:39.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:34:39.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:34:39.97#ibcon#*before write, iclass 38, count 0 2006.281.07:34:39.97#ibcon#enter sib2, iclass 38, count 0 2006.281.07:34:39.97#ibcon#flushed, iclass 38, count 0 2006.281.07:34:39.97#ibcon#about to write, iclass 38, count 0 2006.281.07:34:39.97#ibcon#wrote, iclass 38, count 0 2006.281.07:34:39.97#ibcon#about to read 3, iclass 38, count 0 2006.281.07:34:40.01#ibcon#read 3, iclass 38, count 0 2006.281.07:34:40.01#ibcon#about to read 4, iclass 38, count 0 2006.281.07:34:40.01#ibcon#read 4, iclass 38, count 0 2006.281.07:34:40.01#ibcon#about to read 5, iclass 38, count 0 2006.281.07:34:40.01#ibcon#read 5, iclass 38, count 0 2006.281.07:34:40.01#ibcon#about to read 6, iclass 38, count 0 2006.281.07:34:40.01#ibcon#read 6, iclass 38, count 0 2006.281.07:34:40.01#ibcon#end of sib2, iclass 38, count 0 2006.281.07:34:40.01#ibcon#*after write, iclass 38, count 0 2006.281.07:34:40.01#ibcon#*before return 0, iclass 38, count 0 2006.281.07:34:40.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:40.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:40.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:34:40.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:34:40.01$vc4f8/va=4,6 2006.281.07:34:40.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:34:40.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:34:40.01#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:40.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:40.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:40.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:40.05#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:34:40.05#ibcon#first serial, iclass 40, count 2 2006.281.07:34:40.05#ibcon#enter sib2, iclass 40, count 2 2006.281.07:34:40.05#ibcon#flushed, iclass 40, count 2 2006.281.07:34:40.05#ibcon#about to write, iclass 40, count 2 2006.281.07:34:40.05#ibcon#wrote, iclass 40, count 2 2006.281.07:34:40.05#ibcon#about to read 3, iclass 40, count 2 2006.281.07:34:40.07#ibcon#read 3, iclass 40, count 2 2006.281.07:34:40.07#ibcon#about to read 4, iclass 40, count 2 2006.281.07:34:40.07#ibcon#read 4, iclass 40, count 2 2006.281.07:34:40.07#ibcon#about to read 5, iclass 40, count 2 2006.281.07:34:40.07#ibcon#read 5, iclass 40, count 2 2006.281.07:34:40.07#ibcon#about to read 6, iclass 40, count 2 2006.281.07:34:40.07#ibcon#read 6, iclass 40, count 2 2006.281.07:34:40.07#ibcon#end of sib2, iclass 40, count 2 2006.281.07:34:40.07#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:34:40.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:34:40.07#ibcon#[25=AT04-06\r\n] 2006.281.07:34:40.07#ibcon#*before write, iclass 40, count 2 2006.281.07:34:40.07#ibcon#enter sib2, iclass 40, count 2 2006.281.07:34:40.07#ibcon#flushed, iclass 40, count 2 2006.281.07:34:40.07#ibcon#about to write, iclass 40, count 2 2006.281.07:34:40.07#ibcon#wrote, iclass 40, count 2 2006.281.07:34:40.07#ibcon#about to read 3, iclass 40, count 2 2006.281.07:34:40.10#ibcon#read 3, iclass 40, count 2 2006.281.07:34:40.10#ibcon#about to read 4, iclass 40, count 2 2006.281.07:34:40.10#ibcon#read 4, iclass 40, count 2 2006.281.07:34:40.10#ibcon#about to read 5, iclass 40, count 2 2006.281.07:34:40.10#ibcon#read 5, iclass 40, count 2 2006.281.07:34:40.10#ibcon#about to read 6, iclass 40, count 2 2006.281.07:34:40.10#ibcon#read 6, iclass 40, count 2 2006.281.07:34:40.10#ibcon#end of sib2, iclass 40, count 2 2006.281.07:34:40.10#ibcon#*after write, iclass 40, count 2 2006.281.07:34:40.10#ibcon#*before return 0, iclass 40, count 2 2006.281.07:34:40.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:40.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:40.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:34:40.10#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:40.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:40.19#abcon#<5=/12 2.310.2 21.36 491001.0\r\n> 2006.281.07:34:40.21#abcon#{5=INTERFACE CLEAR} 2006.281.07:34:40.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:40.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:40.22#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:34:40.22#ibcon#first serial, iclass 40, count 0 2006.281.07:34:40.22#ibcon#enter sib2, iclass 40, count 0 2006.281.07:34:40.22#ibcon#flushed, iclass 40, count 0 2006.281.07:34:40.22#ibcon#about to write, iclass 40, count 0 2006.281.07:34:40.22#ibcon#wrote, iclass 40, count 0 2006.281.07:34:40.22#ibcon#about to read 3, iclass 40, count 0 2006.281.07:34:40.24#ibcon#read 3, iclass 40, count 0 2006.281.07:34:40.24#ibcon#about to read 4, iclass 40, count 0 2006.281.07:34:40.24#ibcon#read 4, iclass 40, count 0 2006.281.07:34:40.24#ibcon#about to read 5, iclass 40, count 0 2006.281.07:34:40.24#ibcon#read 5, iclass 40, count 0 2006.281.07:34:40.24#ibcon#about to read 6, iclass 40, count 0 2006.281.07:34:40.24#ibcon#read 6, iclass 40, count 0 2006.281.07:34:40.24#ibcon#end of sib2, iclass 40, count 0 2006.281.07:34:40.24#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:34:40.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:34:40.24#ibcon#[25=USB\r\n] 2006.281.07:34:40.24#ibcon#*before write, iclass 40, count 0 2006.281.07:34:40.24#ibcon#enter sib2, iclass 40, count 0 2006.281.07:34:40.24#ibcon#flushed, iclass 40, count 0 2006.281.07:34:40.24#ibcon#about to write, iclass 40, count 0 2006.281.07:34:40.24#ibcon#wrote, iclass 40, count 0 2006.281.07:34:40.24#ibcon#about to read 3, iclass 40, count 0 2006.281.07:34:40.27#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:34:40.27#ibcon#read 3, iclass 40, count 0 2006.281.07:34:40.27#ibcon#about to read 4, iclass 40, count 0 2006.281.07:34:40.27#ibcon#read 4, iclass 40, count 0 2006.281.07:34:40.27#ibcon#about to read 5, iclass 40, count 0 2006.281.07:34:40.27#ibcon#read 5, iclass 40, count 0 2006.281.07:34:40.27#ibcon#about to read 6, iclass 40, count 0 2006.281.07:34:40.27#ibcon#read 6, iclass 40, count 0 2006.281.07:34:40.27#ibcon#end of sib2, iclass 40, count 0 2006.281.07:34:40.27#ibcon#*after write, iclass 40, count 0 2006.281.07:34:40.27#ibcon#*before return 0, iclass 40, count 0 2006.281.07:34:40.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:40.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:40.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:34:40.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:34:40.27$vc4f8/valo=5,652.99 2006.281.07:34:40.27#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:34:40.27#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:34:40.27#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:40.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:40.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:40.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:40.27#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:34:40.27#ibcon#first serial, iclass 10, count 0 2006.281.07:34:40.27#ibcon#enter sib2, iclass 10, count 0 2006.281.07:34:40.27#ibcon#flushed, iclass 10, count 0 2006.281.07:34:40.27#ibcon#about to write, iclass 10, count 0 2006.281.07:34:40.27#ibcon#wrote, iclass 10, count 0 2006.281.07:34:40.27#ibcon#about to read 3, iclass 10, count 0 2006.281.07:34:40.29#ibcon#read 3, iclass 10, count 0 2006.281.07:34:40.29#ibcon#about to read 4, iclass 10, count 0 2006.281.07:34:40.29#ibcon#read 4, iclass 10, count 0 2006.281.07:34:40.29#ibcon#about to read 5, iclass 10, count 0 2006.281.07:34:40.29#ibcon#read 5, iclass 10, count 0 2006.281.07:34:40.29#ibcon#about to read 6, iclass 10, count 0 2006.281.07:34:40.29#ibcon#read 6, iclass 10, count 0 2006.281.07:34:40.29#ibcon#end of sib2, iclass 10, count 0 2006.281.07:34:40.29#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:34:40.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:34:40.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:34:40.29#ibcon#*before write, iclass 10, count 0 2006.281.07:34:40.29#ibcon#enter sib2, iclass 10, count 0 2006.281.07:34:40.29#ibcon#flushed, iclass 10, count 0 2006.281.07:34:40.29#ibcon#about to write, iclass 10, count 0 2006.281.07:34:40.29#ibcon#wrote, iclass 10, count 0 2006.281.07:34:40.29#ibcon#about to read 3, iclass 10, count 0 2006.281.07:34:40.33#ibcon#read 3, iclass 10, count 0 2006.281.07:34:40.33#ibcon#about to read 4, iclass 10, count 0 2006.281.07:34:40.33#ibcon#read 4, iclass 10, count 0 2006.281.07:34:40.33#ibcon#about to read 5, iclass 10, count 0 2006.281.07:34:40.33#ibcon#read 5, iclass 10, count 0 2006.281.07:34:40.33#ibcon#about to read 6, iclass 10, count 0 2006.281.07:34:40.33#ibcon#read 6, iclass 10, count 0 2006.281.07:34:40.33#ibcon#end of sib2, iclass 10, count 0 2006.281.07:34:40.33#ibcon#*after write, iclass 10, count 0 2006.281.07:34:40.33#ibcon#*before return 0, iclass 10, count 0 2006.281.07:34:40.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:40.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:40.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:34:40.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:34:40.33$vc4f8/va=5,7 2006.281.07:34:40.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:34:40.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:34:40.33#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:40.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:40.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:40.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:40.39#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:34:40.39#ibcon#first serial, iclass 12, count 2 2006.281.07:34:40.39#ibcon#enter sib2, iclass 12, count 2 2006.281.07:34:40.39#ibcon#flushed, iclass 12, count 2 2006.281.07:34:40.39#ibcon#about to write, iclass 12, count 2 2006.281.07:34:40.39#ibcon#wrote, iclass 12, count 2 2006.281.07:34:40.39#ibcon#about to read 3, iclass 12, count 2 2006.281.07:34:40.41#ibcon#read 3, iclass 12, count 2 2006.281.07:34:40.41#ibcon#about to read 4, iclass 12, count 2 2006.281.07:34:40.41#ibcon#read 4, iclass 12, count 2 2006.281.07:34:40.41#ibcon#about to read 5, iclass 12, count 2 2006.281.07:34:40.41#ibcon#read 5, iclass 12, count 2 2006.281.07:34:40.41#ibcon#about to read 6, iclass 12, count 2 2006.281.07:34:40.41#ibcon#read 6, iclass 12, count 2 2006.281.07:34:40.41#ibcon#end of sib2, iclass 12, count 2 2006.281.07:34:40.41#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:34:40.41#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:34:40.41#ibcon#[25=AT05-07\r\n] 2006.281.07:34:40.41#ibcon#*before write, iclass 12, count 2 2006.281.07:34:40.41#ibcon#enter sib2, iclass 12, count 2 2006.281.07:34:40.41#ibcon#flushed, iclass 12, count 2 2006.281.07:34:40.41#ibcon#about to write, iclass 12, count 2 2006.281.07:34:40.41#ibcon#wrote, iclass 12, count 2 2006.281.07:34:40.41#ibcon#about to read 3, iclass 12, count 2 2006.281.07:34:40.44#ibcon#read 3, iclass 12, count 2 2006.281.07:34:40.44#ibcon#about to read 4, iclass 12, count 2 2006.281.07:34:40.44#ibcon#read 4, iclass 12, count 2 2006.281.07:34:40.44#ibcon#about to read 5, iclass 12, count 2 2006.281.07:34:40.44#ibcon#read 5, iclass 12, count 2 2006.281.07:34:40.44#ibcon#about to read 6, iclass 12, count 2 2006.281.07:34:40.44#ibcon#read 6, iclass 12, count 2 2006.281.07:34:40.44#ibcon#end of sib2, iclass 12, count 2 2006.281.07:34:40.44#ibcon#*after write, iclass 12, count 2 2006.281.07:34:40.44#ibcon#*before return 0, iclass 12, count 2 2006.281.07:34:40.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:40.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:40.44#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:34:40.44#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:40.44#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:40.56#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:40.56#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:40.56#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:34:40.56#ibcon#first serial, iclass 12, count 0 2006.281.07:34:40.56#ibcon#enter sib2, iclass 12, count 0 2006.281.07:34:40.56#ibcon#flushed, iclass 12, count 0 2006.281.07:34:40.56#ibcon#about to write, iclass 12, count 0 2006.281.07:34:40.56#ibcon#wrote, iclass 12, count 0 2006.281.07:34:40.56#ibcon#about to read 3, iclass 12, count 0 2006.281.07:34:40.58#ibcon#read 3, iclass 12, count 0 2006.281.07:34:40.58#ibcon#about to read 4, iclass 12, count 0 2006.281.07:34:40.58#ibcon#read 4, iclass 12, count 0 2006.281.07:34:40.58#ibcon#about to read 5, iclass 12, count 0 2006.281.07:34:40.58#ibcon#read 5, iclass 12, count 0 2006.281.07:34:40.58#ibcon#about to read 6, iclass 12, count 0 2006.281.07:34:40.58#ibcon#read 6, iclass 12, count 0 2006.281.07:34:40.58#ibcon#end of sib2, iclass 12, count 0 2006.281.07:34:40.58#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:34:40.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:34:40.58#ibcon#[25=USB\r\n] 2006.281.07:34:40.58#ibcon#*before write, iclass 12, count 0 2006.281.07:34:40.58#ibcon#enter sib2, iclass 12, count 0 2006.281.07:34:40.58#ibcon#flushed, iclass 12, count 0 2006.281.07:34:40.58#ibcon#about to write, iclass 12, count 0 2006.281.07:34:40.58#ibcon#wrote, iclass 12, count 0 2006.281.07:34:40.58#ibcon#about to read 3, iclass 12, count 0 2006.281.07:34:40.61#ibcon#read 3, iclass 12, count 0 2006.281.07:34:40.61#ibcon#about to read 4, iclass 12, count 0 2006.281.07:34:40.61#ibcon#read 4, iclass 12, count 0 2006.281.07:34:40.61#ibcon#about to read 5, iclass 12, count 0 2006.281.07:34:40.61#ibcon#read 5, iclass 12, count 0 2006.281.07:34:40.61#ibcon#about to read 6, iclass 12, count 0 2006.281.07:34:40.61#ibcon#read 6, iclass 12, count 0 2006.281.07:34:40.61#ibcon#end of sib2, iclass 12, count 0 2006.281.07:34:40.61#ibcon#*after write, iclass 12, count 0 2006.281.07:34:40.61#ibcon#*before return 0, iclass 12, count 0 2006.281.07:34:40.61#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:40.61#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:40.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:34:40.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:34:40.61$vc4f8/valo=6,772.99 2006.281.07:34:40.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:34:40.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:34:40.61#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:40.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:40.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:40.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:40.61#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:34:40.61#ibcon#first serial, iclass 14, count 0 2006.281.07:34:40.61#ibcon#enter sib2, iclass 14, count 0 2006.281.07:34:40.61#ibcon#flushed, iclass 14, count 0 2006.281.07:34:40.61#ibcon#about to write, iclass 14, count 0 2006.281.07:34:40.61#ibcon#wrote, iclass 14, count 0 2006.281.07:34:40.61#ibcon#about to read 3, iclass 14, count 0 2006.281.07:34:40.63#ibcon#read 3, iclass 14, count 0 2006.281.07:34:40.63#ibcon#about to read 4, iclass 14, count 0 2006.281.07:34:40.63#ibcon#read 4, iclass 14, count 0 2006.281.07:34:40.63#ibcon#about to read 5, iclass 14, count 0 2006.281.07:34:40.63#ibcon#read 5, iclass 14, count 0 2006.281.07:34:40.63#ibcon#about to read 6, iclass 14, count 0 2006.281.07:34:40.63#ibcon#read 6, iclass 14, count 0 2006.281.07:34:40.63#ibcon#end of sib2, iclass 14, count 0 2006.281.07:34:40.63#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:34:40.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:34:40.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:34:40.63#ibcon#*before write, iclass 14, count 0 2006.281.07:34:40.63#ibcon#enter sib2, iclass 14, count 0 2006.281.07:34:40.63#ibcon#flushed, iclass 14, count 0 2006.281.07:34:40.63#ibcon#about to write, iclass 14, count 0 2006.281.07:34:40.63#ibcon#wrote, iclass 14, count 0 2006.281.07:34:40.63#ibcon#about to read 3, iclass 14, count 0 2006.281.07:34:40.67#ibcon#read 3, iclass 14, count 0 2006.281.07:34:40.67#ibcon#about to read 4, iclass 14, count 0 2006.281.07:34:40.67#ibcon#read 4, iclass 14, count 0 2006.281.07:34:40.67#ibcon#about to read 5, iclass 14, count 0 2006.281.07:34:40.67#ibcon#read 5, iclass 14, count 0 2006.281.07:34:40.67#ibcon#about to read 6, iclass 14, count 0 2006.281.07:34:40.67#ibcon#read 6, iclass 14, count 0 2006.281.07:34:40.67#ibcon#end of sib2, iclass 14, count 0 2006.281.07:34:40.67#ibcon#*after write, iclass 14, count 0 2006.281.07:34:40.67#ibcon#*before return 0, iclass 14, count 0 2006.281.07:34:40.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:40.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:40.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:34:40.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:34:40.67$vc4f8/va=6,6 2006.281.07:34:40.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.07:34:40.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.07:34:40.67#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:40.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:40.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:40.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:40.73#ibcon#enter wrdev, iclass 16, count 2 2006.281.07:34:40.73#ibcon#first serial, iclass 16, count 2 2006.281.07:34:40.73#ibcon#enter sib2, iclass 16, count 2 2006.281.07:34:40.73#ibcon#flushed, iclass 16, count 2 2006.281.07:34:40.73#ibcon#about to write, iclass 16, count 2 2006.281.07:34:40.73#ibcon#wrote, iclass 16, count 2 2006.281.07:34:40.73#ibcon#about to read 3, iclass 16, count 2 2006.281.07:34:40.75#ibcon#read 3, iclass 16, count 2 2006.281.07:34:40.75#ibcon#about to read 4, iclass 16, count 2 2006.281.07:34:40.75#ibcon#read 4, iclass 16, count 2 2006.281.07:34:40.75#ibcon#about to read 5, iclass 16, count 2 2006.281.07:34:40.75#ibcon#read 5, iclass 16, count 2 2006.281.07:34:40.75#ibcon#about to read 6, iclass 16, count 2 2006.281.07:34:40.75#ibcon#read 6, iclass 16, count 2 2006.281.07:34:40.75#ibcon#end of sib2, iclass 16, count 2 2006.281.07:34:40.75#ibcon#*mode == 0, iclass 16, count 2 2006.281.07:34:40.75#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.07:34:40.75#ibcon#[25=AT06-06\r\n] 2006.281.07:34:40.75#ibcon#*before write, iclass 16, count 2 2006.281.07:34:40.75#ibcon#enter sib2, iclass 16, count 2 2006.281.07:34:40.75#ibcon#flushed, iclass 16, count 2 2006.281.07:34:40.75#ibcon#about to write, iclass 16, count 2 2006.281.07:34:40.75#ibcon#wrote, iclass 16, count 2 2006.281.07:34:40.75#ibcon#about to read 3, iclass 16, count 2 2006.281.07:34:40.78#ibcon#read 3, iclass 16, count 2 2006.281.07:34:40.78#ibcon#about to read 4, iclass 16, count 2 2006.281.07:34:40.78#ibcon#read 4, iclass 16, count 2 2006.281.07:34:40.78#ibcon#about to read 5, iclass 16, count 2 2006.281.07:34:40.78#ibcon#read 5, iclass 16, count 2 2006.281.07:34:40.78#ibcon#about to read 6, iclass 16, count 2 2006.281.07:34:40.78#ibcon#read 6, iclass 16, count 2 2006.281.07:34:40.78#ibcon#end of sib2, iclass 16, count 2 2006.281.07:34:40.78#ibcon#*after write, iclass 16, count 2 2006.281.07:34:40.78#ibcon#*before return 0, iclass 16, count 2 2006.281.07:34:40.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:40.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:40.78#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.07:34:40.78#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:40.78#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:34:40.90#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:34:40.90#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:34:40.90#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:34:40.90#ibcon#first serial, iclass 16, count 0 2006.281.07:34:40.90#ibcon#enter sib2, iclass 16, count 0 2006.281.07:34:40.90#ibcon#flushed, iclass 16, count 0 2006.281.07:34:40.90#ibcon#about to write, iclass 16, count 0 2006.281.07:34:40.90#ibcon#wrote, iclass 16, count 0 2006.281.07:34:40.90#ibcon#about to read 3, iclass 16, count 0 2006.281.07:34:40.92#ibcon#read 3, iclass 16, count 0 2006.281.07:34:40.92#ibcon#about to read 4, iclass 16, count 0 2006.281.07:34:40.92#ibcon#read 4, iclass 16, count 0 2006.281.07:34:40.92#ibcon#about to read 5, iclass 16, count 0 2006.281.07:34:40.92#ibcon#read 5, iclass 16, count 0 2006.281.07:34:40.92#ibcon#about to read 6, iclass 16, count 0 2006.281.07:34:40.92#ibcon#read 6, iclass 16, count 0 2006.281.07:34:40.92#ibcon#end of sib2, iclass 16, count 0 2006.281.07:34:40.92#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:34:40.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:34:40.92#ibcon#[25=USB\r\n] 2006.281.07:34:40.92#ibcon#*before write, iclass 16, count 0 2006.281.07:34:40.92#ibcon#enter sib2, iclass 16, count 0 2006.281.07:34:40.92#ibcon#flushed, iclass 16, count 0 2006.281.07:34:40.92#ibcon#about to write, iclass 16, count 0 2006.281.07:34:40.92#ibcon#wrote, iclass 16, count 0 2006.281.07:34:40.92#ibcon#about to read 3, iclass 16, count 0 2006.281.07:34:40.95#ibcon#read 3, iclass 16, count 0 2006.281.07:34:40.95#ibcon#about to read 4, iclass 16, count 0 2006.281.07:34:40.95#ibcon#read 4, iclass 16, count 0 2006.281.07:34:40.95#ibcon#about to read 5, iclass 16, count 0 2006.281.07:34:40.95#ibcon#read 5, iclass 16, count 0 2006.281.07:34:40.95#ibcon#about to read 6, iclass 16, count 0 2006.281.07:34:40.95#ibcon#read 6, iclass 16, count 0 2006.281.07:34:40.95#ibcon#end of sib2, iclass 16, count 0 2006.281.07:34:40.95#ibcon#*after write, iclass 16, count 0 2006.281.07:34:40.95#ibcon#*before return 0, iclass 16, count 0 2006.281.07:34:40.95#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:34:40.95#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:34:40.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:34:40.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:34:40.95$vc4f8/valo=7,832.99 2006.281.07:34:40.95#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.07:34:40.95#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.07:34:40.95#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:40.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:34:40.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:34:40.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:34:40.95#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:34:40.95#ibcon#first serial, iclass 18, count 0 2006.281.07:34:40.95#ibcon#enter sib2, iclass 18, count 0 2006.281.07:34:40.95#ibcon#flushed, iclass 18, count 0 2006.281.07:34:40.95#ibcon#about to write, iclass 18, count 0 2006.281.07:34:40.95#ibcon#wrote, iclass 18, count 0 2006.281.07:34:40.95#ibcon#about to read 3, iclass 18, count 0 2006.281.07:34:40.97#ibcon#read 3, iclass 18, count 0 2006.281.07:34:40.97#ibcon#about to read 4, iclass 18, count 0 2006.281.07:34:40.97#ibcon#read 4, iclass 18, count 0 2006.281.07:34:40.97#ibcon#about to read 5, iclass 18, count 0 2006.281.07:34:40.97#ibcon#read 5, iclass 18, count 0 2006.281.07:34:40.97#ibcon#about to read 6, iclass 18, count 0 2006.281.07:34:40.97#ibcon#read 6, iclass 18, count 0 2006.281.07:34:40.97#ibcon#end of sib2, iclass 18, count 0 2006.281.07:34:40.97#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:34:40.97#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:34:40.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:34:40.99#ibcon#*before write, iclass 18, count 0 2006.281.07:34:40.99#ibcon#enter sib2, iclass 18, count 0 2006.281.07:34:40.99#ibcon#flushed, iclass 18, count 0 2006.281.07:34:40.99#ibcon#about to write, iclass 18, count 0 2006.281.07:34:40.99#ibcon#wrote, iclass 18, count 0 2006.281.07:34:40.99#ibcon#about to read 3, iclass 18, count 0 2006.281.07:34:41.03#ibcon#read 3, iclass 18, count 0 2006.281.07:34:41.03#ibcon#about to read 4, iclass 18, count 0 2006.281.07:34:41.03#ibcon#read 4, iclass 18, count 0 2006.281.07:34:41.03#ibcon#about to read 5, iclass 18, count 0 2006.281.07:34:41.03#ibcon#read 5, iclass 18, count 0 2006.281.07:34:41.03#ibcon#about to read 6, iclass 18, count 0 2006.281.07:34:41.03#ibcon#read 6, iclass 18, count 0 2006.281.07:34:41.03#ibcon#end of sib2, iclass 18, count 0 2006.281.07:34:41.03#ibcon#*after write, iclass 18, count 0 2006.281.07:34:41.03#ibcon#*before return 0, iclass 18, count 0 2006.281.07:34:41.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:34:41.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:34:41.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:34:41.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:34:41.03$vc4f8/va=7,6 2006.281.07:34:41.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.07:34:41.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.07:34:41.03#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:41.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:34:41.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:34:41.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:34:41.07#ibcon#enter wrdev, iclass 20, count 2 2006.281.07:34:41.07#ibcon#first serial, iclass 20, count 2 2006.281.07:34:41.07#ibcon#enter sib2, iclass 20, count 2 2006.281.07:34:41.07#ibcon#flushed, iclass 20, count 2 2006.281.07:34:41.07#ibcon#about to write, iclass 20, count 2 2006.281.07:34:41.07#ibcon#wrote, iclass 20, count 2 2006.281.07:34:41.07#ibcon#about to read 3, iclass 20, count 2 2006.281.07:34:41.09#ibcon#read 3, iclass 20, count 2 2006.281.07:34:41.09#ibcon#about to read 4, iclass 20, count 2 2006.281.07:34:41.09#ibcon#read 4, iclass 20, count 2 2006.281.07:34:41.09#ibcon#about to read 5, iclass 20, count 2 2006.281.07:34:41.09#ibcon#read 5, iclass 20, count 2 2006.281.07:34:41.09#ibcon#about to read 6, iclass 20, count 2 2006.281.07:34:41.09#ibcon#read 6, iclass 20, count 2 2006.281.07:34:41.09#ibcon#end of sib2, iclass 20, count 2 2006.281.07:34:41.09#ibcon#*mode == 0, iclass 20, count 2 2006.281.07:34:41.09#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.07:34:41.09#ibcon#[25=AT07-06\r\n] 2006.281.07:34:41.09#ibcon#*before write, iclass 20, count 2 2006.281.07:34:41.09#ibcon#enter sib2, iclass 20, count 2 2006.281.07:34:41.09#ibcon#flushed, iclass 20, count 2 2006.281.07:34:41.09#ibcon#about to write, iclass 20, count 2 2006.281.07:34:41.09#ibcon#wrote, iclass 20, count 2 2006.281.07:34:41.09#ibcon#about to read 3, iclass 20, count 2 2006.281.07:34:41.12#ibcon#read 3, iclass 20, count 2 2006.281.07:34:41.12#ibcon#about to read 4, iclass 20, count 2 2006.281.07:34:41.12#ibcon#read 4, iclass 20, count 2 2006.281.07:34:41.12#ibcon#about to read 5, iclass 20, count 2 2006.281.07:34:41.12#ibcon#read 5, iclass 20, count 2 2006.281.07:34:41.12#ibcon#about to read 6, iclass 20, count 2 2006.281.07:34:41.12#ibcon#read 6, iclass 20, count 2 2006.281.07:34:41.12#ibcon#end of sib2, iclass 20, count 2 2006.281.07:34:41.12#ibcon#*after write, iclass 20, count 2 2006.281.07:34:41.12#ibcon#*before return 0, iclass 20, count 2 2006.281.07:34:41.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:34:41.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:34:41.12#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.07:34:41.12#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:41.12#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:34:41.24#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:34:41.24#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:34:41.24#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:34:41.24#ibcon#first serial, iclass 20, count 0 2006.281.07:34:41.24#ibcon#enter sib2, iclass 20, count 0 2006.281.07:34:41.24#ibcon#flushed, iclass 20, count 0 2006.281.07:34:41.24#ibcon#about to write, iclass 20, count 0 2006.281.07:34:41.24#ibcon#wrote, iclass 20, count 0 2006.281.07:34:41.24#ibcon#about to read 3, iclass 20, count 0 2006.281.07:34:41.26#ibcon#read 3, iclass 20, count 0 2006.281.07:34:41.26#ibcon#about to read 4, iclass 20, count 0 2006.281.07:34:41.26#ibcon#read 4, iclass 20, count 0 2006.281.07:34:41.26#ibcon#about to read 5, iclass 20, count 0 2006.281.07:34:41.26#ibcon#read 5, iclass 20, count 0 2006.281.07:34:41.26#ibcon#about to read 6, iclass 20, count 0 2006.281.07:34:41.26#ibcon#read 6, iclass 20, count 0 2006.281.07:34:41.26#ibcon#end of sib2, iclass 20, count 0 2006.281.07:34:41.26#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:34:41.26#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:34:41.26#ibcon#[25=USB\r\n] 2006.281.07:34:41.26#ibcon#*before write, iclass 20, count 0 2006.281.07:34:41.26#ibcon#enter sib2, iclass 20, count 0 2006.281.07:34:41.26#ibcon#flushed, iclass 20, count 0 2006.281.07:34:41.26#ibcon#about to write, iclass 20, count 0 2006.281.07:34:41.26#ibcon#wrote, iclass 20, count 0 2006.281.07:34:41.26#ibcon#about to read 3, iclass 20, count 0 2006.281.07:34:41.29#ibcon#read 3, iclass 20, count 0 2006.281.07:34:41.29#ibcon#about to read 4, iclass 20, count 0 2006.281.07:34:41.29#ibcon#read 4, iclass 20, count 0 2006.281.07:34:41.29#ibcon#about to read 5, iclass 20, count 0 2006.281.07:34:41.29#ibcon#read 5, iclass 20, count 0 2006.281.07:34:41.29#ibcon#about to read 6, iclass 20, count 0 2006.281.07:34:41.29#ibcon#read 6, iclass 20, count 0 2006.281.07:34:41.29#ibcon#end of sib2, iclass 20, count 0 2006.281.07:34:41.29#ibcon#*after write, iclass 20, count 0 2006.281.07:34:41.29#ibcon#*before return 0, iclass 20, count 0 2006.281.07:34:41.29#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:34:41.29#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:34:41.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:34:41.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:34:41.29$vc4f8/valo=8,852.99 2006.281.07:34:41.29#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.07:34:41.29#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.07:34:41.29#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:41.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:34:41.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:34:41.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:34:41.29#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:34:41.29#ibcon#first serial, iclass 22, count 0 2006.281.07:34:41.29#ibcon#enter sib2, iclass 22, count 0 2006.281.07:34:41.29#ibcon#flushed, iclass 22, count 0 2006.281.07:34:41.29#ibcon#about to write, iclass 22, count 0 2006.281.07:34:41.29#ibcon#wrote, iclass 22, count 0 2006.281.07:34:41.29#ibcon#about to read 3, iclass 22, count 0 2006.281.07:34:41.31#ibcon#read 3, iclass 22, count 0 2006.281.07:34:41.31#ibcon#about to read 4, iclass 22, count 0 2006.281.07:34:41.31#ibcon#read 4, iclass 22, count 0 2006.281.07:34:41.31#ibcon#about to read 5, iclass 22, count 0 2006.281.07:34:41.31#ibcon#read 5, iclass 22, count 0 2006.281.07:34:41.31#ibcon#about to read 6, iclass 22, count 0 2006.281.07:34:41.31#ibcon#read 6, iclass 22, count 0 2006.281.07:34:41.31#ibcon#end of sib2, iclass 22, count 0 2006.281.07:34:41.31#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:34:41.31#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:34:41.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:34:41.31#ibcon#*before write, iclass 22, count 0 2006.281.07:34:41.31#ibcon#enter sib2, iclass 22, count 0 2006.281.07:34:41.31#ibcon#flushed, iclass 22, count 0 2006.281.07:34:41.31#ibcon#about to write, iclass 22, count 0 2006.281.07:34:41.31#ibcon#wrote, iclass 22, count 0 2006.281.07:34:41.31#ibcon#about to read 3, iclass 22, count 0 2006.281.07:34:41.35#ibcon#read 3, iclass 22, count 0 2006.281.07:34:41.35#ibcon#about to read 4, iclass 22, count 0 2006.281.07:34:41.35#ibcon#read 4, iclass 22, count 0 2006.281.07:34:41.35#ibcon#about to read 5, iclass 22, count 0 2006.281.07:34:41.35#ibcon#read 5, iclass 22, count 0 2006.281.07:34:41.35#ibcon#about to read 6, iclass 22, count 0 2006.281.07:34:41.35#ibcon#read 6, iclass 22, count 0 2006.281.07:34:41.35#ibcon#end of sib2, iclass 22, count 0 2006.281.07:34:41.35#ibcon#*after write, iclass 22, count 0 2006.281.07:34:41.35#ibcon#*before return 0, iclass 22, count 0 2006.281.07:34:41.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:34:41.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:34:41.35#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:34:41.35#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:34:41.35$vc4f8/va=8,6 2006.281.07:34:41.35#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.07:34:41.35#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.07:34:41.35#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:41.35#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:34:41.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:34:41.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:34:41.41#ibcon#enter wrdev, iclass 24, count 2 2006.281.07:34:41.41#ibcon#first serial, iclass 24, count 2 2006.281.07:34:41.41#ibcon#enter sib2, iclass 24, count 2 2006.281.07:34:41.41#ibcon#flushed, iclass 24, count 2 2006.281.07:34:41.41#ibcon#about to write, iclass 24, count 2 2006.281.07:34:41.41#ibcon#wrote, iclass 24, count 2 2006.281.07:34:41.41#ibcon#about to read 3, iclass 24, count 2 2006.281.07:34:41.43#ibcon#read 3, iclass 24, count 2 2006.281.07:34:41.43#ibcon#about to read 4, iclass 24, count 2 2006.281.07:34:41.43#ibcon#read 4, iclass 24, count 2 2006.281.07:34:41.43#ibcon#about to read 5, iclass 24, count 2 2006.281.07:34:41.43#ibcon#read 5, iclass 24, count 2 2006.281.07:34:41.43#ibcon#about to read 6, iclass 24, count 2 2006.281.07:34:41.43#ibcon#read 6, iclass 24, count 2 2006.281.07:34:41.43#ibcon#end of sib2, iclass 24, count 2 2006.281.07:34:41.43#ibcon#*mode == 0, iclass 24, count 2 2006.281.07:34:41.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.07:34:41.43#ibcon#[25=AT08-06\r\n] 2006.281.07:34:41.43#ibcon#*before write, iclass 24, count 2 2006.281.07:34:41.43#ibcon#enter sib2, iclass 24, count 2 2006.281.07:34:41.43#ibcon#flushed, iclass 24, count 2 2006.281.07:34:41.43#ibcon#about to write, iclass 24, count 2 2006.281.07:34:41.43#ibcon#wrote, iclass 24, count 2 2006.281.07:34:41.43#ibcon#about to read 3, iclass 24, count 2 2006.281.07:34:41.46#ibcon#read 3, iclass 24, count 2 2006.281.07:34:41.46#ibcon#about to read 4, iclass 24, count 2 2006.281.07:34:41.46#ibcon#read 4, iclass 24, count 2 2006.281.07:34:41.46#ibcon#about to read 5, iclass 24, count 2 2006.281.07:34:41.46#ibcon#read 5, iclass 24, count 2 2006.281.07:34:41.46#ibcon#about to read 6, iclass 24, count 2 2006.281.07:34:41.46#ibcon#read 6, iclass 24, count 2 2006.281.07:34:41.46#ibcon#end of sib2, iclass 24, count 2 2006.281.07:34:41.46#ibcon#*after write, iclass 24, count 2 2006.281.07:34:41.46#ibcon#*before return 0, iclass 24, count 2 2006.281.07:34:41.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:34:41.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:34:41.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.07:34:41.46#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:41.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:34:41.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:34:41.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:34:41.58#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:34:41.58#ibcon#first serial, iclass 24, count 0 2006.281.07:34:41.58#ibcon#enter sib2, iclass 24, count 0 2006.281.07:34:41.58#ibcon#flushed, iclass 24, count 0 2006.281.07:34:41.58#ibcon#about to write, iclass 24, count 0 2006.281.07:34:41.58#ibcon#wrote, iclass 24, count 0 2006.281.07:34:41.58#ibcon#about to read 3, iclass 24, count 0 2006.281.07:34:41.60#ibcon#read 3, iclass 24, count 0 2006.281.07:34:41.60#ibcon#about to read 4, iclass 24, count 0 2006.281.07:34:41.60#ibcon#read 4, iclass 24, count 0 2006.281.07:34:41.60#ibcon#about to read 5, iclass 24, count 0 2006.281.07:34:41.60#ibcon#read 5, iclass 24, count 0 2006.281.07:34:41.60#ibcon#about to read 6, iclass 24, count 0 2006.281.07:34:41.60#ibcon#read 6, iclass 24, count 0 2006.281.07:34:41.60#ibcon#end of sib2, iclass 24, count 0 2006.281.07:34:41.60#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:34:41.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:34:41.60#ibcon#[25=USB\r\n] 2006.281.07:34:41.60#ibcon#*before write, iclass 24, count 0 2006.281.07:34:41.60#ibcon#enter sib2, iclass 24, count 0 2006.281.07:34:41.60#ibcon#flushed, iclass 24, count 0 2006.281.07:34:41.60#ibcon#about to write, iclass 24, count 0 2006.281.07:34:41.60#ibcon#wrote, iclass 24, count 0 2006.281.07:34:41.60#ibcon#about to read 3, iclass 24, count 0 2006.281.07:34:41.63#ibcon#read 3, iclass 24, count 0 2006.281.07:34:41.63#ibcon#about to read 4, iclass 24, count 0 2006.281.07:34:41.63#ibcon#read 4, iclass 24, count 0 2006.281.07:34:41.63#ibcon#about to read 5, iclass 24, count 0 2006.281.07:34:41.63#ibcon#read 5, iclass 24, count 0 2006.281.07:34:41.63#ibcon#about to read 6, iclass 24, count 0 2006.281.07:34:41.63#ibcon#read 6, iclass 24, count 0 2006.281.07:34:41.63#ibcon#end of sib2, iclass 24, count 0 2006.281.07:34:41.63#ibcon#*after write, iclass 24, count 0 2006.281.07:34:41.63#ibcon#*before return 0, iclass 24, count 0 2006.281.07:34:41.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:34:41.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:34:41.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:34:41.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:34:41.63$vc4f8/vblo=1,632.99 2006.281.07:34:41.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:34:41.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:34:41.63#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:41.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:41.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:41.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:41.63#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:34:41.63#ibcon#first serial, iclass 26, count 0 2006.281.07:34:41.63#ibcon#enter sib2, iclass 26, count 0 2006.281.07:34:41.63#ibcon#flushed, iclass 26, count 0 2006.281.07:34:41.63#ibcon#about to write, iclass 26, count 0 2006.281.07:34:41.63#ibcon#wrote, iclass 26, count 0 2006.281.07:34:41.63#ibcon#about to read 3, iclass 26, count 0 2006.281.07:34:41.65#ibcon#read 3, iclass 26, count 0 2006.281.07:34:41.65#ibcon#about to read 4, iclass 26, count 0 2006.281.07:34:41.65#ibcon#read 4, iclass 26, count 0 2006.281.07:34:41.65#ibcon#about to read 5, iclass 26, count 0 2006.281.07:34:41.65#ibcon#read 5, iclass 26, count 0 2006.281.07:34:41.65#ibcon#about to read 6, iclass 26, count 0 2006.281.07:34:41.65#ibcon#read 6, iclass 26, count 0 2006.281.07:34:41.65#ibcon#end of sib2, iclass 26, count 0 2006.281.07:34:41.65#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:34:41.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:34:41.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:34:41.65#ibcon#*before write, iclass 26, count 0 2006.281.07:34:41.65#ibcon#enter sib2, iclass 26, count 0 2006.281.07:34:41.65#ibcon#flushed, iclass 26, count 0 2006.281.07:34:41.65#ibcon#about to write, iclass 26, count 0 2006.281.07:34:41.65#ibcon#wrote, iclass 26, count 0 2006.281.07:34:41.65#ibcon#about to read 3, iclass 26, count 0 2006.281.07:34:41.69#ibcon#read 3, iclass 26, count 0 2006.281.07:34:41.69#ibcon#about to read 4, iclass 26, count 0 2006.281.07:34:41.69#ibcon#read 4, iclass 26, count 0 2006.281.07:34:41.69#ibcon#about to read 5, iclass 26, count 0 2006.281.07:34:41.69#ibcon#read 5, iclass 26, count 0 2006.281.07:34:41.69#ibcon#about to read 6, iclass 26, count 0 2006.281.07:34:41.69#ibcon#read 6, iclass 26, count 0 2006.281.07:34:41.69#ibcon#end of sib2, iclass 26, count 0 2006.281.07:34:41.69#ibcon#*after write, iclass 26, count 0 2006.281.07:34:41.69#ibcon#*before return 0, iclass 26, count 0 2006.281.07:34:41.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:41.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:34:41.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:34:41.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:34:41.69$vc4f8/vb=1,4 2006.281.07:34:41.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:34:41.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:34:41.70#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:41.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:41.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:41.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:41.70#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:34:41.70#ibcon#first serial, iclass 28, count 2 2006.281.07:34:41.70#ibcon#enter sib2, iclass 28, count 2 2006.281.07:34:41.70#ibcon#flushed, iclass 28, count 2 2006.281.07:34:41.70#ibcon#about to write, iclass 28, count 2 2006.281.07:34:41.70#ibcon#wrote, iclass 28, count 2 2006.281.07:34:41.70#ibcon#about to read 3, iclass 28, count 2 2006.281.07:34:41.72#ibcon#read 3, iclass 28, count 2 2006.281.07:34:41.72#ibcon#about to read 4, iclass 28, count 2 2006.281.07:34:41.72#ibcon#read 4, iclass 28, count 2 2006.281.07:34:41.72#ibcon#about to read 5, iclass 28, count 2 2006.281.07:34:41.72#ibcon#read 5, iclass 28, count 2 2006.281.07:34:41.72#ibcon#about to read 6, iclass 28, count 2 2006.281.07:34:41.72#ibcon#read 6, iclass 28, count 2 2006.281.07:34:41.72#ibcon#end of sib2, iclass 28, count 2 2006.281.07:34:41.72#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:34:41.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:34:41.72#ibcon#[27=AT01-04\r\n] 2006.281.07:34:41.72#ibcon#*before write, iclass 28, count 2 2006.281.07:34:41.72#ibcon#enter sib2, iclass 28, count 2 2006.281.07:34:41.72#ibcon#flushed, iclass 28, count 2 2006.281.07:34:41.72#ibcon#about to write, iclass 28, count 2 2006.281.07:34:41.72#ibcon#wrote, iclass 28, count 2 2006.281.07:34:41.72#ibcon#about to read 3, iclass 28, count 2 2006.281.07:34:41.75#ibcon#read 3, iclass 28, count 2 2006.281.07:34:41.75#ibcon#about to read 4, iclass 28, count 2 2006.281.07:34:41.75#ibcon#read 4, iclass 28, count 2 2006.281.07:34:41.75#ibcon#about to read 5, iclass 28, count 2 2006.281.07:34:41.75#ibcon#read 5, iclass 28, count 2 2006.281.07:34:41.75#ibcon#about to read 6, iclass 28, count 2 2006.281.07:34:41.75#ibcon#read 6, iclass 28, count 2 2006.281.07:34:41.75#ibcon#end of sib2, iclass 28, count 2 2006.281.07:34:41.75#ibcon#*after write, iclass 28, count 2 2006.281.07:34:41.75#ibcon#*before return 0, iclass 28, count 2 2006.281.07:34:41.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:41.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:34:41.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:34:41.75#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:41.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:41.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:41.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:41.87#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:34:41.87#ibcon#first serial, iclass 28, count 0 2006.281.07:34:41.87#ibcon#enter sib2, iclass 28, count 0 2006.281.07:34:41.87#ibcon#flushed, iclass 28, count 0 2006.281.07:34:41.87#ibcon#about to write, iclass 28, count 0 2006.281.07:34:41.87#ibcon#wrote, iclass 28, count 0 2006.281.07:34:41.87#ibcon#about to read 3, iclass 28, count 0 2006.281.07:34:41.89#ibcon#read 3, iclass 28, count 0 2006.281.07:34:41.89#ibcon#about to read 4, iclass 28, count 0 2006.281.07:34:41.89#ibcon#read 4, iclass 28, count 0 2006.281.07:34:41.89#ibcon#about to read 5, iclass 28, count 0 2006.281.07:34:41.89#ibcon#read 5, iclass 28, count 0 2006.281.07:34:41.89#ibcon#about to read 6, iclass 28, count 0 2006.281.07:34:41.89#ibcon#read 6, iclass 28, count 0 2006.281.07:34:41.89#ibcon#end of sib2, iclass 28, count 0 2006.281.07:34:41.89#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:34:41.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:34:41.89#ibcon#[27=USB\r\n] 2006.281.07:34:41.89#ibcon#*before write, iclass 28, count 0 2006.281.07:34:41.89#ibcon#enter sib2, iclass 28, count 0 2006.281.07:34:41.89#ibcon#flushed, iclass 28, count 0 2006.281.07:34:41.89#ibcon#about to write, iclass 28, count 0 2006.281.07:34:41.89#ibcon#wrote, iclass 28, count 0 2006.281.07:34:41.89#ibcon#about to read 3, iclass 28, count 0 2006.281.07:34:41.92#ibcon#read 3, iclass 28, count 0 2006.281.07:34:41.92#ibcon#about to read 4, iclass 28, count 0 2006.281.07:34:41.92#ibcon#read 4, iclass 28, count 0 2006.281.07:34:41.92#ibcon#about to read 5, iclass 28, count 0 2006.281.07:34:41.92#ibcon#read 5, iclass 28, count 0 2006.281.07:34:41.92#ibcon#about to read 6, iclass 28, count 0 2006.281.07:34:41.92#ibcon#read 6, iclass 28, count 0 2006.281.07:34:41.92#ibcon#end of sib2, iclass 28, count 0 2006.281.07:34:41.92#ibcon#*after write, iclass 28, count 0 2006.281.07:34:41.92#ibcon#*before return 0, iclass 28, count 0 2006.281.07:34:41.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:41.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:34:41.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:34:41.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:34:41.92$vc4f8/vblo=2,640.99 2006.281.07:34:41.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:34:41.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:34:41.92#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:41.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:41.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:41.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:41.92#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:34:41.92#ibcon#first serial, iclass 30, count 0 2006.281.07:34:41.92#ibcon#enter sib2, iclass 30, count 0 2006.281.07:34:41.92#ibcon#flushed, iclass 30, count 0 2006.281.07:34:41.92#ibcon#about to write, iclass 30, count 0 2006.281.07:34:41.92#ibcon#wrote, iclass 30, count 0 2006.281.07:34:41.92#ibcon#about to read 3, iclass 30, count 0 2006.281.07:34:41.94#ibcon#read 3, iclass 30, count 0 2006.281.07:34:41.94#ibcon#about to read 4, iclass 30, count 0 2006.281.07:34:41.94#ibcon#read 4, iclass 30, count 0 2006.281.07:34:41.94#ibcon#about to read 5, iclass 30, count 0 2006.281.07:34:41.94#ibcon#read 5, iclass 30, count 0 2006.281.07:34:41.94#ibcon#about to read 6, iclass 30, count 0 2006.281.07:34:41.94#ibcon#read 6, iclass 30, count 0 2006.281.07:34:41.94#ibcon#end of sib2, iclass 30, count 0 2006.281.07:34:41.94#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:34:41.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:34:41.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:34:41.94#ibcon#*before write, iclass 30, count 0 2006.281.07:34:41.94#ibcon#enter sib2, iclass 30, count 0 2006.281.07:34:41.94#ibcon#flushed, iclass 30, count 0 2006.281.07:34:41.94#ibcon#about to write, iclass 30, count 0 2006.281.07:34:41.94#ibcon#wrote, iclass 30, count 0 2006.281.07:34:41.94#ibcon#about to read 3, iclass 30, count 0 2006.281.07:34:41.98#ibcon#read 3, iclass 30, count 0 2006.281.07:34:41.98#ibcon#about to read 4, iclass 30, count 0 2006.281.07:34:41.98#ibcon#read 4, iclass 30, count 0 2006.281.07:34:41.98#ibcon#about to read 5, iclass 30, count 0 2006.281.07:34:41.98#ibcon#read 5, iclass 30, count 0 2006.281.07:34:41.98#ibcon#about to read 6, iclass 30, count 0 2006.281.07:34:41.98#ibcon#read 6, iclass 30, count 0 2006.281.07:34:41.98#ibcon#end of sib2, iclass 30, count 0 2006.281.07:34:41.98#ibcon#*after write, iclass 30, count 0 2006.281.07:34:41.98#ibcon#*before return 0, iclass 30, count 0 2006.281.07:34:41.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:41.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:34:41.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:34:41.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:34:41.98$vc4f8/vb=2,5 2006.281.07:34:41.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:34:41.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:34:41.98#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:41.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:42.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:42.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:42.04#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:34:42.04#ibcon#first serial, iclass 32, count 2 2006.281.07:34:42.04#ibcon#enter sib2, iclass 32, count 2 2006.281.07:34:42.04#ibcon#flushed, iclass 32, count 2 2006.281.07:34:42.04#ibcon#about to write, iclass 32, count 2 2006.281.07:34:42.04#ibcon#wrote, iclass 32, count 2 2006.281.07:34:42.04#ibcon#about to read 3, iclass 32, count 2 2006.281.07:34:42.06#ibcon#read 3, iclass 32, count 2 2006.281.07:34:42.06#ibcon#about to read 4, iclass 32, count 2 2006.281.07:34:42.06#ibcon#read 4, iclass 32, count 2 2006.281.07:34:42.06#ibcon#about to read 5, iclass 32, count 2 2006.281.07:34:42.06#ibcon#read 5, iclass 32, count 2 2006.281.07:34:42.06#ibcon#about to read 6, iclass 32, count 2 2006.281.07:34:42.06#ibcon#read 6, iclass 32, count 2 2006.281.07:34:42.06#ibcon#end of sib2, iclass 32, count 2 2006.281.07:34:42.06#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:34:42.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:34:42.06#ibcon#[27=AT02-05\r\n] 2006.281.07:34:42.06#ibcon#*before write, iclass 32, count 2 2006.281.07:34:42.06#ibcon#enter sib2, iclass 32, count 2 2006.281.07:34:42.06#ibcon#flushed, iclass 32, count 2 2006.281.07:34:42.06#ibcon#about to write, iclass 32, count 2 2006.281.07:34:42.06#ibcon#wrote, iclass 32, count 2 2006.281.07:34:42.06#ibcon#about to read 3, iclass 32, count 2 2006.281.07:34:42.10#ibcon#read 3, iclass 32, count 2 2006.281.07:34:42.10#ibcon#about to read 4, iclass 32, count 2 2006.281.07:34:42.10#ibcon#read 4, iclass 32, count 2 2006.281.07:34:42.10#ibcon#about to read 5, iclass 32, count 2 2006.281.07:34:42.10#ibcon#read 5, iclass 32, count 2 2006.281.07:34:42.10#ibcon#about to read 6, iclass 32, count 2 2006.281.07:34:42.10#ibcon#read 6, iclass 32, count 2 2006.281.07:34:42.10#ibcon#end of sib2, iclass 32, count 2 2006.281.07:34:42.10#ibcon#*after write, iclass 32, count 2 2006.281.07:34:42.10#ibcon#*before return 0, iclass 32, count 2 2006.281.07:34:42.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:42.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:34:42.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:34:42.10#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:42.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:42.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:42.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:42.22#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:34:42.22#ibcon#first serial, iclass 32, count 0 2006.281.07:34:42.22#ibcon#enter sib2, iclass 32, count 0 2006.281.07:34:42.22#ibcon#flushed, iclass 32, count 0 2006.281.07:34:42.22#ibcon#about to write, iclass 32, count 0 2006.281.07:34:42.22#ibcon#wrote, iclass 32, count 0 2006.281.07:34:42.22#ibcon#about to read 3, iclass 32, count 0 2006.281.07:34:42.24#ibcon#read 3, iclass 32, count 0 2006.281.07:34:42.24#ibcon#about to read 4, iclass 32, count 0 2006.281.07:34:42.24#ibcon#read 4, iclass 32, count 0 2006.281.07:34:42.24#ibcon#about to read 5, iclass 32, count 0 2006.281.07:34:42.24#ibcon#read 5, iclass 32, count 0 2006.281.07:34:42.24#ibcon#about to read 6, iclass 32, count 0 2006.281.07:34:42.24#ibcon#read 6, iclass 32, count 0 2006.281.07:34:42.24#ibcon#end of sib2, iclass 32, count 0 2006.281.07:34:42.24#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:34:42.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:34:42.24#ibcon#[27=USB\r\n] 2006.281.07:34:42.24#ibcon#*before write, iclass 32, count 0 2006.281.07:34:42.24#ibcon#enter sib2, iclass 32, count 0 2006.281.07:34:42.24#ibcon#flushed, iclass 32, count 0 2006.281.07:34:42.24#ibcon#about to write, iclass 32, count 0 2006.281.07:34:42.24#ibcon#wrote, iclass 32, count 0 2006.281.07:34:42.24#ibcon#about to read 3, iclass 32, count 0 2006.281.07:34:42.27#ibcon#read 3, iclass 32, count 0 2006.281.07:34:42.27#ibcon#about to read 4, iclass 32, count 0 2006.281.07:34:42.27#ibcon#read 4, iclass 32, count 0 2006.281.07:34:42.27#ibcon#about to read 5, iclass 32, count 0 2006.281.07:34:42.27#ibcon#read 5, iclass 32, count 0 2006.281.07:34:42.27#ibcon#about to read 6, iclass 32, count 0 2006.281.07:34:42.27#ibcon#read 6, iclass 32, count 0 2006.281.07:34:42.27#ibcon#end of sib2, iclass 32, count 0 2006.281.07:34:42.27#ibcon#*after write, iclass 32, count 0 2006.281.07:34:42.27#ibcon#*before return 0, iclass 32, count 0 2006.281.07:34:42.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:42.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:34:42.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:34:42.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:34:42.27$vc4f8/vblo=3,656.99 2006.281.07:34:42.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:34:42.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:34:42.27#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:42.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:42.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:42.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:42.27#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:34:42.27#ibcon#first serial, iclass 34, count 0 2006.281.07:34:42.27#ibcon#enter sib2, iclass 34, count 0 2006.281.07:34:42.27#ibcon#flushed, iclass 34, count 0 2006.281.07:34:42.27#ibcon#about to write, iclass 34, count 0 2006.281.07:34:42.27#ibcon#wrote, iclass 34, count 0 2006.281.07:34:42.27#ibcon#about to read 3, iclass 34, count 0 2006.281.07:34:42.29#ibcon#read 3, iclass 34, count 0 2006.281.07:34:42.29#ibcon#about to read 4, iclass 34, count 0 2006.281.07:34:42.29#ibcon#read 4, iclass 34, count 0 2006.281.07:34:42.29#ibcon#about to read 5, iclass 34, count 0 2006.281.07:34:42.29#ibcon#read 5, iclass 34, count 0 2006.281.07:34:42.29#ibcon#about to read 6, iclass 34, count 0 2006.281.07:34:42.29#ibcon#read 6, iclass 34, count 0 2006.281.07:34:42.29#ibcon#end of sib2, iclass 34, count 0 2006.281.07:34:42.29#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:34:42.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:34:42.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:34:42.29#ibcon#*before write, iclass 34, count 0 2006.281.07:34:42.29#ibcon#enter sib2, iclass 34, count 0 2006.281.07:34:42.29#ibcon#flushed, iclass 34, count 0 2006.281.07:34:42.29#ibcon#about to write, iclass 34, count 0 2006.281.07:34:42.29#ibcon#wrote, iclass 34, count 0 2006.281.07:34:42.29#ibcon#about to read 3, iclass 34, count 0 2006.281.07:34:42.34#ibcon#read 3, iclass 34, count 0 2006.281.07:34:42.34#ibcon#about to read 4, iclass 34, count 0 2006.281.07:34:42.34#ibcon#read 4, iclass 34, count 0 2006.281.07:34:42.34#ibcon#about to read 5, iclass 34, count 0 2006.281.07:34:42.34#ibcon#read 5, iclass 34, count 0 2006.281.07:34:42.34#ibcon#about to read 6, iclass 34, count 0 2006.281.07:34:42.34#ibcon#read 6, iclass 34, count 0 2006.281.07:34:42.34#ibcon#end of sib2, iclass 34, count 0 2006.281.07:34:42.34#ibcon#*after write, iclass 34, count 0 2006.281.07:34:42.34#ibcon#*before return 0, iclass 34, count 0 2006.281.07:34:42.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:42.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:34:42.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:34:42.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:34:42.34$vc4f8/vb=3,4 2006.281.07:34:42.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:34:42.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:34:42.34#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:42.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:42.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:42.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:42.39#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:34:42.39#ibcon#first serial, iclass 36, count 2 2006.281.07:34:42.39#ibcon#enter sib2, iclass 36, count 2 2006.281.07:34:42.39#ibcon#flushed, iclass 36, count 2 2006.281.07:34:42.39#ibcon#about to write, iclass 36, count 2 2006.281.07:34:42.39#ibcon#wrote, iclass 36, count 2 2006.281.07:34:42.39#ibcon#about to read 3, iclass 36, count 2 2006.281.07:34:42.41#ibcon#read 3, iclass 36, count 2 2006.281.07:34:42.41#ibcon#about to read 4, iclass 36, count 2 2006.281.07:34:42.41#ibcon#read 4, iclass 36, count 2 2006.281.07:34:42.41#ibcon#about to read 5, iclass 36, count 2 2006.281.07:34:42.41#ibcon#read 5, iclass 36, count 2 2006.281.07:34:42.41#ibcon#about to read 6, iclass 36, count 2 2006.281.07:34:42.41#ibcon#read 6, iclass 36, count 2 2006.281.07:34:42.41#ibcon#end of sib2, iclass 36, count 2 2006.281.07:34:42.41#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:34:42.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:34:42.41#ibcon#[27=AT03-04\r\n] 2006.281.07:34:42.41#ibcon#*before write, iclass 36, count 2 2006.281.07:34:42.41#ibcon#enter sib2, iclass 36, count 2 2006.281.07:34:42.41#ibcon#flushed, iclass 36, count 2 2006.281.07:34:42.41#ibcon#about to write, iclass 36, count 2 2006.281.07:34:42.41#ibcon#wrote, iclass 36, count 2 2006.281.07:34:42.41#ibcon#about to read 3, iclass 36, count 2 2006.281.07:34:42.44#ibcon#read 3, iclass 36, count 2 2006.281.07:34:42.44#ibcon#about to read 4, iclass 36, count 2 2006.281.07:34:42.44#ibcon#read 4, iclass 36, count 2 2006.281.07:34:42.44#ibcon#about to read 5, iclass 36, count 2 2006.281.07:34:42.44#ibcon#read 5, iclass 36, count 2 2006.281.07:34:42.44#ibcon#about to read 6, iclass 36, count 2 2006.281.07:34:42.44#ibcon#read 6, iclass 36, count 2 2006.281.07:34:42.44#ibcon#end of sib2, iclass 36, count 2 2006.281.07:34:42.44#ibcon#*after write, iclass 36, count 2 2006.281.07:34:42.44#ibcon#*before return 0, iclass 36, count 2 2006.281.07:34:42.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:42.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:34:42.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:34:42.44#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:42.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:42.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:42.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:42.56#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:34:42.56#ibcon#first serial, iclass 36, count 0 2006.281.07:34:42.56#ibcon#enter sib2, iclass 36, count 0 2006.281.07:34:42.56#ibcon#flushed, iclass 36, count 0 2006.281.07:34:42.56#ibcon#about to write, iclass 36, count 0 2006.281.07:34:42.56#ibcon#wrote, iclass 36, count 0 2006.281.07:34:42.56#ibcon#about to read 3, iclass 36, count 0 2006.281.07:34:42.58#ibcon#read 3, iclass 36, count 0 2006.281.07:34:42.58#ibcon#about to read 4, iclass 36, count 0 2006.281.07:34:42.58#ibcon#read 4, iclass 36, count 0 2006.281.07:34:42.58#ibcon#about to read 5, iclass 36, count 0 2006.281.07:34:42.58#ibcon#read 5, iclass 36, count 0 2006.281.07:34:42.58#ibcon#about to read 6, iclass 36, count 0 2006.281.07:34:42.58#ibcon#read 6, iclass 36, count 0 2006.281.07:34:42.58#ibcon#end of sib2, iclass 36, count 0 2006.281.07:34:42.58#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:34:42.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:34:42.58#ibcon#[27=USB\r\n] 2006.281.07:34:42.58#ibcon#*before write, iclass 36, count 0 2006.281.07:34:42.58#ibcon#enter sib2, iclass 36, count 0 2006.281.07:34:42.58#ibcon#flushed, iclass 36, count 0 2006.281.07:34:42.58#ibcon#about to write, iclass 36, count 0 2006.281.07:34:42.58#ibcon#wrote, iclass 36, count 0 2006.281.07:34:42.58#ibcon#about to read 3, iclass 36, count 0 2006.281.07:34:42.61#ibcon#read 3, iclass 36, count 0 2006.281.07:34:42.61#ibcon#about to read 4, iclass 36, count 0 2006.281.07:34:42.61#ibcon#read 4, iclass 36, count 0 2006.281.07:34:42.61#ibcon#about to read 5, iclass 36, count 0 2006.281.07:34:42.61#ibcon#read 5, iclass 36, count 0 2006.281.07:34:42.61#ibcon#about to read 6, iclass 36, count 0 2006.281.07:34:42.61#ibcon#read 6, iclass 36, count 0 2006.281.07:34:42.61#ibcon#end of sib2, iclass 36, count 0 2006.281.07:34:42.61#ibcon#*after write, iclass 36, count 0 2006.281.07:34:42.61#ibcon#*before return 0, iclass 36, count 0 2006.281.07:34:42.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:42.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:34:42.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:34:42.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:34:42.61$vc4f8/vblo=4,712.99 2006.281.07:34:42.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:34:42.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:34:42.61#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:42.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:42.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:42.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:42.61#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:34:42.61#ibcon#first serial, iclass 38, count 0 2006.281.07:34:42.61#ibcon#enter sib2, iclass 38, count 0 2006.281.07:34:42.61#ibcon#flushed, iclass 38, count 0 2006.281.07:34:42.61#ibcon#about to write, iclass 38, count 0 2006.281.07:34:42.61#ibcon#wrote, iclass 38, count 0 2006.281.07:34:42.61#ibcon#about to read 3, iclass 38, count 0 2006.281.07:34:42.63#ibcon#read 3, iclass 38, count 0 2006.281.07:34:42.63#ibcon#about to read 4, iclass 38, count 0 2006.281.07:34:42.63#ibcon#read 4, iclass 38, count 0 2006.281.07:34:42.63#ibcon#about to read 5, iclass 38, count 0 2006.281.07:34:42.63#ibcon#read 5, iclass 38, count 0 2006.281.07:34:42.63#ibcon#about to read 6, iclass 38, count 0 2006.281.07:34:42.63#ibcon#read 6, iclass 38, count 0 2006.281.07:34:42.63#ibcon#end of sib2, iclass 38, count 0 2006.281.07:34:42.63#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:34:42.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:34:42.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:34:42.63#ibcon#*before write, iclass 38, count 0 2006.281.07:34:42.63#ibcon#enter sib2, iclass 38, count 0 2006.281.07:34:42.63#ibcon#flushed, iclass 38, count 0 2006.281.07:34:42.63#ibcon#about to write, iclass 38, count 0 2006.281.07:34:42.63#ibcon#wrote, iclass 38, count 0 2006.281.07:34:42.63#ibcon#about to read 3, iclass 38, count 0 2006.281.07:34:42.67#ibcon#read 3, iclass 38, count 0 2006.281.07:34:42.67#ibcon#about to read 4, iclass 38, count 0 2006.281.07:34:42.67#ibcon#read 4, iclass 38, count 0 2006.281.07:34:42.67#ibcon#about to read 5, iclass 38, count 0 2006.281.07:34:42.67#ibcon#read 5, iclass 38, count 0 2006.281.07:34:42.67#ibcon#about to read 6, iclass 38, count 0 2006.281.07:34:42.67#ibcon#read 6, iclass 38, count 0 2006.281.07:34:42.67#ibcon#end of sib2, iclass 38, count 0 2006.281.07:34:42.67#ibcon#*after write, iclass 38, count 0 2006.281.07:34:42.67#ibcon#*before return 0, iclass 38, count 0 2006.281.07:34:42.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:42.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:34:42.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:34:42.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:34:42.67$vc4f8/vb=4,4 2006.281.07:34:42.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:34:42.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:34:42.67#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:42.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:42.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:42.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:42.73#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:34:42.73#ibcon#first serial, iclass 40, count 2 2006.281.07:34:42.73#ibcon#enter sib2, iclass 40, count 2 2006.281.07:34:42.73#ibcon#flushed, iclass 40, count 2 2006.281.07:34:42.73#ibcon#about to write, iclass 40, count 2 2006.281.07:34:42.73#ibcon#wrote, iclass 40, count 2 2006.281.07:34:42.73#ibcon#about to read 3, iclass 40, count 2 2006.281.07:34:42.75#ibcon#read 3, iclass 40, count 2 2006.281.07:34:42.75#ibcon#about to read 4, iclass 40, count 2 2006.281.07:34:42.75#ibcon#read 4, iclass 40, count 2 2006.281.07:34:42.75#ibcon#about to read 5, iclass 40, count 2 2006.281.07:34:42.75#ibcon#read 5, iclass 40, count 2 2006.281.07:34:42.75#ibcon#about to read 6, iclass 40, count 2 2006.281.07:34:42.75#ibcon#read 6, iclass 40, count 2 2006.281.07:34:42.75#ibcon#end of sib2, iclass 40, count 2 2006.281.07:34:42.75#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:34:42.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:34:42.75#ibcon#[27=AT04-04\r\n] 2006.281.07:34:42.75#ibcon#*before write, iclass 40, count 2 2006.281.07:34:42.75#ibcon#enter sib2, iclass 40, count 2 2006.281.07:34:42.75#ibcon#flushed, iclass 40, count 2 2006.281.07:34:42.75#ibcon#about to write, iclass 40, count 2 2006.281.07:34:42.75#ibcon#wrote, iclass 40, count 2 2006.281.07:34:42.75#ibcon#about to read 3, iclass 40, count 2 2006.281.07:34:42.78#ibcon#read 3, iclass 40, count 2 2006.281.07:34:42.78#ibcon#about to read 4, iclass 40, count 2 2006.281.07:34:42.78#ibcon#read 4, iclass 40, count 2 2006.281.07:34:42.78#ibcon#about to read 5, iclass 40, count 2 2006.281.07:34:42.78#ibcon#read 5, iclass 40, count 2 2006.281.07:34:42.78#ibcon#about to read 6, iclass 40, count 2 2006.281.07:34:42.78#ibcon#read 6, iclass 40, count 2 2006.281.07:34:42.78#ibcon#end of sib2, iclass 40, count 2 2006.281.07:34:42.78#ibcon#*after write, iclass 40, count 2 2006.281.07:34:42.78#ibcon#*before return 0, iclass 40, count 2 2006.281.07:34:42.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:42.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:34:42.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:34:42.78#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:42.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:42.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:42.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:42.90#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:34:42.90#ibcon#first serial, iclass 40, count 0 2006.281.07:34:42.90#ibcon#enter sib2, iclass 40, count 0 2006.281.07:34:42.90#ibcon#flushed, iclass 40, count 0 2006.281.07:34:42.90#ibcon#about to write, iclass 40, count 0 2006.281.07:34:42.90#ibcon#wrote, iclass 40, count 0 2006.281.07:34:42.90#ibcon#about to read 3, iclass 40, count 0 2006.281.07:34:42.92#ibcon#read 3, iclass 40, count 0 2006.281.07:34:42.92#ibcon#about to read 4, iclass 40, count 0 2006.281.07:34:42.92#ibcon#read 4, iclass 40, count 0 2006.281.07:34:42.92#ibcon#about to read 5, iclass 40, count 0 2006.281.07:34:42.92#ibcon#read 5, iclass 40, count 0 2006.281.07:34:42.92#ibcon#about to read 6, iclass 40, count 0 2006.281.07:34:42.92#ibcon#read 6, iclass 40, count 0 2006.281.07:34:42.92#ibcon#end of sib2, iclass 40, count 0 2006.281.07:34:42.92#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:34:42.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:34:42.92#ibcon#[27=USB\r\n] 2006.281.07:34:42.92#ibcon#*before write, iclass 40, count 0 2006.281.07:34:42.92#ibcon#enter sib2, iclass 40, count 0 2006.281.07:34:42.92#ibcon#flushed, iclass 40, count 0 2006.281.07:34:42.92#ibcon#about to write, iclass 40, count 0 2006.281.07:34:42.92#ibcon#wrote, iclass 40, count 0 2006.281.07:34:42.92#ibcon#about to read 3, iclass 40, count 0 2006.281.07:34:42.95#ibcon#read 3, iclass 40, count 0 2006.281.07:34:42.95#ibcon#about to read 4, iclass 40, count 0 2006.281.07:34:42.95#ibcon#read 4, iclass 40, count 0 2006.281.07:34:42.95#ibcon#about to read 5, iclass 40, count 0 2006.281.07:34:42.95#ibcon#read 5, iclass 40, count 0 2006.281.07:34:42.95#ibcon#about to read 6, iclass 40, count 0 2006.281.07:34:42.95#ibcon#read 6, iclass 40, count 0 2006.281.07:34:42.95#ibcon#end of sib2, iclass 40, count 0 2006.281.07:34:42.95#ibcon#*after write, iclass 40, count 0 2006.281.07:34:42.95#ibcon#*before return 0, iclass 40, count 0 2006.281.07:34:42.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:42.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:34:42.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:34:42.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:34:42.95$vc4f8/vblo=5,744.99 2006.281.07:34:42.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:34:42.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:34:42.95#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:42.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:34:42.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:34:42.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:34:42.95#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:34:42.95#ibcon#first serial, iclass 4, count 0 2006.281.07:34:42.95#ibcon#enter sib2, iclass 4, count 0 2006.281.07:34:42.95#ibcon#flushed, iclass 4, count 0 2006.281.07:34:42.95#ibcon#about to write, iclass 4, count 0 2006.281.07:34:42.95#ibcon#wrote, iclass 4, count 0 2006.281.07:34:42.95#ibcon#about to read 3, iclass 4, count 0 2006.281.07:34:42.97#ibcon#read 3, iclass 4, count 0 2006.281.07:34:42.97#ibcon#about to read 4, iclass 4, count 0 2006.281.07:34:42.97#ibcon#read 4, iclass 4, count 0 2006.281.07:34:42.97#ibcon#about to read 5, iclass 4, count 0 2006.281.07:34:42.97#ibcon#read 5, iclass 4, count 0 2006.281.07:34:42.97#ibcon#about to read 6, iclass 4, count 0 2006.281.07:34:42.97#ibcon#read 6, iclass 4, count 0 2006.281.07:34:42.97#ibcon#end of sib2, iclass 4, count 0 2006.281.07:34:42.97#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:34:42.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:34:42.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:34:42.97#ibcon#*before write, iclass 4, count 0 2006.281.07:34:42.97#ibcon#enter sib2, iclass 4, count 0 2006.281.07:34:42.97#ibcon#flushed, iclass 4, count 0 2006.281.07:34:42.97#ibcon#about to write, iclass 4, count 0 2006.281.07:34:42.97#ibcon#wrote, iclass 4, count 0 2006.281.07:34:42.97#ibcon#about to read 3, iclass 4, count 0 2006.281.07:34:43.02#ibcon#read 3, iclass 4, count 0 2006.281.07:34:43.02#ibcon#about to read 4, iclass 4, count 0 2006.281.07:34:43.02#ibcon#read 4, iclass 4, count 0 2006.281.07:34:43.02#ibcon#about to read 5, iclass 4, count 0 2006.281.07:34:43.02#ibcon#read 5, iclass 4, count 0 2006.281.07:34:43.02#ibcon#about to read 6, iclass 4, count 0 2006.281.07:34:43.02#ibcon#read 6, iclass 4, count 0 2006.281.07:34:43.02#ibcon#end of sib2, iclass 4, count 0 2006.281.07:34:43.02#ibcon#*after write, iclass 4, count 0 2006.281.07:34:43.02#ibcon#*before return 0, iclass 4, count 0 2006.281.07:34:43.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:34:43.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:34:43.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:34:43.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:34:43.02$vc4f8/vb=5,4 2006.281.07:34:43.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:34:43.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:34:43.02#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:43.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:34:43.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:34:43.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:34:43.07#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:34:43.07#ibcon#first serial, iclass 6, count 2 2006.281.07:34:43.07#ibcon#enter sib2, iclass 6, count 2 2006.281.07:34:43.07#ibcon#flushed, iclass 6, count 2 2006.281.07:34:43.07#ibcon#about to write, iclass 6, count 2 2006.281.07:34:43.07#ibcon#wrote, iclass 6, count 2 2006.281.07:34:43.07#ibcon#about to read 3, iclass 6, count 2 2006.281.07:34:43.09#ibcon#read 3, iclass 6, count 2 2006.281.07:34:43.09#ibcon#about to read 4, iclass 6, count 2 2006.281.07:34:43.09#ibcon#read 4, iclass 6, count 2 2006.281.07:34:43.09#ibcon#about to read 5, iclass 6, count 2 2006.281.07:34:43.09#ibcon#read 5, iclass 6, count 2 2006.281.07:34:43.09#ibcon#about to read 6, iclass 6, count 2 2006.281.07:34:43.09#ibcon#read 6, iclass 6, count 2 2006.281.07:34:43.09#ibcon#end of sib2, iclass 6, count 2 2006.281.07:34:43.09#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:34:43.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:34:43.09#ibcon#[27=AT05-04\r\n] 2006.281.07:34:43.09#ibcon#*before write, iclass 6, count 2 2006.281.07:34:43.09#ibcon#enter sib2, iclass 6, count 2 2006.281.07:34:43.09#ibcon#flushed, iclass 6, count 2 2006.281.07:34:43.09#ibcon#about to write, iclass 6, count 2 2006.281.07:34:43.09#ibcon#wrote, iclass 6, count 2 2006.281.07:34:43.09#ibcon#about to read 3, iclass 6, count 2 2006.281.07:34:43.12#ibcon#read 3, iclass 6, count 2 2006.281.07:34:43.12#ibcon#about to read 4, iclass 6, count 2 2006.281.07:34:43.12#ibcon#read 4, iclass 6, count 2 2006.281.07:34:43.12#ibcon#about to read 5, iclass 6, count 2 2006.281.07:34:43.12#ibcon#read 5, iclass 6, count 2 2006.281.07:34:43.12#ibcon#about to read 6, iclass 6, count 2 2006.281.07:34:43.12#ibcon#read 6, iclass 6, count 2 2006.281.07:34:43.12#ibcon#end of sib2, iclass 6, count 2 2006.281.07:34:43.12#ibcon#*after write, iclass 6, count 2 2006.281.07:34:43.12#ibcon#*before return 0, iclass 6, count 2 2006.281.07:34:43.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:34:43.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:34:43.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:34:43.12#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:43.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:34:43.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:34:43.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:34:43.24#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:34:43.24#ibcon#first serial, iclass 6, count 0 2006.281.07:34:43.24#ibcon#enter sib2, iclass 6, count 0 2006.281.07:34:43.24#ibcon#flushed, iclass 6, count 0 2006.281.07:34:43.24#ibcon#about to write, iclass 6, count 0 2006.281.07:34:43.24#ibcon#wrote, iclass 6, count 0 2006.281.07:34:43.24#ibcon#about to read 3, iclass 6, count 0 2006.281.07:34:43.26#ibcon#read 3, iclass 6, count 0 2006.281.07:34:43.26#ibcon#about to read 4, iclass 6, count 0 2006.281.07:34:43.26#ibcon#read 4, iclass 6, count 0 2006.281.07:34:43.26#ibcon#about to read 5, iclass 6, count 0 2006.281.07:34:43.26#ibcon#read 5, iclass 6, count 0 2006.281.07:34:43.26#ibcon#about to read 6, iclass 6, count 0 2006.281.07:34:43.26#ibcon#read 6, iclass 6, count 0 2006.281.07:34:43.26#ibcon#end of sib2, iclass 6, count 0 2006.281.07:34:43.26#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:34:43.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:34:43.26#ibcon#[27=USB\r\n] 2006.281.07:34:43.26#ibcon#*before write, iclass 6, count 0 2006.281.07:34:43.26#ibcon#enter sib2, iclass 6, count 0 2006.281.07:34:43.26#ibcon#flushed, iclass 6, count 0 2006.281.07:34:43.26#ibcon#about to write, iclass 6, count 0 2006.281.07:34:43.26#ibcon#wrote, iclass 6, count 0 2006.281.07:34:43.26#ibcon#about to read 3, iclass 6, count 0 2006.281.07:34:43.29#ibcon#read 3, iclass 6, count 0 2006.281.07:34:43.29#ibcon#about to read 4, iclass 6, count 0 2006.281.07:34:43.29#ibcon#read 4, iclass 6, count 0 2006.281.07:34:43.29#ibcon#about to read 5, iclass 6, count 0 2006.281.07:34:43.29#ibcon#read 5, iclass 6, count 0 2006.281.07:34:43.29#ibcon#about to read 6, iclass 6, count 0 2006.281.07:34:43.29#ibcon#read 6, iclass 6, count 0 2006.281.07:34:43.29#ibcon#end of sib2, iclass 6, count 0 2006.281.07:34:43.29#ibcon#*after write, iclass 6, count 0 2006.281.07:34:43.29#ibcon#*before return 0, iclass 6, count 0 2006.281.07:34:43.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:34:43.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:34:43.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:34:43.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:34:43.29$vc4f8/vblo=6,752.99 2006.281.07:34:43.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:34:43.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:34:43.29#ibcon#ireg 17 cls_cnt 0 2006.281.07:34:43.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:43.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:43.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:43.29#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:34:43.29#ibcon#first serial, iclass 10, count 0 2006.281.07:34:43.29#ibcon#enter sib2, iclass 10, count 0 2006.281.07:34:43.29#ibcon#flushed, iclass 10, count 0 2006.281.07:34:43.29#ibcon#about to write, iclass 10, count 0 2006.281.07:34:43.29#ibcon#wrote, iclass 10, count 0 2006.281.07:34:43.29#ibcon#about to read 3, iclass 10, count 0 2006.281.07:34:43.31#ibcon#read 3, iclass 10, count 0 2006.281.07:34:43.31#ibcon#about to read 4, iclass 10, count 0 2006.281.07:34:43.31#ibcon#read 4, iclass 10, count 0 2006.281.07:34:43.31#ibcon#about to read 5, iclass 10, count 0 2006.281.07:34:43.31#ibcon#read 5, iclass 10, count 0 2006.281.07:34:43.31#ibcon#about to read 6, iclass 10, count 0 2006.281.07:34:43.31#ibcon#read 6, iclass 10, count 0 2006.281.07:34:43.31#ibcon#end of sib2, iclass 10, count 0 2006.281.07:34:43.31#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:34:43.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:34:43.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:34:43.31#ibcon#*before write, iclass 10, count 0 2006.281.07:34:43.31#ibcon#enter sib2, iclass 10, count 0 2006.281.07:34:43.31#ibcon#flushed, iclass 10, count 0 2006.281.07:34:43.31#ibcon#about to write, iclass 10, count 0 2006.281.07:34:43.31#ibcon#wrote, iclass 10, count 0 2006.281.07:34:43.31#ibcon#about to read 3, iclass 10, count 0 2006.281.07:34:43.35#ibcon#read 3, iclass 10, count 0 2006.281.07:34:43.35#ibcon#about to read 4, iclass 10, count 0 2006.281.07:34:43.35#ibcon#read 4, iclass 10, count 0 2006.281.07:34:43.35#ibcon#about to read 5, iclass 10, count 0 2006.281.07:34:43.35#ibcon#read 5, iclass 10, count 0 2006.281.07:34:43.35#ibcon#about to read 6, iclass 10, count 0 2006.281.07:34:43.35#ibcon#read 6, iclass 10, count 0 2006.281.07:34:43.35#ibcon#end of sib2, iclass 10, count 0 2006.281.07:34:43.35#ibcon#*after write, iclass 10, count 0 2006.281.07:34:43.35#ibcon#*before return 0, iclass 10, count 0 2006.281.07:34:43.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:43.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:34:43.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:34:43.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:34:43.35$vc4f8/vb=6,4 2006.281.07:34:43.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:34:43.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:34:43.35#ibcon#ireg 11 cls_cnt 2 2006.281.07:34:43.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:43.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:43.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:43.41#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:34:43.41#ibcon#first serial, iclass 12, count 2 2006.281.07:34:43.41#ibcon#enter sib2, iclass 12, count 2 2006.281.07:34:43.41#ibcon#flushed, iclass 12, count 2 2006.281.07:34:43.41#ibcon#about to write, iclass 12, count 2 2006.281.07:34:43.41#ibcon#wrote, iclass 12, count 2 2006.281.07:34:43.41#ibcon#about to read 3, iclass 12, count 2 2006.281.07:34:43.43#ibcon#read 3, iclass 12, count 2 2006.281.07:34:43.43#ibcon#about to read 4, iclass 12, count 2 2006.281.07:34:43.43#ibcon#read 4, iclass 12, count 2 2006.281.07:34:43.43#ibcon#about to read 5, iclass 12, count 2 2006.281.07:34:43.43#ibcon#read 5, iclass 12, count 2 2006.281.07:34:43.43#ibcon#about to read 6, iclass 12, count 2 2006.281.07:34:43.43#ibcon#read 6, iclass 12, count 2 2006.281.07:34:43.43#ibcon#end of sib2, iclass 12, count 2 2006.281.07:34:43.43#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:34:43.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:34:43.43#ibcon#[27=AT06-04\r\n] 2006.281.07:34:43.43#ibcon#*before write, iclass 12, count 2 2006.281.07:34:43.43#ibcon#enter sib2, iclass 12, count 2 2006.281.07:34:43.43#ibcon#flushed, iclass 12, count 2 2006.281.07:34:43.43#ibcon#about to write, iclass 12, count 2 2006.281.07:34:43.43#ibcon#wrote, iclass 12, count 2 2006.281.07:34:43.43#ibcon#about to read 3, iclass 12, count 2 2006.281.07:34:43.47#ibcon#read 3, iclass 12, count 2 2006.281.07:34:43.47#ibcon#about to read 4, iclass 12, count 2 2006.281.07:34:43.47#ibcon#read 4, iclass 12, count 2 2006.281.07:34:43.47#ibcon#about to read 5, iclass 12, count 2 2006.281.07:34:43.47#ibcon#read 5, iclass 12, count 2 2006.281.07:34:43.47#ibcon#about to read 6, iclass 12, count 2 2006.281.07:34:43.47#ibcon#read 6, iclass 12, count 2 2006.281.07:34:43.47#ibcon#end of sib2, iclass 12, count 2 2006.281.07:34:43.47#ibcon#*after write, iclass 12, count 2 2006.281.07:34:43.47#ibcon#*before return 0, iclass 12, count 2 2006.281.07:34:43.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:43.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:34:43.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:34:43.47#ibcon#ireg 7 cls_cnt 0 2006.281.07:34:43.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:43.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:43.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:43.59#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:34:43.59#ibcon#first serial, iclass 12, count 0 2006.281.07:34:43.59#ibcon#enter sib2, iclass 12, count 0 2006.281.07:34:43.59#ibcon#flushed, iclass 12, count 0 2006.281.07:34:43.59#ibcon#about to write, iclass 12, count 0 2006.281.07:34:43.59#ibcon#wrote, iclass 12, count 0 2006.281.07:34:43.59#ibcon#about to read 3, iclass 12, count 0 2006.281.07:34:43.61#ibcon#read 3, iclass 12, count 0 2006.281.07:34:43.61#ibcon#about to read 4, iclass 12, count 0 2006.281.07:34:43.61#ibcon#read 4, iclass 12, count 0 2006.281.07:34:43.61#ibcon#about to read 5, iclass 12, count 0 2006.281.07:34:43.61#ibcon#read 5, iclass 12, count 0 2006.281.07:34:43.61#ibcon#about to read 6, iclass 12, count 0 2006.281.07:34:43.61#ibcon#read 6, iclass 12, count 0 2006.281.07:34:43.61#ibcon#end of sib2, iclass 12, count 0 2006.281.07:34:43.61#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:34:43.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:34:43.61#ibcon#[27=USB\r\n] 2006.281.07:34:43.61#ibcon#*before write, iclass 12, count 0 2006.281.07:34:43.61#ibcon#enter sib2, iclass 12, count 0 2006.281.07:34:43.61#ibcon#flushed, iclass 12, count 0 2006.281.07:34:43.61#ibcon#about to write, iclass 12, count 0 2006.281.07:34:43.61#ibcon#wrote, iclass 12, count 0 2006.281.07:34:43.61#ibcon#about to read 3, iclass 12, count 0 2006.281.07:34:43.64#ibcon#read 3, iclass 12, count 0 2006.281.07:34:43.64#ibcon#about to read 4, iclass 12, count 0 2006.281.07:34:43.64#ibcon#read 4, iclass 12, count 0 2006.281.07:34:43.64#ibcon#about to read 5, iclass 12, count 0 2006.281.07:34:43.64#ibcon#read 5, iclass 12, count 0 2006.281.07:34:43.64#ibcon#about to read 6, iclass 12, count 0 2006.281.07:34:43.64#ibcon#read 6, iclass 12, count 0 2006.281.07:34:43.64#ibcon#end of sib2, iclass 12, count 0 2006.281.07:34:43.64#ibcon#*after write, iclass 12, count 0 2006.281.07:34:43.64#ibcon#*before return 0, iclass 12, count 0 2006.281.07:34:43.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:43.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:34:43.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:34:43.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:34:43.64$vc4f8/vabw=wide 2006.281.07:34:43.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:34:43.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:34:43.64#ibcon#ireg 8 cls_cnt 0 2006.281.07:34:43.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:43.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:43.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:43.64#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:34:43.64#ibcon#first serial, iclass 14, count 0 2006.281.07:34:43.64#ibcon#enter sib2, iclass 14, count 0 2006.281.07:34:43.64#ibcon#flushed, iclass 14, count 0 2006.281.07:34:43.64#ibcon#about to write, iclass 14, count 0 2006.281.07:34:43.64#ibcon#wrote, iclass 14, count 0 2006.281.07:34:43.64#ibcon#about to read 3, iclass 14, count 0 2006.281.07:34:43.66#ibcon#read 3, iclass 14, count 0 2006.281.07:34:43.66#ibcon#about to read 4, iclass 14, count 0 2006.281.07:34:43.66#ibcon#read 4, iclass 14, count 0 2006.281.07:34:43.66#ibcon#about to read 5, iclass 14, count 0 2006.281.07:34:43.66#ibcon#read 5, iclass 14, count 0 2006.281.07:34:43.66#ibcon#about to read 6, iclass 14, count 0 2006.281.07:34:43.66#ibcon#read 6, iclass 14, count 0 2006.281.07:34:43.66#ibcon#end of sib2, iclass 14, count 0 2006.281.07:34:43.66#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:34:43.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:34:43.66#ibcon#[25=BW32\r\n] 2006.281.07:34:43.66#ibcon#*before write, iclass 14, count 0 2006.281.07:34:43.66#ibcon#enter sib2, iclass 14, count 0 2006.281.07:34:43.66#ibcon#flushed, iclass 14, count 0 2006.281.07:34:43.66#ibcon#about to write, iclass 14, count 0 2006.281.07:34:43.66#ibcon#wrote, iclass 14, count 0 2006.281.07:34:43.66#ibcon#about to read 3, iclass 14, count 0 2006.281.07:34:43.69#ibcon#read 3, iclass 14, count 0 2006.281.07:34:43.69#ibcon#about to read 4, iclass 14, count 0 2006.281.07:34:43.69#ibcon#read 4, iclass 14, count 0 2006.281.07:34:43.69#ibcon#about to read 5, iclass 14, count 0 2006.281.07:34:43.69#ibcon#read 5, iclass 14, count 0 2006.281.07:34:43.69#ibcon#about to read 6, iclass 14, count 0 2006.281.07:34:43.69#ibcon#read 6, iclass 14, count 0 2006.281.07:34:43.69#ibcon#end of sib2, iclass 14, count 0 2006.281.07:34:43.69#ibcon#*after write, iclass 14, count 0 2006.281.07:34:43.69#ibcon#*before return 0, iclass 14, count 0 2006.281.07:34:43.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:43.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:34:43.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:34:43.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:34:43.69$vc4f8/vbbw=wide 2006.281.07:34:43.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:34:43.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:34:43.69#ibcon#ireg 8 cls_cnt 0 2006.281.07:34:43.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:34:43.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:34:43.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:34:43.76#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:34:43.76#ibcon#first serial, iclass 16, count 0 2006.281.07:34:43.76#ibcon#enter sib2, iclass 16, count 0 2006.281.07:34:43.76#ibcon#flushed, iclass 16, count 0 2006.281.07:34:43.76#ibcon#about to write, iclass 16, count 0 2006.281.07:34:43.76#ibcon#wrote, iclass 16, count 0 2006.281.07:34:43.76#ibcon#about to read 3, iclass 16, count 0 2006.281.07:34:43.78#ibcon#read 3, iclass 16, count 0 2006.281.07:34:43.78#ibcon#about to read 4, iclass 16, count 0 2006.281.07:34:43.78#ibcon#read 4, iclass 16, count 0 2006.281.07:34:43.78#ibcon#about to read 5, iclass 16, count 0 2006.281.07:34:43.78#ibcon#read 5, iclass 16, count 0 2006.281.07:34:43.78#ibcon#about to read 6, iclass 16, count 0 2006.281.07:34:43.78#ibcon#read 6, iclass 16, count 0 2006.281.07:34:43.78#ibcon#end of sib2, iclass 16, count 0 2006.281.07:34:43.78#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:34:43.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:34:43.78#ibcon#[27=BW32\r\n] 2006.281.07:34:43.78#ibcon#*before write, iclass 16, count 0 2006.281.07:34:43.78#ibcon#enter sib2, iclass 16, count 0 2006.281.07:34:43.78#ibcon#flushed, iclass 16, count 0 2006.281.07:34:43.78#ibcon#about to write, iclass 16, count 0 2006.281.07:34:43.78#ibcon#wrote, iclass 16, count 0 2006.281.07:34:43.78#ibcon#about to read 3, iclass 16, count 0 2006.281.07:34:43.81#ibcon#read 3, iclass 16, count 0 2006.281.07:34:43.81#ibcon#about to read 4, iclass 16, count 0 2006.281.07:34:43.81#ibcon#read 4, iclass 16, count 0 2006.281.07:34:43.81#ibcon#about to read 5, iclass 16, count 0 2006.281.07:34:43.81#ibcon#read 5, iclass 16, count 0 2006.281.07:34:43.81#ibcon#about to read 6, iclass 16, count 0 2006.281.07:34:43.81#ibcon#read 6, iclass 16, count 0 2006.281.07:34:43.81#ibcon#end of sib2, iclass 16, count 0 2006.281.07:34:43.81#ibcon#*after write, iclass 16, count 0 2006.281.07:34:43.81#ibcon#*before return 0, iclass 16, count 0 2006.281.07:34:43.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:34:43.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:34:43.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:34:43.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:34:43.81$4f8m12a/ifd4f 2006.281.07:34:43.81$ifd4f/lo= 2006.281.07:34:43.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:34:43.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:34:43.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:34:43.81$ifd4f/patch= 2006.281.07:34:43.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:34:43.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:34:43.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:34:43.81$4f8m12a/"form=m,16.000,1:2 2006.281.07:34:43.81$4f8m12a/"tpicd 2006.281.07:34:43.81$4f8m12a/echo=off 2006.281.07:34:43.81$4f8m12a/xlog=off 2006.281.07:34:43.81:!2006.281.07:35:10 2006.281.07:34:54.14#trakl#Source acquired 2006.281.07:34:55.14#flagr#flagr/antenna,acquired 2006.281.07:35:10.00:preob 2006.281.07:35:11.14/onsource/TRACKING 2006.281.07:35:11.14:!2006.281.07:35:20 2006.281.07:35:20.00:data_valid=on 2006.281.07:35:20.00:midob 2006.281.07:35:20.14/onsource/TRACKING 2006.281.07:35:20.14/wx/21.35,1001.1,50 2006.281.07:35:20.31/cable/+6.4874E-03 2006.281.07:35:21.40/va/01,07,usb,yes,32,34 2006.281.07:35:21.40/va/02,06,usb,yes,30,31 2006.281.07:35:21.40/va/03,06,usb,yes,28,28 2006.281.07:35:21.40/va/04,06,usb,yes,31,33 2006.281.07:35:21.40/va/05,07,usb,yes,28,30 2006.281.07:35:21.40/va/06,06,usb,yes,28,27 2006.281.07:35:21.40/va/07,06,usb,yes,28,28 2006.281.07:35:21.40/va/08,06,usb,yes,30,29 2006.281.07:35:21.63/valo/01,532.99,yes,locked 2006.281.07:35:21.63/valo/02,572.99,yes,locked 2006.281.07:35:21.63/valo/03,672.99,yes,locked 2006.281.07:35:21.63/valo/04,832.99,yes,locked 2006.281.07:35:21.63/valo/05,652.99,yes,locked 2006.281.07:35:21.63/valo/06,772.99,yes,locked 2006.281.07:35:21.63/valo/07,832.99,yes,locked 2006.281.07:35:21.63/valo/08,852.99,yes,locked 2006.281.07:35:22.72/vb/01,04,usb,yes,30,29 2006.281.07:35:22.72/vb/02,05,usb,yes,28,29 2006.281.07:35:22.72/vb/03,04,usb,yes,28,32 2006.281.07:35:22.72/vb/04,04,usb,yes,29,29 2006.281.07:35:22.72/vb/05,04,usb,yes,27,31 2006.281.07:35:22.72/vb/06,04,usb,yes,28,31 2006.281.07:35:22.72/vb/07,04,usb,yes,30,30 2006.281.07:35:22.72/vb/08,04,usb,yes,28,31 2006.281.07:35:22.95/vblo/01,632.99,yes,locked 2006.281.07:35:22.95/vblo/02,640.99,yes,locked 2006.281.07:35:22.95/vblo/03,656.99,yes,locked 2006.281.07:35:22.95/vblo/04,712.99,yes,locked 2006.281.07:35:22.95/vblo/05,744.99,yes,locked 2006.281.07:35:22.95/vblo/06,752.99,yes,locked 2006.281.07:35:22.95/vblo/07,734.99,yes,locked 2006.281.07:35:22.95/vblo/08,744.99,yes,locked 2006.281.07:35:23.10/vabw/8 2006.281.07:35:23.25/vbbw/8 2006.281.07:35:23.34/xfe/off,on,12.0 2006.281.07:35:23.71/ifatt/23,28,28,28 2006.281.07:35:24.08/fmout-gps/S +3.10E-07 2006.281.07:35:24.09:!2006.281.07:36:20 2006.281.07:35:49.14#trakl#Off source 2006.281.07:35:49.14?ERROR st -7 Antenna off-source! 2006.281.07:35:49.14#trakl#az 359.758 el 47.609 azerr*cos(el) 0.0011 elerr 0.0161 2006.281.07:35:49.14#flagr#flagr/antenna,off-source 2006.281.07:35:56.14#trakl#Source re-acquired 2006.281.07:35:58.14#flagr#flagr/antenna,re-acquired 2006.281.07:36:03.14#trakl#Off source 2006.281.07:36:03.14?ERROR st -7 Antenna off-source! 2006.281.07:36:03.14#trakl#az 359.741 el 47.609 azerr*cos(el) -0.0007 elerr -0.0187 2006.281.07:36:04.14#flagr#flagr/antenna,off-source 2006.281.07:36:18.14#trakl#Source re-acquired 2006.281.07:36:19.14#flagr#flagr/antenna,re-acquired 2006.281.07:36:20.00:data_valid=off 2006.281.07:36:20.00:postob 2006.281.07:36:20.23/cable/+6.4852E-03 2006.281.07:36:20.23/wx/21.31,1001.1,50 2006.281.07:36:21.08/fmout-gps/S +3.09E-07 2006.281.07:36:21.08:scan_name=281-0737,k06281,60 2006.281.07:36:21.08:source=1739+522,174036.98,521143.4,2000.0,ccw 2006.281.07:36:21.14#flagr#flagr/antenna,new-source 2006.281.07:36:22.14:checkk5 2006.281.07:36:22.60/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:36:23.03/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:36:23.46/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:36:23.89/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:36:24.32/chk_obsdata//k5ts1/T2810735??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:36:24.72/chk_obsdata//k5ts2/T2810735??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:36:25.15/chk_obsdata//k5ts3/T2810735??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:36:25.60/chk_obsdata//k5ts4/T2810735??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:36:26.62/k5log//k5ts1_log_newline 2006.281.07:36:27.40/k5log//k5ts2_log_newline 2006.281.07:36:28.39/k5log//k5ts3_log_newline 2006.281.07:36:29.17/k5log//k5ts4_log_newline 2006.281.07:36:29.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:36:29.23:4f8m12a=1 2006.281.07:36:29.23$4f8m12a/echo=on 2006.281.07:36:29.23$4f8m12a/pcalon 2006.281.07:36:29.23$pcalon/"no phase cal control is implemented here 2006.281.07:36:29.23$4f8m12a/"tpicd=stop 2006.281.07:36:29.23$4f8m12a/vc4f8 2006.281.07:36:29.23$vc4f8/valo=1,532.99 2006.281.07:36:29.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:36:29.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:36:29.24#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:29.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:36:29.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:36:29.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:36:29.24#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:36:29.24#ibcon#first serial, iclass 27, count 0 2006.281.07:36:29.24#ibcon#enter sib2, iclass 27, count 0 2006.281.07:36:29.24#ibcon#flushed, iclass 27, count 0 2006.281.07:36:29.24#ibcon#about to write, iclass 27, count 0 2006.281.07:36:29.24#ibcon#wrote, iclass 27, count 0 2006.281.07:36:29.24#ibcon#about to read 3, iclass 27, count 0 2006.281.07:36:29.25#ibcon#read 3, iclass 27, count 0 2006.281.07:36:29.26#ibcon#about to read 4, iclass 27, count 0 2006.281.07:36:29.26#ibcon#read 4, iclass 27, count 0 2006.281.07:36:29.26#ibcon#about to read 5, iclass 27, count 0 2006.281.07:36:29.26#ibcon#read 5, iclass 27, count 0 2006.281.07:36:29.26#ibcon#about to read 6, iclass 27, count 0 2006.281.07:36:29.26#ibcon#read 6, iclass 27, count 0 2006.281.07:36:29.26#ibcon#end of sib2, iclass 27, count 0 2006.281.07:36:29.26#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:36:29.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:36:29.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:36:29.26#ibcon#*before write, iclass 27, count 0 2006.281.07:36:29.26#ibcon#enter sib2, iclass 27, count 0 2006.281.07:36:29.26#ibcon#flushed, iclass 27, count 0 2006.281.07:36:29.26#ibcon#about to write, iclass 27, count 0 2006.281.07:36:29.26#ibcon#wrote, iclass 27, count 0 2006.281.07:36:29.26#ibcon#about to read 3, iclass 27, count 0 2006.281.07:36:29.31#ibcon#read 3, iclass 27, count 0 2006.281.07:36:29.31#ibcon#about to read 4, iclass 27, count 0 2006.281.07:36:29.31#ibcon#read 4, iclass 27, count 0 2006.281.07:36:29.31#ibcon#about to read 5, iclass 27, count 0 2006.281.07:36:29.31#ibcon#read 5, iclass 27, count 0 2006.281.07:36:29.31#ibcon#about to read 6, iclass 27, count 0 2006.281.07:36:29.31#ibcon#read 6, iclass 27, count 0 2006.281.07:36:29.31#ibcon#end of sib2, iclass 27, count 0 2006.281.07:36:29.31#ibcon#*after write, iclass 27, count 0 2006.281.07:36:29.31#ibcon#*before return 0, iclass 27, count 0 2006.281.07:36:29.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:36:29.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:36:29.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:36:29.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:36:29.31$vc4f8/va=1,7 2006.281.07:36:29.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:36:29.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:36:29.31#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:29.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:36:29.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:36:29.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:36:29.31#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:36:29.31#ibcon#first serial, iclass 29, count 2 2006.281.07:36:29.31#ibcon#enter sib2, iclass 29, count 2 2006.281.07:36:29.31#ibcon#flushed, iclass 29, count 2 2006.281.07:36:29.31#ibcon#about to write, iclass 29, count 2 2006.281.07:36:29.31#ibcon#wrote, iclass 29, count 2 2006.281.07:36:29.31#ibcon#about to read 3, iclass 29, count 2 2006.281.07:36:29.33#ibcon#read 3, iclass 29, count 2 2006.281.07:36:29.33#ibcon#about to read 4, iclass 29, count 2 2006.281.07:36:29.33#ibcon#read 4, iclass 29, count 2 2006.281.07:36:29.33#ibcon#about to read 5, iclass 29, count 2 2006.281.07:36:29.33#ibcon#read 5, iclass 29, count 2 2006.281.07:36:29.33#ibcon#about to read 6, iclass 29, count 2 2006.281.07:36:29.33#ibcon#read 6, iclass 29, count 2 2006.281.07:36:29.33#ibcon#end of sib2, iclass 29, count 2 2006.281.07:36:29.33#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:36:29.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:36:29.33#ibcon#[25=AT01-07\r\n] 2006.281.07:36:29.33#ibcon#*before write, iclass 29, count 2 2006.281.07:36:29.33#ibcon#enter sib2, iclass 29, count 2 2006.281.07:36:29.33#ibcon#flushed, iclass 29, count 2 2006.281.07:36:29.33#ibcon#about to write, iclass 29, count 2 2006.281.07:36:29.33#ibcon#wrote, iclass 29, count 2 2006.281.07:36:29.33#ibcon#about to read 3, iclass 29, count 2 2006.281.07:36:29.35#ibcon#read 3, iclass 29, count 2 2006.281.07:36:29.36#ibcon#about to read 4, iclass 29, count 2 2006.281.07:36:29.36#ibcon#read 4, iclass 29, count 2 2006.281.07:36:29.36#ibcon#about to read 5, iclass 29, count 2 2006.281.07:36:29.36#ibcon#read 5, iclass 29, count 2 2006.281.07:36:29.36#ibcon#about to read 6, iclass 29, count 2 2006.281.07:36:29.36#ibcon#read 6, iclass 29, count 2 2006.281.07:36:29.36#ibcon#end of sib2, iclass 29, count 2 2006.281.07:36:29.36#ibcon#*after write, iclass 29, count 2 2006.281.07:36:29.36#ibcon#*before return 0, iclass 29, count 2 2006.281.07:36:29.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:36:29.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:36:29.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:36:29.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:29.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:36:29.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:36:29.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:36:29.48#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:36:29.48#ibcon#first serial, iclass 29, count 0 2006.281.07:36:29.48#ibcon#enter sib2, iclass 29, count 0 2006.281.07:36:29.48#ibcon#flushed, iclass 29, count 0 2006.281.07:36:29.48#ibcon#about to write, iclass 29, count 0 2006.281.07:36:29.48#ibcon#wrote, iclass 29, count 0 2006.281.07:36:29.48#ibcon#about to read 3, iclass 29, count 0 2006.281.07:36:29.50#ibcon#read 3, iclass 29, count 0 2006.281.07:36:29.50#ibcon#about to read 4, iclass 29, count 0 2006.281.07:36:29.50#ibcon#read 4, iclass 29, count 0 2006.281.07:36:29.50#ibcon#about to read 5, iclass 29, count 0 2006.281.07:36:29.50#ibcon#read 5, iclass 29, count 0 2006.281.07:36:29.50#ibcon#about to read 6, iclass 29, count 0 2006.281.07:36:29.50#ibcon#read 6, iclass 29, count 0 2006.281.07:36:29.50#ibcon#end of sib2, iclass 29, count 0 2006.281.07:36:29.50#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:36:29.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:36:29.50#ibcon#[25=USB\r\n] 2006.281.07:36:29.50#ibcon#*before write, iclass 29, count 0 2006.281.07:36:29.50#ibcon#enter sib2, iclass 29, count 0 2006.281.07:36:29.50#ibcon#flushed, iclass 29, count 0 2006.281.07:36:29.50#ibcon#about to write, iclass 29, count 0 2006.281.07:36:29.50#ibcon#wrote, iclass 29, count 0 2006.281.07:36:29.50#ibcon#about to read 3, iclass 29, count 0 2006.281.07:36:29.52#ibcon#read 3, iclass 29, count 0 2006.281.07:36:29.53#ibcon#about to read 4, iclass 29, count 0 2006.281.07:36:29.53#ibcon#read 4, iclass 29, count 0 2006.281.07:36:29.53#ibcon#about to read 5, iclass 29, count 0 2006.281.07:36:29.53#ibcon#read 5, iclass 29, count 0 2006.281.07:36:29.53#ibcon#about to read 6, iclass 29, count 0 2006.281.07:36:29.53#ibcon#read 6, iclass 29, count 0 2006.281.07:36:29.53#ibcon#end of sib2, iclass 29, count 0 2006.281.07:36:29.53#ibcon#*after write, iclass 29, count 0 2006.281.07:36:29.53#ibcon#*before return 0, iclass 29, count 0 2006.281.07:36:29.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:36:29.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:36:29.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:36:29.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:36:29.53$vc4f8/valo=2,572.99 2006.281.07:36:29.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:36:29.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:36:29.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:29.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:29.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:29.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:29.53#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:36:29.53#ibcon#first serial, iclass 31, count 0 2006.281.07:36:29.53#ibcon#enter sib2, iclass 31, count 0 2006.281.07:36:29.53#ibcon#flushed, iclass 31, count 0 2006.281.07:36:29.53#ibcon#about to write, iclass 31, count 0 2006.281.07:36:29.53#ibcon#wrote, iclass 31, count 0 2006.281.07:36:29.53#ibcon#about to read 3, iclass 31, count 0 2006.281.07:36:29.54#ibcon#read 3, iclass 31, count 0 2006.281.07:36:29.55#ibcon#about to read 4, iclass 31, count 0 2006.281.07:36:29.55#ibcon#read 4, iclass 31, count 0 2006.281.07:36:29.55#ibcon#about to read 5, iclass 31, count 0 2006.281.07:36:29.55#ibcon#read 5, iclass 31, count 0 2006.281.07:36:29.55#ibcon#about to read 6, iclass 31, count 0 2006.281.07:36:29.55#ibcon#read 6, iclass 31, count 0 2006.281.07:36:29.55#ibcon#end of sib2, iclass 31, count 0 2006.281.07:36:29.55#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:36:29.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:36:29.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:36:29.55#ibcon#*before write, iclass 31, count 0 2006.281.07:36:29.55#ibcon#enter sib2, iclass 31, count 0 2006.281.07:36:29.55#ibcon#flushed, iclass 31, count 0 2006.281.07:36:29.55#ibcon#about to write, iclass 31, count 0 2006.281.07:36:29.55#ibcon#wrote, iclass 31, count 0 2006.281.07:36:29.55#ibcon#about to read 3, iclass 31, count 0 2006.281.07:36:29.59#ibcon#read 3, iclass 31, count 0 2006.281.07:36:29.59#ibcon#about to read 4, iclass 31, count 0 2006.281.07:36:29.59#ibcon#read 4, iclass 31, count 0 2006.281.07:36:29.59#ibcon#about to read 5, iclass 31, count 0 2006.281.07:36:29.59#ibcon#read 5, iclass 31, count 0 2006.281.07:36:29.59#ibcon#about to read 6, iclass 31, count 0 2006.281.07:36:29.59#ibcon#read 6, iclass 31, count 0 2006.281.07:36:29.59#ibcon#end of sib2, iclass 31, count 0 2006.281.07:36:29.59#ibcon#*after write, iclass 31, count 0 2006.281.07:36:29.59#ibcon#*before return 0, iclass 31, count 0 2006.281.07:36:29.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:29.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:29.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:36:29.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:36:29.59$vc4f8/va=2,6 2006.281.07:36:29.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:36:29.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:36:29.59#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:29.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:29.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:29.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:29.65#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:36:29.65#ibcon#first serial, iclass 33, count 2 2006.281.07:36:29.65#ibcon#enter sib2, iclass 33, count 2 2006.281.07:36:29.65#ibcon#flushed, iclass 33, count 2 2006.281.07:36:29.65#ibcon#about to write, iclass 33, count 2 2006.281.07:36:29.65#ibcon#wrote, iclass 33, count 2 2006.281.07:36:29.65#ibcon#about to read 3, iclass 33, count 2 2006.281.07:36:29.66#ibcon#read 3, iclass 33, count 2 2006.281.07:36:29.67#ibcon#about to read 4, iclass 33, count 2 2006.281.07:36:29.67#ibcon#read 4, iclass 33, count 2 2006.281.07:36:29.67#ibcon#about to read 5, iclass 33, count 2 2006.281.07:36:29.67#ibcon#read 5, iclass 33, count 2 2006.281.07:36:29.67#ibcon#about to read 6, iclass 33, count 2 2006.281.07:36:29.67#ibcon#read 6, iclass 33, count 2 2006.281.07:36:29.67#ibcon#end of sib2, iclass 33, count 2 2006.281.07:36:29.67#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:36:29.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:36:29.67#ibcon#[25=AT02-06\r\n] 2006.281.07:36:29.67#ibcon#*before write, iclass 33, count 2 2006.281.07:36:29.67#ibcon#enter sib2, iclass 33, count 2 2006.281.07:36:29.67#ibcon#flushed, iclass 33, count 2 2006.281.07:36:29.67#ibcon#about to write, iclass 33, count 2 2006.281.07:36:29.67#ibcon#wrote, iclass 33, count 2 2006.281.07:36:29.67#ibcon#about to read 3, iclass 33, count 2 2006.281.07:36:29.70#ibcon#read 3, iclass 33, count 2 2006.281.07:36:29.70#ibcon#about to read 4, iclass 33, count 2 2006.281.07:36:29.70#ibcon#read 4, iclass 33, count 2 2006.281.07:36:29.70#ibcon#about to read 5, iclass 33, count 2 2006.281.07:36:29.70#ibcon#read 5, iclass 33, count 2 2006.281.07:36:29.70#ibcon#about to read 6, iclass 33, count 2 2006.281.07:36:29.70#ibcon#read 6, iclass 33, count 2 2006.281.07:36:29.70#ibcon#end of sib2, iclass 33, count 2 2006.281.07:36:29.70#ibcon#*after write, iclass 33, count 2 2006.281.07:36:29.70#ibcon#*before return 0, iclass 33, count 2 2006.281.07:36:29.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:29.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:29.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:36:29.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:29.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:29.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:29.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:29.82#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:36:29.82#ibcon#first serial, iclass 33, count 0 2006.281.07:36:29.82#ibcon#enter sib2, iclass 33, count 0 2006.281.07:36:29.82#ibcon#flushed, iclass 33, count 0 2006.281.07:36:29.82#ibcon#about to write, iclass 33, count 0 2006.281.07:36:29.82#ibcon#wrote, iclass 33, count 0 2006.281.07:36:29.82#ibcon#about to read 3, iclass 33, count 0 2006.281.07:36:29.84#ibcon#read 3, iclass 33, count 0 2006.281.07:36:29.84#ibcon#about to read 4, iclass 33, count 0 2006.281.07:36:29.84#ibcon#read 4, iclass 33, count 0 2006.281.07:36:29.84#ibcon#about to read 5, iclass 33, count 0 2006.281.07:36:29.84#ibcon#read 5, iclass 33, count 0 2006.281.07:36:29.84#ibcon#about to read 6, iclass 33, count 0 2006.281.07:36:29.84#ibcon#read 6, iclass 33, count 0 2006.281.07:36:29.84#ibcon#end of sib2, iclass 33, count 0 2006.281.07:36:29.84#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:36:29.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:36:29.84#ibcon#[25=USB\r\n] 2006.281.07:36:29.84#ibcon#*before write, iclass 33, count 0 2006.281.07:36:29.84#ibcon#enter sib2, iclass 33, count 0 2006.281.07:36:29.84#ibcon#flushed, iclass 33, count 0 2006.281.07:36:29.84#ibcon#about to write, iclass 33, count 0 2006.281.07:36:29.84#ibcon#wrote, iclass 33, count 0 2006.281.07:36:29.84#ibcon#about to read 3, iclass 33, count 0 2006.281.07:36:29.86#ibcon#read 3, iclass 33, count 0 2006.281.07:36:29.87#ibcon#about to read 4, iclass 33, count 0 2006.281.07:36:29.87#ibcon#read 4, iclass 33, count 0 2006.281.07:36:29.87#ibcon#about to read 5, iclass 33, count 0 2006.281.07:36:29.87#ibcon#read 5, iclass 33, count 0 2006.281.07:36:29.87#ibcon#about to read 6, iclass 33, count 0 2006.281.07:36:29.87#ibcon#read 6, iclass 33, count 0 2006.281.07:36:29.87#ibcon#end of sib2, iclass 33, count 0 2006.281.07:36:29.87#ibcon#*after write, iclass 33, count 0 2006.281.07:36:29.87#ibcon#*before return 0, iclass 33, count 0 2006.281.07:36:29.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:29.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:29.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:36:29.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:36:29.87$vc4f8/valo=3,672.99 2006.281.07:36:29.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:36:29.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:36:29.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:29.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:29.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:29.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:29.87#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:36:29.87#ibcon#first serial, iclass 35, count 0 2006.281.07:36:29.87#ibcon#enter sib2, iclass 35, count 0 2006.281.07:36:29.87#ibcon#flushed, iclass 35, count 0 2006.281.07:36:29.87#ibcon#about to write, iclass 35, count 0 2006.281.07:36:29.87#ibcon#wrote, iclass 35, count 0 2006.281.07:36:29.87#ibcon#about to read 3, iclass 35, count 0 2006.281.07:36:29.88#ibcon#read 3, iclass 35, count 0 2006.281.07:36:29.89#ibcon#about to read 4, iclass 35, count 0 2006.281.07:36:29.89#ibcon#read 4, iclass 35, count 0 2006.281.07:36:29.89#ibcon#about to read 5, iclass 35, count 0 2006.281.07:36:29.89#ibcon#read 5, iclass 35, count 0 2006.281.07:36:29.89#ibcon#about to read 6, iclass 35, count 0 2006.281.07:36:29.89#ibcon#read 6, iclass 35, count 0 2006.281.07:36:29.89#ibcon#end of sib2, iclass 35, count 0 2006.281.07:36:29.89#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:36:29.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:36:29.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:36:29.89#ibcon#*before write, iclass 35, count 0 2006.281.07:36:29.89#ibcon#enter sib2, iclass 35, count 0 2006.281.07:36:29.89#ibcon#flushed, iclass 35, count 0 2006.281.07:36:29.89#ibcon#about to write, iclass 35, count 0 2006.281.07:36:29.89#ibcon#wrote, iclass 35, count 0 2006.281.07:36:29.89#ibcon#about to read 3, iclass 35, count 0 2006.281.07:36:29.93#ibcon#read 3, iclass 35, count 0 2006.281.07:36:29.93#ibcon#about to read 4, iclass 35, count 0 2006.281.07:36:29.93#ibcon#read 4, iclass 35, count 0 2006.281.07:36:29.93#ibcon#about to read 5, iclass 35, count 0 2006.281.07:36:29.93#ibcon#read 5, iclass 35, count 0 2006.281.07:36:29.93#ibcon#about to read 6, iclass 35, count 0 2006.281.07:36:29.93#ibcon#read 6, iclass 35, count 0 2006.281.07:36:29.93#ibcon#end of sib2, iclass 35, count 0 2006.281.07:36:29.93#ibcon#*after write, iclass 35, count 0 2006.281.07:36:29.93#ibcon#*before return 0, iclass 35, count 0 2006.281.07:36:29.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:29.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:29.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:36:29.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:36:29.93$vc4f8/va=3,6 2006.281.07:36:29.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:36:29.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:36:29.93#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:29.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:29.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:29.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:29.99#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:36:29.99#ibcon#first serial, iclass 37, count 2 2006.281.07:36:29.99#ibcon#enter sib2, iclass 37, count 2 2006.281.07:36:29.99#ibcon#flushed, iclass 37, count 2 2006.281.07:36:29.99#ibcon#about to write, iclass 37, count 2 2006.281.07:36:29.99#ibcon#wrote, iclass 37, count 2 2006.281.07:36:29.99#ibcon#about to read 3, iclass 37, count 2 2006.281.07:36:30.01#ibcon#read 3, iclass 37, count 2 2006.281.07:36:30.01#ibcon#about to read 4, iclass 37, count 2 2006.281.07:36:30.01#ibcon#read 4, iclass 37, count 2 2006.281.07:36:30.01#ibcon#about to read 5, iclass 37, count 2 2006.281.07:36:30.01#ibcon#read 5, iclass 37, count 2 2006.281.07:36:30.01#ibcon#about to read 6, iclass 37, count 2 2006.281.07:36:30.01#ibcon#read 6, iclass 37, count 2 2006.281.07:36:30.01#ibcon#end of sib2, iclass 37, count 2 2006.281.07:36:30.01#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:36:30.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:36:30.01#ibcon#[25=AT03-06\r\n] 2006.281.07:36:30.01#ibcon#*before write, iclass 37, count 2 2006.281.07:36:30.01#ibcon#enter sib2, iclass 37, count 2 2006.281.07:36:30.01#ibcon#flushed, iclass 37, count 2 2006.281.07:36:30.01#ibcon#about to write, iclass 37, count 2 2006.281.07:36:30.01#ibcon#wrote, iclass 37, count 2 2006.281.07:36:30.01#ibcon#about to read 3, iclass 37, count 2 2006.281.07:36:30.03#ibcon#read 3, iclass 37, count 2 2006.281.07:36:30.04#ibcon#about to read 4, iclass 37, count 2 2006.281.07:36:30.04#ibcon#read 4, iclass 37, count 2 2006.281.07:36:30.04#ibcon#about to read 5, iclass 37, count 2 2006.281.07:36:30.04#ibcon#read 5, iclass 37, count 2 2006.281.07:36:30.04#ibcon#about to read 6, iclass 37, count 2 2006.281.07:36:30.04#ibcon#read 6, iclass 37, count 2 2006.281.07:36:30.04#ibcon#end of sib2, iclass 37, count 2 2006.281.07:36:30.04#ibcon#*after write, iclass 37, count 2 2006.281.07:36:30.04#ibcon#*before return 0, iclass 37, count 2 2006.281.07:36:30.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:30.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:30.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:36:30.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:30.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:30.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:30.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:30.16#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:36:30.16#ibcon#first serial, iclass 37, count 0 2006.281.07:36:30.16#ibcon#enter sib2, iclass 37, count 0 2006.281.07:36:30.16#ibcon#flushed, iclass 37, count 0 2006.281.07:36:30.16#ibcon#about to write, iclass 37, count 0 2006.281.07:36:30.16#ibcon#wrote, iclass 37, count 0 2006.281.07:36:30.16#ibcon#about to read 3, iclass 37, count 0 2006.281.07:36:30.17#ibcon#read 3, iclass 37, count 0 2006.281.07:36:30.18#ibcon#about to read 4, iclass 37, count 0 2006.281.07:36:30.18#ibcon#read 4, iclass 37, count 0 2006.281.07:36:30.18#ibcon#about to read 5, iclass 37, count 0 2006.281.07:36:30.18#ibcon#read 5, iclass 37, count 0 2006.281.07:36:30.18#ibcon#about to read 6, iclass 37, count 0 2006.281.07:36:30.18#ibcon#read 6, iclass 37, count 0 2006.281.07:36:30.18#ibcon#end of sib2, iclass 37, count 0 2006.281.07:36:30.18#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:36:30.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:36:30.18#ibcon#[25=USB\r\n] 2006.281.07:36:30.18#ibcon#*before write, iclass 37, count 0 2006.281.07:36:30.18#ibcon#enter sib2, iclass 37, count 0 2006.281.07:36:30.18#ibcon#flushed, iclass 37, count 0 2006.281.07:36:30.18#ibcon#about to write, iclass 37, count 0 2006.281.07:36:30.18#ibcon#wrote, iclass 37, count 0 2006.281.07:36:30.18#ibcon#about to read 3, iclass 37, count 0 2006.281.07:36:30.21#ibcon#read 3, iclass 37, count 0 2006.281.07:36:30.21#ibcon#about to read 4, iclass 37, count 0 2006.281.07:36:30.21#ibcon#read 4, iclass 37, count 0 2006.281.07:36:30.21#ibcon#about to read 5, iclass 37, count 0 2006.281.07:36:30.21#ibcon#read 5, iclass 37, count 0 2006.281.07:36:30.21#ibcon#about to read 6, iclass 37, count 0 2006.281.07:36:30.21#ibcon#read 6, iclass 37, count 0 2006.281.07:36:30.21#ibcon#end of sib2, iclass 37, count 0 2006.281.07:36:30.21#ibcon#*after write, iclass 37, count 0 2006.281.07:36:30.21#ibcon#*before return 0, iclass 37, count 0 2006.281.07:36:30.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:30.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:30.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:36:30.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:36:30.21$vc4f8/valo=4,832.99 2006.281.07:36:30.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:36:30.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:36:30.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:30.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:30.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:30.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:30.21#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:36:30.21#ibcon#first serial, iclass 39, count 0 2006.281.07:36:30.21#ibcon#enter sib2, iclass 39, count 0 2006.281.07:36:30.21#ibcon#flushed, iclass 39, count 0 2006.281.07:36:30.21#ibcon#about to write, iclass 39, count 0 2006.281.07:36:30.21#ibcon#wrote, iclass 39, count 0 2006.281.07:36:30.21#ibcon#about to read 3, iclass 39, count 0 2006.281.07:36:30.22#ibcon#read 3, iclass 39, count 0 2006.281.07:36:30.23#ibcon#about to read 4, iclass 39, count 0 2006.281.07:36:30.23#ibcon#read 4, iclass 39, count 0 2006.281.07:36:30.23#ibcon#about to read 5, iclass 39, count 0 2006.281.07:36:30.23#ibcon#read 5, iclass 39, count 0 2006.281.07:36:30.23#ibcon#about to read 6, iclass 39, count 0 2006.281.07:36:30.23#ibcon#read 6, iclass 39, count 0 2006.281.07:36:30.23#ibcon#end of sib2, iclass 39, count 0 2006.281.07:36:30.23#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:36:30.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:36:30.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:36:30.25#ibcon#*before write, iclass 39, count 0 2006.281.07:36:30.25#ibcon#enter sib2, iclass 39, count 0 2006.281.07:36:30.25#ibcon#flushed, iclass 39, count 0 2006.281.07:36:30.25#ibcon#about to write, iclass 39, count 0 2006.281.07:36:30.25#ibcon#wrote, iclass 39, count 0 2006.281.07:36:30.25#ibcon#about to read 3, iclass 39, count 0 2006.281.07:36:30.28#ibcon#read 3, iclass 39, count 0 2006.281.07:36:30.29#ibcon#about to read 4, iclass 39, count 0 2006.281.07:36:30.29#ibcon#read 4, iclass 39, count 0 2006.281.07:36:30.29#ibcon#about to read 5, iclass 39, count 0 2006.281.07:36:30.29#ibcon#read 5, iclass 39, count 0 2006.281.07:36:30.29#ibcon#about to read 6, iclass 39, count 0 2006.281.07:36:30.29#ibcon#read 6, iclass 39, count 0 2006.281.07:36:30.29#ibcon#end of sib2, iclass 39, count 0 2006.281.07:36:30.29#ibcon#*after write, iclass 39, count 0 2006.281.07:36:30.29#ibcon#*before return 0, iclass 39, count 0 2006.281.07:36:30.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:30.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:30.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:36:30.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:36:30.29$vc4f8/va=4,6 2006.281.07:36:30.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:36:30.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:36:30.29#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:30.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:30.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:30.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:30.33#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:36:30.33#ibcon#first serial, iclass 3, count 2 2006.281.07:36:30.33#ibcon#enter sib2, iclass 3, count 2 2006.281.07:36:30.33#ibcon#flushed, iclass 3, count 2 2006.281.07:36:30.33#ibcon#about to write, iclass 3, count 2 2006.281.07:36:30.33#ibcon#wrote, iclass 3, count 2 2006.281.07:36:30.33#ibcon#about to read 3, iclass 3, count 2 2006.281.07:36:30.35#ibcon#read 3, iclass 3, count 2 2006.281.07:36:30.35#ibcon#about to read 4, iclass 3, count 2 2006.281.07:36:30.35#ibcon#read 4, iclass 3, count 2 2006.281.07:36:30.35#ibcon#about to read 5, iclass 3, count 2 2006.281.07:36:30.35#ibcon#read 5, iclass 3, count 2 2006.281.07:36:30.35#ibcon#about to read 6, iclass 3, count 2 2006.281.07:36:30.35#ibcon#read 6, iclass 3, count 2 2006.281.07:36:30.35#ibcon#end of sib2, iclass 3, count 2 2006.281.07:36:30.35#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:36:30.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:36:30.35#ibcon#[25=AT04-06\r\n] 2006.281.07:36:30.35#ibcon#*before write, iclass 3, count 2 2006.281.07:36:30.35#ibcon#enter sib2, iclass 3, count 2 2006.281.07:36:30.35#ibcon#flushed, iclass 3, count 2 2006.281.07:36:30.35#ibcon#about to write, iclass 3, count 2 2006.281.07:36:30.35#ibcon#wrote, iclass 3, count 2 2006.281.07:36:30.35#ibcon#about to read 3, iclass 3, count 2 2006.281.07:36:30.37#ibcon#read 3, iclass 3, count 2 2006.281.07:36:30.38#ibcon#about to read 4, iclass 3, count 2 2006.281.07:36:30.38#ibcon#read 4, iclass 3, count 2 2006.281.07:36:30.38#ibcon#about to read 5, iclass 3, count 2 2006.281.07:36:30.38#ibcon#read 5, iclass 3, count 2 2006.281.07:36:30.38#ibcon#about to read 6, iclass 3, count 2 2006.281.07:36:30.38#ibcon#read 6, iclass 3, count 2 2006.281.07:36:30.38#ibcon#end of sib2, iclass 3, count 2 2006.281.07:36:30.38#ibcon#*after write, iclass 3, count 2 2006.281.07:36:30.38#ibcon#*before return 0, iclass 3, count 2 2006.281.07:36:30.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:30.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:30.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:36:30.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:30.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:30.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:30.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:30.50#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:36:30.50#ibcon#first serial, iclass 3, count 0 2006.281.07:36:30.50#ibcon#enter sib2, iclass 3, count 0 2006.281.07:36:30.50#ibcon#flushed, iclass 3, count 0 2006.281.07:36:30.50#ibcon#about to write, iclass 3, count 0 2006.281.07:36:30.50#ibcon#wrote, iclass 3, count 0 2006.281.07:36:30.50#ibcon#about to read 3, iclass 3, count 0 2006.281.07:36:30.51#ibcon#read 3, iclass 3, count 0 2006.281.07:36:30.52#ibcon#about to read 4, iclass 3, count 0 2006.281.07:36:30.52#ibcon#read 4, iclass 3, count 0 2006.281.07:36:30.52#ibcon#about to read 5, iclass 3, count 0 2006.281.07:36:30.52#ibcon#read 5, iclass 3, count 0 2006.281.07:36:30.52#ibcon#about to read 6, iclass 3, count 0 2006.281.07:36:30.52#ibcon#read 6, iclass 3, count 0 2006.281.07:36:30.52#ibcon#end of sib2, iclass 3, count 0 2006.281.07:36:30.52#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:36:30.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:36:30.52#ibcon#[25=USB\r\n] 2006.281.07:36:30.52#ibcon#*before write, iclass 3, count 0 2006.281.07:36:30.52#ibcon#enter sib2, iclass 3, count 0 2006.281.07:36:30.52#ibcon#flushed, iclass 3, count 0 2006.281.07:36:30.52#ibcon#about to write, iclass 3, count 0 2006.281.07:36:30.52#ibcon#wrote, iclass 3, count 0 2006.281.07:36:30.52#ibcon#about to read 3, iclass 3, count 0 2006.281.07:36:30.55#ibcon#read 3, iclass 3, count 0 2006.281.07:36:30.55#ibcon#about to read 4, iclass 3, count 0 2006.281.07:36:30.55#ibcon#read 4, iclass 3, count 0 2006.281.07:36:30.55#ibcon#about to read 5, iclass 3, count 0 2006.281.07:36:30.55#ibcon#read 5, iclass 3, count 0 2006.281.07:36:30.55#ibcon#about to read 6, iclass 3, count 0 2006.281.07:36:30.55#ibcon#read 6, iclass 3, count 0 2006.281.07:36:30.55#ibcon#end of sib2, iclass 3, count 0 2006.281.07:36:30.55#ibcon#*after write, iclass 3, count 0 2006.281.07:36:30.55#ibcon#*before return 0, iclass 3, count 0 2006.281.07:36:30.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:30.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:30.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:36:30.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:36:30.55$vc4f8/valo=5,652.99 2006.281.07:36:30.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:36:30.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:36:30.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:30.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:30.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:30.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:30.55#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:36:30.55#ibcon#first serial, iclass 5, count 0 2006.281.07:36:30.55#ibcon#enter sib2, iclass 5, count 0 2006.281.07:36:30.55#ibcon#flushed, iclass 5, count 0 2006.281.07:36:30.55#ibcon#about to write, iclass 5, count 0 2006.281.07:36:30.55#ibcon#wrote, iclass 5, count 0 2006.281.07:36:30.55#ibcon#about to read 3, iclass 5, count 0 2006.281.07:36:30.56#ibcon#read 3, iclass 5, count 0 2006.281.07:36:30.57#ibcon#about to read 4, iclass 5, count 0 2006.281.07:36:30.57#ibcon#read 4, iclass 5, count 0 2006.281.07:36:30.57#ibcon#about to read 5, iclass 5, count 0 2006.281.07:36:30.57#ibcon#read 5, iclass 5, count 0 2006.281.07:36:30.57#ibcon#about to read 6, iclass 5, count 0 2006.281.07:36:30.57#ibcon#read 6, iclass 5, count 0 2006.281.07:36:30.57#ibcon#end of sib2, iclass 5, count 0 2006.281.07:36:30.57#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:36:30.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:36:30.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:36:30.57#ibcon#*before write, iclass 5, count 0 2006.281.07:36:30.57#ibcon#enter sib2, iclass 5, count 0 2006.281.07:36:30.57#ibcon#flushed, iclass 5, count 0 2006.281.07:36:30.57#ibcon#about to write, iclass 5, count 0 2006.281.07:36:30.57#ibcon#wrote, iclass 5, count 0 2006.281.07:36:30.57#ibcon#about to read 3, iclass 5, count 0 2006.281.07:36:30.60#ibcon#read 3, iclass 5, count 0 2006.281.07:36:30.61#ibcon#about to read 4, iclass 5, count 0 2006.281.07:36:30.61#ibcon#read 4, iclass 5, count 0 2006.281.07:36:30.61#ibcon#about to read 5, iclass 5, count 0 2006.281.07:36:30.61#ibcon#read 5, iclass 5, count 0 2006.281.07:36:30.61#ibcon#about to read 6, iclass 5, count 0 2006.281.07:36:30.61#ibcon#read 6, iclass 5, count 0 2006.281.07:36:30.61#ibcon#end of sib2, iclass 5, count 0 2006.281.07:36:30.61#ibcon#*after write, iclass 5, count 0 2006.281.07:36:30.61#ibcon#*before return 0, iclass 5, count 0 2006.281.07:36:30.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:30.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:30.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:36:30.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:36:30.61$vc4f8/va=5,7 2006.281.07:36:30.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:36:30.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:36:30.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:30.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:30.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:30.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:30.67#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:36:30.67#ibcon#first serial, iclass 7, count 2 2006.281.07:36:30.67#ibcon#enter sib2, iclass 7, count 2 2006.281.07:36:30.67#ibcon#flushed, iclass 7, count 2 2006.281.07:36:30.67#ibcon#about to write, iclass 7, count 2 2006.281.07:36:30.67#ibcon#wrote, iclass 7, count 2 2006.281.07:36:30.67#ibcon#about to read 3, iclass 7, count 2 2006.281.07:36:30.69#ibcon#read 3, iclass 7, count 2 2006.281.07:36:30.69#ibcon#about to read 4, iclass 7, count 2 2006.281.07:36:30.69#ibcon#read 4, iclass 7, count 2 2006.281.07:36:30.69#ibcon#about to read 5, iclass 7, count 2 2006.281.07:36:30.69#ibcon#read 5, iclass 7, count 2 2006.281.07:36:30.69#ibcon#about to read 6, iclass 7, count 2 2006.281.07:36:30.69#ibcon#read 6, iclass 7, count 2 2006.281.07:36:30.69#ibcon#end of sib2, iclass 7, count 2 2006.281.07:36:30.69#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:36:30.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:36:30.69#ibcon#[25=AT05-07\r\n] 2006.281.07:36:30.69#ibcon#*before write, iclass 7, count 2 2006.281.07:36:30.69#ibcon#enter sib2, iclass 7, count 2 2006.281.07:36:30.69#ibcon#flushed, iclass 7, count 2 2006.281.07:36:30.69#ibcon#about to write, iclass 7, count 2 2006.281.07:36:30.69#ibcon#wrote, iclass 7, count 2 2006.281.07:36:30.69#ibcon#about to read 3, iclass 7, count 2 2006.281.07:36:30.71#ibcon#read 3, iclass 7, count 2 2006.281.07:36:30.72#ibcon#about to read 4, iclass 7, count 2 2006.281.07:36:30.72#ibcon#read 4, iclass 7, count 2 2006.281.07:36:30.72#ibcon#about to read 5, iclass 7, count 2 2006.281.07:36:30.72#ibcon#read 5, iclass 7, count 2 2006.281.07:36:30.72#ibcon#about to read 6, iclass 7, count 2 2006.281.07:36:30.72#ibcon#read 6, iclass 7, count 2 2006.281.07:36:30.72#ibcon#end of sib2, iclass 7, count 2 2006.281.07:36:30.72#ibcon#*after write, iclass 7, count 2 2006.281.07:36:30.72#ibcon#*before return 0, iclass 7, count 2 2006.281.07:36:30.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:30.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:30.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:36:30.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:30.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:30.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:30.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:30.84#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:36:30.84#ibcon#first serial, iclass 7, count 0 2006.281.07:36:30.84#ibcon#enter sib2, iclass 7, count 0 2006.281.07:36:30.84#ibcon#flushed, iclass 7, count 0 2006.281.07:36:30.84#ibcon#about to write, iclass 7, count 0 2006.281.07:36:30.84#ibcon#wrote, iclass 7, count 0 2006.281.07:36:30.84#ibcon#about to read 3, iclass 7, count 0 2006.281.07:36:30.85#ibcon#read 3, iclass 7, count 0 2006.281.07:36:30.86#ibcon#about to read 4, iclass 7, count 0 2006.281.07:36:30.86#ibcon#read 4, iclass 7, count 0 2006.281.07:36:30.86#ibcon#about to read 5, iclass 7, count 0 2006.281.07:36:30.86#ibcon#read 5, iclass 7, count 0 2006.281.07:36:30.86#ibcon#about to read 6, iclass 7, count 0 2006.281.07:36:30.86#ibcon#read 6, iclass 7, count 0 2006.281.07:36:30.86#ibcon#end of sib2, iclass 7, count 0 2006.281.07:36:30.86#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:36:30.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:36:30.86#ibcon#[25=USB\r\n] 2006.281.07:36:30.86#ibcon#*before write, iclass 7, count 0 2006.281.07:36:30.86#ibcon#enter sib2, iclass 7, count 0 2006.281.07:36:30.86#ibcon#flushed, iclass 7, count 0 2006.281.07:36:30.86#ibcon#about to write, iclass 7, count 0 2006.281.07:36:30.86#ibcon#wrote, iclass 7, count 0 2006.281.07:36:30.86#ibcon#about to read 3, iclass 7, count 0 2006.281.07:36:30.89#ibcon#read 3, iclass 7, count 0 2006.281.07:36:30.89#ibcon#about to read 4, iclass 7, count 0 2006.281.07:36:30.89#ibcon#read 4, iclass 7, count 0 2006.281.07:36:30.89#ibcon#about to read 5, iclass 7, count 0 2006.281.07:36:30.89#ibcon#read 5, iclass 7, count 0 2006.281.07:36:30.89#ibcon#about to read 6, iclass 7, count 0 2006.281.07:36:30.89#ibcon#read 6, iclass 7, count 0 2006.281.07:36:30.89#ibcon#end of sib2, iclass 7, count 0 2006.281.07:36:30.89#ibcon#*after write, iclass 7, count 0 2006.281.07:36:30.89#ibcon#*before return 0, iclass 7, count 0 2006.281.07:36:30.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:30.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:30.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:36:30.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:36:30.89$vc4f8/valo=6,772.99 2006.281.07:36:30.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:36:30.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:36:30.89#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:30.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:30.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:30.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:30.89#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:36:30.89#ibcon#first serial, iclass 11, count 0 2006.281.07:36:30.89#ibcon#enter sib2, iclass 11, count 0 2006.281.07:36:30.89#ibcon#flushed, iclass 11, count 0 2006.281.07:36:30.89#ibcon#about to write, iclass 11, count 0 2006.281.07:36:30.89#ibcon#wrote, iclass 11, count 0 2006.281.07:36:30.89#ibcon#about to read 3, iclass 11, count 0 2006.281.07:36:30.90#ibcon#read 3, iclass 11, count 0 2006.281.07:36:30.91#ibcon#about to read 4, iclass 11, count 0 2006.281.07:36:30.91#ibcon#read 4, iclass 11, count 0 2006.281.07:36:30.91#ibcon#about to read 5, iclass 11, count 0 2006.281.07:36:30.91#ibcon#read 5, iclass 11, count 0 2006.281.07:36:30.91#ibcon#about to read 6, iclass 11, count 0 2006.281.07:36:30.91#ibcon#read 6, iclass 11, count 0 2006.281.07:36:30.91#ibcon#end of sib2, iclass 11, count 0 2006.281.07:36:30.91#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:36:30.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:36:30.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:36:30.93#ibcon#*before write, iclass 11, count 0 2006.281.07:36:30.93#ibcon#enter sib2, iclass 11, count 0 2006.281.07:36:30.93#ibcon#flushed, iclass 11, count 0 2006.281.07:36:30.93#ibcon#about to write, iclass 11, count 0 2006.281.07:36:30.93#ibcon#wrote, iclass 11, count 0 2006.281.07:36:30.93#ibcon#about to read 3, iclass 11, count 0 2006.281.07:36:30.96#ibcon#read 3, iclass 11, count 0 2006.281.07:36:30.97#ibcon#about to read 4, iclass 11, count 0 2006.281.07:36:30.97#ibcon#read 4, iclass 11, count 0 2006.281.07:36:30.97#ibcon#about to read 5, iclass 11, count 0 2006.281.07:36:30.97#ibcon#read 5, iclass 11, count 0 2006.281.07:36:30.97#ibcon#about to read 6, iclass 11, count 0 2006.281.07:36:30.97#ibcon#read 6, iclass 11, count 0 2006.281.07:36:30.97#ibcon#end of sib2, iclass 11, count 0 2006.281.07:36:30.97#ibcon#*after write, iclass 11, count 0 2006.281.07:36:30.97#ibcon#*before return 0, iclass 11, count 0 2006.281.07:36:30.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:30.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:30.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:36:30.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:36:30.97$vc4f8/va=6,6 2006.281.07:36:30.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:36:30.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:36:30.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:30.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:31.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:31.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:31.01#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:36:31.01#ibcon#first serial, iclass 13, count 2 2006.281.07:36:31.01#ibcon#enter sib2, iclass 13, count 2 2006.281.07:36:31.01#ibcon#flushed, iclass 13, count 2 2006.281.07:36:31.01#ibcon#about to write, iclass 13, count 2 2006.281.07:36:31.01#ibcon#wrote, iclass 13, count 2 2006.281.07:36:31.01#ibcon#about to read 3, iclass 13, count 2 2006.281.07:36:31.02#ibcon#read 3, iclass 13, count 2 2006.281.07:36:31.03#ibcon#about to read 4, iclass 13, count 2 2006.281.07:36:31.03#ibcon#read 4, iclass 13, count 2 2006.281.07:36:31.03#ibcon#about to read 5, iclass 13, count 2 2006.281.07:36:31.03#ibcon#read 5, iclass 13, count 2 2006.281.07:36:31.03#ibcon#about to read 6, iclass 13, count 2 2006.281.07:36:31.03#ibcon#read 6, iclass 13, count 2 2006.281.07:36:31.03#ibcon#end of sib2, iclass 13, count 2 2006.281.07:36:31.03#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:36:31.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:36:31.03#ibcon#[25=AT06-06\r\n] 2006.281.07:36:31.03#ibcon#*before write, iclass 13, count 2 2006.281.07:36:31.03#ibcon#enter sib2, iclass 13, count 2 2006.281.07:36:31.03#ibcon#flushed, iclass 13, count 2 2006.281.07:36:31.03#ibcon#about to write, iclass 13, count 2 2006.281.07:36:31.03#ibcon#wrote, iclass 13, count 2 2006.281.07:36:31.03#ibcon#about to read 3, iclass 13, count 2 2006.281.07:36:31.05#ibcon#read 3, iclass 13, count 2 2006.281.07:36:31.06#ibcon#about to read 4, iclass 13, count 2 2006.281.07:36:31.06#ibcon#read 4, iclass 13, count 2 2006.281.07:36:31.06#ibcon#about to read 5, iclass 13, count 2 2006.281.07:36:31.06#ibcon#read 5, iclass 13, count 2 2006.281.07:36:31.06#ibcon#about to read 6, iclass 13, count 2 2006.281.07:36:31.06#ibcon#read 6, iclass 13, count 2 2006.281.07:36:31.06#ibcon#end of sib2, iclass 13, count 2 2006.281.07:36:31.06#ibcon#*after write, iclass 13, count 2 2006.281.07:36:31.06#ibcon#*before return 0, iclass 13, count 2 2006.281.07:36:31.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:31.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:31.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:36:31.06#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:31.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:31.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:31.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:31.18#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:36:31.18#ibcon#first serial, iclass 13, count 0 2006.281.07:36:31.18#ibcon#enter sib2, iclass 13, count 0 2006.281.07:36:31.18#ibcon#flushed, iclass 13, count 0 2006.281.07:36:31.18#ibcon#about to write, iclass 13, count 0 2006.281.07:36:31.18#ibcon#wrote, iclass 13, count 0 2006.281.07:36:31.18#ibcon#about to read 3, iclass 13, count 0 2006.281.07:36:31.20#ibcon#read 3, iclass 13, count 0 2006.281.07:36:31.20#ibcon#about to read 4, iclass 13, count 0 2006.281.07:36:31.20#ibcon#read 4, iclass 13, count 0 2006.281.07:36:31.20#ibcon#about to read 5, iclass 13, count 0 2006.281.07:36:31.20#ibcon#read 5, iclass 13, count 0 2006.281.07:36:31.20#ibcon#about to read 6, iclass 13, count 0 2006.281.07:36:31.20#ibcon#read 6, iclass 13, count 0 2006.281.07:36:31.20#ibcon#end of sib2, iclass 13, count 0 2006.281.07:36:31.20#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:36:31.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:36:31.20#ibcon#[25=USB\r\n] 2006.281.07:36:31.20#ibcon#*before write, iclass 13, count 0 2006.281.07:36:31.20#ibcon#enter sib2, iclass 13, count 0 2006.281.07:36:31.20#ibcon#flushed, iclass 13, count 0 2006.281.07:36:31.20#ibcon#about to write, iclass 13, count 0 2006.281.07:36:31.20#ibcon#wrote, iclass 13, count 0 2006.281.07:36:31.20#ibcon#about to read 3, iclass 13, count 0 2006.281.07:36:31.23#ibcon#read 3, iclass 13, count 0 2006.281.07:36:31.23#ibcon#about to read 4, iclass 13, count 0 2006.281.07:36:31.23#ibcon#read 4, iclass 13, count 0 2006.281.07:36:31.23#ibcon#about to read 5, iclass 13, count 0 2006.281.07:36:31.23#ibcon#read 5, iclass 13, count 0 2006.281.07:36:31.23#ibcon#about to read 6, iclass 13, count 0 2006.281.07:36:31.23#ibcon#read 6, iclass 13, count 0 2006.281.07:36:31.23#ibcon#end of sib2, iclass 13, count 0 2006.281.07:36:31.23#ibcon#*after write, iclass 13, count 0 2006.281.07:36:31.23#ibcon#*before return 0, iclass 13, count 0 2006.281.07:36:31.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:31.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:31.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:36:31.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:36:31.23$vc4f8/valo=7,832.99 2006.281.07:36:31.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:36:31.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:36:31.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:31.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:31.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:31.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:31.23#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:36:31.23#ibcon#first serial, iclass 15, count 0 2006.281.07:36:31.23#ibcon#enter sib2, iclass 15, count 0 2006.281.07:36:31.23#ibcon#flushed, iclass 15, count 0 2006.281.07:36:31.23#ibcon#about to write, iclass 15, count 0 2006.281.07:36:31.23#ibcon#wrote, iclass 15, count 0 2006.281.07:36:31.23#ibcon#about to read 3, iclass 15, count 0 2006.281.07:36:31.24#ibcon#read 3, iclass 15, count 0 2006.281.07:36:31.25#ibcon#about to read 4, iclass 15, count 0 2006.281.07:36:31.25#ibcon#read 4, iclass 15, count 0 2006.281.07:36:31.25#ibcon#about to read 5, iclass 15, count 0 2006.281.07:36:31.25#ibcon#read 5, iclass 15, count 0 2006.281.07:36:31.25#ibcon#about to read 6, iclass 15, count 0 2006.281.07:36:31.25#ibcon#read 6, iclass 15, count 0 2006.281.07:36:31.25#ibcon#end of sib2, iclass 15, count 0 2006.281.07:36:31.25#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:36:31.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:36:31.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:36:31.25#ibcon#*before write, iclass 15, count 0 2006.281.07:36:31.25#ibcon#enter sib2, iclass 15, count 0 2006.281.07:36:31.25#ibcon#flushed, iclass 15, count 0 2006.281.07:36:31.25#ibcon#about to write, iclass 15, count 0 2006.281.07:36:31.25#ibcon#wrote, iclass 15, count 0 2006.281.07:36:31.25#ibcon#about to read 3, iclass 15, count 0 2006.281.07:36:31.29#ibcon#read 3, iclass 15, count 0 2006.281.07:36:31.29#ibcon#about to read 4, iclass 15, count 0 2006.281.07:36:31.29#ibcon#read 4, iclass 15, count 0 2006.281.07:36:31.29#ibcon#about to read 5, iclass 15, count 0 2006.281.07:36:31.29#ibcon#read 5, iclass 15, count 0 2006.281.07:36:31.29#ibcon#about to read 6, iclass 15, count 0 2006.281.07:36:31.29#ibcon#read 6, iclass 15, count 0 2006.281.07:36:31.29#ibcon#end of sib2, iclass 15, count 0 2006.281.07:36:31.29#ibcon#*after write, iclass 15, count 0 2006.281.07:36:31.29#ibcon#*before return 0, iclass 15, count 0 2006.281.07:36:31.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:31.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:31.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:36:31.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:36:31.29$vc4f8/va=7,6 2006.281.07:36:31.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:36:31.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:31.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:31.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:31.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:31.35#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:36:31.35#ibcon#first serial, iclass 17, count 2 2006.281.07:36:31.35#ibcon#enter sib2, iclass 17, count 2 2006.281.07:36:31.35#ibcon#flushed, iclass 17, count 2 2006.281.07:36:31.35#ibcon#about to write, iclass 17, count 2 2006.281.07:36:31.35#ibcon#wrote, iclass 17, count 2 2006.281.07:36:31.35#ibcon#about to read 3, iclass 17, count 2 2006.281.07:36:31.36#ibcon#read 3, iclass 17, count 2 2006.281.07:36:31.37#ibcon#about to read 4, iclass 17, count 2 2006.281.07:36:31.37#ibcon#read 4, iclass 17, count 2 2006.281.07:36:31.37#ibcon#about to read 5, iclass 17, count 2 2006.281.07:36:31.37#ibcon#read 5, iclass 17, count 2 2006.281.07:36:31.37#ibcon#about to read 6, iclass 17, count 2 2006.281.07:36:31.37#ibcon#read 6, iclass 17, count 2 2006.281.07:36:31.37#ibcon#end of sib2, iclass 17, count 2 2006.281.07:36:31.37#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:36:31.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:36:31.37#ibcon#[25=AT07-06\r\n] 2006.281.07:36:31.37#ibcon#*before write, iclass 17, count 2 2006.281.07:36:31.37#ibcon#enter sib2, iclass 17, count 2 2006.281.07:36:31.37#ibcon#flushed, iclass 17, count 2 2006.281.07:36:31.37#ibcon#about to write, iclass 17, count 2 2006.281.07:36:31.37#ibcon#wrote, iclass 17, count 2 2006.281.07:36:31.37#ibcon#about to read 3, iclass 17, count 2 2006.281.07:36:31.40#ibcon#read 3, iclass 17, count 2 2006.281.07:36:31.40#ibcon#about to read 4, iclass 17, count 2 2006.281.07:36:31.40#ibcon#read 4, iclass 17, count 2 2006.281.07:36:31.40#ibcon#about to read 5, iclass 17, count 2 2006.281.07:36:31.40#ibcon#read 5, iclass 17, count 2 2006.281.07:36:31.40#ibcon#about to read 6, iclass 17, count 2 2006.281.07:36:31.40#ibcon#read 6, iclass 17, count 2 2006.281.07:36:31.40#ibcon#end of sib2, iclass 17, count 2 2006.281.07:36:31.40#ibcon#*after write, iclass 17, count 2 2006.281.07:36:31.40#ibcon#*before return 0, iclass 17, count 2 2006.281.07:36:31.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:31.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:31.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:36:31.40#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:31.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:36:31.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:36:31.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:36:31.52#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:36:31.52#ibcon#first serial, iclass 17, count 0 2006.281.07:36:31.52#ibcon#enter sib2, iclass 17, count 0 2006.281.07:36:31.52#ibcon#flushed, iclass 17, count 0 2006.281.07:36:31.52#ibcon#about to write, iclass 17, count 0 2006.281.07:36:31.52#ibcon#wrote, iclass 17, count 0 2006.281.07:36:31.52#ibcon#about to read 3, iclass 17, count 0 2006.281.07:36:31.54#ibcon#read 3, iclass 17, count 0 2006.281.07:36:31.54#ibcon#about to read 4, iclass 17, count 0 2006.281.07:36:31.54#ibcon#read 4, iclass 17, count 0 2006.281.07:36:31.54#ibcon#about to read 5, iclass 17, count 0 2006.281.07:36:31.54#ibcon#read 5, iclass 17, count 0 2006.281.07:36:31.54#ibcon#about to read 6, iclass 17, count 0 2006.281.07:36:31.54#ibcon#read 6, iclass 17, count 0 2006.281.07:36:31.54#ibcon#end of sib2, iclass 17, count 0 2006.281.07:36:31.54#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:36:31.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:36:31.54#ibcon#[25=USB\r\n] 2006.281.07:36:31.54#ibcon#*before write, iclass 17, count 0 2006.281.07:36:31.54#ibcon#enter sib2, iclass 17, count 0 2006.281.07:36:31.54#ibcon#flushed, iclass 17, count 0 2006.281.07:36:31.54#ibcon#about to write, iclass 17, count 0 2006.281.07:36:31.54#ibcon#wrote, iclass 17, count 0 2006.281.07:36:31.54#ibcon#about to read 3, iclass 17, count 0 2006.281.07:36:31.56#ibcon#read 3, iclass 17, count 0 2006.281.07:36:31.57#ibcon#about to read 4, iclass 17, count 0 2006.281.07:36:31.57#ibcon#read 4, iclass 17, count 0 2006.281.07:36:31.57#ibcon#about to read 5, iclass 17, count 0 2006.281.07:36:31.57#ibcon#read 5, iclass 17, count 0 2006.281.07:36:31.57#ibcon#about to read 6, iclass 17, count 0 2006.281.07:36:31.57#ibcon#read 6, iclass 17, count 0 2006.281.07:36:31.57#ibcon#end of sib2, iclass 17, count 0 2006.281.07:36:31.57#ibcon#*after write, iclass 17, count 0 2006.281.07:36:31.57#ibcon#*before return 0, iclass 17, count 0 2006.281.07:36:31.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:36:31.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:36:31.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:36:31.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:36:31.57$vc4f8/valo=8,852.99 2006.281.07:36:31.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:36:31.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:36:31.57#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:31.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:36:31.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:36:31.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:36:31.57#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:36:31.57#ibcon#first serial, iclass 19, count 0 2006.281.07:36:31.57#ibcon#enter sib2, iclass 19, count 0 2006.281.07:36:31.57#ibcon#flushed, iclass 19, count 0 2006.281.07:36:31.57#ibcon#about to write, iclass 19, count 0 2006.281.07:36:31.57#ibcon#wrote, iclass 19, count 0 2006.281.07:36:31.57#ibcon#about to read 3, iclass 19, count 0 2006.281.07:36:31.58#ibcon#read 3, iclass 19, count 0 2006.281.07:36:31.59#ibcon#about to read 4, iclass 19, count 0 2006.281.07:36:31.59#ibcon#read 4, iclass 19, count 0 2006.281.07:36:31.59#ibcon#about to read 5, iclass 19, count 0 2006.281.07:36:31.59#ibcon#read 5, iclass 19, count 0 2006.281.07:36:31.59#ibcon#about to read 6, iclass 19, count 0 2006.281.07:36:31.59#ibcon#read 6, iclass 19, count 0 2006.281.07:36:31.59#ibcon#end of sib2, iclass 19, count 0 2006.281.07:36:31.59#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:36:31.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:36:31.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:36:31.59#ibcon#*before write, iclass 19, count 0 2006.281.07:36:31.59#ibcon#enter sib2, iclass 19, count 0 2006.281.07:36:31.59#ibcon#flushed, iclass 19, count 0 2006.281.07:36:31.59#ibcon#about to write, iclass 19, count 0 2006.281.07:36:31.59#ibcon#wrote, iclass 19, count 0 2006.281.07:36:31.59#ibcon#about to read 3, iclass 19, count 0 2006.281.07:36:31.62#ibcon#read 3, iclass 19, count 0 2006.281.07:36:31.63#ibcon#about to read 4, iclass 19, count 0 2006.281.07:36:31.63#ibcon#read 4, iclass 19, count 0 2006.281.07:36:31.63#ibcon#about to read 5, iclass 19, count 0 2006.281.07:36:31.63#ibcon#read 5, iclass 19, count 0 2006.281.07:36:31.63#ibcon#about to read 6, iclass 19, count 0 2006.281.07:36:31.63#ibcon#read 6, iclass 19, count 0 2006.281.07:36:31.63#ibcon#end of sib2, iclass 19, count 0 2006.281.07:36:31.63#ibcon#*after write, iclass 19, count 0 2006.281.07:36:31.63#ibcon#*before return 0, iclass 19, count 0 2006.281.07:36:31.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:36:31.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:36:31.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:36:31.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:36:31.63$vc4f8/va=8,6 2006.281.07:36:31.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:36:31.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:36:31.64#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:31.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:36:31.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:36:31.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:36:31.69#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:36:31.69#ibcon#first serial, iclass 21, count 2 2006.281.07:36:31.69#ibcon#enter sib2, iclass 21, count 2 2006.281.07:36:31.69#ibcon#flushed, iclass 21, count 2 2006.281.07:36:31.69#ibcon#about to write, iclass 21, count 2 2006.281.07:36:31.69#ibcon#wrote, iclass 21, count 2 2006.281.07:36:31.69#ibcon#about to read 3, iclass 21, count 2 2006.281.07:36:31.70#ibcon#read 3, iclass 21, count 2 2006.281.07:36:31.71#ibcon#about to read 4, iclass 21, count 2 2006.281.07:36:31.71#ibcon#read 4, iclass 21, count 2 2006.281.07:36:31.71#ibcon#about to read 5, iclass 21, count 2 2006.281.07:36:31.71#ibcon#read 5, iclass 21, count 2 2006.281.07:36:31.71#ibcon#about to read 6, iclass 21, count 2 2006.281.07:36:31.71#ibcon#read 6, iclass 21, count 2 2006.281.07:36:31.71#ibcon#end of sib2, iclass 21, count 2 2006.281.07:36:31.71#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:36:31.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:36:31.71#ibcon#[25=AT08-06\r\n] 2006.281.07:36:31.71#ibcon#*before write, iclass 21, count 2 2006.281.07:36:31.71#ibcon#enter sib2, iclass 21, count 2 2006.281.07:36:31.71#ibcon#flushed, iclass 21, count 2 2006.281.07:36:31.71#ibcon#about to write, iclass 21, count 2 2006.281.07:36:31.71#ibcon#wrote, iclass 21, count 2 2006.281.07:36:31.71#ibcon#about to read 3, iclass 21, count 2 2006.281.07:36:31.74#ibcon#read 3, iclass 21, count 2 2006.281.07:36:31.74#ibcon#about to read 4, iclass 21, count 2 2006.281.07:36:31.74#ibcon#read 4, iclass 21, count 2 2006.281.07:36:31.74#ibcon#about to read 5, iclass 21, count 2 2006.281.07:36:31.74#ibcon#read 5, iclass 21, count 2 2006.281.07:36:31.74#ibcon#about to read 6, iclass 21, count 2 2006.281.07:36:31.74#ibcon#read 6, iclass 21, count 2 2006.281.07:36:31.74#ibcon#end of sib2, iclass 21, count 2 2006.281.07:36:31.74#ibcon#*after write, iclass 21, count 2 2006.281.07:36:31.74#ibcon#*before return 0, iclass 21, count 2 2006.281.07:36:31.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:36:31.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:36:31.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:36:31.74#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:31.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:36:31.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:36:31.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:36:31.86#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:36:31.86#ibcon#first serial, iclass 21, count 0 2006.281.07:36:31.86#ibcon#enter sib2, iclass 21, count 0 2006.281.07:36:31.86#ibcon#flushed, iclass 21, count 0 2006.281.07:36:31.86#ibcon#about to write, iclass 21, count 0 2006.281.07:36:31.86#ibcon#wrote, iclass 21, count 0 2006.281.07:36:31.86#ibcon#about to read 3, iclass 21, count 0 2006.281.07:36:31.87#ibcon#read 3, iclass 21, count 0 2006.281.07:36:31.88#ibcon#about to read 4, iclass 21, count 0 2006.281.07:36:31.88#ibcon#read 4, iclass 21, count 0 2006.281.07:36:31.88#ibcon#about to read 5, iclass 21, count 0 2006.281.07:36:31.88#ibcon#read 5, iclass 21, count 0 2006.281.07:36:31.88#ibcon#about to read 6, iclass 21, count 0 2006.281.07:36:31.88#ibcon#read 6, iclass 21, count 0 2006.281.07:36:31.88#ibcon#end of sib2, iclass 21, count 0 2006.281.07:36:31.88#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:36:31.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:36:31.88#ibcon#[25=USB\r\n] 2006.281.07:36:31.88#ibcon#*before write, iclass 21, count 0 2006.281.07:36:31.88#ibcon#enter sib2, iclass 21, count 0 2006.281.07:36:31.88#ibcon#flushed, iclass 21, count 0 2006.281.07:36:31.88#ibcon#about to write, iclass 21, count 0 2006.281.07:36:31.88#ibcon#wrote, iclass 21, count 0 2006.281.07:36:31.88#ibcon#about to read 3, iclass 21, count 0 2006.281.07:36:31.91#ibcon#read 3, iclass 21, count 0 2006.281.07:36:31.91#ibcon#about to read 4, iclass 21, count 0 2006.281.07:36:31.91#ibcon#read 4, iclass 21, count 0 2006.281.07:36:31.91#ibcon#about to read 5, iclass 21, count 0 2006.281.07:36:31.91#ibcon#read 5, iclass 21, count 0 2006.281.07:36:31.91#ibcon#about to read 6, iclass 21, count 0 2006.281.07:36:31.91#ibcon#read 6, iclass 21, count 0 2006.281.07:36:31.91#ibcon#end of sib2, iclass 21, count 0 2006.281.07:36:31.91#ibcon#*after write, iclass 21, count 0 2006.281.07:36:31.91#ibcon#*before return 0, iclass 21, count 0 2006.281.07:36:31.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:36:31.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:36:31.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:36:31.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:36:31.91$vc4f8/vblo=1,632.99 2006.281.07:36:31.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:36:31.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:36:31.91#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:31.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:36:31.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:36:31.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:36:31.91#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:36:31.91#ibcon#first serial, iclass 23, count 0 2006.281.07:36:31.91#ibcon#enter sib2, iclass 23, count 0 2006.281.07:36:31.91#ibcon#flushed, iclass 23, count 0 2006.281.07:36:31.91#ibcon#about to write, iclass 23, count 0 2006.281.07:36:31.91#ibcon#wrote, iclass 23, count 0 2006.281.07:36:31.91#ibcon#about to read 3, iclass 23, count 0 2006.281.07:36:31.93#ibcon#read 3, iclass 23, count 0 2006.281.07:36:31.93#ibcon#about to read 4, iclass 23, count 0 2006.281.07:36:31.93#ibcon#read 4, iclass 23, count 0 2006.281.07:36:31.93#ibcon#about to read 5, iclass 23, count 0 2006.281.07:36:31.93#ibcon#read 5, iclass 23, count 0 2006.281.07:36:31.93#ibcon#about to read 6, iclass 23, count 0 2006.281.07:36:31.93#ibcon#read 6, iclass 23, count 0 2006.281.07:36:31.93#ibcon#end of sib2, iclass 23, count 0 2006.281.07:36:31.93#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:36:31.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:36:31.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:36:31.93#ibcon#*before write, iclass 23, count 0 2006.281.07:36:31.93#ibcon#enter sib2, iclass 23, count 0 2006.281.07:36:31.93#ibcon#flushed, iclass 23, count 0 2006.281.07:36:31.93#ibcon#about to write, iclass 23, count 0 2006.281.07:36:31.93#ibcon#wrote, iclass 23, count 0 2006.281.07:36:31.93#ibcon#about to read 3, iclass 23, count 0 2006.281.07:36:31.96#ibcon#read 3, iclass 23, count 0 2006.281.07:36:31.97#ibcon#about to read 4, iclass 23, count 0 2006.281.07:36:31.97#ibcon#read 4, iclass 23, count 0 2006.281.07:36:31.97#ibcon#about to read 5, iclass 23, count 0 2006.281.07:36:31.97#ibcon#read 5, iclass 23, count 0 2006.281.07:36:31.97#ibcon#about to read 6, iclass 23, count 0 2006.281.07:36:31.97#ibcon#read 6, iclass 23, count 0 2006.281.07:36:31.97#ibcon#end of sib2, iclass 23, count 0 2006.281.07:36:31.97#ibcon#*after write, iclass 23, count 0 2006.281.07:36:31.97#ibcon#*before return 0, iclass 23, count 0 2006.281.07:36:31.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:36:31.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:36:31.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:36:31.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:36:31.97$vc4f8/vb=1,4 2006.281.07:36:31.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:36:31.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:36:31.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:31.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:36:31.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:36:31.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:36:31.97#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:36:31.97#ibcon#first serial, iclass 25, count 2 2006.281.07:36:31.97#ibcon#enter sib2, iclass 25, count 2 2006.281.07:36:31.97#ibcon#flushed, iclass 25, count 2 2006.281.07:36:31.97#ibcon#about to write, iclass 25, count 2 2006.281.07:36:31.97#ibcon#wrote, iclass 25, count 2 2006.281.07:36:31.97#ibcon#about to read 3, iclass 25, count 2 2006.281.07:36:31.98#ibcon#read 3, iclass 25, count 2 2006.281.07:36:31.99#ibcon#about to read 4, iclass 25, count 2 2006.281.07:36:31.99#ibcon#read 4, iclass 25, count 2 2006.281.07:36:31.99#ibcon#about to read 5, iclass 25, count 2 2006.281.07:36:31.99#ibcon#read 5, iclass 25, count 2 2006.281.07:36:31.99#ibcon#about to read 6, iclass 25, count 2 2006.281.07:36:31.99#ibcon#read 6, iclass 25, count 2 2006.281.07:36:31.99#ibcon#end of sib2, iclass 25, count 2 2006.281.07:36:31.99#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:36:31.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:36:31.99#ibcon#[27=AT01-04\r\n] 2006.281.07:36:31.99#ibcon#*before write, iclass 25, count 2 2006.281.07:36:31.99#ibcon#enter sib2, iclass 25, count 2 2006.281.07:36:31.99#ibcon#flushed, iclass 25, count 2 2006.281.07:36:31.99#ibcon#about to write, iclass 25, count 2 2006.281.07:36:31.99#ibcon#wrote, iclass 25, count 2 2006.281.07:36:31.99#ibcon#about to read 3, iclass 25, count 2 2006.281.07:36:32.02#ibcon#read 3, iclass 25, count 2 2006.281.07:36:32.02#ibcon#about to read 4, iclass 25, count 2 2006.281.07:36:32.02#ibcon#read 4, iclass 25, count 2 2006.281.07:36:32.02#ibcon#about to read 5, iclass 25, count 2 2006.281.07:36:32.02#ibcon#read 5, iclass 25, count 2 2006.281.07:36:32.02#ibcon#about to read 6, iclass 25, count 2 2006.281.07:36:32.02#ibcon#read 6, iclass 25, count 2 2006.281.07:36:32.02#ibcon#end of sib2, iclass 25, count 2 2006.281.07:36:32.02#ibcon#*after write, iclass 25, count 2 2006.281.07:36:32.02#ibcon#*before return 0, iclass 25, count 2 2006.281.07:36:32.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:36:32.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:36:32.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:36:32.02#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:32.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:36:32.06#abcon#<5=/12 2.410.2 21.30 491001.2\r\n> 2006.281.07:36:32.07#abcon#{5=INTERFACE CLEAR} 2006.281.07:36:32.14#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:36:32.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:36:32.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:36:32.14#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:36:32.14#ibcon#first serial, iclass 25, count 0 2006.281.07:36:32.14#ibcon#enter sib2, iclass 25, count 0 2006.281.07:36:32.14#ibcon#flushed, iclass 25, count 0 2006.281.07:36:32.14#ibcon#about to write, iclass 25, count 0 2006.281.07:36:32.14#ibcon#wrote, iclass 25, count 0 2006.281.07:36:32.14#ibcon#about to read 3, iclass 25, count 0 2006.281.07:36:32.15#ibcon#read 3, iclass 25, count 0 2006.281.07:36:32.16#ibcon#about to read 4, iclass 25, count 0 2006.281.07:36:32.16#ibcon#read 4, iclass 25, count 0 2006.281.07:36:32.16#ibcon#about to read 5, iclass 25, count 0 2006.281.07:36:32.16#ibcon#read 5, iclass 25, count 0 2006.281.07:36:32.16#ibcon#about to read 6, iclass 25, count 0 2006.281.07:36:32.16#ibcon#read 6, iclass 25, count 0 2006.281.07:36:32.16#ibcon#end of sib2, iclass 25, count 0 2006.281.07:36:32.16#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:36:32.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:36:32.16#ibcon#[27=USB\r\n] 2006.281.07:36:32.16#ibcon#*before write, iclass 25, count 0 2006.281.07:36:32.16#ibcon#enter sib2, iclass 25, count 0 2006.281.07:36:32.16#ibcon#flushed, iclass 25, count 0 2006.281.07:36:32.16#ibcon#about to write, iclass 25, count 0 2006.281.07:36:32.16#ibcon#wrote, iclass 25, count 0 2006.281.07:36:32.16#ibcon#about to read 3, iclass 25, count 0 2006.281.07:36:32.19#ibcon#read 3, iclass 25, count 0 2006.281.07:36:32.19#ibcon#about to read 4, iclass 25, count 0 2006.281.07:36:32.19#ibcon#read 4, iclass 25, count 0 2006.281.07:36:32.19#ibcon#about to read 5, iclass 25, count 0 2006.281.07:36:32.19#ibcon#read 5, iclass 25, count 0 2006.281.07:36:32.19#ibcon#about to read 6, iclass 25, count 0 2006.281.07:36:32.19#ibcon#read 6, iclass 25, count 0 2006.281.07:36:32.19#ibcon#end of sib2, iclass 25, count 0 2006.281.07:36:32.19#ibcon#*after write, iclass 25, count 0 2006.281.07:36:32.19#ibcon#*before return 0, iclass 25, count 0 2006.281.07:36:32.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:36:32.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:36:32.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:36:32.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:36:32.19$vc4f8/vblo=2,640.99 2006.281.07:36:32.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:36:32.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:36:32.19#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:32.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:32.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:32.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:32.19#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:36:32.19#ibcon#first serial, iclass 31, count 0 2006.281.07:36:32.19#ibcon#enter sib2, iclass 31, count 0 2006.281.07:36:32.19#ibcon#flushed, iclass 31, count 0 2006.281.07:36:32.19#ibcon#about to write, iclass 31, count 0 2006.281.07:36:32.19#ibcon#wrote, iclass 31, count 0 2006.281.07:36:32.19#ibcon#about to read 3, iclass 31, count 0 2006.281.07:36:32.21#ibcon#read 3, iclass 31, count 0 2006.281.07:36:32.21#ibcon#about to read 4, iclass 31, count 0 2006.281.07:36:32.21#ibcon#read 4, iclass 31, count 0 2006.281.07:36:32.21#ibcon#about to read 5, iclass 31, count 0 2006.281.07:36:32.21#ibcon#read 5, iclass 31, count 0 2006.281.07:36:32.21#ibcon#about to read 6, iclass 31, count 0 2006.281.07:36:32.21#ibcon#read 6, iclass 31, count 0 2006.281.07:36:32.21#ibcon#end of sib2, iclass 31, count 0 2006.281.07:36:32.21#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:36:32.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:36:32.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:36:32.21#ibcon#*before write, iclass 31, count 0 2006.281.07:36:32.21#ibcon#enter sib2, iclass 31, count 0 2006.281.07:36:32.21#ibcon#flushed, iclass 31, count 0 2006.281.07:36:32.21#ibcon#about to write, iclass 31, count 0 2006.281.07:36:32.21#ibcon#wrote, iclass 31, count 0 2006.281.07:36:32.21#ibcon#about to read 3, iclass 31, count 0 2006.281.07:36:32.26#ibcon#read 3, iclass 31, count 0 2006.281.07:36:32.26#ibcon#about to read 4, iclass 31, count 0 2006.281.07:36:32.26#ibcon#read 4, iclass 31, count 0 2006.281.07:36:32.26#ibcon#about to read 5, iclass 31, count 0 2006.281.07:36:32.26#ibcon#read 5, iclass 31, count 0 2006.281.07:36:32.26#ibcon#about to read 6, iclass 31, count 0 2006.281.07:36:32.26#ibcon#read 6, iclass 31, count 0 2006.281.07:36:32.26#ibcon#end of sib2, iclass 31, count 0 2006.281.07:36:32.26#ibcon#*after write, iclass 31, count 0 2006.281.07:36:32.26#ibcon#*before return 0, iclass 31, count 0 2006.281.07:36:32.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:32.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:36:32.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:36:32.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:36:32.26$vc4f8/vb=2,5 2006.281.07:36:32.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:36:32.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:36:32.26#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:32.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:32.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:32.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:32.31#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:36:32.31#ibcon#first serial, iclass 33, count 2 2006.281.07:36:32.31#ibcon#enter sib2, iclass 33, count 2 2006.281.07:36:32.31#ibcon#flushed, iclass 33, count 2 2006.281.07:36:32.31#ibcon#about to write, iclass 33, count 2 2006.281.07:36:32.31#ibcon#wrote, iclass 33, count 2 2006.281.07:36:32.31#ibcon#about to read 3, iclass 33, count 2 2006.281.07:36:32.33#ibcon#read 3, iclass 33, count 2 2006.281.07:36:32.33#ibcon#about to read 4, iclass 33, count 2 2006.281.07:36:32.33#ibcon#read 4, iclass 33, count 2 2006.281.07:36:32.33#ibcon#about to read 5, iclass 33, count 2 2006.281.07:36:32.33#ibcon#read 5, iclass 33, count 2 2006.281.07:36:32.33#ibcon#about to read 6, iclass 33, count 2 2006.281.07:36:32.33#ibcon#read 6, iclass 33, count 2 2006.281.07:36:32.33#ibcon#end of sib2, iclass 33, count 2 2006.281.07:36:32.33#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:36:32.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:36:32.33#ibcon#[27=AT02-05\r\n] 2006.281.07:36:32.33#ibcon#*before write, iclass 33, count 2 2006.281.07:36:32.33#ibcon#enter sib2, iclass 33, count 2 2006.281.07:36:32.33#ibcon#flushed, iclass 33, count 2 2006.281.07:36:32.33#ibcon#about to write, iclass 33, count 2 2006.281.07:36:32.33#ibcon#wrote, iclass 33, count 2 2006.281.07:36:32.33#ibcon#about to read 3, iclass 33, count 2 2006.281.07:36:32.36#ibcon#read 3, iclass 33, count 2 2006.281.07:36:32.36#ibcon#about to read 4, iclass 33, count 2 2006.281.07:36:32.36#ibcon#read 4, iclass 33, count 2 2006.281.07:36:32.36#ibcon#about to read 5, iclass 33, count 2 2006.281.07:36:32.36#ibcon#read 5, iclass 33, count 2 2006.281.07:36:32.36#ibcon#about to read 6, iclass 33, count 2 2006.281.07:36:32.36#ibcon#read 6, iclass 33, count 2 2006.281.07:36:32.36#ibcon#end of sib2, iclass 33, count 2 2006.281.07:36:32.36#ibcon#*after write, iclass 33, count 2 2006.281.07:36:32.36#ibcon#*before return 0, iclass 33, count 2 2006.281.07:36:32.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:32.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:36:32.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:36:32.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:32.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:32.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:32.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:32.48#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:36:32.48#ibcon#first serial, iclass 33, count 0 2006.281.07:36:32.48#ibcon#enter sib2, iclass 33, count 0 2006.281.07:36:32.48#ibcon#flushed, iclass 33, count 0 2006.281.07:36:32.48#ibcon#about to write, iclass 33, count 0 2006.281.07:36:32.48#ibcon#wrote, iclass 33, count 0 2006.281.07:36:32.48#ibcon#about to read 3, iclass 33, count 0 2006.281.07:36:32.49#ibcon#read 3, iclass 33, count 0 2006.281.07:36:32.50#ibcon#about to read 4, iclass 33, count 0 2006.281.07:36:32.50#ibcon#read 4, iclass 33, count 0 2006.281.07:36:32.50#ibcon#about to read 5, iclass 33, count 0 2006.281.07:36:32.50#ibcon#read 5, iclass 33, count 0 2006.281.07:36:32.50#ibcon#about to read 6, iclass 33, count 0 2006.281.07:36:32.50#ibcon#read 6, iclass 33, count 0 2006.281.07:36:32.50#ibcon#end of sib2, iclass 33, count 0 2006.281.07:36:32.50#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:36:32.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:36:32.50#ibcon#[27=USB\r\n] 2006.281.07:36:32.50#ibcon#*before write, iclass 33, count 0 2006.281.07:36:32.50#ibcon#enter sib2, iclass 33, count 0 2006.281.07:36:32.50#ibcon#flushed, iclass 33, count 0 2006.281.07:36:32.50#ibcon#about to write, iclass 33, count 0 2006.281.07:36:32.50#ibcon#wrote, iclass 33, count 0 2006.281.07:36:32.50#ibcon#about to read 3, iclass 33, count 0 2006.281.07:36:32.52#ibcon#read 3, iclass 33, count 0 2006.281.07:36:32.53#ibcon#about to read 4, iclass 33, count 0 2006.281.07:36:32.53#ibcon#read 4, iclass 33, count 0 2006.281.07:36:32.53#ibcon#about to read 5, iclass 33, count 0 2006.281.07:36:32.53#ibcon#read 5, iclass 33, count 0 2006.281.07:36:32.53#ibcon#about to read 6, iclass 33, count 0 2006.281.07:36:32.53#ibcon#read 6, iclass 33, count 0 2006.281.07:36:32.53#ibcon#end of sib2, iclass 33, count 0 2006.281.07:36:32.53#ibcon#*after write, iclass 33, count 0 2006.281.07:36:32.53#ibcon#*before return 0, iclass 33, count 0 2006.281.07:36:32.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:32.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:36:32.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:36:32.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:36:32.53$vc4f8/vblo=3,656.99 2006.281.07:36:32.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:36:32.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:36:32.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:32.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:32.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:32.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:32.53#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:36:32.53#ibcon#first serial, iclass 35, count 0 2006.281.07:36:32.53#ibcon#enter sib2, iclass 35, count 0 2006.281.07:36:32.53#ibcon#flushed, iclass 35, count 0 2006.281.07:36:32.53#ibcon#about to write, iclass 35, count 0 2006.281.07:36:32.53#ibcon#wrote, iclass 35, count 0 2006.281.07:36:32.53#ibcon#about to read 3, iclass 35, count 0 2006.281.07:36:32.54#ibcon#read 3, iclass 35, count 0 2006.281.07:36:32.55#ibcon#about to read 4, iclass 35, count 0 2006.281.07:36:32.55#ibcon#read 4, iclass 35, count 0 2006.281.07:36:32.55#ibcon#about to read 5, iclass 35, count 0 2006.281.07:36:32.55#ibcon#read 5, iclass 35, count 0 2006.281.07:36:32.55#ibcon#about to read 6, iclass 35, count 0 2006.281.07:36:32.55#ibcon#read 6, iclass 35, count 0 2006.281.07:36:32.55#ibcon#end of sib2, iclass 35, count 0 2006.281.07:36:32.55#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:36:32.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:36:32.55#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:36:32.55#ibcon#*before write, iclass 35, count 0 2006.281.07:36:32.55#ibcon#enter sib2, iclass 35, count 0 2006.281.07:36:32.55#ibcon#flushed, iclass 35, count 0 2006.281.07:36:32.55#ibcon#about to write, iclass 35, count 0 2006.281.07:36:32.55#ibcon#wrote, iclass 35, count 0 2006.281.07:36:32.55#ibcon#about to read 3, iclass 35, count 0 2006.281.07:36:32.58#ibcon#read 3, iclass 35, count 0 2006.281.07:36:32.59#ibcon#about to read 4, iclass 35, count 0 2006.281.07:36:32.59#ibcon#read 4, iclass 35, count 0 2006.281.07:36:32.59#ibcon#about to read 5, iclass 35, count 0 2006.281.07:36:32.59#ibcon#read 5, iclass 35, count 0 2006.281.07:36:32.59#ibcon#about to read 6, iclass 35, count 0 2006.281.07:36:32.59#ibcon#read 6, iclass 35, count 0 2006.281.07:36:32.59#ibcon#end of sib2, iclass 35, count 0 2006.281.07:36:32.59#ibcon#*after write, iclass 35, count 0 2006.281.07:36:32.59#ibcon#*before return 0, iclass 35, count 0 2006.281.07:36:32.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:32.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:36:32.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:36:32.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:36:32.59$vc4f8/vb=3,4 2006.281.07:36:32.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:36:32.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:36:32.59#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:32.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:32.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:32.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:32.65#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:36:32.65#ibcon#first serial, iclass 37, count 2 2006.281.07:36:32.65#ibcon#enter sib2, iclass 37, count 2 2006.281.07:36:32.65#ibcon#flushed, iclass 37, count 2 2006.281.07:36:32.65#ibcon#about to write, iclass 37, count 2 2006.281.07:36:32.65#ibcon#wrote, iclass 37, count 2 2006.281.07:36:32.65#ibcon#about to read 3, iclass 37, count 2 2006.281.07:36:32.66#ibcon#read 3, iclass 37, count 2 2006.281.07:36:32.67#ibcon#about to read 4, iclass 37, count 2 2006.281.07:36:32.67#ibcon#read 4, iclass 37, count 2 2006.281.07:36:32.67#ibcon#about to read 5, iclass 37, count 2 2006.281.07:36:32.67#ibcon#read 5, iclass 37, count 2 2006.281.07:36:32.67#ibcon#about to read 6, iclass 37, count 2 2006.281.07:36:32.67#ibcon#read 6, iclass 37, count 2 2006.281.07:36:32.67#ibcon#end of sib2, iclass 37, count 2 2006.281.07:36:32.67#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:36:32.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:36:32.67#ibcon#[27=AT03-04\r\n] 2006.281.07:36:32.67#ibcon#*before write, iclass 37, count 2 2006.281.07:36:32.67#ibcon#enter sib2, iclass 37, count 2 2006.281.07:36:32.67#ibcon#flushed, iclass 37, count 2 2006.281.07:36:32.67#ibcon#about to write, iclass 37, count 2 2006.281.07:36:32.67#ibcon#wrote, iclass 37, count 2 2006.281.07:36:32.67#ibcon#about to read 3, iclass 37, count 2 2006.281.07:36:32.70#ibcon#read 3, iclass 37, count 2 2006.281.07:36:32.70#ibcon#about to read 4, iclass 37, count 2 2006.281.07:36:32.70#ibcon#read 4, iclass 37, count 2 2006.281.07:36:32.70#ibcon#about to read 5, iclass 37, count 2 2006.281.07:36:32.70#ibcon#read 5, iclass 37, count 2 2006.281.07:36:32.70#ibcon#about to read 6, iclass 37, count 2 2006.281.07:36:32.70#ibcon#read 6, iclass 37, count 2 2006.281.07:36:32.70#ibcon#end of sib2, iclass 37, count 2 2006.281.07:36:32.70#ibcon#*after write, iclass 37, count 2 2006.281.07:36:32.70#ibcon#*before return 0, iclass 37, count 2 2006.281.07:36:32.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:32.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:36:32.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:36:32.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:32.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:32.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:32.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:32.82#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:36:32.82#ibcon#first serial, iclass 37, count 0 2006.281.07:36:32.82#ibcon#enter sib2, iclass 37, count 0 2006.281.07:36:32.82#ibcon#flushed, iclass 37, count 0 2006.281.07:36:32.82#ibcon#about to write, iclass 37, count 0 2006.281.07:36:32.82#ibcon#wrote, iclass 37, count 0 2006.281.07:36:32.82#ibcon#about to read 3, iclass 37, count 0 2006.281.07:36:32.84#ibcon#read 3, iclass 37, count 0 2006.281.07:36:32.84#ibcon#about to read 4, iclass 37, count 0 2006.281.07:36:32.84#ibcon#read 4, iclass 37, count 0 2006.281.07:36:32.84#ibcon#about to read 5, iclass 37, count 0 2006.281.07:36:32.84#ibcon#read 5, iclass 37, count 0 2006.281.07:36:32.84#ibcon#about to read 6, iclass 37, count 0 2006.281.07:36:32.84#ibcon#read 6, iclass 37, count 0 2006.281.07:36:32.84#ibcon#end of sib2, iclass 37, count 0 2006.281.07:36:32.84#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:36:32.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:36:32.84#ibcon#[27=USB\r\n] 2006.281.07:36:32.84#ibcon#*before write, iclass 37, count 0 2006.281.07:36:32.84#ibcon#enter sib2, iclass 37, count 0 2006.281.07:36:32.84#ibcon#flushed, iclass 37, count 0 2006.281.07:36:32.84#ibcon#about to write, iclass 37, count 0 2006.281.07:36:32.84#ibcon#wrote, iclass 37, count 0 2006.281.07:36:32.84#ibcon#about to read 3, iclass 37, count 0 2006.281.07:36:32.86#ibcon#read 3, iclass 37, count 0 2006.281.07:36:32.87#ibcon#about to read 4, iclass 37, count 0 2006.281.07:36:32.87#ibcon#read 4, iclass 37, count 0 2006.281.07:36:32.87#ibcon#about to read 5, iclass 37, count 0 2006.281.07:36:32.87#ibcon#read 5, iclass 37, count 0 2006.281.07:36:32.87#ibcon#about to read 6, iclass 37, count 0 2006.281.07:36:32.87#ibcon#read 6, iclass 37, count 0 2006.281.07:36:32.87#ibcon#end of sib2, iclass 37, count 0 2006.281.07:36:32.87#ibcon#*after write, iclass 37, count 0 2006.281.07:36:32.87#ibcon#*before return 0, iclass 37, count 0 2006.281.07:36:32.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:32.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:36:32.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:36:32.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:36:32.87$vc4f8/vblo=4,712.99 2006.281.07:36:32.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:36:32.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:36:32.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:32.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:32.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:32.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:32.87#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:36:32.87#ibcon#first serial, iclass 39, count 0 2006.281.07:36:32.87#ibcon#enter sib2, iclass 39, count 0 2006.281.07:36:32.87#ibcon#flushed, iclass 39, count 0 2006.281.07:36:32.87#ibcon#about to write, iclass 39, count 0 2006.281.07:36:32.87#ibcon#wrote, iclass 39, count 0 2006.281.07:36:32.87#ibcon#about to read 3, iclass 39, count 0 2006.281.07:36:32.88#ibcon#read 3, iclass 39, count 0 2006.281.07:36:32.89#ibcon#about to read 4, iclass 39, count 0 2006.281.07:36:32.89#ibcon#read 4, iclass 39, count 0 2006.281.07:36:32.89#ibcon#about to read 5, iclass 39, count 0 2006.281.07:36:32.89#ibcon#read 5, iclass 39, count 0 2006.281.07:36:32.89#ibcon#about to read 6, iclass 39, count 0 2006.281.07:36:32.89#ibcon#read 6, iclass 39, count 0 2006.281.07:36:32.89#ibcon#end of sib2, iclass 39, count 0 2006.281.07:36:32.89#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:36:32.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:36:32.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:36:32.89#ibcon#*before write, iclass 39, count 0 2006.281.07:36:32.89#ibcon#enter sib2, iclass 39, count 0 2006.281.07:36:32.89#ibcon#flushed, iclass 39, count 0 2006.281.07:36:32.89#ibcon#about to write, iclass 39, count 0 2006.281.07:36:32.89#ibcon#wrote, iclass 39, count 0 2006.281.07:36:32.89#ibcon#about to read 3, iclass 39, count 0 2006.281.07:36:32.93#ibcon#read 3, iclass 39, count 0 2006.281.07:36:32.93#ibcon#about to read 4, iclass 39, count 0 2006.281.07:36:32.93#ibcon#read 4, iclass 39, count 0 2006.281.07:36:32.93#ibcon#about to read 5, iclass 39, count 0 2006.281.07:36:32.93#ibcon#read 5, iclass 39, count 0 2006.281.07:36:32.93#ibcon#about to read 6, iclass 39, count 0 2006.281.07:36:32.93#ibcon#read 6, iclass 39, count 0 2006.281.07:36:32.93#ibcon#end of sib2, iclass 39, count 0 2006.281.07:36:32.93#ibcon#*after write, iclass 39, count 0 2006.281.07:36:32.93#ibcon#*before return 0, iclass 39, count 0 2006.281.07:36:32.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:32.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:36:32.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:36:32.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:36:32.93$vc4f8/vb=4,4 2006.281.07:36:32.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:36:32.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:36:32.93#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:32.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:32.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:32.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:32.99#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:36:32.99#ibcon#first serial, iclass 3, count 2 2006.281.07:36:32.99#ibcon#enter sib2, iclass 3, count 2 2006.281.07:36:32.99#ibcon#flushed, iclass 3, count 2 2006.281.07:36:32.99#ibcon#about to write, iclass 3, count 2 2006.281.07:36:32.99#ibcon#wrote, iclass 3, count 2 2006.281.07:36:32.99#ibcon#about to read 3, iclass 3, count 2 2006.281.07:36:33.00#ibcon#read 3, iclass 3, count 2 2006.281.07:36:33.01#ibcon#about to read 4, iclass 3, count 2 2006.281.07:36:33.01#ibcon#read 4, iclass 3, count 2 2006.281.07:36:33.01#ibcon#about to read 5, iclass 3, count 2 2006.281.07:36:33.01#ibcon#read 5, iclass 3, count 2 2006.281.07:36:33.01#ibcon#about to read 6, iclass 3, count 2 2006.281.07:36:33.01#ibcon#read 6, iclass 3, count 2 2006.281.07:36:33.01#ibcon#end of sib2, iclass 3, count 2 2006.281.07:36:33.01#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:36:33.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:36:33.01#ibcon#[27=AT04-04\r\n] 2006.281.07:36:33.01#ibcon#*before write, iclass 3, count 2 2006.281.07:36:33.01#ibcon#enter sib2, iclass 3, count 2 2006.281.07:36:33.01#ibcon#flushed, iclass 3, count 2 2006.281.07:36:33.01#ibcon#about to write, iclass 3, count 2 2006.281.07:36:33.01#ibcon#wrote, iclass 3, count 2 2006.281.07:36:33.01#ibcon#about to read 3, iclass 3, count 2 2006.281.07:36:33.03#ibcon#read 3, iclass 3, count 2 2006.281.07:36:33.04#ibcon#about to read 4, iclass 3, count 2 2006.281.07:36:33.04#ibcon#read 4, iclass 3, count 2 2006.281.07:36:33.04#ibcon#about to read 5, iclass 3, count 2 2006.281.07:36:33.04#ibcon#read 5, iclass 3, count 2 2006.281.07:36:33.04#ibcon#about to read 6, iclass 3, count 2 2006.281.07:36:33.04#ibcon#read 6, iclass 3, count 2 2006.281.07:36:33.04#ibcon#end of sib2, iclass 3, count 2 2006.281.07:36:33.04#ibcon#*after write, iclass 3, count 2 2006.281.07:36:33.04#ibcon#*before return 0, iclass 3, count 2 2006.281.07:36:33.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:33.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:36:33.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:36:33.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:33.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:33.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:33.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:33.16#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:36:33.16#ibcon#first serial, iclass 3, count 0 2006.281.07:36:33.16#ibcon#enter sib2, iclass 3, count 0 2006.281.07:36:33.16#ibcon#flushed, iclass 3, count 0 2006.281.07:36:33.16#ibcon#about to write, iclass 3, count 0 2006.281.07:36:33.16#ibcon#wrote, iclass 3, count 0 2006.281.07:36:33.16#ibcon#about to read 3, iclass 3, count 0 2006.281.07:36:33.17#ibcon#read 3, iclass 3, count 0 2006.281.07:36:33.18#ibcon#about to read 4, iclass 3, count 0 2006.281.07:36:33.18#ibcon#read 4, iclass 3, count 0 2006.281.07:36:33.18#ibcon#about to read 5, iclass 3, count 0 2006.281.07:36:33.18#ibcon#read 5, iclass 3, count 0 2006.281.07:36:33.18#ibcon#about to read 6, iclass 3, count 0 2006.281.07:36:33.18#ibcon#read 6, iclass 3, count 0 2006.281.07:36:33.18#ibcon#end of sib2, iclass 3, count 0 2006.281.07:36:33.18#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:36:33.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:36:33.18#ibcon#[27=USB\r\n] 2006.281.07:36:33.18#ibcon#*before write, iclass 3, count 0 2006.281.07:36:33.18#ibcon#enter sib2, iclass 3, count 0 2006.281.07:36:33.18#ibcon#flushed, iclass 3, count 0 2006.281.07:36:33.18#ibcon#about to write, iclass 3, count 0 2006.281.07:36:33.18#ibcon#wrote, iclass 3, count 0 2006.281.07:36:33.18#ibcon#about to read 3, iclass 3, count 0 2006.281.07:36:33.21#ibcon#read 3, iclass 3, count 0 2006.281.07:36:33.21#ibcon#about to read 4, iclass 3, count 0 2006.281.07:36:33.21#ibcon#read 4, iclass 3, count 0 2006.281.07:36:33.21#ibcon#about to read 5, iclass 3, count 0 2006.281.07:36:33.21#ibcon#read 5, iclass 3, count 0 2006.281.07:36:33.21#ibcon#about to read 6, iclass 3, count 0 2006.281.07:36:33.21#ibcon#read 6, iclass 3, count 0 2006.281.07:36:33.21#ibcon#end of sib2, iclass 3, count 0 2006.281.07:36:33.21#ibcon#*after write, iclass 3, count 0 2006.281.07:36:33.21#ibcon#*before return 0, iclass 3, count 0 2006.281.07:36:33.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:33.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:36:33.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:36:33.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:36:33.21$vc4f8/vblo=5,744.99 2006.281.07:36:33.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:36:33.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:36:33.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:33.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:33.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:33.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:33.21#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:36:33.21#ibcon#first serial, iclass 5, count 0 2006.281.07:36:33.21#ibcon#enter sib2, iclass 5, count 0 2006.281.07:36:33.21#ibcon#flushed, iclass 5, count 0 2006.281.07:36:33.21#ibcon#about to write, iclass 5, count 0 2006.281.07:36:33.21#ibcon#wrote, iclass 5, count 0 2006.281.07:36:33.21#ibcon#about to read 3, iclass 5, count 0 2006.281.07:36:33.23#ibcon#read 3, iclass 5, count 0 2006.281.07:36:33.23#ibcon#about to read 4, iclass 5, count 0 2006.281.07:36:33.23#ibcon#read 4, iclass 5, count 0 2006.281.07:36:33.23#ibcon#about to read 5, iclass 5, count 0 2006.281.07:36:33.23#ibcon#read 5, iclass 5, count 0 2006.281.07:36:33.23#ibcon#about to read 6, iclass 5, count 0 2006.281.07:36:33.23#ibcon#read 6, iclass 5, count 0 2006.281.07:36:33.23#ibcon#end of sib2, iclass 5, count 0 2006.281.07:36:33.23#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:36:33.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:36:33.23#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:36:33.23#ibcon#*before write, iclass 5, count 0 2006.281.07:36:33.23#ibcon#enter sib2, iclass 5, count 0 2006.281.07:36:33.23#ibcon#flushed, iclass 5, count 0 2006.281.07:36:33.23#ibcon#about to write, iclass 5, count 0 2006.281.07:36:33.23#ibcon#wrote, iclass 5, count 0 2006.281.07:36:33.23#ibcon#about to read 3, iclass 5, count 0 2006.281.07:36:33.28#ibcon#read 3, iclass 5, count 0 2006.281.07:36:33.28#ibcon#about to read 4, iclass 5, count 0 2006.281.07:36:33.28#ibcon#read 4, iclass 5, count 0 2006.281.07:36:33.28#ibcon#about to read 5, iclass 5, count 0 2006.281.07:36:33.28#ibcon#read 5, iclass 5, count 0 2006.281.07:36:33.28#ibcon#about to read 6, iclass 5, count 0 2006.281.07:36:33.28#ibcon#read 6, iclass 5, count 0 2006.281.07:36:33.28#ibcon#end of sib2, iclass 5, count 0 2006.281.07:36:33.28#ibcon#*after write, iclass 5, count 0 2006.281.07:36:33.28#ibcon#*before return 0, iclass 5, count 0 2006.281.07:36:33.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:33.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:36:33.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:36:33.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:36:33.28$vc4f8/vb=5,4 2006.281.07:36:33.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:36:33.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:36:33.28#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:33.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:33.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:33.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:33.33#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:36:33.33#ibcon#first serial, iclass 7, count 2 2006.281.07:36:33.33#ibcon#enter sib2, iclass 7, count 2 2006.281.07:36:33.33#ibcon#flushed, iclass 7, count 2 2006.281.07:36:33.33#ibcon#about to write, iclass 7, count 2 2006.281.07:36:33.33#ibcon#wrote, iclass 7, count 2 2006.281.07:36:33.33#ibcon#about to read 3, iclass 7, count 2 2006.281.07:36:33.34#ibcon#read 3, iclass 7, count 2 2006.281.07:36:33.35#ibcon#about to read 4, iclass 7, count 2 2006.281.07:36:33.35#ibcon#read 4, iclass 7, count 2 2006.281.07:36:33.35#ibcon#about to read 5, iclass 7, count 2 2006.281.07:36:33.35#ibcon#read 5, iclass 7, count 2 2006.281.07:36:33.35#ibcon#about to read 6, iclass 7, count 2 2006.281.07:36:33.35#ibcon#read 6, iclass 7, count 2 2006.281.07:36:33.35#ibcon#end of sib2, iclass 7, count 2 2006.281.07:36:33.35#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:36:33.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:36:33.35#ibcon#[27=AT05-04\r\n] 2006.281.07:36:33.35#ibcon#*before write, iclass 7, count 2 2006.281.07:36:33.35#ibcon#enter sib2, iclass 7, count 2 2006.281.07:36:33.35#ibcon#flushed, iclass 7, count 2 2006.281.07:36:33.35#ibcon#about to write, iclass 7, count 2 2006.281.07:36:33.35#ibcon#wrote, iclass 7, count 2 2006.281.07:36:33.35#ibcon#about to read 3, iclass 7, count 2 2006.281.07:36:33.37#ibcon#read 3, iclass 7, count 2 2006.281.07:36:33.38#ibcon#about to read 4, iclass 7, count 2 2006.281.07:36:33.38#ibcon#read 4, iclass 7, count 2 2006.281.07:36:33.38#ibcon#about to read 5, iclass 7, count 2 2006.281.07:36:33.38#ibcon#read 5, iclass 7, count 2 2006.281.07:36:33.38#ibcon#about to read 6, iclass 7, count 2 2006.281.07:36:33.38#ibcon#read 6, iclass 7, count 2 2006.281.07:36:33.38#ibcon#end of sib2, iclass 7, count 2 2006.281.07:36:33.38#ibcon#*after write, iclass 7, count 2 2006.281.07:36:33.38#ibcon#*before return 0, iclass 7, count 2 2006.281.07:36:33.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:33.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:36:33.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:36:33.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:33.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:33.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:33.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:33.50#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:36:33.50#ibcon#first serial, iclass 7, count 0 2006.281.07:36:33.50#ibcon#enter sib2, iclass 7, count 0 2006.281.07:36:33.50#ibcon#flushed, iclass 7, count 0 2006.281.07:36:33.50#ibcon#about to write, iclass 7, count 0 2006.281.07:36:33.50#ibcon#wrote, iclass 7, count 0 2006.281.07:36:33.50#ibcon#about to read 3, iclass 7, count 0 2006.281.07:36:33.52#ibcon#read 3, iclass 7, count 0 2006.281.07:36:33.52#ibcon#about to read 4, iclass 7, count 0 2006.281.07:36:33.52#ibcon#read 4, iclass 7, count 0 2006.281.07:36:33.52#ibcon#about to read 5, iclass 7, count 0 2006.281.07:36:33.52#ibcon#read 5, iclass 7, count 0 2006.281.07:36:33.52#ibcon#about to read 6, iclass 7, count 0 2006.281.07:36:33.52#ibcon#read 6, iclass 7, count 0 2006.281.07:36:33.52#ibcon#end of sib2, iclass 7, count 0 2006.281.07:36:33.52#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:36:33.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:36:33.52#ibcon#[27=USB\r\n] 2006.281.07:36:33.52#ibcon#*before write, iclass 7, count 0 2006.281.07:36:33.52#ibcon#enter sib2, iclass 7, count 0 2006.281.07:36:33.52#ibcon#flushed, iclass 7, count 0 2006.281.07:36:33.52#ibcon#about to write, iclass 7, count 0 2006.281.07:36:33.52#ibcon#wrote, iclass 7, count 0 2006.281.07:36:33.52#ibcon#about to read 3, iclass 7, count 0 2006.281.07:36:33.54#ibcon#read 3, iclass 7, count 0 2006.281.07:36:33.55#ibcon#about to read 4, iclass 7, count 0 2006.281.07:36:33.55#ibcon#read 4, iclass 7, count 0 2006.281.07:36:33.55#ibcon#about to read 5, iclass 7, count 0 2006.281.07:36:33.55#ibcon#read 5, iclass 7, count 0 2006.281.07:36:33.55#ibcon#about to read 6, iclass 7, count 0 2006.281.07:36:33.55#ibcon#read 6, iclass 7, count 0 2006.281.07:36:33.55#ibcon#end of sib2, iclass 7, count 0 2006.281.07:36:33.55#ibcon#*after write, iclass 7, count 0 2006.281.07:36:33.55#ibcon#*before return 0, iclass 7, count 0 2006.281.07:36:33.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:33.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:36:33.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:36:33.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:36:33.55$vc4f8/vblo=6,752.99 2006.281.07:36:33.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:36:33.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:36:33.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:36:33.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:33.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:33.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:33.55#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:36:33.55#ibcon#first serial, iclass 11, count 0 2006.281.07:36:33.55#ibcon#enter sib2, iclass 11, count 0 2006.281.07:36:33.55#ibcon#flushed, iclass 11, count 0 2006.281.07:36:33.55#ibcon#about to write, iclass 11, count 0 2006.281.07:36:33.55#ibcon#wrote, iclass 11, count 0 2006.281.07:36:33.55#ibcon#about to read 3, iclass 11, count 0 2006.281.07:36:33.56#ibcon#read 3, iclass 11, count 0 2006.281.07:36:33.57#ibcon#about to read 4, iclass 11, count 0 2006.281.07:36:33.57#ibcon#read 4, iclass 11, count 0 2006.281.07:36:33.57#ibcon#about to read 5, iclass 11, count 0 2006.281.07:36:33.57#ibcon#read 5, iclass 11, count 0 2006.281.07:36:33.57#ibcon#about to read 6, iclass 11, count 0 2006.281.07:36:33.57#ibcon#read 6, iclass 11, count 0 2006.281.07:36:33.57#ibcon#end of sib2, iclass 11, count 0 2006.281.07:36:33.57#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:36:33.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:36:33.57#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:36:33.57#ibcon#*before write, iclass 11, count 0 2006.281.07:36:33.57#ibcon#enter sib2, iclass 11, count 0 2006.281.07:36:33.57#ibcon#flushed, iclass 11, count 0 2006.281.07:36:33.57#ibcon#about to write, iclass 11, count 0 2006.281.07:36:33.57#ibcon#wrote, iclass 11, count 0 2006.281.07:36:33.57#ibcon#about to read 3, iclass 11, count 0 2006.281.07:36:33.61#ibcon#read 3, iclass 11, count 0 2006.281.07:36:33.61#ibcon#about to read 4, iclass 11, count 0 2006.281.07:36:33.61#ibcon#read 4, iclass 11, count 0 2006.281.07:36:33.61#ibcon#about to read 5, iclass 11, count 0 2006.281.07:36:33.61#ibcon#read 5, iclass 11, count 0 2006.281.07:36:33.61#ibcon#about to read 6, iclass 11, count 0 2006.281.07:36:33.61#ibcon#read 6, iclass 11, count 0 2006.281.07:36:33.61#ibcon#end of sib2, iclass 11, count 0 2006.281.07:36:33.61#ibcon#*after write, iclass 11, count 0 2006.281.07:36:33.61#ibcon#*before return 0, iclass 11, count 0 2006.281.07:36:33.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:33.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:36:33.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:36:33.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:36:33.61$vc4f8/vb=6,4 2006.281.07:36:33.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:36:33.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:36:33.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:36:33.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:33.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:33.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:33.67#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:36:33.67#ibcon#first serial, iclass 13, count 2 2006.281.07:36:33.67#ibcon#enter sib2, iclass 13, count 2 2006.281.07:36:33.67#ibcon#flushed, iclass 13, count 2 2006.281.07:36:33.67#ibcon#about to write, iclass 13, count 2 2006.281.07:36:33.67#ibcon#wrote, iclass 13, count 2 2006.281.07:36:33.67#ibcon#about to read 3, iclass 13, count 2 2006.281.07:36:33.69#ibcon#read 3, iclass 13, count 2 2006.281.07:36:33.69#ibcon#about to read 4, iclass 13, count 2 2006.281.07:36:33.69#ibcon#read 4, iclass 13, count 2 2006.281.07:36:33.69#ibcon#about to read 5, iclass 13, count 2 2006.281.07:36:33.69#ibcon#read 5, iclass 13, count 2 2006.281.07:36:33.69#ibcon#about to read 6, iclass 13, count 2 2006.281.07:36:33.69#ibcon#read 6, iclass 13, count 2 2006.281.07:36:33.69#ibcon#end of sib2, iclass 13, count 2 2006.281.07:36:33.69#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:36:33.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:36:33.69#ibcon#[27=AT06-04\r\n] 2006.281.07:36:33.69#ibcon#*before write, iclass 13, count 2 2006.281.07:36:33.69#ibcon#enter sib2, iclass 13, count 2 2006.281.07:36:33.69#ibcon#flushed, iclass 13, count 2 2006.281.07:36:33.69#ibcon#about to write, iclass 13, count 2 2006.281.07:36:33.69#ibcon#wrote, iclass 13, count 2 2006.281.07:36:33.69#ibcon#about to read 3, iclass 13, count 2 2006.281.07:36:33.71#ibcon#read 3, iclass 13, count 2 2006.281.07:36:33.72#ibcon#about to read 4, iclass 13, count 2 2006.281.07:36:33.72#ibcon#read 4, iclass 13, count 2 2006.281.07:36:33.72#ibcon#about to read 5, iclass 13, count 2 2006.281.07:36:33.72#ibcon#read 5, iclass 13, count 2 2006.281.07:36:33.72#ibcon#about to read 6, iclass 13, count 2 2006.281.07:36:33.72#ibcon#read 6, iclass 13, count 2 2006.281.07:36:33.72#ibcon#end of sib2, iclass 13, count 2 2006.281.07:36:33.72#ibcon#*after write, iclass 13, count 2 2006.281.07:36:33.72#ibcon#*before return 0, iclass 13, count 2 2006.281.07:36:33.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:33.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:36:33.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:36:33.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:36:33.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:33.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:33.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:33.84#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:36:33.84#ibcon#first serial, iclass 13, count 0 2006.281.07:36:33.84#ibcon#enter sib2, iclass 13, count 0 2006.281.07:36:33.84#ibcon#flushed, iclass 13, count 0 2006.281.07:36:33.84#ibcon#about to write, iclass 13, count 0 2006.281.07:36:33.84#ibcon#wrote, iclass 13, count 0 2006.281.07:36:33.84#ibcon#about to read 3, iclass 13, count 0 2006.281.07:36:33.85#ibcon#read 3, iclass 13, count 0 2006.281.07:36:33.86#ibcon#about to read 4, iclass 13, count 0 2006.281.07:36:33.86#ibcon#read 4, iclass 13, count 0 2006.281.07:36:33.86#ibcon#about to read 5, iclass 13, count 0 2006.281.07:36:33.86#ibcon#read 5, iclass 13, count 0 2006.281.07:36:33.86#ibcon#about to read 6, iclass 13, count 0 2006.281.07:36:33.86#ibcon#read 6, iclass 13, count 0 2006.281.07:36:33.86#ibcon#end of sib2, iclass 13, count 0 2006.281.07:36:33.86#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:36:33.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:36:33.86#ibcon#[27=USB\r\n] 2006.281.07:36:33.86#ibcon#*before write, iclass 13, count 0 2006.281.07:36:33.86#ibcon#enter sib2, iclass 13, count 0 2006.281.07:36:33.86#ibcon#flushed, iclass 13, count 0 2006.281.07:36:33.86#ibcon#about to write, iclass 13, count 0 2006.281.07:36:33.86#ibcon#wrote, iclass 13, count 0 2006.281.07:36:33.86#ibcon#about to read 3, iclass 13, count 0 2006.281.07:36:33.89#ibcon#read 3, iclass 13, count 0 2006.281.07:36:33.89#ibcon#about to read 4, iclass 13, count 0 2006.281.07:36:33.89#ibcon#read 4, iclass 13, count 0 2006.281.07:36:33.89#ibcon#about to read 5, iclass 13, count 0 2006.281.07:36:33.89#ibcon#read 5, iclass 13, count 0 2006.281.07:36:33.89#ibcon#about to read 6, iclass 13, count 0 2006.281.07:36:33.89#ibcon#read 6, iclass 13, count 0 2006.281.07:36:33.89#ibcon#end of sib2, iclass 13, count 0 2006.281.07:36:33.89#ibcon#*after write, iclass 13, count 0 2006.281.07:36:33.89#ibcon#*before return 0, iclass 13, count 0 2006.281.07:36:33.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:33.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:36:33.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:36:33.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:36:33.89$vc4f8/vabw=wide 2006.281.07:36:33.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:36:33.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:36:33.89#ibcon#ireg 8 cls_cnt 0 2006.281.07:36:33.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:33.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:33.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:33.89#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:36:33.89#ibcon#first serial, iclass 15, count 0 2006.281.07:36:33.89#ibcon#enter sib2, iclass 15, count 0 2006.281.07:36:33.89#ibcon#flushed, iclass 15, count 0 2006.281.07:36:33.89#ibcon#about to write, iclass 15, count 0 2006.281.07:36:33.89#ibcon#wrote, iclass 15, count 0 2006.281.07:36:33.89#ibcon#about to read 3, iclass 15, count 0 2006.281.07:36:33.90#ibcon#read 3, iclass 15, count 0 2006.281.07:36:33.91#ibcon#about to read 4, iclass 15, count 0 2006.281.07:36:33.91#ibcon#read 4, iclass 15, count 0 2006.281.07:36:33.91#ibcon#about to read 5, iclass 15, count 0 2006.281.07:36:33.91#ibcon#read 5, iclass 15, count 0 2006.281.07:36:33.91#ibcon#about to read 6, iclass 15, count 0 2006.281.07:36:33.91#ibcon#read 6, iclass 15, count 0 2006.281.07:36:33.91#ibcon#end of sib2, iclass 15, count 0 2006.281.07:36:33.91#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:36:33.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:36:33.93#ibcon#[25=BW32\r\n] 2006.281.07:36:33.93#ibcon#*before write, iclass 15, count 0 2006.281.07:36:33.93#ibcon#enter sib2, iclass 15, count 0 2006.281.07:36:33.93#ibcon#flushed, iclass 15, count 0 2006.281.07:36:33.93#ibcon#about to write, iclass 15, count 0 2006.281.07:36:33.93#ibcon#wrote, iclass 15, count 0 2006.281.07:36:33.93#ibcon#about to read 3, iclass 15, count 0 2006.281.07:36:33.95#ibcon#read 3, iclass 15, count 0 2006.281.07:36:33.96#ibcon#about to read 4, iclass 15, count 0 2006.281.07:36:33.96#ibcon#read 4, iclass 15, count 0 2006.281.07:36:33.96#ibcon#about to read 5, iclass 15, count 0 2006.281.07:36:33.96#ibcon#read 5, iclass 15, count 0 2006.281.07:36:33.96#ibcon#about to read 6, iclass 15, count 0 2006.281.07:36:33.96#ibcon#read 6, iclass 15, count 0 2006.281.07:36:33.96#ibcon#end of sib2, iclass 15, count 0 2006.281.07:36:33.96#ibcon#*after write, iclass 15, count 0 2006.281.07:36:33.96#ibcon#*before return 0, iclass 15, count 0 2006.281.07:36:33.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:33.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:36:33.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:36:33.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:36:33.96$vc4f8/vbbw=wide 2006.281.07:36:33.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:36:33.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:36:33.96#ibcon#ireg 8 cls_cnt 0 2006.281.07:36:33.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:36:34.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:36:34.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:36:34.01#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:36:34.01#ibcon#first serial, iclass 17, count 0 2006.281.07:36:34.01#ibcon#enter sib2, iclass 17, count 0 2006.281.07:36:34.01#ibcon#flushed, iclass 17, count 0 2006.281.07:36:34.01#ibcon#about to write, iclass 17, count 0 2006.281.07:36:34.01#ibcon#wrote, iclass 17, count 0 2006.281.07:36:34.01#ibcon#about to read 3, iclass 17, count 0 2006.281.07:36:34.02#ibcon#read 3, iclass 17, count 0 2006.281.07:36:34.03#ibcon#about to read 4, iclass 17, count 0 2006.281.07:36:34.03#ibcon#read 4, iclass 17, count 0 2006.281.07:36:34.03#ibcon#about to read 5, iclass 17, count 0 2006.281.07:36:34.03#ibcon#read 5, iclass 17, count 0 2006.281.07:36:34.03#ibcon#about to read 6, iclass 17, count 0 2006.281.07:36:34.03#ibcon#read 6, iclass 17, count 0 2006.281.07:36:34.03#ibcon#end of sib2, iclass 17, count 0 2006.281.07:36:34.03#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:36:34.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:36:34.03#ibcon#[27=BW32\r\n] 2006.281.07:36:34.03#ibcon#*before write, iclass 17, count 0 2006.281.07:36:34.03#ibcon#enter sib2, iclass 17, count 0 2006.281.07:36:34.03#ibcon#flushed, iclass 17, count 0 2006.281.07:36:34.03#ibcon#about to write, iclass 17, count 0 2006.281.07:36:34.03#ibcon#wrote, iclass 17, count 0 2006.281.07:36:34.03#ibcon#about to read 3, iclass 17, count 0 2006.281.07:36:34.05#ibcon#read 3, iclass 17, count 0 2006.281.07:36:34.06#ibcon#about to read 4, iclass 17, count 0 2006.281.07:36:34.06#ibcon#read 4, iclass 17, count 0 2006.281.07:36:34.06#ibcon#about to read 5, iclass 17, count 0 2006.281.07:36:34.06#ibcon#read 5, iclass 17, count 0 2006.281.07:36:34.06#ibcon#about to read 6, iclass 17, count 0 2006.281.07:36:34.06#ibcon#read 6, iclass 17, count 0 2006.281.07:36:34.06#ibcon#end of sib2, iclass 17, count 0 2006.281.07:36:34.06#ibcon#*after write, iclass 17, count 0 2006.281.07:36:34.06#ibcon#*before return 0, iclass 17, count 0 2006.281.07:36:34.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:36:34.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:36:34.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:36:34.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:36:34.06$4f8m12a/ifd4f 2006.281.07:36:34.06$ifd4f/lo= 2006.281.07:36:34.06$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:36:34.06$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:36:34.06$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:36:34.06$ifd4f/patch= 2006.281.07:36:34.06$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:36:34.06$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:36:34.06$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:36:34.06$4f8m12a/"form=m,16.000,1:2 2006.281.07:36:34.06$4f8m12a/"tpicd 2006.281.07:36:34.06$4f8m12a/echo=off 2006.281.07:36:34.06$4f8m12a/xlog=off 2006.281.07:36:34.06:!2006.281.07:37:00 2006.281.07:36:43.13#trakl#Source acquired 2006.281.07:36:45.14#flagr#flagr/antenna,acquired 2006.281.07:37:00.02:preob 2006.281.07:37:01.15/onsource/TRACKING 2006.281.07:37:01.15:!2006.281.07:37:10 2006.281.07:37:02.14#trakl#Off source 2006.281.07:37:02.14?ERROR st -7 Antenna off-source! 2006.281.07:37:02.14#trakl#az 347.138 el 73.356 azerr*cos(el) 0.0005 elerr -0.0361 2006.281.07:37:02.15#flagr#flagr/antenna,off-source 2006.281.07:37:10.02:data_valid=on 2006.281.07:37:10.02:midob 2006.281.07:37:10.14#trakl#Source re-acquired 2006.281.07:37:11.15/onsource/TRACKING 2006.281.07:37:11.15/wx/21.28,1001.1,49 2006.281.07:37:11.35/cable/+6.4864E-03 2006.281.07:37:12.15#flagr#flagr/antenna,re-acquired 2006.281.07:37:12.44/va/01,07,usb,yes,32,33 2006.281.07:37:12.44/va/02,06,usb,yes,29,31 2006.281.07:37:12.44/va/03,06,usb,yes,28,28 2006.281.07:37:12.45/va/04,06,usb,yes,31,33 2006.281.07:37:12.45/va/05,07,usb,yes,28,30 2006.281.07:37:12.45/va/06,06,usb,yes,27,27 2006.281.07:37:12.45/va/07,06,usb,yes,28,27 2006.281.07:37:12.45/va/08,06,usb,yes,29,29 2006.281.07:37:12.68/valo/01,532.99,yes,locked 2006.281.07:37:12.68/valo/02,572.99,yes,locked 2006.281.07:37:12.68/valo/03,672.99,yes,locked 2006.281.07:37:12.68/valo/04,832.99,yes,locked 2006.281.07:37:12.68/valo/05,652.99,yes,locked 2006.281.07:37:12.68/valo/06,772.99,yes,locked 2006.281.07:37:12.68/valo/07,832.99,yes,locked 2006.281.07:37:12.68/valo/08,852.99,yes,locked 2006.281.07:37:13.76/vb/01,04,usb,yes,30,29 2006.281.07:37:13.76/vb/02,05,usb,yes,28,29 2006.281.07:37:13.76/vb/03,04,usb,yes,28,32 2006.281.07:37:13.76/vb/04,04,usb,yes,29,29 2006.281.07:37:13.76/vb/05,04,usb,yes,27,31 2006.281.07:37:13.76/vb/06,04,usb,yes,27,31 2006.281.07:37:13.77/vb/07,04,usb,yes,30,30 2006.281.07:37:13.77/vb/08,04,usb,yes,27,31 2006.281.07:37:13.99/vblo/01,632.99,yes,locked 2006.281.07:37:14.00/vblo/02,640.99,yes,locked 2006.281.07:37:14.00/vblo/03,656.99,yes,locked 2006.281.07:37:14.00/vblo/04,712.99,yes,locked 2006.281.07:37:14.00/vblo/05,744.99,yes,locked 2006.281.07:37:14.00/vblo/06,752.99,yes,locked 2006.281.07:37:14.00/vblo/07,734.99,yes,locked 2006.281.07:37:14.00/vblo/08,744.99,yes,locked 2006.281.07:37:14.15/vabw/8 2006.281.07:37:14.29/vbbw/8 2006.281.07:37:14.38/xfe/off,on,12.0 2006.281.07:37:14.76/ifatt/23,28,28,28 2006.281.07:37:15.07/fmout-gps/S +3.11E-07 2006.281.07:37:15.10:!2006.281.07:38:10 2006.281.07:37:32.14#trakl#Off source 2006.281.07:37:32.14?ERROR st -7 Antenna off-source! 2006.281.07:37:32.14#trakl#az 346.882 el 73.333 azerr*cos(el) 0.0005 elerr -0.0194 2006.281.07:37:34.15#flagr#flagr/antenna,off-source 2006.281.07:37:42.14#trakl#Source re-acquired 2006.281.07:37:43.14#trakl#Off source 2006.281.07:37:43.14?ERROR st -7 Antenna off-source! 2006.281.07:37:43.14#trakl#az 346.788 el 73.325 azerr*cos(el) -0.0010 elerr -0.0179 2006.281.07:37:56.14#trakl#Source re-acquired 2006.281.07:37:58.15#flagr#flagr/antenna,re-acquired 2006.281.07:38:10.02:data_valid=off 2006.281.07:38:10.02:postob 2006.281.07:38:10.11/cable/+6.4861E-03 2006.281.07:38:10.12/wx/21.24,1001.1,51 2006.281.07:38:11.07/fmout-gps/S +3.08E-07 2006.281.07:38:11.08:scan_name=281-0739,k06281,60 2006.281.07:38:11.08:source=1053+815,105811.54,811432.7,2000.0,ccw 2006.281.07:38:12.14#flagr#flagr/antenna,new-source 2006.281.07:38:12.14:checkk5 2006.281.07:38:12.75/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:38:13.15/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:38:13.60/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:38:14.29/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:38:14.83/chk_obsdata//k5ts1/T2810737??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:38:15.25/chk_obsdata//k5ts2/T2810737??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:38:15.68/chk_obsdata//k5ts3/T2810737??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:38:16.10/chk_obsdata//k5ts4/T2810737??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:38:16.98/k5log//k5ts1_log_newline 2006.281.07:38:17.68/k5log//k5ts2_log_newline 2006.281.07:38:18.58/k5log//k5ts3_log_newline 2006.281.07:38:19.37/k5log//k5ts4_log_newline 2006.281.07:38:19.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:38:19.40:4f8m12a=1 2006.281.07:38:19.40$4f8m12a/echo=on 2006.281.07:38:19.40$4f8m12a/pcalon 2006.281.07:38:19.40$pcalon/"no phase cal control is implemented here 2006.281.07:38:19.40$4f8m12a/"tpicd=stop 2006.281.07:38:19.40$4f8m12a/vc4f8 2006.281.07:38:19.40$vc4f8/valo=1,532.99 2006.281.07:38:19.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:38:19.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:38:19.40#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:19.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:19.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:19.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:19.40#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:38:19.40#ibcon#first serial, iclass 30, count 0 2006.281.07:38:19.40#ibcon#enter sib2, iclass 30, count 0 2006.281.07:38:19.40#ibcon#flushed, iclass 30, count 0 2006.281.07:38:19.40#ibcon#about to write, iclass 30, count 0 2006.281.07:38:19.40#ibcon#wrote, iclass 30, count 0 2006.281.07:38:19.40#ibcon#about to read 3, iclass 30, count 0 2006.281.07:38:19.41#ibcon#read 3, iclass 30, count 0 2006.281.07:38:19.41#ibcon#about to read 4, iclass 30, count 0 2006.281.07:38:19.41#ibcon#read 4, iclass 30, count 0 2006.281.07:38:19.41#ibcon#about to read 5, iclass 30, count 0 2006.281.07:38:19.41#ibcon#read 5, iclass 30, count 0 2006.281.07:38:19.41#ibcon#about to read 6, iclass 30, count 0 2006.281.07:38:19.41#ibcon#read 6, iclass 30, count 0 2006.281.07:38:19.41#ibcon#end of sib2, iclass 30, count 0 2006.281.07:38:19.41#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:38:19.41#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:38:19.41#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:38:19.41#ibcon#*before write, iclass 30, count 0 2006.281.07:38:19.41#ibcon#enter sib2, iclass 30, count 0 2006.281.07:38:19.41#ibcon#flushed, iclass 30, count 0 2006.281.07:38:19.41#ibcon#about to write, iclass 30, count 0 2006.281.07:38:19.41#ibcon#wrote, iclass 30, count 0 2006.281.07:38:19.41#ibcon#about to read 3, iclass 30, count 0 2006.281.07:38:19.47#ibcon#read 3, iclass 30, count 0 2006.281.07:38:19.47#ibcon#about to read 4, iclass 30, count 0 2006.281.07:38:19.47#ibcon#read 4, iclass 30, count 0 2006.281.07:38:19.47#ibcon#about to read 5, iclass 30, count 0 2006.281.07:38:19.47#ibcon#read 5, iclass 30, count 0 2006.281.07:38:19.47#ibcon#about to read 6, iclass 30, count 0 2006.281.07:38:19.47#ibcon#read 6, iclass 30, count 0 2006.281.07:38:19.47#ibcon#end of sib2, iclass 30, count 0 2006.281.07:38:19.47#ibcon#*after write, iclass 30, count 0 2006.281.07:38:19.47#ibcon#*before return 0, iclass 30, count 0 2006.281.07:38:19.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:19.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:19.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:38:19.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:38:19.47$vc4f8/va=1,7 2006.281.07:38:19.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:38:19.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:38:19.47#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:19.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:19.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:19.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:19.47#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:38:19.47#ibcon#first serial, iclass 32, count 2 2006.281.07:38:19.47#ibcon#enter sib2, iclass 32, count 2 2006.281.07:38:19.47#ibcon#flushed, iclass 32, count 2 2006.281.07:38:19.47#ibcon#about to write, iclass 32, count 2 2006.281.07:38:19.47#ibcon#wrote, iclass 32, count 2 2006.281.07:38:19.47#ibcon#about to read 3, iclass 32, count 2 2006.281.07:38:19.48#ibcon#read 3, iclass 32, count 2 2006.281.07:38:19.49#ibcon#about to read 4, iclass 32, count 2 2006.281.07:38:19.49#ibcon#read 4, iclass 32, count 2 2006.281.07:38:19.49#ibcon#about to read 5, iclass 32, count 2 2006.281.07:38:19.49#ibcon#read 5, iclass 32, count 2 2006.281.07:38:19.49#ibcon#about to read 6, iclass 32, count 2 2006.281.07:38:19.49#ibcon#read 6, iclass 32, count 2 2006.281.07:38:19.49#ibcon#end of sib2, iclass 32, count 2 2006.281.07:38:19.49#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:38:19.49#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:38:19.49#ibcon#[25=AT01-07\r\n] 2006.281.07:38:19.49#ibcon#*before write, iclass 32, count 2 2006.281.07:38:19.49#ibcon#enter sib2, iclass 32, count 2 2006.281.07:38:19.49#ibcon#flushed, iclass 32, count 2 2006.281.07:38:19.49#ibcon#about to write, iclass 32, count 2 2006.281.07:38:19.49#ibcon#wrote, iclass 32, count 2 2006.281.07:38:19.49#ibcon#about to read 3, iclass 32, count 2 2006.281.07:38:19.51#ibcon#read 3, iclass 32, count 2 2006.281.07:38:19.51#ibcon#about to read 4, iclass 32, count 2 2006.281.07:38:19.51#ibcon#read 4, iclass 32, count 2 2006.281.07:38:19.51#ibcon#about to read 5, iclass 32, count 2 2006.281.07:38:19.51#ibcon#read 5, iclass 32, count 2 2006.281.07:38:19.51#ibcon#about to read 6, iclass 32, count 2 2006.281.07:38:19.51#ibcon#read 6, iclass 32, count 2 2006.281.07:38:19.51#ibcon#end of sib2, iclass 32, count 2 2006.281.07:38:19.51#ibcon#*after write, iclass 32, count 2 2006.281.07:38:19.51#ibcon#*before return 0, iclass 32, count 2 2006.281.07:38:19.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:19.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:19.51#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:38:19.51#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:19.51#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:19.63#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:19.63#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:19.63#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:38:19.63#ibcon#first serial, iclass 32, count 0 2006.281.07:38:19.63#ibcon#enter sib2, iclass 32, count 0 2006.281.07:38:19.63#ibcon#flushed, iclass 32, count 0 2006.281.07:38:19.63#ibcon#about to write, iclass 32, count 0 2006.281.07:38:19.63#ibcon#wrote, iclass 32, count 0 2006.281.07:38:19.63#ibcon#about to read 3, iclass 32, count 0 2006.281.07:38:19.66#ibcon#read 3, iclass 32, count 0 2006.281.07:38:19.66#ibcon#about to read 4, iclass 32, count 0 2006.281.07:38:19.66#ibcon#read 4, iclass 32, count 0 2006.281.07:38:19.66#ibcon#about to read 5, iclass 32, count 0 2006.281.07:38:19.66#ibcon#read 5, iclass 32, count 0 2006.281.07:38:19.66#ibcon#about to read 6, iclass 32, count 0 2006.281.07:38:19.66#ibcon#read 6, iclass 32, count 0 2006.281.07:38:19.66#ibcon#end of sib2, iclass 32, count 0 2006.281.07:38:19.66#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:38:19.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:38:19.66#ibcon#[25=USB\r\n] 2006.281.07:38:19.66#ibcon#*before write, iclass 32, count 0 2006.281.07:38:19.66#ibcon#enter sib2, iclass 32, count 0 2006.281.07:38:19.66#ibcon#flushed, iclass 32, count 0 2006.281.07:38:19.66#ibcon#about to write, iclass 32, count 0 2006.281.07:38:19.66#ibcon#wrote, iclass 32, count 0 2006.281.07:38:19.66#ibcon#about to read 3, iclass 32, count 0 2006.281.07:38:19.68#ibcon#read 3, iclass 32, count 0 2006.281.07:38:19.68#ibcon#about to read 4, iclass 32, count 0 2006.281.07:38:19.68#ibcon#read 4, iclass 32, count 0 2006.281.07:38:19.68#ibcon#about to read 5, iclass 32, count 0 2006.281.07:38:19.68#ibcon#read 5, iclass 32, count 0 2006.281.07:38:19.68#ibcon#about to read 6, iclass 32, count 0 2006.281.07:38:19.68#ibcon#read 6, iclass 32, count 0 2006.281.07:38:19.68#ibcon#end of sib2, iclass 32, count 0 2006.281.07:38:19.68#ibcon#*after write, iclass 32, count 0 2006.281.07:38:19.68#ibcon#*before return 0, iclass 32, count 0 2006.281.07:38:19.68#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:19.68#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:19.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:38:19.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:38:19.69$vc4f8/valo=2,572.99 2006.281.07:38:19.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:38:19.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:38:19.69#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:19.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:19.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:19.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:19.69#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:38:19.69#ibcon#first serial, iclass 34, count 0 2006.281.07:38:19.69#ibcon#enter sib2, iclass 34, count 0 2006.281.07:38:19.69#ibcon#flushed, iclass 34, count 0 2006.281.07:38:19.69#ibcon#about to write, iclass 34, count 0 2006.281.07:38:19.69#ibcon#wrote, iclass 34, count 0 2006.281.07:38:19.69#ibcon#about to read 3, iclass 34, count 0 2006.281.07:38:19.71#ibcon#read 3, iclass 34, count 0 2006.281.07:38:19.71#ibcon#about to read 4, iclass 34, count 0 2006.281.07:38:19.71#ibcon#read 4, iclass 34, count 0 2006.281.07:38:19.71#ibcon#about to read 5, iclass 34, count 0 2006.281.07:38:19.71#ibcon#read 5, iclass 34, count 0 2006.281.07:38:19.71#ibcon#about to read 6, iclass 34, count 0 2006.281.07:38:19.71#ibcon#read 6, iclass 34, count 0 2006.281.07:38:19.71#ibcon#end of sib2, iclass 34, count 0 2006.281.07:38:19.71#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:38:19.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:38:19.71#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:38:19.71#ibcon#*before write, iclass 34, count 0 2006.281.07:38:19.71#ibcon#enter sib2, iclass 34, count 0 2006.281.07:38:19.71#ibcon#flushed, iclass 34, count 0 2006.281.07:38:19.71#ibcon#about to write, iclass 34, count 0 2006.281.07:38:19.71#ibcon#wrote, iclass 34, count 0 2006.281.07:38:19.71#ibcon#about to read 3, iclass 34, count 0 2006.281.07:38:19.74#ibcon#read 3, iclass 34, count 0 2006.281.07:38:19.74#ibcon#about to read 4, iclass 34, count 0 2006.281.07:38:19.74#ibcon#read 4, iclass 34, count 0 2006.281.07:38:19.74#ibcon#about to read 5, iclass 34, count 0 2006.281.07:38:19.74#ibcon#read 5, iclass 34, count 0 2006.281.07:38:19.74#ibcon#about to read 6, iclass 34, count 0 2006.281.07:38:19.74#ibcon#read 6, iclass 34, count 0 2006.281.07:38:19.74#ibcon#end of sib2, iclass 34, count 0 2006.281.07:38:19.74#ibcon#*after write, iclass 34, count 0 2006.281.07:38:19.74#ibcon#*before return 0, iclass 34, count 0 2006.281.07:38:19.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:19.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:19.74#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:38:19.74#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:38:19.75$vc4f8/va=2,6 2006.281.07:38:19.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:38:19.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:38:19.75#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:19.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:19.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:19.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:19.79#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:38:19.79#ibcon#first serial, iclass 36, count 2 2006.281.07:38:19.79#ibcon#enter sib2, iclass 36, count 2 2006.281.07:38:19.79#ibcon#flushed, iclass 36, count 2 2006.281.07:38:19.79#ibcon#about to write, iclass 36, count 2 2006.281.07:38:19.79#ibcon#wrote, iclass 36, count 2 2006.281.07:38:19.79#ibcon#about to read 3, iclass 36, count 2 2006.281.07:38:19.81#ibcon#read 3, iclass 36, count 2 2006.281.07:38:19.81#ibcon#about to read 4, iclass 36, count 2 2006.281.07:38:19.81#ibcon#read 4, iclass 36, count 2 2006.281.07:38:19.81#ibcon#about to read 5, iclass 36, count 2 2006.281.07:38:19.81#ibcon#read 5, iclass 36, count 2 2006.281.07:38:19.81#ibcon#about to read 6, iclass 36, count 2 2006.281.07:38:19.81#ibcon#read 6, iclass 36, count 2 2006.281.07:38:19.81#ibcon#end of sib2, iclass 36, count 2 2006.281.07:38:19.81#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:38:19.81#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:38:19.81#ibcon#[25=AT02-06\r\n] 2006.281.07:38:19.81#ibcon#*before write, iclass 36, count 2 2006.281.07:38:19.81#ibcon#enter sib2, iclass 36, count 2 2006.281.07:38:19.81#ibcon#flushed, iclass 36, count 2 2006.281.07:38:19.81#ibcon#about to write, iclass 36, count 2 2006.281.07:38:19.81#ibcon#wrote, iclass 36, count 2 2006.281.07:38:19.81#ibcon#about to read 3, iclass 36, count 2 2006.281.07:38:19.85#ibcon#read 3, iclass 36, count 2 2006.281.07:38:19.85#ibcon#about to read 4, iclass 36, count 2 2006.281.07:38:19.85#ibcon#read 4, iclass 36, count 2 2006.281.07:38:19.85#ibcon#about to read 5, iclass 36, count 2 2006.281.07:38:19.85#ibcon#read 5, iclass 36, count 2 2006.281.07:38:19.85#ibcon#about to read 6, iclass 36, count 2 2006.281.07:38:19.85#ibcon#read 6, iclass 36, count 2 2006.281.07:38:19.85#ibcon#end of sib2, iclass 36, count 2 2006.281.07:38:19.85#ibcon#*after write, iclass 36, count 2 2006.281.07:38:19.85#ibcon#*before return 0, iclass 36, count 2 2006.281.07:38:19.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:19.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:19.85#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:38:19.85#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:19.85#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:19.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:19.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:19.96#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:38:19.96#ibcon#first serial, iclass 36, count 0 2006.281.07:38:19.96#ibcon#enter sib2, iclass 36, count 0 2006.281.07:38:19.96#ibcon#flushed, iclass 36, count 0 2006.281.07:38:19.96#ibcon#about to write, iclass 36, count 0 2006.281.07:38:19.96#ibcon#wrote, iclass 36, count 0 2006.281.07:38:19.96#ibcon#about to read 3, iclass 36, count 0 2006.281.07:38:19.98#ibcon#read 3, iclass 36, count 0 2006.281.07:38:19.98#ibcon#about to read 4, iclass 36, count 0 2006.281.07:38:19.98#ibcon#read 4, iclass 36, count 0 2006.281.07:38:19.98#ibcon#about to read 5, iclass 36, count 0 2006.281.07:38:19.98#ibcon#read 5, iclass 36, count 0 2006.281.07:38:19.98#ibcon#about to read 6, iclass 36, count 0 2006.281.07:38:19.98#ibcon#read 6, iclass 36, count 0 2006.281.07:38:19.98#ibcon#end of sib2, iclass 36, count 0 2006.281.07:38:19.98#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:38:19.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:38:19.98#ibcon#[25=USB\r\n] 2006.281.07:38:19.98#ibcon#*before write, iclass 36, count 0 2006.281.07:38:19.98#ibcon#enter sib2, iclass 36, count 0 2006.281.07:38:19.98#ibcon#flushed, iclass 36, count 0 2006.281.07:38:19.98#ibcon#about to write, iclass 36, count 0 2006.281.07:38:19.98#ibcon#wrote, iclass 36, count 0 2006.281.07:38:19.98#ibcon#about to read 3, iclass 36, count 0 2006.281.07:38:20.02#ibcon#read 3, iclass 36, count 0 2006.281.07:38:20.02#ibcon#about to read 4, iclass 36, count 0 2006.281.07:38:20.02#ibcon#read 4, iclass 36, count 0 2006.281.07:38:20.02#ibcon#about to read 5, iclass 36, count 0 2006.281.07:38:20.02#ibcon#read 5, iclass 36, count 0 2006.281.07:38:20.02#ibcon#about to read 6, iclass 36, count 0 2006.281.07:38:20.02#ibcon#read 6, iclass 36, count 0 2006.281.07:38:20.02#ibcon#end of sib2, iclass 36, count 0 2006.281.07:38:20.02#ibcon#*after write, iclass 36, count 0 2006.281.07:38:20.02#ibcon#*before return 0, iclass 36, count 0 2006.281.07:38:20.02#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:20.02#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:20.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:38:20.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:38:20.02$vc4f8/valo=3,672.99 2006.281.07:38:20.02#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:38:20.02#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:38:20.02#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:20.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:20.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:20.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:20.02#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:38:20.02#ibcon#first serial, iclass 38, count 0 2006.281.07:38:20.02#ibcon#enter sib2, iclass 38, count 0 2006.281.07:38:20.02#ibcon#flushed, iclass 38, count 0 2006.281.07:38:20.02#ibcon#about to write, iclass 38, count 0 2006.281.07:38:20.02#ibcon#wrote, iclass 38, count 0 2006.281.07:38:20.02#ibcon#about to read 3, iclass 38, count 0 2006.281.07:38:20.03#ibcon#read 3, iclass 38, count 0 2006.281.07:38:20.03#ibcon#about to read 4, iclass 38, count 0 2006.281.07:38:20.03#ibcon#read 4, iclass 38, count 0 2006.281.07:38:20.03#ibcon#about to read 5, iclass 38, count 0 2006.281.07:38:20.03#ibcon#read 5, iclass 38, count 0 2006.281.07:38:20.03#ibcon#about to read 6, iclass 38, count 0 2006.281.07:38:20.03#ibcon#read 6, iclass 38, count 0 2006.281.07:38:20.03#ibcon#end of sib2, iclass 38, count 0 2006.281.07:38:20.03#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:38:20.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:38:20.03#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:38:20.03#ibcon#*before write, iclass 38, count 0 2006.281.07:38:20.03#ibcon#enter sib2, iclass 38, count 0 2006.281.07:38:20.06#ibcon#flushed, iclass 38, count 0 2006.281.07:38:20.06#ibcon#about to write, iclass 38, count 0 2006.281.07:38:20.06#ibcon#wrote, iclass 38, count 0 2006.281.07:38:20.06#ibcon#about to read 3, iclass 38, count 0 2006.281.07:38:20.10#ibcon#read 3, iclass 38, count 0 2006.281.07:38:20.10#ibcon#about to read 4, iclass 38, count 0 2006.281.07:38:20.10#ibcon#read 4, iclass 38, count 0 2006.281.07:38:20.10#ibcon#about to read 5, iclass 38, count 0 2006.281.07:38:20.10#ibcon#read 5, iclass 38, count 0 2006.281.07:38:20.10#ibcon#about to read 6, iclass 38, count 0 2006.281.07:38:20.10#ibcon#read 6, iclass 38, count 0 2006.281.07:38:20.10#ibcon#end of sib2, iclass 38, count 0 2006.281.07:38:20.10#ibcon#*after write, iclass 38, count 0 2006.281.07:38:20.10#ibcon#*before return 0, iclass 38, count 0 2006.281.07:38:20.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:20.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:20.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:38:20.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:38:20.10$vc4f8/va=3,6 2006.281.07:38:20.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:38:20.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:38:20.10#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:20.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:20.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:20.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:20.14#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:38:20.14#ibcon#first serial, iclass 40, count 2 2006.281.07:38:20.14#ibcon#enter sib2, iclass 40, count 2 2006.281.07:38:20.14#ibcon#flushed, iclass 40, count 2 2006.281.07:38:20.14#ibcon#about to write, iclass 40, count 2 2006.281.07:38:20.14#ibcon#wrote, iclass 40, count 2 2006.281.07:38:20.14#ibcon#about to read 3, iclass 40, count 2 2006.281.07:38:20.15#ibcon#read 3, iclass 40, count 2 2006.281.07:38:20.15#ibcon#about to read 4, iclass 40, count 2 2006.281.07:38:20.15#ibcon#read 4, iclass 40, count 2 2006.281.07:38:20.15#ibcon#about to read 5, iclass 40, count 2 2006.281.07:38:20.15#ibcon#read 5, iclass 40, count 2 2006.281.07:38:20.15#ibcon#about to read 6, iclass 40, count 2 2006.281.07:38:20.15#ibcon#read 6, iclass 40, count 2 2006.281.07:38:20.15#ibcon#end of sib2, iclass 40, count 2 2006.281.07:38:20.15#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:38:20.15#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:38:20.15#ibcon#[25=AT03-06\r\n] 2006.281.07:38:20.15#ibcon#*before write, iclass 40, count 2 2006.281.07:38:20.15#ibcon#enter sib2, iclass 40, count 2 2006.281.07:38:20.15#ibcon#flushed, iclass 40, count 2 2006.281.07:38:20.15#ibcon#about to write, iclass 40, count 2 2006.281.07:38:20.15#ibcon#wrote, iclass 40, count 2 2006.281.07:38:20.15#ibcon#about to read 3, iclass 40, count 2 2006.281.07:38:20.18#ibcon#read 3, iclass 40, count 2 2006.281.07:38:20.18#ibcon#about to read 4, iclass 40, count 2 2006.281.07:38:20.18#ibcon#read 4, iclass 40, count 2 2006.281.07:38:20.18#ibcon#about to read 5, iclass 40, count 2 2006.281.07:38:20.18#ibcon#read 5, iclass 40, count 2 2006.281.07:38:20.18#ibcon#about to read 6, iclass 40, count 2 2006.281.07:38:20.18#ibcon#read 6, iclass 40, count 2 2006.281.07:38:20.18#ibcon#end of sib2, iclass 40, count 2 2006.281.07:38:20.18#ibcon#*after write, iclass 40, count 2 2006.281.07:38:20.18#ibcon#*before return 0, iclass 40, count 2 2006.281.07:38:20.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:20.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:20.18#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:38:20.18#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:20.18#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:20.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:20.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:20.31#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:38:20.31#ibcon#first serial, iclass 40, count 0 2006.281.07:38:20.31#ibcon#enter sib2, iclass 40, count 0 2006.281.07:38:20.31#ibcon#flushed, iclass 40, count 0 2006.281.07:38:20.31#ibcon#about to write, iclass 40, count 0 2006.281.07:38:20.31#ibcon#wrote, iclass 40, count 0 2006.281.07:38:20.31#ibcon#about to read 3, iclass 40, count 0 2006.281.07:38:20.32#ibcon#read 3, iclass 40, count 0 2006.281.07:38:20.32#ibcon#about to read 4, iclass 40, count 0 2006.281.07:38:20.32#ibcon#read 4, iclass 40, count 0 2006.281.07:38:20.32#ibcon#about to read 5, iclass 40, count 0 2006.281.07:38:20.32#ibcon#read 5, iclass 40, count 0 2006.281.07:38:20.32#ibcon#about to read 6, iclass 40, count 0 2006.281.07:38:20.32#ibcon#read 6, iclass 40, count 0 2006.281.07:38:20.32#ibcon#end of sib2, iclass 40, count 0 2006.281.07:38:20.32#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:38:20.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:38:20.32#ibcon#[25=USB\r\n] 2006.281.07:38:20.32#ibcon#*before write, iclass 40, count 0 2006.281.07:38:20.32#ibcon#enter sib2, iclass 40, count 0 2006.281.07:38:20.32#ibcon#flushed, iclass 40, count 0 2006.281.07:38:20.32#ibcon#about to write, iclass 40, count 0 2006.281.07:38:20.32#ibcon#wrote, iclass 40, count 0 2006.281.07:38:20.32#ibcon#about to read 3, iclass 40, count 0 2006.281.07:38:20.35#ibcon#read 3, iclass 40, count 0 2006.281.07:38:20.35#ibcon#about to read 4, iclass 40, count 0 2006.281.07:38:20.35#ibcon#read 4, iclass 40, count 0 2006.281.07:38:20.35#ibcon#about to read 5, iclass 40, count 0 2006.281.07:38:20.35#ibcon#read 5, iclass 40, count 0 2006.281.07:38:20.35#ibcon#about to read 6, iclass 40, count 0 2006.281.07:38:20.35#ibcon#read 6, iclass 40, count 0 2006.281.07:38:20.35#ibcon#end of sib2, iclass 40, count 0 2006.281.07:38:20.35#ibcon#*after write, iclass 40, count 0 2006.281.07:38:20.35#ibcon#*before return 0, iclass 40, count 0 2006.281.07:38:20.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:20.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:20.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:38:20.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:38:20.36$vc4f8/valo=4,832.99 2006.281.07:38:20.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:38:20.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:38:20.36#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:20.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:20.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:20.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:20.36#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:38:20.36#ibcon#first serial, iclass 4, count 0 2006.281.07:38:20.36#ibcon#enter sib2, iclass 4, count 0 2006.281.07:38:20.36#ibcon#flushed, iclass 4, count 0 2006.281.07:38:20.36#ibcon#about to write, iclass 4, count 0 2006.281.07:38:20.36#ibcon#wrote, iclass 4, count 0 2006.281.07:38:20.36#ibcon#about to read 3, iclass 4, count 0 2006.281.07:38:20.37#ibcon#read 3, iclass 4, count 0 2006.281.07:38:20.37#ibcon#about to read 4, iclass 4, count 0 2006.281.07:38:20.37#ibcon#read 4, iclass 4, count 0 2006.281.07:38:20.37#ibcon#about to read 5, iclass 4, count 0 2006.281.07:38:20.37#ibcon#read 5, iclass 4, count 0 2006.281.07:38:20.37#ibcon#about to read 6, iclass 4, count 0 2006.281.07:38:20.37#ibcon#read 6, iclass 4, count 0 2006.281.07:38:20.37#ibcon#end of sib2, iclass 4, count 0 2006.281.07:38:20.37#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:38:20.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:38:20.37#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:38:20.37#ibcon#*before write, iclass 4, count 0 2006.281.07:38:20.37#ibcon#enter sib2, iclass 4, count 0 2006.281.07:38:20.37#ibcon#flushed, iclass 4, count 0 2006.281.07:38:20.37#ibcon#about to write, iclass 4, count 0 2006.281.07:38:20.37#ibcon#wrote, iclass 4, count 0 2006.281.07:38:20.37#ibcon#about to read 3, iclass 4, count 0 2006.281.07:38:20.42#ibcon#read 3, iclass 4, count 0 2006.281.07:38:20.42#ibcon#about to read 4, iclass 4, count 0 2006.281.07:38:20.42#ibcon#read 4, iclass 4, count 0 2006.281.07:38:20.42#ibcon#about to read 5, iclass 4, count 0 2006.281.07:38:20.42#ibcon#read 5, iclass 4, count 0 2006.281.07:38:20.42#ibcon#about to read 6, iclass 4, count 0 2006.281.07:38:20.42#ibcon#read 6, iclass 4, count 0 2006.281.07:38:20.42#ibcon#end of sib2, iclass 4, count 0 2006.281.07:38:20.42#ibcon#*after write, iclass 4, count 0 2006.281.07:38:20.42#ibcon#*before return 0, iclass 4, count 0 2006.281.07:38:20.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:20.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:20.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:38:20.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:38:20.42$vc4f8/va=4,6 2006.281.07:38:20.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:38:20.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:38:20.42#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:20.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:20.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:20.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:20.46#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:38:20.46#ibcon#first serial, iclass 6, count 2 2006.281.07:38:20.46#ibcon#enter sib2, iclass 6, count 2 2006.281.07:38:20.46#ibcon#flushed, iclass 6, count 2 2006.281.07:38:20.46#ibcon#about to write, iclass 6, count 2 2006.281.07:38:20.46#ibcon#wrote, iclass 6, count 2 2006.281.07:38:20.46#ibcon#about to read 3, iclass 6, count 2 2006.281.07:38:20.48#ibcon#read 3, iclass 6, count 2 2006.281.07:38:20.48#ibcon#about to read 4, iclass 6, count 2 2006.281.07:38:20.48#ibcon#read 4, iclass 6, count 2 2006.281.07:38:20.48#ibcon#about to read 5, iclass 6, count 2 2006.281.07:38:20.48#ibcon#read 5, iclass 6, count 2 2006.281.07:38:20.48#ibcon#about to read 6, iclass 6, count 2 2006.281.07:38:20.48#ibcon#read 6, iclass 6, count 2 2006.281.07:38:20.48#ibcon#end of sib2, iclass 6, count 2 2006.281.07:38:20.48#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:38:20.48#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:38:20.48#ibcon#[25=AT04-06\r\n] 2006.281.07:38:20.48#ibcon#*before write, iclass 6, count 2 2006.281.07:38:20.48#ibcon#enter sib2, iclass 6, count 2 2006.281.07:38:20.48#ibcon#flushed, iclass 6, count 2 2006.281.07:38:20.48#ibcon#about to write, iclass 6, count 2 2006.281.07:38:20.48#ibcon#wrote, iclass 6, count 2 2006.281.07:38:20.48#ibcon#about to read 3, iclass 6, count 2 2006.281.07:38:20.52#ibcon#read 3, iclass 6, count 2 2006.281.07:38:20.52#ibcon#about to read 4, iclass 6, count 2 2006.281.07:38:20.52#ibcon#read 4, iclass 6, count 2 2006.281.07:38:20.52#ibcon#about to read 5, iclass 6, count 2 2006.281.07:38:20.52#ibcon#read 5, iclass 6, count 2 2006.281.07:38:20.52#ibcon#about to read 6, iclass 6, count 2 2006.281.07:38:20.52#ibcon#read 6, iclass 6, count 2 2006.281.07:38:20.52#ibcon#end of sib2, iclass 6, count 2 2006.281.07:38:20.52#ibcon#*after write, iclass 6, count 2 2006.281.07:38:20.52#ibcon#*before return 0, iclass 6, count 2 2006.281.07:38:20.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:20.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:20.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:38:20.52#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:20.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:20.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:20.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:20.63#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:38:20.63#ibcon#first serial, iclass 6, count 0 2006.281.07:38:20.63#ibcon#enter sib2, iclass 6, count 0 2006.281.07:38:20.63#ibcon#flushed, iclass 6, count 0 2006.281.07:38:20.63#ibcon#about to write, iclass 6, count 0 2006.281.07:38:20.63#ibcon#wrote, iclass 6, count 0 2006.281.07:38:20.63#ibcon#about to read 3, iclass 6, count 0 2006.281.07:38:20.65#ibcon#read 3, iclass 6, count 0 2006.281.07:38:20.65#ibcon#about to read 4, iclass 6, count 0 2006.281.07:38:20.65#ibcon#read 4, iclass 6, count 0 2006.281.07:38:20.65#ibcon#about to read 5, iclass 6, count 0 2006.281.07:38:20.65#ibcon#read 5, iclass 6, count 0 2006.281.07:38:20.65#ibcon#about to read 6, iclass 6, count 0 2006.281.07:38:20.65#ibcon#read 6, iclass 6, count 0 2006.281.07:38:20.65#ibcon#end of sib2, iclass 6, count 0 2006.281.07:38:20.65#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:38:20.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:38:20.65#ibcon#[25=USB\r\n] 2006.281.07:38:20.65#ibcon#*before write, iclass 6, count 0 2006.281.07:38:20.65#ibcon#enter sib2, iclass 6, count 0 2006.281.07:38:20.65#ibcon#flushed, iclass 6, count 0 2006.281.07:38:20.65#ibcon#about to write, iclass 6, count 0 2006.281.07:38:20.65#ibcon#wrote, iclass 6, count 0 2006.281.07:38:20.65#ibcon#about to read 3, iclass 6, count 0 2006.281.07:38:20.68#ibcon#read 3, iclass 6, count 0 2006.281.07:38:20.68#ibcon#about to read 4, iclass 6, count 0 2006.281.07:38:20.68#ibcon#read 4, iclass 6, count 0 2006.281.07:38:20.68#ibcon#about to read 5, iclass 6, count 0 2006.281.07:38:20.68#ibcon#read 5, iclass 6, count 0 2006.281.07:38:20.68#ibcon#about to read 6, iclass 6, count 0 2006.281.07:38:20.68#ibcon#read 6, iclass 6, count 0 2006.281.07:38:20.68#ibcon#end of sib2, iclass 6, count 0 2006.281.07:38:20.68#ibcon#*after write, iclass 6, count 0 2006.281.07:38:20.68#ibcon#*before return 0, iclass 6, count 0 2006.281.07:38:20.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:20.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:20.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:38:20.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:38:20.69$vc4f8/valo=5,652.99 2006.281.07:38:20.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:38:20.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:38:20.69#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:20.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:20.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:20.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:20.69#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:38:20.69#ibcon#first serial, iclass 10, count 0 2006.281.07:38:20.69#ibcon#enter sib2, iclass 10, count 0 2006.281.07:38:20.69#ibcon#flushed, iclass 10, count 0 2006.281.07:38:20.69#ibcon#about to write, iclass 10, count 0 2006.281.07:38:20.69#ibcon#wrote, iclass 10, count 0 2006.281.07:38:20.69#ibcon#about to read 3, iclass 10, count 0 2006.281.07:38:20.70#ibcon#read 3, iclass 10, count 0 2006.281.07:38:20.70#ibcon#about to read 4, iclass 10, count 0 2006.281.07:38:20.70#ibcon#read 4, iclass 10, count 0 2006.281.07:38:20.70#ibcon#about to read 5, iclass 10, count 0 2006.281.07:38:20.70#ibcon#read 5, iclass 10, count 0 2006.281.07:38:20.70#ibcon#about to read 6, iclass 10, count 0 2006.281.07:38:20.70#ibcon#read 6, iclass 10, count 0 2006.281.07:38:20.70#ibcon#end of sib2, iclass 10, count 0 2006.281.07:38:20.70#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:38:20.70#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:38:20.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:38:20.70#ibcon#*before write, iclass 10, count 0 2006.281.07:38:20.70#ibcon#enter sib2, iclass 10, count 0 2006.281.07:38:20.70#ibcon#flushed, iclass 10, count 0 2006.281.07:38:20.70#ibcon#about to write, iclass 10, count 0 2006.281.07:38:20.70#ibcon#wrote, iclass 10, count 0 2006.281.07:38:20.70#ibcon#about to read 3, iclass 10, count 0 2006.281.07:38:20.74#ibcon#read 3, iclass 10, count 0 2006.281.07:38:20.74#ibcon#about to read 4, iclass 10, count 0 2006.281.07:38:20.74#ibcon#read 4, iclass 10, count 0 2006.281.07:38:20.74#ibcon#about to read 5, iclass 10, count 0 2006.281.07:38:20.74#ibcon#read 5, iclass 10, count 0 2006.281.07:38:20.74#ibcon#about to read 6, iclass 10, count 0 2006.281.07:38:20.74#ibcon#read 6, iclass 10, count 0 2006.281.07:38:20.74#ibcon#end of sib2, iclass 10, count 0 2006.281.07:38:20.74#ibcon#*after write, iclass 10, count 0 2006.281.07:38:20.74#ibcon#*before return 0, iclass 10, count 0 2006.281.07:38:20.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:20.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:20.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:38:20.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:38:20.75$vc4f8/va=5,7 2006.281.07:38:20.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:38:20.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:38:20.76#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:20.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:20.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:20.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:20.79#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:38:20.79#ibcon#first serial, iclass 12, count 2 2006.281.07:38:20.79#ibcon#enter sib2, iclass 12, count 2 2006.281.07:38:20.79#ibcon#flushed, iclass 12, count 2 2006.281.07:38:20.79#ibcon#about to write, iclass 12, count 2 2006.281.07:38:20.79#ibcon#wrote, iclass 12, count 2 2006.281.07:38:20.79#ibcon#about to read 3, iclass 12, count 2 2006.281.07:38:20.82#ibcon#read 3, iclass 12, count 2 2006.281.07:38:20.82#ibcon#about to read 4, iclass 12, count 2 2006.281.07:38:20.82#ibcon#read 4, iclass 12, count 2 2006.281.07:38:20.82#ibcon#about to read 5, iclass 12, count 2 2006.281.07:38:20.82#ibcon#read 5, iclass 12, count 2 2006.281.07:38:20.82#ibcon#about to read 6, iclass 12, count 2 2006.281.07:38:20.82#ibcon#read 6, iclass 12, count 2 2006.281.07:38:20.82#ibcon#end of sib2, iclass 12, count 2 2006.281.07:38:20.82#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:38:20.82#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:38:20.82#ibcon#[25=AT05-07\r\n] 2006.281.07:38:20.82#ibcon#*before write, iclass 12, count 2 2006.281.07:38:20.82#ibcon#enter sib2, iclass 12, count 2 2006.281.07:38:20.82#ibcon#flushed, iclass 12, count 2 2006.281.07:38:20.82#ibcon#about to write, iclass 12, count 2 2006.281.07:38:20.82#ibcon#wrote, iclass 12, count 2 2006.281.07:38:20.82#ibcon#about to read 3, iclass 12, count 2 2006.281.07:38:20.85#ibcon#read 3, iclass 12, count 2 2006.281.07:38:20.85#ibcon#about to read 4, iclass 12, count 2 2006.281.07:38:20.85#ibcon#read 4, iclass 12, count 2 2006.281.07:38:20.85#ibcon#about to read 5, iclass 12, count 2 2006.281.07:38:20.85#ibcon#read 5, iclass 12, count 2 2006.281.07:38:20.85#ibcon#about to read 6, iclass 12, count 2 2006.281.07:38:20.85#ibcon#read 6, iclass 12, count 2 2006.281.07:38:20.85#ibcon#end of sib2, iclass 12, count 2 2006.281.07:38:20.85#ibcon#*after write, iclass 12, count 2 2006.281.07:38:20.85#ibcon#*before return 0, iclass 12, count 2 2006.281.07:38:20.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:20.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:20.85#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:38:20.85#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:20.85#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:20.97#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:20.97#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:20.97#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:38:20.97#ibcon#first serial, iclass 12, count 0 2006.281.07:38:20.97#ibcon#enter sib2, iclass 12, count 0 2006.281.07:38:20.97#ibcon#flushed, iclass 12, count 0 2006.281.07:38:20.97#ibcon#about to write, iclass 12, count 0 2006.281.07:38:20.97#ibcon#wrote, iclass 12, count 0 2006.281.07:38:20.97#ibcon#about to read 3, iclass 12, count 0 2006.281.07:38:20.99#ibcon#read 3, iclass 12, count 0 2006.281.07:38:20.99#ibcon#about to read 4, iclass 12, count 0 2006.281.07:38:20.99#ibcon#read 4, iclass 12, count 0 2006.281.07:38:20.99#ibcon#about to read 5, iclass 12, count 0 2006.281.07:38:20.99#ibcon#read 5, iclass 12, count 0 2006.281.07:38:20.99#ibcon#about to read 6, iclass 12, count 0 2006.281.07:38:20.99#ibcon#read 6, iclass 12, count 0 2006.281.07:38:20.99#ibcon#end of sib2, iclass 12, count 0 2006.281.07:38:20.99#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:38:20.99#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:38:20.99#ibcon#[25=USB\r\n] 2006.281.07:38:20.99#ibcon#*before write, iclass 12, count 0 2006.281.07:38:20.99#ibcon#enter sib2, iclass 12, count 0 2006.281.07:38:20.99#ibcon#flushed, iclass 12, count 0 2006.281.07:38:20.99#ibcon#about to write, iclass 12, count 0 2006.281.07:38:20.99#ibcon#wrote, iclass 12, count 0 2006.281.07:38:20.99#ibcon#about to read 3, iclass 12, count 0 2006.281.07:38:21.03#ibcon#read 3, iclass 12, count 0 2006.281.07:38:21.03#ibcon#about to read 4, iclass 12, count 0 2006.281.07:38:21.03#ibcon#read 4, iclass 12, count 0 2006.281.07:38:21.03#ibcon#about to read 5, iclass 12, count 0 2006.281.07:38:21.03#ibcon#read 5, iclass 12, count 0 2006.281.07:38:21.03#ibcon#about to read 6, iclass 12, count 0 2006.281.07:38:21.03#ibcon#read 6, iclass 12, count 0 2006.281.07:38:21.03#ibcon#end of sib2, iclass 12, count 0 2006.281.07:38:21.03#ibcon#*after write, iclass 12, count 0 2006.281.07:38:21.03#ibcon#*before return 0, iclass 12, count 0 2006.281.07:38:21.03#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:21.03#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:21.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:38:21.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:38:21.03$vc4f8/valo=6,772.99 2006.281.07:38:21.03#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:38:21.03#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:38:21.03#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:21.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:38:21.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:38:21.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:38:21.03#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:38:21.03#ibcon#first serial, iclass 14, count 0 2006.281.07:38:21.03#ibcon#enter sib2, iclass 14, count 0 2006.281.07:38:21.03#ibcon#flushed, iclass 14, count 0 2006.281.07:38:21.03#ibcon#about to write, iclass 14, count 0 2006.281.07:38:21.03#ibcon#wrote, iclass 14, count 0 2006.281.07:38:21.03#ibcon#about to read 3, iclass 14, count 0 2006.281.07:38:21.05#ibcon#read 3, iclass 14, count 0 2006.281.07:38:21.05#ibcon#about to read 4, iclass 14, count 0 2006.281.07:38:21.05#ibcon#read 4, iclass 14, count 0 2006.281.07:38:21.05#ibcon#about to read 5, iclass 14, count 0 2006.281.07:38:21.05#ibcon#read 5, iclass 14, count 0 2006.281.07:38:21.05#ibcon#about to read 6, iclass 14, count 0 2006.281.07:38:21.05#ibcon#read 6, iclass 14, count 0 2006.281.07:38:21.05#ibcon#end of sib2, iclass 14, count 0 2006.281.07:38:21.05#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:38:21.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:38:21.05#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:38:21.05#ibcon#*before write, iclass 14, count 0 2006.281.07:38:21.05#ibcon#enter sib2, iclass 14, count 0 2006.281.07:38:21.05#ibcon#flushed, iclass 14, count 0 2006.281.07:38:21.05#ibcon#about to write, iclass 14, count 0 2006.281.07:38:21.05#ibcon#wrote, iclass 14, count 0 2006.281.07:38:21.05#ibcon#about to read 3, iclass 14, count 0 2006.281.07:38:21.10#ibcon#read 3, iclass 14, count 0 2006.281.07:38:21.10#ibcon#about to read 4, iclass 14, count 0 2006.281.07:38:21.10#ibcon#read 4, iclass 14, count 0 2006.281.07:38:21.10#ibcon#about to read 5, iclass 14, count 0 2006.281.07:38:21.10#ibcon#read 5, iclass 14, count 0 2006.281.07:38:21.10#ibcon#about to read 6, iclass 14, count 0 2006.281.07:38:21.10#ibcon#read 6, iclass 14, count 0 2006.281.07:38:21.10#ibcon#end of sib2, iclass 14, count 0 2006.281.07:38:21.10#ibcon#*after write, iclass 14, count 0 2006.281.07:38:21.10#ibcon#*before return 0, iclass 14, count 0 2006.281.07:38:21.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:38:21.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:38:21.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:38:21.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:38:21.10$vc4f8/va=6,6 2006.281.07:38:21.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.07:38:21.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.07:38:21.10#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:21.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:38:21.14#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:38:21.14#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:38:21.14#ibcon#enter wrdev, iclass 16, count 2 2006.281.07:38:21.14#ibcon#first serial, iclass 16, count 2 2006.281.07:38:21.14#ibcon#enter sib2, iclass 16, count 2 2006.281.07:38:21.14#ibcon#flushed, iclass 16, count 2 2006.281.07:38:21.14#ibcon#about to write, iclass 16, count 2 2006.281.07:38:21.14#ibcon#wrote, iclass 16, count 2 2006.281.07:38:21.14#ibcon#about to read 3, iclass 16, count 2 2006.281.07:38:21.16#ibcon#read 3, iclass 16, count 2 2006.281.07:38:21.16#ibcon#about to read 4, iclass 16, count 2 2006.281.07:38:21.16#ibcon#read 4, iclass 16, count 2 2006.281.07:38:21.16#ibcon#about to read 5, iclass 16, count 2 2006.281.07:38:21.16#ibcon#read 5, iclass 16, count 2 2006.281.07:38:21.16#ibcon#about to read 6, iclass 16, count 2 2006.281.07:38:21.16#ibcon#read 6, iclass 16, count 2 2006.281.07:38:21.16#ibcon#end of sib2, iclass 16, count 2 2006.281.07:38:21.16#ibcon#*mode == 0, iclass 16, count 2 2006.281.07:38:21.16#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.07:38:21.16#ibcon#[25=AT06-06\r\n] 2006.281.07:38:21.16#ibcon#*before write, iclass 16, count 2 2006.281.07:38:21.16#ibcon#enter sib2, iclass 16, count 2 2006.281.07:38:21.16#ibcon#flushed, iclass 16, count 2 2006.281.07:38:21.16#ibcon#about to write, iclass 16, count 2 2006.281.07:38:21.16#ibcon#wrote, iclass 16, count 2 2006.281.07:38:21.16#ibcon#about to read 3, iclass 16, count 2 2006.281.07:38:21.20#ibcon#read 3, iclass 16, count 2 2006.281.07:38:21.20#ibcon#about to read 4, iclass 16, count 2 2006.281.07:38:21.20#ibcon#read 4, iclass 16, count 2 2006.281.07:38:21.20#ibcon#about to read 5, iclass 16, count 2 2006.281.07:38:21.20#ibcon#read 5, iclass 16, count 2 2006.281.07:38:21.20#ibcon#about to read 6, iclass 16, count 2 2006.281.07:38:21.20#ibcon#read 6, iclass 16, count 2 2006.281.07:38:21.20#ibcon#end of sib2, iclass 16, count 2 2006.281.07:38:21.20#ibcon#*after write, iclass 16, count 2 2006.281.07:38:21.20#ibcon#*before return 0, iclass 16, count 2 2006.281.07:38:21.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:38:21.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:38:21.20#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.07:38:21.20#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:21.20#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:38:21.31#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:38:21.31#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:38:21.31#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:38:21.31#ibcon#first serial, iclass 16, count 0 2006.281.07:38:21.31#ibcon#enter sib2, iclass 16, count 0 2006.281.07:38:21.31#ibcon#flushed, iclass 16, count 0 2006.281.07:38:21.31#ibcon#about to write, iclass 16, count 0 2006.281.07:38:21.31#ibcon#wrote, iclass 16, count 0 2006.281.07:38:21.31#ibcon#about to read 3, iclass 16, count 0 2006.281.07:38:21.33#ibcon#read 3, iclass 16, count 0 2006.281.07:38:21.33#ibcon#about to read 4, iclass 16, count 0 2006.281.07:38:21.33#ibcon#read 4, iclass 16, count 0 2006.281.07:38:21.33#ibcon#about to read 5, iclass 16, count 0 2006.281.07:38:21.33#ibcon#read 5, iclass 16, count 0 2006.281.07:38:21.33#ibcon#about to read 6, iclass 16, count 0 2006.281.07:38:21.33#ibcon#read 6, iclass 16, count 0 2006.281.07:38:21.33#ibcon#end of sib2, iclass 16, count 0 2006.281.07:38:21.33#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:38:21.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:38:21.33#ibcon#[25=USB\r\n] 2006.281.07:38:21.33#ibcon#*before write, iclass 16, count 0 2006.281.07:38:21.33#ibcon#enter sib2, iclass 16, count 0 2006.281.07:38:21.33#ibcon#flushed, iclass 16, count 0 2006.281.07:38:21.33#ibcon#about to write, iclass 16, count 0 2006.281.07:38:21.33#ibcon#wrote, iclass 16, count 0 2006.281.07:38:21.33#ibcon#about to read 3, iclass 16, count 0 2006.281.07:38:21.36#ibcon#read 3, iclass 16, count 0 2006.281.07:38:21.36#ibcon#about to read 4, iclass 16, count 0 2006.281.07:38:21.36#ibcon#read 4, iclass 16, count 0 2006.281.07:38:21.36#ibcon#about to read 5, iclass 16, count 0 2006.281.07:38:21.36#ibcon#read 5, iclass 16, count 0 2006.281.07:38:21.36#ibcon#about to read 6, iclass 16, count 0 2006.281.07:38:21.36#ibcon#read 6, iclass 16, count 0 2006.281.07:38:21.36#ibcon#end of sib2, iclass 16, count 0 2006.281.07:38:21.36#ibcon#*after write, iclass 16, count 0 2006.281.07:38:21.36#ibcon#*before return 0, iclass 16, count 0 2006.281.07:38:21.36#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:38:21.36#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:38:21.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:38:21.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:38:21.37$vc4f8/valo=7,832.99 2006.281.07:38:21.37#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.07:38:21.37#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.07:38:21.37#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:21.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:38:21.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:38:21.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:38:21.37#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:38:21.37#ibcon#first serial, iclass 18, count 0 2006.281.07:38:21.37#ibcon#enter sib2, iclass 18, count 0 2006.281.07:38:21.37#ibcon#flushed, iclass 18, count 0 2006.281.07:38:21.37#ibcon#about to write, iclass 18, count 0 2006.281.07:38:21.37#ibcon#wrote, iclass 18, count 0 2006.281.07:38:21.37#ibcon#about to read 3, iclass 18, count 0 2006.281.07:38:21.38#ibcon#read 3, iclass 18, count 0 2006.281.07:38:21.38#ibcon#about to read 4, iclass 18, count 0 2006.281.07:38:21.38#ibcon#read 4, iclass 18, count 0 2006.281.07:38:21.38#ibcon#about to read 5, iclass 18, count 0 2006.281.07:38:21.38#ibcon#read 5, iclass 18, count 0 2006.281.07:38:21.38#ibcon#about to read 6, iclass 18, count 0 2006.281.07:38:21.38#ibcon#read 6, iclass 18, count 0 2006.281.07:38:21.38#ibcon#end of sib2, iclass 18, count 0 2006.281.07:38:21.38#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:38:21.38#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:38:21.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:38:21.38#ibcon#*before write, iclass 18, count 0 2006.281.07:38:21.38#ibcon#enter sib2, iclass 18, count 0 2006.281.07:38:21.38#ibcon#flushed, iclass 18, count 0 2006.281.07:38:21.38#ibcon#about to write, iclass 18, count 0 2006.281.07:38:21.38#ibcon#wrote, iclass 18, count 0 2006.281.07:38:21.38#ibcon#about to read 3, iclass 18, count 0 2006.281.07:38:21.43#ibcon#read 3, iclass 18, count 0 2006.281.07:38:21.43#ibcon#about to read 4, iclass 18, count 0 2006.281.07:38:21.43#ibcon#read 4, iclass 18, count 0 2006.281.07:38:21.43#ibcon#about to read 5, iclass 18, count 0 2006.281.07:38:21.43#ibcon#read 5, iclass 18, count 0 2006.281.07:38:21.43#ibcon#about to read 6, iclass 18, count 0 2006.281.07:38:21.43#ibcon#read 6, iclass 18, count 0 2006.281.07:38:21.43#ibcon#end of sib2, iclass 18, count 0 2006.281.07:38:21.43#ibcon#*after write, iclass 18, count 0 2006.281.07:38:21.43#ibcon#*before return 0, iclass 18, count 0 2006.281.07:38:21.43#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:38:21.43#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:38:21.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:38:21.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:38:21.43$vc4f8/va=7,6 2006.281.07:38:21.43#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.07:38:21.43#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.07:38:21.43#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:21.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:38:21.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:38:21.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:38:21.47#ibcon#enter wrdev, iclass 20, count 2 2006.281.07:38:21.47#ibcon#first serial, iclass 20, count 2 2006.281.07:38:21.47#ibcon#enter sib2, iclass 20, count 2 2006.281.07:38:21.47#ibcon#flushed, iclass 20, count 2 2006.281.07:38:21.47#ibcon#about to write, iclass 20, count 2 2006.281.07:38:21.47#ibcon#wrote, iclass 20, count 2 2006.281.07:38:21.47#ibcon#about to read 3, iclass 20, count 2 2006.281.07:38:21.50#ibcon#read 3, iclass 20, count 2 2006.281.07:38:21.50#ibcon#about to read 4, iclass 20, count 2 2006.281.07:38:21.50#ibcon#read 4, iclass 20, count 2 2006.281.07:38:21.50#ibcon#about to read 5, iclass 20, count 2 2006.281.07:38:21.50#ibcon#read 5, iclass 20, count 2 2006.281.07:38:21.50#ibcon#about to read 6, iclass 20, count 2 2006.281.07:38:21.50#ibcon#read 6, iclass 20, count 2 2006.281.07:38:21.50#ibcon#end of sib2, iclass 20, count 2 2006.281.07:38:21.50#ibcon#*mode == 0, iclass 20, count 2 2006.281.07:38:21.50#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.07:38:21.50#ibcon#[25=AT07-06\r\n] 2006.281.07:38:21.50#ibcon#*before write, iclass 20, count 2 2006.281.07:38:21.50#ibcon#enter sib2, iclass 20, count 2 2006.281.07:38:21.50#ibcon#flushed, iclass 20, count 2 2006.281.07:38:21.50#ibcon#about to write, iclass 20, count 2 2006.281.07:38:21.50#ibcon#wrote, iclass 20, count 2 2006.281.07:38:21.50#ibcon#about to read 3, iclass 20, count 2 2006.281.07:38:21.53#ibcon#read 3, iclass 20, count 2 2006.281.07:38:21.53#ibcon#about to read 4, iclass 20, count 2 2006.281.07:38:21.53#ibcon#read 4, iclass 20, count 2 2006.281.07:38:21.53#ibcon#about to read 5, iclass 20, count 2 2006.281.07:38:21.53#ibcon#read 5, iclass 20, count 2 2006.281.07:38:21.53#ibcon#about to read 6, iclass 20, count 2 2006.281.07:38:21.53#ibcon#read 6, iclass 20, count 2 2006.281.07:38:21.53#ibcon#end of sib2, iclass 20, count 2 2006.281.07:38:21.53#ibcon#*after write, iclass 20, count 2 2006.281.07:38:21.53#ibcon#*before return 0, iclass 20, count 2 2006.281.07:38:21.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:38:21.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:38:21.53#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.07:38:21.53#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:21.53#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:38:21.64#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:38:21.64#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:38:21.64#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:38:21.64#ibcon#first serial, iclass 20, count 0 2006.281.07:38:21.64#ibcon#enter sib2, iclass 20, count 0 2006.281.07:38:21.64#ibcon#flushed, iclass 20, count 0 2006.281.07:38:21.64#ibcon#about to write, iclass 20, count 0 2006.281.07:38:21.64#ibcon#wrote, iclass 20, count 0 2006.281.07:38:21.64#ibcon#about to read 3, iclass 20, count 0 2006.281.07:38:21.66#ibcon#read 3, iclass 20, count 0 2006.281.07:38:21.66#ibcon#about to read 4, iclass 20, count 0 2006.281.07:38:21.66#ibcon#read 4, iclass 20, count 0 2006.281.07:38:21.66#ibcon#about to read 5, iclass 20, count 0 2006.281.07:38:21.66#ibcon#read 5, iclass 20, count 0 2006.281.07:38:21.66#ibcon#about to read 6, iclass 20, count 0 2006.281.07:38:21.66#ibcon#read 6, iclass 20, count 0 2006.281.07:38:21.66#ibcon#end of sib2, iclass 20, count 0 2006.281.07:38:21.66#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:38:21.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:38:21.66#ibcon#[25=USB\r\n] 2006.281.07:38:21.66#ibcon#*before write, iclass 20, count 0 2006.281.07:38:21.66#ibcon#enter sib2, iclass 20, count 0 2006.281.07:38:21.66#ibcon#flushed, iclass 20, count 0 2006.281.07:38:21.66#ibcon#about to write, iclass 20, count 0 2006.281.07:38:21.66#ibcon#wrote, iclass 20, count 0 2006.281.07:38:21.66#ibcon#about to read 3, iclass 20, count 0 2006.281.07:38:21.69#ibcon#read 3, iclass 20, count 0 2006.281.07:38:21.69#ibcon#about to read 4, iclass 20, count 0 2006.281.07:38:21.69#ibcon#read 4, iclass 20, count 0 2006.281.07:38:21.69#ibcon#about to read 5, iclass 20, count 0 2006.281.07:38:21.69#ibcon#read 5, iclass 20, count 0 2006.281.07:38:21.69#ibcon#about to read 6, iclass 20, count 0 2006.281.07:38:21.69#ibcon#read 6, iclass 20, count 0 2006.281.07:38:21.69#ibcon#end of sib2, iclass 20, count 0 2006.281.07:38:21.69#ibcon#*after write, iclass 20, count 0 2006.281.07:38:21.69#ibcon#*before return 0, iclass 20, count 0 2006.281.07:38:21.69#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:38:21.69#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:38:21.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:38:21.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:38:21.70$vc4f8/valo=8,852.99 2006.281.07:38:21.70#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.07:38:21.70#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.07:38:21.70#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:21.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:38:21.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:38:21.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:38:21.70#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:38:21.70#ibcon#first serial, iclass 22, count 0 2006.281.07:38:21.70#ibcon#enter sib2, iclass 22, count 0 2006.281.07:38:21.70#ibcon#flushed, iclass 22, count 0 2006.281.07:38:21.70#ibcon#about to write, iclass 22, count 0 2006.281.07:38:21.70#ibcon#wrote, iclass 22, count 0 2006.281.07:38:21.70#ibcon#about to read 3, iclass 22, count 0 2006.281.07:38:21.71#ibcon#read 3, iclass 22, count 0 2006.281.07:38:21.71#ibcon#about to read 4, iclass 22, count 0 2006.281.07:38:21.71#ibcon#read 4, iclass 22, count 0 2006.281.07:38:21.71#ibcon#about to read 5, iclass 22, count 0 2006.281.07:38:21.71#ibcon#read 5, iclass 22, count 0 2006.281.07:38:21.71#ibcon#about to read 6, iclass 22, count 0 2006.281.07:38:21.71#ibcon#read 6, iclass 22, count 0 2006.281.07:38:21.71#ibcon#end of sib2, iclass 22, count 0 2006.281.07:38:21.71#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:38:21.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:38:21.71#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:38:21.71#ibcon#*before write, iclass 22, count 0 2006.281.07:38:21.71#ibcon#enter sib2, iclass 22, count 0 2006.281.07:38:21.71#ibcon#flushed, iclass 22, count 0 2006.281.07:38:21.71#ibcon#about to write, iclass 22, count 0 2006.281.07:38:21.71#ibcon#wrote, iclass 22, count 0 2006.281.07:38:21.71#ibcon#about to read 3, iclass 22, count 0 2006.281.07:38:21.75#ibcon#read 3, iclass 22, count 0 2006.281.07:38:21.75#ibcon#about to read 4, iclass 22, count 0 2006.281.07:38:21.75#ibcon#read 4, iclass 22, count 0 2006.281.07:38:21.75#ibcon#about to read 5, iclass 22, count 0 2006.281.07:38:21.75#ibcon#read 5, iclass 22, count 0 2006.281.07:38:21.75#ibcon#about to read 6, iclass 22, count 0 2006.281.07:38:21.75#ibcon#read 6, iclass 22, count 0 2006.281.07:38:21.75#ibcon#end of sib2, iclass 22, count 0 2006.281.07:38:21.75#ibcon#*after write, iclass 22, count 0 2006.281.07:38:21.75#ibcon#*before return 0, iclass 22, count 0 2006.281.07:38:21.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:38:21.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:38:21.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:38:21.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:38:21.76$vc4f8/va=8,6 2006.281.07:38:21.76#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.07:38:21.76#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.07:38:21.76#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:21.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:38:21.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:38:21.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:38:21.80#ibcon#enter wrdev, iclass 24, count 2 2006.281.07:38:21.80#ibcon#first serial, iclass 24, count 2 2006.281.07:38:21.80#ibcon#enter sib2, iclass 24, count 2 2006.281.07:38:21.80#ibcon#flushed, iclass 24, count 2 2006.281.07:38:21.80#ibcon#about to write, iclass 24, count 2 2006.281.07:38:21.80#ibcon#wrote, iclass 24, count 2 2006.281.07:38:21.80#ibcon#about to read 3, iclass 24, count 2 2006.281.07:38:21.83#ibcon#read 3, iclass 24, count 2 2006.281.07:38:21.83#ibcon#about to read 4, iclass 24, count 2 2006.281.07:38:21.83#ibcon#read 4, iclass 24, count 2 2006.281.07:38:21.83#ibcon#about to read 5, iclass 24, count 2 2006.281.07:38:21.83#ibcon#read 5, iclass 24, count 2 2006.281.07:38:21.83#ibcon#about to read 6, iclass 24, count 2 2006.281.07:38:21.83#ibcon#read 6, iclass 24, count 2 2006.281.07:38:21.83#ibcon#end of sib2, iclass 24, count 2 2006.281.07:38:21.83#ibcon#*mode == 0, iclass 24, count 2 2006.281.07:38:21.83#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.07:38:21.83#ibcon#[25=AT08-06\r\n] 2006.281.07:38:21.83#ibcon#*before write, iclass 24, count 2 2006.281.07:38:21.83#ibcon#enter sib2, iclass 24, count 2 2006.281.07:38:21.83#ibcon#flushed, iclass 24, count 2 2006.281.07:38:21.83#ibcon#about to write, iclass 24, count 2 2006.281.07:38:21.83#ibcon#wrote, iclass 24, count 2 2006.281.07:38:21.83#ibcon#about to read 3, iclass 24, count 2 2006.281.07:38:21.86#ibcon#read 3, iclass 24, count 2 2006.281.07:38:21.86#ibcon#about to read 4, iclass 24, count 2 2006.281.07:38:21.86#ibcon#read 4, iclass 24, count 2 2006.281.07:38:21.86#ibcon#about to read 5, iclass 24, count 2 2006.281.07:38:21.86#ibcon#read 5, iclass 24, count 2 2006.281.07:38:21.86#ibcon#about to read 6, iclass 24, count 2 2006.281.07:38:21.86#ibcon#read 6, iclass 24, count 2 2006.281.07:38:21.86#ibcon#end of sib2, iclass 24, count 2 2006.281.07:38:21.86#ibcon#*after write, iclass 24, count 2 2006.281.07:38:21.86#ibcon#*before return 0, iclass 24, count 2 2006.281.07:38:21.86#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:38:21.86#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:38:21.86#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.07:38:21.86#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:21.86#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:38:21.98#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:38:21.98#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:38:21.98#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:38:21.98#ibcon#first serial, iclass 24, count 0 2006.281.07:38:21.98#ibcon#enter sib2, iclass 24, count 0 2006.281.07:38:21.98#ibcon#flushed, iclass 24, count 0 2006.281.07:38:21.98#ibcon#about to write, iclass 24, count 0 2006.281.07:38:21.98#ibcon#wrote, iclass 24, count 0 2006.281.07:38:21.98#ibcon#about to read 3, iclass 24, count 0 2006.281.07:38:22.00#ibcon#read 3, iclass 24, count 0 2006.281.07:38:22.00#ibcon#about to read 4, iclass 24, count 0 2006.281.07:38:22.00#ibcon#read 4, iclass 24, count 0 2006.281.07:38:22.00#ibcon#about to read 5, iclass 24, count 0 2006.281.07:38:22.00#ibcon#read 5, iclass 24, count 0 2006.281.07:38:22.00#ibcon#about to read 6, iclass 24, count 0 2006.281.07:38:22.00#ibcon#read 6, iclass 24, count 0 2006.281.07:38:22.00#ibcon#end of sib2, iclass 24, count 0 2006.281.07:38:22.00#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:38:22.00#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:38:22.00#ibcon#[25=USB\r\n] 2006.281.07:38:22.00#ibcon#*before write, iclass 24, count 0 2006.281.07:38:22.00#ibcon#enter sib2, iclass 24, count 0 2006.281.07:38:22.00#ibcon#flushed, iclass 24, count 0 2006.281.07:38:22.00#ibcon#about to write, iclass 24, count 0 2006.281.07:38:22.00#ibcon#wrote, iclass 24, count 0 2006.281.07:38:22.00#ibcon#about to read 3, iclass 24, count 0 2006.281.07:38:22.04#ibcon#read 3, iclass 24, count 0 2006.281.07:38:22.04#ibcon#about to read 4, iclass 24, count 0 2006.281.07:38:22.04#ibcon#read 4, iclass 24, count 0 2006.281.07:38:22.04#ibcon#about to read 5, iclass 24, count 0 2006.281.07:38:22.04#ibcon#read 5, iclass 24, count 0 2006.281.07:38:22.04#ibcon#about to read 6, iclass 24, count 0 2006.281.07:38:22.04#ibcon#read 6, iclass 24, count 0 2006.281.07:38:22.04#ibcon#end of sib2, iclass 24, count 0 2006.281.07:38:22.04#ibcon#*after write, iclass 24, count 0 2006.281.07:38:22.04#ibcon#*before return 0, iclass 24, count 0 2006.281.07:38:22.04#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:38:22.04#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:38:22.04#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:38:22.04#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:38:22.04$vc4f8/vblo=1,632.99 2006.281.07:38:22.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:38:22.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:38:22.04#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:22.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:38:22.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:38:22.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:38:22.04#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:38:22.04#ibcon#first serial, iclass 26, count 0 2006.281.07:38:22.04#ibcon#enter sib2, iclass 26, count 0 2006.281.07:38:22.04#ibcon#flushed, iclass 26, count 0 2006.281.07:38:22.04#ibcon#about to write, iclass 26, count 0 2006.281.07:38:22.04#ibcon#wrote, iclass 26, count 0 2006.281.07:38:22.04#ibcon#about to read 3, iclass 26, count 0 2006.281.07:38:22.05#ibcon#read 3, iclass 26, count 0 2006.281.07:38:22.05#ibcon#about to read 4, iclass 26, count 0 2006.281.07:38:22.05#ibcon#read 4, iclass 26, count 0 2006.281.07:38:22.05#ibcon#about to read 5, iclass 26, count 0 2006.281.07:38:22.05#ibcon#read 5, iclass 26, count 0 2006.281.07:38:22.05#ibcon#about to read 6, iclass 26, count 0 2006.281.07:38:22.05#ibcon#read 6, iclass 26, count 0 2006.281.07:38:22.05#ibcon#end of sib2, iclass 26, count 0 2006.281.07:38:22.05#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:38:22.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:38:22.05#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:38:22.08#ibcon#*before write, iclass 26, count 0 2006.281.07:38:22.08#ibcon#enter sib2, iclass 26, count 0 2006.281.07:38:22.08#ibcon#flushed, iclass 26, count 0 2006.281.07:38:22.08#ibcon#about to write, iclass 26, count 0 2006.281.07:38:22.08#ibcon#wrote, iclass 26, count 0 2006.281.07:38:22.08#ibcon#about to read 3, iclass 26, count 0 2006.281.07:38:22.11#ibcon#read 3, iclass 26, count 0 2006.281.07:38:22.11#ibcon#about to read 4, iclass 26, count 0 2006.281.07:38:22.11#ibcon#read 4, iclass 26, count 0 2006.281.07:38:22.11#ibcon#about to read 5, iclass 26, count 0 2006.281.07:38:22.11#ibcon#read 5, iclass 26, count 0 2006.281.07:38:22.11#ibcon#about to read 6, iclass 26, count 0 2006.281.07:38:22.11#ibcon#read 6, iclass 26, count 0 2006.281.07:38:22.11#ibcon#end of sib2, iclass 26, count 0 2006.281.07:38:22.11#ibcon#*after write, iclass 26, count 0 2006.281.07:38:22.11#ibcon#*before return 0, iclass 26, count 0 2006.281.07:38:22.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:38:22.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:38:22.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:38:22.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:38:22.12$vc4f8/vb=1,4 2006.281.07:38:22.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:38:22.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:38:22.12#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:22.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:38:22.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:38:22.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:38:22.12#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:38:22.12#ibcon#first serial, iclass 28, count 2 2006.281.07:38:22.12#ibcon#enter sib2, iclass 28, count 2 2006.281.07:38:22.12#ibcon#flushed, iclass 28, count 2 2006.281.07:38:22.12#ibcon#about to write, iclass 28, count 2 2006.281.07:38:22.12#ibcon#wrote, iclass 28, count 2 2006.281.07:38:22.12#ibcon#about to read 3, iclass 28, count 2 2006.281.07:38:22.13#ibcon#read 3, iclass 28, count 2 2006.281.07:38:22.13#ibcon#about to read 4, iclass 28, count 2 2006.281.07:38:22.13#ibcon#read 4, iclass 28, count 2 2006.281.07:38:22.13#ibcon#about to read 5, iclass 28, count 2 2006.281.07:38:22.13#ibcon#read 5, iclass 28, count 2 2006.281.07:38:22.13#ibcon#about to read 6, iclass 28, count 2 2006.281.07:38:22.13#ibcon#read 6, iclass 28, count 2 2006.281.07:38:22.13#ibcon#end of sib2, iclass 28, count 2 2006.281.07:38:22.13#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:38:22.13#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:38:22.13#ibcon#[27=AT01-04\r\n] 2006.281.07:38:22.13#ibcon#*before write, iclass 28, count 2 2006.281.07:38:22.13#ibcon#enter sib2, iclass 28, count 2 2006.281.07:38:22.13#ibcon#flushed, iclass 28, count 2 2006.281.07:38:22.13#ibcon#about to write, iclass 28, count 2 2006.281.07:38:22.13#ibcon#wrote, iclass 28, count 2 2006.281.07:38:22.13#ibcon#about to read 3, iclass 28, count 2 2006.281.07:38:22.17#ibcon#read 3, iclass 28, count 2 2006.281.07:38:22.17#ibcon#about to read 4, iclass 28, count 2 2006.281.07:38:22.17#ibcon#read 4, iclass 28, count 2 2006.281.07:38:22.17#ibcon#about to read 5, iclass 28, count 2 2006.281.07:38:22.17#ibcon#read 5, iclass 28, count 2 2006.281.07:38:22.17#ibcon#about to read 6, iclass 28, count 2 2006.281.07:38:22.17#ibcon#read 6, iclass 28, count 2 2006.281.07:38:22.17#ibcon#end of sib2, iclass 28, count 2 2006.281.07:38:22.17#ibcon#*after write, iclass 28, count 2 2006.281.07:38:22.17#ibcon#*before return 0, iclass 28, count 2 2006.281.07:38:22.17#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:38:22.17#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:38:22.17#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:38:22.17#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:22.17#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:38:22.28#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:38:22.28#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:38:22.28#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:38:22.28#ibcon#first serial, iclass 28, count 0 2006.281.07:38:22.28#ibcon#enter sib2, iclass 28, count 0 2006.281.07:38:22.28#ibcon#flushed, iclass 28, count 0 2006.281.07:38:22.28#ibcon#about to write, iclass 28, count 0 2006.281.07:38:22.28#ibcon#wrote, iclass 28, count 0 2006.281.07:38:22.28#ibcon#about to read 3, iclass 28, count 0 2006.281.07:38:22.30#ibcon#read 3, iclass 28, count 0 2006.281.07:38:22.30#ibcon#about to read 4, iclass 28, count 0 2006.281.07:38:22.30#ibcon#read 4, iclass 28, count 0 2006.281.07:38:22.30#ibcon#about to read 5, iclass 28, count 0 2006.281.07:38:22.30#ibcon#read 5, iclass 28, count 0 2006.281.07:38:22.30#ibcon#about to read 6, iclass 28, count 0 2006.281.07:38:22.30#ibcon#read 6, iclass 28, count 0 2006.281.07:38:22.30#ibcon#end of sib2, iclass 28, count 0 2006.281.07:38:22.30#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:38:22.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:38:22.30#ibcon#[27=USB\r\n] 2006.281.07:38:22.30#ibcon#*before write, iclass 28, count 0 2006.281.07:38:22.30#ibcon#enter sib2, iclass 28, count 0 2006.281.07:38:22.30#ibcon#flushed, iclass 28, count 0 2006.281.07:38:22.30#ibcon#about to write, iclass 28, count 0 2006.281.07:38:22.30#ibcon#wrote, iclass 28, count 0 2006.281.07:38:22.30#ibcon#about to read 3, iclass 28, count 0 2006.281.07:38:22.33#ibcon#read 3, iclass 28, count 0 2006.281.07:38:22.33#ibcon#about to read 4, iclass 28, count 0 2006.281.07:38:22.33#ibcon#read 4, iclass 28, count 0 2006.281.07:38:22.33#ibcon#about to read 5, iclass 28, count 0 2006.281.07:38:22.33#ibcon#read 5, iclass 28, count 0 2006.281.07:38:22.33#ibcon#about to read 6, iclass 28, count 0 2006.281.07:38:22.33#ibcon#read 6, iclass 28, count 0 2006.281.07:38:22.33#ibcon#end of sib2, iclass 28, count 0 2006.281.07:38:22.33#ibcon#*after write, iclass 28, count 0 2006.281.07:38:22.33#ibcon#*before return 0, iclass 28, count 0 2006.281.07:38:22.33#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:38:22.33#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:38:22.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:38:22.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:38:22.34$vc4f8/vblo=2,640.99 2006.281.07:38:22.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:38:22.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:38:22.34#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:22.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:22.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:22.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:22.34#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:38:22.34#ibcon#first serial, iclass 30, count 0 2006.281.07:38:22.34#ibcon#enter sib2, iclass 30, count 0 2006.281.07:38:22.34#ibcon#flushed, iclass 30, count 0 2006.281.07:38:22.34#ibcon#about to write, iclass 30, count 0 2006.281.07:38:22.34#ibcon#wrote, iclass 30, count 0 2006.281.07:38:22.34#ibcon#about to read 3, iclass 30, count 0 2006.281.07:38:22.35#ibcon#read 3, iclass 30, count 0 2006.281.07:38:22.35#ibcon#about to read 4, iclass 30, count 0 2006.281.07:38:22.35#ibcon#read 4, iclass 30, count 0 2006.281.07:38:22.35#ibcon#about to read 5, iclass 30, count 0 2006.281.07:38:22.35#ibcon#read 5, iclass 30, count 0 2006.281.07:38:22.35#ibcon#about to read 6, iclass 30, count 0 2006.281.07:38:22.35#ibcon#read 6, iclass 30, count 0 2006.281.07:38:22.35#ibcon#end of sib2, iclass 30, count 0 2006.281.07:38:22.35#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:38:22.35#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:38:22.35#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:38:22.35#ibcon#*before write, iclass 30, count 0 2006.281.07:38:22.35#ibcon#enter sib2, iclass 30, count 0 2006.281.07:38:22.35#ibcon#flushed, iclass 30, count 0 2006.281.07:38:22.35#ibcon#about to write, iclass 30, count 0 2006.281.07:38:22.35#ibcon#wrote, iclass 30, count 0 2006.281.07:38:22.35#ibcon#about to read 3, iclass 30, count 0 2006.281.07:38:22.39#ibcon#read 3, iclass 30, count 0 2006.281.07:38:22.39#ibcon#about to read 4, iclass 30, count 0 2006.281.07:38:22.39#ibcon#read 4, iclass 30, count 0 2006.281.07:38:22.39#ibcon#about to read 5, iclass 30, count 0 2006.281.07:38:22.39#ibcon#read 5, iclass 30, count 0 2006.281.07:38:22.39#ibcon#about to read 6, iclass 30, count 0 2006.281.07:38:22.39#ibcon#read 6, iclass 30, count 0 2006.281.07:38:22.39#ibcon#end of sib2, iclass 30, count 0 2006.281.07:38:22.39#ibcon#*after write, iclass 30, count 0 2006.281.07:38:22.39#ibcon#*before return 0, iclass 30, count 0 2006.281.07:38:22.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:22.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:38:22.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:38:22.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:38:22.40$vc4f8/vb=2,5 2006.281.07:38:22.40#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:38:22.40#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:38:22.40#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:22.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:22.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:22.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:22.44#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:38:22.44#ibcon#first serial, iclass 32, count 2 2006.281.07:38:22.44#ibcon#enter sib2, iclass 32, count 2 2006.281.07:38:22.44#ibcon#flushed, iclass 32, count 2 2006.281.07:38:22.44#ibcon#about to write, iclass 32, count 2 2006.281.07:38:22.44#ibcon#wrote, iclass 32, count 2 2006.281.07:38:22.44#ibcon#about to read 3, iclass 32, count 2 2006.281.07:38:22.47#ibcon#read 3, iclass 32, count 2 2006.281.07:38:22.47#ibcon#about to read 4, iclass 32, count 2 2006.281.07:38:22.47#ibcon#read 4, iclass 32, count 2 2006.281.07:38:22.47#ibcon#about to read 5, iclass 32, count 2 2006.281.07:38:22.47#ibcon#read 5, iclass 32, count 2 2006.281.07:38:22.47#ibcon#about to read 6, iclass 32, count 2 2006.281.07:38:22.47#ibcon#read 6, iclass 32, count 2 2006.281.07:38:22.47#ibcon#end of sib2, iclass 32, count 2 2006.281.07:38:22.47#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:38:22.47#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:38:22.47#ibcon#[27=AT02-05\r\n] 2006.281.07:38:22.47#ibcon#*before write, iclass 32, count 2 2006.281.07:38:22.47#ibcon#enter sib2, iclass 32, count 2 2006.281.07:38:22.47#ibcon#flushed, iclass 32, count 2 2006.281.07:38:22.47#ibcon#about to write, iclass 32, count 2 2006.281.07:38:22.47#ibcon#wrote, iclass 32, count 2 2006.281.07:38:22.47#ibcon#about to read 3, iclass 32, count 2 2006.281.07:38:22.50#ibcon#read 3, iclass 32, count 2 2006.281.07:38:22.50#ibcon#about to read 4, iclass 32, count 2 2006.281.07:38:22.50#ibcon#read 4, iclass 32, count 2 2006.281.07:38:22.50#ibcon#about to read 5, iclass 32, count 2 2006.281.07:38:22.50#ibcon#read 5, iclass 32, count 2 2006.281.07:38:22.50#ibcon#about to read 6, iclass 32, count 2 2006.281.07:38:22.50#ibcon#read 6, iclass 32, count 2 2006.281.07:38:22.50#ibcon#end of sib2, iclass 32, count 2 2006.281.07:38:22.50#ibcon#*after write, iclass 32, count 2 2006.281.07:38:22.50#ibcon#*before return 0, iclass 32, count 2 2006.281.07:38:22.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:22.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:38:22.50#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:38:22.50#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:22.50#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:22.62#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:22.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:22.62#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:38:22.62#ibcon#first serial, iclass 32, count 0 2006.281.07:38:22.62#ibcon#enter sib2, iclass 32, count 0 2006.281.07:38:22.62#ibcon#flushed, iclass 32, count 0 2006.281.07:38:22.62#ibcon#about to write, iclass 32, count 0 2006.281.07:38:22.62#ibcon#wrote, iclass 32, count 0 2006.281.07:38:22.62#ibcon#about to read 3, iclass 32, count 0 2006.281.07:38:22.64#ibcon#read 3, iclass 32, count 0 2006.281.07:38:22.64#ibcon#about to read 4, iclass 32, count 0 2006.281.07:38:22.64#ibcon#read 4, iclass 32, count 0 2006.281.07:38:22.64#ibcon#about to read 5, iclass 32, count 0 2006.281.07:38:22.64#ibcon#read 5, iclass 32, count 0 2006.281.07:38:22.64#ibcon#about to read 6, iclass 32, count 0 2006.281.07:38:22.64#ibcon#read 6, iclass 32, count 0 2006.281.07:38:22.64#ibcon#end of sib2, iclass 32, count 0 2006.281.07:38:22.64#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:38:22.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:38:22.64#ibcon#[27=USB\r\n] 2006.281.07:38:22.64#ibcon#*before write, iclass 32, count 0 2006.281.07:38:22.64#ibcon#enter sib2, iclass 32, count 0 2006.281.07:38:22.64#ibcon#flushed, iclass 32, count 0 2006.281.07:38:22.64#ibcon#about to write, iclass 32, count 0 2006.281.07:38:22.64#ibcon#wrote, iclass 32, count 0 2006.281.07:38:22.64#ibcon#about to read 3, iclass 32, count 0 2006.281.07:38:22.67#ibcon#read 3, iclass 32, count 0 2006.281.07:38:22.67#ibcon#about to read 4, iclass 32, count 0 2006.281.07:38:22.67#ibcon#read 4, iclass 32, count 0 2006.281.07:38:22.67#ibcon#about to read 5, iclass 32, count 0 2006.281.07:38:22.67#ibcon#read 5, iclass 32, count 0 2006.281.07:38:22.67#ibcon#about to read 6, iclass 32, count 0 2006.281.07:38:22.67#ibcon#read 6, iclass 32, count 0 2006.281.07:38:22.67#ibcon#end of sib2, iclass 32, count 0 2006.281.07:38:22.67#ibcon#*after write, iclass 32, count 0 2006.281.07:38:22.67#ibcon#*before return 0, iclass 32, count 0 2006.281.07:38:22.67#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:22.67#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:38:22.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:38:22.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:38:22.68$vc4f8/vblo=3,656.99 2006.281.07:38:22.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:38:22.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:38:22.68#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:22.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:22.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:22.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:22.68#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:38:22.68#ibcon#first serial, iclass 34, count 0 2006.281.07:38:22.68#ibcon#enter sib2, iclass 34, count 0 2006.281.07:38:22.68#ibcon#flushed, iclass 34, count 0 2006.281.07:38:22.68#ibcon#about to write, iclass 34, count 0 2006.281.07:38:22.68#ibcon#wrote, iclass 34, count 0 2006.281.07:38:22.68#ibcon#about to read 3, iclass 34, count 0 2006.281.07:38:22.69#ibcon#read 3, iclass 34, count 0 2006.281.07:38:22.69#ibcon#about to read 4, iclass 34, count 0 2006.281.07:38:22.69#ibcon#read 4, iclass 34, count 0 2006.281.07:38:22.69#ibcon#about to read 5, iclass 34, count 0 2006.281.07:38:22.69#ibcon#read 5, iclass 34, count 0 2006.281.07:38:22.69#ibcon#about to read 6, iclass 34, count 0 2006.281.07:38:22.69#ibcon#read 6, iclass 34, count 0 2006.281.07:38:22.69#ibcon#end of sib2, iclass 34, count 0 2006.281.07:38:22.69#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:38:22.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:38:22.69#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:38:22.69#ibcon#*before write, iclass 34, count 0 2006.281.07:38:22.69#ibcon#enter sib2, iclass 34, count 0 2006.281.07:38:22.69#ibcon#flushed, iclass 34, count 0 2006.281.07:38:22.69#ibcon#about to write, iclass 34, count 0 2006.281.07:38:22.69#ibcon#wrote, iclass 34, count 0 2006.281.07:38:22.69#ibcon#about to read 3, iclass 34, count 0 2006.281.07:38:22.73#ibcon#read 3, iclass 34, count 0 2006.281.07:38:22.73#ibcon#about to read 4, iclass 34, count 0 2006.281.07:38:22.73#ibcon#read 4, iclass 34, count 0 2006.281.07:38:22.73#ibcon#about to read 5, iclass 34, count 0 2006.281.07:38:22.73#ibcon#read 5, iclass 34, count 0 2006.281.07:38:22.73#ibcon#about to read 6, iclass 34, count 0 2006.281.07:38:22.73#ibcon#read 6, iclass 34, count 0 2006.281.07:38:22.73#ibcon#end of sib2, iclass 34, count 0 2006.281.07:38:22.73#ibcon#*after write, iclass 34, count 0 2006.281.07:38:22.73#ibcon#*before return 0, iclass 34, count 0 2006.281.07:38:22.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:22.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:38:22.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:38:22.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:38:22.74$vc4f8/vb=3,4 2006.281.07:38:22.74#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:38:22.74#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:38:22.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:22.74#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:22.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:22.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:22.78#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:38:22.78#ibcon#first serial, iclass 36, count 2 2006.281.07:38:22.78#ibcon#enter sib2, iclass 36, count 2 2006.281.07:38:22.78#ibcon#flushed, iclass 36, count 2 2006.281.07:38:22.78#ibcon#about to write, iclass 36, count 2 2006.281.07:38:22.78#ibcon#wrote, iclass 36, count 2 2006.281.07:38:22.78#ibcon#about to read 3, iclass 36, count 2 2006.281.07:38:22.80#ibcon#read 3, iclass 36, count 2 2006.281.07:38:22.80#ibcon#about to read 4, iclass 36, count 2 2006.281.07:38:22.80#ibcon#read 4, iclass 36, count 2 2006.281.07:38:22.80#ibcon#about to read 5, iclass 36, count 2 2006.281.07:38:22.80#ibcon#read 5, iclass 36, count 2 2006.281.07:38:22.80#ibcon#about to read 6, iclass 36, count 2 2006.281.07:38:22.80#ibcon#read 6, iclass 36, count 2 2006.281.07:38:22.80#ibcon#end of sib2, iclass 36, count 2 2006.281.07:38:22.80#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:38:22.80#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:38:22.80#ibcon#[27=AT03-04\r\n] 2006.281.07:38:22.80#ibcon#*before write, iclass 36, count 2 2006.281.07:38:22.80#ibcon#enter sib2, iclass 36, count 2 2006.281.07:38:22.80#ibcon#flushed, iclass 36, count 2 2006.281.07:38:22.80#ibcon#about to write, iclass 36, count 2 2006.281.07:38:22.80#ibcon#wrote, iclass 36, count 2 2006.281.07:38:22.80#ibcon#about to read 3, iclass 36, count 2 2006.281.07:38:22.84#ibcon#read 3, iclass 36, count 2 2006.281.07:38:22.84#ibcon#about to read 4, iclass 36, count 2 2006.281.07:38:22.84#ibcon#read 4, iclass 36, count 2 2006.281.07:38:22.84#ibcon#about to read 5, iclass 36, count 2 2006.281.07:38:22.84#ibcon#read 5, iclass 36, count 2 2006.281.07:38:22.84#ibcon#about to read 6, iclass 36, count 2 2006.281.07:38:22.84#ibcon#read 6, iclass 36, count 2 2006.281.07:38:22.84#ibcon#end of sib2, iclass 36, count 2 2006.281.07:38:22.84#ibcon#*after write, iclass 36, count 2 2006.281.07:38:22.84#ibcon#*before return 0, iclass 36, count 2 2006.281.07:38:22.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:22.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:38:22.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:38:22.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:22.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:22.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:22.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:22.95#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:38:22.95#ibcon#first serial, iclass 36, count 0 2006.281.07:38:22.95#ibcon#enter sib2, iclass 36, count 0 2006.281.07:38:22.95#ibcon#flushed, iclass 36, count 0 2006.281.07:38:22.95#ibcon#about to write, iclass 36, count 0 2006.281.07:38:22.95#ibcon#wrote, iclass 36, count 0 2006.281.07:38:22.95#ibcon#about to read 3, iclass 36, count 0 2006.281.07:38:22.98#ibcon#read 3, iclass 36, count 0 2006.281.07:38:22.98#ibcon#about to read 4, iclass 36, count 0 2006.281.07:38:22.98#ibcon#read 4, iclass 36, count 0 2006.281.07:38:22.98#ibcon#about to read 5, iclass 36, count 0 2006.281.07:38:22.98#ibcon#read 5, iclass 36, count 0 2006.281.07:38:22.98#ibcon#about to read 6, iclass 36, count 0 2006.281.07:38:22.98#ibcon#read 6, iclass 36, count 0 2006.281.07:38:22.98#ibcon#end of sib2, iclass 36, count 0 2006.281.07:38:22.98#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:38:22.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:38:22.98#ibcon#[27=USB\r\n] 2006.281.07:38:22.98#ibcon#*before write, iclass 36, count 0 2006.281.07:38:22.98#ibcon#enter sib2, iclass 36, count 0 2006.281.07:38:22.98#ibcon#flushed, iclass 36, count 0 2006.281.07:38:22.98#ibcon#about to write, iclass 36, count 0 2006.281.07:38:22.98#ibcon#wrote, iclass 36, count 0 2006.281.07:38:22.98#ibcon#about to read 3, iclass 36, count 0 2006.281.07:38:23.00#ibcon#read 3, iclass 36, count 0 2006.281.07:38:23.00#ibcon#about to read 4, iclass 36, count 0 2006.281.07:38:23.00#ibcon#read 4, iclass 36, count 0 2006.281.07:38:23.00#ibcon#about to read 5, iclass 36, count 0 2006.281.07:38:23.00#ibcon#read 5, iclass 36, count 0 2006.281.07:38:23.00#ibcon#about to read 6, iclass 36, count 0 2006.281.07:38:23.00#ibcon#read 6, iclass 36, count 0 2006.281.07:38:23.00#ibcon#end of sib2, iclass 36, count 0 2006.281.07:38:23.00#ibcon#*after write, iclass 36, count 0 2006.281.07:38:23.00#ibcon#*before return 0, iclass 36, count 0 2006.281.07:38:23.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:23.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:38:23.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:38:23.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:38:23.01$vc4f8/vblo=4,712.99 2006.281.07:38:23.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:38:23.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:38:23.01#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:23.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:23.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:23.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:23.01#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:38:23.01#ibcon#first serial, iclass 38, count 0 2006.281.07:38:23.01#ibcon#enter sib2, iclass 38, count 0 2006.281.07:38:23.01#ibcon#flushed, iclass 38, count 0 2006.281.07:38:23.01#ibcon#about to write, iclass 38, count 0 2006.281.07:38:23.01#ibcon#wrote, iclass 38, count 0 2006.281.07:38:23.01#ibcon#about to read 3, iclass 38, count 0 2006.281.07:38:23.02#ibcon#read 3, iclass 38, count 0 2006.281.07:38:23.02#ibcon#about to read 4, iclass 38, count 0 2006.281.07:38:23.02#ibcon#read 4, iclass 38, count 0 2006.281.07:38:23.02#ibcon#about to read 5, iclass 38, count 0 2006.281.07:38:23.02#ibcon#read 5, iclass 38, count 0 2006.281.07:38:23.02#ibcon#about to read 6, iclass 38, count 0 2006.281.07:38:23.02#ibcon#read 6, iclass 38, count 0 2006.281.07:38:23.02#ibcon#end of sib2, iclass 38, count 0 2006.281.07:38:23.02#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:38:23.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:38:23.02#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:38:23.02#ibcon#*before write, iclass 38, count 0 2006.281.07:38:23.02#ibcon#enter sib2, iclass 38, count 0 2006.281.07:38:23.02#ibcon#flushed, iclass 38, count 0 2006.281.07:38:23.02#ibcon#about to write, iclass 38, count 0 2006.281.07:38:23.02#ibcon#wrote, iclass 38, count 0 2006.281.07:38:23.02#ibcon#about to read 3, iclass 38, count 0 2006.281.07:38:23.07#ibcon#read 3, iclass 38, count 0 2006.281.07:38:23.07#ibcon#about to read 4, iclass 38, count 0 2006.281.07:38:23.07#ibcon#read 4, iclass 38, count 0 2006.281.07:38:23.07#ibcon#about to read 5, iclass 38, count 0 2006.281.07:38:23.07#ibcon#read 5, iclass 38, count 0 2006.281.07:38:23.07#ibcon#about to read 6, iclass 38, count 0 2006.281.07:38:23.07#ibcon#read 6, iclass 38, count 0 2006.281.07:38:23.07#ibcon#end of sib2, iclass 38, count 0 2006.281.07:38:23.07#ibcon#*after write, iclass 38, count 0 2006.281.07:38:23.07#ibcon#*before return 0, iclass 38, count 0 2006.281.07:38:23.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:23.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:38:23.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:38:23.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:38:23.07$vc4f8/vb=4,4 2006.281.07:38:23.08#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:38:23.08#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:38:23.08#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:23.08#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:23.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:23.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:23.11#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:38:23.11#ibcon#first serial, iclass 40, count 2 2006.281.07:38:23.11#ibcon#enter sib2, iclass 40, count 2 2006.281.07:38:23.11#ibcon#flushed, iclass 40, count 2 2006.281.07:38:23.11#ibcon#about to write, iclass 40, count 2 2006.281.07:38:23.11#ibcon#wrote, iclass 40, count 2 2006.281.07:38:23.11#ibcon#about to read 3, iclass 40, count 2 2006.281.07:38:23.14#ibcon#read 3, iclass 40, count 2 2006.281.07:38:23.14#ibcon#about to read 4, iclass 40, count 2 2006.281.07:38:23.14#ibcon#read 4, iclass 40, count 2 2006.281.07:38:23.14#ibcon#about to read 5, iclass 40, count 2 2006.281.07:38:23.14#ibcon#read 5, iclass 40, count 2 2006.281.07:38:23.14#ibcon#about to read 6, iclass 40, count 2 2006.281.07:38:23.14#ibcon#read 6, iclass 40, count 2 2006.281.07:38:23.14#ibcon#end of sib2, iclass 40, count 2 2006.281.07:38:23.14#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:38:23.14#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:38:23.14#ibcon#[27=AT04-04\r\n] 2006.281.07:38:23.14#ibcon#*before write, iclass 40, count 2 2006.281.07:38:23.14#ibcon#enter sib2, iclass 40, count 2 2006.281.07:38:23.14#ibcon#flushed, iclass 40, count 2 2006.281.07:38:23.14#ibcon#about to write, iclass 40, count 2 2006.281.07:38:23.14#ibcon#wrote, iclass 40, count 2 2006.281.07:38:23.14#ibcon#about to read 3, iclass 40, count 2 2006.281.07:38:23.17#ibcon#read 3, iclass 40, count 2 2006.281.07:38:23.17#ibcon#about to read 4, iclass 40, count 2 2006.281.07:38:23.17#ibcon#read 4, iclass 40, count 2 2006.281.07:38:23.17#ibcon#about to read 5, iclass 40, count 2 2006.281.07:38:23.17#ibcon#read 5, iclass 40, count 2 2006.281.07:38:23.17#ibcon#about to read 6, iclass 40, count 2 2006.281.07:38:23.17#ibcon#read 6, iclass 40, count 2 2006.281.07:38:23.17#ibcon#end of sib2, iclass 40, count 2 2006.281.07:38:23.17#ibcon#*after write, iclass 40, count 2 2006.281.07:38:23.17#ibcon#*before return 0, iclass 40, count 2 2006.281.07:38:23.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:23.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:38:23.17#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:38:23.17#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:23.17#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:23.29#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:23.29#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:23.29#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:38:23.29#ibcon#first serial, iclass 40, count 0 2006.281.07:38:23.29#ibcon#enter sib2, iclass 40, count 0 2006.281.07:38:23.29#ibcon#flushed, iclass 40, count 0 2006.281.07:38:23.29#ibcon#about to write, iclass 40, count 0 2006.281.07:38:23.29#ibcon#wrote, iclass 40, count 0 2006.281.07:38:23.29#ibcon#about to read 3, iclass 40, count 0 2006.281.07:38:23.31#ibcon#read 3, iclass 40, count 0 2006.281.07:38:23.31#ibcon#about to read 4, iclass 40, count 0 2006.281.07:38:23.31#ibcon#read 4, iclass 40, count 0 2006.281.07:38:23.31#ibcon#about to read 5, iclass 40, count 0 2006.281.07:38:23.31#ibcon#read 5, iclass 40, count 0 2006.281.07:38:23.31#ibcon#about to read 6, iclass 40, count 0 2006.281.07:38:23.31#ibcon#read 6, iclass 40, count 0 2006.281.07:38:23.31#ibcon#end of sib2, iclass 40, count 0 2006.281.07:38:23.31#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:38:23.31#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:38:23.31#ibcon#[27=USB\r\n] 2006.281.07:38:23.31#ibcon#*before write, iclass 40, count 0 2006.281.07:38:23.31#ibcon#enter sib2, iclass 40, count 0 2006.281.07:38:23.31#ibcon#flushed, iclass 40, count 0 2006.281.07:38:23.31#ibcon#about to write, iclass 40, count 0 2006.281.07:38:23.31#ibcon#wrote, iclass 40, count 0 2006.281.07:38:23.31#ibcon#about to read 3, iclass 40, count 0 2006.281.07:38:23.34#ibcon#read 3, iclass 40, count 0 2006.281.07:38:23.34#ibcon#about to read 4, iclass 40, count 0 2006.281.07:38:23.34#ibcon#read 4, iclass 40, count 0 2006.281.07:38:23.34#ibcon#about to read 5, iclass 40, count 0 2006.281.07:38:23.34#ibcon#read 5, iclass 40, count 0 2006.281.07:38:23.34#ibcon#about to read 6, iclass 40, count 0 2006.281.07:38:23.34#ibcon#read 6, iclass 40, count 0 2006.281.07:38:23.34#ibcon#end of sib2, iclass 40, count 0 2006.281.07:38:23.34#ibcon#*after write, iclass 40, count 0 2006.281.07:38:23.34#ibcon#*before return 0, iclass 40, count 0 2006.281.07:38:23.34#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:23.34#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:38:23.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:38:23.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:38:23.35$vc4f8/vblo=5,744.99 2006.281.07:38:23.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:38:23.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:38:23.35#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:23.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:23.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:23.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:23.35#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:38:23.35#ibcon#first serial, iclass 4, count 0 2006.281.07:38:23.35#ibcon#enter sib2, iclass 4, count 0 2006.281.07:38:23.35#ibcon#flushed, iclass 4, count 0 2006.281.07:38:23.35#ibcon#about to write, iclass 4, count 0 2006.281.07:38:23.35#ibcon#wrote, iclass 4, count 0 2006.281.07:38:23.35#ibcon#about to read 3, iclass 4, count 0 2006.281.07:38:23.36#ibcon#read 3, iclass 4, count 0 2006.281.07:38:23.37#ibcon#about to read 4, iclass 4, count 0 2006.281.07:38:23.37#ibcon#read 4, iclass 4, count 0 2006.281.07:38:23.37#ibcon#about to read 5, iclass 4, count 0 2006.281.07:38:23.37#ibcon#read 5, iclass 4, count 0 2006.281.07:38:23.37#ibcon#about to read 6, iclass 4, count 0 2006.281.07:38:23.37#ibcon#read 6, iclass 4, count 0 2006.281.07:38:23.37#ibcon#end of sib2, iclass 4, count 0 2006.281.07:38:23.37#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:38:23.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:38:23.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:38:23.37#ibcon#*before write, iclass 4, count 0 2006.281.07:38:23.37#ibcon#enter sib2, iclass 4, count 0 2006.281.07:38:23.37#ibcon#flushed, iclass 4, count 0 2006.281.07:38:23.37#ibcon#about to write, iclass 4, count 0 2006.281.07:38:23.37#ibcon#wrote, iclass 4, count 0 2006.281.07:38:23.37#ibcon#about to read 3, iclass 4, count 0 2006.281.07:38:23.41#ibcon#read 3, iclass 4, count 0 2006.281.07:38:23.41#ibcon#about to read 4, iclass 4, count 0 2006.281.07:38:23.41#ibcon#read 4, iclass 4, count 0 2006.281.07:38:23.41#ibcon#about to read 5, iclass 4, count 0 2006.281.07:38:23.41#ibcon#read 5, iclass 4, count 0 2006.281.07:38:23.41#ibcon#about to read 6, iclass 4, count 0 2006.281.07:38:23.41#ibcon#read 6, iclass 4, count 0 2006.281.07:38:23.41#ibcon#end of sib2, iclass 4, count 0 2006.281.07:38:23.42#ibcon#*after write, iclass 4, count 0 2006.281.07:38:23.42#ibcon#*before return 0, iclass 4, count 0 2006.281.07:38:23.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:23.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:38:23.42#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:38:23.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:38:23.42$vc4f8/vb=5,4 2006.281.07:38:23.42#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:38:23.42#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:38:23.42#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:23.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:23.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:23.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:23.45#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:38:23.45#ibcon#first serial, iclass 6, count 2 2006.281.07:38:23.45#ibcon#enter sib2, iclass 6, count 2 2006.281.07:38:23.45#ibcon#flushed, iclass 6, count 2 2006.281.07:38:23.45#ibcon#about to write, iclass 6, count 2 2006.281.07:38:23.45#ibcon#wrote, iclass 6, count 2 2006.281.07:38:23.45#ibcon#about to read 3, iclass 6, count 2 2006.281.07:38:23.47#ibcon#read 3, iclass 6, count 2 2006.281.07:38:23.47#ibcon#about to read 4, iclass 6, count 2 2006.281.07:38:23.47#ibcon#read 4, iclass 6, count 2 2006.281.07:38:23.47#ibcon#about to read 5, iclass 6, count 2 2006.281.07:38:23.47#ibcon#read 5, iclass 6, count 2 2006.281.07:38:23.47#ibcon#about to read 6, iclass 6, count 2 2006.281.07:38:23.47#ibcon#read 6, iclass 6, count 2 2006.281.07:38:23.47#ibcon#end of sib2, iclass 6, count 2 2006.281.07:38:23.47#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:38:23.47#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:38:23.47#ibcon#[27=AT05-04\r\n] 2006.281.07:38:23.47#ibcon#*before write, iclass 6, count 2 2006.281.07:38:23.47#ibcon#enter sib2, iclass 6, count 2 2006.281.07:38:23.47#ibcon#flushed, iclass 6, count 2 2006.281.07:38:23.47#ibcon#about to write, iclass 6, count 2 2006.281.07:38:23.47#ibcon#wrote, iclass 6, count 2 2006.281.07:38:23.47#ibcon#about to read 3, iclass 6, count 2 2006.281.07:38:23.50#ibcon#read 3, iclass 6, count 2 2006.281.07:38:23.50#ibcon#about to read 4, iclass 6, count 2 2006.281.07:38:23.50#ibcon#read 4, iclass 6, count 2 2006.281.07:38:23.50#ibcon#about to read 5, iclass 6, count 2 2006.281.07:38:23.50#ibcon#read 5, iclass 6, count 2 2006.281.07:38:23.50#ibcon#about to read 6, iclass 6, count 2 2006.281.07:38:23.50#ibcon#read 6, iclass 6, count 2 2006.281.07:38:23.50#ibcon#end of sib2, iclass 6, count 2 2006.281.07:38:23.50#ibcon#*after write, iclass 6, count 2 2006.281.07:38:23.50#ibcon#*before return 0, iclass 6, count 2 2006.281.07:38:23.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:23.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:38:23.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:38:23.50#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:23.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:23.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:23.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:23.63#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:38:23.63#ibcon#first serial, iclass 6, count 0 2006.281.07:38:23.63#ibcon#enter sib2, iclass 6, count 0 2006.281.07:38:23.63#ibcon#flushed, iclass 6, count 0 2006.281.07:38:23.63#ibcon#about to write, iclass 6, count 0 2006.281.07:38:23.63#ibcon#wrote, iclass 6, count 0 2006.281.07:38:23.63#ibcon#about to read 3, iclass 6, count 0 2006.281.07:38:23.64#ibcon#read 3, iclass 6, count 0 2006.281.07:38:23.64#ibcon#about to read 4, iclass 6, count 0 2006.281.07:38:23.64#ibcon#read 4, iclass 6, count 0 2006.281.07:38:23.64#ibcon#about to read 5, iclass 6, count 0 2006.281.07:38:23.64#ibcon#read 5, iclass 6, count 0 2006.281.07:38:23.64#ibcon#about to read 6, iclass 6, count 0 2006.281.07:38:23.64#ibcon#read 6, iclass 6, count 0 2006.281.07:38:23.64#ibcon#end of sib2, iclass 6, count 0 2006.281.07:38:23.64#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:38:23.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:38:23.64#ibcon#[27=USB\r\n] 2006.281.07:38:23.64#ibcon#*before write, iclass 6, count 0 2006.281.07:38:23.64#ibcon#enter sib2, iclass 6, count 0 2006.281.07:38:23.64#ibcon#flushed, iclass 6, count 0 2006.281.07:38:23.64#ibcon#about to write, iclass 6, count 0 2006.281.07:38:23.64#ibcon#wrote, iclass 6, count 0 2006.281.07:38:23.64#ibcon#about to read 3, iclass 6, count 0 2006.281.07:38:23.67#ibcon#read 3, iclass 6, count 0 2006.281.07:38:23.67#ibcon#about to read 4, iclass 6, count 0 2006.281.07:38:23.67#ibcon#read 4, iclass 6, count 0 2006.281.07:38:23.67#ibcon#about to read 5, iclass 6, count 0 2006.281.07:38:23.67#ibcon#read 5, iclass 6, count 0 2006.281.07:38:23.67#ibcon#about to read 6, iclass 6, count 0 2006.281.07:38:23.67#ibcon#read 6, iclass 6, count 0 2006.281.07:38:23.67#ibcon#end of sib2, iclass 6, count 0 2006.281.07:38:23.67#ibcon#*after write, iclass 6, count 0 2006.281.07:38:23.67#ibcon#*before return 0, iclass 6, count 0 2006.281.07:38:23.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:23.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:38:23.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:38:23.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:38:23.68$vc4f8/vblo=6,752.99 2006.281.07:38:23.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:38:23.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:38:23.68#ibcon#ireg 17 cls_cnt 0 2006.281.07:38:23.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:23.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:23.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:23.68#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:38:23.68#ibcon#first serial, iclass 10, count 0 2006.281.07:38:23.68#ibcon#enter sib2, iclass 10, count 0 2006.281.07:38:23.68#ibcon#flushed, iclass 10, count 0 2006.281.07:38:23.68#ibcon#about to write, iclass 10, count 0 2006.281.07:38:23.68#ibcon#wrote, iclass 10, count 0 2006.281.07:38:23.68#ibcon#about to read 3, iclass 10, count 0 2006.281.07:38:23.69#ibcon#read 3, iclass 10, count 0 2006.281.07:38:23.69#ibcon#about to read 4, iclass 10, count 0 2006.281.07:38:23.69#ibcon#read 4, iclass 10, count 0 2006.281.07:38:23.69#ibcon#about to read 5, iclass 10, count 0 2006.281.07:38:23.69#ibcon#read 5, iclass 10, count 0 2006.281.07:38:23.69#ibcon#about to read 6, iclass 10, count 0 2006.281.07:38:23.69#ibcon#read 6, iclass 10, count 0 2006.281.07:38:23.69#ibcon#end of sib2, iclass 10, count 0 2006.281.07:38:23.69#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:38:23.69#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:38:23.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:38:23.69#ibcon#*before write, iclass 10, count 0 2006.281.07:38:23.69#ibcon#enter sib2, iclass 10, count 0 2006.281.07:38:23.69#ibcon#flushed, iclass 10, count 0 2006.281.07:38:23.69#ibcon#about to write, iclass 10, count 0 2006.281.07:38:23.69#ibcon#wrote, iclass 10, count 0 2006.281.07:38:23.69#ibcon#about to read 3, iclass 10, count 0 2006.281.07:38:23.74#ibcon#read 3, iclass 10, count 0 2006.281.07:38:23.74#ibcon#about to read 4, iclass 10, count 0 2006.281.07:38:23.74#ibcon#read 4, iclass 10, count 0 2006.281.07:38:23.74#ibcon#about to read 5, iclass 10, count 0 2006.281.07:38:23.74#ibcon#read 5, iclass 10, count 0 2006.281.07:38:23.74#ibcon#about to read 6, iclass 10, count 0 2006.281.07:38:23.74#ibcon#read 6, iclass 10, count 0 2006.281.07:38:23.74#ibcon#end of sib2, iclass 10, count 0 2006.281.07:38:23.74#ibcon#*after write, iclass 10, count 0 2006.281.07:38:23.74#ibcon#*before return 0, iclass 10, count 0 2006.281.07:38:23.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:23.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:38:23.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:38:23.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:38:23.74$vc4f8/vb=6,4 2006.281.07:38:23.74#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:38:23.74#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:38:23.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:38:23.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:23.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:23.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:23.78#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:38:23.78#ibcon#first serial, iclass 12, count 2 2006.281.07:38:23.78#ibcon#enter sib2, iclass 12, count 2 2006.281.07:38:23.78#ibcon#flushed, iclass 12, count 2 2006.281.07:38:23.78#ibcon#about to write, iclass 12, count 2 2006.281.07:38:23.78#ibcon#wrote, iclass 12, count 2 2006.281.07:38:23.78#ibcon#about to read 3, iclass 12, count 2 2006.281.07:38:23.80#ibcon#read 3, iclass 12, count 2 2006.281.07:38:23.80#ibcon#about to read 4, iclass 12, count 2 2006.281.07:38:23.80#ibcon#read 4, iclass 12, count 2 2006.281.07:38:23.80#ibcon#about to read 5, iclass 12, count 2 2006.281.07:38:23.80#ibcon#read 5, iclass 12, count 2 2006.281.07:38:23.80#ibcon#about to read 6, iclass 12, count 2 2006.281.07:38:23.80#ibcon#read 6, iclass 12, count 2 2006.281.07:38:23.80#ibcon#end of sib2, iclass 12, count 2 2006.281.07:38:23.80#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:38:23.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:38:23.80#ibcon#[27=AT06-04\r\n] 2006.281.07:38:23.80#ibcon#*before write, iclass 12, count 2 2006.281.07:38:23.80#ibcon#enter sib2, iclass 12, count 2 2006.281.07:38:23.80#ibcon#flushed, iclass 12, count 2 2006.281.07:38:23.80#ibcon#about to write, iclass 12, count 2 2006.281.07:38:23.80#ibcon#wrote, iclass 12, count 2 2006.281.07:38:23.80#ibcon#about to read 3, iclass 12, count 2 2006.281.07:38:23.83#ibcon#read 3, iclass 12, count 2 2006.281.07:38:23.83#ibcon#about to read 4, iclass 12, count 2 2006.281.07:38:23.83#ibcon#read 4, iclass 12, count 2 2006.281.07:38:23.83#ibcon#about to read 5, iclass 12, count 2 2006.281.07:38:23.83#ibcon#read 5, iclass 12, count 2 2006.281.07:38:23.83#ibcon#about to read 6, iclass 12, count 2 2006.281.07:38:23.83#ibcon#read 6, iclass 12, count 2 2006.281.07:38:23.83#ibcon#end of sib2, iclass 12, count 2 2006.281.07:38:23.83#ibcon#*after write, iclass 12, count 2 2006.281.07:38:23.83#ibcon#*before return 0, iclass 12, count 2 2006.281.07:38:23.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:23.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:38:23.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:38:23.83#ibcon#ireg 7 cls_cnt 0 2006.281.07:38:23.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:23.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:23.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:23.95#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:38:23.95#ibcon#first serial, iclass 12, count 0 2006.281.07:38:23.95#ibcon#enter sib2, iclass 12, count 0 2006.281.07:38:23.95#ibcon#flushed, iclass 12, count 0 2006.281.07:38:23.95#ibcon#about to write, iclass 12, count 0 2006.281.07:38:23.95#ibcon#wrote, iclass 12, count 0 2006.281.07:38:23.95#ibcon#about to read 3, iclass 12, count 0 2006.281.07:38:23.97#ibcon#read 3, iclass 12, count 0 2006.281.07:38:23.97#ibcon#about to read 4, iclass 12, count 0 2006.281.07:38:23.97#ibcon#read 4, iclass 12, count 0 2006.281.07:38:23.97#ibcon#about to read 5, iclass 12, count 0 2006.281.07:38:23.97#ibcon#read 5, iclass 12, count 0 2006.281.07:38:23.97#ibcon#about to read 6, iclass 12, count 0 2006.281.07:38:23.97#ibcon#read 6, iclass 12, count 0 2006.281.07:38:23.97#ibcon#end of sib2, iclass 12, count 0 2006.281.07:38:23.97#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:38:23.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:38:23.97#ibcon#[27=USB\r\n] 2006.281.07:38:23.97#ibcon#*before write, iclass 12, count 0 2006.281.07:38:23.97#ibcon#enter sib2, iclass 12, count 0 2006.281.07:38:23.97#ibcon#flushed, iclass 12, count 0 2006.281.07:38:23.97#ibcon#about to write, iclass 12, count 0 2006.281.07:38:23.97#ibcon#wrote, iclass 12, count 0 2006.281.07:38:23.97#ibcon#about to read 3, iclass 12, count 0 2006.281.07:38:24.00#ibcon#read 3, iclass 12, count 0 2006.281.07:38:24.00#ibcon#about to read 4, iclass 12, count 0 2006.281.07:38:24.00#ibcon#read 4, iclass 12, count 0 2006.281.07:38:24.00#ibcon#about to read 5, iclass 12, count 0 2006.281.07:38:24.00#ibcon#read 5, iclass 12, count 0 2006.281.07:38:24.00#ibcon#about to read 6, iclass 12, count 0 2006.281.07:38:24.00#ibcon#read 6, iclass 12, count 0 2006.281.07:38:24.00#ibcon#end of sib2, iclass 12, count 0 2006.281.07:38:24.00#ibcon#*after write, iclass 12, count 0 2006.281.07:38:24.00#ibcon#*before return 0, iclass 12, count 0 2006.281.07:38:24.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:24.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:38:24.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:38:24.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:38:24.01$vc4f8/vabw=wide 2006.281.07:38:24.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:38:24.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:38:24.01#ibcon#ireg 8 cls_cnt 0 2006.281.07:38:24.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:38:24.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:38:24.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:38:24.01#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:38:24.01#ibcon#first serial, iclass 15, count 0 2006.281.07:38:24.01#ibcon#enter sib2, iclass 15, count 0 2006.281.07:38:24.01#ibcon#flushed, iclass 15, count 0 2006.281.07:38:24.01#ibcon#about to write, iclass 15, count 0 2006.281.07:38:24.01#ibcon#wrote, iclass 15, count 0 2006.281.07:38:24.01#ibcon#about to read 3, iclass 15, count 0 2006.281.07:38:24.01#abcon#<5=/12 2.510.2 21.23 501001.1\r\n> 2006.281.07:38:24.02#ibcon#read 3, iclass 15, count 0 2006.281.07:38:24.02#ibcon#about to read 4, iclass 15, count 0 2006.281.07:38:24.02#ibcon#read 4, iclass 15, count 0 2006.281.07:38:24.02#ibcon#about to read 5, iclass 15, count 0 2006.281.07:38:24.02#ibcon#read 5, iclass 15, count 0 2006.281.07:38:24.02#ibcon#about to read 6, iclass 15, count 0 2006.281.07:38:24.02#ibcon#read 6, iclass 15, count 0 2006.281.07:38:24.02#ibcon#end of sib2, iclass 15, count 0 2006.281.07:38:24.02#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:38:24.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:38:24.02#ibcon#[25=BW32\r\n] 2006.281.07:38:24.02#ibcon#*before write, iclass 15, count 0 2006.281.07:38:24.02#ibcon#enter sib2, iclass 15, count 0 2006.281.07:38:24.02#ibcon#flushed, iclass 15, count 0 2006.281.07:38:24.02#ibcon#about to write, iclass 15, count 0 2006.281.07:38:24.02#ibcon#wrote, iclass 15, count 0 2006.281.07:38:24.02#ibcon#about to read 3, iclass 15, count 0 2006.281.07:38:24.03#abcon#{5=INTERFACE CLEAR} 2006.281.07:38:24.06#ibcon#read 3, iclass 15, count 0 2006.281.07:38:24.06#ibcon#about to read 4, iclass 15, count 0 2006.281.07:38:24.06#ibcon#read 4, iclass 15, count 0 2006.281.07:38:24.06#ibcon#about to read 5, iclass 15, count 0 2006.281.07:38:24.06#ibcon#read 5, iclass 15, count 0 2006.281.07:38:24.06#ibcon#about to read 6, iclass 15, count 0 2006.281.07:38:24.06#ibcon#read 6, iclass 15, count 0 2006.281.07:38:24.06#ibcon#end of sib2, iclass 15, count 0 2006.281.07:38:24.06#ibcon#*after write, iclass 15, count 0 2006.281.07:38:24.06#ibcon#*before return 0, iclass 15, count 0 2006.281.07:38:24.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:38:24.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:38:24.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:38:24.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:38:24.08$vc4f8/vbbw=wide 2006.281.07:38:24.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:38:24.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:38:24.08#ibcon#ireg 8 cls_cnt 0 2006.281.07:38:24.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:38:24.09#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:38:24.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:38:24.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:38:24.11#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:38:24.11#ibcon#first serial, iclass 19, count 0 2006.281.07:38:24.11#ibcon#enter sib2, iclass 19, count 0 2006.281.07:38:24.11#ibcon#flushed, iclass 19, count 0 2006.281.07:38:24.11#ibcon#about to write, iclass 19, count 0 2006.281.07:38:24.11#ibcon#wrote, iclass 19, count 0 2006.281.07:38:24.11#ibcon#about to read 3, iclass 19, count 0 2006.281.07:38:24.13#ibcon#read 3, iclass 19, count 0 2006.281.07:38:24.13#ibcon#about to read 4, iclass 19, count 0 2006.281.07:38:24.13#ibcon#read 4, iclass 19, count 0 2006.281.07:38:24.13#ibcon#about to read 5, iclass 19, count 0 2006.281.07:38:24.13#ibcon#read 5, iclass 19, count 0 2006.281.07:38:24.13#ibcon#about to read 6, iclass 19, count 0 2006.281.07:38:24.13#ibcon#read 6, iclass 19, count 0 2006.281.07:38:24.13#ibcon#end of sib2, iclass 19, count 0 2006.281.07:38:24.13#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:38:24.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:38:24.13#ibcon#[27=BW32\r\n] 2006.281.07:38:24.13#ibcon#*before write, iclass 19, count 0 2006.281.07:38:24.13#ibcon#enter sib2, iclass 19, count 0 2006.281.07:38:24.13#ibcon#flushed, iclass 19, count 0 2006.281.07:38:24.13#ibcon#about to write, iclass 19, count 0 2006.281.07:38:24.13#ibcon#wrote, iclass 19, count 0 2006.281.07:38:24.13#ibcon#about to read 3, iclass 19, count 0 2006.281.07:38:24.17#ibcon#read 3, iclass 19, count 0 2006.281.07:38:24.17#ibcon#about to read 4, iclass 19, count 0 2006.281.07:38:24.17#ibcon#read 4, iclass 19, count 0 2006.281.07:38:24.17#ibcon#about to read 5, iclass 19, count 0 2006.281.07:38:24.17#ibcon#read 5, iclass 19, count 0 2006.281.07:38:24.17#ibcon#about to read 6, iclass 19, count 0 2006.281.07:38:24.17#ibcon#read 6, iclass 19, count 0 2006.281.07:38:24.17#ibcon#end of sib2, iclass 19, count 0 2006.281.07:38:24.17#ibcon#*after write, iclass 19, count 0 2006.281.07:38:24.17#ibcon#*before return 0, iclass 19, count 0 2006.281.07:38:24.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:38:24.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:38:24.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:38:24.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:38:24.17$4f8m12a/ifd4f 2006.281.07:38:24.17$ifd4f/lo= 2006.281.07:38:24.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:38:24.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:38:24.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:38:24.17$ifd4f/patch= 2006.281.07:38:24.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:38:24.19$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:38:24.19$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:38:24.19$4f8m12a/"form=m,16.000,1:2 2006.281.07:38:24.19$4f8m12a/"tpicd 2006.281.07:38:24.19$4f8m12a/echo=off 2006.281.07:38:24.19$4f8m12a/xlog=off 2006.281.07:38:24.19:!2006.281.07:38:50 2006.281.07:38:37.14#trakl#Source acquired 2006.281.07:38:37.14#flagr#flagr/antenna,acquired 2006.281.07:38:41.14#trakl#Off source 2006.281.07:38:41.14?ERROR st -7 Antenna off-source! 2006.281.07:38:41.14#trakl#az 349.924 el 33.104 azerr*cos(el) 0.0167 elerr -0.0045 2006.281.07:38:43.14#flagr#flagr/antenna,off-source 2006.281.07:38:47.14#trakl#Source re-acquired 2006.281.07:38:48.14#trakl#Off source 2006.281.07:38:48.14?ERROR st -7 Antenna off-source! 2006.281.07:38:48.14#trakl#az 349.926 el 33.099 azerr*cos(el) -0.0043 elerr 0.0186 2006.281.07:38:50.01:preob 2006.281.07:38:51.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:38:51.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:38:51.15/onsource/SLEWING 2006.281.07:38:51.15:!2006.281.07:39:00 2006.281.07:38:54.14#trakl#Source re-acquired 2006.281.07:38:56.14#flagr#flagr/antenna,re-acquired 2006.281.07:39:00.01:data_valid=on 2006.281.07:39:00.02:midob 2006.281.07:39:00.14#trakl#Off source 2006.281.07:39:00.14?ERROR st -7 Antenna off-source! 2006.281.07:39:00.14#trakl#az 349.930 el 33.092 azerr*cos(el) -0.0022 elerr 0.0227 2006.281.07:39:01.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:39:01.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:39:01.14/onsource/SLEWING 2006.281.07:39:01.15/wx/21.21,1001.1,50 2006.281.07:39:01.30/cable/+6.4869E-03 2006.281.07:39:02.14#flagr#flagr/antenna,off-source 2006.281.07:39:02.39/va/01,07,usb,yes,33,34 2006.281.07:39:02.39/va/02,06,usb,yes,30,32 2006.281.07:39:02.39/va/03,06,usb,yes,29,29 2006.281.07:39:02.39/va/04,06,usb,yes,31,34 2006.281.07:39:02.39/va/05,07,usb,yes,29,31 2006.281.07:39:02.39/va/06,06,usb,yes,28,28 2006.281.07:39:02.39/va/07,06,usb,yes,28,28 2006.281.07:39:02.39/va/08,06,usb,yes,30,30 2006.281.07:39:02.62/valo/01,532.99,yes,locked 2006.281.07:39:02.62/valo/02,572.99,yes,locked 2006.281.07:39:02.62/valo/03,672.99,yes,locked 2006.281.07:39:02.62/valo/04,832.99,yes,locked 2006.281.07:39:02.62/valo/05,652.99,yes,locked 2006.281.07:39:02.62/valo/06,772.99,yes,locked 2006.281.07:39:02.62/valo/07,832.99,yes,locked 2006.281.07:39:02.62/valo/08,852.99,yes,locked 2006.281.07:39:03.71/vb/01,04,usb,yes,30,29 2006.281.07:39:03.71/vb/02,05,usb,yes,28,30 2006.281.07:39:03.71/vb/03,04,usb,yes,29,33 2006.281.07:39:03.71/vb/04,04,usb,yes,29,30 2006.281.07:39:03.71/vb/05,04,usb,yes,27,32 2006.281.07:39:03.71/vb/06,04,usb,yes,28,31 2006.281.07:39:03.71/vb/07,04,usb,yes,31,31 2006.281.07:39:03.71/vb/08,04,usb,yes,28,32 2006.281.07:39:03.94/vblo/01,632.99,yes,locked 2006.281.07:39:03.94/vblo/02,640.99,yes,locked 2006.281.07:39:03.94/vblo/03,656.99,yes,locked 2006.281.07:39:03.94/vblo/04,712.99,yes,locked 2006.281.07:39:03.94/vblo/05,744.99,yes,locked 2006.281.07:39:03.94/vblo/06,752.99,yes,locked 2006.281.07:39:03.94/vblo/07,734.99,yes,locked 2006.281.07:39:03.94/vblo/08,744.99,yes,locked 2006.281.07:39:04.09/vabw/8 2006.281.07:39:04.24/vbbw/8 2006.281.07:39:04.33/xfe/off,on,12.2 2006.281.07:39:04.71/ifatt/23,28,28,28 2006.281.07:39:05.07/fmout-gps/S +3.07E-07 2006.281.07:39:05.10:!2006.281.07:40:00 2006.281.07:39:10.14#trakl#Source re-acquired 2006.281.07:39:12.14#flagr#flagr/antenna,re-acquired 2006.281.07:39:19.14#trakl#Off source 2006.281.07:39:19.14?ERROR st -7 Antenna off-source! 2006.281.07:39:19.14#trakl#az 349.935 el 33.081 azerr*cos(el) -0.0036 elerr 0.0169 2006.281.07:39:21.14#flagr#flagr/antenna,off-source 2006.281.07:39:34.14#trakl#Off source 2006.281.07:39:34.14?ERROR st -7 Antenna off-source! 2006.281.07:39:34.14#trakl#az 349.940 el 33.072 azerr*cos(el) 0.0086 elerr -0.0063 2006.281.07:39:37.14#trakl#Source re-acquired 2006.281.07:39:39.14#flagr#flagr/antenna,re-acquired 2006.281.07:39:57.14#trakl#Off source 2006.281.07:39:57.14?ERROR st -7 Antenna off-source! 2006.281.07:39:57.14#trakl#az 349.946 el 33.059 azerr*cos(el) -0.0046 elerr 0.0232 2006.281.07:39:57.14#flagr#flagr/antenna,off-source 2006.281.07:40:00.01:data_valid=off 2006.281.07:40:00.02:postob 2006.281.07:40:00.15/cable/+6.4861E-03 2006.281.07:40:00.16/wx/21.17,1001.1,49 2006.281.07:40:01.07/fmout-gps/S +3.07E-07 2006.281.07:40:01.08:scan_name=281-0740,k06281,60 2006.281.07:40:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.281.07:40:02.14#flagr#flagr/antenna,new-source 2006.281.07:40:02.15:checkk5 2006.281.07:40:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:40:02.97/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:40:03.41/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:40:03.80/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:40:04.26/chk_obsdata//k5ts1/T2810739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:40:04.68/chk_obsdata//k5ts2/T2810739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:40:05.09/chk_obsdata//k5ts3/T2810739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:40:05.53/chk_obsdata//k5ts4/T2810739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:40:06.58/k5log//k5ts1_log_newline 2006.281.07:40:07.54/k5log//k5ts2_log_newline 2006.281.07:40:08.55/k5log//k5ts3_log_newline 2006.281.07:40:09.31/k5log//k5ts4_log_newline 2006.281.07:40:09.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:40:09.33:4f8m12a=1 2006.281.07:40:09.33$4f8m12a/echo=on 2006.281.07:40:09.33$4f8m12a/pcalon 2006.281.07:40:09.33$pcalon/"no phase cal control is implemented here 2006.281.07:40:09.34$4f8m12a/"tpicd=stop 2006.281.07:40:09.34$4f8m12a/vc4f8 2006.281.07:40:09.34$vc4f8/valo=1,532.99 2006.281.07:40:09.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:40:09.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:40:09.35#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:09.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:09.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:09.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:09.35#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:40:09.35#ibcon#first serial, iclass 11, count 0 2006.281.07:40:09.35#ibcon#enter sib2, iclass 11, count 0 2006.281.07:40:09.35#ibcon#flushed, iclass 11, count 0 2006.281.07:40:09.35#ibcon#about to write, iclass 11, count 0 2006.281.07:40:09.35#ibcon#wrote, iclass 11, count 0 2006.281.07:40:09.35#ibcon#about to read 3, iclass 11, count 0 2006.281.07:40:09.36#ibcon#read 3, iclass 11, count 0 2006.281.07:40:09.36#ibcon#about to read 4, iclass 11, count 0 2006.281.07:40:09.36#ibcon#read 4, iclass 11, count 0 2006.281.07:40:09.36#ibcon#about to read 5, iclass 11, count 0 2006.281.07:40:09.36#ibcon#read 5, iclass 11, count 0 2006.281.07:40:09.36#ibcon#about to read 6, iclass 11, count 0 2006.281.07:40:09.36#ibcon#read 6, iclass 11, count 0 2006.281.07:40:09.36#ibcon#end of sib2, iclass 11, count 0 2006.281.07:40:09.36#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:40:09.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:40:09.36#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:40:09.36#ibcon#*before write, iclass 11, count 0 2006.281.07:40:09.36#ibcon#enter sib2, iclass 11, count 0 2006.281.07:40:09.36#ibcon#flushed, iclass 11, count 0 2006.281.07:40:09.36#ibcon#about to write, iclass 11, count 0 2006.281.07:40:09.36#ibcon#wrote, iclass 11, count 0 2006.281.07:40:09.36#ibcon#about to read 3, iclass 11, count 0 2006.281.07:40:09.41#ibcon#read 3, iclass 11, count 0 2006.281.07:40:09.41#ibcon#about to read 4, iclass 11, count 0 2006.281.07:40:09.41#ibcon#read 4, iclass 11, count 0 2006.281.07:40:09.41#ibcon#about to read 5, iclass 11, count 0 2006.281.07:40:09.41#ibcon#read 5, iclass 11, count 0 2006.281.07:40:09.41#ibcon#about to read 6, iclass 11, count 0 2006.281.07:40:09.41#ibcon#read 6, iclass 11, count 0 2006.281.07:40:09.41#ibcon#end of sib2, iclass 11, count 0 2006.281.07:40:09.41#ibcon#*after write, iclass 11, count 0 2006.281.07:40:09.41#ibcon#*before return 0, iclass 11, count 0 2006.281.07:40:09.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:09.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:09.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:40:09.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:40:09.41$vc4f8/va=1,7 2006.281.07:40:09.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:40:09.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:40:09.42#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:09.42#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:09.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:09.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:09.42#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:40:09.42#ibcon#first serial, iclass 13, count 2 2006.281.07:40:09.42#ibcon#enter sib2, iclass 13, count 2 2006.281.07:40:09.42#ibcon#flushed, iclass 13, count 2 2006.281.07:40:09.42#ibcon#about to write, iclass 13, count 2 2006.281.07:40:09.42#ibcon#wrote, iclass 13, count 2 2006.281.07:40:09.42#ibcon#about to read 3, iclass 13, count 2 2006.281.07:40:09.43#ibcon#read 3, iclass 13, count 2 2006.281.07:40:09.43#ibcon#about to read 4, iclass 13, count 2 2006.281.07:40:09.43#ibcon#read 4, iclass 13, count 2 2006.281.07:40:09.43#ibcon#about to read 5, iclass 13, count 2 2006.281.07:40:09.43#ibcon#read 5, iclass 13, count 2 2006.281.07:40:09.43#ibcon#about to read 6, iclass 13, count 2 2006.281.07:40:09.43#ibcon#read 6, iclass 13, count 2 2006.281.07:40:09.43#ibcon#end of sib2, iclass 13, count 2 2006.281.07:40:09.43#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:40:09.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:40:09.43#ibcon#[25=AT01-07\r\n] 2006.281.07:40:09.43#ibcon#*before write, iclass 13, count 2 2006.281.07:40:09.43#ibcon#enter sib2, iclass 13, count 2 2006.281.07:40:09.43#ibcon#flushed, iclass 13, count 2 2006.281.07:40:09.43#ibcon#about to write, iclass 13, count 2 2006.281.07:40:09.43#ibcon#wrote, iclass 13, count 2 2006.281.07:40:09.43#ibcon#about to read 3, iclass 13, count 2 2006.281.07:40:09.46#ibcon#read 3, iclass 13, count 2 2006.281.07:40:09.46#ibcon#about to read 4, iclass 13, count 2 2006.281.07:40:09.46#ibcon#read 4, iclass 13, count 2 2006.281.07:40:09.46#ibcon#about to read 5, iclass 13, count 2 2006.281.07:40:09.46#ibcon#read 5, iclass 13, count 2 2006.281.07:40:09.46#ibcon#about to read 6, iclass 13, count 2 2006.281.07:40:09.46#ibcon#read 6, iclass 13, count 2 2006.281.07:40:09.46#ibcon#end of sib2, iclass 13, count 2 2006.281.07:40:09.46#ibcon#*after write, iclass 13, count 2 2006.281.07:40:09.46#ibcon#*before return 0, iclass 13, count 2 2006.281.07:40:09.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:09.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:09.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:40:09.46#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:09.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:09.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:09.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:09.59#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:40:09.59#ibcon#first serial, iclass 13, count 0 2006.281.07:40:09.59#ibcon#enter sib2, iclass 13, count 0 2006.281.07:40:09.59#ibcon#flushed, iclass 13, count 0 2006.281.07:40:09.59#ibcon#about to write, iclass 13, count 0 2006.281.07:40:09.59#ibcon#wrote, iclass 13, count 0 2006.281.07:40:09.59#ibcon#about to read 3, iclass 13, count 0 2006.281.07:40:09.61#ibcon#read 3, iclass 13, count 0 2006.281.07:40:09.61#ibcon#about to read 4, iclass 13, count 0 2006.281.07:40:09.61#ibcon#read 4, iclass 13, count 0 2006.281.07:40:09.61#ibcon#about to read 5, iclass 13, count 0 2006.281.07:40:09.61#ibcon#read 5, iclass 13, count 0 2006.281.07:40:09.61#ibcon#about to read 6, iclass 13, count 0 2006.281.07:40:09.61#ibcon#read 6, iclass 13, count 0 2006.281.07:40:09.61#ibcon#end of sib2, iclass 13, count 0 2006.281.07:40:09.61#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:40:09.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:40:09.61#ibcon#[25=USB\r\n] 2006.281.07:40:09.61#ibcon#*before write, iclass 13, count 0 2006.281.07:40:09.61#ibcon#enter sib2, iclass 13, count 0 2006.281.07:40:09.61#ibcon#flushed, iclass 13, count 0 2006.281.07:40:09.61#ibcon#about to write, iclass 13, count 0 2006.281.07:40:09.61#ibcon#wrote, iclass 13, count 0 2006.281.07:40:09.61#ibcon#about to read 3, iclass 13, count 0 2006.281.07:40:09.63#ibcon#read 3, iclass 13, count 0 2006.281.07:40:09.63#ibcon#about to read 4, iclass 13, count 0 2006.281.07:40:09.63#ibcon#read 4, iclass 13, count 0 2006.281.07:40:09.63#ibcon#about to read 5, iclass 13, count 0 2006.281.07:40:09.63#ibcon#read 5, iclass 13, count 0 2006.281.07:40:09.63#ibcon#about to read 6, iclass 13, count 0 2006.281.07:40:09.63#ibcon#read 6, iclass 13, count 0 2006.281.07:40:09.63#ibcon#end of sib2, iclass 13, count 0 2006.281.07:40:09.63#ibcon#*after write, iclass 13, count 0 2006.281.07:40:09.63#ibcon#*before return 0, iclass 13, count 0 2006.281.07:40:09.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:09.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:09.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:40:09.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:40:09.63$vc4f8/valo=2,572.99 2006.281.07:40:09.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:40:09.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:40:09.63#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:09.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:09.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:09.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:09.63#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:40:09.63#ibcon#first serial, iclass 15, count 0 2006.281.07:40:09.63#ibcon#enter sib2, iclass 15, count 0 2006.281.07:40:09.63#ibcon#flushed, iclass 15, count 0 2006.281.07:40:09.63#ibcon#about to write, iclass 15, count 0 2006.281.07:40:09.63#ibcon#wrote, iclass 15, count 0 2006.281.07:40:09.63#ibcon#about to read 3, iclass 15, count 0 2006.281.07:40:09.66#ibcon#read 3, iclass 15, count 0 2006.281.07:40:09.66#ibcon#about to read 4, iclass 15, count 0 2006.281.07:40:09.66#ibcon#read 4, iclass 15, count 0 2006.281.07:40:09.66#ibcon#about to read 5, iclass 15, count 0 2006.281.07:40:09.66#ibcon#read 5, iclass 15, count 0 2006.281.07:40:09.66#ibcon#about to read 6, iclass 15, count 0 2006.281.07:40:09.66#ibcon#read 6, iclass 15, count 0 2006.281.07:40:09.66#ibcon#end of sib2, iclass 15, count 0 2006.281.07:40:09.66#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:40:09.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:40:09.66#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:40:09.66#ibcon#*before write, iclass 15, count 0 2006.281.07:40:09.66#ibcon#enter sib2, iclass 15, count 0 2006.281.07:40:09.66#ibcon#flushed, iclass 15, count 0 2006.281.07:40:09.66#ibcon#about to write, iclass 15, count 0 2006.281.07:40:09.66#ibcon#wrote, iclass 15, count 0 2006.281.07:40:09.66#ibcon#about to read 3, iclass 15, count 0 2006.281.07:40:09.69#ibcon#read 3, iclass 15, count 0 2006.281.07:40:09.69#ibcon#about to read 4, iclass 15, count 0 2006.281.07:40:09.69#ibcon#read 4, iclass 15, count 0 2006.281.07:40:09.69#ibcon#about to read 5, iclass 15, count 0 2006.281.07:40:09.69#ibcon#read 5, iclass 15, count 0 2006.281.07:40:09.69#ibcon#about to read 6, iclass 15, count 0 2006.281.07:40:09.69#ibcon#read 6, iclass 15, count 0 2006.281.07:40:09.69#ibcon#end of sib2, iclass 15, count 0 2006.281.07:40:09.69#ibcon#*after write, iclass 15, count 0 2006.281.07:40:09.69#ibcon#*before return 0, iclass 15, count 0 2006.281.07:40:09.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:09.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:09.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:40:09.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:40:09.69$vc4f8/va=2,6 2006.281.07:40:09.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:40:09.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:40:09.69#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:09.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:09.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:09.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:09.75#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:40:09.75#ibcon#first serial, iclass 17, count 2 2006.281.07:40:09.75#ibcon#enter sib2, iclass 17, count 2 2006.281.07:40:09.75#ibcon#flushed, iclass 17, count 2 2006.281.07:40:09.75#ibcon#about to write, iclass 17, count 2 2006.281.07:40:09.75#ibcon#wrote, iclass 17, count 2 2006.281.07:40:09.75#ibcon#about to read 3, iclass 17, count 2 2006.281.07:40:09.78#ibcon#read 3, iclass 17, count 2 2006.281.07:40:09.78#ibcon#about to read 4, iclass 17, count 2 2006.281.07:40:09.78#ibcon#read 4, iclass 17, count 2 2006.281.07:40:09.78#ibcon#about to read 5, iclass 17, count 2 2006.281.07:40:09.78#ibcon#read 5, iclass 17, count 2 2006.281.07:40:09.78#ibcon#about to read 6, iclass 17, count 2 2006.281.07:40:09.78#ibcon#read 6, iclass 17, count 2 2006.281.07:40:09.78#ibcon#end of sib2, iclass 17, count 2 2006.281.07:40:09.78#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:40:09.78#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:40:09.78#ibcon#[25=AT02-06\r\n] 2006.281.07:40:09.78#ibcon#*before write, iclass 17, count 2 2006.281.07:40:09.78#ibcon#enter sib2, iclass 17, count 2 2006.281.07:40:09.78#ibcon#flushed, iclass 17, count 2 2006.281.07:40:09.78#ibcon#about to write, iclass 17, count 2 2006.281.07:40:09.78#ibcon#wrote, iclass 17, count 2 2006.281.07:40:09.78#ibcon#about to read 3, iclass 17, count 2 2006.281.07:40:09.80#ibcon#read 3, iclass 17, count 2 2006.281.07:40:09.80#ibcon#about to read 4, iclass 17, count 2 2006.281.07:40:09.80#ibcon#read 4, iclass 17, count 2 2006.281.07:40:09.80#ibcon#about to read 5, iclass 17, count 2 2006.281.07:40:09.80#ibcon#read 5, iclass 17, count 2 2006.281.07:40:09.80#ibcon#about to read 6, iclass 17, count 2 2006.281.07:40:09.80#ibcon#read 6, iclass 17, count 2 2006.281.07:40:09.80#ibcon#end of sib2, iclass 17, count 2 2006.281.07:40:09.80#ibcon#*after write, iclass 17, count 2 2006.281.07:40:09.80#ibcon#*before return 0, iclass 17, count 2 2006.281.07:40:09.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:09.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:09.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:40:09.80#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:09.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:09.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:09.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:09.92#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:40:09.92#ibcon#first serial, iclass 17, count 0 2006.281.07:40:09.92#ibcon#enter sib2, iclass 17, count 0 2006.281.07:40:09.92#ibcon#flushed, iclass 17, count 0 2006.281.07:40:09.92#ibcon#about to write, iclass 17, count 0 2006.281.07:40:09.92#ibcon#wrote, iclass 17, count 0 2006.281.07:40:09.92#ibcon#about to read 3, iclass 17, count 0 2006.281.07:40:09.94#ibcon#read 3, iclass 17, count 0 2006.281.07:40:09.94#ibcon#about to read 4, iclass 17, count 0 2006.281.07:40:09.94#ibcon#read 4, iclass 17, count 0 2006.281.07:40:09.94#ibcon#about to read 5, iclass 17, count 0 2006.281.07:40:09.94#ibcon#read 5, iclass 17, count 0 2006.281.07:40:09.94#ibcon#about to read 6, iclass 17, count 0 2006.281.07:40:09.94#ibcon#read 6, iclass 17, count 0 2006.281.07:40:09.94#ibcon#end of sib2, iclass 17, count 0 2006.281.07:40:09.94#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:40:09.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:40:09.94#ibcon#[25=USB\r\n] 2006.281.07:40:09.94#ibcon#*before write, iclass 17, count 0 2006.281.07:40:09.94#ibcon#enter sib2, iclass 17, count 0 2006.281.07:40:09.94#ibcon#flushed, iclass 17, count 0 2006.281.07:40:09.94#ibcon#about to write, iclass 17, count 0 2006.281.07:40:09.94#ibcon#wrote, iclass 17, count 0 2006.281.07:40:09.94#ibcon#about to read 3, iclass 17, count 0 2006.281.07:40:09.98#ibcon#read 3, iclass 17, count 0 2006.281.07:40:09.98#ibcon#about to read 4, iclass 17, count 0 2006.281.07:40:09.98#ibcon#read 4, iclass 17, count 0 2006.281.07:40:09.98#ibcon#about to read 5, iclass 17, count 0 2006.281.07:40:09.98#ibcon#read 5, iclass 17, count 0 2006.281.07:40:09.98#ibcon#about to read 6, iclass 17, count 0 2006.281.07:40:09.98#ibcon#read 6, iclass 17, count 0 2006.281.07:40:09.98#ibcon#end of sib2, iclass 17, count 0 2006.281.07:40:09.98#ibcon#*after write, iclass 17, count 0 2006.281.07:40:09.98#ibcon#*before return 0, iclass 17, count 0 2006.281.07:40:09.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:09.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:09.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:40:09.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:40:09.98$vc4f8/valo=3,672.99 2006.281.07:40:09.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:40:09.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:40:09.98#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:09.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:09.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:09.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:09.98#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:40:09.98#ibcon#first serial, iclass 19, count 0 2006.281.07:40:09.98#ibcon#enter sib2, iclass 19, count 0 2006.281.07:40:09.98#ibcon#flushed, iclass 19, count 0 2006.281.07:40:09.98#ibcon#about to write, iclass 19, count 0 2006.281.07:40:09.98#ibcon#wrote, iclass 19, count 0 2006.281.07:40:09.98#ibcon#about to read 3, iclass 19, count 0 2006.281.07:40:09.99#ibcon#read 3, iclass 19, count 0 2006.281.07:40:09.99#ibcon#about to read 4, iclass 19, count 0 2006.281.07:40:09.99#ibcon#read 4, iclass 19, count 0 2006.281.07:40:09.99#ibcon#about to read 5, iclass 19, count 0 2006.281.07:40:09.99#ibcon#read 5, iclass 19, count 0 2006.281.07:40:09.99#ibcon#about to read 6, iclass 19, count 0 2006.281.07:40:09.99#ibcon#read 6, iclass 19, count 0 2006.281.07:40:09.99#ibcon#end of sib2, iclass 19, count 0 2006.281.07:40:09.99#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:40:09.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:40:10.02#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:40:10.02#ibcon#*before write, iclass 19, count 0 2006.281.07:40:10.02#ibcon#enter sib2, iclass 19, count 0 2006.281.07:40:10.02#ibcon#flushed, iclass 19, count 0 2006.281.07:40:10.02#ibcon#about to write, iclass 19, count 0 2006.281.07:40:10.02#ibcon#wrote, iclass 19, count 0 2006.281.07:40:10.02#ibcon#about to read 3, iclass 19, count 0 2006.281.07:40:10.05#ibcon#read 3, iclass 19, count 0 2006.281.07:40:10.05#ibcon#about to read 4, iclass 19, count 0 2006.281.07:40:10.05#ibcon#read 4, iclass 19, count 0 2006.281.07:40:10.05#ibcon#about to read 5, iclass 19, count 0 2006.281.07:40:10.05#ibcon#read 5, iclass 19, count 0 2006.281.07:40:10.05#ibcon#about to read 6, iclass 19, count 0 2006.281.07:40:10.05#ibcon#read 6, iclass 19, count 0 2006.281.07:40:10.05#ibcon#end of sib2, iclass 19, count 0 2006.281.07:40:10.05#ibcon#*after write, iclass 19, count 0 2006.281.07:40:10.05#ibcon#*before return 0, iclass 19, count 0 2006.281.07:40:10.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:10.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:10.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:40:10.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:40:10.05$vc4f8/va=3,6 2006.281.07:40:10.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:40:10.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:40:10.05#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:10.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:10.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:10.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:10.11#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:40:10.11#ibcon#first serial, iclass 21, count 2 2006.281.07:40:10.11#ibcon#enter sib2, iclass 21, count 2 2006.281.07:40:10.11#ibcon#flushed, iclass 21, count 2 2006.281.07:40:10.11#ibcon#about to write, iclass 21, count 2 2006.281.07:40:10.11#ibcon#wrote, iclass 21, count 2 2006.281.07:40:10.11#ibcon#about to read 3, iclass 21, count 2 2006.281.07:40:10.12#ibcon#read 3, iclass 21, count 2 2006.281.07:40:10.12#ibcon#about to read 4, iclass 21, count 2 2006.281.07:40:10.12#ibcon#read 4, iclass 21, count 2 2006.281.07:40:10.12#ibcon#about to read 5, iclass 21, count 2 2006.281.07:40:10.12#ibcon#read 5, iclass 21, count 2 2006.281.07:40:10.12#ibcon#about to read 6, iclass 21, count 2 2006.281.07:40:10.12#ibcon#read 6, iclass 21, count 2 2006.281.07:40:10.12#ibcon#end of sib2, iclass 21, count 2 2006.281.07:40:10.12#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:40:10.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:40:10.12#ibcon#[25=AT03-06\r\n] 2006.281.07:40:10.12#ibcon#*before write, iclass 21, count 2 2006.281.07:40:10.12#ibcon#enter sib2, iclass 21, count 2 2006.281.07:40:10.12#ibcon#flushed, iclass 21, count 2 2006.281.07:40:10.12#ibcon#about to write, iclass 21, count 2 2006.281.07:40:10.12#ibcon#wrote, iclass 21, count 2 2006.281.07:40:10.12#ibcon#about to read 3, iclass 21, count 2 2006.281.07:40:10.15#ibcon#read 3, iclass 21, count 2 2006.281.07:40:10.15#ibcon#about to read 4, iclass 21, count 2 2006.281.07:40:10.15#ibcon#read 4, iclass 21, count 2 2006.281.07:40:10.15#ibcon#about to read 5, iclass 21, count 2 2006.281.07:40:10.15#ibcon#read 5, iclass 21, count 2 2006.281.07:40:10.15#ibcon#about to read 6, iclass 21, count 2 2006.281.07:40:10.15#ibcon#read 6, iclass 21, count 2 2006.281.07:40:10.15#ibcon#end of sib2, iclass 21, count 2 2006.281.07:40:10.15#ibcon#*after write, iclass 21, count 2 2006.281.07:40:10.15#ibcon#*before return 0, iclass 21, count 2 2006.281.07:40:10.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:10.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:10.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:40:10.15#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:10.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:10.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:10.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:10.28#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:40:10.28#ibcon#first serial, iclass 21, count 0 2006.281.07:40:10.28#ibcon#enter sib2, iclass 21, count 0 2006.281.07:40:10.28#ibcon#flushed, iclass 21, count 0 2006.281.07:40:10.28#ibcon#about to write, iclass 21, count 0 2006.281.07:40:10.28#ibcon#wrote, iclass 21, count 0 2006.281.07:40:10.28#ibcon#about to read 3, iclass 21, count 0 2006.281.07:40:10.29#ibcon#read 3, iclass 21, count 0 2006.281.07:40:10.29#ibcon#about to read 4, iclass 21, count 0 2006.281.07:40:10.29#ibcon#read 4, iclass 21, count 0 2006.281.07:40:10.29#ibcon#about to read 5, iclass 21, count 0 2006.281.07:40:10.29#ibcon#read 5, iclass 21, count 0 2006.281.07:40:10.29#ibcon#about to read 6, iclass 21, count 0 2006.281.07:40:10.29#ibcon#read 6, iclass 21, count 0 2006.281.07:40:10.29#ibcon#end of sib2, iclass 21, count 0 2006.281.07:40:10.29#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:40:10.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:40:10.29#ibcon#[25=USB\r\n] 2006.281.07:40:10.29#ibcon#*before write, iclass 21, count 0 2006.281.07:40:10.29#ibcon#enter sib2, iclass 21, count 0 2006.281.07:40:10.29#ibcon#flushed, iclass 21, count 0 2006.281.07:40:10.29#ibcon#about to write, iclass 21, count 0 2006.281.07:40:10.29#ibcon#wrote, iclass 21, count 0 2006.281.07:40:10.29#ibcon#about to read 3, iclass 21, count 0 2006.281.07:40:10.32#ibcon#read 3, iclass 21, count 0 2006.281.07:40:10.32#ibcon#about to read 4, iclass 21, count 0 2006.281.07:40:10.32#ibcon#read 4, iclass 21, count 0 2006.281.07:40:10.32#ibcon#about to read 5, iclass 21, count 0 2006.281.07:40:10.32#ibcon#read 5, iclass 21, count 0 2006.281.07:40:10.32#ibcon#about to read 6, iclass 21, count 0 2006.281.07:40:10.32#ibcon#read 6, iclass 21, count 0 2006.281.07:40:10.32#ibcon#end of sib2, iclass 21, count 0 2006.281.07:40:10.32#ibcon#*after write, iclass 21, count 0 2006.281.07:40:10.32#ibcon#*before return 0, iclass 21, count 0 2006.281.07:40:10.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:10.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:10.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:40:10.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:40:10.32$vc4f8/valo=4,832.99 2006.281.07:40:10.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:40:10.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:40:10.32#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:10.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:10.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:10.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:10.32#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:40:10.32#ibcon#first serial, iclass 23, count 0 2006.281.07:40:10.32#ibcon#enter sib2, iclass 23, count 0 2006.281.07:40:10.32#ibcon#flushed, iclass 23, count 0 2006.281.07:40:10.32#ibcon#about to write, iclass 23, count 0 2006.281.07:40:10.32#ibcon#wrote, iclass 23, count 0 2006.281.07:40:10.32#ibcon#about to read 3, iclass 23, count 0 2006.281.07:40:10.34#ibcon#read 3, iclass 23, count 0 2006.281.07:40:10.34#ibcon#about to read 4, iclass 23, count 0 2006.281.07:40:10.34#ibcon#read 4, iclass 23, count 0 2006.281.07:40:10.34#ibcon#about to read 5, iclass 23, count 0 2006.281.07:40:10.34#ibcon#read 5, iclass 23, count 0 2006.281.07:40:10.34#ibcon#about to read 6, iclass 23, count 0 2006.281.07:40:10.34#ibcon#read 6, iclass 23, count 0 2006.281.07:40:10.34#ibcon#end of sib2, iclass 23, count 0 2006.281.07:40:10.34#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:40:10.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:40:10.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:40:10.34#ibcon#*before write, iclass 23, count 0 2006.281.07:40:10.34#ibcon#enter sib2, iclass 23, count 0 2006.281.07:40:10.34#ibcon#flushed, iclass 23, count 0 2006.281.07:40:10.34#ibcon#about to write, iclass 23, count 0 2006.281.07:40:10.34#ibcon#wrote, iclass 23, count 0 2006.281.07:40:10.34#ibcon#about to read 3, iclass 23, count 0 2006.281.07:40:10.39#ibcon#read 3, iclass 23, count 0 2006.281.07:40:10.39#ibcon#about to read 4, iclass 23, count 0 2006.281.07:40:10.39#ibcon#read 4, iclass 23, count 0 2006.281.07:40:10.39#ibcon#about to read 5, iclass 23, count 0 2006.281.07:40:10.39#ibcon#read 5, iclass 23, count 0 2006.281.07:40:10.39#ibcon#about to read 6, iclass 23, count 0 2006.281.07:40:10.39#ibcon#read 6, iclass 23, count 0 2006.281.07:40:10.39#ibcon#end of sib2, iclass 23, count 0 2006.281.07:40:10.39#ibcon#*after write, iclass 23, count 0 2006.281.07:40:10.39#ibcon#*before return 0, iclass 23, count 0 2006.281.07:40:10.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:10.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:10.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:40:10.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:40:10.39$vc4f8/va=4,6 2006.281.07:40:10.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:40:10.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:40:10.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:10.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:10.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:10.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:10.43#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:40:10.43#ibcon#first serial, iclass 25, count 2 2006.281.07:40:10.43#ibcon#enter sib2, iclass 25, count 2 2006.281.07:40:10.43#ibcon#flushed, iclass 25, count 2 2006.281.07:40:10.43#ibcon#about to write, iclass 25, count 2 2006.281.07:40:10.43#ibcon#wrote, iclass 25, count 2 2006.281.07:40:10.43#ibcon#about to read 3, iclass 25, count 2 2006.281.07:40:10.46#ibcon#read 3, iclass 25, count 2 2006.281.07:40:10.46#ibcon#about to read 4, iclass 25, count 2 2006.281.07:40:10.46#ibcon#read 4, iclass 25, count 2 2006.281.07:40:10.46#ibcon#about to read 5, iclass 25, count 2 2006.281.07:40:10.46#ibcon#read 5, iclass 25, count 2 2006.281.07:40:10.46#ibcon#about to read 6, iclass 25, count 2 2006.281.07:40:10.46#ibcon#read 6, iclass 25, count 2 2006.281.07:40:10.46#ibcon#end of sib2, iclass 25, count 2 2006.281.07:40:10.46#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:40:10.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:40:10.46#ibcon#[25=AT04-06\r\n] 2006.281.07:40:10.46#ibcon#*before write, iclass 25, count 2 2006.281.07:40:10.46#ibcon#enter sib2, iclass 25, count 2 2006.281.07:40:10.46#ibcon#flushed, iclass 25, count 2 2006.281.07:40:10.46#ibcon#about to write, iclass 25, count 2 2006.281.07:40:10.46#ibcon#wrote, iclass 25, count 2 2006.281.07:40:10.46#ibcon#about to read 3, iclass 25, count 2 2006.281.07:40:10.48#ibcon#read 3, iclass 25, count 2 2006.281.07:40:10.48#ibcon#about to read 4, iclass 25, count 2 2006.281.07:40:10.48#ibcon#read 4, iclass 25, count 2 2006.281.07:40:10.48#ibcon#about to read 5, iclass 25, count 2 2006.281.07:40:10.48#ibcon#read 5, iclass 25, count 2 2006.281.07:40:10.48#ibcon#about to read 6, iclass 25, count 2 2006.281.07:40:10.48#ibcon#read 6, iclass 25, count 2 2006.281.07:40:10.49#ibcon#end of sib2, iclass 25, count 2 2006.281.07:40:10.49#ibcon#*after write, iclass 25, count 2 2006.281.07:40:10.49#ibcon#*before return 0, iclass 25, count 2 2006.281.07:40:10.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:10.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:10.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:40:10.49#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:10.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:10.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:10.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:10.60#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:40:10.60#ibcon#first serial, iclass 25, count 0 2006.281.07:40:10.60#ibcon#enter sib2, iclass 25, count 0 2006.281.07:40:10.60#ibcon#flushed, iclass 25, count 0 2006.281.07:40:10.60#ibcon#about to write, iclass 25, count 0 2006.281.07:40:10.60#ibcon#wrote, iclass 25, count 0 2006.281.07:40:10.60#ibcon#about to read 3, iclass 25, count 0 2006.281.07:40:10.62#ibcon#read 3, iclass 25, count 0 2006.281.07:40:10.62#ibcon#about to read 4, iclass 25, count 0 2006.281.07:40:10.62#ibcon#read 4, iclass 25, count 0 2006.281.07:40:10.62#ibcon#about to read 5, iclass 25, count 0 2006.281.07:40:10.62#ibcon#read 5, iclass 25, count 0 2006.281.07:40:10.62#ibcon#about to read 6, iclass 25, count 0 2006.281.07:40:10.62#ibcon#read 6, iclass 25, count 0 2006.281.07:40:10.62#ibcon#end of sib2, iclass 25, count 0 2006.281.07:40:10.62#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:40:10.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:40:10.62#ibcon#[25=USB\r\n] 2006.281.07:40:10.62#ibcon#*before write, iclass 25, count 0 2006.281.07:40:10.62#ibcon#enter sib2, iclass 25, count 0 2006.281.07:40:10.62#ibcon#flushed, iclass 25, count 0 2006.281.07:40:10.62#ibcon#about to write, iclass 25, count 0 2006.281.07:40:10.62#ibcon#wrote, iclass 25, count 0 2006.281.07:40:10.62#ibcon#about to read 3, iclass 25, count 0 2006.281.07:40:10.65#ibcon#read 3, iclass 25, count 0 2006.281.07:40:10.65#ibcon#about to read 4, iclass 25, count 0 2006.281.07:40:10.65#ibcon#read 4, iclass 25, count 0 2006.281.07:40:10.65#ibcon#about to read 5, iclass 25, count 0 2006.281.07:40:10.65#ibcon#read 5, iclass 25, count 0 2006.281.07:40:10.65#ibcon#about to read 6, iclass 25, count 0 2006.281.07:40:10.65#ibcon#read 6, iclass 25, count 0 2006.281.07:40:10.65#ibcon#end of sib2, iclass 25, count 0 2006.281.07:40:10.65#ibcon#*after write, iclass 25, count 0 2006.281.07:40:10.65#ibcon#*before return 0, iclass 25, count 0 2006.281.07:40:10.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:10.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:10.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:40:10.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:40:10.65$vc4f8/valo=5,652.99 2006.281.07:40:10.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:40:10.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:40:10.65#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:10.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:10.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:10.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:10.65#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:40:10.65#ibcon#first serial, iclass 27, count 0 2006.281.07:40:10.65#ibcon#enter sib2, iclass 27, count 0 2006.281.07:40:10.65#ibcon#flushed, iclass 27, count 0 2006.281.07:40:10.65#ibcon#about to write, iclass 27, count 0 2006.281.07:40:10.65#ibcon#wrote, iclass 27, count 0 2006.281.07:40:10.65#ibcon#about to read 3, iclass 27, count 0 2006.281.07:40:10.67#ibcon#read 3, iclass 27, count 0 2006.281.07:40:10.67#ibcon#about to read 4, iclass 27, count 0 2006.281.07:40:10.67#ibcon#read 4, iclass 27, count 0 2006.281.07:40:10.67#ibcon#about to read 5, iclass 27, count 0 2006.281.07:40:10.67#ibcon#read 5, iclass 27, count 0 2006.281.07:40:10.67#ibcon#about to read 6, iclass 27, count 0 2006.281.07:40:10.67#ibcon#read 6, iclass 27, count 0 2006.281.07:40:10.67#ibcon#end of sib2, iclass 27, count 0 2006.281.07:40:10.67#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:40:10.67#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:40:10.69#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:40:10.69#ibcon#*before write, iclass 27, count 0 2006.281.07:40:10.69#ibcon#enter sib2, iclass 27, count 0 2006.281.07:40:10.69#ibcon#flushed, iclass 27, count 0 2006.281.07:40:10.69#ibcon#about to write, iclass 27, count 0 2006.281.07:40:10.69#ibcon#wrote, iclass 27, count 0 2006.281.07:40:10.69#ibcon#about to read 3, iclass 27, count 0 2006.281.07:40:10.73#ibcon#read 3, iclass 27, count 0 2006.281.07:40:10.73#ibcon#about to read 4, iclass 27, count 0 2006.281.07:40:10.73#ibcon#read 4, iclass 27, count 0 2006.281.07:40:10.73#ibcon#about to read 5, iclass 27, count 0 2006.281.07:40:10.73#ibcon#read 5, iclass 27, count 0 2006.281.07:40:10.73#ibcon#about to read 6, iclass 27, count 0 2006.281.07:40:10.73#ibcon#read 6, iclass 27, count 0 2006.281.07:40:10.73#ibcon#end of sib2, iclass 27, count 0 2006.281.07:40:10.73#ibcon#*after write, iclass 27, count 0 2006.281.07:40:10.73#ibcon#*before return 0, iclass 27, count 0 2006.281.07:40:10.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:10.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:10.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:40:10.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:40:10.73$vc4f8/va=5,7 2006.281.07:40:10.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:40:10.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:40:10.73#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:10.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:10.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:10.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:10.77#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:40:10.77#ibcon#first serial, iclass 29, count 2 2006.281.07:40:10.77#ibcon#enter sib2, iclass 29, count 2 2006.281.07:40:10.77#ibcon#flushed, iclass 29, count 2 2006.281.07:40:10.77#ibcon#about to write, iclass 29, count 2 2006.281.07:40:10.77#ibcon#wrote, iclass 29, count 2 2006.281.07:40:10.77#ibcon#about to read 3, iclass 29, count 2 2006.281.07:40:10.79#ibcon#read 3, iclass 29, count 2 2006.281.07:40:10.79#ibcon#about to read 4, iclass 29, count 2 2006.281.07:40:10.79#ibcon#read 4, iclass 29, count 2 2006.281.07:40:10.79#ibcon#about to read 5, iclass 29, count 2 2006.281.07:40:10.79#ibcon#read 5, iclass 29, count 2 2006.281.07:40:10.79#ibcon#about to read 6, iclass 29, count 2 2006.281.07:40:10.79#ibcon#read 6, iclass 29, count 2 2006.281.07:40:10.79#ibcon#end of sib2, iclass 29, count 2 2006.281.07:40:10.79#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:40:10.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:40:10.79#ibcon#[25=AT05-07\r\n] 2006.281.07:40:10.79#ibcon#*before write, iclass 29, count 2 2006.281.07:40:10.79#ibcon#enter sib2, iclass 29, count 2 2006.281.07:40:10.79#ibcon#flushed, iclass 29, count 2 2006.281.07:40:10.79#ibcon#about to write, iclass 29, count 2 2006.281.07:40:10.79#ibcon#wrote, iclass 29, count 2 2006.281.07:40:10.79#ibcon#about to read 3, iclass 29, count 2 2006.281.07:40:10.82#ibcon#read 3, iclass 29, count 2 2006.281.07:40:10.82#ibcon#about to read 4, iclass 29, count 2 2006.281.07:40:10.82#ibcon#read 4, iclass 29, count 2 2006.281.07:40:10.82#ibcon#about to read 5, iclass 29, count 2 2006.281.07:40:10.82#ibcon#read 5, iclass 29, count 2 2006.281.07:40:10.82#ibcon#about to read 6, iclass 29, count 2 2006.281.07:40:10.82#ibcon#read 6, iclass 29, count 2 2006.281.07:40:10.82#ibcon#end of sib2, iclass 29, count 2 2006.281.07:40:10.82#ibcon#*after write, iclass 29, count 2 2006.281.07:40:10.82#ibcon#*before return 0, iclass 29, count 2 2006.281.07:40:10.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:10.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:10.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:40:10.82#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:10.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:10.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:10.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:10.94#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:40:10.94#ibcon#first serial, iclass 29, count 0 2006.281.07:40:10.95#ibcon#enter sib2, iclass 29, count 0 2006.281.07:40:10.95#ibcon#flushed, iclass 29, count 0 2006.281.07:40:10.95#ibcon#about to write, iclass 29, count 0 2006.281.07:40:10.95#ibcon#wrote, iclass 29, count 0 2006.281.07:40:10.95#ibcon#about to read 3, iclass 29, count 0 2006.281.07:40:10.96#ibcon#read 3, iclass 29, count 0 2006.281.07:40:10.96#ibcon#about to read 4, iclass 29, count 0 2006.281.07:40:10.96#ibcon#read 4, iclass 29, count 0 2006.281.07:40:10.96#ibcon#about to read 5, iclass 29, count 0 2006.281.07:40:10.96#ibcon#read 5, iclass 29, count 0 2006.281.07:40:10.96#ibcon#about to read 6, iclass 29, count 0 2006.281.07:40:10.96#ibcon#read 6, iclass 29, count 0 2006.281.07:40:10.96#ibcon#end of sib2, iclass 29, count 0 2006.281.07:40:10.96#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:40:10.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:40:10.96#ibcon#[25=USB\r\n] 2006.281.07:40:10.96#ibcon#*before write, iclass 29, count 0 2006.281.07:40:10.96#ibcon#enter sib2, iclass 29, count 0 2006.281.07:40:10.96#ibcon#flushed, iclass 29, count 0 2006.281.07:40:10.96#ibcon#about to write, iclass 29, count 0 2006.281.07:40:10.96#ibcon#wrote, iclass 29, count 0 2006.281.07:40:10.96#ibcon#about to read 3, iclass 29, count 0 2006.281.07:40:10.99#ibcon#read 3, iclass 29, count 0 2006.281.07:40:10.99#ibcon#about to read 4, iclass 29, count 0 2006.281.07:40:10.99#ibcon#read 4, iclass 29, count 0 2006.281.07:40:10.99#ibcon#about to read 5, iclass 29, count 0 2006.281.07:40:10.99#ibcon#read 5, iclass 29, count 0 2006.281.07:40:10.99#ibcon#about to read 6, iclass 29, count 0 2006.281.07:40:10.99#ibcon#read 6, iclass 29, count 0 2006.281.07:40:10.99#ibcon#end of sib2, iclass 29, count 0 2006.281.07:40:10.99#ibcon#*after write, iclass 29, count 0 2006.281.07:40:10.99#ibcon#*before return 0, iclass 29, count 0 2006.281.07:40:10.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:10.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:10.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:40:10.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:40:10.99$vc4f8/valo=6,772.99 2006.281.07:40:10.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:40:10.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:40:10.99#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:10.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:10.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:10.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:10.99#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:40:10.99#ibcon#first serial, iclass 31, count 0 2006.281.07:40:10.99#ibcon#enter sib2, iclass 31, count 0 2006.281.07:40:10.99#ibcon#flushed, iclass 31, count 0 2006.281.07:40:10.99#ibcon#about to write, iclass 31, count 0 2006.281.07:40:10.99#ibcon#wrote, iclass 31, count 0 2006.281.07:40:10.99#ibcon#about to read 3, iclass 31, count 0 2006.281.07:40:11.01#ibcon#read 3, iclass 31, count 0 2006.281.07:40:11.01#ibcon#about to read 4, iclass 31, count 0 2006.281.07:40:11.01#ibcon#read 4, iclass 31, count 0 2006.281.07:40:11.01#ibcon#about to read 5, iclass 31, count 0 2006.281.07:40:11.01#ibcon#read 5, iclass 31, count 0 2006.281.07:40:11.01#ibcon#about to read 6, iclass 31, count 0 2006.281.07:40:11.01#ibcon#read 6, iclass 31, count 0 2006.281.07:40:11.01#ibcon#end of sib2, iclass 31, count 0 2006.281.07:40:11.01#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:40:11.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:40:11.01#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:40:11.01#ibcon#*before write, iclass 31, count 0 2006.281.07:40:11.01#ibcon#enter sib2, iclass 31, count 0 2006.281.07:40:11.01#ibcon#flushed, iclass 31, count 0 2006.281.07:40:11.01#ibcon#about to write, iclass 31, count 0 2006.281.07:40:11.01#ibcon#wrote, iclass 31, count 0 2006.281.07:40:11.01#ibcon#about to read 3, iclass 31, count 0 2006.281.07:40:11.06#ibcon#read 3, iclass 31, count 0 2006.281.07:40:11.06#ibcon#about to read 4, iclass 31, count 0 2006.281.07:40:11.06#ibcon#read 4, iclass 31, count 0 2006.281.07:40:11.06#ibcon#about to read 5, iclass 31, count 0 2006.281.07:40:11.06#ibcon#read 5, iclass 31, count 0 2006.281.07:40:11.06#ibcon#about to read 6, iclass 31, count 0 2006.281.07:40:11.06#ibcon#read 6, iclass 31, count 0 2006.281.07:40:11.06#ibcon#end of sib2, iclass 31, count 0 2006.281.07:40:11.06#ibcon#*after write, iclass 31, count 0 2006.281.07:40:11.06#ibcon#*before return 0, iclass 31, count 0 2006.281.07:40:11.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:11.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:11.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:40:11.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:40:11.06$vc4f8/va=6,6 2006.281.07:40:11.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:40:11.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:40:11.06#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:11.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:11.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:11.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:11.10#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:40:11.10#ibcon#first serial, iclass 33, count 2 2006.281.07:40:11.10#ibcon#enter sib2, iclass 33, count 2 2006.281.07:40:11.10#ibcon#flushed, iclass 33, count 2 2006.281.07:40:11.10#ibcon#about to write, iclass 33, count 2 2006.281.07:40:11.10#ibcon#wrote, iclass 33, count 2 2006.281.07:40:11.10#ibcon#about to read 3, iclass 33, count 2 2006.281.07:40:11.12#ibcon#read 3, iclass 33, count 2 2006.281.07:40:11.12#ibcon#about to read 4, iclass 33, count 2 2006.281.07:40:11.12#ibcon#read 4, iclass 33, count 2 2006.281.07:40:11.12#ibcon#about to read 5, iclass 33, count 2 2006.281.07:40:11.12#ibcon#read 5, iclass 33, count 2 2006.281.07:40:11.12#ibcon#about to read 6, iclass 33, count 2 2006.281.07:40:11.12#ibcon#read 6, iclass 33, count 2 2006.281.07:40:11.12#ibcon#end of sib2, iclass 33, count 2 2006.281.07:40:11.12#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:40:11.12#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:40:11.12#ibcon#[25=AT06-06\r\n] 2006.281.07:40:11.12#ibcon#*before write, iclass 33, count 2 2006.281.07:40:11.12#ibcon#enter sib2, iclass 33, count 2 2006.281.07:40:11.12#ibcon#flushed, iclass 33, count 2 2006.281.07:40:11.12#ibcon#about to write, iclass 33, count 2 2006.281.07:40:11.12#ibcon#wrote, iclass 33, count 2 2006.281.07:40:11.12#ibcon#about to read 3, iclass 33, count 2 2006.281.07:40:11.15#ibcon#read 3, iclass 33, count 2 2006.281.07:40:11.15#ibcon#about to read 4, iclass 33, count 2 2006.281.07:40:11.15#ibcon#read 4, iclass 33, count 2 2006.281.07:40:11.15#ibcon#about to read 5, iclass 33, count 2 2006.281.07:40:11.15#ibcon#read 5, iclass 33, count 2 2006.281.07:40:11.15#ibcon#about to read 6, iclass 33, count 2 2006.281.07:40:11.15#ibcon#read 6, iclass 33, count 2 2006.281.07:40:11.15#ibcon#end of sib2, iclass 33, count 2 2006.281.07:40:11.15#ibcon#*after write, iclass 33, count 2 2006.281.07:40:11.15#ibcon#*before return 0, iclass 33, count 2 2006.281.07:40:11.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:11.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:11.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:40:11.15#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:11.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:40:11.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:40:11.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:40:11.27#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:40:11.27#ibcon#first serial, iclass 33, count 0 2006.281.07:40:11.27#ibcon#enter sib2, iclass 33, count 0 2006.281.07:40:11.27#ibcon#flushed, iclass 33, count 0 2006.281.07:40:11.27#ibcon#about to write, iclass 33, count 0 2006.281.07:40:11.27#ibcon#wrote, iclass 33, count 0 2006.281.07:40:11.27#ibcon#about to read 3, iclass 33, count 0 2006.281.07:40:11.29#ibcon#read 3, iclass 33, count 0 2006.281.07:40:11.29#ibcon#about to read 4, iclass 33, count 0 2006.281.07:40:11.29#ibcon#read 4, iclass 33, count 0 2006.281.07:40:11.29#ibcon#about to read 5, iclass 33, count 0 2006.281.07:40:11.29#ibcon#read 5, iclass 33, count 0 2006.281.07:40:11.29#ibcon#about to read 6, iclass 33, count 0 2006.281.07:40:11.29#ibcon#read 6, iclass 33, count 0 2006.281.07:40:11.29#ibcon#end of sib2, iclass 33, count 0 2006.281.07:40:11.29#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:40:11.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:40:11.29#ibcon#[25=USB\r\n] 2006.281.07:40:11.29#ibcon#*before write, iclass 33, count 0 2006.281.07:40:11.29#ibcon#enter sib2, iclass 33, count 0 2006.281.07:40:11.29#ibcon#flushed, iclass 33, count 0 2006.281.07:40:11.29#ibcon#about to write, iclass 33, count 0 2006.281.07:40:11.29#ibcon#wrote, iclass 33, count 0 2006.281.07:40:11.29#ibcon#about to read 3, iclass 33, count 0 2006.281.07:40:11.32#ibcon#read 3, iclass 33, count 0 2006.281.07:40:11.32#ibcon#about to read 4, iclass 33, count 0 2006.281.07:40:11.32#ibcon#read 4, iclass 33, count 0 2006.281.07:40:11.32#ibcon#about to read 5, iclass 33, count 0 2006.281.07:40:11.32#ibcon#read 5, iclass 33, count 0 2006.281.07:40:11.32#ibcon#about to read 6, iclass 33, count 0 2006.281.07:40:11.32#ibcon#read 6, iclass 33, count 0 2006.281.07:40:11.32#ibcon#end of sib2, iclass 33, count 0 2006.281.07:40:11.32#ibcon#*after write, iclass 33, count 0 2006.281.07:40:11.32#ibcon#*before return 0, iclass 33, count 0 2006.281.07:40:11.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:40:11.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:40:11.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:40:11.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:40:11.32$vc4f8/valo=7,832.99 2006.281.07:40:11.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:40:11.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:40:11.32#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:11.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:40:11.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:40:11.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:40:11.32#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:40:11.32#ibcon#first serial, iclass 35, count 0 2006.281.07:40:11.32#ibcon#enter sib2, iclass 35, count 0 2006.281.07:40:11.32#ibcon#flushed, iclass 35, count 0 2006.281.07:40:11.32#ibcon#about to write, iclass 35, count 0 2006.281.07:40:11.32#ibcon#wrote, iclass 35, count 0 2006.281.07:40:11.32#ibcon#about to read 3, iclass 35, count 0 2006.281.07:40:11.34#ibcon#read 3, iclass 35, count 0 2006.281.07:40:11.34#ibcon#about to read 4, iclass 35, count 0 2006.281.07:40:11.34#ibcon#read 4, iclass 35, count 0 2006.281.07:40:11.34#ibcon#about to read 5, iclass 35, count 0 2006.281.07:40:11.34#ibcon#read 5, iclass 35, count 0 2006.281.07:40:11.34#ibcon#about to read 6, iclass 35, count 0 2006.281.07:40:11.34#ibcon#read 6, iclass 35, count 0 2006.281.07:40:11.34#ibcon#end of sib2, iclass 35, count 0 2006.281.07:40:11.34#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:40:11.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:40:11.34#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:40:11.34#ibcon#*before write, iclass 35, count 0 2006.281.07:40:11.34#ibcon#enter sib2, iclass 35, count 0 2006.281.07:40:11.34#ibcon#flushed, iclass 35, count 0 2006.281.07:40:11.34#ibcon#about to write, iclass 35, count 0 2006.281.07:40:11.34#ibcon#wrote, iclass 35, count 0 2006.281.07:40:11.34#ibcon#about to read 3, iclass 35, count 0 2006.281.07:40:11.39#ibcon#read 3, iclass 35, count 0 2006.281.07:40:11.39#ibcon#about to read 4, iclass 35, count 0 2006.281.07:40:11.39#ibcon#read 4, iclass 35, count 0 2006.281.07:40:11.39#ibcon#about to read 5, iclass 35, count 0 2006.281.07:40:11.39#ibcon#read 5, iclass 35, count 0 2006.281.07:40:11.39#ibcon#about to read 6, iclass 35, count 0 2006.281.07:40:11.39#ibcon#read 6, iclass 35, count 0 2006.281.07:40:11.39#ibcon#end of sib2, iclass 35, count 0 2006.281.07:40:11.39#ibcon#*after write, iclass 35, count 0 2006.281.07:40:11.39#ibcon#*before return 0, iclass 35, count 0 2006.281.07:40:11.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:40:11.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:40:11.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:40:11.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:40:11.39$vc4f8/va=7,6 2006.281.07:40:11.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:40:11.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:40:11.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:11.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:40:11.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:40:11.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:40:11.43#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:40:11.43#ibcon#first serial, iclass 37, count 2 2006.281.07:40:11.43#ibcon#enter sib2, iclass 37, count 2 2006.281.07:40:11.43#ibcon#flushed, iclass 37, count 2 2006.281.07:40:11.43#ibcon#about to write, iclass 37, count 2 2006.281.07:40:11.43#ibcon#wrote, iclass 37, count 2 2006.281.07:40:11.43#ibcon#about to read 3, iclass 37, count 2 2006.281.07:40:11.46#ibcon#read 3, iclass 37, count 2 2006.281.07:40:11.46#ibcon#about to read 4, iclass 37, count 2 2006.281.07:40:11.46#ibcon#read 4, iclass 37, count 2 2006.281.07:40:11.46#ibcon#about to read 5, iclass 37, count 2 2006.281.07:40:11.46#ibcon#read 5, iclass 37, count 2 2006.281.07:40:11.46#ibcon#about to read 6, iclass 37, count 2 2006.281.07:40:11.46#ibcon#read 6, iclass 37, count 2 2006.281.07:40:11.46#ibcon#end of sib2, iclass 37, count 2 2006.281.07:40:11.46#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:40:11.46#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:40:11.46#ibcon#[25=AT07-06\r\n] 2006.281.07:40:11.46#ibcon#*before write, iclass 37, count 2 2006.281.07:40:11.46#ibcon#enter sib2, iclass 37, count 2 2006.281.07:40:11.46#ibcon#flushed, iclass 37, count 2 2006.281.07:40:11.46#ibcon#about to write, iclass 37, count 2 2006.281.07:40:11.46#ibcon#wrote, iclass 37, count 2 2006.281.07:40:11.46#ibcon#about to read 3, iclass 37, count 2 2006.281.07:40:11.49#ibcon#read 3, iclass 37, count 2 2006.281.07:40:11.49#ibcon#about to read 4, iclass 37, count 2 2006.281.07:40:11.49#ibcon#read 4, iclass 37, count 2 2006.281.07:40:11.49#ibcon#about to read 5, iclass 37, count 2 2006.281.07:40:11.49#ibcon#read 5, iclass 37, count 2 2006.281.07:40:11.49#ibcon#about to read 6, iclass 37, count 2 2006.281.07:40:11.49#ibcon#read 6, iclass 37, count 2 2006.281.07:40:11.49#ibcon#end of sib2, iclass 37, count 2 2006.281.07:40:11.49#ibcon#*after write, iclass 37, count 2 2006.281.07:40:11.49#ibcon#*before return 0, iclass 37, count 2 2006.281.07:40:11.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:40:11.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:40:11.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:40:11.49#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:11.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:40:11.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:40:11.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:40:11.61#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:40:11.61#ibcon#first serial, iclass 37, count 0 2006.281.07:40:11.61#ibcon#enter sib2, iclass 37, count 0 2006.281.07:40:11.61#ibcon#flushed, iclass 37, count 0 2006.281.07:40:11.61#ibcon#about to write, iclass 37, count 0 2006.281.07:40:11.61#ibcon#wrote, iclass 37, count 0 2006.281.07:40:11.61#ibcon#about to read 3, iclass 37, count 0 2006.281.07:40:11.63#ibcon#read 3, iclass 37, count 0 2006.281.07:40:11.63#ibcon#about to read 4, iclass 37, count 0 2006.281.07:40:11.63#ibcon#read 4, iclass 37, count 0 2006.281.07:40:11.63#ibcon#about to read 5, iclass 37, count 0 2006.281.07:40:11.63#ibcon#read 5, iclass 37, count 0 2006.281.07:40:11.63#ibcon#about to read 6, iclass 37, count 0 2006.281.07:40:11.63#ibcon#read 6, iclass 37, count 0 2006.281.07:40:11.63#ibcon#end of sib2, iclass 37, count 0 2006.281.07:40:11.63#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:40:11.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:40:11.63#ibcon#[25=USB\r\n] 2006.281.07:40:11.63#ibcon#*before write, iclass 37, count 0 2006.281.07:40:11.63#ibcon#enter sib2, iclass 37, count 0 2006.281.07:40:11.63#ibcon#flushed, iclass 37, count 0 2006.281.07:40:11.63#ibcon#about to write, iclass 37, count 0 2006.281.07:40:11.63#ibcon#wrote, iclass 37, count 0 2006.281.07:40:11.63#ibcon#about to read 3, iclass 37, count 0 2006.281.07:40:11.66#ibcon#read 3, iclass 37, count 0 2006.281.07:40:11.66#ibcon#about to read 4, iclass 37, count 0 2006.281.07:40:11.66#ibcon#read 4, iclass 37, count 0 2006.281.07:40:11.66#ibcon#about to read 5, iclass 37, count 0 2006.281.07:40:11.66#ibcon#read 5, iclass 37, count 0 2006.281.07:40:11.66#ibcon#about to read 6, iclass 37, count 0 2006.281.07:40:11.66#ibcon#read 6, iclass 37, count 0 2006.281.07:40:11.66#ibcon#end of sib2, iclass 37, count 0 2006.281.07:40:11.66#ibcon#*after write, iclass 37, count 0 2006.281.07:40:11.66#ibcon#*before return 0, iclass 37, count 0 2006.281.07:40:11.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:40:11.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:40:11.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:40:11.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:40:11.66$vc4f8/valo=8,852.99 2006.281.07:40:11.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:40:11.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:40:11.66#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:11.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:40:11.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:40:11.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:40:11.66#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:40:11.66#ibcon#first serial, iclass 39, count 0 2006.281.07:40:11.66#ibcon#enter sib2, iclass 39, count 0 2006.281.07:40:11.66#ibcon#flushed, iclass 39, count 0 2006.281.07:40:11.66#ibcon#about to write, iclass 39, count 0 2006.281.07:40:11.66#ibcon#wrote, iclass 39, count 0 2006.281.07:40:11.66#ibcon#about to read 3, iclass 39, count 0 2006.281.07:40:11.68#ibcon#read 3, iclass 39, count 0 2006.281.07:40:11.68#ibcon#about to read 4, iclass 39, count 0 2006.281.07:40:11.68#ibcon#read 4, iclass 39, count 0 2006.281.07:40:11.68#ibcon#about to read 5, iclass 39, count 0 2006.281.07:40:11.68#ibcon#read 5, iclass 39, count 0 2006.281.07:40:11.68#ibcon#about to read 6, iclass 39, count 0 2006.281.07:40:11.68#ibcon#read 6, iclass 39, count 0 2006.281.07:40:11.68#ibcon#end of sib2, iclass 39, count 0 2006.281.07:40:11.68#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:40:11.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:40:11.71#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:40:11.71#ibcon#*before write, iclass 39, count 0 2006.281.07:40:11.71#ibcon#enter sib2, iclass 39, count 0 2006.281.07:40:11.71#ibcon#flushed, iclass 39, count 0 2006.281.07:40:11.71#ibcon#about to write, iclass 39, count 0 2006.281.07:40:11.71#ibcon#wrote, iclass 39, count 0 2006.281.07:40:11.71#ibcon#about to read 3, iclass 39, count 0 2006.281.07:40:11.74#ibcon#read 3, iclass 39, count 0 2006.281.07:40:11.74#ibcon#about to read 4, iclass 39, count 0 2006.281.07:40:11.74#ibcon#read 4, iclass 39, count 0 2006.281.07:40:11.74#ibcon#about to read 5, iclass 39, count 0 2006.281.07:40:11.74#ibcon#read 5, iclass 39, count 0 2006.281.07:40:11.74#ibcon#about to read 6, iclass 39, count 0 2006.281.07:40:11.74#ibcon#read 6, iclass 39, count 0 2006.281.07:40:11.74#ibcon#end of sib2, iclass 39, count 0 2006.281.07:40:11.74#ibcon#*after write, iclass 39, count 0 2006.281.07:40:11.74#ibcon#*before return 0, iclass 39, count 0 2006.281.07:40:11.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:40:11.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:40:11.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:40:11.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:40:11.74$vc4f8/va=8,6 2006.281.07:40:11.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:40:11.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:40:11.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:11.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:40:11.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:40:11.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:40:11.78#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:40:11.78#ibcon#first serial, iclass 3, count 2 2006.281.07:40:11.78#ibcon#enter sib2, iclass 3, count 2 2006.281.07:40:11.78#ibcon#flushed, iclass 3, count 2 2006.281.07:40:11.78#ibcon#about to write, iclass 3, count 2 2006.281.07:40:11.78#ibcon#wrote, iclass 3, count 2 2006.281.07:40:11.78#ibcon#about to read 3, iclass 3, count 2 2006.281.07:40:11.80#ibcon#read 3, iclass 3, count 2 2006.281.07:40:11.80#ibcon#about to read 4, iclass 3, count 2 2006.281.07:40:11.80#ibcon#read 4, iclass 3, count 2 2006.281.07:40:11.80#ibcon#about to read 5, iclass 3, count 2 2006.281.07:40:11.80#ibcon#read 5, iclass 3, count 2 2006.281.07:40:11.80#ibcon#about to read 6, iclass 3, count 2 2006.281.07:40:11.80#ibcon#read 6, iclass 3, count 2 2006.281.07:40:11.80#ibcon#end of sib2, iclass 3, count 2 2006.281.07:40:11.80#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:40:11.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:40:11.80#ibcon#[25=AT08-06\r\n] 2006.281.07:40:11.80#ibcon#*before write, iclass 3, count 2 2006.281.07:40:11.80#ibcon#enter sib2, iclass 3, count 2 2006.281.07:40:11.80#ibcon#flushed, iclass 3, count 2 2006.281.07:40:11.80#ibcon#about to write, iclass 3, count 2 2006.281.07:40:11.80#ibcon#wrote, iclass 3, count 2 2006.281.07:40:11.80#ibcon#about to read 3, iclass 3, count 2 2006.281.07:40:11.83#ibcon#read 3, iclass 3, count 2 2006.281.07:40:11.83#ibcon#about to read 4, iclass 3, count 2 2006.281.07:40:11.83#ibcon#read 4, iclass 3, count 2 2006.281.07:40:11.83#ibcon#about to read 5, iclass 3, count 2 2006.281.07:40:11.83#ibcon#read 5, iclass 3, count 2 2006.281.07:40:11.83#ibcon#about to read 6, iclass 3, count 2 2006.281.07:40:11.83#ibcon#read 6, iclass 3, count 2 2006.281.07:40:11.83#ibcon#end of sib2, iclass 3, count 2 2006.281.07:40:11.83#ibcon#*after write, iclass 3, count 2 2006.281.07:40:11.83#ibcon#*before return 0, iclass 3, count 2 2006.281.07:40:11.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:40:11.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:40:11.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:40:11.83#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:11.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:40:11.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:40:11.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:40:11.95#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:40:11.95#ibcon#first serial, iclass 3, count 0 2006.281.07:40:11.95#ibcon#enter sib2, iclass 3, count 0 2006.281.07:40:11.96#ibcon#flushed, iclass 3, count 0 2006.281.07:40:11.96#ibcon#about to write, iclass 3, count 0 2006.281.07:40:11.96#ibcon#wrote, iclass 3, count 0 2006.281.07:40:11.96#ibcon#about to read 3, iclass 3, count 0 2006.281.07:40:11.97#ibcon#read 3, iclass 3, count 0 2006.281.07:40:11.97#ibcon#about to read 4, iclass 3, count 0 2006.281.07:40:11.97#ibcon#read 4, iclass 3, count 0 2006.281.07:40:11.97#ibcon#about to read 5, iclass 3, count 0 2006.281.07:40:11.97#ibcon#read 5, iclass 3, count 0 2006.281.07:40:11.97#ibcon#about to read 6, iclass 3, count 0 2006.281.07:40:11.97#ibcon#read 6, iclass 3, count 0 2006.281.07:40:11.97#ibcon#end of sib2, iclass 3, count 0 2006.281.07:40:11.97#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:40:11.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:40:11.97#ibcon#[25=USB\r\n] 2006.281.07:40:11.97#ibcon#*before write, iclass 3, count 0 2006.281.07:40:11.97#ibcon#enter sib2, iclass 3, count 0 2006.281.07:40:11.97#ibcon#flushed, iclass 3, count 0 2006.281.07:40:11.97#ibcon#about to write, iclass 3, count 0 2006.281.07:40:11.97#ibcon#wrote, iclass 3, count 0 2006.281.07:40:11.97#ibcon#about to read 3, iclass 3, count 0 2006.281.07:40:12.00#ibcon#read 3, iclass 3, count 0 2006.281.07:40:12.00#ibcon#about to read 4, iclass 3, count 0 2006.281.07:40:12.00#ibcon#read 4, iclass 3, count 0 2006.281.07:40:12.00#ibcon#about to read 5, iclass 3, count 0 2006.281.07:40:12.00#ibcon#read 5, iclass 3, count 0 2006.281.07:40:12.00#ibcon#about to read 6, iclass 3, count 0 2006.281.07:40:12.00#ibcon#read 6, iclass 3, count 0 2006.281.07:40:12.00#ibcon#end of sib2, iclass 3, count 0 2006.281.07:40:12.00#ibcon#*after write, iclass 3, count 0 2006.281.07:40:12.00#ibcon#*before return 0, iclass 3, count 0 2006.281.07:40:12.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:40:12.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:40:12.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:40:12.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:40:12.00$vc4f8/vblo=1,632.99 2006.281.07:40:12.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:40:12.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:40:12.00#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:12.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:40:12.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:40:12.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:40:12.00#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:40:12.00#ibcon#first serial, iclass 5, count 0 2006.281.07:40:12.00#ibcon#enter sib2, iclass 5, count 0 2006.281.07:40:12.00#ibcon#flushed, iclass 5, count 0 2006.281.07:40:12.00#ibcon#about to write, iclass 5, count 0 2006.281.07:40:12.00#ibcon#wrote, iclass 5, count 0 2006.281.07:40:12.00#ibcon#about to read 3, iclass 5, count 0 2006.281.07:40:12.02#ibcon#read 3, iclass 5, count 0 2006.281.07:40:12.02#ibcon#about to read 4, iclass 5, count 0 2006.281.07:40:12.02#ibcon#read 4, iclass 5, count 0 2006.281.07:40:12.02#ibcon#about to read 5, iclass 5, count 0 2006.281.07:40:12.02#ibcon#read 5, iclass 5, count 0 2006.281.07:40:12.02#ibcon#about to read 6, iclass 5, count 0 2006.281.07:40:12.02#ibcon#read 6, iclass 5, count 0 2006.281.07:40:12.02#ibcon#end of sib2, iclass 5, count 0 2006.281.07:40:12.02#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:40:12.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:40:12.02#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:40:12.02#ibcon#*before write, iclass 5, count 0 2006.281.07:40:12.02#ibcon#enter sib2, iclass 5, count 0 2006.281.07:40:12.02#ibcon#flushed, iclass 5, count 0 2006.281.07:40:12.02#ibcon#about to write, iclass 5, count 0 2006.281.07:40:12.02#ibcon#wrote, iclass 5, count 0 2006.281.07:40:12.02#ibcon#about to read 3, iclass 5, count 0 2006.281.07:40:12.07#ibcon#read 3, iclass 5, count 0 2006.281.07:40:12.07#ibcon#about to read 4, iclass 5, count 0 2006.281.07:40:12.07#ibcon#read 4, iclass 5, count 0 2006.281.07:40:12.07#ibcon#about to read 5, iclass 5, count 0 2006.281.07:40:12.07#ibcon#read 5, iclass 5, count 0 2006.281.07:40:12.07#ibcon#about to read 6, iclass 5, count 0 2006.281.07:40:12.07#ibcon#read 6, iclass 5, count 0 2006.281.07:40:12.07#ibcon#end of sib2, iclass 5, count 0 2006.281.07:40:12.07#ibcon#*after write, iclass 5, count 0 2006.281.07:40:12.07#ibcon#*before return 0, iclass 5, count 0 2006.281.07:40:12.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:40:12.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:40:12.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:40:12.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:40:12.07$vc4f8/vb=1,4 2006.281.07:40:12.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:40:12.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:40:12.07#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:12.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:40:12.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:40:12.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:40:12.07#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:40:12.07#ibcon#first serial, iclass 7, count 2 2006.281.07:40:12.07#ibcon#enter sib2, iclass 7, count 2 2006.281.07:40:12.07#ibcon#flushed, iclass 7, count 2 2006.281.07:40:12.07#ibcon#about to write, iclass 7, count 2 2006.281.07:40:12.07#ibcon#wrote, iclass 7, count 2 2006.281.07:40:12.07#ibcon#about to read 3, iclass 7, count 2 2006.281.07:40:12.08#ibcon#read 3, iclass 7, count 2 2006.281.07:40:12.08#ibcon#about to read 4, iclass 7, count 2 2006.281.07:40:12.08#ibcon#read 4, iclass 7, count 2 2006.281.07:40:12.08#ibcon#about to read 5, iclass 7, count 2 2006.281.07:40:12.08#ibcon#read 5, iclass 7, count 2 2006.281.07:40:12.08#ibcon#about to read 6, iclass 7, count 2 2006.281.07:40:12.08#ibcon#read 6, iclass 7, count 2 2006.281.07:40:12.08#ibcon#end of sib2, iclass 7, count 2 2006.281.07:40:12.08#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:40:12.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:40:12.08#ibcon#[27=AT01-04\r\n] 2006.281.07:40:12.08#ibcon#*before write, iclass 7, count 2 2006.281.07:40:12.08#ibcon#enter sib2, iclass 7, count 2 2006.281.07:40:12.08#ibcon#flushed, iclass 7, count 2 2006.281.07:40:12.12#ibcon#about to write, iclass 7, count 2 2006.281.07:40:12.12#ibcon#wrote, iclass 7, count 2 2006.281.07:40:12.12#ibcon#about to read 3, iclass 7, count 2 2006.281.07:40:12.14#ibcon#read 3, iclass 7, count 2 2006.281.07:40:12.14#ibcon#about to read 4, iclass 7, count 2 2006.281.07:40:12.14#ibcon#read 4, iclass 7, count 2 2006.281.07:40:12.14#ibcon#about to read 5, iclass 7, count 2 2006.281.07:40:12.14#ibcon#read 5, iclass 7, count 2 2006.281.07:40:12.14#ibcon#about to read 6, iclass 7, count 2 2006.281.07:40:12.14#ibcon#read 6, iclass 7, count 2 2006.281.07:40:12.14#ibcon#end of sib2, iclass 7, count 2 2006.281.07:40:12.14#ibcon#*after write, iclass 7, count 2 2006.281.07:40:12.14#ibcon#*before return 0, iclass 7, count 2 2006.281.07:40:12.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:40:12.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:40:12.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:40:12.14#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:12.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:40:12.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:40:12.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:40:12.27#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:40:12.27#ibcon#first serial, iclass 7, count 0 2006.281.07:40:12.27#ibcon#enter sib2, iclass 7, count 0 2006.281.07:40:12.27#ibcon#flushed, iclass 7, count 0 2006.281.07:40:12.27#ibcon#about to write, iclass 7, count 0 2006.281.07:40:12.27#ibcon#wrote, iclass 7, count 0 2006.281.07:40:12.27#ibcon#about to read 3, iclass 7, count 0 2006.281.07:40:12.28#ibcon#read 3, iclass 7, count 0 2006.281.07:40:12.28#ibcon#about to read 4, iclass 7, count 0 2006.281.07:40:12.28#ibcon#read 4, iclass 7, count 0 2006.281.07:40:12.28#ibcon#about to read 5, iclass 7, count 0 2006.281.07:40:12.28#ibcon#read 5, iclass 7, count 0 2006.281.07:40:12.28#ibcon#about to read 6, iclass 7, count 0 2006.281.07:40:12.28#ibcon#read 6, iclass 7, count 0 2006.281.07:40:12.28#ibcon#end of sib2, iclass 7, count 0 2006.281.07:40:12.28#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:40:12.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:40:12.28#ibcon#[27=USB\r\n] 2006.281.07:40:12.28#ibcon#*before write, iclass 7, count 0 2006.281.07:40:12.28#ibcon#enter sib2, iclass 7, count 0 2006.281.07:40:12.28#ibcon#flushed, iclass 7, count 0 2006.281.07:40:12.28#ibcon#about to write, iclass 7, count 0 2006.281.07:40:12.28#ibcon#wrote, iclass 7, count 0 2006.281.07:40:12.28#ibcon#about to read 3, iclass 7, count 0 2006.281.07:40:12.31#ibcon#read 3, iclass 7, count 0 2006.281.07:40:12.31#ibcon#about to read 4, iclass 7, count 0 2006.281.07:40:12.31#ibcon#read 4, iclass 7, count 0 2006.281.07:40:12.31#ibcon#about to read 5, iclass 7, count 0 2006.281.07:40:12.31#ibcon#read 5, iclass 7, count 0 2006.281.07:40:12.31#ibcon#about to read 6, iclass 7, count 0 2006.281.07:40:12.31#ibcon#read 6, iclass 7, count 0 2006.281.07:40:12.31#ibcon#end of sib2, iclass 7, count 0 2006.281.07:40:12.31#ibcon#*after write, iclass 7, count 0 2006.281.07:40:12.31#ibcon#*before return 0, iclass 7, count 0 2006.281.07:40:12.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:40:12.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:40:12.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:40:12.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:40:12.31$vc4f8/vblo=2,640.99 2006.281.07:40:12.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:40:12.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:40:12.31#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:12.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:12.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:12.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:12.31#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:40:12.31#ibcon#first serial, iclass 11, count 0 2006.281.07:40:12.31#ibcon#enter sib2, iclass 11, count 0 2006.281.07:40:12.31#ibcon#flushed, iclass 11, count 0 2006.281.07:40:12.31#ibcon#about to write, iclass 11, count 0 2006.281.07:40:12.31#ibcon#wrote, iclass 11, count 0 2006.281.07:40:12.31#ibcon#about to read 3, iclass 11, count 0 2006.281.07:40:12.33#ibcon#read 3, iclass 11, count 0 2006.281.07:40:12.33#ibcon#about to read 4, iclass 11, count 0 2006.281.07:40:12.33#ibcon#read 4, iclass 11, count 0 2006.281.07:40:12.33#ibcon#about to read 5, iclass 11, count 0 2006.281.07:40:12.33#ibcon#read 5, iclass 11, count 0 2006.281.07:40:12.33#ibcon#about to read 6, iclass 11, count 0 2006.281.07:40:12.33#ibcon#read 6, iclass 11, count 0 2006.281.07:40:12.33#ibcon#end of sib2, iclass 11, count 0 2006.281.07:40:12.33#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:40:12.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:40:12.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:40:12.33#ibcon#*before write, iclass 11, count 0 2006.281.07:40:12.33#ibcon#enter sib2, iclass 11, count 0 2006.281.07:40:12.33#ibcon#flushed, iclass 11, count 0 2006.281.07:40:12.33#ibcon#about to write, iclass 11, count 0 2006.281.07:40:12.33#ibcon#wrote, iclass 11, count 0 2006.281.07:40:12.33#ibcon#about to read 3, iclass 11, count 0 2006.281.07:40:12.37#ibcon#read 3, iclass 11, count 0 2006.281.07:40:12.37#ibcon#about to read 4, iclass 11, count 0 2006.281.07:40:12.37#ibcon#read 4, iclass 11, count 0 2006.281.07:40:12.37#ibcon#about to read 5, iclass 11, count 0 2006.281.07:40:12.37#ibcon#read 5, iclass 11, count 0 2006.281.07:40:12.37#ibcon#about to read 6, iclass 11, count 0 2006.281.07:40:12.37#ibcon#read 6, iclass 11, count 0 2006.281.07:40:12.37#ibcon#end of sib2, iclass 11, count 0 2006.281.07:40:12.37#ibcon#*after write, iclass 11, count 0 2006.281.07:40:12.37#ibcon#*before return 0, iclass 11, count 0 2006.281.07:40:12.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:12.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:40:12.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:40:12.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:40:12.37$vc4f8/vb=2,5 2006.281.07:40:12.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:40:12.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:40:12.37#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:12.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:12.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:12.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:12.43#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:40:12.43#ibcon#first serial, iclass 13, count 2 2006.281.07:40:12.43#ibcon#enter sib2, iclass 13, count 2 2006.281.07:40:12.43#ibcon#flushed, iclass 13, count 2 2006.281.07:40:12.43#ibcon#about to write, iclass 13, count 2 2006.281.07:40:12.43#ibcon#wrote, iclass 13, count 2 2006.281.07:40:12.43#ibcon#about to read 3, iclass 13, count 2 2006.281.07:40:12.45#ibcon#read 3, iclass 13, count 2 2006.281.07:40:12.45#ibcon#about to read 4, iclass 13, count 2 2006.281.07:40:12.45#ibcon#read 4, iclass 13, count 2 2006.281.07:40:12.45#ibcon#about to read 5, iclass 13, count 2 2006.281.07:40:12.45#ibcon#read 5, iclass 13, count 2 2006.281.07:40:12.45#ibcon#about to read 6, iclass 13, count 2 2006.281.07:40:12.45#ibcon#read 6, iclass 13, count 2 2006.281.07:40:12.45#ibcon#end of sib2, iclass 13, count 2 2006.281.07:40:12.45#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:40:12.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:40:12.45#ibcon#[27=AT02-05\r\n] 2006.281.07:40:12.45#ibcon#*before write, iclass 13, count 2 2006.281.07:40:12.45#ibcon#enter sib2, iclass 13, count 2 2006.281.07:40:12.45#ibcon#flushed, iclass 13, count 2 2006.281.07:40:12.45#ibcon#about to write, iclass 13, count 2 2006.281.07:40:12.45#ibcon#wrote, iclass 13, count 2 2006.281.07:40:12.45#ibcon#about to read 3, iclass 13, count 2 2006.281.07:40:12.48#ibcon#read 3, iclass 13, count 2 2006.281.07:40:12.48#ibcon#about to read 4, iclass 13, count 2 2006.281.07:40:12.48#ibcon#read 4, iclass 13, count 2 2006.281.07:40:12.48#ibcon#about to read 5, iclass 13, count 2 2006.281.07:40:12.48#ibcon#read 5, iclass 13, count 2 2006.281.07:40:12.48#ibcon#about to read 6, iclass 13, count 2 2006.281.07:40:12.48#ibcon#read 6, iclass 13, count 2 2006.281.07:40:12.48#ibcon#end of sib2, iclass 13, count 2 2006.281.07:40:12.48#ibcon#*after write, iclass 13, count 2 2006.281.07:40:12.48#ibcon#*before return 0, iclass 13, count 2 2006.281.07:40:12.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:12.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:40:12.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:40:12.48#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:12.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:12.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:12.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:12.60#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:40:12.60#ibcon#first serial, iclass 13, count 0 2006.281.07:40:12.60#ibcon#enter sib2, iclass 13, count 0 2006.281.07:40:12.60#ibcon#flushed, iclass 13, count 0 2006.281.07:40:12.60#ibcon#about to write, iclass 13, count 0 2006.281.07:40:12.60#ibcon#wrote, iclass 13, count 0 2006.281.07:40:12.60#ibcon#about to read 3, iclass 13, count 0 2006.281.07:40:12.62#ibcon#read 3, iclass 13, count 0 2006.281.07:40:12.62#ibcon#about to read 4, iclass 13, count 0 2006.281.07:40:12.62#ibcon#read 4, iclass 13, count 0 2006.281.07:40:12.62#ibcon#about to read 5, iclass 13, count 0 2006.281.07:40:12.62#ibcon#read 5, iclass 13, count 0 2006.281.07:40:12.62#ibcon#about to read 6, iclass 13, count 0 2006.281.07:40:12.62#ibcon#read 6, iclass 13, count 0 2006.281.07:40:12.62#ibcon#end of sib2, iclass 13, count 0 2006.281.07:40:12.62#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:40:12.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:40:12.62#ibcon#[27=USB\r\n] 2006.281.07:40:12.62#ibcon#*before write, iclass 13, count 0 2006.281.07:40:12.62#ibcon#enter sib2, iclass 13, count 0 2006.281.07:40:12.62#ibcon#flushed, iclass 13, count 0 2006.281.07:40:12.62#ibcon#about to write, iclass 13, count 0 2006.281.07:40:12.62#ibcon#wrote, iclass 13, count 0 2006.281.07:40:12.62#ibcon#about to read 3, iclass 13, count 0 2006.281.07:40:12.66#ibcon#read 3, iclass 13, count 0 2006.281.07:40:12.66#ibcon#about to read 4, iclass 13, count 0 2006.281.07:40:12.66#ibcon#read 4, iclass 13, count 0 2006.281.07:40:12.66#ibcon#about to read 5, iclass 13, count 0 2006.281.07:40:12.66#ibcon#read 5, iclass 13, count 0 2006.281.07:40:12.66#ibcon#about to read 6, iclass 13, count 0 2006.281.07:40:12.66#ibcon#read 6, iclass 13, count 0 2006.281.07:40:12.66#ibcon#end of sib2, iclass 13, count 0 2006.281.07:40:12.66#ibcon#*after write, iclass 13, count 0 2006.281.07:40:12.66#ibcon#*before return 0, iclass 13, count 0 2006.281.07:40:12.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:12.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:40:12.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:40:12.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:40:12.66$vc4f8/vblo=3,656.99 2006.281.07:40:12.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:40:12.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:40:12.66#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:12.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:12.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:12.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:12.66#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:40:12.66#ibcon#first serial, iclass 15, count 0 2006.281.07:40:12.66#ibcon#enter sib2, iclass 15, count 0 2006.281.07:40:12.66#ibcon#flushed, iclass 15, count 0 2006.281.07:40:12.66#ibcon#about to write, iclass 15, count 0 2006.281.07:40:12.66#ibcon#wrote, iclass 15, count 0 2006.281.07:40:12.66#ibcon#about to read 3, iclass 15, count 0 2006.281.07:40:12.67#ibcon#read 3, iclass 15, count 0 2006.281.07:40:12.67#ibcon#about to read 4, iclass 15, count 0 2006.281.07:40:12.67#ibcon#read 4, iclass 15, count 0 2006.281.07:40:12.67#ibcon#about to read 5, iclass 15, count 0 2006.281.07:40:12.67#ibcon#read 5, iclass 15, count 0 2006.281.07:40:12.67#ibcon#about to read 6, iclass 15, count 0 2006.281.07:40:12.67#ibcon#read 6, iclass 15, count 0 2006.281.07:40:12.67#ibcon#end of sib2, iclass 15, count 0 2006.281.07:40:12.67#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:40:12.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:40:12.70#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:40:12.70#ibcon#*before write, iclass 15, count 0 2006.281.07:40:12.70#ibcon#enter sib2, iclass 15, count 0 2006.281.07:40:12.70#ibcon#flushed, iclass 15, count 0 2006.281.07:40:12.70#ibcon#about to write, iclass 15, count 0 2006.281.07:40:12.70#ibcon#wrote, iclass 15, count 0 2006.281.07:40:12.70#ibcon#about to read 3, iclass 15, count 0 2006.281.07:40:12.73#ibcon#read 3, iclass 15, count 0 2006.281.07:40:12.73#ibcon#about to read 4, iclass 15, count 0 2006.281.07:40:12.73#ibcon#read 4, iclass 15, count 0 2006.281.07:40:12.73#ibcon#about to read 5, iclass 15, count 0 2006.281.07:40:12.73#ibcon#read 5, iclass 15, count 0 2006.281.07:40:12.73#ibcon#about to read 6, iclass 15, count 0 2006.281.07:40:12.73#ibcon#read 6, iclass 15, count 0 2006.281.07:40:12.73#ibcon#end of sib2, iclass 15, count 0 2006.281.07:40:12.73#ibcon#*after write, iclass 15, count 0 2006.281.07:40:12.73#ibcon#*before return 0, iclass 15, count 0 2006.281.07:40:12.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:12.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:40:12.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:40:12.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:40:12.73$vc4f8/vb=3,4 2006.281.07:40:12.73#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:40:12.73#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:40:12.73#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:12.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:12.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:12.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:12.79#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:40:12.79#ibcon#first serial, iclass 17, count 2 2006.281.07:40:12.79#ibcon#enter sib2, iclass 17, count 2 2006.281.07:40:12.79#ibcon#flushed, iclass 17, count 2 2006.281.07:40:12.79#ibcon#about to write, iclass 17, count 2 2006.281.07:40:12.79#ibcon#wrote, iclass 17, count 2 2006.281.07:40:12.79#ibcon#about to read 3, iclass 17, count 2 2006.281.07:40:12.80#ibcon#read 3, iclass 17, count 2 2006.281.07:40:12.80#ibcon#about to read 4, iclass 17, count 2 2006.281.07:40:12.80#ibcon#read 4, iclass 17, count 2 2006.281.07:40:12.80#ibcon#about to read 5, iclass 17, count 2 2006.281.07:40:12.80#ibcon#read 5, iclass 17, count 2 2006.281.07:40:12.80#ibcon#about to read 6, iclass 17, count 2 2006.281.07:40:12.80#ibcon#read 6, iclass 17, count 2 2006.281.07:40:12.80#ibcon#end of sib2, iclass 17, count 2 2006.281.07:40:12.80#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:40:12.80#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:40:12.80#ibcon#[27=AT03-04\r\n] 2006.281.07:40:12.80#ibcon#*before write, iclass 17, count 2 2006.281.07:40:12.80#ibcon#enter sib2, iclass 17, count 2 2006.281.07:40:12.80#ibcon#flushed, iclass 17, count 2 2006.281.07:40:12.80#ibcon#about to write, iclass 17, count 2 2006.281.07:40:12.80#ibcon#wrote, iclass 17, count 2 2006.281.07:40:12.80#ibcon#about to read 3, iclass 17, count 2 2006.281.07:40:12.84#ibcon#read 3, iclass 17, count 2 2006.281.07:40:12.84#ibcon#about to read 4, iclass 17, count 2 2006.281.07:40:12.84#ibcon#read 4, iclass 17, count 2 2006.281.07:40:12.84#ibcon#about to read 5, iclass 17, count 2 2006.281.07:40:12.84#ibcon#read 5, iclass 17, count 2 2006.281.07:40:12.84#ibcon#about to read 6, iclass 17, count 2 2006.281.07:40:12.84#ibcon#read 6, iclass 17, count 2 2006.281.07:40:12.84#ibcon#end of sib2, iclass 17, count 2 2006.281.07:40:12.84#ibcon#*after write, iclass 17, count 2 2006.281.07:40:12.84#ibcon#*before return 0, iclass 17, count 2 2006.281.07:40:12.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:12.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:40:12.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:40:12.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:12.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:12.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:12.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:12.96#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:40:12.96#ibcon#first serial, iclass 17, count 0 2006.281.07:40:12.96#ibcon#enter sib2, iclass 17, count 0 2006.281.07:40:12.96#ibcon#flushed, iclass 17, count 0 2006.281.07:40:12.96#ibcon#about to write, iclass 17, count 0 2006.281.07:40:12.96#ibcon#wrote, iclass 17, count 0 2006.281.07:40:12.96#ibcon#about to read 3, iclass 17, count 0 2006.281.07:40:12.97#ibcon#read 3, iclass 17, count 0 2006.281.07:40:12.97#ibcon#about to read 4, iclass 17, count 0 2006.281.07:40:12.97#ibcon#read 4, iclass 17, count 0 2006.281.07:40:12.97#ibcon#about to read 5, iclass 17, count 0 2006.281.07:40:12.97#ibcon#read 5, iclass 17, count 0 2006.281.07:40:12.97#ibcon#about to read 6, iclass 17, count 0 2006.281.07:40:12.97#ibcon#read 6, iclass 17, count 0 2006.281.07:40:12.97#ibcon#end of sib2, iclass 17, count 0 2006.281.07:40:12.97#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:40:12.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:40:12.97#ibcon#[27=USB\r\n] 2006.281.07:40:12.97#ibcon#*before write, iclass 17, count 0 2006.281.07:40:12.97#ibcon#enter sib2, iclass 17, count 0 2006.281.07:40:12.97#ibcon#flushed, iclass 17, count 0 2006.281.07:40:12.97#ibcon#about to write, iclass 17, count 0 2006.281.07:40:12.97#ibcon#wrote, iclass 17, count 0 2006.281.07:40:12.97#ibcon#about to read 3, iclass 17, count 0 2006.281.07:40:13.00#ibcon#read 3, iclass 17, count 0 2006.281.07:40:13.00#ibcon#about to read 4, iclass 17, count 0 2006.281.07:40:13.00#ibcon#read 4, iclass 17, count 0 2006.281.07:40:13.00#ibcon#about to read 5, iclass 17, count 0 2006.281.07:40:13.00#ibcon#read 5, iclass 17, count 0 2006.281.07:40:13.00#ibcon#about to read 6, iclass 17, count 0 2006.281.07:40:13.00#ibcon#read 6, iclass 17, count 0 2006.281.07:40:13.00#ibcon#end of sib2, iclass 17, count 0 2006.281.07:40:13.00#ibcon#*after write, iclass 17, count 0 2006.281.07:40:13.00#ibcon#*before return 0, iclass 17, count 0 2006.281.07:40:13.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:13.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:40:13.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:40:13.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:40:13.00$vc4f8/vblo=4,712.99 2006.281.07:40:13.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:40:13.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:40:13.00#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:13.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:13.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:13.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:13.00#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:40:13.00#ibcon#first serial, iclass 19, count 0 2006.281.07:40:13.00#ibcon#enter sib2, iclass 19, count 0 2006.281.07:40:13.00#ibcon#flushed, iclass 19, count 0 2006.281.07:40:13.00#ibcon#about to write, iclass 19, count 0 2006.281.07:40:13.00#ibcon#wrote, iclass 19, count 0 2006.281.07:40:13.00#ibcon#about to read 3, iclass 19, count 0 2006.281.07:40:13.02#ibcon#read 3, iclass 19, count 0 2006.281.07:40:13.02#ibcon#about to read 4, iclass 19, count 0 2006.281.07:40:13.02#ibcon#read 4, iclass 19, count 0 2006.281.07:40:13.02#ibcon#about to read 5, iclass 19, count 0 2006.281.07:40:13.02#ibcon#read 5, iclass 19, count 0 2006.281.07:40:13.02#ibcon#about to read 6, iclass 19, count 0 2006.281.07:40:13.02#ibcon#read 6, iclass 19, count 0 2006.281.07:40:13.02#ibcon#end of sib2, iclass 19, count 0 2006.281.07:40:13.02#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:40:13.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:40:13.02#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:40:13.02#ibcon#*before write, iclass 19, count 0 2006.281.07:40:13.02#ibcon#enter sib2, iclass 19, count 0 2006.281.07:40:13.02#ibcon#flushed, iclass 19, count 0 2006.281.07:40:13.02#ibcon#about to write, iclass 19, count 0 2006.281.07:40:13.02#ibcon#wrote, iclass 19, count 0 2006.281.07:40:13.02#ibcon#about to read 3, iclass 19, count 0 2006.281.07:40:13.06#ibcon#read 3, iclass 19, count 0 2006.281.07:40:13.06#ibcon#about to read 4, iclass 19, count 0 2006.281.07:40:13.06#ibcon#read 4, iclass 19, count 0 2006.281.07:40:13.06#ibcon#about to read 5, iclass 19, count 0 2006.281.07:40:13.06#ibcon#read 5, iclass 19, count 0 2006.281.07:40:13.06#ibcon#about to read 6, iclass 19, count 0 2006.281.07:40:13.06#ibcon#read 6, iclass 19, count 0 2006.281.07:40:13.06#ibcon#end of sib2, iclass 19, count 0 2006.281.07:40:13.06#ibcon#*after write, iclass 19, count 0 2006.281.07:40:13.06#ibcon#*before return 0, iclass 19, count 0 2006.281.07:40:13.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:13.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:40:13.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:40:13.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:40:13.06$vc4f8/vb=4,4 2006.281.07:40:13.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:40:13.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:40:13.06#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:13.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:13.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:13.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:13.12#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:40:13.12#ibcon#first serial, iclass 21, count 2 2006.281.07:40:13.12#ibcon#enter sib2, iclass 21, count 2 2006.281.07:40:13.12#ibcon#flushed, iclass 21, count 2 2006.281.07:40:13.12#ibcon#about to write, iclass 21, count 2 2006.281.07:40:13.12#ibcon#wrote, iclass 21, count 2 2006.281.07:40:13.12#ibcon#about to read 3, iclass 21, count 2 2006.281.07:40:13.15#ibcon#read 3, iclass 21, count 2 2006.281.07:40:13.15#ibcon#about to read 4, iclass 21, count 2 2006.281.07:40:13.15#ibcon#read 4, iclass 21, count 2 2006.281.07:40:13.15#ibcon#about to read 5, iclass 21, count 2 2006.281.07:40:13.15#ibcon#read 5, iclass 21, count 2 2006.281.07:40:13.15#ibcon#about to read 6, iclass 21, count 2 2006.281.07:40:13.15#ibcon#read 6, iclass 21, count 2 2006.281.07:40:13.15#ibcon#end of sib2, iclass 21, count 2 2006.281.07:40:13.15#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:40:13.15#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:40:13.15#ibcon#[27=AT04-04\r\n] 2006.281.07:40:13.15#ibcon#*before write, iclass 21, count 2 2006.281.07:40:13.15#ibcon#enter sib2, iclass 21, count 2 2006.281.07:40:13.15#ibcon#flushed, iclass 21, count 2 2006.281.07:40:13.15#ibcon#about to write, iclass 21, count 2 2006.281.07:40:13.15#ibcon#wrote, iclass 21, count 2 2006.281.07:40:13.15#ibcon#about to read 3, iclass 21, count 2 2006.281.07:40:13.18#ibcon#read 3, iclass 21, count 2 2006.281.07:40:13.18#ibcon#about to read 4, iclass 21, count 2 2006.281.07:40:13.18#ibcon#read 4, iclass 21, count 2 2006.281.07:40:13.18#ibcon#about to read 5, iclass 21, count 2 2006.281.07:40:13.18#ibcon#read 5, iclass 21, count 2 2006.281.07:40:13.18#ibcon#about to read 6, iclass 21, count 2 2006.281.07:40:13.18#ibcon#read 6, iclass 21, count 2 2006.281.07:40:13.18#ibcon#end of sib2, iclass 21, count 2 2006.281.07:40:13.18#ibcon#*after write, iclass 21, count 2 2006.281.07:40:13.18#ibcon#*before return 0, iclass 21, count 2 2006.281.07:40:13.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:13.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:40:13.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:40:13.18#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:13.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:13.30#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:13.30#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:13.30#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:40:13.30#ibcon#first serial, iclass 21, count 0 2006.281.07:40:13.30#ibcon#enter sib2, iclass 21, count 0 2006.281.07:40:13.30#ibcon#flushed, iclass 21, count 0 2006.281.07:40:13.30#ibcon#about to write, iclass 21, count 0 2006.281.07:40:13.30#ibcon#wrote, iclass 21, count 0 2006.281.07:40:13.30#ibcon#about to read 3, iclass 21, count 0 2006.281.07:40:13.32#ibcon#read 3, iclass 21, count 0 2006.281.07:40:13.32#ibcon#about to read 4, iclass 21, count 0 2006.281.07:40:13.32#ibcon#read 4, iclass 21, count 0 2006.281.07:40:13.32#ibcon#about to read 5, iclass 21, count 0 2006.281.07:40:13.32#ibcon#read 5, iclass 21, count 0 2006.281.07:40:13.32#ibcon#about to read 6, iclass 21, count 0 2006.281.07:40:13.32#ibcon#read 6, iclass 21, count 0 2006.281.07:40:13.32#ibcon#end of sib2, iclass 21, count 0 2006.281.07:40:13.32#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:40:13.32#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:40:13.32#ibcon#[27=USB\r\n] 2006.281.07:40:13.32#ibcon#*before write, iclass 21, count 0 2006.281.07:40:13.32#ibcon#enter sib2, iclass 21, count 0 2006.281.07:40:13.32#ibcon#flushed, iclass 21, count 0 2006.281.07:40:13.32#ibcon#about to write, iclass 21, count 0 2006.281.07:40:13.32#ibcon#wrote, iclass 21, count 0 2006.281.07:40:13.32#ibcon#about to read 3, iclass 21, count 0 2006.281.07:40:13.36#ibcon#read 3, iclass 21, count 0 2006.281.07:40:13.36#ibcon#about to read 4, iclass 21, count 0 2006.281.07:40:13.36#ibcon#read 4, iclass 21, count 0 2006.281.07:40:13.36#ibcon#about to read 5, iclass 21, count 0 2006.281.07:40:13.36#ibcon#read 5, iclass 21, count 0 2006.281.07:40:13.36#ibcon#about to read 6, iclass 21, count 0 2006.281.07:40:13.36#ibcon#read 6, iclass 21, count 0 2006.281.07:40:13.36#ibcon#end of sib2, iclass 21, count 0 2006.281.07:40:13.36#ibcon#*after write, iclass 21, count 0 2006.281.07:40:13.36#ibcon#*before return 0, iclass 21, count 0 2006.281.07:40:13.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:13.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:40:13.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:40:13.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:40:13.36$vc4f8/vblo=5,744.99 2006.281.07:40:13.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:40:13.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:40:13.36#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:13.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:13.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:13.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:13.36#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:40:13.36#ibcon#first serial, iclass 23, count 0 2006.281.07:40:13.36#ibcon#enter sib2, iclass 23, count 0 2006.281.07:40:13.36#ibcon#flushed, iclass 23, count 0 2006.281.07:40:13.36#ibcon#about to write, iclass 23, count 0 2006.281.07:40:13.36#ibcon#wrote, iclass 23, count 0 2006.281.07:40:13.36#ibcon#about to read 3, iclass 23, count 0 2006.281.07:40:13.37#ibcon#read 3, iclass 23, count 0 2006.281.07:40:13.37#ibcon#about to read 4, iclass 23, count 0 2006.281.07:40:13.37#ibcon#read 4, iclass 23, count 0 2006.281.07:40:13.37#ibcon#about to read 5, iclass 23, count 0 2006.281.07:40:13.37#ibcon#read 5, iclass 23, count 0 2006.281.07:40:13.37#ibcon#about to read 6, iclass 23, count 0 2006.281.07:40:13.38#ibcon#read 6, iclass 23, count 0 2006.281.07:40:13.38#ibcon#end of sib2, iclass 23, count 0 2006.281.07:40:13.38#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:40:13.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:40:13.38#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:40:13.38#ibcon#*before write, iclass 23, count 0 2006.281.07:40:13.38#ibcon#enter sib2, iclass 23, count 0 2006.281.07:40:13.38#ibcon#flushed, iclass 23, count 0 2006.281.07:40:13.38#ibcon#about to write, iclass 23, count 0 2006.281.07:40:13.38#ibcon#wrote, iclass 23, count 0 2006.281.07:40:13.38#ibcon#about to read 3, iclass 23, count 0 2006.281.07:40:13.42#ibcon#read 3, iclass 23, count 0 2006.281.07:40:13.42#ibcon#about to read 4, iclass 23, count 0 2006.281.07:40:13.42#ibcon#read 4, iclass 23, count 0 2006.281.07:40:13.42#ibcon#about to read 5, iclass 23, count 0 2006.281.07:40:13.42#ibcon#read 5, iclass 23, count 0 2006.281.07:40:13.42#ibcon#about to read 6, iclass 23, count 0 2006.281.07:40:13.42#ibcon#read 6, iclass 23, count 0 2006.281.07:40:13.42#ibcon#end of sib2, iclass 23, count 0 2006.281.07:40:13.42#ibcon#*after write, iclass 23, count 0 2006.281.07:40:13.42#ibcon#*before return 0, iclass 23, count 0 2006.281.07:40:13.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:13.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:40:13.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:40:13.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:40:13.42$vc4f8/vb=5,4 2006.281.07:40:13.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:40:13.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:40:13.42#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:13.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:13.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:13.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:13.48#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:40:13.48#ibcon#first serial, iclass 25, count 2 2006.281.07:40:13.48#ibcon#enter sib2, iclass 25, count 2 2006.281.07:40:13.48#ibcon#flushed, iclass 25, count 2 2006.281.07:40:13.48#ibcon#about to write, iclass 25, count 2 2006.281.07:40:13.48#ibcon#wrote, iclass 25, count 2 2006.281.07:40:13.48#ibcon#about to read 3, iclass 25, count 2 2006.281.07:40:13.50#ibcon#read 3, iclass 25, count 2 2006.281.07:40:13.50#ibcon#about to read 4, iclass 25, count 2 2006.281.07:40:13.50#ibcon#read 4, iclass 25, count 2 2006.281.07:40:13.50#ibcon#about to read 5, iclass 25, count 2 2006.281.07:40:13.50#ibcon#read 5, iclass 25, count 2 2006.281.07:40:13.50#ibcon#about to read 6, iclass 25, count 2 2006.281.07:40:13.50#ibcon#read 6, iclass 25, count 2 2006.281.07:40:13.50#ibcon#end of sib2, iclass 25, count 2 2006.281.07:40:13.50#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:40:13.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:40:13.50#ibcon#[27=AT05-04\r\n] 2006.281.07:40:13.50#ibcon#*before write, iclass 25, count 2 2006.281.07:40:13.50#ibcon#enter sib2, iclass 25, count 2 2006.281.07:40:13.50#ibcon#flushed, iclass 25, count 2 2006.281.07:40:13.50#ibcon#about to write, iclass 25, count 2 2006.281.07:40:13.50#ibcon#wrote, iclass 25, count 2 2006.281.07:40:13.50#ibcon#about to read 3, iclass 25, count 2 2006.281.07:40:13.53#ibcon#read 3, iclass 25, count 2 2006.281.07:40:13.53#ibcon#about to read 4, iclass 25, count 2 2006.281.07:40:13.53#ibcon#read 4, iclass 25, count 2 2006.281.07:40:13.53#ibcon#about to read 5, iclass 25, count 2 2006.281.07:40:13.53#ibcon#read 5, iclass 25, count 2 2006.281.07:40:13.53#ibcon#about to read 6, iclass 25, count 2 2006.281.07:40:13.53#ibcon#read 6, iclass 25, count 2 2006.281.07:40:13.53#ibcon#end of sib2, iclass 25, count 2 2006.281.07:40:13.53#ibcon#*after write, iclass 25, count 2 2006.281.07:40:13.53#ibcon#*before return 0, iclass 25, count 2 2006.281.07:40:13.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:13.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:40:13.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:40:13.53#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:13.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:13.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:13.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:13.65#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:40:13.65#ibcon#first serial, iclass 25, count 0 2006.281.07:40:13.65#ibcon#enter sib2, iclass 25, count 0 2006.281.07:40:13.65#ibcon#flushed, iclass 25, count 0 2006.281.07:40:13.65#ibcon#about to write, iclass 25, count 0 2006.281.07:40:13.65#ibcon#wrote, iclass 25, count 0 2006.281.07:40:13.65#ibcon#about to read 3, iclass 25, count 0 2006.281.07:40:13.67#ibcon#read 3, iclass 25, count 0 2006.281.07:40:13.67#ibcon#about to read 4, iclass 25, count 0 2006.281.07:40:13.67#ibcon#read 4, iclass 25, count 0 2006.281.07:40:13.67#ibcon#about to read 5, iclass 25, count 0 2006.281.07:40:13.67#ibcon#read 5, iclass 25, count 0 2006.281.07:40:13.67#ibcon#about to read 6, iclass 25, count 0 2006.281.07:40:13.67#ibcon#read 6, iclass 25, count 0 2006.281.07:40:13.67#ibcon#end of sib2, iclass 25, count 0 2006.281.07:40:13.67#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:40:13.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:40:13.67#ibcon#[27=USB\r\n] 2006.281.07:40:13.67#ibcon#*before write, iclass 25, count 0 2006.281.07:40:13.67#ibcon#enter sib2, iclass 25, count 0 2006.281.07:40:13.67#ibcon#flushed, iclass 25, count 0 2006.281.07:40:13.67#ibcon#about to write, iclass 25, count 0 2006.281.07:40:13.67#ibcon#wrote, iclass 25, count 0 2006.281.07:40:13.67#ibcon#about to read 3, iclass 25, count 0 2006.281.07:40:13.70#ibcon#read 3, iclass 25, count 0 2006.281.07:40:13.70#ibcon#about to read 4, iclass 25, count 0 2006.281.07:40:13.70#ibcon#read 4, iclass 25, count 0 2006.281.07:40:13.70#ibcon#about to read 5, iclass 25, count 0 2006.281.07:40:13.70#ibcon#read 5, iclass 25, count 0 2006.281.07:40:13.70#ibcon#about to read 6, iclass 25, count 0 2006.281.07:40:13.70#ibcon#read 6, iclass 25, count 0 2006.281.07:40:13.70#ibcon#end of sib2, iclass 25, count 0 2006.281.07:40:13.70#ibcon#*after write, iclass 25, count 0 2006.281.07:40:13.70#ibcon#*before return 0, iclass 25, count 0 2006.281.07:40:13.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:13.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:40:13.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:40:13.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:40:13.70$vc4f8/vblo=6,752.99 2006.281.07:40:13.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:40:13.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:40:13.70#ibcon#ireg 17 cls_cnt 0 2006.281.07:40:13.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:13.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:13.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:13.70#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:40:13.70#ibcon#first serial, iclass 27, count 0 2006.281.07:40:13.70#ibcon#enter sib2, iclass 27, count 0 2006.281.07:40:13.70#ibcon#flushed, iclass 27, count 0 2006.281.07:40:13.70#ibcon#about to write, iclass 27, count 0 2006.281.07:40:13.70#ibcon#wrote, iclass 27, count 0 2006.281.07:40:13.70#ibcon#about to read 3, iclass 27, count 0 2006.281.07:40:13.72#ibcon#read 3, iclass 27, count 0 2006.281.07:40:13.72#ibcon#about to read 4, iclass 27, count 0 2006.281.07:40:13.72#ibcon#read 4, iclass 27, count 0 2006.281.07:40:13.72#ibcon#about to read 5, iclass 27, count 0 2006.281.07:40:13.72#ibcon#read 5, iclass 27, count 0 2006.281.07:40:13.72#ibcon#about to read 6, iclass 27, count 0 2006.281.07:40:13.72#ibcon#read 6, iclass 27, count 0 2006.281.07:40:13.72#ibcon#end of sib2, iclass 27, count 0 2006.281.07:40:13.72#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:40:13.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:40:13.72#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:40:13.72#ibcon#*before write, iclass 27, count 0 2006.281.07:40:13.72#ibcon#enter sib2, iclass 27, count 0 2006.281.07:40:13.72#ibcon#flushed, iclass 27, count 0 2006.281.07:40:13.72#ibcon#about to write, iclass 27, count 0 2006.281.07:40:13.72#ibcon#wrote, iclass 27, count 0 2006.281.07:40:13.72#ibcon#about to read 3, iclass 27, count 0 2006.281.07:40:13.77#ibcon#read 3, iclass 27, count 0 2006.281.07:40:13.77#ibcon#about to read 4, iclass 27, count 0 2006.281.07:40:13.77#ibcon#read 4, iclass 27, count 0 2006.281.07:40:13.77#ibcon#about to read 5, iclass 27, count 0 2006.281.07:40:13.77#ibcon#read 5, iclass 27, count 0 2006.281.07:40:13.77#ibcon#about to read 6, iclass 27, count 0 2006.281.07:40:13.77#ibcon#read 6, iclass 27, count 0 2006.281.07:40:13.77#ibcon#end of sib2, iclass 27, count 0 2006.281.07:40:13.77#ibcon#*after write, iclass 27, count 0 2006.281.07:40:13.77#ibcon#*before return 0, iclass 27, count 0 2006.281.07:40:13.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:13.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:40:13.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:40:13.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:40:13.77$vc4f8/vb=6,4 2006.281.07:40:13.77#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:40:13.77#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:40:13.77#ibcon#ireg 11 cls_cnt 2 2006.281.07:40:13.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:13.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:13.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:13.81#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:40:13.81#ibcon#first serial, iclass 29, count 2 2006.281.07:40:13.81#ibcon#enter sib2, iclass 29, count 2 2006.281.07:40:13.81#ibcon#flushed, iclass 29, count 2 2006.281.07:40:13.81#ibcon#about to write, iclass 29, count 2 2006.281.07:40:13.81#ibcon#wrote, iclass 29, count 2 2006.281.07:40:13.81#ibcon#about to read 3, iclass 29, count 2 2006.281.07:40:13.84#ibcon#read 3, iclass 29, count 2 2006.281.07:40:13.84#ibcon#about to read 4, iclass 29, count 2 2006.281.07:40:13.84#ibcon#read 4, iclass 29, count 2 2006.281.07:40:13.84#ibcon#about to read 5, iclass 29, count 2 2006.281.07:40:13.84#ibcon#read 5, iclass 29, count 2 2006.281.07:40:13.84#ibcon#about to read 6, iclass 29, count 2 2006.281.07:40:13.84#ibcon#read 6, iclass 29, count 2 2006.281.07:40:13.84#ibcon#end of sib2, iclass 29, count 2 2006.281.07:40:13.84#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:40:13.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:40:13.84#ibcon#[27=AT06-04\r\n] 2006.281.07:40:13.84#ibcon#*before write, iclass 29, count 2 2006.281.07:40:13.84#ibcon#enter sib2, iclass 29, count 2 2006.281.07:40:13.84#ibcon#flushed, iclass 29, count 2 2006.281.07:40:13.84#ibcon#about to write, iclass 29, count 2 2006.281.07:40:13.84#ibcon#wrote, iclass 29, count 2 2006.281.07:40:13.84#ibcon#about to read 3, iclass 29, count 2 2006.281.07:40:13.87#ibcon#read 3, iclass 29, count 2 2006.281.07:40:13.87#ibcon#about to read 4, iclass 29, count 2 2006.281.07:40:13.87#ibcon#read 4, iclass 29, count 2 2006.281.07:40:13.87#ibcon#about to read 5, iclass 29, count 2 2006.281.07:40:13.87#ibcon#read 5, iclass 29, count 2 2006.281.07:40:13.87#ibcon#about to read 6, iclass 29, count 2 2006.281.07:40:13.87#ibcon#read 6, iclass 29, count 2 2006.281.07:40:13.87#ibcon#end of sib2, iclass 29, count 2 2006.281.07:40:13.87#ibcon#*after write, iclass 29, count 2 2006.281.07:40:13.87#ibcon#*before return 0, iclass 29, count 2 2006.281.07:40:13.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:13.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:40:13.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:40:13.87#ibcon#ireg 7 cls_cnt 0 2006.281.07:40:13.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:13.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:13.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:13.99#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:40:13.99#ibcon#first serial, iclass 29, count 0 2006.281.07:40:13.99#ibcon#enter sib2, iclass 29, count 0 2006.281.07:40:13.99#ibcon#flushed, iclass 29, count 0 2006.281.07:40:13.99#ibcon#about to write, iclass 29, count 0 2006.281.07:40:13.99#ibcon#wrote, iclass 29, count 0 2006.281.07:40:13.99#ibcon#about to read 3, iclass 29, count 0 2006.281.07:40:14.01#ibcon#read 3, iclass 29, count 0 2006.281.07:40:14.01#ibcon#about to read 4, iclass 29, count 0 2006.281.07:40:14.01#ibcon#read 4, iclass 29, count 0 2006.281.07:40:14.01#ibcon#about to read 5, iclass 29, count 0 2006.281.07:40:14.01#ibcon#read 5, iclass 29, count 0 2006.281.07:40:14.01#ibcon#about to read 6, iclass 29, count 0 2006.281.07:40:14.01#ibcon#read 6, iclass 29, count 0 2006.281.07:40:14.01#ibcon#end of sib2, iclass 29, count 0 2006.281.07:40:14.01#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:40:14.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:40:14.01#ibcon#[27=USB\r\n] 2006.281.07:40:14.01#ibcon#*before write, iclass 29, count 0 2006.281.07:40:14.01#ibcon#enter sib2, iclass 29, count 0 2006.281.07:40:14.01#ibcon#flushed, iclass 29, count 0 2006.281.07:40:14.01#ibcon#about to write, iclass 29, count 0 2006.281.07:40:14.01#ibcon#wrote, iclass 29, count 0 2006.281.07:40:14.01#ibcon#about to read 3, iclass 29, count 0 2006.281.07:40:14.04#ibcon#read 3, iclass 29, count 0 2006.281.07:40:14.04#ibcon#about to read 4, iclass 29, count 0 2006.281.07:40:14.04#ibcon#read 4, iclass 29, count 0 2006.281.07:40:14.04#ibcon#about to read 5, iclass 29, count 0 2006.281.07:40:14.04#ibcon#read 5, iclass 29, count 0 2006.281.07:40:14.04#ibcon#about to read 6, iclass 29, count 0 2006.281.07:40:14.04#ibcon#read 6, iclass 29, count 0 2006.281.07:40:14.04#ibcon#end of sib2, iclass 29, count 0 2006.281.07:40:14.04#ibcon#*after write, iclass 29, count 0 2006.281.07:40:14.04#ibcon#*before return 0, iclass 29, count 0 2006.281.07:40:14.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:14.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:40:14.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:40:14.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:40:14.04$vc4f8/vabw=wide 2006.281.07:40:14.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:40:14.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:40:14.04#ibcon#ireg 8 cls_cnt 0 2006.281.07:40:14.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:14.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:14.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:14.04#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:40:14.04#ibcon#first serial, iclass 31, count 0 2006.281.07:40:14.04#ibcon#enter sib2, iclass 31, count 0 2006.281.07:40:14.04#ibcon#flushed, iclass 31, count 0 2006.281.07:40:14.04#ibcon#about to write, iclass 31, count 0 2006.281.07:40:14.04#ibcon#wrote, iclass 31, count 0 2006.281.07:40:14.04#ibcon#about to read 3, iclass 31, count 0 2006.281.07:40:14.06#ibcon#read 3, iclass 31, count 0 2006.281.07:40:14.06#ibcon#about to read 4, iclass 31, count 0 2006.281.07:40:14.06#ibcon#read 4, iclass 31, count 0 2006.281.07:40:14.06#ibcon#about to read 5, iclass 31, count 0 2006.281.07:40:14.06#ibcon#read 5, iclass 31, count 0 2006.281.07:40:14.06#ibcon#about to read 6, iclass 31, count 0 2006.281.07:40:14.06#ibcon#read 6, iclass 31, count 0 2006.281.07:40:14.06#ibcon#end of sib2, iclass 31, count 0 2006.281.07:40:14.06#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:40:14.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:40:14.09#ibcon#[25=BW32\r\n] 2006.281.07:40:14.09#ibcon#*before write, iclass 31, count 0 2006.281.07:40:14.09#ibcon#enter sib2, iclass 31, count 0 2006.281.07:40:14.09#ibcon#flushed, iclass 31, count 0 2006.281.07:40:14.09#ibcon#about to write, iclass 31, count 0 2006.281.07:40:14.09#ibcon#wrote, iclass 31, count 0 2006.281.07:40:14.09#ibcon#about to read 3, iclass 31, count 0 2006.281.07:40:14.11#ibcon#read 3, iclass 31, count 0 2006.281.07:40:14.11#ibcon#about to read 4, iclass 31, count 0 2006.281.07:40:14.11#ibcon#read 4, iclass 31, count 0 2006.281.07:40:14.11#ibcon#about to read 5, iclass 31, count 0 2006.281.07:40:14.11#ibcon#read 5, iclass 31, count 0 2006.281.07:40:14.11#ibcon#about to read 6, iclass 31, count 0 2006.281.07:40:14.11#ibcon#read 6, iclass 31, count 0 2006.281.07:40:14.11#ibcon#end of sib2, iclass 31, count 0 2006.281.07:40:14.11#ibcon#*after write, iclass 31, count 0 2006.281.07:40:14.11#ibcon#*before return 0, iclass 31, count 0 2006.281.07:40:14.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:14.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:40:14.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:40:14.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:40:14.11$vc4f8/vbbw=wide 2006.281.07:40:14.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.07:40:14.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.07:40:14.11#ibcon#ireg 8 cls_cnt 0 2006.281.07:40:14.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:40:14.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:40:14.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:40:14.17#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:40:14.17#ibcon#first serial, iclass 33, count 0 2006.281.07:40:14.17#ibcon#enter sib2, iclass 33, count 0 2006.281.07:40:14.17#ibcon#flushed, iclass 33, count 0 2006.281.07:40:14.17#ibcon#about to write, iclass 33, count 0 2006.281.07:40:14.17#ibcon#wrote, iclass 33, count 0 2006.281.07:40:14.17#ibcon#about to read 3, iclass 33, count 0 2006.281.07:40:14.18#ibcon#read 3, iclass 33, count 0 2006.281.07:40:14.18#ibcon#about to read 4, iclass 33, count 0 2006.281.07:40:14.18#ibcon#read 4, iclass 33, count 0 2006.281.07:40:14.18#ibcon#about to read 5, iclass 33, count 0 2006.281.07:40:14.18#ibcon#read 5, iclass 33, count 0 2006.281.07:40:14.18#ibcon#about to read 6, iclass 33, count 0 2006.281.07:40:14.18#ibcon#read 6, iclass 33, count 0 2006.281.07:40:14.18#ibcon#end of sib2, iclass 33, count 0 2006.281.07:40:14.18#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:40:14.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:40:14.18#ibcon#[27=BW32\r\n] 2006.281.07:40:14.18#ibcon#*before write, iclass 33, count 0 2006.281.07:40:14.18#ibcon#enter sib2, iclass 33, count 0 2006.281.07:40:14.18#ibcon#flushed, iclass 33, count 0 2006.281.07:40:14.18#ibcon#about to write, iclass 33, count 0 2006.281.07:40:14.18#ibcon#wrote, iclass 33, count 0 2006.281.07:40:14.18#ibcon#about to read 3, iclass 33, count 0 2006.281.07:40:14.21#ibcon#read 3, iclass 33, count 0 2006.281.07:40:14.21#ibcon#about to read 4, iclass 33, count 0 2006.281.07:40:14.21#ibcon#read 4, iclass 33, count 0 2006.281.07:40:14.21#ibcon#about to read 5, iclass 33, count 0 2006.281.07:40:14.21#ibcon#read 5, iclass 33, count 0 2006.281.07:40:14.21#ibcon#about to read 6, iclass 33, count 0 2006.281.07:40:14.21#ibcon#read 6, iclass 33, count 0 2006.281.07:40:14.21#ibcon#end of sib2, iclass 33, count 0 2006.281.07:40:14.21#ibcon#*after write, iclass 33, count 0 2006.281.07:40:14.21#ibcon#*before return 0, iclass 33, count 0 2006.281.07:40:14.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:40:14.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:40:14.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:40:14.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:40:14.21$4f8m12a/ifd4f 2006.281.07:40:14.21$ifd4f/lo= 2006.281.07:40:14.21$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:40:14.22$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:40:14.22$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:40:14.22$ifd4f/patch= 2006.281.07:40:14.22$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:40:14.22$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:40:14.22$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:40:14.22$4f8m12a/"form=m,16.000,1:2 2006.281.07:40:14.22$4f8m12a/"tpicd 2006.281.07:40:14.22$4f8m12a/echo=off 2006.281.07:40:14.22$4f8m12a/xlog=off 2006.281.07:40:14.22:!2006.281.07:40:40 2006.281.07:40:23.14#trakl#Source acquired 2006.281.07:40:25.14#flagr#flagr/antenna,acquired 2006.281.07:40:37.14#trakl#Off source 2006.281.07:40:37.14?ERROR st -7 Antenna off-source! 2006.281.07:40:37.14#trakl#az 313.838 el 47.283 azerr*cos(el) 0.0018 elerr 0.0170 2006.281.07:40:37.14#flagr#flagr/antenna,off-source 2006.281.07:40:40.01:preob 2006.281.07:40:41.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:40:41.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:40:41.14/onsource/SLEWING 2006.281.07:40:41.14:!2006.281.07:40:50 2006.281.07:40:45.13#trakl#Source re-acquired 2006.281.07:40:45.13#flagr#flagr/antenna,re-acquired 2006.281.07:40:50.00:data_valid=on 2006.281.07:40:50.00:midob 2006.281.07:40:50.13/onsource/TRACKING 2006.281.07:40:50.14/wx/21.15,1001.1,50 2006.281.07:40:50.34/cable/+6.4864E-03 2006.281.07:40:51.43/va/01,07,usb,yes,32,34 2006.281.07:40:51.43/va/02,06,usb,yes,30,31 2006.281.07:40:51.43/va/03,06,usb,yes,28,28 2006.281.07:40:51.43/va/04,06,usb,yes,31,33 2006.281.07:40:51.43/va/05,07,usb,yes,29,30 2006.281.07:40:51.43/va/06,06,usb,yes,28,27 2006.281.07:40:51.43/va/07,06,usb,yes,28,28 2006.281.07:40:51.43/va/08,06,usb,yes,30,30 2006.281.07:40:51.66/valo/01,532.99,yes,locked 2006.281.07:40:51.66/valo/02,572.99,yes,locked 2006.281.07:40:51.66/valo/03,672.99,yes,locked 2006.281.07:40:51.66/valo/04,832.99,yes,locked 2006.281.07:40:51.66/valo/05,652.99,yes,locked 2006.281.07:40:51.66/valo/06,772.99,yes,locked 2006.281.07:40:51.66/valo/07,832.99,yes,locked 2006.281.07:40:51.66/valo/08,852.99,yes,locked 2006.281.07:40:52.75/vb/01,04,usb,yes,30,29 2006.281.07:40:52.75/vb/02,05,usb,yes,28,29 2006.281.07:40:52.75/vb/03,04,usb,yes,28,32 2006.281.07:40:52.75/vb/04,04,usb,yes,29,29 2006.281.07:40:52.75/vb/05,04,usb,yes,27,31 2006.281.07:40:52.75/vb/06,04,usb,yes,28,31 2006.281.07:40:52.75/vb/07,04,usb,yes,30,30 2006.281.07:40:52.75/vb/08,04,usb,yes,28,31 2006.281.07:40:52.98/vblo/01,632.99,yes,locked 2006.281.07:40:52.98/vblo/02,640.99,yes,locked 2006.281.07:40:52.98/vblo/03,656.99,yes,locked 2006.281.07:40:52.98/vblo/04,712.99,yes,locked 2006.281.07:40:52.98/vblo/05,744.99,yes,locked 2006.281.07:40:52.98/vblo/06,752.99,yes,locked 2006.281.07:40:52.98/vblo/07,734.99,yes,locked 2006.281.07:40:52.98/vblo/08,744.99,yes,locked 2006.281.07:40:53.13/vabw/8 2006.281.07:40:53.28/vbbw/8 2006.281.07:40:53.37/xfe/off,on,12.2 2006.281.07:40:53.75/ifatt/23,28,28,28 2006.281.07:40:54.07/fmout-gps/S +3.08E-07 2006.281.07:40:54.09:!2006.281.07:41:50 2006.281.07:41:18.13#trakl#Off source 2006.281.07:41:18.13?ERROR st -7 Antenna off-source! 2006.281.07:41:18.13#trakl#az 313.836 el 47.183 azerr*cos(el) -0.0017 elerr -0.0201 2006.281.07:41:19.13#flagr#flagr/antenna,off-source 2006.281.07:41:24.13#trakl#Source re-acquired 2006.281.07:41:25.13#flagr#flagr/antenna,re-acquired 2006.281.07:41:45.13#trakl#Off source 2006.281.07:41:45.13?ERROR st -7 Antenna off-source! 2006.281.07:41:45.13#trakl#az 313.834 el 47.117 azerr*cos(el) 0.0000 elerr -0.0234 2006.281.07:41:46.13#flagr#flagr/antenna,off-source 2006.281.07:41:50.01:data_valid=off 2006.281.07:41:50.01:postob 2006.281.07:41:50.15/cable/+6.4854E-03 2006.281.07:41:50.15/wx/21.09,1001.2,50 2006.281.07:41:51.07/fmout-gps/S +3.11E-07 2006.281.07:41:51.07:scan_name=281-0742,k06281,60 2006.281.07:41:51.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.281.07:41:51.13#flagr#flagr/antenna,new-source 2006.281.07:41:52.13:checkk5 2006.281.07:41:52.55/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:41:52.98/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:41:53.37/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:41:53.82/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:41:54.45/chk_obsdata//k5ts1/T2810740??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:41:54.88/chk_obsdata//k5ts2/T2810740??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:41:55.28/chk_obsdata//k5ts3/T2810740??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:41:55.66/chk_obsdata//k5ts4/T2810740??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:41:57.05/k5log//k5ts1_log_newline 2006.281.07:41:57.81/k5log//k5ts2_log_newline 2006.281.07:41:58.64/k5log//k5ts3_log_newline 2006.281.07:41:59.52/k5log//k5ts4_log_newline 2006.281.07:41:59.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:41:59.54:4f8m12a=1 2006.281.07:41:59.54$4f8m12a/echo=on 2006.281.07:41:59.54$4f8m12a/pcalon 2006.281.07:41:59.54$pcalon/"no phase cal control is implemented here 2006.281.07:41:59.54$4f8m12a/"tpicd=stop 2006.281.07:41:59.54$4f8m12a/vc4f8 2006.281.07:41:59.54$vc4f8/valo=1,532.99 2006.281.07:41:59.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.07:41:59.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.07:41:59.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:41:59.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:41:59.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:41:59.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:41:59.55#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:41:59.55#ibcon#first serial, iclass 7, count 0 2006.281.07:41:59.55#ibcon#enter sib2, iclass 7, count 0 2006.281.07:41:59.55#ibcon#flushed, iclass 7, count 0 2006.281.07:41:59.55#ibcon#about to write, iclass 7, count 0 2006.281.07:41:59.55#ibcon#wrote, iclass 7, count 0 2006.281.07:41:59.55#ibcon#about to read 3, iclass 7, count 0 2006.281.07:41:59.56#ibcon#read 3, iclass 7, count 0 2006.281.07:41:59.56#ibcon#about to read 4, iclass 7, count 0 2006.281.07:41:59.56#ibcon#read 4, iclass 7, count 0 2006.281.07:41:59.56#ibcon#about to read 5, iclass 7, count 0 2006.281.07:41:59.56#ibcon#read 5, iclass 7, count 0 2006.281.07:41:59.56#ibcon#about to read 6, iclass 7, count 0 2006.281.07:41:59.56#ibcon#read 6, iclass 7, count 0 2006.281.07:41:59.56#ibcon#end of sib2, iclass 7, count 0 2006.281.07:41:59.56#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:41:59.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:41:59.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:41:59.56#ibcon#*before write, iclass 7, count 0 2006.281.07:41:59.56#ibcon#enter sib2, iclass 7, count 0 2006.281.07:41:59.56#ibcon#flushed, iclass 7, count 0 2006.281.07:41:59.56#ibcon#about to write, iclass 7, count 0 2006.281.07:41:59.56#ibcon#wrote, iclass 7, count 0 2006.281.07:41:59.56#ibcon#about to read 3, iclass 7, count 0 2006.281.07:41:59.61#ibcon#read 3, iclass 7, count 0 2006.281.07:41:59.61#ibcon#about to read 4, iclass 7, count 0 2006.281.07:41:59.61#ibcon#read 4, iclass 7, count 0 2006.281.07:41:59.61#ibcon#about to read 5, iclass 7, count 0 2006.281.07:41:59.61#ibcon#read 5, iclass 7, count 0 2006.281.07:41:59.61#ibcon#about to read 6, iclass 7, count 0 2006.281.07:41:59.61#ibcon#read 6, iclass 7, count 0 2006.281.07:41:59.61#ibcon#end of sib2, iclass 7, count 0 2006.281.07:41:59.61#ibcon#*after write, iclass 7, count 0 2006.281.07:41:59.61#ibcon#*before return 0, iclass 7, count 0 2006.281.07:41:59.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:41:59.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:41:59.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:41:59.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:41:59.62$vc4f8/va=1,7 2006.281.07:41:59.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.07:41:59.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.07:41:59.62#ibcon#ireg 11 cls_cnt 2 2006.281.07:41:59.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:41:59.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:41:59.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:41:59.62#ibcon#enter wrdev, iclass 11, count 2 2006.281.07:41:59.62#ibcon#first serial, iclass 11, count 2 2006.281.07:41:59.62#ibcon#enter sib2, iclass 11, count 2 2006.281.07:41:59.62#ibcon#flushed, iclass 11, count 2 2006.281.07:41:59.62#ibcon#about to write, iclass 11, count 2 2006.281.07:41:59.62#ibcon#wrote, iclass 11, count 2 2006.281.07:41:59.62#ibcon#about to read 3, iclass 11, count 2 2006.281.07:41:59.63#ibcon#read 3, iclass 11, count 2 2006.281.07:41:59.64#ibcon#about to read 4, iclass 11, count 2 2006.281.07:41:59.64#ibcon#read 4, iclass 11, count 2 2006.281.07:41:59.64#ibcon#about to read 5, iclass 11, count 2 2006.281.07:41:59.64#ibcon#read 5, iclass 11, count 2 2006.281.07:41:59.64#ibcon#about to read 6, iclass 11, count 2 2006.281.07:41:59.64#ibcon#read 6, iclass 11, count 2 2006.281.07:41:59.64#ibcon#end of sib2, iclass 11, count 2 2006.281.07:41:59.64#ibcon#*mode == 0, iclass 11, count 2 2006.281.07:41:59.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.07:41:59.64#ibcon#[25=AT01-07\r\n] 2006.281.07:41:59.64#ibcon#*before write, iclass 11, count 2 2006.281.07:41:59.64#ibcon#enter sib2, iclass 11, count 2 2006.281.07:41:59.64#ibcon#flushed, iclass 11, count 2 2006.281.07:41:59.64#ibcon#about to write, iclass 11, count 2 2006.281.07:41:59.64#ibcon#wrote, iclass 11, count 2 2006.281.07:41:59.64#ibcon#about to read 3, iclass 11, count 2 2006.281.07:41:59.66#ibcon#read 3, iclass 11, count 2 2006.281.07:41:59.66#ibcon#about to read 4, iclass 11, count 2 2006.281.07:41:59.66#ibcon#read 4, iclass 11, count 2 2006.281.07:41:59.66#ibcon#about to read 5, iclass 11, count 2 2006.281.07:41:59.66#ibcon#read 5, iclass 11, count 2 2006.281.07:41:59.66#ibcon#about to read 6, iclass 11, count 2 2006.281.07:41:59.66#ibcon#read 6, iclass 11, count 2 2006.281.07:41:59.66#ibcon#end of sib2, iclass 11, count 2 2006.281.07:41:59.66#ibcon#*after write, iclass 11, count 2 2006.281.07:41:59.66#ibcon#*before return 0, iclass 11, count 2 2006.281.07:41:59.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:41:59.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:41:59.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.07:41:59.66#ibcon#ireg 7 cls_cnt 0 2006.281.07:41:59.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:41:59.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:41:59.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:41:59.78#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:41:59.78#ibcon#first serial, iclass 11, count 0 2006.281.07:41:59.78#ibcon#enter sib2, iclass 11, count 0 2006.281.07:41:59.78#ibcon#flushed, iclass 11, count 0 2006.281.07:41:59.78#ibcon#about to write, iclass 11, count 0 2006.281.07:41:59.78#ibcon#wrote, iclass 11, count 0 2006.281.07:41:59.78#ibcon#about to read 3, iclass 11, count 0 2006.281.07:41:59.81#ibcon#read 3, iclass 11, count 0 2006.281.07:41:59.81#ibcon#about to read 4, iclass 11, count 0 2006.281.07:41:59.81#ibcon#read 4, iclass 11, count 0 2006.281.07:41:59.81#ibcon#about to read 5, iclass 11, count 0 2006.281.07:41:59.81#ibcon#read 5, iclass 11, count 0 2006.281.07:41:59.81#ibcon#about to read 6, iclass 11, count 0 2006.281.07:41:59.81#ibcon#read 6, iclass 11, count 0 2006.281.07:41:59.81#ibcon#end of sib2, iclass 11, count 0 2006.281.07:41:59.81#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:41:59.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:41:59.81#ibcon#[25=USB\r\n] 2006.281.07:41:59.81#ibcon#*before write, iclass 11, count 0 2006.281.07:41:59.81#ibcon#enter sib2, iclass 11, count 0 2006.281.07:41:59.81#ibcon#flushed, iclass 11, count 0 2006.281.07:41:59.81#ibcon#about to write, iclass 11, count 0 2006.281.07:41:59.81#ibcon#wrote, iclass 11, count 0 2006.281.07:41:59.81#ibcon#about to read 3, iclass 11, count 0 2006.281.07:41:59.83#ibcon#read 3, iclass 11, count 0 2006.281.07:41:59.83#ibcon#about to read 4, iclass 11, count 0 2006.281.07:41:59.83#ibcon#read 4, iclass 11, count 0 2006.281.07:41:59.83#ibcon#about to read 5, iclass 11, count 0 2006.281.07:41:59.83#ibcon#read 5, iclass 11, count 0 2006.281.07:41:59.83#ibcon#about to read 6, iclass 11, count 0 2006.281.07:41:59.83#ibcon#read 6, iclass 11, count 0 2006.281.07:41:59.83#ibcon#end of sib2, iclass 11, count 0 2006.281.07:41:59.83#ibcon#*after write, iclass 11, count 0 2006.281.07:41:59.83#ibcon#*before return 0, iclass 11, count 0 2006.281.07:41:59.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:41:59.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:41:59.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:41:59.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:41:59.83$vc4f8/valo=2,572.99 2006.281.07:41:59.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.07:41:59.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.07:41:59.83#ibcon#ireg 17 cls_cnt 0 2006.281.07:41:59.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:41:59.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:41:59.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:41:59.83#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:41:59.83#ibcon#first serial, iclass 13, count 0 2006.281.07:41:59.83#ibcon#enter sib2, iclass 13, count 0 2006.281.07:41:59.83#ibcon#flushed, iclass 13, count 0 2006.281.07:41:59.83#ibcon#about to write, iclass 13, count 0 2006.281.07:41:59.83#ibcon#wrote, iclass 13, count 0 2006.281.07:41:59.83#ibcon#about to read 3, iclass 13, count 0 2006.281.07:41:59.86#ibcon#read 3, iclass 13, count 0 2006.281.07:41:59.86#ibcon#about to read 4, iclass 13, count 0 2006.281.07:41:59.86#ibcon#read 4, iclass 13, count 0 2006.281.07:41:59.86#ibcon#about to read 5, iclass 13, count 0 2006.281.07:41:59.86#ibcon#read 5, iclass 13, count 0 2006.281.07:41:59.86#ibcon#about to read 6, iclass 13, count 0 2006.281.07:41:59.86#ibcon#read 6, iclass 13, count 0 2006.281.07:41:59.86#ibcon#end of sib2, iclass 13, count 0 2006.281.07:41:59.86#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:41:59.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:41:59.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:41:59.86#ibcon#*before write, iclass 13, count 0 2006.281.07:41:59.86#ibcon#enter sib2, iclass 13, count 0 2006.281.07:41:59.86#ibcon#flushed, iclass 13, count 0 2006.281.07:41:59.86#ibcon#about to write, iclass 13, count 0 2006.281.07:41:59.86#ibcon#wrote, iclass 13, count 0 2006.281.07:41:59.86#ibcon#about to read 3, iclass 13, count 0 2006.281.07:41:59.89#ibcon#read 3, iclass 13, count 0 2006.281.07:41:59.89#ibcon#about to read 4, iclass 13, count 0 2006.281.07:41:59.89#ibcon#read 4, iclass 13, count 0 2006.281.07:41:59.89#ibcon#about to read 5, iclass 13, count 0 2006.281.07:41:59.89#ibcon#read 5, iclass 13, count 0 2006.281.07:41:59.89#ibcon#about to read 6, iclass 13, count 0 2006.281.07:41:59.89#ibcon#read 6, iclass 13, count 0 2006.281.07:41:59.89#ibcon#end of sib2, iclass 13, count 0 2006.281.07:41:59.89#ibcon#*after write, iclass 13, count 0 2006.281.07:41:59.89#ibcon#*before return 0, iclass 13, count 0 2006.281.07:41:59.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:41:59.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:41:59.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:41:59.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:41:59.89$vc4f8/va=2,6 2006.281.07:41:59.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.07:41:59.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.07:41:59.89#ibcon#ireg 11 cls_cnt 2 2006.281.07:41:59.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:41:59.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:41:59.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:41:59.96#ibcon#enter wrdev, iclass 15, count 2 2006.281.07:41:59.96#ibcon#first serial, iclass 15, count 2 2006.281.07:41:59.96#ibcon#enter sib2, iclass 15, count 2 2006.281.07:41:59.96#ibcon#flushed, iclass 15, count 2 2006.281.07:41:59.96#ibcon#about to write, iclass 15, count 2 2006.281.07:41:59.96#ibcon#wrote, iclass 15, count 2 2006.281.07:41:59.96#ibcon#about to read 3, iclass 15, count 2 2006.281.07:41:59.98#ibcon#read 3, iclass 15, count 2 2006.281.07:41:59.98#ibcon#about to read 4, iclass 15, count 2 2006.281.07:41:59.98#ibcon#read 4, iclass 15, count 2 2006.281.07:41:59.98#ibcon#about to read 5, iclass 15, count 2 2006.281.07:41:59.98#ibcon#read 5, iclass 15, count 2 2006.281.07:41:59.98#ibcon#about to read 6, iclass 15, count 2 2006.281.07:41:59.98#ibcon#read 6, iclass 15, count 2 2006.281.07:41:59.98#ibcon#end of sib2, iclass 15, count 2 2006.281.07:41:59.98#ibcon#*mode == 0, iclass 15, count 2 2006.281.07:41:59.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.07:41:59.98#ibcon#[25=AT02-06\r\n] 2006.281.07:41:59.98#ibcon#*before write, iclass 15, count 2 2006.281.07:41:59.98#ibcon#enter sib2, iclass 15, count 2 2006.281.07:41:59.98#ibcon#flushed, iclass 15, count 2 2006.281.07:41:59.98#ibcon#about to write, iclass 15, count 2 2006.281.07:41:59.98#ibcon#wrote, iclass 15, count 2 2006.281.07:41:59.98#ibcon#about to read 3, iclass 15, count 2 2006.281.07:42:00.00#ibcon#read 3, iclass 15, count 2 2006.281.07:42:00.00#ibcon#about to read 4, iclass 15, count 2 2006.281.07:42:00.00#ibcon#read 4, iclass 15, count 2 2006.281.07:42:00.00#ibcon#about to read 5, iclass 15, count 2 2006.281.07:42:00.00#ibcon#read 5, iclass 15, count 2 2006.281.07:42:00.00#ibcon#about to read 6, iclass 15, count 2 2006.281.07:42:00.00#ibcon#read 6, iclass 15, count 2 2006.281.07:42:00.00#ibcon#end of sib2, iclass 15, count 2 2006.281.07:42:00.00#ibcon#*after write, iclass 15, count 2 2006.281.07:42:00.00#ibcon#*before return 0, iclass 15, count 2 2006.281.07:42:00.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:00.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:00.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.07:42:00.00#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:00.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:00.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:00.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:00.12#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:42:00.12#ibcon#first serial, iclass 15, count 0 2006.281.07:42:00.12#ibcon#enter sib2, iclass 15, count 0 2006.281.07:42:00.12#ibcon#flushed, iclass 15, count 0 2006.281.07:42:00.12#ibcon#about to write, iclass 15, count 0 2006.281.07:42:00.12#ibcon#wrote, iclass 15, count 0 2006.281.07:42:00.12#ibcon#about to read 3, iclass 15, count 0 2006.281.07:42:00.14#ibcon#read 3, iclass 15, count 0 2006.281.07:42:00.14#ibcon#about to read 4, iclass 15, count 0 2006.281.07:42:00.14#ibcon#read 4, iclass 15, count 0 2006.281.07:42:00.14#ibcon#about to read 5, iclass 15, count 0 2006.281.07:42:00.14#ibcon#read 5, iclass 15, count 0 2006.281.07:42:00.14#ibcon#about to read 6, iclass 15, count 0 2006.281.07:42:00.14#ibcon#read 6, iclass 15, count 0 2006.281.07:42:00.14#ibcon#end of sib2, iclass 15, count 0 2006.281.07:42:00.14#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:42:00.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:42:00.14#ibcon#[25=USB\r\n] 2006.281.07:42:00.14#ibcon#*before write, iclass 15, count 0 2006.281.07:42:00.14#ibcon#enter sib2, iclass 15, count 0 2006.281.07:42:00.14#ibcon#flushed, iclass 15, count 0 2006.281.07:42:00.14#ibcon#about to write, iclass 15, count 0 2006.281.07:42:00.14#ibcon#wrote, iclass 15, count 0 2006.281.07:42:00.14#ibcon#about to read 3, iclass 15, count 0 2006.281.07:42:00.18#ibcon#read 3, iclass 15, count 0 2006.281.07:42:00.18#ibcon#about to read 4, iclass 15, count 0 2006.281.07:42:00.18#ibcon#read 4, iclass 15, count 0 2006.281.07:42:00.18#ibcon#about to read 5, iclass 15, count 0 2006.281.07:42:00.18#ibcon#read 5, iclass 15, count 0 2006.281.07:42:00.18#ibcon#about to read 6, iclass 15, count 0 2006.281.07:42:00.18#ibcon#read 6, iclass 15, count 0 2006.281.07:42:00.18#ibcon#end of sib2, iclass 15, count 0 2006.281.07:42:00.18#ibcon#*after write, iclass 15, count 0 2006.281.07:42:00.18#ibcon#*before return 0, iclass 15, count 0 2006.281.07:42:00.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:00.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:00.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:42:00.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:42:00.18$vc4f8/valo=3,672.99 2006.281.07:42:00.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:42:00.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:42:00.18#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:00.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:00.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:00.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:00.18#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:42:00.18#ibcon#first serial, iclass 17, count 0 2006.281.07:42:00.18#ibcon#enter sib2, iclass 17, count 0 2006.281.07:42:00.18#ibcon#flushed, iclass 17, count 0 2006.281.07:42:00.18#ibcon#about to write, iclass 17, count 0 2006.281.07:42:00.18#ibcon#wrote, iclass 17, count 0 2006.281.07:42:00.18#ibcon#about to read 3, iclass 17, count 0 2006.281.07:42:00.19#ibcon#read 3, iclass 17, count 0 2006.281.07:42:00.19#ibcon#about to read 4, iclass 17, count 0 2006.281.07:42:00.19#ibcon#read 4, iclass 17, count 0 2006.281.07:42:00.19#ibcon#about to read 5, iclass 17, count 0 2006.281.07:42:00.19#ibcon#read 5, iclass 17, count 0 2006.281.07:42:00.19#ibcon#about to read 6, iclass 17, count 0 2006.281.07:42:00.19#ibcon#read 6, iclass 17, count 0 2006.281.07:42:00.19#ibcon#end of sib2, iclass 17, count 0 2006.281.07:42:00.19#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:42:00.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:42:00.22#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:42:00.22#ibcon#*before write, iclass 17, count 0 2006.281.07:42:00.22#ibcon#enter sib2, iclass 17, count 0 2006.281.07:42:00.22#ibcon#flushed, iclass 17, count 0 2006.281.07:42:00.22#ibcon#about to write, iclass 17, count 0 2006.281.07:42:00.22#ibcon#wrote, iclass 17, count 0 2006.281.07:42:00.22#ibcon#about to read 3, iclass 17, count 0 2006.281.07:42:00.25#ibcon#read 3, iclass 17, count 0 2006.281.07:42:00.25#ibcon#about to read 4, iclass 17, count 0 2006.281.07:42:00.25#ibcon#read 4, iclass 17, count 0 2006.281.07:42:00.25#ibcon#about to read 5, iclass 17, count 0 2006.281.07:42:00.25#ibcon#read 5, iclass 17, count 0 2006.281.07:42:00.25#ibcon#about to read 6, iclass 17, count 0 2006.281.07:42:00.25#ibcon#read 6, iclass 17, count 0 2006.281.07:42:00.25#ibcon#end of sib2, iclass 17, count 0 2006.281.07:42:00.25#ibcon#*after write, iclass 17, count 0 2006.281.07:42:00.25#ibcon#*before return 0, iclass 17, count 0 2006.281.07:42:00.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:00.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:00.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:42:00.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:42:00.25$vc4f8/va=3,6 2006.281.07:42:00.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.07:42:00.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.07:42:00.25#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:00.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:00.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:00.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:00.31#ibcon#enter wrdev, iclass 19, count 2 2006.281.07:42:00.31#ibcon#first serial, iclass 19, count 2 2006.281.07:42:00.31#ibcon#enter sib2, iclass 19, count 2 2006.281.07:42:00.31#ibcon#flushed, iclass 19, count 2 2006.281.07:42:00.31#ibcon#about to write, iclass 19, count 2 2006.281.07:42:00.31#ibcon#wrote, iclass 19, count 2 2006.281.07:42:00.31#ibcon#about to read 3, iclass 19, count 2 2006.281.07:42:00.32#ibcon#read 3, iclass 19, count 2 2006.281.07:42:00.32#ibcon#about to read 4, iclass 19, count 2 2006.281.07:42:00.32#ibcon#read 4, iclass 19, count 2 2006.281.07:42:00.32#ibcon#about to read 5, iclass 19, count 2 2006.281.07:42:00.32#ibcon#read 5, iclass 19, count 2 2006.281.07:42:00.32#ibcon#about to read 6, iclass 19, count 2 2006.281.07:42:00.32#ibcon#read 6, iclass 19, count 2 2006.281.07:42:00.32#ibcon#end of sib2, iclass 19, count 2 2006.281.07:42:00.32#ibcon#*mode == 0, iclass 19, count 2 2006.281.07:42:00.32#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.07:42:00.32#ibcon#[25=AT03-06\r\n] 2006.281.07:42:00.32#ibcon#*before write, iclass 19, count 2 2006.281.07:42:00.32#ibcon#enter sib2, iclass 19, count 2 2006.281.07:42:00.32#ibcon#flushed, iclass 19, count 2 2006.281.07:42:00.32#ibcon#about to write, iclass 19, count 2 2006.281.07:42:00.32#ibcon#wrote, iclass 19, count 2 2006.281.07:42:00.32#ibcon#about to read 3, iclass 19, count 2 2006.281.07:42:00.35#ibcon#read 3, iclass 19, count 2 2006.281.07:42:00.35#ibcon#about to read 4, iclass 19, count 2 2006.281.07:42:00.35#ibcon#read 4, iclass 19, count 2 2006.281.07:42:00.35#ibcon#about to read 5, iclass 19, count 2 2006.281.07:42:00.35#ibcon#read 5, iclass 19, count 2 2006.281.07:42:00.35#ibcon#about to read 6, iclass 19, count 2 2006.281.07:42:00.35#ibcon#read 6, iclass 19, count 2 2006.281.07:42:00.35#ibcon#end of sib2, iclass 19, count 2 2006.281.07:42:00.35#ibcon#*after write, iclass 19, count 2 2006.281.07:42:00.35#ibcon#*before return 0, iclass 19, count 2 2006.281.07:42:00.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:00.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:00.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.07:42:00.35#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:00.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:00.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:00.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:00.47#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:42:00.47#ibcon#first serial, iclass 19, count 0 2006.281.07:42:00.47#ibcon#enter sib2, iclass 19, count 0 2006.281.07:42:00.47#ibcon#flushed, iclass 19, count 0 2006.281.07:42:00.47#ibcon#about to write, iclass 19, count 0 2006.281.07:42:00.47#ibcon#wrote, iclass 19, count 0 2006.281.07:42:00.47#ibcon#about to read 3, iclass 19, count 0 2006.281.07:42:00.49#abcon#<5=/12 2.3 9.5 21.08 501001.1\r\n> 2006.281.07:42:00.49#ibcon#read 3, iclass 19, count 0 2006.281.07:42:00.49#ibcon#about to read 4, iclass 19, count 0 2006.281.07:42:00.49#ibcon#read 4, iclass 19, count 0 2006.281.07:42:00.49#ibcon#about to read 5, iclass 19, count 0 2006.281.07:42:00.49#ibcon#read 5, iclass 19, count 0 2006.281.07:42:00.49#ibcon#about to read 6, iclass 19, count 0 2006.281.07:42:00.49#ibcon#read 6, iclass 19, count 0 2006.281.07:42:00.49#ibcon#end of sib2, iclass 19, count 0 2006.281.07:42:00.49#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:42:00.49#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:42:00.49#ibcon#[25=USB\r\n] 2006.281.07:42:00.49#ibcon#*before write, iclass 19, count 0 2006.281.07:42:00.49#ibcon#enter sib2, iclass 19, count 0 2006.281.07:42:00.49#ibcon#flushed, iclass 19, count 0 2006.281.07:42:00.49#ibcon#about to write, iclass 19, count 0 2006.281.07:42:00.49#ibcon#wrote, iclass 19, count 0 2006.281.07:42:00.49#ibcon#about to read 3, iclass 19, count 0 2006.281.07:42:00.50#abcon#{5=INTERFACE CLEAR} 2006.281.07:42:00.52#ibcon#read 3, iclass 19, count 0 2006.281.07:42:00.52#ibcon#about to read 4, iclass 19, count 0 2006.281.07:42:00.52#ibcon#read 4, iclass 19, count 0 2006.281.07:42:00.52#ibcon#about to read 5, iclass 19, count 0 2006.281.07:42:00.52#ibcon#read 5, iclass 19, count 0 2006.281.07:42:00.53#ibcon#about to read 6, iclass 19, count 0 2006.281.07:42:00.53#ibcon#read 6, iclass 19, count 0 2006.281.07:42:00.53#ibcon#end of sib2, iclass 19, count 0 2006.281.07:42:00.53#ibcon#*after write, iclass 19, count 0 2006.281.07:42:00.53#ibcon#*before return 0, iclass 19, count 0 2006.281.07:42:00.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:00.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:00.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:42:00.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:42:00.53$vc4f8/valo=4,832.99 2006.281.07:42:00.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:42:00.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:42:00.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:00.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:42:00.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:42:00.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:42:00.53#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:42:00.53#ibcon#first serial, iclass 24, count 0 2006.281.07:42:00.53#ibcon#enter sib2, iclass 24, count 0 2006.281.07:42:00.53#ibcon#flushed, iclass 24, count 0 2006.281.07:42:00.53#ibcon#about to write, iclass 24, count 0 2006.281.07:42:00.53#ibcon#wrote, iclass 24, count 0 2006.281.07:42:00.53#ibcon#about to read 3, iclass 24, count 0 2006.281.07:42:00.54#ibcon#read 3, iclass 24, count 0 2006.281.07:42:00.54#ibcon#about to read 4, iclass 24, count 0 2006.281.07:42:00.54#ibcon#read 4, iclass 24, count 0 2006.281.07:42:00.54#ibcon#about to read 5, iclass 24, count 0 2006.281.07:42:00.54#ibcon#read 5, iclass 24, count 0 2006.281.07:42:00.54#ibcon#about to read 6, iclass 24, count 0 2006.281.07:42:00.54#ibcon#read 6, iclass 24, count 0 2006.281.07:42:00.54#ibcon#end of sib2, iclass 24, count 0 2006.281.07:42:00.54#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:42:00.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:42:00.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:42:00.54#ibcon#*before write, iclass 24, count 0 2006.281.07:42:00.54#ibcon#enter sib2, iclass 24, count 0 2006.281.07:42:00.54#ibcon#flushed, iclass 24, count 0 2006.281.07:42:00.54#ibcon#about to write, iclass 24, count 0 2006.281.07:42:00.54#ibcon#wrote, iclass 24, count 0 2006.281.07:42:00.54#ibcon#about to read 3, iclass 24, count 0 2006.281.07:42:00.56#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:42:00.58#ibcon#read 3, iclass 24, count 0 2006.281.07:42:00.58#ibcon#about to read 4, iclass 24, count 0 2006.281.07:42:00.58#ibcon#read 4, iclass 24, count 0 2006.281.07:42:00.58#ibcon#about to read 5, iclass 24, count 0 2006.281.07:42:00.58#ibcon#read 5, iclass 24, count 0 2006.281.07:42:00.58#ibcon#about to read 6, iclass 24, count 0 2006.281.07:42:00.58#ibcon#read 6, iclass 24, count 0 2006.281.07:42:00.58#ibcon#end of sib2, iclass 24, count 0 2006.281.07:42:00.58#ibcon#*after write, iclass 24, count 0 2006.281.07:42:00.58#ibcon#*before return 0, iclass 24, count 0 2006.281.07:42:00.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:42:00.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:42:00.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:42:00.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:42:00.58$vc4f8/va=4,6 2006.281.07:42:00.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.07:42:00.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.07:42:00.58#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:00.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:00.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:00.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:00.65#ibcon#enter wrdev, iclass 27, count 2 2006.281.07:42:00.65#ibcon#first serial, iclass 27, count 2 2006.281.07:42:00.65#ibcon#enter sib2, iclass 27, count 2 2006.281.07:42:00.65#ibcon#flushed, iclass 27, count 2 2006.281.07:42:00.65#ibcon#about to write, iclass 27, count 2 2006.281.07:42:00.65#ibcon#wrote, iclass 27, count 2 2006.281.07:42:00.65#ibcon#about to read 3, iclass 27, count 2 2006.281.07:42:00.67#ibcon#read 3, iclass 27, count 2 2006.281.07:42:00.67#ibcon#about to read 4, iclass 27, count 2 2006.281.07:42:00.67#ibcon#read 4, iclass 27, count 2 2006.281.07:42:00.67#ibcon#about to read 5, iclass 27, count 2 2006.281.07:42:00.67#ibcon#read 5, iclass 27, count 2 2006.281.07:42:00.67#ibcon#about to read 6, iclass 27, count 2 2006.281.07:42:00.67#ibcon#read 6, iclass 27, count 2 2006.281.07:42:00.67#ibcon#end of sib2, iclass 27, count 2 2006.281.07:42:00.67#ibcon#*mode == 0, iclass 27, count 2 2006.281.07:42:00.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.07:42:00.67#ibcon#[25=AT04-06\r\n] 2006.281.07:42:00.67#ibcon#*before write, iclass 27, count 2 2006.281.07:42:00.67#ibcon#enter sib2, iclass 27, count 2 2006.281.07:42:00.67#ibcon#flushed, iclass 27, count 2 2006.281.07:42:00.67#ibcon#about to write, iclass 27, count 2 2006.281.07:42:00.67#ibcon#wrote, iclass 27, count 2 2006.281.07:42:00.67#ibcon#about to read 3, iclass 27, count 2 2006.281.07:42:00.70#ibcon#read 3, iclass 27, count 2 2006.281.07:42:00.70#ibcon#about to read 4, iclass 27, count 2 2006.281.07:42:00.70#ibcon#read 4, iclass 27, count 2 2006.281.07:42:00.70#ibcon#about to read 5, iclass 27, count 2 2006.281.07:42:00.70#ibcon#read 5, iclass 27, count 2 2006.281.07:42:00.70#ibcon#about to read 6, iclass 27, count 2 2006.281.07:42:00.70#ibcon#read 6, iclass 27, count 2 2006.281.07:42:00.70#ibcon#end of sib2, iclass 27, count 2 2006.281.07:42:00.70#ibcon#*after write, iclass 27, count 2 2006.281.07:42:00.70#ibcon#*before return 0, iclass 27, count 2 2006.281.07:42:00.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:00.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:00.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.07:42:00.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:00.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:00.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:00.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:00.82#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:42:00.82#ibcon#first serial, iclass 27, count 0 2006.281.07:42:00.82#ibcon#enter sib2, iclass 27, count 0 2006.281.07:42:00.82#ibcon#flushed, iclass 27, count 0 2006.281.07:42:00.82#ibcon#about to write, iclass 27, count 0 2006.281.07:42:00.82#ibcon#wrote, iclass 27, count 0 2006.281.07:42:00.82#ibcon#about to read 3, iclass 27, count 0 2006.281.07:42:00.84#ibcon#read 3, iclass 27, count 0 2006.281.07:42:00.84#ibcon#about to read 4, iclass 27, count 0 2006.281.07:42:00.84#ibcon#read 4, iclass 27, count 0 2006.281.07:42:00.84#ibcon#about to read 5, iclass 27, count 0 2006.281.07:42:00.84#ibcon#read 5, iclass 27, count 0 2006.281.07:42:00.84#ibcon#about to read 6, iclass 27, count 0 2006.281.07:42:00.84#ibcon#read 6, iclass 27, count 0 2006.281.07:42:00.84#ibcon#end of sib2, iclass 27, count 0 2006.281.07:42:00.84#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:42:00.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:42:00.84#ibcon#[25=USB\r\n] 2006.281.07:42:00.84#ibcon#*before write, iclass 27, count 0 2006.281.07:42:00.84#ibcon#enter sib2, iclass 27, count 0 2006.281.07:42:00.84#ibcon#flushed, iclass 27, count 0 2006.281.07:42:00.84#ibcon#about to write, iclass 27, count 0 2006.281.07:42:00.84#ibcon#wrote, iclass 27, count 0 2006.281.07:42:00.84#ibcon#about to read 3, iclass 27, count 0 2006.281.07:42:00.87#ibcon#read 3, iclass 27, count 0 2006.281.07:42:00.87#ibcon#about to read 4, iclass 27, count 0 2006.281.07:42:00.87#ibcon#read 4, iclass 27, count 0 2006.281.07:42:00.87#ibcon#about to read 5, iclass 27, count 0 2006.281.07:42:00.87#ibcon#read 5, iclass 27, count 0 2006.281.07:42:00.87#ibcon#about to read 6, iclass 27, count 0 2006.281.07:42:00.87#ibcon#read 6, iclass 27, count 0 2006.281.07:42:00.87#ibcon#end of sib2, iclass 27, count 0 2006.281.07:42:00.87#ibcon#*after write, iclass 27, count 0 2006.281.07:42:00.87#ibcon#*before return 0, iclass 27, count 0 2006.281.07:42:00.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:00.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:00.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:42:00.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:42:00.87$vc4f8/valo=5,652.99 2006.281.07:42:00.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.07:42:00.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.07:42:00.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:00.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:00.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:00.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:00.87#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:42:00.87#ibcon#first serial, iclass 29, count 0 2006.281.07:42:00.87#ibcon#enter sib2, iclass 29, count 0 2006.281.07:42:00.87#ibcon#flushed, iclass 29, count 0 2006.281.07:42:00.87#ibcon#about to write, iclass 29, count 0 2006.281.07:42:00.87#ibcon#wrote, iclass 29, count 0 2006.281.07:42:00.87#ibcon#about to read 3, iclass 29, count 0 2006.281.07:42:00.89#ibcon#read 3, iclass 29, count 0 2006.281.07:42:00.89#ibcon#about to read 4, iclass 29, count 0 2006.281.07:42:00.89#ibcon#read 4, iclass 29, count 0 2006.281.07:42:00.89#ibcon#about to read 5, iclass 29, count 0 2006.281.07:42:00.89#ibcon#read 5, iclass 29, count 0 2006.281.07:42:00.89#ibcon#about to read 6, iclass 29, count 0 2006.281.07:42:00.89#ibcon#read 6, iclass 29, count 0 2006.281.07:42:00.89#ibcon#end of sib2, iclass 29, count 0 2006.281.07:42:00.89#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:42:00.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:42:00.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:42:00.89#ibcon#*before write, iclass 29, count 0 2006.281.07:42:00.89#ibcon#enter sib2, iclass 29, count 0 2006.281.07:42:00.89#ibcon#flushed, iclass 29, count 0 2006.281.07:42:00.89#ibcon#about to write, iclass 29, count 0 2006.281.07:42:00.89#ibcon#wrote, iclass 29, count 0 2006.281.07:42:00.89#ibcon#about to read 3, iclass 29, count 0 2006.281.07:42:00.93#ibcon#read 3, iclass 29, count 0 2006.281.07:42:00.93#ibcon#about to read 4, iclass 29, count 0 2006.281.07:42:00.93#ibcon#read 4, iclass 29, count 0 2006.281.07:42:00.93#ibcon#about to read 5, iclass 29, count 0 2006.281.07:42:00.93#ibcon#read 5, iclass 29, count 0 2006.281.07:42:00.93#ibcon#about to read 6, iclass 29, count 0 2006.281.07:42:00.93#ibcon#read 6, iclass 29, count 0 2006.281.07:42:00.93#ibcon#end of sib2, iclass 29, count 0 2006.281.07:42:00.93#ibcon#*after write, iclass 29, count 0 2006.281.07:42:00.93#ibcon#*before return 0, iclass 29, count 0 2006.281.07:42:00.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:00.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:00.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:42:00.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:42:00.93$vc4f8/va=5,7 2006.281.07:42:00.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.07:42:00.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.07:42:00.93#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:00.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:01.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:01.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:01.00#ibcon#enter wrdev, iclass 31, count 2 2006.281.07:42:01.00#ibcon#first serial, iclass 31, count 2 2006.281.07:42:01.00#ibcon#enter sib2, iclass 31, count 2 2006.281.07:42:01.00#ibcon#flushed, iclass 31, count 2 2006.281.07:42:01.00#ibcon#about to write, iclass 31, count 2 2006.281.07:42:01.00#ibcon#wrote, iclass 31, count 2 2006.281.07:42:01.00#ibcon#about to read 3, iclass 31, count 2 2006.281.07:42:01.01#ibcon#read 3, iclass 31, count 2 2006.281.07:42:01.01#ibcon#about to read 4, iclass 31, count 2 2006.281.07:42:01.01#ibcon#read 4, iclass 31, count 2 2006.281.07:42:01.01#ibcon#about to read 5, iclass 31, count 2 2006.281.07:42:01.01#ibcon#read 5, iclass 31, count 2 2006.281.07:42:01.01#ibcon#about to read 6, iclass 31, count 2 2006.281.07:42:01.01#ibcon#read 6, iclass 31, count 2 2006.281.07:42:01.01#ibcon#end of sib2, iclass 31, count 2 2006.281.07:42:01.01#ibcon#*mode == 0, iclass 31, count 2 2006.281.07:42:01.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.07:42:01.01#ibcon#[25=AT05-07\r\n] 2006.281.07:42:01.01#ibcon#*before write, iclass 31, count 2 2006.281.07:42:01.01#ibcon#enter sib2, iclass 31, count 2 2006.281.07:42:01.01#ibcon#flushed, iclass 31, count 2 2006.281.07:42:01.01#ibcon#about to write, iclass 31, count 2 2006.281.07:42:01.01#ibcon#wrote, iclass 31, count 2 2006.281.07:42:01.01#ibcon#about to read 3, iclass 31, count 2 2006.281.07:42:01.04#ibcon#read 3, iclass 31, count 2 2006.281.07:42:01.04#ibcon#about to read 4, iclass 31, count 2 2006.281.07:42:01.04#ibcon#read 4, iclass 31, count 2 2006.281.07:42:01.04#ibcon#about to read 5, iclass 31, count 2 2006.281.07:42:01.04#ibcon#read 5, iclass 31, count 2 2006.281.07:42:01.04#ibcon#about to read 6, iclass 31, count 2 2006.281.07:42:01.04#ibcon#read 6, iclass 31, count 2 2006.281.07:42:01.04#ibcon#end of sib2, iclass 31, count 2 2006.281.07:42:01.04#ibcon#*after write, iclass 31, count 2 2006.281.07:42:01.04#ibcon#*before return 0, iclass 31, count 2 2006.281.07:42:01.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:01.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:01.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.07:42:01.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:01.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:01.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:01.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:01.16#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:42:01.16#ibcon#first serial, iclass 31, count 0 2006.281.07:42:01.16#ibcon#enter sib2, iclass 31, count 0 2006.281.07:42:01.16#ibcon#flushed, iclass 31, count 0 2006.281.07:42:01.16#ibcon#about to write, iclass 31, count 0 2006.281.07:42:01.16#ibcon#wrote, iclass 31, count 0 2006.281.07:42:01.16#ibcon#about to read 3, iclass 31, count 0 2006.281.07:42:01.18#ibcon#read 3, iclass 31, count 0 2006.281.07:42:01.18#ibcon#about to read 4, iclass 31, count 0 2006.281.07:42:01.18#ibcon#read 4, iclass 31, count 0 2006.281.07:42:01.18#ibcon#about to read 5, iclass 31, count 0 2006.281.07:42:01.18#ibcon#read 5, iclass 31, count 0 2006.281.07:42:01.18#ibcon#about to read 6, iclass 31, count 0 2006.281.07:42:01.18#ibcon#read 6, iclass 31, count 0 2006.281.07:42:01.18#ibcon#end of sib2, iclass 31, count 0 2006.281.07:42:01.18#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:42:01.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:42:01.18#ibcon#[25=USB\r\n] 2006.281.07:42:01.18#ibcon#*before write, iclass 31, count 0 2006.281.07:42:01.18#ibcon#enter sib2, iclass 31, count 0 2006.281.07:42:01.18#ibcon#flushed, iclass 31, count 0 2006.281.07:42:01.18#ibcon#about to write, iclass 31, count 0 2006.281.07:42:01.18#ibcon#wrote, iclass 31, count 0 2006.281.07:42:01.18#ibcon#about to read 3, iclass 31, count 0 2006.281.07:42:01.21#ibcon#read 3, iclass 31, count 0 2006.281.07:42:01.21#ibcon#about to read 4, iclass 31, count 0 2006.281.07:42:01.21#ibcon#read 4, iclass 31, count 0 2006.281.07:42:01.21#ibcon#about to read 5, iclass 31, count 0 2006.281.07:42:01.21#ibcon#read 5, iclass 31, count 0 2006.281.07:42:01.21#ibcon#about to read 6, iclass 31, count 0 2006.281.07:42:01.21#ibcon#read 6, iclass 31, count 0 2006.281.07:42:01.21#ibcon#end of sib2, iclass 31, count 0 2006.281.07:42:01.21#ibcon#*after write, iclass 31, count 0 2006.281.07:42:01.21#ibcon#*before return 0, iclass 31, count 0 2006.281.07:42:01.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:01.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:01.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:42:01.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:42:01.21$vc4f8/valo=6,772.99 2006.281.07:42:01.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.07:42:01.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.07:42:01.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:01.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:01.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:01.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:01.21#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:42:01.21#ibcon#first serial, iclass 33, count 0 2006.281.07:42:01.21#ibcon#enter sib2, iclass 33, count 0 2006.281.07:42:01.21#ibcon#flushed, iclass 33, count 0 2006.281.07:42:01.21#ibcon#about to write, iclass 33, count 0 2006.281.07:42:01.21#ibcon#wrote, iclass 33, count 0 2006.281.07:42:01.21#ibcon#about to read 3, iclass 33, count 0 2006.281.07:42:01.23#ibcon#read 3, iclass 33, count 0 2006.281.07:42:01.23#ibcon#about to read 4, iclass 33, count 0 2006.281.07:42:01.23#ibcon#read 4, iclass 33, count 0 2006.281.07:42:01.23#ibcon#about to read 5, iclass 33, count 0 2006.281.07:42:01.23#ibcon#read 5, iclass 33, count 0 2006.281.07:42:01.23#ibcon#about to read 6, iclass 33, count 0 2006.281.07:42:01.23#ibcon#read 6, iclass 33, count 0 2006.281.07:42:01.23#ibcon#end of sib2, iclass 33, count 0 2006.281.07:42:01.23#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:42:01.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:42:01.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:42:01.23#ibcon#*before write, iclass 33, count 0 2006.281.07:42:01.23#ibcon#enter sib2, iclass 33, count 0 2006.281.07:42:01.23#ibcon#flushed, iclass 33, count 0 2006.281.07:42:01.23#ibcon#about to write, iclass 33, count 0 2006.281.07:42:01.23#ibcon#wrote, iclass 33, count 0 2006.281.07:42:01.23#ibcon#about to read 3, iclass 33, count 0 2006.281.07:42:01.27#ibcon#read 3, iclass 33, count 0 2006.281.07:42:01.27#ibcon#about to read 4, iclass 33, count 0 2006.281.07:42:01.27#ibcon#read 4, iclass 33, count 0 2006.281.07:42:01.27#ibcon#about to read 5, iclass 33, count 0 2006.281.07:42:01.27#ibcon#read 5, iclass 33, count 0 2006.281.07:42:01.27#ibcon#about to read 6, iclass 33, count 0 2006.281.07:42:01.27#ibcon#read 6, iclass 33, count 0 2006.281.07:42:01.27#ibcon#end of sib2, iclass 33, count 0 2006.281.07:42:01.27#ibcon#*after write, iclass 33, count 0 2006.281.07:42:01.27#ibcon#*before return 0, iclass 33, count 0 2006.281.07:42:01.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:01.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:01.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:42:01.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:42:01.27$vc4f8/va=6,6 2006.281.07:42:01.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.07:42:01.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.07:42:01.27#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:01.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:01.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:01.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:01.33#ibcon#enter wrdev, iclass 35, count 2 2006.281.07:42:01.33#ibcon#first serial, iclass 35, count 2 2006.281.07:42:01.33#ibcon#enter sib2, iclass 35, count 2 2006.281.07:42:01.33#ibcon#flushed, iclass 35, count 2 2006.281.07:42:01.33#ibcon#about to write, iclass 35, count 2 2006.281.07:42:01.33#ibcon#wrote, iclass 35, count 2 2006.281.07:42:01.33#ibcon#about to read 3, iclass 35, count 2 2006.281.07:42:01.35#ibcon#read 3, iclass 35, count 2 2006.281.07:42:01.35#ibcon#about to read 4, iclass 35, count 2 2006.281.07:42:01.35#ibcon#read 4, iclass 35, count 2 2006.281.07:42:01.35#ibcon#about to read 5, iclass 35, count 2 2006.281.07:42:01.35#ibcon#read 5, iclass 35, count 2 2006.281.07:42:01.35#ibcon#about to read 6, iclass 35, count 2 2006.281.07:42:01.35#ibcon#read 6, iclass 35, count 2 2006.281.07:42:01.35#ibcon#end of sib2, iclass 35, count 2 2006.281.07:42:01.35#ibcon#*mode == 0, iclass 35, count 2 2006.281.07:42:01.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.07:42:01.35#ibcon#[25=AT06-06\r\n] 2006.281.07:42:01.35#ibcon#*before write, iclass 35, count 2 2006.281.07:42:01.35#ibcon#enter sib2, iclass 35, count 2 2006.281.07:42:01.35#ibcon#flushed, iclass 35, count 2 2006.281.07:42:01.35#ibcon#about to write, iclass 35, count 2 2006.281.07:42:01.35#ibcon#wrote, iclass 35, count 2 2006.281.07:42:01.35#ibcon#about to read 3, iclass 35, count 2 2006.281.07:42:01.39#ibcon#read 3, iclass 35, count 2 2006.281.07:42:01.39#ibcon#about to read 4, iclass 35, count 2 2006.281.07:42:01.39#ibcon#read 4, iclass 35, count 2 2006.281.07:42:01.39#ibcon#about to read 5, iclass 35, count 2 2006.281.07:42:01.39#ibcon#read 5, iclass 35, count 2 2006.281.07:42:01.39#ibcon#about to read 6, iclass 35, count 2 2006.281.07:42:01.39#ibcon#read 6, iclass 35, count 2 2006.281.07:42:01.39#ibcon#end of sib2, iclass 35, count 2 2006.281.07:42:01.39#ibcon#*after write, iclass 35, count 2 2006.281.07:42:01.39#ibcon#*before return 0, iclass 35, count 2 2006.281.07:42:01.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:01.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:01.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.07:42:01.39#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:01.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:42:01.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:42:01.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:42:01.50#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:42:01.50#ibcon#first serial, iclass 35, count 0 2006.281.07:42:01.50#ibcon#enter sib2, iclass 35, count 0 2006.281.07:42:01.50#ibcon#flushed, iclass 35, count 0 2006.281.07:42:01.50#ibcon#about to write, iclass 35, count 0 2006.281.07:42:01.50#ibcon#wrote, iclass 35, count 0 2006.281.07:42:01.50#ibcon#about to read 3, iclass 35, count 0 2006.281.07:42:01.52#ibcon#read 3, iclass 35, count 0 2006.281.07:42:01.52#ibcon#about to read 4, iclass 35, count 0 2006.281.07:42:01.52#ibcon#read 4, iclass 35, count 0 2006.281.07:42:01.52#ibcon#about to read 5, iclass 35, count 0 2006.281.07:42:01.52#ibcon#read 5, iclass 35, count 0 2006.281.07:42:01.52#ibcon#about to read 6, iclass 35, count 0 2006.281.07:42:01.52#ibcon#read 6, iclass 35, count 0 2006.281.07:42:01.52#ibcon#end of sib2, iclass 35, count 0 2006.281.07:42:01.52#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:42:01.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:42:01.52#ibcon#[25=USB\r\n] 2006.281.07:42:01.52#ibcon#*before write, iclass 35, count 0 2006.281.07:42:01.52#ibcon#enter sib2, iclass 35, count 0 2006.281.07:42:01.52#ibcon#flushed, iclass 35, count 0 2006.281.07:42:01.52#ibcon#about to write, iclass 35, count 0 2006.281.07:42:01.52#ibcon#wrote, iclass 35, count 0 2006.281.07:42:01.52#ibcon#about to read 3, iclass 35, count 0 2006.281.07:42:01.55#ibcon#read 3, iclass 35, count 0 2006.281.07:42:01.55#ibcon#about to read 4, iclass 35, count 0 2006.281.07:42:01.55#ibcon#read 4, iclass 35, count 0 2006.281.07:42:01.55#ibcon#about to read 5, iclass 35, count 0 2006.281.07:42:01.55#ibcon#read 5, iclass 35, count 0 2006.281.07:42:01.55#ibcon#about to read 6, iclass 35, count 0 2006.281.07:42:01.55#ibcon#read 6, iclass 35, count 0 2006.281.07:42:01.55#ibcon#end of sib2, iclass 35, count 0 2006.281.07:42:01.55#ibcon#*after write, iclass 35, count 0 2006.281.07:42:01.55#ibcon#*before return 0, iclass 35, count 0 2006.281.07:42:01.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:42:01.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:42:01.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:42:01.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:42:01.55$vc4f8/valo=7,832.99 2006.281.07:42:01.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.07:42:01.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.07:42:01.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:01.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:42:01.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:42:01.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:42:01.55#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:42:01.55#ibcon#first serial, iclass 37, count 0 2006.281.07:42:01.55#ibcon#enter sib2, iclass 37, count 0 2006.281.07:42:01.55#ibcon#flushed, iclass 37, count 0 2006.281.07:42:01.55#ibcon#about to write, iclass 37, count 0 2006.281.07:42:01.55#ibcon#wrote, iclass 37, count 0 2006.281.07:42:01.55#ibcon#about to read 3, iclass 37, count 0 2006.281.07:42:01.57#ibcon#read 3, iclass 37, count 0 2006.281.07:42:01.57#ibcon#about to read 4, iclass 37, count 0 2006.281.07:42:01.57#ibcon#read 4, iclass 37, count 0 2006.281.07:42:01.57#ibcon#about to read 5, iclass 37, count 0 2006.281.07:42:01.57#ibcon#read 5, iclass 37, count 0 2006.281.07:42:01.57#ibcon#about to read 6, iclass 37, count 0 2006.281.07:42:01.57#ibcon#read 6, iclass 37, count 0 2006.281.07:42:01.57#ibcon#end of sib2, iclass 37, count 0 2006.281.07:42:01.57#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:42:01.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:42:01.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:42:01.57#ibcon#*before write, iclass 37, count 0 2006.281.07:42:01.57#ibcon#enter sib2, iclass 37, count 0 2006.281.07:42:01.57#ibcon#flushed, iclass 37, count 0 2006.281.07:42:01.57#ibcon#about to write, iclass 37, count 0 2006.281.07:42:01.57#ibcon#wrote, iclass 37, count 0 2006.281.07:42:01.57#ibcon#about to read 3, iclass 37, count 0 2006.281.07:42:01.62#ibcon#read 3, iclass 37, count 0 2006.281.07:42:01.62#ibcon#about to read 4, iclass 37, count 0 2006.281.07:42:01.62#ibcon#read 4, iclass 37, count 0 2006.281.07:42:01.62#ibcon#about to read 5, iclass 37, count 0 2006.281.07:42:01.62#ibcon#read 5, iclass 37, count 0 2006.281.07:42:01.62#ibcon#about to read 6, iclass 37, count 0 2006.281.07:42:01.62#ibcon#read 6, iclass 37, count 0 2006.281.07:42:01.62#ibcon#end of sib2, iclass 37, count 0 2006.281.07:42:01.62#ibcon#*after write, iclass 37, count 0 2006.281.07:42:01.62#ibcon#*before return 0, iclass 37, count 0 2006.281.07:42:01.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:42:01.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:42:01.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:42:01.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:42:01.62$vc4f8/va=7,6 2006.281.07:42:01.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.07:42:01.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.07:42:01.62#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:01.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:42:01.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:42:01.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:42:01.66#ibcon#enter wrdev, iclass 39, count 2 2006.281.07:42:01.66#ibcon#first serial, iclass 39, count 2 2006.281.07:42:01.66#ibcon#enter sib2, iclass 39, count 2 2006.281.07:42:01.66#ibcon#flushed, iclass 39, count 2 2006.281.07:42:01.66#ibcon#about to write, iclass 39, count 2 2006.281.07:42:01.66#ibcon#wrote, iclass 39, count 2 2006.281.07:42:01.66#ibcon#about to read 3, iclass 39, count 2 2006.281.07:42:01.69#ibcon#read 3, iclass 39, count 2 2006.281.07:42:01.69#ibcon#about to read 4, iclass 39, count 2 2006.281.07:42:01.69#ibcon#read 4, iclass 39, count 2 2006.281.07:42:01.69#ibcon#about to read 5, iclass 39, count 2 2006.281.07:42:01.69#ibcon#read 5, iclass 39, count 2 2006.281.07:42:01.69#ibcon#about to read 6, iclass 39, count 2 2006.281.07:42:01.69#ibcon#read 6, iclass 39, count 2 2006.281.07:42:01.69#ibcon#end of sib2, iclass 39, count 2 2006.281.07:42:01.69#ibcon#*mode == 0, iclass 39, count 2 2006.281.07:42:01.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.07:42:01.69#ibcon#[25=AT07-06\r\n] 2006.281.07:42:01.69#ibcon#*before write, iclass 39, count 2 2006.281.07:42:01.69#ibcon#enter sib2, iclass 39, count 2 2006.281.07:42:01.69#ibcon#flushed, iclass 39, count 2 2006.281.07:42:01.69#ibcon#about to write, iclass 39, count 2 2006.281.07:42:01.69#ibcon#wrote, iclass 39, count 2 2006.281.07:42:01.69#ibcon#about to read 3, iclass 39, count 2 2006.281.07:42:01.72#ibcon#read 3, iclass 39, count 2 2006.281.07:42:01.72#ibcon#about to read 4, iclass 39, count 2 2006.281.07:42:01.72#ibcon#read 4, iclass 39, count 2 2006.281.07:42:01.72#ibcon#about to read 5, iclass 39, count 2 2006.281.07:42:01.72#ibcon#read 5, iclass 39, count 2 2006.281.07:42:01.72#ibcon#about to read 6, iclass 39, count 2 2006.281.07:42:01.72#ibcon#read 6, iclass 39, count 2 2006.281.07:42:01.72#ibcon#end of sib2, iclass 39, count 2 2006.281.07:42:01.72#ibcon#*after write, iclass 39, count 2 2006.281.07:42:01.72#ibcon#*before return 0, iclass 39, count 2 2006.281.07:42:01.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:42:01.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:42:01.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.07:42:01.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:01.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:42:01.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:42:01.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:42:01.84#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:42:01.84#ibcon#first serial, iclass 39, count 0 2006.281.07:42:01.84#ibcon#enter sib2, iclass 39, count 0 2006.281.07:42:01.84#ibcon#flushed, iclass 39, count 0 2006.281.07:42:01.84#ibcon#about to write, iclass 39, count 0 2006.281.07:42:01.84#ibcon#wrote, iclass 39, count 0 2006.281.07:42:01.84#ibcon#about to read 3, iclass 39, count 0 2006.281.07:42:01.86#ibcon#read 3, iclass 39, count 0 2006.281.07:42:01.86#ibcon#about to read 4, iclass 39, count 0 2006.281.07:42:01.86#ibcon#read 4, iclass 39, count 0 2006.281.07:42:01.86#ibcon#about to read 5, iclass 39, count 0 2006.281.07:42:01.86#ibcon#read 5, iclass 39, count 0 2006.281.07:42:01.86#ibcon#about to read 6, iclass 39, count 0 2006.281.07:42:01.86#ibcon#read 6, iclass 39, count 0 2006.281.07:42:01.86#ibcon#end of sib2, iclass 39, count 0 2006.281.07:42:01.86#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:42:01.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:42:01.86#ibcon#[25=USB\r\n] 2006.281.07:42:01.86#ibcon#*before write, iclass 39, count 0 2006.281.07:42:01.86#ibcon#enter sib2, iclass 39, count 0 2006.281.07:42:01.86#ibcon#flushed, iclass 39, count 0 2006.281.07:42:01.86#ibcon#about to write, iclass 39, count 0 2006.281.07:42:01.86#ibcon#wrote, iclass 39, count 0 2006.281.07:42:01.86#ibcon#about to read 3, iclass 39, count 0 2006.281.07:42:01.90#ibcon#read 3, iclass 39, count 0 2006.281.07:42:01.90#ibcon#about to read 4, iclass 39, count 0 2006.281.07:42:01.90#ibcon#read 4, iclass 39, count 0 2006.281.07:42:01.90#ibcon#about to read 5, iclass 39, count 0 2006.281.07:42:01.90#ibcon#read 5, iclass 39, count 0 2006.281.07:42:01.90#ibcon#about to read 6, iclass 39, count 0 2006.281.07:42:01.90#ibcon#read 6, iclass 39, count 0 2006.281.07:42:01.90#ibcon#end of sib2, iclass 39, count 0 2006.281.07:42:01.90#ibcon#*after write, iclass 39, count 0 2006.281.07:42:01.90#ibcon#*before return 0, iclass 39, count 0 2006.281.07:42:01.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:42:01.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:42:01.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:42:01.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:42:01.90$vc4f8/valo=8,852.99 2006.281.07:42:01.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.07:42:01.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.07:42:01.90#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:01.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:42:01.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:42:01.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:42:01.90#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:42:01.90#ibcon#first serial, iclass 3, count 0 2006.281.07:42:01.90#ibcon#enter sib2, iclass 3, count 0 2006.281.07:42:01.90#ibcon#flushed, iclass 3, count 0 2006.281.07:42:01.90#ibcon#about to write, iclass 3, count 0 2006.281.07:42:01.90#ibcon#wrote, iclass 3, count 0 2006.281.07:42:01.90#ibcon#about to read 3, iclass 3, count 0 2006.281.07:42:01.91#ibcon#read 3, iclass 3, count 0 2006.281.07:42:01.91#ibcon#about to read 4, iclass 3, count 0 2006.281.07:42:01.91#ibcon#read 4, iclass 3, count 0 2006.281.07:42:01.91#ibcon#about to read 5, iclass 3, count 0 2006.281.07:42:01.91#ibcon#read 5, iclass 3, count 0 2006.281.07:42:01.91#ibcon#about to read 6, iclass 3, count 0 2006.281.07:42:01.91#ibcon#read 6, iclass 3, count 0 2006.281.07:42:01.91#ibcon#end of sib2, iclass 3, count 0 2006.281.07:42:01.91#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:42:01.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:42:01.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:42:01.91#ibcon#*before write, iclass 3, count 0 2006.281.07:42:01.91#ibcon#enter sib2, iclass 3, count 0 2006.281.07:42:01.91#ibcon#flushed, iclass 3, count 0 2006.281.07:42:01.91#ibcon#about to write, iclass 3, count 0 2006.281.07:42:01.94#ibcon#wrote, iclass 3, count 0 2006.281.07:42:01.94#ibcon#about to read 3, iclass 3, count 0 2006.281.07:42:01.97#ibcon#read 3, iclass 3, count 0 2006.281.07:42:01.97#ibcon#about to read 4, iclass 3, count 0 2006.281.07:42:01.97#ibcon#read 4, iclass 3, count 0 2006.281.07:42:01.97#ibcon#about to read 5, iclass 3, count 0 2006.281.07:42:01.97#ibcon#read 5, iclass 3, count 0 2006.281.07:42:01.97#ibcon#about to read 6, iclass 3, count 0 2006.281.07:42:01.97#ibcon#read 6, iclass 3, count 0 2006.281.07:42:01.97#ibcon#end of sib2, iclass 3, count 0 2006.281.07:42:01.97#ibcon#*after write, iclass 3, count 0 2006.281.07:42:01.97#ibcon#*before return 0, iclass 3, count 0 2006.281.07:42:01.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:42:01.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:42:01.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:42:01.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:42:01.97$vc4f8/va=8,6 2006.281.07:42:01.97#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.07:42:01.97#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.07:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:01.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:42:02.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:42:02.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:42:02.03#ibcon#enter wrdev, iclass 5, count 2 2006.281.07:42:02.03#ibcon#first serial, iclass 5, count 2 2006.281.07:42:02.03#ibcon#enter sib2, iclass 5, count 2 2006.281.07:42:02.03#ibcon#flushed, iclass 5, count 2 2006.281.07:42:02.03#ibcon#about to write, iclass 5, count 2 2006.281.07:42:02.03#ibcon#wrote, iclass 5, count 2 2006.281.07:42:02.03#ibcon#about to read 3, iclass 5, count 2 2006.281.07:42:02.04#ibcon#read 3, iclass 5, count 2 2006.281.07:42:02.04#ibcon#about to read 4, iclass 5, count 2 2006.281.07:42:02.04#ibcon#read 4, iclass 5, count 2 2006.281.07:42:02.04#ibcon#about to read 5, iclass 5, count 2 2006.281.07:42:02.04#ibcon#read 5, iclass 5, count 2 2006.281.07:42:02.04#ibcon#about to read 6, iclass 5, count 2 2006.281.07:42:02.04#ibcon#read 6, iclass 5, count 2 2006.281.07:42:02.04#ibcon#end of sib2, iclass 5, count 2 2006.281.07:42:02.04#ibcon#*mode == 0, iclass 5, count 2 2006.281.07:42:02.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.07:42:02.04#ibcon#[25=AT08-06\r\n] 2006.281.07:42:02.04#ibcon#*before write, iclass 5, count 2 2006.281.07:42:02.04#ibcon#enter sib2, iclass 5, count 2 2006.281.07:42:02.04#ibcon#flushed, iclass 5, count 2 2006.281.07:42:02.04#ibcon#about to write, iclass 5, count 2 2006.281.07:42:02.04#ibcon#wrote, iclass 5, count 2 2006.281.07:42:02.04#ibcon#about to read 3, iclass 5, count 2 2006.281.07:42:02.07#ibcon#read 3, iclass 5, count 2 2006.281.07:42:02.07#ibcon#about to read 4, iclass 5, count 2 2006.281.07:42:02.07#ibcon#read 4, iclass 5, count 2 2006.281.07:42:02.07#ibcon#about to read 5, iclass 5, count 2 2006.281.07:42:02.07#ibcon#read 5, iclass 5, count 2 2006.281.07:42:02.07#ibcon#about to read 6, iclass 5, count 2 2006.281.07:42:02.07#ibcon#read 6, iclass 5, count 2 2006.281.07:42:02.07#ibcon#end of sib2, iclass 5, count 2 2006.281.07:42:02.07#ibcon#*after write, iclass 5, count 2 2006.281.07:42:02.07#ibcon#*before return 0, iclass 5, count 2 2006.281.07:42:02.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:42:02.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:42:02.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.07:42:02.07#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:02.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:42:02.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:42:02.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:42:02.19#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:42:02.19#ibcon#first serial, iclass 5, count 0 2006.281.07:42:02.19#ibcon#enter sib2, iclass 5, count 0 2006.281.07:42:02.19#ibcon#flushed, iclass 5, count 0 2006.281.07:42:02.19#ibcon#about to write, iclass 5, count 0 2006.281.07:42:02.19#ibcon#wrote, iclass 5, count 0 2006.281.07:42:02.19#ibcon#about to read 3, iclass 5, count 0 2006.281.07:42:02.21#ibcon#read 3, iclass 5, count 0 2006.281.07:42:02.21#ibcon#about to read 4, iclass 5, count 0 2006.281.07:42:02.21#ibcon#read 4, iclass 5, count 0 2006.281.07:42:02.21#ibcon#about to read 5, iclass 5, count 0 2006.281.07:42:02.21#ibcon#read 5, iclass 5, count 0 2006.281.07:42:02.21#ibcon#about to read 6, iclass 5, count 0 2006.281.07:42:02.21#ibcon#read 6, iclass 5, count 0 2006.281.07:42:02.21#ibcon#end of sib2, iclass 5, count 0 2006.281.07:42:02.21#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:42:02.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:42:02.21#ibcon#[25=USB\r\n] 2006.281.07:42:02.21#ibcon#*before write, iclass 5, count 0 2006.281.07:42:02.21#ibcon#enter sib2, iclass 5, count 0 2006.281.07:42:02.21#ibcon#flushed, iclass 5, count 0 2006.281.07:42:02.21#ibcon#about to write, iclass 5, count 0 2006.281.07:42:02.21#ibcon#wrote, iclass 5, count 0 2006.281.07:42:02.22#ibcon#about to read 3, iclass 5, count 0 2006.281.07:42:02.24#ibcon#read 3, iclass 5, count 0 2006.281.07:42:02.24#ibcon#about to read 4, iclass 5, count 0 2006.281.07:42:02.24#ibcon#read 4, iclass 5, count 0 2006.281.07:42:02.24#ibcon#about to read 5, iclass 5, count 0 2006.281.07:42:02.24#ibcon#read 5, iclass 5, count 0 2006.281.07:42:02.24#ibcon#about to read 6, iclass 5, count 0 2006.281.07:42:02.24#ibcon#read 6, iclass 5, count 0 2006.281.07:42:02.24#ibcon#end of sib2, iclass 5, count 0 2006.281.07:42:02.24#ibcon#*after write, iclass 5, count 0 2006.281.07:42:02.24#ibcon#*before return 0, iclass 5, count 0 2006.281.07:42:02.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:42:02.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:42:02.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:42:02.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:42:02.24$vc4f8/vblo=1,632.99 2006.281.07:42:02.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.07:42:02.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.07:42:02.24#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:02.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:42:02.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:42:02.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:42:02.24#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:42:02.24#ibcon#first serial, iclass 7, count 0 2006.281.07:42:02.24#ibcon#enter sib2, iclass 7, count 0 2006.281.07:42:02.24#ibcon#flushed, iclass 7, count 0 2006.281.07:42:02.24#ibcon#about to write, iclass 7, count 0 2006.281.07:42:02.24#ibcon#wrote, iclass 7, count 0 2006.281.07:42:02.24#ibcon#about to read 3, iclass 7, count 0 2006.281.07:42:02.26#ibcon#read 3, iclass 7, count 0 2006.281.07:42:02.26#ibcon#about to read 4, iclass 7, count 0 2006.281.07:42:02.26#ibcon#read 4, iclass 7, count 0 2006.281.07:42:02.26#ibcon#about to read 5, iclass 7, count 0 2006.281.07:42:02.26#ibcon#read 5, iclass 7, count 0 2006.281.07:42:02.26#ibcon#about to read 6, iclass 7, count 0 2006.281.07:42:02.26#ibcon#read 6, iclass 7, count 0 2006.281.07:42:02.26#ibcon#end of sib2, iclass 7, count 0 2006.281.07:42:02.26#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:42:02.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:42:02.26#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:42:02.26#ibcon#*before write, iclass 7, count 0 2006.281.07:42:02.26#ibcon#enter sib2, iclass 7, count 0 2006.281.07:42:02.26#ibcon#flushed, iclass 7, count 0 2006.281.07:42:02.26#ibcon#about to write, iclass 7, count 0 2006.281.07:42:02.26#ibcon#wrote, iclass 7, count 0 2006.281.07:42:02.26#ibcon#about to read 3, iclass 7, count 0 2006.281.07:42:02.30#ibcon#read 3, iclass 7, count 0 2006.281.07:42:02.30#ibcon#about to read 4, iclass 7, count 0 2006.281.07:42:02.30#ibcon#read 4, iclass 7, count 0 2006.281.07:42:02.30#ibcon#about to read 5, iclass 7, count 0 2006.281.07:42:02.30#ibcon#read 5, iclass 7, count 0 2006.281.07:42:02.30#ibcon#about to read 6, iclass 7, count 0 2006.281.07:42:02.30#ibcon#read 6, iclass 7, count 0 2006.281.07:42:02.30#ibcon#end of sib2, iclass 7, count 0 2006.281.07:42:02.30#ibcon#*after write, iclass 7, count 0 2006.281.07:42:02.30#ibcon#*before return 0, iclass 7, count 0 2006.281.07:42:02.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:42:02.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:42:02.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:42:02.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:42:02.30$vc4f8/vb=1,4 2006.281.07:42:02.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.07:42:02.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.07:42:02.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:02.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:42:02.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:42:02.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:42:02.30#ibcon#enter wrdev, iclass 11, count 2 2006.281.07:42:02.30#ibcon#first serial, iclass 11, count 2 2006.281.07:42:02.30#ibcon#enter sib2, iclass 11, count 2 2006.281.07:42:02.30#ibcon#flushed, iclass 11, count 2 2006.281.07:42:02.30#ibcon#about to write, iclass 11, count 2 2006.281.07:42:02.30#ibcon#wrote, iclass 11, count 2 2006.281.07:42:02.30#ibcon#about to read 3, iclass 11, count 2 2006.281.07:42:02.32#ibcon#read 3, iclass 11, count 2 2006.281.07:42:02.32#ibcon#about to read 4, iclass 11, count 2 2006.281.07:42:02.32#ibcon#read 4, iclass 11, count 2 2006.281.07:42:02.32#ibcon#about to read 5, iclass 11, count 2 2006.281.07:42:02.32#ibcon#read 5, iclass 11, count 2 2006.281.07:42:02.32#ibcon#about to read 6, iclass 11, count 2 2006.281.07:42:02.32#ibcon#read 6, iclass 11, count 2 2006.281.07:42:02.32#ibcon#end of sib2, iclass 11, count 2 2006.281.07:42:02.32#ibcon#*mode == 0, iclass 11, count 2 2006.281.07:42:02.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.07:42:02.36#ibcon#[27=AT01-04\r\n] 2006.281.07:42:02.36#ibcon#*before write, iclass 11, count 2 2006.281.07:42:02.36#ibcon#enter sib2, iclass 11, count 2 2006.281.07:42:02.36#ibcon#flushed, iclass 11, count 2 2006.281.07:42:02.36#ibcon#about to write, iclass 11, count 2 2006.281.07:42:02.36#ibcon#wrote, iclass 11, count 2 2006.281.07:42:02.36#ibcon#about to read 3, iclass 11, count 2 2006.281.07:42:02.38#ibcon#read 3, iclass 11, count 2 2006.281.07:42:02.38#ibcon#about to read 4, iclass 11, count 2 2006.281.07:42:02.38#ibcon#read 4, iclass 11, count 2 2006.281.07:42:02.38#ibcon#about to read 5, iclass 11, count 2 2006.281.07:42:02.38#ibcon#read 5, iclass 11, count 2 2006.281.07:42:02.38#ibcon#about to read 6, iclass 11, count 2 2006.281.07:42:02.38#ibcon#read 6, iclass 11, count 2 2006.281.07:42:02.38#ibcon#end of sib2, iclass 11, count 2 2006.281.07:42:02.38#ibcon#*after write, iclass 11, count 2 2006.281.07:42:02.38#ibcon#*before return 0, iclass 11, count 2 2006.281.07:42:02.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:42:02.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:42:02.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.07:42:02.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:02.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:42:02.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:42:02.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:42:02.50#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:42:02.50#ibcon#first serial, iclass 11, count 0 2006.281.07:42:02.50#ibcon#enter sib2, iclass 11, count 0 2006.281.07:42:02.50#ibcon#flushed, iclass 11, count 0 2006.281.07:42:02.50#ibcon#about to write, iclass 11, count 0 2006.281.07:42:02.50#ibcon#wrote, iclass 11, count 0 2006.281.07:42:02.50#ibcon#about to read 3, iclass 11, count 0 2006.281.07:42:02.52#ibcon#read 3, iclass 11, count 0 2006.281.07:42:02.52#ibcon#about to read 4, iclass 11, count 0 2006.281.07:42:02.52#ibcon#read 4, iclass 11, count 0 2006.281.07:42:02.52#ibcon#about to read 5, iclass 11, count 0 2006.281.07:42:02.52#ibcon#read 5, iclass 11, count 0 2006.281.07:42:02.52#ibcon#about to read 6, iclass 11, count 0 2006.281.07:42:02.52#ibcon#read 6, iclass 11, count 0 2006.281.07:42:02.52#ibcon#end of sib2, iclass 11, count 0 2006.281.07:42:02.52#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:42:02.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:42:02.53#ibcon#[27=USB\r\n] 2006.281.07:42:02.53#ibcon#*before write, iclass 11, count 0 2006.281.07:42:02.53#ibcon#enter sib2, iclass 11, count 0 2006.281.07:42:02.53#ibcon#flushed, iclass 11, count 0 2006.281.07:42:02.53#ibcon#about to write, iclass 11, count 0 2006.281.07:42:02.53#ibcon#wrote, iclass 11, count 0 2006.281.07:42:02.53#ibcon#about to read 3, iclass 11, count 0 2006.281.07:42:02.55#ibcon#read 3, iclass 11, count 0 2006.281.07:42:02.55#ibcon#about to read 4, iclass 11, count 0 2006.281.07:42:02.55#ibcon#read 4, iclass 11, count 0 2006.281.07:42:02.55#ibcon#about to read 5, iclass 11, count 0 2006.281.07:42:02.55#ibcon#read 5, iclass 11, count 0 2006.281.07:42:02.55#ibcon#about to read 6, iclass 11, count 0 2006.281.07:42:02.55#ibcon#read 6, iclass 11, count 0 2006.281.07:42:02.55#ibcon#end of sib2, iclass 11, count 0 2006.281.07:42:02.55#ibcon#*after write, iclass 11, count 0 2006.281.07:42:02.55#ibcon#*before return 0, iclass 11, count 0 2006.281.07:42:02.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:42:02.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:42:02.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:42:02.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:42:02.55$vc4f8/vblo=2,640.99 2006.281.07:42:02.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.07:42:02.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.07:42:02.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:02.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:42:02.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:42:02.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:42:02.55#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:42:02.55#ibcon#first serial, iclass 13, count 0 2006.281.07:42:02.55#ibcon#enter sib2, iclass 13, count 0 2006.281.07:42:02.55#ibcon#flushed, iclass 13, count 0 2006.281.07:42:02.55#ibcon#about to write, iclass 13, count 0 2006.281.07:42:02.55#ibcon#wrote, iclass 13, count 0 2006.281.07:42:02.55#ibcon#about to read 3, iclass 13, count 0 2006.281.07:42:02.57#ibcon#read 3, iclass 13, count 0 2006.281.07:42:02.57#ibcon#about to read 4, iclass 13, count 0 2006.281.07:42:02.57#ibcon#read 4, iclass 13, count 0 2006.281.07:42:02.57#ibcon#about to read 5, iclass 13, count 0 2006.281.07:42:02.57#ibcon#read 5, iclass 13, count 0 2006.281.07:42:02.57#ibcon#about to read 6, iclass 13, count 0 2006.281.07:42:02.57#ibcon#read 6, iclass 13, count 0 2006.281.07:42:02.57#ibcon#end of sib2, iclass 13, count 0 2006.281.07:42:02.57#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:42:02.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:42:02.57#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:42:02.57#ibcon#*before write, iclass 13, count 0 2006.281.07:42:02.57#ibcon#enter sib2, iclass 13, count 0 2006.281.07:42:02.57#ibcon#flushed, iclass 13, count 0 2006.281.07:42:02.57#ibcon#about to write, iclass 13, count 0 2006.281.07:42:02.57#ibcon#wrote, iclass 13, count 0 2006.281.07:42:02.57#ibcon#about to read 3, iclass 13, count 0 2006.281.07:42:02.61#ibcon#read 3, iclass 13, count 0 2006.281.07:42:02.61#ibcon#about to read 4, iclass 13, count 0 2006.281.07:42:02.61#ibcon#read 4, iclass 13, count 0 2006.281.07:42:02.61#ibcon#about to read 5, iclass 13, count 0 2006.281.07:42:02.61#ibcon#read 5, iclass 13, count 0 2006.281.07:42:02.61#ibcon#about to read 6, iclass 13, count 0 2006.281.07:42:02.61#ibcon#read 6, iclass 13, count 0 2006.281.07:42:02.61#ibcon#end of sib2, iclass 13, count 0 2006.281.07:42:02.61#ibcon#*after write, iclass 13, count 0 2006.281.07:42:02.61#ibcon#*before return 0, iclass 13, count 0 2006.281.07:42:02.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:42:02.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:42:02.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:42:02.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:42:02.61$vc4f8/vb=2,5 2006.281.07:42:02.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.07:42:02.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.07:42:02.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:02.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:02.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:02.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:02.67#ibcon#enter wrdev, iclass 15, count 2 2006.281.07:42:02.67#ibcon#first serial, iclass 15, count 2 2006.281.07:42:02.67#ibcon#enter sib2, iclass 15, count 2 2006.281.07:42:02.67#ibcon#flushed, iclass 15, count 2 2006.281.07:42:02.67#ibcon#about to write, iclass 15, count 2 2006.281.07:42:02.67#ibcon#wrote, iclass 15, count 2 2006.281.07:42:02.67#ibcon#about to read 3, iclass 15, count 2 2006.281.07:42:02.70#ibcon#read 3, iclass 15, count 2 2006.281.07:42:02.70#ibcon#about to read 4, iclass 15, count 2 2006.281.07:42:02.70#ibcon#read 4, iclass 15, count 2 2006.281.07:42:02.70#ibcon#about to read 5, iclass 15, count 2 2006.281.07:42:02.70#ibcon#read 5, iclass 15, count 2 2006.281.07:42:02.70#ibcon#about to read 6, iclass 15, count 2 2006.281.07:42:02.70#ibcon#read 6, iclass 15, count 2 2006.281.07:42:02.70#ibcon#end of sib2, iclass 15, count 2 2006.281.07:42:02.70#ibcon#*mode == 0, iclass 15, count 2 2006.281.07:42:02.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.07:42:02.70#ibcon#[27=AT02-05\r\n] 2006.281.07:42:02.70#ibcon#*before write, iclass 15, count 2 2006.281.07:42:02.70#ibcon#enter sib2, iclass 15, count 2 2006.281.07:42:02.70#ibcon#flushed, iclass 15, count 2 2006.281.07:42:02.70#ibcon#about to write, iclass 15, count 2 2006.281.07:42:02.70#ibcon#wrote, iclass 15, count 2 2006.281.07:42:02.70#ibcon#about to read 3, iclass 15, count 2 2006.281.07:42:02.73#ibcon#read 3, iclass 15, count 2 2006.281.07:42:02.73#ibcon#about to read 4, iclass 15, count 2 2006.281.07:42:02.73#ibcon#read 4, iclass 15, count 2 2006.281.07:42:02.73#ibcon#about to read 5, iclass 15, count 2 2006.281.07:42:02.73#ibcon#read 5, iclass 15, count 2 2006.281.07:42:02.73#ibcon#about to read 6, iclass 15, count 2 2006.281.07:42:02.73#ibcon#read 6, iclass 15, count 2 2006.281.07:42:02.73#ibcon#end of sib2, iclass 15, count 2 2006.281.07:42:02.73#ibcon#*after write, iclass 15, count 2 2006.281.07:42:02.73#ibcon#*before return 0, iclass 15, count 2 2006.281.07:42:02.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:02.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:42:02.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.07:42:02.73#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:02.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:02.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:02.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:02.85#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:42:02.85#ibcon#first serial, iclass 15, count 0 2006.281.07:42:02.85#ibcon#enter sib2, iclass 15, count 0 2006.281.07:42:02.85#ibcon#flushed, iclass 15, count 0 2006.281.07:42:02.85#ibcon#about to write, iclass 15, count 0 2006.281.07:42:02.85#ibcon#wrote, iclass 15, count 0 2006.281.07:42:02.85#ibcon#about to read 3, iclass 15, count 0 2006.281.07:42:02.87#ibcon#read 3, iclass 15, count 0 2006.281.07:42:02.87#ibcon#about to read 4, iclass 15, count 0 2006.281.07:42:02.87#ibcon#read 4, iclass 15, count 0 2006.281.07:42:02.87#ibcon#about to read 5, iclass 15, count 0 2006.281.07:42:02.87#ibcon#read 5, iclass 15, count 0 2006.281.07:42:02.87#ibcon#about to read 6, iclass 15, count 0 2006.281.07:42:02.87#ibcon#read 6, iclass 15, count 0 2006.281.07:42:02.87#ibcon#end of sib2, iclass 15, count 0 2006.281.07:42:02.87#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:42:02.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:42:02.87#ibcon#[27=USB\r\n] 2006.281.07:42:02.87#ibcon#*before write, iclass 15, count 0 2006.281.07:42:02.87#ibcon#enter sib2, iclass 15, count 0 2006.281.07:42:02.87#ibcon#flushed, iclass 15, count 0 2006.281.07:42:02.87#ibcon#about to write, iclass 15, count 0 2006.281.07:42:02.87#ibcon#wrote, iclass 15, count 0 2006.281.07:42:02.87#ibcon#about to read 3, iclass 15, count 0 2006.281.07:42:02.90#ibcon#read 3, iclass 15, count 0 2006.281.07:42:02.90#ibcon#about to read 4, iclass 15, count 0 2006.281.07:42:02.90#ibcon#read 4, iclass 15, count 0 2006.281.07:42:02.90#ibcon#about to read 5, iclass 15, count 0 2006.281.07:42:02.90#ibcon#read 5, iclass 15, count 0 2006.281.07:42:02.90#ibcon#about to read 6, iclass 15, count 0 2006.281.07:42:02.90#ibcon#read 6, iclass 15, count 0 2006.281.07:42:02.90#ibcon#end of sib2, iclass 15, count 0 2006.281.07:42:02.90#ibcon#*after write, iclass 15, count 0 2006.281.07:42:02.90#ibcon#*before return 0, iclass 15, count 0 2006.281.07:42:02.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:02.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:42:02.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:42:02.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:42:02.90$vc4f8/vblo=3,656.99 2006.281.07:42:02.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:42:02.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:42:02.90#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:02.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:02.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:02.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:02.90#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:42:02.90#ibcon#first serial, iclass 17, count 0 2006.281.07:42:02.90#ibcon#enter sib2, iclass 17, count 0 2006.281.07:42:02.90#ibcon#flushed, iclass 17, count 0 2006.281.07:42:02.90#ibcon#about to write, iclass 17, count 0 2006.281.07:42:02.90#ibcon#wrote, iclass 17, count 0 2006.281.07:42:02.90#ibcon#about to read 3, iclass 17, count 0 2006.281.07:42:02.92#ibcon#read 3, iclass 17, count 0 2006.281.07:42:02.92#ibcon#about to read 4, iclass 17, count 0 2006.281.07:42:02.92#ibcon#read 4, iclass 17, count 0 2006.281.07:42:02.92#ibcon#about to read 5, iclass 17, count 0 2006.281.07:42:02.92#ibcon#read 5, iclass 17, count 0 2006.281.07:42:02.92#ibcon#about to read 6, iclass 17, count 0 2006.281.07:42:02.92#ibcon#read 6, iclass 17, count 0 2006.281.07:42:02.92#ibcon#end of sib2, iclass 17, count 0 2006.281.07:42:02.92#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:42:02.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:42:02.92#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:42:02.92#ibcon#*before write, iclass 17, count 0 2006.281.07:42:02.92#ibcon#enter sib2, iclass 17, count 0 2006.281.07:42:02.92#ibcon#flushed, iclass 17, count 0 2006.281.07:42:02.92#ibcon#about to write, iclass 17, count 0 2006.281.07:42:02.92#ibcon#wrote, iclass 17, count 0 2006.281.07:42:02.92#ibcon#about to read 3, iclass 17, count 0 2006.281.07:42:02.97#ibcon#read 3, iclass 17, count 0 2006.281.07:42:02.97#ibcon#about to read 4, iclass 17, count 0 2006.281.07:42:02.97#ibcon#read 4, iclass 17, count 0 2006.281.07:42:02.97#ibcon#about to read 5, iclass 17, count 0 2006.281.07:42:02.97#ibcon#read 5, iclass 17, count 0 2006.281.07:42:02.97#ibcon#about to read 6, iclass 17, count 0 2006.281.07:42:02.97#ibcon#read 6, iclass 17, count 0 2006.281.07:42:02.97#ibcon#end of sib2, iclass 17, count 0 2006.281.07:42:02.97#ibcon#*after write, iclass 17, count 0 2006.281.07:42:02.97#ibcon#*before return 0, iclass 17, count 0 2006.281.07:42:02.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:02.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:42:02.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:42:02.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:42:02.97$vc4f8/vb=3,4 2006.281.07:42:02.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.07:42:02.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.07:42:02.98#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:02.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:03.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:03.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:03.01#ibcon#enter wrdev, iclass 19, count 2 2006.281.07:42:03.01#ibcon#first serial, iclass 19, count 2 2006.281.07:42:03.01#ibcon#enter sib2, iclass 19, count 2 2006.281.07:42:03.01#ibcon#flushed, iclass 19, count 2 2006.281.07:42:03.01#ibcon#about to write, iclass 19, count 2 2006.281.07:42:03.01#ibcon#wrote, iclass 19, count 2 2006.281.07:42:03.01#ibcon#about to read 3, iclass 19, count 2 2006.281.07:42:03.04#ibcon#read 3, iclass 19, count 2 2006.281.07:42:03.04#ibcon#about to read 4, iclass 19, count 2 2006.281.07:42:03.04#ibcon#read 4, iclass 19, count 2 2006.281.07:42:03.04#ibcon#about to read 5, iclass 19, count 2 2006.281.07:42:03.04#ibcon#read 5, iclass 19, count 2 2006.281.07:42:03.04#ibcon#about to read 6, iclass 19, count 2 2006.281.07:42:03.04#ibcon#read 6, iclass 19, count 2 2006.281.07:42:03.04#ibcon#end of sib2, iclass 19, count 2 2006.281.07:42:03.04#ibcon#*mode == 0, iclass 19, count 2 2006.281.07:42:03.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.07:42:03.04#ibcon#[27=AT03-04\r\n] 2006.281.07:42:03.04#ibcon#*before write, iclass 19, count 2 2006.281.07:42:03.04#ibcon#enter sib2, iclass 19, count 2 2006.281.07:42:03.04#ibcon#flushed, iclass 19, count 2 2006.281.07:42:03.04#ibcon#about to write, iclass 19, count 2 2006.281.07:42:03.04#ibcon#wrote, iclass 19, count 2 2006.281.07:42:03.04#ibcon#about to read 3, iclass 19, count 2 2006.281.07:42:03.07#ibcon#read 3, iclass 19, count 2 2006.281.07:42:03.07#ibcon#about to read 4, iclass 19, count 2 2006.281.07:42:03.07#ibcon#read 4, iclass 19, count 2 2006.281.07:42:03.07#ibcon#about to read 5, iclass 19, count 2 2006.281.07:42:03.07#ibcon#read 5, iclass 19, count 2 2006.281.07:42:03.07#ibcon#about to read 6, iclass 19, count 2 2006.281.07:42:03.07#ibcon#read 6, iclass 19, count 2 2006.281.07:42:03.07#ibcon#end of sib2, iclass 19, count 2 2006.281.07:42:03.07#ibcon#*after write, iclass 19, count 2 2006.281.07:42:03.07#ibcon#*before return 0, iclass 19, count 2 2006.281.07:42:03.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:03.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:42:03.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.07:42:03.07#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:03.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:03.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:03.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:03.19#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:42:03.19#ibcon#first serial, iclass 19, count 0 2006.281.07:42:03.19#ibcon#enter sib2, iclass 19, count 0 2006.281.07:42:03.19#ibcon#flushed, iclass 19, count 0 2006.281.07:42:03.19#ibcon#about to write, iclass 19, count 0 2006.281.07:42:03.19#ibcon#wrote, iclass 19, count 0 2006.281.07:42:03.19#ibcon#about to read 3, iclass 19, count 0 2006.281.07:42:03.21#ibcon#read 3, iclass 19, count 0 2006.281.07:42:03.21#ibcon#about to read 4, iclass 19, count 0 2006.281.07:42:03.21#ibcon#read 4, iclass 19, count 0 2006.281.07:42:03.21#ibcon#about to read 5, iclass 19, count 0 2006.281.07:42:03.21#ibcon#read 5, iclass 19, count 0 2006.281.07:42:03.21#ibcon#about to read 6, iclass 19, count 0 2006.281.07:42:03.21#ibcon#read 6, iclass 19, count 0 2006.281.07:42:03.21#ibcon#end of sib2, iclass 19, count 0 2006.281.07:42:03.21#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:42:03.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:42:03.21#ibcon#[27=USB\r\n] 2006.281.07:42:03.21#ibcon#*before write, iclass 19, count 0 2006.281.07:42:03.21#ibcon#enter sib2, iclass 19, count 0 2006.281.07:42:03.21#ibcon#flushed, iclass 19, count 0 2006.281.07:42:03.21#ibcon#about to write, iclass 19, count 0 2006.281.07:42:03.21#ibcon#wrote, iclass 19, count 0 2006.281.07:42:03.21#ibcon#about to read 3, iclass 19, count 0 2006.281.07:42:03.24#ibcon#read 3, iclass 19, count 0 2006.281.07:42:03.24#ibcon#about to read 4, iclass 19, count 0 2006.281.07:42:03.24#ibcon#read 4, iclass 19, count 0 2006.281.07:42:03.24#ibcon#about to read 5, iclass 19, count 0 2006.281.07:42:03.24#ibcon#read 5, iclass 19, count 0 2006.281.07:42:03.24#ibcon#about to read 6, iclass 19, count 0 2006.281.07:42:03.24#ibcon#read 6, iclass 19, count 0 2006.281.07:42:03.24#ibcon#end of sib2, iclass 19, count 0 2006.281.07:42:03.24#ibcon#*after write, iclass 19, count 0 2006.281.07:42:03.24#ibcon#*before return 0, iclass 19, count 0 2006.281.07:42:03.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:03.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:42:03.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:42:03.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:42:03.24$vc4f8/vblo=4,712.99 2006.281.07:42:03.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.07:42:03.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.07:42:03.24#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:03.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:42:03.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:42:03.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:42:03.24#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:42:03.24#ibcon#first serial, iclass 21, count 0 2006.281.07:42:03.24#ibcon#enter sib2, iclass 21, count 0 2006.281.07:42:03.24#ibcon#flushed, iclass 21, count 0 2006.281.07:42:03.24#ibcon#about to write, iclass 21, count 0 2006.281.07:42:03.24#ibcon#wrote, iclass 21, count 0 2006.281.07:42:03.24#ibcon#about to read 3, iclass 21, count 0 2006.281.07:42:03.26#ibcon#read 3, iclass 21, count 0 2006.281.07:42:03.27#ibcon#about to read 4, iclass 21, count 0 2006.281.07:42:03.27#ibcon#read 4, iclass 21, count 0 2006.281.07:42:03.27#ibcon#about to read 5, iclass 21, count 0 2006.281.07:42:03.27#ibcon#read 5, iclass 21, count 0 2006.281.07:42:03.27#ibcon#about to read 6, iclass 21, count 0 2006.281.07:42:03.27#ibcon#read 6, iclass 21, count 0 2006.281.07:42:03.27#ibcon#end of sib2, iclass 21, count 0 2006.281.07:42:03.27#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:42:03.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:42:03.27#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:42:03.27#ibcon#*before write, iclass 21, count 0 2006.281.07:42:03.27#ibcon#enter sib2, iclass 21, count 0 2006.281.07:42:03.27#ibcon#flushed, iclass 21, count 0 2006.281.07:42:03.27#ibcon#about to write, iclass 21, count 0 2006.281.07:42:03.27#ibcon#wrote, iclass 21, count 0 2006.281.07:42:03.27#ibcon#about to read 3, iclass 21, count 0 2006.281.07:42:03.31#ibcon#read 3, iclass 21, count 0 2006.281.07:42:03.31#ibcon#about to read 4, iclass 21, count 0 2006.281.07:42:03.31#ibcon#read 4, iclass 21, count 0 2006.281.07:42:03.31#ibcon#about to read 5, iclass 21, count 0 2006.281.07:42:03.31#ibcon#read 5, iclass 21, count 0 2006.281.07:42:03.31#ibcon#about to read 6, iclass 21, count 0 2006.281.07:42:03.31#ibcon#read 6, iclass 21, count 0 2006.281.07:42:03.31#ibcon#end of sib2, iclass 21, count 0 2006.281.07:42:03.31#ibcon#*after write, iclass 21, count 0 2006.281.07:42:03.31#ibcon#*before return 0, iclass 21, count 0 2006.281.07:42:03.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:42:03.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:42:03.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:42:03.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:42:03.31$vc4f8/vb=4,4 2006.281.07:42:03.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.07:42:03.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.07:42:03.31#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:03.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:42:03.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:42:03.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:42:03.36#ibcon#enter wrdev, iclass 23, count 2 2006.281.07:42:03.36#ibcon#first serial, iclass 23, count 2 2006.281.07:42:03.36#ibcon#enter sib2, iclass 23, count 2 2006.281.07:42:03.36#ibcon#flushed, iclass 23, count 2 2006.281.07:42:03.36#ibcon#about to write, iclass 23, count 2 2006.281.07:42:03.36#ibcon#wrote, iclass 23, count 2 2006.281.07:42:03.36#ibcon#about to read 3, iclass 23, count 2 2006.281.07:42:03.38#ibcon#read 3, iclass 23, count 2 2006.281.07:42:03.38#ibcon#about to read 4, iclass 23, count 2 2006.281.07:42:03.38#ibcon#read 4, iclass 23, count 2 2006.281.07:42:03.38#ibcon#about to read 5, iclass 23, count 2 2006.281.07:42:03.38#ibcon#read 5, iclass 23, count 2 2006.281.07:42:03.38#ibcon#about to read 6, iclass 23, count 2 2006.281.07:42:03.38#ibcon#read 6, iclass 23, count 2 2006.281.07:42:03.38#ibcon#end of sib2, iclass 23, count 2 2006.281.07:42:03.38#ibcon#*mode == 0, iclass 23, count 2 2006.281.07:42:03.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.07:42:03.38#ibcon#[27=AT04-04\r\n] 2006.281.07:42:03.38#ibcon#*before write, iclass 23, count 2 2006.281.07:42:03.38#ibcon#enter sib2, iclass 23, count 2 2006.281.07:42:03.38#ibcon#flushed, iclass 23, count 2 2006.281.07:42:03.38#ibcon#about to write, iclass 23, count 2 2006.281.07:42:03.38#ibcon#wrote, iclass 23, count 2 2006.281.07:42:03.38#ibcon#about to read 3, iclass 23, count 2 2006.281.07:42:03.41#ibcon#read 3, iclass 23, count 2 2006.281.07:42:03.41#ibcon#about to read 4, iclass 23, count 2 2006.281.07:42:03.41#ibcon#read 4, iclass 23, count 2 2006.281.07:42:03.41#ibcon#about to read 5, iclass 23, count 2 2006.281.07:42:03.41#ibcon#read 5, iclass 23, count 2 2006.281.07:42:03.41#ibcon#about to read 6, iclass 23, count 2 2006.281.07:42:03.41#ibcon#read 6, iclass 23, count 2 2006.281.07:42:03.41#ibcon#end of sib2, iclass 23, count 2 2006.281.07:42:03.41#ibcon#*after write, iclass 23, count 2 2006.281.07:42:03.41#ibcon#*before return 0, iclass 23, count 2 2006.281.07:42:03.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:42:03.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:42:03.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.07:42:03.41#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:03.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:42:03.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:42:03.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:42:03.54#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:42:03.54#ibcon#first serial, iclass 23, count 0 2006.281.07:42:03.54#ibcon#enter sib2, iclass 23, count 0 2006.281.07:42:03.54#ibcon#flushed, iclass 23, count 0 2006.281.07:42:03.54#ibcon#about to write, iclass 23, count 0 2006.281.07:42:03.54#ibcon#wrote, iclass 23, count 0 2006.281.07:42:03.54#ibcon#about to read 3, iclass 23, count 0 2006.281.07:42:03.55#ibcon#read 3, iclass 23, count 0 2006.281.07:42:03.55#ibcon#about to read 4, iclass 23, count 0 2006.281.07:42:03.55#ibcon#read 4, iclass 23, count 0 2006.281.07:42:03.55#ibcon#about to read 5, iclass 23, count 0 2006.281.07:42:03.55#ibcon#read 5, iclass 23, count 0 2006.281.07:42:03.55#ibcon#about to read 6, iclass 23, count 0 2006.281.07:42:03.55#ibcon#read 6, iclass 23, count 0 2006.281.07:42:03.55#ibcon#end of sib2, iclass 23, count 0 2006.281.07:42:03.55#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:42:03.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:42:03.55#ibcon#[27=USB\r\n] 2006.281.07:42:03.55#ibcon#*before write, iclass 23, count 0 2006.281.07:42:03.55#ibcon#enter sib2, iclass 23, count 0 2006.281.07:42:03.55#ibcon#flushed, iclass 23, count 0 2006.281.07:42:03.55#ibcon#about to write, iclass 23, count 0 2006.281.07:42:03.55#ibcon#wrote, iclass 23, count 0 2006.281.07:42:03.55#ibcon#about to read 3, iclass 23, count 0 2006.281.07:42:03.58#ibcon#read 3, iclass 23, count 0 2006.281.07:42:03.58#ibcon#about to read 4, iclass 23, count 0 2006.281.07:42:03.58#ibcon#read 4, iclass 23, count 0 2006.281.07:42:03.58#ibcon#about to read 5, iclass 23, count 0 2006.281.07:42:03.58#ibcon#read 5, iclass 23, count 0 2006.281.07:42:03.58#ibcon#about to read 6, iclass 23, count 0 2006.281.07:42:03.58#ibcon#read 6, iclass 23, count 0 2006.281.07:42:03.58#ibcon#end of sib2, iclass 23, count 0 2006.281.07:42:03.58#ibcon#*after write, iclass 23, count 0 2006.281.07:42:03.58#ibcon#*before return 0, iclass 23, count 0 2006.281.07:42:03.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:42:03.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:42:03.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:42:03.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:42:03.58$vc4f8/vblo=5,744.99 2006.281.07:42:03.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.07:42:03.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.07:42:03.58#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:03.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:42:03.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:42:03.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:42:03.58#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:42:03.58#ibcon#first serial, iclass 25, count 0 2006.281.07:42:03.58#ibcon#enter sib2, iclass 25, count 0 2006.281.07:42:03.58#ibcon#flushed, iclass 25, count 0 2006.281.07:42:03.58#ibcon#about to write, iclass 25, count 0 2006.281.07:42:03.58#ibcon#wrote, iclass 25, count 0 2006.281.07:42:03.58#ibcon#about to read 3, iclass 25, count 0 2006.281.07:42:03.60#ibcon#read 3, iclass 25, count 0 2006.281.07:42:03.60#ibcon#about to read 4, iclass 25, count 0 2006.281.07:42:03.60#ibcon#read 4, iclass 25, count 0 2006.281.07:42:03.60#ibcon#about to read 5, iclass 25, count 0 2006.281.07:42:03.60#ibcon#read 5, iclass 25, count 0 2006.281.07:42:03.60#ibcon#about to read 6, iclass 25, count 0 2006.281.07:42:03.60#ibcon#read 6, iclass 25, count 0 2006.281.07:42:03.60#ibcon#end of sib2, iclass 25, count 0 2006.281.07:42:03.60#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:42:03.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:42:03.60#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:42:03.60#ibcon#*before write, iclass 25, count 0 2006.281.07:42:03.60#ibcon#enter sib2, iclass 25, count 0 2006.281.07:42:03.60#ibcon#flushed, iclass 25, count 0 2006.281.07:42:03.60#ibcon#about to write, iclass 25, count 0 2006.281.07:42:03.60#ibcon#wrote, iclass 25, count 0 2006.281.07:42:03.60#ibcon#about to read 3, iclass 25, count 0 2006.281.07:42:03.65#ibcon#read 3, iclass 25, count 0 2006.281.07:42:03.65#ibcon#about to read 4, iclass 25, count 0 2006.281.07:42:03.65#ibcon#read 4, iclass 25, count 0 2006.281.07:42:03.65#ibcon#about to read 5, iclass 25, count 0 2006.281.07:42:03.65#ibcon#read 5, iclass 25, count 0 2006.281.07:42:03.65#ibcon#about to read 6, iclass 25, count 0 2006.281.07:42:03.65#ibcon#read 6, iclass 25, count 0 2006.281.07:42:03.65#ibcon#end of sib2, iclass 25, count 0 2006.281.07:42:03.65#ibcon#*after write, iclass 25, count 0 2006.281.07:42:03.65#ibcon#*before return 0, iclass 25, count 0 2006.281.07:42:03.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:42:03.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:42:03.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:42:03.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:42:03.65$vc4f8/vb=5,4 2006.281.07:42:03.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.07:42:03.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.07:42:03.65#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:03.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:03.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:03.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:03.69#ibcon#enter wrdev, iclass 27, count 2 2006.281.07:42:03.69#ibcon#first serial, iclass 27, count 2 2006.281.07:42:03.69#ibcon#enter sib2, iclass 27, count 2 2006.281.07:42:03.69#ibcon#flushed, iclass 27, count 2 2006.281.07:42:03.69#ibcon#about to write, iclass 27, count 2 2006.281.07:42:03.69#ibcon#wrote, iclass 27, count 2 2006.281.07:42:03.69#ibcon#about to read 3, iclass 27, count 2 2006.281.07:42:03.72#ibcon#read 3, iclass 27, count 2 2006.281.07:42:03.72#ibcon#about to read 4, iclass 27, count 2 2006.281.07:42:03.72#ibcon#read 4, iclass 27, count 2 2006.281.07:42:03.72#ibcon#about to read 5, iclass 27, count 2 2006.281.07:42:03.72#ibcon#read 5, iclass 27, count 2 2006.281.07:42:03.72#ibcon#about to read 6, iclass 27, count 2 2006.281.07:42:03.72#ibcon#read 6, iclass 27, count 2 2006.281.07:42:03.72#ibcon#end of sib2, iclass 27, count 2 2006.281.07:42:03.72#ibcon#*mode == 0, iclass 27, count 2 2006.281.07:42:03.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.07:42:03.72#ibcon#[27=AT05-04\r\n] 2006.281.07:42:03.72#ibcon#*before write, iclass 27, count 2 2006.281.07:42:03.72#ibcon#enter sib2, iclass 27, count 2 2006.281.07:42:03.72#ibcon#flushed, iclass 27, count 2 2006.281.07:42:03.72#ibcon#about to write, iclass 27, count 2 2006.281.07:42:03.72#ibcon#wrote, iclass 27, count 2 2006.281.07:42:03.72#ibcon#about to read 3, iclass 27, count 2 2006.281.07:42:03.74#ibcon#read 3, iclass 27, count 2 2006.281.07:42:03.74#ibcon#about to read 4, iclass 27, count 2 2006.281.07:42:03.74#ibcon#read 4, iclass 27, count 2 2006.281.07:42:03.74#ibcon#about to read 5, iclass 27, count 2 2006.281.07:42:03.74#ibcon#read 5, iclass 27, count 2 2006.281.07:42:03.74#ibcon#about to read 6, iclass 27, count 2 2006.281.07:42:03.74#ibcon#read 6, iclass 27, count 2 2006.281.07:42:03.74#ibcon#end of sib2, iclass 27, count 2 2006.281.07:42:03.74#ibcon#*after write, iclass 27, count 2 2006.281.07:42:03.74#ibcon#*before return 0, iclass 27, count 2 2006.281.07:42:03.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:03.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:42:03.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.07:42:03.74#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:03.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:03.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:03.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:03.86#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:42:03.86#ibcon#first serial, iclass 27, count 0 2006.281.07:42:03.86#ibcon#enter sib2, iclass 27, count 0 2006.281.07:42:03.86#ibcon#flushed, iclass 27, count 0 2006.281.07:42:03.86#ibcon#about to write, iclass 27, count 0 2006.281.07:42:03.86#ibcon#wrote, iclass 27, count 0 2006.281.07:42:03.86#ibcon#about to read 3, iclass 27, count 0 2006.281.07:42:03.88#ibcon#read 3, iclass 27, count 0 2006.281.07:42:03.88#ibcon#about to read 4, iclass 27, count 0 2006.281.07:42:03.88#ibcon#read 4, iclass 27, count 0 2006.281.07:42:03.88#ibcon#about to read 5, iclass 27, count 0 2006.281.07:42:03.88#ibcon#read 5, iclass 27, count 0 2006.281.07:42:03.88#ibcon#about to read 6, iclass 27, count 0 2006.281.07:42:03.88#ibcon#read 6, iclass 27, count 0 2006.281.07:42:03.88#ibcon#end of sib2, iclass 27, count 0 2006.281.07:42:03.88#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:42:03.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:42:03.88#ibcon#[27=USB\r\n] 2006.281.07:42:03.88#ibcon#*before write, iclass 27, count 0 2006.281.07:42:03.88#ibcon#enter sib2, iclass 27, count 0 2006.281.07:42:03.88#ibcon#flushed, iclass 27, count 0 2006.281.07:42:03.88#ibcon#about to write, iclass 27, count 0 2006.281.07:42:03.88#ibcon#wrote, iclass 27, count 0 2006.281.07:42:03.88#ibcon#about to read 3, iclass 27, count 0 2006.281.07:42:03.91#ibcon#read 3, iclass 27, count 0 2006.281.07:42:03.91#ibcon#about to read 4, iclass 27, count 0 2006.281.07:42:03.91#ibcon#read 4, iclass 27, count 0 2006.281.07:42:03.91#ibcon#about to read 5, iclass 27, count 0 2006.281.07:42:03.91#ibcon#read 5, iclass 27, count 0 2006.281.07:42:03.91#ibcon#about to read 6, iclass 27, count 0 2006.281.07:42:03.91#ibcon#read 6, iclass 27, count 0 2006.281.07:42:03.91#ibcon#end of sib2, iclass 27, count 0 2006.281.07:42:03.91#ibcon#*after write, iclass 27, count 0 2006.281.07:42:03.91#ibcon#*before return 0, iclass 27, count 0 2006.281.07:42:03.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:03.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:42:03.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:42:03.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:42:03.91$vc4f8/vblo=6,752.99 2006.281.07:42:03.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.07:42:03.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.07:42:03.91#ibcon#ireg 17 cls_cnt 0 2006.281.07:42:03.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:03.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:03.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:03.91#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:42:03.91#ibcon#first serial, iclass 29, count 0 2006.281.07:42:03.91#ibcon#enter sib2, iclass 29, count 0 2006.281.07:42:03.91#ibcon#flushed, iclass 29, count 0 2006.281.07:42:03.91#ibcon#about to write, iclass 29, count 0 2006.281.07:42:03.91#ibcon#wrote, iclass 29, count 0 2006.281.07:42:03.91#ibcon#about to read 3, iclass 29, count 0 2006.281.07:42:03.93#ibcon#read 3, iclass 29, count 0 2006.281.07:42:03.93#ibcon#about to read 4, iclass 29, count 0 2006.281.07:42:03.93#ibcon#read 4, iclass 29, count 0 2006.281.07:42:03.93#ibcon#about to read 5, iclass 29, count 0 2006.281.07:42:03.93#ibcon#read 5, iclass 29, count 0 2006.281.07:42:03.93#ibcon#about to read 6, iclass 29, count 0 2006.281.07:42:03.93#ibcon#read 6, iclass 29, count 0 2006.281.07:42:03.93#ibcon#end of sib2, iclass 29, count 0 2006.281.07:42:03.93#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:42:03.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:42:03.95#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:42:03.95#ibcon#*before write, iclass 29, count 0 2006.281.07:42:03.95#ibcon#enter sib2, iclass 29, count 0 2006.281.07:42:03.95#ibcon#flushed, iclass 29, count 0 2006.281.07:42:03.95#ibcon#about to write, iclass 29, count 0 2006.281.07:42:03.95#ibcon#wrote, iclass 29, count 0 2006.281.07:42:03.95#ibcon#about to read 3, iclass 29, count 0 2006.281.07:42:03.99#ibcon#read 3, iclass 29, count 0 2006.281.07:42:03.99#ibcon#about to read 4, iclass 29, count 0 2006.281.07:42:03.99#ibcon#read 4, iclass 29, count 0 2006.281.07:42:03.99#ibcon#about to read 5, iclass 29, count 0 2006.281.07:42:03.99#ibcon#read 5, iclass 29, count 0 2006.281.07:42:03.99#ibcon#about to read 6, iclass 29, count 0 2006.281.07:42:03.99#ibcon#read 6, iclass 29, count 0 2006.281.07:42:03.99#ibcon#end of sib2, iclass 29, count 0 2006.281.07:42:03.99#ibcon#*after write, iclass 29, count 0 2006.281.07:42:03.99#ibcon#*before return 0, iclass 29, count 0 2006.281.07:42:03.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:03.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:42:03.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:42:03.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:42:03.99$vc4f8/vb=6,4 2006.281.07:42:03.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.07:42:03.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.07:42:03.99#ibcon#ireg 11 cls_cnt 2 2006.281.07:42:03.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:04.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:04.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:04.04#ibcon#enter wrdev, iclass 31, count 2 2006.281.07:42:04.04#ibcon#first serial, iclass 31, count 2 2006.281.07:42:04.04#ibcon#enter sib2, iclass 31, count 2 2006.281.07:42:04.04#ibcon#flushed, iclass 31, count 2 2006.281.07:42:04.04#ibcon#about to write, iclass 31, count 2 2006.281.07:42:04.04#ibcon#wrote, iclass 31, count 2 2006.281.07:42:04.04#ibcon#about to read 3, iclass 31, count 2 2006.281.07:42:04.05#ibcon#read 3, iclass 31, count 2 2006.281.07:42:04.05#ibcon#about to read 4, iclass 31, count 2 2006.281.07:42:04.05#ibcon#read 4, iclass 31, count 2 2006.281.07:42:04.05#ibcon#about to read 5, iclass 31, count 2 2006.281.07:42:04.05#ibcon#read 5, iclass 31, count 2 2006.281.07:42:04.05#ibcon#about to read 6, iclass 31, count 2 2006.281.07:42:04.05#ibcon#read 6, iclass 31, count 2 2006.281.07:42:04.05#ibcon#end of sib2, iclass 31, count 2 2006.281.07:42:04.05#ibcon#*mode == 0, iclass 31, count 2 2006.281.07:42:04.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.07:42:04.05#ibcon#[27=AT06-04\r\n] 2006.281.07:42:04.05#ibcon#*before write, iclass 31, count 2 2006.281.07:42:04.05#ibcon#enter sib2, iclass 31, count 2 2006.281.07:42:04.05#ibcon#flushed, iclass 31, count 2 2006.281.07:42:04.05#ibcon#about to write, iclass 31, count 2 2006.281.07:42:04.05#ibcon#wrote, iclass 31, count 2 2006.281.07:42:04.05#ibcon#about to read 3, iclass 31, count 2 2006.281.07:42:04.08#ibcon#read 3, iclass 31, count 2 2006.281.07:42:04.08#ibcon#about to read 4, iclass 31, count 2 2006.281.07:42:04.08#ibcon#read 4, iclass 31, count 2 2006.281.07:42:04.08#ibcon#about to read 5, iclass 31, count 2 2006.281.07:42:04.08#ibcon#read 5, iclass 31, count 2 2006.281.07:42:04.08#ibcon#about to read 6, iclass 31, count 2 2006.281.07:42:04.08#ibcon#read 6, iclass 31, count 2 2006.281.07:42:04.08#ibcon#end of sib2, iclass 31, count 2 2006.281.07:42:04.08#ibcon#*after write, iclass 31, count 2 2006.281.07:42:04.08#ibcon#*before return 0, iclass 31, count 2 2006.281.07:42:04.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:04.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:42:04.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.07:42:04.08#ibcon#ireg 7 cls_cnt 0 2006.281.07:42:04.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:04.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:04.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:04.20#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:42:04.20#ibcon#first serial, iclass 31, count 0 2006.281.07:42:04.20#ibcon#enter sib2, iclass 31, count 0 2006.281.07:42:04.20#ibcon#flushed, iclass 31, count 0 2006.281.07:42:04.20#ibcon#about to write, iclass 31, count 0 2006.281.07:42:04.20#ibcon#wrote, iclass 31, count 0 2006.281.07:42:04.20#ibcon#about to read 3, iclass 31, count 0 2006.281.07:42:04.22#ibcon#read 3, iclass 31, count 0 2006.281.07:42:04.22#ibcon#about to read 4, iclass 31, count 0 2006.281.07:42:04.22#ibcon#read 4, iclass 31, count 0 2006.281.07:42:04.22#ibcon#about to read 5, iclass 31, count 0 2006.281.07:42:04.22#ibcon#read 5, iclass 31, count 0 2006.281.07:42:04.22#ibcon#about to read 6, iclass 31, count 0 2006.281.07:42:04.22#ibcon#read 6, iclass 31, count 0 2006.281.07:42:04.22#ibcon#end of sib2, iclass 31, count 0 2006.281.07:42:04.22#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:42:04.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:42:04.22#ibcon#[27=USB\r\n] 2006.281.07:42:04.22#ibcon#*before write, iclass 31, count 0 2006.281.07:42:04.22#ibcon#enter sib2, iclass 31, count 0 2006.281.07:42:04.22#ibcon#flushed, iclass 31, count 0 2006.281.07:42:04.22#ibcon#about to write, iclass 31, count 0 2006.281.07:42:04.22#ibcon#wrote, iclass 31, count 0 2006.281.07:42:04.22#ibcon#about to read 3, iclass 31, count 0 2006.281.07:42:04.25#ibcon#read 3, iclass 31, count 0 2006.281.07:42:04.25#ibcon#about to read 4, iclass 31, count 0 2006.281.07:42:04.25#ibcon#read 4, iclass 31, count 0 2006.281.07:42:04.25#ibcon#about to read 5, iclass 31, count 0 2006.281.07:42:04.25#ibcon#read 5, iclass 31, count 0 2006.281.07:42:04.25#ibcon#about to read 6, iclass 31, count 0 2006.281.07:42:04.25#ibcon#read 6, iclass 31, count 0 2006.281.07:42:04.25#ibcon#end of sib2, iclass 31, count 0 2006.281.07:42:04.25#ibcon#*after write, iclass 31, count 0 2006.281.07:42:04.25#ibcon#*before return 0, iclass 31, count 0 2006.281.07:42:04.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:04.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:42:04.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:42:04.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:42:04.25$vc4f8/vabw=wide 2006.281.07:42:04.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.07:42:04.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.07:42:04.25#ibcon#ireg 8 cls_cnt 0 2006.281.07:42:04.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:04.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:04.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:04.25#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:42:04.25#ibcon#first serial, iclass 33, count 0 2006.281.07:42:04.25#ibcon#enter sib2, iclass 33, count 0 2006.281.07:42:04.25#ibcon#flushed, iclass 33, count 0 2006.281.07:42:04.25#ibcon#about to write, iclass 33, count 0 2006.281.07:42:04.25#ibcon#wrote, iclass 33, count 0 2006.281.07:42:04.25#ibcon#about to read 3, iclass 33, count 0 2006.281.07:42:04.27#ibcon#read 3, iclass 33, count 0 2006.281.07:42:04.27#ibcon#about to read 4, iclass 33, count 0 2006.281.07:42:04.27#ibcon#read 4, iclass 33, count 0 2006.281.07:42:04.27#ibcon#about to read 5, iclass 33, count 0 2006.281.07:42:04.27#ibcon#read 5, iclass 33, count 0 2006.281.07:42:04.27#ibcon#about to read 6, iclass 33, count 0 2006.281.07:42:04.27#ibcon#read 6, iclass 33, count 0 2006.281.07:42:04.27#ibcon#end of sib2, iclass 33, count 0 2006.281.07:42:04.27#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:42:04.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:42:04.27#ibcon#[25=BW32\r\n] 2006.281.07:42:04.27#ibcon#*before write, iclass 33, count 0 2006.281.07:42:04.27#ibcon#enter sib2, iclass 33, count 0 2006.281.07:42:04.27#ibcon#flushed, iclass 33, count 0 2006.281.07:42:04.27#ibcon#about to write, iclass 33, count 0 2006.281.07:42:04.27#ibcon#wrote, iclass 33, count 0 2006.281.07:42:04.27#ibcon#about to read 3, iclass 33, count 0 2006.281.07:42:04.30#ibcon#read 3, iclass 33, count 0 2006.281.07:42:04.30#ibcon#about to read 4, iclass 33, count 0 2006.281.07:42:04.30#ibcon#read 4, iclass 33, count 0 2006.281.07:42:04.30#ibcon#about to read 5, iclass 33, count 0 2006.281.07:42:04.30#ibcon#read 5, iclass 33, count 0 2006.281.07:42:04.30#ibcon#about to read 6, iclass 33, count 0 2006.281.07:42:04.30#ibcon#read 6, iclass 33, count 0 2006.281.07:42:04.30#ibcon#end of sib2, iclass 33, count 0 2006.281.07:42:04.30#ibcon#*after write, iclass 33, count 0 2006.281.07:42:04.30#ibcon#*before return 0, iclass 33, count 0 2006.281.07:42:04.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:04.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:42:04.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:42:04.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:42:04.30$vc4f8/vbbw=wide 2006.281.07:42:04.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:42:04.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:42:04.31#ibcon#ireg 8 cls_cnt 0 2006.281.07:42:04.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:42:04.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:42:04.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:42:04.36#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:42:04.36#ibcon#first serial, iclass 35, count 0 2006.281.07:42:04.36#ibcon#enter sib2, iclass 35, count 0 2006.281.07:42:04.36#ibcon#flushed, iclass 35, count 0 2006.281.07:42:04.36#ibcon#about to write, iclass 35, count 0 2006.281.07:42:04.36#ibcon#wrote, iclass 35, count 0 2006.281.07:42:04.36#ibcon#about to read 3, iclass 35, count 0 2006.281.07:42:04.38#ibcon#read 3, iclass 35, count 0 2006.281.07:42:04.38#ibcon#about to read 4, iclass 35, count 0 2006.281.07:42:04.38#ibcon#read 4, iclass 35, count 0 2006.281.07:42:04.38#ibcon#about to read 5, iclass 35, count 0 2006.281.07:42:04.38#ibcon#read 5, iclass 35, count 0 2006.281.07:42:04.38#ibcon#about to read 6, iclass 35, count 0 2006.281.07:42:04.38#ibcon#read 6, iclass 35, count 0 2006.281.07:42:04.38#ibcon#end of sib2, iclass 35, count 0 2006.281.07:42:04.38#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:42:04.38#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:42:04.38#ibcon#[27=BW32\r\n] 2006.281.07:42:04.38#ibcon#*before write, iclass 35, count 0 2006.281.07:42:04.38#ibcon#enter sib2, iclass 35, count 0 2006.281.07:42:04.38#ibcon#flushed, iclass 35, count 0 2006.281.07:42:04.38#ibcon#about to write, iclass 35, count 0 2006.281.07:42:04.38#ibcon#wrote, iclass 35, count 0 2006.281.07:42:04.38#ibcon#about to read 3, iclass 35, count 0 2006.281.07:42:04.41#ibcon#read 3, iclass 35, count 0 2006.281.07:42:04.41#ibcon#about to read 4, iclass 35, count 0 2006.281.07:42:04.41#ibcon#read 4, iclass 35, count 0 2006.281.07:42:04.41#ibcon#about to read 5, iclass 35, count 0 2006.281.07:42:04.41#ibcon#read 5, iclass 35, count 0 2006.281.07:42:04.41#ibcon#about to read 6, iclass 35, count 0 2006.281.07:42:04.41#ibcon#read 6, iclass 35, count 0 2006.281.07:42:04.41#ibcon#end of sib2, iclass 35, count 0 2006.281.07:42:04.41#ibcon#*after write, iclass 35, count 0 2006.281.07:42:04.41#ibcon#*before return 0, iclass 35, count 0 2006.281.07:42:04.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:42:04.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:42:04.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:42:04.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:42:04.41$4f8m12a/ifd4f 2006.281.07:42:04.41$ifd4f/lo= 2006.281.07:42:04.41$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:42:04.41$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:42:04.41$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:42:04.41$ifd4f/patch= 2006.281.07:42:04.42$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:42:04.42$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:42:04.42$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:42:04.42$4f8m12a/"form=m,16.000,1:2 2006.281.07:42:04.42$4f8m12a/"tpicd 2006.281.07:42:04.42$4f8m12a/echo=off 2006.281.07:42:04.42$4f8m12a/xlog=off 2006.281.07:42:04.42:!2006.281.07:42:30 2006.281.07:42:15.13#trakl#Source acquired 2006.281.07:42:15.13#flagr#flagr/antenna,acquired 2006.281.07:42:30.01:preob 2006.281.07:42:31.13/onsource/TRACKING 2006.281.07:42:31.13:!2006.281.07:42:40 2006.281.07:42:40.00:data_valid=on 2006.281.07:42:40.00:midob 2006.281.07:42:40.13/onsource/TRACKING 2006.281.07:42:40.13/wx/21.06,1001.2,50 2006.281.07:42:40.30/cable/+6.4845E-03 2006.281.07:42:41.39/va/01,07,usb,yes,41,43 2006.281.07:42:41.39/va/02,06,usb,yes,38,40 2006.281.07:42:41.39/va/03,06,usb,yes,35,35 2006.281.07:42:41.39/va/04,06,usb,yes,39,42 2006.281.07:42:41.39/va/05,07,usb,yes,37,39 2006.281.07:42:41.39/va/06,06,usb,yes,36,36 2006.281.07:42:41.39/va/07,06,usb,yes,36,36 2006.281.07:42:41.39/va/08,06,usb,yes,38,37 2006.281.07:42:41.62/valo/01,532.99,yes,locked 2006.281.07:42:41.62/valo/02,572.99,yes,locked 2006.281.07:42:41.62/valo/03,672.99,yes,locked 2006.281.07:42:41.62/valo/04,832.99,yes,locked 2006.281.07:42:41.62/valo/05,652.99,yes,locked 2006.281.07:42:41.62/valo/06,772.99,yes,locked 2006.281.07:42:41.62/valo/07,832.99,yes,locked 2006.281.07:42:41.62/valo/08,852.99,yes,locked 2006.281.07:42:42.71/vb/01,04,usb,yes,34,32 2006.281.07:42:42.71/vb/02,05,usb,yes,32,33 2006.281.07:42:42.71/vb/03,04,usb,yes,32,36 2006.281.07:42:42.71/vb/04,04,usb,yes,33,33 2006.281.07:42:42.71/vb/05,04,usb,yes,31,35 2006.281.07:42:42.71/vb/06,04,usb,yes,31,35 2006.281.07:42:42.71/vb/07,04,usb,yes,35,35 2006.281.07:42:42.71/vb/08,04,usb,yes,31,35 2006.281.07:42:42.95/vblo/01,632.99,yes,locked 2006.281.07:42:42.95/vblo/02,640.99,yes,locked 2006.281.07:42:42.95/vblo/03,656.99,yes,locked 2006.281.07:42:42.95/vblo/04,712.99,yes,locked 2006.281.07:42:42.95/vblo/05,744.99,yes,locked 2006.281.07:42:42.95/vblo/06,752.99,yes,locked 2006.281.07:42:42.95/vblo/07,734.99,yes,locked 2006.281.07:42:42.95/vblo/08,744.99,yes,locked 2006.281.07:42:43.10/vabw/8 2006.281.07:42:43.25/vbbw/8 2006.281.07:42:43.38/xfe/off,on,12.0 2006.281.07:42:43.75/ifatt/23,28,28,28 2006.281.07:42:44.07/fmout-gps/S +3.10E-07 2006.281.07:42:44.10:!2006.281.07:43:40 2006.281.07:42:56.14#trakl#Off source 2006.281.07:42:56.14?ERROR st -7 Antenna off-source! 2006.281.07:42:56.14#trakl#az 306.775 el 14.868 azerr*cos(el) -0.0047 elerr 0.0244 2006.281.07:42:57.14#flagr#flagr/antenna,off-source 2006.281.07:43:11.14#trakl#Off source 2006.281.07:43:11.14?ERROR st -7 Antenna off-source! 2006.281.07:43:11.14#trakl#az 306.804 el 14.827 azerr*cos(el) -0.0094 elerr -0.0052 2006.281.07:43:13.14#trakl#Source re-acquired 2006.281.07:43:14.14#trakl#Off source 2006.281.07:43:14.14?ERROR st -7 Antenna off-source! 2006.281.07:43:14.14#trakl#az 306.810 el 14.819 azerr*cos(el) -0.0083 elerr -0.0191 2006.281.07:43:21.14#trakl#Source re-acquired 2006.281.07:43:21.14#flagr#flagr/antenna,re-acquired 2006.281.07:43:40.01:data_valid=off 2006.281.07:43:40.02:postob 2006.281.07:43:40.18/cable/+6.4857E-03 2006.281.07:43:40.19/wx/21.04,1001.1,50 2006.281.07:43:41.08/fmout-gps/S +3.08E-07 2006.281.07:43:41.09:scan_name=281-0744,k06281,60 2006.281.07:43:41.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.281.07:43:41.14#flagr#flagr/antenna,new-source 2006.281.07:43:42.14:checkk5 2006.281.07:43:42.72/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:43:43.17/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:43:43.57/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:43:43.99/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:43:44.41/chk_obsdata//k5ts1/T2810742??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:43:44.88/chk_obsdata//k5ts2/T2810742??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:43:45.29/chk_obsdata//k5ts3/T2810742??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:43:45.72/chk_obsdata//k5ts4/T2810742??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:43:46.54/k5log//k5ts1_log_newline 2006.281.07:43:47.35/k5log//k5ts2_log_newline 2006.281.07:43:48.41/k5log//k5ts3_log_newline 2006.281.07:43:49.50/k5log//k5ts4_log_newline 2006.281.07:43:49.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:43:49.52:4f8m12a=1 2006.281.07:43:49.52$4f8m12a/echo=on 2006.281.07:43:49.52$4f8m12a/pcalon 2006.281.07:43:49.52$pcalon/"no phase cal control is implemented here 2006.281.07:43:49.52$4f8m12a/"tpicd=stop 2006.281.07:43:49.52$4f8m12a/vc4f8 2006.281.07:43:49.52$vc4f8/valo=1,532.99 2006.281.07:43:49.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.07:43:49.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.07:43:49.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:49.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:43:49.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:43:49.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:43:49.53#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:43:49.53#ibcon#first serial, iclass 12, count 0 2006.281.07:43:49.53#ibcon#enter sib2, iclass 12, count 0 2006.281.07:43:49.53#ibcon#flushed, iclass 12, count 0 2006.281.07:43:49.53#ibcon#about to write, iclass 12, count 0 2006.281.07:43:49.53#ibcon#wrote, iclass 12, count 0 2006.281.07:43:49.53#ibcon#about to read 3, iclass 12, count 0 2006.281.07:43:49.54#ibcon#read 3, iclass 12, count 0 2006.281.07:43:49.54#ibcon#about to read 4, iclass 12, count 0 2006.281.07:43:49.54#ibcon#read 4, iclass 12, count 0 2006.281.07:43:49.54#ibcon#about to read 5, iclass 12, count 0 2006.281.07:43:49.54#ibcon#read 5, iclass 12, count 0 2006.281.07:43:49.54#ibcon#about to read 6, iclass 12, count 0 2006.281.07:43:49.54#ibcon#read 6, iclass 12, count 0 2006.281.07:43:49.54#ibcon#end of sib2, iclass 12, count 0 2006.281.07:43:49.54#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:43:49.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:43:49.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:43:49.54#ibcon#*before write, iclass 12, count 0 2006.281.07:43:49.54#ibcon#enter sib2, iclass 12, count 0 2006.281.07:43:49.54#ibcon#flushed, iclass 12, count 0 2006.281.07:43:49.54#ibcon#about to write, iclass 12, count 0 2006.281.07:43:49.54#ibcon#wrote, iclass 12, count 0 2006.281.07:43:49.54#ibcon#about to read 3, iclass 12, count 0 2006.281.07:43:49.60#ibcon#read 3, iclass 12, count 0 2006.281.07:43:49.60#ibcon#about to read 4, iclass 12, count 0 2006.281.07:43:49.60#ibcon#read 4, iclass 12, count 0 2006.281.07:43:49.60#ibcon#about to read 5, iclass 12, count 0 2006.281.07:43:49.60#ibcon#read 5, iclass 12, count 0 2006.281.07:43:49.60#ibcon#about to read 6, iclass 12, count 0 2006.281.07:43:49.60#ibcon#read 6, iclass 12, count 0 2006.281.07:43:49.60#ibcon#end of sib2, iclass 12, count 0 2006.281.07:43:49.60#ibcon#*after write, iclass 12, count 0 2006.281.07:43:49.60#ibcon#*before return 0, iclass 12, count 0 2006.281.07:43:49.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:43:49.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:43:49.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:43:49.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:43:49.60$vc4f8/va=1,7 2006.281.07:43:49.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.07:43:49.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.07:43:49.60#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:49.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:43:49.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:43:49.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:43:49.60#ibcon#enter wrdev, iclass 14, count 2 2006.281.07:43:49.60#ibcon#first serial, iclass 14, count 2 2006.281.07:43:49.60#ibcon#enter sib2, iclass 14, count 2 2006.281.07:43:49.60#ibcon#flushed, iclass 14, count 2 2006.281.07:43:49.60#ibcon#about to write, iclass 14, count 2 2006.281.07:43:49.60#ibcon#wrote, iclass 14, count 2 2006.281.07:43:49.60#ibcon#about to read 3, iclass 14, count 2 2006.281.07:43:49.61#ibcon#read 3, iclass 14, count 2 2006.281.07:43:49.62#ibcon#about to read 4, iclass 14, count 2 2006.281.07:43:49.62#ibcon#read 4, iclass 14, count 2 2006.281.07:43:49.62#ibcon#about to read 5, iclass 14, count 2 2006.281.07:43:49.62#ibcon#read 5, iclass 14, count 2 2006.281.07:43:49.62#ibcon#about to read 6, iclass 14, count 2 2006.281.07:43:49.62#ibcon#read 6, iclass 14, count 2 2006.281.07:43:49.62#ibcon#end of sib2, iclass 14, count 2 2006.281.07:43:49.62#ibcon#*mode == 0, iclass 14, count 2 2006.281.07:43:49.62#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.07:43:49.62#ibcon#[25=AT01-07\r\n] 2006.281.07:43:49.62#ibcon#*before write, iclass 14, count 2 2006.281.07:43:49.62#ibcon#enter sib2, iclass 14, count 2 2006.281.07:43:49.62#ibcon#flushed, iclass 14, count 2 2006.281.07:43:49.62#ibcon#about to write, iclass 14, count 2 2006.281.07:43:49.62#ibcon#wrote, iclass 14, count 2 2006.281.07:43:49.62#ibcon#about to read 3, iclass 14, count 2 2006.281.07:43:49.64#ibcon#read 3, iclass 14, count 2 2006.281.07:43:49.64#ibcon#about to read 4, iclass 14, count 2 2006.281.07:43:49.64#ibcon#read 4, iclass 14, count 2 2006.281.07:43:49.64#ibcon#about to read 5, iclass 14, count 2 2006.281.07:43:49.64#ibcon#read 5, iclass 14, count 2 2006.281.07:43:49.64#ibcon#about to read 6, iclass 14, count 2 2006.281.07:43:49.64#ibcon#read 6, iclass 14, count 2 2006.281.07:43:49.64#ibcon#end of sib2, iclass 14, count 2 2006.281.07:43:49.64#ibcon#*after write, iclass 14, count 2 2006.281.07:43:49.64#ibcon#*before return 0, iclass 14, count 2 2006.281.07:43:49.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:43:49.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:43:49.64#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.07:43:49.64#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:49.64#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:43:49.76#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:43:49.76#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:43:49.76#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:43:49.76#ibcon#first serial, iclass 14, count 0 2006.281.07:43:49.76#ibcon#enter sib2, iclass 14, count 0 2006.281.07:43:49.76#ibcon#flushed, iclass 14, count 0 2006.281.07:43:49.76#ibcon#about to write, iclass 14, count 0 2006.281.07:43:49.76#ibcon#wrote, iclass 14, count 0 2006.281.07:43:49.76#ibcon#about to read 3, iclass 14, count 0 2006.281.07:43:49.79#ibcon#read 3, iclass 14, count 0 2006.281.07:43:49.79#ibcon#about to read 4, iclass 14, count 0 2006.281.07:43:49.79#ibcon#read 4, iclass 14, count 0 2006.281.07:43:49.79#ibcon#about to read 5, iclass 14, count 0 2006.281.07:43:49.79#ibcon#read 5, iclass 14, count 0 2006.281.07:43:49.79#ibcon#about to read 6, iclass 14, count 0 2006.281.07:43:49.79#ibcon#read 6, iclass 14, count 0 2006.281.07:43:49.79#ibcon#end of sib2, iclass 14, count 0 2006.281.07:43:49.79#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:43:49.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:43:49.79#ibcon#[25=USB\r\n] 2006.281.07:43:49.79#ibcon#*before write, iclass 14, count 0 2006.281.07:43:49.79#ibcon#enter sib2, iclass 14, count 0 2006.281.07:43:49.79#ibcon#flushed, iclass 14, count 0 2006.281.07:43:49.79#ibcon#about to write, iclass 14, count 0 2006.281.07:43:49.79#ibcon#wrote, iclass 14, count 0 2006.281.07:43:49.79#ibcon#about to read 3, iclass 14, count 0 2006.281.07:43:49.81#ibcon#read 3, iclass 14, count 0 2006.281.07:43:49.81#ibcon#about to read 4, iclass 14, count 0 2006.281.07:43:49.81#ibcon#read 4, iclass 14, count 0 2006.281.07:43:49.81#ibcon#about to read 5, iclass 14, count 0 2006.281.07:43:49.81#ibcon#read 5, iclass 14, count 0 2006.281.07:43:49.81#ibcon#about to read 6, iclass 14, count 0 2006.281.07:43:49.81#ibcon#read 6, iclass 14, count 0 2006.281.07:43:49.81#ibcon#end of sib2, iclass 14, count 0 2006.281.07:43:49.81#ibcon#*after write, iclass 14, count 0 2006.281.07:43:49.81#ibcon#*before return 0, iclass 14, count 0 2006.281.07:43:49.81#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:43:49.81#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:43:49.81#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:43:49.81#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:43:49.81$vc4f8/valo=2,572.99 2006.281.07:43:49.81#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:43:49.81#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:43:49.81#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:49.81#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:49.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:49.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:49.81#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:43:49.81#ibcon#first serial, iclass 16, count 0 2006.281.07:43:49.81#ibcon#enter sib2, iclass 16, count 0 2006.281.07:43:49.81#ibcon#flushed, iclass 16, count 0 2006.281.07:43:49.81#ibcon#about to write, iclass 16, count 0 2006.281.07:43:49.81#ibcon#wrote, iclass 16, count 0 2006.281.07:43:49.81#ibcon#about to read 3, iclass 16, count 0 2006.281.07:43:49.83#ibcon#read 3, iclass 16, count 0 2006.281.07:43:49.83#ibcon#about to read 4, iclass 16, count 0 2006.281.07:43:49.83#ibcon#read 4, iclass 16, count 0 2006.281.07:43:49.83#ibcon#about to read 5, iclass 16, count 0 2006.281.07:43:49.83#ibcon#read 5, iclass 16, count 0 2006.281.07:43:49.83#ibcon#about to read 6, iclass 16, count 0 2006.281.07:43:49.83#ibcon#read 6, iclass 16, count 0 2006.281.07:43:49.83#ibcon#end of sib2, iclass 16, count 0 2006.281.07:43:49.83#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:43:49.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:43:49.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:43:49.83#ibcon#*before write, iclass 16, count 0 2006.281.07:43:49.83#ibcon#enter sib2, iclass 16, count 0 2006.281.07:43:49.83#ibcon#flushed, iclass 16, count 0 2006.281.07:43:49.83#ibcon#about to write, iclass 16, count 0 2006.281.07:43:49.83#ibcon#wrote, iclass 16, count 0 2006.281.07:43:49.83#ibcon#about to read 3, iclass 16, count 0 2006.281.07:43:49.87#ibcon#read 3, iclass 16, count 0 2006.281.07:43:49.87#ibcon#about to read 4, iclass 16, count 0 2006.281.07:43:49.87#ibcon#read 4, iclass 16, count 0 2006.281.07:43:49.87#ibcon#about to read 5, iclass 16, count 0 2006.281.07:43:49.87#ibcon#read 5, iclass 16, count 0 2006.281.07:43:49.87#ibcon#about to read 6, iclass 16, count 0 2006.281.07:43:49.87#ibcon#read 6, iclass 16, count 0 2006.281.07:43:49.87#ibcon#end of sib2, iclass 16, count 0 2006.281.07:43:49.87#ibcon#*after write, iclass 16, count 0 2006.281.07:43:49.87#ibcon#*before return 0, iclass 16, count 0 2006.281.07:43:49.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:49.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:49.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:43:49.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:43:49.87$vc4f8/va=2,6 2006.281.07:43:49.87#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.07:43:49.87#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.07:43:49.87#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:49.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:49.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:49.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:49.93#ibcon#enter wrdev, iclass 18, count 2 2006.281.07:43:49.93#ibcon#first serial, iclass 18, count 2 2006.281.07:43:49.93#ibcon#enter sib2, iclass 18, count 2 2006.281.07:43:49.93#ibcon#flushed, iclass 18, count 2 2006.281.07:43:49.93#ibcon#about to write, iclass 18, count 2 2006.281.07:43:49.93#ibcon#wrote, iclass 18, count 2 2006.281.07:43:49.93#ibcon#about to read 3, iclass 18, count 2 2006.281.07:43:49.95#ibcon#read 3, iclass 18, count 2 2006.281.07:43:49.95#ibcon#about to read 4, iclass 18, count 2 2006.281.07:43:49.95#ibcon#read 4, iclass 18, count 2 2006.281.07:43:49.95#ibcon#about to read 5, iclass 18, count 2 2006.281.07:43:49.95#ibcon#read 5, iclass 18, count 2 2006.281.07:43:49.95#ibcon#about to read 6, iclass 18, count 2 2006.281.07:43:49.95#ibcon#read 6, iclass 18, count 2 2006.281.07:43:49.95#ibcon#end of sib2, iclass 18, count 2 2006.281.07:43:49.95#ibcon#*mode == 0, iclass 18, count 2 2006.281.07:43:49.95#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.07:43:49.95#ibcon#[25=AT02-06\r\n] 2006.281.07:43:49.95#ibcon#*before write, iclass 18, count 2 2006.281.07:43:49.95#ibcon#enter sib2, iclass 18, count 2 2006.281.07:43:49.95#ibcon#flushed, iclass 18, count 2 2006.281.07:43:49.95#ibcon#about to write, iclass 18, count 2 2006.281.07:43:49.95#ibcon#wrote, iclass 18, count 2 2006.281.07:43:49.95#ibcon#about to read 3, iclass 18, count 2 2006.281.07:43:49.98#ibcon#read 3, iclass 18, count 2 2006.281.07:43:49.98#ibcon#about to read 4, iclass 18, count 2 2006.281.07:43:49.98#ibcon#read 4, iclass 18, count 2 2006.281.07:43:49.98#ibcon#about to read 5, iclass 18, count 2 2006.281.07:43:49.98#ibcon#read 5, iclass 18, count 2 2006.281.07:43:49.98#ibcon#about to read 6, iclass 18, count 2 2006.281.07:43:49.98#ibcon#read 6, iclass 18, count 2 2006.281.07:43:49.98#ibcon#end of sib2, iclass 18, count 2 2006.281.07:43:49.98#ibcon#*after write, iclass 18, count 2 2006.281.07:43:49.98#ibcon#*before return 0, iclass 18, count 2 2006.281.07:43:49.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:49.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:49.98#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.07:43:49.98#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:49.98#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:50.10#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:50.10#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:50.10#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:43:50.10#ibcon#first serial, iclass 18, count 0 2006.281.07:43:50.10#ibcon#enter sib2, iclass 18, count 0 2006.281.07:43:50.10#ibcon#flushed, iclass 18, count 0 2006.281.07:43:50.10#ibcon#about to write, iclass 18, count 0 2006.281.07:43:50.10#ibcon#wrote, iclass 18, count 0 2006.281.07:43:50.10#ibcon#about to read 3, iclass 18, count 0 2006.281.07:43:50.12#ibcon#read 3, iclass 18, count 0 2006.281.07:43:50.12#ibcon#about to read 4, iclass 18, count 0 2006.281.07:43:50.12#ibcon#read 4, iclass 18, count 0 2006.281.07:43:50.12#ibcon#about to read 5, iclass 18, count 0 2006.281.07:43:50.12#ibcon#read 5, iclass 18, count 0 2006.281.07:43:50.12#ibcon#about to read 6, iclass 18, count 0 2006.281.07:43:50.12#ibcon#read 6, iclass 18, count 0 2006.281.07:43:50.12#ibcon#end of sib2, iclass 18, count 0 2006.281.07:43:50.12#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:43:50.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:43:50.12#ibcon#[25=USB\r\n] 2006.281.07:43:50.12#ibcon#*before write, iclass 18, count 0 2006.281.07:43:50.12#ibcon#enter sib2, iclass 18, count 0 2006.281.07:43:50.12#ibcon#flushed, iclass 18, count 0 2006.281.07:43:50.12#ibcon#about to write, iclass 18, count 0 2006.281.07:43:50.12#ibcon#wrote, iclass 18, count 0 2006.281.07:43:50.12#ibcon#about to read 3, iclass 18, count 0 2006.281.07:43:50.16#ibcon#read 3, iclass 18, count 0 2006.281.07:43:50.16#ibcon#about to read 4, iclass 18, count 0 2006.281.07:43:50.16#ibcon#read 4, iclass 18, count 0 2006.281.07:43:50.16#ibcon#about to read 5, iclass 18, count 0 2006.281.07:43:50.16#ibcon#read 5, iclass 18, count 0 2006.281.07:43:50.16#ibcon#about to read 6, iclass 18, count 0 2006.281.07:43:50.16#ibcon#read 6, iclass 18, count 0 2006.281.07:43:50.16#ibcon#end of sib2, iclass 18, count 0 2006.281.07:43:50.16#ibcon#*after write, iclass 18, count 0 2006.281.07:43:50.16#ibcon#*before return 0, iclass 18, count 0 2006.281.07:43:50.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:50.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:50.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:43:50.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:43:50.16$vc4f8/valo=3,672.99 2006.281.07:43:50.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:43:50.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:43:50.16#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:50.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:50.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:50.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:50.16#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:43:50.16#ibcon#first serial, iclass 20, count 0 2006.281.07:43:50.16#ibcon#enter sib2, iclass 20, count 0 2006.281.07:43:50.16#ibcon#flushed, iclass 20, count 0 2006.281.07:43:50.16#ibcon#about to write, iclass 20, count 0 2006.281.07:43:50.16#ibcon#wrote, iclass 20, count 0 2006.281.07:43:50.16#ibcon#about to read 3, iclass 20, count 0 2006.281.07:43:50.17#ibcon#read 3, iclass 20, count 0 2006.281.07:43:50.17#ibcon#about to read 4, iclass 20, count 0 2006.281.07:43:50.17#ibcon#read 4, iclass 20, count 0 2006.281.07:43:50.17#ibcon#about to read 5, iclass 20, count 0 2006.281.07:43:50.17#ibcon#read 5, iclass 20, count 0 2006.281.07:43:50.17#ibcon#about to read 6, iclass 20, count 0 2006.281.07:43:50.17#ibcon#read 6, iclass 20, count 0 2006.281.07:43:50.17#ibcon#end of sib2, iclass 20, count 0 2006.281.07:43:50.18#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:43:50.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:43:50.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:43:50.18#ibcon#*before write, iclass 20, count 0 2006.281.07:43:50.18#ibcon#enter sib2, iclass 20, count 0 2006.281.07:43:50.18#ibcon#flushed, iclass 20, count 0 2006.281.07:43:50.18#ibcon#about to write, iclass 20, count 0 2006.281.07:43:50.18#ibcon#wrote, iclass 20, count 0 2006.281.07:43:50.18#ibcon#about to read 3, iclass 20, count 0 2006.281.07:43:50.22#ibcon#read 3, iclass 20, count 0 2006.281.07:43:50.22#ibcon#about to read 4, iclass 20, count 0 2006.281.07:43:50.22#ibcon#read 4, iclass 20, count 0 2006.281.07:43:50.22#ibcon#about to read 5, iclass 20, count 0 2006.281.07:43:50.22#ibcon#read 5, iclass 20, count 0 2006.281.07:43:50.22#ibcon#about to read 6, iclass 20, count 0 2006.281.07:43:50.22#ibcon#read 6, iclass 20, count 0 2006.281.07:43:50.22#ibcon#end of sib2, iclass 20, count 0 2006.281.07:43:50.22#ibcon#*after write, iclass 20, count 0 2006.281.07:43:50.22#ibcon#*before return 0, iclass 20, count 0 2006.281.07:43:50.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:50.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:50.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:43:50.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:43:50.22$vc4f8/va=3,6 2006.281.07:43:50.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:43:50.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:43:50.22#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:50.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:50.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:50.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:50.28#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:43:50.28#ibcon#first serial, iclass 22, count 2 2006.281.07:43:50.28#ibcon#enter sib2, iclass 22, count 2 2006.281.07:43:50.28#ibcon#flushed, iclass 22, count 2 2006.281.07:43:50.28#ibcon#about to write, iclass 22, count 2 2006.281.07:43:50.28#ibcon#wrote, iclass 22, count 2 2006.281.07:43:50.28#ibcon#about to read 3, iclass 22, count 2 2006.281.07:43:50.30#ibcon#read 3, iclass 22, count 2 2006.281.07:43:50.30#ibcon#about to read 4, iclass 22, count 2 2006.281.07:43:50.30#ibcon#read 4, iclass 22, count 2 2006.281.07:43:50.30#ibcon#about to read 5, iclass 22, count 2 2006.281.07:43:50.30#ibcon#read 5, iclass 22, count 2 2006.281.07:43:50.30#ibcon#about to read 6, iclass 22, count 2 2006.281.07:43:50.30#ibcon#read 6, iclass 22, count 2 2006.281.07:43:50.30#ibcon#end of sib2, iclass 22, count 2 2006.281.07:43:50.30#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:43:50.30#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:43:50.30#ibcon#[25=AT03-06\r\n] 2006.281.07:43:50.30#ibcon#*before write, iclass 22, count 2 2006.281.07:43:50.30#ibcon#enter sib2, iclass 22, count 2 2006.281.07:43:50.30#ibcon#flushed, iclass 22, count 2 2006.281.07:43:50.30#ibcon#about to write, iclass 22, count 2 2006.281.07:43:50.30#ibcon#wrote, iclass 22, count 2 2006.281.07:43:50.30#ibcon#about to read 3, iclass 22, count 2 2006.281.07:43:50.33#ibcon#read 3, iclass 22, count 2 2006.281.07:43:50.33#ibcon#about to read 4, iclass 22, count 2 2006.281.07:43:50.33#ibcon#read 4, iclass 22, count 2 2006.281.07:43:50.33#ibcon#about to read 5, iclass 22, count 2 2006.281.07:43:50.33#ibcon#read 5, iclass 22, count 2 2006.281.07:43:50.33#ibcon#about to read 6, iclass 22, count 2 2006.281.07:43:50.33#ibcon#read 6, iclass 22, count 2 2006.281.07:43:50.33#ibcon#end of sib2, iclass 22, count 2 2006.281.07:43:50.33#ibcon#*after write, iclass 22, count 2 2006.281.07:43:50.33#ibcon#*before return 0, iclass 22, count 2 2006.281.07:43:50.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:50.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:50.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:43:50.33#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:50.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:50.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:50.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:50.45#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:43:50.45#ibcon#first serial, iclass 22, count 0 2006.281.07:43:50.45#ibcon#enter sib2, iclass 22, count 0 2006.281.07:43:50.45#ibcon#flushed, iclass 22, count 0 2006.281.07:43:50.45#ibcon#about to write, iclass 22, count 0 2006.281.07:43:50.45#ibcon#wrote, iclass 22, count 0 2006.281.07:43:50.45#ibcon#about to read 3, iclass 22, count 0 2006.281.07:43:50.47#ibcon#read 3, iclass 22, count 0 2006.281.07:43:50.47#ibcon#about to read 4, iclass 22, count 0 2006.281.07:43:50.47#ibcon#read 4, iclass 22, count 0 2006.281.07:43:50.47#ibcon#about to read 5, iclass 22, count 0 2006.281.07:43:50.47#ibcon#read 5, iclass 22, count 0 2006.281.07:43:50.47#ibcon#about to read 6, iclass 22, count 0 2006.281.07:43:50.47#ibcon#read 6, iclass 22, count 0 2006.281.07:43:50.47#ibcon#end of sib2, iclass 22, count 0 2006.281.07:43:50.47#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:43:50.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:43:50.47#ibcon#[25=USB\r\n] 2006.281.07:43:50.47#ibcon#*before write, iclass 22, count 0 2006.281.07:43:50.47#ibcon#enter sib2, iclass 22, count 0 2006.281.07:43:50.47#ibcon#flushed, iclass 22, count 0 2006.281.07:43:50.47#ibcon#about to write, iclass 22, count 0 2006.281.07:43:50.47#ibcon#wrote, iclass 22, count 0 2006.281.07:43:50.47#ibcon#about to read 3, iclass 22, count 0 2006.281.07:43:50.50#ibcon#read 3, iclass 22, count 0 2006.281.07:43:50.50#ibcon#about to read 4, iclass 22, count 0 2006.281.07:43:50.50#ibcon#read 4, iclass 22, count 0 2006.281.07:43:50.50#ibcon#about to read 5, iclass 22, count 0 2006.281.07:43:50.50#ibcon#read 5, iclass 22, count 0 2006.281.07:43:50.50#ibcon#about to read 6, iclass 22, count 0 2006.281.07:43:50.50#ibcon#read 6, iclass 22, count 0 2006.281.07:43:50.50#ibcon#end of sib2, iclass 22, count 0 2006.281.07:43:50.50#ibcon#*after write, iclass 22, count 0 2006.281.07:43:50.50#ibcon#*before return 0, iclass 22, count 0 2006.281.07:43:50.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:50.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:50.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:43:50.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:43:50.50$vc4f8/valo=4,832.99 2006.281.07:43:50.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:43:50.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:43:50.50#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:50.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:50.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:50.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:50.50#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:43:50.50#ibcon#first serial, iclass 24, count 0 2006.281.07:43:50.50#ibcon#enter sib2, iclass 24, count 0 2006.281.07:43:50.50#ibcon#flushed, iclass 24, count 0 2006.281.07:43:50.50#ibcon#about to write, iclass 24, count 0 2006.281.07:43:50.50#ibcon#wrote, iclass 24, count 0 2006.281.07:43:50.50#ibcon#about to read 3, iclass 24, count 0 2006.281.07:43:50.52#ibcon#read 3, iclass 24, count 0 2006.281.07:43:50.52#ibcon#about to read 4, iclass 24, count 0 2006.281.07:43:50.52#ibcon#read 4, iclass 24, count 0 2006.281.07:43:50.52#ibcon#about to read 5, iclass 24, count 0 2006.281.07:43:50.52#ibcon#read 5, iclass 24, count 0 2006.281.07:43:50.52#ibcon#about to read 6, iclass 24, count 0 2006.281.07:43:50.52#ibcon#read 6, iclass 24, count 0 2006.281.07:43:50.52#ibcon#end of sib2, iclass 24, count 0 2006.281.07:43:50.52#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:43:50.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:43:50.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:43:50.52#ibcon#*before write, iclass 24, count 0 2006.281.07:43:50.52#ibcon#enter sib2, iclass 24, count 0 2006.281.07:43:50.52#ibcon#flushed, iclass 24, count 0 2006.281.07:43:50.52#ibcon#about to write, iclass 24, count 0 2006.281.07:43:50.52#ibcon#wrote, iclass 24, count 0 2006.281.07:43:50.52#ibcon#about to read 3, iclass 24, count 0 2006.281.07:43:50.57#ibcon#read 3, iclass 24, count 0 2006.281.07:43:50.57#ibcon#about to read 4, iclass 24, count 0 2006.281.07:43:50.57#ibcon#read 4, iclass 24, count 0 2006.281.07:43:50.57#ibcon#about to read 5, iclass 24, count 0 2006.281.07:43:50.57#ibcon#read 5, iclass 24, count 0 2006.281.07:43:50.57#ibcon#about to read 6, iclass 24, count 0 2006.281.07:43:50.57#ibcon#read 6, iclass 24, count 0 2006.281.07:43:50.57#ibcon#end of sib2, iclass 24, count 0 2006.281.07:43:50.57#ibcon#*after write, iclass 24, count 0 2006.281.07:43:50.57#ibcon#*before return 0, iclass 24, count 0 2006.281.07:43:50.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:50.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:50.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:43:50.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:43:50.57$vc4f8/va=4,6 2006.281.07:43:50.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:43:50.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:43:50.57#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:50.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:50.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:50.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:50.61#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:43:50.61#ibcon#first serial, iclass 26, count 2 2006.281.07:43:50.61#ibcon#enter sib2, iclass 26, count 2 2006.281.07:43:50.61#ibcon#flushed, iclass 26, count 2 2006.281.07:43:50.61#ibcon#about to write, iclass 26, count 2 2006.281.07:43:50.61#ibcon#wrote, iclass 26, count 2 2006.281.07:43:50.61#ibcon#about to read 3, iclass 26, count 2 2006.281.07:43:50.64#ibcon#read 3, iclass 26, count 2 2006.281.07:43:50.64#ibcon#about to read 4, iclass 26, count 2 2006.281.07:43:50.64#ibcon#read 4, iclass 26, count 2 2006.281.07:43:50.64#ibcon#about to read 5, iclass 26, count 2 2006.281.07:43:50.64#ibcon#read 5, iclass 26, count 2 2006.281.07:43:50.64#ibcon#about to read 6, iclass 26, count 2 2006.281.07:43:50.64#ibcon#read 6, iclass 26, count 2 2006.281.07:43:50.64#ibcon#end of sib2, iclass 26, count 2 2006.281.07:43:50.64#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:43:50.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:43:50.64#ibcon#[25=AT04-06\r\n] 2006.281.07:43:50.64#ibcon#*before write, iclass 26, count 2 2006.281.07:43:50.64#ibcon#enter sib2, iclass 26, count 2 2006.281.07:43:50.64#ibcon#flushed, iclass 26, count 2 2006.281.07:43:50.64#ibcon#about to write, iclass 26, count 2 2006.281.07:43:50.64#ibcon#wrote, iclass 26, count 2 2006.281.07:43:50.64#ibcon#about to read 3, iclass 26, count 2 2006.281.07:43:50.67#ibcon#read 3, iclass 26, count 2 2006.281.07:43:50.67#ibcon#about to read 4, iclass 26, count 2 2006.281.07:43:50.67#ibcon#read 4, iclass 26, count 2 2006.281.07:43:50.67#ibcon#about to read 5, iclass 26, count 2 2006.281.07:43:50.67#ibcon#read 5, iclass 26, count 2 2006.281.07:43:50.67#ibcon#about to read 6, iclass 26, count 2 2006.281.07:43:50.67#ibcon#read 6, iclass 26, count 2 2006.281.07:43:50.67#ibcon#end of sib2, iclass 26, count 2 2006.281.07:43:50.67#ibcon#*after write, iclass 26, count 2 2006.281.07:43:50.67#ibcon#*before return 0, iclass 26, count 2 2006.281.07:43:50.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:50.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:50.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:43:50.67#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:50.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:50.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:50.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:50.79#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:43:50.79#ibcon#first serial, iclass 26, count 0 2006.281.07:43:50.79#ibcon#enter sib2, iclass 26, count 0 2006.281.07:43:50.79#ibcon#flushed, iclass 26, count 0 2006.281.07:43:50.79#ibcon#about to write, iclass 26, count 0 2006.281.07:43:50.79#ibcon#wrote, iclass 26, count 0 2006.281.07:43:50.79#ibcon#about to read 3, iclass 26, count 0 2006.281.07:43:50.81#ibcon#read 3, iclass 26, count 0 2006.281.07:43:50.81#ibcon#about to read 4, iclass 26, count 0 2006.281.07:43:50.81#ibcon#read 4, iclass 26, count 0 2006.281.07:43:50.81#ibcon#about to read 5, iclass 26, count 0 2006.281.07:43:50.81#ibcon#read 5, iclass 26, count 0 2006.281.07:43:50.81#ibcon#about to read 6, iclass 26, count 0 2006.281.07:43:50.81#ibcon#read 6, iclass 26, count 0 2006.281.07:43:50.81#ibcon#end of sib2, iclass 26, count 0 2006.281.07:43:50.81#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:43:50.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:43:50.81#ibcon#[25=USB\r\n] 2006.281.07:43:50.81#ibcon#*before write, iclass 26, count 0 2006.281.07:43:50.81#ibcon#enter sib2, iclass 26, count 0 2006.281.07:43:50.81#ibcon#flushed, iclass 26, count 0 2006.281.07:43:50.81#ibcon#about to write, iclass 26, count 0 2006.281.07:43:50.81#ibcon#wrote, iclass 26, count 0 2006.281.07:43:50.81#ibcon#about to read 3, iclass 26, count 0 2006.281.07:43:50.84#ibcon#read 3, iclass 26, count 0 2006.281.07:43:50.85#ibcon#about to read 4, iclass 26, count 0 2006.281.07:43:50.85#ibcon#read 4, iclass 26, count 0 2006.281.07:43:50.85#ibcon#about to read 5, iclass 26, count 0 2006.281.07:43:50.85#ibcon#read 5, iclass 26, count 0 2006.281.07:43:50.85#ibcon#about to read 6, iclass 26, count 0 2006.281.07:43:50.85#ibcon#read 6, iclass 26, count 0 2006.281.07:43:50.85#ibcon#end of sib2, iclass 26, count 0 2006.281.07:43:50.85#ibcon#*after write, iclass 26, count 0 2006.281.07:43:50.85#ibcon#*before return 0, iclass 26, count 0 2006.281.07:43:50.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:50.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:50.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:43:50.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:43:50.85$vc4f8/valo=5,652.99 2006.281.07:43:50.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:43:50.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:43:50.85#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:50.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:50.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:50.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:50.85#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:43:50.85#ibcon#first serial, iclass 28, count 0 2006.281.07:43:50.85#ibcon#enter sib2, iclass 28, count 0 2006.281.07:43:50.85#ibcon#flushed, iclass 28, count 0 2006.281.07:43:50.85#ibcon#about to write, iclass 28, count 0 2006.281.07:43:50.85#ibcon#wrote, iclass 28, count 0 2006.281.07:43:50.85#ibcon#about to read 3, iclass 28, count 0 2006.281.07:43:50.86#ibcon#read 3, iclass 28, count 0 2006.281.07:43:50.86#ibcon#about to read 4, iclass 28, count 0 2006.281.07:43:50.86#ibcon#read 4, iclass 28, count 0 2006.281.07:43:50.86#ibcon#about to read 5, iclass 28, count 0 2006.281.07:43:50.86#ibcon#read 5, iclass 28, count 0 2006.281.07:43:50.86#ibcon#about to read 6, iclass 28, count 0 2006.281.07:43:50.86#ibcon#read 6, iclass 28, count 0 2006.281.07:43:50.86#ibcon#end of sib2, iclass 28, count 0 2006.281.07:43:50.86#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:43:50.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:43:50.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:43:50.88#ibcon#*before write, iclass 28, count 0 2006.281.07:43:50.88#ibcon#enter sib2, iclass 28, count 0 2006.281.07:43:50.88#ibcon#flushed, iclass 28, count 0 2006.281.07:43:50.88#ibcon#about to write, iclass 28, count 0 2006.281.07:43:50.88#ibcon#wrote, iclass 28, count 0 2006.281.07:43:50.89#ibcon#about to read 3, iclass 28, count 0 2006.281.07:43:50.92#ibcon#read 3, iclass 28, count 0 2006.281.07:43:50.92#ibcon#about to read 4, iclass 28, count 0 2006.281.07:43:50.92#ibcon#read 4, iclass 28, count 0 2006.281.07:43:50.92#ibcon#about to read 5, iclass 28, count 0 2006.281.07:43:50.92#ibcon#read 5, iclass 28, count 0 2006.281.07:43:50.92#ibcon#about to read 6, iclass 28, count 0 2006.281.07:43:50.92#ibcon#read 6, iclass 28, count 0 2006.281.07:43:50.92#ibcon#end of sib2, iclass 28, count 0 2006.281.07:43:50.92#ibcon#*after write, iclass 28, count 0 2006.281.07:43:50.92#ibcon#*before return 0, iclass 28, count 0 2006.281.07:43:50.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:50.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:50.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:43:50.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:43:50.92$vc4f8/va=5,7 2006.281.07:43:50.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:43:50.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:43:50.92#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:50.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:50.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:50.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:50.98#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:43:50.98#ibcon#first serial, iclass 30, count 2 2006.281.07:43:50.98#ibcon#enter sib2, iclass 30, count 2 2006.281.07:43:50.98#ibcon#flushed, iclass 30, count 2 2006.281.07:43:50.98#ibcon#about to write, iclass 30, count 2 2006.281.07:43:50.98#ibcon#wrote, iclass 30, count 2 2006.281.07:43:50.98#ibcon#about to read 3, iclass 30, count 2 2006.281.07:43:50.99#ibcon#read 3, iclass 30, count 2 2006.281.07:43:50.99#ibcon#about to read 4, iclass 30, count 2 2006.281.07:43:50.99#ibcon#read 4, iclass 30, count 2 2006.281.07:43:50.99#ibcon#about to read 5, iclass 30, count 2 2006.281.07:43:50.99#ibcon#read 5, iclass 30, count 2 2006.281.07:43:50.99#ibcon#about to read 6, iclass 30, count 2 2006.281.07:43:50.99#ibcon#read 6, iclass 30, count 2 2006.281.07:43:50.99#ibcon#end of sib2, iclass 30, count 2 2006.281.07:43:50.99#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:43:50.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:43:50.99#ibcon#[25=AT05-07\r\n] 2006.281.07:43:50.99#ibcon#*before write, iclass 30, count 2 2006.281.07:43:50.99#ibcon#enter sib2, iclass 30, count 2 2006.281.07:43:50.99#ibcon#flushed, iclass 30, count 2 2006.281.07:43:50.99#ibcon#about to write, iclass 30, count 2 2006.281.07:43:50.99#ibcon#wrote, iclass 30, count 2 2006.281.07:43:50.99#ibcon#about to read 3, iclass 30, count 2 2006.281.07:43:51.03#ibcon#read 3, iclass 30, count 2 2006.281.07:43:51.03#ibcon#about to read 4, iclass 30, count 2 2006.281.07:43:51.03#ibcon#read 4, iclass 30, count 2 2006.281.07:43:51.03#ibcon#about to read 5, iclass 30, count 2 2006.281.07:43:51.03#ibcon#read 5, iclass 30, count 2 2006.281.07:43:51.03#ibcon#about to read 6, iclass 30, count 2 2006.281.07:43:51.03#ibcon#read 6, iclass 30, count 2 2006.281.07:43:51.03#ibcon#end of sib2, iclass 30, count 2 2006.281.07:43:51.03#ibcon#*after write, iclass 30, count 2 2006.281.07:43:51.03#ibcon#*before return 0, iclass 30, count 2 2006.281.07:43:51.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:51.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:51.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:43:51.03#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:51.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:51.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:51.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:51.15#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:43:51.15#ibcon#first serial, iclass 30, count 0 2006.281.07:43:51.15#ibcon#enter sib2, iclass 30, count 0 2006.281.07:43:51.15#ibcon#flushed, iclass 30, count 0 2006.281.07:43:51.15#ibcon#about to write, iclass 30, count 0 2006.281.07:43:51.15#ibcon#wrote, iclass 30, count 0 2006.281.07:43:51.15#ibcon#about to read 3, iclass 30, count 0 2006.281.07:43:51.16#ibcon#read 3, iclass 30, count 0 2006.281.07:43:51.16#ibcon#about to read 4, iclass 30, count 0 2006.281.07:43:51.16#ibcon#read 4, iclass 30, count 0 2006.281.07:43:51.16#ibcon#about to read 5, iclass 30, count 0 2006.281.07:43:51.16#ibcon#read 5, iclass 30, count 0 2006.281.07:43:51.16#ibcon#about to read 6, iclass 30, count 0 2006.281.07:43:51.16#ibcon#read 6, iclass 30, count 0 2006.281.07:43:51.16#ibcon#end of sib2, iclass 30, count 0 2006.281.07:43:51.16#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:43:51.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:43:51.16#ibcon#[25=USB\r\n] 2006.281.07:43:51.16#ibcon#*before write, iclass 30, count 0 2006.281.07:43:51.16#ibcon#enter sib2, iclass 30, count 0 2006.281.07:43:51.16#ibcon#flushed, iclass 30, count 0 2006.281.07:43:51.16#ibcon#about to write, iclass 30, count 0 2006.281.07:43:51.16#ibcon#wrote, iclass 30, count 0 2006.281.07:43:51.16#ibcon#about to read 3, iclass 30, count 0 2006.281.07:43:51.19#ibcon#read 3, iclass 30, count 0 2006.281.07:43:51.19#ibcon#about to read 4, iclass 30, count 0 2006.281.07:43:51.19#ibcon#read 4, iclass 30, count 0 2006.281.07:43:51.19#ibcon#about to read 5, iclass 30, count 0 2006.281.07:43:51.19#ibcon#read 5, iclass 30, count 0 2006.281.07:43:51.19#ibcon#about to read 6, iclass 30, count 0 2006.281.07:43:51.19#ibcon#read 6, iclass 30, count 0 2006.281.07:43:51.19#ibcon#end of sib2, iclass 30, count 0 2006.281.07:43:51.19#ibcon#*after write, iclass 30, count 0 2006.281.07:43:51.19#ibcon#*before return 0, iclass 30, count 0 2006.281.07:43:51.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:51.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:51.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:43:51.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:43:51.19$vc4f8/valo=6,772.99 2006.281.07:43:51.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:43:51.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:43:51.19#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:51.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:51.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:51.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:51.19#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:43:51.19#ibcon#first serial, iclass 32, count 0 2006.281.07:43:51.19#ibcon#enter sib2, iclass 32, count 0 2006.281.07:43:51.19#ibcon#flushed, iclass 32, count 0 2006.281.07:43:51.19#ibcon#about to write, iclass 32, count 0 2006.281.07:43:51.19#ibcon#wrote, iclass 32, count 0 2006.281.07:43:51.19#ibcon#about to read 3, iclass 32, count 0 2006.281.07:43:51.21#ibcon#read 3, iclass 32, count 0 2006.281.07:43:51.21#ibcon#about to read 4, iclass 32, count 0 2006.281.07:43:51.21#ibcon#read 4, iclass 32, count 0 2006.281.07:43:51.21#ibcon#about to read 5, iclass 32, count 0 2006.281.07:43:51.21#ibcon#read 5, iclass 32, count 0 2006.281.07:43:51.21#ibcon#about to read 6, iclass 32, count 0 2006.281.07:43:51.21#ibcon#read 6, iclass 32, count 0 2006.281.07:43:51.21#ibcon#end of sib2, iclass 32, count 0 2006.281.07:43:51.21#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:43:51.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:43:51.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:43:51.21#ibcon#*before write, iclass 32, count 0 2006.281.07:43:51.21#ibcon#enter sib2, iclass 32, count 0 2006.281.07:43:51.21#ibcon#flushed, iclass 32, count 0 2006.281.07:43:51.21#ibcon#about to write, iclass 32, count 0 2006.281.07:43:51.21#ibcon#wrote, iclass 32, count 0 2006.281.07:43:51.21#ibcon#about to read 3, iclass 32, count 0 2006.281.07:43:51.25#ibcon#read 3, iclass 32, count 0 2006.281.07:43:51.25#ibcon#about to read 4, iclass 32, count 0 2006.281.07:43:51.25#ibcon#read 4, iclass 32, count 0 2006.281.07:43:51.25#ibcon#about to read 5, iclass 32, count 0 2006.281.07:43:51.25#ibcon#read 5, iclass 32, count 0 2006.281.07:43:51.25#ibcon#about to read 6, iclass 32, count 0 2006.281.07:43:51.25#ibcon#read 6, iclass 32, count 0 2006.281.07:43:51.25#ibcon#end of sib2, iclass 32, count 0 2006.281.07:43:51.25#ibcon#*after write, iclass 32, count 0 2006.281.07:43:51.25#ibcon#*before return 0, iclass 32, count 0 2006.281.07:43:51.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:51.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:51.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:43:51.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:43:51.25$vc4f8/va=6,6 2006.281.07:43:51.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:43:51.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:43:51.25#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:51.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:51.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:51.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:51.31#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:43:51.31#ibcon#first serial, iclass 34, count 2 2006.281.07:43:51.31#ibcon#enter sib2, iclass 34, count 2 2006.281.07:43:51.31#ibcon#flushed, iclass 34, count 2 2006.281.07:43:51.31#ibcon#about to write, iclass 34, count 2 2006.281.07:43:51.31#ibcon#wrote, iclass 34, count 2 2006.281.07:43:51.31#ibcon#about to read 3, iclass 34, count 2 2006.281.07:43:51.33#ibcon#read 3, iclass 34, count 2 2006.281.07:43:51.33#ibcon#about to read 4, iclass 34, count 2 2006.281.07:43:51.33#ibcon#read 4, iclass 34, count 2 2006.281.07:43:51.33#ibcon#about to read 5, iclass 34, count 2 2006.281.07:43:51.33#ibcon#read 5, iclass 34, count 2 2006.281.07:43:51.33#ibcon#about to read 6, iclass 34, count 2 2006.281.07:43:51.33#ibcon#read 6, iclass 34, count 2 2006.281.07:43:51.33#ibcon#end of sib2, iclass 34, count 2 2006.281.07:43:51.33#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:43:51.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:43:51.33#ibcon#[25=AT06-06\r\n] 2006.281.07:43:51.33#ibcon#*before write, iclass 34, count 2 2006.281.07:43:51.33#ibcon#enter sib2, iclass 34, count 2 2006.281.07:43:51.33#ibcon#flushed, iclass 34, count 2 2006.281.07:43:51.33#ibcon#about to write, iclass 34, count 2 2006.281.07:43:51.33#ibcon#wrote, iclass 34, count 2 2006.281.07:43:51.33#ibcon#about to read 3, iclass 34, count 2 2006.281.07:43:51.36#ibcon#read 3, iclass 34, count 2 2006.281.07:43:51.36#ibcon#about to read 4, iclass 34, count 2 2006.281.07:43:51.36#ibcon#read 4, iclass 34, count 2 2006.281.07:43:51.36#ibcon#about to read 5, iclass 34, count 2 2006.281.07:43:51.36#ibcon#read 5, iclass 34, count 2 2006.281.07:43:51.36#ibcon#about to read 6, iclass 34, count 2 2006.281.07:43:51.36#ibcon#read 6, iclass 34, count 2 2006.281.07:43:51.36#ibcon#end of sib2, iclass 34, count 2 2006.281.07:43:51.36#ibcon#*after write, iclass 34, count 2 2006.281.07:43:51.36#ibcon#*before return 0, iclass 34, count 2 2006.281.07:43:51.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:51.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:51.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:43:51.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:51.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:51.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:51.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:51.48#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:43:51.48#ibcon#first serial, iclass 34, count 0 2006.281.07:43:51.48#ibcon#enter sib2, iclass 34, count 0 2006.281.07:43:51.48#ibcon#flushed, iclass 34, count 0 2006.281.07:43:51.48#ibcon#about to write, iclass 34, count 0 2006.281.07:43:51.48#ibcon#wrote, iclass 34, count 0 2006.281.07:43:51.48#ibcon#about to read 3, iclass 34, count 0 2006.281.07:43:51.50#ibcon#read 3, iclass 34, count 0 2006.281.07:43:51.50#ibcon#about to read 4, iclass 34, count 0 2006.281.07:43:51.50#ibcon#read 4, iclass 34, count 0 2006.281.07:43:51.50#ibcon#about to read 5, iclass 34, count 0 2006.281.07:43:51.50#ibcon#read 5, iclass 34, count 0 2006.281.07:43:51.50#ibcon#about to read 6, iclass 34, count 0 2006.281.07:43:51.50#ibcon#read 6, iclass 34, count 0 2006.281.07:43:51.50#ibcon#end of sib2, iclass 34, count 0 2006.281.07:43:51.50#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:43:51.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:43:51.50#ibcon#[25=USB\r\n] 2006.281.07:43:51.50#ibcon#*before write, iclass 34, count 0 2006.281.07:43:51.50#ibcon#enter sib2, iclass 34, count 0 2006.281.07:43:51.50#ibcon#flushed, iclass 34, count 0 2006.281.07:43:51.50#ibcon#about to write, iclass 34, count 0 2006.281.07:43:51.50#ibcon#wrote, iclass 34, count 0 2006.281.07:43:51.50#ibcon#about to read 3, iclass 34, count 0 2006.281.07:43:51.53#ibcon#read 3, iclass 34, count 0 2006.281.07:43:51.53#ibcon#about to read 4, iclass 34, count 0 2006.281.07:43:51.53#ibcon#read 4, iclass 34, count 0 2006.281.07:43:51.53#ibcon#about to read 5, iclass 34, count 0 2006.281.07:43:51.53#ibcon#read 5, iclass 34, count 0 2006.281.07:43:51.53#ibcon#about to read 6, iclass 34, count 0 2006.281.07:43:51.54#ibcon#read 6, iclass 34, count 0 2006.281.07:43:51.54#ibcon#end of sib2, iclass 34, count 0 2006.281.07:43:51.54#ibcon#*after write, iclass 34, count 0 2006.281.07:43:51.54#ibcon#*before return 0, iclass 34, count 0 2006.281.07:43:51.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:51.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:51.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:43:51.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:43:51.54$vc4f8/valo=7,832.99 2006.281.07:43:51.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:43:51.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:43:51.54#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:51.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:51.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:51.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:51.54#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:43:51.54#ibcon#first serial, iclass 36, count 0 2006.281.07:43:51.54#ibcon#enter sib2, iclass 36, count 0 2006.281.07:43:51.54#ibcon#flushed, iclass 36, count 0 2006.281.07:43:51.54#ibcon#about to write, iclass 36, count 0 2006.281.07:43:51.54#ibcon#wrote, iclass 36, count 0 2006.281.07:43:51.54#ibcon#about to read 3, iclass 36, count 0 2006.281.07:43:51.55#ibcon#read 3, iclass 36, count 0 2006.281.07:43:51.55#ibcon#about to read 4, iclass 36, count 0 2006.281.07:43:51.55#ibcon#read 4, iclass 36, count 0 2006.281.07:43:51.55#ibcon#about to read 5, iclass 36, count 0 2006.281.07:43:51.55#ibcon#read 5, iclass 36, count 0 2006.281.07:43:51.55#ibcon#about to read 6, iclass 36, count 0 2006.281.07:43:51.55#ibcon#read 6, iclass 36, count 0 2006.281.07:43:51.55#ibcon#end of sib2, iclass 36, count 0 2006.281.07:43:51.55#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:43:51.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:43:51.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:43:51.57#ibcon#*before write, iclass 36, count 0 2006.281.07:43:51.57#ibcon#enter sib2, iclass 36, count 0 2006.281.07:43:51.57#ibcon#flushed, iclass 36, count 0 2006.281.07:43:51.57#ibcon#about to write, iclass 36, count 0 2006.281.07:43:51.57#ibcon#wrote, iclass 36, count 0 2006.281.07:43:51.57#ibcon#about to read 3, iclass 36, count 0 2006.281.07:43:51.61#ibcon#read 3, iclass 36, count 0 2006.281.07:43:51.61#ibcon#about to read 4, iclass 36, count 0 2006.281.07:43:51.61#ibcon#read 4, iclass 36, count 0 2006.281.07:43:51.61#ibcon#about to read 5, iclass 36, count 0 2006.281.07:43:51.61#ibcon#read 5, iclass 36, count 0 2006.281.07:43:51.61#ibcon#about to read 6, iclass 36, count 0 2006.281.07:43:51.61#ibcon#read 6, iclass 36, count 0 2006.281.07:43:51.61#ibcon#end of sib2, iclass 36, count 0 2006.281.07:43:51.61#ibcon#*after write, iclass 36, count 0 2006.281.07:43:51.61#ibcon#*before return 0, iclass 36, count 0 2006.281.07:43:51.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:51.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:51.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:43:51.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:43:51.61$vc4f8/va=7,6 2006.281.07:43:51.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:43:51.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:43:51.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:51.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:51.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:51.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:51.67#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:43:51.67#ibcon#first serial, iclass 38, count 2 2006.281.07:43:51.67#ibcon#enter sib2, iclass 38, count 2 2006.281.07:43:51.67#ibcon#flushed, iclass 38, count 2 2006.281.07:43:51.67#ibcon#about to write, iclass 38, count 2 2006.281.07:43:51.67#ibcon#wrote, iclass 38, count 2 2006.281.07:43:51.67#ibcon#about to read 3, iclass 38, count 2 2006.281.07:43:51.68#ibcon#read 3, iclass 38, count 2 2006.281.07:43:51.68#ibcon#about to read 4, iclass 38, count 2 2006.281.07:43:51.68#ibcon#read 4, iclass 38, count 2 2006.281.07:43:51.68#ibcon#about to read 5, iclass 38, count 2 2006.281.07:43:51.68#ibcon#read 5, iclass 38, count 2 2006.281.07:43:51.68#ibcon#about to read 6, iclass 38, count 2 2006.281.07:43:51.68#ibcon#read 6, iclass 38, count 2 2006.281.07:43:51.68#ibcon#end of sib2, iclass 38, count 2 2006.281.07:43:51.68#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:43:51.68#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:43:51.68#ibcon#[25=AT07-06\r\n] 2006.281.07:43:51.68#ibcon#*before write, iclass 38, count 2 2006.281.07:43:51.68#ibcon#enter sib2, iclass 38, count 2 2006.281.07:43:51.68#ibcon#flushed, iclass 38, count 2 2006.281.07:43:51.68#ibcon#about to write, iclass 38, count 2 2006.281.07:43:51.68#ibcon#wrote, iclass 38, count 2 2006.281.07:43:51.68#ibcon#about to read 3, iclass 38, count 2 2006.281.07:43:51.71#ibcon#read 3, iclass 38, count 2 2006.281.07:43:51.71#ibcon#about to read 4, iclass 38, count 2 2006.281.07:43:51.71#ibcon#read 4, iclass 38, count 2 2006.281.07:43:51.71#ibcon#about to read 5, iclass 38, count 2 2006.281.07:43:51.71#ibcon#read 5, iclass 38, count 2 2006.281.07:43:51.71#ibcon#about to read 6, iclass 38, count 2 2006.281.07:43:51.71#ibcon#read 6, iclass 38, count 2 2006.281.07:43:51.71#ibcon#end of sib2, iclass 38, count 2 2006.281.07:43:51.71#ibcon#*after write, iclass 38, count 2 2006.281.07:43:51.71#ibcon#*before return 0, iclass 38, count 2 2006.281.07:43:51.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:51.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:51.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:43:51.71#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:51.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:43:51.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:43:51.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:43:51.83#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:43:51.83#ibcon#first serial, iclass 38, count 0 2006.281.07:43:51.83#ibcon#enter sib2, iclass 38, count 0 2006.281.07:43:51.83#ibcon#flushed, iclass 38, count 0 2006.281.07:43:51.83#ibcon#about to write, iclass 38, count 0 2006.281.07:43:51.83#ibcon#wrote, iclass 38, count 0 2006.281.07:43:51.83#ibcon#about to read 3, iclass 38, count 0 2006.281.07:43:51.85#ibcon#read 3, iclass 38, count 0 2006.281.07:43:51.85#ibcon#about to read 4, iclass 38, count 0 2006.281.07:43:51.85#ibcon#read 4, iclass 38, count 0 2006.281.07:43:51.85#ibcon#about to read 5, iclass 38, count 0 2006.281.07:43:51.85#ibcon#read 5, iclass 38, count 0 2006.281.07:43:51.85#ibcon#about to read 6, iclass 38, count 0 2006.281.07:43:51.85#ibcon#read 6, iclass 38, count 0 2006.281.07:43:51.85#ibcon#end of sib2, iclass 38, count 0 2006.281.07:43:51.85#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:43:51.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:43:51.85#ibcon#[25=USB\r\n] 2006.281.07:43:51.85#ibcon#*before write, iclass 38, count 0 2006.281.07:43:51.85#ibcon#enter sib2, iclass 38, count 0 2006.281.07:43:51.85#ibcon#flushed, iclass 38, count 0 2006.281.07:43:51.85#ibcon#about to write, iclass 38, count 0 2006.281.07:43:51.85#ibcon#wrote, iclass 38, count 0 2006.281.07:43:51.85#ibcon#about to read 3, iclass 38, count 0 2006.281.07:43:51.88#ibcon#read 3, iclass 38, count 0 2006.281.07:43:51.88#ibcon#about to read 4, iclass 38, count 0 2006.281.07:43:51.88#ibcon#read 4, iclass 38, count 0 2006.281.07:43:51.88#ibcon#about to read 5, iclass 38, count 0 2006.281.07:43:51.88#ibcon#read 5, iclass 38, count 0 2006.281.07:43:51.88#ibcon#about to read 6, iclass 38, count 0 2006.281.07:43:51.88#ibcon#read 6, iclass 38, count 0 2006.281.07:43:51.88#ibcon#end of sib2, iclass 38, count 0 2006.281.07:43:51.88#ibcon#*after write, iclass 38, count 0 2006.281.07:43:51.88#ibcon#*before return 0, iclass 38, count 0 2006.281.07:43:51.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:43:51.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:43:51.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:43:51.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:43:51.88$vc4f8/valo=8,852.99 2006.281.07:43:51.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:43:51.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:43:51.88#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:51.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:43:51.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:43:51.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:43:51.88#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:43:51.88#ibcon#first serial, iclass 40, count 0 2006.281.07:43:51.88#ibcon#enter sib2, iclass 40, count 0 2006.281.07:43:51.88#ibcon#flushed, iclass 40, count 0 2006.281.07:43:51.88#ibcon#about to write, iclass 40, count 0 2006.281.07:43:51.88#ibcon#wrote, iclass 40, count 0 2006.281.07:43:51.88#ibcon#about to read 3, iclass 40, count 0 2006.281.07:43:51.90#ibcon#read 3, iclass 40, count 0 2006.281.07:43:51.90#ibcon#about to read 4, iclass 40, count 0 2006.281.07:43:51.90#ibcon#read 4, iclass 40, count 0 2006.281.07:43:51.90#ibcon#about to read 5, iclass 40, count 0 2006.281.07:43:51.90#ibcon#read 5, iclass 40, count 0 2006.281.07:43:51.90#ibcon#about to read 6, iclass 40, count 0 2006.281.07:43:51.90#ibcon#read 6, iclass 40, count 0 2006.281.07:43:51.90#ibcon#end of sib2, iclass 40, count 0 2006.281.07:43:51.90#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:43:51.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:43:51.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:43:51.90#ibcon#*before write, iclass 40, count 0 2006.281.07:43:51.90#ibcon#enter sib2, iclass 40, count 0 2006.281.07:43:51.90#ibcon#flushed, iclass 40, count 0 2006.281.07:43:51.90#ibcon#about to write, iclass 40, count 0 2006.281.07:43:51.90#ibcon#wrote, iclass 40, count 0 2006.281.07:43:51.90#ibcon#about to read 3, iclass 40, count 0 2006.281.07:43:51.94#ibcon#read 3, iclass 40, count 0 2006.281.07:43:51.94#ibcon#about to read 4, iclass 40, count 0 2006.281.07:43:51.94#ibcon#read 4, iclass 40, count 0 2006.281.07:43:51.94#ibcon#about to read 5, iclass 40, count 0 2006.281.07:43:51.94#ibcon#read 5, iclass 40, count 0 2006.281.07:43:51.94#ibcon#about to read 6, iclass 40, count 0 2006.281.07:43:51.94#ibcon#read 6, iclass 40, count 0 2006.281.07:43:51.94#ibcon#end of sib2, iclass 40, count 0 2006.281.07:43:51.94#ibcon#*after write, iclass 40, count 0 2006.281.07:43:51.94#ibcon#*before return 0, iclass 40, count 0 2006.281.07:43:51.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:43:51.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:43:51.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:43:51.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:43:51.94$vc4f8/va=8,6 2006.281.07:43:51.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:43:51.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:43:51.94#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:51.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:43:52.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:43:52.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:43:52.00#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:43:52.00#ibcon#first serial, iclass 4, count 2 2006.281.07:43:52.00#ibcon#enter sib2, iclass 4, count 2 2006.281.07:43:52.00#ibcon#flushed, iclass 4, count 2 2006.281.07:43:52.00#ibcon#about to write, iclass 4, count 2 2006.281.07:43:52.00#ibcon#wrote, iclass 4, count 2 2006.281.07:43:52.00#ibcon#about to read 3, iclass 4, count 2 2006.281.07:43:52.02#ibcon#read 3, iclass 4, count 2 2006.281.07:43:52.02#ibcon#about to read 4, iclass 4, count 2 2006.281.07:43:52.02#ibcon#read 4, iclass 4, count 2 2006.281.07:43:52.02#ibcon#about to read 5, iclass 4, count 2 2006.281.07:43:52.02#ibcon#read 5, iclass 4, count 2 2006.281.07:43:52.02#ibcon#about to read 6, iclass 4, count 2 2006.281.07:43:52.02#ibcon#read 6, iclass 4, count 2 2006.281.07:43:52.02#ibcon#end of sib2, iclass 4, count 2 2006.281.07:43:52.02#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:43:52.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:43:52.02#ibcon#[25=AT08-06\r\n] 2006.281.07:43:52.02#ibcon#*before write, iclass 4, count 2 2006.281.07:43:52.02#ibcon#enter sib2, iclass 4, count 2 2006.281.07:43:52.02#ibcon#flushed, iclass 4, count 2 2006.281.07:43:52.02#ibcon#about to write, iclass 4, count 2 2006.281.07:43:52.02#ibcon#wrote, iclass 4, count 2 2006.281.07:43:52.02#ibcon#about to read 3, iclass 4, count 2 2006.281.07:43:52.05#ibcon#read 3, iclass 4, count 2 2006.281.07:43:52.05#ibcon#about to read 4, iclass 4, count 2 2006.281.07:43:52.05#ibcon#read 4, iclass 4, count 2 2006.281.07:43:52.05#ibcon#about to read 5, iclass 4, count 2 2006.281.07:43:52.05#ibcon#read 5, iclass 4, count 2 2006.281.07:43:52.05#ibcon#about to read 6, iclass 4, count 2 2006.281.07:43:52.05#ibcon#read 6, iclass 4, count 2 2006.281.07:43:52.05#ibcon#end of sib2, iclass 4, count 2 2006.281.07:43:52.05#ibcon#*after write, iclass 4, count 2 2006.281.07:43:52.05#ibcon#*before return 0, iclass 4, count 2 2006.281.07:43:52.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:43:52.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:43:52.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:43:52.05#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:52.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:43:52.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:43:52.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:43:52.17#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:43:52.17#ibcon#first serial, iclass 4, count 0 2006.281.07:43:52.17#ibcon#enter sib2, iclass 4, count 0 2006.281.07:43:52.17#ibcon#flushed, iclass 4, count 0 2006.281.07:43:52.17#ibcon#about to write, iclass 4, count 0 2006.281.07:43:52.17#ibcon#wrote, iclass 4, count 0 2006.281.07:43:52.17#ibcon#about to read 3, iclass 4, count 0 2006.281.07:43:52.19#ibcon#read 3, iclass 4, count 0 2006.281.07:43:52.19#ibcon#about to read 4, iclass 4, count 0 2006.281.07:43:52.19#ibcon#read 4, iclass 4, count 0 2006.281.07:43:52.19#ibcon#about to read 5, iclass 4, count 0 2006.281.07:43:52.19#ibcon#read 5, iclass 4, count 0 2006.281.07:43:52.19#ibcon#about to read 6, iclass 4, count 0 2006.281.07:43:52.19#ibcon#read 6, iclass 4, count 0 2006.281.07:43:52.19#ibcon#end of sib2, iclass 4, count 0 2006.281.07:43:52.19#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:43:52.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:43:52.19#ibcon#[25=USB\r\n] 2006.281.07:43:52.19#ibcon#*before write, iclass 4, count 0 2006.281.07:43:52.19#ibcon#enter sib2, iclass 4, count 0 2006.281.07:43:52.19#ibcon#flushed, iclass 4, count 0 2006.281.07:43:52.19#ibcon#about to write, iclass 4, count 0 2006.281.07:43:52.19#ibcon#wrote, iclass 4, count 0 2006.281.07:43:52.19#ibcon#about to read 3, iclass 4, count 0 2006.281.07:43:52.22#ibcon#read 3, iclass 4, count 0 2006.281.07:43:52.22#ibcon#about to read 4, iclass 4, count 0 2006.281.07:43:52.22#ibcon#read 4, iclass 4, count 0 2006.281.07:43:52.22#ibcon#about to read 5, iclass 4, count 0 2006.281.07:43:52.23#ibcon#read 5, iclass 4, count 0 2006.281.07:43:52.23#ibcon#about to read 6, iclass 4, count 0 2006.281.07:43:52.23#ibcon#read 6, iclass 4, count 0 2006.281.07:43:52.23#ibcon#end of sib2, iclass 4, count 0 2006.281.07:43:52.23#ibcon#*after write, iclass 4, count 0 2006.281.07:43:52.23#ibcon#*before return 0, iclass 4, count 0 2006.281.07:43:52.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:43:52.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:43:52.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:43:52.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:43:52.23$vc4f8/vblo=1,632.99 2006.281.07:43:52.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:43:52.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:43:52.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:52.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:43:52.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:43:52.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:43:52.23#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:43:52.23#ibcon#first serial, iclass 6, count 0 2006.281.07:43:52.23#ibcon#enter sib2, iclass 6, count 0 2006.281.07:43:52.23#ibcon#flushed, iclass 6, count 0 2006.281.07:43:52.23#ibcon#about to write, iclass 6, count 0 2006.281.07:43:52.23#ibcon#wrote, iclass 6, count 0 2006.281.07:43:52.23#ibcon#about to read 3, iclass 6, count 0 2006.281.07:43:52.24#ibcon#read 3, iclass 6, count 0 2006.281.07:43:52.24#ibcon#about to read 4, iclass 6, count 0 2006.281.07:43:52.24#ibcon#read 4, iclass 6, count 0 2006.281.07:43:52.24#ibcon#about to read 5, iclass 6, count 0 2006.281.07:43:52.24#ibcon#read 5, iclass 6, count 0 2006.281.07:43:52.24#ibcon#about to read 6, iclass 6, count 0 2006.281.07:43:52.24#ibcon#read 6, iclass 6, count 0 2006.281.07:43:52.24#ibcon#end of sib2, iclass 6, count 0 2006.281.07:43:52.24#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:43:52.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:43:52.27#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:43:52.27#ibcon#*before write, iclass 6, count 0 2006.281.07:43:52.27#ibcon#enter sib2, iclass 6, count 0 2006.281.07:43:52.27#ibcon#flushed, iclass 6, count 0 2006.281.07:43:52.27#ibcon#about to write, iclass 6, count 0 2006.281.07:43:52.27#ibcon#wrote, iclass 6, count 0 2006.281.07:43:52.27#ibcon#about to read 3, iclass 6, count 0 2006.281.07:43:52.30#ibcon#read 3, iclass 6, count 0 2006.281.07:43:52.30#ibcon#about to read 4, iclass 6, count 0 2006.281.07:43:52.30#ibcon#read 4, iclass 6, count 0 2006.281.07:43:52.30#ibcon#about to read 5, iclass 6, count 0 2006.281.07:43:52.30#ibcon#read 5, iclass 6, count 0 2006.281.07:43:52.30#ibcon#about to read 6, iclass 6, count 0 2006.281.07:43:52.30#ibcon#read 6, iclass 6, count 0 2006.281.07:43:52.30#ibcon#end of sib2, iclass 6, count 0 2006.281.07:43:52.30#ibcon#*after write, iclass 6, count 0 2006.281.07:43:52.30#ibcon#*before return 0, iclass 6, count 0 2006.281.07:43:52.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:43:52.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:43:52.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:43:52.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:43:52.30$vc4f8/vb=1,4 2006.281.07:43:52.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.07:43:52.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.07:43:52.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:52.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:43:52.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:43:52.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:43:52.30#ibcon#enter wrdev, iclass 10, count 2 2006.281.07:43:52.30#ibcon#first serial, iclass 10, count 2 2006.281.07:43:52.30#ibcon#enter sib2, iclass 10, count 2 2006.281.07:43:52.30#ibcon#flushed, iclass 10, count 2 2006.281.07:43:52.30#ibcon#about to write, iclass 10, count 2 2006.281.07:43:52.30#ibcon#wrote, iclass 10, count 2 2006.281.07:43:52.30#ibcon#about to read 3, iclass 10, count 2 2006.281.07:43:52.32#ibcon#read 3, iclass 10, count 2 2006.281.07:43:52.32#ibcon#about to read 4, iclass 10, count 2 2006.281.07:43:52.32#ibcon#read 4, iclass 10, count 2 2006.281.07:43:52.32#ibcon#about to read 5, iclass 10, count 2 2006.281.07:43:52.32#ibcon#read 5, iclass 10, count 2 2006.281.07:43:52.32#ibcon#about to read 6, iclass 10, count 2 2006.281.07:43:52.32#ibcon#read 6, iclass 10, count 2 2006.281.07:43:52.32#ibcon#end of sib2, iclass 10, count 2 2006.281.07:43:52.32#ibcon#*mode == 0, iclass 10, count 2 2006.281.07:43:52.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.07:43:52.32#ibcon#[27=AT01-04\r\n] 2006.281.07:43:52.32#ibcon#*before write, iclass 10, count 2 2006.281.07:43:52.32#ibcon#enter sib2, iclass 10, count 2 2006.281.07:43:52.32#ibcon#flushed, iclass 10, count 2 2006.281.07:43:52.32#ibcon#about to write, iclass 10, count 2 2006.281.07:43:52.32#ibcon#wrote, iclass 10, count 2 2006.281.07:43:52.32#ibcon#about to read 3, iclass 10, count 2 2006.281.07:43:52.35#ibcon#read 3, iclass 10, count 2 2006.281.07:43:52.35#ibcon#about to read 4, iclass 10, count 2 2006.281.07:43:52.37#ibcon#read 4, iclass 10, count 2 2006.281.07:43:52.37#ibcon#about to read 5, iclass 10, count 2 2006.281.07:43:52.37#ibcon#read 5, iclass 10, count 2 2006.281.07:43:52.37#ibcon#about to read 6, iclass 10, count 2 2006.281.07:43:52.37#ibcon#read 6, iclass 10, count 2 2006.281.07:43:52.37#ibcon#end of sib2, iclass 10, count 2 2006.281.07:43:52.37#ibcon#*after write, iclass 10, count 2 2006.281.07:43:52.37#ibcon#*before return 0, iclass 10, count 2 2006.281.07:43:52.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:43:52.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:43:52.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.07:43:52.37#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:52.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:43:52.36#abcon#<5=/12 2.2 9.5 21.03 501001.1\r\n> 2006.281.07:43:52.38#abcon#{5=INTERFACE CLEAR} 2006.281.07:43:52.44#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:43:52.48#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:43:52.48#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:43:52.48#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:43:52.48#ibcon#first serial, iclass 10, count 0 2006.281.07:43:52.48#ibcon#enter sib2, iclass 10, count 0 2006.281.07:43:52.48#ibcon#flushed, iclass 10, count 0 2006.281.07:43:52.48#ibcon#about to write, iclass 10, count 0 2006.281.07:43:52.48#ibcon#wrote, iclass 10, count 0 2006.281.07:43:52.48#ibcon#about to read 3, iclass 10, count 0 2006.281.07:43:52.50#ibcon#read 3, iclass 10, count 0 2006.281.07:43:52.50#ibcon#about to read 4, iclass 10, count 0 2006.281.07:43:52.50#ibcon#read 4, iclass 10, count 0 2006.281.07:43:52.50#ibcon#about to read 5, iclass 10, count 0 2006.281.07:43:52.50#ibcon#read 5, iclass 10, count 0 2006.281.07:43:52.50#ibcon#about to read 6, iclass 10, count 0 2006.281.07:43:52.50#ibcon#read 6, iclass 10, count 0 2006.281.07:43:52.50#ibcon#end of sib2, iclass 10, count 0 2006.281.07:43:52.50#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:43:52.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:43:52.50#ibcon#[27=USB\r\n] 2006.281.07:43:52.50#ibcon#*before write, iclass 10, count 0 2006.281.07:43:52.50#ibcon#enter sib2, iclass 10, count 0 2006.281.07:43:52.50#ibcon#flushed, iclass 10, count 0 2006.281.07:43:52.50#ibcon#about to write, iclass 10, count 0 2006.281.07:43:52.50#ibcon#wrote, iclass 10, count 0 2006.281.07:43:52.50#ibcon#about to read 3, iclass 10, count 0 2006.281.07:43:52.54#ibcon#read 3, iclass 10, count 0 2006.281.07:43:52.54#ibcon#about to read 4, iclass 10, count 0 2006.281.07:43:52.54#ibcon#read 4, iclass 10, count 0 2006.281.07:43:52.54#ibcon#about to read 5, iclass 10, count 0 2006.281.07:43:52.54#ibcon#read 5, iclass 10, count 0 2006.281.07:43:52.54#ibcon#about to read 6, iclass 10, count 0 2006.281.07:43:52.54#ibcon#read 6, iclass 10, count 0 2006.281.07:43:52.54#ibcon#end of sib2, iclass 10, count 0 2006.281.07:43:52.54#ibcon#*after write, iclass 10, count 0 2006.281.07:43:52.54#ibcon#*before return 0, iclass 10, count 0 2006.281.07:43:52.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:43:52.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:43:52.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:43:52.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:43:52.54$vc4f8/vblo=2,640.99 2006.281.07:43:52.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:43:52.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:43:52.54#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:52.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:52.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:52.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:52.54#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:43:52.54#ibcon#first serial, iclass 16, count 0 2006.281.07:43:52.54#ibcon#enter sib2, iclass 16, count 0 2006.281.07:43:52.54#ibcon#flushed, iclass 16, count 0 2006.281.07:43:52.54#ibcon#about to write, iclass 16, count 0 2006.281.07:43:52.54#ibcon#wrote, iclass 16, count 0 2006.281.07:43:52.54#ibcon#about to read 3, iclass 16, count 0 2006.281.07:43:52.55#ibcon#read 3, iclass 16, count 0 2006.281.07:43:52.55#ibcon#about to read 4, iclass 16, count 0 2006.281.07:43:52.55#ibcon#read 4, iclass 16, count 0 2006.281.07:43:52.55#ibcon#about to read 5, iclass 16, count 0 2006.281.07:43:52.55#ibcon#read 5, iclass 16, count 0 2006.281.07:43:52.55#ibcon#about to read 6, iclass 16, count 0 2006.281.07:43:52.56#ibcon#read 6, iclass 16, count 0 2006.281.07:43:52.56#ibcon#end of sib2, iclass 16, count 0 2006.281.07:43:52.56#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:43:52.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:43:52.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:43:52.56#ibcon#*before write, iclass 16, count 0 2006.281.07:43:52.56#ibcon#enter sib2, iclass 16, count 0 2006.281.07:43:52.56#ibcon#flushed, iclass 16, count 0 2006.281.07:43:52.56#ibcon#about to write, iclass 16, count 0 2006.281.07:43:52.56#ibcon#wrote, iclass 16, count 0 2006.281.07:43:52.56#ibcon#about to read 3, iclass 16, count 0 2006.281.07:43:52.60#ibcon#read 3, iclass 16, count 0 2006.281.07:43:52.60#ibcon#about to read 4, iclass 16, count 0 2006.281.07:43:52.60#ibcon#read 4, iclass 16, count 0 2006.281.07:43:52.60#ibcon#about to read 5, iclass 16, count 0 2006.281.07:43:52.60#ibcon#read 5, iclass 16, count 0 2006.281.07:43:52.60#ibcon#about to read 6, iclass 16, count 0 2006.281.07:43:52.60#ibcon#read 6, iclass 16, count 0 2006.281.07:43:52.60#ibcon#end of sib2, iclass 16, count 0 2006.281.07:43:52.60#ibcon#*after write, iclass 16, count 0 2006.281.07:43:52.60#ibcon#*before return 0, iclass 16, count 0 2006.281.07:43:52.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:52.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:43:52.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:43:52.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:43:52.60$vc4f8/vb=2,5 2006.281.07:43:52.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.07:43:52.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.07:43:52.60#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:52.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:52.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:52.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:52.66#ibcon#enter wrdev, iclass 18, count 2 2006.281.07:43:52.66#ibcon#first serial, iclass 18, count 2 2006.281.07:43:52.66#ibcon#enter sib2, iclass 18, count 2 2006.281.07:43:52.66#ibcon#flushed, iclass 18, count 2 2006.281.07:43:52.66#ibcon#about to write, iclass 18, count 2 2006.281.07:43:52.66#ibcon#wrote, iclass 18, count 2 2006.281.07:43:52.66#ibcon#about to read 3, iclass 18, count 2 2006.281.07:43:52.68#ibcon#read 3, iclass 18, count 2 2006.281.07:43:52.68#ibcon#about to read 4, iclass 18, count 2 2006.281.07:43:52.68#ibcon#read 4, iclass 18, count 2 2006.281.07:43:52.68#ibcon#about to read 5, iclass 18, count 2 2006.281.07:43:52.68#ibcon#read 5, iclass 18, count 2 2006.281.07:43:52.68#ibcon#about to read 6, iclass 18, count 2 2006.281.07:43:52.68#ibcon#read 6, iclass 18, count 2 2006.281.07:43:52.68#ibcon#end of sib2, iclass 18, count 2 2006.281.07:43:52.68#ibcon#*mode == 0, iclass 18, count 2 2006.281.07:43:52.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.07:43:52.68#ibcon#[27=AT02-05\r\n] 2006.281.07:43:52.68#ibcon#*before write, iclass 18, count 2 2006.281.07:43:52.68#ibcon#enter sib2, iclass 18, count 2 2006.281.07:43:52.68#ibcon#flushed, iclass 18, count 2 2006.281.07:43:52.68#ibcon#about to write, iclass 18, count 2 2006.281.07:43:52.68#ibcon#wrote, iclass 18, count 2 2006.281.07:43:52.68#ibcon#about to read 3, iclass 18, count 2 2006.281.07:43:52.71#ibcon#read 3, iclass 18, count 2 2006.281.07:43:52.71#ibcon#about to read 4, iclass 18, count 2 2006.281.07:43:52.71#ibcon#read 4, iclass 18, count 2 2006.281.07:43:52.71#ibcon#about to read 5, iclass 18, count 2 2006.281.07:43:52.71#ibcon#read 5, iclass 18, count 2 2006.281.07:43:52.71#ibcon#about to read 6, iclass 18, count 2 2006.281.07:43:52.71#ibcon#read 6, iclass 18, count 2 2006.281.07:43:52.71#ibcon#end of sib2, iclass 18, count 2 2006.281.07:43:52.71#ibcon#*after write, iclass 18, count 2 2006.281.07:43:52.71#ibcon#*before return 0, iclass 18, count 2 2006.281.07:43:52.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:52.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:43:52.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.07:43:52.71#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:52.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:52.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:52.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:52.83#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:43:52.83#ibcon#first serial, iclass 18, count 0 2006.281.07:43:52.83#ibcon#enter sib2, iclass 18, count 0 2006.281.07:43:52.83#ibcon#flushed, iclass 18, count 0 2006.281.07:43:52.83#ibcon#about to write, iclass 18, count 0 2006.281.07:43:52.83#ibcon#wrote, iclass 18, count 0 2006.281.07:43:52.83#ibcon#about to read 3, iclass 18, count 0 2006.281.07:43:52.85#ibcon#read 3, iclass 18, count 0 2006.281.07:43:52.85#ibcon#about to read 4, iclass 18, count 0 2006.281.07:43:52.85#ibcon#read 4, iclass 18, count 0 2006.281.07:43:52.85#ibcon#about to read 5, iclass 18, count 0 2006.281.07:43:52.85#ibcon#read 5, iclass 18, count 0 2006.281.07:43:52.85#ibcon#about to read 6, iclass 18, count 0 2006.281.07:43:52.85#ibcon#read 6, iclass 18, count 0 2006.281.07:43:52.85#ibcon#end of sib2, iclass 18, count 0 2006.281.07:43:52.85#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:43:52.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:43:52.85#ibcon#[27=USB\r\n] 2006.281.07:43:52.85#ibcon#*before write, iclass 18, count 0 2006.281.07:43:52.85#ibcon#enter sib2, iclass 18, count 0 2006.281.07:43:52.85#ibcon#flushed, iclass 18, count 0 2006.281.07:43:52.85#ibcon#about to write, iclass 18, count 0 2006.281.07:43:52.85#ibcon#wrote, iclass 18, count 0 2006.281.07:43:52.85#ibcon#about to read 3, iclass 18, count 0 2006.281.07:43:52.88#ibcon#read 3, iclass 18, count 0 2006.281.07:43:52.88#ibcon#about to read 4, iclass 18, count 0 2006.281.07:43:52.88#ibcon#read 4, iclass 18, count 0 2006.281.07:43:52.88#ibcon#about to read 5, iclass 18, count 0 2006.281.07:43:52.88#ibcon#read 5, iclass 18, count 0 2006.281.07:43:52.88#ibcon#about to read 6, iclass 18, count 0 2006.281.07:43:52.88#ibcon#read 6, iclass 18, count 0 2006.281.07:43:52.88#ibcon#end of sib2, iclass 18, count 0 2006.281.07:43:52.88#ibcon#*after write, iclass 18, count 0 2006.281.07:43:52.88#ibcon#*before return 0, iclass 18, count 0 2006.281.07:43:52.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:52.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:43:52.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:43:52.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:43:52.88$vc4f8/vblo=3,656.99 2006.281.07:43:52.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:43:52.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:43:52.88#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:52.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:52.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:52.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:52.88#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:43:52.88#ibcon#first serial, iclass 20, count 0 2006.281.07:43:52.88#ibcon#enter sib2, iclass 20, count 0 2006.281.07:43:52.88#ibcon#flushed, iclass 20, count 0 2006.281.07:43:52.88#ibcon#about to write, iclass 20, count 0 2006.281.07:43:52.88#ibcon#wrote, iclass 20, count 0 2006.281.07:43:52.88#ibcon#about to read 3, iclass 20, count 0 2006.281.07:43:52.90#ibcon#read 3, iclass 20, count 0 2006.281.07:43:52.90#ibcon#about to read 4, iclass 20, count 0 2006.281.07:43:52.90#ibcon#read 4, iclass 20, count 0 2006.281.07:43:52.90#ibcon#about to read 5, iclass 20, count 0 2006.281.07:43:52.90#ibcon#read 5, iclass 20, count 0 2006.281.07:43:52.90#ibcon#about to read 6, iclass 20, count 0 2006.281.07:43:52.90#ibcon#read 6, iclass 20, count 0 2006.281.07:43:52.90#ibcon#end of sib2, iclass 20, count 0 2006.281.07:43:52.90#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:43:52.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:43:52.90#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:43:52.90#ibcon#*before write, iclass 20, count 0 2006.281.07:43:52.90#ibcon#enter sib2, iclass 20, count 0 2006.281.07:43:52.90#ibcon#flushed, iclass 20, count 0 2006.281.07:43:52.90#ibcon#about to write, iclass 20, count 0 2006.281.07:43:52.90#ibcon#wrote, iclass 20, count 0 2006.281.07:43:52.90#ibcon#about to read 3, iclass 20, count 0 2006.281.07:43:52.95#ibcon#read 3, iclass 20, count 0 2006.281.07:43:52.95#ibcon#about to read 4, iclass 20, count 0 2006.281.07:43:52.95#ibcon#read 4, iclass 20, count 0 2006.281.07:43:52.95#ibcon#about to read 5, iclass 20, count 0 2006.281.07:43:52.95#ibcon#read 5, iclass 20, count 0 2006.281.07:43:52.95#ibcon#about to read 6, iclass 20, count 0 2006.281.07:43:52.95#ibcon#read 6, iclass 20, count 0 2006.281.07:43:52.95#ibcon#end of sib2, iclass 20, count 0 2006.281.07:43:52.95#ibcon#*after write, iclass 20, count 0 2006.281.07:43:52.95#ibcon#*before return 0, iclass 20, count 0 2006.281.07:43:52.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:52.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:43:52.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:43:52.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:43:52.95$vc4f8/vb=3,4 2006.281.07:43:52.95#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:43:52.95#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:43:52.95#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:52.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:52.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:52.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:52.99#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:43:52.99#ibcon#first serial, iclass 22, count 2 2006.281.07:43:52.99#ibcon#enter sib2, iclass 22, count 2 2006.281.07:43:52.99#ibcon#flushed, iclass 22, count 2 2006.281.07:43:52.99#ibcon#about to write, iclass 22, count 2 2006.281.07:43:52.99#ibcon#wrote, iclass 22, count 2 2006.281.07:43:52.99#ibcon#about to read 3, iclass 22, count 2 2006.281.07:43:53.02#ibcon#read 3, iclass 22, count 2 2006.281.07:43:53.02#ibcon#about to read 4, iclass 22, count 2 2006.281.07:43:53.02#ibcon#read 4, iclass 22, count 2 2006.281.07:43:53.02#ibcon#about to read 5, iclass 22, count 2 2006.281.07:43:53.02#ibcon#read 5, iclass 22, count 2 2006.281.07:43:53.02#ibcon#about to read 6, iclass 22, count 2 2006.281.07:43:53.02#ibcon#read 6, iclass 22, count 2 2006.281.07:43:53.02#ibcon#end of sib2, iclass 22, count 2 2006.281.07:43:53.02#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:43:53.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:43:53.02#ibcon#[27=AT03-04\r\n] 2006.281.07:43:53.02#ibcon#*before write, iclass 22, count 2 2006.281.07:43:53.02#ibcon#enter sib2, iclass 22, count 2 2006.281.07:43:53.02#ibcon#flushed, iclass 22, count 2 2006.281.07:43:53.02#ibcon#about to write, iclass 22, count 2 2006.281.07:43:53.02#ibcon#wrote, iclass 22, count 2 2006.281.07:43:53.02#ibcon#about to read 3, iclass 22, count 2 2006.281.07:43:53.05#ibcon#read 3, iclass 22, count 2 2006.281.07:43:53.05#ibcon#about to read 4, iclass 22, count 2 2006.281.07:43:53.05#ibcon#read 4, iclass 22, count 2 2006.281.07:43:53.05#ibcon#about to read 5, iclass 22, count 2 2006.281.07:43:53.05#ibcon#read 5, iclass 22, count 2 2006.281.07:43:53.05#ibcon#about to read 6, iclass 22, count 2 2006.281.07:43:53.05#ibcon#read 6, iclass 22, count 2 2006.281.07:43:53.05#ibcon#end of sib2, iclass 22, count 2 2006.281.07:43:53.05#ibcon#*after write, iclass 22, count 2 2006.281.07:43:53.05#ibcon#*before return 0, iclass 22, count 2 2006.281.07:43:53.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:53.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:43:53.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:43:53.05#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:53.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:53.17#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:53.17#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:53.17#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:43:53.17#ibcon#first serial, iclass 22, count 0 2006.281.07:43:53.17#ibcon#enter sib2, iclass 22, count 0 2006.281.07:43:53.17#ibcon#flushed, iclass 22, count 0 2006.281.07:43:53.17#ibcon#about to write, iclass 22, count 0 2006.281.07:43:53.17#ibcon#wrote, iclass 22, count 0 2006.281.07:43:53.17#ibcon#about to read 3, iclass 22, count 0 2006.281.07:43:53.19#ibcon#read 3, iclass 22, count 0 2006.281.07:43:53.19#ibcon#about to read 4, iclass 22, count 0 2006.281.07:43:53.19#ibcon#read 4, iclass 22, count 0 2006.281.07:43:53.19#ibcon#about to read 5, iclass 22, count 0 2006.281.07:43:53.19#ibcon#read 5, iclass 22, count 0 2006.281.07:43:53.19#ibcon#about to read 6, iclass 22, count 0 2006.281.07:43:53.19#ibcon#read 6, iclass 22, count 0 2006.281.07:43:53.19#ibcon#end of sib2, iclass 22, count 0 2006.281.07:43:53.19#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:43:53.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:43:53.19#ibcon#[27=USB\r\n] 2006.281.07:43:53.19#ibcon#*before write, iclass 22, count 0 2006.281.07:43:53.19#ibcon#enter sib2, iclass 22, count 0 2006.281.07:43:53.19#ibcon#flushed, iclass 22, count 0 2006.281.07:43:53.19#ibcon#about to write, iclass 22, count 0 2006.281.07:43:53.19#ibcon#wrote, iclass 22, count 0 2006.281.07:43:53.19#ibcon#about to read 3, iclass 22, count 0 2006.281.07:43:53.22#ibcon#read 3, iclass 22, count 0 2006.281.07:43:53.22#ibcon#about to read 4, iclass 22, count 0 2006.281.07:43:53.22#ibcon#read 4, iclass 22, count 0 2006.281.07:43:53.23#ibcon#about to read 5, iclass 22, count 0 2006.281.07:43:53.23#ibcon#read 5, iclass 22, count 0 2006.281.07:43:53.23#ibcon#about to read 6, iclass 22, count 0 2006.281.07:43:53.23#ibcon#read 6, iclass 22, count 0 2006.281.07:43:53.23#ibcon#end of sib2, iclass 22, count 0 2006.281.07:43:53.23#ibcon#*after write, iclass 22, count 0 2006.281.07:43:53.23#ibcon#*before return 0, iclass 22, count 0 2006.281.07:43:53.23#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:53.23#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:43:53.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:43:53.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:43:53.23$vc4f8/vblo=4,712.99 2006.281.07:43:53.23#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:43:53.23#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:43:53.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:53.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:53.23#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:53.23#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:53.23#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:43:53.23#ibcon#first serial, iclass 24, count 0 2006.281.07:43:53.23#ibcon#enter sib2, iclass 24, count 0 2006.281.07:43:53.23#ibcon#flushed, iclass 24, count 0 2006.281.07:43:53.23#ibcon#about to write, iclass 24, count 0 2006.281.07:43:53.23#ibcon#wrote, iclass 24, count 0 2006.281.07:43:53.23#ibcon#about to read 3, iclass 24, count 0 2006.281.07:43:53.24#ibcon#read 3, iclass 24, count 0 2006.281.07:43:53.24#ibcon#about to read 4, iclass 24, count 0 2006.281.07:43:53.24#ibcon#read 4, iclass 24, count 0 2006.281.07:43:53.24#ibcon#about to read 5, iclass 24, count 0 2006.281.07:43:53.24#ibcon#read 5, iclass 24, count 0 2006.281.07:43:53.24#ibcon#about to read 6, iclass 24, count 0 2006.281.07:43:53.24#ibcon#read 6, iclass 24, count 0 2006.281.07:43:53.24#ibcon#end of sib2, iclass 24, count 0 2006.281.07:43:53.24#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:43:53.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:43:53.27#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:43:53.27#ibcon#*before write, iclass 24, count 0 2006.281.07:43:53.27#ibcon#enter sib2, iclass 24, count 0 2006.281.07:43:53.27#ibcon#flushed, iclass 24, count 0 2006.281.07:43:53.27#ibcon#about to write, iclass 24, count 0 2006.281.07:43:53.27#ibcon#wrote, iclass 24, count 0 2006.281.07:43:53.27#ibcon#about to read 3, iclass 24, count 0 2006.281.07:43:53.30#ibcon#read 3, iclass 24, count 0 2006.281.07:43:53.30#ibcon#about to read 4, iclass 24, count 0 2006.281.07:43:53.30#ibcon#read 4, iclass 24, count 0 2006.281.07:43:53.30#ibcon#about to read 5, iclass 24, count 0 2006.281.07:43:53.30#ibcon#read 5, iclass 24, count 0 2006.281.07:43:53.30#ibcon#about to read 6, iclass 24, count 0 2006.281.07:43:53.30#ibcon#read 6, iclass 24, count 0 2006.281.07:43:53.30#ibcon#end of sib2, iclass 24, count 0 2006.281.07:43:53.30#ibcon#*after write, iclass 24, count 0 2006.281.07:43:53.30#ibcon#*before return 0, iclass 24, count 0 2006.281.07:43:53.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:53.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:43:53.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:43:53.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:43:53.30$vc4f8/vb=4,4 2006.281.07:43:53.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:43:53.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:43:53.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:53.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:53.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:53.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:53.36#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:43:53.36#ibcon#first serial, iclass 26, count 2 2006.281.07:43:53.36#ibcon#enter sib2, iclass 26, count 2 2006.281.07:43:53.36#ibcon#flushed, iclass 26, count 2 2006.281.07:43:53.36#ibcon#about to write, iclass 26, count 2 2006.281.07:43:53.36#ibcon#wrote, iclass 26, count 2 2006.281.07:43:53.36#ibcon#about to read 3, iclass 26, count 2 2006.281.07:43:53.37#ibcon#read 3, iclass 26, count 2 2006.281.07:43:53.37#ibcon#about to read 4, iclass 26, count 2 2006.281.07:43:53.37#ibcon#read 4, iclass 26, count 2 2006.281.07:43:53.37#ibcon#about to read 5, iclass 26, count 2 2006.281.07:43:53.37#ibcon#read 5, iclass 26, count 2 2006.281.07:43:53.37#ibcon#about to read 6, iclass 26, count 2 2006.281.07:43:53.37#ibcon#read 6, iclass 26, count 2 2006.281.07:43:53.37#ibcon#end of sib2, iclass 26, count 2 2006.281.07:43:53.37#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:43:53.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:43:53.37#ibcon#[27=AT04-04\r\n] 2006.281.07:43:53.37#ibcon#*before write, iclass 26, count 2 2006.281.07:43:53.37#ibcon#enter sib2, iclass 26, count 2 2006.281.07:43:53.37#ibcon#flushed, iclass 26, count 2 2006.281.07:43:53.37#ibcon#about to write, iclass 26, count 2 2006.281.07:43:53.37#ibcon#wrote, iclass 26, count 2 2006.281.07:43:53.37#ibcon#about to read 3, iclass 26, count 2 2006.281.07:43:53.40#ibcon#read 3, iclass 26, count 2 2006.281.07:43:53.40#ibcon#about to read 4, iclass 26, count 2 2006.281.07:43:53.40#ibcon#read 4, iclass 26, count 2 2006.281.07:43:53.40#ibcon#about to read 5, iclass 26, count 2 2006.281.07:43:53.40#ibcon#read 5, iclass 26, count 2 2006.281.07:43:53.40#ibcon#about to read 6, iclass 26, count 2 2006.281.07:43:53.40#ibcon#read 6, iclass 26, count 2 2006.281.07:43:53.40#ibcon#end of sib2, iclass 26, count 2 2006.281.07:43:53.40#ibcon#*after write, iclass 26, count 2 2006.281.07:43:53.40#ibcon#*before return 0, iclass 26, count 2 2006.281.07:43:53.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:53.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:43:53.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:43:53.40#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:53.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:53.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:53.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:53.52#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:43:53.52#ibcon#first serial, iclass 26, count 0 2006.281.07:43:53.52#ibcon#enter sib2, iclass 26, count 0 2006.281.07:43:53.52#ibcon#flushed, iclass 26, count 0 2006.281.07:43:53.52#ibcon#about to write, iclass 26, count 0 2006.281.07:43:53.52#ibcon#wrote, iclass 26, count 0 2006.281.07:43:53.52#ibcon#about to read 3, iclass 26, count 0 2006.281.07:43:53.54#ibcon#read 3, iclass 26, count 0 2006.281.07:43:53.54#ibcon#about to read 4, iclass 26, count 0 2006.281.07:43:53.54#ibcon#read 4, iclass 26, count 0 2006.281.07:43:53.54#ibcon#about to read 5, iclass 26, count 0 2006.281.07:43:53.54#ibcon#read 5, iclass 26, count 0 2006.281.07:43:53.54#ibcon#about to read 6, iclass 26, count 0 2006.281.07:43:53.54#ibcon#read 6, iclass 26, count 0 2006.281.07:43:53.54#ibcon#end of sib2, iclass 26, count 0 2006.281.07:43:53.54#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:43:53.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:43:53.54#ibcon#[27=USB\r\n] 2006.281.07:43:53.54#ibcon#*before write, iclass 26, count 0 2006.281.07:43:53.54#ibcon#enter sib2, iclass 26, count 0 2006.281.07:43:53.54#ibcon#flushed, iclass 26, count 0 2006.281.07:43:53.54#ibcon#about to write, iclass 26, count 0 2006.281.07:43:53.54#ibcon#wrote, iclass 26, count 0 2006.281.07:43:53.54#ibcon#about to read 3, iclass 26, count 0 2006.281.07:43:53.57#ibcon#read 3, iclass 26, count 0 2006.281.07:43:53.57#ibcon#about to read 4, iclass 26, count 0 2006.281.07:43:53.57#ibcon#read 4, iclass 26, count 0 2006.281.07:43:53.57#ibcon#about to read 5, iclass 26, count 0 2006.281.07:43:53.57#ibcon#read 5, iclass 26, count 0 2006.281.07:43:53.57#ibcon#about to read 6, iclass 26, count 0 2006.281.07:43:53.57#ibcon#read 6, iclass 26, count 0 2006.281.07:43:53.57#ibcon#end of sib2, iclass 26, count 0 2006.281.07:43:53.57#ibcon#*after write, iclass 26, count 0 2006.281.07:43:53.57#ibcon#*before return 0, iclass 26, count 0 2006.281.07:43:53.57#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:53.57#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:43:53.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:43:53.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:43:53.57$vc4f8/vblo=5,744.99 2006.281.07:43:53.57#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:43:53.57#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:43:53.57#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:53.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:53.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:53.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:53.57#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:43:53.57#ibcon#first serial, iclass 28, count 0 2006.281.07:43:53.57#ibcon#enter sib2, iclass 28, count 0 2006.281.07:43:53.57#ibcon#flushed, iclass 28, count 0 2006.281.07:43:53.57#ibcon#about to write, iclass 28, count 0 2006.281.07:43:53.57#ibcon#wrote, iclass 28, count 0 2006.281.07:43:53.57#ibcon#about to read 3, iclass 28, count 0 2006.281.07:43:53.59#ibcon#read 3, iclass 28, count 0 2006.281.07:43:53.59#ibcon#about to read 4, iclass 28, count 0 2006.281.07:43:53.59#ibcon#read 4, iclass 28, count 0 2006.281.07:43:53.59#ibcon#about to read 5, iclass 28, count 0 2006.281.07:43:53.59#ibcon#read 5, iclass 28, count 0 2006.281.07:43:53.59#ibcon#about to read 6, iclass 28, count 0 2006.281.07:43:53.59#ibcon#read 6, iclass 28, count 0 2006.281.07:43:53.59#ibcon#end of sib2, iclass 28, count 0 2006.281.07:43:53.59#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:43:53.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:43:53.59#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:43:53.59#ibcon#*before write, iclass 28, count 0 2006.281.07:43:53.59#ibcon#enter sib2, iclass 28, count 0 2006.281.07:43:53.59#ibcon#flushed, iclass 28, count 0 2006.281.07:43:53.59#ibcon#about to write, iclass 28, count 0 2006.281.07:43:53.59#ibcon#wrote, iclass 28, count 0 2006.281.07:43:53.59#ibcon#about to read 3, iclass 28, count 0 2006.281.07:43:53.64#ibcon#read 3, iclass 28, count 0 2006.281.07:43:53.64#ibcon#about to read 4, iclass 28, count 0 2006.281.07:43:53.64#ibcon#read 4, iclass 28, count 0 2006.281.07:43:53.64#ibcon#about to read 5, iclass 28, count 0 2006.281.07:43:53.64#ibcon#read 5, iclass 28, count 0 2006.281.07:43:53.64#ibcon#about to read 6, iclass 28, count 0 2006.281.07:43:53.64#ibcon#read 6, iclass 28, count 0 2006.281.07:43:53.64#ibcon#end of sib2, iclass 28, count 0 2006.281.07:43:53.64#ibcon#*after write, iclass 28, count 0 2006.281.07:43:53.64#ibcon#*before return 0, iclass 28, count 0 2006.281.07:43:53.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:53.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:43:53.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:43:53.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:43:53.64$vc4f8/vb=5,4 2006.281.07:43:53.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:43:53.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:43:53.64#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:53.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:53.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:53.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:53.68#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:43:53.68#ibcon#first serial, iclass 30, count 2 2006.281.07:43:53.68#ibcon#enter sib2, iclass 30, count 2 2006.281.07:43:53.68#ibcon#flushed, iclass 30, count 2 2006.281.07:43:53.68#ibcon#about to write, iclass 30, count 2 2006.281.07:43:53.68#ibcon#wrote, iclass 30, count 2 2006.281.07:43:53.68#ibcon#about to read 3, iclass 30, count 2 2006.281.07:43:53.70#ibcon#read 3, iclass 30, count 2 2006.281.07:43:53.70#ibcon#about to read 4, iclass 30, count 2 2006.281.07:43:53.70#ibcon#read 4, iclass 30, count 2 2006.281.07:43:53.70#ibcon#about to read 5, iclass 30, count 2 2006.281.07:43:53.70#ibcon#read 5, iclass 30, count 2 2006.281.07:43:53.70#ibcon#about to read 6, iclass 30, count 2 2006.281.07:43:53.70#ibcon#read 6, iclass 30, count 2 2006.281.07:43:53.70#ibcon#end of sib2, iclass 30, count 2 2006.281.07:43:53.70#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:43:53.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:43:53.70#ibcon#[27=AT05-04\r\n] 2006.281.07:43:53.70#ibcon#*before write, iclass 30, count 2 2006.281.07:43:53.70#ibcon#enter sib2, iclass 30, count 2 2006.281.07:43:53.70#ibcon#flushed, iclass 30, count 2 2006.281.07:43:53.70#ibcon#about to write, iclass 30, count 2 2006.281.07:43:53.70#ibcon#wrote, iclass 30, count 2 2006.281.07:43:53.70#ibcon#about to read 3, iclass 30, count 2 2006.281.07:43:53.73#ibcon#read 3, iclass 30, count 2 2006.281.07:43:53.73#ibcon#about to read 4, iclass 30, count 2 2006.281.07:43:53.73#ibcon#read 4, iclass 30, count 2 2006.281.07:43:53.73#ibcon#about to read 5, iclass 30, count 2 2006.281.07:43:53.73#ibcon#read 5, iclass 30, count 2 2006.281.07:43:53.73#ibcon#about to read 6, iclass 30, count 2 2006.281.07:43:53.73#ibcon#read 6, iclass 30, count 2 2006.281.07:43:53.73#ibcon#end of sib2, iclass 30, count 2 2006.281.07:43:53.73#ibcon#*after write, iclass 30, count 2 2006.281.07:43:53.73#ibcon#*before return 0, iclass 30, count 2 2006.281.07:43:53.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:53.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:43:53.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:43:53.73#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:53.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:53.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:53.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:53.85#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:43:53.85#ibcon#first serial, iclass 30, count 0 2006.281.07:43:53.85#ibcon#enter sib2, iclass 30, count 0 2006.281.07:43:53.85#ibcon#flushed, iclass 30, count 0 2006.281.07:43:53.85#ibcon#about to write, iclass 30, count 0 2006.281.07:43:53.85#ibcon#wrote, iclass 30, count 0 2006.281.07:43:53.85#ibcon#about to read 3, iclass 30, count 0 2006.281.07:43:53.87#ibcon#read 3, iclass 30, count 0 2006.281.07:43:53.87#ibcon#about to read 4, iclass 30, count 0 2006.281.07:43:53.87#ibcon#read 4, iclass 30, count 0 2006.281.07:43:53.87#ibcon#about to read 5, iclass 30, count 0 2006.281.07:43:53.87#ibcon#read 5, iclass 30, count 0 2006.281.07:43:53.87#ibcon#about to read 6, iclass 30, count 0 2006.281.07:43:53.87#ibcon#read 6, iclass 30, count 0 2006.281.07:43:53.87#ibcon#end of sib2, iclass 30, count 0 2006.281.07:43:53.87#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:43:53.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:43:53.87#ibcon#[27=USB\r\n] 2006.281.07:43:53.87#ibcon#*before write, iclass 30, count 0 2006.281.07:43:53.87#ibcon#enter sib2, iclass 30, count 0 2006.281.07:43:53.87#ibcon#flushed, iclass 30, count 0 2006.281.07:43:53.87#ibcon#about to write, iclass 30, count 0 2006.281.07:43:53.87#ibcon#wrote, iclass 30, count 0 2006.281.07:43:53.87#ibcon#about to read 3, iclass 30, count 0 2006.281.07:43:53.90#ibcon#read 3, iclass 30, count 0 2006.281.07:43:53.90#ibcon#about to read 4, iclass 30, count 0 2006.281.07:43:53.90#ibcon#read 4, iclass 30, count 0 2006.281.07:43:53.90#ibcon#about to read 5, iclass 30, count 0 2006.281.07:43:53.90#ibcon#read 5, iclass 30, count 0 2006.281.07:43:53.90#ibcon#about to read 6, iclass 30, count 0 2006.281.07:43:53.90#ibcon#read 6, iclass 30, count 0 2006.281.07:43:53.90#ibcon#end of sib2, iclass 30, count 0 2006.281.07:43:53.90#ibcon#*after write, iclass 30, count 0 2006.281.07:43:53.90#ibcon#*before return 0, iclass 30, count 0 2006.281.07:43:53.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:53.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:43:53.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:43:53.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:43:53.90$vc4f8/vblo=6,752.99 2006.281.07:43:53.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:43:53.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:43:53.90#ibcon#ireg 17 cls_cnt 0 2006.281.07:43:53.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:53.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:53.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:53.90#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:43:53.90#ibcon#first serial, iclass 32, count 0 2006.281.07:43:53.90#ibcon#enter sib2, iclass 32, count 0 2006.281.07:43:53.90#ibcon#flushed, iclass 32, count 0 2006.281.07:43:53.90#ibcon#about to write, iclass 32, count 0 2006.281.07:43:53.90#ibcon#wrote, iclass 32, count 0 2006.281.07:43:53.90#ibcon#about to read 3, iclass 32, count 0 2006.281.07:43:53.92#ibcon#read 3, iclass 32, count 0 2006.281.07:43:53.92#ibcon#about to read 4, iclass 32, count 0 2006.281.07:43:53.92#ibcon#read 4, iclass 32, count 0 2006.281.07:43:53.92#ibcon#about to read 5, iclass 32, count 0 2006.281.07:43:53.92#ibcon#read 5, iclass 32, count 0 2006.281.07:43:53.92#ibcon#about to read 6, iclass 32, count 0 2006.281.07:43:53.92#ibcon#read 6, iclass 32, count 0 2006.281.07:43:53.92#ibcon#end of sib2, iclass 32, count 0 2006.281.07:43:53.92#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:43:53.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:43:53.92#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:43:53.92#ibcon#*before write, iclass 32, count 0 2006.281.07:43:53.92#ibcon#enter sib2, iclass 32, count 0 2006.281.07:43:53.92#ibcon#flushed, iclass 32, count 0 2006.281.07:43:53.92#ibcon#about to write, iclass 32, count 0 2006.281.07:43:53.92#ibcon#wrote, iclass 32, count 0 2006.281.07:43:53.92#ibcon#about to read 3, iclass 32, count 0 2006.281.07:43:53.97#ibcon#read 3, iclass 32, count 0 2006.281.07:43:53.97#ibcon#about to read 4, iclass 32, count 0 2006.281.07:43:53.97#ibcon#read 4, iclass 32, count 0 2006.281.07:43:53.97#ibcon#about to read 5, iclass 32, count 0 2006.281.07:43:53.97#ibcon#read 5, iclass 32, count 0 2006.281.07:43:53.97#ibcon#about to read 6, iclass 32, count 0 2006.281.07:43:53.97#ibcon#read 6, iclass 32, count 0 2006.281.07:43:53.97#ibcon#end of sib2, iclass 32, count 0 2006.281.07:43:53.97#ibcon#*after write, iclass 32, count 0 2006.281.07:43:53.97#ibcon#*before return 0, iclass 32, count 0 2006.281.07:43:53.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:53.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:43:53.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:43:53.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:43:53.97$vc4f8/vb=6,4 2006.281.07:43:53.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:43:53.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:43:53.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:43:53.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:54.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:54.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:54.01#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:43:54.01#ibcon#first serial, iclass 34, count 2 2006.281.07:43:54.01#ibcon#enter sib2, iclass 34, count 2 2006.281.07:43:54.01#ibcon#flushed, iclass 34, count 2 2006.281.07:43:54.01#ibcon#about to write, iclass 34, count 2 2006.281.07:43:54.01#ibcon#wrote, iclass 34, count 2 2006.281.07:43:54.01#ibcon#about to read 3, iclass 34, count 2 2006.281.07:43:54.03#ibcon#read 3, iclass 34, count 2 2006.281.07:43:54.03#ibcon#about to read 4, iclass 34, count 2 2006.281.07:43:54.03#ibcon#read 4, iclass 34, count 2 2006.281.07:43:54.03#ibcon#about to read 5, iclass 34, count 2 2006.281.07:43:54.03#ibcon#read 5, iclass 34, count 2 2006.281.07:43:54.03#ibcon#about to read 6, iclass 34, count 2 2006.281.07:43:54.03#ibcon#read 6, iclass 34, count 2 2006.281.07:43:54.03#ibcon#end of sib2, iclass 34, count 2 2006.281.07:43:54.03#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:43:54.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:43:54.03#ibcon#[27=AT06-04\r\n] 2006.281.07:43:54.03#ibcon#*before write, iclass 34, count 2 2006.281.07:43:54.03#ibcon#enter sib2, iclass 34, count 2 2006.281.07:43:54.03#ibcon#flushed, iclass 34, count 2 2006.281.07:43:54.03#ibcon#about to write, iclass 34, count 2 2006.281.07:43:54.03#ibcon#wrote, iclass 34, count 2 2006.281.07:43:54.03#ibcon#about to read 3, iclass 34, count 2 2006.281.07:43:54.06#ibcon#read 3, iclass 34, count 2 2006.281.07:43:54.06#ibcon#about to read 4, iclass 34, count 2 2006.281.07:43:54.06#ibcon#read 4, iclass 34, count 2 2006.281.07:43:54.06#ibcon#about to read 5, iclass 34, count 2 2006.281.07:43:54.06#ibcon#read 5, iclass 34, count 2 2006.281.07:43:54.06#ibcon#about to read 6, iclass 34, count 2 2006.281.07:43:54.06#ibcon#read 6, iclass 34, count 2 2006.281.07:43:54.06#ibcon#end of sib2, iclass 34, count 2 2006.281.07:43:54.06#ibcon#*after write, iclass 34, count 2 2006.281.07:43:54.06#ibcon#*before return 0, iclass 34, count 2 2006.281.07:43:54.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:54.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:43:54.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:43:54.06#ibcon#ireg 7 cls_cnt 0 2006.281.07:43:54.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:54.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:54.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:54.18#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:43:54.18#ibcon#first serial, iclass 34, count 0 2006.281.07:43:54.18#ibcon#enter sib2, iclass 34, count 0 2006.281.07:43:54.18#ibcon#flushed, iclass 34, count 0 2006.281.07:43:54.18#ibcon#about to write, iclass 34, count 0 2006.281.07:43:54.18#ibcon#wrote, iclass 34, count 0 2006.281.07:43:54.18#ibcon#about to read 3, iclass 34, count 0 2006.281.07:43:54.20#ibcon#read 3, iclass 34, count 0 2006.281.07:43:54.20#ibcon#about to read 4, iclass 34, count 0 2006.281.07:43:54.20#ibcon#read 4, iclass 34, count 0 2006.281.07:43:54.20#ibcon#about to read 5, iclass 34, count 0 2006.281.07:43:54.20#ibcon#read 5, iclass 34, count 0 2006.281.07:43:54.20#ibcon#about to read 6, iclass 34, count 0 2006.281.07:43:54.20#ibcon#read 6, iclass 34, count 0 2006.281.07:43:54.20#ibcon#end of sib2, iclass 34, count 0 2006.281.07:43:54.20#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:43:54.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:43:54.20#ibcon#[27=USB\r\n] 2006.281.07:43:54.20#ibcon#*before write, iclass 34, count 0 2006.281.07:43:54.20#ibcon#enter sib2, iclass 34, count 0 2006.281.07:43:54.20#ibcon#flushed, iclass 34, count 0 2006.281.07:43:54.20#ibcon#about to write, iclass 34, count 0 2006.281.07:43:54.20#ibcon#wrote, iclass 34, count 0 2006.281.07:43:54.20#ibcon#about to read 3, iclass 34, count 0 2006.281.07:43:54.23#ibcon#read 3, iclass 34, count 0 2006.281.07:43:54.23#ibcon#about to read 4, iclass 34, count 0 2006.281.07:43:54.23#ibcon#read 4, iclass 34, count 0 2006.281.07:43:54.23#ibcon#about to read 5, iclass 34, count 0 2006.281.07:43:54.23#ibcon#read 5, iclass 34, count 0 2006.281.07:43:54.23#ibcon#about to read 6, iclass 34, count 0 2006.281.07:43:54.23#ibcon#read 6, iclass 34, count 0 2006.281.07:43:54.23#ibcon#end of sib2, iclass 34, count 0 2006.281.07:43:54.23#ibcon#*after write, iclass 34, count 0 2006.281.07:43:54.23#ibcon#*before return 0, iclass 34, count 0 2006.281.07:43:54.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:54.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:43:54.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:43:54.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:43:54.23$vc4f8/vabw=wide 2006.281.07:43:54.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:43:54.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:43:54.23#ibcon#ireg 8 cls_cnt 0 2006.281.07:43:54.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:54.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:54.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:54.23#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:43:54.23#ibcon#first serial, iclass 36, count 0 2006.281.07:43:54.23#ibcon#enter sib2, iclass 36, count 0 2006.281.07:43:54.23#ibcon#flushed, iclass 36, count 0 2006.281.07:43:54.23#ibcon#about to write, iclass 36, count 0 2006.281.07:43:54.23#ibcon#wrote, iclass 36, count 0 2006.281.07:43:54.23#ibcon#about to read 3, iclass 36, count 0 2006.281.07:43:54.25#ibcon#read 3, iclass 36, count 0 2006.281.07:43:54.25#ibcon#about to read 4, iclass 36, count 0 2006.281.07:43:54.25#ibcon#read 4, iclass 36, count 0 2006.281.07:43:54.25#ibcon#about to read 5, iclass 36, count 0 2006.281.07:43:54.25#ibcon#read 5, iclass 36, count 0 2006.281.07:43:54.25#ibcon#about to read 6, iclass 36, count 0 2006.281.07:43:54.25#ibcon#read 6, iclass 36, count 0 2006.281.07:43:54.25#ibcon#end of sib2, iclass 36, count 0 2006.281.07:43:54.25#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:43:54.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:43:54.25#ibcon#[25=BW32\r\n] 2006.281.07:43:54.25#ibcon#*before write, iclass 36, count 0 2006.281.07:43:54.25#ibcon#enter sib2, iclass 36, count 0 2006.281.07:43:54.25#ibcon#flushed, iclass 36, count 0 2006.281.07:43:54.25#ibcon#about to write, iclass 36, count 0 2006.281.07:43:54.25#ibcon#wrote, iclass 36, count 0 2006.281.07:43:54.25#ibcon#about to read 3, iclass 36, count 0 2006.281.07:43:54.28#ibcon#read 3, iclass 36, count 0 2006.281.07:43:54.28#ibcon#about to read 4, iclass 36, count 0 2006.281.07:43:54.28#ibcon#read 4, iclass 36, count 0 2006.281.07:43:54.28#ibcon#about to read 5, iclass 36, count 0 2006.281.07:43:54.28#ibcon#read 5, iclass 36, count 0 2006.281.07:43:54.28#ibcon#about to read 6, iclass 36, count 0 2006.281.07:43:54.28#ibcon#read 6, iclass 36, count 0 2006.281.07:43:54.28#ibcon#end of sib2, iclass 36, count 0 2006.281.07:43:54.28#ibcon#*after write, iclass 36, count 0 2006.281.07:43:54.28#ibcon#*before return 0, iclass 36, count 0 2006.281.07:43:54.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:54.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:43:54.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:43:54.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:43:54.29$vc4f8/vbbw=wide 2006.281.07:43:54.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:43:54.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:43:54.29#ibcon#ireg 8 cls_cnt 0 2006.281.07:43:54.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:43:54.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:43:54.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:43:54.34#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:43:54.34#ibcon#first serial, iclass 38, count 0 2006.281.07:43:54.34#ibcon#enter sib2, iclass 38, count 0 2006.281.07:43:54.34#ibcon#flushed, iclass 38, count 0 2006.281.07:43:54.34#ibcon#about to write, iclass 38, count 0 2006.281.07:43:54.34#ibcon#wrote, iclass 38, count 0 2006.281.07:43:54.34#ibcon#about to read 3, iclass 38, count 0 2006.281.07:43:54.36#ibcon#read 3, iclass 38, count 0 2006.281.07:43:54.36#ibcon#about to read 4, iclass 38, count 0 2006.281.07:43:54.36#ibcon#read 4, iclass 38, count 0 2006.281.07:43:54.36#ibcon#about to read 5, iclass 38, count 0 2006.281.07:43:54.36#ibcon#read 5, iclass 38, count 0 2006.281.07:43:54.36#ibcon#about to read 6, iclass 38, count 0 2006.281.07:43:54.36#ibcon#read 6, iclass 38, count 0 2006.281.07:43:54.36#ibcon#end of sib2, iclass 38, count 0 2006.281.07:43:54.36#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:43:54.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:43:54.36#ibcon#[27=BW32\r\n] 2006.281.07:43:54.36#ibcon#*before write, iclass 38, count 0 2006.281.07:43:54.36#ibcon#enter sib2, iclass 38, count 0 2006.281.07:43:54.36#ibcon#flushed, iclass 38, count 0 2006.281.07:43:54.36#ibcon#about to write, iclass 38, count 0 2006.281.07:43:54.36#ibcon#wrote, iclass 38, count 0 2006.281.07:43:54.36#ibcon#about to read 3, iclass 38, count 0 2006.281.07:43:54.39#ibcon#read 3, iclass 38, count 0 2006.281.07:43:54.39#ibcon#about to read 4, iclass 38, count 0 2006.281.07:43:54.39#ibcon#read 4, iclass 38, count 0 2006.281.07:43:54.39#ibcon#about to read 5, iclass 38, count 0 2006.281.07:43:54.39#ibcon#read 5, iclass 38, count 0 2006.281.07:43:54.39#ibcon#about to read 6, iclass 38, count 0 2006.281.07:43:54.39#ibcon#read 6, iclass 38, count 0 2006.281.07:43:54.39#ibcon#end of sib2, iclass 38, count 0 2006.281.07:43:54.39#ibcon#*after write, iclass 38, count 0 2006.281.07:43:54.39#ibcon#*before return 0, iclass 38, count 0 2006.281.07:43:54.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:43:54.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:43:54.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:43:54.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:43:54.39$4f8m12a/ifd4f 2006.281.07:43:54.39$ifd4f/lo= 2006.281.07:43:54.39$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:43:54.39$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:43:54.39$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:43:54.39$ifd4f/patch= 2006.281.07:43:54.39$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:43:54.39$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:43:54.40$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:43:54.40$4f8m12a/"form=m,16.000,1:2 2006.281.07:43:54.40$4f8m12a/"tpicd 2006.281.07:43:54.40$4f8m12a/echo=off 2006.281.07:43:54.40$4f8m12a/xlog=off 2006.281.07:43:54.40:!2006.281.07:44:20 2006.281.07:44:03.14#trakl#Source acquired 2006.281.07:44:05.14#flagr#flagr/antenna,acquired 2006.281.07:44:20.01:preob 2006.281.07:44:21.14/onsource/TRACKING 2006.281.07:44:21.14:!2006.281.07:44:30 2006.281.07:44:30.00:data_valid=on 2006.281.07:44:30.00:midob 2006.281.07:44:30.14/onsource/TRACKING 2006.281.07:44:30.14/wx/21.02,1001.1,50 2006.281.07:44:30.26/cable/+6.4857E-03 2006.281.07:44:31.35/va/01,07,usb,yes,32,34 2006.281.07:44:31.35/va/02,06,usb,yes,30,31 2006.281.07:44:31.35/va/03,06,usb,yes,28,28 2006.281.07:44:31.35/va/04,06,usb,yes,31,33 2006.281.07:44:31.35/va/05,07,usb,yes,29,30 2006.281.07:44:31.35/va/06,06,usb,yes,28,28 2006.281.07:44:31.35/va/07,06,usb,yes,28,28 2006.281.07:44:31.35/va/08,06,usb,yes,30,30 2006.281.07:44:31.58/valo/01,532.99,yes,locked 2006.281.07:44:31.58/valo/02,572.99,yes,locked 2006.281.07:44:31.58/valo/03,672.99,yes,locked 2006.281.07:44:31.58/valo/04,832.99,yes,locked 2006.281.07:44:31.58/valo/05,652.99,yes,locked 2006.281.07:44:31.58/valo/06,772.99,yes,locked 2006.281.07:44:31.58/valo/07,832.99,yes,locked 2006.281.07:44:31.58/valo/08,852.99,yes,locked 2006.281.07:44:32.67/vb/01,04,usb,yes,30,29 2006.281.07:44:32.67/vb/02,05,usb,yes,28,29 2006.281.07:44:32.67/vb/03,04,usb,yes,28,32 2006.281.07:44:32.67/vb/04,04,usb,yes,29,29 2006.281.07:44:32.67/vb/05,04,usb,yes,27,31 2006.281.07:44:32.67/vb/06,04,usb,yes,28,31 2006.281.07:44:32.67/vb/07,04,usb,yes,30,30 2006.281.07:44:32.67/vb/08,04,usb,yes,28,31 2006.281.07:44:32.90/vblo/01,632.99,yes,locked 2006.281.07:44:32.90/vblo/02,640.99,yes,locked 2006.281.07:44:32.90/vblo/03,656.99,yes,locked 2006.281.07:44:32.90/vblo/04,712.99,yes,locked 2006.281.07:44:32.90/vblo/05,744.99,yes,locked 2006.281.07:44:32.90/vblo/06,752.99,yes,locked 2006.281.07:44:32.90/vblo/07,734.99,yes,locked 2006.281.07:44:32.90/vblo/08,744.99,yes,locked 2006.281.07:44:33.05/vabw/8 2006.281.07:44:33.20/vbbw/8 2006.281.07:44:33.29/xfe/off,on,12.2 2006.281.07:44:33.66/ifatt/23,28,28,28 2006.281.07:44:34.07/fmout-gps/S +3.10E-07 2006.281.07:44:34.10:!2006.281.07:45:30 2006.281.07:45:30.01:data_valid=off 2006.281.07:45:30.02:postob 2006.281.07:45:30.08/cable/+6.4864E-03 2006.281.07:45:30.08/wx/21.00,1001.2,51 2006.281.07:45:31.07/fmout-gps/S +3.10E-07 2006.281.07:45:31.08:scan_name=281-0746,k06281,60 2006.281.07:45:31.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.281.07:45:31.14#flagr#flagr/antenna,new-source 2006.281.07:45:32.14:checkk5 2006.281.07:45:32.91/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:45:33.35/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:45:33.78/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:45:34.20/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:45:34.66/chk_obsdata//k5ts1/T2810744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:45:35.04/chk_obsdata//k5ts2/T2810744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:45:35.66/chk_obsdata//k5ts3/T2810744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:45:36.09/chk_obsdata//k5ts4/T2810744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:45:36.93/k5log//k5ts1_log_newline 2006.281.07:45:37.72/k5log//k5ts2_log_newline 2006.281.07:45:38.50/k5log//k5ts3_log_newline 2006.281.07:45:39.58/k5log//k5ts4_log_newline 2006.281.07:45:39.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:45:39.60:4f8m12a=1 2006.281.07:45:39.60$4f8m12a/echo=on 2006.281.07:45:39.60$4f8m12a/pcalon 2006.281.07:45:39.60$pcalon/"no phase cal control is implemented here 2006.281.07:45:39.60$4f8m12a/"tpicd=stop 2006.281.07:45:39.60$4f8m12a/vc4f8 2006.281.07:45:39.60$vc4f8/valo=1,532.99 2006.281.07:45:39.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.07:45:39.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.07:45:39.61#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:39.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:39.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:39.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:39.61#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:45:39.61#ibcon#first serial, iclass 7, count 0 2006.281.07:45:39.61#ibcon#enter sib2, iclass 7, count 0 2006.281.07:45:39.61#ibcon#flushed, iclass 7, count 0 2006.281.07:45:39.61#ibcon#about to write, iclass 7, count 0 2006.281.07:45:39.61#ibcon#wrote, iclass 7, count 0 2006.281.07:45:39.61#ibcon#about to read 3, iclass 7, count 0 2006.281.07:45:39.62#ibcon#read 3, iclass 7, count 0 2006.281.07:45:39.62#ibcon#about to read 4, iclass 7, count 0 2006.281.07:45:39.62#ibcon#read 4, iclass 7, count 0 2006.281.07:45:39.62#ibcon#about to read 5, iclass 7, count 0 2006.281.07:45:39.62#ibcon#read 5, iclass 7, count 0 2006.281.07:45:39.62#ibcon#about to read 6, iclass 7, count 0 2006.281.07:45:39.62#ibcon#read 6, iclass 7, count 0 2006.281.07:45:39.62#ibcon#end of sib2, iclass 7, count 0 2006.281.07:45:39.62#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:45:39.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:45:39.62#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:45:39.62#ibcon#*before write, iclass 7, count 0 2006.281.07:45:39.62#ibcon#enter sib2, iclass 7, count 0 2006.281.07:45:39.62#ibcon#flushed, iclass 7, count 0 2006.281.07:45:39.62#ibcon#about to write, iclass 7, count 0 2006.281.07:45:39.62#ibcon#wrote, iclass 7, count 0 2006.281.07:45:39.62#ibcon#about to read 3, iclass 7, count 0 2006.281.07:45:39.67#ibcon#read 3, iclass 7, count 0 2006.281.07:45:39.67#ibcon#about to read 4, iclass 7, count 0 2006.281.07:45:39.67#ibcon#read 4, iclass 7, count 0 2006.281.07:45:39.67#ibcon#about to read 5, iclass 7, count 0 2006.281.07:45:39.67#ibcon#read 5, iclass 7, count 0 2006.281.07:45:39.67#ibcon#about to read 6, iclass 7, count 0 2006.281.07:45:39.67#ibcon#read 6, iclass 7, count 0 2006.281.07:45:39.67#ibcon#end of sib2, iclass 7, count 0 2006.281.07:45:39.67#ibcon#*after write, iclass 7, count 0 2006.281.07:45:39.67#ibcon#*before return 0, iclass 7, count 0 2006.281.07:45:39.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:39.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:39.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:45:39.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:45:39.67$vc4f8/va=1,7 2006.281.07:45:39.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.07:45:39.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.07:45:39.67#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:39.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:39.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:39.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:39.67#ibcon#enter wrdev, iclass 11, count 2 2006.281.07:45:39.67#ibcon#first serial, iclass 11, count 2 2006.281.07:45:39.67#ibcon#enter sib2, iclass 11, count 2 2006.281.07:45:39.67#ibcon#flushed, iclass 11, count 2 2006.281.07:45:39.67#ibcon#about to write, iclass 11, count 2 2006.281.07:45:39.67#ibcon#wrote, iclass 11, count 2 2006.281.07:45:39.67#ibcon#about to read 3, iclass 11, count 2 2006.281.07:45:39.69#ibcon#read 3, iclass 11, count 2 2006.281.07:45:39.69#ibcon#about to read 4, iclass 11, count 2 2006.281.07:45:39.69#ibcon#read 4, iclass 11, count 2 2006.281.07:45:39.69#ibcon#about to read 5, iclass 11, count 2 2006.281.07:45:39.69#ibcon#read 5, iclass 11, count 2 2006.281.07:45:39.69#ibcon#about to read 6, iclass 11, count 2 2006.281.07:45:39.69#ibcon#read 6, iclass 11, count 2 2006.281.07:45:39.69#ibcon#end of sib2, iclass 11, count 2 2006.281.07:45:39.69#ibcon#*mode == 0, iclass 11, count 2 2006.281.07:45:39.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.07:45:39.69#ibcon#[25=AT01-07\r\n] 2006.281.07:45:39.69#ibcon#*before write, iclass 11, count 2 2006.281.07:45:39.69#ibcon#enter sib2, iclass 11, count 2 2006.281.07:45:39.69#ibcon#flushed, iclass 11, count 2 2006.281.07:45:39.69#ibcon#about to write, iclass 11, count 2 2006.281.07:45:39.69#ibcon#wrote, iclass 11, count 2 2006.281.07:45:39.69#ibcon#about to read 3, iclass 11, count 2 2006.281.07:45:39.72#ibcon#read 3, iclass 11, count 2 2006.281.07:45:39.72#ibcon#about to read 4, iclass 11, count 2 2006.281.07:45:39.72#ibcon#read 4, iclass 11, count 2 2006.281.07:45:39.72#ibcon#about to read 5, iclass 11, count 2 2006.281.07:45:39.72#ibcon#read 5, iclass 11, count 2 2006.281.07:45:39.72#ibcon#about to read 6, iclass 11, count 2 2006.281.07:45:39.72#ibcon#read 6, iclass 11, count 2 2006.281.07:45:39.72#ibcon#end of sib2, iclass 11, count 2 2006.281.07:45:39.72#ibcon#*after write, iclass 11, count 2 2006.281.07:45:39.72#ibcon#*before return 0, iclass 11, count 2 2006.281.07:45:39.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:39.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:39.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.07:45:39.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:39.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:39.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:39.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:39.84#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:45:39.84#ibcon#first serial, iclass 11, count 0 2006.281.07:45:39.84#ibcon#enter sib2, iclass 11, count 0 2006.281.07:45:39.84#ibcon#flushed, iclass 11, count 0 2006.281.07:45:39.84#ibcon#about to write, iclass 11, count 0 2006.281.07:45:39.84#ibcon#wrote, iclass 11, count 0 2006.281.07:45:39.84#ibcon#about to read 3, iclass 11, count 0 2006.281.07:45:39.86#ibcon#read 3, iclass 11, count 0 2006.281.07:45:39.86#ibcon#about to read 4, iclass 11, count 0 2006.281.07:45:39.86#ibcon#read 4, iclass 11, count 0 2006.281.07:45:39.86#ibcon#about to read 5, iclass 11, count 0 2006.281.07:45:39.86#ibcon#read 5, iclass 11, count 0 2006.281.07:45:39.86#ibcon#about to read 6, iclass 11, count 0 2006.281.07:45:39.86#ibcon#read 6, iclass 11, count 0 2006.281.07:45:39.86#ibcon#end of sib2, iclass 11, count 0 2006.281.07:45:39.86#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:45:39.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:45:39.86#ibcon#[25=USB\r\n] 2006.281.07:45:39.86#ibcon#*before write, iclass 11, count 0 2006.281.07:45:39.86#ibcon#enter sib2, iclass 11, count 0 2006.281.07:45:39.86#ibcon#flushed, iclass 11, count 0 2006.281.07:45:39.86#ibcon#about to write, iclass 11, count 0 2006.281.07:45:39.86#ibcon#wrote, iclass 11, count 0 2006.281.07:45:39.86#ibcon#about to read 3, iclass 11, count 0 2006.281.07:45:39.89#ibcon#read 3, iclass 11, count 0 2006.281.07:45:39.89#ibcon#about to read 4, iclass 11, count 0 2006.281.07:45:39.89#ibcon#read 4, iclass 11, count 0 2006.281.07:45:39.89#ibcon#about to read 5, iclass 11, count 0 2006.281.07:45:39.89#ibcon#read 5, iclass 11, count 0 2006.281.07:45:39.89#ibcon#about to read 6, iclass 11, count 0 2006.281.07:45:39.89#ibcon#read 6, iclass 11, count 0 2006.281.07:45:39.89#ibcon#end of sib2, iclass 11, count 0 2006.281.07:45:39.89#ibcon#*after write, iclass 11, count 0 2006.281.07:45:39.89#ibcon#*before return 0, iclass 11, count 0 2006.281.07:45:39.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:39.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:39.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:45:39.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:45:39.89$vc4f8/valo=2,572.99 2006.281.07:45:39.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.07:45:39.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.07:45:39.89#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:39.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:39.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:39.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:39.89#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:45:39.89#ibcon#first serial, iclass 13, count 0 2006.281.07:45:39.89#ibcon#enter sib2, iclass 13, count 0 2006.281.07:45:39.89#ibcon#flushed, iclass 13, count 0 2006.281.07:45:39.89#ibcon#about to write, iclass 13, count 0 2006.281.07:45:39.89#ibcon#wrote, iclass 13, count 0 2006.281.07:45:39.89#ibcon#about to read 3, iclass 13, count 0 2006.281.07:45:39.91#ibcon#read 3, iclass 13, count 0 2006.281.07:45:39.91#ibcon#about to read 4, iclass 13, count 0 2006.281.07:45:39.91#ibcon#read 4, iclass 13, count 0 2006.281.07:45:39.91#ibcon#about to read 5, iclass 13, count 0 2006.281.07:45:39.91#ibcon#read 5, iclass 13, count 0 2006.281.07:45:39.91#ibcon#about to read 6, iclass 13, count 0 2006.281.07:45:39.91#ibcon#read 6, iclass 13, count 0 2006.281.07:45:39.91#ibcon#end of sib2, iclass 13, count 0 2006.281.07:45:39.91#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:45:39.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:45:39.91#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:45:39.91#ibcon#*before write, iclass 13, count 0 2006.281.07:45:39.91#ibcon#enter sib2, iclass 13, count 0 2006.281.07:45:39.91#ibcon#flushed, iclass 13, count 0 2006.281.07:45:39.91#ibcon#about to write, iclass 13, count 0 2006.281.07:45:39.91#ibcon#wrote, iclass 13, count 0 2006.281.07:45:39.91#ibcon#about to read 3, iclass 13, count 0 2006.281.07:45:39.96#ibcon#read 3, iclass 13, count 0 2006.281.07:45:39.96#ibcon#about to read 4, iclass 13, count 0 2006.281.07:45:39.96#ibcon#read 4, iclass 13, count 0 2006.281.07:45:39.96#ibcon#about to read 5, iclass 13, count 0 2006.281.07:45:39.96#ibcon#read 5, iclass 13, count 0 2006.281.07:45:39.96#ibcon#about to read 6, iclass 13, count 0 2006.281.07:45:39.96#ibcon#read 6, iclass 13, count 0 2006.281.07:45:39.96#ibcon#end of sib2, iclass 13, count 0 2006.281.07:45:39.96#ibcon#*after write, iclass 13, count 0 2006.281.07:45:39.96#ibcon#*before return 0, iclass 13, count 0 2006.281.07:45:39.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:39.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:39.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:45:39.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:45:39.96$vc4f8/va=2,6 2006.281.07:45:39.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.07:45:39.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.07:45:39.96#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:39.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:40.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:40.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:40.00#ibcon#enter wrdev, iclass 15, count 2 2006.281.07:45:40.00#ibcon#first serial, iclass 15, count 2 2006.281.07:45:40.00#ibcon#enter sib2, iclass 15, count 2 2006.281.07:45:40.00#ibcon#flushed, iclass 15, count 2 2006.281.07:45:40.00#ibcon#about to write, iclass 15, count 2 2006.281.07:45:40.00#ibcon#wrote, iclass 15, count 2 2006.281.07:45:40.00#ibcon#about to read 3, iclass 15, count 2 2006.281.07:45:40.02#ibcon#read 3, iclass 15, count 2 2006.281.07:45:40.02#ibcon#about to read 4, iclass 15, count 2 2006.281.07:45:40.02#ibcon#read 4, iclass 15, count 2 2006.281.07:45:40.02#ibcon#about to read 5, iclass 15, count 2 2006.281.07:45:40.02#ibcon#read 5, iclass 15, count 2 2006.281.07:45:40.02#ibcon#about to read 6, iclass 15, count 2 2006.281.07:45:40.02#ibcon#read 6, iclass 15, count 2 2006.281.07:45:40.02#ibcon#end of sib2, iclass 15, count 2 2006.281.07:45:40.02#ibcon#*mode == 0, iclass 15, count 2 2006.281.07:45:40.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.07:45:40.02#ibcon#[25=AT02-06\r\n] 2006.281.07:45:40.02#ibcon#*before write, iclass 15, count 2 2006.281.07:45:40.02#ibcon#enter sib2, iclass 15, count 2 2006.281.07:45:40.02#ibcon#flushed, iclass 15, count 2 2006.281.07:45:40.02#ibcon#about to write, iclass 15, count 2 2006.281.07:45:40.02#ibcon#wrote, iclass 15, count 2 2006.281.07:45:40.02#ibcon#about to read 3, iclass 15, count 2 2006.281.07:45:40.05#ibcon#read 3, iclass 15, count 2 2006.281.07:45:40.05#ibcon#about to read 4, iclass 15, count 2 2006.281.07:45:40.05#ibcon#read 4, iclass 15, count 2 2006.281.07:45:40.05#ibcon#about to read 5, iclass 15, count 2 2006.281.07:45:40.05#ibcon#read 5, iclass 15, count 2 2006.281.07:45:40.05#ibcon#about to read 6, iclass 15, count 2 2006.281.07:45:40.05#ibcon#read 6, iclass 15, count 2 2006.281.07:45:40.05#ibcon#end of sib2, iclass 15, count 2 2006.281.07:45:40.05#ibcon#*after write, iclass 15, count 2 2006.281.07:45:40.05#ibcon#*before return 0, iclass 15, count 2 2006.281.07:45:40.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:40.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:40.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.07:45:40.05#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:40.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:40.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:40.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:40.17#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:45:40.17#ibcon#first serial, iclass 15, count 0 2006.281.07:45:40.17#ibcon#enter sib2, iclass 15, count 0 2006.281.07:45:40.17#ibcon#flushed, iclass 15, count 0 2006.281.07:45:40.17#ibcon#about to write, iclass 15, count 0 2006.281.07:45:40.17#ibcon#wrote, iclass 15, count 0 2006.281.07:45:40.17#ibcon#about to read 3, iclass 15, count 0 2006.281.07:45:40.19#ibcon#read 3, iclass 15, count 0 2006.281.07:45:40.19#ibcon#about to read 4, iclass 15, count 0 2006.281.07:45:40.19#ibcon#read 4, iclass 15, count 0 2006.281.07:45:40.19#ibcon#about to read 5, iclass 15, count 0 2006.281.07:45:40.19#ibcon#read 5, iclass 15, count 0 2006.281.07:45:40.19#ibcon#about to read 6, iclass 15, count 0 2006.281.07:45:40.19#ibcon#read 6, iclass 15, count 0 2006.281.07:45:40.19#ibcon#end of sib2, iclass 15, count 0 2006.281.07:45:40.19#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:45:40.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:45:40.19#ibcon#[25=USB\r\n] 2006.281.07:45:40.19#ibcon#*before write, iclass 15, count 0 2006.281.07:45:40.19#ibcon#enter sib2, iclass 15, count 0 2006.281.07:45:40.19#ibcon#flushed, iclass 15, count 0 2006.281.07:45:40.19#ibcon#about to write, iclass 15, count 0 2006.281.07:45:40.19#ibcon#wrote, iclass 15, count 0 2006.281.07:45:40.19#ibcon#about to read 3, iclass 15, count 0 2006.281.07:45:40.22#ibcon#read 3, iclass 15, count 0 2006.281.07:45:40.22#ibcon#about to read 4, iclass 15, count 0 2006.281.07:45:40.22#ibcon#read 4, iclass 15, count 0 2006.281.07:45:40.22#ibcon#about to read 5, iclass 15, count 0 2006.281.07:45:40.22#ibcon#read 5, iclass 15, count 0 2006.281.07:45:40.22#ibcon#about to read 6, iclass 15, count 0 2006.281.07:45:40.22#ibcon#read 6, iclass 15, count 0 2006.281.07:45:40.22#ibcon#end of sib2, iclass 15, count 0 2006.281.07:45:40.22#ibcon#*after write, iclass 15, count 0 2006.281.07:45:40.22#ibcon#*before return 0, iclass 15, count 0 2006.281.07:45:40.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:40.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:40.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:45:40.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:45:40.22$vc4f8/valo=3,672.99 2006.281.07:45:40.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:45:40.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:45:40.22#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:40.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:40.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:40.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:40.22#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:45:40.22#ibcon#first serial, iclass 17, count 0 2006.281.07:45:40.22#ibcon#enter sib2, iclass 17, count 0 2006.281.07:45:40.22#ibcon#flushed, iclass 17, count 0 2006.281.07:45:40.22#ibcon#about to write, iclass 17, count 0 2006.281.07:45:40.22#ibcon#wrote, iclass 17, count 0 2006.281.07:45:40.22#ibcon#about to read 3, iclass 17, count 0 2006.281.07:45:40.24#ibcon#read 3, iclass 17, count 0 2006.281.07:45:40.24#ibcon#about to read 4, iclass 17, count 0 2006.281.07:45:40.24#ibcon#read 4, iclass 17, count 0 2006.281.07:45:40.24#ibcon#about to read 5, iclass 17, count 0 2006.281.07:45:40.24#ibcon#read 5, iclass 17, count 0 2006.281.07:45:40.24#ibcon#about to read 6, iclass 17, count 0 2006.281.07:45:40.24#ibcon#read 6, iclass 17, count 0 2006.281.07:45:40.24#ibcon#end of sib2, iclass 17, count 0 2006.281.07:45:40.24#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:45:40.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:45:40.24#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:45:40.24#ibcon#*before write, iclass 17, count 0 2006.281.07:45:40.24#ibcon#enter sib2, iclass 17, count 0 2006.281.07:45:40.24#ibcon#flushed, iclass 17, count 0 2006.281.07:45:40.24#ibcon#about to write, iclass 17, count 0 2006.281.07:45:40.24#ibcon#wrote, iclass 17, count 0 2006.281.07:45:40.24#ibcon#about to read 3, iclass 17, count 0 2006.281.07:45:40.29#ibcon#read 3, iclass 17, count 0 2006.281.07:45:40.29#ibcon#about to read 4, iclass 17, count 0 2006.281.07:45:40.29#ibcon#read 4, iclass 17, count 0 2006.281.07:45:40.29#ibcon#about to read 5, iclass 17, count 0 2006.281.07:45:40.29#ibcon#read 5, iclass 17, count 0 2006.281.07:45:40.29#ibcon#about to read 6, iclass 17, count 0 2006.281.07:45:40.29#ibcon#read 6, iclass 17, count 0 2006.281.07:45:40.29#ibcon#end of sib2, iclass 17, count 0 2006.281.07:45:40.29#ibcon#*after write, iclass 17, count 0 2006.281.07:45:40.29#ibcon#*before return 0, iclass 17, count 0 2006.281.07:45:40.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:40.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:40.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:45:40.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:45:40.29$vc4f8/va=3,6 2006.281.07:45:40.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.07:45:40.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.07:45:40.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:40.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:40.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:40.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:40.33#ibcon#enter wrdev, iclass 19, count 2 2006.281.07:45:40.33#ibcon#first serial, iclass 19, count 2 2006.281.07:45:40.33#ibcon#enter sib2, iclass 19, count 2 2006.281.07:45:40.33#ibcon#flushed, iclass 19, count 2 2006.281.07:45:40.33#ibcon#about to write, iclass 19, count 2 2006.281.07:45:40.33#ibcon#wrote, iclass 19, count 2 2006.281.07:45:40.33#ibcon#about to read 3, iclass 19, count 2 2006.281.07:45:40.36#ibcon#read 3, iclass 19, count 2 2006.281.07:45:40.36#ibcon#about to read 4, iclass 19, count 2 2006.281.07:45:40.36#ibcon#read 4, iclass 19, count 2 2006.281.07:45:40.36#ibcon#about to read 5, iclass 19, count 2 2006.281.07:45:40.36#ibcon#read 5, iclass 19, count 2 2006.281.07:45:40.36#ibcon#about to read 6, iclass 19, count 2 2006.281.07:45:40.36#ibcon#read 6, iclass 19, count 2 2006.281.07:45:40.36#ibcon#end of sib2, iclass 19, count 2 2006.281.07:45:40.36#ibcon#*mode == 0, iclass 19, count 2 2006.281.07:45:40.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.07:45:40.36#ibcon#[25=AT03-06\r\n] 2006.281.07:45:40.36#ibcon#*before write, iclass 19, count 2 2006.281.07:45:40.36#ibcon#enter sib2, iclass 19, count 2 2006.281.07:45:40.36#ibcon#flushed, iclass 19, count 2 2006.281.07:45:40.36#ibcon#about to write, iclass 19, count 2 2006.281.07:45:40.36#ibcon#wrote, iclass 19, count 2 2006.281.07:45:40.36#ibcon#about to read 3, iclass 19, count 2 2006.281.07:45:40.38#ibcon#read 3, iclass 19, count 2 2006.281.07:45:40.38#ibcon#about to read 4, iclass 19, count 2 2006.281.07:45:40.38#ibcon#read 4, iclass 19, count 2 2006.281.07:45:40.38#ibcon#about to read 5, iclass 19, count 2 2006.281.07:45:40.38#ibcon#read 5, iclass 19, count 2 2006.281.07:45:40.38#ibcon#about to read 6, iclass 19, count 2 2006.281.07:45:40.38#ibcon#read 6, iclass 19, count 2 2006.281.07:45:40.38#ibcon#end of sib2, iclass 19, count 2 2006.281.07:45:40.38#ibcon#*after write, iclass 19, count 2 2006.281.07:45:40.38#ibcon#*before return 0, iclass 19, count 2 2006.281.07:45:40.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:40.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:40.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.07:45:40.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:40.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:40.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:40.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:40.50#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:45:40.50#ibcon#first serial, iclass 19, count 0 2006.281.07:45:40.50#ibcon#enter sib2, iclass 19, count 0 2006.281.07:45:40.50#ibcon#flushed, iclass 19, count 0 2006.281.07:45:40.50#ibcon#about to write, iclass 19, count 0 2006.281.07:45:40.50#ibcon#wrote, iclass 19, count 0 2006.281.07:45:40.50#ibcon#about to read 3, iclass 19, count 0 2006.281.07:45:40.52#ibcon#read 3, iclass 19, count 0 2006.281.07:45:40.52#ibcon#about to read 4, iclass 19, count 0 2006.281.07:45:40.52#ibcon#read 4, iclass 19, count 0 2006.281.07:45:40.52#ibcon#about to read 5, iclass 19, count 0 2006.281.07:45:40.52#ibcon#read 5, iclass 19, count 0 2006.281.07:45:40.52#ibcon#about to read 6, iclass 19, count 0 2006.281.07:45:40.52#ibcon#read 6, iclass 19, count 0 2006.281.07:45:40.52#ibcon#end of sib2, iclass 19, count 0 2006.281.07:45:40.52#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:45:40.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:45:40.52#ibcon#[25=USB\r\n] 2006.281.07:45:40.52#ibcon#*before write, iclass 19, count 0 2006.281.07:45:40.52#ibcon#enter sib2, iclass 19, count 0 2006.281.07:45:40.52#ibcon#flushed, iclass 19, count 0 2006.281.07:45:40.52#ibcon#about to write, iclass 19, count 0 2006.281.07:45:40.52#ibcon#wrote, iclass 19, count 0 2006.281.07:45:40.52#ibcon#about to read 3, iclass 19, count 0 2006.281.07:45:40.55#ibcon#read 3, iclass 19, count 0 2006.281.07:45:40.55#ibcon#about to read 4, iclass 19, count 0 2006.281.07:45:40.55#ibcon#read 4, iclass 19, count 0 2006.281.07:45:40.55#ibcon#about to read 5, iclass 19, count 0 2006.281.07:45:40.55#ibcon#read 5, iclass 19, count 0 2006.281.07:45:40.55#ibcon#about to read 6, iclass 19, count 0 2006.281.07:45:40.55#ibcon#read 6, iclass 19, count 0 2006.281.07:45:40.55#ibcon#end of sib2, iclass 19, count 0 2006.281.07:45:40.55#ibcon#*after write, iclass 19, count 0 2006.281.07:45:40.55#ibcon#*before return 0, iclass 19, count 0 2006.281.07:45:40.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:40.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:40.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:45:40.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:45:40.56$vc4f8/valo=4,832.99 2006.281.07:45:40.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.07:45:40.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.07:45:40.56#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:40.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:40.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:40.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:40.56#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:45:40.56#ibcon#first serial, iclass 21, count 0 2006.281.07:45:40.56#ibcon#enter sib2, iclass 21, count 0 2006.281.07:45:40.56#ibcon#flushed, iclass 21, count 0 2006.281.07:45:40.56#ibcon#about to write, iclass 21, count 0 2006.281.07:45:40.56#ibcon#wrote, iclass 21, count 0 2006.281.07:45:40.56#ibcon#about to read 3, iclass 21, count 0 2006.281.07:45:40.57#ibcon#read 3, iclass 21, count 0 2006.281.07:45:40.57#ibcon#about to read 4, iclass 21, count 0 2006.281.07:45:40.57#ibcon#read 4, iclass 21, count 0 2006.281.07:45:40.57#ibcon#about to read 5, iclass 21, count 0 2006.281.07:45:40.57#ibcon#read 5, iclass 21, count 0 2006.281.07:45:40.57#ibcon#about to read 6, iclass 21, count 0 2006.281.07:45:40.57#ibcon#read 6, iclass 21, count 0 2006.281.07:45:40.57#ibcon#end of sib2, iclass 21, count 0 2006.281.07:45:40.57#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:45:40.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:45:40.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:45:40.59#ibcon#*before write, iclass 21, count 0 2006.281.07:45:40.59#ibcon#enter sib2, iclass 21, count 0 2006.281.07:45:40.59#ibcon#flushed, iclass 21, count 0 2006.281.07:45:40.59#ibcon#about to write, iclass 21, count 0 2006.281.07:45:40.59#ibcon#wrote, iclass 21, count 0 2006.281.07:45:40.59#ibcon#about to read 3, iclass 21, count 0 2006.281.07:45:40.63#ibcon#read 3, iclass 21, count 0 2006.281.07:45:40.63#ibcon#about to read 4, iclass 21, count 0 2006.281.07:45:40.63#ibcon#read 4, iclass 21, count 0 2006.281.07:45:40.63#ibcon#about to read 5, iclass 21, count 0 2006.281.07:45:40.63#ibcon#read 5, iclass 21, count 0 2006.281.07:45:40.63#ibcon#about to read 6, iclass 21, count 0 2006.281.07:45:40.63#ibcon#read 6, iclass 21, count 0 2006.281.07:45:40.63#ibcon#end of sib2, iclass 21, count 0 2006.281.07:45:40.63#ibcon#*after write, iclass 21, count 0 2006.281.07:45:40.63#ibcon#*before return 0, iclass 21, count 0 2006.281.07:45:40.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:40.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:40.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:45:40.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:45:40.63$vc4f8/va=4,6 2006.281.07:45:40.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.07:45:40.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.07:45:40.63#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:40.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:40.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:40.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:40.67#ibcon#enter wrdev, iclass 23, count 2 2006.281.07:45:40.67#ibcon#first serial, iclass 23, count 2 2006.281.07:45:40.67#ibcon#enter sib2, iclass 23, count 2 2006.281.07:45:40.67#ibcon#flushed, iclass 23, count 2 2006.281.07:45:40.67#ibcon#about to write, iclass 23, count 2 2006.281.07:45:40.67#ibcon#wrote, iclass 23, count 2 2006.281.07:45:40.67#ibcon#about to read 3, iclass 23, count 2 2006.281.07:45:40.69#ibcon#read 3, iclass 23, count 2 2006.281.07:45:40.69#ibcon#about to read 4, iclass 23, count 2 2006.281.07:45:40.69#ibcon#read 4, iclass 23, count 2 2006.281.07:45:40.69#ibcon#about to read 5, iclass 23, count 2 2006.281.07:45:40.69#ibcon#read 5, iclass 23, count 2 2006.281.07:45:40.69#ibcon#about to read 6, iclass 23, count 2 2006.281.07:45:40.69#ibcon#read 6, iclass 23, count 2 2006.281.07:45:40.69#ibcon#end of sib2, iclass 23, count 2 2006.281.07:45:40.69#ibcon#*mode == 0, iclass 23, count 2 2006.281.07:45:40.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.07:45:40.69#ibcon#[25=AT04-06\r\n] 2006.281.07:45:40.69#ibcon#*before write, iclass 23, count 2 2006.281.07:45:40.69#ibcon#enter sib2, iclass 23, count 2 2006.281.07:45:40.69#ibcon#flushed, iclass 23, count 2 2006.281.07:45:40.69#ibcon#about to write, iclass 23, count 2 2006.281.07:45:40.69#ibcon#wrote, iclass 23, count 2 2006.281.07:45:40.69#ibcon#about to read 3, iclass 23, count 2 2006.281.07:45:40.72#ibcon#read 3, iclass 23, count 2 2006.281.07:45:40.72#ibcon#about to read 4, iclass 23, count 2 2006.281.07:45:40.72#ibcon#read 4, iclass 23, count 2 2006.281.07:45:40.72#ibcon#about to read 5, iclass 23, count 2 2006.281.07:45:40.72#ibcon#read 5, iclass 23, count 2 2006.281.07:45:40.72#ibcon#about to read 6, iclass 23, count 2 2006.281.07:45:40.72#ibcon#read 6, iclass 23, count 2 2006.281.07:45:40.72#ibcon#end of sib2, iclass 23, count 2 2006.281.07:45:40.72#ibcon#*after write, iclass 23, count 2 2006.281.07:45:40.72#ibcon#*before return 0, iclass 23, count 2 2006.281.07:45:40.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:40.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:40.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.07:45:40.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:40.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:40.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:40.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:40.84#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:45:40.84#ibcon#first serial, iclass 23, count 0 2006.281.07:45:40.84#ibcon#enter sib2, iclass 23, count 0 2006.281.07:45:40.84#ibcon#flushed, iclass 23, count 0 2006.281.07:45:40.84#ibcon#about to write, iclass 23, count 0 2006.281.07:45:40.84#ibcon#wrote, iclass 23, count 0 2006.281.07:45:40.84#ibcon#about to read 3, iclass 23, count 0 2006.281.07:45:40.86#ibcon#read 3, iclass 23, count 0 2006.281.07:45:40.86#ibcon#about to read 4, iclass 23, count 0 2006.281.07:45:40.86#ibcon#read 4, iclass 23, count 0 2006.281.07:45:40.86#ibcon#about to read 5, iclass 23, count 0 2006.281.07:45:40.86#ibcon#read 5, iclass 23, count 0 2006.281.07:45:40.86#ibcon#about to read 6, iclass 23, count 0 2006.281.07:45:40.86#ibcon#read 6, iclass 23, count 0 2006.281.07:45:40.86#ibcon#end of sib2, iclass 23, count 0 2006.281.07:45:40.86#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:45:40.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:45:40.86#ibcon#[25=USB\r\n] 2006.281.07:45:40.86#ibcon#*before write, iclass 23, count 0 2006.281.07:45:40.86#ibcon#enter sib2, iclass 23, count 0 2006.281.07:45:40.86#ibcon#flushed, iclass 23, count 0 2006.281.07:45:40.86#ibcon#about to write, iclass 23, count 0 2006.281.07:45:40.86#ibcon#wrote, iclass 23, count 0 2006.281.07:45:40.86#ibcon#about to read 3, iclass 23, count 0 2006.281.07:45:40.89#ibcon#read 3, iclass 23, count 0 2006.281.07:45:40.89#ibcon#about to read 4, iclass 23, count 0 2006.281.07:45:40.89#ibcon#read 4, iclass 23, count 0 2006.281.07:45:40.89#ibcon#about to read 5, iclass 23, count 0 2006.281.07:45:40.89#ibcon#read 5, iclass 23, count 0 2006.281.07:45:40.89#ibcon#about to read 6, iclass 23, count 0 2006.281.07:45:40.89#ibcon#read 6, iclass 23, count 0 2006.281.07:45:40.89#ibcon#end of sib2, iclass 23, count 0 2006.281.07:45:40.89#ibcon#*after write, iclass 23, count 0 2006.281.07:45:40.89#ibcon#*before return 0, iclass 23, count 0 2006.281.07:45:40.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:40.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:40.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:45:40.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:45:40.89$vc4f8/valo=5,652.99 2006.281.07:45:40.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.07:45:40.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.07:45:40.89#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:40.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:40.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:40.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:40.89#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:45:40.89#ibcon#first serial, iclass 25, count 0 2006.281.07:45:40.89#ibcon#enter sib2, iclass 25, count 0 2006.281.07:45:40.89#ibcon#flushed, iclass 25, count 0 2006.281.07:45:40.89#ibcon#about to write, iclass 25, count 0 2006.281.07:45:40.89#ibcon#wrote, iclass 25, count 0 2006.281.07:45:40.89#ibcon#about to read 3, iclass 25, count 0 2006.281.07:45:40.91#ibcon#read 3, iclass 25, count 0 2006.281.07:45:40.91#ibcon#about to read 4, iclass 25, count 0 2006.281.07:45:40.91#ibcon#read 4, iclass 25, count 0 2006.281.07:45:40.91#ibcon#about to read 5, iclass 25, count 0 2006.281.07:45:40.91#ibcon#read 5, iclass 25, count 0 2006.281.07:45:40.91#ibcon#about to read 6, iclass 25, count 0 2006.281.07:45:40.91#ibcon#read 6, iclass 25, count 0 2006.281.07:45:40.91#ibcon#end of sib2, iclass 25, count 0 2006.281.07:45:40.91#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:45:40.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:45:40.91#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:45:40.91#ibcon#*before write, iclass 25, count 0 2006.281.07:45:40.91#ibcon#enter sib2, iclass 25, count 0 2006.281.07:45:40.91#ibcon#flushed, iclass 25, count 0 2006.281.07:45:40.91#ibcon#about to write, iclass 25, count 0 2006.281.07:45:40.91#ibcon#wrote, iclass 25, count 0 2006.281.07:45:40.91#ibcon#about to read 3, iclass 25, count 0 2006.281.07:45:40.95#ibcon#read 3, iclass 25, count 0 2006.281.07:45:40.95#ibcon#about to read 4, iclass 25, count 0 2006.281.07:45:40.95#ibcon#read 4, iclass 25, count 0 2006.281.07:45:40.95#ibcon#about to read 5, iclass 25, count 0 2006.281.07:45:40.95#ibcon#read 5, iclass 25, count 0 2006.281.07:45:40.95#ibcon#about to read 6, iclass 25, count 0 2006.281.07:45:40.95#ibcon#read 6, iclass 25, count 0 2006.281.07:45:40.95#ibcon#end of sib2, iclass 25, count 0 2006.281.07:45:40.95#ibcon#*after write, iclass 25, count 0 2006.281.07:45:40.95#ibcon#*before return 0, iclass 25, count 0 2006.281.07:45:40.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:40.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:40.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:45:40.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:45:40.95$vc4f8/va=5,7 2006.281.07:45:40.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.07:45:40.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.07:45:40.95#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:40.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:41.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:41.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:41.01#ibcon#enter wrdev, iclass 27, count 2 2006.281.07:45:41.01#ibcon#first serial, iclass 27, count 2 2006.281.07:45:41.01#ibcon#enter sib2, iclass 27, count 2 2006.281.07:45:41.01#ibcon#flushed, iclass 27, count 2 2006.281.07:45:41.01#ibcon#about to write, iclass 27, count 2 2006.281.07:45:41.01#ibcon#wrote, iclass 27, count 2 2006.281.07:45:41.01#ibcon#about to read 3, iclass 27, count 2 2006.281.07:45:41.03#ibcon#read 3, iclass 27, count 2 2006.281.07:45:41.03#ibcon#about to read 4, iclass 27, count 2 2006.281.07:45:41.03#ibcon#read 4, iclass 27, count 2 2006.281.07:45:41.03#ibcon#about to read 5, iclass 27, count 2 2006.281.07:45:41.03#ibcon#read 5, iclass 27, count 2 2006.281.07:45:41.03#ibcon#about to read 6, iclass 27, count 2 2006.281.07:45:41.03#ibcon#read 6, iclass 27, count 2 2006.281.07:45:41.03#ibcon#end of sib2, iclass 27, count 2 2006.281.07:45:41.03#ibcon#*mode == 0, iclass 27, count 2 2006.281.07:45:41.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.07:45:41.03#ibcon#[25=AT05-07\r\n] 2006.281.07:45:41.03#ibcon#*before write, iclass 27, count 2 2006.281.07:45:41.03#ibcon#enter sib2, iclass 27, count 2 2006.281.07:45:41.03#ibcon#flushed, iclass 27, count 2 2006.281.07:45:41.03#ibcon#about to write, iclass 27, count 2 2006.281.07:45:41.03#ibcon#wrote, iclass 27, count 2 2006.281.07:45:41.03#ibcon#about to read 3, iclass 27, count 2 2006.281.07:45:41.07#ibcon#read 3, iclass 27, count 2 2006.281.07:45:41.07#ibcon#about to read 4, iclass 27, count 2 2006.281.07:45:41.07#ibcon#read 4, iclass 27, count 2 2006.281.07:45:41.07#ibcon#about to read 5, iclass 27, count 2 2006.281.07:45:41.07#ibcon#read 5, iclass 27, count 2 2006.281.07:45:41.07#ibcon#about to read 6, iclass 27, count 2 2006.281.07:45:41.07#ibcon#read 6, iclass 27, count 2 2006.281.07:45:41.07#ibcon#end of sib2, iclass 27, count 2 2006.281.07:45:41.07#ibcon#*after write, iclass 27, count 2 2006.281.07:45:41.07#ibcon#*before return 0, iclass 27, count 2 2006.281.07:45:41.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:41.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:41.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.07:45:41.07#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:41.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:41.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:41.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:41.18#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:45:41.18#ibcon#first serial, iclass 27, count 0 2006.281.07:45:41.18#ibcon#enter sib2, iclass 27, count 0 2006.281.07:45:41.18#ibcon#flushed, iclass 27, count 0 2006.281.07:45:41.18#ibcon#about to write, iclass 27, count 0 2006.281.07:45:41.18#ibcon#wrote, iclass 27, count 0 2006.281.07:45:41.18#ibcon#about to read 3, iclass 27, count 0 2006.281.07:45:41.20#ibcon#read 3, iclass 27, count 0 2006.281.07:45:41.20#ibcon#about to read 4, iclass 27, count 0 2006.281.07:45:41.20#ibcon#read 4, iclass 27, count 0 2006.281.07:45:41.20#ibcon#about to read 5, iclass 27, count 0 2006.281.07:45:41.20#ibcon#read 5, iclass 27, count 0 2006.281.07:45:41.20#ibcon#about to read 6, iclass 27, count 0 2006.281.07:45:41.20#ibcon#read 6, iclass 27, count 0 2006.281.07:45:41.20#ibcon#end of sib2, iclass 27, count 0 2006.281.07:45:41.20#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:45:41.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:45:41.20#ibcon#[25=USB\r\n] 2006.281.07:45:41.20#ibcon#*before write, iclass 27, count 0 2006.281.07:45:41.20#ibcon#enter sib2, iclass 27, count 0 2006.281.07:45:41.20#ibcon#flushed, iclass 27, count 0 2006.281.07:45:41.20#ibcon#about to write, iclass 27, count 0 2006.281.07:45:41.20#ibcon#wrote, iclass 27, count 0 2006.281.07:45:41.20#ibcon#about to read 3, iclass 27, count 0 2006.281.07:45:41.23#ibcon#read 3, iclass 27, count 0 2006.281.07:45:41.23#ibcon#about to read 4, iclass 27, count 0 2006.281.07:45:41.23#ibcon#read 4, iclass 27, count 0 2006.281.07:45:41.23#ibcon#about to read 5, iclass 27, count 0 2006.281.07:45:41.23#ibcon#read 5, iclass 27, count 0 2006.281.07:45:41.23#ibcon#about to read 6, iclass 27, count 0 2006.281.07:45:41.23#ibcon#read 6, iclass 27, count 0 2006.281.07:45:41.23#ibcon#end of sib2, iclass 27, count 0 2006.281.07:45:41.23#ibcon#*after write, iclass 27, count 0 2006.281.07:45:41.23#ibcon#*before return 0, iclass 27, count 0 2006.281.07:45:41.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:41.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:41.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:45:41.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:45:41.23$vc4f8/valo=6,772.99 2006.281.07:45:41.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.07:45:41.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.07:45:41.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:41.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:45:41.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:45:41.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:45:41.23#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:45:41.23#ibcon#first serial, iclass 29, count 0 2006.281.07:45:41.23#ibcon#enter sib2, iclass 29, count 0 2006.281.07:45:41.23#ibcon#flushed, iclass 29, count 0 2006.281.07:45:41.23#ibcon#about to write, iclass 29, count 0 2006.281.07:45:41.23#ibcon#wrote, iclass 29, count 0 2006.281.07:45:41.23#ibcon#about to read 3, iclass 29, count 0 2006.281.07:45:41.25#ibcon#read 3, iclass 29, count 0 2006.281.07:45:41.25#ibcon#about to read 4, iclass 29, count 0 2006.281.07:45:41.25#ibcon#read 4, iclass 29, count 0 2006.281.07:45:41.25#ibcon#about to read 5, iclass 29, count 0 2006.281.07:45:41.25#ibcon#read 5, iclass 29, count 0 2006.281.07:45:41.25#ibcon#about to read 6, iclass 29, count 0 2006.281.07:45:41.25#ibcon#read 6, iclass 29, count 0 2006.281.07:45:41.25#ibcon#end of sib2, iclass 29, count 0 2006.281.07:45:41.25#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:45:41.25#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:45:41.25#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:45:41.25#ibcon#*before write, iclass 29, count 0 2006.281.07:45:41.25#ibcon#enter sib2, iclass 29, count 0 2006.281.07:45:41.25#ibcon#flushed, iclass 29, count 0 2006.281.07:45:41.25#ibcon#about to write, iclass 29, count 0 2006.281.07:45:41.25#ibcon#wrote, iclass 29, count 0 2006.281.07:45:41.25#ibcon#about to read 3, iclass 29, count 0 2006.281.07:45:41.29#ibcon#read 3, iclass 29, count 0 2006.281.07:45:41.29#ibcon#about to read 4, iclass 29, count 0 2006.281.07:45:41.29#ibcon#read 4, iclass 29, count 0 2006.281.07:45:41.29#ibcon#about to read 5, iclass 29, count 0 2006.281.07:45:41.29#ibcon#read 5, iclass 29, count 0 2006.281.07:45:41.29#ibcon#about to read 6, iclass 29, count 0 2006.281.07:45:41.29#ibcon#read 6, iclass 29, count 0 2006.281.07:45:41.29#ibcon#end of sib2, iclass 29, count 0 2006.281.07:45:41.29#ibcon#*after write, iclass 29, count 0 2006.281.07:45:41.29#ibcon#*before return 0, iclass 29, count 0 2006.281.07:45:41.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:45:41.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.07:45:41.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:45:41.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:45:41.29$vc4f8/va=6,6 2006.281.07:45:41.29#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.07:45:41.29#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.07:45:41.29#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:41.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:45:41.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:45:41.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:45:41.36#ibcon#enter wrdev, iclass 31, count 2 2006.281.07:45:41.36#ibcon#first serial, iclass 31, count 2 2006.281.07:45:41.36#ibcon#enter sib2, iclass 31, count 2 2006.281.07:45:41.36#ibcon#flushed, iclass 31, count 2 2006.281.07:45:41.36#ibcon#about to write, iclass 31, count 2 2006.281.07:45:41.36#ibcon#wrote, iclass 31, count 2 2006.281.07:45:41.36#ibcon#about to read 3, iclass 31, count 2 2006.281.07:45:41.37#ibcon#read 3, iclass 31, count 2 2006.281.07:45:41.37#ibcon#about to read 4, iclass 31, count 2 2006.281.07:45:41.37#ibcon#read 4, iclass 31, count 2 2006.281.07:45:41.37#ibcon#about to read 5, iclass 31, count 2 2006.281.07:45:41.37#ibcon#read 5, iclass 31, count 2 2006.281.07:45:41.37#ibcon#about to read 6, iclass 31, count 2 2006.281.07:45:41.37#ibcon#read 6, iclass 31, count 2 2006.281.07:45:41.37#ibcon#end of sib2, iclass 31, count 2 2006.281.07:45:41.37#ibcon#*mode == 0, iclass 31, count 2 2006.281.07:45:41.37#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.07:45:41.37#ibcon#[25=AT06-06\r\n] 2006.281.07:45:41.37#ibcon#*before write, iclass 31, count 2 2006.281.07:45:41.37#ibcon#enter sib2, iclass 31, count 2 2006.281.07:45:41.37#ibcon#flushed, iclass 31, count 2 2006.281.07:45:41.37#ibcon#about to write, iclass 31, count 2 2006.281.07:45:41.37#ibcon#wrote, iclass 31, count 2 2006.281.07:45:41.37#ibcon#about to read 3, iclass 31, count 2 2006.281.07:45:41.40#ibcon#read 3, iclass 31, count 2 2006.281.07:45:41.40#ibcon#about to read 4, iclass 31, count 2 2006.281.07:45:41.40#ibcon#read 4, iclass 31, count 2 2006.281.07:45:41.40#ibcon#about to read 5, iclass 31, count 2 2006.281.07:45:41.40#ibcon#read 5, iclass 31, count 2 2006.281.07:45:41.40#ibcon#about to read 6, iclass 31, count 2 2006.281.07:45:41.40#ibcon#read 6, iclass 31, count 2 2006.281.07:45:41.40#ibcon#end of sib2, iclass 31, count 2 2006.281.07:45:41.40#ibcon#*after write, iclass 31, count 2 2006.281.07:45:41.40#ibcon#*before return 0, iclass 31, count 2 2006.281.07:45:41.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:45:41.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.07:45:41.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.07:45:41.40#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:41.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:45:41.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:45:41.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:45:41.52#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:45:41.52#ibcon#first serial, iclass 31, count 0 2006.281.07:45:41.52#ibcon#enter sib2, iclass 31, count 0 2006.281.07:45:41.52#ibcon#flushed, iclass 31, count 0 2006.281.07:45:41.52#ibcon#about to write, iclass 31, count 0 2006.281.07:45:41.52#ibcon#wrote, iclass 31, count 0 2006.281.07:45:41.52#ibcon#about to read 3, iclass 31, count 0 2006.281.07:45:41.54#ibcon#read 3, iclass 31, count 0 2006.281.07:45:41.54#ibcon#about to read 4, iclass 31, count 0 2006.281.07:45:41.54#ibcon#read 4, iclass 31, count 0 2006.281.07:45:41.54#ibcon#about to read 5, iclass 31, count 0 2006.281.07:45:41.54#ibcon#read 5, iclass 31, count 0 2006.281.07:45:41.54#ibcon#about to read 6, iclass 31, count 0 2006.281.07:45:41.54#ibcon#read 6, iclass 31, count 0 2006.281.07:45:41.54#ibcon#end of sib2, iclass 31, count 0 2006.281.07:45:41.54#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:45:41.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:45:41.54#ibcon#[25=USB\r\n] 2006.281.07:45:41.54#ibcon#*before write, iclass 31, count 0 2006.281.07:45:41.54#ibcon#enter sib2, iclass 31, count 0 2006.281.07:45:41.54#ibcon#flushed, iclass 31, count 0 2006.281.07:45:41.54#ibcon#about to write, iclass 31, count 0 2006.281.07:45:41.54#ibcon#wrote, iclass 31, count 0 2006.281.07:45:41.54#ibcon#about to read 3, iclass 31, count 0 2006.281.07:45:41.57#ibcon#read 3, iclass 31, count 0 2006.281.07:45:41.57#ibcon#about to read 4, iclass 31, count 0 2006.281.07:45:41.57#ibcon#read 4, iclass 31, count 0 2006.281.07:45:41.57#ibcon#about to read 5, iclass 31, count 0 2006.281.07:45:41.57#ibcon#read 5, iclass 31, count 0 2006.281.07:45:41.57#ibcon#about to read 6, iclass 31, count 0 2006.281.07:45:41.57#ibcon#read 6, iclass 31, count 0 2006.281.07:45:41.57#ibcon#end of sib2, iclass 31, count 0 2006.281.07:45:41.57#ibcon#*after write, iclass 31, count 0 2006.281.07:45:41.57#ibcon#*before return 0, iclass 31, count 0 2006.281.07:45:41.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:45:41.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.07:45:41.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:45:41.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:45:41.57$vc4f8/valo=7,832.99 2006.281.07:45:41.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.07:45:41.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.07:45:41.57#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:41.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:45:41.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:45:41.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:45:41.57#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:45:41.57#ibcon#first serial, iclass 33, count 0 2006.281.07:45:41.57#ibcon#enter sib2, iclass 33, count 0 2006.281.07:45:41.57#ibcon#flushed, iclass 33, count 0 2006.281.07:45:41.57#ibcon#about to write, iclass 33, count 0 2006.281.07:45:41.57#ibcon#wrote, iclass 33, count 0 2006.281.07:45:41.57#ibcon#about to read 3, iclass 33, count 0 2006.281.07:45:41.59#ibcon#read 3, iclass 33, count 0 2006.281.07:45:41.59#ibcon#about to read 4, iclass 33, count 0 2006.281.07:45:41.59#ibcon#read 4, iclass 33, count 0 2006.281.07:45:41.59#ibcon#about to read 5, iclass 33, count 0 2006.281.07:45:41.59#ibcon#read 5, iclass 33, count 0 2006.281.07:45:41.59#ibcon#about to read 6, iclass 33, count 0 2006.281.07:45:41.59#ibcon#read 6, iclass 33, count 0 2006.281.07:45:41.59#ibcon#end of sib2, iclass 33, count 0 2006.281.07:45:41.59#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:45:41.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:45:41.59#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:45:41.59#ibcon#*before write, iclass 33, count 0 2006.281.07:45:41.59#ibcon#enter sib2, iclass 33, count 0 2006.281.07:45:41.59#ibcon#flushed, iclass 33, count 0 2006.281.07:45:41.59#ibcon#about to write, iclass 33, count 0 2006.281.07:45:41.59#ibcon#wrote, iclass 33, count 0 2006.281.07:45:41.59#ibcon#about to read 3, iclass 33, count 0 2006.281.07:45:41.63#ibcon#read 3, iclass 33, count 0 2006.281.07:45:41.63#ibcon#about to read 4, iclass 33, count 0 2006.281.07:45:41.64#ibcon#read 4, iclass 33, count 0 2006.281.07:45:41.64#ibcon#about to read 5, iclass 33, count 0 2006.281.07:45:41.64#ibcon#read 5, iclass 33, count 0 2006.281.07:45:41.64#ibcon#about to read 6, iclass 33, count 0 2006.281.07:45:41.64#ibcon#read 6, iclass 33, count 0 2006.281.07:45:41.64#ibcon#end of sib2, iclass 33, count 0 2006.281.07:45:41.64#ibcon#*after write, iclass 33, count 0 2006.281.07:45:41.64#ibcon#*before return 0, iclass 33, count 0 2006.281.07:45:41.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:45:41.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.07:45:41.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:45:41.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:45:41.64$vc4f8/va=7,6 2006.281.07:45:41.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.07:45:41.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.07:45:41.64#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:41.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:45:41.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:45:41.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:45:41.68#ibcon#enter wrdev, iclass 35, count 2 2006.281.07:45:41.68#ibcon#first serial, iclass 35, count 2 2006.281.07:45:41.68#ibcon#enter sib2, iclass 35, count 2 2006.281.07:45:41.68#ibcon#flushed, iclass 35, count 2 2006.281.07:45:41.68#ibcon#about to write, iclass 35, count 2 2006.281.07:45:41.68#ibcon#wrote, iclass 35, count 2 2006.281.07:45:41.68#ibcon#about to read 3, iclass 35, count 2 2006.281.07:45:41.70#ibcon#read 3, iclass 35, count 2 2006.281.07:45:41.70#ibcon#about to read 4, iclass 35, count 2 2006.281.07:45:41.70#ibcon#read 4, iclass 35, count 2 2006.281.07:45:41.70#ibcon#about to read 5, iclass 35, count 2 2006.281.07:45:41.70#ibcon#read 5, iclass 35, count 2 2006.281.07:45:41.70#ibcon#about to read 6, iclass 35, count 2 2006.281.07:45:41.70#ibcon#read 6, iclass 35, count 2 2006.281.07:45:41.70#ibcon#end of sib2, iclass 35, count 2 2006.281.07:45:41.70#ibcon#*mode == 0, iclass 35, count 2 2006.281.07:45:41.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.07:45:41.70#ibcon#[25=AT07-06\r\n] 2006.281.07:45:41.70#ibcon#*before write, iclass 35, count 2 2006.281.07:45:41.70#ibcon#enter sib2, iclass 35, count 2 2006.281.07:45:41.70#ibcon#flushed, iclass 35, count 2 2006.281.07:45:41.70#ibcon#about to write, iclass 35, count 2 2006.281.07:45:41.70#ibcon#wrote, iclass 35, count 2 2006.281.07:45:41.70#ibcon#about to read 3, iclass 35, count 2 2006.281.07:45:41.73#ibcon#read 3, iclass 35, count 2 2006.281.07:45:41.73#ibcon#about to read 4, iclass 35, count 2 2006.281.07:45:41.73#ibcon#read 4, iclass 35, count 2 2006.281.07:45:41.73#ibcon#about to read 5, iclass 35, count 2 2006.281.07:45:41.73#ibcon#read 5, iclass 35, count 2 2006.281.07:45:41.73#ibcon#about to read 6, iclass 35, count 2 2006.281.07:45:41.73#ibcon#read 6, iclass 35, count 2 2006.281.07:45:41.73#ibcon#end of sib2, iclass 35, count 2 2006.281.07:45:41.73#ibcon#*after write, iclass 35, count 2 2006.281.07:45:41.73#ibcon#*before return 0, iclass 35, count 2 2006.281.07:45:41.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:45:41.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.07:45:41.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.07:45:41.73#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:41.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:45:41.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:45:41.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:45:41.85#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:45:41.85#ibcon#first serial, iclass 35, count 0 2006.281.07:45:41.85#ibcon#enter sib2, iclass 35, count 0 2006.281.07:45:41.85#ibcon#flushed, iclass 35, count 0 2006.281.07:45:41.85#ibcon#about to write, iclass 35, count 0 2006.281.07:45:41.85#ibcon#wrote, iclass 35, count 0 2006.281.07:45:41.85#ibcon#about to read 3, iclass 35, count 0 2006.281.07:45:41.87#ibcon#read 3, iclass 35, count 0 2006.281.07:45:41.87#ibcon#about to read 4, iclass 35, count 0 2006.281.07:45:41.87#ibcon#read 4, iclass 35, count 0 2006.281.07:45:41.87#ibcon#about to read 5, iclass 35, count 0 2006.281.07:45:41.87#ibcon#read 5, iclass 35, count 0 2006.281.07:45:41.87#ibcon#about to read 6, iclass 35, count 0 2006.281.07:45:41.87#ibcon#read 6, iclass 35, count 0 2006.281.07:45:41.87#ibcon#end of sib2, iclass 35, count 0 2006.281.07:45:41.87#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:45:41.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:45:41.87#ibcon#[25=USB\r\n] 2006.281.07:45:41.87#ibcon#*before write, iclass 35, count 0 2006.281.07:45:41.87#ibcon#enter sib2, iclass 35, count 0 2006.281.07:45:41.87#ibcon#flushed, iclass 35, count 0 2006.281.07:45:41.87#ibcon#about to write, iclass 35, count 0 2006.281.07:45:41.87#ibcon#wrote, iclass 35, count 0 2006.281.07:45:41.87#ibcon#about to read 3, iclass 35, count 0 2006.281.07:45:41.90#ibcon#read 3, iclass 35, count 0 2006.281.07:45:41.90#ibcon#about to read 4, iclass 35, count 0 2006.281.07:45:41.90#ibcon#read 4, iclass 35, count 0 2006.281.07:45:41.90#ibcon#about to read 5, iclass 35, count 0 2006.281.07:45:41.90#ibcon#read 5, iclass 35, count 0 2006.281.07:45:41.90#ibcon#about to read 6, iclass 35, count 0 2006.281.07:45:41.90#ibcon#read 6, iclass 35, count 0 2006.281.07:45:41.90#ibcon#end of sib2, iclass 35, count 0 2006.281.07:45:41.90#ibcon#*after write, iclass 35, count 0 2006.281.07:45:41.90#ibcon#*before return 0, iclass 35, count 0 2006.281.07:45:41.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:45:41.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.07:45:41.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:45:41.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:45:41.90$vc4f8/valo=8,852.99 2006.281.07:45:41.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.07:45:41.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.07:45:41.90#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:41.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:45:41.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:45:41.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:45:41.90#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:45:41.90#ibcon#first serial, iclass 37, count 0 2006.281.07:45:41.90#ibcon#enter sib2, iclass 37, count 0 2006.281.07:45:41.90#ibcon#flushed, iclass 37, count 0 2006.281.07:45:41.90#ibcon#about to write, iclass 37, count 0 2006.281.07:45:41.90#ibcon#wrote, iclass 37, count 0 2006.281.07:45:41.90#ibcon#about to read 3, iclass 37, count 0 2006.281.07:45:41.92#ibcon#read 3, iclass 37, count 0 2006.281.07:45:41.92#ibcon#about to read 4, iclass 37, count 0 2006.281.07:45:41.92#ibcon#read 4, iclass 37, count 0 2006.281.07:45:41.92#ibcon#about to read 5, iclass 37, count 0 2006.281.07:45:41.92#ibcon#read 5, iclass 37, count 0 2006.281.07:45:41.92#ibcon#about to read 6, iclass 37, count 0 2006.281.07:45:41.92#ibcon#read 6, iclass 37, count 0 2006.281.07:45:41.92#ibcon#end of sib2, iclass 37, count 0 2006.281.07:45:41.92#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:45:41.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:45:41.92#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:45:41.92#ibcon#*before write, iclass 37, count 0 2006.281.07:45:41.92#ibcon#enter sib2, iclass 37, count 0 2006.281.07:45:41.92#ibcon#flushed, iclass 37, count 0 2006.281.07:45:41.92#ibcon#about to write, iclass 37, count 0 2006.281.07:45:41.92#ibcon#wrote, iclass 37, count 0 2006.281.07:45:41.92#ibcon#about to read 3, iclass 37, count 0 2006.281.07:45:41.96#ibcon#read 3, iclass 37, count 0 2006.281.07:45:41.96#ibcon#about to read 4, iclass 37, count 0 2006.281.07:45:41.96#ibcon#read 4, iclass 37, count 0 2006.281.07:45:41.96#ibcon#about to read 5, iclass 37, count 0 2006.281.07:45:41.96#ibcon#read 5, iclass 37, count 0 2006.281.07:45:41.96#ibcon#about to read 6, iclass 37, count 0 2006.281.07:45:41.96#ibcon#read 6, iclass 37, count 0 2006.281.07:45:41.96#ibcon#end of sib2, iclass 37, count 0 2006.281.07:45:41.96#ibcon#*after write, iclass 37, count 0 2006.281.07:45:41.96#ibcon#*before return 0, iclass 37, count 0 2006.281.07:45:41.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:45:41.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.07:45:41.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:45:41.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:45:41.96$vc4f8/va=8,6 2006.281.07:45:41.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.07:45:41.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.07:45:41.96#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:41.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:45:42.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:45:42.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:45:42.02#ibcon#enter wrdev, iclass 39, count 2 2006.281.07:45:42.02#ibcon#first serial, iclass 39, count 2 2006.281.07:45:42.02#ibcon#enter sib2, iclass 39, count 2 2006.281.07:45:42.02#ibcon#flushed, iclass 39, count 2 2006.281.07:45:42.02#ibcon#about to write, iclass 39, count 2 2006.281.07:45:42.02#ibcon#wrote, iclass 39, count 2 2006.281.07:45:42.02#ibcon#about to read 3, iclass 39, count 2 2006.281.07:45:42.04#ibcon#read 3, iclass 39, count 2 2006.281.07:45:42.04#ibcon#about to read 4, iclass 39, count 2 2006.281.07:45:42.04#ibcon#read 4, iclass 39, count 2 2006.281.07:45:42.04#ibcon#about to read 5, iclass 39, count 2 2006.281.07:45:42.04#ibcon#read 5, iclass 39, count 2 2006.281.07:45:42.04#ibcon#about to read 6, iclass 39, count 2 2006.281.07:45:42.04#ibcon#read 6, iclass 39, count 2 2006.281.07:45:42.04#ibcon#end of sib2, iclass 39, count 2 2006.281.07:45:42.04#ibcon#*mode == 0, iclass 39, count 2 2006.281.07:45:42.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.07:45:42.04#ibcon#[25=AT08-06\r\n] 2006.281.07:45:42.04#ibcon#*before write, iclass 39, count 2 2006.281.07:45:42.04#ibcon#enter sib2, iclass 39, count 2 2006.281.07:45:42.04#ibcon#flushed, iclass 39, count 2 2006.281.07:45:42.04#ibcon#about to write, iclass 39, count 2 2006.281.07:45:42.04#ibcon#wrote, iclass 39, count 2 2006.281.07:45:42.04#ibcon#about to read 3, iclass 39, count 2 2006.281.07:45:42.07#ibcon#read 3, iclass 39, count 2 2006.281.07:45:42.07#ibcon#about to read 4, iclass 39, count 2 2006.281.07:45:42.07#ibcon#read 4, iclass 39, count 2 2006.281.07:45:42.07#ibcon#about to read 5, iclass 39, count 2 2006.281.07:45:42.07#ibcon#read 5, iclass 39, count 2 2006.281.07:45:42.07#ibcon#about to read 6, iclass 39, count 2 2006.281.07:45:42.07#ibcon#read 6, iclass 39, count 2 2006.281.07:45:42.07#ibcon#end of sib2, iclass 39, count 2 2006.281.07:45:42.07#ibcon#*after write, iclass 39, count 2 2006.281.07:45:42.07#ibcon#*before return 0, iclass 39, count 2 2006.281.07:45:42.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:45:42.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.07:45:42.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.07:45:42.07#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:42.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:45:42.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:45:42.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:45:42.19#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:45:42.19#ibcon#first serial, iclass 39, count 0 2006.281.07:45:42.19#ibcon#enter sib2, iclass 39, count 0 2006.281.07:45:42.19#ibcon#flushed, iclass 39, count 0 2006.281.07:45:42.19#ibcon#about to write, iclass 39, count 0 2006.281.07:45:42.19#ibcon#wrote, iclass 39, count 0 2006.281.07:45:42.19#ibcon#about to read 3, iclass 39, count 0 2006.281.07:45:42.21#ibcon#read 3, iclass 39, count 0 2006.281.07:45:42.21#ibcon#about to read 4, iclass 39, count 0 2006.281.07:45:42.21#ibcon#read 4, iclass 39, count 0 2006.281.07:45:42.21#ibcon#about to read 5, iclass 39, count 0 2006.281.07:45:42.21#ibcon#read 5, iclass 39, count 0 2006.281.07:45:42.21#ibcon#about to read 6, iclass 39, count 0 2006.281.07:45:42.21#ibcon#read 6, iclass 39, count 0 2006.281.07:45:42.21#ibcon#end of sib2, iclass 39, count 0 2006.281.07:45:42.21#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:45:42.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:45:42.21#ibcon#[25=USB\r\n] 2006.281.07:45:42.21#ibcon#*before write, iclass 39, count 0 2006.281.07:45:42.21#ibcon#enter sib2, iclass 39, count 0 2006.281.07:45:42.21#ibcon#flushed, iclass 39, count 0 2006.281.07:45:42.21#ibcon#about to write, iclass 39, count 0 2006.281.07:45:42.21#ibcon#wrote, iclass 39, count 0 2006.281.07:45:42.21#ibcon#about to read 3, iclass 39, count 0 2006.281.07:45:42.24#ibcon#read 3, iclass 39, count 0 2006.281.07:45:42.24#ibcon#about to read 4, iclass 39, count 0 2006.281.07:45:42.24#ibcon#read 4, iclass 39, count 0 2006.281.07:45:42.24#ibcon#about to read 5, iclass 39, count 0 2006.281.07:45:42.24#ibcon#read 5, iclass 39, count 0 2006.281.07:45:42.24#ibcon#about to read 6, iclass 39, count 0 2006.281.07:45:42.24#ibcon#read 6, iclass 39, count 0 2006.281.07:45:42.24#ibcon#end of sib2, iclass 39, count 0 2006.281.07:45:42.24#ibcon#*after write, iclass 39, count 0 2006.281.07:45:42.24#ibcon#*before return 0, iclass 39, count 0 2006.281.07:45:42.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:45:42.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.07:45:42.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:45:42.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:45:42.24$vc4f8/vblo=1,632.99 2006.281.07:45:42.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.07:45:42.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.07:45:42.24#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:42.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:45:42.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:45:42.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:45:42.24#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:45:42.24#ibcon#first serial, iclass 3, count 0 2006.281.07:45:42.24#ibcon#enter sib2, iclass 3, count 0 2006.281.07:45:42.24#ibcon#flushed, iclass 3, count 0 2006.281.07:45:42.24#ibcon#about to write, iclass 3, count 0 2006.281.07:45:42.24#ibcon#wrote, iclass 3, count 0 2006.281.07:45:42.24#ibcon#about to read 3, iclass 3, count 0 2006.281.07:45:42.26#ibcon#read 3, iclass 3, count 0 2006.281.07:45:42.27#ibcon#about to read 4, iclass 3, count 0 2006.281.07:45:42.27#ibcon#read 4, iclass 3, count 0 2006.281.07:45:42.27#ibcon#about to read 5, iclass 3, count 0 2006.281.07:45:42.27#ibcon#read 5, iclass 3, count 0 2006.281.07:45:42.27#ibcon#about to read 6, iclass 3, count 0 2006.281.07:45:42.27#ibcon#read 6, iclass 3, count 0 2006.281.07:45:42.27#ibcon#end of sib2, iclass 3, count 0 2006.281.07:45:42.27#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:45:42.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:45:42.27#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:45:42.27#ibcon#*before write, iclass 3, count 0 2006.281.07:45:42.27#ibcon#enter sib2, iclass 3, count 0 2006.281.07:45:42.27#ibcon#flushed, iclass 3, count 0 2006.281.07:45:42.27#ibcon#about to write, iclass 3, count 0 2006.281.07:45:42.27#ibcon#wrote, iclass 3, count 0 2006.281.07:45:42.27#ibcon#about to read 3, iclass 3, count 0 2006.281.07:45:42.30#ibcon#read 3, iclass 3, count 0 2006.281.07:45:42.30#ibcon#about to read 4, iclass 3, count 0 2006.281.07:45:42.30#ibcon#read 4, iclass 3, count 0 2006.281.07:45:42.30#ibcon#about to read 5, iclass 3, count 0 2006.281.07:45:42.30#ibcon#read 5, iclass 3, count 0 2006.281.07:45:42.30#ibcon#about to read 6, iclass 3, count 0 2006.281.07:45:42.30#ibcon#read 6, iclass 3, count 0 2006.281.07:45:42.30#ibcon#end of sib2, iclass 3, count 0 2006.281.07:45:42.30#ibcon#*after write, iclass 3, count 0 2006.281.07:45:42.30#ibcon#*before return 0, iclass 3, count 0 2006.281.07:45:42.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:45:42.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:45:42.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:45:42.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:45:42.30$vc4f8/vb=1,4 2006.281.07:45:42.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.07:45:42.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.07:45:42.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:42.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:45:42.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:45:42.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:45:42.30#ibcon#enter wrdev, iclass 5, count 2 2006.281.07:45:42.30#ibcon#first serial, iclass 5, count 2 2006.281.07:45:42.30#ibcon#enter sib2, iclass 5, count 2 2006.281.07:45:42.30#ibcon#flushed, iclass 5, count 2 2006.281.07:45:42.30#ibcon#about to write, iclass 5, count 2 2006.281.07:45:42.30#ibcon#wrote, iclass 5, count 2 2006.281.07:45:42.30#ibcon#about to read 3, iclass 5, count 2 2006.281.07:45:42.32#ibcon#read 3, iclass 5, count 2 2006.281.07:45:42.32#ibcon#about to read 4, iclass 5, count 2 2006.281.07:45:42.32#ibcon#read 4, iclass 5, count 2 2006.281.07:45:42.32#ibcon#about to read 5, iclass 5, count 2 2006.281.07:45:42.32#ibcon#read 5, iclass 5, count 2 2006.281.07:45:42.32#ibcon#about to read 6, iclass 5, count 2 2006.281.07:45:42.32#ibcon#read 6, iclass 5, count 2 2006.281.07:45:42.32#ibcon#end of sib2, iclass 5, count 2 2006.281.07:45:42.32#ibcon#*mode == 0, iclass 5, count 2 2006.281.07:45:42.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.07:45:42.32#ibcon#[27=AT01-04\r\n] 2006.281.07:45:42.32#ibcon#*before write, iclass 5, count 2 2006.281.07:45:42.32#ibcon#enter sib2, iclass 5, count 2 2006.281.07:45:42.32#ibcon#flushed, iclass 5, count 2 2006.281.07:45:42.32#ibcon#about to write, iclass 5, count 2 2006.281.07:45:42.32#ibcon#wrote, iclass 5, count 2 2006.281.07:45:42.32#ibcon#about to read 3, iclass 5, count 2 2006.281.07:45:42.35#ibcon#read 3, iclass 5, count 2 2006.281.07:45:42.38#ibcon#about to read 4, iclass 5, count 2 2006.281.07:45:42.38#ibcon#read 4, iclass 5, count 2 2006.281.07:45:42.38#ibcon#about to read 5, iclass 5, count 2 2006.281.07:45:42.38#ibcon#read 5, iclass 5, count 2 2006.281.07:45:42.38#ibcon#about to read 6, iclass 5, count 2 2006.281.07:45:42.38#ibcon#read 6, iclass 5, count 2 2006.281.07:45:42.38#ibcon#end of sib2, iclass 5, count 2 2006.281.07:45:42.38#ibcon#*after write, iclass 5, count 2 2006.281.07:45:42.38#ibcon#*before return 0, iclass 5, count 2 2006.281.07:45:42.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:45:42.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.07:45:42.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.07:45:42.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:42.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:45:42.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:45:42.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:45:42.49#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:45:42.49#ibcon#first serial, iclass 5, count 0 2006.281.07:45:42.49#ibcon#enter sib2, iclass 5, count 0 2006.281.07:45:42.49#ibcon#flushed, iclass 5, count 0 2006.281.07:45:42.49#ibcon#about to write, iclass 5, count 0 2006.281.07:45:42.49#ibcon#wrote, iclass 5, count 0 2006.281.07:45:42.49#ibcon#about to read 3, iclass 5, count 0 2006.281.07:45:42.51#ibcon#read 3, iclass 5, count 0 2006.281.07:45:42.51#ibcon#about to read 4, iclass 5, count 0 2006.281.07:45:42.51#ibcon#read 4, iclass 5, count 0 2006.281.07:45:42.51#ibcon#about to read 5, iclass 5, count 0 2006.281.07:45:42.51#ibcon#read 5, iclass 5, count 0 2006.281.07:45:42.51#ibcon#about to read 6, iclass 5, count 0 2006.281.07:45:42.51#ibcon#read 6, iclass 5, count 0 2006.281.07:45:42.51#ibcon#end of sib2, iclass 5, count 0 2006.281.07:45:42.51#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:45:42.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:45:42.51#ibcon#[27=USB\r\n] 2006.281.07:45:42.51#ibcon#*before write, iclass 5, count 0 2006.281.07:45:42.51#ibcon#enter sib2, iclass 5, count 0 2006.281.07:45:42.51#ibcon#flushed, iclass 5, count 0 2006.281.07:45:42.51#ibcon#about to write, iclass 5, count 0 2006.281.07:45:42.51#ibcon#wrote, iclass 5, count 0 2006.281.07:45:42.51#ibcon#about to read 3, iclass 5, count 0 2006.281.07:45:42.54#ibcon#read 3, iclass 5, count 0 2006.281.07:45:42.54#ibcon#about to read 4, iclass 5, count 0 2006.281.07:45:42.54#ibcon#read 4, iclass 5, count 0 2006.281.07:45:42.54#ibcon#about to read 5, iclass 5, count 0 2006.281.07:45:42.54#ibcon#read 5, iclass 5, count 0 2006.281.07:45:42.54#ibcon#about to read 6, iclass 5, count 0 2006.281.07:45:42.54#ibcon#read 6, iclass 5, count 0 2006.281.07:45:42.54#ibcon#end of sib2, iclass 5, count 0 2006.281.07:45:42.54#ibcon#*after write, iclass 5, count 0 2006.281.07:45:42.54#ibcon#*before return 0, iclass 5, count 0 2006.281.07:45:42.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:45:42.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.07:45:42.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:45:42.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:45:42.54$vc4f8/vblo=2,640.99 2006.281.07:45:42.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.07:45:42.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.07:45:42.54#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:42.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:42.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:42.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:42.54#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:45:42.54#ibcon#first serial, iclass 7, count 0 2006.281.07:45:42.54#ibcon#enter sib2, iclass 7, count 0 2006.281.07:45:42.54#ibcon#flushed, iclass 7, count 0 2006.281.07:45:42.54#ibcon#about to write, iclass 7, count 0 2006.281.07:45:42.54#ibcon#wrote, iclass 7, count 0 2006.281.07:45:42.54#ibcon#about to read 3, iclass 7, count 0 2006.281.07:45:42.56#ibcon#read 3, iclass 7, count 0 2006.281.07:45:42.56#ibcon#about to read 4, iclass 7, count 0 2006.281.07:45:42.56#ibcon#read 4, iclass 7, count 0 2006.281.07:45:42.56#ibcon#about to read 5, iclass 7, count 0 2006.281.07:45:42.56#ibcon#read 5, iclass 7, count 0 2006.281.07:45:42.56#ibcon#about to read 6, iclass 7, count 0 2006.281.07:45:42.56#ibcon#read 6, iclass 7, count 0 2006.281.07:45:42.56#ibcon#end of sib2, iclass 7, count 0 2006.281.07:45:42.56#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:45:42.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:45:42.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:45:42.56#ibcon#*before write, iclass 7, count 0 2006.281.07:45:42.56#ibcon#enter sib2, iclass 7, count 0 2006.281.07:45:42.56#ibcon#flushed, iclass 7, count 0 2006.281.07:45:42.56#ibcon#about to write, iclass 7, count 0 2006.281.07:45:42.56#ibcon#wrote, iclass 7, count 0 2006.281.07:45:42.56#ibcon#about to read 3, iclass 7, count 0 2006.281.07:45:42.60#ibcon#read 3, iclass 7, count 0 2006.281.07:45:42.60#ibcon#about to read 4, iclass 7, count 0 2006.281.07:45:42.60#ibcon#read 4, iclass 7, count 0 2006.281.07:45:42.60#ibcon#about to read 5, iclass 7, count 0 2006.281.07:45:42.60#ibcon#read 5, iclass 7, count 0 2006.281.07:45:42.60#ibcon#about to read 6, iclass 7, count 0 2006.281.07:45:42.60#ibcon#read 6, iclass 7, count 0 2006.281.07:45:42.60#ibcon#end of sib2, iclass 7, count 0 2006.281.07:45:42.60#ibcon#*after write, iclass 7, count 0 2006.281.07:45:42.60#ibcon#*before return 0, iclass 7, count 0 2006.281.07:45:42.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:42.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.07:45:42.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:45:42.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:45:42.60$vc4f8/vb=2,5 2006.281.07:45:42.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.07:45:42.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.07:45:42.60#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:42.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:42.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:42.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:42.66#ibcon#enter wrdev, iclass 11, count 2 2006.281.07:45:42.66#ibcon#first serial, iclass 11, count 2 2006.281.07:45:42.66#ibcon#enter sib2, iclass 11, count 2 2006.281.07:45:42.66#ibcon#flushed, iclass 11, count 2 2006.281.07:45:42.66#ibcon#about to write, iclass 11, count 2 2006.281.07:45:42.66#ibcon#wrote, iclass 11, count 2 2006.281.07:45:42.66#ibcon#about to read 3, iclass 11, count 2 2006.281.07:45:42.68#ibcon#read 3, iclass 11, count 2 2006.281.07:45:42.68#ibcon#about to read 4, iclass 11, count 2 2006.281.07:45:42.68#ibcon#read 4, iclass 11, count 2 2006.281.07:45:42.68#ibcon#about to read 5, iclass 11, count 2 2006.281.07:45:42.68#ibcon#read 5, iclass 11, count 2 2006.281.07:45:42.68#ibcon#about to read 6, iclass 11, count 2 2006.281.07:45:42.68#ibcon#read 6, iclass 11, count 2 2006.281.07:45:42.68#ibcon#end of sib2, iclass 11, count 2 2006.281.07:45:42.68#ibcon#*mode == 0, iclass 11, count 2 2006.281.07:45:42.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.07:45:42.68#ibcon#[27=AT02-05\r\n] 2006.281.07:45:42.68#ibcon#*before write, iclass 11, count 2 2006.281.07:45:42.68#ibcon#enter sib2, iclass 11, count 2 2006.281.07:45:42.68#ibcon#flushed, iclass 11, count 2 2006.281.07:45:42.68#ibcon#about to write, iclass 11, count 2 2006.281.07:45:42.68#ibcon#wrote, iclass 11, count 2 2006.281.07:45:42.68#ibcon#about to read 3, iclass 11, count 2 2006.281.07:45:42.71#ibcon#read 3, iclass 11, count 2 2006.281.07:45:42.71#ibcon#about to read 4, iclass 11, count 2 2006.281.07:45:42.71#ibcon#read 4, iclass 11, count 2 2006.281.07:45:42.71#ibcon#about to read 5, iclass 11, count 2 2006.281.07:45:42.71#ibcon#read 5, iclass 11, count 2 2006.281.07:45:42.71#ibcon#about to read 6, iclass 11, count 2 2006.281.07:45:42.71#ibcon#read 6, iclass 11, count 2 2006.281.07:45:42.71#ibcon#end of sib2, iclass 11, count 2 2006.281.07:45:42.71#ibcon#*after write, iclass 11, count 2 2006.281.07:45:42.71#ibcon#*before return 0, iclass 11, count 2 2006.281.07:45:42.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:42.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.07:45:42.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.07:45:42.71#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:42.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:42.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:42.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:42.83#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:45:42.83#ibcon#first serial, iclass 11, count 0 2006.281.07:45:42.83#ibcon#enter sib2, iclass 11, count 0 2006.281.07:45:42.83#ibcon#flushed, iclass 11, count 0 2006.281.07:45:42.83#ibcon#about to write, iclass 11, count 0 2006.281.07:45:42.83#ibcon#wrote, iclass 11, count 0 2006.281.07:45:42.83#ibcon#about to read 3, iclass 11, count 0 2006.281.07:45:42.85#ibcon#read 3, iclass 11, count 0 2006.281.07:45:42.85#ibcon#about to read 4, iclass 11, count 0 2006.281.07:45:42.85#ibcon#read 4, iclass 11, count 0 2006.281.07:45:42.85#ibcon#about to read 5, iclass 11, count 0 2006.281.07:45:42.85#ibcon#read 5, iclass 11, count 0 2006.281.07:45:42.85#ibcon#about to read 6, iclass 11, count 0 2006.281.07:45:42.85#ibcon#read 6, iclass 11, count 0 2006.281.07:45:42.85#ibcon#end of sib2, iclass 11, count 0 2006.281.07:45:42.85#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:45:42.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:45:42.85#ibcon#[27=USB\r\n] 2006.281.07:45:42.85#ibcon#*before write, iclass 11, count 0 2006.281.07:45:42.85#ibcon#enter sib2, iclass 11, count 0 2006.281.07:45:42.85#ibcon#flushed, iclass 11, count 0 2006.281.07:45:42.85#ibcon#about to write, iclass 11, count 0 2006.281.07:45:42.85#ibcon#wrote, iclass 11, count 0 2006.281.07:45:42.85#ibcon#about to read 3, iclass 11, count 0 2006.281.07:45:42.88#ibcon#read 3, iclass 11, count 0 2006.281.07:45:42.88#ibcon#about to read 4, iclass 11, count 0 2006.281.07:45:42.88#ibcon#read 4, iclass 11, count 0 2006.281.07:45:42.88#ibcon#about to read 5, iclass 11, count 0 2006.281.07:45:42.88#ibcon#read 5, iclass 11, count 0 2006.281.07:45:42.88#ibcon#about to read 6, iclass 11, count 0 2006.281.07:45:42.88#ibcon#read 6, iclass 11, count 0 2006.281.07:45:42.88#ibcon#end of sib2, iclass 11, count 0 2006.281.07:45:42.88#ibcon#*after write, iclass 11, count 0 2006.281.07:45:42.88#ibcon#*before return 0, iclass 11, count 0 2006.281.07:45:42.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:42.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.07:45:42.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:45:42.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:45:42.88$vc4f8/vblo=3,656.99 2006.281.07:45:42.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.07:45:42.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.07:45:42.88#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:42.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:42.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:42.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:42.88#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:45:42.88#ibcon#first serial, iclass 13, count 0 2006.281.07:45:42.88#ibcon#enter sib2, iclass 13, count 0 2006.281.07:45:42.88#ibcon#flushed, iclass 13, count 0 2006.281.07:45:42.88#ibcon#about to write, iclass 13, count 0 2006.281.07:45:42.88#ibcon#wrote, iclass 13, count 0 2006.281.07:45:42.88#ibcon#about to read 3, iclass 13, count 0 2006.281.07:45:42.90#ibcon#read 3, iclass 13, count 0 2006.281.07:45:42.90#ibcon#about to read 4, iclass 13, count 0 2006.281.07:45:42.90#ibcon#read 4, iclass 13, count 0 2006.281.07:45:42.90#ibcon#about to read 5, iclass 13, count 0 2006.281.07:45:42.90#ibcon#read 5, iclass 13, count 0 2006.281.07:45:42.90#ibcon#about to read 6, iclass 13, count 0 2006.281.07:45:42.90#ibcon#read 6, iclass 13, count 0 2006.281.07:45:42.90#ibcon#end of sib2, iclass 13, count 0 2006.281.07:45:42.90#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:45:42.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:45:42.90#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:45:42.90#ibcon#*before write, iclass 13, count 0 2006.281.07:45:42.90#ibcon#enter sib2, iclass 13, count 0 2006.281.07:45:42.90#ibcon#flushed, iclass 13, count 0 2006.281.07:45:42.90#ibcon#about to write, iclass 13, count 0 2006.281.07:45:42.90#ibcon#wrote, iclass 13, count 0 2006.281.07:45:42.90#ibcon#about to read 3, iclass 13, count 0 2006.281.07:45:42.94#ibcon#read 3, iclass 13, count 0 2006.281.07:45:42.94#ibcon#about to read 4, iclass 13, count 0 2006.281.07:45:42.94#ibcon#read 4, iclass 13, count 0 2006.281.07:45:42.94#ibcon#about to read 5, iclass 13, count 0 2006.281.07:45:42.94#ibcon#read 5, iclass 13, count 0 2006.281.07:45:42.94#ibcon#about to read 6, iclass 13, count 0 2006.281.07:45:42.94#ibcon#read 6, iclass 13, count 0 2006.281.07:45:42.94#ibcon#end of sib2, iclass 13, count 0 2006.281.07:45:42.94#ibcon#*after write, iclass 13, count 0 2006.281.07:45:42.94#ibcon#*before return 0, iclass 13, count 0 2006.281.07:45:42.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:42.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.07:45:42.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:45:42.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:45:42.94$vc4f8/vb=3,4 2006.281.07:45:42.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.07:45:42.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.07:45:42.94#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:42.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:43.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:43.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:43.01#ibcon#enter wrdev, iclass 15, count 2 2006.281.07:45:43.01#ibcon#first serial, iclass 15, count 2 2006.281.07:45:43.01#ibcon#enter sib2, iclass 15, count 2 2006.281.07:45:43.01#ibcon#flushed, iclass 15, count 2 2006.281.07:45:43.01#ibcon#about to write, iclass 15, count 2 2006.281.07:45:43.01#ibcon#wrote, iclass 15, count 2 2006.281.07:45:43.01#ibcon#about to read 3, iclass 15, count 2 2006.281.07:45:43.02#ibcon#read 3, iclass 15, count 2 2006.281.07:45:43.02#ibcon#about to read 4, iclass 15, count 2 2006.281.07:45:43.02#ibcon#read 4, iclass 15, count 2 2006.281.07:45:43.02#ibcon#about to read 5, iclass 15, count 2 2006.281.07:45:43.02#ibcon#read 5, iclass 15, count 2 2006.281.07:45:43.02#ibcon#about to read 6, iclass 15, count 2 2006.281.07:45:43.02#ibcon#read 6, iclass 15, count 2 2006.281.07:45:43.02#ibcon#end of sib2, iclass 15, count 2 2006.281.07:45:43.02#ibcon#*mode == 0, iclass 15, count 2 2006.281.07:45:43.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.07:45:43.02#ibcon#[27=AT03-04\r\n] 2006.281.07:45:43.02#ibcon#*before write, iclass 15, count 2 2006.281.07:45:43.02#ibcon#enter sib2, iclass 15, count 2 2006.281.07:45:43.02#ibcon#flushed, iclass 15, count 2 2006.281.07:45:43.02#ibcon#about to write, iclass 15, count 2 2006.281.07:45:43.02#ibcon#wrote, iclass 15, count 2 2006.281.07:45:43.02#ibcon#about to read 3, iclass 15, count 2 2006.281.07:45:43.05#ibcon#read 3, iclass 15, count 2 2006.281.07:45:43.05#ibcon#about to read 4, iclass 15, count 2 2006.281.07:45:43.05#ibcon#read 4, iclass 15, count 2 2006.281.07:45:43.05#ibcon#about to read 5, iclass 15, count 2 2006.281.07:45:43.05#ibcon#read 5, iclass 15, count 2 2006.281.07:45:43.05#ibcon#about to read 6, iclass 15, count 2 2006.281.07:45:43.05#ibcon#read 6, iclass 15, count 2 2006.281.07:45:43.05#ibcon#end of sib2, iclass 15, count 2 2006.281.07:45:43.05#ibcon#*after write, iclass 15, count 2 2006.281.07:45:43.05#ibcon#*before return 0, iclass 15, count 2 2006.281.07:45:43.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:43.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.07:45:43.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.07:45:43.05#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:43.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:43.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:43.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:43.17#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:45:43.17#ibcon#first serial, iclass 15, count 0 2006.281.07:45:43.17#ibcon#enter sib2, iclass 15, count 0 2006.281.07:45:43.17#ibcon#flushed, iclass 15, count 0 2006.281.07:45:43.17#ibcon#about to write, iclass 15, count 0 2006.281.07:45:43.17#ibcon#wrote, iclass 15, count 0 2006.281.07:45:43.17#ibcon#about to read 3, iclass 15, count 0 2006.281.07:45:43.19#ibcon#read 3, iclass 15, count 0 2006.281.07:45:43.19#ibcon#about to read 4, iclass 15, count 0 2006.281.07:45:43.19#ibcon#read 4, iclass 15, count 0 2006.281.07:45:43.19#ibcon#about to read 5, iclass 15, count 0 2006.281.07:45:43.19#ibcon#read 5, iclass 15, count 0 2006.281.07:45:43.19#ibcon#about to read 6, iclass 15, count 0 2006.281.07:45:43.19#ibcon#read 6, iclass 15, count 0 2006.281.07:45:43.19#ibcon#end of sib2, iclass 15, count 0 2006.281.07:45:43.19#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:45:43.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:45:43.19#ibcon#[27=USB\r\n] 2006.281.07:45:43.19#ibcon#*before write, iclass 15, count 0 2006.281.07:45:43.19#ibcon#enter sib2, iclass 15, count 0 2006.281.07:45:43.19#ibcon#flushed, iclass 15, count 0 2006.281.07:45:43.19#ibcon#about to write, iclass 15, count 0 2006.281.07:45:43.19#ibcon#wrote, iclass 15, count 0 2006.281.07:45:43.19#ibcon#about to read 3, iclass 15, count 0 2006.281.07:45:43.22#ibcon#read 3, iclass 15, count 0 2006.281.07:45:43.22#ibcon#about to read 4, iclass 15, count 0 2006.281.07:45:43.22#ibcon#read 4, iclass 15, count 0 2006.281.07:45:43.22#ibcon#about to read 5, iclass 15, count 0 2006.281.07:45:43.22#ibcon#read 5, iclass 15, count 0 2006.281.07:45:43.22#ibcon#about to read 6, iclass 15, count 0 2006.281.07:45:43.22#ibcon#read 6, iclass 15, count 0 2006.281.07:45:43.22#ibcon#end of sib2, iclass 15, count 0 2006.281.07:45:43.22#ibcon#*after write, iclass 15, count 0 2006.281.07:45:43.22#ibcon#*before return 0, iclass 15, count 0 2006.281.07:45:43.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:43.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.07:45:43.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:45:43.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:45:43.22$vc4f8/vblo=4,712.99 2006.281.07:45:43.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:45:43.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:45:43.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:43.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:43.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:43.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:43.23#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:45:43.23#ibcon#first serial, iclass 17, count 0 2006.281.07:45:43.23#ibcon#enter sib2, iclass 17, count 0 2006.281.07:45:43.23#ibcon#flushed, iclass 17, count 0 2006.281.07:45:43.23#ibcon#about to write, iclass 17, count 0 2006.281.07:45:43.23#ibcon#wrote, iclass 17, count 0 2006.281.07:45:43.23#ibcon#about to read 3, iclass 17, count 0 2006.281.07:45:43.24#ibcon#read 3, iclass 17, count 0 2006.281.07:45:43.24#ibcon#about to read 4, iclass 17, count 0 2006.281.07:45:43.24#ibcon#read 4, iclass 17, count 0 2006.281.07:45:43.24#ibcon#about to read 5, iclass 17, count 0 2006.281.07:45:43.24#ibcon#read 5, iclass 17, count 0 2006.281.07:45:43.24#ibcon#about to read 6, iclass 17, count 0 2006.281.07:45:43.24#ibcon#read 6, iclass 17, count 0 2006.281.07:45:43.24#ibcon#end of sib2, iclass 17, count 0 2006.281.07:45:43.24#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:45:43.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:45:43.27#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:45:43.27#ibcon#*before write, iclass 17, count 0 2006.281.07:45:43.27#ibcon#enter sib2, iclass 17, count 0 2006.281.07:45:43.27#ibcon#flushed, iclass 17, count 0 2006.281.07:45:43.27#ibcon#about to write, iclass 17, count 0 2006.281.07:45:43.27#ibcon#wrote, iclass 17, count 0 2006.281.07:45:43.27#ibcon#about to read 3, iclass 17, count 0 2006.281.07:45:43.30#ibcon#read 3, iclass 17, count 0 2006.281.07:45:43.30#ibcon#about to read 4, iclass 17, count 0 2006.281.07:45:43.30#ibcon#read 4, iclass 17, count 0 2006.281.07:45:43.30#ibcon#about to read 5, iclass 17, count 0 2006.281.07:45:43.30#ibcon#read 5, iclass 17, count 0 2006.281.07:45:43.30#ibcon#about to read 6, iclass 17, count 0 2006.281.07:45:43.30#ibcon#read 6, iclass 17, count 0 2006.281.07:45:43.30#ibcon#end of sib2, iclass 17, count 0 2006.281.07:45:43.30#ibcon#*after write, iclass 17, count 0 2006.281.07:45:43.30#ibcon#*before return 0, iclass 17, count 0 2006.281.07:45:43.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:43.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:45:43.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:45:43.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:45:43.30$vc4f8/vb=4,4 2006.281.07:45:43.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.07:45:43.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.07:45:43.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:43.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:43.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:43.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:43.34#ibcon#enter wrdev, iclass 19, count 2 2006.281.07:45:43.34#ibcon#first serial, iclass 19, count 2 2006.281.07:45:43.34#ibcon#enter sib2, iclass 19, count 2 2006.281.07:45:43.34#ibcon#flushed, iclass 19, count 2 2006.281.07:45:43.34#ibcon#about to write, iclass 19, count 2 2006.281.07:45:43.34#ibcon#wrote, iclass 19, count 2 2006.281.07:45:43.34#ibcon#about to read 3, iclass 19, count 2 2006.281.07:45:43.36#ibcon#read 3, iclass 19, count 2 2006.281.07:45:43.36#ibcon#about to read 4, iclass 19, count 2 2006.281.07:45:43.36#ibcon#read 4, iclass 19, count 2 2006.281.07:45:43.36#ibcon#about to read 5, iclass 19, count 2 2006.281.07:45:43.36#ibcon#read 5, iclass 19, count 2 2006.281.07:45:43.36#ibcon#about to read 6, iclass 19, count 2 2006.281.07:45:43.36#ibcon#read 6, iclass 19, count 2 2006.281.07:45:43.36#ibcon#end of sib2, iclass 19, count 2 2006.281.07:45:43.36#ibcon#*mode == 0, iclass 19, count 2 2006.281.07:45:43.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.07:45:43.36#ibcon#[27=AT04-04\r\n] 2006.281.07:45:43.36#ibcon#*before write, iclass 19, count 2 2006.281.07:45:43.36#ibcon#enter sib2, iclass 19, count 2 2006.281.07:45:43.36#ibcon#flushed, iclass 19, count 2 2006.281.07:45:43.36#ibcon#about to write, iclass 19, count 2 2006.281.07:45:43.36#ibcon#wrote, iclass 19, count 2 2006.281.07:45:43.36#ibcon#about to read 3, iclass 19, count 2 2006.281.07:45:43.39#ibcon#read 3, iclass 19, count 2 2006.281.07:45:43.39#ibcon#about to read 4, iclass 19, count 2 2006.281.07:45:43.39#ibcon#read 4, iclass 19, count 2 2006.281.07:45:43.39#ibcon#about to read 5, iclass 19, count 2 2006.281.07:45:43.39#ibcon#read 5, iclass 19, count 2 2006.281.07:45:43.39#ibcon#about to read 6, iclass 19, count 2 2006.281.07:45:43.39#ibcon#read 6, iclass 19, count 2 2006.281.07:45:43.39#ibcon#end of sib2, iclass 19, count 2 2006.281.07:45:43.39#ibcon#*after write, iclass 19, count 2 2006.281.07:45:43.39#ibcon#*before return 0, iclass 19, count 2 2006.281.07:45:43.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:43.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.07:45:43.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.07:45:43.39#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:43.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:43.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:43.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:43.52#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:45:43.52#ibcon#first serial, iclass 19, count 0 2006.281.07:45:43.52#ibcon#enter sib2, iclass 19, count 0 2006.281.07:45:43.52#ibcon#flushed, iclass 19, count 0 2006.281.07:45:43.52#ibcon#about to write, iclass 19, count 0 2006.281.07:45:43.52#ibcon#wrote, iclass 19, count 0 2006.281.07:45:43.52#ibcon#about to read 3, iclass 19, count 0 2006.281.07:45:43.53#ibcon#read 3, iclass 19, count 0 2006.281.07:45:43.53#ibcon#about to read 4, iclass 19, count 0 2006.281.07:45:43.53#ibcon#read 4, iclass 19, count 0 2006.281.07:45:43.53#ibcon#about to read 5, iclass 19, count 0 2006.281.07:45:43.53#ibcon#read 5, iclass 19, count 0 2006.281.07:45:43.53#ibcon#about to read 6, iclass 19, count 0 2006.281.07:45:43.53#ibcon#read 6, iclass 19, count 0 2006.281.07:45:43.53#ibcon#end of sib2, iclass 19, count 0 2006.281.07:45:43.53#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:45:43.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:45:43.53#ibcon#[27=USB\r\n] 2006.281.07:45:43.53#ibcon#*before write, iclass 19, count 0 2006.281.07:45:43.53#ibcon#enter sib2, iclass 19, count 0 2006.281.07:45:43.53#ibcon#flushed, iclass 19, count 0 2006.281.07:45:43.53#ibcon#about to write, iclass 19, count 0 2006.281.07:45:43.53#ibcon#wrote, iclass 19, count 0 2006.281.07:45:43.53#ibcon#about to read 3, iclass 19, count 0 2006.281.07:45:43.56#ibcon#read 3, iclass 19, count 0 2006.281.07:45:43.56#ibcon#about to read 4, iclass 19, count 0 2006.281.07:45:43.56#ibcon#read 4, iclass 19, count 0 2006.281.07:45:43.56#ibcon#about to read 5, iclass 19, count 0 2006.281.07:45:43.56#ibcon#read 5, iclass 19, count 0 2006.281.07:45:43.56#ibcon#about to read 6, iclass 19, count 0 2006.281.07:45:43.56#ibcon#read 6, iclass 19, count 0 2006.281.07:45:43.56#ibcon#end of sib2, iclass 19, count 0 2006.281.07:45:43.56#ibcon#*after write, iclass 19, count 0 2006.281.07:45:43.56#ibcon#*before return 0, iclass 19, count 0 2006.281.07:45:43.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:43.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.07:45:43.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:45:43.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:45:43.56$vc4f8/vblo=5,744.99 2006.281.07:45:43.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.07:45:43.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.07:45:43.56#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:43.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:43.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:43.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:43.56#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:45:43.56#ibcon#first serial, iclass 21, count 0 2006.281.07:45:43.56#ibcon#enter sib2, iclass 21, count 0 2006.281.07:45:43.56#ibcon#flushed, iclass 21, count 0 2006.281.07:45:43.56#ibcon#about to write, iclass 21, count 0 2006.281.07:45:43.56#ibcon#wrote, iclass 21, count 0 2006.281.07:45:43.56#ibcon#about to read 3, iclass 21, count 0 2006.281.07:45:43.58#ibcon#read 3, iclass 21, count 0 2006.281.07:45:43.58#ibcon#about to read 4, iclass 21, count 0 2006.281.07:45:43.58#ibcon#read 4, iclass 21, count 0 2006.281.07:45:43.58#ibcon#about to read 5, iclass 21, count 0 2006.281.07:45:43.58#ibcon#read 5, iclass 21, count 0 2006.281.07:45:43.58#ibcon#about to read 6, iclass 21, count 0 2006.281.07:45:43.58#ibcon#read 6, iclass 21, count 0 2006.281.07:45:43.58#ibcon#end of sib2, iclass 21, count 0 2006.281.07:45:43.58#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:45:43.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:45:43.58#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:45:43.58#ibcon#*before write, iclass 21, count 0 2006.281.07:45:43.58#ibcon#enter sib2, iclass 21, count 0 2006.281.07:45:43.58#ibcon#flushed, iclass 21, count 0 2006.281.07:45:43.58#ibcon#about to write, iclass 21, count 0 2006.281.07:45:43.58#ibcon#wrote, iclass 21, count 0 2006.281.07:45:43.58#ibcon#about to read 3, iclass 21, count 0 2006.281.07:45:43.62#ibcon#read 3, iclass 21, count 0 2006.281.07:45:43.62#ibcon#about to read 4, iclass 21, count 0 2006.281.07:45:43.62#ibcon#read 4, iclass 21, count 0 2006.281.07:45:43.62#ibcon#about to read 5, iclass 21, count 0 2006.281.07:45:43.62#ibcon#read 5, iclass 21, count 0 2006.281.07:45:43.63#ibcon#about to read 6, iclass 21, count 0 2006.281.07:45:43.63#ibcon#read 6, iclass 21, count 0 2006.281.07:45:43.63#ibcon#end of sib2, iclass 21, count 0 2006.281.07:45:43.63#ibcon#*after write, iclass 21, count 0 2006.281.07:45:43.63#ibcon#*before return 0, iclass 21, count 0 2006.281.07:45:43.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:43.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.07:45:43.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:45:43.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:45:43.63$vc4f8/vb=5,4 2006.281.07:45:43.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.07:45:43.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.07:45:43.63#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:43.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:43.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:43.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:43.67#ibcon#enter wrdev, iclass 23, count 2 2006.281.07:45:43.67#ibcon#first serial, iclass 23, count 2 2006.281.07:45:43.67#ibcon#enter sib2, iclass 23, count 2 2006.281.07:45:43.67#ibcon#flushed, iclass 23, count 2 2006.281.07:45:43.67#ibcon#about to write, iclass 23, count 2 2006.281.07:45:43.67#ibcon#wrote, iclass 23, count 2 2006.281.07:45:43.67#ibcon#about to read 3, iclass 23, count 2 2006.281.07:45:43.69#ibcon#read 3, iclass 23, count 2 2006.281.07:45:43.69#ibcon#about to read 4, iclass 23, count 2 2006.281.07:45:43.69#ibcon#read 4, iclass 23, count 2 2006.281.07:45:43.69#ibcon#about to read 5, iclass 23, count 2 2006.281.07:45:43.69#ibcon#read 5, iclass 23, count 2 2006.281.07:45:43.69#ibcon#about to read 6, iclass 23, count 2 2006.281.07:45:43.69#ibcon#read 6, iclass 23, count 2 2006.281.07:45:43.69#ibcon#end of sib2, iclass 23, count 2 2006.281.07:45:43.69#ibcon#*mode == 0, iclass 23, count 2 2006.281.07:45:43.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.07:45:43.69#ibcon#[27=AT05-04\r\n] 2006.281.07:45:43.69#ibcon#*before write, iclass 23, count 2 2006.281.07:45:43.69#ibcon#enter sib2, iclass 23, count 2 2006.281.07:45:43.69#ibcon#flushed, iclass 23, count 2 2006.281.07:45:43.69#ibcon#about to write, iclass 23, count 2 2006.281.07:45:43.69#ibcon#wrote, iclass 23, count 2 2006.281.07:45:43.69#ibcon#about to read 3, iclass 23, count 2 2006.281.07:45:43.72#ibcon#read 3, iclass 23, count 2 2006.281.07:45:43.72#ibcon#about to read 4, iclass 23, count 2 2006.281.07:45:43.72#ibcon#read 4, iclass 23, count 2 2006.281.07:45:43.72#ibcon#about to read 5, iclass 23, count 2 2006.281.07:45:43.72#ibcon#read 5, iclass 23, count 2 2006.281.07:45:43.72#ibcon#about to read 6, iclass 23, count 2 2006.281.07:45:43.72#ibcon#read 6, iclass 23, count 2 2006.281.07:45:43.72#ibcon#end of sib2, iclass 23, count 2 2006.281.07:45:43.72#ibcon#*after write, iclass 23, count 2 2006.281.07:45:43.72#ibcon#*before return 0, iclass 23, count 2 2006.281.07:45:43.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:43.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.07:45:43.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.07:45:43.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:43.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:43.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:43.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:43.84#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:45:43.84#ibcon#first serial, iclass 23, count 0 2006.281.07:45:43.84#ibcon#enter sib2, iclass 23, count 0 2006.281.07:45:43.84#ibcon#flushed, iclass 23, count 0 2006.281.07:45:43.84#ibcon#about to write, iclass 23, count 0 2006.281.07:45:43.84#ibcon#wrote, iclass 23, count 0 2006.281.07:45:43.84#ibcon#about to read 3, iclass 23, count 0 2006.281.07:45:43.86#ibcon#read 3, iclass 23, count 0 2006.281.07:45:43.86#ibcon#about to read 4, iclass 23, count 0 2006.281.07:45:43.86#ibcon#read 4, iclass 23, count 0 2006.281.07:45:43.86#ibcon#about to read 5, iclass 23, count 0 2006.281.07:45:43.86#ibcon#read 5, iclass 23, count 0 2006.281.07:45:43.86#ibcon#about to read 6, iclass 23, count 0 2006.281.07:45:43.86#ibcon#read 6, iclass 23, count 0 2006.281.07:45:43.86#ibcon#end of sib2, iclass 23, count 0 2006.281.07:45:43.86#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:45:43.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:45:43.86#ibcon#[27=USB\r\n] 2006.281.07:45:43.86#ibcon#*before write, iclass 23, count 0 2006.281.07:45:43.86#ibcon#enter sib2, iclass 23, count 0 2006.281.07:45:43.86#ibcon#flushed, iclass 23, count 0 2006.281.07:45:43.86#ibcon#about to write, iclass 23, count 0 2006.281.07:45:43.86#ibcon#wrote, iclass 23, count 0 2006.281.07:45:43.86#ibcon#about to read 3, iclass 23, count 0 2006.281.07:45:43.89#ibcon#read 3, iclass 23, count 0 2006.281.07:45:43.89#ibcon#about to read 4, iclass 23, count 0 2006.281.07:45:43.89#ibcon#read 4, iclass 23, count 0 2006.281.07:45:43.89#ibcon#about to read 5, iclass 23, count 0 2006.281.07:45:43.89#ibcon#read 5, iclass 23, count 0 2006.281.07:45:43.89#ibcon#about to read 6, iclass 23, count 0 2006.281.07:45:43.89#ibcon#read 6, iclass 23, count 0 2006.281.07:45:43.89#ibcon#end of sib2, iclass 23, count 0 2006.281.07:45:43.89#ibcon#*after write, iclass 23, count 0 2006.281.07:45:43.89#ibcon#*before return 0, iclass 23, count 0 2006.281.07:45:43.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:43.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.07:45:43.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:45:43.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:45:43.89$vc4f8/vblo=6,752.99 2006.281.07:45:43.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.07:45:43.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.07:45:43.90#ibcon#ireg 17 cls_cnt 0 2006.281.07:45:43.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:43.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:43.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:43.90#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:45:43.90#ibcon#first serial, iclass 25, count 0 2006.281.07:45:43.90#ibcon#enter sib2, iclass 25, count 0 2006.281.07:45:43.90#ibcon#flushed, iclass 25, count 0 2006.281.07:45:43.90#ibcon#about to write, iclass 25, count 0 2006.281.07:45:43.90#ibcon#wrote, iclass 25, count 0 2006.281.07:45:43.90#ibcon#about to read 3, iclass 25, count 0 2006.281.07:45:43.91#ibcon#read 3, iclass 25, count 0 2006.281.07:45:43.91#ibcon#about to read 4, iclass 25, count 0 2006.281.07:45:43.91#ibcon#read 4, iclass 25, count 0 2006.281.07:45:43.91#ibcon#about to read 5, iclass 25, count 0 2006.281.07:45:43.91#ibcon#read 5, iclass 25, count 0 2006.281.07:45:43.91#ibcon#about to read 6, iclass 25, count 0 2006.281.07:45:43.91#ibcon#read 6, iclass 25, count 0 2006.281.07:45:43.91#ibcon#end of sib2, iclass 25, count 0 2006.281.07:45:43.91#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:45:43.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:45:43.91#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:45:43.93#ibcon#*before write, iclass 25, count 0 2006.281.07:45:43.93#ibcon#enter sib2, iclass 25, count 0 2006.281.07:45:43.93#ibcon#flushed, iclass 25, count 0 2006.281.07:45:43.93#ibcon#about to write, iclass 25, count 0 2006.281.07:45:43.93#ibcon#wrote, iclass 25, count 0 2006.281.07:45:43.93#ibcon#about to read 3, iclass 25, count 0 2006.281.07:45:43.97#ibcon#read 3, iclass 25, count 0 2006.281.07:45:43.97#ibcon#about to read 4, iclass 25, count 0 2006.281.07:45:43.97#ibcon#read 4, iclass 25, count 0 2006.281.07:45:43.97#ibcon#about to read 5, iclass 25, count 0 2006.281.07:45:43.97#ibcon#read 5, iclass 25, count 0 2006.281.07:45:43.97#ibcon#about to read 6, iclass 25, count 0 2006.281.07:45:43.97#ibcon#read 6, iclass 25, count 0 2006.281.07:45:43.97#ibcon#end of sib2, iclass 25, count 0 2006.281.07:45:43.97#ibcon#*after write, iclass 25, count 0 2006.281.07:45:43.97#ibcon#*before return 0, iclass 25, count 0 2006.281.07:45:43.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:43.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.07:45:43.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:45:43.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:45:43.97$vc4f8/vb=6,4 2006.281.07:45:43.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.07:45:43.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.07:45:43.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:45:43.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:44.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:44.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:44.01#ibcon#enter wrdev, iclass 27, count 2 2006.281.07:45:44.01#ibcon#first serial, iclass 27, count 2 2006.281.07:45:44.01#ibcon#enter sib2, iclass 27, count 2 2006.281.07:45:44.01#ibcon#flushed, iclass 27, count 2 2006.281.07:45:44.01#ibcon#about to write, iclass 27, count 2 2006.281.07:45:44.01#ibcon#wrote, iclass 27, count 2 2006.281.07:45:44.01#ibcon#about to read 3, iclass 27, count 2 2006.281.07:45:44.03#ibcon#read 3, iclass 27, count 2 2006.281.07:45:44.03#ibcon#about to read 4, iclass 27, count 2 2006.281.07:45:44.03#ibcon#read 4, iclass 27, count 2 2006.281.07:45:44.03#ibcon#about to read 5, iclass 27, count 2 2006.281.07:45:44.03#ibcon#read 5, iclass 27, count 2 2006.281.07:45:44.03#ibcon#about to read 6, iclass 27, count 2 2006.281.07:45:44.03#ibcon#read 6, iclass 27, count 2 2006.281.07:45:44.03#ibcon#end of sib2, iclass 27, count 2 2006.281.07:45:44.03#ibcon#*mode == 0, iclass 27, count 2 2006.281.07:45:44.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.07:45:44.03#ibcon#[27=AT06-04\r\n] 2006.281.07:45:44.03#ibcon#*before write, iclass 27, count 2 2006.281.07:45:44.03#ibcon#enter sib2, iclass 27, count 2 2006.281.07:45:44.03#ibcon#flushed, iclass 27, count 2 2006.281.07:45:44.03#ibcon#about to write, iclass 27, count 2 2006.281.07:45:44.03#ibcon#wrote, iclass 27, count 2 2006.281.07:45:44.03#ibcon#about to read 3, iclass 27, count 2 2006.281.07:45:44.06#ibcon#read 3, iclass 27, count 2 2006.281.07:45:44.06#ibcon#about to read 4, iclass 27, count 2 2006.281.07:45:44.06#ibcon#read 4, iclass 27, count 2 2006.281.07:45:44.06#ibcon#about to read 5, iclass 27, count 2 2006.281.07:45:44.06#ibcon#read 5, iclass 27, count 2 2006.281.07:45:44.06#ibcon#about to read 6, iclass 27, count 2 2006.281.07:45:44.06#ibcon#read 6, iclass 27, count 2 2006.281.07:45:44.06#ibcon#end of sib2, iclass 27, count 2 2006.281.07:45:44.06#ibcon#*after write, iclass 27, count 2 2006.281.07:45:44.06#ibcon#*before return 0, iclass 27, count 2 2006.281.07:45:44.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:44.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.07:45:44.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.07:45:44.06#ibcon#ireg 7 cls_cnt 0 2006.281.07:45:44.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:44.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:44.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:44.18#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:45:44.18#ibcon#first serial, iclass 27, count 0 2006.281.07:45:44.18#ibcon#enter sib2, iclass 27, count 0 2006.281.07:45:44.18#ibcon#flushed, iclass 27, count 0 2006.281.07:45:44.18#ibcon#about to write, iclass 27, count 0 2006.281.07:45:44.18#ibcon#wrote, iclass 27, count 0 2006.281.07:45:44.18#ibcon#about to read 3, iclass 27, count 0 2006.281.07:45:44.20#ibcon#read 3, iclass 27, count 0 2006.281.07:45:44.20#ibcon#about to read 4, iclass 27, count 0 2006.281.07:45:44.20#ibcon#read 4, iclass 27, count 0 2006.281.07:45:44.20#ibcon#about to read 5, iclass 27, count 0 2006.281.07:45:44.20#ibcon#read 5, iclass 27, count 0 2006.281.07:45:44.20#ibcon#about to read 6, iclass 27, count 0 2006.281.07:45:44.20#ibcon#read 6, iclass 27, count 0 2006.281.07:45:44.20#ibcon#end of sib2, iclass 27, count 0 2006.281.07:45:44.20#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:45:44.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:45:44.20#ibcon#[27=USB\r\n] 2006.281.07:45:44.20#ibcon#*before write, iclass 27, count 0 2006.281.07:45:44.20#ibcon#enter sib2, iclass 27, count 0 2006.281.07:45:44.20#ibcon#flushed, iclass 27, count 0 2006.281.07:45:44.20#ibcon#about to write, iclass 27, count 0 2006.281.07:45:44.20#ibcon#wrote, iclass 27, count 0 2006.281.07:45:44.20#ibcon#about to read 3, iclass 27, count 0 2006.281.07:45:44.23#abcon#<5=/13 2.2 9.5 21.00 511001.2\r\n> 2006.281.07:45:44.23#ibcon#read 3, iclass 27, count 0 2006.281.07:45:44.23#ibcon#about to read 4, iclass 27, count 0 2006.281.07:45:44.23#ibcon#read 4, iclass 27, count 0 2006.281.07:45:44.23#ibcon#about to read 5, iclass 27, count 0 2006.281.07:45:44.23#ibcon#read 5, iclass 27, count 0 2006.281.07:45:44.23#ibcon#about to read 6, iclass 27, count 0 2006.281.07:45:44.23#ibcon#read 6, iclass 27, count 0 2006.281.07:45:44.23#ibcon#end of sib2, iclass 27, count 0 2006.281.07:45:44.23#ibcon#*after write, iclass 27, count 0 2006.281.07:45:44.23#ibcon#*before return 0, iclass 27, count 0 2006.281.07:45:44.23#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:44.23#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.07:45:44.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:45:44.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:45:44.23$vc4f8/vabw=wide 2006.281.07:45:44.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:45:44.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:45:44.23#ibcon#ireg 8 cls_cnt 0 2006.281.07:45:44.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:45:44.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:45:44.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:45:44.23#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:45:44.23#ibcon#first serial, iclass 32, count 0 2006.281.07:45:44.23#ibcon#enter sib2, iclass 32, count 0 2006.281.07:45:44.24#ibcon#flushed, iclass 32, count 0 2006.281.07:45:44.24#ibcon#about to write, iclass 32, count 0 2006.281.07:45:44.24#ibcon#wrote, iclass 32, count 0 2006.281.07:45:44.24#ibcon#about to read 3, iclass 32, count 0 2006.281.07:45:44.25#abcon#{5=INTERFACE CLEAR} 2006.281.07:45:44.25#ibcon#read 3, iclass 32, count 0 2006.281.07:45:44.25#ibcon#about to read 4, iclass 32, count 0 2006.281.07:45:44.25#ibcon#read 4, iclass 32, count 0 2006.281.07:45:44.25#ibcon#about to read 5, iclass 32, count 0 2006.281.07:45:44.25#ibcon#read 5, iclass 32, count 0 2006.281.07:45:44.25#ibcon#about to read 6, iclass 32, count 0 2006.281.07:45:44.25#ibcon#read 6, iclass 32, count 0 2006.281.07:45:44.25#ibcon#end of sib2, iclass 32, count 0 2006.281.07:45:44.25#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:45:44.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:45:44.25#ibcon#[25=BW32\r\n] 2006.281.07:45:44.25#ibcon#*before write, iclass 32, count 0 2006.281.07:45:44.25#ibcon#enter sib2, iclass 32, count 0 2006.281.07:45:44.25#ibcon#flushed, iclass 32, count 0 2006.281.07:45:44.25#ibcon#about to write, iclass 32, count 0 2006.281.07:45:44.25#ibcon#wrote, iclass 32, count 0 2006.281.07:45:44.25#ibcon#about to read 3, iclass 32, count 0 2006.281.07:45:44.28#ibcon#read 3, iclass 32, count 0 2006.281.07:45:44.28#ibcon#about to read 4, iclass 32, count 0 2006.281.07:45:44.28#ibcon#read 4, iclass 32, count 0 2006.281.07:45:44.28#ibcon#about to read 5, iclass 32, count 0 2006.281.07:45:44.28#ibcon#read 5, iclass 32, count 0 2006.281.07:45:44.28#ibcon#about to read 6, iclass 32, count 0 2006.281.07:45:44.28#ibcon#read 6, iclass 32, count 0 2006.281.07:45:44.28#ibcon#end of sib2, iclass 32, count 0 2006.281.07:45:44.28#ibcon#*after write, iclass 32, count 0 2006.281.07:45:44.28#ibcon#*before return 0, iclass 32, count 0 2006.281.07:45:44.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:45:44.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:45:44.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:45:44.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:45:44.28$vc4f8/vbbw=wide 2006.281.07:45:44.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:45:44.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:45:44.28#ibcon#ireg 8 cls_cnt 0 2006.281.07:45:44.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:45:44.31#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:45:44.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:45:44.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:45:44.35#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:45:44.35#ibcon#first serial, iclass 34, count 0 2006.281.07:45:44.35#ibcon#enter sib2, iclass 34, count 0 2006.281.07:45:44.35#ibcon#flushed, iclass 34, count 0 2006.281.07:45:44.35#ibcon#about to write, iclass 34, count 0 2006.281.07:45:44.35#ibcon#wrote, iclass 34, count 0 2006.281.07:45:44.35#ibcon#about to read 3, iclass 34, count 0 2006.281.07:45:44.37#ibcon#read 3, iclass 34, count 0 2006.281.07:45:44.37#ibcon#about to read 4, iclass 34, count 0 2006.281.07:45:44.37#ibcon#read 4, iclass 34, count 0 2006.281.07:45:44.37#ibcon#about to read 5, iclass 34, count 0 2006.281.07:45:44.37#ibcon#read 5, iclass 34, count 0 2006.281.07:45:44.37#ibcon#about to read 6, iclass 34, count 0 2006.281.07:45:44.37#ibcon#read 6, iclass 34, count 0 2006.281.07:45:44.37#ibcon#end of sib2, iclass 34, count 0 2006.281.07:45:44.37#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:45:44.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:45:44.37#ibcon#[27=BW32\r\n] 2006.281.07:45:44.37#ibcon#*before write, iclass 34, count 0 2006.281.07:45:44.37#ibcon#enter sib2, iclass 34, count 0 2006.281.07:45:44.37#ibcon#flushed, iclass 34, count 0 2006.281.07:45:44.37#ibcon#about to write, iclass 34, count 0 2006.281.07:45:44.37#ibcon#wrote, iclass 34, count 0 2006.281.07:45:44.37#ibcon#about to read 3, iclass 34, count 0 2006.281.07:45:44.41#ibcon#read 3, iclass 34, count 0 2006.281.07:45:44.41#ibcon#about to read 4, iclass 34, count 0 2006.281.07:45:44.41#ibcon#read 4, iclass 34, count 0 2006.281.07:45:44.41#ibcon#about to read 5, iclass 34, count 0 2006.281.07:45:44.41#ibcon#read 5, iclass 34, count 0 2006.281.07:45:44.41#ibcon#about to read 6, iclass 34, count 0 2006.281.07:45:44.41#ibcon#read 6, iclass 34, count 0 2006.281.07:45:44.41#ibcon#end of sib2, iclass 34, count 0 2006.281.07:45:44.41#ibcon#*after write, iclass 34, count 0 2006.281.07:45:44.41#ibcon#*before return 0, iclass 34, count 0 2006.281.07:45:44.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:45:44.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:45:44.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:45:44.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:45:44.41$4f8m12a/ifd4f 2006.281.07:45:44.41$ifd4f/lo= 2006.281.07:45:44.41$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:45:44.41$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:45:44.41$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:45:44.41$ifd4f/patch= 2006.281.07:45:44.41$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:45:44.41$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:45:44.41$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:45:44.41$4f8m12a/"form=m,16.000,1:2 2006.281.07:45:44.41$4f8m12a/"tpicd 2006.281.07:45:44.41$4f8m12a/echo=off 2006.281.07:45:44.41$4f8m12a/xlog=off 2006.281.07:45:44.41:!2006.281.07:46:10 2006.281.07:45:54.14#trakl#Source acquired 2006.281.07:45:55.14#flagr#flagr/antenna,acquired 2006.281.07:46:09.14#trakl#Off source 2006.281.07:46:09.14?ERROR st -7 Antenna off-source! 2006.281.07:46:09.14#trakl#az 252.752 el 18.762 azerr*cos(el) 0.0210 elerr 0.0051 2006.281.07:46:10.01:preob 2006.281.07:46:10.14#flagr#flagr/antenna,off-source 2006.281.07:46:11.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:46:11.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:46:11.14/onsource/SLEWING 2006.281.07:46:11.14:!2006.281.07:46:20 2006.281.07:46:15.14#trakl#Source re-acquired 2006.281.07:46:15.14#flagr#flagr/antenna,re-acquired 2006.281.07:46:20.00:data_valid=on 2006.281.07:46:20.00:midob 2006.281.07:46:20.14/onsource/TRACKING 2006.281.07:46:20.14/wx/20.99,1001.2,51 2006.281.07:46:20.26/cable/+6.4867E-03 2006.281.07:46:21.35/va/01,07,usb,yes,34,36 2006.281.07:46:21.35/va/02,06,usb,yes,32,33 2006.281.07:46:21.35/va/03,06,usb,yes,30,30 2006.281.07:46:21.35/va/04,06,usb,yes,33,35 2006.281.07:46:21.35/va/05,07,usb,yes,31,32 2006.281.07:46:21.35/va/06,06,usb,yes,30,29 2006.281.07:46:21.35/va/07,06,usb,yes,30,30 2006.281.07:46:21.35/va/08,06,usb,yes,32,32 2006.281.07:46:21.58/valo/01,532.99,yes,locked 2006.281.07:46:21.58/valo/02,572.99,yes,locked 2006.281.07:46:21.58/valo/03,672.99,yes,locked 2006.281.07:46:21.58/valo/04,832.99,yes,locked 2006.281.07:46:21.58/valo/05,652.99,yes,locked 2006.281.07:46:21.58/valo/06,772.99,yes,locked 2006.281.07:46:21.58/valo/07,832.99,yes,locked 2006.281.07:46:21.58/valo/08,852.99,yes,locked 2006.281.07:46:22.67/vb/01,04,usb,yes,32,30 2006.281.07:46:22.67/vb/02,05,usb,yes,30,31 2006.281.07:46:22.67/vb/03,04,usb,yes,30,34 2006.281.07:46:22.67/vb/04,04,usb,yes,31,31 2006.281.07:46:22.67/vb/05,04,usb,yes,28,33 2006.281.07:46:22.67/vb/06,04,usb,yes,29,33 2006.281.07:46:22.67/vb/07,04,usb,yes,32,32 2006.281.07:46:22.67/vb/08,04,usb,yes,29,33 2006.281.07:46:22.90/vblo/01,632.99,yes,locked 2006.281.07:46:22.90/vblo/02,640.99,yes,locked 2006.281.07:46:22.90/vblo/03,656.99,yes,locked 2006.281.07:46:22.90/vblo/04,712.99,yes,locked 2006.281.07:46:22.90/vblo/05,744.99,yes,locked 2006.281.07:46:22.90/vblo/06,752.99,yes,locked 2006.281.07:46:22.90/vblo/07,734.99,yes,locked 2006.281.07:46:22.90/vblo/08,744.99,yes,locked 2006.281.07:46:23.05/vabw/8 2006.281.07:46:23.20/vbbw/8 2006.281.07:46:23.29/xfe/off,on,12.0 2006.281.07:46:23.67/ifatt/23,28,28,28 2006.281.07:46:24.07/fmout-gps/S +3.11E-07 2006.281.07:46:24.10:!2006.281.07:47:20 2006.281.07:46:30.14#trakl#Off source 2006.281.07:46:30.14?ERROR st -7 Antenna off-source! 2006.281.07:46:30.14#trakl#az 252.811 el 18.694 azerr*cos(el) -0.0025 elerr -0.0163 2006.281.07:46:31.14#flagr#flagr/antenna,off-source 2006.281.07:46:36.14#trakl#Source re-acquired 2006.281.07:46:37.14#flagr#flagr/antenna,re-acquired 2006.281.07:46:53.14#trakl#Off source 2006.281.07:46:53.14?ERROR st -7 Antenna off-source! 2006.281.07:46:53.14#trakl#az 252.875 el 18.620 azerr*cos(el) 0.0170 elerr 0.0036 2006.281.07:46:55.14#flagr#flagr/antenna,off-source 2006.281.07:46:59.14#trakl#Source re-acquired 2006.281.07:47:01.14#flagr#flagr/antenna,re-acquired 2006.281.07:47:20.01:data_valid=off 2006.281.07:47:20.01:postob 2006.281.07:47:20.07/cable/+6.4865E-03 2006.281.07:47:20.07/wx/20.97,1001.1,50 2006.281.07:47:21.07/fmout-gps/S +3.10E-07 2006.281.07:47:21.07:scan_name=281-0748,k06281,60 2006.281.07:47:21.07:source=1538+149,154049.49,144745.9,2000.0,ccw 2006.281.07:47:21.14#trakl#Off source 2006.281.07:47:21.14?ERROR st -7 Antenna off-source! 2006.281.07:47:21.14#trakl#az 252.953 el 18.530 azerr*cos(el) 0.0196 elerr 0.0037 2006.281.07:47:21.14#flagr#flagr/antenna,new-source 2006.281.07:47:22.14:checkk5 2006.281.07:47:22.61/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:47:23.03/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:47:23.44/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:47:23.84/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:47:24.25/chk_obsdata//k5ts1/T2810746??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:47:24.68/chk_obsdata//k5ts2/T2810746??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:47:25.09/chk_obsdata//k5ts3/T2810746??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:47:25.56/chk_obsdata//k5ts4/T2810746??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:47:26.34/k5log//k5ts1_log_newline 2006.281.07:47:27.08/k5log//k5ts2_log_newline 2006.281.07:47:27.86/k5log//k5ts3_log_newline 2006.281.07:47:28.68/k5log//k5ts4_log_newline 2006.281.07:47:28.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:47:28.70:4f8m12a=1 2006.281.07:47:28.70$4f8m12a/echo=on 2006.281.07:47:28.70$4f8m12a/pcalon 2006.281.07:47:28.70$pcalon/"no phase cal control is implemented here 2006.281.07:47:28.70$4f8m12a/"tpicd=stop 2006.281.07:47:28.70$4f8m12a/vc4f8 2006.281.07:47:28.70$vc4f8/valo=1,532.99 2006.281.07:47:28.71#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.07:47:28.71#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.07:47:28.71#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:28.71#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:28.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:28.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:28.71#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:47:28.71#ibcon#first serial, iclass 18, count 0 2006.281.07:47:28.71#ibcon#enter sib2, iclass 18, count 0 2006.281.07:47:28.71#ibcon#flushed, iclass 18, count 0 2006.281.07:47:28.71#ibcon#about to write, iclass 18, count 0 2006.281.07:47:28.71#ibcon#wrote, iclass 18, count 0 2006.281.07:47:28.71#ibcon#about to read 3, iclass 18, count 0 2006.281.07:47:28.72#ibcon#read 3, iclass 18, count 0 2006.281.07:47:28.72#ibcon#about to read 4, iclass 18, count 0 2006.281.07:47:28.72#ibcon#read 4, iclass 18, count 0 2006.281.07:47:28.72#ibcon#about to read 5, iclass 18, count 0 2006.281.07:47:28.72#ibcon#read 5, iclass 18, count 0 2006.281.07:47:28.72#ibcon#about to read 6, iclass 18, count 0 2006.281.07:47:28.72#ibcon#read 6, iclass 18, count 0 2006.281.07:47:28.72#ibcon#end of sib2, iclass 18, count 0 2006.281.07:47:28.72#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:47:28.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:47:28.72#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:47:28.72#ibcon#*before write, iclass 18, count 0 2006.281.07:47:28.72#ibcon#enter sib2, iclass 18, count 0 2006.281.07:47:28.72#ibcon#flushed, iclass 18, count 0 2006.281.07:47:28.72#ibcon#about to write, iclass 18, count 0 2006.281.07:47:28.72#ibcon#wrote, iclass 18, count 0 2006.281.07:47:28.72#ibcon#about to read 3, iclass 18, count 0 2006.281.07:47:28.77#ibcon#read 3, iclass 18, count 0 2006.281.07:47:28.77#ibcon#about to read 4, iclass 18, count 0 2006.281.07:47:28.77#ibcon#read 4, iclass 18, count 0 2006.281.07:47:28.77#ibcon#about to read 5, iclass 18, count 0 2006.281.07:47:28.77#ibcon#read 5, iclass 18, count 0 2006.281.07:47:28.77#ibcon#about to read 6, iclass 18, count 0 2006.281.07:47:28.77#ibcon#read 6, iclass 18, count 0 2006.281.07:47:28.77#ibcon#end of sib2, iclass 18, count 0 2006.281.07:47:28.77#ibcon#*after write, iclass 18, count 0 2006.281.07:47:28.77#ibcon#*before return 0, iclass 18, count 0 2006.281.07:47:28.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:28.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:28.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:47:28.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:47:28.77$vc4f8/va=1,7 2006.281.07:47:28.77#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.07:47:28.77#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.07:47:28.77#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:28.77#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:28.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:28.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:28.77#ibcon#enter wrdev, iclass 20, count 2 2006.281.07:47:28.77#ibcon#first serial, iclass 20, count 2 2006.281.07:47:28.77#ibcon#enter sib2, iclass 20, count 2 2006.281.07:47:28.77#ibcon#flushed, iclass 20, count 2 2006.281.07:47:28.77#ibcon#about to write, iclass 20, count 2 2006.281.07:47:28.77#ibcon#wrote, iclass 20, count 2 2006.281.07:47:28.77#ibcon#about to read 3, iclass 20, count 2 2006.281.07:47:28.79#ibcon#read 3, iclass 20, count 2 2006.281.07:47:28.79#ibcon#about to read 4, iclass 20, count 2 2006.281.07:47:28.79#ibcon#read 4, iclass 20, count 2 2006.281.07:47:28.79#ibcon#about to read 5, iclass 20, count 2 2006.281.07:47:28.79#ibcon#read 5, iclass 20, count 2 2006.281.07:47:28.79#ibcon#about to read 6, iclass 20, count 2 2006.281.07:47:28.79#ibcon#read 6, iclass 20, count 2 2006.281.07:47:28.79#ibcon#end of sib2, iclass 20, count 2 2006.281.07:47:28.79#ibcon#*mode == 0, iclass 20, count 2 2006.281.07:47:28.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.07:47:28.79#ibcon#[25=AT01-07\r\n] 2006.281.07:47:28.79#ibcon#*before write, iclass 20, count 2 2006.281.07:47:28.79#ibcon#enter sib2, iclass 20, count 2 2006.281.07:47:28.79#ibcon#flushed, iclass 20, count 2 2006.281.07:47:28.79#ibcon#about to write, iclass 20, count 2 2006.281.07:47:28.79#ibcon#wrote, iclass 20, count 2 2006.281.07:47:28.79#ibcon#about to read 3, iclass 20, count 2 2006.281.07:47:28.82#ibcon#read 3, iclass 20, count 2 2006.281.07:47:28.82#ibcon#about to read 4, iclass 20, count 2 2006.281.07:47:28.82#ibcon#read 4, iclass 20, count 2 2006.281.07:47:28.82#ibcon#about to read 5, iclass 20, count 2 2006.281.07:47:28.82#ibcon#read 5, iclass 20, count 2 2006.281.07:47:28.82#ibcon#about to read 6, iclass 20, count 2 2006.281.07:47:28.82#ibcon#read 6, iclass 20, count 2 2006.281.07:47:28.82#ibcon#end of sib2, iclass 20, count 2 2006.281.07:47:28.82#ibcon#*after write, iclass 20, count 2 2006.281.07:47:28.82#ibcon#*before return 0, iclass 20, count 2 2006.281.07:47:28.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:28.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:28.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.07:47:28.82#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:28.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:28.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:28.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:28.95#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:47:28.95#ibcon#first serial, iclass 20, count 0 2006.281.07:47:28.95#ibcon#enter sib2, iclass 20, count 0 2006.281.07:47:28.95#ibcon#flushed, iclass 20, count 0 2006.281.07:47:28.95#ibcon#about to write, iclass 20, count 0 2006.281.07:47:28.95#ibcon#wrote, iclass 20, count 0 2006.281.07:47:28.95#ibcon#about to read 3, iclass 20, count 0 2006.281.07:47:28.96#ibcon#read 3, iclass 20, count 0 2006.281.07:47:28.96#ibcon#about to read 4, iclass 20, count 0 2006.281.07:47:28.96#ibcon#read 4, iclass 20, count 0 2006.281.07:47:28.96#ibcon#about to read 5, iclass 20, count 0 2006.281.07:47:28.96#ibcon#read 5, iclass 20, count 0 2006.281.07:47:28.96#ibcon#about to read 6, iclass 20, count 0 2006.281.07:47:28.96#ibcon#read 6, iclass 20, count 0 2006.281.07:47:28.96#ibcon#end of sib2, iclass 20, count 0 2006.281.07:47:28.96#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:47:28.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:47:28.96#ibcon#[25=USB\r\n] 2006.281.07:47:28.96#ibcon#*before write, iclass 20, count 0 2006.281.07:47:28.96#ibcon#enter sib2, iclass 20, count 0 2006.281.07:47:28.96#ibcon#flushed, iclass 20, count 0 2006.281.07:47:28.96#ibcon#about to write, iclass 20, count 0 2006.281.07:47:28.96#ibcon#wrote, iclass 20, count 0 2006.281.07:47:28.96#ibcon#about to read 3, iclass 20, count 0 2006.281.07:47:28.99#ibcon#read 3, iclass 20, count 0 2006.281.07:47:28.99#ibcon#about to read 4, iclass 20, count 0 2006.281.07:47:28.99#ibcon#read 4, iclass 20, count 0 2006.281.07:47:28.99#ibcon#about to read 5, iclass 20, count 0 2006.281.07:47:28.99#ibcon#read 5, iclass 20, count 0 2006.281.07:47:28.99#ibcon#about to read 6, iclass 20, count 0 2006.281.07:47:28.99#ibcon#read 6, iclass 20, count 0 2006.281.07:47:28.99#ibcon#end of sib2, iclass 20, count 0 2006.281.07:47:28.99#ibcon#*after write, iclass 20, count 0 2006.281.07:47:28.99#ibcon#*before return 0, iclass 20, count 0 2006.281.07:47:28.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:28.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:28.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:47:28.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:47:28.99$vc4f8/valo=2,572.99 2006.281.07:47:28.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.07:47:28.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.07:47:28.99#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:28.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:28.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:28.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:28.99#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:47:28.99#ibcon#first serial, iclass 22, count 0 2006.281.07:47:28.99#ibcon#enter sib2, iclass 22, count 0 2006.281.07:47:28.99#ibcon#flushed, iclass 22, count 0 2006.281.07:47:28.99#ibcon#about to write, iclass 22, count 0 2006.281.07:47:28.99#ibcon#wrote, iclass 22, count 0 2006.281.07:47:28.99#ibcon#about to read 3, iclass 22, count 0 2006.281.07:47:29.01#ibcon#read 3, iclass 22, count 0 2006.281.07:47:29.01#ibcon#about to read 4, iclass 22, count 0 2006.281.07:47:29.01#ibcon#read 4, iclass 22, count 0 2006.281.07:47:29.01#ibcon#about to read 5, iclass 22, count 0 2006.281.07:47:29.01#ibcon#read 5, iclass 22, count 0 2006.281.07:47:29.01#ibcon#about to read 6, iclass 22, count 0 2006.281.07:47:29.01#ibcon#read 6, iclass 22, count 0 2006.281.07:47:29.01#ibcon#end of sib2, iclass 22, count 0 2006.281.07:47:29.01#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:47:29.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:47:29.01#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:47:29.01#ibcon#*before write, iclass 22, count 0 2006.281.07:47:29.01#ibcon#enter sib2, iclass 22, count 0 2006.281.07:47:29.01#ibcon#flushed, iclass 22, count 0 2006.281.07:47:29.01#ibcon#about to write, iclass 22, count 0 2006.281.07:47:29.01#ibcon#wrote, iclass 22, count 0 2006.281.07:47:29.01#ibcon#about to read 3, iclass 22, count 0 2006.281.07:47:29.06#ibcon#read 3, iclass 22, count 0 2006.281.07:47:29.06#ibcon#about to read 4, iclass 22, count 0 2006.281.07:47:29.06#ibcon#read 4, iclass 22, count 0 2006.281.07:47:29.06#ibcon#about to read 5, iclass 22, count 0 2006.281.07:47:29.06#ibcon#read 5, iclass 22, count 0 2006.281.07:47:29.06#ibcon#about to read 6, iclass 22, count 0 2006.281.07:47:29.06#ibcon#read 6, iclass 22, count 0 2006.281.07:47:29.06#ibcon#end of sib2, iclass 22, count 0 2006.281.07:47:29.06#ibcon#*after write, iclass 22, count 0 2006.281.07:47:29.06#ibcon#*before return 0, iclass 22, count 0 2006.281.07:47:29.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:29.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:29.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:47:29.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:47:29.06$vc4f8/va=2,6 2006.281.07:47:29.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.07:47:29.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.07:47:29.06#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:29.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:29.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:29.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:29.10#ibcon#enter wrdev, iclass 24, count 2 2006.281.07:47:29.10#ibcon#first serial, iclass 24, count 2 2006.281.07:47:29.10#ibcon#enter sib2, iclass 24, count 2 2006.281.07:47:29.10#ibcon#flushed, iclass 24, count 2 2006.281.07:47:29.10#ibcon#about to write, iclass 24, count 2 2006.281.07:47:29.10#ibcon#wrote, iclass 24, count 2 2006.281.07:47:29.10#ibcon#about to read 3, iclass 24, count 2 2006.281.07:47:29.12#ibcon#read 3, iclass 24, count 2 2006.281.07:47:29.12#ibcon#about to read 4, iclass 24, count 2 2006.281.07:47:29.12#ibcon#read 4, iclass 24, count 2 2006.281.07:47:29.12#ibcon#about to read 5, iclass 24, count 2 2006.281.07:47:29.12#ibcon#read 5, iclass 24, count 2 2006.281.07:47:29.12#ibcon#about to read 6, iclass 24, count 2 2006.281.07:47:29.12#ibcon#read 6, iclass 24, count 2 2006.281.07:47:29.12#ibcon#end of sib2, iclass 24, count 2 2006.281.07:47:29.12#ibcon#*mode == 0, iclass 24, count 2 2006.281.07:47:29.12#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.07:47:29.12#ibcon#[25=AT02-06\r\n] 2006.281.07:47:29.12#ibcon#*before write, iclass 24, count 2 2006.281.07:47:29.12#ibcon#enter sib2, iclass 24, count 2 2006.281.07:47:29.12#ibcon#flushed, iclass 24, count 2 2006.281.07:47:29.12#ibcon#about to write, iclass 24, count 2 2006.281.07:47:29.12#ibcon#wrote, iclass 24, count 2 2006.281.07:47:29.12#ibcon#about to read 3, iclass 24, count 2 2006.281.07:47:29.16#ibcon#read 3, iclass 24, count 2 2006.281.07:47:29.16#ibcon#about to read 4, iclass 24, count 2 2006.281.07:47:29.16#ibcon#read 4, iclass 24, count 2 2006.281.07:47:29.16#ibcon#about to read 5, iclass 24, count 2 2006.281.07:47:29.16#ibcon#read 5, iclass 24, count 2 2006.281.07:47:29.16#ibcon#about to read 6, iclass 24, count 2 2006.281.07:47:29.16#ibcon#read 6, iclass 24, count 2 2006.281.07:47:29.16#ibcon#end of sib2, iclass 24, count 2 2006.281.07:47:29.16#ibcon#*after write, iclass 24, count 2 2006.281.07:47:29.16#ibcon#*before return 0, iclass 24, count 2 2006.281.07:47:29.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:29.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:29.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.07:47:29.16#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:29.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:29.27#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:29.27#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:29.27#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:47:29.27#ibcon#first serial, iclass 24, count 0 2006.281.07:47:29.27#ibcon#enter sib2, iclass 24, count 0 2006.281.07:47:29.27#ibcon#flushed, iclass 24, count 0 2006.281.07:47:29.27#ibcon#about to write, iclass 24, count 0 2006.281.07:47:29.27#ibcon#wrote, iclass 24, count 0 2006.281.07:47:29.27#ibcon#about to read 3, iclass 24, count 0 2006.281.07:47:29.29#ibcon#read 3, iclass 24, count 0 2006.281.07:47:29.29#ibcon#about to read 4, iclass 24, count 0 2006.281.07:47:29.29#ibcon#read 4, iclass 24, count 0 2006.281.07:47:29.29#ibcon#about to read 5, iclass 24, count 0 2006.281.07:47:29.29#ibcon#read 5, iclass 24, count 0 2006.281.07:47:29.29#ibcon#about to read 6, iclass 24, count 0 2006.281.07:47:29.29#ibcon#read 6, iclass 24, count 0 2006.281.07:47:29.29#ibcon#end of sib2, iclass 24, count 0 2006.281.07:47:29.29#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:47:29.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:47:29.29#ibcon#[25=USB\r\n] 2006.281.07:47:29.29#ibcon#*before write, iclass 24, count 0 2006.281.07:47:29.29#ibcon#enter sib2, iclass 24, count 0 2006.281.07:47:29.29#ibcon#flushed, iclass 24, count 0 2006.281.07:47:29.29#ibcon#about to write, iclass 24, count 0 2006.281.07:47:29.29#ibcon#wrote, iclass 24, count 0 2006.281.07:47:29.29#ibcon#about to read 3, iclass 24, count 0 2006.281.07:47:29.32#ibcon#read 3, iclass 24, count 0 2006.281.07:47:29.32#ibcon#about to read 4, iclass 24, count 0 2006.281.07:47:29.32#ibcon#read 4, iclass 24, count 0 2006.281.07:47:29.32#ibcon#about to read 5, iclass 24, count 0 2006.281.07:47:29.32#ibcon#read 5, iclass 24, count 0 2006.281.07:47:29.32#ibcon#about to read 6, iclass 24, count 0 2006.281.07:47:29.32#ibcon#read 6, iclass 24, count 0 2006.281.07:47:29.32#ibcon#end of sib2, iclass 24, count 0 2006.281.07:47:29.32#ibcon#*after write, iclass 24, count 0 2006.281.07:47:29.32#ibcon#*before return 0, iclass 24, count 0 2006.281.07:47:29.32#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:29.32#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:29.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:47:29.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:47:29.32$vc4f8/valo=3,672.99 2006.281.07:47:29.32#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:47:29.32#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:47:29.32#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:29.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:29.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:29.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:29.32#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:47:29.32#ibcon#first serial, iclass 26, count 0 2006.281.07:47:29.32#ibcon#enter sib2, iclass 26, count 0 2006.281.07:47:29.32#ibcon#flushed, iclass 26, count 0 2006.281.07:47:29.32#ibcon#about to write, iclass 26, count 0 2006.281.07:47:29.32#ibcon#wrote, iclass 26, count 0 2006.281.07:47:29.32#ibcon#about to read 3, iclass 26, count 0 2006.281.07:47:29.35#ibcon#read 3, iclass 26, count 0 2006.281.07:47:29.35#ibcon#about to read 4, iclass 26, count 0 2006.281.07:47:29.35#ibcon#read 4, iclass 26, count 0 2006.281.07:47:29.35#ibcon#about to read 5, iclass 26, count 0 2006.281.07:47:29.35#ibcon#read 5, iclass 26, count 0 2006.281.07:47:29.35#ibcon#about to read 6, iclass 26, count 0 2006.281.07:47:29.35#ibcon#read 6, iclass 26, count 0 2006.281.07:47:29.35#ibcon#end of sib2, iclass 26, count 0 2006.281.07:47:29.35#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:47:29.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:47:29.35#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:47:29.35#ibcon#*before write, iclass 26, count 0 2006.281.07:47:29.35#ibcon#enter sib2, iclass 26, count 0 2006.281.07:47:29.35#ibcon#flushed, iclass 26, count 0 2006.281.07:47:29.35#ibcon#about to write, iclass 26, count 0 2006.281.07:47:29.35#ibcon#wrote, iclass 26, count 0 2006.281.07:47:29.35#ibcon#about to read 3, iclass 26, count 0 2006.281.07:47:29.39#ibcon#read 3, iclass 26, count 0 2006.281.07:47:29.39#ibcon#about to read 4, iclass 26, count 0 2006.281.07:47:29.39#ibcon#read 4, iclass 26, count 0 2006.281.07:47:29.39#ibcon#about to read 5, iclass 26, count 0 2006.281.07:47:29.39#ibcon#read 5, iclass 26, count 0 2006.281.07:47:29.39#ibcon#about to read 6, iclass 26, count 0 2006.281.07:47:29.39#ibcon#read 6, iclass 26, count 0 2006.281.07:47:29.39#ibcon#end of sib2, iclass 26, count 0 2006.281.07:47:29.39#ibcon#*after write, iclass 26, count 0 2006.281.07:47:29.39#ibcon#*before return 0, iclass 26, count 0 2006.281.07:47:29.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:29.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:29.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:47:29.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:47:29.39$vc4f8/va=3,6 2006.281.07:47:29.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:47:29.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:47:29.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:29.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:29.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:29.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:29.44#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:47:29.44#ibcon#first serial, iclass 28, count 2 2006.281.07:47:29.44#ibcon#enter sib2, iclass 28, count 2 2006.281.07:47:29.44#ibcon#flushed, iclass 28, count 2 2006.281.07:47:29.44#ibcon#about to write, iclass 28, count 2 2006.281.07:47:29.44#ibcon#wrote, iclass 28, count 2 2006.281.07:47:29.44#ibcon#about to read 3, iclass 28, count 2 2006.281.07:47:29.46#ibcon#read 3, iclass 28, count 2 2006.281.07:47:29.46#ibcon#about to read 4, iclass 28, count 2 2006.281.07:47:29.46#ibcon#read 4, iclass 28, count 2 2006.281.07:47:29.46#ibcon#about to read 5, iclass 28, count 2 2006.281.07:47:29.46#ibcon#read 5, iclass 28, count 2 2006.281.07:47:29.46#ibcon#about to read 6, iclass 28, count 2 2006.281.07:47:29.46#ibcon#read 6, iclass 28, count 2 2006.281.07:47:29.46#ibcon#end of sib2, iclass 28, count 2 2006.281.07:47:29.46#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:47:29.46#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:47:29.46#ibcon#[25=AT03-06\r\n] 2006.281.07:47:29.46#ibcon#*before write, iclass 28, count 2 2006.281.07:47:29.46#ibcon#enter sib2, iclass 28, count 2 2006.281.07:47:29.46#ibcon#flushed, iclass 28, count 2 2006.281.07:47:29.46#ibcon#about to write, iclass 28, count 2 2006.281.07:47:29.46#ibcon#wrote, iclass 28, count 2 2006.281.07:47:29.46#ibcon#about to read 3, iclass 28, count 2 2006.281.07:47:29.49#ibcon#read 3, iclass 28, count 2 2006.281.07:47:29.49#ibcon#about to read 4, iclass 28, count 2 2006.281.07:47:29.49#ibcon#read 4, iclass 28, count 2 2006.281.07:47:29.49#ibcon#about to read 5, iclass 28, count 2 2006.281.07:47:29.49#ibcon#read 5, iclass 28, count 2 2006.281.07:47:29.49#ibcon#about to read 6, iclass 28, count 2 2006.281.07:47:29.49#ibcon#read 6, iclass 28, count 2 2006.281.07:47:29.49#ibcon#end of sib2, iclass 28, count 2 2006.281.07:47:29.49#ibcon#*after write, iclass 28, count 2 2006.281.07:47:29.49#ibcon#*before return 0, iclass 28, count 2 2006.281.07:47:29.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:29.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:29.49#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:47:29.49#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:29.49#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:29.61#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:29.61#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:29.61#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:47:29.61#ibcon#first serial, iclass 28, count 0 2006.281.07:47:29.61#ibcon#enter sib2, iclass 28, count 0 2006.281.07:47:29.61#ibcon#flushed, iclass 28, count 0 2006.281.07:47:29.61#ibcon#about to write, iclass 28, count 0 2006.281.07:47:29.61#ibcon#wrote, iclass 28, count 0 2006.281.07:47:29.61#ibcon#about to read 3, iclass 28, count 0 2006.281.07:47:29.63#ibcon#read 3, iclass 28, count 0 2006.281.07:47:29.63#ibcon#about to read 4, iclass 28, count 0 2006.281.07:47:29.63#ibcon#read 4, iclass 28, count 0 2006.281.07:47:29.63#ibcon#about to read 5, iclass 28, count 0 2006.281.07:47:29.63#ibcon#read 5, iclass 28, count 0 2006.281.07:47:29.63#ibcon#about to read 6, iclass 28, count 0 2006.281.07:47:29.63#ibcon#read 6, iclass 28, count 0 2006.281.07:47:29.63#ibcon#end of sib2, iclass 28, count 0 2006.281.07:47:29.63#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:47:29.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:47:29.63#ibcon#[25=USB\r\n] 2006.281.07:47:29.63#ibcon#*before write, iclass 28, count 0 2006.281.07:47:29.63#ibcon#enter sib2, iclass 28, count 0 2006.281.07:47:29.63#ibcon#flushed, iclass 28, count 0 2006.281.07:47:29.63#ibcon#about to write, iclass 28, count 0 2006.281.07:47:29.63#ibcon#wrote, iclass 28, count 0 2006.281.07:47:29.63#ibcon#about to read 3, iclass 28, count 0 2006.281.07:47:29.66#ibcon#read 3, iclass 28, count 0 2006.281.07:47:29.66#ibcon#about to read 4, iclass 28, count 0 2006.281.07:47:29.66#ibcon#read 4, iclass 28, count 0 2006.281.07:47:29.66#ibcon#about to read 5, iclass 28, count 0 2006.281.07:47:29.66#ibcon#read 5, iclass 28, count 0 2006.281.07:47:29.66#ibcon#about to read 6, iclass 28, count 0 2006.281.07:47:29.66#ibcon#read 6, iclass 28, count 0 2006.281.07:47:29.66#ibcon#end of sib2, iclass 28, count 0 2006.281.07:47:29.66#ibcon#*after write, iclass 28, count 0 2006.281.07:47:29.66#ibcon#*before return 0, iclass 28, count 0 2006.281.07:47:29.66#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:29.66#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:29.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:47:29.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:47:29.66$vc4f8/valo=4,832.99 2006.281.07:47:29.66#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:47:29.66#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:47:29.66#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:29.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:29.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:29.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:29.66#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:47:29.66#ibcon#first serial, iclass 30, count 0 2006.281.07:47:29.66#ibcon#enter sib2, iclass 30, count 0 2006.281.07:47:29.66#ibcon#flushed, iclass 30, count 0 2006.281.07:47:29.66#ibcon#about to write, iclass 30, count 0 2006.281.07:47:29.66#ibcon#wrote, iclass 30, count 0 2006.281.07:47:29.66#ibcon#about to read 3, iclass 30, count 0 2006.281.07:47:29.68#ibcon#read 3, iclass 30, count 0 2006.281.07:47:29.68#ibcon#about to read 4, iclass 30, count 0 2006.281.07:47:29.68#ibcon#read 4, iclass 30, count 0 2006.281.07:47:29.68#ibcon#about to read 5, iclass 30, count 0 2006.281.07:47:29.68#ibcon#read 5, iclass 30, count 0 2006.281.07:47:29.68#ibcon#about to read 6, iclass 30, count 0 2006.281.07:47:29.68#ibcon#read 6, iclass 30, count 0 2006.281.07:47:29.68#ibcon#end of sib2, iclass 30, count 0 2006.281.07:47:29.68#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:47:29.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:47:29.68#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:47:29.68#ibcon#*before write, iclass 30, count 0 2006.281.07:47:29.68#ibcon#enter sib2, iclass 30, count 0 2006.281.07:47:29.68#ibcon#flushed, iclass 30, count 0 2006.281.07:47:29.68#ibcon#about to write, iclass 30, count 0 2006.281.07:47:29.68#ibcon#wrote, iclass 30, count 0 2006.281.07:47:29.68#ibcon#about to read 3, iclass 30, count 0 2006.281.07:47:29.72#ibcon#read 3, iclass 30, count 0 2006.281.07:47:29.72#ibcon#about to read 4, iclass 30, count 0 2006.281.07:47:29.72#ibcon#read 4, iclass 30, count 0 2006.281.07:47:29.72#ibcon#about to read 5, iclass 30, count 0 2006.281.07:47:29.72#ibcon#read 5, iclass 30, count 0 2006.281.07:47:29.72#ibcon#about to read 6, iclass 30, count 0 2006.281.07:47:29.72#ibcon#read 6, iclass 30, count 0 2006.281.07:47:29.72#ibcon#end of sib2, iclass 30, count 0 2006.281.07:47:29.72#ibcon#*after write, iclass 30, count 0 2006.281.07:47:29.72#ibcon#*before return 0, iclass 30, count 0 2006.281.07:47:29.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:29.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:29.72#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:47:29.72#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:47:29.72$vc4f8/va=4,6 2006.281.07:47:29.72#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:47:29.72#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:47:29.72#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:29.72#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:29.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:29.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:29.78#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:47:29.78#ibcon#first serial, iclass 32, count 2 2006.281.07:47:29.78#ibcon#enter sib2, iclass 32, count 2 2006.281.07:47:29.78#ibcon#flushed, iclass 32, count 2 2006.281.07:47:29.78#ibcon#about to write, iclass 32, count 2 2006.281.07:47:29.78#ibcon#wrote, iclass 32, count 2 2006.281.07:47:29.78#ibcon#about to read 3, iclass 32, count 2 2006.281.07:47:29.80#ibcon#read 3, iclass 32, count 2 2006.281.07:47:29.80#ibcon#about to read 4, iclass 32, count 2 2006.281.07:47:29.80#ibcon#read 4, iclass 32, count 2 2006.281.07:47:29.80#ibcon#about to read 5, iclass 32, count 2 2006.281.07:47:29.80#ibcon#read 5, iclass 32, count 2 2006.281.07:47:29.80#ibcon#about to read 6, iclass 32, count 2 2006.281.07:47:29.80#ibcon#read 6, iclass 32, count 2 2006.281.07:47:29.80#ibcon#end of sib2, iclass 32, count 2 2006.281.07:47:29.80#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:47:29.80#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:47:29.80#ibcon#[25=AT04-06\r\n] 2006.281.07:47:29.80#ibcon#*before write, iclass 32, count 2 2006.281.07:47:29.80#ibcon#enter sib2, iclass 32, count 2 2006.281.07:47:29.80#ibcon#flushed, iclass 32, count 2 2006.281.07:47:29.80#ibcon#about to write, iclass 32, count 2 2006.281.07:47:29.80#ibcon#wrote, iclass 32, count 2 2006.281.07:47:29.80#ibcon#about to read 3, iclass 32, count 2 2006.281.07:47:29.84#ibcon#read 3, iclass 32, count 2 2006.281.07:47:29.84#ibcon#about to read 4, iclass 32, count 2 2006.281.07:47:29.84#ibcon#read 4, iclass 32, count 2 2006.281.07:47:29.84#ibcon#about to read 5, iclass 32, count 2 2006.281.07:47:29.84#ibcon#read 5, iclass 32, count 2 2006.281.07:47:29.84#ibcon#about to read 6, iclass 32, count 2 2006.281.07:47:29.84#ibcon#read 6, iclass 32, count 2 2006.281.07:47:29.84#ibcon#end of sib2, iclass 32, count 2 2006.281.07:47:29.84#ibcon#*after write, iclass 32, count 2 2006.281.07:47:29.84#ibcon#*before return 0, iclass 32, count 2 2006.281.07:47:29.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:29.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:29.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:47:29.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:29.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:29.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:29.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:29.95#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:47:29.95#ibcon#first serial, iclass 32, count 0 2006.281.07:47:29.95#ibcon#enter sib2, iclass 32, count 0 2006.281.07:47:29.95#ibcon#flushed, iclass 32, count 0 2006.281.07:47:29.95#ibcon#about to write, iclass 32, count 0 2006.281.07:47:29.95#ibcon#wrote, iclass 32, count 0 2006.281.07:47:29.95#ibcon#about to read 3, iclass 32, count 0 2006.281.07:47:29.97#ibcon#read 3, iclass 32, count 0 2006.281.07:47:29.97#ibcon#about to read 4, iclass 32, count 0 2006.281.07:47:29.97#ibcon#read 4, iclass 32, count 0 2006.281.07:47:29.97#ibcon#about to read 5, iclass 32, count 0 2006.281.07:47:29.97#ibcon#read 5, iclass 32, count 0 2006.281.07:47:29.97#ibcon#about to read 6, iclass 32, count 0 2006.281.07:47:29.97#ibcon#read 6, iclass 32, count 0 2006.281.07:47:29.97#ibcon#end of sib2, iclass 32, count 0 2006.281.07:47:29.97#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:47:29.97#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:47:29.97#ibcon#[25=USB\r\n] 2006.281.07:47:29.97#ibcon#*before write, iclass 32, count 0 2006.281.07:47:29.97#ibcon#enter sib2, iclass 32, count 0 2006.281.07:47:29.97#ibcon#flushed, iclass 32, count 0 2006.281.07:47:29.97#ibcon#about to write, iclass 32, count 0 2006.281.07:47:29.97#ibcon#wrote, iclass 32, count 0 2006.281.07:47:29.97#ibcon#about to read 3, iclass 32, count 0 2006.281.07:47:30.00#ibcon#read 3, iclass 32, count 0 2006.281.07:47:30.00#ibcon#about to read 4, iclass 32, count 0 2006.281.07:47:30.00#ibcon#read 4, iclass 32, count 0 2006.281.07:47:30.00#ibcon#about to read 5, iclass 32, count 0 2006.281.07:47:30.00#ibcon#read 5, iclass 32, count 0 2006.281.07:47:30.00#ibcon#about to read 6, iclass 32, count 0 2006.281.07:47:30.00#ibcon#read 6, iclass 32, count 0 2006.281.07:47:30.00#ibcon#end of sib2, iclass 32, count 0 2006.281.07:47:30.00#ibcon#*after write, iclass 32, count 0 2006.281.07:47:30.00#ibcon#*before return 0, iclass 32, count 0 2006.281.07:47:30.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:30.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:30.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:47:30.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:47:30.00$vc4f8/valo=5,652.99 2006.281.07:47:30.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:47:30.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:47:30.00#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:30.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:30.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:30.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:30.00#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:47:30.00#ibcon#first serial, iclass 34, count 0 2006.281.07:47:30.00#ibcon#enter sib2, iclass 34, count 0 2006.281.07:47:30.00#ibcon#flushed, iclass 34, count 0 2006.281.07:47:30.00#ibcon#about to write, iclass 34, count 0 2006.281.07:47:30.00#ibcon#wrote, iclass 34, count 0 2006.281.07:47:30.00#ibcon#about to read 3, iclass 34, count 0 2006.281.07:47:30.02#ibcon#read 3, iclass 34, count 0 2006.281.07:47:30.02#ibcon#about to read 4, iclass 34, count 0 2006.281.07:47:30.02#ibcon#read 4, iclass 34, count 0 2006.281.07:47:30.02#ibcon#about to read 5, iclass 34, count 0 2006.281.07:47:30.02#ibcon#read 5, iclass 34, count 0 2006.281.07:47:30.02#ibcon#about to read 6, iclass 34, count 0 2006.281.07:47:30.02#ibcon#read 6, iclass 34, count 0 2006.281.07:47:30.02#ibcon#end of sib2, iclass 34, count 0 2006.281.07:47:30.02#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:47:30.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:47:30.02#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:47:30.02#ibcon#*before write, iclass 34, count 0 2006.281.07:47:30.02#ibcon#enter sib2, iclass 34, count 0 2006.281.07:47:30.02#ibcon#flushed, iclass 34, count 0 2006.281.07:47:30.02#ibcon#about to write, iclass 34, count 0 2006.281.07:47:30.02#ibcon#wrote, iclass 34, count 0 2006.281.07:47:30.02#ibcon#about to read 3, iclass 34, count 0 2006.281.07:47:30.07#ibcon#read 3, iclass 34, count 0 2006.281.07:47:30.07#ibcon#about to read 4, iclass 34, count 0 2006.281.07:47:30.07#ibcon#read 4, iclass 34, count 0 2006.281.07:47:30.07#ibcon#about to read 5, iclass 34, count 0 2006.281.07:47:30.07#ibcon#read 5, iclass 34, count 0 2006.281.07:47:30.07#ibcon#about to read 6, iclass 34, count 0 2006.281.07:47:30.07#ibcon#read 6, iclass 34, count 0 2006.281.07:47:30.07#ibcon#end of sib2, iclass 34, count 0 2006.281.07:47:30.07#ibcon#*after write, iclass 34, count 0 2006.281.07:47:30.07#ibcon#*before return 0, iclass 34, count 0 2006.281.07:47:30.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:30.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:30.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:47:30.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:47:30.07$vc4f8/va=5,7 2006.281.07:47:30.08#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:47:30.08#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:47:30.08#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:30.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:30.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:30.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:30.11#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:47:30.11#ibcon#first serial, iclass 36, count 2 2006.281.07:47:30.11#ibcon#enter sib2, iclass 36, count 2 2006.281.07:47:30.11#ibcon#flushed, iclass 36, count 2 2006.281.07:47:30.11#ibcon#about to write, iclass 36, count 2 2006.281.07:47:30.11#ibcon#wrote, iclass 36, count 2 2006.281.07:47:30.11#ibcon#about to read 3, iclass 36, count 2 2006.281.07:47:30.13#ibcon#read 3, iclass 36, count 2 2006.281.07:47:30.13#ibcon#about to read 4, iclass 36, count 2 2006.281.07:47:30.13#ibcon#read 4, iclass 36, count 2 2006.281.07:47:30.13#ibcon#about to read 5, iclass 36, count 2 2006.281.07:47:30.13#ibcon#read 5, iclass 36, count 2 2006.281.07:47:30.13#ibcon#about to read 6, iclass 36, count 2 2006.281.07:47:30.13#ibcon#read 6, iclass 36, count 2 2006.281.07:47:30.13#ibcon#end of sib2, iclass 36, count 2 2006.281.07:47:30.13#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:47:30.13#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:47:30.13#ibcon#[25=AT05-07\r\n] 2006.281.07:47:30.13#ibcon#*before write, iclass 36, count 2 2006.281.07:47:30.13#ibcon#enter sib2, iclass 36, count 2 2006.281.07:47:30.13#ibcon#flushed, iclass 36, count 2 2006.281.07:47:30.13#ibcon#about to write, iclass 36, count 2 2006.281.07:47:30.13#ibcon#wrote, iclass 36, count 2 2006.281.07:47:30.13#ibcon#about to read 3, iclass 36, count 2 2006.281.07:47:30.16#ibcon#read 3, iclass 36, count 2 2006.281.07:47:30.16#ibcon#about to read 4, iclass 36, count 2 2006.281.07:47:30.16#ibcon#read 4, iclass 36, count 2 2006.281.07:47:30.16#ibcon#about to read 5, iclass 36, count 2 2006.281.07:47:30.16#ibcon#read 5, iclass 36, count 2 2006.281.07:47:30.16#ibcon#about to read 6, iclass 36, count 2 2006.281.07:47:30.16#ibcon#read 6, iclass 36, count 2 2006.281.07:47:30.16#ibcon#end of sib2, iclass 36, count 2 2006.281.07:47:30.16#ibcon#*after write, iclass 36, count 2 2006.281.07:47:30.16#ibcon#*before return 0, iclass 36, count 2 2006.281.07:47:30.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:30.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:30.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:47:30.16#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:30.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:30.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:30.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:30.28#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:47:30.28#ibcon#first serial, iclass 36, count 0 2006.281.07:47:30.28#ibcon#enter sib2, iclass 36, count 0 2006.281.07:47:30.28#ibcon#flushed, iclass 36, count 0 2006.281.07:47:30.28#ibcon#about to write, iclass 36, count 0 2006.281.07:47:30.28#ibcon#wrote, iclass 36, count 0 2006.281.07:47:30.28#ibcon#about to read 3, iclass 36, count 0 2006.281.07:47:30.30#ibcon#read 3, iclass 36, count 0 2006.281.07:47:30.30#ibcon#about to read 4, iclass 36, count 0 2006.281.07:47:30.30#ibcon#read 4, iclass 36, count 0 2006.281.07:47:30.30#ibcon#about to read 5, iclass 36, count 0 2006.281.07:47:30.30#ibcon#read 5, iclass 36, count 0 2006.281.07:47:30.30#ibcon#about to read 6, iclass 36, count 0 2006.281.07:47:30.30#ibcon#read 6, iclass 36, count 0 2006.281.07:47:30.30#ibcon#end of sib2, iclass 36, count 0 2006.281.07:47:30.30#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:47:30.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:47:30.30#ibcon#[25=USB\r\n] 2006.281.07:47:30.30#ibcon#*before write, iclass 36, count 0 2006.281.07:47:30.30#ibcon#enter sib2, iclass 36, count 0 2006.281.07:47:30.30#ibcon#flushed, iclass 36, count 0 2006.281.07:47:30.30#ibcon#about to write, iclass 36, count 0 2006.281.07:47:30.30#ibcon#wrote, iclass 36, count 0 2006.281.07:47:30.30#ibcon#about to read 3, iclass 36, count 0 2006.281.07:47:30.33#ibcon#read 3, iclass 36, count 0 2006.281.07:47:30.33#ibcon#about to read 4, iclass 36, count 0 2006.281.07:47:30.33#ibcon#read 4, iclass 36, count 0 2006.281.07:47:30.33#ibcon#about to read 5, iclass 36, count 0 2006.281.07:47:30.33#ibcon#read 5, iclass 36, count 0 2006.281.07:47:30.33#ibcon#about to read 6, iclass 36, count 0 2006.281.07:47:30.33#ibcon#read 6, iclass 36, count 0 2006.281.07:47:30.33#ibcon#end of sib2, iclass 36, count 0 2006.281.07:47:30.33#ibcon#*after write, iclass 36, count 0 2006.281.07:47:30.33#ibcon#*before return 0, iclass 36, count 0 2006.281.07:47:30.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:30.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:30.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:47:30.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:47:30.33$vc4f8/valo=6,772.99 2006.281.07:47:30.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:47:30.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:47:30.33#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:30.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:30.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:30.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:30.33#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:47:30.33#ibcon#first serial, iclass 38, count 0 2006.281.07:47:30.33#ibcon#enter sib2, iclass 38, count 0 2006.281.07:47:30.33#ibcon#flushed, iclass 38, count 0 2006.281.07:47:30.33#ibcon#about to write, iclass 38, count 0 2006.281.07:47:30.33#ibcon#wrote, iclass 38, count 0 2006.281.07:47:30.33#ibcon#about to read 3, iclass 38, count 0 2006.281.07:47:30.35#ibcon#read 3, iclass 38, count 0 2006.281.07:47:30.35#ibcon#about to read 4, iclass 38, count 0 2006.281.07:47:30.35#ibcon#read 4, iclass 38, count 0 2006.281.07:47:30.35#ibcon#about to read 5, iclass 38, count 0 2006.281.07:47:30.35#ibcon#read 5, iclass 38, count 0 2006.281.07:47:30.35#ibcon#about to read 6, iclass 38, count 0 2006.281.07:47:30.35#ibcon#read 6, iclass 38, count 0 2006.281.07:47:30.35#ibcon#end of sib2, iclass 38, count 0 2006.281.07:47:30.35#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:47:30.35#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:47:30.37#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:47:30.37#ibcon#*before write, iclass 38, count 0 2006.281.07:47:30.37#ibcon#enter sib2, iclass 38, count 0 2006.281.07:47:30.37#ibcon#flushed, iclass 38, count 0 2006.281.07:47:30.37#ibcon#about to write, iclass 38, count 0 2006.281.07:47:30.37#ibcon#wrote, iclass 38, count 0 2006.281.07:47:30.37#ibcon#about to read 3, iclass 38, count 0 2006.281.07:47:30.41#ibcon#read 3, iclass 38, count 0 2006.281.07:47:30.41#ibcon#about to read 4, iclass 38, count 0 2006.281.07:47:30.41#ibcon#read 4, iclass 38, count 0 2006.281.07:47:30.41#ibcon#about to read 5, iclass 38, count 0 2006.281.07:47:30.41#ibcon#read 5, iclass 38, count 0 2006.281.07:47:30.41#ibcon#about to read 6, iclass 38, count 0 2006.281.07:47:30.41#ibcon#read 6, iclass 38, count 0 2006.281.07:47:30.41#ibcon#end of sib2, iclass 38, count 0 2006.281.07:47:30.41#ibcon#*after write, iclass 38, count 0 2006.281.07:47:30.41#ibcon#*before return 0, iclass 38, count 0 2006.281.07:47:30.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:30.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:30.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:47:30.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:47:30.41$vc4f8/va=6,6 2006.281.07:47:30.41#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:47:30.41#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:47:30.41#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:30.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:30.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:30.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:30.46#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:47:30.46#ibcon#first serial, iclass 40, count 2 2006.281.07:47:30.46#ibcon#enter sib2, iclass 40, count 2 2006.281.07:47:30.46#ibcon#flushed, iclass 40, count 2 2006.281.07:47:30.46#ibcon#about to write, iclass 40, count 2 2006.281.07:47:30.46#ibcon#wrote, iclass 40, count 2 2006.281.07:47:30.46#ibcon#about to read 3, iclass 40, count 2 2006.281.07:47:30.47#ibcon#read 3, iclass 40, count 2 2006.281.07:47:30.47#ibcon#about to read 4, iclass 40, count 2 2006.281.07:47:30.47#ibcon#read 4, iclass 40, count 2 2006.281.07:47:30.47#ibcon#about to read 5, iclass 40, count 2 2006.281.07:47:30.47#ibcon#read 5, iclass 40, count 2 2006.281.07:47:30.47#ibcon#about to read 6, iclass 40, count 2 2006.281.07:47:30.47#ibcon#read 6, iclass 40, count 2 2006.281.07:47:30.47#ibcon#end of sib2, iclass 40, count 2 2006.281.07:47:30.47#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:47:30.47#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:47:30.47#ibcon#[25=AT06-06\r\n] 2006.281.07:47:30.47#ibcon#*before write, iclass 40, count 2 2006.281.07:47:30.47#ibcon#enter sib2, iclass 40, count 2 2006.281.07:47:30.47#ibcon#flushed, iclass 40, count 2 2006.281.07:47:30.47#ibcon#about to write, iclass 40, count 2 2006.281.07:47:30.47#ibcon#wrote, iclass 40, count 2 2006.281.07:47:30.47#ibcon#about to read 3, iclass 40, count 2 2006.281.07:47:30.50#ibcon#read 3, iclass 40, count 2 2006.281.07:47:30.50#ibcon#about to read 4, iclass 40, count 2 2006.281.07:47:30.50#ibcon#read 4, iclass 40, count 2 2006.281.07:47:30.50#ibcon#about to read 5, iclass 40, count 2 2006.281.07:47:30.50#ibcon#read 5, iclass 40, count 2 2006.281.07:47:30.50#ibcon#about to read 6, iclass 40, count 2 2006.281.07:47:30.50#ibcon#read 6, iclass 40, count 2 2006.281.07:47:30.50#ibcon#end of sib2, iclass 40, count 2 2006.281.07:47:30.50#ibcon#*after write, iclass 40, count 2 2006.281.07:47:30.50#ibcon#*before return 0, iclass 40, count 2 2006.281.07:47:30.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:30.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:30.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:47:30.50#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:30.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:47:30.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:47:30.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:47:30.62#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:47:30.62#ibcon#first serial, iclass 40, count 0 2006.281.07:47:30.62#ibcon#enter sib2, iclass 40, count 0 2006.281.07:47:30.62#ibcon#flushed, iclass 40, count 0 2006.281.07:47:30.62#ibcon#about to write, iclass 40, count 0 2006.281.07:47:30.62#ibcon#wrote, iclass 40, count 0 2006.281.07:47:30.62#ibcon#about to read 3, iclass 40, count 0 2006.281.07:47:30.64#ibcon#read 3, iclass 40, count 0 2006.281.07:47:30.64#ibcon#about to read 4, iclass 40, count 0 2006.281.07:47:30.64#ibcon#read 4, iclass 40, count 0 2006.281.07:47:30.64#ibcon#about to read 5, iclass 40, count 0 2006.281.07:47:30.64#ibcon#read 5, iclass 40, count 0 2006.281.07:47:30.64#ibcon#about to read 6, iclass 40, count 0 2006.281.07:47:30.64#ibcon#read 6, iclass 40, count 0 2006.281.07:47:30.64#ibcon#end of sib2, iclass 40, count 0 2006.281.07:47:30.64#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:47:30.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:47:30.64#ibcon#[25=USB\r\n] 2006.281.07:47:30.64#ibcon#*before write, iclass 40, count 0 2006.281.07:47:30.64#ibcon#enter sib2, iclass 40, count 0 2006.281.07:47:30.64#ibcon#flushed, iclass 40, count 0 2006.281.07:47:30.64#ibcon#about to write, iclass 40, count 0 2006.281.07:47:30.64#ibcon#wrote, iclass 40, count 0 2006.281.07:47:30.64#ibcon#about to read 3, iclass 40, count 0 2006.281.07:47:30.67#ibcon#read 3, iclass 40, count 0 2006.281.07:47:30.67#ibcon#about to read 4, iclass 40, count 0 2006.281.07:47:30.67#ibcon#read 4, iclass 40, count 0 2006.281.07:47:30.67#ibcon#about to read 5, iclass 40, count 0 2006.281.07:47:30.67#ibcon#read 5, iclass 40, count 0 2006.281.07:47:30.67#ibcon#about to read 6, iclass 40, count 0 2006.281.07:47:30.67#ibcon#read 6, iclass 40, count 0 2006.281.07:47:30.67#ibcon#end of sib2, iclass 40, count 0 2006.281.07:47:30.67#ibcon#*after write, iclass 40, count 0 2006.281.07:47:30.67#ibcon#*before return 0, iclass 40, count 0 2006.281.07:47:30.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:47:30.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:47:30.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:47:30.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:47:30.67$vc4f8/valo=7,832.99 2006.281.07:47:30.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:47:30.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:47:30.67#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:30.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:47:30.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:47:30.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:47:30.67#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:47:30.67#ibcon#first serial, iclass 4, count 0 2006.281.07:47:30.67#ibcon#enter sib2, iclass 4, count 0 2006.281.07:47:30.67#ibcon#flushed, iclass 4, count 0 2006.281.07:47:30.67#ibcon#about to write, iclass 4, count 0 2006.281.07:47:30.67#ibcon#wrote, iclass 4, count 0 2006.281.07:47:30.67#ibcon#about to read 3, iclass 4, count 0 2006.281.07:47:30.69#ibcon#read 3, iclass 4, count 0 2006.281.07:47:30.69#ibcon#about to read 4, iclass 4, count 0 2006.281.07:47:30.69#ibcon#read 4, iclass 4, count 0 2006.281.07:47:30.69#ibcon#about to read 5, iclass 4, count 0 2006.281.07:47:30.69#ibcon#read 5, iclass 4, count 0 2006.281.07:47:30.69#ibcon#about to read 6, iclass 4, count 0 2006.281.07:47:30.69#ibcon#read 6, iclass 4, count 0 2006.281.07:47:30.69#ibcon#end of sib2, iclass 4, count 0 2006.281.07:47:30.69#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:47:30.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:47:30.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:47:30.69#ibcon#*before write, iclass 4, count 0 2006.281.07:47:30.69#ibcon#enter sib2, iclass 4, count 0 2006.281.07:47:30.69#ibcon#flushed, iclass 4, count 0 2006.281.07:47:30.69#ibcon#about to write, iclass 4, count 0 2006.281.07:47:30.69#ibcon#wrote, iclass 4, count 0 2006.281.07:47:30.69#ibcon#about to read 3, iclass 4, count 0 2006.281.07:47:30.73#ibcon#read 3, iclass 4, count 0 2006.281.07:47:30.73#ibcon#about to read 4, iclass 4, count 0 2006.281.07:47:30.73#ibcon#read 4, iclass 4, count 0 2006.281.07:47:30.73#ibcon#about to read 5, iclass 4, count 0 2006.281.07:47:30.73#ibcon#read 5, iclass 4, count 0 2006.281.07:47:30.73#ibcon#about to read 6, iclass 4, count 0 2006.281.07:47:30.73#ibcon#read 6, iclass 4, count 0 2006.281.07:47:30.73#ibcon#end of sib2, iclass 4, count 0 2006.281.07:47:30.73#ibcon#*after write, iclass 4, count 0 2006.281.07:47:30.73#ibcon#*before return 0, iclass 4, count 0 2006.281.07:47:30.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:47:30.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:47:30.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:47:30.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:47:30.73$vc4f8/va=7,6 2006.281.07:47:30.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:47:30.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:47:30.73#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:30.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:47:30.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:47:30.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:47:30.79#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:47:30.79#ibcon#first serial, iclass 6, count 2 2006.281.07:47:30.79#ibcon#enter sib2, iclass 6, count 2 2006.281.07:47:30.79#ibcon#flushed, iclass 6, count 2 2006.281.07:47:30.79#ibcon#about to write, iclass 6, count 2 2006.281.07:47:30.79#ibcon#wrote, iclass 6, count 2 2006.281.07:47:30.79#ibcon#about to read 3, iclass 6, count 2 2006.281.07:47:30.81#ibcon#read 3, iclass 6, count 2 2006.281.07:47:30.81#ibcon#about to read 4, iclass 6, count 2 2006.281.07:47:30.81#ibcon#read 4, iclass 6, count 2 2006.281.07:47:30.81#ibcon#about to read 5, iclass 6, count 2 2006.281.07:47:30.81#ibcon#read 5, iclass 6, count 2 2006.281.07:47:30.81#ibcon#about to read 6, iclass 6, count 2 2006.281.07:47:30.81#ibcon#read 6, iclass 6, count 2 2006.281.07:47:30.81#ibcon#end of sib2, iclass 6, count 2 2006.281.07:47:30.81#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:47:30.81#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:47:30.81#ibcon#[25=AT07-06\r\n] 2006.281.07:47:30.81#ibcon#*before write, iclass 6, count 2 2006.281.07:47:30.81#ibcon#enter sib2, iclass 6, count 2 2006.281.07:47:30.81#ibcon#flushed, iclass 6, count 2 2006.281.07:47:30.81#ibcon#about to write, iclass 6, count 2 2006.281.07:47:30.81#ibcon#wrote, iclass 6, count 2 2006.281.07:47:30.81#ibcon#about to read 3, iclass 6, count 2 2006.281.07:47:30.84#ibcon#read 3, iclass 6, count 2 2006.281.07:47:30.84#ibcon#about to read 4, iclass 6, count 2 2006.281.07:47:30.84#ibcon#read 4, iclass 6, count 2 2006.281.07:47:30.84#ibcon#about to read 5, iclass 6, count 2 2006.281.07:47:30.84#ibcon#read 5, iclass 6, count 2 2006.281.07:47:30.84#ibcon#about to read 6, iclass 6, count 2 2006.281.07:47:30.84#ibcon#read 6, iclass 6, count 2 2006.281.07:47:30.84#ibcon#end of sib2, iclass 6, count 2 2006.281.07:47:30.84#ibcon#*after write, iclass 6, count 2 2006.281.07:47:30.84#ibcon#*before return 0, iclass 6, count 2 2006.281.07:47:30.84#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:47:30.84#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:47:30.84#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:47:30.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:30.84#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:47:30.96#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:47:30.96#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:47:30.96#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:47:30.96#ibcon#first serial, iclass 6, count 0 2006.281.07:47:30.96#ibcon#enter sib2, iclass 6, count 0 2006.281.07:47:30.96#ibcon#flushed, iclass 6, count 0 2006.281.07:47:30.96#ibcon#about to write, iclass 6, count 0 2006.281.07:47:30.96#ibcon#wrote, iclass 6, count 0 2006.281.07:47:30.96#ibcon#about to read 3, iclass 6, count 0 2006.281.07:47:30.98#ibcon#read 3, iclass 6, count 0 2006.281.07:47:30.98#ibcon#about to read 4, iclass 6, count 0 2006.281.07:47:30.98#ibcon#read 4, iclass 6, count 0 2006.281.07:47:30.98#ibcon#about to read 5, iclass 6, count 0 2006.281.07:47:30.98#ibcon#read 5, iclass 6, count 0 2006.281.07:47:30.98#ibcon#about to read 6, iclass 6, count 0 2006.281.07:47:30.98#ibcon#read 6, iclass 6, count 0 2006.281.07:47:30.98#ibcon#end of sib2, iclass 6, count 0 2006.281.07:47:30.98#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:47:30.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:47:30.98#ibcon#[25=USB\r\n] 2006.281.07:47:30.98#ibcon#*before write, iclass 6, count 0 2006.281.07:47:30.98#ibcon#enter sib2, iclass 6, count 0 2006.281.07:47:30.98#ibcon#flushed, iclass 6, count 0 2006.281.07:47:30.98#ibcon#about to write, iclass 6, count 0 2006.281.07:47:30.98#ibcon#wrote, iclass 6, count 0 2006.281.07:47:30.98#ibcon#about to read 3, iclass 6, count 0 2006.281.07:47:31.01#ibcon#read 3, iclass 6, count 0 2006.281.07:47:31.01#ibcon#about to read 4, iclass 6, count 0 2006.281.07:47:31.01#ibcon#read 4, iclass 6, count 0 2006.281.07:47:31.01#ibcon#about to read 5, iclass 6, count 0 2006.281.07:47:31.01#ibcon#read 5, iclass 6, count 0 2006.281.07:47:31.01#ibcon#about to read 6, iclass 6, count 0 2006.281.07:47:31.01#ibcon#read 6, iclass 6, count 0 2006.281.07:47:31.01#ibcon#end of sib2, iclass 6, count 0 2006.281.07:47:31.01#ibcon#*after write, iclass 6, count 0 2006.281.07:47:31.01#ibcon#*before return 0, iclass 6, count 0 2006.281.07:47:31.01#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:47:31.01#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:47:31.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:47:31.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:47:31.01$vc4f8/valo=8,852.99 2006.281.07:47:31.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:47:31.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:47:31.01#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:31.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:47:31.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:47:31.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:47:31.01#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:47:31.01#ibcon#first serial, iclass 10, count 0 2006.281.07:47:31.01#ibcon#enter sib2, iclass 10, count 0 2006.281.07:47:31.01#ibcon#flushed, iclass 10, count 0 2006.281.07:47:31.01#ibcon#about to write, iclass 10, count 0 2006.281.07:47:31.01#ibcon#wrote, iclass 10, count 0 2006.281.07:47:31.01#ibcon#about to read 3, iclass 10, count 0 2006.281.07:47:31.03#ibcon#read 3, iclass 10, count 0 2006.281.07:47:31.03#ibcon#about to read 4, iclass 10, count 0 2006.281.07:47:31.03#ibcon#read 4, iclass 10, count 0 2006.281.07:47:31.03#ibcon#about to read 5, iclass 10, count 0 2006.281.07:47:31.03#ibcon#read 5, iclass 10, count 0 2006.281.07:47:31.03#ibcon#about to read 6, iclass 10, count 0 2006.281.07:47:31.03#ibcon#read 6, iclass 10, count 0 2006.281.07:47:31.03#ibcon#end of sib2, iclass 10, count 0 2006.281.07:47:31.03#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:47:31.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:47:31.03#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:47:31.03#ibcon#*before write, iclass 10, count 0 2006.281.07:47:31.03#ibcon#enter sib2, iclass 10, count 0 2006.281.07:47:31.03#ibcon#flushed, iclass 10, count 0 2006.281.07:47:31.03#ibcon#about to write, iclass 10, count 0 2006.281.07:47:31.03#ibcon#wrote, iclass 10, count 0 2006.281.07:47:31.03#ibcon#about to read 3, iclass 10, count 0 2006.281.07:47:31.08#ibcon#read 3, iclass 10, count 0 2006.281.07:47:31.08#ibcon#about to read 4, iclass 10, count 0 2006.281.07:47:31.08#ibcon#read 4, iclass 10, count 0 2006.281.07:47:31.08#ibcon#about to read 5, iclass 10, count 0 2006.281.07:47:31.08#ibcon#read 5, iclass 10, count 0 2006.281.07:47:31.08#ibcon#about to read 6, iclass 10, count 0 2006.281.07:47:31.08#ibcon#read 6, iclass 10, count 0 2006.281.07:47:31.08#ibcon#end of sib2, iclass 10, count 0 2006.281.07:47:31.08#ibcon#*after write, iclass 10, count 0 2006.281.07:47:31.08#ibcon#*before return 0, iclass 10, count 0 2006.281.07:47:31.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:47:31.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:47:31.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:47:31.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:47:31.08$vc4f8/va=8,6 2006.281.07:47:31.09#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:47:31.09#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:47:31.09#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:31.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:47:31.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:47:31.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:47:31.12#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:47:31.12#ibcon#first serial, iclass 12, count 2 2006.281.07:47:31.12#ibcon#enter sib2, iclass 12, count 2 2006.281.07:47:31.12#ibcon#flushed, iclass 12, count 2 2006.281.07:47:31.12#ibcon#about to write, iclass 12, count 2 2006.281.07:47:31.12#ibcon#wrote, iclass 12, count 2 2006.281.07:47:31.12#ibcon#about to read 3, iclass 12, count 2 2006.281.07:47:31.15#ibcon#read 3, iclass 12, count 2 2006.281.07:47:31.15#ibcon#about to read 4, iclass 12, count 2 2006.281.07:47:31.15#ibcon#read 4, iclass 12, count 2 2006.281.07:47:31.15#ibcon#about to read 5, iclass 12, count 2 2006.281.07:47:31.15#ibcon#read 5, iclass 12, count 2 2006.281.07:47:31.15#ibcon#about to read 6, iclass 12, count 2 2006.281.07:47:31.15#ibcon#read 6, iclass 12, count 2 2006.281.07:47:31.15#ibcon#end of sib2, iclass 12, count 2 2006.281.07:47:31.15#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:47:31.15#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:47:31.15#ibcon#[25=AT08-06\r\n] 2006.281.07:47:31.15#ibcon#*before write, iclass 12, count 2 2006.281.07:47:31.15#ibcon#enter sib2, iclass 12, count 2 2006.281.07:47:31.15#ibcon#flushed, iclass 12, count 2 2006.281.07:47:31.15#ibcon#about to write, iclass 12, count 2 2006.281.07:47:31.15#ibcon#wrote, iclass 12, count 2 2006.281.07:47:31.15#ibcon#about to read 3, iclass 12, count 2 2006.281.07:47:31.18#ibcon#read 3, iclass 12, count 2 2006.281.07:47:31.18#ibcon#about to read 4, iclass 12, count 2 2006.281.07:47:31.18#ibcon#read 4, iclass 12, count 2 2006.281.07:47:31.18#ibcon#about to read 5, iclass 12, count 2 2006.281.07:47:31.18#ibcon#read 5, iclass 12, count 2 2006.281.07:47:31.18#ibcon#about to read 6, iclass 12, count 2 2006.281.07:47:31.18#ibcon#read 6, iclass 12, count 2 2006.281.07:47:31.18#ibcon#end of sib2, iclass 12, count 2 2006.281.07:47:31.18#ibcon#*after write, iclass 12, count 2 2006.281.07:47:31.18#ibcon#*before return 0, iclass 12, count 2 2006.281.07:47:31.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:47:31.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:47:31.18#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:47:31.18#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:31.18#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:47:31.30#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:47:31.30#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:47:31.30#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:47:31.30#ibcon#first serial, iclass 12, count 0 2006.281.07:47:31.30#ibcon#enter sib2, iclass 12, count 0 2006.281.07:47:31.30#ibcon#flushed, iclass 12, count 0 2006.281.07:47:31.30#ibcon#about to write, iclass 12, count 0 2006.281.07:47:31.30#ibcon#wrote, iclass 12, count 0 2006.281.07:47:31.30#ibcon#about to read 3, iclass 12, count 0 2006.281.07:47:31.32#ibcon#read 3, iclass 12, count 0 2006.281.07:47:31.32#ibcon#about to read 4, iclass 12, count 0 2006.281.07:47:31.32#ibcon#read 4, iclass 12, count 0 2006.281.07:47:31.32#ibcon#about to read 5, iclass 12, count 0 2006.281.07:47:31.32#ibcon#read 5, iclass 12, count 0 2006.281.07:47:31.32#ibcon#about to read 6, iclass 12, count 0 2006.281.07:47:31.32#ibcon#read 6, iclass 12, count 0 2006.281.07:47:31.32#ibcon#end of sib2, iclass 12, count 0 2006.281.07:47:31.32#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:47:31.32#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:47:31.32#ibcon#[25=USB\r\n] 2006.281.07:47:31.32#ibcon#*before write, iclass 12, count 0 2006.281.07:47:31.32#ibcon#enter sib2, iclass 12, count 0 2006.281.07:47:31.32#ibcon#flushed, iclass 12, count 0 2006.281.07:47:31.32#ibcon#about to write, iclass 12, count 0 2006.281.07:47:31.32#ibcon#wrote, iclass 12, count 0 2006.281.07:47:31.32#ibcon#about to read 3, iclass 12, count 0 2006.281.07:47:31.35#ibcon#read 3, iclass 12, count 0 2006.281.07:47:31.35#ibcon#about to read 4, iclass 12, count 0 2006.281.07:47:31.35#ibcon#read 4, iclass 12, count 0 2006.281.07:47:31.35#ibcon#about to read 5, iclass 12, count 0 2006.281.07:47:31.35#ibcon#read 5, iclass 12, count 0 2006.281.07:47:31.35#ibcon#about to read 6, iclass 12, count 0 2006.281.07:47:31.35#ibcon#read 6, iclass 12, count 0 2006.281.07:47:31.35#ibcon#end of sib2, iclass 12, count 0 2006.281.07:47:31.35#ibcon#*after write, iclass 12, count 0 2006.281.07:47:31.35#ibcon#*before return 0, iclass 12, count 0 2006.281.07:47:31.35#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:47:31.35#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:47:31.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:47:31.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:47:31.35$vc4f8/vblo=1,632.99 2006.281.07:47:31.35#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:47:31.35#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:47:31.35#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:31.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:47:31.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:47:31.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:47:31.35#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:47:31.35#ibcon#first serial, iclass 14, count 0 2006.281.07:47:31.35#ibcon#enter sib2, iclass 14, count 0 2006.281.07:47:31.35#ibcon#flushed, iclass 14, count 0 2006.281.07:47:31.35#ibcon#about to write, iclass 14, count 0 2006.281.07:47:31.35#ibcon#wrote, iclass 14, count 0 2006.281.07:47:31.35#ibcon#about to read 3, iclass 14, count 0 2006.281.07:47:31.37#ibcon#read 3, iclass 14, count 0 2006.281.07:47:31.38#ibcon#about to read 4, iclass 14, count 0 2006.281.07:47:31.38#ibcon#read 4, iclass 14, count 0 2006.281.07:47:31.38#ibcon#about to read 5, iclass 14, count 0 2006.281.07:47:31.38#ibcon#read 5, iclass 14, count 0 2006.281.07:47:31.38#ibcon#about to read 6, iclass 14, count 0 2006.281.07:47:31.38#ibcon#read 6, iclass 14, count 0 2006.281.07:47:31.38#ibcon#end of sib2, iclass 14, count 0 2006.281.07:47:31.38#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:47:31.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:47:31.38#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:47:31.38#ibcon#*before write, iclass 14, count 0 2006.281.07:47:31.38#ibcon#enter sib2, iclass 14, count 0 2006.281.07:47:31.38#ibcon#flushed, iclass 14, count 0 2006.281.07:47:31.38#ibcon#about to write, iclass 14, count 0 2006.281.07:47:31.38#ibcon#wrote, iclass 14, count 0 2006.281.07:47:31.38#ibcon#about to read 3, iclass 14, count 0 2006.281.07:47:31.42#ibcon#read 3, iclass 14, count 0 2006.281.07:47:31.42#ibcon#about to read 4, iclass 14, count 0 2006.281.07:47:31.42#ibcon#read 4, iclass 14, count 0 2006.281.07:47:31.42#ibcon#about to read 5, iclass 14, count 0 2006.281.07:47:31.42#ibcon#read 5, iclass 14, count 0 2006.281.07:47:31.42#ibcon#about to read 6, iclass 14, count 0 2006.281.07:47:31.42#ibcon#read 6, iclass 14, count 0 2006.281.07:47:31.42#ibcon#end of sib2, iclass 14, count 0 2006.281.07:47:31.42#ibcon#*after write, iclass 14, count 0 2006.281.07:47:31.42#ibcon#*before return 0, iclass 14, count 0 2006.281.07:47:31.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:47:31.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:47:31.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:47:31.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:47:31.42$vc4f8/vb=1,4 2006.281.07:47:31.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.07:47:31.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.07:47:31.42#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:31.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:47:31.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:47:31.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:47:31.42#ibcon#enter wrdev, iclass 16, count 2 2006.281.07:47:31.42#ibcon#first serial, iclass 16, count 2 2006.281.07:47:31.42#ibcon#enter sib2, iclass 16, count 2 2006.281.07:47:31.42#ibcon#flushed, iclass 16, count 2 2006.281.07:47:31.42#ibcon#about to write, iclass 16, count 2 2006.281.07:47:31.42#ibcon#wrote, iclass 16, count 2 2006.281.07:47:31.42#ibcon#about to read 3, iclass 16, count 2 2006.281.07:47:31.44#ibcon#read 3, iclass 16, count 2 2006.281.07:47:31.44#ibcon#about to read 4, iclass 16, count 2 2006.281.07:47:31.44#ibcon#read 4, iclass 16, count 2 2006.281.07:47:31.44#ibcon#about to read 5, iclass 16, count 2 2006.281.07:47:31.44#ibcon#read 5, iclass 16, count 2 2006.281.07:47:31.44#ibcon#about to read 6, iclass 16, count 2 2006.281.07:47:31.44#ibcon#read 6, iclass 16, count 2 2006.281.07:47:31.44#ibcon#end of sib2, iclass 16, count 2 2006.281.07:47:31.44#ibcon#*mode == 0, iclass 16, count 2 2006.281.07:47:31.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.07:47:31.44#ibcon#[27=AT01-04\r\n] 2006.281.07:47:31.44#ibcon#*before write, iclass 16, count 2 2006.281.07:47:31.44#ibcon#enter sib2, iclass 16, count 2 2006.281.07:47:31.44#ibcon#flushed, iclass 16, count 2 2006.281.07:47:31.44#ibcon#about to write, iclass 16, count 2 2006.281.07:47:31.44#ibcon#wrote, iclass 16, count 2 2006.281.07:47:31.44#ibcon#about to read 3, iclass 16, count 2 2006.281.07:47:31.47#ibcon#read 3, iclass 16, count 2 2006.281.07:47:31.47#ibcon#about to read 4, iclass 16, count 2 2006.281.07:47:31.47#ibcon#read 4, iclass 16, count 2 2006.281.07:47:31.47#ibcon#about to read 5, iclass 16, count 2 2006.281.07:47:31.47#ibcon#read 5, iclass 16, count 2 2006.281.07:47:31.47#ibcon#about to read 6, iclass 16, count 2 2006.281.07:47:31.47#ibcon#read 6, iclass 16, count 2 2006.281.07:47:31.47#ibcon#end of sib2, iclass 16, count 2 2006.281.07:47:31.47#ibcon#*after write, iclass 16, count 2 2006.281.07:47:31.47#ibcon#*before return 0, iclass 16, count 2 2006.281.07:47:31.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:47:31.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:47:31.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.07:47:31.47#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:31.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:47:31.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:47:31.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:47:31.59#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:47:31.59#ibcon#first serial, iclass 16, count 0 2006.281.07:47:31.59#ibcon#enter sib2, iclass 16, count 0 2006.281.07:47:31.59#ibcon#flushed, iclass 16, count 0 2006.281.07:47:31.59#ibcon#about to write, iclass 16, count 0 2006.281.07:47:31.59#ibcon#wrote, iclass 16, count 0 2006.281.07:47:31.59#ibcon#about to read 3, iclass 16, count 0 2006.281.07:47:31.61#ibcon#read 3, iclass 16, count 0 2006.281.07:47:31.61#ibcon#about to read 4, iclass 16, count 0 2006.281.07:47:31.61#ibcon#read 4, iclass 16, count 0 2006.281.07:47:31.61#ibcon#about to read 5, iclass 16, count 0 2006.281.07:47:31.61#ibcon#read 5, iclass 16, count 0 2006.281.07:47:31.61#ibcon#about to read 6, iclass 16, count 0 2006.281.07:47:31.61#ibcon#read 6, iclass 16, count 0 2006.281.07:47:31.61#ibcon#end of sib2, iclass 16, count 0 2006.281.07:47:31.61#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:47:31.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:47:31.61#ibcon#[27=USB\r\n] 2006.281.07:47:31.61#ibcon#*before write, iclass 16, count 0 2006.281.07:47:31.61#ibcon#enter sib2, iclass 16, count 0 2006.281.07:47:31.61#ibcon#flushed, iclass 16, count 0 2006.281.07:47:31.61#ibcon#about to write, iclass 16, count 0 2006.281.07:47:31.61#ibcon#wrote, iclass 16, count 0 2006.281.07:47:31.61#ibcon#about to read 3, iclass 16, count 0 2006.281.07:47:31.65#ibcon#read 3, iclass 16, count 0 2006.281.07:47:31.65#ibcon#about to read 4, iclass 16, count 0 2006.281.07:47:31.65#ibcon#read 4, iclass 16, count 0 2006.281.07:47:31.65#ibcon#about to read 5, iclass 16, count 0 2006.281.07:47:31.65#ibcon#read 5, iclass 16, count 0 2006.281.07:47:31.65#ibcon#about to read 6, iclass 16, count 0 2006.281.07:47:31.65#ibcon#read 6, iclass 16, count 0 2006.281.07:47:31.65#ibcon#end of sib2, iclass 16, count 0 2006.281.07:47:31.65#ibcon#*after write, iclass 16, count 0 2006.281.07:47:31.65#ibcon#*before return 0, iclass 16, count 0 2006.281.07:47:31.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:47:31.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:47:31.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:47:31.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:47:31.65$vc4f8/vblo=2,640.99 2006.281.07:47:31.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.07:47:31.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.07:47:31.65#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:31.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:31.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:31.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:31.65#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:47:31.65#ibcon#first serial, iclass 18, count 0 2006.281.07:47:31.65#ibcon#enter sib2, iclass 18, count 0 2006.281.07:47:31.65#ibcon#flushed, iclass 18, count 0 2006.281.07:47:31.65#ibcon#about to write, iclass 18, count 0 2006.281.07:47:31.65#ibcon#wrote, iclass 18, count 0 2006.281.07:47:31.65#ibcon#about to read 3, iclass 18, count 0 2006.281.07:47:31.66#ibcon#read 3, iclass 18, count 0 2006.281.07:47:31.66#ibcon#about to read 4, iclass 18, count 0 2006.281.07:47:31.66#ibcon#read 4, iclass 18, count 0 2006.281.07:47:31.66#ibcon#about to read 5, iclass 18, count 0 2006.281.07:47:31.66#ibcon#read 5, iclass 18, count 0 2006.281.07:47:31.66#ibcon#about to read 6, iclass 18, count 0 2006.281.07:47:31.66#ibcon#read 6, iclass 18, count 0 2006.281.07:47:31.66#ibcon#end of sib2, iclass 18, count 0 2006.281.07:47:31.66#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:47:31.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:47:31.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:47:31.66#ibcon#*before write, iclass 18, count 0 2006.281.07:47:31.66#ibcon#enter sib2, iclass 18, count 0 2006.281.07:47:31.66#ibcon#flushed, iclass 18, count 0 2006.281.07:47:31.66#ibcon#about to write, iclass 18, count 0 2006.281.07:47:31.66#ibcon#wrote, iclass 18, count 0 2006.281.07:47:31.66#ibcon#about to read 3, iclass 18, count 0 2006.281.07:47:31.70#ibcon#read 3, iclass 18, count 0 2006.281.07:47:31.70#ibcon#about to read 4, iclass 18, count 0 2006.281.07:47:31.70#ibcon#read 4, iclass 18, count 0 2006.281.07:47:31.70#ibcon#about to read 5, iclass 18, count 0 2006.281.07:47:31.70#ibcon#read 5, iclass 18, count 0 2006.281.07:47:31.70#ibcon#about to read 6, iclass 18, count 0 2006.281.07:47:31.70#ibcon#read 6, iclass 18, count 0 2006.281.07:47:31.70#ibcon#end of sib2, iclass 18, count 0 2006.281.07:47:31.70#ibcon#*after write, iclass 18, count 0 2006.281.07:47:31.70#ibcon#*before return 0, iclass 18, count 0 2006.281.07:47:31.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:31.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:47:31.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:47:31.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:47:31.70$vc4f8/vb=2,5 2006.281.07:47:31.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.07:47:31.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.07:47:31.70#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:31.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:31.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:31.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:31.77#ibcon#enter wrdev, iclass 20, count 2 2006.281.07:47:31.77#ibcon#first serial, iclass 20, count 2 2006.281.07:47:31.77#ibcon#enter sib2, iclass 20, count 2 2006.281.07:47:31.77#ibcon#flushed, iclass 20, count 2 2006.281.07:47:31.77#ibcon#about to write, iclass 20, count 2 2006.281.07:47:31.77#ibcon#wrote, iclass 20, count 2 2006.281.07:47:31.77#ibcon#about to read 3, iclass 20, count 2 2006.281.07:47:31.79#ibcon#read 3, iclass 20, count 2 2006.281.07:47:31.79#ibcon#about to read 4, iclass 20, count 2 2006.281.07:47:31.79#ibcon#read 4, iclass 20, count 2 2006.281.07:47:31.79#ibcon#about to read 5, iclass 20, count 2 2006.281.07:47:31.79#ibcon#read 5, iclass 20, count 2 2006.281.07:47:31.79#ibcon#about to read 6, iclass 20, count 2 2006.281.07:47:31.79#ibcon#read 6, iclass 20, count 2 2006.281.07:47:31.79#ibcon#end of sib2, iclass 20, count 2 2006.281.07:47:31.79#ibcon#*mode == 0, iclass 20, count 2 2006.281.07:47:31.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.07:47:31.79#ibcon#[27=AT02-05\r\n] 2006.281.07:47:31.79#ibcon#*before write, iclass 20, count 2 2006.281.07:47:31.79#ibcon#enter sib2, iclass 20, count 2 2006.281.07:47:31.79#ibcon#flushed, iclass 20, count 2 2006.281.07:47:31.79#ibcon#about to write, iclass 20, count 2 2006.281.07:47:31.79#ibcon#wrote, iclass 20, count 2 2006.281.07:47:31.79#ibcon#about to read 3, iclass 20, count 2 2006.281.07:47:31.82#ibcon#read 3, iclass 20, count 2 2006.281.07:47:31.82#ibcon#about to read 4, iclass 20, count 2 2006.281.07:47:31.82#ibcon#read 4, iclass 20, count 2 2006.281.07:47:31.82#ibcon#about to read 5, iclass 20, count 2 2006.281.07:47:31.82#ibcon#read 5, iclass 20, count 2 2006.281.07:47:31.82#ibcon#about to read 6, iclass 20, count 2 2006.281.07:47:31.82#ibcon#read 6, iclass 20, count 2 2006.281.07:47:31.82#ibcon#end of sib2, iclass 20, count 2 2006.281.07:47:31.82#ibcon#*after write, iclass 20, count 2 2006.281.07:47:31.82#ibcon#*before return 0, iclass 20, count 2 2006.281.07:47:31.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:31.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:47:31.82#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.07:47:31.82#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:31.82#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:31.94#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:31.94#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:31.94#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:47:31.94#ibcon#first serial, iclass 20, count 0 2006.281.07:47:31.94#ibcon#enter sib2, iclass 20, count 0 2006.281.07:47:31.94#ibcon#flushed, iclass 20, count 0 2006.281.07:47:31.94#ibcon#about to write, iclass 20, count 0 2006.281.07:47:31.94#ibcon#wrote, iclass 20, count 0 2006.281.07:47:31.94#ibcon#about to read 3, iclass 20, count 0 2006.281.07:47:31.96#ibcon#read 3, iclass 20, count 0 2006.281.07:47:31.96#ibcon#about to read 4, iclass 20, count 0 2006.281.07:47:31.96#ibcon#read 4, iclass 20, count 0 2006.281.07:47:31.96#ibcon#about to read 5, iclass 20, count 0 2006.281.07:47:31.96#ibcon#read 5, iclass 20, count 0 2006.281.07:47:31.96#ibcon#about to read 6, iclass 20, count 0 2006.281.07:47:31.96#ibcon#read 6, iclass 20, count 0 2006.281.07:47:31.96#ibcon#end of sib2, iclass 20, count 0 2006.281.07:47:31.96#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:47:31.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:47:31.96#ibcon#[27=USB\r\n] 2006.281.07:47:31.96#ibcon#*before write, iclass 20, count 0 2006.281.07:47:31.96#ibcon#enter sib2, iclass 20, count 0 2006.281.07:47:31.96#ibcon#flushed, iclass 20, count 0 2006.281.07:47:31.96#ibcon#about to write, iclass 20, count 0 2006.281.07:47:31.96#ibcon#wrote, iclass 20, count 0 2006.281.07:47:31.96#ibcon#about to read 3, iclass 20, count 0 2006.281.07:47:31.99#ibcon#read 3, iclass 20, count 0 2006.281.07:47:31.99#ibcon#about to read 4, iclass 20, count 0 2006.281.07:47:31.99#ibcon#read 4, iclass 20, count 0 2006.281.07:47:31.99#ibcon#about to read 5, iclass 20, count 0 2006.281.07:47:31.99#ibcon#read 5, iclass 20, count 0 2006.281.07:47:31.99#ibcon#about to read 6, iclass 20, count 0 2006.281.07:47:31.99#ibcon#read 6, iclass 20, count 0 2006.281.07:47:31.99#ibcon#end of sib2, iclass 20, count 0 2006.281.07:47:31.99#ibcon#*after write, iclass 20, count 0 2006.281.07:47:31.99#ibcon#*before return 0, iclass 20, count 0 2006.281.07:47:31.99#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:31.99#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:47:31.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:47:31.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:47:31.99$vc4f8/vblo=3,656.99 2006.281.07:47:31.99#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.07:47:31.99#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.07:47:31.99#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:31.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:31.99#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:31.99#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:31.99#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:47:31.99#ibcon#first serial, iclass 22, count 0 2006.281.07:47:31.99#ibcon#enter sib2, iclass 22, count 0 2006.281.07:47:31.99#ibcon#flushed, iclass 22, count 0 2006.281.07:47:31.99#ibcon#about to write, iclass 22, count 0 2006.281.07:47:31.99#ibcon#wrote, iclass 22, count 0 2006.281.07:47:31.99#ibcon#about to read 3, iclass 22, count 0 2006.281.07:47:32.01#ibcon#read 3, iclass 22, count 0 2006.281.07:47:32.01#ibcon#about to read 4, iclass 22, count 0 2006.281.07:47:32.01#ibcon#read 4, iclass 22, count 0 2006.281.07:47:32.01#ibcon#about to read 5, iclass 22, count 0 2006.281.07:47:32.01#ibcon#read 5, iclass 22, count 0 2006.281.07:47:32.01#ibcon#about to read 6, iclass 22, count 0 2006.281.07:47:32.01#ibcon#read 6, iclass 22, count 0 2006.281.07:47:32.01#ibcon#end of sib2, iclass 22, count 0 2006.281.07:47:32.01#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:47:32.01#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:47:32.01#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:47:32.01#ibcon#*before write, iclass 22, count 0 2006.281.07:47:32.01#ibcon#enter sib2, iclass 22, count 0 2006.281.07:47:32.01#ibcon#flushed, iclass 22, count 0 2006.281.07:47:32.01#ibcon#about to write, iclass 22, count 0 2006.281.07:47:32.01#ibcon#wrote, iclass 22, count 0 2006.281.07:47:32.01#ibcon#about to read 3, iclass 22, count 0 2006.281.07:47:32.05#ibcon#read 3, iclass 22, count 0 2006.281.07:47:32.05#ibcon#about to read 4, iclass 22, count 0 2006.281.07:47:32.05#ibcon#read 4, iclass 22, count 0 2006.281.07:47:32.05#ibcon#about to read 5, iclass 22, count 0 2006.281.07:47:32.05#ibcon#read 5, iclass 22, count 0 2006.281.07:47:32.05#ibcon#about to read 6, iclass 22, count 0 2006.281.07:47:32.05#ibcon#read 6, iclass 22, count 0 2006.281.07:47:32.05#ibcon#end of sib2, iclass 22, count 0 2006.281.07:47:32.05#ibcon#*after write, iclass 22, count 0 2006.281.07:47:32.05#ibcon#*before return 0, iclass 22, count 0 2006.281.07:47:32.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:32.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:47:32.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:47:32.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:47:32.05$vc4f8/vb=3,4 2006.281.07:47:32.05#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.07:47:32.05#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.07:47:32.05#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:32.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:32.11#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:32.11#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:32.11#ibcon#enter wrdev, iclass 24, count 2 2006.281.07:47:32.11#ibcon#first serial, iclass 24, count 2 2006.281.07:47:32.11#ibcon#enter sib2, iclass 24, count 2 2006.281.07:47:32.11#ibcon#flushed, iclass 24, count 2 2006.281.07:47:32.11#ibcon#about to write, iclass 24, count 2 2006.281.07:47:32.11#ibcon#wrote, iclass 24, count 2 2006.281.07:47:32.11#ibcon#about to read 3, iclass 24, count 2 2006.281.07:47:32.13#ibcon#read 3, iclass 24, count 2 2006.281.07:47:32.13#ibcon#about to read 4, iclass 24, count 2 2006.281.07:47:32.13#ibcon#read 4, iclass 24, count 2 2006.281.07:47:32.13#ibcon#about to read 5, iclass 24, count 2 2006.281.07:47:32.13#ibcon#read 5, iclass 24, count 2 2006.281.07:47:32.13#ibcon#about to read 6, iclass 24, count 2 2006.281.07:47:32.13#ibcon#read 6, iclass 24, count 2 2006.281.07:47:32.13#ibcon#end of sib2, iclass 24, count 2 2006.281.07:47:32.13#ibcon#*mode == 0, iclass 24, count 2 2006.281.07:47:32.13#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.07:47:32.13#ibcon#[27=AT03-04\r\n] 2006.281.07:47:32.13#ibcon#*before write, iclass 24, count 2 2006.281.07:47:32.13#ibcon#enter sib2, iclass 24, count 2 2006.281.07:47:32.13#ibcon#flushed, iclass 24, count 2 2006.281.07:47:32.13#ibcon#about to write, iclass 24, count 2 2006.281.07:47:32.13#ibcon#wrote, iclass 24, count 2 2006.281.07:47:32.13#ibcon#about to read 3, iclass 24, count 2 2006.281.07:47:32.16#ibcon#read 3, iclass 24, count 2 2006.281.07:47:32.16#ibcon#about to read 4, iclass 24, count 2 2006.281.07:47:32.16#ibcon#read 4, iclass 24, count 2 2006.281.07:47:32.16#ibcon#about to read 5, iclass 24, count 2 2006.281.07:47:32.16#ibcon#read 5, iclass 24, count 2 2006.281.07:47:32.16#ibcon#about to read 6, iclass 24, count 2 2006.281.07:47:32.16#ibcon#read 6, iclass 24, count 2 2006.281.07:47:32.16#ibcon#end of sib2, iclass 24, count 2 2006.281.07:47:32.16#ibcon#*after write, iclass 24, count 2 2006.281.07:47:32.16#ibcon#*before return 0, iclass 24, count 2 2006.281.07:47:32.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:32.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:47:32.16#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.07:47:32.16#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:32.16#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:32.28#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:32.28#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:32.28#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:47:32.28#ibcon#first serial, iclass 24, count 0 2006.281.07:47:32.28#ibcon#enter sib2, iclass 24, count 0 2006.281.07:47:32.28#ibcon#flushed, iclass 24, count 0 2006.281.07:47:32.28#ibcon#about to write, iclass 24, count 0 2006.281.07:47:32.28#ibcon#wrote, iclass 24, count 0 2006.281.07:47:32.28#ibcon#about to read 3, iclass 24, count 0 2006.281.07:47:32.30#ibcon#read 3, iclass 24, count 0 2006.281.07:47:32.30#ibcon#about to read 4, iclass 24, count 0 2006.281.07:47:32.30#ibcon#read 4, iclass 24, count 0 2006.281.07:47:32.30#ibcon#about to read 5, iclass 24, count 0 2006.281.07:47:32.30#ibcon#read 5, iclass 24, count 0 2006.281.07:47:32.30#ibcon#about to read 6, iclass 24, count 0 2006.281.07:47:32.30#ibcon#read 6, iclass 24, count 0 2006.281.07:47:32.30#ibcon#end of sib2, iclass 24, count 0 2006.281.07:47:32.30#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:47:32.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:47:32.30#ibcon#[27=USB\r\n] 2006.281.07:47:32.30#ibcon#*before write, iclass 24, count 0 2006.281.07:47:32.30#ibcon#enter sib2, iclass 24, count 0 2006.281.07:47:32.30#ibcon#flushed, iclass 24, count 0 2006.281.07:47:32.30#ibcon#about to write, iclass 24, count 0 2006.281.07:47:32.30#ibcon#wrote, iclass 24, count 0 2006.281.07:47:32.30#ibcon#about to read 3, iclass 24, count 0 2006.281.07:47:32.34#ibcon#read 3, iclass 24, count 0 2006.281.07:47:32.34#ibcon#about to read 4, iclass 24, count 0 2006.281.07:47:32.34#ibcon#read 4, iclass 24, count 0 2006.281.07:47:32.34#ibcon#about to read 5, iclass 24, count 0 2006.281.07:47:32.34#ibcon#read 5, iclass 24, count 0 2006.281.07:47:32.34#ibcon#about to read 6, iclass 24, count 0 2006.281.07:47:32.34#ibcon#read 6, iclass 24, count 0 2006.281.07:47:32.34#ibcon#end of sib2, iclass 24, count 0 2006.281.07:47:32.34#ibcon#*after write, iclass 24, count 0 2006.281.07:47:32.34#ibcon#*before return 0, iclass 24, count 0 2006.281.07:47:32.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:32.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:47:32.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:47:32.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:47:32.34$vc4f8/vblo=4,712.99 2006.281.07:47:32.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:47:32.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:47:32.34#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:32.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:32.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:32.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:32.34#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:47:32.34#ibcon#first serial, iclass 26, count 0 2006.281.07:47:32.34#ibcon#enter sib2, iclass 26, count 0 2006.281.07:47:32.34#ibcon#flushed, iclass 26, count 0 2006.281.07:47:32.34#ibcon#about to write, iclass 26, count 0 2006.281.07:47:32.34#ibcon#wrote, iclass 26, count 0 2006.281.07:47:32.34#ibcon#about to read 3, iclass 26, count 0 2006.281.07:47:32.35#ibcon#read 3, iclass 26, count 0 2006.281.07:47:32.35#ibcon#about to read 4, iclass 26, count 0 2006.281.07:47:32.35#ibcon#read 4, iclass 26, count 0 2006.281.07:47:32.35#ibcon#about to read 5, iclass 26, count 0 2006.281.07:47:32.35#ibcon#read 5, iclass 26, count 0 2006.281.07:47:32.35#ibcon#about to read 6, iclass 26, count 0 2006.281.07:47:32.35#ibcon#read 6, iclass 26, count 0 2006.281.07:47:32.35#ibcon#end of sib2, iclass 26, count 0 2006.281.07:47:32.35#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:47:32.35#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:47:32.35#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:47:32.35#ibcon#*before write, iclass 26, count 0 2006.281.07:47:32.35#ibcon#enter sib2, iclass 26, count 0 2006.281.07:47:32.35#ibcon#flushed, iclass 26, count 0 2006.281.07:47:32.35#ibcon#about to write, iclass 26, count 0 2006.281.07:47:32.35#ibcon#wrote, iclass 26, count 0 2006.281.07:47:32.35#ibcon#about to read 3, iclass 26, count 0 2006.281.07:47:32.39#ibcon#read 3, iclass 26, count 0 2006.281.07:47:32.39#ibcon#about to read 4, iclass 26, count 0 2006.281.07:47:32.39#ibcon#read 4, iclass 26, count 0 2006.281.07:47:32.39#ibcon#about to read 5, iclass 26, count 0 2006.281.07:47:32.39#ibcon#read 5, iclass 26, count 0 2006.281.07:47:32.39#ibcon#about to read 6, iclass 26, count 0 2006.281.07:47:32.39#ibcon#read 6, iclass 26, count 0 2006.281.07:47:32.39#ibcon#end of sib2, iclass 26, count 0 2006.281.07:47:32.39#ibcon#*after write, iclass 26, count 0 2006.281.07:47:32.39#ibcon#*before return 0, iclass 26, count 0 2006.281.07:47:32.39#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:32.39#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:47:32.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:47:32.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:47:32.39$vc4f8/vb=4,4 2006.281.07:47:32.39#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:47:32.39#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:47:32.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:32.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:32.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:32.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:32.46#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:47:32.46#ibcon#first serial, iclass 28, count 2 2006.281.07:47:32.46#ibcon#enter sib2, iclass 28, count 2 2006.281.07:47:32.46#ibcon#flushed, iclass 28, count 2 2006.281.07:47:32.46#ibcon#about to write, iclass 28, count 2 2006.281.07:47:32.46#ibcon#wrote, iclass 28, count 2 2006.281.07:47:32.46#ibcon#about to read 3, iclass 28, count 2 2006.281.07:47:32.48#ibcon#read 3, iclass 28, count 2 2006.281.07:47:32.48#ibcon#about to read 4, iclass 28, count 2 2006.281.07:47:32.48#ibcon#read 4, iclass 28, count 2 2006.281.07:47:32.48#ibcon#about to read 5, iclass 28, count 2 2006.281.07:47:32.48#ibcon#read 5, iclass 28, count 2 2006.281.07:47:32.48#ibcon#about to read 6, iclass 28, count 2 2006.281.07:47:32.48#ibcon#read 6, iclass 28, count 2 2006.281.07:47:32.48#ibcon#end of sib2, iclass 28, count 2 2006.281.07:47:32.48#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:47:32.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:47:32.48#ibcon#[27=AT04-04\r\n] 2006.281.07:47:32.48#ibcon#*before write, iclass 28, count 2 2006.281.07:47:32.48#ibcon#enter sib2, iclass 28, count 2 2006.281.07:47:32.48#ibcon#flushed, iclass 28, count 2 2006.281.07:47:32.48#ibcon#about to write, iclass 28, count 2 2006.281.07:47:32.48#ibcon#wrote, iclass 28, count 2 2006.281.07:47:32.48#ibcon#about to read 3, iclass 28, count 2 2006.281.07:47:32.51#ibcon#read 3, iclass 28, count 2 2006.281.07:47:32.51#ibcon#about to read 4, iclass 28, count 2 2006.281.07:47:32.51#ibcon#read 4, iclass 28, count 2 2006.281.07:47:32.51#ibcon#about to read 5, iclass 28, count 2 2006.281.07:47:32.51#ibcon#read 5, iclass 28, count 2 2006.281.07:47:32.51#ibcon#about to read 6, iclass 28, count 2 2006.281.07:47:32.51#ibcon#read 6, iclass 28, count 2 2006.281.07:47:32.51#ibcon#end of sib2, iclass 28, count 2 2006.281.07:47:32.51#ibcon#*after write, iclass 28, count 2 2006.281.07:47:32.51#ibcon#*before return 0, iclass 28, count 2 2006.281.07:47:32.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:32.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:47:32.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:47:32.51#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:32.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:32.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:32.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:32.63#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:47:32.63#ibcon#first serial, iclass 28, count 0 2006.281.07:47:32.63#ibcon#enter sib2, iclass 28, count 0 2006.281.07:47:32.63#ibcon#flushed, iclass 28, count 0 2006.281.07:47:32.63#ibcon#about to write, iclass 28, count 0 2006.281.07:47:32.63#ibcon#wrote, iclass 28, count 0 2006.281.07:47:32.63#ibcon#about to read 3, iclass 28, count 0 2006.281.07:47:32.65#ibcon#read 3, iclass 28, count 0 2006.281.07:47:32.65#ibcon#about to read 4, iclass 28, count 0 2006.281.07:47:32.65#ibcon#read 4, iclass 28, count 0 2006.281.07:47:32.65#ibcon#about to read 5, iclass 28, count 0 2006.281.07:47:32.65#ibcon#read 5, iclass 28, count 0 2006.281.07:47:32.65#ibcon#about to read 6, iclass 28, count 0 2006.281.07:47:32.65#ibcon#read 6, iclass 28, count 0 2006.281.07:47:32.65#ibcon#end of sib2, iclass 28, count 0 2006.281.07:47:32.65#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:47:32.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:47:32.65#ibcon#[27=USB\r\n] 2006.281.07:47:32.65#ibcon#*before write, iclass 28, count 0 2006.281.07:47:32.65#ibcon#enter sib2, iclass 28, count 0 2006.281.07:47:32.65#ibcon#flushed, iclass 28, count 0 2006.281.07:47:32.65#ibcon#about to write, iclass 28, count 0 2006.281.07:47:32.65#ibcon#wrote, iclass 28, count 0 2006.281.07:47:32.65#ibcon#about to read 3, iclass 28, count 0 2006.281.07:47:32.68#ibcon#read 3, iclass 28, count 0 2006.281.07:47:32.68#ibcon#about to read 4, iclass 28, count 0 2006.281.07:47:32.68#ibcon#read 4, iclass 28, count 0 2006.281.07:47:32.68#ibcon#about to read 5, iclass 28, count 0 2006.281.07:47:32.68#ibcon#read 5, iclass 28, count 0 2006.281.07:47:32.68#ibcon#about to read 6, iclass 28, count 0 2006.281.07:47:32.68#ibcon#read 6, iclass 28, count 0 2006.281.07:47:32.68#ibcon#end of sib2, iclass 28, count 0 2006.281.07:47:32.68#ibcon#*after write, iclass 28, count 0 2006.281.07:47:32.68#ibcon#*before return 0, iclass 28, count 0 2006.281.07:47:32.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:32.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:47:32.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:47:32.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:47:32.68$vc4f8/vblo=5,744.99 2006.281.07:47:32.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:47:32.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:47:32.68#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:32.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:32.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:32.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:32.68#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:47:32.68#ibcon#first serial, iclass 30, count 0 2006.281.07:47:32.68#ibcon#enter sib2, iclass 30, count 0 2006.281.07:47:32.68#ibcon#flushed, iclass 30, count 0 2006.281.07:47:32.68#ibcon#about to write, iclass 30, count 0 2006.281.07:47:32.68#ibcon#wrote, iclass 30, count 0 2006.281.07:47:32.68#ibcon#about to read 3, iclass 30, count 0 2006.281.07:47:32.70#ibcon#read 3, iclass 30, count 0 2006.281.07:47:32.70#ibcon#about to read 4, iclass 30, count 0 2006.281.07:47:32.70#ibcon#read 4, iclass 30, count 0 2006.281.07:47:32.70#ibcon#about to read 5, iclass 30, count 0 2006.281.07:47:32.70#ibcon#read 5, iclass 30, count 0 2006.281.07:47:32.70#ibcon#about to read 6, iclass 30, count 0 2006.281.07:47:32.70#ibcon#read 6, iclass 30, count 0 2006.281.07:47:32.70#ibcon#end of sib2, iclass 30, count 0 2006.281.07:47:32.70#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:47:32.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:47:32.70#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:47:32.70#ibcon#*before write, iclass 30, count 0 2006.281.07:47:32.70#ibcon#enter sib2, iclass 30, count 0 2006.281.07:47:32.70#ibcon#flushed, iclass 30, count 0 2006.281.07:47:32.70#ibcon#about to write, iclass 30, count 0 2006.281.07:47:32.70#ibcon#wrote, iclass 30, count 0 2006.281.07:47:32.70#ibcon#about to read 3, iclass 30, count 0 2006.281.07:47:32.74#ibcon#read 3, iclass 30, count 0 2006.281.07:47:32.74#ibcon#about to read 4, iclass 30, count 0 2006.281.07:47:32.74#ibcon#read 4, iclass 30, count 0 2006.281.07:47:32.74#ibcon#about to read 5, iclass 30, count 0 2006.281.07:47:32.74#ibcon#read 5, iclass 30, count 0 2006.281.07:47:32.74#ibcon#about to read 6, iclass 30, count 0 2006.281.07:47:32.74#ibcon#read 6, iclass 30, count 0 2006.281.07:47:32.74#ibcon#end of sib2, iclass 30, count 0 2006.281.07:47:32.74#ibcon#*after write, iclass 30, count 0 2006.281.07:47:32.74#ibcon#*before return 0, iclass 30, count 0 2006.281.07:47:32.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:32.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:47:32.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:47:32.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:47:32.74$vc4f8/vb=5,4 2006.281.07:47:32.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:47:32.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:47:32.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:32.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:32.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:32.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:32.80#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:47:32.80#ibcon#first serial, iclass 32, count 2 2006.281.07:47:32.80#ibcon#enter sib2, iclass 32, count 2 2006.281.07:47:32.80#ibcon#flushed, iclass 32, count 2 2006.281.07:47:32.80#ibcon#about to write, iclass 32, count 2 2006.281.07:47:32.80#ibcon#wrote, iclass 32, count 2 2006.281.07:47:32.80#ibcon#about to read 3, iclass 32, count 2 2006.281.07:47:32.83#ibcon#read 3, iclass 32, count 2 2006.281.07:47:32.83#ibcon#about to read 4, iclass 32, count 2 2006.281.07:47:32.83#ibcon#read 4, iclass 32, count 2 2006.281.07:47:32.83#ibcon#about to read 5, iclass 32, count 2 2006.281.07:47:32.83#ibcon#read 5, iclass 32, count 2 2006.281.07:47:32.83#ibcon#about to read 6, iclass 32, count 2 2006.281.07:47:32.83#ibcon#read 6, iclass 32, count 2 2006.281.07:47:32.83#ibcon#end of sib2, iclass 32, count 2 2006.281.07:47:32.83#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:47:32.83#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:47:32.83#ibcon#[27=AT05-04\r\n] 2006.281.07:47:32.83#ibcon#*before write, iclass 32, count 2 2006.281.07:47:32.83#ibcon#enter sib2, iclass 32, count 2 2006.281.07:47:32.83#ibcon#flushed, iclass 32, count 2 2006.281.07:47:32.83#ibcon#about to write, iclass 32, count 2 2006.281.07:47:32.83#ibcon#wrote, iclass 32, count 2 2006.281.07:47:32.83#ibcon#about to read 3, iclass 32, count 2 2006.281.07:47:32.86#ibcon#read 3, iclass 32, count 2 2006.281.07:47:32.86#ibcon#about to read 4, iclass 32, count 2 2006.281.07:47:32.86#ibcon#read 4, iclass 32, count 2 2006.281.07:47:32.86#ibcon#about to read 5, iclass 32, count 2 2006.281.07:47:32.86#ibcon#read 5, iclass 32, count 2 2006.281.07:47:32.86#ibcon#about to read 6, iclass 32, count 2 2006.281.07:47:32.86#ibcon#read 6, iclass 32, count 2 2006.281.07:47:32.86#ibcon#end of sib2, iclass 32, count 2 2006.281.07:47:32.86#ibcon#*after write, iclass 32, count 2 2006.281.07:47:32.86#ibcon#*before return 0, iclass 32, count 2 2006.281.07:47:32.86#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:32.86#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:47:32.86#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:47:32.86#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:32.86#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:32.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:32.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:32.98#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:47:32.98#ibcon#first serial, iclass 32, count 0 2006.281.07:47:32.98#ibcon#enter sib2, iclass 32, count 0 2006.281.07:47:32.98#ibcon#flushed, iclass 32, count 0 2006.281.07:47:32.98#ibcon#about to write, iclass 32, count 0 2006.281.07:47:32.98#ibcon#wrote, iclass 32, count 0 2006.281.07:47:32.98#ibcon#about to read 3, iclass 32, count 0 2006.281.07:47:33.00#ibcon#read 3, iclass 32, count 0 2006.281.07:47:33.00#ibcon#about to read 4, iclass 32, count 0 2006.281.07:47:33.00#ibcon#read 4, iclass 32, count 0 2006.281.07:47:33.00#ibcon#about to read 5, iclass 32, count 0 2006.281.07:47:33.00#ibcon#read 5, iclass 32, count 0 2006.281.07:47:33.00#ibcon#about to read 6, iclass 32, count 0 2006.281.07:47:33.00#ibcon#read 6, iclass 32, count 0 2006.281.07:47:33.00#ibcon#end of sib2, iclass 32, count 0 2006.281.07:47:33.00#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:47:33.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:47:33.00#ibcon#[27=USB\r\n] 2006.281.07:47:33.00#ibcon#*before write, iclass 32, count 0 2006.281.07:47:33.00#ibcon#enter sib2, iclass 32, count 0 2006.281.07:47:33.00#ibcon#flushed, iclass 32, count 0 2006.281.07:47:33.00#ibcon#about to write, iclass 32, count 0 2006.281.07:47:33.00#ibcon#wrote, iclass 32, count 0 2006.281.07:47:33.00#ibcon#about to read 3, iclass 32, count 0 2006.281.07:47:33.03#ibcon#read 3, iclass 32, count 0 2006.281.07:47:33.03#ibcon#about to read 4, iclass 32, count 0 2006.281.07:47:33.03#ibcon#read 4, iclass 32, count 0 2006.281.07:47:33.03#ibcon#about to read 5, iclass 32, count 0 2006.281.07:47:33.03#ibcon#read 5, iclass 32, count 0 2006.281.07:47:33.03#ibcon#about to read 6, iclass 32, count 0 2006.281.07:47:33.03#ibcon#read 6, iclass 32, count 0 2006.281.07:47:33.03#ibcon#end of sib2, iclass 32, count 0 2006.281.07:47:33.03#ibcon#*after write, iclass 32, count 0 2006.281.07:47:33.03#ibcon#*before return 0, iclass 32, count 0 2006.281.07:47:33.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:33.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:47:33.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:47:33.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:47:33.03$vc4f8/vblo=6,752.99 2006.281.07:47:33.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:47:33.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:47:33.03#ibcon#ireg 17 cls_cnt 0 2006.281.07:47:33.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:33.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:33.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:33.03#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:47:33.03#ibcon#first serial, iclass 34, count 0 2006.281.07:47:33.03#ibcon#enter sib2, iclass 34, count 0 2006.281.07:47:33.03#ibcon#flushed, iclass 34, count 0 2006.281.07:47:33.03#ibcon#about to write, iclass 34, count 0 2006.281.07:47:33.03#ibcon#wrote, iclass 34, count 0 2006.281.07:47:33.03#ibcon#about to read 3, iclass 34, count 0 2006.281.07:47:33.05#ibcon#read 3, iclass 34, count 0 2006.281.07:47:33.05#ibcon#about to read 4, iclass 34, count 0 2006.281.07:47:33.05#ibcon#read 4, iclass 34, count 0 2006.281.07:47:33.05#ibcon#about to read 5, iclass 34, count 0 2006.281.07:47:33.05#ibcon#read 5, iclass 34, count 0 2006.281.07:47:33.05#ibcon#about to read 6, iclass 34, count 0 2006.281.07:47:33.05#ibcon#read 6, iclass 34, count 0 2006.281.07:47:33.05#ibcon#end of sib2, iclass 34, count 0 2006.281.07:47:33.05#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:47:33.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:47:33.05#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:47:33.05#ibcon#*before write, iclass 34, count 0 2006.281.07:47:33.05#ibcon#enter sib2, iclass 34, count 0 2006.281.07:47:33.05#ibcon#flushed, iclass 34, count 0 2006.281.07:47:33.05#ibcon#about to write, iclass 34, count 0 2006.281.07:47:33.05#ibcon#wrote, iclass 34, count 0 2006.281.07:47:33.05#ibcon#about to read 3, iclass 34, count 0 2006.281.07:47:33.09#ibcon#read 3, iclass 34, count 0 2006.281.07:47:33.09#ibcon#about to read 4, iclass 34, count 0 2006.281.07:47:33.09#ibcon#read 4, iclass 34, count 0 2006.281.07:47:33.09#ibcon#about to read 5, iclass 34, count 0 2006.281.07:47:33.09#ibcon#read 5, iclass 34, count 0 2006.281.07:47:33.09#ibcon#about to read 6, iclass 34, count 0 2006.281.07:47:33.09#ibcon#read 6, iclass 34, count 0 2006.281.07:47:33.09#ibcon#end of sib2, iclass 34, count 0 2006.281.07:47:33.09#ibcon#*after write, iclass 34, count 0 2006.281.07:47:33.09#ibcon#*before return 0, iclass 34, count 0 2006.281.07:47:33.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:33.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:47:33.09#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:47:33.09#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:47:33.09$vc4f8/vb=6,4 2006.281.07:47:33.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:47:33.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:47:33.10#ibcon#ireg 11 cls_cnt 2 2006.281.07:47:33.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:33.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:33.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:33.14#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:47:33.14#ibcon#first serial, iclass 36, count 2 2006.281.07:47:33.14#ibcon#enter sib2, iclass 36, count 2 2006.281.07:47:33.14#ibcon#flushed, iclass 36, count 2 2006.281.07:47:33.14#ibcon#about to write, iclass 36, count 2 2006.281.07:47:33.14#ibcon#wrote, iclass 36, count 2 2006.281.07:47:33.14#ibcon#about to read 3, iclass 36, count 2 2006.281.07:47:33.16#ibcon#read 3, iclass 36, count 2 2006.281.07:47:33.16#ibcon#about to read 4, iclass 36, count 2 2006.281.07:47:33.16#ibcon#read 4, iclass 36, count 2 2006.281.07:47:33.16#ibcon#about to read 5, iclass 36, count 2 2006.281.07:47:33.16#ibcon#read 5, iclass 36, count 2 2006.281.07:47:33.16#ibcon#about to read 6, iclass 36, count 2 2006.281.07:47:33.16#ibcon#read 6, iclass 36, count 2 2006.281.07:47:33.16#ibcon#end of sib2, iclass 36, count 2 2006.281.07:47:33.16#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:47:33.16#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:47:33.16#ibcon#[27=AT06-04\r\n] 2006.281.07:47:33.16#ibcon#*before write, iclass 36, count 2 2006.281.07:47:33.16#ibcon#enter sib2, iclass 36, count 2 2006.281.07:47:33.16#ibcon#flushed, iclass 36, count 2 2006.281.07:47:33.16#ibcon#about to write, iclass 36, count 2 2006.281.07:47:33.16#ibcon#wrote, iclass 36, count 2 2006.281.07:47:33.16#ibcon#about to read 3, iclass 36, count 2 2006.281.07:47:33.19#ibcon#read 3, iclass 36, count 2 2006.281.07:47:33.19#ibcon#about to read 4, iclass 36, count 2 2006.281.07:47:33.19#ibcon#read 4, iclass 36, count 2 2006.281.07:47:33.19#ibcon#about to read 5, iclass 36, count 2 2006.281.07:47:33.19#ibcon#read 5, iclass 36, count 2 2006.281.07:47:33.19#ibcon#about to read 6, iclass 36, count 2 2006.281.07:47:33.19#ibcon#read 6, iclass 36, count 2 2006.281.07:47:33.19#ibcon#end of sib2, iclass 36, count 2 2006.281.07:47:33.19#ibcon#*after write, iclass 36, count 2 2006.281.07:47:33.19#ibcon#*before return 0, iclass 36, count 2 2006.281.07:47:33.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:33.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:47:33.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:47:33.19#ibcon#ireg 7 cls_cnt 0 2006.281.07:47:33.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:33.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:33.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:33.31#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:47:33.31#ibcon#first serial, iclass 36, count 0 2006.281.07:47:33.31#ibcon#enter sib2, iclass 36, count 0 2006.281.07:47:33.31#ibcon#flushed, iclass 36, count 0 2006.281.07:47:33.31#ibcon#about to write, iclass 36, count 0 2006.281.07:47:33.31#ibcon#wrote, iclass 36, count 0 2006.281.07:47:33.31#ibcon#about to read 3, iclass 36, count 0 2006.281.07:47:33.33#ibcon#read 3, iclass 36, count 0 2006.281.07:47:33.33#ibcon#about to read 4, iclass 36, count 0 2006.281.07:47:33.33#ibcon#read 4, iclass 36, count 0 2006.281.07:47:33.33#ibcon#about to read 5, iclass 36, count 0 2006.281.07:47:33.33#ibcon#read 5, iclass 36, count 0 2006.281.07:47:33.33#ibcon#about to read 6, iclass 36, count 0 2006.281.07:47:33.33#ibcon#read 6, iclass 36, count 0 2006.281.07:47:33.33#ibcon#end of sib2, iclass 36, count 0 2006.281.07:47:33.33#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:47:33.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:47:33.33#ibcon#[27=USB\r\n] 2006.281.07:47:33.33#ibcon#*before write, iclass 36, count 0 2006.281.07:47:33.33#ibcon#enter sib2, iclass 36, count 0 2006.281.07:47:33.33#ibcon#flushed, iclass 36, count 0 2006.281.07:47:33.33#ibcon#about to write, iclass 36, count 0 2006.281.07:47:33.33#ibcon#wrote, iclass 36, count 0 2006.281.07:47:33.33#ibcon#about to read 3, iclass 36, count 0 2006.281.07:47:33.37#ibcon#read 3, iclass 36, count 0 2006.281.07:47:33.37#ibcon#about to read 4, iclass 36, count 0 2006.281.07:47:33.37#ibcon#read 4, iclass 36, count 0 2006.281.07:47:33.37#ibcon#about to read 5, iclass 36, count 0 2006.281.07:47:33.37#ibcon#read 5, iclass 36, count 0 2006.281.07:47:33.37#ibcon#about to read 6, iclass 36, count 0 2006.281.07:47:33.37#ibcon#read 6, iclass 36, count 0 2006.281.07:47:33.37#ibcon#end of sib2, iclass 36, count 0 2006.281.07:47:33.37#ibcon#*after write, iclass 36, count 0 2006.281.07:47:33.37#ibcon#*before return 0, iclass 36, count 0 2006.281.07:47:33.37#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:33.37#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:47:33.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:47:33.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:47:33.37$vc4f8/vabw=wide 2006.281.07:47:33.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:47:33.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:47:33.37#ibcon#ireg 8 cls_cnt 0 2006.281.07:47:33.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:33.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:33.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:33.37#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:47:33.37#ibcon#first serial, iclass 38, count 0 2006.281.07:47:33.37#ibcon#enter sib2, iclass 38, count 0 2006.281.07:47:33.37#ibcon#flushed, iclass 38, count 0 2006.281.07:47:33.37#ibcon#about to write, iclass 38, count 0 2006.281.07:47:33.37#ibcon#wrote, iclass 38, count 0 2006.281.07:47:33.37#ibcon#about to read 3, iclass 38, count 0 2006.281.07:47:33.38#ibcon#read 3, iclass 38, count 0 2006.281.07:47:33.38#ibcon#about to read 4, iclass 38, count 0 2006.281.07:47:33.38#ibcon#read 4, iclass 38, count 0 2006.281.07:47:33.38#ibcon#about to read 5, iclass 38, count 0 2006.281.07:47:33.38#ibcon#read 5, iclass 38, count 0 2006.281.07:47:33.38#ibcon#about to read 6, iclass 38, count 0 2006.281.07:47:33.38#ibcon#read 6, iclass 38, count 0 2006.281.07:47:33.38#ibcon#end of sib2, iclass 38, count 0 2006.281.07:47:33.39#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:47:33.39#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:47:33.39#ibcon#[25=BW32\r\n] 2006.281.07:47:33.39#ibcon#*before write, iclass 38, count 0 2006.281.07:47:33.39#ibcon#enter sib2, iclass 38, count 0 2006.281.07:47:33.39#ibcon#flushed, iclass 38, count 0 2006.281.07:47:33.39#ibcon#about to write, iclass 38, count 0 2006.281.07:47:33.39#ibcon#wrote, iclass 38, count 0 2006.281.07:47:33.39#ibcon#about to read 3, iclass 38, count 0 2006.281.07:47:33.42#ibcon#read 3, iclass 38, count 0 2006.281.07:47:33.42#ibcon#about to read 4, iclass 38, count 0 2006.281.07:47:33.42#ibcon#read 4, iclass 38, count 0 2006.281.07:47:33.42#ibcon#about to read 5, iclass 38, count 0 2006.281.07:47:33.42#ibcon#read 5, iclass 38, count 0 2006.281.07:47:33.42#ibcon#about to read 6, iclass 38, count 0 2006.281.07:47:33.42#ibcon#read 6, iclass 38, count 0 2006.281.07:47:33.42#ibcon#end of sib2, iclass 38, count 0 2006.281.07:47:33.42#ibcon#*after write, iclass 38, count 0 2006.281.07:47:33.42#ibcon#*before return 0, iclass 38, count 0 2006.281.07:47:33.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:33.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:47:33.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:47:33.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:47:33.42$vc4f8/vbbw=wide 2006.281.07:47:33.42#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:47:33.42#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:47:33.42#ibcon#ireg 8 cls_cnt 0 2006.281.07:47:33.42#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:47:33.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:47:33.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:47:33.49#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:47:33.49#ibcon#first serial, iclass 40, count 0 2006.281.07:47:33.49#ibcon#enter sib2, iclass 40, count 0 2006.281.07:47:33.49#ibcon#flushed, iclass 40, count 0 2006.281.07:47:33.49#ibcon#about to write, iclass 40, count 0 2006.281.07:47:33.49#ibcon#wrote, iclass 40, count 0 2006.281.07:47:33.49#ibcon#about to read 3, iclass 40, count 0 2006.281.07:47:33.51#ibcon#read 3, iclass 40, count 0 2006.281.07:47:33.51#ibcon#about to read 4, iclass 40, count 0 2006.281.07:47:33.51#ibcon#read 4, iclass 40, count 0 2006.281.07:47:33.51#ibcon#about to read 5, iclass 40, count 0 2006.281.07:47:33.51#ibcon#read 5, iclass 40, count 0 2006.281.07:47:33.51#ibcon#about to read 6, iclass 40, count 0 2006.281.07:47:33.51#ibcon#read 6, iclass 40, count 0 2006.281.07:47:33.51#ibcon#end of sib2, iclass 40, count 0 2006.281.07:47:33.51#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:47:33.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:47:33.51#ibcon#[27=BW32\r\n] 2006.281.07:47:33.51#ibcon#*before write, iclass 40, count 0 2006.281.07:47:33.51#ibcon#enter sib2, iclass 40, count 0 2006.281.07:47:33.51#ibcon#flushed, iclass 40, count 0 2006.281.07:47:33.51#ibcon#about to write, iclass 40, count 0 2006.281.07:47:33.51#ibcon#wrote, iclass 40, count 0 2006.281.07:47:33.51#ibcon#about to read 3, iclass 40, count 0 2006.281.07:47:33.54#ibcon#read 3, iclass 40, count 0 2006.281.07:47:33.54#ibcon#about to read 4, iclass 40, count 0 2006.281.07:47:33.54#ibcon#read 4, iclass 40, count 0 2006.281.07:47:33.54#ibcon#about to read 5, iclass 40, count 0 2006.281.07:47:33.54#ibcon#read 5, iclass 40, count 0 2006.281.07:47:33.54#ibcon#about to read 6, iclass 40, count 0 2006.281.07:47:33.54#ibcon#read 6, iclass 40, count 0 2006.281.07:47:33.54#ibcon#end of sib2, iclass 40, count 0 2006.281.07:47:33.54#ibcon#*after write, iclass 40, count 0 2006.281.07:47:33.54#ibcon#*before return 0, iclass 40, count 0 2006.281.07:47:33.54#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:47:33.54#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:47:33.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:47:33.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:47:33.54$4f8m12a/ifd4f 2006.281.07:47:33.54$ifd4f/lo= 2006.281.07:47:33.54$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:47:33.54$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:47:33.54$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:47:33.54$ifd4f/patch= 2006.281.07:47:33.54$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:47:33.54$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:47:33.54$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:47:33.54$4f8m12a/"form=m,16.000,1:2 2006.281.07:47:33.54$4f8m12a/"tpicd 2006.281.07:47:33.54$4f8m12a/echo=off 2006.281.07:47:33.54$4f8m12a/xlog=off 2006.281.07:47:33.54:!2006.281.07:48:00 2006.281.07:47:54.14#trakl#Source acquired 2006.281.07:47:54.14#flagr#flagr/antenna,acquired 2006.281.07:47:58.14#trakl#Off source 2006.281.07:47:58.14?ERROR st -7 Antenna off-source! 2006.281.07:47:58.14#trakl#az 248.352 el 49.516 azerr*cos(el) -0.0010 elerr -0.0207 2006.281.07:48:00.00:preob 2006.281.07:48:00.14#flagr#flagr/antenna,off-source 2006.281.07:48:01.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:48:01.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:48:01.14/onsource/SLEWING 2006.281.07:48:01.14:!2006.281.07:48:10 2006.281.07:48:05.14#trakl#Source re-acquired 2006.281.07:48:05.14#flagr#flagr/antenna,re-acquired 2006.281.07:48:10.00:data_valid=on 2006.281.07:48:10.00:midob 2006.281.07:48:10.14/onsource/TRACKING 2006.281.07:48:10.14/wx/20.95,1001.2,50 2006.281.07:48:10.22/cable/+6.4868E-03 2006.281.07:48:11.31/va/01,07,usb,yes,32,34 2006.281.07:48:11.31/va/02,06,usb,yes,30,31 2006.281.07:48:11.31/va/03,06,usb,yes,28,28 2006.281.07:48:11.31/va/04,06,usb,yes,31,33 2006.281.07:48:11.31/va/05,07,usb,yes,29,30 2006.281.07:48:11.31/va/06,06,usb,yes,28,27 2006.281.07:48:11.31/va/07,06,usb,yes,28,28 2006.281.07:48:11.31/va/08,06,usb,yes,30,30 2006.281.07:48:11.54/valo/01,532.99,yes,locked 2006.281.07:48:11.54/valo/02,572.99,yes,locked 2006.281.07:48:11.54/valo/03,672.99,yes,locked 2006.281.07:48:11.54/valo/04,832.99,yes,locked 2006.281.07:48:11.54/valo/05,652.99,yes,locked 2006.281.07:48:11.54/valo/06,772.99,yes,locked 2006.281.07:48:11.54/valo/07,832.99,yes,locked 2006.281.07:48:11.54/valo/08,852.99,yes,locked 2006.281.07:48:12.63/vb/01,04,usb,yes,30,29 2006.281.07:48:12.63/vb/02,05,usb,yes,28,29 2006.281.07:48:12.63/vb/03,04,usb,yes,28,32 2006.281.07:48:12.63/vb/04,04,usb,yes,29,29 2006.281.07:48:12.63/vb/05,04,usb,yes,27,31 2006.281.07:48:12.63/vb/06,04,usb,yes,27,31 2006.281.07:48:12.63/vb/07,04,usb,yes,30,30 2006.281.07:48:12.63/vb/08,04,usb,yes,27,31 2006.281.07:48:12.86/vblo/01,632.99,yes,locked 2006.281.07:48:12.86/vblo/02,640.99,yes,locked 2006.281.07:48:12.86/vblo/03,656.99,yes,locked 2006.281.07:48:12.86/vblo/04,712.99,yes,locked 2006.281.07:48:12.86/vblo/05,744.99,yes,locked 2006.281.07:48:12.86/vblo/06,752.99,yes,locked 2006.281.07:48:12.86/vblo/07,734.99,yes,locked 2006.281.07:48:12.86/vblo/08,744.99,yes,locked 2006.281.07:48:13.01/vabw/8 2006.281.07:48:13.16/vbbw/8 2006.281.07:48:13.37/xfe/off,on,12.0 2006.281.07:48:13.74/ifatt/23,28,28,28 2006.281.07:48:14.07/fmout-gps/S +3.09E-07 2006.281.07:48:14.09:!2006.281.07:49:10 2006.281.07:48:25.14#trakl#Off source 2006.281.07:48:25.14?ERROR st -7 Antenna off-source! 2006.281.07:48:25.14#trakl#az 248.457 el 49.431 azerr*cos(el) 0.0011 elerr -0.0199 2006.281.07:48:27.14#flagr#flagr/antenna,off-source 2006.281.07:48:34.14#trakl#Source re-acquired 2006.281.07:48:36.14#flagr#flagr/antenna,re-acquired 2006.281.07:48:41.14#trakl#Off source 2006.281.07:48:41.14?ERROR st -7 Antenna off-source! 2006.281.07:48:41.14#trakl#az 248.520 el 49.381 azerr*cos(el) 0.0001 elerr -0.0197 2006.281.07:48:42.14#flagr#flagr/antenna,off-source 2006.281.07:48:47.14#trakl#Source re-acquired 2006.281.07:48:48.14#flagr#flagr/antenna,re-acquired 2006.281.07:48:51.14#trakl#Off source 2006.281.07:48:51.14?ERROR st -7 Antenna off-source! 2006.281.07:48:51.14#trakl#az 248.559 el 49.349 azerr*cos(el) -0.0019 elerr -0.0212 2006.281.07:48:51.14#flagr#flagr/antenna,off-source 2006.281.07:48:57.14#trakl#Source re-acquired 2006.281.07:48:57.14#flagr#flagr/antenna,re-acquired 2006.281.07:49:06.14#trakl#Off source 2006.281.07:49:06.14?ERROR st -7 Antenna off-source! 2006.281.07:49:06.14#trakl#az 248.617 el 49.302 azerr*cos(el) -0.0002 elerr -0.0181 2006.281.07:49:06.14#flagr#flagr/antenna,off-source 2006.281.07:49:10.01:data_valid=off 2006.281.07:49:10.01:postob 2006.281.07:49:10.11/cable/+6.4864E-03 2006.281.07:49:10.11/wx/20.93,1001.2,51 2006.281.07:49:11.08/fmout-gps/S +3.09E-07 2006.281.07:49:11.08:scan_name=281-0750,k06281,60 2006.281.07:49:11.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.281.07:49:11.14#flagr#flagr/antenna,new-source 2006.281.07:49:12.14:checkk5 2006.281.07:49:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:49:13.01/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:49:13.41/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:49:13.85/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:49:14.28/chk_obsdata//k5ts1/T2810748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:49:14.89/chk_obsdata//k5ts2/T2810748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:49:15.29/chk_obsdata//k5ts3/T2810748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:49:15.74/chk_obsdata//k5ts4/T2810748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:49:16.58/k5log//k5ts1_log_newline 2006.281.07:49:17.42/k5log//k5ts2_log_newline 2006.281.07:49:18.49/k5log//k5ts3_log_newline 2006.281.07:49:19.65/k5log//k5ts4_log_newline 2006.281.07:49:19.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:49:19.68:4f8m12a=1 2006.281.07:49:19.68$4f8m12a/echo=on 2006.281.07:49:19.68$4f8m12a/pcalon 2006.281.07:49:19.68$pcalon/"no phase cal control is implemented here 2006.281.07:49:19.68$4f8m12a/"tpicd=stop 2006.281.07:49:19.68$4f8m12a/vc4f8 2006.281.07:49:19.68$vc4f8/valo=1,532.99 2006.281.07:49:19.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:49:19.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:49:19.68#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:19.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:19.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:19.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:19.68#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:49:19.68#ibcon#first serial, iclass 20, count 0 2006.281.07:49:19.68#ibcon#enter sib2, iclass 20, count 0 2006.281.07:49:19.68#ibcon#flushed, iclass 20, count 0 2006.281.07:49:19.68#ibcon#about to write, iclass 20, count 0 2006.281.07:49:19.68#ibcon#wrote, iclass 20, count 0 2006.281.07:49:19.68#ibcon#about to read 3, iclass 20, count 0 2006.281.07:49:19.70#ibcon#read 3, iclass 20, count 0 2006.281.07:49:19.70#ibcon#about to read 4, iclass 20, count 0 2006.281.07:49:19.70#ibcon#read 4, iclass 20, count 0 2006.281.07:49:19.70#ibcon#about to read 5, iclass 20, count 0 2006.281.07:49:19.70#ibcon#read 5, iclass 20, count 0 2006.281.07:49:19.70#ibcon#about to read 6, iclass 20, count 0 2006.281.07:49:19.70#ibcon#read 6, iclass 20, count 0 2006.281.07:49:19.70#ibcon#end of sib2, iclass 20, count 0 2006.281.07:49:19.70#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:49:19.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:49:19.70#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:49:19.70#ibcon#*before write, iclass 20, count 0 2006.281.07:49:19.70#ibcon#enter sib2, iclass 20, count 0 2006.281.07:49:19.70#ibcon#flushed, iclass 20, count 0 2006.281.07:49:19.70#ibcon#about to write, iclass 20, count 0 2006.281.07:49:19.70#ibcon#wrote, iclass 20, count 0 2006.281.07:49:19.70#ibcon#about to read 3, iclass 20, count 0 2006.281.07:49:19.75#ibcon#read 3, iclass 20, count 0 2006.281.07:49:19.75#ibcon#about to read 4, iclass 20, count 0 2006.281.07:49:19.75#ibcon#read 4, iclass 20, count 0 2006.281.07:49:19.75#ibcon#about to read 5, iclass 20, count 0 2006.281.07:49:19.75#ibcon#read 5, iclass 20, count 0 2006.281.07:49:19.75#ibcon#about to read 6, iclass 20, count 0 2006.281.07:49:19.75#ibcon#read 6, iclass 20, count 0 2006.281.07:49:19.75#ibcon#end of sib2, iclass 20, count 0 2006.281.07:49:19.75#ibcon#*after write, iclass 20, count 0 2006.281.07:49:19.75#ibcon#*before return 0, iclass 20, count 0 2006.281.07:49:19.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:19.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:19.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:49:19.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:49:19.75$vc4f8/va=1,7 2006.281.07:49:19.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:49:19.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:49:19.76#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:19.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:19.76#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:19.76#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:19.76#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:49:19.76#ibcon#first serial, iclass 22, count 2 2006.281.07:49:19.76#ibcon#enter sib2, iclass 22, count 2 2006.281.07:49:19.76#ibcon#flushed, iclass 22, count 2 2006.281.07:49:19.76#ibcon#about to write, iclass 22, count 2 2006.281.07:49:19.76#ibcon#wrote, iclass 22, count 2 2006.281.07:49:19.76#ibcon#about to read 3, iclass 22, count 2 2006.281.07:49:19.77#ibcon#read 3, iclass 22, count 2 2006.281.07:49:19.77#ibcon#about to read 4, iclass 22, count 2 2006.281.07:49:19.77#ibcon#read 4, iclass 22, count 2 2006.281.07:49:19.77#ibcon#about to read 5, iclass 22, count 2 2006.281.07:49:19.77#ibcon#read 5, iclass 22, count 2 2006.281.07:49:19.77#ibcon#about to read 6, iclass 22, count 2 2006.281.07:49:19.77#ibcon#read 6, iclass 22, count 2 2006.281.07:49:19.77#ibcon#end of sib2, iclass 22, count 2 2006.281.07:49:19.77#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:49:19.77#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:49:19.77#ibcon#[25=AT01-07\r\n] 2006.281.07:49:19.77#ibcon#*before write, iclass 22, count 2 2006.281.07:49:19.77#ibcon#enter sib2, iclass 22, count 2 2006.281.07:49:19.77#ibcon#flushed, iclass 22, count 2 2006.281.07:49:19.77#ibcon#about to write, iclass 22, count 2 2006.281.07:49:19.77#ibcon#wrote, iclass 22, count 2 2006.281.07:49:19.77#ibcon#about to read 3, iclass 22, count 2 2006.281.07:49:19.80#ibcon#read 3, iclass 22, count 2 2006.281.07:49:19.80#ibcon#about to read 4, iclass 22, count 2 2006.281.07:49:19.80#ibcon#read 4, iclass 22, count 2 2006.281.07:49:19.80#ibcon#about to read 5, iclass 22, count 2 2006.281.07:49:19.80#ibcon#read 5, iclass 22, count 2 2006.281.07:49:19.80#ibcon#about to read 6, iclass 22, count 2 2006.281.07:49:19.80#ibcon#read 6, iclass 22, count 2 2006.281.07:49:19.80#ibcon#end of sib2, iclass 22, count 2 2006.281.07:49:19.80#ibcon#*after write, iclass 22, count 2 2006.281.07:49:19.80#ibcon#*before return 0, iclass 22, count 2 2006.281.07:49:19.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:19.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:19.80#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:49:19.80#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:19.80#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:19.93#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:19.93#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:19.93#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:49:19.93#ibcon#first serial, iclass 22, count 0 2006.281.07:49:19.93#ibcon#enter sib2, iclass 22, count 0 2006.281.07:49:19.93#ibcon#flushed, iclass 22, count 0 2006.281.07:49:19.93#ibcon#about to write, iclass 22, count 0 2006.281.07:49:19.93#ibcon#wrote, iclass 22, count 0 2006.281.07:49:19.93#ibcon#about to read 3, iclass 22, count 0 2006.281.07:49:19.94#ibcon#read 3, iclass 22, count 0 2006.281.07:49:19.94#ibcon#about to read 4, iclass 22, count 0 2006.281.07:49:19.94#ibcon#read 4, iclass 22, count 0 2006.281.07:49:19.94#ibcon#about to read 5, iclass 22, count 0 2006.281.07:49:19.94#ibcon#read 5, iclass 22, count 0 2006.281.07:49:19.94#ibcon#about to read 6, iclass 22, count 0 2006.281.07:49:19.94#ibcon#read 6, iclass 22, count 0 2006.281.07:49:19.94#ibcon#end of sib2, iclass 22, count 0 2006.281.07:49:19.94#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:49:19.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:49:19.94#ibcon#[25=USB\r\n] 2006.281.07:49:19.94#ibcon#*before write, iclass 22, count 0 2006.281.07:49:19.94#ibcon#enter sib2, iclass 22, count 0 2006.281.07:49:19.94#ibcon#flushed, iclass 22, count 0 2006.281.07:49:19.94#ibcon#about to write, iclass 22, count 0 2006.281.07:49:19.94#ibcon#wrote, iclass 22, count 0 2006.281.07:49:19.94#ibcon#about to read 3, iclass 22, count 0 2006.281.07:49:19.97#ibcon#read 3, iclass 22, count 0 2006.281.07:49:19.97#ibcon#about to read 4, iclass 22, count 0 2006.281.07:49:19.97#ibcon#read 4, iclass 22, count 0 2006.281.07:49:19.97#ibcon#about to read 5, iclass 22, count 0 2006.281.07:49:19.97#ibcon#read 5, iclass 22, count 0 2006.281.07:49:19.97#ibcon#about to read 6, iclass 22, count 0 2006.281.07:49:19.97#ibcon#read 6, iclass 22, count 0 2006.281.07:49:19.97#ibcon#end of sib2, iclass 22, count 0 2006.281.07:49:19.97#ibcon#*after write, iclass 22, count 0 2006.281.07:49:19.97#ibcon#*before return 0, iclass 22, count 0 2006.281.07:49:19.97#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:19.97#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:19.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:49:19.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:49:19.97$vc4f8/valo=2,572.99 2006.281.07:49:19.97#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:49:19.97#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:49:19.97#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:19.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:19.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:19.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:19.97#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:49:19.97#ibcon#first serial, iclass 24, count 0 2006.281.07:49:19.97#ibcon#enter sib2, iclass 24, count 0 2006.281.07:49:19.97#ibcon#flushed, iclass 24, count 0 2006.281.07:49:19.97#ibcon#about to write, iclass 24, count 0 2006.281.07:49:19.97#ibcon#wrote, iclass 24, count 0 2006.281.07:49:19.97#ibcon#about to read 3, iclass 24, count 0 2006.281.07:49:19.99#ibcon#read 3, iclass 24, count 0 2006.281.07:49:19.99#ibcon#about to read 4, iclass 24, count 0 2006.281.07:49:19.99#ibcon#read 4, iclass 24, count 0 2006.281.07:49:19.99#ibcon#about to read 5, iclass 24, count 0 2006.281.07:49:19.99#ibcon#read 5, iclass 24, count 0 2006.281.07:49:19.99#ibcon#about to read 6, iclass 24, count 0 2006.281.07:49:19.99#ibcon#read 6, iclass 24, count 0 2006.281.07:49:19.99#ibcon#end of sib2, iclass 24, count 0 2006.281.07:49:19.99#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:49:19.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:49:19.99#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:49:19.99#ibcon#*before write, iclass 24, count 0 2006.281.07:49:19.99#ibcon#enter sib2, iclass 24, count 0 2006.281.07:49:19.99#ibcon#flushed, iclass 24, count 0 2006.281.07:49:19.99#ibcon#about to write, iclass 24, count 0 2006.281.07:49:19.99#ibcon#wrote, iclass 24, count 0 2006.281.07:49:19.99#ibcon#about to read 3, iclass 24, count 0 2006.281.07:49:20.03#ibcon#read 3, iclass 24, count 0 2006.281.07:49:20.03#ibcon#about to read 4, iclass 24, count 0 2006.281.07:49:20.03#ibcon#read 4, iclass 24, count 0 2006.281.07:49:20.03#ibcon#about to read 5, iclass 24, count 0 2006.281.07:49:20.03#ibcon#read 5, iclass 24, count 0 2006.281.07:49:20.03#ibcon#about to read 6, iclass 24, count 0 2006.281.07:49:20.03#ibcon#read 6, iclass 24, count 0 2006.281.07:49:20.03#ibcon#end of sib2, iclass 24, count 0 2006.281.07:49:20.03#ibcon#*after write, iclass 24, count 0 2006.281.07:49:20.03#ibcon#*before return 0, iclass 24, count 0 2006.281.07:49:20.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:20.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:20.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:49:20.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:49:20.03$vc4f8/va=2,6 2006.281.07:49:20.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:49:20.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:49:20.03#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:20.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:20.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:20.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:20.09#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:49:20.09#ibcon#first serial, iclass 26, count 2 2006.281.07:49:20.09#ibcon#enter sib2, iclass 26, count 2 2006.281.07:49:20.09#ibcon#flushed, iclass 26, count 2 2006.281.07:49:20.09#ibcon#about to write, iclass 26, count 2 2006.281.07:49:20.09#ibcon#wrote, iclass 26, count 2 2006.281.07:49:20.09#ibcon#about to read 3, iclass 26, count 2 2006.281.07:49:20.11#ibcon#read 3, iclass 26, count 2 2006.281.07:49:20.11#ibcon#about to read 4, iclass 26, count 2 2006.281.07:49:20.11#ibcon#read 4, iclass 26, count 2 2006.281.07:49:20.11#ibcon#about to read 5, iclass 26, count 2 2006.281.07:49:20.11#ibcon#read 5, iclass 26, count 2 2006.281.07:49:20.11#ibcon#about to read 6, iclass 26, count 2 2006.281.07:49:20.11#ibcon#read 6, iclass 26, count 2 2006.281.07:49:20.11#ibcon#end of sib2, iclass 26, count 2 2006.281.07:49:20.11#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:49:20.11#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:49:20.11#ibcon#[25=AT02-06\r\n] 2006.281.07:49:20.11#ibcon#*before write, iclass 26, count 2 2006.281.07:49:20.11#ibcon#enter sib2, iclass 26, count 2 2006.281.07:49:20.11#ibcon#flushed, iclass 26, count 2 2006.281.07:49:20.11#ibcon#about to write, iclass 26, count 2 2006.281.07:49:20.11#ibcon#wrote, iclass 26, count 2 2006.281.07:49:20.11#ibcon#about to read 3, iclass 26, count 2 2006.281.07:49:20.14#ibcon#read 3, iclass 26, count 2 2006.281.07:49:20.14#ibcon#about to read 4, iclass 26, count 2 2006.281.07:49:20.14#ibcon#read 4, iclass 26, count 2 2006.281.07:49:20.14#ibcon#about to read 5, iclass 26, count 2 2006.281.07:49:20.14#ibcon#read 5, iclass 26, count 2 2006.281.07:49:20.14#ibcon#about to read 6, iclass 26, count 2 2006.281.07:49:20.14#ibcon#read 6, iclass 26, count 2 2006.281.07:49:20.14#ibcon#end of sib2, iclass 26, count 2 2006.281.07:49:20.14#ibcon#*after write, iclass 26, count 2 2006.281.07:49:20.14#ibcon#*before return 0, iclass 26, count 2 2006.281.07:49:20.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:20.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:20.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:49:20.14#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:20.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:20.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:20.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:20.26#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:49:20.26#ibcon#first serial, iclass 26, count 0 2006.281.07:49:20.26#ibcon#enter sib2, iclass 26, count 0 2006.281.07:49:20.26#ibcon#flushed, iclass 26, count 0 2006.281.07:49:20.26#ibcon#about to write, iclass 26, count 0 2006.281.07:49:20.26#ibcon#wrote, iclass 26, count 0 2006.281.07:49:20.26#ibcon#about to read 3, iclass 26, count 0 2006.281.07:49:20.28#ibcon#read 3, iclass 26, count 0 2006.281.07:49:20.28#ibcon#about to read 4, iclass 26, count 0 2006.281.07:49:20.28#ibcon#read 4, iclass 26, count 0 2006.281.07:49:20.28#ibcon#about to read 5, iclass 26, count 0 2006.281.07:49:20.28#ibcon#read 5, iclass 26, count 0 2006.281.07:49:20.28#ibcon#about to read 6, iclass 26, count 0 2006.281.07:49:20.28#ibcon#read 6, iclass 26, count 0 2006.281.07:49:20.28#ibcon#end of sib2, iclass 26, count 0 2006.281.07:49:20.28#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:49:20.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:49:20.28#ibcon#[25=USB\r\n] 2006.281.07:49:20.28#ibcon#*before write, iclass 26, count 0 2006.281.07:49:20.28#ibcon#enter sib2, iclass 26, count 0 2006.281.07:49:20.28#ibcon#flushed, iclass 26, count 0 2006.281.07:49:20.28#ibcon#about to write, iclass 26, count 0 2006.281.07:49:20.28#ibcon#wrote, iclass 26, count 0 2006.281.07:49:20.28#ibcon#about to read 3, iclass 26, count 0 2006.281.07:49:20.32#ibcon#read 3, iclass 26, count 0 2006.281.07:49:20.32#ibcon#about to read 4, iclass 26, count 0 2006.281.07:49:20.32#ibcon#read 4, iclass 26, count 0 2006.281.07:49:20.32#ibcon#about to read 5, iclass 26, count 0 2006.281.07:49:20.32#ibcon#read 5, iclass 26, count 0 2006.281.07:49:20.32#ibcon#about to read 6, iclass 26, count 0 2006.281.07:49:20.32#ibcon#read 6, iclass 26, count 0 2006.281.07:49:20.32#ibcon#end of sib2, iclass 26, count 0 2006.281.07:49:20.32#ibcon#*after write, iclass 26, count 0 2006.281.07:49:20.32#ibcon#*before return 0, iclass 26, count 0 2006.281.07:49:20.32#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:20.32#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:20.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:49:20.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:49:20.32$vc4f8/valo=3,672.99 2006.281.07:49:20.32#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:49:20.32#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:49:20.32#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:20.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:20.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:20.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:20.32#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:49:20.32#ibcon#first serial, iclass 28, count 0 2006.281.07:49:20.32#ibcon#enter sib2, iclass 28, count 0 2006.281.07:49:20.32#ibcon#flushed, iclass 28, count 0 2006.281.07:49:20.32#ibcon#about to write, iclass 28, count 0 2006.281.07:49:20.32#ibcon#wrote, iclass 28, count 0 2006.281.07:49:20.32#ibcon#about to read 3, iclass 28, count 0 2006.281.07:49:20.33#ibcon#read 3, iclass 28, count 0 2006.281.07:49:20.33#ibcon#about to read 4, iclass 28, count 0 2006.281.07:49:20.33#ibcon#read 4, iclass 28, count 0 2006.281.07:49:20.33#ibcon#about to read 5, iclass 28, count 0 2006.281.07:49:20.33#ibcon#read 5, iclass 28, count 0 2006.281.07:49:20.33#ibcon#about to read 6, iclass 28, count 0 2006.281.07:49:20.33#ibcon#read 6, iclass 28, count 0 2006.281.07:49:20.33#ibcon#end of sib2, iclass 28, count 0 2006.281.07:49:20.33#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:49:20.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:49:20.33#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:49:20.33#ibcon#*before write, iclass 28, count 0 2006.281.07:49:20.33#ibcon#enter sib2, iclass 28, count 0 2006.281.07:49:20.33#ibcon#flushed, iclass 28, count 0 2006.281.07:49:20.35#ibcon#about to write, iclass 28, count 0 2006.281.07:49:20.35#ibcon#wrote, iclass 28, count 0 2006.281.07:49:20.35#ibcon#about to read 3, iclass 28, count 0 2006.281.07:49:20.39#ibcon#read 3, iclass 28, count 0 2006.281.07:49:20.39#ibcon#about to read 4, iclass 28, count 0 2006.281.07:49:20.39#ibcon#read 4, iclass 28, count 0 2006.281.07:49:20.39#ibcon#about to read 5, iclass 28, count 0 2006.281.07:49:20.39#ibcon#read 5, iclass 28, count 0 2006.281.07:49:20.39#ibcon#about to read 6, iclass 28, count 0 2006.281.07:49:20.39#ibcon#read 6, iclass 28, count 0 2006.281.07:49:20.39#ibcon#end of sib2, iclass 28, count 0 2006.281.07:49:20.39#ibcon#*after write, iclass 28, count 0 2006.281.07:49:20.39#ibcon#*before return 0, iclass 28, count 0 2006.281.07:49:20.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:20.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:20.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:49:20.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:49:20.39$vc4f8/va=3,6 2006.281.07:49:20.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:49:20.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:49:20.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:20.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:20.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:20.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:20.44#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:49:20.44#ibcon#first serial, iclass 30, count 2 2006.281.07:49:20.44#ibcon#enter sib2, iclass 30, count 2 2006.281.07:49:20.44#ibcon#flushed, iclass 30, count 2 2006.281.07:49:20.44#ibcon#about to write, iclass 30, count 2 2006.281.07:49:20.44#ibcon#wrote, iclass 30, count 2 2006.281.07:49:20.44#ibcon#about to read 3, iclass 30, count 2 2006.281.07:49:20.46#ibcon#read 3, iclass 30, count 2 2006.281.07:49:20.46#ibcon#about to read 4, iclass 30, count 2 2006.281.07:49:20.46#ibcon#read 4, iclass 30, count 2 2006.281.07:49:20.46#ibcon#about to read 5, iclass 30, count 2 2006.281.07:49:20.46#ibcon#read 5, iclass 30, count 2 2006.281.07:49:20.46#ibcon#about to read 6, iclass 30, count 2 2006.281.07:49:20.46#ibcon#read 6, iclass 30, count 2 2006.281.07:49:20.46#ibcon#end of sib2, iclass 30, count 2 2006.281.07:49:20.46#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:49:20.46#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:49:20.46#ibcon#[25=AT03-06\r\n] 2006.281.07:49:20.46#ibcon#*before write, iclass 30, count 2 2006.281.07:49:20.46#ibcon#enter sib2, iclass 30, count 2 2006.281.07:49:20.46#ibcon#flushed, iclass 30, count 2 2006.281.07:49:20.46#ibcon#about to write, iclass 30, count 2 2006.281.07:49:20.46#ibcon#wrote, iclass 30, count 2 2006.281.07:49:20.46#ibcon#about to read 3, iclass 30, count 2 2006.281.07:49:20.49#ibcon#read 3, iclass 30, count 2 2006.281.07:49:20.49#ibcon#about to read 4, iclass 30, count 2 2006.281.07:49:20.49#ibcon#read 4, iclass 30, count 2 2006.281.07:49:20.49#ibcon#about to read 5, iclass 30, count 2 2006.281.07:49:20.49#ibcon#read 5, iclass 30, count 2 2006.281.07:49:20.49#ibcon#about to read 6, iclass 30, count 2 2006.281.07:49:20.49#ibcon#read 6, iclass 30, count 2 2006.281.07:49:20.49#ibcon#end of sib2, iclass 30, count 2 2006.281.07:49:20.49#ibcon#*after write, iclass 30, count 2 2006.281.07:49:20.49#ibcon#*before return 0, iclass 30, count 2 2006.281.07:49:20.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:20.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:20.49#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:49:20.49#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:20.49#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:20.61#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:20.61#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:20.61#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:49:20.61#ibcon#first serial, iclass 30, count 0 2006.281.07:49:20.61#ibcon#enter sib2, iclass 30, count 0 2006.281.07:49:20.61#ibcon#flushed, iclass 30, count 0 2006.281.07:49:20.61#ibcon#about to write, iclass 30, count 0 2006.281.07:49:20.61#ibcon#wrote, iclass 30, count 0 2006.281.07:49:20.61#ibcon#about to read 3, iclass 30, count 0 2006.281.07:49:20.63#ibcon#read 3, iclass 30, count 0 2006.281.07:49:20.63#ibcon#about to read 4, iclass 30, count 0 2006.281.07:49:20.63#ibcon#read 4, iclass 30, count 0 2006.281.07:49:20.63#ibcon#about to read 5, iclass 30, count 0 2006.281.07:49:20.63#ibcon#read 5, iclass 30, count 0 2006.281.07:49:20.63#ibcon#about to read 6, iclass 30, count 0 2006.281.07:49:20.63#ibcon#read 6, iclass 30, count 0 2006.281.07:49:20.63#ibcon#end of sib2, iclass 30, count 0 2006.281.07:49:20.63#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:49:20.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:49:20.63#ibcon#[25=USB\r\n] 2006.281.07:49:20.63#ibcon#*before write, iclass 30, count 0 2006.281.07:49:20.63#ibcon#enter sib2, iclass 30, count 0 2006.281.07:49:20.63#ibcon#flushed, iclass 30, count 0 2006.281.07:49:20.63#ibcon#about to write, iclass 30, count 0 2006.281.07:49:20.63#ibcon#wrote, iclass 30, count 0 2006.281.07:49:20.63#ibcon#about to read 3, iclass 30, count 0 2006.281.07:49:20.63#abcon#<5=/13 2.2 9.5 20.92 511001.3\r\n> 2006.281.07:49:20.65#abcon#{5=INTERFACE CLEAR} 2006.281.07:49:20.66#ibcon#read 3, iclass 30, count 0 2006.281.07:49:20.66#ibcon#about to read 4, iclass 30, count 0 2006.281.07:49:20.66#ibcon#read 4, iclass 30, count 0 2006.281.07:49:20.66#ibcon#about to read 5, iclass 30, count 0 2006.281.07:49:20.66#ibcon#read 5, iclass 30, count 0 2006.281.07:49:20.66#ibcon#about to read 6, iclass 30, count 0 2006.281.07:49:20.66#ibcon#read 6, iclass 30, count 0 2006.281.07:49:20.66#ibcon#end of sib2, iclass 30, count 0 2006.281.07:49:20.66#ibcon#*after write, iclass 30, count 0 2006.281.07:49:20.66#ibcon#*before return 0, iclass 30, count 0 2006.281.07:49:20.66#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:20.66#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:20.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:49:20.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:49:20.66$vc4f8/valo=4,832.99 2006.281.07:49:20.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:49:20.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:49:20.66#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:20.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:49:20.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:49:20.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:49:20.66#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:49:20.66#ibcon#first serial, iclass 35, count 0 2006.281.07:49:20.66#ibcon#enter sib2, iclass 35, count 0 2006.281.07:49:20.66#ibcon#flushed, iclass 35, count 0 2006.281.07:49:20.66#ibcon#about to write, iclass 35, count 0 2006.281.07:49:20.66#ibcon#wrote, iclass 35, count 0 2006.281.07:49:20.66#ibcon#about to read 3, iclass 35, count 0 2006.281.07:49:20.68#ibcon#read 3, iclass 35, count 0 2006.281.07:49:20.68#ibcon#about to read 4, iclass 35, count 0 2006.281.07:49:20.68#ibcon#read 4, iclass 35, count 0 2006.281.07:49:20.68#ibcon#about to read 5, iclass 35, count 0 2006.281.07:49:20.68#ibcon#read 5, iclass 35, count 0 2006.281.07:49:20.68#ibcon#about to read 6, iclass 35, count 0 2006.281.07:49:20.68#ibcon#read 6, iclass 35, count 0 2006.281.07:49:20.68#ibcon#end of sib2, iclass 35, count 0 2006.281.07:49:20.68#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:49:20.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:49:20.68#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:49:20.68#ibcon#*before write, iclass 35, count 0 2006.281.07:49:20.68#ibcon#enter sib2, iclass 35, count 0 2006.281.07:49:20.68#ibcon#flushed, iclass 35, count 0 2006.281.07:49:20.68#ibcon#about to write, iclass 35, count 0 2006.281.07:49:20.68#ibcon#wrote, iclass 35, count 0 2006.281.07:49:20.68#ibcon#about to read 3, iclass 35, count 0 2006.281.07:49:20.71#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:49:20.73#ibcon#read 3, iclass 35, count 0 2006.281.07:49:20.73#ibcon#about to read 4, iclass 35, count 0 2006.281.07:49:20.73#ibcon#read 4, iclass 35, count 0 2006.281.07:49:20.73#ibcon#about to read 5, iclass 35, count 0 2006.281.07:49:20.73#ibcon#read 5, iclass 35, count 0 2006.281.07:49:20.73#ibcon#about to read 6, iclass 35, count 0 2006.281.07:49:20.73#ibcon#read 6, iclass 35, count 0 2006.281.07:49:20.73#ibcon#end of sib2, iclass 35, count 0 2006.281.07:49:20.73#ibcon#*after write, iclass 35, count 0 2006.281.07:49:20.73#ibcon#*before return 0, iclass 35, count 0 2006.281.07:49:20.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:49:20.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:49:20.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:49:20.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:49:20.73$vc4f8/va=4,6 2006.281.07:49:20.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:49:20.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:49:20.73#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:20.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:20.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:20.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:20.77#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:49:20.77#ibcon#first serial, iclass 38, count 2 2006.281.07:49:20.77#ibcon#enter sib2, iclass 38, count 2 2006.281.07:49:20.77#ibcon#flushed, iclass 38, count 2 2006.281.07:49:20.77#ibcon#about to write, iclass 38, count 2 2006.281.07:49:20.77#ibcon#wrote, iclass 38, count 2 2006.281.07:49:20.77#ibcon#about to read 3, iclass 38, count 2 2006.281.07:49:20.79#ibcon#read 3, iclass 38, count 2 2006.281.07:49:20.79#ibcon#about to read 4, iclass 38, count 2 2006.281.07:49:20.79#ibcon#read 4, iclass 38, count 2 2006.281.07:49:20.79#ibcon#about to read 5, iclass 38, count 2 2006.281.07:49:20.79#ibcon#read 5, iclass 38, count 2 2006.281.07:49:20.79#ibcon#about to read 6, iclass 38, count 2 2006.281.07:49:20.79#ibcon#read 6, iclass 38, count 2 2006.281.07:49:20.79#ibcon#end of sib2, iclass 38, count 2 2006.281.07:49:20.79#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:49:20.79#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:49:20.79#ibcon#[25=AT04-06\r\n] 2006.281.07:49:20.79#ibcon#*before write, iclass 38, count 2 2006.281.07:49:20.79#ibcon#enter sib2, iclass 38, count 2 2006.281.07:49:20.79#ibcon#flushed, iclass 38, count 2 2006.281.07:49:20.79#ibcon#about to write, iclass 38, count 2 2006.281.07:49:20.79#ibcon#wrote, iclass 38, count 2 2006.281.07:49:20.79#ibcon#about to read 3, iclass 38, count 2 2006.281.07:49:20.82#ibcon#read 3, iclass 38, count 2 2006.281.07:49:20.82#ibcon#about to read 4, iclass 38, count 2 2006.281.07:49:20.82#ibcon#read 4, iclass 38, count 2 2006.281.07:49:20.82#ibcon#about to read 5, iclass 38, count 2 2006.281.07:49:20.82#ibcon#read 5, iclass 38, count 2 2006.281.07:49:20.82#ibcon#about to read 6, iclass 38, count 2 2006.281.07:49:20.82#ibcon#read 6, iclass 38, count 2 2006.281.07:49:20.82#ibcon#end of sib2, iclass 38, count 2 2006.281.07:49:20.82#ibcon#*after write, iclass 38, count 2 2006.281.07:49:20.82#ibcon#*before return 0, iclass 38, count 2 2006.281.07:49:20.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:20.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:20.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:49:20.82#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:20.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:20.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:20.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:20.94#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:49:20.94#ibcon#first serial, iclass 38, count 0 2006.281.07:49:20.94#ibcon#enter sib2, iclass 38, count 0 2006.281.07:49:20.94#ibcon#flushed, iclass 38, count 0 2006.281.07:49:20.94#ibcon#about to write, iclass 38, count 0 2006.281.07:49:20.94#ibcon#wrote, iclass 38, count 0 2006.281.07:49:20.94#ibcon#about to read 3, iclass 38, count 0 2006.281.07:49:20.96#ibcon#read 3, iclass 38, count 0 2006.281.07:49:20.96#ibcon#about to read 4, iclass 38, count 0 2006.281.07:49:20.96#ibcon#read 4, iclass 38, count 0 2006.281.07:49:20.96#ibcon#about to read 5, iclass 38, count 0 2006.281.07:49:20.96#ibcon#read 5, iclass 38, count 0 2006.281.07:49:20.96#ibcon#about to read 6, iclass 38, count 0 2006.281.07:49:20.96#ibcon#read 6, iclass 38, count 0 2006.281.07:49:20.96#ibcon#end of sib2, iclass 38, count 0 2006.281.07:49:20.96#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:49:20.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:49:20.96#ibcon#[25=USB\r\n] 2006.281.07:49:20.96#ibcon#*before write, iclass 38, count 0 2006.281.07:49:20.96#ibcon#enter sib2, iclass 38, count 0 2006.281.07:49:20.96#ibcon#flushed, iclass 38, count 0 2006.281.07:49:20.96#ibcon#about to write, iclass 38, count 0 2006.281.07:49:20.96#ibcon#wrote, iclass 38, count 0 2006.281.07:49:20.96#ibcon#about to read 3, iclass 38, count 0 2006.281.07:49:20.99#ibcon#read 3, iclass 38, count 0 2006.281.07:49:20.99#ibcon#about to read 4, iclass 38, count 0 2006.281.07:49:20.99#ibcon#read 4, iclass 38, count 0 2006.281.07:49:20.99#ibcon#about to read 5, iclass 38, count 0 2006.281.07:49:20.99#ibcon#read 5, iclass 38, count 0 2006.281.07:49:20.99#ibcon#about to read 6, iclass 38, count 0 2006.281.07:49:20.99#ibcon#read 6, iclass 38, count 0 2006.281.07:49:20.99#ibcon#end of sib2, iclass 38, count 0 2006.281.07:49:20.99#ibcon#*after write, iclass 38, count 0 2006.281.07:49:20.99#ibcon#*before return 0, iclass 38, count 0 2006.281.07:49:20.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:20.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:20.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:49:20.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:49:20.99$vc4f8/valo=5,652.99 2006.281.07:49:20.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:49:20.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:49:20.99#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:20.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:20.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:20.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:20.99#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:49:20.99#ibcon#first serial, iclass 40, count 0 2006.281.07:49:20.99#ibcon#enter sib2, iclass 40, count 0 2006.281.07:49:20.99#ibcon#flushed, iclass 40, count 0 2006.281.07:49:20.99#ibcon#about to write, iclass 40, count 0 2006.281.07:49:20.99#ibcon#wrote, iclass 40, count 0 2006.281.07:49:20.99#ibcon#about to read 3, iclass 40, count 0 2006.281.07:49:21.01#ibcon#read 3, iclass 40, count 0 2006.281.07:49:21.01#ibcon#about to read 4, iclass 40, count 0 2006.281.07:49:21.01#ibcon#read 4, iclass 40, count 0 2006.281.07:49:21.01#ibcon#about to read 5, iclass 40, count 0 2006.281.07:49:21.01#ibcon#read 5, iclass 40, count 0 2006.281.07:49:21.01#ibcon#about to read 6, iclass 40, count 0 2006.281.07:49:21.01#ibcon#read 6, iclass 40, count 0 2006.281.07:49:21.01#ibcon#end of sib2, iclass 40, count 0 2006.281.07:49:21.01#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:49:21.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:49:21.01#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:49:21.01#ibcon#*before write, iclass 40, count 0 2006.281.07:49:21.01#ibcon#enter sib2, iclass 40, count 0 2006.281.07:49:21.01#ibcon#flushed, iclass 40, count 0 2006.281.07:49:21.01#ibcon#about to write, iclass 40, count 0 2006.281.07:49:21.01#ibcon#wrote, iclass 40, count 0 2006.281.07:49:21.01#ibcon#about to read 3, iclass 40, count 0 2006.281.07:49:21.05#ibcon#read 3, iclass 40, count 0 2006.281.07:49:21.05#ibcon#about to read 4, iclass 40, count 0 2006.281.07:49:21.05#ibcon#read 4, iclass 40, count 0 2006.281.07:49:21.05#ibcon#about to read 5, iclass 40, count 0 2006.281.07:49:21.05#ibcon#read 5, iclass 40, count 0 2006.281.07:49:21.05#ibcon#about to read 6, iclass 40, count 0 2006.281.07:49:21.05#ibcon#read 6, iclass 40, count 0 2006.281.07:49:21.05#ibcon#end of sib2, iclass 40, count 0 2006.281.07:49:21.05#ibcon#*after write, iclass 40, count 0 2006.281.07:49:21.05#ibcon#*before return 0, iclass 40, count 0 2006.281.07:49:21.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:21.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:21.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:49:21.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:49:21.05$vc4f8/va=5,7 2006.281.07:49:21.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:49:21.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:49:21.05#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:21.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:21.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:21.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:21.12#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:49:21.12#ibcon#first serial, iclass 4, count 2 2006.281.07:49:21.12#ibcon#enter sib2, iclass 4, count 2 2006.281.07:49:21.12#ibcon#flushed, iclass 4, count 2 2006.281.07:49:21.12#ibcon#about to write, iclass 4, count 2 2006.281.07:49:21.12#ibcon#wrote, iclass 4, count 2 2006.281.07:49:21.12#ibcon#about to read 3, iclass 4, count 2 2006.281.07:49:21.13#ibcon#read 3, iclass 4, count 2 2006.281.07:49:21.13#ibcon#about to read 4, iclass 4, count 2 2006.281.07:49:21.13#ibcon#read 4, iclass 4, count 2 2006.281.07:49:21.13#ibcon#about to read 5, iclass 4, count 2 2006.281.07:49:21.13#ibcon#read 5, iclass 4, count 2 2006.281.07:49:21.13#ibcon#about to read 6, iclass 4, count 2 2006.281.07:49:21.13#ibcon#read 6, iclass 4, count 2 2006.281.07:49:21.13#ibcon#end of sib2, iclass 4, count 2 2006.281.07:49:21.13#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:49:21.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:49:21.13#ibcon#[25=AT05-07\r\n] 2006.281.07:49:21.13#ibcon#*before write, iclass 4, count 2 2006.281.07:49:21.13#ibcon#enter sib2, iclass 4, count 2 2006.281.07:49:21.13#ibcon#flushed, iclass 4, count 2 2006.281.07:49:21.13#ibcon#about to write, iclass 4, count 2 2006.281.07:49:21.13#ibcon#wrote, iclass 4, count 2 2006.281.07:49:21.13#ibcon#about to read 3, iclass 4, count 2 2006.281.07:49:21.16#ibcon#read 3, iclass 4, count 2 2006.281.07:49:21.16#ibcon#about to read 4, iclass 4, count 2 2006.281.07:49:21.16#ibcon#read 4, iclass 4, count 2 2006.281.07:49:21.16#ibcon#about to read 5, iclass 4, count 2 2006.281.07:49:21.16#ibcon#read 5, iclass 4, count 2 2006.281.07:49:21.16#ibcon#about to read 6, iclass 4, count 2 2006.281.07:49:21.16#ibcon#read 6, iclass 4, count 2 2006.281.07:49:21.16#ibcon#end of sib2, iclass 4, count 2 2006.281.07:49:21.16#ibcon#*after write, iclass 4, count 2 2006.281.07:49:21.16#ibcon#*before return 0, iclass 4, count 2 2006.281.07:49:21.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:21.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:21.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:49:21.16#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:21.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:21.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:21.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:21.28#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:49:21.28#ibcon#first serial, iclass 4, count 0 2006.281.07:49:21.28#ibcon#enter sib2, iclass 4, count 0 2006.281.07:49:21.28#ibcon#flushed, iclass 4, count 0 2006.281.07:49:21.28#ibcon#about to write, iclass 4, count 0 2006.281.07:49:21.28#ibcon#wrote, iclass 4, count 0 2006.281.07:49:21.28#ibcon#about to read 3, iclass 4, count 0 2006.281.07:49:21.30#ibcon#read 3, iclass 4, count 0 2006.281.07:49:21.30#ibcon#about to read 4, iclass 4, count 0 2006.281.07:49:21.30#ibcon#read 4, iclass 4, count 0 2006.281.07:49:21.30#ibcon#about to read 5, iclass 4, count 0 2006.281.07:49:21.30#ibcon#read 5, iclass 4, count 0 2006.281.07:49:21.30#ibcon#about to read 6, iclass 4, count 0 2006.281.07:49:21.30#ibcon#read 6, iclass 4, count 0 2006.281.07:49:21.30#ibcon#end of sib2, iclass 4, count 0 2006.281.07:49:21.30#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:49:21.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:49:21.30#ibcon#[25=USB\r\n] 2006.281.07:49:21.30#ibcon#*before write, iclass 4, count 0 2006.281.07:49:21.30#ibcon#enter sib2, iclass 4, count 0 2006.281.07:49:21.30#ibcon#flushed, iclass 4, count 0 2006.281.07:49:21.30#ibcon#about to write, iclass 4, count 0 2006.281.07:49:21.30#ibcon#wrote, iclass 4, count 0 2006.281.07:49:21.30#ibcon#about to read 3, iclass 4, count 0 2006.281.07:49:21.33#ibcon#read 3, iclass 4, count 0 2006.281.07:49:21.33#ibcon#about to read 4, iclass 4, count 0 2006.281.07:49:21.33#ibcon#read 4, iclass 4, count 0 2006.281.07:49:21.33#ibcon#about to read 5, iclass 4, count 0 2006.281.07:49:21.33#ibcon#read 5, iclass 4, count 0 2006.281.07:49:21.33#ibcon#about to read 6, iclass 4, count 0 2006.281.07:49:21.33#ibcon#read 6, iclass 4, count 0 2006.281.07:49:21.33#ibcon#end of sib2, iclass 4, count 0 2006.281.07:49:21.33#ibcon#*after write, iclass 4, count 0 2006.281.07:49:21.33#ibcon#*before return 0, iclass 4, count 0 2006.281.07:49:21.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:21.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:21.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:49:21.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:49:21.33$vc4f8/valo=6,772.99 2006.281.07:49:21.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:49:21.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:49:21.33#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:21.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:21.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:21.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:21.33#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:49:21.33#ibcon#first serial, iclass 6, count 0 2006.281.07:49:21.33#ibcon#enter sib2, iclass 6, count 0 2006.281.07:49:21.33#ibcon#flushed, iclass 6, count 0 2006.281.07:49:21.33#ibcon#about to write, iclass 6, count 0 2006.281.07:49:21.33#ibcon#wrote, iclass 6, count 0 2006.281.07:49:21.33#ibcon#about to read 3, iclass 6, count 0 2006.281.07:49:21.35#ibcon#read 3, iclass 6, count 0 2006.281.07:49:21.35#ibcon#about to read 4, iclass 6, count 0 2006.281.07:49:21.35#ibcon#read 4, iclass 6, count 0 2006.281.07:49:21.35#ibcon#about to read 5, iclass 6, count 0 2006.281.07:49:21.35#ibcon#read 5, iclass 6, count 0 2006.281.07:49:21.35#ibcon#about to read 6, iclass 6, count 0 2006.281.07:49:21.35#ibcon#read 6, iclass 6, count 0 2006.281.07:49:21.35#ibcon#end of sib2, iclass 6, count 0 2006.281.07:49:21.35#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:49:21.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:49:21.35#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:49:21.35#ibcon#*before write, iclass 6, count 0 2006.281.07:49:21.35#ibcon#enter sib2, iclass 6, count 0 2006.281.07:49:21.35#ibcon#flushed, iclass 6, count 0 2006.281.07:49:21.35#ibcon#about to write, iclass 6, count 0 2006.281.07:49:21.35#ibcon#wrote, iclass 6, count 0 2006.281.07:49:21.35#ibcon#about to read 3, iclass 6, count 0 2006.281.07:49:21.39#ibcon#read 3, iclass 6, count 0 2006.281.07:49:21.39#ibcon#about to read 4, iclass 6, count 0 2006.281.07:49:21.39#ibcon#read 4, iclass 6, count 0 2006.281.07:49:21.39#ibcon#about to read 5, iclass 6, count 0 2006.281.07:49:21.39#ibcon#read 5, iclass 6, count 0 2006.281.07:49:21.39#ibcon#about to read 6, iclass 6, count 0 2006.281.07:49:21.39#ibcon#read 6, iclass 6, count 0 2006.281.07:49:21.39#ibcon#end of sib2, iclass 6, count 0 2006.281.07:49:21.39#ibcon#*after write, iclass 6, count 0 2006.281.07:49:21.39#ibcon#*before return 0, iclass 6, count 0 2006.281.07:49:21.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:21.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:21.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:49:21.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:49:21.39$vc4f8/va=6,6 2006.281.07:49:21.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.07:49:21.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.07:49:21.39#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:21.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:21.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:21.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:21.45#ibcon#enter wrdev, iclass 10, count 2 2006.281.07:49:21.45#ibcon#first serial, iclass 10, count 2 2006.281.07:49:21.45#ibcon#enter sib2, iclass 10, count 2 2006.281.07:49:21.45#ibcon#flushed, iclass 10, count 2 2006.281.07:49:21.45#ibcon#about to write, iclass 10, count 2 2006.281.07:49:21.45#ibcon#wrote, iclass 10, count 2 2006.281.07:49:21.45#ibcon#about to read 3, iclass 10, count 2 2006.281.07:49:21.47#ibcon#read 3, iclass 10, count 2 2006.281.07:49:21.47#ibcon#about to read 4, iclass 10, count 2 2006.281.07:49:21.47#ibcon#read 4, iclass 10, count 2 2006.281.07:49:21.47#ibcon#about to read 5, iclass 10, count 2 2006.281.07:49:21.47#ibcon#read 5, iclass 10, count 2 2006.281.07:49:21.47#ibcon#about to read 6, iclass 10, count 2 2006.281.07:49:21.47#ibcon#read 6, iclass 10, count 2 2006.281.07:49:21.47#ibcon#end of sib2, iclass 10, count 2 2006.281.07:49:21.47#ibcon#*mode == 0, iclass 10, count 2 2006.281.07:49:21.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.07:49:21.47#ibcon#[25=AT06-06\r\n] 2006.281.07:49:21.47#ibcon#*before write, iclass 10, count 2 2006.281.07:49:21.47#ibcon#enter sib2, iclass 10, count 2 2006.281.07:49:21.47#ibcon#flushed, iclass 10, count 2 2006.281.07:49:21.47#ibcon#about to write, iclass 10, count 2 2006.281.07:49:21.47#ibcon#wrote, iclass 10, count 2 2006.281.07:49:21.47#ibcon#about to read 3, iclass 10, count 2 2006.281.07:49:21.50#ibcon#read 3, iclass 10, count 2 2006.281.07:49:21.50#ibcon#about to read 4, iclass 10, count 2 2006.281.07:49:21.50#ibcon#read 4, iclass 10, count 2 2006.281.07:49:21.50#ibcon#about to read 5, iclass 10, count 2 2006.281.07:49:21.50#ibcon#read 5, iclass 10, count 2 2006.281.07:49:21.50#ibcon#about to read 6, iclass 10, count 2 2006.281.07:49:21.50#ibcon#read 6, iclass 10, count 2 2006.281.07:49:21.50#ibcon#end of sib2, iclass 10, count 2 2006.281.07:49:21.50#ibcon#*after write, iclass 10, count 2 2006.281.07:49:21.50#ibcon#*before return 0, iclass 10, count 2 2006.281.07:49:21.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:21.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:21.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.07:49:21.50#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:21.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:49:21.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:49:21.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:49:21.62#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:49:21.62#ibcon#first serial, iclass 10, count 0 2006.281.07:49:21.62#ibcon#enter sib2, iclass 10, count 0 2006.281.07:49:21.62#ibcon#flushed, iclass 10, count 0 2006.281.07:49:21.62#ibcon#about to write, iclass 10, count 0 2006.281.07:49:21.62#ibcon#wrote, iclass 10, count 0 2006.281.07:49:21.62#ibcon#about to read 3, iclass 10, count 0 2006.281.07:49:21.64#ibcon#read 3, iclass 10, count 0 2006.281.07:49:21.64#ibcon#about to read 4, iclass 10, count 0 2006.281.07:49:21.64#ibcon#read 4, iclass 10, count 0 2006.281.07:49:21.64#ibcon#about to read 5, iclass 10, count 0 2006.281.07:49:21.64#ibcon#read 5, iclass 10, count 0 2006.281.07:49:21.64#ibcon#about to read 6, iclass 10, count 0 2006.281.07:49:21.64#ibcon#read 6, iclass 10, count 0 2006.281.07:49:21.64#ibcon#end of sib2, iclass 10, count 0 2006.281.07:49:21.64#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:49:21.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:49:21.64#ibcon#[25=USB\r\n] 2006.281.07:49:21.64#ibcon#*before write, iclass 10, count 0 2006.281.07:49:21.64#ibcon#enter sib2, iclass 10, count 0 2006.281.07:49:21.64#ibcon#flushed, iclass 10, count 0 2006.281.07:49:21.64#ibcon#about to write, iclass 10, count 0 2006.281.07:49:21.64#ibcon#wrote, iclass 10, count 0 2006.281.07:49:21.64#ibcon#about to read 3, iclass 10, count 0 2006.281.07:49:21.67#ibcon#read 3, iclass 10, count 0 2006.281.07:49:21.67#ibcon#about to read 4, iclass 10, count 0 2006.281.07:49:21.67#ibcon#read 4, iclass 10, count 0 2006.281.07:49:21.67#ibcon#about to read 5, iclass 10, count 0 2006.281.07:49:21.67#ibcon#read 5, iclass 10, count 0 2006.281.07:49:21.67#ibcon#about to read 6, iclass 10, count 0 2006.281.07:49:21.67#ibcon#read 6, iclass 10, count 0 2006.281.07:49:21.67#ibcon#end of sib2, iclass 10, count 0 2006.281.07:49:21.67#ibcon#*after write, iclass 10, count 0 2006.281.07:49:21.67#ibcon#*before return 0, iclass 10, count 0 2006.281.07:49:21.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:49:21.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:49:21.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:49:21.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:49:21.67$vc4f8/valo=7,832.99 2006.281.07:49:21.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.07:49:21.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.07:49:21.67#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:21.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:49:21.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:49:21.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:49:21.67#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:49:21.67#ibcon#first serial, iclass 12, count 0 2006.281.07:49:21.67#ibcon#enter sib2, iclass 12, count 0 2006.281.07:49:21.67#ibcon#flushed, iclass 12, count 0 2006.281.07:49:21.67#ibcon#about to write, iclass 12, count 0 2006.281.07:49:21.67#ibcon#wrote, iclass 12, count 0 2006.281.07:49:21.67#ibcon#about to read 3, iclass 12, count 0 2006.281.07:49:21.69#ibcon#read 3, iclass 12, count 0 2006.281.07:49:21.69#ibcon#about to read 4, iclass 12, count 0 2006.281.07:49:21.69#ibcon#read 4, iclass 12, count 0 2006.281.07:49:21.69#ibcon#about to read 5, iclass 12, count 0 2006.281.07:49:21.69#ibcon#read 5, iclass 12, count 0 2006.281.07:49:21.69#ibcon#about to read 6, iclass 12, count 0 2006.281.07:49:21.69#ibcon#read 6, iclass 12, count 0 2006.281.07:49:21.69#ibcon#end of sib2, iclass 12, count 0 2006.281.07:49:21.69#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:49:21.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:49:21.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:49:21.69#ibcon#*before write, iclass 12, count 0 2006.281.07:49:21.69#ibcon#enter sib2, iclass 12, count 0 2006.281.07:49:21.69#ibcon#flushed, iclass 12, count 0 2006.281.07:49:21.69#ibcon#about to write, iclass 12, count 0 2006.281.07:49:21.69#ibcon#wrote, iclass 12, count 0 2006.281.07:49:21.69#ibcon#about to read 3, iclass 12, count 0 2006.281.07:49:21.74#ibcon#read 3, iclass 12, count 0 2006.281.07:49:21.74#ibcon#about to read 4, iclass 12, count 0 2006.281.07:49:21.74#ibcon#read 4, iclass 12, count 0 2006.281.07:49:21.74#ibcon#about to read 5, iclass 12, count 0 2006.281.07:49:21.74#ibcon#read 5, iclass 12, count 0 2006.281.07:49:21.74#ibcon#about to read 6, iclass 12, count 0 2006.281.07:49:21.74#ibcon#read 6, iclass 12, count 0 2006.281.07:49:21.74#ibcon#end of sib2, iclass 12, count 0 2006.281.07:49:21.74#ibcon#*after write, iclass 12, count 0 2006.281.07:49:21.74#ibcon#*before return 0, iclass 12, count 0 2006.281.07:49:21.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:49:21.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:49:21.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:49:21.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:49:21.74$vc4f8/va=7,6 2006.281.07:49:21.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.07:49:21.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.07:49:21.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:21.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:49:21.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:49:21.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:49:21.78#ibcon#enter wrdev, iclass 14, count 2 2006.281.07:49:21.78#ibcon#first serial, iclass 14, count 2 2006.281.07:49:21.78#ibcon#enter sib2, iclass 14, count 2 2006.281.07:49:21.78#ibcon#flushed, iclass 14, count 2 2006.281.07:49:21.78#ibcon#about to write, iclass 14, count 2 2006.281.07:49:21.78#ibcon#wrote, iclass 14, count 2 2006.281.07:49:21.78#ibcon#about to read 3, iclass 14, count 2 2006.281.07:49:21.81#ibcon#read 3, iclass 14, count 2 2006.281.07:49:21.81#ibcon#about to read 4, iclass 14, count 2 2006.281.07:49:21.81#ibcon#read 4, iclass 14, count 2 2006.281.07:49:21.81#ibcon#about to read 5, iclass 14, count 2 2006.281.07:49:21.81#ibcon#read 5, iclass 14, count 2 2006.281.07:49:21.81#ibcon#about to read 6, iclass 14, count 2 2006.281.07:49:21.81#ibcon#read 6, iclass 14, count 2 2006.281.07:49:21.81#ibcon#end of sib2, iclass 14, count 2 2006.281.07:49:21.81#ibcon#*mode == 0, iclass 14, count 2 2006.281.07:49:21.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.07:49:21.81#ibcon#[25=AT07-06\r\n] 2006.281.07:49:21.81#ibcon#*before write, iclass 14, count 2 2006.281.07:49:21.81#ibcon#enter sib2, iclass 14, count 2 2006.281.07:49:21.81#ibcon#flushed, iclass 14, count 2 2006.281.07:49:21.81#ibcon#about to write, iclass 14, count 2 2006.281.07:49:21.81#ibcon#wrote, iclass 14, count 2 2006.281.07:49:21.81#ibcon#about to read 3, iclass 14, count 2 2006.281.07:49:21.84#ibcon#read 3, iclass 14, count 2 2006.281.07:49:21.84#ibcon#about to read 4, iclass 14, count 2 2006.281.07:49:21.84#ibcon#read 4, iclass 14, count 2 2006.281.07:49:21.84#ibcon#about to read 5, iclass 14, count 2 2006.281.07:49:21.84#ibcon#read 5, iclass 14, count 2 2006.281.07:49:21.84#ibcon#about to read 6, iclass 14, count 2 2006.281.07:49:21.84#ibcon#read 6, iclass 14, count 2 2006.281.07:49:21.84#ibcon#end of sib2, iclass 14, count 2 2006.281.07:49:21.84#ibcon#*after write, iclass 14, count 2 2006.281.07:49:21.84#ibcon#*before return 0, iclass 14, count 2 2006.281.07:49:21.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:49:21.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.07:49:21.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.07:49:21.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:21.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:49:21.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:49:21.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:49:21.96#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:49:21.96#ibcon#first serial, iclass 14, count 0 2006.281.07:49:21.96#ibcon#enter sib2, iclass 14, count 0 2006.281.07:49:21.96#ibcon#flushed, iclass 14, count 0 2006.281.07:49:21.96#ibcon#about to write, iclass 14, count 0 2006.281.07:49:21.96#ibcon#wrote, iclass 14, count 0 2006.281.07:49:21.96#ibcon#about to read 3, iclass 14, count 0 2006.281.07:49:21.98#ibcon#read 3, iclass 14, count 0 2006.281.07:49:21.98#ibcon#about to read 4, iclass 14, count 0 2006.281.07:49:21.98#ibcon#read 4, iclass 14, count 0 2006.281.07:49:21.98#ibcon#about to read 5, iclass 14, count 0 2006.281.07:49:21.98#ibcon#read 5, iclass 14, count 0 2006.281.07:49:21.98#ibcon#about to read 6, iclass 14, count 0 2006.281.07:49:21.98#ibcon#read 6, iclass 14, count 0 2006.281.07:49:21.98#ibcon#end of sib2, iclass 14, count 0 2006.281.07:49:21.98#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:49:21.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:49:21.98#ibcon#[25=USB\r\n] 2006.281.07:49:21.98#ibcon#*before write, iclass 14, count 0 2006.281.07:49:21.98#ibcon#enter sib2, iclass 14, count 0 2006.281.07:49:21.98#ibcon#flushed, iclass 14, count 0 2006.281.07:49:21.98#ibcon#about to write, iclass 14, count 0 2006.281.07:49:21.98#ibcon#wrote, iclass 14, count 0 2006.281.07:49:21.98#ibcon#about to read 3, iclass 14, count 0 2006.281.07:49:22.01#ibcon#read 3, iclass 14, count 0 2006.281.07:49:22.01#ibcon#about to read 4, iclass 14, count 0 2006.281.07:49:22.01#ibcon#read 4, iclass 14, count 0 2006.281.07:49:22.01#ibcon#about to read 5, iclass 14, count 0 2006.281.07:49:22.01#ibcon#read 5, iclass 14, count 0 2006.281.07:49:22.01#ibcon#about to read 6, iclass 14, count 0 2006.281.07:49:22.01#ibcon#read 6, iclass 14, count 0 2006.281.07:49:22.01#ibcon#end of sib2, iclass 14, count 0 2006.281.07:49:22.01#ibcon#*after write, iclass 14, count 0 2006.281.07:49:22.01#ibcon#*before return 0, iclass 14, count 0 2006.281.07:49:22.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:49:22.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.07:49:22.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:49:22.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:49:22.01$vc4f8/valo=8,852.99 2006.281.07:49:22.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:49:22.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:49:22.01#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:22.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:49:22.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:49:22.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:49:22.01#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:49:22.01#ibcon#first serial, iclass 16, count 0 2006.281.07:49:22.01#ibcon#enter sib2, iclass 16, count 0 2006.281.07:49:22.01#ibcon#flushed, iclass 16, count 0 2006.281.07:49:22.01#ibcon#about to write, iclass 16, count 0 2006.281.07:49:22.01#ibcon#wrote, iclass 16, count 0 2006.281.07:49:22.01#ibcon#about to read 3, iclass 16, count 0 2006.281.07:49:22.03#ibcon#read 3, iclass 16, count 0 2006.281.07:49:22.03#ibcon#about to read 4, iclass 16, count 0 2006.281.07:49:22.03#ibcon#read 4, iclass 16, count 0 2006.281.07:49:22.03#ibcon#about to read 5, iclass 16, count 0 2006.281.07:49:22.03#ibcon#read 5, iclass 16, count 0 2006.281.07:49:22.03#ibcon#about to read 6, iclass 16, count 0 2006.281.07:49:22.03#ibcon#read 6, iclass 16, count 0 2006.281.07:49:22.03#ibcon#end of sib2, iclass 16, count 0 2006.281.07:49:22.03#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:49:22.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:49:22.05#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:49:22.05#ibcon#*before write, iclass 16, count 0 2006.281.07:49:22.05#ibcon#enter sib2, iclass 16, count 0 2006.281.07:49:22.05#ibcon#flushed, iclass 16, count 0 2006.281.07:49:22.05#ibcon#about to write, iclass 16, count 0 2006.281.07:49:22.05#ibcon#wrote, iclass 16, count 0 2006.281.07:49:22.05#ibcon#about to read 3, iclass 16, count 0 2006.281.07:49:22.09#ibcon#read 3, iclass 16, count 0 2006.281.07:49:22.09#ibcon#about to read 4, iclass 16, count 0 2006.281.07:49:22.09#ibcon#read 4, iclass 16, count 0 2006.281.07:49:22.09#ibcon#about to read 5, iclass 16, count 0 2006.281.07:49:22.09#ibcon#read 5, iclass 16, count 0 2006.281.07:49:22.09#ibcon#about to read 6, iclass 16, count 0 2006.281.07:49:22.09#ibcon#read 6, iclass 16, count 0 2006.281.07:49:22.09#ibcon#end of sib2, iclass 16, count 0 2006.281.07:49:22.09#ibcon#*after write, iclass 16, count 0 2006.281.07:49:22.09#ibcon#*before return 0, iclass 16, count 0 2006.281.07:49:22.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:49:22.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:49:22.09#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:49:22.09#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:49:22.09$vc4f8/va=8,6 2006.281.07:49:22.09#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.07:49:22.09#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.07:49:22.09#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:22.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:49:22.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:49:22.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:49:22.13#ibcon#enter wrdev, iclass 18, count 2 2006.281.07:49:22.13#ibcon#first serial, iclass 18, count 2 2006.281.07:49:22.13#ibcon#enter sib2, iclass 18, count 2 2006.281.07:49:22.13#ibcon#flushed, iclass 18, count 2 2006.281.07:49:22.13#ibcon#about to write, iclass 18, count 2 2006.281.07:49:22.13#ibcon#wrote, iclass 18, count 2 2006.281.07:49:22.13#ibcon#about to read 3, iclass 18, count 2 2006.281.07:49:22.15#ibcon#read 3, iclass 18, count 2 2006.281.07:49:22.15#ibcon#about to read 4, iclass 18, count 2 2006.281.07:49:22.15#ibcon#read 4, iclass 18, count 2 2006.281.07:49:22.15#ibcon#about to read 5, iclass 18, count 2 2006.281.07:49:22.15#ibcon#read 5, iclass 18, count 2 2006.281.07:49:22.15#ibcon#about to read 6, iclass 18, count 2 2006.281.07:49:22.15#ibcon#read 6, iclass 18, count 2 2006.281.07:49:22.15#ibcon#end of sib2, iclass 18, count 2 2006.281.07:49:22.15#ibcon#*mode == 0, iclass 18, count 2 2006.281.07:49:22.15#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.07:49:22.15#ibcon#[25=AT08-06\r\n] 2006.281.07:49:22.15#ibcon#*before write, iclass 18, count 2 2006.281.07:49:22.15#ibcon#enter sib2, iclass 18, count 2 2006.281.07:49:22.15#ibcon#flushed, iclass 18, count 2 2006.281.07:49:22.15#ibcon#about to write, iclass 18, count 2 2006.281.07:49:22.15#ibcon#wrote, iclass 18, count 2 2006.281.07:49:22.15#ibcon#about to read 3, iclass 18, count 2 2006.281.07:49:22.18#ibcon#read 3, iclass 18, count 2 2006.281.07:49:22.18#ibcon#about to read 4, iclass 18, count 2 2006.281.07:49:22.18#ibcon#read 4, iclass 18, count 2 2006.281.07:49:22.18#ibcon#about to read 5, iclass 18, count 2 2006.281.07:49:22.18#ibcon#read 5, iclass 18, count 2 2006.281.07:49:22.18#ibcon#about to read 6, iclass 18, count 2 2006.281.07:49:22.18#ibcon#read 6, iclass 18, count 2 2006.281.07:49:22.18#ibcon#end of sib2, iclass 18, count 2 2006.281.07:49:22.18#ibcon#*after write, iclass 18, count 2 2006.281.07:49:22.18#ibcon#*before return 0, iclass 18, count 2 2006.281.07:49:22.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:49:22.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.07:49:22.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.07:49:22.18#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:22.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:49:22.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:49:22.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:49:22.30#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:49:22.30#ibcon#first serial, iclass 18, count 0 2006.281.07:49:22.30#ibcon#enter sib2, iclass 18, count 0 2006.281.07:49:22.30#ibcon#flushed, iclass 18, count 0 2006.281.07:49:22.30#ibcon#about to write, iclass 18, count 0 2006.281.07:49:22.30#ibcon#wrote, iclass 18, count 0 2006.281.07:49:22.30#ibcon#about to read 3, iclass 18, count 0 2006.281.07:49:22.32#ibcon#read 3, iclass 18, count 0 2006.281.07:49:22.32#ibcon#about to read 4, iclass 18, count 0 2006.281.07:49:22.32#ibcon#read 4, iclass 18, count 0 2006.281.07:49:22.32#ibcon#about to read 5, iclass 18, count 0 2006.281.07:49:22.32#ibcon#read 5, iclass 18, count 0 2006.281.07:49:22.32#ibcon#about to read 6, iclass 18, count 0 2006.281.07:49:22.32#ibcon#read 6, iclass 18, count 0 2006.281.07:49:22.32#ibcon#end of sib2, iclass 18, count 0 2006.281.07:49:22.32#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:49:22.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:49:22.32#ibcon#[25=USB\r\n] 2006.281.07:49:22.32#ibcon#*before write, iclass 18, count 0 2006.281.07:49:22.32#ibcon#enter sib2, iclass 18, count 0 2006.281.07:49:22.32#ibcon#flushed, iclass 18, count 0 2006.281.07:49:22.32#ibcon#about to write, iclass 18, count 0 2006.281.07:49:22.32#ibcon#wrote, iclass 18, count 0 2006.281.07:49:22.32#ibcon#about to read 3, iclass 18, count 0 2006.281.07:49:22.35#ibcon#read 3, iclass 18, count 0 2006.281.07:49:22.35#ibcon#about to read 4, iclass 18, count 0 2006.281.07:49:22.35#ibcon#read 4, iclass 18, count 0 2006.281.07:49:22.35#ibcon#about to read 5, iclass 18, count 0 2006.281.07:49:22.35#ibcon#read 5, iclass 18, count 0 2006.281.07:49:22.35#ibcon#about to read 6, iclass 18, count 0 2006.281.07:49:22.35#ibcon#read 6, iclass 18, count 0 2006.281.07:49:22.35#ibcon#end of sib2, iclass 18, count 0 2006.281.07:49:22.35#ibcon#*after write, iclass 18, count 0 2006.281.07:49:22.35#ibcon#*before return 0, iclass 18, count 0 2006.281.07:49:22.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:49:22.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.07:49:22.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:49:22.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:49:22.35$vc4f8/vblo=1,632.99 2006.281.07:49:22.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:49:22.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:49:22.35#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:22.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:22.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:22.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:22.35#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:49:22.35#ibcon#first serial, iclass 20, count 0 2006.281.07:49:22.35#ibcon#enter sib2, iclass 20, count 0 2006.281.07:49:22.35#ibcon#flushed, iclass 20, count 0 2006.281.07:49:22.35#ibcon#about to write, iclass 20, count 0 2006.281.07:49:22.35#ibcon#wrote, iclass 20, count 0 2006.281.07:49:22.35#ibcon#about to read 3, iclass 20, count 0 2006.281.07:49:22.37#ibcon#read 3, iclass 20, count 0 2006.281.07:49:22.37#ibcon#about to read 4, iclass 20, count 0 2006.281.07:49:22.37#ibcon#read 4, iclass 20, count 0 2006.281.07:49:22.37#ibcon#about to read 5, iclass 20, count 0 2006.281.07:49:22.37#ibcon#read 5, iclass 20, count 0 2006.281.07:49:22.37#ibcon#about to read 6, iclass 20, count 0 2006.281.07:49:22.37#ibcon#read 6, iclass 20, count 0 2006.281.07:49:22.37#ibcon#end of sib2, iclass 20, count 0 2006.281.07:49:22.37#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:49:22.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:49:22.37#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:49:22.37#ibcon#*before write, iclass 20, count 0 2006.281.07:49:22.37#ibcon#enter sib2, iclass 20, count 0 2006.281.07:49:22.37#ibcon#flushed, iclass 20, count 0 2006.281.07:49:22.37#ibcon#about to write, iclass 20, count 0 2006.281.07:49:22.37#ibcon#wrote, iclass 20, count 0 2006.281.07:49:22.37#ibcon#about to read 3, iclass 20, count 0 2006.281.07:49:22.41#ibcon#read 3, iclass 20, count 0 2006.281.07:49:22.41#ibcon#about to read 4, iclass 20, count 0 2006.281.07:49:22.41#ibcon#read 4, iclass 20, count 0 2006.281.07:49:22.41#ibcon#about to read 5, iclass 20, count 0 2006.281.07:49:22.41#ibcon#read 5, iclass 20, count 0 2006.281.07:49:22.41#ibcon#about to read 6, iclass 20, count 0 2006.281.07:49:22.41#ibcon#read 6, iclass 20, count 0 2006.281.07:49:22.41#ibcon#end of sib2, iclass 20, count 0 2006.281.07:49:22.41#ibcon#*after write, iclass 20, count 0 2006.281.07:49:22.41#ibcon#*before return 0, iclass 20, count 0 2006.281.07:49:22.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:22.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:49:22.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:49:22.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:49:22.41$vc4f8/vb=1,4 2006.281.07:49:22.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:49:22.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:49:22.41#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:22.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:22.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:22.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:22.41#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:49:22.41#ibcon#first serial, iclass 22, count 2 2006.281.07:49:22.41#ibcon#enter sib2, iclass 22, count 2 2006.281.07:49:22.41#ibcon#flushed, iclass 22, count 2 2006.281.07:49:22.41#ibcon#about to write, iclass 22, count 2 2006.281.07:49:22.41#ibcon#wrote, iclass 22, count 2 2006.281.07:49:22.41#ibcon#about to read 3, iclass 22, count 2 2006.281.07:49:22.44#ibcon#read 3, iclass 22, count 2 2006.281.07:49:22.44#ibcon#about to read 4, iclass 22, count 2 2006.281.07:49:22.44#ibcon#read 4, iclass 22, count 2 2006.281.07:49:22.44#ibcon#about to read 5, iclass 22, count 2 2006.281.07:49:22.44#ibcon#read 5, iclass 22, count 2 2006.281.07:49:22.44#ibcon#about to read 6, iclass 22, count 2 2006.281.07:49:22.44#ibcon#read 6, iclass 22, count 2 2006.281.07:49:22.44#ibcon#end of sib2, iclass 22, count 2 2006.281.07:49:22.47#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:49:22.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:49:22.47#ibcon#[27=AT01-04\r\n] 2006.281.07:49:22.47#ibcon#*before write, iclass 22, count 2 2006.281.07:49:22.47#ibcon#enter sib2, iclass 22, count 2 2006.281.07:49:22.47#ibcon#flushed, iclass 22, count 2 2006.281.07:49:22.47#ibcon#about to write, iclass 22, count 2 2006.281.07:49:22.47#ibcon#wrote, iclass 22, count 2 2006.281.07:49:22.47#ibcon#about to read 3, iclass 22, count 2 2006.281.07:49:22.50#ibcon#read 3, iclass 22, count 2 2006.281.07:49:22.50#ibcon#about to read 4, iclass 22, count 2 2006.281.07:49:22.50#ibcon#read 4, iclass 22, count 2 2006.281.07:49:22.50#ibcon#about to read 5, iclass 22, count 2 2006.281.07:49:22.50#ibcon#read 5, iclass 22, count 2 2006.281.07:49:22.50#ibcon#about to read 6, iclass 22, count 2 2006.281.07:49:22.50#ibcon#read 6, iclass 22, count 2 2006.281.07:49:22.50#ibcon#end of sib2, iclass 22, count 2 2006.281.07:49:22.50#ibcon#*after write, iclass 22, count 2 2006.281.07:49:22.50#ibcon#*before return 0, iclass 22, count 2 2006.281.07:49:22.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:22.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:49:22.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:49:22.50#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:22.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:22.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:22.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:22.63#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:49:22.63#ibcon#first serial, iclass 22, count 0 2006.281.07:49:22.63#ibcon#enter sib2, iclass 22, count 0 2006.281.07:49:22.63#ibcon#flushed, iclass 22, count 0 2006.281.07:49:22.63#ibcon#about to write, iclass 22, count 0 2006.281.07:49:22.63#ibcon#wrote, iclass 22, count 0 2006.281.07:49:22.63#ibcon#about to read 3, iclass 22, count 0 2006.281.07:49:22.64#ibcon#read 3, iclass 22, count 0 2006.281.07:49:22.64#ibcon#about to read 4, iclass 22, count 0 2006.281.07:49:22.64#ibcon#read 4, iclass 22, count 0 2006.281.07:49:22.64#ibcon#about to read 5, iclass 22, count 0 2006.281.07:49:22.64#ibcon#read 5, iclass 22, count 0 2006.281.07:49:22.64#ibcon#about to read 6, iclass 22, count 0 2006.281.07:49:22.64#ibcon#read 6, iclass 22, count 0 2006.281.07:49:22.64#ibcon#end of sib2, iclass 22, count 0 2006.281.07:49:22.64#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:49:22.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:49:22.64#ibcon#[27=USB\r\n] 2006.281.07:49:22.64#ibcon#*before write, iclass 22, count 0 2006.281.07:49:22.64#ibcon#enter sib2, iclass 22, count 0 2006.281.07:49:22.64#ibcon#flushed, iclass 22, count 0 2006.281.07:49:22.64#ibcon#about to write, iclass 22, count 0 2006.281.07:49:22.64#ibcon#wrote, iclass 22, count 0 2006.281.07:49:22.64#ibcon#about to read 3, iclass 22, count 0 2006.281.07:49:22.67#ibcon#read 3, iclass 22, count 0 2006.281.07:49:22.67#ibcon#about to read 4, iclass 22, count 0 2006.281.07:49:22.67#ibcon#read 4, iclass 22, count 0 2006.281.07:49:22.67#ibcon#about to read 5, iclass 22, count 0 2006.281.07:49:22.67#ibcon#read 5, iclass 22, count 0 2006.281.07:49:22.67#ibcon#about to read 6, iclass 22, count 0 2006.281.07:49:22.67#ibcon#read 6, iclass 22, count 0 2006.281.07:49:22.67#ibcon#end of sib2, iclass 22, count 0 2006.281.07:49:22.67#ibcon#*after write, iclass 22, count 0 2006.281.07:49:22.67#ibcon#*before return 0, iclass 22, count 0 2006.281.07:49:22.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:22.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:49:22.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:49:22.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:49:22.67$vc4f8/vblo=2,640.99 2006.281.07:49:22.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:49:22.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:49:22.67#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:22.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:22.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:22.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:22.67#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:49:22.67#ibcon#first serial, iclass 24, count 0 2006.281.07:49:22.67#ibcon#enter sib2, iclass 24, count 0 2006.281.07:49:22.67#ibcon#flushed, iclass 24, count 0 2006.281.07:49:22.67#ibcon#about to write, iclass 24, count 0 2006.281.07:49:22.67#ibcon#wrote, iclass 24, count 0 2006.281.07:49:22.67#ibcon#about to read 3, iclass 24, count 0 2006.281.07:49:22.69#ibcon#read 3, iclass 24, count 0 2006.281.07:49:22.69#ibcon#about to read 4, iclass 24, count 0 2006.281.07:49:22.69#ibcon#read 4, iclass 24, count 0 2006.281.07:49:22.69#ibcon#about to read 5, iclass 24, count 0 2006.281.07:49:22.69#ibcon#read 5, iclass 24, count 0 2006.281.07:49:22.69#ibcon#about to read 6, iclass 24, count 0 2006.281.07:49:22.69#ibcon#read 6, iclass 24, count 0 2006.281.07:49:22.69#ibcon#end of sib2, iclass 24, count 0 2006.281.07:49:22.69#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:49:22.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:49:22.69#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:49:22.69#ibcon#*before write, iclass 24, count 0 2006.281.07:49:22.69#ibcon#enter sib2, iclass 24, count 0 2006.281.07:49:22.69#ibcon#flushed, iclass 24, count 0 2006.281.07:49:22.69#ibcon#about to write, iclass 24, count 0 2006.281.07:49:22.69#ibcon#wrote, iclass 24, count 0 2006.281.07:49:22.69#ibcon#about to read 3, iclass 24, count 0 2006.281.07:49:22.74#ibcon#read 3, iclass 24, count 0 2006.281.07:49:22.74#ibcon#about to read 4, iclass 24, count 0 2006.281.07:49:22.74#ibcon#read 4, iclass 24, count 0 2006.281.07:49:22.74#ibcon#about to read 5, iclass 24, count 0 2006.281.07:49:22.74#ibcon#read 5, iclass 24, count 0 2006.281.07:49:22.74#ibcon#about to read 6, iclass 24, count 0 2006.281.07:49:22.74#ibcon#read 6, iclass 24, count 0 2006.281.07:49:22.74#ibcon#end of sib2, iclass 24, count 0 2006.281.07:49:22.74#ibcon#*after write, iclass 24, count 0 2006.281.07:49:22.74#ibcon#*before return 0, iclass 24, count 0 2006.281.07:49:22.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:22.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:49:22.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:49:22.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:49:22.74$vc4f8/vb=2,5 2006.281.07:49:22.74#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:49:22.74#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:49:22.74#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:22.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:22.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:22.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:22.78#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:49:22.78#ibcon#first serial, iclass 26, count 2 2006.281.07:49:22.78#ibcon#enter sib2, iclass 26, count 2 2006.281.07:49:22.78#ibcon#flushed, iclass 26, count 2 2006.281.07:49:22.78#ibcon#about to write, iclass 26, count 2 2006.281.07:49:22.78#ibcon#wrote, iclass 26, count 2 2006.281.07:49:22.78#ibcon#about to read 3, iclass 26, count 2 2006.281.07:49:22.81#ibcon#read 3, iclass 26, count 2 2006.281.07:49:22.81#ibcon#about to read 4, iclass 26, count 2 2006.281.07:49:22.81#ibcon#read 4, iclass 26, count 2 2006.281.07:49:22.81#ibcon#about to read 5, iclass 26, count 2 2006.281.07:49:22.81#ibcon#read 5, iclass 26, count 2 2006.281.07:49:22.81#ibcon#about to read 6, iclass 26, count 2 2006.281.07:49:22.81#ibcon#read 6, iclass 26, count 2 2006.281.07:49:22.81#ibcon#end of sib2, iclass 26, count 2 2006.281.07:49:22.81#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:49:22.81#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:49:22.81#ibcon#[27=AT02-05\r\n] 2006.281.07:49:22.81#ibcon#*before write, iclass 26, count 2 2006.281.07:49:22.81#ibcon#enter sib2, iclass 26, count 2 2006.281.07:49:22.81#ibcon#flushed, iclass 26, count 2 2006.281.07:49:22.81#ibcon#about to write, iclass 26, count 2 2006.281.07:49:22.81#ibcon#wrote, iclass 26, count 2 2006.281.07:49:22.81#ibcon#about to read 3, iclass 26, count 2 2006.281.07:49:22.84#ibcon#read 3, iclass 26, count 2 2006.281.07:49:22.84#ibcon#about to read 4, iclass 26, count 2 2006.281.07:49:22.84#ibcon#read 4, iclass 26, count 2 2006.281.07:49:22.84#ibcon#about to read 5, iclass 26, count 2 2006.281.07:49:22.84#ibcon#read 5, iclass 26, count 2 2006.281.07:49:22.84#ibcon#about to read 6, iclass 26, count 2 2006.281.07:49:22.84#ibcon#read 6, iclass 26, count 2 2006.281.07:49:22.84#ibcon#end of sib2, iclass 26, count 2 2006.281.07:49:22.84#ibcon#*after write, iclass 26, count 2 2006.281.07:49:22.84#ibcon#*before return 0, iclass 26, count 2 2006.281.07:49:22.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:22.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:49:22.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:49:22.84#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:22.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:22.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:22.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:22.96#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:49:22.96#ibcon#first serial, iclass 26, count 0 2006.281.07:49:22.96#ibcon#enter sib2, iclass 26, count 0 2006.281.07:49:22.96#ibcon#flushed, iclass 26, count 0 2006.281.07:49:22.96#ibcon#about to write, iclass 26, count 0 2006.281.07:49:22.96#ibcon#wrote, iclass 26, count 0 2006.281.07:49:22.96#ibcon#about to read 3, iclass 26, count 0 2006.281.07:49:22.98#ibcon#read 3, iclass 26, count 0 2006.281.07:49:22.98#ibcon#about to read 4, iclass 26, count 0 2006.281.07:49:22.98#ibcon#read 4, iclass 26, count 0 2006.281.07:49:22.98#ibcon#about to read 5, iclass 26, count 0 2006.281.07:49:22.98#ibcon#read 5, iclass 26, count 0 2006.281.07:49:22.98#ibcon#about to read 6, iclass 26, count 0 2006.281.07:49:22.98#ibcon#read 6, iclass 26, count 0 2006.281.07:49:22.98#ibcon#end of sib2, iclass 26, count 0 2006.281.07:49:22.98#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:49:22.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:49:22.98#ibcon#[27=USB\r\n] 2006.281.07:49:22.98#ibcon#*before write, iclass 26, count 0 2006.281.07:49:22.98#ibcon#enter sib2, iclass 26, count 0 2006.281.07:49:22.98#ibcon#flushed, iclass 26, count 0 2006.281.07:49:22.98#ibcon#about to write, iclass 26, count 0 2006.281.07:49:22.98#ibcon#wrote, iclass 26, count 0 2006.281.07:49:22.98#ibcon#about to read 3, iclass 26, count 0 2006.281.07:49:23.01#ibcon#read 3, iclass 26, count 0 2006.281.07:49:23.01#ibcon#about to read 4, iclass 26, count 0 2006.281.07:49:23.01#ibcon#read 4, iclass 26, count 0 2006.281.07:49:23.01#ibcon#about to read 5, iclass 26, count 0 2006.281.07:49:23.01#ibcon#read 5, iclass 26, count 0 2006.281.07:49:23.01#ibcon#about to read 6, iclass 26, count 0 2006.281.07:49:23.01#ibcon#read 6, iclass 26, count 0 2006.281.07:49:23.01#ibcon#end of sib2, iclass 26, count 0 2006.281.07:49:23.01#ibcon#*after write, iclass 26, count 0 2006.281.07:49:23.01#ibcon#*before return 0, iclass 26, count 0 2006.281.07:49:23.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:23.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:49:23.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:49:23.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:49:23.01$vc4f8/vblo=3,656.99 2006.281.07:49:23.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:49:23.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:49:23.01#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:23.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:23.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:23.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:23.01#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:49:23.01#ibcon#first serial, iclass 28, count 0 2006.281.07:49:23.01#ibcon#enter sib2, iclass 28, count 0 2006.281.07:49:23.01#ibcon#flushed, iclass 28, count 0 2006.281.07:49:23.01#ibcon#about to write, iclass 28, count 0 2006.281.07:49:23.01#ibcon#wrote, iclass 28, count 0 2006.281.07:49:23.01#ibcon#about to read 3, iclass 28, count 0 2006.281.07:49:23.03#ibcon#read 3, iclass 28, count 0 2006.281.07:49:23.04#ibcon#about to read 4, iclass 28, count 0 2006.281.07:49:23.04#ibcon#read 4, iclass 28, count 0 2006.281.07:49:23.04#ibcon#about to read 5, iclass 28, count 0 2006.281.07:49:23.04#ibcon#read 5, iclass 28, count 0 2006.281.07:49:23.04#ibcon#about to read 6, iclass 28, count 0 2006.281.07:49:23.04#ibcon#read 6, iclass 28, count 0 2006.281.07:49:23.04#ibcon#end of sib2, iclass 28, count 0 2006.281.07:49:23.04#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:49:23.04#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:49:23.04#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:49:23.04#ibcon#*before write, iclass 28, count 0 2006.281.07:49:23.04#ibcon#enter sib2, iclass 28, count 0 2006.281.07:49:23.04#ibcon#flushed, iclass 28, count 0 2006.281.07:49:23.04#ibcon#about to write, iclass 28, count 0 2006.281.07:49:23.04#ibcon#wrote, iclass 28, count 0 2006.281.07:49:23.04#ibcon#about to read 3, iclass 28, count 0 2006.281.07:49:23.08#ibcon#read 3, iclass 28, count 0 2006.281.07:49:23.08#ibcon#about to read 4, iclass 28, count 0 2006.281.07:49:23.08#ibcon#read 4, iclass 28, count 0 2006.281.07:49:23.08#ibcon#about to read 5, iclass 28, count 0 2006.281.07:49:23.08#ibcon#read 5, iclass 28, count 0 2006.281.07:49:23.08#ibcon#about to read 6, iclass 28, count 0 2006.281.07:49:23.08#ibcon#read 6, iclass 28, count 0 2006.281.07:49:23.08#ibcon#end of sib2, iclass 28, count 0 2006.281.07:49:23.08#ibcon#*after write, iclass 28, count 0 2006.281.07:49:23.08#ibcon#*before return 0, iclass 28, count 0 2006.281.07:49:23.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:23.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:49:23.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:49:23.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:49:23.08$vc4f8/vb=3,4 2006.281.07:49:23.08#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:49:23.08#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:49:23.08#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:23.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:23.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:23.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:23.13#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:49:23.13#ibcon#first serial, iclass 30, count 2 2006.281.07:49:23.13#ibcon#enter sib2, iclass 30, count 2 2006.281.07:49:23.13#ibcon#flushed, iclass 30, count 2 2006.281.07:49:23.13#ibcon#about to write, iclass 30, count 2 2006.281.07:49:23.13#ibcon#wrote, iclass 30, count 2 2006.281.07:49:23.13#ibcon#about to read 3, iclass 30, count 2 2006.281.07:49:23.15#ibcon#read 3, iclass 30, count 2 2006.281.07:49:23.15#ibcon#about to read 4, iclass 30, count 2 2006.281.07:49:23.15#ibcon#read 4, iclass 30, count 2 2006.281.07:49:23.15#ibcon#about to read 5, iclass 30, count 2 2006.281.07:49:23.15#ibcon#read 5, iclass 30, count 2 2006.281.07:49:23.15#ibcon#about to read 6, iclass 30, count 2 2006.281.07:49:23.15#ibcon#read 6, iclass 30, count 2 2006.281.07:49:23.15#ibcon#end of sib2, iclass 30, count 2 2006.281.07:49:23.15#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:49:23.15#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:49:23.15#ibcon#[27=AT03-04\r\n] 2006.281.07:49:23.15#ibcon#*before write, iclass 30, count 2 2006.281.07:49:23.15#ibcon#enter sib2, iclass 30, count 2 2006.281.07:49:23.15#ibcon#flushed, iclass 30, count 2 2006.281.07:49:23.15#ibcon#about to write, iclass 30, count 2 2006.281.07:49:23.15#ibcon#wrote, iclass 30, count 2 2006.281.07:49:23.15#ibcon#about to read 3, iclass 30, count 2 2006.281.07:49:23.18#ibcon#read 3, iclass 30, count 2 2006.281.07:49:23.18#ibcon#about to read 4, iclass 30, count 2 2006.281.07:49:23.18#ibcon#read 4, iclass 30, count 2 2006.281.07:49:23.18#ibcon#about to read 5, iclass 30, count 2 2006.281.07:49:23.18#ibcon#read 5, iclass 30, count 2 2006.281.07:49:23.18#ibcon#about to read 6, iclass 30, count 2 2006.281.07:49:23.18#ibcon#read 6, iclass 30, count 2 2006.281.07:49:23.18#ibcon#end of sib2, iclass 30, count 2 2006.281.07:49:23.18#ibcon#*after write, iclass 30, count 2 2006.281.07:49:23.18#ibcon#*before return 0, iclass 30, count 2 2006.281.07:49:23.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:23.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:49:23.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:49:23.18#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:23.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:23.31#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:23.31#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:23.31#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:49:23.31#ibcon#first serial, iclass 30, count 0 2006.281.07:49:23.31#ibcon#enter sib2, iclass 30, count 0 2006.281.07:49:23.31#ibcon#flushed, iclass 30, count 0 2006.281.07:49:23.31#ibcon#about to write, iclass 30, count 0 2006.281.07:49:23.31#ibcon#wrote, iclass 30, count 0 2006.281.07:49:23.31#ibcon#about to read 3, iclass 30, count 0 2006.281.07:49:23.32#ibcon#read 3, iclass 30, count 0 2006.281.07:49:23.32#ibcon#about to read 4, iclass 30, count 0 2006.281.07:49:23.32#ibcon#read 4, iclass 30, count 0 2006.281.07:49:23.32#ibcon#about to read 5, iclass 30, count 0 2006.281.07:49:23.32#ibcon#read 5, iclass 30, count 0 2006.281.07:49:23.32#ibcon#about to read 6, iclass 30, count 0 2006.281.07:49:23.32#ibcon#read 6, iclass 30, count 0 2006.281.07:49:23.32#ibcon#end of sib2, iclass 30, count 0 2006.281.07:49:23.32#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:49:23.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:49:23.32#ibcon#[27=USB\r\n] 2006.281.07:49:23.32#ibcon#*before write, iclass 30, count 0 2006.281.07:49:23.32#ibcon#enter sib2, iclass 30, count 0 2006.281.07:49:23.32#ibcon#flushed, iclass 30, count 0 2006.281.07:49:23.32#ibcon#about to write, iclass 30, count 0 2006.281.07:49:23.32#ibcon#wrote, iclass 30, count 0 2006.281.07:49:23.32#ibcon#about to read 3, iclass 30, count 0 2006.281.07:49:23.35#ibcon#read 3, iclass 30, count 0 2006.281.07:49:23.35#ibcon#about to read 4, iclass 30, count 0 2006.281.07:49:23.35#ibcon#read 4, iclass 30, count 0 2006.281.07:49:23.35#ibcon#about to read 5, iclass 30, count 0 2006.281.07:49:23.35#ibcon#read 5, iclass 30, count 0 2006.281.07:49:23.35#ibcon#about to read 6, iclass 30, count 0 2006.281.07:49:23.35#ibcon#read 6, iclass 30, count 0 2006.281.07:49:23.35#ibcon#end of sib2, iclass 30, count 0 2006.281.07:49:23.35#ibcon#*after write, iclass 30, count 0 2006.281.07:49:23.35#ibcon#*before return 0, iclass 30, count 0 2006.281.07:49:23.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:23.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:49:23.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:49:23.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:49:23.35$vc4f8/vblo=4,712.99 2006.281.07:49:23.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:49:23.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:49:23.35#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:23.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:49:23.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:49:23.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:49:23.35#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:49:23.35#ibcon#first serial, iclass 32, count 0 2006.281.07:49:23.35#ibcon#enter sib2, iclass 32, count 0 2006.281.07:49:23.35#ibcon#flushed, iclass 32, count 0 2006.281.07:49:23.35#ibcon#about to write, iclass 32, count 0 2006.281.07:49:23.35#ibcon#wrote, iclass 32, count 0 2006.281.07:49:23.35#ibcon#about to read 3, iclass 32, count 0 2006.281.07:49:23.37#ibcon#read 3, iclass 32, count 0 2006.281.07:49:23.37#ibcon#about to read 4, iclass 32, count 0 2006.281.07:49:23.37#ibcon#read 4, iclass 32, count 0 2006.281.07:49:23.37#ibcon#about to read 5, iclass 32, count 0 2006.281.07:49:23.37#ibcon#read 5, iclass 32, count 0 2006.281.07:49:23.37#ibcon#about to read 6, iclass 32, count 0 2006.281.07:49:23.37#ibcon#read 6, iclass 32, count 0 2006.281.07:49:23.37#ibcon#end of sib2, iclass 32, count 0 2006.281.07:49:23.37#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:49:23.37#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:49:23.37#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:49:23.37#ibcon#*before write, iclass 32, count 0 2006.281.07:49:23.37#ibcon#enter sib2, iclass 32, count 0 2006.281.07:49:23.37#ibcon#flushed, iclass 32, count 0 2006.281.07:49:23.37#ibcon#about to write, iclass 32, count 0 2006.281.07:49:23.37#ibcon#wrote, iclass 32, count 0 2006.281.07:49:23.37#ibcon#about to read 3, iclass 32, count 0 2006.281.07:49:23.41#ibcon#read 3, iclass 32, count 0 2006.281.07:49:23.41#ibcon#about to read 4, iclass 32, count 0 2006.281.07:49:23.41#ibcon#read 4, iclass 32, count 0 2006.281.07:49:23.41#ibcon#about to read 5, iclass 32, count 0 2006.281.07:49:23.41#ibcon#read 5, iclass 32, count 0 2006.281.07:49:23.41#ibcon#about to read 6, iclass 32, count 0 2006.281.07:49:23.41#ibcon#read 6, iclass 32, count 0 2006.281.07:49:23.41#ibcon#end of sib2, iclass 32, count 0 2006.281.07:49:23.41#ibcon#*after write, iclass 32, count 0 2006.281.07:49:23.41#ibcon#*before return 0, iclass 32, count 0 2006.281.07:49:23.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:49:23.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:49:23.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:49:23.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:49:23.41$vc4f8/vb=4,4 2006.281.07:49:23.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:49:23.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:49:23.41#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:23.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:49:23.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:49:23.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:49:23.47#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:49:23.47#ibcon#first serial, iclass 34, count 2 2006.281.07:49:23.47#ibcon#enter sib2, iclass 34, count 2 2006.281.07:49:23.47#ibcon#flushed, iclass 34, count 2 2006.281.07:49:23.47#ibcon#about to write, iclass 34, count 2 2006.281.07:49:23.47#ibcon#wrote, iclass 34, count 2 2006.281.07:49:23.47#ibcon#about to read 3, iclass 34, count 2 2006.281.07:49:23.49#ibcon#read 3, iclass 34, count 2 2006.281.07:49:23.49#ibcon#about to read 4, iclass 34, count 2 2006.281.07:49:23.49#ibcon#read 4, iclass 34, count 2 2006.281.07:49:23.49#ibcon#about to read 5, iclass 34, count 2 2006.281.07:49:23.49#ibcon#read 5, iclass 34, count 2 2006.281.07:49:23.49#ibcon#about to read 6, iclass 34, count 2 2006.281.07:49:23.49#ibcon#read 6, iclass 34, count 2 2006.281.07:49:23.49#ibcon#end of sib2, iclass 34, count 2 2006.281.07:49:23.49#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:49:23.49#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:49:23.49#ibcon#[27=AT04-04\r\n] 2006.281.07:49:23.49#ibcon#*before write, iclass 34, count 2 2006.281.07:49:23.49#ibcon#enter sib2, iclass 34, count 2 2006.281.07:49:23.49#ibcon#flushed, iclass 34, count 2 2006.281.07:49:23.49#ibcon#about to write, iclass 34, count 2 2006.281.07:49:23.49#ibcon#wrote, iclass 34, count 2 2006.281.07:49:23.49#ibcon#about to read 3, iclass 34, count 2 2006.281.07:49:23.52#ibcon#read 3, iclass 34, count 2 2006.281.07:49:23.52#ibcon#about to read 4, iclass 34, count 2 2006.281.07:49:23.52#ibcon#read 4, iclass 34, count 2 2006.281.07:49:23.52#ibcon#about to read 5, iclass 34, count 2 2006.281.07:49:23.52#ibcon#read 5, iclass 34, count 2 2006.281.07:49:23.52#ibcon#about to read 6, iclass 34, count 2 2006.281.07:49:23.52#ibcon#read 6, iclass 34, count 2 2006.281.07:49:23.52#ibcon#end of sib2, iclass 34, count 2 2006.281.07:49:23.52#ibcon#*after write, iclass 34, count 2 2006.281.07:49:23.52#ibcon#*before return 0, iclass 34, count 2 2006.281.07:49:23.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:49:23.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:49:23.52#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:49:23.52#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:23.52#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:49:23.64#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:49:23.64#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:49:23.64#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:49:23.64#ibcon#first serial, iclass 34, count 0 2006.281.07:49:23.64#ibcon#enter sib2, iclass 34, count 0 2006.281.07:49:23.64#ibcon#flushed, iclass 34, count 0 2006.281.07:49:23.64#ibcon#about to write, iclass 34, count 0 2006.281.07:49:23.64#ibcon#wrote, iclass 34, count 0 2006.281.07:49:23.64#ibcon#about to read 3, iclass 34, count 0 2006.281.07:49:23.66#ibcon#read 3, iclass 34, count 0 2006.281.07:49:23.66#ibcon#about to read 4, iclass 34, count 0 2006.281.07:49:23.66#ibcon#read 4, iclass 34, count 0 2006.281.07:49:23.66#ibcon#about to read 5, iclass 34, count 0 2006.281.07:49:23.66#ibcon#read 5, iclass 34, count 0 2006.281.07:49:23.66#ibcon#about to read 6, iclass 34, count 0 2006.281.07:49:23.66#ibcon#read 6, iclass 34, count 0 2006.281.07:49:23.66#ibcon#end of sib2, iclass 34, count 0 2006.281.07:49:23.66#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:49:23.66#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:49:23.66#ibcon#[27=USB\r\n] 2006.281.07:49:23.66#ibcon#*before write, iclass 34, count 0 2006.281.07:49:23.66#ibcon#enter sib2, iclass 34, count 0 2006.281.07:49:23.66#ibcon#flushed, iclass 34, count 0 2006.281.07:49:23.66#ibcon#about to write, iclass 34, count 0 2006.281.07:49:23.66#ibcon#wrote, iclass 34, count 0 2006.281.07:49:23.66#ibcon#about to read 3, iclass 34, count 0 2006.281.07:49:23.69#ibcon#read 3, iclass 34, count 0 2006.281.07:49:23.69#ibcon#about to read 4, iclass 34, count 0 2006.281.07:49:23.69#ibcon#read 4, iclass 34, count 0 2006.281.07:49:23.69#ibcon#about to read 5, iclass 34, count 0 2006.281.07:49:23.69#ibcon#read 5, iclass 34, count 0 2006.281.07:49:23.69#ibcon#about to read 6, iclass 34, count 0 2006.281.07:49:23.69#ibcon#read 6, iclass 34, count 0 2006.281.07:49:23.69#ibcon#end of sib2, iclass 34, count 0 2006.281.07:49:23.69#ibcon#*after write, iclass 34, count 0 2006.281.07:49:23.69#ibcon#*before return 0, iclass 34, count 0 2006.281.07:49:23.69#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:49:23.69#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:49:23.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:49:23.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:49:23.69$vc4f8/vblo=5,744.99 2006.281.07:49:23.69#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:49:23.69#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:49:23.69#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:23.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:49:23.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:49:23.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:49:23.69#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:49:23.69#ibcon#first serial, iclass 36, count 0 2006.281.07:49:23.69#ibcon#enter sib2, iclass 36, count 0 2006.281.07:49:23.69#ibcon#flushed, iclass 36, count 0 2006.281.07:49:23.69#ibcon#about to write, iclass 36, count 0 2006.281.07:49:23.69#ibcon#wrote, iclass 36, count 0 2006.281.07:49:23.69#ibcon#about to read 3, iclass 36, count 0 2006.281.07:49:23.71#ibcon#read 3, iclass 36, count 0 2006.281.07:49:23.71#ibcon#about to read 4, iclass 36, count 0 2006.281.07:49:23.71#ibcon#read 4, iclass 36, count 0 2006.281.07:49:23.71#ibcon#about to read 5, iclass 36, count 0 2006.281.07:49:23.71#ibcon#read 5, iclass 36, count 0 2006.281.07:49:23.71#ibcon#about to read 6, iclass 36, count 0 2006.281.07:49:23.71#ibcon#read 6, iclass 36, count 0 2006.281.07:49:23.71#ibcon#end of sib2, iclass 36, count 0 2006.281.07:49:23.71#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:49:23.71#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:49:23.71#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:49:23.71#ibcon#*before write, iclass 36, count 0 2006.281.07:49:23.71#ibcon#enter sib2, iclass 36, count 0 2006.281.07:49:23.71#ibcon#flushed, iclass 36, count 0 2006.281.07:49:23.71#ibcon#about to write, iclass 36, count 0 2006.281.07:49:23.71#ibcon#wrote, iclass 36, count 0 2006.281.07:49:23.71#ibcon#about to read 3, iclass 36, count 0 2006.281.07:49:23.76#ibcon#read 3, iclass 36, count 0 2006.281.07:49:23.76#ibcon#about to read 4, iclass 36, count 0 2006.281.07:49:23.76#ibcon#read 4, iclass 36, count 0 2006.281.07:49:23.76#ibcon#about to read 5, iclass 36, count 0 2006.281.07:49:23.76#ibcon#read 5, iclass 36, count 0 2006.281.07:49:23.76#ibcon#about to read 6, iclass 36, count 0 2006.281.07:49:23.76#ibcon#read 6, iclass 36, count 0 2006.281.07:49:23.76#ibcon#end of sib2, iclass 36, count 0 2006.281.07:49:23.76#ibcon#*after write, iclass 36, count 0 2006.281.07:49:23.76#ibcon#*before return 0, iclass 36, count 0 2006.281.07:49:23.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:49:23.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:49:23.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:49:23.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:49:23.76$vc4f8/vb=5,4 2006.281.07:49:23.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:49:23.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:49:23.76#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:23.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:23.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:23.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:23.80#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:49:23.80#ibcon#first serial, iclass 38, count 2 2006.281.07:49:23.80#ibcon#enter sib2, iclass 38, count 2 2006.281.07:49:23.80#ibcon#flushed, iclass 38, count 2 2006.281.07:49:23.80#ibcon#about to write, iclass 38, count 2 2006.281.07:49:23.80#ibcon#wrote, iclass 38, count 2 2006.281.07:49:23.80#ibcon#about to read 3, iclass 38, count 2 2006.281.07:49:23.83#ibcon#read 3, iclass 38, count 2 2006.281.07:49:23.83#ibcon#about to read 4, iclass 38, count 2 2006.281.07:49:23.83#ibcon#read 4, iclass 38, count 2 2006.281.07:49:23.83#ibcon#about to read 5, iclass 38, count 2 2006.281.07:49:23.83#ibcon#read 5, iclass 38, count 2 2006.281.07:49:23.83#ibcon#about to read 6, iclass 38, count 2 2006.281.07:49:23.83#ibcon#read 6, iclass 38, count 2 2006.281.07:49:23.83#ibcon#end of sib2, iclass 38, count 2 2006.281.07:49:23.83#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:49:23.83#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:49:23.83#ibcon#[27=AT05-04\r\n] 2006.281.07:49:23.83#ibcon#*before write, iclass 38, count 2 2006.281.07:49:23.83#ibcon#enter sib2, iclass 38, count 2 2006.281.07:49:23.83#ibcon#flushed, iclass 38, count 2 2006.281.07:49:23.83#ibcon#about to write, iclass 38, count 2 2006.281.07:49:23.83#ibcon#wrote, iclass 38, count 2 2006.281.07:49:23.83#ibcon#about to read 3, iclass 38, count 2 2006.281.07:49:23.86#ibcon#read 3, iclass 38, count 2 2006.281.07:49:23.86#ibcon#about to read 4, iclass 38, count 2 2006.281.07:49:23.86#ibcon#read 4, iclass 38, count 2 2006.281.07:49:23.86#ibcon#about to read 5, iclass 38, count 2 2006.281.07:49:23.86#ibcon#read 5, iclass 38, count 2 2006.281.07:49:23.86#ibcon#about to read 6, iclass 38, count 2 2006.281.07:49:23.86#ibcon#read 6, iclass 38, count 2 2006.281.07:49:23.86#ibcon#end of sib2, iclass 38, count 2 2006.281.07:49:23.86#ibcon#*after write, iclass 38, count 2 2006.281.07:49:23.86#ibcon#*before return 0, iclass 38, count 2 2006.281.07:49:23.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:23.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:49:23.86#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:49:23.86#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:23.86#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:23.98#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:23.98#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:23.98#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:49:23.98#ibcon#first serial, iclass 38, count 0 2006.281.07:49:23.98#ibcon#enter sib2, iclass 38, count 0 2006.281.07:49:23.98#ibcon#flushed, iclass 38, count 0 2006.281.07:49:23.98#ibcon#about to write, iclass 38, count 0 2006.281.07:49:23.98#ibcon#wrote, iclass 38, count 0 2006.281.07:49:23.98#ibcon#about to read 3, iclass 38, count 0 2006.281.07:49:24.00#ibcon#read 3, iclass 38, count 0 2006.281.07:49:24.00#ibcon#about to read 4, iclass 38, count 0 2006.281.07:49:24.00#ibcon#read 4, iclass 38, count 0 2006.281.07:49:24.00#ibcon#about to read 5, iclass 38, count 0 2006.281.07:49:24.00#ibcon#read 5, iclass 38, count 0 2006.281.07:49:24.00#ibcon#about to read 6, iclass 38, count 0 2006.281.07:49:24.00#ibcon#read 6, iclass 38, count 0 2006.281.07:49:24.00#ibcon#end of sib2, iclass 38, count 0 2006.281.07:49:24.00#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:49:24.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:49:24.00#ibcon#[27=USB\r\n] 2006.281.07:49:24.00#ibcon#*before write, iclass 38, count 0 2006.281.07:49:24.00#ibcon#enter sib2, iclass 38, count 0 2006.281.07:49:24.00#ibcon#flushed, iclass 38, count 0 2006.281.07:49:24.00#ibcon#about to write, iclass 38, count 0 2006.281.07:49:24.00#ibcon#wrote, iclass 38, count 0 2006.281.07:49:24.00#ibcon#about to read 3, iclass 38, count 0 2006.281.07:49:24.03#ibcon#read 3, iclass 38, count 0 2006.281.07:49:24.03#ibcon#about to read 4, iclass 38, count 0 2006.281.07:49:24.03#ibcon#read 4, iclass 38, count 0 2006.281.07:49:24.03#ibcon#about to read 5, iclass 38, count 0 2006.281.07:49:24.03#ibcon#read 5, iclass 38, count 0 2006.281.07:49:24.03#ibcon#about to read 6, iclass 38, count 0 2006.281.07:49:24.03#ibcon#read 6, iclass 38, count 0 2006.281.07:49:24.03#ibcon#end of sib2, iclass 38, count 0 2006.281.07:49:24.03#ibcon#*after write, iclass 38, count 0 2006.281.07:49:24.03#ibcon#*before return 0, iclass 38, count 0 2006.281.07:49:24.03#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:24.03#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:49:24.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:49:24.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:49:24.03$vc4f8/vblo=6,752.99 2006.281.07:49:24.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:49:24.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:49:24.03#ibcon#ireg 17 cls_cnt 0 2006.281.07:49:24.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:24.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:24.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:24.03#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:49:24.03#ibcon#first serial, iclass 40, count 0 2006.281.07:49:24.03#ibcon#enter sib2, iclass 40, count 0 2006.281.07:49:24.03#ibcon#flushed, iclass 40, count 0 2006.281.07:49:24.03#ibcon#about to write, iclass 40, count 0 2006.281.07:49:24.03#ibcon#wrote, iclass 40, count 0 2006.281.07:49:24.03#ibcon#about to read 3, iclass 40, count 0 2006.281.07:49:24.05#ibcon#read 3, iclass 40, count 0 2006.281.07:49:24.06#ibcon#about to read 4, iclass 40, count 0 2006.281.07:49:24.06#ibcon#read 4, iclass 40, count 0 2006.281.07:49:24.06#ibcon#about to read 5, iclass 40, count 0 2006.281.07:49:24.06#ibcon#read 5, iclass 40, count 0 2006.281.07:49:24.06#ibcon#about to read 6, iclass 40, count 0 2006.281.07:49:24.06#ibcon#read 6, iclass 40, count 0 2006.281.07:49:24.06#ibcon#end of sib2, iclass 40, count 0 2006.281.07:49:24.06#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:49:24.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:49:24.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:49:24.06#ibcon#*before write, iclass 40, count 0 2006.281.07:49:24.06#ibcon#enter sib2, iclass 40, count 0 2006.281.07:49:24.06#ibcon#flushed, iclass 40, count 0 2006.281.07:49:24.06#ibcon#about to write, iclass 40, count 0 2006.281.07:49:24.06#ibcon#wrote, iclass 40, count 0 2006.281.07:49:24.06#ibcon#about to read 3, iclass 40, count 0 2006.281.07:49:24.10#ibcon#read 3, iclass 40, count 0 2006.281.07:49:24.10#ibcon#about to read 4, iclass 40, count 0 2006.281.07:49:24.10#ibcon#read 4, iclass 40, count 0 2006.281.07:49:24.10#ibcon#about to read 5, iclass 40, count 0 2006.281.07:49:24.10#ibcon#read 5, iclass 40, count 0 2006.281.07:49:24.10#ibcon#about to read 6, iclass 40, count 0 2006.281.07:49:24.10#ibcon#read 6, iclass 40, count 0 2006.281.07:49:24.10#ibcon#end of sib2, iclass 40, count 0 2006.281.07:49:24.10#ibcon#*after write, iclass 40, count 0 2006.281.07:49:24.10#ibcon#*before return 0, iclass 40, count 0 2006.281.07:49:24.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:24.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:49:24.10#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:49:24.10#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:49:24.10$vc4f8/vb=6,4 2006.281.07:49:24.10#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:49:24.10#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:49:24.10#ibcon#ireg 11 cls_cnt 2 2006.281.07:49:24.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:24.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:24.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:24.15#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:49:24.15#ibcon#first serial, iclass 4, count 2 2006.281.07:49:24.15#ibcon#enter sib2, iclass 4, count 2 2006.281.07:49:24.15#ibcon#flushed, iclass 4, count 2 2006.281.07:49:24.15#ibcon#about to write, iclass 4, count 2 2006.281.07:49:24.15#ibcon#wrote, iclass 4, count 2 2006.281.07:49:24.15#ibcon#about to read 3, iclass 4, count 2 2006.281.07:49:24.17#ibcon#read 3, iclass 4, count 2 2006.281.07:49:24.17#ibcon#about to read 4, iclass 4, count 2 2006.281.07:49:24.17#ibcon#read 4, iclass 4, count 2 2006.281.07:49:24.17#ibcon#about to read 5, iclass 4, count 2 2006.281.07:49:24.17#ibcon#read 5, iclass 4, count 2 2006.281.07:49:24.17#ibcon#about to read 6, iclass 4, count 2 2006.281.07:49:24.17#ibcon#read 6, iclass 4, count 2 2006.281.07:49:24.17#ibcon#end of sib2, iclass 4, count 2 2006.281.07:49:24.17#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:49:24.17#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:49:24.17#ibcon#[27=AT06-04\r\n] 2006.281.07:49:24.17#ibcon#*before write, iclass 4, count 2 2006.281.07:49:24.17#ibcon#enter sib2, iclass 4, count 2 2006.281.07:49:24.17#ibcon#flushed, iclass 4, count 2 2006.281.07:49:24.17#ibcon#about to write, iclass 4, count 2 2006.281.07:49:24.17#ibcon#wrote, iclass 4, count 2 2006.281.07:49:24.17#ibcon#about to read 3, iclass 4, count 2 2006.281.07:49:24.20#ibcon#read 3, iclass 4, count 2 2006.281.07:49:24.20#ibcon#about to read 4, iclass 4, count 2 2006.281.07:49:24.20#ibcon#read 4, iclass 4, count 2 2006.281.07:49:24.20#ibcon#about to read 5, iclass 4, count 2 2006.281.07:49:24.20#ibcon#read 5, iclass 4, count 2 2006.281.07:49:24.20#ibcon#about to read 6, iclass 4, count 2 2006.281.07:49:24.20#ibcon#read 6, iclass 4, count 2 2006.281.07:49:24.20#ibcon#end of sib2, iclass 4, count 2 2006.281.07:49:24.20#ibcon#*after write, iclass 4, count 2 2006.281.07:49:24.20#ibcon#*before return 0, iclass 4, count 2 2006.281.07:49:24.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:24.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:49:24.20#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:49:24.20#ibcon#ireg 7 cls_cnt 0 2006.281.07:49:24.20#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:24.32#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:24.32#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:24.32#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:49:24.32#ibcon#first serial, iclass 4, count 0 2006.281.07:49:24.32#ibcon#enter sib2, iclass 4, count 0 2006.281.07:49:24.32#ibcon#flushed, iclass 4, count 0 2006.281.07:49:24.32#ibcon#about to write, iclass 4, count 0 2006.281.07:49:24.32#ibcon#wrote, iclass 4, count 0 2006.281.07:49:24.32#ibcon#about to read 3, iclass 4, count 0 2006.281.07:49:24.34#ibcon#read 3, iclass 4, count 0 2006.281.07:49:24.34#ibcon#about to read 4, iclass 4, count 0 2006.281.07:49:24.34#ibcon#read 4, iclass 4, count 0 2006.281.07:49:24.34#ibcon#about to read 5, iclass 4, count 0 2006.281.07:49:24.34#ibcon#read 5, iclass 4, count 0 2006.281.07:49:24.34#ibcon#about to read 6, iclass 4, count 0 2006.281.07:49:24.34#ibcon#read 6, iclass 4, count 0 2006.281.07:49:24.34#ibcon#end of sib2, iclass 4, count 0 2006.281.07:49:24.34#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:49:24.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:49:24.34#ibcon#[27=USB\r\n] 2006.281.07:49:24.34#ibcon#*before write, iclass 4, count 0 2006.281.07:49:24.34#ibcon#enter sib2, iclass 4, count 0 2006.281.07:49:24.34#ibcon#flushed, iclass 4, count 0 2006.281.07:49:24.34#ibcon#about to write, iclass 4, count 0 2006.281.07:49:24.34#ibcon#wrote, iclass 4, count 0 2006.281.07:49:24.34#ibcon#about to read 3, iclass 4, count 0 2006.281.07:49:24.37#ibcon#read 3, iclass 4, count 0 2006.281.07:49:24.37#ibcon#about to read 4, iclass 4, count 0 2006.281.07:49:24.37#ibcon#read 4, iclass 4, count 0 2006.281.07:49:24.37#ibcon#about to read 5, iclass 4, count 0 2006.281.07:49:24.37#ibcon#read 5, iclass 4, count 0 2006.281.07:49:24.37#ibcon#about to read 6, iclass 4, count 0 2006.281.07:49:24.37#ibcon#read 6, iclass 4, count 0 2006.281.07:49:24.37#ibcon#end of sib2, iclass 4, count 0 2006.281.07:49:24.37#ibcon#*after write, iclass 4, count 0 2006.281.07:49:24.37#ibcon#*before return 0, iclass 4, count 0 2006.281.07:49:24.37#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:24.37#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:49:24.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:49:24.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:49:24.37$vc4f8/vabw=wide 2006.281.07:49:24.37#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:49:24.37#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:49:24.37#ibcon#ireg 8 cls_cnt 0 2006.281.07:49:24.37#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:24.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:24.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:24.37#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:49:24.37#ibcon#first serial, iclass 6, count 0 2006.281.07:49:24.37#ibcon#enter sib2, iclass 6, count 0 2006.281.07:49:24.37#ibcon#flushed, iclass 6, count 0 2006.281.07:49:24.37#ibcon#about to write, iclass 6, count 0 2006.281.07:49:24.37#ibcon#wrote, iclass 6, count 0 2006.281.07:49:24.37#ibcon#about to read 3, iclass 6, count 0 2006.281.07:49:24.39#ibcon#read 3, iclass 6, count 0 2006.281.07:49:24.39#ibcon#about to read 4, iclass 6, count 0 2006.281.07:49:24.39#ibcon#read 4, iclass 6, count 0 2006.281.07:49:24.39#ibcon#about to read 5, iclass 6, count 0 2006.281.07:49:24.39#ibcon#read 5, iclass 6, count 0 2006.281.07:49:24.39#ibcon#about to read 6, iclass 6, count 0 2006.281.07:49:24.39#ibcon#read 6, iclass 6, count 0 2006.281.07:49:24.39#ibcon#end of sib2, iclass 6, count 0 2006.281.07:49:24.39#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:49:24.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:49:24.39#ibcon#[25=BW32\r\n] 2006.281.07:49:24.39#ibcon#*before write, iclass 6, count 0 2006.281.07:49:24.39#ibcon#enter sib2, iclass 6, count 0 2006.281.07:49:24.39#ibcon#flushed, iclass 6, count 0 2006.281.07:49:24.39#ibcon#about to write, iclass 6, count 0 2006.281.07:49:24.39#ibcon#wrote, iclass 6, count 0 2006.281.07:49:24.39#ibcon#about to read 3, iclass 6, count 0 2006.281.07:49:24.42#ibcon#read 3, iclass 6, count 0 2006.281.07:49:24.42#ibcon#about to read 4, iclass 6, count 0 2006.281.07:49:24.42#ibcon#read 4, iclass 6, count 0 2006.281.07:49:24.42#ibcon#about to read 5, iclass 6, count 0 2006.281.07:49:24.42#ibcon#read 5, iclass 6, count 0 2006.281.07:49:24.42#ibcon#about to read 6, iclass 6, count 0 2006.281.07:49:24.42#ibcon#read 6, iclass 6, count 0 2006.281.07:49:24.42#ibcon#end of sib2, iclass 6, count 0 2006.281.07:49:24.42#ibcon#*after write, iclass 6, count 0 2006.281.07:49:24.42#ibcon#*before return 0, iclass 6, count 0 2006.281.07:49:24.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:24.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:49:24.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:49:24.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:49:24.42$vc4f8/vbbw=wide 2006.281.07:49:24.42#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:49:24.42#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:49:24.42#ibcon#ireg 8 cls_cnt 0 2006.281.07:49:24.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:49:24.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:49:24.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:49:24.49#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:49:24.49#ibcon#first serial, iclass 10, count 0 2006.281.07:49:24.49#ibcon#enter sib2, iclass 10, count 0 2006.281.07:49:24.49#ibcon#flushed, iclass 10, count 0 2006.281.07:49:24.49#ibcon#about to write, iclass 10, count 0 2006.281.07:49:24.49#ibcon#wrote, iclass 10, count 0 2006.281.07:49:24.49#ibcon#about to read 3, iclass 10, count 0 2006.281.07:49:24.51#ibcon#read 3, iclass 10, count 0 2006.281.07:49:24.51#ibcon#about to read 4, iclass 10, count 0 2006.281.07:49:24.51#ibcon#read 4, iclass 10, count 0 2006.281.07:49:24.51#ibcon#about to read 5, iclass 10, count 0 2006.281.07:49:24.51#ibcon#read 5, iclass 10, count 0 2006.281.07:49:24.51#ibcon#about to read 6, iclass 10, count 0 2006.281.07:49:24.51#ibcon#read 6, iclass 10, count 0 2006.281.07:49:24.51#ibcon#end of sib2, iclass 10, count 0 2006.281.07:49:24.51#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:49:24.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:49:24.51#ibcon#[27=BW32\r\n] 2006.281.07:49:24.51#ibcon#*before write, iclass 10, count 0 2006.281.07:49:24.51#ibcon#enter sib2, iclass 10, count 0 2006.281.07:49:24.51#ibcon#flushed, iclass 10, count 0 2006.281.07:49:24.51#ibcon#about to write, iclass 10, count 0 2006.281.07:49:24.51#ibcon#wrote, iclass 10, count 0 2006.281.07:49:24.51#ibcon#about to read 3, iclass 10, count 0 2006.281.07:49:24.54#ibcon#read 3, iclass 10, count 0 2006.281.07:49:24.54#ibcon#about to read 4, iclass 10, count 0 2006.281.07:49:24.54#ibcon#read 4, iclass 10, count 0 2006.281.07:49:24.54#ibcon#about to read 5, iclass 10, count 0 2006.281.07:49:24.54#ibcon#read 5, iclass 10, count 0 2006.281.07:49:24.54#ibcon#about to read 6, iclass 10, count 0 2006.281.07:49:24.54#ibcon#read 6, iclass 10, count 0 2006.281.07:49:24.54#ibcon#end of sib2, iclass 10, count 0 2006.281.07:49:24.54#ibcon#*after write, iclass 10, count 0 2006.281.07:49:24.54#ibcon#*before return 0, iclass 10, count 0 2006.281.07:49:24.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:49:24.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:49:24.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:49:24.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:49:24.54$4f8m12a/ifd4f 2006.281.07:49:24.54$ifd4f/lo= 2006.281.07:49:24.54$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:49:24.54$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:49:24.54$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:49:24.54$ifd4f/patch= 2006.281.07:49:24.54$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:49:24.54$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:49:24.54$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:49:24.54$4f8m12a/"form=m,16.000,1:2 2006.281.07:49:24.54$4f8m12a/"tpicd 2006.281.07:49:24.54$4f8m12a/echo=off 2006.281.07:49:24.54$4f8m12a/xlog=off 2006.281.07:49:24.54:!2006.281.07:49:50 2006.281.07:49:36.13#trakl#Source acquired 2006.281.07:49:38.13#flagr#flagr/antenna,acquired 2006.281.07:49:50.00:preob 2006.281.07:49:51.13/onsource/TRACKING 2006.281.07:49:51.13:!2006.281.07:50:00 2006.281.07:49:52.13#trakl#Off source 2006.281.07:49:52.13?ERROR st -7 Antenna off-source! 2006.281.07:49:52.13#trakl#az 274.800 el 64.773 azerr*cos(el) 0.0055 elerr -0.0194 2006.281.07:49:52.13#flagr#flagr/antenna,off-source 2006.281.07:50:00.00:data_valid=on 2006.281.07:50:00.00:midob 2006.281.07:50:00.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:50:00.13?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:50:00.13/onsource/SLEWING 2006.281.07:50:00.13/wx/20.91,1001.3,51 2006.281.07:50:00.19/cable/+6.4867E-03 2006.281.07:50:01.28/va/01,07,usb,yes,32,34 2006.281.07:50:01.28/va/02,06,usb,yes,30,31 2006.281.07:50:01.28/va/03,06,usb,yes,28,28 2006.281.07:50:01.28/va/04,06,usb,yes,31,33 2006.281.07:50:01.28/va/05,07,usb,yes,29,30 2006.281.07:50:01.28/va/06,06,usb,yes,28,27 2006.281.07:50:01.28/va/07,06,usb,yes,28,28 2006.281.07:50:01.28/va/08,06,usb,yes,30,30 2006.281.07:50:01.51/valo/01,532.99,yes,locked 2006.281.07:50:01.51/valo/02,572.99,yes,locked 2006.281.07:50:01.51/valo/03,672.99,yes,locked 2006.281.07:50:01.51/valo/04,832.99,yes,locked 2006.281.07:50:01.51/valo/05,652.99,yes,locked 2006.281.07:50:01.51/valo/06,772.99,yes,locked 2006.281.07:50:01.51/valo/07,832.99,yes,locked 2006.281.07:50:01.51/valo/08,852.99,yes,locked 2006.281.07:50:02.60/vb/01,04,usb,yes,30,29 2006.281.07:50:02.60/vb/02,05,usb,yes,28,29 2006.281.07:50:02.60/vb/03,04,usb,yes,28,32 2006.281.07:50:02.60/vb/04,04,usb,yes,29,29 2006.281.07:50:02.60/vb/05,04,usb,yes,27,31 2006.281.07:50:02.60/vb/06,04,usb,yes,28,31 2006.281.07:50:02.60/vb/07,04,usb,yes,30,30 2006.281.07:50:02.60/vb/08,04,usb,yes,27,31 2006.281.07:50:02.83/vblo/01,632.99,yes,locked 2006.281.07:50:02.83/vblo/02,640.99,yes,locked 2006.281.07:50:02.83/vblo/03,656.99,yes,locked 2006.281.07:50:02.83/vblo/04,712.99,yes,locked 2006.281.07:50:02.83/vblo/05,744.99,yes,locked 2006.281.07:50:02.83/vblo/06,752.99,yes,locked 2006.281.07:50:02.83/vblo/07,734.99,yes,locked 2006.281.07:50:02.83/vblo/08,744.99,yes,locked 2006.281.07:50:02.98/vabw/8 2006.281.07:50:03.13/vbbw/8 2006.281.07:50:03.22/xfe/off,on,12.0 2006.281.07:50:03.59/ifatt/23,28,28,28 2006.281.07:50:04.08/fmout-gps/S +3.07E-07 2006.281.07:50:04.11:!2006.281.07:51:00 2006.281.07:50:05.13#trakl#Source re-acquired 2006.281.07:50:05.13#flagr#flagr/antenna,re-acquired 2006.281.07:50:38.13#trakl#Off source 2006.281.07:50:38.13?ERROR st -7 Antenna off-source! 2006.281.07:50:38.13#trakl#az 274.886 el 64.619 azerr*cos(el) -0.0050 elerr -0.0335 2006.281.07:50:38.13#flagr#flagr/antenna,off-source 2006.281.07:50:45.13#trakl#Source re-acquired 2006.281.07:50:47.13#flagr#flagr/antenna,re-acquired 2006.281.07:50:49.13#trakl#Off source 2006.281.07:50:49.13?ERROR st -7 Antenna off-source! 2006.281.07:50:49.13#trakl#az 274.906 el 64.582 azerr*cos(el) -0.0021 elerr -0.0165 2006.281.07:50:50.13#flagr#flagr/antenna,off-source 2006.281.07:51:00.01:data_valid=off 2006.281.07:51:00.02:postob 2006.281.07:51:00.11/cable/+6.4862E-03 2006.281.07:51:00.11/wx/20.87,1001.3,51 2006.281.07:51:00.13#trakl#Source re-acquired 2006.281.07:51:01.07/fmout-gps/S +3.04E-07 2006.281.07:51:01.07:scan_name=281-0751,k06281,60 2006.281.07:51:01.08:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.281.07:51:01.15#flagr#flagr/antenna,new-source 2006.281.07:51:02.12:checkk5 2006.281.07:51:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:51:03.24/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:51:03.78/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:51:04.40/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:51:04.83/chk_obsdata//k5ts1/T2810750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:51:05.30/chk_obsdata//k5ts2/T2810750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:51:05.73/chk_obsdata//k5ts3/T2810750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:51:06.14/chk_obsdata//k5ts4/T2810750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:51:07.01/k5log//k5ts1_log_newline 2006.281.07:51:07.84/k5log//k5ts2_log_newline 2006.281.07:51:08.64/k5log//k5ts3_log_newline 2006.281.07:51:09.45/k5log//k5ts4_log_newline 2006.281.07:51:09.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:51:09.47:4f8m12a=1 2006.281.07:51:09.47$4f8m12a/echo=on 2006.281.07:51:09.47$4f8m12a/pcalon 2006.281.07:51:09.47$pcalon/"no phase cal control is implemented here 2006.281.07:51:09.47$4f8m12a/"tpicd=stop 2006.281.07:51:09.47$4f8m12a/vc4f8 2006.281.07:51:09.47$vc4f8/valo=1,532.99 2006.281.07:51:09.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:51:09.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:51:09.47#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:09.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:51:09.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:51:09.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:51:09.47#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:51:09.47#ibcon#first serial, iclass 27, count 0 2006.281.07:51:09.47#ibcon#enter sib2, iclass 27, count 0 2006.281.07:51:09.47#ibcon#flushed, iclass 27, count 0 2006.281.07:51:09.47#ibcon#about to write, iclass 27, count 0 2006.281.07:51:09.47#ibcon#wrote, iclass 27, count 0 2006.281.07:51:09.47#ibcon#about to read 3, iclass 27, count 0 2006.281.07:51:09.49#ibcon#read 3, iclass 27, count 0 2006.281.07:51:09.49#ibcon#about to read 4, iclass 27, count 0 2006.281.07:51:09.49#ibcon#read 4, iclass 27, count 0 2006.281.07:51:09.49#ibcon#about to read 5, iclass 27, count 0 2006.281.07:51:09.49#ibcon#read 5, iclass 27, count 0 2006.281.07:51:09.49#ibcon#about to read 6, iclass 27, count 0 2006.281.07:51:09.49#ibcon#read 6, iclass 27, count 0 2006.281.07:51:09.49#ibcon#end of sib2, iclass 27, count 0 2006.281.07:51:09.49#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:51:09.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:51:09.49#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:51:09.49#ibcon#*before write, iclass 27, count 0 2006.281.07:51:09.49#ibcon#enter sib2, iclass 27, count 0 2006.281.07:51:09.49#ibcon#flushed, iclass 27, count 0 2006.281.07:51:09.49#ibcon#about to write, iclass 27, count 0 2006.281.07:51:09.49#ibcon#wrote, iclass 27, count 0 2006.281.07:51:09.49#ibcon#about to read 3, iclass 27, count 0 2006.281.07:51:09.55#ibcon#read 3, iclass 27, count 0 2006.281.07:51:09.55#ibcon#about to read 4, iclass 27, count 0 2006.281.07:51:09.55#ibcon#read 4, iclass 27, count 0 2006.281.07:51:09.55#ibcon#about to read 5, iclass 27, count 0 2006.281.07:51:09.55#ibcon#read 5, iclass 27, count 0 2006.281.07:51:09.55#ibcon#about to read 6, iclass 27, count 0 2006.281.07:51:09.55#ibcon#read 6, iclass 27, count 0 2006.281.07:51:09.55#ibcon#end of sib2, iclass 27, count 0 2006.281.07:51:09.55#ibcon#*after write, iclass 27, count 0 2006.281.07:51:09.55#ibcon#*before return 0, iclass 27, count 0 2006.281.07:51:09.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:51:09.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:51:09.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:51:09.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:51:09.55$vc4f8/va=1,7 2006.281.07:51:09.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:51:09.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:51:09.55#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:09.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:51:09.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:51:09.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:51:09.55#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:51:09.55#ibcon#first serial, iclass 29, count 2 2006.281.07:51:09.55#ibcon#enter sib2, iclass 29, count 2 2006.281.07:51:09.55#ibcon#flushed, iclass 29, count 2 2006.281.07:51:09.55#ibcon#about to write, iclass 29, count 2 2006.281.07:51:09.55#ibcon#wrote, iclass 29, count 2 2006.281.07:51:09.55#ibcon#about to read 3, iclass 29, count 2 2006.281.07:51:09.56#ibcon#read 3, iclass 29, count 2 2006.281.07:51:09.56#ibcon#about to read 4, iclass 29, count 2 2006.281.07:51:09.56#ibcon#read 4, iclass 29, count 2 2006.281.07:51:09.56#ibcon#about to read 5, iclass 29, count 2 2006.281.07:51:09.56#ibcon#read 5, iclass 29, count 2 2006.281.07:51:09.56#ibcon#about to read 6, iclass 29, count 2 2006.281.07:51:09.56#ibcon#read 6, iclass 29, count 2 2006.281.07:51:09.56#ibcon#end of sib2, iclass 29, count 2 2006.281.07:51:09.56#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:51:09.56#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:51:09.56#ibcon#[25=AT01-07\r\n] 2006.281.07:51:09.56#ibcon#*before write, iclass 29, count 2 2006.281.07:51:09.56#ibcon#enter sib2, iclass 29, count 2 2006.281.07:51:09.56#ibcon#flushed, iclass 29, count 2 2006.281.07:51:09.56#ibcon#about to write, iclass 29, count 2 2006.281.07:51:09.56#ibcon#wrote, iclass 29, count 2 2006.281.07:51:09.56#ibcon#about to read 3, iclass 29, count 2 2006.281.07:51:09.59#ibcon#read 3, iclass 29, count 2 2006.281.07:51:09.59#ibcon#about to read 4, iclass 29, count 2 2006.281.07:51:09.59#ibcon#read 4, iclass 29, count 2 2006.281.07:51:09.59#ibcon#about to read 5, iclass 29, count 2 2006.281.07:51:09.59#ibcon#read 5, iclass 29, count 2 2006.281.07:51:09.59#ibcon#about to read 6, iclass 29, count 2 2006.281.07:51:09.59#ibcon#read 6, iclass 29, count 2 2006.281.07:51:09.59#ibcon#end of sib2, iclass 29, count 2 2006.281.07:51:09.59#ibcon#*after write, iclass 29, count 2 2006.281.07:51:09.59#ibcon#*before return 0, iclass 29, count 2 2006.281.07:51:09.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:51:09.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:51:09.59#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:51:09.59#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:09.59#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:51:09.71#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:51:09.71#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:51:09.71#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:51:09.71#ibcon#first serial, iclass 29, count 0 2006.281.07:51:09.71#ibcon#enter sib2, iclass 29, count 0 2006.281.07:51:09.71#ibcon#flushed, iclass 29, count 0 2006.281.07:51:09.71#ibcon#about to write, iclass 29, count 0 2006.281.07:51:09.71#ibcon#wrote, iclass 29, count 0 2006.281.07:51:09.71#ibcon#about to read 3, iclass 29, count 0 2006.281.07:51:09.73#ibcon#read 3, iclass 29, count 0 2006.281.07:51:09.73#ibcon#about to read 4, iclass 29, count 0 2006.281.07:51:09.73#ibcon#read 4, iclass 29, count 0 2006.281.07:51:09.73#ibcon#about to read 5, iclass 29, count 0 2006.281.07:51:09.73#ibcon#read 5, iclass 29, count 0 2006.281.07:51:09.73#ibcon#about to read 6, iclass 29, count 0 2006.281.07:51:09.73#ibcon#read 6, iclass 29, count 0 2006.281.07:51:09.73#ibcon#end of sib2, iclass 29, count 0 2006.281.07:51:09.73#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:51:09.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:51:09.73#ibcon#[25=USB\r\n] 2006.281.07:51:09.73#ibcon#*before write, iclass 29, count 0 2006.281.07:51:09.73#ibcon#enter sib2, iclass 29, count 0 2006.281.07:51:09.73#ibcon#flushed, iclass 29, count 0 2006.281.07:51:09.73#ibcon#about to write, iclass 29, count 0 2006.281.07:51:09.73#ibcon#wrote, iclass 29, count 0 2006.281.07:51:09.73#ibcon#about to read 3, iclass 29, count 0 2006.281.07:51:09.76#ibcon#read 3, iclass 29, count 0 2006.281.07:51:09.76#ibcon#about to read 4, iclass 29, count 0 2006.281.07:51:09.76#ibcon#read 4, iclass 29, count 0 2006.281.07:51:09.76#ibcon#about to read 5, iclass 29, count 0 2006.281.07:51:09.76#ibcon#read 5, iclass 29, count 0 2006.281.07:51:09.76#ibcon#about to read 6, iclass 29, count 0 2006.281.07:51:09.76#ibcon#read 6, iclass 29, count 0 2006.281.07:51:09.76#ibcon#end of sib2, iclass 29, count 0 2006.281.07:51:09.76#ibcon#*after write, iclass 29, count 0 2006.281.07:51:09.76#ibcon#*before return 0, iclass 29, count 0 2006.281.07:51:09.76#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:51:09.76#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:51:09.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:51:09.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:51:09.76$vc4f8/valo=2,572.99 2006.281.07:51:09.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:51:09.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:51:09.76#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:09.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:51:09.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:51:09.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:51:09.76#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:51:09.76#ibcon#first serial, iclass 31, count 0 2006.281.07:51:09.76#ibcon#enter sib2, iclass 31, count 0 2006.281.07:51:09.76#ibcon#flushed, iclass 31, count 0 2006.281.07:51:09.76#ibcon#about to write, iclass 31, count 0 2006.281.07:51:09.76#ibcon#wrote, iclass 31, count 0 2006.281.07:51:09.76#ibcon#about to read 3, iclass 31, count 0 2006.281.07:51:09.78#ibcon#read 3, iclass 31, count 0 2006.281.07:51:09.78#ibcon#about to read 4, iclass 31, count 0 2006.281.07:51:09.78#ibcon#read 4, iclass 31, count 0 2006.281.07:51:09.78#ibcon#about to read 5, iclass 31, count 0 2006.281.07:51:09.78#ibcon#read 5, iclass 31, count 0 2006.281.07:51:09.78#ibcon#about to read 6, iclass 31, count 0 2006.281.07:51:09.78#ibcon#read 6, iclass 31, count 0 2006.281.07:51:09.78#ibcon#end of sib2, iclass 31, count 0 2006.281.07:51:09.78#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:51:09.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:51:09.78#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:51:09.78#ibcon#*before write, iclass 31, count 0 2006.281.07:51:09.78#ibcon#enter sib2, iclass 31, count 0 2006.281.07:51:09.78#ibcon#flushed, iclass 31, count 0 2006.281.07:51:09.78#ibcon#about to write, iclass 31, count 0 2006.281.07:51:09.78#ibcon#wrote, iclass 31, count 0 2006.281.07:51:09.78#ibcon#about to read 3, iclass 31, count 0 2006.281.07:51:09.82#ibcon#read 3, iclass 31, count 0 2006.281.07:51:09.82#ibcon#about to read 4, iclass 31, count 0 2006.281.07:51:09.82#ibcon#read 4, iclass 31, count 0 2006.281.07:51:09.82#ibcon#about to read 5, iclass 31, count 0 2006.281.07:51:09.82#ibcon#read 5, iclass 31, count 0 2006.281.07:51:09.82#ibcon#about to read 6, iclass 31, count 0 2006.281.07:51:09.82#ibcon#read 6, iclass 31, count 0 2006.281.07:51:09.82#ibcon#end of sib2, iclass 31, count 0 2006.281.07:51:09.82#ibcon#*after write, iclass 31, count 0 2006.281.07:51:09.82#ibcon#*before return 0, iclass 31, count 0 2006.281.07:51:09.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:51:09.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:51:09.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:51:09.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:51:09.82$vc4f8/va=2,6 2006.281.07:51:09.82#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:51:09.82#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:51:09.82#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:09.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:51:09.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:51:09.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:51:09.88#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:51:09.88#ibcon#first serial, iclass 33, count 2 2006.281.07:51:09.88#ibcon#enter sib2, iclass 33, count 2 2006.281.07:51:09.88#ibcon#flushed, iclass 33, count 2 2006.281.07:51:09.88#ibcon#about to write, iclass 33, count 2 2006.281.07:51:09.88#ibcon#wrote, iclass 33, count 2 2006.281.07:51:09.88#ibcon#about to read 3, iclass 33, count 2 2006.281.07:51:09.91#ibcon#read 3, iclass 33, count 2 2006.281.07:51:09.91#ibcon#about to read 4, iclass 33, count 2 2006.281.07:51:09.91#ibcon#read 4, iclass 33, count 2 2006.281.07:51:09.91#ibcon#about to read 5, iclass 33, count 2 2006.281.07:51:09.91#ibcon#read 5, iclass 33, count 2 2006.281.07:51:09.91#ibcon#about to read 6, iclass 33, count 2 2006.281.07:51:09.91#ibcon#read 6, iclass 33, count 2 2006.281.07:51:09.91#ibcon#end of sib2, iclass 33, count 2 2006.281.07:51:09.91#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:51:09.91#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:51:09.91#ibcon#[25=AT02-06\r\n] 2006.281.07:51:09.91#ibcon#*before write, iclass 33, count 2 2006.281.07:51:09.91#ibcon#enter sib2, iclass 33, count 2 2006.281.07:51:09.91#ibcon#flushed, iclass 33, count 2 2006.281.07:51:09.91#ibcon#about to write, iclass 33, count 2 2006.281.07:51:09.91#ibcon#wrote, iclass 33, count 2 2006.281.07:51:09.91#ibcon#about to read 3, iclass 33, count 2 2006.281.07:51:09.94#ibcon#read 3, iclass 33, count 2 2006.281.07:51:09.94#ibcon#about to read 4, iclass 33, count 2 2006.281.07:51:09.94#ibcon#read 4, iclass 33, count 2 2006.281.07:51:09.94#ibcon#about to read 5, iclass 33, count 2 2006.281.07:51:09.94#ibcon#read 5, iclass 33, count 2 2006.281.07:51:09.94#ibcon#about to read 6, iclass 33, count 2 2006.281.07:51:09.94#ibcon#read 6, iclass 33, count 2 2006.281.07:51:09.94#ibcon#end of sib2, iclass 33, count 2 2006.281.07:51:09.94#ibcon#*after write, iclass 33, count 2 2006.281.07:51:09.94#ibcon#*before return 0, iclass 33, count 2 2006.281.07:51:09.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:51:09.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:51:09.94#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:51:09.94#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:09.94#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:51:10.06#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:51:10.06#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:51:10.06#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:51:10.06#ibcon#first serial, iclass 33, count 0 2006.281.07:51:10.06#ibcon#enter sib2, iclass 33, count 0 2006.281.07:51:10.06#ibcon#flushed, iclass 33, count 0 2006.281.07:51:10.06#ibcon#about to write, iclass 33, count 0 2006.281.07:51:10.06#ibcon#wrote, iclass 33, count 0 2006.281.07:51:10.06#ibcon#about to read 3, iclass 33, count 0 2006.281.07:51:10.08#ibcon#read 3, iclass 33, count 0 2006.281.07:51:10.08#ibcon#about to read 4, iclass 33, count 0 2006.281.07:51:10.08#ibcon#read 4, iclass 33, count 0 2006.281.07:51:10.08#ibcon#about to read 5, iclass 33, count 0 2006.281.07:51:10.08#ibcon#read 5, iclass 33, count 0 2006.281.07:51:10.08#ibcon#about to read 6, iclass 33, count 0 2006.281.07:51:10.08#ibcon#read 6, iclass 33, count 0 2006.281.07:51:10.08#ibcon#end of sib2, iclass 33, count 0 2006.281.07:51:10.08#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:51:10.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:51:10.08#ibcon#[25=USB\r\n] 2006.281.07:51:10.08#ibcon#*before write, iclass 33, count 0 2006.281.07:51:10.08#ibcon#enter sib2, iclass 33, count 0 2006.281.07:51:10.08#ibcon#flushed, iclass 33, count 0 2006.281.07:51:10.08#ibcon#about to write, iclass 33, count 0 2006.281.07:51:10.08#ibcon#wrote, iclass 33, count 0 2006.281.07:51:10.08#ibcon#about to read 3, iclass 33, count 0 2006.281.07:51:10.11#ibcon#read 3, iclass 33, count 0 2006.281.07:51:10.11#ibcon#about to read 4, iclass 33, count 0 2006.281.07:51:10.11#ibcon#read 4, iclass 33, count 0 2006.281.07:51:10.11#ibcon#about to read 5, iclass 33, count 0 2006.281.07:51:10.11#ibcon#read 5, iclass 33, count 0 2006.281.07:51:10.11#ibcon#about to read 6, iclass 33, count 0 2006.281.07:51:10.11#ibcon#read 6, iclass 33, count 0 2006.281.07:51:10.11#ibcon#end of sib2, iclass 33, count 0 2006.281.07:51:10.11#ibcon#*after write, iclass 33, count 0 2006.281.07:51:10.11#ibcon#*before return 0, iclass 33, count 0 2006.281.07:51:10.11#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:51:10.11#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:51:10.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:51:10.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:51:10.11$vc4f8/valo=3,672.99 2006.281.07:51:10.11#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:51:10.11#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:51:10.11#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:10.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:10.11#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:10.11#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:10.11#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:51:10.11#ibcon#first serial, iclass 35, count 0 2006.281.07:51:10.11#ibcon#enter sib2, iclass 35, count 0 2006.281.07:51:10.11#ibcon#flushed, iclass 35, count 0 2006.281.07:51:10.11#ibcon#about to write, iclass 35, count 0 2006.281.07:51:10.11#ibcon#wrote, iclass 35, count 0 2006.281.07:51:10.11#ibcon#about to read 3, iclass 35, count 0 2006.281.07:51:10.13#ibcon#read 3, iclass 35, count 0 2006.281.07:51:10.14#ibcon#about to read 4, iclass 35, count 0 2006.281.07:51:10.14#ibcon#read 4, iclass 35, count 0 2006.281.07:51:10.14#ibcon#about to read 5, iclass 35, count 0 2006.281.07:51:10.14#ibcon#read 5, iclass 35, count 0 2006.281.07:51:10.14#ibcon#about to read 6, iclass 35, count 0 2006.281.07:51:10.14#ibcon#read 6, iclass 35, count 0 2006.281.07:51:10.14#ibcon#end of sib2, iclass 35, count 0 2006.281.07:51:10.14#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:51:10.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:51:10.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:51:10.14#ibcon#*before write, iclass 35, count 0 2006.281.07:51:10.14#ibcon#enter sib2, iclass 35, count 0 2006.281.07:51:10.14#ibcon#flushed, iclass 35, count 0 2006.281.07:51:10.14#ibcon#about to write, iclass 35, count 0 2006.281.07:51:10.14#ibcon#wrote, iclass 35, count 0 2006.281.07:51:10.14#ibcon#about to read 3, iclass 35, count 0 2006.281.07:51:10.17#ibcon#read 3, iclass 35, count 0 2006.281.07:51:10.17#ibcon#about to read 4, iclass 35, count 0 2006.281.07:51:10.17#ibcon#read 4, iclass 35, count 0 2006.281.07:51:10.17#ibcon#about to read 5, iclass 35, count 0 2006.281.07:51:10.17#ibcon#read 5, iclass 35, count 0 2006.281.07:51:10.17#ibcon#about to read 6, iclass 35, count 0 2006.281.07:51:10.17#ibcon#read 6, iclass 35, count 0 2006.281.07:51:10.17#ibcon#end of sib2, iclass 35, count 0 2006.281.07:51:10.17#ibcon#*after write, iclass 35, count 0 2006.281.07:51:10.17#ibcon#*before return 0, iclass 35, count 0 2006.281.07:51:10.17#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:10.17#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:10.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:51:10.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:51:10.17$vc4f8/va=3,6 2006.281.07:51:10.17#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:51:10.17#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:51:10.17#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:10.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:10.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:10.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:10.23#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:51:10.23#ibcon#first serial, iclass 37, count 2 2006.281.07:51:10.23#ibcon#enter sib2, iclass 37, count 2 2006.281.07:51:10.23#ibcon#flushed, iclass 37, count 2 2006.281.07:51:10.23#ibcon#about to write, iclass 37, count 2 2006.281.07:51:10.23#ibcon#wrote, iclass 37, count 2 2006.281.07:51:10.23#ibcon#about to read 3, iclass 37, count 2 2006.281.07:51:10.25#ibcon#read 3, iclass 37, count 2 2006.281.07:51:10.25#ibcon#about to read 4, iclass 37, count 2 2006.281.07:51:10.25#ibcon#read 4, iclass 37, count 2 2006.281.07:51:10.25#ibcon#about to read 5, iclass 37, count 2 2006.281.07:51:10.25#ibcon#read 5, iclass 37, count 2 2006.281.07:51:10.25#ibcon#about to read 6, iclass 37, count 2 2006.281.07:51:10.25#ibcon#read 6, iclass 37, count 2 2006.281.07:51:10.25#ibcon#end of sib2, iclass 37, count 2 2006.281.07:51:10.25#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:51:10.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:51:10.25#ibcon#[25=AT03-06\r\n] 2006.281.07:51:10.25#ibcon#*before write, iclass 37, count 2 2006.281.07:51:10.25#ibcon#enter sib2, iclass 37, count 2 2006.281.07:51:10.25#ibcon#flushed, iclass 37, count 2 2006.281.07:51:10.25#ibcon#about to write, iclass 37, count 2 2006.281.07:51:10.25#ibcon#wrote, iclass 37, count 2 2006.281.07:51:10.25#ibcon#about to read 3, iclass 37, count 2 2006.281.07:51:10.28#ibcon#read 3, iclass 37, count 2 2006.281.07:51:10.28#ibcon#about to read 4, iclass 37, count 2 2006.281.07:51:10.28#ibcon#read 4, iclass 37, count 2 2006.281.07:51:10.28#ibcon#about to read 5, iclass 37, count 2 2006.281.07:51:10.28#ibcon#read 5, iclass 37, count 2 2006.281.07:51:10.28#ibcon#about to read 6, iclass 37, count 2 2006.281.07:51:10.28#ibcon#read 6, iclass 37, count 2 2006.281.07:51:10.28#ibcon#end of sib2, iclass 37, count 2 2006.281.07:51:10.28#ibcon#*after write, iclass 37, count 2 2006.281.07:51:10.28#ibcon#*before return 0, iclass 37, count 2 2006.281.07:51:10.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:10.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:10.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:51:10.28#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:10.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:10.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:10.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:10.40#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:51:10.40#ibcon#first serial, iclass 37, count 0 2006.281.07:51:10.40#ibcon#enter sib2, iclass 37, count 0 2006.281.07:51:10.40#ibcon#flushed, iclass 37, count 0 2006.281.07:51:10.40#ibcon#about to write, iclass 37, count 0 2006.281.07:51:10.40#ibcon#wrote, iclass 37, count 0 2006.281.07:51:10.40#ibcon#about to read 3, iclass 37, count 0 2006.281.07:51:10.42#ibcon#read 3, iclass 37, count 0 2006.281.07:51:10.42#ibcon#about to read 4, iclass 37, count 0 2006.281.07:51:10.42#ibcon#read 4, iclass 37, count 0 2006.281.07:51:10.42#ibcon#about to read 5, iclass 37, count 0 2006.281.07:51:10.42#ibcon#read 5, iclass 37, count 0 2006.281.07:51:10.42#ibcon#about to read 6, iclass 37, count 0 2006.281.07:51:10.42#ibcon#read 6, iclass 37, count 0 2006.281.07:51:10.42#ibcon#end of sib2, iclass 37, count 0 2006.281.07:51:10.42#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:51:10.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:51:10.42#ibcon#[25=USB\r\n] 2006.281.07:51:10.42#ibcon#*before write, iclass 37, count 0 2006.281.07:51:10.42#ibcon#enter sib2, iclass 37, count 0 2006.281.07:51:10.42#ibcon#flushed, iclass 37, count 0 2006.281.07:51:10.42#ibcon#about to write, iclass 37, count 0 2006.281.07:51:10.42#ibcon#wrote, iclass 37, count 0 2006.281.07:51:10.42#ibcon#about to read 3, iclass 37, count 0 2006.281.07:51:10.45#ibcon#read 3, iclass 37, count 0 2006.281.07:51:10.45#ibcon#about to read 4, iclass 37, count 0 2006.281.07:51:10.45#ibcon#read 4, iclass 37, count 0 2006.281.07:51:10.45#ibcon#about to read 5, iclass 37, count 0 2006.281.07:51:10.45#ibcon#read 5, iclass 37, count 0 2006.281.07:51:10.45#ibcon#about to read 6, iclass 37, count 0 2006.281.07:51:10.45#ibcon#read 6, iclass 37, count 0 2006.281.07:51:10.45#ibcon#end of sib2, iclass 37, count 0 2006.281.07:51:10.45#ibcon#*after write, iclass 37, count 0 2006.281.07:51:10.45#ibcon#*before return 0, iclass 37, count 0 2006.281.07:51:10.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:10.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:10.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:51:10.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:51:10.45$vc4f8/valo=4,832.99 2006.281.07:51:10.45#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:51:10.45#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:51:10.45#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:10.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:10.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:10.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:10.45#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:51:10.45#ibcon#first serial, iclass 39, count 0 2006.281.07:51:10.45#ibcon#enter sib2, iclass 39, count 0 2006.281.07:51:10.45#ibcon#flushed, iclass 39, count 0 2006.281.07:51:10.45#ibcon#about to write, iclass 39, count 0 2006.281.07:51:10.45#ibcon#wrote, iclass 39, count 0 2006.281.07:51:10.45#ibcon#about to read 3, iclass 39, count 0 2006.281.07:51:10.47#ibcon#read 3, iclass 39, count 0 2006.281.07:51:10.47#ibcon#about to read 4, iclass 39, count 0 2006.281.07:51:10.47#ibcon#read 4, iclass 39, count 0 2006.281.07:51:10.47#ibcon#about to read 5, iclass 39, count 0 2006.281.07:51:10.47#ibcon#read 5, iclass 39, count 0 2006.281.07:51:10.47#ibcon#about to read 6, iclass 39, count 0 2006.281.07:51:10.47#ibcon#read 6, iclass 39, count 0 2006.281.07:51:10.47#ibcon#end of sib2, iclass 39, count 0 2006.281.07:51:10.47#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:51:10.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:51:10.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:51:10.47#ibcon#*before write, iclass 39, count 0 2006.281.07:51:10.47#ibcon#enter sib2, iclass 39, count 0 2006.281.07:51:10.47#ibcon#flushed, iclass 39, count 0 2006.281.07:51:10.47#ibcon#about to write, iclass 39, count 0 2006.281.07:51:10.47#ibcon#wrote, iclass 39, count 0 2006.281.07:51:10.47#ibcon#about to read 3, iclass 39, count 0 2006.281.07:51:10.51#ibcon#read 3, iclass 39, count 0 2006.281.07:51:10.51#ibcon#about to read 4, iclass 39, count 0 2006.281.07:51:10.51#ibcon#read 4, iclass 39, count 0 2006.281.07:51:10.51#ibcon#about to read 5, iclass 39, count 0 2006.281.07:51:10.51#ibcon#read 5, iclass 39, count 0 2006.281.07:51:10.51#ibcon#about to read 6, iclass 39, count 0 2006.281.07:51:10.51#ibcon#read 6, iclass 39, count 0 2006.281.07:51:10.51#ibcon#end of sib2, iclass 39, count 0 2006.281.07:51:10.51#ibcon#*after write, iclass 39, count 0 2006.281.07:51:10.51#ibcon#*before return 0, iclass 39, count 0 2006.281.07:51:10.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:10.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:10.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:51:10.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:51:10.51$vc4f8/va=4,6 2006.281.07:51:10.51#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:51:10.51#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:51:10.51#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:10.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:10.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:10.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:10.57#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:51:10.57#ibcon#first serial, iclass 3, count 2 2006.281.07:51:10.57#ibcon#enter sib2, iclass 3, count 2 2006.281.07:51:10.57#ibcon#flushed, iclass 3, count 2 2006.281.07:51:10.57#ibcon#about to write, iclass 3, count 2 2006.281.07:51:10.57#ibcon#wrote, iclass 3, count 2 2006.281.07:51:10.57#ibcon#about to read 3, iclass 3, count 2 2006.281.07:51:10.60#ibcon#read 3, iclass 3, count 2 2006.281.07:51:10.60#ibcon#about to read 4, iclass 3, count 2 2006.281.07:51:10.60#ibcon#read 4, iclass 3, count 2 2006.281.07:51:10.60#ibcon#about to read 5, iclass 3, count 2 2006.281.07:51:10.60#ibcon#read 5, iclass 3, count 2 2006.281.07:51:10.60#ibcon#about to read 6, iclass 3, count 2 2006.281.07:51:10.60#ibcon#read 6, iclass 3, count 2 2006.281.07:51:10.60#ibcon#end of sib2, iclass 3, count 2 2006.281.07:51:10.60#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:51:10.60#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:51:10.60#ibcon#[25=AT04-06\r\n] 2006.281.07:51:10.60#ibcon#*before write, iclass 3, count 2 2006.281.07:51:10.60#ibcon#enter sib2, iclass 3, count 2 2006.281.07:51:10.60#ibcon#flushed, iclass 3, count 2 2006.281.07:51:10.60#ibcon#about to write, iclass 3, count 2 2006.281.07:51:10.60#ibcon#wrote, iclass 3, count 2 2006.281.07:51:10.60#ibcon#about to read 3, iclass 3, count 2 2006.281.07:51:10.63#ibcon#read 3, iclass 3, count 2 2006.281.07:51:10.63#ibcon#about to read 4, iclass 3, count 2 2006.281.07:51:10.63#ibcon#read 4, iclass 3, count 2 2006.281.07:51:10.63#ibcon#about to read 5, iclass 3, count 2 2006.281.07:51:10.63#ibcon#read 5, iclass 3, count 2 2006.281.07:51:10.63#ibcon#about to read 6, iclass 3, count 2 2006.281.07:51:10.63#ibcon#read 6, iclass 3, count 2 2006.281.07:51:10.63#ibcon#end of sib2, iclass 3, count 2 2006.281.07:51:10.63#ibcon#*after write, iclass 3, count 2 2006.281.07:51:10.63#ibcon#*before return 0, iclass 3, count 2 2006.281.07:51:10.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:10.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:10.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:51:10.63#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:10.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:10.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:10.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:10.75#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:51:10.75#ibcon#first serial, iclass 3, count 0 2006.281.07:51:10.75#ibcon#enter sib2, iclass 3, count 0 2006.281.07:51:10.75#ibcon#flushed, iclass 3, count 0 2006.281.07:51:10.75#ibcon#about to write, iclass 3, count 0 2006.281.07:51:10.75#ibcon#wrote, iclass 3, count 0 2006.281.07:51:10.75#ibcon#about to read 3, iclass 3, count 0 2006.281.07:51:10.77#ibcon#read 3, iclass 3, count 0 2006.281.07:51:10.77#ibcon#about to read 4, iclass 3, count 0 2006.281.07:51:10.77#ibcon#read 4, iclass 3, count 0 2006.281.07:51:10.77#ibcon#about to read 5, iclass 3, count 0 2006.281.07:51:10.77#ibcon#read 5, iclass 3, count 0 2006.281.07:51:10.77#ibcon#about to read 6, iclass 3, count 0 2006.281.07:51:10.77#ibcon#read 6, iclass 3, count 0 2006.281.07:51:10.77#ibcon#end of sib2, iclass 3, count 0 2006.281.07:51:10.77#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:51:10.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:51:10.77#ibcon#[25=USB\r\n] 2006.281.07:51:10.77#ibcon#*before write, iclass 3, count 0 2006.281.07:51:10.77#ibcon#enter sib2, iclass 3, count 0 2006.281.07:51:10.77#ibcon#flushed, iclass 3, count 0 2006.281.07:51:10.77#ibcon#about to write, iclass 3, count 0 2006.281.07:51:10.77#ibcon#wrote, iclass 3, count 0 2006.281.07:51:10.77#ibcon#about to read 3, iclass 3, count 0 2006.281.07:51:10.80#ibcon#read 3, iclass 3, count 0 2006.281.07:51:10.80#ibcon#about to read 4, iclass 3, count 0 2006.281.07:51:10.80#ibcon#read 4, iclass 3, count 0 2006.281.07:51:10.80#ibcon#about to read 5, iclass 3, count 0 2006.281.07:51:10.80#ibcon#read 5, iclass 3, count 0 2006.281.07:51:10.80#ibcon#about to read 6, iclass 3, count 0 2006.281.07:51:10.80#ibcon#read 6, iclass 3, count 0 2006.281.07:51:10.80#ibcon#end of sib2, iclass 3, count 0 2006.281.07:51:10.80#ibcon#*after write, iclass 3, count 0 2006.281.07:51:10.80#ibcon#*before return 0, iclass 3, count 0 2006.281.07:51:10.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:10.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:10.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:51:10.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:51:10.80$vc4f8/valo=5,652.99 2006.281.07:51:10.80#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:51:10.80#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:51:10.80#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:10.80#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:10.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:10.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:10.80#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:51:10.80#ibcon#first serial, iclass 5, count 0 2006.281.07:51:10.80#ibcon#enter sib2, iclass 5, count 0 2006.281.07:51:10.80#ibcon#flushed, iclass 5, count 0 2006.281.07:51:10.80#ibcon#about to write, iclass 5, count 0 2006.281.07:51:10.80#ibcon#wrote, iclass 5, count 0 2006.281.07:51:10.80#ibcon#about to read 3, iclass 5, count 0 2006.281.07:51:10.82#ibcon#read 3, iclass 5, count 0 2006.281.07:51:10.82#ibcon#about to read 4, iclass 5, count 0 2006.281.07:51:10.82#ibcon#read 4, iclass 5, count 0 2006.281.07:51:10.82#ibcon#about to read 5, iclass 5, count 0 2006.281.07:51:10.82#ibcon#read 5, iclass 5, count 0 2006.281.07:51:10.82#ibcon#about to read 6, iclass 5, count 0 2006.281.07:51:10.82#ibcon#read 6, iclass 5, count 0 2006.281.07:51:10.82#ibcon#end of sib2, iclass 5, count 0 2006.281.07:51:10.82#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:51:10.82#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:51:10.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:51:10.82#ibcon#*before write, iclass 5, count 0 2006.281.07:51:10.82#ibcon#enter sib2, iclass 5, count 0 2006.281.07:51:10.82#ibcon#flushed, iclass 5, count 0 2006.281.07:51:10.82#ibcon#about to write, iclass 5, count 0 2006.281.07:51:10.82#ibcon#wrote, iclass 5, count 0 2006.281.07:51:10.82#ibcon#about to read 3, iclass 5, count 0 2006.281.07:51:10.86#ibcon#read 3, iclass 5, count 0 2006.281.07:51:10.86#ibcon#about to read 4, iclass 5, count 0 2006.281.07:51:10.86#ibcon#read 4, iclass 5, count 0 2006.281.07:51:10.86#ibcon#about to read 5, iclass 5, count 0 2006.281.07:51:10.86#ibcon#read 5, iclass 5, count 0 2006.281.07:51:10.86#ibcon#about to read 6, iclass 5, count 0 2006.281.07:51:10.86#ibcon#read 6, iclass 5, count 0 2006.281.07:51:10.86#ibcon#end of sib2, iclass 5, count 0 2006.281.07:51:10.86#ibcon#*after write, iclass 5, count 0 2006.281.07:51:10.86#ibcon#*before return 0, iclass 5, count 0 2006.281.07:51:10.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:10.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:10.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:51:10.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:51:10.87$vc4f8/va=5,7 2006.281.07:51:10.87#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:51:10.87#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:51:10.87#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:10.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:10.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:10.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:10.92#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:51:10.92#ibcon#first serial, iclass 7, count 2 2006.281.07:51:10.92#ibcon#enter sib2, iclass 7, count 2 2006.281.07:51:10.92#ibcon#flushed, iclass 7, count 2 2006.281.07:51:10.92#ibcon#about to write, iclass 7, count 2 2006.281.07:51:10.92#ibcon#wrote, iclass 7, count 2 2006.281.07:51:10.92#ibcon#about to read 3, iclass 7, count 2 2006.281.07:51:10.94#ibcon#read 3, iclass 7, count 2 2006.281.07:51:10.94#ibcon#about to read 4, iclass 7, count 2 2006.281.07:51:10.94#ibcon#read 4, iclass 7, count 2 2006.281.07:51:10.94#ibcon#about to read 5, iclass 7, count 2 2006.281.07:51:10.94#ibcon#read 5, iclass 7, count 2 2006.281.07:51:10.94#ibcon#about to read 6, iclass 7, count 2 2006.281.07:51:10.94#ibcon#read 6, iclass 7, count 2 2006.281.07:51:10.94#ibcon#end of sib2, iclass 7, count 2 2006.281.07:51:10.94#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:51:10.94#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:51:10.94#ibcon#[25=AT05-07\r\n] 2006.281.07:51:10.94#ibcon#*before write, iclass 7, count 2 2006.281.07:51:10.94#ibcon#enter sib2, iclass 7, count 2 2006.281.07:51:10.94#ibcon#flushed, iclass 7, count 2 2006.281.07:51:10.94#ibcon#about to write, iclass 7, count 2 2006.281.07:51:10.94#ibcon#wrote, iclass 7, count 2 2006.281.07:51:10.94#ibcon#about to read 3, iclass 7, count 2 2006.281.07:51:10.97#ibcon#read 3, iclass 7, count 2 2006.281.07:51:10.97#ibcon#about to read 4, iclass 7, count 2 2006.281.07:51:10.97#ibcon#read 4, iclass 7, count 2 2006.281.07:51:10.97#ibcon#about to read 5, iclass 7, count 2 2006.281.07:51:10.97#ibcon#read 5, iclass 7, count 2 2006.281.07:51:10.97#ibcon#about to read 6, iclass 7, count 2 2006.281.07:51:10.97#ibcon#read 6, iclass 7, count 2 2006.281.07:51:10.97#ibcon#end of sib2, iclass 7, count 2 2006.281.07:51:10.97#ibcon#*after write, iclass 7, count 2 2006.281.07:51:10.97#ibcon#*before return 0, iclass 7, count 2 2006.281.07:51:10.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:10.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:10.97#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:51:10.97#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:10.97#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:11.09#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:11.09#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:11.09#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:51:11.09#ibcon#first serial, iclass 7, count 0 2006.281.07:51:11.09#ibcon#enter sib2, iclass 7, count 0 2006.281.07:51:11.09#ibcon#flushed, iclass 7, count 0 2006.281.07:51:11.09#ibcon#about to write, iclass 7, count 0 2006.281.07:51:11.09#ibcon#wrote, iclass 7, count 0 2006.281.07:51:11.09#ibcon#about to read 3, iclass 7, count 0 2006.281.07:51:11.11#ibcon#read 3, iclass 7, count 0 2006.281.07:51:11.11#ibcon#about to read 4, iclass 7, count 0 2006.281.07:51:11.11#ibcon#read 4, iclass 7, count 0 2006.281.07:51:11.11#ibcon#about to read 5, iclass 7, count 0 2006.281.07:51:11.11#ibcon#read 5, iclass 7, count 0 2006.281.07:51:11.11#ibcon#about to read 6, iclass 7, count 0 2006.281.07:51:11.11#ibcon#read 6, iclass 7, count 0 2006.281.07:51:11.11#ibcon#end of sib2, iclass 7, count 0 2006.281.07:51:11.11#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:51:11.11#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:51:11.11#ibcon#[25=USB\r\n] 2006.281.07:51:11.11#ibcon#*before write, iclass 7, count 0 2006.281.07:51:11.11#ibcon#enter sib2, iclass 7, count 0 2006.281.07:51:11.11#ibcon#flushed, iclass 7, count 0 2006.281.07:51:11.11#ibcon#about to write, iclass 7, count 0 2006.281.07:51:11.11#ibcon#wrote, iclass 7, count 0 2006.281.07:51:11.11#ibcon#about to read 3, iclass 7, count 0 2006.281.07:51:11.14#ibcon#read 3, iclass 7, count 0 2006.281.07:51:11.14#ibcon#about to read 4, iclass 7, count 0 2006.281.07:51:11.14#ibcon#read 4, iclass 7, count 0 2006.281.07:51:11.14#ibcon#about to read 5, iclass 7, count 0 2006.281.07:51:11.14#ibcon#read 5, iclass 7, count 0 2006.281.07:51:11.14#ibcon#about to read 6, iclass 7, count 0 2006.281.07:51:11.14#ibcon#read 6, iclass 7, count 0 2006.281.07:51:11.14#ibcon#end of sib2, iclass 7, count 0 2006.281.07:51:11.14#ibcon#*after write, iclass 7, count 0 2006.281.07:51:11.14#ibcon#*before return 0, iclass 7, count 0 2006.281.07:51:11.14#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:11.14#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:11.14#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:51:11.14#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:51:11.14$vc4f8/valo=6,772.99 2006.281.07:51:11.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:51:11.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:51:11.14#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:11.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:11.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:11.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:11.14#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:51:11.14#ibcon#first serial, iclass 11, count 0 2006.281.07:51:11.14#ibcon#enter sib2, iclass 11, count 0 2006.281.07:51:11.14#ibcon#flushed, iclass 11, count 0 2006.281.07:51:11.14#ibcon#about to write, iclass 11, count 0 2006.281.07:51:11.14#ibcon#wrote, iclass 11, count 0 2006.281.07:51:11.14#ibcon#about to read 3, iclass 11, count 0 2006.281.07:51:11.16#ibcon#read 3, iclass 11, count 0 2006.281.07:51:11.17#ibcon#about to read 4, iclass 11, count 0 2006.281.07:51:11.17#ibcon#read 4, iclass 11, count 0 2006.281.07:51:11.17#ibcon#about to read 5, iclass 11, count 0 2006.281.07:51:11.17#ibcon#read 5, iclass 11, count 0 2006.281.07:51:11.17#ibcon#about to read 6, iclass 11, count 0 2006.281.07:51:11.17#ibcon#read 6, iclass 11, count 0 2006.281.07:51:11.17#ibcon#end of sib2, iclass 11, count 0 2006.281.07:51:11.17#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:51:11.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:51:11.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:51:11.17#ibcon#*before write, iclass 11, count 0 2006.281.07:51:11.17#ibcon#enter sib2, iclass 11, count 0 2006.281.07:51:11.17#ibcon#flushed, iclass 11, count 0 2006.281.07:51:11.17#ibcon#about to write, iclass 11, count 0 2006.281.07:51:11.17#ibcon#wrote, iclass 11, count 0 2006.281.07:51:11.17#ibcon#about to read 3, iclass 11, count 0 2006.281.07:51:11.21#ibcon#read 3, iclass 11, count 0 2006.281.07:51:11.21#ibcon#about to read 4, iclass 11, count 0 2006.281.07:51:11.21#ibcon#read 4, iclass 11, count 0 2006.281.07:51:11.21#ibcon#about to read 5, iclass 11, count 0 2006.281.07:51:11.21#ibcon#read 5, iclass 11, count 0 2006.281.07:51:11.21#ibcon#about to read 6, iclass 11, count 0 2006.281.07:51:11.21#ibcon#read 6, iclass 11, count 0 2006.281.07:51:11.21#ibcon#end of sib2, iclass 11, count 0 2006.281.07:51:11.21#ibcon#*after write, iclass 11, count 0 2006.281.07:51:11.21#ibcon#*before return 0, iclass 11, count 0 2006.281.07:51:11.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:11.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:11.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:51:11.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:51:11.21$vc4f8/va=6,6 2006.281.07:51:11.21#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:51:11.21#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:51:11.21#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:11.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:11.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:11.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:11.26#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:51:11.26#ibcon#first serial, iclass 13, count 2 2006.281.07:51:11.26#ibcon#enter sib2, iclass 13, count 2 2006.281.07:51:11.26#ibcon#flushed, iclass 13, count 2 2006.281.07:51:11.26#ibcon#about to write, iclass 13, count 2 2006.281.07:51:11.26#ibcon#wrote, iclass 13, count 2 2006.281.07:51:11.26#ibcon#about to read 3, iclass 13, count 2 2006.281.07:51:11.28#ibcon#read 3, iclass 13, count 2 2006.281.07:51:11.28#ibcon#about to read 4, iclass 13, count 2 2006.281.07:51:11.28#ibcon#read 4, iclass 13, count 2 2006.281.07:51:11.28#ibcon#about to read 5, iclass 13, count 2 2006.281.07:51:11.28#ibcon#read 5, iclass 13, count 2 2006.281.07:51:11.28#ibcon#about to read 6, iclass 13, count 2 2006.281.07:51:11.28#ibcon#read 6, iclass 13, count 2 2006.281.07:51:11.28#ibcon#end of sib2, iclass 13, count 2 2006.281.07:51:11.28#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:51:11.28#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:51:11.28#ibcon#[25=AT06-06\r\n] 2006.281.07:51:11.28#ibcon#*before write, iclass 13, count 2 2006.281.07:51:11.28#ibcon#enter sib2, iclass 13, count 2 2006.281.07:51:11.28#ibcon#flushed, iclass 13, count 2 2006.281.07:51:11.28#ibcon#about to write, iclass 13, count 2 2006.281.07:51:11.28#ibcon#wrote, iclass 13, count 2 2006.281.07:51:11.28#ibcon#about to read 3, iclass 13, count 2 2006.281.07:51:11.31#ibcon#read 3, iclass 13, count 2 2006.281.07:51:11.31#ibcon#about to read 4, iclass 13, count 2 2006.281.07:51:11.31#ibcon#read 4, iclass 13, count 2 2006.281.07:51:11.31#ibcon#about to read 5, iclass 13, count 2 2006.281.07:51:11.31#ibcon#read 5, iclass 13, count 2 2006.281.07:51:11.31#ibcon#about to read 6, iclass 13, count 2 2006.281.07:51:11.31#ibcon#read 6, iclass 13, count 2 2006.281.07:51:11.31#ibcon#end of sib2, iclass 13, count 2 2006.281.07:51:11.31#ibcon#*after write, iclass 13, count 2 2006.281.07:51:11.31#ibcon#*before return 0, iclass 13, count 2 2006.281.07:51:11.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:11.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:11.31#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:51:11.31#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:11.31#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:11.43#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:11.43#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:11.43#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:51:11.43#ibcon#first serial, iclass 13, count 0 2006.281.07:51:11.43#ibcon#enter sib2, iclass 13, count 0 2006.281.07:51:11.43#ibcon#flushed, iclass 13, count 0 2006.281.07:51:11.43#ibcon#about to write, iclass 13, count 0 2006.281.07:51:11.43#ibcon#wrote, iclass 13, count 0 2006.281.07:51:11.43#ibcon#about to read 3, iclass 13, count 0 2006.281.07:51:11.45#ibcon#read 3, iclass 13, count 0 2006.281.07:51:11.45#ibcon#about to read 4, iclass 13, count 0 2006.281.07:51:11.45#ibcon#read 4, iclass 13, count 0 2006.281.07:51:11.45#ibcon#about to read 5, iclass 13, count 0 2006.281.07:51:11.45#ibcon#read 5, iclass 13, count 0 2006.281.07:51:11.45#ibcon#about to read 6, iclass 13, count 0 2006.281.07:51:11.45#ibcon#read 6, iclass 13, count 0 2006.281.07:51:11.45#ibcon#end of sib2, iclass 13, count 0 2006.281.07:51:11.45#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:51:11.45#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:51:11.45#ibcon#[25=USB\r\n] 2006.281.07:51:11.45#ibcon#*before write, iclass 13, count 0 2006.281.07:51:11.45#ibcon#enter sib2, iclass 13, count 0 2006.281.07:51:11.45#ibcon#flushed, iclass 13, count 0 2006.281.07:51:11.45#ibcon#about to write, iclass 13, count 0 2006.281.07:51:11.45#ibcon#wrote, iclass 13, count 0 2006.281.07:51:11.45#ibcon#about to read 3, iclass 13, count 0 2006.281.07:51:11.48#ibcon#read 3, iclass 13, count 0 2006.281.07:51:11.48#ibcon#about to read 4, iclass 13, count 0 2006.281.07:51:11.48#ibcon#read 4, iclass 13, count 0 2006.281.07:51:11.48#ibcon#about to read 5, iclass 13, count 0 2006.281.07:51:11.48#ibcon#read 5, iclass 13, count 0 2006.281.07:51:11.48#ibcon#about to read 6, iclass 13, count 0 2006.281.07:51:11.48#ibcon#read 6, iclass 13, count 0 2006.281.07:51:11.48#ibcon#end of sib2, iclass 13, count 0 2006.281.07:51:11.48#ibcon#*after write, iclass 13, count 0 2006.281.07:51:11.48#ibcon#*before return 0, iclass 13, count 0 2006.281.07:51:11.48#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:11.48#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:11.48#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:51:11.48#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:51:11.48$vc4f8/valo=7,832.99 2006.281.07:51:11.48#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:51:11.48#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:51:11.48#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:11.48#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:11.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:11.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:11.48#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:51:11.48#ibcon#first serial, iclass 15, count 0 2006.281.07:51:11.48#ibcon#enter sib2, iclass 15, count 0 2006.281.07:51:11.48#ibcon#flushed, iclass 15, count 0 2006.281.07:51:11.48#ibcon#about to write, iclass 15, count 0 2006.281.07:51:11.48#ibcon#wrote, iclass 15, count 0 2006.281.07:51:11.48#ibcon#about to read 3, iclass 15, count 0 2006.281.07:51:11.50#ibcon#read 3, iclass 15, count 0 2006.281.07:51:11.50#ibcon#about to read 4, iclass 15, count 0 2006.281.07:51:11.50#ibcon#read 4, iclass 15, count 0 2006.281.07:51:11.50#ibcon#about to read 5, iclass 15, count 0 2006.281.07:51:11.50#ibcon#read 5, iclass 15, count 0 2006.281.07:51:11.50#ibcon#about to read 6, iclass 15, count 0 2006.281.07:51:11.50#ibcon#read 6, iclass 15, count 0 2006.281.07:51:11.50#ibcon#end of sib2, iclass 15, count 0 2006.281.07:51:11.50#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:51:11.50#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:51:11.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:51:11.50#ibcon#*before write, iclass 15, count 0 2006.281.07:51:11.50#ibcon#enter sib2, iclass 15, count 0 2006.281.07:51:11.50#ibcon#flushed, iclass 15, count 0 2006.281.07:51:11.50#ibcon#about to write, iclass 15, count 0 2006.281.07:51:11.50#ibcon#wrote, iclass 15, count 0 2006.281.07:51:11.50#ibcon#about to read 3, iclass 15, count 0 2006.281.07:51:11.54#ibcon#read 3, iclass 15, count 0 2006.281.07:51:11.54#ibcon#about to read 4, iclass 15, count 0 2006.281.07:51:11.54#ibcon#read 4, iclass 15, count 0 2006.281.07:51:11.54#ibcon#about to read 5, iclass 15, count 0 2006.281.07:51:11.54#ibcon#read 5, iclass 15, count 0 2006.281.07:51:11.54#ibcon#about to read 6, iclass 15, count 0 2006.281.07:51:11.54#ibcon#read 6, iclass 15, count 0 2006.281.07:51:11.54#ibcon#end of sib2, iclass 15, count 0 2006.281.07:51:11.54#ibcon#*after write, iclass 15, count 0 2006.281.07:51:11.54#ibcon#*before return 0, iclass 15, count 0 2006.281.07:51:11.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:11.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:11.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:51:11.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:51:11.54$vc4f8/va=7,6 2006.281.07:51:11.54#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:51:11.54#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:51:11.54#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:11.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:11.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:11.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:11.60#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:51:11.60#ibcon#first serial, iclass 17, count 2 2006.281.07:51:11.60#ibcon#enter sib2, iclass 17, count 2 2006.281.07:51:11.60#ibcon#flushed, iclass 17, count 2 2006.281.07:51:11.60#ibcon#about to write, iclass 17, count 2 2006.281.07:51:11.60#ibcon#wrote, iclass 17, count 2 2006.281.07:51:11.60#ibcon#about to read 3, iclass 17, count 2 2006.281.07:51:11.63#ibcon#read 3, iclass 17, count 2 2006.281.07:51:11.63#ibcon#about to read 4, iclass 17, count 2 2006.281.07:51:11.63#ibcon#read 4, iclass 17, count 2 2006.281.07:51:11.63#ibcon#about to read 5, iclass 17, count 2 2006.281.07:51:11.63#ibcon#read 5, iclass 17, count 2 2006.281.07:51:11.63#ibcon#about to read 6, iclass 17, count 2 2006.281.07:51:11.63#ibcon#read 6, iclass 17, count 2 2006.281.07:51:11.63#ibcon#end of sib2, iclass 17, count 2 2006.281.07:51:11.63#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:51:11.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:51:11.63#ibcon#[25=AT07-06\r\n] 2006.281.07:51:11.63#ibcon#*before write, iclass 17, count 2 2006.281.07:51:11.63#ibcon#enter sib2, iclass 17, count 2 2006.281.07:51:11.63#ibcon#flushed, iclass 17, count 2 2006.281.07:51:11.63#ibcon#about to write, iclass 17, count 2 2006.281.07:51:11.63#ibcon#wrote, iclass 17, count 2 2006.281.07:51:11.63#ibcon#about to read 3, iclass 17, count 2 2006.281.07:51:11.66#ibcon#read 3, iclass 17, count 2 2006.281.07:51:11.66#ibcon#about to read 4, iclass 17, count 2 2006.281.07:51:11.66#ibcon#read 4, iclass 17, count 2 2006.281.07:51:11.66#ibcon#about to read 5, iclass 17, count 2 2006.281.07:51:11.66#ibcon#read 5, iclass 17, count 2 2006.281.07:51:11.66#ibcon#about to read 6, iclass 17, count 2 2006.281.07:51:11.66#ibcon#read 6, iclass 17, count 2 2006.281.07:51:11.66#ibcon#end of sib2, iclass 17, count 2 2006.281.07:51:11.66#ibcon#*after write, iclass 17, count 2 2006.281.07:51:11.66#ibcon#*before return 0, iclass 17, count 2 2006.281.07:51:11.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:11.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:11.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:51:11.66#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:11.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:51:11.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:51:11.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:51:11.78#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:51:11.78#ibcon#first serial, iclass 17, count 0 2006.281.07:51:11.78#ibcon#enter sib2, iclass 17, count 0 2006.281.07:51:11.78#ibcon#flushed, iclass 17, count 0 2006.281.07:51:11.78#ibcon#about to write, iclass 17, count 0 2006.281.07:51:11.78#ibcon#wrote, iclass 17, count 0 2006.281.07:51:11.78#ibcon#about to read 3, iclass 17, count 0 2006.281.07:51:11.80#ibcon#read 3, iclass 17, count 0 2006.281.07:51:11.80#ibcon#about to read 4, iclass 17, count 0 2006.281.07:51:11.80#ibcon#read 4, iclass 17, count 0 2006.281.07:51:11.80#ibcon#about to read 5, iclass 17, count 0 2006.281.07:51:11.80#ibcon#read 5, iclass 17, count 0 2006.281.07:51:11.80#ibcon#about to read 6, iclass 17, count 0 2006.281.07:51:11.80#ibcon#read 6, iclass 17, count 0 2006.281.07:51:11.80#ibcon#end of sib2, iclass 17, count 0 2006.281.07:51:11.80#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:51:11.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:51:11.80#ibcon#[25=USB\r\n] 2006.281.07:51:11.80#ibcon#*before write, iclass 17, count 0 2006.281.07:51:11.80#ibcon#enter sib2, iclass 17, count 0 2006.281.07:51:11.80#ibcon#flushed, iclass 17, count 0 2006.281.07:51:11.80#ibcon#about to write, iclass 17, count 0 2006.281.07:51:11.80#ibcon#wrote, iclass 17, count 0 2006.281.07:51:11.80#ibcon#about to read 3, iclass 17, count 0 2006.281.07:51:11.83#ibcon#read 3, iclass 17, count 0 2006.281.07:51:11.83#ibcon#about to read 4, iclass 17, count 0 2006.281.07:51:11.83#ibcon#read 4, iclass 17, count 0 2006.281.07:51:11.83#ibcon#about to read 5, iclass 17, count 0 2006.281.07:51:11.83#ibcon#read 5, iclass 17, count 0 2006.281.07:51:11.83#ibcon#about to read 6, iclass 17, count 0 2006.281.07:51:11.83#ibcon#read 6, iclass 17, count 0 2006.281.07:51:11.83#ibcon#end of sib2, iclass 17, count 0 2006.281.07:51:11.83#ibcon#*after write, iclass 17, count 0 2006.281.07:51:11.83#ibcon#*before return 0, iclass 17, count 0 2006.281.07:51:11.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:51:11.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:51:11.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:51:11.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:51:11.83$vc4f8/valo=8,852.99 2006.281.07:51:11.83#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:51:11.83#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:51:11.83#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:11.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:51:11.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:51:11.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:51:11.83#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:51:11.83#ibcon#first serial, iclass 19, count 0 2006.281.07:51:11.83#ibcon#enter sib2, iclass 19, count 0 2006.281.07:51:11.83#ibcon#flushed, iclass 19, count 0 2006.281.07:51:11.83#ibcon#about to write, iclass 19, count 0 2006.281.07:51:11.83#ibcon#wrote, iclass 19, count 0 2006.281.07:51:11.83#ibcon#about to read 3, iclass 19, count 0 2006.281.07:51:11.85#ibcon#read 3, iclass 19, count 0 2006.281.07:51:11.85#ibcon#about to read 4, iclass 19, count 0 2006.281.07:51:11.85#ibcon#read 4, iclass 19, count 0 2006.281.07:51:11.85#ibcon#about to read 5, iclass 19, count 0 2006.281.07:51:11.85#ibcon#read 5, iclass 19, count 0 2006.281.07:51:11.85#ibcon#about to read 6, iclass 19, count 0 2006.281.07:51:11.85#ibcon#read 6, iclass 19, count 0 2006.281.07:51:11.85#ibcon#end of sib2, iclass 19, count 0 2006.281.07:51:11.85#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:51:11.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:51:11.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:51:11.85#ibcon#*before write, iclass 19, count 0 2006.281.07:51:11.85#ibcon#enter sib2, iclass 19, count 0 2006.281.07:51:11.85#ibcon#flushed, iclass 19, count 0 2006.281.07:51:11.85#ibcon#about to write, iclass 19, count 0 2006.281.07:51:11.85#ibcon#wrote, iclass 19, count 0 2006.281.07:51:11.85#ibcon#about to read 3, iclass 19, count 0 2006.281.07:51:11.89#ibcon#read 3, iclass 19, count 0 2006.281.07:51:11.89#ibcon#about to read 4, iclass 19, count 0 2006.281.07:51:11.89#ibcon#read 4, iclass 19, count 0 2006.281.07:51:11.89#ibcon#about to read 5, iclass 19, count 0 2006.281.07:51:11.89#ibcon#read 5, iclass 19, count 0 2006.281.07:51:11.89#ibcon#about to read 6, iclass 19, count 0 2006.281.07:51:11.89#ibcon#read 6, iclass 19, count 0 2006.281.07:51:11.89#ibcon#end of sib2, iclass 19, count 0 2006.281.07:51:11.89#ibcon#*after write, iclass 19, count 0 2006.281.07:51:11.89#ibcon#*before return 0, iclass 19, count 0 2006.281.07:51:11.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:51:11.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:51:11.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:51:11.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:51:11.89$vc4f8/va=8,6 2006.281.07:51:11.90#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:51:11.90#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:51:11.90#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:11.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:51:11.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:51:11.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:51:11.94#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:51:11.94#ibcon#first serial, iclass 21, count 2 2006.281.07:51:11.94#ibcon#enter sib2, iclass 21, count 2 2006.281.07:51:11.94#ibcon#flushed, iclass 21, count 2 2006.281.07:51:11.94#ibcon#about to write, iclass 21, count 2 2006.281.07:51:11.94#ibcon#wrote, iclass 21, count 2 2006.281.07:51:11.94#ibcon#about to read 3, iclass 21, count 2 2006.281.07:51:11.96#ibcon#read 3, iclass 21, count 2 2006.281.07:51:11.96#ibcon#about to read 4, iclass 21, count 2 2006.281.07:51:11.96#ibcon#read 4, iclass 21, count 2 2006.281.07:51:11.96#ibcon#about to read 5, iclass 21, count 2 2006.281.07:51:11.96#ibcon#read 5, iclass 21, count 2 2006.281.07:51:11.96#ibcon#about to read 6, iclass 21, count 2 2006.281.07:51:11.96#ibcon#read 6, iclass 21, count 2 2006.281.07:51:11.96#ibcon#end of sib2, iclass 21, count 2 2006.281.07:51:11.96#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:51:11.96#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:51:11.96#ibcon#[25=AT08-06\r\n] 2006.281.07:51:11.96#ibcon#*before write, iclass 21, count 2 2006.281.07:51:11.96#ibcon#enter sib2, iclass 21, count 2 2006.281.07:51:11.96#ibcon#flushed, iclass 21, count 2 2006.281.07:51:11.96#ibcon#about to write, iclass 21, count 2 2006.281.07:51:11.96#ibcon#wrote, iclass 21, count 2 2006.281.07:51:11.96#ibcon#about to read 3, iclass 21, count 2 2006.281.07:51:11.99#ibcon#read 3, iclass 21, count 2 2006.281.07:51:11.99#ibcon#about to read 4, iclass 21, count 2 2006.281.07:51:11.99#ibcon#read 4, iclass 21, count 2 2006.281.07:51:11.99#ibcon#about to read 5, iclass 21, count 2 2006.281.07:51:11.99#ibcon#read 5, iclass 21, count 2 2006.281.07:51:11.99#ibcon#about to read 6, iclass 21, count 2 2006.281.07:51:11.99#ibcon#read 6, iclass 21, count 2 2006.281.07:51:11.99#ibcon#end of sib2, iclass 21, count 2 2006.281.07:51:11.99#ibcon#*after write, iclass 21, count 2 2006.281.07:51:11.99#ibcon#*before return 0, iclass 21, count 2 2006.281.07:51:11.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:51:11.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:51:11.99#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:51:11.99#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:11.99#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:51:12.11#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:51:12.11#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:51:12.11#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:51:12.11#ibcon#first serial, iclass 21, count 0 2006.281.07:51:12.11#ibcon#enter sib2, iclass 21, count 0 2006.281.07:51:12.11#ibcon#flushed, iclass 21, count 0 2006.281.07:51:12.11#ibcon#about to write, iclass 21, count 0 2006.281.07:51:12.11#ibcon#wrote, iclass 21, count 0 2006.281.07:51:12.11#ibcon#about to read 3, iclass 21, count 0 2006.281.07:51:12.13#ibcon#read 3, iclass 21, count 0 2006.281.07:51:12.13#ibcon#about to read 4, iclass 21, count 0 2006.281.07:51:12.13#ibcon#read 4, iclass 21, count 0 2006.281.07:51:12.13#ibcon#about to read 5, iclass 21, count 0 2006.281.07:51:12.13#ibcon#read 5, iclass 21, count 0 2006.281.07:51:12.13#ibcon#about to read 6, iclass 21, count 0 2006.281.07:51:12.13#ibcon#read 6, iclass 21, count 0 2006.281.07:51:12.13#ibcon#end of sib2, iclass 21, count 0 2006.281.07:51:12.13#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:51:12.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:51:12.13#ibcon#[25=USB\r\n] 2006.281.07:51:12.13#ibcon#*before write, iclass 21, count 0 2006.281.07:51:12.13#ibcon#enter sib2, iclass 21, count 0 2006.281.07:51:12.13#ibcon#flushed, iclass 21, count 0 2006.281.07:51:12.13#ibcon#about to write, iclass 21, count 0 2006.281.07:51:12.13#ibcon#wrote, iclass 21, count 0 2006.281.07:51:12.13#ibcon#about to read 3, iclass 21, count 0 2006.281.07:51:12.16#ibcon#read 3, iclass 21, count 0 2006.281.07:51:12.16#ibcon#about to read 4, iclass 21, count 0 2006.281.07:51:12.16#ibcon#read 4, iclass 21, count 0 2006.281.07:51:12.16#ibcon#about to read 5, iclass 21, count 0 2006.281.07:51:12.16#ibcon#read 5, iclass 21, count 0 2006.281.07:51:12.16#ibcon#about to read 6, iclass 21, count 0 2006.281.07:51:12.16#ibcon#read 6, iclass 21, count 0 2006.281.07:51:12.16#ibcon#end of sib2, iclass 21, count 0 2006.281.07:51:12.16#ibcon#*after write, iclass 21, count 0 2006.281.07:51:12.16#ibcon#*before return 0, iclass 21, count 0 2006.281.07:51:12.16#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:51:12.16#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:51:12.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:51:12.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:51:12.16$vc4f8/vblo=1,632.99 2006.281.07:51:12.16#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:51:12.16#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:51:12.16#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:12.16#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:51:12.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:51:12.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:51:12.16#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:51:12.16#ibcon#first serial, iclass 23, count 0 2006.281.07:51:12.16#ibcon#enter sib2, iclass 23, count 0 2006.281.07:51:12.16#ibcon#flushed, iclass 23, count 0 2006.281.07:51:12.16#ibcon#about to write, iclass 23, count 0 2006.281.07:51:12.16#ibcon#wrote, iclass 23, count 0 2006.281.07:51:12.16#ibcon#about to read 3, iclass 23, count 0 2006.281.07:51:12.18#ibcon#read 3, iclass 23, count 0 2006.281.07:51:12.18#ibcon#about to read 4, iclass 23, count 0 2006.281.07:51:12.18#ibcon#read 4, iclass 23, count 0 2006.281.07:51:12.18#ibcon#about to read 5, iclass 23, count 0 2006.281.07:51:12.18#ibcon#read 5, iclass 23, count 0 2006.281.07:51:12.18#ibcon#about to read 6, iclass 23, count 0 2006.281.07:51:12.18#ibcon#read 6, iclass 23, count 0 2006.281.07:51:12.18#ibcon#end of sib2, iclass 23, count 0 2006.281.07:51:12.18#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:51:12.18#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:51:12.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:51:12.18#ibcon#*before write, iclass 23, count 0 2006.281.07:51:12.18#ibcon#enter sib2, iclass 23, count 0 2006.281.07:51:12.18#ibcon#flushed, iclass 23, count 0 2006.281.07:51:12.18#ibcon#about to write, iclass 23, count 0 2006.281.07:51:12.18#ibcon#wrote, iclass 23, count 0 2006.281.07:51:12.18#ibcon#about to read 3, iclass 23, count 0 2006.281.07:51:12.22#ibcon#read 3, iclass 23, count 0 2006.281.07:51:12.22#ibcon#about to read 4, iclass 23, count 0 2006.281.07:51:12.22#ibcon#read 4, iclass 23, count 0 2006.281.07:51:12.22#ibcon#about to read 5, iclass 23, count 0 2006.281.07:51:12.22#ibcon#read 5, iclass 23, count 0 2006.281.07:51:12.22#ibcon#about to read 6, iclass 23, count 0 2006.281.07:51:12.22#ibcon#read 6, iclass 23, count 0 2006.281.07:51:12.22#ibcon#end of sib2, iclass 23, count 0 2006.281.07:51:12.22#ibcon#*after write, iclass 23, count 0 2006.281.07:51:12.22#ibcon#*before return 0, iclass 23, count 0 2006.281.07:51:12.22#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:51:12.22#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:51:12.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:51:12.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:51:12.22$vc4f8/vb=1,4 2006.281.07:51:12.22#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:51:12.22#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:51:12.22#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:12.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:51:12.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:51:12.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:51:12.22#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:51:12.22#ibcon#first serial, iclass 25, count 2 2006.281.07:51:12.22#ibcon#enter sib2, iclass 25, count 2 2006.281.07:51:12.22#ibcon#flushed, iclass 25, count 2 2006.281.07:51:12.22#ibcon#about to write, iclass 25, count 2 2006.281.07:51:12.22#ibcon#wrote, iclass 25, count 2 2006.281.07:51:12.22#ibcon#about to read 3, iclass 25, count 2 2006.281.07:51:12.24#ibcon#read 3, iclass 25, count 2 2006.281.07:51:12.24#ibcon#about to read 4, iclass 25, count 2 2006.281.07:51:12.24#ibcon#read 4, iclass 25, count 2 2006.281.07:51:12.24#ibcon#about to read 5, iclass 25, count 2 2006.281.07:51:12.24#ibcon#read 5, iclass 25, count 2 2006.281.07:51:12.24#ibcon#about to read 6, iclass 25, count 2 2006.281.07:51:12.24#ibcon#read 6, iclass 25, count 2 2006.281.07:51:12.24#ibcon#end of sib2, iclass 25, count 2 2006.281.07:51:12.24#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:51:12.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:51:12.29#ibcon#[27=AT01-04\r\n] 2006.281.07:51:12.29#ibcon#*before write, iclass 25, count 2 2006.281.07:51:12.29#ibcon#enter sib2, iclass 25, count 2 2006.281.07:51:12.29#ibcon#flushed, iclass 25, count 2 2006.281.07:51:12.29#ibcon#about to write, iclass 25, count 2 2006.281.07:51:12.29#ibcon#wrote, iclass 25, count 2 2006.281.07:51:12.29#ibcon#about to read 3, iclass 25, count 2 2006.281.07:51:12.32#ibcon#read 3, iclass 25, count 2 2006.281.07:51:12.32#ibcon#about to read 4, iclass 25, count 2 2006.281.07:51:12.32#ibcon#read 4, iclass 25, count 2 2006.281.07:51:12.32#ibcon#about to read 5, iclass 25, count 2 2006.281.07:51:12.32#ibcon#read 5, iclass 25, count 2 2006.281.07:51:12.32#ibcon#about to read 6, iclass 25, count 2 2006.281.07:51:12.32#ibcon#read 6, iclass 25, count 2 2006.281.07:51:12.32#ibcon#end of sib2, iclass 25, count 2 2006.281.07:51:12.32#ibcon#*after write, iclass 25, count 2 2006.281.07:51:12.32#ibcon#*before return 0, iclass 25, count 2 2006.281.07:51:12.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:51:12.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:51:12.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:51:12.32#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:12.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:51:12.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:51:12.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:51:12.44#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:51:12.44#ibcon#first serial, iclass 25, count 0 2006.281.07:51:12.44#ibcon#enter sib2, iclass 25, count 0 2006.281.07:51:12.44#ibcon#flushed, iclass 25, count 0 2006.281.07:51:12.44#ibcon#about to write, iclass 25, count 0 2006.281.07:51:12.44#ibcon#wrote, iclass 25, count 0 2006.281.07:51:12.44#ibcon#about to read 3, iclass 25, count 0 2006.281.07:51:12.46#ibcon#read 3, iclass 25, count 0 2006.281.07:51:12.46#ibcon#about to read 4, iclass 25, count 0 2006.281.07:51:12.46#ibcon#read 4, iclass 25, count 0 2006.281.07:51:12.46#ibcon#about to read 5, iclass 25, count 0 2006.281.07:51:12.46#ibcon#read 5, iclass 25, count 0 2006.281.07:51:12.46#ibcon#about to read 6, iclass 25, count 0 2006.281.07:51:12.46#ibcon#read 6, iclass 25, count 0 2006.281.07:51:12.46#ibcon#end of sib2, iclass 25, count 0 2006.281.07:51:12.46#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:51:12.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:51:12.46#ibcon#[27=USB\r\n] 2006.281.07:51:12.46#ibcon#*before write, iclass 25, count 0 2006.281.07:51:12.46#ibcon#enter sib2, iclass 25, count 0 2006.281.07:51:12.46#ibcon#flushed, iclass 25, count 0 2006.281.07:51:12.46#ibcon#about to write, iclass 25, count 0 2006.281.07:51:12.46#ibcon#wrote, iclass 25, count 0 2006.281.07:51:12.46#ibcon#about to read 3, iclass 25, count 0 2006.281.07:51:12.49#ibcon#read 3, iclass 25, count 0 2006.281.07:51:12.49#ibcon#about to read 4, iclass 25, count 0 2006.281.07:51:12.49#ibcon#read 4, iclass 25, count 0 2006.281.07:51:12.49#ibcon#about to read 5, iclass 25, count 0 2006.281.07:51:12.49#ibcon#read 5, iclass 25, count 0 2006.281.07:51:12.49#ibcon#about to read 6, iclass 25, count 0 2006.281.07:51:12.49#ibcon#read 6, iclass 25, count 0 2006.281.07:51:12.49#ibcon#end of sib2, iclass 25, count 0 2006.281.07:51:12.49#ibcon#*after write, iclass 25, count 0 2006.281.07:51:12.49#ibcon#*before return 0, iclass 25, count 0 2006.281.07:51:12.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:51:12.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:51:12.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:51:12.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:51:12.49$vc4f8/vblo=2,640.99 2006.281.07:51:12.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:51:12.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:51:12.49#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:12.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:51:12.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:51:12.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:51:12.49#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:51:12.49#ibcon#first serial, iclass 28, count 0 2006.281.07:51:12.49#ibcon#enter sib2, iclass 28, count 0 2006.281.07:51:12.49#ibcon#flushed, iclass 28, count 0 2006.281.07:51:12.49#ibcon#about to write, iclass 28, count 0 2006.281.07:51:12.49#ibcon#wrote, iclass 28, count 0 2006.281.07:51:12.49#ibcon#about to read 3, iclass 28, count 0 2006.281.07:51:12.50#abcon#<5=/13 2.3 8.3 20.86 511001.3\r\n> 2006.281.07:51:12.51#ibcon#read 3, iclass 28, count 0 2006.281.07:51:12.51#ibcon#about to read 4, iclass 28, count 0 2006.281.07:51:12.51#ibcon#read 4, iclass 28, count 0 2006.281.07:51:12.51#ibcon#about to read 5, iclass 28, count 0 2006.281.07:51:12.51#ibcon#read 5, iclass 28, count 0 2006.281.07:51:12.51#ibcon#about to read 6, iclass 28, count 0 2006.281.07:51:12.51#ibcon#read 6, iclass 28, count 0 2006.281.07:51:12.51#ibcon#end of sib2, iclass 28, count 0 2006.281.07:51:12.51#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:51:12.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:51:12.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:51:12.51#ibcon#*before write, iclass 28, count 0 2006.281.07:51:12.51#ibcon#enter sib2, iclass 28, count 0 2006.281.07:51:12.51#ibcon#flushed, iclass 28, count 0 2006.281.07:51:12.51#ibcon#about to write, iclass 28, count 0 2006.281.07:51:12.51#ibcon#wrote, iclass 28, count 0 2006.281.07:51:12.51#ibcon#about to read 3, iclass 28, count 0 2006.281.07:51:12.52#abcon#{5=INTERFACE CLEAR} 2006.281.07:51:12.55#ibcon#read 3, iclass 28, count 0 2006.281.07:51:12.55#ibcon#about to read 4, iclass 28, count 0 2006.281.07:51:12.55#ibcon#read 4, iclass 28, count 0 2006.281.07:51:12.55#ibcon#about to read 5, iclass 28, count 0 2006.281.07:51:12.55#ibcon#read 5, iclass 28, count 0 2006.281.07:51:12.55#ibcon#about to read 6, iclass 28, count 0 2006.281.07:51:12.55#ibcon#read 6, iclass 28, count 0 2006.281.07:51:12.55#ibcon#end of sib2, iclass 28, count 0 2006.281.07:51:12.55#ibcon#*after write, iclass 28, count 0 2006.281.07:51:12.55#ibcon#*before return 0, iclass 28, count 0 2006.281.07:51:12.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:51:12.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:51:12.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:51:12.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:51:12.55$vc4f8/vb=2,5 2006.281.07:51:12.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:51:12.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:51:12.55#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:12.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:51:12.58#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:51:12.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:51:12.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:51:12.61#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:51:12.61#ibcon#first serial, iclass 32, count 2 2006.281.07:51:12.61#ibcon#enter sib2, iclass 32, count 2 2006.281.07:51:12.61#ibcon#flushed, iclass 32, count 2 2006.281.07:51:12.61#ibcon#about to write, iclass 32, count 2 2006.281.07:51:12.61#ibcon#wrote, iclass 32, count 2 2006.281.07:51:12.61#ibcon#about to read 3, iclass 32, count 2 2006.281.07:51:12.63#ibcon#read 3, iclass 32, count 2 2006.281.07:51:12.63#ibcon#about to read 4, iclass 32, count 2 2006.281.07:51:12.63#ibcon#read 4, iclass 32, count 2 2006.281.07:51:12.63#ibcon#about to read 5, iclass 32, count 2 2006.281.07:51:12.63#ibcon#read 5, iclass 32, count 2 2006.281.07:51:12.63#ibcon#about to read 6, iclass 32, count 2 2006.281.07:51:12.63#ibcon#read 6, iclass 32, count 2 2006.281.07:51:12.63#ibcon#end of sib2, iclass 32, count 2 2006.281.07:51:12.63#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:51:12.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:51:12.63#ibcon#[27=AT02-05\r\n] 2006.281.07:51:12.63#ibcon#*before write, iclass 32, count 2 2006.281.07:51:12.63#ibcon#enter sib2, iclass 32, count 2 2006.281.07:51:12.63#ibcon#flushed, iclass 32, count 2 2006.281.07:51:12.63#ibcon#about to write, iclass 32, count 2 2006.281.07:51:12.63#ibcon#wrote, iclass 32, count 2 2006.281.07:51:12.63#ibcon#about to read 3, iclass 32, count 2 2006.281.07:51:12.67#ibcon#read 3, iclass 32, count 2 2006.281.07:51:12.67#ibcon#about to read 4, iclass 32, count 2 2006.281.07:51:12.67#ibcon#read 4, iclass 32, count 2 2006.281.07:51:12.67#ibcon#about to read 5, iclass 32, count 2 2006.281.07:51:12.67#ibcon#read 5, iclass 32, count 2 2006.281.07:51:12.67#ibcon#about to read 6, iclass 32, count 2 2006.281.07:51:12.67#ibcon#read 6, iclass 32, count 2 2006.281.07:51:12.67#ibcon#end of sib2, iclass 32, count 2 2006.281.07:51:12.67#ibcon#*after write, iclass 32, count 2 2006.281.07:51:12.67#ibcon#*before return 0, iclass 32, count 2 2006.281.07:51:12.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:51:12.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:51:12.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:51:12.67#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:12.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:51:12.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:51:12.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:51:12.78#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:51:12.78#ibcon#first serial, iclass 32, count 0 2006.281.07:51:12.78#ibcon#enter sib2, iclass 32, count 0 2006.281.07:51:12.78#ibcon#flushed, iclass 32, count 0 2006.281.07:51:12.78#ibcon#about to write, iclass 32, count 0 2006.281.07:51:12.78#ibcon#wrote, iclass 32, count 0 2006.281.07:51:12.78#ibcon#about to read 3, iclass 32, count 0 2006.281.07:51:12.80#ibcon#read 3, iclass 32, count 0 2006.281.07:51:12.80#ibcon#about to read 4, iclass 32, count 0 2006.281.07:51:12.80#ibcon#read 4, iclass 32, count 0 2006.281.07:51:12.80#ibcon#about to read 5, iclass 32, count 0 2006.281.07:51:12.80#ibcon#read 5, iclass 32, count 0 2006.281.07:51:12.80#ibcon#about to read 6, iclass 32, count 0 2006.281.07:51:12.80#ibcon#read 6, iclass 32, count 0 2006.281.07:51:12.80#ibcon#end of sib2, iclass 32, count 0 2006.281.07:51:12.80#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:51:12.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:51:12.80#ibcon#[27=USB\r\n] 2006.281.07:51:12.80#ibcon#*before write, iclass 32, count 0 2006.281.07:51:12.80#ibcon#enter sib2, iclass 32, count 0 2006.281.07:51:12.80#ibcon#flushed, iclass 32, count 0 2006.281.07:51:12.80#ibcon#about to write, iclass 32, count 0 2006.281.07:51:12.80#ibcon#wrote, iclass 32, count 0 2006.281.07:51:12.80#ibcon#about to read 3, iclass 32, count 0 2006.281.07:51:12.83#ibcon#read 3, iclass 32, count 0 2006.281.07:51:12.83#ibcon#about to read 4, iclass 32, count 0 2006.281.07:51:12.83#ibcon#read 4, iclass 32, count 0 2006.281.07:51:12.83#ibcon#about to read 5, iclass 32, count 0 2006.281.07:51:12.83#ibcon#read 5, iclass 32, count 0 2006.281.07:51:12.83#ibcon#about to read 6, iclass 32, count 0 2006.281.07:51:12.83#ibcon#read 6, iclass 32, count 0 2006.281.07:51:12.83#ibcon#end of sib2, iclass 32, count 0 2006.281.07:51:12.83#ibcon#*after write, iclass 32, count 0 2006.281.07:51:12.83#ibcon#*before return 0, iclass 32, count 0 2006.281.07:51:12.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:51:12.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:51:12.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:51:12.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:51:12.83$vc4f8/vblo=3,656.99 2006.281.07:51:12.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:51:12.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:51:12.83#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:12.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:12.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:12.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:12.83#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:51:12.83#ibcon#first serial, iclass 35, count 0 2006.281.07:51:12.83#ibcon#enter sib2, iclass 35, count 0 2006.281.07:51:12.83#ibcon#flushed, iclass 35, count 0 2006.281.07:51:12.83#ibcon#about to write, iclass 35, count 0 2006.281.07:51:12.83#ibcon#wrote, iclass 35, count 0 2006.281.07:51:12.83#ibcon#about to read 3, iclass 35, count 0 2006.281.07:51:12.85#ibcon#read 3, iclass 35, count 0 2006.281.07:51:12.85#ibcon#about to read 4, iclass 35, count 0 2006.281.07:51:12.85#ibcon#read 4, iclass 35, count 0 2006.281.07:51:12.85#ibcon#about to read 5, iclass 35, count 0 2006.281.07:51:12.85#ibcon#read 5, iclass 35, count 0 2006.281.07:51:12.85#ibcon#about to read 6, iclass 35, count 0 2006.281.07:51:12.85#ibcon#read 6, iclass 35, count 0 2006.281.07:51:12.85#ibcon#end of sib2, iclass 35, count 0 2006.281.07:51:12.85#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:51:12.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:51:12.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:51:12.85#ibcon#*before write, iclass 35, count 0 2006.281.07:51:12.85#ibcon#enter sib2, iclass 35, count 0 2006.281.07:51:12.85#ibcon#flushed, iclass 35, count 0 2006.281.07:51:12.85#ibcon#about to write, iclass 35, count 0 2006.281.07:51:12.85#ibcon#wrote, iclass 35, count 0 2006.281.07:51:12.85#ibcon#about to read 3, iclass 35, count 0 2006.281.07:51:12.90#ibcon#read 3, iclass 35, count 0 2006.281.07:51:12.90#ibcon#about to read 4, iclass 35, count 0 2006.281.07:51:12.90#ibcon#read 4, iclass 35, count 0 2006.281.07:51:12.90#ibcon#about to read 5, iclass 35, count 0 2006.281.07:51:12.90#ibcon#read 5, iclass 35, count 0 2006.281.07:51:12.90#ibcon#about to read 6, iclass 35, count 0 2006.281.07:51:12.90#ibcon#read 6, iclass 35, count 0 2006.281.07:51:12.90#ibcon#end of sib2, iclass 35, count 0 2006.281.07:51:12.90#ibcon#*after write, iclass 35, count 0 2006.281.07:51:12.90#ibcon#*before return 0, iclass 35, count 0 2006.281.07:51:12.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:12.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:51:12.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:51:12.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:51:12.90$vc4f8/vb=3,4 2006.281.07:51:12.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:51:12.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:51:12.90#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:12.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:12.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:12.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:12.95#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:51:12.95#ibcon#first serial, iclass 37, count 2 2006.281.07:51:12.95#ibcon#enter sib2, iclass 37, count 2 2006.281.07:51:12.95#ibcon#flushed, iclass 37, count 2 2006.281.07:51:12.95#ibcon#about to write, iclass 37, count 2 2006.281.07:51:12.95#ibcon#wrote, iclass 37, count 2 2006.281.07:51:12.95#ibcon#about to read 3, iclass 37, count 2 2006.281.07:51:12.97#ibcon#read 3, iclass 37, count 2 2006.281.07:51:12.97#ibcon#about to read 4, iclass 37, count 2 2006.281.07:51:12.97#ibcon#read 4, iclass 37, count 2 2006.281.07:51:12.97#ibcon#about to read 5, iclass 37, count 2 2006.281.07:51:12.97#ibcon#read 5, iclass 37, count 2 2006.281.07:51:12.97#ibcon#about to read 6, iclass 37, count 2 2006.281.07:51:12.97#ibcon#read 6, iclass 37, count 2 2006.281.07:51:12.97#ibcon#end of sib2, iclass 37, count 2 2006.281.07:51:12.97#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:51:12.97#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:51:12.97#ibcon#[27=AT03-04\r\n] 2006.281.07:51:12.97#ibcon#*before write, iclass 37, count 2 2006.281.07:51:12.97#ibcon#enter sib2, iclass 37, count 2 2006.281.07:51:12.97#ibcon#flushed, iclass 37, count 2 2006.281.07:51:12.97#ibcon#about to write, iclass 37, count 2 2006.281.07:51:12.97#ibcon#wrote, iclass 37, count 2 2006.281.07:51:12.97#ibcon#about to read 3, iclass 37, count 2 2006.281.07:51:13.00#ibcon#read 3, iclass 37, count 2 2006.281.07:51:13.00#ibcon#about to read 4, iclass 37, count 2 2006.281.07:51:13.00#ibcon#read 4, iclass 37, count 2 2006.281.07:51:13.00#ibcon#about to read 5, iclass 37, count 2 2006.281.07:51:13.00#ibcon#read 5, iclass 37, count 2 2006.281.07:51:13.00#ibcon#about to read 6, iclass 37, count 2 2006.281.07:51:13.00#ibcon#read 6, iclass 37, count 2 2006.281.07:51:13.00#ibcon#end of sib2, iclass 37, count 2 2006.281.07:51:13.00#ibcon#*after write, iclass 37, count 2 2006.281.07:51:13.00#ibcon#*before return 0, iclass 37, count 2 2006.281.07:51:13.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:13.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:51:13.00#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:51:13.00#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:13.00#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:13.12#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:13.12#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:13.12#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:51:13.12#ibcon#first serial, iclass 37, count 0 2006.281.07:51:13.12#ibcon#enter sib2, iclass 37, count 0 2006.281.07:51:13.12#ibcon#flushed, iclass 37, count 0 2006.281.07:51:13.12#ibcon#about to write, iclass 37, count 0 2006.281.07:51:13.12#ibcon#wrote, iclass 37, count 0 2006.281.07:51:13.12#ibcon#about to read 3, iclass 37, count 0 2006.281.07:51:13.14#ibcon#read 3, iclass 37, count 0 2006.281.07:51:13.14#ibcon#about to read 4, iclass 37, count 0 2006.281.07:51:13.14#ibcon#read 4, iclass 37, count 0 2006.281.07:51:13.14#ibcon#about to read 5, iclass 37, count 0 2006.281.07:51:13.14#ibcon#read 5, iclass 37, count 0 2006.281.07:51:13.14#ibcon#about to read 6, iclass 37, count 0 2006.281.07:51:13.14#ibcon#read 6, iclass 37, count 0 2006.281.07:51:13.14#ibcon#end of sib2, iclass 37, count 0 2006.281.07:51:13.14#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:51:13.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:51:13.14#ibcon#[27=USB\r\n] 2006.281.07:51:13.14#ibcon#*before write, iclass 37, count 0 2006.281.07:51:13.14#ibcon#enter sib2, iclass 37, count 0 2006.281.07:51:13.14#ibcon#flushed, iclass 37, count 0 2006.281.07:51:13.14#ibcon#about to write, iclass 37, count 0 2006.281.07:51:13.14#ibcon#wrote, iclass 37, count 0 2006.281.07:51:13.14#ibcon#about to read 3, iclass 37, count 0 2006.281.07:51:13.17#ibcon#read 3, iclass 37, count 0 2006.281.07:51:13.17#ibcon#about to read 4, iclass 37, count 0 2006.281.07:51:13.17#ibcon#read 4, iclass 37, count 0 2006.281.07:51:13.17#ibcon#about to read 5, iclass 37, count 0 2006.281.07:51:13.17#ibcon#read 5, iclass 37, count 0 2006.281.07:51:13.17#ibcon#about to read 6, iclass 37, count 0 2006.281.07:51:13.17#ibcon#read 6, iclass 37, count 0 2006.281.07:51:13.17#ibcon#end of sib2, iclass 37, count 0 2006.281.07:51:13.17#ibcon#*after write, iclass 37, count 0 2006.281.07:51:13.17#ibcon#*before return 0, iclass 37, count 0 2006.281.07:51:13.17#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:13.17#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:51:13.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:51:13.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:51:13.17$vc4f8/vblo=4,712.99 2006.281.07:51:13.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:51:13.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:51:13.17#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:13.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:13.17#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:13.17#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:13.17#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:51:13.17#ibcon#first serial, iclass 39, count 0 2006.281.07:51:13.17#ibcon#enter sib2, iclass 39, count 0 2006.281.07:51:13.17#ibcon#flushed, iclass 39, count 0 2006.281.07:51:13.17#ibcon#about to write, iclass 39, count 0 2006.281.07:51:13.17#ibcon#wrote, iclass 39, count 0 2006.281.07:51:13.17#ibcon#about to read 3, iclass 39, count 0 2006.281.07:51:13.19#ibcon#read 3, iclass 39, count 0 2006.281.07:51:13.19#ibcon#about to read 4, iclass 39, count 0 2006.281.07:51:13.19#ibcon#read 4, iclass 39, count 0 2006.281.07:51:13.19#ibcon#about to read 5, iclass 39, count 0 2006.281.07:51:13.19#ibcon#read 5, iclass 39, count 0 2006.281.07:51:13.19#ibcon#about to read 6, iclass 39, count 0 2006.281.07:51:13.19#ibcon#read 6, iclass 39, count 0 2006.281.07:51:13.19#ibcon#end of sib2, iclass 39, count 0 2006.281.07:51:13.19#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:51:13.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:51:13.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:51:13.19#ibcon#*before write, iclass 39, count 0 2006.281.07:51:13.19#ibcon#enter sib2, iclass 39, count 0 2006.281.07:51:13.19#ibcon#flushed, iclass 39, count 0 2006.281.07:51:13.19#ibcon#about to write, iclass 39, count 0 2006.281.07:51:13.19#ibcon#wrote, iclass 39, count 0 2006.281.07:51:13.19#ibcon#about to read 3, iclass 39, count 0 2006.281.07:51:13.23#ibcon#read 3, iclass 39, count 0 2006.281.07:51:13.23#ibcon#about to read 4, iclass 39, count 0 2006.281.07:51:13.23#ibcon#read 4, iclass 39, count 0 2006.281.07:51:13.23#ibcon#about to read 5, iclass 39, count 0 2006.281.07:51:13.23#ibcon#read 5, iclass 39, count 0 2006.281.07:51:13.23#ibcon#about to read 6, iclass 39, count 0 2006.281.07:51:13.23#ibcon#read 6, iclass 39, count 0 2006.281.07:51:13.23#ibcon#end of sib2, iclass 39, count 0 2006.281.07:51:13.23#ibcon#*after write, iclass 39, count 0 2006.281.07:51:13.23#ibcon#*before return 0, iclass 39, count 0 2006.281.07:51:13.23#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:13.23#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:51:13.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:51:13.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:51:13.23$vc4f8/vb=4,4 2006.281.07:51:13.23#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:51:13.23#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:51:13.23#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:13.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:13.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:13.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:13.29#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:51:13.29#ibcon#first serial, iclass 3, count 2 2006.281.07:51:13.29#ibcon#enter sib2, iclass 3, count 2 2006.281.07:51:13.29#ibcon#flushed, iclass 3, count 2 2006.281.07:51:13.29#ibcon#about to write, iclass 3, count 2 2006.281.07:51:13.29#ibcon#wrote, iclass 3, count 2 2006.281.07:51:13.29#ibcon#about to read 3, iclass 3, count 2 2006.281.07:51:13.31#ibcon#read 3, iclass 3, count 2 2006.281.07:51:13.31#ibcon#about to read 4, iclass 3, count 2 2006.281.07:51:13.31#ibcon#read 4, iclass 3, count 2 2006.281.07:51:13.31#ibcon#about to read 5, iclass 3, count 2 2006.281.07:51:13.31#ibcon#read 5, iclass 3, count 2 2006.281.07:51:13.31#ibcon#about to read 6, iclass 3, count 2 2006.281.07:51:13.31#ibcon#read 6, iclass 3, count 2 2006.281.07:51:13.31#ibcon#end of sib2, iclass 3, count 2 2006.281.07:51:13.31#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:51:13.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:51:13.31#ibcon#[27=AT04-04\r\n] 2006.281.07:51:13.31#ibcon#*before write, iclass 3, count 2 2006.281.07:51:13.31#ibcon#enter sib2, iclass 3, count 2 2006.281.07:51:13.31#ibcon#flushed, iclass 3, count 2 2006.281.07:51:13.31#ibcon#about to write, iclass 3, count 2 2006.281.07:51:13.31#ibcon#wrote, iclass 3, count 2 2006.281.07:51:13.31#ibcon#about to read 3, iclass 3, count 2 2006.281.07:51:13.34#ibcon#read 3, iclass 3, count 2 2006.281.07:51:13.34#ibcon#about to read 4, iclass 3, count 2 2006.281.07:51:13.34#ibcon#read 4, iclass 3, count 2 2006.281.07:51:13.34#ibcon#about to read 5, iclass 3, count 2 2006.281.07:51:13.34#ibcon#read 5, iclass 3, count 2 2006.281.07:51:13.34#ibcon#about to read 6, iclass 3, count 2 2006.281.07:51:13.34#ibcon#read 6, iclass 3, count 2 2006.281.07:51:13.34#ibcon#end of sib2, iclass 3, count 2 2006.281.07:51:13.34#ibcon#*after write, iclass 3, count 2 2006.281.07:51:13.34#ibcon#*before return 0, iclass 3, count 2 2006.281.07:51:13.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:13.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:51:13.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:51:13.34#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:13.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:13.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:13.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:13.46#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:51:13.46#ibcon#first serial, iclass 3, count 0 2006.281.07:51:13.46#ibcon#enter sib2, iclass 3, count 0 2006.281.07:51:13.46#ibcon#flushed, iclass 3, count 0 2006.281.07:51:13.46#ibcon#about to write, iclass 3, count 0 2006.281.07:51:13.46#ibcon#wrote, iclass 3, count 0 2006.281.07:51:13.46#ibcon#about to read 3, iclass 3, count 0 2006.281.07:51:13.48#ibcon#read 3, iclass 3, count 0 2006.281.07:51:13.48#ibcon#about to read 4, iclass 3, count 0 2006.281.07:51:13.48#ibcon#read 4, iclass 3, count 0 2006.281.07:51:13.48#ibcon#about to read 5, iclass 3, count 0 2006.281.07:51:13.48#ibcon#read 5, iclass 3, count 0 2006.281.07:51:13.48#ibcon#about to read 6, iclass 3, count 0 2006.281.07:51:13.48#ibcon#read 6, iclass 3, count 0 2006.281.07:51:13.48#ibcon#end of sib2, iclass 3, count 0 2006.281.07:51:13.48#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:51:13.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:51:13.48#ibcon#[27=USB\r\n] 2006.281.07:51:13.48#ibcon#*before write, iclass 3, count 0 2006.281.07:51:13.48#ibcon#enter sib2, iclass 3, count 0 2006.281.07:51:13.48#ibcon#flushed, iclass 3, count 0 2006.281.07:51:13.48#ibcon#about to write, iclass 3, count 0 2006.281.07:51:13.48#ibcon#wrote, iclass 3, count 0 2006.281.07:51:13.48#ibcon#about to read 3, iclass 3, count 0 2006.281.07:51:13.51#ibcon#read 3, iclass 3, count 0 2006.281.07:51:13.51#ibcon#about to read 4, iclass 3, count 0 2006.281.07:51:13.51#ibcon#read 4, iclass 3, count 0 2006.281.07:51:13.51#ibcon#about to read 5, iclass 3, count 0 2006.281.07:51:13.51#ibcon#read 5, iclass 3, count 0 2006.281.07:51:13.51#ibcon#about to read 6, iclass 3, count 0 2006.281.07:51:13.51#ibcon#read 6, iclass 3, count 0 2006.281.07:51:13.51#ibcon#end of sib2, iclass 3, count 0 2006.281.07:51:13.51#ibcon#*after write, iclass 3, count 0 2006.281.07:51:13.51#ibcon#*before return 0, iclass 3, count 0 2006.281.07:51:13.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:13.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:51:13.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:51:13.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:51:13.51$vc4f8/vblo=5,744.99 2006.281.07:51:13.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:51:13.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:51:13.51#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:13.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:13.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:13.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:13.51#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:51:13.51#ibcon#first serial, iclass 5, count 0 2006.281.07:51:13.51#ibcon#enter sib2, iclass 5, count 0 2006.281.07:51:13.51#ibcon#flushed, iclass 5, count 0 2006.281.07:51:13.51#ibcon#about to write, iclass 5, count 0 2006.281.07:51:13.51#ibcon#wrote, iclass 5, count 0 2006.281.07:51:13.51#ibcon#about to read 3, iclass 5, count 0 2006.281.07:51:13.53#ibcon#read 3, iclass 5, count 0 2006.281.07:51:13.53#ibcon#about to read 4, iclass 5, count 0 2006.281.07:51:13.53#ibcon#read 4, iclass 5, count 0 2006.281.07:51:13.53#ibcon#about to read 5, iclass 5, count 0 2006.281.07:51:13.53#ibcon#read 5, iclass 5, count 0 2006.281.07:51:13.53#ibcon#about to read 6, iclass 5, count 0 2006.281.07:51:13.53#ibcon#read 6, iclass 5, count 0 2006.281.07:51:13.53#ibcon#end of sib2, iclass 5, count 0 2006.281.07:51:13.53#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:51:13.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:51:13.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:51:13.53#ibcon#*before write, iclass 5, count 0 2006.281.07:51:13.53#ibcon#enter sib2, iclass 5, count 0 2006.281.07:51:13.53#ibcon#flushed, iclass 5, count 0 2006.281.07:51:13.53#ibcon#about to write, iclass 5, count 0 2006.281.07:51:13.53#ibcon#wrote, iclass 5, count 0 2006.281.07:51:13.53#ibcon#about to read 3, iclass 5, count 0 2006.281.07:51:13.57#ibcon#read 3, iclass 5, count 0 2006.281.07:51:13.57#ibcon#about to read 4, iclass 5, count 0 2006.281.07:51:13.57#ibcon#read 4, iclass 5, count 0 2006.281.07:51:13.57#ibcon#about to read 5, iclass 5, count 0 2006.281.07:51:13.57#ibcon#read 5, iclass 5, count 0 2006.281.07:51:13.57#ibcon#about to read 6, iclass 5, count 0 2006.281.07:51:13.57#ibcon#read 6, iclass 5, count 0 2006.281.07:51:13.57#ibcon#end of sib2, iclass 5, count 0 2006.281.07:51:13.57#ibcon#*after write, iclass 5, count 0 2006.281.07:51:13.57#ibcon#*before return 0, iclass 5, count 0 2006.281.07:51:13.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:13.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:51:13.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:51:13.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:51:13.57$vc4f8/vb=5,4 2006.281.07:51:13.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:51:13.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:51:13.58#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:13.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:13.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:13.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:13.63#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:51:13.63#ibcon#first serial, iclass 7, count 2 2006.281.07:51:13.63#ibcon#enter sib2, iclass 7, count 2 2006.281.07:51:13.63#ibcon#flushed, iclass 7, count 2 2006.281.07:51:13.63#ibcon#about to write, iclass 7, count 2 2006.281.07:51:13.63#ibcon#wrote, iclass 7, count 2 2006.281.07:51:13.63#ibcon#about to read 3, iclass 7, count 2 2006.281.07:51:13.65#ibcon#read 3, iclass 7, count 2 2006.281.07:51:13.65#ibcon#about to read 4, iclass 7, count 2 2006.281.07:51:13.65#ibcon#read 4, iclass 7, count 2 2006.281.07:51:13.65#ibcon#about to read 5, iclass 7, count 2 2006.281.07:51:13.65#ibcon#read 5, iclass 7, count 2 2006.281.07:51:13.65#ibcon#about to read 6, iclass 7, count 2 2006.281.07:51:13.65#ibcon#read 6, iclass 7, count 2 2006.281.07:51:13.65#ibcon#end of sib2, iclass 7, count 2 2006.281.07:51:13.65#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:51:13.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:51:13.65#ibcon#[27=AT05-04\r\n] 2006.281.07:51:13.65#ibcon#*before write, iclass 7, count 2 2006.281.07:51:13.65#ibcon#enter sib2, iclass 7, count 2 2006.281.07:51:13.65#ibcon#flushed, iclass 7, count 2 2006.281.07:51:13.65#ibcon#about to write, iclass 7, count 2 2006.281.07:51:13.65#ibcon#wrote, iclass 7, count 2 2006.281.07:51:13.65#ibcon#about to read 3, iclass 7, count 2 2006.281.07:51:13.68#ibcon#read 3, iclass 7, count 2 2006.281.07:51:13.68#ibcon#about to read 4, iclass 7, count 2 2006.281.07:51:13.68#ibcon#read 4, iclass 7, count 2 2006.281.07:51:13.68#ibcon#about to read 5, iclass 7, count 2 2006.281.07:51:13.68#ibcon#read 5, iclass 7, count 2 2006.281.07:51:13.68#ibcon#about to read 6, iclass 7, count 2 2006.281.07:51:13.68#ibcon#read 6, iclass 7, count 2 2006.281.07:51:13.68#ibcon#end of sib2, iclass 7, count 2 2006.281.07:51:13.68#ibcon#*after write, iclass 7, count 2 2006.281.07:51:13.68#ibcon#*before return 0, iclass 7, count 2 2006.281.07:51:13.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:13.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:51:13.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:51:13.68#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:13.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:13.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:13.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:13.80#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:51:13.80#ibcon#first serial, iclass 7, count 0 2006.281.07:51:13.80#ibcon#enter sib2, iclass 7, count 0 2006.281.07:51:13.80#ibcon#flushed, iclass 7, count 0 2006.281.07:51:13.80#ibcon#about to write, iclass 7, count 0 2006.281.07:51:13.80#ibcon#wrote, iclass 7, count 0 2006.281.07:51:13.80#ibcon#about to read 3, iclass 7, count 0 2006.281.07:51:13.82#ibcon#read 3, iclass 7, count 0 2006.281.07:51:13.82#ibcon#about to read 4, iclass 7, count 0 2006.281.07:51:13.82#ibcon#read 4, iclass 7, count 0 2006.281.07:51:13.82#ibcon#about to read 5, iclass 7, count 0 2006.281.07:51:13.82#ibcon#read 5, iclass 7, count 0 2006.281.07:51:13.82#ibcon#about to read 6, iclass 7, count 0 2006.281.07:51:13.82#ibcon#read 6, iclass 7, count 0 2006.281.07:51:13.82#ibcon#end of sib2, iclass 7, count 0 2006.281.07:51:13.82#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:51:13.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:51:13.82#ibcon#[27=USB\r\n] 2006.281.07:51:13.82#ibcon#*before write, iclass 7, count 0 2006.281.07:51:13.82#ibcon#enter sib2, iclass 7, count 0 2006.281.07:51:13.82#ibcon#flushed, iclass 7, count 0 2006.281.07:51:13.82#ibcon#about to write, iclass 7, count 0 2006.281.07:51:13.82#ibcon#wrote, iclass 7, count 0 2006.281.07:51:13.82#ibcon#about to read 3, iclass 7, count 0 2006.281.07:51:13.85#ibcon#read 3, iclass 7, count 0 2006.281.07:51:13.86#ibcon#about to read 4, iclass 7, count 0 2006.281.07:51:13.86#ibcon#read 4, iclass 7, count 0 2006.281.07:51:13.86#ibcon#about to read 5, iclass 7, count 0 2006.281.07:51:13.86#ibcon#read 5, iclass 7, count 0 2006.281.07:51:13.86#ibcon#about to read 6, iclass 7, count 0 2006.281.07:51:13.86#ibcon#read 6, iclass 7, count 0 2006.281.07:51:13.86#ibcon#end of sib2, iclass 7, count 0 2006.281.07:51:13.86#ibcon#*after write, iclass 7, count 0 2006.281.07:51:13.86#ibcon#*before return 0, iclass 7, count 0 2006.281.07:51:13.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:13.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:51:13.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:51:13.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:51:13.86$vc4f8/vblo=6,752.99 2006.281.07:51:13.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:51:13.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:51:13.86#ibcon#ireg 17 cls_cnt 0 2006.281.07:51:13.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:13.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:13.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:13.86#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:51:13.86#ibcon#first serial, iclass 11, count 0 2006.281.07:51:13.86#ibcon#enter sib2, iclass 11, count 0 2006.281.07:51:13.86#ibcon#flushed, iclass 11, count 0 2006.281.07:51:13.86#ibcon#about to write, iclass 11, count 0 2006.281.07:51:13.86#ibcon#wrote, iclass 11, count 0 2006.281.07:51:13.86#ibcon#about to read 3, iclass 11, count 0 2006.281.07:51:13.87#ibcon#read 3, iclass 11, count 0 2006.281.07:51:13.87#ibcon#about to read 4, iclass 11, count 0 2006.281.07:51:13.87#ibcon#read 4, iclass 11, count 0 2006.281.07:51:13.87#ibcon#about to read 5, iclass 11, count 0 2006.281.07:51:13.87#ibcon#read 5, iclass 11, count 0 2006.281.07:51:13.87#ibcon#about to read 6, iclass 11, count 0 2006.281.07:51:13.87#ibcon#read 6, iclass 11, count 0 2006.281.07:51:13.88#ibcon#end of sib2, iclass 11, count 0 2006.281.07:51:13.88#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:51:13.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:51:13.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:51:13.88#ibcon#*before write, iclass 11, count 0 2006.281.07:51:13.88#ibcon#enter sib2, iclass 11, count 0 2006.281.07:51:13.88#ibcon#flushed, iclass 11, count 0 2006.281.07:51:13.88#ibcon#about to write, iclass 11, count 0 2006.281.07:51:13.88#ibcon#wrote, iclass 11, count 0 2006.281.07:51:13.88#ibcon#about to read 3, iclass 11, count 0 2006.281.07:51:13.92#ibcon#read 3, iclass 11, count 0 2006.281.07:51:13.92#ibcon#about to read 4, iclass 11, count 0 2006.281.07:51:13.92#ibcon#read 4, iclass 11, count 0 2006.281.07:51:13.92#ibcon#about to read 5, iclass 11, count 0 2006.281.07:51:13.92#ibcon#read 5, iclass 11, count 0 2006.281.07:51:13.92#ibcon#about to read 6, iclass 11, count 0 2006.281.07:51:13.92#ibcon#read 6, iclass 11, count 0 2006.281.07:51:13.92#ibcon#end of sib2, iclass 11, count 0 2006.281.07:51:13.92#ibcon#*after write, iclass 11, count 0 2006.281.07:51:13.92#ibcon#*before return 0, iclass 11, count 0 2006.281.07:51:13.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:13.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:51:13.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:51:13.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:51:13.92$vc4f8/vb=6,4 2006.281.07:51:13.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:51:13.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:51:13.92#ibcon#ireg 11 cls_cnt 2 2006.281.07:51:13.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:13.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:13.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:13.98#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:51:13.98#ibcon#first serial, iclass 13, count 2 2006.281.07:51:13.98#ibcon#enter sib2, iclass 13, count 2 2006.281.07:51:13.98#ibcon#flushed, iclass 13, count 2 2006.281.07:51:13.98#ibcon#about to write, iclass 13, count 2 2006.281.07:51:13.98#ibcon#wrote, iclass 13, count 2 2006.281.07:51:13.98#ibcon#about to read 3, iclass 13, count 2 2006.281.07:51:14.00#ibcon#read 3, iclass 13, count 2 2006.281.07:51:14.00#ibcon#about to read 4, iclass 13, count 2 2006.281.07:51:14.00#ibcon#read 4, iclass 13, count 2 2006.281.07:51:14.00#ibcon#about to read 5, iclass 13, count 2 2006.281.07:51:14.00#ibcon#read 5, iclass 13, count 2 2006.281.07:51:14.00#ibcon#about to read 6, iclass 13, count 2 2006.281.07:51:14.00#ibcon#read 6, iclass 13, count 2 2006.281.07:51:14.00#ibcon#end of sib2, iclass 13, count 2 2006.281.07:51:14.00#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:51:14.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:51:14.00#ibcon#[27=AT06-04\r\n] 2006.281.07:51:14.00#ibcon#*before write, iclass 13, count 2 2006.281.07:51:14.00#ibcon#enter sib2, iclass 13, count 2 2006.281.07:51:14.00#ibcon#flushed, iclass 13, count 2 2006.281.07:51:14.00#ibcon#about to write, iclass 13, count 2 2006.281.07:51:14.00#ibcon#wrote, iclass 13, count 2 2006.281.07:51:14.00#ibcon#about to read 3, iclass 13, count 2 2006.281.07:51:14.03#ibcon#read 3, iclass 13, count 2 2006.281.07:51:14.03#ibcon#about to read 4, iclass 13, count 2 2006.281.07:51:14.03#ibcon#read 4, iclass 13, count 2 2006.281.07:51:14.03#ibcon#about to read 5, iclass 13, count 2 2006.281.07:51:14.03#ibcon#read 5, iclass 13, count 2 2006.281.07:51:14.03#ibcon#about to read 6, iclass 13, count 2 2006.281.07:51:14.03#ibcon#read 6, iclass 13, count 2 2006.281.07:51:14.03#ibcon#end of sib2, iclass 13, count 2 2006.281.07:51:14.03#ibcon#*after write, iclass 13, count 2 2006.281.07:51:14.03#ibcon#*before return 0, iclass 13, count 2 2006.281.07:51:14.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:14.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:51:14.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:51:14.03#ibcon#ireg 7 cls_cnt 0 2006.281.07:51:14.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:14.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:14.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:14.15#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:51:14.15#ibcon#first serial, iclass 13, count 0 2006.281.07:51:14.15#ibcon#enter sib2, iclass 13, count 0 2006.281.07:51:14.15#ibcon#flushed, iclass 13, count 0 2006.281.07:51:14.15#ibcon#about to write, iclass 13, count 0 2006.281.07:51:14.15#ibcon#wrote, iclass 13, count 0 2006.281.07:51:14.15#ibcon#about to read 3, iclass 13, count 0 2006.281.07:51:14.17#ibcon#read 3, iclass 13, count 0 2006.281.07:51:14.17#ibcon#about to read 4, iclass 13, count 0 2006.281.07:51:14.17#ibcon#read 4, iclass 13, count 0 2006.281.07:51:14.17#ibcon#about to read 5, iclass 13, count 0 2006.281.07:51:14.17#ibcon#read 5, iclass 13, count 0 2006.281.07:51:14.17#ibcon#about to read 6, iclass 13, count 0 2006.281.07:51:14.17#ibcon#read 6, iclass 13, count 0 2006.281.07:51:14.17#ibcon#end of sib2, iclass 13, count 0 2006.281.07:51:14.17#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:51:14.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:51:14.17#ibcon#[27=USB\r\n] 2006.281.07:51:14.17#ibcon#*before write, iclass 13, count 0 2006.281.07:51:14.17#ibcon#enter sib2, iclass 13, count 0 2006.281.07:51:14.17#ibcon#flushed, iclass 13, count 0 2006.281.07:51:14.17#ibcon#about to write, iclass 13, count 0 2006.281.07:51:14.17#ibcon#wrote, iclass 13, count 0 2006.281.07:51:14.17#ibcon#about to read 3, iclass 13, count 0 2006.281.07:51:14.20#ibcon#read 3, iclass 13, count 0 2006.281.07:51:14.20#ibcon#about to read 4, iclass 13, count 0 2006.281.07:51:14.20#ibcon#read 4, iclass 13, count 0 2006.281.07:51:14.20#ibcon#about to read 5, iclass 13, count 0 2006.281.07:51:14.20#ibcon#read 5, iclass 13, count 0 2006.281.07:51:14.20#ibcon#about to read 6, iclass 13, count 0 2006.281.07:51:14.20#ibcon#read 6, iclass 13, count 0 2006.281.07:51:14.20#ibcon#end of sib2, iclass 13, count 0 2006.281.07:51:14.20#ibcon#*after write, iclass 13, count 0 2006.281.07:51:14.20#ibcon#*before return 0, iclass 13, count 0 2006.281.07:51:14.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:14.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:51:14.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:51:14.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:51:14.20$vc4f8/vabw=wide 2006.281.07:51:14.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:51:14.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:51:14.20#ibcon#ireg 8 cls_cnt 0 2006.281.07:51:14.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:14.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:14.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:14.20#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:51:14.20#ibcon#first serial, iclass 15, count 0 2006.281.07:51:14.20#ibcon#enter sib2, iclass 15, count 0 2006.281.07:51:14.20#ibcon#flushed, iclass 15, count 0 2006.281.07:51:14.20#ibcon#about to write, iclass 15, count 0 2006.281.07:51:14.20#ibcon#wrote, iclass 15, count 0 2006.281.07:51:14.20#ibcon#about to read 3, iclass 15, count 0 2006.281.07:51:14.22#ibcon#read 3, iclass 15, count 0 2006.281.07:51:14.22#ibcon#about to read 4, iclass 15, count 0 2006.281.07:51:14.22#ibcon#read 4, iclass 15, count 0 2006.281.07:51:14.22#ibcon#about to read 5, iclass 15, count 0 2006.281.07:51:14.22#ibcon#read 5, iclass 15, count 0 2006.281.07:51:14.22#ibcon#about to read 6, iclass 15, count 0 2006.281.07:51:14.22#ibcon#read 6, iclass 15, count 0 2006.281.07:51:14.22#ibcon#end of sib2, iclass 15, count 0 2006.281.07:51:14.22#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:51:14.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:51:14.22#ibcon#[25=BW32\r\n] 2006.281.07:51:14.22#ibcon#*before write, iclass 15, count 0 2006.281.07:51:14.22#ibcon#enter sib2, iclass 15, count 0 2006.281.07:51:14.22#ibcon#flushed, iclass 15, count 0 2006.281.07:51:14.22#ibcon#about to write, iclass 15, count 0 2006.281.07:51:14.22#ibcon#wrote, iclass 15, count 0 2006.281.07:51:14.22#ibcon#about to read 3, iclass 15, count 0 2006.281.07:51:14.25#ibcon#read 3, iclass 15, count 0 2006.281.07:51:14.25#ibcon#about to read 4, iclass 15, count 0 2006.281.07:51:14.25#ibcon#read 4, iclass 15, count 0 2006.281.07:51:14.25#ibcon#about to read 5, iclass 15, count 0 2006.281.07:51:14.25#ibcon#read 5, iclass 15, count 0 2006.281.07:51:14.25#ibcon#about to read 6, iclass 15, count 0 2006.281.07:51:14.25#ibcon#read 6, iclass 15, count 0 2006.281.07:51:14.25#ibcon#end of sib2, iclass 15, count 0 2006.281.07:51:14.25#ibcon#*after write, iclass 15, count 0 2006.281.07:51:14.25#ibcon#*before return 0, iclass 15, count 0 2006.281.07:51:14.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:14.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:51:14.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:51:14.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:51:14.25$vc4f8/vbbw=wide 2006.281.07:51:14.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.07:51:14.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.07:51:14.25#ibcon#ireg 8 cls_cnt 0 2006.281.07:51:14.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:51:14.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:51:14.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:51:14.32#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:51:14.32#ibcon#first serial, iclass 17, count 0 2006.281.07:51:14.32#ibcon#enter sib2, iclass 17, count 0 2006.281.07:51:14.32#ibcon#flushed, iclass 17, count 0 2006.281.07:51:14.32#ibcon#about to write, iclass 17, count 0 2006.281.07:51:14.32#ibcon#wrote, iclass 17, count 0 2006.281.07:51:14.32#ibcon#about to read 3, iclass 17, count 0 2006.281.07:51:14.34#ibcon#read 3, iclass 17, count 0 2006.281.07:51:14.34#ibcon#about to read 4, iclass 17, count 0 2006.281.07:51:14.34#ibcon#read 4, iclass 17, count 0 2006.281.07:51:14.34#ibcon#about to read 5, iclass 17, count 0 2006.281.07:51:14.34#ibcon#read 5, iclass 17, count 0 2006.281.07:51:14.34#ibcon#about to read 6, iclass 17, count 0 2006.281.07:51:14.34#ibcon#read 6, iclass 17, count 0 2006.281.07:51:14.34#ibcon#end of sib2, iclass 17, count 0 2006.281.07:51:14.34#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:51:14.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:51:14.34#ibcon#[27=BW32\r\n] 2006.281.07:51:14.34#ibcon#*before write, iclass 17, count 0 2006.281.07:51:14.34#ibcon#enter sib2, iclass 17, count 0 2006.281.07:51:14.34#ibcon#flushed, iclass 17, count 0 2006.281.07:51:14.34#ibcon#about to write, iclass 17, count 0 2006.281.07:51:14.34#ibcon#wrote, iclass 17, count 0 2006.281.07:51:14.34#ibcon#about to read 3, iclass 17, count 0 2006.281.07:51:14.37#ibcon#read 3, iclass 17, count 0 2006.281.07:51:14.37#ibcon#about to read 4, iclass 17, count 0 2006.281.07:51:14.37#ibcon#read 4, iclass 17, count 0 2006.281.07:51:14.37#ibcon#about to read 5, iclass 17, count 0 2006.281.07:51:14.37#ibcon#read 5, iclass 17, count 0 2006.281.07:51:14.37#ibcon#about to read 6, iclass 17, count 0 2006.281.07:51:14.37#ibcon#read 6, iclass 17, count 0 2006.281.07:51:14.37#ibcon#end of sib2, iclass 17, count 0 2006.281.07:51:14.37#ibcon#*after write, iclass 17, count 0 2006.281.07:51:14.37#ibcon#*before return 0, iclass 17, count 0 2006.281.07:51:14.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:51:14.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.07:51:14.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:51:14.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:51:14.37$4f8m12a/ifd4f 2006.281.07:51:14.38$ifd4f/lo= 2006.281.07:51:14.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:51:14.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:51:14.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:51:14.38$ifd4f/patch= 2006.281.07:51:14.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:51:14.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:51:14.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:51:14.38$4f8m12a/"form=m,16.000,1:2 2006.281.07:51:14.38$4f8m12a/"tpicd 2006.281.07:51:14.38$4f8m12a/echo=off 2006.281.07:51:14.38$4f8m12a/xlog=off 2006.281.07:51:14.38:!2006.281.07:51:40 2006.281.07:51:16.13#trakl#Source acquired 2006.281.07:51:16.13#flagr#flagr/antenna,acquired 2006.281.07:51:40.01:preob 2006.281.07:51:41.14/onsource/TRACKING 2006.281.07:51:41.14:!2006.281.07:51:50 2006.281.07:51:48.14#trakl#Off source 2006.281.07:51:48.14?ERROR st -7 Antenna off-source! 2006.281.07:51:48.14#trakl#az 288.138 el 70.259 azerr*cos(el) -0.0017 elerr -0.0166 2006.281.07:51:48.14#flagr#flagr/antenna,off-source 2006.281.07:51:50.00:data_valid=on 2006.281.07:51:50.00:midob 2006.281.07:51:50.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.07:51:50.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.07:51:50.14/onsource/SLEWING 2006.281.07:51:50.14/wx/20.85,1001.3,50 2006.281.07:51:50.31/cable/+6.4865E-03 2006.281.07:51:51.40/va/01,07,usb,yes,32,33 2006.281.07:51:51.40/va/02,06,usb,yes,29,31 2006.281.07:51:51.40/va/03,06,usb,yes,28,28 2006.281.07:51:51.40/va/04,06,usb,yes,30,33 2006.281.07:51:51.40/va/05,07,usb,yes,29,30 2006.281.07:51:51.40/va/06,06,usb,yes,28,27 2006.281.07:51:51.40/va/07,06,usb,yes,28,28 2006.281.07:51:51.40/va/08,06,usb,yes,30,30 2006.281.07:51:51.63/valo/01,532.99,yes,locked 2006.281.07:51:51.63/valo/02,572.99,yes,locked 2006.281.07:51:51.63/valo/03,672.99,yes,locked 2006.281.07:51:51.63/valo/04,832.99,yes,locked 2006.281.07:51:51.63/valo/05,652.99,yes,locked 2006.281.07:51:51.63/valo/06,772.99,yes,locked 2006.281.07:51:51.63/valo/07,832.99,yes,locked 2006.281.07:51:51.63/valo/08,852.99,yes,locked 2006.281.07:51:52.72/vb/01,04,usb,yes,30,29 2006.281.07:51:52.72/vb/02,05,usb,yes,28,29 2006.281.07:51:52.72/vb/03,04,usb,yes,28,32 2006.281.07:51:52.72/vb/04,04,usb,yes,29,29 2006.281.07:51:52.72/vb/05,04,usb,yes,27,31 2006.281.07:51:52.72/vb/06,04,usb,yes,27,31 2006.281.07:51:52.72/vb/07,04,usb,yes,30,30 2006.281.07:51:52.72/vb/08,04,usb,yes,27,31 2006.281.07:51:52.95/vblo/01,632.99,yes,locked 2006.281.07:51:52.95/vblo/02,640.99,yes,locked 2006.281.07:51:52.95/vblo/03,656.99,yes,locked 2006.281.07:51:52.95/vblo/04,712.99,yes,locked 2006.281.07:51:52.95/vblo/05,744.99,yes,locked 2006.281.07:51:52.95/vblo/06,752.99,yes,locked 2006.281.07:51:52.95/vblo/07,734.99,yes,locked 2006.281.07:51:52.95/vblo/08,744.99,yes,locked 2006.281.07:51:53.10/vabw/8 2006.281.07:51:53.25/vbbw/8 2006.281.07:51:53.58/xfe/off,on,12.0 2006.281.07:51:53.95/ifatt/23,28,28,28 2006.281.07:51:54.07/fmout-gps/S +3.03E-07 2006.281.07:51:54.09:!2006.281.07:52:50 2006.281.07:51:55.14#trakl#Source re-acquired 2006.281.07:51:55.14#flagr#flagr/antenna,re-acquired 2006.281.07:52:50.01:data_valid=off 2006.281.07:52:50.01:postob 2006.281.07:52:50.18/cable/+6.4852E-03 2006.281.07:52:50.18/wx/20.81,1001.3,51 2006.281.07:52:51.08/fmout-gps/S +3.03E-07 2006.281.07:52:51.08:scan_name=281-0754,k06281,60 2006.281.07:52:51.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.281.07:52:51.14#flagr#flagr/antenna,new-source 2006.281.07:52:52.14:checkk5 2006.281.07:52:52.99/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:52:53.38/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:52:53.82/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:52:54.24/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:52:54.67/chk_obsdata//k5ts1/T2810751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:52:55.16/chk_obsdata//k5ts2/T2810751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:52:55.59/chk_obsdata//k5ts3/T2810751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:52:56.07/chk_obsdata//k5ts4/T2810751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.07:52:57.07/k5log//k5ts1_log_newline 2006.281.07:52:57.87/k5log//k5ts2_log_newline 2006.281.07:52:58.70/k5log//k5ts3_log_newline 2006.281.07:52:59.53/k5log//k5ts4_log_newline 2006.281.07:52:59.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:52:59.55:4f8m12a=2 2006.281.07:52:59.55$4f8m12a/echo=on 2006.281.07:52:59.55$4f8m12a/pcalon 2006.281.07:52:59.55$pcalon/"no phase cal control is implemented here 2006.281.07:52:59.55$4f8m12a/"tpicd=stop 2006.281.07:52:59.55$4f8m12a/vc4f8 2006.281.07:52:59.55$vc4f8/valo=1,532.99 2006.281.07:52:59.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:52:59.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:52:59.56#ibcon#ireg 17 cls_cnt 0 2006.281.07:52:59.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:52:59.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:52:59.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:52:59.56#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:52:59.56#ibcon#first serial, iclass 30, count 0 2006.281.07:52:59.56#ibcon#enter sib2, iclass 30, count 0 2006.281.07:52:59.56#ibcon#flushed, iclass 30, count 0 2006.281.07:52:59.56#ibcon#about to write, iclass 30, count 0 2006.281.07:52:59.56#ibcon#wrote, iclass 30, count 0 2006.281.07:52:59.56#ibcon#about to read 3, iclass 30, count 0 2006.281.07:52:59.57#ibcon#read 3, iclass 30, count 0 2006.281.07:52:59.57#ibcon#about to read 4, iclass 30, count 0 2006.281.07:52:59.57#ibcon#read 4, iclass 30, count 0 2006.281.07:52:59.57#ibcon#about to read 5, iclass 30, count 0 2006.281.07:52:59.57#ibcon#read 5, iclass 30, count 0 2006.281.07:52:59.57#ibcon#about to read 6, iclass 30, count 0 2006.281.07:52:59.57#ibcon#read 6, iclass 30, count 0 2006.281.07:52:59.57#ibcon#end of sib2, iclass 30, count 0 2006.281.07:52:59.57#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:52:59.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:52:59.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:52:59.57#ibcon#*before write, iclass 30, count 0 2006.281.07:52:59.57#ibcon#enter sib2, iclass 30, count 0 2006.281.07:52:59.57#ibcon#flushed, iclass 30, count 0 2006.281.07:52:59.57#ibcon#about to write, iclass 30, count 0 2006.281.07:52:59.57#ibcon#wrote, iclass 30, count 0 2006.281.07:52:59.57#ibcon#about to read 3, iclass 30, count 0 2006.281.07:52:59.63#ibcon#read 3, iclass 30, count 0 2006.281.07:52:59.63#ibcon#about to read 4, iclass 30, count 0 2006.281.07:52:59.63#ibcon#read 4, iclass 30, count 0 2006.281.07:52:59.63#ibcon#about to read 5, iclass 30, count 0 2006.281.07:52:59.63#ibcon#read 5, iclass 30, count 0 2006.281.07:52:59.63#ibcon#about to read 6, iclass 30, count 0 2006.281.07:52:59.63#ibcon#read 6, iclass 30, count 0 2006.281.07:52:59.63#ibcon#end of sib2, iclass 30, count 0 2006.281.07:52:59.63#ibcon#*after write, iclass 30, count 0 2006.281.07:52:59.63#ibcon#*before return 0, iclass 30, count 0 2006.281.07:52:59.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:52:59.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:52:59.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:52:59.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:52:59.63$vc4f8/va=1,7 2006.281.07:52:59.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:52:59.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:52:59.63#ibcon#ireg 11 cls_cnt 2 2006.281.07:52:59.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:52:59.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:52:59.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:52:59.63#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:52:59.63#ibcon#first serial, iclass 32, count 2 2006.281.07:52:59.63#ibcon#enter sib2, iclass 32, count 2 2006.281.07:52:59.63#ibcon#flushed, iclass 32, count 2 2006.281.07:52:59.63#ibcon#about to write, iclass 32, count 2 2006.281.07:52:59.63#ibcon#wrote, iclass 32, count 2 2006.281.07:52:59.63#ibcon#about to read 3, iclass 32, count 2 2006.281.07:52:59.64#ibcon#read 3, iclass 32, count 2 2006.281.07:52:59.64#ibcon#about to read 4, iclass 32, count 2 2006.281.07:52:59.64#ibcon#read 4, iclass 32, count 2 2006.281.07:52:59.64#ibcon#about to read 5, iclass 32, count 2 2006.281.07:52:59.64#ibcon#read 5, iclass 32, count 2 2006.281.07:52:59.64#ibcon#about to read 6, iclass 32, count 2 2006.281.07:52:59.64#ibcon#read 6, iclass 32, count 2 2006.281.07:52:59.64#ibcon#end of sib2, iclass 32, count 2 2006.281.07:52:59.64#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:52:59.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:52:59.64#ibcon#[25=AT01-07\r\n] 2006.281.07:52:59.64#ibcon#*before write, iclass 32, count 2 2006.281.07:52:59.64#ibcon#enter sib2, iclass 32, count 2 2006.281.07:52:59.64#ibcon#flushed, iclass 32, count 2 2006.281.07:52:59.64#ibcon#about to write, iclass 32, count 2 2006.281.07:52:59.64#ibcon#wrote, iclass 32, count 2 2006.281.07:52:59.64#ibcon#about to read 3, iclass 32, count 2 2006.281.07:52:59.67#ibcon#read 3, iclass 32, count 2 2006.281.07:52:59.67#ibcon#about to read 4, iclass 32, count 2 2006.281.07:52:59.67#ibcon#read 4, iclass 32, count 2 2006.281.07:52:59.67#ibcon#about to read 5, iclass 32, count 2 2006.281.07:52:59.67#ibcon#read 5, iclass 32, count 2 2006.281.07:52:59.67#ibcon#about to read 6, iclass 32, count 2 2006.281.07:52:59.67#ibcon#read 6, iclass 32, count 2 2006.281.07:52:59.67#ibcon#end of sib2, iclass 32, count 2 2006.281.07:52:59.67#ibcon#*after write, iclass 32, count 2 2006.281.07:52:59.67#ibcon#*before return 0, iclass 32, count 2 2006.281.07:52:59.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:52:59.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:52:59.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:52:59.67#ibcon#ireg 7 cls_cnt 0 2006.281.07:52:59.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:52:59.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:52:59.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:52:59.79#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:52:59.79#ibcon#first serial, iclass 32, count 0 2006.281.07:52:59.79#ibcon#enter sib2, iclass 32, count 0 2006.281.07:52:59.79#ibcon#flushed, iclass 32, count 0 2006.281.07:52:59.79#ibcon#about to write, iclass 32, count 0 2006.281.07:52:59.79#ibcon#wrote, iclass 32, count 0 2006.281.07:52:59.79#ibcon#about to read 3, iclass 32, count 0 2006.281.07:52:59.82#ibcon#read 3, iclass 32, count 0 2006.281.07:52:59.82#ibcon#about to read 4, iclass 32, count 0 2006.281.07:52:59.82#ibcon#read 4, iclass 32, count 0 2006.281.07:52:59.82#ibcon#about to read 5, iclass 32, count 0 2006.281.07:52:59.82#ibcon#read 5, iclass 32, count 0 2006.281.07:52:59.82#ibcon#about to read 6, iclass 32, count 0 2006.281.07:52:59.82#ibcon#read 6, iclass 32, count 0 2006.281.07:52:59.82#ibcon#end of sib2, iclass 32, count 0 2006.281.07:52:59.82#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:52:59.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:52:59.82#ibcon#[25=USB\r\n] 2006.281.07:52:59.82#ibcon#*before write, iclass 32, count 0 2006.281.07:52:59.82#ibcon#enter sib2, iclass 32, count 0 2006.281.07:52:59.82#ibcon#flushed, iclass 32, count 0 2006.281.07:52:59.82#ibcon#about to write, iclass 32, count 0 2006.281.07:52:59.82#ibcon#wrote, iclass 32, count 0 2006.281.07:52:59.82#ibcon#about to read 3, iclass 32, count 0 2006.281.07:52:59.84#ibcon#read 3, iclass 32, count 0 2006.281.07:52:59.84#ibcon#about to read 4, iclass 32, count 0 2006.281.07:52:59.84#ibcon#read 4, iclass 32, count 0 2006.281.07:52:59.84#ibcon#about to read 5, iclass 32, count 0 2006.281.07:52:59.84#ibcon#read 5, iclass 32, count 0 2006.281.07:52:59.84#ibcon#about to read 6, iclass 32, count 0 2006.281.07:52:59.84#ibcon#read 6, iclass 32, count 0 2006.281.07:52:59.84#ibcon#end of sib2, iclass 32, count 0 2006.281.07:52:59.84#ibcon#*after write, iclass 32, count 0 2006.281.07:52:59.84#ibcon#*before return 0, iclass 32, count 0 2006.281.07:52:59.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:52:59.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:52:59.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:52:59.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:52:59.84$vc4f8/valo=2,572.99 2006.281.07:52:59.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:52:59.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:52:59.84#ibcon#ireg 17 cls_cnt 0 2006.281.07:52:59.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:52:59.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:52:59.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:52:59.84#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:52:59.84#ibcon#first serial, iclass 34, count 0 2006.281.07:52:59.84#ibcon#enter sib2, iclass 34, count 0 2006.281.07:52:59.84#ibcon#flushed, iclass 34, count 0 2006.281.07:52:59.84#ibcon#about to write, iclass 34, count 0 2006.281.07:52:59.84#ibcon#wrote, iclass 34, count 0 2006.281.07:52:59.84#ibcon#about to read 3, iclass 34, count 0 2006.281.07:52:59.86#ibcon#read 3, iclass 34, count 0 2006.281.07:52:59.86#ibcon#about to read 4, iclass 34, count 0 2006.281.07:52:59.86#ibcon#read 4, iclass 34, count 0 2006.281.07:52:59.86#ibcon#about to read 5, iclass 34, count 0 2006.281.07:52:59.86#ibcon#read 5, iclass 34, count 0 2006.281.07:52:59.86#ibcon#about to read 6, iclass 34, count 0 2006.281.07:52:59.86#ibcon#read 6, iclass 34, count 0 2006.281.07:52:59.86#ibcon#end of sib2, iclass 34, count 0 2006.281.07:52:59.86#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:52:59.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:52:59.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:52:59.86#ibcon#*before write, iclass 34, count 0 2006.281.07:52:59.86#ibcon#enter sib2, iclass 34, count 0 2006.281.07:52:59.86#ibcon#flushed, iclass 34, count 0 2006.281.07:52:59.86#ibcon#about to write, iclass 34, count 0 2006.281.07:52:59.86#ibcon#wrote, iclass 34, count 0 2006.281.07:52:59.86#ibcon#about to read 3, iclass 34, count 0 2006.281.07:52:59.90#ibcon#read 3, iclass 34, count 0 2006.281.07:52:59.90#ibcon#about to read 4, iclass 34, count 0 2006.281.07:52:59.90#ibcon#read 4, iclass 34, count 0 2006.281.07:52:59.90#ibcon#about to read 5, iclass 34, count 0 2006.281.07:52:59.90#ibcon#read 5, iclass 34, count 0 2006.281.07:52:59.90#ibcon#about to read 6, iclass 34, count 0 2006.281.07:52:59.90#ibcon#read 6, iclass 34, count 0 2006.281.07:52:59.90#ibcon#end of sib2, iclass 34, count 0 2006.281.07:52:59.90#ibcon#*after write, iclass 34, count 0 2006.281.07:52:59.90#ibcon#*before return 0, iclass 34, count 0 2006.281.07:52:59.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:52:59.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:52:59.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:52:59.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:52:59.90$vc4f8/va=2,6 2006.281.07:52:59.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:52:59.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:52:59.90#ibcon#ireg 11 cls_cnt 2 2006.281.07:52:59.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:52:59.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:52:59.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:52:59.96#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:52:59.96#ibcon#first serial, iclass 36, count 2 2006.281.07:52:59.96#ibcon#enter sib2, iclass 36, count 2 2006.281.07:52:59.96#ibcon#flushed, iclass 36, count 2 2006.281.07:52:59.96#ibcon#about to write, iclass 36, count 2 2006.281.07:52:59.96#ibcon#wrote, iclass 36, count 2 2006.281.07:52:59.96#ibcon#about to read 3, iclass 36, count 2 2006.281.07:52:59.98#ibcon#read 3, iclass 36, count 2 2006.281.07:52:59.98#ibcon#about to read 4, iclass 36, count 2 2006.281.07:52:59.98#ibcon#read 4, iclass 36, count 2 2006.281.07:52:59.98#ibcon#about to read 5, iclass 36, count 2 2006.281.07:52:59.98#ibcon#read 5, iclass 36, count 2 2006.281.07:52:59.98#ibcon#about to read 6, iclass 36, count 2 2006.281.07:52:59.98#ibcon#read 6, iclass 36, count 2 2006.281.07:52:59.98#ibcon#end of sib2, iclass 36, count 2 2006.281.07:52:59.98#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:52:59.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:52:59.98#ibcon#[25=AT02-06\r\n] 2006.281.07:52:59.98#ibcon#*before write, iclass 36, count 2 2006.281.07:52:59.98#ibcon#enter sib2, iclass 36, count 2 2006.281.07:52:59.98#ibcon#flushed, iclass 36, count 2 2006.281.07:52:59.98#ibcon#about to write, iclass 36, count 2 2006.281.07:52:59.98#ibcon#wrote, iclass 36, count 2 2006.281.07:52:59.98#ibcon#about to read 3, iclass 36, count 2 2006.281.07:53:00.01#ibcon#read 3, iclass 36, count 2 2006.281.07:53:00.01#ibcon#about to read 4, iclass 36, count 2 2006.281.07:53:00.01#ibcon#read 4, iclass 36, count 2 2006.281.07:53:00.01#ibcon#about to read 5, iclass 36, count 2 2006.281.07:53:00.01#ibcon#read 5, iclass 36, count 2 2006.281.07:53:00.01#ibcon#about to read 6, iclass 36, count 2 2006.281.07:53:00.01#ibcon#read 6, iclass 36, count 2 2006.281.07:53:00.01#ibcon#end of sib2, iclass 36, count 2 2006.281.07:53:00.01#ibcon#*after write, iclass 36, count 2 2006.281.07:53:00.01#ibcon#*before return 0, iclass 36, count 2 2006.281.07:53:00.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:00.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:00.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:53:00.01#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:00.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:00.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:00.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:00.13#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:53:00.13#ibcon#first serial, iclass 36, count 0 2006.281.07:53:00.13#ibcon#enter sib2, iclass 36, count 0 2006.281.07:53:00.13#ibcon#flushed, iclass 36, count 0 2006.281.07:53:00.13#ibcon#about to write, iclass 36, count 0 2006.281.07:53:00.13#ibcon#wrote, iclass 36, count 0 2006.281.07:53:00.13#ibcon#about to read 3, iclass 36, count 0 2006.281.07:53:00.15#ibcon#read 3, iclass 36, count 0 2006.281.07:53:00.15#ibcon#about to read 4, iclass 36, count 0 2006.281.07:53:00.15#ibcon#read 4, iclass 36, count 0 2006.281.07:53:00.15#ibcon#about to read 5, iclass 36, count 0 2006.281.07:53:00.15#ibcon#read 5, iclass 36, count 0 2006.281.07:53:00.15#ibcon#about to read 6, iclass 36, count 0 2006.281.07:53:00.15#ibcon#read 6, iclass 36, count 0 2006.281.07:53:00.15#ibcon#end of sib2, iclass 36, count 0 2006.281.07:53:00.15#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:53:00.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:53:00.15#ibcon#[25=USB\r\n] 2006.281.07:53:00.15#ibcon#*before write, iclass 36, count 0 2006.281.07:53:00.15#ibcon#enter sib2, iclass 36, count 0 2006.281.07:53:00.15#ibcon#flushed, iclass 36, count 0 2006.281.07:53:00.15#ibcon#about to write, iclass 36, count 0 2006.281.07:53:00.15#ibcon#wrote, iclass 36, count 0 2006.281.07:53:00.15#ibcon#about to read 3, iclass 36, count 0 2006.281.07:53:00.19#ibcon#read 3, iclass 36, count 0 2006.281.07:53:00.19#ibcon#about to read 4, iclass 36, count 0 2006.281.07:53:00.19#ibcon#read 4, iclass 36, count 0 2006.281.07:53:00.19#ibcon#about to read 5, iclass 36, count 0 2006.281.07:53:00.19#ibcon#read 5, iclass 36, count 0 2006.281.07:53:00.19#ibcon#about to read 6, iclass 36, count 0 2006.281.07:53:00.19#ibcon#read 6, iclass 36, count 0 2006.281.07:53:00.19#ibcon#end of sib2, iclass 36, count 0 2006.281.07:53:00.19#ibcon#*after write, iclass 36, count 0 2006.281.07:53:00.19#ibcon#*before return 0, iclass 36, count 0 2006.281.07:53:00.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:00.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:00.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:53:00.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:53:00.19$vc4f8/valo=3,672.99 2006.281.07:53:00.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:53:00.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:53:00.19#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:00.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:00.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:00.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:00.19#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:53:00.19#ibcon#first serial, iclass 38, count 0 2006.281.07:53:00.19#ibcon#enter sib2, iclass 38, count 0 2006.281.07:53:00.19#ibcon#flushed, iclass 38, count 0 2006.281.07:53:00.19#ibcon#about to write, iclass 38, count 0 2006.281.07:53:00.19#ibcon#wrote, iclass 38, count 0 2006.281.07:53:00.19#ibcon#about to read 3, iclass 38, count 0 2006.281.07:53:00.20#ibcon#read 3, iclass 38, count 0 2006.281.07:53:00.20#ibcon#about to read 4, iclass 38, count 0 2006.281.07:53:00.20#ibcon#read 4, iclass 38, count 0 2006.281.07:53:00.20#ibcon#about to read 5, iclass 38, count 0 2006.281.07:53:00.20#ibcon#read 5, iclass 38, count 0 2006.281.07:53:00.20#ibcon#about to read 6, iclass 38, count 0 2006.281.07:53:00.20#ibcon#read 6, iclass 38, count 0 2006.281.07:53:00.20#ibcon#end of sib2, iclass 38, count 0 2006.281.07:53:00.20#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:53:00.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:53:00.20#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:53:00.20#ibcon#*before write, iclass 38, count 0 2006.281.07:53:00.20#ibcon#enter sib2, iclass 38, count 0 2006.281.07:53:00.20#ibcon#flushed, iclass 38, count 0 2006.281.07:53:00.20#ibcon#about to write, iclass 38, count 0 2006.281.07:53:00.20#ibcon#wrote, iclass 38, count 0 2006.281.07:53:00.20#ibcon#about to read 3, iclass 38, count 0 2006.281.07:53:00.24#ibcon#read 3, iclass 38, count 0 2006.281.07:53:00.24#ibcon#about to read 4, iclass 38, count 0 2006.281.07:53:00.24#ibcon#read 4, iclass 38, count 0 2006.281.07:53:00.24#ibcon#about to read 5, iclass 38, count 0 2006.281.07:53:00.24#ibcon#read 5, iclass 38, count 0 2006.281.07:53:00.24#ibcon#about to read 6, iclass 38, count 0 2006.281.07:53:00.24#ibcon#read 6, iclass 38, count 0 2006.281.07:53:00.24#ibcon#end of sib2, iclass 38, count 0 2006.281.07:53:00.24#ibcon#*after write, iclass 38, count 0 2006.281.07:53:00.24#ibcon#*before return 0, iclass 38, count 0 2006.281.07:53:00.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:00.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:00.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:53:00.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:53:00.24$vc4f8/va=3,6 2006.281.07:53:00.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:53:00.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:53:00.24#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:00.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:00.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:00.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:00.31#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:53:00.31#ibcon#first serial, iclass 40, count 2 2006.281.07:53:00.31#ibcon#enter sib2, iclass 40, count 2 2006.281.07:53:00.31#ibcon#flushed, iclass 40, count 2 2006.281.07:53:00.31#ibcon#about to write, iclass 40, count 2 2006.281.07:53:00.31#ibcon#wrote, iclass 40, count 2 2006.281.07:53:00.31#ibcon#about to read 3, iclass 40, count 2 2006.281.07:53:00.33#ibcon#read 3, iclass 40, count 2 2006.281.07:53:00.33#ibcon#about to read 4, iclass 40, count 2 2006.281.07:53:00.33#ibcon#read 4, iclass 40, count 2 2006.281.07:53:00.33#ibcon#about to read 5, iclass 40, count 2 2006.281.07:53:00.33#ibcon#read 5, iclass 40, count 2 2006.281.07:53:00.33#ibcon#about to read 6, iclass 40, count 2 2006.281.07:53:00.33#ibcon#read 6, iclass 40, count 2 2006.281.07:53:00.33#ibcon#end of sib2, iclass 40, count 2 2006.281.07:53:00.33#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:53:00.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:53:00.33#ibcon#[25=AT03-06\r\n] 2006.281.07:53:00.33#ibcon#*before write, iclass 40, count 2 2006.281.07:53:00.33#ibcon#enter sib2, iclass 40, count 2 2006.281.07:53:00.33#ibcon#flushed, iclass 40, count 2 2006.281.07:53:00.33#ibcon#about to write, iclass 40, count 2 2006.281.07:53:00.33#ibcon#wrote, iclass 40, count 2 2006.281.07:53:00.33#ibcon#about to read 3, iclass 40, count 2 2006.281.07:53:00.36#ibcon#read 3, iclass 40, count 2 2006.281.07:53:00.36#ibcon#about to read 4, iclass 40, count 2 2006.281.07:53:00.36#ibcon#read 4, iclass 40, count 2 2006.281.07:53:00.36#ibcon#about to read 5, iclass 40, count 2 2006.281.07:53:00.36#ibcon#read 5, iclass 40, count 2 2006.281.07:53:00.36#ibcon#about to read 6, iclass 40, count 2 2006.281.07:53:00.36#ibcon#read 6, iclass 40, count 2 2006.281.07:53:00.36#ibcon#end of sib2, iclass 40, count 2 2006.281.07:53:00.36#ibcon#*after write, iclass 40, count 2 2006.281.07:53:00.36#ibcon#*before return 0, iclass 40, count 2 2006.281.07:53:00.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:00.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:00.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:53:00.36#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:00.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:00.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:00.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:00.49#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:53:00.49#ibcon#first serial, iclass 40, count 0 2006.281.07:53:00.49#ibcon#enter sib2, iclass 40, count 0 2006.281.07:53:00.49#ibcon#flushed, iclass 40, count 0 2006.281.07:53:00.49#ibcon#about to write, iclass 40, count 0 2006.281.07:53:00.49#ibcon#wrote, iclass 40, count 0 2006.281.07:53:00.49#ibcon#about to read 3, iclass 40, count 0 2006.281.07:53:00.50#ibcon#read 3, iclass 40, count 0 2006.281.07:53:00.50#ibcon#about to read 4, iclass 40, count 0 2006.281.07:53:00.50#ibcon#read 4, iclass 40, count 0 2006.281.07:53:00.50#ibcon#about to read 5, iclass 40, count 0 2006.281.07:53:00.50#ibcon#read 5, iclass 40, count 0 2006.281.07:53:00.50#ibcon#about to read 6, iclass 40, count 0 2006.281.07:53:00.50#ibcon#read 6, iclass 40, count 0 2006.281.07:53:00.50#ibcon#end of sib2, iclass 40, count 0 2006.281.07:53:00.50#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:53:00.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:53:00.50#ibcon#[25=USB\r\n] 2006.281.07:53:00.50#ibcon#*before write, iclass 40, count 0 2006.281.07:53:00.50#ibcon#enter sib2, iclass 40, count 0 2006.281.07:53:00.50#ibcon#flushed, iclass 40, count 0 2006.281.07:53:00.50#ibcon#about to write, iclass 40, count 0 2006.281.07:53:00.50#ibcon#wrote, iclass 40, count 0 2006.281.07:53:00.50#ibcon#about to read 3, iclass 40, count 0 2006.281.07:53:00.53#ibcon#read 3, iclass 40, count 0 2006.281.07:53:00.53#ibcon#about to read 4, iclass 40, count 0 2006.281.07:53:00.53#ibcon#read 4, iclass 40, count 0 2006.281.07:53:00.53#ibcon#about to read 5, iclass 40, count 0 2006.281.07:53:00.53#ibcon#read 5, iclass 40, count 0 2006.281.07:53:00.53#ibcon#about to read 6, iclass 40, count 0 2006.281.07:53:00.53#ibcon#read 6, iclass 40, count 0 2006.281.07:53:00.53#ibcon#end of sib2, iclass 40, count 0 2006.281.07:53:00.53#ibcon#*after write, iclass 40, count 0 2006.281.07:53:00.53#ibcon#*before return 0, iclass 40, count 0 2006.281.07:53:00.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:00.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:00.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:53:00.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:53:00.53$vc4f8/valo=4,832.99 2006.281.07:53:00.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:53:00.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:53:00.53#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:00.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:00.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:00.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:00.53#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:53:00.53#ibcon#first serial, iclass 4, count 0 2006.281.07:53:00.53#ibcon#enter sib2, iclass 4, count 0 2006.281.07:53:00.53#ibcon#flushed, iclass 4, count 0 2006.281.07:53:00.53#ibcon#about to write, iclass 4, count 0 2006.281.07:53:00.53#ibcon#wrote, iclass 4, count 0 2006.281.07:53:00.53#ibcon#about to read 3, iclass 4, count 0 2006.281.07:53:00.55#ibcon#read 3, iclass 4, count 0 2006.281.07:53:00.55#ibcon#about to read 4, iclass 4, count 0 2006.281.07:53:00.55#ibcon#read 4, iclass 4, count 0 2006.281.07:53:00.55#ibcon#about to read 5, iclass 4, count 0 2006.281.07:53:00.55#ibcon#read 5, iclass 4, count 0 2006.281.07:53:00.55#ibcon#about to read 6, iclass 4, count 0 2006.281.07:53:00.55#ibcon#read 6, iclass 4, count 0 2006.281.07:53:00.55#ibcon#end of sib2, iclass 4, count 0 2006.281.07:53:00.55#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:53:00.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:53:00.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:53:00.55#ibcon#*before write, iclass 4, count 0 2006.281.07:53:00.55#ibcon#enter sib2, iclass 4, count 0 2006.281.07:53:00.55#ibcon#flushed, iclass 4, count 0 2006.281.07:53:00.55#ibcon#about to write, iclass 4, count 0 2006.281.07:53:00.55#ibcon#wrote, iclass 4, count 0 2006.281.07:53:00.55#ibcon#about to read 3, iclass 4, count 0 2006.281.07:53:00.59#ibcon#read 3, iclass 4, count 0 2006.281.07:53:00.59#ibcon#about to read 4, iclass 4, count 0 2006.281.07:53:00.59#ibcon#read 4, iclass 4, count 0 2006.281.07:53:00.59#ibcon#about to read 5, iclass 4, count 0 2006.281.07:53:00.59#ibcon#read 5, iclass 4, count 0 2006.281.07:53:00.59#ibcon#about to read 6, iclass 4, count 0 2006.281.07:53:00.59#ibcon#read 6, iclass 4, count 0 2006.281.07:53:00.59#ibcon#end of sib2, iclass 4, count 0 2006.281.07:53:00.59#ibcon#*after write, iclass 4, count 0 2006.281.07:53:00.59#ibcon#*before return 0, iclass 4, count 0 2006.281.07:53:00.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:00.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:00.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:53:00.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:53:00.59$vc4f8/va=4,6 2006.281.07:53:00.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:53:00.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:53:00.59#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:00.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:00.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:00.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:00.65#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:53:00.65#ibcon#first serial, iclass 6, count 2 2006.281.07:53:00.65#ibcon#enter sib2, iclass 6, count 2 2006.281.07:53:00.65#ibcon#flushed, iclass 6, count 2 2006.281.07:53:00.65#ibcon#about to write, iclass 6, count 2 2006.281.07:53:00.65#ibcon#wrote, iclass 6, count 2 2006.281.07:53:00.65#ibcon#about to read 3, iclass 6, count 2 2006.281.07:53:00.67#ibcon#read 3, iclass 6, count 2 2006.281.07:53:00.67#ibcon#about to read 4, iclass 6, count 2 2006.281.07:53:00.67#ibcon#read 4, iclass 6, count 2 2006.281.07:53:00.67#ibcon#about to read 5, iclass 6, count 2 2006.281.07:53:00.67#ibcon#read 5, iclass 6, count 2 2006.281.07:53:00.67#ibcon#about to read 6, iclass 6, count 2 2006.281.07:53:00.67#ibcon#read 6, iclass 6, count 2 2006.281.07:53:00.67#ibcon#end of sib2, iclass 6, count 2 2006.281.07:53:00.67#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:53:00.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:53:00.67#ibcon#[25=AT04-06\r\n] 2006.281.07:53:00.67#ibcon#*before write, iclass 6, count 2 2006.281.07:53:00.67#ibcon#enter sib2, iclass 6, count 2 2006.281.07:53:00.67#ibcon#flushed, iclass 6, count 2 2006.281.07:53:00.67#ibcon#about to write, iclass 6, count 2 2006.281.07:53:00.67#ibcon#wrote, iclass 6, count 2 2006.281.07:53:00.67#ibcon#about to read 3, iclass 6, count 2 2006.281.07:53:00.70#ibcon#read 3, iclass 6, count 2 2006.281.07:53:00.70#ibcon#about to read 4, iclass 6, count 2 2006.281.07:53:00.70#ibcon#read 4, iclass 6, count 2 2006.281.07:53:00.70#ibcon#about to read 5, iclass 6, count 2 2006.281.07:53:00.70#ibcon#read 5, iclass 6, count 2 2006.281.07:53:00.70#ibcon#about to read 6, iclass 6, count 2 2006.281.07:53:00.70#ibcon#read 6, iclass 6, count 2 2006.281.07:53:00.70#ibcon#end of sib2, iclass 6, count 2 2006.281.07:53:00.70#ibcon#*after write, iclass 6, count 2 2006.281.07:53:00.70#ibcon#*before return 0, iclass 6, count 2 2006.281.07:53:00.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:00.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:00.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:53:00.70#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:00.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:00.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:00.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:00.82#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:53:00.82#ibcon#first serial, iclass 6, count 0 2006.281.07:53:00.82#ibcon#enter sib2, iclass 6, count 0 2006.281.07:53:00.82#ibcon#flushed, iclass 6, count 0 2006.281.07:53:00.82#ibcon#about to write, iclass 6, count 0 2006.281.07:53:00.82#ibcon#wrote, iclass 6, count 0 2006.281.07:53:00.82#ibcon#about to read 3, iclass 6, count 0 2006.281.07:53:00.84#ibcon#read 3, iclass 6, count 0 2006.281.07:53:00.84#ibcon#about to read 4, iclass 6, count 0 2006.281.07:53:00.84#ibcon#read 4, iclass 6, count 0 2006.281.07:53:00.84#ibcon#about to read 5, iclass 6, count 0 2006.281.07:53:00.84#ibcon#read 5, iclass 6, count 0 2006.281.07:53:00.84#ibcon#about to read 6, iclass 6, count 0 2006.281.07:53:00.84#ibcon#read 6, iclass 6, count 0 2006.281.07:53:00.84#ibcon#end of sib2, iclass 6, count 0 2006.281.07:53:00.84#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:53:00.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:53:00.84#ibcon#[25=USB\r\n] 2006.281.07:53:00.84#ibcon#*before write, iclass 6, count 0 2006.281.07:53:00.84#ibcon#enter sib2, iclass 6, count 0 2006.281.07:53:00.84#ibcon#flushed, iclass 6, count 0 2006.281.07:53:00.84#ibcon#about to write, iclass 6, count 0 2006.281.07:53:00.84#ibcon#wrote, iclass 6, count 0 2006.281.07:53:00.84#ibcon#about to read 3, iclass 6, count 0 2006.281.07:53:00.87#ibcon#read 3, iclass 6, count 0 2006.281.07:53:00.87#ibcon#about to read 4, iclass 6, count 0 2006.281.07:53:00.87#ibcon#read 4, iclass 6, count 0 2006.281.07:53:00.87#ibcon#about to read 5, iclass 6, count 0 2006.281.07:53:00.87#ibcon#read 5, iclass 6, count 0 2006.281.07:53:00.87#ibcon#about to read 6, iclass 6, count 0 2006.281.07:53:00.87#ibcon#read 6, iclass 6, count 0 2006.281.07:53:00.87#ibcon#end of sib2, iclass 6, count 0 2006.281.07:53:00.87#ibcon#*after write, iclass 6, count 0 2006.281.07:53:00.87#ibcon#*before return 0, iclass 6, count 0 2006.281.07:53:00.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:00.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:00.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:53:00.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:53:00.87$vc4f8/valo=5,652.99 2006.281.07:53:00.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:53:00.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:53:00.87#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:00.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:00.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:00.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:00.87#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:53:00.87#ibcon#first serial, iclass 10, count 0 2006.281.07:53:00.87#ibcon#enter sib2, iclass 10, count 0 2006.281.07:53:00.87#ibcon#flushed, iclass 10, count 0 2006.281.07:53:00.87#ibcon#about to write, iclass 10, count 0 2006.281.07:53:00.87#ibcon#wrote, iclass 10, count 0 2006.281.07:53:00.87#ibcon#about to read 3, iclass 10, count 0 2006.281.07:53:00.89#ibcon#read 3, iclass 10, count 0 2006.281.07:53:00.89#ibcon#about to read 4, iclass 10, count 0 2006.281.07:53:00.89#ibcon#read 4, iclass 10, count 0 2006.281.07:53:00.89#ibcon#about to read 5, iclass 10, count 0 2006.281.07:53:00.89#ibcon#read 5, iclass 10, count 0 2006.281.07:53:00.89#ibcon#about to read 6, iclass 10, count 0 2006.281.07:53:00.89#ibcon#read 6, iclass 10, count 0 2006.281.07:53:00.89#ibcon#end of sib2, iclass 10, count 0 2006.281.07:53:00.89#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:53:00.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:53:00.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:53:00.89#ibcon#*before write, iclass 10, count 0 2006.281.07:53:00.89#ibcon#enter sib2, iclass 10, count 0 2006.281.07:53:00.89#ibcon#flushed, iclass 10, count 0 2006.281.07:53:00.89#ibcon#about to write, iclass 10, count 0 2006.281.07:53:00.89#ibcon#wrote, iclass 10, count 0 2006.281.07:53:00.89#ibcon#about to read 3, iclass 10, count 0 2006.281.07:53:00.93#ibcon#read 3, iclass 10, count 0 2006.281.07:53:00.93#ibcon#about to read 4, iclass 10, count 0 2006.281.07:53:00.93#ibcon#read 4, iclass 10, count 0 2006.281.07:53:00.93#ibcon#about to read 5, iclass 10, count 0 2006.281.07:53:00.93#ibcon#read 5, iclass 10, count 0 2006.281.07:53:00.93#ibcon#about to read 6, iclass 10, count 0 2006.281.07:53:00.93#ibcon#read 6, iclass 10, count 0 2006.281.07:53:00.93#ibcon#end of sib2, iclass 10, count 0 2006.281.07:53:00.93#ibcon#*after write, iclass 10, count 0 2006.281.07:53:00.93#ibcon#*before return 0, iclass 10, count 0 2006.281.07:53:00.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:00.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:00.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:53:00.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:53:00.93$vc4f8/va=5,7 2006.281.07:53:00.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:53:00.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:53:00.94#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:00.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:00.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:00.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:00.99#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:53:00.99#ibcon#first serial, iclass 12, count 2 2006.281.07:53:00.99#ibcon#enter sib2, iclass 12, count 2 2006.281.07:53:00.99#ibcon#flushed, iclass 12, count 2 2006.281.07:53:00.99#ibcon#about to write, iclass 12, count 2 2006.281.07:53:00.99#ibcon#wrote, iclass 12, count 2 2006.281.07:53:00.99#ibcon#about to read 3, iclass 12, count 2 2006.281.07:53:01.01#ibcon#read 3, iclass 12, count 2 2006.281.07:53:01.01#ibcon#about to read 4, iclass 12, count 2 2006.281.07:53:01.01#ibcon#read 4, iclass 12, count 2 2006.281.07:53:01.01#ibcon#about to read 5, iclass 12, count 2 2006.281.07:53:01.01#ibcon#read 5, iclass 12, count 2 2006.281.07:53:01.01#ibcon#about to read 6, iclass 12, count 2 2006.281.07:53:01.01#ibcon#read 6, iclass 12, count 2 2006.281.07:53:01.01#ibcon#end of sib2, iclass 12, count 2 2006.281.07:53:01.01#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:53:01.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:53:01.01#ibcon#[25=AT05-07\r\n] 2006.281.07:53:01.01#ibcon#*before write, iclass 12, count 2 2006.281.07:53:01.01#ibcon#enter sib2, iclass 12, count 2 2006.281.07:53:01.01#ibcon#flushed, iclass 12, count 2 2006.281.07:53:01.01#ibcon#about to write, iclass 12, count 2 2006.281.07:53:01.01#ibcon#wrote, iclass 12, count 2 2006.281.07:53:01.01#ibcon#about to read 3, iclass 12, count 2 2006.281.07:53:01.04#ibcon#read 3, iclass 12, count 2 2006.281.07:53:01.04#ibcon#about to read 4, iclass 12, count 2 2006.281.07:53:01.04#ibcon#read 4, iclass 12, count 2 2006.281.07:53:01.04#ibcon#about to read 5, iclass 12, count 2 2006.281.07:53:01.04#ibcon#read 5, iclass 12, count 2 2006.281.07:53:01.04#ibcon#about to read 6, iclass 12, count 2 2006.281.07:53:01.04#ibcon#read 6, iclass 12, count 2 2006.281.07:53:01.04#ibcon#end of sib2, iclass 12, count 2 2006.281.07:53:01.04#ibcon#*after write, iclass 12, count 2 2006.281.07:53:01.04#ibcon#*before return 0, iclass 12, count 2 2006.281.07:53:01.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:01.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:01.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:53:01.04#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:01.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:01.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:01.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:01.16#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:53:01.16#ibcon#first serial, iclass 12, count 0 2006.281.07:53:01.16#ibcon#enter sib2, iclass 12, count 0 2006.281.07:53:01.16#ibcon#flushed, iclass 12, count 0 2006.281.07:53:01.16#ibcon#about to write, iclass 12, count 0 2006.281.07:53:01.16#ibcon#wrote, iclass 12, count 0 2006.281.07:53:01.16#ibcon#about to read 3, iclass 12, count 0 2006.281.07:53:01.18#ibcon#read 3, iclass 12, count 0 2006.281.07:53:01.18#ibcon#about to read 4, iclass 12, count 0 2006.281.07:53:01.18#ibcon#read 4, iclass 12, count 0 2006.281.07:53:01.18#ibcon#about to read 5, iclass 12, count 0 2006.281.07:53:01.18#ibcon#read 5, iclass 12, count 0 2006.281.07:53:01.18#ibcon#about to read 6, iclass 12, count 0 2006.281.07:53:01.18#ibcon#read 6, iclass 12, count 0 2006.281.07:53:01.18#ibcon#end of sib2, iclass 12, count 0 2006.281.07:53:01.18#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:53:01.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:53:01.18#ibcon#[25=USB\r\n] 2006.281.07:53:01.18#ibcon#*before write, iclass 12, count 0 2006.281.07:53:01.18#ibcon#enter sib2, iclass 12, count 0 2006.281.07:53:01.18#ibcon#flushed, iclass 12, count 0 2006.281.07:53:01.18#ibcon#about to write, iclass 12, count 0 2006.281.07:53:01.18#ibcon#wrote, iclass 12, count 0 2006.281.07:53:01.18#ibcon#about to read 3, iclass 12, count 0 2006.281.07:53:01.21#ibcon#read 3, iclass 12, count 0 2006.281.07:53:01.21#ibcon#about to read 4, iclass 12, count 0 2006.281.07:53:01.21#ibcon#read 4, iclass 12, count 0 2006.281.07:53:01.21#ibcon#about to read 5, iclass 12, count 0 2006.281.07:53:01.21#ibcon#read 5, iclass 12, count 0 2006.281.07:53:01.21#ibcon#about to read 6, iclass 12, count 0 2006.281.07:53:01.21#ibcon#read 6, iclass 12, count 0 2006.281.07:53:01.21#ibcon#end of sib2, iclass 12, count 0 2006.281.07:53:01.21#ibcon#*after write, iclass 12, count 0 2006.281.07:53:01.21#ibcon#*before return 0, iclass 12, count 0 2006.281.07:53:01.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:01.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:01.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:53:01.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:53:01.21$vc4f8/valo=6,772.99 2006.281.07:53:01.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:53:01.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:53:01.21#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:01.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:01.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:01.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:01.21#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:53:01.21#ibcon#first serial, iclass 14, count 0 2006.281.07:53:01.21#ibcon#enter sib2, iclass 14, count 0 2006.281.07:53:01.21#ibcon#flushed, iclass 14, count 0 2006.281.07:53:01.21#ibcon#about to write, iclass 14, count 0 2006.281.07:53:01.21#ibcon#wrote, iclass 14, count 0 2006.281.07:53:01.21#ibcon#about to read 3, iclass 14, count 0 2006.281.07:53:01.23#ibcon#read 3, iclass 14, count 0 2006.281.07:53:01.24#ibcon#about to read 4, iclass 14, count 0 2006.281.07:53:01.24#ibcon#read 4, iclass 14, count 0 2006.281.07:53:01.24#ibcon#about to read 5, iclass 14, count 0 2006.281.07:53:01.24#ibcon#read 5, iclass 14, count 0 2006.281.07:53:01.24#ibcon#about to read 6, iclass 14, count 0 2006.281.07:53:01.24#ibcon#read 6, iclass 14, count 0 2006.281.07:53:01.24#ibcon#end of sib2, iclass 14, count 0 2006.281.07:53:01.24#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:53:01.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:53:01.24#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:53:01.24#ibcon#*before write, iclass 14, count 0 2006.281.07:53:01.24#ibcon#enter sib2, iclass 14, count 0 2006.281.07:53:01.24#ibcon#flushed, iclass 14, count 0 2006.281.07:53:01.24#ibcon#about to write, iclass 14, count 0 2006.281.07:53:01.24#ibcon#wrote, iclass 14, count 0 2006.281.07:53:01.24#ibcon#about to read 3, iclass 14, count 0 2006.281.07:53:01.29#ibcon#read 3, iclass 14, count 0 2006.281.07:53:01.29#ibcon#about to read 4, iclass 14, count 0 2006.281.07:53:01.29#ibcon#read 4, iclass 14, count 0 2006.281.07:53:01.29#ibcon#about to read 5, iclass 14, count 0 2006.281.07:53:01.29#ibcon#read 5, iclass 14, count 0 2006.281.07:53:01.29#ibcon#about to read 6, iclass 14, count 0 2006.281.07:53:01.29#ibcon#read 6, iclass 14, count 0 2006.281.07:53:01.29#ibcon#end of sib2, iclass 14, count 0 2006.281.07:53:01.29#ibcon#*after write, iclass 14, count 0 2006.281.07:53:01.29#ibcon#*before return 0, iclass 14, count 0 2006.281.07:53:01.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:01.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:01.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:53:01.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:53:01.29$vc4f8/va=6,6 2006.281.07:53:01.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.07:53:01.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.07:53:01.29#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:01.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:01.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:01.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:01.33#ibcon#enter wrdev, iclass 16, count 2 2006.281.07:53:01.33#ibcon#first serial, iclass 16, count 2 2006.281.07:53:01.33#ibcon#enter sib2, iclass 16, count 2 2006.281.07:53:01.33#ibcon#flushed, iclass 16, count 2 2006.281.07:53:01.33#ibcon#about to write, iclass 16, count 2 2006.281.07:53:01.33#ibcon#wrote, iclass 16, count 2 2006.281.07:53:01.33#ibcon#about to read 3, iclass 16, count 2 2006.281.07:53:01.34#ibcon#read 3, iclass 16, count 2 2006.281.07:53:01.35#ibcon#about to read 4, iclass 16, count 2 2006.281.07:53:01.36#ibcon#read 4, iclass 16, count 2 2006.281.07:53:01.36#ibcon#about to read 5, iclass 16, count 2 2006.281.07:53:01.36#ibcon#read 5, iclass 16, count 2 2006.281.07:53:01.36#ibcon#about to read 6, iclass 16, count 2 2006.281.07:53:01.36#ibcon#read 6, iclass 16, count 2 2006.281.07:53:01.36#ibcon#end of sib2, iclass 16, count 2 2006.281.07:53:01.36#ibcon#*mode == 0, iclass 16, count 2 2006.281.07:53:01.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.07:53:01.36#ibcon#[25=AT06-06\r\n] 2006.281.07:53:01.36#ibcon#*before write, iclass 16, count 2 2006.281.07:53:01.36#ibcon#enter sib2, iclass 16, count 2 2006.281.07:53:01.36#ibcon#flushed, iclass 16, count 2 2006.281.07:53:01.36#ibcon#about to write, iclass 16, count 2 2006.281.07:53:01.36#ibcon#wrote, iclass 16, count 2 2006.281.07:53:01.36#ibcon#about to read 3, iclass 16, count 2 2006.281.07:53:01.38#ibcon#read 3, iclass 16, count 2 2006.281.07:53:01.38#ibcon#about to read 4, iclass 16, count 2 2006.281.07:53:01.38#ibcon#read 4, iclass 16, count 2 2006.281.07:53:01.38#ibcon#about to read 5, iclass 16, count 2 2006.281.07:53:01.38#ibcon#read 5, iclass 16, count 2 2006.281.07:53:01.38#ibcon#about to read 6, iclass 16, count 2 2006.281.07:53:01.38#ibcon#read 6, iclass 16, count 2 2006.281.07:53:01.38#ibcon#end of sib2, iclass 16, count 2 2006.281.07:53:01.38#ibcon#*after write, iclass 16, count 2 2006.281.07:53:01.38#ibcon#*before return 0, iclass 16, count 2 2006.281.07:53:01.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:01.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:01.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.07:53:01.38#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:01.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:53:01.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:53:01.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:53:01.50#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:53:01.50#ibcon#first serial, iclass 16, count 0 2006.281.07:53:01.50#ibcon#enter sib2, iclass 16, count 0 2006.281.07:53:01.50#ibcon#flushed, iclass 16, count 0 2006.281.07:53:01.50#ibcon#about to write, iclass 16, count 0 2006.281.07:53:01.50#ibcon#wrote, iclass 16, count 0 2006.281.07:53:01.50#ibcon#about to read 3, iclass 16, count 0 2006.281.07:53:01.52#ibcon#read 3, iclass 16, count 0 2006.281.07:53:01.52#ibcon#about to read 4, iclass 16, count 0 2006.281.07:53:01.52#ibcon#read 4, iclass 16, count 0 2006.281.07:53:01.52#ibcon#about to read 5, iclass 16, count 0 2006.281.07:53:01.52#ibcon#read 5, iclass 16, count 0 2006.281.07:53:01.52#ibcon#about to read 6, iclass 16, count 0 2006.281.07:53:01.52#ibcon#read 6, iclass 16, count 0 2006.281.07:53:01.52#ibcon#end of sib2, iclass 16, count 0 2006.281.07:53:01.52#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:53:01.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:53:01.52#ibcon#[25=USB\r\n] 2006.281.07:53:01.52#ibcon#*before write, iclass 16, count 0 2006.281.07:53:01.52#ibcon#enter sib2, iclass 16, count 0 2006.281.07:53:01.52#ibcon#flushed, iclass 16, count 0 2006.281.07:53:01.52#ibcon#about to write, iclass 16, count 0 2006.281.07:53:01.52#ibcon#wrote, iclass 16, count 0 2006.281.07:53:01.52#ibcon#about to read 3, iclass 16, count 0 2006.281.07:53:01.55#ibcon#read 3, iclass 16, count 0 2006.281.07:53:01.55#ibcon#about to read 4, iclass 16, count 0 2006.281.07:53:01.55#ibcon#read 4, iclass 16, count 0 2006.281.07:53:01.55#ibcon#about to read 5, iclass 16, count 0 2006.281.07:53:01.55#ibcon#read 5, iclass 16, count 0 2006.281.07:53:01.55#ibcon#about to read 6, iclass 16, count 0 2006.281.07:53:01.55#ibcon#read 6, iclass 16, count 0 2006.281.07:53:01.55#ibcon#end of sib2, iclass 16, count 0 2006.281.07:53:01.55#ibcon#*after write, iclass 16, count 0 2006.281.07:53:01.55#ibcon#*before return 0, iclass 16, count 0 2006.281.07:53:01.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:53:01.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.07:53:01.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:53:01.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:53:01.55$vc4f8/valo=7,832.99 2006.281.07:53:01.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.07:53:01.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.07:53:01.55#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:01.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:53:01.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:53:01.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:53:01.55#ibcon#enter wrdev, iclass 18, count 0 2006.281.07:53:01.55#ibcon#first serial, iclass 18, count 0 2006.281.07:53:01.55#ibcon#enter sib2, iclass 18, count 0 2006.281.07:53:01.55#ibcon#flushed, iclass 18, count 0 2006.281.07:53:01.55#ibcon#about to write, iclass 18, count 0 2006.281.07:53:01.55#ibcon#wrote, iclass 18, count 0 2006.281.07:53:01.55#ibcon#about to read 3, iclass 18, count 0 2006.281.07:53:01.57#ibcon#read 3, iclass 18, count 0 2006.281.07:53:01.57#ibcon#about to read 4, iclass 18, count 0 2006.281.07:53:01.57#ibcon#read 4, iclass 18, count 0 2006.281.07:53:01.57#ibcon#about to read 5, iclass 18, count 0 2006.281.07:53:01.57#ibcon#read 5, iclass 18, count 0 2006.281.07:53:01.57#ibcon#about to read 6, iclass 18, count 0 2006.281.07:53:01.57#ibcon#read 6, iclass 18, count 0 2006.281.07:53:01.57#ibcon#end of sib2, iclass 18, count 0 2006.281.07:53:01.57#ibcon#*mode == 0, iclass 18, count 0 2006.281.07:53:01.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.07:53:01.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:53:01.57#ibcon#*before write, iclass 18, count 0 2006.281.07:53:01.57#ibcon#enter sib2, iclass 18, count 0 2006.281.07:53:01.57#ibcon#flushed, iclass 18, count 0 2006.281.07:53:01.57#ibcon#about to write, iclass 18, count 0 2006.281.07:53:01.57#ibcon#wrote, iclass 18, count 0 2006.281.07:53:01.57#ibcon#about to read 3, iclass 18, count 0 2006.281.07:53:01.61#ibcon#read 3, iclass 18, count 0 2006.281.07:53:01.61#ibcon#about to read 4, iclass 18, count 0 2006.281.07:53:01.61#ibcon#read 4, iclass 18, count 0 2006.281.07:53:01.61#ibcon#about to read 5, iclass 18, count 0 2006.281.07:53:01.61#ibcon#read 5, iclass 18, count 0 2006.281.07:53:01.61#ibcon#about to read 6, iclass 18, count 0 2006.281.07:53:01.61#ibcon#read 6, iclass 18, count 0 2006.281.07:53:01.61#ibcon#end of sib2, iclass 18, count 0 2006.281.07:53:01.61#ibcon#*after write, iclass 18, count 0 2006.281.07:53:01.61#ibcon#*before return 0, iclass 18, count 0 2006.281.07:53:01.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:53:01.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.07:53:01.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.07:53:01.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.07:53:01.61$vc4f8/va=7,6 2006.281.07:53:01.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.07:53:01.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.07:53:01.61#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:01.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:53:01.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:53:01.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:53:01.67#ibcon#enter wrdev, iclass 20, count 2 2006.281.07:53:01.67#ibcon#first serial, iclass 20, count 2 2006.281.07:53:01.67#ibcon#enter sib2, iclass 20, count 2 2006.281.07:53:01.67#ibcon#flushed, iclass 20, count 2 2006.281.07:53:01.67#ibcon#about to write, iclass 20, count 2 2006.281.07:53:01.67#ibcon#wrote, iclass 20, count 2 2006.281.07:53:01.67#ibcon#about to read 3, iclass 20, count 2 2006.281.07:53:01.69#ibcon#read 3, iclass 20, count 2 2006.281.07:53:01.69#ibcon#about to read 4, iclass 20, count 2 2006.281.07:53:01.69#ibcon#read 4, iclass 20, count 2 2006.281.07:53:01.69#ibcon#about to read 5, iclass 20, count 2 2006.281.07:53:01.69#ibcon#read 5, iclass 20, count 2 2006.281.07:53:01.69#ibcon#about to read 6, iclass 20, count 2 2006.281.07:53:01.69#ibcon#read 6, iclass 20, count 2 2006.281.07:53:01.69#ibcon#end of sib2, iclass 20, count 2 2006.281.07:53:01.69#ibcon#*mode == 0, iclass 20, count 2 2006.281.07:53:01.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.07:53:01.69#ibcon#[25=AT07-06\r\n] 2006.281.07:53:01.69#ibcon#*before write, iclass 20, count 2 2006.281.07:53:01.69#ibcon#enter sib2, iclass 20, count 2 2006.281.07:53:01.69#ibcon#flushed, iclass 20, count 2 2006.281.07:53:01.69#ibcon#about to write, iclass 20, count 2 2006.281.07:53:01.69#ibcon#wrote, iclass 20, count 2 2006.281.07:53:01.69#ibcon#about to read 3, iclass 20, count 2 2006.281.07:53:01.72#ibcon#read 3, iclass 20, count 2 2006.281.07:53:01.72#ibcon#about to read 4, iclass 20, count 2 2006.281.07:53:01.72#ibcon#read 4, iclass 20, count 2 2006.281.07:53:01.72#ibcon#about to read 5, iclass 20, count 2 2006.281.07:53:01.72#ibcon#read 5, iclass 20, count 2 2006.281.07:53:01.72#ibcon#about to read 6, iclass 20, count 2 2006.281.07:53:01.72#ibcon#read 6, iclass 20, count 2 2006.281.07:53:01.72#ibcon#end of sib2, iclass 20, count 2 2006.281.07:53:01.72#ibcon#*after write, iclass 20, count 2 2006.281.07:53:01.72#ibcon#*before return 0, iclass 20, count 2 2006.281.07:53:01.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:53:01.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.07:53:01.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.07:53:01.72#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:01.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:53:01.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:53:01.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:53:01.84#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:53:01.84#ibcon#first serial, iclass 20, count 0 2006.281.07:53:01.84#ibcon#enter sib2, iclass 20, count 0 2006.281.07:53:01.84#ibcon#flushed, iclass 20, count 0 2006.281.07:53:01.84#ibcon#about to write, iclass 20, count 0 2006.281.07:53:01.84#ibcon#wrote, iclass 20, count 0 2006.281.07:53:01.84#ibcon#about to read 3, iclass 20, count 0 2006.281.07:53:01.86#ibcon#read 3, iclass 20, count 0 2006.281.07:53:01.86#ibcon#about to read 4, iclass 20, count 0 2006.281.07:53:01.86#ibcon#read 4, iclass 20, count 0 2006.281.07:53:01.86#ibcon#about to read 5, iclass 20, count 0 2006.281.07:53:01.86#ibcon#read 5, iclass 20, count 0 2006.281.07:53:01.86#ibcon#about to read 6, iclass 20, count 0 2006.281.07:53:01.86#ibcon#read 6, iclass 20, count 0 2006.281.07:53:01.86#ibcon#end of sib2, iclass 20, count 0 2006.281.07:53:01.86#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:53:01.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:53:01.86#ibcon#[25=USB\r\n] 2006.281.07:53:01.86#ibcon#*before write, iclass 20, count 0 2006.281.07:53:01.86#ibcon#enter sib2, iclass 20, count 0 2006.281.07:53:01.86#ibcon#flushed, iclass 20, count 0 2006.281.07:53:01.86#ibcon#about to write, iclass 20, count 0 2006.281.07:53:01.86#ibcon#wrote, iclass 20, count 0 2006.281.07:53:01.86#ibcon#about to read 3, iclass 20, count 0 2006.281.07:53:01.89#ibcon#read 3, iclass 20, count 0 2006.281.07:53:01.89#ibcon#about to read 4, iclass 20, count 0 2006.281.07:53:01.89#ibcon#read 4, iclass 20, count 0 2006.281.07:53:01.89#ibcon#about to read 5, iclass 20, count 0 2006.281.07:53:01.89#ibcon#read 5, iclass 20, count 0 2006.281.07:53:01.89#ibcon#about to read 6, iclass 20, count 0 2006.281.07:53:01.89#ibcon#read 6, iclass 20, count 0 2006.281.07:53:01.89#ibcon#end of sib2, iclass 20, count 0 2006.281.07:53:01.89#ibcon#*after write, iclass 20, count 0 2006.281.07:53:01.89#ibcon#*before return 0, iclass 20, count 0 2006.281.07:53:01.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:53:01.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.07:53:01.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:53:01.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:53:01.89$vc4f8/valo=8,852.99 2006.281.07:53:01.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.07:53:01.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.07:53:01.89#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:01.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:53:01.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:53:01.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:53:01.89#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:53:01.89#ibcon#first serial, iclass 22, count 0 2006.281.07:53:01.89#ibcon#enter sib2, iclass 22, count 0 2006.281.07:53:01.89#ibcon#flushed, iclass 22, count 0 2006.281.07:53:01.89#ibcon#about to write, iclass 22, count 0 2006.281.07:53:01.89#ibcon#wrote, iclass 22, count 0 2006.281.07:53:01.89#ibcon#about to read 3, iclass 22, count 0 2006.281.07:53:01.91#ibcon#read 3, iclass 22, count 0 2006.281.07:53:01.91#ibcon#about to read 4, iclass 22, count 0 2006.281.07:53:01.91#ibcon#read 4, iclass 22, count 0 2006.281.07:53:01.91#ibcon#about to read 5, iclass 22, count 0 2006.281.07:53:01.91#ibcon#read 5, iclass 22, count 0 2006.281.07:53:01.91#ibcon#about to read 6, iclass 22, count 0 2006.281.07:53:01.91#ibcon#read 6, iclass 22, count 0 2006.281.07:53:01.91#ibcon#end of sib2, iclass 22, count 0 2006.281.07:53:01.91#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:53:01.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:53:01.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:53:01.91#ibcon#*before write, iclass 22, count 0 2006.281.07:53:01.91#ibcon#enter sib2, iclass 22, count 0 2006.281.07:53:01.91#ibcon#flushed, iclass 22, count 0 2006.281.07:53:01.91#ibcon#about to write, iclass 22, count 0 2006.281.07:53:01.91#ibcon#wrote, iclass 22, count 0 2006.281.07:53:01.91#ibcon#about to read 3, iclass 22, count 0 2006.281.07:53:01.95#ibcon#read 3, iclass 22, count 0 2006.281.07:53:01.95#ibcon#about to read 4, iclass 22, count 0 2006.281.07:53:01.95#ibcon#read 4, iclass 22, count 0 2006.281.07:53:01.95#ibcon#about to read 5, iclass 22, count 0 2006.281.07:53:01.95#ibcon#read 5, iclass 22, count 0 2006.281.07:53:01.95#ibcon#about to read 6, iclass 22, count 0 2006.281.07:53:01.95#ibcon#read 6, iclass 22, count 0 2006.281.07:53:01.95#ibcon#end of sib2, iclass 22, count 0 2006.281.07:53:01.95#ibcon#*after write, iclass 22, count 0 2006.281.07:53:01.95#ibcon#*before return 0, iclass 22, count 0 2006.281.07:53:01.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:53:01.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.07:53:01.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:53:01.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:53:01.95$vc4f8/va=8,6 2006.281.07:53:01.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.07:53:01.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.07:53:01.96#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:01.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:53:02.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:53:02.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:53:02.01#ibcon#enter wrdev, iclass 24, count 2 2006.281.07:53:02.01#ibcon#first serial, iclass 24, count 2 2006.281.07:53:02.01#ibcon#enter sib2, iclass 24, count 2 2006.281.07:53:02.01#ibcon#flushed, iclass 24, count 2 2006.281.07:53:02.01#ibcon#about to write, iclass 24, count 2 2006.281.07:53:02.01#ibcon#wrote, iclass 24, count 2 2006.281.07:53:02.01#ibcon#about to read 3, iclass 24, count 2 2006.281.07:53:02.03#ibcon#read 3, iclass 24, count 2 2006.281.07:53:02.03#ibcon#about to read 4, iclass 24, count 2 2006.281.07:53:02.03#ibcon#read 4, iclass 24, count 2 2006.281.07:53:02.03#ibcon#about to read 5, iclass 24, count 2 2006.281.07:53:02.03#ibcon#read 5, iclass 24, count 2 2006.281.07:53:02.03#ibcon#about to read 6, iclass 24, count 2 2006.281.07:53:02.03#ibcon#read 6, iclass 24, count 2 2006.281.07:53:02.03#ibcon#end of sib2, iclass 24, count 2 2006.281.07:53:02.03#ibcon#*mode == 0, iclass 24, count 2 2006.281.07:53:02.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.07:53:02.03#ibcon#[25=AT08-06\r\n] 2006.281.07:53:02.03#ibcon#*before write, iclass 24, count 2 2006.281.07:53:02.03#ibcon#enter sib2, iclass 24, count 2 2006.281.07:53:02.03#ibcon#flushed, iclass 24, count 2 2006.281.07:53:02.03#ibcon#about to write, iclass 24, count 2 2006.281.07:53:02.03#ibcon#wrote, iclass 24, count 2 2006.281.07:53:02.03#ibcon#about to read 3, iclass 24, count 2 2006.281.07:53:02.06#ibcon#read 3, iclass 24, count 2 2006.281.07:53:02.06#ibcon#about to read 4, iclass 24, count 2 2006.281.07:53:02.06#ibcon#read 4, iclass 24, count 2 2006.281.07:53:02.06#ibcon#about to read 5, iclass 24, count 2 2006.281.07:53:02.06#ibcon#read 5, iclass 24, count 2 2006.281.07:53:02.06#ibcon#about to read 6, iclass 24, count 2 2006.281.07:53:02.06#ibcon#read 6, iclass 24, count 2 2006.281.07:53:02.06#ibcon#end of sib2, iclass 24, count 2 2006.281.07:53:02.06#ibcon#*after write, iclass 24, count 2 2006.281.07:53:02.06#ibcon#*before return 0, iclass 24, count 2 2006.281.07:53:02.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:53:02.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.07:53:02.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.07:53:02.06#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:02.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:53:02.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:53:02.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:53:02.18#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:53:02.18#ibcon#first serial, iclass 24, count 0 2006.281.07:53:02.18#ibcon#enter sib2, iclass 24, count 0 2006.281.07:53:02.18#ibcon#flushed, iclass 24, count 0 2006.281.07:53:02.18#ibcon#about to write, iclass 24, count 0 2006.281.07:53:02.18#ibcon#wrote, iclass 24, count 0 2006.281.07:53:02.18#ibcon#about to read 3, iclass 24, count 0 2006.281.07:53:02.20#ibcon#read 3, iclass 24, count 0 2006.281.07:53:02.20#ibcon#about to read 4, iclass 24, count 0 2006.281.07:53:02.20#ibcon#read 4, iclass 24, count 0 2006.281.07:53:02.20#ibcon#about to read 5, iclass 24, count 0 2006.281.07:53:02.20#ibcon#read 5, iclass 24, count 0 2006.281.07:53:02.20#ibcon#about to read 6, iclass 24, count 0 2006.281.07:53:02.20#ibcon#read 6, iclass 24, count 0 2006.281.07:53:02.20#ibcon#end of sib2, iclass 24, count 0 2006.281.07:53:02.20#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:53:02.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:53:02.20#ibcon#[25=USB\r\n] 2006.281.07:53:02.20#ibcon#*before write, iclass 24, count 0 2006.281.07:53:02.20#ibcon#enter sib2, iclass 24, count 0 2006.281.07:53:02.20#ibcon#flushed, iclass 24, count 0 2006.281.07:53:02.20#ibcon#about to write, iclass 24, count 0 2006.281.07:53:02.20#ibcon#wrote, iclass 24, count 0 2006.281.07:53:02.20#ibcon#about to read 3, iclass 24, count 0 2006.281.07:53:02.23#ibcon#read 3, iclass 24, count 0 2006.281.07:53:02.23#ibcon#about to read 4, iclass 24, count 0 2006.281.07:53:02.23#ibcon#read 4, iclass 24, count 0 2006.281.07:53:02.23#ibcon#about to read 5, iclass 24, count 0 2006.281.07:53:02.23#ibcon#read 5, iclass 24, count 0 2006.281.07:53:02.23#ibcon#about to read 6, iclass 24, count 0 2006.281.07:53:02.23#ibcon#read 6, iclass 24, count 0 2006.281.07:53:02.23#ibcon#end of sib2, iclass 24, count 0 2006.281.07:53:02.23#ibcon#*after write, iclass 24, count 0 2006.281.07:53:02.23#ibcon#*before return 0, iclass 24, count 0 2006.281.07:53:02.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:53:02.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.07:53:02.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:53:02.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:53:02.23$vc4f8/vblo=1,632.99 2006.281.07:53:02.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.07:53:02.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.07:53:02.23#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:02.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:53:02.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:53:02.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:53:02.23#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:53:02.23#ibcon#first serial, iclass 26, count 0 2006.281.07:53:02.23#ibcon#enter sib2, iclass 26, count 0 2006.281.07:53:02.23#ibcon#flushed, iclass 26, count 0 2006.281.07:53:02.23#ibcon#about to write, iclass 26, count 0 2006.281.07:53:02.23#ibcon#wrote, iclass 26, count 0 2006.281.07:53:02.23#ibcon#about to read 3, iclass 26, count 0 2006.281.07:53:02.25#ibcon#read 3, iclass 26, count 0 2006.281.07:53:02.26#ibcon#about to read 4, iclass 26, count 0 2006.281.07:53:02.26#ibcon#read 4, iclass 26, count 0 2006.281.07:53:02.26#ibcon#about to read 5, iclass 26, count 0 2006.281.07:53:02.26#ibcon#read 5, iclass 26, count 0 2006.281.07:53:02.26#ibcon#about to read 6, iclass 26, count 0 2006.281.07:53:02.26#ibcon#read 6, iclass 26, count 0 2006.281.07:53:02.26#ibcon#end of sib2, iclass 26, count 0 2006.281.07:53:02.26#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:53:02.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:53:02.26#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:53:02.26#ibcon#*before write, iclass 26, count 0 2006.281.07:53:02.26#ibcon#enter sib2, iclass 26, count 0 2006.281.07:53:02.26#ibcon#flushed, iclass 26, count 0 2006.281.07:53:02.26#ibcon#about to write, iclass 26, count 0 2006.281.07:53:02.26#ibcon#wrote, iclass 26, count 0 2006.281.07:53:02.26#ibcon#about to read 3, iclass 26, count 0 2006.281.07:53:02.30#ibcon#read 3, iclass 26, count 0 2006.281.07:53:02.30#ibcon#about to read 4, iclass 26, count 0 2006.281.07:53:02.30#ibcon#read 4, iclass 26, count 0 2006.281.07:53:02.30#ibcon#about to read 5, iclass 26, count 0 2006.281.07:53:02.30#ibcon#read 5, iclass 26, count 0 2006.281.07:53:02.30#ibcon#about to read 6, iclass 26, count 0 2006.281.07:53:02.30#ibcon#read 6, iclass 26, count 0 2006.281.07:53:02.30#ibcon#end of sib2, iclass 26, count 0 2006.281.07:53:02.30#ibcon#*after write, iclass 26, count 0 2006.281.07:53:02.30#ibcon#*before return 0, iclass 26, count 0 2006.281.07:53:02.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:53:02.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.07:53:02.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:53:02.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:53:02.30$vc4f8/vb=1,4 2006.281.07:53:02.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.07:53:02.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.07:53:02.30#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:02.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:53:02.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:53:02.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:53:02.30#ibcon#enter wrdev, iclass 28, count 2 2006.281.07:53:02.30#ibcon#first serial, iclass 28, count 2 2006.281.07:53:02.30#ibcon#enter sib2, iclass 28, count 2 2006.281.07:53:02.30#ibcon#flushed, iclass 28, count 2 2006.281.07:53:02.30#ibcon#about to write, iclass 28, count 2 2006.281.07:53:02.30#ibcon#wrote, iclass 28, count 2 2006.281.07:53:02.30#ibcon#about to read 3, iclass 28, count 2 2006.281.07:53:02.33#ibcon#read 3, iclass 28, count 2 2006.281.07:53:02.33#ibcon#about to read 4, iclass 28, count 2 2006.281.07:53:02.33#ibcon#read 4, iclass 28, count 2 2006.281.07:53:02.33#ibcon#about to read 5, iclass 28, count 2 2006.281.07:53:02.33#ibcon#read 5, iclass 28, count 2 2006.281.07:53:02.33#ibcon#about to read 6, iclass 28, count 2 2006.281.07:53:02.33#ibcon#read 6, iclass 28, count 2 2006.281.07:53:02.33#ibcon#end of sib2, iclass 28, count 2 2006.281.07:53:02.33#ibcon#*mode == 0, iclass 28, count 2 2006.281.07:53:02.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.07:53:02.33#ibcon#[27=AT01-04\r\n] 2006.281.07:53:02.33#ibcon#*before write, iclass 28, count 2 2006.281.07:53:02.33#ibcon#enter sib2, iclass 28, count 2 2006.281.07:53:02.33#ibcon#flushed, iclass 28, count 2 2006.281.07:53:02.33#ibcon#about to write, iclass 28, count 2 2006.281.07:53:02.33#ibcon#wrote, iclass 28, count 2 2006.281.07:53:02.33#ibcon#about to read 3, iclass 28, count 2 2006.281.07:53:02.35#ibcon#read 3, iclass 28, count 2 2006.281.07:53:02.35#ibcon#about to read 4, iclass 28, count 2 2006.281.07:53:02.35#ibcon#read 4, iclass 28, count 2 2006.281.07:53:02.35#ibcon#about to read 5, iclass 28, count 2 2006.281.07:53:02.35#ibcon#read 5, iclass 28, count 2 2006.281.07:53:02.35#ibcon#about to read 6, iclass 28, count 2 2006.281.07:53:02.35#ibcon#read 6, iclass 28, count 2 2006.281.07:53:02.35#ibcon#end of sib2, iclass 28, count 2 2006.281.07:53:02.35#ibcon#*after write, iclass 28, count 2 2006.281.07:53:02.35#ibcon#*before return 0, iclass 28, count 2 2006.281.07:53:02.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:53:02.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.07:53:02.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.07:53:02.35#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:02.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:53:02.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:53:02.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:53:02.47#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:53:02.47#ibcon#first serial, iclass 28, count 0 2006.281.07:53:02.47#ibcon#enter sib2, iclass 28, count 0 2006.281.07:53:02.47#ibcon#flushed, iclass 28, count 0 2006.281.07:53:02.47#ibcon#about to write, iclass 28, count 0 2006.281.07:53:02.47#ibcon#wrote, iclass 28, count 0 2006.281.07:53:02.47#ibcon#about to read 3, iclass 28, count 0 2006.281.07:53:02.49#ibcon#read 3, iclass 28, count 0 2006.281.07:53:02.49#ibcon#about to read 4, iclass 28, count 0 2006.281.07:53:02.49#ibcon#read 4, iclass 28, count 0 2006.281.07:53:02.49#ibcon#about to read 5, iclass 28, count 0 2006.281.07:53:02.49#ibcon#read 5, iclass 28, count 0 2006.281.07:53:02.49#ibcon#about to read 6, iclass 28, count 0 2006.281.07:53:02.49#ibcon#read 6, iclass 28, count 0 2006.281.07:53:02.49#ibcon#end of sib2, iclass 28, count 0 2006.281.07:53:02.49#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:53:02.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:53:02.49#ibcon#[27=USB\r\n] 2006.281.07:53:02.49#ibcon#*before write, iclass 28, count 0 2006.281.07:53:02.49#ibcon#enter sib2, iclass 28, count 0 2006.281.07:53:02.49#ibcon#flushed, iclass 28, count 0 2006.281.07:53:02.49#ibcon#about to write, iclass 28, count 0 2006.281.07:53:02.49#ibcon#wrote, iclass 28, count 0 2006.281.07:53:02.49#ibcon#about to read 3, iclass 28, count 0 2006.281.07:53:02.52#ibcon#read 3, iclass 28, count 0 2006.281.07:53:02.52#ibcon#about to read 4, iclass 28, count 0 2006.281.07:53:02.52#ibcon#read 4, iclass 28, count 0 2006.281.07:53:02.52#ibcon#about to read 5, iclass 28, count 0 2006.281.07:53:02.52#ibcon#read 5, iclass 28, count 0 2006.281.07:53:02.52#ibcon#about to read 6, iclass 28, count 0 2006.281.07:53:02.52#ibcon#read 6, iclass 28, count 0 2006.281.07:53:02.52#ibcon#end of sib2, iclass 28, count 0 2006.281.07:53:02.52#ibcon#*after write, iclass 28, count 0 2006.281.07:53:02.52#ibcon#*before return 0, iclass 28, count 0 2006.281.07:53:02.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:53:02.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.07:53:02.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:53:02.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:53:02.52$vc4f8/vblo=2,640.99 2006.281.07:53:02.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.07:53:02.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.07:53:02.52#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:02.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:53:02.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:53:02.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:53:02.52#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:53:02.52#ibcon#first serial, iclass 30, count 0 2006.281.07:53:02.52#ibcon#enter sib2, iclass 30, count 0 2006.281.07:53:02.52#ibcon#flushed, iclass 30, count 0 2006.281.07:53:02.52#ibcon#about to write, iclass 30, count 0 2006.281.07:53:02.52#ibcon#wrote, iclass 30, count 0 2006.281.07:53:02.52#ibcon#about to read 3, iclass 30, count 0 2006.281.07:53:02.54#ibcon#read 3, iclass 30, count 0 2006.281.07:53:02.54#ibcon#about to read 4, iclass 30, count 0 2006.281.07:53:02.54#ibcon#read 4, iclass 30, count 0 2006.281.07:53:02.54#ibcon#about to read 5, iclass 30, count 0 2006.281.07:53:02.54#ibcon#read 5, iclass 30, count 0 2006.281.07:53:02.54#ibcon#about to read 6, iclass 30, count 0 2006.281.07:53:02.54#ibcon#read 6, iclass 30, count 0 2006.281.07:53:02.56#ibcon#end of sib2, iclass 30, count 0 2006.281.07:53:02.56#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:53:02.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:53:02.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:53:02.56#ibcon#*before write, iclass 30, count 0 2006.281.07:53:02.56#ibcon#enter sib2, iclass 30, count 0 2006.281.07:53:02.56#ibcon#flushed, iclass 30, count 0 2006.281.07:53:02.56#ibcon#about to write, iclass 30, count 0 2006.281.07:53:02.56#ibcon#wrote, iclass 30, count 0 2006.281.07:53:02.56#ibcon#about to read 3, iclass 30, count 0 2006.281.07:53:02.60#ibcon#read 3, iclass 30, count 0 2006.281.07:53:02.60#ibcon#about to read 4, iclass 30, count 0 2006.281.07:53:02.60#ibcon#read 4, iclass 30, count 0 2006.281.07:53:02.60#ibcon#about to read 5, iclass 30, count 0 2006.281.07:53:02.60#ibcon#read 5, iclass 30, count 0 2006.281.07:53:02.60#ibcon#about to read 6, iclass 30, count 0 2006.281.07:53:02.60#ibcon#read 6, iclass 30, count 0 2006.281.07:53:02.60#ibcon#end of sib2, iclass 30, count 0 2006.281.07:53:02.60#ibcon#*after write, iclass 30, count 0 2006.281.07:53:02.60#ibcon#*before return 0, iclass 30, count 0 2006.281.07:53:02.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:53:02.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.07:53:02.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:53:02.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:53:02.60$vc4f8/vb=2,5 2006.281.07:53:02.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.07:53:02.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.07:53:02.60#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:02.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:53:02.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:53:02.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:53:02.64#ibcon#enter wrdev, iclass 32, count 2 2006.281.07:53:02.64#ibcon#first serial, iclass 32, count 2 2006.281.07:53:02.64#ibcon#enter sib2, iclass 32, count 2 2006.281.07:53:02.64#ibcon#flushed, iclass 32, count 2 2006.281.07:53:02.64#ibcon#about to write, iclass 32, count 2 2006.281.07:53:02.64#ibcon#wrote, iclass 32, count 2 2006.281.07:53:02.64#ibcon#about to read 3, iclass 32, count 2 2006.281.07:53:02.66#ibcon#read 3, iclass 32, count 2 2006.281.07:53:02.66#ibcon#about to read 4, iclass 32, count 2 2006.281.07:53:02.66#ibcon#read 4, iclass 32, count 2 2006.281.07:53:02.66#ibcon#about to read 5, iclass 32, count 2 2006.281.07:53:02.66#ibcon#read 5, iclass 32, count 2 2006.281.07:53:02.66#ibcon#about to read 6, iclass 32, count 2 2006.281.07:53:02.66#ibcon#read 6, iclass 32, count 2 2006.281.07:53:02.66#ibcon#end of sib2, iclass 32, count 2 2006.281.07:53:02.66#ibcon#*mode == 0, iclass 32, count 2 2006.281.07:53:02.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.07:53:02.66#ibcon#[27=AT02-05\r\n] 2006.281.07:53:02.66#ibcon#*before write, iclass 32, count 2 2006.281.07:53:02.66#ibcon#enter sib2, iclass 32, count 2 2006.281.07:53:02.66#ibcon#flushed, iclass 32, count 2 2006.281.07:53:02.66#ibcon#about to write, iclass 32, count 2 2006.281.07:53:02.66#ibcon#wrote, iclass 32, count 2 2006.281.07:53:02.66#ibcon#about to read 3, iclass 32, count 2 2006.281.07:53:02.69#ibcon#read 3, iclass 32, count 2 2006.281.07:53:02.69#ibcon#about to read 4, iclass 32, count 2 2006.281.07:53:02.69#ibcon#read 4, iclass 32, count 2 2006.281.07:53:02.69#ibcon#about to read 5, iclass 32, count 2 2006.281.07:53:02.69#ibcon#read 5, iclass 32, count 2 2006.281.07:53:02.69#ibcon#about to read 6, iclass 32, count 2 2006.281.07:53:02.69#ibcon#read 6, iclass 32, count 2 2006.281.07:53:02.69#ibcon#end of sib2, iclass 32, count 2 2006.281.07:53:02.69#ibcon#*after write, iclass 32, count 2 2006.281.07:53:02.69#ibcon#*before return 0, iclass 32, count 2 2006.281.07:53:02.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:53:02.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.07:53:02.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.07:53:02.69#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:02.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:53:02.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:53:02.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:53:02.81#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:53:02.81#ibcon#first serial, iclass 32, count 0 2006.281.07:53:02.81#ibcon#enter sib2, iclass 32, count 0 2006.281.07:53:02.81#ibcon#flushed, iclass 32, count 0 2006.281.07:53:02.81#ibcon#about to write, iclass 32, count 0 2006.281.07:53:02.81#ibcon#wrote, iclass 32, count 0 2006.281.07:53:02.81#ibcon#about to read 3, iclass 32, count 0 2006.281.07:53:02.83#ibcon#read 3, iclass 32, count 0 2006.281.07:53:02.83#ibcon#about to read 4, iclass 32, count 0 2006.281.07:53:02.83#ibcon#read 4, iclass 32, count 0 2006.281.07:53:02.83#ibcon#about to read 5, iclass 32, count 0 2006.281.07:53:02.83#ibcon#read 5, iclass 32, count 0 2006.281.07:53:02.83#ibcon#about to read 6, iclass 32, count 0 2006.281.07:53:02.83#ibcon#read 6, iclass 32, count 0 2006.281.07:53:02.83#ibcon#end of sib2, iclass 32, count 0 2006.281.07:53:02.83#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:53:02.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:53:02.83#ibcon#[27=USB\r\n] 2006.281.07:53:02.83#ibcon#*before write, iclass 32, count 0 2006.281.07:53:02.83#ibcon#enter sib2, iclass 32, count 0 2006.281.07:53:02.83#ibcon#flushed, iclass 32, count 0 2006.281.07:53:02.83#ibcon#about to write, iclass 32, count 0 2006.281.07:53:02.83#ibcon#wrote, iclass 32, count 0 2006.281.07:53:02.83#ibcon#about to read 3, iclass 32, count 0 2006.281.07:53:02.86#ibcon#read 3, iclass 32, count 0 2006.281.07:53:02.86#ibcon#about to read 4, iclass 32, count 0 2006.281.07:53:02.86#ibcon#read 4, iclass 32, count 0 2006.281.07:53:02.86#ibcon#about to read 5, iclass 32, count 0 2006.281.07:53:02.86#ibcon#read 5, iclass 32, count 0 2006.281.07:53:02.86#ibcon#about to read 6, iclass 32, count 0 2006.281.07:53:02.86#ibcon#read 6, iclass 32, count 0 2006.281.07:53:02.86#ibcon#end of sib2, iclass 32, count 0 2006.281.07:53:02.86#ibcon#*after write, iclass 32, count 0 2006.281.07:53:02.86#ibcon#*before return 0, iclass 32, count 0 2006.281.07:53:02.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:53:02.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.07:53:02.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:53:02.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:53:02.86$vc4f8/vblo=3,656.99 2006.281.07:53:02.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.07:53:02.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.07:53:02.86#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:02.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:53:02.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:53:02.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:53:02.86#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:53:02.86#ibcon#first serial, iclass 34, count 0 2006.281.07:53:02.86#ibcon#enter sib2, iclass 34, count 0 2006.281.07:53:02.86#ibcon#flushed, iclass 34, count 0 2006.281.07:53:02.86#ibcon#about to write, iclass 34, count 0 2006.281.07:53:02.86#ibcon#wrote, iclass 34, count 0 2006.281.07:53:02.86#ibcon#about to read 3, iclass 34, count 0 2006.281.07:53:02.88#ibcon#read 3, iclass 34, count 0 2006.281.07:53:02.88#ibcon#about to read 4, iclass 34, count 0 2006.281.07:53:02.88#ibcon#read 4, iclass 34, count 0 2006.281.07:53:02.88#ibcon#about to read 5, iclass 34, count 0 2006.281.07:53:02.88#ibcon#read 5, iclass 34, count 0 2006.281.07:53:02.88#ibcon#about to read 6, iclass 34, count 0 2006.281.07:53:02.88#ibcon#read 6, iclass 34, count 0 2006.281.07:53:02.88#ibcon#end of sib2, iclass 34, count 0 2006.281.07:53:02.88#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:53:02.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:53:02.88#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:53:02.88#ibcon#*before write, iclass 34, count 0 2006.281.07:53:02.88#ibcon#enter sib2, iclass 34, count 0 2006.281.07:53:02.88#ibcon#flushed, iclass 34, count 0 2006.281.07:53:02.88#ibcon#about to write, iclass 34, count 0 2006.281.07:53:02.88#ibcon#wrote, iclass 34, count 0 2006.281.07:53:02.88#ibcon#about to read 3, iclass 34, count 0 2006.281.07:53:02.92#ibcon#read 3, iclass 34, count 0 2006.281.07:53:02.92#ibcon#about to read 4, iclass 34, count 0 2006.281.07:53:02.92#ibcon#read 4, iclass 34, count 0 2006.281.07:53:02.92#ibcon#about to read 5, iclass 34, count 0 2006.281.07:53:02.92#ibcon#read 5, iclass 34, count 0 2006.281.07:53:02.92#ibcon#about to read 6, iclass 34, count 0 2006.281.07:53:02.92#ibcon#read 6, iclass 34, count 0 2006.281.07:53:02.92#ibcon#end of sib2, iclass 34, count 0 2006.281.07:53:02.92#ibcon#*after write, iclass 34, count 0 2006.281.07:53:02.92#ibcon#*before return 0, iclass 34, count 0 2006.281.07:53:02.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:53:02.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.07:53:02.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:53:02.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:53:02.92$vc4f8/vb=3,4 2006.281.07:53:02.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.07:53:02.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.07:53:02.92#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:02.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:02.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:02.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:02.98#ibcon#enter wrdev, iclass 36, count 2 2006.281.07:53:02.98#ibcon#first serial, iclass 36, count 2 2006.281.07:53:02.98#ibcon#enter sib2, iclass 36, count 2 2006.281.07:53:02.98#ibcon#flushed, iclass 36, count 2 2006.281.07:53:02.98#ibcon#about to write, iclass 36, count 2 2006.281.07:53:02.98#ibcon#wrote, iclass 36, count 2 2006.281.07:53:02.98#ibcon#about to read 3, iclass 36, count 2 2006.281.07:53:03.00#ibcon#read 3, iclass 36, count 2 2006.281.07:53:03.00#ibcon#about to read 4, iclass 36, count 2 2006.281.07:53:03.00#ibcon#read 4, iclass 36, count 2 2006.281.07:53:03.00#ibcon#about to read 5, iclass 36, count 2 2006.281.07:53:03.00#ibcon#read 5, iclass 36, count 2 2006.281.07:53:03.00#ibcon#about to read 6, iclass 36, count 2 2006.281.07:53:03.00#ibcon#read 6, iclass 36, count 2 2006.281.07:53:03.00#ibcon#end of sib2, iclass 36, count 2 2006.281.07:53:03.00#ibcon#*mode == 0, iclass 36, count 2 2006.281.07:53:03.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.07:53:03.00#ibcon#[27=AT03-04\r\n] 2006.281.07:53:03.00#ibcon#*before write, iclass 36, count 2 2006.281.07:53:03.00#ibcon#enter sib2, iclass 36, count 2 2006.281.07:53:03.00#ibcon#flushed, iclass 36, count 2 2006.281.07:53:03.00#ibcon#about to write, iclass 36, count 2 2006.281.07:53:03.00#ibcon#wrote, iclass 36, count 2 2006.281.07:53:03.00#ibcon#about to read 3, iclass 36, count 2 2006.281.07:53:03.03#ibcon#read 3, iclass 36, count 2 2006.281.07:53:03.03#ibcon#about to read 4, iclass 36, count 2 2006.281.07:53:03.03#ibcon#read 4, iclass 36, count 2 2006.281.07:53:03.03#ibcon#about to read 5, iclass 36, count 2 2006.281.07:53:03.03#ibcon#read 5, iclass 36, count 2 2006.281.07:53:03.03#ibcon#about to read 6, iclass 36, count 2 2006.281.07:53:03.03#ibcon#read 6, iclass 36, count 2 2006.281.07:53:03.03#ibcon#end of sib2, iclass 36, count 2 2006.281.07:53:03.03#ibcon#*after write, iclass 36, count 2 2006.281.07:53:03.03#ibcon#*before return 0, iclass 36, count 2 2006.281.07:53:03.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:03.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.07:53:03.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.07:53:03.03#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:03.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:03.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:03.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:03.15#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:53:03.15#ibcon#first serial, iclass 36, count 0 2006.281.07:53:03.15#ibcon#enter sib2, iclass 36, count 0 2006.281.07:53:03.15#ibcon#flushed, iclass 36, count 0 2006.281.07:53:03.15#ibcon#about to write, iclass 36, count 0 2006.281.07:53:03.15#ibcon#wrote, iclass 36, count 0 2006.281.07:53:03.15#ibcon#about to read 3, iclass 36, count 0 2006.281.07:53:03.17#ibcon#read 3, iclass 36, count 0 2006.281.07:53:03.17#ibcon#about to read 4, iclass 36, count 0 2006.281.07:53:03.17#ibcon#read 4, iclass 36, count 0 2006.281.07:53:03.17#ibcon#about to read 5, iclass 36, count 0 2006.281.07:53:03.17#ibcon#read 5, iclass 36, count 0 2006.281.07:53:03.17#ibcon#about to read 6, iclass 36, count 0 2006.281.07:53:03.17#ibcon#read 6, iclass 36, count 0 2006.281.07:53:03.17#ibcon#end of sib2, iclass 36, count 0 2006.281.07:53:03.17#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:53:03.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:53:03.17#ibcon#[27=USB\r\n] 2006.281.07:53:03.17#ibcon#*before write, iclass 36, count 0 2006.281.07:53:03.17#ibcon#enter sib2, iclass 36, count 0 2006.281.07:53:03.17#ibcon#flushed, iclass 36, count 0 2006.281.07:53:03.17#ibcon#about to write, iclass 36, count 0 2006.281.07:53:03.17#ibcon#wrote, iclass 36, count 0 2006.281.07:53:03.17#ibcon#about to read 3, iclass 36, count 0 2006.281.07:53:03.20#ibcon#read 3, iclass 36, count 0 2006.281.07:53:03.20#ibcon#about to read 4, iclass 36, count 0 2006.281.07:53:03.20#ibcon#read 4, iclass 36, count 0 2006.281.07:53:03.20#ibcon#about to read 5, iclass 36, count 0 2006.281.07:53:03.20#ibcon#read 5, iclass 36, count 0 2006.281.07:53:03.20#ibcon#about to read 6, iclass 36, count 0 2006.281.07:53:03.20#ibcon#read 6, iclass 36, count 0 2006.281.07:53:03.20#ibcon#end of sib2, iclass 36, count 0 2006.281.07:53:03.20#ibcon#*after write, iclass 36, count 0 2006.281.07:53:03.20#ibcon#*before return 0, iclass 36, count 0 2006.281.07:53:03.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:03.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.07:53:03.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:53:03.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:53:03.20$vc4f8/vblo=4,712.99 2006.281.07:53:03.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.07:53:03.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.07:53:03.20#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:03.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:03.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:03.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:03.20#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:53:03.20#ibcon#first serial, iclass 38, count 0 2006.281.07:53:03.20#ibcon#enter sib2, iclass 38, count 0 2006.281.07:53:03.20#ibcon#flushed, iclass 38, count 0 2006.281.07:53:03.20#ibcon#about to write, iclass 38, count 0 2006.281.07:53:03.20#ibcon#wrote, iclass 38, count 0 2006.281.07:53:03.20#ibcon#about to read 3, iclass 38, count 0 2006.281.07:53:03.22#ibcon#read 3, iclass 38, count 0 2006.281.07:53:03.22#ibcon#about to read 4, iclass 38, count 0 2006.281.07:53:03.22#ibcon#read 4, iclass 38, count 0 2006.281.07:53:03.22#ibcon#about to read 5, iclass 38, count 0 2006.281.07:53:03.22#ibcon#read 5, iclass 38, count 0 2006.281.07:53:03.22#ibcon#about to read 6, iclass 38, count 0 2006.281.07:53:03.22#ibcon#read 6, iclass 38, count 0 2006.281.07:53:03.22#ibcon#end of sib2, iclass 38, count 0 2006.281.07:53:03.22#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:53:03.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:53:03.22#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:53:03.22#ibcon#*before write, iclass 38, count 0 2006.281.07:53:03.22#ibcon#enter sib2, iclass 38, count 0 2006.281.07:53:03.22#ibcon#flushed, iclass 38, count 0 2006.281.07:53:03.22#ibcon#about to write, iclass 38, count 0 2006.281.07:53:03.22#ibcon#wrote, iclass 38, count 0 2006.281.07:53:03.22#ibcon#about to read 3, iclass 38, count 0 2006.281.07:53:03.26#ibcon#read 3, iclass 38, count 0 2006.281.07:53:03.26#ibcon#about to read 4, iclass 38, count 0 2006.281.07:53:03.26#ibcon#read 4, iclass 38, count 0 2006.281.07:53:03.26#ibcon#about to read 5, iclass 38, count 0 2006.281.07:53:03.26#ibcon#read 5, iclass 38, count 0 2006.281.07:53:03.26#ibcon#about to read 6, iclass 38, count 0 2006.281.07:53:03.26#ibcon#read 6, iclass 38, count 0 2006.281.07:53:03.26#ibcon#end of sib2, iclass 38, count 0 2006.281.07:53:03.26#ibcon#*after write, iclass 38, count 0 2006.281.07:53:03.26#ibcon#*before return 0, iclass 38, count 0 2006.281.07:53:03.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:03.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.07:53:03.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:53:03.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:53:03.26$vc4f8/vb=4,4 2006.281.07:53:03.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.07:53:03.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.07:53:03.26#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:03.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:03.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:03.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:03.32#ibcon#enter wrdev, iclass 40, count 2 2006.281.07:53:03.32#ibcon#first serial, iclass 40, count 2 2006.281.07:53:03.32#ibcon#enter sib2, iclass 40, count 2 2006.281.07:53:03.32#ibcon#flushed, iclass 40, count 2 2006.281.07:53:03.32#ibcon#about to write, iclass 40, count 2 2006.281.07:53:03.32#ibcon#wrote, iclass 40, count 2 2006.281.07:53:03.32#ibcon#about to read 3, iclass 40, count 2 2006.281.07:53:03.34#ibcon#read 3, iclass 40, count 2 2006.281.07:53:03.34#ibcon#about to read 4, iclass 40, count 2 2006.281.07:53:03.34#ibcon#read 4, iclass 40, count 2 2006.281.07:53:03.34#ibcon#about to read 5, iclass 40, count 2 2006.281.07:53:03.34#ibcon#read 5, iclass 40, count 2 2006.281.07:53:03.34#ibcon#about to read 6, iclass 40, count 2 2006.281.07:53:03.34#ibcon#read 6, iclass 40, count 2 2006.281.07:53:03.34#ibcon#end of sib2, iclass 40, count 2 2006.281.07:53:03.34#ibcon#*mode == 0, iclass 40, count 2 2006.281.07:53:03.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.07:53:03.34#ibcon#[27=AT04-04\r\n] 2006.281.07:53:03.34#ibcon#*before write, iclass 40, count 2 2006.281.07:53:03.34#ibcon#enter sib2, iclass 40, count 2 2006.281.07:53:03.34#ibcon#flushed, iclass 40, count 2 2006.281.07:53:03.34#ibcon#about to write, iclass 40, count 2 2006.281.07:53:03.34#ibcon#wrote, iclass 40, count 2 2006.281.07:53:03.34#ibcon#about to read 3, iclass 40, count 2 2006.281.07:53:03.37#ibcon#read 3, iclass 40, count 2 2006.281.07:53:03.37#ibcon#about to read 4, iclass 40, count 2 2006.281.07:53:03.37#ibcon#read 4, iclass 40, count 2 2006.281.07:53:03.37#ibcon#about to read 5, iclass 40, count 2 2006.281.07:53:03.37#ibcon#read 5, iclass 40, count 2 2006.281.07:53:03.37#ibcon#about to read 6, iclass 40, count 2 2006.281.07:53:03.37#ibcon#read 6, iclass 40, count 2 2006.281.07:53:03.37#ibcon#end of sib2, iclass 40, count 2 2006.281.07:53:03.37#ibcon#*after write, iclass 40, count 2 2006.281.07:53:03.37#ibcon#*before return 0, iclass 40, count 2 2006.281.07:53:03.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:03.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.07:53:03.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.07:53:03.37#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:03.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:03.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:03.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:03.49#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:53:03.49#ibcon#first serial, iclass 40, count 0 2006.281.07:53:03.49#ibcon#enter sib2, iclass 40, count 0 2006.281.07:53:03.49#ibcon#flushed, iclass 40, count 0 2006.281.07:53:03.49#ibcon#about to write, iclass 40, count 0 2006.281.07:53:03.49#ibcon#wrote, iclass 40, count 0 2006.281.07:53:03.49#ibcon#about to read 3, iclass 40, count 0 2006.281.07:53:03.51#ibcon#read 3, iclass 40, count 0 2006.281.07:53:03.51#ibcon#about to read 4, iclass 40, count 0 2006.281.07:53:03.51#ibcon#read 4, iclass 40, count 0 2006.281.07:53:03.51#ibcon#about to read 5, iclass 40, count 0 2006.281.07:53:03.51#ibcon#read 5, iclass 40, count 0 2006.281.07:53:03.51#ibcon#about to read 6, iclass 40, count 0 2006.281.07:53:03.51#ibcon#read 6, iclass 40, count 0 2006.281.07:53:03.51#ibcon#end of sib2, iclass 40, count 0 2006.281.07:53:03.51#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:53:03.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:53:03.51#ibcon#[27=USB\r\n] 2006.281.07:53:03.51#ibcon#*before write, iclass 40, count 0 2006.281.07:53:03.51#ibcon#enter sib2, iclass 40, count 0 2006.281.07:53:03.51#ibcon#flushed, iclass 40, count 0 2006.281.07:53:03.51#ibcon#about to write, iclass 40, count 0 2006.281.07:53:03.51#ibcon#wrote, iclass 40, count 0 2006.281.07:53:03.51#ibcon#about to read 3, iclass 40, count 0 2006.281.07:53:03.54#ibcon#read 3, iclass 40, count 0 2006.281.07:53:03.54#ibcon#about to read 4, iclass 40, count 0 2006.281.07:53:03.54#ibcon#read 4, iclass 40, count 0 2006.281.07:53:03.54#ibcon#about to read 5, iclass 40, count 0 2006.281.07:53:03.54#ibcon#read 5, iclass 40, count 0 2006.281.07:53:03.54#ibcon#about to read 6, iclass 40, count 0 2006.281.07:53:03.54#ibcon#read 6, iclass 40, count 0 2006.281.07:53:03.54#ibcon#end of sib2, iclass 40, count 0 2006.281.07:53:03.54#ibcon#*after write, iclass 40, count 0 2006.281.07:53:03.54#ibcon#*before return 0, iclass 40, count 0 2006.281.07:53:03.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:03.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.07:53:03.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:53:03.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:53:03.54$vc4f8/vblo=5,744.99 2006.281.07:53:03.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.07:53:03.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.07:53:03.54#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:03.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:03.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:03.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:03.54#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:53:03.54#ibcon#first serial, iclass 4, count 0 2006.281.07:53:03.54#ibcon#enter sib2, iclass 4, count 0 2006.281.07:53:03.54#ibcon#flushed, iclass 4, count 0 2006.281.07:53:03.54#ibcon#about to write, iclass 4, count 0 2006.281.07:53:03.54#ibcon#wrote, iclass 4, count 0 2006.281.07:53:03.54#ibcon#about to read 3, iclass 4, count 0 2006.281.07:53:03.56#ibcon#read 3, iclass 4, count 0 2006.281.07:53:03.56#ibcon#about to read 4, iclass 4, count 0 2006.281.07:53:03.56#ibcon#read 4, iclass 4, count 0 2006.281.07:53:03.56#ibcon#about to read 5, iclass 4, count 0 2006.281.07:53:03.56#ibcon#read 5, iclass 4, count 0 2006.281.07:53:03.56#ibcon#about to read 6, iclass 4, count 0 2006.281.07:53:03.56#ibcon#read 6, iclass 4, count 0 2006.281.07:53:03.56#ibcon#end of sib2, iclass 4, count 0 2006.281.07:53:03.56#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:53:03.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:53:03.56#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:53:03.56#ibcon#*before write, iclass 4, count 0 2006.281.07:53:03.56#ibcon#enter sib2, iclass 4, count 0 2006.281.07:53:03.56#ibcon#flushed, iclass 4, count 0 2006.281.07:53:03.56#ibcon#about to write, iclass 4, count 0 2006.281.07:53:03.56#ibcon#wrote, iclass 4, count 0 2006.281.07:53:03.56#ibcon#about to read 3, iclass 4, count 0 2006.281.07:53:03.60#ibcon#read 3, iclass 4, count 0 2006.281.07:53:03.60#ibcon#about to read 4, iclass 4, count 0 2006.281.07:53:03.60#ibcon#read 4, iclass 4, count 0 2006.281.07:53:03.60#ibcon#about to read 5, iclass 4, count 0 2006.281.07:53:03.60#ibcon#read 5, iclass 4, count 0 2006.281.07:53:03.60#ibcon#about to read 6, iclass 4, count 0 2006.281.07:53:03.60#ibcon#read 6, iclass 4, count 0 2006.281.07:53:03.60#ibcon#end of sib2, iclass 4, count 0 2006.281.07:53:03.60#ibcon#*after write, iclass 4, count 0 2006.281.07:53:03.60#ibcon#*before return 0, iclass 4, count 0 2006.281.07:53:03.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:03.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.07:53:03.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:53:03.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:53:03.60$vc4f8/vb=5,4 2006.281.07:53:03.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.07:53:03.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.07:53:03.60#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:03.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:03.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:03.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:03.66#ibcon#enter wrdev, iclass 6, count 2 2006.281.07:53:03.66#ibcon#first serial, iclass 6, count 2 2006.281.07:53:03.66#ibcon#enter sib2, iclass 6, count 2 2006.281.07:53:03.66#ibcon#flushed, iclass 6, count 2 2006.281.07:53:03.66#ibcon#about to write, iclass 6, count 2 2006.281.07:53:03.66#ibcon#wrote, iclass 6, count 2 2006.281.07:53:03.66#ibcon#about to read 3, iclass 6, count 2 2006.281.07:53:03.68#ibcon#read 3, iclass 6, count 2 2006.281.07:53:03.68#ibcon#about to read 4, iclass 6, count 2 2006.281.07:53:03.68#ibcon#read 4, iclass 6, count 2 2006.281.07:53:03.68#ibcon#about to read 5, iclass 6, count 2 2006.281.07:53:03.68#ibcon#read 5, iclass 6, count 2 2006.281.07:53:03.68#ibcon#about to read 6, iclass 6, count 2 2006.281.07:53:03.68#ibcon#read 6, iclass 6, count 2 2006.281.07:53:03.68#ibcon#end of sib2, iclass 6, count 2 2006.281.07:53:03.68#ibcon#*mode == 0, iclass 6, count 2 2006.281.07:53:03.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.07:53:03.68#ibcon#[27=AT05-04\r\n] 2006.281.07:53:03.68#ibcon#*before write, iclass 6, count 2 2006.281.07:53:03.68#ibcon#enter sib2, iclass 6, count 2 2006.281.07:53:03.68#ibcon#flushed, iclass 6, count 2 2006.281.07:53:03.68#ibcon#about to write, iclass 6, count 2 2006.281.07:53:03.68#ibcon#wrote, iclass 6, count 2 2006.281.07:53:03.68#ibcon#about to read 3, iclass 6, count 2 2006.281.07:53:03.71#ibcon#read 3, iclass 6, count 2 2006.281.07:53:03.71#ibcon#about to read 4, iclass 6, count 2 2006.281.07:53:03.71#ibcon#read 4, iclass 6, count 2 2006.281.07:53:03.71#ibcon#about to read 5, iclass 6, count 2 2006.281.07:53:03.71#ibcon#read 5, iclass 6, count 2 2006.281.07:53:03.71#ibcon#about to read 6, iclass 6, count 2 2006.281.07:53:03.71#ibcon#read 6, iclass 6, count 2 2006.281.07:53:03.71#ibcon#end of sib2, iclass 6, count 2 2006.281.07:53:03.71#ibcon#*after write, iclass 6, count 2 2006.281.07:53:03.71#ibcon#*before return 0, iclass 6, count 2 2006.281.07:53:03.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:03.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.07:53:03.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.07:53:03.71#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:03.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:03.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:03.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:03.83#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:53:03.83#ibcon#first serial, iclass 6, count 0 2006.281.07:53:03.83#ibcon#enter sib2, iclass 6, count 0 2006.281.07:53:03.83#ibcon#flushed, iclass 6, count 0 2006.281.07:53:03.83#ibcon#about to write, iclass 6, count 0 2006.281.07:53:03.83#ibcon#wrote, iclass 6, count 0 2006.281.07:53:03.83#ibcon#about to read 3, iclass 6, count 0 2006.281.07:53:03.85#ibcon#read 3, iclass 6, count 0 2006.281.07:53:03.85#ibcon#about to read 4, iclass 6, count 0 2006.281.07:53:03.85#ibcon#read 4, iclass 6, count 0 2006.281.07:53:03.85#ibcon#about to read 5, iclass 6, count 0 2006.281.07:53:03.85#ibcon#read 5, iclass 6, count 0 2006.281.07:53:03.85#ibcon#about to read 6, iclass 6, count 0 2006.281.07:53:03.85#ibcon#read 6, iclass 6, count 0 2006.281.07:53:03.85#ibcon#end of sib2, iclass 6, count 0 2006.281.07:53:03.85#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:53:03.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:53:03.85#ibcon#[27=USB\r\n] 2006.281.07:53:03.85#ibcon#*before write, iclass 6, count 0 2006.281.07:53:03.85#ibcon#enter sib2, iclass 6, count 0 2006.281.07:53:03.85#ibcon#flushed, iclass 6, count 0 2006.281.07:53:03.85#ibcon#about to write, iclass 6, count 0 2006.281.07:53:03.85#ibcon#wrote, iclass 6, count 0 2006.281.07:53:03.85#ibcon#about to read 3, iclass 6, count 0 2006.281.07:53:03.88#ibcon#read 3, iclass 6, count 0 2006.281.07:53:03.88#ibcon#about to read 4, iclass 6, count 0 2006.281.07:53:03.88#ibcon#read 4, iclass 6, count 0 2006.281.07:53:03.88#ibcon#about to read 5, iclass 6, count 0 2006.281.07:53:03.88#ibcon#read 5, iclass 6, count 0 2006.281.07:53:03.88#ibcon#about to read 6, iclass 6, count 0 2006.281.07:53:03.88#ibcon#read 6, iclass 6, count 0 2006.281.07:53:03.88#ibcon#end of sib2, iclass 6, count 0 2006.281.07:53:03.88#ibcon#*after write, iclass 6, count 0 2006.281.07:53:03.88#ibcon#*before return 0, iclass 6, count 0 2006.281.07:53:03.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:03.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.07:53:03.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:53:03.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:53:03.88$vc4f8/vblo=6,752.99 2006.281.07:53:03.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.07:53:03.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.07:53:03.88#ibcon#ireg 17 cls_cnt 0 2006.281.07:53:03.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:03.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:03.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:03.88#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:53:03.88#ibcon#first serial, iclass 10, count 0 2006.281.07:53:03.88#ibcon#enter sib2, iclass 10, count 0 2006.281.07:53:03.88#ibcon#flushed, iclass 10, count 0 2006.281.07:53:03.88#ibcon#about to write, iclass 10, count 0 2006.281.07:53:03.88#ibcon#wrote, iclass 10, count 0 2006.281.07:53:03.88#ibcon#about to read 3, iclass 10, count 0 2006.281.07:53:03.90#ibcon#read 3, iclass 10, count 0 2006.281.07:53:03.90#ibcon#about to read 4, iclass 10, count 0 2006.281.07:53:03.90#ibcon#read 4, iclass 10, count 0 2006.281.07:53:03.90#ibcon#about to read 5, iclass 10, count 0 2006.281.07:53:03.90#ibcon#read 5, iclass 10, count 0 2006.281.07:53:03.90#ibcon#about to read 6, iclass 10, count 0 2006.281.07:53:03.90#ibcon#read 6, iclass 10, count 0 2006.281.07:53:03.90#ibcon#end of sib2, iclass 10, count 0 2006.281.07:53:03.90#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:53:03.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:53:03.90#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:53:03.90#ibcon#*before write, iclass 10, count 0 2006.281.07:53:03.90#ibcon#enter sib2, iclass 10, count 0 2006.281.07:53:03.90#ibcon#flushed, iclass 10, count 0 2006.281.07:53:03.90#ibcon#about to write, iclass 10, count 0 2006.281.07:53:03.90#ibcon#wrote, iclass 10, count 0 2006.281.07:53:03.90#ibcon#about to read 3, iclass 10, count 0 2006.281.07:53:03.95#ibcon#read 3, iclass 10, count 0 2006.281.07:53:03.95#ibcon#about to read 4, iclass 10, count 0 2006.281.07:53:03.95#ibcon#read 4, iclass 10, count 0 2006.281.07:53:03.95#ibcon#about to read 5, iclass 10, count 0 2006.281.07:53:03.95#ibcon#read 5, iclass 10, count 0 2006.281.07:53:03.95#ibcon#about to read 6, iclass 10, count 0 2006.281.07:53:03.95#ibcon#read 6, iclass 10, count 0 2006.281.07:53:03.95#ibcon#end of sib2, iclass 10, count 0 2006.281.07:53:03.95#ibcon#*after write, iclass 10, count 0 2006.281.07:53:03.95#ibcon#*before return 0, iclass 10, count 0 2006.281.07:53:03.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:03.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.07:53:03.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:53:03.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:53:03.95$vc4f8/vb=6,4 2006.281.07:53:03.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.07:53:03.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.07:53:03.95#ibcon#ireg 11 cls_cnt 2 2006.281.07:53:03.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:03.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:03.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:03.99#ibcon#enter wrdev, iclass 12, count 2 2006.281.07:53:03.99#ibcon#first serial, iclass 12, count 2 2006.281.07:53:03.99#ibcon#enter sib2, iclass 12, count 2 2006.281.07:53:03.99#ibcon#flushed, iclass 12, count 2 2006.281.07:53:03.99#ibcon#about to write, iclass 12, count 2 2006.281.07:53:03.99#ibcon#wrote, iclass 12, count 2 2006.281.07:53:03.99#ibcon#about to read 3, iclass 12, count 2 2006.281.07:53:04.02#ibcon#read 3, iclass 12, count 2 2006.281.07:53:04.02#ibcon#about to read 4, iclass 12, count 2 2006.281.07:53:04.02#ibcon#read 4, iclass 12, count 2 2006.281.07:53:04.02#ibcon#about to read 5, iclass 12, count 2 2006.281.07:53:04.02#ibcon#read 5, iclass 12, count 2 2006.281.07:53:04.02#ibcon#about to read 6, iclass 12, count 2 2006.281.07:53:04.02#ibcon#read 6, iclass 12, count 2 2006.281.07:53:04.02#ibcon#end of sib2, iclass 12, count 2 2006.281.07:53:04.02#ibcon#*mode == 0, iclass 12, count 2 2006.281.07:53:04.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.07:53:04.02#ibcon#[27=AT06-04\r\n] 2006.281.07:53:04.02#ibcon#*before write, iclass 12, count 2 2006.281.07:53:04.02#ibcon#enter sib2, iclass 12, count 2 2006.281.07:53:04.02#ibcon#flushed, iclass 12, count 2 2006.281.07:53:04.02#ibcon#about to write, iclass 12, count 2 2006.281.07:53:04.02#ibcon#wrote, iclass 12, count 2 2006.281.07:53:04.02#ibcon#about to read 3, iclass 12, count 2 2006.281.07:53:04.05#ibcon#read 3, iclass 12, count 2 2006.281.07:53:04.05#ibcon#about to read 4, iclass 12, count 2 2006.281.07:53:04.05#ibcon#read 4, iclass 12, count 2 2006.281.07:53:04.05#ibcon#about to read 5, iclass 12, count 2 2006.281.07:53:04.05#ibcon#read 5, iclass 12, count 2 2006.281.07:53:04.05#ibcon#about to read 6, iclass 12, count 2 2006.281.07:53:04.05#ibcon#read 6, iclass 12, count 2 2006.281.07:53:04.05#ibcon#end of sib2, iclass 12, count 2 2006.281.07:53:04.05#ibcon#*after write, iclass 12, count 2 2006.281.07:53:04.05#ibcon#*before return 0, iclass 12, count 2 2006.281.07:53:04.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:04.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.07:53:04.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.07:53:04.05#ibcon#ireg 7 cls_cnt 0 2006.281.07:53:04.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:04.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:04.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:04.17#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:53:04.17#ibcon#first serial, iclass 12, count 0 2006.281.07:53:04.17#ibcon#enter sib2, iclass 12, count 0 2006.281.07:53:04.17#ibcon#flushed, iclass 12, count 0 2006.281.07:53:04.17#ibcon#about to write, iclass 12, count 0 2006.281.07:53:04.17#ibcon#wrote, iclass 12, count 0 2006.281.07:53:04.17#ibcon#about to read 3, iclass 12, count 0 2006.281.07:53:04.19#ibcon#read 3, iclass 12, count 0 2006.281.07:53:04.19#ibcon#about to read 4, iclass 12, count 0 2006.281.07:53:04.19#ibcon#read 4, iclass 12, count 0 2006.281.07:53:04.19#ibcon#about to read 5, iclass 12, count 0 2006.281.07:53:04.19#ibcon#read 5, iclass 12, count 0 2006.281.07:53:04.19#ibcon#about to read 6, iclass 12, count 0 2006.281.07:53:04.19#ibcon#read 6, iclass 12, count 0 2006.281.07:53:04.19#ibcon#end of sib2, iclass 12, count 0 2006.281.07:53:04.19#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:53:04.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:53:04.19#ibcon#[27=USB\r\n] 2006.281.07:53:04.19#ibcon#*before write, iclass 12, count 0 2006.281.07:53:04.19#ibcon#enter sib2, iclass 12, count 0 2006.281.07:53:04.19#ibcon#flushed, iclass 12, count 0 2006.281.07:53:04.19#ibcon#about to write, iclass 12, count 0 2006.281.07:53:04.19#ibcon#wrote, iclass 12, count 0 2006.281.07:53:04.19#ibcon#about to read 3, iclass 12, count 0 2006.281.07:53:04.22#ibcon#read 3, iclass 12, count 0 2006.281.07:53:04.22#ibcon#about to read 4, iclass 12, count 0 2006.281.07:53:04.22#ibcon#read 4, iclass 12, count 0 2006.281.07:53:04.22#ibcon#about to read 5, iclass 12, count 0 2006.281.07:53:04.22#ibcon#read 5, iclass 12, count 0 2006.281.07:53:04.22#ibcon#about to read 6, iclass 12, count 0 2006.281.07:53:04.22#ibcon#read 6, iclass 12, count 0 2006.281.07:53:04.22#ibcon#end of sib2, iclass 12, count 0 2006.281.07:53:04.22#ibcon#*after write, iclass 12, count 0 2006.281.07:53:04.22#ibcon#*before return 0, iclass 12, count 0 2006.281.07:53:04.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:04.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.07:53:04.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:53:04.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:53:04.22$vc4f8/vabw=wide 2006.281.07:53:04.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:53:04.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:53:04.22#ibcon#ireg 8 cls_cnt 0 2006.281.07:53:04.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:04.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:04.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:04.22#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:53:04.22#ibcon#first serial, iclass 14, count 0 2006.281.07:53:04.22#ibcon#enter sib2, iclass 14, count 0 2006.281.07:53:04.22#ibcon#flushed, iclass 14, count 0 2006.281.07:53:04.22#ibcon#about to write, iclass 14, count 0 2006.281.07:53:04.22#ibcon#wrote, iclass 14, count 0 2006.281.07:53:04.22#ibcon#about to read 3, iclass 14, count 0 2006.281.07:53:04.24#ibcon#read 3, iclass 14, count 0 2006.281.07:53:04.24#ibcon#about to read 4, iclass 14, count 0 2006.281.07:53:04.24#ibcon#read 4, iclass 14, count 0 2006.281.07:53:04.24#ibcon#about to read 5, iclass 14, count 0 2006.281.07:53:04.24#ibcon#read 5, iclass 14, count 0 2006.281.07:53:04.24#ibcon#about to read 6, iclass 14, count 0 2006.281.07:53:04.24#ibcon#read 6, iclass 14, count 0 2006.281.07:53:04.24#ibcon#end of sib2, iclass 14, count 0 2006.281.07:53:04.24#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:53:04.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:53:04.26#ibcon#[25=BW32\r\n] 2006.281.07:53:04.26#ibcon#*before write, iclass 14, count 0 2006.281.07:53:04.26#ibcon#enter sib2, iclass 14, count 0 2006.281.07:53:04.26#ibcon#flushed, iclass 14, count 0 2006.281.07:53:04.26#ibcon#about to write, iclass 14, count 0 2006.281.07:53:04.26#ibcon#wrote, iclass 14, count 0 2006.281.07:53:04.26#ibcon#about to read 3, iclass 14, count 0 2006.281.07:53:04.29#ibcon#read 3, iclass 14, count 0 2006.281.07:53:04.29#ibcon#about to read 4, iclass 14, count 0 2006.281.07:53:04.29#ibcon#read 4, iclass 14, count 0 2006.281.07:53:04.29#ibcon#about to read 5, iclass 14, count 0 2006.281.07:53:04.29#ibcon#read 5, iclass 14, count 0 2006.281.07:53:04.29#ibcon#about to read 6, iclass 14, count 0 2006.281.07:53:04.29#ibcon#read 6, iclass 14, count 0 2006.281.07:53:04.29#ibcon#end of sib2, iclass 14, count 0 2006.281.07:53:04.29#ibcon#*after write, iclass 14, count 0 2006.281.07:53:04.29#ibcon#*before return 0, iclass 14, count 0 2006.281.07:53:04.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:04.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:53:04.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:53:04.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:53:04.29$vc4f8/vbbw=wide 2006.281.07:53:04.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.07:53:04.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.07:53:04.29#ibcon#ireg 8 cls_cnt 0 2006.281.07:53:04.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:53:04.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:53:04.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:53:04.34#ibcon#enter wrdev, iclass 16, count 0 2006.281.07:53:04.34#ibcon#first serial, iclass 16, count 0 2006.281.07:53:04.34#ibcon#enter sib2, iclass 16, count 0 2006.281.07:53:04.34#ibcon#flushed, iclass 16, count 0 2006.281.07:53:04.34#ibcon#about to write, iclass 16, count 0 2006.281.07:53:04.34#ibcon#wrote, iclass 16, count 0 2006.281.07:53:04.34#ibcon#about to read 3, iclass 16, count 0 2006.281.07:53:04.36#ibcon#read 3, iclass 16, count 0 2006.281.07:53:04.36#ibcon#about to read 4, iclass 16, count 0 2006.281.07:53:04.36#ibcon#read 4, iclass 16, count 0 2006.281.07:53:04.36#ibcon#about to read 5, iclass 16, count 0 2006.281.07:53:04.36#ibcon#read 5, iclass 16, count 0 2006.281.07:53:04.36#ibcon#about to read 6, iclass 16, count 0 2006.281.07:53:04.36#ibcon#read 6, iclass 16, count 0 2006.281.07:53:04.36#ibcon#end of sib2, iclass 16, count 0 2006.281.07:53:04.36#ibcon#*mode == 0, iclass 16, count 0 2006.281.07:53:04.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.07:53:04.36#ibcon#[27=BW32\r\n] 2006.281.07:53:04.36#ibcon#*before write, iclass 16, count 0 2006.281.07:53:04.36#ibcon#enter sib2, iclass 16, count 0 2006.281.07:53:04.36#ibcon#flushed, iclass 16, count 0 2006.281.07:53:04.36#ibcon#about to write, iclass 16, count 0 2006.281.07:53:04.36#ibcon#wrote, iclass 16, count 0 2006.281.07:53:04.36#ibcon#about to read 3, iclass 16, count 0 2006.281.07:53:04.39#ibcon#read 3, iclass 16, count 0 2006.281.07:53:04.39#ibcon#about to read 4, iclass 16, count 0 2006.281.07:53:04.39#ibcon#read 4, iclass 16, count 0 2006.281.07:53:04.39#ibcon#about to read 5, iclass 16, count 0 2006.281.07:53:04.39#ibcon#read 5, iclass 16, count 0 2006.281.07:53:04.39#ibcon#about to read 6, iclass 16, count 0 2006.281.07:53:04.39#ibcon#read 6, iclass 16, count 0 2006.281.07:53:04.39#ibcon#end of sib2, iclass 16, count 0 2006.281.07:53:04.39#ibcon#*after write, iclass 16, count 0 2006.281.07:53:04.39#ibcon#*before return 0, iclass 16, count 0 2006.281.07:53:04.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:53:04.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.07:53:04.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.07:53:04.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.07:53:04.39$4f8m12a/ifd4f 2006.281.07:53:04.39$ifd4f/lo= 2006.281.07:53:04.39$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:53:04.39$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:53:04.39$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:53:04.39$ifd4f/patch= 2006.281.07:53:04.39$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:53:04.39$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:53:04.39$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:53:04.39$4f8m12a/"form=m,16.000,1:2 2006.281.07:53:04.39$4f8m12a/"tpicd 2006.281.07:53:04.39$4f8m12a/echo=off 2006.281.07:53:04.39$4f8m12a/xlog=off 2006.281.07:53:04.39:!2006.281.07:54:40 2006.281.07:53:35.14#trakl#Source acquired 2006.281.07:53:36.14#flagr#flagr/antenna,acquired 2006.281.07:54:40.00:preob 2006.281.07:54:40.14/onsource/TRACKING 2006.281.07:54:40.14:!2006.281.07:54:50 2006.281.07:54:50.00:data_valid=on 2006.281.07:54:50.00:midob 2006.281.07:54:51.14/onsource/TRACKING 2006.281.07:54:51.14/wx/20.73,1001.4,51 2006.281.07:54:51.35/cable/+6.4853E-03 2006.281.07:54:52.44/va/01,07,usb,yes,33,35 2006.281.07:54:52.44/va/02,06,usb,yes,31,32 2006.281.07:54:52.44/va/03,06,usb,yes,29,29 2006.281.07:54:52.44/va/04,06,usb,yes,32,34 2006.281.07:54:52.44/va/05,07,usb,yes,30,32 2006.281.07:54:52.44/va/06,06,usb,yes,29,29 2006.281.07:54:52.44/va/07,06,usb,yes,30,30 2006.281.07:54:52.44/va/08,06,usb,yes,32,31 2006.281.07:54:52.67/valo/01,532.99,yes,locked 2006.281.07:54:52.67/valo/02,572.99,yes,locked 2006.281.07:54:52.67/valo/03,672.99,yes,locked 2006.281.07:54:52.67/valo/04,832.99,yes,locked 2006.281.07:54:52.67/valo/05,652.99,yes,locked 2006.281.07:54:52.67/valo/06,772.99,yes,locked 2006.281.07:54:52.67/valo/07,832.99,yes,locked 2006.281.07:54:52.67/valo/08,852.99,yes,locked 2006.281.07:54:53.76/vb/01,04,usb,yes,31,29 2006.281.07:54:53.76/vb/02,05,usb,yes,29,30 2006.281.07:54:53.76/vb/03,04,usb,yes,29,33 2006.281.07:54:53.76/vb/04,04,usb,yes,30,30 2006.281.07:54:53.76/vb/05,04,usb,yes,28,32 2006.281.07:54:53.76/vb/06,04,usb,yes,28,32 2006.281.07:54:53.76/vb/07,04,usb,yes,31,31 2006.281.07:54:53.76/vb/08,04,usb,yes,28,32 2006.281.07:54:53.99/vblo/01,632.99,yes,locked 2006.281.07:54:53.99/vblo/02,640.99,yes,locked 2006.281.07:54:53.99/vblo/03,656.99,yes,locked 2006.281.07:54:53.99/vblo/04,712.99,yes,locked 2006.281.07:54:53.99/vblo/05,744.99,yes,locked 2006.281.07:54:53.99/vblo/06,752.99,yes,locked 2006.281.07:54:53.99/vblo/07,734.99,yes,locked 2006.281.07:54:53.99/vblo/08,744.99,yes,locked 2006.281.07:54:54.14/vabw/8 2006.281.07:54:54.29/vbbw/8 2006.281.07:54:54.38/xfe/off,on,12.2 2006.281.07:54:54.78/ifatt/23,28,28,28 2006.281.07:54:55.07/fmout-gps/S +3.04E-07 2006.281.07:54:55.09:!2006.281.07:55:50 2006.281.07:55:50.01:data_valid=off 2006.281.07:55:50.01:postob 2006.281.07:55:50.19/cable/+6.4853E-03 2006.281.07:55:50.19/wx/20.69,1001.4,52 2006.281.07:55:51.08/fmout-gps/S +3.03E-07 2006.281.07:55:51.08:scan_name=281-0758,k06281,60 2006.281.07:55:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.281.07:55:51.14#flagr#flagr/antenna,new-source 2006.281.07:55:52.14:checkk5 2006.281.07:55:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:55:53.21/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:55:53.65/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:55:54.05/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:55:54.48/chk_obsdata//k5ts1/T2810754??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:55:54.86/chk_obsdata//k5ts2/T2810754??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:55:55.31/chk_obsdata//k5ts3/T2810754??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:55:55.72/chk_obsdata//k5ts4/T2810754??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:55:56.73/k5log//k5ts1_log_newline 2006.281.07:55:57.50/k5log//k5ts2_log_newline 2006.281.07:55:58.38/k5log//k5ts3_log_newline 2006.281.07:55:59.94/k5log//k5ts4_log_newline 2006.281.07:55:59.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:55:59.96:4f8m12a=2 2006.281.07:55:59.96$4f8m12a/echo=on 2006.281.07:55:59.96$4f8m12a/pcalon 2006.281.07:55:59.96$pcalon/"no phase cal control is implemented here 2006.281.07:55:59.96$4f8m12a/"tpicd=stop 2006.281.07:55:59.96$4f8m12a/vc4f8 2006.281.07:55:59.96$vc4f8/valo=1,532.99 2006.281.07:55:59.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:55:59.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:55:59.96#ibcon#ireg 17 cls_cnt 0 2006.281.07:55:59.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:55:59.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:55:59.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:55:59.96#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:55:59.96#ibcon#first serial, iclass 19, count 0 2006.281.07:55:59.96#ibcon#enter sib2, iclass 19, count 0 2006.281.07:55:59.96#ibcon#flushed, iclass 19, count 0 2006.281.07:55:59.96#ibcon#about to write, iclass 19, count 0 2006.281.07:55:59.96#ibcon#wrote, iclass 19, count 0 2006.281.07:55:59.96#ibcon#about to read 3, iclass 19, count 0 2006.281.07:55:59.98#ibcon#read 3, iclass 19, count 0 2006.281.07:55:59.98#ibcon#about to read 4, iclass 19, count 0 2006.281.07:55:59.98#ibcon#read 4, iclass 19, count 0 2006.281.07:55:59.98#ibcon#about to read 5, iclass 19, count 0 2006.281.07:55:59.98#ibcon#read 5, iclass 19, count 0 2006.281.07:55:59.98#ibcon#about to read 6, iclass 19, count 0 2006.281.07:55:59.98#ibcon#read 6, iclass 19, count 0 2006.281.07:55:59.98#ibcon#end of sib2, iclass 19, count 0 2006.281.07:55:59.98#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:55:59.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:55:59.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:55:59.98#ibcon#*before write, iclass 19, count 0 2006.281.07:55:59.98#ibcon#enter sib2, iclass 19, count 0 2006.281.07:55:59.98#ibcon#flushed, iclass 19, count 0 2006.281.07:55:59.98#ibcon#about to write, iclass 19, count 0 2006.281.07:55:59.98#ibcon#wrote, iclass 19, count 0 2006.281.07:55:59.98#ibcon#about to read 3, iclass 19, count 0 2006.281.07:56:00.03#ibcon#read 3, iclass 19, count 0 2006.281.07:56:00.03#ibcon#about to read 4, iclass 19, count 0 2006.281.07:56:00.03#ibcon#read 4, iclass 19, count 0 2006.281.07:56:00.03#ibcon#about to read 5, iclass 19, count 0 2006.281.07:56:00.03#ibcon#read 5, iclass 19, count 0 2006.281.07:56:00.03#ibcon#about to read 6, iclass 19, count 0 2006.281.07:56:00.03#ibcon#read 6, iclass 19, count 0 2006.281.07:56:00.03#ibcon#end of sib2, iclass 19, count 0 2006.281.07:56:00.03#ibcon#*after write, iclass 19, count 0 2006.281.07:56:00.03#ibcon#*before return 0, iclass 19, count 0 2006.281.07:56:00.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:00.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:00.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:56:00.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:56:00.03$vc4f8/va=1,7 2006.281.07:56:00.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:56:00.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:56:00.03#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:00.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:00.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:00.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:00.03#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:56:00.03#ibcon#first serial, iclass 21, count 2 2006.281.07:56:00.03#ibcon#enter sib2, iclass 21, count 2 2006.281.07:56:00.03#ibcon#flushed, iclass 21, count 2 2006.281.07:56:00.03#ibcon#about to write, iclass 21, count 2 2006.281.07:56:00.03#ibcon#wrote, iclass 21, count 2 2006.281.07:56:00.03#ibcon#about to read 3, iclass 21, count 2 2006.281.07:56:00.05#ibcon#read 3, iclass 21, count 2 2006.281.07:56:00.05#ibcon#about to read 4, iclass 21, count 2 2006.281.07:56:00.05#ibcon#read 4, iclass 21, count 2 2006.281.07:56:00.05#ibcon#about to read 5, iclass 21, count 2 2006.281.07:56:00.05#ibcon#read 5, iclass 21, count 2 2006.281.07:56:00.05#ibcon#about to read 6, iclass 21, count 2 2006.281.07:56:00.05#ibcon#read 6, iclass 21, count 2 2006.281.07:56:00.05#ibcon#end of sib2, iclass 21, count 2 2006.281.07:56:00.05#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:56:00.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:56:00.05#ibcon#[25=AT01-07\r\n] 2006.281.07:56:00.05#ibcon#*before write, iclass 21, count 2 2006.281.07:56:00.05#ibcon#enter sib2, iclass 21, count 2 2006.281.07:56:00.05#ibcon#flushed, iclass 21, count 2 2006.281.07:56:00.05#ibcon#about to write, iclass 21, count 2 2006.281.07:56:00.05#ibcon#wrote, iclass 21, count 2 2006.281.07:56:00.05#ibcon#about to read 3, iclass 21, count 2 2006.281.07:56:00.08#ibcon#read 3, iclass 21, count 2 2006.281.07:56:00.08#ibcon#about to read 4, iclass 21, count 2 2006.281.07:56:00.08#ibcon#read 4, iclass 21, count 2 2006.281.07:56:00.08#ibcon#about to read 5, iclass 21, count 2 2006.281.07:56:00.08#ibcon#read 5, iclass 21, count 2 2006.281.07:56:00.08#ibcon#about to read 6, iclass 21, count 2 2006.281.07:56:00.08#ibcon#read 6, iclass 21, count 2 2006.281.07:56:00.08#ibcon#end of sib2, iclass 21, count 2 2006.281.07:56:00.08#ibcon#*after write, iclass 21, count 2 2006.281.07:56:00.08#ibcon#*before return 0, iclass 21, count 2 2006.281.07:56:00.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:00.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:00.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:56:00.08#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:00.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:00.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:00.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:00.20#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:56:00.20#ibcon#first serial, iclass 21, count 0 2006.281.07:56:00.20#ibcon#enter sib2, iclass 21, count 0 2006.281.07:56:00.20#ibcon#flushed, iclass 21, count 0 2006.281.07:56:00.20#ibcon#about to write, iclass 21, count 0 2006.281.07:56:00.20#ibcon#wrote, iclass 21, count 0 2006.281.07:56:00.20#ibcon#about to read 3, iclass 21, count 0 2006.281.07:56:00.22#ibcon#read 3, iclass 21, count 0 2006.281.07:56:00.22#ibcon#about to read 4, iclass 21, count 0 2006.281.07:56:00.22#ibcon#read 4, iclass 21, count 0 2006.281.07:56:00.22#ibcon#about to read 5, iclass 21, count 0 2006.281.07:56:00.22#ibcon#read 5, iclass 21, count 0 2006.281.07:56:00.22#ibcon#about to read 6, iclass 21, count 0 2006.281.07:56:00.22#ibcon#read 6, iclass 21, count 0 2006.281.07:56:00.22#ibcon#end of sib2, iclass 21, count 0 2006.281.07:56:00.22#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:56:00.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:56:00.22#ibcon#[25=USB\r\n] 2006.281.07:56:00.22#ibcon#*before write, iclass 21, count 0 2006.281.07:56:00.22#ibcon#enter sib2, iclass 21, count 0 2006.281.07:56:00.22#ibcon#flushed, iclass 21, count 0 2006.281.07:56:00.22#ibcon#about to write, iclass 21, count 0 2006.281.07:56:00.22#ibcon#wrote, iclass 21, count 0 2006.281.07:56:00.22#ibcon#about to read 3, iclass 21, count 0 2006.281.07:56:00.25#ibcon#read 3, iclass 21, count 0 2006.281.07:56:00.25#ibcon#about to read 4, iclass 21, count 0 2006.281.07:56:00.25#ibcon#read 4, iclass 21, count 0 2006.281.07:56:00.25#ibcon#about to read 5, iclass 21, count 0 2006.281.07:56:00.25#ibcon#read 5, iclass 21, count 0 2006.281.07:56:00.25#ibcon#about to read 6, iclass 21, count 0 2006.281.07:56:00.25#ibcon#read 6, iclass 21, count 0 2006.281.07:56:00.25#ibcon#end of sib2, iclass 21, count 0 2006.281.07:56:00.25#ibcon#*after write, iclass 21, count 0 2006.281.07:56:00.25#ibcon#*before return 0, iclass 21, count 0 2006.281.07:56:00.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:00.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:00.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:56:00.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:56:00.25$vc4f8/valo=2,572.99 2006.281.07:56:00.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:56:00.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:56:00.25#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:00.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:00.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:00.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:00.25#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:56:00.25#ibcon#first serial, iclass 23, count 0 2006.281.07:56:00.25#ibcon#enter sib2, iclass 23, count 0 2006.281.07:56:00.25#ibcon#flushed, iclass 23, count 0 2006.281.07:56:00.25#ibcon#about to write, iclass 23, count 0 2006.281.07:56:00.25#ibcon#wrote, iclass 23, count 0 2006.281.07:56:00.25#ibcon#about to read 3, iclass 23, count 0 2006.281.07:56:00.27#ibcon#read 3, iclass 23, count 0 2006.281.07:56:00.27#ibcon#about to read 4, iclass 23, count 0 2006.281.07:56:00.27#ibcon#read 4, iclass 23, count 0 2006.281.07:56:00.27#ibcon#about to read 5, iclass 23, count 0 2006.281.07:56:00.27#ibcon#read 5, iclass 23, count 0 2006.281.07:56:00.27#ibcon#about to read 6, iclass 23, count 0 2006.281.07:56:00.27#ibcon#read 6, iclass 23, count 0 2006.281.07:56:00.27#ibcon#end of sib2, iclass 23, count 0 2006.281.07:56:00.27#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:56:00.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:56:00.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:56:00.27#ibcon#*before write, iclass 23, count 0 2006.281.07:56:00.27#ibcon#enter sib2, iclass 23, count 0 2006.281.07:56:00.27#ibcon#flushed, iclass 23, count 0 2006.281.07:56:00.27#ibcon#about to write, iclass 23, count 0 2006.281.07:56:00.27#ibcon#wrote, iclass 23, count 0 2006.281.07:56:00.27#ibcon#about to read 3, iclass 23, count 0 2006.281.07:56:00.31#ibcon#read 3, iclass 23, count 0 2006.281.07:56:00.31#ibcon#about to read 4, iclass 23, count 0 2006.281.07:56:00.31#ibcon#read 4, iclass 23, count 0 2006.281.07:56:00.31#ibcon#about to read 5, iclass 23, count 0 2006.281.07:56:00.31#ibcon#read 5, iclass 23, count 0 2006.281.07:56:00.31#ibcon#about to read 6, iclass 23, count 0 2006.281.07:56:00.31#ibcon#read 6, iclass 23, count 0 2006.281.07:56:00.31#ibcon#end of sib2, iclass 23, count 0 2006.281.07:56:00.31#ibcon#*after write, iclass 23, count 0 2006.281.07:56:00.31#ibcon#*before return 0, iclass 23, count 0 2006.281.07:56:00.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:00.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:00.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:56:00.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:56:00.31$vc4f8/va=2,6 2006.281.07:56:00.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:56:00.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:56:00.31#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:00.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:00.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:00.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:00.37#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:56:00.37#ibcon#first serial, iclass 25, count 2 2006.281.07:56:00.37#ibcon#enter sib2, iclass 25, count 2 2006.281.07:56:00.37#ibcon#flushed, iclass 25, count 2 2006.281.07:56:00.37#ibcon#about to write, iclass 25, count 2 2006.281.07:56:00.37#ibcon#wrote, iclass 25, count 2 2006.281.07:56:00.37#ibcon#about to read 3, iclass 25, count 2 2006.281.07:56:00.39#ibcon#read 3, iclass 25, count 2 2006.281.07:56:00.39#ibcon#about to read 4, iclass 25, count 2 2006.281.07:56:00.39#ibcon#read 4, iclass 25, count 2 2006.281.07:56:00.39#ibcon#about to read 5, iclass 25, count 2 2006.281.07:56:00.39#ibcon#read 5, iclass 25, count 2 2006.281.07:56:00.39#ibcon#about to read 6, iclass 25, count 2 2006.281.07:56:00.39#ibcon#read 6, iclass 25, count 2 2006.281.07:56:00.39#ibcon#end of sib2, iclass 25, count 2 2006.281.07:56:00.39#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:56:00.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:56:00.39#ibcon#[25=AT02-06\r\n] 2006.281.07:56:00.39#ibcon#*before write, iclass 25, count 2 2006.281.07:56:00.39#ibcon#enter sib2, iclass 25, count 2 2006.281.07:56:00.39#ibcon#flushed, iclass 25, count 2 2006.281.07:56:00.39#ibcon#about to write, iclass 25, count 2 2006.281.07:56:00.39#ibcon#wrote, iclass 25, count 2 2006.281.07:56:00.39#ibcon#about to read 3, iclass 25, count 2 2006.281.07:56:00.42#ibcon#read 3, iclass 25, count 2 2006.281.07:56:00.42#ibcon#about to read 4, iclass 25, count 2 2006.281.07:56:00.42#ibcon#read 4, iclass 25, count 2 2006.281.07:56:00.42#ibcon#about to read 5, iclass 25, count 2 2006.281.07:56:00.42#ibcon#read 5, iclass 25, count 2 2006.281.07:56:00.42#ibcon#about to read 6, iclass 25, count 2 2006.281.07:56:00.42#ibcon#read 6, iclass 25, count 2 2006.281.07:56:00.42#ibcon#end of sib2, iclass 25, count 2 2006.281.07:56:00.42#ibcon#*after write, iclass 25, count 2 2006.281.07:56:00.42#ibcon#*before return 0, iclass 25, count 2 2006.281.07:56:00.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:00.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:00.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:56:00.42#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:00.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:00.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:00.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:00.54#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:56:00.54#ibcon#first serial, iclass 25, count 0 2006.281.07:56:00.54#ibcon#enter sib2, iclass 25, count 0 2006.281.07:56:00.54#ibcon#flushed, iclass 25, count 0 2006.281.07:56:00.54#ibcon#about to write, iclass 25, count 0 2006.281.07:56:00.54#ibcon#wrote, iclass 25, count 0 2006.281.07:56:00.54#ibcon#about to read 3, iclass 25, count 0 2006.281.07:56:00.56#ibcon#read 3, iclass 25, count 0 2006.281.07:56:00.56#ibcon#about to read 4, iclass 25, count 0 2006.281.07:56:00.56#ibcon#read 4, iclass 25, count 0 2006.281.07:56:00.56#ibcon#about to read 5, iclass 25, count 0 2006.281.07:56:00.56#ibcon#read 5, iclass 25, count 0 2006.281.07:56:00.56#ibcon#about to read 6, iclass 25, count 0 2006.281.07:56:00.56#ibcon#read 6, iclass 25, count 0 2006.281.07:56:00.56#ibcon#end of sib2, iclass 25, count 0 2006.281.07:56:00.56#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:56:00.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:56:00.56#ibcon#[25=USB\r\n] 2006.281.07:56:00.56#ibcon#*before write, iclass 25, count 0 2006.281.07:56:00.56#ibcon#enter sib2, iclass 25, count 0 2006.281.07:56:00.56#ibcon#flushed, iclass 25, count 0 2006.281.07:56:00.56#ibcon#about to write, iclass 25, count 0 2006.281.07:56:00.56#ibcon#wrote, iclass 25, count 0 2006.281.07:56:00.56#ibcon#about to read 3, iclass 25, count 0 2006.281.07:56:00.59#ibcon#read 3, iclass 25, count 0 2006.281.07:56:00.59#ibcon#about to read 4, iclass 25, count 0 2006.281.07:56:00.59#ibcon#read 4, iclass 25, count 0 2006.281.07:56:00.59#ibcon#about to read 5, iclass 25, count 0 2006.281.07:56:00.59#ibcon#read 5, iclass 25, count 0 2006.281.07:56:00.59#ibcon#about to read 6, iclass 25, count 0 2006.281.07:56:00.59#ibcon#read 6, iclass 25, count 0 2006.281.07:56:00.59#ibcon#end of sib2, iclass 25, count 0 2006.281.07:56:00.59#ibcon#*after write, iclass 25, count 0 2006.281.07:56:00.59#ibcon#*before return 0, iclass 25, count 0 2006.281.07:56:00.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:00.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:00.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:56:00.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:56:00.59$vc4f8/valo=3,672.99 2006.281.07:56:00.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:56:00.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:56:00.59#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:00.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:00.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:00.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:00.59#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:56:00.59#ibcon#first serial, iclass 27, count 0 2006.281.07:56:00.59#ibcon#enter sib2, iclass 27, count 0 2006.281.07:56:00.59#ibcon#flushed, iclass 27, count 0 2006.281.07:56:00.59#ibcon#about to write, iclass 27, count 0 2006.281.07:56:00.59#ibcon#wrote, iclass 27, count 0 2006.281.07:56:00.59#ibcon#about to read 3, iclass 27, count 0 2006.281.07:56:00.61#ibcon#read 3, iclass 27, count 0 2006.281.07:56:00.61#ibcon#about to read 4, iclass 27, count 0 2006.281.07:56:00.61#ibcon#read 4, iclass 27, count 0 2006.281.07:56:00.61#ibcon#about to read 5, iclass 27, count 0 2006.281.07:56:00.61#ibcon#read 5, iclass 27, count 0 2006.281.07:56:00.61#ibcon#about to read 6, iclass 27, count 0 2006.281.07:56:00.61#ibcon#read 6, iclass 27, count 0 2006.281.07:56:00.61#ibcon#end of sib2, iclass 27, count 0 2006.281.07:56:00.61#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:56:00.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:56:00.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:56:00.63#ibcon#*before write, iclass 27, count 0 2006.281.07:56:00.63#ibcon#enter sib2, iclass 27, count 0 2006.281.07:56:00.63#ibcon#flushed, iclass 27, count 0 2006.281.07:56:00.63#ibcon#about to write, iclass 27, count 0 2006.281.07:56:00.63#ibcon#wrote, iclass 27, count 0 2006.281.07:56:00.63#ibcon#about to read 3, iclass 27, count 0 2006.281.07:56:00.67#ibcon#read 3, iclass 27, count 0 2006.281.07:56:00.67#ibcon#about to read 4, iclass 27, count 0 2006.281.07:56:00.67#ibcon#read 4, iclass 27, count 0 2006.281.07:56:00.67#ibcon#about to read 5, iclass 27, count 0 2006.281.07:56:00.67#ibcon#read 5, iclass 27, count 0 2006.281.07:56:00.67#ibcon#about to read 6, iclass 27, count 0 2006.281.07:56:00.67#ibcon#read 6, iclass 27, count 0 2006.281.07:56:00.67#ibcon#end of sib2, iclass 27, count 0 2006.281.07:56:00.67#ibcon#*after write, iclass 27, count 0 2006.281.07:56:00.67#ibcon#*before return 0, iclass 27, count 0 2006.281.07:56:00.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:00.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:00.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:56:00.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:56:00.67$vc4f8/va=3,6 2006.281.07:56:00.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:56:00.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:56:00.67#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:00.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:00.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:00.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:00.71#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:56:00.71#ibcon#first serial, iclass 29, count 2 2006.281.07:56:00.71#ibcon#enter sib2, iclass 29, count 2 2006.281.07:56:00.71#ibcon#flushed, iclass 29, count 2 2006.281.07:56:00.71#ibcon#about to write, iclass 29, count 2 2006.281.07:56:00.71#ibcon#wrote, iclass 29, count 2 2006.281.07:56:00.71#ibcon#about to read 3, iclass 29, count 2 2006.281.07:56:00.73#ibcon#read 3, iclass 29, count 2 2006.281.07:56:00.73#ibcon#about to read 4, iclass 29, count 2 2006.281.07:56:00.73#ibcon#read 4, iclass 29, count 2 2006.281.07:56:00.73#ibcon#about to read 5, iclass 29, count 2 2006.281.07:56:00.73#ibcon#read 5, iclass 29, count 2 2006.281.07:56:00.73#ibcon#about to read 6, iclass 29, count 2 2006.281.07:56:00.73#ibcon#read 6, iclass 29, count 2 2006.281.07:56:00.73#ibcon#end of sib2, iclass 29, count 2 2006.281.07:56:00.73#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:56:00.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:56:00.73#ibcon#[25=AT03-06\r\n] 2006.281.07:56:00.73#ibcon#*before write, iclass 29, count 2 2006.281.07:56:00.73#ibcon#enter sib2, iclass 29, count 2 2006.281.07:56:00.73#ibcon#flushed, iclass 29, count 2 2006.281.07:56:00.73#ibcon#about to write, iclass 29, count 2 2006.281.07:56:00.73#ibcon#wrote, iclass 29, count 2 2006.281.07:56:00.73#ibcon#about to read 3, iclass 29, count 2 2006.281.07:56:00.76#ibcon#read 3, iclass 29, count 2 2006.281.07:56:00.76#ibcon#about to read 4, iclass 29, count 2 2006.281.07:56:00.76#ibcon#read 4, iclass 29, count 2 2006.281.07:56:00.76#ibcon#about to read 5, iclass 29, count 2 2006.281.07:56:00.76#ibcon#read 5, iclass 29, count 2 2006.281.07:56:00.76#ibcon#about to read 6, iclass 29, count 2 2006.281.07:56:00.76#ibcon#read 6, iclass 29, count 2 2006.281.07:56:00.76#ibcon#end of sib2, iclass 29, count 2 2006.281.07:56:00.76#ibcon#*after write, iclass 29, count 2 2006.281.07:56:00.76#ibcon#*before return 0, iclass 29, count 2 2006.281.07:56:00.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:00.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:00.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:56:00.76#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:00.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:00.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:00.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:00.88#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:56:00.88#ibcon#first serial, iclass 29, count 0 2006.281.07:56:00.88#ibcon#enter sib2, iclass 29, count 0 2006.281.07:56:00.88#ibcon#flushed, iclass 29, count 0 2006.281.07:56:00.88#ibcon#about to write, iclass 29, count 0 2006.281.07:56:00.88#ibcon#wrote, iclass 29, count 0 2006.281.07:56:00.88#ibcon#about to read 3, iclass 29, count 0 2006.281.07:56:00.90#ibcon#read 3, iclass 29, count 0 2006.281.07:56:00.90#ibcon#about to read 4, iclass 29, count 0 2006.281.07:56:00.90#ibcon#read 4, iclass 29, count 0 2006.281.07:56:00.90#ibcon#about to read 5, iclass 29, count 0 2006.281.07:56:00.90#ibcon#read 5, iclass 29, count 0 2006.281.07:56:00.90#ibcon#about to read 6, iclass 29, count 0 2006.281.07:56:00.90#ibcon#read 6, iclass 29, count 0 2006.281.07:56:00.90#ibcon#end of sib2, iclass 29, count 0 2006.281.07:56:00.90#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:56:00.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:56:00.90#ibcon#[25=USB\r\n] 2006.281.07:56:00.90#ibcon#*before write, iclass 29, count 0 2006.281.07:56:00.90#ibcon#enter sib2, iclass 29, count 0 2006.281.07:56:00.90#ibcon#flushed, iclass 29, count 0 2006.281.07:56:00.90#ibcon#about to write, iclass 29, count 0 2006.281.07:56:00.90#ibcon#wrote, iclass 29, count 0 2006.281.07:56:00.90#ibcon#about to read 3, iclass 29, count 0 2006.281.07:56:00.93#ibcon#read 3, iclass 29, count 0 2006.281.07:56:00.93#ibcon#about to read 4, iclass 29, count 0 2006.281.07:56:00.93#ibcon#read 4, iclass 29, count 0 2006.281.07:56:00.93#ibcon#about to read 5, iclass 29, count 0 2006.281.07:56:00.93#ibcon#read 5, iclass 29, count 0 2006.281.07:56:00.93#ibcon#about to read 6, iclass 29, count 0 2006.281.07:56:00.93#ibcon#read 6, iclass 29, count 0 2006.281.07:56:00.93#ibcon#end of sib2, iclass 29, count 0 2006.281.07:56:00.93#ibcon#*after write, iclass 29, count 0 2006.281.07:56:00.93#ibcon#*before return 0, iclass 29, count 0 2006.281.07:56:00.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:00.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:00.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:56:00.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:56:00.93$vc4f8/valo=4,832.99 2006.281.07:56:00.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:56:00.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:56:00.93#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:00.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:00.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:00.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:00.93#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:56:00.93#ibcon#first serial, iclass 31, count 0 2006.281.07:56:00.93#ibcon#enter sib2, iclass 31, count 0 2006.281.07:56:00.93#ibcon#flushed, iclass 31, count 0 2006.281.07:56:00.93#ibcon#about to write, iclass 31, count 0 2006.281.07:56:00.93#ibcon#wrote, iclass 31, count 0 2006.281.07:56:00.93#ibcon#about to read 3, iclass 31, count 0 2006.281.07:56:00.95#ibcon#read 3, iclass 31, count 0 2006.281.07:56:00.95#ibcon#about to read 4, iclass 31, count 0 2006.281.07:56:00.95#ibcon#read 4, iclass 31, count 0 2006.281.07:56:00.95#ibcon#about to read 5, iclass 31, count 0 2006.281.07:56:00.95#ibcon#read 5, iclass 31, count 0 2006.281.07:56:00.95#ibcon#about to read 6, iclass 31, count 0 2006.281.07:56:00.95#ibcon#read 6, iclass 31, count 0 2006.281.07:56:00.95#ibcon#end of sib2, iclass 31, count 0 2006.281.07:56:00.95#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:56:00.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:56:00.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:56:00.95#ibcon#*before write, iclass 31, count 0 2006.281.07:56:00.95#ibcon#enter sib2, iclass 31, count 0 2006.281.07:56:00.95#ibcon#flushed, iclass 31, count 0 2006.281.07:56:00.95#ibcon#about to write, iclass 31, count 0 2006.281.07:56:00.95#ibcon#wrote, iclass 31, count 0 2006.281.07:56:00.95#ibcon#about to read 3, iclass 31, count 0 2006.281.07:56:01.00#ibcon#read 3, iclass 31, count 0 2006.281.07:56:01.00#ibcon#about to read 4, iclass 31, count 0 2006.281.07:56:01.00#ibcon#read 4, iclass 31, count 0 2006.281.07:56:01.00#ibcon#about to read 5, iclass 31, count 0 2006.281.07:56:01.00#ibcon#read 5, iclass 31, count 0 2006.281.07:56:01.00#ibcon#about to read 6, iclass 31, count 0 2006.281.07:56:01.00#ibcon#read 6, iclass 31, count 0 2006.281.07:56:01.00#ibcon#end of sib2, iclass 31, count 0 2006.281.07:56:01.00#ibcon#*after write, iclass 31, count 0 2006.281.07:56:01.00#ibcon#*before return 0, iclass 31, count 0 2006.281.07:56:01.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:01.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:01.00#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:56:01.00#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:56:01.00$vc4f8/va=4,6 2006.281.07:56:01.00#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:56:01.00#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:56:01.00#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:01.00#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:01.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:01.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:01.04#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:56:01.04#ibcon#first serial, iclass 33, count 2 2006.281.07:56:01.04#ibcon#enter sib2, iclass 33, count 2 2006.281.07:56:01.04#ibcon#flushed, iclass 33, count 2 2006.281.07:56:01.04#ibcon#about to write, iclass 33, count 2 2006.281.07:56:01.04#ibcon#wrote, iclass 33, count 2 2006.281.07:56:01.04#ibcon#about to read 3, iclass 33, count 2 2006.281.07:56:01.06#ibcon#read 3, iclass 33, count 2 2006.281.07:56:01.06#ibcon#about to read 4, iclass 33, count 2 2006.281.07:56:01.06#ibcon#read 4, iclass 33, count 2 2006.281.07:56:01.06#ibcon#about to read 5, iclass 33, count 2 2006.281.07:56:01.06#ibcon#read 5, iclass 33, count 2 2006.281.07:56:01.06#ibcon#about to read 6, iclass 33, count 2 2006.281.07:56:01.06#ibcon#read 6, iclass 33, count 2 2006.281.07:56:01.06#ibcon#end of sib2, iclass 33, count 2 2006.281.07:56:01.06#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:56:01.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:56:01.06#ibcon#[25=AT04-06\r\n] 2006.281.07:56:01.06#ibcon#*before write, iclass 33, count 2 2006.281.07:56:01.06#ibcon#enter sib2, iclass 33, count 2 2006.281.07:56:01.06#ibcon#flushed, iclass 33, count 2 2006.281.07:56:01.06#ibcon#about to write, iclass 33, count 2 2006.281.07:56:01.06#ibcon#wrote, iclass 33, count 2 2006.281.07:56:01.06#ibcon#about to read 3, iclass 33, count 2 2006.281.07:56:01.10#ibcon#read 3, iclass 33, count 2 2006.281.07:56:01.10#ibcon#about to read 4, iclass 33, count 2 2006.281.07:56:01.10#ibcon#read 4, iclass 33, count 2 2006.281.07:56:01.10#ibcon#about to read 5, iclass 33, count 2 2006.281.07:56:01.10#ibcon#read 5, iclass 33, count 2 2006.281.07:56:01.10#ibcon#about to read 6, iclass 33, count 2 2006.281.07:56:01.10#ibcon#read 6, iclass 33, count 2 2006.281.07:56:01.10#ibcon#end of sib2, iclass 33, count 2 2006.281.07:56:01.10#ibcon#*after write, iclass 33, count 2 2006.281.07:56:01.10#ibcon#*before return 0, iclass 33, count 2 2006.281.07:56:01.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:01.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:01.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:56:01.10#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:01.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:01.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:01.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:01.21#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:56:01.21#ibcon#first serial, iclass 33, count 0 2006.281.07:56:01.21#ibcon#enter sib2, iclass 33, count 0 2006.281.07:56:01.21#ibcon#flushed, iclass 33, count 0 2006.281.07:56:01.21#ibcon#about to write, iclass 33, count 0 2006.281.07:56:01.21#ibcon#wrote, iclass 33, count 0 2006.281.07:56:01.21#ibcon#about to read 3, iclass 33, count 0 2006.281.07:56:01.23#ibcon#read 3, iclass 33, count 0 2006.281.07:56:01.23#ibcon#about to read 4, iclass 33, count 0 2006.281.07:56:01.23#ibcon#read 4, iclass 33, count 0 2006.281.07:56:01.23#ibcon#about to read 5, iclass 33, count 0 2006.281.07:56:01.23#ibcon#read 5, iclass 33, count 0 2006.281.07:56:01.23#ibcon#about to read 6, iclass 33, count 0 2006.281.07:56:01.23#ibcon#read 6, iclass 33, count 0 2006.281.07:56:01.23#ibcon#end of sib2, iclass 33, count 0 2006.281.07:56:01.23#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:56:01.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:56:01.23#ibcon#[25=USB\r\n] 2006.281.07:56:01.23#ibcon#*before write, iclass 33, count 0 2006.281.07:56:01.23#ibcon#enter sib2, iclass 33, count 0 2006.281.07:56:01.23#ibcon#flushed, iclass 33, count 0 2006.281.07:56:01.23#ibcon#about to write, iclass 33, count 0 2006.281.07:56:01.23#ibcon#wrote, iclass 33, count 0 2006.281.07:56:01.23#ibcon#about to read 3, iclass 33, count 0 2006.281.07:56:01.26#ibcon#read 3, iclass 33, count 0 2006.281.07:56:01.26#ibcon#about to read 4, iclass 33, count 0 2006.281.07:56:01.26#ibcon#read 4, iclass 33, count 0 2006.281.07:56:01.26#ibcon#about to read 5, iclass 33, count 0 2006.281.07:56:01.26#ibcon#read 5, iclass 33, count 0 2006.281.07:56:01.26#ibcon#about to read 6, iclass 33, count 0 2006.281.07:56:01.26#ibcon#read 6, iclass 33, count 0 2006.281.07:56:01.26#ibcon#end of sib2, iclass 33, count 0 2006.281.07:56:01.26#ibcon#*after write, iclass 33, count 0 2006.281.07:56:01.26#ibcon#*before return 0, iclass 33, count 0 2006.281.07:56:01.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:01.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:01.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:56:01.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:56:01.26$vc4f8/valo=5,652.99 2006.281.07:56:01.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:56:01.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:56:01.26#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:01.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:01.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:01.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:01.26#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:56:01.26#ibcon#first serial, iclass 35, count 0 2006.281.07:56:01.26#ibcon#enter sib2, iclass 35, count 0 2006.281.07:56:01.26#ibcon#flushed, iclass 35, count 0 2006.281.07:56:01.26#ibcon#about to write, iclass 35, count 0 2006.281.07:56:01.26#ibcon#wrote, iclass 35, count 0 2006.281.07:56:01.26#ibcon#about to read 3, iclass 35, count 0 2006.281.07:56:01.28#ibcon#read 3, iclass 35, count 0 2006.281.07:56:01.28#ibcon#about to read 4, iclass 35, count 0 2006.281.07:56:01.28#ibcon#read 4, iclass 35, count 0 2006.281.07:56:01.28#ibcon#about to read 5, iclass 35, count 0 2006.281.07:56:01.28#ibcon#read 5, iclass 35, count 0 2006.281.07:56:01.28#ibcon#about to read 6, iclass 35, count 0 2006.281.07:56:01.28#ibcon#read 6, iclass 35, count 0 2006.281.07:56:01.28#ibcon#end of sib2, iclass 35, count 0 2006.281.07:56:01.28#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:56:01.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:56:01.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:56:01.28#ibcon#*before write, iclass 35, count 0 2006.281.07:56:01.28#ibcon#enter sib2, iclass 35, count 0 2006.281.07:56:01.28#ibcon#flushed, iclass 35, count 0 2006.281.07:56:01.28#ibcon#about to write, iclass 35, count 0 2006.281.07:56:01.28#ibcon#wrote, iclass 35, count 0 2006.281.07:56:01.28#ibcon#about to read 3, iclass 35, count 0 2006.281.07:56:01.32#ibcon#read 3, iclass 35, count 0 2006.281.07:56:01.32#ibcon#about to read 4, iclass 35, count 0 2006.281.07:56:01.32#ibcon#read 4, iclass 35, count 0 2006.281.07:56:01.32#ibcon#about to read 5, iclass 35, count 0 2006.281.07:56:01.32#ibcon#read 5, iclass 35, count 0 2006.281.07:56:01.32#ibcon#about to read 6, iclass 35, count 0 2006.281.07:56:01.32#ibcon#read 6, iclass 35, count 0 2006.281.07:56:01.32#ibcon#end of sib2, iclass 35, count 0 2006.281.07:56:01.32#ibcon#*after write, iclass 35, count 0 2006.281.07:56:01.32#ibcon#*before return 0, iclass 35, count 0 2006.281.07:56:01.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:01.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:01.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:56:01.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:56:01.32$vc4f8/va=5,7 2006.281.07:56:01.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:56:01.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:56:01.32#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:01.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:01.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:01.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:01.38#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:56:01.38#ibcon#first serial, iclass 37, count 2 2006.281.07:56:01.38#ibcon#enter sib2, iclass 37, count 2 2006.281.07:56:01.38#ibcon#flushed, iclass 37, count 2 2006.281.07:56:01.38#ibcon#about to write, iclass 37, count 2 2006.281.07:56:01.38#ibcon#wrote, iclass 37, count 2 2006.281.07:56:01.38#ibcon#about to read 3, iclass 37, count 2 2006.281.07:56:01.40#ibcon#read 3, iclass 37, count 2 2006.281.07:56:01.40#ibcon#about to read 4, iclass 37, count 2 2006.281.07:56:01.40#ibcon#read 4, iclass 37, count 2 2006.281.07:56:01.40#ibcon#about to read 5, iclass 37, count 2 2006.281.07:56:01.40#ibcon#read 5, iclass 37, count 2 2006.281.07:56:01.40#ibcon#about to read 6, iclass 37, count 2 2006.281.07:56:01.40#ibcon#read 6, iclass 37, count 2 2006.281.07:56:01.40#ibcon#end of sib2, iclass 37, count 2 2006.281.07:56:01.40#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:56:01.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:56:01.40#ibcon#[25=AT05-07\r\n] 2006.281.07:56:01.40#ibcon#*before write, iclass 37, count 2 2006.281.07:56:01.40#ibcon#enter sib2, iclass 37, count 2 2006.281.07:56:01.40#ibcon#flushed, iclass 37, count 2 2006.281.07:56:01.40#ibcon#about to write, iclass 37, count 2 2006.281.07:56:01.40#ibcon#wrote, iclass 37, count 2 2006.281.07:56:01.40#ibcon#about to read 3, iclass 37, count 2 2006.281.07:56:01.43#ibcon#read 3, iclass 37, count 2 2006.281.07:56:01.43#ibcon#about to read 4, iclass 37, count 2 2006.281.07:56:01.43#ibcon#read 4, iclass 37, count 2 2006.281.07:56:01.43#ibcon#about to read 5, iclass 37, count 2 2006.281.07:56:01.43#ibcon#read 5, iclass 37, count 2 2006.281.07:56:01.43#ibcon#about to read 6, iclass 37, count 2 2006.281.07:56:01.43#ibcon#read 6, iclass 37, count 2 2006.281.07:56:01.43#ibcon#end of sib2, iclass 37, count 2 2006.281.07:56:01.43#ibcon#*after write, iclass 37, count 2 2006.281.07:56:01.43#ibcon#*before return 0, iclass 37, count 2 2006.281.07:56:01.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:01.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:01.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:56:01.43#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:01.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:01.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:01.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:01.55#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:56:01.55#ibcon#first serial, iclass 37, count 0 2006.281.07:56:01.55#ibcon#enter sib2, iclass 37, count 0 2006.281.07:56:01.55#ibcon#flushed, iclass 37, count 0 2006.281.07:56:01.55#ibcon#about to write, iclass 37, count 0 2006.281.07:56:01.55#ibcon#wrote, iclass 37, count 0 2006.281.07:56:01.55#ibcon#about to read 3, iclass 37, count 0 2006.281.07:56:01.57#ibcon#read 3, iclass 37, count 0 2006.281.07:56:01.57#ibcon#about to read 4, iclass 37, count 0 2006.281.07:56:01.57#ibcon#read 4, iclass 37, count 0 2006.281.07:56:01.57#ibcon#about to read 5, iclass 37, count 0 2006.281.07:56:01.57#ibcon#read 5, iclass 37, count 0 2006.281.07:56:01.57#ibcon#about to read 6, iclass 37, count 0 2006.281.07:56:01.57#ibcon#read 6, iclass 37, count 0 2006.281.07:56:01.57#ibcon#end of sib2, iclass 37, count 0 2006.281.07:56:01.57#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:56:01.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:56:01.57#ibcon#[25=USB\r\n] 2006.281.07:56:01.57#ibcon#*before write, iclass 37, count 0 2006.281.07:56:01.57#ibcon#enter sib2, iclass 37, count 0 2006.281.07:56:01.57#ibcon#flushed, iclass 37, count 0 2006.281.07:56:01.57#ibcon#about to write, iclass 37, count 0 2006.281.07:56:01.57#ibcon#wrote, iclass 37, count 0 2006.281.07:56:01.57#ibcon#about to read 3, iclass 37, count 0 2006.281.07:56:01.60#ibcon#read 3, iclass 37, count 0 2006.281.07:56:01.60#ibcon#about to read 4, iclass 37, count 0 2006.281.07:56:01.60#ibcon#read 4, iclass 37, count 0 2006.281.07:56:01.60#ibcon#about to read 5, iclass 37, count 0 2006.281.07:56:01.60#ibcon#read 5, iclass 37, count 0 2006.281.07:56:01.60#ibcon#about to read 6, iclass 37, count 0 2006.281.07:56:01.60#ibcon#read 6, iclass 37, count 0 2006.281.07:56:01.60#ibcon#end of sib2, iclass 37, count 0 2006.281.07:56:01.60#ibcon#*after write, iclass 37, count 0 2006.281.07:56:01.60#ibcon#*before return 0, iclass 37, count 0 2006.281.07:56:01.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:01.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:01.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:56:01.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:56:01.60$vc4f8/valo=6,772.99 2006.281.07:56:01.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:56:01.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:56:01.60#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:01.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:01.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:01.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:01.60#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:56:01.60#ibcon#first serial, iclass 39, count 0 2006.281.07:56:01.60#ibcon#enter sib2, iclass 39, count 0 2006.281.07:56:01.60#ibcon#flushed, iclass 39, count 0 2006.281.07:56:01.60#ibcon#about to write, iclass 39, count 0 2006.281.07:56:01.60#ibcon#wrote, iclass 39, count 0 2006.281.07:56:01.60#ibcon#about to read 3, iclass 39, count 0 2006.281.07:56:01.62#ibcon#read 3, iclass 39, count 0 2006.281.07:56:01.62#ibcon#about to read 4, iclass 39, count 0 2006.281.07:56:01.62#ibcon#read 4, iclass 39, count 0 2006.281.07:56:01.62#ibcon#about to read 5, iclass 39, count 0 2006.281.07:56:01.62#ibcon#read 5, iclass 39, count 0 2006.281.07:56:01.62#ibcon#about to read 6, iclass 39, count 0 2006.281.07:56:01.62#ibcon#read 6, iclass 39, count 0 2006.281.07:56:01.62#ibcon#end of sib2, iclass 39, count 0 2006.281.07:56:01.62#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:56:01.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:56:01.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:56:01.64#ibcon#*before write, iclass 39, count 0 2006.281.07:56:01.64#ibcon#enter sib2, iclass 39, count 0 2006.281.07:56:01.64#ibcon#flushed, iclass 39, count 0 2006.281.07:56:01.64#ibcon#about to write, iclass 39, count 0 2006.281.07:56:01.64#ibcon#wrote, iclass 39, count 0 2006.281.07:56:01.64#ibcon#about to read 3, iclass 39, count 0 2006.281.07:56:01.68#ibcon#read 3, iclass 39, count 0 2006.281.07:56:01.68#ibcon#about to read 4, iclass 39, count 0 2006.281.07:56:01.68#ibcon#read 4, iclass 39, count 0 2006.281.07:56:01.68#ibcon#about to read 5, iclass 39, count 0 2006.281.07:56:01.68#ibcon#read 5, iclass 39, count 0 2006.281.07:56:01.68#ibcon#about to read 6, iclass 39, count 0 2006.281.07:56:01.68#ibcon#read 6, iclass 39, count 0 2006.281.07:56:01.68#ibcon#end of sib2, iclass 39, count 0 2006.281.07:56:01.68#ibcon#*after write, iclass 39, count 0 2006.281.07:56:01.68#ibcon#*before return 0, iclass 39, count 0 2006.281.07:56:01.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:01.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:01.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:56:01.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:56:01.68$vc4f8/va=6,6 2006.281.07:56:01.68#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.07:56:01.68#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.07:56:01.68#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:01.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:01.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:01.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:01.72#ibcon#enter wrdev, iclass 3, count 2 2006.281.07:56:01.72#ibcon#first serial, iclass 3, count 2 2006.281.07:56:01.72#ibcon#enter sib2, iclass 3, count 2 2006.281.07:56:01.72#ibcon#flushed, iclass 3, count 2 2006.281.07:56:01.72#ibcon#about to write, iclass 3, count 2 2006.281.07:56:01.72#ibcon#wrote, iclass 3, count 2 2006.281.07:56:01.72#ibcon#about to read 3, iclass 3, count 2 2006.281.07:56:01.74#ibcon#read 3, iclass 3, count 2 2006.281.07:56:01.74#ibcon#about to read 4, iclass 3, count 2 2006.281.07:56:01.74#ibcon#read 4, iclass 3, count 2 2006.281.07:56:01.74#ibcon#about to read 5, iclass 3, count 2 2006.281.07:56:01.74#ibcon#read 5, iclass 3, count 2 2006.281.07:56:01.74#ibcon#about to read 6, iclass 3, count 2 2006.281.07:56:01.74#ibcon#read 6, iclass 3, count 2 2006.281.07:56:01.74#ibcon#end of sib2, iclass 3, count 2 2006.281.07:56:01.74#ibcon#*mode == 0, iclass 3, count 2 2006.281.07:56:01.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.07:56:01.74#ibcon#[25=AT06-06\r\n] 2006.281.07:56:01.74#ibcon#*before write, iclass 3, count 2 2006.281.07:56:01.74#ibcon#enter sib2, iclass 3, count 2 2006.281.07:56:01.74#ibcon#flushed, iclass 3, count 2 2006.281.07:56:01.74#ibcon#about to write, iclass 3, count 2 2006.281.07:56:01.74#ibcon#wrote, iclass 3, count 2 2006.281.07:56:01.74#ibcon#about to read 3, iclass 3, count 2 2006.281.07:56:01.77#ibcon#read 3, iclass 3, count 2 2006.281.07:56:01.77#ibcon#about to read 4, iclass 3, count 2 2006.281.07:56:01.77#ibcon#read 4, iclass 3, count 2 2006.281.07:56:01.77#ibcon#about to read 5, iclass 3, count 2 2006.281.07:56:01.77#ibcon#read 5, iclass 3, count 2 2006.281.07:56:01.77#ibcon#about to read 6, iclass 3, count 2 2006.281.07:56:01.77#ibcon#read 6, iclass 3, count 2 2006.281.07:56:01.77#ibcon#end of sib2, iclass 3, count 2 2006.281.07:56:01.77#ibcon#*after write, iclass 3, count 2 2006.281.07:56:01.77#ibcon#*before return 0, iclass 3, count 2 2006.281.07:56:01.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:01.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:01.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.07:56:01.77#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:01.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:56:01.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:56:01.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:56:01.89#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:56:01.89#ibcon#first serial, iclass 3, count 0 2006.281.07:56:01.89#ibcon#enter sib2, iclass 3, count 0 2006.281.07:56:01.89#ibcon#flushed, iclass 3, count 0 2006.281.07:56:01.89#ibcon#about to write, iclass 3, count 0 2006.281.07:56:01.89#ibcon#wrote, iclass 3, count 0 2006.281.07:56:01.89#ibcon#about to read 3, iclass 3, count 0 2006.281.07:56:01.91#ibcon#read 3, iclass 3, count 0 2006.281.07:56:01.91#ibcon#about to read 4, iclass 3, count 0 2006.281.07:56:01.91#ibcon#read 4, iclass 3, count 0 2006.281.07:56:01.91#ibcon#about to read 5, iclass 3, count 0 2006.281.07:56:01.91#ibcon#read 5, iclass 3, count 0 2006.281.07:56:01.91#ibcon#about to read 6, iclass 3, count 0 2006.281.07:56:01.91#ibcon#read 6, iclass 3, count 0 2006.281.07:56:01.91#ibcon#end of sib2, iclass 3, count 0 2006.281.07:56:01.91#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:56:01.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:56:01.91#ibcon#[25=USB\r\n] 2006.281.07:56:01.91#ibcon#*before write, iclass 3, count 0 2006.281.07:56:01.91#ibcon#enter sib2, iclass 3, count 0 2006.281.07:56:01.91#ibcon#flushed, iclass 3, count 0 2006.281.07:56:01.91#ibcon#about to write, iclass 3, count 0 2006.281.07:56:01.91#ibcon#wrote, iclass 3, count 0 2006.281.07:56:01.91#ibcon#about to read 3, iclass 3, count 0 2006.281.07:56:01.94#ibcon#read 3, iclass 3, count 0 2006.281.07:56:01.94#ibcon#about to read 4, iclass 3, count 0 2006.281.07:56:01.94#ibcon#read 4, iclass 3, count 0 2006.281.07:56:01.94#ibcon#about to read 5, iclass 3, count 0 2006.281.07:56:01.94#ibcon#read 5, iclass 3, count 0 2006.281.07:56:01.94#ibcon#about to read 6, iclass 3, count 0 2006.281.07:56:01.94#ibcon#read 6, iclass 3, count 0 2006.281.07:56:01.94#ibcon#end of sib2, iclass 3, count 0 2006.281.07:56:01.94#ibcon#*after write, iclass 3, count 0 2006.281.07:56:01.94#ibcon#*before return 0, iclass 3, count 0 2006.281.07:56:01.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:56:01.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.07:56:01.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:56:01.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:56:01.94$vc4f8/valo=7,832.99 2006.281.07:56:01.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.07:56:01.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.07:56:01.94#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:01.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:56:01.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:56:01.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:56:01.94#ibcon#enter wrdev, iclass 5, count 0 2006.281.07:56:01.94#ibcon#first serial, iclass 5, count 0 2006.281.07:56:01.94#ibcon#enter sib2, iclass 5, count 0 2006.281.07:56:01.94#ibcon#flushed, iclass 5, count 0 2006.281.07:56:01.94#ibcon#about to write, iclass 5, count 0 2006.281.07:56:01.94#ibcon#wrote, iclass 5, count 0 2006.281.07:56:01.94#ibcon#about to read 3, iclass 5, count 0 2006.281.07:56:01.96#ibcon#read 3, iclass 5, count 0 2006.281.07:56:01.96#ibcon#about to read 4, iclass 5, count 0 2006.281.07:56:01.96#ibcon#read 4, iclass 5, count 0 2006.281.07:56:01.96#ibcon#about to read 5, iclass 5, count 0 2006.281.07:56:01.96#ibcon#read 5, iclass 5, count 0 2006.281.07:56:01.96#ibcon#about to read 6, iclass 5, count 0 2006.281.07:56:01.96#ibcon#read 6, iclass 5, count 0 2006.281.07:56:01.96#ibcon#end of sib2, iclass 5, count 0 2006.281.07:56:01.96#ibcon#*mode == 0, iclass 5, count 0 2006.281.07:56:01.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.07:56:01.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:56:01.96#ibcon#*before write, iclass 5, count 0 2006.281.07:56:01.96#ibcon#enter sib2, iclass 5, count 0 2006.281.07:56:01.96#ibcon#flushed, iclass 5, count 0 2006.281.07:56:01.96#ibcon#about to write, iclass 5, count 0 2006.281.07:56:01.96#ibcon#wrote, iclass 5, count 0 2006.281.07:56:01.96#ibcon#about to read 3, iclass 5, count 0 2006.281.07:56:02.00#ibcon#read 3, iclass 5, count 0 2006.281.07:56:02.00#ibcon#about to read 4, iclass 5, count 0 2006.281.07:56:02.00#ibcon#read 4, iclass 5, count 0 2006.281.07:56:02.00#ibcon#about to read 5, iclass 5, count 0 2006.281.07:56:02.00#ibcon#read 5, iclass 5, count 0 2006.281.07:56:02.00#ibcon#about to read 6, iclass 5, count 0 2006.281.07:56:02.00#ibcon#read 6, iclass 5, count 0 2006.281.07:56:02.00#ibcon#end of sib2, iclass 5, count 0 2006.281.07:56:02.00#ibcon#*after write, iclass 5, count 0 2006.281.07:56:02.00#ibcon#*before return 0, iclass 5, count 0 2006.281.07:56:02.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:56:02.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.07:56:02.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.07:56:02.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.07:56:02.00$vc4f8/va=7,6 2006.281.07:56:02.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.07:56:02.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.07:56:02.00#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:02.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:56:02.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:56:02.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:56:02.06#ibcon#enter wrdev, iclass 7, count 2 2006.281.07:56:02.06#ibcon#first serial, iclass 7, count 2 2006.281.07:56:02.06#ibcon#enter sib2, iclass 7, count 2 2006.281.07:56:02.06#ibcon#flushed, iclass 7, count 2 2006.281.07:56:02.06#ibcon#about to write, iclass 7, count 2 2006.281.07:56:02.06#ibcon#wrote, iclass 7, count 2 2006.281.07:56:02.06#ibcon#about to read 3, iclass 7, count 2 2006.281.07:56:02.08#ibcon#read 3, iclass 7, count 2 2006.281.07:56:02.08#ibcon#about to read 4, iclass 7, count 2 2006.281.07:56:02.08#ibcon#read 4, iclass 7, count 2 2006.281.07:56:02.08#ibcon#about to read 5, iclass 7, count 2 2006.281.07:56:02.08#ibcon#read 5, iclass 7, count 2 2006.281.07:56:02.08#ibcon#about to read 6, iclass 7, count 2 2006.281.07:56:02.08#ibcon#read 6, iclass 7, count 2 2006.281.07:56:02.08#ibcon#end of sib2, iclass 7, count 2 2006.281.07:56:02.08#ibcon#*mode == 0, iclass 7, count 2 2006.281.07:56:02.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.07:56:02.08#ibcon#[25=AT07-06\r\n] 2006.281.07:56:02.08#ibcon#*before write, iclass 7, count 2 2006.281.07:56:02.08#ibcon#enter sib2, iclass 7, count 2 2006.281.07:56:02.08#ibcon#flushed, iclass 7, count 2 2006.281.07:56:02.08#ibcon#about to write, iclass 7, count 2 2006.281.07:56:02.08#ibcon#wrote, iclass 7, count 2 2006.281.07:56:02.08#ibcon#about to read 3, iclass 7, count 2 2006.281.07:56:02.11#ibcon#read 3, iclass 7, count 2 2006.281.07:56:02.11#ibcon#about to read 4, iclass 7, count 2 2006.281.07:56:02.11#ibcon#read 4, iclass 7, count 2 2006.281.07:56:02.11#ibcon#about to read 5, iclass 7, count 2 2006.281.07:56:02.11#ibcon#read 5, iclass 7, count 2 2006.281.07:56:02.11#ibcon#about to read 6, iclass 7, count 2 2006.281.07:56:02.11#ibcon#read 6, iclass 7, count 2 2006.281.07:56:02.11#ibcon#end of sib2, iclass 7, count 2 2006.281.07:56:02.11#ibcon#*after write, iclass 7, count 2 2006.281.07:56:02.11#ibcon#*before return 0, iclass 7, count 2 2006.281.07:56:02.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:56:02.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.07:56:02.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.07:56:02.11#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:02.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:56:02.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:56:02.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:56:02.23#ibcon#enter wrdev, iclass 7, count 0 2006.281.07:56:02.23#ibcon#first serial, iclass 7, count 0 2006.281.07:56:02.23#ibcon#enter sib2, iclass 7, count 0 2006.281.07:56:02.23#ibcon#flushed, iclass 7, count 0 2006.281.07:56:02.23#ibcon#about to write, iclass 7, count 0 2006.281.07:56:02.23#ibcon#wrote, iclass 7, count 0 2006.281.07:56:02.23#ibcon#about to read 3, iclass 7, count 0 2006.281.07:56:02.25#ibcon#read 3, iclass 7, count 0 2006.281.07:56:02.25#ibcon#about to read 4, iclass 7, count 0 2006.281.07:56:02.25#ibcon#read 4, iclass 7, count 0 2006.281.07:56:02.25#ibcon#about to read 5, iclass 7, count 0 2006.281.07:56:02.25#ibcon#read 5, iclass 7, count 0 2006.281.07:56:02.25#ibcon#about to read 6, iclass 7, count 0 2006.281.07:56:02.25#ibcon#read 6, iclass 7, count 0 2006.281.07:56:02.25#ibcon#end of sib2, iclass 7, count 0 2006.281.07:56:02.25#ibcon#*mode == 0, iclass 7, count 0 2006.281.07:56:02.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.07:56:02.25#ibcon#[25=USB\r\n] 2006.281.07:56:02.25#ibcon#*before write, iclass 7, count 0 2006.281.07:56:02.25#ibcon#enter sib2, iclass 7, count 0 2006.281.07:56:02.25#ibcon#flushed, iclass 7, count 0 2006.281.07:56:02.25#ibcon#about to write, iclass 7, count 0 2006.281.07:56:02.25#ibcon#wrote, iclass 7, count 0 2006.281.07:56:02.25#ibcon#about to read 3, iclass 7, count 0 2006.281.07:56:02.28#ibcon#read 3, iclass 7, count 0 2006.281.07:56:02.28#ibcon#about to read 4, iclass 7, count 0 2006.281.07:56:02.28#ibcon#read 4, iclass 7, count 0 2006.281.07:56:02.28#ibcon#about to read 5, iclass 7, count 0 2006.281.07:56:02.28#ibcon#read 5, iclass 7, count 0 2006.281.07:56:02.28#ibcon#about to read 6, iclass 7, count 0 2006.281.07:56:02.28#ibcon#read 6, iclass 7, count 0 2006.281.07:56:02.28#ibcon#end of sib2, iclass 7, count 0 2006.281.07:56:02.28#ibcon#*after write, iclass 7, count 0 2006.281.07:56:02.28#ibcon#*before return 0, iclass 7, count 0 2006.281.07:56:02.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:56:02.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.07:56:02.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.07:56:02.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.07:56:02.28$vc4f8/valo=8,852.99 2006.281.07:56:02.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.07:56:02.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.07:56:02.28#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:02.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:56:02.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:56:02.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:56:02.28#ibcon#enter wrdev, iclass 11, count 0 2006.281.07:56:02.28#ibcon#first serial, iclass 11, count 0 2006.281.07:56:02.28#ibcon#enter sib2, iclass 11, count 0 2006.281.07:56:02.28#ibcon#flushed, iclass 11, count 0 2006.281.07:56:02.28#ibcon#about to write, iclass 11, count 0 2006.281.07:56:02.28#ibcon#wrote, iclass 11, count 0 2006.281.07:56:02.28#ibcon#about to read 3, iclass 11, count 0 2006.281.07:56:02.30#ibcon#read 3, iclass 11, count 0 2006.281.07:56:02.30#ibcon#about to read 4, iclass 11, count 0 2006.281.07:56:02.30#ibcon#read 4, iclass 11, count 0 2006.281.07:56:02.30#ibcon#about to read 5, iclass 11, count 0 2006.281.07:56:02.30#ibcon#read 5, iclass 11, count 0 2006.281.07:56:02.30#ibcon#about to read 6, iclass 11, count 0 2006.281.07:56:02.30#ibcon#read 6, iclass 11, count 0 2006.281.07:56:02.30#ibcon#end of sib2, iclass 11, count 0 2006.281.07:56:02.30#ibcon#*mode == 0, iclass 11, count 0 2006.281.07:56:02.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.07:56:02.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:56:02.32#ibcon#*before write, iclass 11, count 0 2006.281.07:56:02.32#ibcon#enter sib2, iclass 11, count 0 2006.281.07:56:02.32#ibcon#flushed, iclass 11, count 0 2006.281.07:56:02.32#ibcon#about to write, iclass 11, count 0 2006.281.07:56:02.32#ibcon#wrote, iclass 11, count 0 2006.281.07:56:02.32#ibcon#about to read 3, iclass 11, count 0 2006.281.07:56:02.36#ibcon#read 3, iclass 11, count 0 2006.281.07:56:02.36#ibcon#about to read 4, iclass 11, count 0 2006.281.07:56:02.36#ibcon#read 4, iclass 11, count 0 2006.281.07:56:02.36#ibcon#about to read 5, iclass 11, count 0 2006.281.07:56:02.36#ibcon#read 5, iclass 11, count 0 2006.281.07:56:02.36#ibcon#about to read 6, iclass 11, count 0 2006.281.07:56:02.36#ibcon#read 6, iclass 11, count 0 2006.281.07:56:02.36#ibcon#end of sib2, iclass 11, count 0 2006.281.07:56:02.36#ibcon#*after write, iclass 11, count 0 2006.281.07:56:02.36#ibcon#*before return 0, iclass 11, count 0 2006.281.07:56:02.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:56:02.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.07:56:02.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.07:56:02.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.07:56:02.36$vc4f8/va=8,6 2006.281.07:56:02.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.07:56:02.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.07:56:02.36#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:02.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:56:02.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:56:02.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:56:02.40#ibcon#enter wrdev, iclass 13, count 2 2006.281.07:56:02.40#ibcon#first serial, iclass 13, count 2 2006.281.07:56:02.40#ibcon#enter sib2, iclass 13, count 2 2006.281.07:56:02.40#ibcon#flushed, iclass 13, count 2 2006.281.07:56:02.40#ibcon#about to write, iclass 13, count 2 2006.281.07:56:02.40#ibcon#wrote, iclass 13, count 2 2006.281.07:56:02.40#ibcon#about to read 3, iclass 13, count 2 2006.281.07:56:02.42#ibcon#read 3, iclass 13, count 2 2006.281.07:56:02.42#ibcon#about to read 4, iclass 13, count 2 2006.281.07:56:02.42#ibcon#read 4, iclass 13, count 2 2006.281.07:56:02.42#ibcon#about to read 5, iclass 13, count 2 2006.281.07:56:02.42#ibcon#read 5, iclass 13, count 2 2006.281.07:56:02.42#ibcon#about to read 6, iclass 13, count 2 2006.281.07:56:02.42#ibcon#read 6, iclass 13, count 2 2006.281.07:56:02.42#ibcon#end of sib2, iclass 13, count 2 2006.281.07:56:02.42#ibcon#*mode == 0, iclass 13, count 2 2006.281.07:56:02.42#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.07:56:02.42#ibcon#[25=AT08-06\r\n] 2006.281.07:56:02.42#ibcon#*before write, iclass 13, count 2 2006.281.07:56:02.42#ibcon#enter sib2, iclass 13, count 2 2006.281.07:56:02.42#ibcon#flushed, iclass 13, count 2 2006.281.07:56:02.42#ibcon#about to write, iclass 13, count 2 2006.281.07:56:02.42#ibcon#wrote, iclass 13, count 2 2006.281.07:56:02.42#ibcon#about to read 3, iclass 13, count 2 2006.281.07:56:02.45#ibcon#read 3, iclass 13, count 2 2006.281.07:56:02.45#ibcon#about to read 4, iclass 13, count 2 2006.281.07:56:02.45#ibcon#read 4, iclass 13, count 2 2006.281.07:56:02.45#ibcon#about to read 5, iclass 13, count 2 2006.281.07:56:02.45#ibcon#read 5, iclass 13, count 2 2006.281.07:56:02.45#ibcon#about to read 6, iclass 13, count 2 2006.281.07:56:02.45#ibcon#read 6, iclass 13, count 2 2006.281.07:56:02.45#ibcon#end of sib2, iclass 13, count 2 2006.281.07:56:02.45#ibcon#*after write, iclass 13, count 2 2006.281.07:56:02.45#ibcon#*before return 0, iclass 13, count 2 2006.281.07:56:02.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:56:02.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.07:56:02.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.07:56:02.45#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:02.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:56:02.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:56:02.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:56:02.57#ibcon#enter wrdev, iclass 13, count 0 2006.281.07:56:02.57#ibcon#first serial, iclass 13, count 0 2006.281.07:56:02.57#ibcon#enter sib2, iclass 13, count 0 2006.281.07:56:02.57#ibcon#flushed, iclass 13, count 0 2006.281.07:56:02.57#ibcon#about to write, iclass 13, count 0 2006.281.07:56:02.57#ibcon#wrote, iclass 13, count 0 2006.281.07:56:02.57#ibcon#about to read 3, iclass 13, count 0 2006.281.07:56:02.59#ibcon#read 3, iclass 13, count 0 2006.281.07:56:02.59#ibcon#about to read 4, iclass 13, count 0 2006.281.07:56:02.59#ibcon#read 4, iclass 13, count 0 2006.281.07:56:02.59#ibcon#about to read 5, iclass 13, count 0 2006.281.07:56:02.59#ibcon#read 5, iclass 13, count 0 2006.281.07:56:02.59#ibcon#about to read 6, iclass 13, count 0 2006.281.07:56:02.59#ibcon#read 6, iclass 13, count 0 2006.281.07:56:02.59#ibcon#end of sib2, iclass 13, count 0 2006.281.07:56:02.59#ibcon#*mode == 0, iclass 13, count 0 2006.281.07:56:02.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.07:56:02.59#ibcon#[25=USB\r\n] 2006.281.07:56:02.59#ibcon#*before write, iclass 13, count 0 2006.281.07:56:02.59#ibcon#enter sib2, iclass 13, count 0 2006.281.07:56:02.59#ibcon#flushed, iclass 13, count 0 2006.281.07:56:02.59#ibcon#about to write, iclass 13, count 0 2006.281.07:56:02.59#ibcon#wrote, iclass 13, count 0 2006.281.07:56:02.59#ibcon#about to read 3, iclass 13, count 0 2006.281.07:56:02.62#ibcon#read 3, iclass 13, count 0 2006.281.07:56:02.62#ibcon#about to read 4, iclass 13, count 0 2006.281.07:56:02.62#ibcon#read 4, iclass 13, count 0 2006.281.07:56:02.62#ibcon#about to read 5, iclass 13, count 0 2006.281.07:56:02.62#ibcon#read 5, iclass 13, count 0 2006.281.07:56:02.62#ibcon#about to read 6, iclass 13, count 0 2006.281.07:56:02.62#ibcon#read 6, iclass 13, count 0 2006.281.07:56:02.62#ibcon#end of sib2, iclass 13, count 0 2006.281.07:56:02.62#ibcon#*after write, iclass 13, count 0 2006.281.07:56:02.62#ibcon#*before return 0, iclass 13, count 0 2006.281.07:56:02.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:56:02.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.07:56:02.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.07:56:02.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.07:56:02.62$vc4f8/vblo=1,632.99 2006.281.07:56:02.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.07:56:02.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.07:56:02.62#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:02.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:56:02.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:56:02.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:56:02.62#ibcon#enter wrdev, iclass 15, count 0 2006.281.07:56:02.62#ibcon#first serial, iclass 15, count 0 2006.281.07:56:02.62#ibcon#enter sib2, iclass 15, count 0 2006.281.07:56:02.62#ibcon#flushed, iclass 15, count 0 2006.281.07:56:02.62#ibcon#about to write, iclass 15, count 0 2006.281.07:56:02.62#ibcon#wrote, iclass 15, count 0 2006.281.07:56:02.62#ibcon#about to read 3, iclass 15, count 0 2006.281.07:56:02.64#ibcon#read 3, iclass 15, count 0 2006.281.07:56:02.64#ibcon#about to read 4, iclass 15, count 0 2006.281.07:56:02.64#ibcon#read 4, iclass 15, count 0 2006.281.07:56:02.64#ibcon#about to read 5, iclass 15, count 0 2006.281.07:56:02.64#ibcon#read 5, iclass 15, count 0 2006.281.07:56:02.64#ibcon#about to read 6, iclass 15, count 0 2006.281.07:56:02.64#ibcon#read 6, iclass 15, count 0 2006.281.07:56:02.64#ibcon#end of sib2, iclass 15, count 0 2006.281.07:56:02.64#ibcon#*mode == 0, iclass 15, count 0 2006.281.07:56:02.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.07:56:02.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:56:02.64#ibcon#*before write, iclass 15, count 0 2006.281.07:56:02.64#ibcon#enter sib2, iclass 15, count 0 2006.281.07:56:02.64#ibcon#flushed, iclass 15, count 0 2006.281.07:56:02.64#ibcon#about to write, iclass 15, count 0 2006.281.07:56:02.64#ibcon#wrote, iclass 15, count 0 2006.281.07:56:02.64#ibcon#about to read 3, iclass 15, count 0 2006.281.07:56:02.68#ibcon#read 3, iclass 15, count 0 2006.281.07:56:02.68#ibcon#about to read 4, iclass 15, count 0 2006.281.07:56:02.68#ibcon#read 4, iclass 15, count 0 2006.281.07:56:02.68#ibcon#about to read 5, iclass 15, count 0 2006.281.07:56:02.68#ibcon#read 5, iclass 15, count 0 2006.281.07:56:02.68#ibcon#about to read 6, iclass 15, count 0 2006.281.07:56:02.68#ibcon#read 6, iclass 15, count 0 2006.281.07:56:02.68#ibcon#end of sib2, iclass 15, count 0 2006.281.07:56:02.68#ibcon#*after write, iclass 15, count 0 2006.281.07:56:02.68#ibcon#*before return 0, iclass 15, count 0 2006.281.07:56:02.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:56:02.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.07:56:02.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.07:56:02.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.07:56:02.68$vc4f8/vb=1,4 2006.281.07:56:02.68#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:56:02.68#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:56:02.68#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:02.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:56:02.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:56:02.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:56:02.68#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:56:02.68#ibcon#first serial, iclass 17, count 2 2006.281.07:56:02.68#ibcon#enter sib2, iclass 17, count 2 2006.281.07:56:02.68#ibcon#flushed, iclass 17, count 2 2006.281.07:56:02.68#ibcon#about to write, iclass 17, count 2 2006.281.07:56:02.68#ibcon#wrote, iclass 17, count 2 2006.281.07:56:02.68#ibcon#about to read 3, iclass 17, count 2 2006.281.07:56:02.70#ibcon#read 3, iclass 17, count 2 2006.281.07:56:02.71#ibcon#about to read 4, iclass 17, count 2 2006.281.07:56:02.71#ibcon#read 4, iclass 17, count 2 2006.281.07:56:02.71#ibcon#about to read 5, iclass 17, count 2 2006.281.07:56:02.71#ibcon#read 5, iclass 17, count 2 2006.281.07:56:02.71#ibcon#about to read 6, iclass 17, count 2 2006.281.07:56:02.71#ibcon#read 6, iclass 17, count 2 2006.281.07:56:02.71#ibcon#end of sib2, iclass 17, count 2 2006.281.07:56:02.71#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:56:02.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:56:02.71#ibcon#[27=AT01-04\r\n] 2006.281.07:56:02.71#ibcon#*before write, iclass 17, count 2 2006.281.07:56:02.71#ibcon#enter sib2, iclass 17, count 2 2006.281.07:56:02.71#ibcon#flushed, iclass 17, count 2 2006.281.07:56:02.71#ibcon#about to write, iclass 17, count 2 2006.281.07:56:02.71#ibcon#wrote, iclass 17, count 2 2006.281.07:56:02.71#ibcon#about to read 3, iclass 17, count 2 2006.281.07:56:02.74#ibcon#read 3, iclass 17, count 2 2006.281.07:56:02.74#ibcon#about to read 4, iclass 17, count 2 2006.281.07:56:02.74#ibcon#read 4, iclass 17, count 2 2006.281.07:56:02.74#ibcon#about to read 5, iclass 17, count 2 2006.281.07:56:02.74#ibcon#read 5, iclass 17, count 2 2006.281.07:56:02.74#ibcon#about to read 6, iclass 17, count 2 2006.281.07:56:02.74#ibcon#read 6, iclass 17, count 2 2006.281.07:56:02.74#ibcon#end of sib2, iclass 17, count 2 2006.281.07:56:02.74#ibcon#*after write, iclass 17, count 2 2006.281.07:56:02.74#ibcon#*before return 0, iclass 17, count 2 2006.281.07:56:02.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:56:02.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:56:02.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:56:02.74#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:02.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:56:02.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:56:02.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:56:02.86#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:56:02.86#ibcon#first serial, iclass 17, count 0 2006.281.07:56:02.86#ibcon#enter sib2, iclass 17, count 0 2006.281.07:56:02.86#ibcon#flushed, iclass 17, count 0 2006.281.07:56:02.86#ibcon#about to write, iclass 17, count 0 2006.281.07:56:02.86#ibcon#wrote, iclass 17, count 0 2006.281.07:56:02.86#ibcon#about to read 3, iclass 17, count 0 2006.281.07:56:02.88#ibcon#read 3, iclass 17, count 0 2006.281.07:56:02.88#ibcon#about to read 4, iclass 17, count 0 2006.281.07:56:02.88#ibcon#read 4, iclass 17, count 0 2006.281.07:56:02.88#ibcon#about to read 5, iclass 17, count 0 2006.281.07:56:02.88#ibcon#read 5, iclass 17, count 0 2006.281.07:56:02.88#ibcon#about to read 6, iclass 17, count 0 2006.281.07:56:02.88#ibcon#read 6, iclass 17, count 0 2006.281.07:56:02.88#ibcon#end of sib2, iclass 17, count 0 2006.281.07:56:02.88#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:56:02.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:56:02.88#ibcon#[27=USB\r\n] 2006.281.07:56:02.88#ibcon#*before write, iclass 17, count 0 2006.281.07:56:02.88#ibcon#enter sib2, iclass 17, count 0 2006.281.07:56:02.88#ibcon#flushed, iclass 17, count 0 2006.281.07:56:02.88#ibcon#about to write, iclass 17, count 0 2006.281.07:56:02.88#ibcon#wrote, iclass 17, count 0 2006.281.07:56:02.88#ibcon#about to read 3, iclass 17, count 0 2006.281.07:56:02.91#ibcon#read 3, iclass 17, count 0 2006.281.07:56:02.91#ibcon#about to read 4, iclass 17, count 0 2006.281.07:56:02.91#ibcon#read 4, iclass 17, count 0 2006.281.07:56:02.91#ibcon#about to read 5, iclass 17, count 0 2006.281.07:56:02.91#ibcon#read 5, iclass 17, count 0 2006.281.07:56:02.91#ibcon#about to read 6, iclass 17, count 0 2006.281.07:56:02.91#ibcon#read 6, iclass 17, count 0 2006.281.07:56:02.91#ibcon#end of sib2, iclass 17, count 0 2006.281.07:56:02.91#ibcon#*after write, iclass 17, count 0 2006.281.07:56:02.91#ibcon#*before return 0, iclass 17, count 0 2006.281.07:56:02.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:56:02.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:56:02.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:56:02.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:56:02.91$vc4f8/vblo=2,640.99 2006.281.07:56:02.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.07:56:02.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.07:56:02.91#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:02.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:02.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:02.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:02.91#ibcon#enter wrdev, iclass 19, count 0 2006.281.07:56:02.91#ibcon#first serial, iclass 19, count 0 2006.281.07:56:02.91#ibcon#enter sib2, iclass 19, count 0 2006.281.07:56:02.91#ibcon#flushed, iclass 19, count 0 2006.281.07:56:02.91#ibcon#about to write, iclass 19, count 0 2006.281.07:56:02.91#ibcon#wrote, iclass 19, count 0 2006.281.07:56:02.91#ibcon#about to read 3, iclass 19, count 0 2006.281.07:56:02.93#ibcon#read 3, iclass 19, count 0 2006.281.07:56:02.93#ibcon#about to read 4, iclass 19, count 0 2006.281.07:56:02.93#ibcon#read 4, iclass 19, count 0 2006.281.07:56:02.93#ibcon#about to read 5, iclass 19, count 0 2006.281.07:56:02.93#ibcon#read 5, iclass 19, count 0 2006.281.07:56:02.93#ibcon#about to read 6, iclass 19, count 0 2006.281.07:56:02.93#ibcon#read 6, iclass 19, count 0 2006.281.07:56:02.93#ibcon#end of sib2, iclass 19, count 0 2006.281.07:56:02.93#ibcon#*mode == 0, iclass 19, count 0 2006.281.07:56:02.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.07:56:02.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:56:02.93#ibcon#*before write, iclass 19, count 0 2006.281.07:56:02.93#ibcon#enter sib2, iclass 19, count 0 2006.281.07:56:02.93#ibcon#flushed, iclass 19, count 0 2006.281.07:56:02.93#ibcon#about to write, iclass 19, count 0 2006.281.07:56:02.93#ibcon#wrote, iclass 19, count 0 2006.281.07:56:02.93#ibcon#about to read 3, iclass 19, count 0 2006.281.07:56:02.97#ibcon#read 3, iclass 19, count 0 2006.281.07:56:02.97#ibcon#about to read 4, iclass 19, count 0 2006.281.07:56:02.97#ibcon#read 4, iclass 19, count 0 2006.281.07:56:02.97#ibcon#about to read 5, iclass 19, count 0 2006.281.07:56:02.97#ibcon#read 5, iclass 19, count 0 2006.281.07:56:02.97#ibcon#about to read 6, iclass 19, count 0 2006.281.07:56:02.97#ibcon#read 6, iclass 19, count 0 2006.281.07:56:02.97#ibcon#end of sib2, iclass 19, count 0 2006.281.07:56:02.97#ibcon#*after write, iclass 19, count 0 2006.281.07:56:02.97#ibcon#*before return 0, iclass 19, count 0 2006.281.07:56:02.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:02.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.07:56:02.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.07:56:02.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.07:56:02.97$vc4f8/vb=2,5 2006.281.07:56:02.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.07:56:02.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.07:56:02.97#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:02.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:03.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:03.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:03.03#ibcon#enter wrdev, iclass 21, count 2 2006.281.07:56:03.03#ibcon#first serial, iclass 21, count 2 2006.281.07:56:03.03#ibcon#enter sib2, iclass 21, count 2 2006.281.07:56:03.03#ibcon#flushed, iclass 21, count 2 2006.281.07:56:03.03#ibcon#about to write, iclass 21, count 2 2006.281.07:56:03.03#ibcon#wrote, iclass 21, count 2 2006.281.07:56:03.03#ibcon#about to read 3, iclass 21, count 2 2006.281.07:56:03.05#ibcon#read 3, iclass 21, count 2 2006.281.07:56:03.05#ibcon#about to read 4, iclass 21, count 2 2006.281.07:56:03.05#ibcon#read 4, iclass 21, count 2 2006.281.07:56:03.05#ibcon#about to read 5, iclass 21, count 2 2006.281.07:56:03.05#ibcon#read 5, iclass 21, count 2 2006.281.07:56:03.05#ibcon#about to read 6, iclass 21, count 2 2006.281.07:56:03.05#ibcon#read 6, iclass 21, count 2 2006.281.07:56:03.05#ibcon#end of sib2, iclass 21, count 2 2006.281.07:56:03.05#ibcon#*mode == 0, iclass 21, count 2 2006.281.07:56:03.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.07:56:03.05#ibcon#[27=AT02-05\r\n] 2006.281.07:56:03.05#ibcon#*before write, iclass 21, count 2 2006.281.07:56:03.05#ibcon#enter sib2, iclass 21, count 2 2006.281.07:56:03.05#ibcon#flushed, iclass 21, count 2 2006.281.07:56:03.05#ibcon#about to write, iclass 21, count 2 2006.281.07:56:03.05#ibcon#wrote, iclass 21, count 2 2006.281.07:56:03.05#ibcon#about to read 3, iclass 21, count 2 2006.281.07:56:03.08#ibcon#read 3, iclass 21, count 2 2006.281.07:56:03.08#ibcon#about to read 4, iclass 21, count 2 2006.281.07:56:03.08#ibcon#read 4, iclass 21, count 2 2006.281.07:56:03.08#ibcon#about to read 5, iclass 21, count 2 2006.281.07:56:03.08#ibcon#read 5, iclass 21, count 2 2006.281.07:56:03.08#ibcon#about to read 6, iclass 21, count 2 2006.281.07:56:03.08#ibcon#read 6, iclass 21, count 2 2006.281.07:56:03.08#ibcon#end of sib2, iclass 21, count 2 2006.281.07:56:03.08#ibcon#*after write, iclass 21, count 2 2006.281.07:56:03.08#ibcon#*before return 0, iclass 21, count 2 2006.281.07:56:03.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:03.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.07:56:03.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.07:56:03.08#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:03.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:03.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:03.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:03.20#ibcon#enter wrdev, iclass 21, count 0 2006.281.07:56:03.20#ibcon#first serial, iclass 21, count 0 2006.281.07:56:03.20#ibcon#enter sib2, iclass 21, count 0 2006.281.07:56:03.20#ibcon#flushed, iclass 21, count 0 2006.281.07:56:03.20#ibcon#about to write, iclass 21, count 0 2006.281.07:56:03.20#ibcon#wrote, iclass 21, count 0 2006.281.07:56:03.20#ibcon#about to read 3, iclass 21, count 0 2006.281.07:56:03.22#ibcon#read 3, iclass 21, count 0 2006.281.07:56:03.22#ibcon#about to read 4, iclass 21, count 0 2006.281.07:56:03.22#ibcon#read 4, iclass 21, count 0 2006.281.07:56:03.22#ibcon#about to read 5, iclass 21, count 0 2006.281.07:56:03.22#ibcon#read 5, iclass 21, count 0 2006.281.07:56:03.22#ibcon#about to read 6, iclass 21, count 0 2006.281.07:56:03.22#ibcon#read 6, iclass 21, count 0 2006.281.07:56:03.22#ibcon#end of sib2, iclass 21, count 0 2006.281.07:56:03.22#ibcon#*mode == 0, iclass 21, count 0 2006.281.07:56:03.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.07:56:03.22#ibcon#[27=USB\r\n] 2006.281.07:56:03.22#ibcon#*before write, iclass 21, count 0 2006.281.07:56:03.22#ibcon#enter sib2, iclass 21, count 0 2006.281.07:56:03.22#ibcon#flushed, iclass 21, count 0 2006.281.07:56:03.22#ibcon#about to write, iclass 21, count 0 2006.281.07:56:03.22#ibcon#wrote, iclass 21, count 0 2006.281.07:56:03.22#ibcon#about to read 3, iclass 21, count 0 2006.281.07:56:03.25#ibcon#read 3, iclass 21, count 0 2006.281.07:56:03.25#ibcon#about to read 4, iclass 21, count 0 2006.281.07:56:03.25#ibcon#read 4, iclass 21, count 0 2006.281.07:56:03.25#ibcon#about to read 5, iclass 21, count 0 2006.281.07:56:03.25#ibcon#read 5, iclass 21, count 0 2006.281.07:56:03.25#ibcon#about to read 6, iclass 21, count 0 2006.281.07:56:03.25#ibcon#read 6, iclass 21, count 0 2006.281.07:56:03.25#ibcon#end of sib2, iclass 21, count 0 2006.281.07:56:03.25#ibcon#*after write, iclass 21, count 0 2006.281.07:56:03.25#ibcon#*before return 0, iclass 21, count 0 2006.281.07:56:03.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:03.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.07:56:03.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.07:56:03.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.07:56:03.25$vc4f8/vblo=3,656.99 2006.281.07:56:03.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.07:56:03.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.07:56:03.25#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:03.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:03.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:03.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:03.25#ibcon#enter wrdev, iclass 23, count 0 2006.281.07:56:03.25#ibcon#first serial, iclass 23, count 0 2006.281.07:56:03.25#ibcon#enter sib2, iclass 23, count 0 2006.281.07:56:03.25#ibcon#flushed, iclass 23, count 0 2006.281.07:56:03.25#ibcon#about to write, iclass 23, count 0 2006.281.07:56:03.25#ibcon#wrote, iclass 23, count 0 2006.281.07:56:03.25#ibcon#about to read 3, iclass 23, count 0 2006.281.07:56:03.27#ibcon#read 3, iclass 23, count 0 2006.281.07:56:03.27#ibcon#about to read 4, iclass 23, count 0 2006.281.07:56:03.27#ibcon#read 4, iclass 23, count 0 2006.281.07:56:03.27#ibcon#about to read 5, iclass 23, count 0 2006.281.07:56:03.27#ibcon#read 5, iclass 23, count 0 2006.281.07:56:03.27#ibcon#about to read 6, iclass 23, count 0 2006.281.07:56:03.27#ibcon#read 6, iclass 23, count 0 2006.281.07:56:03.27#ibcon#end of sib2, iclass 23, count 0 2006.281.07:56:03.27#ibcon#*mode == 0, iclass 23, count 0 2006.281.07:56:03.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.07:56:03.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:56:03.29#ibcon#*before write, iclass 23, count 0 2006.281.07:56:03.29#ibcon#enter sib2, iclass 23, count 0 2006.281.07:56:03.29#ibcon#flushed, iclass 23, count 0 2006.281.07:56:03.29#ibcon#about to write, iclass 23, count 0 2006.281.07:56:03.29#ibcon#wrote, iclass 23, count 0 2006.281.07:56:03.29#ibcon#about to read 3, iclass 23, count 0 2006.281.07:56:03.33#ibcon#read 3, iclass 23, count 0 2006.281.07:56:03.33#ibcon#about to read 4, iclass 23, count 0 2006.281.07:56:03.33#ibcon#read 4, iclass 23, count 0 2006.281.07:56:03.33#ibcon#about to read 5, iclass 23, count 0 2006.281.07:56:03.33#ibcon#read 5, iclass 23, count 0 2006.281.07:56:03.33#ibcon#about to read 6, iclass 23, count 0 2006.281.07:56:03.33#ibcon#read 6, iclass 23, count 0 2006.281.07:56:03.33#ibcon#end of sib2, iclass 23, count 0 2006.281.07:56:03.33#ibcon#*after write, iclass 23, count 0 2006.281.07:56:03.33#ibcon#*before return 0, iclass 23, count 0 2006.281.07:56:03.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:03.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.07:56:03.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.07:56:03.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.07:56:03.33$vc4f8/vb=3,4 2006.281.07:56:03.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.07:56:03.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.07:56:03.33#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:03.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:03.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:03.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:03.37#ibcon#enter wrdev, iclass 25, count 2 2006.281.07:56:03.37#ibcon#first serial, iclass 25, count 2 2006.281.07:56:03.37#ibcon#enter sib2, iclass 25, count 2 2006.281.07:56:03.37#ibcon#flushed, iclass 25, count 2 2006.281.07:56:03.37#ibcon#about to write, iclass 25, count 2 2006.281.07:56:03.37#ibcon#wrote, iclass 25, count 2 2006.281.07:56:03.37#ibcon#about to read 3, iclass 25, count 2 2006.281.07:56:03.39#ibcon#read 3, iclass 25, count 2 2006.281.07:56:03.39#ibcon#about to read 4, iclass 25, count 2 2006.281.07:56:03.39#ibcon#read 4, iclass 25, count 2 2006.281.07:56:03.39#ibcon#about to read 5, iclass 25, count 2 2006.281.07:56:03.39#ibcon#read 5, iclass 25, count 2 2006.281.07:56:03.39#ibcon#about to read 6, iclass 25, count 2 2006.281.07:56:03.39#ibcon#read 6, iclass 25, count 2 2006.281.07:56:03.39#ibcon#end of sib2, iclass 25, count 2 2006.281.07:56:03.39#ibcon#*mode == 0, iclass 25, count 2 2006.281.07:56:03.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.07:56:03.39#ibcon#[27=AT03-04\r\n] 2006.281.07:56:03.39#ibcon#*before write, iclass 25, count 2 2006.281.07:56:03.39#ibcon#enter sib2, iclass 25, count 2 2006.281.07:56:03.39#ibcon#flushed, iclass 25, count 2 2006.281.07:56:03.39#ibcon#about to write, iclass 25, count 2 2006.281.07:56:03.39#ibcon#wrote, iclass 25, count 2 2006.281.07:56:03.39#ibcon#about to read 3, iclass 25, count 2 2006.281.07:56:03.42#ibcon#read 3, iclass 25, count 2 2006.281.07:56:03.42#ibcon#about to read 4, iclass 25, count 2 2006.281.07:56:03.42#ibcon#read 4, iclass 25, count 2 2006.281.07:56:03.42#ibcon#about to read 5, iclass 25, count 2 2006.281.07:56:03.42#ibcon#read 5, iclass 25, count 2 2006.281.07:56:03.42#ibcon#about to read 6, iclass 25, count 2 2006.281.07:56:03.42#ibcon#read 6, iclass 25, count 2 2006.281.07:56:03.42#ibcon#end of sib2, iclass 25, count 2 2006.281.07:56:03.42#ibcon#*after write, iclass 25, count 2 2006.281.07:56:03.42#ibcon#*before return 0, iclass 25, count 2 2006.281.07:56:03.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:03.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.07:56:03.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.07:56:03.42#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:03.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:03.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:03.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:03.54#ibcon#enter wrdev, iclass 25, count 0 2006.281.07:56:03.54#ibcon#first serial, iclass 25, count 0 2006.281.07:56:03.54#ibcon#enter sib2, iclass 25, count 0 2006.281.07:56:03.54#ibcon#flushed, iclass 25, count 0 2006.281.07:56:03.54#ibcon#about to write, iclass 25, count 0 2006.281.07:56:03.54#ibcon#wrote, iclass 25, count 0 2006.281.07:56:03.54#ibcon#about to read 3, iclass 25, count 0 2006.281.07:56:03.56#ibcon#read 3, iclass 25, count 0 2006.281.07:56:03.56#ibcon#about to read 4, iclass 25, count 0 2006.281.07:56:03.56#ibcon#read 4, iclass 25, count 0 2006.281.07:56:03.56#ibcon#about to read 5, iclass 25, count 0 2006.281.07:56:03.56#ibcon#read 5, iclass 25, count 0 2006.281.07:56:03.56#ibcon#about to read 6, iclass 25, count 0 2006.281.07:56:03.56#ibcon#read 6, iclass 25, count 0 2006.281.07:56:03.56#ibcon#end of sib2, iclass 25, count 0 2006.281.07:56:03.56#ibcon#*mode == 0, iclass 25, count 0 2006.281.07:56:03.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.07:56:03.56#ibcon#[27=USB\r\n] 2006.281.07:56:03.56#ibcon#*before write, iclass 25, count 0 2006.281.07:56:03.56#ibcon#enter sib2, iclass 25, count 0 2006.281.07:56:03.56#ibcon#flushed, iclass 25, count 0 2006.281.07:56:03.56#ibcon#about to write, iclass 25, count 0 2006.281.07:56:03.56#ibcon#wrote, iclass 25, count 0 2006.281.07:56:03.56#ibcon#about to read 3, iclass 25, count 0 2006.281.07:56:03.59#ibcon#read 3, iclass 25, count 0 2006.281.07:56:03.59#ibcon#about to read 4, iclass 25, count 0 2006.281.07:56:03.59#ibcon#read 4, iclass 25, count 0 2006.281.07:56:03.59#ibcon#about to read 5, iclass 25, count 0 2006.281.07:56:03.59#ibcon#read 5, iclass 25, count 0 2006.281.07:56:03.59#ibcon#about to read 6, iclass 25, count 0 2006.281.07:56:03.59#ibcon#read 6, iclass 25, count 0 2006.281.07:56:03.59#ibcon#end of sib2, iclass 25, count 0 2006.281.07:56:03.59#ibcon#*after write, iclass 25, count 0 2006.281.07:56:03.59#ibcon#*before return 0, iclass 25, count 0 2006.281.07:56:03.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:03.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.07:56:03.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.07:56:03.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.07:56:03.59$vc4f8/vblo=4,712.99 2006.281.07:56:03.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.07:56:03.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.07:56:03.59#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:03.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:03.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:03.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:03.59#ibcon#enter wrdev, iclass 27, count 0 2006.281.07:56:03.59#ibcon#first serial, iclass 27, count 0 2006.281.07:56:03.59#ibcon#enter sib2, iclass 27, count 0 2006.281.07:56:03.59#ibcon#flushed, iclass 27, count 0 2006.281.07:56:03.59#ibcon#about to write, iclass 27, count 0 2006.281.07:56:03.59#ibcon#wrote, iclass 27, count 0 2006.281.07:56:03.59#ibcon#about to read 3, iclass 27, count 0 2006.281.07:56:03.61#ibcon#read 3, iclass 27, count 0 2006.281.07:56:03.61#ibcon#about to read 4, iclass 27, count 0 2006.281.07:56:03.61#ibcon#read 4, iclass 27, count 0 2006.281.07:56:03.61#ibcon#about to read 5, iclass 27, count 0 2006.281.07:56:03.61#ibcon#read 5, iclass 27, count 0 2006.281.07:56:03.61#ibcon#about to read 6, iclass 27, count 0 2006.281.07:56:03.61#ibcon#read 6, iclass 27, count 0 2006.281.07:56:03.61#ibcon#end of sib2, iclass 27, count 0 2006.281.07:56:03.61#ibcon#*mode == 0, iclass 27, count 0 2006.281.07:56:03.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.07:56:03.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:56:03.61#ibcon#*before write, iclass 27, count 0 2006.281.07:56:03.61#ibcon#enter sib2, iclass 27, count 0 2006.281.07:56:03.61#ibcon#flushed, iclass 27, count 0 2006.281.07:56:03.61#ibcon#about to write, iclass 27, count 0 2006.281.07:56:03.61#ibcon#wrote, iclass 27, count 0 2006.281.07:56:03.61#ibcon#about to read 3, iclass 27, count 0 2006.281.07:56:03.65#ibcon#read 3, iclass 27, count 0 2006.281.07:56:03.65#ibcon#about to read 4, iclass 27, count 0 2006.281.07:56:03.65#ibcon#read 4, iclass 27, count 0 2006.281.07:56:03.65#ibcon#about to read 5, iclass 27, count 0 2006.281.07:56:03.65#ibcon#read 5, iclass 27, count 0 2006.281.07:56:03.65#ibcon#about to read 6, iclass 27, count 0 2006.281.07:56:03.65#ibcon#read 6, iclass 27, count 0 2006.281.07:56:03.65#ibcon#end of sib2, iclass 27, count 0 2006.281.07:56:03.65#ibcon#*after write, iclass 27, count 0 2006.281.07:56:03.65#ibcon#*before return 0, iclass 27, count 0 2006.281.07:56:03.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:03.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.07:56:03.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.07:56:03.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.07:56:03.65$vc4f8/vb=4,4 2006.281.07:56:03.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.07:56:03.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.07:56:03.65#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:03.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:03.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:03.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:03.71#ibcon#enter wrdev, iclass 29, count 2 2006.281.07:56:03.71#ibcon#first serial, iclass 29, count 2 2006.281.07:56:03.71#ibcon#enter sib2, iclass 29, count 2 2006.281.07:56:03.71#ibcon#flushed, iclass 29, count 2 2006.281.07:56:03.71#ibcon#about to write, iclass 29, count 2 2006.281.07:56:03.71#ibcon#wrote, iclass 29, count 2 2006.281.07:56:03.71#ibcon#about to read 3, iclass 29, count 2 2006.281.07:56:03.73#ibcon#read 3, iclass 29, count 2 2006.281.07:56:03.73#ibcon#about to read 4, iclass 29, count 2 2006.281.07:56:03.73#ibcon#read 4, iclass 29, count 2 2006.281.07:56:03.73#ibcon#about to read 5, iclass 29, count 2 2006.281.07:56:03.73#ibcon#read 5, iclass 29, count 2 2006.281.07:56:03.73#ibcon#about to read 6, iclass 29, count 2 2006.281.07:56:03.73#ibcon#read 6, iclass 29, count 2 2006.281.07:56:03.73#ibcon#end of sib2, iclass 29, count 2 2006.281.07:56:03.73#ibcon#*mode == 0, iclass 29, count 2 2006.281.07:56:03.73#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.07:56:03.73#ibcon#[27=AT04-04\r\n] 2006.281.07:56:03.73#ibcon#*before write, iclass 29, count 2 2006.281.07:56:03.73#ibcon#enter sib2, iclass 29, count 2 2006.281.07:56:03.73#ibcon#flushed, iclass 29, count 2 2006.281.07:56:03.73#ibcon#about to write, iclass 29, count 2 2006.281.07:56:03.73#ibcon#wrote, iclass 29, count 2 2006.281.07:56:03.73#ibcon#about to read 3, iclass 29, count 2 2006.281.07:56:03.76#ibcon#read 3, iclass 29, count 2 2006.281.07:56:03.76#ibcon#about to read 4, iclass 29, count 2 2006.281.07:56:03.76#ibcon#read 4, iclass 29, count 2 2006.281.07:56:03.76#ibcon#about to read 5, iclass 29, count 2 2006.281.07:56:03.76#ibcon#read 5, iclass 29, count 2 2006.281.07:56:03.76#ibcon#about to read 6, iclass 29, count 2 2006.281.07:56:03.76#ibcon#read 6, iclass 29, count 2 2006.281.07:56:03.76#ibcon#end of sib2, iclass 29, count 2 2006.281.07:56:03.76#ibcon#*after write, iclass 29, count 2 2006.281.07:56:03.76#ibcon#*before return 0, iclass 29, count 2 2006.281.07:56:03.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:03.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.07:56:03.76#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.07:56:03.76#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:03.76#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:03.88#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:03.88#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:03.88#ibcon#enter wrdev, iclass 29, count 0 2006.281.07:56:03.88#ibcon#first serial, iclass 29, count 0 2006.281.07:56:03.88#ibcon#enter sib2, iclass 29, count 0 2006.281.07:56:03.88#ibcon#flushed, iclass 29, count 0 2006.281.07:56:03.88#ibcon#about to write, iclass 29, count 0 2006.281.07:56:03.88#ibcon#wrote, iclass 29, count 0 2006.281.07:56:03.88#ibcon#about to read 3, iclass 29, count 0 2006.281.07:56:03.90#ibcon#read 3, iclass 29, count 0 2006.281.07:56:03.90#ibcon#about to read 4, iclass 29, count 0 2006.281.07:56:03.90#ibcon#read 4, iclass 29, count 0 2006.281.07:56:03.90#ibcon#about to read 5, iclass 29, count 0 2006.281.07:56:03.90#ibcon#read 5, iclass 29, count 0 2006.281.07:56:03.90#ibcon#about to read 6, iclass 29, count 0 2006.281.07:56:03.90#ibcon#read 6, iclass 29, count 0 2006.281.07:56:03.90#ibcon#end of sib2, iclass 29, count 0 2006.281.07:56:03.90#ibcon#*mode == 0, iclass 29, count 0 2006.281.07:56:03.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.07:56:03.90#ibcon#[27=USB\r\n] 2006.281.07:56:03.90#ibcon#*before write, iclass 29, count 0 2006.281.07:56:03.90#ibcon#enter sib2, iclass 29, count 0 2006.281.07:56:03.90#ibcon#flushed, iclass 29, count 0 2006.281.07:56:03.90#ibcon#about to write, iclass 29, count 0 2006.281.07:56:03.90#ibcon#wrote, iclass 29, count 0 2006.281.07:56:03.90#ibcon#about to read 3, iclass 29, count 0 2006.281.07:56:03.93#ibcon#read 3, iclass 29, count 0 2006.281.07:56:03.93#ibcon#about to read 4, iclass 29, count 0 2006.281.07:56:03.93#ibcon#read 4, iclass 29, count 0 2006.281.07:56:03.93#ibcon#about to read 5, iclass 29, count 0 2006.281.07:56:03.93#ibcon#read 5, iclass 29, count 0 2006.281.07:56:03.93#ibcon#about to read 6, iclass 29, count 0 2006.281.07:56:03.93#ibcon#read 6, iclass 29, count 0 2006.281.07:56:03.93#ibcon#end of sib2, iclass 29, count 0 2006.281.07:56:03.93#ibcon#*after write, iclass 29, count 0 2006.281.07:56:03.93#ibcon#*before return 0, iclass 29, count 0 2006.281.07:56:03.93#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:03.93#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.07:56:03.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.07:56:03.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.07:56:03.93$vc4f8/vblo=5,744.99 2006.281.07:56:03.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.07:56:03.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.07:56:03.93#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:03.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:03.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:03.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:03.93#ibcon#enter wrdev, iclass 31, count 0 2006.281.07:56:03.93#ibcon#first serial, iclass 31, count 0 2006.281.07:56:03.93#ibcon#enter sib2, iclass 31, count 0 2006.281.07:56:03.93#ibcon#flushed, iclass 31, count 0 2006.281.07:56:03.93#ibcon#about to write, iclass 31, count 0 2006.281.07:56:03.93#ibcon#wrote, iclass 31, count 0 2006.281.07:56:03.93#ibcon#about to read 3, iclass 31, count 0 2006.281.07:56:03.95#ibcon#read 3, iclass 31, count 0 2006.281.07:56:03.95#ibcon#about to read 4, iclass 31, count 0 2006.281.07:56:03.95#ibcon#read 4, iclass 31, count 0 2006.281.07:56:03.95#ibcon#about to read 5, iclass 31, count 0 2006.281.07:56:03.95#ibcon#read 5, iclass 31, count 0 2006.281.07:56:03.95#ibcon#about to read 6, iclass 31, count 0 2006.281.07:56:03.95#ibcon#read 6, iclass 31, count 0 2006.281.07:56:03.95#ibcon#end of sib2, iclass 31, count 0 2006.281.07:56:03.95#ibcon#*mode == 0, iclass 31, count 0 2006.281.07:56:03.95#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.07:56:03.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:56:03.95#ibcon#*before write, iclass 31, count 0 2006.281.07:56:03.95#ibcon#enter sib2, iclass 31, count 0 2006.281.07:56:03.95#ibcon#flushed, iclass 31, count 0 2006.281.07:56:03.95#ibcon#about to write, iclass 31, count 0 2006.281.07:56:03.95#ibcon#wrote, iclass 31, count 0 2006.281.07:56:03.95#ibcon#about to read 3, iclass 31, count 0 2006.281.07:56:03.99#ibcon#read 3, iclass 31, count 0 2006.281.07:56:03.99#ibcon#about to read 4, iclass 31, count 0 2006.281.07:56:03.99#ibcon#read 4, iclass 31, count 0 2006.281.07:56:03.99#ibcon#about to read 5, iclass 31, count 0 2006.281.07:56:03.99#ibcon#read 5, iclass 31, count 0 2006.281.07:56:03.99#ibcon#about to read 6, iclass 31, count 0 2006.281.07:56:03.99#ibcon#read 6, iclass 31, count 0 2006.281.07:56:03.99#ibcon#end of sib2, iclass 31, count 0 2006.281.07:56:03.99#ibcon#*after write, iclass 31, count 0 2006.281.07:56:03.99#ibcon#*before return 0, iclass 31, count 0 2006.281.07:56:03.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:03.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.07:56:03.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.07:56:03.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.07:56:03.99$vc4f8/vb=5,4 2006.281.07:56:03.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.07:56:03.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.07:56:03.99#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:03.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:04.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:04.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:04.05#ibcon#enter wrdev, iclass 33, count 2 2006.281.07:56:04.05#ibcon#first serial, iclass 33, count 2 2006.281.07:56:04.05#ibcon#enter sib2, iclass 33, count 2 2006.281.07:56:04.05#ibcon#flushed, iclass 33, count 2 2006.281.07:56:04.05#ibcon#about to write, iclass 33, count 2 2006.281.07:56:04.05#ibcon#wrote, iclass 33, count 2 2006.281.07:56:04.05#ibcon#about to read 3, iclass 33, count 2 2006.281.07:56:04.07#ibcon#read 3, iclass 33, count 2 2006.281.07:56:04.07#ibcon#about to read 4, iclass 33, count 2 2006.281.07:56:04.07#ibcon#read 4, iclass 33, count 2 2006.281.07:56:04.07#ibcon#about to read 5, iclass 33, count 2 2006.281.07:56:04.07#ibcon#read 5, iclass 33, count 2 2006.281.07:56:04.07#ibcon#about to read 6, iclass 33, count 2 2006.281.07:56:04.07#ibcon#read 6, iclass 33, count 2 2006.281.07:56:04.07#ibcon#end of sib2, iclass 33, count 2 2006.281.07:56:04.07#ibcon#*mode == 0, iclass 33, count 2 2006.281.07:56:04.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.07:56:04.07#ibcon#[27=AT05-04\r\n] 2006.281.07:56:04.07#ibcon#*before write, iclass 33, count 2 2006.281.07:56:04.07#ibcon#enter sib2, iclass 33, count 2 2006.281.07:56:04.07#ibcon#flushed, iclass 33, count 2 2006.281.07:56:04.07#ibcon#about to write, iclass 33, count 2 2006.281.07:56:04.07#ibcon#wrote, iclass 33, count 2 2006.281.07:56:04.07#ibcon#about to read 3, iclass 33, count 2 2006.281.07:56:04.10#ibcon#read 3, iclass 33, count 2 2006.281.07:56:04.10#ibcon#about to read 4, iclass 33, count 2 2006.281.07:56:04.10#ibcon#read 4, iclass 33, count 2 2006.281.07:56:04.10#ibcon#about to read 5, iclass 33, count 2 2006.281.07:56:04.10#ibcon#read 5, iclass 33, count 2 2006.281.07:56:04.10#ibcon#about to read 6, iclass 33, count 2 2006.281.07:56:04.10#ibcon#read 6, iclass 33, count 2 2006.281.07:56:04.10#ibcon#end of sib2, iclass 33, count 2 2006.281.07:56:04.10#ibcon#*after write, iclass 33, count 2 2006.281.07:56:04.10#ibcon#*before return 0, iclass 33, count 2 2006.281.07:56:04.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:04.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.07:56:04.10#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.07:56:04.10#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:04.10#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:04.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:04.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:04.22#ibcon#enter wrdev, iclass 33, count 0 2006.281.07:56:04.22#ibcon#first serial, iclass 33, count 0 2006.281.07:56:04.22#ibcon#enter sib2, iclass 33, count 0 2006.281.07:56:04.22#ibcon#flushed, iclass 33, count 0 2006.281.07:56:04.22#ibcon#about to write, iclass 33, count 0 2006.281.07:56:04.22#ibcon#wrote, iclass 33, count 0 2006.281.07:56:04.22#ibcon#about to read 3, iclass 33, count 0 2006.281.07:56:04.24#ibcon#read 3, iclass 33, count 0 2006.281.07:56:04.24#ibcon#about to read 4, iclass 33, count 0 2006.281.07:56:04.24#ibcon#read 4, iclass 33, count 0 2006.281.07:56:04.24#ibcon#about to read 5, iclass 33, count 0 2006.281.07:56:04.24#ibcon#read 5, iclass 33, count 0 2006.281.07:56:04.24#ibcon#about to read 6, iclass 33, count 0 2006.281.07:56:04.24#ibcon#read 6, iclass 33, count 0 2006.281.07:56:04.24#ibcon#end of sib2, iclass 33, count 0 2006.281.07:56:04.24#ibcon#*mode == 0, iclass 33, count 0 2006.281.07:56:04.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.07:56:04.24#ibcon#[27=USB\r\n] 2006.281.07:56:04.24#ibcon#*before write, iclass 33, count 0 2006.281.07:56:04.24#ibcon#enter sib2, iclass 33, count 0 2006.281.07:56:04.24#ibcon#flushed, iclass 33, count 0 2006.281.07:56:04.24#ibcon#about to write, iclass 33, count 0 2006.281.07:56:04.24#ibcon#wrote, iclass 33, count 0 2006.281.07:56:04.24#ibcon#about to read 3, iclass 33, count 0 2006.281.07:56:04.27#ibcon#read 3, iclass 33, count 0 2006.281.07:56:04.27#ibcon#about to read 4, iclass 33, count 0 2006.281.07:56:04.27#ibcon#read 4, iclass 33, count 0 2006.281.07:56:04.27#ibcon#about to read 5, iclass 33, count 0 2006.281.07:56:04.27#ibcon#read 5, iclass 33, count 0 2006.281.07:56:04.27#ibcon#about to read 6, iclass 33, count 0 2006.281.07:56:04.27#ibcon#read 6, iclass 33, count 0 2006.281.07:56:04.27#ibcon#end of sib2, iclass 33, count 0 2006.281.07:56:04.27#ibcon#*after write, iclass 33, count 0 2006.281.07:56:04.27#ibcon#*before return 0, iclass 33, count 0 2006.281.07:56:04.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:04.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.07:56:04.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.07:56:04.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.07:56:04.27$vc4f8/vblo=6,752.99 2006.281.07:56:04.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.07:56:04.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.07:56:04.27#ibcon#ireg 17 cls_cnt 0 2006.281.07:56:04.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:04.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:04.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:04.27#ibcon#enter wrdev, iclass 35, count 0 2006.281.07:56:04.27#ibcon#first serial, iclass 35, count 0 2006.281.07:56:04.27#ibcon#enter sib2, iclass 35, count 0 2006.281.07:56:04.27#ibcon#flushed, iclass 35, count 0 2006.281.07:56:04.27#ibcon#about to write, iclass 35, count 0 2006.281.07:56:04.27#ibcon#wrote, iclass 35, count 0 2006.281.07:56:04.27#ibcon#about to read 3, iclass 35, count 0 2006.281.07:56:04.29#ibcon#read 3, iclass 35, count 0 2006.281.07:56:04.29#ibcon#about to read 4, iclass 35, count 0 2006.281.07:56:04.29#ibcon#read 4, iclass 35, count 0 2006.281.07:56:04.29#ibcon#about to read 5, iclass 35, count 0 2006.281.07:56:04.29#ibcon#read 5, iclass 35, count 0 2006.281.07:56:04.29#ibcon#about to read 6, iclass 35, count 0 2006.281.07:56:04.29#ibcon#read 6, iclass 35, count 0 2006.281.07:56:04.29#ibcon#end of sib2, iclass 35, count 0 2006.281.07:56:04.29#ibcon#*mode == 0, iclass 35, count 0 2006.281.07:56:04.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.07:56:04.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:56:04.29#ibcon#*before write, iclass 35, count 0 2006.281.07:56:04.29#ibcon#enter sib2, iclass 35, count 0 2006.281.07:56:04.29#ibcon#flushed, iclass 35, count 0 2006.281.07:56:04.29#ibcon#about to write, iclass 35, count 0 2006.281.07:56:04.29#ibcon#wrote, iclass 35, count 0 2006.281.07:56:04.29#ibcon#about to read 3, iclass 35, count 0 2006.281.07:56:04.33#ibcon#read 3, iclass 35, count 0 2006.281.07:56:04.33#ibcon#about to read 4, iclass 35, count 0 2006.281.07:56:04.33#ibcon#read 4, iclass 35, count 0 2006.281.07:56:04.33#ibcon#about to read 5, iclass 35, count 0 2006.281.07:56:04.33#ibcon#read 5, iclass 35, count 0 2006.281.07:56:04.33#ibcon#about to read 6, iclass 35, count 0 2006.281.07:56:04.33#ibcon#read 6, iclass 35, count 0 2006.281.07:56:04.33#ibcon#end of sib2, iclass 35, count 0 2006.281.07:56:04.33#ibcon#*after write, iclass 35, count 0 2006.281.07:56:04.33#ibcon#*before return 0, iclass 35, count 0 2006.281.07:56:04.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:04.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.07:56:04.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.07:56:04.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.07:56:04.33$vc4f8/vb=6,4 2006.281.07:56:04.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.07:56:04.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.07:56:04.33#ibcon#ireg 11 cls_cnt 2 2006.281.07:56:04.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:04.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:04.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:04.39#ibcon#enter wrdev, iclass 37, count 2 2006.281.07:56:04.39#ibcon#first serial, iclass 37, count 2 2006.281.07:56:04.39#ibcon#enter sib2, iclass 37, count 2 2006.281.07:56:04.39#ibcon#flushed, iclass 37, count 2 2006.281.07:56:04.39#ibcon#about to write, iclass 37, count 2 2006.281.07:56:04.39#ibcon#wrote, iclass 37, count 2 2006.281.07:56:04.39#ibcon#about to read 3, iclass 37, count 2 2006.281.07:56:04.41#ibcon#read 3, iclass 37, count 2 2006.281.07:56:04.41#ibcon#about to read 4, iclass 37, count 2 2006.281.07:56:04.41#ibcon#read 4, iclass 37, count 2 2006.281.07:56:04.41#ibcon#about to read 5, iclass 37, count 2 2006.281.07:56:04.41#ibcon#read 5, iclass 37, count 2 2006.281.07:56:04.41#ibcon#about to read 6, iclass 37, count 2 2006.281.07:56:04.41#ibcon#read 6, iclass 37, count 2 2006.281.07:56:04.41#ibcon#end of sib2, iclass 37, count 2 2006.281.07:56:04.41#ibcon#*mode == 0, iclass 37, count 2 2006.281.07:56:04.41#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.07:56:04.41#ibcon#[27=AT06-04\r\n] 2006.281.07:56:04.41#ibcon#*before write, iclass 37, count 2 2006.281.07:56:04.41#ibcon#enter sib2, iclass 37, count 2 2006.281.07:56:04.41#ibcon#flushed, iclass 37, count 2 2006.281.07:56:04.41#ibcon#about to write, iclass 37, count 2 2006.281.07:56:04.41#ibcon#wrote, iclass 37, count 2 2006.281.07:56:04.41#ibcon#about to read 3, iclass 37, count 2 2006.281.07:56:04.44#ibcon#read 3, iclass 37, count 2 2006.281.07:56:04.44#ibcon#about to read 4, iclass 37, count 2 2006.281.07:56:04.44#ibcon#read 4, iclass 37, count 2 2006.281.07:56:04.44#ibcon#about to read 5, iclass 37, count 2 2006.281.07:56:04.44#ibcon#read 5, iclass 37, count 2 2006.281.07:56:04.44#ibcon#about to read 6, iclass 37, count 2 2006.281.07:56:04.44#ibcon#read 6, iclass 37, count 2 2006.281.07:56:04.44#ibcon#end of sib2, iclass 37, count 2 2006.281.07:56:04.44#ibcon#*after write, iclass 37, count 2 2006.281.07:56:04.44#ibcon#*before return 0, iclass 37, count 2 2006.281.07:56:04.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:04.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.07:56:04.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.07:56:04.44#ibcon#ireg 7 cls_cnt 0 2006.281.07:56:04.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:04.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:04.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:04.56#ibcon#enter wrdev, iclass 37, count 0 2006.281.07:56:04.56#ibcon#first serial, iclass 37, count 0 2006.281.07:56:04.56#ibcon#enter sib2, iclass 37, count 0 2006.281.07:56:04.56#ibcon#flushed, iclass 37, count 0 2006.281.07:56:04.56#ibcon#about to write, iclass 37, count 0 2006.281.07:56:04.56#ibcon#wrote, iclass 37, count 0 2006.281.07:56:04.56#ibcon#about to read 3, iclass 37, count 0 2006.281.07:56:04.58#ibcon#read 3, iclass 37, count 0 2006.281.07:56:04.58#ibcon#about to read 4, iclass 37, count 0 2006.281.07:56:04.58#ibcon#read 4, iclass 37, count 0 2006.281.07:56:04.58#ibcon#about to read 5, iclass 37, count 0 2006.281.07:56:04.58#ibcon#read 5, iclass 37, count 0 2006.281.07:56:04.58#ibcon#about to read 6, iclass 37, count 0 2006.281.07:56:04.58#ibcon#read 6, iclass 37, count 0 2006.281.07:56:04.58#ibcon#end of sib2, iclass 37, count 0 2006.281.07:56:04.58#ibcon#*mode == 0, iclass 37, count 0 2006.281.07:56:04.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.07:56:04.58#ibcon#[27=USB\r\n] 2006.281.07:56:04.58#ibcon#*before write, iclass 37, count 0 2006.281.07:56:04.58#ibcon#enter sib2, iclass 37, count 0 2006.281.07:56:04.58#ibcon#flushed, iclass 37, count 0 2006.281.07:56:04.58#ibcon#about to write, iclass 37, count 0 2006.281.07:56:04.58#ibcon#wrote, iclass 37, count 0 2006.281.07:56:04.58#ibcon#about to read 3, iclass 37, count 0 2006.281.07:56:04.61#ibcon#read 3, iclass 37, count 0 2006.281.07:56:04.61#ibcon#about to read 4, iclass 37, count 0 2006.281.07:56:04.61#ibcon#read 4, iclass 37, count 0 2006.281.07:56:04.61#ibcon#about to read 5, iclass 37, count 0 2006.281.07:56:04.61#ibcon#read 5, iclass 37, count 0 2006.281.07:56:04.61#ibcon#about to read 6, iclass 37, count 0 2006.281.07:56:04.61#ibcon#read 6, iclass 37, count 0 2006.281.07:56:04.61#ibcon#end of sib2, iclass 37, count 0 2006.281.07:56:04.61#ibcon#*after write, iclass 37, count 0 2006.281.07:56:04.61#ibcon#*before return 0, iclass 37, count 0 2006.281.07:56:04.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:04.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.07:56:04.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.07:56:04.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.07:56:04.61$vc4f8/vabw=wide 2006.281.07:56:04.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.07:56:04.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.07:56:04.61#ibcon#ireg 8 cls_cnt 0 2006.281.07:56:04.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:04.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:04.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:04.61#ibcon#enter wrdev, iclass 39, count 0 2006.281.07:56:04.61#ibcon#first serial, iclass 39, count 0 2006.281.07:56:04.61#ibcon#enter sib2, iclass 39, count 0 2006.281.07:56:04.61#ibcon#flushed, iclass 39, count 0 2006.281.07:56:04.61#ibcon#about to write, iclass 39, count 0 2006.281.07:56:04.61#ibcon#wrote, iclass 39, count 0 2006.281.07:56:04.61#ibcon#about to read 3, iclass 39, count 0 2006.281.07:56:04.63#ibcon#read 3, iclass 39, count 0 2006.281.07:56:04.63#ibcon#about to read 4, iclass 39, count 0 2006.281.07:56:04.63#ibcon#read 4, iclass 39, count 0 2006.281.07:56:04.63#ibcon#about to read 5, iclass 39, count 0 2006.281.07:56:04.63#ibcon#read 5, iclass 39, count 0 2006.281.07:56:04.63#ibcon#about to read 6, iclass 39, count 0 2006.281.07:56:04.63#ibcon#read 6, iclass 39, count 0 2006.281.07:56:04.63#ibcon#end of sib2, iclass 39, count 0 2006.281.07:56:04.63#ibcon#*mode == 0, iclass 39, count 0 2006.281.07:56:04.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.07:56:04.63#ibcon#[25=BW32\r\n] 2006.281.07:56:04.63#ibcon#*before write, iclass 39, count 0 2006.281.07:56:04.63#ibcon#enter sib2, iclass 39, count 0 2006.281.07:56:04.63#ibcon#flushed, iclass 39, count 0 2006.281.07:56:04.63#ibcon#about to write, iclass 39, count 0 2006.281.07:56:04.63#ibcon#wrote, iclass 39, count 0 2006.281.07:56:04.63#ibcon#about to read 3, iclass 39, count 0 2006.281.07:56:04.66#ibcon#read 3, iclass 39, count 0 2006.281.07:56:04.66#ibcon#about to read 4, iclass 39, count 0 2006.281.07:56:04.66#ibcon#read 4, iclass 39, count 0 2006.281.07:56:04.66#ibcon#about to read 5, iclass 39, count 0 2006.281.07:56:04.66#ibcon#read 5, iclass 39, count 0 2006.281.07:56:04.66#ibcon#about to read 6, iclass 39, count 0 2006.281.07:56:04.66#ibcon#read 6, iclass 39, count 0 2006.281.07:56:04.66#ibcon#end of sib2, iclass 39, count 0 2006.281.07:56:04.66#ibcon#*after write, iclass 39, count 0 2006.281.07:56:04.66#ibcon#*before return 0, iclass 39, count 0 2006.281.07:56:04.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:04.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.07:56:04.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.07:56:04.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.07:56:04.66$vc4f8/vbbw=wide 2006.281.07:56:04.68#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.07:56:04.68#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.07:56:04.68#ibcon#ireg 8 cls_cnt 0 2006.281.07:56:04.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:56:04.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:56:04.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:56:04.73#ibcon#enter wrdev, iclass 3, count 0 2006.281.07:56:04.73#ibcon#first serial, iclass 3, count 0 2006.281.07:56:04.73#ibcon#enter sib2, iclass 3, count 0 2006.281.07:56:04.73#ibcon#flushed, iclass 3, count 0 2006.281.07:56:04.73#ibcon#about to write, iclass 3, count 0 2006.281.07:56:04.73#ibcon#wrote, iclass 3, count 0 2006.281.07:56:04.73#ibcon#about to read 3, iclass 3, count 0 2006.281.07:56:04.75#ibcon#read 3, iclass 3, count 0 2006.281.07:56:04.75#ibcon#about to read 4, iclass 3, count 0 2006.281.07:56:04.75#ibcon#read 4, iclass 3, count 0 2006.281.07:56:04.75#ibcon#about to read 5, iclass 3, count 0 2006.281.07:56:04.75#ibcon#read 5, iclass 3, count 0 2006.281.07:56:04.75#ibcon#about to read 6, iclass 3, count 0 2006.281.07:56:04.75#ibcon#read 6, iclass 3, count 0 2006.281.07:56:04.75#ibcon#end of sib2, iclass 3, count 0 2006.281.07:56:04.75#ibcon#*mode == 0, iclass 3, count 0 2006.281.07:56:04.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.07:56:04.75#ibcon#[27=BW32\r\n] 2006.281.07:56:04.75#ibcon#*before write, iclass 3, count 0 2006.281.07:56:04.75#ibcon#enter sib2, iclass 3, count 0 2006.281.07:56:04.75#ibcon#flushed, iclass 3, count 0 2006.281.07:56:04.75#ibcon#about to write, iclass 3, count 0 2006.281.07:56:04.75#ibcon#wrote, iclass 3, count 0 2006.281.07:56:04.75#ibcon#about to read 3, iclass 3, count 0 2006.281.07:56:04.78#ibcon#read 3, iclass 3, count 0 2006.281.07:56:04.78#ibcon#about to read 4, iclass 3, count 0 2006.281.07:56:04.78#ibcon#read 4, iclass 3, count 0 2006.281.07:56:04.78#ibcon#about to read 5, iclass 3, count 0 2006.281.07:56:04.78#ibcon#read 5, iclass 3, count 0 2006.281.07:56:04.78#ibcon#about to read 6, iclass 3, count 0 2006.281.07:56:04.78#ibcon#read 6, iclass 3, count 0 2006.281.07:56:04.78#ibcon#end of sib2, iclass 3, count 0 2006.281.07:56:04.78#ibcon#*after write, iclass 3, count 0 2006.281.07:56:04.78#ibcon#*before return 0, iclass 3, count 0 2006.281.07:56:04.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:56:04.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.07:56:04.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.07:56:04.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.07:56:04.78$4f8m12a/ifd4f 2006.281.07:56:04.78$ifd4f/lo= 2006.281.07:56:04.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:56:04.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:56:04.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:56:04.79$ifd4f/patch= 2006.281.07:56:04.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:56:04.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:56:04.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:56:04.79$4f8m12a/"form=m,16.000,1:2 2006.281.07:56:04.79$4f8m12a/"tpicd 2006.281.07:56:04.79$4f8m12a/echo=off 2006.281.07:56:04.79$4f8m12a/xlog=off 2006.281.07:56:04.79:!2006.281.07:58:10 2006.281.07:56:31.14#trakl#Source acquired 2006.281.07:56:33.14#flagr#flagr/antenna,acquired 2006.281.07:56:44.14#trakl#Off source 2006.281.07:56:44.14?ERROR st -7 Antenna off-source! 2006.281.07:56:44.14#trakl#az 308.397 el 12.665 azerr*cos(el) 0.0035 elerr 0.0162 2006.281.07:56:45.14#flagr#flagr/antenna,off-source 2006.281.07:56:58.14#trakl#Source re-acquired 2006.281.07:57:00.14#flagr#flagr/antenna,re-acquired 2006.281.07:57:48.13#trakl#Off source 2006.281.07:57:48.13?ERROR st -7 Antenna off-source! 2006.281.07:57:48.13#trakl#az 308.525 el 12.497 azerr*cos(el) 0.0107 elerr -0.0237 2006.281.07:57:48.13#flagr#flagr/antenna,off-source 2006.281.07:57:54.13#trakl#Source re-acquired 2006.281.07:57:54.13#flagr#flagr/antenna,re-acquired 2006.281.07:58:10.01:preob 2006.281.07:58:11.13/onsource/TRACKING 2006.281.07:58:11.13:!2006.281.07:58:20 2006.281.07:58:20.00:data_valid=on 2006.281.07:58:20.00:midob 2006.281.07:58:20.13/onsource/TRACKING 2006.281.07:58:20.13/wx/20.58,1001.3,51 2006.281.07:58:20.23/cable/+6.4868E-03 2006.281.07:58:21.32/va/01,07,usb,yes,48,50 2006.281.07:58:21.32/va/02,06,usb,yes,44,46 2006.281.07:58:21.32/va/03,06,usb,yes,41,41 2006.281.07:58:21.32/va/04,06,usb,yes,45,48 2006.281.07:58:21.32/va/05,07,usb,yes,43,46 2006.281.07:58:21.32/va/06,06,usb,yes,42,42 2006.281.07:58:21.32/va/07,06,usb,yes,42,42 2006.281.07:58:21.32/va/08,06,usb,yes,44,44 2006.281.07:58:21.55/valo/01,532.99,yes,locked 2006.281.07:58:21.55/valo/02,572.99,yes,locked 2006.281.07:58:21.55/valo/03,672.99,yes,locked 2006.281.07:58:21.55/valo/04,832.99,yes,locked 2006.281.07:58:21.55/valo/05,652.99,yes,locked 2006.281.07:58:21.55/valo/06,772.99,yes,locked 2006.281.07:58:21.55/valo/07,832.99,yes,locked 2006.281.07:58:21.55/valo/08,852.99,yes,locked 2006.281.07:58:22.64/vb/01,04,usb,yes,38,36 2006.281.07:58:22.64/vb/02,05,usb,yes,36,37 2006.281.07:58:22.64/vb/03,04,usb,yes,36,41 2006.281.07:58:22.64/vb/04,04,usb,yes,37,38 2006.281.07:58:22.64/vb/05,04,usb,yes,35,40 2006.281.07:58:22.64/vb/06,04,usb,yes,35,40 2006.281.07:58:22.64/vb/07,04,usb,yes,39,39 2006.281.07:58:22.64/vb/08,04,usb,yes,35,40 2006.281.07:58:22.87/vblo/01,632.99,yes,locked 2006.281.07:58:22.87/vblo/02,640.99,yes,locked 2006.281.07:58:22.87/vblo/03,656.99,yes,locked 2006.281.07:58:22.87/vblo/04,712.99,yes,locked 2006.281.07:58:22.87/vblo/05,744.99,yes,locked 2006.281.07:58:22.87/vblo/06,752.99,yes,locked 2006.281.07:58:22.87/vblo/07,734.99,yes,locked 2006.281.07:58:22.87/vblo/08,744.99,yes,locked 2006.281.07:58:23.02/vabw/8 2006.281.07:58:23.17/vbbw/8 2006.281.07:58:23.26/xfe/off,on,12.0 2006.281.07:58:23.64/ifatt/23,28,28,28 2006.281.07:58:24.07/fmout-gps/S +3.06E-07 2006.281.07:58:24.09:!2006.281.07:59:20 2006.281.07:58:24.13#trakl#Off source 2006.281.07:58:24.13?ERROR st -7 Antenna off-source! 2006.281.07:58:24.13#trakl#az 308.597 el 12.402 azerr*cos(el) 0.0048 elerr -0.0193 2006.281.07:58:24.13#flagr#flagr/antenna,off-source 2006.281.07:58:30.13#trakl#Source re-acquired 2006.281.07:58:30.13#flagr#flagr/antenna,re-acquired 2006.281.07:58:36.13#trakl#Off source 2006.281.07:58:36.13?ERROR st -7 Antenna off-source! 2006.281.07:58:36.13#trakl#az 308.621 el 12.371 azerr*cos(el) -0.0020 elerr -0.0199 2006.281.07:58:36.13#flagr#flagr/antenna,off-source 2006.281.07:58:42.13#trakl#Source re-acquired 2006.281.07:58:42.13#flagr#flagr/antenna,re-acquired 2006.281.07:59:20.01:data_valid=off 2006.281.07:59:20.01:postob 2006.281.07:59:20.15/cable/+6.4876E-03 2006.281.07:59:20.15/wx/20.55,1001.3,51 2006.281.07:59:21.08/fmout-gps/S +3.10E-07 2006.281.07:59:21.08:scan_name=281-0800,k06281,60 2006.281.07:59:21.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.281.07:59:22.13#flagr#flagr/antenna,new-source 2006.281.07:59:22.13:checkk5 2006.281.07:59:22.56/chk_autoobs//k5ts1/ autoobs is running! 2006.281.07:59:22.95/chk_autoobs//k5ts2/ autoobs is running! 2006.281.07:59:23.37/chk_autoobs//k5ts3/ autoobs is running! 2006.281.07:59:23.80/chk_autoobs//k5ts4/ autoobs is running! 2006.281.07:59:24.18/chk_obsdata//k5ts1/T2810758??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:59:24.84/chk_obsdata//k5ts2/T2810758??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:59:25.21/chk_obsdata//k5ts3/T2810758??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:59:25.65/chk_obsdata//k5ts4/T2810758??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.07:59:26.48/k5log//k5ts1_log_newline 2006.281.07:59:27.50/k5log//k5ts2_log_newline 2006.281.07:59:28.28/k5log//k5ts3_log_newline 2006.281.07:59:29.04/k5log//k5ts4_log_newline 2006.281.07:59:29.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.07:59:29.09:4f8m12a=2 2006.281.07:59:29.10$4f8m12a/echo=on 2006.281.07:59:29.10$4f8m12a/pcalon 2006.281.07:59:29.10$pcalon/"no phase cal control is implemented here 2006.281.07:59:29.10$4f8m12a/"tpicd=stop 2006.281.07:59:29.10$4f8m12a/vc4f8 2006.281.07:59:29.10$vc4f8/valo=1,532.99 2006.281.07:59:29.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:59:29.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:59:29.10#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:29.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:29.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:29.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:29.10#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:59:29.10#ibcon#first serial, iclass 24, count 0 2006.281.07:59:29.10#ibcon#enter sib2, iclass 24, count 0 2006.281.07:59:29.10#ibcon#flushed, iclass 24, count 0 2006.281.07:59:29.10#ibcon#about to write, iclass 24, count 0 2006.281.07:59:29.10#ibcon#wrote, iclass 24, count 0 2006.281.07:59:29.10#ibcon#about to read 3, iclass 24, count 0 2006.281.07:59:29.12#ibcon#read 3, iclass 24, count 0 2006.281.07:59:29.12#ibcon#about to read 4, iclass 24, count 0 2006.281.07:59:29.12#ibcon#read 4, iclass 24, count 0 2006.281.07:59:29.12#ibcon#about to read 5, iclass 24, count 0 2006.281.07:59:29.12#ibcon#read 5, iclass 24, count 0 2006.281.07:59:29.12#ibcon#about to read 6, iclass 24, count 0 2006.281.07:59:29.12#ibcon#read 6, iclass 24, count 0 2006.281.07:59:29.12#ibcon#end of sib2, iclass 24, count 0 2006.281.07:59:29.12#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:59:29.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:59:29.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.07:59:29.12#ibcon#*before write, iclass 24, count 0 2006.281.07:59:29.12#ibcon#enter sib2, iclass 24, count 0 2006.281.07:59:29.12#ibcon#flushed, iclass 24, count 0 2006.281.07:59:29.12#ibcon#about to write, iclass 24, count 0 2006.281.07:59:29.12#ibcon#wrote, iclass 24, count 0 2006.281.07:59:29.12#ibcon#about to read 3, iclass 24, count 0 2006.281.07:59:29.17#ibcon#read 3, iclass 24, count 0 2006.281.07:59:29.17#ibcon#about to read 4, iclass 24, count 0 2006.281.07:59:29.17#ibcon#read 4, iclass 24, count 0 2006.281.07:59:29.17#ibcon#about to read 5, iclass 24, count 0 2006.281.07:59:29.17#ibcon#read 5, iclass 24, count 0 2006.281.07:59:29.17#ibcon#about to read 6, iclass 24, count 0 2006.281.07:59:29.17#ibcon#read 6, iclass 24, count 0 2006.281.07:59:29.17#ibcon#end of sib2, iclass 24, count 0 2006.281.07:59:29.17#ibcon#*after write, iclass 24, count 0 2006.281.07:59:29.17#ibcon#*before return 0, iclass 24, count 0 2006.281.07:59:29.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:29.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:29.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:59:29.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:59:29.17$vc4f8/va=1,7 2006.281.07:59:29.17#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:59:29.17#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:59:29.17#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:29.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:29.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:29.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:29.17#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:59:29.17#ibcon#first serial, iclass 26, count 2 2006.281.07:59:29.17#ibcon#enter sib2, iclass 26, count 2 2006.281.07:59:29.17#ibcon#flushed, iclass 26, count 2 2006.281.07:59:29.17#ibcon#about to write, iclass 26, count 2 2006.281.07:59:29.17#ibcon#wrote, iclass 26, count 2 2006.281.07:59:29.17#ibcon#about to read 3, iclass 26, count 2 2006.281.07:59:29.19#ibcon#read 3, iclass 26, count 2 2006.281.07:59:29.19#ibcon#about to read 4, iclass 26, count 2 2006.281.07:59:29.19#ibcon#read 4, iclass 26, count 2 2006.281.07:59:29.19#ibcon#about to read 5, iclass 26, count 2 2006.281.07:59:29.19#ibcon#read 5, iclass 26, count 2 2006.281.07:59:29.19#ibcon#about to read 6, iclass 26, count 2 2006.281.07:59:29.19#ibcon#read 6, iclass 26, count 2 2006.281.07:59:29.19#ibcon#end of sib2, iclass 26, count 2 2006.281.07:59:29.19#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:59:29.19#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:59:29.19#ibcon#[25=AT01-07\r\n] 2006.281.07:59:29.19#ibcon#*before write, iclass 26, count 2 2006.281.07:59:29.19#ibcon#enter sib2, iclass 26, count 2 2006.281.07:59:29.19#ibcon#flushed, iclass 26, count 2 2006.281.07:59:29.19#ibcon#about to write, iclass 26, count 2 2006.281.07:59:29.19#ibcon#wrote, iclass 26, count 2 2006.281.07:59:29.19#ibcon#about to read 3, iclass 26, count 2 2006.281.07:59:29.22#ibcon#read 3, iclass 26, count 2 2006.281.07:59:29.22#ibcon#about to read 4, iclass 26, count 2 2006.281.07:59:29.22#ibcon#read 4, iclass 26, count 2 2006.281.07:59:29.22#ibcon#about to read 5, iclass 26, count 2 2006.281.07:59:29.22#ibcon#read 5, iclass 26, count 2 2006.281.07:59:29.22#ibcon#about to read 6, iclass 26, count 2 2006.281.07:59:29.22#ibcon#read 6, iclass 26, count 2 2006.281.07:59:29.22#ibcon#end of sib2, iclass 26, count 2 2006.281.07:59:29.22#ibcon#*after write, iclass 26, count 2 2006.281.07:59:29.22#ibcon#*before return 0, iclass 26, count 2 2006.281.07:59:29.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:29.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:29.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:59:29.22#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:29.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:29.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:29.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:29.34#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:59:29.34#ibcon#first serial, iclass 26, count 0 2006.281.07:59:29.34#ibcon#enter sib2, iclass 26, count 0 2006.281.07:59:29.34#ibcon#flushed, iclass 26, count 0 2006.281.07:59:29.34#ibcon#about to write, iclass 26, count 0 2006.281.07:59:29.34#ibcon#wrote, iclass 26, count 0 2006.281.07:59:29.34#ibcon#about to read 3, iclass 26, count 0 2006.281.07:59:29.36#ibcon#read 3, iclass 26, count 0 2006.281.07:59:29.36#ibcon#about to read 4, iclass 26, count 0 2006.281.07:59:29.36#ibcon#read 4, iclass 26, count 0 2006.281.07:59:29.36#ibcon#about to read 5, iclass 26, count 0 2006.281.07:59:29.36#ibcon#read 5, iclass 26, count 0 2006.281.07:59:29.36#ibcon#about to read 6, iclass 26, count 0 2006.281.07:59:29.36#ibcon#read 6, iclass 26, count 0 2006.281.07:59:29.36#ibcon#end of sib2, iclass 26, count 0 2006.281.07:59:29.36#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:59:29.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:59:29.36#ibcon#[25=USB\r\n] 2006.281.07:59:29.36#ibcon#*before write, iclass 26, count 0 2006.281.07:59:29.36#ibcon#enter sib2, iclass 26, count 0 2006.281.07:59:29.36#ibcon#flushed, iclass 26, count 0 2006.281.07:59:29.36#ibcon#about to write, iclass 26, count 0 2006.281.07:59:29.36#ibcon#wrote, iclass 26, count 0 2006.281.07:59:29.36#ibcon#about to read 3, iclass 26, count 0 2006.281.07:59:29.39#ibcon#read 3, iclass 26, count 0 2006.281.07:59:29.39#ibcon#about to read 4, iclass 26, count 0 2006.281.07:59:29.39#ibcon#read 4, iclass 26, count 0 2006.281.07:59:29.39#ibcon#about to read 5, iclass 26, count 0 2006.281.07:59:29.39#ibcon#read 5, iclass 26, count 0 2006.281.07:59:29.39#ibcon#about to read 6, iclass 26, count 0 2006.281.07:59:29.39#ibcon#read 6, iclass 26, count 0 2006.281.07:59:29.39#ibcon#end of sib2, iclass 26, count 0 2006.281.07:59:29.39#ibcon#*after write, iclass 26, count 0 2006.281.07:59:29.39#ibcon#*before return 0, iclass 26, count 0 2006.281.07:59:29.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:29.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:29.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:59:29.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:59:29.39$vc4f8/valo=2,572.99 2006.281.07:59:29.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:59:29.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:59:29.39#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:29.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:29.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:29.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:29.39#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:59:29.39#ibcon#first serial, iclass 28, count 0 2006.281.07:59:29.39#ibcon#enter sib2, iclass 28, count 0 2006.281.07:59:29.39#ibcon#flushed, iclass 28, count 0 2006.281.07:59:29.39#ibcon#about to write, iclass 28, count 0 2006.281.07:59:29.39#ibcon#wrote, iclass 28, count 0 2006.281.07:59:29.39#ibcon#about to read 3, iclass 28, count 0 2006.281.07:59:29.41#ibcon#read 3, iclass 28, count 0 2006.281.07:59:29.41#ibcon#about to read 4, iclass 28, count 0 2006.281.07:59:29.41#ibcon#read 4, iclass 28, count 0 2006.281.07:59:29.41#ibcon#about to read 5, iclass 28, count 0 2006.281.07:59:29.41#ibcon#read 5, iclass 28, count 0 2006.281.07:59:29.41#ibcon#about to read 6, iclass 28, count 0 2006.281.07:59:29.41#ibcon#read 6, iclass 28, count 0 2006.281.07:59:29.41#ibcon#end of sib2, iclass 28, count 0 2006.281.07:59:29.41#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:59:29.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:59:29.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.07:59:29.41#ibcon#*before write, iclass 28, count 0 2006.281.07:59:29.41#ibcon#enter sib2, iclass 28, count 0 2006.281.07:59:29.41#ibcon#flushed, iclass 28, count 0 2006.281.07:59:29.41#ibcon#about to write, iclass 28, count 0 2006.281.07:59:29.41#ibcon#wrote, iclass 28, count 0 2006.281.07:59:29.41#ibcon#about to read 3, iclass 28, count 0 2006.281.07:59:29.45#ibcon#read 3, iclass 28, count 0 2006.281.07:59:29.45#ibcon#about to read 4, iclass 28, count 0 2006.281.07:59:29.45#ibcon#read 4, iclass 28, count 0 2006.281.07:59:29.45#ibcon#about to read 5, iclass 28, count 0 2006.281.07:59:29.45#ibcon#read 5, iclass 28, count 0 2006.281.07:59:29.45#ibcon#about to read 6, iclass 28, count 0 2006.281.07:59:29.45#ibcon#read 6, iclass 28, count 0 2006.281.07:59:29.45#ibcon#end of sib2, iclass 28, count 0 2006.281.07:59:29.45#ibcon#*after write, iclass 28, count 0 2006.281.07:59:29.45#ibcon#*before return 0, iclass 28, count 0 2006.281.07:59:29.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:29.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:29.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:59:29.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:59:29.45$vc4f8/va=2,6 2006.281.07:59:29.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:59:29.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:59:29.45#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:29.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:29.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:29.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:29.51#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:59:29.51#ibcon#first serial, iclass 30, count 2 2006.281.07:59:29.51#ibcon#enter sib2, iclass 30, count 2 2006.281.07:59:29.51#ibcon#flushed, iclass 30, count 2 2006.281.07:59:29.51#ibcon#about to write, iclass 30, count 2 2006.281.07:59:29.51#ibcon#wrote, iclass 30, count 2 2006.281.07:59:29.51#ibcon#about to read 3, iclass 30, count 2 2006.281.07:59:29.53#ibcon#read 3, iclass 30, count 2 2006.281.07:59:29.53#ibcon#about to read 4, iclass 30, count 2 2006.281.07:59:29.53#ibcon#read 4, iclass 30, count 2 2006.281.07:59:29.53#ibcon#about to read 5, iclass 30, count 2 2006.281.07:59:29.53#ibcon#read 5, iclass 30, count 2 2006.281.07:59:29.53#ibcon#about to read 6, iclass 30, count 2 2006.281.07:59:29.53#ibcon#read 6, iclass 30, count 2 2006.281.07:59:29.53#ibcon#end of sib2, iclass 30, count 2 2006.281.07:59:29.53#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:59:29.53#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:59:29.53#ibcon#[25=AT02-06\r\n] 2006.281.07:59:29.53#ibcon#*before write, iclass 30, count 2 2006.281.07:59:29.53#ibcon#enter sib2, iclass 30, count 2 2006.281.07:59:29.53#ibcon#flushed, iclass 30, count 2 2006.281.07:59:29.53#ibcon#about to write, iclass 30, count 2 2006.281.07:59:29.53#ibcon#wrote, iclass 30, count 2 2006.281.07:59:29.53#ibcon#about to read 3, iclass 30, count 2 2006.281.07:59:29.56#ibcon#read 3, iclass 30, count 2 2006.281.07:59:29.56#ibcon#about to read 4, iclass 30, count 2 2006.281.07:59:29.56#ibcon#read 4, iclass 30, count 2 2006.281.07:59:29.56#ibcon#about to read 5, iclass 30, count 2 2006.281.07:59:29.56#ibcon#read 5, iclass 30, count 2 2006.281.07:59:29.56#ibcon#about to read 6, iclass 30, count 2 2006.281.07:59:29.56#ibcon#read 6, iclass 30, count 2 2006.281.07:59:29.56#ibcon#end of sib2, iclass 30, count 2 2006.281.07:59:29.56#ibcon#*after write, iclass 30, count 2 2006.281.07:59:29.56#ibcon#*before return 0, iclass 30, count 2 2006.281.07:59:29.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:29.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:29.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:59:29.56#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:29.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:29.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:29.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:29.68#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:59:29.68#ibcon#first serial, iclass 30, count 0 2006.281.07:59:29.68#ibcon#enter sib2, iclass 30, count 0 2006.281.07:59:29.68#ibcon#flushed, iclass 30, count 0 2006.281.07:59:29.68#ibcon#about to write, iclass 30, count 0 2006.281.07:59:29.68#ibcon#wrote, iclass 30, count 0 2006.281.07:59:29.68#ibcon#about to read 3, iclass 30, count 0 2006.281.07:59:29.70#ibcon#read 3, iclass 30, count 0 2006.281.07:59:29.70#ibcon#about to read 4, iclass 30, count 0 2006.281.07:59:29.70#ibcon#read 4, iclass 30, count 0 2006.281.07:59:29.70#ibcon#about to read 5, iclass 30, count 0 2006.281.07:59:29.70#ibcon#read 5, iclass 30, count 0 2006.281.07:59:29.70#ibcon#about to read 6, iclass 30, count 0 2006.281.07:59:29.70#ibcon#read 6, iclass 30, count 0 2006.281.07:59:29.70#ibcon#end of sib2, iclass 30, count 0 2006.281.07:59:29.70#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:59:29.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:59:29.70#ibcon#[25=USB\r\n] 2006.281.07:59:29.70#ibcon#*before write, iclass 30, count 0 2006.281.07:59:29.70#ibcon#enter sib2, iclass 30, count 0 2006.281.07:59:29.70#ibcon#flushed, iclass 30, count 0 2006.281.07:59:29.70#ibcon#about to write, iclass 30, count 0 2006.281.07:59:29.70#ibcon#wrote, iclass 30, count 0 2006.281.07:59:29.70#ibcon#about to read 3, iclass 30, count 0 2006.281.07:59:29.73#ibcon#read 3, iclass 30, count 0 2006.281.07:59:29.73#ibcon#about to read 4, iclass 30, count 0 2006.281.07:59:29.73#ibcon#read 4, iclass 30, count 0 2006.281.07:59:29.73#ibcon#about to read 5, iclass 30, count 0 2006.281.07:59:29.73#ibcon#read 5, iclass 30, count 0 2006.281.07:59:29.73#ibcon#about to read 6, iclass 30, count 0 2006.281.07:59:29.73#ibcon#read 6, iclass 30, count 0 2006.281.07:59:29.73#ibcon#end of sib2, iclass 30, count 0 2006.281.07:59:29.73#ibcon#*after write, iclass 30, count 0 2006.281.07:59:29.73#ibcon#*before return 0, iclass 30, count 0 2006.281.07:59:29.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:29.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:29.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:59:29.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:59:29.73$vc4f8/valo=3,672.99 2006.281.07:59:29.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:59:29.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:59:29.73#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:29.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:29.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:29.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:29.73#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:59:29.73#ibcon#first serial, iclass 32, count 0 2006.281.07:59:29.73#ibcon#enter sib2, iclass 32, count 0 2006.281.07:59:29.73#ibcon#flushed, iclass 32, count 0 2006.281.07:59:29.73#ibcon#about to write, iclass 32, count 0 2006.281.07:59:29.73#ibcon#wrote, iclass 32, count 0 2006.281.07:59:29.73#ibcon#about to read 3, iclass 32, count 0 2006.281.07:59:29.75#ibcon#read 3, iclass 32, count 0 2006.281.07:59:29.75#ibcon#about to read 4, iclass 32, count 0 2006.281.07:59:29.75#ibcon#read 4, iclass 32, count 0 2006.281.07:59:29.75#ibcon#about to read 5, iclass 32, count 0 2006.281.07:59:29.75#ibcon#read 5, iclass 32, count 0 2006.281.07:59:29.75#ibcon#about to read 6, iclass 32, count 0 2006.281.07:59:29.75#ibcon#read 6, iclass 32, count 0 2006.281.07:59:29.75#ibcon#end of sib2, iclass 32, count 0 2006.281.07:59:29.75#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:59:29.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:59:29.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.07:59:29.75#ibcon#*before write, iclass 32, count 0 2006.281.07:59:29.75#ibcon#enter sib2, iclass 32, count 0 2006.281.07:59:29.75#ibcon#flushed, iclass 32, count 0 2006.281.07:59:29.75#ibcon#about to write, iclass 32, count 0 2006.281.07:59:29.75#ibcon#wrote, iclass 32, count 0 2006.281.07:59:29.75#ibcon#about to read 3, iclass 32, count 0 2006.281.07:59:29.79#ibcon#read 3, iclass 32, count 0 2006.281.07:59:29.79#ibcon#about to read 4, iclass 32, count 0 2006.281.07:59:29.79#ibcon#read 4, iclass 32, count 0 2006.281.07:59:29.79#ibcon#about to read 5, iclass 32, count 0 2006.281.07:59:29.79#ibcon#read 5, iclass 32, count 0 2006.281.07:59:29.79#ibcon#about to read 6, iclass 32, count 0 2006.281.07:59:29.79#ibcon#read 6, iclass 32, count 0 2006.281.07:59:29.79#ibcon#end of sib2, iclass 32, count 0 2006.281.07:59:29.79#ibcon#*after write, iclass 32, count 0 2006.281.07:59:29.79#ibcon#*before return 0, iclass 32, count 0 2006.281.07:59:29.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:29.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:29.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:59:29.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:59:29.79$vc4f8/va=3,6 2006.281.07:59:29.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:59:29.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:59:29.79#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:29.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:29.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:29.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:29.85#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:59:29.85#ibcon#first serial, iclass 34, count 2 2006.281.07:59:29.85#ibcon#enter sib2, iclass 34, count 2 2006.281.07:59:29.85#ibcon#flushed, iclass 34, count 2 2006.281.07:59:29.85#ibcon#about to write, iclass 34, count 2 2006.281.07:59:29.85#ibcon#wrote, iclass 34, count 2 2006.281.07:59:29.85#ibcon#about to read 3, iclass 34, count 2 2006.281.07:59:29.87#ibcon#read 3, iclass 34, count 2 2006.281.07:59:29.87#ibcon#about to read 4, iclass 34, count 2 2006.281.07:59:29.87#ibcon#read 4, iclass 34, count 2 2006.281.07:59:29.87#ibcon#about to read 5, iclass 34, count 2 2006.281.07:59:29.87#ibcon#read 5, iclass 34, count 2 2006.281.07:59:29.87#ibcon#about to read 6, iclass 34, count 2 2006.281.07:59:29.87#ibcon#read 6, iclass 34, count 2 2006.281.07:59:29.87#ibcon#end of sib2, iclass 34, count 2 2006.281.07:59:29.87#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:59:29.87#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:59:29.87#ibcon#[25=AT03-06\r\n] 2006.281.07:59:29.87#ibcon#*before write, iclass 34, count 2 2006.281.07:59:29.87#ibcon#enter sib2, iclass 34, count 2 2006.281.07:59:29.87#ibcon#flushed, iclass 34, count 2 2006.281.07:59:29.87#ibcon#about to write, iclass 34, count 2 2006.281.07:59:29.87#ibcon#wrote, iclass 34, count 2 2006.281.07:59:29.87#ibcon#about to read 3, iclass 34, count 2 2006.281.07:59:29.90#ibcon#read 3, iclass 34, count 2 2006.281.07:59:29.90#ibcon#about to read 4, iclass 34, count 2 2006.281.07:59:29.90#ibcon#read 4, iclass 34, count 2 2006.281.07:59:29.90#ibcon#about to read 5, iclass 34, count 2 2006.281.07:59:29.90#ibcon#read 5, iclass 34, count 2 2006.281.07:59:29.90#ibcon#about to read 6, iclass 34, count 2 2006.281.07:59:29.90#ibcon#read 6, iclass 34, count 2 2006.281.07:59:29.90#ibcon#end of sib2, iclass 34, count 2 2006.281.07:59:29.90#ibcon#*after write, iclass 34, count 2 2006.281.07:59:29.90#ibcon#*before return 0, iclass 34, count 2 2006.281.07:59:29.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:29.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:29.90#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:59:29.90#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:29.90#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:30.02#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:30.02#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:30.02#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:59:30.02#ibcon#first serial, iclass 34, count 0 2006.281.07:59:30.02#ibcon#enter sib2, iclass 34, count 0 2006.281.07:59:30.02#ibcon#flushed, iclass 34, count 0 2006.281.07:59:30.02#ibcon#about to write, iclass 34, count 0 2006.281.07:59:30.02#ibcon#wrote, iclass 34, count 0 2006.281.07:59:30.02#ibcon#about to read 3, iclass 34, count 0 2006.281.07:59:30.04#ibcon#read 3, iclass 34, count 0 2006.281.07:59:30.04#ibcon#about to read 4, iclass 34, count 0 2006.281.07:59:30.04#ibcon#read 4, iclass 34, count 0 2006.281.07:59:30.04#ibcon#about to read 5, iclass 34, count 0 2006.281.07:59:30.04#ibcon#read 5, iclass 34, count 0 2006.281.07:59:30.04#ibcon#about to read 6, iclass 34, count 0 2006.281.07:59:30.04#ibcon#read 6, iclass 34, count 0 2006.281.07:59:30.04#ibcon#end of sib2, iclass 34, count 0 2006.281.07:59:30.04#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:59:30.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:59:30.04#ibcon#[25=USB\r\n] 2006.281.07:59:30.04#ibcon#*before write, iclass 34, count 0 2006.281.07:59:30.04#ibcon#enter sib2, iclass 34, count 0 2006.281.07:59:30.04#ibcon#flushed, iclass 34, count 0 2006.281.07:59:30.04#ibcon#about to write, iclass 34, count 0 2006.281.07:59:30.04#ibcon#wrote, iclass 34, count 0 2006.281.07:59:30.04#ibcon#about to read 3, iclass 34, count 0 2006.281.07:59:30.07#ibcon#read 3, iclass 34, count 0 2006.281.07:59:30.07#ibcon#about to read 4, iclass 34, count 0 2006.281.07:59:30.07#ibcon#read 4, iclass 34, count 0 2006.281.07:59:30.07#ibcon#about to read 5, iclass 34, count 0 2006.281.07:59:30.07#ibcon#read 5, iclass 34, count 0 2006.281.07:59:30.07#ibcon#about to read 6, iclass 34, count 0 2006.281.07:59:30.07#ibcon#read 6, iclass 34, count 0 2006.281.07:59:30.07#ibcon#end of sib2, iclass 34, count 0 2006.281.07:59:30.07#ibcon#*after write, iclass 34, count 0 2006.281.07:59:30.07#ibcon#*before return 0, iclass 34, count 0 2006.281.07:59:30.07#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:30.07#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:30.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:59:30.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:59:30.07$vc4f8/valo=4,832.99 2006.281.07:59:30.07#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:59:30.07#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:59:30.07#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:30.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:30.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:30.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:30.07#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:59:30.07#ibcon#first serial, iclass 36, count 0 2006.281.07:59:30.07#ibcon#enter sib2, iclass 36, count 0 2006.281.07:59:30.07#ibcon#flushed, iclass 36, count 0 2006.281.07:59:30.07#ibcon#about to write, iclass 36, count 0 2006.281.07:59:30.07#ibcon#wrote, iclass 36, count 0 2006.281.07:59:30.07#ibcon#about to read 3, iclass 36, count 0 2006.281.07:59:30.09#ibcon#read 3, iclass 36, count 0 2006.281.07:59:30.09#ibcon#about to read 4, iclass 36, count 0 2006.281.07:59:30.09#ibcon#read 4, iclass 36, count 0 2006.281.07:59:30.09#ibcon#about to read 5, iclass 36, count 0 2006.281.07:59:30.09#ibcon#read 5, iclass 36, count 0 2006.281.07:59:30.09#ibcon#about to read 6, iclass 36, count 0 2006.281.07:59:30.09#ibcon#read 6, iclass 36, count 0 2006.281.07:59:30.09#ibcon#end of sib2, iclass 36, count 0 2006.281.07:59:30.09#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:59:30.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:59:30.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.07:59:30.11#ibcon#*before write, iclass 36, count 0 2006.281.07:59:30.11#ibcon#enter sib2, iclass 36, count 0 2006.281.07:59:30.11#ibcon#flushed, iclass 36, count 0 2006.281.07:59:30.11#ibcon#about to write, iclass 36, count 0 2006.281.07:59:30.11#ibcon#wrote, iclass 36, count 0 2006.281.07:59:30.11#ibcon#about to read 3, iclass 36, count 0 2006.281.07:59:30.15#ibcon#read 3, iclass 36, count 0 2006.281.07:59:30.15#ibcon#about to read 4, iclass 36, count 0 2006.281.07:59:30.15#ibcon#read 4, iclass 36, count 0 2006.281.07:59:30.15#ibcon#about to read 5, iclass 36, count 0 2006.281.07:59:30.15#ibcon#read 5, iclass 36, count 0 2006.281.07:59:30.15#ibcon#about to read 6, iclass 36, count 0 2006.281.07:59:30.15#ibcon#read 6, iclass 36, count 0 2006.281.07:59:30.15#ibcon#end of sib2, iclass 36, count 0 2006.281.07:59:30.15#ibcon#*after write, iclass 36, count 0 2006.281.07:59:30.15#ibcon#*before return 0, iclass 36, count 0 2006.281.07:59:30.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:30.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:30.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:59:30.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:59:30.15$vc4f8/va=4,6 2006.281.07:59:30.15#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:59:30.15#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:59:30.15#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:30.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:30.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:30.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:30.19#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:59:30.19#ibcon#first serial, iclass 38, count 2 2006.281.07:59:30.19#ibcon#enter sib2, iclass 38, count 2 2006.281.07:59:30.19#ibcon#flushed, iclass 38, count 2 2006.281.07:59:30.19#ibcon#about to write, iclass 38, count 2 2006.281.07:59:30.19#ibcon#wrote, iclass 38, count 2 2006.281.07:59:30.19#ibcon#about to read 3, iclass 38, count 2 2006.281.07:59:30.21#ibcon#read 3, iclass 38, count 2 2006.281.07:59:30.21#ibcon#about to read 4, iclass 38, count 2 2006.281.07:59:30.21#ibcon#read 4, iclass 38, count 2 2006.281.07:59:30.21#ibcon#about to read 5, iclass 38, count 2 2006.281.07:59:30.21#ibcon#read 5, iclass 38, count 2 2006.281.07:59:30.21#ibcon#about to read 6, iclass 38, count 2 2006.281.07:59:30.21#ibcon#read 6, iclass 38, count 2 2006.281.07:59:30.21#ibcon#end of sib2, iclass 38, count 2 2006.281.07:59:30.21#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:59:30.21#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:59:30.21#ibcon#[25=AT04-06\r\n] 2006.281.07:59:30.21#ibcon#*before write, iclass 38, count 2 2006.281.07:59:30.21#ibcon#enter sib2, iclass 38, count 2 2006.281.07:59:30.21#ibcon#flushed, iclass 38, count 2 2006.281.07:59:30.21#ibcon#about to write, iclass 38, count 2 2006.281.07:59:30.21#ibcon#wrote, iclass 38, count 2 2006.281.07:59:30.21#ibcon#about to read 3, iclass 38, count 2 2006.281.07:59:30.24#ibcon#read 3, iclass 38, count 2 2006.281.07:59:30.24#ibcon#about to read 4, iclass 38, count 2 2006.281.07:59:30.24#ibcon#read 4, iclass 38, count 2 2006.281.07:59:30.24#ibcon#about to read 5, iclass 38, count 2 2006.281.07:59:30.24#ibcon#read 5, iclass 38, count 2 2006.281.07:59:30.24#ibcon#about to read 6, iclass 38, count 2 2006.281.07:59:30.24#ibcon#read 6, iclass 38, count 2 2006.281.07:59:30.24#ibcon#end of sib2, iclass 38, count 2 2006.281.07:59:30.24#ibcon#*after write, iclass 38, count 2 2006.281.07:59:30.24#ibcon#*before return 0, iclass 38, count 2 2006.281.07:59:30.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:30.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:30.24#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:59:30.24#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:30.24#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:30.36#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:30.36#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:30.36#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:59:30.36#ibcon#first serial, iclass 38, count 0 2006.281.07:59:30.36#ibcon#enter sib2, iclass 38, count 0 2006.281.07:59:30.36#ibcon#flushed, iclass 38, count 0 2006.281.07:59:30.36#ibcon#about to write, iclass 38, count 0 2006.281.07:59:30.36#ibcon#wrote, iclass 38, count 0 2006.281.07:59:30.36#ibcon#about to read 3, iclass 38, count 0 2006.281.07:59:30.38#ibcon#read 3, iclass 38, count 0 2006.281.07:59:30.38#ibcon#about to read 4, iclass 38, count 0 2006.281.07:59:30.38#ibcon#read 4, iclass 38, count 0 2006.281.07:59:30.38#ibcon#about to read 5, iclass 38, count 0 2006.281.07:59:30.38#ibcon#read 5, iclass 38, count 0 2006.281.07:59:30.38#ibcon#about to read 6, iclass 38, count 0 2006.281.07:59:30.38#ibcon#read 6, iclass 38, count 0 2006.281.07:59:30.38#ibcon#end of sib2, iclass 38, count 0 2006.281.07:59:30.38#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:59:30.38#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:59:30.38#ibcon#[25=USB\r\n] 2006.281.07:59:30.38#ibcon#*before write, iclass 38, count 0 2006.281.07:59:30.38#ibcon#enter sib2, iclass 38, count 0 2006.281.07:59:30.38#ibcon#flushed, iclass 38, count 0 2006.281.07:59:30.38#ibcon#about to write, iclass 38, count 0 2006.281.07:59:30.38#ibcon#wrote, iclass 38, count 0 2006.281.07:59:30.38#ibcon#about to read 3, iclass 38, count 0 2006.281.07:59:30.41#ibcon#read 3, iclass 38, count 0 2006.281.07:59:30.41#ibcon#about to read 4, iclass 38, count 0 2006.281.07:59:30.41#ibcon#read 4, iclass 38, count 0 2006.281.07:59:30.41#ibcon#about to read 5, iclass 38, count 0 2006.281.07:59:30.41#ibcon#read 5, iclass 38, count 0 2006.281.07:59:30.41#ibcon#about to read 6, iclass 38, count 0 2006.281.07:59:30.41#ibcon#read 6, iclass 38, count 0 2006.281.07:59:30.41#ibcon#end of sib2, iclass 38, count 0 2006.281.07:59:30.41#ibcon#*after write, iclass 38, count 0 2006.281.07:59:30.41#ibcon#*before return 0, iclass 38, count 0 2006.281.07:59:30.41#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:30.41#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:30.41#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:59:30.41#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:59:30.41$vc4f8/valo=5,652.99 2006.281.07:59:30.41#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:59:30.41#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:59:30.41#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:30.41#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:30.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:30.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:30.41#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:59:30.41#ibcon#first serial, iclass 40, count 0 2006.281.07:59:30.41#ibcon#enter sib2, iclass 40, count 0 2006.281.07:59:30.41#ibcon#flushed, iclass 40, count 0 2006.281.07:59:30.41#ibcon#about to write, iclass 40, count 0 2006.281.07:59:30.41#ibcon#wrote, iclass 40, count 0 2006.281.07:59:30.41#ibcon#about to read 3, iclass 40, count 0 2006.281.07:59:30.43#ibcon#read 3, iclass 40, count 0 2006.281.07:59:30.43#ibcon#about to read 4, iclass 40, count 0 2006.281.07:59:30.43#ibcon#read 4, iclass 40, count 0 2006.281.07:59:30.43#ibcon#about to read 5, iclass 40, count 0 2006.281.07:59:30.43#ibcon#read 5, iclass 40, count 0 2006.281.07:59:30.43#ibcon#about to read 6, iclass 40, count 0 2006.281.07:59:30.43#ibcon#read 6, iclass 40, count 0 2006.281.07:59:30.43#ibcon#end of sib2, iclass 40, count 0 2006.281.07:59:30.43#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:59:30.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:59:30.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.07:59:30.43#ibcon#*before write, iclass 40, count 0 2006.281.07:59:30.43#ibcon#enter sib2, iclass 40, count 0 2006.281.07:59:30.43#ibcon#flushed, iclass 40, count 0 2006.281.07:59:30.43#ibcon#about to write, iclass 40, count 0 2006.281.07:59:30.43#ibcon#wrote, iclass 40, count 0 2006.281.07:59:30.43#ibcon#about to read 3, iclass 40, count 0 2006.281.07:59:30.47#ibcon#read 3, iclass 40, count 0 2006.281.07:59:30.47#ibcon#about to read 4, iclass 40, count 0 2006.281.07:59:30.47#ibcon#read 4, iclass 40, count 0 2006.281.07:59:30.47#ibcon#about to read 5, iclass 40, count 0 2006.281.07:59:30.47#ibcon#read 5, iclass 40, count 0 2006.281.07:59:30.47#ibcon#about to read 6, iclass 40, count 0 2006.281.07:59:30.47#ibcon#read 6, iclass 40, count 0 2006.281.07:59:30.47#ibcon#end of sib2, iclass 40, count 0 2006.281.07:59:30.47#ibcon#*after write, iclass 40, count 0 2006.281.07:59:30.47#ibcon#*before return 0, iclass 40, count 0 2006.281.07:59:30.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:30.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:30.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:59:30.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:59:30.47$vc4f8/va=5,7 2006.281.07:59:30.47#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:59:30.47#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:59:30.47#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:30.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:30.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:30.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:30.53#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:59:30.53#ibcon#first serial, iclass 4, count 2 2006.281.07:59:30.53#ibcon#enter sib2, iclass 4, count 2 2006.281.07:59:30.53#ibcon#flushed, iclass 4, count 2 2006.281.07:59:30.53#ibcon#about to write, iclass 4, count 2 2006.281.07:59:30.53#ibcon#wrote, iclass 4, count 2 2006.281.07:59:30.53#ibcon#about to read 3, iclass 4, count 2 2006.281.07:59:30.55#ibcon#read 3, iclass 4, count 2 2006.281.07:59:30.55#ibcon#about to read 4, iclass 4, count 2 2006.281.07:59:30.55#ibcon#read 4, iclass 4, count 2 2006.281.07:59:30.55#ibcon#about to read 5, iclass 4, count 2 2006.281.07:59:30.55#ibcon#read 5, iclass 4, count 2 2006.281.07:59:30.55#ibcon#about to read 6, iclass 4, count 2 2006.281.07:59:30.55#ibcon#read 6, iclass 4, count 2 2006.281.07:59:30.55#ibcon#end of sib2, iclass 4, count 2 2006.281.07:59:30.55#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:59:30.55#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:59:30.55#ibcon#[25=AT05-07\r\n] 2006.281.07:59:30.55#ibcon#*before write, iclass 4, count 2 2006.281.07:59:30.55#ibcon#enter sib2, iclass 4, count 2 2006.281.07:59:30.55#ibcon#flushed, iclass 4, count 2 2006.281.07:59:30.55#ibcon#about to write, iclass 4, count 2 2006.281.07:59:30.55#ibcon#wrote, iclass 4, count 2 2006.281.07:59:30.55#ibcon#about to read 3, iclass 4, count 2 2006.281.07:59:30.58#ibcon#read 3, iclass 4, count 2 2006.281.07:59:30.58#ibcon#about to read 4, iclass 4, count 2 2006.281.07:59:30.58#ibcon#read 4, iclass 4, count 2 2006.281.07:59:30.58#ibcon#about to read 5, iclass 4, count 2 2006.281.07:59:30.58#ibcon#read 5, iclass 4, count 2 2006.281.07:59:30.58#ibcon#about to read 6, iclass 4, count 2 2006.281.07:59:30.58#ibcon#read 6, iclass 4, count 2 2006.281.07:59:30.58#ibcon#end of sib2, iclass 4, count 2 2006.281.07:59:30.58#ibcon#*after write, iclass 4, count 2 2006.281.07:59:30.58#ibcon#*before return 0, iclass 4, count 2 2006.281.07:59:30.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:30.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:30.58#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:59:30.58#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:30.58#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:30.70#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:30.70#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:30.70#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:59:30.70#ibcon#first serial, iclass 4, count 0 2006.281.07:59:30.70#ibcon#enter sib2, iclass 4, count 0 2006.281.07:59:30.70#ibcon#flushed, iclass 4, count 0 2006.281.07:59:30.70#ibcon#about to write, iclass 4, count 0 2006.281.07:59:30.70#ibcon#wrote, iclass 4, count 0 2006.281.07:59:30.70#ibcon#about to read 3, iclass 4, count 0 2006.281.07:59:30.72#ibcon#read 3, iclass 4, count 0 2006.281.07:59:30.72#ibcon#about to read 4, iclass 4, count 0 2006.281.07:59:30.72#ibcon#read 4, iclass 4, count 0 2006.281.07:59:30.72#ibcon#about to read 5, iclass 4, count 0 2006.281.07:59:30.72#ibcon#read 5, iclass 4, count 0 2006.281.07:59:30.72#ibcon#about to read 6, iclass 4, count 0 2006.281.07:59:30.72#ibcon#read 6, iclass 4, count 0 2006.281.07:59:30.72#ibcon#end of sib2, iclass 4, count 0 2006.281.07:59:30.72#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:59:30.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:59:30.72#ibcon#[25=USB\r\n] 2006.281.07:59:30.72#ibcon#*before write, iclass 4, count 0 2006.281.07:59:30.72#ibcon#enter sib2, iclass 4, count 0 2006.281.07:59:30.72#ibcon#flushed, iclass 4, count 0 2006.281.07:59:30.72#ibcon#about to write, iclass 4, count 0 2006.281.07:59:30.72#ibcon#wrote, iclass 4, count 0 2006.281.07:59:30.72#ibcon#about to read 3, iclass 4, count 0 2006.281.07:59:30.75#ibcon#read 3, iclass 4, count 0 2006.281.07:59:30.75#ibcon#about to read 4, iclass 4, count 0 2006.281.07:59:30.75#ibcon#read 4, iclass 4, count 0 2006.281.07:59:30.75#ibcon#about to read 5, iclass 4, count 0 2006.281.07:59:30.75#ibcon#read 5, iclass 4, count 0 2006.281.07:59:30.75#ibcon#about to read 6, iclass 4, count 0 2006.281.07:59:30.75#ibcon#read 6, iclass 4, count 0 2006.281.07:59:30.75#ibcon#end of sib2, iclass 4, count 0 2006.281.07:59:30.75#ibcon#*after write, iclass 4, count 0 2006.281.07:59:30.75#ibcon#*before return 0, iclass 4, count 0 2006.281.07:59:30.75#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:30.75#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:30.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:59:30.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:59:30.75$vc4f8/valo=6,772.99 2006.281.07:59:30.75#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:59:30.75#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:59:30.75#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:30.75#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:30.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:30.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:30.75#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:59:30.75#ibcon#first serial, iclass 6, count 0 2006.281.07:59:30.75#ibcon#enter sib2, iclass 6, count 0 2006.281.07:59:30.75#ibcon#flushed, iclass 6, count 0 2006.281.07:59:30.75#ibcon#about to write, iclass 6, count 0 2006.281.07:59:30.75#ibcon#wrote, iclass 6, count 0 2006.281.07:59:30.75#ibcon#about to read 3, iclass 6, count 0 2006.281.07:59:30.77#ibcon#read 3, iclass 6, count 0 2006.281.07:59:30.77#ibcon#about to read 4, iclass 6, count 0 2006.281.07:59:30.77#ibcon#read 4, iclass 6, count 0 2006.281.07:59:30.77#ibcon#about to read 5, iclass 6, count 0 2006.281.07:59:30.77#ibcon#read 5, iclass 6, count 0 2006.281.07:59:30.77#ibcon#about to read 6, iclass 6, count 0 2006.281.07:59:30.77#ibcon#read 6, iclass 6, count 0 2006.281.07:59:30.77#ibcon#end of sib2, iclass 6, count 0 2006.281.07:59:30.77#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:59:30.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:59:30.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.07:59:30.79#ibcon#*before write, iclass 6, count 0 2006.281.07:59:30.79#ibcon#enter sib2, iclass 6, count 0 2006.281.07:59:30.79#ibcon#flushed, iclass 6, count 0 2006.281.07:59:30.79#ibcon#about to write, iclass 6, count 0 2006.281.07:59:30.79#ibcon#wrote, iclass 6, count 0 2006.281.07:59:30.79#ibcon#about to read 3, iclass 6, count 0 2006.281.07:59:30.83#ibcon#read 3, iclass 6, count 0 2006.281.07:59:30.83#ibcon#about to read 4, iclass 6, count 0 2006.281.07:59:30.83#ibcon#read 4, iclass 6, count 0 2006.281.07:59:30.83#ibcon#about to read 5, iclass 6, count 0 2006.281.07:59:30.83#ibcon#read 5, iclass 6, count 0 2006.281.07:59:30.83#ibcon#about to read 6, iclass 6, count 0 2006.281.07:59:30.83#ibcon#read 6, iclass 6, count 0 2006.281.07:59:30.83#ibcon#end of sib2, iclass 6, count 0 2006.281.07:59:30.83#ibcon#*after write, iclass 6, count 0 2006.281.07:59:30.83#ibcon#*before return 0, iclass 6, count 0 2006.281.07:59:30.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:30.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:30.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:59:30.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:59:30.83$vc4f8/va=6,6 2006.281.07:59:30.83#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.07:59:30.83#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.07:59:30.83#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:30.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:30.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:30.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:30.87#ibcon#enter wrdev, iclass 10, count 2 2006.281.07:59:30.87#ibcon#first serial, iclass 10, count 2 2006.281.07:59:30.87#ibcon#enter sib2, iclass 10, count 2 2006.281.07:59:30.87#ibcon#flushed, iclass 10, count 2 2006.281.07:59:30.87#ibcon#about to write, iclass 10, count 2 2006.281.07:59:30.87#ibcon#wrote, iclass 10, count 2 2006.281.07:59:30.87#ibcon#about to read 3, iclass 10, count 2 2006.281.07:59:30.89#ibcon#read 3, iclass 10, count 2 2006.281.07:59:30.89#ibcon#about to read 4, iclass 10, count 2 2006.281.07:59:30.89#ibcon#read 4, iclass 10, count 2 2006.281.07:59:30.89#ibcon#about to read 5, iclass 10, count 2 2006.281.07:59:30.89#ibcon#read 5, iclass 10, count 2 2006.281.07:59:30.89#ibcon#about to read 6, iclass 10, count 2 2006.281.07:59:30.89#ibcon#read 6, iclass 10, count 2 2006.281.07:59:30.89#ibcon#end of sib2, iclass 10, count 2 2006.281.07:59:30.89#ibcon#*mode == 0, iclass 10, count 2 2006.281.07:59:30.89#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.07:59:30.89#ibcon#[25=AT06-06\r\n] 2006.281.07:59:30.89#ibcon#*before write, iclass 10, count 2 2006.281.07:59:30.89#ibcon#enter sib2, iclass 10, count 2 2006.281.07:59:30.89#ibcon#flushed, iclass 10, count 2 2006.281.07:59:30.89#ibcon#about to write, iclass 10, count 2 2006.281.07:59:30.89#ibcon#wrote, iclass 10, count 2 2006.281.07:59:30.89#ibcon#about to read 3, iclass 10, count 2 2006.281.07:59:30.92#ibcon#read 3, iclass 10, count 2 2006.281.07:59:30.92#ibcon#about to read 4, iclass 10, count 2 2006.281.07:59:30.92#ibcon#read 4, iclass 10, count 2 2006.281.07:59:30.92#ibcon#about to read 5, iclass 10, count 2 2006.281.07:59:30.92#ibcon#read 5, iclass 10, count 2 2006.281.07:59:30.92#ibcon#about to read 6, iclass 10, count 2 2006.281.07:59:30.92#ibcon#read 6, iclass 10, count 2 2006.281.07:59:30.92#ibcon#end of sib2, iclass 10, count 2 2006.281.07:59:30.92#ibcon#*after write, iclass 10, count 2 2006.281.07:59:30.92#ibcon#*before return 0, iclass 10, count 2 2006.281.07:59:30.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:30.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:30.92#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.07:59:30.92#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:30.92#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:31.04#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:31.04#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:31.04#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:59:31.04#ibcon#first serial, iclass 10, count 0 2006.281.07:59:31.04#ibcon#enter sib2, iclass 10, count 0 2006.281.07:59:31.04#ibcon#flushed, iclass 10, count 0 2006.281.07:59:31.04#ibcon#about to write, iclass 10, count 0 2006.281.07:59:31.04#ibcon#wrote, iclass 10, count 0 2006.281.07:59:31.04#ibcon#about to read 3, iclass 10, count 0 2006.281.07:59:31.06#ibcon#read 3, iclass 10, count 0 2006.281.07:59:31.06#ibcon#about to read 4, iclass 10, count 0 2006.281.07:59:31.06#ibcon#read 4, iclass 10, count 0 2006.281.07:59:31.06#ibcon#about to read 5, iclass 10, count 0 2006.281.07:59:31.06#ibcon#read 5, iclass 10, count 0 2006.281.07:59:31.06#ibcon#about to read 6, iclass 10, count 0 2006.281.07:59:31.06#ibcon#read 6, iclass 10, count 0 2006.281.07:59:31.06#ibcon#end of sib2, iclass 10, count 0 2006.281.07:59:31.06#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:59:31.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:59:31.06#ibcon#[25=USB\r\n] 2006.281.07:59:31.06#ibcon#*before write, iclass 10, count 0 2006.281.07:59:31.06#ibcon#enter sib2, iclass 10, count 0 2006.281.07:59:31.06#ibcon#flushed, iclass 10, count 0 2006.281.07:59:31.06#ibcon#about to write, iclass 10, count 0 2006.281.07:59:31.06#ibcon#wrote, iclass 10, count 0 2006.281.07:59:31.06#ibcon#about to read 3, iclass 10, count 0 2006.281.07:59:31.09#ibcon#read 3, iclass 10, count 0 2006.281.07:59:31.09#ibcon#about to read 4, iclass 10, count 0 2006.281.07:59:31.09#ibcon#read 4, iclass 10, count 0 2006.281.07:59:31.09#ibcon#about to read 5, iclass 10, count 0 2006.281.07:59:31.09#ibcon#read 5, iclass 10, count 0 2006.281.07:59:31.09#ibcon#about to read 6, iclass 10, count 0 2006.281.07:59:31.09#ibcon#read 6, iclass 10, count 0 2006.281.07:59:31.09#ibcon#end of sib2, iclass 10, count 0 2006.281.07:59:31.09#ibcon#*after write, iclass 10, count 0 2006.281.07:59:31.09#ibcon#*before return 0, iclass 10, count 0 2006.281.07:59:31.09#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:31.09#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:31.09#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:59:31.09#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:59:31.09$vc4f8/valo=7,832.99 2006.281.07:59:31.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.07:59:31.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.07:59:31.09#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:31.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:31.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:31.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:31.09#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:59:31.09#ibcon#first serial, iclass 12, count 0 2006.281.07:59:31.09#ibcon#enter sib2, iclass 12, count 0 2006.281.07:59:31.09#ibcon#flushed, iclass 12, count 0 2006.281.07:59:31.09#ibcon#about to write, iclass 12, count 0 2006.281.07:59:31.09#ibcon#wrote, iclass 12, count 0 2006.281.07:59:31.09#ibcon#about to read 3, iclass 12, count 0 2006.281.07:59:31.11#ibcon#read 3, iclass 12, count 0 2006.281.07:59:31.11#ibcon#about to read 4, iclass 12, count 0 2006.281.07:59:31.11#ibcon#read 4, iclass 12, count 0 2006.281.07:59:31.11#ibcon#about to read 5, iclass 12, count 0 2006.281.07:59:31.11#ibcon#read 5, iclass 12, count 0 2006.281.07:59:31.11#ibcon#about to read 6, iclass 12, count 0 2006.281.07:59:31.11#ibcon#read 6, iclass 12, count 0 2006.281.07:59:31.11#ibcon#end of sib2, iclass 12, count 0 2006.281.07:59:31.11#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:59:31.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:59:31.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.07:59:31.11#ibcon#*before write, iclass 12, count 0 2006.281.07:59:31.11#ibcon#enter sib2, iclass 12, count 0 2006.281.07:59:31.11#ibcon#flushed, iclass 12, count 0 2006.281.07:59:31.11#ibcon#about to write, iclass 12, count 0 2006.281.07:59:31.11#ibcon#wrote, iclass 12, count 0 2006.281.07:59:31.11#ibcon#about to read 3, iclass 12, count 0 2006.281.07:59:31.14#abcon#<5=/13 2.4 7.9 20.54 511001.3\r\n> 2006.281.07:59:31.15#ibcon#read 3, iclass 12, count 0 2006.281.07:59:31.15#ibcon#about to read 4, iclass 12, count 0 2006.281.07:59:31.15#ibcon#read 4, iclass 12, count 0 2006.281.07:59:31.15#ibcon#about to read 5, iclass 12, count 0 2006.281.07:59:31.15#ibcon#read 5, iclass 12, count 0 2006.281.07:59:31.15#ibcon#about to read 6, iclass 12, count 0 2006.281.07:59:31.15#ibcon#read 6, iclass 12, count 0 2006.281.07:59:31.15#ibcon#end of sib2, iclass 12, count 0 2006.281.07:59:31.15#ibcon#*after write, iclass 12, count 0 2006.281.07:59:31.15#ibcon#*before return 0, iclass 12, count 0 2006.281.07:59:31.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:31.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:31.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:59:31.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:59:31.15$vc4f8/va=7,6 2006.281.07:59:31.15#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.07:59:31.15#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.07:59:31.15#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:31.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:59:31.16#abcon#{5=INTERFACE CLEAR} 2006.281.07:59:31.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:59:31.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:59:31.21#ibcon#enter wrdev, iclass 17, count 2 2006.281.07:59:31.21#ibcon#first serial, iclass 17, count 2 2006.281.07:59:31.21#ibcon#enter sib2, iclass 17, count 2 2006.281.07:59:31.21#ibcon#flushed, iclass 17, count 2 2006.281.07:59:31.21#ibcon#about to write, iclass 17, count 2 2006.281.07:59:31.21#ibcon#wrote, iclass 17, count 2 2006.281.07:59:31.21#ibcon#about to read 3, iclass 17, count 2 2006.281.07:59:31.22#abcon#[5=S1D000X0/0*\r\n] 2006.281.07:59:31.23#ibcon#read 3, iclass 17, count 2 2006.281.07:59:31.23#ibcon#about to read 4, iclass 17, count 2 2006.281.07:59:31.23#ibcon#read 4, iclass 17, count 2 2006.281.07:59:31.23#ibcon#about to read 5, iclass 17, count 2 2006.281.07:59:31.23#ibcon#read 5, iclass 17, count 2 2006.281.07:59:31.23#ibcon#about to read 6, iclass 17, count 2 2006.281.07:59:31.23#ibcon#read 6, iclass 17, count 2 2006.281.07:59:31.23#ibcon#end of sib2, iclass 17, count 2 2006.281.07:59:31.23#ibcon#*mode == 0, iclass 17, count 2 2006.281.07:59:31.23#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.07:59:31.23#ibcon#[25=AT07-06\r\n] 2006.281.07:59:31.23#ibcon#*before write, iclass 17, count 2 2006.281.07:59:31.23#ibcon#enter sib2, iclass 17, count 2 2006.281.07:59:31.23#ibcon#flushed, iclass 17, count 2 2006.281.07:59:31.23#ibcon#about to write, iclass 17, count 2 2006.281.07:59:31.23#ibcon#wrote, iclass 17, count 2 2006.281.07:59:31.23#ibcon#about to read 3, iclass 17, count 2 2006.281.07:59:31.26#ibcon#read 3, iclass 17, count 2 2006.281.07:59:31.26#ibcon#about to read 4, iclass 17, count 2 2006.281.07:59:31.26#ibcon#read 4, iclass 17, count 2 2006.281.07:59:31.26#ibcon#about to read 5, iclass 17, count 2 2006.281.07:59:31.26#ibcon#read 5, iclass 17, count 2 2006.281.07:59:31.26#ibcon#about to read 6, iclass 17, count 2 2006.281.07:59:31.26#ibcon#read 6, iclass 17, count 2 2006.281.07:59:31.26#ibcon#end of sib2, iclass 17, count 2 2006.281.07:59:31.26#ibcon#*after write, iclass 17, count 2 2006.281.07:59:31.26#ibcon#*before return 0, iclass 17, count 2 2006.281.07:59:31.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:59:31.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.07:59:31.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.07:59:31.26#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:31.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:59:31.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:59:31.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:59:31.38#ibcon#enter wrdev, iclass 17, count 0 2006.281.07:59:31.38#ibcon#first serial, iclass 17, count 0 2006.281.07:59:31.38#ibcon#enter sib2, iclass 17, count 0 2006.281.07:59:31.38#ibcon#flushed, iclass 17, count 0 2006.281.07:59:31.38#ibcon#about to write, iclass 17, count 0 2006.281.07:59:31.38#ibcon#wrote, iclass 17, count 0 2006.281.07:59:31.38#ibcon#about to read 3, iclass 17, count 0 2006.281.07:59:31.40#ibcon#read 3, iclass 17, count 0 2006.281.07:59:31.40#ibcon#about to read 4, iclass 17, count 0 2006.281.07:59:31.40#ibcon#read 4, iclass 17, count 0 2006.281.07:59:31.40#ibcon#about to read 5, iclass 17, count 0 2006.281.07:59:31.40#ibcon#read 5, iclass 17, count 0 2006.281.07:59:31.40#ibcon#about to read 6, iclass 17, count 0 2006.281.07:59:31.40#ibcon#read 6, iclass 17, count 0 2006.281.07:59:31.40#ibcon#end of sib2, iclass 17, count 0 2006.281.07:59:31.40#ibcon#*mode == 0, iclass 17, count 0 2006.281.07:59:31.40#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.07:59:31.40#ibcon#[25=USB\r\n] 2006.281.07:59:31.40#ibcon#*before write, iclass 17, count 0 2006.281.07:59:31.40#ibcon#enter sib2, iclass 17, count 0 2006.281.07:59:31.40#ibcon#flushed, iclass 17, count 0 2006.281.07:59:31.40#ibcon#about to write, iclass 17, count 0 2006.281.07:59:31.40#ibcon#wrote, iclass 17, count 0 2006.281.07:59:31.40#ibcon#about to read 3, iclass 17, count 0 2006.281.07:59:31.43#ibcon#read 3, iclass 17, count 0 2006.281.07:59:31.43#ibcon#about to read 4, iclass 17, count 0 2006.281.07:59:31.43#ibcon#read 4, iclass 17, count 0 2006.281.07:59:31.43#ibcon#about to read 5, iclass 17, count 0 2006.281.07:59:31.43#ibcon#read 5, iclass 17, count 0 2006.281.07:59:31.43#ibcon#about to read 6, iclass 17, count 0 2006.281.07:59:31.43#ibcon#read 6, iclass 17, count 0 2006.281.07:59:31.43#ibcon#end of sib2, iclass 17, count 0 2006.281.07:59:31.43#ibcon#*after write, iclass 17, count 0 2006.281.07:59:31.43#ibcon#*before return 0, iclass 17, count 0 2006.281.07:59:31.43#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:59:31.43#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.07:59:31.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.07:59:31.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.07:59:31.43$vc4f8/valo=8,852.99 2006.281.07:59:31.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.07:59:31.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.07:59:31.43#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:31.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:59:31.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:59:31.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:59:31.43#ibcon#enter wrdev, iclass 20, count 0 2006.281.07:59:31.43#ibcon#first serial, iclass 20, count 0 2006.281.07:59:31.43#ibcon#enter sib2, iclass 20, count 0 2006.281.07:59:31.43#ibcon#flushed, iclass 20, count 0 2006.281.07:59:31.43#ibcon#about to write, iclass 20, count 0 2006.281.07:59:31.43#ibcon#wrote, iclass 20, count 0 2006.281.07:59:31.43#ibcon#about to read 3, iclass 20, count 0 2006.281.07:59:31.45#ibcon#read 3, iclass 20, count 0 2006.281.07:59:31.45#ibcon#about to read 4, iclass 20, count 0 2006.281.07:59:31.45#ibcon#read 4, iclass 20, count 0 2006.281.07:59:31.45#ibcon#about to read 5, iclass 20, count 0 2006.281.07:59:31.45#ibcon#read 5, iclass 20, count 0 2006.281.07:59:31.45#ibcon#about to read 6, iclass 20, count 0 2006.281.07:59:31.45#ibcon#read 6, iclass 20, count 0 2006.281.07:59:31.45#ibcon#end of sib2, iclass 20, count 0 2006.281.07:59:31.45#ibcon#*mode == 0, iclass 20, count 0 2006.281.07:59:31.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.07:59:31.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.07:59:31.45#ibcon#*before write, iclass 20, count 0 2006.281.07:59:31.45#ibcon#enter sib2, iclass 20, count 0 2006.281.07:59:31.45#ibcon#flushed, iclass 20, count 0 2006.281.07:59:31.45#ibcon#about to write, iclass 20, count 0 2006.281.07:59:31.45#ibcon#wrote, iclass 20, count 0 2006.281.07:59:31.45#ibcon#about to read 3, iclass 20, count 0 2006.281.07:59:31.49#ibcon#read 3, iclass 20, count 0 2006.281.07:59:31.49#ibcon#about to read 4, iclass 20, count 0 2006.281.07:59:31.49#ibcon#read 4, iclass 20, count 0 2006.281.07:59:31.49#ibcon#about to read 5, iclass 20, count 0 2006.281.07:59:31.49#ibcon#read 5, iclass 20, count 0 2006.281.07:59:31.49#ibcon#about to read 6, iclass 20, count 0 2006.281.07:59:31.49#ibcon#read 6, iclass 20, count 0 2006.281.07:59:31.49#ibcon#end of sib2, iclass 20, count 0 2006.281.07:59:31.49#ibcon#*after write, iclass 20, count 0 2006.281.07:59:31.49#ibcon#*before return 0, iclass 20, count 0 2006.281.07:59:31.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:59:31.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.07:59:31.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.07:59:31.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.07:59:31.49$vc4f8/va=8,6 2006.281.07:59:31.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.07:59:31.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.07:59:31.49#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:31.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:59:31.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:59:31.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:59:31.55#ibcon#enter wrdev, iclass 22, count 2 2006.281.07:59:31.55#ibcon#first serial, iclass 22, count 2 2006.281.07:59:31.55#ibcon#enter sib2, iclass 22, count 2 2006.281.07:59:31.55#ibcon#flushed, iclass 22, count 2 2006.281.07:59:31.55#ibcon#about to write, iclass 22, count 2 2006.281.07:59:31.55#ibcon#wrote, iclass 22, count 2 2006.281.07:59:31.55#ibcon#about to read 3, iclass 22, count 2 2006.281.07:59:31.57#ibcon#read 3, iclass 22, count 2 2006.281.07:59:31.57#ibcon#about to read 4, iclass 22, count 2 2006.281.07:59:31.57#ibcon#read 4, iclass 22, count 2 2006.281.07:59:31.57#ibcon#about to read 5, iclass 22, count 2 2006.281.07:59:31.57#ibcon#read 5, iclass 22, count 2 2006.281.07:59:31.57#ibcon#about to read 6, iclass 22, count 2 2006.281.07:59:31.57#ibcon#read 6, iclass 22, count 2 2006.281.07:59:31.57#ibcon#end of sib2, iclass 22, count 2 2006.281.07:59:31.57#ibcon#*mode == 0, iclass 22, count 2 2006.281.07:59:31.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.07:59:31.57#ibcon#[25=AT08-06\r\n] 2006.281.07:59:31.57#ibcon#*before write, iclass 22, count 2 2006.281.07:59:31.57#ibcon#enter sib2, iclass 22, count 2 2006.281.07:59:31.57#ibcon#flushed, iclass 22, count 2 2006.281.07:59:31.57#ibcon#about to write, iclass 22, count 2 2006.281.07:59:31.57#ibcon#wrote, iclass 22, count 2 2006.281.07:59:31.57#ibcon#about to read 3, iclass 22, count 2 2006.281.07:59:31.60#ibcon#read 3, iclass 22, count 2 2006.281.07:59:31.60#ibcon#about to read 4, iclass 22, count 2 2006.281.07:59:31.60#ibcon#read 4, iclass 22, count 2 2006.281.07:59:31.60#ibcon#about to read 5, iclass 22, count 2 2006.281.07:59:31.60#ibcon#read 5, iclass 22, count 2 2006.281.07:59:31.60#ibcon#about to read 6, iclass 22, count 2 2006.281.07:59:31.60#ibcon#read 6, iclass 22, count 2 2006.281.07:59:31.60#ibcon#end of sib2, iclass 22, count 2 2006.281.07:59:31.60#ibcon#*after write, iclass 22, count 2 2006.281.07:59:31.60#ibcon#*before return 0, iclass 22, count 2 2006.281.07:59:31.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:59:31.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.07:59:31.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.07:59:31.60#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:31.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:59:31.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:59:31.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:59:31.72#ibcon#enter wrdev, iclass 22, count 0 2006.281.07:59:31.72#ibcon#first serial, iclass 22, count 0 2006.281.07:59:31.72#ibcon#enter sib2, iclass 22, count 0 2006.281.07:59:31.72#ibcon#flushed, iclass 22, count 0 2006.281.07:59:31.72#ibcon#about to write, iclass 22, count 0 2006.281.07:59:31.72#ibcon#wrote, iclass 22, count 0 2006.281.07:59:31.72#ibcon#about to read 3, iclass 22, count 0 2006.281.07:59:31.74#ibcon#read 3, iclass 22, count 0 2006.281.07:59:31.74#ibcon#about to read 4, iclass 22, count 0 2006.281.07:59:31.74#ibcon#read 4, iclass 22, count 0 2006.281.07:59:31.74#ibcon#about to read 5, iclass 22, count 0 2006.281.07:59:31.74#ibcon#read 5, iclass 22, count 0 2006.281.07:59:31.74#ibcon#about to read 6, iclass 22, count 0 2006.281.07:59:31.74#ibcon#read 6, iclass 22, count 0 2006.281.07:59:31.74#ibcon#end of sib2, iclass 22, count 0 2006.281.07:59:31.74#ibcon#*mode == 0, iclass 22, count 0 2006.281.07:59:31.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.07:59:31.74#ibcon#[25=USB\r\n] 2006.281.07:59:31.74#ibcon#*before write, iclass 22, count 0 2006.281.07:59:31.74#ibcon#enter sib2, iclass 22, count 0 2006.281.07:59:31.74#ibcon#flushed, iclass 22, count 0 2006.281.07:59:31.74#ibcon#about to write, iclass 22, count 0 2006.281.07:59:31.74#ibcon#wrote, iclass 22, count 0 2006.281.07:59:31.74#ibcon#about to read 3, iclass 22, count 0 2006.281.07:59:31.77#ibcon#read 3, iclass 22, count 0 2006.281.07:59:31.77#ibcon#about to read 4, iclass 22, count 0 2006.281.07:59:31.77#ibcon#read 4, iclass 22, count 0 2006.281.07:59:31.77#ibcon#about to read 5, iclass 22, count 0 2006.281.07:59:31.77#ibcon#read 5, iclass 22, count 0 2006.281.07:59:31.77#ibcon#about to read 6, iclass 22, count 0 2006.281.07:59:31.77#ibcon#read 6, iclass 22, count 0 2006.281.07:59:31.77#ibcon#end of sib2, iclass 22, count 0 2006.281.07:59:31.77#ibcon#*after write, iclass 22, count 0 2006.281.07:59:31.77#ibcon#*before return 0, iclass 22, count 0 2006.281.07:59:31.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:59:31.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.07:59:31.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.07:59:31.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.07:59:31.77$vc4f8/vblo=1,632.99 2006.281.07:59:31.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.07:59:31.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.07:59:31.77#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:31.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:31.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:31.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:31.77#ibcon#enter wrdev, iclass 24, count 0 2006.281.07:59:31.77#ibcon#first serial, iclass 24, count 0 2006.281.07:59:31.77#ibcon#enter sib2, iclass 24, count 0 2006.281.07:59:31.77#ibcon#flushed, iclass 24, count 0 2006.281.07:59:31.77#ibcon#about to write, iclass 24, count 0 2006.281.07:59:31.77#ibcon#wrote, iclass 24, count 0 2006.281.07:59:31.77#ibcon#about to read 3, iclass 24, count 0 2006.281.07:59:31.79#ibcon#read 3, iclass 24, count 0 2006.281.07:59:31.79#ibcon#about to read 4, iclass 24, count 0 2006.281.07:59:31.79#ibcon#read 4, iclass 24, count 0 2006.281.07:59:31.79#ibcon#about to read 5, iclass 24, count 0 2006.281.07:59:31.79#ibcon#read 5, iclass 24, count 0 2006.281.07:59:31.79#ibcon#about to read 6, iclass 24, count 0 2006.281.07:59:31.79#ibcon#read 6, iclass 24, count 0 2006.281.07:59:31.79#ibcon#end of sib2, iclass 24, count 0 2006.281.07:59:31.79#ibcon#*mode == 0, iclass 24, count 0 2006.281.07:59:31.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.07:59:31.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.07:59:31.81#ibcon#*before write, iclass 24, count 0 2006.281.07:59:31.81#ibcon#enter sib2, iclass 24, count 0 2006.281.07:59:31.81#ibcon#flushed, iclass 24, count 0 2006.281.07:59:31.81#ibcon#about to write, iclass 24, count 0 2006.281.07:59:31.81#ibcon#wrote, iclass 24, count 0 2006.281.07:59:31.81#ibcon#about to read 3, iclass 24, count 0 2006.281.07:59:31.85#ibcon#read 3, iclass 24, count 0 2006.281.07:59:31.85#ibcon#about to read 4, iclass 24, count 0 2006.281.07:59:31.85#ibcon#read 4, iclass 24, count 0 2006.281.07:59:31.85#ibcon#about to read 5, iclass 24, count 0 2006.281.07:59:31.85#ibcon#read 5, iclass 24, count 0 2006.281.07:59:31.85#ibcon#about to read 6, iclass 24, count 0 2006.281.07:59:31.85#ibcon#read 6, iclass 24, count 0 2006.281.07:59:31.85#ibcon#end of sib2, iclass 24, count 0 2006.281.07:59:31.85#ibcon#*after write, iclass 24, count 0 2006.281.07:59:31.85#ibcon#*before return 0, iclass 24, count 0 2006.281.07:59:31.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:31.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.07:59:31.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.07:59:31.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.07:59:31.85$vc4f8/vb=1,4 2006.281.07:59:31.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.07:59:31.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.07:59:31.85#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:31.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:31.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:31.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:31.85#ibcon#enter wrdev, iclass 26, count 2 2006.281.07:59:31.85#ibcon#first serial, iclass 26, count 2 2006.281.07:59:31.85#ibcon#enter sib2, iclass 26, count 2 2006.281.07:59:31.85#ibcon#flushed, iclass 26, count 2 2006.281.07:59:31.85#ibcon#about to write, iclass 26, count 2 2006.281.07:59:31.85#ibcon#wrote, iclass 26, count 2 2006.281.07:59:31.85#ibcon#about to read 3, iclass 26, count 2 2006.281.07:59:31.87#ibcon#read 3, iclass 26, count 2 2006.281.07:59:31.87#ibcon#about to read 4, iclass 26, count 2 2006.281.07:59:31.87#ibcon#read 4, iclass 26, count 2 2006.281.07:59:31.87#ibcon#about to read 5, iclass 26, count 2 2006.281.07:59:31.87#ibcon#read 5, iclass 26, count 2 2006.281.07:59:31.87#ibcon#about to read 6, iclass 26, count 2 2006.281.07:59:31.87#ibcon#read 6, iclass 26, count 2 2006.281.07:59:31.87#ibcon#end of sib2, iclass 26, count 2 2006.281.07:59:31.87#ibcon#*mode == 0, iclass 26, count 2 2006.281.07:59:31.87#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.07:59:31.87#ibcon#[27=AT01-04\r\n] 2006.281.07:59:31.87#ibcon#*before write, iclass 26, count 2 2006.281.07:59:31.87#ibcon#enter sib2, iclass 26, count 2 2006.281.07:59:31.87#ibcon#flushed, iclass 26, count 2 2006.281.07:59:31.87#ibcon#about to write, iclass 26, count 2 2006.281.07:59:31.87#ibcon#wrote, iclass 26, count 2 2006.281.07:59:31.87#ibcon#about to read 3, iclass 26, count 2 2006.281.07:59:31.90#ibcon#read 3, iclass 26, count 2 2006.281.07:59:31.90#ibcon#about to read 4, iclass 26, count 2 2006.281.07:59:31.90#ibcon#read 4, iclass 26, count 2 2006.281.07:59:31.90#ibcon#about to read 5, iclass 26, count 2 2006.281.07:59:31.90#ibcon#read 5, iclass 26, count 2 2006.281.07:59:31.90#ibcon#about to read 6, iclass 26, count 2 2006.281.07:59:31.90#ibcon#read 6, iclass 26, count 2 2006.281.07:59:31.90#ibcon#end of sib2, iclass 26, count 2 2006.281.07:59:31.90#ibcon#*after write, iclass 26, count 2 2006.281.07:59:31.90#ibcon#*before return 0, iclass 26, count 2 2006.281.07:59:31.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:31.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.07:59:31.90#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.07:59:31.90#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:31.90#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:32.02#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:32.02#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:32.02#ibcon#enter wrdev, iclass 26, count 0 2006.281.07:59:32.02#ibcon#first serial, iclass 26, count 0 2006.281.07:59:32.02#ibcon#enter sib2, iclass 26, count 0 2006.281.07:59:32.02#ibcon#flushed, iclass 26, count 0 2006.281.07:59:32.02#ibcon#about to write, iclass 26, count 0 2006.281.07:59:32.02#ibcon#wrote, iclass 26, count 0 2006.281.07:59:32.02#ibcon#about to read 3, iclass 26, count 0 2006.281.07:59:32.04#ibcon#read 3, iclass 26, count 0 2006.281.07:59:32.04#ibcon#about to read 4, iclass 26, count 0 2006.281.07:59:32.04#ibcon#read 4, iclass 26, count 0 2006.281.07:59:32.04#ibcon#about to read 5, iclass 26, count 0 2006.281.07:59:32.04#ibcon#read 5, iclass 26, count 0 2006.281.07:59:32.04#ibcon#about to read 6, iclass 26, count 0 2006.281.07:59:32.04#ibcon#read 6, iclass 26, count 0 2006.281.07:59:32.04#ibcon#end of sib2, iclass 26, count 0 2006.281.07:59:32.04#ibcon#*mode == 0, iclass 26, count 0 2006.281.07:59:32.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.07:59:32.04#ibcon#[27=USB\r\n] 2006.281.07:59:32.04#ibcon#*before write, iclass 26, count 0 2006.281.07:59:32.04#ibcon#enter sib2, iclass 26, count 0 2006.281.07:59:32.04#ibcon#flushed, iclass 26, count 0 2006.281.07:59:32.04#ibcon#about to write, iclass 26, count 0 2006.281.07:59:32.04#ibcon#wrote, iclass 26, count 0 2006.281.07:59:32.04#ibcon#about to read 3, iclass 26, count 0 2006.281.07:59:32.07#ibcon#read 3, iclass 26, count 0 2006.281.07:59:32.07#ibcon#about to read 4, iclass 26, count 0 2006.281.07:59:32.07#ibcon#read 4, iclass 26, count 0 2006.281.07:59:32.07#ibcon#about to read 5, iclass 26, count 0 2006.281.07:59:32.07#ibcon#read 5, iclass 26, count 0 2006.281.07:59:32.07#ibcon#about to read 6, iclass 26, count 0 2006.281.07:59:32.07#ibcon#read 6, iclass 26, count 0 2006.281.07:59:32.07#ibcon#end of sib2, iclass 26, count 0 2006.281.07:59:32.07#ibcon#*after write, iclass 26, count 0 2006.281.07:59:32.07#ibcon#*before return 0, iclass 26, count 0 2006.281.07:59:32.07#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:32.07#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.07:59:32.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.07:59:32.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.07:59:32.07$vc4f8/vblo=2,640.99 2006.281.07:59:32.07#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.07:59:32.07#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.07:59:32.07#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:32.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:32.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:32.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:32.07#ibcon#enter wrdev, iclass 28, count 0 2006.281.07:59:32.07#ibcon#first serial, iclass 28, count 0 2006.281.07:59:32.07#ibcon#enter sib2, iclass 28, count 0 2006.281.07:59:32.07#ibcon#flushed, iclass 28, count 0 2006.281.07:59:32.07#ibcon#about to write, iclass 28, count 0 2006.281.07:59:32.07#ibcon#wrote, iclass 28, count 0 2006.281.07:59:32.07#ibcon#about to read 3, iclass 28, count 0 2006.281.07:59:32.09#ibcon#read 3, iclass 28, count 0 2006.281.07:59:32.09#ibcon#about to read 4, iclass 28, count 0 2006.281.07:59:32.09#ibcon#read 4, iclass 28, count 0 2006.281.07:59:32.09#ibcon#about to read 5, iclass 28, count 0 2006.281.07:59:32.09#ibcon#read 5, iclass 28, count 0 2006.281.07:59:32.09#ibcon#about to read 6, iclass 28, count 0 2006.281.07:59:32.09#ibcon#read 6, iclass 28, count 0 2006.281.07:59:32.09#ibcon#end of sib2, iclass 28, count 0 2006.281.07:59:32.09#ibcon#*mode == 0, iclass 28, count 0 2006.281.07:59:32.09#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.07:59:32.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.07:59:32.11#ibcon#*before write, iclass 28, count 0 2006.281.07:59:32.11#ibcon#enter sib2, iclass 28, count 0 2006.281.07:59:32.11#ibcon#flushed, iclass 28, count 0 2006.281.07:59:32.11#ibcon#about to write, iclass 28, count 0 2006.281.07:59:32.11#ibcon#wrote, iclass 28, count 0 2006.281.07:59:32.11#ibcon#about to read 3, iclass 28, count 0 2006.281.07:59:32.15#ibcon#read 3, iclass 28, count 0 2006.281.07:59:32.15#ibcon#about to read 4, iclass 28, count 0 2006.281.07:59:32.15#ibcon#read 4, iclass 28, count 0 2006.281.07:59:32.15#ibcon#about to read 5, iclass 28, count 0 2006.281.07:59:32.15#ibcon#read 5, iclass 28, count 0 2006.281.07:59:32.15#ibcon#about to read 6, iclass 28, count 0 2006.281.07:59:32.15#ibcon#read 6, iclass 28, count 0 2006.281.07:59:32.15#ibcon#end of sib2, iclass 28, count 0 2006.281.07:59:32.15#ibcon#*after write, iclass 28, count 0 2006.281.07:59:32.15#ibcon#*before return 0, iclass 28, count 0 2006.281.07:59:32.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:32.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.07:59:32.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.07:59:32.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.07:59:32.15$vc4f8/vb=2,5 2006.281.07:59:32.15#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.07:59:32.15#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.07:59:32.15#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:32.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:32.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:32.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:32.19#ibcon#enter wrdev, iclass 30, count 2 2006.281.07:59:32.19#ibcon#first serial, iclass 30, count 2 2006.281.07:59:32.19#ibcon#enter sib2, iclass 30, count 2 2006.281.07:59:32.19#ibcon#flushed, iclass 30, count 2 2006.281.07:59:32.19#ibcon#about to write, iclass 30, count 2 2006.281.07:59:32.19#ibcon#wrote, iclass 30, count 2 2006.281.07:59:32.19#ibcon#about to read 3, iclass 30, count 2 2006.281.07:59:32.21#ibcon#read 3, iclass 30, count 2 2006.281.07:59:32.21#ibcon#about to read 4, iclass 30, count 2 2006.281.07:59:32.21#ibcon#read 4, iclass 30, count 2 2006.281.07:59:32.21#ibcon#about to read 5, iclass 30, count 2 2006.281.07:59:32.21#ibcon#read 5, iclass 30, count 2 2006.281.07:59:32.21#ibcon#about to read 6, iclass 30, count 2 2006.281.07:59:32.21#ibcon#read 6, iclass 30, count 2 2006.281.07:59:32.21#ibcon#end of sib2, iclass 30, count 2 2006.281.07:59:32.21#ibcon#*mode == 0, iclass 30, count 2 2006.281.07:59:32.21#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.07:59:32.21#ibcon#[27=AT02-05\r\n] 2006.281.07:59:32.21#ibcon#*before write, iclass 30, count 2 2006.281.07:59:32.21#ibcon#enter sib2, iclass 30, count 2 2006.281.07:59:32.21#ibcon#flushed, iclass 30, count 2 2006.281.07:59:32.21#ibcon#about to write, iclass 30, count 2 2006.281.07:59:32.21#ibcon#wrote, iclass 30, count 2 2006.281.07:59:32.21#ibcon#about to read 3, iclass 30, count 2 2006.281.07:59:32.24#ibcon#read 3, iclass 30, count 2 2006.281.07:59:32.24#ibcon#about to read 4, iclass 30, count 2 2006.281.07:59:32.24#ibcon#read 4, iclass 30, count 2 2006.281.07:59:32.24#ibcon#about to read 5, iclass 30, count 2 2006.281.07:59:32.24#ibcon#read 5, iclass 30, count 2 2006.281.07:59:32.24#ibcon#about to read 6, iclass 30, count 2 2006.281.07:59:32.24#ibcon#read 6, iclass 30, count 2 2006.281.07:59:32.24#ibcon#end of sib2, iclass 30, count 2 2006.281.07:59:32.24#ibcon#*after write, iclass 30, count 2 2006.281.07:59:32.24#ibcon#*before return 0, iclass 30, count 2 2006.281.07:59:32.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:32.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.07:59:32.24#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.07:59:32.24#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:32.24#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:32.36#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:32.36#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:32.36#ibcon#enter wrdev, iclass 30, count 0 2006.281.07:59:32.36#ibcon#first serial, iclass 30, count 0 2006.281.07:59:32.36#ibcon#enter sib2, iclass 30, count 0 2006.281.07:59:32.36#ibcon#flushed, iclass 30, count 0 2006.281.07:59:32.36#ibcon#about to write, iclass 30, count 0 2006.281.07:59:32.36#ibcon#wrote, iclass 30, count 0 2006.281.07:59:32.36#ibcon#about to read 3, iclass 30, count 0 2006.281.07:59:32.38#ibcon#read 3, iclass 30, count 0 2006.281.07:59:32.38#ibcon#about to read 4, iclass 30, count 0 2006.281.07:59:32.38#ibcon#read 4, iclass 30, count 0 2006.281.07:59:32.38#ibcon#about to read 5, iclass 30, count 0 2006.281.07:59:32.38#ibcon#read 5, iclass 30, count 0 2006.281.07:59:32.38#ibcon#about to read 6, iclass 30, count 0 2006.281.07:59:32.38#ibcon#read 6, iclass 30, count 0 2006.281.07:59:32.38#ibcon#end of sib2, iclass 30, count 0 2006.281.07:59:32.38#ibcon#*mode == 0, iclass 30, count 0 2006.281.07:59:32.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.07:59:32.38#ibcon#[27=USB\r\n] 2006.281.07:59:32.38#ibcon#*before write, iclass 30, count 0 2006.281.07:59:32.38#ibcon#enter sib2, iclass 30, count 0 2006.281.07:59:32.38#ibcon#flushed, iclass 30, count 0 2006.281.07:59:32.38#ibcon#about to write, iclass 30, count 0 2006.281.07:59:32.38#ibcon#wrote, iclass 30, count 0 2006.281.07:59:32.38#ibcon#about to read 3, iclass 30, count 0 2006.281.07:59:32.41#ibcon#read 3, iclass 30, count 0 2006.281.07:59:32.41#ibcon#about to read 4, iclass 30, count 0 2006.281.07:59:32.41#ibcon#read 4, iclass 30, count 0 2006.281.07:59:32.41#ibcon#about to read 5, iclass 30, count 0 2006.281.07:59:32.41#ibcon#read 5, iclass 30, count 0 2006.281.07:59:32.41#ibcon#about to read 6, iclass 30, count 0 2006.281.07:59:32.41#ibcon#read 6, iclass 30, count 0 2006.281.07:59:32.41#ibcon#end of sib2, iclass 30, count 0 2006.281.07:59:32.41#ibcon#*after write, iclass 30, count 0 2006.281.07:59:32.41#ibcon#*before return 0, iclass 30, count 0 2006.281.07:59:32.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:32.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.07:59:32.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.07:59:32.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.07:59:32.41$vc4f8/vblo=3,656.99 2006.281.07:59:32.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.07:59:32.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.07:59:32.41#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:32.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:32.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:32.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:32.41#ibcon#enter wrdev, iclass 32, count 0 2006.281.07:59:32.41#ibcon#first serial, iclass 32, count 0 2006.281.07:59:32.41#ibcon#enter sib2, iclass 32, count 0 2006.281.07:59:32.41#ibcon#flushed, iclass 32, count 0 2006.281.07:59:32.41#ibcon#about to write, iclass 32, count 0 2006.281.07:59:32.41#ibcon#wrote, iclass 32, count 0 2006.281.07:59:32.41#ibcon#about to read 3, iclass 32, count 0 2006.281.07:59:32.43#ibcon#read 3, iclass 32, count 0 2006.281.07:59:32.43#ibcon#about to read 4, iclass 32, count 0 2006.281.07:59:32.43#ibcon#read 4, iclass 32, count 0 2006.281.07:59:32.43#ibcon#about to read 5, iclass 32, count 0 2006.281.07:59:32.43#ibcon#read 5, iclass 32, count 0 2006.281.07:59:32.43#ibcon#about to read 6, iclass 32, count 0 2006.281.07:59:32.43#ibcon#read 6, iclass 32, count 0 2006.281.07:59:32.43#ibcon#end of sib2, iclass 32, count 0 2006.281.07:59:32.43#ibcon#*mode == 0, iclass 32, count 0 2006.281.07:59:32.43#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.07:59:32.43#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.07:59:32.43#ibcon#*before write, iclass 32, count 0 2006.281.07:59:32.43#ibcon#enter sib2, iclass 32, count 0 2006.281.07:59:32.43#ibcon#flushed, iclass 32, count 0 2006.281.07:59:32.43#ibcon#about to write, iclass 32, count 0 2006.281.07:59:32.43#ibcon#wrote, iclass 32, count 0 2006.281.07:59:32.43#ibcon#about to read 3, iclass 32, count 0 2006.281.07:59:32.47#ibcon#read 3, iclass 32, count 0 2006.281.07:59:32.47#ibcon#about to read 4, iclass 32, count 0 2006.281.07:59:32.47#ibcon#read 4, iclass 32, count 0 2006.281.07:59:32.47#ibcon#about to read 5, iclass 32, count 0 2006.281.07:59:32.47#ibcon#read 5, iclass 32, count 0 2006.281.07:59:32.47#ibcon#about to read 6, iclass 32, count 0 2006.281.07:59:32.47#ibcon#read 6, iclass 32, count 0 2006.281.07:59:32.47#ibcon#end of sib2, iclass 32, count 0 2006.281.07:59:32.47#ibcon#*after write, iclass 32, count 0 2006.281.07:59:32.47#ibcon#*before return 0, iclass 32, count 0 2006.281.07:59:32.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:32.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.07:59:32.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.07:59:32.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.07:59:32.47$vc4f8/vb=3,4 2006.281.07:59:32.47#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.07:59:32.47#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.07:59:32.47#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:32.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:32.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:32.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:32.53#ibcon#enter wrdev, iclass 34, count 2 2006.281.07:59:32.53#ibcon#first serial, iclass 34, count 2 2006.281.07:59:32.53#ibcon#enter sib2, iclass 34, count 2 2006.281.07:59:32.53#ibcon#flushed, iclass 34, count 2 2006.281.07:59:32.53#ibcon#about to write, iclass 34, count 2 2006.281.07:59:32.53#ibcon#wrote, iclass 34, count 2 2006.281.07:59:32.53#ibcon#about to read 3, iclass 34, count 2 2006.281.07:59:32.55#ibcon#read 3, iclass 34, count 2 2006.281.07:59:32.55#ibcon#about to read 4, iclass 34, count 2 2006.281.07:59:32.55#ibcon#read 4, iclass 34, count 2 2006.281.07:59:32.55#ibcon#about to read 5, iclass 34, count 2 2006.281.07:59:32.55#ibcon#read 5, iclass 34, count 2 2006.281.07:59:32.55#ibcon#about to read 6, iclass 34, count 2 2006.281.07:59:32.55#ibcon#read 6, iclass 34, count 2 2006.281.07:59:32.55#ibcon#end of sib2, iclass 34, count 2 2006.281.07:59:32.55#ibcon#*mode == 0, iclass 34, count 2 2006.281.07:59:32.55#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.07:59:32.55#ibcon#[27=AT03-04\r\n] 2006.281.07:59:32.55#ibcon#*before write, iclass 34, count 2 2006.281.07:59:32.55#ibcon#enter sib2, iclass 34, count 2 2006.281.07:59:32.55#ibcon#flushed, iclass 34, count 2 2006.281.07:59:32.55#ibcon#about to write, iclass 34, count 2 2006.281.07:59:32.55#ibcon#wrote, iclass 34, count 2 2006.281.07:59:32.55#ibcon#about to read 3, iclass 34, count 2 2006.281.07:59:32.58#ibcon#read 3, iclass 34, count 2 2006.281.07:59:32.58#ibcon#about to read 4, iclass 34, count 2 2006.281.07:59:32.58#ibcon#read 4, iclass 34, count 2 2006.281.07:59:32.58#ibcon#about to read 5, iclass 34, count 2 2006.281.07:59:32.58#ibcon#read 5, iclass 34, count 2 2006.281.07:59:32.58#ibcon#about to read 6, iclass 34, count 2 2006.281.07:59:32.58#ibcon#read 6, iclass 34, count 2 2006.281.07:59:32.58#ibcon#end of sib2, iclass 34, count 2 2006.281.07:59:32.58#ibcon#*after write, iclass 34, count 2 2006.281.07:59:32.58#ibcon#*before return 0, iclass 34, count 2 2006.281.07:59:32.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:32.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.07:59:32.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.07:59:32.58#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:32.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:32.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:32.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:32.70#ibcon#enter wrdev, iclass 34, count 0 2006.281.07:59:32.70#ibcon#first serial, iclass 34, count 0 2006.281.07:59:32.70#ibcon#enter sib2, iclass 34, count 0 2006.281.07:59:32.70#ibcon#flushed, iclass 34, count 0 2006.281.07:59:32.70#ibcon#about to write, iclass 34, count 0 2006.281.07:59:32.70#ibcon#wrote, iclass 34, count 0 2006.281.07:59:32.70#ibcon#about to read 3, iclass 34, count 0 2006.281.07:59:32.72#ibcon#read 3, iclass 34, count 0 2006.281.07:59:32.72#ibcon#about to read 4, iclass 34, count 0 2006.281.07:59:32.72#ibcon#read 4, iclass 34, count 0 2006.281.07:59:32.72#ibcon#about to read 5, iclass 34, count 0 2006.281.07:59:32.72#ibcon#read 5, iclass 34, count 0 2006.281.07:59:32.72#ibcon#about to read 6, iclass 34, count 0 2006.281.07:59:32.72#ibcon#read 6, iclass 34, count 0 2006.281.07:59:32.72#ibcon#end of sib2, iclass 34, count 0 2006.281.07:59:32.72#ibcon#*mode == 0, iclass 34, count 0 2006.281.07:59:32.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.07:59:32.72#ibcon#[27=USB\r\n] 2006.281.07:59:32.72#ibcon#*before write, iclass 34, count 0 2006.281.07:59:32.72#ibcon#enter sib2, iclass 34, count 0 2006.281.07:59:32.72#ibcon#flushed, iclass 34, count 0 2006.281.07:59:32.72#ibcon#about to write, iclass 34, count 0 2006.281.07:59:32.72#ibcon#wrote, iclass 34, count 0 2006.281.07:59:32.72#ibcon#about to read 3, iclass 34, count 0 2006.281.07:59:32.75#ibcon#read 3, iclass 34, count 0 2006.281.07:59:32.75#ibcon#about to read 4, iclass 34, count 0 2006.281.07:59:32.75#ibcon#read 4, iclass 34, count 0 2006.281.07:59:32.75#ibcon#about to read 5, iclass 34, count 0 2006.281.07:59:32.75#ibcon#read 5, iclass 34, count 0 2006.281.07:59:32.75#ibcon#about to read 6, iclass 34, count 0 2006.281.07:59:32.75#ibcon#read 6, iclass 34, count 0 2006.281.07:59:32.75#ibcon#end of sib2, iclass 34, count 0 2006.281.07:59:32.75#ibcon#*after write, iclass 34, count 0 2006.281.07:59:32.75#ibcon#*before return 0, iclass 34, count 0 2006.281.07:59:32.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:32.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.07:59:32.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.07:59:32.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.07:59:32.75$vc4f8/vblo=4,712.99 2006.281.07:59:32.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.07:59:32.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.07:59:32.75#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:32.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:32.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:32.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:32.75#ibcon#enter wrdev, iclass 36, count 0 2006.281.07:59:32.75#ibcon#first serial, iclass 36, count 0 2006.281.07:59:32.75#ibcon#enter sib2, iclass 36, count 0 2006.281.07:59:32.75#ibcon#flushed, iclass 36, count 0 2006.281.07:59:32.75#ibcon#about to write, iclass 36, count 0 2006.281.07:59:32.75#ibcon#wrote, iclass 36, count 0 2006.281.07:59:32.75#ibcon#about to read 3, iclass 36, count 0 2006.281.07:59:32.77#ibcon#read 3, iclass 36, count 0 2006.281.07:59:32.77#ibcon#about to read 4, iclass 36, count 0 2006.281.07:59:32.77#ibcon#read 4, iclass 36, count 0 2006.281.07:59:32.77#ibcon#about to read 5, iclass 36, count 0 2006.281.07:59:32.77#ibcon#read 5, iclass 36, count 0 2006.281.07:59:32.77#ibcon#about to read 6, iclass 36, count 0 2006.281.07:59:32.77#ibcon#read 6, iclass 36, count 0 2006.281.07:59:32.77#ibcon#end of sib2, iclass 36, count 0 2006.281.07:59:32.77#ibcon#*mode == 0, iclass 36, count 0 2006.281.07:59:32.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.07:59:32.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.07:59:32.77#ibcon#*before write, iclass 36, count 0 2006.281.07:59:32.77#ibcon#enter sib2, iclass 36, count 0 2006.281.07:59:32.77#ibcon#flushed, iclass 36, count 0 2006.281.07:59:32.77#ibcon#about to write, iclass 36, count 0 2006.281.07:59:32.77#ibcon#wrote, iclass 36, count 0 2006.281.07:59:32.77#ibcon#about to read 3, iclass 36, count 0 2006.281.07:59:32.81#ibcon#read 3, iclass 36, count 0 2006.281.07:59:32.81#ibcon#about to read 4, iclass 36, count 0 2006.281.07:59:32.81#ibcon#read 4, iclass 36, count 0 2006.281.07:59:32.81#ibcon#about to read 5, iclass 36, count 0 2006.281.07:59:32.81#ibcon#read 5, iclass 36, count 0 2006.281.07:59:32.81#ibcon#about to read 6, iclass 36, count 0 2006.281.07:59:32.81#ibcon#read 6, iclass 36, count 0 2006.281.07:59:32.81#ibcon#end of sib2, iclass 36, count 0 2006.281.07:59:32.81#ibcon#*after write, iclass 36, count 0 2006.281.07:59:32.81#ibcon#*before return 0, iclass 36, count 0 2006.281.07:59:32.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:32.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.07:59:32.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.07:59:32.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.07:59:32.81$vc4f8/vb=4,4 2006.281.07:59:32.82#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.07:59:32.82#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.07:59:32.82#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:32.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:32.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:32.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:32.87#ibcon#enter wrdev, iclass 38, count 2 2006.281.07:59:32.87#ibcon#first serial, iclass 38, count 2 2006.281.07:59:32.87#ibcon#enter sib2, iclass 38, count 2 2006.281.07:59:32.87#ibcon#flushed, iclass 38, count 2 2006.281.07:59:32.87#ibcon#about to write, iclass 38, count 2 2006.281.07:59:32.87#ibcon#wrote, iclass 38, count 2 2006.281.07:59:32.87#ibcon#about to read 3, iclass 38, count 2 2006.281.07:59:32.89#ibcon#read 3, iclass 38, count 2 2006.281.07:59:32.89#ibcon#about to read 4, iclass 38, count 2 2006.281.07:59:32.89#ibcon#read 4, iclass 38, count 2 2006.281.07:59:32.89#ibcon#about to read 5, iclass 38, count 2 2006.281.07:59:32.89#ibcon#read 5, iclass 38, count 2 2006.281.07:59:32.89#ibcon#about to read 6, iclass 38, count 2 2006.281.07:59:32.89#ibcon#read 6, iclass 38, count 2 2006.281.07:59:32.89#ibcon#end of sib2, iclass 38, count 2 2006.281.07:59:32.89#ibcon#*mode == 0, iclass 38, count 2 2006.281.07:59:32.89#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.07:59:32.89#ibcon#[27=AT04-04\r\n] 2006.281.07:59:32.89#ibcon#*before write, iclass 38, count 2 2006.281.07:59:32.89#ibcon#enter sib2, iclass 38, count 2 2006.281.07:59:32.89#ibcon#flushed, iclass 38, count 2 2006.281.07:59:32.89#ibcon#about to write, iclass 38, count 2 2006.281.07:59:32.89#ibcon#wrote, iclass 38, count 2 2006.281.07:59:32.89#ibcon#about to read 3, iclass 38, count 2 2006.281.07:59:32.92#ibcon#read 3, iclass 38, count 2 2006.281.07:59:32.92#ibcon#about to read 4, iclass 38, count 2 2006.281.07:59:32.92#ibcon#read 4, iclass 38, count 2 2006.281.07:59:32.92#ibcon#about to read 5, iclass 38, count 2 2006.281.07:59:32.92#ibcon#read 5, iclass 38, count 2 2006.281.07:59:32.92#ibcon#about to read 6, iclass 38, count 2 2006.281.07:59:32.92#ibcon#read 6, iclass 38, count 2 2006.281.07:59:32.92#ibcon#end of sib2, iclass 38, count 2 2006.281.07:59:32.92#ibcon#*after write, iclass 38, count 2 2006.281.07:59:32.92#ibcon#*before return 0, iclass 38, count 2 2006.281.07:59:32.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:32.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.07:59:32.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.07:59:32.92#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:32.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:33.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:33.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:33.04#ibcon#enter wrdev, iclass 38, count 0 2006.281.07:59:33.04#ibcon#first serial, iclass 38, count 0 2006.281.07:59:33.04#ibcon#enter sib2, iclass 38, count 0 2006.281.07:59:33.04#ibcon#flushed, iclass 38, count 0 2006.281.07:59:33.04#ibcon#about to write, iclass 38, count 0 2006.281.07:59:33.04#ibcon#wrote, iclass 38, count 0 2006.281.07:59:33.04#ibcon#about to read 3, iclass 38, count 0 2006.281.07:59:33.06#ibcon#read 3, iclass 38, count 0 2006.281.07:59:33.06#ibcon#about to read 4, iclass 38, count 0 2006.281.07:59:33.06#ibcon#read 4, iclass 38, count 0 2006.281.07:59:33.06#ibcon#about to read 5, iclass 38, count 0 2006.281.07:59:33.06#ibcon#read 5, iclass 38, count 0 2006.281.07:59:33.06#ibcon#about to read 6, iclass 38, count 0 2006.281.07:59:33.06#ibcon#read 6, iclass 38, count 0 2006.281.07:59:33.06#ibcon#end of sib2, iclass 38, count 0 2006.281.07:59:33.06#ibcon#*mode == 0, iclass 38, count 0 2006.281.07:59:33.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.07:59:33.06#ibcon#[27=USB\r\n] 2006.281.07:59:33.06#ibcon#*before write, iclass 38, count 0 2006.281.07:59:33.06#ibcon#enter sib2, iclass 38, count 0 2006.281.07:59:33.06#ibcon#flushed, iclass 38, count 0 2006.281.07:59:33.06#ibcon#about to write, iclass 38, count 0 2006.281.07:59:33.06#ibcon#wrote, iclass 38, count 0 2006.281.07:59:33.06#ibcon#about to read 3, iclass 38, count 0 2006.281.07:59:33.09#ibcon#read 3, iclass 38, count 0 2006.281.07:59:33.09#ibcon#about to read 4, iclass 38, count 0 2006.281.07:59:33.09#ibcon#read 4, iclass 38, count 0 2006.281.07:59:33.09#ibcon#about to read 5, iclass 38, count 0 2006.281.07:59:33.09#ibcon#read 5, iclass 38, count 0 2006.281.07:59:33.09#ibcon#about to read 6, iclass 38, count 0 2006.281.07:59:33.09#ibcon#read 6, iclass 38, count 0 2006.281.07:59:33.09#ibcon#end of sib2, iclass 38, count 0 2006.281.07:59:33.09#ibcon#*after write, iclass 38, count 0 2006.281.07:59:33.09#ibcon#*before return 0, iclass 38, count 0 2006.281.07:59:33.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:33.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.07:59:33.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.07:59:33.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.07:59:33.09$vc4f8/vblo=5,744.99 2006.281.07:59:33.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.07:59:33.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.07:59:33.09#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:33.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:33.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:33.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:33.09#ibcon#enter wrdev, iclass 40, count 0 2006.281.07:59:33.09#ibcon#first serial, iclass 40, count 0 2006.281.07:59:33.09#ibcon#enter sib2, iclass 40, count 0 2006.281.07:59:33.09#ibcon#flushed, iclass 40, count 0 2006.281.07:59:33.09#ibcon#about to write, iclass 40, count 0 2006.281.07:59:33.09#ibcon#wrote, iclass 40, count 0 2006.281.07:59:33.09#ibcon#about to read 3, iclass 40, count 0 2006.281.07:59:33.11#ibcon#read 3, iclass 40, count 0 2006.281.07:59:33.11#ibcon#about to read 4, iclass 40, count 0 2006.281.07:59:33.11#ibcon#read 4, iclass 40, count 0 2006.281.07:59:33.11#ibcon#about to read 5, iclass 40, count 0 2006.281.07:59:33.11#ibcon#read 5, iclass 40, count 0 2006.281.07:59:33.11#ibcon#about to read 6, iclass 40, count 0 2006.281.07:59:33.11#ibcon#read 6, iclass 40, count 0 2006.281.07:59:33.11#ibcon#end of sib2, iclass 40, count 0 2006.281.07:59:33.11#ibcon#*mode == 0, iclass 40, count 0 2006.281.07:59:33.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.07:59:33.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.07:59:33.11#ibcon#*before write, iclass 40, count 0 2006.281.07:59:33.11#ibcon#enter sib2, iclass 40, count 0 2006.281.07:59:33.11#ibcon#flushed, iclass 40, count 0 2006.281.07:59:33.11#ibcon#about to write, iclass 40, count 0 2006.281.07:59:33.11#ibcon#wrote, iclass 40, count 0 2006.281.07:59:33.11#ibcon#about to read 3, iclass 40, count 0 2006.281.07:59:33.15#ibcon#read 3, iclass 40, count 0 2006.281.07:59:33.15#ibcon#about to read 4, iclass 40, count 0 2006.281.07:59:33.15#ibcon#read 4, iclass 40, count 0 2006.281.07:59:33.15#ibcon#about to read 5, iclass 40, count 0 2006.281.07:59:33.15#ibcon#read 5, iclass 40, count 0 2006.281.07:59:33.15#ibcon#about to read 6, iclass 40, count 0 2006.281.07:59:33.15#ibcon#read 6, iclass 40, count 0 2006.281.07:59:33.15#ibcon#end of sib2, iclass 40, count 0 2006.281.07:59:33.15#ibcon#*after write, iclass 40, count 0 2006.281.07:59:33.15#ibcon#*before return 0, iclass 40, count 0 2006.281.07:59:33.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:33.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.07:59:33.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.07:59:33.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.07:59:33.15$vc4f8/vb=5,4 2006.281.07:59:33.15#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.07:59:33.15#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.07:59:33.15#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:33.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:33.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:33.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:33.21#ibcon#enter wrdev, iclass 4, count 2 2006.281.07:59:33.21#ibcon#first serial, iclass 4, count 2 2006.281.07:59:33.21#ibcon#enter sib2, iclass 4, count 2 2006.281.07:59:33.21#ibcon#flushed, iclass 4, count 2 2006.281.07:59:33.21#ibcon#about to write, iclass 4, count 2 2006.281.07:59:33.21#ibcon#wrote, iclass 4, count 2 2006.281.07:59:33.21#ibcon#about to read 3, iclass 4, count 2 2006.281.07:59:33.23#ibcon#read 3, iclass 4, count 2 2006.281.07:59:33.23#ibcon#about to read 4, iclass 4, count 2 2006.281.07:59:33.23#ibcon#read 4, iclass 4, count 2 2006.281.07:59:33.23#ibcon#about to read 5, iclass 4, count 2 2006.281.07:59:33.23#ibcon#read 5, iclass 4, count 2 2006.281.07:59:33.23#ibcon#about to read 6, iclass 4, count 2 2006.281.07:59:33.23#ibcon#read 6, iclass 4, count 2 2006.281.07:59:33.23#ibcon#end of sib2, iclass 4, count 2 2006.281.07:59:33.23#ibcon#*mode == 0, iclass 4, count 2 2006.281.07:59:33.23#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.07:59:33.23#ibcon#[27=AT05-04\r\n] 2006.281.07:59:33.23#ibcon#*before write, iclass 4, count 2 2006.281.07:59:33.23#ibcon#enter sib2, iclass 4, count 2 2006.281.07:59:33.23#ibcon#flushed, iclass 4, count 2 2006.281.07:59:33.23#ibcon#about to write, iclass 4, count 2 2006.281.07:59:33.23#ibcon#wrote, iclass 4, count 2 2006.281.07:59:33.23#ibcon#about to read 3, iclass 4, count 2 2006.281.07:59:33.26#ibcon#read 3, iclass 4, count 2 2006.281.07:59:33.26#ibcon#about to read 4, iclass 4, count 2 2006.281.07:59:33.26#ibcon#read 4, iclass 4, count 2 2006.281.07:59:33.26#ibcon#about to read 5, iclass 4, count 2 2006.281.07:59:33.26#ibcon#read 5, iclass 4, count 2 2006.281.07:59:33.26#ibcon#about to read 6, iclass 4, count 2 2006.281.07:59:33.26#ibcon#read 6, iclass 4, count 2 2006.281.07:59:33.26#ibcon#end of sib2, iclass 4, count 2 2006.281.07:59:33.26#ibcon#*after write, iclass 4, count 2 2006.281.07:59:33.26#ibcon#*before return 0, iclass 4, count 2 2006.281.07:59:33.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:33.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.07:59:33.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.07:59:33.26#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:33.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:33.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:33.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:33.38#ibcon#enter wrdev, iclass 4, count 0 2006.281.07:59:33.38#ibcon#first serial, iclass 4, count 0 2006.281.07:59:33.38#ibcon#enter sib2, iclass 4, count 0 2006.281.07:59:33.38#ibcon#flushed, iclass 4, count 0 2006.281.07:59:33.38#ibcon#about to write, iclass 4, count 0 2006.281.07:59:33.38#ibcon#wrote, iclass 4, count 0 2006.281.07:59:33.38#ibcon#about to read 3, iclass 4, count 0 2006.281.07:59:33.40#ibcon#read 3, iclass 4, count 0 2006.281.07:59:33.40#ibcon#about to read 4, iclass 4, count 0 2006.281.07:59:33.40#ibcon#read 4, iclass 4, count 0 2006.281.07:59:33.40#ibcon#about to read 5, iclass 4, count 0 2006.281.07:59:33.40#ibcon#read 5, iclass 4, count 0 2006.281.07:59:33.40#ibcon#about to read 6, iclass 4, count 0 2006.281.07:59:33.40#ibcon#read 6, iclass 4, count 0 2006.281.07:59:33.40#ibcon#end of sib2, iclass 4, count 0 2006.281.07:59:33.40#ibcon#*mode == 0, iclass 4, count 0 2006.281.07:59:33.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.07:59:33.40#ibcon#[27=USB\r\n] 2006.281.07:59:33.40#ibcon#*before write, iclass 4, count 0 2006.281.07:59:33.40#ibcon#enter sib2, iclass 4, count 0 2006.281.07:59:33.40#ibcon#flushed, iclass 4, count 0 2006.281.07:59:33.40#ibcon#about to write, iclass 4, count 0 2006.281.07:59:33.40#ibcon#wrote, iclass 4, count 0 2006.281.07:59:33.40#ibcon#about to read 3, iclass 4, count 0 2006.281.07:59:33.43#ibcon#read 3, iclass 4, count 0 2006.281.07:59:33.43#ibcon#about to read 4, iclass 4, count 0 2006.281.07:59:33.43#ibcon#read 4, iclass 4, count 0 2006.281.07:59:33.43#ibcon#about to read 5, iclass 4, count 0 2006.281.07:59:33.43#ibcon#read 5, iclass 4, count 0 2006.281.07:59:33.43#ibcon#about to read 6, iclass 4, count 0 2006.281.07:59:33.43#ibcon#read 6, iclass 4, count 0 2006.281.07:59:33.43#ibcon#end of sib2, iclass 4, count 0 2006.281.07:59:33.43#ibcon#*after write, iclass 4, count 0 2006.281.07:59:33.43#ibcon#*before return 0, iclass 4, count 0 2006.281.07:59:33.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:33.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.07:59:33.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.07:59:33.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.07:59:33.43$vc4f8/vblo=6,752.99 2006.281.07:59:33.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.07:59:33.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.07:59:33.43#ibcon#ireg 17 cls_cnt 0 2006.281.07:59:33.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:33.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:33.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:33.43#ibcon#enter wrdev, iclass 6, count 0 2006.281.07:59:33.43#ibcon#first serial, iclass 6, count 0 2006.281.07:59:33.43#ibcon#enter sib2, iclass 6, count 0 2006.281.07:59:33.43#ibcon#flushed, iclass 6, count 0 2006.281.07:59:33.43#ibcon#about to write, iclass 6, count 0 2006.281.07:59:33.43#ibcon#wrote, iclass 6, count 0 2006.281.07:59:33.43#ibcon#about to read 3, iclass 6, count 0 2006.281.07:59:33.45#ibcon#read 3, iclass 6, count 0 2006.281.07:59:33.45#ibcon#about to read 4, iclass 6, count 0 2006.281.07:59:33.45#ibcon#read 4, iclass 6, count 0 2006.281.07:59:33.45#ibcon#about to read 5, iclass 6, count 0 2006.281.07:59:33.45#ibcon#read 5, iclass 6, count 0 2006.281.07:59:33.45#ibcon#about to read 6, iclass 6, count 0 2006.281.07:59:33.45#ibcon#read 6, iclass 6, count 0 2006.281.07:59:33.45#ibcon#end of sib2, iclass 6, count 0 2006.281.07:59:33.45#ibcon#*mode == 0, iclass 6, count 0 2006.281.07:59:33.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.07:59:33.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.07:59:33.45#ibcon#*before write, iclass 6, count 0 2006.281.07:59:33.45#ibcon#enter sib2, iclass 6, count 0 2006.281.07:59:33.45#ibcon#flushed, iclass 6, count 0 2006.281.07:59:33.45#ibcon#about to write, iclass 6, count 0 2006.281.07:59:33.45#ibcon#wrote, iclass 6, count 0 2006.281.07:59:33.45#ibcon#about to read 3, iclass 6, count 0 2006.281.07:59:33.49#ibcon#read 3, iclass 6, count 0 2006.281.07:59:33.49#ibcon#about to read 4, iclass 6, count 0 2006.281.07:59:33.49#ibcon#read 4, iclass 6, count 0 2006.281.07:59:33.49#ibcon#about to read 5, iclass 6, count 0 2006.281.07:59:33.49#ibcon#read 5, iclass 6, count 0 2006.281.07:59:33.49#ibcon#about to read 6, iclass 6, count 0 2006.281.07:59:33.49#ibcon#read 6, iclass 6, count 0 2006.281.07:59:33.49#ibcon#end of sib2, iclass 6, count 0 2006.281.07:59:33.49#ibcon#*after write, iclass 6, count 0 2006.281.07:59:33.49#ibcon#*before return 0, iclass 6, count 0 2006.281.07:59:33.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:33.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.07:59:33.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.07:59:33.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.07:59:33.49$vc4f8/vb=6,4 2006.281.07:59:33.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.07:59:33.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.07:59:33.49#ibcon#ireg 11 cls_cnt 2 2006.281.07:59:33.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:33.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:33.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:33.55#ibcon#enter wrdev, iclass 10, count 2 2006.281.07:59:33.55#ibcon#first serial, iclass 10, count 2 2006.281.07:59:33.55#ibcon#enter sib2, iclass 10, count 2 2006.281.07:59:33.55#ibcon#flushed, iclass 10, count 2 2006.281.07:59:33.55#ibcon#about to write, iclass 10, count 2 2006.281.07:59:33.55#ibcon#wrote, iclass 10, count 2 2006.281.07:59:33.55#ibcon#about to read 3, iclass 10, count 2 2006.281.07:59:33.57#ibcon#read 3, iclass 10, count 2 2006.281.07:59:33.57#ibcon#about to read 4, iclass 10, count 2 2006.281.07:59:33.57#ibcon#read 4, iclass 10, count 2 2006.281.07:59:33.57#ibcon#about to read 5, iclass 10, count 2 2006.281.07:59:33.57#ibcon#read 5, iclass 10, count 2 2006.281.07:59:33.57#ibcon#about to read 6, iclass 10, count 2 2006.281.07:59:33.57#ibcon#read 6, iclass 10, count 2 2006.281.07:59:33.57#ibcon#end of sib2, iclass 10, count 2 2006.281.07:59:33.57#ibcon#*mode == 0, iclass 10, count 2 2006.281.07:59:33.57#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.07:59:33.57#ibcon#[27=AT06-04\r\n] 2006.281.07:59:33.57#ibcon#*before write, iclass 10, count 2 2006.281.07:59:33.57#ibcon#enter sib2, iclass 10, count 2 2006.281.07:59:33.57#ibcon#flushed, iclass 10, count 2 2006.281.07:59:33.57#ibcon#about to write, iclass 10, count 2 2006.281.07:59:33.57#ibcon#wrote, iclass 10, count 2 2006.281.07:59:33.57#ibcon#about to read 3, iclass 10, count 2 2006.281.07:59:33.60#ibcon#read 3, iclass 10, count 2 2006.281.07:59:33.60#ibcon#about to read 4, iclass 10, count 2 2006.281.07:59:33.60#ibcon#read 4, iclass 10, count 2 2006.281.07:59:33.60#ibcon#about to read 5, iclass 10, count 2 2006.281.07:59:33.60#ibcon#read 5, iclass 10, count 2 2006.281.07:59:33.60#ibcon#about to read 6, iclass 10, count 2 2006.281.07:59:33.60#ibcon#read 6, iclass 10, count 2 2006.281.07:59:33.60#ibcon#end of sib2, iclass 10, count 2 2006.281.07:59:33.60#ibcon#*after write, iclass 10, count 2 2006.281.07:59:33.60#ibcon#*before return 0, iclass 10, count 2 2006.281.07:59:33.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:33.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.07:59:33.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.07:59:33.61#ibcon#ireg 7 cls_cnt 0 2006.281.07:59:33.61#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:33.71#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:33.71#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:33.71#ibcon#enter wrdev, iclass 10, count 0 2006.281.07:59:33.71#ibcon#first serial, iclass 10, count 0 2006.281.07:59:33.71#ibcon#enter sib2, iclass 10, count 0 2006.281.07:59:33.71#ibcon#flushed, iclass 10, count 0 2006.281.07:59:33.71#ibcon#about to write, iclass 10, count 0 2006.281.07:59:33.71#ibcon#wrote, iclass 10, count 0 2006.281.07:59:33.71#ibcon#about to read 3, iclass 10, count 0 2006.281.07:59:33.73#ibcon#read 3, iclass 10, count 0 2006.281.07:59:33.73#ibcon#about to read 4, iclass 10, count 0 2006.281.07:59:33.73#ibcon#read 4, iclass 10, count 0 2006.281.07:59:33.73#ibcon#about to read 5, iclass 10, count 0 2006.281.07:59:33.73#ibcon#read 5, iclass 10, count 0 2006.281.07:59:33.73#ibcon#about to read 6, iclass 10, count 0 2006.281.07:59:33.73#ibcon#read 6, iclass 10, count 0 2006.281.07:59:33.73#ibcon#end of sib2, iclass 10, count 0 2006.281.07:59:33.73#ibcon#*mode == 0, iclass 10, count 0 2006.281.07:59:33.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.07:59:33.73#ibcon#[27=USB\r\n] 2006.281.07:59:33.73#ibcon#*before write, iclass 10, count 0 2006.281.07:59:33.73#ibcon#enter sib2, iclass 10, count 0 2006.281.07:59:33.73#ibcon#flushed, iclass 10, count 0 2006.281.07:59:33.73#ibcon#about to write, iclass 10, count 0 2006.281.07:59:33.73#ibcon#wrote, iclass 10, count 0 2006.281.07:59:33.73#ibcon#about to read 3, iclass 10, count 0 2006.281.07:59:33.76#ibcon#read 3, iclass 10, count 0 2006.281.07:59:33.76#ibcon#about to read 4, iclass 10, count 0 2006.281.07:59:33.76#ibcon#read 4, iclass 10, count 0 2006.281.07:59:33.76#ibcon#about to read 5, iclass 10, count 0 2006.281.07:59:33.76#ibcon#read 5, iclass 10, count 0 2006.281.07:59:33.76#ibcon#about to read 6, iclass 10, count 0 2006.281.07:59:33.76#ibcon#read 6, iclass 10, count 0 2006.281.07:59:33.76#ibcon#end of sib2, iclass 10, count 0 2006.281.07:59:33.76#ibcon#*after write, iclass 10, count 0 2006.281.07:59:33.76#ibcon#*before return 0, iclass 10, count 0 2006.281.07:59:33.76#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:33.76#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.07:59:33.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.07:59:33.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.07:59:33.76$vc4f8/vabw=wide 2006.281.07:59:33.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.07:59:33.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.07:59:33.76#ibcon#ireg 8 cls_cnt 0 2006.281.07:59:33.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:33.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:33.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:33.76#ibcon#enter wrdev, iclass 12, count 0 2006.281.07:59:33.76#ibcon#first serial, iclass 12, count 0 2006.281.07:59:33.76#ibcon#enter sib2, iclass 12, count 0 2006.281.07:59:33.76#ibcon#flushed, iclass 12, count 0 2006.281.07:59:33.76#ibcon#about to write, iclass 12, count 0 2006.281.07:59:33.76#ibcon#wrote, iclass 12, count 0 2006.281.07:59:33.76#ibcon#about to read 3, iclass 12, count 0 2006.281.07:59:33.78#ibcon#read 3, iclass 12, count 0 2006.281.07:59:33.78#ibcon#about to read 4, iclass 12, count 0 2006.281.07:59:33.78#ibcon#read 4, iclass 12, count 0 2006.281.07:59:33.78#ibcon#about to read 5, iclass 12, count 0 2006.281.07:59:33.78#ibcon#read 5, iclass 12, count 0 2006.281.07:59:33.78#ibcon#about to read 6, iclass 12, count 0 2006.281.07:59:33.78#ibcon#read 6, iclass 12, count 0 2006.281.07:59:33.78#ibcon#end of sib2, iclass 12, count 0 2006.281.07:59:33.78#ibcon#*mode == 0, iclass 12, count 0 2006.281.07:59:33.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.07:59:33.78#ibcon#[25=BW32\r\n] 2006.281.07:59:33.78#ibcon#*before write, iclass 12, count 0 2006.281.07:59:33.78#ibcon#enter sib2, iclass 12, count 0 2006.281.07:59:33.78#ibcon#flushed, iclass 12, count 0 2006.281.07:59:33.78#ibcon#about to write, iclass 12, count 0 2006.281.07:59:33.78#ibcon#wrote, iclass 12, count 0 2006.281.07:59:33.78#ibcon#about to read 3, iclass 12, count 0 2006.281.07:59:33.81#ibcon#read 3, iclass 12, count 0 2006.281.07:59:33.81#ibcon#about to read 4, iclass 12, count 0 2006.281.07:59:33.81#ibcon#read 4, iclass 12, count 0 2006.281.07:59:33.81#ibcon#about to read 5, iclass 12, count 0 2006.281.07:59:33.81#ibcon#read 5, iclass 12, count 0 2006.281.07:59:33.81#ibcon#about to read 6, iclass 12, count 0 2006.281.07:59:33.81#ibcon#read 6, iclass 12, count 0 2006.281.07:59:33.81#ibcon#end of sib2, iclass 12, count 0 2006.281.07:59:33.81#ibcon#*after write, iclass 12, count 0 2006.281.07:59:33.81#ibcon#*before return 0, iclass 12, count 0 2006.281.07:59:33.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:33.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.07:59:33.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.07:59:33.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.07:59:33.81$vc4f8/vbbw=wide 2006.281.07:59:33.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.07:59:33.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.07:59:33.81#ibcon#ireg 8 cls_cnt 0 2006.281.07:59:33.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:59:33.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:59:33.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:59:33.88#ibcon#enter wrdev, iclass 14, count 0 2006.281.07:59:33.88#ibcon#first serial, iclass 14, count 0 2006.281.07:59:33.88#ibcon#enter sib2, iclass 14, count 0 2006.281.07:59:33.88#ibcon#flushed, iclass 14, count 0 2006.281.07:59:33.88#ibcon#about to write, iclass 14, count 0 2006.281.07:59:33.88#ibcon#wrote, iclass 14, count 0 2006.281.07:59:33.88#ibcon#about to read 3, iclass 14, count 0 2006.281.07:59:33.90#ibcon#read 3, iclass 14, count 0 2006.281.07:59:33.90#ibcon#about to read 4, iclass 14, count 0 2006.281.07:59:33.90#ibcon#read 4, iclass 14, count 0 2006.281.07:59:33.90#ibcon#about to read 5, iclass 14, count 0 2006.281.07:59:33.90#ibcon#read 5, iclass 14, count 0 2006.281.07:59:33.90#ibcon#about to read 6, iclass 14, count 0 2006.281.07:59:33.90#ibcon#read 6, iclass 14, count 0 2006.281.07:59:33.90#ibcon#end of sib2, iclass 14, count 0 2006.281.07:59:33.90#ibcon#*mode == 0, iclass 14, count 0 2006.281.07:59:33.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.07:59:33.90#ibcon#[27=BW32\r\n] 2006.281.07:59:33.90#ibcon#*before write, iclass 14, count 0 2006.281.07:59:33.90#ibcon#enter sib2, iclass 14, count 0 2006.281.07:59:33.90#ibcon#flushed, iclass 14, count 0 2006.281.07:59:33.90#ibcon#about to write, iclass 14, count 0 2006.281.07:59:33.90#ibcon#wrote, iclass 14, count 0 2006.281.07:59:33.90#ibcon#about to read 3, iclass 14, count 0 2006.281.07:59:33.93#ibcon#read 3, iclass 14, count 0 2006.281.07:59:33.93#ibcon#about to read 4, iclass 14, count 0 2006.281.07:59:33.93#ibcon#read 4, iclass 14, count 0 2006.281.07:59:33.93#ibcon#about to read 5, iclass 14, count 0 2006.281.07:59:33.93#ibcon#read 5, iclass 14, count 0 2006.281.07:59:33.93#ibcon#about to read 6, iclass 14, count 0 2006.281.07:59:33.93#ibcon#read 6, iclass 14, count 0 2006.281.07:59:33.93#ibcon#end of sib2, iclass 14, count 0 2006.281.07:59:33.93#ibcon#*after write, iclass 14, count 0 2006.281.07:59:33.93#ibcon#*before return 0, iclass 14, count 0 2006.281.07:59:33.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:59:33.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.07:59:33.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.07:59:33.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.07:59:33.93$4f8m12a/ifd4f 2006.281.07:59:33.93$ifd4f/lo= 2006.281.07:59:33.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.07:59:33.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.07:59:33.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.07:59:33.93$ifd4f/patch= 2006.281.07:59:33.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.07:59:33.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.07:59:33.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.07:59:33.93$4f8m12a/"form=m,16.000,1:2 2006.281.07:59:33.93$4f8m12a/"tpicd 2006.281.07:59:33.93$4f8m12a/echo=off 2006.281.07:59:33.93$4f8m12a/xlog=off 2006.281.07:59:33.93:!2006.281.08:00:00 2006.281.07:59:42.13#trakl#Source acquired 2006.281.07:59:44.13#flagr#flagr/antenna,acquired 2006.281.08:00:00.00:preob 2006.281.08:00:00.14#trakl#Off source 2006.281.08:00:00.14?ERROR st -7 Antenna off-source! 2006.281.08:00:00.14#trakl#az 292.255 el 41.590 azerr*cos(el) 0.0043 elerr -0.0167 2006.281.08:00:00.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:00:00.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:00:00.14/onsource/SLEWING 2006.281.08:00:00.14:!2006.281.08:00:10 2006.281.08:00:01.14#flagr#flagr/antenna,off-source 2006.281.08:00:06.14#trakl#Source re-acquired 2006.281.08:00:07.14#flagr#flagr/antenna,re-acquired 2006.281.08:00:10.00:data_valid=on 2006.281.08:00:10.00:midob 2006.281.08:00:11.14/onsource/TRACKING 2006.281.08:00:11.14/wx/20.53,1001.4,52 2006.281.08:00:11.23/cable/+6.4850E-03 2006.281.08:00:12.32/va/01,07,usb,yes,32,34 2006.281.08:00:12.32/va/02,06,usb,yes,30,31 2006.281.08:00:12.32/va/03,06,usb,yes,28,28 2006.281.08:00:12.32/va/04,06,usb,yes,31,33 2006.281.08:00:12.32/va/05,07,usb,yes,29,31 2006.281.08:00:12.32/va/06,06,usb,yes,29,28 2006.281.08:00:12.32/va/07,06,usb,yes,29,29 2006.281.08:00:12.32/va/08,06,usb,yes,31,30 2006.281.08:00:12.55/valo/01,532.99,yes,locked 2006.281.08:00:12.55/valo/02,572.99,yes,locked 2006.281.08:00:12.55/valo/03,672.99,yes,locked 2006.281.08:00:12.55/valo/04,832.99,yes,locked 2006.281.08:00:12.55/valo/05,652.99,yes,locked 2006.281.08:00:12.55/valo/06,772.99,yes,locked 2006.281.08:00:12.55/valo/07,832.99,yes,locked 2006.281.08:00:12.55/valo/08,852.99,yes,locked 2006.281.08:00:13.64/vb/01,04,usb,yes,30,29 2006.281.08:00:13.64/vb/02,05,usb,yes,28,29 2006.281.08:00:13.64/vb/03,04,usb,yes,28,32 2006.281.08:00:13.64/vb/04,04,usb,yes,29,29 2006.281.08:00:13.64/vb/05,04,usb,yes,27,31 2006.281.08:00:13.64/vb/06,04,usb,yes,28,31 2006.281.08:00:13.64/vb/07,04,usb,yes,31,31 2006.281.08:00:13.64/vb/08,04,usb,yes,28,31 2006.281.08:00:13.87/vblo/01,632.99,yes,locked 2006.281.08:00:13.87/vblo/02,640.99,yes,locked 2006.281.08:00:13.87/vblo/03,656.99,yes,locked 2006.281.08:00:13.87/vblo/04,712.99,yes,locked 2006.281.08:00:13.87/vblo/05,744.99,yes,locked 2006.281.08:00:13.87/vblo/06,752.99,yes,locked 2006.281.08:00:13.87/vblo/07,734.99,yes,locked 2006.281.08:00:13.87/vblo/08,744.99,yes,locked 2006.281.08:00:14.02/vabw/8 2006.281.08:00:14.17/vbbw/8 2006.281.08:00:14.26/xfe/off,on,12.0 2006.281.08:00:14.64/ifatt/23,28,28,28 2006.281.08:00:15.08/fmout-gps/S +3.10E-07 2006.281.08:00:15.10:!2006.281.08:01:10 2006.281.08:00:16.14#trakl#Off source 2006.281.08:00:16.14?ERROR st -7 Antenna off-source! 2006.281.08:00:16.14#trakl#az 292.276 el 41.540 azerr*cos(el) -0.0033 elerr -0.0188 2006.281.08:00:18.14#flagr#flagr/antenna,off-source 2006.281.08:00:22.14#trakl#Source re-acquired 2006.281.08:00:24.14#flagr#flagr/antenna,re-acquired 2006.281.08:01:10.01:data_valid=off 2006.281.08:01:10.01:postob 2006.281.08:01:10.19/cable/+6.4849E-03 2006.281.08:01:10.19/wx/20.50,1001.4,51 2006.281.08:01:11.08/fmout-gps/S +3.14E-07 2006.281.08:01:11.08:scan_name=281-0802,k06281,60 2006.281.08:01:11.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.281.08:01:11.14#flagr#flagr/antenna,new-source 2006.281.08:01:12.14:checkk5 2006.281.08:01:12.56/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:01:13.02/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:01:13.45/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:01:13.85/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:01:14.27/chk_obsdata//k5ts1/T2810800??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:01:14.70/chk_obsdata//k5ts2/T2810800??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:01:15.08/chk_obsdata//k5ts3/T2810800??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:01:15.72/chk_obsdata//k5ts4/T2810800??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:01:16.43/k5log//k5ts1_log_newline 2006.281.08:01:17.16/k5log//k5ts2_log_newline 2006.281.08:01:18.20/k5log//k5ts3_log_newline 2006.281.08:01:19.11/k5log//k5ts4_log_newline 2006.281.08:01:19.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:01:19.13:4f8m12a=2 2006.281.08:01:19.13$4f8m12a/echo=on 2006.281.08:01:19.13$4f8m12a/pcalon 2006.281.08:01:19.13$pcalon/"no phase cal control is implemented here 2006.281.08:01:19.13$4f8m12a/"tpicd=stop 2006.281.08:01:19.13$4f8m12a/vc4f8 2006.281.08:01:19.13$vc4f8/valo=1,532.99 2006.281.08:01:19.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:01:19.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:01:19.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:19.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:19.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:19.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:19.14#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:01:19.14#ibcon#first serial, iclass 29, count 0 2006.281.08:01:19.14#ibcon#enter sib2, iclass 29, count 0 2006.281.08:01:19.14#ibcon#flushed, iclass 29, count 0 2006.281.08:01:19.14#ibcon#about to write, iclass 29, count 0 2006.281.08:01:19.14#ibcon#wrote, iclass 29, count 0 2006.281.08:01:19.14#ibcon#about to read 3, iclass 29, count 0 2006.281.08:01:19.16#ibcon#read 3, iclass 29, count 0 2006.281.08:01:19.16#ibcon#about to read 4, iclass 29, count 0 2006.281.08:01:19.16#ibcon#read 4, iclass 29, count 0 2006.281.08:01:19.16#ibcon#about to read 5, iclass 29, count 0 2006.281.08:01:19.16#ibcon#read 5, iclass 29, count 0 2006.281.08:01:19.16#ibcon#about to read 6, iclass 29, count 0 2006.281.08:01:19.16#ibcon#read 6, iclass 29, count 0 2006.281.08:01:19.16#ibcon#end of sib2, iclass 29, count 0 2006.281.08:01:19.16#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:01:19.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:01:19.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:01:19.16#ibcon#*before write, iclass 29, count 0 2006.281.08:01:19.16#ibcon#enter sib2, iclass 29, count 0 2006.281.08:01:19.16#ibcon#flushed, iclass 29, count 0 2006.281.08:01:19.16#ibcon#about to write, iclass 29, count 0 2006.281.08:01:19.16#ibcon#wrote, iclass 29, count 0 2006.281.08:01:19.16#ibcon#about to read 3, iclass 29, count 0 2006.281.08:01:19.21#ibcon#read 3, iclass 29, count 0 2006.281.08:01:19.21#ibcon#about to read 4, iclass 29, count 0 2006.281.08:01:19.21#ibcon#read 4, iclass 29, count 0 2006.281.08:01:19.21#ibcon#about to read 5, iclass 29, count 0 2006.281.08:01:19.21#ibcon#read 5, iclass 29, count 0 2006.281.08:01:19.21#ibcon#about to read 6, iclass 29, count 0 2006.281.08:01:19.21#ibcon#read 6, iclass 29, count 0 2006.281.08:01:19.21#ibcon#end of sib2, iclass 29, count 0 2006.281.08:01:19.21#ibcon#*after write, iclass 29, count 0 2006.281.08:01:19.21#ibcon#*before return 0, iclass 29, count 0 2006.281.08:01:19.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:19.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:19.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:01:19.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:01:19.21$vc4f8/va=1,7 2006.281.08:01:19.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:01:19.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:01:19.21#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:19.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:19.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:19.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:19.22#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:01:19.22#ibcon#first serial, iclass 31, count 2 2006.281.08:01:19.22#ibcon#enter sib2, iclass 31, count 2 2006.281.08:01:19.22#ibcon#flushed, iclass 31, count 2 2006.281.08:01:19.22#ibcon#about to write, iclass 31, count 2 2006.281.08:01:19.22#ibcon#wrote, iclass 31, count 2 2006.281.08:01:19.22#ibcon#about to read 3, iclass 31, count 2 2006.281.08:01:19.23#ibcon#read 3, iclass 31, count 2 2006.281.08:01:19.23#ibcon#about to read 4, iclass 31, count 2 2006.281.08:01:19.23#ibcon#read 4, iclass 31, count 2 2006.281.08:01:19.23#ibcon#about to read 5, iclass 31, count 2 2006.281.08:01:19.23#ibcon#read 5, iclass 31, count 2 2006.281.08:01:19.23#ibcon#about to read 6, iclass 31, count 2 2006.281.08:01:19.23#ibcon#read 6, iclass 31, count 2 2006.281.08:01:19.23#ibcon#end of sib2, iclass 31, count 2 2006.281.08:01:19.23#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:01:19.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:01:19.23#ibcon#[25=AT01-07\r\n] 2006.281.08:01:19.23#ibcon#*before write, iclass 31, count 2 2006.281.08:01:19.23#ibcon#enter sib2, iclass 31, count 2 2006.281.08:01:19.23#ibcon#flushed, iclass 31, count 2 2006.281.08:01:19.23#ibcon#about to write, iclass 31, count 2 2006.281.08:01:19.23#ibcon#wrote, iclass 31, count 2 2006.281.08:01:19.23#ibcon#about to read 3, iclass 31, count 2 2006.281.08:01:19.26#ibcon#read 3, iclass 31, count 2 2006.281.08:01:19.26#ibcon#about to read 4, iclass 31, count 2 2006.281.08:01:19.26#ibcon#read 4, iclass 31, count 2 2006.281.08:01:19.26#ibcon#about to read 5, iclass 31, count 2 2006.281.08:01:19.26#ibcon#read 5, iclass 31, count 2 2006.281.08:01:19.26#ibcon#about to read 6, iclass 31, count 2 2006.281.08:01:19.26#ibcon#read 6, iclass 31, count 2 2006.281.08:01:19.26#ibcon#end of sib2, iclass 31, count 2 2006.281.08:01:19.26#ibcon#*after write, iclass 31, count 2 2006.281.08:01:19.26#ibcon#*before return 0, iclass 31, count 2 2006.281.08:01:19.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:19.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:19.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:01:19.26#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:19.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:19.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:19.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:19.38#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:01:19.38#ibcon#first serial, iclass 31, count 0 2006.281.08:01:19.38#ibcon#enter sib2, iclass 31, count 0 2006.281.08:01:19.38#ibcon#flushed, iclass 31, count 0 2006.281.08:01:19.38#ibcon#about to write, iclass 31, count 0 2006.281.08:01:19.38#ibcon#wrote, iclass 31, count 0 2006.281.08:01:19.38#ibcon#about to read 3, iclass 31, count 0 2006.281.08:01:19.40#ibcon#read 3, iclass 31, count 0 2006.281.08:01:19.40#ibcon#about to read 4, iclass 31, count 0 2006.281.08:01:19.40#ibcon#read 4, iclass 31, count 0 2006.281.08:01:19.40#ibcon#about to read 5, iclass 31, count 0 2006.281.08:01:19.40#ibcon#read 5, iclass 31, count 0 2006.281.08:01:19.40#ibcon#about to read 6, iclass 31, count 0 2006.281.08:01:19.40#ibcon#read 6, iclass 31, count 0 2006.281.08:01:19.40#ibcon#end of sib2, iclass 31, count 0 2006.281.08:01:19.40#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:01:19.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:01:19.40#ibcon#[25=USB\r\n] 2006.281.08:01:19.40#ibcon#*before write, iclass 31, count 0 2006.281.08:01:19.40#ibcon#enter sib2, iclass 31, count 0 2006.281.08:01:19.40#ibcon#flushed, iclass 31, count 0 2006.281.08:01:19.40#ibcon#about to write, iclass 31, count 0 2006.281.08:01:19.40#ibcon#wrote, iclass 31, count 0 2006.281.08:01:19.40#ibcon#about to read 3, iclass 31, count 0 2006.281.08:01:19.43#ibcon#read 3, iclass 31, count 0 2006.281.08:01:19.43#ibcon#about to read 4, iclass 31, count 0 2006.281.08:01:19.43#ibcon#read 4, iclass 31, count 0 2006.281.08:01:19.43#ibcon#about to read 5, iclass 31, count 0 2006.281.08:01:19.43#ibcon#read 5, iclass 31, count 0 2006.281.08:01:19.43#ibcon#about to read 6, iclass 31, count 0 2006.281.08:01:19.43#ibcon#read 6, iclass 31, count 0 2006.281.08:01:19.43#ibcon#end of sib2, iclass 31, count 0 2006.281.08:01:19.43#ibcon#*after write, iclass 31, count 0 2006.281.08:01:19.43#ibcon#*before return 0, iclass 31, count 0 2006.281.08:01:19.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:19.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:19.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:01:19.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:01:19.43$vc4f8/valo=2,572.99 2006.281.08:01:19.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:01:19.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:01:19.43#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:19.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:19.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:19.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:19.43#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:01:19.43#ibcon#first serial, iclass 33, count 0 2006.281.08:01:19.43#ibcon#enter sib2, iclass 33, count 0 2006.281.08:01:19.43#ibcon#flushed, iclass 33, count 0 2006.281.08:01:19.43#ibcon#about to write, iclass 33, count 0 2006.281.08:01:19.43#ibcon#wrote, iclass 33, count 0 2006.281.08:01:19.43#ibcon#about to read 3, iclass 33, count 0 2006.281.08:01:19.45#ibcon#read 3, iclass 33, count 0 2006.281.08:01:19.45#ibcon#about to read 4, iclass 33, count 0 2006.281.08:01:19.45#ibcon#read 4, iclass 33, count 0 2006.281.08:01:19.45#ibcon#about to read 5, iclass 33, count 0 2006.281.08:01:19.45#ibcon#read 5, iclass 33, count 0 2006.281.08:01:19.45#ibcon#about to read 6, iclass 33, count 0 2006.281.08:01:19.45#ibcon#read 6, iclass 33, count 0 2006.281.08:01:19.45#ibcon#end of sib2, iclass 33, count 0 2006.281.08:01:19.45#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:01:19.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:01:19.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:01:19.45#ibcon#*before write, iclass 33, count 0 2006.281.08:01:19.45#ibcon#enter sib2, iclass 33, count 0 2006.281.08:01:19.45#ibcon#flushed, iclass 33, count 0 2006.281.08:01:19.45#ibcon#about to write, iclass 33, count 0 2006.281.08:01:19.45#ibcon#wrote, iclass 33, count 0 2006.281.08:01:19.45#ibcon#about to read 3, iclass 33, count 0 2006.281.08:01:19.49#ibcon#read 3, iclass 33, count 0 2006.281.08:01:19.49#ibcon#about to read 4, iclass 33, count 0 2006.281.08:01:19.49#ibcon#read 4, iclass 33, count 0 2006.281.08:01:19.49#ibcon#about to read 5, iclass 33, count 0 2006.281.08:01:19.49#ibcon#read 5, iclass 33, count 0 2006.281.08:01:19.49#ibcon#about to read 6, iclass 33, count 0 2006.281.08:01:19.49#ibcon#read 6, iclass 33, count 0 2006.281.08:01:19.49#ibcon#end of sib2, iclass 33, count 0 2006.281.08:01:19.49#ibcon#*after write, iclass 33, count 0 2006.281.08:01:19.49#ibcon#*before return 0, iclass 33, count 0 2006.281.08:01:19.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:19.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:19.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:01:19.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:01:19.49$vc4f8/va=2,6 2006.281.08:01:19.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:01:19.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:01:19.49#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:19.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:19.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:19.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:19.55#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:01:19.55#ibcon#first serial, iclass 35, count 2 2006.281.08:01:19.55#ibcon#enter sib2, iclass 35, count 2 2006.281.08:01:19.55#ibcon#flushed, iclass 35, count 2 2006.281.08:01:19.55#ibcon#about to write, iclass 35, count 2 2006.281.08:01:19.55#ibcon#wrote, iclass 35, count 2 2006.281.08:01:19.55#ibcon#about to read 3, iclass 35, count 2 2006.281.08:01:19.57#ibcon#read 3, iclass 35, count 2 2006.281.08:01:19.57#ibcon#about to read 4, iclass 35, count 2 2006.281.08:01:19.57#ibcon#read 4, iclass 35, count 2 2006.281.08:01:19.57#ibcon#about to read 5, iclass 35, count 2 2006.281.08:01:19.57#ibcon#read 5, iclass 35, count 2 2006.281.08:01:19.57#ibcon#about to read 6, iclass 35, count 2 2006.281.08:01:19.57#ibcon#read 6, iclass 35, count 2 2006.281.08:01:19.57#ibcon#end of sib2, iclass 35, count 2 2006.281.08:01:19.57#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:01:19.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:01:19.57#ibcon#[25=AT02-06\r\n] 2006.281.08:01:19.57#ibcon#*before write, iclass 35, count 2 2006.281.08:01:19.57#ibcon#enter sib2, iclass 35, count 2 2006.281.08:01:19.57#ibcon#flushed, iclass 35, count 2 2006.281.08:01:19.57#ibcon#about to write, iclass 35, count 2 2006.281.08:01:19.57#ibcon#wrote, iclass 35, count 2 2006.281.08:01:19.57#ibcon#about to read 3, iclass 35, count 2 2006.281.08:01:19.60#ibcon#read 3, iclass 35, count 2 2006.281.08:01:19.60#ibcon#about to read 4, iclass 35, count 2 2006.281.08:01:19.60#ibcon#read 4, iclass 35, count 2 2006.281.08:01:19.60#ibcon#about to read 5, iclass 35, count 2 2006.281.08:01:19.60#ibcon#read 5, iclass 35, count 2 2006.281.08:01:19.60#ibcon#about to read 6, iclass 35, count 2 2006.281.08:01:19.60#ibcon#read 6, iclass 35, count 2 2006.281.08:01:19.60#ibcon#end of sib2, iclass 35, count 2 2006.281.08:01:19.60#ibcon#*after write, iclass 35, count 2 2006.281.08:01:19.60#ibcon#*before return 0, iclass 35, count 2 2006.281.08:01:19.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:19.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:19.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:01:19.60#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:19.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:19.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:19.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:19.72#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:01:19.72#ibcon#first serial, iclass 35, count 0 2006.281.08:01:19.72#ibcon#enter sib2, iclass 35, count 0 2006.281.08:01:19.72#ibcon#flushed, iclass 35, count 0 2006.281.08:01:19.72#ibcon#about to write, iclass 35, count 0 2006.281.08:01:19.72#ibcon#wrote, iclass 35, count 0 2006.281.08:01:19.72#ibcon#about to read 3, iclass 35, count 0 2006.281.08:01:19.74#ibcon#read 3, iclass 35, count 0 2006.281.08:01:19.74#ibcon#about to read 4, iclass 35, count 0 2006.281.08:01:19.74#ibcon#read 4, iclass 35, count 0 2006.281.08:01:19.74#ibcon#about to read 5, iclass 35, count 0 2006.281.08:01:19.74#ibcon#read 5, iclass 35, count 0 2006.281.08:01:19.74#ibcon#about to read 6, iclass 35, count 0 2006.281.08:01:19.74#ibcon#read 6, iclass 35, count 0 2006.281.08:01:19.74#ibcon#end of sib2, iclass 35, count 0 2006.281.08:01:19.74#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:01:19.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:01:19.74#ibcon#[25=USB\r\n] 2006.281.08:01:19.74#ibcon#*before write, iclass 35, count 0 2006.281.08:01:19.74#ibcon#enter sib2, iclass 35, count 0 2006.281.08:01:19.74#ibcon#flushed, iclass 35, count 0 2006.281.08:01:19.74#ibcon#about to write, iclass 35, count 0 2006.281.08:01:19.74#ibcon#wrote, iclass 35, count 0 2006.281.08:01:19.74#ibcon#about to read 3, iclass 35, count 0 2006.281.08:01:19.77#ibcon#read 3, iclass 35, count 0 2006.281.08:01:19.77#ibcon#about to read 4, iclass 35, count 0 2006.281.08:01:19.77#ibcon#read 4, iclass 35, count 0 2006.281.08:01:19.77#ibcon#about to read 5, iclass 35, count 0 2006.281.08:01:19.77#ibcon#read 5, iclass 35, count 0 2006.281.08:01:19.77#ibcon#about to read 6, iclass 35, count 0 2006.281.08:01:19.77#ibcon#read 6, iclass 35, count 0 2006.281.08:01:19.77#ibcon#end of sib2, iclass 35, count 0 2006.281.08:01:19.77#ibcon#*after write, iclass 35, count 0 2006.281.08:01:19.77#ibcon#*before return 0, iclass 35, count 0 2006.281.08:01:19.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:19.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:19.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:01:19.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:01:19.77$vc4f8/valo=3,672.99 2006.281.08:01:19.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:01:19.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:01:19.77#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:19.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:19.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:19.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:19.77#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:01:19.77#ibcon#first serial, iclass 37, count 0 2006.281.08:01:19.77#ibcon#enter sib2, iclass 37, count 0 2006.281.08:01:19.77#ibcon#flushed, iclass 37, count 0 2006.281.08:01:19.77#ibcon#about to write, iclass 37, count 0 2006.281.08:01:19.77#ibcon#wrote, iclass 37, count 0 2006.281.08:01:19.77#ibcon#about to read 3, iclass 37, count 0 2006.281.08:01:19.79#ibcon#read 3, iclass 37, count 0 2006.281.08:01:19.79#ibcon#about to read 4, iclass 37, count 0 2006.281.08:01:19.79#ibcon#read 4, iclass 37, count 0 2006.281.08:01:19.79#ibcon#about to read 5, iclass 37, count 0 2006.281.08:01:19.79#ibcon#read 5, iclass 37, count 0 2006.281.08:01:19.79#ibcon#about to read 6, iclass 37, count 0 2006.281.08:01:19.79#ibcon#read 6, iclass 37, count 0 2006.281.08:01:19.79#ibcon#end of sib2, iclass 37, count 0 2006.281.08:01:19.79#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:01:19.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:01:19.81#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:01:19.81#ibcon#*before write, iclass 37, count 0 2006.281.08:01:19.81#ibcon#enter sib2, iclass 37, count 0 2006.281.08:01:19.81#ibcon#flushed, iclass 37, count 0 2006.281.08:01:19.81#ibcon#about to write, iclass 37, count 0 2006.281.08:01:19.81#ibcon#wrote, iclass 37, count 0 2006.281.08:01:19.81#ibcon#about to read 3, iclass 37, count 0 2006.281.08:01:19.85#ibcon#read 3, iclass 37, count 0 2006.281.08:01:19.85#ibcon#about to read 4, iclass 37, count 0 2006.281.08:01:19.85#ibcon#read 4, iclass 37, count 0 2006.281.08:01:19.85#ibcon#about to read 5, iclass 37, count 0 2006.281.08:01:19.85#ibcon#read 5, iclass 37, count 0 2006.281.08:01:19.85#ibcon#about to read 6, iclass 37, count 0 2006.281.08:01:19.85#ibcon#read 6, iclass 37, count 0 2006.281.08:01:19.85#ibcon#end of sib2, iclass 37, count 0 2006.281.08:01:19.85#ibcon#*after write, iclass 37, count 0 2006.281.08:01:19.85#ibcon#*before return 0, iclass 37, count 0 2006.281.08:01:19.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:19.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:19.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:01:19.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:01:19.85$vc4f8/va=3,6 2006.281.08:01:19.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.08:01:19.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.08:01:19.85#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:19.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:19.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:19.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:19.89#ibcon#enter wrdev, iclass 39, count 2 2006.281.08:01:19.89#ibcon#first serial, iclass 39, count 2 2006.281.08:01:19.89#ibcon#enter sib2, iclass 39, count 2 2006.281.08:01:19.89#ibcon#flushed, iclass 39, count 2 2006.281.08:01:19.89#ibcon#about to write, iclass 39, count 2 2006.281.08:01:19.89#ibcon#wrote, iclass 39, count 2 2006.281.08:01:19.89#ibcon#about to read 3, iclass 39, count 2 2006.281.08:01:19.91#ibcon#read 3, iclass 39, count 2 2006.281.08:01:19.91#ibcon#about to read 4, iclass 39, count 2 2006.281.08:01:19.91#ibcon#read 4, iclass 39, count 2 2006.281.08:01:19.91#ibcon#about to read 5, iclass 39, count 2 2006.281.08:01:19.91#ibcon#read 5, iclass 39, count 2 2006.281.08:01:19.91#ibcon#about to read 6, iclass 39, count 2 2006.281.08:01:19.91#ibcon#read 6, iclass 39, count 2 2006.281.08:01:19.91#ibcon#end of sib2, iclass 39, count 2 2006.281.08:01:19.91#ibcon#*mode == 0, iclass 39, count 2 2006.281.08:01:19.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.08:01:19.91#ibcon#[25=AT03-06\r\n] 2006.281.08:01:19.91#ibcon#*before write, iclass 39, count 2 2006.281.08:01:19.91#ibcon#enter sib2, iclass 39, count 2 2006.281.08:01:19.91#ibcon#flushed, iclass 39, count 2 2006.281.08:01:19.91#ibcon#about to write, iclass 39, count 2 2006.281.08:01:19.91#ibcon#wrote, iclass 39, count 2 2006.281.08:01:19.91#ibcon#about to read 3, iclass 39, count 2 2006.281.08:01:19.94#ibcon#read 3, iclass 39, count 2 2006.281.08:01:19.94#ibcon#about to read 4, iclass 39, count 2 2006.281.08:01:19.94#ibcon#read 4, iclass 39, count 2 2006.281.08:01:19.94#ibcon#about to read 5, iclass 39, count 2 2006.281.08:01:19.94#ibcon#read 5, iclass 39, count 2 2006.281.08:01:19.94#ibcon#about to read 6, iclass 39, count 2 2006.281.08:01:19.94#ibcon#read 6, iclass 39, count 2 2006.281.08:01:19.94#ibcon#end of sib2, iclass 39, count 2 2006.281.08:01:19.94#ibcon#*after write, iclass 39, count 2 2006.281.08:01:19.94#ibcon#*before return 0, iclass 39, count 2 2006.281.08:01:19.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:19.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:19.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.08:01:19.94#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:19.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:20.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:20.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:20.06#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:01:20.06#ibcon#first serial, iclass 39, count 0 2006.281.08:01:20.06#ibcon#enter sib2, iclass 39, count 0 2006.281.08:01:20.06#ibcon#flushed, iclass 39, count 0 2006.281.08:01:20.06#ibcon#about to write, iclass 39, count 0 2006.281.08:01:20.06#ibcon#wrote, iclass 39, count 0 2006.281.08:01:20.06#ibcon#about to read 3, iclass 39, count 0 2006.281.08:01:20.08#ibcon#read 3, iclass 39, count 0 2006.281.08:01:20.08#ibcon#about to read 4, iclass 39, count 0 2006.281.08:01:20.08#ibcon#read 4, iclass 39, count 0 2006.281.08:01:20.08#ibcon#about to read 5, iclass 39, count 0 2006.281.08:01:20.08#ibcon#read 5, iclass 39, count 0 2006.281.08:01:20.08#ibcon#about to read 6, iclass 39, count 0 2006.281.08:01:20.08#ibcon#read 6, iclass 39, count 0 2006.281.08:01:20.08#ibcon#end of sib2, iclass 39, count 0 2006.281.08:01:20.08#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:01:20.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:01:20.08#ibcon#[25=USB\r\n] 2006.281.08:01:20.08#ibcon#*before write, iclass 39, count 0 2006.281.08:01:20.08#ibcon#enter sib2, iclass 39, count 0 2006.281.08:01:20.08#ibcon#flushed, iclass 39, count 0 2006.281.08:01:20.08#ibcon#about to write, iclass 39, count 0 2006.281.08:01:20.08#ibcon#wrote, iclass 39, count 0 2006.281.08:01:20.08#ibcon#about to read 3, iclass 39, count 0 2006.281.08:01:20.11#ibcon#read 3, iclass 39, count 0 2006.281.08:01:20.11#ibcon#about to read 4, iclass 39, count 0 2006.281.08:01:20.11#ibcon#read 4, iclass 39, count 0 2006.281.08:01:20.11#ibcon#about to read 5, iclass 39, count 0 2006.281.08:01:20.11#ibcon#read 5, iclass 39, count 0 2006.281.08:01:20.11#ibcon#about to read 6, iclass 39, count 0 2006.281.08:01:20.11#ibcon#read 6, iclass 39, count 0 2006.281.08:01:20.11#ibcon#end of sib2, iclass 39, count 0 2006.281.08:01:20.11#ibcon#*after write, iclass 39, count 0 2006.281.08:01:20.11#ibcon#*before return 0, iclass 39, count 0 2006.281.08:01:20.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:20.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:20.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:01:20.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:01:20.11$vc4f8/valo=4,832.99 2006.281.08:01:20.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.08:01:20.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.08:01:20.11#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:20.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:01:20.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:01:20.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:01:20.11#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:01:20.11#ibcon#first serial, iclass 3, count 0 2006.281.08:01:20.11#ibcon#enter sib2, iclass 3, count 0 2006.281.08:01:20.11#ibcon#flushed, iclass 3, count 0 2006.281.08:01:20.11#ibcon#about to write, iclass 3, count 0 2006.281.08:01:20.11#ibcon#wrote, iclass 3, count 0 2006.281.08:01:20.11#ibcon#about to read 3, iclass 3, count 0 2006.281.08:01:20.13#ibcon#read 3, iclass 3, count 0 2006.281.08:01:20.13#ibcon#about to read 4, iclass 3, count 0 2006.281.08:01:20.13#ibcon#read 4, iclass 3, count 0 2006.281.08:01:20.13#ibcon#about to read 5, iclass 3, count 0 2006.281.08:01:20.13#ibcon#read 5, iclass 3, count 0 2006.281.08:01:20.13#ibcon#about to read 6, iclass 3, count 0 2006.281.08:01:20.13#ibcon#read 6, iclass 3, count 0 2006.281.08:01:20.13#ibcon#end of sib2, iclass 3, count 0 2006.281.08:01:20.13#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:01:20.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:01:20.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:01:20.13#ibcon#*before write, iclass 3, count 0 2006.281.08:01:20.13#ibcon#enter sib2, iclass 3, count 0 2006.281.08:01:20.13#ibcon#flushed, iclass 3, count 0 2006.281.08:01:20.13#ibcon#about to write, iclass 3, count 0 2006.281.08:01:20.13#ibcon#wrote, iclass 3, count 0 2006.281.08:01:20.13#ibcon#about to read 3, iclass 3, count 0 2006.281.08:01:20.17#ibcon#read 3, iclass 3, count 0 2006.281.08:01:20.17#ibcon#about to read 4, iclass 3, count 0 2006.281.08:01:20.17#ibcon#read 4, iclass 3, count 0 2006.281.08:01:20.17#ibcon#about to read 5, iclass 3, count 0 2006.281.08:01:20.17#ibcon#read 5, iclass 3, count 0 2006.281.08:01:20.17#ibcon#about to read 6, iclass 3, count 0 2006.281.08:01:20.17#ibcon#read 6, iclass 3, count 0 2006.281.08:01:20.17#ibcon#end of sib2, iclass 3, count 0 2006.281.08:01:20.17#ibcon#*after write, iclass 3, count 0 2006.281.08:01:20.17#ibcon#*before return 0, iclass 3, count 0 2006.281.08:01:20.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:01:20.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:01:20.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:01:20.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:01:20.17$vc4f8/va=4,6 2006.281.08:01:20.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.08:01:20.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.08:01:20.17#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:20.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:01:20.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:01:20.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:01:20.23#ibcon#enter wrdev, iclass 5, count 2 2006.281.08:01:20.23#ibcon#first serial, iclass 5, count 2 2006.281.08:01:20.23#ibcon#enter sib2, iclass 5, count 2 2006.281.08:01:20.23#ibcon#flushed, iclass 5, count 2 2006.281.08:01:20.23#ibcon#about to write, iclass 5, count 2 2006.281.08:01:20.23#ibcon#wrote, iclass 5, count 2 2006.281.08:01:20.23#ibcon#about to read 3, iclass 5, count 2 2006.281.08:01:20.25#ibcon#read 3, iclass 5, count 2 2006.281.08:01:20.25#ibcon#about to read 4, iclass 5, count 2 2006.281.08:01:20.25#ibcon#read 4, iclass 5, count 2 2006.281.08:01:20.25#ibcon#about to read 5, iclass 5, count 2 2006.281.08:01:20.25#ibcon#read 5, iclass 5, count 2 2006.281.08:01:20.25#ibcon#about to read 6, iclass 5, count 2 2006.281.08:01:20.25#ibcon#read 6, iclass 5, count 2 2006.281.08:01:20.25#ibcon#end of sib2, iclass 5, count 2 2006.281.08:01:20.25#ibcon#*mode == 0, iclass 5, count 2 2006.281.08:01:20.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.08:01:20.25#ibcon#[25=AT04-06\r\n] 2006.281.08:01:20.25#ibcon#*before write, iclass 5, count 2 2006.281.08:01:20.25#ibcon#enter sib2, iclass 5, count 2 2006.281.08:01:20.25#ibcon#flushed, iclass 5, count 2 2006.281.08:01:20.25#ibcon#about to write, iclass 5, count 2 2006.281.08:01:20.25#ibcon#wrote, iclass 5, count 2 2006.281.08:01:20.25#ibcon#about to read 3, iclass 5, count 2 2006.281.08:01:20.28#ibcon#read 3, iclass 5, count 2 2006.281.08:01:20.28#ibcon#about to read 4, iclass 5, count 2 2006.281.08:01:20.28#ibcon#read 4, iclass 5, count 2 2006.281.08:01:20.28#ibcon#about to read 5, iclass 5, count 2 2006.281.08:01:20.28#ibcon#read 5, iclass 5, count 2 2006.281.08:01:20.28#ibcon#about to read 6, iclass 5, count 2 2006.281.08:01:20.28#ibcon#read 6, iclass 5, count 2 2006.281.08:01:20.28#ibcon#end of sib2, iclass 5, count 2 2006.281.08:01:20.28#ibcon#*after write, iclass 5, count 2 2006.281.08:01:20.28#ibcon#*before return 0, iclass 5, count 2 2006.281.08:01:20.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:01:20.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:01:20.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.08:01:20.28#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:20.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:01:20.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:01:20.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:01:20.40#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:01:20.40#ibcon#first serial, iclass 5, count 0 2006.281.08:01:20.40#ibcon#enter sib2, iclass 5, count 0 2006.281.08:01:20.40#ibcon#flushed, iclass 5, count 0 2006.281.08:01:20.40#ibcon#about to write, iclass 5, count 0 2006.281.08:01:20.40#ibcon#wrote, iclass 5, count 0 2006.281.08:01:20.40#ibcon#about to read 3, iclass 5, count 0 2006.281.08:01:20.42#ibcon#read 3, iclass 5, count 0 2006.281.08:01:20.42#ibcon#about to read 4, iclass 5, count 0 2006.281.08:01:20.42#ibcon#read 4, iclass 5, count 0 2006.281.08:01:20.42#ibcon#about to read 5, iclass 5, count 0 2006.281.08:01:20.42#ibcon#read 5, iclass 5, count 0 2006.281.08:01:20.42#ibcon#about to read 6, iclass 5, count 0 2006.281.08:01:20.42#ibcon#read 6, iclass 5, count 0 2006.281.08:01:20.42#ibcon#end of sib2, iclass 5, count 0 2006.281.08:01:20.42#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:01:20.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:01:20.42#ibcon#[25=USB\r\n] 2006.281.08:01:20.42#ibcon#*before write, iclass 5, count 0 2006.281.08:01:20.42#ibcon#enter sib2, iclass 5, count 0 2006.281.08:01:20.42#ibcon#flushed, iclass 5, count 0 2006.281.08:01:20.42#ibcon#about to write, iclass 5, count 0 2006.281.08:01:20.42#ibcon#wrote, iclass 5, count 0 2006.281.08:01:20.42#ibcon#about to read 3, iclass 5, count 0 2006.281.08:01:20.46#ibcon#read 3, iclass 5, count 0 2006.281.08:01:20.46#ibcon#about to read 4, iclass 5, count 0 2006.281.08:01:20.46#ibcon#read 4, iclass 5, count 0 2006.281.08:01:20.46#ibcon#about to read 5, iclass 5, count 0 2006.281.08:01:20.46#ibcon#read 5, iclass 5, count 0 2006.281.08:01:20.46#ibcon#about to read 6, iclass 5, count 0 2006.281.08:01:20.46#ibcon#read 6, iclass 5, count 0 2006.281.08:01:20.46#ibcon#end of sib2, iclass 5, count 0 2006.281.08:01:20.46#ibcon#*after write, iclass 5, count 0 2006.281.08:01:20.46#ibcon#*before return 0, iclass 5, count 0 2006.281.08:01:20.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:01:20.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:01:20.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:01:20.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:01:20.46$vc4f8/valo=5,652.99 2006.281.08:01:20.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:01:20.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:01:20.46#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:20.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:20.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:20.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:20.46#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:01:20.46#ibcon#first serial, iclass 7, count 0 2006.281.08:01:20.46#ibcon#enter sib2, iclass 7, count 0 2006.281.08:01:20.46#ibcon#flushed, iclass 7, count 0 2006.281.08:01:20.46#ibcon#about to write, iclass 7, count 0 2006.281.08:01:20.46#ibcon#wrote, iclass 7, count 0 2006.281.08:01:20.46#ibcon#about to read 3, iclass 7, count 0 2006.281.08:01:20.47#ibcon#read 3, iclass 7, count 0 2006.281.08:01:20.47#ibcon#about to read 4, iclass 7, count 0 2006.281.08:01:20.47#ibcon#read 4, iclass 7, count 0 2006.281.08:01:20.47#ibcon#about to read 5, iclass 7, count 0 2006.281.08:01:20.47#ibcon#read 5, iclass 7, count 0 2006.281.08:01:20.47#ibcon#about to read 6, iclass 7, count 0 2006.281.08:01:20.47#ibcon#read 6, iclass 7, count 0 2006.281.08:01:20.47#ibcon#end of sib2, iclass 7, count 0 2006.281.08:01:20.47#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:01:20.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:01:20.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:01:20.47#ibcon#*before write, iclass 7, count 0 2006.281.08:01:20.47#ibcon#enter sib2, iclass 7, count 0 2006.281.08:01:20.47#ibcon#flushed, iclass 7, count 0 2006.281.08:01:20.49#ibcon#about to write, iclass 7, count 0 2006.281.08:01:20.49#ibcon#wrote, iclass 7, count 0 2006.281.08:01:20.49#ibcon#about to read 3, iclass 7, count 0 2006.281.08:01:20.53#ibcon#read 3, iclass 7, count 0 2006.281.08:01:20.53#ibcon#about to read 4, iclass 7, count 0 2006.281.08:01:20.53#ibcon#read 4, iclass 7, count 0 2006.281.08:01:20.53#ibcon#about to read 5, iclass 7, count 0 2006.281.08:01:20.53#ibcon#read 5, iclass 7, count 0 2006.281.08:01:20.53#ibcon#about to read 6, iclass 7, count 0 2006.281.08:01:20.53#ibcon#read 6, iclass 7, count 0 2006.281.08:01:20.53#ibcon#end of sib2, iclass 7, count 0 2006.281.08:01:20.53#ibcon#*after write, iclass 7, count 0 2006.281.08:01:20.53#ibcon#*before return 0, iclass 7, count 0 2006.281.08:01:20.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:20.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:20.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:01:20.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:01:20.53$vc4f8/va=5,7 2006.281.08:01:20.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:01:20.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:01:20.53#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:20.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:20.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:20.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:20.58#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:01:20.58#ibcon#first serial, iclass 11, count 2 2006.281.08:01:20.58#ibcon#enter sib2, iclass 11, count 2 2006.281.08:01:20.58#ibcon#flushed, iclass 11, count 2 2006.281.08:01:20.58#ibcon#about to write, iclass 11, count 2 2006.281.08:01:20.58#ibcon#wrote, iclass 11, count 2 2006.281.08:01:20.58#ibcon#about to read 3, iclass 11, count 2 2006.281.08:01:20.60#ibcon#read 3, iclass 11, count 2 2006.281.08:01:20.60#ibcon#about to read 4, iclass 11, count 2 2006.281.08:01:20.60#ibcon#read 4, iclass 11, count 2 2006.281.08:01:20.60#ibcon#about to read 5, iclass 11, count 2 2006.281.08:01:20.60#ibcon#read 5, iclass 11, count 2 2006.281.08:01:20.60#ibcon#about to read 6, iclass 11, count 2 2006.281.08:01:20.60#ibcon#read 6, iclass 11, count 2 2006.281.08:01:20.60#ibcon#end of sib2, iclass 11, count 2 2006.281.08:01:20.60#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:01:20.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:01:20.60#ibcon#[25=AT05-07\r\n] 2006.281.08:01:20.60#ibcon#*before write, iclass 11, count 2 2006.281.08:01:20.60#ibcon#enter sib2, iclass 11, count 2 2006.281.08:01:20.60#ibcon#flushed, iclass 11, count 2 2006.281.08:01:20.60#ibcon#about to write, iclass 11, count 2 2006.281.08:01:20.60#ibcon#wrote, iclass 11, count 2 2006.281.08:01:20.60#ibcon#about to read 3, iclass 11, count 2 2006.281.08:01:20.63#ibcon#read 3, iclass 11, count 2 2006.281.08:01:20.63#ibcon#about to read 4, iclass 11, count 2 2006.281.08:01:20.63#ibcon#read 4, iclass 11, count 2 2006.281.08:01:20.63#ibcon#about to read 5, iclass 11, count 2 2006.281.08:01:20.63#ibcon#read 5, iclass 11, count 2 2006.281.08:01:20.63#ibcon#about to read 6, iclass 11, count 2 2006.281.08:01:20.63#ibcon#read 6, iclass 11, count 2 2006.281.08:01:20.63#ibcon#end of sib2, iclass 11, count 2 2006.281.08:01:20.63#ibcon#*after write, iclass 11, count 2 2006.281.08:01:20.63#ibcon#*before return 0, iclass 11, count 2 2006.281.08:01:20.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:20.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:20.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:01:20.63#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:20.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:20.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:20.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:20.75#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:01:20.75#ibcon#first serial, iclass 11, count 0 2006.281.08:01:20.75#ibcon#enter sib2, iclass 11, count 0 2006.281.08:01:20.75#ibcon#flushed, iclass 11, count 0 2006.281.08:01:20.75#ibcon#about to write, iclass 11, count 0 2006.281.08:01:20.75#ibcon#wrote, iclass 11, count 0 2006.281.08:01:20.75#ibcon#about to read 3, iclass 11, count 0 2006.281.08:01:20.77#ibcon#read 3, iclass 11, count 0 2006.281.08:01:20.77#ibcon#about to read 4, iclass 11, count 0 2006.281.08:01:20.77#ibcon#read 4, iclass 11, count 0 2006.281.08:01:20.77#ibcon#about to read 5, iclass 11, count 0 2006.281.08:01:20.77#ibcon#read 5, iclass 11, count 0 2006.281.08:01:20.77#ibcon#about to read 6, iclass 11, count 0 2006.281.08:01:20.77#ibcon#read 6, iclass 11, count 0 2006.281.08:01:20.77#ibcon#end of sib2, iclass 11, count 0 2006.281.08:01:20.77#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:01:20.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:01:20.77#ibcon#[25=USB\r\n] 2006.281.08:01:20.77#ibcon#*before write, iclass 11, count 0 2006.281.08:01:20.77#ibcon#enter sib2, iclass 11, count 0 2006.281.08:01:20.77#ibcon#flushed, iclass 11, count 0 2006.281.08:01:20.77#ibcon#about to write, iclass 11, count 0 2006.281.08:01:20.77#ibcon#wrote, iclass 11, count 0 2006.281.08:01:20.77#ibcon#about to read 3, iclass 11, count 0 2006.281.08:01:20.80#ibcon#read 3, iclass 11, count 0 2006.281.08:01:20.80#ibcon#about to read 4, iclass 11, count 0 2006.281.08:01:20.80#ibcon#read 4, iclass 11, count 0 2006.281.08:01:20.80#ibcon#about to read 5, iclass 11, count 0 2006.281.08:01:20.80#ibcon#read 5, iclass 11, count 0 2006.281.08:01:20.80#ibcon#about to read 6, iclass 11, count 0 2006.281.08:01:20.80#ibcon#read 6, iclass 11, count 0 2006.281.08:01:20.80#ibcon#end of sib2, iclass 11, count 0 2006.281.08:01:20.80#ibcon#*after write, iclass 11, count 0 2006.281.08:01:20.80#ibcon#*before return 0, iclass 11, count 0 2006.281.08:01:20.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:20.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:20.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:01:20.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:01:20.80$vc4f8/valo=6,772.99 2006.281.08:01:20.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:01:20.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:01:20.80#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:20.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:20.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:20.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:20.80#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:01:20.80#ibcon#first serial, iclass 13, count 0 2006.281.08:01:20.80#ibcon#enter sib2, iclass 13, count 0 2006.281.08:01:20.80#ibcon#flushed, iclass 13, count 0 2006.281.08:01:20.80#ibcon#about to write, iclass 13, count 0 2006.281.08:01:20.80#ibcon#wrote, iclass 13, count 0 2006.281.08:01:20.80#ibcon#about to read 3, iclass 13, count 0 2006.281.08:01:20.82#ibcon#read 3, iclass 13, count 0 2006.281.08:01:20.82#ibcon#about to read 4, iclass 13, count 0 2006.281.08:01:20.82#ibcon#read 4, iclass 13, count 0 2006.281.08:01:20.82#ibcon#about to read 5, iclass 13, count 0 2006.281.08:01:20.82#ibcon#read 5, iclass 13, count 0 2006.281.08:01:20.82#ibcon#about to read 6, iclass 13, count 0 2006.281.08:01:20.82#ibcon#read 6, iclass 13, count 0 2006.281.08:01:20.82#ibcon#end of sib2, iclass 13, count 0 2006.281.08:01:20.82#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:01:20.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:01:20.82#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:01:20.82#ibcon#*before write, iclass 13, count 0 2006.281.08:01:20.82#ibcon#enter sib2, iclass 13, count 0 2006.281.08:01:20.82#ibcon#flushed, iclass 13, count 0 2006.281.08:01:20.82#ibcon#about to write, iclass 13, count 0 2006.281.08:01:20.82#ibcon#wrote, iclass 13, count 0 2006.281.08:01:20.82#ibcon#about to read 3, iclass 13, count 0 2006.281.08:01:20.86#ibcon#read 3, iclass 13, count 0 2006.281.08:01:20.86#ibcon#about to read 4, iclass 13, count 0 2006.281.08:01:20.86#ibcon#read 4, iclass 13, count 0 2006.281.08:01:20.86#ibcon#about to read 5, iclass 13, count 0 2006.281.08:01:20.86#ibcon#read 5, iclass 13, count 0 2006.281.08:01:20.86#ibcon#about to read 6, iclass 13, count 0 2006.281.08:01:20.86#ibcon#read 6, iclass 13, count 0 2006.281.08:01:20.86#ibcon#end of sib2, iclass 13, count 0 2006.281.08:01:20.86#ibcon#*after write, iclass 13, count 0 2006.281.08:01:20.86#ibcon#*before return 0, iclass 13, count 0 2006.281.08:01:20.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:20.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:20.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:01:20.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:01:20.86$vc4f8/va=6,6 2006.281.08:01:20.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:01:20.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:01:20.86#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:20.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:20.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:20.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:20.92#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:01:20.92#ibcon#first serial, iclass 15, count 2 2006.281.08:01:20.92#ibcon#enter sib2, iclass 15, count 2 2006.281.08:01:20.92#ibcon#flushed, iclass 15, count 2 2006.281.08:01:20.92#ibcon#about to write, iclass 15, count 2 2006.281.08:01:20.92#ibcon#wrote, iclass 15, count 2 2006.281.08:01:20.92#ibcon#about to read 3, iclass 15, count 2 2006.281.08:01:20.94#ibcon#read 3, iclass 15, count 2 2006.281.08:01:20.94#ibcon#about to read 4, iclass 15, count 2 2006.281.08:01:20.94#ibcon#read 4, iclass 15, count 2 2006.281.08:01:20.94#ibcon#about to read 5, iclass 15, count 2 2006.281.08:01:20.94#ibcon#read 5, iclass 15, count 2 2006.281.08:01:20.94#ibcon#about to read 6, iclass 15, count 2 2006.281.08:01:20.94#ibcon#read 6, iclass 15, count 2 2006.281.08:01:20.94#ibcon#end of sib2, iclass 15, count 2 2006.281.08:01:20.94#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:01:20.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:01:20.94#ibcon#[25=AT06-06\r\n] 2006.281.08:01:20.94#ibcon#*before write, iclass 15, count 2 2006.281.08:01:20.94#ibcon#enter sib2, iclass 15, count 2 2006.281.08:01:20.94#ibcon#flushed, iclass 15, count 2 2006.281.08:01:20.94#ibcon#about to write, iclass 15, count 2 2006.281.08:01:20.94#ibcon#wrote, iclass 15, count 2 2006.281.08:01:20.94#ibcon#about to read 3, iclass 15, count 2 2006.281.08:01:20.97#ibcon#read 3, iclass 15, count 2 2006.281.08:01:20.97#ibcon#about to read 4, iclass 15, count 2 2006.281.08:01:20.97#ibcon#read 4, iclass 15, count 2 2006.281.08:01:20.97#ibcon#about to read 5, iclass 15, count 2 2006.281.08:01:20.97#ibcon#read 5, iclass 15, count 2 2006.281.08:01:20.97#ibcon#about to read 6, iclass 15, count 2 2006.281.08:01:20.97#ibcon#read 6, iclass 15, count 2 2006.281.08:01:20.97#ibcon#end of sib2, iclass 15, count 2 2006.281.08:01:20.97#ibcon#*after write, iclass 15, count 2 2006.281.08:01:20.97#ibcon#*before return 0, iclass 15, count 2 2006.281.08:01:20.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:20.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:20.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:01:20.97#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:20.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:21.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:21.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:21.09#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:01:21.09#ibcon#first serial, iclass 15, count 0 2006.281.08:01:21.09#ibcon#enter sib2, iclass 15, count 0 2006.281.08:01:21.09#ibcon#flushed, iclass 15, count 0 2006.281.08:01:21.09#ibcon#about to write, iclass 15, count 0 2006.281.08:01:21.09#ibcon#wrote, iclass 15, count 0 2006.281.08:01:21.09#ibcon#about to read 3, iclass 15, count 0 2006.281.08:01:21.11#ibcon#read 3, iclass 15, count 0 2006.281.08:01:21.11#ibcon#about to read 4, iclass 15, count 0 2006.281.08:01:21.11#ibcon#read 4, iclass 15, count 0 2006.281.08:01:21.11#ibcon#about to read 5, iclass 15, count 0 2006.281.08:01:21.11#ibcon#read 5, iclass 15, count 0 2006.281.08:01:21.11#ibcon#about to read 6, iclass 15, count 0 2006.281.08:01:21.11#ibcon#read 6, iclass 15, count 0 2006.281.08:01:21.11#ibcon#end of sib2, iclass 15, count 0 2006.281.08:01:21.11#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:01:21.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:01:21.11#ibcon#[25=USB\r\n] 2006.281.08:01:21.11#ibcon#*before write, iclass 15, count 0 2006.281.08:01:21.11#ibcon#enter sib2, iclass 15, count 0 2006.281.08:01:21.11#ibcon#flushed, iclass 15, count 0 2006.281.08:01:21.11#ibcon#about to write, iclass 15, count 0 2006.281.08:01:21.11#ibcon#wrote, iclass 15, count 0 2006.281.08:01:21.11#ibcon#about to read 3, iclass 15, count 0 2006.281.08:01:21.14#ibcon#read 3, iclass 15, count 0 2006.281.08:01:21.14#ibcon#about to read 4, iclass 15, count 0 2006.281.08:01:21.14#ibcon#read 4, iclass 15, count 0 2006.281.08:01:21.14#ibcon#about to read 5, iclass 15, count 0 2006.281.08:01:21.14#ibcon#read 5, iclass 15, count 0 2006.281.08:01:21.14#ibcon#about to read 6, iclass 15, count 0 2006.281.08:01:21.14#ibcon#read 6, iclass 15, count 0 2006.281.08:01:21.14#ibcon#end of sib2, iclass 15, count 0 2006.281.08:01:21.14#ibcon#*after write, iclass 15, count 0 2006.281.08:01:21.14#ibcon#*before return 0, iclass 15, count 0 2006.281.08:01:21.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:21.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:21.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:01:21.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:01:21.14$vc4f8/valo=7,832.99 2006.281.08:01:21.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:01:21.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:01:21.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:21.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:21.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:21.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:21.14#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:01:21.14#ibcon#first serial, iclass 17, count 0 2006.281.08:01:21.14#ibcon#enter sib2, iclass 17, count 0 2006.281.08:01:21.14#ibcon#flushed, iclass 17, count 0 2006.281.08:01:21.14#ibcon#about to write, iclass 17, count 0 2006.281.08:01:21.14#ibcon#wrote, iclass 17, count 0 2006.281.08:01:21.14#ibcon#about to read 3, iclass 17, count 0 2006.281.08:01:21.16#ibcon#read 3, iclass 17, count 0 2006.281.08:01:21.16#ibcon#about to read 4, iclass 17, count 0 2006.281.08:01:21.16#ibcon#read 4, iclass 17, count 0 2006.281.08:01:21.16#ibcon#about to read 5, iclass 17, count 0 2006.281.08:01:21.16#ibcon#read 5, iclass 17, count 0 2006.281.08:01:21.16#ibcon#about to read 6, iclass 17, count 0 2006.281.08:01:21.16#ibcon#read 6, iclass 17, count 0 2006.281.08:01:21.16#ibcon#end of sib2, iclass 17, count 0 2006.281.08:01:21.16#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:01:21.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:01:21.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:01:21.18#ibcon#*before write, iclass 17, count 0 2006.281.08:01:21.18#ibcon#enter sib2, iclass 17, count 0 2006.281.08:01:21.18#ibcon#flushed, iclass 17, count 0 2006.281.08:01:21.18#ibcon#about to write, iclass 17, count 0 2006.281.08:01:21.18#ibcon#wrote, iclass 17, count 0 2006.281.08:01:21.18#ibcon#about to read 3, iclass 17, count 0 2006.281.08:01:21.22#ibcon#read 3, iclass 17, count 0 2006.281.08:01:21.22#ibcon#about to read 4, iclass 17, count 0 2006.281.08:01:21.22#ibcon#read 4, iclass 17, count 0 2006.281.08:01:21.22#ibcon#about to read 5, iclass 17, count 0 2006.281.08:01:21.22#ibcon#read 5, iclass 17, count 0 2006.281.08:01:21.22#ibcon#about to read 6, iclass 17, count 0 2006.281.08:01:21.22#ibcon#read 6, iclass 17, count 0 2006.281.08:01:21.22#ibcon#end of sib2, iclass 17, count 0 2006.281.08:01:21.22#ibcon#*after write, iclass 17, count 0 2006.281.08:01:21.22#ibcon#*before return 0, iclass 17, count 0 2006.281.08:01:21.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:21.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:21.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:01:21.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:01:21.22$vc4f8/va=7,6 2006.281.08:01:21.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:01:21.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:01:21.22#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:21.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:21.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:21.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:21.26#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:01:21.26#ibcon#first serial, iclass 19, count 2 2006.281.08:01:21.26#ibcon#enter sib2, iclass 19, count 2 2006.281.08:01:21.26#ibcon#flushed, iclass 19, count 2 2006.281.08:01:21.26#ibcon#about to write, iclass 19, count 2 2006.281.08:01:21.26#ibcon#wrote, iclass 19, count 2 2006.281.08:01:21.26#ibcon#about to read 3, iclass 19, count 2 2006.281.08:01:21.28#ibcon#read 3, iclass 19, count 2 2006.281.08:01:21.28#ibcon#about to read 4, iclass 19, count 2 2006.281.08:01:21.28#ibcon#read 4, iclass 19, count 2 2006.281.08:01:21.28#ibcon#about to read 5, iclass 19, count 2 2006.281.08:01:21.28#ibcon#read 5, iclass 19, count 2 2006.281.08:01:21.28#ibcon#about to read 6, iclass 19, count 2 2006.281.08:01:21.28#ibcon#read 6, iclass 19, count 2 2006.281.08:01:21.28#ibcon#end of sib2, iclass 19, count 2 2006.281.08:01:21.28#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:01:21.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:01:21.28#ibcon#[25=AT07-06\r\n] 2006.281.08:01:21.28#ibcon#*before write, iclass 19, count 2 2006.281.08:01:21.28#ibcon#enter sib2, iclass 19, count 2 2006.281.08:01:21.28#ibcon#flushed, iclass 19, count 2 2006.281.08:01:21.28#ibcon#about to write, iclass 19, count 2 2006.281.08:01:21.28#ibcon#wrote, iclass 19, count 2 2006.281.08:01:21.28#ibcon#about to read 3, iclass 19, count 2 2006.281.08:01:21.31#ibcon#read 3, iclass 19, count 2 2006.281.08:01:21.31#ibcon#about to read 4, iclass 19, count 2 2006.281.08:01:21.31#ibcon#read 4, iclass 19, count 2 2006.281.08:01:21.31#ibcon#about to read 5, iclass 19, count 2 2006.281.08:01:21.31#ibcon#read 5, iclass 19, count 2 2006.281.08:01:21.31#ibcon#about to read 6, iclass 19, count 2 2006.281.08:01:21.31#ibcon#read 6, iclass 19, count 2 2006.281.08:01:21.31#ibcon#end of sib2, iclass 19, count 2 2006.281.08:01:21.31#ibcon#*after write, iclass 19, count 2 2006.281.08:01:21.31#ibcon#*before return 0, iclass 19, count 2 2006.281.08:01:21.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:21.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:21.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:01:21.31#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:21.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:01:21.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:01:21.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:01:21.43#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:01:21.43#ibcon#first serial, iclass 19, count 0 2006.281.08:01:21.43#ibcon#enter sib2, iclass 19, count 0 2006.281.08:01:21.43#ibcon#flushed, iclass 19, count 0 2006.281.08:01:21.43#ibcon#about to write, iclass 19, count 0 2006.281.08:01:21.43#ibcon#wrote, iclass 19, count 0 2006.281.08:01:21.43#ibcon#about to read 3, iclass 19, count 0 2006.281.08:01:21.45#ibcon#read 3, iclass 19, count 0 2006.281.08:01:21.45#ibcon#about to read 4, iclass 19, count 0 2006.281.08:01:21.45#ibcon#read 4, iclass 19, count 0 2006.281.08:01:21.45#ibcon#about to read 5, iclass 19, count 0 2006.281.08:01:21.45#ibcon#read 5, iclass 19, count 0 2006.281.08:01:21.45#ibcon#about to read 6, iclass 19, count 0 2006.281.08:01:21.45#ibcon#read 6, iclass 19, count 0 2006.281.08:01:21.45#ibcon#end of sib2, iclass 19, count 0 2006.281.08:01:21.45#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:01:21.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:01:21.45#ibcon#[25=USB\r\n] 2006.281.08:01:21.45#ibcon#*before write, iclass 19, count 0 2006.281.08:01:21.45#ibcon#enter sib2, iclass 19, count 0 2006.281.08:01:21.45#ibcon#flushed, iclass 19, count 0 2006.281.08:01:21.45#ibcon#about to write, iclass 19, count 0 2006.281.08:01:21.45#ibcon#wrote, iclass 19, count 0 2006.281.08:01:21.45#ibcon#about to read 3, iclass 19, count 0 2006.281.08:01:21.48#ibcon#read 3, iclass 19, count 0 2006.281.08:01:21.48#ibcon#about to read 4, iclass 19, count 0 2006.281.08:01:21.48#ibcon#read 4, iclass 19, count 0 2006.281.08:01:21.48#ibcon#about to read 5, iclass 19, count 0 2006.281.08:01:21.48#ibcon#read 5, iclass 19, count 0 2006.281.08:01:21.48#ibcon#about to read 6, iclass 19, count 0 2006.281.08:01:21.48#ibcon#read 6, iclass 19, count 0 2006.281.08:01:21.48#ibcon#end of sib2, iclass 19, count 0 2006.281.08:01:21.48#ibcon#*after write, iclass 19, count 0 2006.281.08:01:21.48#ibcon#*before return 0, iclass 19, count 0 2006.281.08:01:21.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:01:21.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:01:21.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:01:21.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:01:21.48$vc4f8/valo=8,852.99 2006.281.08:01:21.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:01:21.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:01:21.48#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:21.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:01:21.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:01:21.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:01:21.48#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:01:21.48#ibcon#first serial, iclass 21, count 0 2006.281.08:01:21.48#ibcon#enter sib2, iclass 21, count 0 2006.281.08:01:21.48#ibcon#flushed, iclass 21, count 0 2006.281.08:01:21.48#ibcon#about to write, iclass 21, count 0 2006.281.08:01:21.48#ibcon#wrote, iclass 21, count 0 2006.281.08:01:21.48#ibcon#about to read 3, iclass 21, count 0 2006.281.08:01:21.50#ibcon#read 3, iclass 21, count 0 2006.281.08:01:21.50#ibcon#about to read 4, iclass 21, count 0 2006.281.08:01:21.50#ibcon#read 4, iclass 21, count 0 2006.281.08:01:21.50#ibcon#about to read 5, iclass 21, count 0 2006.281.08:01:21.50#ibcon#read 5, iclass 21, count 0 2006.281.08:01:21.50#ibcon#about to read 6, iclass 21, count 0 2006.281.08:01:21.50#ibcon#read 6, iclass 21, count 0 2006.281.08:01:21.50#ibcon#end of sib2, iclass 21, count 0 2006.281.08:01:21.50#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:01:21.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:01:21.50#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:01:21.50#ibcon#*before write, iclass 21, count 0 2006.281.08:01:21.50#ibcon#enter sib2, iclass 21, count 0 2006.281.08:01:21.50#ibcon#flushed, iclass 21, count 0 2006.281.08:01:21.50#ibcon#about to write, iclass 21, count 0 2006.281.08:01:21.50#ibcon#wrote, iclass 21, count 0 2006.281.08:01:21.50#ibcon#about to read 3, iclass 21, count 0 2006.281.08:01:21.54#ibcon#read 3, iclass 21, count 0 2006.281.08:01:21.54#ibcon#about to read 4, iclass 21, count 0 2006.281.08:01:21.54#ibcon#read 4, iclass 21, count 0 2006.281.08:01:21.54#ibcon#about to read 5, iclass 21, count 0 2006.281.08:01:21.54#ibcon#read 5, iclass 21, count 0 2006.281.08:01:21.54#ibcon#about to read 6, iclass 21, count 0 2006.281.08:01:21.54#ibcon#read 6, iclass 21, count 0 2006.281.08:01:21.54#ibcon#end of sib2, iclass 21, count 0 2006.281.08:01:21.54#ibcon#*after write, iclass 21, count 0 2006.281.08:01:21.54#ibcon#*before return 0, iclass 21, count 0 2006.281.08:01:21.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:01:21.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:01:21.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:01:21.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:01:21.54$vc4f8/va=8,6 2006.281.08:01:21.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:01:21.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:01:21.54#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:21.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:01:21.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:01:21.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:01:21.60#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:01:21.60#ibcon#first serial, iclass 23, count 2 2006.281.08:01:21.60#ibcon#enter sib2, iclass 23, count 2 2006.281.08:01:21.60#ibcon#flushed, iclass 23, count 2 2006.281.08:01:21.60#ibcon#about to write, iclass 23, count 2 2006.281.08:01:21.60#ibcon#wrote, iclass 23, count 2 2006.281.08:01:21.60#ibcon#about to read 3, iclass 23, count 2 2006.281.08:01:21.62#ibcon#read 3, iclass 23, count 2 2006.281.08:01:21.62#ibcon#about to read 4, iclass 23, count 2 2006.281.08:01:21.62#ibcon#read 4, iclass 23, count 2 2006.281.08:01:21.62#ibcon#about to read 5, iclass 23, count 2 2006.281.08:01:21.62#ibcon#read 5, iclass 23, count 2 2006.281.08:01:21.62#ibcon#about to read 6, iclass 23, count 2 2006.281.08:01:21.62#ibcon#read 6, iclass 23, count 2 2006.281.08:01:21.62#ibcon#end of sib2, iclass 23, count 2 2006.281.08:01:21.62#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:01:21.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:01:21.62#ibcon#[25=AT08-06\r\n] 2006.281.08:01:21.62#ibcon#*before write, iclass 23, count 2 2006.281.08:01:21.62#ibcon#enter sib2, iclass 23, count 2 2006.281.08:01:21.62#ibcon#flushed, iclass 23, count 2 2006.281.08:01:21.62#ibcon#about to write, iclass 23, count 2 2006.281.08:01:21.62#ibcon#wrote, iclass 23, count 2 2006.281.08:01:21.62#ibcon#about to read 3, iclass 23, count 2 2006.281.08:01:21.65#ibcon#read 3, iclass 23, count 2 2006.281.08:01:21.65#ibcon#about to read 4, iclass 23, count 2 2006.281.08:01:21.65#ibcon#read 4, iclass 23, count 2 2006.281.08:01:21.65#ibcon#about to read 5, iclass 23, count 2 2006.281.08:01:21.65#ibcon#read 5, iclass 23, count 2 2006.281.08:01:21.65#ibcon#about to read 6, iclass 23, count 2 2006.281.08:01:21.65#ibcon#read 6, iclass 23, count 2 2006.281.08:01:21.65#ibcon#end of sib2, iclass 23, count 2 2006.281.08:01:21.65#ibcon#*after write, iclass 23, count 2 2006.281.08:01:21.65#ibcon#*before return 0, iclass 23, count 2 2006.281.08:01:21.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:01:21.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:01:21.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:01:21.65#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:21.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:01:21.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:01:21.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:01:21.77#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:01:21.77#ibcon#first serial, iclass 23, count 0 2006.281.08:01:21.77#ibcon#enter sib2, iclass 23, count 0 2006.281.08:01:21.77#ibcon#flushed, iclass 23, count 0 2006.281.08:01:21.77#ibcon#about to write, iclass 23, count 0 2006.281.08:01:21.77#ibcon#wrote, iclass 23, count 0 2006.281.08:01:21.77#ibcon#about to read 3, iclass 23, count 0 2006.281.08:01:21.79#ibcon#read 3, iclass 23, count 0 2006.281.08:01:21.79#ibcon#about to read 4, iclass 23, count 0 2006.281.08:01:21.79#ibcon#read 4, iclass 23, count 0 2006.281.08:01:21.79#ibcon#about to read 5, iclass 23, count 0 2006.281.08:01:21.79#ibcon#read 5, iclass 23, count 0 2006.281.08:01:21.79#ibcon#about to read 6, iclass 23, count 0 2006.281.08:01:21.79#ibcon#read 6, iclass 23, count 0 2006.281.08:01:21.79#ibcon#end of sib2, iclass 23, count 0 2006.281.08:01:21.79#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:01:21.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:01:21.79#ibcon#[25=USB\r\n] 2006.281.08:01:21.79#ibcon#*before write, iclass 23, count 0 2006.281.08:01:21.79#ibcon#enter sib2, iclass 23, count 0 2006.281.08:01:21.79#ibcon#flushed, iclass 23, count 0 2006.281.08:01:21.79#ibcon#about to write, iclass 23, count 0 2006.281.08:01:21.79#ibcon#wrote, iclass 23, count 0 2006.281.08:01:21.79#ibcon#about to read 3, iclass 23, count 0 2006.281.08:01:21.82#ibcon#read 3, iclass 23, count 0 2006.281.08:01:21.82#ibcon#about to read 4, iclass 23, count 0 2006.281.08:01:21.82#ibcon#read 4, iclass 23, count 0 2006.281.08:01:21.82#ibcon#about to read 5, iclass 23, count 0 2006.281.08:01:21.82#ibcon#read 5, iclass 23, count 0 2006.281.08:01:21.82#ibcon#about to read 6, iclass 23, count 0 2006.281.08:01:21.82#ibcon#read 6, iclass 23, count 0 2006.281.08:01:21.82#ibcon#end of sib2, iclass 23, count 0 2006.281.08:01:21.82#ibcon#*after write, iclass 23, count 0 2006.281.08:01:21.82#ibcon#*before return 0, iclass 23, count 0 2006.281.08:01:21.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:01:21.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:01:21.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:01:21.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:01:21.82$vc4f8/vblo=1,632.99 2006.281.08:01:21.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:01:21.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:01:21.82#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:21.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:01:21.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:01:21.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:01:21.82#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:01:21.82#ibcon#first serial, iclass 25, count 0 2006.281.08:01:21.82#ibcon#enter sib2, iclass 25, count 0 2006.281.08:01:21.82#ibcon#flushed, iclass 25, count 0 2006.281.08:01:21.82#ibcon#about to write, iclass 25, count 0 2006.281.08:01:21.82#ibcon#wrote, iclass 25, count 0 2006.281.08:01:21.82#ibcon#about to read 3, iclass 25, count 0 2006.281.08:01:21.84#ibcon#read 3, iclass 25, count 0 2006.281.08:01:21.84#ibcon#about to read 4, iclass 25, count 0 2006.281.08:01:21.84#ibcon#read 4, iclass 25, count 0 2006.281.08:01:21.84#ibcon#about to read 5, iclass 25, count 0 2006.281.08:01:21.84#ibcon#read 5, iclass 25, count 0 2006.281.08:01:21.84#ibcon#about to read 6, iclass 25, count 0 2006.281.08:01:21.84#ibcon#read 6, iclass 25, count 0 2006.281.08:01:21.84#ibcon#end of sib2, iclass 25, count 0 2006.281.08:01:21.84#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:01:21.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:01:21.84#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:01:21.84#ibcon#*before write, iclass 25, count 0 2006.281.08:01:21.84#ibcon#enter sib2, iclass 25, count 0 2006.281.08:01:21.84#ibcon#flushed, iclass 25, count 0 2006.281.08:01:21.84#ibcon#about to write, iclass 25, count 0 2006.281.08:01:21.84#ibcon#wrote, iclass 25, count 0 2006.281.08:01:21.84#ibcon#about to read 3, iclass 25, count 0 2006.281.08:01:21.88#ibcon#read 3, iclass 25, count 0 2006.281.08:01:21.88#ibcon#about to read 4, iclass 25, count 0 2006.281.08:01:21.88#ibcon#read 4, iclass 25, count 0 2006.281.08:01:21.88#ibcon#about to read 5, iclass 25, count 0 2006.281.08:01:21.88#ibcon#read 5, iclass 25, count 0 2006.281.08:01:21.88#ibcon#about to read 6, iclass 25, count 0 2006.281.08:01:21.88#ibcon#read 6, iclass 25, count 0 2006.281.08:01:21.88#ibcon#end of sib2, iclass 25, count 0 2006.281.08:01:21.88#ibcon#*after write, iclass 25, count 0 2006.281.08:01:21.88#ibcon#*before return 0, iclass 25, count 0 2006.281.08:01:21.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:01:21.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:01:21.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:01:21.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:01:21.88$vc4f8/vb=1,4 2006.281.08:01:21.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:01:21.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:01:21.88#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:21.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:01:21.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:01:21.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:01:21.88#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:01:21.88#ibcon#first serial, iclass 27, count 2 2006.281.08:01:21.88#ibcon#enter sib2, iclass 27, count 2 2006.281.08:01:21.88#ibcon#flushed, iclass 27, count 2 2006.281.08:01:21.88#ibcon#about to write, iclass 27, count 2 2006.281.08:01:21.88#ibcon#wrote, iclass 27, count 2 2006.281.08:01:21.88#ibcon#about to read 3, iclass 27, count 2 2006.281.08:01:21.90#ibcon#read 3, iclass 27, count 2 2006.281.08:01:21.90#ibcon#about to read 4, iclass 27, count 2 2006.281.08:01:21.90#ibcon#read 4, iclass 27, count 2 2006.281.08:01:21.90#ibcon#about to read 5, iclass 27, count 2 2006.281.08:01:21.90#ibcon#read 5, iclass 27, count 2 2006.281.08:01:21.90#ibcon#about to read 6, iclass 27, count 2 2006.281.08:01:21.90#ibcon#read 6, iclass 27, count 2 2006.281.08:01:21.90#ibcon#end of sib2, iclass 27, count 2 2006.281.08:01:21.90#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:01:21.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:01:21.90#ibcon#[27=AT01-04\r\n] 2006.281.08:01:21.90#ibcon#*before write, iclass 27, count 2 2006.281.08:01:21.90#ibcon#enter sib2, iclass 27, count 2 2006.281.08:01:21.90#ibcon#flushed, iclass 27, count 2 2006.281.08:01:21.90#ibcon#about to write, iclass 27, count 2 2006.281.08:01:21.90#ibcon#wrote, iclass 27, count 2 2006.281.08:01:21.90#ibcon#about to read 3, iclass 27, count 2 2006.281.08:01:21.93#ibcon#read 3, iclass 27, count 2 2006.281.08:01:21.93#ibcon#about to read 4, iclass 27, count 2 2006.281.08:01:21.93#ibcon#read 4, iclass 27, count 2 2006.281.08:01:21.93#ibcon#about to read 5, iclass 27, count 2 2006.281.08:01:21.93#ibcon#read 5, iclass 27, count 2 2006.281.08:01:21.93#ibcon#about to read 6, iclass 27, count 2 2006.281.08:01:21.93#ibcon#read 6, iclass 27, count 2 2006.281.08:01:21.93#ibcon#end of sib2, iclass 27, count 2 2006.281.08:01:21.93#ibcon#*after write, iclass 27, count 2 2006.281.08:01:21.93#ibcon#*before return 0, iclass 27, count 2 2006.281.08:01:21.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:01:21.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:01:21.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:01:21.93#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:21.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:01:22.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:01:22.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:01:22.05#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:01:22.05#ibcon#first serial, iclass 27, count 0 2006.281.08:01:22.05#ibcon#enter sib2, iclass 27, count 0 2006.281.08:01:22.05#ibcon#flushed, iclass 27, count 0 2006.281.08:01:22.05#ibcon#about to write, iclass 27, count 0 2006.281.08:01:22.05#ibcon#wrote, iclass 27, count 0 2006.281.08:01:22.05#ibcon#about to read 3, iclass 27, count 0 2006.281.08:01:22.07#ibcon#read 3, iclass 27, count 0 2006.281.08:01:22.07#ibcon#about to read 4, iclass 27, count 0 2006.281.08:01:22.07#ibcon#read 4, iclass 27, count 0 2006.281.08:01:22.07#ibcon#about to read 5, iclass 27, count 0 2006.281.08:01:22.07#ibcon#read 5, iclass 27, count 0 2006.281.08:01:22.07#ibcon#about to read 6, iclass 27, count 0 2006.281.08:01:22.07#ibcon#read 6, iclass 27, count 0 2006.281.08:01:22.07#ibcon#end of sib2, iclass 27, count 0 2006.281.08:01:22.07#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:01:22.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:01:22.07#ibcon#[27=USB\r\n] 2006.281.08:01:22.07#ibcon#*before write, iclass 27, count 0 2006.281.08:01:22.07#ibcon#enter sib2, iclass 27, count 0 2006.281.08:01:22.07#ibcon#flushed, iclass 27, count 0 2006.281.08:01:22.07#ibcon#about to write, iclass 27, count 0 2006.281.08:01:22.07#ibcon#wrote, iclass 27, count 0 2006.281.08:01:22.07#ibcon#about to read 3, iclass 27, count 0 2006.281.08:01:22.10#ibcon#read 3, iclass 27, count 0 2006.281.08:01:22.10#ibcon#about to read 4, iclass 27, count 0 2006.281.08:01:22.10#ibcon#read 4, iclass 27, count 0 2006.281.08:01:22.10#ibcon#about to read 5, iclass 27, count 0 2006.281.08:01:22.10#ibcon#read 5, iclass 27, count 0 2006.281.08:01:22.10#ibcon#about to read 6, iclass 27, count 0 2006.281.08:01:22.10#ibcon#read 6, iclass 27, count 0 2006.281.08:01:22.10#ibcon#end of sib2, iclass 27, count 0 2006.281.08:01:22.10#ibcon#*after write, iclass 27, count 0 2006.281.08:01:22.10#ibcon#*before return 0, iclass 27, count 0 2006.281.08:01:22.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:01:22.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:01:22.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:01:22.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:01:22.10$vc4f8/vblo=2,640.99 2006.281.08:01:22.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:01:22.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:01:22.10#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:22.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:22.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:22.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:22.10#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:01:22.10#ibcon#first serial, iclass 29, count 0 2006.281.08:01:22.10#ibcon#enter sib2, iclass 29, count 0 2006.281.08:01:22.10#ibcon#flushed, iclass 29, count 0 2006.281.08:01:22.10#ibcon#about to write, iclass 29, count 0 2006.281.08:01:22.10#ibcon#wrote, iclass 29, count 0 2006.281.08:01:22.10#ibcon#about to read 3, iclass 29, count 0 2006.281.08:01:22.12#ibcon#read 3, iclass 29, count 0 2006.281.08:01:22.12#ibcon#about to read 4, iclass 29, count 0 2006.281.08:01:22.12#ibcon#read 4, iclass 29, count 0 2006.281.08:01:22.12#ibcon#about to read 5, iclass 29, count 0 2006.281.08:01:22.12#ibcon#read 5, iclass 29, count 0 2006.281.08:01:22.12#ibcon#about to read 6, iclass 29, count 0 2006.281.08:01:22.12#ibcon#read 6, iclass 29, count 0 2006.281.08:01:22.12#ibcon#end of sib2, iclass 29, count 0 2006.281.08:01:22.12#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:01:22.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:01:22.12#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:01:22.12#ibcon#*before write, iclass 29, count 0 2006.281.08:01:22.12#ibcon#enter sib2, iclass 29, count 0 2006.281.08:01:22.12#ibcon#flushed, iclass 29, count 0 2006.281.08:01:22.12#ibcon#about to write, iclass 29, count 0 2006.281.08:01:22.12#ibcon#wrote, iclass 29, count 0 2006.281.08:01:22.12#ibcon#about to read 3, iclass 29, count 0 2006.281.08:01:22.16#ibcon#read 3, iclass 29, count 0 2006.281.08:01:22.16#ibcon#about to read 4, iclass 29, count 0 2006.281.08:01:22.16#ibcon#read 4, iclass 29, count 0 2006.281.08:01:22.16#ibcon#about to read 5, iclass 29, count 0 2006.281.08:01:22.16#ibcon#read 5, iclass 29, count 0 2006.281.08:01:22.16#ibcon#about to read 6, iclass 29, count 0 2006.281.08:01:22.16#ibcon#read 6, iclass 29, count 0 2006.281.08:01:22.16#ibcon#end of sib2, iclass 29, count 0 2006.281.08:01:22.16#ibcon#*after write, iclass 29, count 0 2006.281.08:01:22.16#ibcon#*before return 0, iclass 29, count 0 2006.281.08:01:22.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:22.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:01:22.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:01:22.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:01:22.16$vc4f8/vb=2,5 2006.281.08:01:22.16#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:01:22.16#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:01:22.16#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:22.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:22.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:22.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:22.22#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:01:22.22#ibcon#first serial, iclass 31, count 2 2006.281.08:01:22.22#ibcon#enter sib2, iclass 31, count 2 2006.281.08:01:22.22#ibcon#flushed, iclass 31, count 2 2006.281.08:01:22.22#ibcon#about to write, iclass 31, count 2 2006.281.08:01:22.22#ibcon#wrote, iclass 31, count 2 2006.281.08:01:22.22#ibcon#about to read 3, iclass 31, count 2 2006.281.08:01:22.24#ibcon#read 3, iclass 31, count 2 2006.281.08:01:22.24#ibcon#about to read 4, iclass 31, count 2 2006.281.08:01:22.24#ibcon#read 4, iclass 31, count 2 2006.281.08:01:22.24#ibcon#about to read 5, iclass 31, count 2 2006.281.08:01:22.24#ibcon#read 5, iclass 31, count 2 2006.281.08:01:22.24#ibcon#about to read 6, iclass 31, count 2 2006.281.08:01:22.24#ibcon#read 6, iclass 31, count 2 2006.281.08:01:22.24#ibcon#end of sib2, iclass 31, count 2 2006.281.08:01:22.24#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:01:22.24#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:01:22.24#ibcon#[27=AT02-05\r\n] 2006.281.08:01:22.24#ibcon#*before write, iclass 31, count 2 2006.281.08:01:22.24#ibcon#enter sib2, iclass 31, count 2 2006.281.08:01:22.24#ibcon#flushed, iclass 31, count 2 2006.281.08:01:22.24#ibcon#about to write, iclass 31, count 2 2006.281.08:01:22.24#ibcon#wrote, iclass 31, count 2 2006.281.08:01:22.24#ibcon#about to read 3, iclass 31, count 2 2006.281.08:01:22.27#ibcon#read 3, iclass 31, count 2 2006.281.08:01:22.27#ibcon#about to read 4, iclass 31, count 2 2006.281.08:01:22.27#ibcon#read 4, iclass 31, count 2 2006.281.08:01:22.27#ibcon#about to read 5, iclass 31, count 2 2006.281.08:01:22.27#ibcon#read 5, iclass 31, count 2 2006.281.08:01:22.27#ibcon#about to read 6, iclass 31, count 2 2006.281.08:01:22.27#ibcon#read 6, iclass 31, count 2 2006.281.08:01:22.27#ibcon#end of sib2, iclass 31, count 2 2006.281.08:01:22.27#ibcon#*after write, iclass 31, count 2 2006.281.08:01:22.27#ibcon#*before return 0, iclass 31, count 2 2006.281.08:01:22.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:22.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:01:22.27#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:01:22.27#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:22.27#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:22.39#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:22.39#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:22.39#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:01:22.39#ibcon#first serial, iclass 31, count 0 2006.281.08:01:22.39#ibcon#enter sib2, iclass 31, count 0 2006.281.08:01:22.39#ibcon#flushed, iclass 31, count 0 2006.281.08:01:22.39#ibcon#about to write, iclass 31, count 0 2006.281.08:01:22.39#ibcon#wrote, iclass 31, count 0 2006.281.08:01:22.39#ibcon#about to read 3, iclass 31, count 0 2006.281.08:01:22.41#ibcon#read 3, iclass 31, count 0 2006.281.08:01:22.41#ibcon#about to read 4, iclass 31, count 0 2006.281.08:01:22.41#ibcon#read 4, iclass 31, count 0 2006.281.08:01:22.41#ibcon#about to read 5, iclass 31, count 0 2006.281.08:01:22.41#ibcon#read 5, iclass 31, count 0 2006.281.08:01:22.41#ibcon#about to read 6, iclass 31, count 0 2006.281.08:01:22.41#ibcon#read 6, iclass 31, count 0 2006.281.08:01:22.41#ibcon#end of sib2, iclass 31, count 0 2006.281.08:01:22.41#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:01:22.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:01:22.41#ibcon#[27=USB\r\n] 2006.281.08:01:22.41#ibcon#*before write, iclass 31, count 0 2006.281.08:01:22.41#ibcon#enter sib2, iclass 31, count 0 2006.281.08:01:22.41#ibcon#flushed, iclass 31, count 0 2006.281.08:01:22.41#ibcon#about to write, iclass 31, count 0 2006.281.08:01:22.41#ibcon#wrote, iclass 31, count 0 2006.281.08:01:22.41#ibcon#about to read 3, iclass 31, count 0 2006.281.08:01:22.44#ibcon#read 3, iclass 31, count 0 2006.281.08:01:22.44#ibcon#about to read 4, iclass 31, count 0 2006.281.08:01:22.44#ibcon#read 4, iclass 31, count 0 2006.281.08:01:22.44#ibcon#about to read 5, iclass 31, count 0 2006.281.08:01:22.44#ibcon#read 5, iclass 31, count 0 2006.281.08:01:22.44#ibcon#about to read 6, iclass 31, count 0 2006.281.08:01:22.44#ibcon#read 6, iclass 31, count 0 2006.281.08:01:22.44#ibcon#end of sib2, iclass 31, count 0 2006.281.08:01:22.44#ibcon#*after write, iclass 31, count 0 2006.281.08:01:22.44#ibcon#*before return 0, iclass 31, count 0 2006.281.08:01:22.44#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:22.44#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:01:22.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:01:22.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:01:22.44$vc4f8/vblo=3,656.99 2006.281.08:01:22.44#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:01:22.44#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:01:22.44#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:22.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:22.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:22.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:22.44#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:01:22.44#ibcon#first serial, iclass 33, count 0 2006.281.08:01:22.44#ibcon#enter sib2, iclass 33, count 0 2006.281.08:01:22.44#ibcon#flushed, iclass 33, count 0 2006.281.08:01:22.44#ibcon#about to write, iclass 33, count 0 2006.281.08:01:22.44#ibcon#wrote, iclass 33, count 0 2006.281.08:01:22.44#ibcon#about to read 3, iclass 33, count 0 2006.281.08:01:22.46#ibcon#read 3, iclass 33, count 0 2006.281.08:01:22.46#ibcon#about to read 4, iclass 33, count 0 2006.281.08:01:22.46#ibcon#read 4, iclass 33, count 0 2006.281.08:01:22.46#ibcon#about to read 5, iclass 33, count 0 2006.281.08:01:22.46#ibcon#read 5, iclass 33, count 0 2006.281.08:01:22.46#ibcon#about to read 6, iclass 33, count 0 2006.281.08:01:22.46#ibcon#read 6, iclass 33, count 0 2006.281.08:01:22.46#ibcon#end of sib2, iclass 33, count 0 2006.281.08:01:22.46#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:01:22.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:01:22.46#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:01:22.46#ibcon#*before write, iclass 33, count 0 2006.281.08:01:22.46#ibcon#enter sib2, iclass 33, count 0 2006.281.08:01:22.46#ibcon#flushed, iclass 33, count 0 2006.281.08:01:22.46#ibcon#about to write, iclass 33, count 0 2006.281.08:01:22.48#ibcon#wrote, iclass 33, count 0 2006.281.08:01:22.48#ibcon#about to read 3, iclass 33, count 0 2006.281.08:01:22.52#ibcon#read 3, iclass 33, count 0 2006.281.08:01:22.52#ibcon#about to read 4, iclass 33, count 0 2006.281.08:01:22.52#ibcon#read 4, iclass 33, count 0 2006.281.08:01:22.52#ibcon#about to read 5, iclass 33, count 0 2006.281.08:01:22.52#ibcon#read 5, iclass 33, count 0 2006.281.08:01:22.52#ibcon#about to read 6, iclass 33, count 0 2006.281.08:01:22.52#ibcon#read 6, iclass 33, count 0 2006.281.08:01:22.52#ibcon#end of sib2, iclass 33, count 0 2006.281.08:01:22.52#ibcon#*after write, iclass 33, count 0 2006.281.08:01:22.52#ibcon#*before return 0, iclass 33, count 0 2006.281.08:01:22.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:22.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:01:22.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:01:22.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:01:22.52$vc4f8/vb=3,4 2006.281.08:01:22.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:01:22.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:01:22.52#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:22.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:22.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:22.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:22.56#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:01:22.56#ibcon#first serial, iclass 35, count 2 2006.281.08:01:22.56#ibcon#enter sib2, iclass 35, count 2 2006.281.08:01:22.56#ibcon#flushed, iclass 35, count 2 2006.281.08:01:22.56#ibcon#about to write, iclass 35, count 2 2006.281.08:01:22.56#ibcon#wrote, iclass 35, count 2 2006.281.08:01:22.56#ibcon#about to read 3, iclass 35, count 2 2006.281.08:01:22.58#ibcon#read 3, iclass 35, count 2 2006.281.08:01:22.58#ibcon#about to read 4, iclass 35, count 2 2006.281.08:01:22.58#ibcon#read 4, iclass 35, count 2 2006.281.08:01:22.58#ibcon#about to read 5, iclass 35, count 2 2006.281.08:01:22.58#ibcon#read 5, iclass 35, count 2 2006.281.08:01:22.58#ibcon#about to read 6, iclass 35, count 2 2006.281.08:01:22.58#ibcon#read 6, iclass 35, count 2 2006.281.08:01:22.58#ibcon#end of sib2, iclass 35, count 2 2006.281.08:01:22.58#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:01:22.58#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:01:22.58#ibcon#[27=AT03-04\r\n] 2006.281.08:01:22.58#ibcon#*before write, iclass 35, count 2 2006.281.08:01:22.58#ibcon#enter sib2, iclass 35, count 2 2006.281.08:01:22.58#ibcon#flushed, iclass 35, count 2 2006.281.08:01:22.58#ibcon#about to write, iclass 35, count 2 2006.281.08:01:22.58#ibcon#wrote, iclass 35, count 2 2006.281.08:01:22.58#ibcon#about to read 3, iclass 35, count 2 2006.281.08:01:22.61#ibcon#read 3, iclass 35, count 2 2006.281.08:01:22.61#ibcon#about to read 4, iclass 35, count 2 2006.281.08:01:22.61#ibcon#read 4, iclass 35, count 2 2006.281.08:01:22.61#ibcon#about to read 5, iclass 35, count 2 2006.281.08:01:22.61#ibcon#read 5, iclass 35, count 2 2006.281.08:01:22.61#ibcon#about to read 6, iclass 35, count 2 2006.281.08:01:22.61#ibcon#read 6, iclass 35, count 2 2006.281.08:01:22.61#ibcon#end of sib2, iclass 35, count 2 2006.281.08:01:22.61#ibcon#*after write, iclass 35, count 2 2006.281.08:01:22.61#ibcon#*before return 0, iclass 35, count 2 2006.281.08:01:22.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:22.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:01:22.61#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:01:22.61#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:22.61#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:22.73#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:22.73#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:22.73#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:01:22.73#ibcon#first serial, iclass 35, count 0 2006.281.08:01:22.73#ibcon#enter sib2, iclass 35, count 0 2006.281.08:01:22.73#ibcon#flushed, iclass 35, count 0 2006.281.08:01:22.73#ibcon#about to write, iclass 35, count 0 2006.281.08:01:22.73#ibcon#wrote, iclass 35, count 0 2006.281.08:01:22.73#ibcon#about to read 3, iclass 35, count 0 2006.281.08:01:22.75#ibcon#read 3, iclass 35, count 0 2006.281.08:01:22.75#ibcon#about to read 4, iclass 35, count 0 2006.281.08:01:22.75#ibcon#read 4, iclass 35, count 0 2006.281.08:01:22.75#ibcon#about to read 5, iclass 35, count 0 2006.281.08:01:22.75#ibcon#read 5, iclass 35, count 0 2006.281.08:01:22.75#ibcon#about to read 6, iclass 35, count 0 2006.281.08:01:22.75#ibcon#read 6, iclass 35, count 0 2006.281.08:01:22.75#ibcon#end of sib2, iclass 35, count 0 2006.281.08:01:22.75#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:01:22.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:01:22.75#ibcon#[27=USB\r\n] 2006.281.08:01:22.75#ibcon#*before write, iclass 35, count 0 2006.281.08:01:22.75#ibcon#enter sib2, iclass 35, count 0 2006.281.08:01:22.75#ibcon#flushed, iclass 35, count 0 2006.281.08:01:22.75#ibcon#about to write, iclass 35, count 0 2006.281.08:01:22.75#ibcon#wrote, iclass 35, count 0 2006.281.08:01:22.75#ibcon#about to read 3, iclass 35, count 0 2006.281.08:01:22.78#ibcon#read 3, iclass 35, count 0 2006.281.08:01:22.78#ibcon#about to read 4, iclass 35, count 0 2006.281.08:01:22.78#ibcon#read 4, iclass 35, count 0 2006.281.08:01:22.78#ibcon#about to read 5, iclass 35, count 0 2006.281.08:01:22.78#ibcon#read 5, iclass 35, count 0 2006.281.08:01:22.78#ibcon#about to read 6, iclass 35, count 0 2006.281.08:01:22.78#ibcon#read 6, iclass 35, count 0 2006.281.08:01:22.78#ibcon#end of sib2, iclass 35, count 0 2006.281.08:01:22.78#ibcon#*after write, iclass 35, count 0 2006.281.08:01:22.78#ibcon#*before return 0, iclass 35, count 0 2006.281.08:01:22.78#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:22.78#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:01:22.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:01:22.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:01:22.78$vc4f8/vblo=4,712.99 2006.281.08:01:22.78#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:01:22.78#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:01:22.78#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:22.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:22.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:22.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:22.78#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:01:22.78#ibcon#first serial, iclass 37, count 0 2006.281.08:01:22.78#ibcon#enter sib2, iclass 37, count 0 2006.281.08:01:22.78#ibcon#flushed, iclass 37, count 0 2006.281.08:01:22.78#ibcon#about to write, iclass 37, count 0 2006.281.08:01:22.78#ibcon#wrote, iclass 37, count 0 2006.281.08:01:22.78#ibcon#about to read 3, iclass 37, count 0 2006.281.08:01:22.80#ibcon#read 3, iclass 37, count 0 2006.281.08:01:22.80#ibcon#about to read 4, iclass 37, count 0 2006.281.08:01:22.80#ibcon#read 4, iclass 37, count 0 2006.281.08:01:22.80#ibcon#about to read 5, iclass 37, count 0 2006.281.08:01:22.80#ibcon#read 5, iclass 37, count 0 2006.281.08:01:22.80#ibcon#about to read 6, iclass 37, count 0 2006.281.08:01:22.80#ibcon#read 6, iclass 37, count 0 2006.281.08:01:22.80#ibcon#end of sib2, iclass 37, count 0 2006.281.08:01:22.80#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:01:22.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:01:22.80#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:01:22.80#ibcon#*before write, iclass 37, count 0 2006.281.08:01:22.80#ibcon#enter sib2, iclass 37, count 0 2006.281.08:01:22.80#ibcon#flushed, iclass 37, count 0 2006.281.08:01:22.80#ibcon#about to write, iclass 37, count 0 2006.281.08:01:22.80#ibcon#wrote, iclass 37, count 0 2006.281.08:01:22.80#ibcon#about to read 3, iclass 37, count 0 2006.281.08:01:22.84#ibcon#read 3, iclass 37, count 0 2006.281.08:01:22.84#ibcon#about to read 4, iclass 37, count 0 2006.281.08:01:22.84#ibcon#read 4, iclass 37, count 0 2006.281.08:01:22.84#ibcon#about to read 5, iclass 37, count 0 2006.281.08:01:22.84#ibcon#read 5, iclass 37, count 0 2006.281.08:01:22.84#ibcon#about to read 6, iclass 37, count 0 2006.281.08:01:22.84#ibcon#read 6, iclass 37, count 0 2006.281.08:01:22.84#ibcon#end of sib2, iclass 37, count 0 2006.281.08:01:22.84#ibcon#*after write, iclass 37, count 0 2006.281.08:01:22.84#ibcon#*before return 0, iclass 37, count 0 2006.281.08:01:22.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:22.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:01:22.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:01:22.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:01:22.84$vc4f8/vb=4,4 2006.281.08:01:22.84#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.08:01:22.84#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.08:01:22.84#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:22.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:22.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:22.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:22.90#ibcon#enter wrdev, iclass 39, count 2 2006.281.08:01:22.90#ibcon#first serial, iclass 39, count 2 2006.281.08:01:22.90#ibcon#enter sib2, iclass 39, count 2 2006.281.08:01:22.90#ibcon#flushed, iclass 39, count 2 2006.281.08:01:22.90#ibcon#about to write, iclass 39, count 2 2006.281.08:01:22.90#ibcon#wrote, iclass 39, count 2 2006.281.08:01:22.90#ibcon#about to read 3, iclass 39, count 2 2006.281.08:01:22.92#ibcon#read 3, iclass 39, count 2 2006.281.08:01:22.92#ibcon#about to read 4, iclass 39, count 2 2006.281.08:01:22.92#ibcon#read 4, iclass 39, count 2 2006.281.08:01:22.92#ibcon#about to read 5, iclass 39, count 2 2006.281.08:01:22.92#ibcon#read 5, iclass 39, count 2 2006.281.08:01:22.92#ibcon#about to read 6, iclass 39, count 2 2006.281.08:01:22.92#ibcon#read 6, iclass 39, count 2 2006.281.08:01:22.92#ibcon#end of sib2, iclass 39, count 2 2006.281.08:01:22.92#ibcon#*mode == 0, iclass 39, count 2 2006.281.08:01:22.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.08:01:22.92#ibcon#[27=AT04-04\r\n] 2006.281.08:01:22.92#ibcon#*before write, iclass 39, count 2 2006.281.08:01:22.92#ibcon#enter sib2, iclass 39, count 2 2006.281.08:01:22.92#ibcon#flushed, iclass 39, count 2 2006.281.08:01:22.92#ibcon#about to write, iclass 39, count 2 2006.281.08:01:22.92#ibcon#wrote, iclass 39, count 2 2006.281.08:01:22.92#ibcon#about to read 3, iclass 39, count 2 2006.281.08:01:22.95#ibcon#read 3, iclass 39, count 2 2006.281.08:01:22.95#ibcon#about to read 4, iclass 39, count 2 2006.281.08:01:22.95#ibcon#read 4, iclass 39, count 2 2006.281.08:01:22.95#ibcon#about to read 5, iclass 39, count 2 2006.281.08:01:22.95#ibcon#read 5, iclass 39, count 2 2006.281.08:01:22.95#ibcon#about to read 6, iclass 39, count 2 2006.281.08:01:22.95#ibcon#read 6, iclass 39, count 2 2006.281.08:01:22.95#ibcon#end of sib2, iclass 39, count 2 2006.281.08:01:22.95#ibcon#*after write, iclass 39, count 2 2006.281.08:01:22.95#ibcon#*before return 0, iclass 39, count 2 2006.281.08:01:22.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:22.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:01:22.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.08:01:22.95#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:22.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:23.01#abcon#<5=/13 2.2 7.9 20.49 511001.4\r\n> 2006.281.08:01:23.03#abcon#{5=INTERFACE CLEAR} 2006.281.08:01:23.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:23.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:23.07#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:01:23.07#ibcon#first serial, iclass 39, count 0 2006.281.08:01:23.07#ibcon#enter sib2, iclass 39, count 0 2006.281.08:01:23.07#ibcon#flushed, iclass 39, count 0 2006.281.08:01:23.07#ibcon#about to write, iclass 39, count 0 2006.281.08:01:23.07#ibcon#wrote, iclass 39, count 0 2006.281.08:01:23.07#ibcon#about to read 3, iclass 39, count 0 2006.281.08:01:23.09#ibcon#read 3, iclass 39, count 0 2006.281.08:01:23.09#ibcon#about to read 4, iclass 39, count 0 2006.281.08:01:23.09#ibcon#read 4, iclass 39, count 0 2006.281.08:01:23.09#ibcon#about to read 5, iclass 39, count 0 2006.281.08:01:23.09#ibcon#read 5, iclass 39, count 0 2006.281.08:01:23.09#ibcon#about to read 6, iclass 39, count 0 2006.281.08:01:23.09#ibcon#read 6, iclass 39, count 0 2006.281.08:01:23.09#ibcon#end of sib2, iclass 39, count 0 2006.281.08:01:23.09#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:01:23.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:01:23.09#ibcon#[27=USB\r\n] 2006.281.08:01:23.09#ibcon#*before write, iclass 39, count 0 2006.281.08:01:23.09#ibcon#enter sib2, iclass 39, count 0 2006.281.08:01:23.09#ibcon#flushed, iclass 39, count 0 2006.281.08:01:23.09#ibcon#about to write, iclass 39, count 0 2006.281.08:01:23.09#ibcon#wrote, iclass 39, count 0 2006.281.08:01:23.09#ibcon#about to read 3, iclass 39, count 0 2006.281.08:01:23.09#abcon#[5=S1D000X0/0*\r\n] 2006.281.08:01:23.12#ibcon#read 3, iclass 39, count 0 2006.281.08:01:23.12#ibcon#about to read 4, iclass 39, count 0 2006.281.08:01:23.12#ibcon#read 4, iclass 39, count 0 2006.281.08:01:23.12#ibcon#about to read 5, iclass 39, count 0 2006.281.08:01:23.12#ibcon#read 5, iclass 39, count 0 2006.281.08:01:23.12#ibcon#about to read 6, iclass 39, count 0 2006.281.08:01:23.12#ibcon#read 6, iclass 39, count 0 2006.281.08:01:23.12#ibcon#end of sib2, iclass 39, count 0 2006.281.08:01:23.12#ibcon#*after write, iclass 39, count 0 2006.281.08:01:23.12#ibcon#*before return 0, iclass 39, count 0 2006.281.08:01:23.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:23.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:01:23.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:01:23.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:01:23.12$vc4f8/vblo=5,744.99 2006.281.08:01:23.12#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:01:23.12#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:01:23.12#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:23.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:23.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:23.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:23.12#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:01:23.12#ibcon#first serial, iclass 7, count 0 2006.281.08:01:23.12#ibcon#enter sib2, iclass 7, count 0 2006.281.08:01:23.12#ibcon#flushed, iclass 7, count 0 2006.281.08:01:23.12#ibcon#about to write, iclass 7, count 0 2006.281.08:01:23.12#ibcon#wrote, iclass 7, count 0 2006.281.08:01:23.12#ibcon#about to read 3, iclass 7, count 0 2006.281.08:01:23.14#ibcon#read 3, iclass 7, count 0 2006.281.08:01:23.14#ibcon#about to read 4, iclass 7, count 0 2006.281.08:01:23.14#ibcon#read 4, iclass 7, count 0 2006.281.08:01:23.14#ibcon#about to read 5, iclass 7, count 0 2006.281.08:01:23.14#ibcon#read 5, iclass 7, count 0 2006.281.08:01:23.14#ibcon#about to read 6, iclass 7, count 0 2006.281.08:01:23.14#ibcon#read 6, iclass 7, count 0 2006.281.08:01:23.14#ibcon#end of sib2, iclass 7, count 0 2006.281.08:01:23.14#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:01:23.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:01:23.14#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:01:23.14#ibcon#*before write, iclass 7, count 0 2006.281.08:01:23.14#ibcon#enter sib2, iclass 7, count 0 2006.281.08:01:23.14#ibcon#flushed, iclass 7, count 0 2006.281.08:01:23.14#ibcon#about to write, iclass 7, count 0 2006.281.08:01:23.14#ibcon#wrote, iclass 7, count 0 2006.281.08:01:23.14#ibcon#about to read 3, iclass 7, count 0 2006.281.08:01:23.18#ibcon#read 3, iclass 7, count 0 2006.281.08:01:23.18#ibcon#about to read 4, iclass 7, count 0 2006.281.08:01:23.18#ibcon#read 4, iclass 7, count 0 2006.281.08:01:23.18#ibcon#about to read 5, iclass 7, count 0 2006.281.08:01:23.18#ibcon#read 5, iclass 7, count 0 2006.281.08:01:23.18#ibcon#about to read 6, iclass 7, count 0 2006.281.08:01:23.18#ibcon#read 6, iclass 7, count 0 2006.281.08:01:23.18#ibcon#end of sib2, iclass 7, count 0 2006.281.08:01:23.18#ibcon#*after write, iclass 7, count 0 2006.281.08:01:23.18#ibcon#*before return 0, iclass 7, count 0 2006.281.08:01:23.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:23.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:01:23.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:01:23.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:01:23.18$vc4f8/vb=5,4 2006.281.08:01:23.18#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:01:23.18#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:01:23.18#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:23.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:23.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:23.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:23.24#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:01:23.24#ibcon#first serial, iclass 11, count 2 2006.281.08:01:23.24#ibcon#enter sib2, iclass 11, count 2 2006.281.08:01:23.24#ibcon#flushed, iclass 11, count 2 2006.281.08:01:23.24#ibcon#about to write, iclass 11, count 2 2006.281.08:01:23.24#ibcon#wrote, iclass 11, count 2 2006.281.08:01:23.24#ibcon#about to read 3, iclass 11, count 2 2006.281.08:01:23.26#ibcon#read 3, iclass 11, count 2 2006.281.08:01:23.26#ibcon#about to read 4, iclass 11, count 2 2006.281.08:01:23.26#ibcon#read 4, iclass 11, count 2 2006.281.08:01:23.26#ibcon#about to read 5, iclass 11, count 2 2006.281.08:01:23.26#ibcon#read 5, iclass 11, count 2 2006.281.08:01:23.26#ibcon#about to read 6, iclass 11, count 2 2006.281.08:01:23.26#ibcon#read 6, iclass 11, count 2 2006.281.08:01:23.26#ibcon#end of sib2, iclass 11, count 2 2006.281.08:01:23.26#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:01:23.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:01:23.26#ibcon#[27=AT05-04\r\n] 2006.281.08:01:23.26#ibcon#*before write, iclass 11, count 2 2006.281.08:01:23.26#ibcon#enter sib2, iclass 11, count 2 2006.281.08:01:23.26#ibcon#flushed, iclass 11, count 2 2006.281.08:01:23.26#ibcon#about to write, iclass 11, count 2 2006.281.08:01:23.26#ibcon#wrote, iclass 11, count 2 2006.281.08:01:23.26#ibcon#about to read 3, iclass 11, count 2 2006.281.08:01:23.30#ibcon#read 3, iclass 11, count 2 2006.281.08:01:23.30#ibcon#about to read 4, iclass 11, count 2 2006.281.08:01:23.30#ibcon#read 4, iclass 11, count 2 2006.281.08:01:23.30#ibcon#about to read 5, iclass 11, count 2 2006.281.08:01:23.30#ibcon#read 5, iclass 11, count 2 2006.281.08:01:23.30#ibcon#about to read 6, iclass 11, count 2 2006.281.08:01:23.30#ibcon#read 6, iclass 11, count 2 2006.281.08:01:23.30#ibcon#end of sib2, iclass 11, count 2 2006.281.08:01:23.30#ibcon#*after write, iclass 11, count 2 2006.281.08:01:23.30#ibcon#*before return 0, iclass 11, count 2 2006.281.08:01:23.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:23.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:01:23.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:01:23.30#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:23.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:23.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:23.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:23.42#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:01:23.42#ibcon#first serial, iclass 11, count 0 2006.281.08:01:23.42#ibcon#enter sib2, iclass 11, count 0 2006.281.08:01:23.42#ibcon#flushed, iclass 11, count 0 2006.281.08:01:23.42#ibcon#about to write, iclass 11, count 0 2006.281.08:01:23.42#ibcon#wrote, iclass 11, count 0 2006.281.08:01:23.42#ibcon#about to read 3, iclass 11, count 0 2006.281.08:01:23.44#ibcon#read 3, iclass 11, count 0 2006.281.08:01:23.44#ibcon#about to read 4, iclass 11, count 0 2006.281.08:01:23.44#ibcon#read 4, iclass 11, count 0 2006.281.08:01:23.44#ibcon#about to read 5, iclass 11, count 0 2006.281.08:01:23.44#ibcon#read 5, iclass 11, count 0 2006.281.08:01:23.44#ibcon#about to read 6, iclass 11, count 0 2006.281.08:01:23.44#ibcon#read 6, iclass 11, count 0 2006.281.08:01:23.44#ibcon#end of sib2, iclass 11, count 0 2006.281.08:01:23.44#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:01:23.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:01:23.44#ibcon#[27=USB\r\n] 2006.281.08:01:23.44#ibcon#*before write, iclass 11, count 0 2006.281.08:01:23.44#ibcon#enter sib2, iclass 11, count 0 2006.281.08:01:23.44#ibcon#flushed, iclass 11, count 0 2006.281.08:01:23.44#ibcon#about to write, iclass 11, count 0 2006.281.08:01:23.44#ibcon#wrote, iclass 11, count 0 2006.281.08:01:23.44#ibcon#about to read 3, iclass 11, count 0 2006.281.08:01:23.47#ibcon#read 3, iclass 11, count 0 2006.281.08:01:23.47#ibcon#about to read 4, iclass 11, count 0 2006.281.08:01:23.47#ibcon#read 4, iclass 11, count 0 2006.281.08:01:23.47#ibcon#about to read 5, iclass 11, count 0 2006.281.08:01:23.47#ibcon#read 5, iclass 11, count 0 2006.281.08:01:23.47#ibcon#about to read 6, iclass 11, count 0 2006.281.08:01:23.47#ibcon#read 6, iclass 11, count 0 2006.281.08:01:23.47#ibcon#end of sib2, iclass 11, count 0 2006.281.08:01:23.47#ibcon#*after write, iclass 11, count 0 2006.281.08:01:23.47#ibcon#*before return 0, iclass 11, count 0 2006.281.08:01:23.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:23.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:01:23.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:01:23.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:01:23.47$vc4f8/vblo=6,752.99 2006.281.08:01:23.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:01:23.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:01:23.47#ibcon#ireg 17 cls_cnt 0 2006.281.08:01:23.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:23.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:23.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:23.47#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:01:23.47#ibcon#first serial, iclass 13, count 0 2006.281.08:01:23.47#ibcon#enter sib2, iclass 13, count 0 2006.281.08:01:23.47#ibcon#flushed, iclass 13, count 0 2006.281.08:01:23.47#ibcon#about to write, iclass 13, count 0 2006.281.08:01:23.47#ibcon#wrote, iclass 13, count 0 2006.281.08:01:23.47#ibcon#about to read 3, iclass 13, count 0 2006.281.08:01:23.49#ibcon#read 3, iclass 13, count 0 2006.281.08:01:23.49#ibcon#about to read 4, iclass 13, count 0 2006.281.08:01:23.49#ibcon#read 4, iclass 13, count 0 2006.281.08:01:23.49#ibcon#about to read 5, iclass 13, count 0 2006.281.08:01:23.49#ibcon#read 5, iclass 13, count 0 2006.281.08:01:23.49#ibcon#about to read 6, iclass 13, count 0 2006.281.08:01:23.49#ibcon#read 6, iclass 13, count 0 2006.281.08:01:23.49#ibcon#end of sib2, iclass 13, count 0 2006.281.08:01:23.49#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:01:23.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:01:23.49#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:01:23.49#ibcon#*before write, iclass 13, count 0 2006.281.08:01:23.49#ibcon#enter sib2, iclass 13, count 0 2006.281.08:01:23.49#ibcon#flushed, iclass 13, count 0 2006.281.08:01:23.49#ibcon#about to write, iclass 13, count 0 2006.281.08:01:23.49#ibcon#wrote, iclass 13, count 0 2006.281.08:01:23.49#ibcon#about to read 3, iclass 13, count 0 2006.281.08:01:23.53#ibcon#read 3, iclass 13, count 0 2006.281.08:01:23.53#ibcon#about to read 4, iclass 13, count 0 2006.281.08:01:23.53#ibcon#read 4, iclass 13, count 0 2006.281.08:01:23.53#ibcon#about to read 5, iclass 13, count 0 2006.281.08:01:23.53#ibcon#read 5, iclass 13, count 0 2006.281.08:01:23.53#ibcon#about to read 6, iclass 13, count 0 2006.281.08:01:23.53#ibcon#read 6, iclass 13, count 0 2006.281.08:01:23.53#ibcon#end of sib2, iclass 13, count 0 2006.281.08:01:23.53#ibcon#*after write, iclass 13, count 0 2006.281.08:01:23.53#ibcon#*before return 0, iclass 13, count 0 2006.281.08:01:23.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:23.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:01:23.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:01:23.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:01:23.53$vc4f8/vb=6,4 2006.281.08:01:23.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:01:23.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:01:23.53#ibcon#ireg 11 cls_cnt 2 2006.281.08:01:23.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:23.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:23.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:23.59#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:01:23.59#ibcon#first serial, iclass 15, count 2 2006.281.08:01:23.59#ibcon#enter sib2, iclass 15, count 2 2006.281.08:01:23.59#ibcon#flushed, iclass 15, count 2 2006.281.08:01:23.59#ibcon#about to write, iclass 15, count 2 2006.281.08:01:23.59#ibcon#wrote, iclass 15, count 2 2006.281.08:01:23.59#ibcon#about to read 3, iclass 15, count 2 2006.281.08:01:23.61#ibcon#read 3, iclass 15, count 2 2006.281.08:01:23.61#ibcon#about to read 4, iclass 15, count 2 2006.281.08:01:23.61#ibcon#read 4, iclass 15, count 2 2006.281.08:01:23.61#ibcon#about to read 5, iclass 15, count 2 2006.281.08:01:23.61#ibcon#read 5, iclass 15, count 2 2006.281.08:01:23.61#ibcon#about to read 6, iclass 15, count 2 2006.281.08:01:23.61#ibcon#read 6, iclass 15, count 2 2006.281.08:01:23.61#ibcon#end of sib2, iclass 15, count 2 2006.281.08:01:23.61#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:01:23.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:01:23.61#ibcon#[27=AT06-04\r\n] 2006.281.08:01:23.61#ibcon#*before write, iclass 15, count 2 2006.281.08:01:23.61#ibcon#enter sib2, iclass 15, count 2 2006.281.08:01:23.61#ibcon#flushed, iclass 15, count 2 2006.281.08:01:23.61#ibcon#about to write, iclass 15, count 2 2006.281.08:01:23.61#ibcon#wrote, iclass 15, count 2 2006.281.08:01:23.61#ibcon#about to read 3, iclass 15, count 2 2006.281.08:01:23.64#ibcon#read 3, iclass 15, count 2 2006.281.08:01:23.64#ibcon#about to read 4, iclass 15, count 2 2006.281.08:01:23.64#ibcon#read 4, iclass 15, count 2 2006.281.08:01:23.64#ibcon#about to read 5, iclass 15, count 2 2006.281.08:01:23.64#ibcon#read 5, iclass 15, count 2 2006.281.08:01:23.64#ibcon#about to read 6, iclass 15, count 2 2006.281.08:01:23.64#ibcon#read 6, iclass 15, count 2 2006.281.08:01:23.64#ibcon#end of sib2, iclass 15, count 2 2006.281.08:01:23.64#ibcon#*after write, iclass 15, count 2 2006.281.08:01:23.64#ibcon#*before return 0, iclass 15, count 2 2006.281.08:01:23.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:23.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:01:23.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:01:23.64#ibcon#ireg 7 cls_cnt 0 2006.281.08:01:23.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:23.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:23.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:23.76#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:01:23.76#ibcon#first serial, iclass 15, count 0 2006.281.08:01:23.76#ibcon#enter sib2, iclass 15, count 0 2006.281.08:01:23.76#ibcon#flushed, iclass 15, count 0 2006.281.08:01:23.76#ibcon#about to write, iclass 15, count 0 2006.281.08:01:23.76#ibcon#wrote, iclass 15, count 0 2006.281.08:01:23.76#ibcon#about to read 3, iclass 15, count 0 2006.281.08:01:23.78#ibcon#read 3, iclass 15, count 0 2006.281.08:01:23.78#ibcon#about to read 4, iclass 15, count 0 2006.281.08:01:23.78#ibcon#read 4, iclass 15, count 0 2006.281.08:01:23.78#ibcon#about to read 5, iclass 15, count 0 2006.281.08:01:23.78#ibcon#read 5, iclass 15, count 0 2006.281.08:01:23.78#ibcon#about to read 6, iclass 15, count 0 2006.281.08:01:23.78#ibcon#read 6, iclass 15, count 0 2006.281.08:01:23.78#ibcon#end of sib2, iclass 15, count 0 2006.281.08:01:23.78#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:01:23.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:01:23.78#ibcon#[27=USB\r\n] 2006.281.08:01:23.78#ibcon#*before write, iclass 15, count 0 2006.281.08:01:23.78#ibcon#enter sib2, iclass 15, count 0 2006.281.08:01:23.78#ibcon#flushed, iclass 15, count 0 2006.281.08:01:23.78#ibcon#about to write, iclass 15, count 0 2006.281.08:01:23.78#ibcon#wrote, iclass 15, count 0 2006.281.08:01:23.78#ibcon#about to read 3, iclass 15, count 0 2006.281.08:01:23.81#ibcon#read 3, iclass 15, count 0 2006.281.08:01:23.81#ibcon#about to read 4, iclass 15, count 0 2006.281.08:01:23.81#ibcon#read 4, iclass 15, count 0 2006.281.08:01:23.81#ibcon#about to read 5, iclass 15, count 0 2006.281.08:01:23.81#ibcon#read 5, iclass 15, count 0 2006.281.08:01:23.81#ibcon#about to read 6, iclass 15, count 0 2006.281.08:01:23.81#ibcon#read 6, iclass 15, count 0 2006.281.08:01:23.81#ibcon#end of sib2, iclass 15, count 0 2006.281.08:01:23.81#ibcon#*after write, iclass 15, count 0 2006.281.08:01:23.81#ibcon#*before return 0, iclass 15, count 0 2006.281.08:01:23.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:23.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:01:23.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:01:23.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:01:23.81$vc4f8/vabw=wide 2006.281.08:01:23.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:01:23.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:01:23.81#ibcon#ireg 8 cls_cnt 0 2006.281.08:01:23.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:23.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:23.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:23.81#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:01:23.81#ibcon#first serial, iclass 17, count 0 2006.281.08:01:23.81#ibcon#enter sib2, iclass 17, count 0 2006.281.08:01:23.81#ibcon#flushed, iclass 17, count 0 2006.281.08:01:23.81#ibcon#about to write, iclass 17, count 0 2006.281.08:01:23.81#ibcon#wrote, iclass 17, count 0 2006.281.08:01:23.81#ibcon#about to read 3, iclass 17, count 0 2006.281.08:01:23.83#ibcon#read 3, iclass 17, count 0 2006.281.08:01:23.83#ibcon#about to read 4, iclass 17, count 0 2006.281.08:01:23.83#ibcon#read 4, iclass 17, count 0 2006.281.08:01:23.83#ibcon#about to read 5, iclass 17, count 0 2006.281.08:01:23.83#ibcon#read 5, iclass 17, count 0 2006.281.08:01:23.83#ibcon#about to read 6, iclass 17, count 0 2006.281.08:01:23.83#ibcon#read 6, iclass 17, count 0 2006.281.08:01:23.83#ibcon#end of sib2, iclass 17, count 0 2006.281.08:01:23.83#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:01:23.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:01:23.83#ibcon#[25=BW32\r\n] 2006.281.08:01:23.83#ibcon#*before write, iclass 17, count 0 2006.281.08:01:23.83#ibcon#enter sib2, iclass 17, count 0 2006.281.08:01:23.83#ibcon#flushed, iclass 17, count 0 2006.281.08:01:23.83#ibcon#about to write, iclass 17, count 0 2006.281.08:01:23.83#ibcon#wrote, iclass 17, count 0 2006.281.08:01:23.83#ibcon#about to read 3, iclass 17, count 0 2006.281.08:01:23.86#ibcon#read 3, iclass 17, count 0 2006.281.08:01:23.86#ibcon#about to read 4, iclass 17, count 0 2006.281.08:01:23.86#ibcon#read 4, iclass 17, count 0 2006.281.08:01:23.86#ibcon#about to read 5, iclass 17, count 0 2006.281.08:01:23.86#ibcon#read 5, iclass 17, count 0 2006.281.08:01:23.86#ibcon#about to read 6, iclass 17, count 0 2006.281.08:01:23.86#ibcon#read 6, iclass 17, count 0 2006.281.08:01:23.86#ibcon#end of sib2, iclass 17, count 0 2006.281.08:01:23.86#ibcon#*after write, iclass 17, count 0 2006.281.08:01:23.86#ibcon#*before return 0, iclass 17, count 0 2006.281.08:01:23.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:23.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:01:23.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:01:23.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:01:23.86$vc4f8/vbbw=wide 2006.281.08:01:23.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.08:01:23.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.08:01:23.86#ibcon#ireg 8 cls_cnt 0 2006.281.08:01:23.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:01:23.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:01:23.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:01:23.93#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:01:23.93#ibcon#first serial, iclass 19, count 0 2006.281.08:01:23.93#ibcon#enter sib2, iclass 19, count 0 2006.281.08:01:23.93#ibcon#flushed, iclass 19, count 0 2006.281.08:01:23.93#ibcon#about to write, iclass 19, count 0 2006.281.08:01:23.93#ibcon#wrote, iclass 19, count 0 2006.281.08:01:23.93#ibcon#about to read 3, iclass 19, count 0 2006.281.08:01:23.95#ibcon#read 3, iclass 19, count 0 2006.281.08:01:23.95#ibcon#about to read 4, iclass 19, count 0 2006.281.08:01:23.95#ibcon#read 4, iclass 19, count 0 2006.281.08:01:23.95#ibcon#about to read 5, iclass 19, count 0 2006.281.08:01:23.95#ibcon#read 5, iclass 19, count 0 2006.281.08:01:23.95#ibcon#about to read 6, iclass 19, count 0 2006.281.08:01:23.95#ibcon#read 6, iclass 19, count 0 2006.281.08:01:23.95#ibcon#end of sib2, iclass 19, count 0 2006.281.08:01:23.95#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:01:23.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:01:23.95#ibcon#[27=BW32\r\n] 2006.281.08:01:23.95#ibcon#*before write, iclass 19, count 0 2006.281.08:01:23.95#ibcon#enter sib2, iclass 19, count 0 2006.281.08:01:23.95#ibcon#flushed, iclass 19, count 0 2006.281.08:01:23.95#ibcon#about to write, iclass 19, count 0 2006.281.08:01:23.95#ibcon#wrote, iclass 19, count 0 2006.281.08:01:23.95#ibcon#about to read 3, iclass 19, count 0 2006.281.08:01:23.98#ibcon#read 3, iclass 19, count 0 2006.281.08:01:23.98#ibcon#about to read 4, iclass 19, count 0 2006.281.08:01:23.98#ibcon#read 4, iclass 19, count 0 2006.281.08:01:23.98#ibcon#about to read 5, iclass 19, count 0 2006.281.08:01:23.98#ibcon#read 5, iclass 19, count 0 2006.281.08:01:23.98#ibcon#about to read 6, iclass 19, count 0 2006.281.08:01:23.98#ibcon#read 6, iclass 19, count 0 2006.281.08:01:23.98#ibcon#end of sib2, iclass 19, count 0 2006.281.08:01:23.98#ibcon#*after write, iclass 19, count 0 2006.281.08:01:23.98#ibcon#*before return 0, iclass 19, count 0 2006.281.08:01:23.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:01:23.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:01:23.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:01:23.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:01:23.98$4f8m12a/ifd4f 2006.281.08:01:23.98$ifd4f/lo= 2006.281.08:01:23.98$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:01:23.98$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:01:23.98$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:01:23.98$ifd4f/patch= 2006.281.08:01:23.98$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:01:23.98$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:01:23.98$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:01:23.98$4f8m12a/"form=m,16.000,1:2 2006.281.08:01:23.98$4f8m12a/"tpicd 2006.281.08:01:23.98$4f8m12a/echo=off 2006.281.08:01:23.98$4f8m12a/xlog=off 2006.281.08:01:23.98:!2006.281.08:01:50 2006.281.08:01:33.14#trakl#Source acquired 2006.281.08:01:35.14#flagr#flagr/antenna,acquired 2006.281.08:01:50.00:preob 2006.281.08:01:51.14/onsource/TRACKING 2006.281.08:01:51.14:!2006.281.08:02:00 2006.281.08:02:00.00:data_valid=on 2006.281.08:02:00.00:midob 2006.281.08:02:00.14/onsource/TRACKING 2006.281.08:02:00.14/wx/20.47,1001.4,51 2006.281.08:02:00.36/cable/+6.4869E-03 2006.281.08:02:01.45/va/01,07,usb,yes,35,37 2006.281.08:02:01.45/va/02,06,usb,yes,32,34 2006.281.08:02:01.45/va/03,06,usb,yes,31,30 2006.281.08:02:01.45/va/04,06,usb,yes,34,36 2006.281.08:02:01.45/va/05,07,usb,yes,32,34 2006.281.08:02:01.45/va/06,06,usb,yes,31,31 2006.281.08:02:01.45/va/07,06,usb,yes,31,31 2006.281.08:02:01.45/va/08,06,usb,yes,33,33 2006.281.08:02:01.68/valo/01,532.99,yes,locked 2006.281.08:02:01.68/valo/02,572.99,yes,locked 2006.281.08:02:01.68/valo/03,672.99,yes,locked 2006.281.08:02:01.68/valo/04,832.99,yes,locked 2006.281.08:02:01.68/valo/05,652.99,yes,locked 2006.281.08:02:01.68/valo/06,772.99,yes,locked 2006.281.08:02:01.68/valo/07,832.99,yes,locked 2006.281.08:02:01.68/valo/08,852.99,yes,locked 2006.281.08:02:02.14#trakl#Off source 2006.281.08:02:02.14?ERROR st -7 Antenna off-source! 2006.281.08:02:02.14#trakl#az 255.373 el 15.679 azerr*cos(el) -0.0100 elerr 0.0220 2006.281.08:02:02.14#flagr#flagr/antenna,off-source 2006.281.08:02:02.77/vb/01,04,usb,yes,33,29 2006.281.08:02:02.77/vb/02,05,usb,yes,30,30 2006.281.08:02:02.77/vb/03,04,usb,yes,29,34 2006.281.08:02:02.77/vb/04,04,usb,yes,29,30 2006.281.08:02:02.77/vb/05,04,usb,yes,27,32 2006.281.08:02:02.77/vb/06,04,usb,yes,28,31 2006.281.08:02:02.77/vb/07,04,usb,yes,31,31 2006.281.08:02:02.77/vb/08,04,usb,yes,28,32 2006.281.08:02:03.01/vblo/01,632.99,yes,locked 2006.281.08:02:03.01/vblo/02,640.99,yes,locked 2006.281.08:02:03.01/vblo/03,656.99,yes,locked 2006.281.08:02:03.01/vblo/04,712.99,yes,locked 2006.281.08:02:03.01/vblo/05,744.99,yes,locked 2006.281.08:02:03.01/vblo/06,752.99,yes,locked 2006.281.08:02:03.01/vblo/07,734.99,yes,locked 2006.281.08:02:03.01/vblo/08,744.99,yes,locked 2006.281.08:02:03.16/vabw/8 2006.281.08:02:03.31/vbbw/8 2006.281.08:02:03.40/xfe/off,on,12.0 2006.281.08:02:03.77/ifatt/23,28,28,28 2006.281.08:02:04.08/fmout-gps/S +3.15E-07 2006.281.08:02:04.10:!2006.281.08:03:00 2006.281.08:02:14.14#trakl#Source re-acquired 2006.281.08:02:14.14#flagr#flagr/antenna,re-acquired 2006.281.08:02:19.14#trakl#Off source 2006.281.08:02:19.14?ERROR st -7 Antenna off-source! 2006.281.08:02:19.14#trakl#az 255.419 el 15.624 azerr*cos(el) 0.0189 elerr 0.0013 2006.281.08:02:20.14#flagr#flagr/antenna,off-source 2006.281.08:02:25.14#trakl#Source re-acquired 2006.281.08:02:26.14#flagr#flagr/antenna,re-acquired 2006.281.08:02:34.14#trakl#Off source 2006.281.08:02:34.14?ERROR st -7 Antenna off-source! 2006.281.08:02:34.14#trakl#az 255.460 el 15.575 azerr*cos(el) 0.0059 elerr -0.0279 2006.281.08:02:35.14#flagr#flagr/antenna,off-source 2006.281.08:02:40.14#trakl#Source re-acquired 2006.281.08:02:41.14#trakl#Off source 2006.281.08:02:41.14?ERROR st -7 Antenna off-source! 2006.281.08:02:41.14#trakl#az 255.479 el 15.552 azerr*cos(el) -0.0103 elerr 0.0199 2006.281.08:02:49.14#trakl#Source re-acquired 2006.281.08:02:50.14#flagr#flagr/antenna,re-acquired 2006.281.08:03:00.01:data_valid=off 2006.281.08:03:00.01:postob 2006.281.08:03:00.12/cable/+6.4871E-03 2006.281.08:03:00.12/wx/20.44,1001.4,51 2006.281.08:03:01.08/fmout-gps/S +3.15E-07 2006.281.08:03:01.08:scan_name=281-0803,k06281,70 2006.281.08:03:01.08:source=1252+119,125438.26,114105.9,2000.0,ccw 2006.281.08:03:01.14#flagr#flagr/antenna,new-source 2006.281.08:03:02.14:checkk5 2006.281.08:03:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:03:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:03:03.43/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:03:03.84/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:03:04.26/chk_obsdata//k5ts1/T2810802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:03:04.68/chk_obsdata//k5ts2/T2810802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:03:05.12/chk_obsdata//k5ts3/T2810802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:03:05.54/chk_obsdata//k5ts4/T2810802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:03:06.20/k5log//k5ts1_log_newline 2006.281.08:03:07.03/k5log//k5ts2_log_newline 2006.281.08:03:08.12/k5log//k5ts3_log_newline 2006.281.08:03:08.95/k5log//k5ts4_log_newline 2006.281.08:03:08.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:03:08.98:4f8m12a=2 2006.281.08:03:08.98$4f8m12a/echo=on 2006.281.08:03:08.98$4f8m12a/pcalon 2006.281.08:03:08.98$pcalon/"no phase cal control is implemented here 2006.281.08:03:08.98$4f8m12a/"tpicd=stop 2006.281.08:03:08.98$4f8m12a/vc4f8 2006.281.08:03:08.98$vc4f8/valo=1,532.99 2006.281.08:03:08.98#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.08:03:08.98#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.08:03:08.98#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:08.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:08.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:08.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:08.98#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:03:08.98#ibcon#first serial, iclass 34, count 0 2006.281.08:03:08.98#ibcon#enter sib2, iclass 34, count 0 2006.281.08:03:08.98#ibcon#flushed, iclass 34, count 0 2006.281.08:03:08.98#ibcon#about to write, iclass 34, count 0 2006.281.08:03:08.98#ibcon#wrote, iclass 34, count 0 2006.281.08:03:08.98#ibcon#about to read 3, iclass 34, count 0 2006.281.08:03:09.00#ibcon#read 3, iclass 34, count 0 2006.281.08:03:09.00#ibcon#about to read 4, iclass 34, count 0 2006.281.08:03:09.00#ibcon#read 4, iclass 34, count 0 2006.281.08:03:09.00#ibcon#about to read 5, iclass 34, count 0 2006.281.08:03:09.00#ibcon#read 5, iclass 34, count 0 2006.281.08:03:09.00#ibcon#about to read 6, iclass 34, count 0 2006.281.08:03:09.00#ibcon#read 6, iclass 34, count 0 2006.281.08:03:09.00#ibcon#end of sib2, iclass 34, count 0 2006.281.08:03:09.00#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:03:09.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:03:09.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:03:09.00#ibcon#*before write, iclass 34, count 0 2006.281.08:03:09.00#ibcon#enter sib2, iclass 34, count 0 2006.281.08:03:09.00#ibcon#flushed, iclass 34, count 0 2006.281.08:03:09.00#ibcon#about to write, iclass 34, count 0 2006.281.08:03:09.00#ibcon#wrote, iclass 34, count 0 2006.281.08:03:09.00#ibcon#about to read 3, iclass 34, count 0 2006.281.08:03:09.05#ibcon#read 3, iclass 34, count 0 2006.281.08:03:09.05#ibcon#about to read 4, iclass 34, count 0 2006.281.08:03:09.05#ibcon#read 4, iclass 34, count 0 2006.281.08:03:09.05#ibcon#about to read 5, iclass 34, count 0 2006.281.08:03:09.05#ibcon#read 5, iclass 34, count 0 2006.281.08:03:09.05#ibcon#about to read 6, iclass 34, count 0 2006.281.08:03:09.05#ibcon#read 6, iclass 34, count 0 2006.281.08:03:09.05#ibcon#end of sib2, iclass 34, count 0 2006.281.08:03:09.05#ibcon#*after write, iclass 34, count 0 2006.281.08:03:09.05#ibcon#*before return 0, iclass 34, count 0 2006.281.08:03:09.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:09.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:09.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:03:09.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:03:09.05$vc4f8/va=1,7 2006.281.08:03:09.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.08:03:09.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.08:03:09.05#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:09.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:09.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:09.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:09.05#ibcon#enter wrdev, iclass 36, count 2 2006.281.08:03:09.05#ibcon#first serial, iclass 36, count 2 2006.281.08:03:09.05#ibcon#enter sib2, iclass 36, count 2 2006.281.08:03:09.05#ibcon#flushed, iclass 36, count 2 2006.281.08:03:09.05#ibcon#about to write, iclass 36, count 2 2006.281.08:03:09.05#ibcon#wrote, iclass 36, count 2 2006.281.08:03:09.05#ibcon#about to read 3, iclass 36, count 2 2006.281.08:03:09.07#ibcon#read 3, iclass 36, count 2 2006.281.08:03:09.07#ibcon#about to read 4, iclass 36, count 2 2006.281.08:03:09.07#ibcon#read 4, iclass 36, count 2 2006.281.08:03:09.07#ibcon#about to read 5, iclass 36, count 2 2006.281.08:03:09.07#ibcon#read 5, iclass 36, count 2 2006.281.08:03:09.07#ibcon#about to read 6, iclass 36, count 2 2006.281.08:03:09.07#ibcon#read 6, iclass 36, count 2 2006.281.08:03:09.07#ibcon#end of sib2, iclass 36, count 2 2006.281.08:03:09.07#ibcon#*mode == 0, iclass 36, count 2 2006.281.08:03:09.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.08:03:09.07#ibcon#[25=AT01-07\r\n] 2006.281.08:03:09.07#ibcon#*before write, iclass 36, count 2 2006.281.08:03:09.07#ibcon#enter sib2, iclass 36, count 2 2006.281.08:03:09.07#ibcon#flushed, iclass 36, count 2 2006.281.08:03:09.07#ibcon#about to write, iclass 36, count 2 2006.281.08:03:09.07#ibcon#wrote, iclass 36, count 2 2006.281.08:03:09.07#ibcon#about to read 3, iclass 36, count 2 2006.281.08:03:09.10#ibcon#read 3, iclass 36, count 2 2006.281.08:03:09.10#ibcon#about to read 4, iclass 36, count 2 2006.281.08:03:09.10#ibcon#read 4, iclass 36, count 2 2006.281.08:03:09.10#ibcon#about to read 5, iclass 36, count 2 2006.281.08:03:09.10#ibcon#read 5, iclass 36, count 2 2006.281.08:03:09.10#ibcon#about to read 6, iclass 36, count 2 2006.281.08:03:09.10#ibcon#read 6, iclass 36, count 2 2006.281.08:03:09.10#ibcon#end of sib2, iclass 36, count 2 2006.281.08:03:09.10#ibcon#*after write, iclass 36, count 2 2006.281.08:03:09.10#ibcon#*before return 0, iclass 36, count 2 2006.281.08:03:09.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:09.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:09.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.08:03:09.10#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:09.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:09.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:09.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:09.22#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:03:09.22#ibcon#first serial, iclass 36, count 0 2006.281.08:03:09.22#ibcon#enter sib2, iclass 36, count 0 2006.281.08:03:09.22#ibcon#flushed, iclass 36, count 0 2006.281.08:03:09.22#ibcon#about to write, iclass 36, count 0 2006.281.08:03:09.22#ibcon#wrote, iclass 36, count 0 2006.281.08:03:09.22#ibcon#about to read 3, iclass 36, count 0 2006.281.08:03:09.24#ibcon#read 3, iclass 36, count 0 2006.281.08:03:09.24#ibcon#about to read 4, iclass 36, count 0 2006.281.08:03:09.24#ibcon#read 4, iclass 36, count 0 2006.281.08:03:09.24#ibcon#about to read 5, iclass 36, count 0 2006.281.08:03:09.24#ibcon#read 5, iclass 36, count 0 2006.281.08:03:09.24#ibcon#about to read 6, iclass 36, count 0 2006.281.08:03:09.24#ibcon#read 6, iclass 36, count 0 2006.281.08:03:09.24#ibcon#end of sib2, iclass 36, count 0 2006.281.08:03:09.24#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:03:09.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:03:09.24#ibcon#[25=USB\r\n] 2006.281.08:03:09.24#ibcon#*before write, iclass 36, count 0 2006.281.08:03:09.24#ibcon#enter sib2, iclass 36, count 0 2006.281.08:03:09.24#ibcon#flushed, iclass 36, count 0 2006.281.08:03:09.24#ibcon#about to write, iclass 36, count 0 2006.281.08:03:09.24#ibcon#wrote, iclass 36, count 0 2006.281.08:03:09.24#ibcon#about to read 3, iclass 36, count 0 2006.281.08:03:09.27#ibcon#read 3, iclass 36, count 0 2006.281.08:03:09.27#ibcon#about to read 4, iclass 36, count 0 2006.281.08:03:09.27#ibcon#read 4, iclass 36, count 0 2006.281.08:03:09.27#ibcon#about to read 5, iclass 36, count 0 2006.281.08:03:09.27#ibcon#read 5, iclass 36, count 0 2006.281.08:03:09.27#ibcon#about to read 6, iclass 36, count 0 2006.281.08:03:09.27#ibcon#read 6, iclass 36, count 0 2006.281.08:03:09.27#ibcon#end of sib2, iclass 36, count 0 2006.281.08:03:09.27#ibcon#*after write, iclass 36, count 0 2006.281.08:03:09.27#ibcon#*before return 0, iclass 36, count 0 2006.281.08:03:09.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:09.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:09.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:03:09.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:03:09.27$vc4f8/valo=2,572.99 2006.281.08:03:09.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:03:09.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:03:09.27#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:09.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:09.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:09.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:09.27#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:03:09.27#ibcon#first serial, iclass 38, count 0 2006.281.08:03:09.27#ibcon#enter sib2, iclass 38, count 0 2006.281.08:03:09.27#ibcon#flushed, iclass 38, count 0 2006.281.08:03:09.27#ibcon#about to write, iclass 38, count 0 2006.281.08:03:09.27#ibcon#wrote, iclass 38, count 0 2006.281.08:03:09.27#ibcon#about to read 3, iclass 38, count 0 2006.281.08:03:09.29#ibcon#read 3, iclass 38, count 0 2006.281.08:03:09.29#ibcon#about to read 4, iclass 38, count 0 2006.281.08:03:09.29#ibcon#read 4, iclass 38, count 0 2006.281.08:03:09.29#ibcon#about to read 5, iclass 38, count 0 2006.281.08:03:09.29#ibcon#read 5, iclass 38, count 0 2006.281.08:03:09.29#ibcon#about to read 6, iclass 38, count 0 2006.281.08:03:09.29#ibcon#read 6, iclass 38, count 0 2006.281.08:03:09.29#ibcon#end of sib2, iclass 38, count 0 2006.281.08:03:09.29#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:03:09.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:03:09.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:03:09.29#ibcon#*before write, iclass 38, count 0 2006.281.08:03:09.29#ibcon#enter sib2, iclass 38, count 0 2006.281.08:03:09.29#ibcon#flushed, iclass 38, count 0 2006.281.08:03:09.29#ibcon#about to write, iclass 38, count 0 2006.281.08:03:09.29#ibcon#wrote, iclass 38, count 0 2006.281.08:03:09.29#ibcon#about to read 3, iclass 38, count 0 2006.281.08:03:09.33#ibcon#read 3, iclass 38, count 0 2006.281.08:03:09.33#ibcon#about to read 4, iclass 38, count 0 2006.281.08:03:09.33#ibcon#read 4, iclass 38, count 0 2006.281.08:03:09.33#ibcon#about to read 5, iclass 38, count 0 2006.281.08:03:09.33#ibcon#read 5, iclass 38, count 0 2006.281.08:03:09.33#ibcon#about to read 6, iclass 38, count 0 2006.281.08:03:09.33#ibcon#read 6, iclass 38, count 0 2006.281.08:03:09.33#ibcon#end of sib2, iclass 38, count 0 2006.281.08:03:09.33#ibcon#*after write, iclass 38, count 0 2006.281.08:03:09.33#ibcon#*before return 0, iclass 38, count 0 2006.281.08:03:09.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:09.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:09.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:03:09.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:03:09.33$vc4f8/va=2,6 2006.281.08:03:09.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:03:09.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:03:09.33#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:09.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:09.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:09.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:09.39#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:03:09.39#ibcon#first serial, iclass 40, count 2 2006.281.08:03:09.39#ibcon#enter sib2, iclass 40, count 2 2006.281.08:03:09.39#ibcon#flushed, iclass 40, count 2 2006.281.08:03:09.39#ibcon#about to write, iclass 40, count 2 2006.281.08:03:09.39#ibcon#wrote, iclass 40, count 2 2006.281.08:03:09.39#ibcon#about to read 3, iclass 40, count 2 2006.281.08:03:09.41#ibcon#read 3, iclass 40, count 2 2006.281.08:03:09.41#ibcon#about to read 4, iclass 40, count 2 2006.281.08:03:09.41#ibcon#read 4, iclass 40, count 2 2006.281.08:03:09.41#ibcon#about to read 5, iclass 40, count 2 2006.281.08:03:09.41#ibcon#read 5, iclass 40, count 2 2006.281.08:03:09.41#ibcon#about to read 6, iclass 40, count 2 2006.281.08:03:09.41#ibcon#read 6, iclass 40, count 2 2006.281.08:03:09.41#ibcon#end of sib2, iclass 40, count 2 2006.281.08:03:09.41#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:03:09.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:03:09.41#ibcon#[25=AT02-06\r\n] 2006.281.08:03:09.41#ibcon#*before write, iclass 40, count 2 2006.281.08:03:09.41#ibcon#enter sib2, iclass 40, count 2 2006.281.08:03:09.41#ibcon#flushed, iclass 40, count 2 2006.281.08:03:09.41#ibcon#about to write, iclass 40, count 2 2006.281.08:03:09.41#ibcon#wrote, iclass 40, count 2 2006.281.08:03:09.41#ibcon#about to read 3, iclass 40, count 2 2006.281.08:03:09.44#ibcon#read 3, iclass 40, count 2 2006.281.08:03:09.44#ibcon#about to read 4, iclass 40, count 2 2006.281.08:03:09.44#ibcon#read 4, iclass 40, count 2 2006.281.08:03:09.44#ibcon#about to read 5, iclass 40, count 2 2006.281.08:03:09.44#ibcon#read 5, iclass 40, count 2 2006.281.08:03:09.44#ibcon#about to read 6, iclass 40, count 2 2006.281.08:03:09.44#ibcon#read 6, iclass 40, count 2 2006.281.08:03:09.44#ibcon#end of sib2, iclass 40, count 2 2006.281.08:03:09.44#ibcon#*after write, iclass 40, count 2 2006.281.08:03:09.44#ibcon#*before return 0, iclass 40, count 2 2006.281.08:03:09.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:09.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:09.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:03:09.44#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:09.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:09.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:09.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:09.56#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:03:09.56#ibcon#first serial, iclass 40, count 0 2006.281.08:03:09.56#ibcon#enter sib2, iclass 40, count 0 2006.281.08:03:09.56#ibcon#flushed, iclass 40, count 0 2006.281.08:03:09.56#ibcon#about to write, iclass 40, count 0 2006.281.08:03:09.56#ibcon#wrote, iclass 40, count 0 2006.281.08:03:09.56#ibcon#about to read 3, iclass 40, count 0 2006.281.08:03:09.58#ibcon#read 3, iclass 40, count 0 2006.281.08:03:09.58#ibcon#about to read 4, iclass 40, count 0 2006.281.08:03:09.58#ibcon#read 4, iclass 40, count 0 2006.281.08:03:09.58#ibcon#about to read 5, iclass 40, count 0 2006.281.08:03:09.58#ibcon#read 5, iclass 40, count 0 2006.281.08:03:09.58#ibcon#about to read 6, iclass 40, count 0 2006.281.08:03:09.58#ibcon#read 6, iclass 40, count 0 2006.281.08:03:09.58#ibcon#end of sib2, iclass 40, count 0 2006.281.08:03:09.58#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:03:09.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:03:09.58#ibcon#[25=USB\r\n] 2006.281.08:03:09.58#ibcon#*before write, iclass 40, count 0 2006.281.08:03:09.58#ibcon#enter sib2, iclass 40, count 0 2006.281.08:03:09.58#ibcon#flushed, iclass 40, count 0 2006.281.08:03:09.58#ibcon#about to write, iclass 40, count 0 2006.281.08:03:09.58#ibcon#wrote, iclass 40, count 0 2006.281.08:03:09.58#ibcon#about to read 3, iclass 40, count 0 2006.281.08:03:09.61#ibcon#read 3, iclass 40, count 0 2006.281.08:03:09.61#ibcon#about to read 4, iclass 40, count 0 2006.281.08:03:09.61#ibcon#read 4, iclass 40, count 0 2006.281.08:03:09.61#ibcon#about to read 5, iclass 40, count 0 2006.281.08:03:09.61#ibcon#read 5, iclass 40, count 0 2006.281.08:03:09.61#ibcon#about to read 6, iclass 40, count 0 2006.281.08:03:09.61#ibcon#read 6, iclass 40, count 0 2006.281.08:03:09.61#ibcon#end of sib2, iclass 40, count 0 2006.281.08:03:09.61#ibcon#*after write, iclass 40, count 0 2006.281.08:03:09.61#ibcon#*before return 0, iclass 40, count 0 2006.281.08:03:09.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:09.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:09.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:03:09.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:03:09.61$vc4f8/valo=3,672.99 2006.281.08:03:09.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:03:09.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:03:09.61#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:09.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:09.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:09.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:09.61#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:03:09.61#ibcon#first serial, iclass 4, count 0 2006.281.08:03:09.61#ibcon#enter sib2, iclass 4, count 0 2006.281.08:03:09.61#ibcon#flushed, iclass 4, count 0 2006.281.08:03:09.61#ibcon#about to write, iclass 4, count 0 2006.281.08:03:09.61#ibcon#wrote, iclass 4, count 0 2006.281.08:03:09.61#ibcon#about to read 3, iclass 4, count 0 2006.281.08:03:09.63#ibcon#read 3, iclass 4, count 0 2006.281.08:03:09.63#ibcon#about to read 4, iclass 4, count 0 2006.281.08:03:09.63#ibcon#read 4, iclass 4, count 0 2006.281.08:03:09.63#ibcon#about to read 5, iclass 4, count 0 2006.281.08:03:09.63#ibcon#read 5, iclass 4, count 0 2006.281.08:03:09.63#ibcon#about to read 6, iclass 4, count 0 2006.281.08:03:09.63#ibcon#read 6, iclass 4, count 0 2006.281.08:03:09.63#ibcon#end of sib2, iclass 4, count 0 2006.281.08:03:09.63#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:03:09.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:03:09.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:03:09.63#ibcon#*before write, iclass 4, count 0 2006.281.08:03:09.63#ibcon#enter sib2, iclass 4, count 0 2006.281.08:03:09.63#ibcon#flushed, iclass 4, count 0 2006.281.08:03:09.63#ibcon#about to write, iclass 4, count 0 2006.281.08:03:09.63#ibcon#wrote, iclass 4, count 0 2006.281.08:03:09.63#ibcon#about to read 3, iclass 4, count 0 2006.281.08:03:09.67#ibcon#read 3, iclass 4, count 0 2006.281.08:03:09.67#ibcon#about to read 4, iclass 4, count 0 2006.281.08:03:09.67#ibcon#read 4, iclass 4, count 0 2006.281.08:03:09.67#ibcon#about to read 5, iclass 4, count 0 2006.281.08:03:09.67#ibcon#read 5, iclass 4, count 0 2006.281.08:03:09.67#ibcon#about to read 6, iclass 4, count 0 2006.281.08:03:09.67#ibcon#read 6, iclass 4, count 0 2006.281.08:03:09.67#ibcon#end of sib2, iclass 4, count 0 2006.281.08:03:09.67#ibcon#*after write, iclass 4, count 0 2006.281.08:03:09.67#ibcon#*before return 0, iclass 4, count 0 2006.281.08:03:09.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:09.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:09.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:03:09.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:03:09.67$vc4f8/va=3,6 2006.281.08:03:09.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.08:03:09.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.08:03:09.68#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:09.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:09.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:09.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:09.73#ibcon#enter wrdev, iclass 6, count 2 2006.281.08:03:09.73#ibcon#first serial, iclass 6, count 2 2006.281.08:03:09.73#ibcon#enter sib2, iclass 6, count 2 2006.281.08:03:09.73#ibcon#flushed, iclass 6, count 2 2006.281.08:03:09.73#ibcon#about to write, iclass 6, count 2 2006.281.08:03:09.73#ibcon#wrote, iclass 6, count 2 2006.281.08:03:09.73#ibcon#about to read 3, iclass 6, count 2 2006.281.08:03:09.75#ibcon#read 3, iclass 6, count 2 2006.281.08:03:09.75#ibcon#about to read 4, iclass 6, count 2 2006.281.08:03:09.75#ibcon#read 4, iclass 6, count 2 2006.281.08:03:09.75#ibcon#about to read 5, iclass 6, count 2 2006.281.08:03:09.75#ibcon#read 5, iclass 6, count 2 2006.281.08:03:09.75#ibcon#about to read 6, iclass 6, count 2 2006.281.08:03:09.75#ibcon#read 6, iclass 6, count 2 2006.281.08:03:09.75#ibcon#end of sib2, iclass 6, count 2 2006.281.08:03:09.75#ibcon#*mode == 0, iclass 6, count 2 2006.281.08:03:09.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.08:03:09.75#ibcon#[25=AT03-06\r\n] 2006.281.08:03:09.75#ibcon#*before write, iclass 6, count 2 2006.281.08:03:09.75#ibcon#enter sib2, iclass 6, count 2 2006.281.08:03:09.75#ibcon#flushed, iclass 6, count 2 2006.281.08:03:09.75#ibcon#about to write, iclass 6, count 2 2006.281.08:03:09.75#ibcon#wrote, iclass 6, count 2 2006.281.08:03:09.75#ibcon#about to read 3, iclass 6, count 2 2006.281.08:03:09.78#ibcon#read 3, iclass 6, count 2 2006.281.08:03:09.78#ibcon#about to read 4, iclass 6, count 2 2006.281.08:03:09.78#ibcon#read 4, iclass 6, count 2 2006.281.08:03:09.78#ibcon#about to read 5, iclass 6, count 2 2006.281.08:03:09.78#ibcon#read 5, iclass 6, count 2 2006.281.08:03:09.78#ibcon#about to read 6, iclass 6, count 2 2006.281.08:03:09.78#ibcon#read 6, iclass 6, count 2 2006.281.08:03:09.78#ibcon#end of sib2, iclass 6, count 2 2006.281.08:03:09.78#ibcon#*after write, iclass 6, count 2 2006.281.08:03:09.78#ibcon#*before return 0, iclass 6, count 2 2006.281.08:03:09.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:09.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:09.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.08:03:09.78#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:09.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:09.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:09.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:09.90#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:03:09.90#ibcon#first serial, iclass 6, count 0 2006.281.08:03:09.90#ibcon#enter sib2, iclass 6, count 0 2006.281.08:03:09.90#ibcon#flushed, iclass 6, count 0 2006.281.08:03:09.90#ibcon#about to write, iclass 6, count 0 2006.281.08:03:09.90#ibcon#wrote, iclass 6, count 0 2006.281.08:03:09.90#ibcon#about to read 3, iclass 6, count 0 2006.281.08:03:09.92#ibcon#read 3, iclass 6, count 0 2006.281.08:03:09.92#ibcon#about to read 4, iclass 6, count 0 2006.281.08:03:09.92#ibcon#read 4, iclass 6, count 0 2006.281.08:03:09.92#ibcon#about to read 5, iclass 6, count 0 2006.281.08:03:09.92#ibcon#read 5, iclass 6, count 0 2006.281.08:03:09.92#ibcon#about to read 6, iclass 6, count 0 2006.281.08:03:09.92#ibcon#read 6, iclass 6, count 0 2006.281.08:03:09.92#ibcon#end of sib2, iclass 6, count 0 2006.281.08:03:09.92#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:03:09.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:03:09.92#ibcon#[25=USB\r\n] 2006.281.08:03:09.92#ibcon#*before write, iclass 6, count 0 2006.281.08:03:09.92#ibcon#enter sib2, iclass 6, count 0 2006.281.08:03:09.92#ibcon#flushed, iclass 6, count 0 2006.281.08:03:09.92#ibcon#about to write, iclass 6, count 0 2006.281.08:03:09.92#ibcon#wrote, iclass 6, count 0 2006.281.08:03:09.92#ibcon#about to read 3, iclass 6, count 0 2006.281.08:03:09.95#ibcon#read 3, iclass 6, count 0 2006.281.08:03:09.95#ibcon#about to read 4, iclass 6, count 0 2006.281.08:03:09.95#ibcon#read 4, iclass 6, count 0 2006.281.08:03:09.95#ibcon#about to read 5, iclass 6, count 0 2006.281.08:03:09.95#ibcon#read 5, iclass 6, count 0 2006.281.08:03:09.95#ibcon#about to read 6, iclass 6, count 0 2006.281.08:03:09.95#ibcon#read 6, iclass 6, count 0 2006.281.08:03:09.95#ibcon#end of sib2, iclass 6, count 0 2006.281.08:03:09.95#ibcon#*after write, iclass 6, count 0 2006.281.08:03:09.95#ibcon#*before return 0, iclass 6, count 0 2006.281.08:03:09.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:09.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:09.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:03:09.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:03:09.95$vc4f8/valo=4,832.99 2006.281.08:03:09.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.08:03:09.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.08:03:09.95#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:09.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:09.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:09.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:09.95#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:03:09.95#ibcon#first serial, iclass 10, count 0 2006.281.08:03:09.95#ibcon#enter sib2, iclass 10, count 0 2006.281.08:03:09.95#ibcon#flushed, iclass 10, count 0 2006.281.08:03:09.95#ibcon#about to write, iclass 10, count 0 2006.281.08:03:09.95#ibcon#wrote, iclass 10, count 0 2006.281.08:03:09.95#ibcon#about to read 3, iclass 10, count 0 2006.281.08:03:09.97#ibcon#read 3, iclass 10, count 0 2006.281.08:03:09.97#ibcon#about to read 4, iclass 10, count 0 2006.281.08:03:09.97#ibcon#read 4, iclass 10, count 0 2006.281.08:03:09.97#ibcon#about to read 5, iclass 10, count 0 2006.281.08:03:09.97#ibcon#read 5, iclass 10, count 0 2006.281.08:03:09.97#ibcon#about to read 6, iclass 10, count 0 2006.281.08:03:09.97#ibcon#read 6, iclass 10, count 0 2006.281.08:03:09.97#ibcon#end of sib2, iclass 10, count 0 2006.281.08:03:09.97#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:03:09.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:03:09.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:03:09.97#ibcon#*before write, iclass 10, count 0 2006.281.08:03:09.97#ibcon#enter sib2, iclass 10, count 0 2006.281.08:03:09.97#ibcon#flushed, iclass 10, count 0 2006.281.08:03:09.97#ibcon#about to write, iclass 10, count 0 2006.281.08:03:09.97#ibcon#wrote, iclass 10, count 0 2006.281.08:03:09.97#ibcon#about to read 3, iclass 10, count 0 2006.281.08:03:10.02#ibcon#read 3, iclass 10, count 0 2006.281.08:03:10.02#ibcon#about to read 4, iclass 10, count 0 2006.281.08:03:10.02#ibcon#read 4, iclass 10, count 0 2006.281.08:03:10.02#ibcon#about to read 5, iclass 10, count 0 2006.281.08:03:10.02#ibcon#read 5, iclass 10, count 0 2006.281.08:03:10.02#ibcon#about to read 6, iclass 10, count 0 2006.281.08:03:10.02#ibcon#read 6, iclass 10, count 0 2006.281.08:03:10.02#ibcon#end of sib2, iclass 10, count 0 2006.281.08:03:10.02#ibcon#*after write, iclass 10, count 0 2006.281.08:03:10.02#ibcon#*before return 0, iclass 10, count 0 2006.281.08:03:10.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:10.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:10.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:03:10.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:03:10.02$vc4f8/va=4,6 2006.281.08:03:10.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.08:03:10.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.08:03:10.02#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:10.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:10.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:10.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:10.07#ibcon#enter wrdev, iclass 12, count 2 2006.281.08:03:10.07#ibcon#first serial, iclass 12, count 2 2006.281.08:03:10.07#ibcon#enter sib2, iclass 12, count 2 2006.281.08:03:10.07#ibcon#flushed, iclass 12, count 2 2006.281.08:03:10.07#ibcon#about to write, iclass 12, count 2 2006.281.08:03:10.07#ibcon#wrote, iclass 12, count 2 2006.281.08:03:10.07#ibcon#about to read 3, iclass 12, count 2 2006.281.08:03:10.09#ibcon#read 3, iclass 12, count 2 2006.281.08:03:10.09#ibcon#about to read 4, iclass 12, count 2 2006.281.08:03:10.09#ibcon#read 4, iclass 12, count 2 2006.281.08:03:10.09#ibcon#about to read 5, iclass 12, count 2 2006.281.08:03:10.09#ibcon#read 5, iclass 12, count 2 2006.281.08:03:10.09#ibcon#about to read 6, iclass 12, count 2 2006.281.08:03:10.09#ibcon#read 6, iclass 12, count 2 2006.281.08:03:10.09#ibcon#end of sib2, iclass 12, count 2 2006.281.08:03:10.09#ibcon#*mode == 0, iclass 12, count 2 2006.281.08:03:10.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.08:03:10.09#ibcon#[25=AT04-06\r\n] 2006.281.08:03:10.09#ibcon#*before write, iclass 12, count 2 2006.281.08:03:10.09#ibcon#enter sib2, iclass 12, count 2 2006.281.08:03:10.09#ibcon#flushed, iclass 12, count 2 2006.281.08:03:10.09#ibcon#about to write, iclass 12, count 2 2006.281.08:03:10.09#ibcon#wrote, iclass 12, count 2 2006.281.08:03:10.09#ibcon#about to read 3, iclass 12, count 2 2006.281.08:03:10.12#ibcon#read 3, iclass 12, count 2 2006.281.08:03:10.12#ibcon#about to read 4, iclass 12, count 2 2006.281.08:03:10.12#ibcon#read 4, iclass 12, count 2 2006.281.08:03:10.12#ibcon#about to read 5, iclass 12, count 2 2006.281.08:03:10.12#ibcon#read 5, iclass 12, count 2 2006.281.08:03:10.12#ibcon#about to read 6, iclass 12, count 2 2006.281.08:03:10.12#ibcon#read 6, iclass 12, count 2 2006.281.08:03:10.12#ibcon#end of sib2, iclass 12, count 2 2006.281.08:03:10.12#ibcon#*after write, iclass 12, count 2 2006.281.08:03:10.12#ibcon#*before return 0, iclass 12, count 2 2006.281.08:03:10.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:10.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:10.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.08:03:10.12#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:10.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:10.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:10.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:10.24#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:03:10.24#ibcon#first serial, iclass 12, count 0 2006.281.08:03:10.24#ibcon#enter sib2, iclass 12, count 0 2006.281.08:03:10.24#ibcon#flushed, iclass 12, count 0 2006.281.08:03:10.24#ibcon#about to write, iclass 12, count 0 2006.281.08:03:10.24#ibcon#wrote, iclass 12, count 0 2006.281.08:03:10.24#ibcon#about to read 3, iclass 12, count 0 2006.281.08:03:10.26#ibcon#read 3, iclass 12, count 0 2006.281.08:03:10.26#ibcon#about to read 4, iclass 12, count 0 2006.281.08:03:10.26#ibcon#read 4, iclass 12, count 0 2006.281.08:03:10.26#ibcon#about to read 5, iclass 12, count 0 2006.281.08:03:10.26#ibcon#read 5, iclass 12, count 0 2006.281.08:03:10.26#ibcon#about to read 6, iclass 12, count 0 2006.281.08:03:10.26#ibcon#read 6, iclass 12, count 0 2006.281.08:03:10.26#ibcon#end of sib2, iclass 12, count 0 2006.281.08:03:10.26#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:03:10.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:03:10.26#ibcon#[25=USB\r\n] 2006.281.08:03:10.26#ibcon#*before write, iclass 12, count 0 2006.281.08:03:10.26#ibcon#enter sib2, iclass 12, count 0 2006.281.08:03:10.26#ibcon#flushed, iclass 12, count 0 2006.281.08:03:10.26#ibcon#about to write, iclass 12, count 0 2006.281.08:03:10.26#ibcon#wrote, iclass 12, count 0 2006.281.08:03:10.26#ibcon#about to read 3, iclass 12, count 0 2006.281.08:03:10.29#ibcon#read 3, iclass 12, count 0 2006.281.08:03:10.29#ibcon#about to read 4, iclass 12, count 0 2006.281.08:03:10.29#ibcon#read 4, iclass 12, count 0 2006.281.08:03:10.29#ibcon#about to read 5, iclass 12, count 0 2006.281.08:03:10.29#ibcon#read 5, iclass 12, count 0 2006.281.08:03:10.29#ibcon#about to read 6, iclass 12, count 0 2006.281.08:03:10.29#ibcon#read 6, iclass 12, count 0 2006.281.08:03:10.29#ibcon#end of sib2, iclass 12, count 0 2006.281.08:03:10.29#ibcon#*after write, iclass 12, count 0 2006.281.08:03:10.29#ibcon#*before return 0, iclass 12, count 0 2006.281.08:03:10.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:10.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:10.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:03:10.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:03:10.29$vc4f8/valo=5,652.99 2006.281.08:03:10.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:03:10.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:03:10.29#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:10.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:10.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:10.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:10.29#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:03:10.29#ibcon#first serial, iclass 14, count 0 2006.281.08:03:10.29#ibcon#enter sib2, iclass 14, count 0 2006.281.08:03:10.29#ibcon#flushed, iclass 14, count 0 2006.281.08:03:10.29#ibcon#about to write, iclass 14, count 0 2006.281.08:03:10.29#ibcon#wrote, iclass 14, count 0 2006.281.08:03:10.29#ibcon#about to read 3, iclass 14, count 0 2006.281.08:03:10.31#ibcon#read 3, iclass 14, count 0 2006.281.08:03:10.31#ibcon#about to read 4, iclass 14, count 0 2006.281.08:03:10.31#ibcon#read 4, iclass 14, count 0 2006.281.08:03:10.31#ibcon#about to read 5, iclass 14, count 0 2006.281.08:03:10.31#ibcon#read 5, iclass 14, count 0 2006.281.08:03:10.31#ibcon#about to read 6, iclass 14, count 0 2006.281.08:03:10.31#ibcon#read 6, iclass 14, count 0 2006.281.08:03:10.31#ibcon#end of sib2, iclass 14, count 0 2006.281.08:03:10.31#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:03:10.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:03:10.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:03:10.31#ibcon#*before write, iclass 14, count 0 2006.281.08:03:10.31#ibcon#enter sib2, iclass 14, count 0 2006.281.08:03:10.31#ibcon#flushed, iclass 14, count 0 2006.281.08:03:10.31#ibcon#about to write, iclass 14, count 0 2006.281.08:03:10.31#ibcon#wrote, iclass 14, count 0 2006.281.08:03:10.31#ibcon#about to read 3, iclass 14, count 0 2006.281.08:03:10.35#ibcon#read 3, iclass 14, count 0 2006.281.08:03:10.35#ibcon#about to read 4, iclass 14, count 0 2006.281.08:03:10.35#ibcon#read 4, iclass 14, count 0 2006.281.08:03:10.35#ibcon#about to read 5, iclass 14, count 0 2006.281.08:03:10.35#ibcon#read 5, iclass 14, count 0 2006.281.08:03:10.35#ibcon#about to read 6, iclass 14, count 0 2006.281.08:03:10.35#ibcon#read 6, iclass 14, count 0 2006.281.08:03:10.35#ibcon#end of sib2, iclass 14, count 0 2006.281.08:03:10.35#ibcon#*after write, iclass 14, count 0 2006.281.08:03:10.35#ibcon#*before return 0, iclass 14, count 0 2006.281.08:03:10.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:10.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:10.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:03:10.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:03:10.35$vc4f8/va=5,7 2006.281.08:03:10.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.08:03:10.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.08:03:10.35#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:10.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:10.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:10.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:10.41#ibcon#enter wrdev, iclass 16, count 2 2006.281.08:03:10.41#ibcon#first serial, iclass 16, count 2 2006.281.08:03:10.41#ibcon#enter sib2, iclass 16, count 2 2006.281.08:03:10.41#ibcon#flushed, iclass 16, count 2 2006.281.08:03:10.41#ibcon#about to write, iclass 16, count 2 2006.281.08:03:10.41#ibcon#wrote, iclass 16, count 2 2006.281.08:03:10.41#ibcon#about to read 3, iclass 16, count 2 2006.281.08:03:10.43#ibcon#read 3, iclass 16, count 2 2006.281.08:03:10.43#ibcon#about to read 4, iclass 16, count 2 2006.281.08:03:10.43#ibcon#read 4, iclass 16, count 2 2006.281.08:03:10.43#ibcon#about to read 5, iclass 16, count 2 2006.281.08:03:10.43#ibcon#read 5, iclass 16, count 2 2006.281.08:03:10.43#ibcon#about to read 6, iclass 16, count 2 2006.281.08:03:10.43#ibcon#read 6, iclass 16, count 2 2006.281.08:03:10.43#ibcon#end of sib2, iclass 16, count 2 2006.281.08:03:10.43#ibcon#*mode == 0, iclass 16, count 2 2006.281.08:03:10.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.08:03:10.43#ibcon#[25=AT05-07\r\n] 2006.281.08:03:10.43#ibcon#*before write, iclass 16, count 2 2006.281.08:03:10.43#ibcon#enter sib2, iclass 16, count 2 2006.281.08:03:10.43#ibcon#flushed, iclass 16, count 2 2006.281.08:03:10.43#ibcon#about to write, iclass 16, count 2 2006.281.08:03:10.43#ibcon#wrote, iclass 16, count 2 2006.281.08:03:10.43#ibcon#about to read 3, iclass 16, count 2 2006.281.08:03:10.46#ibcon#read 3, iclass 16, count 2 2006.281.08:03:10.46#ibcon#about to read 4, iclass 16, count 2 2006.281.08:03:10.46#ibcon#read 4, iclass 16, count 2 2006.281.08:03:10.46#ibcon#about to read 5, iclass 16, count 2 2006.281.08:03:10.46#ibcon#read 5, iclass 16, count 2 2006.281.08:03:10.46#ibcon#about to read 6, iclass 16, count 2 2006.281.08:03:10.46#ibcon#read 6, iclass 16, count 2 2006.281.08:03:10.46#ibcon#end of sib2, iclass 16, count 2 2006.281.08:03:10.46#ibcon#*after write, iclass 16, count 2 2006.281.08:03:10.46#ibcon#*before return 0, iclass 16, count 2 2006.281.08:03:10.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:10.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:10.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.08:03:10.46#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:10.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:10.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:10.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:10.58#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:03:10.58#ibcon#first serial, iclass 16, count 0 2006.281.08:03:10.58#ibcon#enter sib2, iclass 16, count 0 2006.281.08:03:10.58#ibcon#flushed, iclass 16, count 0 2006.281.08:03:10.58#ibcon#about to write, iclass 16, count 0 2006.281.08:03:10.58#ibcon#wrote, iclass 16, count 0 2006.281.08:03:10.58#ibcon#about to read 3, iclass 16, count 0 2006.281.08:03:10.60#ibcon#read 3, iclass 16, count 0 2006.281.08:03:10.60#ibcon#about to read 4, iclass 16, count 0 2006.281.08:03:10.60#ibcon#read 4, iclass 16, count 0 2006.281.08:03:10.60#ibcon#about to read 5, iclass 16, count 0 2006.281.08:03:10.60#ibcon#read 5, iclass 16, count 0 2006.281.08:03:10.60#ibcon#about to read 6, iclass 16, count 0 2006.281.08:03:10.60#ibcon#read 6, iclass 16, count 0 2006.281.08:03:10.60#ibcon#end of sib2, iclass 16, count 0 2006.281.08:03:10.60#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:03:10.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:03:10.60#ibcon#[25=USB\r\n] 2006.281.08:03:10.60#ibcon#*before write, iclass 16, count 0 2006.281.08:03:10.60#ibcon#enter sib2, iclass 16, count 0 2006.281.08:03:10.60#ibcon#flushed, iclass 16, count 0 2006.281.08:03:10.60#ibcon#about to write, iclass 16, count 0 2006.281.08:03:10.60#ibcon#wrote, iclass 16, count 0 2006.281.08:03:10.60#ibcon#about to read 3, iclass 16, count 0 2006.281.08:03:10.63#ibcon#read 3, iclass 16, count 0 2006.281.08:03:10.63#ibcon#about to read 4, iclass 16, count 0 2006.281.08:03:10.63#ibcon#read 4, iclass 16, count 0 2006.281.08:03:10.63#ibcon#about to read 5, iclass 16, count 0 2006.281.08:03:10.63#ibcon#read 5, iclass 16, count 0 2006.281.08:03:10.63#ibcon#about to read 6, iclass 16, count 0 2006.281.08:03:10.63#ibcon#read 6, iclass 16, count 0 2006.281.08:03:10.63#ibcon#end of sib2, iclass 16, count 0 2006.281.08:03:10.63#ibcon#*after write, iclass 16, count 0 2006.281.08:03:10.63#ibcon#*before return 0, iclass 16, count 0 2006.281.08:03:10.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:10.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:10.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:03:10.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:03:10.63$vc4f8/valo=6,772.99 2006.281.08:03:10.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.08:03:10.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.08:03:10.63#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:10.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:10.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:10.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:10.63#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:03:10.63#ibcon#first serial, iclass 18, count 0 2006.281.08:03:10.63#ibcon#enter sib2, iclass 18, count 0 2006.281.08:03:10.63#ibcon#flushed, iclass 18, count 0 2006.281.08:03:10.63#ibcon#about to write, iclass 18, count 0 2006.281.08:03:10.63#ibcon#wrote, iclass 18, count 0 2006.281.08:03:10.63#ibcon#about to read 3, iclass 18, count 0 2006.281.08:03:10.65#ibcon#read 3, iclass 18, count 0 2006.281.08:03:10.65#ibcon#about to read 4, iclass 18, count 0 2006.281.08:03:10.65#ibcon#read 4, iclass 18, count 0 2006.281.08:03:10.65#ibcon#about to read 5, iclass 18, count 0 2006.281.08:03:10.65#ibcon#read 5, iclass 18, count 0 2006.281.08:03:10.65#ibcon#about to read 6, iclass 18, count 0 2006.281.08:03:10.65#ibcon#read 6, iclass 18, count 0 2006.281.08:03:10.65#ibcon#end of sib2, iclass 18, count 0 2006.281.08:03:10.65#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:03:10.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:03:10.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:03:10.65#ibcon#*before write, iclass 18, count 0 2006.281.08:03:10.65#ibcon#enter sib2, iclass 18, count 0 2006.281.08:03:10.65#ibcon#flushed, iclass 18, count 0 2006.281.08:03:10.65#ibcon#about to write, iclass 18, count 0 2006.281.08:03:10.65#ibcon#wrote, iclass 18, count 0 2006.281.08:03:10.65#ibcon#about to read 3, iclass 18, count 0 2006.281.08:03:10.69#ibcon#read 3, iclass 18, count 0 2006.281.08:03:10.69#ibcon#about to read 4, iclass 18, count 0 2006.281.08:03:10.69#ibcon#read 4, iclass 18, count 0 2006.281.08:03:10.69#ibcon#about to read 5, iclass 18, count 0 2006.281.08:03:10.69#ibcon#read 5, iclass 18, count 0 2006.281.08:03:10.69#ibcon#about to read 6, iclass 18, count 0 2006.281.08:03:10.69#ibcon#read 6, iclass 18, count 0 2006.281.08:03:10.69#ibcon#end of sib2, iclass 18, count 0 2006.281.08:03:10.69#ibcon#*after write, iclass 18, count 0 2006.281.08:03:10.69#ibcon#*before return 0, iclass 18, count 0 2006.281.08:03:10.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:10.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:10.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:03:10.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:03:10.69$vc4f8/va=6,6 2006.281.08:03:10.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.08:03:10.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.08:03:10.70#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:10.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:10.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:10.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:10.75#ibcon#enter wrdev, iclass 20, count 2 2006.281.08:03:10.75#ibcon#first serial, iclass 20, count 2 2006.281.08:03:10.75#ibcon#enter sib2, iclass 20, count 2 2006.281.08:03:10.75#ibcon#flushed, iclass 20, count 2 2006.281.08:03:10.75#ibcon#about to write, iclass 20, count 2 2006.281.08:03:10.75#ibcon#wrote, iclass 20, count 2 2006.281.08:03:10.75#ibcon#about to read 3, iclass 20, count 2 2006.281.08:03:10.77#ibcon#read 3, iclass 20, count 2 2006.281.08:03:10.77#ibcon#about to read 4, iclass 20, count 2 2006.281.08:03:10.77#ibcon#read 4, iclass 20, count 2 2006.281.08:03:10.77#ibcon#about to read 5, iclass 20, count 2 2006.281.08:03:10.77#ibcon#read 5, iclass 20, count 2 2006.281.08:03:10.77#ibcon#about to read 6, iclass 20, count 2 2006.281.08:03:10.77#ibcon#read 6, iclass 20, count 2 2006.281.08:03:10.77#ibcon#end of sib2, iclass 20, count 2 2006.281.08:03:10.77#ibcon#*mode == 0, iclass 20, count 2 2006.281.08:03:10.77#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.08:03:10.77#ibcon#[25=AT06-06\r\n] 2006.281.08:03:10.77#ibcon#*before write, iclass 20, count 2 2006.281.08:03:10.77#ibcon#enter sib2, iclass 20, count 2 2006.281.08:03:10.77#ibcon#flushed, iclass 20, count 2 2006.281.08:03:10.77#ibcon#about to write, iclass 20, count 2 2006.281.08:03:10.77#ibcon#wrote, iclass 20, count 2 2006.281.08:03:10.77#ibcon#about to read 3, iclass 20, count 2 2006.281.08:03:10.80#ibcon#read 3, iclass 20, count 2 2006.281.08:03:10.80#ibcon#about to read 4, iclass 20, count 2 2006.281.08:03:10.80#ibcon#read 4, iclass 20, count 2 2006.281.08:03:10.80#ibcon#about to read 5, iclass 20, count 2 2006.281.08:03:10.80#ibcon#read 5, iclass 20, count 2 2006.281.08:03:10.80#ibcon#about to read 6, iclass 20, count 2 2006.281.08:03:10.80#ibcon#read 6, iclass 20, count 2 2006.281.08:03:10.80#ibcon#end of sib2, iclass 20, count 2 2006.281.08:03:10.80#ibcon#*after write, iclass 20, count 2 2006.281.08:03:10.80#ibcon#*before return 0, iclass 20, count 2 2006.281.08:03:10.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:10.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:10.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.08:03:10.80#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:10.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:03:10.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:03:10.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:03:10.92#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:03:10.92#ibcon#first serial, iclass 20, count 0 2006.281.08:03:10.92#ibcon#enter sib2, iclass 20, count 0 2006.281.08:03:10.92#ibcon#flushed, iclass 20, count 0 2006.281.08:03:10.92#ibcon#about to write, iclass 20, count 0 2006.281.08:03:10.92#ibcon#wrote, iclass 20, count 0 2006.281.08:03:10.92#ibcon#about to read 3, iclass 20, count 0 2006.281.08:03:10.94#ibcon#read 3, iclass 20, count 0 2006.281.08:03:10.94#ibcon#about to read 4, iclass 20, count 0 2006.281.08:03:10.94#ibcon#read 4, iclass 20, count 0 2006.281.08:03:10.94#ibcon#about to read 5, iclass 20, count 0 2006.281.08:03:10.94#ibcon#read 5, iclass 20, count 0 2006.281.08:03:10.94#ibcon#about to read 6, iclass 20, count 0 2006.281.08:03:10.94#ibcon#read 6, iclass 20, count 0 2006.281.08:03:10.94#ibcon#end of sib2, iclass 20, count 0 2006.281.08:03:10.94#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:03:10.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:03:10.94#ibcon#[25=USB\r\n] 2006.281.08:03:10.94#ibcon#*before write, iclass 20, count 0 2006.281.08:03:10.94#ibcon#enter sib2, iclass 20, count 0 2006.281.08:03:10.94#ibcon#flushed, iclass 20, count 0 2006.281.08:03:10.94#ibcon#about to write, iclass 20, count 0 2006.281.08:03:10.94#ibcon#wrote, iclass 20, count 0 2006.281.08:03:10.94#ibcon#about to read 3, iclass 20, count 0 2006.281.08:03:10.97#ibcon#read 3, iclass 20, count 0 2006.281.08:03:10.97#ibcon#about to read 4, iclass 20, count 0 2006.281.08:03:10.97#ibcon#read 4, iclass 20, count 0 2006.281.08:03:10.97#ibcon#about to read 5, iclass 20, count 0 2006.281.08:03:10.97#ibcon#read 5, iclass 20, count 0 2006.281.08:03:10.97#ibcon#about to read 6, iclass 20, count 0 2006.281.08:03:10.97#ibcon#read 6, iclass 20, count 0 2006.281.08:03:10.97#ibcon#end of sib2, iclass 20, count 0 2006.281.08:03:10.97#ibcon#*after write, iclass 20, count 0 2006.281.08:03:10.97#ibcon#*before return 0, iclass 20, count 0 2006.281.08:03:10.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:03:10.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:03:10.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:03:10.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:03:10.97$vc4f8/valo=7,832.99 2006.281.08:03:10.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.08:03:10.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.08:03:10.97#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:10.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:03:10.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:03:10.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:03:10.97#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:03:10.97#ibcon#first serial, iclass 22, count 0 2006.281.08:03:10.97#ibcon#enter sib2, iclass 22, count 0 2006.281.08:03:10.97#ibcon#flushed, iclass 22, count 0 2006.281.08:03:10.97#ibcon#about to write, iclass 22, count 0 2006.281.08:03:10.97#ibcon#wrote, iclass 22, count 0 2006.281.08:03:10.97#ibcon#about to read 3, iclass 22, count 0 2006.281.08:03:10.99#ibcon#read 3, iclass 22, count 0 2006.281.08:03:10.99#ibcon#about to read 4, iclass 22, count 0 2006.281.08:03:10.99#ibcon#read 4, iclass 22, count 0 2006.281.08:03:10.99#ibcon#about to read 5, iclass 22, count 0 2006.281.08:03:10.99#ibcon#read 5, iclass 22, count 0 2006.281.08:03:10.99#ibcon#about to read 6, iclass 22, count 0 2006.281.08:03:10.99#ibcon#read 6, iclass 22, count 0 2006.281.08:03:10.99#ibcon#end of sib2, iclass 22, count 0 2006.281.08:03:10.99#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:03:10.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:03:10.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:03:10.99#ibcon#*before write, iclass 22, count 0 2006.281.08:03:10.99#ibcon#enter sib2, iclass 22, count 0 2006.281.08:03:10.99#ibcon#flushed, iclass 22, count 0 2006.281.08:03:10.99#ibcon#about to write, iclass 22, count 0 2006.281.08:03:10.99#ibcon#wrote, iclass 22, count 0 2006.281.08:03:10.99#ibcon#about to read 3, iclass 22, count 0 2006.281.08:03:11.04#ibcon#read 3, iclass 22, count 0 2006.281.08:03:11.04#ibcon#about to read 4, iclass 22, count 0 2006.281.08:03:11.04#ibcon#read 4, iclass 22, count 0 2006.281.08:03:11.04#ibcon#about to read 5, iclass 22, count 0 2006.281.08:03:11.04#ibcon#read 5, iclass 22, count 0 2006.281.08:03:11.04#ibcon#about to read 6, iclass 22, count 0 2006.281.08:03:11.04#ibcon#read 6, iclass 22, count 0 2006.281.08:03:11.04#ibcon#end of sib2, iclass 22, count 0 2006.281.08:03:11.04#ibcon#*after write, iclass 22, count 0 2006.281.08:03:11.04#ibcon#*before return 0, iclass 22, count 0 2006.281.08:03:11.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:03:11.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:03:11.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:03:11.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:03:11.04$vc4f8/va=7,6 2006.281.08:03:11.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.08:03:11.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.08:03:11.04#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:11.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:03:11.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:03:11.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:03:11.09#ibcon#enter wrdev, iclass 24, count 2 2006.281.08:03:11.09#ibcon#first serial, iclass 24, count 2 2006.281.08:03:11.09#ibcon#enter sib2, iclass 24, count 2 2006.281.08:03:11.09#ibcon#flushed, iclass 24, count 2 2006.281.08:03:11.09#ibcon#about to write, iclass 24, count 2 2006.281.08:03:11.09#ibcon#wrote, iclass 24, count 2 2006.281.08:03:11.09#ibcon#about to read 3, iclass 24, count 2 2006.281.08:03:11.11#ibcon#read 3, iclass 24, count 2 2006.281.08:03:11.11#ibcon#about to read 4, iclass 24, count 2 2006.281.08:03:11.11#ibcon#read 4, iclass 24, count 2 2006.281.08:03:11.11#ibcon#about to read 5, iclass 24, count 2 2006.281.08:03:11.11#ibcon#read 5, iclass 24, count 2 2006.281.08:03:11.11#ibcon#about to read 6, iclass 24, count 2 2006.281.08:03:11.11#ibcon#read 6, iclass 24, count 2 2006.281.08:03:11.11#ibcon#end of sib2, iclass 24, count 2 2006.281.08:03:11.11#ibcon#*mode == 0, iclass 24, count 2 2006.281.08:03:11.11#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.08:03:11.11#ibcon#[25=AT07-06\r\n] 2006.281.08:03:11.11#ibcon#*before write, iclass 24, count 2 2006.281.08:03:11.11#ibcon#enter sib2, iclass 24, count 2 2006.281.08:03:11.11#ibcon#flushed, iclass 24, count 2 2006.281.08:03:11.11#ibcon#about to write, iclass 24, count 2 2006.281.08:03:11.11#ibcon#wrote, iclass 24, count 2 2006.281.08:03:11.11#ibcon#about to read 3, iclass 24, count 2 2006.281.08:03:11.14#ibcon#read 3, iclass 24, count 2 2006.281.08:03:11.14#ibcon#about to read 4, iclass 24, count 2 2006.281.08:03:11.14#ibcon#read 4, iclass 24, count 2 2006.281.08:03:11.14#ibcon#about to read 5, iclass 24, count 2 2006.281.08:03:11.14#ibcon#read 5, iclass 24, count 2 2006.281.08:03:11.14#ibcon#about to read 6, iclass 24, count 2 2006.281.08:03:11.14#ibcon#read 6, iclass 24, count 2 2006.281.08:03:11.14#ibcon#end of sib2, iclass 24, count 2 2006.281.08:03:11.14#ibcon#*after write, iclass 24, count 2 2006.281.08:03:11.14#ibcon#*before return 0, iclass 24, count 2 2006.281.08:03:11.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:03:11.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:03:11.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.08:03:11.14#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:11.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:03:11.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:03:11.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:03:11.26#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:03:11.26#ibcon#first serial, iclass 24, count 0 2006.281.08:03:11.26#ibcon#enter sib2, iclass 24, count 0 2006.281.08:03:11.26#ibcon#flushed, iclass 24, count 0 2006.281.08:03:11.26#ibcon#about to write, iclass 24, count 0 2006.281.08:03:11.26#ibcon#wrote, iclass 24, count 0 2006.281.08:03:11.26#ibcon#about to read 3, iclass 24, count 0 2006.281.08:03:11.28#ibcon#read 3, iclass 24, count 0 2006.281.08:03:11.28#ibcon#about to read 4, iclass 24, count 0 2006.281.08:03:11.28#ibcon#read 4, iclass 24, count 0 2006.281.08:03:11.28#ibcon#about to read 5, iclass 24, count 0 2006.281.08:03:11.28#ibcon#read 5, iclass 24, count 0 2006.281.08:03:11.28#ibcon#about to read 6, iclass 24, count 0 2006.281.08:03:11.28#ibcon#read 6, iclass 24, count 0 2006.281.08:03:11.28#ibcon#end of sib2, iclass 24, count 0 2006.281.08:03:11.28#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:03:11.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:03:11.28#ibcon#[25=USB\r\n] 2006.281.08:03:11.28#ibcon#*before write, iclass 24, count 0 2006.281.08:03:11.28#ibcon#enter sib2, iclass 24, count 0 2006.281.08:03:11.28#ibcon#flushed, iclass 24, count 0 2006.281.08:03:11.28#ibcon#about to write, iclass 24, count 0 2006.281.08:03:11.28#ibcon#wrote, iclass 24, count 0 2006.281.08:03:11.28#ibcon#about to read 3, iclass 24, count 0 2006.281.08:03:11.31#ibcon#read 3, iclass 24, count 0 2006.281.08:03:11.31#ibcon#about to read 4, iclass 24, count 0 2006.281.08:03:11.31#ibcon#read 4, iclass 24, count 0 2006.281.08:03:11.31#ibcon#about to read 5, iclass 24, count 0 2006.281.08:03:11.31#ibcon#read 5, iclass 24, count 0 2006.281.08:03:11.31#ibcon#about to read 6, iclass 24, count 0 2006.281.08:03:11.31#ibcon#read 6, iclass 24, count 0 2006.281.08:03:11.31#ibcon#end of sib2, iclass 24, count 0 2006.281.08:03:11.31#ibcon#*after write, iclass 24, count 0 2006.281.08:03:11.31#ibcon#*before return 0, iclass 24, count 0 2006.281.08:03:11.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:03:11.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:03:11.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:03:11.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:03:11.31$vc4f8/valo=8,852.99 2006.281.08:03:11.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.08:03:11.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.08:03:11.31#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:11.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:03:11.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:03:11.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:03:11.31#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:03:11.31#ibcon#first serial, iclass 26, count 0 2006.281.08:03:11.31#ibcon#enter sib2, iclass 26, count 0 2006.281.08:03:11.31#ibcon#flushed, iclass 26, count 0 2006.281.08:03:11.31#ibcon#about to write, iclass 26, count 0 2006.281.08:03:11.31#ibcon#wrote, iclass 26, count 0 2006.281.08:03:11.31#ibcon#about to read 3, iclass 26, count 0 2006.281.08:03:11.33#ibcon#read 3, iclass 26, count 0 2006.281.08:03:11.33#ibcon#about to read 4, iclass 26, count 0 2006.281.08:03:11.33#ibcon#read 4, iclass 26, count 0 2006.281.08:03:11.33#ibcon#about to read 5, iclass 26, count 0 2006.281.08:03:11.33#ibcon#read 5, iclass 26, count 0 2006.281.08:03:11.33#ibcon#about to read 6, iclass 26, count 0 2006.281.08:03:11.33#ibcon#read 6, iclass 26, count 0 2006.281.08:03:11.33#ibcon#end of sib2, iclass 26, count 0 2006.281.08:03:11.33#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:03:11.33#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:03:11.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:03:11.33#ibcon#*before write, iclass 26, count 0 2006.281.08:03:11.33#ibcon#enter sib2, iclass 26, count 0 2006.281.08:03:11.33#ibcon#flushed, iclass 26, count 0 2006.281.08:03:11.33#ibcon#about to write, iclass 26, count 0 2006.281.08:03:11.33#ibcon#wrote, iclass 26, count 0 2006.281.08:03:11.33#ibcon#about to read 3, iclass 26, count 0 2006.281.08:03:11.37#ibcon#read 3, iclass 26, count 0 2006.281.08:03:11.37#ibcon#about to read 4, iclass 26, count 0 2006.281.08:03:11.37#ibcon#read 4, iclass 26, count 0 2006.281.08:03:11.37#ibcon#about to read 5, iclass 26, count 0 2006.281.08:03:11.37#ibcon#read 5, iclass 26, count 0 2006.281.08:03:11.37#ibcon#about to read 6, iclass 26, count 0 2006.281.08:03:11.37#ibcon#read 6, iclass 26, count 0 2006.281.08:03:11.37#ibcon#end of sib2, iclass 26, count 0 2006.281.08:03:11.37#ibcon#*after write, iclass 26, count 0 2006.281.08:03:11.37#ibcon#*before return 0, iclass 26, count 0 2006.281.08:03:11.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:03:11.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:03:11.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:03:11.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:03:11.37$vc4f8/va=8,6 2006.281.08:03:11.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.08:03:11.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.08:03:11.37#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:11.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:03:11.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:03:11.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:03:11.43#ibcon#enter wrdev, iclass 28, count 2 2006.281.08:03:11.43#ibcon#first serial, iclass 28, count 2 2006.281.08:03:11.43#ibcon#enter sib2, iclass 28, count 2 2006.281.08:03:11.43#ibcon#flushed, iclass 28, count 2 2006.281.08:03:11.43#ibcon#about to write, iclass 28, count 2 2006.281.08:03:11.43#ibcon#wrote, iclass 28, count 2 2006.281.08:03:11.43#ibcon#about to read 3, iclass 28, count 2 2006.281.08:03:11.45#ibcon#read 3, iclass 28, count 2 2006.281.08:03:11.45#ibcon#about to read 4, iclass 28, count 2 2006.281.08:03:11.45#ibcon#read 4, iclass 28, count 2 2006.281.08:03:11.45#ibcon#about to read 5, iclass 28, count 2 2006.281.08:03:11.45#ibcon#read 5, iclass 28, count 2 2006.281.08:03:11.45#ibcon#about to read 6, iclass 28, count 2 2006.281.08:03:11.45#ibcon#read 6, iclass 28, count 2 2006.281.08:03:11.45#ibcon#end of sib2, iclass 28, count 2 2006.281.08:03:11.45#ibcon#*mode == 0, iclass 28, count 2 2006.281.08:03:11.45#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.08:03:11.45#ibcon#[25=AT08-06\r\n] 2006.281.08:03:11.45#ibcon#*before write, iclass 28, count 2 2006.281.08:03:11.45#ibcon#enter sib2, iclass 28, count 2 2006.281.08:03:11.45#ibcon#flushed, iclass 28, count 2 2006.281.08:03:11.45#ibcon#about to write, iclass 28, count 2 2006.281.08:03:11.45#ibcon#wrote, iclass 28, count 2 2006.281.08:03:11.45#ibcon#about to read 3, iclass 28, count 2 2006.281.08:03:11.48#ibcon#read 3, iclass 28, count 2 2006.281.08:03:11.48#ibcon#about to read 4, iclass 28, count 2 2006.281.08:03:11.48#ibcon#read 4, iclass 28, count 2 2006.281.08:03:11.48#ibcon#about to read 5, iclass 28, count 2 2006.281.08:03:11.48#ibcon#read 5, iclass 28, count 2 2006.281.08:03:11.48#ibcon#about to read 6, iclass 28, count 2 2006.281.08:03:11.48#ibcon#read 6, iclass 28, count 2 2006.281.08:03:11.48#ibcon#end of sib2, iclass 28, count 2 2006.281.08:03:11.48#ibcon#*after write, iclass 28, count 2 2006.281.08:03:11.48#ibcon#*before return 0, iclass 28, count 2 2006.281.08:03:11.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:03:11.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:03:11.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.08:03:11.48#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:11.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:03:11.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:03:11.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:03:11.60#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:03:11.60#ibcon#first serial, iclass 28, count 0 2006.281.08:03:11.60#ibcon#enter sib2, iclass 28, count 0 2006.281.08:03:11.60#ibcon#flushed, iclass 28, count 0 2006.281.08:03:11.60#ibcon#about to write, iclass 28, count 0 2006.281.08:03:11.60#ibcon#wrote, iclass 28, count 0 2006.281.08:03:11.60#ibcon#about to read 3, iclass 28, count 0 2006.281.08:03:11.62#ibcon#read 3, iclass 28, count 0 2006.281.08:03:11.62#ibcon#about to read 4, iclass 28, count 0 2006.281.08:03:11.62#ibcon#read 4, iclass 28, count 0 2006.281.08:03:11.62#ibcon#about to read 5, iclass 28, count 0 2006.281.08:03:11.62#ibcon#read 5, iclass 28, count 0 2006.281.08:03:11.62#ibcon#about to read 6, iclass 28, count 0 2006.281.08:03:11.62#ibcon#read 6, iclass 28, count 0 2006.281.08:03:11.62#ibcon#end of sib2, iclass 28, count 0 2006.281.08:03:11.62#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:03:11.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:03:11.62#ibcon#[25=USB\r\n] 2006.281.08:03:11.62#ibcon#*before write, iclass 28, count 0 2006.281.08:03:11.62#ibcon#enter sib2, iclass 28, count 0 2006.281.08:03:11.62#ibcon#flushed, iclass 28, count 0 2006.281.08:03:11.62#ibcon#about to write, iclass 28, count 0 2006.281.08:03:11.62#ibcon#wrote, iclass 28, count 0 2006.281.08:03:11.62#ibcon#about to read 3, iclass 28, count 0 2006.281.08:03:11.65#ibcon#read 3, iclass 28, count 0 2006.281.08:03:11.65#ibcon#about to read 4, iclass 28, count 0 2006.281.08:03:11.65#ibcon#read 4, iclass 28, count 0 2006.281.08:03:11.65#ibcon#about to read 5, iclass 28, count 0 2006.281.08:03:11.65#ibcon#read 5, iclass 28, count 0 2006.281.08:03:11.65#ibcon#about to read 6, iclass 28, count 0 2006.281.08:03:11.65#ibcon#read 6, iclass 28, count 0 2006.281.08:03:11.65#ibcon#end of sib2, iclass 28, count 0 2006.281.08:03:11.65#ibcon#*after write, iclass 28, count 0 2006.281.08:03:11.65#ibcon#*before return 0, iclass 28, count 0 2006.281.08:03:11.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:03:11.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:03:11.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:03:11.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:03:11.65$vc4f8/vblo=1,632.99 2006.281.08:03:11.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.08:03:11.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.08:03:11.65#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:11.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:03:11.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:03:11.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:03:11.65#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:03:11.65#ibcon#first serial, iclass 30, count 0 2006.281.08:03:11.65#ibcon#enter sib2, iclass 30, count 0 2006.281.08:03:11.65#ibcon#flushed, iclass 30, count 0 2006.281.08:03:11.65#ibcon#about to write, iclass 30, count 0 2006.281.08:03:11.65#ibcon#wrote, iclass 30, count 0 2006.281.08:03:11.65#ibcon#about to read 3, iclass 30, count 0 2006.281.08:03:11.67#ibcon#read 3, iclass 30, count 0 2006.281.08:03:11.67#ibcon#about to read 4, iclass 30, count 0 2006.281.08:03:11.67#ibcon#read 4, iclass 30, count 0 2006.281.08:03:11.67#ibcon#about to read 5, iclass 30, count 0 2006.281.08:03:11.67#ibcon#read 5, iclass 30, count 0 2006.281.08:03:11.67#ibcon#about to read 6, iclass 30, count 0 2006.281.08:03:11.67#ibcon#read 6, iclass 30, count 0 2006.281.08:03:11.67#ibcon#end of sib2, iclass 30, count 0 2006.281.08:03:11.67#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:03:11.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:03:11.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:03:11.67#ibcon#*before write, iclass 30, count 0 2006.281.08:03:11.67#ibcon#enter sib2, iclass 30, count 0 2006.281.08:03:11.67#ibcon#flushed, iclass 30, count 0 2006.281.08:03:11.67#ibcon#about to write, iclass 30, count 0 2006.281.08:03:11.69#ibcon#wrote, iclass 30, count 0 2006.281.08:03:11.69#ibcon#about to read 3, iclass 30, count 0 2006.281.08:03:11.73#ibcon#read 3, iclass 30, count 0 2006.281.08:03:11.73#ibcon#about to read 4, iclass 30, count 0 2006.281.08:03:11.73#ibcon#read 4, iclass 30, count 0 2006.281.08:03:11.73#ibcon#about to read 5, iclass 30, count 0 2006.281.08:03:11.73#ibcon#read 5, iclass 30, count 0 2006.281.08:03:11.73#ibcon#about to read 6, iclass 30, count 0 2006.281.08:03:11.73#ibcon#read 6, iclass 30, count 0 2006.281.08:03:11.73#ibcon#end of sib2, iclass 30, count 0 2006.281.08:03:11.73#ibcon#*after write, iclass 30, count 0 2006.281.08:03:11.73#ibcon#*before return 0, iclass 30, count 0 2006.281.08:03:11.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:03:11.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:03:11.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:03:11.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:03:11.73$vc4f8/vb=1,4 2006.281.08:03:11.73#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.08:03:11.73#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.08:03:11.73#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:11.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:03:11.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:03:11.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:03:11.73#ibcon#enter wrdev, iclass 32, count 2 2006.281.08:03:11.73#ibcon#first serial, iclass 32, count 2 2006.281.08:03:11.73#ibcon#enter sib2, iclass 32, count 2 2006.281.08:03:11.73#ibcon#flushed, iclass 32, count 2 2006.281.08:03:11.73#ibcon#about to write, iclass 32, count 2 2006.281.08:03:11.73#ibcon#wrote, iclass 32, count 2 2006.281.08:03:11.73#ibcon#about to read 3, iclass 32, count 2 2006.281.08:03:11.75#ibcon#read 3, iclass 32, count 2 2006.281.08:03:11.75#ibcon#about to read 4, iclass 32, count 2 2006.281.08:03:11.75#ibcon#read 4, iclass 32, count 2 2006.281.08:03:11.75#ibcon#about to read 5, iclass 32, count 2 2006.281.08:03:11.75#ibcon#read 5, iclass 32, count 2 2006.281.08:03:11.75#ibcon#about to read 6, iclass 32, count 2 2006.281.08:03:11.75#ibcon#read 6, iclass 32, count 2 2006.281.08:03:11.75#ibcon#end of sib2, iclass 32, count 2 2006.281.08:03:11.75#ibcon#*mode == 0, iclass 32, count 2 2006.281.08:03:11.75#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.08:03:11.75#ibcon#[27=AT01-04\r\n] 2006.281.08:03:11.75#ibcon#*before write, iclass 32, count 2 2006.281.08:03:11.75#ibcon#enter sib2, iclass 32, count 2 2006.281.08:03:11.75#ibcon#flushed, iclass 32, count 2 2006.281.08:03:11.75#ibcon#about to write, iclass 32, count 2 2006.281.08:03:11.75#ibcon#wrote, iclass 32, count 2 2006.281.08:03:11.75#ibcon#about to read 3, iclass 32, count 2 2006.281.08:03:11.79#ibcon#read 3, iclass 32, count 2 2006.281.08:03:11.79#ibcon#about to read 4, iclass 32, count 2 2006.281.08:03:11.79#ibcon#read 4, iclass 32, count 2 2006.281.08:03:11.79#ibcon#about to read 5, iclass 32, count 2 2006.281.08:03:11.79#ibcon#read 5, iclass 32, count 2 2006.281.08:03:11.79#ibcon#about to read 6, iclass 32, count 2 2006.281.08:03:11.79#ibcon#read 6, iclass 32, count 2 2006.281.08:03:11.79#ibcon#end of sib2, iclass 32, count 2 2006.281.08:03:11.79#ibcon#*after write, iclass 32, count 2 2006.281.08:03:11.79#ibcon#*before return 0, iclass 32, count 2 2006.281.08:03:11.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:03:11.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:03:11.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.08:03:11.79#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:11.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:03:11.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:03:11.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:03:11.91#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:03:11.91#ibcon#first serial, iclass 32, count 0 2006.281.08:03:11.91#ibcon#enter sib2, iclass 32, count 0 2006.281.08:03:11.91#ibcon#flushed, iclass 32, count 0 2006.281.08:03:11.91#ibcon#about to write, iclass 32, count 0 2006.281.08:03:11.91#ibcon#wrote, iclass 32, count 0 2006.281.08:03:11.91#ibcon#about to read 3, iclass 32, count 0 2006.281.08:03:11.93#ibcon#read 3, iclass 32, count 0 2006.281.08:03:11.93#ibcon#about to read 4, iclass 32, count 0 2006.281.08:03:11.93#ibcon#read 4, iclass 32, count 0 2006.281.08:03:11.93#ibcon#about to read 5, iclass 32, count 0 2006.281.08:03:11.93#ibcon#read 5, iclass 32, count 0 2006.281.08:03:11.93#ibcon#about to read 6, iclass 32, count 0 2006.281.08:03:11.93#ibcon#read 6, iclass 32, count 0 2006.281.08:03:11.93#ibcon#end of sib2, iclass 32, count 0 2006.281.08:03:11.93#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:03:11.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:03:11.93#ibcon#[27=USB\r\n] 2006.281.08:03:11.93#ibcon#*before write, iclass 32, count 0 2006.281.08:03:11.93#ibcon#enter sib2, iclass 32, count 0 2006.281.08:03:11.93#ibcon#flushed, iclass 32, count 0 2006.281.08:03:11.93#ibcon#about to write, iclass 32, count 0 2006.281.08:03:11.93#ibcon#wrote, iclass 32, count 0 2006.281.08:03:11.93#ibcon#about to read 3, iclass 32, count 0 2006.281.08:03:11.96#ibcon#read 3, iclass 32, count 0 2006.281.08:03:11.96#ibcon#about to read 4, iclass 32, count 0 2006.281.08:03:11.96#ibcon#read 4, iclass 32, count 0 2006.281.08:03:11.96#ibcon#about to read 5, iclass 32, count 0 2006.281.08:03:11.96#ibcon#read 5, iclass 32, count 0 2006.281.08:03:11.96#ibcon#about to read 6, iclass 32, count 0 2006.281.08:03:11.96#ibcon#read 6, iclass 32, count 0 2006.281.08:03:11.96#ibcon#end of sib2, iclass 32, count 0 2006.281.08:03:11.96#ibcon#*after write, iclass 32, count 0 2006.281.08:03:11.96#ibcon#*before return 0, iclass 32, count 0 2006.281.08:03:11.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:03:11.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:03:11.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:03:11.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:03:11.96$vc4f8/vblo=2,640.99 2006.281.08:03:11.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.08:03:11.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.08:03:11.96#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:11.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:11.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:11.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:11.96#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:03:11.96#ibcon#first serial, iclass 34, count 0 2006.281.08:03:11.96#ibcon#enter sib2, iclass 34, count 0 2006.281.08:03:11.96#ibcon#flushed, iclass 34, count 0 2006.281.08:03:11.96#ibcon#about to write, iclass 34, count 0 2006.281.08:03:11.96#ibcon#wrote, iclass 34, count 0 2006.281.08:03:11.96#ibcon#about to read 3, iclass 34, count 0 2006.281.08:03:11.98#ibcon#read 3, iclass 34, count 0 2006.281.08:03:11.98#ibcon#about to read 4, iclass 34, count 0 2006.281.08:03:11.98#ibcon#read 4, iclass 34, count 0 2006.281.08:03:11.98#ibcon#about to read 5, iclass 34, count 0 2006.281.08:03:11.98#ibcon#read 5, iclass 34, count 0 2006.281.08:03:11.98#ibcon#about to read 6, iclass 34, count 0 2006.281.08:03:11.98#ibcon#read 6, iclass 34, count 0 2006.281.08:03:11.98#ibcon#end of sib2, iclass 34, count 0 2006.281.08:03:11.98#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:03:11.98#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:03:11.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:03:11.98#ibcon#*before write, iclass 34, count 0 2006.281.08:03:11.98#ibcon#enter sib2, iclass 34, count 0 2006.281.08:03:11.98#ibcon#flushed, iclass 34, count 0 2006.281.08:03:11.98#ibcon#about to write, iclass 34, count 0 2006.281.08:03:11.98#ibcon#wrote, iclass 34, count 0 2006.281.08:03:11.98#ibcon#about to read 3, iclass 34, count 0 2006.281.08:03:12.03#ibcon#read 3, iclass 34, count 0 2006.281.08:03:12.03#ibcon#about to read 4, iclass 34, count 0 2006.281.08:03:12.03#ibcon#read 4, iclass 34, count 0 2006.281.08:03:12.03#ibcon#about to read 5, iclass 34, count 0 2006.281.08:03:12.03#ibcon#read 5, iclass 34, count 0 2006.281.08:03:12.03#ibcon#about to read 6, iclass 34, count 0 2006.281.08:03:12.03#ibcon#read 6, iclass 34, count 0 2006.281.08:03:12.03#ibcon#end of sib2, iclass 34, count 0 2006.281.08:03:12.03#ibcon#*after write, iclass 34, count 0 2006.281.08:03:12.03#ibcon#*before return 0, iclass 34, count 0 2006.281.08:03:12.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:12.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:03:12.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:03:12.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:03:12.03$vc4f8/vb=2,5 2006.281.08:03:12.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.08:03:12.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.08:03:12.03#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:12.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:12.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:12.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:12.08#ibcon#enter wrdev, iclass 36, count 2 2006.281.08:03:12.08#ibcon#first serial, iclass 36, count 2 2006.281.08:03:12.08#ibcon#enter sib2, iclass 36, count 2 2006.281.08:03:12.08#ibcon#flushed, iclass 36, count 2 2006.281.08:03:12.08#ibcon#about to write, iclass 36, count 2 2006.281.08:03:12.08#ibcon#wrote, iclass 36, count 2 2006.281.08:03:12.08#ibcon#about to read 3, iclass 36, count 2 2006.281.08:03:12.10#ibcon#read 3, iclass 36, count 2 2006.281.08:03:12.10#ibcon#about to read 4, iclass 36, count 2 2006.281.08:03:12.10#ibcon#read 4, iclass 36, count 2 2006.281.08:03:12.10#ibcon#about to read 5, iclass 36, count 2 2006.281.08:03:12.10#ibcon#read 5, iclass 36, count 2 2006.281.08:03:12.10#ibcon#about to read 6, iclass 36, count 2 2006.281.08:03:12.10#ibcon#read 6, iclass 36, count 2 2006.281.08:03:12.10#ibcon#end of sib2, iclass 36, count 2 2006.281.08:03:12.10#ibcon#*mode == 0, iclass 36, count 2 2006.281.08:03:12.10#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.08:03:12.10#ibcon#[27=AT02-05\r\n] 2006.281.08:03:12.10#ibcon#*before write, iclass 36, count 2 2006.281.08:03:12.10#ibcon#enter sib2, iclass 36, count 2 2006.281.08:03:12.10#ibcon#flushed, iclass 36, count 2 2006.281.08:03:12.10#ibcon#about to write, iclass 36, count 2 2006.281.08:03:12.10#ibcon#wrote, iclass 36, count 2 2006.281.08:03:12.10#ibcon#about to read 3, iclass 36, count 2 2006.281.08:03:12.13#ibcon#read 3, iclass 36, count 2 2006.281.08:03:12.13#ibcon#about to read 4, iclass 36, count 2 2006.281.08:03:12.13#ibcon#read 4, iclass 36, count 2 2006.281.08:03:12.13#ibcon#about to read 5, iclass 36, count 2 2006.281.08:03:12.13#ibcon#read 5, iclass 36, count 2 2006.281.08:03:12.13#ibcon#about to read 6, iclass 36, count 2 2006.281.08:03:12.13#ibcon#read 6, iclass 36, count 2 2006.281.08:03:12.13#ibcon#end of sib2, iclass 36, count 2 2006.281.08:03:12.13#ibcon#*after write, iclass 36, count 2 2006.281.08:03:12.13#ibcon#*before return 0, iclass 36, count 2 2006.281.08:03:12.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:12.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:03:12.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.08:03:12.13#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:12.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:12.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:12.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:12.25#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:03:12.25#ibcon#first serial, iclass 36, count 0 2006.281.08:03:12.25#ibcon#enter sib2, iclass 36, count 0 2006.281.08:03:12.25#ibcon#flushed, iclass 36, count 0 2006.281.08:03:12.25#ibcon#about to write, iclass 36, count 0 2006.281.08:03:12.25#ibcon#wrote, iclass 36, count 0 2006.281.08:03:12.25#ibcon#about to read 3, iclass 36, count 0 2006.281.08:03:12.27#ibcon#read 3, iclass 36, count 0 2006.281.08:03:12.27#ibcon#about to read 4, iclass 36, count 0 2006.281.08:03:12.27#ibcon#read 4, iclass 36, count 0 2006.281.08:03:12.27#ibcon#about to read 5, iclass 36, count 0 2006.281.08:03:12.27#ibcon#read 5, iclass 36, count 0 2006.281.08:03:12.27#ibcon#about to read 6, iclass 36, count 0 2006.281.08:03:12.27#ibcon#read 6, iclass 36, count 0 2006.281.08:03:12.27#ibcon#end of sib2, iclass 36, count 0 2006.281.08:03:12.27#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:03:12.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:03:12.27#ibcon#[27=USB\r\n] 2006.281.08:03:12.27#ibcon#*before write, iclass 36, count 0 2006.281.08:03:12.27#ibcon#enter sib2, iclass 36, count 0 2006.281.08:03:12.27#ibcon#flushed, iclass 36, count 0 2006.281.08:03:12.27#ibcon#about to write, iclass 36, count 0 2006.281.08:03:12.27#ibcon#wrote, iclass 36, count 0 2006.281.08:03:12.27#ibcon#about to read 3, iclass 36, count 0 2006.281.08:03:12.30#ibcon#read 3, iclass 36, count 0 2006.281.08:03:12.30#ibcon#about to read 4, iclass 36, count 0 2006.281.08:03:12.30#ibcon#read 4, iclass 36, count 0 2006.281.08:03:12.30#ibcon#about to read 5, iclass 36, count 0 2006.281.08:03:12.30#ibcon#read 5, iclass 36, count 0 2006.281.08:03:12.30#ibcon#about to read 6, iclass 36, count 0 2006.281.08:03:12.30#ibcon#read 6, iclass 36, count 0 2006.281.08:03:12.30#ibcon#end of sib2, iclass 36, count 0 2006.281.08:03:12.30#ibcon#*after write, iclass 36, count 0 2006.281.08:03:12.30#ibcon#*before return 0, iclass 36, count 0 2006.281.08:03:12.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:12.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:03:12.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:03:12.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:03:12.30$vc4f8/vblo=3,656.99 2006.281.08:03:12.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:03:12.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:03:12.30#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:12.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:12.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:12.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:12.30#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:03:12.30#ibcon#first serial, iclass 38, count 0 2006.281.08:03:12.30#ibcon#enter sib2, iclass 38, count 0 2006.281.08:03:12.30#ibcon#flushed, iclass 38, count 0 2006.281.08:03:12.30#ibcon#about to write, iclass 38, count 0 2006.281.08:03:12.30#ibcon#wrote, iclass 38, count 0 2006.281.08:03:12.30#ibcon#about to read 3, iclass 38, count 0 2006.281.08:03:12.32#ibcon#read 3, iclass 38, count 0 2006.281.08:03:12.33#ibcon#about to read 4, iclass 38, count 0 2006.281.08:03:12.33#ibcon#read 4, iclass 38, count 0 2006.281.08:03:12.33#ibcon#about to read 5, iclass 38, count 0 2006.281.08:03:12.33#ibcon#read 5, iclass 38, count 0 2006.281.08:03:12.33#ibcon#about to read 6, iclass 38, count 0 2006.281.08:03:12.33#ibcon#read 6, iclass 38, count 0 2006.281.08:03:12.33#ibcon#end of sib2, iclass 38, count 0 2006.281.08:03:12.33#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:03:12.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:03:12.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:03:12.33#ibcon#*before write, iclass 38, count 0 2006.281.08:03:12.33#ibcon#enter sib2, iclass 38, count 0 2006.281.08:03:12.33#ibcon#flushed, iclass 38, count 0 2006.281.08:03:12.33#ibcon#about to write, iclass 38, count 0 2006.281.08:03:12.33#ibcon#wrote, iclass 38, count 0 2006.281.08:03:12.33#ibcon#about to read 3, iclass 38, count 0 2006.281.08:03:12.37#ibcon#read 3, iclass 38, count 0 2006.281.08:03:12.37#ibcon#about to read 4, iclass 38, count 0 2006.281.08:03:12.37#ibcon#read 4, iclass 38, count 0 2006.281.08:03:12.37#ibcon#about to read 5, iclass 38, count 0 2006.281.08:03:12.37#ibcon#read 5, iclass 38, count 0 2006.281.08:03:12.37#ibcon#about to read 6, iclass 38, count 0 2006.281.08:03:12.37#ibcon#read 6, iclass 38, count 0 2006.281.08:03:12.37#ibcon#end of sib2, iclass 38, count 0 2006.281.08:03:12.37#ibcon#*after write, iclass 38, count 0 2006.281.08:03:12.37#ibcon#*before return 0, iclass 38, count 0 2006.281.08:03:12.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:12.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:03:12.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:03:12.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:03:12.37$vc4f8/vb=3,4 2006.281.08:03:12.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:03:12.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:03:12.37#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:12.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:12.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:12.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:12.42#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:03:12.42#ibcon#first serial, iclass 40, count 2 2006.281.08:03:12.42#ibcon#enter sib2, iclass 40, count 2 2006.281.08:03:12.42#ibcon#flushed, iclass 40, count 2 2006.281.08:03:12.42#ibcon#about to write, iclass 40, count 2 2006.281.08:03:12.42#ibcon#wrote, iclass 40, count 2 2006.281.08:03:12.42#ibcon#about to read 3, iclass 40, count 2 2006.281.08:03:12.44#ibcon#read 3, iclass 40, count 2 2006.281.08:03:12.44#ibcon#about to read 4, iclass 40, count 2 2006.281.08:03:12.44#ibcon#read 4, iclass 40, count 2 2006.281.08:03:12.44#ibcon#about to read 5, iclass 40, count 2 2006.281.08:03:12.44#ibcon#read 5, iclass 40, count 2 2006.281.08:03:12.44#ibcon#about to read 6, iclass 40, count 2 2006.281.08:03:12.44#ibcon#read 6, iclass 40, count 2 2006.281.08:03:12.44#ibcon#end of sib2, iclass 40, count 2 2006.281.08:03:12.44#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:03:12.44#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:03:12.44#ibcon#[27=AT03-04\r\n] 2006.281.08:03:12.44#ibcon#*before write, iclass 40, count 2 2006.281.08:03:12.44#ibcon#enter sib2, iclass 40, count 2 2006.281.08:03:12.44#ibcon#flushed, iclass 40, count 2 2006.281.08:03:12.44#ibcon#about to write, iclass 40, count 2 2006.281.08:03:12.44#ibcon#wrote, iclass 40, count 2 2006.281.08:03:12.44#ibcon#about to read 3, iclass 40, count 2 2006.281.08:03:12.47#ibcon#read 3, iclass 40, count 2 2006.281.08:03:12.47#ibcon#about to read 4, iclass 40, count 2 2006.281.08:03:12.47#ibcon#read 4, iclass 40, count 2 2006.281.08:03:12.47#ibcon#about to read 5, iclass 40, count 2 2006.281.08:03:12.47#ibcon#read 5, iclass 40, count 2 2006.281.08:03:12.47#ibcon#about to read 6, iclass 40, count 2 2006.281.08:03:12.47#ibcon#read 6, iclass 40, count 2 2006.281.08:03:12.47#ibcon#end of sib2, iclass 40, count 2 2006.281.08:03:12.47#ibcon#*after write, iclass 40, count 2 2006.281.08:03:12.47#ibcon#*before return 0, iclass 40, count 2 2006.281.08:03:12.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:12.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:03:12.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:03:12.47#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:12.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:12.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:12.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:12.59#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:03:12.59#ibcon#first serial, iclass 40, count 0 2006.281.08:03:12.59#ibcon#enter sib2, iclass 40, count 0 2006.281.08:03:12.59#ibcon#flushed, iclass 40, count 0 2006.281.08:03:12.59#ibcon#about to write, iclass 40, count 0 2006.281.08:03:12.59#ibcon#wrote, iclass 40, count 0 2006.281.08:03:12.59#ibcon#about to read 3, iclass 40, count 0 2006.281.08:03:12.61#ibcon#read 3, iclass 40, count 0 2006.281.08:03:12.61#ibcon#about to read 4, iclass 40, count 0 2006.281.08:03:12.61#ibcon#read 4, iclass 40, count 0 2006.281.08:03:12.61#ibcon#about to read 5, iclass 40, count 0 2006.281.08:03:12.61#ibcon#read 5, iclass 40, count 0 2006.281.08:03:12.61#ibcon#about to read 6, iclass 40, count 0 2006.281.08:03:12.61#ibcon#read 6, iclass 40, count 0 2006.281.08:03:12.61#ibcon#end of sib2, iclass 40, count 0 2006.281.08:03:12.61#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:03:12.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:03:12.61#ibcon#[27=USB\r\n] 2006.281.08:03:12.61#ibcon#*before write, iclass 40, count 0 2006.281.08:03:12.61#ibcon#enter sib2, iclass 40, count 0 2006.281.08:03:12.61#ibcon#flushed, iclass 40, count 0 2006.281.08:03:12.61#ibcon#about to write, iclass 40, count 0 2006.281.08:03:12.61#ibcon#wrote, iclass 40, count 0 2006.281.08:03:12.61#ibcon#about to read 3, iclass 40, count 0 2006.281.08:03:12.64#ibcon#read 3, iclass 40, count 0 2006.281.08:03:12.64#ibcon#about to read 4, iclass 40, count 0 2006.281.08:03:12.64#ibcon#read 4, iclass 40, count 0 2006.281.08:03:12.64#ibcon#about to read 5, iclass 40, count 0 2006.281.08:03:12.64#ibcon#read 5, iclass 40, count 0 2006.281.08:03:12.64#ibcon#about to read 6, iclass 40, count 0 2006.281.08:03:12.64#ibcon#read 6, iclass 40, count 0 2006.281.08:03:12.64#ibcon#end of sib2, iclass 40, count 0 2006.281.08:03:12.64#ibcon#*after write, iclass 40, count 0 2006.281.08:03:12.64#ibcon#*before return 0, iclass 40, count 0 2006.281.08:03:12.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:12.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:03:12.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:03:12.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:03:12.64$vc4f8/vblo=4,712.99 2006.281.08:03:12.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:03:12.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:03:12.64#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:12.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:12.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:12.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:12.64#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:03:12.64#ibcon#first serial, iclass 4, count 0 2006.281.08:03:12.64#ibcon#enter sib2, iclass 4, count 0 2006.281.08:03:12.64#ibcon#flushed, iclass 4, count 0 2006.281.08:03:12.64#ibcon#about to write, iclass 4, count 0 2006.281.08:03:12.64#ibcon#wrote, iclass 4, count 0 2006.281.08:03:12.64#ibcon#about to read 3, iclass 4, count 0 2006.281.08:03:12.66#ibcon#read 3, iclass 4, count 0 2006.281.08:03:12.66#ibcon#about to read 4, iclass 4, count 0 2006.281.08:03:12.66#ibcon#read 4, iclass 4, count 0 2006.281.08:03:12.66#ibcon#about to read 5, iclass 4, count 0 2006.281.08:03:12.66#ibcon#read 5, iclass 4, count 0 2006.281.08:03:12.66#ibcon#about to read 6, iclass 4, count 0 2006.281.08:03:12.66#ibcon#read 6, iclass 4, count 0 2006.281.08:03:12.66#ibcon#end of sib2, iclass 4, count 0 2006.281.08:03:12.66#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:03:12.66#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:03:12.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:03:12.66#ibcon#*before write, iclass 4, count 0 2006.281.08:03:12.66#ibcon#enter sib2, iclass 4, count 0 2006.281.08:03:12.66#ibcon#flushed, iclass 4, count 0 2006.281.08:03:12.66#ibcon#about to write, iclass 4, count 0 2006.281.08:03:12.66#ibcon#wrote, iclass 4, count 0 2006.281.08:03:12.66#ibcon#about to read 3, iclass 4, count 0 2006.281.08:03:12.70#ibcon#read 3, iclass 4, count 0 2006.281.08:03:12.70#ibcon#about to read 4, iclass 4, count 0 2006.281.08:03:12.70#ibcon#read 4, iclass 4, count 0 2006.281.08:03:12.70#ibcon#about to read 5, iclass 4, count 0 2006.281.08:03:12.70#ibcon#read 5, iclass 4, count 0 2006.281.08:03:12.70#ibcon#about to read 6, iclass 4, count 0 2006.281.08:03:12.70#ibcon#read 6, iclass 4, count 0 2006.281.08:03:12.70#ibcon#end of sib2, iclass 4, count 0 2006.281.08:03:12.70#ibcon#*after write, iclass 4, count 0 2006.281.08:03:12.70#ibcon#*before return 0, iclass 4, count 0 2006.281.08:03:12.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:12.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:03:12.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:03:12.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:03:12.70$vc4f8/vb=4,4 2006.281.08:03:12.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.08:03:12.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.08:03:12.70#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:12.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:12.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:12.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:12.76#ibcon#enter wrdev, iclass 6, count 2 2006.281.08:03:12.76#ibcon#first serial, iclass 6, count 2 2006.281.08:03:12.76#ibcon#enter sib2, iclass 6, count 2 2006.281.08:03:12.76#ibcon#flushed, iclass 6, count 2 2006.281.08:03:12.76#ibcon#about to write, iclass 6, count 2 2006.281.08:03:12.76#ibcon#wrote, iclass 6, count 2 2006.281.08:03:12.76#ibcon#about to read 3, iclass 6, count 2 2006.281.08:03:12.78#ibcon#read 3, iclass 6, count 2 2006.281.08:03:12.78#ibcon#about to read 4, iclass 6, count 2 2006.281.08:03:12.78#ibcon#read 4, iclass 6, count 2 2006.281.08:03:12.78#ibcon#about to read 5, iclass 6, count 2 2006.281.08:03:12.78#ibcon#read 5, iclass 6, count 2 2006.281.08:03:12.78#ibcon#about to read 6, iclass 6, count 2 2006.281.08:03:12.78#ibcon#read 6, iclass 6, count 2 2006.281.08:03:12.78#ibcon#end of sib2, iclass 6, count 2 2006.281.08:03:12.78#ibcon#*mode == 0, iclass 6, count 2 2006.281.08:03:12.78#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.08:03:12.78#ibcon#[27=AT04-04\r\n] 2006.281.08:03:12.78#ibcon#*before write, iclass 6, count 2 2006.281.08:03:12.78#ibcon#enter sib2, iclass 6, count 2 2006.281.08:03:12.78#ibcon#flushed, iclass 6, count 2 2006.281.08:03:12.78#ibcon#about to write, iclass 6, count 2 2006.281.08:03:12.78#ibcon#wrote, iclass 6, count 2 2006.281.08:03:12.78#ibcon#about to read 3, iclass 6, count 2 2006.281.08:03:12.81#ibcon#read 3, iclass 6, count 2 2006.281.08:03:12.81#ibcon#about to read 4, iclass 6, count 2 2006.281.08:03:12.81#ibcon#read 4, iclass 6, count 2 2006.281.08:03:12.81#ibcon#about to read 5, iclass 6, count 2 2006.281.08:03:12.81#ibcon#read 5, iclass 6, count 2 2006.281.08:03:12.81#ibcon#about to read 6, iclass 6, count 2 2006.281.08:03:12.81#ibcon#read 6, iclass 6, count 2 2006.281.08:03:12.81#ibcon#end of sib2, iclass 6, count 2 2006.281.08:03:12.81#ibcon#*after write, iclass 6, count 2 2006.281.08:03:12.81#ibcon#*before return 0, iclass 6, count 2 2006.281.08:03:12.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:12.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:03:12.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.08:03:12.81#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:12.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:12.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:12.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:12.93#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:03:12.93#ibcon#first serial, iclass 6, count 0 2006.281.08:03:12.93#ibcon#enter sib2, iclass 6, count 0 2006.281.08:03:12.93#ibcon#flushed, iclass 6, count 0 2006.281.08:03:12.93#ibcon#about to write, iclass 6, count 0 2006.281.08:03:12.93#ibcon#wrote, iclass 6, count 0 2006.281.08:03:12.93#ibcon#about to read 3, iclass 6, count 0 2006.281.08:03:12.95#ibcon#read 3, iclass 6, count 0 2006.281.08:03:12.95#ibcon#about to read 4, iclass 6, count 0 2006.281.08:03:12.95#ibcon#read 4, iclass 6, count 0 2006.281.08:03:12.95#ibcon#about to read 5, iclass 6, count 0 2006.281.08:03:12.95#ibcon#read 5, iclass 6, count 0 2006.281.08:03:12.95#ibcon#about to read 6, iclass 6, count 0 2006.281.08:03:12.95#ibcon#read 6, iclass 6, count 0 2006.281.08:03:12.95#ibcon#end of sib2, iclass 6, count 0 2006.281.08:03:12.95#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:03:12.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:03:12.95#ibcon#[27=USB\r\n] 2006.281.08:03:12.95#ibcon#*before write, iclass 6, count 0 2006.281.08:03:12.95#ibcon#enter sib2, iclass 6, count 0 2006.281.08:03:12.95#ibcon#flushed, iclass 6, count 0 2006.281.08:03:12.95#ibcon#about to write, iclass 6, count 0 2006.281.08:03:12.95#ibcon#wrote, iclass 6, count 0 2006.281.08:03:12.95#ibcon#about to read 3, iclass 6, count 0 2006.281.08:03:12.98#ibcon#read 3, iclass 6, count 0 2006.281.08:03:12.98#ibcon#about to read 4, iclass 6, count 0 2006.281.08:03:12.98#ibcon#read 4, iclass 6, count 0 2006.281.08:03:12.98#ibcon#about to read 5, iclass 6, count 0 2006.281.08:03:12.98#ibcon#read 5, iclass 6, count 0 2006.281.08:03:12.98#ibcon#about to read 6, iclass 6, count 0 2006.281.08:03:12.98#ibcon#read 6, iclass 6, count 0 2006.281.08:03:12.98#ibcon#end of sib2, iclass 6, count 0 2006.281.08:03:12.98#ibcon#*after write, iclass 6, count 0 2006.281.08:03:12.98#ibcon#*before return 0, iclass 6, count 0 2006.281.08:03:12.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:12.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:03:12.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:03:12.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:03:12.98$vc4f8/vblo=5,744.99 2006.281.08:03:12.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.08:03:12.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.08:03:12.98#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:12.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:12.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:12.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:12.98#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:03:12.98#ibcon#first serial, iclass 10, count 0 2006.281.08:03:12.98#ibcon#enter sib2, iclass 10, count 0 2006.281.08:03:12.98#ibcon#flushed, iclass 10, count 0 2006.281.08:03:12.98#ibcon#about to write, iclass 10, count 0 2006.281.08:03:12.98#ibcon#wrote, iclass 10, count 0 2006.281.08:03:12.98#ibcon#about to read 3, iclass 10, count 0 2006.281.08:03:13.00#ibcon#read 3, iclass 10, count 0 2006.281.08:03:13.00#ibcon#about to read 4, iclass 10, count 0 2006.281.08:03:13.00#ibcon#read 4, iclass 10, count 0 2006.281.08:03:13.00#ibcon#about to read 5, iclass 10, count 0 2006.281.08:03:13.00#ibcon#read 5, iclass 10, count 0 2006.281.08:03:13.00#ibcon#about to read 6, iclass 10, count 0 2006.281.08:03:13.00#ibcon#read 6, iclass 10, count 0 2006.281.08:03:13.00#ibcon#end of sib2, iclass 10, count 0 2006.281.08:03:13.00#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:03:13.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:03:13.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:03:13.00#ibcon#*before write, iclass 10, count 0 2006.281.08:03:13.00#ibcon#enter sib2, iclass 10, count 0 2006.281.08:03:13.00#ibcon#flushed, iclass 10, count 0 2006.281.08:03:13.00#ibcon#about to write, iclass 10, count 0 2006.281.08:03:13.00#ibcon#wrote, iclass 10, count 0 2006.281.08:03:13.00#ibcon#about to read 3, iclass 10, count 0 2006.281.08:03:13.04#ibcon#read 3, iclass 10, count 0 2006.281.08:03:13.04#ibcon#about to read 4, iclass 10, count 0 2006.281.08:03:13.04#ibcon#read 4, iclass 10, count 0 2006.281.08:03:13.04#ibcon#about to read 5, iclass 10, count 0 2006.281.08:03:13.04#ibcon#read 5, iclass 10, count 0 2006.281.08:03:13.04#ibcon#about to read 6, iclass 10, count 0 2006.281.08:03:13.04#ibcon#read 6, iclass 10, count 0 2006.281.08:03:13.04#ibcon#end of sib2, iclass 10, count 0 2006.281.08:03:13.04#ibcon#*after write, iclass 10, count 0 2006.281.08:03:13.04#ibcon#*before return 0, iclass 10, count 0 2006.281.08:03:13.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:13.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:03:13.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:03:13.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:03:13.04$vc4f8/vb=5,4 2006.281.08:03:13.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.08:03:13.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.08:03:13.05#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:13.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:13.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:13.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:13.10#ibcon#enter wrdev, iclass 12, count 2 2006.281.08:03:13.10#ibcon#first serial, iclass 12, count 2 2006.281.08:03:13.10#ibcon#enter sib2, iclass 12, count 2 2006.281.08:03:13.10#ibcon#flushed, iclass 12, count 2 2006.281.08:03:13.10#ibcon#about to write, iclass 12, count 2 2006.281.08:03:13.10#ibcon#wrote, iclass 12, count 2 2006.281.08:03:13.10#ibcon#about to read 3, iclass 12, count 2 2006.281.08:03:13.12#ibcon#read 3, iclass 12, count 2 2006.281.08:03:13.12#ibcon#about to read 4, iclass 12, count 2 2006.281.08:03:13.12#ibcon#read 4, iclass 12, count 2 2006.281.08:03:13.12#ibcon#about to read 5, iclass 12, count 2 2006.281.08:03:13.12#ibcon#read 5, iclass 12, count 2 2006.281.08:03:13.12#ibcon#about to read 6, iclass 12, count 2 2006.281.08:03:13.12#ibcon#read 6, iclass 12, count 2 2006.281.08:03:13.12#ibcon#end of sib2, iclass 12, count 2 2006.281.08:03:13.12#ibcon#*mode == 0, iclass 12, count 2 2006.281.08:03:13.12#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.08:03:13.12#ibcon#[27=AT05-04\r\n] 2006.281.08:03:13.12#ibcon#*before write, iclass 12, count 2 2006.281.08:03:13.12#ibcon#enter sib2, iclass 12, count 2 2006.281.08:03:13.12#ibcon#flushed, iclass 12, count 2 2006.281.08:03:13.12#ibcon#about to write, iclass 12, count 2 2006.281.08:03:13.12#ibcon#wrote, iclass 12, count 2 2006.281.08:03:13.12#ibcon#about to read 3, iclass 12, count 2 2006.281.08:03:13.15#ibcon#read 3, iclass 12, count 2 2006.281.08:03:13.15#ibcon#about to read 4, iclass 12, count 2 2006.281.08:03:13.15#ibcon#read 4, iclass 12, count 2 2006.281.08:03:13.15#ibcon#about to read 5, iclass 12, count 2 2006.281.08:03:13.15#ibcon#read 5, iclass 12, count 2 2006.281.08:03:13.15#ibcon#about to read 6, iclass 12, count 2 2006.281.08:03:13.15#ibcon#read 6, iclass 12, count 2 2006.281.08:03:13.15#ibcon#end of sib2, iclass 12, count 2 2006.281.08:03:13.15#ibcon#*after write, iclass 12, count 2 2006.281.08:03:13.15#ibcon#*before return 0, iclass 12, count 2 2006.281.08:03:13.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:13.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:03:13.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.08:03:13.15#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:13.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:13.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:13.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:13.27#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:03:13.27#ibcon#first serial, iclass 12, count 0 2006.281.08:03:13.27#ibcon#enter sib2, iclass 12, count 0 2006.281.08:03:13.27#ibcon#flushed, iclass 12, count 0 2006.281.08:03:13.27#ibcon#about to write, iclass 12, count 0 2006.281.08:03:13.27#ibcon#wrote, iclass 12, count 0 2006.281.08:03:13.27#ibcon#about to read 3, iclass 12, count 0 2006.281.08:03:13.29#ibcon#read 3, iclass 12, count 0 2006.281.08:03:13.29#ibcon#about to read 4, iclass 12, count 0 2006.281.08:03:13.29#ibcon#read 4, iclass 12, count 0 2006.281.08:03:13.29#ibcon#about to read 5, iclass 12, count 0 2006.281.08:03:13.29#ibcon#read 5, iclass 12, count 0 2006.281.08:03:13.29#ibcon#about to read 6, iclass 12, count 0 2006.281.08:03:13.29#ibcon#read 6, iclass 12, count 0 2006.281.08:03:13.29#ibcon#end of sib2, iclass 12, count 0 2006.281.08:03:13.29#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:03:13.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:03:13.29#ibcon#[27=USB\r\n] 2006.281.08:03:13.29#ibcon#*before write, iclass 12, count 0 2006.281.08:03:13.29#ibcon#enter sib2, iclass 12, count 0 2006.281.08:03:13.29#ibcon#flushed, iclass 12, count 0 2006.281.08:03:13.29#ibcon#about to write, iclass 12, count 0 2006.281.08:03:13.29#ibcon#wrote, iclass 12, count 0 2006.281.08:03:13.29#ibcon#about to read 3, iclass 12, count 0 2006.281.08:03:13.32#ibcon#read 3, iclass 12, count 0 2006.281.08:03:13.32#ibcon#about to read 4, iclass 12, count 0 2006.281.08:03:13.32#ibcon#read 4, iclass 12, count 0 2006.281.08:03:13.32#ibcon#about to read 5, iclass 12, count 0 2006.281.08:03:13.32#ibcon#read 5, iclass 12, count 0 2006.281.08:03:13.32#ibcon#about to read 6, iclass 12, count 0 2006.281.08:03:13.32#ibcon#read 6, iclass 12, count 0 2006.281.08:03:13.32#ibcon#end of sib2, iclass 12, count 0 2006.281.08:03:13.32#ibcon#*after write, iclass 12, count 0 2006.281.08:03:13.32#ibcon#*before return 0, iclass 12, count 0 2006.281.08:03:13.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:13.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:03:13.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:03:13.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:03:13.32$vc4f8/vblo=6,752.99 2006.281.08:03:13.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:03:13.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:03:13.32#ibcon#ireg 17 cls_cnt 0 2006.281.08:03:13.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:13.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:13.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:13.32#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:03:13.32#ibcon#first serial, iclass 14, count 0 2006.281.08:03:13.32#ibcon#enter sib2, iclass 14, count 0 2006.281.08:03:13.32#ibcon#flushed, iclass 14, count 0 2006.281.08:03:13.32#ibcon#about to write, iclass 14, count 0 2006.281.08:03:13.32#ibcon#wrote, iclass 14, count 0 2006.281.08:03:13.32#ibcon#about to read 3, iclass 14, count 0 2006.281.08:03:13.34#ibcon#read 3, iclass 14, count 0 2006.281.08:03:13.34#ibcon#about to read 4, iclass 14, count 0 2006.281.08:03:13.34#ibcon#read 4, iclass 14, count 0 2006.281.08:03:13.34#ibcon#about to read 5, iclass 14, count 0 2006.281.08:03:13.34#ibcon#read 5, iclass 14, count 0 2006.281.08:03:13.34#ibcon#about to read 6, iclass 14, count 0 2006.281.08:03:13.34#ibcon#read 6, iclass 14, count 0 2006.281.08:03:13.34#ibcon#end of sib2, iclass 14, count 0 2006.281.08:03:13.34#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:03:13.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:03:13.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:03:13.34#ibcon#*before write, iclass 14, count 0 2006.281.08:03:13.34#ibcon#enter sib2, iclass 14, count 0 2006.281.08:03:13.34#ibcon#flushed, iclass 14, count 0 2006.281.08:03:13.34#ibcon#about to write, iclass 14, count 0 2006.281.08:03:13.34#ibcon#wrote, iclass 14, count 0 2006.281.08:03:13.34#ibcon#about to read 3, iclass 14, count 0 2006.281.08:03:13.39#ibcon#read 3, iclass 14, count 0 2006.281.08:03:13.39#ibcon#about to read 4, iclass 14, count 0 2006.281.08:03:13.39#ibcon#read 4, iclass 14, count 0 2006.281.08:03:13.39#ibcon#about to read 5, iclass 14, count 0 2006.281.08:03:13.39#ibcon#read 5, iclass 14, count 0 2006.281.08:03:13.39#ibcon#about to read 6, iclass 14, count 0 2006.281.08:03:13.39#ibcon#read 6, iclass 14, count 0 2006.281.08:03:13.39#ibcon#end of sib2, iclass 14, count 0 2006.281.08:03:13.39#ibcon#*after write, iclass 14, count 0 2006.281.08:03:13.39#ibcon#*before return 0, iclass 14, count 0 2006.281.08:03:13.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:13.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:03:13.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:03:13.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:03:13.39$vc4f8/vb=6,4 2006.281.08:03:13.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.08:03:13.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.08:03:13.39#ibcon#ireg 11 cls_cnt 2 2006.281.08:03:13.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:13.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:13.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:13.44#ibcon#enter wrdev, iclass 16, count 2 2006.281.08:03:13.44#ibcon#first serial, iclass 16, count 2 2006.281.08:03:13.44#ibcon#enter sib2, iclass 16, count 2 2006.281.08:03:13.44#ibcon#flushed, iclass 16, count 2 2006.281.08:03:13.44#ibcon#about to write, iclass 16, count 2 2006.281.08:03:13.44#ibcon#wrote, iclass 16, count 2 2006.281.08:03:13.44#ibcon#about to read 3, iclass 16, count 2 2006.281.08:03:13.46#ibcon#read 3, iclass 16, count 2 2006.281.08:03:13.46#ibcon#about to read 4, iclass 16, count 2 2006.281.08:03:13.46#ibcon#read 4, iclass 16, count 2 2006.281.08:03:13.46#ibcon#about to read 5, iclass 16, count 2 2006.281.08:03:13.46#ibcon#read 5, iclass 16, count 2 2006.281.08:03:13.46#ibcon#about to read 6, iclass 16, count 2 2006.281.08:03:13.46#ibcon#read 6, iclass 16, count 2 2006.281.08:03:13.46#ibcon#end of sib2, iclass 16, count 2 2006.281.08:03:13.46#ibcon#*mode == 0, iclass 16, count 2 2006.281.08:03:13.46#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.08:03:13.46#ibcon#[27=AT06-04\r\n] 2006.281.08:03:13.46#ibcon#*before write, iclass 16, count 2 2006.281.08:03:13.46#ibcon#enter sib2, iclass 16, count 2 2006.281.08:03:13.46#ibcon#flushed, iclass 16, count 2 2006.281.08:03:13.46#ibcon#about to write, iclass 16, count 2 2006.281.08:03:13.46#ibcon#wrote, iclass 16, count 2 2006.281.08:03:13.46#ibcon#about to read 3, iclass 16, count 2 2006.281.08:03:13.49#ibcon#read 3, iclass 16, count 2 2006.281.08:03:13.49#ibcon#about to read 4, iclass 16, count 2 2006.281.08:03:13.49#ibcon#read 4, iclass 16, count 2 2006.281.08:03:13.49#ibcon#about to read 5, iclass 16, count 2 2006.281.08:03:13.49#ibcon#read 5, iclass 16, count 2 2006.281.08:03:13.49#ibcon#about to read 6, iclass 16, count 2 2006.281.08:03:13.49#ibcon#read 6, iclass 16, count 2 2006.281.08:03:13.49#ibcon#end of sib2, iclass 16, count 2 2006.281.08:03:13.49#ibcon#*after write, iclass 16, count 2 2006.281.08:03:13.49#ibcon#*before return 0, iclass 16, count 2 2006.281.08:03:13.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:13.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:03:13.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.08:03:13.49#ibcon#ireg 7 cls_cnt 0 2006.281.08:03:13.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:13.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:13.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:13.61#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:03:13.61#ibcon#first serial, iclass 16, count 0 2006.281.08:03:13.61#ibcon#enter sib2, iclass 16, count 0 2006.281.08:03:13.61#ibcon#flushed, iclass 16, count 0 2006.281.08:03:13.61#ibcon#about to write, iclass 16, count 0 2006.281.08:03:13.61#ibcon#wrote, iclass 16, count 0 2006.281.08:03:13.61#ibcon#about to read 3, iclass 16, count 0 2006.281.08:03:13.63#ibcon#read 3, iclass 16, count 0 2006.281.08:03:13.63#ibcon#about to read 4, iclass 16, count 0 2006.281.08:03:13.63#ibcon#read 4, iclass 16, count 0 2006.281.08:03:13.63#ibcon#about to read 5, iclass 16, count 0 2006.281.08:03:13.63#ibcon#read 5, iclass 16, count 0 2006.281.08:03:13.63#ibcon#about to read 6, iclass 16, count 0 2006.281.08:03:13.63#ibcon#read 6, iclass 16, count 0 2006.281.08:03:13.63#ibcon#end of sib2, iclass 16, count 0 2006.281.08:03:13.63#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:03:13.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:03:13.63#ibcon#[27=USB\r\n] 2006.281.08:03:13.63#ibcon#*before write, iclass 16, count 0 2006.281.08:03:13.63#ibcon#enter sib2, iclass 16, count 0 2006.281.08:03:13.63#ibcon#flushed, iclass 16, count 0 2006.281.08:03:13.63#ibcon#about to write, iclass 16, count 0 2006.281.08:03:13.63#ibcon#wrote, iclass 16, count 0 2006.281.08:03:13.63#ibcon#about to read 3, iclass 16, count 0 2006.281.08:03:13.66#ibcon#read 3, iclass 16, count 0 2006.281.08:03:13.66#ibcon#about to read 4, iclass 16, count 0 2006.281.08:03:13.66#ibcon#read 4, iclass 16, count 0 2006.281.08:03:13.66#ibcon#about to read 5, iclass 16, count 0 2006.281.08:03:13.66#ibcon#read 5, iclass 16, count 0 2006.281.08:03:13.66#ibcon#about to read 6, iclass 16, count 0 2006.281.08:03:13.66#ibcon#read 6, iclass 16, count 0 2006.281.08:03:13.66#ibcon#end of sib2, iclass 16, count 0 2006.281.08:03:13.66#ibcon#*after write, iclass 16, count 0 2006.281.08:03:13.66#ibcon#*before return 0, iclass 16, count 0 2006.281.08:03:13.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:13.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:03:13.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:03:13.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:03:13.66$vc4f8/vabw=wide 2006.281.08:03:13.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.08:03:13.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.08:03:13.66#ibcon#ireg 8 cls_cnt 0 2006.281.08:03:13.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:13.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:13.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:13.66#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:03:13.66#ibcon#first serial, iclass 18, count 0 2006.281.08:03:13.66#ibcon#enter sib2, iclass 18, count 0 2006.281.08:03:13.66#ibcon#flushed, iclass 18, count 0 2006.281.08:03:13.66#ibcon#about to write, iclass 18, count 0 2006.281.08:03:13.66#ibcon#wrote, iclass 18, count 0 2006.281.08:03:13.66#ibcon#about to read 3, iclass 18, count 0 2006.281.08:03:13.68#ibcon#read 3, iclass 18, count 0 2006.281.08:03:13.68#ibcon#about to read 4, iclass 18, count 0 2006.281.08:03:13.68#ibcon#read 4, iclass 18, count 0 2006.281.08:03:13.68#ibcon#about to read 5, iclass 18, count 0 2006.281.08:03:13.68#ibcon#read 5, iclass 18, count 0 2006.281.08:03:13.68#ibcon#about to read 6, iclass 18, count 0 2006.281.08:03:13.68#ibcon#read 6, iclass 18, count 0 2006.281.08:03:13.68#ibcon#end of sib2, iclass 18, count 0 2006.281.08:03:13.68#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:03:13.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:03:13.68#ibcon#[25=BW32\r\n] 2006.281.08:03:13.68#ibcon#*before write, iclass 18, count 0 2006.281.08:03:13.68#ibcon#enter sib2, iclass 18, count 0 2006.281.08:03:13.68#ibcon#flushed, iclass 18, count 0 2006.281.08:03:13.68#ibcon#about to write, iclass 18, count 0 2006.281.08:03:13.68#ibcon#wrote, iclass 18, count 0 2006.281.08:03:13.68#ibcon#about to read 3, iclass 18, count 0 2006.281.08:03:13.71#ibcon#read 3, iclass 18, count 0 2006.281.08:03:13.71#ibcon#about to read 4, iclass 18, count 0 2006.281.08:03:13.71#ibcon#read 4, iclass 18, count 0 2006.281.08:03:13.71#ibcon#about to read 5, iclass 18, count 0 2006.281.08:03:13.71#ibcon#read 5, iclass 18, count 0 2006.281.08:03:13.71#ibcon#about to read 6, iclass 18, count 0 2006.281.08:03:13.71#ibcon#read 6, iclass 18, count 0 2006.281.08:03:13.71#ibcon#end of sib2, iclass 18, count 0 2006.281.08:03:13.71#ibcon#*after write, iclass 18, count 0 2006.281.08:03:13.71#ibcon#*before return 0, iclass 18, count 0 2006.281.08:03:13.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:13.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:03:13.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:03:13.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:03:13.71$vc4f8/vbbw=wide 2006.281.08:03:13.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.08:03:13.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.08:03:13.71#ibcon#ireg 8 cls_cnt 0 2006.281.08:03:13.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:03:13.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:03:13.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:03:13.78#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:03:13.78#ibcon#first serial, iclass 20, count 0 2006.281.08:03:13.78#ibcon#enter sib2, iclass 20, count 0 2006.281.08:03:13.78#ibcon#flushed, iclass 20, count 0 2006.281.08:03:13.78#ibcon#about to write, iclass 20, count 0 2006.281.08:03:13.78#ibcon#wrote, iclass 20, count 0 2006.281.08:03:13.78#ibcon#about to read 3, iclass 20, count 0 2006.281.08:03:13.80#ibcon#read 3, iclass 20, count 0 2006.281.08:03:13.80#ibcon#about to read 4, iclass 20, count 0 2006.281.08:03:13.80#ibcon#read 4, iclass 20, count 0 2006.281.08:03:13.80#ibcon#about to read 5, iclass 20, count 0 2006.281.08:03:13.80#ibcon#read 5, iclass 20, count 0 2006.281.08:03:13.80#ibcon#about to read 6, iclass 20, count 0 2006.281.08:03:13.80#ibcon#read 6, iclass 20, count 0 2006.281.08:03:13.80#ibcon#end of sib2, iclass 20, count 0 2006.281.08:03:13.80#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:03:13.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:03:13.80#ibcon#[27=BW32\r\n] 2006.281.08:03:13.80#ibcon#*before write, iclass 20, count 0 2006.281.08:03:13.80#ibcon#enter sib2, iclass 20, count 0 2006.281.08:03:13.80#ibcon#flushed, iclass 20, count 0 2006.281.08:03:13.80#ibcon#about to write, iclass 20, count 0 2006.281.08:03:13.80#ibcon#wrote, iclass 20, count 0 2006.281.08:03:13.80#ibcon#about to read 3, iclass 20, count 0 2006.281.08:03:13.83#ibcon#read 3, iclass 20, count 0 2006.281.08:03:13.83#ibcon#about to read 4, iclass 20, count 0 2006.281.08:03:13.83#ibcon#read 4, iclass 20, count 0 2006.281.08:03:13.83#ibcon#about to read 5, iclass 20, count 0 2006.281.08:03:13.83#ibcon#read 5, iclass 20, count 0 2006.281.08:03:13.83#ibcon#about to read 6, iclass 20, count 0 2006.281.08:03:13.83#ibcon#read 6, iclass 20, count 0 2006.281.08:03:13.83#ibcon#end of sib2, iclass 20, count 0 2006.281.08:03:13.83#ibcon#*after write, iclass 20, count 0 2006.281.08:03:13.83#ibcon#*before return 0, iclass 20, count 0 2006.281.08:03:13.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:03:13.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:03:13.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:03:13.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:03:13.83$4f8m12a/ifd4f 2006.281.08:03:13.83$ifd4f/lo= 2006.281.08:03:13.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:03:13.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:03:13.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:03:13.84$ifd4f/patch= 2006.281.08:03:13.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:03:13.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:03:13.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:03:13.84$4f8m12a/"form=m,16.000,1:2 2006.281.08:03:13.84$4f8m12a/"tpicd 2006.281.08:03:13.84$4f8m12a/echo=off 2006.281.08:03:13.84$4f8m12a/xlog=off 2006.281.08:03:13.84:!2006.281.08:03:40 2006.281.08:03:18.14#trakl#Source acquired 2006.281.08:03:19.14#flagr#flagr/antenna,acquired 2006.281.08:03:40.00:preob 2006.281.08:03:41.14/onsource/TRACKING 2006.281.08:03:41.14:!2006.281.08:03:50 2006.281.08:03:50.00:data_valid=on 2006.281.08:03:50.00:midob 2006.281.08:03:50.14#trakl#Off source 2006.281.08:03:50.14?ERROR st -7 Antenna off-source! 2006.281.08:03:50.14#trakl#az 276.090 el 11.573 azerr*cos(el) 0.0192 elerr 0.0019 2006.281.08:03:50.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:03:50.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:03:50.14/onsource/SLEWING 2006.281.08:03:50.14/wx/20.42,1001.5,51 2006.281.08:03:50.35/cable/+6.4890E-03 2006.281.08:03:51.14#flagr#flagr/antenna,off-source 2006.281.08:03:51.44/va/01,07,usb,yes,36,38 2006.281.08:03:51.44/va/02,06,usb,yes,34,35 2006.281.08:03:51.44/va/03,06,usb,yes,32,32 2006.281.08:03:51.44/va/04,06,usb,yes,35,38 2006.281.08:03:51.44/va/05,07,usb,yes,33,35 2006.281.08:03:51.44/va/06,06,usb,yes,33,32 2006.281.08:03:51.44/va/07,06,usb,yes,33,33 2006.281.08:03:51.44/va/08,06,usb,yes,35,35 2006.281.08:03:51.67/valo/01,532.99,yes,locked 2006.281.08:03:51.67/valo/02,572.99,yes,locked 2006.281.08:03:51.67/valo/03,672.99,yes,locked 2006.281.08:03:51.67/valo/04,832.99,yes,locked 2006.281.08:03:51.67/valo/05,652.99,yes,locked 2006.281.08:03:51.67/valo/06,772.99,yes,locked 2006.281.08:03:51.67/valo/07,832.99,yes,locked 2006.281.08:03:51.67/valo/08,852.99,yes,locked 2006.281.08:03:52.76/vb/01,04,usb,yes,29,28 2006.281.08:03:52.76/vb/02,05,usb,yes,27,28 2006.281.08:03:52.76/vb/03,04,usb,yes,27,31 2006.281.08:03:52.76/vb/04,04,usb,yes,28,28 2006.281.08:03:52.76/vb/05,04,usb,yes,26,30 2006.281.08:03:52.76/vb/06,04,usb,yes,27,30 2006.281.08:03:52.76/vb/07,04,usb,yes,30,29 2006.281.08:03:52.76/vb/08,04,usb,yes,27,30 2006.281.08:03:52.99/vblo/01,632.99,yes,locked 2006.281.08:03:52.99/vblo/02,640.99,yes,locked 2006.281.08:03:52.99/vblo/03,656.99,yes,locked 2006.281.08:03:52.99/vblo/04,712.99,yes,locked 2006.281.08:03:52.99/vblo/05,744.99,yes,locked 2006.281.08:03:52.99/vblo/06,752.99,yes,locked 2006.281.08:03:52.99/vblo/07,734.99,yes,locked 2006.281.08:03:52.99/vblo/08,744.99,yes,locked 2006.281.08:03:53.14/vabw/8 2006.281.08:03:53.29/vbbw/8 2006.281.08:03:53.38/xfe/off,on,12.0 2006.281.08:03:53.76/ifatt/23,28,28,28 2006.281.08:03:54.08/fmout-gps/S +3.15E-07 2006.281.08:03:54.10:!2006.281.08:05:00 2006.281.08:03:56.14#trakl#Source re-acquired 2006.281.08:03:58.14#flagr#flagr/antenna,re-acquired 2006.281.08:04:23.14#trakl#Off source 2006.281.08:04:23.14?ERROR st -7 Antenna off-source! 2006.281.08:04:23.14#trakl#az 276.169 el 11.463 azerr*cos(el) 0.0173 elerr 0.0108 2006.281.08:04:25.14#flagr#flagr/antenna,off-source 2006.281.08:04:29.14#trakl#Source re-acquired 2006.281.08:04:31.14#flagr#flagr/antenna,re-acquired 2006.281.08:04:45.14#trakl#Off source 2006.281.08:04:45.14?ERROR st -7 Antenna off-source! 2006.281.08:04:45.14#trakl#az 276.222 el 11.390 azerr*cos(el) 0.0187 elerr -0.0009 2006.281.08:04:46.14#flagr#flagr/antenna,off-source 2006.281.08:04:52.14#trakl#Source re-acquired 2006.281.08:04:52.14#flagr#flagr/antenna,re-acquired 2006.281.08:05:00.01:data_valid=off 2006.281.08:05:00.01:postob 2006.281.08:05:00.15/cable/+6.4869E-03 2006.281.08:05:00.15/wx/20.38,1001.6,52 2006.281.08:05:01.08/fmout-gps/S +3.13E-07 2006.281.08:05:01.08:scan_name=281-0805,k06281,60 2006.281.08:05:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.281.08:05:02.14#flagr#flagr/antenna,new-source 2006.281.08:05:02.14:checkk5 2006.281.08:05:02.80/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:05:03.23/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:05:03.79/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:05:04.37/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:05:04.76/chk_obsdata//k5ts1/T2810803??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.281.08:05:05.20/chk_obsdata//k5ts2/T2810803??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.281.08:05:05.57/chk_obsdata//k5ts3/T2810803??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.281.08:05:05.97/chk_obsdata//k5ts4/T2810803??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.281.08:05:06.72/k5log//k5ts1_log_newline 2006.281.08:05:07.48/k5log//k5ts2_log_newline 2006.281.08:05:08.30/k5log//k5ts3_log_newline 2006.281.08:05:09.25/k5log//k5ts4_log_newline 2006.281.08:05:09.27/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:05:09.27:4f8m12a=2 2006.281.08:05:09.27$4f8m12a/echo=on 2006.281.08:05:09.28$4f8m12a/pcalon 2006.281.08:05:09.28$pcalon/"no phase cal control is implemented here 2006.281.08:05:09.28$4f8m12a/"tpicd=stop 2006.281.08:05:09.28$4f8m12a/vc4f8 2006.281.08:05:09.28$vc4f8/valo=1,532.99 2006.281.08:05:09.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:05:09.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:05:09.28#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:09.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:09.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:09.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:09.28#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:05:09.28#ibcon#first serial, iclass 7, count 0 2006.281.08:05:09.28#ibcon#enter sib2, iclass 7, count 0 2006.281.08:05:09.28#ibcon#flushed, iclass 7, count 0 2006.281.08:05:09.28#ibcon#about to write, iclass 7, count 0 2006.281.08:05:09.28#ibcon#wrote, iclass 7, count 0 2006.281.08:05:09.28#ibcon#about to read 3, iclass 7, count 0 2006.281.08:05:09.30#ibcon#read 3, iclass 7, count 0 2006.281.08:05:09.30#ibcon#about to read 4, iclass 7, count 0 2006.281.08:05:09.30#ibcon#read 4, iclass 7, count 0 2006.281.08:05:09.30#ibcon#about to read 5, iclass 7, count 0 2006.281.08:05:09.30#ibcon#read 5, iclass 7, count 0 2006.281.08:05:09.30#ibcon#about to read 6, iclass 7, count 0 2006.281.08:05:09.30#ibcon#read 6, iclass 7, count 0 2006.281.08:05:09.30#ibcon#end of sib2, iclass 7, count 0 2006.281.08:05:09.30#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:05:09.30#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:05:09.30#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:05:09.30#ibcon#*before write, iclass 7, count 0 2006.281.08:05:09.30#ibcon#enter sib2, iclass 7, count 0 2006.281.08:05:09.30#ibcon#flushed, iclass 7, count 0 2006.281.08:05:09.30#ibcon#about to write, iclass 7, count 0 2006.281.08:05:09.30#ibcon#wrote, iclass 7, count 0 2006.281.08:05:09.30#ibcon#about to read 3, iclass 7, count 0 2006.281.08:05:09.35#ibcon#read 3, iclass 7, count 0 2006.281.08:05:09.35#ibcon#about to read 4, iclass 7, count 0 2006.281.08:05:09.35#ibcon#read 4, iclass 7, count 0 2006.281.08:05:09.35#ibcon#about to read 5, iclass 7, count 0 2006.281.08:05:09.35#ibcon#read 5, iclass 7, count 0 2006.281.08:05:09.35#ibcon#about to read 6, iclass 7, count 0 2006.281.08:05:09.35#ibcon#read 6, iclass 7, count 0 2006.281.08:05:09.35#ibcon#end of sib2, iclass 7, count 0 2006.281.08:05:09.35#ibcon#*after write, iclass 7, count 0 2006.281.08:05:09.35#ibcon#*before return 0, iclass 7, count 0 2006.281.08:05:09.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:09.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:09.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:05:09.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:05:09.35$vc4f8/va=1,7 2006.281.08:05:09.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:05:09.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:05:09.35#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:09.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:09.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:09.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:09.35#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:05:09.35#ibcon#first serial, iclass 11, count 2 2006.281.08:05:09.35#ibcon#enter sib2, iclass 11, count 2 2006.281.08:05:09.35#ibcon#flushed, iclass 11, count 2 2006.281.08:05:09.35#ibcon#about to write, iclass 11, count 2 2006.281.08:05:09.35#ibcon#wrote, iclass 11, count 2 2006.281.08:05:09.35#ibcon#about to read 3, iclass 11, count 2 2006.281.08:05:09.37#ibcon#read 3, iclass 11, count 2 2006.281.08:05:09.37#ibcon#about to read 4, iclass 11, count 2 2006.281.08:05:09.37#ibcon#read 4, iclass 11, count 2 2006.281.08:05:09.37#ibcon#about to read 5, iclass 11, count 2 2006.281.08:05:09.37#ibcon#read 5, iclass 11, count 2 2006.281.08:05:09.37#ibcon#about to read 6, iclass 11, count 2 2006.281.08:05:09.37#ibcon#read 6, iclass 11, count 2 2006.281.08:05:09.37#ibcon#end of sib2, iclass 11, count 2 2006.281.08:05:09.37#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:05:09.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:05:09.37#ibcon#[25=AT01-07\r\n] 2006.281.08:05:09.37#ibcon#*before write, iclass 11, count 2 2006.281.08:05:09.37#ibcon#enter sib2, iclass 11, count 2 2006.281.08:05:09.37#ibcon#flushed, iclass 11, count 2 2006.281.08:05:09.37#ibcon#about to write, iclass 11, count 2 2006.281.08:05:09.37#ibcon#wrote, iclass 11, count 2 2006.281.08:05:09.37#ibcon#about to read 3, iclass 11, count 2 2006.281.08:05:09.41#ibcon#read 3, iclass 11, count 2 2006.281.08:05:09.41#ibcon#about to read 4, iclass 11, count 2 2006.281.08:05:09.41#ibcon#read 4, iclass 11, count 2 2006.281.08:05:09.41#ibcon#about to read 5, iclass 11, count 2 2006.281.08:05:09.41#ibcon#read 5, iclass 11, count 2 2006.281.08:05:09.41#ibcon#about to read 6, iclass 11, count 2 2006.281.08:05:09.41#ibcon#read 6, iclass 11, count 2 2006.281.08:05:09.41#ibcon#end of sib2, iclass 11, count 2 2006.281.08:05:09.41#ibcon#*after write, iclass 11, count 2 2006.281.08:05:09.41#ibcon#*before return 0, iclass 11, count 2 2006.281.08:05:09.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:09.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:09.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:05:09.41#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:09.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:09.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:09.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:09.53#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:05:09.53#ibcon#first serial, iclass 11, count 0 2006.281.08:05:09.53#ibcon#enter sib2, iclass 11, count 0 2006.281.08:05:09.53#ibcon#flushed, iclass 11, count 0 2006.281.08:05:09.53#ibcon#about to write, iclass 11, count 0 2006.281.08:05:09.53#ibcon#wrote, iclass 11, count 0 2006.281.08:05:09.53#ibcon#about to read 3, iclass 11, count 0 2006.281.08:05:09.55#ibcon#read 3, iclass 11, count 0 2006.281.08:05:09.55#ibcon#about to read 4, iclass 11, count 0 2006.281.08:05:09.55#ibcon#read 4, iclass 11, count 0 2006.281.08:05:09.55#ibcon#about to read 5, iclass 11, count 0 2006.281.08:05:09.55#ibcon#read 5, iclass 11, count 0 2006.281.08:05:09.55#ibcon#about to read 6, iclass 11, count 0 2006.281.08:05:09.55#ibcon#read 6, iclass 11, count 0 2006.281.08:05:09.55#ibcon#end of sib2, iclass 11, count 0 2006.281.08:05:09.55#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:05:09.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:05:09.55#ibcon#[25=USB\r\n] 2006.281.08:05:09.55#ibcon#*before write, iclass 11, count 0 2006.281.08:05:09.55#ibcon#enter sib2, iclass 11, count 0 2006.281.08:05:09.55#ibcon#flushed, iclass 11, count 0 2006.281.08:05:09.55#ibcon#about to write, iclass 11, count 0 2006.281.08:05:09.55#ibcon#wrote, iclass 11, count 0 2006.281.08:05:09.55#ibcon#about to read 3, iclass 11, count 0 2006.281.08:05:09.58#ibcon#read 3, iclass 11, count 0 2006.281.08:05:09.58#ibcon#about to read 4, iclass 11, count 0 2006.281.08:05:09.58#ibcon#read 4, iclass 11, count 0 2006.281.08:05:09.58#ibcon#about to read 5, iclass 11, count 0 2006.281.08:05:09.58#ibcon#read 5, iclass 11, count 0 2006.281.08:05:09.58#ibcon#about to read 6, iclass 11, count 0 2006.281.08:05:09.58#ibcon#read 6, iclass 11, count 0 2006.281.08:05:09.58#ibcon#end of sib2, iclass 11, count 0 2006.281.08:05:09.58#ibcon#*after write, iclass 11, count 0 2006.281.08:05:09.58#ibcon#*before return 0, iclass 11, count 0 2006.281.08:05:09.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:09.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:09.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:05:09.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:05:09.58$vc4f8/valo=2,572.99 2006.281.08:05:09.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:05:09.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:05:09.58#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:09.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:09.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:09.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:09.58#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:05:09.58#ibcon#first serial, iclass 13, count 0 2006.281.08:05:09.58#ibcon#enter sib2, iclass 13, count 0 2006.281.08:05:09.58#ibcon#flushed, iclass 13, count 0 2006.281.08:05:09.58#ibcon#about to write, iclass 13, count 0 2006.281.08:05:09.58#ibcon#wrote, iclass 13, count 0 2006.281.08:05:09.58#ibcon#about to read 3, iclass 13, count 0 2006.281.08:05:09.60#ibcon#read 3, iclass 13, count 0 2006.281.08:05:09.60#ibcon#about to read 4, iclass 13, count 0 2006.281.08:05:09.60#ibcon#read 4, iclass 13, count 0 2006.281.08:05:09.60#ibcon#about to read 5, iclass 13, count 0 2006.281.08:05:09.60#ibcon#read 5, iclass 13, count 0 2006.281.08:05:09.60#ibcon#about to read 6, iclass 13, count 0 2006.281.08:05:09.60#ibcon#read 6, iclass 13, count 0 2006.281.08:05:09.60#ibcon#end of sib2, iclass 13, count 0 2006.281.08:05:09.60#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:05:09.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:05:09.60#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:05:09.60#ibcon#*before write, iclass 13, count 0 2006.281.08:05:09.60#ibcon#enter sib2, iclass 13, count 0 2006.281.08:05:09.60#ibcon#flushed, iclass 13, count 0 2006.281.08:05:09.60#ibcon#about to write, iclass 13, count 0 2006.281.08:05:09.60#ibcon#wrote, iclass 13, count 0 2006.281.08:05:09.60#ibcon#about to read 3, iclass 13, count 0 2006.281.08:05:09.64#ibcon#read 3, iclass 13, count 0 2006.281.08:05:09.64#ibcon#about to read 4, iclass 13, count 0 2006.281.08:05:09.64#ibcon#read 4, iclass 13, count 0 2006.281.08:05:09.64#ibcon#about to read 5, iclass 13, count 0 2006.281.08:05:09.64#ibcon#read 5, iclass 13, count 0 2006.281.08:05:09.64#ibcon#about to read 6, iclass 13, count 0 2006.281.08:05:09.64#ibcon#read 6, iclass 13, count 0 2006.281.08:05:09.64#ibcon#end of sib2, iclass 13, count 0 2006.281.08:05:09.64#ibcon#*after write, iclass 13, count 0 2006.281.08:05:09.64#ibcon#*before return 0, iclass 13, count 0 2006.281.08:05:09.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:09.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:09.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:05:09.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:05:09.64$vc4f8/va=2,6 2006.281.08:05:09.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:05:09.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:05:09.64#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:09.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:09.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:09.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:09.70#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:05:09.70#ibcon#first serial, iclass 15, count 2 2006.281.08:05:09.70#ibcon#enter sib2, iclass 15, count 2 2006.281.08:05:09.70#ibcon#flushed, iclass 15, count 2 2006.281.08:05:09.70#ibcon#about to write, iclass 15, count 2 2006.281.08:05:09.70#ibcon#wrote, iclass 15, count 2 2006.281.08:05:09.70#ibcon#about to read 3, iclass 15, count 2 2006.281.08:05:09.72#ibcon#read 3, iclass 15, count 2 2006.281.08:05:09.72#ibcon#about to read 4, iclass 15, count 2 2006.281.08:05:09.72#ibcon#read 4, iclass 15, count 2 2006.281.08:05:09.72#ibcon#about to read 5, iclass 15, count 2 2006.281.08:05:09.72#ibcon#read 5, iclass 15, count 2 2006.281.08:05:09.72#ibcon#about to read 6, iclass 15, count 2 2006.281.08:05:09.72#ibcon#read 6, iclass 15, count 2 2006.281.08:05:09.72#ibcon#end of sib2, iclass 15, count 2 2006.281.08:05:09.72#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:05:09.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:05:09.72#ibcon#[25=AT02-06\r\n] 2006.281.08:05:09.72#ibcon#*before write, iclass 15, count 2 2006.281.08:05:09.72#ibcon#enter sib2, iclass 15, count 2 2006.281.08:05:09.72#ibcon#flushed, iclass 15, count 2 2006.281.08:05:09.72#ibcon#about to write, iclass 15, count 2 2006.281.08:05:09.72#ibcon#wrote, iclass 15, count 2 2006.281.08:05:09.72#ibcon#about to read 3, iclass 15, count 2 2006.281.08:05:09.75#ibcon#read 3, iclass 15, count 2 2006.281.08:05:09.75#ibcon#about to read 4, iclass 15, count 2 2006.281.08:05:09.75#ibcon#read 4, iclass 15, count 2 2006.281.08:05:09.75#ibcon#about to read 5, iclass 15, count 2 2006.281.08:05:09.75#ibcon#read 5, iclass 15, count 2 2006.281.08:05:09.75#ibcon#about to read 6, iclass 15, count 2 2006.281.08:05:09.75#ibcon#read 6, iclass 15, count 2 2006.281.08:05:09.75#ibcon#end of sib2, iclass 15, count 2 2006.281.08:05:09.75#ibcon#*after write, iclass 15, count 2 2006.281.08:05:09.75#ibcon#*before return 0, iclass 15, count 2 2006.281.08:05:09.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:09.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:09.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:05:09.75#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:09.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:09.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:09.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:09.87#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:05:09.87#ibcon#first serial, iclass 15, count 0 2006.281.08:05:09.87#ibcon#enter sib2, iclass 15, count 0 2006.281.08:05:09.87#ibcon#flushed, iclass 15, count 0 2006.281.08:05:09.87#ibcon#about to write, iclass 15, count 0 2006.281.08:05:09.87#ibcon#wrote, iclass 15, count 0 2006.281.08:05:09.87#ibcon#about to read 3, iclass 15, count 0 2006.281.08:05:09.89#ibcon#read 3, iclass 15, count 0 2006.281.08:05:09.89#ibcon#about to read 4, iclass 15, count 0 2006.281.08:05:09.89#ibcon#read 4, iclass 15, count 0 2006.281.08:05:09.89#ibcon#about to read 5, iclass 15, count 0 2006.281.08:05:09.89#ibcon#read 5, iclass 15, count 0 2006.281.08:05:09.89#ibcon#about to read 6, iclass 15, count 0 2006.281.08:05:09.89#ibcon#read 6, iclass 15, count 0 2006.281.08:05:09.89#ibcon#end of sib2, iclass 15, count 0 2006.281.08:05:09.89#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:05:09.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:05:09.89#ibcon#[25=USB\r\n] 2006.281.08:05:09.89#ibcon#*before write, iclass 15, count 0 2006.281.08:05:09.89#ibcon#enter sib2, iclass 15, count 0 2006.281.08:05:09.89#ibcon#flushed, iclass 15, count 0 2006.281.08:05:09.89#ibcon#about to write, iclass 15, count 0 2006.281.08:05:09.89#ibcon#wrote, iclass 15, count 0 2006.281.08:05:09.89#ibcon#about to read 3, iclass 15, count 0 2006.281.08:05:09.92#ibcon#read 3, iclass 15, count 0 2006.281.08:05:09.92#ibcon#about to read 4, iclass 15, count 0 2006.281.08:05:09.92#ibcon#read 4, iclass 15, count 0 2006.281.08:05:09.92#ibcon#about to read 5, iclass 15, count 0 2006.281.08:05:09.92#ibcon#read 5, iclass 15, count 0 2006.281.08:05:09.92#ibcon#about to read 6, iclass 15, count 0 2006.281.08:05:09.92#ibcon#read 6, iclass 15, count 0 2006.281.08:05:09.92#ibcon#end of sib2, iclass 15, count 0 2006.281.08:05:09.92#ibcon#*after write, iclass 15, count 0 2006.281.08:05:09.92#ibcon#*before return 0, iclass 15, count 0 2006.281.08:05:09.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:09.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:09.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:05:09.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:05:09.92$vc4f8/valo=3,672.99 2006.281.08:05:09.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:05:09.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:05:09.92#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:09.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:09.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:09.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:09.92#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:05:09.92#ibcon#first serial, iclass 17, count 0 2006.281.08:05:09.92#ibcon#enter sib2, iclass 17, count 0 2006.281.08:05:09.92#ibcon#flushed, iclass 17, count 0 2006.281.08:05:09.92#ibcon#about to write, iclass 17, count 0 2006.281.08:05:09.92#ibcon#wrote, iclass 17, count 0 2006.281.08:05:09.92#ibcon#about to read 3, iclass 17, count 0 2006.281.08:05:09.94#ibcon#read 3, iclass 17, count 0 2006.281.08:05:09.94#ibcon#about to read 4, iclass 17, count 0 2006.281.08:05:09.94#ibcon#read 4, iclass 17, count 0 2006.281.08:05:09.94#ibcon#about to read 5, iclass 17, count 0 2006.281.08:05:09.94#ibcon#read 5, iclass 17, count 0 2006.281.08:05:09.94#ibcon#about to read 6, iclass 17, count 0 2006.281.08:05:09.94#ibcon#read 6, iclass 17, count 0 2006.281.08:05:09.94#ibcon#end of sib2, iclass 17, count 0 2006.281.08:05:09.94#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:05:09.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:05:09.94#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:05:09.94#ibcon#*before write, iclass 17, count 0 2006.281.08:05:09.94#ibcon#enter sib2, iclass 17, count 0 2006.281.08:05:09.94#ibcon#flushed, iclass 17, count 0 2006.281.08:05:09.94#ibcon#about to write, iclass 17, count 0 2006.281.08:05:09.94#ibcon#wrote, iclass 17, count 0 2006.281.08:05:09.94#ibcon#about to read 3, iclass 17, count 0 2006.281.08:05:09.98#ibcon#read 3, iclass 17, count 0 2006.281.08:05:09.98#ibcon#about to read 4, iclass 17, count 0 2006.281.08:05:09.98#ibcon#read 4, iclass 17, count 0 2006.281.08:05:09.98#ibcon#about to read 5, iclass 17, count 0 2006.281.08:05:09.98#ibcon#read 5, iclass 17, count 0 2006.281.08:05:09.98#ibcon#about to read 6, iclass 17, count 0 2006.281.08:05:09.98#ibcon#read 6, iclass 17, count 0 2006.281.08:05:09.98#ibcon#end of sib2, iclass 17, count 0 2006.281.08:05:09.98#ibcon#*after write, iclass 17, count 0 2006.281.08:05:09.98#ibcon#*before return 0, iclass 17, count 0 2006.281.08:05:09.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:09.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:09.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:05:09.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:05:09.98$vc4f8/va=3,6 2006.281.08:05:09.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:05:09.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:05:09.99#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:09.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:10.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:10.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:10.04#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:05:10.04#ibcon#first serial, iclass 19, count 2 2006.281.08:05:10.04#ibcon#enter sib2, iclass 19, count 2 2006.281.08:05:10.04#ibcon#flushed, iclass 19, count 2 2006.281.08:05:10.04#ibcon#about to write, iclass 19, count 2 2006.281.08:05:10.04#ibcon#wrote, iclass 19, count 2 2006.281.08:05:10.04#ibcon#about to read 3, iclass 19, count 2 2006.281.08:05:10.06#ibcon#read 3, iclass 19, count 2 2006.281.08:05:10.06#ibcon#about to read 4, iclass 19, count 2 2006.281.08:05:10.06#ibcon#read 4, iclass 19, count 2 2006.281.08:05:10.06#ibcon#about to read 5, iclass 19, count 2 2006.281.08:05:10.06#ibcon#read 5, iclass 19, count 2 2006.281.08:05:10.06#ibcon#about to read 6, iclass 19, count 2 2006.281.08:05:10.06#ibcon#read 6, iclass 19, count 2 2006.281.08:05:10.06#ibcon#end of sib2, iclass 19, count 2 2006.281.08:05:10.06#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:05:10.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:05:10.06#ibcon#[25=AT03-06\r\n] 2006.281.08:05:10.06#ibcon#*before write, iclass 19, count 2 2006.281.08:05:10.06#ibcon#enter sib2, iclass 19, count 2 2006.281.08:05:10.06#ibcon#flushed, iclass 19, count 2 2006.281.08:05:10.06#ibcon#about to write, iclass 19, count 2 2006.281.08:05:10.06#ibcon#wrote, iclass 19, count 2 2006.281.08:05:10.06#ibcon#about to read 3, iclass 19, count 2 2006.281.08:05:10.09#ibcon#read 3, iclass 19, count 2 2006.281.08:05:10.09#ibcon#about to read 4, iclass 19, count 2 2006.281.08:05:10.09#ibcon#read 4, iclass 19, count 2 2006.281.08:05:10.09#ibcon#about to read 5, iclass 19, count 2 2006.281.08:05:10.09#ibcon#read 5, iclass 19, count 2 2006.281.08:05:10.09#ibcon#about to read 6, iclass 19, count 2 2006.281.08:05:10.09#ibcon#read 6, iclass 19, count 2 2006.281.08:05:10.09#ibcon#end of sib2, iclass 19, count 2 2006.281.08:05:10.09#ibcon#*after write, iclass 19, count 2 2006.281.08:05:10.09#ibcon#*before return 0, iclass 19, count 2 2006.281.08:05:10.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:10.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:10.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:05:10.09#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:10.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:10.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:10.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:10.21#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:05:10.21#ibcon#first serial, iclass 19, count 0 2006.281.08:05:10.21#ibcon#enter sib2, iclass 19, count 0 2006.281.08:05:10.21#ibcon#flushed, iclass 19, count 0 2006.281.08:05:10.21#ibcon#about to write, iclass 19, count 0 2006.281.08:05:10.21#ibcon#wrote, iclass 19, count 0 2006.281.08:05:10.21#ibcon#about to read 3, iclass 19, count 0 2006.281.08:05:10.23#ibcon#read 3, iclass 19, count 0 2006.281.08:05:10.23#ibcon#about to read 4, iclass 19, count 0 2006.281.08:05:10.23#ibcon#read 4, iclass 19, count 0 2006.281.08:05:10.23#ibcon#about to read 5, iclass 19, count 0 2006.281.08:05:10.23#ibcon#read 5, iclass 19, count 0 2006.281.08:05:10.23#ibcon#about to read 6, iclass 19, count 0 2006.281.08:05:10.23#ibcon#read 6, iclass 19, count 0 2006.281.08:05:10.23#ibcon#end of sib2, iclass 19, count 0 2006.281.08:05:10.23#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:05:10.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:05:10.23#ibcon#[25=USB\r\n] 2006.281.08:05:10.23#ibcon#*before write, iclass 19, count 0 2006.281.08:05:10.23#ibcon#enter sib2, iclass 19, count 0 2006.281.08:05:10.23#ibcon#flushed, iclass 19, count 0 2006.281.08:05:10.23#ibcon#about to write, iclass 19, count 0 2006.281.08:05:10.23#ibcon#wrote, iclass 19, count 0 2006.281.08:05:10.23#ibcon#about to read 3, iclass 19, count 0 2006.281.08:05:10.26#ibcon#read 3, iclass 19, count 0 2006.281.08:05:10.26#ibcon#about to read 4, iclass 19, count 0 2006.281.08:05:10.26#ibcon#read 4, iclass 19, count 0 2006.281.08:05:10.26#ibcon#about to read 5, iclass 19, count 0 2006.281.08:05:10.26#ibcon#read 5, iclass 19, count 0 2006.281.08:05:10.26#ibcon#about to read 6, iclass 19, count 0 2006.281.08:05:10.26#ibcon#read 6, iclass 19, count 0 2006.281.08:05:10.26#ibcon#end of sib2, iclass 19, count 0 2006.281.08:05:10.26#ibcon#*after write, iclass 19, count 0 2006.281.08:05:10.26#ibcon#*before return 0, iclass 19, count 0 2006.281.08:05:10.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:10.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:10.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:05:10.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:05:10.26$vc4f8/valo=4,832.99 2006.281.08:05:10.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:05:10.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:05:10.26#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:10.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:10.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:10.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:10.26#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:05:10.26#ibcon#first serial, iclass 21, count 0 2006.281.08:05:10.26#ibcon#enter sib2, iclass 21, count 0 2006.281.08:05:10.26#ibcon#flushed, iclass 21, count 0 2006.281.08:05:10.26#ibcon#about to write, iclass 21, count 0 2006.281.08:05:10.26#ibcon#wrote, iclass 21, count 0 2006.281.08:05:10.26#ibcon#about to read 3, iclass 21, count 0 2006.281.08:05:10.28#ibcon#read 3, iclass 21, count 0 2006.281.08:05:10.28#ibcon#about to read 4, iclass 21, count 0 2006.281.08:05:10.28#ibcon#read 4, iclass 21, count 0 2006.281.08:05:10.28#ibcon#about to read 5, iclass 21, count 0 2006.281.08:05:10.28#ibcon#read 5, iclass 21, count 0 2006.281.08:05:10.28#ibcon#about to read 6, iclass 21, count 0 2006.281.08:05:10.28#ibcon#read 6, iclass 21, count 0 2006.281.08:05:10.28#ibcon#end of sib2, iclass 21, count 0 2006.281.08:05:10.28#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:05:10.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:05:10.28#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:05:10.28#ibcon#*before write, iclass 21, count 0 2006.281.08:05:10.28#ibcon#enter sib2, iclass 21, count 0 2006.281.08:05:10.28#ibcon#flushed, iclass 21, count 0 2006.281.08:05:10.28#ibcon#about to write, iclass 21, count 0 2006.281.08:05:10.28#ibcon#wrote, iclass 21, count 0 2006.281.08:05:10.28#ibcon#about to read 3, iclass 21, count 0 2006.281.08:05:10.33#ibcon#read 3, iclass 21, count 0 2006.281.08:05:10.33#ibcon#about to read 4, iclass 21, count 0 2006.281.08:05:10.33#ibcon#read 4, iclass 21, count 0 2006.281.08:05:10.33#ibcon#about to read 5, iclass 21, count 0 2006.281.08:05:10.33#ibcon#read 5, iclass 21, count 0 2006.281.08:05:10.33#ibcon#about to read 6, iclass 21, count 0 2006.281.08:05:10.33#ibcon#read 6, iclass 21, count 0 2006.281.08:05:10.33#ibcon#end of sib2, iclass 21, count 0 2006.281.08:05:10.33#ibcon#*after write, iclass 21, count 0 2006.281.08:05:10.33#ibcon#*before return 0, iclass 21, count 0 2006.281.08:05:10.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:10.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:10.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:05:10.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:05:10.33$vc4f8/va=4,6 2006.281.08:05:10.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:05:10.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:05:10.33#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:10.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:10.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:10.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:10.38#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:05:10.38#ibcon#first serial, iclass 23, count 2 2006.281.08:05:10.38#ibcon#enter sib2, iclass 23, count 2 2006.281.08:05:10.38#ibcon#flushed, iclass 23, count 2 2006.281.08:05:10.38#ibcon#about to write, iclass 23, count 2 2006.281.08:05:10.38#ibcon#wrote, iclass 23, count 2 2006.281.08:05:10.38#ibcon#about to read 3, iclass 23, count 2 2006.281.08:05:10.40#ibcon#read 3, iclass 23, count 2 2006.281.08:05:10.40#ibcon#about to read 4, iclass 23, count 2 2006.281.08:05:10.40#ibcon#read 4, iclass 23, count 2 2006.281.08:05:10.40#ibcon#about to read 5, iclass 23, count 2 2006.281.08:05:10.40#ibcon#read 5, iclass 23, count 2 2006.281.08:05:10.40#ibcon#about to read 6, iclass 23, count 2 2006.281.08:05:10.40#ibcon#read 6, iclass 23, count 2 2006.281.08:05:10.40#ibcon#end of sib2, iclass 23, count 2 2006.281.08:05:10.40#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:05:10.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:05:10.40#ibcon#[25=AT04-06\r\n] 2006.281.08:05:10.40#ibcon#*before write, iclass 23, count 2 2006.281.08:05:10.40#ibcon#enter sib2, iclass 23, count 2 2006.281.08:05:10.40#ibcon#flushed, iclass 23, count 2 2006.281.08:05:10.40#ibcon#about to write, iclass 23, count 2 2006.281.08:05:10.40#ibcon#wrote, iclass 23, count 2 2006.281.08:05:10.40#ibcon#about to read 3, iclass 23, count 2 2006.281.08:05:10.43#ibcon#read 3, iclass 23, count 2 2006.281.08:05:10.43#ibcon#about to read 4, iclass 23, count 2 2006.281.08:05:10.43#ibcon#read 4, iclass 23, count 2 2006.281.08:05:10.43#ibcon#about to read 5, iclass 23, count 2 2006.281.08:05:10.43#ibcon#read 5, iclass 23, count 2 2006.281.08:05:10.43#ibcon#about to read 6, iclass 23, count 2 2006.281.08:05:10.43#ibcon#read 6, iclass 23, count 2 2006.281.08:05:10.43#ibcon#end of sib2, iclass 23, count 2 2006.281.08:05:10.43#ibcon#*after write, iclass 23, count 2 2006.281.08:05:10.43#ibcon#*before return 0, iclass 23, count 2 2006.281.08:05:10.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:10.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:10.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:05:10.43#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:10.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:10.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:10.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:10.55#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:05:10.55#ibcon#first serial, iclass 23, count 0 2006.281.08:05:10.55#ibcon#enter sib2, iclass 23, count 0 2006.281.08:05:10.55#ibcon#flushed, iclass 23, count 0 2006.281.08:05:10.55#ibcon#about to write, iclass 23, count 0 2006.281.08:05:10.55#ibcon#wrote, iclass 23, count 0 2006.281.08:05:10.55#ibcon#about to read 3, iclass 23, count 0 2006.281.08:05:10.57#ibcon#read 3, iclass 23, count 0 2006.281.08:05:10.57#ibcon#about to read 4, iclass 23, count 0 2006.281.08:05:10.57#ibcon#read 4, iclass 23, count 0 2006.281.08:05:10.57#ibcon#about to read 5, iclass 23, count 0 2006.281.08:05:10.57#ibcon#read 5, iclass 23, count 0 2006.281.08:05:10.57#ibcon#about to read 6, iclass 23, count 0 2006.281.08:05:10.57#ibcon#read 6, iclass 23, count 0 2006.281.08:05:10.57#ibcon#end of sib2, iclass 23, count 0 2006.281.08:05:10.57#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:05:10.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:05:10.57#ibcon#[25=USB\r\n] 2006.281.08:05:10.57#ibcon#*before write, iclass 23, count 0 2006.281.08:05:10.57#ibcon#enter sib2, iclass 23, count 0 2006.281.08:05:10.57#ibcon#flushed, iclass 23, count 0 2006.281.08:05:10.57#ibcon#about to write, iclass 23, count 0 2006.281.08:05:10.57#ibcon#wrote, iclass 23, count 0 2006.281.08:05:10.57#ibcon#about to read 3, iclass 23, count 0 2006.281.08:05:10.60#ibcon#read 3, iclass 23, count 0 2006.281.08:05:10.60#ibcon#about to read 4, iclass 23, count 0 2006.281.08:05:10.60#ibcon#read 4, iclass 23, count 0 2006.281.08:05:10.60#ibcon#about to read 5, iclass 23, count 0 2006.281.08:05:10.60#ibcon#read 5, iclass 23, count 0 2006.281.08:05:10.60#ibcon#about to read 6, iclass 23, count 0 2006.281.08:05:10.60#ibcon#read 6, iclass 23, count 0 2006.281.08:05:10.60#ibcon#end of sib2, iclass 23, count 0 2006.281.08:05:10.60#ibcon#*after write, iclass 23, count 0 2006.281.08:05:10.60#ibcon#*before return 0, iclass 23, count 0 2006.281.08:05:10.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:10.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:10.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:05:10.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:05:10.60$vc4f8/valo=5,652.99 2006.281.08:05:10.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:05:10.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:05:10.60#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:10.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:10.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:10.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:10.60#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:05:10.60#ibcon#first serial, iclass 25, count 0 2006.281.08:05:10.60#ibcon#enter sib2, iclass 25, count 0 2006.281.08:05:10.60#ibcon#flushed, iclass 25, count 0 2006.281.08:05:10.60#ibcon#about to write, iclass 25, count 0 2006.281.08:05:10.60#ibcon#wrote, iclass 25, count 0 2006.281.08:05:10.60#ibcon#about to read 3, iclass 25, count 0 2006.281.08:05:10.62#ibcon#read 3, iclass 25, count 0 2006.281.08:05:10.62#ibcon#about to read 4, iclass 25, count 0 2006.281.08:05:10.62#ibcon#read 4, iclass 25, count 0 2006.281.08:05:10.62#ibcon#about to read 5, iclass 25, count 0 2006.281.08:05:10.62#ibcon#read 5, iclass 25, count 0 2006.281.08:05:10.62#ibcon#about to read 6, iclass 25, count 0 2006.281.08:05:10.62#ibcon#read 6, iclass 25, count 0 2006.281.08:05:10.62#ibcon#end of sib2, iclass 25, count 0 2006.281.08:05:10.62#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:05:10.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:05:10.62#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:05:10.62#ibcon#*before write, iclass 25, count 0 2006.281.08:05:10.62#ibcon#enter sib2, iclass 25, count 0 2006.281.08:05:10.62#ibcon#flushed, iclass 25, count 0 2006.281.08:05:10.62#ibcon#about to write, iclass 25, count 0 2006.281.08:05:10.62#ibcon#wrote, iclass 25, count 0 2006.281.08:05:10.62#ibcon#about to read 3, iclass 25, count 0 2006.281.08:05:10.66#ibcon#read 3, iclass 25, count 0 2006.281.08:05:10.66#ibcon#about to read 4, iclass 25, count 0 2006.281.08:05:10.66#ibcon#read 4, iclass 25, count 0 2006.281.08:05:10.66#ibcon#about to read 5, iclass 25, count 0 2006.281.08:05:10.66#ibcon#read 5, iclass 25, count 0 2006.281.08:05:10.66#ibcon#about to read 6, iclass 25, count 0 2006.281.08:05:10.66#ibcon#read 6, iclass 25, count 0 2006.281.08:05:10.66#ibcon#end of sib2, iclass 25, count 0 2006.281.08:05:10.66#ibcon#*after write, iclass 25, count 0 2006.281.08:05:10.66#ibcon#*before return 0, iclass 25, count 0 2006.281.08:05:10.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:10.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:10.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:05:10.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:05:10.66$vc4f8/va=5,7 2006.281.08:05:10.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:05:10.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:05:10.66#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:10.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:10.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:10.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:10.72#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:05:10.72#ibcon#first serial, iclass 27, count 2 2006.281.08:05:10.72#ibcon#enter sib2, iclass 27, count 2 2006.281.08:05:10.72#ibcon#flushed, iclass 27, count 2 2006.281.08:05:10.72#ibcon#about to write, iclass 27, count 2 2006.281.08:05:10.72#ibcon#wrote, iclass 27, count 2 2006.281.08:05:10.72#ibcon#about to read 3, iclass 27, count 2 2006.281.08:05:10.74#ibcon#read 3, iclass 27, count 2 2006.281.08:05:10.74#ibcon#about to read 4, iclass 27, count 2 2006.281.08:05:10.74#ibcon#read 4, iclass 27, count 2 2006.281.08:05:10.74#ibcon#about to read 5, iclass 27, count 2 2006.281.08:05:10.74#ibcon#read 5, iclass 27, count 2 2006.281.08:05:10.74#ibcon#about to read 6, iclass 27, count 2 2006.281.08:05:10.74#ibcon#read 6, iclass 27, count 2 2006.281.08:05:10.74#ibcon#end of sib2, iclass 27, count 2 2006.281.08:05:10.74#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:05:10.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:05:10.74#ibcon#[25=AT05-07\r\n] 2006.281.08:05:10.74#ibcon#*before write, iclass 27, count 2 2006.281.08:05:10.74#ibcon#enter sib2, iclass 27, count 2 2006.281.08:05:10.74#ibcon#flushed, iclass 27, count 2 2006.281.08:05:10.74#ibcon#about to write, iclass 27, count 2 2006.281.08:05:10.74#ibcon#wrote, iclass 27, count 2 2006.281.08:05:10.74#ibcon#about to read 3, iclass 27, count 2 2006.281.08:05:10.77#ibcon#read 3, iclass 27, count 2 2006.281.08:05:10.77#ibcon#about to read 4, iclass 27, count 2 2006.281.08:05:10.77#ibcon#read 4, iclass 27, count 2 2006.281.08:05:10.77#ibcon#about to read 5, iclass 27, count 2 2006.281.08:05:10.77#ibcon#read 5, iclass 27, count 2 2006.281.08:05:10.77#ibcon#about to read 6, iclass 27, count 2 2006.281.08:05:10.77#ibcon#read 6, iclass 27, count 2 2006.281.08:05:10.77#ibcon#end of sib2, iclass 27, count 2 2006.281.08:05:10.77#ibcon#*after write, iclass 27, count 2 2006.281.08:05:10.77#ibcon#*before return 0, iclass 27, count 2 2006.281.08:05:10.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:10.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:10.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:05:10.77#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:10.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:10.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:10.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:10.89#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:05:10.89#ibcon#first serial, iclass 27, count 0 2006.281.08:05:10.89#ibcon#enter sib2, iclass 27, count 0 2006.281.08:05:10.89#ibcon#flushed, iclass 27, count 0 2006.281.08:05:10.89#ibcon#about to write, iclass 27, count 0 2006.281.08:05:10.89#ibcon#wrote, iclass 27, count 0 2006.281.08:05:10.89#ibcon#about to read 3, iclass 27, count 0 2006.281.08:05:10.91#ibcon#read 3, iclass 27, count 0 2006.281.08:05:10.91#ibcon#about to read 4, iclass 27, count 0 2006.281.08:05:10.91#ibcon#read 4, iclass 27, count 0 2006.281.08:05:10.91#ibcon#about to read 5, iclass 27, count 0 2006.281.08:05:10.91#ibcon#read 5, iclass 27, count 0 2006.281.08:05:10.91#ibcon#about to read 6, iclass 27, count 0 2006.281.08:05:10.91#ibcon#read 6, iclass 27, count 0 2006.281.08:05:10.91#ibcon#end of sib2, iclass 27, count 0 2006.281.08:05:10.91#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:05:10.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:05:10.91#ibcon#[25=USB\r\n] 2006.281.08:05:10.91#ibcon#*before write, iclass 27, count 0 2006.281.08:05:10.91#ibcon#enter sib2, iclass 27, count 0 2006.281.08:05:10.91#ibcon#flushed, iclass 27, count 0 2006.281.08:05:10.91#ibcon#about to write, iclass 27, count 0 2006.281.08:05:10.91#ibcon#wrote, iclass 27, count 0 2006.281.08:05:10.91#ibcon#about to read 3, iclass 27, count 0 2006.281.08:05:10.94#ibcon#read 3, iclass 27, count 0 2006.281.08:05:10.94#ibcon#about to read 4, iclass 27, count 0 2006.281.08:05:10.94#ibcon#read 4, iclass 27, count 0 2006.281.08:05:10.94#ibcon#about to read 5, iclass 27, count 0 2006.281.08:05:10.94#ibcon#read 5, iclass 27, count 0 2006.281.08:05:10.94#ibcon#about to read 6, iclass 27, count 0 2006.281.08:05:10.94#ibcon#read 6, iclass 27, count 0 2006.281.08:05:10.94#ibcon#end of sib2, iclass 27, count 0 2006.281.08:05:10.94#ibcon#*after write, iclass 27, count 0 2006.281.08:05:10.94#ibcon#*before return 0, iclass 27, count 0 2006.281.08:05:10.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:10.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:10.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:05:10.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:05:10.94$vc4f8/valo=6,772.99 2006.281.08:05:10.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:05:10.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:05:10.94#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:10.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:10.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:10.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:10.94#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:05:10.94#ibcon#first serial, iclass 29, count 0 2006.281.08:05:10.94#ibcon#enter sib2, iclass 29, count 0 2006.281.08:05:10.94#ibcon#flushed, iclass 29, count 0 2006.281.08:05:10.94#ibcon#about to write, iclass 29, count 0 2006.281.08:05:10.94#ibcon#wrote, iclass 29, count 0 2006.281.08:05:10.94#ibcon#about to read 3, iclass 29, count 0 2006.281.08:05:10.96#ibcon#read 3, iclass 29, count 0 2006.281.08:05:10.96#ibcon#about to read 4, iclass 29, count 0 2006.281.08:05:10.96#ibcon#read 4, iclass 29, count 0 2006.281.08:05:10.96#ibcon#about to read 5, iclass 29, count 0 2006.281.08:05:10.96#ibcon#read 5, iclass 29, count 0 2006.281.08:05:10.96#ibcon#about to read 6, iclass 29, count 0 2006.281.08:05:10.96#ibcon#read 6, iclass 29, count 0 2006.281.08:05:10.96#ibcon#end of sib2, iclass 29, count 0 2006.281.08:05:10.96#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:05:10.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:05:10.96#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:05:10.96#ibcon#*before write, iclass 29, count 0 2006.281.08:05:10.96#ibcon#enter sib2, iclass 29, count 0 2006.281.08:05:10.96#ibcon#flushed, iclass 29, count 0 2006.281.08:05:10.96#ibcon#about to write, iclass 29, count 0 2006.281.08:05:10.96#ibcon#wrote, iclass 29, count 0 2006.281.08:05:10.96#ibcon#about to read 3, iclass 29, count 0 2006.281.08:05:11.00#ibcon#read 3, iclass 29, count 0 2006.281.08:05:11.00#ibcon#about to read 4, iclass 29, count 0 2006.281.08:05:11.00#ibcon#read 4, iclass 29, count 0 2006.281.08:05:11.00#ibcon#about to read 5, iclass 29, count 0 2006.281.08:05:11.00#ibcon#read 5, iclass 29, count 0 2006.281.08:05:11.00#ibcon#about to read 6, iclass 29, count 0 2006.281.08:05:11.00#ibcon#read 6, iclass 29, count 0 2006.281.08:05:11.00#ibcon#end of sib2, iclass 29, count 0 2006.281.08:05:11.00#ibcon#*after write, iclass 29, count 0 2006.281.08:05:11.00#ibcon#*before return 0, iclass 29, count 0 2006.281.08:05:11.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:11.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:11.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:05:11.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:05:11.00$vc4f8/va=6,6 2006.281.08:05:11.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:05:11.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:05:11.01#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:11.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:11.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:11.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:11.06#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:05:11.06#ibcon#first serial, iclass 31, count 2 2006.281.08:05:11.06#ibcon#enter sib2, iclass 31, count 2 2006.281.08:05:11.06#ibcon#flushed, iclass 31, count 2 2006.281.08:05:11.06#ibcon#about to write, iclass 31, count 2 2006.281.08:05:11.06#ibcon#wrote, iclass 31, count 2 2006.281.08:05:11.06#ibcon#about to read 3, iclass 31, count 2 2006.281.08:05:11.08#ibcon#read 3, iclass 31, count 2 2006.281.08:05:11.08#ibcon#about to read 4, iclass 31, count 2 2006.281.08:05:11.08#ibcon#read 4, iclass 31, count 2 2006.281.08:05:11.08#ibcon#about to read 5, iclass 31, count 2 2006.281.08:05:11.08#ibcon#read 5, iclass 31, count 2 2006.281.08:05:11.08#ibcon#about to read 6, iclass 31, count 2 2006.281.08:05:11.08#ibcon#read 6, iclass 31, count 2 2006.281.08:05:11.08#ibcon#end of sib2, iclass 31, count 2 2006.281.08:05:11.08#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:05:11.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:05:11.08#ibcon#[25=AT06-06\r\n] 2006.281.08:05:11.08#ibcon#*before write, iclass 31, count 2 2006.281.08:05:11.08#ibcon#enter sib2, iclass 31, count 2 2006.281.08:05:11.08#ibcon#flushed, iclass 31, count 2 2006.281.08:05:11.08#ibcon#about to write, iclass 31, count 2 2006.281.08:05:11.08#ibcon#wrote, iclass 31, count 2 2006.281.08:05:11.08#ibcon#about to read 3, iclass 31, count 2 2006.281.08:05:11.11#ibcon#read 3, iclass 31, count 2 2006.281.08:05:11.11#ibcon#about to read 4, iclass 31, count 2 2006.281.08:05:11.11#ibcon#read 4, iclass 31, count 2 2006.281.08:05:11.11#ibcon#about to read 5, iclass 31, count 2 2006.281.08:05:11.11#ibcon#read 5, iclass 31, count 2 2006.281.08:05:11.11#ibcon#about to read 6, iclass 31, count 2 2006.281.08:05:11.11#ibcon#read 6, iclass 31, count 2 2006.281.08:05:11.11#ibcon#end of sib2, iclass 31, count 2 2006.281.08:05:11.11#ibcon#*after write, iclass 31, count 2 2006.281.08:05:11.11#ibcon#*before return 0, iclass 31, count 2 2006.281.08:05:11.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:11.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:11.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:05:11.11#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:11.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:05:11.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:05:11.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:05:11.23#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:05:11.23#ibcon#first serial, iclass 31, count 0 2006.281.08:05:11.23#ibcon#enter sib2, iclass 31, count 0 2006.281.08:05:11.23#ibcon#flushed, iclass 31, count 0 2006.281.08:05:11.23#ibcon#about to write, iclass 31, count 0 2006.281.08:05:11.23#ibcon#wrote, iclass 31, count 0 2006.281.08:05:11.23#ibcon#about to read 3, iclass 31, count 0 2006.281.08:05:11.25#ibcon#read 3, iclass 31, count 0 2006.281.08:05:11.25#ibcon#about to read 4, iclass 31, count 0 2006.281.08:05:11.25#ibcon#read 4, iclass 31, count 0 2006.281.08:05:11.25#ibcon#about to read 5, iclass 31, count 0 2006.281.08:05:11.25#ibcon#read 5, iclass 31, count 0 2006.281.08:05:11.25#ibcon#about to read 6, iclass 31, count 0 2006.281.08:05:11.25#ibcon#read 6, iclass 31, count 0 2006.281.08:05:11.25#ibcon#end of sib2, iclass 31, count 0 2006.281.08:05:11.25#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:05:11.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:05:11.25#ibcon#[25=USB\r\n] 2006.281.08:05:11.25#ibcon#*before write, iclass 31, count 0 2006.281.08:05:11.25#ibcon#enter sib2, iclass 31, count 0 2006.281.08:05:11.25#ibcon#flushed, iclass 31, count 0 2006.281.08:05:11.25#ibcon#about to write, iclass 31, count 0 2006.281.08:05:11.25#ibcon#wrote, iclass 31, count 0 2006.281.08:05:11.25#ibcon#about to read 3, iclass 31, count 0 2006.281.08:05:11.28#ibcon#read 3, iclass 31, count 0 2006.281.08:05:11.28#ibcon#about to read 4, iclass 31, count 0 2006.281.08:05:11.28#ibcon#read 4, iclass 31, count 0 2006.281.08:05:11.28#ibcon#about to read 5, iclass 31, count 0 2006.281.08:05:11.28#ibcon#read 5, iclass 31, count 0 2006.281.08:05:11.28#ibcon#about to read 6, iclass 31, count 0 2006.281.08:05:11.28#ibcon#read 6, iclass 31, count 0 2006.281.08:05:11.28#ibcon#end of sib2, iclass 31, count 0 2006.281.08:05:11.28#ibcon#*after write, iclass 31, count 0 2006.281.08:05:11.28#ibcon#*before return 0, iclass 31, count 0 2006.281.08:05:11.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:05:11.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:05:11.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:05:11.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:05:11.28$vc4f8/valo=7,832.99 2006.281.08:05:11.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:05:11.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:05:11.28#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:11.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:05:11.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:05:11.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:05:11.28#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:05:11.28#ibcon#first serial, iclass 33, count 0 2006.281.08:05:11.28#ibcon#enter sib2, iclass 33, count 0 2006.281.08:05:11.28#ibcon#flushed, iclass 33, count 0 2006.281.08:05:11.28#ibcon#about to write, iclass 33, count 0 2006.281.08:05:11.28#ibcon#wrote, iclass 33, count 0 2006.281.08:05:11.28#ibcon#about to read 3, iclass 33, count 0 2006.281.08:05:11.30#ibcon#read 3, iclass 33, count 0 2006.281.08:05:11.30#ibcon#about to read 4, iclass 33, count 0 2006.281.08:05:11.30#ibcon#read 4, iclass 33, count 0 2006.281.08:05:11.30#ibcon#about to read 5, iclass 33, count 0 2006.281.08:05:11.30#ibcon#read 5, iclass 33, count 0 2006.281.08:05:11.30#ibcon#about to read 6, iclass 33, count 0 2006.281.08:05:11.30#ibcon#read 6, iclass 33, count 0 2006.281.08:05:11.30#ibcon#end of sib2, iclass 33, count 0 2006.281.08:05:11.30#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:05:11.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:05:11.30#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:05:11.30#ibcon#*before write, iclass 33, count 0 2006.281.08:05:11.30#ibcon#enter sib2, iclass 33, count 0 2006.281.08:05:11.30#ibcon#flushed, iclass 33, count 0 2006.281.08:05:11.30#ibcon#about to write, iclass 33, count 0 2006.281.08:05:11.30#ibcon#wrote, iclass 33, count 0 2006.281.08:05:11.30#ibcon#about to read 3, iclass 33, count 0 2006.281.08:05:11.35#ibcon#read 3, iclass 33, count 0 2006.281.08:05:11.35#ibcon#about to read 4, iclass 33, count 0 2006.281.08:05:11.35#ibcon#read 4, iclass 33, count 0 2006.281.08:05:11.35#ibcon#about to read 5, iclass 33, count 0 2006.281.08:05:11.35#ibcon#read 5, iclass 33, count 0 2006.281.08:05:11.35#ibcon#about to read 6, iclass 33, count 0 2006.281.08:05:11.35#ibcon#read 6, iclass 33, count 0 2006.281.08:05:11.35#ibcon#end of sib2, iclass 33, count 0 2006.281.08:05:11.35#ibcon#*after write, iclass 33, count 0 2006.281.08:05:11.35#ibcon#*before return 0, iclass 33, count 0 2006.281.08:05:11.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:05:11.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:05:11.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:05:11.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:05:11.35$vc4f8/va=7,6 2006.281.08:05:11.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:05:11.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:05:11.35#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:11.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:05:11.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:05:11.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:05:11.40#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:05:11.40#ibcon#first serial, iclass 35, count 2 2006.281.08:05:11.40#ibcon#enter sib2, iclass 35, count 2 2006.281.08:05:11.40#ibcon#flushed, iclass 35, count 2 2006.281.08:05:11.40#ibcon#about to write, iclass 35, count 2 2006.281.08:05:11.40#ibcon#wrote, iclass 35, count 2 2006.281.08:05:11.40#ibcon#about to read 3, iclass 35, count 2 2006.281.08:05:11.42#ibcon#read 3, iclass 35, count 2 2006.281.08:05:11.42#ibcon#about to read 4, iclass 35, count 2 2006.281.08:05:11.42#ibcon#read 4, iclass 35, count 2 2006.281.08:05:11.42#ibcon#about to read 5, iclass 35, count 2 2006.281.08:05:11.42#ibcon#read 5, iclass 35, count 2 2006.281.08:05:11.42#ibcon#about to read 6, iclass 35, count 2 2006.281.08:05:11.42#ibcon#read 6, iclass 35, count 2 2006.281.08:05:11.42#ibcon#end of sib2, iclass 35, count 2 2006.281.08:05:11.42#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:05:11.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:05:11.42#ibcon#[25=AT07-06\r\n] 2006.281.08:05:11.42#ibcon#*before write, iclass 35, count 2 2006.281.08:05:11.42#ibcon#enter sib2, iclass 35, count 2 2006.281.08:05:11.42#ibcon#flushed, iclass 35, count 2 2006.281.08:05:11.42#ibcon#about to write, iclass 35, count 2 2006.281.08:05:11.42#ibcon#wrote, iclass 35, count 2 2006.281.08:05:11.42#ibcon#about to read 3, iclass 35, count 2 2006.281.08:05:11.45#ibcon#read 3, iclass 35, count 2 2006.281.08:05:11.45#ibcon#about to read 4, iclass 35, count 2 2006.281.08:05:11.45#ibcon#read 4, iclass 35, count 2 2006.281.08:05:11.45#ibcon#about to read 5, iclass 35, count 2 2006.281.08:05:11.45#ibcon#read 5, iclass 35, count 2 2006.281.08:05:11.45#ibcon#about to read 6, iclass 35, count 2 2006.281.08:05:11.45#ibcon#read 6, iclass 35, count 2 2006.281.08:05:11.45#ibcon#end of sib2, iclass 35, count 2 2006.281.08:05:11.45#ibcon#*after write, iclass 35, count 2 2006.281.08:05:11.45#ibcon#*before return 0, iclass 35, count 2 2006.281.08:05:11.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:05:11.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:05:11.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:05:11.45#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:11.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:05:11.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:05:11.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:05:11.57#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:05:11.57#ibcon#first serial, iclass 35, count 0 2006.281.08:05:11.57#ibcon#enter sib2, iclass 35, count 0 2006.281.08:05:11.57#ibcon#flushed, iclass 35, count 0 2006.281.08:05:11.57#ibcon#about to write, iclass 35, count 0 2006.281.08:05:11.57#ibcon#wrote, iclass 35, count 0 2006.281.08:05:11.57#ibcon#about to read 3, iclass 35, count 0 2006.281.08:05:11.59#ibcon#read 3, iclass 35, count 0 2006.281.08:05:11.59#ibcon#about to read 4, iclass 35, count 0 2006.281.08:05:11.59#ibcon#read 4, iclass 35, count 0 2006.281.08:05:11.59#ibcon#about to read 5, iclass 35, count 0 2006.281.08:05:11.59#ibcon#read 5, iclass 35, count 0 2006.281.08:05:11.59#ibcon#about to read 6, iclass 35, count 0 2006.281.08:05:11.59#ibcon#read 6, iclass 35, count 0 2006.281.08:05:11.59#ibcon#end of sib2, iclass 35, count 0 2006.281.08:05:11.59#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:05:11.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:05:11.59#ibcon#[25=USB\r\n] 2006.281.08:05:11.59#ibcon#*before write, iclass 35, count 0 2006.281.08:05:11.59#ibcon#enter sib2, iclass 35, count 0 2006.281.08:05:11.59#ibcon#flushed, iclass 35, count 0 2006.281.08:05:11.59#ibcon#about to write, iclass 35, count 0 2006.281.08:05:11.59#ibcon#wrote, iclass 35, count 0 2006.281.08:05:11.59#ibcon#about to read 3, iclass 35, count 0 2006.281.08:05:11.62#ibcon#read 3, iclass 35, count 0 2006.281.08:05:11.62#ibcon#about to read 4, iclass 35, count 0 2006.281.08:05:11.62#ibcon#read 4, iclass 35, count 0 2006.281.08:05:11.62#ibcon#about to read 5, iclass 35, count 0 2006.281.08:05:11.62#ibcon#read 5, iclass 35, count 0 2006.281.08:05:11.62#ibcon#about to read 6, iclass 35, count 0 2006.281.08:05:11.62#ibcon#read 6, iclass 35, count 0 2006.281.08:05:11.62#ibcon#end of sib2, iclass 35, count 0 2006.281.08:05:11.62#ibcon#*after write, iclass 35, count 0 2006.281.08:05:11.62#ibcon#*before return 0, iclass 35, count 0 2006.281.08:05:11.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:05:11.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:05:11.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:05:11.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:05:11.62$vc4f8/valo=8,852.99 2006.281.08:05:11.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:05:11.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:05:11.62#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:11.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:05:11.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:05:11.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:05:11.62#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:05:11.62#ibcon#first serial, iclass 37, count 0 2006.281.08:05:11.62#ibcon#enter sib2, iclass 37, count 0 2006.281.08:05:11.62#ibcon#flushed, iclass 37, count 0 2006.281.08:05:11.62#ibcon#about to write, iclass 37, count 0 2006.281.08:05:11.62#ibcon#wrote, iclass 37, count 0 2006.281.08:05:11.62#ibcon#about to read 3, iclass 37, count 0 2006.281.08:05:11.64#ibcon#read 3, iclass 37, count 0 2006.281.08:05:11.64#ibcon#about to read 4, iclass 37, count 0 2006.281.08:05:11.64#ibcon#read 4, iclass 37, count 0 2006.281.08:05:11.64#ibcon#about to read 5, iclass 37, count 0 2006.281.08:05:11.64#ibcon#read 5, iclass 37, count 0 2006.281.08:05:11.64#ibcon#about to read 6, iclass 37, count 0 2006.281.08:05:11.64#ibcon#read 6, iclass 37, count 0 2006.281.08:05:11.64#ibcon#end of sib2, iclass 37, count 0 2006.281.08:05:11.64#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:05:11.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:05:11.64#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:05:11.64#ibcon#*before write, iclass 37, count 0 2006.281.08:05:11.64#ibcon#enter sib2, iclass 37, count 0 2006.281.08:05:11.64#ibcon#flushed, iclass 37, count 0 2006.281.08:05:11.64#ibcon#about to write, iclass 37, count 0 2006.281.08:05:11.64#ibcon#wrote, iclass 37, count 0 2006.281.08:05:11.64#ibcon#about to read 3, iclass 37, count 0 2006.281.08:05:11.68#ibcon#read 3, iclass 37, count 0 2006.281.08:05:11.68#ibcon#about to read 4, iclass 37, count 0 2006.281.08:05:11.68#ibcon#read 4, iclass 37, count 0 2006.281.08:05:11.68#ibcon#about to read 5, iclass 37, count 0 2006.281.08:05:11.68#ibcon#read 5, iclass 37, count 0 2006.281.08:05:11.68#ibcon#about to read 6, iclass 37, count 0 2006.281.08:05:11.68#ibcon#read 6, iclass 37, count 0 2006.281.08:05:11.68#ibcon#end of sib2, iclass 37, count 0 2006.281.08:05:11.68#ibcon#*after write, iclass 37, count 0 2006.281.08:05:11.68#ibcon#*before return 0, iclass 37, count 0 2006.281.08:05:11.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:05:11.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:05:11.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:05:11.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:05:11.68$vc4f8/va=8,6 2006.281.08:05:11.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.08:05:11.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.08:05:11.68#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:11.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:05:11.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:05:11.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:05:11.74#ibcon#enter wrdev, iclass 39, count 2 2006.281.08:05:11.74#ibcon#first serial, iclass 39, count 2 2006.281.08:05:11.74#ibcon#enter sib2, iclass 39, count 2 2006.281.08:05:11.74#ibcon#flushed, iclass 39, count 2 2006.281.08:05:11.74#ibcon#about to write, iclass 39, count 2 2006.281.08:05:11.74#ibcon#wrote, iclass 39, count 2 2006.281.08:05:11.74#ibcon#about to read 3, iclass 39, count 2 2006.281.08:05:11.76#ibcon#read 3, iclass 39, count 2 2006.281.08:05:11.76#ibcon#about to read 4, iclass 39, count 2 2006.281.08:05:11.76#ibcon#read 4, iclass 39, count 2 2006.281.08:05:11.76#ibcon#about to read 5, iclass 39, count 2 2006.281.08:05:11.76#ibcon#read 5, iclass 39, count 2 2006.281.08:05:11.76#ibcon#about to read 6, iclass 39, count 2 2006.281.08:05:11.76#ibcon#read 6, iclass 39, count 2 2006.281.08:05:11.76#ibcon#end of sib2, iclass 39, count 2 2006.281.08:05:11.76#ibcon#*mode == 0, iclass 39, count 2 2006.281.08:05:11.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.08:05:11.76#ibcon#[25=AT08-06\r\n] 2006.281.08:05:11.76#ibcon#*before write, iclass 39, count 2 2006.281.08:05:11.76#ibcon#enter sib2, iclass 39, count 2 2006.281.08:05:11.76#ibcon#flushed, iclass 39, count 2 2006.281.08:05:11.76#ibcon#about to write, iclass 39, count 2 2006.281.08:05:11.76#ibcon#wrote, iclass 39, count 2 2006.281.08:05:11.76#ibcon#about to read 3, iclass 39, count 2 2006.281.08:05:11.79#ibcon#read 3, iclass 39, count 2 2006.281.08:05:11.79#ibcon#about to read 4, iclass 39, count 2 2006.281.08:05:11.79#ibcon#read 4, iclass 39, count 2 2006.281.08:05:11.79#ibcon#about to read 5, iclass 39, count 2 2006.281.08:05:11.79#ibcon#read 5, iclass 39, count 2 2006.281.08:05:11.79#ibcon#about to read 6, iclass 39, count 2 2006.281.08:05:11.79#ibcon#read 6, iclass 39, count 2 2006.281.08:05:11.79#ibcon#end of sib2, iclass 39, count 2 2006.281.08:05:11.79#ibcon#*after write, iclass 39, count 2 2006.281.08:05:11.79#ibcon#*before return 0, iclass 39, count 2 2006.281.08:05:11.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:05:11.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:05:11.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.08:05:11.79#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:11.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:05:11.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:05:11.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:05:11.91#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:05:11.91#ibcon#first serial, iclass 39, count 0 2006.281.08:05:11.91#ibcon#enter sib2, iclass 39, count 0 2006.281.08:05:11.91#ibcon#flushed, iclass 39, count 0 2006.281.08:05:11.91#ibcon#about to write, iclass 39, count 0 2006.281.08:05:11.91#ibcon#wrote, iclass 39, count 0 2006.281.08:05:11.91#ibcon#about to read 3, iclass 39, count 0 2006.281.08:05:11.93#ibcon#read 3, iclass 39, count 0 2006.281.08:05:11.93#ibcon#about to read 4, iclass 39, count 0 2006.281.08:05:11.93#ibcon#read 4, iclass 39, count 0 2006.281.08:05:11.93#ibcon#about to read 5, iclass 39, count 0 2006.281.08:05:11.93#ibcon#read 5, iclass 39, count 0 2006.281.08:05:11.93#ibcon#about to read 6, iclass 39, count 0 2006.281.08:05:11.93#ibcon#read 6, iclass 39, count 0 2006.281.08:05:11.93#ibcon#end of sib2, iclass 39, count 0 2006.281.08:05:11.93#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:05:11.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:05:11.93#ibcon#[25=USB\r\n] 2006.281.08:05:11.93#ibcon#*before write, iclass 39, count 0 2006.281.08:05:11.93#ibcon#enter sib2, iclass 39, count 0 2006.281.08:05:11.93#ibcon#flushed, iclass 39, count 0 2006.281.08:05:11.93#ibcon#about to write, iclass 39, count 0 2006.281.08:05:11.93#ibcon#wrote, iclass 39, count 0 2006.281.08:05:11.93#ibcon#about to read 3, iclass 39, count 0 2006.281.08:05:11.96#ibcon#read 3, iclass 39, count 0 2006.281.08:05:11.96#ibcon#about to read 4, iclass 39, count 0 2006.281.08:05:11.96#ibcon#read 4, iclass 39, count 0 2006.281.08:05:11.96#ibcon#about to read 5, iclass 39, count 0 2006.281.08:05:11.96#ibcon#read 5, iclass 39, count 0 2006.281.08:05:11.96#ibcon#about to read 6, iclass 39, count 0 2006.281.08:05:11.96#ibcon#read 6, iclass 39, count 0 2006.281.08:05:11.96#ibcon#end of sib2, iclass 39, count 0 2006.281.08:05:11.96#ibcon#*after write, iclass 39, count 0 2006.281.08:05:11.96#ibcon#*before return 0, iclass 39, count 0 2006.281.08:05:11.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:05:11.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:05:11.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:05:11.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:05:11.96$vc4f8/vblo=1,632.99 2006.281.08:05:11.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.08:05:11.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.08:05:11.96#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:11.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:05:11.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:05:11.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:05:11.96#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:05:11.96#ibcon#first serial, iclass 3, count 0 2006.281.08:05:11.96#ibcon#enter sib2, iclass 3, count 0 2006.281.08:05:11.96#ibcon#flushed, iclass 3, count 0 2006.281.08:05:11.96#ibcon#about to write, iclass 3, count 0 2006.281.08:05:11.96#ibcon#wrote, iclass 3, count 0 2006.281.08:05:11.96#ibcon#about to read 3, iclass 3, count 0 2006.281.08:05:11.98#ibcon#read 3, iclass 3, count 0 2006.281.08:05:11.98#ibcon#about to read 4, iclass 3, count 0 2006.281.08:05:11.98#ibcon#read 4, iclass 3, count 0 2006.281.08:05:11.98#ibcon#about to read 5, iclass 3, count 0 2006.281.08:05:11.98#ibcon#read 5, iclass 3, count 0 2006.281.08:05:11.98#ibcon#about to read 6, iclass 3, count 0 2006.281.08:05:11.98#ibcon#read 6, iclass 3, count 0 2006.281.08:05:11.98#ibcon#end of sib2, iclass 3, count 0 2006.281.08:05:11.98#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:05:11.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:05:11.98#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:05:11.98#ibcon#*before write, iclass 3, count 0 2006.281.08:05:11.98#ibcon#enter sib2, iclass 3, count 0 2006.281.08:05:11.98#ibcon#flushed, iclass 3, count 0 2006.281.08:05:11.98#ibcon#about to write, iclass 3, count 0 2006.281.08:05:11.98#ibcon#wrote, iclass 3, count 0 2006.281.08:05:11.98#ibcon#about to read 3, iclass 3, count 0 2006.281.08:05:12.02#ibcon#read 3, iclass 3, count 0 2006.281.08:05:12.02#ibcon#about to read 4, iclass 3, count 0 2006.281.08:05:12.02#ibcon#read 4, iclass 3, count 0 2006.281.08:05:12.02#ibcon#about to read 5, iclass 3, count 0 2006.281.08:05:12.02#ibcon#read 5, iclass 3, count 0 2006.281.08:05:12.02#ibcon#about to read 6, iclass 3, count 0 2006.281.08:05:12.02#ibcon#read 6, iclass 3, count 0 2006.281.08:05:12.02#ibcon#end of sib2, iclass 3, count 0 2006.281.08:05:12.02#ibcon#*after write, iclass 3, count 0 2006.281.08:05:12.02#ibcon#*before return 0, iclass 3, count 0 2006.281.08:05:12.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:05:12.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:05:12.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:05:12.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:05:12.02$vc4f8/vb=1,4 2006.281.08:05:12.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.08:05:12.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.08:05:12.03#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:12.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:05:12.03#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:05:12.03#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:05:12.03#ibcon#enter wrdev, iclass 5, count 2 2006.281.08:05:12.03#ibcon#first serial, iclass 5, count 2 2006.281.08:05:12.03#ibcon#enter sib2, iclass 5, count 2 2006.281.08:05:12.03#ibcon#flushed, iclass 5, count 2 2006.281.08:05:12.03#ibcon#about to write, iclass 5, count 2 2006.281.08:05:12.03#ibcon#wrote, iclass 5, count 2 2006.281.08:05:12.03#ibcon#about to read 3, iclass 5, count 2 2006.281.08:05:12.05#ibcon#read 3, iclass 5, count 2 2006.281.08:05:12.05#ibcon#about to read 4, iclass 5, count 2 2006.281.08:05:12.05#ibcon#read 4, iclass 5, count 2 2006.281.08:05:12.05#ibcon#about to read 5, iclass 5, count 2 2006.281.08:05:12.05#ibcon#read 5, iclass 5, count 2 2006.281.08:05:12.05#ibcon#about to read 6, iclass 5, count 2 2006.281.08:05:12.05#ibcon#read 6, iclass 5, count 2 2006.281.08:05:12.05#ibcon#end of sib2, iclass 5, count 2 2006.281.08:05:12.05#ibcon#*mode == 0, iclass 5, count 2 2006.281.08:05:12.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.08:05:12.05#ibcon#[27=AT01-04\r\n] 2006.281.08:05:12.05#ibcon#*before write, iclass 5, count 2 2006.281.08:05:12.05#ibcon#enter sib2, iclass 5, count 2 2006.281.08:05:12.05#ibcon#flushed, iclass 5, count 2 2006.281.08:05:12.05#ibcon#about to write, iclass 5, count 2 2006.281.08:05:12.05#ibcon#wrote, iclass 5, count 2 2006.281.08:05:12.05#ibcon#about to read 3, iclass 5, count 2 2006.281.08:05:12.08#ibcon#read 3, iclass 5, count 2 2006.281.08:05:12.08#ibcon#about to read 4, iclass 5, count 2 2006.281.08:05:12.08#ibcon#read 4, iclass 5, count 2 2006.281.08:05:12.08#ibcon#about to read 5, iclass 5, count 2 2006.281.08:05:12.08#ibcon#read 5, iclass 5, count 2 2006.281.08:05:12.08#ibcon#about to read 6, iclass 5, count 2 2006.281.08:05:12.08#ibcon#read 6, iclass 5, count 2 2006.281.08:05:12.08#ibcon#end of sib2, iclass 5, count 2 2006.281.08:05:12.08#ibcon#*after write, iclass 5, count 2 2006.281.08:05:12.08#ibcon#*before return 0, iclass 5, count 2 2006.281.08:05:12.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:05:12.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:05:12.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.08:05:12.08#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:12.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:05:12.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:05:12.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:05:12.20#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:05:12.20#ibcon#first serial, iclass 5, count 0 2006.281.08:05:12.20#ibcon#enter sib2, iclass 5, count 0 2006.281.08:05:12.20#ibcon#flushed, iclass 5, count 0 2006.281.08:05:12.20#ibcon#about to write, iclass 5, count 0 2006.281.08:05:12.20#ibcon#wrote, iclass 5, count 0 2006.281.08:05:12.20#ibcon#about to read 3, iclass 5, count 0 2006.281.08:05:12.22#ibcon#read 3, iclass 5, count 0 2006.281.08:05:12.22#ibcon#about to read 4, iclass 5, count 0 2006.281.08:05:12.22#ibcon#read 4, iclass 5, count 0 2006.281.08:05:12.22#ibcon#about to read 5, iclass 5, count 0 2006.281.08:05:12.22#ibcon#read 5, iclass 5, count 0 2006.281.08:05:12.22#ibcon#about to read 6, iclass 5, count 0 2006.281.08:05:12.22#ibcon#read 6, iclass 5, count 0 2006.281.08:05:12.22#ibcon#end of sib2, iclass 5, count 0 2006.281.08:05:12.22#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:05:12.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:05:12.22#ibcon#[27=USB\r\n] 2006.281.08:05:12.22#ibcon#*before write, iclass 5, count 0 2006.281.08:05:12.22#ibcon#enter sib2, iclass 5, count 0 2006.281.08:05:12.22#ibcon#flushed, iclass 5, count 0 2006.281.08:05:12.22#ibcon#about to write, iclass 5, count 0 2006.281.08:05:12.22#ibcon#wrote, iclass 5, count 0 2006.281.08:05:12.22#ibcon#about to read 3, iclass 5, count 0 2006.281.08:05:12.25#ibcon#read 3, iclass 5, count 0 2006.281.08:05:12.25#ibcon#about to read 4, iclass 5, count 0 2006.281.08:05:12.25#ibcon#read 4, iclass 5, count 0 2006.281.08:05:12.25#ibcon#about to read 5, iclass 5, count 0 2006.281.08:05:12.25#ibcon#read 5, iclass 5, count 0 2006.281.08:05:12.25#ibcon#about to read 6, iclass 5, count 0 2006.281.08:05:12.25#ibcon#read 6, iclass 5, count 0 2006.281.08:05:12.25#ibcon#end of sib2, iclass 5, count 0 2006.281.08:05:12.25#ibcon#*after write, iclass 5, count 0 2006.281.08:05:12.25#ibcon#*before return 0, iclass 5, count 0 2006.281.08:05:12.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:05:12.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:05:12.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:05:12.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:05:12.25$vc4f8/vblo=2,640.99 2006.281.08:05:12.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:05:12.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:05:12.25#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:12.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:12.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:12.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:12.25#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:05:12.25#ibcon#first serial, iclass 7, count 0 2006.281.08:05:12.25#ibcon#enter sib2, iclass 7, count 0 2006.281.08:05:12.25#ibcon#flushed, iclass 7, count 0 2006.281.08:05:12.25#ibcon#about to write, iclass 7, count 0 2006.281.08:05:12.25#ibcon#wrote, iclass 7, count 0 2006.281.08:05:12.25#ibcon#about to read 3, iclass 7, count 0 2006.281.08:05:12.27#ibcon#read 3, iclass 7, count 0 2006.281.08:05:12.27#ibcon#about to read 4, iclass 7, count 0 2006.281.08:05:12.27#ibcon#read 4, iclass 7, count 0 2006.281.08:05:12.27#ibcon#about to read 5, iclass 7, count 0 2006.281.08:05:12.27#ibcon#read 5, iclass 7, count 0 2006.281.08:05:12.27#ibcon#about to read 6, iclass 7, count 0 2006.281.08:05:12.27#ibcon#read 6, iclass 7, count 0 2006.281.08:05:12.27#ibcon#end of sib2, iclass 7, count 0 2006.281.08:05:12.27#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:05:12.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:05:12.27#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:05:12.27#ibcon#*before write, iclass 7, count 0 2006.281.08:05:12.27#ibcon#enter sib2, iclass 7, count 0 2006.281.08:05:12.27#ibcon#flushed, iclass 7, count 0 2006.281.08:05:12.27#ibcon#about to write, iclass 7, count 0 2006.281.08:05:12.27#ibcon#wrote, iclass 7, count 0 2006.281.08:05:12.27#ibcon#about to read 3, iclass 7, count 0 2006.281.08:05:12.31#ibcon#read 3, iclass 7, count 0 2006.281.08:05:12.31#ibcon#about to read 4, iclass 7, count 0 2006.281.08:05:12.31#ibcon#read 4, iclass 7, count 0 2006.281.08:05:12.31#ibcon#about to read 5, iclass 7, count 0 2006.281.08:05:12.31#ibcon#read 5, iclass 7, count 0 2006.281.08:05:12.31#ibcon#about to read 6, iclass 7, count 0 2006.281.08:05:12.31#ibcon#read 6, iclass 7, count 0 2006.281.08:05:12.31#ibcon#end of sib2, iclass 7, count 0 2006.281.08:05:12.31#ibcon#*after write, iclass 7, count 0 2006.281.08:05:12.31#ibcon#*before return 0, iclass 7, count 0 2006.281.08:05:12.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:12.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:05:12.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:05:12.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:05:12.31$vc4f8/vb=2,5 2006.281.08:05:12.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:05:12.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:05:12.31#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:12.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:12.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:12.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:12.37#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:05:12.37#ibcon#first serial, iclass 11, count 2 2006.281.08:05:12.37#ibcon#enter sib2, iclass 11, count 2 2006.281.08:05:12.37#ibcon#flushed, iclass 11, count 2 2006.281.08:05:12.37#ibcon#about to write, iclass 11, count 2 2006.281.08:05:12.37#ibcon#wrote, iclass 11, count 2 2006.281.08:05:12.37#ibcon#about to read 3, iclass 11, count 2 2006.281.08:05:12.39#ibcon#read 3, iclass 11, count 2 2006.281.08:05:12.39#ibcon#about to read 4, iclass 11, count 2 2006.281.08:05:12.39#ibcon#read 4, iclass 11, count 2 2006.281.08:05:12.39#ibcon#about to read 5, iclass 11, count 2 2006.281.08:05:12.39#ibcon#read 5, iclass 11, count 2 2006.281.08:05:12.39#ibcon#about to read 6, iclass 11, count 2 2006.281.08:05:12.39#ibcon#read 6, iclass 11, count 2 2006.281.08:05:12.39#ibcon#end of sib2, iclass 11, count 2 2006.281.08:05:12.39#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:05:12.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:05:12.39#ibcon#[27=AT02-05\r\n] 2006.281.08:05:12.39#ibcon#*before write, iclass 11, count 2 2006.281.08:05:12.39#ibcon#enter sib2, iclass 11, count 2 2006.281.08:05:12.39#ibcon#flushed, iclass 11, count 2 2006.281.08:05:12.39#ibcon#about to write, iclass 11, count 2 2006.281.08:05:12.39#ibcon#wrote, iclass 11, count 2 2006.281.08:05:12.39#ibcon#about to read 3, iclass 11, count 2 2006.281.08:05:12.42#ibcon#read 3, iclass 11, count 2 2006.281.08:05:12.42#ibcon#about to read 4, iclass 11, count 2 2006.281.08:05:12.42#ibcon#read 4, iclass 11, count 2 2006.281.08:05:12.42#ibcon#about to read 5, iclass 11, count 2 2006.281.08:05:12.42#ibcon#read 5, iclass 11, count 2 2006.281.08:05:12.42#ibcon#about to read 6, iclass 11, count 2 2006.281.08:05:12.42#ibcon#read 6, iclass 11, count 2 2006.281.08:05:12.42#ibcon#end of sib2, iclass 11, count 2 2006.281.08:05:12.42#ibcon#*after write, iclass 11, count 2 2006.281.08:05:12.42#ibcon#*before return 0, iclass 11, count 2 2006.281.08:05:12.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:12.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:05:12.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:05:12.42#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:12.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:12.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:12.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:12.54#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:05:12.54#ibcon#first serial, iclass 11, count 0 2006.281.08:05:12.54#ibcon#enter sib2, iclass 11, count 0 2006.281.08:05:12.54#ibcon#flushed, iclass 11, count 0 2006.281.08:05:12.54#ibcon#about to write, iclass 11, count 0 2006.281.08:05:12.54#ibcon#wrote, iclass 11, count 0 2006.281.08:05:12.54#ibcon#about to read 3, iclass 11, count 0 2006.281.08:05:12.56#ibcon#read 3, iclass 11, count 0 2006.281.08:05:12.56#ibcon#about to read 4, iclass 11, count 0 2006.281.08:05:12.56#ibcon#read 4, iclass 11, count 0 2006.281.08:05:12.56#ibcon#about to read 5, iclass 11, count 0 2006.281.08:05:12.56#ibcon#read 5, iclass 11, count 0 2006.281.08:05:12.56#ibcon#about to read 6, iclass 11, count 0 2006.281.08:05:12.56#ibcon#read 6, iclass 11, count 0 2006.281.08:05:12.56#ibcon#end of sib2, iclass 11, count 0 2006.281.08:05:12.56#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:05:12.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:05:12.56#ibcon#[27=USB\r\n] 2006.281.08:05:12.56#ibcon#*before write, iclass 11, count 0 2006.281.08:05:12.56#ibcon#enter sib2, iclass 11, count 0 2006.281.08:05:12.56#ibcon#flushed, iclass 11, count 0 2006.281.08:05:12.56#ibcon#about to write, iclass 11, count 0 2006.281.08:05:12.56#ibcon#wrote, iclass 11, count 0 2006.281.08:05:12.56#ibcon#about to read 3, iclass 11, count 0 2006.281.08:05:12.59#ibcon#read 3, iclass 11, count 0 2006.281.08:05:12.59#ibcon#about to read 4, iclass 11, count 0 2006.281.08:05:12.59#ibcon#read 4, iclass 11, count 0 2006.281.08:05:12.59#ibcon#about to read 5, iclass 11, count 0 2006.281.08:05:12.59#ibcon#read 5, iclass 11, count 0 2006.281.08:05:12.59#ibcon#about to read 6, iclass 11, count 0 2006.281.08:05:12.59#ibcon#read 6, iclass 11, count 0 2006.281.08:05:12.59#ibcon#end of sib2, iclass 11, count 0 2006.281.08:05:12.59#ibcon#*after write, iclass 11, count 0 2006.281.08:05:12.59#ibcon#*before return 0, iclass 11, count 0 2006.281.08:05:12.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:12.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:05:12.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:05:12.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:05:12.59$vc4f8/vblo=3,656.99 2006.281.08:05:12.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:05:12.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:05:12.59#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:12.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:12.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:12.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:12.59#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:05:12.59#ibcon#first serial, iclass 13, count 0 2006.281.08:05:12.59#ibcon#enter sib2, iclass 13, count 0 2006.281.08:05:12.59#ibcon#flushed, iclass 13, count 0 2006.281.08:05:12.59#ibcon#about to write, iclass 13, count 0 2006.281.08:05:12.59#ibcon#wrote, iclass 13, count 0 2006.281.08:05:12.59#ibcon#about to read 3, iclass 13, count 0 2006.281.08:05:12.61#ibcon#read 3, iclass 13, count 0 2006.281.08:05:12.61#ibcon#about to read 4, iclass 13, count 0 2006.281.08:05:12.61#ibcon#read 4, iclass 13, count 0 2006.281.08:05:12.61#ibcon#about to read 5, iclass 13, count 0 2006.281.08:05:12.61#ibcon#read 5, iclass 13, count 0 2006.281.08:05:12.61#ibcon#about to read 6, iclass 13, count 0 2006.281.08:05:12.61#ibcon#read 6, iclass 13, count 0 2006.281.08:05:12.61#ibcon#end of sib2, iclass 13, count 0 2006.281.08:05:12.61#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:05:12.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:05:12.61#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:05:12.61#ibcon#*before write, iclass 13, count 0 2006.281.08:05:12.61#ibcon#enter sib2, iclass 13, count 0 2006.281.08:05:12.61#ibcon#flushed, iclass 13, count 0 2006.281.08:05:12.61#ibcon#about to write, iclass 13, count 0 2006.281.08:05:12.61#ibcon#wrote, iclass 13, count 0 2006.281.08:05:12.61#ibcon#about to read 3, iclass 13, count 0 2006.281.08:05:12.65#ibcon#read 3, iclass 13, count 0 2006.281.08:05:12.65#ibcon#about to read 4, iclass 13, count 0 2006.281.08:05:12.65#ibcon#read 4, iclass 13, count 0 2006.281.08:05:12.65#ibcon#about to read 5, iclass 13, count 0 2006.281.08:05:12.65#ibcon#read 5, iclass 13, count 0 2006.281.08:05:12.65#ibcon#about to read 6, iclass 13, count 0 2006.281.08:05:12.65#ibcon#read 6, iclass 13, count 0 2006.281.08:05:12.65#ibcon#end of sib2, iclass 13, count 0 2006.281.08:05:12.65#ibcon#*after write, iclass 13, count 0 2006.281.08:05:12.65#ibcon#*before return 0, iclass 13, count 0 2006.281.08:05:12.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:12.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:05:12.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:05:12.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:05:12.65$vc4f8/vb=3,4 2006.281.08:05:12.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:05:12.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:05:12.66#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:12.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:12.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:12.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:12.71#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:05:12.71#ibcon#first serial, iclass 15, count 2 2006.281.08:05:12.71#ibcon#enter sib2, iclass 15, count 2 2006.281.08:05:12.71#ibcon#flushed, iclass 15, count 2 2006.281.08:05:12.71#ibcon#about to write, iclass 15, count 2 2006.281.08:05:12.71#ibcon#wrote, iclass 15, count 2 2006.281.08:05:12.71#ibcon#about to read 3, iclass 15, count 2 2006.281.08:05:12.73#ibcon#read 3, iclass 15, count 2 2006.281.08:05:12.73#ibcon#about to read 4, iclass 15, count 2 2006.281.08:05:12.73#ibcon#read 4, iclass 15, count 2 2006.281.08:05:12.73#ibcon#about to read 5, iclass 15, count 2 2006.281.08:05:12.73#ibcon#read 5, iclass 15, count 2 2006.281.08:05:12.73#ibcon#about to read 6, iclass 15, count 2 2006.281.08:05:12.73#ibcon#read 6, iclass 15, count 2 2006.281.08:05:12.73#ibcon#end of sib2, iclass 15, count 2 2006.281.08:05:12.73#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:05:12.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:05:12.73#ibcon#[27=AT03-04\r\n] 2006.281.08:05:12.73#ibcon#*before write, iclass 15, count 2 2006.281.08:05:12.73#ibcon#enter sib2, iclass 15, count 2 2006.281.08:05:12.73#ibcon#flushed, iclass 15, count 2 2006.281.08:05:12.73#ibcon#about to write, iclass 15, count 2 2006.281.08:05:12.73#ibcon#wrote, iclass 15, count 2 2006.281.08:05:12.73#ibcon#about to read 3, iclass 15, count 2 2006.281.08:05:12.77#ibcon#read 3, iclass 15, count 2 2006.281.08:05:12.77#ibcon#about to read 4, iclass 15, count 2 2006.281.08:05:12.77#ibcon#read 4, iclass 15, count 2 2006.281.08:05:12.77#ibcon#about to read 5, iclass 15, count 2 2006.281.08:05:12.77#ibcon#read 5, iclass 15, count 2 2006.281.08:05:12.77#ibcon#about to read 6, iclass 15, count 2 2006.281.08:05:12.77#ibcon#read 6, iclass 15, count 2 2006.281.08:05:12.77#ibcon#end of sib2, iclass 15, count 2 2006.281.08:05:12.77#ibcon#*after write, iclass 15, count 2 2006.281.08:05:12.77#ibcon#*before return 0, iclass 15, count 2 2006.281.08:05:12.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:12.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:05:12.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:05:12.77#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:12.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:12.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:12.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:12.89#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:05:12.89#ibcon#first serial, iclass 15, count 0 2006.281.08:05:12.89#ibcon#enter sib2, iclass 15, count 0 2006.281.08:05:12.89#ibcon#flushed, iclass 15, count 0 2006.281.08:05:12.89#ibcon#about to write, iclass 15, count 0 2006.281.08:05:12.89#ibcon#wrote, iclass 15, count 0 2006.281.08:05:12.89#ibcon#about to read 3, iclass 15, count 0 2006.281.08:05:12.91#ibcon#read 3, iclass 15, count 0 2006.281.08:05:12.91#ibcon#about to read 4, iclass 15, count 0 2006.281.08:05:12.91#ibcon#read 4, iclass 15, count 0 2006.281.08:05:12.91#ibcon#about to read 5, iclass 15, count 0 2006.281.08:05:12.91#ibcon#read 5, iclass 15, count 0 2006.281.08:05:12.91#ibcon#about to read 6, iclass 15, count 0 2006.281.08:05:12.91#ibcon#read 6, iclass 15, count 0 2006.281.08:05:12.91#ibcon#end of sib2, iclass 15, count 0 2006.281.08:05:12.91#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:05:12.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:05:12.91#ibcon#[27=USB\r\n] 2006.281.08:05:12.91#ibcon#*before write, iclass 15, count 0 2006.281.08:05:12.91#ibcon#enter sib2, iclass 15, count 0 2006.281.08:05:12.91#ibcon#flushed, iclass 15, count 0 2006.281.08:05:12.91#ibcon#about to write, iclass 15, count 0 2006.281.08:05:12.91#ibcon#wrote, iclass 15, count 0 2006.281.08:05:12.91#ibcon#about to read 3, iclass 15, count 0 2006.281.08:05:12.94#ibcon#read 3, iclass 15, count 0 2006.281.08:05:12.94#ibcon#about to read 4, iclass 15, count 0 2006.281.08:05:12.94#ibcon#read 4, iclass 15, count 0 2006.281.08:05:12.94#ibcon#about to read 5, iclass 15, count 0 2006.281.08:05:12.94#ibcon#read 5, iclass 15, count 0 2006.281.08:05:12.94#ibcon#about to read 6, iclass 15, count 0 2006.281.08:05:12.94#ibcon#read 6, iclass 15, count 0 2006.281.08:05:12.94#ibcon#end of sib2, iclass 15, count 0 2006.281.08:05:12.94#ibcon#*after write, iclass 15, count 0 2006.281.08:05:12.94#ibcon#*before return 0, iclass 15, count 0 2006.281.08:05:12.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:12.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:05:12.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:05:12.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:05:12.94$vc4f8/vblo=4,712.99 2006.281.08:05:12.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:05:12.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:05:12.94#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:12.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:12.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:12.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:12.94#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:05:12.94#ibcon#first serial, iclass 17, count 0 2006.281.08:05:12.94#ibcon#enter sib2, iclass 17, count 0 2006.281.08:05:12.94#ibcon#flushed, iclass 17, count 0 2006.281.08:05:12.94#ibcon#about to write, iclass 17, count 0 2006.281.08:05:12.94#ibcon#wrote, iclass 17, count 0 2006.281.08:05:12.94#ibcon#about to read 3, iclass 17, count 0 2006.281.08:05:12.96#ibcon#read 3, iclass 17, count 0 2006.281.08:05:12.96#ibcon#about to read 4, iclass 17, count 0 2006.281.08:05:12.96#ibcon#read 4, iclass 17, count 0 2006.281.08:05:12.96#ibcon#about to read 5, iclass 17, count 0 2006.281.08:05:12.96#ibcon#read 5, iclass 17, count 0 2006.281.08:05:12.96#ibcon#about to read 6, iclass 17, count 0 2006.281.08:05:12.96#ibcon#read 6, iclass 17, count 0 2006.281.08:05:12.96#ibcon#end of sib2, iclass 17, count 0 2006.281.08:05:12.96#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:05:12.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:05:12.96#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:05:12.96#ibcon#*before write, iclass 17, count 0 2006.281.08:05:12.96#ibcon#enter sib2, iclass 17, count 0 2006.281.08:05:12.96#ibcon#flushed, iclass 17, count 0 2006.281.08:05:12.96#ibcon#about to write, iclass 17, count 0 2006.281.08:05:12.96#ibcon#wrote, iclass 17, count 0 2006.281.08:05:12.96#ibcon#about to read 3, iclass 17, count 0 2006.281.08:05:13.00#ibcon#read 3, iclass 17, count 0 2006.281.08:05:13.00#ibcon#about to read 4, iclass 17, count 0 2006.281.08:05:13.00#ibcon#read 4, iclass 17, count 0 2006.281.08:05:13.00#ibcon#about to read 5, iclass 17, count 0 2006.281.08:05:13.00#ibcon#read 5, iclass 17, count 0 2006.281.08:05:13.00#ibcon#about to read 6, iclass 17, count 0 2006.281.08:05:13.00#ibcon#read 6, iclass 17, count 0 2006.281.08:05:13.00#ibcon#end of sib2, iclass 17, count 0 2006.281.08:05:13.00#ibcon#*after write, iclass 17, count 0 2006.281.08:05:13.00#ibcon#*before return 0, iclass 17, count 0 2006.281.08:05:13.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:13.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:05:13.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:05:13.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:05:13.00$vc4f8/vb=4,4 2006.281.08:05:13.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:05:13.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:05:13.00#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:13.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:13.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:13.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:13.06#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:05:13.06#ibcon#first serial, iclass 19, count 2 2006.281.08:05:13.06#ibcon#enter sib2, iclass 19, count 2 2006.281.08:05:13.06#ibcon#flushed, iclass 19, count 2 2006.281.08:05:13.06#ibcon#about to write, iclass 19, count 2 2006.281.08:05:13.06#ibcon#wrote, iclass 19, count 2 2006.281.08:05:13.06#ibcon#about to read 3, iclass 19, count 2 2006.281.08:05:13.08#ibcon#read 3, iclass 19, count 2 2006.281.08:05:13.08#ibcon#about to read 4, iclass 19, count 2 2006.281.08:05:13.08#ibcon#read 4, iclass 19, count 2 2006.281.08:05:13.08#ibcon#about to read 5, iclass 19, count 2 2006.281.08:05:13.08#ibcon#read 5, iclass 19, count 2 2006.281.08:05:13.08#ibcon#about to read 6, iclass 19, count 2 2006.281.08:05:13.08#ibcon#read 6, iclass 19, count 2 2006.281.08:05:13.08#ibcon#end of sib2, iclass 19, count 2 2006.281.08:05:13.08#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:05:13.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:05:13.08#ibcon#[27=AT04-04\r\n] 2006.281.08:05:13.08#ibcon#*before write, iclass 19, count 2 2006.281.08:05:13.08#ibcon#enter sib2, iclass 19, count 2 2006.281.08:05:13.08#ibcon#flushed, iclass 19, count 2 2006.281.08:05:13.08#ibcon#about to write, iclass 19, count 2 2006.281.08:05:13.08#ibcon#wrote, iclass 19, count 2 2006.281.08:05:13.08#ibcon#about to read 3, iclass 19, count 2 2006.281.08:05:13.11#ibcon#read 3, iclass 19, count 2 2006.281.08:05:13.11#ibcon#about to read 4, iclass 19, count 2 2006.281.08:05:13.11#ibcon#read 4, iclass 19, count 2 2006.281.08:05:13.11#ibcon#about to read 5, iclass 19, count 2 2006.281.08:05:13.11#ibcon#read 5, iclass 19, count 2 2006.281.08:05:13.11#ibcon#about to read 6, iclass 19, count 2 2006.281.08:05:13.11#ibcon#read 6, iclass 19, count 2 2006.281.08:05:13.11#ibcon#end of sib2, iclass 19, count 2 2006.281.08:05:13.11#ibcon#*after write, iclass 19, count 2 2006.281.08:05:13.11#ibcon#*before return 0, iclass 19, count 2 2006.281.08:05:13.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:13.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:05:13.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:05:13.11#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:13.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:13.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:13.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:13.23#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:05:13.23#ibcon#first serial, iclass 19, count 0 2006.281.08:05:13.23#ibcon#enter sib2, iclass 19, count 0 2006.281.08:05:13.23#ibcon#flushed, iclass 19, count 0 2006.281.08:05:13.23#ibcon#about to write, iclass 19, count 0 2006.281.08:05:13.23#ibcon#wrote, iclass 19, count 0 2006.281.08:05:13.23#ibcon#about to read 3, iclass 19, count 0 2006.281.08:05:13.25#ibcon#read 3, iclass 19, count 0 2006.281.08:05:13.25#ibcon#about to read 4, iclass 19, count 0 2006.281.08:05:13.25#ibcon#read 4, iclass 19, count 0 2006.281.08:05:13.25#ibcon#about to read 5, iclass 19, count 0 2006.281.08:05:13.25#ibcon#read 5, iclass 19, count 0 2006.281.08:05:13.25#ibcon#about to read 6, iclass 19, count 0 2006.281.08:05:13.25#ibcon#read 6, iclass 19, count 0 2006.281.08:05:13.25#ibcon#end of sib2, iclass 19, count 0 2006.281.08:05:13.25#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:05:13.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:05:13.25#ibcon#[27=USB\r\n] 2006.281.08:05:13.25#ibcon#*before write, iclass 19, count 0 2006.281.08:05:13.25#ibcon#enter sib2, iclass 19, count 0 2006.281.08:05:13.25#ibcon#flushed, iclass 19, count 0 2006.281.08:05:13.25#ibcon#about to write, iclass 19, count 0 2006.281.08:05:13.25#ibcon#wrote, iclass 19, count 0 2006.281.08:05:13.25#ibcon#about to read 3, iclass 19, count 0 2006.281.08:05:13.28#ibcon#read 3, iclass 19, count 0 2006.281.08:05:13.28#ibcon#about to read 4, iclass 19, count 0 2006.281.08:05:13.28#ibcon#read 4, iclass 19, count 0 2006.281.08:05:13.28#ibcon#about to read 5, iclass 19, count 0 2006.281.08:05:13.28#ibcon#read 5, iclass 19, count 0 2006.281.08:05:13.28#ibcon#about to read 6, iclass 19, count 0 2006.281.08:05:13.28#ibcon#read 6, iclass 19, count 0 2006.281.08:05:13.28#ibcon#end of sib2, iclass 19, count 0 2006.281.08:05:13.28#ibcon#*after write, iclass 19, count 0 2006.281.08:05:13.28#ibcon#*before return 0, iclass 19, count 0 2006.281.08:05:13.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:13.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:05:13.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:05:13.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:05:13.28$vc4f8/vblo=5,744.99 2006.281.08:05:13.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:05:13.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:05:13.28#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:13.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:13.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:13.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:13.28#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:05:13.28#ibcon#first serial, iclass 21, count 0 2006.281.08:05:13.28#ibcon#enter sib2, iclass 21, count 0 2006.281.08:05:13.28#ibcon#flushed, iclass 21, count 0 2006.281.08:05:13.28#ibcon#about to write, iclass 21, count 0 2006.281.08:05:13.28#ibcon#wrote, iclass 21, count 0 2006.281.08:05:13.28#ibcon#about to read 3, iclass 21, count 0 2006.281.08:05:13.30#ibcon#read 3, iclass 21, count 0 2006.281.08:05:13.30#ibcon#about to read 4, iclass 21, count 0 2006.281.08:05:13.30#ibcon#read 4, iclass 21, count 0 2006.281.08:05:13.30#ibcon#about to read 5, iclass 21, count 0 2006.281.08:05:13.30#ibcon#read 5, iclass 21, count 0 2006.281.08:05:13.30#ibcon#about to read 6, iclass 21, count 0 2006.281.08:05:13.30#ibcon#read 6, iclass 21, count 0 2006.281.08:05:13.30#ibcon#end of sib2, iclass 21, count 0 2006.281.08:05:13.30#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:05:13.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:05:13.30#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:05:13.30#ibcon#*before write, iclass 21, count 0 2006.281.08:05:13.30#ibcon#enter sib2, iclass 21, count 0 2006.281.08:05:13.30#ibcon#flushed, iclass 21, count 0 2006.281.08:05:13.30#ibcon#about to write, iclass 21, count 0 2006.281.08:05:13.30#ibcon#wrote, iclass 21, count 0 2006.281.08:05:13.30#ibcon#about to read 3, iclass 21, count 0 2006.281.08:05:13.34#ibcon#read 3, iclass 21, count 0 2006.281.08:05:13.34#ibcon#about to read 4, iclass 21, count 0 2006.281.08:05:13.34#ibcon#read 4, iclass 21, count 0 2006.281.08:05:13.34#ibcon#about to read 5, iclass 21, count 0 2006.281.08:05:13.34#ibcon#read 5, iclass 21, count 0 2006.281.08:05:13.34#ibcon#about to read 6, iclass 21, count 0 2006.281.08:05:13.34#ibcon#read 6, iclass 21, count 0 2006.281.08:05:13.34#ibcon#end of sib2, iclass 21, count 0 2006.281.08:05:13.34#ibcon#*after write, iclass 21, count 0 2006.281.08:05:13.34#ibcon#*before return 0, iclass 21, count 0 2006.281.08:05:13.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:13.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:05:13.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:05:13.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:05:13.34$vc4f8/vb=5,4 2006.281.08:05:13.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:05:13.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:05:13.34#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:13.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:13.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:13.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:13.40#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:05:13.40#ibcon#first serial, iclass 23, count 2 2006.281.08:05:13.40#ibcon#enter sib2, iclass 23, count 2 2006.281.08:05:13.40#ibcon#flushed, iclass 23, count 2 2006.281.08:05:13.40#ibcon#about to write, iclass 23, count 2 2006.281.08:05:13.40#ibcon#wrote, iclass 23, count 2 2006.281.08:05:13.40#ibcon#about to read 3, iclass 23, count 2 2006.281.08:05:13.42#ibcon#read 3, iclass 23, count 2 2006.281.08:05:13.42#ibcon#about to read 4, iclass 23, count 2 2006.281.08:05:13.42#ibcon#read 4, iclass 23, count 2 2006.281.08:05:13.42#ibcon#about to read 5, iclass 23, count 2 2006.281.08:05:13.42#ibcon#read 5, iclass 23, count 2 2006.281.08:05:13.42#ibcon#about to read 6, iclass 23, count 2 2006.281.08:05:13.42#ibcon#read 6, iclass 23, count 2 2006.281.08:05:13.42#ibcon#end of sib2, iclass 23, count 2 2006.281.08:05:13.42#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:05:13.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:05:13.42#ibcon#[27=AT05-04\r\n] 2006.281.08:05:13.42#ibcon#*before write, iclass 23, count 2 2006.281.08:05:13.42#ibcon#enter sib2, iclass 23, count 2 2006.281.08:05:13.42#ibcon#flushed, iclass 23, count 2 2006.281.08:05:13.42#ibcon#about to write, iclass 23, count 2 2006.281.08:05:13.42#ibcon#wrote, iclass 23, count 2 2006.281.08:05:13.42#ibcon#about to read 3, iclass 23, count 2 2006.281.08:05:13.45#ibcon#read 3, iclass 23, count 2 2006.281.08:05:13.45#ibcon#about to read 4, iclass 23, count 2 2006.281.08:05:13.45#ibcon#read 4, iclass 23, count 2 2006.281.08:05:13.45#ibcon#about to read 5, iclass 23, count 2 2006.281.08:05:13.45#ibcon#read 5, iclass 23, count 2 2006.281.08:05:13.45#ibcon#about to read 6, iclass 23, count 2 2006.281.08:05:13.45#ibcon#read 6, iclass 23, count 2 2006.281.08:05:13.45#ibcon#end of sib2, iclass 23, count 2 2006.281.08:05:13.45#ibcon#*after write, iclass 23, count 2 2006.281.08:05:13.45#ibcon#*before return 0, iclass 23, count 2 2006.281.08:05:13.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:13.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:05:13.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:05:13.45#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:13.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:13.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:13.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:13.57#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:05:13.57#ibcon#first serial, iclass 23, count 0 2006.281.08:05:13.57#ibcon#enter sib2, iclass 23, count 0 2006.281.08:05:13.57#ibcon#flushed, iclass 23, count 0 2006.281.08:05:13.57#ibcon#about to write, iclass 23, count 0 2006.281.08:05:13.57#ibcon#wrote, iclass 23, count 0 2006.281.08:05:13.57#ibcon#about to read 3, iclass 23, count 0 2006.281.08:05:13.59#ibcon#read 3, iclass 23, count 0 2006.281.08:05:13.59#ibcon#about to read 4, iclass 23, count 0 2006.281.08:05:13.59#ibcon#read 4, iclass 23, count 0 2006.281.08:05:13.59#ibcon#about to read 5, iclass 23, count 0 2006.281.08:05:13.59#ibcon#read 5, iclass 23, count 0 2006.281.08:05:13.59#ibcon#about to read 6, iclass 23, count 0 2006.281.08:05:13.59#ibcon#read 6, iclass 23, count 0 2006.281.08:05:13.59#ibcon#end of sib2, iclass 23, count 0 2006.281.08:05:13.59#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:05:13.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:05:13.59#ibcon#[27=USB\r\n] 2006.281.08:05:13.59#ibcon#*before write, iclass 23, count 0 2006.281.08:05:13.59#ibcon#enter sib2, iclass 23, count 0 2006.281.08:05:13.59#ibcon#flushed, iclass 23, count 0 2006.281.08:05:13.59#ibcon#about to write, iclass 23, count 0 2006.281.08:05:13.59#ibcon#wrote, iclass 23, count 0 2006.281.08:05:13.59#ibcon#about to read 3, iclass 23, count 0 2006.281.08:05:13.62#ibcon#read 3, iclass 23, count 0 2006.281.08:05:13.62#ibcon#about to read 4, iclass 23, count 0 2006.281.08:05:13.62#ibcon#read 4, iclass 23, count 0 2006.281.08:05:13.62#ibcon#about to read 5, iclass 23, count 0 2006.281.08:05:13.62#ibcon#read 5, iclass 23, count 0 2006.281.08:05:13.62#ibcon#about to read 6, iclass 23, count 0 2006.281.08:05:13.62#ibcon#read 6, iclass 23, count 0 2006.281.08:05:13.62#ibcon#end of sib2, iclass 23, count 0 2006.281.08:05:13.62#ibcon#*after write, iclass 23, count 0 2006.281.08:05:13.62#ibcon#*before return 0, iclass 23, count 0 2006.281.08:05:13.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:13.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:05:13.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:05:13.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:05:13.62$vc4f8/vblo=6,752.99 2006.281.08:05:13.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:05:13.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:05:13.62#ibcon#ireg 17 cls_cnt 0 2006.281.08:05:13.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:13.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:13.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:13.62#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:05:13.62#ibcon#first serial, iclass 25, count 0 2006.281.08:05:13.62#ibcon#enter sib2, iclass 25, count 0 2006.281.08:05:13.62#ibcon#flushed, iclass 25, count 0 2006.281.08:05:13.62#ibcon#about to write, iclass 25, count 0 2006.281.08:05:13.62#ibcon#wrote, iclass 25, count 0 2006.281.08:05:13.62#ibcon#about to read 3, iclass 25, count 0 2006.281.08:05:13.64#ibcon#read 3, iclass 25, count 0 2006.281.08:05:13.64#ibcon#about to read 4, iclass 25, count 0 2006.281.08:05:13.64#ibcon#read 4, iclass 25, count 0 2006.281.08:05:13.64#ibcon#about to read 5, iclass 25, count 0 2006.281.08:05:13.64#ibcon#read 5, iclass 25, count 0 2006.281.08:05:13.64#ibcon#about to read 6, iclass 25, count 0 2006.281.08:05:13.64#ibcon#read 6, iclass 25, count 0 2006.281.08:05:13.64#ibcon#end of sib2, iclass 25, count 0 2006.281.08:05:13.64#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:05:13.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:05:13.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:05:13.64#ibcon#*before write, iclass 25, count 0 2006.281.08:05:13.64#ibcon#enter sib2, iclass 25, count 0 2006.281.08:05:13.64#ibcon#flushed, iclass 25, count 0 2006.281.08:05:13.64#ibcon#about to write, iclass 25, count 0 2006.281.08:05:13.64#ibcon#wrote, iclass 25, count 0 2006.281.08:05:13.64#ibcon#about to read 3, iclass 25, count 0 2006.281.08:05:13.69#ibcon#read 3, iclass 25, count 0 2006.281.08:05:13.69#ibcon#about to read 4, iclass 25, count 0 2006.281.08:05:13.69#ibcon#read 4, iclass 25, count 0 2006.281.08:05:13.69#ibcon#about to read 5, iclass 25, count 0 2006.281.08:05:13.69#ibcon#read 5, iclass 25, count 0 2006.281.08:05:13.69#ibcon#about to read 6, iclass 25, count 0 2006.281.08:05:13.69#ibcon#read 6, iclass 25, count 0 2006.281.08:05:13.69#ibcon#end of sib2, iclass 25, count 0 2006.281.08:05:13.69#ibcon#*after write, iclass 25, count 0 2006.281.08:05:13.69#ibcon#*before return 0, iclass 25, count 0 2006.281.08:05:13.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:13.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:05:13.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:05:13.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:05:13.69$vc4f8/vb=6,4 2006.281.08:05:13.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:05:13.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:05:13.69#ibcon#ireg 11 cls_cnt 2 2006.281.08:05:13.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:13.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:13.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:13.74#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:05:13.74#ibcon#first serial, iclass 27, count 2 2006.281.08:05:13.74#ibcon#enter sib2, iclass 27, count 2 2006.281.08:05:13.74#ibcon#flushed, iclass 27, count 2 2006.281.08:05:13.74#ibcon#about to write, iclass 27, count 2 2006.281.08:05:13.74#ibcon#wrote, iclass 27, count 2 2006.281.08:05:13.74#ibcon#about to read 3, iclass 27, count 2 2006.281.08:05:13.76#ibcon#read 3, iclass 27, count 2 2006.281.08:05:13.76#ibcon#about to read 4, iclass 27, count 2 2006.281.08:05:13.76#ibcon#read 4, iclass 27, count 2 2006.281.08:05:13.76#ibcon#about to read 5, iclass 27, count 2 2006.281.08:05:13.76#ibcon#read 5, iclass 27, count 2 2006.281.08:05:13.76#ibcon#about to read 6, iclass 27, count 2 2006.281.08:05:13.76#ibcon#read 6, iclass 27, count 2 2006.281.08:05:13.76#ibcon#end of sib2, iclass 27, count 2 2006.281.08:05:13.76#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:05:13.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:05:13.76#ibcon#[27=AT06-04\r\n] 2006.281.08:05:13.76#ibcon#*before write, iclass 27, count 2 2006.281.08:05:13.76#ibcon#enter sib2, iclass 27, count 2 2006.281.08:05:13.76#ibcon#flushed, iclass 27, count 2 2006.281.08:05:13.76#ibcon#about to write, iclass 27, count 2 2006.281.08:05:13.76#ibcon#wrote, iclass 27, count 2 2006.281.08:05:13.76#ibcon#about to read 3, iclass 27, count 2 2006.281.08:05:13.79#ibcon#read 3, iclass 27, count 2 2006.281.08:05:13.79#ibcon#about to read 4, iclass 27, count 2 2006.281.08:05:13.79#ibcon#read 4, iclass 27, count 2 2006.281.08:05:13.79#ibcon#about to read 5, iclass 27, count 2 2006.281.08:05:13.79#ibcon#read 5, iclass 27, count 2 2006.281.08:05:13.79#ibcon#about to read 6, iclass 27, count 2 2006.281.08:05:13.79#ibcon#read 6, iclass 27, count 2 2006.281.08:05:13.79#ibcon#end of sib2, iclass 27, count 2 2006.281.08:05:13.79#ibcon#*after write, iclass 27, count 2 2006.281.08:05:13.79#ibcon#*before return 0, iclass 27, count 2 2006.281.08:05:13.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:13.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:05:13.79#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:05:13.79#ibcon#ireg 7 cls_cnt 0 2006.281.08:05:13.79#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:13.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:13.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:13.91#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:05:13.91#ibcon#first serial, iclass 27, count 0 2006.281.08:05:13.91#ibcon#enter sib2, iclass 27, count 0 2006.281.08:05:13.91#ibcon#flushed, iclass 27, count 0 2006.281.08:05:13.91#ibcon#about to write, iclass 27, count 0 2006.281.08:05:13.91#ibcon#wrote, iclass 27, count 0 2006.281.08:05:13.91#ibcon#about to read 3, iclass 27, count 0 2006.281.08:05:13.93#ibcon#read 3, iclass 27, count 0 2006.281.08:05:13.93#ibcon#about to read 4, iclass 27, count 0 2006.281.08:05:13.93#ibcon#read 4, iclass 27, count 0 2006.281.08:05:13.93#ibcon#about to read 5, iclass 27, count 0 2006.281.08:05:13.93#ibcon#read 5, iclass 27, count 0 2006.281.08:05:13.93#ibcon#about to read 6, iclass 27, count 0 2006.281.08:05:13.93#ibcon#read 6, iclass 27, count 0 2006.281.08:05:13.93#ibcon#end of sib2, iclass 27, count 0 2006.281.08:05:13.93#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:05:13.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:05:13.93#ibcon#[27=USB\r\n] 2006.281.08:05:13.93#ibcon#*before write, iclass 27, count 0 2006.281.08:05:13.93#ibcon#enter sib2, iclass 27, count 0 2006.281.08:05:13.93#ibcon#flushed, iclass 27, count 0 2006.281.08:05:13.93#ibcon#about to write, iclass 27, count 0 2006.281.08:05:13.93#ibcon#wrote, iclass 27, count 0 2006.281.08:05:13.93#ibcon#about to read 3, iclass 27, count 0 2006.281.08:05:13.96#ibcon#read 3, iclass 27, count 0 2006.281.08:05:13.96#ibcon#about to read 4, iclass 27, count 0 2006.281.08:05:13.96#ibcon#read 4, iclass 27, count 0 2006.281.08:05:13.96#ibcon#about to read 5, iclass 27, count 0 2006.281.08:05:13.96#ibcon#read 5, iclass 27, count 0 2006.281.08:05:13.96#ibcon#about to read 6, iclass 27, count 0 2006.281.08:05:13.96#ibcon#read 6, iclass 27, count 0 2006.281.08:05:13.96#ibcon#end of sib2, iclass 27, count 0 2006.281.08:05:13.96#ibcon#*after write, iclass 27, count 0 2006.281.08:05:13.96#ibcon#*before return 0, iclass 27, count 0 2006.281.08:05:13.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:13.96#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:05:13.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:05:13.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:05:13.96$vc4f8/vabw=wide 2006.281.08:05:13.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:05:13.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:05:13.96#ibcon#ireg 8 cls_cnt 0 2006.281.08:05:13.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:13.96#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:13.96#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:13.96#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:05:13.96#ibcon#first serial, iclass 29, count 0 2006.281.08:05:13.96#ibcon#enter sib2, iclass 29, count 0 2006.281.08:05:13.96#ibcon#flushed, iclass 29, count 0 2006.281.08:05:13.96#ibcon#about to write, iclass 29, count 0 2006.281.08:05:13.96#ibcon#wrote, iclass 29, count 0 2006.281.08:05:13.96#ibcon#about to read 3, iclass 29, count 0 2006.281.08:05:13.98#ibcon#read 3, iclass 29, count 0 2006.281.08:05:13.98#ibcon#about to read 4, iclass 29, count 0 2006.281.08:05:13.98#ibcon#read 4, iclass 29, count 0 2006.281.08:05:13.98#ibcon#about to read 5, iclass 29, count 0 2006.281.08:05:13.98#ibcon#read 5, iclass 29, count 0 2006.281.08:05:13.98#ibcon#about to read 6, iclass 29, count 0 2006.281.08:05:13.98#ibcon#read 6, iclass 29, count 0 2006.281.08:05:13.98#ibcon#end of sib2, iclass 29, count 0 2006.281.08:05:13.98#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:05:13.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:05:13.98#ibcon#[25=BW32\r\n] 2006.281.08:05:13.98#ibcon#*before write, iclass 29, count 0 2006.281.08:05:13.98#ibcon#enter sib2, iclass 29, count 0 2006.281.08:05:13.98#ibcon#flushed, iclass 29, count 0 2006.281.08:05:13.98#ibcon#about to write, iclass 29, count 0 2006.281.08:05:13.98#ibcon#wrote, iclass 29, count 0 2006.281.08:05:13.98#ibcon#about to read 3, iclass 29, count 0 2006.281.08:05:14.01#ibcon#read 3, iclass 29, count 0 2006.281.08:05:14.01#ibcon#about to read 4, iclass 29, count 0 2006.281.08:05:14.01#ibcon#read 4, iclass 29, count 0 2006.281.08:05:14.01#ibcon#about to read 5, iclass 29, count 0 2006.281.08:05:14.01#ibcon#read 5, iclass 29, count 0 2006.281.08:05:14.01#ibcon#about to read 6, iclass 29, count 0 2006.281.08:05:14.01#ibcon#read 6, iclass 29, count 0 2006.281.08:05:14.01#ibcon#end of sib2, iclass 29, count 0 2006.281.08:05:14.01#ibcon#*after write, iclass 29, count 0 2006.281.08:05:14.01#ibcon#*before return 0, iclass 29, count 0 2006.281.08:05:14.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:14.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:05:14.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:05:14.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:05:14.01$vc4f8/vbbw=wide 2006.281.08:05:14.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:05:14.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:05:14.01#ibcon#ireg 8 cls_cnt 0 2006.281.08:05:14.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:05:14.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:05:14.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:05:14.08#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:05:14.08#ibcon#first serial, iclass 31, count 0 2006.281.08:05:14.08#ibcon#enter sib2, iclass 31, count 0 2006.281.08:05:14.08#ibcon#flushed, iclass 31, count 0 2006.281.08:05:14.08#ibcon#about to write, iclass 31, count 0 2006.281.08:05:14.08#ibcon#wrote, iclass 31, count 0 2006.281.08:05:14.08#ibcon#about to read 3, iclass 31, count 0 2006.281.08:05:14.10#ibcon#read 3, iclass 31, count 0 2006.281.08:05:14.10#ibcon#about to read 4, iclass 31, count 0 2006.281.08:05:14.10#ibcon#read 4, iclass 31, count 0 2006.281.08:05:14.10#ibcon#about to read 5, iclass 31, count 0 2006.281.08:05:14.10#ibcon#read 5, iclass 31, count 0 2006.281.08:05:14.10#ibcon#about to read 6, iclass 31, count 0 2006.281.08:05:14.10#ibcon#read 6, iclass 31, count 0 2006.281.08:05:14.10#ibcon#end of sib2, iclass 31, count 0 2006.281.08:05:14.10#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:05:14.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:05:14.10#ibcon#[27=BW32\r\n] 2006.281.08:05:14.10#ibcon#*before write, iclass 31, count 0 2006.281.08:05:14.10#ibcon#enter sib2, iclass 31, count 0 2006.281.08:05:14.10#ibcon#flushed, iclass 31, count 0 2006.281.08:05:14.10#ibcon#about to write, iclass 31, count 0 2006.281.08:05:14.10#ibcon#wrote, iclass 31, count 0 2006.281.08:05:14.10#ibcon#about to read 3, iclass 31, count 0 2006.281.08:05:14.13#ibcon#read 3, iclass 31, count 0 2006.281.08:05:14.13#ibcon#about to read 4, iclass 31, count 0 2006.281.08:05:14.13#ibcon#read 4, iclass 31, count 0 2006.281.08:05:14.13#ibcon#about to read 5, iclass 31, count 0 2006.281.08:05:14.13#ibcon#read 5, iclass 31, count 0 2006.281.08:05:14.13#ibcon#about to read 6, iclass 31, count 0 2006.281.08:05:14.13#ibcon#read 6, iclass 31, count 0 2006.281.08:05:14.13#ibcon#end of sib2, iclass 31, count 0 2006.281.08:05:14.13#ibcon#*after write, iclass 31, count 0 2006.281.08:05:14.13#ibcon#*before return 0, iclass 31, count 0 2006.281.08:05:14.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:05:14.13#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:05:14.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:05:14.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:05:14.13$4f8m12a/ifd4f 2006.281.08:05:14.13$ifd4f/lo= 2006.281.08:05:14.13$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:05:14.13$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:05:14.14$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:05:14.14$ifd4f/patch= 2006.281.08:05:14.14$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:05:14.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:05:14.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:05:14.14$4f8m12a/"form=m,16.000,1:2 2006.281.08:05:14.14$4f8m12a/"tpicd 2006.281.08:05:14.14$4f8m12a/echo=off 2006.281.08:05:14.14$4f8m12a/xlog=off 2006.281.08:05:14.14:!2006.281.08:05:40 2006.281.08:05:23.14#trakl#Source acquired 2006.281.08:05:24.14#flagr#flagr/antenna,acquired 2006.281.08:05:40.00:preob 2006.281.08:05:40.14/onsource/TRACKING 2006.281.08:05:40.14:!2006.281.08:05:50 2006.281.08:05:50.00:data_valid=on 2006.281.08:05:50.00:midob 2006.281.08:05:51.14/onsource/TRACKING 2006.281.08:05:51.14/wx/20.35,1001.6,52 2006.281.08:05:51.28/cable/+6.4872E-03 2006.281.08:05:52.37/va/01,07,usb,yes,32,34 2006.281.08:05:52.37/va/02,06,usb,yes,30,31 2006.281.08:05:52.37/va/03,06,usb,yes,28,28 2006.281.08:05:52.37/va/04,06,usb,yes,31,33 2006.281.08:05:52.37/va/05,07,usb,yes,29,31 2006.281.08:05:52.37/va/06,06,usb,yes,29,28 2006.281.08:05:52.37/va/07,06,usb,yes,29,29 2006.281.08:05:52.37/va/08,06,usb,yes,31,30 2006.281.08:05:52.60/valo/01,532.99,yes,locked 2006.281.08:05:52.60/valo/02,572.99,yes,locked 2006.281.08:05:52.60/valo/03,672.99,yes,locked 2006.281.08:05:52.60/valo/04,832.99,yes,locked 2006.281.08:05:52.60/valo/05,652.99,yes,locked 2006.281.08:05:52.60/valo/06,772.99,yes,locked 2006.281.08:05:52.60/valo/07,832.99,yes,locked 2006.281.08:05:52.60/valo/08,852.99,yes,locked 2006.281.08:05:53.69/vb/01,04,usb,yes,29,28 2006.281.08:05:53.69/vb/02,05,usb,yes,27,29 2006.281.08:05:53.69/vb/03,04,usb,yes,28,31 2006.281.08:05:53.69/vb/04,04,usb,yes,28,29 2006.281.08:05:53.69/vb/05,04,usb,yes,26,31 2006.281.08:05:53.69/vb/06,04,usb,yes,27,30 2006.281.08:05:53.69/vb/07,04,usb,yes,30,30 2006.281.08:05:53.69/vb/08,04,usb,yes,27,31 2006.281.08:05:53.92/vblo/01,632.99,yes,locked 2006.281.08:05:53.92/vblo/02,640.99,yes,locked 2006.281.08:05:53.92/vblo/03,656.99,yes,locked 2006.281.08:05:53.92/vblo/04,712.99,yes,locked 2006.281.08:05:53.92/vblo/05,744.99,yes,locked 2006.281.08:05:53.92/vblo/06,752.99,yes,locked 2006.281.08:05:53.92/vblo/07,734.99,yes,locked 2006.281.08:05:53.92/vblo/08,744.99,yes,locked 2006.281.08:05:54.07/vabw/8 2006.281.08:05:54.22/vbbw/8 2006.281.08:05:54.31/xfe/off,on,12.0 2006.281.08:05:54.69/ifatt/23,28,28,28 2006.281.08:05:55.08/fmout-gps/S +3.15E-07 2006.281.08:05:55.10:!2006.281.08:06:50 2006.281.08:06:07.14#trakl#Off source 2006.281.08:06:07.14?ERROR st -7 Antenna off-source! 2006.281.08:06:07.14#trakl#az 313.968 el 43.560 azerr*cos(el) -0.0079 elerr -0.0178 2006.281.08:06:07.14#flagr#flagr/antenna,off-source 2006.281.08:06:15.13#trakl#Source re-acquired 2006.281.08:06:16.13#flagr#flagr/antenna,re-acquired 2006.281.08:06:50.00:data_valid=off 2006.281.08:06:50.00:postob 2006.281.08:06:50.11/cable/+6.4870E-03 2006.281.08:06:50.11/wx/20.32,1001.6,52 2006.281.08:06:51.08/fmout-gps/S +3.17E-07 2006.281.08:06:51.08:scan_name=281-0807,k06281,60 2006.281.08:06:51.08:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.281.08:06:51.13#flagr#flagr/antenna,new-source 2006.281.08:06:52.13:checkk5 2006.281.08:06:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:06:53.02/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:06:53.44/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:06:53.84/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:06:54.46/chk_obsdata//k5ts1/T2810805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:06:54.91/chk_obsdata//k5ts2/T2810805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:06:55.31/chk_obsdata//k5ts3/T2810805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:06:55.72/chk_obsdata//k5ts4/T2810805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:06:56.69/k5log//k5ts1_log_newline 2006.281.08:06:57.53/k5log//k5ts2_log_newline 2006.281.08:06:58.53/k5log//k5ts3_log_newline 2006.281.08:06:59.31/k5log//k5ts4_log_newline 2006.281.08:06:59.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:06:59.33:4f8m12a=2 2006.281.08:06:59.33$4f8m12a/echo=on 2006.281.08:06:59.33$4f8m12a/pcalon 2006.281.08:06:59.33$pcalon/"no phase cal control is implemented here 2006.281.08:06:59.33$4f8m12a/"tpicd=stop 2006.281.08:06:59.33$4f8m12a/vc4f8 2006.281.08:06:59.33$vc4f8/valo=1,532.99 2006.281.08:06:59.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:06:59.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:06:59.34#ibcon#ireg 17 cls_cnt 0 2006.281.08:06:59.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:06:59.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:06:59.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:06:59.34#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:06:59.34#ibcon#first serial, iclass 6, count 0 2006.281.08:06:59.34#ibcon#enter sib2, iclass 6, count 0 2006.281.08:06:59.34#ibcon#flushed, iclass 6, count 0 2006.281.08:06:59.34#ibcon#about to write, iclass 6, count 0 2006.281.08:06:59.34#ibcon#wrote, iclass 6, count 0 2006.281.08:06:59.34#ibcon#about to read 3, iclass 6, count 0 2006.281.08:06:59.36#ibcon#read 3, iclass 6, count 0 2006.281.08:06:59.36#ibcon#about to read 4, iclass 6, count 0 2006.281.08:06:59.36#ibcon#read 4, iclass 6, count 0 2006.281.08:06:59.36#ibcon#about to read 5, iclass 6, count 0 2006.281.08:06:59.36#ibcon#read 5, iclass 6, count 0 2006.281.08:06:59.36#ibcon#about to read 6, iclass 6, count 0 2006.281.08:06:59.36#ibcon#read 6, iclass 6, count 0 2006.281.08:06:59.36#ibcon#end of sib2, iclass 6, count 0 2006.281.08:06:59.36#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:06:59.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:06:59.36#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:06:59.36#ibcon#*before write, iclass 6, count 0 2006.281.08:06:59.36#ibcon#enter sib2, iclass 6, count 0 2006.281.08:06:59.36#ibcon#flushed, iclass 6, count 0 2006.281.08:06:59.36#ibcon#about to write, iclass 6, count 0 2006.281.08:06:59.36#ibcon#wrote, iclass 6, count 0 2006.281.08:06:59.36#ibcon#about to read 3, iclass 6, count 0 2006.281.08:06:59.41#ibcon#read 3, iclass 6, count 0 2006.281.08:06:59.41#ibcon#about to read 4, iclass 6, count 0 2006.281.08:06:59.41#ibcon#read 4, iclass 6, count 0 2006.281.08:06:59.41#ibcon#about to read 5, iclass 6, count 0 2006.281.08:06:59.41#ibcon#read 5, iclass 6, count 0 2006.281.08:06:59.41#ibcon#about to read 6, iclass 6, count 0 2006.281.08:06:59.41#ibcon#read 6, iclass 6, count 0 2006.281.08:06:59.41#ibcon#end of sib2, iclass 6, count 0 2006.281.08:06:59.41#ibcon#*after write, iclass 6, count 0 2006.281.08:06:59.41#ibcon#*before return 0, iclass 6, count 0 2006.281.08:06:59.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:06:59.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:06:59.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:06:59.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:06:59.41$vc4f8/va=1,7 2006.281.08:06:59.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:06:59.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:06:59.41#ibcon#ireg 11 cls_cnt 2 2006.281.08:06:59.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:06:59.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:06:59.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:06:59.41#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:06:59.41#ibcon#first serial, iclass 10, count 2 2006.281.08:06:59.41#ibcon#enter sib2, iclass 10, count 2 2006.281.08:06:59.41#ibcon#flushed, iclass 10, count 2 2006.281.08:06:59.41#ibcon#about to write, iclass 10, count 2 2006.281.08:06:59.41#ibcon#wrote, iclass 10, count 2 2006.281.08:06:59.41#ibcon#about to read 3, iclass 10, count 2 2006.281.08:06:59.43#ibcon#read 3, iclass 10, count 2 2006.281.08:06:59.43#ibcon#about to read 4, iclass 10, count 2 2006.281.08:06:59.43#ibcon#read 4, iclass 10, count 2 2006.281.08:06:59.43#ibcon#about to read 5, iclass 10, count 2 2006.281.08:06:59.43#ibcon#read 5, iclass 10, count 2 2006.281.08:06:59.43#ibcon#about to read 6, iclass 10, count 2 2006.281.08:06:59.43#ibcon#read 6, iclass 10, count 2 2006.281.08:06:59.43#ibcon#end of sib2, iclass 10, count 2 2006.281.08:06:59.43#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:06:59.43#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:06:59.43#ibcon#[25=AT01-07\r\n] 2006.281.08:06:59.43#ibcon#*before write, iclass 10, count 2 2006.281.08:06:59.43#ibcon#enter sib2, iclass 10, count 2 2006.281.08:06:59.43#ibcon#flushed, iclass 10, count 2 2006.281.08:06:59.43#ibcon#about to write, iclass 10, count 2 2006.281.08:06:59.43#ibcon#wrote, iclass 10, count 2 2006.281.08:06:59.43#ibcon#about to read 3, iclass 10, count 2 2006.281.08:06:59.46#ibcon#read 3, iclass 10, count 2 2006.281.08:06:59.46#ibcon#about to read 4, iclass 10, count 2 2006.281.08:06:59.46#ibcon#read 4, iclass 10, count 2 2006.281.08:06:59.46#ibcon#about to read 5, iclass 10, count 2 2006.281.08:06:59.46#ibcon#read 5, iclass 10, count 2 2006.281.08:06:59.46#ibcon#about to read 6, iclass 10, count 2 2006.281.08:06:59.46#ibcon#read 6, iclass 10, count 2 2006.281.08:06:59.46#ibcon#end of sib2, iclass 10, count 2 2006.281.08:06:59.46#ibcon#*after write, iclass 10, count 2 2006.281.08:06:59.46#ibcon#*before return 0, iclass 10, count 2 2006.281.08:06:59.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:06:59.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:06:59.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:06:59.46#ibcon#ireg 7 cls_cnt 0 2006.281.08:06:59.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:06:59.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:06:59.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:06:59.58#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:06:59.58#ibcon#first serial, iclass 10, count 0 2006.281.08:06:59.58#ibcon#enter sib2, iclass 10, count 0 2006.281.08:06:59.58#ibcon#flushed, iclass 10, count 0 2006.281.08:06:59.58#ibcon#about to write, iclass 10, count 0 2006.281.08:06:59.58#ibcon#wrote, iclass 10, count 0 2006.281.08:06:59.58#ibcon#about to read 3, iclass 10, count 0 2006.281.08:06:59.60#ibcon#read 3, iclass 10, count 0 2006.281.08:06:59.60#ibcon#about to read 4, iclass 10, count 0 2006.281.08:06:59.60#ibcon#read 4, iclass 10, count 0 2006.281.08:06:59.60#ibcon#about to read 5, iclass 10, count 0 2006.281.08:06:59.60#ibcon#read 5, iclass 10, count 0 2006.281.08:06:59.60#ibcon#about to read 6, iclass 10, count 0 2006.281.08:06:59.60#ibcon#read 6, iclass 10, count 0 2006.281.08:06:59.60#ibcon#end of sib2, iclass 10, count 0 2006.281.08:06:59.60#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:06:59.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:06:59.60#ibcon#[25=USB\r\n] 2006.281.08:06:59.60#ibcon#*before write, iclass 10, count 0 2006.281.08:06:59.60#ibcon#enter sib2, iclass 10, count 0 2006.281.08:06:59.60#ibcon#flushed, iclass 10, count 0 2006.281.08:06:59.60#ibcon#about to write, iclass 10, count 0 2006.281.08:06:59.60#ibcon#wrote, iclass 10, count 0 2006.281.08:06:59.60#ibcon#about to read 3, iclass 10, count 0 2006.281.08:06:59.63#ibcon#read 3, iclass 10, count 0 2006.281.08:06:59.63#ibcon#about to read 4, iclass 10, count 0 2006.281.08:06:59.63#ibcon#read 4, iclass 10, count 0 2006.281.08:06:59.63#ibcon#about to read 5, iclass 10, count 0 2006.281.08:06:59.63#ibcon#read 5, iclass 10, count 0 2006.281.08:06:59.63#ibcon#about to read 6, iclass 10, count 0 2006.281.08:06:59.63#ibcon#read 6, iclass 10, count 0 2006.281.08:06:59.63#ibcon#end of sib2, iclass 10, count 0 2006.281.08:06:59.63#ibcon#*after write, iclass 10, count 0 2006.281.08:06:59.63#ibcon#*before return 0, iclass 10, count 0 2006.281.08:06:59.63#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:06:59.63#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:06:59.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:06:59.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:06:59.63$vc4f8/valo=2,572.99 2006.281.08:06:59.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:06:59.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:06:59.63#ibcon#ireg 17 cls_cnt 0 2006.281.08:06:59.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:06:59.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:06:59.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:06:59.63#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:06:59.63#ibcon#first serial, iclass 12, count 0 2006.281.08:06:59.63#ibcon#enter sib2, iclass 12, count 0 2006.281.08:06:59.63#ibcon#flushed, iclass 12, count 0 2006.281.08:06:59.63#ibcon#about to write, iclass 12, count 0 2006.281.08:06:59.63#ibcon#wrote, iclass 12, count 0 2006.281.08:06:59.63#ibcon#about to read 3, iclass 12, count 0 2006.281.08:06:59.65#ibcon#read 3, iclass 12, count 0 2006.281.08:06:59.65#ibcon#about to read 4, iclass 12, count 0 2006.281.08:06:59.65#ibcon#read 4, iclass 12, count 0 2006.281.08:06:59.65#ibcon#about to read 5, iclass 12, count 0 2006.281.08:06:59.65#ibcon#read 5, iclass 12, count 0 2006.281.08:06:59.65#ibcon#about to read 6, iclass 12, count 0 2006.281.08:06:59.65#ibcon#read 6, iclass 12, count 0 2006.281.08:06:59.65#ibcon#end of sib2, iclass 12, count 0 2006.281.08:06:59.65#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:06:59.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:06:59.65#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:06:59.65#ibcon#*before write, iclass 12, count 0 2006.281.08:06:59.65#ibcon#enter sib2, iclass 12, count 0 2006.281.08:06:59.65#ibcon#flushed, iclass 12, count 0 2006.281.08:06:59.65#ibcon#about to write, iclass 12, count 0 2006.281.08:06:59.65#ibcon#wrote, iclass 12, count 0 2006.281.08:06:59.65#ibcon#about to read 3, iclass 12, count 0 2006.281.08:06:59.69#ibcon#read 3, iclass 12, count 0 2006.281.08:06:59.69#ibcon#about to read 4, iclass 12, count 0 2006.281.08:06:59.69#ibcon#read 4, iclass 12, count 0 2006.281.08:06:59.69#ibcon#about to read 5, iclass 12, count 0 2006.281.08:06:59.69#ibcon#read 5, iclass 12, count 0 2006.281.08:06:59.69#ibcon#about to read 6, iclass 12, count 0 2006.281.08:06:59.69#ibcon#read 6, iclass 12, count 0 2006.281.08:06:59.69#ibcon#end of sib2, iclass 12, count 0 2006.281.08:06:59.69#ibcon#*after write, iclass 12, count 0 2006.281.08:06:59.69#ibcon#*before return 0, iclass 12, count 0 2006.281.08:06:59.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:06:59.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:06:59.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:06:59.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:06:59.69$vc4f8/va=2,6 2006.281.08:06:59.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.08:06:59.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.08:06:59.69#ibcon#ireg 11 cls_cnt 2 2006.281.08:06:59.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:06:59.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:06:59.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:06:59.75#ibcon#enter wrdev, iclass 14, count 2 2006.281.08:06:59.75#ibcon#first serial, iclass 14, count 2 2006.281.08:06:59.75#ibcon#enter sib2, iclass 14, count 2 2006.281.08:06:59.75#ibcon#flushed, iclass 14, count 2 2006.281.08:06:59.75#ibcon#about to write, iclass 14, count 2 2006.281.08:06:59.75#ibcon#wrote, iclass 14, count 2 2006.281.08:06:59.75#ibcon#about to read 3, iclass 14, count 2 2006.281.08:06:59.77#ibcon#read 3, iclass 14, count 2 2006.281.08:06:59.77#ibcon#about to read 4, iclass 14, count 2 2006.281.08:06:59.77#ibcon#read 4, iclass 14, count 2 2006.281.08:06:59.77#ibcon#about to read 5, iclass 14, count 2 2006.281.08:06:59.77#ibcon#read 5, iclass 14, count 2 2006.281.08:06:59.77#ibcon#about to read 6, iclass 14, count 2 2006.281.08:06:59.77#ibcon#read 6, iclass 14, count 2 2006.281.08:06:59.77#ibcon#end of sib2, iclass 14, count 2 2006.281.08:06:59.77#ibcon#*mode == 0, iclass 14, count 2 2006.281.08:06:59.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.08:06:59.77#ibcon#[25=AT02-06\r\n] 2006.281.08:06:59.77#ibcon#*before write, iclass 14, count 2 2006.281.08:06:59.77#ibcon#enter sib2, iclass 14, count 2 2006.281.08:06:59.77#ibcon#flushed, iclass 14, count 2 2006.281.08:06:59.77#ibcon#about to write, iclass 14, count 2 2006.281.08:06:59.77#ibcon#wrote, iclass 14, count 2 2006.281.08:06:59.77#ibcon#about to read 3, iclass 14, count 2 2006.281.08:06:59.80#ibcon#read 3, iclass 14, count 2 2006.281.08:06:59.80#ibcon#about to read 4, iclass 14, count 2 2006.281.08:06:59.80#ibcon#read 4, iclass 14, count 2 2006.281.08:06:59.80#ibcon#about to read 5, iclass 14, count 2 2006.281.08:06:59.80#ibcon#read 5, iclass 14, count 2 2006.281.08:06:59.80#ibcon#about to read 6, iclass 14, count 2 2006.281.08:06:59.80#ibcon#read 6, iclass 14, count 2 2006.281.08:06:59.80#ibcon#end of sib2, iclass 14, count 2 2006.281.08:06:59.80#ibcon#*after write, iclass 14, count 2 2006.281.08:06:59.80#ibcon#*before return 0, iclass 14, count 2 2006.281.08:06:59.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:06:59.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:06:59.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.08:06:59.80#ibcon#ireg 7 cls_cnt 0 2006.281.08:06:59.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:06:59.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:06:59.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:06:59.92#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:06:59.92#ibcon#first serial, iclass 14, count 0 2006.281.08:06:59.92#ibcon#enter sib2, iclass 14, count 0 2006.281.08:06:59.92#ibcon#flushed, iclass 14, count 0 2006.281.08:06:59.92#ibcon#about to write, iclass 14, count 0 2006.281.08:06:59.92#ibcon#wrote, iclass 14, count 0 2006.281.08:06:59.92#ibcon#about to read 3, iclass 14, count 0 2006.281.08:06:59.94#ibcon#read 3, iclass 14, count 0 2006.281.08:06:59.94#ibcon#about to read 4, iclass 14, count 0 2006.281.08:06:59.94#ibcon#read 4, iclass 14, count 0 2006.281.08:06:59.94#ibcon#about to read 5, iclass 14, count 0 2006.281.08:06:59.94#ibcon#read 5, iclass 14, count 0 2006.281.08:06:59.94#ibcon#about to read 6, iclass 14, count 0 2006.281.08:06:59.94#ibcon#read 6, iclass 14, count 0 2006.281.08:06:59.94#ibcon#end of sib2, iclass 14, count 0 2006.281.08:06:59.94#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:06:59.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:06:59.94#ibcon#[25=USB\r\n] 2006.281.08:06:59.94#ibcon#*before write, iclass 14, count 0 2006.281.08:06:59.94#ibcon#enter sib2, iclass 14, count 0 2006.281.08:06:59.94#ibcon#flushed, iclass 14, count 0 2006.281.08:06:59.94#ibcon#about to write, iclass 14, count 0 2006.281.08:06:59.94#ibcon#wrote, iclass 14, count 0 2006.281.08:06:59.94#ibcon#about to read 3, iclass 14, count 0 2006.281.08:06:59.97#ibcon#read 3, iclass 14, count 0 2006.281.08:06:59.97#ibcon#about to read 4, iclass 14, count 0 2006.281.08:06:59.97#ibcon#read 4, iclass 14, count 0 2006.281.08:06:59.97#ibcon#about to read 5, iclass 14, count 0 2006.281.08:06:59.97#ibcon#read 5, iclass 14, count 0 2006.281.08:06:59.97#ibcon#about to read 6, iclass 14, count 0 2006.281.08:06:59.97#ibcon#read 6, iclass 14, count 0 2006.281.08:06:59.97#ibcon#end of sib2, iclass 14, count 0 2006.281.08:06:59.97#ibcon#*after write, iclass 14, count 0 2006.281.08:06:59.97#ibcon#*before return 0, iclass 14, count 0 2006.281.08:06:59.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:06:59.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:06:59.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:06:59.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:06:59.97$vc4f8/valo=3,672.99 2006.281.08:06:59.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.08:06:59.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.08:06:59.97#ibcon#ireg 17 cls_cnt 0 2006.281.08:06:59.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:06:59.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:06:59.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:06:59.97#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:06:59.97#ibcon#first serial, iclass 16, count 0 2006.281.08:06:59.97#ibcon#enter sib2, iclass 16, count 0 2006.281.08:06:59.97#ibcon#flushed, iclass 16, count 0 2006.281.08:06:59.97#ibcon#about to write, iclass 16, count 0 2006.281.08:06:59.97#ibcon#wrote, iclass 16, count 0 2006.281.08:06:59.97#ibcon#about to read 3, iclass 16, count 0 2006.281.08:06:59.99#ibcon#read 3, iclass 16, count 0 2006.281.08:06:59.99#ibcon#about to read 4, iclass 16, count 0 2006.281.08:06:59.99#ibcon#read 4, iclass 16, count 0 2006.281.08:06:59.99#ibcon#about to read 5, iclass 16, count 0 2006.281.08:06:59.99#ibcon#read 5, iclass 16, count 0 2006.281.08:06:59.99#ibcon#about to read 6, iclass 16, count 0 2006.281.08:06:59.99#ibcon#read 6, iclass 16, count 0 2006.281.08:06:59.99#ibcon#end of sib2, iclass 16, count 0 2006.281.08:06:59.99#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:06:59.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:06:59.99#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:06:59.99#ibcon#*before write, iclass 16, count 0 2006.281.08:06:59.99#ibcon#enter sib2, iclass 16, count 0 2006.281.08:06:59.99#ibcon#flushed, iclass 16, count 0 2006.281.08:06:59.99#ibcon#about to write, iclass 16, count 0 2006.281.08:06:59.99#ibcon#wrote, iclass 16, count 0 2006.281.08:06:59.99#ibcon#about to read 3, iclass 16, count 0 2006.281.08:07:00.04#ibcon#read 3, iclass 16, count 0 2006.281.08:07:00.04#ibcon#about to read 4, iclass 16, count 0 2006.281.08:07:00.04#ibcon#read 4, iclass 16, count 0 2006.281.08:07:00.04#ibcon#about to read 5, iclass 16, count 0 2006.281.08:07:00.04#ibcon#read 5, iclass 16, count 0 2006.281.08:07:00.04#ibcon#about to read 6, iclass 16, count 0 2006.281.08:07:00.04#ibcon#read 6, iclass 16, count 0 2006.281.08:07:00.04#ibcon#end of sib2, iclass 16, count 0 2006.281.08:07:00.04#ibcon#*after write, iclass 16, count 0 2006.281.08:07:00.04#ibcon#*before return 0, iclass 16, count 0 2006.281.08:07:00.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:00.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:00.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:07:00.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:07:00.04$vc4f8/va=3,6 2006.281.08:07:00.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.08:07:00.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.08:07:00.04#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:00.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:00.09#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:00.09#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:00.09#ibcon#enter wrdev, iclass 18, count 2 2006.281.08:07:00.09#ibcon#first serial, iclass 18, count 2 2006.281.08:07:00.09#ibcon#enter sib2, iclass 18, count 2 2006.281.08:07:00.09#ibcon#flushed, iclass 18, count 2 2006.281.08:07:00.09#ibcon#about to write, iclass 18, count 2 2006.281.08:07:00.09#ibcon#wrote, iclass 18, count 2 2006.281.08:07:00.09#ibcon#about to read 3, iclass 18, count 2 2006.281.08:07:00.11#ibcon#read 3, iclass 18, count 2 2006.281.08:07:00.11#ibcon#about to read 4, iclass 18, count 2 2006.281.08:07:00.11#ibcon#read 4, iclass 18, count 2 2006.281.08:07:00.11#ibcon#about to read 5, iclass 18, count 2 2006.281.08:07:00.11#ibcon#read 5, iclass 18, count 2 2006.281.08:07:00.11#ibcon#about to read 6, iclass 18, count 2 2006.281.08:07:00.11#ibcon#read 6, iclass 18, count 2 2006.281.08:07:00.11#ibcon#end of sib2, iclass 18, count 2 2006.281.08:07:00.11#ibcon#*mode == 0, iclass 18, count 2 2006.281.08:07:00.11#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.08:07:00.11#ibcon#[25=AT03-06\r\n] 2006.281.08:07:00.11#ibcon#*before write, iclass 18, count 2 2006.281.08:07:00.11#ibcon#enter sib2, iclass 18, count 2 2006.281.08:07:00.11#ibcon#flushed, iclass 18, count 2 2006.281.08:07:00.11#ibcon#about to write, iclass 18, count 2 2006.281.08:07:00.11#ibcon#wrote, iclass 18, count 2 2006.281.08:07:00.11#ibcon#about to read 3, iclass 18, count 2 2006.281.08:07:00.14#ibcon#read 3, iclass 18, count 2 2006.281.08:07:00.14#ibcon#about to read 4, iclass 18, count 2 2006.281.08:07:00.14#ibcon#read 4, iclass 18, count 2 2006.281.08:07:00.14#ibcon#about to read 5, iclass 18, count 2 2006.281.08:07:00.14#ibcon#read 5, iclass 18, count 2 2006.281.08:07:00.14#ibcon#about to read 6, iclass 18, count 2 2006.281.08:07:00.14#ibcon#read 6, iclass 18, count 2 2006.281.08:07:00.14#ibcon#end of sib2, iclass 18, count 2 2006.281.08:07:00.14#ibcon#*after write, iclass 18, count 2 2006.281.08:07:00.14#ibcon#*before return 0, iclass 18, count 2 2006.281.08:07:00.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:00.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:00.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.08:07:00.14#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:00.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:00.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:00.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:00.26#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:07:00.26#ibcon#first serial, iclass 18, count 0 2006.281.08:07:00.26#ibcon#enter sib2, iclass 18, count 0 2006.281.08:07:00.26#ibcon#flushed, iclass 18, count 0 2006.281.08:07:00.26#ibcon#about to write, iclass 18, count 0 2006.281.08:07:00.26#ibcon#wrote, iclass 18, count 0 2006.281.08:07:00.26#ibcon#about to read 3, iclass 18, count 0 2006.281.08:07:00.28#ibcon#read 3, iclass 18, count 0 2006.281.08:07:00.28#ibcon#about to read 4, iclass 18, count 0 2006.281.08:07:00.28#ibcon#read 4, iclass 18, count 0 2006.281.08:07:00.28#ibcon#about to read 5, iclass 18, count 0 2006.281.08:07:00.28#ibcon#read 5, iclass 18, count 0 2006.281.08:07:00.28#ibcon#about to read 6, iclass 18, count 0 2006.281.08:07:00.28#ibcon#read 6, iclass 18, count 0 2006.281.08:07:00.28#ibcon#end of sib2, iclass 18, count 0 2006.281.08:07:00.28#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:07:00.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:07:00.28#ibcon#[25=USB\r\n] 2006.281.08:07:00.28#ibcon#*before write, iclass 18, count 0 2006.281.08:07:00.28#ibcon#enter sib2, iclass 18, count 0 2006.281.08:07:00.28#ibcon#flushed, iclass 18, count 0 2006.281.08:07:00.28#ibcon#about to write, iclass 18, count 0 2006.281.08:07:00.28#ibcon#wrote, iclass 18, count 0 2006.281.08:07:00.28#ibcon#about to read 3, iclass 18, count 0 2006.281.08:07:00.31#ibcon#read 3, iclass 18, count 0 2006.281.08:07:00.31#ibcon#about to read 4, iclass 18, count 0 2006.281.08:07:00.31#ibcon#read 4, iclass 18, count 0 2006.281.08:07:00.31#ibcon#about to read 5, iclass 18, count 0 2006.281.08:07:00.31#ibcon#read 5, iclass 18, count 0 2006.281.08:07:00.31#ibcon#about to read 6, iclass 18, count 0 2006.281.08:07:00.31#ibcon#read 6, iclass 18, count 0 2006.281.08:07:00.31#ibcon#end of sib2, iclass 18, count 0 2006.281.08:07:00.31#ibcon#*after write, iclass 18, count 0 2006.281.08:07:00.31#ibcon#*before return 0, iclass 18, count 0 2006.281.08:07:00.31#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:00.31#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:00.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:07:00.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:07:00.31$vc4f8/valo=4,832.99 2006.281.08:07:00.31#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.08:07:00.31#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.08:07:00.31#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:00.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:00.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:00.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:00.31#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:07:00.31#ibcon#first serial, iclass 20, count 0 2006.281.08:07:00.31#ibcon#enter sib2, iclass 20, count 0 2006.281.08:07:00.31#ibcon#flushed, iclass 20, count 0 2006.281.08:07:00.31#ibcon#about to write, iclass 20, count 0 2006.281.08:07:00.31#ibcon#wrote, iclass 20, count 0 2006.281.08:07:00.31#ibcon#about to read 3, iclass 20, count 0 2006.281.08:07:00.33#ibcon#read 3, iclass 20, count 0 2006.281.08:07:00.33#ibcon#about to read 4, iclass 20, count 0 2006.281.08:07:00.33#ibcon#read 4, iclass 20, count 0 2006.281.08:07:00.33#ibcon#about to read 5, iclass 20, count 0 2006.281.08:07:00.33#ibcon#read 5, iclass 20, count 0 2006.281.08:07:00.33#ibcon#about to read 6, iclass 20, count 0 2006.281.08:07:00.33#ibcon#read 6, iclass 20, count 0 2006.281.08:07:00.33#ibcon#end of sib2, iclass 20, count 0 2006.281.08:07:00.33#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:07:00.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:07:00.33#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:07:00.33#ibcon#*before write, iclass 20, count 0 2006.281.08:07:00.33#ibcon#enter sib2, iclass 20, count 0 2006.281.08:07:00.33#ibcon#flushed, iclass 20, count 0 2006.281.08:07:00.33#ibcon#about to write, iclass 20, count 0 2006.281.08:07:00.33#ibcon#wrote, iclass 20, count 0 2006.281.08:07:00.33#ibcon#about to read 3, iclass 20, count 0 2006.281.08:07:00.37#ibcon#read 3, iclass 20, count 0 2006.281.08:07:00.37#ibcon#about to read 4, iclass 20, count 0 2006.281.08:07:00.37#ibcon#read 4, iclass 20, count 0 2006.281.08:07:00.37#ibcon#about to read 5, iclass 20, count 0 2006.281.08:07:00.37#ibcon#read 5, iclass 20, count 0 2006.281.08:07:00.37#ibcon#about to read 6, iclass 20, count 0 2006.281.08:07:00.37#ibcon#read 6, iclass 20, count 0 2006.281.08:07:00.37#ibcon#end of sib2, iclass 20, count 0 2006.281.08:07:00.37#ibcon#*after write, iclass 20, count 0 2006.281.08:07:00.37#ibcon#*before return 0, iclass 20, count 0 2006.281.08:07:00.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:00.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:00.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:07:00.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:07:00.37$vc4f8/va=4,6 2006.281.08:07:00.37#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.08:07:00.37#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.08:07:00.37#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:00.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:00.43#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:00.43#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:00.43#ibcon#enter wrdev, iclass 22, count 2 2006.281.08:07:00.43#ibcon#first serial, iclass 22, count 2 2006.281.08:07:00.43#ibcon#enter sib2, iclass 22, count 2 2006.281.08:07:00.43#ibcon#flushed, iclass 22, count 2 2006.281.08:07:00.43#ibcon#about to write, iclass 22, count 2 2006.281.08:07:00.43#ibcon#wrote, iclass 22, count 2 2006.281.08:07:00.43#ibcon#about to read 3, iclass 22, count 2 2006.281.08:07:00.45#ibcon#read 3, iclass 22, count 2 2006.281.08:07:00.45#ibcon#about to read 4, iclass 22, count 2 2006.281.08:07:00.45#ibcon#read 4, iclass 22, count 2 2006.281.08:07:00.45#ibcon#about to read 5, iclass 22, count 2 2006.281.08:07:00.45#ibcon#read 5, iclass 22, count 2 2006.281.08:07:00.45#ibcon#about to read 6, iclass 22, count 2 2006.281.08:07:00.45#ibcon#read 6, iclass 22, count 2 2006.281.08:07:00.45#ibcon#end of sib2, iclass 22, count 2 2006.281.08:07:00.45#ibcon#*mode == 0, iclass 22, count 2 2006.281.08:07:00.45#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.08:07:00.45#ibcon#[25=AT04-06\r\n] 2006.281.08:07:00.45#ibcon#*before write, iclass 22, count 2 2006.281.08:07:00.45#ibcon#enter sib2, iclass 22, count 2 2006.281.08:07:00.45#ibcon#flushed, iclass 22, count 2 2006.281.08:07:00.45#ibcon#about to write, iclass 22, count 2 2006.281.08:07:00.45#ibcon#wrote, iclass 22, count 2 2006.281.08:07:00.45#ibcon#about to read 3, iclass 22, count 2 2006.281.08:07:00.49#ibcon#read 3, iclass 22, count 2 2006.281.08:07:00.49#ibcon#about to read 4, iclass 22, count 2 2006.281.08:07:00.49#ibcon#read 4, iclass 22, count 2 2006.281.08:07:00.49#ibcon#about to read 5, iclass 22, count 2 2006.281.08:07:00.49#ibcon#read 5, iclass 22, count 2 2006.281.08:07:00.49#ibcon#about to read 6, iclass 22, count 2 2006.281.08:07:00.49#ibcon#read 6, iclass 22, count 2 2006.281.08:07:00.49#ibcon#end of sib2, iclass 22, count 2 2006.281.08:07:00.49#ibcon#*after write, iclass 22, count 2 2006.281.08:07:00.49#ibcon#*before return 0, iclass 22, count 2 2006.281.08:07:00.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:00.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:00.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.08:07:00.49#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:00.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:00.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:00.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:00.61#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:07:00.61#ibcon#first serial, iclass 22, count 0 2006.281.08:07:00.61#ibcon#enter sib2, iclass 22, count 0 2006.281.08:07:00.61#ibcon#flushed, iclass 22, count 0 2006.281.08:07:00.61#ibcon#about to write, iclass 22, count 0 2006.281.08:07:00.61#ibcon#wrote, iclass 22, count 0 2006.281.08:07:00.61#ibcon#about to read 3, iclass 22, count 0 2006.281.08:07:00.63#ibcon#read 3, iclass 22, count 0 2006.281.08:07:00.63#ibcon#about to read 4, iclass 22, count 0 2006.281.08:07:00.63#ibcon#read 4, iclass 22, count 0 2006.281.08:07:00.63#ibcon#about to read 5, iclass 22, count 0 2006.281.08:07:00.63#ibcon#read 5, iclass 22, count 0 2006.281.08:07:00.63#ibcon#about to read 6, iclass 22, count 0 2006.281.08:07:00.63#ibcon#read 6, iclass 22, count 0 2006.281.08:07:00.63#ibcon#end of sib2, iclass 22, count 0 2006.281.08:07:00.63#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:07:00.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:07:00.63#ibcon#[25=USB\r\n] 2006.281.08:07:00.63#ibcon#*before write, iclass 22, count 0 2006.281.08:07:00.63#ibcon#enter sib2, iclass 22, count 0 2006.281.08:07:00.63#ibcon#flushed, iclass 22, count 0 2006.281.08:07:00.63#ibcon#about to write, iclass 22, count 0 2006.281.08:07:00.63#ibcon#wrote, iclass 22, count 0 2006.281.08:07:00.63#ibcon#about to read 3, iclass 22, count 0 2006.281.08:07:00.66#ibcon#read 3, iclass 22, count 0 2006.281.08:07:00.66#ibcon#about to read 4, iclass 22, count 0 2006.281.08:07:00.66#ibcon#read 4, iclass 22, count 0 2006.281.08:07:00.66#ibcon#about to read 5, iclass 22, count 0 2006.281.08:07:00.66#ibcon#read 5, iclass 22, count 0 2006.281.08:07:00.66#ibcon#about to read 6, iclass 22, count 0 2006.281.08:07:00.66#ibcon#read 6, iclass 22, count 0 2006.281.08:07:00.66#ibcon#end of sib2, iclass 22, count 0 2006.281.08:07:00.66#ibcon#*after write, iclass 22, count 0 2006.281.08:07:00.66#ibcon#*before return 0, iclass 22, count 0 2006.281.08:07:00.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:00.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:00.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:07:00.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:07:00.66$vc4f8/valo=5,652.99 2006.281.08:07:00.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.08:07:00.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.08:07:00.66#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:00.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:00.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:00.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:00.66#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:07:00.66#ibcon#first serial, iclass 24, count 0 2006.281.08:07:00.66#ibcon#enter sib2, iclass 24, count 0 2006.281.08:07:00.66#ibcon#flushed, iclass 24, count 0 2006.281.08:07:00.66#ibcon#about to write, iclass 24, count 0 2006.281.08:07:00.66#ibcon#wrote, iclass 24, count 0 2006.281.08:07:00.66#ibcon#about to read 3, iclass 24, count 0 2006.281.08:07:00.68#ibcon#read 3, iclass 24, count 0 2006.281.08:07:00.69#ibcon#about to read 4, iclass 24, count 0 2006.281.08:07:00.69#ibcon#read 4, iclass 24, count 0 2006.281.08:07:00.69#ibcon#about to read 5, iclass 24, count 0 2006.281.08:07:00.69#ibcon#read 5, iclass 24, count 0 2006.281.08:07:00.69#ibcon#about to read 6, iclass 24, count 0 2006.281.08:07:00.69#ibcon#read 6, iclass 24, count 0 2006.281.08:07:00.69#ibcon#end of sib2, iclass 24, count 0 2006.281.08:07:00.69#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:07:00.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:07:00.69#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:07:00.69#ibcon#*before write, iclass 24, count 0 2006.281.08:07:00.69#ibcon#enter sib2, iclass 24, count 0 2006.281.08:07:00.69#ibcon#flushed, iclass 24, count 0 2006.281.08:07:00.69#ibcon#about to write, iclass 24, count 0 2006.281.08:07:00.69#ibcon#wrote, iclass 24, count 0 2006.281.08:07:00.69#ibcon#about to read 3, iclass 24, count 0 2006.281.08:07:00.73#ibcon#read 3, iclass 24, count 0 2006.281.08:07:00.73#ibcon#about to read 4, iclass 24, count 0 2006.281.08:07:00.73#ibcon#read 4, iclass 24, count 0 2006.281.08:07:00.73#ibcon#about to read 5, iclass 24, count 0 2006.281.08:07:00.73#ibcon#read 5, iclass 24, count 0 2006.281.08:07:00.73#ibcon#about to read 6, iclass 24, count 0 2006.281.08:07:00.73#ibcon#read 6, iclass 24, count 0 2006.281.08:07:00.73#ibcon#end of sib2, iclass 24, count 0 2006.281.08:07:00.73#ibcon#*after write, iclass 24, count 0 2006.281.08:07:00.73#ibcon#*before return 0, iclass 24, count 0 2006.281.08:07:00.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:00.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:00.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:07:00.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:07:00.73$vc4f8/va=5,7 2006.281.08:07:00.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.08:07:00.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.08:07:00.73#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:00.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:00.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:00.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:00.78#ibcon#enter wrdev, iclass 26, count 2 2006.281.08:07:00.78#ibcon#first serial, iclass 26, count 2 2006.281.08:07:00.78#ibcon#enter sib2, iclass 26, count 2 2006.281.08:07:00.78#ibcon#flushed, iclass 26, count 2 2006.281.08:07:00.78#ibcon#about to write, iclass 26, count 2 2006.281.08:07:00.78#ibcon#wrote, iclass 26, count 2 2006.281.08:07:00.78#ibcon#about to read 3, iclass 26, count 2 2006.281.08:07:00.80#ibcon#read 3, iclass 26, count 2 2006.281.08:07:00.80#ibcon#about to read 4, iclass 26, count 2 2006.281.08:07:00.80#ibcon#read 4, iclass 26, count 2 2006.281.08:07:00.80#ibcon#about to read 5, iclass 26, count 2 2006.281.08:07:00.80#ibcon#read 5, iclass 26, count 2 2006.281.08:07:00.80#ibcon#about to read 6, iclass 26, count 2 2006.281.08:07:00.80#ibcon#read 6, iclass 26, count 2 2006.281.08:07:00.80#ibcon#end of sib2, iclass 26, count 2 2006.281.08:07:00.80#ibcon#*mode == 0, iclass 26, count 2 2006.281.08:07:00.80#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.08:07:00.80#ibcon#[25=AT05-07\r\n] 2006.281.08:07:00.80#ibcon#*before write, iclass 26, count 2 2006.281.08:07:00.80#ibcon#enter sib2, iclass 26, count 2 2006.281.08:07:00.80#ibcon#flushed, iclass 26, count 2 2006.281.08:07:00.80#ibcon#about to write, iclass 26, count 2 2006.281.08:07:00.80#ibcon#wrote, iclass 26, count 2 2006.281.08:07:00.80#ibcon#about to read 3, iclass 26, count 2 2006.281.08:07:00.83#ibcon#read 3, iclass 26, count 2 2006.281.08:07:00.83#ibcon#about to read 4, iclass 26, count 2 2006.281.08:07:00.83#ibcon#read 4, iclass 26, count 2 2006.281.08:07:00.83#ibcon#about to read 5, iclass 26, count 2 2006.281.08:07:00.83#ibcon#read 5, iclass 26, count 2 2006.281.08:07:00.83#ibcon#about to read 6, iclass 26, count 2 2006.281.08:07:00.83#ibcon#read 6, iclass 26, count 2 2006.281.08:07:00.83#ibcon#end of sib2, iclass 26, count 2 2006.281.08:07:00.83#ibcon#*after write, iclass 26, count 2 2006.281.08:07:00.83#ibcon#*before return 0, iclass 26, count 2 2006.281.08:07:00.83#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:00.83#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:00.83#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.08:07:00.83#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:00.83#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:00.95#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:00.95#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:00.95#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:07:00.95#ibcon#first serial, iclass 26, count 0 2006.281.08:07:00.95#ibcon#enter sib2, iclass 26, count 0 2006.281.08:07:00.95#ibcon#flushed, iclass 26, count 0 2006.281.08:07:00.95#ibcon#about to write, iclass 26, count 0 2006.281.08:07:00.95#ibcon#wrote, iclass 26, count 0 2006.281.08:07:00.95#ibcon#about to read 3, iclass 26, count 0 2006.281.08:07:00.97#ibcon#read 3, iclass 26, count 0 2006.281.08:07:00.97#ibcon#about to read 4, iclass 26, count 0 2006.281.08:07:00.97#ibcon#read 4, iclass 26, count 0 2006.281.08:07:00.97#ibcon#about to read 5, iclass 26, count 0 2006.281.08:07:00.97#ibcon#read 5, iclass 26, count 0 2006.281.08:07:00.97#ibcon#about to read 6, iclass 26, count 0 2006.281.08:07:00.97#ibcon#read 6, iclass 26, count 0 2006.281.08:07:00.97#ibcon#end of sib2, iclass 26, count 0 2006.281.08:07:00.97#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:07:00.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:07:00.97#ibcon#[25=USB\r\n] 2006.281.08:07:00.97#ibcon#*before write, iclass 26, count 0 2006.281.08:07:00.97#ibcon#enter sib2, iclass 26, count 0 2006.281.08:07:00.97#ibcon#flushed, iclass 26, count 0 2006.281.08:07:00.97#ibcon#about to write, iclass 26, count 0 2006.281.08:07:00.97#ibcon#wrote, iclass 26, count 0 2006.281.08:07:00.97#ibcon#about to read 3, iclass 26, count 0 2006.281.08:07:01.00#ibcon#read 3, iclass 26, count 0 2006.281.08:07:01.00#ibcon#about to read 4, iclass 26, count 0 2006.281.08:07:01.00#ibcon#read 4, iclass 26, count 0 2006.281.08:07:01.00#ibcon#about to read 5, iclass 26, count 0 2006.281.08:07:01.00#ibcon#read 5, iclass 26, count 0 2006.281.08:07:01.00#ibcon#about to read 6, iclass 26, count 0 2006.281.08:07:01.00#ibcon#read 6, iclass 26, count 0 2006.281.08:07:01.00#ibcon#end of sib2, iclass 26, count 0 2006.281.08:07:01.00#ibcon#*after write, iclass 26, count 0 2006.281.08:07:01.00#ibcon#*before return 0, iclass 26, count 0 2006.281.08:07:01.00#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:01.00#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:01.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:07:01.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:07:01.00$vc4f8/valo=6,772.99 2006.281.08:07:01.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:07:01.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:07:01.00#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:01.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:01.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:01.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:01.00#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:07:01.00#ibcon#first serial, iclass 28, count 0 2006.281.08:07:01.00#ibcon#enter sib2, iclass 28, count 0 2006.281.08:07:01.00#ibcon#flushed, iclass 28, count 0 2006.281.08:07:01.00#ibcon#about to write, iclass 28, count 0 2006.281.08:07:01.00#ibcon#wrote, iclass 28, count 0 2006.281.08:07:01.00#ibcon#about to read 3, iclass 28, count 0 2006.281.08:07:01.02#ibcon#read 3, iclass 28, count 0 2006.281.08:07:01.02#ibcon#about to read 4, iclass 28, count 0 2006.281.08:07:01.02#ibcon#read 4, iclass 28, count 0 2006.281.08:07:01.02#ibcon#about to read 5, iclass 28, count 0 2006.281.08:07:01.02#ibcon#read 5, iclass 28, count 0 2006.281.08:07:01.02#ibcon#about to read 6, iclass 28, count 0 2006.281.08:07:01.02#ibcon#read 6, iclass 28, count 0 2006.281.08:07:01.02#ibcon#end of sib2, iclass 28, count 0 2006.281.08:07:01.02#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:07:01.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:07:01.02#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:07:01.02#ibcon#*before write, iclass 28, count 0 2006.281.08:07:01.02#ibcon#enter sib2, iclass 28, count 0 2006.281.08:07:01.02#ibcon#flushed, iclass 28, count 0 2006.281.08:07:01.02#ibcon#about to write, iclass 28, count 0 2006.281.08:07:01.02#ibcon#wrote, iclass 28, count 0 2006.281.08:07:01.02#ibcon#about to read 3, iclass 28, count 0 2006.281.08:07:01.06#ibcon#read 3, iclass 28, count 0 2006.281.08:07:01.06#ibcon#about to read 4, iclass 28, count 0 2006.281.08:07:01.06#ibcon#read 4, iclass 28, count 0 2006.281.08:07:01.06#ibcon#about to read 5, iclass 28, count 0 2006.281.08:07:01.06#ibcon#read 5, iclass 28, count 0 2006.281.08:07:01.06#ibcon#about to read 6, iclass 28, count 0 2006.281.08:07:01.06#ibcon#read 6, iclass 28, count 0 2006.281.08:07:01.06#ibcon#end of sib2, iclass 28, count 0 2006.281.08:07:01.06#ibcon#*after write, iclass 28, count 0 2006.281.08:07:01.06#ibcon#*before return 0, iclass 28, count 0 2006.281.08:07:01.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:01.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:01.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:07:01.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:07:01.06$vc4f8/va=6,6 2006.281.08:07:01.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.08:07:01.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.08:07:01.06#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:01.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:01.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:01.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:01.12#ibcon#enter wrdev, iclass 30, count 2 2006.281.08:07:01.12#ibcon#first serial, iclass 30, count 2 2006.281.08:07:01.12#ibcon#enter sib2, iclass 30, count 2 2006.281.08:07:01.12#ibcon#flushed, iclass 30, count 2 2006.281.08:07:01.12#ibcon#about to write, iclass 30, count 2 2006.281.08:07:01.12#ibcon#wrote, iclass 30, count 2 2006.281.08:07:01.12#ibcon#about to read 3, iclass 30, count 2 2006.281.08:07:01.14#ibcon#read 3, iclass 30, count 2 2006.281.08:07:01.14#ibcon#about to read 4, iclass 30, count 2 2006.281.08:07:01.14#ibcon#read 4, iclass 30, count 2 2006.281.08:07:01.14#ibcon#about to read 5, iclass 30, count 2 2006.281.08:07:01.14#ibcon#read 5, iclass 30, count 2 2006.281.08:07:01.14#ibcon#about to read 6, iclass 30, count 2 2006.281.08:07:01.14#ibcon#read 6, iclass 30, count 2 2006.281.08:07:01.14#ibcon#end of sib2, iclass 30, count 2 2006.281.08:07:01.14#ibcon#*mode == 0, iclass 30, count 2 2006.281.08:07:01.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.08:07:01.14#ibcon#[25=AT06-06\r\n] 2006.281.08:07:01.14#ibcon#*before write, iclass 30, count 2 2006.281.08:07:01.14#ibcon#enter sib2, iclass 30, count 2 2006.281.08:07:01.14#ibcon#flushed, iclass 30, count 2 2006.281.08:07:01.14#ibcon#about to write, iclass 30, count 2 2006.281.08:07:01.14#ibcon#wrote, iclass 30, count 2 2006.281.08:07:01.14#ibcon#about to read 3, iclass 30, count 2 2006.281.08:07:01.18#ibcon#read 3, iclass 30, count 2 2006.281.08:07:01.18#ibcon#about to read 4, iclass 30, count 2 2006.281.08:07:01.18#ibcon#read 4, iclass 30, count 2 2006.281.08:07:01.18#ibcon#about to read 5, iclass 30, count 2 2006.281.08:07:01.18#ibcon#read 5, iclass 30, count 2 2006.281.08:07:01.18#ibcon#about to read 6, iclass 30, count 2 2006.281.08:07:01.18#ibcon#read 6, iclass 30, count 2 2006.281.08:07:01.18#ibcon#end of sib2, iclass 30, count 2 2006.281.08:07:01.18#ibcon#*after write, iclass 30, count 2 2006.281.08:07:01.18#ibcon#*before return 0, iclass 30, count 2 2006.281.08:07:01.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:01.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:01.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.08:07:01.18#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:01.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:07:01.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:07:01.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:07:01.30#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:07:01.30#ibcon#first serial, iclass 30, count 0 2006.281.08:07:01.30#ibcon#enter sib2, iclass 30, count 0 2006.281.08:07:01.30#ibcon#flushed, iclass 30, count 0 2006.281.08:07:01.30#ibcon#about to write, iclass 30, count 0 2006.281.08:07:01.30#ibcon#wrote, iclass 30, count 0 2006.281.08:07:01.30#ibcon#about to read 3, iclass 30, count 0 2006.281.08:07:01.32#ibcon#read 3, iclass 30, count 0 2006.281.08:07:01.32#ibcon#about to read 4, iclass 30, count 0 2006.281.08:07:01.32#ibcon#read 4, iclass 30, count 0 2006.281.08:07:01.32#ibcon#about to read 5, iclass 30, count 0 2006.281.08:07:01.32#ibcon#read 5, iclass 30, count 0 2006.281.08:07:01.32#ibcon#about to read 6, iclass 30, count 0 2006.281.08:07:01.32#ibcon#read 6, iclass 30, count 0 2006.281.08:07:01.32#ibcon#end of sib2, iclass 30, count 0 2006.281.08:07:01.32#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:07:01.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:07:01.32#ibcon#[25=USB\r\n] 2006.281.08:07:01.32#ibcon#*before write, iclass 30, count 0 2006.281.08:07:01.32#ibcon#enter sib2, iclass 30, count 0 2006.281.08:07:01.32#ibcon#flushed, iclass 30, count 0 2006.281.08:07:01.32#ibcon#about to write, iclass 30, count 0 2006.281.08:07:01.32#ibcon#wrote, iclass 30, count 0 2006.281.08:07:01.32#ibcon#about to read 3, iclass 30, count 0 2006.281.08:07:01.35#ibcon#read 3, iclass 30, count 0 2006.281.08:07:01.35#ibcon#about to read 4, iclass 30, count 0 2006.281.08:07:01.35#ibcon#read 4, iclass 30, count 0 2006.281.08:07:01.35#ibcon#about to read 5, iclass 30, count 0 2006.281.08:07:01.35#ibcon#read 5, iclass 30, count 0 2006.281.08:07:01.35#ibcon#about to read 6, iclass 30, count 0 2006.281.08:07:01.35#ibcon#read 6, iclass 30, count 0 2006.281.08:07:01.35#ibcon#end of sib2, iclass 30, count 0 2006.281.08:07:01.35#ibcon#*after write, iclass 30, count 0 2006.281.08:07:01.35#ibcon#*before return 0, iclass 30, count 0 2006.281.08:07:01.35#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:07:01.35#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:07:01.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:07:01.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:07:01.35$vc4f8/valo=7,832.99 2006.281.08:07:01.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.08:07:01.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.08:07:01.35#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:01.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:07:01.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:07:01.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:07:01.35#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:07:01.35#ibcon#first serial, iclass 32, count 0 2006.281.08:07:01.35#ibcon#enter sib2, iclass 32, count 0 2006.281.08:07:01.35#ibcon#flushed, iclass 32, count 0 2006.281.08:07:01.35#ibcon#about to write, iclass 32, count 0 2006.281.08:07:01.35#ibcon#wrote, iclass 32, count 0 2006.281.08:07:01.35#ibcon#about to read 3, iclass 32, count 0 2006.281.08:07:01.37#ibcon#read 3, iclass 32, count 0 2006.281.08:07:01.37#ibcon#about to read 4, iclass 32, count 0 2006.281.08:07:01.37#ibcon#read 4, iclass 32, count 0 2006.281.08:07:01.37#ibcon#about to read 5, iclass 32, count 0 2006.281.08:07:01.37#ibcon#read 5, iclass 32, count 0 2006.281.08:07:01.37#ibcon#about to read 6, iclass 32, count 0 2006.281.08:07:01.37#ibcon#read 6, iclass 32, count 0 2006.281.08:07:01.37#ibcon#end of sib2, iclass 32, count 0 2006.281.08:07:01.37#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:07:01.37#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:07:01.37#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:07:01.37#ibcon#*before write, iclass 32, count 0 2006.281.08:07:01.37#ibcon#enter sib2, iclass 32, count 0 2006.281.08:07:01.37#ibcon#flushed, iclass 32, count 0 2006.281.08:07:01.37#ibcon#about to write, iclass 32, count 0 2006.281.08:07:01.37#ibcon#wrote, iclass 32, count 0 2006.281.08:07:01.37#ibcon#about to read 3, iclass 32, count 0 2006.281.08:07:01.41#ibcon#read 3, iclass 32, count 0 2006.281.08:07:01.41#ibcon#about to read 4, iclass 32, count 0 2006.281.08:07:01.41#ibcon#read 4, iclass 32, count 0 2006.281.08:07:01.41#ibcon#about to read 5, iclass 32, count 0 2006.281.08:07:01.41#ibcon#read 5, iclass 32, count 0 2006.281.08:07:01.41#ibcon#about to read 6, iclass 32, count 0 2006.281.08:07:01.41#ibcon#read 6, iclass 32, count 0 2006.281.08:07:01.41#ibcon#end of sib2, iclass 32, count 0 2006.281.08:07:01.41#ibcon#*after write, iclass 32, count 0 2006.281.08:07:01.41#ibcon#*before return 0, iclass 32, count 0 2006.281.08:07:01.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:07:01.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:07:01.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:07:01.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:07:01.41$vc4f8/va=7,6 2006.281.08:07:01.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.08:07:01.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.08:07:01.41#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:01.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:07:01.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:07:01.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:07:01.47#ibcon#enter wrdev, iclass 34, count 2 2006.281.08:07:01.47#ibcon#first serial, iclass 34, count 2 2006.281.08:07:01.47#ibcon#enter sib2, iclass 34, count 2 2006.281.08:07:01.47#ibcon#flushed, iclass 34, count 2 2006.281.08:07:01.47#ibcon#about to write, iclass 34, count 2 2006.281.08:07:01.47#ibcon#wrote, iclass 34, count 2 2006.281.08:07:01.47#ibcon#about to read 3, iclass 34, count 2 2006.281.08:07:01.49#ibcon#read 3, iclass 34, count 2 2006.281.08:07:01.49#ibcon#about to read 4, iclass 34, count 2 2006.281.08:07:01.49#ibcon#read 4, iclass 34, count 2 2006.281.08:07:01.49#ibcon#about to read 5, iclass 34, count 2 2006.281.08:07:01.49#ibcon#read 5, iclass 34, count 2 2006.281.08:07:01.49#ibcon#about to read 6, iclass 34, count 2 2006.281.08:07:01.49#ibcon#read 6, iclass 34, count 2 2006.281.08:07:01.49#ibcon#end of sib2, iclass 34, count 2 2006.281.08:07:01.49#ibcon#*mode == 0, iclass 34, count 2 2006.281.08:07:01.49#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.08:07:01.49#ibcon#[25=AT07-06\r\n] 2006.281.08:07:01.49#ibcon#*before write, iclass 34, count 2 2006.281.08:07:01.49#ibcon#enter sib2, iclass 34, count 2 2006.281.08:07:01.49#ibcon#flushed, iclass 34, count 2 2006.281.08:07:01.49#ibcon#about to write, iclass 34, count 2 2006.281.08:07:01.49#ibcon#wrote, iclass 34, count 2 2006.281.08:07:01.49#ibcon#about to read 3, iclass 34, count 2 2006.281.08:07:01.52#ibcon#read 3, iclass 34, count 2 2006.281.08:07:01.52#ibcon#about to read 4, iclass 34, count 2 2006.281.08:07:01.52#ibcon#read 4, iclass 34, count 2 2006.281.08:07:01.52#ibcon#about to read 5, iclass 34, count 2 2006.281.08:07:01.52#ibcon#read 5, iclass 34, count 2 2006.281.08:07:01.52#ibcon#about to read 6, iclass 34, count 2 2006.281.08:07:01.52#ibcon#read 6, iclass 34, count 2 2006.281.08:07:01.52#ibcon#end of sib2, iclass 34, count 2 2006.281.08:07:01.52#ibcon#*after write, iclass 34, count 2 2006.281.08:07:01.52#ibcon#*before return 0, iclass 34, count 2 2006.281.08:07:01.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:07:01.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:07:01.52#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.08:07:01.52#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:01.52#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:07:01.64#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:07:01.64#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:07:01.64#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:07:01.64#ibcon#first serial, iclass 34, count 0 2006.281.08:07:01.64#ibcon#enter sib2, iclass 34, count 0 2006.281.08:07:01.64#ibcon#flushed, iclass 34, count 0 2006.281.08:07:01.64#ibcon#about to write, iclass 34, count 0 2006.281.08:07:01.64#ibcon#wrote, iclass 34, count 0 2006.281.08:07:01.64#ibcon#about to read 3, iclass 34, count 0 2006.281.08:07:01.66#ibcon#read 3, iclass 34, count 0 2006.281.08:07:01.66#ibcon#about to read 4, iclass 34, count 0 2006.281.08:07:01.66#ibcon#read 4, iclass 34, count 0 2006.281.08:07:01.66#ibcon#about to read 5, iclass 34, count 0 2006.281.08:07:01.66#ibcon#read 5, iclass 34, count 0 2006.281.08:07:01.66#ibcon#about to read 6, iclass 34, count 0 2006.281.08:07:01.66#ibcon#read 6, iclass 34, count 0 2006.281.08:07:01.66#ibcon#end of sib2, iclass 34, count 0 2006.281.08:07:01.66#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:07:01.66#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:07:01.66#ibcon#[25=USB\r\n] 2006.281.08:07:01.66#ibcon#*before write, iclass 34, count 0 2006.281.08:07:01.66#ibcon#enter sib2, iclass 34, count 0 2006.281.08:07:01.66#ibcon#flushed, iclass 34, count 0 2006.281.08:07:01.66#ibcon#about to write, iclass 34, count 0 2006.281.08:07:01.66#ibcon#wrote, iclass 34, count 0 2006.281.08:07:01.66#ibcon#about to read 3, iclass 34, count 0 2006.281.08:07:01.69#ibcon#read 3, iclass 34, count 0 2006.281.08:07:01.69#ibcon#about to read 4, iclass 34, count 0 2006.281.08:07:01.69#ibcon#read 4, iclass 34, count 0 2006.281.08:07:01.69#ibcon#about to read 5, iclass 34, count 0 2006.281.08:07:01.69#ibcon#read 5, iclass 34, count 0 2006.281.08:07:01.69#ibcon#about to read 6, iclass 34, count 0 2006.281.08:07:01.69#ibcon#read 6, iclass 34, count 0 2006.281.08:07:01.69#ibcon#end of sib2, iclass 34, count 0 2006.281.08:07:01.69#ibcon#*after write, iclass 34, count 0 2006.281.08:07:01.69#ibcon#*before return 0, iclass 34, count 0 2006.281.08:07:01.69#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:07:01.69#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:07:01.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:07:01.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:07:01.69$vc4f8/valo=8,852.99 2006.281.08:07:01.69#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.08:07:01.69#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.08:07:01.69#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:01.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:07:01.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:07:01.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:07:01.69#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:07:01.69#ibcon#first serial, iclass 36, count 0 2006.281.08:07:01.69#ibcon#enter sib2, iclass 36, count 0 2006.281.08:07:01.69#ibcon#flushed, iclass 36, count 0 2006.281.08:07:01.69#ibcon#about to write, iclass 36, count 0 2006.281.08:07:01.69#ibcon#wrote, iclass 36, count 0 2006.281.08:07:01.69#ibcon#about to read 3, iclass 36, count 0 2006.281.08:07:01.71#ibcon#read 3, iclass 36, count 0 2006.281.08:07:01.71#ibcon#about to read 4, iclass 36, count 0 2006.281.08:07:01.71#ibcon#read 4, iclass 36, count 0 2006.281.08:07:01.71#ibcon#about to read 5, iclass 36, count 0 2006.281.08:07:01.71#ibcon#read 5, iclass 36, count 0 2006.281.08:07:01.71#ibcon#about to read 6, iclass 36, count 0 2006.281.08:07:01.71#ibcon#read 6, iclass 36, count 0 2006.281.08:07:01.71#ibcon#end of sib2, iclass 36, count 0 2006.281.08:07:01.71#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:07:01.71#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:07:01.71#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:07:01.71#ibcon#*before write, iclass 36, count 0 2006.281.08:07:01.71#ibcon#enter sib2, iclass 36, count 0 2006.281.08:07:01.71#ibcon#flushed, iclass 36, count 0 2006.281.08:07:01.71#ibcon#about to write, iclass 36, count 0 2006.281.08:07:01.71#ibcon#wrote, iclass 36, count 0 2006.281.08:07:01.71#ibcon#about to read 3, iclass 36, count 0 2006.281.08:07:01.75#ibcon#read 3, iclass 36, count 0 2006.281.08:07:01.75#ibcon#about to read 4, iclass 36, count 0 2006.281.08:07:01.75#ibcon#read 4, iclass 36, count 0 2006.281.08:07:01.75#ibcon#about to read 5, iclass 36, count 0 2006.281.08:07:01.75#ibcon#read 5, iclass 36, count 0 2006.281.08:07:01.75#ibcon#about to read 6, iclass 36, count 0 2006.281.08:07:01.75#ibcon#read 6, iclass 36, count 0 2006.281.08:07:01.75#ibcon#end of sib2, iclass 36, count 0 2006.281.08:07:01.75#ibcon#*after write, iclass 36, count 0 2006.281.08:07:01.75#ibcon#*before return 0, iclass 36, count 0 2006.281.08:07:01.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:07:01.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:07:01.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:07:01.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:07:01.75$vc4f8/va=8,6 2006.281.08:07:01.75#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.08:07:01.75#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.08:07:01.75#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:01.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:07:01.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:07:01.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:07:01.81#ibcon#enter wrdev, iclass 38, count 2 2006.281.08:07:01.81#ibcon#first serial, iclass 38, count 2 2006.281.08:07:01.81#ibcon#enter sib2, iclass 38, count 2 2006.281.08:07:01.81#ibcon#flushed, iclass 38, count 2 2006.281.08:07:01.81#ibcon#about to write, iclass 38, count 2 2006.281.08:07:01.81#ibcon#wrote, iclass 38, count 2 2006.281.08:07:01.81#ibcon#about to read 3, iclass 38, count 2 2006.281.08:07:01.83#ibcon#read 3, iclass 38, count 2 2006.281.08:07:01.83#ibcon#about to read 4, iclass 38, count 2 2006.281.08:07:01.83#ibcon#read 4, iclass 38, count 2 2006.281.08:07:01.83#ibcon#about to read 5, iclass 38, count 2 2006.281.08:07:01.83#ibcon#read 5, iclass 38, count 2 2006.281.08:07:01.83#ibcon#about to read 6, iclass 38, count 2 2006.281.08:07:01.83#ibcon#read 6, iclass 38, count 2 2006.281.08:07:01.83#ibcon#end of sib2, iclass 38, count 2 2006.281.08:07:01.83#ibcon#*mode == 0, iclass 38, count 2 2006.281.08:07:01.83#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.08:07:01.83#ibcon#[25=AT08-06\r\n] 2006.281.08:07:01.83#ibcon#*before write, iclass 38, count 2 2006.281.08:07:01.83#ibcon#enter sib2, iclass 38, count 2 2006.281.08:07:01.83#ibcon#flushed, iclass 38, count 2 2006.281.08:07:01.83#ibcon#about to write, iclass 38, count 2 2006.281.08:07:01.83#ibcon#wrote, iclass 38, count 2 2006.281.08:07:01.83#ibcon#about to read 3, iclass 38, count 2 2006.281.08:07:01.86#ibcon#read 3, iclass 38, count 2 2006.281.08:07:01.86#ibcon#about to read 4, iclass 38, count 2 2006.281.08:07:01.86#ibcon#read 4, iclass 38, count 2 2006.281.08:07:01.86#ibcon#about to read 5, iclass 38, count 2 2006.281.08:07:01.86#ibcon#read 5, iclass 38, count 2 2006.281.08:07:01.86#ibcon#about to read 6, iclass 38, count 2 2006.281.08:07:01.86#ibcon#read 6, iclass 38, count 2 2006.281.08:07:01.86#ibcon#end of sib2, iclass 38, count 2 2006.281.08:07:01.86#ibcon#*after write, iclass 38, count 2 2006.281.08:07:01.86#ibcon#*before return 0, iclass 38, count 2 2006.281.08:07:01.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:07:01.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:07:01.86#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.08:07:01.86#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:01.86#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:07:01.98#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:07:01.98#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:07:01.98#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:07:01.98#ibcon#first serial, iclass 38, count 0 2006.281.08:07:01.98#ibcon#enter sib2, iclass 38, count 0 2006.281.08:07:01.98#ibcon#flushed, iclass 38, count 0 2006.281.08:07:01.98#ibcon#about to write, iclass 38, count 0 2006.281.08:07:01.98#ibcon#wrote, iclass 38, count 0 2006.281.08:07:01.98#ibcon#about to read 3, iclass 38, count 0 2006.281.08:07:02.00#ibcon#read 3, iclass 38, count 0 2006.281.08:07:02.00#ibcon#about to read 4, iclass 38, count 0 2006.281.08:07:02.00#ibcon#read 4, iclass 38, count 0 2006.281.08:07:02.00#ibcon#about to read 5, iclass 38, count 0 2006.281.08:07:02.00#ibcon#read 5, iclass 38, count 0 2006.281.08:07:02.00#ibcon#about to read 6, iclass 38, count 0 2006.281.08:07:02.00#ibcon#read 6, iclass 38, count 0 2006.281.08:07:02.00#ibcon#end of sib2, iclass 38, count 0 2006.281.08:07:02.00#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:07:02.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:07:02.00#ibcon#[25=USB\r\n] 2006.281.08:07:02.00#ibcon#*before write, iclass 38, count 0 2006.281.08:07:02.00#ibcon#enter sib2, iclass 38, count 0 2006.281.08:07:02.00#ibcon#flushed, iclass 38, count 0 2006.281.08:07:02.00#ibcon#about to write, iclass 38, count 0 2006.281.08:07:02.00#ibcon#wrote, iclass 38, count 0 2006.281.08:07:02.00#ibcon#about to read 3, iclass 38, count 0 2006.281.08:07:02.03#ibcon#read 3, iclass 38, count 0 2006.281.08:07:02.03#ibcon#about to read 4, iclass 38, count 0 2006.281.08:07:02.03#ibcon#read 4, iclass 38, count 0 2006.281.08:07:02.03#ibcon#about to read 5, iclass 38, count 0 2006.281.08:07:02.03#ibcon#read 5, iclass 38, count 0 2006.281.08:07:02.03#ibcon#about to read 6, iclass 38, count 0 2006.281.08:07:02.03#ibcon#read 6, iclass 38, count 0 2006.281.08:07:02.03#ibcon#end of sib2, iclass 38, count 0 2006.281.08:07:02.03#ibcon#*after write, iclass 38, count 0 2006.281.08:07:02.03#ibcon#*before return 0, iclass 38, count 0 2006.281.08:07:02.03#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:07:02.03#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:07:02.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:07:02.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:07:02.03$vc4f8/vblo=1,632.99 2006.281.08:07:02.03#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:07:02.03#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:07:02.03#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:02.03#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:07:02.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:07:02.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:07:02.03#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:07:02.03#ibcon#first serial, iclass 40, count 0 2006.281.08:07:02.03#ibcon#enter sib2, iclass 40, count 0 2006.281.08:07:02.03#ibcon#flushed, iclass 40, count 0 2006.281.08:07:02.03#ibcon#about to write, iclass 40, count 0 2006.281.08:07:02.03#ibcon#wrote, iclass 40, count 0 2006.281.08:07:02.03#ibcon#about to read 3, iclass 40, count 0 2006.281.08:07:02.05#ibcon#read 3, iclass 40, count 0 2006.281.08:07:02.05#ibcon#about to read 4, iclass 40, count 0 2006.281.08:07:02.05#ibcon#read 4, iclass 40, count 0 2006.281.08:07:02.05#ibcon#about to read 5, iclass 40, count 0 2006.281.08:07:02.05#ibcon#read 5, iclass 40, count 0 2006.281.08:07:02.05#ibcon#about to read 6, iclass 40, count 0 2006.281.08:07:02.05#ibcon#read 6, iclass 40, count 0 2006.281.08:07:02.05#ibcon#end of sib2, iclass 40, count 0 2006.281.08:07:02.05#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:07:02.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:07:02.05#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:07:02.05#ibcon#*before write, iclass 40, count 0 2006.281.08:07:02.05#ibcon#enter sib2, iclass 40, count 0 2006.281.08:07:02.05#ibcon#flushed, iclass 40, count 0 2006.281.08:07:02.05#ibcon#about to write, iclass 40, count 0 2006.281.08:07:02.05#ibcon#wrote, iclass 40, count 0 2006.281.08:07:02.05#ibcon#about to read 3, iclass 40, count 0 2006.281.08:07:02.09#ibcon#read 3, iclass 40, count 0 2006.281.08:07:02.09#ibcon#about to read 4, iclass 40, count 0 2006.281.08:07:02.09#ibcon#read 4, iclass 40, count 0 2006.281.08:07:02.09#ibcon#about to read 5, iclass 40, count 0 2006.281.08:07:02.09#ibcon#read 5, iclass 40, count 0 2006.281.08:07:02.09#ibcon#about to read 6, iclass 40, count 0 2006.281.08:07:02.09#ibcon#read 6, iclass 40, count 0 2006.281.08:07:02.09#ibcon#end of sib2, iclass 40, count 0 2006.281.08:07:02.09#ibcon#*after write, iclass 40, count 0 2006.281.08:07:02.09#ibcon#*before return 0, iclass 40, count 0 2006.281.08:07:02.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:07:02.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:07:02.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:07:02.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:07:02.09$vc4f8/vb=1,4 2006.281.08:07:02.09#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.08:07:02.09#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.08:07:02.09#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:02.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:07:02.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:07:02.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:07:02.09#ibcon#enter wrdev, iclass 4, count 2 2006.281.08:07:02.09#ibcon#first serial, iclass 4, count 2 2006.281.08:07:02.09#ibcon#enter sib2, iclass 4, count 2 2006.281.08:07:02.09#ibcon#flushed, iclass 4, count 2 2006.281.08:07:02.09#ibcon#about to write, iclass 4, count 2 2006.281.08:07:02.09#ibcon#wrote, iclass 4, count 2 2006.281.08:07:02.09#ibcon#about to read 3, iclass 4, count 2 2006.281.08:07:02.11#ibcon#read 3, iclass 4, count 2 2006.281.08:07:02.11#ibcon#about to read 4, iclass 4, count 2 2006.281.08:07:02.11#ibcon#read 4, iclass 4, count 2 2006.281.08:07:02.11#ibcon#about to read 5, iclass 4, count 2 2006.281.08:07:02.11#ibcon#read 5, iclass 4, count 2 2006.281.08:07:02.11#ibcon#about to read 6, iclass 4, count 2 2006.281.08:07:02.11#ibcon#read 6, iclass 4, count 2 2006.281.08:07:02.11#ibcon#end of sib2, iclass 4, count 2 2006.281.08:07:02.11#ibcon#*mode == 0, iclass 4, count 2 2006.281.08:07:02.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.08:07:02.11#ibcon#[27=AT01-04\r\n] 2006.281.08:07:02.11#ibcon#*before write, iclass 4, count 2 2006.281.08:07:02.11#ibcon#enter sib2, iclass 4, count 2 2006.281.08:07:02.11#ibcon#flushed, iclass 4, count 2 2006.281.08:07:02.11#ibcon#about to write, iclass 4, count 2 2006.281.08:07:02.11#ibcon#wrote, iclass 4, count 2 2006.281.08:07:02.11#ibcon#about to read 3, iclass 4, count 2 2006.281.08:07:02.14#ibcon#read 3, iclass 4, count 2 2006.281.08:07:02.14#ibcon#about to read 4, iclass 4, count 2 2006.281.08:07:02.14#ibcon#read 4, iclass 4, count 2 2006.281.08:07:02.14#ibcon#about to read 5, iclass 4, count 2 2006.281.08:07:02.14#ibcon#read 5, iclass 4, count 2 2006.281.08:07:02.14#ibcon#about to read 6, iclass 4, count 2 2006.281.08:07:02.14#ibcon#read 6, iclass 4, count 2 2006.281.08:07:02.14#ibcon#end of sib2, iclass 4, count 2 2006.281.08:07:02.14#ibcon#*after write, iclass 4, count 2 2006.281.08:07:02.14#ibcon#*before return 0, iclass 4, count 2 2006.281.08:07:02.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:07:02.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:07:02.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.08:07:02.14#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:02.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:07:02.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:07:02.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:07:02.26#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:07:02.26#ibcon#first serial, iclass 4, count 0 2006.281.08:07:02.26#ibcon#enter sib2, iclass 4, count 0 2006.281.08:07:02.26#ibcon#flushed, iclass 4, count 0 2006.281.08:07:02.26#ibcon#about to write, iclass 4, count 0 2006.281.08:07:02.26#ibcon#wrote, iclass 4, count 0 2006.281.08:07:02.26#ibcon#about to read 3, iclass 4, count 0 2006.281.08:07:02.28#ibcon#read 3, iclass 4, count 0 2006.281.08:07:02.28#ibcon#about to read 4, iclass 4, count 0 2006.281.08:07:02.28#ibcon#read 4, iclass 4, count 0 2006.281.08:07:02.28#ibcon#about to read 5, iclass 4, count 0 2006.281.08:07:02.28#ibcon#read 5, iclass 4, count 0 2006.281.08:07:02.28#ibcon#about to read 6, iclass 4, count 0 2006.281.08:07:02.28#ibcon#read 6, iclass 4, count 0 2006.281.08:07:02.28#ibcon#end of sib2, iclass 4, count 0 2006.281.08:07:02.28#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:07:02.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:07:02.28#ibcon#[27=USB\r\n] 2006.281.08:07:02.28#ibcon#*before write, iclass 4, count 0 2006.281.08:07:02.28#ibcon#enter sib2, iclass 4, count 0 2006.281.08:07:02.28#ibcon#flushed, iclass 4, count 0 2006.281.08:07:02.28#ibcon#about to write, iclass 4, count 0 2006.281.08:07:02.28#ibcon#wrote, iclass 4, count 0 2006.281.08:07:02.28#ibcon#about to read 3, iclass 4, count 0 2006.281.08:07:02.31#ibcon#read 3, iclass 4, count 0 2006.281.08:07:02.31#ibcon#about to read 4, iclass 4, count 0 2006.281.08:07:02.31#ibcon#read 4, iclass 4, count 0 2006.281.08:07:02.31#ibcon#about to read 5, iclass 4, count 0 2006.281.08:07:02.31#ibcon#read 5, iclass 4, count 0 2006.281.08:07:02.31#ibcon#about to read 6, iclass 4, count 0 2006.281.08:07:02.31#ibcon#read 6, iclass 4, count 0 2006.281.08:07:02.31#ibcon#end of sib2, iclass 4, count 0 2006.281.08:07:02.31#ibcon#*after write, iclass 4, count 0 2006.281.08:07:02.31#ibcon#*before return 0, iclass 4, count 0 2006.281.08:07:02.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:07:02.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:07:02.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:07:02.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:07:02.31$vc4f8/vblo=2,640.99 2006.281.08:07:02.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:07:02.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:07:02.31#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:02.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:07:02.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:07:02.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:07:02.31#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:07:02.31#ibcon#first serial, iclass 6, count 0 2006.281.08:07:02.31#ibcon#enter sib2, iclass 6, count 0 2006.281.08:07:02.31#ibcon#flushed, iclass 6, count 0 2006.281.08:07:02.31#ibcon#about to write, iclass 6, count 0 2006.281.08:07:02.31#ibcon#wrote, iclass 6, count 0 2006.281.08:07:02.31#ibcon#about to read 3, iclass 6, count 0 2006.281.08:07:02.33#ibcon#read 3, iclass 6, count 0 2006.281.08:07:02.33#ibcon#about to read 4, iclass 6, count 0 2006.281.08:07:02.33#ibcon#read 4, iclass 6, count 0 2006.281.08:07:02.33#ibcon#about to read 5, iclass 6, count 0 2006.281.08:07:02.33#ibcon#read 5, iclass 6, count 0 2006.281.08:07:02.33#ibcon#about to read 6, iclass 6, count 0 2006.281.08:07:02.33#ibcon#read 6, iclass 6, count 0 2006.281.08:07:02.33#ibcon#end of sib2, iclass 6, count 0 2006.281.08:07:02.33#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:07:02.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:07:02.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:07:02.33#ibcon#*before write, iclass 6, count 0 2006.281.08:07:02.33#ibcon#enter sib2, iclass 6, count 0 2006.281.08:07:02.33#ibcon#flushed, iclass 6, count 0 2006.281.08:07:02.33#ibcon#about to write, iclass 6, count 0 2006.281.08:07:02.33#ibcon#wrote, iclass 6, count 0 2006.281.08:07:02.33#ibcon#about to read 3, iclass 6, count 0 2006.281.08:07:02.37#ibcon#read 3, iclass 6, count 0 2006.281.08:07:02.37#ibcon#about to read 4, iclass 6, count 0 2006.281.08:07:02.37#ibcon#read 4, iclass 6, count 0 2006.281.08:07:02.37#ibcon#about to read 5, iclass 6, count 0 2006.281.08:07:02.37#ibcon#read 5, iclass 6, count 0 2006.281.08:07:02.37#ibcon#about to read 6, iclass 6, count 0 2006.281.08:07:02.37#ibcon#read 6, iclass 6, count 0 2006.281.08:07:02.37#ibcon#end of sib2, iclass 6, count 0 2006.281.08:07:02.37#ibcon#*after write, iclass 6, count 0 2006.281.08:07:02.37#ibcon#*before return 0, iclass 6, count 0 2006.281.08:07:02.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:07:02.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:07:02.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:07:02.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:07:02.37$vc4f8/vb=2,5 2006.281.08:07:02.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:07:02.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:07:02.38#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:02.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:07:02.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:07:02.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:07:02.43#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:07:02.43#ibcon#first serial, iclass 10, count 2 2006.281.08:07:02.43#ibcon#enter sib2, iclass 10, count 2 2006.281.08:07:02.43#ibcon#flushed, iclass 10, count 2 2006.281.08:07:02.43#ibcon#about to write, iclass 10, count 2 2006.281.08:07:02.43#ibcon#wrote, iclass 10, count 2 2006.281.08:07:02.43#ibcon#about to read 3, iclass 10, count 2 2006.281.08:07:02.45#ibcon#read 3, iclass 10, count 2 2006.281.08:07:02.45#ibcon#about to read 4, iclass 10, count 2 2006.281.08:07:02.45#ibcon#read 4, iclass 10, count 2 2006.281.08:07:02.45#ibcon#about to read 5, iclass 10, count 2 2006.281.08:07:02.45#ibcon#read 5, iclass 10, count 2 2006.281.08:07:02.45#ibcon#about to read 6, iclass 10, count 2 2006.281.08:07:02.45#ibcon#read 6, iclass 10, count 2 2006.281.08:07:02.45#ibcon#end of sib2, iclass 10, count 2 2006.281.08:07:02.45#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:07:02.45#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:07:02.45#ibcon#[27=AT02-05\r\n] 2006.281.08:07:02.45#ibcon#*before write, iclass 10, count 2 2006.281.08:07:02.45#ibcon#enter sib2, iclass 10, count 2 2006.281.08:07:02.45#ibcon#flushed, iclass 10, count 2 2006.281.08:07:02.45#ibcon#about to write, iclass 10, count 2 2006.281.08:07:02.45#ibcon#wrote, iclass 10, count 2 2006.281.08:07:02.45#ibcon#about to read 3, iclass 10, count 2 2006.281.08:07:02.48#ibcon#read 3, iclass 10, count 2 2006.281.08:07:02.48#ibcon#about to read 4, iclass 10, count 2 2006.281.08:07:02.48#ibcon#read 4, iclass 10, count 2 2006.281.08:07:02.48#ibcon#about to read 5, iclass 10, count 2 2006.281.08:07:02.48#ibcon#read 5, iclass 10, count 2 2006.281.08:07:02.48#ibcon#about to read 6, iclass 10, count 2 2006.281.08:07:02.48#ibcon#read 6, iclass 10, count 2 2006.281.08:07:02.48#ibcon#end of sib2, iclass 10, count 2 2006.281.08:07:02.48#ibcon#*after write, iclass 10, count 2 2006.281.08:07:02.48#ibcon#*before return 0, iclass 10, count 2 2006.281.08:07:02.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:07:02.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:07:02.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:07:02.48#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:02.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:07:02.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:07:02.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:07:02.60#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:07:02.60#ibcon#first serial, iclass 10, count 0 2006.281.08:07:02.60#ibcon#enter sib2, iclass 10, count 0 2006.281.08:07:02.60#ibcon#flushed, iclass 10, count 0 2006.281.08:07:02.60#ibcon#about to write, iclass 10, count 0 2006.281.08:07:02.60#ibcon#wrote, iclass 10, count 0 2006.281.08:07:02.60#ibcon#about to read 3, iclass 10, count 0 2006.281.08:07:02.62#ibcon#read 3, iclass 10, count 0 2006.281.08:07:02.62#ibcon#about to read 4, iclass 10, count 0 2006.281.08:07:02.62#ibcon#read 4, iclass 10, count 0 2006.281.08:07:02.62#ibcon#about to read 5, iclass 10, count 0 2006.281.08:07:02.62#ibcon#read 5, iclass 10, count 0 2006.281.08:07:02.62#ibcon#about to read 6, iclass 10, count 0 2006.281.08:07:02.62#ibcon#read 6, iclass 10, count 0 2006.281.08:07:02.62#ibcon#end of sib2, iclass 10, count 0 2006.281.08:07:02.62#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:07:02.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:07:02.62#ibcon#[27=USB\r\n] 2006.281.08:07:02.62#ibcon#*before write, iclass 10, count 0 2006.281.08:07:02.62#ibcon#enter sib2, iclass 10, count 0 2006.281.08:07:02.62#ibcon#flushed, iclass 10, count 0 2006.281.08:07:02.62#ibcon#about to write, iclass 10, count 0 2006.281.08:07:02.62#ibcon#wrote, iclass 10, count 0 2006.281.08:07:02.62#ibcon#about to read 3, iclass 10, count 0 2006.281.08:07:02.65#ibcon#read 3, iclass 10, count 0 2006.281.08:07:02.65#ibcon#about to read 4, iclass 10, count 0 2006.281.08:07:02.65#ibcon#read 4, iclass 10, count 0 2006.281.08:07:02.65#ibcon#about to read 5, iclass 10, count 0 2006.281.08:07:02.65#ibcon#read 5, iclass 10, count 0 2006.281.08:07:02.65#ibcon#about to read 6, iclass 10, count 0 2006.281.08:07:02.65#ibcon#read 6, iclass 10, count 0 2006.281.08:07:02.65#ibcon#end of sib2, iclass 10, count 0 2006.281.08:07:02.65#ibcon#*after write, iclass 10, count 0 2006.281.08:07:02.65#ibcon#*before return 0, iclass 10, count 0 2006.281.08:07:02.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:07:02.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:07:02.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:07:02.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:07:02.65$vc4f8/vblo=3,656.99 2006.281.08:07:02.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:07:02.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:07:02.65#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:02.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:07:02.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:07:02.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:07:02.65#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:07:02.65#ibcon#first serial, iclass 12, count 0 2006.281.08:07:02.65#ibcon#enter sib2, iclass 12, count 0 2006.281.08:07:02.65#ibcon#flushed, iclass 12, count 0 2006.281.08:07:02.65#ibcon#about to write, iclass 12, count 0 2006.281.08:07:02.65#ibcon#wrote, iclass 12, count 0 2006.281.08:07:02.65#ibcon#about to read 3, iclass 12, count 0 2006.281.08:07:02.67#ibcon#read 3, iclass 12, count 0 2006.281.08:07:02.67#ibcon#about to read 4, iclass 12, count 0 2006.281.08:07:02.67#ibcon#read 4, iclass 12, count 0 2006.281.08:07:02.67#ibcon#about to read 5, iclass 12, count 0 2006.281.08:07:02.67#ibcon#read 5, iclass 12, count 0 2006.281.08:07:02.67#ibcon#about to read 6, iclass 12, count 0 2006.281.08:07:02.67#ibcon#read 6, iclass 12, count 0 2006.281.08:07:02.67#ibcon#end of sib2, iclass 12, count 0 2006.281.08:07:02.67#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:07:02.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:07:02.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:07:02.67#ibcon#*before write, iclass 12, count 0 2006.281.08:07:02.67#ibcon#enter sib2, iclass 12, count 0 2006.281.08:07:02.67#ibcon#flushed, iclass 12, count 0 2006.281.08:07:02.67#ibcon#about to write, iclass 12, count 0 2006.281.08:07:02.67#ibcon#wrote, iclass 12, count 0 2006.281.08:07:02.67#ibcon#about to read 3, iclass 12, count 0 2006.281.08:07:02.71#ibcon#read 3, iclass 12, count 0 2006.281.08:07:02.71#ibcon#about to read 4, iclass 12, count 0 2006.281.08:07:02.71#ibcon#read 4, iclass 12, count 0 2006.281.08:07:02.71#ibcon#about to read 5, iclass 12, count 0 2006.281.08:07:02.71#ibcon#read 5, iclass 12, count 0 2006.281.08:07:02.71#ibcon#about to read 6, iclass 12, count 0 2006.281.08:07:02.71#ibcon#read 6, iclass 12, count 0 2006.281.08:07:02.71#ibcon#end of sib2, iclass 12, count 0 2006.281.08:07:02.71#ibcon#*after write, iclass 12, count 0 2006.281.08:07:02.71#ibcon#*before return 0, iclass 12, count 0 2006.281.08:07:02.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:07:02.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:07:02.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:07:02.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:07:02.71$vc4f8/vb=3,4 2006.281.08:07:02.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.08:07:02.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.08:07:02.71#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:02.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:07:02.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:07:02.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:07:02.77#ibcon#enter wrdev, iclass 14, count 2 2006.281.08:07:02.77#ibcon#first serial, iclass 14, count 2 2006.281.08:07:02.77#ibcon#enter sib2, iclass 14, count 2 2006.281.08:07:02.77#ibcon#flushed, iclass 14, count 2 2006.281.08:07:02.77#ibcon#about to write, iclass 14, count 2 2006.281.08:07:02.77#ibcon#wrote, iclass 14, count 2 2006.281.08:07:02.77#ibcon#about to read 3, iclass 14, count 2 2006.281.08:07:02.79#ibcon#read 3, iclass 14, count 2 2006.281.08:07:02.79#ibcon#about to read 4, iclass 14, count 2 2006.281.08:07:02.79#ibcon#read 4, iclass 14, count 2 2006.281.08:07:02.79#ibcon#about to read 5, iclass 14, count 2 2006.281.08:07:02.79#ibcon#read 5, iclass 14, count 2 2006.281.08:07:02.79#ibcon#about to read 6, iclass 14, count 2 2006.281.08:07:02.79#ibcon#read 6, iclass 14, count 2 2006.281.08:07:02.79#ibcon#end of sib2, iclass 14, count 2 2006.281.08:07:02.79#ibcon#*mode == 0, iclass 14, count 2 2006.281.08:07:02.79#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.08:07:02.79#ibcon#[27=AT03-04\r\n] 2006.281.08:07:02.79#ibcon#*before write, iclass 14, count 2 2006.281.08:07:02.79#ibcon#enter sib2, iclass 14, count 2 2006.281.08:07:02.79#ibcon#flushed, iclass 14, count 2 2006.281.08:07:02.79#ibcon#about to write, iclass 14, count 2 2006.281.08:07:02.79#ibcon#wrote, iclass 14, count 2 2006.281.08:07:02.79#ibcon#about to read 3, iclass 14, count 2 2006.281.08:07:02.82#ibcon#read 3, iclass 14, count 2 2006.281.08:07:02.82#ibcon#about to read 4, iclass 14, count 2 2006.281.08:07:02.82#ibcon#read 4, iclass 14, count 2 2006.281.08:07:02.82#ibcon#about to read 5, iclass 14, count 2 2006.281.08:07:02.82#ibcon#read 5, iclass 14, count 2 2006.281.08:07:02.82#ibcon#about to read 6, iclass 14, count 2 2006.281.08:07:02.82#ibcon#read 6, iclass 14, count 2 2006.281.08:07:02.82#ibcon#end of sib2, iclass 14, count 2 2006.281.08:07:02.82#ibcon#*after write, iclass 14, count 2 2006.281.08:07:02.82#ibcon#*before return 0, iclass 14, count 2 2006.281.08:07:02.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:07:02.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:07:02.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.08:07:02.82#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:02.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:07:02.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:07:02.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:07:02.94#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:07:02.94#ibcon#first serial, iclass 14, count 0 2006.281.08:07:02.94#ibcon#enter sib2, iclass 14, count 0 2006.281.08:07:02.94#ibcon#flushed, iclass 14, count 0 2006.281.08:07:02.94#ibcon#about to write, iclass 14, count 0 2006.281.08:07:02.94#ibcon#wrote, iclass 14, count 0 2006.281.08:07:02.94#ibcon#about to read 3, iclass 14, count 0 2006.281.08:07:02.96#ibcon#read 3, iclass 14, count 0 2006.281.08:07:02.96#ibcon#about to read 4, iclass 14, count 0 2006.281.08:07:02.96#ibcon#read 4, iclass 14, count 0 2006.281.08:07:02.96#ibcon#about to read 5, iclass 14, count 0 2006.281.08:07:02.96#ibcon#read 5, iclass 14, count 0 2006.281.08:07:02.96#ibcon#about to read 6, iclass 14, count 0 2006.281.08:07:02.96#ibcon#read 6, iclass 14, count 0 2006.281.08:07:02.96#ibcon#end of sib2, iclass 14, count 0 2006.281.08:07:02.96#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:07:02.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:07:02.96#ibcon#[27=USB\r\n] 2006.281.08:07:02.96#ibcon#*before write, iclass 14, count 0 2006.281.08:07:02.96#ibcon#enter sib2, iclass 14, count 0 2006.281.08:07:02.96#ibcon#flushed, iclass 14, count 0 2006.281.08:07:02.96#ibcon#about to write, iclass 14, count 0 2006.281.08:07:02.96#ibcon#wrote, iclass 14, count 0 2006.281.08:07:02.96#ibcon#about to read 3, iclass 14, count 0 2006.281.08:07:02.99#ibcon#read 3, iclass 14, count 0 2006.281.08:07:02.99#ibcon#about to read 4, iclass 14, count 0 2006.281.08:07:02.99#ibcon#read 4, iclass 14, count 0 2006.281.08:07:02.99#ibcon#about to read 5, iclass 14, count 0 2006.281.08:07:02.99#ibcon#read 5, iclass 14, count 0 2006.281.08:07:02.99#ibcon#about to read 6, iclass 14, count 0 2006.281.08:07:02.99#ibcon#read 6, iclass 14, count 0 2006.281.08:07:02.99#ibcon#end of sib2, iclass 14, count 0 2006.281.08:07:02.99#ibcon#*after write, iclass 14, count 0 2006.281.08:07:02.99#ibcon#*before return 0, iclass 14, count 0 2006.281.08:07:02.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:07:02.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:07:02.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:07:02.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:07:02.99$vc4f8/vblo=4,712.99 2006.281.08:07:02.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.08:07:02.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.08:07:02.99#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:02.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:02.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:02.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:02.99#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:07:02.99#ibcon#first serial, iclass 16, count 0 2006.281.08:07:02.99#ibcon#enter sib2, iclass 16, count 0 2006.281.08:07:02.99#ibcon#flushed, iclass 16, count 0 2006.281.08:07:02.99#ibcon#about to write, iclass 16, count 0 2006.281.08:07:02.99#ibcon#wrote, iclass 16, count 0 2006.281.08:07:02.99#ibcon#about to read 3, iclass 16, count 0 2006.281.08:07:03.01#ibcon#read 3, iclass 16, count 0 2006.281.08:07:03.01#ibcon#about to read 4, iclass 16, count 0 2006.281.08:07:03.01#ibcon#read 4, iclass 16, count 0 2006.281.08:07:03.01#ibcon#about to read 5, iclass 16, count 0 2006.281.08:07:03.01#ibcon#read 5, iclass 16, count 0 2006.281.08:07:03.01#ibcon#about to read 6, iclass 16, count 0 2006.281.08:07:03.01#ibcon#read 6, iclass 16, count 0 2006.281.08:07:03.01#ibcon#end of sib2, iclass 16, count 0 2006.281.08:07:03.01#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:07:03.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:07:03.01#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:07:03.01#ibcon#*before write, iclass 16, count 0 2006.281.08:07:03.01#ibcon#enter sib2, iclass 16, count 0 2006.281.08:07:03.01#ibcon#flushed, iclass 16, count 0 2006.281.08:07:03.01#ibcon#about to write, iclass 16, count 0 2006.281.08:07:03.01#ibcon#wrote, iclass 16, count 0 2006.281.08:07:03.01#ibcon#about to read 3, iclass 16, count 0 2006.281.08:07:03.05#ibcon#read 3, iclass 16, count 0 2006.281.08:07:03.05#ibcon#about to read 4, iclass 16, count 0 2006.281.08:07:03.05#ibcon#read 4, iclass 16, count 0 2006.281.08:07:03.05#ibcon#about to read 5, iclass 16, count 0 2006.281.08:07:03.05#ibcon#read 5, iclass 16, count 0 2006.281.08:07:03.05#ibcon#about to read 6, iclass 16, count 0 2006.281.08:07:03.05#ibcon#read 6, iclass 16, count 0 2006.281.08:07:03.05#ibcon#end of sib2, iclass 16, count 0 2006.281.08:07:03.05#ibcon#*after write, iclass 16, count 0 2006.281.08:07:03.05#ibcon#*before return 0, iclass 16, count 0 2006.281.08:07:03.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:03.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:07:03.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:07:03.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:07:03.05$vc4f8/vb=4,4 2006.281.08:07:03.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.08:07:03.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.08:07:03.05#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:03.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:03.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:03.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:03.11#ibcon#enter wrdev, iclass 18, count 2 2006.281.08:07:03.11#ibcon#first serial, iclass 18, count 2 2006.281.08:07:03.11#ibcon#enter sib2, iclass 18, count 2 2006.281.08:07:03.11#ibcon#flushed, iclass 18, count 2 2006.281.08:07:03.11#ibcon#about to write, iclass 18, count 2 2006.281.08:07:03.11#ibcon#wrote, iclass 18, count 2 2006.281.08:07:03.11#ibcon#about to read 3, iclass 18, count 2 2006.281.08:07:03.13#ibcon#read 3, iclass 18, count 2 2006.281.08:07:03.13#ibcon#about to read 4, iclass 18, count 2 2006.281.08:07:03.13#ibcon#read 4, iclass 18, count 2 2006.281.08:07:03.13#ibcon#about to read 5, iclass 18, count 2 2006.281.08:07:03.13#ibcon#read 5, iclass 18, count 2 2006.281.08:07:03.13#ibcon#about to read 6, iclass 18, count 2 2006.281.08:07:03.13#ibcon#read 6, iclass 18, count 2 2006.281.08:07:03.13#ibcon#end of sib2, iclass 18, count 2 2006.281.08:07:03.13#ibcon#*mode == 0, iclass 18, count 2 2006.281.08:07:03.13#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.08:07:03.13#ibcon#[27=AT04-04\r\n] 2006.281.08:07:03.13#ibcon#*before write, iclass 18, count 2 2006.281.08:07:03.13#ibcon#enter sib2, iclass 18, count 2 2006.281.08:07:03.13#ibcon#flushed, iclass 18, count 2 2006.281.08:07:03.13#ibcon#about to write, iclass 18, count 2 2006.281.08:07:03.13#ibcon#wrote, iclass 18, count 2 2006.281.08:07:03.13#ibcon#about to read 3, iclass 18, count 2 2006.281.08:07:03.16#ibcon#read 3, iclass 18, count 2 2006.281.08:07:03.16#ibcon#about to read 4, iclass 18, count 2 2006.281.08:07:03.16#ibcon#read 4, iclass 18, count 2 2006.281.08:07:03.16#ibcon#about to read 5, iclass 18, count 2 2006.281.08:07:03.16#ibcon#read 5, iclass 18, count 2 2006.281.08:07:03.16#ibcon#about to read 6, iclass 18, count 2 2006.281.08:07:03.16#ibcon#read 6, iclass 18, count 2 2006.281.08:07:03.16#ibcon#end of sib2, iclass 18, count 2 2006.281.08:07:03.16#ibcon#*after write, iclass 18, count 2 2006.281.08:07:03.16#ibcon#*before return 0, iclass 18, count 2 2006.281.08:07:03.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:03.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:07:03.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.08:07:03.16#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:03.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:03.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:03.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:03.28#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:07:03.28#ibcon#first serial, iclass 18, count 0 2006.281.08:07:03.28#ibcon#enter sib2, iclass 18, count 0 2006.281.08:07:03.28#ibcon#flushed, iclass 18, count 0 2006.281.08:07:03.28#ibcon#about to write, iclass 18, count 0 2006.281.08:07:03.28#ibcon#wrote, iclass 18, count 0 2006.281.08:07:03.28#ibcon#about to read 3, iclass 18, count 0 2006.281.08:07:03.30#ibcon#read 3, iclass 18, count 0 2006.281.08:07:03.30#ibcon#about to read 4, iclass 18, count 0 2006.281.08:07:03.30#ibcon#read 4, iclass 18, count 0 2006.281.08:07:03.30#ibcon#about to read 5, iclass 18, count 0 2006.281.08:07:03.30#ibcon#read 5, iclass 18, count 0 2006.281.08:07:03.30#ibcon#about to read 6, iclass 18, count 0 2006.281.08:07:03.30#ibcon#read 6, iclass 18, count 0 2006.281.08:07:03.30#ibcon#end of sib2, iclass 18, count 0 2006.281.08:07:03.30#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:07:03.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:07:03.30#ibcon#[27=USB\r\n] 2006.281.08:07:03.30#ibcon#*before write, iclass 18, count 0 2006.281.08:07:03.30#ibcon#enter sib2, iclass 18, count 0 2006.281.08:07:03.30#ibcon#flushed, iclass 18, count 0 2006.281.08:07:03.30#ibcon#about to write, iclass 18, count 0 2006.281.08:07:03.30#ibcon#wrote, iclass 18, count 0 2006.281.08:07:03.30#ibcon#about to read 3, iclass 18, count 0 2006.281.08:07:03.33#ibcon#read 3, iclass 18, count 0 2006.281.08:07:03.33#ibcon#about to read 4, iclass 18, count 0 2006.281.08:07:03.33#ibcon#read 4, iclass 18, count 0 2006.281.08:07:03.33#ibcon#about to read 5, iclass 18, count 0 2006.281.08:07:03.33#ibcon#read 5, iclass 18, count 0 2006.281.08:07:03.33#ibcon#about to read 6, iclass 18, count 0 2006.281.08:07:03.33#ibcon#read 6, iclass 18, count 0 2006.281.08:07:03.33#ibcon#end of sib2, iclass 18, count 0 2006.281.08:07:03.33#ibcon#*after write, iclass 18, count 0 2006.281.08:07:03.33#ibcon#*before return 0, iclass 18, count 0 2006.281.08:07:03.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:03.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:07:03.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:07:03.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:07:03.33$vc4f8/vblo=5,744.99 2006.281.08:07:03.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.08:07:03.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.08:07:03.33#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:03.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:03.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:03.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:03.33#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:07:03.33#ibcon#first serial, iclass 20, count 0 2006.281.08:07:03.33#ibcon#enter sib2, iclass 20, count 0 2006.281.08:07:03.33#ibcon#flushed, iclass 20, count 0 2006.281.08:07:03.33#ibcon#about to write, iclass 20, count 0 2006.281.08:07:03.33#ibcon#wrote, iclass 20, count 0 2006.281.08:07:03.33#ibcon#about to read 3, iclass 20, count 0 2006.281.08:07:03.35#ibcon#read 3, iclass 20, count 0 2006.281.08:07:03.35#ibcon#about to read 4, iclass 20, count 0 2006.281.08:07:03.35#ibcon#read 4, iclass 20, count 0 2006.281.08:07:03.35#ibcon#about to read 5, iclass 20, count 0 2006.281.08:07:03.35#ibcon#read 5, iclass 20, count 0 2006.281.08:07:03.35#ibcon#about to read 6, iclass 20, count 0 2006.281.08:07:03.35#ibcon#read 6, iclass 20, count 0 2006.281.08:07:03.35#ibcon#end of sib2, iclass 20, count 0 2006.281.08:07:03.35#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:07:03.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:07:03.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:07:03.37#ibcon#*before write, iclass 20, count 0 2006.281.08:07:03.37#ibcon#enter sib2, iclass 20, count 0 2006.281.08:07:03.37#ibcon#flushed, iclass 20, count 0 2006.281.08:07:03.37#ibcon#about to write, iclass 20, count 0 2006.281.08:07:03.37#ibcon#wrote, iclass 20, count 0 2006.281.08:07:03.37#ibcon#about to read 3, iclass 20, count 0 2006.281.08:07:03.41#ibcon#read 3, iclass 20, count 0 2006.281.08:07:03.41#ibcon#about to read 4, iclass 20, count 0 2006.281.08:07:03.41#ibcon#read 4, iclass 20, count 0 2006.281.08:07:03.41#ibcon#about to read 5, iclass 20, count 0 2006.281.08:07:03.41#ibcon#read 5, iclass 20, count 0 2006.281.08:07:03.41#ibcon#about to read 6, iclass 20, count 0 2006.281.08:07:03.41#ibcon#read 6, iclass 20, count 0 2006.281.08:07:03.41#ibcon#end of sib2, iclass 20, count 0 2006.281.08:07:03.41#ibcon#*after write, iclass 20, count 0 2006.281.08:07:03.41#ibcon#*before return 0, iclass 20, count 0 2006.281.08:07:03.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:03.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:07:03.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:07:03.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:07:03.41$vc4f8/vb=5,4 2006.281.08:07:03.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.08:07:03.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.08:07:03.41#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:03.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:03.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:03.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:03.45#ibcon#enter wrdev, iclass 22, count 2 2006.281.08:07:03.45#ibcon#first serial, iclass 22, count 2 2006.281.08:07:03.45#ibcon#enter sib2, iclass 22, count 2 2006.281.08:07:03.45#ibcon#flushed, iclass 22, count 2 2006.281.08:07:03.45#ibcon#about to write, iclass 22, count 2 2006.281.08:07:03.45#ibcon#wrote, iclass 22, count 2 2006.281.08:07:03.45#ibcon#about to read 3, iclass 22, count 2 2006.281.08:07:03.47#ibcon#read 3, iclass 22, count 2 2006.281.08:07:03.47#ibcon#about to read 4, iclass 22, count 2 2006.281.08:07:03.47#ibcon#read 4, iclass 22, count 2 2006.281.08:07:03.47#ibcon#about to read 5, iclass 22, count 2 2006.281.08:07:03.47#ibcon#read 5, iclass 22, count 2 2006.281.08:07:03.47#ibcon#about to read 6, iclass 22, count 2 2006.281.08:07:03.47#ibcon#read 6, iclass 22, count 2 2006.281.08:07:03.47#ibcon#end of sib2, iclass 22, count 2 2006.281.08:07:03.47#ibcon#*mode == 0, iclass 22, count 2 2006.281.08:07:03.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.08:07:03.47#ibcon#[27=AT05-04\r\n] 2006.281.08:07:03.47#ibcon#*before write, iclass 22, count 2 2006.281.08:07:03.47#ibcon#enter sib2, iclass 22, count 2 2006.281.08:07:03.47#ibcon#flushed, iclass 22, count 2 2006.281.08:07:03.47#ibcon#about to write, iclass 22, count 2 2006.281.08:07:03.47#ibcon#wrote, iclass 22, count 2 2006.281.08:07:03.47#ibcon#about to read 3, iclass 22, count 2 2006.281.08:07:03.50#ibcon#read 3, iclass 22, count 2 2006.281.08:07:03.50#ibcon#about to read 4, iclass 22, count 2 2006.281.08:07:03.50#ibcon#read 4, iclass 22, count 2 2006.281.08:07:03.50#ibcon#about to read 5, iclass 22, count 2 2006.281.08:07:03.50#ibcon#read 5, iclass 22, count 2 2006.281.08:07:03.50#ibcon#about to read 6, iclass 22, count 2 2006.281.08:07:03.50#ibcon#read 6, iclass 22, count 2 2006.281.08:07:03.50#ibcon#end of sib2, iclass 22, count 2 2006.281.08:07:03.50#ibcon#*after write, iclass 22, count 2 2006.281.08:07:03.50#ibcon#*before return 0, iclass 22, count 2 2006.281.08:07:03.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:03.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:07:03.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.08:07:03.50#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:03.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:03.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:03.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:03.62#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:07:03.62#ibcon#first serial, iclass 22, count 0 2006.281.08:07:03.62#ibcon#enter sib2, iclass 22, count 0 2006.281.08:07:03.62#ibcon#flushed, iclass 22, count 0 2006.281.08:07:03.62#ibcon#about to write, iclass 22, count 0 2006.281.08:07:03.62#ibcon#wrote, iclass 22, count 0 2006.281.08:07:03.62#ibcon#about to read 3, iclass 22, count 0 2006.281.08:07:03.64#ibcon#read 3, iclass 22, count 0 2006.281.08:07:03.64#ibcon#about to read 4, iclass 22, count 0 2006.281.08:07:03.64#ibcon#read 4, iclass 22, count 0 2006.281.08:07:03.64#ibcon#about to read 5, iclass 22, count 0 2006.281.08:07:03.64#ibcon#read 5, iclass 22, count 0 2006.281.08:07:03.64#ibcon#about to read 6, iclass 22, count 0 2006.281.08:07:03.64#ibcon#read 6, iclass 22, count 0 2006.281.08:07:03.64#ibcon#end of sib2, iclass 22, count 0 2006.281.08:07:03.64#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:07:03.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:07:03.64#ibcon#[27=USB\r\n] 2006.281.08:07:03.64#ibcon#*before write, iclass 22, count 0 2006.281.08:07:03.64#ibcon#enter sib2, iclass 22, count 0 2006.281.08:07:03.64#ibcon#flushed, iclass 22, count 0 2006.281.08:07:03.64#ibcon#about to write, iclass 22, count 0 2006.281.08:07:03.64#ibcon#wrote, iclass 22, count 0 2006.281.08:07:03.64#ibcon#about to read 3, iclass 22, count 0 2006.281.08:07:03.67#ibcon#read 3, iclass 22, count 0 2006.281.08:07:03.67#ibcon#about to read 4, iclass 22, count 0 2006.281.08:07:03.67#ibcon#read 4, iclass 22, count 0 2006.281.08:07:03.67#ibcon#about to read 5, iclass 22, count 0 2006.281.08:07:03.67#ibcon#read 5, iclass 22, count 0 2006.281.08:07:03.67#ibcon#about to read 6, iclass 22, count 0 2006.281.08:07:03.67#ibcon#read 6, iclass 22, count 0 2006.281.08:07:03.67#ibcon#end of sib2, iclass 22, count 0 2006.281.08:07:03.67#ibcon#*after write, iclass 22, count 0 2006.281.08:07:03.67#ibcon#*before return 0, iclass 22, count 0 2006.281.08:07:03.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:03.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:07:03.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:07:03.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:07:03.67$vc4f8/vblo=6,752.99 2006.281.08:07:03.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.08:07:03.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.08:07:03.67#ibcon#ireg 17 cls_cnt 0 2006.281.08:07:03.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:03.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:03.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:03.67#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:07:03.67#ibcon#first serial, iclass 24, count 0 2006.281.08:07:03.67#ibcon#enter sib2, iclass 24, count 0 2006.281.08:07:03.67#ibcon#flushed, iclass 24, count 0 2006.281.08:07:03.67#ibcon#about to write, iclass 24, count 0 2006.281.08:07:03.67#ibcon#wrote, iclass 24, count 0 2006.281.08:07:03.67#ibcon#about to read 3, iclass 24, count 0 2006.281.08:07:03.69#ibcon#read 3, iclass 24, count 0 2006.281.08:07:03.69#ibcon#about to read 4, iclass 24, count 0 2006.281.08:07:03.69#ibcon#read 4, iclass 24, count 0 2006.281.08:07:03.69#ibcon#about to read 5, iclass 24, count 0 2006.281.08:07:03.69#ibcon#read 5, iclass 24, count 0 2006.281.08:07:03.69#ibcon#about to read 6, iclass 24, count 0 2006.281.08:07:03.69#ibcon#read 6, iclass 24, count 0 2006.281.08:07:03.69#ibcon#end of sib2, iclass 24, count 0 2006.281.08:07:03.69#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:07:03.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:07:03.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:07:03.69#ibcon#*before write, iclass 24, count 0 2006.281.08:07:03.69#ibcon#enter sib2, iclass 24, count 0 2006.281.08:07:03.69#ibcon#flushed, iclass 24, count 0 2006.281.08:07:03.69#ibcon#about to write, iclass 24, count 0 2006.281.08:07:03.69#ibcon#wrote, iclass 24, count 0 2006.281.08:07:03.69#ibcon#about to read 3, iclass 24, count 0 2006.281.08:07:03.73#ibcon#read 3, iclass 24, count 0 2006.281.08:07:03.73#ibcon#about to read 4, iclass 24, count 0 2006.281.08:07:03.73#ibcon#read 4, iclass 24, count 0 2006.281.08:07:03.73#ibcon#about to read 5, iclass 24, count 0 2006.281.08:07:03.73#ibcon#read 5, iclass 24, count 0 2006.281.08:07:03.73#ibcon#about to read 6, iclass 24, count 0 2006.281.08:07:03.73#ibcon#read 6, iclass 24, count 0 2006.281.08:07:03.73#ibcon#end of sib2, iclass 24, count 0 2006.281.08:07:03.73#ibcon#*after write, iclass 24, count 0 2006.281.08:07:03.73#ibcon#*before return 0, iclass 24, count 0 2006.281.08:07:03.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:03.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:07:03.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:07:03.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:07:03.73$vc4f8/vb=6,4 2006.281.08:07:03.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.08:07:03.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.08:07:03.73#ibcon#ireg 11 cls_cnt 2 2006.281.08:07:03.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:03.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:03.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:03.79#ibcon#enter wrdev, iclass 26, count 2 2006.281.08:07:03.79#ibcon#first serial, iclass 26, count 2 2006.281.08:07:03.79#ibcon#enter sib2, iclass 26, count 2 2006.281.08:07:03.79#ibcon#flushed, iclass 26, count 2 2006.281.08:07:03.79#ibcon#about to write, iclass 26, count 2 2006.281.08:07:03.79#ibcon#wrote, iclass 26, count 2 2006.281.08:07:03.79#ibcon#about to read 3, iclass 26, count 2 2006.281.08:07:03.81#ibcon#read 3, iclass 26, count 2 2006.281.08:07:03.81#ibcon#about to read 4, iclass 26, count 2 2006.281.08:07:03.81#ibcon#read 4, iclass 26, count 2 2006.281.08:07:03.81#ibcon#about to read 5, iclass 26, count 2 2006.281.08:07:03.81#ibcon#read 5, iclass 26, count 2 2006.281.08:07:03.81#ibcon#about to read 6, iclass 26, count 2 2006.281.08:07:03.81#ibcon#read 6, iclass 26, count 2 2006.281.08:07:03.81#ibcon#end of sib2, iclass 26, count 2 2006.281.08:07:03.81#ibcon#*mode == 0, iclass 26, count 2 2006.281.08:07:03.81#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.08:07:03.81#ibcon#[27=AT06-04\r\n] 2006.281.08:07:03.81#ibcon#*before write, iclass 26, count 2 2006.281.08:07:03.81#ibcon#enter sib2, iclass 26, count 2 2006.281.08:07:03.81#ibcon#flushed, iclass 26, count 2 2006.281.08:07:03.81#ibcon#about to write, iclass 26, count 2 2006.281.08:07:03.81#ibcon#wrote, iclass 26, count 2 2006.281.08:07:03.81#ibcon#about to read 3, iclass 26, count 2 2006.281.08:07:03.84#ibcon#read 3, iclass 26, count 2 2006.281.08:07:03.84#ibcon#about to read 4, iclass 26, count 2 2006.281.08:07:03.84#ibcon#read 4, iclass 26, count 2 2006.281.08:07:03.84#ibcon#about to read 5, iclass 26, count 2 2006.281.08:07:03.84#ibcon#read 5, iclass 26, count 2 2006.281.08:07:03.84#ibcon#about to read 6, iclass 26, count 2 2006.281.08:07:03.84#ibcon#read 6, iclass 26, count 2 2006.281.08:07:03.84#ibcon#end of sib2, iclass 26, count 2 2006.281.08:07:03.84#ibcon#*after write, iclass 26, count 2 2006.281.08:07:03.84#ibcon#*before return 0, iclass 26, count 2 2006.281.08:07:03.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:03.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:07:03.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.08:07:03.84#ibcon#ireg 7 cls_cnt 0 2006.281.08:07:03.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:03.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:03.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:03.96#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:07:03.96#ibcon#first serial, iclass 26, count 0 2006.281.08:07:03.96#ibcon#enter sib2, iclass 26, count 0 2006.281.08:07:03.96#ibcon#flushed, iclass 26, count 0 2006.281.08:07:03.96#ibcon#about to write, iclass 26, count 0 2006.281.08:07:03.96#ibcon#wrote, iclass 26, count 0 2006.281.08:07:03.96#ibcon#about to read 3, iclass 26, count 0 2006.281.08:07:03.98#ibcon#read 3, iclass 26, count 0 2006.281.08:07:03.98#ibcon#about to read 4, iclass 26, count 0 2006.281.08:07:03.98#ibcon#read 4, iclass 26, count 0 2006.281.08:07:03.98#ibcon#about to read 5, iclass 26, count 0 2006.281.08:07:03.98#ibcon#read 5, iclass 26, count 0 2006.281.08:07:03.98#ibcon#about to read 6, iclass 26, count 0 2006.281.08:07:03.98#ibcon#read 6, iclass 26, count 0 2006.281.08:07:03.98#ibcon#end of sib2, iclass 26, count 0 2006.281.08:07:03.98#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:07:03.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:07:03.98#ibcon#[27=USB\r\n] 2006.281.08:07:03.98#ibcon#*before write, iclass 26, count 0 2006.281.08:07:03.98#ibcon#enter sib2, iclass 26, count 0 2006.281.08:07:03.98#ibcon#flushed, iclass 26, count 0 2006.281.08:07:03.98#ibcon#about to write, iclass 26, count 0 2006.281.08:07:03.98#ibcon#wrote, iclass 26, count 0 2006.281.08:07:03.98#ibcon#about to read 3, iclass 26, count 0 2006.281.08:07:04.01#ibcon#read 3, iclass 26, count 0 2006.281.08:07:04.01#ibcon#about to read 4, iclass 26, count 0 2006.281.08:07:04.01#ibcon#read 4, iclass 26, count 0 2006.281.08:07:04.01#ibcon#about to read 5, iclass 26, count 0 2006.281.08:07:04.01#ibcon#read 5, iclass 26, count 0 2006.281.08:07:04.01#ibcon#about to read 6, iclass 26, count 0 2006.281.08:07:04.01#ibcon#read 6, iclass 26, count 0 2006.281.08:07:04.01#ibcon#end of sib2, iclass 26, count 0 2006.281.08:07:04.01#ibcon#*after write, iclass 26, count 0 2006.281.08:07:04.01#ibcon#*before return 0, iclass 26, count 0 2006.281.08:07:04.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:04.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:07:04.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:07:04.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:07:04.01$vc4f8/vabw=wide 2006.281.08:07:04.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:07:04.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:07:04.01#ibcon#ireg 8 cls_cnt 0 2006.281.08:07:04.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:04.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:04.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:04.01#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:07:04.01#ibcon#first serial, iclass 28, count 0 2006.281.08:07:04.01#ibcon#enter sib2, iclass 28, count 0 2006.281.08:07:04.01#ibcon#flushed, iclass 28, count 0 2006.281.08:07:04.01#ibcon#about to write, iclass 28, count 0 2006.281.08:07:04.01#ibcon#wrote, iclass 28, count 0 2006.281.08:07:04.01#ibcon#about to read 3, iclass 28, count 0 2006.281.08:07:04.03#ibcon#read 3, iclass 28, count 0 2006.281.08:07:04.03#ibcon#about to read 4, iclass 28, count 0 2006.281.08:07:04.03#ibcon#read 4, iclass 28, count 0 2006.281.08:07:04.03#ibcon#about to read 5, iclass 28, count 0 2006.281.08:07:04.03#ibcon#read 5, iclass 28, count 0 2006.281.08:07:04.03#ibcon#about to read 6, iclass 28, count 0 2006.281.08:07:04.03#ibcon#read 6, iclass 28, count 0 2006.281.08:07:04.03#ibcon#end of sib2, iclass 28, count 0 2006.281.08:07:04.03#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:07:04.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:07:04.03#ibcon#[25=BW32\r\n] 2006.281.08:07:04.03#ibcon#*before write, iclass 28, count 0 2006.281.08:07:04.03#ibcon#enter sib2, iclass 28, count 0 2006.281.08:07:04.03#ibcon#flushed, iclass 28, count 0 2006.281.08:07:04.03#ibcon#about to write, iclass 28, count 0 2006.281.08:07:04.03#ibcon#wrote, iclass 28, count 0 2006.281.08:07:04.03#ibcon#about to read 3, iclass 28, count 0 2006.281.08:07:04.06#ibcon#read 3, iclass 28, count 0 2006.281.08:07:04.06#ibcon#about to read 4, iclass 28, count 0 2006.281.08:07:04.06#ibcon#read 4, iclass 28, count 0 2006.281.08:07:04.06#ibcon#about to read 5, iclass 28, count 0 2006.281.08:07:04.06#ibcon#read 5, iclass 28, count 0 2006.281.08:07:04.06#ibcon#about to read 6, iclass 28, count 0 2006.281.08:07:04.06#ibcon#read 6, iclass 28, count 0 2006.281.08:07:04.06#ibcon#end of sib2, iclass 28, count 0 2006.281.08:07:04.06#ibcon#*after write, iclass 28, count 0 2006.281.08:07:04.06#ibcon#*before return 0, iclass 28, count 0 2006.281.08:07:04.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:04.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:07:04.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:07:04.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:07:04.06$vc4f8/vbbw=wide 2006.281.08:07:04.06#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.08:07:04.06#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.08:07:04.06#ibcon#ireg 8 cls_cnt 0 2006.281.08:07:04.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:07:04.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:07:04.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:07:04.13#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:07:04.13#ibcon#first serial, iclass 30, count 0 2006.281.08:07:04.13#ibcon#enter sib2, iclass 30, count 0 2006.281.08:07:04.13#ibcon#flushed, iclass 30, count 0 2006.281.08:07:04.13#ibcon#about to write, iclass 30, count 0 2006.281.08:07:04.13#ibcon#wrote, iclass 30, count 0 2006.281.08:07:04.13#ibcon#about to read 3, iclass 30, count 0 2006.281.08:07:04.15#ibcon#read 3, iclass 30, count 0 2006.281.08:07:04.15#ibcon#about to read 4, iclass 30, count 0 2006.281.08:07:04.15#ibcon#read 4, iclass 30, count 0 2006.281.08:07:04.15#ibcon#about to read 5, iclass 30, count 0 2006.281.08:07:04.15#ibcon#read 5, iclass 30, count 0 2006.281.08:07:04.15#ibcon#about to read 6, iclass 30, count 0 2006.281.08:07:04.15#ibcon#read 6, iclass 30, count 0 2006.281.08:07:04.15#ibcon#end of sib2, iclass 30, count 0 2006.281.08:07:04.15#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:07:04.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:07:04.15#ibcon#[27=BW32\r\n] 2006.281.08:07:04.15#ibcon#*before write, iclass 30, count 0 2006.281.08:07:04.15#ibcon#enter sib2, iclass 30, count 0 2006.281.08:07:04.15#ibcon#flushed, iclass 30, count 0 2006.281.08:07:04.15#ibcon#about to write, iclass 30, count 0 2006.281.08:07:04.15#ibcon#wrote, iclass 30, count 0 2006.281.08:07:04.15#ibcon#about to read 3, iclass 30, count 0 2006.281.08:07:04.18#ibcon#read 3, iclass 30, count 0 2006.281.08:07:04.18#ibcon#about to read 4, iclass 30, count 0 2006.281.08:07:04.18#ibcon#read 4, iclass 30, count 0 2006.281.08:07:04.18#ibcon#about to read 5, iclass 30, count 0 2006.281.08:07:04.18#ibcon#read 5, iclass 30, count 0 2006.281.08:07:04.18#ibcon#about to read 6, iclass 30, count 0 2006.281.08:07:04.18#ibcon#read 6, iclass 30, count 0 2006.281.08:07:04.18#ibcon#end of sib2, iclass 30, count 0 2006.281.08:07:04.18#ibcon#*after write, iclass 30, count 0 2006.281.08:07:04.18#ibcon#*before return 0, iclass 30, count 0 2006.281.08:07:04.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:07:04.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:07:04.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:07:04.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:07:04.18$4f8m12a/ifd4f 2006.281.08:07:04.18$ifd4f/lo= 2006.281.08:07:04.18$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:07:04.18$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:07:04.18$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:07:04.18$ifd4f/patch= 2006.281.08:07:04.18$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:07:04.18$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:07:04.18$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:07:04.18$4f8m12a/"form=m,16.000,1:2 2006.281.08:07:04.18$4f8m12a/"tpicd 2006.281.08:07:04.18$4f8m12a/echo=off 2006.281.08:07:04.18$4f8m12a/xlog=off 2006.281.08:07:04.18:!2006.281.08:07:30 2006.281.08:07:13.13#trakl#Source acquired 2006.281.08:07:15.13#flagr#flagr/antenna,acquired 2006.281.08:07:27.13#trakl#Off source 2006.281.08:07:27.13?ERROR st -7 Antenna off-source! 2006.281.08:07:27.13#trakl#az 350.498 el 32.114 azerr*cos(el) -0.0162 elerr 0.0074 2006.281.08:07:27.13#flagr#flagr/antenna,off-source 2006.281.08:07:30.00:preob 2006.281.08:07:31.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:07:31.13?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:07:31.13/onsource/SLEWING 2006.281.08:07:31.13:!2006.281.08:07:40 2006.281.08:07:37.13#trakl#Source re-acquired 2006.281.08:07:38.13#flagr#flagr/antenna,re-acquired 2006.281.08:07:40.00:data_valid=on 2006.281.08:07:40.00:midob 2006.281.08:07:40.13/onsource/TRACKING 2006.281.08:07:40.13/wx/20.29,1001.5,52 2006.281.08:07:40.24/cable/+6.4884E-03 2006.281.08:07:41.33/va/01,07,usb,yes,33,34 2006.281.08:07:41.33/va/02,06,usb,yes,30,32 2006.281.08:07:41.33/va/03,06,usb,yes,29,29 2006.281.08:07:41.33/va/04,06,usb,yes,32,34 2006.281.08:07:41.33/va/05,07,usb,yes,30,32 2006.281.08:07:41.33/va/06,06,usb,yes,29,29 2006.281.08:07:41.33/va/07,06,usb,yes,29,29 2006.281.08:07:41.33/va/08,06,usb,yes,31,31 2006.281.08:07:41.56/valo/01,532.99,yes,locked 2006.281.08:07:41.56/valo/02,572.99,yes,locked 2006.281.08:07:41.56/valo/03,672.99,yes,locked 2006.281.08:07:41.56/valo/04,832.99,yes,locked 2006.281.08:07:41.56/valo/05,652.99,yes,locked 2006.281.08:07:41.56/valo/06,772.99,yes,locked 2006.281.08:07:41.56/valo/07,832.99,yes,locked 2006.281.08:07:41.56/valo/08,852.99,yes,locked 2006.281.08:07:42.65/vb/01,04,usb,yes,30,29 2006.281.08:07:42.65/vb/02,05,usb,yes,28,29 2006.281.08:07:42.65/vb/03,04,usb,yes,28,32 2006.281.08:07:42.65/vb/04,04,usb,yes,29,29 2006.281.08:07:42.65/vb/05,04,usb,yes,27,31 2006.281.08:07:42.65/vb/06,04,usb,yes,28,31 2006.281.08:07:42.65/vb/07,04,usb,yes,31,30 2006.281.08:07:42.65/vb/08,04,usb,yes,28,31 2006.281.08:07:42.89/vblo/01,632.99,yes,locked 2006.281.08:07:42.89/vblo/02,640.99,yes,locked 2006.281.08:07:42.89/vblo/03,656.99,yes,locked 2006.281.08:07:42.89/vblo/04,712.99,yes,locked 2006.281.08:07:42.89/vblo/05,744.99,yes,locked 2006.281.08:07:42.89/vblo/06,752.99,yes,locked 2006.281.08:07:42.89/vblo/07,734.99,yes,locked 2006.281.08:07:42.89/vblo/08,744.99,yes,locked 2006.281.08:07:43.04/vabw/8 2006.281.08:07:43.19/vbbw/8 2006.281.08:07:43.33/xfe/off,on,12.2 2006.281.08:07:43.70/ifatt/23,28,28,28 2006.281.08:07:44.08/fmout-gps/S +3.18E-07 2006.281.08:07:44.09:!2006.281.08:08:40 2006.281.08:07:46.13#trakl#Off source 2006.281.08:07:46.13?ERROR st -7 Antenna off-source! 2006.281.08:07:46.13#trakl#az 350.505 el 32.103 azerr*cos(el) -0.0010 elerr -0.0180 2006.281.08:07:48.13#flagr#flagr/antenna,off-source 2006.281.08:07:56.13#trakl#Source re-acquired 2006.281.08:07:57.13#flagr#flagr/antenna,re-acquired 2006.281.08:07:58.13#trakl#Off source 2006.281.08:07:58.13?ERROR st -7 Antenna off-source! 2006.281.08:07:58.13#trakl#az 350.510 el 32.096 azerr*cos(el) 0.0028 elerr -0.0164 2006.281.08:08:00.13#flagr#flagr/antenna,off-source 2006.281.08:08:13.13#trakl#Off source 2006.281.08:08:13.13?ERROR st -7 Antenna off-source! 2006.281.08:08:13.13#trakl#az 350.515 el 32.088 azerr*cos(el) -0.0027 elerr -0.0050 2006.281.08:08:15.13#trakl#Source re-acquired 2006.281.08:08:15.13#flagr#flagr/antenna,re-acquired 2006.281.08:08:40.00:data_valid=off 2006.281.08:08:40.00:postob 2006.281.08:08:40.15/cable/+6.4873E-03 2006.281.08:08:40.15/wx/20.26,1001.6,52 2006.281.08:08:41.08/fmout-gps/S +3.19E-07 2006.281.08:08:41.08:scan_name=281-0809,k06281,60 2006.281.08:08:41.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.281.08:08:41.15#flagr#flagr/antenna,new-source 2006.281.08:08:42.14:checkk5 2006.281.08:08:42.59/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:08:43.02/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:08:43.43/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:08:43.83/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:08:44.22/chk_obsdata//k5ts1/T2810807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:08:44.64/chk_obsdata//k5ts2/T2810807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:08:45.02/chk_obsdata//k5ts3/T2810807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:08:45.46/chk_obsdata//k5ts4/T2810807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:08:46.21/k5log//k5ts1_log_newline 2006.281.08:08:47.13/k5log//k5ts2_log_newline 2006.281.08:08:47.88/k5log//k5ts3_log_newline 2006.281.08:08:48.77/k5log//k5ts4_log_newline 2006.281.08:08:48.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:08:48.79:4f8m12a=2 2006.281.08:08:48.79$4f8m12a/echo=on 2006.281.08:08:48.79$4f8m12a/pcalon 2006.281.08:08:48.80$pcalon/"no phase cal control is implemented here 2006.281.08:08:48.80$4f8m12a/"tpicd=stop 2006.281.08:08:48.80$4f8m12a/vc4f8 2006.281.08:08:48.80$vc4f8/valo=1,532.99 2006.281.08:08:48.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:08:48.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:08:48.81#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:48.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:48.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:48.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:48.81#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:08:48.81#ibcon#first serial, iclass 13, count 0 2006.281.08:08:48.81#ibcon#enter sib2, iclass 13, count 0 2006.281.08:08:48.81#ibcon#flushed, iclass 13, count 0 2006.281.08:08:48.81#ibcon#about to write, iclass 13, count 0 2006.281.08:08:48.81#ibcon#wrote, iclass 13, count 0 2006.281.08:08:48.81#ibcon#about to read 3, iclass 13, count 0 2006.281.08:08:48.83#ibcon#read 3, iclass 13, count 0 2006.281.08:08:48.83#ibcon#about to read 4, iclass 13, count 0 2006.281.08:08:48.83#ibcon#read 4, iclass 13, count 0 2006.281.08:08:48.83#ibcon#about to read 5, iclass 13, count 0 2006.281.08:08:48.83#ibcon#read 5, iclass 13, count 0 2006.281.08:08:48.83#ibcon#about to read 6, iclass 13, count 0 2006.281.08:08:48.83#ibcon#read 6, iclass 13, count 0 2006.281.08:08:48.83#ibcon#end of sib2, iclass 13, count 0 2006.281.08:08:48.83#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:08:48.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:08:48.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:08:48.83#ibcon#*before write, iclass 13, count 0 2006.281.08:08:48.83#ibcon#enter sib2, iclass 13, count 0 2006.281.08:08:48.83#ibcon#flushed, iclass 13, count 0 2006.281.08:08:48.83#ibcon#about to write, iclass 13, count 0 2006.281.08:08:48.83#ibcon#wrote, iclass 13, count 0 2006.281.08:08:48.83#ibcon#about to read 3, iclass 13, count 0 2006.281.08:08:48.88#ibcon#read 3, iclass 13, count 0 2006.281.08:08:48.88#ibcon#about to read 4, iclass 13, count 0 2006.281.08:08:48.88#ibcon#read 4, iclass 13, count 0 2006.281.08:08:48.88#ibcon#about to read 5, iclass 13, count 0 2006.281.08:08:48.88#ibcon#read 5, iclass 13, count 0 2006.281.08:08:48.88#ibcon#about to read 6, iclass 13, count 0 2006.281.08:08:48.88#ibcon#read 6, iclass 13, count 0 2006.281.08:08:48.88#ibcon#end of sib2, iclass 13, count 0 2006.281.08:08:48.88#ibcon#*after write, iclass 13, count 0 2006.281.08:08:48.88#ibcon#*before return 0, iclass 13, count 0 2006.281.08:08:48.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:48.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:48.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:08:48.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:08:48.88$vc4f8/va=1,7 2006.281.08:08:48.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:08:48.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:08:48.88#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:48.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:48.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:48.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:48.88#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:08:48.88#ibcon#first serial, iclass 15, count 2 2006.281.08:08:48.88#ibcon#enter sib2, iclass 15, count 2 2006.281.08:08:48.88#ibcon#flushed, iclass 15, count 2 2006.281.08:08:48.88#ibcon#about to write, iclass 15, count 2 2006.281.08:08:48.88#ibcon#wrote, iclass 15, count 2 2006.281.08:08:48.88#ibcon#about to read 3, iclass 15, count 2 2006.281.08:08:48.90#ibcon#read 3, iclass 15, count 2 2006.281.08:08:48.90#ibcon#about to read 4, iclass 15, count 2 2006.281.08:08:48.90#ibcon#read 4, iclass 15, count 2 2006.281.08:08:48.90#ibcon#about to read 5, iclass 15, count 2 2006.281.08:08:48.90#ibcon#read 5, iclass 15, count 2 2006.281.08:08:48.90#ibcon#about to read 6, iclass 15, count 2 2006.281.08:08:48.90#ibcon#read 6, iclass 15, count 2 2006.281.08:08:48.90#ibcon#end of sib2, iclass 15, count 2 2006.281.08:08:48.90#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:08:48.90#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:08:48.90#ibcon#[25=AT01-07\r\n] 2006.281.08:08:48.90#ibcon#*before write, iclass 15, count 2 2006.281.08:08:48.90#ibcon#enter sib2, iclass 15, count 2 2006.281.08:08:48.90#ibcon#flushed, iclass 15, count 2 2006.281.08:08:48.90#ibcon#about to write, iclass 15, count 2 2006.281.08:08:48.90#ibcon#wrote, iclass 15, count 2 2006.281.08:08:48.90#ibcon#about to read 3, iclass 15, count 2 2006.281.08:08:48.93#ibcon#read 3, iclass 15, count 2 2006.281.08:08:48.93#ibcon#about to read 4, iclass 15, count 2 2006.281.08:08:48.93#ibcon#read 4, iclass 15, count 2 2006.281.08:08:48.93#ibcon#about to read 5, iclass 15, count 2 2006.281.08:08:48.93#ibcon#read 5, iclass 15, count 2 2006.281.08:08:48.93#ibcon#about to read 6, iclass 15, count 2 2006.281.08:08:48.93#ibcon#read 6, iclass 15, count 2 2006.281.08:08:48.93#ibcon#end of sib2, iclass 15, count 2 2006.281.08:08:48.93#ibcon#*after write, iclass 15, count 2 2006.281.08:08:48.93#ibcon#*before return 0, iclass 15, count 2 2006.281.08:08:48.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:48.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:48.93#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:08:48.93#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:48.93#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:49.05#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:49.05#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:49.05#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:08:49.05#ibcon#first serial, iclass 15, count 0 2006.281.08:08:49.05#ibcon#enter sib2, iclass 15, count 0 2006.281.08:08:49.05#ibcon#flushed, iclass 15, count 0 2006.281.08:08:49.05#ibcon#about to write, iclass 15, count 0 2006.281.08:08:49.05#ibcon#wrote, iclass 15, count 0 2006.281.08:08:49.05#ibcon#about to read 3, iclass 15, count 0 2006.281.08:08:49.07#ibcon#read 3, iclass 15, count 0 2006.281.08:08:49.07#ibcon#about to read 4, iclass 15, count 0 2006.281.08:08:49.07#ibcon#read 4, iclass 15, count 0 2006.281.08:08:49.07#ibcon#about to read 5, iclass 15, count 0 2006.281.08:08:49.07#ibcon#read 5, iclass 15, count 0 2006.281.08:08:49.07#ibcon#about to read 6, iclass 15, count 0 2006.281.08:08:49.07#ibcon#read 6, iclass 15, count 0 2006.281.08:08:49.07#ibcon#end of sib2, iclass 15, count 0 2006.281.08:08:49.07#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:08:49.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:08:49.07#ibcon#[25=USB\r\n] 2006.281.08:08:49.07#ibcon#*before write, iclass 15, count 0 2006.281.08:08:49.07#ibcon#enter sib2, iclass 15, count 0 2006.281.08:08:49.07#ibcon#flushed, iclass 15, count 0 2006.281.08:08:49.07#ibcon#about to write, iclass 15, count 0 2006.281.08:08:49.07#ibcon#wrote, iclass 15, count 0 2006.281.08:08:49.07#ibcon#about to read 3, iclass 15, count 0 2006.281.08:08:49.10#ibcon#read 3, iclass 15, count 0 2006.281.08:08:49.10#ibcon#about to read 4, iclass 15, count 0 2006.281.08:08:49.10#ibcon#read 4, iclass 15, count 0 2006.281.08:08:49.10#ibcon#about to read 5, iclass 15, count 0 2006.281.08:08:49.10#ibcon#read 5, iclass 15, count 0 2006.281.08:08:49.10#ibcon#about to read 6, iclass 15, count 0 2006.281.08:08:49.10#ibcon#read 6, iclass 15, count 0 2006.281.08:08:49.10#ibcon#end of sib2, iclass 15, count 0 2006.281.08:08:49.10#ibcon#*after write, iclass 15, count 0 2006.281.08:08:49.10#ibcon#*before return 0, iclass 15, count 0 2006.281.08:08:49.10#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:49.10#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:49.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:08:49.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:08:49.10$vc4f8/valo=2,572.99 2006.281.08:08:49.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:08:49.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:08:49.10#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:49.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:49.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:49.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:49.10#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:08:49.10#ibcon#first serial, iclass 17, count 0 2006.281.08:08:49.10#ibcon#enter sib2, iclass 17, count 0 2006.281.08:08:49.10#ibcon#flushed, iclass 17, count 0 2006.281.08:08:49.10#ibcon#about to write, iclass 17, count 0 2006.281.08:08:49.10#ibcon#wrote, iclass 17, count 0 2006.281.08:08:49.10#ibcon#about to read 3, iclass 17, count 0 2006.281.08:08:49.12#ibcon#read 3, iclass 17, count 0 2006.281.08:08:49.12#ibcon#about to read 4, iclass 17, count 0 2006.281.08:08:49.12#ibcon#read 4, iclass 17, count 0 2006.281.08:08:49.12#ibcon#about to read 5, iclass 17, count 0 2006.281.08:08:49.12#ibcon#read 5, iclass 17, count 0 2006.281.08:08:49.12#ibcon#about to read 6, iclass 17, count 0 2006.281.08:08:49.12#ibcon#read 6, iclass 17, count 0 2006.281.08:08:49.12#ibcon#end of sib2, iclass 17, count 0 2006.281.08:08:49.12#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:08:49.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:08:49.12#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:08:49.12#ibcon#*before write, iclass 17, count 0 2006.281.08:08:49.12#ibcon#enter sib2, iclass 17, count 0 2006.281.08:08:49.12#ibcon#flushed, iclass 17, count 0 2006.281.08:08:49.12#ibcon#about to write, iclass 17, count 0 2006.281.08:08:49.12#ibcon#wrote, iclass 17, count 0 2006.281.08:08:49.12#ibcon#about to read 3, iclass 17, count 0 2006.281.08:08:49.16#ibcon#read 3, iclass 17, count 0 2006.281.08:08:49.16#ibcon#about to read 4, iclass 17, count 0 2006.281.08:08:49.16#ibcon#read 4, iclass 17, count 0 2006.281.08:08:49.16#ibcon#about to read 5, iclass 17, count 0 2006.281.08:08:49.16#ibcon#read 5, iclass 17, count 0 2006.281.08:08:49.16#ibcon#about to read 6, iclass 17, count 0 2006.281.08:08:49.16#ibcon#read 6, iclass 17, count 0 2006.281.08:08:49.16#ibcon#end of sib2, iclass 17, count 0 2006.281.08:08:49.16#ibcon#*after write, iclass 17, count 0 2006.281.08:08:49.16#ibcon#*before return 0, iclass 17, count 0 2006.281.08:08:49.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:49.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:49.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:08:49.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:08:49.16$vc4f8/va=2,6 2006.281.08:08:49.16#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:08:49.16#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:08:49.16#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:49.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:49.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:49.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:49.22#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:08:49.22#ibcon#first serial, iclass 19, count 2 2006.281.08:08:49.22#ibcon#enter sib2, iclass 19, count 2 2006.281.08:08:49.22#ibcon#flushed, iclass 19, count 2 2006.281.08:08:49.22#ibcon#about to write, iclass 19, count 2 2006.281.08:08:49.22#ibcon#wrote, iclass 19, count 2 2006.281.08:08:49.22#ibcon#about to read 3, iclass 19, count 2 2006.281.08:08:49.24#ibcon#read 3, iclass 19, count 2 2006.281.08:08:49.24#ibcon#about to read 4, iclass 19, count 2 2006.281.08:08:49.24#ibcon#read 4, iclass 19, count 2 2006.281.08:08:49.24#ibcon#about to read 5, iclass 19, count 2 2006.281.08:08:49.24#ibcon#read 5, iclass 19, count 2 2006.281.08:08:49.24#ibcon#about to read 6, iclass 19, count 2 2006.281.08:08:49.24#ibcon#read 6, iclass 19, count 2 2006.281.08:08:49.24#ibcon#end of sib2, iclass 19, count 2 2006.281.08:08:49.24#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:08:49.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:08:49.24#ibcon#[25=AT02-06\r\n] 2006.281.08:08:49.24#ibcon#*before write, iclass 19, count 2 2006.281.08:08:49.24#ibcon#enter sib2, iclass 19, count 2 2006.281.08:08:49.24#ibcon#flushed, iclass 19, count 2 2006.281.08:08:49.24#ibcon#about to write, iclass 19, count 2 2006.281.08:08:49.24#ibcon#wrote, iclass 19, count 2 2006.281.08:08:49.24#ibcon#about to read 3, iclass 19, count 2 2006.281.08:08:49.28#ibcon#read 3, iclass 19, count 2 2006.281.08:08:49.28#ibcon#about to read 4, iclass 19, count 2 2006.281.08:08:49.28#ibcon#read 4, iclass 19, count 2 2006.281.08:08:49.28#ibcon#about to read 5, iclass 19, count 2 2006.281.08:08:49.28#ibcon#read 5, iclass 19, count 2 2006.281.08:08:49.28#ibcon#about to read 6, iclass 19, count 2 2006.281.08:08:49.28#ibcon#read 6, iclass 19, count 2 2006.281.08:08:49.28#ibcon#end of sib2, iclass 19, count 2 2006.281.08:08:49.28#ibcon#*after write, iclass 19, count 2 2006.281.08:08:49.28#ibcon#*before return 0, iclass 19, count 2 2006.281.08:08:49.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:49.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:49.28#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:08:49.28#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:49.28#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:49.40#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:49.40#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:49.40#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:08:49.40#ibcon#first serial, iclass 19, count 0 2006.281.08:08:49.40#ibcon#enter sib2, iclass 19, count 0 2006.281.08:08:49.40#ibcon#flushed, iclass 19, count 0 2006.281.08:08:49.40#ibcon#about to write, iclass 19, count 0 2006.281.08:08:49.40#ibcon#wrote, iclass 19, count 0 2006.281.08:08:49.40#ibcon#about to read 3, iclass 19, count 0 2006.281.08:08:49.42#ibcon#read 3, iclass 19, count 0 2006.281.08:08:49.42#ibcon#about to read 4, iclass 19, count 0 2006.281.08:08:49.42#ibcon#read 4, iclass 19, count 0 2006.281.08:08:49.42#ibcon#about to read 5, iclass 19, count 0 2006.281.08:08:49.42#ibcon#read 5, iclass 19, count 0 2006.281.08:08:49.42#ibcon#about to read 6, iclass 19, count 0 2006.281.08:08:49.42#ibcon#read 6, iclass 19, count 0 2006.281.08:08:49.42#ibcon#end of sib2, iclass 19, count 0 2006.281.08:08:49.42#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:08:49.42#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:08:49.42#ibcon#[25=USB\r\n] 2006.281.08:08:49.42#ibcon#*before write, iclass 19, count 0 2006.281.08:08:49.42#ibcon#enter sib2, iclass 19, count 0 2006.281.08:08:49.42#ibcon#flushed, iclass 19, count 0 2006.281.08:08:49.42#ibcon#about to write, iclass 19, count 0 2006.281.08:08:49.42#ibcon#wrote, iclass 19, count 0 2006.281.08:08:49.42#ibcon#about to read 3, iclass 19, count 0 2006.281.08:08:49.45#ibcon#read 3, iclass 19, count 0 2006.281.08:08:49.45#ibcon#about to read 4, iclass 19, count 0 2006.281.08:08:49.45#ibcon#read 4, iclass 19, count 0 2006.281.08:08:49.45#ibcon#about to read 5, iclass 19, count 0 2006.281.08:08:49.45#ibcon#read 5, iclass 19, count 0 2006.281.08:08:49.45#ibcon#about to read 6, iclass 19, count 0 2006.281.08:08:49.45#ibcon#read 6, iclass 19, count 0 2006.281.08:08:49.45#ibcon#end of sib2, iclass 19, count 0 2006.281.08:08:49.45#ibcon#*after write, iclass 19, count 0 2006.281.08:08:49.45#ibcon#*before return 0, iclass 19, count 0 2006.281.08:08:49.45#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:49.45#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:49.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:08:49.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:08:49.45$vc4f8/valo=3,672.99 2006.281.08:08:49.45#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:08:49.45#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:08:49.45#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:49.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:49.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:49.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:49.45#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:08:49.45#ibcon#first serial, iclass 21, count 0 2006.281.08:08:49.45#ibcon#enter sib2, iclass 21, count 0 2006.281.08:08:49.45#ibcon#flushed, iclass 21, count 0 2006.281.08:08:49.45#ibcon#about to write, iclass 21, count 0 2006.281.08:08:49.45#ibcon#wrote, iclass 21, count 0 2006.281.08:08:49.45#ibcon#about to read 3, iclass 21, count 0 2006.281.08:08:49.47#ibcon#read 3, iclass 21, count 0 2006.281.08:08:49.47#ibcon#about to read 4, iclass 21, count 0 2006.281.08:08:49.47#ibcon#read 4, iclass 21, count 0 2006.281.08:08:49.47#ibcon#about to read 5, iclass 21, count 0 2006.281.08:08:49.47#ibcon#read 5, iclass 21, count 0 2006.281.08:08:49.47#ibcon#about to read 6, iclass 21, count 0 2006.281.08:08:49.47#ibcon#read 6, iclass 21, count 0 2006.281.08:08:49.47#ibcon#end of sib2, iclass 21, count 0 2006.281.08:08:49.47#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:08:49.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:08:49.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:08:49.47#ibcon#*before write, iclass 21, count 0 2006.281.08:08:49.47#ibcon#enter sib2, iclass 21, count 0 2006.281.08:08:49.47#ibcon#flushed, iclass 21, count 0 2006.281.08:08:49.47#ibcon#about to write, iclass 21, count 0 2006.281.08:08:49.47#ibcon#wrote, iclass 21, count 0 2006.281.08:08:49.47#ibcon#about to read 3, iclass 21, count 0 2006.281.08:08:49.51#ibcon#read 3, iclass 21, count 0 2006.281.08:08:49.51#ibcon#about to read 4, iclass 21, count 0 2006.281.08:08:49.51#ibcon#read 4, iclass 21, count 0 2006.281.08:08:49.51#ibcon#about to read 5, iclass 21, count 0 2006.281.08:08:49.51#ibcon#read 5, iclass 21, count 0 2006.281.08:08:49.51#ibcon#about to read 6, iclass 21, count 0 2006.281.08:08:49.51#ibcon#read 6, iclass 21, count 0 2006.281.08:08:49.51#ibcon#end of sib2, iclass 21, count 0 2006.281.08:08:49.51#ibcon#*after write, iclass 21, count 0 2006.281.08:08:49.51#ibcon#*before return 0, iclass 21, count 0 2006.281.08:08:49.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:49.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:49.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:08:49.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:08:49.51$vc4f8/va=3,6 2006.281.08:08:49.51#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:08:49.51#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:08:49.51#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:49.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:49.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:49.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:49.57#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:08:49.57#ibcon#first serial, iclass 23, count 2 2006.281.08:08:49.57#ibcon#enter sib2, iclass 23, count 2 2006.281.08:08:49.57#ibcon#flushed, iclass 23, count 2 2006.281.08:08:49.57#ibcon#about to write, iclass 23, count 2 2006.281.08:08:49.57#ibcon#wrote, iclass 23, count 2 2006.281.08:08:49.57#ibcon#about to read 3, iclass 23, count 2 2006.281.08:08:49.59#ibcon#read 3, iclass 23, count 2 2006.281.08:08:49.59#ibcon#about to read 4, iclass 23, count 2 2006.281.08:08:49.59#ibcon#read 4, iclass 23, count 2 2006.281.08:08:49.59#ibcon#about to read 5, iclass 23, count 2 2006.281.08:08:49.59#ibcon#read 5, iclass 23, count 2 2006.281.08:08:49.59#ibcon#about to read 6, iclass 23, count 2 2006.281.08:08:49.59#ibcon#read 6, iclass 23, count 2 2006.281.08:08:49.59#ibcon#end of sib2, iclass 23, count 2 2006.281.08:08:49.59#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:08:49.59#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:08:49.59#ibcon#[25=AT03-06\r\n] 2006.281.08:08:49.59#ibcon#*before write, iclass 23, count 2 2006.281.08:08:49.59#ibcon#enter sib2, iclass 23, count 2 2006.281.08:08:49.59#ibcon#flushed, iclass 23, count 2 2006.281.08:08:49.59#ibcon#about to write, iclass 23, count 2 2006.281.08:08:49.59#ibcon#wrote, iclass 23, count 2 2006.281.08:08:49.59#ibcon#about to read 3, iclass 23, count 2 2006.281.08:08:49.62#ibcon#read 3, iclass 23, count 2 2006.281.08:08:49.62#ibcon#about to read 4, iclass 23, count 2 2006.281.08:08:49.62#ibcon#read 4, iclass 23, count 2 2006.281.08:08:49.62#ibcon#about to read 5, iclass 23, count 2 2006.281.08:08:49.62#ibcon#read 5, iclass 23, count 2 2006.281.08:08:49.62#ibcon#about to read 6, iclass 23, count 2 2006.281.08:08:49.62#ibcon#read 6, iclass 23, count 2 2006.281.08:08:49.62#ibcon#end of sib2, iclass 23, count 2 2006.281.08:08:49.62#ibcon#*after write, iclass 23, count 2 2006.281.08:08:49.62#ibcon#*before return 0, iclass 23, count 2 2006.281.08:08:49.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:49.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:49.62#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:08:49.62#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:49.62#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:49.74#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:49.74#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:49.74#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:08:49.74#ibcon#first serial, iclass 23, count 0 2006.281.08:08:49.74#ibcon#enter sib2, iclass 23, count 0 2006.281.08:08:49.74#ibcon#flushed, iclass 23, count 0 2006.281.08:08:49.74#ibcon#about to write, iclass 23, count 0 2006.281.08:08:49.74#ibcon#wrote, iclass 23, count 0 2006.281.08:08:49.74#ibcon#about to read 3, iclass 23, count 0 2006.281.08:08:49.76#ibcon#read 3, iclass 23, count 0 2006.281.08:08:49.76#ibcon#about to read 4, iclass 23, count 0 2006.281.08:08:49.76#ibcon#read 4, iclass 23, count 0 2006.281.08:08:49.76#ibcon#about to read 5, iclass 23, count 0 2006.281.08:08:49.76#ibcon#read 5, iclass 23, count 0 2006.281.08:08:49.76#ibcon#about to read 6, iclass 23, count 0 2006.281.08:08:49.76#ibcon#read 6, iclass 23, count 0 2006.281.08:08:49.76#ibcon#end of sib2, iclass 23, count 0 2006.281.08:08:49.76#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:08:49.76#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:08:49.76#ibcon#[25=USB\r\n] 2006.281.08:08:49.76#ibcon#*before write, iclass 23, count 0 2006.281.08:08:49.76#ibcon#enter sib2, iclass 23, count 0 2006.281.08:08:49.76#ibcon#flushed, iclass 23, count 0 2006.281.08:08:49.76#ibcon#about to write, iclass 23, count 0 2006.281.08:08:49.76#ibcon#wrote, iclass 23, count 0 2006.281.08:08:49.76#ibcon#about to read 3, iclass 23, count 0 2006.281.08:08:49.79#ibcon#read 3, iclass 23, count 0 2006.281.08:08:49.79#ibcon#about to read 4, iclass 23, count 0 2006.281.08:08:49.79#ibcon#read 4, iclass 23, count 0 2006.281.08:08:49.79#ibcon#about to read 5, iclass 23, count 0 2006.281.08:08:49.79#ibcon#read 5, iclass 23, count 0 2006.281.08:08:49.79#ibcon#about to read 6, iclass 23, count 0 2006.281.08:08:49.79#ibcon#read 6, iclass 23, count 0 2006.281.08:08:49.79#ibcon#end of sib2, iclass 23, count 0 2006.281.08:08:49.79#ibcon#*after write, iclass 23, count 0 2006.281.08:08:49.79#ibcon#*before return 0, iclass 23, count 0 2006.281.08:08:49.79#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:49.79#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:49.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:08:49.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:08:49.79$vc4f8/valo=4,832.99 2006.281.08:08:49.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:08:49.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:08:49.79#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:49.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:49.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:49.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:49.79#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:08:49.79#ibcon#first serial, iclass 25, count 0 2006.281.08:08:49.79#ibcon#enter sib2, iclass 25, count 0 2006.281.08:08:49.79#ibcon#flushed, iclass 25, count 0 2006.281.08:08:49.79#ibcon#about to write, iclass 25, count 0 2006.281.08:08:49.79#ibcon#wrote, iclass 25, count 0 2006.281.08:08:49.79#ibcon#about to read 3, iclass 25, count 0 2006.281.08:08:49.81#ibcon#read 3, iclass 25, count 0 2006.281.08:08:49.81#ibcon#about to read 4, iclass 25, count 0 2006.281.08:08:49.81#ibcon#read 4, iclass 25, count 0 2006.281.08:08:49.81#ibcon#about to read 5, iclass 25, count 0 2006.281.08:08:49.81#ibcon#read 5, iclass 25, count 0 2006.281.08:08:49.81#ibcon#about to read 6, iclass 25, count 0 2006.281.08:08:49.81#ibcon#read 6, iclass 25, count 0 2006.281.08:08:49.81#ibcon#end of sib2, iclass 25, count 0 2006.281.08:08:49.81#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:08:49.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:08:49.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:08:49.81#ibcon#*before write, iclass 25, count 0 2006.281.08:08:49.81#ibcon#enter sib2, iclass 25, count 0 2006.281.08:08:49.81#ibcon#flushed, iclass 25, count 0 2006.281.08:08:49.81#ibcon#about to write, iclass 25, count 0 2006.281.08:08:49.81#ibcon#wrote, iclass 25, count 0 2006.281.08:08:49.81#ibcon#about to read 3, iclass 25, count 0 2006.281.08:08:49.85#ibcon#read 3, iclass 25, count 0 2006.281.08:08:49.85#ibcon#about to read 4, iclass 25, count 0 2006.281.08:08:49.85#ibcon#read 4, iclass 25, count 0 2006.281.08:08:49.85#ibcon#about to read 5, iclass 25, count 0 2006.281.08:08:49.85#ibcon#read 5, iclass 25, count 0 2006.281.08:08:49.85#ibcon#about to read 6, iclass 25, count 0 2006.281.08:08:49.85#ibcon#read 6, iclass 25, count 0 2006.281.08:08:49.85#ibcon#end of sib2, iclass 25, count 0 2006.281.08:08:49.85#ibcon#*after write, iclass 25, count 0 2006.281.08:08:49.85#ibcon#*before return 0, iclass 25, count 0 2006.281.08:08:49.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:49.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:49.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:08:49.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:08:49.85$vc4f8/va=4,6 2006.281.08:08:49.86#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:08:49.86#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:08:49.86#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:49.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:49.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:49.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:49.91#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:08:49.91#ibcon#first serial, iclass 27, count 2 2006.281.08:08:49.91#ibcon#enter sib2, iclass 27, count 2 2006.281.08:08:49.91#ibcon#flushed, iclass 27, count 2 2006.281.08:08:49.91#ibcon#about to write, iclass 27, count 2 2006.281.08:08:49.91#ibcon#wrote, iclass 27, count 2 2006.281.08:08:49.91#ibcon#about to read 3, iclass 27, count 2 2006.281.08:08:49.93#ibcon#read 3, iclass 27, count 2 2006.281.08:08:49.93#ibcon#about to read 4, iclass 27, count 2 2006.281.08:08:49.93#ibcon#read 4, iclass 27, count 2 2006.281.08:08:49.93#ibcon#about to read 5, iclass 27, count 2 2006.281.08:08:49.93#ibcon#read 5, iclass 27, count 2 2006.281.08:08:49.93#ibcon#about to read 6, iclass 27, count 2 2006.281.08:08:49.93#ibcon#read 6, iclass 27, count 2 2006.281.08:08:49.93#ibcon#end of sib2, iclass 27, count 2 2006.281.08:08:49.93#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:08:49.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:08:49.93#ibcon#[25=AT04-06\r\n] 2006.281.08:08:49.93#ibcon#*before write, iclass 27, count 2 2006.281.08:08:49.93#ibcon#enter sib2, iclass 27, count 2 2006.281.08:08:49.93#ibcon#flushed, iclass 27, count 2 2006.281.08:08:49.93#ibcon#about to write, iclass 27, count 2 2006.281.08:08:49.93#ibcon#wrote, iclass 27, count 2 2006.281.08:08:49.93#ibcon#about to read 3, iclass 27, count 2 2006.281.08:08:49.96#ibcon#read 3, iclass 27, count 2 2006.281.08:08:49.96#ibcon#about to read 4, iclass 27, count 2 2006.281.08:08:49.96#ibcon#read 4, iclass 27, count 2 2006.281.08:08:49.96#ibcon#about to read 5, iclass 27, count 2 2006.281.08:08:49.96#ibcon#read 5, iclass 27, count 2 2006.281.08:08:49.96#ibcon#about to read 6, iclass 27, count 2 2006.281.08:08:49.96#ibcon#read 6, iclass 27, count 2 2006.281.08:08:49.96#ibcon#end of sib2, iclass 27, count 2 2006.281.08:08:49.96#ibcon#*after write, iclass 27, count 2 2006.281.08:08:49.96#ibcon#*before return 0, iclass 27, count 2 2006.281.08:08:49.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:49.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:49.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:08:49.96#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:49.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:50.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:50.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:50.08#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:08:50.08#ibcon#first serial, iclass 27, count 0 2006.281.08:08:50.08#ibcon#enter sib2, iclass 27, count 0 2006.281.08:08:50.08#ibcon#flushed, iclass 27, count 0 2006.281.08:08:50.08#ibcon#about to write, iclass 27, count 0 2006.281.08:08:50.08#ibcon#wrote, iclass 27, count 0 2006.281.08:08:50.08#ibcon#about to read 3, iclass 27, count 0 2006.281.08:08:50.10#ibcon#read 3, iclass 27, count 0 2006.281.08:08:50.10#ibcon#about to read 4, iclass 27, count 0 2006.281.08:08:50.10#ibcon#read 4, iclass 27, count 0 2006.281.08:08:50.10#ibcon#about to read 5, iclass 27, count 0 2006.281.08:08:50.10#ibcon#read 5, iclass 27, count 0 2006.281.08:08:50.10#ibcon#about to read 6, iclass 27, count 0 2006.281.08:08:50.10#ibcon#read 6, iclass 27, count 0 2006.281.08:08:50.10#ibcon#end of sib2, iclass 27, count 0 2006.281.08:08:50.10#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:08:50.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:08:50.10#ibcon#[25=USB\r\n] 2006.281.08:08:50.10#ibcon#*before write, iclass 27, count 0 2006.281.08:08:50.10#ibcon#enter sib2, iclass 27, count 0 2006.281.08:08:50.10#ibcon#flushed, iclass 27, count 0 2006.281.08:08:50.10#ibcon#about to write, iclass 27, count 0 2006.281.08:08:50.10#ibcon#wrote, iclass 27, count 0 2006.281.08:08:50.10#ibcon#about to read 3, iclass 27, count 0 2006.281.08:08:50.13#ibcon#read 3, iclass 27, count 0 2006.281.08:08:50.13#ibcon#about to read 4, iclass 27, count 0 2006.281.08:08:50.13#ibcon#read 4, iclass 27, count 0 2006.281.08:08:50.13#ibcon#about to read 5, iclass 27, count 0 2006.281.08:08:50.13#ibcon#read 5, iclass 27, count 0 2006.281.08:08:50.13#ibcon#about to read 6, iclass 27, count 0 2006.281.08:08:50.13#ibcon#read 6, iclass 27, count 0 2006.281.08:08:50.13#ibcon#end of sib2, iclass 27, count 0 2006.281.08:08:50.13#ibcon#*after write, iclass 27, count 0 2006.281.08:08:50.13#ibcon#*before return 0, iclass 27, count 0 2006.281.08:08:50.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:50.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:50.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:08:50.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:08:50.13$vc4f8/valo=5,652.99 2006.281.08:08:50.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:08:50.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:08:50.13#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:50.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:50.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:50.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:50.13#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:08:50.13#ibcon#first serial, iclass 29, count 0 2006.281.08:08:50.13#ibcon#enter sib2, iclass 29, count 0 2006.281.08:08:50.13#ibcon#flushed, iclass 29, count 0 2006.281.08:08:50.13#ibcon#about to write, iclass 29, count 0 2006.281.08:08:50.13#ibcon#wrote, iclass 29, count 0 2006.281.08:08:50.13#ibcon#about to read 3, iclass 29, count 0 2006.281.08:08:50.15#ibcon#read 3, iclass 29, count 0 2006.281.08:08:50.15#ibcon#about to read 4, iclass 29, count 0 2006.281.08:08:50.15#ibcon#read 4, iclass 29, count 0 2006.281.08:08:50.15#ibcon#about to read 5, iclass 29, count 0 2006.281.08:08:50.15#ibcon#read 5, iclass 29, count 0 2006.281.08:08:50.15#ibcon#about to read 6, iclass 29, count 0 2006.281.08:08:50.15#ibcon#read 6, iclass 29, count 0 2006.281.08:08:50.15#ibcon#end of sib2, iclass 29, count 0 2006.281.08:08:50.15#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:08:50.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:08:50.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:08:50.16#ibcon#*before write, iclass 29, count 0 2006.281.08:08:50.16#ibcon#enter sib2, iclass 29, count 0 2006.281.08:08:50.16#ibcon#flushed, iclass 29, count 0 2006.281.08:08:50.16#ibcon#about to write, iclass 29, count 0 2006.281.08:08:50.16#ibcon#wrote, iclass 29, count 0 2006.281.08:08:50.16#ibcon#about to read 3, iclass 29, count 0 2006.281.08:08:50.20#ibcon#read 3, iclass 29, count 0 2006.281.08:08:50.20#ibcon#about to read 4, iclass 29, count 0 2006.281.08:08:50.20#ibcon#read 4, iclass 29, count 0 2006.281.08:08:50.20#ibcon#about to read 5, iclass 29, count 0 2006.281.08:08:50.20#ibcon#read 5, iclass 29, count 0 2006.281.08:08:50.20#ibcon#about to read 6, iclass 29, count 0 2006.281.08:08:50.20#ibcon#read 6, iclass 29, count 0 2006.281.08:08:50.20#ibcon#end of sib2, iclass 29, count 0 2006.281.08:08:50.20#ibcon#*after write, iclass 29, count 0 2006.281.08:08:50.20#ibcon#*before return 0, iclass 29, count 0 2006.281.08:08:50.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:50.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:50.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:08:50.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:08:50.20$vc4f8/va=5,7 2006.281.08:08:50.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:08:50.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:08:50.20#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:50.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:50.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:50.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:50.25#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:08:50.25#ibcon#first serial, iclass 31, count 2 2006.281.08:08:50.25#ibcon#enter sib2, iclass 31, count 2 2006.281.08:08:50.25#ibcon#flushed, iclass 31, count 2 2006.281.08:08:50.25#ibcon#about to write, iclass 31, count 2 2006.281.08:08:50.25#ibcon#wrote, iclass 31, count 2 2006.281.08:08:50.25#ibcon#about to read 3, iclass 31, count 2 2006.281.08:08:50.27#ibcon#read 3, iclass 31, count 2 2006.281.08:08:50.27#ibcon#about to read 4, iclass 31, count 2 2006.281.08:08:50.27#ibcon#read 4, iclass 31, count 2 2006.281.08:08:50.27#ibcon#about to read 5, iclass 31, count 2 2006.281.08:08:50.27#ibcon#read 5, iclass 31, count 2 2006.281.08:08:50.27#ibcon#about to read 6, iclass 31, count 2 2006.281.08:08:50.27#ibcon#read 6, iclass 31, count 2 2006.281.08:08:50.27#ibcon#end of sib2, iclass 31, count 2 2006.281.08:08:50.27#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:08:50.27#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:08:50.27#ibcon#[25=AT05-07\r\n] 2006.281.08:08:50.27#ibcon#*before write, iclass 31, count 2 2006.281.08:08:50.27#ibcon#enter sib2, iclass 31, count 2 2006.281.08:08:50.27#ibcon#flushed, iclass 31, count 2 2006.281.08:08:50.27#ibcon#about to write, iclass 31, count 2 2006.281.08:08:50.27#ibcon#wrote, iclass 31, count 2 2006.281.08:08:50.27#ibcon#about to read 3, iclass 31, count 2 2006.281.08:08:50.30#ibcon#read 3, iclass 31, count 2 2006.281.08:08:50.30#ibcon#about to read 4, iclass 31, count 2 2006.281.08:08:50.30#ibcon#read 4, iclass 31, count 2 2006.281.08:08:50.30#ibcon#about to read 5, iclass 31, count 2 2006.281.08:08:50.30#ibcon#read 5, iclass 31, count 2 2006.281.08:08:50.30#ibcon#about to read 6, iclass 31, count 2 2006.281.08:08:50.30#ibcon#read 6, iclass 31, count 2 2006.281.08:08:50.30#ibcon#end of sib2, iclass 31, count 2 2006.281.08:08:50.30#ibcon#*after write, iclass 31, count 2 2006.281.08:08:50.30#ibcon#*before return 0, iclass 31, count 2 2006.281.08:08:50.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:50.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:50.30#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:08:50.30#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:50.30#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:50.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:50.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:50.42#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:08:50.42#ibcon#first serial, iclass 31, count 0 2006.281.08:08:50.42#ibcon#enter sib2, iclass 31, count 0 2006.281.08:08:50.42#ibcon#flushed, iclass 31, count 0 2006.281.08:08:50.42#ibcon#about to write, iclass 31, count 0 2006.281.08:08:50.42#ibcon#wrote, iclass 31, count 0 2006.281.08:08:50.42#ibcon#about to read 3, iclass 31, count 0 2006.281.08:08:50.44#ibcon#read 3, iclass 31, count 0 2006.281.08:08:50.44#ibcon#about to read 4, iclass 31, count 0 2006.281.08:08:50.44#ibcon#read 4, iclass 31, count 0 2006.281.08:08:50.44#ibcon#about to read 5, iclass 31, count 0 2006.281.08:08:50.44#ibcon#read 5, iclass 31, count 0 2006.281.08:08:50.44#ibcon#about to read 6, iclass 31, count 0 2006.281.08:08:50.44#ibcon#read 6, iclass 31, count 0 2006.281.08:08:50.44#ibcon#end of sib2, iclass 31, count 0 2006.281.08:08:50.44#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:08:50.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:08:50.44#ibcon#[25=USB\r\n] 2006.281.08:08:50.44#ibcon#*before write, iclass 31, count 0 2006.281.08:08:50.44#ibcon#enter sib2, iclass 31, count 0 2006.281.08:08:50.44#ibcon#flushed, iclass 31, count 0 2006.281.08:08:50.44#ibcon#about to write, iclass 31, count 0 2006.281.08:08:50.44#ibcon#wrote, iclass 31, count 0 2006.281.08:08:50.44#ibcon#about to read 3, iclass 31, count 0 2006.281.08:08:50.47#ibcon#read 3, iclass 31, count 0 2006.281.08:08:50.47#ibcon#about to read 4, iclass 31, count 0 2006.281.08:08:50.47#ibcon#read 4, iclass 31, count 0 2006.281.08:08:50.47#ibcon#about to read 5, iclass 31, count 0 2006.281.08:08:50.47#ibcon#read 5, iclass 31, count 0 2006.281.08:08:50.47#ibcon#about to read 6, iclass 31, count 0 2006.281.08:08:50.47#ibcon#read 6, iclass 31, count 0 2006.281.08:08:50.47#ibcon#end of sib2, iclass 31, count 0 2006.281.08:08:50.47#ibcon#*after write, iclass 31, count 0 2006.281.08:08:50.47#ibcon#*before return 0, iclass 31, count 0 2006.281.08:08:50.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:50.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:50.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:08:50.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:08:50.47$vc4f8/valo=6,772.99 2006.281.08:08:50.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:08:50.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:08:50.47#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:50.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:50.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:50.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:50.47#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:08:50.47#ibcon#first serial, iclass 33, count 0 2006.281.08:08:50.47#ibcon#enter sib2, iclass 33, count 0 2006.281.08:08:50.47#ibcon#flushed, iclass 33, count 0 2006.281.08:08:50.47#ibcon#about to write, iclass 33, count 0 2006.281.08:08:50.47#ibcon#wrote, iclass 33, count 0 2006.281.08:08:50.47#ibcon#about to read 3, iclass 33, count 0 2006.281.08:08:50.49#ibcon#read 3, iclass 33, count 0 2006.281.08:08:50.49#ibcon#about to read 4, iclass 33, count 0 2006.281.08:08:50.49#ibcon#read 4, iclass 33, count 0 2006.281.08:08:50.49#ibcon#about to read 5, iclass 33, count 0 2006.281.08:08:50.49#ibcon#read 5, iclass 33, count 0 2006.281.08:08:50.49#ibcon#about to read 6, iclass 33, count 0 2006.281.08:08:50.49#ibcon#read 6, iclass 33, count 0 2006.281.08:08:50.49#ibcon#end of sib2, iclass 33, count 0 2006.281.08:08:50.49#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:08:50.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:08:50.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:08:50.49#ibcon#*before write, iclass 33, count 0 2006.281.08:08:50.49#ibcon#enter sib2, iclass 33, count 0 2006.281.08:08:50.49#ibcon#flushed, iclass 33, count 0 2006.281.08:08:50.49#ibcon#about to write, iclass 33, count 0 2006.281.08:08:50.49#ibcon#wrote, iclass 33, count 0 2006.281.08:08:50.49#ibcon#about to read 3, iclass 33, count 0 2006.281.08:08:50.53#ibcon#read 3, iclass 33, count 0 2006.281.08:08:50.53#ibcon#about to read 4, iclass 33, count 0 2006.281.08:08:50.53#ibcon#read 4, iclass 33, count 0 2006.281.08:08:50.53#ibcon#about to read 5, iclass 33, count 0 2006.281.08:08:50.53#ibcon#read 5, iclass 33, count 0 2006.281.08:08:50.53#ibcon#about to read 6, iclass 33, count 0 2006.281.08:08:50.53#ibcon#read 6, iclass 33, count 0 2006.281.08:08:50.53#ibcon#end of sib2, iclass 33, count 0 2006.281.08:08:50.53#ibcon#*after write, iclass 33, count 0 2006.281.08:08:50.53#ibcon#*before return 0, iclass 33, count 0 2006.281.08:08:50.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:50.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:50.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:08:50.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:08:50.53$vc4f8/va=6,6 2006.281.08:08:50.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:08:50.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:08:50.53#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:50.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:50.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:50.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:50.59#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:08:50.59#ibcon#first serial, iclass 35, count 2 2006.281.08:08:50.59#ibcon#enter sib2, iclass 35, count 2 2006.281.08:08:50.59#ibcon#flushed, iclass 35, count 2 2006.281.08:08:50.59#ibcon#about to write, iclass 35, count 2 2006.281.08:08:50.59#ibcon#wrote, iclass 35, count 2 2006.281.08:08:50.59#ibcon#about to read 3, iclass 35, count 2 2006.281.08:08:50.61#ibcon#read 3, iclass 35, count 2 2006.281.08:08:50.61#ibcon#about to read 4, iclass 35, count 2 2006.281.08:08:50.61#ibcon#read 4, iclass 35, count 2 2006.281.08:08:50.61#ibcon#about to read 5, iclass 35, count 2 2006.281.08:08:50.61#ibcon#read 5, iclass 35, count 2 2006.281.08:08:50.61#ibcon#about to read 6, iclass 35, count 2 2006.281.08:08:50.61#ibcon#read 6, iclass 35, count 2 2006.281.08:08:50.61#ibcon#end of sib2, iclass 35, count 2 2006.281.08:08:50.61#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:08:50.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:08:50.61#ibcon#[25=AT06-06\r\n] 2006.281.08:08:50.61#ibcon#*before write, iclass 35, count 2 2006.281.08:08:50.61#ibcon#enter sib2, iclass 35, count 2 2006.281.08:08:50.61#ibcon#flushed, iclass 35, count 2 2006.281.08:08:50.61#ibcon#about to write, iclass 35, count 2 2006.281.08:08:50.61#ibcon#wrote, iclass 35, count 2 2006.281.08:08:50.61#ibcon#about to read 3, iclass 35, count 2 2006.281.08:08:50.65#ibcon#read 3, iclass 35, count 2 2006.281.08:08:50.65#ibcon#about to read 4, iclass 35, count 2 2006.281.08:08:50.65#ibcon#read 4, iclass 35, count 2 2006.281.08:08:50.65#ibcon#about to read 5, iclass 35, count 2 2006.281.08:08:50.65#ibcon#read 5, iclass 35, count 2 2006.281.08:08:50.65#ibcon#about to read 6, iclass 35, count 2 2006.281.08:08:50.65#ibcon#read 6, iclass 35, count 2 2006.281.08:08:50.65#ibcon#end of sib2, iclass 35, count 2 2006.281.08:08:50.65#ibcon#*after write, iclass 35, count 2 2006.281.08:08:50.65#ibcon#*before return 0, iclass 35, count 2 2006.281.08:08:50.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:50.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:50.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:08:50.65#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:50.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:50.76#abcon#<5=/13 2.2 7.8 20.25 521001.6\r\n> 2006.281.08:08:50.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:50.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:50.77#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:08:50.77#ibcon#first serial, iclass 35, count 0 2006.281.08:08:50.77#ibcon#enter sib2, iclass 35, count 0 2006.281.08:08:50.77#ibcon#flushed, iclass 35, count 0 2006.281.08:08:50.77#ibcon#about to write, iclass 35, count 0 2006.281.08:08:50.77#ibcon#wrote, iclass 35, count 0 2006.281.08:08:50.77#ibcon#about to read 3, iclass 35, count 0 2006.281.08:08:50.78#abcon#{5=INTERFACE CLEAR} 2006.281.08:08:50.79#ibcon#read 3, iclass 35, count 0 2006.281.08:08:50.79#ibcon#about to read 4, iclass 35, count 0 2006.281.08:08:50.79#ibcon#read 4, iclass 35, count 0 2006.281.08:08:50.79#ibcon#about to read 5, iclass 35, count 0 2006.281.08:08:50.79#ibcon#read 5, iclass 35, count 0 2006.281.08:08:50.79#ibcon#about to read 6, iclass 35, count 0 2006.281.08:08:50.79#ibcon#read 6, iclass 35, count 0 2006.281.08:08:50.79#ibcon#end of sib2, iclass 35, count 0 2006.281.08:08:50.79#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:08:50.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:08:50.79#ibcon#[25=USB\r\n] 2006.281.08:08:50.79#ibcon#*before write, iclass 35, count 0 2006.281.08:08:50.79#ibcon#enter sib2, iclass 35, count 0 2006.281.08:08:50.79#ibcon#flushed, iclass 35, count 0 2006.281.08:08:50.79#ibcon#about to write, iclass 35, count 0 2006.281.08:08:50.79#ibcon#wrote, iclass 35, count 0 2006.281.08:08:50.79#ibcon#about to read 3, iclass 35, count 0 2006.281.08:08:50.82#ibcon#read 3, iclass 35, count 0 2006.281.08:08:50.82#ibcon#about to read 4, iclass 35, count 0 2006.281.08:08:50.82#ibcon#read 4, iclass 35, count 0 2006.281.08:08:50.82#ibcon#about to read 5, iclass 35, count 0 2006.281.08:08:50.82#ibcon#read 5, iclass 35, count 0 2006.281.08:08:50.82#ibcon#about to read 6, iclass 35, count 0 2006.281.08:08:50.82#ibcon#read 6, iclass 35, count 0 2006.281.08:08:50.82#ibcon#end of sib2, iclass 35, count 0 2006.281.08:08:50.82#ibcon#*after write, iclass 35, count 0 2006.281.08:08:50.82#ibcon#*before return 0, iclass 35, count 0 2006.281.08:08:50.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:50.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:50.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:08:50.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:08:50.82$vc4f8/valo=7,832.99 2006.281.08:08:50.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:08:50.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:08:50.82#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:50.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:08:50.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:08:50.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:08:50.82#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:08:50.82#ibcon#first serial, iclass 40, count 0 2006.281.08:08:50.82#ibcon#enter sib2, iclass 40, count 0 2006.281.08:08:50.82#ibcon#flushed, iclass 40, count 0 2006.281.08:08:50.82#ibcon#about to write, iclass 40, count 0 2006.281.08:08:50.82#ibcon#wrote, iclass 40, count 0 2006.281.08:08:50.82#ibcon#about to read 3, iclass 40, count 0 2006.281.08:08:50.84#ibcon#read 3, iclass 40, count 0 2006.281.08:08:50.84#ibcon#about to read 4, iclass 40, count 0 2006.281.08:08:50.84#ibcon#read 4, iclass 40, count 0 2006.281.08:08:50.84#ibcon#about to read 5, iclass 40, count 0 2006.281.08:08:50.84#ibcon#read 5, iclass 40, count 0 2006.281.08:08:50.84#ibcon#about to read 6, iclass 40, count 0 2006.281.08:08:50.84#ibcon#read 6, iclass 40, count 0 2006.281.08:08:50.84#ibcon#end of sib2, iclass 40, count 0 2006.281.08:08:50.84#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:08:50.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:08:50.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:08:50.84#ibcon#*before write, iclass 40, count 0 2006.281.08:08:50.84#ibcon#enter sib2, iclass 40, count 0 2006.281.08:08:50.84#ibcon#flushed, iclass 40, count 0 2006.281.08:08:50.84#ibcon#about to write, iclass 40, count 0 2006.281.08:08:50.84#ibcon#wrote, iclass 40, count 0 2006.281.08:08:50.84#ibcon#about to read 3, iclass 40, count 0 2006.281.08:08:50.84#abcon#[5=S1D000X0/0*\r\n] 2006.281.08:08:50.88#ibcon#read 3, iclass 40, count 0 2006.281.08:08:50.88#ibcon#about to read 4, iclass 40, count 0 2006.281.08:08:50.88#ibcon#read 4, iclass 40, count 0 2006.281.08:08:50.88#ibcon#about to read 5, iclass 40, count 0 2006.281.08:08:50.88#ibcon#read 5, iclass 40, count 0 2006.281.08:08:50.88#ibcon#about to read 6, iclass 40, count 0 2006.281.08:08:50.88#ibcon#read 6, iclass 40, count 0 2006.281.08:08:50.88#ibcon#end of sib2, iclass 40, count 0 2006.281.08:08:50.88#ibcon#*after write, iclass 40, count 0 2006.281.08:08:50.88#ibcon#*before return 0, iclass 40, count 0 2006.281.08:08:50.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:08:50.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:08:50.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:08:50.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:08:50.88$vc4f8/va=7,6 2006.281.08:08:50.88#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.08:08:50.88#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.08:08:50.88#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:50.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:08:50.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:08:50.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:08:50.94#ibcon#enter wrdev, iclass 5, count 2 2006.281.08:08:50.94#ibcon#first serial, iclass 5, count 2 2006.281.08:08:50.94#ibcon#enter sib2, iclass 5, count 2 2006.281.08:08:50.94#ibcon#flushed, iclass 5, count 2 2006.281.08:08:50.94#ibcon#about to write, iclass 5, count 2 2006.281.08:08:50.94#ibcon#wrote, iclass 5, count 2 2006.281.08:08:50.94#ibcon#about to read 3, iclass 5, count 2 2006.281.08:08:50.96#ibcon#read 3, iclass 5, count 2 2006.281.08:08:50.96#ibcon#about to read 4, iclass 5, count 2 2006.281.08:08:50.96#ibcon#read 4, iclass 5, count 2 2006.281.08:08:50.96#ibcon#about to read 5, iclass 5, count 2 2006.281.08:08:50.96#ibcon#read 5, iclass 5, count 2 2006.281.08:08:50.96#ibcon#about to read 6, iclass 5, count 2 2006.281.08:08:50.96#ibcon#read 6, iclass 5, count 2 2006.281.08:08:50.96#ibcon#end of sib2, iclass 5, count 2 2006.281.08:08:50.96#ibcon#*mode == 0, iclass 5, count 2 2006.281.08:08:50.96#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.08:08:50.96#ibcon#[25=AT07-06\r\n] 2006.281.08:08:50.96#ibcon#*before write, iclass 5, count 2 2006.281.08:08:50.96#ibcon#enter sib2, iclass 5, count 2 2006.281.08:08:50.96#ibcon#flushed, iclass 5, count 2 2006.281.08:08:50.96#ibcon#about to write, iclass 5, count 2 2006.281.08:08:50.96#ibcon#wrote, iclass 5, count 2 2006.281.08:08:50.96#ibcon#about to read 3, iclass 5, count 2 2006.281.08:08:50.99#ibcon#read 3, iclass 5, count 2 2006.281.08:08:50.99#ibcon#about to read 4, iclass 5, count 2 2006.281.08:08:50.99#ibcon#read 4, iclass 5, count 2 2006.281.08:08:50.99#ibcon#about to read 5, iclass 5, count 2 2006.281.08:08:50.99#ibcon#read 5, iclass 5, count 2 2006.281.08:08:50.99#ibcon#about to read 6, iclass 5, count 2 2006.281.08:08:50.99#ibcon#read 6, iclass 5, count 2 2006.281.08:08:50.99#ibcon#end of sib2, iclass 5, count 2 2006.281.08:08:50.99#ibcon#*after write, iclass 5, count 2 2006.281.08:08:50.99#ibcon#*before return 0, iclass 5, count 2 2006.281.08:08:50.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:08:50.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:08:50.99#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.08:08:50.99#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:50.99#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:08:51.11#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:08:51.11#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:08:51.11#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:08:51.11#ibcon#first serial, iclass 5, count 0 2006.281.08:08:51.11#ibcon#enter sib2, iclass 5, count 0 2006.281.08:08:51.11#ibcon#flushed, iclass 5, count 0 2006.281.08:08:51.11#ibcon#about to write, iclass 5, count 0 2006.281.08:08:51.11#ibcon#wrote, iclass 5, count 0 2006.281.08:08:51.11#ibcon#about to read 3, iclass 5, count 0 2006.281.08:08:51.13#ibcon#read 3, iclass 5, count 0 2006.281.08:08:51.13#ibcon#about to read 4, iclass 5, count 0 2006.281.08:08:51.13#ibcon#read 4, iclass 5, count 0 2006.281.08:08:51.13#ibcon#about to read 5, iclass 5, count 0 2006.281.08:08:51.13#ibcon#read 5, iclass 5, count 0 2006.281.08:08:51.13#ibcon#about to read 6, iclass 5, count 0 2006.281.08:08:51.13#ibcon#read 6, iclass 5, count 0 2006.281.08:08:51.13#ibcon#end of sib2, iclass 5, count 0 2006.281.08:08:51.13#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:08:51.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:08:51.13#ibcon#[25=USB\r\n] 2006.281.08:08:51.13#ibcon#*before write, iclass 5, count 0 2006.281.08:08:51.13#ibcon#enter sib2, iclass 5, count 0 2006.281.08:08:51.13#ibcon#flushed, iclass 5, count 0 2006.281.08:08:51.13#ibcon#about to write, iclass 5, count 0 2006.281.08:08:51.13#ibcon#wrote, iclass 5, count 0 2006.281.08:08:51.13#ibcon#about to read 3, iclass 5, count 0 2006.281.08:08:51.16#ibcon#read 3, iclass 5, count 0 2006.281.08:08:51.16#ibcon#about to read 4, iclass 5, count 0 2006.281.08:08:51.16#ibcon#read 4, iclass 5, count 0 2006.281.08:08:51.16#ibcon#about to read 5, iclass 5, count 0 2006.281.08:08:51.16#ibcon#read 5, iclass 5, count 0 2006.281.08:08:51.16#ibcon#about to read 6, iclass 5, count 0 2006.281.08:08:51.16#ibcon#read 6, iclass 5, count 0 2006.281.08:08:51.16#ibcon#end of sib2, iclass 5, count 0 2006.281.08:08:51.16#ibcon#*after write, iclass 5, count 0 2006.281.08:08:51.16#ibcon#*before return 0, iclass 5, count 0 2006.281.08:08:51.16#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:08:51.16#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:08:51.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:08:51.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:08:51.16$vc4f8/valo=8,852.99 2006.281.08:08:51.16#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:08:51.16#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:08:51.16#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:51.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:08:51.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:08:51.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:08:51.16#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:08:51.16#ibcon#first serial, iclass 7, count 0 2006.281.08:08:51.16#ibcon#enter sib2, iclass 7, count 0 2006.281.08:08:51.16#ibcon#flushed, iclass 7, count 0 2006.281.08:08:51.16#ibcon#about to write, iclass 7, count 0 2006.281.08:08:51.16#ibcon#wrote, iclass 7, count 0 2006.281.08:08:51.16#ibcon#about to read 3, iclass 7, count 0 2006.281.08:08:51.18#ibcon#read 3, iclass 7, count 0 2006.281.08:08:51.18#ibcon#about to read 4, iclass 7, count 0 2006.281.08:08:51.18#ibcon#read 4, iclass 7, count 0 2006.281.08:08:51.18#ibcon#about to read 5, iclass 7, count 0 2006.281.08:08:51.18#ibcon#read 5, iclass 7, count 0 2006.281.08:08:51.18#ibcon#about to read 6, iclass 7, count 0 2006.281.08:08:51.18#ibcon#read 6, iclass 7, count 0 2006.281.08:08:51.18#ibcon#end of sib2, iclass 7, count 0 2006.281.08:08:51.18#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:08:51.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:08:51.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:08:51.18#ibcon#*before write, iclass 7, count 0 2006.281.08:08:51.18#ibcon#enter sib2, iclass 7, count 0 2006.281.08:08:51.18#ibcon#flushed, iclass 7, count 0 2006.281.08:08:51.18#ibcon#about to write, iclass 7, count 0 2006.281.08:08:51.18#ibcon#wrote, iclass 7, count 0 2006.281.08:08:51.18#ibcon#about to read 3, iclass 7, count 0 2006.281.08:08:51.22#ibcon#read 3, iclass 7, count 0 2006.281.08:08:51.22#ibcon#about to read 4, iclass 7, count 0 2006.281.08:08:51.22#ibcon#read 4, iclass 7, count 0 2006.281.08:08:51.22#ibcon#about to read 5, iclass 7, count 0 2006.281.08:08:51.22#ibcon#read 5, iclass 7, count 0 2006.281.08:08:51.22#ibcon#about to read 6, iclass 7, count 0 2006.281.08:08:51.22#ibcon#read 6, iclass 7, count 0 2006.281.08:08:51.22#ibcon#end of sib2, iclass 7, count 0 2006.281.08:08:51.22#ibcon#*after write, iclass 7, count 0 2006.281.08:08:51.22#ibcon#*before return 0, iclass 7, count 0 2006.281.08:08:51.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:08:51.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:08:51.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:08:51.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:08:51.22$vc4f8/va=8,6 2006.281.08:08:51.22#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:08:51.22#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:08:51.22#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:51.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:08:51.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:08:51.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:08:51.28#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:08:51.28#ibcon#first serial, iclass 11, count 2 2006.281.08:08:51.28#ibcon#enter sib2, iclass 11, count 2 2006.281.08:08:51.28#ibcon#flushed, iclass 11, count 2 2006.281.08:08:51.28#ibcon#about to write, iclass 11, count 2 2006.281.08:08:51.28#ibcon#wrote, iclass 11, count 2 2006.281.08:08:51.28#ibcon#about to read 3, iclass 11, count 2 2006.281.08:08:51.30#ibcon#read 3, iclass 11, count 2 2006.281.08:08:51.30#ibcon#about to read 4, iclass 11, count 2 2006.281.08:08:51.30#ibcon#read 4, iclass 11, count 2 2006.281.08:08:51.30#ibcon#about to read 5, iclass 11, count 2 2006.281.08:08:51.30#ibcon#read 5, iclass 11, count 2 2006.281.08:08:51.30#ibcon#about to read 6, iclass 11, count 2 2006.281.08:08:51.30#ibcon#read 6, iclass 11, count 2 2006.281.08:08:51.30#ibcon#end of sib2, iclass 11, count 2 2006.281.08:08:51.30#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:08:51.30#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:08:51.30#ibcon#[25=AT08-06\r\n] 2006.281.08:08:51.30#ibcon#*before write, iclass 11, count 2 2006.281.08:08:51.30#ibcon#enter sib2, iclass 11, count 2 2006.281.08:08:51.30#ibcon#flushed, iclass 11, count 2 2006.281.08:08:51.30#ibcon#about to write, iclass 11, count 2 2006.281.08:08:51.30#ibcon#wrote, iclass 11, count 2 2006.281.08:08:51.30#ibcon#about to read 3, iclass 11, count 2 2006.281.08:08:51.33#ibcon#read 3, iclass 11, count 2 2006.281.08:08:51.33#ibcon#about to read 4, iclass 11, count 2 2006.281.08:08:51.33#ibcon#read 4, iclass 11, count 2 2006.281.08:08:51.33#ibcon#about to read 5, iclass 11, count 2 2006.281.08:08:51.33#ibcon#read 5, iclass 11, count 2 2006.281.08:08:51.33#ibcon#about to read 6, iclass 11, count 2 2006.281.08:08:51.33#ibcon#read 6, iclass 11, count 2 2006.281.08:08:51.33#ibcon#end of sib2, iclass 11, count 2 2006.281.08:08:51.33#ibcon#*after write, iclass 11, count 2 2006.281.08:08:51.33#ibcon#*before return 0, iclass 11, count 2 2006.281.08:08:51.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:08:51.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:08:51.33#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:08:51.33#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:51.33#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:08:51.45#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:08:51.45#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:08:51.45#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:08:51.45#ibcon#first serial, iclass 11, count 0 2006.281.08:08:51.45#ibcon#enter sib2, iclass 11, count 0 2006.281.08:08:51.45#ibcon#flushed, iclass 11, count 0 2006.281.08:08:51.45#ibcon#about to write, iclass 11, count 0 2006.281.08:08:51.45#ibcon#wrote, iclass 11, count 0 2006.281.08:08:51.45#ibcon#about to read 3, iclass 11, count 0 2006.281.08:08:51.47#ibcon#read 3, iclass 11, count 0 2006.281.08:08:51.47#ibcon#about to read 4, iclass 11, count 0 2006.281.08:08:51.47#ibcon#read 4, iclass 11, count 0 2006.281.08:08:51.47#ibcon#about to read 5, iclass 11, count 0 2006.281.08:08:51.47#ibcon#read 5, iclass 11, count 0 2006.281.08:08:51.47#ibcon#about to read 6, iclass 11, count 0 2006.281.08:08:51.47#ibcon#read 6, iclass 11, count 0 2006.281.08:08:51.47#ibcon#end of sib2, iclass 11, count 0 2006.281.08:08:51.47#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:08:51.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:08:51.47#ibcon#[25=USB\r\n] 2006.281.08:08:51.47#ibcon#*before write, iclass 11, count 0 2006.281.08:08:51.47#ibcon#enter sib2, iclass 11, count 0 2006.281.08:08:51.47#ibcon#flushed, iclass 11, count 0 2006.281.08:08:51.47#ibcon#about to write, iclass 11, count 0 2006.281.08:08:51.47#ibcon#wrote, iclass 11, count 0 2006.281.08:08:51.47#ibcon#about to read 3, iclass 11, count 0 2006.281.08:08:51.50#ibcon#read 3, iclass 11, count 0 2006.281.08:08:51.50#ibcon#about to read 4, iclass 11, count 0 2006.281.08:08:51.50#ibcon#read 4, iclass 11, count 0 2006.281.08:08:51.50#ibcon#about to read 5, iclass 11, count 0 2006.281.08:08:51.50#ibcon#read 5, iclass 11, count 0 2006.281.08:08:51.50#ibcon#about to read 6, iclass 11, count 0 2006.281.08:08:51.50#ibcon#read 6, iclass 11, count 0 2006.281.08:08:51.50#ibcon#end of sib2, iclass 11, count 0 2006.281.08:08:51.50#ibcon#*after write, iclass 11, count 0 2006.281.08:08:51.50#ibcon#*before return 0, iclass 11, count 0 2006.281.08:08:51.50#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:08:51.50#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:08:51.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:08:51.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:08:51.50$vc4f8/vblo=1,632.99 2006.281.08:08:51.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:08:51.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:08:51.50#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:51.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:51.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:51.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:51.50#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:08:51.50#ibcon#first serial, iclass 13, count 0 2006.281.08:08:51.50#ibcon#enter sib2, iclass 13, count 0 2006.281.08:08:51.50#ibcon#flushed, iclass 13, count 0 2006.281.08:08:51.50#ibcon#about to write, iclass 13, count 0 2006.281.08:08:51.50#ibcon#wrote, iclass 13, count 0 2006.281.08:08:51.50#ibcon#about to read 3, iclass 13, count 0 2006.281.08:08:51.52#ibcon#read 3, iclass 13, count 0 2006.281.08:08:51.52#ibcon#about to read 4, iclass 13, count 0 2006.281.08:08:51.52#ibcon#read 4, iclass 13, count 0 2006.281.08:08:51.52#ibcon#about to read 5, iclass 13, count 0 2006.281.08:08:51.52#ibcon#read 5, iclass 13, count 0 2006.281.08:08:51.52#ibcon#about to read 6, iclass 13, count 0 2006.281.08:08:51.52#ibcon#read 6, iclass 13, count 0 2006.281.08:08:51.52#ibcon#end of sib2, iclass 13, count 0 2006.281.08:08:51.52#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:08:51.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:08:51.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:08:51.52#ibcon#*before write, iclass 13, count 0 2006.281.08:08:51.52#ibcon#enter sib2, iclass 13, count 0 2006.281.08:08:51.52#ibcon#flushed, iclass 13, count 0 2006.281.08:08:51.52#ibcon#about to write, iclass 13, count 0 2006.281.08:08:51.52#ibcon#wrote, iclass 13, count 0 2006.281.08:08:51.52#ibcon#about to read 3, iclass 13, count 0 2006.281.08:08:51.56#ibcon#read 3, iclass 13, count 0 2006.281.08:08:51.56#ibcon#about to read 4, iclass 13, count 0 2006.281.08:08:51.56#ibcon#read 4, iclass 13, count 0 2006.281.08:08:51.56#ibcon#about to read 5, iclass 13, count 0 2006.281.08:08:51.56#ibcon#read 5, iclass 13, count 0 2006.281.08:08:51.56#ibcon#about to read 6, iclass 13, count 0 2006.281.08:08:51.56#ibcon#read 6, iclass 13, count 0 2006.281.08:08:51.56#ibcon#end of sib2, iclass 13, count 0 2006.281.08:08:51.56#ibcon#*after write, iclass 13, count 0 2006.281.08:08:51.56#ibcon#*before return 0, iclass 13, count 0 2006.281.08:08:51.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:51.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:08:51.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:08:51.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:08:51.56$vc4f8/vb=1,4 2006.281.08:08:51.56#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:08:51.56#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:08:51.56#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:51.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:51.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:51.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:51.56#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:08:51.56#ibcon#first serial, iclass 15, count 2 2006.281.08:08:51.56#ibcon#enter sib2, iclass 15, count 2 2006.281.08:08:51.56#ibcon#flushed, iclass 15, count 2 2006.281.08:08:51.56#ibcon#about to write, iclass 15, count 2 2006.281.08:08:51.56#ibcon#wrote, iclass 15, count 2 2006.281.08:08:51.56#ibcon#about to read 3, iclass 15, count 2 2006.281.08:08:51.58#ibcon#read 3, iclass 15, count 2 2006.281.08:08:51.58#ibcon#about to read 4, iclass 15, count 2 2006.281.08:08:51.58#ibcon#read 4, iclass 15, count 2 2006.281.08:08:51.58#ibcon#about to read 5, iclass 15, count 2 2006.281.08:08:51.58#ibcon#read 5, iclass 15, count 2 2006.281.08:08:51.58#ibcon#about to read 6, iclass 15, count 2 2006.281.08:08:51.58#ibcon#read 6, iclass 15, count 2 2006.281.08:08:51.58#ibcon#end of sib2, iclass 15, count 2 2006.281.08:08:51.58#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:08:51.58#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:08:51.58#ibcon#[27=AT01-04\r\n] 2006.281.08:08:51.58#ibcon#*before write, iclass 15, count 2 2006.281.08:08:51.58#ibcon#enter sib2, iclass 15, count 2 2006.281.08:08:51.58#ibcon#flushed, iclass 15, count 2 2006.281.08:08:51.58#ibcon#about to write, iclass 15, count 2 2006.281.08:08:51.58#ibcon#wrote, iclass 15, count 2 2006.281.08:08:51.58#ibcon#about to read 3, iclass 15, count 2 2006.281.08:08:51.61#ibcon#read 3, iclass 15, count 2 2006.281.08:08:51.61#ibcon#about to read 4, iclass 15, count 2 2006.281.08:08:51.61#ibcon#read 4, iclass 15, count 2 2006.281.08:08:51.61#ibcon#about to read 5, iclass 15, count 2 2006.281.08:08:51.61#ibcon#read 5, iclass 15, count 2 2006.281.08:08:51.61#ibcon#about to read 6, iclass 15, count 2 2006.281.08:08:51.61#ibcon#read 6, iclass 15, count 2 2006.281.08:08:51.61#ibcon#end of sib2, iclass 15, count 2 2006.281.08:08:51.61#ibcon#*after write, iclass 15, count 2 2006.281.08:08:51.61#ibcon#*before return 0, iclass 15, count 2 2006.281.08:08:51.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:51.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:08:51.61#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:08:51.61#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:51.61#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:51.73#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:51.73#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:51.73#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:08:51.73#ibcon#first serial, iclass 15, count 0 2006.281.08:08:51.73#ibcon#enter sib2, iclass 15, count 0 2006.281.08:08:51.73#ibcon#flushed, iclass 15, count 0 2006.281.08:08:51.73#ibcon#about to write, iclass 15, count 0 2006.281.08:08:51.73#ibcon#wrote, iclass 15, count 0 2006.281.08:08:51.73#ibcon#about to read 3, iclass 15, count 0 2006.281.08:08:51.75#ibcon#read 3, iclass 15, count 0 2006.281.08:08:51.75#ibcon#about to read 4, iclass 15, count 0 2006.281.08:08:51.75#ibcon#read 4, iclass 15, count 0 2006.281.08:08:51.75#ibcon#about to read 5, iclass 15, count 0 2006.281.08:08:51.75#ibcon#read 5, iclass 15, count 0 2006.281.08:08:51.75#ibcon#about to read 6, iclass 15, count 0 2006.281.08:08:51.75#ibcon#read 6, iclass 15, count 0 2006.281.08:08:51.75#ibcon#end of sib2, iclass 15, count 0 2006.281.08:08:51.75#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:08:51.75#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:08:51.75#ibcon#[27=USB\r\n] 2006.281.08:08:51.75#ibcon#*before write, iclass 15, count 0 2006.281.08:08:51.75#ibcon#enter sib2, iclass 15, count 0 2006.281.08:08:51.75#ibcon#flushed, iclass 15, count 0 2006.281.08:08:51.75#ibcon#about to write, iclass 15, count 0 2006.281.08:08:51.75#ibcon#wrote, iclass 15, count 0 2006.281.08:08:51.75#ibcon#about to read 3, iclass 15, count 0 2006.281.08:08:51.78#ibcon#read 3, iclass 15, count 0 2006.281.08:08:51.78#ibcon#about to read 4, iclass 15, count 0 2006.281.08:08:51.78#ibcon#read 4, iclass 15, count 0 2006.281.08:08:51.78#ibcon#about to read 5, iclass 15, count 0 2006.281.08:08:51.78#ibcon#read 5, iclass 15, count 0 2006.281.08:08:51.78#ibcon#about to read 6, iclass 15, count 0 2006.281.08:08:51.78#ibcon#read 6, iclass 15, count 0 2006.281.08:08:51.78#ibcon#end of sib2, iclass 15, count 0 2006.281.08:08:51.78#ibcon#*after write, iclass 15, count 0 2006.281.08:08:51.78#ibcon#*before return 0, iclass 15, count 0 2006.281.08:08:51.78#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:51.78#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:08:51.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:08:51.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:08:51.78$vc4f8/vblo=2,640.99 2006.281.08:08:51.78#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:08:51.78#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:08:51.78#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:51.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:51.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:51.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:51.78#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:08:51.78#ibcon#first serial, iclass 17, count 0 2006.281.08:08:51.78#ibcon#enter sib2, iclass 17, count 0 2006.281.08:08:51.78#ibcon#flushed, iclass 17, count 0 2006.281.08:08:51.78#ibcon#about to write, iclass 17, count 0 2006.281.08:08:51.78#ibcon#wrote, iclass 17, count 0 2006.281.08:08:51.78#ibcon#about to read 3, iclass 17, count 0 2006.281.08:08:51.80#ibcon#read 3, iclass 17, count 0 2006.281.08:08:51.80#ibcon#about to read 4, iclass 17, count 0 2006.281.08:08:51.80#ibcon#read 4, iclass 17, count 0 2006.281.08:08:51.80#ibcon#about to read 5, iclass 17, count 0 2006.281.08:08:51.80#ibcon#read 5, iclass 17, count 0 2006.281.08:08:51.80#ibcon#about to read 6, iclass 17, count 0 2006.281.08:08:51.80#ibcon#read 6, iclass 17, count 0 2006.281.08:08:51.80#ibcon#end of sib2, iclass 17, count 0 2006.281.08:08:51.80#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:08:51.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:08:51.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:08:51.80#ibcon#*before write, iclass 17, count 0 2006.281.08:08:51.80#ibcon#enter sib2, iclass 17, count 0 2006.281.08:08:51.80#ibcon#flushed, iclass 17, count 0 2006.281.08:08:51.80#ibcon#about to write, iclass 17, count 0 2006.281.08:08:51.80#ibcon#wrote, iclass 17, count 0 2006.281.08:08:51.80#ibcon#about to read 3, iclass 17, count 0 2006.281.08:08:51.84#ibcon#read 3, iclass 17, count 0 2006.281.08:08:51.84#ibcon#about to read 4, iclass 17, count 0 2006.281.08:08:51.84#ibcon#read 4, iclass 17, count 0 2006.281.08:08:51.84#ibcon#about to read 5, iclass 17, count 0 2006.281.08:08:51.84#ibcon#read 5, iclass 17, count 0 2006.281.08:08:51.84#ibcon#about to read 6, iclass 17, count 0 2006.281.08:08:51.84#ibcon#read 6, iclass 17, count 0 2006.281.08:08:51.84#ibcon#end of sib2, iclass 17, count 0 2006.281.08:08:51.84#ibcon#*after write, iclass 17, count 0 2006.281.08:08:51.84#ibcon#*before return 0, iclass 17, count 0 2006.281.08:08:51.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:51.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:08:51.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:08:51.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:08:51.84$vc4f8/vb=2,5 2006.281.08:08:51.84#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:08:51.84#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:08:51.84#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:51.84#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:51.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:51.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:51.90#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:08:51.90#ibcon#first serial, iclass 19, count 2 2006.281.08:08:51.90#ibcon#enter sib2, iclass 19, count 2 2006.281.08:08:51.90#ibcon#flushed, iclass 19, count 2 2006.281.08:08:51.90#ibcon#about to write, iclass 19, count 2 2006.281.08:08:51.90#ibcon#wrote, iclass 19, count 2 2006.281.08:08:51.90#ibcon#about to read 3, iclass 19, count 2 2006.281.08:08:51.92#ibcon#read 3, iclass 19, count 2 2006.281.08:08:51.92#ibcon#about to read 4, iclass 19, count 2 2006.281.08:08:51.92#ibcon#read 4, iclass 19, count 2 2006.281.08:08:51.92#ibcon#about to read 5, iclass 19, count 2 2006.281.08:08:51.92#ibcon#read 5, iclass 19, count 2 2006.281.08:08:51.92#ibcon#about to read 6, iclass 19, count 2 2006.281.08:08:51.92#ibcon#read 6, iclass 19, count 2 2006.281.08:08:51.92#ibcon#end of sib2, iclass 19, count 2 2006.281.08:08:51.92#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:08:51.92#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:08:51.92#ibcon#[27=AT02-05\r\n] 2006.281.08:08:51.92#ibcon#*before write, iclass 19, count 2 2006.281.08:08:51.92#ibcon#enter sib2, iclass 19, count 2 2006.281.08:08:51.92#ibcon#flushed, iclass 19, count 2 2006.281.08:08:51.92#ibcon#about to write, iclass 19, count 2 2006.281.08:08:51.92#ibcon#wrote, iclass 19, count 2 2006.281.08:08:51.92#ibcon#about to read 3, iclass 19, count 2 2006.281.08:08:51.95#ibcon#read 3, iclass 19, count 2 2006.281.08:08:51.95#ibcon#about to read 4, iclass 19, count 2 2006.281.08:08:51.95#ibcon#read 4, iclass 19, count 2 2006.281.08:08:51.95#ibcon#about to read 5, iclass 19, count 2 2006.281.08:08:51.95#ibcon#read 5, iclass 19, count 2 2006.281.08:08:51.95#ibcon#about to read 6, iclass 19, count 2 2006.281.08:08:51.95#ibcon#read 6, iclass 19, count 2 2006.281.08:08:51.95#ibcon#end of sib2, iclass 19, count 2 2006.281.08:08:51.95#ibcon#*after write, iclass 19, count 2 2006.281.08:08:51.95#ibcon#*before return 0, iclass 19, count 2 2006.281.08:08:51.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:51.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:08:51.95#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:08:51.95#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:51.95#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:52.07#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:52.07#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:52.07#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:08:52.07#ibcon#first serial, iclass 19, count 0 2006.281.08:08:52.07#ibcon#enter sib2, iclass 19, count 0 2006.281.08:08:52.07#ibcon#flushed, iclass 19, count 0 2006.281.08:08:52.07#ibcon#about to write, iclass 19, count 0 2006.281.08:08:52.07#ibcon#wrote, iclass 19, count 0 2006.281.08:08:52.07#ibcon#about to read 3, iclass 19, count 0 2006.281.08:08:52.09#ibcon#read 3, iclass 19, count 0 2006.281.08:08:52.09#ibcon#about to read 4, iclass 19, count 0 2006.281.08:08:52.09#ibcon#read 4, iclass 19, count 0 2006.281.08:08:52.09#ibcon#about to read 5, iclass 19, count 0 2006.281.08:08:52.09#ibcon#read 5, iclass 19, count 0 2006.281.08:08:52.09#ibcon#about to read 6, iclass 19, count 0 2006.281.08:08:52.09#ibcon#read 6, iclass 19, count 0 2006.281.08:08:52.09#ibcon#end of sib2, iclass 19, count 0 2006.281.08:08:52.09#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:08:52.09#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:08:52.09#ibcon#[27=USB\r\n] 2006.281.08:08:52.09#ibcon#*before write, iclass 19, count 0 2006.281.08:08:52.09#ibcon#enter sib2, iclass 19, count 0 2006.281.08:08:52.09#ibcon#flushed, iclass 19, count 0 2006.281.08:08:52.09#ibcon#about to write, iclass 19, count 0 2006.281.08:08:52.09#ibcon#wrote, iclass 19, count 0 2006.281.08:08:52.09#ibcon#about to read 3, iclass 19, count 0 2006.281.08:08:52.12#ibcon#read 3, iclass 19, count 0 2006.281.08:08:52.12#ibcon#about to read 4, iclass 19, count 0 2006.281.08:08:52.12#ibcon#read 4, iclass 19, count 0 2006.281.08:08:52.12#ibcon#about to read 5, iclass 19, count 0 2006.281.08:08:52.12#ibcon#read 5, iclass 19, count 0 2006.281.08:08:52.12#ibcon#about to read 6, iclass 19, count 0 2006.281.08:08:52.12#ibcon#read 6, iclass 19, count 0 2006.281.08:08:52.12#ibcon#end of sib2, iclass 19, count 0 2006.281.08:08:52.12#ibcon#*after write, iclass 19, count 0 2006.281.08:08:52.12#ibcon#*before return 0, iclass 19, count 0 2006.281.08:08:52.12#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:52.12#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:08:52.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:08:52.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:08:52.12$vc4f8/vblo=3,656.99 2006.281.08:08:52.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:08:52.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:08:52.12#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:52.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:52.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:52.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:52.12#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:08:52.12#ibcon#first serial, iclass 21, count 0 2006.281.08:08:52.12#ibcon#enter sib2, iclass 21, count 0 2006.281.08:08:52.12#ibcon#flushed, iclass 21, count 0 2006.281.08:08:52.12#ibcon#about to write, iclass 21, count 0 2006.281.08:08:52.12#ibcon#wrote, iclass 21, count 0 2006.281.08:08:52.12#ibcon#about to read 3, iclass 21, count 0 2006.281.08:08:52.14#ibcon#read 3, iclass 21, count 0 2006.281.08:08:52.14#ibcon#about to read 4, iclass 21, count 0 2006.281.08:08:52.14#ibcon#read 4, iclass 21, count 0 2006.281.08:08:52.14#ibcon#about to read 5, iclass 21, count 0 2006.281.08:08:52.14#ibcon#read 5, iclass 21, count 0 2006.281.08:08:52.14#ibcon#about to read 6, iclass 21, count 0 2006.281.08:08:52.14#ibcon#read 6, iclass 21, count 0 2006.281.08:08:52.14#ibcon#end of sib2, iclass 21, count 0 2006.281.08:08:52.14#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:08:52.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:08:52.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:08:52.14#ibcon#*before write, iclass 21, count 0 2006.281.08:08:52.14#ibcon#enter sib2, iclass 21, count 0 2006.281.08:08:52.14#ibcon#flushed, iclass 21, count 0 2006.281.08:08:52.14#ibcon#about to write, iclass 21, count 0 2006.281.08:08:52.14#ibcon#wrote, iclass 21, count 0 2006.281.08:08:52.14#ibcon#about to read 3, iclass 21, count 0 2006.281.08:08:52.18#ibcon#read 3, iclass 21, count 0 2006.281.08:08:52.18#ibcon#about to read 4, iclass 21, count 0 2006.281.08:08:52.18#ibcon#read 4, iclass 21, count 0 2006.281.08:08:52.18#ibcon#about to read 5, iclass 21, count 0 2006.281.08:08:52.18#ibcon#read 5, iclass 21, count 0 2006.281.08:08:52.18#ibcon#about to read 6, iclass 21, count 0 2006.281.08:08:52.18#ibcon#read 6, iclass 21, count 0 2006.281.08:08:52.18#ibcon#end of sib2, iclass 21, count 0 2006.281.08:08:52.18#ibcon#*after write, iclass 21, count 0 2006.281.08:08:52.18#ibcon#*before return 0, iclass 21, count 0 2006.281.08:08:52.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:52.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:08:52.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:08:52.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:08:52.18$vc4f8/vb=3,4 2006.281.08:08:52.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:08:52.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:08:52.18#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:52.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:52.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:52.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:52.24#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:08:52.24#ibcon#first serial, iclass 23, count 2 2006.281.08:08:52.24#ibcon#enter sib2, iclass 23, count 2 2006.281.08:08:52.24#ibcon#flushed, iclass 23, count 2 2006.281.08:08:52.24#ibcon#about to write, iclass 23, count 2 2006.281.08:08:52.24#ibcon#wrote, iclass 23, count 2 2006.281.08:08:52.24#ibcon#about to read 3, iclass 23, count 2 2006.281.08:08:52.26#ibcon#read 3, iclass 23, count 2 2006.281.08:08:52.26#ibcon#about to read 4, iclass 23, count 2 2006.281.08:08:52.26#ibcon#read 4, iclass 23, count 2 2006.281.08:08:52.26#ibcon#about to read 5, iclass 23, count 2 2006.281.08:08:52.26#ibcon#read 5, iclass 23, count 2 2006.281.08:08:52.26#ibcon#about to read 6, iclass 23, count 2 2006.281.08:08:52.26#ibcon#read 6, iclass 23, count 2 2006.281.08:08:52.26#ibcon#end of sib2, iclass 23, count 2 2006.281.08:08:52.26#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:08:52.26#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:08:52.26#ibcon#[27=AT03-04\r\n] 2006.281.08:08:52.26#ibcon#*before write, iclass 23, count 2 2006.281.08:08:52.26#ibcon#enter sib2, iclass 23, count 2 2006.281.08:08:52.26#ibcon#flushed, iclass 23, count 2 2006.281.08:08:52.26#ibcon#about to write, iclass 23, count 2 2006.281.08:08:52.26#ibcon#wrote, iclass 23, count 2 2006.281.08:08:52.26#ibcon#about to read 3, iclass 23, count 2 2006.281.08:08:52.29#ibcon#read 3, iclass 23, count 2 2006.281.08:08:52.29#ibcon#about to read 4, iclass 23, count 2 2006.281.08:08:52.29#ibcon#read 4, iclass 23, count 2 2006.281.08:08:52.29#ibcon#about to read 5, iclass 23, count 2 2006.281.08:08:52.29#ibcon#read 5, iclass 23, count 2 2006.281.08:08:52.29#ibcon#about to read 6, iclass 23, count 2 2006.281.08:08:52.29#ibcon#read 6, iclass 23, count 2 2006.281.08:08:52.29#ibcon#end of sib2, iclass 23, count 2 2006.281.08:08:52.29#ibcon#*after write, iclass 23, count 2 2006.281.08:08:52.29#ibcon#*before return 0, iclass 23, count 2 2006.281.08:08:52.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:52.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:08:52.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:08:52.29#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:52.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:52.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:52.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:52.41#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:08:52.41#ibcon#first serial, iclass 23, count 0 2006.281.08:08:52.41#ibcon#enter sib2, iclass 23, count 0 2006.281.08:08:52.41#ibcon#flushed, iclass 23, count 0 2006.281.08:08:52.41#ibcon#about to write, iclass 23, count 0 2006.281.08:08:52.41#ibcon#wrote, iclass 23, count 0 2006.281.08:08:52.41#ibcon#about to read 3, iclass 23, count 0 2006.281.08:08:52.43#ibcon#read 3, iclass 23, count 0 2006.281.08:08:52.43#ibcon#about to read 4, iclass 23, count 0 2006.281.08:08:52.43#ibcon#read 4, iclass 23, count 0 2006.281.08:08:52.43#ibcon#about to read 5, iclass 23, count 0 2006.281.08:08:52.43#ibcon#read 5, iclass 23, count 0 2006.281.08:08:52.43#ibcon#about to read 6, iclass 23, count 0 2006.281.08:08:52.43#ibcon#read 6, iclass 23, count 0 2006.281.08:08:52.43#ibcon#end of sib2, iclass 23, count 0 2006.281.08:08:52.43#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:08:52.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:08:52.43#ibcon#[27=USB\r\n] 2006.281.08:08:52.43#ibcon#*before write, iclass 23, count 0 2006.281.08:08:52.43#ibcon#enter sib2, iclass 23, count 0 2006.281.08:08:52.43#ibcon#flushed, iclass 23, count 0 2006.281.08:08:52.43#ibcon#about to write, iclass 23, count 0 2006.281.08:08:52.43#ibcon#wrote, iclass 23, count 0 2006.281.08:08:52.43#ibcon#about to read 3, iclass 23, count 0 2006.281.08:08:52.46#ibcon#read 3, iclass 23, count 0 2006.281.08:08:52.46#ibcon#about to read 4, iclass 23, count 0 2006.281.08:08:52.46#ibcon#read 4, iclass 23, count 0 2006.281.08:08:52.46#ibcon#about to read 5, iclass 23, count 0 2006.281.08:08:52.46#ibcon#read 5, iclass 23, count 0 2006.281.08:08:52.46#ibcon#about to read 6, iclass 23, count 0 2006.281.08:08:52.46#ibcon#read 6, iclass 23, count 0 2006.281.08:08:52.46#ibcon#end of sib2, iclass 23, count 0 2006.281.08:08:52.46#ibcon#*after write, iclass 23, count 0 2006.281.08:08:52.46#ibcon#*before return 0, iclass 23, count 0 2006.281.08:08:52.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:52.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:08:52.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:08:52.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:08:52.46$vc4f8/vblo=4,712.99 2006.281.08:08:52.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:08:52.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:08:52.46#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:52.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:52.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:52.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:52.46#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:08:52.46#ibcon#first serial, iclass 25, count 0 2006.281.08:08:52.46#ibcon#enter sib2, iclass 25, count 0 2006.281.08:08:52.46#ibcon#flushed, iclass 25, count 0 2006.281.08:08:52.46#ibcon#about to write, iclass 25, count 0 2006.281.08:08:52.46#ibcon#wrote, iclass 25, count 0 2006.281.08:08:52.46#ibcon#about to read 3, iclass 25, count 0 2006.281.08:08:52.48#ibcon#read 3, iclass 25, count 0 2006.281.08:08:52.48#ibcon#about to read 4, iclass 25, count 0 2006.281.08:08:52.48#ibcon#read 4, iclass 25, count 0 2006.281.08:08:52.48#ibcon#about to read 5, iclass 25, count 0 2006.281.08:08:52.48#ibcon#read 5, iclass 25, count 0 2006.281.08:08:52.48#ibcon#about to read 6, iclass 25, count 0 2006.281.08:08:52.48#ibcon#read 6, iclass 25, count 0 2006.281.08:08:52.48#ibcon#end of sib2, iclass 25, count 0 2006.281.08:08:52.48#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:08:52.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:08:52.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:08:52.48#ibcon#*before write, iclass 25, count 0 2006.281.08:08:52.48#ibcon#enter sib2, iclass 25, count 0 2006.281.08:08:52.48#ibcon#flushed, iclass 25, count 0 2006.281.08:08:52.48#ibcon#about to write, iclass 25, count 0 2006.281.08:08:52.48#ibcon#wrote, iclass 25, count 0 2006.281.08:08:52.48#ibcon#about to read 3, iclass 25, count 0 2006.281.08:08:52.52#ibcon#read 3, iclass 25, count 0 2006.281.08:08:52.52#ibcon#about to read 4, iclass 25, count 0 2006.281.08:08:52.52#ibcon#read 4, iclass 25, count 0 2006.281.08:08:52.52#ibcon#about to read 5, iclass 25, count 0 2006.281.08:08:52.52#ibcon#read 5, iclass 25, count 0 2006.281.08:08:52.52#ibcon#about to read 6, iclass 25, count 0 2006.281.08:08:52.52#ibcon#read 6, iclass 25, count 0 2006.281.08:08:52.52#ibcon#end of sib2, iclass 25, count 0 2006.281.08:08:52.52#ibcon#*after write, iclass 25, count 0 2006.281.08:08:52.52#ibcon#*before return 0, iclass 25, count 0 2006.281.08:08:52.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:52.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:08:52.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:08:52.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:08:52.52$vc4f8/vb=4,4 2006.281.08:08:52.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:08:52.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:08:52.52#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:52.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:52.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:52.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:52.58#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:08:52.58#ibcon#first serial, iclass 27, count 2 2006.281.08:08:52.58#ibcon#enter sib2, iclass 27, count 2 2006.281.08:08:52.58#ibcon#flushed, iclass 27, count 2 2006.281.08:08:52.58#ibcon#about to write, iclass 27, count 2 2006.281.08:08:52.58#ibcon#wrote, iclass 27, count 2 2006.281.08:08:52.58#ibcon#about to read 3, iclass 27, count 2 2006.281.08:08:52.60#ibcon#read 3, iclass 27, count 2 2006.281.08:08:52.60#ibcon#about to read 4, iclass 27, count 2 2006.281.08:08:52.60#ibcon#read 4, iclass 27, count 2 2006.281.08:08:52.60#ibcon#about to read 5, iclass 27, count 2 2006.281.08:08:52.60#ibcon#read 5, iclass 27, count 2 2006.281.08:08:52.60#ibcon#about to read 6, iclass 27, count 2 2006.281.08:08:52.60#ibcon#read 6, iclass 27, count 2 2006.281.08:08:52.60#ibcon#end of sib2, iclass 27, count 2 2006.281.08:08:52.60#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:08:52.60#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:08:52.60#ibcon#[27=AT04-04\r\n] 2006.281.08:08:52.60#ibcon#*before write, iclass 27, count 2 2006.281.08:08:52.60#ibcon#enter sib2, iclass 27, count 2 2006.281.08:08:52.60#ibcon#flushed, iclass 27, count 2 2006.281.08:08:52.60#ibcon#about to write, iclass 27, count 2 2006.281.08:08:52.60#ibcon#wrote, iclass 27, count 2 2006.281.08:08:52.60#ibcon#about to read 3, iclass 27, count 2 2006.281.08:08:52.63#ibcon#read 3, iclass 27, count 2 2006.281.08:08:52.63#ibcon#about to read 4, iclass 27, count 2 2006.281.08:08:52.63#ibcon#read 4, iclass 27, count 2 2006.281.08:08:52.63#ibcon#about to read 5, iclass 27, count 2 2006.281.08:08:52.63#ibcon#read 5, iclass 27, count 2 2006.281.08:08:52.63#ibcon#about to read 6, iclass 27, count 2 2006.281.08:08:52.63#ibcon#read 6, iclass 27, count 2 2006.281.08:08:52.63#ibcon#end of sib2, iclass 27, count 2 2006.281.08:08:52.63#ibcon#*after write, iclass 27, count 2 2006.281.08:08:52.63#ibcon#*before return 0, iclass 27, count 2 2006.281.08:08:52.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:52.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:08:52.63#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:08:52.63#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:52.63#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:52.75#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:52.75#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:52.75#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:08:52.75#ibcon#first serial, iclass 27, count 0 2006.281.08:08:52.75#ibcon#enter sib2, iclass 27, count 0 2006.281.08:08:52.75#ibcon#flushed, iclass 27, count 0 2006.281.08:08:52.75#ibcon#about to write, iclass 27, count 0 2006.281.08:08:52.75#ibcon#wrote, iclass 27, count 0 2006.281.08:08:52.75#ibcon#about to read 3, iclass 27, count 0 2006.281.08:08:52.77#ibcon#read 3, iclass 27, count 0 2006.281.08:08:52.77#ibcon#about to read 4, iclass 27, count 0 2006.281.08:08:52.77#ibcon#read 4, iclass 27, count 0 2006.281.08:08:52.77#ibcon#about to read 5, iclass 27, count 0 2006.281.08:08:52.77#ibcon#read 5, iclass 27, count 0 2006.281.08:08:52.77#ibcon#about to read 6, iclass 27, count 0 2006.281.08:08:52.77#ibcon#read 6, iclass 27, count 0 2006.281.08:08:52.77#ibcon#end of sib2, iclass 27, count 0 2006.281.08:08:52.77#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:08:52.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:08:52.77#ibcon#[27=USB\r\n] 2006.281.08:08:52.77#ibcon#*before write, iclass 27, count 0 2006.281.08:08:52.77#ibcon#enter sib2, iclass 27, count 0 2006.281.08:08:52.77#ibcon#flushed, iclass 27, count 0 2006.281.08:08:52.77#ibcon#about to write, iclass 27, count 0 2006.281.08:08:52.77#ibcon#wrote, iclass 27, count 0 2006.281.08:08:52.77#ibcon#about to read 3, iclass 27, count 0 2006.281.08:08:52.80#ibcon#read 3, iclass 27, count 0 2006.281.08:08:52.80#ibcon#about to read 4, iclass 27, count 0 2006.281.08:08:52.80#ibcon#read 4, iclass 27, count 0 2006.281.08:08:52.80#ibcon#about to read 5, iclass 27, count 0 2006.281.08:08:52.80#ibcon#read 5, iclass 27, count 0 2006.281.08:08:52.80#ibcon#about to read 6, iclass 27, count 0 2006.281.08:08:52.80#ibcon#read 6, iclass 27, count 0 2006.281.08:08:52.80#ibcon#end of sib2, iclass 27, count 0 2006.281.08:08:52.80#ibcon#*after write, iclass 27, count 0 2006.281.08:08:52.80#ibcon#*before return 0, iclass 27, count 0 2006.281.08:08:52.80#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:52.80#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:08:52.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:08:52.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:08:52.80$vc4f8/vblo=5,744.99 2006.281.08:08:52.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:08:52.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:08:52.80#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:52.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:52.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:52.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:52.80#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:08:52.80#ibcon#first serial, iclass 29, count 0 2006.281.08:08:52.80#ibcon#enter sib2, iclass 29, count 0 2006.281.08:08:52.80#ibcon#flushed, iclass 29, count 0 2006.281.08:08:52.80#ibcon#about to write, iclass 29, count 0 2006.281.08:08:52.80#ibcon#wrote, iclass 29, count 0 2006.281.08:08:52.80#ibcon#about to read 3, iclass 29, count 0 2006.281.08:08:52.82#ibcon#read 3, iclass 29, count 0 2006.281.08:08:52.82#ibcon#about to read 4, iclass 29, count 0 2006.281.08:08:52.82#ibcon#read 4, iclass 29, count 0 2006.281.08:08:52.82#ibcon#about to read 5, iclass 29, count 0 2006.281.08:08:52.82#ibcon#read 5, iclass 29, count 0 2006.281.08:08:52.82#ibcon#about to read 6, iclass 29, count 0 2006.281.08:08:52.82#ibcon#read 6, iclass 29, count 0 2006.281.08:08:52.82#ibcon#end of sib2, iclass 29, count 0 2006.281.08:08:52.82#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:08:52.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:08:52.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:08:52.82#ibcon#*before write, iclass 29, count 0 2006.281.08:08:52.82#ibcon#enter sib2, iclass 29, count 0 2006.281.08:08:52.82#ibcon#flushed, iclass 29, count 0 2006.281.08:08:52.82#ibcon#about to write, iclass 29, count 0 2006.281.08:08:52.82#ibcon#wrote, iclass 29, count 0 2006.281.08:08:52.82#ibcon#about to read 3, iclass 29, count 0 2006.281.08:08:52.87#ibcon#read 3, iclass 29, count 0 2006.281.08:08:52.87#ibcon#about to read 4, iclass 29, count 0 2006.281.08:08:52.87#ibcon#read 4, iclass 29, count 0 2006.281.08:08:52.87#ibcon#about to read 5, iclass 29, count 0 2006.281.08:08:52.87#ibcon#read 5, iclass 29, count 0 2006.281.08:08:52.87#ibcon#about to read 6, iclass 29, count 0 2006.281.08:08:52.87#ibcon#read 6, iclass 29, count 0 2006.281.08:08:52.87#ibcon#end of sib2, iclass 29, count 0 2006.281.08:08:52.87#ibcon#*after write, iclass 29, count 0 2006.281.08:08:52.87#ibcon#*before return 0, iclass 29, count 0 2006.281.08:08:52.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:52.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:08:52.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:08:52.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:08:52.87$vc4f8/vb=5,4 2006.281.08:08:52.87#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:08:52.87#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:08:52.87#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:52.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:52.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:52.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:52.92#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:08:52.92#ibcon#first serial, iclass 31, count 2 2006.281.08:08:52.92#ibcon#enter sib2, iclass 31, count 2 2006.281.08:08:52.92#ibcon#flushed, iclass 31, count 2 2006.281.08:08:52.92#ibcon#about to write, iclass 31, count 2 2006.281.08:08:52.92#ibcon#wrote, iclass 31, count 2 2006.281.08:08:52.92#ibcon#about to read 3, iclass 31, count 2 2006.281.08:08:52.94#ibcon#read 3, iclass 31, count 2 2006.281.08:08:52.94#ibcon#about to read 4, iclass 31, count 2 2006.281.08:08:52.94#ibcon#read 4, iclass 31, count 2 2006.281.08:08:52.94#ibcon#about to read 5, iclass 31, count 2 2006.281.08:08:52.94#ibcon#read 5, iclass 31, count 2 2006.281.08:08:52.94#ibcon#about to read 6, iclass 31, count 2 2006.281.08:08:52.94#ibcon#read 6, iclass 31, count 2 2006.281.08:08:52.94#ibcon#end of sib2, iclass 31, count 2 2006.281.08:08:52.94#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:08:52.94#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:08:52.94#ibcon#[27=AT05-04\r\n] 2006.281.08:08:52.94#ibcon#*before write, iclass 31, count 2 2006.281.08:08:52.94#ibcon#enter sib2, iclass 31, count 2 2006.281.08:08:52.94#ibcon#flushed, iclass 31, count 2 2006.281.08:08:52.94#ibcon#about to write, iclass 31, count 2 2006.281.08:08:52.94#ibcon#wrote, iclass 31, count 2 2006.281.08:08:52.94#ibcon#about to read 3, iclass 31, count 2 2006.281.08:08:52.97#ibcon#read 3, iclass 31, count 2 2006.281.08:08:52.97#ibcon#about to read 4, iclass 31, count 2 2006.281.08:08:52.97#ibcon#read 4, iclass 31, count 2 2006.281.08:08:52.97#ibcon#about to read 5, iclass 31, count 2 2006.281.08:08:52.97#ibcon#read 5, iclass 31, count 2 2006.281.08:08:52.97#ibcon#about to read 6, iclass 31, count 2 2006.281.08:08:52.97#ibcon#read 6, iclass 31, count 2 2006.281.08:08:52.97#ibcon#end of sib2, iclass 31, count 2 2006.281.08:08:52.97#ibcon#*after write, iclass 31, count 2 2006.281.08:08:52.97#ibcon#*before return 0, iclass 31, count 2 2006.281.08:08:52.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:52.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:08:52.97#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:08:52.97#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:52.97#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:53.09#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:53.09#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:53.09#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:08:53.09#ibcon#first serial, iclass 31, count 0 2006.281.08:08:53.09#ibcon#enter sib2, iclass 31, count 0 2006.281.08:08:53.09#ibcon#flushed, iclass 31, count 0 2006.281.08:08:53.09#ibcon#about to write, iclass 31, count 0 2006.281.08:08:53.09#ibcon#wrote, iclass 31, count 0 2006.281.08:08:53.09#ibcon#about to read 3, iclass 31, count 0 2006.281.08:08:53.11#ibcon#read 3, iclass 31, count 0 2006.281.08:08:53.11#ibcon#about to read 4, iclass 31, count 0 2006.281.08:08:53.11#ibcon#read 4, iclass 31, count 0 2006.281.08:08:53.11#ibcon#about to read 5, iclass 31, count 0 2006.281.08:08:53.11#ibcon#read 5, iclass 31, count 0 2006.281.08:08:53.11#ibcon#about to read 6, iclass 31, count 0 2006.281.08:08:53.11#ibcon#read 6, iclass 31, count 0 2006.281.08:08:53.11#ibcon#end of sib2, iclass 31, count 0 2006.281.08:08:53.11#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:08:53.11#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:08:53.11#ibcon#[27=USB\r\n] 2006.281.08:08:53.11#ibcon#*before write, iclass 31, count 0 2006.281.08:08:53.11#ibcon#enter sib2, iclass 31, count 0 2006.281.08:08:53.11#ibcon#flushed, iclass 31, count 0 2006.281.08:08:53.11#ibcon#about to write, iclass 31, count 0 2006.281.08:08:53.11#ibcon#wrote, iclass 31, count 0 2006.281.08:08:53.11#ibcon#about to read 3, iclass 31, count 0 2006.281.08:08:53.14#ibcon#read 3, iclass 31, count 0 2006.281.08:08:53.14#ibcon#about to read 4, iclass 31, count 0 2006.281.08:08:53.14#ibcon#read 4, iclass 31, count 0 2006.281.08:08:53.14#ibcon#about to read 5, iclass 31, count 0 2006.281.08:08:53.14#ibcon#read 5, iclass 31, count 0 2006.281.08:08:53.14#ibcon#about to read 6, iclass 31, count 0 2006.281.08:08:53.14#ibcon#read 6, iclass 31, count 0 2006.281.08:08:53.14#ibcon#end of sib2, iclass 31, count 0 2006.281.08:08:53.14#ibcon#*after write, iclass 31, count 0 2006.281.08:08:53.14#ibcon#*before return 0, iclass 31, count 0 2006.281.08:08:53.14#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:53.14#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:08:53.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:08:53.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:08:53.14$vc4f8/vblo=6,752.99 2006.281.08:08:53.14#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:08:53.14#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:08:53.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:08:53.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:53.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:53.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:53.14#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:08:53.14#ibcon#first serial, iclass 33, count 0 2006.281.08:08:53.14#ibcon#enter sib2, iclass 33, count 0 2006.281.08:08:53.14#ibcon#flushed, iclass 33, count 0 2006.281.08:08:53.14#ibcon#about to write, iclass 33, count 0 2006.281.08:08:53.14#ibcon#wrote, iclass 33, count 0 2006.281.08:08:53.14#ibcon#about to read 3, iclass 33, count 0 2006.281.08:08:53.16#ibcon#read 3, iclass 33, count 0 2006.281.08:08:53.16#ibcon#about to read 4, iclass 33, count 0 2006.281.08:08:53.16#ibcon#read 4, iclass 33, count 0 2006.281.08:08:53.16#ibcon#about to read 5, iclass 33, count 0 2006.281.08:08:53.16#ibcon#read 5, iclass 33, count 0 2006.281.08:08:53.16#ibcon#about to read 6, iclass 33, count 0 2006.281.08:08:53.16#ibcon#read 6, iclass 33, count 0 2006.281.08:08:53.16#ibcon#end of sib2, iclass 33, count 0 2006.281.08:08:53.16#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:08:53.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:08:53.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:08:53.16#ibcon#*before write, iclass 33, count 0 2006.281.08:08:53.16#ibcon#enter sib2, iclass 33, count 0 2006.281.08:08:53.16#ibcon#flushed, iclass 33, count 0 2006.281.08:08:53.16#ibcon#about to write, iclass 33, count 0 2006.281.08:08:53.16#ibcon#wrote, iclass 33, count 0 2006.281.08:08:53.16#ibcon#about to read 3, iclass 33, count 0 2006.281.08:08:53.20#ibcon#read 3, iclass 33, count 0 2006.281.08:08:53.20#ibcon#about to read 4, iclass 33, count 0 2006.281.08:08:53.20#ibcon#read 4, iclass 33, count 0 2006.281.08:08:53.20#ibcon#about to read 5, iclass 33, count 0 2006.281.08:08:53.20#ibcon#read 5, iclass 33, count 0 2006.281.08:08:53.20#ibcon#about to read 6, iclass 33, count 0 2006.281.08:08:53.20#ibcon#read 6, iclass 33, count 0 2006.281.08:08:53.20#ibcon#end of sib2, iclass 33, count 0 2006.281.08:08:53.20#ibcon#*after write, iclass 33, count 0 2006.281.08:08:53.20#ibcon#*before return 0, iclass 33, count 0 2006.281.08:08:53.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:53.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:08:53.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:08:53.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:08:53.20$vc4f8/vb=6,4 2006.281.08:08:53.21#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:08:53.21#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:08:53.21#ibcon#ireg 11 cls_cnt 2 2006.281.08:08:53.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:53.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:53.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:53.26#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:08:53.26#ibcon#first serial, iclass 35, count 2 2006.281.08:08:53.26#ibcon#enter sib2, iclass 35, count 2 2006.281.08:08:53.26#ibcon#flushed, iclass 35, count 2 2006.281.08:08:53.26#ibcon#about to write, iclass 35, count 2 2006.281.08:08:53.26#ibcon#wrote, iclass 35, count 2 2006.281.08:08:53.26#ibcon#about to read 3, iclass 35, count 2 2006.281.08:08:53.28#ibcon#read 3, iclass 35, count 2 2006.281.08:08:53.28#ibcon#about to read 4, iclass 35, count 2 2006.281.08:08:53.28#ibcon#read 4, iclass 35, count 2 2006.281.08:08:53.28#ibcon#about to read 5, iclass 35, count 2 2006.281.08:08:53.28#ibcon#read 5, iclass 35, count 2 2006.281.08:08:53.28#ibcon#about to read 6, iclass 35, count 2 2006.281.08:08:53.28#ibcon#read 6, iclass 35, count 2 2006.281.08:08:53.28#ibcon#end of sib2, iclass 35, count 2 2006.281.08:08:53.28#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:08:53.28#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:08:53.28#ibcon#[27=AT06-04\r\n] 2006.281.08:08:53.28#ibcon#*before write, iclass 35, count 2 2006.281.08:08:53.28#ibcon#enter sib2, iclass 35, count 2 2006.281.08:08:53.28#ibcon#flushed, iclass 35, count 2 2006.281.08:08:53.28#ibcon#about to write, iclass 35, count 2 2006.281.08:08:53.28#ibcon#wrote, iclass 35, count 2 2006.281.08:08:53.28#ibcon#about to read 3, iclass 35, count 2 2006.281.08:08:53.31#ibcon#read 3, iclass 35, count 2 2006.281.08:08:53.31#ibcon#about to read 4, iclass 35, count 2 2006.281.08:08:53.31#ibcon#read 4, iclass 35, count 2 2006.281.08:08:53.31#ibcon#about to read 5, iclass 35, count 2 2006.281.08:08:53.31#ibcon#read 5, iclass 35, count 2 2006.281.08:08:53.31#ibcon#about to read 6, iclass 35, count 2 2006.281.08:08:53.31#ibcon#read 6, iclass 35, count 2 2006.281.08:08:53.31#ibcon#end of sib2, iclass 35, count 2 2006.281.08:08:53.31#ibcon#*after write, iclass 35, count 2 2006.281.08:08:53.31#ibcon#*before return 0, iclass 35, count 2 2006.281.08:08:53.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:53.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:08:53.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:08:53.31#ibcon#ireg 7 cls_cnt 0 2006.281.08:08:53.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:53.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:53.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:53.43#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:08:53.43#ibcon#first serial, iclass 35, count 0 2006.281.08:08:53.43#ibcon#enter sib2, iclass 35, count 0 2006.281.08:08:53.43#ibcon#flushed, iclass 35, count 0 2006.281.08:08:53.43#ibcon#about to write, iclass 35, count 0 2006.281.08:08:53.43#ibcon#wrote, iclass 35, count 0 2006.281.08:08:53.43#ibcon#about to read 3, iclass 35, count 0 2006.281.08:08:53.45#ibcon#read 3, iclass 35, count 0 2006.281.08:08:53.45#ibcon#about to read 4, iclass 35, count 0 2006.281.08:08:53.45#ibcon#read 4, iclass 35, count 0 2006.281.08:08:53.45#ibcon#about to read 5, iclass 35, count 0 2006.281.08:08:53.45#ibcon#read 5, iclass 35, count 0 2006.281.08:08:53.45#ibcon#about to read 6, iclass 35, count 0 2006.281.08:08:53.45#ibcon#read 6, iclass 35, count 0 2006.281.08:08:53.45#ibcon#end of sib2, iclass 35, count 0 2006.281.08:08:53.45#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:08:53.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:08:53.45#ibcon#[27=USB\r\n] 2006.281.08:08:53.45#ibcon#*before write, iclass 35, count 0 2006.281.08:08:53.45#ibcon#enter sib2, iclass 35, count 0 2006.281.08:08:53.45#ibcon#flushed, iclass 35, count 0 2006.281.08:08:53.45#ibcon#about to write, iclass 35, count 0 2006.281.08:08:53.45#ibcon#wrote, iclass 35, count 0 2006.281.08:08:53.45#ibcon#about to read 3, iclass 35, count 0 2006.281.08:08:53.48#ibcon#read 3, iclass 35, count 0 2006.281.08:08:53.48#ibcon#about to read 4, iclass 35, count 0 2006.281.08:08:53.48#ibcon#read 4, iclass 35, count 0 2006.281.08:08:53.48#ibcon#about to read 5, iclass 35, count 0 2006.281.08:08:53.48#ibcon#read 5, iclass 35, count 0 2006.281.08:08:53.48#ibcon#about to read 6, iclass 35, count 0 2006.281.08:08:53.48#ibcon#read 6, iclass 35, count 0 2006.281.08:08:53.48#ibcon#end of sib2, iclass 35, count 0 2006.281.08:08:53.48#ibcon#*after write, iclass 35, count 0 2006.281.08:08:53.48#ibcon#*before return 0, iclass 35, count 0 2006.281.08:08:53.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:53.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:08:53.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:08:53.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:08:53.48$vc4f8/vabw=wide 2006.281.08:08:53.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:08:53.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:08:53.48#ibcon#ireg 8 cls_cnt 0 2006.281.08:08:53.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:08:53.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:08:53.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:08:53.48#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:08:53.48#ibcon#first serial, iclass 37, count 0 2006.281.08:08:53.48#ibcon#enter sib2, iclass 37, count 0 2006.281.08:08:53.48#ibcon#flushed, iclass 37, count 0 2006.281.08:08:53.48#ibcon#about to write, iclass 37, count 0 2006.281.08:08:53.48#ibcon#wrote, iclass 37, count 0 2006.281.08:08:53.48#ibcon#about to read 3, iclass 37, count 0 2006.281.08:08:53.50#ibcon#read 3, iclass 37, count 0 2006.281.08:08:53.50#ibcon#about to read 4, iclass 37, count 0 2006.281.08:08:53.50#ibcon#read 4, iclass 37, count 0 2006.281.08:08:53.50#ibcon#about to read 5, iclass 37, count 0 2006.281.08:08:53.50#ibcon#read 5, iclass 37, count 0 2006.281.08:08:53.50#ibcon#about to read 6, iclass 37, count 0 2006.281.08:08:53.50#ibcon#read 6, iclass 37, count 0 2006.281.08:08:53.50#ibcon#end of sib2, iclass 37, count 0 2006.281.08:08:53.50#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:08:53.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:08:53.50#ibcon#[25=BW32\r\n] 2006.281.08:08:53.50#ibcon#*before write, iclass 37, count 0 2006.281.08:08:53.50#ibcon#enter sib2, iclass 37, count 0 2006.281.08:08:53.50#ibcon#flushed, iclass 37, count 0 2006.281.08:08:53.50#ibcon#about to write, iclass 37, count 0 2006.281.08:08:53.50#ibcon#wrote, iclass 37, count 0 2006.281.08:08:53.50#ibcon#about to read 3, iclass 37, count 0 2006.281.08:08:53.54#ibcon#read 3, iclass 37, count 0 2006.281.08:08:53.54#ibcon#about to read 4, iclass 37, count 0 2006.281.08:08:53.54#ibcon#read 4, iclass 37, count 0 2006.281.08:08:53.54#ibcon#about to read 5, iclass 37, count 0 2006.281.08:08:53.54#ibcon#read 5, iclass 37, count 0 2006.281.08:08:53.54#ibcon#about to read 6, iclass 37, count 0 2006.281.08:08:53.54#ibcon#read 6, iclass 37, count 0 2006.281.08:08:53.54#ibcon#end of sib2, iclass 37, count 0 2006.281.08:08:53.54#ibcon#*after write, iclass 37, count 0 2006.281.08:08:53.54#ibcon#*before return 0, iclass 37, count 0 2006.281.08:08:53.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:08:53.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:08:53.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:08:53.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:08:53.54$vc4f8/vbbw=wide 2006.281.08:08:53.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:08:53.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:08:53.54#ibcon#ireg 8 cls_cnt 0 2006.281.08:08:53.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:08:53.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:08:53.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:08:53.60#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:08:53.60#ibcon#first serial, iclass 39, count 0 2006.281.08:08:53.60#ibcon#enter sib2, iclass 39, count 0 2006.281.08:08:53.60#ibcon#flushed, iclass 39, count 0 2006.281.08:08:53.60#ibcon#about to write, iclass 39, count 0 2006.281.08:08:53.60#ibcon#wrote, iclass 39, count 0 2006.281.08:08:53.60#ibcon#about to read 3, iclass 39, count 0 2006.281.08:08:53.62#ibcon#read 3, iclass 39, count 0 2006.281.08:08:53.62#ibcon#about to read 4, iclass 39, count 0 2006.281.08:08:53.62#ibcon#read 4, iclass 39, count 0 2006.281.08:08:53.62#ibcon#about to read 5, iclass 39, count 0 2006.281.08:08:53.62#ibcon#read 5, iclass 39, count 0 2006.281.08:08:53.62#ibcon#about to read 6, iclass 39, count 0 2006.281.08:08:53.62#ibcon#read 6, iclass 39, count 0 2006.281.08:08:53.62#ibcon#end of sib2, iclass 39, count 0 2006.281.08:08:53.62#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:08:53.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:08:53.62#ibcon#[27=BW32\r\n] 2006.281.08:08:53.62#ibcon#*before write, iclass 39, count 0 2006.281.08:08:53.62#ibcon#enter sib2, iclass 39, count 0 2006.281.08:08:53.62#ibcon#flushed, iclass 39, count 0 2006.281.08:08:53.62#ibcon#about to write, iclass 39, count 0 2006.281.08:08:53.62#ibcon#wrote, iclass 39, count 0 2006.281.08:08:53.62#ibcon#about to read 3, iclass 39, count 0 2006.281.08:08:53.65#ibcon#read 3, iclass 39, count 0 2006.281.08:08:53.65#ibcon#about to read 4, iclass 39, count 0 2006.281.08:08:53.65#ibcon#read 4, iclass 39, count 0 2006.281.08:08:53.65#ibcon#about to read 5, iclass 39, count 0 2006.281.08:08:53.65#ibcon#read 5, iclass 39, count 0 2006.281.08:08:53.65#ibcon#about to read 6, iclass 39, count 0 2006.281.08:08:53.65#ibcon#read 6, iclass 39, count 0 2006.281.08:08:53.65#ibcon#end of sib2, iclass 39, count 0 2006.281.08:08:53.65#ibcon#*after write, iclass 39, count 0 2006.281.08:08:53.65#ibcon#*before return 0, iclass 39, count 0 2006.281.08:08:53.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:08:53.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:08:53.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:08:53.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:08:53.65$4f8m12a/ifd4f 2006.281.08:08:53.65$ifd4f/lo= 2006.281.08:08:53.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:08:53.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:08:53.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:08:53.65$ifd4f/patch= 2006.281.08:08:53.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:08:53.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:08:53.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:08:53.65$4f8m12a/"form=m,16.000,1:2 2006.281.08:08:53.65$4f8m12a/"tpicd 2006.281.08:08:53.65$4f8m12a/echo=off 2006.281.08:08:53.65$4f8m12a/xlog=off 2006.281.08:08:53.65:!2006.281.08:09:20 2006.281.08:08:57.14#trakl#Source acquired 2006.281.08:08:59.14#flagr#flagr/antenna,acquired 2006.281.08:09:14.14#trakl#Off source 2006.281.08:09:14.14?ERROR st -7 Antenna off-source! 2006.281.08:09:14.14#trakl#az 357.386 el 25.496 azerr*cos(el) 0.0196 elerr -0.0113 2006.281.08:09:14.14#flagr#flagr/antenna,off-source 2006.281.08:09:20.02:preob 2006.281.08:09:21.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:09:21.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:09:21.14/onsource/SLEWING 2006.281.08:09:21.14:!2006.281.08:09:30 2006.281.08:09:28.13#trakl#Source re-acquired 2006.281.08:09:28.14#flagr#flagr/antenna,re-acquired 2006.281.08:09:30.02:data_valid=on 2006.281.08:09:30.02:midob 2006.281.08:09:31.14/onsource/TRACKING 2006.281.08:09:31.14/wx/20.24,1001.7,52 2006.281.08:09:31.28/cable/+6.4872E-03 2006.281.08:09:32.37/va/01,07,usb,yes,33,35 2006.281.08:09:32.37/va/02,06,usb,yes,31,32 2006.281.08:09:32.37/va/03,06,usb,yes,29,29 2006.281.08:09:32.37/va/04,06,usb,yes,32,34 2006.281.08:09:32.37/va/05,07,usb,yes,30,32 2006.281.08:09:32.37/va/06,06,usb,yes,30,29 2006.281.08:09:32.37/va/07,06,usb,yes,30,30 2006.281.08:09:32.37/va/08,06,usb,yes,32,31 2006.281.08:09:32.60/valo/01,532.99,yes,locked 2006.281.08:09:32.60/valo/02,572.99,yes,locked 2006.281.08:09:32.60/valo/03,672.99,yes,locked 2006.281.08:09:32.60/valo/04,832.99,yes,locked 2006.281.08:09:32.60/valo/05,652.99,yes,locked 2006.281.08:09:32.60/valo/06,772.99,yes,locked 2006.281.08:09:32.60/valo/07,832.99,yes,locked 2006.281.08:09:32.60/valo/08,852.99,yes,locked 2006.281.08:09:33.69/vb/01,04,usb,yes,30,29 2006.281.08:09:33.69/vb/02,05,usb,yes,28,29 2006.281.08:09:33.69/vb/03,04,usb,yes,29,32 2006.281.08:09:33.69/vb/04,04,usb,yes,29,30 2006.281.08:09:33.69/vb/05,04,usb,yes,27,32 2006.281.08:09:33.69/vb/06,04,usb,yes,28,31 2006.281.08:09:33.69/vb/07,04,usb,yes,31,31 2006.281.08:09:33.69/vb/08,04,usb,yes,28,32 2006.281.08:09:33.92/vblo/01,632.99,yes,locked 2006.281.08:09:33.92/vblo/02,640.99,yes,locked 2006.281.08:09:33.92/vblo/03,656.99,yes,locked 2006.281.08:09:33.92/vblo/04,712.99,yes,locked 2006.281.08:09:33.92/vblo/05,744.99,yes,locked 2006.281.08:09:33.92/vblo/06,752.99,yes,locked 2006.281.08:09:33.92/vblo/07,734.99,yes,locked 2006.281.08:09:33.92/vblo/08,744.99,yes,locked 2006.281.08:09:34.07/vabw/8 2006.281.08:09:34.22/vbbw/8 2006.281.08:09:34.31/xfe/off,on,12.0 2006.281.08:09:34.71/ifatt/23,28,28,28 2006.281.08:09:35.08/fmout-gps/S +3.16E-07 2006.281.08:09:35.09:!2006.281.08:10:30 2006.281.08:09:50.14#trakl#Off source 2006.281.08:09:50.14?ERROR st -7 Antenna off-source! 2006.281.08:09:50.14#trakl#az 357.417 el 25.491 azerr*cos(el) 0.0216 elerr -0.0038 2006.281.08:09:51.15#flagr#flagr/antenna,off-source 2006.281.08:09:56.14#trakl#Source re-acquired 2006.281.08:09:57.15#flagr#flagr/antenna,re-acquired 2006.281.08:10:30.02:data_valid=off 2006.281.08:10:30.02:postob 2006.281.08:10:30.15/cable/+6.4878E-03 2006.281.08:10:30.16/wx/20.21,1001.6,52 2006.281.08:10:31.07/fmout-gps/S +3.14E-07 2006.281.08:10:31.08:scan_name=281-0811,k06281,60 2006.281.08:10:31.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.281.08:10:32.15#flagr#flagr/antenna,new-source 2006.281.08:10:32.15:checkk5 2006.281.08:10:32.56/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:10:32.99/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:10:33.42/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:10:33.85/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:10:34.29/chk_obsdata//k5ts1/T2810809??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:10:34.72/chk_obsdata//k5ts2/T2810809??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:10:35.12/chk_obsdata//k5ts3/T2810809??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:10:35.57/chk_obsdata//k5ts4/T2810809??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:10:36.37/k5log//k5ts1_log_newline 2006.281.08:10:37.11/k5log//k5ts2_log_newline 2006.281.08:10:37.96/k5log//k5ts3_log_newline 2006.281.08:10:38.77/k5log//k5ts4_log_newline 2006.281.08:10:38.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:10:38.80:4f8m12a=2 2006.281.08:10:38.80$4f8m12a/echo=on 2006.281.08:10:38.80$4f8m12a/pcalon 2006.281.08:10:38.80$pcalon/"no phase cal control is implemented here 2006.281.08:10:38.80$4f8m12a/"tpicd=stop 2006.281.08:10:38.80$4f8m12a/vc4f8 2006.281.08:10:38.80$vc4f8/valo=1,532.99 2006.281.08:10:38.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.08:10:38.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.08:10:38.80#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:38.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:38.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:38.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:38.80#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:10:38.80#ibcon#first serial, iclass 18, count 0 2006.281.08:10:38.80#ibcon#enter sib2, iclass 18, count 0 2006.281.08:10:38.80#ibcon#flushed, iclass 18, count 0 2006.281.08:10:38.80#ibcon#about to write, iclass 18, count 0 2006.281.08:10:38.80#ibcon#wrote, iclass 18, count 0 2006.281.08:10:38.80#ibcon#about to read 3, iclass 18, count 0 2006.281.08:10:38.81#ibcon#read 3, iclass 18, count 0 2006.281.08:10:38.81#ibcon#about to read 4, iclass 18, count 0 2006.281.08:10:38.81#ibcon#read 4, iclass 18, count 0 2006.281.08:10:38.81#ibcon#about to read 5, iclass 18, count 0 2006.281.08:10:38.81#ibcon#read 5, iclass 18, count 0 2006.281.08:10:38.81#ibcon#about to read 6, iclass 18, count 0 2006.281.08:10:38.81#ibcon#read 6, iclass 18, count 0 2006.281.08:10:38.81#ibcon#end of sib2, iclass 18, count 0 2006.281.08:10:38.81#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:10:38.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:10:38.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:10:38.81#ibcon#*before write, iclass 18, count 0 2006.281.08:10:38.81#ibcon#enter sib2, iclass 18, count 0 2006.281.08:10:38.81#ibcon#flushed, iclass 18, count 0 2006.281.08:10:38.81#ibcon#about to write, iclass 18, count 0 2006.281.08:10:38.81#ibcon#wrote, iclass 18, count 0 2006.281.08:10:38.81#ibcon#about to read 3, iclass 18, count 0 2006.281.08:10:38.87#ibcon#read 3, iclass 18, count 0 2006.281.08:10:38.87#ibcon#about to read 4, iclass 18, count 0 2006.281.08:10:38.87#ibcon#read 4, iclass 18, count 0 2006.281.08:10:38.87#ibcon#about to read 5, iclass 18, count 0 2006.281.08:10:38.87#ibcon#read 5, iclass 18, count 0 2006.281.08:10:38.87#ibcon#about to read 6, iclass 18, count 0 2006.281.08:10:38.87#ibcon#read 6, iclass 18, count 0 2006.281.08:10:38.87#ibcon#end of sib2, iclass 18, count 0 2006.281.08:10:38.87#ibcon#*after write, iclass 18, count 0 2006.281.08:10:38.87#ibcon#*before return 0, iclass 18, count 0 2006.281.08:10:38.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:38.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:38.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:10:38.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:10:38.87$vc4f8/va=1,7 2006.281.08:10:38.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.08:10:38.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.08:10:38.87#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:38.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:38.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:38.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:38.87#ibcon#enter wrdev, iclass 20, count 2 2006.281.08:10:38.87#ibcon#first serial, iclass 20, count 2 2006.281.08:10:38.87#ibcon#enter sib2, iclass 20, count 2 2006.281.08:10:38.87#ibcon#flushed, iclass 20, count 2 2006.281.08:10:38.87#ibcon#about to write, iclass 20, count 2 2006.281.08:10:38.87#ibcon#wrote, iclass 20, count 2 2006.281.08:10:38.87#ibcon#about to read 3, iclass 20, count 2 2006.281.08:10:38.88#ibcon#read 3, iclass 20, count 2 2006.281.08:10:38.89#ibcon#about to read 4, iclass 20, count 2 2006.281.08:10:38.89#ibcon#read 4, iclass 20, count 2 2006.281.08:10:38.89#ibcon#about to read 5, iclass 20, count 2 2006.281.08:10:38.89#ibcon#read 5, iclass 20, count 2 2006.281.08:10:38.89#ibcon#about to read 6, iclass 20, count 2 2006.281.08:10:38.89#ibcon#read 6, iclass 20, count 2 2006.281.08:10:38.89#ibcon#end of sib2, iclass 20, count 2 2006.281.08:10:38.89#ibcon#*mode == 0, iclass 20, count 2 2006.281.08:10:38.89#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.08:10:38.89#ibcon#[25=AT01-07\r\n] 2006.281.08:10:38.89#ibcon#*before write, iclass 20, count 2 2006.281.08:10:38.89#ibcon#enter sib2, iclass 20, count 2 2006.281.08:10:38.89#ibcon#flushed, iclass 20, count 2 2006.281.08:10:38.89#ibcon#about to write, iclass 20, count 2 2006.281.08:10:38.89#ibcon#wrote, iclass 20, count 2 2006.281.08:10:38.89#ibcon#about to read 3, iclass 20, count 2 2006.281.08:10:38.91#ibcon#read 3, iclass 20, count 2 2006.281.08:10:38.91#ibcon#about to read 4, iclass 20, count 2 2006.281.08:10:38.91#ibcon#read 4, iclass 20, count 2 2006.281.08:10:38.91#ibcon#about to read 5, iclass 20, count 2 2006.281.08:10:38.91#ibcon#read 5, iclass 20, count 2 2006.281.08:10:38.91#ibcon#about to read 6, iclass 20, count 2 2006.281.08:10:38.91#ibcon#read 6, iclass 20, count 2 2006.281.08:10:38.91#ibcon#end of sib2, iclass 20, count 2 2006.281.08:10:38.91#ibcon#*after write, iclass 20, count 2 2006.281.08:10:38.91#ibcon#*before return 0, iclass 20, count 2 2006.281.08:10:38.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:38.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:38.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.08:10:38.91#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:38.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:39.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:39.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:39.03#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:10:39.03#ibcon#first serial, iclass 20, count 0 2006.281.08:10:39.03#ibcon#enter sib2, iclass 20, count 0 2006.281.08:10:39.03#ibcon#flushed, iclass 20, count 0 2006.281.08:10:39.03#ibcon#about to write, iclass 20, count 0 2006.281.08:10:39.03#ibcon#wrote, iclass 20, count 0 2006.281.08:10:39.03#ibcon#about to read 3, iclass 20, count 0 2006.281.08:10:39.06#ibcon#read 3, iclass 20, count 0 2006.281.08:10:39.06#ibcon#about to read 4, iclass 20, count 0 2006.281.08:10:39.06#ibcon#read 4, iclass 20, count 0 2006.281.08:10:39.06#ibcon#about to read 5, iclass 20, count 0 2006.281.08:10:39.06#ibcon#read 5, iclass 20, count 0 2006.281.08:10:39.06#ibcon#about to read 6, iclass 20, count 0 2006.281.08:10:39.06#ibcon#read 6, iclass 20, count 0 2006.281.08:10:39.06#ibcon#end of sib2, iclass 20, count 0 2006.281.08:10:39.06#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:10:39.06#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:10:39.06#ibcon#[25=USB\r\n] 2006.281.08:10:39.06#ibcon#*before write, iclass 20, count 0 2006.281.08:10:39.06#ibcon#enter sib2, iclass 20, count 0 2006.281.08:10:39.06#ibcon#flushed, iclass 20, count 0 2006.281.08:10:39.06#ibcon#about to write, iclass 20, count 0 2006.281.08:10:39.06#ibcon#wrote, iclass 20, count 0 2006.281.08:10:39.06#ibcon#about to read 3, iclass 20, count 0 2006.281.08:10:39.08#ibcon#read 3, iclass 20, count 0 2006.281.08:10:39.08#ibcon#about to read 4, iclass 20, count 0 2006.281.08:10:39.08#ibcon#read 4, iclass 20, count 0 2006.281.08:10:39.08#ibcon#about to read 5, iclass 20, count 0 2006.281.08:10:39.08#ibcon#read 5, iclass 20, count 0 2006.281.08:10:39.08#ibcon#about to read 6, iclass 20, count 0 2006.281.08:10:39.08#ibcon#read 6, iclass 20, count 0 2006.281.08:10:39.08#ibcon#end of sib2, iclass 20, count 0 2006.281.08:10:39.08#ibcon#*after write, iclass 20, count 0 2006.281.08:10:39.08#ibcon#*before return 0, iclass 20, count 0 2006.281.08:10:39.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:39.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:39.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:10:39.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:10:39.09$vc4f8/valo=2,572.99 2006.281.08:10:39.09#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.08:10:39.09#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.08:10:39.09#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:39.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:39.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:39.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:39.09#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:10:39.09#ibcon#first serial, iclass 22, count 0 2006.281.08:10:39.09#ibcon#enter sib2, iclass 22, count 0 2006.281.08:10:39.09#ibcon#flushed, iclass 22, count 0 2006.281.08:10:39.09#ibcon#about to write, iclass 22, count 0 2006.281.08:10:39.09#ibcon#wrote, iclass 22, count 0 2006.281.08:10:39.09#ibcon#about to read 3, iclass 22, count 0 2006.281.08:10:39.10#ibcon#read 3, iclass 22, count 0 2006.281.08:10:39.10#ibcon#about to read 4, iclass 22, count 0 2006.281.08:10:39.10#ibcon#read 4, iclass 22, count 0 2006.281.08:10:39.10#ibcon#about to read 5, iclass 22, count 0 2006.281.08:10:39.10#ibcon#read 5, iclass 22, count 0 2006.281.08:10:39.10#ibcon#about to read 6, iclass 22, count 0 2006.281.08:10:39.10#ibcon#read 6, iclass 22, count 0 2006.281.08:10:39.10#ibcon#end of sib2, iclass 22, count 0 2006.281.08:10:39.10#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:10:39.10#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:10:39.10#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:10:39.10#ibcon#*before write, iclass 22, count 0 2006.281.08:10:39.10#ibcon#enter sib2, iclass 22, count 0 2006.281.08:10:39.10#ibcon#flushed, iclass 22, count 0 2006.281.08:10:39.10#ibcon#about to write, iclass 22, count 0 2006.281.08:10:39.10#ibcon#wrote, iclass 22, count 0 2006.281.08:10:39.10#ibcon#about to read 3, iclass 22, count 0 2006.281.08:10:39.15#ibcon#read 3, iclass 22, count 0 2006.281.08:10:39.15#ibcon#about to read 4, iclass 22, count 0 2006.281.08:10:39.15#ibcon#read 4, iclass 22, count 0 2006.281.08:10:39.15#ibcon#about to read 5, iclass 22, count 0 2006.281.08:10:39.15#ibcon#read 5, iclass 22, count 0 2006.281.08:10:39.15#ibcon#about to read 6, iclass 22, count 0 2006.281.08:10:39.15#ibcon#read 6, iclass 22, count 0 2006.281.08:10:39.15#ibcon#end of sib2, iclass 22, count 0 2006.281.08:10:39.15#ibcon#*after write, iclass 22, count 0 2006.281.08:10:39.15#ibcon#*before return 0, iclass 22, count 0 2006.281.08:10:39.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:39.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:39.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:10:39.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:10:39.15$vc4f8/va=2,6 2006.281.08:10:39.15#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.08:10:39.15#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.08:10:39.15#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:39.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:39.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:39.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:39.19#ibcon#enter wrdev, iclass 24, count 2 2006.281.08:10:39.19#ibcon#first serial, iclass 24, count 2 2006.281.08:10:39.19#ibcon#enter sib2, iclass 24, count 2 2006.281.08:10:39.19#ibcon#flushed, iclass 24, count 2 2006.281.08:10:39.19#ibcon#about to write, iclass 24, count 2 2006.281.08:10:39.19#ibcon#wrote, iclass 24, count 2 2006.281.08:10:39.19#ibcon#about to read 3, iclass 24, count 2 2006.281.08:10:39.22#ibcon#read 3, iclass 24, count 2 2006.281.08:10:39.22#ibcon#about to read 4, iclass 24, count 2 2006.281.08:10:39.22#ibcon#read 4, iclass 24, count 2 2006.281.08:10:39.22#ibcon#about to read 5, iclass 24, count 2 2006.281.08:10:39.22#ibcon#read 5, iclass 24, count 2 2006.281.08:10:39.22#ibcon#about to read 6, iclass 24, count 2 2006.281.08:10:39.22#ibcon#read 6, iclass 24, count 2 2006.281.08:10:39.22#ibcon#end of sib2, iclass 24, count 2 2006.281.08:10:39.22#ibcon#*mode == 0, iclass 24, count 2 2006.281.08:10:39.22#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.08:10:39.22#ibcon#[25=AT02-06\r\n] 2006.281.08:10:39.22#ibcon#*before write, iclass 24, count 2 2006.281.08:10:39.22#ibcon#enter sib2, iclass 24, count 2 2006.281.08:10:39.22#ibcon#flushed, iclass 24, count 2 2006.281.08:10:39.22#ibcon#about to write, iclass 24, count 2 2006.281.08:10:39.22#ibcon#wrote, iclass 24, count 2 2006.281.08:10:39.22#ibcon#about to read 3, iclass 24, count 2 2006.281.08:10:39.25#ibcon#read 3, iclass 24, count 2 2006.281.08:10:39.25#ibcon#about to read 4, iclass 24, count 2 2006.281.08:10:39.25#ibcon#read 4, iclass 24, count 2 2006.281.08:10:39.25#ibcon#about to read 5, iclass 24, count 2 2006.281.08:10:39.25#ibcon#read 5, iclass 24, count 2 2006.281.08:10:39.25#ibcon#about to read 6, iclass 24, count 2 2006.281.08:10:39.25#ibcon#read 6, iclass 24, count 2 2006.281.08:10:39.25#ibcon#end of sib2, iclass 24, count 2 2006.281.08:10:39.25#ibcon#*after write, iclass 24, count 2 2006.281.08:10:39.25#ibcon#*before return 0, iclass 24, count 2 2006.281.08:10:39.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:39.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:39.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.08:10:39.25#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:39.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:39.36#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:39.36#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:39.36#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:10:39.36#ibcon#first serial, iclass 24, count 0 2006.281.08:10:39.36#ibcon#enter sib2, iclass 24, count 0 2006.281.08:10:39.36#ibcon#flushed, iclass 24, count 0 2006.281.08:10:39.36#ibcon#about to write, iclass 24, count 0 2006.281.08:10:39.36#ibcon#wrote, iclass 24, count 0 2006.281.08:10:39.36#ibcon#about to read 3, iclass 24, count 0 2006.281.08:10:39.38#ibcon#read 3, iclass 24, count 0 2006.281.08:10:39.38#ibcon#about to read 4, iclass 24, count 0 2006.281.08:10:39.38#ibcon#read 4, iclass 24, count 0 2006.281.08:10:39.38#ibcon#about to read 5, iclass 24, count 0 2006.281.08:10:39.38#ibcon#read 5, iclass 24, count 0 2006.281.08:10:39.38#ibcon#about to read 6, iclass 24, count 0 2006.281.08:10:39.38#ibcon#read 6, iclass 24, count 0 2006.281.08:10:39.38#ibcon#end of sib2, iclass 24, count 0 2006.281.08:10:39.38#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:10:39.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:10:39.38#ibcon#[25=USB\r\n] 2006.281.08:10:39.38#ibcon#*before write, iclass 24, count 0 2006.281.08:10:39.38#ibcon#enter sib2, iclass 24, count 0 2006.281.08:10:39.38#ibcon#flushed, iclass 24, count 0 2006.281.08:10:39.38#ibcon#about to write, iclass 24, count 0 2006.281.08:10:39.38#ibcon#wrote, iclass 24, count 0 2006.281.08:10:39.38#ibcon#about to read 3, iclass 24, count 0 2006.281.08:10:39.42#ibcon#read 3, iclass 24, count 0 2006.281.08:10:39.42#ibcon#about to read 4, iclass 24, count 0 2006.281.08:10:39.42#ibcon#read 4, iclass 24, count 0 2006.281.08:10:39.42#ibcon#about to read 5, iclass 24, count 0 2006.281.08:10:39.42#ibcon#read 5, iclass 24, count 0 2006.281.08:10:39.42#ibcon#about to read 6, iclass 24, count 0 2006.281.08:10:39.42#ibcon#read 6, iclass 24, count 0 2006.281.08:10:39.42#ibcon#end of sib2, iclass 24, count 0 2006.281.08:10:39.42#ibcon#*after write, iclass 24, count 0 2006.281.08:10:39.42#ibcon#*before return 0, iclass 24, count 0 2006.281.08:10:39.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:39.42#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:39.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:10:39.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:10:39.42$vc4f8/valo=3,672.99 2006.281.08:10:39.42#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.08:10:39.42#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.08:10:39.42#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:39.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:39.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:39.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:39.42#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:10:39.42#ibcon#first serial, iclass 26, count 0 2006.281.08:10:39.42#ibcon#enter sib2, iclass 26, count 0 2006.281.08:10:39.42#ibcon#flushed, iclass 26, count 0 2006.281.08:10:39.42#ibcon#about to write, iclass 26, count 0 2006.281.08:10:39.42#ibcon#wrote, iclass 26, count 0 2006.281.08:10:39.42#ibcon#about to read 3, iclass 26, count 0 2006.281.08:10:39.43#ibcon#read 3, iclass 26, count 0 2006.281.08:10:39.43#ibcon#about to read 4, iclass 26, count 0 2006.281.08:10:39.43#ibcon#read 4, iclass 26, count 0 2006.281.08:10:39.43#ibcon#about to read 5, iclass 26, count 0 2006.281.08:10:39.43#ibcon#read 5, iclass 26, count 0 2006.281.08:10:39.43#ibcon#about to read 6, iclass 26, count 0 2006.281.08:10:39.43#ibcon#read 6, iclass 26, count 0 2006.281.08:10:39.43#ibcon#end of sib2, iclass 26, count 0 2006.281.08:10:39.43#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:10:39.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:10:39.46#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:10:39.46#ibcon#*before write, iclass 26, count 0 2006.281.08:10:39.46#ibcon#enter sib2, iclass 26, count 0 2006.281.08:10:39.46#ibcon#flushed, iclass 26, count 0 2006.281.08:10:39.46#ibcon#about to write, iclass 26, count 0 2006.281.08:10:39.46#ibcon#wrote, iclass 26, count 0 2006.281.08:10:39.46#ibcon#about to read 3, iclass 26, count 0 2006.281.08:10:39.49#ibcon#read 3, iclass 26, count 0 2006.281.08:10:39.49#ibcon#about to read 4, iclass 26, count 0 2006.281.08:10:39.49#ibcon#read 4, iclass 26, count 0 2006.281.08:10:39.49#ibcon#about to read 5, iclass 26, count 0 2006.281.08:10:39.49#ibcon#read 5, iclass 26, count 0 2006.281.08:10:39.49#ibcon#about to read 6, iclass 26, count 0 2006.281.08:10:39.49#ibcon#read 6, iclass 26, count 0 2006.281.08:10:39.49#ibcon#end of sib2, iclass 26, count 0 2006.281.08:10:39.49#ibcon#*after write, iclass 26, count 0 2006.281.08:10:39.49#ibcon#*before return 0, iclass 26, count 0 2006.281.08:10:39.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:39.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:39.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:10:39.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:10:39.50$vc4f8/va=3,6 2006.281.08:10:39.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.08:10:39.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.08:10:39.50#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:39.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:39.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:39.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:39.54#ibcon#enter wrdev, iclass 28, count 2 2006.281.08:10:39.54#ibcon#first serial, iclass 28, count 2 2006.281.08:10:39.54#ibcon#enter sib2, iclass 28, count 2 2006.281.08:10:39.54#ibcon#flushed, iclass 28, count 2 2006.281.08:10:39.54#ibcon#about to write, iclass 28, count 2 2006.281.08:10:39.54#ibcon#wrote, iclass 28, count 2 2006.281.08:10:39.54#ibcon#about to read 3, iclass 28, count 2 2006.281.08:10:39.55#ibcon#read 3, iclass 28, count 2 2006.281.08:10:39.55#ibcon#about to read 4, iclass 28, count 2 2006.281.08:10:39.55#ibcon#read 4, iclass 28, count 2 2006.281.08:10:39.55#ibcon#about to read 5, iclass 28, count 2 2006.281.08:10:39.55#ibcon#read 5, iclass 28, count 2 2006.281.08:10:39.55#ibcon#about to read 6, iclass 28, count 2 2006.281.08:10:39.55#ibcon#read 6, iclass 28, count 2 2006.281.08:10:39.55#ibcon#end of sib2, iclass 28, count 2 2006.281.08:10:39.55#ibcon#*mode == 0, iclass 28, count 2 2006.281.08:10:39.55#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.08:10:39.55#ibcon#[25=AT03-06\r\n] 2006.281.08:10:39.55#ibcon#*before write, iclass 28, count 2 2006.281.08:10:39.55#ibcon#enter sib2, iclass 28, count 2 2006.281.08:10:39.55#ibcon#flushed, iclass 28, count 2 2006.281.08:10:39.55#ibcon#about to write, iclass 28, count 2 2006.281.08:10:39.55#ibcon#wrote, iclass 28, count 2 2006.281.08:10:39.55#ibcon#about to read 3, iclass 28, count 2 2006.281.08:10:39.58#ibcon#read 3, iclass 28, count 2 2006.281.08:10:39.58#ibcon#about to read 4, iclass 28, count 2 2006.281.08:10:39.58#ibcon#read 4, iclass 28, count 2 2006.281.08:10:39.58#ibcon#about to read 5, iclass 28, count 2 2006.281.08:10:39.58#ibcon#read 5, iclass 28, count 2 2006.281.08:10:39.58#ibcon#about to read 6, iclass 28, count 2 2006.281.08:10:39.58#ibcon#read 6, iclass 28, count 2 2006.281.08:10:39.58#ibcon#end of sib2, iclass 28, count 2 2006.281.08:10:39.58#ibcon#*after write, iclass 28, count 2 2006.281.08:10:39.58#ibcon#*before return 0, iclass 28, count 2 2006.281.08:10:39.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:39.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:39.58#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.08:10:39.58#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:39.58#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:39.70#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:39.70#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:39.70#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:10:39.70#ibcon#first serial, iclass 28, count 0 2006.281.08:10:39.70#ibcon#enter sib2, iclass 28, count 0 2006.281.08:10:39.70#ibcon#flushed, iclass 28, count 0 2006.281.08:10:39.70#ibcon#about to write, iclass 28, count 0 2006.281.08:10:39.70#ibcon#wrote, iclass 28, count 0 2006.281.08:10:39.70#ibcon#about to read 3, iclass 28, count 0 2006.281.08:10:39.72#ibcon#read 3, iclass 28, count 0 2006.281.08:10:39.72#ibcon#about to read 4, iclass 28, count 0 2006.281.08:10:39.72#ibcon#read 4, iclass 28, count 0 2006.281.08:10:39.72#ibcon#about to read 5, iclass 28, count 0 2006.281.08:10:39.72#ibcon#read 5, iclass 28, count 0 2006.281.08:10:39.72#ibcon#about to read 6, iclass 28, count 0 2006.281.08:10:39.72#ibcon#read 6, iclass 28, count 0 2006.281.08:10:39.72#ibcon#end of sib2, iclass 28, count 0 2006.281.08:10:39.72#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:10:39.72#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:10:39.72#ibcon#[25=USB\r\n] 2006.281.08:10:39.72#ibcon#*before write, iclass 28, count 0 2006.281.08:10:39.72#ibcon#enter sib2, iclass 28, count 0 2006.281.08:10:39.72#ibcon#flushed, iclass 28, count 0 2006.281.08:10:39.72#ibcon#about to write, iclass 28, count 0 2006.281.08:10:39.72#ibcon#wrote, iclass 28, count 0 2006.281.08:10:39.72#ibcon#about to read 3, iclass 28, count 0 2006.281.08:10:39.75#ibcon#read 3, iclass 28, count 0 2006.281.08:10:39.75#ibcon#about to read 4, iclass 28, count 0 2006.281.08:10:39.75#ibcon#read 4, iclass 28, count 0 2006.281.08:10:39.75#ibcon#about to read 5, iclass 28, count 0 2006.281.08:10:39.75#ibcon#read 5, iclass 28, count 0 2006.281.08:10:39.75#ibcon#about to read 6, iclass 28, count 0 2006.281.08:10:39.75#ibcon#read 6, iclass 28, count 0 2006.281.08:10:39.75#ibcon#end of sib2, iclass 28, count 0 2006.281.08:10:39.75#ibcon#*after write, iclass 28, count 0 2006.281.08:10:39.75#ibcon#*before return 0, iclass 28, count 0 2006.281.08:10:39.75#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:39.75#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:39.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:10:39.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:10:39.76$vc4f8/valo=4,832.99 2006.281.08:10:39.76#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.08:10:39.76#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.08:10:39.76#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:39.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:10:39.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:10:39.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:10:39.76#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:10:39.76#ibcon#first serial, iclass 30, count 0 2006.281.08:10:39.76#ibcon#enter sib2, iclass 30, count 0 2006.281.08:10:39.76#ibcon#flushed, iclass 30, count 0 2006.281.08:10:39.76#ibcon#about to write, iclass 30, count 0 2006.281.08:10:39.76#ibcon#wrote, iclass 30, count 0 2006.281.08:10:39.76#ibcon#about to read 3, iclass 30, count 0 2006.281.08:10:39.77#ibcon#read 3, iclass 30, count 0 2006.281.08:10:39.77#ibcon#about to read 4, iclass 30, count 0 2006.281.08:10:39.77#ibcon#read 4, iclass 30, count 0 2006.281.08:10:39.77#ibcon#about to read 5, iclass 30, count 0 2006.281.08:10:39.77#ibcon#read 5, iclass 30, count 0 2006.281.08:10:39.77#ibcon#about to read 6, iclass 30, count 0 2006.281.08:10:39.77#ibcon#read 6, iclass 30, count 0 2006.281.08:10:39.77#ibcon#end of sib2, iclass 30, count 0 2006.281.08:10:39.77#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:10:39.77#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:10:39.77#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:10:39.77#ibcon#*before write, iclass 30, count 0 2006.281.08:10:39.77#ibcon#enter sib2, iclass 30, count 0 2006.281.08:10:39.77#ibcon#flushed, iclass 30, count 0 2006.281.08:10:39.77#ibcon#about to write, iclass 30, count 0 2006.281.08:10:39.77#ibcon#wrote, iclass 30, count 0 2006.281.08:10:39.78#ibcon#about to read 3, iclass 30, count 0 2006.281.08:10:39.82#ibcon#read 3, iclass 30, count 0 2006.281.08:10:39.82#ibcon#about to read 4, iclass 30, count 0 2006.281.08:10:39.82#ibcon#read 4, iclass 30, count 0 2006.281.08:10:39.82#ibcon#about to read 5, iclass 30, count 0 2006.281.08:10:39.82#ibcon#read 5, iclass 30, count 0 2006.281.08:10:39.82#ibcon#about to read 6, iclass 30, count 0 2006.281.08:10:39.82#ibcon#read 6, iclass 30, count 0 2006.281.08:10:39.82#ibcon#end of sib2, iclass 30, count 0 2006.281.08:10:39.82#ibcon#*after write, iclass 30, count 0 2006.281.08:10:39.82#ibcon#*before return 0, iclass 30, count 0 2006.281.08:10:39.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:10:39.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:10:39.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:10:39.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:10:39.82$vc4f8/va=4,6 2006.281.08:10:39.82#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.08:10:39.82#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.08:10:39.82#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:39.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:10:39.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:10:39.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:10:39.86#ibcon#enter wrdev, iclass 32, count 2 2006.281.08:10:39.86#ibcon#first serial, iclass 32, count 2 2006.281.08:10:39.86#ibcon#enter sib2, iclass 32, count 2 2006.281.08:10:39.86#ibcon#flushed, iclass 32, count 2 2006.281.08:10:39.86#ibcon#about to write, iclass 32, count 2 2006.281.08:10:39.86#ibcon#wrote, iclass 32, count 2 2006.281.08:10:39.86#ibcon#about to read 3, iclass 32, count 2 2006.281.08:10:39.88#ibcon#read 3, iclass 32, count 2 2006.281.08:10:39.88#ibcon#about to read 4, iclass 32, count 2 2006.281.08:10:39.88#ibcon#read 4, iclass 32, count 2 2006.281.08:10:39.88#ibcon#about to read 5, iclass 32, count 2 2006.281.08:10:39.88#ibcon#read 5, iclass 32, count 2 2006.281.08:10:39.88#ibcon#about to read 6, iclass 32, count 2 2006.281.08:10:39.88#ibcon#read 6, iclass 32, count 2 2006.281.08:10:39.88#ibcon#end of sib2, iclass 32, count 2 2006.281.08:10:39.88#ibcon#*mode == 0, iclass 32, count 2 2006.281.08:10:39.88#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.08:10:39.88#ibcon#[25=AT04-06\r\n] 2006.281.08:10:39.88#ibcon#*before write, iclass 32, count 2 2006.281.08:10:39.88#ibcon#enter sib2, iclass 32, count 2 2006.281.08:10:39.88#ibcon#flushed, iclass 32, count 2 2006.281.08:10:39.88#ibcon#about to write, iclass 32, count 2 2006.281.08:10:39.88#ibcon#wrote, iclass 32, count 2 2006.281.08:10:39.88#ibcon#about to read 3, iclass 32, count 2 2006.281.08:10:39.92#ibcon#read 3, iclass 32, count 2 2006.281.08:10:39.92#ibcon#about to read 4, iclass 32, count 2 2006.281.08:10:39.92#ibcon#read 4, iclass 32, count 2 2006.281.08:10:39.92#ibcon#about to read 5, iclass 32, count 2 2006.281.08:10:39.92#ibcon#read 5, iclass 32, count 2 2006.281.08:10:39.92#ibcon#about to read 6, iclass 32, count 2 2006.281.08:10:39.92#ibcon#read 6, iclass 32, count 2 2006.281.08:10:39.92#ibcon#end of sib2, iclass 32, count 2 2006.281.08:10:39.92#ibcon#*after write, iclass 32, count 2 2006.281.08:10:39.92#ibcon#*before return 0, iclass 32, count 2 2006.281.08:10:39.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:10:39.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:10:39.92#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.08:10:39.92#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:39.92#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:10:40.04#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:10:40.04#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:10:40.04#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:10:40.04#ibcon#first serial, iclass 32, count 0 2006.281.08:10:40.04#ibcon#enter sib2, iclass 32, count 0 2006.281.08:10:40.04#ibcon#flushed, iclass 32, count 0 2006.281.08:10:40.04#ibcon#about to write, iclass 32, count 0 2006.281.08:10:40.04#ibcon#wrote, iclass 32, count 0 2006.281.08:10:40.04#ibcon#about to read 3, iclass 32, count 0 2006.281.08:10:40.05#ibcon#read 3, iclass 32, count 0 2006.281.08:10:40.05#ibcon#about to read 4, iclass 32, count 0 2006.281.08:10:40.05#ibcon#read 4, iclass 32, count 0 2006.281.08:10:40.05#ibcon#about to read 5, iclass 32, count 0 2006.281.08:10:40.05#ibcon#read 5, iclass 32, count 0 2006.281.08:10:40.05#ibcon#about to read 6, iclass 32, count 0 2006.281.08:10:40.05#ibcon#read 6, iclass 32, count 0 2006.281.08:10:40.05#ibcon#end of sib2, iclass 32, count 0 2006.281.08:10:40.05#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:10:40.05#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:10:40.05#ibcon#[25=USB\r\n] 2006.281.08:10:40.05#ibcon#*before write, iclass 32, count 0 2006.281.08:10:40.05#ibcon#enter sib2, iclass 32, count 0 2006.281.08:10:40.05#ibcon#flushed, iclass 32, count 0 2006.281.08:10:40.05#ibcon#about to write, iclass 32, count 0 2006.281.08:10:40.06#ibcon#wrote, iclass 32, count 0 2006.281.08:10:40.06#ibcon#about to read 3, iclass 32, count 0 2006.281.08:10:40.08#ibcon#read 3, iclass 32, count 0 2006.281.08:10:40.08#ibcon#about to read 4, iclass 32, count 0 2006.281.08:10:40.08#ibcon#read 4, iclass 32, count 0 2006.281.08:10:40.08#ibcon#about to read 5, iclass 32, count 0 2006.281.08:10:40.08#ibcon#read 5, iclass 32, count 0 2006.281.08:10:40.08#ibcon#about to read 6, iclass 32, count 0 2006.281.08:10:40.08#ibcon#read 6, iclass 32, count 0 2006.281.08:10:40.08#ibcon#end of sib2, iclass 32, count 0 2006.281.08:10:40.08#ibcon#*after write, iclass 32, count 0 2006.281.08:10:40.08#ibcon#*before return 0, iclass 32, count 0 2006.281.08:10:40.08#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:10:40.08#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:10:40.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:10:40.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:10:40.09$vc4f8/valo=5,652.99 2006.281.08:10:40.09#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.08:10:40.09#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.08:10:40.09#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:40.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:10:40.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:10:40.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:10:40.09#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:10:40.09#ibcon#first serial, iclass 34, count 0 2006.281.08:10:40.09#ibcon#enter sib2, iclass 34, count 0 2006.281.08:10:40.09#ibcon#flushed, iclass 34, count 0 2006.281.08:10:40.09#ibcon#about to write, iclass 34, count 0 2006.281.08:10:40.09#ibcon#wrote, iclass 34, count 0 2006.281.08:10:40.09#ibcon#about to read 3, iclass 34, count 0 2006.281.08:10:40.10#ibcon#read 3, iclass 34, count 0 2006.281.08:10:40.10#ibcon#about to read 4, iclass 34, count 0 2006.281.08:10:40.10#ibcon#read 4, iclass 34, count 0 2006.281.08:10:40.10#ibcon#about to read 5, iclass 34, count 0 2006.281.08:10:40.10#ibcon#read 5, iclass 34, count 0 2006.281.08:10:40.10#ibcon#about to read 6, iclass 34, count 0 2006.281.08:10:40.10#ibcon#read 6, iclass 34, count 0 2006.281.08:10:40.10#ibcon#end of sib2, iclass 34, count 0 2006.281.08:10:40.10#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:10:40.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:10:40.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:10:40.10#ibcon#*before write, iclass 34, count 0 2006.281.08:10:40.10#ibcon#enter sib2, iclass 34, count 0 2006.281.08:10:40.10#ibcon#flushed, iclass 34, count 0 2006.281.08:10:40.10#ibcon#about to write, iclass 34, count 0 2006.281.08:10:40.10#ibcon#wrote, iclass 34, count 0 2006.281.08:10:40.10#ibcon#about to read 3, iclass 34, count 0 2006.281.08:10:40.15#ibcon#read 3, iclass 34, count 0 2006.281.08:10:40.15#ibcon#about to read 4, iclass 34, count 0 2006.281.08:10:40.15#ibcon#read 4, iclass 34, count 0 2006.281.08:10:40.15#ibcon#about to read 5, iclass 34, count 0 2006.281.08:10:40.15#ibcon#read 5, iclass 34, count 0 2006.281.08:10:40.15#ibcon#about to read 6, iclass 34, count 0 2006.281.08:10:40.15#ibcon#read 6, iclass 34, count 0 2006.281.08:10:40.15#ibcon#end of sib2, iclass 34, count 0 2006.281.08:10:40.15#ibcon#*after write, iclass 34, count 0 2006.281.08:10:40.15#ibcon#*before return 0, iclass 34, count 0 2006.281.08:10:40.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:10:40.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:10:40.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:10:40.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:10:40.15$vc4f8/va=5,7 2006.281.08:10:40.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.08:10:40.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.08:10:40.16#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:40.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:10:40.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:10:40.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:10:40.19#ibcon#enter wrdev, iclass 36, count 2 2006.281.08:10:40.19#ibcon#first serial, iclass 36, count 2 2006.281.08:10:40.19#ibcon#enter sib2, iclass 36, count 2 2006.281.08:10:40.19#ibcon#flushed, iclass 36, count 2 2006.281.08:10:40.19#ibcon#about to write, iclass 36, count 2 2006.281.08:10:40.19#ibcon#wrote, iclass 36, count 2 2006.281.08:10:40.19#ibcon#about to read 3, iclass 36, count 2 2006.281.08:10:40.21#ibcon#read 3, iclass 36, count 2 2006.281.08:10:40.21#ibcon#about to read 4, iclass 36, count 2 2006.281.08:10:40.21#ibcon#read 4, iclass 36, count 2 2006.281.08:10:40.21#ibcon#about to read 5, iclass 36, count 2 2006.281.08:10:40.21#ibcon#read 5, iclass 36, count 2 2006.281.08:10:40.21#ibcon#about to read 6, iclass 36, count 2 2006.281.08:10:40.21#ibcon#read 6, iclass 36, count 2 2006.281.08:10:40.21#ibcon#end of sib2, iclass 36, count 2 2006.281.08:10:40.21#ibcon#*mode == 0, iclass 36, count 2 2006.281.08:10:40.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.08:10:40.21#ibcon#[25=AT05-07\r\n] 2006.281.08:10:40.21#ibcon#*before write, iclass 36, count 2 2006.281.08:10:40.21#ibcon#enter sib2, iclass 36, count 2 2006.281.08:10:40.21#ibcon#flushed, iclass 36, count 2 2006.281.08:10:40.21#ibcon#about to write, iclass 36, count 2 2006.281.08:10:40.21#ibcon#wrote, iclass 36, count 2 2006.281.08:10:40.21#ibcon#about to read 3, iclass 36, count 2 2006.281.08:10:40.24#ibcon#read 3, iclass 36, count 2 2006.281.08:10:40.24#ibcon#about to read 4, iclass 36, count 2 2006.281.08:10:40.24#ibcon#read 4, iclass 36, count 2 2006.281.08:10:40.24#ibcon#about to read 5, iclass 36, count 2 2006.281.08:10:40.24#ibcon#read 5, iclass 36, count 2 2006.281.08:10:40.24#ibcon#about to read 6, iclass 36, count 2 2006.281.08:10:40.24#ibcon#read 6, iclass 36, count 2 2006.281.08:10:40.24#ibcon#end of sib2, iclass 36, count 2 2006.281.08:10:40.24#ibcon#*after write, iclass 36, count 2 2006.281.08:10:40.24#ibcon#*before return 0, iclass 36, count 2 2006.281.08:10:40.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:10:40.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:10:40.24#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.08:10:40.24#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:40.24#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:10:40.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:10:40.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:10:40.36#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:10:40.36#ibcon#first serial, iclass 36, count 0 2006.281.08:10:40.36#ibcon#enter sib2, iclass 36, count 0 2006.281.08:10:40.36#ibcon#flushed, iclass 36, count 0 2006.281.08:10:40.36#ibcon#about to write, iclass 36, count 0 2006.281.08:10:40.36#ibcon#wrote, iclass 36, count 0 2006.281.08:10:40.36#ibcon#about to read 3, iclass 36, count 0 2006.281.08:10:40.38#ibcon#read 3, iclass 36, count 0 2006.281.08:10:40.38#ibcon#about to read 4, iclass 36, count 0 2006.281.08:10:40.38#ibcon#read 4, iclass 36, count 0 2006.281.08:10:40.38#ibcon#about to read 5, iclass 36, count 0 2006.281.08:10:40.38#ibcon#read 5, iclass 36, count 0 2006.281.08:10:40.38#ibcon#about to read 6, iclass 36, count 0 2006.281.08:10:40.38#ibcon#read 6, iclass 36, count 0 2006.281.08:10:40.38#ibcon#end of sib2, iclass 36, count 0 2006.281.08:10:40.38#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:10:40.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:10:40.38#ibcon#[25=USB\r\n] 2006.281.08:10:40.38#ibcon#*before write, iclass 36, count 0 2006.281.08:10:40.38#ibcon#enter sib2, iclass 36, count 0 2006.281.08:10:40.38#ibcon#flushed, iclass 36, count 0 2006.281.08:10:40.38#ibcon#about to write, iclass 36, count 0 2006.281.08:10:40.38#ibcon#wrote, iclass 36, count 0 2006.281.08:10:40.38#ibcon#about to read 3, iclass 36, count 0 2006.281.08:10:40.42#ibcon#read 3, iclass 36, count 0 2006.281.08:10:40.42#ibcon#about to read 4, iclass 36, count 0 2006.281.08:10:40.42#ibcon#read 4, iclass 36, count 0 2006.281.08:10:40.42#ibcon#about to read 5, iclass 36, count 0 2006.281.08:10:40.42#ibcon#read 5, iclass 36, count 0 2006.281.08:10:40.42#ibcon#about to read 6, iclass 36, count 0 2006.281.08:10:40.42#ibcon#read 6, iclass 36, count 0 2006.281.08:10:40.42#ibcon#end of sib2, iclass 36, count 0 2006.281.08:10:40.42#ibcon#*after write, iclass 36, count 0 2006.281.08:10:40.42#ibcon#*before return 0, iclass 36, count 0 2006.281.08:10:40.42#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:10:40.42#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:10:40.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:10:40.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:10:40.42$vc4f8/valo=6,772.99 2006.281.08:10:40.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:10:40.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:10:40.42#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:40.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:40.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:40.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:40.42#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:10:40.42#ibcon#first serial, iclass 38, count 0 2006.281.08:10:40.42#ibcon#enter sib2, iclass 38, count 0 2006.281.08:10:40.42#ibcon#flushed, iclass 38, count 0 2006.281.08:10:40.42#ibcon#about to write, iclass 38, count 0 2006.281.08:10:40.42#ibcon#wrote, iclass 38, count 0 2006.281.08:10:40.42#ibcon#about to read 3, iclass 38, count 0 2006.281.08:10:40.44#ibcon#read 3, iclass 38, count 0 2006.281.08:10:40.44#ibcon#about to read 4, iclass 38, count 0 2006.281.08:10:40.44#ibcon#read 4, iclass 38, count 0 2006.281.08:10:40.44#ibcon#about to read 5, iclass 38, count 0 2006.281.08:10:40.44#ibcon#read 5, iclass 38, count 0 2006.281.08:10:40.44#ibcon#about to read 6, iclass 38, count 0 2006.281.08:10:40.44#ibcon#read 6, iclass 38, count 0 2006.281.08:10:40.44#ibcon#end of sib2, iclass 38, count 0 2006.281.08:10:40.44#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:10:40.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:10:40.44#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:10:40.44#ibcon#*before write, iclass 38, count 0 2006.281.08:10:40.44#ibcon#enter sib2, iclass 38, count 0 2006.281.08:10:40.44#ibcon#flushed, iclass 38, count 0 2006.281.08:10:40.44#ibcon#about to write, iclass 38, count 0 2006.281.08:10:40.45#ibcon#wrote, iclass 38, count 0 2006.281.08:10:40.45#ibcon#about to read 3, iclass 38, count 0 2006.281.08:10:40.49#ibcon#read 3, iclass 38, count 0 2006.281.08:10:40.49#ibcon#about to read 4, iclass 38, count 0 2006.281.08:10:40.49#ibcon#read 4, iclass 38, count 0 2006.281.08:10:40.49#ibcon#about to read 5, iclass 38, count 0 2006.281.08:10:40.49#ibcon#read 5, iclass 38, count 0 2006.281.08:10:40.49#ibcon#about to read 6, iclass 38, count 0 2006.281.08:10:40.49#ibcon#read 6, iclass 38, count 0 2006.281.08:10:40.49#ibcon#end of sib2, iclass 38, count 0 2006.281.08:10:40.49#ibcon#*after write, iclass 38, count 0 2006.281.08:10:40.49#ibcon#*before return 0, iclass 38, count 0 2006.281.08:10:40.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:40.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:40.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:10:40.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:10:40.50$vc4f8/va=6,6 2006.281.08:10:40.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:10:40.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:10:40.50#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:40.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:40.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:40.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:40.54#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:10:40.54#ibcon#first serial, iclass 40, count 2 2006.281.08:10:40.54#ibcon#enter sib2, iclass 40, count 2 2006.281.08:10:40.54#ibcon#flushed, iclass 40, count 2 2006.281.08:10:40.54#ibcon#about to write, iclass 40, count 2 2006.281.08:10:40.54#ibcon#wrote, iclass 40, count 2 2006.281.08:10:40.54#ibcon#about to read 3, iclass 40, count 2 2006.281.08:10:40.55#ibcon#read 3, iclass 40, count 2 2006.281.08:10:40.55#ibcon#about to read 4, iclass 40, count 2 2006.281.08:10:40.55#ibcon#read 4, iclass 40, count 2 2006.281.08:10:40.55#ibcon#about to read 5, iclass 40, count 2 2006.281.08:10:40.55#ibcon#read 5, iclass 40, count 2 2006.281.08:10:40.55#ibcon#about to read 6, iclass 40, count 2 2006.281.08:10:40.55#ibcon#read 6, iclass 40, count 2 2006.281.08:10:40.55#ibcon#end of sib2, iclass 40, count 2 2006.281.08:10:40.55#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:10:40.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:10:40.55#ibcon#[25=AT06-06\r\n] 2006.281.08:10:40.55#ibcon#*before write, iclass 40, count 2 2006.281.08:10:40.55#ibcon#enter sib2, iclass 40, count 2 2006.281.08:10:40.55#ibcon#flushed, iclass 40, count 2 2006.281.08:10:40.55#ibcon#about to write, iclass 40, count 2 2006.281.08:10:40.56#ibcon#wrote, iclass 40, count 2 2006.281.08:10:40.56#ibcon#about to read 3, iclass 40, count 2 2006.281.08:10:40.58#ibcon#read 3, iclass 40, count 2 2006.281.08:10:40.58#ibcon#about to read 4, iclass 40, count 2 2006.281.08:10:40.58#ibcon#read 4, iclass 40, count 2 2006.281.08:10:40.58#ibcon#about to read 5, iclass 40, count 2 2006.281.08:10:40.58#ibcon#read 5, iclass 40, count 2 2006.281.08:10:40.58#ibcon#about to read 6, iclass 40, count 2 2006.281.08:10:40.58#ibcon#read 6, iclass 40, count 2 2006.281.08:10:40.58#ibcon#end of sib2, iclass 40, count 2 2006.281.08:10:40.58#ibcon#*after write, iclass 40, count 2 2006.281.08:10:40.58#ibcon#*before return 0, iclass 40, count 2 2006.281.08:10:40.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:40.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:40.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:10:40.58#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:40.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:40.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:40.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:40.70#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:10:40.70#ibcon#first serial, iclass 40, count 0 2006.281.08:10:40.70#ibcon#enter sib2, iclass 40, count 0 2006.281.08:10:40.70#ibcon#flushed, iclass 40, count 0 2006.281.08:10:40.70#ibcon#about to write, iclass 40, count 0 2006.281.08:10:40.70#ibcon#wrote, iclass 40, count 0 2006.281.08:10:40.70#ibcon#about to read 3, iclass 40, count 0 2006.281.08:10:40.72#ibcon#read 3, iclass 40, count 0 2006.281.08:10:40.72#ibcon#about to read 4, iclass 40, count 0 2006.281.08:10:40.72#ibcon#read 4, iclass 40, count 0 2006.281.08:10:40.72#ibcon#about to read 5, iclass 40, count 0 2006.281.08:10:40.72#ibcon#read 5, iclass 40, count 0 2006.281.08:10:40.72#ibcon#about to read 6, iclass 40, count 0 2006.281.08:10:40.72#ibcon#read 6, iclass 40, count 0 2006.281.08:10:40.72#ibcon#end of sib2, iclass 40, count 0 2006.281.08:10:40.72#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:10:40.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:10:40.72#ibcon#[25=USB\r\n] 2006.281.08:10:40.72#ibcon#*before write, iclass 40, count 0 2006.281.08:10:40.72#ibcon#enter sib2, iclass 40, count 0 2006.281.08:10:40.72#ibcon#flushed, iclass 40, count 0 2006.281.08:10:40.72#ibcon#about to write, iclass 40, count 0 2006.281.08:10:40.72#ibcon#wrote, iclass 40, count 0 2006.281.08:10:40.72#ibcon#about to read 3, iclass 40, count 0 2006.281.08:10:40.75#ibcon#read 3, iclass 40, count 0 2006.281.08:10:40.75#ibcon#about to read 4, iclass 40, count 0 2006.281.08:10:40.75#ibcon#read 4, iclass 40, count 0 2006.281.08:10:40.75#ibcon#about to read 5, iclass 40, count 0 2006.281.08:10:40.75#ibcon#read 5, iclass 40, count 0 2006.281.08:10:40.75#ibcon#about to read 6, iclass 40, count 0 2006.281.08:10:40.75#ibcon#read 6, iclass 40, count 0 2006.281.08:10:40.75#ibcon#end of sib2, iclass 40, count 0 2006.281.08:10:40.75#ibcon#*after write, iclass 40, count 0 2006.281.08:10:40.75#ibcon#*before return 0, iclass 40, count 0 2006.281.08:10:40.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:40.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:40.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:10:40.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:10:40.76$vc4f8/valo=7,832.99 2006.281.08:10:40.76#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:10:40.76#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:10:40.76#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:40.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:40.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:40.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:40.76#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:10:40.76#ibcon#first serial, iclass 4, count 0 2006.281.08:10:40.76#ibcon#enter sib2, iclass 4, count 0 2006.281.08:10:40.76#ibcon#flushed, iclass 4, count 0 2006.281.08:10:40.76#ibcon#about to write, iclass 4, count 0 2006.281.08:10:40.76#ibcon#wrote, iclass 4, count 0 2006.281.08:10:40.76#ibcon#about to read 3, iclass 4, count 0 2006.281.08:10:40.77#ibcon#read 3, iclass 4, count 0 2006.281.08:10:40.77#ibcon#about to read 4, iclass 4, count 0 2006.281.08:10:40.77#ibcon#read 4, iclass 4, count 0 2006.281.08:10:40.77#ibcon#about to read 5, iclass 4, count 0 2006.281.08:10:40.77#ibcon#read 5, iclass 4, count 0 2006.281.08:10:40.77#ibcon#about to read 6, iclass 4, count 0 2006.281.08:10:40.77#ibcon#read 6, iclass 4, count 0 2006.281.08:10:40.77#ibcon#end of sib2, iclass 4, count 0 2006.281.08:10:40.77#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:10:40.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:10:40.77#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:10:40.77#ibcon#*before write, iclass 4, count 0 2006.281.08:10:40.77#ibcon#enter sib2, iclass 4, count 0 2006.281.08:10:40.77#ibcon#flushed, iclass 4, count 0 2006.281.08:10:40.77#ibcon#about to write, iclass 4, count 0 2006.281.08:10:40.77#ibcon#wrote, iclass 4, count 0 2006.281.08:10:40.77#ibcon#about to read 3, iclass 4, count 0 2006.281.08:10:40.81#ibcon#read 3, iclass 4, count 0 2006.281.08:10:40.81#ibcon#about to read 4, iclass 4, count 0 2006.281.08:10:40.81#ibcon#read 4, iclass 4, count 0 2006.281.08:10:40.81#ibcon#about to read 5, iclass 4, count 0 2006.281.08:10:40.81#ibcon#read 5, iclass 4, count 0 2006.281.08:10:40.81#ibcon#about to read 6, iclass 4, count 0 2006.281.08:10:40.81#ibcon#read 6, iclass 4, count 0 2006.281.08:10:40.81#ibcon#end of sib2, iclass 4, count 0 2006.281.08:10:40.81#ibcon#*after write, iclass 4, count 0 2006.281.08:10:40.81#ibcon#*before return 0, iclass 4, count 0 2006.281.08:10:40.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:40.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:40.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:10:40.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:10:40.82$vc4f8/va=7,6 2006.281.08:10:40.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.08:10:40.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.08:10:40.82#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:40.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:40.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:40.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:40.86#ibcon#enter wrdev, iclass 6, count 2 2006.281.08:10:40.86#ibcon#first serial, iclass 6, count 2 2006.281.08:10:40.86#ibcon#enter sib2, iclass 6, count 2 2006.281.08:10:40.86#ibcon#flushed, iclass 6, count 2 2006.281.08:10:40.86#ibcon#about to write, iclass 6, count 2 2006.281.08:10:40.86#ibcon#wrote, iclass 6, count 2 2006.281.08:10:40.86#ibcon#about to read 3, iclass 6, count 2 2006.281.08:10:40.88#ibcon#read 3, iclass 6, count 2 2006.281.08:10:40.88#ibcon#about to read 4, iclass 6, count 2 2006.281.08:10:40.88#ibcon#read 4, iclass 6, count 2 2006.281.08:10:40.88#ibcon#about to read 5, iclass 6, count 2 2006.281.08:10:40.88#ibcon#read 5, iclass 6, count 2 2006.281.08:10:40.88#ibcon#about to read 6, iclass 6, count 2 2006.281.08:10:40.88#ibcon#read 6, iclass 6, count 2 2006.281.08:10:40.88#ibcon#end of sib2, iclass 6, count 2 2006.281.08:10:40.88#ibcon#*mode == 0, iclass 6, count 2 2006.281.08:10:40.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.08:10:40.88#ibcon#[25=AT07-06\r\n] 2006.281.08:10:40.88#ibcon#*before write, iclass 6, count 2 2006.281.08:10:40.88#ibcon#enter sib2, iclass 6, count 2 2006.281.08:10:40.88#ibcon#flushed, iclass 6, count 2 2006.281.08:10:40.88#ibcon#about to write, iclass 6, count 2 2006.281.08:10:40.88#ibcon#wrote, iclass 6, count 2 2006.281.08:10:40.88#ibcon#about to read 3, iclass 6, count 2 2006.281.08:10:40.91#ibcon#read 3, iclass 6, count 2 2006.281.08:10:40.91#ibcon#about to read 4, iclass 6, count 2 2006.281.08:10:40.91#ibcon#read 4, iclass 6, count 2 2006.281.08:10:40.91#ibcon#about to read 5, iclass 6, count 2 2006.281.08:10:40.91#ibcon#read 5, iclass 6, count 2 2006.281.08:10:40.91#ibcon#about to read 6, iclass 6, count 2 2006.281.08:10:40.91#ibcon#read 6, iclass 6, count 2 2006.281.08:10:40.91#ibcon#end of sib2, iclass 6, count 2 2006.281.08:10:40.91#ibcon#*after write, iclass 6, count 2 2006.281.08:10:40.91#ibcon#*before return 0, iclass 6, count 2 2006.281.08:10:40.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:40.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:40.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.08:10:40.91#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:40.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:10:41.04#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:10:41.04#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:10:41.04#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:10:41.04#ibcon#first serial, iclass 6, count 0 2006.281.08:10:41.04#ibcon#enter sib2, iclass 6, count 0 2006.281.08:10:41.04#ibcon#flushed, iclass 6, count 0 2006.281.08:10:41.04#ibcon#about to write, iclass 6, count 0 2006.281.08:10:41.04#ibcon#wrote, iclass 6, count 0 2006.281.08:10:41.04#ibcon#about to read 3, iclass 6, count 0 2006.281.08:10:41.05#ibcon#read 3, iclass 6, count 0 2006.281.08:10:41.05#ibcon#about to read 4, iclass 6, count 0 2006.281.08:10:41.05#ibcon#read 4, iclass 6, count 0 2006.281.08:10:41.05#ibcon#about to read 5, iclass 6, count 0 2006.281.08:10:41.05#ibcon#read 5, iclass 6, count 0 2006.281.08:10:41.05#ibcon#about to read 6, iclass 6, count 0 2006.281.08:10:41.05#ibcon#read 6, iclass 6, count 0 2006.281.08:10:41.05#ibcon#end of sib2, iclass 6, count 0 2006.281.08:10:41.05#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:10:41.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:10:41.05#ibcon#[25=USB\r\n] 2006.281.08:10:41.05#ibcon#*before write, iclass 6, count 0 2006.281.08:10:41.05#ibcon#enter sib2, iclass 6, count 0 2006.281.08:10:41.05#ibcon#flushed, iclass 6, count 0 2006.281.08:10:41.05#ibcon#about to write, iclass 6, count 0 2006.281.08:10:41.06#ibcon#wrote, iclass 6, count 0 2006.281.08:10:41.06#ibcon#about to read 3, iclass 6, count 0 2006.281.08:10:41.08#ibcon#read 3, iclass 6, count 0 2006.281.08:10:41.08#ibcon#about to read 4, iclass 6, count 0 2006.281.08:10:41.08#ibcon#read 4, iclass 6, count 0 2006.281.08:10:41.08#ibcon#about to read 5, iclass 6, count 0 2006.281.08:10:41.08#ibcon#read 5, iclass 6, count 0 2006.281.08:10:41.08#ibcon#about to read 6, iclass 6, count 0 2006.281.08:10:41.08#ibcon#read 6, iclass 6, count 0 2006.281.08:10:41.08#ibcon#end of sib2, iclass 6, count 0 2006.281.08:10:41.08#ibcon#*after write, iclass 6, count 0 2006.281.08:10:41.08#ibcon#*before return 0, iclass 6, count 0 2006.281.08:10:41.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:10:41.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:10:41.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:10:41.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:10:41.09$vc4f8/valo=8,852.99 2006.281.08:10:41.09#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.08:10:41.09#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.08:10:41.09#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:41.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:10:41.09#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:10:41.09#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:10:41.09#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:10:41.09#ibcon#first serial, iclass 10, count 0 2006.281.08:10:41.09#ibcon#enter sib2, iclass 10, count 0 2006.281.08:10:41.09#ibcon#flushed, iclass 10, count 0 2006.281.08:10:41.09#ibcon#about to write, iclass 10, count 0 2006.281.08:10:41.09#ibcon#wrote, iclass 10, count 0 2006.281.08:10:41.09#ibcon#about to read 3, iclass 10, count 0 2006.281.08:10:41.10#ibcon#read 3, iclass 10, count 0 2006.281.08:10:41.11#ibcon#about to read 4, iclass 10, count 0 2006.281.08:10:41.11#ibcon#read 4, iclass 10, count 0 2006.281.08:10:41.11#ibcon#about to read 5, iclass 10, count 0 2006.281.08:10:41.11#ibcon#read 5, iclass 10, count 0 2006.281.08:10:41.11#ibcon#about to read 6, iclass 10, count 0 2006.281.08:10:41.11#ibcon#read 6, iclass 10, count 0 2006.281.08:10:41.11#ibcon#end of sib2, iclass 10, count 0 2006.281.08:10:41.11#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:10:41.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:10:41.11#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:10:41.11#ibcon#*before write, iclass 10, count 0 2006.281.08:10:41.11#ibcon#enter sib2, iclass 10, count 0 2006.281.08:10:41.11#ibcon#flushed, iclass 10, count 0 2006.281.08:10:41.11#ibcon#about to write, iclass 10, count 0 2006.281.08:10:41.11#ibcon#wrote, iclass 10, count 0 2006.281.08:10:41.11#ibcon#about to read 3, iclass 10, count 0 2006.281.08:10:41.15#ibcon#read 3, iclass 10, count 0 2006.281.08:10:41.15#ibcon#about to read 4, iclass 10, count 0 2006.281.08:10:41.15#ibcon#read 4, iclass 10, count 0 2006.281.08:10:41.15#ibcon#about to read 5, iclass 10, count 0 2006.281.08:10:41.15#ibcon#read 5, iclass 10, count 0 2006.281.08:10:41.15#ibcon#about to read 6, iclass 10, count 0 2006.281.08:10:41.15#ibcon#read 6, iclass 10, count 0 2006.281.08:10:41.15#ibcon#end of sib2, iclass 10, count 0 2006.281.08:10:41.15#ibcon#*after write, iclass 10, count 0 2006.281.08:10:41.15#ibcon#*before return 0, iclass 10, count 0 2006.281.08:10:41.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:10:41.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:10:41.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:10:41.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:10:41.15$vc4f8/va=8,6 2006.281.08:10:41.16#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.08:10:41.16#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.08:10:41.16#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:41.16#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:10:41.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:10:41.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:10:41.19#ibcon#enter wrdev, iclass 12, count 2 2006.281.08:10:41.19#ibcon#first serial, iclass 12, count 2 2006.281.08:10:41.19#ibcon#enter sib2, iclass 12, count 2 2006.281.08:10:41.19#ibcon#flushed, iclass 12, count 2 2006.281.08:10:41.19#ibcon#about to write, iclass 12, count 2 2006.281.08:10:41.19#ibcon#wrote, iclass 12, count 2 2006.281.08:10:41.19#ibcon#about to read 3, iclass 12, count 2 2006.281.08:10:41.21#ibcon#read 3, iclass 12, count 2 2006.281.08:10:41.21#ibcon#about to read 4, iclass 12, count 2 2006.281.08:10:41.21#ibcon#read 4, iclass 12, count 2 2006.281.08:10:41.21#ibcon#about to read 5, iclass 12, count 2 2006.281.08:10:41.21#ibcon#read 5, iclass 12, count 2 2006.281.08:10:41.21#ibcon#about to read 6, iclass 12, count 2 2006.281.08:10:41.21#ibcon#read 6, iclass 12, count 2 2006.281.08:10:41.21#ibcon#end of sib2, iclass 12, count 2 2006.281.08:10:41.21#ibcon#*mode == 0, iclass 12, count 2 2006.281.08:10:41.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.08:10:41.21#ibcon#[25=AT08-06\r\n] 2006.281.08:10:41.21#ibcon#*before write, iclass 12, count 2 2006.281.08:10:41.21#ibcon#enter sib2, iclass 12, count 2 2006.281.08:10:41.21#ibcon#flushed, iclass 12, count 2 2006.281.08:10:41.21#ibcon#about to write, iclass 12, count 2 2006.281.08:10:41.21#ibcon#wrote, iclass 12, count 2 2006.281.08:10:41.21#ibcon#about to read 3, iclass 12, count 2 2006.281.08:10:41.24#ibcon#read 3, iclass 12, count 2 2006.281.08:10:41.24#ibcon#about to read 4, iclass 12, count 2 2006.281.08:10:41.24#ibcon#read 4, iclass 12, count 2 2006.281.08:10:41.24#ibcon#about to read 5, iclass 12, count 2 2006.281.08:10:41.24#ibcon#read 5, iclass 12, count 2 2006.281.08:10:41.24#ibcon#about to read 6, iclass 12, count 2 2006.281.08:10:41.24#ibcon#read 6, iclass 12, count 2 2006.281.08:10:41.24#ibcon#end of sib2, iclass 12, count 2 2006.281.08:10:41.24#ibcon#*after write, iclass 12, count 2 2006.281.08:10:41.24#ibcon#*before return 0, iclass 12, count 2 2006.281.08:10:41.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:10:41.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:10:41.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.08:10:41.24#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:41.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:10:41.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:10:41.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:10:41.36#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:10:41.36#ibcon#first serial, iclass 12, count 0 2006.281.08:10:41.36#ibcon#enter sib2, iclass 12, count 0 2006.281.08:10:41.36#ibcon#flushed, iclass 12, count 0 2006.281.08:10:41.36#ibcon#about to write, iclass 12, count 0 2006.281.08:10:41.36#ibcon#wrote, iclass 12, count 0 2006.281.08:10:41.36#ibcon#about to read 3, iclass 12, count 0 2006.281.08:10:41.38#ibcon#read 3, iclass 12, count 0 2006.281.08:10:41.38#ibcon#about to read 4, iclass 12, count 0 2006.281.08:10:41.38#ibcon#read 4, iclass 12, count 0 2006.281.08:10:41.38#ibcon#about to read 5, iclass 12, count 0 2006.281.08:10:41.38#ibcon#read 5, iclass 12, count 0 2006.281.08:10:41.38#ibcon#about to read 6, iclass 12, count 0 2006.281.08:10:41.38#ibcon#read 6, iclass 12, count 0 2006.281.08:10:41.38#ibcon#end of sib2, iclass 12, count 0 2006.281.08:10:41.38#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:10:41.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:10:41.38#ibcon#[25=USB\r\n] 2006.281.08:10:41.38#ibcon#*before write, iclass 12, count 0 2006.281.08:10:41.38#ibcon#enter sib2, iclass 12, count 0 2006.281.08:10:41.38#ibcon#flushed, iclass 12, count 0 2006.281.08:10:41.38#ibcon#about to write, iclass 12, count 0 2006.281.08:10:41.38#ibcon#wrote, iclass 12, count 0 2006.281.08:10:41.38#ibcon#about to read 3, iclass 12, count 0 2006.281.08:10:41.41#ibcon#read 3, iclass 12, count 0 2006.281.08:10:41.41#ibcon#about to read 4, iclass 12, count 0 2006.281.08:10:41.41#ibcon#read 4, iclass 12, count 0 2006.281.08:10:41.41#ibcon#about to read 5, iclass 12, count 0 2006.281.08:10:41.41#ibcon#read 5, iclass 12, count 0 2006.281.08:10:41.41#ibcon#about to read 6, iclass 12, count 0 2006.281.08:10:41.41#ibcon#read 6, iclass 12, count 0 2006.281.08:10:41.41#ibcon#end of sib2, iclass 12, count 0 2006.281.08:10:41.41#ibcon#*after write, iclass 12, count 0 2006.281.08:10:41.41#ibcon#*before return 0, iclass 12, count 0 2006.281.08:10:41.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:10:41.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:10:41.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:10:41.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:10:41.42$vc4f8/vblo=1,632.99 2006.281.08:10:41.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:10:41.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:10:41.42#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:41.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:10:41.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:10:41.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:10:41.42#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:10:41.42#ibcon#first serial, iclass 14, count 0 2006.281.08:10:41.42#ibcon#enter sib2, iclass 14, count 0 2006.281.08:10:41.42#ibcon#flushed, iclass 14, count 0 2006.281.08:10:41.42#ibcon#about to write, iclass 14, count 0 2006.281.08:10:41.42#ibcon#wrote, iclass 14, count 0 2006.281.08:10:41.42#ibcon#about to read 3, iclass 14, count 0 2006.281.08:10:41.43#ibcon#read 3, iclass 14, count 0 2006.281.08:10:41.43#ibcon#about to read 4, iclass 14, count 0 2006.281.08:10:41.43#ibcon#read 4, iclass 14, count 0 2006.281.08:10:41.43#ibcon#about to read 5, iclass 14, count 0 2006.281.08:10:41.43#ibcon#read 5, iclass 14, count 0 2006.281.08:10:41.43#ibcon#about to read 6, iclass 14, count 0 2006.281.08:10:41.43#ibcon#read 6, iclass 14, count 0 2006.281.08:10:41.43#ibcon#end of sib2, iclass 14, count 0 2006.281.08:10:41.43#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:10:41.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:10:41.45#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:10:41.45#ibcon#*before write, iclass 14, count 0 2006.281.08:10:41.45#ibcon#enter sib2, iclass 14, count 0 2006.281.08:10:41.45#ibcon#flushed, iclass 14, count 0 2006.281.08:10:41.45#ibcon#about to write, iclass 14, count 0 2006.281.08:10:41.45#ibcon#wrote, iclass 14, count 0 2006.281.08:10:41.45#ibcon#about to read 3, iclass 14, count 0 2006.281.08:10:41.49#ibcon#read 3, iclass 14, count 0 2006.281.08:10:41.49#ibcon#about to read 4, iclass 14, count 0 2006.281.08:10:41.49#ibcon#read 4, iclass 14, count 0 2006.281.08:10:41.49#ibcon#about to read 5, iclass 14, count 0 2006.281.08:10:41.49#ibcon#read 5, iclass 14, count 0 2006.281.08:10:41.49#ibcon#about to read 6, iclass 14, count 0 2006.281.08:10:41.49#ibcon#read 6, iclass 14, count 0 2006.281.08:10:41.49#ibcon#end of sib2, iclass 14, count 0 2006.281.08:10:41.49#ibcon#*after write, iclass 14, count 0 2006.281.08:10:41.49#ibcon#*before return 0, iclass 14, count 0 2006.281.08:10:41.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:10:41.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:10:41.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:10:41.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:10:41.50$vc4f8/vb=1,4 2006.281.08:10:41.50#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.08:10:41.50#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.08:10:41.50#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:41.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:10:41.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:10:41.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:10:41.50#ibcon#enter wrdev, iclass 16, count 2 2006.281.08:10:41.50#ibcon#first serial, iclass 16, count 2 2006.281.08:10:41.50#ibcon#enter sib2, iclass 16, count 2 2006.281.08:10:41.50#ibcon#flushed, iclass 16, count 2 2006.281.08:10:41.50#ibcon#about to write, iclass 16, count 2 2006.281.08:10:41.50#ibcon#wrote, iclass 16, count 2 2006.281.08:10:41.50#ibcon#about to read 3, iclass 16, count 2 2006.281.08:10:41.51#ibcon#read 3, iclass 16, count 2 2006.281.08:10:41.51#ibcon#about to read 4, iclass 16, count 2 2006.281.08:10:41.51#ibcon#read 4, iclass 16, count 2 2006.281.08:10:41.51#ibcon#about to read 5, iclass 16, count 2 2006.281.08:10:41.51#ibcon#read 5, iclass 16, count 2 2006.281.08:10:41.51#ibcon#about to read 6, iclass 16, count 2 2006.281.08:10:41.51#ibcon#read 6, iclass 16, count 2 2006.281.08:10:41.51#ibcon#end of sib2, iclass 16, count 2 2006.281.08:10:41.51#ibcon#*mode == 0, iclass 16, count 2 2006.281.08:10:41.51#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.08:10:41.51#ibcon#[27=AT01-04\r\n] 2006.281.08:10:41.51#ibcon#*before write, iclass 16, count 2 2006.281.08:10:41.51#ibcon#enter sib2, iclass 16, count 2 2006.281.08:10:41.51#ibcon#flushed, iclass 16, count 2 2006.281.08:10:41.51#ibcon#about to write, iclass 16, count 2 2006.281.08:10:41.51#ibcon#wrote, iclass 16, count 2 2006.281.08:10:41.51#ibcon#about to read 3, iclass 16, count 2 2006.281.08:10:41.54#ibcon#read 3, iclass 16, count 2 2006.281.08:10:41.54#ibcon#about to read 4, iclass 16, count 2 2006.281.08:10:41.54#ibcon#read 4, iclass 16, count 2 2006.281.08:10:41.54#ibcon#about to read 5, iclass 16, count 2 2006.281.08:10:41.54#ibcon#read 5, iclass 16, count 2 2006.281.08:10:41.54#ibcon#about to read 6, iclass 16, count 2 2006.281.08:10:41.54#ibcon#read 6, iclass 16, count 2 2006.281.08:10:41.54#ibcon#end of sib2, iclass 16, count 2 2006.281.08:10:41.54#ibcon#*after write, iclass 16, count 2 2006.281.08:10:41.54#ibcon#*before return 0, iclass 16, count 2 2006.281.08:10:41.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:10:41.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:10:41.54#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.08:10:41.54#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:41.54#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:10:41.66#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:10:41.66#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:10:41.66#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:10:41.66#ibcon#first serial, iclass 16, count 0 2006.281.08:10:41.66#ibcon#enter sib2, iclass 16, count 0 2006.281.08:10:41.66#ibcon#flushed, iclass 16, count 0 2006.281.08:10:41.66#ibcon#about to write, iclass 16, count 0 2006.281.08:10:41.66#ibcon#wrote, iclass 16, count 0 2006.281.08:10:41.66#ibcon#about to read 3, iclass 16, count 0 2006.281.08:10:41.68#ibcon#read 3, iclass 16, count 0 2006.281.08:10:41.68#ibcon#about to read 4, iclass 16, count 0 2006.281.08:10:41.68#ibcon#read 4, iclass 16, count 0 2006.281.08:10:41.68#ibcon#about to read 5, iclass 16, count 0 2006.281.08:10:41.68#ibcon#read 5, iclass 16, count 0 2006.281.08:10:41.68#ibcon#about to read 6, iclass 16, count 0 2006.281.08:10:41.68#ibcon#read 6, iclass 16, count 0 2006.281.08:10:41.68#ibcon#end of sib2, iclass 16, count 0 2006.281.08:10:41.68#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:10:41.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:10:41.68#ibcon#[27=USB\r\n] 2006.281.08:10:41.68#ibcon#*before write, iclass 16, count 0 2006.281.08:10:41.68#ibcon#enter sib2, iclass 16, count 0 2006.281.08:10:41.68#ibcon#flushed, iclass 16, count 0 2006.281.08:10:41.68#ibcon#about to write, iclass 16, count 0 2006.281.08:10:41.68#ibcon#wrote, iclass 16, count 0 2006.281.08:10:41.68#ibcon#about to read 3, iclass 16, count 0 2006.281.08:10:41.72#ibcon#read 3, iclass 16, count 0 2006.281.08:10:41.72#ibcon#about to read 4, iclass 16, count 0 2006.281.08:10:41.72#ibcon#read 4, iclass 16, count 0 2006.281.08:10:41.72#ibcon#about to read 5, iclass 16, count 0 2006.281.08:10:41.72#ibcon#read 5, iclass 16, count 0 2006.281.08:10:41.72#ibcon#about to read 6, iclass 16, count 0 2006.281.08:10:41.72#ibcon#read 6, iclass 16, count 0 2006.281.08:10:41.72#ibcon#end of sib2, iclass 16, count 0 2006.281.08:10:41.72#ibcon#*after write, iclass 16, count 0 2006.281.08:10:41.72#ibcon#*before return 0, iclass 16, count 0 2006.281.08:10:41.72#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:10:41.72#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:10:41.72#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:10:41.72#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:10:41.72$vc4f8/vblo=2,640.99 2006.281.08:10:41.72#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.08:10:41.72#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.08:10:41.72#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:41.72#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:41.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:41.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:41.72#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:10:41.72#ibcon#first serial, iclass 18, count 0 2006.281.08:10:41.72#ibcon#enter sib2, iclass 18, count 0 2006.281.08:10:41.72#ibcon#flushed, iclass 18, count 0 2006.281.08:10:41.72#ibcon#about to write, iclass 18, count 0 2006.281.08:10:41.72#ibcon#wrote, iclass 18, count 0 2006.281.08:10:41.72#ibcon#about to read 3, iclass 18, count 0 2006.281.08:10:41.74#ibcon#read 3, iclass 18, count 0 2006.281.08:10:41.74#ibcon#about to read 4, iclass 18, count 0 2006.281.08:10:41.74#ibcon#read 4, iclass 18, count 0 2006.281.08:10:41.74#ibcon#about to read 5, iclass 18, count 0 2006.281.08:10:41.74#ibcon#read 5, iclass 18, count 0 2006.281.08:10:41.74#ibcon#about to read 6, iclass 18, count 0 2006.281.08:10:41.74#ibcon#read 6, iclass 18, count 0 2006.281.08:10:41.74#ibcon#end of sib2, iclass 18, count 0 2006.281.08:10:41.74#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:10:41.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:10:41.74#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:10:41.74#ibcon#*before write, iclass 18, count 0 2006.281.08:10:41.74#ibcon#enter sib2, iclass 18, count 0 2006.281.08:10:41.74#ibcon#flushed, iclass 18, count 0 2006.281.08:10:41.74#ibcon#about to write, iclass 18, count 0 2006.281.08:10:41.75#ibcon#wrote, iclass 18, count 0 2006.281.08:10:41.75#ibcon#about to read 3, iclass 18, count 0 2006.281.08:10:41.79#ibcon#read 3, iclass 18, count 0 2006.281.08:10:41.79#ibcon#about to read 4, iclass 18, count 0 2006.281.08:10:41.79#ibcon#read 4, iclass 18, count 0 2006.281.08:10:41.79#ibcon#about to read 5, iclass 18, count 0 2006.281.08:10:41.79#ibcon#read 5, iclass 18, count 0 2006.281.08:10:41.79#ibcon#about to read 6, iclass 18, count 0 2006.281.08:10:41.79#ibcon#read 6, iclass 18, count 0 2006.281.08:10:41.79#ibcon#end of sib2, iclass 18, count 0 2006.281.08:10:41.79#ibcon#*after write, iclass 18, count 0 2006.281.08:10:41.79#ibcon#*before return 0, iclass 18, count 0 2006.281.08:10:41.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:41.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:10:41.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:10:41.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:10:41.80$vc4f8/vb=2,5 2006.281.08:10:41.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.08:10:41.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.08:10:41.80#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:41.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:41.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:41.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:41.83#ibcon#enter wrdev, iclass 20, count 2 2006.281.08:10:41.83#ibcon#first serial, iclass 20, count 2 2006.281.08:10:41.83#ibcon#enter sib2, iclass 20, count 2 2006.281.08:10:41.83#ibcon#flushed, iclass 20, count 2 2006.281.08:10:41.83#ibcon#about to write, iclass 20, count 2 2006.281.08:10:41.83#ibcon#wrote, iclass 20, count 2 2006.281.08:10:41.83#ibcon#about to read 3, iclass 20, count 2 2006.281.08:10:41.85#ibcon#read 3, iclass 20, count 2 2006.281.08:10:41.85#ibcon#about to read 4, iclass 20, count 2 2006.281.08:10:41.85#ibcon#read 4, iclass 20, count 2 2006.281.08:10:41.85#ibcon#about to read 5, iclass 20, count 2 2006.281.08:10:41.85#ibcon#read 5, iclass 20, count 2 2006.281.08:10:41.85#ibcon#about to read 6, iclass 20, count 2 2006.281.08:10:41.85#ibcon#read 6, iclass 20, count 2 2006.281.08:10:41.85#ibcon#end of sib2, iclass 20, count 2 2006.281.08:10:41.85#ibcon#*mode == 0, iclass 20, count 2 2006.281.08:10:41.85#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.08:10:41.85#ibcon#[27=AT02-05\r\n] 2006.281.08:10:41.85#ibcon#*before write, iclass 20, count 2 2006.281.08:10:41.85#ibcon#enter sib2, iclass 20, count 2 2006.281.08:10:41.85#ibcon#flushed, iclass 20, count 2 2006.281.08:10:41.85#ibcon#about to write, iclass 20, count 2 2006.281.08:10:41.85#ibcon#wrote, iclass 20, count 2 2006.281.08:10:41.85#ibcon#about to read 3, iclass 20, count 2 2006.281.08:10:41.88#ibcon#read 3, iclass 20, count 2 2006.281.08:10:41.88#ibcon#about to read 4, iclass 20, count 2 2006.281.08:10:41.88#ibcon#read 4, iclass 20, count 2 2006.281.08:10:41.88#ibcon#about to read 5, iclass 20, count 2 2006.281.08:10:41.88#ibcon#read 5, iclass 20, count 2 2006.281.08:10:41.88#ibcon#about to read 6, iclass 20, count 2 2006.281.08:10:41.88#ibcon#read 6, iclass 20, count 2 2006.281.08:10:41.88#ibcon#end of sib2, iclass 20, count 2 2006.281.08:10:41.88#ibcon#*after write, iclass 20, count 2 2006.281.08:10:41.88#ibcon#*before return 0, iclass 20, count 2 2006.281.08:10:41.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:41.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:10:41.88#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.08:10:41.88#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:41.88#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:42.01#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:42.01#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:42.01#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:10:42.01#ibcon#first serial, iclass 20, count 0 2006.281.08:10:42.01#ibcon#enter sib2, iclass 20, count 0 2006.281.08:10:42.01#ibcon#flushed, iclass 20, count 0 2006.281.08:10:42.01#ibcon#about to write, iclass 20, count 0 2006.281.08:10:42.01#ibcon#wrote, iclass 20, count 0 2006.281.08:10:42.01#ibcon#about to read 3, iclass 20, count 0 2006.281.08:10:42.02#ibcon#read 3, iclass 20, count 0 2006.281.08:10:42.02#ibcon#about to read 4, iclass 20, count 0 2006.281.08:10:42.02#ibcon#read 4, iclass 20, count 0 2006.281.08:10:42.02#ibcon#about to read 5, iclass 20, count 0 2006.281.08:10:42.02#ibcon#read 5, iclass 20, count 0 2006.281.08:10:42.02#ibcon#about to read 6, iclass 20, count 0 2006.281.08:10:42.02#ibcon#read 6, iclass 20, count 0 2006.281.08:10:42.02#ibcon#end of sib2, iclass 20, count 0 2006.281.08:10:42.02#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:10:42.02#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:10:42.02#ibcon#[27=USB\r\n] 2006.281.08:10:42.02#ibcon#*before write, iclass 20, count 0 2006.281.08:10:42.02#ibcon#enter sib2, iclass 20, count 0 2006.281.08:10:42.02#ibcon#flushed, iclass 20, count 0 2006.281.08:10:42.02#ibcon#about to write, iclass 20, count 0 2006.281.08:10:42.03#ibcon#wrote, iclass 20, count 0 2006.281.08:10:42.03#ibcon#about to read 3, iclass 20, count 0 2006.281.08:10:42.05#ibcon#read 3, iclass 20, count 0 2006.281.08:10:42.05#ibcon#about to read 4, iclass 20, count 0 2006.281.08:10:42.05#ibcon#read 4, iclass 20, count 0 2006.281.08:10:42.05#ibcon#about to read 5, iclass 20, count 0 2006.281.08:10:42.05#ibcon#read 5, iclass 20, count 0 2006.281.08:10:42.05#ibcon#about to read 6, iclass 20, count 0 2006.281.08:10:42.05#ibcon#read 6, iclass 20, count 0 2006.281.08:10:42.05#ibcon#end of sib2, iclass 20, count 0 2006.281.08:10:42.05#ibcon#*after write, iclass 20, count 0 2006.281.08:10:42.05#ibcon#*before return 0, iclass 20, count 0 2006.281.08:10:42.05#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:42.05#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:10:42.05#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:10:42.05#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:10:42.06$vc4f8/vblo=3,656.99 2006.281.08:10:42.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.08:10:42.06#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.08:10:42.06#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:42.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:42.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:42.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:42.06#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:10:42.06#ibcon#first serial, iclass 22, count 0 2006.281.08:10:42.06#ibcon#enter sib2, iclass 22, count 0 2006.281.08:10:42.06#ibcon#flushed, iclass 22, count 0 2006.281.08:10:42.06#ibcon#about to write, iclass 22, count 0 2006.281.08:10:42.06#ibcon#wrote, iclass 22, count 0 2006.281.08:10:42.06#ibcon#about to read 3, iclass 22, count 0 2006.281.08:10:42.07#ibcon#read 3, iclass 22, count 0 2006.281.08:10:42.07#ibcon#about to read 4, iclass 22, count 0 2006.281.08:10:42.07#ibcon#read 4, iclass 22, count 0 2006.281.08:10:42.07#ibcon#about to read 5, iclass 22, count 0 2006.281.08:10:42.07#ibcon#read 5, iclass 22, count 0 2006.281.08:10:42.07#ibcon#about to read 6, iclass 22, count 0 2006.281.08:10:42.07#ibcon#read 6, iclass 22, count 0 2006.281.08:10:42.07#ibcon#end of sib2, iclass 22, count 0 2006.281.08:10:42.07#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:10:42.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:10:42.07#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:10:42.07#ibcon#*before write, iclass 22, count 0 2006.281.08:10:42.07#ibcon#enter sib2, iclass 22, count 0 2006.281.08:10:42.07#ibcon#flushed, iclass 22, count 0 2006.281.08:10:42.07#ibcon#about to write, iclass 22, count 0 2006.281.08:10:42.07#ibcon#wrote, iclass 22, count 0 2006.281.08:10:42.07#ibcon#about to read 3, iclass 22, count 0 2006.281.08:10:42.12#ibcon#read 3, iclass 22, count 0 2006.281.08:10:42.12#ibcon#about to read 4, iclass 22, count 0 2006.281.08:10:42.12#ibcon#read 4, iclass 22, count 0 2006.281.08:10:42.12#ibcon#about to read 5, iclass 22, count 0 2006.281.08:10:42.12#ibcon#read 5, iclass 22, count 0 2006.281.08:10:42.12#ibcon#about to read 6, iclass 22, count 0 2006.281.08:10:42.12#ibcon#read 6, iclass 22, count 0 2006.281.08:10:42.12#ibcon#end of sib2, iclass 22, count 0 2006.281.08:10:42.12#ibcon#*after write, iclass 22, count 0 2006.281.08:10:42.12#ibcon#*before return 0, iclass 22, count 0 2006.281.08:10:42.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:42.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:10:42.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:10:42.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:10:42.12$vc4f8/vb=3,4 2006.281.08:10:42.12#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.08:10:42.12#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.08:10:42.12#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:42.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:42.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:42.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:42.16#ibcon#enter wrdev, iclass 24, count 2 2006.281.08:10:42.16#ibcon#first serial, iclass 24, count 2 2006.281.08:10:42.16#ibcon#enter sib2, iclass 24, count 2 2006.281.08:10:42.16#ibcon#flushed, iclass 24, count 2 2006.281.08:10:42.16#ibcon#about to write, iclass 24, count 2 2006.281.08:10:42.16#ibcon#wrote, iclass 24, count 2 2006.281.08:10:42.16#ibcon#about to read 3, iclass 24, count 2 2006.281.08:10:42.18#ibcon#read 3, iclass 24, count 2 2006.281.08:10:42.18#ibcon#about to read 4, iclass 24, count 2 2006.281.08:10:42.18#ibcon#read 4, iclass 24, count 2 2006.281.08:10:42.18#ibcon#about to read 5, iclass 24, count 2 2006.281.08:10:42.18#ibcon#read 5, iclass 24, count 2 2006.281.08:10:42.18#ibcon#about to read 6, iclass 24, count 2 2006.281.08:10:42.18#ibcon#read 6, iclass 24, count 2 2006.281.08:10:42.18#ibcon#end of sib2, iclass 24, count 2 2006.281.08:10:42.18#ibcon#*mode == 0, iclass 24, count 2 2006.281.08:10:42.18#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.08:10:42.18#ibcon#[27=AT03-04\r\n] 2006.281.08:10:42.18#ibcon#*before write, iclass 24, count 2 2006.281.08:10:42.18#ibcon#enter sib2, iclass 24, count 2 2006.281.08:10:42.18#ibcon#flushed, iclass 24, count 2 2006.281.08:10:42.18#ibcon#about to write, iclass 24, count 2 2006.281.08:10:42.18#ibcon#wrote, iclass 24, count 2 2006.281.08:10:42.18#ibcon#about to read 3, iclass 24, count 2 2006.281.08:10:42.22#ibcon#read 3, iclass 24, count 2 2006.281.08:10:42.22#ibcon#about to read 4, iclass 24, count 2 2006.281.08:10:42.22#ibcon#read 4, iclass 24, count 2 2006.281.08:10:42.22#ibcon#about to read 5, iclass 24, count 2 2006.281.08:10:42.22#ibcon#read 5, iclass 24, count 2 2006.281.08:10:42.22#ibcon#about to read 6, iclass 24, count 2 2006.281.08:10:42.22#ibcon#read 6, iclass 24, count 2 2006.281.08:10:42.22#ibcon#end of sib2, iclass 24, count 2 2006.281.08:10:42.22#ibcon#*after write, iclass 24, count 2 2006.281.08:10:42.22#ibcon#*before return 0, iclass 24, count 2 2006.281.08:10:42.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:42.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:10:42.22#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.08:10:42.22#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:42.22#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:42.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:42.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:42.33#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:10:42.33#ibcon#first serial, iclass 24, count 0 2006.281.08:10:42.33#ibcon#enter sib2, iclass 24, count 0 2006.281.08:10:42.33#ibcon#flushed, iclass 24, count 0 2006.281.08:10:42.33#ibcon#about to write, iclass 24, count 0 2006.281.08:10:42.33#ibcon#wrote, iclass 24, count 0 2006.281.08:10:42.33#ibcon#about to read 3, iclass 24, count 0 2006.281.08:10:42.35#ibcon#read 3, iclass 24, count 0 2006.281.08:10:42.35#ibcon#about to read 4, iclass 24, count 0 2006.281.08:10:42.35#ibcon#read 4, iclass 24, count 0 2006.281.08:10:42.35#ibcon#about to read 5, iclass 24, count 0 2006.281.08:10:42.35#ibcon#read 5, iclass 24, count 0 2006.281.08:10:42.35#ibcon#about to read 6, iclass 24, count 0 2006.281.08:10:42.35#ibcon#read 6, iclass 24, count 0 2006.281.08:10:42.35#ibcon#end of sib2, iclass 24, count 0 2006.281.08:10:42.35#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:10:42.35#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:10:42.35#ibcon#[27=USB\r\n] 2006.281.08:10:42.35#ibcon#*before write, iclass 24, count 0 2006.281.08:10:42.35#ibcon#enter sib2, iclass 24, count 0 2006.281.08:10:42.35#ibcon#flushed, iclass 24, count 0 2006.281.08:10:42.35#ibcon#about to write, iclass 24, count 0 2006.281.08:10:42.35#ibcon#wrote, iclass 24, count 0 2006.281.08:10:42.35#ibcon#about to read 3, iclass 24, count 0 2006.281.08:10:42.38#ibcon#read 3, iclass 24, count 0 2006.281.08:10:42.38#ibcon#about to read 4, iclass 24, count 0 2006.281.08:10:42.38#ibcon#read 4, iclass 24, count 0 2006.281.08:10:42.38#ibcon#about to read 5, iclass 24, count 0 2006.281.08:10:42.38#ibcon#read 5, iclass 24, count 0 2006.281.08:10:42.38#ibcon#about to read 6, iclass 24, count 0 2006.281.08:10:42.38#ibcon#read 6, iclass 24, count 0 2006.281.08:10:42.38#ibcon#end of sib2, iclass 24, count 0 2006.281.08:10:42.38#ibcon#*after write, iclass 24, count 0 2006.281.08:10:42.38#ibcon#*before return 0, iclass 24, count 0 2006.281.08:10:42.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:42.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:10:42.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:10:42.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:10:42.39$vc4f8/vblo=4,712.99 2006.281.08:10:42.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.08:10:42.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.08:10:42.39#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:42.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:42.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:42.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:42.39#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:10:42.39#ibcon#first serial, iclass 26, count 0 2006.281.08:10:42.39#ibcon#enter sib2, iclass 26, count 0 2006.281.08:10:42.39#ibcon#flushed, iclass 26, count 0 2006.281.08:10:42.39#ibcon#about to write, iclass 26, count 0 2006.281.08:10:42.39#ibcon#wrote, iclass 26, count 0 2006.281.08:10:42.39#ibcon#about to read 3, iclass 26, count 0 2006.281.08:10:42.40#ibcon#read 3, iclass 26, count 0 2006.281.08:10:42.40#ibcon#about to read 4, iclass 26, count 0 2006.281.08:10:42.40#ibcon#read 4, iclass 26, count 0 2006.281.08:10:42.40#ibcon#about to read 5, iclass 26, count 0 2006.281.08:10:42.40#ibcon#read 5, iclass 26, count 0 2006.281.08:10:42.40#ibcon#about to read 6, iclass 26, count 0 2006.281.08:10:42.40#ibcon#read 6, iclass 26, count 0 2006.281.08:10:42.40#ibcon#end of sib2, iclass 26, count 0 2006.281.08:10:42.40#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:10:42.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:10:42.40#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:10:42.40#ibcon#*before write, iclass 26, count 0 2006.281.08:10:42.40#ibcon#enter sib2, iclass 26, count 0 2006.281.08:10:42.40#ibcon#flushed, iclass 26, count 0 2006.281.08:10:42.40#ibcon#about to write, iclass 26, count 0 2006.281.08:10:42.40#ibcon#wrote, iclass 26, count 0 2006.281.08:10:42.40#ibcon#about to read 3, iclass 26, count 0 2006.281.08:10:42.44#ibcon#read 3, iclass 26, count 0 2006.281.08:10:42.44#ibcon#about to read 4, iclass 26, count 0 2006.281.08:10:42.44#ibcon#read 4, iclass 26, count 0 2006.281.08:10:42.44#ibcon#about to read 5, iclass 26, count 0 2006.281.08:10:42.44#ibcon#read 5, iclass 26, count 0 2006.281.08:10:42.44#ibcon#about to read 6, iclass 26, count 0 2006.281.08:10:42.44#ibcon#read 6, iclass 26, count 0 2006.281.08:10:42.44#ibcon#end of sib2, iclass 26, count 0 2006.281.08:10:42.44#ibcon#*after write, iclass 26, count 0 2006.281.08:10:42.44#ibcon#*before return 0, iclass 26, count 0 2006.281.08:10:42.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:42.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:10:42.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:10:42.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:10:42.45$vc4f8/vb=4,4 2006.281.08:10:42.46#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.08:10:42.46#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.08:10:42.46#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:42.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:42.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:42.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:42.49#ibcon#enter wrdev, iclass 28, count 2 2006.281.08:10:42.49#ibcon#first serial, iclass 28, count 2 2006.281.08:10:42.49#ibcon#enter sib2, iclass 28, count 2 2006.281.08:10:42.49#ibcon#flushed, iclass 28, count 2 2006.281.08:10:42.49#ibcon#about to write, iclass 28, count 2 2006.281.08:10:42.49#ibcon#wrote, iclass 28, count 2 2006.281.08:10:42.49#ibcon#about to read 3, iclass 28, count 2 2006.281.08:10:42.51#ibcon#read 3, iclass 28, count 2 2006.281.08:10:42.51#ibcon#about to read 4, iclass 28, count 2 2006.281.08:10:42.51#ibcon#read 4, iclass 28, count 2 2006.281.08:10:42.51#ibcon#about to read 5, iclass 28, count 2 2006.281.08:10:42.51#ibcon#read 5, iclass 28, count 2 2006.281.08:10:42.51#ibcon#about to read 6, iclass 28, count 2 2006.281.08:10:42.51#ibcon#read 6, iclass 28, count 2 2006.281.08:10:42.51#ibcon#end of sib2, iclass 28, count 2 2006.281.08:10:42.51#ibcon#*mode == 0, iclass 28, count 2 2006.281.08:10:42.51#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.08:10:42.51#ibcon#[27=AT04-04\r\n] 2006.281.08:10:42.51#ibcon#*before write, iclass 28, count 2 2006.281.08:10:42.51#ibcon#enter sib2, iclass 28, count 2 2006.281.08:10:42.51#ibcon#flushed, iclass 28, count 2 2006.281.08:10:42.51#ibcon#about to write, iclass 28, count 2 2006.281.08:10:42.51#ibcon#wrote, iclass 28, count 2 2006.281.08:10:42.51#ibcon#about to read 3, iclass 28, count 2 2006.281.08:10:42.54#ibcon#read 3, iclass 28, count 2 2006.281.08:10:42.54#ibcon#about to read 4, iclass 28, count 2 2006.281.08:10:42.54#ibcon#read 4, iclass 28, count 2 2006.281.08:10:42.54#ibcon#about to read 5, iclass 28, count 2 2006.281.08:10:42.54#ibcon#read 5, iclass 28, count 2 2006.281.08:10:42.54#ibcon#about to read 6, iclass 28, count 2 2006.281.08:10:42.54#ibcon#read 6, iclass 28, count 2 2006.281.08:10:42.54#ibcon#end of sib2, iclass 28, count 2 2006.281.08:10:42.54#ibcon#*after write, iclass 28, count 2 2006.281.08:10:42.54#ibcon#*before return 0, iclass 28, count 2 2006.281.08:10:42.54#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:42.54#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:10:42.54#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.08:10:42.54#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:42.54#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:42.66#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:42.66#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:42.66#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:10:42.66#ibcon#first serial, iclass 28, count 0 2006.281.08:10:42.66#ibcon#enter sib2, iclass 28, count 0 2006.281.08:10:42.66#ibcon#flushed, iclass 28, count 0 2006.281.08:10:42.66#ibcon#about to write, iclass 28, count 0 2006.281.08:10:42.66#ibcon#wrote, iclass 28, count 0 2006.281.08:10:42.66#ibcon#about to read 3, iclass 28, count 0 2006.281.08:10:42.68#ibcon#read 3, iclass 28, count 0 2006.281.08:10:42.68#ibcon#about to read 4, iclass 28, count 0 2006.281.08:10:42.68#ibcon#read 4, iclass 28, count 0 2006.281.08:10:42.68#ibcon#about to read 5, iclass 28, count 0 2006.281.08:10:42.68#ibcon#read 5, iclass 28, count 0 2006.281.08:10:42.68#ibcon#about to read 6, iclass 28, count 0 2006.281.08:10:42.68#ibcon#read 6, iclass 28, count 0 2006.281.08:10:42.68#ibcon#end of sib2, iclass 28, count 0 2006.281.08:10:42.68#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:10:42.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:10:42.68#ibcon#[27=USB\r\n] 2006.281.08:10:42.68#ibcon#*before write, iclass 28, count 0 2006.281.08:10:42.68#ibcon#enter sib2, iclass 28, count 0 2006.281.08:10:42.68#ibcon#flushed, iclass 28, count 0 2006.281.08:10:42.68#ibcon#about to write, iclass 28, count 0 2006.281.08:10:42.69#ibcon#wrote, iclass 28, count 0 2006.281.08:10:42.69#ibcon#about to read 3, iclass 28, count 0 2006.281.08:10:42.71#ibcon#read 3, iclass 28, count 0 2006.281.08:10:42.71#ibcon#about to read 4, iclass 28, count 0 2006.281.08:10:42.71#ibcon#read 4, iclass 28, count 0 2006.281.08:10:42.71#ibcon#about to read 5, iclass 28, count 0 2006.281.08:10:42.71#ibcon#read 5, iclass 28, count 0 2006.281.08:10:42.71#ibcon#about to read 6, iclass 28, count 0 2006.281.08:10:42.71#ibcon#read 6, iclass 28, count 0 2006.281.08:10:42.71#ibcon#end of sib2, iclass 28, count 0 2006.281.08:10:42.71#ibcon#*after write, iclass 28, count 0 2006.281.08:10:42.71#ibcon#*before return 0, iclass 28, count 0 2006.281.08:10:42.71#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:42.71#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:10:42.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:10:42.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:10:42.72$vc4f8/vblo=5,744.99 2006.281.08:10:42.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:10:42.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:10:42.72#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:42.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:10:42.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:10:42.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:10:42.72#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:10:42.72#ibcon#first serial, iclass 31, count 0 2006.281.08:10:42.72#ibcon#enter sib2, iclass 31, count 0 2006.281.08:10:42.72#ibcon#flushed, iclass 31, count 0 2006.281.08:10:42.72#ibcon#about to write, iclass 31, count 0 2006.281.08:10:42.72#ibcon#wrote, iclass 31, count 0 2006.281.08:10:42.72#ibcon#about to read 3, iclass 31, count 0 2006.281.08:10:42.73#abcon#<5=/13 2.0 7.8 20.20 521001.6\r\n> 2006.281.08:10:42.74#ibcon#read 3, iclass 31, count 0 2006.281.08:10:42.75#ibcon#about to read 4, iclass 31, count 0 2006.281.08:10:42.75#ibcon#read 4, iclass 31, count 0 2006.281.08:10:42.75#ibcon#about to read 5, iclass 31, count 0 2006.281.08:10:42.75#ibcon#read 5, iclass 31, count 0 2006.281.08:10:42.75#ibcon#about to read 6, iclass 31, count 0 2006.281.08:10:42.75#ibcon#read 6, iclass 31, count 0 2006.281.08:10:42.75#ibcon#end of sib2, iclass 31, count 0 2006.281.08:10:42.75#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:10:42.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:10:42.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:10:42.75#ibcon#*before write, iclass 31, count 0 2006.281.08:10:42.75#ibcon#enter sib2, iclass 31, count 0 2006.281.08:10:42.75#ibcon#flushed, iclass 31, count 0 2006.281.08:10:42.75#ibcon#about to write, iclass 31, count 0 2006.281.08:10:42.75#ibcon#wrote, iclass 31, count 0 2006.281.08:10:42.75#ibcon#about to read 3, iclass 31, count 0 2006.281.08:10:42.74#abcon#{5=INTERFACE CLEAR} 2006.281.08:10:42.78#ibcon#read 3, iclass 31, count 0 2006.281.08:10:42.78#ibcon#about to read 4, iclass 31, count 0 2006.281.08:10:42.78#ibcon#read 4, iclass 31, count 0 2006.281.08:10:42.78#ibcon#about to read 5, iclass 31, count 0 2006.281.08:10:42.78#ibcon#read 5, iclass 31, count 0 2006.281.08:10:42.78#ibcon#about to read 6, iclass 31, count 0 2006.281.08:10:42.78#ibcon#read 6, iclass 31, count 0 2006.281.08:10:42.78#ibcon#end of sib2, iclass 31, count 0 2006.281.08:10:42.78#ibcon#*after write, iclass 31, count 0 2006.281.08:10:42.78#ibcon#*before return 0, iclass 31, count 0 2006.281.08:10:42.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:10:42.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:10:42.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:10:42.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:10:42.79$vc4f8/vb=5,4 2006.281.08:10:42.79#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:10:42.79#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:10:42.79#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:42.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:10:42.80#abcon#[5=S1D000X0/0*\r\n] 2006.281.08:10:42.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:10:42.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:10:42.83#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:10:42.83#ibcon#first serial, iclass 35, count 2 2006.281.08:10:42.83#ibcon#enter sib2, iclass 35, count 2 2006.281.08:10:42.83#ibcon#flushed, iclass 35, count 2 2006.281.08:10:42.83#ibcon#about to write, iclass 35, count 2 2006.281.08:10:42.83#ibcon#wrote, iclass 35, count 2 2006.281.08:10:42.83#ibcon#about to read 3, iclass 35, count 2 2006.281.08:10:42.84#ibcon#read 3, iclass 35, count 2 2006.281.08:10:42.84#ibcon#about to read 4, iclass 35, count 2 2006.281.08:10:42.84#ibcon#read 4, iclass 35, count 2 2006.281.08:10:42.84#ibcon#about to read 5, iclass 35, count 2 2006.281.08:10:42.84#ibcon#read 5, iclass 35, count 2 2006.281.08:10:42.84#ibcon#about to read 6, iclass 35, count 2 2006.281.08:10:42.84#ibcon#read 6, iclass 35, count 2 2006.281.08:10:42.84#ibcon#end of sib2, iclass 35, count 2 2006.281.08:10:42.84#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:10:42.84#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:10:42.84#ibcon#[27=AT05-04\r\n] 2006.281.08:10:42.84#ibcon#*before write, iclass 35, count 2 2006.281.08:10:42.84#ibcon#enter sib2, iclass 35, count 2 2006.281.08:10:42.84#ibcon#flushed, iclass 35, count 2 2006.281.08:10:42.84#ibcon#about to write, iclass 35, count 2 2006.281.08:10:42.84#ibcon#wrote, iclass 35, count 2 2006.281.08:10:42.84#ibcon#about to read 3, iclass 35, count 2 2006.281.08:10:42.87#ibcon#read 3, iclass 35, count 2 2006.281.08:10:42.87#ibcon#about to read 4, iclass 35, count 2 2006.281.08:10:42.87#ibcon#read 4, iclass 35, count 2 2006.281.08:10:42.87#ibcon#about to read 5, iclass 35, count 2 2006.281.08:10:42.87#ibcon#read 5, iclass 35, count 2 2006.281.08:10:42.87#ibcon#about to read 6, iclass 35, count 2 2006.281.08:10:42.87#ibcon#read 6, iclass 35, count 2 2006.281.08:10:42.87#ibcon#end of sib2, iclass 35, count 2 2006.281.08:10:42.87#ibcon#*after write, iclass 35, count 2 2006.281.08:10:42.87#ibcon#*before return 0, iclass 35, count 2 2006.281.08:10:42.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:10:42.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:10:42.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:10:42.87#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:42.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:10:42.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:10:42.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:10:42.99#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:10:42.99#ibcon#first serial, iclass 35, count 0 2006.281.08:10:42.99#ibcon#enter sib2, iclass 35, count 0 2006.281.08:10:42.99#ibcon#flushed, iclass 35, count 0 2006.281.08:10:42.99#ibcon#about to write, iclass 35, count 0 2006.281.08:10:42.99#ibcon#wrote, iclass 35, count 0 2006.281.08:10:42.99#ibcon#about to read 3, iclass 35, count 0 2006.281.08:10:43.01#ibcon#read 3, iclass 35, count 0 2006.281.08:10:43.01#ibcon#about to read 4, iclass 35, count 0 2006.281.08:10:43.01#ibcon#read 4, iclass 35, count 0 2006.281.08:10:43.01#ibcon#about to read 5, iclass 35, count 0 2006.281.08:10:43.01#ibcon#read 5, iclass 35, count 0 2006.281.08:10:43.01#ibcon#about to read 6, iclass 35, count 0 2006.281.08:10:43.01#ibcon#read 6, iclass 35, count 0 2006.281.08:10:43.01#ibcon#end of sib2, iclass 35, count 0 2006.281.08:10:43.01#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:10:43.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:10:43.01#ibcon#[27=USB\r\n] 2006.281.08:10:43.01#ibcon#*before write, iclass 35, count 0 2006.281.08:10:43.01#ibcon#enter sib2, iclass 35, count 0 2006.281.08:10:43.01#ibcon#flushed, iclass 35, count 0 2006.281.08:10:43.01#ibcon#about to write, iclass 35, count 0 2006.281.08:10:43.01#ibcon#wrote, iclass 35, count 0 2006.281.08:10:43.01#ibcon#about to read 3, iclass 35, count 0 2006.281.08:10:43.04#ibcon#read 3, iclass 35, count 0 2006.281.08:10:43.04#ibcon#about to read 4, iclass 35, count 0 2006.281.08:10:43.04#ibcon#read 4, iclass 35, count 0 2006.281.08:10:43.04#ibcon#about to read 5, iclass 35, count 0 2006.281.08:10:43.04#ibcon#read 5, iclass 35, count 0 2006.281.08:10:43.04#ibcon#about to read 6, iclass 35, count 0 2006.281.08:10:43.04#ibcon#read 6, iclass 35, count 0 2006.281.08:10:43.04#ibcon#end of sib2, iclass 35, count 0 2006.281.08:10:43.04#ibcon#*after write, iclass 35, count 0 2006.281.08:10:43.04#ibcon#*before return 0, iclass 35, count 0 2006.281.08:10:43.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:10:43.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:10:43.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:10:43.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:10:43.05$vc4f8/vblo=6,752.99 2006.281.08:10:43.05#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:10:43.05#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:10:43.05#ibcon#ireg 17 cls_cnt 0 2006.281.08:10:43.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:43.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:43.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:43.05#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:10:43.05#ibcon#first serial, iclass 38, count 0 2006.281.08:10:43.05#ibcon#enter sib2, iclass 38, count 0 2006.281.08:10:43.05#ibcon#flushed, iclass 38, count 0 2006.281.08:10:43.05#ibcon#about to write, iclass 38, count 0 2006.281.08:10:43.05#ibcon#wrote, iclass 38, count 0 2006.281.08:10:43.05#ibcon#about to read 3, iclass 38, count 0 2006.281.08:10:43.06#ibcon#read 3, iclass 38, count 0 2006.281.08:10:43.06#ibcon#about to read 4, iclass 38, count 0 2006.281.08:10:43.06#ibcon#read 4, iclass 38, count 0 2006.281.08:10:43.06#ibcon#about to read 5, iclass 38, count 0 2006.281.08:10:43.06#ibcon#read 5, iclass 38, count 0 2006.281.08:10:43.06#ibcon#about to read 6, iclass 38, count 0 2006.281.08:10:43.06#ibcon#read 6, iclass 38, count 0 2006.281.08:10:43.06#ibcon#end of sib2, iclass 38, count 0 2006.281.08:10:43.06#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:10:43.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:10:43.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:10:43.06#ibcon#*before write, iclass 38, count 0 2006.281.08:10:43.06#ibcon#enter sib2, iclass 38, count 0 2006.281.08:10:43.06#ibcon#flushed, iclass 38, count 0 2006.281.08:10:43.06#ibcon#about to write, iclass 38, count 0 2006.281.08:10:43.06#ibcon#wrote, iclass 38, count 0 2006.281.08:10:43.06#ibcon#about to read 3, iclass 38, count 0 2006.281.08:10:43.10#ibcon#read 3, iclass 38, count 0 2006.281.08:10:43.10#ibcon#about to read 4, iclass 38, count 0 2006.281.08:10:43.10#ibcon#read 4, iclass 38, count 0 2006.281.08:10:43.10#ibcon#about to read 5, iclass 38, count 0 2006.281.08:10:43.10#ibcon#read 5, iclass 38, count 0 2006.281.08:10:43.10#ibcon#about to read 6, iclass 38, count 0 2006.281.08:10:43.10#ibcon#read 6, iclass 38, count 0 2006.281.08:10:43.10#ibcon#end of sib2, iclass 38, count 0 2006.281.08:10:43.10#ibcon#*after write, iclass 38, count 0 2006.281.08:10:43.10#ibcon#*before return 0, iclass 38, count 0 2006.281.08:10:43.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:43.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:10:43.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:10:43.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:10:43.11$vc4f8/vb=6,4 2006.281.08:10:43.11#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:10:43.11#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:10:43.11#ibcon#ireg 11 cls_cnt 2 2006.281.08:10:43.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:43.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:43.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:43.15#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:10:43.15#ibcon#first serial, iclass 40, count 2 2006.281.08:10:43.15#ibcon#enter sib2, iclass 40, count 2 2006.281.08:10:43.15#ibcon#flushed, iclass 40, count 2 2006.281.08:10:43.15#ibcon#about to write, iclass 40, count 2 2006.281.08:10:43.15#ibcon#wrote, iclass 40, count 2 2006.281.08:10:43.15#ibcon#about to read 3, iclass 40, count 2 2006.281.08:10:43.17#ibcon#read 3, iclass 40, count 2 2006.281.08:10:43.17#ibcon#about to read 4, iclass 40, count 2 2006.281.08:10:43.17#ibcon#read 4, iclass 40, count 2 2006.281.08:10:43.17#ibcon#about to read 5, iclass 40, count 2 2006.281.08:10:43.17#ibcon#read 5, iclass 40, count 2 2006.281.08:10:43.17#ibcon#about to read 6, iclass 40, count 2 2006.281.08:10:43.17#ibcon#read 6, iclass 40, count 2 2006.281.08:10:43.17#ibcon#end of sib2, iclass 40, count 2 2006.281.08:10:43.17#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:10:43.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:10:43.17#ibcon#[27=AT06-04\r\n] 2006.281.08:10:43.17#ibcon#*before write, iclass 40, count 2 2006.281.08:10:43.17#ibcon#enter sib2, iclass 40, count 2 2006.281.08:10:43.17#ibcon#flushed, iclass 40, count 2 2006.281.08:10:43.17#ibcon#about to write, iclass 40, count 2 2006.281.08:10:43.17#ibcon#wrote, iclass 40, count 2 2006.281.08:10:43.17#ibcon#about to read 3, iclass 40, count 2 2006.281.08:10:43.21#ibcon#read 3, iclass 40, count 2 2006.281.08:10:43.21#ibcon#about to read 4, iclass 40, count 2 2006.281.08:10:43.21#ibcon#read 4, iclass 40, count 2 2006.281.08:10:43.21#ibcon#about to read 5, iclass 40, count 2 2006.281.08:10:43.21#ibcon#read 5, iclass 40, count 2 2006.281.08:10:43.21#ibcon#about to read 6, iclass 40, count 2 2006.281.08:10:43.21#ibcon#read 6, iclass 40, count 2 2006.281.08:10:43.21#ibcon#end of sib2, iclass 40, count 2 2006.281.08:10:43.21#ibcon#*after write, iclass 40, count 2 2006.281.08:10:43.21#ibcon#*before return 0, iclass 40, count 2 2006.281.08:10:43.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:43.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:10:43.21#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:10:43.21#ibcon#ireg 7 cls_cnt 0 2006.281.08:10:43.21#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:43.33#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:43.33#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:43.33#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:10:43.33#ibcon#first serial, iclass 40, count 0 2006.281.08:10:43.33#ibcon#enter sib2, iclass 40, count 0 2006.281.08:10:43.33#ibcon#flushed, iclass 40, count 0 2006.281.08:10:43.33#ibcon#about to write, iclass 40, count 0 2006.281.08:10:43.33#ibcon#wrote, iclass 40, count 0 2006.281.08:10:43.33#ibcon#about to read 3, iclass 40, count 0 2006.281.08:10:43.34#ibcon#read 3, iclass 40, count 0 2006.281.08:10:43.34#ibcon#about to read 4, iclass 40, count 0 2006.281.08:10:43.34#ibcon#read 4, iclass 40, count 0 2006.281.08:10:43.34#ibcon#about to read 5, iclass 40, count 0 2006.281.08:10:43.34#ibcon#read 5, iclass 40, count 0 2006.281.08:10:43.34#ibcon#about to read 6, iclass 40, count 0 2006.281.08:10:43.34#ibcon#read 6, iclass 40, count 0 2006.281.08:10:43.34#ibcon#end of sib2, iclass 40, count 0 2006.281.08:10:43.34#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:10:43.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:10:43.34#ibcon#[27=USB\r\n] 2006.281.08:10:43.34#ibcon#*before write, iclass 40, count 0 2006.281.08:10:43.34#ibcon#enter sib2, iclass 40, count 0 2006.281.08:10:43.34#ibcon#flushed, iclass 40, count 0 2006.281.08:10:43.34#ibcon#about to write, iclass 40, count 0 2006.281.08:10:43.34#ibcon#wrote, iclass 40, count 0 2006.281.08:10:43.34#ibcon#about to read 3, iclass 40, count 0 2006.281.08:10:43.37#ibcon#read 3, iclass 40, count 0 2006.281.08:10:43.37#ibcon#about to read 4, iclass 40, count 0 2006.281.08:10:43.37#ibcon#read 4, iclass 40, count 0 2006.281.08:10:43.37#ibcon#about to read 5, iclass 40, count 0 2006.281.08:10:43.37#ibcon#read 5, iclass 40, count 0 2006.281.08:10:43.37#ibcon#about to read 6, iclass 40, count 0 2006.281.08:10:43.37#ibcon#read 6, iclass 40, count 0 2006.281.08:10:43.37#ibcon#end of sib2, iclass 40, count 0 2006.281.08:10:43.37#ibcon#*after write, iclass 40, count 0 2006.281.08:10:43.37#ibcon#*before return 0, iclass 40, count 0 2006.281.08:10:43.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:43.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:10:43.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:10:43.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:10:43.38$vc4f8/vabw=wide 2006.281.08:10:43.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:10:43.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:10:43.38#ibcon#ireg 8 cls_cnt 0 2006.281.08:10:43.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:43.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:43.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:43.38#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:10:43.38#ibcon#first serial, iclass 4, count 0 2006.281.08:10:43.38#ibcon#enter sib2, iclass 4, count 0 2006.281.08:10:43.38#ibcon#flushed, iclass 4, count 0 2006.281.08:10:43.38#ibcon#about to write, iclass 4, count 0 2006.281.08:10:43.38#ibcon#wrote, iclass 4, count 0 2006.281.08:10:43.38#ibcon#about to read 3, iclass 4, count 0 2006.281.08:10:43.39#ibcon#read 3, iclass 4, count 0 2006.281.08:10:43.39#ibcon#about to read 4, iclass 4, count 0 2006.281.08:10:43.39#ibcon#read 4, iclass 4, count 0 2006.281.08:10:43.39#ibcon#about to read 5, iclass 4, count 0 2006.281.08:10:43.39#ibcon#read 5, iclass 4, count 0 2006.281.08:10:43.39#ibcon#about to read 6, iclass 4, count 0 2006.281.08:10:43.39#ibcon#read 6, iclass 4, count 0 2006.281.08:10:43.39#ibcon#end of sib2, iclass 4, count 0 2006.281.08:10:43.39#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:10:43.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:10:43.39#ibcon#[25=BW32\r\n] 2006.281.08:10:43.39#ibcon#*before write, iclass 4, count 0 2006.281.08:10:43.39#ibcon#enter sib2, iclass 4, count 0 2006.281.08:10:43.39#ibcon#flushed, iclass 4, count 0 2006.281.08:10:43.39#ibcon#about to write, iclass 4, count 0 2006.281.08:10:43.39#ibcon#wrote, iclass 4, count 0 2006.281.08:10:43.39#ibcon#about to read 3, iclass 4, count 0 2006.281.08:10:43.43#ibcon#read 3, iclass 4, count 0 2006.281.08:10:43.43#ibcon#about to read 4, iclass 4, count 0 2006.281.08:10:43.43#ibcon#read 4, iclass 4, count 0 2006.281.08:10:43.43#ibcon#about to read 5, iclass 4, count 0 2006.281.08:10:43.43#ibcon#read 5, iclass 4, count 0 2006.281.08:10:43.43#ibcon#about to read 6, iclass 4, count 0 2006.281.08:10:43.43#ibcon#read 6, iclass 4, count 0 2006.281.08:10:43.43#ibcon#end of sib2, iclass 4, count 0 2006.281.08:10:43.43#ibcon#*after write, iclass 4, count 0 2006.281.08:10:43.43#ibcon#*before return 0, iclass 4, count 0 2006.281.08:10:43.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:43.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:10:43.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:10:43.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:10:43.43$vc4f8/vbbw=wide 2006.281.08:10:43.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:10:43.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:10:43.43#ibcon#ireg 8 cls_cnt 0 2006.281.08:10:43.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:10:43.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:10:43.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:10:43.48#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:10:43.48#ibcon#first serial, iclass 6, count 0 2006.281.08:10:43.48#ibcon#enter sib2, iclass 6, count 0 2006.281.08:10:43.48#ibcon#flushed, iclass 6, count 0 2006.281.08:10:43.48#ibcon#about to write, iclass 6, count 0 2006.281.08:10:43.48#ibcon#wrote, iclass 6, count 0 2006.281.08:10:43.48#ibcon#about to read 3, iclass 6, count 0 2006.281.08:10:43.50#ibcon#read 3, iclass 6, count 0 2006.281.08:10:43.50#ibcon#about to read 4, iclass 6, count 0 2006.281.08:10:43.50#ibcon#read 4, iclass 6, count 0 2006.281.08:10:43.50#ibcon#about to read 5, iclass 6, count 0 2006.281.08:10:43.50#ibcon#read 5, iclass 6, count 0 2006.281.08:10:43.50#ibcon#about to read 6, iclass 6, count 0 2006.281.08:10:43.50#ibcon#read 6, iclass 6, count 0 2006.281.08:10:43.50#ibcon#end of sib2, iclass 6, count 0 2006.281.08:10:43.50#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:10:43.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:10:43.50#ibcon#[27=BW32\r\n] 2006.281.08:10:43.50#ibcon#*before write, iclass 6, count 0 2006.281.08:10:43.50#ibcon#enter sib2, iclass 6, count 0 2006.281.08:10:43.50#ibcon#flushed, iclass 6, count 0 2006.281.08:10:43.50#ibcon#about to write, iclass 6, count 0 2006.281.08:10:43.50#ibcon#wrote, iclass 6, count 0 2006.281.08:10:43.50#ibcon#about to read 3, iclass 6, count 0 2006.281.08:10:43.53#ibcon#read 3, iclass 6, count 0 2006.281.08:10:43.53#ibcon#about to read 4, iclass 6, count 0 2006.281.08:10:43.53#ibcon#read 4, iclass 6, count 0 2006.281.08:10:43.53#ibcon#about to read 5, iclass 6, count 0 2006.281.08:10:43.53#ibcon#read 5, iclass 6, count 0 2006.281.08:10:43.53#ibcon#about to read 6, iclass 6, count 0 2006.281.08:10:43.53#ibcon#read 6, iclass 6, count 0 2006.281.08:10:43.53#ibcon#end of sib2, iclass 6, count 0 2006.281.08:10:43.53#ibcon#*after write, iclass 6, count 0 2006.281.08:10:43.53#ibcon#*before return 0, iclass 6, count 0 2006.281.08:10:43.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:10:43.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:10:43.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:10:43.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:10:43.54$4f8m12a/ifd4f 2006.281.08:10:43.54$ifd4f/lo= 2006.281.08:10:43.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:10:43.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:10:43.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:10:43.55$ifd4f/patch= 2006.281.08:10:43.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:10:43.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:10:43.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:10:43.55$4f8m12a/"form=m,16.000,1:2 2006.281.08:10:43.55$4f8m12a/"tpicd 2006.281.08:10:43.55$4f8m12a/echo=off 2006.281.08:10:43.55$4f8m12a/xlog=off 2006.281.08:10:43.55:!2006.281.08:11:10 2006.281.08:10:56.14#trakl#Source acquired 2006.281.08:10:58.15#flagr#flagr/antenna,acquired 2006.281.08:11:10.02:preob 2006.281.08:11:11.15/onsource/TRACKING 2006.281.08:11:11.15:!2006.281.08:11:20 2006.281.08:11:20.02:data_valid=on 2006.281.08:11:20.02:midob 2006.281.08:11:21.15/onsource/TRACKING 2006.281.08:11:21.15/wx/20.19,1001.6,52 2006.281.08:11:21.34/cable/+6.4865E-03 2006.281.08:11:22.43/va/01,07,usb,yes,33,35 2006.281.08:11:22.43/va/02,06,usb,yes,31,32 2006.281.08:11:22.43/va/03,06,usb,yes,29,29 2006.281.08:11:22.43/va/04,06,usb,yes,32,34 2006.281.08:11:22.43/va/05,07,usb,yes,31,32 2006.281.08:11:22.43/va/06,06,usb,yes,30,29 2006.281.08:11:22.43/va/07,06,usb,yes,30,30 2006.281.08:11:22.43/va/08,06,usb,yes,32,32 2006.281.08:11:22.66/valo/01,532.99,yes,locked 2006.281.08:11:22.66/valo/02,572.99,yes,locked 2006.281.08:11:22.66/valo/03,672.99,yes,locked 2006.281.08:11:22.66/valo/04,832.99,yes,locked 2006.281.08:11:22.66/valo/05,652.99,yes,locked 2006.281.08:11:22.66/valo/06,772.99,yes,locked 2006.281.08:11:22.66/valo/07,832.99,yes,locked 2006.281.08:11:22.66/valo/08,852.99,yes,locked 2006.281.08:11:23.75/vb/01,04,usb,yes,31,29 2006.281.08:11:23.75/vb/02,05,usb,yes,28,30 2006.281.08:11:23.75/vb/03,04,usb,yes,29,33 2006.281.08:11:23.75/vb/04,04,usb,yes,29,30 2006.281.08:11:23.75/vb/05,04,usb,yes,28,32 2006.281.08:11:23.75/vb/06,04,usb,yes,28,32 2006.281.08:11:23.75/vb/07,04,usb,yes,31,31 2006.281.08:11:23.75/vb/08,04,usb,yes,28,32 2006.281.08:11:23.98/vblo/01,632.99,yes,locked 2006.281.08:11:23.98/vblo/02,640.99,yes,locked 2006.281.08:11:23.98/vblo/03,656.99,yes,locked 2006.281.08:11:23.98/vblo/04,712.99,yes,locked 2006.281.08:11:23.98/vblo/05,744.99,yes,locked 2006.281.08:11:23.98/vblo/06,752.99,yes,locked 2006.281.08:11:23.98/vblo/07,734.99,yes,locked 2006.281.08:11:23.98/vblo/08,744.99,yes,locked 2006.281.08:11:24.13/vabw/8 2006.281.08:11:24.28/vbbw/8 2006.281.08:11:24.37/xfe/off,on,12.0 2006.281.08:11:24.74/ifatt/23,28,28,28 2006.281.08:11:25.07/fmout-gps/S +3.13E-07 2006.281.08:11:25.10:!2006.281.08:12:20 2006.281.08:11:54.14#trakl#Off source 2006.281.08:11:54.14?ERROR st -7 Antenna off-source! 2006.281.08:11:54.14#trakl#az 35.847 el 27.274 azerr*cos(el) 0.0045 elerr 0.0225 2006.281.08:11:56.14#flagr#flagr/antenna,off-source 2006.281.08:12:03.14#trakl#Source re-acquired 2006.281.08:12:05.14#flagr#flagr/antenna,re-acquired 2006.281.08:12:20.01:data_valid=off 2006.281.08:12:20.02:postob 2006.281.08:12:20.18/cable/+6.4874E-03 2006.281.08:12:20.19/wx/20.16,1001.7,52 2006.281.08:12:21.07/fmout-gps/S +3.12E-07 2006.281.08:12:21.08:scan_name=281-0813,k06281,60 2006.281.08:12:21.08:source=3c371,180650.68,694928.1,2000.0,neutral 2006.281.08:12:22.14#flagr#flagr/antenna,new-source 2006.281.08:12:22.15:checkk5 2006.281.08:12:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:12:23.19/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:12:23.83/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:12:24.31/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:12:24.74/chk_obsdata//k5ts1/T2810811??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:12:25.16/chk_obsdata//k5ts2/T2810811??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:12:25.57/chk_obsdata//k5ts3/T2810811??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:12:25.95/chk_obsdata//k5ts4/T2810811??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:12:26.81/k5log//k5ts1_log_newline 2006.281.08:12:27.64/k5log//k5ts2_log_newline 2006.281.08:12:28.42/k5log//k5ts3_log_newline 2006.281.08:12:29.36/k5log//k5ts4_log_newline 2006.281.08:12:29.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:12:29.39:4f8m12a=2 2006.281.08:12:29.39$4f8m12a/echo=on 2006.281.08:12:29.39$4f8m12a/pcalon 2006.281.08:12:29.39$pcalon/"no phase cal control is implemented here 2006.281.08:12:29.39$4f8m12a/"tpicd=stop 2006.281.08:12:29.39$4f8m12a/vc4f8 2006.281.08:12:29.39$vc4f8/valo=1,532.99 2006.281.08:12:29.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:12:29.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:12:29.40#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:29.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:29.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:29.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:29.40#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:12:29.40#ibcon#first serial, iclass 17, count 0 2006.281.08:12:29.40#ibcon#enter sib2, iclass 17, count 0 2006.281.08:12:29.40#ibcon#flushed, iclass 17, count 0 2006.281.08:12:29.40#ibcon#about to write, iclass 17, count 0 2006.281.08:12:29.40#ibcon#wrote, iclass 17, count 0 2006.281.08:12:29.40#ibcon#about to read 3, iclass 17, count 0 2006.281.08:12:29.41#ibcon#read 3, iclass 17, count 0 2006.281.08:12:29.41#ibcon#about to read 4, iclass 17, count 0 2006.281.08:12:29.41#ibcon#read 4, iclass 17, count 0 2006.281.08:12:29.41#ibcon#about to read 5, iclass 17, count 0 2006.281.08:12:29.41#ibcon#read 5, iclass 17, count 0 2006.281.08:12:29.41#ibcon#about to read 6, iclass 17, count 0 2006.281.08:12:29.41#ibcon#read 6, iclass 17, count 0 2006.281.08:12:29.41#ibcon#end of sib2, iclass 17, count 0 2006.281.08:12:29.41#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:12:29.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:12:29.41#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:12:29.41#ibcon#*before write, iclass 17, count 0 2006.281.08:12:29.41#ibcon#enter sib2, iclass 17, count 0 2006.281.08:12:29.41#ibcon#flushed, iclass 17, count 0 2006.281.08:12:29.41#ibcon#about to write, iclass 17, count 0 2006.281.08:12:29.41#ibcon#wrote, iclass 17, count 0 2006.281.08:12:29.41#ibcon#about to read 3, iclass 17, count 0 2006.281.08:12:29.46#ibcon#read 3, iclass 17, count 0 2006.281.08:12:29.46#ibcon#about to read 4, iclass 17, count 0 2006.281.08:12:29.46#ibcon#read 4, iclass 17, count 0 2006.281.08:12:29.46#ibcon#about to read 5, iclass 17, count 0 2006.281.08:12:29.46#ibcon#read 5, iclass 17, count 0 2006.281.08:12:29.46#ibcon#about to read 6, iclass 17, count 0 2006.281.08:12:29.46#ibcon#read 6, iclass 17, count 0 2006.281.08:12:29.46#ibcon#end of sib2, iclass 17, count 0 2006.281.08:12:29.46#ibcon#*after write, iclass 17, count 0 2006.281.08:12:29.46#ibcon#*before return 0, iclass 17, count 0 2006.281.08:12:29.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:29.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:29.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:12:29.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:12:29.46$vc4f8/va=1,7 2006.281.08:12:29.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:12:29.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:12:29.47#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:29.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:29.47#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:29.47#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:29.47#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:12:29.47#ibcon#first serial, iclass 19, count 2 2006.281.08:12:29.47#ibcon#enter sib2, iclass 19, count 2 2006.281.08:12:29.47#ibcon#flushed, iclass 19, count 2 2006.281.08:12:29.47#ibcon#about to write, iclass 19, count 2 2006.281.08:12:29.47#ibcon#wrote, iclass 19, count 2 2006.281.08:12:29.47#ibcon#about to read 3, iclass 19, count 2 2006.281.08:12:29.48#ibcon#read 3, iclass 19, count 2 2006.281.08:12:29.48#ibcon#about to read 4, iclass 19, count 2 2006.281.08:12:29.48#ibcon#read 4, iclass 19, count 2 2006.281.08:12:29.48#ibcon#about to read 5, iclass 19, count 2 2006.281.08:12:29.48#ibcon#read 5, iclass 19, count 2 2006.281.08:12:29.48#ibcon#about to read 6, iclass 19, count 2 2006.281.08:12:29.48#ibcon#read 6, iclass 19, count 2 2006.281.08:12:29.48#ibcon#end of sib2, iclass 19, count 2 2006.281.08:12:29.48#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:12:29.48#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:12:29.48#ibcon#[25=AT01-07\r\n] 2006.281.08:12:29.48#ibcon#*before write, iclass 19, count 2 2006.281.08:12:29.48#ibcon#enter sib2, iclass 19, count 2 2006.281.08:12:29.48#ibcon#flushed, iclass 19, count 2 2006.281.08:12:29.48#ibcon#about to write, iclass 19, count 2 2006.281.08:12:29.48#ibcon#wrote, iclass 19, count 2 2006.281.08:12:29.48#ibcon#about to read 3, iclass 19, count 2 2006.281.08:12:29.52#ibcon#read 3, iclass 19, count 2 2006.281.08:12:29.52#ibcon#about to read 4, iclass 19, count 2 2006.281.08:12:29.52#ibcon#read 4, iclass 19, count 2 2006.281.08:12:29.52#ibcon#about to read 5, iclass 19, count 2 2006.281.08:12:29.52#ibcon#read 5, iclass 19, count 2 2006.281.08:12:29.52#ibcon#about to read 6, iclass 19, count 2 2006.281.08:12:29.52#ibcon#read 6, iclass 19, count 2 2006.281.08:12:29.52#ibcon#end of sib2, iclass 19, count 2 2006.281.08:12:29.52#ibcon#*after write, iclass 19, count 2 2006.281.08:12:29.52#ibcon#*before return 0, iclass 19, count 2 2006.281.08:12:29.52#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:29.52#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:29.52#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:12:29.52#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:29.52#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:29.64#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:29.64#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:29.64#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:12:29.64#ibcon#first serial, iclass 19, count 0 2006.281.08:12:29.64#ibcon#enter sib2, iclass 19, count 0 2006.281.08:12:29.64#ibcon#flushed, iclass 19, count 0 2006.281.08:12:29.64#ibcon#about to write, iclass 19, count 0 2006.281.08:12:29.64#ibcon#wrote, iclass 19, count 0 2006.281.08:12:29.64#ibcon#about to read 3, iclass 19, count 0 2006.281.08:12:29.66#ibcon#read 3, iclass 19, count 0 2006.281.08:12:29.66#ibcon#about to read 4, iclass 19, count 0 2006.281.08:12:29.66#ibcon#read 4, iclass 19, count 0 2006.281.08:12:29.66#ibcon#about to read 5, iclass 19, count 0 2006.281.08:12:29.66#ibcon#read 5, iclass 19, count 0 2006.281.08:12:29.66#ibcon#about to read 6, iclass 19, count 0 2006.281.08:12:29.66#ibcon#read 6, iclass 19, count 0 2006.281.08:12:29.66#ibcon#end of sib2, iclass 19, count 0 2006.281.08:12:29.66#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:12:29.66#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:12:29.66#ibcon#[25=USB\r\n] 2006.281.08:12:29.66#ibcon#*before write, iclass 19, count 0 2006.281.08:12:29.66#ibcon#enter sib2, iclass 19, count 0 2006.281.08:12:29.66#ibcon#flushed, iclass 19, count 0 2006.281.08:12:29.66#ibcon#about to write, iclass 19, count 0 2006.281.08:12:29.66#ibcon#wrote, iclass 19, count 0 2006.281.08:12:29.66#ibcon#about to read 3, iclass 19, count 0 2006.281.08:12:29.68#ibcon#read 3, iclass 19, count 0 2006.281.08:12:29.68#ibcon#about to read 4, iclass 19, count 0 2006.281.08:12:29.68#ibcon#read 4, iclass 19, count 0 2006.281.08:12:29.68#ibcon#about to read 5, iclass 19, count 0 2006.281.08:12:29.68#ibcon#read 5, iclass 19, count 0 2006.281.08:12:29.68#ibcon#about to read 6, iclass 19, count 0 2006.281.08:12:29.68#ibcon#read 6, iclass 19, count 0 2006.281.08:12:29.68#ibcon#end of sib2, iclass 19, count 0 2006.281.08:12:29.68#ibcon#*after write, iclass 19, count 0 2006.281.08:12:29.68#ibcon#*before return 0, iclass 19, count 0 2006.281.08:12:29.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:29.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:29.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:12:29.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:12:29.68$vc4f8/valo=2,572.99 2006.281.08:12:29.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:12:29.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:12:29.68#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:29.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:29.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:29.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:29.68#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:12:29.69#ibcon#first serial, iclass 21, count 0 2006.281.08:12:29.69#ibcon#enter sib2, iclass 21, count 0 2006.281.08:12:29.69#ibcon#flushed, iclass 21, count 0 2006.281.08:12:29.69#ibcon#about to write, iclass 21, count 0 2006.281.08:12:29.69#ibcon#wrote, iclass 21, count 0 2006.281.08:12:29.69#ibcon#about to read 3, iclass 21, count 0 2006.281.08:12:29.70#ibcon#read 3, iclass 21, count 0 2006.281.08:12:29.70#ibcon#about to read 4, iclass 21, count 0 2006.281.08:12:29.70#ibcon#read 4, iclass 21, count 0 2006.281.08:12:29.70#ibcon#about to read 5, iclass 21, count 0 2006.281.08:12:29.70#ibcon#read 5, iclass 21, count 0 2006.281.08:12:29.70#ibcon#about to read 6, iclass 21, count 0 2006.281.08:12:29.70#ibcon#read 6, iclass 21, count 0 2006.281.08:12:29.70#ibcon#end of sib2, iclass 21, count 0 2006.281.08:12:29.70#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:12:29.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:12:29.70#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:12:29.70#ibcon#*before write, iclass 21, count 0 2006.281.08:12:29.70#ibcon#enter sib2, iclass 21, count 0 2006.281.08:12:29.70#ibcon#flushed, iclass 21, count 0 2006.281.08:12:29.70#ibcon#about to write, iclass 21, count 0 2006.281.08:12:29.70#ibcon#wrote, iclass 21, count 0 2006.281.08:12:29.70#ibcon#about to read 3, iclass 21, count 0 2006.281.08:12:29.75#ibcon#read 3, iclass 21, count 0 2006.281.08:12:29.75#ibcon#about to read 4, iclass 21, count 0 2006.281.08:12:29.75#ibcon#read 4, iclass 21, count 0 2006.281.08:12:29.75#ibcon#about to read 5, iclass 21, count 0 2006.281.08:12:29.75#ibcon#read 5, iclass 21, count 0 2006.281.08:12:29.75#ibcon#about to read 6, iclass 21, count 0 2006.281.08:12:29.75#ibcon#read 6, iclass 21, count 0 2006.281.08:12:29.75#ibcon#end of sib2, iclass 21, count 0 2006.281.08:12:29.75#ibcon#*after write, iclass 21, count 0 2006.281.08:12:29.75#ibcon#*before return 0, iclass 21, count 0 2006.281.08:12:29.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:29.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:29.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:12:29.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:12:29.75$vc4f8/va=2,6 2006.281.08:12:29.75#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:12:29.75#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:12:29.75#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:29.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:29.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:29.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:29.79#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:12:29.79#ibcon#first serial, iclass 23, count 2 2006.281.08:12:29.79#ibcon#enter sib2, iclass 23, count 2 2006.281.08:12:29.79#ibcon#flushed, iclass 23, count 2 2006.281.08:12:29.79#ibcon#about to write, iclass 23, count 2 2006.281.08:12:29.79#ibcon#wrote, iclass 23, count 2 2006.281.08:12:29.79#ibcon#about to read 3, iclass 23, count 2 2006.281.08:12:29.81#ibcon#read 3, iclass 23, count 2 2006.281.08:12:29.81#ibcon#about to read 4, iclass 23, count 2 2006.281.08:12:29.81#ibcon#read 4, iclass 23, count 2 2006.281.08:12:29.81#ibcon#about to read 5, iclass 23, count 2 2006.281.08:12:29.81#ibcon#read 5, iclass 23, count 2 2006.281.08:12:29.81#ibcon#about to read 6, iclass 23, count 2 2006.281.08:12:29.81#ibcon#read 6, iclass 23, count 2 2006.281.08:12:29.81#ibcon#end of sib2, iclass 23, count 2 2006.281.08:12:29.81#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:12:29.81#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:12:29.81#ibcon#[25=AT02-06\r\n] 2006.281.08:12:29.81#ibcon#*before write, iclass 23, count 2 2006.281.08:12:29.81#ibcon#enter sib2, iclass 23, count 2 2006.281.08:12:29.81#ibcon#flushed, iclass 23, count 2 2006.281.08:12:29.81#ibcon#about to write, iclass 23, count 2 2006.281.08:12:29.81#ibcon#wrote, iclass 23, count 2 2006.281.08:12:29.81#ibcon#about to read 3, iclass 23, count 2 2006.281.08:12:29.85#ibcon#read 3, iclass 23, count 2 2006.281.08:12:29.85#ibcon#about to read 4, iclass 23, count 2 2006.281.08:12:29.85#ibcon#read 4, iclass 23, count 2 2006.281.08:12:29.85#ibcon#about to read 5, iclass 23, count 2 2006.281.08:12:29.85#ibcon#read 5, iclass 23, count 2 2006.281.08:12:29.85#ibcon#about to read 6, iclass 23, count 2 2006.281.08:12:29.85#ibcon#read 6, iclass 23, count 2 2006.281.08:12:29.85#ibcon#end of sib2, iclass 23, count 2 2006.281.08:12:29.85#ibcon#*after write, iclass 23, count 2 2006.281.08:12:29.85#ibcon#*before return 0, iclass 23, count 2 2006.281.08:12:29.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:29.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:29.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:12:29.85#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:29.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:29.96#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:29.96#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:29.96#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:12:29.96#ibcon#first serial, iclass 23, count 0 2006.281.08:12:29.96#ibcon#enter sib2, iclass 23, count 0 2006.281.08:12:29.96#ibcon#flushed, iclass 23, count 0 2006.281.08:12:29.96#ibcon#about to write, iclass 23, count 0 2006.281.08:12:29.96#ibcon#wrote, iclass 23, count 0 2006.281.08:12:29.96#ibcon#about to read 3, iclass 23, count 0 2006.281.08:12:29.98#ibcon#read 3, iclass 23, count 0 2006.281.08:12:29.98#ibcon#about to read 4, iclass 23, count 0 2006.281.08:12:29.98#ibcon#read 4, iclass 23, count 0 2006.281.08:12:29.98#ibcon#about to read 5, iclass 23, count 0 2006.281.08:12:29.98#ibcon#read 5, iclass 23, count 0 2006.281.08:12:29.98#ibcon#about to read 6, iclass 23, count 0 2006.281.08:12:29.98#ibcon#read 6, iclass 23, count 0 2006.281.08:12:29.98#ibcon#end of sib2, iclass 23, count 0 2006.281.08:12:29.98#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:12:29.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:12:29.98#ibcon#[25=USB\r\n] 2006.281.08:12:29.98#ibcon#*before write, iclass 23, count 0 2006.281.08:12:29.98#ibcon#enter sib2, iclass 23, count 0 2006.281.08:12:29.98#ibcon#flushed, iclass 23, count 0 2006.281.08:12:29.98#ibcon#about to write, iclass 23, count 0 2006.281.08:12:29.98#ibcon#wrote, iclass 23, count 0 2006.281.08:12:29.98#ibcon#about to read 3, iclass 23, count 0 2006.281.08:12:30.02#ibcon#read 3, iclass 23, count 0 2006.281.08:12:30.02#ibcon#about to read 4, iclass 23, count 0 2006.281.08:12:30.02#ibcon#read 4, iclass 23, count 0 2006.281.08:12:30.02#ibcon#about to read 5, iclass 23, count 0 2006.281.08:12:30.02#ibcon#read 5, iclass 23, count 0 2006.281.08:12:30.02#ibcon#about to read 6, iclass 23, count 0 2006.281.08:12:30.02#ibcon#read 6, iclass 23, count 0 2006.281.08:12:30.02#ibcon#end of sib2, iclass 23, count 0 2006.281.08:12:30.02#ibcon#*after write, iclass 23, count 0 2006.281.08:12:30.02#ibcon#*before return 0, iclass 23, count 0 2006.281.08:12:30.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:30.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:30.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:12:30.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:12:30.02$vc4f8/valo=3,672.99 2006.281.08:12:30.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:12:30.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:12:30.02#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:30.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:30.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:30.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:30.02#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:12:30.02#ibcon#first serial, iclass 25, count 0 2006.281.08:12:30.02#ibcon#enter sib2, iclass 25, count 0 2006.281.08:12:30.02#ibcon#flushed, iclass 25, count 0 2006.281.08:12:30.02#ibcon#about to write, iclass 25, count 0 2006.281.08:12:30.02#ibcon#wrote, iclass 25, count 0 2006.281.08:12:30.02#ibcon#about to read 3, iclass 25, count 0 2006.281.08:12:30.03#ibcon#read 3, iclass 25, count 0 2006.281.08:12:30.03#ibcon#about to read 4, iclass 25, count 0 2006.281.08:12:30.03#ibcon#read 4, iclass 25, count 0 2006.281.08:12:30.03#ibcon#about to read 5, iclass 25, count 0 2006.281.08:12:30.03#ibcon#read 5, iclass 25, count 0 2006.281.08:12:30.03#ibcon#about to read 6, iclass 25, count 0 2006.281.08:12:30.03#ibcon#read 6, iclass 25, count 0 2006.281.08:12:30.03#ibcon#end of sib2, iclass 25, count 0 2006.281.08:12:30.03#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:12:30.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:12:30.03#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:12:30.03#ibcon#*before write, iclass 25, count 0 2006.281.08:12:30.03#ibcon#enter sib2, iclass 25, count 0 2006.281.08:12:30.06#ibcon#flushed, iclass 25, count 0 2006.281.08:12:30.06#ibcon#about to write, iclass 25, count 0 2006.281.08:12:30.06#ibcon#wrote, iclass 25, count 0 2006.281.08:12:30.06#ibcon#about to read 3, iclass 25, count 0 2006.281.08:12:30.09#ibcon#read 3, iclass 25, count 0 2006.281.08:12:30.09#ibcon#about to read 4, iclass 25, count 0 2006.281.08:12:30.09#ibcon#read 4, iclass 25, count 0 2006.281.08:12:30.09#ibcon#about to read 5, iclass 25, count 0 2006.281.08:12:30.09#ibcon#read 5, iclass 25, count 0 2006.281.08:12:30.09#ibcon#about to read 6, iclass 25, count 0 2006.281.08:12:30.09#ibcon#read 6, iclass 25, count 0 2006.281.08:12:30.09#ibcon#end of sib2, iclass 25, count 0 2006.281.08:12:30.09#ibcon#*after write, iclass 25, count 0 2006.281.08:12:30.09#ibcon#*before return 0, iclass 25, count 0 2006.281.08:12:30.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:30.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:30.09#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:12:30.09#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:12:30.09$vc4f8/va=3,6 2006.281.08:12:30.09#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:12:30.09#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:12:30.09#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:30.09#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:30.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:30.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:30.15#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:12:30.15#ibcon#first serial, iclass 27, count 2 2006.281.08:12:30.15#ibcon#enter sib2, iclass 27, count 2 2006.281.08:12:30.15#ibcon#flushed, iclass 27, count 2 2006.281.08:12:30.15#ibcon#about to write, iclass 27, count 2 2006.281.08:12:30.15#ibcon#wrote, iclass 27, count 2 2006.281.08:12:30.15#ibcon#about to read 3, iclass 27, count 2 2006.281.08:12:30.16#ibcon#read 3, iclass 27, count 2 2006.281.08:12:30.16#ibcon#about to read 4, iclass 27, count 2 2006.281.08:12:30.16#ibcon#read 4, iclass 27, count 2 2006.281.08:12:30.16#ibcon#about to read 5, iclass 27, count 2 2006.281.08:12:30.16#ibcon#read 5, iclass 27, count 2 2006.281.08:12:30.16#ibcon#about to read 6, iclass 27, count 2 2006.281.08:12:30.16#ibcon#read 6, iclass 27, count 2 2006.281.08:12:30.16#ibcon#end of sib2, iclass 27, count 2 2006.281.08:12:30.16#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:12:30.16#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:12:30.16#ibcon#[25=AT03-06\r\n] 2006.281.08:12:30.16#ibcon#*before write, iclass 27, count 2 2006.281.08:12:30.16#ibcon#enter sib2, iclass 27, count 2 2006.281.08:12:30.16#ibcon#flushed, iclass 27, count 2 2006.281.08:12:30.16#ibcon#about to write, iclass 27, count 2 2006.281.08:12:30.16#ibcon#wrote, iclass 27, count 2 2006.281.08:12:30.16#ibcon#about to read 3, iclass 27, count 2 2006.281.08:12:30.19#ibcon#read 3, iclass 27, count 2 2006.281.08:12:30.19#ibcon#about to read 4, iclass 27, count 2 2006.281.08:12:30.19#ibcon#read 4, iclass 27, count 2 2006.281.08:12:30.19#ibcon#about to read 5, iclass 27, count 2 2006.281.08:12:30.19#ibcon#read 5, iclass 27, count 2 2006.281.08:12:30.19#ibcon#about to read 6, iclass 27, count 2 2006.281.08:12:30.19#ibcon#read 6, iclass 27, count 2 2006.281.08:12:30.19#ibcon#end of sib2, iclass 27, count 2 2006.281.08:12:30.19#ibcon#*after write, iclass 27, count 2 2006.281.08:12:30.19#ibcon#*before return 0, iclass 27, count 2 2006.281.08:12:30.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:30.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:30.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:12:30.19#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:30.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:30.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:30.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:30.31#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:12:30.31#ibcon#first serial, iclass 27, count 0 2006.281.08:12:30.31#ibcon#enter sib2, iclass 27, count 0 2006.281.08:12:30.31#ibcon#flushed, iclass 27, count 0 2006.281.08:12:30.31#ibcon#about to write, iclass 27, count 0 2006.281.08:12:30.31#ibcon#wrote, iclass 27, count 0 2006.281.08:12:30.31#ibcon#about to read 3, iclass 27, count 0 2006.281.08:12:30.33#ibcon#read 3, iclass 27, count 0 2006.281.08:12:30.33#ibcon#about to read 4, iclass 27, count 0 2006.281.08:12:30.33#ibcon#read 4, iclass 27, count 0 2006.281.08:12:30.33#ibcon#about to read 5, iclass 27, count 0 2006.281.08:12:30.33#ibcon#read 5, iclass 27, count 0 2006.281.08:12:30.33#ibcon#about to read 6, iclass 27, count 0 2006.281.08:12:30.33#ibcon#read 6, iclass 27, count 0 2006.281.08:12:30.33#ibcon#end of sib2, iclass 27, count 0 2006.281.08:12:30.33#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:12:30.33#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:12:30.33#ibcon#[25=USB\r\n] 2006.281.08:12:30.33#ibcon#*before write, iclass 27, count 0 2006.281.08:12:30.33#ibcon#enter sib2, iclass 27, count 0 2006.281.08:12:30.33#ibcon#flushed, iclass 27, count 0 2006.281.08:12:30.33#ibcon#about to write, iclass 27, count 0 2006.281.08:12:30.33#ibcon#wrote, iclass 27, count 0 2006.281.08:12:30.33#ibcon#about to read 3, iclass 27, count 0 2006.281.08:12:30.36#ibcon#read 3, iclass 27, count 0 2006.281.08:12:30.36#ibcon#about to read 4, iclass 27, count 0 2006.281.08:12:30.36#ibcon#read 4, iclass 27, count 0 2006.281.08:12:30.36#ibcon#about to read 5, iclass 27, count 0 2006.281.08:12:30.36#ibcon#read 5, iclass 27, count 0 2006.281.08:12:30.36#ibcon#about to read 6, iclass 27, count 0 2006.281.08:12:30.36#ibcon#read 6, iclass 27, count 0 2006.281.08:12:30.36#ibcon#end of sib2, iclass 27, count 0 2006.281.08:12:30.36#ibcon#*after write, iclass 27, count 0 2006.281.08:12:30.36#ibcon#*before return 0, iclass 27, count 0 2006.281.08:12:30.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:30.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:30.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:12:30.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:12:30.36$vc4f8/valo=4,832.99 2006.281.08:12:30.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:12:30.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:12:30.36#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:30.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:30.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:30.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:30.37#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:12:30.37#ibcon#first serial, iclass 29, count 0 2006.281.08:12:30.37#ibcon#enter sib2, iclass 29, count 0 2006.281.08:12:30.37#ibcon#flushed, iclass 29, count 0 2006.281.08:12:30.37#ibcon#about to write, iclass 29, count 0 2006.281.08:12:30.37#ibcon#wrote, iclass 29, count 0 2006.281.08:12:30.37#ibcon#about to read 3, iclass 29, count 0 2006.281.08:12:30.38#ibcon#read 3, iclass 29, count 0 2006.281.08:12:30.38#ibcon#about to read 4, iclass 29, count 0 2006.281.08:12:30.38#ibcon#read 4, iclass 29, count 0 2006.281.08:12:30.38#ibcon#about to read 5, iclass 29, count 0 2006.281.08:12:30.38#ibcon#read 5, iclass 29, count 0 2006.281.08:12:30.38#ibcon#about to read 6, iclass 29, count 0 2006.281.08:12:30.38#ibcon#read 6, iclass 29, count 0 2006.281.08:12:30.38#ibcon#end of sib2, iclass 29, count 0 2006.281.08:12:30.38#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:12:30.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:12:30.38#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:12:30.38#ibcon#*before write, iclass 29, count 0 2006.281.08:12:30.38#ibcon#enter sib2, iclass 29, count 0 2006.281.08:12:30.38#ibcon#flushed, iclass 29, count 0 2006.281.08:12:30.38#ibcon#about to write, iclass 29, count 0 2006.281.08:12:30.38#ibcon#wrote, iclass 29, count 0 2006.281.08:12:30.38#ibcon#about to read 3, iclass 29, count 0 2006.281.08:12:30.43#ibcon#read 3, iclass 29, count 0 2006.281.08:12:30.43#ibcon#about to read 4, iclass 29, count 0 2006.281.08:12:30.43#ibcon#read 4, iclass 29, count 0 2006.281.08:12:30.43#ibcon#about to read 5, iclass 29, count 0 2006.281.08:12:30.43#ibcon#read 5, iclass 29, count 0 2006.281.08:12:30.43#ibcon#about to read 6, iclass 29, count 0 2006.281.08:12:30.43#ibcon#read 6, iclass 29, count 0 2006.281.08:12:30.43#ibcon#end of sib2, iclass 29, count 0 2006.281.08:12:30.43#ibcon#*after write, iclass 29, count 0 2006.281.08:12:30.43#ibcon#*before return 0, iclass 29, count 0 2006.281.08:12:30.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:30.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:30.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:12:30.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:12:30.43$vc4f8/va=4,6 2006.281.08:12:30.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:12:30.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:12:30.43#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:30.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:30.47#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:30.47#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:30.47#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:12:30.47#ibcon#first serial, iclass 31, count 2 2006.281.08:12:30.47#ibcon#enter sib2, iclass 31, count 2 2006.281.08:12:30.47#ibcon#flushed, iclass 31, count 2 2006.281.08:12:30.47#ibcon#about to write, iclass 31, count 2 2006.281.08:12:30.47#ibcon#wrote, iclass 31, count 2 2006.281.08:12:30.47#ibcon#about to read 3, iclass 31, count 2 2006.281.08:12:30.50#ibcon#read 3, iclass 31, count 2 2006.281.08:12:30.50#ibcon#about to read 4, iclass 31, count 2 2006.281.08:12:30.50#ibcon#read 4, iclass 31, count 2 2006.281.08:12:30.50#ibcon#about to read 5, iclass 31, count 2 2006.281.08:12:30.50#ibcon#read 5, iclass 31, count 2 2006.281.08:12:30.50#ibcon#about to read 6, iclass 31, count 2 2006.281.08:12:30.50#ibcon#read 6, iclass 31, count 2 2006.281.08:12:30.50#ibcon#end of sib2, iclass 31, count 2 2006.281.08:12:30.50#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:12:30.50#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:12:30.50#ibcon#[25=AT04-06\r\n] 2006.281.08:12:30.50#ibcon#*before write, iclass 31, count 2 2006.281.08:12:30.50#ibcon#enter sib2, iclass 31, count 2 2006.281.08:12:30.50#ibcon#flushed, iclass 31, count 2 2006.281.08:12:30.50#ibcon#about to write, iclass 31, count 2 2006.281.08:12:30.50#ibcon#wrote, iclass 31, count 2 2006.281.08:12:30.50#ibcon#about to read 3, iclass 31, count 2 2006.281.08:12:30.53#ibcon#read 3, iclass 31, count 2 2006.281.08:12:30.53#ibcon#about to read 4, iclass 31, count 2 2006.281.08:12:30.53#ibcon#read 4, iclass 31, count 2 2006.281.08:12:30.53#ibcon#about to read 5, iclass 31, count 2 2006.281.08:12:30.53#ibcon#read 5, iclass 31, count 2 2006.281.08:12:30.53#ibcon#about to read 6, iclass 31, count 2 2006.281.08:12:30.53#ibcon#read 6, iclass 31, count 2 2006.281.08:12:30.53#ibcon#end of sib2, iclass 31, count 2 2006.281.08:12:30.53#ibcon#*after write, iclass 31, count 2 2006.281.08:12:30.53#ibcon#*before return 0, iclass 31, count 2 2006.281.08:12:30.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:30.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:30.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:12:30.53#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:30.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:30.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:30.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:30.64#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:12:30.64#ibcon#first serial, iclass 31, count 0 2006.281.08:12:30.64#ibcon#enter sib2, iclass 31, count 0 2006.281.08:12:30.64#ibcon#flushed, iclass 31, count 0 2006.281.08:12:30.64#ibcon#about to write, iclass 31, count 0 2006.281.08:12:30.64#ibcon#wrote, iclass 31, count 0 2006.281.08:12:30.64#ibcon#about to read 3, iclass 31, count 0 2006.281.08:12:30.66#ibcon#read 3, iclass 31, count 0 2006.281.08:12:30.66#ibcon#about to read 4, iclass 31, count 0 2006.281.08:12:30.66#ibcon#read 4, iclass 31, count 0 2006.281.08:12:30.66#ibcon#about to read 5, iclass 31, count 0 2006.281.08:12:30.66#ibcon#read 5, iclass 31, count 0 2006.281.08:12:30.66#ibcon#about to read 6, iclass 31, count 0 2006.281.08:12:30.66#ibcon#read 6, iclass 31, count 0 2006.281.08:12:30.66#ibcon#end of sib2, iclass 31, count 0 2006.281.08:12:30.66#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:12:30.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:12:30.66#ibcon#[25=USB\r\n] 2006.281.08:12:30.66#ibcon#*before write, iclass 31, count 0 2006.281.08:12:30.66#ibcon#enter sib2, iclass 31, count 0 2006.281.08:12:30.66#ibcon#flushed, iclass 31, count 0 2006.281.08:12:30.66#ibcon#about to write, iclass 31, count 0 2006.281.08:12:30.66#ibcon#wrote, iclass 31, count 0 2006.281.08:12:30.66#ibcon#about to read 3, iclass 31, count 0 2006.281.08:12:30.69#ibcon#read 3, iclass 31, count 0 2006.281.08:12:30.69#ibcon#about to read 4, iclass 31, count 0 2006.281.08:12:30.69#ibcon#read 4, iclass 31, count 0 2006.281.08:12:30.69#ibcon#about to read 5, iclass 31, count 0 2006.281.08:12:30.69#ibcon#read 5, iclass 31, count 0 2006.281.08:12:30.69#ibcon#about to read 6, iclass 31, count 0 2006.281.08:12:30.69#ibcon#read 6, iclass 31, count 0 2006.281.08:12:30.69#ibcon#end of sib2, iclass 31, count 0 2006.281.08:12:30.69#ibcon#*after write, iclass 31, count 0 2006.281.08:12:30.69#ibcon#*before return 0, iclass 31, count 0 2006.281.08:12:30.69#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:30.69#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:30.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:12:30.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:12:30.69$vc4f8/valo=5,652.99 2006.281.08:12:30.69#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:12:30.69#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:12:30.69#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:30.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:30.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:30.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:30.69#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:12:30.70#ibcon#first serial, iclass 33, count 0 2006.281.08:12:30.70#ibcon#enter sib2, iclass 33, count 0 2006.281.08:12:30.70#ibcon#flushed, iclass 33, count 0 2006.281.08:12:30.70#ibcon#about to write, iclass 33, count 0 2006.281.08:12:30.70#ibcon#wrote, iclass 33, count 0 2006.281.08:12:30.70#ibcon#about to read 3, iclass 33, count 0 2006.281.08:12:30.71#ibcon#read 3, iclass 33, count 0 2006.281.08:12:30.71#ibcon#about to read 4, iclass 33, count 0 2006.281.08:12:30.71#ibcon#read 4, iclass 33, count 0 2006.281.08:12:30.71#ibcon#about to read 5, iclass 33, count 0 2006.281.08:12:30.71#ibcon#read 5, iclass 33, count 0 2006.281.08:12:30.71#ibcon#about to read 6, iclass 33, count 0 2006.281.08:12:30.71#ibcon#read 6, iclass 33, count 0 2006.281.08:12:30.71#ibcon#end of sib2, iclass 33, count 0 2006.281.08:12:30.71#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:12:30.71#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:12:30.71#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:12:30.71#ibcon#*before write, iclass 33, count 0 2006.281.08:12:30.71#ibcon#enter sib2, iclass 33, count 0 2006.281.08:12:30.71#ibcon#flushed, iclass 33, count 0 2006.281.08:12:30.71#ibcon#about to write, iclass 33, count 0 2006.281.08:12:30.71#ibcon#wrote, iclass 33, count 0 2006.281.08:12:30.71#ibcon#about to read 3, iclass 33, count 0 2006.281.08:12:30.76#ibcon#read 3, iclass 33, count 0 2006.281.08:12:30.76#ibcon#about to read 4, iclass 33, count 0 2006.281.08:12:30.76#ibcon#read 4, iclass 33, count 0 2006.281.08:12:30.76#ibcon#about to read 5, iclass 33, count 0 2006.281.08:12:30.76#ibcon#read 5, iclass 33, count 0 2006.281.08:12:30.76#ibcon#about to read 6, iclass 33, count 0 2006.281.08:12:30.76#ibcon#read 6, iclass 33, count 0 2006.281.08:12:30.76#ibcon#end of sib2, iclass 33, count 0 2006.281.08:12:30.76#ibcon#*after write, iclass 33, count 0 2006.281.08:12:30.76#ibcon#*before return 0, iclass 33, count 0 2006.281.08:12:30.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:30.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:30.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:12:30.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:12:30.76$vc4f8/va=5,7 2006.281.08:12:30.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:12:30.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:12:30.77#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:30.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:30.81#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:30.81#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:30.81#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:12:30.81#ibcon#first serial, iclass 35, count 2 2006.281.08:12:30.81#ibcon#enter sib2, iclass 35, count 2 2006.281.08:12:30.81#ibcon#flushed, iclass 35, count 2 2006.281.08:12:30.81#ibcon#about to write, iclass 35, count 2 2006.281.08:12:30.81#ibcon#wrote, iclass 35, count 2 2006.281.08:12:30.81#ibcon#about to read 3, iclass 35, count 2 2006.281.08:12:30.83#ibcon#read 3, iclass 35, count 2 2006.281.08:12:30.83#ibcon#about to read 4, iclass 35, count 2 2006.281.08:12:30.83#ibcon#read 4, iclass 35, count 2 2006.281.08:12:30.83#ibcon#about to read 5, iclass 35, count 2 2006.281.08:12:30.83#ibcon#read 5, iclass 35, count 2 2006.281.08:12:30.83#ibcon#about to read 6, iclass 35, count 2 2006.281.08:12:30.83#ibcon#read 6, iclass 35, count 2 2006.281.08:12:30.83#ibcon#end of sib2, iclass 35, count 2 2006.281.08:12:30.83#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:12:30.83#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:12:30.83#ibcon#[25=AT05-07\r\n] 2006.281.08:12:30.83#ibcon#*before write, iclass 35, count 2 2006.281.08:12:30.83#ibcon#enter sib2, iclass 35, count 2 2006.281.08:12:30.83#ibcon#flushed, iclass 35, count 2 2006.281.08:12:30.83#ibcon#about to write, iclass 35, count 2 2006.281.08:12:30.83#ibcon#wrote, iclass 35, count 2 2006.281.08:12:30.83#ibcon#about to read 3, iclass 35, count 2 2006.281.08:12:30.86#ibcon#read 3, iclass 35, count 2 2006.281.08:12:30.86#ibcon#about to read 4, iclass 35, count 2 2006.281.08:12:30.86#ibcon#read 4, iclass 35, count 2 2006.281.08:12:30.86#ibcon#about to read 5, iclass 35, count 2 2006.281.08:12:30.86#ibcon#read 5, iclass 35, count 2 2006.281.08:12:30.86#ibcon#about to read 6, iclass 35, count 2 2006.281.08:12:30.86#ibcon#read 6, iclass 35, count 2 2006.281.08:12:30.86#ibcon#end of sib2, iclass 35, count 2 2006.281.08:12:30.86#ibcon#*after write, iclass 35, count 2 2006.281.08:12:30.86#ibcon#*before return 0, iclass 35, count 2 2006.281.08:12:30.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:30.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:30.86#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:12:30.86#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:30.86#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:30.97#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:30.97#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:30.97#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:12:30.97#ibcon#first serial, iclass 35, count 0 2006.281.08:12:30.97#ibcon#enter sib2, iclass 35, count 0 2006.281.08:12:30.97#ibcon#flushed, iclass 35, count 0 2006.281.08:12:30.97#ibcon#about to write, iclass 35, count 0 2006.281.08:12:30.97#ibcon#wrote, iclass 35, count 0 2006.281.08:12:30.97#ibcon#about to read 3, iclass 35, count 0 2006.281.08:12:30.99#ibcon#read 3, iclass 35, count 0 2006.281.08:12:30.99#ibcon#about to read 4, iclass 35, count 0 2006.281.08:12:30.99#ibcon#read 4, iclass 35, count 0 2006.281.08:12:30.99#ibcon#about to read 5, iclass 35, count 0 2006.281.08:12:30.99#ibcon#read 5, iclass 35, count 0 2006.281.08:12:30.99#ibcon#about to read 6, iclass 35, count 0 2006.281.08:12:30.99#ibcon#read 6, iclass 35, count 0 2006.281.08:12:30.99#ibcon#end of sib2, iclass 35, count 0 2006.281.08:12:30.99#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:12:30.99#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:12:30.99#ibcon#[25=USB\r\n] 2006.281.08:12:30.99#ibcon#*before write, iclass 35, count 0 2006.281.08:12:30.99#ibcon#enter sib2, iclass 35, count 0 2006.281.08:12:30.99#ibcon#flushed, iclass 35, count 0 2006.281.08:12:30.99#ibcon#about to write, iclass 35, count 0 2006.281.08:12:30.99#ibcon#wrote, iclass 35, count 0 2006.281.08:12:30.99#ibcon#about to read 3, iclass 35, count 0 2006.281.08:12:31.03#ibcon#read 3, iclass 35, count 0 2006.281.08:12:31.03#ibcon#about to read 4, iclass 35, count 0 2006.281.08:12:31.03#ibcon#read 4, iclass 35, count 0 2006.281.08:12:31.03#ibcon#about to read 5, iclass 35, count 0 2006.281.08:12:31.03#ibcon#read 5, iclass 35, count 0 2006.281.08:12:31.03#ibcon#about to read 6, iclass 35, count 0 2006.281.08:12:31.03#ibcon#read 6, iclass 35, count 0 2006.281.08:12:31.03#ibcon#end of sib2, iclass 35, count 0 2006.281.08:12:31.03#ibcon#*after write, iclass 35, count 0 2006.281.08:12:31.03#ibcon#*before return 0, iclass 35, count 0 2006.281.08:12:31.03#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:31.03#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:31.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:12:31.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:12:31.03$vc4f8/valo=6,772.99 2006.281.08:12:31.03#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:12:31.03#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:12:31.03#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:31.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:31.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:31.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:31.03#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:12:31.03#ibcon#first serial, iclass 37, count 0 2006.281.08:12:31.03#ibcon#enter sib2, iclass 37, count 0 2006.281.08:12:31.03#ibcon#flushed, iclass 37, count 0 2006.281.08:12:31.03#ibcon#about to write, iclass 37, count 0 2006.281.08:12:31.03#ibcon#wrote, iclass 37, count 0 2006.281.08:12:31.03#ibcon#about to read 3, iclass 37, count 0 2006.281.08:12:31.05#ibcon#read 3, iclass 37, count 0 2006.281.08:12:31.05#ibcon#about to read 4, iclass 37, count 0 2006.281.08:12:31.05#ibcon#read 4, iclass 37, count 0 2006.281.08:12:31.05#ibcon#about to read 5, iclass 37, count 0 2006.281.08:12:31.05#ibcon#read 5, iclass 37, count 0 2006.281.08:12:31.05#ibcon#about to read 6, iclass 37, count 0 2006.281.08:12:31.05#ibcon#read 6, iclass 37, count 0 2006.281.08:12:31.05#ibcon#end of sib2, iclass 37, count 0 2006.281.08:12:31.05#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:12:31.05#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:12:31.05#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:12:31.05#ibcon#*before write, iclass 37, count 0 2006.281.08:12:31.05#ibcon#enter sib2, iclass 37, count 0 2006.281.08:12:31.05#ibcon#flushed, iclass 37, count 0 2006.281.08:12:31.05#ibcon#about to write, iclass 37, count 0 2006.281.08:12:31.06#ibcon#wrote, iclass 37, count 0 2006.281.08:12:31.06#ibcon#about to read 3, iclass 37, count 0 2006.281.08:12:31.10#ibcon#read 3, iclass 37, count 0 2006.281.08:12:31.10#ibcon#about to read 4, iclass 37, count 0 2006.281.08:12:31.10#ibcon#read 4, iclass 37, count 0 2006.281.08:12:31.10#ibcon#about to read 5, iclass 37, count 0 2006.281.08:12:31.10#ibcon#read 5, iclass 37, count 0 2006.281.08:12:31.10#ibcon#about to read 6, iclass 37, count 0 2006.281.08:12:31.10#ibcon#read 6, iclass 37, count 0 2006.281.08:12:31.10#ibcon#end of sib2, iclass 37, count 0 2006.281.08:12:31.10#ibcon#*after write, iclass 37, count 0 2006.281.08:12:31.10#ibcon#*before return 0, iclass 37, count 0 2006.281.08:12:31.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:31.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:31.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:12:31.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:12:31.10$vc4f8/va=6,6 2006.281.08:12:31.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.281.08:12:31.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.281.08:12:31.10#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:31.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:31.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:31.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:31.16#ibcon#enter wrdev, iclass 39, count 2 2006.281.08:12:31.16#ibcon#first serial, iclass 39, count 2 2006.281.08:12:31.16#ibcon#enter sib2, iclass 39, count 2 2006.281.08:12:31.16#ibcon#flushed, iclass 39, count 2 2006.281.08:12:31.16#ibcon#about to write, iclass 39, count 2 2006.281.08:12:31.16#ibcon#wrote, iclass 39, count 2 2006.281.08:12:31.16#ibcon#about to read 3, iclass 39, count 2 2006.281.08:12:31.17#ibcon#read 3, iclass 39, count 2 2006.281.08:12:31.17#ibcon#about to read 4, iclass 39, count 2 2006.281.08:12:31.17#ibcon#read 4, iclass 39, count 2 2006.281.08:12:31.17#ibcon#about to read 5, iclass 39, count 2 2006.281.08:12:31.17#ibcon#read 5, iclass 39, count 2 2006.281.08:12:31.17#ibcon#about to read 6, iclass 39, count 2 2006.281.08:12:31.17#ibcon#read 6, iclass 39, count 2 2006.281.08:12:31.17#ibcon#end of sib2, iclass 39, count 2 2006.281.08:12:31.17#ibcon#*mode == 0, iclass 39, count 2 2006.281.08:12:31.17#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.281.08:12:31.17#ibcon#[25=AT06-06\r\n] 2006.281.08:12:31.17#ibcon#*before write, iclass 39, count 2 2006.281.08:12:31.17#ibcon#enter sib2, iclass 39, count 2 2006.281.08:12:31.17#ibcon#flushed, iclass 39, count 2 2006.281.08:12:31.17#ibcon#about to write, iclass 39, count 2 2006.281.08:12:31.17#ibcon#wrote, iclass 39, count 2 2006.281.08:12:31.17#ibcon#about to read 3, iclass 39, count 2 2006.281.08:12:31.20#ibcon#read 3, iclass 39, count 2 2006.281.08:12:31.20#ibcon#about to read 4, iclass 39, count 2 2006.281.08:12:31.20#ibcon#read 4, iclass 39, count 2 2006.281.08:12:31.20#ibcon#about to read 5, iclass 39, count 2 2006.281.08:12:31.20#ibcon#read 5, iclass 39, count 2 2006.281.08:12:31.20#ibcon#about to read 6, iclass 39, count 2 2006.281.08:12:31.20#ibcon#read 6, iclass 39, count 2 2006.281.08:12:31.20#ibcon#end of sib2, iclass 39, count 2 2006.281.08:12:31.20#ibcon#*after write, iclass 39, count 2 2006.281.08:12:31.20#ibcon#*before return 0, iclass 39, count 2 2006.281.08:12:31.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:31.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:31.20#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.281.08:12:31.20#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:31.20#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:12:31.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:12:31.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:12:31.33#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:12:31.33#ibcon#first serial, iclass 39, count 0 2006.281.08:12:31.33#ibcon#enter sib2, iclass 39, count 0 2006.281.08:12:31.33#ibcon#flushed, iclass 39, count 0 2006.281.08:12:31.33#ibcon#about to write, iclass 39, count 0 2006.281.08:12:31.33#ibcon#wrote, iclass 39, count 0 2006.281.08:12:31.33#ibcon#about to read 3, iclass 39, count 0 2006.281.08:12:31.34#ibcon#read 3, iclass 39, count 0 2006.281.08:12:31.34#ibcon#about to read 4, iclass 39, count 0 2006.281.08:12:31.34#ibcon#read 4, iclass 39, count 0 2006.281.08:12:31.34#ibcon#about to read 5, iclass 39, count 0 2006.281.08:12:31.34#ibcon#read 5, iclass 39, count 0 2006.281.08:12:31.34#ibcon#about to read 6, iclass 39, count 0 2006.281.08:12:31.34#ibcon#read 6, iclass 39, count 0 2006.281.08:12:31.34#ibcon#end of sib2, iclass 39, count 0 2006.281.08:12:31.34#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:12:31.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:12:31.34#ibcon#[25=USB\r\n] 2006.281.08:12:31.34#ibcon#*before write, iclass 39, count 0 2006.281.08:12:31.34#ibcon#enter sib2, iclass 39, count 0 2006.281.08:12:31.34#ibcon#flushed, iclass 39, count 0 2006.281.08:12:31.34#ibcon#about to write, iclass 39, count 0 2006.281.08:12:31.34#ibcon#wrote, iclass 39, count 0 2006.281.08:12:31.34#ibcon#about to read 3, iclass 39, count 0 2006.281.08:12:31.37#ibcon#read 3, iclass 39, count 0 2006.281.08:12:31.37#ibcon#about to read 4, iclass 39, count 0 2006.281.08:12:31.37#ibcon#read 4, iclass 39, count 0 2006.281.08:12:31.37#ibcon#about to read 5, iclass 39, count 0 2006.281.08:12:31.37#ibcon#read 5, iclass 39, count 0 2006.281.08:12:31.37#ibcon#about to read 6, iclass 39, count 0 2006.281.08:12:31.37#ibcon#read 6, iclass 39, count 0 2006.281.08:12:31.37#ibcon#end of sib2, iclass 39, count 0 2006.281.08:12:31.37#ibcon#*after write, iclass 39, count 0 2006.281.08:12:31.37#ibcon#*before return 0, iclass 39, count 0 2006.281.08:12:31.37#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:12:31.37#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.281.08:12:31.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:12:31.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:12:31.37$vc4f8/valo=7,832.99 2006.281.08:12:31.37#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.281.08:12:31.37#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.281.08:12:31.37#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:31.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:12:31.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:12:31.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:12:31.38#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:12:31.38#ibcon#first serial, iclass 3, count 0 2006.281.08:12:31.38#ibcon#enter sib2, iclass 3, count 0 2006.281.08:12:31.38#ibcon#flushed, iclass 3, count 0 2006.281.08:12:31.38#ibcon#about to write, iclass 3, count 0 2006.281.08:12:31.38#ibcon#wrote, iclass 3, count 0 2006.281.08:12:31.38#ibcon#about to read 3, iclass 3, count 0 2006.281.08:12:31.39#ibcon#read 3, iclass 3, count 0 2006.281.08:12:31.39#ibcon#about to read 4, iclass 3, count 0 2006.281.08:12:31.39#ibcon#read 4, iclass 3, count 0 2006.281.08:12:31.39#ibcon#about to read 5, iclass 3, count 0 2006.281.08:12:31.39#ibcon#read 5, iclass 3, count 0 2006.281.08:12:31.39#ibcon#about to read 6, iclass 3, count 0 2006.281.08:12:31.39#ibcon#read 6, iclass 3, count 0 2006.281.08:12:31.39#ibcon#end of sib2, iclass 3, count 0 2006.281.08:12:31.39#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:12:31.39#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:12:31.39#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:12:31.39#ibcon#*before write, iclass 3, count 0 2006.281.08:12:31.39#ibcon#enter sib2, iclass 3, count 0 2006.281.08:12:31.39#ibcon#flushed, iclass 3, count 0 2006.281.08:12:31.39#ibcon#about to write, iclass 3, count 0 2006.281.08:12:31.39#ibcon#wrote, iclass 3, count 0 2006.281.08:12:31.39#ibcon#about to read 3, iclass 3, count 0 2006.281.08:12:31.44#ibcon#read 3, iclass 3, count 0 2006.281.08:12:31.44#ibcon#about to read 4, iclass 3, count 0 2006.281.08:12:31.44#ibcon#read 4, iclass 3, count 0 2006.281.08:12:31.44#ibcon#about to read 5, iclass 3, count 0 2006.281.08:12:31.44#ibcon#read 5, iclass 3, count 0 2006.281.08:12:31.44#ibcon#about to read 6, iclass 3, count 0 2006.281.08:12:31.44#ibcon#read 6, iclass 3, count 0 2006.281.08:12:31.44#ibcon#end of sib2, iclass 3, count 0 2006.281.08:12:31.44#ibcon#*after write, iclass 3, count 0 2006.281.08:12:31.44#ibcon#*before return 0, iclass 3, count 0 2006.281.08:12:31.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:12:31.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.281.08:12:31.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:12:31.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:12:31.44$vc4f8/va=7,6 2006.281.08:12:31.44#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.281.08:12:31.44#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.281.08:12:31.44#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:31.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:12:31.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:12:31.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:12:31.48#ibcon#enter wrdev, iclass 5, count 2 2006.281.08:12:31.48#ibcon#first serial, iclass 5, count 2 2006.281.08:12:31.48#ibcon#enter sib2, iclass 5, count 2 2006.281.08:12:31.48#ibcon#flushed, iclass 5, count 2 2006.281.08:12:31.48#ibcon#about to write, iclass 5, count 2 2006.281.08:12:31.48#ibcon#wrote, iclass 5, count 2 2006.281.08:12:31.48#ibcon#about to read 3, iclass 5, count 2 2006.281.08:12:31.51#ibcon#read 3, iclass 5, count 2 2006.281.08:12:31.51#ibcon#about to read 4, iclass 5, count 2 2006.281.08:12:31.51#ibcon#read 4, iclass 5, count 2 2006.281.08:12:31.51#ibcon#about to read 5, iclass 5, count 2 2006.281.08:12:31.51#ibcon#read 5, iclass 5, count 2 2006.281.08:12:31.51#ibcon#about to read 6, iclass 5, count 2 2006.281.08:12:31.51#ibcon#read 6, iclass 5, count 2 2006.281.08:12:31.51#ibcon#end of sib2, iclass 5, count 2 2006.281.08:12:31.51#ibcon#*mode == 0, iclass 5, count 2 2006.281.08:12:31.51#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.281.08:12:31.51#ibcon#[25=AT07-06\r\n] 2006.281.08:12:31.51#ibcon#*before write, iclass 5, count 2 2006.281.08:12:31.51#ibcon#enter sib2, iclass 5, count 2 2006.281.08:12:31.51#ibcon#flushed, iclass 5, count 2 2006.281.08:12:31.51#ibcon#about to write, iclass 5, count 2 2006.281.08:12:31.51#ibcon#wrote, iclass 5, count 2 2006.281.08:12:31.51#ibcon#about to read 3, iclass 5, count 2 2006.281.08:12:31.54#ibcon#read 3, iclass 5, count 2 2006.281.08:12:31.54#ibcon#about to read 4, iclass 5, count 2 2006.281.08:12:31.54#ibcon#read 4, iclass 5, count 2 2006.281.08:12:31.54#ibcon#about to read 5, iclass 5, count 2 2006.281.08:12:31.54#ibcon#read 5, iclass 5, count 2 2006.281.08:12:31.54#ibcon#about to read 6, iclass 5, count 2 2006.281.08:12:31.54#ibcon#read 6, iclass 5, count 2 2006.281.08:12:31.54#ibcon#end of sib2, iclass 5, count 2 2006.281.08:12:31.54#ibcon#*after write, iclass 5, count 2 2006.281.08:12:31.54#ibcon#*before return 0, iclass 5, count 2 2006.281.08:12:31.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:12:31.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.281.08:12:31.54#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.281.08:12:31.54#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:31.54#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:12:31.65#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:12:31.65#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:12:31.65#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:12:31.65#ibcon#first serial, iclass 5, count 0 2006.281.08:12:31.65#ibcon#enter sib2, iclass 5, count 0 2006.281.08:12:31.65#ibcon#flushed, iclass 5, count 0 2006.281.08:12:31.65#ibcon#about to write, iclass 5, count 0 2006.281.08:12:31.65#ibcon#wrote, iclass 5, count 0 2006.281.08:12:31.65#ibcon#about to read 3, iclass 5, count 0 2006.281.08:12:31.67#ibcon#read 3, iclass 5, count 0 2006.281.08:12:31.67#ibcon#about to read 4, iclass 5, count 0 2006.281.08:12:31.67#ibcon#read 4, iclass 5, count 0 2006.281.08:12:31.67#ibcon#about to read 5, iclass 5, count 0 2006.281.08:12:31.67#ibcon#read 5, iclass 5, count 0 2006.281.08:12:31.67#ibcon#about to read 6, iclass 5, count 0 2006.281.08:12:31.67#ibcon#read 6, iclass 5, count 0 2006.281.08:12:31.67#ibcon#end of sib2, iclass 5, count 0 2006.281.08:12:31.67#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:12:31.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:12:31.67#ibcon#[25=USB\r\n] 2006.281.08:12:31.67#ibcon#*before write, iclass 5, count 0 2006.281.08:12:31.67#ibcon#enter sib2, iclass 5, count 0 2006.281.08:12:31.67#ibcon#flushed, iclass 5, count 0 2006.281.08:12:31.67#ibcon#about to write, iclass 5, count 0 2006.281.08:12:31.67#ibcon#wrote, iclass 5, count 0 2006.281.08:12:31.67#ibcon#about to read 3, iclass 5, count 0 2006.281.08:12:31.71#ibcon#read 3, iclass 5, count 0 2006.281.08:12:31.71#ibcon#about to read 4, iclass 5, count 0 2006.281.08:12:31.71#ibcon#read 4, iclass 5, count 0 2006.281.08:12:31.71#ibcon#about to read 5, iclass 5, count 0 2006.281.08:12:31.71#ibcon#read 5, iclass 5, count 0 2006.281.08:12:31.71#ibcon#about to read 6, iclass 5, count 0 2006.281.08:12:31.71#ibcon#read 6, iclass 5, count 0 2006.281.08:12:31.71#ibcon#end of sib2, iclass 5, count 0 2006.281.08:12:31.71#ibcon#*after write, iclass 5, count 0 2006.281.08:12:31.71#ibcon#*before return 0, iclass 5, count 0 2006.281.08:12:31.71#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:12:31.71#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.281.08:12:31.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:12:31.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:12:31.71$vc4f8/valo=8,852.99 2006.281.08:12:31.71#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:12:31.71#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:12:31.71#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:31.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:12:31.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:12:31.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:12:31.71#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:12:31.71#ibcon#first serial, iclass 7, count 0 2006.281.08:12:31.71#ibcon#enter sib2, iclass 7, count 0 2006.281.08:12:31.71#ibcon#flushed, iclass 7, count 0 2006.281.08:12:31.71#ibcon#about to write, iclass 7, count 0 2006.281.08:12:31.71#ibcon#wrote, iclass 7, count 0 2006.281.08:12:31.71#ibcon#about to read 3, iclass 7, count 0 2006.281.08:12:31.72#ibcon#read 3, iclass 7, count 0 2006.281.08:12:31.72#ibcon#about to read 4, iclass 7, count 0 2006.281.08:12:31.72#ibcon#read 4, iclass 7, count 0 2006.281.08:12:31.72#ibcon#about to read 5, iclass 7, count 0 2006.281.08:12:31.72#ibcon#read 5, iclass 7, count 0 2006.281.08:12:31.72#ibcon#about to read 6, iclass 7, count 0 2006.281.08:12:31.72#ibcon#read 6, iclass 7, count 0 2006.281.08:12:31.72#ibcon#end of sib2, iclass 7, count 0 2006.281.08:12:31.72#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:12:31.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:12:31.72#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:12:31.72#ibcon#*before write, iclass 7, count 0 2006.281.08:12:31.72#ibcon#enter sib2, iclass 7, count 0 2006.281.08:12:31.72#ibcon#flushed, iclass 7, count 0 2006.281.08:12:31.74#ibcon#about to write, iclass 7, count 0 2006.281.08:12:31.74#ibcon#wrote, iclass 7, count 0 2006.281.08:12:31.74#ibcon#about to read 3, iclass 7, count 0 2006.281.08:12:31.78#ibcon#read 3, iclass 7, count 0 2006.281.08:12:31.78#ibcon#about to read 4, iclass 7, count 0 2006.281.08:12:31.78#ibcon#read 4, iclass 7, count 0 2006.281.08:12:31.78#ibcon#about to read 5, iclass 7, count 0 2006.281.08:12:31.78#ibcon#read 5, iclass 7, count 0 2006.281.08:12:31.78#ibcon#about to read 6, iclass 7, count 0 2006.281.08:12:31.78#ibcon#read 6, iclass 7, count 0 2006.281.08:12:31.78#ibcon#end of sib2, iclass 7, count 0 2006.281.08:12:31.78#ibcon#*after write, iclass 7, count 0 2006.281.08:12:31.78#ibcon#*before return 0, iclass 7, count 0 2006.281.08:12:31.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:12:31.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:12:31.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:12:31.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:12:31.78$vc4f8/va=8,6 2006.281.08:12:31.78#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.281.08:12:31.78#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.281.08:12:31.78#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:31.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:12:31.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:12:31.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:12:31.84#ibcon#enter wrdev, iclass 11, count 2 2006.281.08:12:31.84#ibcon#first serial, iclass 11, count 2 2006.281.08:12:31.84#ibcon#enter sib2, iclass 11, count 2 2006.281.08:12:31.84#ibcon#flushed, iclass 11, count 2 2006.281.08:12:31.84#ibcon#about to write, iclass 11, count 2 2006.281.08:12:31.84#ibcon#wrote, iclass 11, count 2 2006.281.08:12:31.84#ibcon#about to read 3, iclass 11, count 2 2006.281.08:12:31.85#ibcon#read 3, iclass 11, count 2 2006.281.08:12:31.85#ibcon#about to read 4, iclass 11, count 2 2006.281.08:12:31.85#ibcon#read 4, iclass 11, count 2 2006.281.08:12:31.85#ibcon#about to read 5, iclass 11, count 2 2006.281.08:12:31.85#ibcon#read 5, iclass 11, count 2 2006.281.08:12:31.85#ibcon#about to read 6, iclass 11, count 2 2006.281.08:12:31.85#ibcon#read 6, iclass 11, count 2 2006.281.08:12:31.85#ibcon#end of sib2, iclass 11, count 2 2006.281.08:12:31.85#ibcon#*mode == 0, iclass 11, count 2 2006.281.08:12:31.85#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.281.08:12:31.85#ibcon#[25=AT08-06\r\n] 2006.281.08:12:31.85#ibcon#*before write, iclass 11, count 2 2006.281.08:12:31.85#ibcon#enter sib2, iclass 11, count 2 2006.281.08:12:31.85#ibcon#flushed, iclass 11, count 2 2006.281.08:12:31.85#ibcon#about to write, iclass 11, count 2 2006.281.08:12:31.85#ibcon#wrote, iclass 11, count 2 2006.281.08:12:31.85#ibcon#about to read 3, iclass 11, count 2 2006.281.08:12:31.88#ibcon#read 3, iclass 11, count 2 2006.281.08:12:31.88#ibcon#about to read 4, iclass 11, count 2 2006.281.08:12:31.88#ibcon#read 4, iclass 11, count 2 2006.281.08:12:31.88#ibcon#about to read 5, iclass 11, count 2 2006.281.08:12:31.88#ibcon#read 5, iclass 11, count 2 2006.281.08:12:31.88#ibcon#about to read 6, iclass 11, count 2 2006.281.08:12:31.88#ibcon#read 6, iclass 11, count 2 2006.281.08:12:31.88#ibcon#end of sib2, iclass 11, count 2 2006.281.08:12:31.88#ibcon#*after write, iclass 11, count 2 2006.281.08:12:31.88#ibcon#*before return 0, iclass 11, count 2 2006.281.08:12:31.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:12:31.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.281.08:12:31.88#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.281.08:12:31.88#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:31.88#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:12:32.01#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:12:32.01#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:12:32.01#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:12:32.01#ibcon#first serial, iclass 11, count 0 2006.281.08:12:32.01#ibcon#enter sib2, iclass 11, count 0 2006.281.08:12:32.01#ibcon#flushed, iclass 11, count 0 2006.281.08:12:32.01#ibcon#about to write, iclass 11, count 0 2006.281.08:12:32.01#ibcon#wrote, iclass 11, count 0 2006.281.08:12:32.01#ibcon#about to read 3, iclass 11, count 0 2006.281.08:12:32.02#ibcon#read 3, iclass 11, count 0 2006.281.08:12:32.02#ibcon#about to read 4, iclass 11, count 0 2006.281.08:12:32.02#ibcon#read 4, iclass 11, count 0 2006.281.08:12:32.02#ibcon#about to read 5, iclass 11, count 0 2006.281.08:12:32.02#ibcon#read 5, iclass 11, count 0 2006.281.08:12:32.02#ibcon#about to read 6, iclass 11, count 0 2006.281.08:12:32.02#ibcon#read 6, iclass 11, count 0 2006.281.08:12:32.02#ibcon#end of sib2, iclass 11, count 0 2006.281.08:12:32.02#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:12:32.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:12:32.02#ibcon#[25=USB\r\n] 2006.281.08:12:32.02#ibcon#*before write, iclass 11, count 0 2006.281.08:12:32.02#ibcon#enter sib2, iclass 11, count 0 2006.281.08:12:32.02#ibcon#flushed, iclass 11, count 0 2006.281.08:12:32.02#ibcon#about to write, iclass 11, count 0 2006.281.08:12:32.02#ibcon#wrote, iclass 11, count 0 2006.281.08:12:32.02#ibcon#about to read 3, iclass 11, count 0 2006.281.08:12:32.05#ibcon#read 3, iclass 11, count 0 2006.281.08:12:32.05#ibcon#about to read 4, iclass 11, count 0 2006.281.08:12:32.05#ibcon#read 4, iclass 11, count 0 2006.281.08:12:32.05#ibcon#about to read 5, iclass 11, count 0 2006.281.08:12:32.05#ibcon#read 5, iclass 11, count 0 2006.281.08:12:32.05#ibcon#about to read 6, iclass 11, count 0 2006.281.08:12:32.05#ibcon#read 6, iclass 11, count 0 2006.281.08:12:32.05#ibcon#end of sib2, iclass 11, count 0 2006.281.08:12:32.05#ibcon#*after write, iclass 11, count 0 2006.281.08:12:32.05#ibcon#*before return 0, iclass 11, count 0 2006.281.08:12:32.05#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:12:32.05#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.281.08:12:32.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:12:32.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:12:32.05$vc4f8/vblo=1,632.99 2006.281.08:12:32.05#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.281.08:12:32.05#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.281.08:12:32.05#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:32.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:12:32.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:12:32.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:12:32.06#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:12:32.06#ibcon#first serial, iclass 13, count 0 2006.281.08:12:32.06#ibcon#enter sib2, iclass 13, count 0 2006.281.08:12:32.06#ibcon#flushed, iclass 13, count 0 2006.281.08:12:32.06#ibcon#about to write, iclass 13, count 0 2006.281.08:12:32.06#ibcon#wrote, iclass 13, count 0 2006.281.08:12:32.06#ibcon#about to read 3, iclass 13, count 0 2006.281.08:12:32.07#ibcon#read 3, iclass 13, count 0 2006.281.08:12:32.07#ibcon#about to read 4, iclass 13, count 0 2006.281.08:12:32.07#ibcon#read 4, iclass 13, count 0 2006.281.08:12:32.07#ibcon#about to read 5, iclass 13, count 0 2006.281.08:12:32.07#ibcon#read 5, iclass 13, count 0 2006.281.08:12:32.07#ibcon#about to read 6, iclass 13, count 0 2006.281.08:12:32.07#ibcon#read 6, iclass 13, count 0 2006.281.08:12:32.07#ibcon#end of sib2, iclass 13, count 0 2006.281.08:12:32.07#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:12:32.07#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:12:32.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:12:32.07#ibcon#*before write, iclass 13, count 0 2006.281.08:12:32.07#ibcon#enter sib2, iclass 13, count 0 2006.281.08:12:32.07#ibcon#flushed, iclass 13, count 0 2006.281.08:12:32.07#ibcon#about to write, iclass 13, count 0 2006.281.08:12:32.07#ibcon#wrote, iclass 13, count 0 2006.281.08:12:32.07#ibcon#about to read 3, iclass 13, count 0 2006.281.08:12:32.11#ibcon#read 3, iclass 13, count 0 2006.281.08:12:32.11#ibcon#about to read 4, iclass 13, count 0 2006.281.08:12:32.11#ibcon#read 4, iclass 13, count 0 2006.281.08:12:32.11#ibcon#about to read 5, iclass 13, count 0 2006.281.08:12:32.11#ibcon#read 5, iclass 13, count 0 2006.281.08:12:32.11#ibcon#about to read 6, iclass 13, count 0 2006.281.08:12:32.11#ibcon#read 6, iclass 13, count 0 2006.281.08:12:32.11#ibcon#end of sib2, iclass 13, count 0 2006.281.08:12:32.11#ibcon#*after write, iclass 13, count 0 2006.281.08:12:32.11#ibcon#*before return 0, iclass 13, count 0 2006.281.08:12:32.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:12:32.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.281.08:12:32.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:12:32.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:12:32.11$vc4f8/vb=1,4 2006.281.08:12:32.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.281.08:12:32.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.281.08:12:32.11#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:32.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:12:32.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:12:32.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:12:32.11#ibcon#enter wrdev, iclass 15, count 2 2006.281.08:12:32.11#ibcon#first serial, iclass 15, count 2 2006.281.08:12:32.11#ibcon#enter sib2, iclass 15, count 2 2006.281.08:12:32.12#ibcon#flushed, iclass 15, count 2 2006.281.08:12:32.12#ibcon#about to write, iclass 15, count 2 2006.281.08:12:32.12#ibcon#wrote, iclass 15, count 2 2006.281.08:12:32.12#ibcon#about to read 3, iclass 15, count 2 2006.281.08:12:32.13#ibcon#read 3, iclass 15, count 2 2006.281.08:12:32.15#ibcon#about to read 4, iclass 15, count 2 2006.281.08:12:32.15#ibcon#read 4, iclass 15, count 2 2006.281.08:12:32.15#ibcon#about to read 5, iclass 15, count 2 2006.281.08:12:32.15#ibcon#read 5, iclass 15, count 2 2006.281.08:12:32.15#ibcon#about to read 6, iclass 15, count 2 2006.281.08:12:32.15#ibcon#read 6, iclass 15, count 2 2006.281.08:12:32.15#ibcon#end of sib2, iclass 15, count 2 2006.281.08:12:32.15#ibcon#*mode == 0, iclass 15, count 2 2006.281.08:12:32.15#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.281.08:12:32.15#ibcon#[27=AT01-04\r\n] 2006.281.08:12:32.15#ibcon#*before write, iclass 15, count 2 2006.281.08:12:32.15#ibcon#enter sib2, iclass 15, count 2 2006.281.08:12:32.15#ibcon#flushed, iclass 15, count 2 2006.281.08:12:32.15#ibcon#about to write, iclass 15, count 2 2006.281.08:12:32.15#ibcon#wrote, iclass 15, count 2 2006.281.08:12:32.15#ibcon#about to read 3, iclass 15, count 2 2006.281.08:12:32.17#ibcon#read 3, iclass 15, count 2 2006.281.08:12:32.17#ibcon#about to read 4, iclass 15, count 2 2006.281.08:12:32.17#ibcon#read 4, iclass 15, count 2 2006.281.08:12:32.17#ibcon#about to read 5, iclass 15, count 2 2006.281.08:12:32.17#ibcon#read 5, iclass 15, count 2 2006.281.08:12:32.17#ibcon#about to read 6, iclass 15, count 2 2006.281.08:12:32.17#ibcon#read 6, iclass 15, count 2 2006.281.08:12:32.17#ibcon#end of sib2, iclass 15, count 2 2006.281.08:12:32.17#ibcon#*after write, iclass 15, count 2 2006.281.08:12:32.17#ibcon#*before return 0, iclass 15, count 2 2006.281.08:12:32.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:12:32.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.281.08:12:32.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.281.08:12:32.17#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:32.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:12:32.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:12:32.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:12:32.29#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:12:32.29#ibcon#first serial, iclass 15, count 0 2006.281.08:12:32.29#ibcon#enter sib2, iclass 15, count 0 2006.281.08:12:32.29#ibcon#flushed, iclass 15, count 0 2006.281.08:12:32.29#ibcon#about to write, iclass 15, count 0 2006.281.08:12:32.29#ibcon#wrote, iclass 15, count 0 2006.281.08:12:32.29#ibcon#about to read 3, iclass 15, count 0 2006.281.08:12:32.31#ibcon#read 3, iclass 15, count 0 2006.281.08:12:32.31#ibcon#about to read 4, iclass 15, count 0 2006.281.08:12:32.31#ibcon#read 4, iclass 15, count 0 2006.281.08:12:32.31#ibcon#about to read 5, iclass 15, count 0 2006.281.08:12:32.31#ibcon#read 5, iclass 15, count 0 2006.281.08:12:32.31#ibcon#about to read 6, iclass 15, count 0 2006.281.08:12:32.31#ibcon#read 6, iclass 15, count 0 2006.281.08:12:32.31#ibcon#end of sib2, iclass 15, count 0 2006.281.08:12:32.31#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:12:32.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:12:32.31#ibcon#[27=USB\r\n] 2006.281.08:12:32.31#ibcon#*before write, iclass 15, count 0 2006.281.08:12:32.31#ibcon#enter sib2, iclass 15, count 0 2006.281.08:12:32.31#ibcon#flushed, iclass 15, count 0 2006.281.08:12:32.31#ibcon#about to write, iclass 15, count 0 2006.281.08:12:32.31#ibcon#wrote, iclass 15, count 0 2006.281.08:12:32.31#ibcon#about to read 3, iclass 15, count 0 2006.281.08:12:32.34#ibcon#read 3, iclass 15, count 0 2006.281.08:12:32.34#ibcon#about to read 4, iclass 15, count 0 2006.281.08:12:32.34#ibcon#read 4, iclass 15, count 0 2006.281.08:12:32.34#ibcon#about to read 5, iclass 15, count 0 2006.281.08:12:32.34#ibcon#read 5, iclass 15, count 0 2006.281.08:12:32.34#ibcon#about to read 6, iclass 15, count 0 2006.281.08:12:32.34#ibcon#read 6, iclass 15, count 0 2006.281.08:12:32.34#ibcon#end of sib2, iclass 15, count 0 2006.281.08:12:32.34#ibcon#*after write, iclass 15, count 0 2006.281.08:12:32.34#ibcon#*before return 0, iclass 15, count 0 2006.281.08:12:32.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:12:32.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.281.08:12:32.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:12:32.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:12:32.34$vc4f8/vblo=2,640.99 2006.281.08:12:32.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:12:32.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:12:32.34#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:32.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:32.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:32.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:32.34#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:12:32.34#ibcon#first serial, iclass 17, count 0 2006.281.08:12:32.35#ibcon#enter sib2, iclass 17, count 0 2006.281.08:12:32.35#ibcon#flushed, iclass 17, count 0 2006.281.08:12:32.35#ibcon#about to write, iclass 17, count 0 2006.281.08:12:32.35#ibcon#wrote, iclass 17, count 0 2006.281.08:12:32.35#ibcon#about to read 3, iclass 17, count 0 2006.281.08:12:32.36#ibcon#read 3, iclass 17, count 0 2006.281.08:12:32.36#ibcon#about to read 4, iclass 17, count 0 2006.281.08:12:32.36#ibcon#read 4, iclass 17, count 0 2006.281.08:12:32.36#ibcon#about to read 5, iclass 17, count 0 2006.281.08:12:32.36#ibcon#read 5, iclass 17, count 0 2006.281.08:12:32.36#ibcon#about to read 6, iclass 17, count 0 2006.281.08:12:32.36#ibcon#read 6, iclass 17, count 0 2006.281.08:12:32.36#ibcon#end of sib2, iclass 17, count 0 2006.281.08:12:32.36#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:12:32.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:12:32.36#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:12:32.36#ibcon#*before write, iclass 17, count 0 2006.281.08:12:32.36#ibcon#enter sib2, iclass 17, count 0 2006.281.08:12:32.36#ibcon#flushed, iclass 17, count 0 2006.281.08:12:32.36#ibcon#about to write, iclass 17, count 0 2006.281.08:12:32.36#ibcon#wrote, iclass 17, count 0 2006.281.08:12:32.36#ibcon#about to read 3, iclass 17, count 0 2006.281.08:12:32.41#ibcon#read 3, iclass 17, count 0 2006.281.08:12:32.41#ibcon#about to read 4, iclass 17, count 0 2006.281.08:12:32.41#ibcon#read 4, iclass 17, count 0 2006.281.08:12:32.41#ibcon#about to read 5, iclass 17, count 0 2006.281.08:12:32.41#ibcon#read 5, iclass 17, count 0 2006.281.08:12:32.41#ibcon#about to read 6, iclass 17, count 0 2006.281.08:12:32.41#ibcon#read 6, iclass 17, count 0 2006.281.08:12:32.41#ibcon#end of sib2, iclass 17, count 0 2006.281.08:12:32.41#ibcon#*after write, iclass 17, count 0 2006.281.08:12:32.41#ibcon#*before return 0, iclass 17, count 0 2006.281.08:12:32.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:32.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:12:32.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:12:32.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:12:32.41$vc4f8/vb=2,5 2006.281.08:12:32.41#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.281.08:12:32.41#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.281.08:12:32.41#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:32.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:32.45#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:32.45#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:32.45#ibcon#enter wrdev, iclass 19, count 2 2006.281.08:12:32.45#ibcon#first serial, iclass 19, count 2 2006.281.08:12:32.45#ibcon#enter sib2, iclass 19, count 2 2006.281.08:12:32.45#ibcon#flushed, iclass 19, count 2 2006.281.08:12:32.45#ibcon#about to write, iclass 19, count 2 2006.281.08:12:32.45#ibcon#wrote, iclass 19, count 2 2006.281.08:12:32.45#ibcon#about to read 3, iclass 19, count 2 2006.281.08:12:32.47#ibcon#read 3, iclass 19, count 2 2006.281.08:12:32.47#ibcon#about to read 4, iclass 19, count 2 2006.281.08:12:32.47#ibcon#read 4, iclass 19, count 2 2006.281.08:12:32.47#ibcon#about to read 5, iclass 19, count 2 2006.281.08:12:32.47#ibcon#read 5, iclass 19, count 2 2006.281.08:12:32.47#ibcon#about to read 6, iclass 19, count 2 2006.281.08:12:32.47#ibcon#read 6, iclass 19, count 2 2006.281.08:12:32.47#ibcon#end of sib2, iclass 19, count 2 2006.281.08:12:32.47#ibcon#*mode == 0, iclass 19, count 2 2006.281.08:12:32.47#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.281.08:12:32.47#ibcon#[27=AT02-05\r\n] 2006.281.08:12:32.47#ibcon#*before write, iclass 19, count 2 2006.281.08:12:32.47#ibcon#enter sib2, iclass 19, count 2 2006.281.08:12:32.47#ibcon#flushed, iclass 19, count 2 2006.281.08:12:32.47#ibcon#about to write, iclass 19, count 2 2006.281.08:12:32.47#ibcon#wrote, iclass 19, count 2 2006.281.08:12:32.47#ibcon#about to read 3, iclass 19, count 2 2006.281.08:12:32.51#ibcon#read 3, iclass 19, count 2 2006.281.08:12:32.51#ibcon#about to read 4, iclass 19, count 2 2006.281.08:12:32.51#ibcon#read 4, iclass 19, count 2 2006.281.08:12:32.51#ibcon#about to read 5, iclass 19, count 2 2006.281.08:12:32.51#ibcon#read 5, iclass 19, count 2 2006.281.08:12:32.51#ibcon#about to read 6, iclass 19, count 2 2006.281.08:12:32.51#ibcon#read 6, iclass 19, count 2 2006.281.08:12:32.51#ibcon#end of sib2, iclass 19, count 2 2006.281.08:12:32.51#ibcon#*after write, iclass 19, count 2 2006.281.08:12:32.51#ibcon#*before return 0, iclass 19, count 2 2006.281.08:12:32.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:32.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.281.08:12:32.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.281.08:12:32.51#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:32.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:32.62#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:32.62#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:32.62#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:12:32.62#ibcon#first serial, iclass 19, count 0 2006.281.08:12:32.62#ibcon#enter sib2, iclass 19, count 0 2006.281.08:12:32.62#ibcon#flushed, iclass 19, count 0 2006.281.08:12:32.62#ibcon#about to write, iclass 19, count 0 2006.281.08:12:32.62#ibcon#wrote, iclass 19, count 0 2006.281.08:12:32.62#ibcon#about to read 3, iclass 19, count 0 2006.281.08:12:32.64#ibcon#read 3, iclass 19, count 0 2006.281.08:12:32.64#ibcon#about to read 4, iclass 19, count 0 2006.281.08:12:32.64#ibcon#read 4, iclass 19, count 0 2006.281.08:12:32.64#ibcon#about to read 5, iclass 19, count 0 2006.281.08:12:32.64#ibcon#read 5, iclass 19, count 0 2006.281.08:12:32.64#ibcon#about to read 6, iclass 19, count 0 2006.281.08:12:32.64#ibcon#read 6, iclass 19, count 0 2006.281.08:12:32.64#ibcon#end of sib2, iclass 19, count 0 2006.281.08:12:32.64#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:12:32.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:12:32.64#ibcon#[27=USB\r\n] 2006.281.08:12:32.64#ibcon#*before write, iclass 19, count 0 2006.281.08:12:32.64#ibcon#enter sib2, iclass 19, count 0 2006.281.08:12:32.64#ibcon#flushed, iclass 19, count 0 2006.281.08:12:32.64#ibcon#about to write, iclass 19, count 0 2006.281.08:12:32.64#ibcon#wrote, iclass 19, count 0 2006.281.08:12:32.64#ibcon#about to read 3, iclass 19, count 0 2006.281.08:12:32.67#ibcon#read 3, iclass 19, count 0 2006.281.08:12:32.67#ibcon#about to read 4, iclass 19, count 0 2006.281.08:12:32.67#ibcon#read 4, iclass 19, count 0 2006.281.08:12:32.67#ibcon#about to read 5, iclass 19, count 0 2006.281.08:12:32.67#ibcon#read 5, iclass 19, count 0 2006.281.08:12:32.67#ibcon#about to read 6, iclass 19, count 0 2006.281.08:12:32.67#ibcon#read 6, iclass 19, count 0 2006.281.08:12:32.67#ibcon#end of sib2, iclass 19, count 0 2006.281.08:12:32.67#ibcon#*after write, iclass 19, count 0 2006.281.08:12:32.67#ibcon#*before return 0, iclass 19, count 0 2006.281.08:12:32.67#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:32.67#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.281.08:12:32.67#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:12:32.67#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:12:32.67$vc4f8/vblo=3,656.99 2006.281.08:12:32.67#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.281.08:12:32.67#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.281.08:12:32.67#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:32.67#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:32.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:32.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:32.67#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:12:32.67#ibcon#first serial, iclass 21, count 0 2006.281.08:12:32.68#ibcon#enter sib2, iclass 21, count 0 2006.281.08:12:32.68#ibcon#flushed, iclass 21, count 0 2006.281.08:12:32.68#ibcon#about to write, iclass 21, count 0 2006.281.08:12:32.68#ibcon#wrote, iclass 21, count 0 2006.281.08:12:32.68#ibcon#about to read 3, iclass 21, count 0 2006.281.08:12:32.69#ibcon#read 3, iclass 21, count 0 2006.281.08:12:32.69#ibcon#about to read 4, iclass 21, count 0 2006.281.08:12:32.69#ibcon#read 4, iclass 21, count 0 2006.281.08:12:32.69#ibcon#about to read 5, iclass 21, count 0 2006.281.08:12:32.69#ibcon#read 5, iclass 21, count 0 2006.281.08:12:32.69#ibcon#about to read 6, iclass 21, count 0 2006.281.08:12:32.69#ibcon#read 6, iclass 21, count 0 2006.281.08:12:32.69#ibcon#end of sib2, iclass 21, count 0 2006.281.08:12:32.69#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:12:32.69#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:12:32.69#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:12:32.69#ibcon#*before write, iclass 21, count 0 2006.281.08:12:32.69#ibcon#enter sib2, iclass 21, count 0 2006.281.08:12:32.69#ibcon#flushed, iclass 21, count 0 2006.281.08:12:32.69#ibcon#about to write, iclass 21, count 0 2006.281.08:12:32.69#ibcon#wrote, iclass 21, count 0 2006.281.08:12:32.69#ibcon#about to read 3, iclass 21, count 0 2006.281.08:12:32.74#ibcon#read 3, iclass 21, count 0 2006.281.08:12:32.74#ibcon#about to read 4, iclass 21, count 0 2006.281.08:12:32.74#ibcon#read 4, iclass 21, count 0 2006.281.08:12:32.74#ibcon#about to read 5, iclass 21, count 0 2006.281.08:12:32.74#ibcon#read 5, iclass 21, count 0 2006.281.08:12:32.74#ibcon#about to read 6, iclass 21, count 0 2006.281.08:12:32.74#ibcon#read 6, iclass 21, count 0 2006.281.08:12:32.74#ibcon#end of sib2, iclass 21, count 0 2006.281.08:12:32.74#ibcon#*after write, iclass 21, count 0 2006.281.08:12:32.74#ibcon#*before return 0, iclass 21, count 0 2006.281.08:12:32.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:32.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.281.08:12:32.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:12:32.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:12:32.74$vc4f8/vb=3,4 2006.281.08:12:32.75#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.281.08:12:32.75#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.281.08:12:32.75#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:32.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:32.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:32.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:32.78#ibcon#enter wrdev, iclass 23, count 2 2006.281.08:12:32.78#ibcon#first serial, iclass 23, count 2 2006.281.08:12:32.78#ibcon#enter sib2, iclass 23, count 2 2006.281.08:12:32.78#ibcon#flushed, iclass 23, count 2 2006.281.08:12:32.78#ibcon#about to write, iclass 23, count 2 2006.281.08:12:32.78#ibcon#wrote, iclass 23, count 2 2006.281.08:12:32.78#ibcon#about to read 3, iclass 23, count 2 2006.281.08:12:32.80#ibcon#read 3, iclass 23, count 2 2006.281.08:12:32.80#ibcon#about to read 4, iclass 23, count 2 2006.281.08:12:32.80#ibcon#read 4, iclass 23, count 2 2006.281.08:12:32.80#ibcon#about to read 5, iclass 23, count 2 2006.281.08:12:32.80#ibcon#read 5, iclass 23, count 2 2006.281.08:12:32.80#ibcon#about to read 6, iclass 23, count 2 2006.281.08:12:32.80#ibcon#read 6, iclass 23, count 2 2006.281.08:12:32.80#ibcon#end of sib2, iclass 23, count 2 2006.281.08:12:32.80#ibcon#*mode == 0, iclass 23, count 2 2006.281.08:12:32.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.281.08:12:32.80#ibcon#[27=AT03-04\r\n] 2006.281.08:12:32.80#ibcon#*before write, iclass 23, count 2 2006.281.08:12:32.80#ibcon#enter sib2, iclass 23, count 2 2006.281.08:12:32.80#ibcon#flushed, iclass 23, count 2 2006.281.08:12:32.80#ibcon#about to write, iclass 23, count 2 2006.281.08:12:32.80#ibcon#wrote, iclass 23, count 2 2006.281.08:12:32.80#ibcon#about to read 3, iclass 23, count 2 2006.281.08:12:32.83#ibcon#read 3, iclass 23, count 2 2006.281.08:12:32.83#ibcon#about to read 4, iclass 23, count 2 2006.281.08:12:32.83#ibcon#read 4, iclass 23, count 2 2006.281.08:12:32.83#ibcon#about to read 5, iclass 23, count 2 2006.281.08:12:32.83#ibcon#read 5, iclass 23, count 2 2006.281.08:12:32.83#ibcon#about to read 6, iclass 23, count 2 2006.281.08:12:32.83#ibcon#read 6, iclass 23, count 2 2006.281.08:12:32.83#ibcon#end of sib2, iclass 23, count 2 2006.281.08:12:32.83#ibcon#*after write, iclass 23, count 2 2006.281.08:12:32.83#ibcon#*before return 0, iclass 23, count 2 2006.281.08:12:32.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:32.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.281.08:12:32.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.281.08:12:32.83#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:32.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:32.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:32.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:32.95#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:12:32.95#ibcon#first serial, iclass 23, count 0 2006.281.08:12:32.95#ibcon#enter sib2, iclass 23, count 0 2006.281.08:12:32.95#ibcon#flushed, iclass 23, count 0 2006.281.08:12:32.95#ibcon#about to write, iclass 23, count 0 2006.281.08:12:32.95#ibcon#wrote, iclass 23, count 0 2006.281.08:12:32.95#ibcon#about to read 3, iclass 23, count 0 2006.281.08:12:32.97#ibcon#read 3, iclass 23, count 0 2006.281.08:12:32.97#ibcon#about to read 4, iclass 23, count 0 2006.281.08:12:32.97#ibcon#read 4, iclass 23, count 0 2006.281.08:12:32.97#ibcon#about to read 5, iclass 23, count 0 2006.281.08:12:32.97#ibcon#read 5, iclass 23, count 0 2006.281.08:12:32.97#ibcon#about to read 6, iclass 23, count 0 2006.281.08:12:32.97#ibcon#read 6, iclass 23, count 0 2006.281.08:12:32.97#ibcon#end of sib2, iclass 23, count 0 2006.281.08:12:32.97#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:12:32.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:12:32.97#ibcon#[27=USB\r\n] 2006.281.08:12:32.97#ibcon#*before write, iclass 23, count 0 2006.281.08:12:32.97#ibcon#enter sib2, iclass 23, count 0 2006.281.08:12:32.97#ibcon#flushed, iclass 23, count 0 2006.281.08:12:32.97#ibcon#about to write, iclass 23, count 0 2006.281.08:12:32.97#ibcon#wrote, iclass 23, count 0 2006.281.08:12:32.97#ibcon#about to read 3, iclass 23, count 0 2006.281.08:12:33.01#ibcon#read 3, iclass 23, count 0 2006.281.08:12:33.01#ibcon#about to read 4, iclass 23, count 0 2006.281.08:12:33.01#ibcon#read 4, iclass 23, count 0 2006.281.08:12:33.01#ibcon#about to read 5, iclass 23, count 0 2006.281.08:12:33.01#ibcon#read 5, iclass 23, count 0 2006.281.08:12:33.01#ibcon#about to read 6, iclass 23, count 0 2006.281.08:12:33.01#ibcon#read 6, iclass 23, count 0 2006.281.08:12:33.01#ibcon#end of sib2, iclass 23, count 0 2006.281.08:12:33.01#ibcon#*after write, iclass 23, count 0 2006.281.08:12:33.01#ibcon#*before return 0, iclass 23, count 0 2006.281.08:12:33.01#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:33.01#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.281.08:12:33.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:12:33.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:12:33.01$vc4f8/vblo=4,712.99 2006.281.08:12:33.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.281.08:12:33.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.281.08:12:33.01#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:33.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:33.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:33.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:33.01#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:12:33.01#ibcon#first serial, iclass 25, count 0 2006.281.08:12:33.01#ibcon#enter sib2, iclass 25, count 0 2006.281.08:12:33.01#ibcon#flushed, iclass 25, count 0 2006.281.08:12:33.01#ibcon#about to write, iclass 25, count 0 2006.281.08:12:33.01#ibcon#wrote, iclass 25, count 0 2006.281.08:12:33.01#ibcon#about to read 3, iclass 25, count 0 2006.281.08:12:33.02#ibcon#read 3, iclass 25, count 0 2006.281.08:12:33.02#ibcon#about to read 4, iclass 25, count 0 2006.281.08:12:33.02#ibcon#read 4, iclass 25, count 0 2006.281.08:12:33.02#ibcon#about to read 5, iclass 25, count 0 2006.281.08:12:33.02#ibcon#read 5, iclass 25, count 0 2006.281.08:12:33.02#ibcon#about to read 6, iclass 25, count 0 2006.281.08:12:33.02#ibcon#read 6, iclass 25, count 0 2006.281.08:12:33.02#ibcon#end of sib2, iclass 25, count 0 2006.281.08:12:33.02#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:12:33.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:12:33.05#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:12:33.05#ibcon#*before write, iclass 25, count 0 2006.281.08:12:33.05#ibcon#enter sib2, iclass 25, count 0 2006.281.08:12:33.05#ibcon#flushed, iclass 25, count 0 2006.281.08:12:33.05#ibcon#about to write, iclass 25, count 0 2006.281.08:12:33.05#ibcon#wrote, iclass 25, count 0 2006.281.08:12:33.05#ibcon#about to read 3, iclass 25, count 0 2006.281.08:12:33.08#ibcon#read 3, iclass 25, count 0 2006.281.08:12:33.08#ibcon#about to read 4, iclass 25, count 0 2006.281.08:12:33.08#ibcon#read 4, iclass 25, count 0 2006.281.08:12:33.08#ibcon#about to read 5, iclass 25, count 0 2006.281.08:12:33.08#ibcon#read 5, iclass 25, count 0 2006.281.08:12:33.08#ibcon#about to read 6, iclass 25, count 0 2006.281.08:12:33.08#ibcon#read 6, iclass 25, count 0 2006.281.08:12:33.08#ibcon#end of sib2, iclass 25, count 0 2006.281.08:12:33.08#ibcon#*after write, iclass 25, count 0 2006.281.08:12:33.08#ibcon#*before return 0, iclass 25, count 0 2006.281.08:12:33.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:33.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.281.08:12:33.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:12:33.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:12:33.08$vc4f8/vb=4,4 2006.281.08:12:33.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.281.08:12:33.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.281.08:12:33.08#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:33.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:33.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:33.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:33.14#ibcon#enter wrdev, iclass 27, count 2 2006.281.08:12:33.14#ibcon#first serial, iclass 27, count 2 2006.281.08:12:33.14#ibcon#enter sib2, iclass 27, count 2 2006.281.08:12:33.14#ibcon#flushed, iclass 27, count 2 2006.281.08:12:33.14#ibcon#about to write, iclass 27, count 2 2006.281.08:12:33.14#ibcon#wrote, iclass 27, count 2 2006.281.08:12:33.14#ibcon#about to read 3, iclass 27, count 2 2006.281.08:12:33.15#ibcon#read 3, iclass 27, count 2 2006.281.08:12:33.15#ibcon#about to read 4, iclass 27, count 2 2006.281.08:12:33.15#ibcon#read 4, iclass 27, count 2 2006.281.08:12:33.15#ibcon#about to read 5, iclass 27, count 2 2006.281.08:12:33.15#ibcon#read 5, iclass 27, count 2 2006.281.08:12:33.15#ibcon#about to read 6, iclass 27, count 2 2006.281.08:12:33.15#ibcon#read 6, iclass 27, count 2 2006.281.08:12:33.15#ibcon#end of sib2, iclass 27, count 2 2006.281.08:12:33.15#ibcon#*mode == 0, iclass 27, count 2 2006.281.08:12:33.15#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.281.08:12:33.15#ibcon#[27=AT04-04\r\n] 2006.281.08:12:33.15#ibcon#*before write, iclass 27, count 2 2006.281.08:12:33.15#ibcon#enter sib2, iclass 27, count 2 2006.281.08:12:33.15#ibcon#flushed, iclass 27, count 2 2006.281.08:12:33.15#ibcon#about to write, iclass 27, count 2 2006.281.08:12:33.15#ibcon#wrote, iclass 27, count 2 2006.281.08:12:33.15#ibcon#about to read 3, iclass 27, count 2 2006.281.08:12:33.18#ibcon#read 3, iclass 27, count 2 2006.281.08:12:33.18#ibcon#about to read 4, iclass 27, count 2 2006.281.08:12:33.18#ibcon#read 4, iclass 27, count 2 2006.281.08:12:33.18#ibcon#about to read 5, iclass 27, count 2 2006.281.08:12:33.18#ibcon#read 5, iclass 27, count 2 2006.281.08:12:33.18#ibcon#about to read 6, iclass 27, count 2 2006.281.08:12:33.18#ibcon#read 6, iclass 27, count 2 2006.281.08:12:33.18#ibcon#end of sib2, iclass 27, count 2 2006.281.08:12:33.18#ibcon#*after write, iclass 27, count 2 2006.281.08:12:33.18#ibcon#*before return 0, iclass 27, count 2 2006.281.08:12:33.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:33.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.281.08:12:33.18#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.281.08:12:33.18#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:33.18#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:33.30#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:33.30#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:33.30#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:12:33.30#ibcon#first serial, iclass 27, count 0 2006.281.08:12:33.30#ibcon#enter sib2, iclass 27, count 0 2006.281.08:12:33.30#ibcon#flushed, iclass 27, count 0 2006.281.08:12:33.30#ibcon#about to write, iclass 27, count 0 2006.281.08:12:33.30#ibcon#wrote, iclass 27, count 0 2006.281.08:12:33.30#ibcon#about to read 3, iclass 27, count 0 2006.281.08:12:33.32#ibcon#read 3, iclass 27, count 0 2006.281.08:12:33.32#ibcon#about to read 4, iclass 27, count 0 2006.281.08:12:33.32#ibcon#read 4, iclass 27, count 0 2006.281.08:12:33.32#ibcon#about to read 5, iclass 27, count 0 2006.281.08:12:33.32#ibcon#read 5, iclass 27, count 0 2006.281.08:12:33.32#ibcon#about to read 6, iclass 27, count 0 2006.281.08:12:33.32#ibcon#read 6, iclass 27, count 0 2006.281.08:12:33.32#ibcon#end of sib2, iclass 27, count 0 2006.281.08:12:33.32#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:12:33.32#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:12:33.32#ibcon#[27=USB\r\n] 2006.281.08:12:33.32#ibcon#*before write, iclass 27, count 0 2006.281.08:12:33.32#ibcon#enter sib2, iclass 27, count 0 2006.281.08:12:33.32#ibcon#flushed, iclass 27, count 0 2006.281.08:12:33.32#ibcon#about to write, iclass 27, count 0 2006.281.08:12:33.32#ibcon#wrote, iclass 27, count 0 2006.281.08:12:33.32#ibcon#about to read 3, iclass 27, count 0 2006.281.08:12:33.35#ibcon#read 3, iclass 27, count 0 2006.281.08:12:33.35#ibcon#about to read 4, iclass 27, count 0 2006.281.08:12:33.35#ibcon#read 4, iclass 27, count 0 2006.281.08:12:33.35#ibcon#about to read 5, iclass 27, count 0 2006.281.08:12:33.35#ibcon#read 5, iclass 27, count 0 2006.281.08:12:33.35#ibcon#about to read 6, iclass 27, count 0 2006.281.08:12:33.35#ibcon#read 6, iclass 27, count 0 2006.281.08:12:33.35#ibcon#end of sib2, iclass 27, count 0 2006.281.08:12:33.35#ibcon#*after write, iclass 27, count 0 2006.281.08:12:33.35#ibcon#*before return 0, iclass 27, count 0 2006.281.08:12:33.35#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:33.35#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.281.08:12:33.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:12:33.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:12:33.35$vc4f8/vblo=5,744.99 2006.281.08:12:33.35#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.281.08:12:33.35#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.281.08:12:33.35#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:33.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:33.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:33.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:33.36#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:12:33.36#ibcon#first serial, iclass 29, count 0 2006.281.08:12:33.36#ibcon#enter sib2, iclass 29, count 0 2006.281.08:12:33.36#ibcon#flushed, iclass 29, count 0 2006.281.08:12:33.36#ibcon#about to write, iclass 29, count 0 2006.281.08:12:33.36#ibcon#wrote, iclass 29, count 0 2006.281.08:12:33.36#ibcon#about to read 3, iclass 29, count 0 2006.281.08:12:33.37#ibcon#read 3, iclass 29, count 0 2006.281.08:12:33.37#ibcon#about to read 4, iclass 29, count 0 2006.281.08:12:33.37#ibcon#read 4, iclass 29, count 0 2006.281.08:12:33.37#ibcon#about to read 5, iclass 29, count 0 2006.281.08:12:33.37#ibcon#read 5, iclass 29, count 0 2006.281.08:12:33.37#ibcon#about to read 6, iclass 29, count 0 2006.281.08:12:33.37#ibcon#read 6, iclass 29, count 0 2006.281.08:12:33.37#ibcon#end of sib2, iclass 29, count 0 2006.281.08:12:33.37#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:12:33.37#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:12:33.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:12:33.37#ibcon#*before write, iclass 29, count 0 2006.281.08:12:33.37#ibcon#enter sib2, iclass 29, count 0 2006.281.08:12:33.37#ibcon#flushed, iclass 29, count 0 2006.281.08:12:33.37#ibcon#about to write, iclass 29, count 0 2006.281.08:12:33.37#ibcon#wrote, iclass 29, count 0 2006.281.08:12:33.37#ibcon#about to read 3, iclass 29, count 0 2006.281.08:12:33.42#ibcon#read 3, iclass 29, count 0 2006.281.08:12:33.42#ibcon#about to read 4, iclass 29, count 0 2006.281.08:12:33.42#ibcon#read 4, iclass 29, count 0 2006.281.08:12:33.42#ibcon#about to read 5, iclass 29, count 0 2006.281.08:12:33.42#ibcon#read 5, iclass 29, count 0 2006.281.08:12:33.42#ibcon#about to read 6, iclass 29, count 0 2006.281.08:12:33.42#ibcon#read 6, iclass 29, count 0 2006.281.08:12:33.42#ibcon#end of sib2, iclass 29, count 0 2006.281.08:12:33.42#ibcon#*after write, iclass 29, count 0 2006.281.08:12:33.42#ibcon#*before return 0, iclass 29, count 0 2006.281.08:12:33.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:33.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.281.08:12:33.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:12:33.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:12:33.42$vc4f8/vb=5,4 2006.281.08:12:33.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.281.08:12:33.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.281.08:12:33.42#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:33.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:33.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:33.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:33.46#ibcon#enter wrdev, iclass 31, count 2 2006.281.08:12:33.46#ibcon#first serial, iclass 31, count 2 2006.281.08:12:33.46#ibcon#enter sib2, iclass 31, count 2 2006.281.08:12:33.46#ibcon#flushed, iclass 31, count 2 2006.281.08:12:33.46#ibcon#about to write, iclass 31, count 2 2006.281.08:12:33.46#ibcon#wrote, iclass 31, count 2 2006.281.08:12:33.46#ibcon#about to read 3, iclass 31, count 2 2006.281.08:12:33.48#ibcon#read 3, iclass 31, count 2 2006.281.08:12:33.48#ibcon#about to read 4, iclass 31, count 2 2006.281.08:12:33.48#ibcon#read 4, iclass 31, count 2 2006.281.08:12:33.48#ibcon#about to read 5, iclass 31, count 2 2006.281.08:12:33.48#ibcon#read 5, iclass 31, count 2 2006.281.08:12:33.48#ibcon#about to read 6, iclass 31, count 2 2006.281.08:12:33.48#ibcon#read 6, iclass 31, count 2 2006.281.08:12:33.48#ibcon#end of sib2, iclass 31, count 2 2006.281.08:12:33.48#ibcon#*mode == 0, iclass 31, count 2 2006.281.08:12:33.48#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.281.08:12:33.48#ibcon#[27=AT05-04\r\n] 2006.281.08:12:33.48#ibcon#*before write, iclass 31, count 2 2006.281.08:12:33.48#ibcon#enter sib2, iclass 31, count 2 2006.281.08:12:33.48#ibcon#flushed, iclass 31, count 2 2006.281.08:12:33.48#ibcon#about to write, iclass 31, count 2 2006.281.08:12:33.48#ibcon#wrote, iclass 31, count 2 2006.281.08:12:33.48#ibcon#about to read 3, iclass 31, count 2 2006.281.08:12:33.52#ibcon#read 3, iclass 31, count 2 2006.281.08:12:33.52#ibcon#about to read 4, iclass 31, count 2 2006.281.08:12:33.52#ibcon#read 4, iclass 31, count 2 2006.281.08:12:33.52#ibcon#about to read 5, iclass 31, count 2 2006.281.08:12:33.52#ibcon#read 5, iclass 31, count 2 2006.281.08:12:33.52#ibcon#about to read 6, iclass 31, count 2 2006.281.08:12:33.52#ibcon#read 6, iclass 31, count 2 2006.281.08:12:33.52#ibcon#end of sib2, iclass 31, count 2 2006.281.08:12:33.52#ibcon#*after write, iclass 31, count 2 2006.281.08:12:33.52#ibcon#*before return 0, iclass 31, count 2 2006.281.08:12:33.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:33.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.281.08:12:33.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.281.08:12:33.52#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:33.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:33.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:33.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:33.63#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:12:33.63#ibcon#first serial, iclass 31, count 0 2006.281.08:12:33.63#ibcon#enter sib2, iclass 31, count 0 2006.281.08:12:33.63#ibcon#flushed, iclass 31, count 0 2006.281.08:12:33.63#ibcon#about to write, iclass 31, count 0 2006.281.08:12:33.63#ibcon#wrote, iclass 31, count 0 2006.281.08:12:33.63#ibcon#about to read 3, iclass 31, count 0 2006.281.08:12:33.65#ibcon#read 3, iclass 31, count 0 2006.281.08:12:33.65#ibcon#about to read 4, iclass 31, count 0 2006.281.08:12:33.65#ibcon#read 4, iclass 31, count 0 2006.281.08:12:33.65#ibcon#about to read 5, iclass 31, count 0 2006.281.08:12:33.65#ibcon#read 5, iclass 31, count 0 2006.281.08:12:33.65#ibcon#about to read 6, iclass 31, count 0 2006.281.08:12:33.65#ibcon#read 6, iclass 31, count 0 2006.281.08:12:33.65#ibcon#end of sib2, iclass 31, count 0 2006.281.08:12:33.65#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:12:33.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:12:33.65#ibcon#[27=USB\r\n] 2006.281.08:12:33.65#ibcon#*before write, iclass 31, count 0 2006.281.08:12:33.65#ibcon#enter sib2, iclass 31, count 0 2006.281.08:12:33.65#ibcon#flushed, iclass 31, count 0 2006.281.08:12:33.65#ibcon#about to write, iclass 31, count 0 2006.281.08:12:33.65#ibcon#wrote, iclass 31, count 0 2006.281.08:12:33.65#ibcon#about to read 3, iclass 31, count 0 2006.281.08:12:33.68#ibcon#read 3, iclass 31, count 0 2006.281.08:12:33.68#ibcon#about to read 4, iclass 31, count 0 2006.281.08:12:33.68#ibcon#read 4, iclass 31, count 0 2006.281.08:12:33.68#ibcon#about to read 5, iclass 31, count 0 2006.281.08:12:33.68#ibcon#read 5, iclass 31, count 0 2006.281.08:12:33.68#ibcon#about to read 6, iclass 31, count 0 2006.281.08:12:33.68#ibcon#read 6, iclass 31, count 0 2006.281.08:12:33.68#ibcon#end of sib2, iclass 31, count 0 2006.281.08:12:33.68#ibcon#*after write, iclass 31, count 0 2006.281.08:12:33.68#ibcon#*before return 0, iclass 31, count 0 2006.281.08:12:33.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:33.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.281.08:12:33.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:12:33.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:12:33.68$vc4f8/vblo=6,752.99 2006.281.08:12:33.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.281.08:12:33.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.281.08:12:33.68#ibcon#ireg 17 cls_cnt 0 2006.281.08:12:33.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:33.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:33.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:33.68#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:12:33.68#ibcon#first serial, iclass 33, count 0 2006.281.08:12:33.69#ibcon#enter sib2, iclass 33, count 0 2006.281.08:12:33.69#ibcon#flushed, iclass 33, count 0 2006.281.08:12:33.69#ibcon#about to write, iclass 33, count 0 2006.281.08:12:33.69#ibcon#wrote, iclass 33, count 0 2006.281.08:12:33.69#ibcon#about to read 3, iclass 33, count 0 2006.281.08:12:33.70#ibcon#read 3, iclass 33, count 0 2006.281.08:12:33.70#ibcon#about to read 4, iclass 33, count 0 2006.281.08:12:33.70#ibcon#read 4, iclass 33, count 0 2006.281.08:12:33.70#ibcon#about to read 5, iclass 33, count 0 2006.281.08:12:33.70#ibcon#read 5, iclass 33, count 0 2006.281.08:12:33.70#ibcon#about to read 6, iclass 33, count 0 2006.281.08:12:33.70#ibcon#read 6, iclass 33, count 0 2006.281.08:12:33.70#ibcon#end of sib2, iclass 33, count 0 2006.281.08:12:33.70#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:12:33.70#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:12:33.70#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:12:33.70#ibcon#*before write, iclass 33, count 0 2006.281.08:12:33.70#ibcon#enter sib2, iclass 33, count 0 2006.281.08:12:33.70#ibcon#flushed, iclass 33, count 0 2006.281.08:12:33.70#ibcon#about to write, iclass 33, count 0 2006.281.08:12:33.70#ibcon#wrote, iclass 33, count 0 2006.281.08:12:33.70#ibcon#about to read 3, iclass 33, count 0 2006.281.08:12:33.75#ibcon#read 3, iclass 33, count 0 2006.281.08:12:33.75#ibcon#about to read 4, iclass 33, count 0 2006.281.08:12:33.75#ibcon#read 4, iclass 33, count 0 2006.281.08:12:33.75#ibcon#about to read 5, iclass 33, count 0 2006.281.08:12:33.75#ibcon#read 5, iclass 33, count 0 2006.281.08:12:33.75#ibcon#about to read 6, iclass 33, count 0 2006.281.08:12:33.75#ibcon#read 6, iclass 33, count 0 2006.281.08:12:33.75#ibcon#end of sib2, iclass 33, count 0 2006.281.08:12:33.75#ibcon#*after write, iclass 33, count 0 2006.281.08:12:33.75#ibcon#*before return 0, iclass 33, count 0 2006.281.08:12:33.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:33.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.281.08:12:33.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:12:33.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:12:33.75$vc4f8/vb=6,4 2006.281.08:12:33.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.281.08:12:33.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.281.08:12:33.76#ibcon#ireg 11 cls_cnt 2 2006.281.08:12:33.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:33.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:33.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:33.80#ibcon#enter wrdev, iclass 35, count 2 2006.281.08:12:33.80#ibcon#first serial, iclass 35, count 2 2006.281.08:12:33.80#ibcon#enter sib2, iclass 35, count 2 2006.281.08:12:33.80#ibcon#flushed, iclass 35, count 2 2006.281.08:12:33.80#ibcon#about to write, iclass 35, count 2 2006.281.08:12:33.80#ibcon#wrote, iclass 35, count 2 2006.281.08:12:33.80#ibcon#about to read 3, iclass 35, count 2 2006.281.08:12:33.82#ibcon#read 3, iclass 35, count 2 2006.281.08:12:33.82#ibcon#about to read 4, iclass 35, count 2 2006.281.08:12:33.82#ibcon#read 4, iclass 35, count 2 2006.281.08:12:33.82#ibcon#about to read 5, iclass 35, count 2 2006.281.08:12:33.82#ibcon#read 5, iclass 35, count 2 2006.281.08:12:33.82#ibcon#about to read 6, iclass 35, count 2 2006.281.08:12:33.82#ibcon#read 6, iclass 35, count 2 2006.281.08:12:33.82#ibcon#end of sib2, iclass 35, count 2 2006.281.08:12:33.82#ibcon#*mode == 0, iclass 35, count 2 2006.281.08:12:33.82#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.281.08:12:33.82#ibcon#[27=AT06-04\r\n] 2006.281.08:12:33.82#ibcon#*before write, iclass 35, count 2 2006.281.08:12:33.82#ibcon#enter sib2, iclass 35, count 2 2006.281.08:12:33.82#ibcon#flushed, iclass 35, count 2 2006.281.08:12:33.82#ibcon#about to write, iclass 35, count 2 2006.281.08:12:33.82#ibcon#wrote, iclass 35, count 2 2006.281.08:12:33.82#ibcon#about to read 3, iclass 35, count 2 2006.281.08:12:33.84#ibcon#read 3, iclass 35, count 2 2006.281.08:12:33.84#ibcon#about to read 4, iclass 35, count 2 2006.281.08:12:33.84#ibcon#read 4, iclass 35, count 2 2006.281.08:12:33.84#ibcon#about to read 5, iclass 35, count 2 2006.281.08:12:33.84#ibcon#read 5, iclass 35, count 2 2006.281.08:12:33.84#ibcon#about to read 6, iclass 35, count 2 2006.281.08:12:33.84#ibcon#read 6, iclass 35, count 2 2006.281.08:12:33.84#ibcon#end of sib2, iclass 35, count 2 2006.281.08:12:33.84#ibcon#*after write, iclass 35, count 2 2006.281.08:12:33.84#ibcon#*before return 0, iclass 35, count 2 2006.281.08:12:33.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:33.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.281.08:12:33.84#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.281.08:12:33.84#ibcon#ireg 7 cls_cnt 0 2006.281.08:12:33.84#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:33.96#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:33.96#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:33.96#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:12:33.96#ibcon#first serial, iclass 35, count 0 2006.281.08:12:33.96#ibcon#enter sib2, iclass 35, count 0 2006.281.08:12:33.96#ibcon#flushed, iclass 35, count 0 2006.281.08:12:33.96#ibcon#about to write, iclass 35, count 0 2006.281.08:12:33.96#ibcon#wrote, iclass 35, count 0 2006.281.08:12:33.96#ibcon#about to read 3, iclass 35, count 0 2006.281.08:12:33.98#ibcon#read 3, iclass 35, count 0 2006.281.08:12:33.98#ibcon#about to read 4, iclass 35, count 0 2006.281.08:12:33.98#ibcon#read 4, iclass 35, count 0 2006.281.08:12:33.98#ibcon#about to read 5, iclass 35, count 0 2006.281.08:12:33.98#ibcon#read 5, iclass 35, count 0 2006.281.08:12:33.98#ibcon#about to read 6, iclass 35, count 0 2006.281.08:12:33.98#ibcon#read 6, iclass 35, count 0 2006.281.08:12:33.98#ibcon#end of sib2, iclass 35, count 0 2006.281.08:12:33.98#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:12:33.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:12:33.98#ibcon#[27=USB\r\n] 2006.281.08:12:33.98#ibcon#*before write, iclass 35, count 0 2006.281.08:12:33.98#ibcon#enter sib2, iclass 35, count 0 2006.281.08:12:33.98#ibcon#flushed, iclass 35, count 0 2006.281.08:12:33.98#ibcon#about to write, iclass 35, count 0 2006.281.08:12:33.98#ibcon#wrote, iclass 35, count 0 2006.281.08:12:33.98#ibcon#about to read 3, iclass 35, count 0 2006.281.08:12:34.02#ibcon#read 3, iclass 35, count 0 2006.281.08:12:34.02#ibcon#about to read 4, iclass 35, count 0 2006.281.08:12:34.02#ibcon#read 4, iclass 35, count 0 2006.281.08:12:34.02#ibcon#about to read 5, iclass 35, count 0 2006.281.08:12:34.02#ibcon#read 5, iclass 35, count 0 2006.281.08:12:34.02#ibcon#about to read 6, iclass 35, count 0 2006.281.08:12:34.02#ibcon#read 6, iclass 35, count 0 2006.281.08:12:34.02#ibcon#end of sib2, iclass 35, count 0 2006.281.08:12:34.02#ibcon#*after write, iclass 35, count 0 2006.281.08:12:34.02#ibcon#*before return 0, iclass 35, count 0 2006.281.08:12:34.02#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:34.02#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.281.08:12:34.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:12:34.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:12:34.02$vc4f8/vabw=wide 2006.281.08:12:34.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.281.08:12:34.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.281.08:12:34.02#ibcon#ireg 8 cls_cnt 0 2006.281.08:12:34.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:34.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:34.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:34.02#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:12:34.02#ibcon#first serial, iclass 37, count 0 2006.281.08:12:34.02#ibcon#enter sib2, iclass 37, count 0 2006.281.08:12:34.02#ibcon#flushed, iclass 37, count 0 2006.281.08:12:34.02#ibcon#about to write, iclass 37, count 0 2006.281.08:12:34.02#ibcon#wrote, iclass 37, count 0 2006.281.08:12:34.02#ibcon#about to read 3, iclass 37, count 0 2006.281.08:12:34.03#ibcon#read 3, iclass 37, count 0 2006.281.08:12:34.03#ibcon#about to read 4, iclass 37, count 0 2006.281.08:12:34.03#ibcon#read 4, iclass 37, count 0 2006.281.08:12:34.03#ibcon#about to read 5, iclass 37, count 0 2006.281.08:12:34.03#ibcon#read 5, iclass 37, count 0 2006.281.08:12:34.03#ibcon#about to read 6, iclass 37, count 0 2006.281.08:12:34.03#ibcon#read 6, iclass 37, count 0 2006.281.08:12:34.03#ibcon#end of sib2, iclass 37, count 0 2006.281.08:12:34.03#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:12:34.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:12:34.06#ibcon#[25=BW32\r\n] 2006.281.08:12:34.06#ibcon#*before write, iclass 37, count 0 2006.281.08:12:34.06#ibcon#enter sib2, iclass 37, count 0 2006.281.08:12:34.06#ibcon#flushed, iclass 37, count 0 2006.281.08:12:34.06#ibcon#about to write, iclass 37, count 0 2006.281.08:12:34.06#ibcon#wrote, iclass 37, count 0 2006.281.08:12:34.06#ibcon#about to read 3, iclass 37, count 0 2006.281.08:12:34.08#ibcon#read 3, iclass 37, count 0 2006.281.08:12:34.08#ibcon#about to read 4, iclass 37, count 0 2006.281.08:12:34.08#ibcon#read 4, iclass 37, count 0 2006.281.08:12:34.08#ibcon#about to read 5, iclass 37, count 0 2006.281.08:12:34.08#ibcon#read 5, iclass 37, count 0 2006.281.08:12:34.08#ibcon#about to read 6, iclass 37, count 0 2006.281.08:12:34.08#ibcon#read 6, iclass 37, count 0 2006.281.08:12:34.08#ibcon#end of sib2, iclass 37, count 0 2006.281.08:12:34.08#ibcon#*after write, iclass 37, count 0 2006.281.08:12:34.08#ibcon#*before return 0, iclass 37, count 0 2006.281.08:12:34.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:34.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.281.08:12:34.08#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:12:34.08#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:12:34.08$vc4f8/vbbw=wide 2006.281.08:12:34.08#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:12:34.08#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:12:34.08#ibcon#ireg 8 cls_cnt 0 2006.281.08:12:34.08#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:12:34.15#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:12:34.15#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:12:34.15#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:12:34.15#ibcon#first serial, iclass 39, count 0 2006.281.08:12:34.15#ibcon#enter sib2, iclass 39, count 0 2006.281.08:12:34.15#ibcon#flushed, iclass 39, count 0 2006.281.08:12:34.15#ibcon#about to write, iclass 39, count 0 2006.281.08:12:34.15#ibcon#wrote, iclass 39, count 0 2006.281.08:12:34.15#ibcon#about to read 3, iclass 39, count 0 2006.281.08:12:34.16#ibcon#read 3, iclass 39, count 0 2006.281.08:12:34.16#ibcon#about to read 4, iclass 39, count 0 2006.281.08:12:34.16#ibcon#read 4, iclass 39, count 0 2006.281.08:12:34.16#ibcon#about to read 5, iclass 39, count 0 2006.281.08:12:34.16#ibcon#read 5, iclass 39, count 0 2006.281.08:12:34.16#ibcon#about to read 6, iclass 39, count 0 2006.281.08:12:34.16#ibcon#read 6, iclass 39, count 0 2006.281.08:12:34.16#ibcon#end of sib2, iclass 39, count 0 2006.281.08:12:34.16#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:12:34.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:12:34.16#ibcon#[27=BW32\r\n] 2006.281.08:12:34.16#ibcon#*before write, iclass 39, count 0 2006.281.08:12:34.16#ibcon#enter sib2, iclass 39, count 0 2006.281.08:12:34.16#ibcon#flushed, iclass 39, count 0 2006.281.08:12:34.16#ibcon#about to write, iclass 39, count 0 2006.281.08:12:34.16#ibcon#wrote, iclass 39, count 0 2006.281.08:12:34.16#ibcon#about to read 3, iclass 39, count 0 2006.281.08:12:34.19#ibcon#read 3, iclass 39, count 0 2006.281.08:12:34.19#ibcon#about to read 4, iclass 39, count 0 2006.281.08:12:34.19#ibcon#read 4, iclass 39, count 0 2006.281.08:12:34.19#ibcon#about to read 5, iclass 39, count 0 2006.281.08:12:34.19#ibcon#read 5, iclass 39, count 0 2006.281.08:12:34.19#ibcon#about to read 6, iclass 39, count 0 2006.281.08:12:34.19#ibcon#read 6, iclass 39, count 0 2006.281.08:12:34.19#ibcon#end of sib2, iclass 39, count 0 2006.281.08:12:34.19#ibcon#*after write, iclass 39, count 0 2006.281.08:12:34.19#ibcon#*before return 0, iclass 39, count 0 2006.281.08:12:34.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:12:34.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:12:34.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:12:34.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:12:34.19$4f8m12a/ifd4f 2006.281.08:12:34.19$ifd4f/lo= 2006.281.08:12:34.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:12:34.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:12:34.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:12:34.20$ifd4f/patch= 2006.281.08:12:34.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:12:34.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:12:34.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:12:34.20$4f8m12a/"form=m,16.000,1:2 2006.281.08:12:34.20$4f8m12a/"tpicd 2006.281.08:12:34.20$4f8m12a/echo=off 2006.281.08:12:34.20$4f8m12a/xlog=off 2006.281.08:12:34.20:!2006.281.08:13:00 2006.281.08:12:44.14#trakl#Source acquired 2006.281.08:12:45.14#flagr#flagr/antenna,acquired 2006.281.08:12:56.14#trakl#Off source 2006.281.08:12:56.14?ERROR st -7 Antenna off-source! 2006.281.08:12:56.14#trakl#az 354.784 el 55.944 azerr*cos(el) 0.0007 elerr 0.0239 2006.281.08:12:57.14#flagr#flagr/antenna,off-source 2006.281.08:13:00.01:preob 2006.281.08:13:01.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:13:01.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:13:01.14/onsource/SLEWING 2006.281.08:13:01.14:!2006.281.08:13:10 2006.281.08:13:02.14#trakl#Source re-acquired 2006.281.08:13:02.14#flagr#flagr/antenna,re-acquired 2006.281.08:13:10.00:data_valid=on 2006.281.08:13:10.00:midob 2006.281.08:13:10.14/onsource/TRACKING 2006.281.08:13:10.15/wx/20.14,1001.6,52 2006.281.08:13:10.22/cable/+6.4878E-03 2006.281.08:13:11.31/va/01,07,usb,yes,32,34 2006.281.08:13:11.31/va/02,06,usb,yes,30,31 2006.281.08:13:11.31/va/03,06,usb,yes,28,28 2006.281.08:13:11.31/va/04,06,usb,yes,31,33 2006.281.08:13:11.31/va/05,07,usb,yes,29,31 2006.281.08:13:11.31/va/06,06,usb,yes,28,28 2006.281.08:13:11.31/va/07,06,usb,yes,29,29 2006.281.08:13:11.31/va/08,06,usb,yes,30,30 2006.281.08:13:11.54/valo/01,532.99,yes,locked 2006.281.08:13:11.54/valo/02,572.99,yes,locked 2006.281.08:13:11.54/valo/03,672.99,yes,locked 2006.281.08:13:11.54/valo/04,832.99,yes,locked 2006.281.08:13:11.54/valo/05,652.99,yes,locked 2006.281.08:13:11.54/valo/06,772.99,yes,locked 2006.281.08:13:11.54/valo/07,832.99,yes,locked 2006.281.08:13:11.54/valo/08,852.99,yes,locked 2006.281.08:13:12.63/vb/01,04,usb,yes,29,28 2006.281.08:13:12.63/vb/02,05,usb,yes,27,29 2006.281.08:13:12.63/vb/03,04,usb,yes,28,31 2006.281.08:13:12.63/vb/04,04,usb,yes,28,29 2006.281.08:13:12.63/vb/05,04,usb,yes,26,31 2006.281.08:13:12.63/vb/06,04,usb,yes,27,30 2006.281.08:13:12.63/vb/07,04,usb,yes,30,30 2006.281.08:13:12.63/vb/08,04,usb,yes,27,31 2006.281.08:13:12.87/vblo/01,632.99,yes,locked 2006.281.08:13:12.87/vblo/02,640.99,yes,locked 2006.281.08:13:12.87/vblo/03,656.99,yes,locked 2006.281.08:13:12.87/vblo/04,712.99,yes,locked 2006.281.08:13:12.87/vblo/05,744.99,yes,locked 2006.281.08:13:12.87/vblo/06,752.99,yes,locked 2006.281.08:13:12.87/vblo/07,734.99,yes,locked 2006.281.08:13:12.87/vblo/08,744.99,yes,locked 2006.281.08:13:13.02/vabw/8 2006.281.08:13:13.14#trakl#Off source 2006.281.08:13:13.14?ERROR st -7 Antenna off-source! 2006.281.08:13:13.14#trakl#az 354.741 el 55.939 azerr*cos(el) 0.0011 elerr -0.0199 2006.281.08:13:13.17/vbbw/8 2006.281.08:13:13.29/xfe/off,on,12.0 2006.281.08:13:13.67/ifatt/23,28,28,28 2006.281.08:13:14.07/fmout-gps/S +3.12E-07 2006.281.08:13:14.09:!2006.281.08:14:10 2006.281.08:13:15.14#flagr#flagr/antenna,off-source 2006.281.08:13:28.14#trakl#Off source 2006.281.08:13:28.14?ERROR st -7 Antenna off-source! 2006.281.08:13:28.14#trakl#az 354.703 el 55.934 azerr*cos(el) 0.0026 elerr -0.0043 2006.281.08:13:31.14#trakl#Source re-acquired 2006.281.08:13:33.14#flagr#flagr/antenna,re-acquired 2006.281.08:13:44.14#trakl#Off source 2006.281.08:13:44.14?ERROR st -7 Antenna off-source! 2006.281.08:13:44.14#trakl#az 354.663 el 55.929 azerr*cos(el) -0.0007 elerr -0.0173 2006.281.08:13:45.14#flagr#flagr/antenna,off-source 2006.281.08:13:50.14#trakl#Source re-acquired 2006.281.08:13:51.14#flagr#flagr/antenna,re-acquired 2006.281.08:14:10.01:data_valid=off 2006.281.08:14:10.01:postob 2006.281.08:14:10.10/cable/+6.4891E-03 2006.281.08:14:10.10/wx/20.11,1001.7,52 2006.281.08:14:11.07/fmout-gps/S +3.11E-07 2006.281.08:14:11.07:scan_name=281-0815,k06281,60 2006.281.08:14:11.07:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.281.08:14:11.14#flagr#flagr/antenna,new-source 2006.281.08:14:12.14:checkk5 2006.281.08:14:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:14:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:14:13.50/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:14:13.91/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:14:14.30/chk_obsdata//k5ts1/T2810813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:14:14.72/chk_obsdata//k5ts2/T2810813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:14:15.12/chk_obsdata//k5ts3/T2810813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:14:15.54/chk_obsdata//k5ts4/T2810813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:14:16.60/k5log//k5ts1_log_newline 2006.281.08:14:17.39/k5log//k5ts2_log_newline 2006.281.08:14:18.23/k5log//k5ts3_log_newline 2006.281.08:14:19.21/k5log//k5ts4_log_newline 2006.281.08:14:19.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:14:19.24:4f8m12a=2 2006.281.08:14:19.24$4f8m12a/echo=on 2006.281.08:14:19.24$4f8m12a/pcalon 2006.281.08:14:19.24$pcalon/"no phase cal control is implemented here 2006.281.08:14:19.24$4f8m12a/"tpicd=stop 2006.281.08:14:19.24$4f8m12a/vc4f8 2006.281.08:14:19.24$vc4f8/valo=1,532.99 2006.281.08:14:19.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.08:14:19.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.08:14:19.25#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:19.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:19.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:19.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:19.25#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:14:19.25#ibcon#first serial, iclass 26, count 0 2006.281.08:14:19.25#ibcon#enter sib2, iclass 26, count 0 2006.281.08:14:19.25#ibcon#flushed, iclass 26, count 0 2006.281.08:14:19.25#ibcon#about to write, iclass 26, count 0 2006.281.08:14:19.25#ibcon#wrote, iclass 26, count 0 2006.281.08:14:19.25#ibcon#about to read 3, iclass 26, count 0 2006.281.08:14:19.26#ibcon#read 3, iclass 26, count 0 2006.281.08:14:19.26#ibcon#about to read 4, iclass 26, count 0 2006.281.08:14:19.26#ibcon#read 4, iclass 26, count 0 2006.281.08:14:19.26#ibcon#about to read 5, iclass 26, count 0 2006.281.08:14:19.26#ibcon#read 5, iclass 26, count 0 2006.281.08:14:19.26#ibcon#about to read 6, iclass 26, count 0 2006.281.08:14:19.26#ibcon#read 6, iclass 26, count 0 2006.281.08:14:19.26#ibcon#end of sib2, iclass 26, count 0 2006.281.08:14:19.26#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:14:19.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:14:19.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:14:19.26#ibcon#*before write, iclass 26, count 0 2006.281.08:14:19.26#ibcon#enter sib2, iclass 26, count 0 2006.281.08:14:19.26#ibcon#flushed, iclass 26, count 0 2006.281.08:14:19.26#ibcon#about to write, iclass 26, count 0 2006.281.08:14:19.26#ibcon#wrote, iclass 26, count 0 2006.281.08:14:19.26#ibcon#about to read 3, iclass 26, count 0 2006.281.08:14:19.31#ibcon#read 3, iclass 26, count 0 2006.281.08:14:19.31#ibcon#about to read 4, iclass 26, count 0 2006.281.08:14:19.31#ibcon#read 4, iclass 26, count 0 2006.281.08:14:19.31#ibcon#about to read 5, iclass 26, count 0 2006.281.08:14:19.31#ibcon#read 5, iclass 26, count 0 2006.281.08:14:19.31#ibcon#about to read 6, iclass 26, count 0 2006.281.08:14:19.31#ibcon#read 6, iclass 26, count 0 2006.281.08:14:19.31#ibcon#end of sib2, iclass 26, count 0 2006.281.08:14:19.31#ibcon#*after write, iclass 26, count 0 2006.281.08:14:19.31#ibcon#*before return 0, iclass 26, count 0 2006.281.08:14:19.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:19.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:19.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:14:19.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:14:19.31$vc4f8/va=1,7 2006.281.08:14:19.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.08:14:19.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.08:14:19.32#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:19.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:19.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:19.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:19.32#ibcon#enter wrdev, iclass 28, count 2 2006.281.08:14:19.32#ibcon#first serial, iclass 28, count 2 2006.281.08:14:19.32#ibcon#enter sib2, iclass 28, count 2 2006.281.08:14:19.32#ibcon#flushed, iclass 28, count 2 2006.281.08:14:19.32#ibcon#about to write, iclass 28, count 2 2006.281.08:14:19.32#ibcon#wrote, iclass 28, count 2 2006.281.08:14:19.32#ibcon#about to read 3, iclass 28, count 2 2006.281.08:14:19.33#ibcon#read 3, iclass 28, count 2 2006.281.08:14:19.33#ibcon#about to read 4, iclass 28, count 2 2006.281.08:14:19.33#ibcon#read 4, iclass 28, count 2 2006.281.08:14:19.33#ibcon#about to read 5, iclass 28, count 2 2006.281.08:14:19.33#ibcon#read 5, iclass 28, count 2 2006.281.08:14:19.33#ibcon#about to read 6, iclass 28, count 2 2006.281.08:14:19.33#ibcon#read 6, iclass 28, count 2 2006.281.08:14:19.33#ibcon#end of sib2, iclass 28, count 2 2006.281.08:14:19.33#ibcon#*mode == 0, iclass 28, count 2 2006.281.08:14:19.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.08:14:19.33#ibcon#[25=AT01-07\r\n] 2006.281.08:14:19.33#ibcon#*before write, iclass 28, count 2 2006.281.08:14:19.33#ibcon#enter sib2, iclass 28, count 2 2006.281.08:14:19.33#ibcon#flushed, iclass 28, count 2 2006.281.08:14:19.33#ibcon#about to write, iclass 28, count 2 2006.281.08:14:19.33#ibcon#wrote, iclass 28, count 2 2006.281.08:14:19.33#ibcon#about to read 3, iclass 28, count 2 2006.281.08:14:19.36#ibcon#read 3, iclass 28, count 2 2006.281.08:14:19.36#ibcon#about to read 4, iclass 28, count 2 2006.281.08:14:19.36#ibcon#read 4, iclass 28, count 2 2006.281.08:14:19.36#ibcon#about to read 5, iclass 28, count 2 2006.281.08:14:19.36#ibcon#read 5, iclass 28, count 2 2006.281.08:14:19.36#ibcon#about to read 6, iclass 28, count 2 2006.281.08:14:19.36#ibcon#read 6, iclass 28, count 2 2006.281.08:14:19.36#ibcon#end of sib2, iclass 28, count 2 2006.281.08:14:19.36#ibcon#*after write, iclass 28, count 2 2006.281.08:14:19.36#ibcon#*before return 0, iclass 28, count 2 2006.281.08:14:19.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:19.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:19.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.08:14:19.37#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:19.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:19.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:19.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:19.49#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:14:19.49#ibcon#first serial, iclass 28, count 0 2006.281.08:14:19.49#ibcon#enter sib2, iclass 28, count 0 2006.281.08:14:19.49#ibcon#flushed, iclass 28, count 0 2006.281.08:14:19.49#ibcon#about to write, iclass 28, count 0 2006.281.08:14:19.49#ibcon#wrote, iclass 28, count 0 2006.281.08:14:19.49#ibcon#about to read 3, iclass 28, count 0 2006.281.08:14:19.51#ibcon#read 3, iclass 28, count 0 2006.281.08:14:19.51#ibcon#about to read 4, iclass 28, count 0 2006.281.08:14:19.51#ibcon#read 4, iclass 28, count 0 2006.281.08:14:19.51#ibcon#about to read 5, iclass 28, count 0 2006.281.08:14:19.51#ibcon#read 5, iclass 28, count 0 2006.281.08:14:19.51#ibcon#about to read 6, iclass 28, count 0 2006.281.08:14:19.51#ibcon#read 6, iclass 28, count 0 2006.281.08:14:19.51#ibcon#end of sib2, iclass 28, count 0 2006.281.08:14:19.51#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:14:19.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:14:19.51#ibcon#[25=USB\r\n] 2006.281.08:14:19.51#ibcon#*before write, iclass 28, count 0 2006.281.08:14:19.51#ibcon#enter sib2, iclass 28, count 0 2006.281.08:14:19.51#ibcon#flushed, iclass 28, count 0 2006.281.08:14:19.51#ibcon#about to write, iclass 28, count 0 2006.281.08:14:19.51#ibcon#wrote, iclass 28, count 0 2006.281.08:14:19.51#ibcon#about to read 3, iclass 28, count 0 2006.281.08:14:19.53#ibcon#read 3, iclass 28, count 0 2006.281.08:14:19.53#ibcon#about to read 4, iclass 28, count 0 2006.281.08:14:19.53#ibcon#read 4, iclass 28, count 0 2006.281.08:14:19.53#ibcon#about to read 5, iclass 28, count 0 2006.281.08:14:19.53#ibcon#read 5, iclass 28, count 0 2006.281.08:14:19.53#ibcon#about to read 6, iclass 28, count 0 2006.281.08:14:19.53#ibcon#read 6, iclass 28, count 0 2006.281.08:14:19.53#ibcon#end of sib2, iclass 28, count 0 2006.281.08:14:19.53#ibcon#*after write, iclass 28, count 0 2006.281.08:14:19.53#ibcon#*before return 0, iclass 28, count 0 2006.281.08:14:19.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:19.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:19.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:14:19.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:14:19.53$vc4f8/valo=2,572.99 2006.281.08:14:19.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.08:14:19.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.08:14:19.53#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:19.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:19.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:19.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:19.53#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:14:19.53#ibcon#first serial, iclass 30, count 0 2006.281.08:14:19.53#ibcon#enter sib2, iclass 30, count 0 2006.281.08:14:19.53#ibcon#flushed, iclass 30, count 0 2006.281.08:14:19.53#ibcon#about to write, iclass 30, count 0 2006.281.08:14:19.53#ibcon#wrote, iclass 30, count 0 2006.281.08:14:19.53#ibcon#about to read 3, iclass 30, count 0 2006.281.08:14:19.55#ibcon#read 3, iclass 30, count 0 2006.281.08:14:19.55#ibcon#about to read 4, iclass 30, count 0 2006.281.08:14:19.55#ibcon#read 4, iclass 30, count 0 2006.281.08:14:19.55#ibcon#about to read 5, iclass 30, count 0 2006.281.08:14:19.55#ibcon#read 5, iclass 30, count 0 2006.281.08:14:19.55#ibcon#about to read 6, iclass 30, count 0 2006.281.08:14:19.55#ibcon#read 6, iclass 30, count 0 2006.281.08:14:19.55#ibcon#end of sib2, iclass 30, count 0 2006.281.08:14:19.55#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:14:19.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:14:19.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:14:19.55#ibcon#*before write, iclass 30, count 0 2006.281.08:14:19.55#ibcon#enter sib2, iclass 30, count 0 2006.281.08:14:19.55#ibcon#flushed, iclass 30, count 0 2006.281.08:14:19.55#ibcon#about to write, iclass 30, count 0 2006.281.08:14:19.55#ibcon#wrote, iclass 30, count 0 2006.281.08:14:19.55#ibcon#about to read 3, iclass 30, count 0 2006.281.08:14:19.60#ibcon#read 3, iclass 30, count 0 2006.281.08:14:19.60#ibcon#about to read 4, iclass 30, count 0 2006.281.08:14:19.60#ibcon#read 4, iclass 30, count 0 2006.281.08:14:19.60#ibcon#about to read 5, iclass 30, count 0 2006.281.08:14:19.60#ibcon#read 5, iclass 30, count 0 2006.281.08:14:19.60#ibcon#about to read 6, iclass 30, count 0 2006.281.08:14:19.60#ibcon#read 6, iclass 30, count 0 2006.281.08:14:19.60#ibcon#end of sib2, iclass 30, count 0 2006.281.08:14:19.60#ibcon#*after write, iclass 30, count 0 2006.281.08:14:19.60#ibcon#*before return 0, iclass 30, count 0 2006.281.08:14:19.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:19.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:19.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:14:19.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:14:19.60$vc4f8/va=2,6 2006.281.08:14:19.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.08:14:19.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.08:14:19.60#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:19.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:19.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:19.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:19.64#ibcon#enter wrdev, iclass 32, count 2 2006.281.08:14:19.64#ibcon#first serial, iclass 32, count 2 2006.281.08:14:19.64#ibcon#enter sib2, iclass 32, count 2 2006.281.08:14:19.64#ibcon#flushed, iclass 32, count 2 2006.281.08:14:19.64#ibcon#about to write, iclass 32, count 2 2006.281.08:14:19.64#ibcon#wrote, iclass 32, count 2 2006.281.08:14:19.64#ibcon#about to read 3, iclass 32, count 2 2006.281.08:14:19.67#ibcon#read 3, iclass 32, count 2 2006.281.08:14:19.67#ibcon#about to read 4, iclass 32, count 2 2006.281.08:14:19.67#ibcon#read 4, iclass 32, count 2 2006.281.08:14:19.67#ibcon#about to read 5, iclass 32, count 2 2006.281.08:14:19.67#ibcon#read 5, iclass 32, count 2 2006.281.08:14:19.67#ibcon#about to read 6, iclass 32, count 2 2006.281.08:14:19.67#ibcon#read 6, iclass 32, count 2 2006.281.08:14:19.67#ibcon#end of sib2, iclass 32, count 2 2006.281.08:14:19.67#ibcon#*mode == 0, iclass 32, count 2 2006.281.08:14:19.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.08:14:19.67#ibcon#[25=AT02-06\r\n] 2006.281.08:14:19.67#ibcon#*before write, iclass 32, count 2 2006.281.08:14:19.67#ibcon#enter sib2, iclass 32, count 2 2006.281.08:14:19.67#ibcon#flushed, iclass 32, count 2 2006.281.08:14:19.67#ibcon#about to write, iclass 32, count 2 2006.281.08:14:19.67#ibcon#wrote, iclass 32, count 2 2006.281.08:14:19.67#ibcon#about to read 3, iclass 32, count 2 2006.281.08:14:19.70#ibcon#read 3, iclass 32, count 2 2006.281.08:14:19.70#ibcon#about to read 4, iclass 32, count 2 2006.281.08:14:19.70#ibcon#read 4, iclass 32, count 2 2006.281.08:14:19.70#ibcon#about to read 5, iclass 32, count 2 2006.281.08:14:19.70#ibcon#read 5, iclass 32, count 2 2006.281.08:14:19.70#ibcon#about to read 6, iclass 32, count 2 2006.281.08:14:19.70#ibcon#read 6, iclass 32, count 2 2006.281.08:14:19.70#ibcon#end of sib2, iclass 32, count 2 2006.281.08:14:19.70#ibcon#*after write, iclass 32, count 2 2006.281.08:14:19.70#ibcon#*before return 0, iclass 32, count 2 2006.281.08:14:19.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:19.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:19.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.08:14:19.70#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:19.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:19.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:19.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:19.82#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:14:19.82#ibcon#first serial, iclass 32, count 0 2006.281.08:14:19.82#ibcon#enter sib2, iclass 32, count 0 2006.281.08:14:19.82#ibcon#flushed, iclass 32, count 0 2006.281.08:14:19.82#ibcon#about to write, iclass 32, count 0 2006.281.08:14:19.82#ibcon#wrote, iclass 32, count 0 2006.281.08:14:19.82#ibcon#about to read 3, iclass 32, count 0 2006.281.08:14:19.84#ibcon#read 3, iclass 32, count 0 2006.281.08:14:19.84#ibcon#about to read 4, iclass 32, count 0 2006.281.08:14:19.84#ibcon#read 4, iclass 32, count 0 2006.281.08:14:19.84#ibcon#about to read 5, iclass 32, count 0 2006.281.08:14:19.84#ibcon#read 5, iclass 32, count 0 2006.281.08:14:19.84#ibcon#about to read 6, iclass 32, count 0 2006.281.08:14:19.84#ibcon#read 6, iclass 32, count 0 2006.281.08:14:19.84#ibcon#end of sib2, iclass 32, count 0 2006.281.08:14:19.84#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:14:19.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:14:19.84#ibcon#[25=USB\r\n] 2006.281.08:14:19.84#ibcon#*before write, iclass 32, count 0 2006.281.08:14:19.84#ibcon#enter sib2, iclass 32, count 0 2006.281.08:14:19.84#ibcon#flushed, iclass 32, count 0 2006.281.08:14:19.84#ibcon#about to write, iclass 32, count 0 2006.281.08:14:19.84#ibcon#wrote, iclass 32, count 0 2006.281.08:14:19.84#ibcon#about to read 3, iclass 32, count 0 2006.281.08:14:19.88#ibcon#read 3, iclass 32, count 0 2006.281.08:14:19.88#ibcon#about to read 4, iclass 32, count 0 2006.281.08:14:19.88#ibcon#read 4, iclass 32, count 0 2006.281.08:14:19.88#ibcon#about to read 5, iclass 32, count 0 2006.281.08:14:19.88#ibcon#read 5, iclass 32, count 0 2006.281.08:14:19.88#ibcon#about to read 6, iclass 32, count 0 2006.281.08:14:19.88#ibcon#read 6, iclass 32, count 0 2006.281.08:14:19.88#ibcon#end of sib2, iclass 32, count 0 2006.281.08:14:19.88#ibcon#*after write, iclass 32, count 0 2006.281.08:14:19.88#ibcon#*before return 0, iclass 32, count 0 2006.281.08:14:19.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:19.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:19.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:14:19.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:14:19.88$vc4f8/valo=3,672.99 2006.281.08:14:19.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.08:14:19.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.08:14:19.88#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:19.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:19.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:19.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:19.88#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:14:19.88#ibcon#first serial, iclass 34, count 0 2006.281.08:14:19.88#ibcon#enter sib2, iclass 34, count 0 2006.281.08:14:19.88#ibcon#flushed, iclass 34, count 0 2006.281.08:14:19.88#ibcon#about to write, iclass 34, count 0 2006.281.08:14:19.88#ibcon#wrote, iclass 34, count 0 2006.281.08:14:19.88#ibcon#about to read 3, iclass 34, count 0 2006.281.08:14:19.89#ibcon#read 3, iclass 34, count 0 2006.281.08:14:19.89#ibcon#about to read 4, iclass 34, count 0 2006.281.08:14:19.89#ibcon#read 4, iclass 34, count 0 2006.281.08:14:19.89#ibcon#about to read 5, iclass 34, count 0 2006.281.08:14:19.89#ibcon#read 5, iclass 34, count 0 2006.281.08:14:19.90#ibcon#about to read 6, iclass 34, count 0 2006.281.08:14:19.90#ibcon#read 6, iclass 34, count 0 2006.281.08:14:19.90#ibcon#end of sib2, iclass 34, count 0 2006.281.08:14:19.90#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:14:19.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:14:19.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:14:19.90#ibcon#*before write, iclass 34, count 0 2006.281.08:14:19.90#ibcon#enter sib2, iclass 34, count 0 2006.281.08:14:19.90#ibcon#flushed, iclass 34, count 0 2006.281.08:14:19.90#ibcon#about to write, iclass 34, count 0 2006.281.08:14:19.90#ibcon#wrote, iclass 34, count 0 2006.281.08:14:19.90#ibcon#about to read 3, iclass 34, count 0 2006.281.08:14:19.94#ibcon#read 3, iclass 34, count 0 2006.281.08:14:19.94#ibcon#about to read 4, iclass 34, count 0 2006.281.08:14:19.94#ibcon#read 4, iclass 34, count 0 2006.281.08:14:19.94#ibcon#about to read 5, iclass 34, count 0 2006.281.08:14:19.94#ibcon#read 5, iclass 34, count 0 2006.281.08:14:19.94#ibcon#about to read 6, iclass 34, count 0 2006.281.08:14:19.94#ibcon#read 6, iclass 34, count 0 2006.281.08:14:19.94#ibcon#end of sib2, iclass 34, count 0 2006.281.08:14:19.94#ibcon#*after write, iclass 34, count 0 2006.281.08:14:19.94#ibcon#*before return 0, iclass 34, count 0 2006.281.08:14:19.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:19.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:19.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:14:19.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:14:19.95$vc4f8/va=3,6 2006.281.08:14:19.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.08:14:19.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.08:14:19.95#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:19.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:19.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:19.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:19.99#ibcon#enter wrdev, iclass 36, count 2 2006.281.08:14:19.99#ibcon#first serial, iclass 36, count 2 2006.281.08:14:19.99#ibcon#enter sib2, iclass 36, count 2 2006.281.08:14:19.99#ibcon#flushed, iclass 36, count 2 2006.281.08:14:19.99#ibcon#about to write, iclass 36, count 2 2006.281.08:14:19.99#ibcon#wrote, iclass 36, count 2 2006.281.08:14:19.99#ibcon#about to read 3, iclass 36, count 2 2006.281.08:14:20.01#ibcon#read 3, iclass 36, count 2 2006.281.08:14:20.01#ibcon#about to read 4, iclass 36, count 2 2006.281.08:14:20.01#ibcon#read 4, iclass 36, count 2 2006.281.08:14:20.01#ibcon#about to read 5, iclass 36, count 2 2006.281.08:14:20.01#ibcon#read 5, iclass 36, count 2 2006.281.08:14:20.01#ibcon#about to read 6, iclass 36, count 2 2006.281.08:14:20.01#ibcon#read 6, iclass 36, count 2 2006.281.08:14:20.01#ibcon#end of sib2, iclass 36, count 2 2006.281.08:14:20.01#ibcon#*mode == 0, iclass 36, count 2 2006.281.08:14:20.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.08:14:20.01#ibcon#[25=AT03-06\r\n] 2006.281.08:14:20.01#ibcon#*before write, iclass 36, count 2 2006.281.08:14:20.01#ibcon#enter sib2, iclass 36, count 2 2006.281.08:14:20.01#ibcon#flushed, iclass 36, count 2 2006.281.08:14:20.01#ibcon#about to write, iclass 36, count 2 2006.281.08:14:20.01#ibcon#wrote, iclass 36, count 2 2006.281.08:14:20.01#ibcon#about to read 3, iclass 36, count 2 2006.281.08:14:20.04#ibcon#read 3, iclass 36, count 2 2006.281.08:14:20.04#ibcon#about to read 4, iclass 36, count 2 2006.281.08:14:20.04#ibcon#read 4, iclass 36, count 2 2006.281.08:14:20.04#ibcon#about to read 5, iclass 36, count 2 2006.281.08:14:20.04#ibcon#read 5, iclass 36, count 2 2006.281.08:14:20.04#ibcon#about to read 6, iclass 36, count 2 2006.281.08:14:20.04#ibcon#read 6, iclass 36, count 2 2006.281.08:14:20.04#ibcon#end of sib2, iclass 36, count 2 2006.281.08:14:20.04#ibcon#*after write, iclass 36, count 2 2006.281.08:14:20.04#ibcon#*before return 0, iclass 36, count 2 2006.281.08:14:20.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:20.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:20.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.08:14:20.04#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:20.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:20.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:20.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:20.17#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:14:20.17#ibcon#first serial, iclass 36, count 0 2006.281.08:14:20.17#ibcon#enter sib2, iclass 36, count 0 2006.281.08:14:20.17#ibcon#flushed, iclass 36, count 0 2006.281.08:14:20.17#ibcon#about to write, iclass 36, count 0 2006.281.08:14:20.17#ibcon#wrote, iclass 36, count 0 2006.281.08:14:20.17#ibcon#about to read 3, iclass 36, count 0 2006.281.08:14:20.18#ibcon#read 3, iclass 36, count 0 2006.281.08:14:20.18#ibcon#about to read 4, iclass 36, count 0 2006.281.08:14:20.18#ibcon#read 4, iclass 36, count 0 2006.281.08:14:20.18#ibcon#about to read 5, iclass 36, count 0 2006.281.08:14:20.18#ibcon#read 5, iclass 36, count 0 2006.281.08:14:20.18#ibcon#about to read 6, iclass 36, count 0 2006.281.08:14:20.18#ibcon#read 6, iclass 36, count 0 2006.281.08:14:20.18#ibcon#end of sib2, iclass 36, count 0 2006.281.08:14:20.18#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:14:20.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:14:20.18#ibcon#[25=USB\r\n] 2006.281.08:14:20.18#ibcon#*before write, iclass 36, count 0 2006.281.08:14:20.18#ibcon#enter sib2, iclass 36, count 0 2006.281.08:14:20.18#ibcon#flushed, iclass 36, count 0 2006.281.08:14:20.18#ibcon#about to write, iclass 36, count 0 2006.281.08:14:20.18#ibcon#wrote, iclass 36, count 0 2006.281.08:14:20.18#ibcon#about to read 3, iclass 36, count 0 2006.281.08:14:20.21#ibcon#read 3, iclass 36, count 0 2006.281.08:14:20.21#ibcon#about to read 4, iclass 36, count 0 2006.281.08:14:20.21#ibcon#read 4, iclass 36, count 0 2006.281.08:14:20.21#ibcon#about to read 5, iclass 36, count 0 2006.281.08:14:20.21#ibcon#read 5, iclass 36, count 0 2006.281.08:14:20.21#ibcon#about to read 6, iclass 36, count 0 2006.281.08:14:20.21#ibcon#read 6, iclass 36, count 0 2006.281.08:14:20.21#ibcon#end of sib2, iclass 36, count 0 2006.281.08:14:20.21#ibcon#*after write, iclass 36, count 0 2006.281.08:14:20.21#ibcon#*before return 0, iclass 36, count 0 2006.281.08:14:20.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:20.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:20.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:14:20.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:14:20.21$vc4f8/valo=4,832.99 2006.281.08:14:20.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:14:20.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:14:20.21#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:20.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:20.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:20.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:20.21#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:14:20.21#ibcon#first serial, iclass 38, count 0 2006.281.08:14:20.21#ibcon#enter sib2, iclass 38, count 0 2006.281.08:14:20.21#ibcon#flushed, iclass 38, count 0 2006.281.08:14:20.21#ibcon#about to write, iclass 38, count 0 2006.281.08:14:20.21#ibcon#wrote, iclass 38, count 0 2006.281.08:14:20.21#ibcon#about to read 3, iclass 38, count 0 2006.281.08:14:20.23#ibcon#read 3, iclass 38, count 0 2006.281.08:14:20.23#ibcon#about to read 4, iclass 38, count 0 2006.281.08:14:20.23#ibcon#read 4, iclass 38, count 0 2006.281.08:14:20.23#ibcon#about to read 5, iclass 38, count 0 2006.281.08:14:20.23#ibcon#read 5, iclass 38, count 0 2006.281.08:14:20.23#ibcon#about to read 6, iclass 38, count 0 2006.281.08:14:20.23#ibcon#read 6, iclass 38, count 0 2006.281.08:14:20.23#ibcon#end of sib2, iclass 38, count 0 2006.281.08:14:20.23#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:14:20.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:14:20.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:14:20.23#ibcon#*before write, iclass 38, count 0 2006.281.08:14:20.23#ibcon#enter sib2, iclass 38, count 0 2006.281.08:14:20.23#ibcon#flushed, iclass 38, count 0 2006.281.08:14:20.23#ibcon#about to write, iclass 38, count 0 2006.281.08:14:20.23#ibcon#wrote, iclass 38, count 0 2006.281.08:14:20.23#ibcon#about to read 3, iclass 38, count 0 2006.281.08:14:20.27#ibcon#read 3, iclass 38, count 0 2006.281.08:14:20.27#ibcon#about to read 4, iclass 38, count 0 2006.281.08:14:20.27#ibcon#read 4, iclass 38, count 0 2006.281.08:14:20.27#ibcon#about to read 5, iclass 38, count 0 2006.281.08:14:20.27#ibcon#read 5, iclass 38, count 0 2006.281.08:14:20.27#ibcon#about to read 6, iclass 38, count 0 2006.281.08:14:20.27#ibcon#read 6, iclass 38, count 0 2006.281.08:14:20.27#ibcon#end of sib2, iclass 38, count 0 2006.281.08:14:20.27#ibcon#*after write, iclass 38, count 0 2006.281.08:14:20.27#ibcon#*before return 0, iclass 38, count 0 2006.281.08:14:20.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:20.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:20.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:14:20.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:14:20.27$vc4f8/va=4,6 2006.281.08:14:20.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:14:20.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:14:20.27#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:20.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:20.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:20.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:20.33#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:14:20.33#ibcon#first serial, iclass 40, count 2 2006.281.08:14:20.33#ibcon#enter sib2, iclass 40, count 2 2006.281.08:14:20.33#ibcon#flushed, iclass 40, count 2 2006.281.08:14:20.33#ibcon#about to write, iclass 40, count 2 2006.281.08:14:20.33#ibcon#wrote, iclass 40, count 2 2006.281.08:14:20.33#ibcon#about to read 3, iclass 40, count 2 2006.281.08:14:20.36#ibcon#read 3, iclass 40, count 2 2006.281.08:14:20.36#ibcon#about to read 4, iclass 40, count 2 2006.281.08:14:20.36#ibcon#read 4, iclass 40, count 2 2006.281.08:14:20.36#ibcon#about to read 5, iclass 40, count 2 2006.281.08:14:20.36#ibcon#read 5, iclass 40, count 2 2006.281.08:14:20.36#ibcon#about to read 6, iclass 40, count 2 2006.281.08:14:20.36#ibcon#read 6, iclass 40, count 2 2006.281.08:14:20.36#ibcon#end of sib2, iclass 40, count 2 2006.281.08:14:20.36#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:14:20.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:14:20.36#ibcon#[25=AT04-06\r\n] 2006.281.08:14:20.36#ibcon#*before write, iclass 40, count 2 2006.281.08:14:20.36#ibcon#enter sib2, iclass 40, count 2 2006.281.08:14:20.36#ibcon#flushed, iclass 40, count 2 2006.281.08:14:20.36#ibcon#about to write, iclass 40, count 2 2006.281.08:14:20.36#ibcon#wrote, iclass 40, count 2 2006.281.08:14:20.36#ibcon#about to read 3, iclass 40, count 2 2006.281.08:14:20.39#ibcon#read 3, iclass 40, count 2 2006.281.08:14:20.39#ibcon#about to read 4, iclass 40, count 2 2006.281.08:14:20.39#ibcon#read 4, iclass 40, count 2 2006.281.08:14:20.39#ibcon#about to read 5, iclass 40, count 2 2006.281.08:14:20.39#ibcon#read 5, iclass 40, count 2 2006.281.08:14:20.39#ibcon#about to read 6, iclass 40, count 2 2006.281.08:14:20.39#ibcon#read 6, iclass 40, count 2 2006.281.08:14:20.39#ibcon#end of sib2, iclass 40, count 2 2006.281.08:14:20.39#ibcon#*after write, iclass 40, count 2 2006.281.08:14:20.39#ibcon#*before return 0, iclass 40, count 2 2006.281.08:14:20.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:20.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:20.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:14:20.39#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:20.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:20.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:20.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:20.50#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:14:20.50#ibcon#first serial, iclass 40, count 0 2006.281.08:14:20.50#ibcon#enter sib2, iclass 40, count 0 2006.281.08:14:20.50#ibcon#flushed, iclass 40, count 0 2006.281.08:14:20.50#ibcon#about to write, iclass 40, count 0 2006.281.08:14:20.50#ibcon#wrote, iclass 40, count 0 2006.281.08:14:20.50#ibcon#about to read 3, iclass 40, count 0 2006.281.08:14:20.52#ibcon#read 3, iclass 40, count 0 2006.281.08:14:20.52#ibcon#about to read 4, iclass 40, count 0 2006.281.08:14:20.52#ibcon#read 4, iclass 40, count 0 2006.281.08:14:20.52#ibcon#about to read 5, iclass 40, count 0 2006.281.08:14:20.52#ibcon#read 5, iclass 40, count 0 2006.281.08:14:20.52#ibcon#about to read 6, iclass 40, count 0 2006.281.08:14:20.52#ibcon#read 6, iclass 40, count 0 2006.281.08:14:20.52#ibcon#end of sib2, iclass 40, count 0 2006.281.08:14:20.52#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:14:20.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:14:20.52#ibcon#[25=USB\r\n] 2006.281.08:14:20.52#ibcon#*before write, iclass 40, count 0 2006.281.08:14:20.52#ibcon#enter sib2, iclass 40, count 0 2006.281.08:14:20.52#ibcon#flushed, iclass 40, count 0 2006.281.08:14:20.52#ibcon#about to write, iclass 40, count 0 2006.281.08:14:20.52#ibcon#wrote, iclass 40, count 0 2006.281.08:14:20.52#ibcon#about to read 3, iclass 40, count 0 2006.281.08:14:20.56#ibcon#read 3, iclass 40, count 0 2006.281.08:14:20.56#ibcon#about to read 4, iclass 40, count 0 2006.281.08:14:20.56#ibcon#read 4, iclass 40, count 0 2006.281.08:14:20.56#ibcon#about to read 5, iclass 40, count 0 2006.281.08:14:20.56#ibcon#read 5, iclass 40, count 0 2006.281.08:14:20.56#ibcon#about to read 6, iclass 40, count 0 2006.281.08:14:20.56#ibcon#read 6, iclass 40, count 0 2006.281.08:14:20.56#ibcon#end of sib2, iclass 40, count 0 2006.281.08:14:20.56#ibcon#*after write, iclass 40, count 0 2006.281.08:14:20.56#ibcon#*before return 0, iclass 40, count 0 2006.281.08:14:20.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:20.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:20.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:14:20.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:14:20.56$vc4f8/valo=5,652.99 2006.281.08:14:20.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:14:20.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:14:20.56#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:20.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:20.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:20.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:20.56#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:14:20.56#ibcon#first serial, iclass 4, count 0 2006.281.08:14:20.56#ibcon#enter sib2, iclass 4, count 0 2006.281.08:14:20.56#ibcon#flushed, iclass 4, count 0 2006.281.08:14:20.56#ibcon#about to write, iclass 4, count 0 2006.281.08:14:20.56#ibcon#wrote, iclass 4, count 0 2006.281.08:14:20.56#ibcon#about to read 3, iclass 4, count 0 2006.281.08:14:20.58#ibcon#read 3, iclass 4, count 0 2006.281.08:14:20.58#ibcon#about to read 4, iclass 4, count 0 2006.281.08:14:20.58#ibcon#read 4, iclass 4, count 0 2006.281.08:14:20.58#ibcon#about to read 5, iclass 4, count 0 2006.281.08:14:20.58#ibcon#read 5, iclass 4, count 0 2006.281.08:14:20.58#ibcon#about to read 6, iclass 4, count 0 2006.281.08:14:20.58#ibcon#read 6, iclass 4, count 0 2006.281.08:14:20.58#ibcon#end of sib2, iclass 4, count 0 2006.281.08:14:20.58#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:14:20.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:14:20.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:14:20.58#ibcon#*before write, iclass 4, count 0 2006.281.08:14:20.58#ibcon#enter sib2, iclass 4, count 0 2006.281.08:14:20.58#ibcon#flushed, iclass 4, count 0 2006.281.08:14:20.59#ibcon#about to write, iclass 4, count 0 2006.281.08:14:20.59#ibcon#wrote, iclass 4, count 0 2006.281.08:14:20.59#ibcon#about to read 3, iclass 4, count 0 2006.281.08:14:20.63#ibcon#read 3, iclass 4, count 0 2006.281.08:14:20.63#ibcon#about to read 4, iclass 4, count 0 2006.281.08:14:20.63#ibcon#read 4, iclass 4, count 0 2006.281.08:14:20.63#ibcon#about to read 5, iclass 4, count 0 2006.281.08:14:20.63#ibcon#read 5, iclass 4, count 0 2006.281.08:14:20.63#ibcon#about to read 6, iclass 4, count 0 2006.281.08:14:20.63#ibcon#read 6, iclass 4, count 0 2006.281.08:14:20.63#ibcon#end of sib2, iclass 4, count 0 2006.281.08:14:20.63#ibcon#*after write, iclass 4, count 0 2006.281.08:14:20.63#ibcon#*before return 0, iclass 4, count 0 2006.281.08:14:20.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:20.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:20.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:14:20.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:14:20.63$vc4f8/va=5,7 2006.281.08:14:20.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.08:14:20.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.08:14:20.63#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:20.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:20.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:20.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:20.68#ibcon#enter wrdev, iclass 6, count 2 2006.281.08:14:20.68#ibcon#first serial, iclass 6, count 2 2006.281.08:14:20.68#ibcon#enter sib2, iclass 6, count 2 2006.281.08:14:20.68#ibcon#flushed, iclass 6, count 2 2006.281.08:14:20.68#ibcon#about to write, iclass 6, count 2 2006.281.08:14:20.68#ibcon#wrote, iclass 6, count 2 2006.281.08:14:20.68#ibcon#about to read 3, iclass 6, count 2 2006.281.08:14:20.70#ibcon#read 3, iclass 6, count 2 2006.281.08:14:20.70#ibcon#about to read 4, iclass 6, count 2 2006.281.08:14:20.70#ibcon#read 4, iclass 6, count 2 2006.281.08:14:20.70#ibcon#about to read 5, iclass 6, count 2 2006.281.08:14:20.70#ibcon#read 5, iclass 6, count 2 2006.281.08:14:20.70#ibcon#about to read 6, iclass 6, count 2 2006.281.08:14:20.70#ibcon#read 6, iclass 6, count 2 2006.281.08:14:20.70#ibcon#end of sib2, iclass 6, count 2 2006.281.08:14:20.70#ibcon#*mode == 0, iclass 6, count 2 2006.281.08:14:20.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.08:14:20.70#ibcon#[25=AT05-07\r\n] 2006.281.08:14:20.70#ibcon#*before write, iclass 6, count 2 2006.281.08:14:20.70#ibcon#enter sib2, iclass 6, count 2 2006.281.08:14:20.70#ibcon#flushed, iclass 6, count 2 2006.281.08:14:20.70#ibcon#about to write, iclass 6, count 2 2006.281.08:14:20.70#ibcon#wrote, iclass 6, count 2 2006.281.08:14:20.70#ibcon#about to read 3, iclass 6, count 2 2006.281.08:14:20.73#ibcon#read 3, iclass 6, count 2 2006.281.08:14:20.73#ibcon#about to read 4, iclass 6, count 2 2006.281.08:14:20.73#ibcon#read 4, iclass 6, count 2 2006.281.08:14:20.73#ibcon#about to read 5, iclass 6, count 2 2006.281.08:14:20.73#ibcon#read 5, iclass 6, count 2 2006.281.08:14:20.73#ibcon#about to read 6, iclass 6, count 2 2006.281.08:14:20.73#ibcon#read 6, iclass 6, count 2 2006.281.08:14:20.73#ibcon#end of sib2, iclass 6, count 2 2006.281.08:14:20.73#ibcon#*after write, iclass 6, count 2 2006.281.08:14:20.73#ibcon#*before return 0, iclass 6, count 2 2006.281.08:14:20.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:20.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:20.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.08:14:20.73#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:20.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:20.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:20.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:20.85#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:14:20.85#ibcon#first serial, iclass 6, count 0 2006.281.08:14:20.85#ibcon#enter sib2, iclass 6, count 0 2006.281.08:14:20.85#ibcon#flushed, iclass 6, count 0 2006.281.08:14:20.85#ibcon#about to write, iclass 6, count 0 2006.281.08:14:20.85#ibcon#wrote, iclass 6, count 0 2006.281.08:14:20.85#ibcon#about to read 3, iclass 6, count 0 2006.281.08:14:20.87#ibcon#read 3, iclass 6, count 0 2006.281.08:14:20.87#ibcon#about to read 4, iclass 6, count 0 2006.281.08:14:20.87#ibcon#read 4, iclass 6, count 0 2006.281.08:14:20.87#ibcon#about to read 5, iclass 6, count 0 2006.281.08:14:20.87#ibcon#read 5, iclass 6, count 0 2006.281.08:14:20.87#ibcon#about to read 6, iclass 6, count 0 2006.281.08:14:20.87#ibcon#read 6, iclass 6, count 0 2006.281.08:14:20.87#ibcon#end of sib2, iclass 6, count 0 2006.281.08:14:20.87#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:14:20.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:14:20.87#ibcon#[25=USB\r\n] 2006.281.08:14:20.87#ibcon#*before write, iclass 6, count 0 2006.281.08:14:20.87#ibcon#enter sib2, iclass 6, count 0 2006.281.08:14:20.87#ibcon#flushed, iclass 6, count 0 2006.281.08:14:20.87#ibcon#about to write, iclass 6, count 0 2006.281.08:14:20.87#ibcon#wrote, iclass 6, count 0 2006.281.08:14:20.87#ibcon#about to read 3, iclass 6, count 0 2006.281.08:14:20.90#ibcon#read 3, iclass 6, count 0 2006.281.08:14:20.90#ibcon#about to read 4, iclass 6, count 0 2006.281.08:14:20.90#ibcon#read 4, iclass 6, count 0 2006.281.08:14:20.90#ibcon#about to read 5, iclass 6, count 0 2006.281.08:14:20.90#ibcon#read 5, iclass 6, count 0 2006.281.08:14:20.90#ibcon#about to read 6, iclass 6, count 0 2006.281.08:14:20.90#ibcon#read 6, iclass 6, count 0 2006.281.08:14:20.90#ibcon#end of sib2, iclass 6, count 0 2006.281.08:14:20.90#ibcon#*after write, iclass 6, count 0 2006.281.08:14:20.90#ibcon#*before return 0, iclass 6, count 0 2006.281.08:14:20.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:20.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:20.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:14:20.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:14:20.90$vc4f8/valo=6,772.99 2006.281.08:14:20.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.08:14:20.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.08:14:20.90#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:20.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:20.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:20.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:20.90#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:14:20.90#ibcon#first serial, iclass 10, count 0 2006.281.08:14:20.90#ibcon#enter sib2, iclass 10, count 0 2006.281.08:14:20.90#ibcon#flushed, iclass 10, count 0 2006.281.08:14:20.90#ibcon#about to write, iclass 10, count 0 2006.281.08:14:20.90#ibcon#wrote, iclass 10, count 0 2006.281.08:14:20.90#ibcon#about to read 3, iclass 10, count 0 2006.281.08:14:20.92#ibcon#read 3, iclass 10, count 0 2006.281.08:14:20.92#ibcon#about to read 4, iclass 10, count 0 2006.281.08:14:20.92#ibcon#read 4, iclass 10, count 0 2006.281.08:14:20.92#ibcon#about to read 5, iclass 10, count 0 2006.281.08:14:20.92#ibcon#read 5, iclass 10, count 0 2006.281.08:14:20.92#ibcon#about to read 6, iclass 10, count 0 2006.281.08:14:20.92#ibcon#read 6, iclass 10, count 0 2006.281.08:14:20.92#ibcon#end of sib2, iclass 10, count 0 2006.281.08:14:20.92#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:14:20.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:14:20.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:14:20.92#ibcon#*before write, iclass 10, count 0 2006.281.08:14:20.92#ibcon#enter sib2, iclass 10, count 0 2006.281.08:14:20.92#ibcon#flushed, iclass 10, count 0 2006.281.08:14:20.92#ibcon#about to write, iclass 10, count 0 2006.281.08:14:20.92#ibcon#wrote, iclass 10, count 0 2006.281.08:14:20.92#ibcon#about to read 3, iclass 10, count 0 2006.281.08:14:20.96#ibcon#read 3, iclass 10, count 0 2006.281.08:14:20.96#ibcon#about to read 4, iclass 10, count 0 2006.281.08:14:20.96#ibcon#read 4, iclass 10, count 0 2006.281.08:14:20.96#ibcon#about to read 5, iclass 10, count 0 2006.281.08:14:20.96#ibcon#read 5, iclass 10, count 0 2006.281.08:14:20.96#ibcon#about to read 6, iclass 10, count 0 2006.281.08:14:20.96#ibcon#read 6, iclass 10, count 0 2006.281.08:14:20.96#ibcon#end of sib2, iclass 10, count 0 2006.281.08:14:20.96#ibcon#*after write, iclass 10, count 0 2006.281.08:14:20.96#ibcon#*before return 0, iclass 10, count 0 2006.281.08:14:20.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:20.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:20.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:14:20.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:14:20.96$vc4f8/va=6,6 2006.281.08:14:20.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.281.08:14:20.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.281.08:14:20.96#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:20.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:21.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:21.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:21.02#ibcon#enter wrdev, iclass 12, count 2 2006.281.08:14:21.02#ibcon#first serial, iclass 12, count 2 2006.281.08:14:21.02#ibcon#enter sib2, iclass 12, count 2 2006.281.08:14:21.02#ibcon#flushed, iclass 12, count 2 2006.281.08:14:21.02#ibcon#about to write, iclass 12, count 2 2006.281.08:14:21.02#ibcon#wrote, iclass 12, count 2 2006.281.08:14:21.02#ibcon#about to read 3, iclass 12, count 2 2006.281.08:14:21.05#ibcon#read 3, iclass 12, count 2 2006.281.08:14:21.05#ibcon#about to read 4, iclass 12, count 2 2006.281.08:14:21.05#ibcon#read 4, iclass 12, count 2 2006.281.08:14:21.05#ibcon#about to read 5, iclass 12, count 2 2006.281.08:14:21.05#ibcon#read 5, iclass 12, count 2 2006.281.08:14:21.05#ibcon#about to read 6, iclass 12, count 2 2006.281.08:14:21.05#ibcon#read 6, iclass 12, count 2 2006.281.08:14:21.05#ibcon#end of sib2, iclass 12, count 2 2006.281.08:14:21.05#ibcon#*mode == 0, iclass 12, count 2 2006.281.08:14:21.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.281.08:14:21.05#ibcon#[25=AT06-06\r\n] 2006.281.08:14:21.05#ibcon#*before write, iclass 12, count 2 2006.281.08:14:21.05#ibcon#enter sib2, iclass 12, count 2 2006.281.08:14:21.05#ibcon#flushed, iclass 12, count 2 2006.281.08:14:21.05#ibcon#about to write, iclass 12, count 2 2006.281.08:14:21.05#ibcon#wrote, iclass 12, count 2 2006.281.08:14:21.05#ibcon#about to read 3, iclass 12, count 2 2006.281.08:14:21.08#ibcon#read 3, iclass 12, count 2 2006.281.08:14:21.08#ibcon#about to read 4, iclass 12, count 2 2006.281.08:14:21.08#ibcon#read 4, iclass 12, count 2 2006.281.08:14:21.08#ibcon#about to read 5, iclass 12, count 2 2006.281.08:14:21.08#ibcon#read 5, iclass 12, count 2 2006.281.08:14:21.08#ibcon#about to read 6, iclass 12, count 2 2006.281.08:14:21.08#ibcon#read 6, iclass 12, count 2 2006.281.08:14:21.08#ibcon#end of sib2, iclass 12, count 2 2006.281.08:14:21.08#ibcon#*after write, iclass 12, count 2 2006.281.08:14:21.08#ibcon#*before return 0, iclass 12, count 2 2006.281.08:14:21.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:21.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:21.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.281.08:14:21.08#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:21.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:14:21.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:14:21.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:14:21.20#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:14:21.20#ibcon#first serial, iclass 12, count 0 2006.281.08:14:21.20#ibcon#enter sib2, iclass 12, count 0 2006.281.08:14:21.20#ibcon#flushed, iclass 12, count 0 2006.281.08:14:21.20#ibcon#about to write, iclass 12, count 0 2006.281.08:14:21.20#ibcon#wrote, iclass 12, count 0 2006.281.08:14:21.20#ibcon#about to read 3, iclass 12, count 0 2006.281.08:14:21.22#ibcon#read 3, iclass 12, count 0 2006.281.08:14:21.22#ibcon#about to read 4, iclass 12, count 0 2006.281.08:14:21.22#ibcon#read 4, iclass 12, count 0 2006.281.08:14:21.22#ibcon#about to read 5, iclass 12, count 0 2006.281.08:14:21.22#ibcon#read 5, iclass 12, count 0 2006.281.08:14:21.22#ibcon#about to read 6, iclass 12, count 0 2006.281.08:14:21.22#ibcon#read 6, iclass 12, count 0 2006.281.08:14:21.22#ibcon#end of sib2, iclass 12, count 0 2006.281.08:14:21.22#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:14:21.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:14:21.22#ibcon#[25=USB\r\n] 2006.281.08:14:21.22#ibcon#*before write, iclass 12, count 0 2006.281.08:14:21.22#ibcon#enter sib2, iclass 12, count 0 2006.281.08:14:21.22#ibcon#flushed, iclass 12, count 0 2006.281.08:14:21.22#ibcon#about to write, iclass 12, count 0 2006.281.08:14:21.22#ibcon#wrote, iclass 12, count 0 2006.281.08:14:21.22#ibcon#about to read 3, iclass 12, count 0 2006.281.08:14:21.25#ibcon#read 3, iclass 12, count 0 2006.281.08:14:21.25#ibcon#about to read 4, iclass 12, count 0 2006.281.08:14:21.25#ibcon#read 4, iclass 12, count 0 2006.281.08:14:21.25#ibcon#about to read 5, iclass 12, count 0 2006.281.08:14:21.25#ibcon#read 5, iclass 12, count 0 2006.281.08:14:21.25#ibcon#about to read 6, iclass 12, count 0 2006.281.08:14:21.25#ibcon#read 6, iclass 12, count 0 2006.281.08:14:21.25#ibcon#end of sib2, iclass 12, count 0 2006.281.08:14:21.25#ibcon#*after write, iclass 12, count 0 2006.281.08:14:21.25#ibcon#*before return 0, iclass 12, count 0 2006.281.08:14:21.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:14:21.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.281.08:14:21.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:14:21.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:14:21.25$vc4f8/valo=7,832.99 2006.281.08:14:21.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:14:21.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:14:21.25#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:21.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:14:21.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:14:21.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:14:21.25#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:14:21.25#ibcon#first serial, iclass 14, count 0 2006.281.08:14:21.25#ibcon#enter sib2, iclass 14, count 0 2006.281.08:14:21.25#ibcon#flushed, iclass 14, count 0 2006.281.08:14:21.25#ibcon#about to write, iclass 14, count 0 2006.281.08:14:21.25#ibcon#wrote, iclass 14, count 0 2006.281.08:14:21.25#ibcon#about to read 3, iclass 14, count 0 2006.281.08:14:21.27#ibcon#read 3, iclass 14, count 0 2006.281.08:14:21.28#ibcon#about to read 4, iclass 14, count 0 2006.281.08:14:21.28#ibcon#read 4, iclass 14, count 0 2006.281.08:14:21.28#ibcon#about to read 5, iclass 14, count 0 2006.281.08:14:21.28#ibcon#read 5, iclass 14, count 0 2006.281.08:14:21.28#ibcon#about to read 6, iclass 14, count 0 2006.281.08:14:21.28#ibcon#read 6, iclass 14, count 0 2006.281.08:14:21.28#ibcon#end of sib2, iclass 14, count 0 2006.281.08:14:21.28#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:14:21.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:14:21.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:14:21.28#ibcon#*before write, iclass 14, count 0 2006.281.08:14:21.28#ibcon#enter sib2, iclass 14, count 0 2006.281.08:14:21.28#ibcon#flushed, iclass 14, count 0 2006.281.08:14:21.28#ibcon#about to write, iclass 14, count 0 2006.281.08:14:21.28#ibcon#wrote, iclass 14, count 0 2006.281.08:14:21.28#ibcon#about to read 3, iclass 14, count 0 2006.281.08:14:21.32#ibcon#read 3, iclass 14, count 0 2006.281.08:14:21.32#ibcon#about to read 4, iclass 14, count 0 2006.281.08:14:21.32#ibcon#read 4, iclass 14, count 0 2006.281.08:14:21.32#ibcon#about to read 5, iclass 14, count 0 2006.281.08:14:21.32#ibcon#read 5, iclass 14, count 0 2006.281.08:14:21.32#ibcon#about to read 6, iclass 14, count 0 2006.281.08:14:21.32#ibcon#read 6, iclass 14, count 0 2006.281.08:14:21.32#ibcon#end of sib2, iclass 14, count 0 2006.281.08:14:21.32#ibcon#*after write, iclass 14, count 0 2006.281.08:14:21.32#ibcon#*before return 0, iclass 14, count 0 2006.281.08:14:21.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:14:21.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:14:21.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:14:21.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:14:21.32$vc4f8/va=7,6 2006.281.08:14:21.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.281.08:14:21.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.281.08:14:21.32#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:21.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:14:21.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:14:21.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:14:21.37#ibcon#enter wrdev, iclass 16, count 2 2006.281.08:14:21.37#ibcon#first serial, iclass 16, count 2 2006.281.08:14:21.37#ibcon#enter sib2, iclass 16, count 2 2006.281.08:14:21.37#ibcon#flushed, iclass 16, count 2 2006.281.08:14:21.37#ibcon#about to write, iclass 16, count 2 2006.281.08:14:21.37#ibcon#wrote, iclass 16, count 2 2006.281.08:14:21.37#ibcon#about to read 3, iclass 16, count 2 2006.281.08:14:21.39#ibcon#read 3, iclass 16, count 2 2006.281.08:14:21.39#ibcon#about to read 4, iclass 16, count 2 2006.281.08:14:21.39#ibcon#read 4, iclass 16, count 2 2006.281.08:14:21.39#ibcon#about to read 5, iclass 16, count 2 2006.281.08:14:21.39#ibcon#read 5, iclass 16, count 2 2006.281.08:14:21.39#ibcon#about to read 6, iclass 16, count 2 2006.281.08:14:21.39#ibcon#read 6, iclass 16, count 2 2006.281.08:14:21.39#ibcon#end of sib2, iclass 16, count 2 2006.281.08:14:21.39#ibcon#*mode == 0, iclass 16, count 2 2006.281.08:14:21.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.281.08:14:21.39#ibcon#[25=AT07-06\r\n] 2006.281.08:14:21.39#ibcon#*before write, iclass 16, count 2 2006.281.08:14:21.39#ibcon#enter sib2, iclass 16, count 2 2006.281.08:14:21.39#ibcon#flushed, iclass 16, count 2 2006.281.08:14:21.39#ibcon#about to write, iclass 16, count 2 2006.281.08:14:21.39#ibcon#wrote, iclass 16, count 2 2006.281.08:14:21.39#ibcon#about to read 3, iclass 16, count 2 2006.281.08:14:21.42#ibcon#read 3, iclass 16, count 2 2006.281.08:14:21.42#ibcon#about to read 4, iclass 16, count 2 2006.281.08:14:21.42#ibcon#read 4, iclass 16, count 2 2006.281.08:14:21.42#ibcon#about to read 5, iclass 16, count 2 2006.281.08:14:21.42#ibcon#read 5, iclass 16, count 2 2006.281.08:14:21.42#ibcon#about to read 6, iclass 16, count 2 2006.281.08:14:21.42#ibcon#read 6, iclass 16, count 2 2006.281.08:14:21.42#ibcon#end of sib2, iclass 16, count 2 2006.281.08:14:21.42#ibcon#*after write, iclass 16, count 2 2006.281.08:14:21.42#ibcon#*before return 0, iclass 16, count 2 2006.281.08:14:21.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:14:21.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.281.08:14:21.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.281.08:14:21.42#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:21.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:14:21.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:14:21.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:14:21.54#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:14:21.54#ibcon#first serial, iclass 16, count 0 2006.281.08:14:21.54#ibcon#enter sib2, iclass 16, count 0 2006.281.08:14:21.54#ibcon#flushed, iclass 16, count 0 2006.281.08:14:21.54#ibcon#about to write, iclass 16, count 0 2006.281.08:14:21.54#ibcon#wrote, iclass 16, count 0 2006.281.08:14:21.54#ibcon#about to read 3, iclass 16, count 0 2006.281.08:14:21.56#ibcon#read 3, iclass 16, count 0 2006.281.08:14:21.56#ibcon#about to read 4, iclass 16, count 0 2006.281.08:14:21.57#ibcon#read 4, iclass 16, count 0 2006.281.08:14:21.57#ibcon#about to read 5, iclass 16, count 0 2006.281.08:14:21.57#ibcon#read 5, iclass 16, count 0 2006.281.08:14:21.57#ibcon#about to read 6, iclass 16, count 0 2006.281.08:14:21.57#ibcon#read 6, iclass 16, count 0 2006.281.08:14:21.57#ibcon#end of sib2, iclass 16, count 0 2006.281.08:14:21.57#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:14:21.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:14:21.57#ibcon#[25=USB\r\n] 2006.281.08:14:21.57#ibcon#*before write, iclass 16, count 0 2006.281.08:14:21.57#ibcon#enter sib2, iclass 16, count 0 2006.281.08:14:21.57#ibcon#flushed, iclass 16, count 0 2006.281.08:14:21.57#ibcon#about to write, iclass 16, count 0 2006.281.08:14:21.57#ibcon#wrote, iclass 16, count 0 2006.281.08:14:21.57#ibcon#about to read 3, iclass 16, count 0 2006.281.08:14:21.59#ibcon#read 3, iclass 16, count 0 2006.281.08:14:21.59#ibcon#about to read 4, iclass 16, count 0 2006.281.08:14:21.59#ibcon#read 4, iclass 16, count 0 2006.281.08:14:21.59#ibcon#about to read 5, iclass 16, count 0 2006.281.08:14:21.59#ibcon#read 5, iclass 16, count 0 2006.281.08:14:21.59#ibcon#about to read 6, iclass 16, count 0 2006.281.08:14:21.59#ibcon#read 6, iclass 16, count 0 2006.281.08:14:21.59#ibcon#end of sib2, iclass 16, count 0 2006.281.08:14:21.59#ibcon#*after write, iclass 16, count 0 2006.281.08:14:21.59#ibcon#*before return 0, iclass 16, count 0 2006.281.08:14:21.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:14:21.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.281.08:14:21.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:14:21.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:14:21.59$vc4f8/valo=8,852.99 2006.281.08:14:21.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.281.08:14:21.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.281.08:14:21.59#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:21.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:14:21.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:14:21.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:14:21.59#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:14:21.59#ibcon#first serial, iclass 18, count 0 2006.281.08:14:21.59#ibcon#enter sib2, iclass 18, count 0 2006.281.08:14:21.59#ibcon#flushed, iclass 18, count 0 2006.281.08:14:21.59#ibcon#about to write, iclass 18, count 0 2006.281.08:14:21.59#ibcon#wrote, iclass 18, count 0 2006.281.08:14:21.59#ibcon#about to read 3, iclass 18, count 0 2006.281.08:14:21.61#ibcon#read 3, iclass 18, count 0 2006.281.08:14:21.61#ibcon#about to read 4, iclass 18, count 0 2006.281.08:14:21.61#ibcon#read 4, iclass 18, count 0 2006.281.08:14:21.61#ibcon#about to read 5, iclass 18, count 0 2006.281.08:14:21.61#ibcon#read 5, iclass 18, count 0 2006.281.08:14:21.61#ibcon#about to read 6, iclass 18, count 0 2006.281.08:14:21.61#ibcon#read 6, iclass 18, count 0 2006.281.08:14:21.61#ibcon#end of sib2, iclass 18, count 0 2006.281.08:14:21.61#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:14:21.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:14:21.61#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:14:21.61#ibcon#*before write, iclass 18, count 0 2006.281.08:14:21.61#ibcon#enter sib2, iclass 18, count 0 2006.281.08:14:21.61#ibcon#flushed, iclass 18, count 0 2006.281.08:14:21.61#ibcon#about to write, iclass 18, count 0 2006.281.08:14:21.61#ibcon#wrote, iclass 18, count 0 2006.281.08:14:21.61#ibcon#about to read 3, iclass 18, count 0 2006.281.08:14:21.65#ibcon#read 3, iclass 18, count 0 2006.281.08:14:21.65#ibcon#about to read 4, iclass 18, count 0 2006.281.08:14:21.65#ibcon#read 4, iclass 18, count 0 2006.281.08:14:21.65#ibcon#about to read 5, iclass 18, count 0 2006.281.08:14:21.65#ibcon#read 5, iclass 18, count 0 2006.281.08:14:21.65#ibcon#about to read 6, iclass 18, count 0 2006.281.08:14:21.65#ibcon#read 6, iclass 18, count 0 2006.281.08:14:21.65#ibcon#end of sib2, iclass 18, count 0 2006.281.08:14:21.65#ibcon#*after write, iclass 18, count 0 2006.281.08:14:21.65#ibcon#*before return 0, iclass 18, count 0 2006.281.08:14:21.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:14:21.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.281.08:14:21.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:14:21.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:14:21.65$vc4f8/va=8,6 2006.281.08:14:21.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.281.08:14:21.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.281.08:14:21.65#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:21.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:14:21.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:14:21.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:14:21.71#ibcon#enter wrdev, iclass 20, count 2 2006.281.08:14:21.71#ibcon#first serial, iclass 20, count 2 2006.281.08:14:21.71#ibcon#enter sib2, iclass 20, count 2 2006.281.08:14:21.71#ibcon#flushed, iclass 20, count 2 2006.281.08:14:21.71#ibcon#about to write, iclass 20, count 2 2006.281.08:14:21.71#ibcon#wrote, iclass 20, count 2 2006.281.08:14:21.71#ibcon#about to read 3, iclass 20, count 2 2006.281.08:14:21.73#ibcon#read 3, iclass 20, count 2 2006.281.08:14:21.73#ibcon#about to read 4, iclass 20, count 2 2006.281.08:14:21.73#ibcon#read 4, iclass 20, count 2 2006.281.08:14:21.73#ibcon#about to read 5, iclass 20, count 2 2006.281.08:14:21.73#ibcon#read 5, iclass 20, count 2 2006.281.08:14:21.73#ibcon#about to read 6, iclass 20, count 2 2006.281.08:14:21.73#ibcon#read 6, iclass 20, count 2 2006.281.08:14:21.73#ibcon#end of sib2, iclass 20, count 2 2006.281.08:14:21.73#ibcon#*mode == 0, iclass 20, count 2 2006.281.08:14:21.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.281.08:14:21.73#ibcon#[25=AT08-06\r\n] 2006.281.08:14:21.73#ibcon#*before write, iclass 20, count 2 2006.281.08:14:21.73#ibcon#enter sib2, iclass 20, count 2 2006.281.08:14:21.73#ibcon#flushed, iclass 20, count 2 2006.281.08:14:21.73#ibcon#about to write, iclass 20, count 2 2006.281.08:14:21.73#ibcon#wrote, iclass 20, count 2 2006.281.08:14:21.73#ibcon#about to read 3, iclass 20, count 2 2006.281.08:14:21.76#ibcon#read 3, iclass 20, count 2 2006.281.08:14:21.76#ibcon#about to read 4, iclass 20, count 2 2006.281.08:14:21.76#ibcon#read 4, iclass 20, count 2 2006.281.08:14:21.76#ibcon#about to read 5, iclass 20, count 2 2006.281.08:14:21.76#ibcon#read 5, iclass 20, count 2 2006.281.08:14:21.76#ibcon#about to read 6, iclass 20, count 2 2006.281.08:14:21.76#ibcon#read 6, iclass 20, count 2 2006.281.08:14:21.76#ibcon#end of sib2, iclass 20, count 2 2006.281.08:14:21.76#ibcon#*after write, iclass 20, count 2 2006.281.08:14:21.76#ibcon#*before return 0, iclass 20, count 2 2006.281.08:14:21.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:14:21.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.281.08:14:21.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.281.08:14:21.76#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:21.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:14:21.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:14:21.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:14:21.88#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:14:21.88#ibcon#first serial, iclass 20, count 0 2006.281.08:14:21.88#ibcon#enter sib2, iclass 20, count 0 2006.281.08:14:21.88#ibcon#flushed, iclass 20, count 0 2006.281.08:14:21.88#ibcon#about to write, iclass 20, count 0 2006.281.08:14:21.88#ibcon#wrote, iclass 20, count 0 2006.281.08:14:21.88#ibcon#about to read 3, iclass 20, count 0 2006.281.08:14:21.90#ibcon#read 3, iclass 20, count 0 2006.281.08:14:21.90#ibcon#about to read 4, iclass 20, count 0 2006.281.08:14:21.90#ibcon#read 4, iclass 20, count 0 2006.281.08:14:21.90#ibcon#about to read 5, iclass 20, count 0 2006.281.08:14:21.90#ibcon#read 5, iclass 20, count 0 2006.281.08:14:21.90#ibcon#about to read 6, iclass 20, count 0 2006.281.08:14:21.90#ibcon#read 6, iclass 20, count 0 2006.281.08:14:21.90#ibcon#end of sib2, iclass 20, count 0 2006.281.08:14:21.90#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:14:21.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:14:21.90#ibcon#[25=USB\r\n] 2006.281.08:14:21.90#ibcon#*before write, iclass 20, count 0 2006.281.08:14:21.90#ibcon#enter sib2, iclass 20, count 0 2006.281.08:14:21.90#ibcon#flushed, iclass 20, count 0 2006.281.08:14:21.90#ibcon#about to write, iclass 20, count 0 2006.281.08:14:21.90#ibcon#wrote, iclass 20, count 0 2006.281.08:14:21.90#ibcon#about to read 3, iclass 20, count 0 2006.281.08:14:21.93#ibcon#read 3, iclass 20, count 0 2006.281.08:14:21.93#ibcon#about to read 4, iclass 20, count 0 2006.281.08:14:21.93#ibcon#read 4, iclass 20, count 0 2006.281.08:14:21.93#ibcon#about to read 5, iclass 20, count 0 2006.281.08:14:21.93#ibcon#read 5, iclass 20, count 0 2006.281.08:14:21.93#ibcon#about to read 6, iclass 20, count 0 2006.281.08:14:21.93#ibcon#read 6, iclass 20, count 0 2006.281.08:14:21.93#ibcon#end of sib2, iclass 20, count 0 2006.281.08:14:21.93#ibcon#*after write, iclass 20, count 0 2006.281.08:14:21.93#ibcon#*before return 0, iclass 20, count 0 2006.281.08:14:21.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:14:21.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.281.08:14:21.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:14:21.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:14:21.93$vc4f8/vblo=1,632.99 2006.281.08:14:21.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.281.08:14:21.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.281.08:14:21.93#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:21.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:14:21.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:14:21.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:14:21.93#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:14:21.93#ibcon#first serial, iclass 22, count 0 2006.281.08:14:21.93#ibcon#enter sib2, iclass 22, count 0 2006.281.08:14:21.93#ibcon#flushed, iclass 22, count 0 2006.281.08:14:21.93#ibcon#about to write, iclass 22, count 0 2006.281.08:14:21.93#ibcon#wrote, iclass 22, count 0 2006.281.08:14:21.93#ibcon#about to read 3, iclass 22, count 0 2006.281.08:14:21.95#ibcon#read 3, iclass 22, count 0 2006.281.08:14:21.95#ibcon#about to read 4, iclass 22, count 0 2006.281.08:14:21.95#ibcon#read 4, iclass 22, count 0 2006.281.08:14:21.95#ibcon#about to read 5, iclass 22, count 0 2006.281.08:14:21.95#ibcon#read 5, iclass 22, count 0 2006.281.08:14:21.95#ibcon#about to read 6, iclass 22, count 0 2006.281.08:14:21.95#ibcon#read 6, iclass 22, count 0 2006.281.08:14:21.95#ibcon#end of sib2, iclass 22, count 0 2006.281.08:14:21.95#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:14:21.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:14:21.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:14:21.95#ibcon#*before write, iclass 22, count 0 2006.281.08:14:21.95#ibcon#enter sib2, iclass 22, count 0 2006.281.08:14:21.95#ibcon#flushed, iclass 22, count 0 2006.281.08:14:21.95#ibcon#about to write, iclass 22, count 0 2006.281.08:14:21.95#ibcon#wrote, iclass 22, count 0 2006.281.08:14:21.95#ibcon#about to read 3, iclass 22, count 0 2006.281.08:14:21.99#ibcon#read 3, iclass 22, count 0 2006.281.08:14:21.99#ibcon#about to read 4, iclass 22, count 0 2006.281.08:14:21.99#ibcon#read 4, iclass 22, count 0 2006.281.08:14:21.99#ibcon#about to read 5, iclass 22, count 0 2006.281.08:14:21.99#ibcon#read 5, iclass 22, count 0 2006.281.08:14:21.99#ibcon#about to read 6, iclass 22, count 0 2006.281.08:14:21.99#ibcon#read 6, iclass 22, count 0 2006.281.08:14:21.99#ibcon#end of sib2, iclass 22, count 0 2006.281.08:14:21.99#ibcon#*after write, iclass 22, count 0 2006.281.08:14:21.99#ibcon#*before return 0, iclass 22, count 0 2006.281.08:14:21.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:14:21.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.281.08:14:21.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:14:21.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:14:21.99$vc4f8/vb=1,4 2006.281.08:14:22.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.281.08:14:22.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.281.08:14:22.01#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:22.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:14:22.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:14:22.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:14:22.01#ibcon#enter wrdev, iclass 24, count 2 2006.281.08:14:22.01#ibcon#first serial, iclass 24, count 2 2006.281.08:14:22.01#ibcon#enter sib2, iclass 24, count 2 2006.281.08:14:22.01#ibcon#flushed, iclass 24, count 2 2006.281.08:14:22.01#ibcon#about to write, iclass 24, count 2 2006.281.08:14:22.01#ibcon#wrote, iclass 24, count 2 2006.281.08:14:22.01#ibcon#about to read 3, iclass 24, count 2 2006.281.08:14:22.02#ibcon#read 3, iclass 24, count 2 2006.281.08:14:22.02#ibcon#about to read 4, iclass 24, count 2 2006.281.08:14:22.02#ibcon#read 4, iclass 24, count 2 2006.281.08:14:22.02#ibcon#about to read 5, iclass 24, count 2 2006.281.08:14:22.02#ibcon#read 5, iclass 24, count 2 2006.281.08:14:22.02#ibcon#about to read 6, iclass 24, count 2 2006.281.08:14:22.02#ibcon#read 6, iclass 24, count 2 2006.281.08:14:22.02#ibcon#end of sib2, iclass 24, count 2 2006.281.08:14:22.02#ibcon#*mode == 0, iclass 24, count 2 2006.281.08:14:22.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.281.08:14:22.02#ibcon#[27=AT01-04\r\n] 2006.281.08:14:22.02#ibcon#*before write, iclass 24, count 2 2006.281.08:14:22.02#ibcon#enter sib2, iclass 24, count 2 2006.281.08:14:22.02#ibcon#flushed, iclass 24, count 2 2006.281.08:14:22.02#ibcon#about to write, iclass 24, count 2 2006.281.08:14:22.02#ibcon#wrote, iclass 24, count 2 2006.281.08:14:22.02#ibcon#about to read 3, iclass 24, count 2 2006.281.08:14:22.05#ibcon#read 3, iclass 24, count 2 2006.281.08:14:22.05#ibcon#about to read 4, iclass 24, count 2 2006.281.08:14:22.05#ibcon#read 4, iclass 24, count 2 2006.281.08:14:22.05#ibcon#about to read 5, iclass 24, count 2 2006.281.08:14:22.05#ibcon#read 5, iclass 24, count 2 2006.281.08:14:22.05#ibcon#about to read 6, iclass 24, count 2 2006.281.08:14:22.05#ibcon#read 6, iclass 24, count 2 2006.281.08:14:22.05#ibcon#end of sib2, iclass 24, count 2 2006.281.08:14:22.05#ibcon#*after write, iclass 24, count 2 2006.281.08:14:22.05#ibcon#*before return 0, iclass 24, count 2 2006.281.08:14:22.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:14:22.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.281.08:14:22.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.281.08:14:22.05#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:22.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:14:22.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:14:22.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:14:22.17#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:14:22.17#ibcon#first serial, iclass 24, count 0 2006.281.08:14:22.17#ibcon#enter sib2, iclass 24, count 0 2006.281.08:14:22.17#ibcon#flushed, iclass 24, count 0 2006.281.08:14:22.17#ibcon#about to write, iclass 24, count 0 2006.281.08:14:22.17#ibcon#wrote, iclass 24, count 0 2006.281.08:14:22.17#ibcon#about to read 3, iclass 24, count 0 2006.281.08:14:22.20#ibcon#read 3, iclass 24, count 0 2006.281.08:14:22.20#ibcon#about to read 4, iclass 24, count 0 2006.281.08:14:22.20#ibcon#read 4, iclass 24, count 0 2006.281.08:14:22.20#ibcon#about to read 5, iclass 24, count 0 2006.281.08:14:22.20#ibcon#read 5, iclass 24, count 0 2006.281.08:14:22.20#ibcon#about to read 6, iclass 24, count 0 2006.281.08:14:22.20#ibcon#read 6, iclass 24, count 0 2006.281.08:14:22.20#ibcon#end of sib2, iclass 24, count 0 2006.281.08:14:22.20#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:14:22.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:14:22.20#ibcon#[27=USB\r\n] 2006.281.08:14:22.20#ibcon#*before write, iclass 24, count 0 2006.281.08:14:22.20#ibcon#enter sib2, iclass 24, count 0 2006.281.08:14:22.20#ibcon#flushed, iclass 24, count 0 2006.281.08:14:22.20#ibcon#about to write, iclass 24, count 0 2006.281.08:14:22.20#ibcon#wrote, iclass 24, count 0 2006.281.08:14:22.20#ibcon#about to read 3, iclass 24, count 0 2006.281.08:14:22.22#ibcon#read 3, iclass 24, count 0 2006.281.08:14:22.22#ibcon#about to read 4, iclass 24, count 0 2006.281.08:14:22.22#ibcon#read 4, iclass 24, count 0 2006.281.08:14:22.22#ibcon#about to read 5, iclass 24, count 0 2006.281.08:14:22.22#ibcon#read 5, iclass 24, count 0 2006.281.08:14:22.22#ibcon#about to read 6, iclass 24, count 0 2006.281.08:14:22.22#ibcon#read 6, iclass 24, count 0 2006.281.08:14:22.22#ibcon#end of sib2, iclass 24, count 0 2006.281.08:14:22.22#ibcon#*after write, iclass 24, count 0 2006.281.08:14:22.22#ibcon#*before return 0, iclass 24, count 0 2006.281.08:14:22.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:14:22.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.281.08:14:22.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:14:22.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:14:22.22$vc4f8/vblo=2,640.99 2006.281.08:14:22.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.281.08:14:22.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.281.08:14:22.22#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:22.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:22.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:22.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:22.22#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:14:22.22#ibcon#first serial, iclass 26, count 0 2006.281.08:14:22.22#ibcon#enter sib2, iclass 26, count 0 2006.281.08:14:22.22#ibcon#flushed, iclass 26, count 0 2006.281.08:14:22.22#ibcon#about to write, iclass 26, count 0 2006.281.08:14:22.22#ibcon#wrote, iclass 26, count 0 2006.281.08:14:22.22#ibcon#about to read 3, iclass 26, count 0 2006.281.08:14:22.24#ibcon#read 3, iclass 26, count 0 2006.281.08:14:22.24#ibcon#about to read 4, iclass 26, count 0 2006.281.08:14:22.24#ibcon#read 4, iclass 26, count 0 2006.281.08:14:22.24#ibcon#about to read 5, iclass 26, count 0 2006.281.08:14:22.24#ibcon#read 5, iclass 26, count 0 2006.281.08:14:22.24#ibcon#about to read 6, iclass 26, count 0 2006.281.08:14:22.24#ibcon#read 6, iclass 26, count 0 2006.281.08:14:22.24#ibcon#end of sib2, iclass 26, count 0 2006.281.08:14:22.24#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:14:22.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:14:22.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:14:22.24#ibcon#*before write, iclass 26, count 0 2006.281.08:14:22.24#ibcon#enter sib2, iclass 26, count 0 2006.281.08:14:22.24#ibcon#flushed, iclass 26, count 0 2006.281.08:14:22.24#ibcon#about to write, iclass 26, count 0 2006.281.08:14:22.24#ibcon#wrote, iclass 26, count 0 2006.281.08:14:22.24#ibcon#about to read 3, iclass 26, count 0 2006.281.08:14:22.28#ibcon#read 3, iclass 26, count 0 2006.281.08:14:22.28#ibcon#about to read 4, iclass 26, count 0 2006.281.08:14:22.28#ibcon#read 4, iclass 26, count 0 2006.281.08:14:22.28#ibcon#about to read 5, iclass 26, count 0 2006.281.08:14:22.28#ibcon#read 5, iclass 26, count 0 2006.281.08:14:22.28#ibcon#about to read 6, iclass 26, count 0 2006.281.08:14:22.28#ibcon#read 6, iclass 26, count 0 2006.281.08:14:22.28#ibcon#end of sib2, iclass 26, count 0 2006.281.08:14:22.28#ibcon#*after write, iclass 26, count 0 2006.281.08:14:22.28#ibcon#*before return 0, iclass 26, count 0 2006.281.08:14:22.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:22.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.281.08:14:22.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:14:22.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:14:22.28$vc4f8/vb=2,5 2006.281.08:14:22.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.281.08:14:22.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.281.08:14:22.28#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:22.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:22.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:22.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:22.34#ibcon#enter wrdev, iclass 28, count 2 2006.281.08:14:22.34#ibcon#first serial, iclass 28, count 2 2006.281.08:14:22.34#ibcon#enter sib2, iclass 28, count 2 2006.281.08:14:22.34#ibcon#flushed, iclass 28, count 2 2006.281.08:14:22.34#ibcon#about to write, iclass 28, count 2 2006.281.08:14:22.34#ibcon#wrote, iclass 28, count 2 2006.281.08:14:22.34#ibcon#about to read 3, iclass 28, count 2 2006.281.08:14:22.36#ibcon#read 3, iclass 28, count 2 2006.281.08:14:22.36#ibcon#about to read 4, iclass 28, count 2 2006.281.08:14:22.36#ibcon#read 4, iclass 28, count 2 2006.281.08:14:22.36#ibcon#about to read 5, iclass 28, count 2 2006.281.08:14:22.36#ibcon#read 5, iclass 28, count 2 2006.281.08:14:22.36#ibcon#about to read 6, iclass 28, count 2 2006.281.08:14:22.36#ibcon#read 6, iclass 28, count 2 2006.281.08:14:22.36#ibcon#end of sib2, iclass 28, count 2 2006.281.08:14:22.36#ibcon#*mode == 0, iclass 28, count 2 2006.281.08:14:22.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.281.08:14:22.36#ibcon#[27=AT02-05\r\n] 2006.281.08:14:22.36#ibcon#*before write, iclass 28, count 2 2006.281.08:14:22.36#ibcon#enter sib2, iclass 28, count 2 2006.281.08:14:22.36#ibcon#flushed, iclass 28, count 2 2006.281.08:14:22.36#ibcon#about to write, iclass 28, count 2 2006.281.08:14:22.36#ibcon#wrote, iclass 28, count 2 2006.281.08:14:22.36#ibcon#about to read 3, iclass 28, count 2 2006.281.08:14:22.39#ibcon#read 3, iclass 28, count 2 2006.281.08:14:22.39#ibcon#about to read 4, iclass 28, count 2 2006.281.08:14:22.39#ibcon#read 4, iclass 28, count 2 2006.281.08:14:22.39#ibcon#about to read 5, iclass 28, count 2 2006.281.08:14:22.39#ibcon#read 5, iclass 28, count 2 2006.281.08:14:22.39#ibcon#about to read 6, iclass 28, count 2 2006.281.08:14:22.39#ibcon#read 6, iclass 28, count 2 2006.281.08:14:22.39#ibcon#end of sib2, iclass 28, count 2 2006.281.08:14:22.39#ibcon#*after write, iclass 28, count 2 2006.281.08:14:22.39#ibcon#*before return 0, iclass 28, count 2 2006.281.08:14:22.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:22.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.281.08:14:22.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.281.08:14:22.39#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:22.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:22.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:22.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:22.51#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:14:22.51#ibcon#first serial, iclass 28, count 0 2006.281.08:14:22.51#ibcon#enter sib2, iclass 28, count 0 2006.281.08:14:22.51#ibcon#flushed, iclass 28, count 0 2006.281.08:14:22.51#ibcon#about to write, iclass 28, count 0 2006.281.08:14:22.51#ibcon#wrote, iclass 28, count 0 2006.281.08:14:22.51#ibcon#about to read 3, iclass 28, count 0 2006.281.08:14:22.53#ibcon#read 3, iclass 28, count 0 2006.281.08:14:22.53#ibcon#about to read 4, iclass 28, count 0 2006.281.08:14:22.53#ibcon#read 4, iclass 28, count 0 2006.281.08:14:22.53#ibcon#about to read 5, iclass 28, count 0 2006.281.08:14:22.53#ibcon#read 5, iclass 28, count 0 2006.281.08:14:22.53#ibcon#about to read 6, iclass 28, count 0 2006.281.08:14:22.53#ibcon#read 6, iclass 28, count 0 2006.281.08:14:22.53#ibcon#end of sib2, iclass 28, count 0 2006.281.08:14:22.53#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:14:22.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:14:22.53#ibcon#[27=USB\r\n] 2006.281.08:14:22.53#ibcon#*before write, iclass 28, count 0 2006.281.08:14:22.53#ibcon#enter sib2, iclass 28, count 0 2006.281.08:14:22.53#ibcon#flushed, iclass 28, count 0 2006.281.08:14:22.53#ibcon#about to write, iclass 28, count 0 2006.281.08:14:22.53#ibcon#wrote, iclass 28, count 0 2006.281.08:14:22.53#ibcon#about to read 3, iclass 28, count 0 2006.281.08:14:22.56#ibcon#read 3, iclass 28, count 0 2006.281.08:14:22.56#ibcon#about to read 4, iclass 28, count 0 2006.281.08:14:22.56#ibcon#read 4, iclass 28, count 0 2006.281.08:14:22.56#ibcon#about to read 5, iclass 28, count 0 2006.281.08:14:22.56#ibcon#read 5, iclass 28, count 0 2006.281.08:14:22.56#ibcon#about to read 6, iclass 28, count 0 2006.281.08:14:22.56#ibcon#read 6, iclass 28, count 0 2006.281.08:14:22.56#ibcon#end of sib2, iclass 28, count 0 2006.281.08:14:22.56#ibcon#*after write, iclass 28, count 0 2006.281.08:14:22.56#ibcon#*before return 0, iclass 28, count 0 2006.281.08:14:22.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:22.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.281.08:14:22.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:14:22.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:14:22.56$vc4f8/vblo=3,656.99 2006.281.08:14:22.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.281.08:14:22.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.281.08:14:22.56#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:22.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:22.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:22.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:22.56#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:14:22.56#ibcon#first serial, iclass 30, count 0 2006.281.08:14:22.56#ibcon#enter sib2, iclass 30, count 0 2006.281.08:14:22.56#ibcon#flushed, iclass 30, count 0 2006.281.08:14:22.56#ibcon#about to write, iclass 30, count 0 2006.281.08:14:22.56#ibcon#wrote, iclass 30, count 0 2006.281.08:14:22.56#ibcon#about to read 3, iclass 30, count 0 2006.281.08:14:22.58#ibcon#read 3, iclass 30, count 0 2006.281.08:14:22.58#ibcon#about to read 4, iclass 30, count 0 2006.281.08:14:22.58#ibcon#read 4, iclass 30, count 0 2006.281.08:14:22.58#ibcon#about to read 5, iclass 30, count 0 2006.281.08:14:22.58#ibcon#read 5, iclass 30, count 0 2006.281.08:14:22.58#ibcon#about to read 6, iclass 30, count 0 2006.281.08:14:22.58#ibcon#read 6, iclass 30, count 0 2006.281.08:14:22.58#ibcon#end of sib2, iclass 30, count 0 2006.281.08:14:22.58#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:14:22.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:14:22.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:14:22.58#ibcon#*before write, iclass 30, count 0 2006.281.08:14:22.58#ibcon#enter sib2, iclass 30, count 0 2006.281.08:14:22.58#ibcon#flushed, iclass 30, count 0 2006.281.08:14:22.58#ibcon#about to write, iclass 30, count 0 2006.281.08:14:22.58#ibcon#wrote, iclass 30, count 0 2006.281.08:14:22.58#ibcon#about to read 3, iclass 30, count 0 2006.281.08:14:22.63#ibcon#read 3, iclass 30, count 0 2006.281.08:14:22.63#ibcon#about to read 4, iclass 30, count 0 2006.281.08:14:22.63#ibcon#read 4, iclass 30, count 0 2006.281.08:14:22.63#ibcon#about to read 5, iclass 30, count 0 2006.281.08:14:22.63#ibcon#read 5, iclass 30, count 0 2006.281.08:14:22.63#ibcon#about to read 6, iclass 30, count 0 2006.281.08:14:22.63#ibcon#read 6, iclass 30, count 0 2006.281.08:14:22.63#ibcon#end of sib2, iclass 30, count 0 2006.281.08:14:22.63#ibcon#*after write, iclass 30, count 0 2006.281.08:14:22.63#ibcon#*before return 0, iclass 30, count 0 2006.281.08:14:22.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:22.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.281.08:14:22.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:14:22.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:14:22.63$vc4f8/vb=3,4 2006.281.08:14:22.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.281.08:14:22.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.281.08:14:22.63#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:22.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:22.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:22.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:22.67#ibcon#enter wrdev, iclass 32, count 2 2006.281.08:14:22.67#ibcon#first serial, iclass 32, count 2 2006.281.08:14:22.67#ibcon#enter sib2, iclass 32, count 2 2006.281.08:14:22.67#ibcon#flushed, iclass 32, count 2 2006.281.08:14:22.67#ibcon#about to write, iclass 32, count 2 2006.281.08:14:22.67#ibcon#wrote, iclass 32, count 2 2006.281.08:14:22.67#ibcon#about to read 3, iclass 32, count 2 2006.281.08:14:22.70#ibcon#read 3, iclass 32, count 2 2006.281.08:14:22.70#ibcon#about to read 4, iclass 32, count 2 2006.281.08:14:22.70#ibcon#read 4, iclass 32, count 2 2006.281.08:14:22.70#ibcon#about to read 5, iclass 32, count 2 2006.281.08:14:22.70#ibcon#read 5, iclass 32, count 2 2006.281.08:14:22.70#ibcon#about to read 6, iclass 32, count 2 2006.281.08:14:22.70#ibcon#read 6, iclass 32, count 2 2006.281.08:14:22.70#ibcon#end of sib2, iclass 32, count 2 2006.281.08:14:22.70#ibcon#*mode == 0, iclass 32, count 2 2006.281.08:14:22.70#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.281.08:14:22.70#ibcon#[27=AT03-04\r\n] 2006.281.08:14:22.70#ibcon#*before write, iclass 32, count 2 2006.281.08:14:22.70#ibcon#enter sib2, iclass 32, count 2 2006.281.08:14:22.70#ibcon#flushed, iclass 32, count 2 2006.281.08:14:22.70#ibcon#about to write, iclass 32, count 2 2006.281.08:14:22.70#ibcon#wrote, iclass 32, count 2 2006.281.08:14:22.70#ibcon#about to read 3, iclass 32, count 2 2006.281.08:14:22.73#ibcon#read 3, iclass 32, count 2 2006.281.08:14:22.73#ibcon#about to read 4, iclass 32, count 2 2006.281.08:14:22.73#ibcon#read 4, iclass 32, count 2 2006.281.08:14:22.73#ibcon#about to read 5, iclass 32, count 2 2006.281.08:14:22.73#ibcon#read 5, iclass 32, count 2 2006.281.08:14:22.73#ibcon#about to read 6, iclass 32, count 2 2006.281.08:14:22.73#ibcon#read 6, iclass 32, count 2 2006.281.08:14:22.73#ibcon#end of sib2, iclass 32, count 2 2006.281.08:14:22.73#ibcon#*after write, iclass 32, count 2 2006.281.08:14:22.73#ibcon#*before return 0, iclass 32, count 2 2006.281.08:14:22.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:22.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.281.08:14:22.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.281.08:14:22.73#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:22.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:22.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:22.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:22.85#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:14:22.85#ibcon#first serial, iclass 32, count 0 2006.281.08:14:22.85#ibcon#enter sib2, iclass 32, count 0 2006.281.08:14:22.85#ibcon#flushed, iclass 32, count 0 2006.281.08:14:22.85#ibcon#about to write, iclass 32, count 0 2006.281.08:14:22.85#ibcon#wrote, iclass 32, count 0 2006.281.08:14:22.85#ibcon#about to read 3, iclass 32, count 0 2006.281.08:14:22.87#ibcon#read 3, iclass 32, count 0 2006.281.08:14:22.87#ibcon#about to read 4, iclass 32, count 0 2006.281.08:14:22.87#ibcon#read 4, iclass 32, count 0 2006.281.08:14:22.87#ibcon#about to read 5, iclass 32, count 0 2006.281.08:14:22.87#ibcon#read 5, iclass 32, count 0 2006.281.08:14:22.87#ibcon#about to read 6, iclass 32, count 0 2006.281.08:14:22.87#ibcon#read 6, iclass 32, count 0 2006.281.08:14:22.87#ibcon#end of sib2, iclass 32, count 0 2006.281.08:14:22.87#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:14:22.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:14:22.87#ibcon#[27=USB\r\n] 2006.281.08:14:22.87#ibcon#*before write, iclass 32, count 0 2006.281.08:14:22.87#ibcon#enter sib2, iclass 32, count 0 2006.281.08:14:22.87#ibcon#flushed, iclass 32, count 0 2006.281.08:14:22.87#ibcon#about to write, iclass 32, count 0 2006.281.08:14:22.87#ibcon#wrote, iclass 32, count 0 2006.281.08:14:22.87#ibcon#about to read 3, iclass 32, count 0 2006.281.08:14:22.90#ibcon#read 3, iclass 32, count 0 2006.281.08:14:22.90#ibcon#about to read 4, iclass 32, count 0 2006.281.08:14:22.90#ibcon#read 4, iclass 32, count 0 2006.281.08:14:22.90#ibcon#about to read 5, iclass 32, count 0 2006.281.08:14:22.90#ibcon#read 5, iclass 32, count 0 2006.281.08:14:22.90#ibcon#about to read 6, iclass 32, count 0 2006.281.08:14:22.90#ibcon#read 6, iclass 32, count 0 2006.281.08:14:22.90#ibcon#end of sib2, iclass 32, count 0 2006.281.08:14:22.90#ibcon#*after write, iclass 32, count 0 2006.281.08:14:22.90#ibcon#*before return 0, iclass 32, count 0 2006.281.08:14:22.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:22.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.281.08:14:22.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:14:22.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:14:22.90$vc4f8/vblo=4,712.99 2006.281.08:14:22.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.281.08:14:22.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.281.08:14:22.90#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:22.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:22.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:22.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:22.90#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:14:22.90#ibcon#first serial, iclass 34, count 0 2006.281.08:14:22.90#ibcon#enter sib2, iclass 34, count 0 2006.281.08:14:22.90#ibcon#flushed, iclass 34, count 0 2006.281.08:14:22.90#ibcon#about to write, iclass 34, count 0 2006.281.08:14:22.90#ibcon#wrote, iclass 34, count 0 2006.281.08:14:22.90#ibcon#about to read 3, iclass 34, count 0 2006.281.08:14:22.92#ibcon#read 3, iclass 34, count 0 2006.281.08:14:22.92#ibcon#about to read 4, iclass 34, count 0 2006.281.08:14:22.92#ibcon#read 4, iclass 34, count 0 2006.281.08:14:22.92#ibcon#about to read 5, iclass 34, count 0 2006.281.08:14:22.92#ibcon#read 5, iclass 34, count 0 2006.281.08:14:22.92#ibcon#about to read 6, iclass 34, count 0 2006.281.08:14:22.92#ibcon#read 6, iclass 34, count 0 2006.281.08:14:22.92#ibcon#end of sib2, iclass 34, count 0 2006.281.08:14:22.92#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:14:22.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:14:22.95#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:14:22.95#ibcon#*before write, iclass 34, count 0 2006.281.08:14:22.95#ibcon#enter sib2, iclass 34, count 0 2006.281.08:14:22.95#ibcon#flushed, iclass 34, count 0 2006.281.08:14:22.95#ibcon#about to write, iclass 34, count 0 2006.281.08:14:22.95#ibcon#wrote, iclass 34, count 0 2006.281.08:14:22.95#ibcon#about to read 3, iclass 34, count 0 2006.281.08:14:22.98#ibcon#read 3, iclass 34, count 0 2006.281.08:14:22.98#ibcon#about to read 4, iclass 34, count 0 2006.281.08:14:22.98#ibcon#read 4, iclass 34, count 0 2006.281.08:14:22.98#ibcon#about to read 5, iclass 34, count 0 2006.281.08:14:22.98#ibcon#read 5, iclass 34, count 0 2006.281.08:14:22.98#ibcon#about to read 6, iclass 34, count 0 2006.281.08:14:22.98#ibcon#read 6, iclass 34, count 0 2006.281.08:14:22.98#ibcon#end of sib2, iclass 34, count 0 2006.281.08:14:22.98#ibcon#*after write, iclass 34, count 0 2006.281.08:14:22.98#ibcon#*before return 0, iclass 34, count 0 2006.281.08:14:22.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:22.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.281.08:14:22.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:14:22.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:14:22.98$vc4f8/vb=4,4 2006.281.08:14:22.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.281.08:14:22.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.281.08:14:22.98#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:22.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:23.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:23.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:23.02#ibcon#enter wrdev, iclass 36, count 2 2006.281.08:14:23.02#ibcon#first serial, iclass 36, count 2 2006.281.08:14:23.02#ibcon#enter sib2, iclass 36, count 2 2006.281.08:14:23.02#ibcon#flushed, iclass 36, count 2 2006.281.08:14:23.02#ibcon#about to write, iclass 36, count 2 2006.281.08:14:23.02#ibcon#wrote, iclass 36, count 2 2006.281.08:14:23.02#ibcon#about to read 3, iclass 36, count 2 2006.281.08:14:23.04#ibcon#read 3, iclass 36, count 2 2006.281.08:14:23.04#ibcon#about to read 4, iclass 36, count 2 2006.281.08:14:23.04#ibcon#read 4, iclass 36, count 2 2006.281.08:14:23.04#ibcon#about to read 5, iclass 36, count 2 2006.281.08:14:23.04#ibcon#read 5, iclass 36, count 2 2006.281.08:14:23.04#ibcon#about to read 6, iclass 36, count 2 2006.281.08:14:23.04#ibcon#read 6, iclass 36, count 2 2006.281.08:14:23.04#ibcon#end of sib2, iclass 36, count 2 2006.281.08:14:23.04#ibcon#*mode == 0, iclass 36, count 2 2006.281.08:14:23.04#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.281.08:14:23.04#ibcon#[27=AT04-04\r\n] 2006.281.08:14:23.04#ibcon#*before write, iclass 36, count 2 2006.281.08:14:23.04#ibcon#enter sib2, iclass 36, count 2 2006.281.08:14:23.04#ibcon#flushed, iclass 36, count 2 2006.281.08:14:23.04#ibcon#about to write, iclass 36, count 2 2006.281.08:14:23.04#ibcon#wrote, iclass 36, count 2 2006.281.08:14:23.04#ibcon#about to read 3, iclass 36, count 2 2006.281.08:14:23.07#ibcon#read 3, iclass 36, count 2 2006.281.08:14:23.07#ibcon#about to read 4, iclass 36, count 2 2006.281.08:14:23.07#ibcon#read 4, iclass 36, count 2 2006.281.08:14:23.07#ibcon#about to read 5, iclass 36, count 2 2006.281.08:14:23.07#ibcon#read 5, iclass 36, count 2 2006.281.08:14:23.07#ibcon#about to read 6, iclass 36, count 2 2006.281.08:14:23.07#ibcon#read 6, iclass 36, count 2 2006.281.08:14:23.07#ibcon#end of sib2, iclass 36, count 2 2006.281.08:14:23.07#ibcon#*after write, iclass 36, count 2 2006.281.08:14:23.07#ibcon#*before return 0, iclass 36, count 2 2006.281.08:14:23.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:23.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.281.08:14:23.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.281.08:14:23.07#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:23.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:23.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:23.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:23.20#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:14:23.20#ibcon#first serial, iclass 36, count 0 2006.281.08:14:23.20#ibcon#enter sib2, iclass 36, count 0 2006.281.08:14:23.20#ibcon#flushed, iclass 36, count 0 2006.281.08:14:23.20#ibcon#about to write, iclass 36, count 0 2006.281.08:14:23.20#ibcon#wrote, iclass 36, count 0 2006.281.08:14:23.20#ibcon#about to read 3, iclass 36, count 0 2006.281.08:14:23.21#ibcon#read 3, iclass 36, count 0 2006.281.08:14:23.21#ibcon#about to read 4, iclass 36, count 0 2006.281.08:14:23.21#ibcon#read 4, iclass 36, count 0 2006.281.08:14:23.21#ibcon#about to read 5, iclass 36, count 0 2006.281.08:14:23.21#ibcon#read 5, iclass 36, count 0 2006.281.08:14:23.21#ibcon#about to read 6, iclass 36, count 0 2006.281.08:14:23.21#ibcon#read 6, iclass 36, count 0 2006.281.08:14:23.21#ibcon#end of sib2, iclass 36, count 0 2006.281.08:14:23.21#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:14:23.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:14:23.21#ibcon#[27=USB\r\n] 2006.281.08:14:23.21#ibcon#*before write, iclass 36, count 0 2006.281.08:14:23.21#ibcon#enter sib2, iclass 36, count 0 2006.281.08:14:23.21#ibcon#flushed, iclass 36, count 0 2006.281.08:14:23.21#ibcon#about to write, iclass 36, count 0 2006.281.08:14:23.21#ibcon#wrote, iclass 36, count 0 2006.281.08:14:23.21#ibcon#about to read 3, iclass 36, count 0 2006.281.08:14:23.24#ibcon#read 3, iclass 36, count 0 2006.281.08:14:23.24#ibcon#about to read 4, iclass 36, count 0 2006.281.08:14:23.24#ibcon#read 4, iclass 36, count 0 2006.281.08:14:23.24#ibcon#about to read 5, iclass 36, count 0 2006.281.08:14:23.24#ibcon#read 5, iclass 36, count 0 2006.281.08:14:23.24#ibcon#about to read 6, iclass 36, count 0 2006.281.08:14:23.24#ibcon#read 6, iclass 36, count 0 2006.281.08:14:23.24#ibcon#end of sib2, iclass 36, count 0 2006.281.08:14:23.24#ibcon#*after write, iclass 36, count 0 2006.281.08:14:23.24#ibcon#*before return 0, iclass 36, count 0 2006.281.08:14:23.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:23.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.281.08:14:23.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:14:23.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:14:23.24$vc4f8/vblo=5,744.99 2006.281.08:14:23.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.281.08:14:23.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.281.08:14:23.24#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:23.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:23.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:23.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:23.24#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:14:23.24#ibcon#first serial, iclass 38, count 0 2006.281.08:14:23.24#ibcon#enter sib2, iclass 38, count 0 2006.281.08:14:23.24#ibcon#flushed, iclass 38, count 0 2006.281.08:14:23.24#ibcon#about to write, iclass 38, count 0 2006.281.08:14:23.24#ibcon#wrote, iclass 38, count 0 2006.281.08:14:23.24#ibcon#about to read 3, iclass 38, count 0 2006.281.08:14:23.26#ibcon#read 3, iclass 38, count 0 2006.281.08:14:23.26#ibcon#about to read 4, iclass 38, count 0 2006.281.08:14:23.26#ibcon#read 4, iclass 38, count 0 2006.281.08:14:23.26#ibcon#about to read 5, iclass 38, count 0 2006.281.08:14:23.26#ibcon#read 5, iclass 38, count 0 2006.281.08:14:23.26#ibcon#about to read 6, iclass 38, count 0 2006.281.08:14:23.26#ibcon#read 6, iclass 38, count 0 2006.281.08:14:23.26#ibcon#end of sib2, iclass 38, count 0 2006.281.08:14:23.26#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:14:23.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:14:23.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:14:23.26#ibcon#*before write, iclass 38, count 0 2006.281.08:14:23.26#ibcon#enter sib2, iclass 38, count 0 2006.281.08:14:23.26#ibcon#flushed, iclass 38, count 0 2006.281.08:14:23.26#ibcon#about to write, iclass 38, count 0 2006.281.08:14:23.26#ibcon#wrote, iclass 38, count 0 2006.281.08:14:23.26#ibcon#about to read 3, iclass 38, count 0 2006.281.08:14:23.30#ibcon#read 3, iclass 38, count 0 2006.281.08:14:23.30#ibcon#about to read 4, iclass 38, count 0 2006.281.08:14:23.30#ibcon#read 4, iclass 38, count 0 2006.281.08:14:23.30#ibcon#about to read 5, iclass 38, count 0 2006.281.08:14:23.30#ibcon#read 5, iclass 38, count 0 2006.281.08:14:23.30#ibcon#about to read 6, iclass 38, count 0 2006.281.08:14:23.30#ibcon#read 6, iclass 38, count 0 2006.281.08:14:23.30#ibcon#end of sib2, iclass 38, count 0 2006.281.08:14:23.30#ibcon#*after write, iclass 38, count 0 2006.281.08:14:23.30#ibcon#*before return 0, iclass 38, count 0 2006.281.08:14:23.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:23.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.281.08:14:23.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:14:23.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:14:23.31$vc4f8/vb=5,4 2006.281.08:14:23.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.281.08:14:23.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.281.08:14:23.31#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:23.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:23.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:23.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:23.35#ibcon#enter wrdev, iclass 40, count 2 2006.281.08:14:23.35#ibcon#first serial, iclass 40, count 2 2006.281.08:14:23.35#ibcon#enter sib2, iclass 40, count 2 2006.281.08:14:23.35#ibcon#flushed, iclass 40, count 2 2006.281.08:14:23.35#ibcon#about to write, iclass 40, count 2 2006.281.08:14:23.35#ibcon#wrote, iclass 40, count 2 2006.281.08:14:23.35#ibcon#about to read 3, iclass 40, count 2 2006.281.08:14:23.37#ibcon#read 3, iclass 40, count 2 2006.281.08:14:23.37#ibcon#about to read 4, iclass 40, count 2 2006.281.08:14:23.37#ibcon#read 4, iclass 40, count 2 2006.281.08:14:23.37#ibcon#about to read 5, iclass 40, count 2 2006.281.08:14:23.37#ibcon#read 5, iclass 40, count 2 2006.281.08:14:23.37#ibcon#about to read 6, iclass 40, count 2 2006.281.08:14:23.37#ibcon#read 6, iclass 40, count 2 2006.281.08:14:23.37#ibcon#end of sib2, iclass 40, count 2 2006.281.08:14:23.37#ibcon#*mode == 0, iclass 40, count 2 2006.281.08:14:23.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.281.08:14:23.37#ibcon#[27=AT05-04\r\n] 2006.281.08:14:23.37#ibcon#*before write, iclass 40, count 2 2006.281.08:14:23.37#ibcon#enter sib2, iclass 40, count 2 2006.281.08:14:23.37#ibcon#flushed, iclass 40, count 2 2006.281.08:14:23.37#ibcon#about to write, iclass 40, count 2 2006.281.08:14:23.37#ibcon#wrote, iclass 40, count 2 2006.281.08:14:23.37#ibcon#about to read 3, iclass 40, count 2 2006.281.08:14:23.40#ibcon#read 3, iclass 40, count 2 2006.281.08:14:23.40#ibcon#about to read 4, iclass 40, count 2 2006.281.08:14:23.40#ibcon#read 4, iclass 40, count 2 2006.281.08:14:23.40#ibcon#about to read 5, iclass 40, count 2 2006.281.08:14:23.40#ibcon#read 5, iclass 40, count 2 2006.281.08:14:23.40#ibcon#about to read 6, iclass 40, count 2 2006.281.08:14:23.40#ibcon#read 6, iclass 40, count 2 2006.281.08:14:23.40#ibcon#end of sib2, iclass 40, count 2 2006.281.08:14:23.40#ibcon#*after write, iclass 40, count 2 2006.281.08:14:23.40#ibcon#*before return 0, iclass 40, count 2 2006.281.08:14:23.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:23.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.281.08:14:23.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.281.08:14:23.40#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:23.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:23.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:23.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:23.52#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:14:23.52#ibcon#first serial, iclass 40, count 0 2006.281.08:14:23.52#ibcon#enter sib2, iclass 40, count 0 2006.281.08:14:23.52#ibcon#flushed, iclass 40, count 0 2006.281.08:14:23.52#ibcon#about to write, iclass 40, count 0 2006.281.08:14:23.52#ibcon#wrote, iclass 40, count 0 2006.281.08:14:23.52#ibcon#about to read 3, iclass 40, count 0 2006.281.08:14:23.54#ibcon#read 3, iclass 40, count 0 2006.281.08:14:23.54#ibcon#about to read 4, iclass 40, count 0 2006.281.08:14:23.54#ibcon#read 4, iclass 40, count 0 2006.281.08:14:23.54#ibcon#about to read 5, iclass 40, count 0 2006.281.08:14:23.54#ibcon#read 5, iclass 40, count 0 2006.281.08:14:23.54#ibcon#about to read 6, iclass 40, count 0 2006.281.08:14:23.54#ibcon#read 6, iclass 40, count 0 2006.281.08:14:23.54#ibcon#end of sib2, iclass 40, count 0 2006.281.08:14:23.54#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:14:23.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:14:23.54#ibcon#[27=USB\r\n] 2006.281.08:14:23.54#ibcon#*before write, iclass 40, count 0 2006.281.08:14:23.54#ibcon#enter sib2, iclass 40, count 0 2006.281.08:14:23.54#ibcon#flushed, iclass 40, count 0 2006.281.08:14:23.54#ibcon#about to write, iclass 40, count 0 2006.281.08:14:23.54#ibcon#wrote, iclass 40, count 0 2006.281.08:14:23.54#ibcon#about to read 3, iclass 40, count 0 2006.281.08:14:23.57#ibcon#read 3, iclass 40, count 0 2006.281.08:14:23.57#ibcon#about to read 4, iclass 40, count 0 2006.281.08:14:23.57#ibcon#read 4, iclass 40, count 0 2006.281.08:14:23.57#ibcon#about to read 5, iclass 40, count 0 2006.281.08:14:23.57#ibcon#read 5, iclass 40, count 0 2006.281.08:14:23.57#ibcon#about to read 6, iclass 40, count 0 2006.281.08:14:23.57#ibcon#read 6, iclass 40, count 0 2006.281.08:14:23.57#ibcon#end of sib2, iclass 40, count 0 2006.281.08:14:23.57#ibcon#*after write, iclass 40, count 0 2006.281.08:14:23.57#ibcon#*before return 0, iclass 40, count 0 2006.281.08:14:23.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:23.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.281.08:14:23.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:14:23.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:14:23.57$vc4f8/vblo=6,752.99 2006.281.08:14:23.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.281.08:14:23.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.281.08:14:23.57#ibcon#ireg 17 cls_cnt 0 2006.281.08:14:23.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:23.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:23.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:23.57#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:14:23.57#ibcon#first serial, iclass 4, count 0 2006.281.08:14:23.57#ibcon#enter sib2, iclass 4, count 0 2006.281.08:14:23.57#ibcon#flushed, iclass 4, count 0 2006.281.08:14:23.57#ibcon#about to write, iclass 4, count 0 2006.281.08:14:23.57#ibcon#wrote, iclass 4, count 0 2006.281.08:14:23.57#ibcon#about to read 3, iclass 4, count 0 2006.281.08:14:23.59#ibcon#read 3, iclass 4, count 0 2006.281.08:14:23.59#ibcon#about to read 4, iclass 4, count 0 2006.281.08:14:23.59#ibcon#read 4, iclass 4, count 0 2006.281.08:14:23.59#ibcon#about to read 5, iclass 4, count 0 2006.281.08:14:23.59#ibcon#read 5, iclass 4, count 0 2006.281.08:14:23.59#ibcon#about to read 6, iclass 4, count 0 2006.281.08:14:23.59#ibcon#read 6, iclass 4, count 0 2006.281.08:14:23.59#ibcon#end of sib2, iclass 4, count 0 2006.281.08:14:23.59#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:14:23.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:14:23.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:14:23.59#ibcon#*before write, iclass 4, count 0 2006.281.08:14:23.59#ibcon#enter sib2, iclass 4, count 0 2006.281.08:14:23.59#ibcon#flushed, iclass 4, count 0 2006.281.08:14:23.59#ibcon#about to write, iclass 4, count 0 2006.281.08:14:23.59#ibcon#wrote, iclass 4, count 0 2006.281.08:14:23.59#ibcon#about to read 3, iclass 4, count 0 2006.281.08:14:23.64#ibcon#read 3, iclass 4, count 0 2006.281.08:14:23.64#ibcon#about to read 4, iclass 4, count 0 2006.281.08:14:23.64#ibcon#read 4, iclass 4, count 0 2006.281.08:14:23.64#ibcon#about to read 5, iclass 4, count 0 2006.281.08:14:23.64#ibcon#read 5, iclass 4, count 0 2006.281.08:14:23.64#ibcon#about to read 6, iclass 4, count 0 2006.281.08:14:23.64#ibcon#read 6, iclass 4, count 0 2006.281.08:14:23.64#ibcon#end of sib2, iclass 4, count 0 2006.281.08:14:23.64#ibcon#*after write, iclass 4, count 0 2006.281.08:14:23.64#ibcon#*before return 0, iclass 4, count 0 2006.281.08:14:23.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:23.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.281.08:14:23.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:14:23.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:14:23.64$vc4f8/vb=6,4 2006.281.08:14:23.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.281.08:14:23.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.281.08:14:23.64#ibcon#ireg 11 cls_cnt 2 2006.281.08:14:23.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:23.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:23.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:23.68#ibcon#enter wrdev, iclass 6, count 2 2006.281.08:14:23.68#ibcon#first serial, iclass 6, count 2 2006.281.08:14:23.68#ibcon#enter sib2, iclass 6, count 2 2006.281.08:14:23.68#ibcon#flushed, iclass 6, count 2 2006.281.08:14:23.68#ibcon#about to write, iclass 6, count 2 2006.281.08:14:23.68#ibcon#wrote, iclass 6, count 2 2006.281.08:14:23.68#ibcon#about to read 3, iclass 6, count 2 2006.281.08:14:23.71#ibcon#read 3, iclass 6, count 2 2006.281.08:14:23.71#ibcon#about to read 4, iclass 6, count 2 2006.281.08:14:23.71#ibcon#read 4, iclass 6, count 2 2006.281.08:14:23.71#ibcon#about to read 5, iclass 6, count 2 2006.281.08:14:23.71#ibcon#read 5, iclass 6, count 2 2006.281.08:14:23.71#ibcon#about to read 6, iclass 6, count 2 2006.281.08:14:23.71#ibcon#read 6, iclass 6, count 2 2006.281.08:14:23.71#ibcon#end of sib2, iclass 6, count 2 2006.281.08:14:23.71#ibcon#*mode == 0, iclass 6, count 2 2006.281.08:14:23.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.281.08:14:23.71#ibcon#[27=AT06-04\r\n] 2006.281.08:14:23.71#ibcon#*before write, iclass 6, count 2 2006.281.08:14:23.71#ibcon#enter sib2, iclass 6, count 2 2006.281.08:14:23.71#ibcon#flushed, iclass 6, count 2 2006.281.08:14:23.71#ibcon#about to write, iclass 6, count 2 2006.281.08:14:23.71#ibcon#wrote, iclass 6, count 2 2006.281.08:14:23.71#ibcon#about to read 3, iclass 6, count 2 2006.281.08:14:23.74#ibcon#read 3, iclass 6, count 2 2006.281.08:14:23.74#ibcon#about to read 4, iclass 6, count 2 2006.281.08:14:23.74#ibcon#read 4, iclass 6, count 2 2006.281.08:14:23.74#ibcon#about to read 5, iclass 6, count 2 2006.281.08:14:23.74#ibcon#read 5, iclass 6, count 2 2006.281.08:14:23.74#ibcon#about to read 6, iclass 6, count 2 2006.281.08:14:23.74#ibcon#read 6, iclass 6, count 2 2006.281.08:14:23.74#ibcon#end of sib2, iclass 6, count 2 2006.281.08:14:23.74#ibcon#*after write, iclass 6, count 2 2006.281.08:14:23.74#ibcon#*before return 0, iclass 6, count 2 2006.281.08:14:23.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:23.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.281.08:14:23.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.281.08:14:23.74#ibcon#ireg 7 cls_cnt 0 2006.281.08:14:23.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:23.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:23.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:23.86#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:14:23.86#ibcon#first serial, iclass 6, count 0 2006.281.08:14:23.86#ibcon#enter sib2, iclass 6, count 0 2006.281.08:14:23.86#ibcon#flushed, iclass 6, count 0 2006.281.08:14:23.86#ibcon#about to write, iclass 6, count 0 2006.281.08:14:23.86#ibcon#wrote, iclass 6, count 0 2006.281.08:14:23.86#ibcon#about to read 3, iclass 6, count 0 2006.281.08:14:23.88#ibcon#read 3, iclass 6, count 0 2006.281.08:14:23.88#ibcon#about to read 4, iclass 6, count 0 2006.281.08:14:23.88#ibcon#read 4, iclass 6, count 0 2006.281.08:14:23.88#ibcon#about to read 5, iclass 6, count 0 2006.281.08:14:23.88#ibcon#read 5, iclass 6, count 0 2006.281.08:14:23.88#ibcon#about to read 6, iclass 6, count 0 2006.281.08:14:23.88#ibcon#read 6, iclass 6, count 0 2006.281.08:14:23.88#ibcon#end of sib2, iclass 6, count 0 2006.281.08:14:23.88#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:14:23.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:14:23.88#ibcon#[27=USB\r\n] 2006.281.08:14:23.88#ibcon#*before write, iclass 6, count 0 2006.281.08:14:23.88#ibcon#enter sib2, iclass 6, count 0 2006.281.08:14:23.88#ibcon#flushed, iclass 6, count 0 2006.281.08:14:23.88#ibcon#about to write, iclass 6, count 0 2006.281.08:14:23.88#ibcon#wrote, iclass 6, count 0 2006.281.08:14:23.88#ibcon#about to read 3, iclass 6, count 0 2006.281.08:14:23.92#ibcon#read 3, iclass 6, count 0 2006.281.08:14:23.92#ibcon#about to read 4, iclass 6, count 0 2006.281.08:14:23.92#ibcon#read 4, iclass 6, count 0 2006.281.08:14:23.92#ibcon#about to read 5, iclass 6, count 0 2006.281.08:14:23.92#ibcon#read 5, iclass 6, count 0 2006.281.08:14:23.92#ibcon#about to read 6, iclass 6, count 0 2006.281.08:14:23.92#ibcon#read 6, iclass 6, count 0 2006.281.08:14:23.92#ibcon#end of sib2, iclass 6, count 0 2006.281.08:14:23.92#ibcon#*after write, iclass 6, count 0 2006.281.08:14:23.92#ibcon#*before return 0, iclass 6, count 0 2006.281.08:14:23.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:23.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.281.08:14:23.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:14:23.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:14:23.92$vc4f8/vabw=wide 2006.281.08:14:23.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.281.08:14:23.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.281.08:14:23.92#ibcon#ireg 8 cls_cnt 0 2006.281.08:14:23.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:23.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:23.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:23.92#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:14:23.92#ibcon#first serial, iclass 10, count 0 2006.281.08:14:23.92#ibcon#enter sib2, iclass 10, count 0 2006.281.08:14:23.92#ibcon#flushed, iclass 10, count 0 2006.281.08:14:23.92#ibcon#about to write, iclass 10, count 0 2006.281.08:14:23.92#ibcon#wrote, iclass 10, count 0 2006.281.08:14:23.92#ibcon#about to read 3, iclass 10, count 0 2006.281.08:14:23.93#ibcon#read 3, iclass 10, count 0 2006.281.08:14:23.93#ibcon#about to read 4, iclass 10, count 0 2006.281.08:14:23.93#ibcon#read 4, iclass 10, count 0 2006.281.08:14:23.93#ibcon#about to read 5, iclass 10, count 0 2006.281.08:14:23.93#ibcon#read 5, iclass 10, count 0 2006.281.08:14:23.93#ibcon#about to read 6, iclass 10, count 0 2006.281.08:14:23.94#ibcon#read 6, iclass 10, count 0 2006.281.08:14:23.94#ibcon#end of sib2, iclass 10, count 0 2006.281.08:14:23.94#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:14:23.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:14:23.94#ibcon#[25=BW32\r\n] 2006.281.08:14:23.94#ibcon#*before write, iclass 10, count 0 2006.281.08:14:23.94#ibcon#enter sib2, iclass 10, count 0 2006.281.08:14:23.94#ibcon#flushed, iclass 10, count 0 2006.281.08:14:23.94#ibcon#about to write, iclass 10, count 0 2006.281.08:14:23.94#ibcon#wrote, iclass 10, count 0 2006.281.08:14:23.94#ibcon#about to read 3, iclass 10, count 0 2006.281.08:14:23.97#ibcon#read 3, iclass 10, count 0 2006.281.08:14:23.97#ibcon#about to read 4, iclass 10, count 0 2006.281.08:14:23.97#ibcon#read 4, iclass 10, count 0 2006.281.08:14:23.97#ibcon#about to read 5, iclass 10, count 0 2006.281.08:14:23.97#ibcon#read 5, iclass 10, count 0 2006.281.08:14:23.97#ibcon#about to read 6, iclass 10, count 0 2006.281.08:14:23.97#ibcon#read 6, iclass 10, count 0 2006.281.08:14:23.97#ibcon#end of sib2, iclass 10, count 0 2006.281.08:14:23.97#ibcon#*after write, iclass 10, count 0 2006.281.08:14:23.97#ibcon#*before return 0, iclass 10, count 0 2006.281.08:14:23.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:23.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.281.08:14:23.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:14:23.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:14:23.97$vc4f8/vbbw=wide 2006.281.08:14:23.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:14:23.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:14:23.97#ibcon#ireg 8 cls_cnt 0 2006.281.08:14:23.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:14:24.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:14:24.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:14:24.04#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:14:24.04#ibcon#first serial, iclass 12, count 0 2006.281.08:14:24.04#ibcon#enter sib2, iclass 12, count 0 2006.281.08:14:24.04#ibcon#flushed, iclass 12, count 0 2006.281.08:14:24.04#ibcon#about to write, iclass 12, count 0 2006.281.08:14:24.04#ibcon#wrote, iclass 12, count 0 2006.281.08:14:24.04#ibcon#about to read 3, iclass 12, count 0 2006.281.08:14:24.06#ibcon#read 3, iclass 12, count 0 2006.281.08:14:24.06#ibcon#about to read 4, iclass 12, count 0 2006.281.08:14:24.06#ibcon#read 4, iclass 12, count 0 2006.281.08:14:24.06#ibcon#about to read 5, iclass 12, count 0 2006.281.08:14:24.06#ibcon#read 5, iclass 12, count 0 2006.281.08:14:24.06#ibcon#about to read 6, iclass 12, count 0 2006.281.08:14:24.06#ibcon#read 6, iclass 12, count 0 2006.281.08:14:24.06#ibcon#end of sib2, iclass 12, count 0 2006.281.08:14:24.06#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:14:24.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:14:24.06#ibcon#[27=BW32\r\n] 2006.281.08:14:24.06#ibcon#*before write, iclass 12, count 0 2006.281.08:14:24.06#ibcon#enter sib2, iclass 12, count 0 2006.281.08:14:24.06#ibcon#flushed, iclass 12, count 0 2006.281.08:14:24.06#ibcon#about to write, iclass 12, count 0 2006.281.08:14:24.06#ibcon#wrote, iclass 12, count 0 2006.281.08:14:24.06#ibcon#about to read 3, iclass 12, count 0 2006.281.08:14:24.09#ibcon#read 3, iclass 12, count 0 2006.281.08:14:24.09#ibcon#about to read 4, iclass 12, count 0 2006.281.08:14:24.09#ibcon#read 4, iclass 12, count 0 2006.281.08:14:24.09#ibcon#about to read 5, iclass 12, count 0 2006.281.08:14:24.09#ibcon#read 5, iclass 12, count 0 2006.281.08:14:24.09#ibcon#about to read 6, iclass 12, count 0 2006.281.08:14:24.09#ibcon#read 6, iclass 12, count 0 2006.281.08:14:24.09#ibcon#end of sib2, iclass 12, count 0 2006.281.08:14:24.09#ibcon#*after write, iclass 12, count 0 2006.281.08:14:24.09#ibcon#*before return 0, iclass 12, count 0 2006.281.08:14:24.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:14:24.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:14:24.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:14:24.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:14:24.09$4f8m12a/ifd4f 2006.281.08:14:24.09$ifd4f/lo= 2006.281.08:14:24.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:14:24.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:14:24.10$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:14:24.10$ifd4f/patch= 2006.281.08:14:24.10$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:14:24.10$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:14:24.10$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:14:24.10$4f8m12a/"form=m,16.000,1:2 2006.281.08:14:24.10$4f8m12a/"tpicd 2006.281.08:14:24.10$4f8m12a/echo=off 2006.281.08:14:24.10$4f8m12a/xlog=off 2006.281.08:14:24.10:!2006.281.08:14:50 2006.281.08:14:34.14#trakl#Source acquired 2006.281.08:14:35.14#flagr#flagr/antenna,acquired 2006.281.08:14:50.01:preob 2006.281.08:14:51.13/onsource/TRACKING 2006.281.08:14:51.13:!2006.281.08:15:00 2006.281.08:15:00.00:data_valid=on 2006.281.08:15:00.00:midob 2006.281.08:15:00.13/onsource/TRACKING 2006.281.08:15:00.13/wx/20.10,1001.6,52 2006.281.08:15:00.34/cable/+6.4877E-03 2006.281.08:15:01.43/va/01,07,usb,yes,33,34 2006.281.08:15:01.43/va/02,06,usb,yes,30,32 2006.281.08:15:01.43/va/03,06,usb,yes,29,28 2006.281.08:15:01.43/va/04,06,usb,yes,31,34 2006.281.08:15:01.43/va/05,07,usb,yes,30,32 2006.281.08:15:01.43/va/06,06,usb,yes,29,29 2006.281.08:15:01.43/va/07,06,usb,yes,29,29 2006.281.08:15:01.43/va/08,06,usb,yes,32,31 2006.281.08:15:01.66/valo/01,532.99,yes,locked 2006.281.08:15:01.66/valo/02,572.99,yes,locked 2006.281.08:15:01.66/valo/03,672.99,yes,locked 2006.281.08:15:01.66/valo/04,832.99,yes,locked 2006.281.08:15:01.66/valo/05,652.99,yes,locked 2006.281.08:15:01.66/valo/06,772.99,yes,locked 2006.281.08:15:01.66/valo/07,832.99,yes,locked 2006.281.08:15:01.66/valo/08,852.99,yes,locked 2006.281.08:15:02.75/vb/01,04,usb,yes,30,29 2006.281.08:15:02.75/vb/02,05,usb,yes,28,29 2006.281.08:15:02.75/vb/03,04,usb,yes,28,32 2006.281.08:15:02.75/vb/04,04,usb,yes,29,29 2006.281.08:15:02.75/vb/05,04,usb,yes,27,31 2006.281.08:15:02.75/vb/06,04,usb,yes,27,31 2006.281.08:15:02.75/vb/07,04,usb,yes,30,30 2006.281.08:15:02.75/vb/08,04,usb,yes,27,31 2006.281.08:15:02.98/vblo/01,632.99,yes,locked 2006.281.08:15:02.98/vblo/02,640.99,yes,locked 2006.281.08:15:02.98/vblo/03,656.99,yes,locked 2006.281.08:15:02.98/vblo/04,712.99,yes,locked 2006.281.08:15:02.98/vblo/05,744.99,yes,locked 2006.281.08:15:02.98/vblo/06,752.99,yes,locked 2006.281.08:15:02.98/vblo/07,734.99,yes,locked 2006.281.08:15:02.98/vblo/08,744.99,yes,locked 2006.281.08:15:03.13/vabw/8 2006.281.08:15:03.28/vbbw/8 2006.281.08:15:03.37/xfe/off,on,12.2 2006.281.08:15:03.74/ifatt/23,28,28,28 2006.281.08:15:04.07/fmout-gps/S +3.12E-07 2006.281.08:15:04.10:!2006.281.08:16:00 2006.281.08:16:00.01:data_valid=off 2006.281.08:16:00.02:postob 2006.281.08:16:00.22/cable/+6.4880E-03 2006.281.08:16:00.23/wx/20.08,1001.6,52 2006.281.08:16:01.08/fmout-gps/S +3.10E-07 2006.281.08:16:01.09:scan_name=281-0816,k06281,60 2006.281.08:16:01.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.281.08:16:01.13#flagr#flagr/antenna,new-source 2006.281.08:16:02.13:checkk5 2006.281.08:16:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:16:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:16:03.36/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:16:03.80/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:16:04.25/chk_obsdata//k5ts1/T2810815??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:16:04.68/chk_obsdata//k5ts2/T2810815??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:16:05.11/chk_obsdata//k5ts3/T2810815??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:16:05.51/chk_obsdata//k5ts4/T2810815??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:16:06.35/k5log//k5ts1_log_newline 2006.281.08:16:07.23/k5log//k5ts2_log_newline 2006.281.08:16:08.26/k5log//k5ts3_log_newline 2006.281.08:16:09.07/k5log//k5ts4_log_newline 2006.281.08:16:09.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:16:09.09:4f8m12a=2 2006.281.08:16:09.09$4f8m12a/echo=on 2006.281.08:16:09.09$4f8m12a/pcalon 2006.281.08:16:09.09$pcalon/"no phase cal control is implemented here 2006.281.08:16:09.09$4f8m12a/"tpicd=stop 2006.281.08:16:09.09$4f8m12a/vc4f8 2006.281.08:16:09.09$vc4f8/valo=1,532.99 2006.281.08:16:09.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.08:16:09.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.08:16:09.10#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:09.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:09.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:09.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:09.10#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:16:09.10#ibcon#first serial, iclass 23, count 0 2006.281.08:16:09.10#ibcon#enter sib2, iclass 23, count 0 2006.281.08:16:09.10#ibcon#flushed, iclass 23, count 0 2006.281.08:16:09.10#ibcon#about to write, iclass 23, count 0 2006.281.08:16:09.10#ibcon#wrote, iclass 23, count 0 2006.281.08:16:09.10#ibcon#about to read 3, iclass 23, count 0 2006.281.08:16:09.12#ibcon#read 3, iclass 23, count 0 2006.281.08:16:09.12#ibcon#about to read 4, iclass 23, count 0 2006.281.08:16:09.12#ibcon#read 4, iclass 23, count 0 2006.281.08:16:09.12#ibcon#about to read 5, iclass 23, count 0 2006.281.08:16:09.12#ibcon#read 5, iclass 23, count 0 2006.281.08:16:09.12#ibcon#about to read 6, iclass 23, count 0 2006.281.08:16:09.12#ibcon#read 6, iclass 23, count 0 2006.281.08:16:09.12#ibcon#end of sib2, iclass 23, count 0 2006.281.08:16:09.12#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:16:09.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:16:09.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:16:09.12#ibcon#*before write, iclass 23, count 0 2006.281.08:16:09.12#ibcon#enter sib2, iclass 23, count 0 2006.281.08:16:09.12#ibcon#flushed, iclass 23, count 0 2006.281.08:16:09.12#ibcon#about to write, iclass 23, count 0 2006.281.08:16:09.12#ibcon#wrote, iclass 23, count 0 2006.281.08:16:09.12#ibcon#about to read 3, iclass 23, count 0 2006.281.08:16:09.17#ibcon#read 3, iclass 23, count 0 2006.281.08:16:09.17#ibcon#about to read 4, iclass 23, count 0 2006.281.08:16:09.17#ibcon#read 4, iclass 23, count 0 2006.281.08:16:09.17#ibcon#about to read 5, iclass 23, count 0 2006.281.08:16:09.17#ibcon#read 5, iclass 23, count 0 2006.281.08:16:09.17#ibcon#about to read 6, iclass 23, count 0 2006.281.08:16:09.17#ibcon#read 6, iclass 23, count 0 2006.281.08:16:09.17#ibcon#end of sib2, iclass 23, count 0 2006.281.08:16:09.17#ibcon#*after write, iclass 23, count 0 2006.281.08:16:09.17#ibcon#*before return 0, iclass 23, count 0 2006.281.08:16:09.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:09.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:09.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:16:09.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:16:09.17$vc4f8/va=1,7 2006.281.08:16:09.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.08:16:09.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.08:16:09.17#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:09.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:09.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:09.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:09.17#ibcon#enter wrdev, iclass 25, count 2 2006.281.08:16:09.17#ibcon#first serial, iclass 25, count 2 2006.281.08:16:09.17#ibcon#enter sib2, iclass 25, count 2 2006.281.08:16:09.17#ibcon#flushed, iclass 25, count 2 2006.281.08:16:09.17#ibcon#about to write, iclass 25, count 2 2006.281.08:16:09.17#ibcon#wrote, iclass 25, count 2 2006.281.08:16:09.17#ibcon#about to read 3, iclass 25, count 2 2006.281.08:16:09.20#ibcon#read 3, iclass 25, count 2 2006.281.08:16:09.20#ibcon#about to read 4, iclass 25, count 2 2006.281.08:16:09.20#ibcon#read 4, iclass 25, count 2 2006.281.08:16:09.20#ibcon#about to read 5, iclass 25, count 2 2006.281.08:16:09.20#ibcon#read 5, iclass 25, count 2 2006.281.08:16:09.20#ibcon#about to read 6, iclass 25, count 2 2006.281.08:16:09.20#ibcon#read 6, iclass 25, count 2 2006.281.08:16:09.20#ibcon#end of sib2, iclass 25, count 2 2006.281.08:16:09.20#ibcon#*mode == 0, iclass 25, count 2 2006.281.08:16:09.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.08:16:09.20#ibcon#[25=AT01-07\r\n] 2006.281.08:16:09.20#ibcon#*before write, iclass 25, count 2 2006.281.08:16:09.20#ibcon#enter sib2, iclass 25, count 2 2006.281.08:16:09.20#ibcon#flushed, iclass 25, count 2 2006.281.08:16:09.20#ibcon#about to write, iclass 25, count 2 2006.281.08:16:09.20#ibcon#wrote, iclass 25, count 2 2006.281.08:16:09.20#ibcon#about to read 3, iclass 25, count 2 2006.281.08:16:09.23#ibcon#read 3, iclass 25, count 2 2006.281.08:16:09.23#ibcon#about to read 4, iclass 25, count 2 2006.281.08:16:09.23#ibcon#read 4, iclass 25, count 2 2006.281.08:16:09.23#ibcon#about to read 5, iclass 25, count 2 2006.281.08:16:09.23#ibcon#read 5, iclass 25, count 2 2006.281.08:16:09.23#ibcon#about to read 6, iclass 25, count 2 2006.281.08:16:09.23#ibcon#read 6, iclass 25, count 2 2006.281.08:16:09.23#ibcon#end of sib2, iclass 25, count 2 2006.281.08:16:09.23#ibcon#*after write, iclass 25, count 2 2006.281.08:16:09.23#ibcon#*before return 0, iclass 25, count 2 2006.281.08:16:09.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:09.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:09.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.08:16:09.23#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:09.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:09.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:09.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:09.35#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:16:09.35#ibcon#first serial, iclass 25, count 0 2006.281.08:16:09.35#ibcon#enter sib2, iclass 25, count 0 2006.281.08:16:09.35#ibcon#flushed, iclass 25, count 0 2006.281.08:16:09.35#ibcon#about to write, iclass 25, count 0 2006.281.08:16:09.35#ibcon#wrote, iclass 25, count 0 2006.281.08:16:09.35#ibcon#about to read 3, iclass 25, count 0 2006.281.08:16:09.37#ibcon#read 3, iclass 25, count 0 2006.281.08:16:09.37#ibcon#about to read 4, iclass 25, count 0 2006.281.08:16:09.37#ibcon#read 4, iclass 25, count 0 2006.281.08:16:09.37#ibcon#about to read 5, iclass 25, count 0 2006.281.08:16:09.37#ibcon#read 5, iclass 25, count 0 2006.281.08:16:09.37#ibcon#about to read 6, iclass 25, count 0 2006.281.08:16:09.37#ibcon#read 6, iclass 25, count 0 2006.281.08:16:09.37#ibcon#end of sib2, iclass 25, count 0 2006.281.08:16:09.37#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:16:09.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:16:09.37#ibcon#[25=USB\r\n] 2006.281.08:16:09.37#ibcon#*before write, iclass 25, count 0 2006.281.08:16:09.37#ibcon#enter sib2, iclass 25, count 0 2006.281.08:16:09.37#ibcon#flushed, iclass 25, count 0 2006.281.08:16:09.37#ibcon#about to write, iclass 25, count 0 2006.281.08:16:09.37#ibcon#wrote, iclass 25, count 0 2006.281.08:16:09.37#ibcon#about to read 3, iclass 25, count 0 2006.281.08:16:09.40#ibcon#read 3, iclass 25, count 0 2006.281.08:16:09.40#ibcon#about to read 4, iclass 25, count 0 2006.281.08:16:09.40#ibcon#read 4, iclass 25, count 0 2006.281.08:16:09.40#ibcon#about to read 5, iclass 25, count 0 2006.281.08:16:09.40#ibcon#read 5, iclass 25, count 0 2006.281.08:16:09.40#ibcon#about to read 6, iclass 25, count 0 2006.281.08:16:09.40#ibcon#read 6, iclass 25, count 0 2006.281.08:16:09.40#ibcon#end of sib2, iclass 25, count 0 2006.281.08:16:09.40#ibcon#*after write, iclass 25, count 0 2006.281.08:16:09.40#ibcon#*before return 0, iclass 25, count 0 2006.281.08:16:09.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:09.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:09.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:16:09.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:16:09.40$vc4f8/valo=2,572.99 2006.281.08:16:09.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.08:16:09.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.08:16:09.40#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:09.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:09.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:09.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:09.40#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:16:09.40#ibcon#first serial, iclass 27, count 0 2006.281.08:16:09.40#ibcon#enter sib2, iclass 27, count 0 2006.281.08:16:09.40#ibcon#flushed, iclass 27, count 0 2006.281.08:16:09.40#ibcon#about to write, iclass 27, count 0 2006.281.08:16:09.40#ibcon#wrote, iclass 27, count 0 2006.281.08:16:09.40#ibcon#about to read 3, iclass 27, count 0 2006.281.08:16:09.42#ibcon#read 3, iclass 27, count 0 2006.281.08:16:09.42#ibcon#about to read 4, iclass 27, count 0 2006.281.08:16:09.42#ibcon#read 4, iclass 27, count 0 2006.281.08:16:09.42#ibcon#about to read 5, iclass 27, count 0 2006.281.08:16:09.42#ibcon#read 5, iclass 27, count 0 2006.281.08:16:09.42#ibcon#about to read 6, iclass 27, count 0 2006.281.08:16:09.42#ibcon#read 6, iclass 27, count 0 2006.281.08:16:09.42#ibcon#end of sib2, iclass 27, count 0 2006.281.08:16:09.42#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:16:09.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:16:09.42#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:16:09.42#ibcon#*before write, iclass 27, count 0 2006.281.08:16:09.42#ibcon#enter sib2, iclass 27, count 0 2006.281.08:16:09.42#ibcon#flushed, iclass 27, count 0 2006.281.08:16:09.42#ibcon#about to write, iclass 27, count 0 2006.281.08:16:09.42#ibcon#wrote, iclass 27, count 0 2006.281.08:16:09.42#ibcon#about to read 3, iclass 27, count 0 2006.281.08:16:09.47#ibcon#read 3, iclass 27, count 0 2006.281.08:16:09.47#ibcon#about to read 4, iclass 27, count 0 2006.281.08:16:09.47#ibcon#read 4, iclass 27, count 0 2006.281.08:16:09.47#ibcon#about to read 5, iclass 27, count 0 2006.281.08:16:09.47#ibcon#read 5, iclass 27, count 0 2006.281.08:16:09.47#ibcon#about to read 6, iclass 27, count 0 2006.281.08:16:09.47#ibcon#read 6, iclass 27, count 0 2006.281.08:16:09.47#ibcon#end of sib2, iclass 27, count 0 2006.281.08:16:09.47#ibcon#*after write, iclass 27, count 0 2006.281.08:16:09.47#ibcon#*before return 0, iclass 27, count 0 2006.281.08:16:09.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:09.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:09.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:16:09.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:16:09.47$vc4f8/va=2,6 2006.281.08:16:09.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.08:16:09.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.08:16:09.47#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:09.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:09.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:09.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:09.51#ibcon#enter wrdev, iclass 29, count 2 2006.281.08:16:09.51#ibcon#first serial, iclass 29, count 2 2006.281.08:16:09.51#ibcon#enter sib2, iclass 29, count 2 2006.281.08:16:09.51#ibcon#flushed, iclass 29, count 2 2006.281.08:16:09.51#ibcon#about to write, iclass 29, count 2 2006.281.08:16:09.51#ibcon#wrote, iclass 29, count 2 2006.281.08:16:09.51#ibcon#about to read 3, iclass 29, count 2 2006.281.08:16:09.53#ibcon#read 3, iclass 29, count 2 2006.281.08:16:09.53#ibcon#about to read 4, iclass 29, count 2 2006.281.08:16:09.53#ibcon#read 4, iclass 29, count 2 2006.281.08:16:09.53#ibcon#about to read 5, iclass 29, count 2 2006.281.08:16:09.53#ibcon#read 5, iclass 29, count 2 2006.281.08:16:09.53#ibcon#about to read 6, iclass 29, count 2 2006.281.08:16:09.53#ibcon#read 6, iclass 29, count 2 2006.281.08:16:09.53#ibcon#end of sib2, iclass 29, count 2 2006.281.08:16:09.53#ibcon#*mode == 0, iclass 29, count 2 2006.281.08:16:09.53#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.08:16:09.53#ibcon#[25=AT02-06\r\n] 2006.281.08:16:09.53#ibcon#*before write, iclass 29, count 2 2006.281.08:16:09.53#ibcon#enter sib2, iclass 29, count 2 2006.281.08:16:09.53#ibcon#flushed, iclass 29, count 2 2006.281.08:16:09.53#ibcon#about to write, iclass 29, count 2 2006.281.08:16:09.53#ibcon#wrote, iclass 29, count 2 2006.281.08:16:09.53#ibcon#about to read 3, iclass 29, count 2 2006.281.08:16:09.56#ibcon#read 3, iclass 29, count 2 2006.281.08:16:09.56#ibcon#about to read 4, iclass 29, count 2 2006.281.08:16:09.56#ibcon#read 4, iclass 29, count 2 2006.281.08:16:09.56#ibcon#about to read 5, iclass 29, count 2 2006.281.08:16:09.56#ibcon#read 5, iclass 29, count 2 2006.281.08:16:09.56#ibcon#about to read 6, iclass 29, count 2 2006.281.08:16:09.56#ibcon#read 6, iclass 29, count 2 2006.281.08:16:09.56#ibcon#end of sib2, iclass 29, count 2 2006.281.08:16:09.56#ibcon#*after write, iclass 29, count 2 2006.281.08:16:09.56#ibcon#*before return 0, iclass 29, count 2 2006.281.08:16:09.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:09.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:09.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.08:16:09.56#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:09.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:09.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:09.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:09.68#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:16:09.68#ibcon#first serial, iclass 29, count 0 2006.281.08:16:09.68#ibcon#enter sib2, iclass 29, count 0 2006.281.08:16:09.68#ibcon#flushed, iclass 29, count 0 2006.281.08:16:09.68#ibcon#about to write, iclass 29, count 0 2006.281.08:16:09.68#ibcon#wrote, iclass 29, count 0 2006.281.08:16:09.68#ibcon#about to read 3, iclass 29, count 0 2006.281.08:16:09.70#ibcon#read 3, iclass 29, count 0 2006.281.08:16:09.70#ibcon#about to read 4, iclass 29, count 0 2006.281.08:16:09.70#ibcon#read 4, iclass 29, count 0 2006.281.08:16:09.70#ibcon#about to read 5, iclass 29, count 0 2006.281.08:16:09.70#ibcon#read 5, iclass 29, count 0 2006.281.08:16:09.70#ibcon#about to read 6, iclass 29, count 0 2006.281.08:16:09.70#ibcon#read 6, iclass 29, count 0 2006.281.08:16:09.70#ibcon#end of sib2, iclass 29, count 0 2006.281.08:16:09.70#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:16:09.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:16:09.70#ibcon#[25=USB\r\n] 2006.281.08:16:09.70#ibcon#*before write, iclass 29, count 0 2006.281.08:16:09.70#ibcon#enter sib2, iclass 29, count 0 2006.281.08:16:09.70#ibcon#flushed, iclass 29, count 0 2006.281.08:16:09.70#ibcon#about to write, iclass 29, count 0 2006.281.08:16:09.70#ibcon#wrote, iclass 29, count 0 2006.281.08:16:09.70#ibcon#about to read 3, iclass 29, count 0 2006.281.08:16:09.73#ibcon#read 3, iclass 29, count 0 2006.281.08:16:09.73#ibcon#about to read 4, iclass 29, count 0 2006.281.08:16:09.73#ibcon#read 4, iclass 29, count 0 2006.281.08:16:09.73#ibcon#about to read 5, iclass 29, count 0 2006.281.08:16:09.73#ibcon#read 5, iclass 29, count 0 2006.281.08:16:09.73#ibcon#about to read 6, iclass 29, count 0 2006.281.08:16:09.73#ibcon#read 6, iclass 29, count 0 2006.281.08:16:09.73#ibcon#end of sib2, iclass 29, count 0 2006.281.08:16:09.73#ibcon#*after write, iclass 29, count 0 2006.281.08:16:09.73#ibcon#*before return 0, iclass 29, count 0 2006.281.08:16:09.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:09.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:09.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:16:09.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:16:09.73$vc4f8/valo=3,672.99 2006.281.08:16:09.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:16:09.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:16:09.73#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:09.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:09.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:09.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:09.73#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:16:09.73#ibcon#first serial, iclass 31, count 0 2006.281.08:16:09.73#ibcon#enter sib2, iclass 31, count 0 2006.281.08:16:09.73#ibcon#flushed, iclass 31, count 0 2006.281.08:16:09.73#ibcon#about to write, iclass 31, count 0 2006.281.08:16:09.73#ibcon#wrote, iclass 31, count 0 2006.281.08:16:09.73#ibcon#about to read 3, iclass 31, count 0 2006.281.08:16:09.75#ibcon#read 3, iclass 31, count 0 2006.281.08:16:09.75#ibcon#about to read 4, iclass 31, count 0 2006.281.08:16:09.75#ibcon#read 4, iclass 31, count 0 2006.281.08:16:09.75#ibcon#about to read 5, iclass 31, count 0 2006.281.08:16:09.75#ibcon#read 5, iclass 31, count 0 2006.281.08:16:09.75#ibcon#about to read 6, iclass 31, count 0 2006.281.08:16:09.75#ibcon#read 6, iclass 31, count 0 2006.281.08:16:09.75#ibcon#end of sib2, iclass 31, count 0 2006.281.08:16:09.75#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:16:09.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:16:09.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:16:09.75#ibcon#*before write, iclass 31, count 0 2006.281.08:16:09.75#ibcon#enter sib2, iclass 31, count 0 2006.281.08:16:09.75#ibcon#flushed, iclass 31, count 0 2006.281.08:16:09.75#ibcon#about to write, iclass 31, count 0 2006.281.08:16:09.75#ibcon#wrote, iclass 31, count 0 2006.281.08:16:09.75#ibcon#about to read 3, iclass 31, count 0 2006.281.08:16:09.80#ibcon#read 3, iclass 31, count 0 2006.281.08:16:09.80#ibcon#about to read 4, iclass 31, count 0 2006.281.08:16:09.80#ibcon#read 4, iclass 31, count 0 2006.281.08:16:09.80#ibcon#about to read 5, iclass 31, count 0 2006.281.08:16:09.80#ibcon#read 5, iclass 31, count 0 2006.281.08:16:09.80#ibcon#about to read 6, iclass 31, count 0 2006.281.08:16:09.80#ibcon#read 6, iclass 31, count 0 2006.281.08:16:09.80#ibcon#end of sib2, iclass 31, count 0 2006.281.08:16:09.80#ibcon#*after write, iclass 31, count 0 2006.281.08:16:09.80#ibcon#*before return 0, iclass 31, count 0 2006.281.08:16:09.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:09.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:09.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:16:09.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:16:09.80$vc4f8/va=3,6 2006.281.08:16:09.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.08:16:09.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.08:16:09.81#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:09.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:09.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:09.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:09.85#ibcon#enter wrdev, iclass 33, count 2 2006.281.08:16:09.85#ibcon#first serial, iclass 33, count 2 2006.281.08:16:09.85#ibcon#enter sib2, iclass 33, count 2 2006.281.08:16:09.85#ibcon#flushed, iclass 33, count 2 2006.281.08:16:09.85#ibcon#about to write, iclass 33, count 2 2006.281.08:16:09.85#ibcon#wrote, iclass 33, count 2 2006.281.08:16:09.85#ibcon#about to read 3, iclass 33, count 2 2006.281.08:16:09.87#ibcon#read 3, iclass 33, count 2 2006.281.08:16:09.87#ibcon#about to read 4, iclass 33, count 2 2006.281.08:16:09.87#ibcon#read 4, iclass 33, count 2 2006.281.08:16:09.87#ibcon#about to read 5, iclass 33, count 2 2006.281.08:16:09.87#ibcon#read 5, iclass 33, count 2 2006.281.08:16:09.87#ibcon#about to read 6, iclass 33, count 2 2006.281.08:16:09.87#ibcon#read 6, iclass 33, count 2 2006.281.08:16:09.87#ibcon#end of sib2, iclass 33, count 2 2006.281.08:16:09.87#ibcon#*mode == 0, iclass 33, count 2 2006.281.08:16:09.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.08:16:09.87#ibcon#[25=AT03-06\r\n] 2006.281.08:16:09.87#ibcon#*before write, iclass 33, count 2 2006.281.08:16:09.87#ibcon#enter sib2, iclass 33, count 2 2006.281.08:16:09.87#ibcon#flushed, iclass 33, count 2 2006.281.08:16:09.87#ibcon#about to write, iclass 33, count 2 2006.281.08:16:09.87#ibcon#wrote, iclass 33, count 2 2006.281.08:16:09.87#ibcon#about to read 3, iclass 33, count 2 2006.281.08:16:09.89#ibcon#read 3, iclass 33, count 2 2006.281.08:16:09.89#ibcon#about to read 4, iclass 33, count 2 2006.281.08:16:09.89#ibcon#read 4, iclass 33, count 2 2006.281.08:16:09.89#ibcon#about to read 5, iclass 33, count 2 2006.281.08:16:09.89#ibcon#read 5, iclass 33, count 2 2006.281.08:16:09.89#ibcon#about to read 6, iclass 33, count 2 2006.281.08:16:09.89#ibcon#read 6, iclass 33, count 2 2006.281.08:16:09.89#ibcon#end of sib2, iclass 33, count 2 2006.281.08:16:09.89#ibcon#*after write, iclass 33, count 2 2006.281.08:16:09.89#ibcon#*before return 0, iclass 33, count 2 2006.281.08:16:09.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:09.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:09.89#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.08:16:09.89#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:09.89#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:10.01#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:10.01#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:10.01#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:16:10.01#ibcon#first serial, iclass 33, count 0 2006.281.08:16:10.01#ibcon#enter sib2, iclass 33, count 0 2006.281.08:16:10.01#ibcon#flushed, iclass 33, count 0 2006.281.08:16:10.01#ibcon#about to write, iclass 33, count 0 2006.281.08:16:10.01#ibcon#wrote, iclass 33, count 0 2006.281.08:16:10.01#ibcon#about to read 3, iclass 33, count 0 2006.281.08:16:10.03#ibcon#read 3, iclass 33, count 0 2006.281.08:16:10.03#ibcon#about to read 4, iclass 33, count 0 2006.281.08:16:10.03#ibcon#read 4, iclass 33, count 0 2006.281.08:16:10.03#ibcon#about to read 5, iclass 33, count 0 2006.281.08:16:10.03#ibcon#read 5, iclass 33, count 0 2006.281.08:16:10.03#ibcon#about to read 6, iclass 33, count 0 2006.281.08:16:10.03#ibcon#read 6, iclass 33, count 0 2006.281.08:16:10.03#ibcon#end of sib2, iclass 33, count 0 2006.281.08:16:10.03#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:16:10.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:16:10.03#ibcon#[25=USB\r\n] 2006.281.08:16:10.03#ibcon#*before write, iclass 33, count 0 2006.281.08:16:10.03#ibcon#enter sib2, iclass 33, count 0 2006.281.08:16:10.03#ibcon#flushed, iclass 33, count 0 2006.281.08:16:10.03#ibcon#about to write, iclass 33, count 0 2006.281.08:16:10.03#ibcon#wrote, iclass 33, count 0 2006.281.08:16:10.03#ibcon#about to read 3, iclass 33, count 0 2006.281.08:16:10.06#ibcon#read 3, iclass 33, count 0 2006.281.08:16:10.06#ibcon#about to read 4, iclass 33, count 0 2006.281.08:16:10.06#ibcon#read 4, iclass 33, count 0 2006.281.08:16:10.06#ibcon#about to read 5, iclass 33, count 0 2006.281.08:16:10.06#ibcon#read 5, iclass 33, count 0 2006.281.08:16:10.06#ibcon#about to read 6, iclass 33, count 0 2006.281.08:16:10.06#ibcon#read 6, iclass 33, count 0 2006.281.08:16:10.06#ibcon#end of sib2, iclass 33, count 0 2006.281.08:16:10.06#ibcon#*after write, iclass 33, count 0 2006.281.08:16:10.06#ibcon#*before return 0, iclass 33, count 0 2006.281.08:16:10.06#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:10.06#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:10.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:16:10.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:16:10.06$vc4f8/valo=4,832.99 2006.281.08:16:10.06#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.08:16:10.06#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.08:16:10.06#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:10.06#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:10.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:10.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:10.06#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:16:10.06#ibcon#first serial, iclass 35, count 0 2006.281.08:16:10.06#ibcon#enter sib2, iclass 35, count 0 2006.281.08:16:10.06#ibcon#flushed, iclass 35, count 0 2006.281.08:16:10.06#ibcon#about to write, iclass 35, count 0 2006.281.08:16:10.06#ibcon#wrote, iclass 35, count 0 2006.281.08:16:10.06#ibcon#about to read 3, iclass 35, count 0 2006.281.08:16:10.08#ibcon#read 3, iclass 35, count 0 2006.281.08:16:10.08#ibcon#about to read 4, iclass 35, count 0 2006.281.08:16:10.08#ibcon#read 4, iclass 35, count 0 2006.281.08:16:10.08#ibcon#about to read 5, iclass 35, count 0 2006.281.08:16:10.08#ibcon#read 5, iclass 35, count 0 2006.281.08:16:10.08#ibcon#about to read 6, iclass 35, count 0 2006.281.08:16:10.08#ibcon#read 6, iclass 35, count 0 2006.281.08:16:10.08#ibcon#end of sib2, iclass 35, count 0 2006.281.08:16:10.08#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:16:10.08#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:16:10.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:16:10.10#ibcon#*before write, iclass 35, count 0 2006.281.08:16:10.10#ibcon#enter sib2, iclass 35, count 0 2006.281.08:16:10.10#ibcon#flushed, iclass 35, count 0 2006.281.08:16:10.10#ibcon#about to write, iclass 35, count 0 2006.281.08:16:10.10#ibcon#wrote, iclass 35, count 0 2006.281.08:16:10.10#ibcon#about to read 3, iclass 35, count 0 2006.281.08:16:10.14#ibcon#read 3, iclass 35, count 0 2006.281.08:16:10.14#ibcon#about to read 4, iclass 35, count 0 2006.281.08:16:10.14#ibcon#read 4, iclass 35, count 0 2006.281.08:16:10.14#ibcon#about to read 5, iclass 35, count 0 2006.281.08:16:10.14#ibcon#read 5, iclass 35, count 0 2006.281.08:16:10.14#ibcon#about to read 6, iclass 35, count 0 2006.281.08:16:10.14#ibcon#read 6, iclass 35, count 0 2006.281.08:16:10.14#ibcon#end of sib2, iclass 35, count 0 2006.281.08:16:10.14#ibcon#*after write, iclass 35, count 0 2006.281.08:16:10.14#ibcon#*before return 0, iclass 35, count 0 2006.281.08:16:10.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:10.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:10.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:16:10.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:16:10.14$vc4f8/va=4,6 2006.281.08:16:10.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.08:16:10.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.08:16:10.14#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:10.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:10.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:10.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:10.18#ibcon#enter wrdev, iclass 37, count 2 2006.281.08:16:10.18#ibcon#first serial, iclass 37, count 2 2006.281.08:16:10.18#ibcon#enter sib2, iclass 37, count 2 2006.281.08:16:10.18#ibcon#flushed, iclass 37, count 2 2006.281.08:16:10.18#ibcon#about to write, iclass 37, count 2 2006.281.08:16:10.18#ibcon#wrote, iclass 37, count 2 2006.281.08:16:10.18#ibcon#about to read 3, iclass 37, count 2 2006.281.08:16:10.20#ibcon#read 3, iclass 37, count 2 2006.281.08:16:10.20#ibcon#about to read 4, iclass 37, count 2 2006.281.08:16:10.20#ibcon#read 4, iclass 37, count 2 2006.281.08:16:10.20#ibcon#about to read 5, iclass 37, count 2 2006.281.08:16:10.20#ibcon#read 5, iclass 37, count 2 2006.281.08:16:10.20#ibcon#about to read 6, iclass 37, count 2 2006.281.08:16:10.20#ibcon#read 6, iclass 37, count 2 2006.281.08:16:10.20#ibcon#end of sib2, iclass 37, count 2 2006.281.08:16:10.20#ibcon#*mode == 0, iclass 37, count 2 2006.281.08:16:10.20#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.08:16:10.20#ibcon#[25=AT04-06\r\n] 2006.281.08:16:10.20#ibcon#*before write, iclass 37, count 2 2006.281.08:16:10.20#ibcon#enter sib2, iclass 37, count 2 2006.281.08:16:10.20#ibcon#flushed, iclass 37, count 2 2006.281.08:16:10.20#ibcon#about to write, iclass 37, count 2 2006.281.08:16:10.20#ibcon#wrote, iclass 37, count 2 2006.281.08:16:10.20#ibcon#about to read 3, iclass 37, count 2 2006.281.08:16:10.23#ibcon#read 3, iclass 37, count 2 2006.281.08:16:10.23#ibcon#about to read 4, iclass 37, count 2 2006.281.08:16:10.23#ibcon#read 4, iclass 37, count 2 2006.281.08:16:10.23#ibcon#about to read 5, iclass 37, count 2 2006.281.08:16:10.23#ibcon#read 5, iclass 37, count 2 2006.281.08:16:10.23#ibcon#about to read 6, iclass 37, count 2 2006.281.08:16:10.23#ibcon#read 6, iclass 37, count 2 2006.281.08:16:10.23#ibcon#end of sib2, iclass 37, count 2 2006.281.08:16:10.23#ibcon#*after write, iclass 37, count 2 2006.281.08:16:10.23#ibcon#*before return 0, iclass 37, count 2 2006.281.08:16:10.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:10.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:10.23#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.08:16:10.23#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:10.23#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:10.35#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:10.35#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:10.35#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:16:10.35#ibcon#first serial, iclass 37, count 0 2006.281.08:16:10.35#ibcon#enter sib2, iclass 37, count 0 2006.281.08:16:10.35#ibcon#flushed, iclass 37, count 0 2006.281.08:16:10.35#ibcon#about to write, iclass 37, count 0 2006.281.08:16:10.35#ibcon#wrote, iclass 37, count 0 2006.281.08:16:10.35#ibcon#about to read 3, iclass 37, count 0 2006.281.08:16:10.37#ibcon#read 3, iclass 37, count 0 2006.281.08:16:10.37#ibcon#about to read 4, iclass 37, count 0 2006.281.08:16:10.37#ibcon#read 4, iclass 37, count 0 2006.281.08:16:10.37#ibcon#about to read 5, iclass 37, count 0 2006.281.08:16:10.37#ibcon#read 5, iclass 37, count 0 2006.281.08:16:10.37#ibcon#about to read 6, iclass 37, count 0 2006.281.08:16:10.37#ibcon#read 6, iclass 37, count 0 2006.281.08:16:10.37#ibcon#end of sib2, iclass 37, count 0 2006.281.08:16:10.37#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:16:10.37#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:16:10.37#ibcon#[25=USB\r\n] 2006.281.08:16:10.37#ibcon#*before write, iclass 37, count 0 2006.281.08:16:10.37#ibcon#enter sib2, iclass 37, count 0 2006.281.08:16:10.37#ibcon#flushed, iclass 37, count 0 2006.281.08:16:10.37#ibcon#about to write, iclass 37, count 0 2006.281.08:16:10.37#ibcon#wrote, iclass 37, count 0 2006.281.08:16:10.37#ibcon#about to read 3, iclass 37, count 0 2006.281.08:16:10.40#ibcon#read 3, iclass 37, count 0 2006.281.08:16:10.40#ibcon#about to read 4, iclass 37, count 0 2006.281.08:16:10.40#ibcon#read 4, iclass 37, count 0 2006.281.08:16:10.40#ibcon#about to read 5, iclass 37, count 0 2006.281.08:16:10.40#ibcon#read 5, iclass 37, count 0 2006.281.08:16:10.40#ibcon#about to read 6, iclass 37, count 0 2006.281.08:16:10.40#ibcon#read 6, iclass 37, count 0 2006.281.08:16:10.40#ibcon#end of sib2, iclass 37, count 0 2006.281.08:16:10.40#ibcon#*after write, iclass 37, count 0 2006.281.08:16:10.40#ibcon#*before return 0, iclass 37, count 0 2006.281.08:16:10.40#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:10.40#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:10.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:16:10.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:16:10.40$vc4f8/valo=5,652.99 2006.281.08:16:10.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:16:10.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:16:10.40#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:10.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:10.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:10.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:10.40#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:16:10.40#ibcon#first serial, iclass 39, count 0 2006.281.08:16:10.40#ibcon#enter sib2, iclass 39, count 0 2006.281.08:16:10.40#ibcon#flushed, iclass 39, count 0 2006.281.08:16:10.40#ibcon#about to write, iclass 39, count 0 2006.281.08:16:10.40#ibcon#wrote, iclass 39, count 0 2006.281.08:16:10.40#ibcon#about to read 3, iclass 39, count 0 2006.281.08:16:10.42#ibcon#read 3, iclass 39, count 0 2006.281.08:16:10.42#ibcon#about to read 4, iclass 39, count 0 2006.281.08:16:10.42#ibcon#read 4, iclass 39, count 0 2006.281.08:16:10.42#ibcon#about to read 5, iclass 39, count 0 2006.281.08:16:10.42#ibcon#read 5, iclass 39, count 0 2006.281.08:16:10.42#ibcon#about to read 6, iclass 39, count 0 2006.281.08:16:10.42#ibcon#read 6, iclass 39, count 0 2006.281.08:16:10.42#ibcon#end of sib2, iclass 39, count 0 2006.281.08:16:10.42#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:16:10.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:16:10.42#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:16:10.42#ibcon#*before write, iclass 39, count 0 2006.281.08:16:10.42#ibcon#enter sib2, iclass 39, count 0 2006.281.08:16:10.42#ibcon#flushed, iclass 39, count 0 2006.281.08:16:10.42#ibcon#about to write, iclass 39, count 0 2006.281.08:16:10.42#ibcon#wrote, iclass 39, count 0 2006.281.08:16:10.42#ibcon#about to read 3, iclass 39, count 0 2006.281.08:16:10.47#ibcon#read 3, iclass 39, count 0 2006.281.08:16:10.47#ibcon#about to read 4, iclass 39, count 0 2006.281.08:16:10.47#ibcon#read 4, iclass 39, count 0 2006.281.08:16:10.47#ibcon#about to read 5, iclass 39, count 0 2006.281.08:16:10.47#ibcon#read 5, iclass 39, count 0 2006.281.08:16:10.47#ibcon#about to read 6, iclass 39, count 0 2006.281.08:16:10.47#ibcon#read 6, iclass 39, count 0 2006.281.08:16:10.47#ibcon#end of sib2, iclass 39, count 0 2006.281.08:16:10.47#ibcon#*after write, iclass 39, count 0 2006.281.08:16:10.47#ibcon#*before return 0, iclass 39, count 0 2006.281.08:16:10.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:10.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:10.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:16:10.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:16:10.47$vc4f8/va=5,7 2006.281.08:16:10.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.08:16:10.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.08:16:10.47#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:10.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:10.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:10.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:10.51#ibcon#enter wrdev, iclass 3, count 2 2006.281.08:16:10.51#ibcon#first serial, iclass 3, count 2 2006.281.08:16:10.51#ibcon#enter sib2, iclass 3, count 2 2006.281.08:16:10.51#ibcon#flushed, iclass 3, count 2 2006.281.08:16:10.51#ibcon#about to write, iclass 3, count 2 2006.281.08:16:10.51#ibcon#wrote, iclass 3, count 2 2006.281.08:16:10.51#ibcon#about to read 3, iclass 3, count 2 2006.281.08:16:10.53#ibcon#read 3, iclass 3, count 2 2006.281.08:16:10.53#ibcon#about to read 4, iclass 3, count 2 2006.281.08:16:10.53#ibcon#read 4, iclass 3, count 2 2006.281.08:16:10.53#ibcon#about to read 5, iclass 3, count 2 2006.281.08:16:10.53#ibcon#read 5, iclass 3, count 2 2006.281.08:16:10.53#ibcon#about to read 6, iclass 3, count 2 2006.281.08:16:10.53#ibcon#read 6, iclass 3, count 2 2006.281.08:16:10.53#ibcon#end of sib2, iclass 3, count 2 2006.281.08:16:10.53#ibcon#*mode == 0, iclass 3, count 2 2006.281.08:16:10.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.08:16:10.53#ibcon#[25=AT05-07\r\n] 2006.281.08:16:10.53#ibcon#*before write, iclass 3, count 2 2006.281.08:16:10.53#ibcon#enter sib2, iclass 3, count 2 2006.281.08:16:10.53#ibcon#flushed, iclass 3, count 2 2006.281.08:16:10.53#ibcon#about to write, iclass 3, count 2 2006.281.08:16:10.53#ibcon#wrote, iclass 3, count 2 2006.281.08:16:10.53#ibcon#about to read 3, iclass 3, count 2 2006.281.08:16:10.56#ibcon#read 3, iclass 3, count 2 2006.281.08:16:10.56#ibcon#about to read 4, iclass 3, count 2 2006.281.08:16:10.56#ibcon#read 4, iclass 3, count 2 2006.281.08:16:10.56#ibcon#about to read 5, iclass 3, count 2 2006.281.08:16:10.56#ibcon#read 5, iclass 3, count 2 2006.281.08:16:10.56#ibcon#about to read 6, iclass 3, count 2 2006.281.08:16:10.56#ibcon#read 6, iclass 3, count 2 2006.281.08:16:10.56#ibcon#end of sib2, iclass 3, count 2 2006.281.08:16:10.56#ibcon#*after write, iclass 3, count 2 2006.281.08:16:10.56#ibcon#*before return 0, iclass 3, count 2 2006.281.08:16:10.56#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:10.56#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:10.56#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.08:16:10.56#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:10.56#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:10.68#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:10.68#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:10.68#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:16:10.68#ibcon#first serial, iclass 3, count 0 2006.281.08:16:10.68#ibcon#enter sib2, iclass 3, count 0 2006.281.08:16:10.68#ibcon#flushed, iclass 3, count 0 2006.281.08:16:10.68#ibcon#about to write, iclass 3, count 0 2006.281.08:16:10.68#ibcon#wrote, iclass 3, count 0 2006.281.08:16:10.68#ibcon#about to read 3, iclass 3, count 0 2006.281.08:16:10.70#ibcon#read 3, iclass 3, count 0 2006.281.08:16:10.70#ibcon#about to read 4, iclass 3, count 0 2006.281.08:16:10.70#ibcon#read 4, iclass 3, count 0 2006.281.08:16:10.70#ibcon#about to read 5, iclass 3, count 0 2006.281.08:16:10.70#ibcon#read 5, iclass 3, count 0 2006.281.08:16:10.70#ibcon#about to read 6, iclass 3, count 0 2006.281.08:16:10.70#ibcon#read 6, iclass 3, count 0 2006.281.08:16:10.70#ibcon#end of sib2, iclass 3, count 0 2006.281.08:16:10.70#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:16:10.70#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:16:10.70#ibcon#[25=USB\r\n] 2006.281.08:16:10.70#ibcon#*before write, iclass 3, count 0 2006.281.08:16:10.70#ibcon#enter sib2, iclass 3, count 0 2006.281.08:16:10.70#ibcon#flushed, iclass 3, count 0 2006.281.08:16:10.70#ibcon#about to write, iclass 3, count 0 2006.281.08:16:10.70#ibcon#wrote, iclass 3, count 0 2006.281.08:16:10.70#ibcon#about to read 3, iclass 3, count 0 2006.281.08:16:10.73#ibcon#read 3, iclass 3, count 0 2006.281.08:16:10.73#ibcon#about to read 4, iclass 3, count 0 2006.281.08:16:10.73#ibcon#read 4, iclass 3, count 0 2006.281.08:16:10.73#ibcon#about to read 5, iclass 3, count 0 2006.281.08:16:10.73#ibcon#read 5, iclass 3, count 0 2006.281.08:16:10.73#ibcon#about to read 6, iclass 3, count 0 2006.281.08:16:10.73#ibcon#read 6, iclass 3, count 0 2006.281.08:16:10.73#ibcon#end of sib2, iclass 3, count 0 2006.281.08:16:10.73#ibcon#*after write, iclass 3, count 0 2006.281.08:16:10.73#ibcon#*before return 0, iclass 3, count 0 2006.281.08:16:10.73#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:10.73#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:10.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:16:10.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:16:10.73$vc4f8/valo=6,772.99 2006.281.08:16:10.73#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.08:16:10.73#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.08:16:10.73#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:10.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:10.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:10.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:10.73#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:16:10.73#ibcon#first serial, iclass 5, count 0 2006.281.08:16:10.73#ibcon#enter sib2, iclass 5, count 0 2006.281.08:16:10.73#ibcon#flushed, iclass 5, count 0 2006.281.08:16:10.73#ibcon#about to write, iclass 5, count 0 2006.281.08:16:10.73#ibcon#wrote, iclass 5, count 0 2006.281.08:16:10.73#ibcon#about to read 3, iclass 5, count 0 2006.281.08:16:10.75#ibcon#read 3, iclass 5, count 0 2006.281.08:16:10.75#ibcon#about to read 4, iclass 5, count 0 2006.281.08:16:10.75#ibcon#read 4, iclass 5, count 0 2006.281.08:16:10.75#ibcon#about to read 5, iclass 5, count 0 2006.281.08:16:10.75#ibcon#read 5, iclass 5, count 0 2006.281.08:16:10.75#ibcon#about to read 6, iclass 5, count 0 2006.281.08:16:10.75#ibcon#read 6, iclass 5, count 0 2006.281.08:16:10.75#ibcon#end of sib2, iclass 5, count 0 2006.281.08:16:10.75#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:16:10.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:16:10.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:16:10.75#ibcon#*before write, iclass 5, count 0 2006.281.08:16:10.75#ibcon#enter sib2, iclass 5, count 0 2006.281.08:16:10.75#ibcon#flushed, iclass 5, count 0 2006.281.08:16:10.75#ibcon#about to write, iclass 5, count 0 2006.281.08:16:10.75#ibcon#wrote, iclass 5, count 0 2006.281.08:16:10.75#ibcon#about to read 3, iclass 5, count 0 2006.281.08:16:10.79#ibcon#read 3, iclass 5, count 0 2006.281.08:16:10.79#ibcon#about to read 4, iclass 5, count 0 2006.281.08:16:10.79#ibcon#read 4, iclass 5, count 0 2006.281.08:16:10.79#ibcon#about to read 5, iclass 5, count 0 2006.281.08:16:10.79#ibcon#read 5, iclass 5, count 0 2006.281.08:16:10.79#ibcon#about to read 6, iclass 5, count 0 2006.281.08:16:10.79#ibcon#read 6, iclass 5, count 0 2006.281.08:16:10.79#ibcon#end of sib2, iclass 5, count 0 2006.281.08:16:10.79#ibcon#*after write, iclass 5, count 0 2006.281.08:16:10.79#ibcon#*before return 0, iclass 5, count 0 2006.281.08:16:10.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:10.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:10.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:16:10.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:16:10.79$vc4f8/va=6,6 2006.281.08:16:10.81#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.08:16:10.81#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.08:16:10.81#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:10.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:10.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:10.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:10.84#ibcon#enter wrdev, iclass 7, count 2 2006.281.08:16:10.84#ibcon#first serial, iclass 7, count 2 2006.281.08:16:10.84#ibcon#enter sib2, iclass 7, count 2 2006.281.08:16:10.84#ibcon#flushed, iclass 7, count 2 2006.281.08:16:10.84#ibcon#about to write, iclass 7, count 2 2006.281.08:16:10.84#ibcon#wrote, iclass 7, count 2 2006.281.08:16:10.84#ibcon#about to read 3, iclass 7, count 2 2006.281.08:16:10.87#ibcon#read 3, iclass 7, count 2 2006.281.08:16:10.87#ibcon#about to read 4, iclass 7, count 2 2006.281.08:16:10.87#ibcon#read 4, iclass 7, count 2 2006.281.08:16:10.87#ibcon#about to read 5, iclass 7, count 2 2006.281.08:16:10.87#ibcon#read 5, iclass 7, count 2 2006.281.08:16:10.87#ibcon#about to read 6, iclass 7, count 2 2006.281.08:16:10.87#ibcon#read 6, iclass 7, count 2 2006.281.08:16:10.87#ibcon#end of sib2, iclass 7, count 2 2006.281.08:16:10.87#ibcon#*mode == 0, iclass 7, count 2 2006.281.08:16:10.87#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.08:16:10.87#ibcon#[25=AT06-06\r\n] 2006.281.08:16:10.87#ibcon#*before write, iclass 7, count 2 2006.281.08:16:10.87#ibcon#enter sib2, iclass 7, count 2 2006.281.08:16:10.87#ibcon#flushed, iclass 7, count 2 2006.281.08:16:10.87#ibcon#about to write, iclass 7, count 2 2006.281.08:16:10.87#ibcon#wrote, iclass 7, count 2 2006.281.08:16:10.87#ibcon#about to read 3, iclass 7, count 2 2006.281.08:16:10.89#ibcon#read 3, iclass 7, count 2 2006.281.08:16:10.89#ibcon#about to read 4, iclass 7, count 2 2006.281.08:16:10.89#ibcon#read 4, iclass 7, count 2 2006.281.08:16:10.89#ibcon#about to read 5, iclass 7, count 2 2006.281.08:16:10.89#ibcon#read 5, iclass 7, count 2 2006.281.08:16:10.89#ibcon#about to read 6, iclass 7, count 2 2006.281.08:16:10.89#ibcon#read 6, iclass 7, count 2 2006.281.08:16:10.89#ibcon#end of sib2, iclass 7, count 2 2006.281.08:16:10.89#ibcon#*after write, iclass 7, count 2 2006.281.08:16:10.89#ibcon#*before return 0, iclass 7, count 2 2006.281.08:16:10.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:10.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:10.89#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.08:16:10.89#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:10.89#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:16:11.01#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:16:11.01#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:16:11.01#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:16:11.01#ibcon#first serial, iclass 7, count 0 2006.281.08:16:11.01#ibcon#enter sib2, iclass 7, count 0 2006.281.08:16:11.01#ibcon#flushed, iclass 7, count 0 2006.281.08:16:11.01#ibcon#about to write, iclass 7, count 0 2006.281.08:16:11.01#ibcon#wrote, iclass 7, count 0 2006.281.08:16:11.01#ibcon#about to read 3, iclass 7, count 0 2006.281.08:16:11.03#ibcon#read 3, iclass 7, count 0 2006.281.08:16:11.03#ibcon#about to read 4, iclass 7, count 0 2006.281.08:16:11.03#ibcon#read 4, iclass 7, count 0 2006.281.08:16:11.03#ibcon#about to read 5, iclass 7, count 0 2006.281.08:16:11.03#ibcon#read 5, iclass 7, count 0 2006.281.08:16:11.03#ibcon#about to read 6, iclass 7, count 0 2006.281.08:16:11.03#ibcon#read 6, iclass 7, count 0 2006.281.08:16:11.03#ibcon#end of sib2, iclass 7, count 0 2006.281.08:16:11.03#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:16:11.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:16:11.03#ibcon#[25=USB\r\n] 2006.281.08:16:11.03#ibcon#*before write, iclass 7, count 0 2006.281.08:16:11.03#ibcon#enter sib2, iclass 7, count 0 2006.281.08:16:11.03#ibcon#flushed, iclass 7, count 0 2006.281.08:16:11.03#ibcon#about to write, iclass 7, count 0 2006.281.08:16:11.03#ibcon#wrote, iclass 7, count 0 2006.281.08:16:11.03#ibcon#about to read 3, iclass 7, count 0 2006.281.08:16:11.07#ibcon#read 3, iclass 7, count 0 2006.281.08:16:11.07#ibcon#about to read 4, iclass 7, count 0 2006.281.08:16:11.07#ibcon#read 4, iclass 7, count 0 2006.281.08:16:11.07#ibcon#about to read 5, iclass 7, count 0 2006.281.08:16:11.07#ibcon#read 5, iclass 7, count 0 2006.281.08:16:11.07#ibcon#about to read 6, iclass 7, count 0 2006.281.08:16:11.07#ibcon#read 6, iclass 7, count 0 2006.281.08:16:11.07#ibcon#end of sib2, iclass 7, count 0 2006.281.08:16:11.07#ibcon#*after write, iclass 7, count 0 2006.281.08:16:11.07#ibcon#*before return 0, iclass 7, count 0 2006.281.08:16:11.07#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:16:11.07#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:16:11.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:16:11.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:16:11.07$vc4f8/valo=7,832.99 2006.281.08:16:11.07#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.08:16:11.07#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.08:16:11.07#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:11.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:16:11.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:16:11.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:16:11.07#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:16:11.07#ibcon#first serial, iclass 11, count 0 2006.281.08:16:11.07#ibcon#enter sib2, iclass 11, count 0 2006.281.08:16:11.07#ibcon#flushed, iclass 11, count 0 2006.281.08:16:11.07#ibcon#about to write, iclass 11, count 0 2006.281.08:16:11.07#ibcon#wrote, iclass 11, count 0 2006.281.08:16:11.07#ibcon#about to read 3, iclass 11, count 0 2006.281.08:16:11.09#ibcon#read 3, iclass 11, count 0 2006.281.08:16:11.09#ibcon#about to read 4, iclass 11, count 0 2006.281.08:16:11.09#ibcon#read 4, iclass 11, count 0 2006.281.08:16:11.09#ibcon#about to read 5, iclass 11, count 0 2006.281.08:16:11.09#ibcon#read 5, iclass 11, count 0 2006.281.08:16:11.09#ibcon#about to read 6, iclass 11, count 0 2006.281.08:16:11.09#ibcon#read 6, iclass 11, count 0 2006.281.08:16:11.09#ibcon#end of sib2, iclass 11, count 0 2006.281.08:16:11.09#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:16:11.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:16:11.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:16:11.09#ibcon#*before write, iclass 11, count 0 2006.281.08:16:11.09#ibcon#enter sib2, iclass 11, count 0 2006.281.08:16:11.09#ibcon#flushed, iclass 11, count 0 2006.281.08:16:11.10#ibcon#about to write, iclass 11, count 0 2006.281.08:16:11.10#ibcon#wrote, iclass 11, count 0 2006.281.08:16:11.10#ibcon#about to read 3, iclass 11, count 0 2006.281.08:16:11.14#ibcon#read 3, iclass 11, count 0 2006.281.08:16:11.14#ibcon#about to read 4, iclass 11, count 0 2006.281.08:16:11.14#ibcon#read 4, iclass 11, count 0 2006.281.08:16:11.14#ibcon#about to read 5, iclass 11, count 0 2006.281.08:16:11.14#ibcon#read 5, iclass 11, count 0 2006.281.08:16:11.14#ibcon#about to read 6, iclass 11, count 0 2006.281.08:16:11.14#ibcon#read 6, iclass 11, count 0 2006.281.08:16:11.14#ibcon#end of sib2, iclass 11, count 0 2006.281.08:16:11.14#ibcon#*after write, iclass 11, count 0 2006.281.08:16:11.14#ibcon#*before return 0, iclass 11, count 0 2006.281.08:16:11.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:16:11.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:16:11.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:16:11.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:16:11.14$vc4f8/va=7,6 2006.281.08:16:11.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.08:16:11.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.08:16:11.14#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:11.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:16:11.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:16:11.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:16:11.19#ibcon#enter wrdev, iclass 13, count 2 2006.281.08:16:11.19#ibcon#first serial, iclass 13, count 2 2006.281.08:16:11.19#ibcon#enter sib2, iclass 13, count 2 2006.281.08:16:11.19#ibcon#flushed, iclass 13, count 2 2006.281.08:16:11.19#ibcon#about to write, iclass 13, count 2 2006.281.08:16:11.19#ibcon#wrote, iclass 13, count 2 2006.281.08:16:11.19#ibcon#about to read 3, iclass 13, count 2 2006.281.08:16:11.21#ibcon#read 3, iclass 13, count 2 2006.281.08:16:11.21#ibcon#about to read 4, iclass 13, count 2 2006.281.08:16:11.21#ibcon#read 4, iclass 13, count 2 2006.281.08:16:11.21#ibcon#about to read 5, iclass 13, count 2 2006.281.08:16:11.21#ibcon#read 5, iclass 13, count 2 2006.281.08:16:11.21#ibcon#about to read 6, iclass 13, count 2 2006.281.08:16:11.21#ibcon#read 6, iclass 13, count 2 2006.281.08:16:11.21#ibcon#end of sib2, iclass 13, count 2 2006.281.08:16:11.21#ibcon#*mode == 0, iclass 13, count 2 2006.281.08:16:11.21#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.08:16:11.21#ibcon#[25=AT07-06\r\n] 2006.281.08:16:11.21#ibcon#*before write, iclass 13, count 2 2006.281.08:16:11.21#ibcon#enter sib2, iclass 13, count 2 2006.281.08:16:11.21#ibcon#flushed, iclass 13, count 2 2006.281.08:16:11.21#ibcon#about to write, iclass 13, count 2 2006.281.08:16:11.21#ibcon#wrote, iclass 13, count 2 2006.281.08:16:11.21#ibcon#about to read 3, iclass 13, count 2 2006.281.08:16:11.24#ibcon#read 3, iclass 13, count 2 2006.281.08:16:11.24#ibcon#about to read 4, iclass 13, count 2 2006.281.08:16:11.24#ibcon#read 4, iclass 13, count 2 2006.281.08:16:11.24#ibcon#about to read 5, iclass 13, count 2 2006.281.08:16:11.24#ibcon#read 5, iclass 13, count 2 2006.281.08:16:11.24#ibcon#about to read 6, iclass 13, count 2 2006.281.08:16:11.24#ibcon#read 6, iclass 13, count 2 2006.281.08:16:11.24#ibcon#end of sib2, iclass 13, count 2 2006.281.08:16:11.24#ibcon#*after write, iclass 13, count 2 2006.281.08:16:11.24#ibcon#*before return 0, iclass 13, count 2 2006.281.08:16:11.24#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:16:11.24#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:16:11.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.08:16:11.25#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:11.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:16:11.35#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:16:11.35#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:16:11.35#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:16:11.35#ibcon#first serial, iclass 13, count 0 2006.281.08:16:11.35#ibcon#enter sib2, iclass 13, count 0 2006.281.08:16:11.35#ibcon#flushed, iclass 13, count 0 2006.281.08:16:11.35#ibcon#about to write, iclass 13, count 0 2006.281.08:16:11.35#ibcon#wrote, iclass 13, count 0 2006.281.08:16:11.35#ibcon#about to read 3, iclass 13, count 0 2006.281.08:16:11.37#ibcon#read 3, iclass 13, count 0 2006.281.08:16:11.37#ibcon#about to read 4, iclass 13, count 0 2006.281.08:16:11.37#ibcon#read 4, iclass 13, count 0 2006.281.08:16:11.37#ibcon#about to read 5, iclass 13, count 0 2006.281.08:16:11.37#ibcon#read 5, iclass 13, count 0 2006.281.08:16:11.37#ibcon#about to read 6, iclass 13, count 0 2006.281.08:16:11.37#ibcon#read 6, iclass 13, count 0 2006.281.08:16:11.37#ibcon#end of sib2, iclass 13, count 0 2006.281.08:16:11.37#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:16:11.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:16:11.37#ibcon#[25=USB\r\n] 2006.281.08:16:11.37#ibcon#*before write, iclass 13, count 0 2006.281.08:16:11.37#ibcon#enter sib2, iclass 13, count 0 2006.281.08:16:11.37#ibcon#flushed, iclass 13, count 0 2006.281.08:16:11.37#ibcon#about to write, iclass 13, count 0 2006.281.08:16:11.37#ibcon#wrote, iclass 13, count 0 2006.281.08:16:11.37#ibcon#about to read 3, iclass 13, count 0 2006.281.08:16:11.40#ibcon#read 3, iclass 13, count 0 2006.281.08:16:11.40#ibcon#about to read 4, iclass 13, count 0 2006.281.08:16:11.40#ibcon#read 4, iclass 13, count 0 2006.281.08:16:11.40#ibcon#about to read 5, iclass 13, count 0 2006.281.08:16:11.40#ibcon#read 5, iclass 13, count 0 2006.281.08:16:11.40#ibcon#about to read 6, iclass 13, count 0 2006.281.08:16:11.40#ibcon#read 6, iclass 13, count 0 2006.281.08:16:11.40#ibcon#end of sib2, iclass 13, count 0 2006.281.08:16:11.40#ibcon#*after write, iclass 13, count 0 2006.281.08:16:11.40#ibcon#*before return 0, iclass 13, count 0 2006.281.08:16:11.40#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:16:11.40#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:16:11.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:16:11.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:16:11.40$vc4f8/valo=8,852.99 2006.281.08:16:11.40#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.08:16:11.40#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.08:16:11.40#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:11.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:16:11.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:16:11.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:16:11.40#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:16:11.40#ibcon#first serial, iclass 15, count 0 2006.281.08:16:11.40#ibcon#enter sib2, iclass 15, count 0 2006.281.08:16:11.40#ibcon#flushed, iclass 15, count 0 2006.281.08:16:11.40#ibcon#about to write, iclass 15, count 0 2006.281.08:16:11.40#ibcon#wrote, iclass 15, count 0 2006.281.08:16:11.40#ibcon#about to read 3, iclass 15, count 0 2006.281.08:16:11.42#ibcon#read 3, iclass 15, count 0 2006.281.08:16:11.42#ibcon#about to read 4, iclass 15, count 0 2006.281.08:16:11.42#ibcon#read 4, iclass 15, count 0 2006.281.08:16:11.42#ibcon#about to read 5, iclass 15, count 0 2006.281.08:16:11.42#ibcon#read 5, iclass 15, count 0 2006.281.08:16:11.42#ibcon#about to read 6, iclass 15, count 0 2006.281.08:16:11.42#ibcon#read 6, iclass 15, count 0 2006.281.08:16:11.42#ibcon#end of sib2, iclass 15, count 0 2006.281.08:16:11.42#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:16:11.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:16:11.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:16:11.42#ibcon#*before write, iclass 15, count 0 2006.281.08:16:11.42#ibcon#enter sib2, iclass 15, count 0 2006.281.08:16:11.42#ibcon#flushed, iclass 15, count 0 2006.281.08:16:11.42#ibcon#about to write, iclass 15, count 0 2006.281.08:16:11.42#ibcon#wrote, iclass 15, count 0 2006.281.08:16:11.42#ibcon#about to read 3, iclass 15, count 0 2006.281.08:16:11.47#ibcon#read 3, iclass 15, count 0 2006.281.08:16:11.47#ibcon#about to read 4, iclass 15, count 0 2006.281.08:16:11.47#ibcon#read 4, iclass 15, count 0 2006.281.08:16:11.47#ibcon#about to read 5, iclass 15, count 0 2006.281.08:16:11.47#ibcon#read 5, iclass 15, count 0 2006.281.08:16:11.47#ibcon#about to read 6, iclass 15, count 0 2006.281.08:16:11.47#ibcon#read 6, iclass 15, count 0 2006.281.08:16:11.47#ibcon#end of sib2, iclass 15, count 0 2006.281.08:16:11.47#ibcon#*after write, iclass 15, count 0 2006.281.08:16:11.47#ibcon#*before return 0, iclass 15, count 0 2006.281.08:16:11.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:16:11.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:16:11.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:16:11.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:16:11.47$vc4f8/va=8,6 2006.281.08:16:11.47#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.08:16:11.47#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.08:16:11.47#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:11.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:16:11.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:16:11.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:16:11.51#ibcon#enter wrdev, iclass 17, count 2 2006.281.08:16:11.51#ibcon#first serial, iclass 17, count 2 2006.281.08:16:11.51#ibcon#enter sib2, iclass 17, count 2 2006.281.08:16:11.51#ibcon#flushed, iclass 17, count 2 2006.281.08:16:11.51#ibcon#about to write, iclass 17, count 2 2006.281.08:16:11.51#ibcon#wrote, iclass 17, count 2 2006.281.08:16:11.51#ibcon#about to read 3, iclass 17, count 2 2006.281.08:16:11.53#ibcon#read 3, iclass 17, count 2 2006.281.08:16:11.53#ibcon#about to read 4, iclass 17, count 2 2006.281.08:16:11.53#ibcon#read 4, iclass 17, count 2 2006.281.08:16:11.53#ibcon#about to read 5, iclass 17, count 2 2006.281.08:16:11.53#ibcon#read 5, iclass 17, count 2 2006.281.08:16:11.53#ibcon#about to read 6, iclass 17, count 2 2006.281.08:16:11.53#ibcon#read 6, iclass 17, count 2 2006.281.08:16:11.53#ibcon#end of sib2, iclass 17, count 2 2006.281.08:16:11.53#ibcon#*mode == 0, iclass 17, count 2 2006.281.08:16:11.53#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.08:16:11.53#ibcon#[25=AT08-06\r\n] 2006.281.08:16:11.53#ibcon#*before write, iclass 17, count 2 2006.281.08:16:11.53#ibcon#enter sib2, iclass 17, count 2 2006.281.08:16:11.53#ibcon#flushed, iclass 17, count 2 2006.281.08:16:11.53#ibcon#about to write, iclass 17, count 2 2006.281.08:16:11.53#ibcon#wrote, iclass 17, count 2 2006.281.08:16:11.53#ibcon#about to read 3, iclass 17, count 2 2006.281.08:16:11.56#ibcon#read 3, iclass 17, count 2 2006.281.08:16:11.56#ibcon#about to read 4, iclass 17, count 2 2006.281.08:16:11.56#ibcon#read 4, iclass 17, count 2 2006.281.08:16:11.56#ibcon#about to read 5, iclass 17, count 2 2006.281.08:16:11.56#ibcon#read 5, iclass 17, count 2 2006.281.08:16:11.56#ibcon#about to read 6, iclass 17, count 2 2006.281.08:16:11.56#ibcon#read 6, iclass 17, count 2 2006.281.08:16:11.56#ibcon#end of sib2, iclass 17, count 2 2006.281.08:16:11.56#ibcon#*after write, iclass 17, count 2 2006.281.08:16:11.56#ibcon#*before return 0, iclass 17, count 2 2006.281.08:16:11.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:16:11.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:16:11.56#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.08:16:11.56#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:11.56#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:16:11.68#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:16:11.68#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:16:11.68#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:16:11.68#ibcon#first serial, iclass 17, count 0 2006.281.08:16:11.68#ibcon#enter sib2, iclass 17, count 0 2006.281.08:16:11.68#ibcon#flushed, iclass 17, count 0 2006.281.08:16:11.68#ibcon#about to write, iclass 17, count 0 2006.281.08:16:11.68#ibcon#wrote, iclass 17, count 0 2006.281.08:16:11.68#ibcon#about to read 3, iclass 17, count 0 2006.281.08:16:11.70#ibcon#read 3, iclass 17, count 0 2006.281.08:16:11.70#ibcon#about to read 4, iclass 17, count 0 2006.281.08:16:11.70#ibcon#read 4, iclass 17, count 0 2006.281.08:16:11.70#ibcon#about to read 5, iclass 17, count 0 2006.281.08:16:11.70#ibcon#read 5, iclass 17, count 0 2006.281.08:16:11.70#ibcon#about to read 6, iclass 17, count 0 2006.281.08:16:11.70#ibcon#read 6, iclass 17, count 0 2006.281.08:16:11.70#ibcon#end of sib2, iclass 17, count 0 2006.281.08:16:11.70#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:16:11.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:16:11.70#ibcon#[25=USB\r\n] 2006.281.08:16:11.70#ibcon#*before write, iclass 17, count 0 2006.281.08:16:11.70#ibcon#enter sib2, iclass 17, count 0 2006.281.08:16:11.70#ibcon#flushed, iclass 17, count 0 2006.281.08:16:11.70#ibcon#about to write, iclass 17, count 0 2006.281.08:16:11.70#ibcon#wrote, iclass 17, count 0 2006.281.08:16:11.70#ibcon#about to read 3, iclass 17, count 0 2006.281.08:16:11.73#ibcon#read 3, iclass 17, count 0 2006.281.08:16:11.73#ibcon#about to read 4, iclass 17, count 0 2006.281.08:16:11.73#ibcon#read 4, iclass 17, count 0 2006.281.08:16:11.73#ibcon#about to read 5, iclass 17, count 0 2006.281.08:16:11.73#ibcon#read 5, iclass 17, count 0 2006.281.08:16:11.73#ibcon#about to read 6, iclass 17, count 0 2006.281.08:16:11.73#ibcon#read 6, iclass 17, count 0 2006.281.08:16:11.73#ibcon#end of sib2, iclass 17, count 0 2006.281.08:16:11.73#ibcon#*after write, iclass 17, count 0 2006.281.08:16:11.73#ibcon#*before return 0, iclass 17, count 0 2006.281.08:16:11.73#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:16:11.73#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:16:11.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:16:11.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:16:11.73$vc4f8/vblo=1,632.99 2006.281.08:16:11.73#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.08:16:11.73#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.08:16:11.73#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:11.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:16:11.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:16:11.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:16:11.73#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:16:11.73#ibcon#first serial, iclass 19, count 0 2006.281.08:16:11.73#ibcon#enter sib2, iclass 19, count 0 2006.281.08:16:11.73#ibcon#flushed, iclass 19, count 0 2006.281.08:16:11.73#ibcon#about to write, iclass 19, count 0 2006.281.08:16:11.73#ibcon#wrote, iclass 19, count 0 2006.281.08:16:11.73#ibcon#about to read 3, iclass 19, count 0 2006.281.08:16:11.75#ibcon#read 3, iclass 19, count 0 2006.281.08:16:11.75#ibcon#about to read 4, iclass 19, count 0 2006.281.08:16:11.75#ibcon#read 4, iclass 19, count 0 2006.281.08:16:11.75#ibcon#about to read 5, iclass 19, count 0 2006.281.08:16:11.75#ibcon#read 5, iclass 19, count 0 2006.281.08:16:11.75#ibcon#about to read 6, iclass 19, count 0 2006.281.08:16:11.75#ibcon#read 6, iclass 19, count 0 2006.281.08:16:11.75#ibcon#end of sib2, iclass 19, count 0 2006.281.08:16:11.75#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:16:11.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:16:11.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:16:11.75#ibcon#*before write, iclass 19, count 0 2006.281.08:16:11.75#ibcon#enter sib2, iclass 19, count 0 2006.281.08:16:11.75#ibcon#flushed, iclass 19, count 0 2006.281.08:16:11.75#ibcon#about to write, iclass 19, count 0 2006.281.08:16:11.75#ibcon#wrote, iclass 19, count 0 2006.281.08:16:11.75#ibcon#about to read 3, iclass 19, count 0 2006.281.08:16:11.79#ibcon#read 3, iclass 19, count 0 2006.281.08:16:11.79#ibcon#about to read 4, iclass 19, count 0 2006.281.08:16:11.79#ibcon#read 4, iclass 19, count 0 2006.281.08:16:11.79#ibcon#about to read 5, iclass 19, count 0 2006.281.08:16:11.79#ibcon#read 5, iclass 19, count 0 2006.281.08:16:11.79#ibcon#about to read 6, iclass 19, count 0 2006.281.08:16:11.79#ibcon#read 6, iclass 19, count 0 2006.281.08:16:11.79#ibcon#end of sib2, iclass 19, count 0 2006.281.08:16:11.79#ibcon#*after write, iclass 19, count 0 2006.281.08:16:11.79#ibcon#*before return 0, iclass 19, count 0 2006.281.08:16:11.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:16:11.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:16:11.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:16:11.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:16:11.79$vc4f8/vb=1,4 2006.281.08:16:11.81#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.08:16:11.81#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.08:16:11.81#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:11.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:16:11.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:16:11.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:16:11.81#ibcon#enter wrdev, iclass 21, count 2 2006.281.08:16:11.81#ibcon#first serial, iclass 21, count 2 2006.281.08:16:11.81#ibcon#enter sib2, iclass 21, count 2 2006.281.08:16:11.81#ibcon#flushed, iclass 21, count 2 2006.281.08:16:11.81#ibcon#about to write, iclass 21, count 2 2006.281.08:16:11.81#ibcon#wrote, iclass 21, count 2 2006.281.08:16:11.81#ibcon#about to read 3, iclass 21, count 2 2006.281.08:16:11.82#ibcon#read 3, iclass 21, count 2 2006.281.08:16:11.82#ibcon#about to read 4, iclass 21, count 2 2006.281.08:16:11.82#ibcon#read 4, iclass 21, count 2 2006.281.08:16:11.82#ibcon#about to read 5, iclass 21, count 2 2006.281.08:16:11.82#ibcon#read 5, iclass 21, count 2 2006.281.08:16:11.82#ibcon#about to read 6, iclass 21, count 2 2006.281.08:16:11.82#ibcon#read 6, iclass 21, count 2 2006.281.08:16:11.82#ibcon#end of sib2, iclass 21, count 2 2006.281.08:16:11.82#ibcon#*mode == 0, iclass 21, count 2 2006.281.08:16:11.82#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.08:16:11.82#ibcon#[27=AT01-04\r\n] 2006.281.08:16:11.82#ibcon#*before write, iclass 21, count 2 2006.281.08:16:11.82#ibcon#enter sib2, iclass 21, count 2 2006.281.08:16:11.82#ibcon#flushed, iclass 21, count 2 2006.281.08:16:11.82#ibcon#about to write, iclass 21, count 2 2006.281.08:16:11.82#ibcon#wrote, iclass 21, count 2 2006.281.08:16:11.82#ibcon#about to read 3, iclass 21, count 2 2006.281.08:16:11.85#ibcon#read 3, iclass 21, count 2 2006.281.08:16:11.85#ibcon#about to read 4, iclass 21, count 2 2006.281.08:16:11.85#ibcon#read 4, iclass 21, count 2 2006.281.08:16:11.85#ibcon#about to read 5, iclass 21, count 2 2006.281.08:16:11.85#ibcon#read 5, iclass 21, count 2 2006.281.08:16:11.85#ibcon#about to read 6, iclass 21, count 2 2006.281.08:16:11.85#ibcon#read 6, iclass 21, count 2 2006.281.08:16:11.85#ibcon#end of sib2, iclass 21, count 2 2006.281.08:16:11.85#ibcon#*after write, iclass 21, count 2 2006.281.08:16:11.85#ibcon#*before return 0, iclass 21, count 2 2006.281.08:16:11.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:16:11.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:16:11.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.08:16:11.85#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:11.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:16:11.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:16:11.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:16:11.97#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:16:11.97#ibcon#first serial, iclass 21, count 0 2006.281.08:16:11.97#ibcon#enter sib2, iclass 21, count 0 2006.281.08:16:11.97#ibcon#flushed, iclass 21, count 0 2006.281.08:16:11.97#ibcon#about to write, iclass 21, count 0 2006.281.08:16:11.97#ibcon#wrote, iclass 21, count 0 2006.281.08:16:11.97#ibcon#about to read 3, iclass 21, count 0 2006.281.08:16:12.00#ibcon#read 3, iclass 21, count 0 2006.281.08:16:12.00#ibcon#about to read 4, iclass 21, count 0 2006.281.08:16:12.00#ibcon#read 4, iclass 21, count 0 2006.281.08:16:12.00#ibcon#about to read 5, iclass 21, count 0 2006.281.08:16:12.00#ibcon#read 5, iclass 21, count 0 2006.281.08:16:12.00#ibcon#about to read 6, iclass 21, count 0 2006.281.08:16:12.00#ibcon#read 6, iclass 21, count 0 2006.281.08:16:12.00#ibcon#end of sib2, iclass 21, count 0 2006.281.08:16:12.00#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:16:12.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:16:12.00#ibcon#[27=USB\r\n] 2006.281.08:16:12.00#ibcon#*before write, iclass 21, count 0 2006.281.08:16:12.00#ibcon#enter sib2, iclass 21, count 0 2006.281.08:16:12.00#ibcon#flushed, iclass 21, count 0 2006.281.08:16:12.00#ibcon#about to write, iclass 21, count 0 2006.281.08:16:12.00#ibcon#wrote, iclass 21, count 0 2006.281.08:16:12.00#ibcon#about to read 3, iclass 21, count 0 2006.281.08:16:12.02#ibcon#read 3, iclass 21, count 0 2006.281.08:16:12.02#ibcon#about to read 4, iclass 21, count 0 2006.281.08:16:12.02#ibcon#read 4, iclass 21, count 0 2006.281.08:16:12.02#ibcon#about to read 5, iclass 21, count 0 2006.281.08:16:12.02#ibcon#read 5, iclass 21, count 0 2006.281.08:16:12.02#ibcon#about to read 6, iclass 21, count 0 2006.281.08:16:12.02#ibcon#read 6, iclass 21, count 0 2006.281.08:16:12.02#ibcon#end of sib2, iclass 21, count 0 2006.281.08:16:12.02#ibcon#*after write, iclass 21, count 0 2006.281.08:16:12.02#ibcon#*before return 0, iclass 21, count 0 2006.281.08:16:12.02#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:16:12.02#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:16:12.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:16:12.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:16:12.02$vc4f8/vblo=2,640.99 2006.281.08:16:12.02#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.08:16:12.02#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.08:16:12.02#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:12.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:12.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:12.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:12.02#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:16:12.02#ibcon#first serial, iclass 23, count 0 2006.281.08:16:12.02#ibcon#enter sib2, iclass 23, count 0 2006.281.08:16:12.02#ibcon#flushed, iclass 23, count 0 2006.281.08:16:12.02#ibcon#about to write, iclass 23, count 0 2006.281.08:16:12.02#ibcon#wrote, iclass 23, count 0 2006.281.08:16:12.02#ibcon#about to read 3, iclass 23, count 0 2006.281.08:16:12.04#ibcon#read 3, iclass 23, count 0 2006.281.08:16:12.04#ibcon#about to read 4, iclass 23, count 0 2006.281.08:16:12.04#ibcon#read 4, iclass 23, count 0 2006.281.08:16:12.04#ibcon#about to read 5, iclass 23, count 0 2006.281.08:16:12.04#ibcon#read 5, iclass 23, count 0 2006.281.08:16:12.04#ibcon#about to read 6, iclass 23, count 0 2006.281.08:16:12.04#ibcon#read 6, iclass 23, count 0 2006.281.08:16:12.04#ibcon#end of sib2, iclass 23, count 0 2006.281.08:16:12.04#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:16:12.04#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:16:12.04#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:16:12.04#ibcon#*before write, iclass 23, count 0 2006.281.08:16:12.04#ibcon#enter sib2, iclass 23, count 0 2006.281.08:16:12.04#ibcon#flushed, iclass 23, count 0 2006.281.08:16:12.04#ibcon#about to write, iclass 23, count 0 2006.281.08:16:12.04#ibcon#wrote, iclass 23, count 0 2006.281.08:16:12.04#ibcon#about to read 3, iclass 23, count 0 2006.281.08:16:12.08#ibcon#read 3, iclass 23, count 0 2006.281.08:16:12.08#ibcon#about to read 4, iclass 23, count 0 2006.281.08:16:12.08#ibcon#read 4, iclass 23, count 0 2006.281.08:16:12.08#ibcon#about to read 5, iclass 23, count 0 2006.281.08:16:12.08#ibcon#read 5, iclass 23, count 0 2006.281.08:16:12.08#ibcon#about to read 6, iclass 23, count 0 2006.281.08:16:12.08#ibcon#read 6, iclass 23, count 0 2006.281.08:16:12.08#ibcon#end of sib2, iclass 23, count 0 2006.281.08:16:12.08#ibcon#*after write, iclass 23, count 0 2006.281.08:16:12.08#ibcon#*before return 0, iclass 23, count 0 2006.281.08:16:12.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:12.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:16:12.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:16:12.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:16:12.08$vc4f8/vb=2,5 2006.281.08:16:12.08#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.08:16:12.08#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.08:16:12.08#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:12.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:12.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:12.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:12.14#ibcon#enter wrdev, iclass 25, count 2 2006.281.08:16:12.14#ibcon#first serial, iclass 25, count 2 2006.281.08:16:12.14#ibcon#enter sib2, iclass 25, count 2 2006.281.08:16:12.14#ibcon#flushed, iclass 25, count 2 2006.281.08:16:12.14#ibcon#about to write, iclass 25, count 2 2006.281.08:16:12.14#ibcon#wrote, iclass 25, count 2 2006.281.08:16:12.14#ibcon#about to read 3, iclass 25, count 2 2006.281.08:16:12.16#ibcon#read 3, iclass 25, count 2 2006.281.08:16:12.16#ibcon#about to read 4, iclass 25, count 2 2006.281.08:16:12.16#ibcon#read 4, iclass 25, count 2 2006.281.08:16:12.16#ibcon#about to read 5, iclass 25, count 2 2006.281.08:16:12.16#ibcon#read 5, iclass 25, count 2 2006.281.08:16:12.16#ibcon#about to read 6, iclass 25, count 2 2006.281.08:16:12.16#ibcon#read 6, iclass 25, count 2 2006.281.08:16:12.16#ibcon#end of sib2, iclass 25, count 2 2006.281.08:16:12.16#ibcon#*mode == 0, iclass 25, count 2 2006.281.08:16:12.16#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.08:16:12.16#ibcon#[27=AT02-05\r\n] 2006.281.08:16:12.16#ibcon#*before write, iclass 25, count 2 2006.281.08:16:12.16#ibcon#enter sib2, iclass 25, count 2 2006.281.08:16:12.16#ibcon#flushed, iclass 25, count 2 2006.281.08:16:12.16#ibcon#about to write, iclass 25, count 2 2006.281.08:16:12.16#ibcon#wrote, iclass 25, count 2 2006.281.08:16:12.16#ibcon#about to read 3, iclass 25, count 2 2006.281.08:16:12.19#ibcon#read 3, iclass 25, count 2 2006.281.08:16:12.19#ibcon#about to read 4, iclass 25, count 2 2006.281.08:16:12.19#ibcon#read 4, iclass 25, count 2 2006.281.08:16:12.19#ibcon#about to read 5, iclass 25, count 2 2006.281.08:16:12.19#ibcon#read 5, iclass 25, count 2 2006.281.08:16:12.19#ibcon#about to read 6, iclass 25, count 2 2006.281.08:16:12.19#ibcon#read 6, iclass 25, count 2 2006.281.08:16:12.19#ibcon#end of sib2, iclass 25, count 2 2006.281.08:16:12.19#ibcon#*after write, iclass 25, count 2 2006.281.08:16:12.19#ibcon#*before return 0, iclass 25, count 2 2006.281.08:16:12.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:12.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:16:12.19#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.08:16:12.19#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:12.19#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:12.31#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:12.31#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:12.31#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:16:12.31#ibcon#first serial, iclass 25, count 0 2006.281.08:16:12.31#ibcon#enter sib2, iclass 25, count 0 2006.281.08:16:12.31#ibcon#flushed, iclass 25, count 0 2006.281.08:16:12.31#ibcon#about to write, iclass 25, count 0 2006.281.08:16:12.31#ibcon#wrote, iclass 25, count 0 2006.281.08:16:12.31#ibcon#about to read 3, iclass 25, count 0 2006.281.08:16:12.33#ibcon#read 3, iclass 25, count 0 2006.281.08:16:12.33#ibcon#about to read 4, iclass 25, count 0 2006.281.08:16:12.33#ibcon#read 4, iclass 25, count 0 2006.281.08:16:12.33#ibcon#about to read 5, iclass 25, count 0 2006.281.08:16:12.33#ibcon#read 5, iclass 25, count 0 2006.281.08:16:12.33#ibcon#about to read 6, iclass 25, count 0 2006.281.08:16:12.33#ibcon#read 6, iclass 25, count 0 2006.281.08:16:12.33#ibcon#end of sib2, iclass 25, count 0 2006.281.08:16:12.33#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:16:12.33#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:16:12.33#ibcon#[27=USB\r\n] 2006.281.08:16:12.33#ibcon#*before write, iclass 25, count 0 2006.281.08:16:12.33#ibcon#enter sib2, iclass 25, count 0 2006.281.08:16:12.33#ibcon#flushed, iclass 25, count 0 2006.281.08:16:12.33#ibcon#about to write, iclass 25, count 0 2006.281.08:16:12.33#ibcon#wrote, iclass 25, count 0 2006.281.08:16:12.33#ibcon#about to read 3, iclass 25, count 0 2006.281.08:16:12.37#ibcon#read 3, iclass 25, count 0 2006.281.08:16:12.37#ibcon#about to read 4, iclass 25, count 0 2006.281.08:16:12.37#ibcon#read 4, iclass 25, count 0 2006.281.08:16:12.37#ibcon#about to read 5, iclass 25, count 0 2006.281.08:16:12.37#ibcon#read 5, iclass 25, count 0 2006.281.08:16:12.37#ibcon#about to read 6, iclass 25, count 0 2006.281.08:16:12.37#ibcon#read 6, iclass 25, count 0 2006.281.08:16:12.37#ibcon#end of sib2, iclass 25, count 0 2006.281.08:16:12.37#ibcon#*after write, iclass 25, count 0 2006.281.08:16:12.37#ibcon#*before return 0, iclass 25, count 0 2006.281.08:16:12.37#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:12.37#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:16:12.37#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:16:12.37#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:16:12.37$vc4f8/vblo=3,656.99 2006.281.08:16:12.37#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.08:16:12.37#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.08:16:12.37#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:12.37#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:12.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:12.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:12.37#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:16:12.37#ibcon#first serial, iclass 27, count 0 2006.281.08:16:12.37#ibcon#enter sib2, iclass 27, count 0 2006.281.08:16:12.37#ibcon#flushed, iclass 27, count 0 2006.281.08:16:12.37#ibcon#about to write, iclass 27, count 0 2006.281.08:16:12.37#ibcon#wrote, iclass 27, count 0 2006.281.08:16:12.37#ibcon#about to read 3, iclass 27, count 0 2006.281.08:16:12.38#ibcon#read 3, iclass 27, count 0 2006.281.08:16:12.38#ibcon#about to read 4, iclass 27, count 0 2006.281.08:16:12.38#ibcon#read 4, iclass 27, count 0 2006.281.08:16:12.38#ibcon#about to read 5, iclass 27, count 0 2006.281.08:16:12.38#ibcon#read 5, iclass 27, count 0 2006.281.08:16:12.38#ibcon#about to read 6, iclass 27, count 0 2006.281.08:16:12.38#ibcon#read 6, iclass 27, count 0 2006.281.08:16:12.38#ibcon#end of sib2, iclass 27, count 0 2006.281.08:16:12.38#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:16:12.38#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:16:12.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:16:12.41#ibcon#*before write, iclass 27, count 0 2006.281.08:16:12.41#ibcon#enter sib2, iclass 27, count 0 2006.281.08:16:12.41#ibcon#flushed, iclass 27, count 0 2006.281.08:16:12.41#ibcon#about to write, iclass 27, count 0 2006.281.08:16:12.41#ibcon#wrote, iclass 27, count 0 2006.281.08:16:12.41#ibcon#about to read 3, iclass 27, count 0 2006.281.08:16:12.44#ibcon#read 3, iclass 27, count 0 2006.281.08:16:12.44#ibcon#about to read 4, iclass 27, count 0 2006.281.08:16:12.44#ibcon#read 4, iclass 27, count 0 2006.281.08:16:12.44#ibcon#about to read 5, iclass 27, count 0 2006.281.08:16:12.44#ibcon#read 5, iclass 27, count 0 2006.281.08:16:12.44#ibcon#about to read 6, iclass 27, count 0 2006.281.08:16:12.44#ibcon#read 6, iclass 27, count 0 2006.281.08:16:12.44#ibcon#end of sib2, iclass 27, count 0 2006.281.08:16:12.44#ibcon#*after write, iclass 27, count 0 2006.281.08:16:12.44#ibcon#*before return 0, iclass 27, count 0 2006.281.08:16:12.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:12.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:16:12.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:16:12.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:16:12.44$vc4f8/vb=3,4 2006.281.08:16:12.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.08:16:12.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.08:16:12.44#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:12.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:12.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:12.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:12.50#ibcon#enter wrdev, iclass 29, count 2 2006.281.08:16:12.50#ibcon#first serial, iclass 29, count 2 2006.281.08:16:12.50#ibcon#enter sib2, iclass 29, count 2 2006.281.08:16:12.50#ibcon#flushed, iclass 29, count 2 2006.281.08:16:12.50#ibcon#about to write, iclass 29, count 2 2006.281.08:16:12.50#ibcon#wrote, iclass 29, count 2 2006.281.08:16:12.50#ibcon#about to read 3, iclass 29, count 2 2006.281.08:16:12.51#ibcon#read 3, iclass 29, count 2 2006.281.08:16:12.51#ibcon#about to read 4, iclass 29, count 2 2006.281.08:16:12.51#ibcon#read 4, iclass 29, count 2 2006.281.08:16:12.51#ibcon#about to read 5, iclass 29, count 2 2006.281.08:16:12.51#ibcon#read 5, iclass 29, count 2 2006.281.08:16:12.51#ibcon#about to read 6, iclass 29, count 2 2006.281.08:16:12.51#ibcon#read 6, iclass 29, count 2 2006.281.08:16:12.51#ibcon#end of sib2, iclass 29, count 2 2006.281.08:16:12.51#ibcon#*mode == 0, iclass 29, count 2 2006.281.08:16:12.51#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.08:16:12.51#ibcon#[27=AT03-04\r\n] 2006.281.08:16:12.51#ibcon#*before write, iclass 29, count 2 2006.281.08:16:12.51#ibcon#enter sib2, iclass 29, count 2 2006.281.08:16:12.51#ibcon#flushed, iclass 29, count 2 2006.281.08:16:12.51#ibcon#about to write, iclass 29, count 2 2006.281.08:16:12.51#ibcon#wrote, iclass 29, count 2 2006.281.08:16:12.51#ibcon#about to read 3, iclass 29, count 2 2006.281.08:16:12.54#ibcon#read 3, iclass 29, count 2 2006.281.08:16:12.54#ibcon#about to read 4, iclass 29, count 2 2006.281.08:16:12.55#ibcon#read 4, iclass 29, count 2 2006.281.08:16:12.55#ibcon#about to read 5, iclass 29, count 2 2006.281.08:16:12.55#ibcon#read 5, iclass 29, count 2 2006.281.08:16:12.55#ibcon#about to read 6, iclass 29, count 2 2006.281.08:16:12.55#ibcon#read 6, iclass 29, count 2 2006.281.08:16:12.55#ibcon#end of sib2, iclass 29, count 2 2006.281.08:16:12.55#ibcon#*after write, iclass 29, count 2 2006.281.08:16:12.55#ibcon#*before return 0, iclass 29, count 2 2006.281.08:16:12.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:12.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:16:12.55#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.08:16:12.55#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:12.55#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:12.67#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:12.67#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:12.67#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:16:12.67#ibcon#first serial, iclass 29, count 0 2006.281.08:16:12.67#ibcon#enter sib2, iclass 29, count 0 2006.281.08:16:12.67#ibcon#flushed, iclass 29, count 0 2006.281.08:16:12.67#ibcon#about to write, iclass 29, count 0 2006.281.08:16:12.67#ibcon#wrote, iclass 29, count 0 2006.281.08:16:12.67#ibcon#about to read 3, iclass 29, count 0 2006.281.08:16:12.68#ibcon#read 3, iclass 29, count 0 2006.281.08:16:12.68#ibcon#about to read 4, iclass 29, count 0 2006.281.08:16:12.68#ibcon#read 4, iclass 29, count 0 2006.281.08:16:12.68#ibcon#about to read 5, iclass 29, count 0 2006.281.08:16:12.68#ibcon#read 5, iclass 29, count 0 2006.281.08:16:12.68#ibcon#about to read 6, iclass 29, count 0 2006.281.08:16:12.68#ibcon#read 6, iclass 29, count 0 2006.281.08:16:12.68#ibcon#end of sib2, iclass 29, count 0 2006.281.08:16:12.68#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:16:12.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:16:12.68#ibcon#[27=USB\r\n] 2006.281.08:16:12.68#ibcon#*before write, iclass 29, count 0 2006.281.08:16:12.68#ibcon#enter sib2, iclass 29, count 0 2006.281.08:16:12.68#ibcon#flushed, iclass 29, count 0 2006.281.08:16:12.68#ibcon#about to write, iclass 29, count 0 2006.281.08:16:12.68#ibcon#wrote, iclass 29, count 0 2006.281.08:16:12.68#ibcon#about to read 3, iclass 29, count 0 2006.281.08:16:12.71#ibcon#read 3, iclass 29, count 0 2006.281.08:16:12.71#ibcon#about to read 4, iclass 29, count 0 2006.281.08:16:12.71#ibcon#read 4, iclass 29, count 0 2006.281.08:16:12.71#ibcon#about to read 5, iclass 29, count 0 2006.281.08:16:12.71#ibcon#read 5, iclass 29, count 0 2006.281.08:16:12.71#ibcon#about to read 6, iclass 29, count 0 2006.281.08:16:12.71#ibcon#read 6, iclass 29, count 0 2006.281.08:16:12.71#ibcon#end of sib2, iclass 29, count 0 2006.281.08:16:12.71#ibcon#*after write, iclass 29, count 0 2006.281.08:16:12.71#ibcon#*before return 0, iclass 29, count 0 2006.281.08:16:12.71#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:12.71#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:16:12.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:16:12.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:16:12.71$vc4f8/vblo=4,712.99 2006.281.08:16:12.71#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:16:12.71#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:16:12.71#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:12.71#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:12.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:12.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:12.71#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:16:12.71#ibcon#first serial, iclass 31, count 0 2006.281.08:16:12.71#ibcon#enter sib2, iclass 31, count 0 2006.281.08:16:12.71#ibcon#flushed, iclass 31, count 0 2006.281.08:16:12.71#ibcon#about to write, iclass 31, count 0 2006.281.08:16:12.71#ibcon#wrote, iclass 31, count 0 2006.281.08:16:12.71#ibcon#about to read 3, iclass 31, count 0 2006.281.08:16:12.73#ibcon#read 3, iclass 31, count 0 2006.281.08:16:12.73#ibcon#about to read 4, iclass 31, count 0 2006.281.08:16:12.73#ibcon#read 4, iclass 31, count 0 2006.281.08:16:12.73#ibcon#about to read 5, iclass 31, count 0 2006.281.08:16:12.73#ibcon#read 5, iclass 31, count 0 2006.281.08:16:12.73#ibcon#about to read 6, iclass 31, count 0 2006.281.08:16:12.73#ibcon#read 6, iclass 31, count 0 2006.281.08:16:12.73#ibcon#end of sib2, iclass 31, count 0 2006.281.08:16:12.73#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:16:12.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:16:12.73#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:16:12.73#ibcon#*before write, iclass 31, count 0 2006.281.08:16:12.73#ibcon#enter sib2, iclass 31, count 0 2006.281.08:16:12.73#ibcon#flushed, iclass 31, count 0 2006.281.08:16:12.73#ibcon#about to write, iclass 31, count 0 2006.281.08:16:12.73#ibcon#wrote, iclass 31, count 0 2006.281.08:16:12.73#ibcon#about to read 3, iclass 31, count 0 2006.281.08:16:12.78#ibcon#read 3, iclass 31, count 0 2006.281.08:16:12.78#ibcon#about to read 4, iclass 31, count 0 2006.281.08:16:12.78#ibcon#read 4, iclass 31, count 0 2006.281.08:16:12.78#ibcon#about to read 5, iclass 31, count 0 2006.281.08:16:12.78#ibcon#read 5, iclass 31, count 0 2006.281.08:16:12.78#ibcon#about to read 6, iclass 31, count 0 2006.281.08:16:12.78#ibcon#read 6, iclass 31, count 0 2006.281.08:16:12.78#ibcon#end of sib2, iclass 31, count 0 2006.281.08:16:12.78#ibcon#*after write, iclass 31, count 0 2006.281.08:16:12.78#ibcon#*before return 0, iclass 31, count 0 2006.281.08:16:12.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:12.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:16:12.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:16:12.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:16:12.78$vc4f8/vb=4,4 2006.281.08:16:12.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.08:16:12.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.08:16:12.78#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:12.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:12.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:12.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:12.82#ibcon#enter wrdev, iclass 33, count 2 2006.281.08:16:12.82#ibcon#first serial, iclass 33, count 2 2006.281.08:16:12.82#ibcon#enter sib2, iclass 33, count 2 2006.281.08:16:12.82#ibcon#flushed, iclass 33, count 2 2006.281.08:16:12.82#ibcon#about to write, iclass 33, count 2 2006.281.08:16:12.82#ibcon#wrote, iclass 33, count 2 2006.281.08:16:12.82#ibcon#about to read 3, iclass 33, count 2 2006.281.08:16:12.84#ibcon#read 3, iclass 33, count 2 2006.281.08:16:12.84#ibcon#about to read 4, iclass 33, count 2 2006.281.08:16:12.84#ibcon#read 4, iclass 33, count 2 2006.281.08:16:12.84#ibcon#about to read 5, iclass 33, count 2 2006.281.08:16:12.84#ibcon#read 5, iclass 33, count 2 2006.281.08:16:12.84#ibcon#about to read 6, iclass 33, count 2 2006.281.08:16:12.84#ibcon#read 6, iclass 33, count 2 2006.281.08:16:12.84#ibcon#end of sib2, iclass 33, count 2 2006.281.08:16:12.84#ibcon#*mode == 0, iclass 33, count 2 2006.281.08:16:12.84#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.08:16:12.84#ibcon#[27=AT04-04\r\n] 2006.281.08:16:12.84#ibcon#*before write, iclass 33, count 2 2006.281.08:16:12.84#ibcon#enter sib2, iclass 33, count 2 2006.281.08:16:12.84#ibcon#flushed, iclass 33, count 2 2006.281.08:16:12.84#ibcon#about to write, iclass 33, count 2 2006.281.08:16:12.84#ibcon#wrote, iclass 33, count 2 2006.281.08:16:12.84#ibcon#about to read 3, iclass 33, count 2 2006.281.08:16:12.87#ibcon#read 3, iclass 33, count 2 2006.281.08:16:12.87#ibcon#about to read 4, iclass 33, count 2 2006.281.08:16:12.87#ibcon#read 4, iclass 33, count 2 2006.281.08:16:12.87#ibcon#about to read 5, iclass 33, count 2 2006.281.08:16:12.87#ibcon#read 5, iclass 33, count 2 2006.281.08:16:12.87#ibcon#about to read 6, iclass 33, count 2 2006.281.08:16:12.87#ibcon#read 6, iclass 33, count 2 2006.281.08:16:12.87#ibcon#end of sib2, iclass 33, count 2 2006.281.08:16:12.87#ibcon#*after write, iclass 33, count 2 2006.281.08:16:12.87#ibcon#*before return 0, iclass 33, count 2 2006.281.08:16:12.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:12.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:16:12.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.08:16:12.87#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:12.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:12.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:12.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:12.99#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:16:12.99#ibcon#first serial, iclass 33, count 0 2006.281.08:16:12.99#ibcon#enter sib2, iclass 33, count 0 2006.281.08:16:12.99#ibcon#flushed, iclass 33, count 0 2006.281.08:16:12.99#ibcon#about to write, iclass 33, count 0 2006.281.08:16:12.99#ibcon#wrote, iclass 33, count 0 2006.281.08:16:12.99#ibcon#about to read 3, iclass 33, count 0 2006.281.08:16:13.01#ibcon#read 3, iclass 33, count 0 2006.281.08:16:13.01#ibcon#about to read 4, iclass 33, count 0 2006.281.08:16:13.01#ibcon#read 4, iclass 33, count 0 2006.281.08:16:13.01#ibcon#about to read 5, iclass 33, count 0 2006.281.08:16:13.01#ibcon#read 5, iclass 33, count 0 2006.281.08:16:13.01#ibcon#about to read 6, iclass 33, count 0 2006.281.08:16:13.01#ibcon#read 6, iclass 33, count 0 2006.281.08:16:13.01#ibcon#end of sib2, iclass 33, count 0 2006.281.08:16:13.01#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:16:13.01#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:16:13.01#ibcon#[27=USB\r\n] 2006.281.08:16:13.01#ibcon#*before write, iclass 33, count 0 2006.281.08:16:13.01#ibcon#enter sib2, iclass 33, count 0 2006.281.08:16:13.01#ibcon#flushed, iclass 33, count 0 2006.281.08:16:13.01#ibcon#about to write, iclass 33, count 0 2006.281.08:16:13.01#ibcon#wrote, iclass 33, count 0 2006.281.08:16:13.01#ibcon#about to read 3, iclass 33, count 0 2006.281.08:16:13.05#ibcon#read 3, iclass 33, count 0 2006.281.08:16:13.05#ibcon#about to read 4, iclass 33, count 0 2006.281.08:16:13.05#ibcon#read 4, iclass 33, count 0 2006.281.08:16:13.05#ibcon#about to read 5, iclass 33, count 0 2006.281.08:16:13.05#ibcon#read 5, iclass 33, count 0 2006.281.08:16:13.05#ibcon#about to read 6, iclass 33, count 0 2006.281.08:16:13.05#ibcon#read 6, iclass 33, count 0 2006.281.08:16:13.05#ibcon#end of sib2, iclass 33, count 0 2006.281.08:16:13.05#ibcon#*after write, iclass 33, count 0 2006.281.08:16:13.05#ibcon#*before return 0, iclass 33, count 0 2006.281.08:16:13.05#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:13.05#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:16:13.05#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:16:13.05#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:16:13.05$vc4f8/vblo=5,744.99 2006.281.08:16:13.05#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.08:16:13.05#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.08:16:13.05#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:13.05#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:13.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:13.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:13.05#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:16:13.05#ibcon#first serial, iclass 35, count 0 2006.281.08:16:13.05#ibcon#enter sib2, iclass 35, count 0 2006.281.08:16:13.05#ibcon#flushed, iclass 35, count 0 2006.281.08:16:13.05#ibcon#about to write, iclass 35, count 0 2006.281.08:16:13.05#ibcon#wrote, iclass 35, count 0 2006.281.08:16:13.05#ibcon#about to read 3, iclass 35, count 0 2006.281.08:16:13.07#ibcon#read 3, iclass 35, count 0 2006.281.08:16:13.07#ibcon#about to read 4, iclass 35, count 0 2006.281.08:16:13.07#ibcon#read 4, iclass 35, count 0 2006.281.08:16:13.07#ibcon#about to read 5, iclass 35, count 0 2006.281.08:16:13.07#ibcon#read 5, iclass 35, count 0 2006.281.08:16:13.07#ibcon#about to read 6, iclass 35, count 0 2006.281.08:16:13.07#ibcon#read 6, iclass 35, count 0 2006.281.08:16:13.07#ibcon#end of sib2, iclass 35, count 0 2006.281.08:16:13.07#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:16:13.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:16:13.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:16:13.07#ibcon#*before write, iclass 35, count 0 2006.281.08:16:13.07#ibcon#enter sib2, iclass 35, count 0 2006.281.08:16:13.07#ibcon#flushed, iclass 35, count 0 2006.281.08:16:13.09#ibcon#about to write, iclass 35, count 0 2006.281.08:16:13.09#ibcon#wrote, iclass 35, count 0 2006.281.08:16:13.09#ibcon#about to read 3, iclass 35, count 0 2006.281.08:16:13.13#ibcon#read 3, iclass 35, count 0 2006.281.08:16:13.13#ibcon#about to read 4, iclass 35, count 0 2006.281.08:16:13.13#ibcon#read 4, iclass 35, count 0 2006.281.08:16:13.13#ibcon#about to read 5, iclass 35, count 0 2006.281.08:16:13.13#ibcon#read 5, iclass 35, count 0 2006.281.08:16:13.13#ibcon#about to read 6, iclass 35, count 0 2006.281.08:16:13.13#ibcon#read 6, iclass 35, count 0 2006.281.08:16:13.13#ibcon#end of sib2, iclass 35, count 0 2006.281.08:16:13.13#ibcon#*after write, iclass 35, count 0 2006.281.08:16:13.13#ibcon#*before return 0, iclass 35, count 0 2006.281.08:16:13.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:13.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:16:13.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:16:13.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:16:13.13$vc4f8/vb=5,4 2006.281.08:16:13.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.08:16:13.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.08:16:13.13#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:13.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:13.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:13.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:13.18#ibcon#enter wrdev, iclass 37, count 2 2006.281.08:16:13.18#ibcon#first serial, iclass 37, count 2 2006.281.08:16:13.18#ibcon#enter sib2, iclass 37, count 2 2006.281.08:16:13.18#ibcon#flushed, iclass 37, count 2 2006.281.08:16:13.18#ibcon#about to write, iclass 37, count 2 2006.281.08:16:13.18#ibcon#wrote, iclass 37, count 2 2006.281.08:16:13.18#ibcon#about to read 3, iclass 37, count 2 2006.281.08:16:13.19#ibcon#read 3, iclass 37, count 2 2006.281.08:16:13.19#ibcon#about to read 4, iclass 37, count 2 2006.281.08:16:13.19#ibcon#read 4, iclass 37, count 2 2006.281.08:16:13.19#ibcon#about to read 5, iclass 37, count 2 2006.281.08:16:13.19#ibcon#read 5, iclass 37, count 2 2006.281.08:16:13.19#ibcon#about to read 6, iclass 37, count 2 2006.281.08:16:13.19#ibcon#read 6, iclass 37, count 2 2006.281.08:16:13.19#ibcon#end of sib2, iclass 37, count 2 2006.281.08:16:13.19#ibcon#*mode == 0, iclass 37, count 2 2006.281.08:16:13.19#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.08:16:13.19#ibcon#[27=AT05-04\r\n] 2006.281.08:16:13.19#ibcon#*before write, iclass 37, count 2 2006.281.08:16:13.19#ibcon#enter sib2, iclass 37, count 2 2006.281.08:16:13.19#ibcon#flushed, iclass 37, count 2 2006.281.08:16:13.19#ibcon#about to write, iclass 37, count 2 2006.281.08:16:13.19#ibcon#wrote, iclass 37, count 2 2006.281.08:16:13.19#ibcon#about to read 3, iclass 37, count 2 2006.281.08:16:13.22#ibcon#read 3, iclass 37, count 2 2006.281.08:16:13.22#ibcon#about to read 4, iclass 37, count 2 2006.281.08:16:13.22#ibcon#read 4, iclass 37, count 2 2006.281.08:16:13.22#ibcon#about to read 5, iclass 37, count 2 2006.281.08:16:13.22#ibcon#read 5, iclass 37, count 2 2006.281.08:16:13.22#ibcon#about to read 6, iclass 37, count 2 2006.281.08:16:13.22#ibcon#read 6, iclass 37, count 2 2006.281.08:16:13.22#ibcon#end of sib2, iclass 37, count 2 2006.281.08:16:13.22#ibcon#*after write, iclass 37, count 2 2006.281.08:16:13.22#ibcon#*before return 0, iclass 37, count 2 2006.281.08:16:13.22#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:13.22#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:16:13.22#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.08:16:13.22#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:13.22#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:13.35#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:13.35#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:13.35#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:16:13.35#ibcon#first serial, iclass 37, count 0 2006.281.08:16:13.35#ibcon#enter sib2, iclass 37, count 0 2006.281.08:16:13.35#ibcon#flushed, iclass 37, count 0 2006.281.08:16:13.35#ibcon#about to write, iclass 37, count 0 2006.281.08:16:13.35#ibcon#wrote, iclass 37, count 0 2006.281.08:16:13.35#ibcon#about to read 3, iclass 37, count 0 2006.281.08:16:13.36#ibcon#read 3, iclass 37, count 0 2006.281.08:16:13.36#ibcon#about to read 4, iclass 37, count 0 2006.281.08:16:13.36#ibcon#read 4, iclass 37, count 0 2006.281.08:16:13.36#ibcon#about to read 5, iclass 37, count 0 2006.281.08:16:13.36#ibcon#read 5, iclass 37, count 0 2006.281.08:16:13.36#ibcon#about to read 6, iclass 37, count 0 2006.281.08:16:13.36#ibcon#read 6, iclass 37, count 0 2006.281.08:16:13.36#ibcon#end of sib2, iclass 37, count 0 2006.281.08:16:13.36#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:16:13.36#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:16:13.36#ibcon#[27=USB\r\n] 2006.281.08:16:13.36#ibcon#*before write, iclass 37, count 0 2006.281.08:16:13.36#ibcon#enter sib2, iclass 37, count 0 2006.281.08:16:13.36#ibcon#flushed, iclass 37, count 0 2006.281.08:16:13.36#ibcon#about to write, iclass 37, count 0 2006.281.08:16:13.36#ibcon#wrote, iclass 37, count 0 2006.281.08:16:13.36#ibcon#about to read 3, iclass 37, count 0 2006.281.08:16:13.39#ibcon#read 3, iclass 37, count 0 2006.281.08:16:13.39#ibcon#about to read 4, iclass 37, count 0 2006.281.08:16:13.39#ibcon#read 4, iclass 37, count 0 2006.281.08:16:13.39#ibcon#about to read 5, iclass 37, count 0 2006.281.08:16:13.39#ibcon#read 5, iclass 37, count 0 2006.281.08:16:13.39#ibcon#about to read 6, iclass 37, count 0 2006.281.08:16:13.39#ibcon#read 6, iclass 37, count 0 2006.281.08:16:13.39#ibcon#end of sib2, iclass 37, count 0 2006.281.08:16:13.39#ibcon#*after write, iclass 37, count 0 2006.281.08:16:13.39#ibcon#*before return 0, iclass 37, count 0 2006.281.08:16:13.39#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:13.39#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:16:13.39#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:16:13.39#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:16:13.39$vc4f8/vblo=6,752.99 2006.281.08:16:13.39#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:16:13.39#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:16:13.39#ibcon#ireg 17 cls_cnt 0 2006.281.08:16:13.39#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:13.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:13.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:13.39#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:16:13.39#ibcon#first serial, iclass 39, count 0 2006.281.08:16:13.39#ibcon#enter sib2, iclass 39, count 0 2006.281.08:16:13.39#ibcon#flushed, iclass 39, count 0 2006.281.08:16:13.39#ibcon#about to write, iclass 39, count 0 2006.281.08:16:13.39#ibcon#wrote, iclass 39, count 0 2006.281.08:16:13.39#ibcon#about to read 3, iclass 39, count 0 2006.281.08:16:13.41#ibcon#read 3, iclass 39, count 0 2006.281.08:16:13.41#ibcon#about to read 4, iclass 39, count 0 2006.281.08:16:13.41#ibcon#read 4, iclass 39, count 0 2006.281.08:16:13.41#ibcon#about to read 5, iclass 39, count 0 2006.281.08:16:13.41#ibcon#read 5, iclass 39, count 0 2006.281.08:16:13.41#ibcon#about to read 6, iclass 39, count 0 2006.281.08:16:13.41#ibcon#read 6, iclass 39, count 0 2006.281.08:16:13.41#ibcon#end of sib2, iclass 39, count 0 2006.281.08:16:13.41#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:16:13.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:16:13.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:16:13.41#ibcon#*before write, iclass 39, count 0 2006.281.08:16:13.41#ibcon#enter sib2, iclass 39, count 0 2006.281.08:16:13.41#ibcon#flushed, iclass 39, count 0 2006.281.08:16:13.41#ibcon#about to write, iclass 39, count 0 2006.281.08:16:13.41#ibcon#wrote, iclass 39, count 0 2006.281.08:16:13.41#ibcon#about to read 3, iclass 39, count 0 2006.281.08:16:13.46#ibcon#read 3, iclass 39, count 0 2006.281.08:16:13.46#ibcon#about to read 4, iclass 39, count 0 2006.281.08:16:13.46#ibcon#read 4, iclass 39, count 0 2006.281.08:16:13.46#ibcon#about to read 5, iclass 39, count 0 2006.281.08:16:13.46#ibcon#read 5, iclass 39, count 0 2006.281.08:16:13.46#ibcon#about to read 6, iclass 39, count 0 2006.281.08:16:13.46#ibcon#read 6, iclass 39, count 0 2006.281.08:16:13.46#ibcon#end of sib2, iclass 39, count 0 2006.281.08:16:13.46#ibcon#*after write, iclass 39, count 0 2006.281.08:16:13.46#ibcon#*before return 0, iclass 39, count 0 2006.281.08:16:13.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:13.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:16:13.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:16:13.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:16:13.46$vc4f8/vb=6,4 2006.281.08:16:13.46#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.08:16:13.46#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.08:16:13.46#ibcon#ireg 11 cls_cnt 2 2006.281.08:16:13.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:13.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:13.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:13.50#ibcon#enter wrdev, iclass 3, count 2 2006.281.08:16:13.50#ibcon#first serial, iclass 3, count 2 2006.281.08:16:13.50#ibcon#enter sib2, iclass 3, count 2 2006.281.08:16:13.50#ibcon#flushed, iclass 3, count 2 2006.281.08:16:13.50#ibcon#about to write, iclass 3, count 2 2006.281.08:16:13.50#ibcon#wrote, iclass 3, count 2 2006.281.08:16:13.50#ibcon#about to read 3, iclass 3, count 2 2006.281.08:16:13.53#ibcon#read 3, iclass 3, count 2 2006.281.08:16:13.53#ibcon#about to read 4, iclass 3, count 2 2006.281.08:16:13.53#ibcon#read 4, iclass 3, count 2 2006.281.08:16:13.53#ibcon#about to read 5, iclass 3, count 2 2006.281.08:16:13.53#ibcon#read 5, iclass 3, count 2 2006.281.08:16:13.53#ibcon#about to read 6, iclass 3, count 2 2006.281.08:16:13.53#ibcon#read 6, iclass 3, count 2 2006.281.08:16:13.53#ibcon#end of sib2, iclass 3, count 2 2006.281.08:16:13.53#ibcon#*mode == 0, iclass 3, count 2 2006.281.08:16:13.53#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.08:16:13.53#ibcon#[27=AT06-04\r\n] 2006.281.08:16:13.53#ibcon#*before write, iclass 3, count 2 2006.281.08:16:13.53#ibcon#enter sib2, iclass 3, count 2 2006.281.08:16:13.53#ibcon#flushed, iclass 3, count 2 2006.281.08:16:13.53#ibcon#about to write, iclass 3, count 2 2006.281.08:16:13.53#ibcon#wrote, iclass 3, count 2 2006.281.08:16:13.53#ibcon#about to read 3, iclass 3, count 2 2006.281.08:16:13.55#ibcon#read 3, iclass 3, count 2 2006.281.08:16:13.55#ibcon#about to read 4, iclass 3, count 2 2006.281.08:16:13.55#ibcon#read 4, iclass 3, count 2 2006.281.08:16:13.55#ibcon#about to read 5, iclass 3, count 2 2006.281.08:16:13.55#ibcon#read 5, iclass 3, count 2 2006.281.08:16:13.55#ibcon#about to read 6, iclass 3, count 2 2006.281.08:16:13.55#ibcon#read 6, iclass 3, count 2 2006.281.08:16:13.55#ibcon#end of sib2, iclass 3, count 2 2006.281.08:16:13.55#ibcon#*after write, iclass 3, count 2 2006.281.08:16:13.55#ibcon#*before return 0, iclass 3, count 2 2006.281.08:16:13.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:13.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:16:13.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.08:16:13.55#ibcon#ireg 7 cls_cnt 0 2006.281.08:16:13.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:13.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:13.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:13.67#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:16:13.67#ibcon#first serial, iclass 3, count 0 2006.281.08:16:13.67#ibcon#enter sib2, iclass 3, count 0 2006.281.08:16:13.67#ibcon#flushed, iclass 3, count 0 2006.281.08:16:13.67#ibcon#about to write, iclass 3, count 0 2006.281.08:16:13.67#ibcon#wrote, iclass 3, count 0 2006.281.08:16:13.67#ibcon#about to read 3, iclass 3, count 0 2006.281.08:16:13.69#ibcon#read 3, iclass 3, count 0 2006.281.08:16:13.69#ibcon#about to read 4, iclass 3, count 0 2006.281.08:16:13.69#ibcon#read 4, iclass 3, count 0 2006.281.08:16:13.69#ibcon#about to read 5, iclass 3, count 0 2006.281.08:16:13.69#ibcon#read 5, iclass 3, count 0 2006.281.08:16:13.69#ibcon#about to read 6, iclass 3, count 0 2006.281.08:16:13.69#ibcon#read 6, iclass 3, count 0 2006.281.08:16:13.69#ibcon#end of sib2, iclass 3, count 0 2006.281.08:16:13.69#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:16:13.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:16:13.69#ibcon#[27=USB\r\n] 2006.281.08:16:13.69#ibcon#*before write, iclass 3, count 0 2006.281.08:16:13.69#ibcon#enter sib2, iclass 3, count 0 2006.281.08:16:13.69#ibcon#flushed, iclass 3, count 0 2006.281.08:16:13.69#ibcon#about to write, iclass 3, count 0 2006.281.08:16:13.69#ibcon#wrote, iclass 3, count 0 2006.281.08:16:13.69#ibcon#about to read 3, iclass 3, count 0 2006.281.08:16:13.73#ibcon#read 3, iclass 3, count 0 2006.281.08:16:13.73#ibcon#about to read 4, iclass 3, count 0 2006.281.08:16:13.73#ibcon#read 4, iclass 3, count 0 2006.281.08:16:13.73#ibcon#about to read 5, iclass 3, count 0 2006.281.08:16:13.73#ibcon#read 5, iclass 3, count 0 2006.281.08:16:13.73#ibcon#about to read 6, iclass 3, count 0 2006.281.08:16:13.73#ibcon#read 6, iclass 3, count 0 2006.281.08:16:13.73#ibcon#end of sib2, iclass 3, count 0 2006.281.08:16:13.73#ibcon#*after write, iclass 3, count 0 2006.281.08:16:13.73#ibcon#*before return 0, iclass 3, count 0 2006.281.08:16:13.73#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:13.73#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:16:13.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:16:13.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:16:13.73$vc4f8/vabw=wide 2006.281.08:16:13.73#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.08:16:13.73#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.08:16:13.73#ibcon#ireg 8 cls_cnt 0 2006.281.08:16:13.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:13.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:13.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:13.73#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:16:13.73#ibcon#first serial, iclass 5, count 0 2006.281.08:16:13.73#ibcon#enter sib2, iclass 5, count 0 2006.281.08:16:13.73#ibcon#flushed, iclass 5, count 0 2006.281.08:16:13.73#ibcon#about to write, iclass 5, count 0 2006.281.08:16:13.73#ibcon#wrote, iclass 5, count 0 2006.281.08:16:13.73#ibcon#about to read 3, iclass 5, count 0 2006.281.08:16:13.74#ibcon#read 3, iclass 5, count 0 2006.281.08:16:13.74#ibcon#about to read 4, iclass 5, count 0 2006.281.08:16:13.74#ibcon#read 4, iclass 5, count 0 2006.281.08:16:13.74#ibcon#about to read 5, iclass 5, count 0 2006.281.08:16:13.74#ibcon#read 5, iclass 5, count 0 2006.281.08:16:13.74#ibcon#about to read 6, iclass 5, count 0 2006.281.08:16:13.74#ibcon#read 6, iclass 5, count 0 2006.281.08:16:13.74#ibcon#end of sib2, iclass 5, count 0 2006.281.08:16:13.74#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:16:13.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:16:13.76#ibcon#[25=BW32\r\n] 2006.281.08:16:13.76#ibcon#*before write, iclass 5, count 0 2006.281.08:16:13.76#ibcon#enter sib2, iclass 5, count 0 2006.281.08:16:13.76#ibcon#flushed, iclass 5, count 0 2006.281.08:16:13.76#ibcon#about to write, iclass 5, count 0 2006.281.08:16:13.77#ibcon#wrote, iclass 5, count 0 2006.281.08:16:13.77#ibcon#about to read 3, iclass 5, count 0 2006.281.08:16:13.79#ibcon#read 3, iclass 5, count 0 2006.281.08:16:13.79#ibcon#about to read 4, iclass 5, count 0 2006.281.08:16:13.79#ibcon#read 4, iclass 5, count 0 2006.281.08:16:13.79#ibcon#about to read 5, iclass 5, count 0 2006.281.08:16:13.79#ibcon#read 5, iclass 5, count 0 2006.281.08:16:13.79#ibcon#about to read 6, iclass 5, count 0 2006.281.08:16:13.79#ibcon#read 6, iclass 5, count 0 2006.281.08:16:13.79#ibcon#end of sib2, iclass 5, count 0 2006.281.08:16:13.79#ibcon#*after write, iclass 5, count 0 2006.281.08:16:13.79#ibcon#*before return 0, iclass 5, count 0 2006.281.08:16:13.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:13.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:16:13.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:16:13.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:16:13.79$vc4f8/vbbw=wide 2006.281.08:16:13.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.281.08:16:13.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.281.08:16:13.79#ibcon#ireg 8 cls_cnt 0 2006.281.08:16:13.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:16:13.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:16:13.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:16:13.86#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:16:13.86#ibcon#first serial, iclass 7, count 0 2006.281.08:16:13.86#ibcon#enter sib2, iclass 7, count 0 2006.281.08:16:13.86#ibcon#flushed, iclass 7, count 0 2006.281.08:16:13.86#ibcon#about to write, iclass 7, count 0 2006.281.08:16:13.86#ibcon#wrote, iclass 7, count 0 2006.281.08:16:13.86#ibcon#about to read 3, iclass 7, count 0 2006.281.08:16:13.87#ibcon#read 3, iclass 7, count 0 2006.281.08:16:13.87#ibcon#about to read 4, iclass 7, count 0 2006.281.08:16:13.87#ibcon#read 4, iclass 7, count 0 2006.281.08:16:13.87#ibcon#about to read 5, iclass 7, count 0 2006.281.08:16:13.87#ibcon#read 5, iclass 7, count 0 2006.281.08:16:13.87#ibcon#about to read 6, iclass 7, count 0 2006.281.08:16:13.87#ibcon#read 6, iclass 7, count 0 2006.281.08:16:13.87#ibcon#end of sib2, iclass 7, count 0 2006.281.08:16:13.87#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:16:13.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:16:13.87#ibcon#[27=BW32\r\n] 2006.281.08:16:13.87#ibcon#*before write, iclass 7, count 0 2006.281.08:16:13.87#ibcon#enter sib2, iclass 7, count 0 2006.281.08:16:13.87#ibcon#flushed, iclass 7, count 0 2006.281.08:16:13.87#ibcon#about to write, iclass 7, count 0 2006.281.08:16:13.87#ibcon#wrote, iclass 7, count 0 2006.281.08:16:13.87#ibcon#about to read 3, iclass 7, count 0 2006.281.08:16:13.90#ibcon#read 3, iclass 7, count 0 2006.281.08:16:13.90#ibcon#about to read 4, iclass 7, count 0 2006.281.08:16:13.90#ibcon#read 4, iclass 7, count 0 2006.281.08:16:13.90#ibcon#about to read 5, iclass 7, count 0 2006.281.08:16:13.90#ibcon#read 5, iclass 7, count 0 2006.281.08:16:13.90#ibcon#about to read 6, iclass 7, count 0 2006.281.08:16:13.90#ibcon#read 6, iclass 7, count 0 2006.281.08:16:13.90#ibcon#end of sib2, iclass 7, count 0 2006.281.08:16:13.90#ibcon#*after write, iclass 7, count 0 2006.281.08:16:13.90#ibcon#*before return 0, iclass 7, count 0 2006.281.08:16:13.90#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:16:13.90#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.281.08:16:13.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:16:13.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:16:13.90$4f8m12a/ifd4f 2006.281.08:16:13.90$ifd4f/lo= 2006.281.08:16:13.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:16:13.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:16:13.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:16:13.90$ifd4f/patch= 2006.281.08:16:13.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:16:13.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:16:13.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:16:13.91$4f8m12a/"form=m,16.000,1:2 2006.281.08:16:13.91$4f8m12a/"tpicd 2006.281.08:16:13.91$4f8m12a/echo=off 2006.281.08:16:13.91$4f8m12a/xlog=off 2006.281.08:16:13.91:!2006.281.08:16:40 2006.281.08:16:22.13#trakl#Source acquired 2006.281.08:16:22.13#flagr#flagr/antenna,acquired 2006.281.08:16:40.01:preob 2006.281.08:16:41.13/onsource/TRACKING 2006.281.08:16:41.13:!2006.281.08:16:50 2006.281.08:16:48.13#trakl#Off source 2006.281.08:16:48.13?ERROR st -7 Antenna off-source! 2006.281.08:16:48.13#trakl#az 293.623 el 38.457 azerr*cos(el) -0.0008 elerr -0.0166 2006.281.08:16:48.13#flagr#flagr/antenna,off-source 2006.281.08:16:50.00:data_valid=on 2006.281.08:16:50.00:midob 2006.281.08:16:50.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:16:50.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:16:50.14/onsource/SLEWING 2006.281.08:16:50.14/wx/20.06,1001.7,53 2006.281.08:16:50.27/cable/+6.4883E-03 2006.281.08:16:51.36/va/01,07,usb,yes,32,34 2006.281.08:16:51.36/va/02,06,usb,yes,30,31 2006.281.08:16:51.36/va/03,06,usb,yes,28,28 2006.281.08:16:51.36/va/04,06,usb,yes,31,33 2006.281.08:16:51.36/va/05,07,usb,yes,30,32 2006.281.08:16:51.36/va/06,06,usb,yes,29,29 2006.281.08:16:51.36/va/07,06,usb,yes,29,29 2006.281.08:16:51.36/va/08,06,usb,yes,31,31 2006.281.08:16:51.59/valo/01,532.99,yes,locked 2006.281.08:16:51.59/valo/02,572.99,yes,locked 2006.281.08:16:51.59/valo/03,672.99,yes,locked 2006.281.08:16:51.59/valo/04,832.99,yes,locked 2006.281.08:16:51.59/valo/05,652.99,yes,locked 2006.281.08:16:51.59/valo/06,772.99,yes,locked 2006.281.08:16:51.59/valo/07,832.99,yes,locked 2006.281.08:16:51.59/valo/08,852.99,yes,locked 2006.281.08:16:52.68/vb/01,04,usb,yes,30,29 2006.281.08:16:52.68/vb/02,05,usb,yes,28,30 2006.281.08:16:52.68/vb/03,04,usb,yes,29,32 2006.281.08:16:52.68/vb/04,04,usb,yes,29,29 2006.281.08:16:52.68/vb/05,04,usb,yes,27,32 2006.281.08:16:52.68/vb/06,04,usb,yes,28,31 2006.281.08:16:52.68/vb/07,04,usb,yes,31,31 2006.281.08:16:52.68/vb/08,04,usb,yes,28,32 2006.281.08:16:52.91/vblo/01,632.99,yes,locked 2006.281.08:16:52.91/vblo/02,640.99,yes,locked 2006.281.08:16:52.91/vblo/03,656.99,yes,locked 2006.281.08:16:52.91/vblo/04,712.99,yes,locked 2006.281.08:16:52.91/vblo/05,744.99,yes,locked 2006.281.08:16:52.91/vblo/06,752.99,yes,locked 2006.281.08:16:52.91/vblo/07,734.99,yes,locked 2006.281.08:16:52.91/vblo/08,744.99,yes,locked 2006.281.08:16:53.06/vabw/8 2006.281.08:16:53.21/vbbw/8 2006.281.08:16:53.30/xfe/off,on,12.0 2006.281.08:16:53.68/ifatt/23,28,28,28 2006.281.08:16:54.07/fmout-gps/S +3.11E-07 2006.281.08:16:54.09:!2006.281.08:17:50 2006.281.08:16:54.14#trakl#Source re-acquired 2006.281.08:16:55.14#flagr#flagr/antenna,re-acquired 2006.281.08:17:50.01:data_valid=off 2006.281.08:17:50.01:postob 2006.281.08:17:50.23/cable/+6.4880E-03 2006.281.08:17:50.23/wx/20.04,1001.8,52 2006.281.08:17:51.07/fmout-gps/S +3.11E-07 2006.281.08:17:51.07:scan_name=281-0819,k06281,60 2006.281.08:17:51.07:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.281.08:17:51.14#flagr#flagr/antenna,new-source 2006.281.08:17:52.14#trakl#Off source 2006.281.08:17:52.14?ERROR st -7 Antenna off-source! 2006.281.08:17:52.14#trakl#az 293.712 el 38.259 azerr*cos(el) 0.0040 elerr -0.0348 2006.281.08:17:52.14:checkk5 2006.281.08:17:52.61/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:17:53.02/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:17:53.45/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:17:53.89/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:17:54.30/chk_obsdata//k5ts1/T2810816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:17:54.74/chk_obsdata//k5ts2/T2810816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:17:55.18/chk_obsdata//k5ts3/T2810816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:17:55.59/chk_obsdata//k5ts4/T2810816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:17:56.35/k5log//k5ts1_log_newline 2006.281.08:17:57.17/k5log//k5ts2_log_newline 2006.281.08:17:58.04/k5log//k5ts3_log_newline 2006.281.08:17:58.86/k5log//k5ts4_log_newline 2006.281.08:17:58.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:17:58.89:4f8m12a=3 2006.281.08:17:58.89$4f8m12a/echo=on 2006.281.08:17:58.89$4f8m12a/pcalon 2006.281.08:17:58.89$pcalon/"no phase cal control is implemented here 2006.281.08:17:58.89$4f8m12a/"tpicd=stop 2006.281.08:17:58.89$4f8m12a/vc4f8 2006.281.08:17:58.89$vc4f8/valo=1,532.99 2006.281.08:17:58.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.08:17:58.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.08:17:58.89#ibcon#ireg 17 cls_cnt 0 2006.281.08:17:58.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:17:58.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:17:58.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:17:58.89#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:17:58.89#ibcon#first serial, iclass 24, count 0 2006.281.08:17:58.89#ibcon#enter sib2, iclass 24, count 0 2006.281.08:17:58.89#ibcon#flushed, iclass 24, count 0 2006.281.08:17:58.89#ibcon#about to write, iclass 24, count 0 2006.281.08:17:58.89#ibcon#wrote, iclass 24, count 0 2006.281.08:17:58.89#ibcon#about to read 3, iclass 24, count 0 2006.281.08:17:58.91#ibcon#read 3, iclass 24, count 0 2006.281.08:17:58.91#ibcon#about to read 4, iclass 24, count 0 2006.281.08:17:58.91#ibcon#read 4, iclass 24, count 0 2006.281.08:17:58.91#ibcon#about to read 5, iclass 24, count 0 2006.281.08:17:58.91#ibcon#read 5, iclass 24, count 0 2006.281.08:17:58.91#ibcon#about to read 6, iclass 24, count 0 2006.281.08:17:58.91#ibcon#read 6, iclass 24, count 0 2006.281.08:17:58.91#ibcon#end of sib2, iclass 24, count 0 2006.281.08:17:58.91#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:17:58.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:17:58.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:17:58.91#ibcon#*before write, iclass 24, count 0 2006.281.08:17:58.91#ibcon#enter sib2, iclass 24, count 0 2006.281.08:17:58.91#ibcon#flushed, iclass 24, count 0 2006.281.08:17:58.91#ibcon#about to write, iclass 24, count 0 2006.281.08:17:58.91#ibcon#wrote, iclass 24, count 0 2006.281.08:17:58.91#ibcon#about to read 3, iclass 24, count 0 2006.281.08:17:58.96#ibcon#read 3, iclass 24, count 0 2006.281.08:17:58.96#ibcon#about to read 4, iclass 24, count 0 2006.281.08:17:58.96#ibcon#read 4, iclass 24, count 0 2006.281.08:17:58.96#ibcon#about to read 5, iclass 24, count 0 2006.281.08:17:58.96#ibcon#read 5, iclass 24, count 0 2006.281.08:17:58.96#ibcon#about to read 6, iclass 24, count 0 2006.281.08:17:58.96#ibcon#read 6, iclass 24, count 0 2006.281.08:17:58.96#ibcon#end of sib2, iclass 24, count 0 2006.281.08:17:58.96#ibcon#*after write, iclass 24, count 0 2006.281.08:17:58.96#ibcon#*before return 0, iclass 24, count 0 2006.281.08:17:58.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:17:58.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:17:58.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:17:58.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:17:58.96$vc4f8/va=1,7 2006.281.08:17:58.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.08:17:58.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.08:17:58.97#ibcon#ireg 11 cls_cnt 2 2006.281.08:17:58.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:17:58.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:17:58.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:17:58.97#ibcon#enter wrdev, iclass 26, count 2 2006.281.08:17:58.97#ibcon#first serial, iclass 26, count 2 2006.281.08:17:58.97#ibcon#enter sib2, iclass 26, count 2 2006.281.08:17:58.97#ibcon#flushed, iclass 26, count 2 2006.281.08:17:58.97#ibcon#about to write, iclass 26, count 2 2006.281.08:17:58.97#ibcon#wrote, iclass 26, count 2 2006.281.08:17:58.97#ibcon#about to read 3, iclass 26, count 2 2006.281.08:17:58.98#ibcon#read 3, iclass 26, count 2 2006.281.08:17:58.98#ibcon#about to read 4, iclass 26, count 2 2006.281.08:17:58.98#ibcon#read 4, iclass 26, count 2 2006.281.08:17:58.98#ibcon#about to read 5, iclass 26, count 2 2006.281.08:17:58.98#ibcon#read 5, iclass 26, count 2 2006.281.08:17:58.98#ibcon#about to read 6, iclass 26, count 2 2006.281.08:17:58.98#ibcon#read 6, iclass 26, count 2 2006.281.08:17:58.98#ibcon#end of sib2, iclass 26, count 2 2006.281.08:17:58.98#ibcon#*mode == 0, iclass 26, count 2 2006.281.08:17:58.98#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.08:17:58.98#ibcon#[25=AT01-07\r\n] 2006.281.08:17:58.98#ibcon#*before write, iclass 26, count 2 2006.281.08:17:58.98#ibcon#enter sib2, iclass 26, count 2 2006.281.08:17:58.98#ibcon#flushed, iclass 26, count 2 2006.281.08:17:58.98#ibcon#about to write, iclass 26, count 2 2006.281.08:17:58.98#ibcon#wrote, iclass 26, count 2 2006.281.08:17:58.98#ibcon#about to read 3, iclass 26, count 2 2006.281.08:17:59.01#ibcon#read 3, iclass 26, count 2 2006.281.08:17:59.01#ibcon#about to read 4, iclass 26, count 2 2006.281.08:17:59.01#ibcon#read 4, iclass 26, count 2 2006.281.08:17:59.01#ibcon#about to read 5, iclass 26, count 2 2006.281.08:17:59.01#ibcon#read 5, iclass 26, count 2 2006.281.08:17:59.01#ibcon#about to read 6, iclass 26, count 2 2006.281.08:17:59.01#ibcon#read 6, iclass 26, count 2 2006.281.08:17:59.01#ibcon#end of sib2, iclass 26, count 2 2006.281.08:17:59.01#ibcon#*after write, iclass 26, count 2 2006.281.08:17:59.01#ibcon#*before return 0, iclass 26, count 2 2006.281.08:17:59.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:17:59.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:17:59.01#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.08:17:59.01#ibcon#ireg 7 cls_cnt 0 2006.281.08:17:59.01#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:17:59.13#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:17:59.13#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:17:59.13#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:17:59.13#ibcon#first serial, iclass 26, count 0 2006.281.08:17:59.13#ibcon#enter sib2, iclass 26, count 0 2006.281.08:17:59.13#ibcon#flushed, iclass 26, count 0 2006.281.08:17:59.13#ibcon#about to write, iclass 26, count 0 2006.281.08:17:59.13#ibcon#wrote, iclass 26, count 0 2006.281.08:17:59.13#ibcon#about to read 3, iclass 26, count 0 2006.281.08:17:59.16#ibcon#read 3, iclass 26, count 0 2006.281.08:17:59.16#ibcon#about to read 4, iclass 26, count 0 2006.281.08:17:59.16#ibcon#read 4, iclass 26, count 0 2006.281.08:17:59.16#ibcon#about to read 5, iclass 26, count 0 2006.281.08:17:59.16#ibcon#read 5, iclass 26, count 0 2006.281.08:17:59.16#ibcon#about to read 6, iclass 26, count 0 2006.281.08:17:59.16#ibcon#read 6, iclass 26, count 0 2006.281.08:17:59.16#ibcon#end of sib2, iclass 26, count 0 2006.281.08:17:59.16#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:17:59.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:17:59.16#ibcon#[25=USB\r\n] 2006.281.08:17:59.16#ibcon#*before write, iclass 26, count 0 2006.281.08:17:59.16#ibcon#enter sib2, iclass 26, count 0 2006.281.08:17:59.16#ibcon#flushed, iclass 26, count 0 2006.281.08:17:59.16#ibcon#about to write, iclass 26, count 0 2006.281.08:17:59.16#ibcon#wrote, iclass 26, count 0 2006.281.08:17:59.16#ibcon#about to read 3, iclass 26, count 0 2006.281.08:17:59.18#ibcon#read 3, iclass 26, count 0 2006.281.08:17:59.18#ibcon#about to read 4, iclass 26, count 0 2006.281.08:17:59.18#ibcon#read 4, iclass 26, count 0 2006.281.08:17:59.18#ibcon#about to read 5, iclass 26, count 0 2006.281.08:17:59.18#ibcon#read 5, iclass 26, count 0 2006.281.08:17:59.18#ibcon#about to read 6, iclass 26, count 0 2006.281.08:17:59.18#ibcon#read 6, iclass 26, count 0 2006.281.08:17:59.18#ibcon#end of sib2, iclass 26, count 0 2006.281.08:17:59.18#ibcon#*after write, iclass 26, count 0 2006.281.08:17:59.18#ibcon#*before return 0, iclass 26, count 0 2006.281.08:17:59.18#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:17:59.18#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:17:59.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:17:59.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:17:59.18$vc4f8/valo=2,572.99 2006.281.08:17:59.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:17:59.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:17:59.18#ibcon#ireg 17 cls_cnt 0 2006.281.08:17:59.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:17:59.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:17:59.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:17:59.18#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:17:59.18#ibcon#first serial, iclass 28, count 0 2006.281.08:17:59.18#ibcon#enter sib2, iclass 28, count 0 2006.281.08:17:59.18#ibcon#flushed, iclass 28, count 0 2006.281.08:17:59.18#ibcon#about to write, iclass 28, count 0 2006.281.08:17:59.18#ibcon#wrote, iclass 28, count 0 2006.281.08:17:59.18#ibcon#about to read 3, iclass 28, count 0 2006.281.08:17:59.20#ibcon#read 3, iclass 28, count 0 2006.281.08:17:59.20#ibcon#about to read 4, iclass 28, count 0 2006.281.08:17:59.20#ibcon#read 4, iclass 28, count 0 2006.281.08:17:59.20#ibcon#about to read 5, iclass 28, count 0 2006.281.08:17:59.20#ibcon#read 5, iclass 28, count 0 2006.281.08:17:59.20#ibcon#about to read 6, iclass 28, count 0 2006.281.08:17:59.20#ibcon#read 6, iclass 28, count 0 2006.281.08:17:59.20#ibcon#end of sib2, iclass 28, count 0 2006.281.08:17:59.20#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:17:59.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:17:59.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:17:59.20#ibcon#*before write, iclass 28, count 0 2006.281.08:17:59.20#ibcon#enter sib2, iclass 28, count 0 2006.281.08:17:59.20#ibcon#flushed, iclass 28, count 0 2006.281.08:17:59.20#ibcon#about to write, iclass 28, count 0 2006.281.08:17:59.20#ibcon#wrote, iclass 28, count 0 2006.281.08:17:59.20#ibcon#about to read 3, iclass 28, count 0 2006.281.08:17:59.24#ibcon#read 3, iclass 28, count 0 2006.281.08:17:59.24#ibcon#about to read 4, iclass 28, count 0 2006.281.08:17:59.24#ibcon#read 4, iclass 28, count 0 2006.281.08:17:59.24#ibcon#about to read 5, iclass 28, count 0 2006.281.08:17:59.24#ibcon#read 5, iclass 28, count 0 2006.281.08:17:59.24#ibcon#about to read 6, iclass 28, count 0 2006.281.08:17:59.24#ibcon#read 6, iclass 28, count 0 2006.281.08:17:59.24#ibcon#end of sib2, iclass 28, count 0 2006.281.08:17:59.24#ibcon#*after write, iclass 28, count 0 2006.281.08:17:59.24#ibcon#*before return 0, iclass 28, count 0 2006.281.08:17:59.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:17:59.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:17:59.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:17:59.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:17:59.24$vc4f8/va=2,6 2006.281.08:17:59.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.08:17:59.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.08:17:59.24#ibcon#ireg 11 cls_cnt 2 2006.281.08:17:59.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:17:59.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:17:59.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:17:59.31#ibcon#enter wrdev, iclass 30, count 2 2006.281.08:17:59.31#ibcon#first serial, iclass 30, count 2 2006.281.08:17:59.31#ibcon#enter sib2, iclass 30, count 2 2006.281.08:17:59.31#ibcon#flushed, iclass 30, count 2 2006.281.08:17:59.31#ibcon#about to write, iclass 30, count 2 2006.281.08:17:59.31#ibcon#wrote, iclass 30, count 2 2006.281.08:17:59.31#ibcon#about to read 3, iclass 30, count 2 2006.281.08:17:59.33#ibcon#read 3, iclass 30, count 2 2006.281.08:17:59.33#ibcon#about to read 4, iclass 30, count 2 2006.281.08:17:59.33#ibcon#read 4, iclass 30, count 2 2006.281.08:17:59.33#ibcon#about to read 5, iclass 30, count 2 2006.281.08:17:59.33#ibcon#read 5, iclass 30, count 2 2006.281.08:17:59.33#ibcon#about to read 6, iclass 30, count 2 2006.281.08:17:59.33#ibcon#read 6, iclass 30, count 2 2006.281.08:17:59.33#ibcon#end of sib2, iclass 30, count 2 2006.281.08:17:59.33#ibcon#*mode == 0, iclass 30, count 2 2006.281.08:17:59.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.08:17:59.33#ibcon#[25=AT02-06\r\n] 2006.281.08:17:59.33#ibcon#*before write, iclass 30, count 2 2006.281.08:17:59.33#ibcon#enter sib2, iclass 30, count 2 2006.281.08:17:59.33#ibcon#flushed, iclass 30, count 2 2006.281.08:17:59.33#ibcon#about to write, iclass 30, count 2 2006.281.08:17:59.33#ibcon#wrote, iclass 30, count 2 2006.281.08:17:59.33#ibcon#about to read 3, iclass 30, count 2 2006.281.08:17:59.35#ibcon#read 3, iclass 30, count 2 2006.281.08:17:59.35#ibcon#about to read 4, iclass 30, count 2 2006.281.08:17:59.35#ibcon#read 4, iclass 30, count 2 2006.281.08:17:59.35#ibcon#about to read 5, iclass 30, count 2 2006.281.08:17:59.35#ibcon#read 5, iclass 30, count 2 2006.281.08:17:59.35#ibcon#about to read 6, iclass 30, count 2 2006.281.08:17:59.35#ibcon#read 6, iclass 30, count 2 2006.281.08:17:59.35#ibcon#end of sib2, iclass 30, count 2 2006.281.08:17:59.35#ibcon#*after write, iclass 30, count 2 2006.281.08:17:59.35#ibcon#*before return 0, iclass 30, count 2 2006.281.08:17:59.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:17:59.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:17:59.35#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.08:17:59.35#ibcon#ireg 7 cls_cnt 0 2006.281.08:17:59.35#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:17:59.47#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:17:59.47#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:17:59.47#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:17:59.47#ibcon#first serial, iclass 30, count 0 2006.281.08:17:59.47#ibcon#enter sib2, iclass 30, count 0 2006.281.08:17:59.47#ibcon#flushed, iclass 30, count 0 2006.281.08:17:59.47#ibcon#about to write, iclass 30, count 0 2006.281.08:17:59.47#ibcon#wrote, iclass 30, count 0 2006.281.08:17:59.47#ibcon#about to read 3, iclass 30, count 0 2006.281.08:17:59.49#ibcon#read 3, iclass 30, count 0 2006.281.08:17:59.49#ibcon#about to read 4, iclass 30, count 0 2006.281.08:17:59.49#ibcon#read 4, iclass 30, count 0 2006.281.08:17:59.49#ibcon#about to read 5, iclass 30, count 0 2006.281.08:17:59.49#ibcon#read 5, iclass 30, count 0 2006.281.08:17:59.49#ibcon#about to read 6, iclass 30, count 0 2006.281.08:17:59.49#ibcon#read 6, iclass 30, count 0 2006.281.08:17:59.49#ibcon#end of sib2, iclass 30, count 0 2006.281.08:17:59.49#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:17:59.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:17:59.49#ibcon#[25=USB\r\n] 2006.281.08:17:59.49#ibcon#*before write, iclass 30, count 0 2006.281.08:17:59.49#ibcon#enter sib2, iclass 30, count 0 2006.281.08:17:59.49#ibcon#flushed, iclass 30, count 0 2006.281.08:17:59.49#ibcon#about to write, iclass 30, count 0 2006.281.08:17:59.49#ibcon#wrote, iclass 30, count 0 2006.281.08:17:59.49#ibcon#about to read 3, iclass 30, count 0 2006.281.08:17:59.53#ibcon#read 3, iclass 30, count 0 2006.281.08:17:59.53#ibcon#about to read 4, iclass 30, count 0 2006.281.08:17:59.53#ibcon#read 4, iclass 30, count 0 2006.281.08:17:59.53#ibcon#about to read 5, iclass 30, count 0 2006.281.08:17:59.53#ibcon#read 5, iclass 30, count 0 2006.281.08:17:59.53#ibcon#about to read 6, iclass 30, count 0 2006.281.08:17:59.53#ibcon#read 6, iclass 30, count 0 2006.281.08:17:59.53#ibcon#end of sib2, iclass 30, count 0 2006.281.08:17:59.53#ibcon#*after write, iclass 30, count 0 2006.281.08:17:59.53#ibcon#*before return 0, iclass 30, count 0 2006.281.08:17:59.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:17:59.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:17:59.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:17:59.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:17:59.53$vc4f8/valo=3,672.99 2006.281.08:17:59.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.08:17:59.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.08:17:59.53#ibcon#ireg 17 cls_cnt 0 2006.281.08:17:59.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:17:59.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:17:59.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:17:59.53#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:17:59.53#ibcon#first serial, iclass 32, count 0 2006.281.08:17:59.53#ibcon#enter sib2, iclass 32, count 0 2006.281.08:17:59.53#ibcon#flushed, iclass 32, count 0 2006.281.08:17:59.53#ibcon#about to write, iclass 32, count 0 2006.281.08:17:59.53#ibcon#wrote, iclass 32, count 0 2006.281.08:17:59.53#ibcon#about to read 3, iclass 32, count 0 2006.281.08:17:59.54#ibcon#read 3, iclass 32, count 0 2006.281.08:17:59.55#ibcon#about to read 4, iclass 32, count 0 2006.281.08:17:59.55#ibcon#read 4, iclass 32, count 0 2006.281.08:17:59.55#ibcon#about to read 5, iclass 32, count 0 2006.281.08:17:59.55#ibcon#read 5, iclass 32, count 0 2006.281.08:17:59.55#ibcon#about to read 6, iclass 32, count 0 2006.281.08:17:59.55#ibcon#read 6, iclass 32, count 0 2006.281.08:17:59.55#ibcon#end of sib2, iclass 32, count 0 2006.281.08:17:59.55#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:17:59.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:17:59.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:17:59.55#ibcon#*before write, iclass 32, count 0 2006.281.08:17:59.55#ibcon#enter sib2, iclass 32, count 0 2006.281.08:17:59.55#ibcon#flushed, iclass 32, count 0 2006.281.08:17:59.55#ibcon#about to write, iclass 32, count 0 2006.281.08:17:59.55#ibcon#wrote, iclass 32, count 0 2006.281.08:17:59.55#ibcon#about to read 3, iclass 32, count 0 2006.281.08:17:59.58#ibcon#read 3, iclass 32, count 0 2006.281.08:17:59.58#ibcon#about to read 4, iclass 32, count 0 2006.281.08:17:59.58#ibcon#read 4, iclass 32, count 0 2006.281.08:17:59.58#ibcon#about to read 5, iclass 32, count 0 2006.281.08:17:59.58#ibcon#read 5, iclass 32, count 0 2006.281.08:17:59.58#ibcon#about to read 6, iclass 32, count 0 2006.281.08:17:59.58#ibcon#read 6, iclass 32, count 0 2006.281.08:17:59.58#ibcon#end of sib2, iclass 32, count 0 2006.281.08:17:59.58#ibcon#*after write, iclass 32, count 0 2006.281.08:17:59.58#ibcon#*before return 0, iclass 32, count 0 2006.281.08:17:59.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:17:59.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:17:59.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:17:59.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:17:59.58$vc4f8/va=3,6 2006.281.08:17:59.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.08:17:59.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.08:17:59.58#ibcon#ireg 11 cls_cnt 2 2006.281.08:17:59.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:17:59.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:17:59.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:17:59.65#ibcon#enter wrdev, iclass 34, count 2 2006.281.08:17:59.65#ibcon#first serial, iclass 34, count 2 2006.281.08:17:59.65#ibcon#enter sib2, iclass 34, count 2 2006.281.08:17:59.65#ibcon#flushed, iclass 34, count 2 2006.281.08:17:59.65#ibcon#about to write, iclass 34, count 2 2006.281.08:17:59.65#ibcon#wrote, iclass 34, count 2 2006.281.08:17:59.65#ibcon#about to read 3, iclass 34, count 2 2006.281.08:17:59.67#ibcon#read 3, iclass 34, count 2 2006.281.08:17:59.67#ibcon#about to read 4, iclass 34, count 2 2006.281.08:17:59.67#ibcon#read 4, iclass 34, count 2 2006.281.08:17:59.67#ibcon#about to read 5, iclass 34, count 2 2006.281.08:17:59.67#ibcon#read 5, iclass 34, count 2 2006.281.08:17:59.67#ibcon#about to read 6, iclass 34, count 2 2006.281.08:17:59.67#ibcon#read 6, iclass 34, count 2 2006.281.08:17:59.67#ibcon#end of sib2, iclass 34, count 2 2006.281.08:17:59.67#ibcon#*mode == 0, iclass 34, count 2 2006.281.08:17:59.67#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.08:17:59.67#ibcon#[25=AT03-06\r\n] 2006.281.08:17:59.67#ibcon#*before write, iclass 34, count 2 2006.281.08:17:59.67#ibcon#enter sib2, iclass 34, count 2 2006.281.08:17:59.67#ibcon#flushed, iclass 34, count 2 2006.281.08:17:59.67#ibcon#about to write, iclass 34, count 2 2006.281.08:17:59.67#ibcon#wrote, iclass 34, count 2 2006.281.08:17:59.67#ibcon#about to read 3, iclass 34, count 2 2006.281.08:17:59.70#ibcon#read 3, iclass 34, count 2 2006.281.08:17:59.70#ibcon#about to read 4, iclass 34, count 2 2006.281.08:17:59.70#ibcon#read 4, iclass 34, count 2 2006.281.08:17:59.70#ibcon#about to read 5, iclass 34, count 2 2006.281.08:17:59.70#ibcon#read 5, iclass 34, count 2 2006.281.08:17:59.70#ibcon#about to read 6, iclass 34, count 2 2006.281.08:17:59.70#ibcon#read 6, iclass 34, count 2 2006.281.08:17:59.70#ibcon#end of sib2, iclass 34, count 2 2006.281.08:17:59.70#ibcon#*after write, iclass 34, count 2 2006.281.08:17:59.70#ibcon#*before return 0, iclass 34, count 2 2006.281.08:17:59.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:17:59.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:17:59.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.08:17:59.70#ibcon#ireg 7 cls_cnt 0 2006.281.08:17:59.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:17:59.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:17:59.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:17:59.82#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:17:59.82#ibcon#first serial, iclass 34, count 0 2006.281.08:17:59.82#ibcon#enter sib2, iclass 34, count 0 2006.281.08:17:59.82#ibcon#flushed, iclass 34, count 0 2006.281.08:17:59.82#ibcon#about to write, iclass 34, count 0 2006.281.08:17:59.82#ibcon#wrote, iclass 34, count 0 2006.281.08:17:59.82#ibcon#about to read 3, iclass 34, count 0 2006.281.08:17:59.84#ibcon#read 3, iclass 34, count 0 2006.281.08:17:59.84#ibcon#about to read 4, iclass 34, count 0 2006.281.08:17:59.84#ibcon#read 4, iclass 34, count 0 2006.281.08:17:59.84#ibcon#about to read 5, iclass 34, count 0 2006.281.08:17:59.84#ibcon#read 5, iclass 34, count 0 2006.281.08:17:59.84#ibcon#about to read 6, iclass 34, count 0 2006.281.08:17:59.84#ibcon#read 6, iclass 34, count 0 2006.281.08:17:59.84#ibcon#end of sib2, iclass 34, count 0 2006.281.08:17:59.84#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:17:59.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:17:59.84#ibcon#[25=USB\r\n] 2006.281.08:17:59.84#ibcon#*before write, iclass 34, count 0 2006.281.08:17:59.84#ibcon#enter sib2, iclass 34, count 0 2006.281.08:17:59.84#ibcon#flushed, iclass 34, count 0 2006.281.08:17:59.84#ibcon#about to write, iclass 34, count 0 2006.281.08:17:59.84#ibcon#wrote, iclass 34, count 0 2006.281.08:17:59.84#ibcon#about to read 3, iclass 34, count 0 2006.281.08:17:59.87#ibcon#read 3, iclass 34, count 0 2006.281.08:17:59.87#ibcon#about to read 4, iclass 34, count 0 2006.281.08:17:59.87#ibcon#read 4, iclass 34, count 0 2006.281.08:17:59.87#ibcon#about to read 5, iclass 34, count 0 2006.281.08:17:59.87#ibcon#read 5, iclass 34, count 0 2006.281.08:17:59.87#ibcon#about to read 6, iclass 34, count 0 2006.281.08:17:59.87#ibcon#read 6, iclass 34, count 0 2006.281.08:17:59.87#ibcon#end of sib2, iclass 34, count 0 2006.281.08:17:59.87#ibcon#*after write, iclass 34, count 0 2006.281.08:17:59.87#ibcon#*before return 0, iclass 34, count 0 2006.281.08:17:59.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:17:59.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:17:59.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:17:59.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:17:59.87$vc4f8/valo=4,832.99 2006.281.08:17:59.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.08:17:59.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.08:17:59.87#ibcon#ireg 17 cls_cnt 0 2006.281.08:17:59.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:17:59.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:17:59.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:17:59.87#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:17:59.87#ibcon#first serial, iclass 36, count 0 2006.281.08:17:59.87#ibcon#enter sib2, iclass 36, count 0 2006.281.08:17:59.87#ibcon#flushed, iclass 36, count 0 2006.281.08:17:59.87#ibcon#about to write, iclass 36, count 0 2006.281.08:17:59.87#ibcon#wrote, iclass 36, count 0 2006.281.08:17:59.87#ibcon#about to read 3, iclass 36, count 0 2006.281.08:17:59.89#ibcon#read 3, iclass 36, count 0 2006.281.08:17:59.89#ibcon#about to read 4, iclass 36, count 0 2006.281.08:17:59.89#ibcon#read 4, iclass 36, count 0 2006.281.08:17:59.89#ibcon#about to read 5, iclass 36, count 0 2006.281.08:17:59.89#ibcon#read 5, iclass 36, count 0 2006.281.08:17:59.89#ibcon#about to read 6, iclass 36, count 0 2006.281.08:17:59.89#ibcon#read 6, iclass 36, count 0 2006.281.08:17:59.89#ibcon#end of sib2, iclass 36, count 0 2006.281.08:17:59.89#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:17:59.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:17:59.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:17:59.89#ibcon#*before write, iclass 36, count 0 2006.281.08:17:59.89#ibcon#enter sib2, iclass 36, count 0 2006.281.08:17:59.89#ibcon#flushed, iclass 36, count 0 2006.281.08:17:59.89#ibcon#about to write, iclass 36, count 0 2006.281.08:17:59.89#ibcon#wrote, iclass 36, count 0 2006.281.08:17:59.89#ibcon#about to read 3, iclass 36, count 0 2006.281.08:17:59.93#ibcon#read 3, iclass 36, count 0 2006.281.08:17:59.93#ibcon#about to read 4, iclass 36, count 0 2006.281.08:17:59.93#ibcon#read 4, iclass 36, count 0 2006.281.08:17:59.93#ibcon#about to read 5, iclass 36, count 0 2006.281.08:17:59.93#ibcon#read 5, iclass 36, count 0 2006.281.08:17:59.93#ibcon#about to read 6, iclass 36, count 0 2006.281.08:17:59.93#ibcon#read 6, iclass 36, count 0 2006.281.08:17:59.93#ibcon#end of sib2, iclass 36, count 0 2006.281.08:17:59.93#ibcon#*after write, iclass 36, count 0 2006.281.08:17:59.93#ibcon#*before return 0, iclass 36, count 0 2006.281.08:17:59.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:17:59.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:17:59.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:17:59.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:17:59.93$vc4f8/va=4,6 2006.281.08:17:59.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.08:17:59.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.08:17:59.93#ibcon#ireg 11 cls_cnt 2 2006.281.08:17:59.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:17:59.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:17:59.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:17:59.99#ibcon#enter wrdev, iclass 38, count 2 2006.281.08:17:59.99#ibcon#first serial, iclass 38, count 2 2006.281.08:17:59.99#ibcon#enter sib2, iclass 38, count 2 2006.281.08:17:59.99#ibcon#flushed, iclass 38, count 2 2006.281.08:17:59.99#ibcon#about to write, iclass 38, count 2 2006.281.08:17:59.99#ibcon#wrote, iclass 38, count 2 2006.281.08:17:59.99#ibcon#about to read 3, iclass 38, count 2 2006.281.08:18:00.02#ibcon#read 3, iclass 38, count 2 2006.281.08:18:00.02#ibcon#about to read 4, iclass 38, count 2 2006.281.08:18:00.02#ibcon#read 4, iclass 38, count 2 2006.281.08:18:00.02#ibcon#about to read 5, iclass 38, count 2 2006.281.08:18:00.02#ibcon#read 5, iclass 38, count 2 2006.281.08:18:00.02#ibcon#about to read 6, iclass 38, count 2 2006.281.08:18:00.02#ibcon#read 6, iclass 38, count 2 2006.281.08:18:00.02#ibcon#end of sib2, iclass 38, count 2 2006.281.08:18:00.02#ibcon#*mode == 0, iclass 38, count 2 2006.281.08:18:00.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.08:18:00.02#ibcon#[25=AT04-06\r\n] 2006.281.08:18:00.02#ibcon#*before write, iclass 38, count 2 2006.281.08:18:00.02#ibcon#enter sib2, iclass 38, count 2 2006.281.08:18:00.02#ibcon#flushed, iclass 38, count 2 2006.281.08:18:00.02#ibcon#about to write, iclass 38, count 2 2006.281.08:18:00.02#ibcon#wrote, iclass 38, count 2 2006.281.08:18:00.02#ibcon#about to read 3, iclass 38, count 2 2006.281.08:18:00.04#ibcon#read 3, iclass 38, count 2 2006.281.08:18:00.04#ibcon#about to read 4, iclass 38, count 2 2006.281.08:18:00.04#ibcon#read 4, iclass 38, count 2 2006.281.08:18:00.04#ibcon#about to read 5, iclass 38, count 2 2006.281.08:18:00.05#ibcon#read 5, iclass 38, count 2 2006.281.08:18:00.05#ibcon#about to read 6, iclass 38, count 2 2006.281.08:18:00.05#ibcon#read 6, iclass 38, count 2 2006.281.08:18:00.05#ibcon#end of sib2, iclass 38, count 2 2006.281.08:18:00.05#ibcon#*after write, iclass 38, count 2 2006.281.08:18:00.05#ibcon#*before return 0, iclass 38, count 2 2006.281.08:18:00.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:00.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:00.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.08:18:00.05#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:00.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:00.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:00.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:00.16#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:18:00.16#ibcon#first serial, iclass 38, count 0 2006.281.08:18:00.16#ibcon#enter sib2, iclass 38, count 0 2006.281.08:18:00.16#ibcon#flushed, iclass 38, count 0 2006.281.08:18:00.16#ibcon#about to write, iclass 38, count 0 2006.281.08:18:00.16#ibcon#wrote, iclass 38, count 0 2006.281.08:18:00.16#ibcon#about to read 3, iclass 38, count 0 2006.281.08:18:00.18#ibcon#read 3, iclass 38, count 0 2006.281.08:18:00.18#ibcon#about to read 4, iclass 38, count 0 2006.281.08:18:00.18#ibcon#read 4, iclass 38, count 0 2006.281.08:18:00.18#ibcon#about to read 5, iclass 38, count 0 2006.281.08:18:00.18#ibcon#read 5, iclass 38, count 0 2006.281.08:18:00.18#ibcon#about to read 6, iclass 38, count 0 2006.281.08:18:00.18#ibcon#read 6, iclass 38, count 0 2006.281.08:18:00.18#ibcon#end of sib2, iclass 38, count 0 2006.281.08:18:00.18#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:18:00.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:18:00.18#ibcon#[25=USB\r\n] 2006.281.08:18:00.18#ibcon#*before write, iclass 38, count 0 2006.281.08:18:00.18#ibcon#enter sib2, iclass 38, count 0 2006.281.08:18:00.18#ibcon#flushed, iclass 38, count 0 2006.281.08:18:00.18#ibcon#about to write, iclass 38, count 0 2006.281.08:18:00.18#ibcon#wrote, iclass 38, count 0 2006.281.08:18:00.18#ibcon#about to read 3, iclass 38, count 0 2006.281.08:18:00.21#ibcon#read 3, iclass 38, count 0 2006.281.08:18:00.21#ibcon#about to read 4, iclass 38, count 0 2006.281.08:18:00.21#ibcon#read 4, iclass 38, count 0 2006.281.08:18:00.21#ibcon#about to read 5, iclass 38, count 0 2006.281.08:18:00.21#ibcon#read 5, iclass 38, count 0 2006.281.08:18:00.21#ibcon#about to read 6, iclass 38, count 0 2006.281.08:18:00.21#ibcon#read 6, iclass 38, count 0 2006.281.08:18:00.21#ibcon#end of sib2, iclass 38, count 0 2006.281.08:18:00.21#ibcon#*after write, iclass 38, count 0 2006.281.08:18:00.21#ibcon#*before return 0, iclass 38, count 0 2006.281.08:18:00.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:00.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:00.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:18:00.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:18:00.21$vc4f8/valo=5,652.99 2006.281.08:18:00.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:18:00.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:18:00.21#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:00.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:00.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:00.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:00.21#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:18:00.21#ibcon#first serial, iclass 40, count 0 2006.281.08:18:00.21#ibcon#enter sib2, iclass 40, count 0 2006.281.08:18:00.21#ibcon#flushed, iclass 40, count 0 2006.281.08:18:00.21#ibcon#about to write, iclass 40, count 0 2006.281.08:18:00.21#ibcon#wrote, iclass 40, count 0 2006.281.08:18:00.21#ibcon#about to read 3, iclass 40, count 0 2006.281.08:18:00.23#ibcon#read 3, iclass 40, count 0 2006.281.08:18:00.23#ibcon#about to read 4, iclass 40, count 0 2006.281.08:18:00.23#ibcon#read 4, iclass 40, count 0 2006.281.08:18:00.23#ibcon#about to read 5, iclass 40, count 0 2006.281.08:18:00.23#ibcon#read 5, iclass 40, count 0 2006.281.08:18:00.23#ibcon#about to read 6, iclass 40, count 0 2006.281.08:18:00.23#ibcon#read 6, iclass 40, count 0 2006.281.08:18:00.23#ibcon#end of sib2, iclass 40, count 0 2006.281.08:18:00.23#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:18:00.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:18:00.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:18:00.25#ibcon#*before write, iclass 40, count 0 2006.281.08:18:00.25#ibcon#enter sib2, iclass 40, count 0 2006.281.08:18:00.25#ibcon#flushed, iclass 40, count 0 2006.281.08:18:00.25#ibcon#about to write, iclass 40, count 0 2006.281.08:18:00.25#ibcon#wrote, iclass 40, count 0 2006.281.08:18:00.25#ibcon#about to read 3, iclass 40, count 0 2006.281.08:18:00.29#ibcon#read 3, iclass 40, count 0 2006.281.08:18:00.29#ibcon#about to read 4, iclass 40, count 0 2006.281.08:18:00.29#ibcon#read 4, iclass 40, count 0 2006.281.08:18:00.29#ibcon#about to read 5, iclass 40, count 0 2006.281.08:18:00.29#ibcon#read 5, iclass 40, count 0 2006.281.08:18:00.29#ibcon#about to read 6, iclass 40, count 0 2006.281.08:18:00.29#ibcon#read 6, iclass 40, count 0 2006.281.08:18:00.29#ibcon#end of sib2, iclass 40, count 0 2006.281.08:18:00.29#ibcon#*after write, iclass 40, count 0 2006.281.08:18:00.29#ibcon#*before return 0, iclass 40, count 0 2006.281.08:18:00.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:00.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:00.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:18:00.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:18:00.29$vc4f8/va=5,7 2006.281.08:18:00.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.08:18:00.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.08:18:00.29#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:00.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:00.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:00.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:00.33#ibcon#enter wrdev, iclass 4, count 2 2006.281.08:18:00.33#ibcon#first serial, iclass 4, count 2 2006.281.08:18:00.33#ibcon#enter sib2, iclass 4, count 2 2006.281.08:18:00.33#ibcon#flushed, iclass 4, count 2 2006.281.08:18:00.33#ibcon#about to write, iclass 4, count 2 2006.281.08:18:00.33#ibcon#wrote, iclass 4, count 2 2006.281.08:18:00.33#ibcon#about to read 3, iclass 4, count 2 2006.281.08:18:00.35#ibcon#read 3, iclass 4, count 2 2006.281.08:18:00.35#ibcon#about to read 4, iclass 4, count 2 2006.281.08:18:00.35#ibcon#read 4, iclass 4, count 2 2006.281.08:18:00.35#ibcon#about to read 5, iclass 4, count 2 2006.281.08:18:00.35#ibcon#read 5, iclass 4, count 2 2006.281.08:18:00.35#ibcon#about to read 6, iclass 4, count 2 2006.281.08:18:00.35#ibcon#read 6, iclass 4, count 2 2006.281.08:18:00.35#ibcon#end of sib2, iclass 4, count 2 2006.281.08:18:00.35#ibcon#*mode == 0, iclass 4, count 2 2006.281.08:18:00.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.08:18:00.35#ibcon#[25=AT05-07\r\n] 2006.281.08:18:00.35#ibcon#*before write, iclass 4, count 2 2006.281.08:18:00.35#ibcon#enter sib2, iclass 4, count 2 2006.281.08:18:00.35#ibcon#flushed, iclass 4, count 2 2006.281.08:18:00.35#ibcon#about to write, iclass 4, count 2 2006.281.08:18:00.35#ibcon#wrote, iclass 4, count 2 2006.281.08:18:00.35#ibcon#about to read 3, iclass 4, count 2 2006.281.08:18:00.35#abcon#<5=/13 2.1 9.4 20.04 531001.8\r\n> 2006.281.08:18:00.37#abcon#{5=INTERFACE CLEAR} 2006.281.08:18:00.38#ibcon#read 3, iclass 4, count 2 2006.281.08:18:00.38#ibcon#about to read 4, iclass 4, count 2 2006.281.08:18:00.38#ibcon#read 4, iclass 4, count 2 2006.281.08:18:00.38#ibcon#about to read 5, iclass 4, count 2 2006.281.08:18:00.38#ibcon#read 5, iclass 4, count 2 2006.281.08:18:00.38#ibcon#about to read 6, iclass 4, count 2 2006.281.08:18:00.38#ibcon#read 6, iclass 4, count 2 2006.281.08:18:00.38#ibcon#end of sib2, iclass 4, count 2 2006.281.08:18:00.38#ibcon#*after write, iclass 4, count 2 2006.281.08:18:00.38#ibcon#*before return 0, iclass 4, count 2 2006.281.08:18:00.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:00.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:00.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.08:18:00.38#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:00.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:00.43#abcon#[5=S1D000X0/0*\r\n] 2006.281.08:18:00.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:00.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:00.50#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:18:00.50#ibcon#first serial, iclass 4, count 0 2006.281.08:18:00.50#ibcon#enter sib2, iclass 4, count 0 2006.281.08:18:00.50#ibcon#flushed, iclass 4, count 0 2006.281.08:18:00.50#ibcon#about to write, iclass 4, count 0 2006.281.08:18:00.50#ibcon#wrote, iclass 4, count 0 2006.281.08:18:00.50#ibcon#about to read 3, iclass 4, count 0 2006.281.08:18:00.52#ibcon#read 3, iclass 4, count 0 2006.281.08:18:00.52#ibcon#about to read 4, iclass 4, count 0 2006.281.08:18:00.52#ibcon#read 4, iclass 4, count 0 2006.281.08:18:00.52#ibcon#about to read 5, iclass 4, count 0 2006.281.08:18:00.52#ibcon#read 5, iclass 4, count 0 2006.281.08:18:00.52#ibcon#about to read 6, iclass 4, count 0 2006.281.08:18:00.52#ibcon#read 6, iclass 4, count 0 2006.281.08:18:00.52#ibcon#end of sib2, iclass 4, count 0 2006.281.08:18:00.52#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:18:00.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:18:00.52#ibcon#[25=USB\r\n] 2006.281.08:18:00.52#ibcon#*before write, iclass 4, count 0 2006.281.08:18:00.52#ibcon#enter sib2, iclass 4, count 0 2006.281.08:18:00.52#ibcon#flushed, iclass 4, count 0 2006.281.08:18:00.52#ibcon#about to write, iclass 4, count 0 2006.281.08:18:00.52#ibcon#wrote, iclass 4, count 0 2006.281.08:18:00.52#ibcon#about to read 3, iclass 4, count 0 2006.281.08:18:00.55#ibcon#read 3, iclass 4, count 0 2006.281.08:18:00.55#ibcon#about to read 4, iclass 4, count 0 2006.281.08:18:00.55#ibcon#read 4, iclass 4, count 0 2006.281.08:18:00.55#ibcon#about to read 5, iclass 4, count 0 2006.281.08:18:00.55#ibcon#read 5, iclass 4, count 0 2006.281.08:18:00.55#ibcon#about to read 6, iclass 4, count 0 2006.281.08:18:00.55#ibcon#read 6, iclass 4, count 0 2006.281.08:18:00.55#ibcon#end of sib2, iclass 4, count 0 2006.281.08:18:00.55#ibcon#*after write, iclass 4, count 0 2006.281.08:18:00.55#ibcon#*before return 0, iclass 4, count 0 2006.281.08:18:00.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:00.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:00.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:18:00.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:18:00.55$vc4f8/valo=6,772.99 2006.281.08:18:00.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:18:00.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:18:00.55#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:00.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:00.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:00.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:00.55#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:18:00.55#ibcon#first serial, iclass 12, count 0 2006.281.08:18:00.55#ibcon#enter sib2, iclass 12, count 0 2006.281.08:18:00.55#ibcon#flushed, iclass 12, count 0 2006.281.08:18:00.55#ibcon#about to write, iclass 12, count 0 2006.281.08:18:00.55#ibcon#wrote, iclass 12, count 0 2006.281.08:18:00.55#ibcon#about to read 3, iclass 12, count 0 2006.281.08:18:00.57#ibcon#read 3, iclass 12, count 0 2006.281.08:18:00.57#ibcon#about to read 4, iclass 12, count 0 2006.281.08:18:00.57#ibcon#read 4, iclass 12, count 0 2006.281.08:18:00.57#ibcon#about to read 5, iclass 12, count 0 2006.281.08:18:00.57#ibcon#read 5, iclass 12, count 0 2006.281.08:18:00.57#ibcon#about to read 6, iclass 12, count 0 2006.281.08:18:00.57#ibcon#read 6, iclass 12, count 0 2006.281.08:18:00.57#ibcon#end of sib2, iclass 12, count 0 2006.281.08:18:00.57#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:18:00.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:18:00.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:18:00.57#ibcon#*before write, iclass 12, count 0 2006.281.08:18:00.57#ibcon#enter sib2, iclass 12, count 0 2006.281.08:18:00.57#ibcon#flushed, iclass 12, count 0 2006.281.08:18:00.57#ibcon#about to write, iclass 12, count 0 2006.281.08:18:00.57#ibcon#wrote, iclass 12, count 0 2006.281.08:18:00.57#ibcon#about to read 3, iclass 12, count 0 2006.281.08:18:00.62#ibcon#read 3, iclass 12, count 0 2006.281.08:18:00.62#ibcon#about to read 4, iclass 12, count 0 2006.281.08:18:00.62#ibcon#read 4, iclass 12, count 0 2006.281.08:18:00.62#ibcon#about to read 5, iclass 12, count 0 2006.281.08:18:00.62#ibcon#read 5, iclass 12, count 0 2006.281.08:18:00.62#ibcon#about to read 6, iclass 12, count 0 2006.281.08:18:00.62#ibcon#read 6, iclass 12, count 0 2006.281.08:18:00.62#ibcon#end of sib2, iclass 12, count 0 2006.281.08:18:00.62#ibcon#*after write, iclass 12, count 0 2006.281.08:18:00.62#ibcon#*before return 0, iclass 12, count 0 2006.281.08:18:00.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:00.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:00.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:18:00.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:18:00.62$vc4f8/va=6,6 2006.281.08:18:00.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.08:18:00.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.08:18:00.62#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:00.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:00.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:00.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:00.66#ibcon#enter wrdev, iclass 14, count 2 2006.281.08:18:00.66#ibcon#first serial, iclass 14, count 2 2006.281.08:18:00.66#ibcon#enter sib2, iclass 14, count 2 2006.281.08:18:00.66#ibcon#flushed, iclass 14, count 2 2006.281.08:18:00.66#ibcon#about to write, iclass 14, count 2 2006.281.08:18:00.66#ibcon#wrote, iclass 14, count 2 2006.281.08:18:00.66#ibcon#about to read 3, iclass 14, count 2 2006.281.08:18:00.68#ibcon#read 3, iclass 14, count 2 2006.281.08:18:00.68#ibcon#about to read 4, iclass 14, count 2 2006.281.08:18:00.68#ibcon#read 4, iclass 14, count 2 2006.281.08:18:00.68#ibcon#about to read 5, iclass 14, count 2 2006.281.08:18:00.68#ibcon#read 5, iclass 14, count 2 2006.281.08:18:00.68#ibcon#about to read 6, iclass 14, count 2 2006.281.08:18:00.68#ibcon#read 6, iclass 14, count 2 2006.281.08:18:00.68#ibcon#end of sib2, iclass 14, count 2 2006.281.08:18:00.68#ibcon#*mode == 0, iclass 14, count 2 2006.281.08:18:00.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.08:18:00.68#ibcon#[25=AT06-06\r\n] 2006.281.08:18:00.68#ibcon#*before write, iclass 14, count 2 2006.281.08:18:00.68#ibcon#enter sib2, iclass 14, count 2 2006.281.08:18:00.68#ibcon#flushed, iclass 14, count 2 2006.281.08:18:00.68#ibcon#about to write, iclass 14, count 2 2006.281.08:18:00.68#ibcon#wrote, iclass 14, count 2 2006.281.08:18:00.68#ibcon#about to read 3, iclass 14, count 2 2006.281.08:18:00.71#ibcon#read 3, iclass 14, count 2 2006.281.08:18:00.71#ibcon#about to read 4, iclass 14, count 2 2006.281.08:18:00.71#ibcon#read 4, iclass 14, count 2 2006.281.08:18:00.71#ibcon#about to read 5, iclass 14, count 2 2006.281.08:18:00.71#ibcon#read 5, iclass 14, count 2 2006.281.08:18:00.71#ibcon#about to read 6, iclass 14, count 2 2006.281.08:18:00.71#ibcon#read 6, iclass 14, count 2 2006.281.08:18:00.71#ibcon#end of sib2, iclass 14, count 2 2006.281.08:18:00.71#ibcon#*after write, iclass 14, count 2 2006.281.08:18:00.71#ibcon#*before return 0, iclass 14, count 2 2006.281.08:18:00.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:00.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:00.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.08:18:00.71#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:00.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:18:00.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:18:00.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:18:00.83#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:18:00.83#ibcon#first serial, iclass 14, count 0 2006.281.08:18:00.83#ibcon#enter sib2, iclass 14, count 0 2006.281.08:18:00.83#ibcon#flushed, iclass 14, count 0 2006.281.08:18:00.83#ibcon#about to write, iclass 14, count 0 2006.281.08:18:00.83#ibcon#wrote, iclass 14, count 0 2006.281.08:18:00.83#ibcon#about to read 3, iclass 14, count 0 2006.281.08:18:00.85#ibcon#read 3, iclass 14, count 0 2006.281.08:18:00.85#ibcon#about to read 4, iclass 14, count 0 2006.281.08:18:00.85#ibcon#read 4, iclass 14, count 0 2006.281.08:18:00.85#ibcon#about to read 5, iclass 14, count 0 2006.281.08:18:00.85#ibcon#read 5, iclass 14, count 0 2006.281.08:18:00.85#ibcon#about to read 6, iclass 14, count 0 2006.281.08:18:00.85#ibcon#read 6, iclass 14, count 0 2006.281.08:18:00.85#ibcon#end of sib2, iclass 14, count 0 2006.281.08:18:00.85#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:18:00.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:18:00.85#ibcon#[25=USB\r\n] 2006.281.08:18:00.85#ibcon#*before write, iclass 14, count 0 2006.281.08:18:00.85#ibcon#enter sib2, iclass 14, count 0 2006.281.08:18:00.85#ibcon#flushed, iclass 14, count 0 2006.281.08:18:00.85#ibcon#about to write, iclass 14, count 0 2006.281.08:18:00.85#ibcon#wrote, iclass 14, count 0 2006.281.08:18:00.85#ibcon#about to read 3, iclass 14, count 0 2006.281.08:18:00.88#ibcon#read 3, iclass 14, count 0 2006.281.08:18:00.88#ibcon#about to read 4, iclass 14, count 0 2006.281.08:18:00.88#ibcon#read 4, iclass 14, count 0 2006.281.08:18:00.88#ibcon#about to read 5, iclass 14, count 0 2006.281.08:18:00.88#ibcon#read 5, iclass 14, count 0 2006.281.08:18:00.88#ibcon#about to read 6, iclass 14, count 0 2006.281.08:18:00.88#ibcon#read 6, iclass 14, count 0 2006.281.08:18:00.88#ibcon#end of sib2, iclass 14, count 0 2006.281.08:18:00.88#ibcon#*after write, iclass 14, count 0 2006.281.08:18:00.88#ibcon#*before return 0, iclass 14, count 0 2006.281.08:18:00.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:18:00.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:18:00.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:18:00.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:18:00.88$vc4f8/valo=7,832.99 2006.281.08:18:00.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.08:18:00.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.08:18:00.88#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:00.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:18:00.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:18:00.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:18:00.88#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:18:00.88#ibcon#first serial, iclass 16, count 0 2006.281.08:18:00.88#ibcon#enter sib2, iclass 16, count 0 2006.281.08:18:00.88#ibcon#flushed, iclass 16, count 0 2006.281.08:18:00.88#ibcon#about to write, iclass 16, count 0 2006.281.08:18:00.88#ibcon#wrote, iclass 16, count 0 2006.281.08:18:00.88#ibcon#about to read 3, iclass 16, count 0 2006.281.08:18:00.90#ibcon#read 3, iclass 16, count 0 2006.281.08:18:00.90#ibcon#about to read 4, iclass 16, count 0 2006.281.08:18:00.90#ibcon#read 4, iclass 16, count 0 2006.281.08:18:00.90#ibcon#about to read 5, iclass 16, count 0 2006.281.08:18:00.90#ibcon#read 5, iclass 16, count 0 2006.281.08:18:00.90#ibcon#about to read 6, iclass 16, count 0 2006.281.08:18:00.90#ibcon#read 6, iclass 16, count 0 2006.281.08:18:00.90#ibcon#end of sib2, iclass 16, count 0 2006.281.08:18:00.90#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:18:00.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:18:00.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:18:00.90#ibcon#*before write, iclass 16, count 0 2006.281.08:18:00.90#ibcon#enter sib2, iclass 16, count 0 2006.281.08:18:00.90#ibcon#flushed, iclass 16, count 0 2006.281.08:18:00.90#ibcon#about to write, iclass 16, count 0 2006.281.08:18:00.90#ibcon#wrote, iclass 16, count 0 2006.281.08:18:00.90#ibcon#about to read 3, iclass 16, count 0 2006.281.08:18:00.94#ibcon#read 3, iclass 16, count 0 2006.281.08:18:00.94#ibcon#about to read 4, iclass 16, count 0 2006.281.08:18:00.94#ibcon#read 4, iclass 16, count 0 2006.281.08:18:00.94#ibcon#about to read 5, iclass 16, count 0 2006.281.08:18:00.94#ibcon#read 5, iclass 16, count 0 2006.281.08:18:00.94#ibcon#about to read 6, iclass 16, count 0 2006.281.08:18:00.94#ibcon#read 6, iclass 16, count 0 2006.281.08:18:00.94#ibcon#end of sib2, iclass 16, count 0 2006.281.08:18:00.94#ibcon#*after write, iclass 16, count 0 2006.281.08:18:00.94#ibcon#*before return 0, iclass 16, count 0 2006.281.08:18:00.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:18:00.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:18:00.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:18:00.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:18:00.94$vc4f8/va=7,6 2006.281.08:18:00.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.08:18:00.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.08:18:00.96#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:00.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:18:01.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:18:01.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:18:01.00#ibcon#enter wrdev, iclass 18, count 2 2006.281.08:18:01.00#ibcon#first serial, iclass 18, count 2 2006.281.08:18:01.00#ibcon#enter sib2, iclass 18, count 2 2006.281.08:18:01.00#ibcon#flushed, iclass 18, count 2 2006.281.08:18:01.00#ibcon#about to write, iclass 18, count 2 2006.281.08:18:01.00#ibcon#wrote, iclass 18, count 2 2006.281.08:18:01.00#ibcon#about to read 3, iclass 18, count 2 2006.281.08:18:01.02#ibcon#read 3, iclass 18, count 2 2006.281.08:18:01.02#ibcon#about to read 4, iclass 18, count 2 2006.281.08:18:01.02#ibcon#read 4, iclass 18, count 2 2006.281.08:18:01.02#ibcon#about to read 5, iclass 18, count 2 2006.281.08:18:01.02#ibcon#read 5, iclass 18, count 2 2006.281.08:18:01.02#ibcon#about to read 6, iclass 18, count 2 2006.281.08:18:01.02#ibcon#read 6, iclass 18, count 2 2006.281.08:18:01.02#ibcon#end of sib2, iclass 18, count 2 2006.281.08:18:01.02#ibcon#*mode == 0, iclass 18, count 2 2006.281.08:18:01.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.08:18:01.02#ibcon#[25=AT07-06\r\n] 2006.281.08:18:01.02#ibcon#*before write, iclass 18, count 2 2006.281.08:18:01.02#ibcon#enter sib2, iclass 18, count 2 2006.281.08:18:01.02#ibcon#flushed, iclass 18, count 2 2006.281.08:18:01.02#ibcon#about to write, iclass 18, count 2 2006.281.08:18:01.02#ibcon#wrote, iclass 18, count 2 2006.281.08:18:01.02#ibcon#about to read 3, iclass 18, count 2 2006.281.08:18:01.04#ibcon#read 3, iclass 18, count 2 2006.281.08:18:01.04#ibcon#about to read 4, iclass 18, count 2 2006.281.08:18:01.04#ibcon#read 4, iclass 18, count 2 2006.281.08:18:01.04#ibcon#about to read 5, iclass 18, count 2 2006.281.08:18:01.04#ibcon#read 5, iclass 18, count 2 2006.281.08:18:01.04#ibcon#about to read 6, iclass 18, count 2 2006.281.08:18:01.04#ibcon#read 6, iclass 18, count 2 2006.281.08:18:01.04#ibcon#end of sib2, iclass 18, count 2 2006.281.08:18:01.04#ibcon#*after write, iclass 18, count 2 2006.281.08:18:01.04#ibcon#*before return 0, iclass 18, count 2 2006.281.08:18:01.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:18:01.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:18:01.04#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.08:18:01.04#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:01.04#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:18:01.16#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:18:01.16#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:18:01.16#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:18:01.16#ibcon#first serial, iclass 18, count 0 2006.281.08:18:01.16#ibcon#enter sib2, iclass 18, count 0 2006.281.08:18:01.16#ibcon#flushed, iclass 18, count 0 2006.281.08:18:01.16#ibcon#about to write, iclass 18, count 0 2006.281.08:18:01.16#ibcon#wrote, iclass 18, count 0 2006.281.08:18:01.16#ibcon#about to read 3, iclass 18, count 0 2006.281.08:18:01.18#ibcon#read 3, iclass 18, count 0 2006.281.08:18:01.18#ibcon#about to read 4, iclass 18, count 0 2006.281.08:18:01.18#ibcon#read 4, iclass 18, count 0 2006.281.08:18:01.18#ibcon#about to read 5, iclass 18, count 0 2006.281.08:18:01.18#ibcon#read 5, iclass 18, count 0 2006.281.08:18:01.18#ibcon#about to read 6, iclass 18, count 0 2006.281.08:18:01.18#ibcon#read 6, iclass 18, count 0 2006.281.08:18:01.18#ibcon#end of sib2, iclass 18, count 0 2006.281.08:18:01.18#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:18:01.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:18:01.18#ibcon#[25=USB\r\n] 2006.281.08:18:01.18#ibcon#*before write, iclass 18, count 0 2006.281.08:18:01.18#ibcon#enter sib2, iclass 18, count 0 2006.281.08:18:01.18#ibcon#flushed, iclass 18, count 0 2006.281.08:18:01.18#ibcon#about to write, iclass 18, count 0 2006.281.08:18:01.18#ibcon#wrote, iclass 18, count 0 2006.281.08:18:01.18#ibcon#about to read 3, iclass 18, count 0 2006.281.08:18:01.22#ibcon#read 3, iclass 18, count 0 2006.281.08:18:01.22#ibcon#about to read 4, iclass 18, count 0 2006.281.08:18:01.22#ibcon#read 4, iclass 18, count 0 2006.281.08:18:01.22#ibcon#about to read 5, iclass 18, count 0 2006.281.08:18:01.22#ibcon#read 5, iclass 18, count 0 2006.281.08:18:01.22#ibcon#about to read 6, iclass 18, count 0 2006.281.08:18:01.22#ibcon#read 6, iclass 18, count 0 2006.281.08:18:01.22#ibcon#end of sib2, iclass 18, count 0 2006.281.08:18:01.22#ibcon#*after write, iclass 18, count 0 2006.281.08:18:01.22#ibcon#*before return 0, iclass 18, count 0 2006.281.08:18:01.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:18:01.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:18:01.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:18:01.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:18:01.22$vc4f8/valo=8,852.99 2006.281.08:18:01.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.08:18:01.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.08:18:01.22#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:01.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:18:01.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:18:01.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:18:01.22#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:18:01.22#ibcon#first serial, iclass 20, count 0 2006.281.08:18:01.22#ibcon#enter sib2, iclass 20, count 0 2006.281.08:18:01.22#ibcon#flushed, iclass 20, count 0 2006.281.08:18:01.22#ibcon#about to write, iclass 20, count 0 2006.281.08:18:01.22#ibcon#wrote, iclass 20, count 0 2006.281.08:18:01.22#ibcon#about to read 3, iclass 20, count 0 2006.281.08:18:01.23#ibcon#read 3, iclass 20, count 0 2006.281.08:18:01.23#ibcon#about to read 4, iclass 20, count 0 2006.281.08:18:01.23#ibcon#read 4, iclass 20, count 0 2006.281.08:18:01.23#ibcon#about to read 5, iclass 20, count 0 2006.281.08:18:01.23#ibcon#read 5, iclass 20, count 0 2006.281.08:18:01.23#ibcon#about to read 6, iclass 20, count 0 2006.281.08:18:01.23#ibcon#read 6, iclass 20, count 0 2006.281.08:18:01.23#ibcon#end of sib2, iclass 20, count 0 2006.281.08:18:01.23#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:18:01.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:18:01.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:18:01.23#ibcon#*before write, iclass 20, count 0 2006.281.08:18:01.23#ibcon#enter sib2, iclass 20, count 0 2006.281.08:18:01.23#ibcon#flushed, iclass 20, count 0 2006.281.08:18:01.23#ibcon#about to write, iclass 20, count 0 2006.281.08:18:01.23#ibcon#wrote, iclass 20, count 0 2006.281.08:18:01.23#ibcon#about to read 3, iclass 20, count 0 2006.281.08:18:01.27#ibcon#read 3, iclass 20, count 0 2006.281.08:18:01.27#ibcon#about to read 4, iclass 20, count 0 2006.281.08:18:01.27#ibcon#read 4, iclass 20, count 0 2006.281.08:18:01.27#ibcon#about to read 5, iclass 20, count 0 2006.281.08:18:01.27#ibcon#read 5, iclass 20, count 0 2006.281.08:18:01.27#ibcon#about to read 6, iclass 20, count 0 2006.281.08:18:01.27#ibcon#read 6, iclass 20, count 0 2006.281.08:18:01.27#ibcon#end of sib2, iclass 20, count 0 2006.281.08:18:01.27#ibcon#*after write, iclass 20, count 0 2006.281.08:18:01.27#ibcon#*before return 0, iclass 20, count 0 2006.281.08:18:01.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:18:01.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:18:01.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:18:01.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:18:01.27$vc4f8/va=8,6 2006.281.08:18:01.27#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.08:18:01.27#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.08:18:01.27#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:01.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:18:01.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:18:01.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:18:01.34#ibcon#enter wrdev, iclass 22, count 2 2006.281.08:18:01.34#ibcon#first serial, iclass 22, count 2 2006.281.08:18:01.34#ibcon#enter sib2, iclass 22, count 2 2006.281.08:18:01.34#ibcon#flushed, iclass 22, count 2 2006.281.08:18:01.34#ibcon#about to write, iclass 22, count 2 2006.281.08:18:01.34#ibcon#wrote, iclass 22, count 2 2006.281.08:18:01.34#ibcon#about to read 3, iclass 22, count 2 2006.281.08:18:01.36#ibcon#read 3, iclass 22, count 2 2006.281.08:18:01.36#ibcon#about to read 4, iclass 22, count 2 2006.281.08:18:01.36#ibcon#read 4, iclass 22, count 2 2006.281.08:18:01.36#ibcon#about to read 5, iclass 22, count 2 2006.281.08:18:01.36#ibcon#read 5, iclass 22, count 2 2006.281.08:18:01.36#ibcon#about to read 6, iclass 22, count 2 2006.281.08:18:01.36#ibcon#read 6, iclass 22, count 2 2006.281.08:18:01.36#ibcon#end of sib2, iclass 22, count 2 2006.281.08:18:01.36#ibcon#*mode == 0, iclass 22, count 2 2006.281.08:18:01.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.08:18:01.36#ibcon#[25=AT08-06\r\n] 2006.281.08:18:01.36#ibcon#*before write, iclass 22, count 2 2006.281.08:18:01.36#ibcon#enter sib2, iclass 22, count 2 2006.281.08:18:01.36#ibcon#flushed, iclass 22, count 2 2006.281.08:18:01.36#ibcon#about to write, iclass 22, count 2 2006.281.08:18:01.36#ibcon#wrote, iclass 22, count 2 2006.281.08:18:01.36#ibcon#about to read 3, iclass 22, count 2 2006.281.08:18:01.39#ibcon#read 3, iclass 22, count 2 2006.281.08:18:01.39#ibcon#about to read 4, iclass 22, count 2 2006.281.08:18:01.39#ibcon#read 4, iclass 22, count 2 2006.281.08:18:01.39#ibcon#about to read 5, iclass 22, count 2 2006.281.08:18:01.39#ibcon#read 5, iclass 22, count 2 2006.281.08:18:01.39#ibcon#about to read 6, iclass 22, count 2 2006.281.08:18:01.39#ibcon#read 6, iclass 22, count 2 2006.281.08:18:01.39#ibcon#end of sib2, iclass 22, count 2 2006.281.08:18:01.39#ibcon#*after write, iclass 22, count 2 2006.281.08:18:01.39#ibcon#*before return 0, iclass 22, count 2 2006.281.08:18:01.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:18:01.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:18:01.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.08:18:01.39#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:01.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:18:01.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:18:01.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:18:01.51#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:18:01.51#ibcon#first serial, iclass 22, count 0 2006.281.08:18:01.51#ibcon#enter sib2, iclass 22, count 0 2006.281.08:18:01.51#ibcon#flushed, iclass 22, count 0 2006.281.08:18:01.51#ibcon#about to write, iclass 22, count 0 2006.281.08:18:01.51#ibcon#wrote, iclass 22, count 0 2006.281.08:18:01.51#ibcon#about to read 3, iclass 22, count 0 2006.281.08:18:01.53#ibcon#read 3, iclass 22, count 0 2006.281.08:18:01.53#ibcon#about to read 4, iclass 22, count 0 2006.281.08:18:01.53#ibcon#read 4, iclass 22, count 0 2006.281.08:18:01.53#ibcon#about to read 5, iclass 22, count 0 2006.281.08:18:01.53#ibcon#read 5, iclass 22, count 0 2006.281.08:18:01.53#ibcon#about to read 6, iclass 22, count 0 2006.281.08:18:01.53#ibcon#read 6, iclass 22, count 0 2006.281.08:18:01.53#ibcon#end of sib2, iclass 22, count 0 2006.281.08:18:01.53#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:18:01.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:18:01.53#ibcon#[25=USB\r\n] 2006.281.08:18:01.53#ibcon#*before write, iclass 22, count 0 2006.281.08:18:01.53#ibcon#enter sib2, iclass 22, count 0 2006.281.08:18:01.53#ibcon#flushed, iclass 22, count 0 2006.281.08:18:01.53#ibcon#about to write, iclass 22, count 0 2006.281.08:18:01.53#ibcon#wrote, iclass 22, count 0 2006.281.08:18:01.53#ibcon#about to read 3, iclass 22, count 0 2006.281.08:18:01.56#ibcon#read 3, iclass 22, count 0 2006.281.08:18:01.56#ibcon#about to read 4, iclass 22, count 0 2006.281.08:18:01.56#ibcon#read 4, iclass 22, count 0 2006.281.08:18:01.56#ibcon#about to read 5, iclass 22, count 0 2006.281.08:18:01.56#ibcon#read 5, iclass 22, count 0 2006.281.08:18:01.56#ibcon#about to read 6, iclass 22, count 0 2006.281.08:18:01.56#ibcon#read 6, iclass 22, count 0 2006.281.08:18:01.56#ibcon#end of sib2, iclass 22, count 0 2006.281.08:18:01.56#ibcon#*after write, iclass 22, count 0 2006.281.08:18:01.56#ibcon#*before return 0, iclass 22, count 0 2006.281.08:18:01.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:18:01.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:18:01.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:18:01.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:18:01.56$vc4f8/vblo=1,632.99 2006.281.08:18:01.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.08:18:01.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.08:18:01.56#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:01.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:18:01.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:18:01.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:18:01.56#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:18:01.56#ibcon#first serial, iclass 24, count 0 2006.281.08:18:01.56#ibcon#enter sib2, iclass 24, count 0 2006.281.08:18:01.56#ibcon#flushed, iclass 24, count 0 2006.281.08:18:01.56#ibcon#about to write, iclass 24, count 0 2006.281.08:18:01.56#ibcon#wrote, iclass 24, count 0 2006.281.08:18:01.56#ibcon#about to read 3, iclass 24, count 0 2006.281.08:18:01.58#ibcon#read 3, iclass 24, count 0 2006.281.08:18:01.58#ibcon#about to read 4, iclass 24, count 0 2006.281.08:18:01.58#ibcon#read 4, iclass 24, count 0 2006.281.08:18:01.58#ibcon#about to read 5, iclass 24, count 0 2006.281.08:18:01.58#ibcon#read 5, iclass 24, count 0 2006.281.08:18:01.58#ibcon#about to read 6, iclass 24, count 0 2006.281.08:18:01.58#ibcon#read 6, iclass 24, count 0 2006.281.08:18:01.58#ibcon#end of sib2, iclass 24, count 0 2006.281.08:18:01.58#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:18:01.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:18:01.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:18:01.58#ibcon#*before write, iclass 24, count 0 2006.281.08:18:01.58#ibcon#enter sib2, iclass 24, count 0 2006.281.08:18:01.58#ibcon#flushed, iclass 24, count 0 2006.281.08:18:01.58#ibcon#about to write, iclass 24, count 0 2006.281.08:18:01.58#ibcon#wrote, iclass 24, count 0 2006.281.08:18:01.58#ibcon#about to read 3, iclass 24, count 0 2006.281.08:18:01.63#ibcon#read 3, iclass 24, count 0 2006.281.08:18:01.63#ibcon#about to read 4, iclass 24, count 0 2006.281.08:18:01.63#ibcon#read 4, iclass 24, count 0 2006.281.08:18:01.63#ibcon#about to read 5, iclass 24, count 0 2006.281.08:18:01.63#ibcon#read 5, iclass 24, count 0 2006.281.08:18:01.63#ibcon#about to read 6, iclass 24, count 0 2006.281.08:18:01.63#ibcon#read 6, iclass 24, count 0 2006.281.08:18:01.63#ibcon#end of sib2, iclass 24, count 0 2006.281.08:18:01.63#ibcon#*after write, iclass 24, count 0 2006.281.08:18:01.63#ibcon#*before return 0, iclass 24, count 0 2006.281.08:18:01.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:18:01.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:18:01.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:18:01.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:18:01.63$vc4f8/vb=1,4 2006.281.08:18:01.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.08:18:01.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.08:18:01.63#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:01.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:18:01.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:18:01.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:18:01.63#ibcon#enter wrdev, iclass 26, count 2 2006.281.08:18:01.63#ibcon#first serial, iclass 26, count 2 2006.281.08:18:01.63#ibcon#enter sib2, iclass 26, count 2 2006.281.08:18:01.63#ibcon#flushed, iclass 26, count 2 2006.281.08:18:01.63#ibcon#about to write, iclass 26, count 2 2006.281.08:18:01.63#ibcon#wrote, iclass 26, count 2 2006.281.08:18:01.63#ibcon#about to read 3, iclass 26, count 2 2006.281.08:18:01.64#ibcon#read 3, iclass 26, count 2 2006.281.08:18:01.64#ibcon#about to read 4, iclass 26, count 2 2006.281.08:18:01.64#ibcon#read 4, iclass 26, count 2 2006.281.08:18:01.64#ibcon#about to read 5, iclass 26, count 2 2006.281.08:18:01.64#ibcon#read 5, iclass 26, count 2 2006.281.08:18:01.64#ibcon#about to read 6, iclass 26, count 2 2006.281.08:18:01.64#ibcon#read 6, iclass 26, count 2 2006.281.08:18:01.64#ibcon#end of sib2, iclass 26, count 2 2006.281.08:18:01.64#ibcon#*mode == 0, iclass 26, count 2 2006.281.08:18:01.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.08:18:01.64#ibcon#[27=AT01-04\r\n] 2006.281.08:18:01.65#ibcon#*before write, iclass 26, count 2 2006.281.08:18:01.65#ibcon#enter sib2, iclass 26, count 2 2006.281.08:18:01.65#ibcon#flushed, iclass 26, count 2 2006.281.08:18:01.65#ibcon#about to write, iclass 26, count 2 2006.281.08:18:01.65#ibcon#wrote, iclass 26, count 2 2006.281.08:18:01.65#ibcon#about to read 3, iclass 26, count 2 2006.281.08:18:01.68#ibcon#read 3, iclass 26, count 2 2006.281.08:18:01.68#ibcon#about to read 4, iclass 26, count 2 2006.281.08:18:01.68#ibcon#read 4, iclass 26, count 2 2006.281.08:18:01.68#ibcon#about to read 5, iclass 26, count 2 2006.281.08:18:01.68#ibcon#read 5, iclass 26, count 2 2006.281.08:18:01.68#ibcon#about to read 6, iclass 26, count 2 2006.281.08:18:01.68#ibcon#read 6, iclass 26, count 2 2006.281.08:18:01.68#ibcon#end of sib2, iclass 26, count 2 2006.281.08:18:01.68#ibcon#*after write, iclass 26, count 2 2006.281.08:18:01.68#ibcon#*before return 0, iclass 26, count 2 2006.281.08:18:01.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:18:01.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:18:01.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.08:18:01.68#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:01.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:18:01.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:18:01.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:18:01.80#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:18:01.80#ibcon#first serial, iclass 26, count 0 2006.281.08:18:01.80#ibcon#enter sib2, iclass 26, count 0 2006.281.08:18:01.80#ibcon#flushed, iclass 26, count 0 2006.281.08:18:01.80#ibcon#about to write, iclass 26, count 0 2006.281.08:18:01.80#ibcon#wrote, iclass 26, count 0 2006.281.08:18:01.80#ibcon#about to read 3, iclass 26, count 0 2006.281.08:18:01.82#ibcon#read 3, iclass 26, count 0 2006.281.08:18:01.82#ibcon#about to read 4, iclass 26, count 0 2006.281.08:18:01.82#ibcon#read 4, iclass 26, count 0 2006.281.08:18:01.82#ibcon#about to read 5, iclass 26, count 0 2006.281.08:18:01.82#ibcon#read 5, iclass 26, count 0 2006.281.08:18:01.82#ibcon#about to read 6, iclass 26, count 0 2006.281.08:18:01.82#ibcon#read 6, iclass 26, count 0 2006.281.08:18:01.82#ibcon#end of sib2, iclass 26, count 0 2006.281.08:18:01.82#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:18:01.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:18:01.82#ibcon#[27=USB\r\n] 2006.281.08:18:01.82#ibcon#*before write, iclass 26, count 0 2006.281.08:18:01.82#ibcon#enter sib2, iclass 26, count 0 2006.281.08:18:01.82#ibcon#flushed, iclass 26, count 0 2006.281.08:18:01.82#ibcon#about to write, iclass 26, count 0 2006.281.08:18:01.82#ibcon#wrote, iclass 26, count 0 2006.281.08:18:01.82#ibcon#about to read 3, iclass 26, count 0 2006.281.08:18:01.85#ibcon#read 3, iclass 26, count 0 2006.281.08:18:01.85#ibcon#about to read 4, iclass 26, count 0 2006.281.08:18:01.85#ibcon#read 4, iclass 26, count 0 2006.281.08:18:01.85#ibcon#about to read 5, iclass 26, count 0 2006.281.08:18:01.85#ibcon#read 5, iclass 26, count 0 2006.281.08:18:01.85#ibcon#about to read 6, iclass 26, count 0 2006.281.08:18:01.85#ibcon#read 6, iclass 26, count 0 2006.281.08:18:01.85#ibcon#end of sib2, iclass 26, count 0 2006.281.08:18:01.85#ibcon#*after write, iclass 26, count 0 2006.281.08:18:01.85#ibcon#*before return 0, iclass 26, count 0 2006.281.08:18:01.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:18:01.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:18:01.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:18:01.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:18:01.85$vc4f8/vblo=2,640.99 2006.281.08:18:01.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:18:01.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:18:01.85#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:01.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:18:01.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:18:01.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:18:01.85#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:18:01.85#ibcon#first serial, iclass 28, count 0 2006.281.08:18:01.85#ibcon#enter sib2, iclass 28, count 0 2006.281.08:18:01.85#ibcon#flushed, iclass 28, count 0 2006.281.08:18:01.85#ibcon#about to write, iclass 28, count 0 2006.281.08:18:01.85#ibcon#wrote, iclass 28, count 0 2006.281.08:18:01.85#ibcon#about to read 3, iclass 28, count 0 2006.281.08:18:01.87#ibcon#read 3, iclass 28, count 0 2006.281.08:18:01.87#ibcon#about to read 4, iclass 28, count 0 2006.281.08:18:01.87#ibcon#read 4, iclass 28, count 0 2006.281.08:18:01.87#ibcon#about to read 5, iclass 28, count 0 2006.281.08:18:01.87#ibcon#read 5, iclass 28, count 0 2006.281.08:18:01.87#ibcon#about to read 6, iclass 28, count 0 2006.281.08:18:01.87#ibcon#read 6, iclass 28, count 0 2006.281.08:18:01.87#ibcon#end of sib2, iclass 28, count 0 2006.281.08:18:01.87#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:18:01.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:18:01.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:18:01.87#ibcon#*before write, iclass 28, count 0 2006.281.08:18:01.87#ibcon#enter sib2, iclass 28, count 0 2006.281.08:18:01.87#ibcon#flushed, iclass 28, count 0 2006.281.08:18:01.87#ibcon#about to write, iclass 28, count 0 2006.281.08:18:01.87#ibcon#wrote, iclass 28, count 0 2006.281.08:18:01.87#ibcon#about to read 3, iclass 28, count 0 2006.281.08:18:01.91#ibcon#read 3, iclass 28, count 0 2006.281.08:18:01.91#ibcon#about to read 4, iclass 28, count 0 2006.281.08:18:01.91#ibcon#read 4, iclass 28, count 0 2006.281.08:18:01.91#ibcon#about to read 5, iclass 28, count 0 2006.281.08:18:01.91#ibcon#read 5, iclass 28, count 0 2006.281.08:18:01.91#ibcon#about to read 6, iclass 28, count 0 2006.281.08:18:01.91#ibcon#read 6, iclass 28, count 0 2006.281.08:18:01.91#ibcon#end of sib2, iclass 28, count 0 2006.281.08:18:01.91#ibcon#*after write, iclass 28, count 0 2006.281.08:18:01.91#ibcon#*before return 0, iclass 28, count 0 2006.281.08:18:01.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:18:01.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:18:01.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:18:01.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:18:01.91$vc4f8/vb=2,5 2006.281.08:18:01.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.08:18:01.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.08:18:01.91#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:01.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:18:01.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:18:01.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:18:01.97#ibcon#enter wrdev, iclass 30, count 2 2006.281.08:18:01.97#ibcon#first serial, iclass 30, count 2 2006.281.08:18:01.97#ibcon#enter sib2, iclass 30, count 2 2006.281.08:18:01.97#ibcon#flushed, iclass 30, count 2 2006.281.08:18:01.97#ibcon#about to write, iclass 30, count 2 2006.281.08:18:01.97#ibcon#wrote, iclass 30, count 2 2006.281.08:18:01.97#ibcon#about to read 3, iclass 30, count 2 2006.281.08:18:01.99#ibcon#read 3, iclass 30, count 2 2006.281.08:18:01.99#ibcon#about to read 4, iclass 30, count 2 2006.281.08:18:01.99#ibcon#read 4, iclass 30, count 2 2006.281.08:18:01.99#ibcon#about to read 5, iclass 30, count 2 2006.281.08:18:01.99#ibcon#read 5, iclass 30, count 2 2006.281.08:18:01.99#ibcon#about to read 6, iclass 30, count 2 2006.281.08:18:01.99#ibcon#read 6, iclass 30, count 2 2006.281.08:18:01.99#ibcon#end of sib2, iclass 30, count 2 2006.281.08:18:01.99#ibcon#*mode == 0, iclass 30, count 2 2006.281.08:18:01.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.08:18:01.99#ibcon#[27=AT02-05\r\n] 2006.281.08:18:01.99#ibcon#*before write, iclass 30, count 2 2006.281.08:18:01.99#ibcon#enter sib2, iclass 30, count 2 2006.281.08:18:01.99#ibcon#flushed, iclass 30, count 2 2006.281.08:18:01.99#ibcon#about to write, iclass 30, count 2 2006.281.08:18:01.99#ibcon#wrote, iclass 30, count 2 2006.281.08:18:01.99#ibcon#about to read 3, iclass 30, count 2 2006.281.08:18:02.02#ibcon#read 3, iclass 30, count 2 2006.281.08:18:02.02#ibcon#about to read 4, iclass 30, count 2 2006.281.08:18:02.02#ibcon#read 4, iclass 30, count 2 2006.281.08:18:02.02#ibcon#about to read 5, iclass 30, count 2 2006.281.08:18:02.02#ibcon#read 5, iclass 30, count 2 2006.281.08:18:02.02#ibcon#about to read 6, iclass 30, count 2 2006.281.08:18:02.02#ibcon#read 6, iclass 30, count 2 2006.281.08:18:02.02#ibcon#end of sib2, iclass 30, count 2 2006.281.08:18:02.02#ibcon#*after write, iclass 30, count 2 2006.281.08:18:02.02#ibcon#*before return 0, iclass 30, count 2 2006.281.08:18:02.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:18:02.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:18:02.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.08:18:02.02#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:02.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:18:02.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:18:02.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:18:02.14#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:18:02.14#ibcon#first serial, iclass 30, count 0 2006.281.08:18:02.14#ibcon#enter sib2, iclass 30, count 0 2006.281.08:18:02.14#ibcon#flushed, iclass 30, count 0 2006.281.08:18:02.14#ibcon#about to write, iclass 30, count 0 2006.281.08:18:02.14#ibcon#wrote, iclass 30, count 0 2006.281.08:18:02.14#ibcon#about to read 3, iclass 30, count 0 2006.281.08:18:02.16#ibcon#read 3, iclass 30, count 0 2006.281.08:18:02.16#ibcon#about to read 4, iclass 30, count 0 2006.281.08:18:02.16#ibcon#read 4, iclass 30, count 0 2006.281.08:18:02.16#ibcon#about to read 5, iclass 30, count 0 2006.281.08:18:02.16#ibcon#read 5, iclass 30, count 0 2006.281.08:18:02.16#ibcon#about to read 6, iclass 30, count 0 2006.281.08:18:02.16#ibcon#read 6, iclass 30, count 0 2006.281.08:18:02.16#ibcon#end of sib2, iclass 30, count 0 2006.281.08:18:02.16#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:18:02.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:18:02.16#ibcon#[27=USB\r\n] 2006.281.08:18:02.16#ibcon#*before write, iclass 30, count 0 2006.281.08:18:02.16#ibcon#enter sib2, iclass 30, count 0 2006.281.08:18:02.16#ibcon#flushed, iclass 30, count 0 2006.281.08:18:02.16#ibcon#about to write, iclass 30, count 0 2006.281.08:18:02.16#ibcon#wrote, iclass 30, count 0 2006.281.08:18:02.16#ibcon#about to read 3, iclass 30, count 0 2006.281.08:18:02.19#ibcon#read 3, iclass 30, count 0 2006.281.08:18:02.19#ibcon#about to read 4, iclass 30, count 0 2006.281.08:18:02.19#ibcon#read 4, iclass 30, count 0 2006.281.08:18:02.19#ibcon#about to read 5, iclass 30, count 0 2006.281.08:18:02.19#ibcon#read 5, iclass 30, count 0 2006.281.08:18:02.19#ibcon#about to read 6, iclass 30, count 0 2006.281.08:18:02.19#ibcon#read 6, iclass 30, count 0 2006.281.08:18:02.19#ibcon#end of sib2, iclass 30, count 0 2006.281.08:18:02.19#ibcon#*after write, iclass 30, count 0 2006.281.08:18:02.19#ibcon#*before return 0, iclass 30, count 0 2006.281.08:18:02.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:18:02.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:18:02.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:18:02.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:18:02.19$vc4f8/vblo=3,656.99 2006.281.08:18:02.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.08:18:02.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.08:18:02.19#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:02.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:18:02.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:18:02.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:18:02.19#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:18:02.19#ibcon#first serial, iclass 32, count 0 2006.281.08:18:02.19#ibcon#enter sib2, iclass 32, count 0 2006.281.08:18:02.19#ibcon#flushed, iclass 32, count 0 2006.281.08:18:02.19#ibcon#about to write, iclass 32, count 0 2006.281.08:18:02.19#ibcon#wrote, iclass 32, count 0 2006.281.08:18:02.19#ibcon#about to read 3, iclass 32, count 0 2006.281.08:18:02.21#ibcon#read 3, iclass 32, count 0 2006.281.08:18:02.21#ibcon#about to read 4, iclass 32, count 0 2006.281.08:18:02.21#ibcon#read 4, iclass 32, count 0 2006.281.08:18:02.21#ibcon#about to read 5, iclass 32, count 0 2006.281.08:18:02.21#ibcon#read 5, iclass 32, count 0 2006.281.08:18:02.21#ibcon#about to read 6, iclass 32, count 0 2006.281.08:18:02.21#ibcon#read 6, iclass 32, count 0 2006.281.08:18:02.21#ibcon#end of sib2, iclass 32, count 0 2006.281.08:18:02.21#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:18:02.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:18:02.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:18:02.21#ibcon#*before write, iclass 32, count 0 2006.281.08:18:02.21#ibcon#enter sib2, iclass 32, count 0 2006.281.08:18:02.21#ibcon#flushed, iclass 32, count 0 2006.281.08:18:02.21#ibcon#about to write, iclass 32, count 0 2006.281.08:18:02.21#ibcon#wrote, iclass 32, count 0 2006.281.08:18:02.21#ibcon#about to read 3, iclass 32, count 0 2006.281.08:18:02.26#ibcon#read 3, iclass 32, count 0 2006.281.08:18:02.26#ibcon#about to read 4, iclass 32, count 0 2006.281.08:18:02.26#ibcon#read 4, iclass 32, count 0 2006.281.08:18:02.26#ibcon#about to read 5, iclass 32, count 0 2006.281.08:18:02.26#ibcon#read 5, iclass 32, count 0 2006.281.08:18:02.26#ibcon#about to read 6, iclass 32, count 0 2006.281.08:18:02.26#ibcon#read 6, iclass 32, count 0 2006.281.08:18:02.26#ibcon#end of sib2, iclass 32, count 0 2006.281.08:18:02.26#ibcon#*after write, iclass 32, count 0 2006.281.08:18:02.26#ibcon#*before return 0, iclass 32, count 0 2006.281.08:18:02.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:18:02.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:18:02.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:18:02.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:18:02.26$vc4f8/vb=3,4 2006.281.08:18:02.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.08:18:02.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.08:18:02.26#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:02.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:18:02.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:18:02.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:18:02.30#ibcon#enter wrdev, iclass 34, count 2 2006.281.08:18:02.30#ibcon#first serial, iclass 34, count 2 2006.281.08:18:02.30#ibcon#enter sib2, iclass 34, count 2 2006.281.08:18:02.30#ibcon#flushed, iclass 34, count 2 2006.281.08:18:02.30#ibcon#about to write, iclass 34, count 2 2006.281.08:18:02.30#ibcon#wrote, iclass 34, count 2 2006.281.08:18:02.30#ibcon#about to read 3, iclass 34, count 2 2006.281.08:18:02.32#ibcon#read 3, iclass 34, count 2 2006.281.08:18:02.32#ibcon#about to read 4, iclass 34, count 2 2006.281.08:18:02.32#ibcon#read 4, iclass 34, count 2 2006.281.08:18:02.32#ibcon#about to read 5, iclass 34, count 2 2006.281.08:18:02.32#ibcon#read 5, iclass 34, count 2 2006.281.08:18:02.32#ibcon#about to read 6, iclass 34, count 2 2006.281.08:18:02.32#ibcon#read 6, iclass 34, count 2 2006.281.08:18:02.32#ibcon#end of sib2, iclass 34, count 2 2006.281.08:18:02.32#ibcon#*mode == 0, iclass 34, count 2 2006.281.08:18:02.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.08:18:02.32#ibcon#[27=AT03-04\r\n] 2006.281.08:18:02.32#ibcon#*before write, iclass 34, count 2 2006.281.08:18:02.32#ibcon#enter sib2, iclass 34, count 2 2006.281.08:18:02.32#ibcon#flushed, iclass 34, count 2 2006.281.08:18:02.32#ibcon#about to write, iclass 34, count 2 2006.281.08:18:02.32#ibcon#wrote, iclass 34, count 2 2006.281.08:18:02.32#ibcon#about to read 3, iclass 34, count 2 2006.281.08:18:02.36#ibcon#read 3, iclass 34, count 2 2006.281.08:18:02.36#ibcon#about to read 4, iclass 34, count 2 2006.281.08:18:02.36#ibcon#read 4, iclass 34, count 2 2006.281.08:18:02.36#ibcon#about to read 5, iclass 34, count 2 2006.281.08:18:02.36#ibcon#read 5, iclass 34, count 2 2006.281.08:18:02.36#ibcon#about to read 6, iclass 34, count 2 2006.281.08:18:02.36#ibcon#read 6, iclass 34, count 2 2006.281.08:18:02.36#ibcon#end of sib2, iclass 34, count 2 2006.281.08:18:02.36#ibcon#*after write, iclass 34, count 2 2006.281.08:18:02.36#ibcon#*before return 0, iclass 34, count 2 2006.281.08:18:02.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:18:02.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:18:02.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.08:18:02.36#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:02.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:18:02.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:18:02.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:18:02.47#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:18:02.47#ibcon#first serial, iclass 34, count 0 2006.281.08:18:02.47#ibcon#enter sib2, iclass 34, count 0 2006.281.08:18:02.47#ibcon#flushed, iclass 34, count 0 2006.281.08:18:02.47#ibcon#about to write, iclass 34, count 0 2006.281.08:18:02.47#ibcon#wrote, iclass 34, count 0 2006.281.08:18:02.47#ibcon#about to read 3, iclass 34, count 0 2006.281.08:18:02.49#ibcon#read 3, iclass 34, count 0 2006.281.08:18:02.49#ibcon#about to read 4, iclass 34, count 0 2006.281.08:18:02.49#ibcon#read 4, iclass 34, count 0 2006.281.08:18:02.49#ibcon#about to read 5, iclass 34, count 0 2006.281.08:18:02.49#ibcon#read 5, iclass 34, count 0 2006.281.08:18:02.49#ibcon#about to read 6, iclass 34, count 0 2006.281.08:18:02.49#ibcon#read 6, iclass 34, count 0 2006.281.08:18:02.49#ibcon#end of sib2, iclass 34, count 0 2006.281.08:18:02.49#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:18:02.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:18:02.49#ibcon#[27=USB\r\n] 2006.281.08:18:02.49#ibcon#*before write, iclass 34, count 0 2006.281.08:18:02.49#ibcon#enter sib2, iclass 34, count 0 2006.281.08:18:02.49#ibcon#flushed, iclass 34, count 0 2006.281.08:18:02.49#ibcon#about to write, iclass 34, count 0 2006.281.08:18:02.49#ibcon#wrote, iclass 34, count 0 2006.281.08:18:02.49#ibcon#about to read 3, iclass 34, count 0 2006.281.08:18:02.52#ibcon#read 3, iclass 34, count 0 2006.281.08:18:02.52#ibcon#about to read 4, iclass 34, count 0 2006.281.08:18:02.52#ibcon#read 4, iclass 34, count 0 2006.281.08:18:02.52#ibcon#about to read 5, iclass 34, count 0 2006.281.08:18:02.52#ibcon#read 5, iclass 34, count 0 2006.281.08:18:02.52#ibcon#about to read 6, iclass 34, count 0 2006.281.08:18:02.52#ibcon#read 6, iclass 34, count 0 2006.281.08:18:02.52#ibcon#end of sib2, iclass 34, count 0 2006.281.08:18:02.52#ibcon#*after write, iclass 34, count 0 2006.281.08:18:02.52#ibcon#*before return 0, iclass 34, count 0 2006.281.08:18:02.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:18:02.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:18:02.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:18:02.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:18:02.52$vc4f8/vblo=4,712.99 2006.281.08:18:02.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.08:18:02.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.08:18:02.52#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:02.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:18:02.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:18:02.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:18:02.52#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:18:02.52#ibcon#first serial, iclass 36, count 0 2006.281.08:18:02.52#ibcon#enter sib2, iclass 36, count 0 2006.281.08:18:02.52#ibcon#flushed, iclass 36, count 0 2006.281.08:18:02.52#ibcon#about to write, iclass 36, count 0 2006.281.08:18:02.52#ibcon#wrote, iclass 36, count 0 2006.281.08:18:02.52#ibcon#about to read 3, iclass 36, count 0 2006.281.08:18:02.54#ibcon#read 3, iclass 36, count 0 2006.281.08:18:02.54#ibcon#about to read 4, iclass 36, count 0 2006.281.08:18:02.54#ibcon#read 4, iclass 36, count 0 2006.281.08:18:02.54#ibcon#about to read 5, iclass 36, count 0 2006.281.08:18:02.54#ibcon#read 5, iclass 36, count 0 2006.281.08:18:02.54#ibcon#about to read 6, iclass 36, count 0 2006.281.08:18:02.54#ibcon#read 6, iclass 36, count 0 2006.281.08:18:02.54#ibcon#end of sib2, iclass 36, count 0 2006.281.08:18:02.54#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:18:02.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:18:02.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:18:02.56#ibcon#*before write, iclass 36, count 0 2006.281.08:18:02.56#ibcon#enter sib2, iclass 36, count 0 2006.281.08:18:02.56#ibcon#flushed, iclass 36, count 0 2006.281.08:18:02.56#ibcon#about to write, iclass 36, count 0 2006.281.08:18:02.56#ibcon#wrote, iclass 36, count 0 2006.281.08:18:02.56#ibcon#about to read 3, iclass 36, count 0 2006.281.08:18:02.60#ibcon#read 3, iclass 36, count 0 2006.281.08:18:02.60#ibcon#about to read 4, iclass 36, count 0 2006.281.08:18:02.60#ibcon#read 4, iclass 36, count 0 2006.281.08:18:02.60#ibcon#about to read 5, iclass 36, count 0 2006.281.08:18:02.60#ibcon#read 5, iclass 36, count 0 2006.281.08:18:02.60#ibcon#about to read 6, iclass 36, count 0 2006.281.08:18:02.60#ibcon#read 6, iclass 36, count 0 2006.281.08:18:02.60#ibcon#end of sib2, iclass 36, count 0 2006.281.08:18:02.60#ibcon#*after write, iclass 36, count 0 2006.281.08:18:02.60#ibcon#*before return 0, iclass 36, count 0 2006.281.08:18:02.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:18:02.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:18:02.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:18:02.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:18:02.60$vc4f8/vb=4,4 2006.281.08:18:02.60#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.08:18:02.60#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.08:18:02.60#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:02.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:02.64#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:02.64#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:02.64#ibcon#enter wrdev, iclass 38, count 2 2006.281.08:18:02.64#ibcon#first serial, iclass 38, count 2 2006.281.08:18:02.64#ibcon#enter sib2, iclass 38, count 2 2006.281.08:18:02.64#ibcon#flushed, iclass 38, count 2 2006.281.08:18:02.64#ibcon#about to write, iclass 38, count 2 2006.281.08:18:02.64#ibcon#wrote, iclass 38, count 2 2006.281.08:18:02.64#ibcon#about to read 3, iclass 38, count 2 2006.281.08:18:02.66#ibcon#read 3, iclass 38, count 2 2006.281.08:18:02.66#ibcon#about to read 4, iclass 38, count 2 2006.281.08:18:02.66#ibcon#read 4, iclass 38, count 2 2006.281.08:18:02.66#ibcon#about to read 5, iclass 38, count 2 2006.281.08:18:02.66#ibcon#read 5, iclass 38, count 2 2006.281.08:18:02.66#ibcon#about to read 6, iclass 38, count 2 2006.281.08:18:02.66#ibcon#read 6, iclass 38, count 2 2006.281.08:18:02.66#ibcon#end of sib2, iclass 38, count 2 2006.281.08:18:02.66#ibcon#*mode == 0, iclass 38, count 2 2006.281.08:18:02.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.08:18:02.66#ibcon#[27=AT04-04\r\n] 2006.281.08:18:02.66#ibcon#*before write, iclass 38, count 2 2006.281.08:18:02.66#ibcon#enter sib2, iclass 38, count 2 2006.281.08:18:02.66#ibcon#flushed, iclass 38, count 2 2006.281.08:18:02.66#ibcon#about to write, iclass 38, count 2 2006.281.08:18:02.66#ibcon#wrote, iclass 38, count 2 2006.281.08:18:02.66#ibcon#about to read 3, iclass 38, count 2 2006.281.08:18:02.69#ibcon#read 3, iclass 38, count 2 2006.281.08:18:02.69#ibcon#about to read 4, iclass 38, count 2 2006.281.08:18:02.69#ibcon#read 4, iclass 38, count 2 2006.281.08:18:02.69#ibcon#about to read 5, iclass 38, count 2 2006.281.08:18:02.69#ibcon#read 5, iclass 38, count 2 2006.281.08:18:02.69#ibcon#about to read 6, iclass 38, count 2 2006.281.08:18:02.69#ibcon#read 6, iclass 38, count 2 2006.281.08:18:02.69#ibcon#end of sib2, iclass 38, count 2 2006.281.08:18:02.69#ibcon#*after write, iclass 38, count 2 2006.281.08:18:02.69#ibcon#*before return 0, iclass 38, count 2 2006.281.08:18:02.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:02.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:18:02.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.08:18:02.69#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:02.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:02.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:02.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:02.81#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:18:02.81#ibcon#first serial, iclass 38, count 0 2006.281.08:18:02.81#ibcon#enter sib2, iclass 38, count 0 2006.281.08:18:02.81#ibcon#flushed, iclass 38, count 0 2006.281.08:18:02.81#ibcon#about to write, iclass 38, count 0 2006.281.08:18:02.81#ibcon#wrote, iclass 38, count 0 2006.281.08:18:02.81#ibcon#about to read 3, iclass 38, count 0 2006.281.08:18:02.83#ibcon#read 3, iclass 38, count 0 2006.281.08:18:02.83#ibcon#about to read 4, iclass 38, count 0 2006.281.08:18:02.83#ibcon#read 4, iclass 38, count 0 2006.281.08:18:02.83#ibcon#about to read 5, iclass 38, count 0 2006.281.08:18:02.83#ibcon#read 5, iclass 38, count 0 2006.281.08:18:02.83#ibcon#about to read 6, iclass 38, count 0 2006.281.08:18:02.83#ibcon#read 6, iclass 38, count 0 2006.281.08:18:02.83#ibcon#end of sib2, iclass 38, count 0 2006.281.08:18:02.83#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:18:02.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:18:02.83#ibcon#[27=USB\r\n] 2006.281.08:18:02.83#ibcon#*before write, iclass 38, count 0 2006.281.08:18:02.83#ibcon#enter sib2, iclass 38, count 0 2006.281.08:18:02.83#ibcon#flushed, iclass 38, count 0 2006.281.08:18:02.83#ibcon#about to write, iclass 38, count 0 2006.281.08:18:02.83#ibcon#wrote, iclass 38, count 0 2006.281.08:18:02.83#ibcon#about to read 3, iclass 38, count 0 2006.281.08:18:02.86#ibcon#read 3, iclass 38, count 0 2006.281.08:18:02.86#ibcon#about to read 4, iclass 38, count 0 2006.281.08:18:02.86#ibcon#read 4, iclass 38, count 0 2006.281.08:18:02.86#ibcon#about to read 5, iclass 38, count 0 2006.281.08:18:02.86#ibcon#read 5, iclass 38, count 0 2006.281.08:18:02.86#ibcon#about to read 6, iclass 38, count 0 2006.281.08:18:02.86#ibcon#read 6, iclass 38, count 0 2006.281.08:18:02.86#ibcon#end of sib2, iclass 38, count 0 2006.281.08:18:02.86#ibcon#*after write, iclass 38, count 0 2006.281.08:18:02.86#ibcon#*before return 0, iclass 38, count 0 2006.281.08:18:02.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:02.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:18:02.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:18:02.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:18:02.86$vc4f8/vblo=5,744.99 2006.281.08:18:02.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:18:02.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:18:02.86#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:02.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:02.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:02.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:02.86#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:18:02.86#ibcon#first serial, iclass 40, count 0 2006.281.08:18:02.86#ibcon#enter sib2, iclass 40, count 0 2006.281.08:18:02.86#ibcon#flushed, iclass 40, count 0 2006.281.08:18:02.86#ibcon#about to write, iclass 40, count 0 2006.281.08:18:02.86#ibcon#wrote, iclass 40, count 0 2006.281.08:18:02.86#ibcon#about to read 3, iclass 40, count 0 2006.281.08:18:02.88#ibcon#read 3, iclass 40, count 0 2006.281.08:18:02.88#ibcon#about to read 4, iclass 40, count 0 2006.281.08:18:02.88#ibcon#read 4, iclass 40, count 0 2006.281.08:18:02.88#ibcon#about to read 5, iclass 40, count 0 2006.281.08:18:02.88#ibcon#read 5, iclass 40, count 0 2006.281.08:18:02.88#ibcon#about to read 6, iclass 40, count 0 2006.281.08:18:02.88#ibcon#read 6, iclass 40, count 0 2006.281.08:18:02.88#ibcon#end of sib2, iclass 40, count 0 2006.281.08:18:02.88#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:18:02.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:18:02.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:18:02.88#ibcon#*before write, iclass 40, count 0 2006.281.08:18:02.88#ibcon#enter sib2, iclass 40, count 0 2006.281.08:18:02.88#ibcon#flushed, iclass 40, count 0 2006.281.08:18:02.88#ibcon#about to write, iclass 40, count 0 2006.281.08:18:02.88#ibcon#wrote, iclass 40, count 0 2006.281.08:18:02.88#ibcon#about to read 3, iclass 40, count 0 2006.281.08:18:02.93#ibcon#read 3, iclass 40, count 0 2006.281.08:18:02.93#ibcon#about to read 4, iclass 40, count 0 2006.281.08:18:02.93#ibcon#read 4, iclass 40, count 0 2006.281.08:18:02.93#ibcon#about to read 5, iclass 40, count 0 2006.281.08:18:02.93#ibcon#read 5, iclass 40, count 0 2006.281.08:18:02.93#ibcon#about to read 6, iclass 40, count 0 2006.281.08:18:02.93#ibcon#read 6, iclass 40, count 0 2006.281.08:18:02.93#ibcon#end of sib2, iclass 40, count 0 2006.281.08:18:02.93#ibcon#*after write, iclass 40, count 0 2006.281.08:18:02.93#ibcon#*before return 0, iclass 40, count 0 2006.281.08:18:02.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:02.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:18:02.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:18:02.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:18:02.93$vc4f8/vb=5,4 2006.281.08:18:02.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.08:18:02.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.08:18:02.93#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:02.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:02.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:02.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:02.97#ibcon#enter wrdev, iclass 4, count 2 2006.281.08:18:02.97#ibcon#first serial, iclass 4, count 2 2006.281.08:18:02.97#ibcon#enter sib2, iclass 4, count 2 2006.281.08:18:02.97#ibcon#flushed, iclass 4, count 2 2006.281.08:18:02.97#ibcon#about to write, iclass 4, count 2 2006.281.08:18:02.97#ibcon#wrote, iclass 4, count 2 2006.281.08:18:02.97#ibcon#about to read 3, iclass 4, count 2 2006.281.08:18:02.99#ibcon#read 3, iclass 4, count 2 2006.281.08:18:02.99#ibcon#about to read 4, iclass 4, count 2 2006.281.08:18:02.99#ibcon#read 4, iclass 4, count 2 2006.281.08:18:02.99#ibcon#about to read 5, iclass 4, count 2 2006.281.08:18:02.99#ibcon#read 5, iclass 4, count 2 2006.281.08:18:02.99#ibcon#about to read 6, iclass 4, count 2 2006.281.08:18:02.99#ibcon#read 6, iclass 4, count 2 2006.281.08:18:02.99#ibcon#end of sib2, iclass 4, count 2 2006.281.08:18:02.99#ibcon#*mode == 0, iclass 4, count 2 2006.281.08:18:02.99#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.08:18:02.99#ibcon#[27=AT05-04\r\n] 2006.281.08:18:02.99#ibcon#*before write, iclass 4, count 2 2006.281.08:18:02.99#ibcon#enter sib2, iclass 4, count 2 2006.281.08:18:02.99#ibcon#flushed, iclass 4, count 2 2006.281.08:18:02.99#ibcon#about to write, iclass 4, count 2 2006.281.08:18:02.99#ibcon#wrote, iclass 4, count 2 2006.281.08:18:02.99#ibcon#about to read 3, iclass 4, count 2 2006.281.08:18:03.02#ibcon#read 3, iclass 4, count 2 2006.281.08:18:03.02#ibcon#about to read 4, iclass 4, count 2 2006.281.08:18:03.02#ibcon#read 4, iclass 4, count 2 2006.281.08:18:03.02#ibcon#about to read 5, iclass 4, count 2 2006.281.08:18:03.02#ibcon#read 5, iclass 4, count 2 2006.281.08:18:03.02#ibcon#about to read 6, iclass 4, count 2 2006.281.08:18:03.02#ibcon#read 6, iclass 4, count 2 2006.281.08:18:03.02#ibcon#end of sib2, iclass 4, count 2 2006.281.08:18:03.02#ibcon#*after write, iclass 4, count 2 2006.281.08:18:03.02#ibcon#*before return 0, iclass 4, count 2 2006.281.08:18:03.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:03.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:18:03.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.08:18:03.02#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:03.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:03.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:03.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:03.14#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:18:03.14#ibcon#first serial, iclass 4, count 0 2006.281.08:18:03.14#ibcon#enter sib2, iclass 4, count 0 2006.281.08:18:03.14#ibcon#flushed, iclass 4, count 0 2006.281.08:18:03.14#ibcon#about to write, iclass 4, count 0 2006.281.08:18:03.14#ibcon#wrote, iclass 4, count 0 2006.281.08:18:03.14#ibcon#about to read 3, iclass 4, count 0 2006.281.08:18:03.16#ibcon#read 3, iclass 4, count 0 2006.281.08:18:03.16#ibcon#about to read 4, iclass 4, count 0 2006.281.08:18:03.16#ibcon#read 4, iclass 4, count 0 2006.281.08:18:03.16#ibcon#about to read 5, iclass 4, count 0 2006.281.08:18:03.16#ibcon#read 5, iclass 4, count 0 2006.281.08:18:03.16#ibcon#about to read 6, iclass 4, count 0 2006.281.08:18:03.16#ibcon#read 6, iclass 4, count 0 2006.281.08:18:03.16#ibcon#end of sib2, iclass 4, count 0 2006.281.08:18:03.16#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:18:03.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:18:03.16#ibcon#[27=USB\r\n] 2006.281.08:18:03.16#ibcon#*before write, iclass 4, count 0 2006.281.08:18:03.16#ibcon#enter sib2, iclass 4, count 0 2006.281.08:18:03.16#ibcon#flushed, iclass 4, count 0 2006.281.08:18:03.16#ibcon#about to write, iclass 4, count 0 2006.281.08:18:03.16#ibcon#wrote, iclass 4, count 0 2006.281.08:18:03.16#ibcon#about to read 3, iclass 4, count 0 2006.281.08:18:03.19#ibcon#read 3, iclass 4, count 0 2006.281.08:18:03.19#ibcon#about to read 4, iclass 4, count 0 2006.281.08:18:03.19#ibcon#read 4, iclass 4, count 0 2006.281.08:18:03.19#ibcon#about to read 5, iclass 4, count 0 2006.281.08:18:03.19#ibcon#read 5, iclass 4, count 0 2006.281.08:18:03.19#ibcon#about to read 6, iclass 4, count 0 2006.281.08:18:03.19#ibcon#read 6, iclass 4, count 0 2006.281.08:18:03.19#ibcon#end of sib2, iclass 4, count 0 2006.281.08:18:03.19#ibcon#*after write, iclass 4, count 0 2006.281.08:18:03.19#ibcon#*before return 0, iclass 4, count 0 2006.281.08:18:03.19#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:03.19#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:18:03.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:18:03.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:18:03.19$vc4f8/vblo=6,752.99 2006.281.08:18:03.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:18:03.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:18:03.19#ibcon#ireg 17 cls_cnt 0 2006.281.08:18:03.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:18:03.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:18:03.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:18:03.19#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:18:03.19#ibcon#first serial, iclass 6, count 0 2006.281.08:18:03.19#ibcon#enter sib2, iclass 6, count 0 2006.281.08:18:03.19#ibcon#flushed, iclass 6, count 0 2006.281.08:18:03.19#ibcon#about to write, iclass 6, count 0 2006.281.08:18:03.19#ibcon#wrote, iclass 6, count 0 2006.281.08:18:03.19#ibcon#about to read 3, iclass 6, count 0 2006.281.08:18:03.21#ibcon#read 3, iclass 6, count 0 2006.281.08:18:03.21#ibcon#about to read 4, iclass 6, count 0 2006.281.08:18:03.21#ibcon#read 4, iclass 6, count 0 2006.281.08:18:03.21#ibcon#about to read 5, iclass 6, count 0 2006.281.08:18:03.21#ibcon#read 5, iclass 6, count 0 2006.281.08:18:03.21#ibcon#about to read 6, iclass 6, count 0 2006.281.08:18:03.21#ibcon#read 6, iclass 6, count 0 2006.281.08:18:03.21#ibcon#end of sib2, iclass 6, count 0 2006.281.08:18:03.21#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:18:03.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:18:03.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:18:03.21#ibcon#*before write, iclass 6, count 0 2006.281.08:18:03.21#ibcon#enter sib2, iclass 6, count 0 2006.281.08:18:03.21#ibcon#flushed, iclass 6, count 0 2006.281.08:18:03.21#ibcon#about to write, iclass 6, count 0 2006.281.08:18:03.21#ibcon#wrote, iclass 6, count 0 2006.281.08:18:03.21#ibcon#about to read 3, iclass 6, count 0 2006.281.08:18:03.25#ibcon#read 3, iclass 6, count 0 2006.281.08:18:03.25#ibcon#about to read 4, iclass 6, count 0 2006.281.08:18:03.25#ibcon#read 4, iclass 6, count 0 2006.281.08:18:03.25#ibcon#about to read 5, iclass 6, count 0 2006.281.08:18:03.25#ibcon#read 5, iclass 6, count 0 2006.281.08:18:03.25#ibcon#about to read 6, iclass 6, count 0 2006.281.08:18:03.25#ibcon#read 6, iclass 6, count 0 2006.281.08:18:03.25#ibcon#end of sib2, iclass 6, count 0 2006.281.08:18:03.25#ibcon#*after write, iclass 6, count 0 2006.281.08:18:03.25#ibcon#*before return 0, iclass 6, count 0 2006.281.08:18:03.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:18:03.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:18:03.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:18:03.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:18:03.25$vc4f8/vb=6,4 2006.281.08:18:03.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:18:03.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:18:03.27#ibcon#ireg 11 cls_cnt 2 2006.281.08:18:03.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:18:03.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:18:03.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:18:03.30#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:18:03.30#ibcon#first serial, iclass 10, count 2 2006.281.08:18:03.30#ibcon#enter sib2, iclass 10, count 2 2006.281.08:18:03.30#ibcon#flushed, iclass 10, count 2 2006.281.08:18:03.30#ibcon#about to write, iclass 10, count 2 2006.281.08:18:03.30#ibcon#wrote, iclass 10, count 2 2006.281.08:18:03.30#ibcon#about to read 3, iclass 10, count 2 2006.281.08:18:03.33#ibcon#read 3, iclass 10, count 2 2006.281.08:18:03.33#ibcon#about to read 4, iclass 10, count 2 2006.281.08:18:03.33#ibcon#read 4, iclass 10, count 2 2006.281.08:18:03.33#ibcon#about to read 5, iclass 10, count 2 2006.281.08:18:03.33#ibcon#read 5, iclass 10, count 2 2006.281.08:18:03.33#ibcon#about to read 6, iclass 10, count 2 2006.281.08:18:03.33#ibcon#read 6, iclass 10, count 2 2006.281.08:18:03.33#ibcon#end of sib2, iclass 10, count 2 2006.281.08:18:03.33#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:18:03.33#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:18:03.33#ibcon#[27=AT06-04\r\n] 2006.281.08:18:03.33#ibcon#*before write, iclass 10, count 2 2006.281.08:18:03.33#ibcon#enter sib2, iclass 10, count 2 2006.281.08:18:03.33#ibcon#flushed, iclass 10, count 2 2006.281.08:18:03.33#ibcon#about to write, iclass 10, count 2 2006.281.08:18:03.33#ibcon#wrote, iclass 10, count 2 2006.281.08:18:03.33#ibcon#about to read 3, iclass 10, count 2 2006.281.08:18:03.35#ibcon#read 3, iclass 10, count 2 2006.281.08:18:03.35#ibcon#about to read 4, iclass 10, count 2 2006.281.08:18:03.35#ibcon#read 4, iclass 10, count 2 2006.281.08:18:03.35#ibcon#about to read 5, iclass 10, count 2 2006.281.08:18:03.35#ibcon#read 5, iclass 10, count 2 2006.281.08:18:03.35#ibcon#about to read 6, iclass 10, count 2 2006.281.08:18:03.35#ibcon#read 6, iclass 10, count 2 2006.281.08:18:03.35#ibcon#end of sib2, iclass 10, count 2 2006.281.08:18:03.35#ibcon#*after write, iclass 10, count 2 2006.281.08:18:03.35#ibcon#*before return 0, iclass 10, count 2 2006.281.08:18:03.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:18:03.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:18:03.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:18:03.35#ibcon#ireg 7 cls_cnt 0 2006.281.08:18:03.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:18:03.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:18:03.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:18:03.47#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:18:03.47#ibcon#first serial, iclass 10, count 0 2006.281.08:18:03.47#ibcon#enter sib2, iclass 10, count 0 2006.281.08:18:03.47#ibcon#flushed, iclass 10, count 0 2006.281.08:18:03.47#ibcon#about to write, iclass 10, count 0 2006.281.08:18:03.47#ibcon#wrote, iclass 10, count 0 2006.281.08:18:03.47#ibcon#about to read 3, iclass 10, count 0 2006.281.08:18:03.49#ibcon#read 3, iclass 10, count 0 2006.281.08:18:03.49#ibcon#about to read 4, iclass 10, count 0 2006.281.08:18:03.49#ibcon#read 4, iclass 10, count 0 2006.281.08:18:03.49#ibcon#about to read 5, iclass 10, count 0 2006.281.08:18:03.49#ibcon#read 5, iclass 10, count 0 2006.281.08:18:03.49#ibcon#about to read 6, iclass 10, count 0 2006.281.08:18:03.49#ibcon#read 6, iclass 10, count 0 2006.281.08:18:03.49#ibcon#end of sib2, iclass 10, count 0 2006.281.08:18:03.49#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:18:03.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:18:03.49#ibcon#[27=USB\r\n] 2006.281.08:18:03.49#ibcon#*before write, iclass 10, count 0 2006.281.08:18:03.49#ibcon#enter sib2, iclass 10, count 0 2006.281.08:18:03.49#ibcon#flushed, iclass 10, count 0 2006.281.08:18:03.49#ibcon#about to write, iclass 10, count 0 2006.281.08:18:03.49#ibcon#wrote, iclass 10, count 0 2006.281.08:18:03.49#ibcon#about to read 3, iclass 10, count 0 2006.281.08:18:03.53#ibcon#read 3, iclass 10, count 0 2006.281.08:18:03.53#ibcon#about to read 4, iclass 10, count 0 2006.281.08:18:03.53#ibcon#read 4, iclass 10, count 0 2006.281.08:18:03.53#ibcon#about to read 5, iclass 10, count 0 2006.281.08:18:03.53#ibcon#read 5, iclass 10, count 0 2006.281.08:18:03.53#ibcon#about to read 6, iclass 10, count 0 2006.281.08:18:03.53#ibcon#read 6, iclass 10, count 0 2006.281.08:18:03.53#ibcon#end of sib2, iclass 10, count 0 2006.281.08:18:03.53#ibcon#*after write, iclass 10, count 0 2006.281.08:18:03.53#ibcon#*before return 0, iclass 10, count 0 2006.281.08:18:03.53#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:18:03.53#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:18:03.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:18:03.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:18:03.53$vc4f8/vabw=wide 2006.281.08:18:03.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:18:03.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:18:03.53#ibcon#ireg 8 cls_cnt 0 2006.281.08:18:03.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:03.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:03.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:03.53#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:18:03.53#ibcon#first serial, iclass 12, count 0 2006.281.08:18:03.53#ibcon#enter sib2, iclass 12, count 0 2006.281.08:18:03.53#ibcon#flushed, iclass 12, count 0 2006.281.08:18:03.53#ibcon#about to write, iclass 12, count 0 2006.281.08:18:03.53#ibcon#wrote, iclass 12, count 0 2006.281.08:18:03.53#ibcon#about to read 3, iclass 12, count 0 2006.281.08:18:03.54#ibcon#read 3, iclass 12, count 0 2006.281.08:18:03.54#ibcon#about to read 4, iclass 12, count 0 2006.281.08:18:03.54#ibcon#read 4, iclass 12, count 0 2006.281.08:18:03.55#ibcon#about to read 5, iclass 12, count 0 2006.281.08:18:03.55#ibcon#read 5, iclass 12, count 0 2006.281.08:18:03.55#ibcon#about to read 6, iclass 12, count 0 2006.281.08:18:03.55#ibcon#read 6, iclass 12, count 0 2006.281.08:18:03.55#ibcon#end of sib2, iclass 12, count 0 2006.281.08:18:03.55#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:18:03.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:18:03.55#ibcon#[25=BW32\r\n] 2006.281.08:18:03.55#ibcon#*before write, iclass 12, count 0 2006.281.08:18:03.55#ibcon#enter sib2, iclass 12, count 0 2006.281.08:18:03.55#ibcon#flushed, iclass 12, count 0 2006.281.08:18:03.55#ibcon#about to write, iclass 12, count 0 2006.281.08:18:03.56#ibcon#wrote, iclass 12, count 0 2006.281.08:18:03.56#ibcon#about to read 3, iclass 12, count 0 2006.281.08:18:03.59#ibcon#read 3, iclass 12, count 0 2006.281.08:18:03.59#ibcon#about to read 4, iclass 12, count 0 2006.281.08:18:03.59#ibcon#read 4, iclass 12, count 0 2006.281.08:18:03.59#ibcon#about to read 5, iclass 12, count 0 2006.281.08:18:03.59#ibcon#read 5, iclass 12, count 0 2006.281.08:18:03.59#ibcon#about to read 6, iclass 12, count 0 2006.281.08:18:03.59#ibcon#read 6, iclass 12, count 0 2006.281.08:18:03.59#ibcon#end of sib2, iclass 12, count 0 2006.281.08:18:03.59#ibcon#*after write, iclass 12, count 0 2006.281.08:18:03.59#ibcon#*before return 0, iclass 12, count 0 2006.281.08:18:03.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:03.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:18:03.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:18:03.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:18:03.59$vc4f8/vbbw=wide 2006.281.08:18:03.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:18:03.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:18:03.59#ibcon#ireg 8 cls_cnt 0 2006.281.08:18:03.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:18:03.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:18:03.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:18:03.65#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:18:03.65#ibcon#first serial, iclass 14, count 0 2006.281.08:18:03.65#ibcon#enter sib2, iclass 14, count 0 2006.281.08:18:03.65#ibcon#flushed, iclass 14, count 0 2006.281.08:18:03.65#ibcon#about to write, iclass 14, count 0 2006.281.08:18:03.65#ibcon#wrote, iclass 14, count 0 2006.281.08:18:03.65#ibcon#about to read 3, iclass 14, count 0 2006.281.08:18:03.67#ibcon#read 3, iclass 14, count 0 2006.281.08:18:03.67#ibcon#about to read 4, iclass 14, count 0 2006.281.08:18:03.67#ibcon#read 4, iclass 14, count 0 2006.281.08:18:03.67#ibcon#about to read 5, iclass 14, count 0 2006.281.08:18:03.67#ibcon#read 5, iclass 14, count 0 2006.281.08:18:03.67#ibcon#about to read 6, iclass 14, count 0 2006.281.08:18:03.67#ibcon#read 6, iclass 14, count 0 2006.281.08:18:03.67#ibcon#end of sib2, iclass 14, count 0 2006.281.08:18:03.67#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:18:03.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:18:03.67#ibcon#[27=BW32\r\n] 2006.281.08:18:03.67#ibcon#*before write, iclass 14, count 0 2006.281.08:18:03.67#ibcon#enter sib2, iclass 14, count 0 2006.281.08:18:03.67#ibcon#flushed, iclass 14, count 0 2006.281.08:18:03.67#ibcon#about to write, iclass 14, count 0 2006.281.08:18:03.67#ibcon#wrote, iclass 14, count 0 2006.281.08:18:03.67#ibcon#about to read 3, iclass 14, count 0 2006.281.08:18:03.70#ibcon#read 3, iclass 14, count 0 2006.281.08:18:03.70#ibcon#about to read 4, iclass 14, count 0 2006.281.08:18:03.70#ibcon#read 4, iclass 14, count 0 2006.281.08:18:03.70#ibcon#about to read 5, iclass 14, count 0 2006.281.08:18:03.70#ibcon#read 5, iclass 14, count 0 2006.281.08:18:03.70#ibcon#about to read 6, iclass 14, count 0 2006.281.08:18:03.70#ibcon#read 6, iclass 14, count 0 2006.281.08:18:03.70#ibcon#end of sib2, iclass 14, count 0 2006.281.08:18:03.70#ibcon#*after write, iclass 14, count 0 2006.281.08:18:03.70#ibcon#*before return 0, iclass 14, count 0 2006.281.08:18:03.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:18:03.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:18:03.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:18:03.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:18:03.70$4f8m12a/ifd4f 2006.281.08:18:03.70$ifd4f/lo= 2006.281.08:18:03.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:18:03.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:18:03.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:18:03.70$ifd4f/patch= 2006.281.08:18:03.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:18:03.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:18:03.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:18:03.71$4f8m12a/"form=m,16.000,1:2 2006.281.08:18:03.71$4f8m12a/"tpicd 2006.281.08:18:03.71$4f8m12a/echo=off 2006.281.08:18:03.71$4f8m12a/xlog=off 2006.281.08:18:03.71:!2006.281.08:19:30 2006.281.08:18:19.14#trakl#Source acquired 2006.281.08:18:21.14#flagr#flagr/antenna,acquired 2006.281.08:18:24.14#trakl#Off source 2006.281.08:18:24.14?ERROR st -7 Antenna off-source! 2006.281.08:18:24.14#trakl#az 257.984 el 12.470 azerr*cos(el) -0.0002 elerr -0.0212 2006.281.08:18:24.14#flagr#flagr/antenna,off-source 2006.281.08:18:31.14#trakl#Source re-acquired 2006.281.08:18:33.14#flagr#flagr/antenna,re-acquired 2006.281.08:18:57.14#trakl#Off source 2006.281.08:18:57.14?ERROR st -7 Antenna off-source! 2006.281.08:18:57.14#trakl#az 258.071 el 12.362 azerr*cos(el) -0.0015 elerr -0.0209 2006.281.08:18:57.14#flagr#flagr/antenna,off-source 2006.281.08:19:03.14#trakl#Source re-acquired 2006.281.08:19:03.14#flagr#flagr/antenna,re-acquired 2006.281.08:19:27.14#trakl#Off source 2006.281.08:19:27.14?ERROR st -7 Antenna off-source! 2006.281.08:19:27.14#trakl#az 258.149 el 12.264 azerr*cos(el) 0.0176 elerr -0.0005 2006.281.08:19:27.14#flagr#flagr/antenna,off-source 2006.281.08:19:30.01:preob 2006.281.08:19:31.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.281.08:19:31.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.281.08:19:31.14/onsource/SLEWING 2006.281.08:19:31.14:!2006.281.08:19:40 2006.281.08:19:34.14#trakl#Source re-acquired 2006.281.08:19:35.14#flagr#flagr/antenna,re-acquired 2006.281.08:19:40.00:data_valid=on 2006.281.08:19:40.00:midob 2006.281.08:19:40.14/onsource/TRACKING 2006.281.08:19:40.14/wx/19.99,1001.7,52 2006.281.08:19:40.24/cable/+6.4887E-03 2006.281.08:19:41.33/va/01,07,usb,yes,36,38 2006.281.08:19:41.33/va/02,06,usb,yes,34,35 2006.281.08:19:41.33/va/03,06,usb,yes,32,32 2006.281.08:19:41.33/va/04,06,usb,yes,35,37 2006.281.08:19:41.33/va/05,07,usb,yes,33,35 2006.281.08:19:41.33/va/06,06,usb,yes,33,32 2006.281.08:19:41.33/va/07,06,usb,yes,33,33 2006.281.08:19:41.33/va/08,06,usb,yes,35,35 2006.281.08:19:41.56/valo/01,532.99,yes,locked 2006.281.08:19:41.56/valo/02,572.99,yes,locked 2006.281.08:19:41.56/valo/03,672.99,yes,locked 2006.281.08:19:41.56/valo/04,832.99,yes,locked 2006.281.08:19:41.56/valo/05,652.99,yes,locked 2006.281.08:19:41.56/valo/06,772.99,yes,locked 2006.281.08:19:41.56/valo/07,832.99,yes,locked 2006.281.08:19:41.56/valo/08,852.99,yes,locked 2006.281.08:19:42.65/vb/01,04,usb,yes,27,26 2006.281.08:19:42.65/vb/02,05,usb,yes,25,26 2006.281.08:19:42.65/vb/03,04,usb,yes,25,29 2006.281.08:19:42.65/vb/04,04,usb,yes,26,26 2006.281.08:19:42.65/vb/05,04,usb,yes,24,28 2006.281.08:19:42.65/vb/06,04,usb,yes,25,28 2006.281.08:19:42.65/vb/07,04,usb,yes,27,27 2006.281.08:19:42.65/vb/08,04,usb,yes,25,28 2006.281.08:19:42.89/vblo/01,632.99,yes,locked 2006.281.08:19:42.89/vblo/02,640.99,yes,locked 2006.281.08:19:42.89/vblo/03,656.99,yes,locked 2006.281.08:19:42.89/vblo/04,712.99,yes,locked 2006.281.08:19:42.89/vblo/05,744.99,yes,locked 2006.281.08:19:42.89/vblo/06,752.99,yes,locked 2006.281.08:19:42.89/vblo/07,734.99,yes,locked 2006.281.08:19:42.89/vblo/08,744.99,yes,locked 2006.281.08:19:43.04/vabw/8 2006.281.08:19:43.19/vbbw/8 2006.281.08:19:43.28/xfe/off,on,12.0 2006.281.08:19:43.66/ifatt/23,28,28,28 2006.281.08:19:44.08/fmout-gps/S +3.13E-07 2006.281.08:19:44.11:!2006.281.08:20:40 2006.281.08:19:51.14#trakl#Off source 2006.281.08:19:51.14?ERROR st -7 Antenna off-source! 2006.281.08:19:51.14#trakl#az 258.212 el 12.185 azerr*cos(el) 0.0003 elerr -0.0327 2006.281.08:19:51.14#flagr#flagr/antenna,off-source 2006.281.08:20:06.14#trakl#Off source 2006.281.08:20:06.14?ERROR st -7 Antenna off-source! 2006.281.08:20:06.14#trakl#az 258.251 el 12.136 azerr*cos(el) 0.0011 elerr -0.0075 2006.281.08:20:08.14#trakl#Source re-acquired 2006.281.08:20:09.14#flagr#flagr/antenna,re-acquired 2006.281.08:20:15.14#trakl#Off source 2006.281.08:20:15.14?ERROR st -7 Antenna off-source! 2006.281.08:20:15.14#trakl#az 258.274 el 12.106 azerr*cos(el) 0.0182 elerr 0.0240 2006.281.08:20:15.14#flagr#flagr/antenna,off-source 2006.281.08:20:23.14#trakl#Source re-acquired 2006.281.08:20:24.14#flagr#flagr/antenna,re-acquired 2006.281.08:20:26.14#trakl#Off source 2006.281.08:20:26.14?ERROR st -7 Antenna off-source! 2006.281.08:20:26.14#trakl#az 258.303 el 12.070 azerr*cos(el) 0.0068 elerr -0.0269 2006.281.08:20:27.14#flagr#flagr/antenna,off-source 2006.281.08:20:35.14#trakl#Source re-acquired 2006.281.08:20:36.14#flagr#flagr/antenna,re-acquired 2006.281.08:20:40.01:data_valid=off 2006.281.08:20:40.01:postob 2006.281.08:20:40.07/cable/+6.4883E-03 2006.281.08:20:40.07/wx/19.96,1001.7,53 2006.281.08:20:41.07/fmout-gps/S +3.13E-07 2006.281.08:20:41.07:scan_name=281-0823,k06281,60 2006.281.08:20:41.07:source=0133+476,013658.59,475129.1,2000.0,cw 2006.281.08:20:41.14#flagr#flagr/antenna,new-source 2006.281.08:20:42.14:checkk5 2006.281.08:20:42.58/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:20:43.02/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:20:43.44/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:20:43.84/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:20:44.23/chk_obsdata//k5ts1/T2810819??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:20:44.63/chk_obsdata//k5ts2/T2810819??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:20:45.03/chk_obsdata//k5ts3/T2810819??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:20:45.42/chk_obsdata//k5ts4/T2810819??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:20:46.18/k5log//k5ts1_log_newline 2006.281.08:20:47.26/k5log//k5ts2_log_newline 2006.281.08:20:48.05/k5log//k5ts3_log_newline 2006.281.08:20:48.82/k5log//k5ts4_log_newline 2006.281.08:20:48.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:20:48.85:4f8m12a=3 2006.281.08:20:48.85$4f8m12a/echo=on 2006.281.08:20:48.85$4f8m12a/pcalon 2006.281.08:20:48.85$pcalon/"no phase cal control is implemented here 2006.281.08:20:48.85$4f8m12a/"tpicd=stop 2006.281.08:20:48.85$4f8m12a/vc4f8 2006.281.08:20:48.85$vc4f8/valo=1,532.99 2006.281.08:20:48.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.08:20:48.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.08:20:48.85#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:48.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:48.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:48.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:48.85#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:20:48.85#ibcon#first serial, iclass 27, count 0 2006.281.08:20:48.85#ibcon#enter sib2, iclass 27, count 0 2006.281.08:20:48.85#ibcon#flushed, iclass 27, count 0 2006.281.08:20:48.85#ibcon#about to write, iclass 27, count 0 2006.281.08:20:48.85#ibcon#wrote, iclass 27, count 0 2006.281.08:20:48.85#ibcon#about to read 3, iclass 27, count 0 2006.281.08:20:48.86#ibcon#read 3, iclass 27, count 0 2006.281.08:20:48.86#ibcon#about to read 4, iclass 27, count 0 2006.281.08:20:48.86#ibcon#read 4, iclass 27, count 0 2006.281.08:20:48.86#ibcon#about to read 5, iclass 27, count 0 2006.281.08:20:48.86#ibcon#read 5, iclass 27, count 0 2006.281.08:20:48.86#ibcon#about to read 6, iclass 27, count 0 2006.281.08:20:48.86#ibcon#read 6, iclass 27, count 0 2006.281.08:20:48.86#ibcon#end of sib2, iclass 27, count 0 2006.281.08:20:48.86#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:20:48.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:20:48.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:20:48.86#ibcon#*before write, iclass 27, count 0 2006.281.08:20:48.86#ibcon#enter sib2, iclass 27, count 0 2006.281.08:20:48.86#ibcon#flushed, iclass 27, count 0 2006.281.08:20:48.86#ibcon#about to write, iclass 27, count 0 2006.281.08:20:48.86#ibcon#wrote, iclass 27, count 0 2006.281.08:20:48.86#ibcon#about to read 3, iclass 27, count 0 2006.281.08:20:48.92#ibcon#read 3, iclass 27, count 0 2006.281.08:20:48.92#ibcon#about to read 4, iclass 27, count 0 2006.281.08:20:48.92#ibcon#read 4, iclass 27, count 0 2006.281.08:20:48.92#ibcon#about to read 5, iclass 27, count 0 2006.281.08:20:48.92#ibcon#read 5, iclass 27, count 0 2006.281.08:20:48.92#ibcon#about to read 6, iclass 27, count 0 2006.281.08:20:48.92#ibcon#read 6, iclass 27, count 0 2006.281.08:20:48.92#ibcon#end of sib2, iclass 27, count 0 2006.281.08:20:48.92#ibcon#*after write, iclass 27, count 0 2006.281.08:20:48.92#ibcon#*before return 0, iclass 27, count 0 2006.281.08:20:48.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:48.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:48.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:20:48.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:20:48.92$vc4f8/va=1,7 2006.281.08:20:48.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.08:20:48.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.08:20:48.92#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:48.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:48.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:48.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:48.92#ibcon#enter wrdev, iclass 29, count 2 2006.281.08:20:48.92#ibcon#first serial, iclass 29, count 2 2006.281.08:20:48.92#ibcon#enter sib2, iclass 29, count 2 2006.281.08:20:48.92#ibcon#flushed, iclass 29, count 2 2006.281.08:20:48.92#ibcon#about to write, iclass 29, count 2 2006.281.08:20:48.92#ibcon#wrote, iclass 29, count 2 2006.281.08:20:48.92#ibcon#about to read 3, iclass 29, count 2 2006.281.08:20:48.93#ibcon#read 3, iclass 29, count 2 2006.281.08:20:48.94#ibcon#about to read 4, iclass 29, count 2 2006.281.08:20:48.94#ibcon#read 4, iclass 29, count 2 2006.281.08:20:48.94#ibcon#about to read 5, iclass 29, count 2 2006.281.08:20:48.94#ibcon#read 5, iclass 29, count 2 2006.281.08:20:48.94#ibcon#about to read 6, iclass 29, count 2 2006.281.08:20:48.94#ibcon#read 6, iclass 29, count 2 2006.281.08:20:48.94#ibcon#end of sib2, iclass 29, count 2 2006.281.08:20:48.94#ibcon#*mode == 0, iclass 29, count 2 2006.281.08:20:48.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.08:20:48.94#ibcon#[25=AT01-07\r\n] 2006.281.08:20:48.94#ibcon#*before write, iclass 29, count 2 2006.281.08:20:48.94#ibcon#enter sib2, iclass 29, count 2 2006.281.08:20:48.94#ibcon#flushed, iclass 29, count 2 2006.281.08:20:48.94#ibcon#about to write, iclass 29, count 2 2006.281.08:20:48.94#ibcon#wrote, iclass 29, count 2 2006.281.08:20:48.94#ibcon#about to read 3, iclass 29, count 2 2006.281.08:20:48.97#ibcon#read 3, iclass 29, count 2 2006.281.08:20:48.97#ibcon#about to read 4, iclass 29, count 2 2006.281.08:20:48.97#ibcon#read 4, iclass 29, count 2 2006.281.08:20:48.97#ibcon#about to read 5, iclass 29, count 2 2006.281.08:20:48.97#ibcon#read 5, iclass 29, count 2 2006.281.08:20:48.97#ibcon#about to read 6, iclass 29, count 2 2006.281.08:20:48.97#ibcon#read 6, iclass 29, count 2 2006.281.08:20:48.97#ibcon#end of sib2, iclass 29, count 2 2006.281.08:20:48.97#ibcon#*after write, iclass 29, count 2 2006.281.08:20:48.97#ibcon#*before return 0, iclass 29, count 2 2006.281.08:20:48.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:48.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:48.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.08:20:48.97#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:48.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:49.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:49.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:49.10#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:20:49.10#ibcon#first serial, iclass 29, count 0 2006.281.08:20:49.10#ibcon#enter sib2, iclass 29, count 0 2006.281.08:20:49.10#ibcon#flushed, iclass 29, count 0 2006.281.08:20:49.10#ibcon#about to write, iclass 29, count 0 2006.281.08:20:49.10#ibcon#wrote, iclass 29, count 0 2006.281.08:20:49.10#ibcon#about to read 3, iclass 29, count 0 2006.281.08:20:49.11#ibcon#read 3, iclass 29, count 0 2006.281.08:20:49.11#ibcon#about to read 4, iclass 29, count 0 2006.281.08:20:49.11#ibcon#read 4, iclass 29, count 0 2006.281.08:20:49.11#ibcon#about to read 5, iclass 29, count 0 2006.281.08:20:49.11#ibcon#read 5, iclass 29, count 0 2006.281.08:20:49.11#ibcon#about to read 6, iclass 29, count 0 2006.281.08:20:49.11#ibcon#read 6, iclass 29, count 0 2006.281.08:20:49.11#ibcon#end of sib2, iclass 29, count 0 2006.281.08:20:49.11#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:20:49.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:20:49.11#ibcon#[25=USB\r\n] 2006.281.08:20:49.11#ibcon#*before write, iclass 29, count 0 2006.281.08:20:49.11#ibcon#enter sib2, iclass 29, count 0 2006.281.08:20:49.11#ibcon#flushed, iclass 29, count 0 2006.281.08:20:49.11#ibcon#about to write, iclass 29, count 0 2006.281.08:20:49.11#ibcon#wrote, iclass 29, count 0 2006.281.08:20:49.11#ibcon#about to read 3, iclass 29, count 0 2006.281.08:20:49.14#ibcon#read 3, iclass 29, count 0 2006.281.08:20:49.14#ibcon#about to read 4, iclass 29, count 0 2006.281.08:20:49.14#ibcon#read 4, iclass 29, count 0 2006.281.08:20:49.14#ibcon#about to read 5, iclass 29, count 0 2006.281.08:20:49.14#ibcon#read 5, iclass 29, count 0 2006.281.08:20:49.14#ibcon#about to read 6, iclass 29, count 0 2006.281.08:20:49.14#ibcon#read 6, iclass 29, count 0 2006.281.08:20:49.14#ibcon#end of sib2, iclass 29, count 0 2006.281.08:20:49.14#ibcon#*after write, iclass 29, count 0 2006.281.08:20:49.14#ibcon#*before return 0, iclass 29, count 0 2006.281.08:20:49.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:49.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:49.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:20:49.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:20:49.14$vc4f8/valo=2,572.99 2006.281.08:20:49.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:20:49.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:20:49.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:49.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:49.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:49.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:49.14#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:20:49.14#ibcon#first serial, iclass 31, count 0 2006.281.08:20:49.14#ibcon#enter sib2, iclass 31, count 0 2006.281.08:20:49.14#ibcon#flushed, iclass 31, count 0 2006.281.08:20:49.14#ibcon#about to write, iclass 31, count 0 2006.281.08:20:49.14#ibcon#wrote, iclass 31, count 0 2006.281.08:20:49.14#ibcon#about to read 3, iclass 31, count 0 2006.281.08:20:49.16#ibcon#read 3, iclass 31, count 0 2006.281.08:20:49.16#ibcon#about to read 4, iclass 31, count 0 2006.281.08:20:49.16#ibcon#read 4, iclass 31, count 0 2006.281.08:20:49.16#ibcon#about to read 5, iclass 31, count 0 2006.281.08:20:49.16#ibcon#read 5, iclass 31, count 0 2006.281.08:20:49.16#ibcon#about to read 6, iclass 31, count 0 2006.281.08:20:49.16#ibcon#read 6, iclass 31, count 0 2006.281.08:20:49.16#ibcon#end of sib2, iclass 31, count 0 2006.281.08:20:49.16#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:20:49.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:20:49.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:20:49.16#ibcon#*before write, iclass 31, count 0 2006.281.08:20:49.16#ibcon#enter sib2, iclass 31, count 0 2006.281.08:20:49.16#ibcon#flushed, iclass 31, count 0 2006.281.08:20:49.16#ibcon#about to write, iclass 31, count 0 2006.281.08:20:49.16#ibcon#wrote, iclass 31, count 0 2006.281.08:20:49.16#ibcon#about to read 3, iclass 31, count 0 2006.281.08:20:49.20#ibcon#read 3, iclass 31, count 0 2006.281.08:20:49.20#ibcon#about to read 4, iclass 31, count 0 2006.281.08:20:49.20#ibcon#read 4, iclass 31, count 0 2006.281.08:20:49.20#ibcon#about to read 5, iclass 31, count 0 2006.281.08:20:49.20#ibcon#read 5, iclass 31, count 0 2006.281.08:20:49.20#ibcon#about to read 6, iclass 31, count 0 2006.281.08:20:49.20#ibcon#read 6, iclass 31, count 0 2006.281.08:20:49.20#ibcon#end of sib2, iclass 31, count 0 2006.281.08:20:49.20#ibcon#*after write, iclass 31, count 0 2006.281.08:20:49.20#ibcon#*before return 0, iclass 31, count 0 2006.281.08:20:49.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:49.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:49.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:20:49.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:20:49.20$vc4f8/va=2,6 2006.281.08:20:49.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.08:20:49.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.08:20:49.20#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:49.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:49.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:49.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:49.27#ibcon#enter wrdev, iclass 33, count 2 2006.281.08:20:49.27#ibcon#first serial, iclass 33, count 2 2006.281.08:20:49.27#ibcon#enter sib2, iclass 33, count 2 2006.281.08:20:49.27#ibcon#flushed, iclass 33, count 2 2006.281.08:20:49.27#ibcon#about to write, iclass 33, count 2 2006.281.08:20:49.27#ibcon#wrote, iclass 33, count 2 2006.281.08:20:49.27#ibcon#about to read 3, iclass 33, count 2 2006.281.08:20:49.28#ibcon#read 3, iclass 33, count 2 2006.281.08:20:49.28#ibcon#about to read 4, iclass 33, count 2 2006.281.08:20:49.28#ibcon#read 4, iclass 33, count 2 2006.281.08:20:49.28#ibcon#about to read 5, iclass 33, count 2 2006.281.08:20:49.28#ibcon#read 5, iclass 33, count 2 2006.281.08:20:49.28#ibcon#about to read 6, iclass 33, count 2 2006.281.08:20:49.28#ibcon#read 6, iclass 33, count 2 2006.281.08:20:49.28#ibcon#end of sib2, iclass 33, count 2 2006.281.08:20:49.28#ibcon#*mode == 0, iclass 33, count 2 2006.281.08:20:49.28#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.08:20:49.28#ibcon#[25=AT02-06\r\n] 2006.281.08:20:49.28#ibcon#*before write, iclass 33, count 2 2006.281.08:20:49.28#ibcon#enter sib2, iclass 33, count 2 2006.281.08:20:49.28#ibcon#flushed, iclass 33, count 2 2006.281.08:20:49.28#ibcon#about to write, iclass 33, count 2 2006.281.08:20:49.28#ibcon#wrote, iclass 33, count 2 2006.281.08:20:49.28#ibcon#about to read 3, iclass 33, count 2 2006.281.08:20:49.31#ibcon#read 3, iclass 33, count 2 2006.281.08:20:49.31#ibcon#about to read 4, iclass 33, count 2 2006.281.08:20:49.31#ibcon#read 4, iclass 33, count 2 2006.281.08:20:49.31#ibcon#about to read 5, iclass 33, count 2 2006.281.08:20:49.31#ibcon#read 5, iclass 33, count 2 2006.281.08:20:49.31#ibcon#about to read 6, iclass 33, count 2 2006.281.08:20:49.31#ibcon#read 6, iclass 33, count 2 2006.281.08:20:49.31#ibcon#end of sib2, iclass 33, count 2 2006.281.08:20:49.31#ibcon#*after write, iclass 33, count 2 2006.281.08:20:49.31#ibcon#*before return 0, iclass 33, count 2 2006.281.08:20:49.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:49.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:49.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.08:20:49.31#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:49.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:49.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:49.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:49.43#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:20:49.43#ibcon#first serial, iclass 33, count 0 2006.281.08:20:49.43#ibcon#enter sib2, iclass 33, count 0 2006.281.08:20:49.43#ibcon#flushed, iclass 33, count 0 2006.281.08:20:49.43#ibcon#about to write, iclass 33, count 0 2006.281.08:20:49.43#ibcon#wrote, iclass 33, count 0 2006.281.08:20:49.43#ibcon#about to read 3, iclass 33, count 0 2006.281.08:20:49.45#ibcon#read 3, iclass 33, count 0 2006.281.08:20:49.45#ibcon#about to read 4, iclass 33, count 0 2006.281.08:20:49.45#ibcon#read 4, iclass 33, count 0 2006.281.08:20:49.45#ibcon#about to read 5, iclass 33, count 0 2006.281.08:20:49.45#ibcon#read 5, iclass 33, count 0 2006.281.08:20:49.45#ibcon#about to read 6, iclass 33, count 0 2006.281.08:20:49.45#ibcon#read 6, iclass 33, count 0 2006.281.08:20:49.45#ibcon#end of sib2, iclass 33, count 0 2006.281.08:20:49.45#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:20:49.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:20:49.45#ibcon#[25=USB\r\n] 2006.281.08:20:49.45#ibcon#*before write, iclass 33, count 0 2006.281.08:20:49.45#ibcon#enter sib2, iclass 33, count 0 2006.281.08:20:49.45#ibcon#flushed, iclass 33, count 0 2006.281.08:20:49.45#ibcon#about to write, iclass 33, count 0 2006.281.08:20:49.45#ibcon#wrote, iclass 33, count 0 2006.281.08:20:49.45#ibcon#about to read 3, iclass 33, count 0 2006.281.08:20:49.48#ibcon#read 3, iclass 33, count 0 2006.281.08:20:49.48#ibcon#about to read 4, iclass 33, count 0 2006.281.08:20:49.48#ibcon#read 4, iclass 33, count 0 2006.281.08:20:49.48#ibcon#about to read 5, iclass 33, count 0 2006.281.08:20:49.48#ibcon#read 5, iclass 33, count 0 2006.281.08:20:49.48#ibcon#about to read 6, iclass 33, count 0 2006.281.08:20:49.48#ibcon#read 6, iclass 33, count 0 2006.281.08:20:49.48#ibcon#end of sib2, iclass 33, count 0 2006.281.08:20:49.48#ibcon#*after write, iclass 33, count 0 2006.281.08:20:49.48#ibcon#*before return 0, iclass 33, count 0 2006.281.08:20:49.48#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:49.48#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:49.48#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:20:49.48#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:20:49.48$vc4f8/valo=3,672.99 2006.281.08:20:49.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.08:20:49.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.08:20:49.48#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:49.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:49.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:49.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:49.48#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:20:49.48#ibcon#first serial, iclass 35, count 0 2006.281.08:20:49.48#ibcon#enter sib2, iclass 35, count 0 2006.281.08:20:49.48#ibcon#flushed, iclass 35, count 0 2006.281.08:20:49.49#ibcon#about to write, iclass 35, count 0 2006.281.08:20:49.49#ibcon#wrote, iclass 35, count 0 2006.281.08:20:49.49#ibcon#about to read 3, iclass 35, count 0 2006.281.08:20:49.50#ibcon#read 3, iclass 35, count 0 2006.281.08:20:49.50#ibcon#about to read 4, iclass 35, count 0 2006.281.08:20:49.50#ibcon#read 4, iclass 35, count 0 2006.281.08:20:49.50#ibcon#about to read 5, iclass 35, count 0 2006.281.08:20:49.50#ibcon#read 5, iclass 35, count 0 2006.281.08:20:49.50#ibcon#about to read 6, iclass 35, count 0 2006.281.08:20:49.50#ibcon#read 6, iclass 35, count 0 2006.281.08:20:49.50#ibcon#end of sib2, iclass 35, count 0 2006.281.08:20:49.50#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:20:49.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:20:49.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:20:49.52#ibcon#*before write, iclass 35, count 0 2006.281.08:20:49.52#ibcon#enter sib2, iclass 35, count 0 2006.281.08:20:49.52#ibcon#flushed, iclass 35, count 0 2006.281.08:20:49.52#ibcon#about to write, iclass 35, count 0 2006.281.08:20:49.52#ibcon#wrote, iclass 35, count 0 2006.281.08:20:49.52#ibcon#about to read 3, iclass 35, count 0 2006.281.08:20:49.56#ibcon#read 3, iclass 35, count 0 2006.281.08:20:49.56#ibcon#about to read 4, iclass 35, count 0 2006.281.08:20:49.56#ibcon#read 4, iclass 35, count 0 2006.281.08:20:49.56#ibcon#about to read 5, iclass 35, count 0 2006.281.08:20:49.56#ibcon#read 5, iclass 35, count 0 2006.281.08:20:49.56#ibcon#about to read 6, iclass 35, count 0 2006.281.08:20:49.56#ibcon#read 6, iclass 35, count 0 2006.281.08:20:49.56#ibcon#end of sib2, iclass 35, count 0 2006.281.08:20:49.56#ibcon#*after write, iclass 35, count 0 2006.281.08:20:49.56#ibcon#*before return 0, iclass 35, count 0 2006.281.08:20:49.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:49.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:49.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:20:49.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:20:49.56$vc4f8/va=3,6 2006.281.08:20:49.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.08:20:49.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.08:20:49.56#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:49.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:49.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:49.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:49.60#ibcon#enter wrdev, iclass 37, count 2 2006.281.08:20:49.60#ibcon#first serial, iclass 37, count 2 2006.281.08:20:49.60#ibcon#enter sib2, iclass 37, count 2 2006.281.08:20:49.60#ibcon#flushed, iclass 37, count 2 2006.281.08:20:49.60#ibcon#about to write, iclass 37, count 2 2006.281.08:20:49.60#ibcon#wrote, iclass 37, count 2 2006.281.08:20:49.60#ibcon#about to read 3, iclass 37, count 2 2006.281.08:20:49.62#ibcon#read 3, iclass 37, count 2 2006.281.08:20:49.62#ibcon#about to read 4, iclass 37, count 2 2006.281.08:20:49.62#ibcon#read 4, iclass 37, count 2 2006.281.08:20:49.62#ibcon#about to read 5, iclass 37, count 2 2006.281.08:20:49.62#ibcon#read 5, iclass 37, count 2 2006.281.08:20:49.62#ibcon#about to read 6, iclass 37, count 2 2006.281.08:20:49.62#ibcon#read 6, iclass 37, count 2 2006.281.08:20:49.62#ibcon#end of sib2, iclass 37, count 2 2006.281.08:20:49.62#ibcon#*mode == 0, iclass 37, count 2 2006.281.08:20:49.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.08:20:49.62#ibcon#[25=AT03-06\r\n] 2006.281.08:20:49.62#ibcon#*before write, iclass 37, count 2 2006.281.08:20:49.62#ibcon#enter sib2, iclass 37, count 2 2006.281.08:20:49.62#ibcon#flushed, iclass 37, count 2 2006.281.08:20:49.62#ibcon#about to write, iclass 37, count 2 2006.281.08:20:49.62#ibcon#wrote, iclass 37, count 2 2006.281.08:20:49.62#ibcon#about to read 3, iclass 37, count 2 2006.281.08:20:49.65#ibcon#read 3, iclass 37, count 2 2006.281.08:20:49.65#ibcon#about to read 4, iclass 37, count 2 2006.281.08:20:49.65#ibcon#read 4, iclass 37, count 2 2006.281.08:20:49.65#ibcon#about to read 5, iclass 37, count 2 2006.281.08:20:49.65#ibcon#read 5, iclass 37, count 2 2006.281.08:20:49.65#ibcon#about to read 6, iclass 37, count 2 2006.281.08:20:49.65#ibcon#read 6, iclass 37, count 2 2006.281.08:20:49.65#ibcon#end of sib2, iclass 37, count 2 2006.281.08:20:49.65#ibcon#*after write, iclass 37, count 2 2006.281.08:20:49.65#ibcon#*before return 0, iclass 37, count 2 2006.281.08:20:49.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:49.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:49.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.08:20:49.65#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:49.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:49.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:49.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:49.77#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:20:49.77#ibcon#first serial, iclass 37, count 0 2006.281.08:20:49.77#ibcon#enter sib2, iclass 37, count 0 2006.281.08:20:49.77#ibcon#flushed, iclass 37, count 0 2006.281.08:20:49.77#ibcon#about to write, iclass 37, count 0 2006.281.08:20:49.77#ibcon#wrote, iclass 37, count 0 2006.281.08:20:49.77#ibcon#about to read 3, iclass 37, count 0 2006.281.08:20:49.79#ibcon#read 3, iclass 37, count 0 2006.281.08:20:49.79#ibcon#about to read 4, iclass 37, count 0 2006.281.08:20:49.79#ibcon#read 4, iclass 37, count 0 2006.281.08:20:49.79#ibcon#about to read 5, iclass 37, count 0 2006.281.08:20:49.79#ibcon#read 5, iclass 37, count 0 2006.281.08:20:49.79#ibcon#about to read 6, iclass 37, count 0 2006.281.08:20:49.79#ibcon#read 6, iclass 37, count 0 2006.281.08:20:49.79#ibcon#end of sib2, iclass 37, count 0 2006.281.08:20:49.79#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:20:49.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:20:49.79#ibcon#[25=USB\r\n] 2006.281.08:20:49.79#ibcon#*before write, iclass 37, count 0 2006.281.08:20:49.79#ibcon#enter sib2, iclass 37, count 0 2006.281.08:20:49.79#ibcon#flushed, iclass 37, count 0 2006.281.08:20:49.79#ibcon#about to write, iclass 37, count 0 2006.281.08:20:49.79#ibcon#wrote, iclass 37, count 0 2006.281.08:20:49.79#ibcon#about to read 3, iclass 37, count 0 2006.281.08:20:49.82#ibcon#read 3, iclass 37, count 0 2006.281.08:20:49.82#ibcon#about to read 4, iclass 37, count 0 2006.281.08:20:49.82#ibcon#read 4, iclass 37, count 0 2006.281.08:20:49.82#ibcon#about to read 5, iclass 37, count 0 2006.281.08:20:49.82#ibcon#read 5, iclass 37, count 0 2006.281.08:20:49.82#ibcon#about to read 6, iclass 37, count 0 2006.281.08:20:49.82#ibcon#read 6, iclass 37, count 0 2006.281.08:20:49.82#ibcon#end of sib2, iclass 37, count 0 2006.281.08:20:49.82#ibcon#*after write, iclass 37, count 0 2006.281.08:20:49.82#ibcon#*before return 0, iclass 37, count 0 2006.281.08:20:49.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:49.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:49.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:20:49.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:20:49.82$vc4f8/valo=4,832.99 2006.281.08:20:49.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:20:49.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:20:49.82#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:49.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:49.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:49.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:49.82#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:20:49.82#ibcon#first serial, iclass 39, count 0 2006.281.08:20:49.82#ibcon#enter sib2, iclass 39, count 0 2006.281.08:20:49.82#ibcon#flushed, iclass 39, count 0 2006.281.08:20:49.82#ibcon#about to write, iclass 39, count 0 2006.281.08:20:49.82#ibcon#wrote, iclass 39, count 0 2006.281.08:20:49.82#ibcon#about to read 3, iclass 39, count 0 2006.281.08:20:49.84#ibcon#read 3, iclass 39, count 0 2006.281.08:20:49.84#ibcon#about to read 4, iclass 39, count 0 2006.281.08:20:49.84#ibcon#read 4, iclass 39, count 0 2006.281.08:20:49.84#ibcon#about to read 5, iclass 39, count 0 2006.281.08:20:49.84#ibcon#read 5, iclass 39, count 0 2006.281.08:20:49.84#ibcon#about to read 6, iclass 39, count 0 2006.281.08:20:49.84#ibcon#read 6, iclass 39, count 0 2006.281.08:20:49.84#ibcon#end of sib2, iclass 39, count 0 2006.281.08:20:49.84#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:20:49.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:20:49.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:20:49.84#ibcon#*before write, iclass 39, count 0 2006.281.08:20:49.84#ibcon#enter sib2, iclass 39, count 0 2006.281.08:20:49.84#ibcon#flushed, iclass 39, count 0 2006.281.08:20:49.84#ibcon#about to write, iclass 39, count 0 2006.281.08:20:49.84#ibcon#wrote, iclass 39, count 0 2006.281.08:20:49.84#ibcon#about to read 3, iclass 39, count 0 2006.281.08:20:49.88#ibcon#read 3, iclass 39, count 0 2006.281.08:20:49.89#ibcon#about to read 4, iclass 39, count 0 2006.281.08:20:49.89#ibcon#read 4, iclass 39, count 0 2006.281.08:20:49.89#ibcon#about to read 5, iclass 39, count 0 2006.281.08:20:49.89#ibcon#read 5, iclass 39, count 0 2006.281.08:20:49.89#ibcon#about to read 6, iclass 39, count 0 2006.281.08:20:49.89#ibcon#read 6, iclass 39, count 0 2006.281.08:20:49.89#ibcon#end of sib2, iclass 39, count 0 2006.281.08:20:49.89#ibcon#*after write, iclass 39, count 0 2006.281.08:20:49.89#ibcon#*before return 0, iclass 39, count 0 2006.281.08:20:49.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:49.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:49.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:20:49.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:20:49.89$vc4f8/va=4,6 2006.281.08:20:49.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.08:20:49.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.08:20:49.89#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:49.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:49.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:49.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:49.93#ibcon#enter wrdev, iclass 3, count 2 2006.281.08:20:49.93#ibcon#first serial, iclass 3, count 2 2006.281.08:20:49.93#ibcon#enter sib2, iclass 3, count 2 2006.281.08:20:49.93#ibcon#flushed, iclass 3, count 2 2006.281.08:20:49.93#ibcon#about to write, iclass 3, count 2 2006.281.08:20:49.93#ibcon#wrote, iclass 3, count 2 2006.281.08:20:49.93#ibcon#about to read 3, iclass 3, count 2 2006.281.08:20:49.95#ibcon#read 3, iclass 3, count 2 2006.281.08:20:49.95#ibcon#about to read 4, iclass 3, count 2 2006.281.08:20:49.95#ibcon#read 4, iclass 3, count 2 2006.281.08:20:49.95#ibcon#about to read 5, iclass 3, count 2 2006.281.08:20:49.95#ibcon#read 5, iclass 3, count 2 2006.281.08:20:49.95#ibcon#about to read 6, iclass 3, count 2 2006.281.08:20:49.95#ibcon#read 6, iclass 3, count 2 2006.281.08:20:49.95#ibcon#end of sib2, iclass 3, count 2 2006.281.08:20:49.95#ibcon#*mode == 0, iclass 3, count 2 2006.281.08:20:49.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.08:20:49.95#ibcon#[25=AT04-06\r\n] 2006.281.08:20:49.95#ibcon#*before write, iclass 3, count 2 2006.281.08:20:49.95#ibcon#enter sib2, iclass 3, count 2 2006.281.08:20:49.95#ibcon#flushed, iclass 3, count 2 2006.281.08:20:49.95#ibcon#about to write, iclass 3, count 2 2006.281.08:20:49.95#ibcon#wrote, iclass 3, count 2 2006.281.08:20:49.95#ibcon#about to read 3, iclass 3, count 2 2006.281.08:20:49.98#ibcon#read 3, iclass 3, count 2 2006.281.08:20:49.98#ibcon#about to read 4, iclass 3, count 2 2006.281.08:20:49.98#ibcon#read 4, iclass 3, count 2 2006.281.08:20:49.98#ibcon#about to read 5, iclass 3, count 2 2006.281.08:20:49.98#ibcon#read 5, iclass 3, count 2 2006.281.08:20:49.98#ibcon#about to read 6, iclass 3, count 2 2006.281.08:20:49.98#ibcon#read 6, iclass 3, count 2 2006.281.08:20:49.98#ibcon#end of sib2, iclass 3, count 2 2006.281.08:20:49.98#ibcon#*after write, iclass 3, count 2 2006.281.08:20:49.98#ibcon#*before return 0, iclass 3, count 2 2006.281.08:20:49.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:49.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:49.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.08:20:49.98#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:49.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:50.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:50.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:50.10#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:20:50.10#ibcon#first serial, iclass 3, count 0 2006.281.08:20:50.10#ibcon#enter sib2, iclass 3, count 0 2006.281.08:20:50.10#ibcon#flushed, iclass 3, count 0 2006.281.08:20:50.10#ibcon#about to write, iclass 3, count 0 2006.281.08:20:50.10#ibcon#wrote, iclass 3, count 0 2006.281.08:20:50.10#ibcon#about to read 3, iclass 3, count 0 2006.281.08:20:50.12#ibcon#read 3, iclass 3, count 0 2006.281.08:20:50.12#ibcon#about to read 4, iclass 3, count 0 2006.281.08:20:50.12#ibcon#read 4, iclass 3, count 0 2006.281.08:20:50.12#ibcon#about to read 5, iclass 3, count 0 2006.281.08:20:50.12#ibcon#read 5, iclass 3, count 0 2006.281.08:20:50.12#ibcon#about to read 6, iclass 3, count 0 2006.281.08:20:50.12#ibcon#read 6, iclass 3, count 0 2006.281.08:20:50.12#ibcon#end of sib2, iclass 3, count 0 2006.281.08:20:50.12#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:20:50.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:20:50.12#ibcon#[25=USB\r\n] 2006.281.08:20:50.12#ibcon#*before write, iclass 3, count 0 2006.281.08:20:50.12#ibcon#enter sib2, iclass 3, count 0 2006.281.08:20:50.12#ibcon#flushed, iclass 3, count 0 2006.281.08:20:50.12#ibcon#about to write, iclass 3, count 0 2006.281.08:20:50.12#ibcon#wrote, iclass 3, count 0 2006.281.08:20:50.12#ibcon#about to read 3, iclass 3, count 0 2006.281.08:20:50.15#ibcon#read 3, iclass 3, count 0 2006.281.08:20:50.15#ibcon#about to read 4, iclass 3, count 0 2006.281.08:20:50.15#ibcon#read 4, iclass 3, count 0 2006.281.08:20:50.15#ibcon#about to read 5, iclass 3, count 0 2006.281.08:20:50.15#ibcon#read 5, iclass 3, count 0 2006.281.08:20:50.15#ibcon#about to read 6, iclass 3, count 0 2006.281.08:20:50.15#ibcon#read 6, iclass 3, count 0 2006.281.08:20:50.15#ibcon#end of sib2, iclass 3, count 0 2006.281.08:20:50.15#ibcon#*after write, iclass 3, count 0 2006.281.08:20:50.15#ibcon#*before return 0, iclass 3, count 0 2006.281.08:20:50.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:50.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:50.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:20:50.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:20:50.15$vc4f8/valo=5,652.99 2006.281.08:20:50.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.08:20:50.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.08:20:50.15#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:50.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:50.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:50.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:50.15#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:20:50.15#ibcon#first serial, iclass 5, count 0 2006.281.08:20:50.15#ibcon#enter sib2, iclass 5, count 0 2006.281.08:20:50.15#ibcon#flushed, iclass 5, count 0 2006.281.08:20:50.15#ibcon#about to write, iclass 5, count 0 2006.281.08:20:50.15#ibcon#wrote, iclass 5, count 0 2006.281.08:20:50.15#ibcon#about to read 3, iclass 5, count 0 2006.281.08:20:50.17#ibcon#read 3, iclass 5, count 0 2006.281.08:20:50.17#ibcon#about to read 4, iclass 5, count 0 2006.281.08:20:50.17#ibcon#read 4, iclass 5, count 0 2006.281.08:20:50.17#ibcon#about to read 5, iclass 5, count 0 2006.281.08:20:50.17#ibcon#read 5, iclass 5, count 0 2006.281.08:20:50.17#ibcon#about to read 6, iclass 5, count 0 2006.281.08:20:50.17#ibcon#read 6, iclass 5, count 0 2006.281.08:20:50.17#ibcon#end of sib2, iclass 5, count 0 2006.281.08:20:50.17#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:20:50.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:20:50.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:20:50.17#ibcon#*before write, iclass 5, count 0 2006.281.08:20:50.17#ibcon#enter sib2, iclass 5, count 0 2006.281.08:20:50.17#ibcon#flushed, iclass 5, count 0 2006.281.08:20:50.17#ibcon#about to write, iclass 5, count 0 2006.281.08:20:50.17#ibcon#wrote, iclass 5, count 0 2006.281.08:20:50.17#ibcon#about to read 3, iclass 5, count 0 2006.281.08:20:50.22#ibcon#read 3, iclass 5, count 0 2006.281.08:20:50.22#ibcon#about to read 4, iclass 5, count 0 2006.281.08:20:50.22#ibcon#read 4, iclass 5, count 0 2006.281.08:20:50.22#ibcon#about to read 5, iclass 5, count 0 2006.281.08:20:50.22#ibcon#read 5, iclass 5, count 0 2006.281.08:20:50.22#ibcon#about to read 6, iclass 5, count 0 2006.281.08:20:50.22#ibcon#read 6, iclass 5, count 0 2006.281.08:20:50.22#ibcon#end of sib2, iclass 5, count 0 2006.281.08:20:50.22#ibcon#*after write, iclass 5, count 0 2006.281.08:20:50.22#ibcon#*before return 0, iclass 5, count 0 2006.281.08:20:50.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:50.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:50.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:20:50.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:20:50.22$vc4f8/va=5,7 2006.281.08:20:50.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.281.08:20:50.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.281.08:20:50.23#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:50.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:20:50.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:20:50.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:20:50.26#ibcon#enter wrdev, iclass 7, count 2 2006.281.08:20:50.26#ibcon#first serial, iclass 7, count 2 2006.281.08:20:50.26#ibcon#enter sib2, iclass 7, count 2 2006.281.08:20:50.26#ibcon#flushed, iclass 7, count 2 2006.281.08:20:50.26#ibcon#about to write, iclass 7, count 2 2006.281.08:20:50.26#ibcon#wrote, iclass 7, count 2 2006.281.08:20:50.26#ibcon#about to read 3, iclass 7, count 2 2006.281.08:20:50.28#ibcon#read 3, iclass 7, count 2 2006.281.08:20:50.28#ibcon#about to read 4, iclass 7, count 2 2006.281.08:20:50.28#ibcon#read 4, iclass 7, count 2 2006.281.08:20:50.28#ibcon#about to read 5, iclass 7, count 2 2006.281.08:20:50.28#ibcon#read 5, iclass 7, count 2 2006.281.08:20:50.28#ibcon#about to read 6, iclass 7, count 2 2006.281.08:20:50.28#ibcon#read 6, iclass 7, count 2 2006.281.08:20:50.28#ibcon#end of sib2, iclass 7, count 2 2006.281.08:20:50.28#ibcon#*mode == 0, iclass 7, count 2 2006.281.08:20:50.28#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.281.08:20:50.28#ibcon#[25=AT05-07\r\n] 2006.281.08:20:50.28#ibcon#*before write, iclass 7, count 2 2006.281.08:20:50.28#ibcon#enter sib2, iclass 7, count 2 2006.281.08:20:50.28#ibcon#flushed, iclass 7, count 2 2006.281.08:20:50.28#ibcon#about to write, iclass 7, count 2 2006.281.08:20:50.28#ibcon#wrote, iclass 7, count 2 2006.281.08:20:50.28#ibcon#about to read 3, iclass 7, count 2 2006.281.08:20:50.32#ibcon#read 3, iclass 7, count 2 2006.281.08:20:50.32#ibcon#about to read 4, iclass 7, count 2 2006.281.08:20:50.32#ibcon#read 4, iclass 7, count 2 2006.281.08:20:50.32#ibcon#about to read 5, iclass 7, count 2 2006.281.08:20:50.32#ibcon#read 5, iclass 7, count 2 2006.281.08:20:50.32#ibcon#about to read 6, iclass 7, count 2 2006.281.08:20:50.32#ibcon#read 6, iclass 7, count 2 2006.281.08:20:50.32#ibcon#end of sib2, iclass 7, count 2 2006.281.08:20:50.32#ibcon#*after write, iclass 7, count 2 2006.281.08:20:50.32#ibcon#*before return 0, iclass 7, count 2 2006.281.08:20:50.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:20:50.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.281.08:20:50.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.281.08:20:50.32#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:50.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:20:50.43#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:20:50.43#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:20:50.43#ibcon#enter wrdev, iclass 7, count 0 2006.281.08:20:50.43#ibcon#first serial, iclass 7, count 0 2006.281.08:20:50.43#ibcon#enter sib2, iclass 7, count 0 2006.281.08:20:50.43#ibcon#flushed, iclass 7, count 0 2006.281.08:20:50.43#ibcon#about to write, iclass 7, count 0 2006.281.08:20:50.43#ibcon#wrote, iclass 7, count 0 2006.281.08:20:50.43#ibcon#about to read 3, iclass 7, count 0 2006.281.08:20:50.45#ibcon#read 3, iclass 7, count 0 2006.281.08:20:50.45#ibcon#about to read 4, iclass 7, count 0 2006.281.08:20:50.45#ibcon#read 4, iclass 7, count 0 2006.281.08:20:50.45#ibcon#about to read 5, iclass 7, count 0 2006.281.08:20:50.45#ibcon#read 5, iclass 7, count 0 2006.281.08:20:50.45#ibcon#about to read 6, iclass 7, count 0 2006.281.08:20:50.45#ibcon#read 6, iclass 7, count 0 2006.281.08:20:50.45#ibcon#end of sib2, iclass 7, count 0 2006.281.08:20:50.45#ibcon#*mode == 0, iclass 7, count 0 2006.281.08:20:50.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.281.08:20:50.45#ibcon#[25=USB\r\n] 2006.281.08:20:50.45#ibcon#*before write, iclass 7, count 0 2006.281.08:20:50.45#ibcon#enter sib2, iclass 7, count 0 2006.281.08:20:50.45#ibcon#flushed, iclass 7, count 0 2006.281.08:20:50.45#ibcon#about to write, iclass 7, count 0 2006.281.08:20:50.45#ibcon#wrote, iclass 7, count 0 2006.281.08:20:50.45#ibcon#about to read 3, iclass 7, count 0 2006.281.08:20:50.48#ibcon#read 3, iclass 7, count 0 2006.281.08:20:50.48#ibcon#about to read 4, iclass 7, count 0 2006.281.08:20:50.48#ibcon#read 4, iclass 7, count 0 2006.281.08:20:50.48#ibcon#about to read 5, iclass 7, count 0 2006.281.08:20:50.48#ibcon#read 5, iclass 7, count 0 2006.281.08:20:50.48#ibcon#about to read 6, iclass 7, count 0 2006.281.08:20:50.48#ibcon#read 6, iclass 7, count 0 2006.281.08:20:50.48#ibcon#end of sib2, iclass 7, count 0 2006.281.08:20:50.48#ibcon#*after write, iclass 7, count 0 2006.281.08:20:50.48#ibcon#*before return 0, iclass 7, count 0 2006.281.08:20:50.48#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:20:50.48#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.281.08:20:50.48#ibcon#about to clear, iclass 7 cls_cnt 0 2006.281.08:20:50.48#ibcon#cleared, iclass 7 cls_cnt 0 2006.281.08:20:50.48$vc4f8/valo=6,772.99 2006.281.08:20:50.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.281.08:20:50.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.281.08:20:50.48#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:50.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:20:50.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:20:50.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:20:50.48#ibcon#enter wrdev, iclass 11, count 0 2006.281.08:20:50.48#ibcon#first serial, iclass 11, count 0 2006.281.08:20:50.48#ibcon#enter sib2, iclass 11, count 0 2006.281.08:20:50.48#ibcon#flushed, iclass 11, count 0 2006.281.08:20:50.48#ibcon#about to write, iclass 11, count 0 2006.281.08:20:50.48#ibcon#wrote, iclass 11, count 0 2006.281.08:20:50.48#ibcon#about to read 3, iclass 11, count 0 2006.281.08:20:50.50#ibcon#read 3, iclass 11, count 0 2006.281.08:20:50.50#ibcon#about to read 4, iclass 11, count 0 2006.281.08:20:50.50#ibcon#read 4, iclass 11, count 0 2006.281.08:20:50.50#ibcon#about to read 5, iclass 11, count 0 2006.281.08:20:50.50#ibcon#read 5, iclass 11, count 0 2006.281.08:20:50.50#ibcon#about to read 6, iclass 11, count 0 2006.281.08:20:50.50#ibcon#read 6, iclass 11, count 0 2006.281.08:20:50.50#ibcon#end of sib2, iclass 11, count 0 2006.281.08:20:50.50#ibcon#*mode == 0, iclass 11, count 0 2006.281.08:20:50.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.281.08:20:50.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:20:50.52#ibcon#*before write, iclass 11, count 0 2006.281.08:20:50.52#ibcon#enter sib2, iclass 11, count 0 2006.281.08:20:50.52#ibcon#flushed, iclass 11, count 0 2006.281.08:20:50.52#ibcon#about to write, iclass 11, count 0 2006.281.08:20:50.52#ibcon#wrote, iclass 11, count 0 2006.281.08:20:50.52#ibcon#about to read 3, iclass 11, count 0 2006.281.08:20:50.56#ibcon#read 3, iclass 11, count 0 2006.281.08:20:50.56#ibcon#about to read 4, iclass 11, count 0 2006.281.08:20:50.56#ibcon#read 4, iclass 11, count 0 2006.281.08:20:50.56#ibcon#about to read 5, iclass 11, count 0 2006.281.08:20:50.56#ibcon#read 5, iclass 11, count 0 2006.281.08:20:50.56#ibcon#about to read 6, iclass 11, count 0 2006.281.08:20:50.56#ibcon#read 6, iclass 11, count 0 2006.281.08:20:50.56#ibcon#end of sib2, iclass 11, count 0 2006.281.08:20:50.56#ibcon#*after write, iclass 11, count 0 2006.281.08:20:50.56#ibcon#*before return 0, iclass 11, count 0 2006.281.08:20:50.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:20:50.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.281.08:20:50.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.281.08:20:50.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.281.08:20:50.56$vc4f8/va=6,6 2006.281.08:20:50.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.281.08:20:50.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.281.08:20:50.56#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:50.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:20:50.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:20:50.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:20:50.60#ibcon#enter wrdev, iclass 13, count 2 2006.281.08:20:50.60#ibcon#first serial, iclass 13, count 2 2006.281.08:20:50.60#ibcon#enter sib2, iclass 13, count 2 2006.281.08:20:50.60#ibcon#flushed, iclass 13, count 2 2006.281.08:20:50.60#ibcon#about to write, iclass 13, count 2 2006.281.08:20:50.60#ibcon#wrote, iclass 13, count 2 2006.281.08:20:50.60#ibcon#about to read 3, iclass 13, count 2 2006.281.08:20:50.62#ibcon#read 3, iclass 13, count 2 2006.281.08:20:50.62#ibcon#about to read 4, iclass 13, count 2 2006.281.08:20:50.62#ibcon#read 4, iclass 13, count 2 2006.281.08:20:50.62#ibcon#about to read 5, iclass 13, count 2 2006.281.08:20:50.62#ibcon#read 5, iclass 13, count 2 2006.281.08:20:50.62#ibcon#about to read 6, iclass 13, count 2 2006.281.08:20:50.62#ibcon#read 6, iclass 13, count 2 2006.281.08:20:50.62#ibcon#end of sib2, iclass 13, count 2 2006.281.08:20:50.62#ibcon#*mode == 0, iclass 13, count 2 2006.281.08:20:50.62#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.281.08:20:50.62#ibcon#[25=AT06-06\r\n] 2006.281.08:20:50.62#ibcon#*before write, iclass 13, count 2 2006.281.08:20:50.62#ibcon#enter sib2, iclass 13, count 2 2006.281.08:20:50.62#ibcon#flushed, iclass 13, count 2 2006.281.08:20:50.62#ibcon#about to write, iclass 13, count 2 2006.281.08:20:50.62#ibcon#wrote, iclass 13, count 2 2006.281.08:20:50.62#ibcon#about to read 3, iclass 13, count 2 2006.281.08:20:50.65#ibcon#read 3, iclass 13, count 2 2006.281.08:20:50.65#ibcon#about to read 4, iclass 13, count 2 2006.281.08:20:50.65#ibcon#read 4, iclass 13, count 2 2006.281.08:20:50.65#ibcon#about to read 5, iclass 13, count 2 2006.281.08:20:50.65#ibcon#read 5, iclass 13, count 2 2006.281.08:20:50.65#ibcon#about to read 6, iclass 13, count 2 2006.281.08:20:50.65#ibcon#read 6, iclass 13, count 2 2006.281.08:20:50.65#ibcon#end of sib2, iclass 13, count 2 2006.281.08:20:50.65#ibcon#*after write, iclass 13, count 2 2006.281.08:20:50.65#ibcon#*before return 0, iclass 13, count 2 2006.281.08:20:50.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:20:50.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.281.08:20:50.65#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.281.08:20:50.65#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:50.65#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:20:50.77#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:20:50.77#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:20:50.77#ibcon#enter wrdev, iclass 13, count 0 2006.281.08:20:50.77#ibcon#first serial, iclass 13, count 0 2006.281.08:20:50.77#ibcon#enter sib2, iclass 13, count 0 2006.281.08:20:50.77#ibcon#flushed, iclass 13, count 0 2006.281.08:20:50.77#ibcon#about to write, iclass 13, count 0 2006.281.08:20:50.77#ibcon#wrote, iclass 13, count 0 2006.281.08:20:50.77#ibcon#about to read 3, iclass 13, count 0 2006.281.08:20:50.79#ibcon#read 3, iclass 13, count 0 2006.281.08:20:50.79#ibcon#about to read 4, iclass 13, count 0 2006.281.08:20:50.79#ibcon#read 4, iclass 13, count 0 2006.281.08:20:50.79#ibcon#about to read 5, iclass 13, count 0 2006.281.08:20:50.79#ibcon#read 5, iclass 13, count 0 2006.281.08:20:50.79#ibcon#about to read 6, iclass 13, count 0 2006.281.08:20:50.79#ibcon#read 6, iclass 13, count 0 2006.281.08:20:50.79#ibcon#end of sib2, iclass 13, count 0 2006.281.08:20:50.79#ibcon#*mode == 0, iclass 13, count 0 2006.281.08:20:50.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.281.08:20:50.79#ibcon#[25=USB\r\n] 2006.281.08:20:50.79#ibcon#*before write, iclass 13, count 0 2006.281.08:20:50.79#ibcon#enter sib2, iclass 13, count 0 2006.281.08:20:50.79#ibcon#flushed, iclass 13, count 0 2006.281.08:20:50.79#ibcon#about to write, iclass 13, count 0 2006.281.08:20:50.79#ibcon#wrote, iclass 13, count 0 2006.281.08:20:50.79#ibcon#about to read 3, iclass 13, count 0 2006.281.08:20:50.82#ibcon#read 3, iclass 13, count 0 2006.281.08:20:50.82#ibcon#about to read 4, iclass 13, count 0 2006.281.08:20:50.82#ibcon#read 4, iclass 13, count 0 2006.281.08:20:50.82#ibcon#about to read 5, iclass 13, count 0 2006.281.08:20:50.82#ibcon#read 5, iclass 13, count 0 2006.281.08:20:50.82#ibcon#about to read 6, iclass 13, count 0 2006.281.08:20:50.82#ibcon#read 6, iclass 13, count 0 2006.281.08:20:50.82#ibcon#end of sib2, iclass 13, count 0 2006.281.08:20:50.82#ibcon#*after write, iclass 13, count 0 2006.281.08:20:50.82#ibcon#*before return 0, iclass 13, count 0 2006.281.08:20:50.82#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:20:50.82#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.281.08:20:50.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.281.08:20:50.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.281.08:20:50.82$vc4f8/valo=7,832.99 2006.281.08:20:50.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.08:20:50.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.08:20:50.82#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:50.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:50.82#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:50.82#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:50.82#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:20:50.82#ibcon#first serial, iclass 15, count 0 2006.281.08:20:50.82#ibcon#enter sib2, iclass 15, count 0 2006.281.08:20:50.82#ibcon#flushed, iclass 15, count 0 2006.281.08:20:50.82#ibcon#about to write, iclass 15, count 0 2006.281.08:20:50.82#ibcon#wrote, iclass 15, count 0 2006.281.08:20:50.82#ibcon#about to read 3, iclass 15, count 0 2006.281.08:20:50.84#ibcon#read 3, iclass 15, count 0 2006.281.08:20:50.84#ibcon#about to read 4, iclass 15, count 0 2006.281.08:20:50.84#ibcon#read 4, iclass 15, count 0 2006.281.08:20:50.84#ibcon#about to read 5, iclass 15, count 0 2006.281.08:20:50.84#ibcon#read 5, iclass 15, count 0 2006.281.08:20:50.84#ibcon#about to read 6, iclass 15, count 0 2006.281.08:20:50.84#ibcon#read 6, iclass 15, count 0 2006.281.08:20:50.84#ibcon#end of sib2, iclass 15, count 0 2006.281.08:20:50.84#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:20:50.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:20:50.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:20:50.84#ibcon#*before write, iclass 15, count 0 2006.281.08:20:50.84#ibcon#enter sib2, iclass 15, count 0 2006.281.08:20:50.84#ibcon#flushed, iclass 15, count 0 2006.281.08:20:50.84#ibcon#about to write, iclass 15, count 0 2006.281.08:20:50.84#ibcon#wrote, iclass 15, count 0 2006.281.08:20:50.84#ibcon#about to read 3, iclass 15, count 0 2006.281.08:20:50.88#ibcon#read 3, iclass 15, count 0 2006.281.08:20:50.88#ibcon#about to read 4, iclass 15, count 0 2006.281.08:20:50.89#ibcon#read 4, iclass 15, count 0 2006.281.08:20:50.89#ibcon#about to read 5, iclass 15, count 0 2006.281.08:20:50.89#ibcon#read 5, iclass 15, count 0 2006.281.08:20:50.89#ibcon#about to read 6, iclass 15, count 0 2006.281.08:20:50.89#ibcon#read 6, iclass 15, count 0 2006.281.08:20:50.89#ibcon#end of sib2, iclass 15, count 0 2006.281.08:20:50.89#ibcon#*after write, iclass 15, count 0 2006.281.08:20:50.89#ibcon#*before return 0, iclass 15, count 0 2006.281.08:20:50.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:50.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:50.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:20:50.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:20:50.89$vc4f8/va=7,6 2006.281.08:20:50.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.281.08:20:50.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.281.08:20:50.89#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:50.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:50.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:50.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:50.93#ibcon#enter wrdev, iclass 17, count 2 2006.281.08:20:50.93#ibcon#first serial, iclass 17, count 2 2006.281.08:20:50.93#ibcon#enter sib2, iclass 17, count 2 2006.281.08:20:50.93#ibcon#flushed, iclass 17, count 2 2006.281.08:20:50.93#ibcon#about to write, iclass 17, count 2 2006.281.08:20:50.93#ibcon#wrote, iclass 17, count 2 2006.281.08:20:50.93#ibcon#about to read 3, iclass 17, count 2 2006.281.08:20:50.95#ibcon#read 3, iclass 17, count 2 2006.281.08:20:50.95#ibcon#about to read 4, iclass 17, count 2 2006.281.08:20:50.95#ibcon#read 4, iclass 17, count 2 2006.281.08:20:50.95#ibcon#about to read 5, iclass 17, count 2 2006.281.08:20:50.95#ibcon#read 5, iclass 17, count 2 2006.281.08:20:50.95#ibcon#about to read 6, iclass 17, count 2 2006.281.08:20:50.95#ibcon#read 6, iclass 17, count 2 2006.281.08:20:50.95#ibcon#end of sib2, iclass 17, count 2 2006.281.08:20:50.95#ibcon#*mode == 0, iclass 17, count 2 2006.281.08:20:50.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.281.08:20:50.95#ibcon#[25=AT07-06\r\n] 2006.281.08:20:50.95#ibcon#*before write, iclass 17, count 2 2006.281.08:20:50.95#ibcon#enter sib2, iclass 17, count 2 2006.281.08:20:50.95#ibcon#flushed, iclass 17, count 2 2006.281.08:20:50.95#ibcon#about to write, iclass 17, count 2 2006.281.08:20:50.95#ibcon#wrote, iclass 17, count 2 2006.281.08:20:50.95#ibcon#about to read 3, iclass 17, count 2 2006.281.08:20:50.98#ibcon#read 3, iclass 17, count 2 2006.281.08:20:50.98#ibcon#about to read 4, iclass 17, count 2 2006.281.08:20:50.98#ibcon#read 4, iclass 17, count 2 2006.281.08:20:50.98#ibcon#about to read 5, iclass 17, count 2 2006.281.08:20:50.98#ibcon#read 5, iclass 17, count 2 2006.281.08:20:50.98#ibcon#about to read 6, iclass 17, count 2 2006.281.08:20:50.98#ibcon#read 6, iclass 17, count 2 2006.281.08:20:50.98#ibcon#end of sib2, iclass 17, count 2 2006.281.08:20:50.98#ibcon#*after write, iclass 17, count 2 2006.281.08:20:50.98#ibcon#*before return 0, iclass 17, count 2 2006.281.08:20:50.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:50.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:50.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.281.08:20:50.98#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:50.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:20:51.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:20:51.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:20:51.10#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:20:51.10#ibcon#first serial, iclass 17, count 0 2006.281.08:20:51.10#ibcon#enter sib2, iclass 17, count 0 2006.281.08:20:51.10#ibcon#flushed, iclass 17, count 0 2006.281.08:20:51.10#ibcon#about to write, iclass 17, count 0 2006.281.08:20:51.10#ibcon#wrote, iclass 17, count 0 2006.281.08:20:51.10#ibcon#about to read 3, iclass 17, count 0 2006.281.08:20:51.12#ibcon#read 3, iclass 17, count 0 2006.281.08:20:51.12#ibcon#about to read 4, iclass 17, count 0 2006.281.08:20:51.12#ibcon#read 4, iclass 17, count 0 2006.281.08:20:51.12#ibcon#about to read 5, iclass 17, count 0 2006.281.08:20:51.12#ibcon#read 5, iclass 17, count 0 2006.281.08:20:51.12#ibcon#about to read 6, iclass 17, count 0 2006.281.08:20:51.12#ibcon#read 6, iclass 17, count 0 2006.281.08:20:51.12#ibcon#end of sib2, iclass 17, count 0 2006.281.08:20:51.12#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:20:51.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:20:51.12#ibcon#[25=USB\r\n] 2006.281.08:20:51.12#ibcon#*before write, iclass 17, count 0 2006.281.08:20:51.12#ibcon#enter sib2, iclass 17, count 0 2006.281.08:20:51.12#ibcon#flushed, iclass 17, count 0 2006.281.08:20:51.12#ibcon#about to write, iclass 17, count 0 2006.281.08:20:51.12#ibcon#wrote, iclass 17, count 0 2006.281.08:20:51.12#ibcon#about to read 3, iclass 17, count 0 2006.281.08:20:51.15#ibcon#read 3, iclass 17, count 0 2006.281.08:20:51.15#ibcon#about to read 4, iclass 17, count 0 2006.281.08:20:51.15#ibcon#read 4, iclass 17, count 0 2006.281.08:20:51.15#ibcon#about to read 5, iclass 17, count 0 2006.281.08:20:51.15#ibcon#read 5, iclass 17, count 0 2006.281.08:20:51.15#ibcon#about to read 6, iclass 17, count 0 2006.281.08:20:51.15#ibcon#read 6, iclass 17, count 0 2006.281.08:20:51.15#ibcon#end of sib2, iclass 17, count 0 2006.281.08:20:51.15#ibcon#*after write, iclass 17, count 0 2006.281.08:20:51.15#ibcon#*before return 0, iclass 17, count 0 2006.281.08:20:51.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:20:51.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.281.08:20:51.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:20:51.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:20:51.15$vc4f8/valo=8,852.99 2006.281.08:20:51.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.281.08:20:51.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.281.08:20:51.15#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:51.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:20:51.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:20:51.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:20:51.15#ibcon#enter wrdev, iclass 19, count 0 2006.281.08:20:51.15#ibcon#first serial, iclass 19, count 0 2006.281.08:20:51.15#ibcon#enter sib2, iclass 19, count 0 2006.281.08:20:51.15#ibcon#flushed, iclass 19, count 0 2006.281.08:20:51.15#ibcon#about to write, iclass 19, count 0 2006.281.08:20:51.15#ibcon#wrote, iclass 19, count 0 2006.281.08:20:51.15#ibcon#about to read 3, iclass 19, count 0 2006.281.08:20:51.17#ibcon#read 3, iclass 19, count 0 2006.281.08:20:51.17#ibcon#about to read 4, iclass 19, count 0 2006.281.08:20:51.17#ibcon#read 4, iclass 19, count 0 2006.281.08:20:51.17#ibcon#about to read 5, iclass 19, count 0 2006.281.08:20:51.17#ibcon#read 5, iclass 19, count 0 2006.281.08:20:51.17#ibcon#about to read 6, iclass 19, count 0 2006.281.08:20:51.17#ibcon#read 6, iclass 19, count 0 2006.281.08:20:51.17#ibcon#end of sib2, iclass 19, count 0 2006.281.08:20:51.17#ibcon#*mode == 0, iclass 19, count 0 2006.281.08:20:51.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.281.08:20:51.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:20:51.17#ibcon#*before write, iclass 19, count 0 2006.281.08:20:51.17#ibcon#enter sib2, iclass 19, count 0 2006.281.08:20:51.17#ibcon#flushed, iclass 19, count 0 2006.281.08:20:51.17#ibcon#about to write, iclass 19, count 0 2006.281.08:20:51.17#ibcon#wrote, iclass 19, count 0 2006.281.08:20:51.17#ibcon#about to read 3, iclass 19, count 0 2006.281.08:20:51.22#ibcon#read 3, iclass 19, count 0 2006.281.08:20:51.22#ibcon#about to read 4, iclass 19, count 0 2006.281.08:20:51.22#ibcon#read 4, iclass 19, count 0 2006.281.08:20:51.22#ibcon#about to read 5, iclass 19, count 0 2006.281.08:20:51.22#ibcon#read 5, iclass 19, count 0 2006.281.08:20:51.22#ibcon#about to read 6, iclass 19, count 0 2006.281.08:20:51.22#ibcon#read 6, iclass 19, count 0 2006.281.08:20:51.22#ibcon#end of sib2, iclass 19, count 0 2006.281.08:20:51.22#ibcon#*after write, iclass 19, count 0 2006.281.08:20:51.22#ibcon#*before return 0, iclass 19, count 0 2006.281.08:20:51.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:20:51.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.281.08:20:51.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.281.08:20:51.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.281.08:20:51.22$vc4f8/va=8,6 2006.281.08:20:51.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.281.08:20:51.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.281.08:20:51.22#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:51.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:20:51.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:20:51.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:20:51.26#ibcon#enter wrdev, iclass 21, count 2 2006.281.08:20:51.26#ibcon#first serial, iclass 21, count 2 2006.281.08:20:51.26#ibcon#enter sib2, iclass 21, count 2 2006.281.08:20:51.26#ibcon#flushed, iclass 21, count 2 2006.281.08:20:51.26#ibcon#about to write, iclass 21, count 2 2006.281.08:20:51.26#ibcon#wrote, iclass 21, count 2 2006.281.08:20:51.26#ibcon#about to read 3, iclass 21, count 2 2006.281.08:20:51.29#ibcon#read 3, iclass 21, count 2 2006.281.08:20:51.29#ibcon#about to read 4, iclass 21, count 2 2006.281.08:20:51.29#ibcon#read 4, iclass 21, count 2 2006.281.08:20:51.29#ibcon#about to read 5, iclass 21, count 2 2006.281.08:20:51.29#ibcon#read 5, iclass 21, count 2 2006.281.08:20:51.29#ibcon#about to read 6, iclass 21, count 2 2006.281.08:20:51.29#ibcon#read 6, iclass 21, count 2 2006.281.08:20:51.29#ibcon#end of sib2, iclass 21, count 2 2006.281.08:20:51.29#ibcon#*mode == 0, iclass 21, count 2 2006.281.08:20:51.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.281.08:20:51.29#ibcon#[25=AT08-06\r\n] 2006.281.08:20:51.29#ibcon#*before write, iclass 21, count 2 2006.281.08:20:51.29#ibcon#enter sib2, iclass 21, count 2 2006.281.08:20:51.29#ibcon#flushed, iclass 21, count 2 2006.281.08:20:51.29#ibcon#about to write, iclass 21, count 2 2006.281.08:20:51.29#ibcon#wrote, iclass 21, count 2 2006.281.08:20:51.29#ibcon#about to read 3, iclass 21, count 2 2006.281.08:20:51.32#ibcon#read 3, iclass 21, count 2 2006.281.08:20:51.32#ibcon#about to read 4, iclass 21, count 2 2006.281.08:20:51.32#ibcon#read 4, iclass 21, count 2 2006.281.08:20:51.32#ibcon#about to read 5, iclass 21, count 2 2006.281.08:20:51.32#ibcon#read 5, iclass 21, count 2 2006.281.08:20:51.32#ibcon#about to read 6, iclass 21, count 2 2006.281.08:20:51.32#ibcon#read 6, iclass 21, count 2 2006.281.08:20:51.32#ibcon#end of sib2, iclass 21, count 2 2006.281.08:20:51.32#ibcon#*after write, iclass 21, count 2 2006.281.08:20:51.32#ibcon#*before return 0, iclass 21, count 2 2006.281.08:20:51.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:20:51.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.281.08:20:51.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.281.08:20:51.32#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:51.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:20:51.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:20:51.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:20:51.44#ibcon#enter wrdev, iclass 21, count 0 2006.281.08:20:51.44#ibcon#first serial, iclass 21, count 0 2006.281.08:20:51.44#ibcon#enter sib2, iclass 21, count 0 2006.281.08:20:51.44#ibcon#flushed, iclass 21, count 0 2006.281.08:20:51.44#ibcon#about to write, iclass 21, count 0 2006.281.08:20:51.44#ibcon#wrote, iclass 21, count 0 2006.281.08:20:51.44#ibcon#about to read 3, iclass 21, count 0 2006.281.08:20:51.46#ibcon#read 3, iclass 21, count 0 2006.281.08:20:51.46#ibcon#about to read 4, iclass 21, count 0 2006.281.08:20:51.46#ibcon#read 4, iclass 21, count 0 2006.281.08:20:51.46#ibcon#about to read 5, iclass 21, count 0 2006.281.08:20:51.46#ibcon#read 5, iclass 21, count 0 2006.281.08:20:51.46#ibcon#about to read 6, iclass 21, count 0 2006.281.08:20:51.46#ibcon#read 6, iclass 21, count 0 2006.281.08:20:51.46#ibcon#end of sib2, iclass 21, count 0 2006.281.08:20:51.46#ibcon#*mode == 0, iclass 21, count 0 2006.281.08:20:51.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.281.08:20:51.46#ibcon#[25=USB\r\n] 2006.281.08:20:51.46#ibcon#*before write, iclass 21, count 0 2006.281.08:20:51.46#ibcon#enter sib2, iclass 21, count 0 2006.281.08:20:51.46#ibcon#flushed, iclass 21, count 0 2006.281.08:20:51.46#ibcon#about to write, iclass 21, count 0 2006.281.08:20:51.46#ibcon#wrote, iclass 21, count 0 2006.281.08:20:51.46#ibcon#about to read 3, iclass 21, count 0 2006.281.08:20:51.49#ibcon#read 3, iclass 21, count 0 2006.281.08:20:51.49#ibcon#about to read 4, iclass 21, count 0 2006.281.08:20:51.49#ibcon#read 4, iclass 21, count 0 2006.281.08:20:51.49#ibcon#about to read 5, iclass 21, count 0 2006.281.08:20:51.49#ibcon#read 5, iclass 21, count 0 2006.281.08:20:51.49#ibcon#about to read 6, iclass 21, count 0 2006.281.08:20:51.49#ibcon#read 6, iclass 21, count 0 2006.281.08:20:51.49#ibcon#end of sib2, iclass 21, count 0 2006.281.08:20:51.49#ibcon#*after write, iclass 21, count 0 2006.281.08:20:51.49#ibcon#*before return 0, iclass 21, count 0 2006.281.08:20:51.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:20:51.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.281.08:20:51.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.281.08:20:51.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.281.08:20:51.49$vc4f8/vblo=1,632.99 2006.281.08:20:51.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.281.08:20:51.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.281.08:20:51.49#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:51.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:20:51.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:20:51.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:20:51.49#ibcon#enter wrdev, iclass 23, count 0 2006.281.08:20:51.49#ibcon#first serial, iclass 23, count 0 2006.281.08:20:51.49#ibcon#enter sib2, iclass 23, count 0 2006.281.08:20:51.49#ibcon#flushed, iclass 23, count 0 2006.281.08:20:51.49#ibcon#about to write, iclass 23, count 0 2006.281.08:20:51.49#ibcon#wrote, iclass 23, count 0 2006.281.08:20:51.49#ibcon#about to read 3, iclass 23, count 0 2006.281.08:20:51.51#ibcon#read 3, iclass 23, count 0 2006.281.08:20:51.51#ibcon#about to read 4, iclass 23, count 0 2006.281.08:20:51.51#ibcon#read 4, iclass 23, count 0 2006.281.08:20:51.51#ibcon#about to read 5, iclass 23, count 0 2006.281.08:20:51.51#ibcon#read 5, iclass 23, count 0 2006.281.08:20:51.51#ibcon#about to read 6, iclass 23, count 0 2006.281.08:20:51.51#ibcon#read 6, iclass 23, count 0 2006.281.08:20:51.51#ibcon#end of sib2, iclass 23, count 0 2006.281.08:20:51.51#ibcon#*mode == 0, iclass 23, count 0 2006.281.08:20:51.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.281.08:20:51.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:20:51.53#ibcon#*before write, iclass 23, count 0 2006.281.08:20:51.53#ibcon#enter sib2, iclass 23, count 0 2006.281.08:20:51.53#ibcon#flushed, iclass 23, count 0 2006.281.08:20:51.53#ibcon#about to write, iclass 23, count 0 2006.281.08:20:51.53#ibcon#wrote, iclass 23, count 0 2006.281.08:20:51.53#ibcon#about to read 3, iclass 23, count 0 2006.281.08:20:51.57#ibcon#read 3, iclass 23, count 0 2006.281.08:20:51.57#ibcon#about to read 4, iclass 23, count 0 2006.281.08:20:51.57#ibcon#read 4, iclass 23, count 0 2006.281.08:20:51.57#ibcon#about to read 5, iclass 23, count 0 2006.281.08:20:51.57#ibcon#read 5, iclass 23, count 0 2006.281.08:20:51.57#ibcon#about to read 6, iclass 23, count 0 2006.281.08:20:51.57#ibcon#read 6, iclass 23, count 0 2006.281.08:20:51.57#ibcon#end of sib2, iclass 23, count 0 2006.281.08:20:51.57#ibcon#*after write, iclass 23, count 0 2006.281.08:20:51.57#ibcon#*before return 0, iclass 23, count 0 2006.281.08:20:51.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:20:51.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.281.08:20:51.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.281.08:20:51.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.281.08:20:51.57$vc4f8/vb=1,4 2006.281.08:20:51.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.281.08:20:51.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.281.08:20:51.57#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:51.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:20:51.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:20:51.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:20:51.57#ibcon#enter wrdev, iclass 25, count 2 2006.281.08:20:51.57#ibcon#first serial, iclass 25, count 2 2006.281.08:20:51.57#ibcon#enter sib2, iclass 25, count 2 2006.281.08:20:51.57#ibcon#flushed, iclass 25, count 2 2006.281.08:20:51.57#ibcon#about to write, iclass 25, count 2 2006.281.08:20:51.57#ibcon#wrote, iclass 25, count 2 2006.281.08:20:51.57#ibcon#about to read 3, iclass 25, count 2 2006.281.08:20:51.59#ibcon#read 3, iclass 25, count 2 2006.281.08:20:51.59#ibcon#about to read 4, iclass 25, count 2 2006.281.08:20:51.59#ibcon#read 4, iclass 25, count 2 2006.281.08:20:51.59#ibcon#about to read 5, iclass 25, count 2 2006.281.08:20:51.59#ibcon#read 5, iclass 25, count 2 2006.281.08:20:51.59#ibcon#about to read 6, iclass 25, count 2 2006.281.08:20:51.59#ibcon#read 6, iclass 25, count 2 2006.281.08:20:51.59#ibcon#end of sib2, iclass 25, count 2 2006.281.08:20:51.59#ibcon#*mode == 0, iclass 25, count 2 2006.281.08:20:51.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.281.08:20:51.59#ibcon#[27=AT01-04\r\n] 2006.281.08:20:51.59#ibcon#*before write, iclass 25, count 2 2006.281.08:20:51.59#ibcon#enter sib2, iclass 25, count 2 2006.281.08:20:51.59#ibcon#flushed, iclass 25, count 2 2006.281.08:20:51.59#ibcon#about to write, iclass 25, count 2 2006.281.08:20:51.59#ibcon#wrote, iclass 25, count 2 2006.281.08:20:51.59#ibcon#about to read 3, iclass 25, count 2 2006.281.08:20:51.62#ibcon#read 3, iclass 25, count 2 2006.281.08:20:51.64#ibcon#about to read 4, iclass 25, count 2 2006.281.08:20:51.64#ibcon#read 4, iclass 25, count 2 2006.281.08:20:51.64#ibcon#about to read 5, iclass 25, count 2 2006.281.08:20:51.64#ibcon#read 5, iclass 25, count 2 2006.281.08:20:51.64#ibcon#about to read 6, iclass 25, count 2 2006.281.08:20:51.64#ibcon#read 6, iclass 25, count 2 2006.281.08:20:51.64#ibcon#end of sib2, iclass 25, count 2 2006.281.08:20:51.64#ibcon#*after write, iclass 25, count 2 2006.281.08:20:51.64#ibcon#*before return 0, iclass 25, count 2 2006.281.08:20:51.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:20:51.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.281.08:20:51.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.281.08:20:51.64#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:51.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:20:51.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:20:51.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:20:51.75#ibcon#enter wrdev, iclass 25, count 0 2006.281.08:20:51.75#ibcon#first serial, iclass 25, count 0 2006.281.08:20:51.75#ibcon#enter sib2, iclass 25, count 0 2006.281.08:20:51.75#ibcon#flushed, iclass 25, count 0 2006.281.08:20:51.75#ibcon#about to write, iclass 25, count 0 2006.281.08:20:51.75#ibcon#wrote, iclass 25, count 0 2006.281.08:20:51.75#ibcon#about to read 3, iclass 25, count 0 2006.281.08:20:51.77#ibcon#read 3, iclass 25, count 0 2006.281.08:20:51.77#ibcon#about to read 4, iclass 25, count 0 2006.281.08:20:51.77#ibcon#read 4, iclass 25, count 0 2006.281.08:20:51.77#ibcon#about to read 5, iclass 25, count 0 2006.281.08:20:51.77#ibcon#read 5, iclass 25, count 0 2006.281.08:20:51.77#ibcon#about to read 6, iclass 25, count 0 2006.281.08:20:51.77#ibcon#read 6, iclass 25, count 0 2006.281.08:20:51.77#ibcon#end of sib2, iclass 25, count 0 2006.281.08:20:51.77#ibcon#*mode == 0, iclass 25, count 0 2006.281.08:20:51.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.281.08:20:51.77#ibcon#[27=USB\r\n] 2006.281.08:20:51.77#ibcon#*before write, iclass 25, count 0 2006.281.08:20:51.77#ibcon#enter sib2, iclass 25, count 0 2006.281.08:20:51.77#ibcon#flushed, iclass 25, count 0 2006.281.08:20:51.77#ibcon#about to write, iclass 25, count 0 2006.281.08:20:51.77#ibcon#wrote, iclass 25, count 0 2006.281.08:20:51.77#ibcon#about to read 3, iclass 25, count 0 2006.281.08:20:51.80#ibcon#read 3, iclass 25, count 0 2006.281.08:20:51.80#ibcon#about to read 4, iclass 25, count 0 2006.281.08:20:51.80#ibcon#read 4, iclass 25, count 0 2006.281.08:20:51.80#ibcon#about to read 5, iclass 25, count 0 2006.281.08:20:51.80#ibcon#read 5, iclass 25, count 0 2006.281.08:20:51.80#ibcon#about to read 6, iclass 25, count 0 2006.281.08:20:51.80#ibcon#read 6, iclass 25, count 0 2006.281.08:20:51.80#ibcon#end of sib2, iclass 25, count 0 2006.281.08:20:51.80#ibcon#*after write, iclass 25, count 0 2006.281.08:20:51.80#ibcon#*before return 0, iclass 25, count 0 2006.281.08:20:51.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:20:51.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.281.08:20:51.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.281.08:20:51.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.281.08:20:51.80$vc4f8/vblo=2,640.99 2006.281.08:20:51.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.281.08:20:51.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.281.08:20:51.80#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:51.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:51.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:51.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:51.80#ibcon#enter wrdev, iclass 27, count 0 2006.281.08:20:51.80#ibcon#first serial, iclass 27, count 0 2006.281.08:20:51.80#ibcon#enter sib2, iclass 27, count 0 2006.281.08:20:51.80#ibcon#flushed, iclass 27, count 0 2006.281.08:20:51.80#ibcon#about to write, iclass 27, count 0 2006.281.08:20:51.80#ibcon#wrote, iclass 27, count 0 2006.281.08:20:51.80#ibcon#about to read 3, iclass 27, count 0 2006.281.08:20:51.82#ibcon#read 3, iclass 27, count 0 2006.281.08:20:51.82#ibcon#about to read 4, iclass 27, count 0 2006.281.08:20:51.82#ibcon#read 4, iclass 27, count 0 2006.281.08:20:51.82#ibcon#about to read 5, iclass 27, count 0 2006.281.08:20:51.82#ibcon#read 5, iclass 27, count 0 2006.281.08:20:51.82#ibcon#about to read 6, iclass 27, count 0 2006.281.08:20:51.82#ibcon#read 6, iclass 27, count 0 2006.281.08:20:51.82#ibcon#end of sib2, iclass 27, count 0 2006.281.08:20:51.82#ibcon#*mode == 0, iclass 27, count 0 2006.281.08:20:51.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.281.08:20:51.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:20:51.82#ibcon#*before write, iclass 27, count 0 2006.281.08:20:51.82#ibcon#enter sib2, iclass 27, count 0 2006.281.08:20:51.82#ibcon#flushed, iclass 27, count 0 2006.281.08:20:51.82#ibcon#about to write, iclass 27, count 0 2006.281.08:20:51.82#ibcon#wrote, iclass 27, count 0 2006.281.08:20:51.82#ibcon#about to read 3, iclass 27, count 0 2006.281.08:20:51.86#ibcon#read 3, iclass 27, count 0 2006.281.08:20:51.86#ibcon#about to read 4, iclass 27, count 0 2006.281.08:20:51.86#ibcon#read 4, iclass 27, count 0 2006.281.08:20:51.86#ibcon#about to read 5, iclass 27, count 0 2006.281.08:20:51.86#ibcon#read 5, iclass 27, count 0 2006.281.08:20:51.86#ibcon#about to read 6, iclass 27, count 0 2006.281.08:20:51.86#ibcon#read 6, iclass 27, count 0 2006.281.08:20:51.86#ibcon#end of sib2, iclass 27, count 0 2006.281.08:20:51.86#ibcon#*after write, iclass 27, count 0 2006.281.08:20:51.86#ibcon#*before return 0, iclass 27, count 0 2006.281.08:20:51.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:51.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.281.08:20:51.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.281.08:20:51.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.281.08:20:51.86$vc4f8/vb=2,5 2006.281.08:20:51.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.281.08:20:51.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.281.08:20:51.86#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:51.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:51.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:51.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:51.92#ibcon#enter wrdev, iclass 29, count 2 2006.281.08:20:51.92#ibcon#first serial, iclass 29, count 2 2006.281.08:20:51.92#ibcon#enter sib2, iclass 29, count 2 2006.281.08:20:51.92#ibcon#flushed, iclass 29, count 2 2006.281.08:20:51.92#ibcon#about to write, iclass 29, count 2 2006.281.08:20:51.92#ibcon#wrote, iclass 29, count 2 2006.281.08:20:51.92#ibcon#about to read 3, iclass 29, count 2 2006.281.08:20:51.94#ibcon#read 3, iclass 29, count 2 2006.281.08:20:51.94#ibcon#about to read 4, iclass 29, count 2 2006.281.08:20:51.94#ibcon#read 4, iclass 29, count 2 2006.281.08:20:51.94#ibcon#about to read 5, iclass 29, count 2 2006.281.08:20:51.94#ibcon#read 5, iclass 29, count 2 2006.281.08:20:51.94#ibcon#about to read 6, iclass 29, count 2 2006.281.08:20:51.94#ibcon#read 6, iclass 29, count 2 2006.281.08:20:51.94#ibcon#end of sib2, iclass 29, count 2 2006.281.08:20:51.94#ibcon#*mode == 0, iclass 29, count 2 2006.281.08:20:51.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.281.08:20:51.94#ibcon#[27=AT02-05\r\n] 2006.281.08:20:51.94#ibcon#*before write, iclass 29, count 2 2006.281.08:20:51.94#ibcon#enter sib2, iclass 29, count 2 2006.281.08:20:51.94#ibcon#flushed, iclass 29, count 2 2006.281.08:20:51.94#ibcon#about to write, iclass 29, count 2 2006.281.08:20:51.94#ibcon#wrote, iclass 29, count 2 2006.281.08:20:51.94#ibcon#about to read 3, iclass 29, count 2 2006.281.08:20:51.97#ibcon#read 3, iclass 29, count 2 2006.281.08:20:51.97#ibcon#about to read 4, iclass 29, count 2 2006.281.08:20:51.97#ibcon#read 4, iclass 29, count 2 2006.281.08:20:51.97#ibcon#about to read 5, iclass 29, count 2 2006.281.08:20:51.97#ibcon#read 5, iclass 29, count 2 2006.281.08:20:51.97#ibcon#about to read 6, iclass 29, count 2 2006.281.08:20:51.97#ibcon#read 6, iclass 29, count 2 2006.281.08:20:51.97#ibcon#end of sib2, iclass 29, count 2 2006.281.08:20:51.97#ibcon#*after write, iclass 29, count 2 2006.281.08:20:51.97#ibcon#*before return 0, iclass 29, count 2 2006.281.08:20:51.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:51.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.281.08:20:51.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.281.08:20:51.97#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:51.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:52.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:52.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:52.09#ibcon#enter wrdev, iclass 29, count 0 2006.281.08:20:52.09#ibcon#first serial, iclass 29, count 0 2006.281.08:20:52.09#ibcon#enter sib2, iclass 29, count 0 2006.281.08:20:52.09#ibcon#flushed, iclass 29, count 0 2006.281.08:20:52.09#ibcon#about to write, iclass 29, count 0 2006.281.08:20:52.09#ibcon#wrote, iclass 29, count 0 2006.281.08:20:52.09#ibcon#about to read 3, iclass 29, count 0 2006.281.08:20:52.11#ibcon#read 3, iclass 29, count 0 2006.281.08:20:52.11#ibcon#about to read 4, iclass 29, count 0 2006.281.08:20:52.11#ibcon#read 4, iclass 29, count 0 2006.281.08:20:52.11#ibcon#about to read 5, iclass 29, count 0 2006.281.08:20:52.11#ibcon#read 5, iclass 29, count 0 2006.281.08:20:52.11#ibcon#about to read 6, iclass 29, count 0 2006.281.08:20:52.11#ibcon#read 6, iclass 29, count 0 2006.281.08:20:52.11#ibcon#end of sib2, iclass 29, count 0 2006.281.08:20:52.11#ibcon#*mode == 0, iclass 29, count 0 2006.281.08:20:52.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.281.08:20:52.11#ibcon#[27=USB\r\n] 2006.281.08:20:52.11#ibcon#*before write, iclass 29, count 0 2006.281.08:20:52.11#ibcon#enter sib2, iclass 29, count 0 2006.281.08:20:52.11#ibcon#flushed, iclass 29, count 0 2006.281.08:20:52.11#ibcon#about to write, iclass 29, count 0 2006.281.08:20:52.11#ibcon#wrote, iclass 29, count 0 2006.281.08:20:52.11#ibcon#about to read 3, iclass 29, count 0 2006.281.08:20:52.14#ibcon#read 3, iclass 29, count 0 2006.281.08:20:52.14#ibcon#about to read 4, iclass 29, count 0 2006.281.08:20:52.14#ibcon#read 4, iclass 29, count 0 2006.281.08:20:52.14#ibcon#about to read 5, iclass 29, count 0 2006.281.08:20:52.14#ibcon#read 5, iclass 29, count 0 2006.281.08:20:52.14#ibcon#about to read 6, iclass 29, count 0 2006.281.08:20:52.14#ibcon#read 6, iclass 29, count 0 2006.281.08:20:52.14#ibcon#end of sib2, iclass 29, count 0 2006.281.08:20:52.14#ibcon#*after write, iclass 29, count 0 2006.281.08:20:52.14#ibcon#*before return 0, iclass 29, count 0 2006.281.08:20:52.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:52.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.281.08:20:52.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.281.08:20:52.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.281.08:20:52.14$vc4f8/vblo=3,656.99 2006.281.08:20:52.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.281.08:20:52.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.281.08:20:52.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:52.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:52.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:52.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:52.14#ibcon#enter wrdev, iclass 31, count 0 2006.281.08:20:52.14#ibcon#first serial, iclass 31, count 0 2006.281.08:20:52.14#ibcon#enter sib2, iclass 31, count 0 2006.281.08:20:52.14#ibcon#flushed, iclass 31, count 0 2006.281.08:20:52.14#ibcon#about to write, iclass 31, count 0 2006.281.08:20:52.14#ibcon#wrote, iclass 31, count 0 2006.281.08:20:52.14#ibcon#about to read 3, iclass 31, count 0 2006.281.08:20:52.16#ibcon#read 3, iclass 31, count 0 2006.281.08:20:52.16#ibcon#about to read 4, iclass 31, count 0 2006.281.08:20:52.16#ibcon#read 4, iclass 31, count 0 2006.281.08:20:52.16#ibcon#about to read 5, iclass 31, count 0 2006.281.08:20:52.16#ibcon#read 5, iclass 31, count 0 2006.281.08:20:52.16#ibcon#about to read 6, iclass 31, count 0 2006.281.08:20:52.16#ibcon#read 6, iclass 31, count 0 2006.281.08:20:52.16#ibcon#end of sib2, iclass 31, count 0 2006.281.08:20:52.16#ibcon#*mode == 0, iclass 31, count 0 2006.281.08:20:52.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.281.08:20:52.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:20:52.16#ibcon#*before write, iclass 31, count 0 2006.281.08:20:52.16#ibcon#enter sib2, iclass 31, count 0 2006.281.08:20:52.16#ibcon#flushed, iclass 31, count 0 2006.281.08:20:52.16#ibcon#about to write, iclass 31, count 0 2006.281.08:20:52.16#ibcon#wrote, iclass 31, count 0 2006.281.08:20:52.16#ibcon#about to read 3, iclass 31, count 0 2006.281.08:20:52.21#ibcon#read 3, iclass 31, count 0 2006.281.08:20:52.21#ibcon#about to read 4, iclass 31, count 0 2006.281.08:20:52.21#ibcon#read 4, iclass 31, count 0 2006.281.08:20:52.21#ibcon#about to read 5, iclass 31, count 0 2006.281.08:20:52.21#ibcon#read 5, iclass 31, count 0 2006.281.08:20:52.21#ibcon#about to read 6, iclass 31, count 0 2006.281.08:20:52.21#ibcon#read 6, iclass 31, count 0 2006.281.08:20:52.21#ibcon#end of sib2, iclass 31, count 0 2006.281.08:20:52.21#ibcon#*after write, iclass 31, count 0 2006.281.08:20:52.21#ibcon#*before return 0, iclass 31, count 0 2006.281.08:20:52.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:52.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.281.08:20:52.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.281.08:20:52.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.281.08:20:52.21$vc4f8/vb=3,4 2006.281.08:20:52.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.281.08:20:52.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.281.08:20:52.21#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:52.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:52.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:52.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:52.25#ibcon#enter wrdev, iclass 33, count 2 2006.281.08:20:52.25#ibcon#first serial, iclass 33, count 2 2006.281.08:20:52.25#ibcon#enter sib2, iclass 33, count 2 2006.281.08:20:52.25#ibcon#flushed, iclass 33, count 2 2006.281.08:20:52.25#ibcon#about to write, iclass 33, count 2 2006.281.08:20:52.25#ibcon#wrote, iclass 33, count 2 2006.281.08:20:52.25#ibcon#about to read 3, iclass 33, count 2 2006.281.08:20:52.27#ibcon#read 3, iclass 33, count 2 2006.281.08:20:52.27#ibcon#about to read 4, iclass 33, count 2 2006.281.08:20:52.27#ibcon#read 4, iclass 33, count 2 2006.281.08:20:52.27#ibcon#about to read 5, iclass 33, count 2 2006.281.08:20:52.27#ibcon#read 5, iclass 33, count 2 2006.281.08:20:52.27#ibcon#about to read 6, iclass 33, count 2 2006.281.08:20:52.27#ibcon#read 6, iclass 33, count 2 2006.281.08:20:52.27#ibcon#end of sib2, iclass 33, count 2 2006.281.08:20:52.27#ibcon#*mode == 0, iclass 33, count 2 2006.281.08:20:52.27#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.281.08:20:52.27#ibcon#[27=AT03-04\r\n] 2006.281.08:20:52.27#ibcon#*before write, iclass 33, count 2 2006.281.08:20:52.27#ibcon#enter sib2, iclass 33, count 2 2006.281.08:20:52.27#ibcon#flushed, iclass 33, count 2 2006.281.08:20:52.27#ibcon#about to write, iclass 33, count 2 2006.281.08:20:52.27#ibcon#wrote, iclass 33, count 2 2006.281.08:20:52.27#ibcon#about to read 3, iclass 33, count 2 2006.281.08:20:52.31#ibcon#read 3, iclass 33, count 2 2006.281.08:20:52.31#ibcon#about to read 4, iclass 33, count 2 2006.281.08:20:52.31#ibcon#read 4, iclass 33, count 2 2006.281.08:20:52.31#ibcon#about to read 5, iclass 33, count 2 2006.281.08:20:52.31#ibcon#read 5, iclass 33, count 2 2006.281.08:20:52.31#ibcon#about to read 6, iclass 33, count 2 2006.281.08:20:52.31#ibcon#read 6, iclass 33, count 2 2006.281.08:20:52.31#ibcon#end of sib2, iclass 33, count 2 2006.281.08:20:52.31#ibcon#*after write, iclass 33, count 2 2006.281.08:20:52.31#ibcon#*before return 0, iclass 33, count 2 2006.281.08:20:52.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:52.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.281.08:20:52.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.281.08:20:52.31#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:52.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:52.42#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:52.42#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:52.42#ibcon#enter wrdev, iclass 33, count 0 2006.281.08:20:52.42#ibcon#first serial, iclass 33, count 0 2006.281.08:20:52.42#ibcon#enter sib2, iclass 33, count 0 2006.281.08:20:52.42#ibcon#flushed, iclass 33, count 0 2006.281.08:20:52.42#ibcon#about to write, iclass 33, count 0 2006.281.08:20:52.42#ibcon#wrote, iclass 33, count 0 2006.281.08:20:52.42#ibcon#about to read 3, iclass 33, count 0 2006.281.08:20:52.44#ibcon#read 3, iclass 33, count 0 2006.281.08:20:52.44#ibcon#about to read 4, iclass 33, count 0 2006.281.08:20:52.44#ibcon#read 4, iclass 33, count 0 2006.281.08:20:52.44#ibcon#about to read 5, iclass 33, count 0 2006.281.08:20:52.44#ibcon#read 5, iclass 33, count 0 2006.281.08:20:52.44#ibcon#about to read 6, iclass 33, count 0 2006.281.08:20:52.44#ibcon#read 6, iclass 33, count 0 2006.281.08:20:52.44#ibcon#end of sib2, iclass 33, count 0 2006.281.08:20:52.44#ibcon#*mode == 0, iclass 33, count 0 2006.281.08:20:52.44#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.281.08:20:52.44#ibcon#[27=USB\r\n] 2006.281.08:20:52.44#ibcon#*before write, iclass 33, count 0 2006.281.08:20:52.44#ibcon#enter sib2, iclass 33, count 0 2006.281.08:20:52.44#ibcon#flushed, iclass 33, count 0 2006.281.08:20:52.44#ibcon#about to write, iclass 33, count 0 2006.281.08:20:52.44#ibcon#wrote, iclass 33, count 0 2006.281.08:20:52.44#ibcon#about to read 3, iclass 33, count 0 2006.281.08:20:52.47#ibcon#read 3, iclass 33, count 0 2006.281.08:20:52.47#ibcon#about to read 4, iclass 33, count 0 2006.281.08:20:52.47#ibcon#read 4, iclass 33, count 0 2006.281.08:20:52.47#ibcon#about to read 5, iclass 33, count 0 2006.281.08:20:52.47#ibcon#read 5, iclass 33, count 0 2006.281.08:20:52.47#ibcon#about to read 6, iclass 33, count 0 2006.281.08:20:52.47#ibcon#read 6, iclass 33, count 0 2006.281.08:20:52.47#ibcon#end of sib2, iclass 33, count 0 2006.281.08:20:52.47#ibcon#*after write, iclass 33, count 0 2006.281.08:20:52.47#ibcon#*before return 0, iclass 33, count 0 2006.281.08:20:52.47#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:52.47#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.281.08:20:52.47#ibcon#about to clear, iclass 33 cls_cnt 0 2006.281.08:20:52.47#ibcon#cleared, iclass 33 cls_cnt 0 2006.281.08:20:52.47$vc4f8/vblo=4,712.99 2006.281.08:20:52.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.281.08:20:52.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.281.08:20:52.47#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:52.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:52.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:52.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:52.47#ibcon#enter wrdev, iclass 35, count 0 2006.281.08:20:52.47#ibcon#first serial, iclass 35, count 0 2006.281.08:20:52.47#ibcon#enter sib2, iclass 35, count 0 2006.281.08:20:52.47#ibcon#flushed, iclass 35, count 0 2006.281.08:20:52.47#ibcon#about to write, iclass 35, count 0 2006.281.08:20:52.47#ibcon#wrote, iclass 35, count 0 2006.281.08:20:52.47#ibcon#about to read 3, iclass 35, count 0 2006.281.08:20:52.49#ibcon#read 3, iclass 35, count 0 2006.281.08:20:52.49#ibcon#about to read 4, iclass 35, count 0 2006.281.08:20:52.49#ibcon#read 4, iclass 35, count 0 2006.281.08:20:52.49#ibcon#about to read 5, iclass 35, count 0 2006.281.08:20:52.49#ibcon#read 5, iclass 35, count 0 2006.281.08:20:52.49#ibcon#about to read 6, iclass 35, count 0 2006.281.08:20:52.49#ibcon#read 6, iclass 35, count 0 2006.281.08:20:52.49#ibcon#end of sib2, iclass 35, count 0 2006.281.08:20:52.49#ibcon#*mode == 0, iclass 35, count 0 2006.281.08:20:52.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.281.08:20:52.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:20:52.51#ibcon#*before write, iclass 35, count 0 2006.281.08:20:52.51#ibcon#enter sib2, iclass 35, count 0 2006.281.08:20:52.51#ibcon#flushed, iclass 35, count 0 2006.281.08:20:52.51#ibcon#about to write, iclass 35, count 0 2006.281.08:20:52.51#ibcon#wrote, iclass 35, count 0 2006.281.08:20:52.51#ibcon#about to read 3, iclass 35, count 0 2006.281.08:20:52.55#ibcon#read 3, iclass 35, count 0 2006.281.08:20:52.55#ibcon#about to read 4, iclass 35, count 0 2006.281.08:20:52.55#ibcon#read 4, iclass 35, count 0 2006.281.08:20:52.55#ibcon#about to read 5, iclass 35, count 0 2006.281.08:20:52.55#ibcon#read 5, iclass 35, count 0 2006.281.08:20:52.55#ibcon#about to read 6, iclass 35, count 0 2006.281.08:20:52.55#ibcon#read 6, iclass 35, count 0 2006.281.08:20:52.55#ibcon#end of sib2, iclass 35, count 0 2006.281.08:20:52.55#ibcon#*after write, iclass 35, count 0 2006.281.08:20:52.55#ibcon#*before return 0, iclass 35, count 0 2006.281.08:20:52.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:52.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.281.08:20:52.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.281.08:20:52.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.281.08:20:52.55$vc4f8/vb=4,4 2006.281.08:20:52.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.281.08:20:52.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.281.08:20:52.55#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:52.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:52.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:52.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:52.59#ibcon#enter wrdev, iclass 37, count 2 2006.281.08:20:52.59#ibcon#first serial, iclass 37, count 2 2006.281.08:20:52.59#ibcon#enter sib2, iclass 37, count 2 2006.281.08:20:52.59#ibcon#flushed, iclass 37, count 2 2006.281.08:20:52.59#ibcon#about to write, iclass 37, count 2 2006.281.08:20:52.59#ibcon#wrote, iclass 37, count 2 2006.281.08:20:52.59#ibcon#about to read 3, iclass 37, count 2 2006.281.08:20:52.61#ibcon#read 3, iclass 37, count 2 2006.281.08:20:52.61#ibcon#about to read 4, iclass 37, count 2 2006.281.08:20:52.61#ibcon#read 4, iclass 37, count 2 2006.281.08:20:52.61#ibcon#about to read 5, iclass 37, count 2 2006.281.08:20:52.61#ibcon#read 5, iclass 37, count 2 2006.281.08:20:52.61#ibcon#about to read 6, iclass 37, count 2 2006.281.08:20:52.61#ibcon#read 6, iclass 37, count 2 2006.281.08:20:52.61#ibcon#end of sib2, iclass 37, count 2 2006.281.08:20:52.61#ibcon#*mode == 0, iclass 37, count 2 2006.281.08:20:52.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.281.08:20:52.61#ibcon#[27=AT04-04\r\n] 2006.281.08:20:52.61#ibcon#*before write, iclass 37, count 2 2006.281.08:20:52.61#ibcon#enter sib2, iclass 37, count 2 2006.281.08:20:52.61#ibcon#flushed, iclass 37, count 2 2006.281.08:20:52.61#ibcon#about to write, iclass 37, count 2 2006.281.08:20:52.61#ibcon#wrote, iclass 37, count 2 2006.281.08:20:52.61#ibcon#about to read 3, iclass 37, count 2 2006.281.08:20:52.64#ibcon#read 3, iclass 37, count 2 2006.281.08:20:52.64#ibcon#about to read 4, iclass 37, count 2 2006.281.08:20:52.64#ibcon#read 4, iclass 37, count 2 2006.281.08:20:52.64#ibcon#about to read 5, iclass 37, count 2 2006.281.08:20:52.64#ibcon#read 5, iclass 37, count 2 2006.281.08:20:52.64#ibcon#about to read 6, iclass 37, count 2 2006.281.08:20:52.64#ibcon#read 6, iclass 37, count 2 2006.281.08:20:52.64#ibcon#end of sib2, iclass 37, count 2 2006.281.08:20:52.64#ibcon#*after write, iclass 37, count 2 2006.281.08:20:52.64#ibcon#*before return 0, iclass 37, count 2 2006.281.08:20:52.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:52.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.281.08:20:52.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.281.08:20:52.64#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:52.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:52.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:52.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:52.76#ibcon#enter wrdev, iclass 37, count 0 2006.281.08:20:52.76#ibcon#first serial, iclass 37, count 0 2006.281.08:20:52.76#ibcon#enter sib2, iclass 37, count 0 2006.281.08:20:52.76#ibcon#flushed, iclass 37, count 0 2006.281.08:20:52.76#ibcon#about to write, iclass 37, count 0 2006.281.08:20:52.76#ibcon#wrote, iclass 37, count 0 2006.281.08:20:52.76#ibcon#about to read 3, iclass 37, count 0 2006.281.08:20:52.78#ibcon#read 3, iclass 37, count 0 2006.281.08:20:52.78#ibcon#about to read 4, iclass 37, count 0 2006.281.08:20:52.78#ibcon#read 4, iclass 37, count 0 2006.281.08:20:52.78#ibcon#about to read 5, iclass 37, count 0 2006.281.08:20:52.78#ibcon#read 5, iclass 37, count 0 2006.281.08:20:52.78#ibcon#about to read 6, iclass 37, count 0 2006.281.08:20:52.78#ibcon#read 6, iclass 37, count 0 2006.281.08:20:52.78#ibcon#end of sib2, iclass 37, count 0 2006.281.08:20:52.78#ibcon#*mode == 0, iclass 37, count 0 2006.281.08:20:52.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.281.08:20:52.78#ibcon#[27=USB\r\n] 2006.281.08:20:52.78#ibcon#*before write, iclass 37, count 0 2006.281.08:20:52.78#ibcon#enter sib2, iclass 37, count 0 2006.281.08:20:52.78#ibcon#flushed, iclass 37, count 0 2006.281.08:20:52.78#ibcon#about to write, iclass 37, count 0 2006.281.08:20:52.78#ibcon#wrote, iclass 37, count 0 2006.281.08:20:52.78#ibcon#about to read 3, iclass 37, count 0 2006.281.08:20:52.81#ibcon#read 3, iclass 37, count 0 2006.281.08:20:52.81#ibcon#about to read 4, iclass 37, count 0 2006.281.08:20:52.81#ibcon#read 4, iclass 37, count 0 2006.281.08:20:52.81#ibcon#about to read 5, iclass 37, count 0 2006.281.08:20:52.81#ibcon#read 5, iclass 37, count 0 2006.281.08:20:52.81#ibcon#about to read 6, iclass 37, count 0 2006.281.08:20:52.81#ibcon#read 6, iclass 37, count 0 2006.281.08:20:52.81#ibcon#end of sib2, iclass 37, count 0 2006.281.08:20:52.81#ibcon#*after write, iclass 37, count 0 2006.281.08:20:52.81#ibcon#*before return 0, iclass 37, count 0 2006.281.08:20:52.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:52.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.281.08:20:52.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.281.08:20:52.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.281.08:20:52.81$vc4f8/vblo=5,744.99 2006.281.08:20:52.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.281.08:20:52.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.281.08:20:52.81#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:52.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:52.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:52.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:52.81#ibcon#enter wrdev, iclass 39, count 0 2006.281.08:20:52.81#ibcon#first serial, iclass 39, count 0 2006.281.08:20:52.81#ibcon#enter sib2, iclass 39, count 0 2006.281.08:20:52.81#ibcon#flushed, iclass 39, count 0 2006.281.08:20:52.81#ibcon#about to write, iclass 39, count 0 2006.281.08:20:52.81#ibcon#wrote, iclass 39, count 0 2006.281.08:20:52.81#ibcon#about to read 3, iclass 39, count 0 2006.281.08:20:52.83#ibcon#read 3, iclass 39, count 0 2006.281.08:20:52.83#ibcon#about to read 4, iclass 39, count 0 2006.281.08:20:52.83#ibcon#read 4, iclass 39, count 0 2006.281.08:20:52.83#ibcon#about to read 5, iclass 39, count 0 2006.281.08:20:52.83#ibcon#read 5, iclass 39, count 0 2006.281.08:20:52.83#ibcon#about to read 6, iclass 39, count 0 2006.281.08:20:52.83#ibcon#read 6, iclass 39, count 0 2006.281.08:20:52.83#ibcon#end of sib2, iclass 39, count 0 2006.281.08:20:52.83#ibcon#*mode == 0, iclass 39, count 0 2006.281.08:20:52.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.281.08:20:52.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:20:52.83#ibcon#*before write, iclass 39, count 0 2006.281.08:20:52.83#ibcon#enter sib2, iclass 39, count 0 2006.281.08:20:52.83#ibcon#flushed, iclass 39, count 0 2006.281.08:20:52.83#ibcon#about to write, iclass 39, count 0 2006.281.08:20:52.83#ibcon#wrote, iclass 39, count 0 2006.281.08:20:52.83#ibcon#about to read 3, iclass 39, count 0 2006.281.08:20:52.87#ibcon#read 3, iclass 39, count 0 2006.281.08:20:52.87#ibcon#about to read 4, iclass 39, count 0 2006.281.08:20:52.88#ibcon#read 4, iclass 39, count 0 2006.281.08:20:52.88#ibcon#about to read 5, iclass 39, count 0 2006.281.08:20:52.88#ibcon#read 5, iclass 39, count 0 2006.281.08:20:52.88#ibcon#about to read 6, iclass 39, count 0 2006.281.08:20:52.88#ibcon#read 6, iclass 39, count 0 2006.281.08:20:52.88#ibcon#end of sib2, iclass 39, count 0 2006.281.08:20:52.88#ibcon#*after write, iclass 39, count 0 2006.281.08:20:52.88#ibcon#*before return 0, iclass 39, count 0 2006.281.08:20:52.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:52.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.281.08:20:52.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.281.08:20:52.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.281.08:20:52.88$vc4f8/vb=5,4 2006.281.08:20:52.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.281.08:20:52.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.281.08:20:52.88#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:52.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:52.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:52.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:52.92#ibcon#enter wrdev, iclass 3, count 2 2006.281.08:20:52.92#ibcon#first serial, iclass 3, count 2 2006.281.08:20:52.92#ibcon#enter sib2, iclass 3, count 2 2006.281.08:20:52.92#ibcon#flushed, iclass 3, count 2 2006.281.08:20:52.92#ibcon#about to write, iclass 3, count 2 2006.281.08:20:52.92#ibcon#wrote, iclass 3, count 2 2006.281.08:20:52.92#ibcon#about to read 3, iclass 3, count 2 2006.281.08:20:52.94#ibcon#read 3, iclass 3, count 2 2006.281.08:20:52.94#ibcon#about to read 4, iclass 3, count 2 2006.281.08:20:52.94#ibcon#read 4, iclass 3, count 2 2006.281.08:20:52.94#ibcon#about to read 5, iclass 3, count 2 2006.281.08:20:52.94#ibcon#read 5, iclass 3, count 2 2006.281.08:20:52.94#ibcon#about to read 6, iclass 3, count 2 2006.281.08:20:52.94#ibcon#read 6, iclass 3, count 2 2006.281.08:20:52.94#ibcon#end of sib2, iclass 3, count 2 2006.281.08:20:52.94#ibcon#*mode == 0, iclass 3, count 2 2006.281.08:20:52.94#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.281.08:20:52.94#ibcon#[27=AT05-04\r\n] 2006.281.08:20:52.94#ibcon#*before write, iclass 3, count 2 2006.281.08:20:52.94#ibcon#enter sib2, iclass 3, count 2 2006.281.08:20:52.94#ibcon#flushed, iclass 3, count 2 2006.281.08:20:52.94#ibcon#about to write, iclass 3, count 2 2006.281.08:20:52.94#ibcon#wrote, iclass 3, count 2 2006.281.08:20:52.94#ibcon#about to read 3, iclass 3, count 2 2006.281.08:20:52.97#ibcon#read 3, iclass 3, count 2 2006.281.08:20:52.97#ibcon#about to read 4, iclass 3, count 2 2006.281.08:20:52.97#ibcon#read 4, iclass 3, count 2 2006.281.08:20:52.97#ibcon#about to read 5, iclass 3, count 2 2006.281.08:20:52.97#ibcon#read 5, iclass 3, count 2 2006.281.08:20:52.97#ibcon#about to read 6, iclass 3, count 2 2006.281.08:20:52.97#ibcon#read 6, iclass 3, count 2 2006.281.08:20:52.97#ibcon#end of sib2, iclass 3, count 2 2006.281.08:20:52.97#ibcon#*after write, iclass 3, count 2 2006.281.08:20:52.97#ibcon#*before return 0, iclass 3, count 2 2006.281.08:20:52.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:52.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.281.08:20:52.97#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.281.08:20:52.97#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:52.97#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:53.09#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:53.09#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:53.09#ibcon#enter wrdev, iclass 3, count 0 2006.281.08:20:53.09#ibcon#first serial, iclass 3, count 0 2006.281.08:20:53.09#ibcon#enter sib2, iclass 3, count 0 2006.281.08:20:53.09#ibcon#flushed, iclass 3, count 0 2006.281.08:20:53.09#ibcon#about to write, iclass 3, count 0 2006.281.08:20:53.09#ibcon#wrote, iclass 3, count 0 2006.281.08:20:53.09#ibcon#about to read 3, iclass 3, count 0 2006.281.08:20:53.11#ibcon#read 3, iclass 3, count 0 2006.281.08:20:53.11#ibcon#about to read 4, iclass 3, count 0 2006.281.08:20:53.11#ibcon#read 4, iclass 3, count 0 2006.281.08:20:53.11#ibcon#about to read 5, iclass 3, count 0 2006.281.08:20:53.11#ibcon#read 5, iclass 3, count 0 2006.281.08:20:53.11#ibcon#about to read 6, iclass 3, count 0 2006.281.08:20:53.11#ibcon#read 6, iclass 3, count 0 2006.281.08:20:53.11#ibcon#end of sib2, iclass 3, count 0 2006.281.08:20:53.11#ibcon#*mode == 0, iclass 3, count 0 2006.281.08:20:53.11#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.281.08:20:53.11#ibcon#[27=USB\r\n] 2006.281.08:20:53.11#ibcon#*before write, iclass 3, count 0 2006.281.08:20:53.11#ibcon#enter sib2, iclass 3, count 0 2006.281.08:20:53.11#ibcon#flushed, iclass 3, count 0 2006.281.08:20:53.11#ibcon#about to write, iclass 3, count 0 2006.281.08:20:53.11#ibcon#wrote, iclass 3, count 0 2006.281.08:20:53.11#ibcon#about to read 3, iclass 3, count 0 2006.281.08:20:53.14#ibcon#read 3, iclass 3, count 0 2006.281.08:20:53.14#ibcon#about to read 4, iclass 3, count 0 2006.281.08:20:53.14#ibcon#read 4, iclass 3, count 0 2006.281.08:20:53.14#ibcon#about to read 5, iclass 3, count 0 2006.281.08:20:53.14#ibcon#read 5, iclass 3, count 0 2006.281.08:20:53.14#ibcon#about to read 6, iclass 3, count 0 2006.281.08:20:53.14#ibcon#read 6, iclass 3, count 0 2006.281.08:20:53.14#ibcon#end of sib2, iclass 3, count 0 2006.281.08:20:53.14#ibcon#*after write, iclass 3, count 0 2006.281.08:20:53.14#ibcon#*before return 0, iclass 3, count 0 2006.281.08:20:53.14#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:53.14#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.281.08:20:53.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.281.08:20:53.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.281.08:20:53.14$vc4f8/vblo=6,752.99 2006.281.08:20:53.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.281.08:20:53.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.281.08:20:53.14#ibcon#ireg 17 cls_cnt 0 2006.281.08:20:53.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:53.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:53.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:53.14#ibcon#enter wrdev, iclass 5, count 0 2006.281.08:20:53.14#ibcon#first serial, iclass 5, count 0 2006.281.08:20:53.14#ibcon#enter sib2, iclass 5, count 0 2006.281.08:20:53.14#ibcon#flushed, iclass 5, count 0 2006.281.08:20:53.14#ibcon#about to write, iclass 5, count 0 2006.281.08:20:53.14#ibcon#wrote, iclass 5, count 0 2006.281.08:20:53.14#ibcon#about to read 3, iclass 5, count 0 2006.281.08:20:53.16#ibcon#read 3, iclass 5, count 0 2006.281.08:20:53.16#ibcon#about to read 4, iclass 5, count 0 2006.281.08:20:53.16#ibcon#read 4, iclass 5, count 0 2006.281.08:20:53.16#ibcon#about to read 5, iclass 5, count 0 2006.281.08:20:53.16#ibcon#read 5, iclass 5, count 0 2006.281.08:20:53.16#ibcon#about to read 6, iclass 5, count 0 2006.281.08:20:53.16#ibcon#read 6, iclass 5, count 0 2006.281.08:20:53.16#ibcon#end of sib2, iclass 5, count 0 2006.281.08:20:53.16#ibcon#*mode == 0, iclass 5, count 0 2006.281.08:20:53.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.281.08:20:53.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:20:53.16#ibcon#*before write, iclass 5, count 0 2006.281.08:20:53.16#ibcon#enter sib2, iclass 5, count 0 2006.281.08:20:53.16#ibcon#flushed, iclass 5, count 0 2006.281.08:20:53.16#ibcon#about to write, iclass 5, count 0 2006.281.08:20:53.16#ibcon#wrote, iclass 5, count 0 2006.281.08:20:53.16#ibcon#about to read 3, iclass 5, count 0 2006.281.08:20:53.21#ibcon#read 3, iclass 5, count 0 2006.281.08:20:53.21#ibcon#about to read 4, iclass 5, count 0 2006.281.08:20:53.21#ibcon#read 4, iclass 5, count 0 2006.281.08:20:53.21#ibcon#about to read 5, iclass 5, count 0 2006.281.08:20:53.21#ibcon#read 5, iclass 5, count 0 2006.281.08:20:53.21#ibcon#about to read 6, iclass 5, count 0 2006.281.08:20:53.21#ibcon#read 6, iclass 5, count 0 2006.281.08:20:53.21#ibcon#end of sib2, iclass 5, count 0 2006.281.08:20:53.21#ibcon#*after write, iclass 5, count 0 2006.281.08:20:53.21#ibcon#*before return 0, iclass 5, count 0 2006.281.08:20:53.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:53.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.281.08:20:53.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.281.08:20:53.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.281.08:20:53.21$vc4f8/vb=6,4 2006.281.08:20:53.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:20:53.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:20:53.22#ibcon#ireg 11 cls_cnt 2 2006.281.08:20:53.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:20:53.24#abcon#<5=/13 2.7 9.5 19.96 521001.7\r\n> 2006.281.08:20:53.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:20:53.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:20:53.25#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:20:53.25#ibcon#first serial, iclass 10, count 2 2006.281.08:20:53.25#ibcon#enter sib2, iclass 10, count 2 2006.281.08:20:53.25#ibcon#flushed, iclass 10, count 2 2006.281.08:20:53.25#ibcon#about to write, iclass 10, count 2 2006.281.08:20:53.25#ibcon#wrote, iclass 10, count 2 2006.281.08:20:53.25#ibcon#about to read 3, iclass 10, count 2 2006.281.08:20:53.27#abcon#{5=INTERFACE CLEAR} 2006.281.08:20:53.28#ibcon#read 3, iclass 10, count 2 2006.281.08:20:53.28#ibcon#about to read 4, iclass 10, count 2 2006.281.08:20:53.28#ibcon#read 4, iclass 10, count 2 2006.281.08:20:53.28#ibcon#about to read 5, iclass 10, count 2 2006.281.08:20:53.28#ibcon#read 5, iclass 10, count 2 2006.281.08:20:53.28#ibcon#about to read 6, iclass 10, count 2 2006.281.08:20:53.28#ibcon#read 6, iclass 10, count 2 2006.281.08:20:53.28#ibcon#end of sib2, iclass 10, count 2 2006.281.08:20:53.28#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:20:53.28#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:20:53.28#ibcon#[27=AT06-04\r\n] 2006.281.08:20:53.28#ibcon#*before write, iclass 10, count 2 2006.281.08:20:53.28#ibcon#enter sib2, iclass 10, count 2 2006.281.08:20:53.28#ibcon#flushed, iclass 10, count 2 2006.281.08:20:53.28#ibcon#about to write, iclass 10, count 2 2006.281.08:20:53.28#ibcon#wrote, iclass 10, count 2 2006.281.08:20:53.28#ibcon#about to read 3, iclass 10, count 2 2006.281.08:20:53.31#ibcon#read 3, iclass 10, count 2 2006.281.08:20:53.31#ibcon#about to read 4, iclass 10, count 2 2006.281.08:20:53.31#ibcon#read 4, iclass 10, count 2 2006.281.08:20:53.31#ibcon#about to read 5, iclass 10, count 2 2006.281.08:20:53.31#ibcon#read 5, iclass 10, count 2 2006.281.08:20:53.31#ibcon#about to read 6, iclass 10, count 2 2006.281.08:20:53.31#ibcon#read 6, iclass 10, count 2 2006.281.08:20:53.31#ibcon#end of sib2, iclass 10, count 2 2006.281.08:20:53.31#ibcon#*after write, iclass 10, count 2 2006.281.08:20:53.31#ibcon#*before return 0, iclass 10, count 2 2006.281.08:20:53.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:20:53.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:20:53.31#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:20:53.31#ibcon#ireg 7 cls_cnt 0 2006.281.08:20:53.31#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:20:53.32#abcon#[5=S1D000X0/0*\r\n] 2006.281.08:20:53.43#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:20:53.43#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:20:53.43#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:20:53.43#ibcon#first serial, iclass 10, count 0 2006.281.08:20:53.43#ibcon#enter sib2, iclass 10, count 0 2006.281.08:20:53.43#ibcon#flushed, iclass 10, count 0 2006.281.08:20:53.43#ibcon#about to write, iclass 10, count 0 2006.281.08:20:53.43#ibcon#wrote, iclass 10, count 0 2006.281.08:20:53.43#ibcon#about to read 3, iclass 10, count 0 2006.281.08:20:53.45#ibcon#read 3, iclass 10, count 0 2006.281.08:20:53.45#ibcon#about to read 4, iclass 10, count 0 2006.281.08:20:53.45#ibcon#read 4, iclass 10, count 0 2006.281.08:20:53.45#ibcon#about to read 5, iclass 10, count 0 2006.281.08:20:53.45#ibcon#read 5, iclass 10, count 0 2006.281.08:20:53.45#ibcon#about to read 6, iclass 10, count 0 2006.281.08:20:53.45#ibcon#read 6, iclass 10, count 0 2006.281.08:20:53.45#ibcon#end of sib2, iclass 10, count 0 2006.281.08:20:53.45#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:20:53.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:20:53.45#ibcon#[27=USB\r\n] 2006.281.08:20:53.45#ibcon#*before write, iclass 10, count 0 2006.281.08:20:53.45#ibcon#enter sib2, iclass 10, count 0 2006.281.08:20:53.45#ibcon#flushed, iclass 10, count 0 2006.281.08:20:53.45#ibcon#about to write, iclass 10, count 0 2006.281.08:20:53.45#ibcon#wrote, iclass 10, count 0 2006.281.08:20:53.45#ibcon#about to read 3, iclass 10, count 0 2006.281.08:20:53.49#ibcon#read 3, iclass 10, count 0 2006.281.08:20:53.49#ibcon#about to read 4, iclass 10, count 0 2006.281.08:20:53.49#ibcon#read 4, iclass 10, count 0 2006.281.08:20:53.49#ibcon#about to read 5, iclass 10, count 0 2006.281.08:20:53.49#ibcon#read 5, iclass 10, count 0 2006.281.08:20:53.49#ibcon#about to read 6, iclass 10, count 0 2006.281.08:20:53.49#ibcon#read 6, iclass 10, count 0 2006.281.08:20:53.49#ibcon#end of sib2, iclass 10, count 0 2006.281.08:20:53.49#ibcon#*after write, iclass 10, count 0 2006.281.08:20:53.49#ibcon#*before return 0, iclass 10, count 0 2006.281.08:20:53.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:20:53.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:20:53.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:20:53.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:20:53.49$vc4f8/vabw=wide 2006.281.08:20:53.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.281.08:20:53.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.281.08:20:53.49#ibcon#ireg 8 cls_cnt 0 2006.281.08:20:53.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:53.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:53.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:53.49#ibcon#enter wrdev, iclass 15, count 0 2006.281.08:20:53.49#ibcon#first serial, iclass 15, count 0 2006.281.08:20:53.49#ibcon#enter sib2, iclass 15, count 0 2006.281.08:20:53.49#ibcon#flushed, iclass 15, count 0 2006.281.08:20:53.49#ibcon#about to write, iclass 15, count 0 2006.281.08:20:53.49#ibcon#wrote, iclass 15, count 0 2006.281.08:20:53.49#ibcon#about to read 3, iclass 15, count 0 2006.281.08:20:53.50#ibcon#read 3, iclass 15, count 0 2006.281.08:20:53.50#ibcon#about to read 4, iclass 15, count 0 2006.281.08:20:53.50#ibcon#read 4, iclass 15, count 0 2006.281.08:20:53.50#ibcon#about to read 5, iclass 15, count 0 2006.281.08:20:53.50#ibcon#read 5, iclass 15, count 0 2006.281.08:20:53.50#ibcon#about to read 6, iclass 15, count 0 2006.281.08:20:53.51#ibcon#read 6, iclass 15, count 0 2006.281.08:20:53.51#ibcon#end of sib2, iclass 15, count 0 2006.281.08:20:53.51#ibcon#*mode == 0, iclass 15, count 0 2006.281.08:20:53.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.281.08:20:53.51#ibcon#[25=BW32\r\n] 2006.281.08:20:53.51#ibcon#*before write, iclass 15, count 0 2006.281.08:20:53.51#ibcon#enter sib2, iclass 15, count 0 2006.281.08:20:53.51#ibcon#flushed, iclass 15, count 0 2006.281.08:20:53.51#ibcon#about to write, iclass 15, count 0 2006.281.08:20:53.51#ibcon#wrote, iclass 15, count 0 2006.281.08:20:53.51#ibcon#about to read 3, iclass 15, count 0 2006.281.08:20:53.54#ibcon#read 3, iclass 15, count 0 2006.281.08:20:53.54#ibcon#about to read 4, iclass 15, count 0 2006.281.08:20:53.54#ibcon#read 4, iclass 15, count 0 2006.281.08:20:53.54#ibcon#about to read 5, iclass 15, count 0 2006.281.08:20:53.54#ibcon#read 5, iclass 15, count 0 2006.281.08:20:53.54#ibcon#about to read 6, iclass 15, count 0 2006.281.08:20:53.54#ibcon#read 6, iclass 15, count 0 2006.281.08:20:53.54#ibcon#end of sib2, iclass 15, count 0 2006.281.08:20:53.54#ibcon#*after write, iclass 15, count 0 2006.281.08:20:53.54#ibcon#*before return 0, iclass 15, count 0 2006.281.08:20:53.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:53.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.281.08:20:53.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.281.08:20:53.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.281.08:20:53.54$vc4f8/vbbw=wide 2006.281.08:20:53.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.281.08:20:53.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.281.08:20:53.54#ibcon#ireg 8 cls_cnt 0 2006.281.08:20:53.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:20:53.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:20:53.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:20:53.61#ibcon#enter wrdev, iclass 17, count 0 2006.281.08:20:53.61#ibcon#first serial, iclass 17, count 0 2006.281.08:20:53.61#ibcon#enter sib2, iclass 17, count 0 2006.281.08:20:53.61#ibcon#flushed, iclass 17, count 0 2006.281.08:20:53.61#ibcon#about to write, iclass 17, count 0 2006.281.08:20:53.61#ibcon#wrote, iclass 17, count 0 2006.281.08:20:53.61#ibcon#about to read 3, iclass 17, count 0 2006.281.08:20:53.63#ibcon#read 3, iclass 17, count 0 2006.281.08:20:53.63#ibcon#about to read 4, iclass 17, count 0 2006.281.08:20:53.63#ibcon#read 4, iclass 17, count 0 2006.281.08:20:53.63#ibcon#about to read 5, iclass 17, count 0 2006.281.08:20:53.63#ibcon#read 5, iclass 17, count 0 2006.281.08:20:53.63#ibcon#about to read 6, iclass 17, count 0 2006.281.08:20:53.63#ibcon#read 6, iclass 17, count 0 2006.281.08:20:53.63#ibcon#end of sib2, iclass 17, count 0 2006.281.08:20:53.63#ibcon#*mode == 0, iclass 17, count 0 2006.281.08:20:53.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.281.08:20:53.63#ibcon#[27=BW32\r\n] 2006.281.08:20:53.63#ibcon#*before write, iclass 17, count 0 2006.281.08:20:53.63#ibcon#enter sib2, iclass 17, count 0 2006.281.08:20:53.63#ibcon#flushed, iclass 17, count 0 2006.281.08:20:53.63#ibcon#about to write, iclass 17, count 0 2006.281.08:20:53.63#ibcon#wrote, iclass 17, count 0 2006.281.08:20:53.63#ibcon#about to read 3, iclass 17, count 0 2006.281.08:20:53.66#ibcon#read 3, iclass 17, count 0 2006.281.08:20:53.66#ibcon#about to read 4, iclass 17, count 0 2006.281.08:20:53.66#ibcon#read 4, iclass 17, count 0 2006.281.08:20:53.66#ibcon#about to read 5, iclass 17, count 0 2006.281.08:20:53.66#ibcon#read 5, iclass 17, count 0 2006.281.08:20:53.66#ibcon#about to read 6, iclass 17, count 0 2006.281.08:20:53.66#ibcon#read 6, iclass 17, count 0 2006.281.08:20:53.66#ibcon#end of sib2, iclass 17, count 0 2006.281.08:20:53.66#ibcon#*after write, iclass 17, count 0 2006.281.08:20:53.66#ibcon#*before return 0, iclass 17, count 0 2006.281.08:20:53.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:20:53.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.281.08:20:53.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.281.08:20:53.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.281.08:20:53.66$4f8m12a/ifd4f 2006.281.08:20:53.66$ifd4f/lo= 2006.281.08:20:53.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:20:53.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:20:53.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:20:53.66$ifd4f/patch= 2006.281.08:20:53.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:20:53.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:20:53.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:20:53.66$4f8m12a/"form=m,16.000,1:2 2006.281.08:20:53.66$4f8m12a/"tpicd 2006.281.08:20:53.66$4f8m12a/echo=off 2006.281.08:20:53.66$4f8m12a/xlog=off 2006.281.08:20:53.66:!2006.281.08:23:00 2006.281.08:21:39.14#trakl#Source acquired 2006.281.08:21:41.14#flagr#flagr/antenna,acquired 2006.281.08:23:00.00:preob 2006.281.08:23:00.14/onsource/TRACKING 2006.281.08:23:00.14:!2006.281.08:23:10 2006.281.08:23:10.00:data_valid=on 2006.281.08:23:10.00:midob 2006.281.08:23:11.13/onsource/TRACKING 2006.281.08:23:11.13/wx/19.91,1001.8,52 2006.281.08:23:11.23/cable/+6.4877E-03 2006.281.08:23:12.32/va/01,07,usb,yes,34,36 2006.281.08:23:12.32/va/02,06,usb,yes,32,33 2006.281.08:23:12.32/va/03,06,usb,yes,30,30 2006.281.08:23:12.32/va/04,06,usb,yes,33,35 2006.281.08:23:12.32/va/05,07,usb,yes,32,34 2006.281.08:23:12.32/va/06,06,usb,yes,31,31 2006.281.08:23:12.32/va/07,06,usb,yes,31,31 2006.281.08:23:12.32/va/08,06,usb,yes,33,33 2006.281.08:23:12.55/valo/01,532.99,yes,locked 2006.281.08:23:12.55/valo/02,572.99,yes,locked 2006.281.08:23:12.55/valo/03,672.99,yes,locked 2006.281.08:23:12.55/valo/04,832.99,yes,locked 2006.281.08:23:12.55/valo/05,652.99,yes,locked 2006.281.08:23:12.55/valo/06,772.99,yes,locked 2006.281.08:23:12.55/valo/07,832.99,yes,locked 2006.281.08:23:12.55/valo/08,852.99,yes,locked 2006.281.08:23:13.64/vb/01,04,usb,yes,31,30 2006.281.08:23:13.64/vb/02,05,usb,yes,29,30 2006.281.08:23:13.64/vb/03,04,usb,yes,29,33 2006.281.08:23:13.64/vb/04,04,usb,yes,30,30 2006.281.08:23:13.64/vb/05,04,usb,yes,28,33 2006.281.08:23:13.64/vb/06,04,usb,yes,29,32 2006.281.08:23:13.64/vb/07,04,usb,yes,32,32 2006.281.08:23:13.64/vb/08,04,usb,yes,29,33 2006.281.08:23:13.87/vblo/01,632.99,yes,locked 2006.281.08:23:13.87/vblo/02,640.99,yes,locked 2006.281.08:23:13.87/vblo/03,656.99,yes,locked 2006.281.08:23:13.87/vblo/04,712.99,yes,locked 2006.281.08:23:13.87/vblo/05,744.99,yes,locked 2006.281.08:23:13.87/vblo/06,752.99,yes,locked 2006.281.08:23:13.87/vblo/07,734.99,yes,locked 2006.281.08:23:13.87/vblo/08,744.99,yes,locked 2006.281.08:23:14.02/vabw/8 2006.281.08:23:14.17/vbbw/8 2006.281.08:23:14.31/xfe/off,on,12.0 2006.281.08:23:14.69/ifatt/23,28,28,28 2006.281.08:23:15.08/fmout-gps/S +3.12E-07 2006.281.08:23:15.11:!2006.281.08:24:10 2006.281.08:24:10.01:data_valid=off 2006.281.08:24:10.02:postob 2006.281.08:24:10.23/cable/+6.4885E-03 2006.281.08:24:10.23/wx/19.88,1001.9,52 2006.281.08:24:11.08/fmout-gps/S +3.12E-07 2006.281.08:24:11.08:scan_name=281-0825,k06281,60 2006.281.08:24:11.09:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.281.08:24:11.13#flagr#flagr/antenna,new-source 2006.281.08:24:12.13:checkk5 2006.281.08:24:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.281.08:24:12.95/chk_autoobs//k5ts2/ autoobs is running! 2006.281.08:24:13.36/chk_autoobs//k5ts3/ autoobs is running! 2006.281.08:24:13.77/chk_autoobs//k5ts4/ autoobs is running! 2006.281.08:24:14.18/chk_obsdata//k5ts1/T2810823??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:24:14.78/chk_obsdata//k5ts2/T2810823??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:24:15.20/chk_obsdata//k5ts3/T2810823??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:24:15.66/chk_obsdata//k5ts4/T2810823??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.281.08:24:16.43/k5log//k5ts1_log_newline 2006.281.08:24:17.20/k5log//k5ts2_log_newline 2006.281.08:24:18.48/k5log//k5ts3_log_newline 2006.281.08:24:19.27/k5log//k5ts4_log_newline 2006.281.08:24:19.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:24:19.30:4f8m12a=3 2006.281.08:24:19.30$4f8m12a/echo=on 2006.281.08:24:19.30$4f8m12a/pcalon 2006.281.08:24:19.30$pcalon/"no phase cal control is implemented here 2006.281.08:24:19.30$4f8m12a/"tpicd=stop 2006.281.08:24:19.30$4f8m12a/vc4f8 2006.281.08:24:19.30$vc4f8/valo=1,532.99 2006.281.08:24:19.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:24:19.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:24:19.31#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:19.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:19.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:19.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:19.31#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:24:19.31#ibcon#first serial, iclass 28, count 0 2006.281.08:24:19.31#ibcon#enter sib2, iclass 28, count 0 2006.281.08:24:19.31#ibcon#flushed, iclass 28, count 0 2006.281.08:24:19.31#ibcon#about to write, iclass 28, count 0 2006.281.08:24:19.31#ibcon#wrote, iclass 28, count 0 2006.281.08:24:19.31#ibcon#about to read 3, iclass 28, count 0 2006.281.08:24:19.32#ibcon#read 3, iclass 28, count 0 2006.281.08:24:19.32#ibcon#about to read 4, iclass 28, count 0 2006.281.08:24:19.32#ibcon#read 4, iclass 28, count 0 2006.281.08:24:19.32#ibcon#about to read 5, iclass 28, count 0 2006.281.08:24:19.32#ibcon#read 5, iclass 28, count 0 2006.281.08:24:19.32#ibcon#about to read 6, iclass 28, count 0 2006.281.08:24:19.32#ibcon#read 6, iclass 28, count 0 2006.281.08:24:19.32#ibcon#end of sib2, iclass 28, count 0 2006.281.08:24:19.32#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:24:19.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:24:19.32#ibcon#[26=FRQ=01,532.99\r\n] 2006.281.08:24:19.32#ibcon#*before write, iclass 28, count 0 2006.281.08:24:19.32#ibcon#enter sib2, iclass 28, count 0 2006.281.08:24:19.32#ibcon#flushed, iclass 28, count 0 2006.281.08:24:19.32#ibcon#about to write, iclass 28, count 0 2006.281.08:24:19.32#ibcon#wrote, iclass 28, count 0 2006.281.08:24:19.32#ibcon#about to read 3, iclass 28, count 0 2006.281.08:24:19.37#ibcon#read 3, iclass 28, count 0 2006.281.08:24:19.37#ibcon#about to read 4, iclass 28, count 0 2006.281.08:24:19.37#ibcon#read 4, iclass 28, count 0 2006.281.08:24:19.37#ibcon#about to read 5, iclass 28, count 0 2006.281.08:24:19.37#ibcon#read 5, iclass 28, count 0 2006.281.08:24:19.37#ibcon#about to read 6, iclass 28, count 0 2006.281.08:24:19.37#ibcon#read 6, iclass 28, count 0 2006.281.08:24:19.37#ibcon#end of sib2, iclass 28, count 0 2006.281.08:24:19.37#ibcon#*after write, iclass 28, count 0 2006.281.08:24:19.37#ibcon#*before return 0, iclass 28, count 0 2006.281.08:24:19.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:19.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:19.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:24:19.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:24:19.37$vc4f8/va=1,7 2006.281.08:24:19.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.08:24:19.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.08:24:19.37#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:19.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:19.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:19.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:19.37#ibcon#enter wrdev, iclass 30, count 2 2006.281.08:24:19.37#ibcon#first serial, iclass 30, count 2 2006.281.08:24:19.37#ibcon#enter sib2, iclass 30, count 2 2006.281.08:24:19.37#ibcon#flushed, iclass 30, count 2 2006.281.08:24:19.37#ibcon#about to write, iclass 30, count 2 2006.281.08:24:19.37#ibcon#wrote, iclass 30, count 2 2006.281.08:24:19.37#ibcon#about to read 3, iclass 30, count 2 2006.281.08:24:19.39#ibcon#read 3, iclass 30, count 2 2006.281.08:24:19.39#ibcon#about to read 4, iclass 30, count 2 2006.281.08:24:19.39#ibcon#read 4, iclass 30, count 2 2006.281.08:24:19.39#ibcon#about to read 5, iclass 30, count 2 2006.281.08:24:19.39#ibcon#read 5, iclass 30, count 2 2006.281.08:24:19.39#ibcon#about to read 6, iclass 30, count 2 2006.281.08:24:19.39#ibcon#read 6, iclass 30, count 2 2006.281.08:24:19.39#ibcon#end of sib2, iclass 30, count 2 2006.281.08:24:19.39#ibcon#*mode == 0, iclass 30, count 2 2006.281.08:24:19.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.08:24:19.39#ibcon#[25=AT01-07\r\n] 2006.281.08:24:19.39#ibcon#*before write, iclass 30, count 2 2006.281.08:24:19.39#ibcon#enter sib2, iclass 30, count 2 2006.281.08:24:19.39#ibcon#flushed, iclass 30, count 2 2006.281.08:24:19.39#ibcon#about to write, iclass 30, count 2 2006.281.08:24:19.39#ibcon#wrote, iclass 30, count 2 2006.281.08:24:19.39#ibcon#about to read 3, iclass 30, count 2 2006.281.08:24:19.42#ibcon#read 3, iclass 30, count 2 2006.281.08:24:19.42#ibcon#about to read 4, iclass 30, count 2 2006.281.08:24:19.42#ibcon#read 4, iclass 30, count 2 2006.281.08:24:19.42#ibcon#about to read 5, iclass 30, count 2 2006.281.08:24:19.42#ibcon#read 5, iclass 30, count 2 2006.281.08:24:19.42#ibcon#about to read 6, iclass 30, count 2 2006.281.08:24:19.42#ibcon#read 6, iclass 30, count 2 2006.281.08:24:19.42#ibcon#end of sib2, iclass 30, count 2 2006.281.08:24:19.42#ibcon#*after write, iclass 30, count 2 2006.281.08:24:19.42#ibcon#*before return 0, iclass 30, count 2 2006.281.08:24:19.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:19.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:19.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.08:24:19.42#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:19.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:19.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:19.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:19.54#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:24:19.54#ibcon#first serial, iclass 30, count 0 2006.281.08:24:19.54#ibcon#enter sib2, iclass 30, count 0 2006.281.08:24:19.54#ibcon#flushed, iclass 30, count 0 2006.281.08:24:19.54#ibcon#about to write, iclass 30, count 0 2006.281.08:24:19.54#ibcon#wrote, iclass 30, count 0 2006.281.08:24:19.54#ibcon#about to read 3, iclass 30, count 0 2006.281.08:24:19.56#ibcon#read 3, iclass 30, count 0 2006.281.08:24:19.56#ibcon#about to read 4, iclass 30, count 0 2006.281.08:24:19.56#ibcon#read 4, iclass 30, count 0 2006.281.08:24:19.56#ibcon#about to read 5, iclass 30, count 0 2006.281.08:24:19.56#ibcon#read 5, iclass 30, count 0 2006.281.08:24:19.56#ibcon#about to read 6, iclass 30, count 0 2006.281.08:24:19.56#ibcon#read 6, iclass 30, count 0 2006.281.08:24:19.56#ibcon#end of sib2, iclass 30, count 0 2006.281.08:24:19.56#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:24:19.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:24:19.56#ibcon#[25=USB\r\n] 2006.281.08:24:19.56#ibcon#*before write, iclass 30, count 0 2006.281.08:24:19.56#ibcon#enter sib2, iclass 30, count 0 2006.281.08:24:19.56#ibcon#flushed, iclass 30, count 0 2006.281.08:24:19.56#ibcon#about to write, iclass 30, count 0 2006.281.08:24:19.56#ibcon#wrote, iclass 30, count 0 2006.281.08:24:19.56#ibcon#about to read 3, iclass 30, count 0 2006.281.08:24:19.59#ibcon#read 3, iclass 30, count 0 2006.281.08:24:19.59#ibcon#about to read 4, iclass 30, count 0 2006.281.08:24:19.59#ibcon#read 4, iclass 30, count 0 2006.281.08:24:19.59#ibcon#about to read 5, iclass 30, count 0 2006.281.08:24:19.59#ibcon#read 5, iclass 30, count 0 2006.281.08:24:19.59#ibcon#about to read 6, iclass 30, count 0 2006.281.08:24:19.59#ibcon#read 6, iclass 30, count 0 2006.281.08:24:19.59#ibcon#end of sib2, iclass 30, count 0 2006.281.08:24:19.59#ibcon#*after write, iclass 30, count 0 2006.281.08:24:19.59#ibcon#*before return 0, iclass 30, count 0 2006.281.08:24:19.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:19.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:19.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:24:19.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:24:19.59$vc4f8/valo=2,572.99 2006.281.08:24:19.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.08:24:19.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.08:24:19.59#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:19.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:19.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:19.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:19.59#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:24:19.59#ibcon#first serial, iclass 32, count 0 2006.281.08:24:19.59#ibcon#enter sib2, iclass 32, count 0 2006.281.08:24:19.59#ibcon#flushed, iclass 32, count 0 2006.281.08:24:19.59#ibcon#about to write, iclass 32, count 0 2006.281.08:24:19.59#ibcon#wrote, iclass 32, count 0 2006.281.08:24:19.59#ibcon#about to read 3, iclass 32, count 0 2006.281.08:24:19.61#ibcon#read 3, iclass 32, count 0 2006.281.08:24:19.61#ibcon#about to read 4, iclass 32, count 0 2006.281.08:24:19.61#ibcon#read 4, iclass 32, count 0 2006.281.08:24:19.61#ibcon#about to read 5, iclass 32, count 0 2006.281.08:24:19.61#ibcon#read 5, iclass 32, count 0 2006.281.08:24:19.61#ibcon#about to read 6, iclass 32, count 0 2006.281.08:24:19.61#ibcon#read 6, iclass 32, count 0 2006.281.08:24:19.61#ibcon#end of sib2, iclass 32, count 0 2006.281.08:24:19.61#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:24:19.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:24:19.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.281.08:24:19.61#ibcon#*before write, iclass 32, count 0 2006.281.08:24:19.61#ibcon#enter sib2, iclass 32, count 0 2006.281.08:24:19.61#ibcon#flushed, iclass 32, count 0 2006.281.08:24:19.61#ibcon#about to write, iclass 32, count 0 2006.281.08:24:19.61#ibcon#wrote, iclass 32, count 0 2006.281.08:24:19.61#ibcon#about to read 3, iclass 32, count 0 2006.281.08:24:19.65#ibcon#read 3, iclass 32, count 0 2006.281.08:24:19.65#ibcon#about to read 4, iclass 32, count 0 2006.281.08:24:19.65#ibcon#read 4, iclass 32, count 0 2006.281.08:24:19.65#ibcon#about to read 5, iclass 32, count 0 2006.281.08:24:19.65#ibcon#read 5, iclass 32, count 0 2006.281.08:24:19.65#ibcon#about to read 6, iclass 32, count 0 2006.281.08:24:19.65#ibcon#read 6, iclass 32, count 0 2006.281.08:24:19.65#ibcon#end of sib2, iclass 32, count 0 2006.281.08:24:19.65#ibcon#*after write, iclass 32, count 0 2006.281.08:24:19.65#ibcon#*before return 0, iclass 32, count 0 2006.281.08:24:19.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:19.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:19.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:24:19.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:24:19.65$vc4f8/va=2,6 2006.281.08:24:19.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.08:24:19.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.08:24:19.66#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:19.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:19.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:19.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:19.70#ibcon#enter wrdev, iclass 34, count 2 2006.281.08:24:19.70#ibcon#first serial, iclass 34, count 2 2006.281.08:24:19.70#ibcon#enter sib2, iclass 34, count 2 2006.281.08:24:19.70#ibcon#flushed, iclass 34, count 2 2006.281.08:24:19.70#ibcon#about to write, iclass 34, count 2 2006.281.08:24:19.70#ibcon#wrote, iclass 34, count 2 2006.281.08:24:19.70#ibcon#about to read 3, iclass 34, count 2 2006.281.08:24:19.72#ibcon#read 3, iclass 34, count 2 2006.281.08:24:19.72#ibcon#about to read 4, iclass 34, count 2 2006.281.08:24:19.72#ibcon#read 4, iclass 34, count 2 2006.281.08:24:19.72#ibcon#about to read 5, iclass 34, count 2 2006.281.08:24:19.72#ibcon#read 5, iclass 34, count 2 2006.281.08:24:19.72#ibcon#about to read 6, iclass 34, count 2 2006.281.08:24:19.72#ibcon#read 6, iclass 34, count 2 2006.281.08:24:19.72#ibcon#end of sib2, iclass 34, count 2 2006.281.08:24:19.72#ibcon#*mode == 0, iclass 34, count 2 2006.281.08:24:19.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.08:24:19.72#ibcon#[25=AT02-06\r\n] 2006.281.08:24:19.72#ibcon#*before write, iclass 34, count 2 2006.281.08:24:19.72#ibcon#enter sib2, iclass 34, count 2 2006.281.08:24:19.72#ibcon#flushed, iclass 34, count 2 2006.281.08:24:19.72#ibcon#about to write, iclass 34, count 2 2006.281.08:24:19.72#ibcon#wrote, iclass 34, count 2 2006.281.08:24:19.72#ibcon#about to read 3, iclass 34, count 2 2006.281.08:24:19.75#ibcon#read 3, iclass 34, count 2 2006.281.08:24:19.75#ibcon#about to read 4, iclass 34, count 2 2006.281.08:24:19.75#ibcon#read 4, iclass 34, count 2 2006.281.08:24:19.75#ibcon#about to read 5, iclass 34, count 2 2006.281.08:24:19.75#ibcon#read 5, iclass 34, count 2 2006.281.08:24:19.75#ibcon#about to read 6, iclass 34, count 2 2006.281.08:24:19.75#ibcon#read 6, iclass 34, count 2 2006.281.08:24:19.75#ibcon#end of sib2, iclass 34, count 2 2006.281.08:24:19.75#ibcon#*after write, iclass 34, count 2 2006.281.08:24:19.75#ibcon#*before return 0, iclass 34, count 2 2006.281.08:24:19.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:19.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:19.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.08:24:19.75#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:19.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:19.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:19.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:19.87#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:24:19.87#ibcon#first serial, iclass 34, count 0 2006.281.08:24:19.87#ibcon#enter sib2, iclass 34, count 0 2006.281.08:24:19.87#ibcon#flushed, iclass 34, count 0 2006.281.08:24:19.87#ibcon#about to write, iclass 34, count 0 2006.281.08:24:19.87#ibcon#wrote, iclass 34, count 0 2006.281.08:24:19.87#ibcon#about to read 3, iclass 34, count 0 2006.281.08:24:19.89#ibcon#read 3, iclass 34, count 0 2006.281.08:24:19.89#ibcon#about to read 4, iclass 34, count 0 2006.281.08:24:19.89#ibcon#read 4, iclass 34, count 0 2006.281.08:24:19.89#ibcon#about to read 5, iclass 34, count 0 2006.281.08:24:19.89#ibcon#read 5, iclass 34, count 0 2006.281.08:24:19.89#ibcon#about to read 6, iclass 34, count 0 2006.281.08:24:19.89#ibcon#read 6, iclass 34, count 0 2006.281.08:24:19.89#ibcon#end of sib2, iclass 34, count 0 2006.281.08:24:19.89#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:24:19.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:24:19.89#ibcon#[25=USB\r\n] 2006.281.08:24:19.89#ibcon#*before write, iclass 34, count 0 2006.281.08:24:19.89#ibcon#enter sib2, iclass 34, count 0 2006.281.08:24:19.89#ibcon#flushed, iclass 34, count 0 2006.281.08:24:19.89#ibcon#about to write, iclass 34, count 0 2006.281.08:24:19.89#ibcon#wrote, iclass 34, count 0 2006.281.08:24:19.89#ibcon#about to read 3, iclass 34, count 0 2006.281.08:24:19.92#ibcon#read 3, iclass 34, count 0 2006.281.08:24:19.92#ibcon#about to read 4, iclass 34, count 0 2006.281.08:24:19.92#ibcon#read 4, iclass 34, count 0 2006.281.08:24:19.92#ibcon#about to read 5, iclass 34, count 0 2006.281.08:24:19.92#ibcon#read 5, iclass 34, count 0 2006.281.08:24:19.92#ibcon#about to read 6, iclass 34, count 0 2006.281.08:24:19.92#ibcon#read 6, iclass 34, count 0 2006.281.08:24:19.92#ibcon#end of sib2, iclass 34, count 0 2006.281.08:24:19.92#ibcon#*after write, iclass 34, count 0 2006.281.08:24:19.92#ibcon#*before return 0, iclass 34, count 0 2006.281.08:24:19.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:19.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:19.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:24:19.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:24:19.92$vc4f8/valo=3,672.99 2006.281.08:24:19.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.08:24:19.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.08:24:19.92#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:19.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:19.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:19.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:19.92#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:24:19.92#ibcon#first serial, iclass 36, count 0 2006.281.08:24:19.92#ibcon#enter sib2, iclass 36, count 0 2006.281.08:24:19.92#ibcon#flushed, iclass 36, count 0 2006.281.08:24:19.92#ibcon#about to write, iclass 36, count 0 2006.281.08:24:19.92#ibcon#wrote, iclass 36, count 0 2006.281.08:24:19.92#ibcon#about to read 3, iclass 36, count 0 2006.281.08:24:19.94#ibcon#read 3, iclass 36, count 0 2006.281.08:24:19.94#ibcon#about to read 4, iclass 36, count 0 2006.281.08:24:19.94#ibcon#read 4, iclass 36, count 0 2006.281.08:24:19.94#ibcon#about to read 5, iclass 36, count 0 2006.281.08:24:19.94#ibcon#read 5, iclass 36, count 0 2006.281.08:24:19.94#ibcon#about to read 6, iclass 36, count 0 2006.281.08:24:19.94#ibcon#read 6, iclass 36, count 0 2006.281.08:24:19.94#ibcon#end of sib2, iclass 36, count 0 2006.281.08:24:19.94#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:24:19.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:24:19.94#ibcon#[26=FRQ=03,672.99\r\n] 2006.281.08:24:19.94#ibcon#*before write, iclass 36, count 0 2006.281.08:24:19.94#ibcon#enter sib2, iclass 36, count 0 2006.281.08:24:19.94#ibcon#flushed, iclass 36, count 0 2006.281.08:24:19.94#ibcon#about to write, iclass 36, count 0 2006.281.08:24:19.94#ibcon#wrote, iclass 36, count 0 2006.281.08:24:19.94#ibcon#about to read 3, iclass 36, count 0 2006.281.08:24:19.99#ibcon#read 3, iclass 36, count 0 2006.281.08:24:19.99#ibcon#about to read 4, iclass 36, count 0 2006.281.08:24:19.99#ibcon#read 4, iclass 36, count 0 2006.281.08:24:19.99#ibcon#about to read 5, iclass 36, count 0 2006.281.08:24:19.99#ibcon#read 5, iclass 36, count 0 2006.281.08:24:19.99#ibcon#about to read 6, iclass 36, count 0 2006.281.08:24:19.99#ibcon#read 6, iclass 36, count 0 2006.281.08:24:19.99#ibcon#end of sib2, iclass 36, count 0 2006.281.08:24:19.99#ibcon#*after write, iclass 36, count 0 2006.281.08:24:19.99#ibcon#*before return 0, iclass 36, count 0 2006.281.08:24:19.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:19.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:19.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:24:19.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:24:19.99$vc4f8/va=3,6 2006.281.08:24:19.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.08:24:19.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.08:24:19.99#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:19.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:20.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:20.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:20.04#ibcon#enter wrdev, iclass 38, count 2 2006.281.08:24:20.04#ibcon#first serial, iclass 38, count 2 2006.281.08:24:20.04#ibcon#enter sib2, iclass 38, count 2 2006.281.08:24:20.04#ibcon#flushed, iclass 38, count 2 2006.281.08:24:20.04#ibcon#about to write, iclass 38, count 2 2006.281.08:24:20.04#ibcon#wrote, iclass 38, count 2 2006.281.08:24:20.04#ibcon#about to read 3, iclass 38, count 2 2006.281.08:24:20.06#ibcon#read 3, iclass 38, count 2 2006.281.08:24:20.06#ibcon#about to read 4, iclass 38, count 2 2006.281.08:24:20.06#ibcon#read 4, iclass 38, count 2 2006.281.08:24:20.06#ibcon#about to read 5, iclass 38, count 2 2006.281.08:24:20.06#ibcon#read 5, iclass 38, count 2 2006.281.08:24:20.06#ibcon#about to read 6, iclass 38, count 2 2006.281.08:24:20.06#ibcon#read 6, iclass 38, count 2 2006.281.08:24:20.06#ibcon#end of sib2, iclass 38, count 2 2006.281.08:24:20.06#ibcon#*mode == 0, iclass 38, count 2 2006.281.08:24:20.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.08:24:20.06#ibcon#[25=AT03-06\r\n] 2006.281.08:24:20.06#ibcon#*before write, iclass 38, count 2 2006.281.08:24:20.06#ibcon#enter sib2, iclass 38, count 2 2006.281.08:24:20.06#ibcon#flushed, iclass 38, count 2 2006.281.08:24:20.06#ibcon#about to write, iclass 38, count 2 2006.281.08:24:20.06#ibcon#wrote, iclass 38, count 2 2006.281.08:24:20.06#ibcon#about to read 3, iclass 38, count 2 2006.281.08:24:20.09#ibcon#read 3, iclass 38, count 2 2006.281.08:24:20.09#ibcon#about to read 4, iclass 38, count 2 2006.281.08:24:20.09#ibcon#read 4, iclass 38, count 2 2006.281.08:24:20.09#ibcon#about to read 5, iclass 38, count 2 2006.281.08:24:20.09#ibcon#read 5, iclass 38, count 2 2006.281.08:24:20.09#ibcon#about to read 6, iclass 38, count 2 2006.281.08:24:20.09#ibcon#read 6, iclass 38, count 2 2006.281.08:24:20.09#ibcon#end of sib2, iclass 38, count 2 2006.281.08:24:20.09#ibcon#*after write, iclass 38, count 2 2006.281.08:24:20.09#ibcon#*before return 0, iclass 38, count 2 2006.281.08:24:20.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:20.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:20.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.08:24:20.09#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:20.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:20.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:20.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:20.21#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:24:20.21#ibcon#first serial, iclass 38, count 0 2006.281.08:24:20.21#ibcon#enter sib2, iclass 38, count 0 2006.281.08:24:20.21#ibcon#flushed, iclass 38, count 0 2006.281.08:24:20.21#ibcon#about to write, iclass 38, count 0 2006.281.08:24:20.21#ibcon#wrote, iclass 38, count 0 2006.281.08:24:20.21#ibcon#about to read 3, iclass 38, count 0 2006.281.08:24:20.23#ibcon#read 3, iclass 38, count 0 2006.281.08:24:20.23#ibcon#about to read 4, iclass 38, count 0 2006.281.08:24:20.23#ibcon#read 4, iclass 38, count 0 2006.281.08:24:20.23#ibcon#about to read 5, iclass 38, count 0 2006.281.08:24:20.23#ibcon#read 5, iclass 38, count 0 2006.281.08:24:20.23#ibcon#about to read 6, iclass 38, count 0 2006.281.08:24:20.23#ibcon#read 6, iclass 38, count 0 2006.281.08:24:20.23#ibcon#end of sib2, iclass 38, count 0 2006.281.08:24:20.23#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:24:20.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:24:20.23#ibcon#[25=USB\r\n] 2006.281.08:24:20.23#ibcon#*before write, iclass 38, count 0 2006.281.08:24:20.23#ibcon#enter sib2, iclass 38, count 0 2006.281.08:24:20.23#ibcon#flushed, iclass 38, count 0 2006.281.08:24:20.23#ibcon#about to write, iclass 38, count 0 2006.281.08:24:20.23#ibcon#wrote, iclass 38, count 0 2006.281.08:24:20.23#ibcon#about to read 3, iclass 38, count 0 2006.281.08:24:20.26#ibcon#read 3, iclass 38, count 0 2006.281.08:24:20.26#ibcon#about to read 4, iclass 38, count 0 2006.281.08:24:20.26#ibcon#read 4, iclass 38, count 0 2006.281.08:24:20.26#ibcon#about to read 5, iclass 38, count 0 2006.281.08:24:20.26#ibcon#read 5, iclass 38, count 0 2006.281.08:24:20.26#ibcon#about to read 6, iclass 38, count 0 2006.281.08:24:20.26#ibcon#read 6, iclass 38, count 0 2006.281.08:24:20.26#ibcon#end of sib2, iclass 38, count 0 2006.281.08:24:20.26#ibcon#*after write, iclass 38, count 0 2006.281.08:24:20.26#ibcon#*before return 0, iclass 38, count 0 2006.281.08:24:20.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:20.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:20.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:24:20.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:24:20.26$vc4f8/valo=4,832.99 2006.281.08:24:20.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:24:20.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:24:20.26#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:20.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:20.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:20.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:20.26#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:24:20.26#ibcon#first serial, iclass 40, count 0 2006.281.08:24:20.26#ibcon#enter sib2, iclass 40, count 0 2006.281.08:24:20.26#ibcon#flushed, iclass 40, count 0 2006.281.08:24:20.26#ibcon#about to write, iclass 40, count 0 2006.281.08:24:20.26#ibcon#wrote, iclass 40, count 0 2006.281.08:24:20.26#ibcon#about to read 3, iclass 40, count 0 2006.281.08:24:20.28#ibcon#read 3, iclass 40, count 0 2006.281.08:24:20.29#ibcon#about to read 4, iclass 40, count 0 2006.281.08:24:20.29#ibcon#read 4, iclass 40, count 0 2006.281.08:24:20.29#ibcon#about to read 5, iclass 40, count 0 2006.281.08:24:20.29#ibcon#read 5, iclass 40, count 0 2006.281.08:24:20.29#ibcon#about to read 6, iclass 40, count 0 2006.281.08:24:20.29#ibcon#read 6, iclass 40, count 0 2006.281.08:24:20.29#ibcon#end of sib2, iclass 40, count 0 2006.281.08:24:20.29#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:24:20.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:24:20.29#ibcon#[26=FRQ=04,832.99\r\n] 2006.281.08:24:20.29#ibcon#*before write, iclass 40, count 0 2006.281.08:24:20.29#ibcon#enter sib2, iclass 40, count 0 2006.281.08:24:20.29#ibcon#flushed, iclass 40, count 0 2006.281.08:24:20.29#ibcon#about to write, iclass 40, count 0 2006.281.08:24:20.29#ibcon#wrote, iclass 40, count 0 2006.281.08:24:20.29#ibcon#about to read 3, iclass 40, count 0 2006.281.08:24:20.33#ibcon#read 3, iclass 40, count 0 2006.281.08:24:20.33#ibcon#about to read 4, iclass 40, count 0 2006.281.08:24:20.33#ibcon#read 4, iclass 40, count 0 2006.281.08:24:20.33#ibcon#about to read 5, iclass 40, count 0 2006.281.08:24:20.33#ibcon#read 5, iclass 40, count 0 2006.281.08:24:20.33#ibcon#about to read 6, iclass 40, count 0 2006.281.08:24:20.33#ibcon#read 6, iclass 40, count 0 2006.281.08:24:20.33#ibcon#end of sib2, iclass 40, count 0 2006.281.08:24:20.33#ibcon#*after write, iclass 40, count 0 2006.281.08:24:20.33#ibcon#*before return 0, iclass 40, count 0 2006.281.08:24:20.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:20.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:20.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:24:20.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:24:20.33$vc4f8/va=4,6 2006.281.08:24:20.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.08:24:20.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.08:24:20.33#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:20.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:20.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:20.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:20.38#ibcon#enter wrdev, iclass 4, count 2 2006.281.08:24:20.38#ibcon#first serial, iclass 4, count 2 2006.281.08:24:20.38#ibcon#enter sib2, iclass 4, count 2 2006.281.08:24:20.38#ibcon#flushed, iclass 4, count 2 2006.281.08:24:20.38#ibcon#about to write, iclass 4, count 2 2006.281.08:24:20.38#ibcon#wrote, iclass 4, count 2 2006.281.08:24:20.38#ibcon#about to read 3, iclass 4, count 2 2006.281.08:24:20.40#ibcon#read 3, iclass 4, count 2 2006.281.08:24:20.40#ibcon#about to read 4, iclass 4, count 2 2006.281.08:24:20.40#ibcon#read 4, iclass 4, count 2 2006.281.08:24:20.40#ibcon#about to read 5, iclass 4, count 2 2006.281.08:24:20.40#ibcon#read 5, iclass 4, count 2 2006.281.08:24:20.40#ibcon#about to read 6, iclass 4, count 2 2006.281.08:24:20.40#ibcon#read 6, iclass 4, count 2 2006.281.08:24:20.40#ibcon#end of sib2, iclass 4, count 2 2006.281.08:24:20.40#ibcon#*mode == 0, iclass 4, count 2 2006.281.08:24:20.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.08:24:20.40#ibcon#[25=AT04-06\r\n] 2006.281.08:24:20.40#ibcon#*before write, iclass 4, count 2 2006.281.08:24:20.40#ibcon#enter sib2, iclass 4, count 2 2006.281.08:24:20.40#ibcon#flushed, iclass 4, count 2 2006.281.08:24:20.40#ibcon#about to write, iclass 4, count 2 2006.281.08:24:20.40#ibcon#wrote, iclass 4, count 2 2006.281.08:24:20.40#ibcon#about to read 3, iclass 4, count 2 2006.281.08:24:20.43#ibcon#read 3, iclass 4, count 2 2006.281.08:24:20.43#ibcon#about to read 4, iclass 4, count 2 2006.281.08:24:20.43#ibcon#read 4, iclass 4, count 2 2006.281.08:24:20.43#ibcon#about to read 5, iclass 4, count 2 2006.281.08:24:20.43#ibcon#read 5, iclass 4, count 2 2006.281.08:24:20.43#ibcon#about to read 6, iclass 4, count 2 2006.281.08:24:20.43#ibcon#read 6, iclass 4, count 2 2006.281.08:24:20.43#ibcon#end of sib2, iclass 4, count 2 2006.281.08:24:20.43#ibcon#*after write, iclass 4, count 2 2006.281.08:24:20.43#ibcon#*before return 0, iclass 4, count 2 2006.281.08:24:20.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:20.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:20.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.08:24:20.43#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:20.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:20.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:20.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:20.55#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:24:20.55#ibcon#first serial, iclass 4, count 0 2006.281.08:24:20.55#ibcon#enter sib2, iclass 4, count 0 2006.281.08:24:20.55#ibcon#flushed, iclass 4, count 0 2006.281.08:24:20.55#ibcon#about to write, iclass 4, count 0 2006.281.08:24:20.55#ibcon#wrote, iclass 4, count 0 2006.281.08:24:20.55#ibcon#about to read 3, iclass 4, count 0 2006.281.08:24:20.57#ibcon#read 3, iclass 4, count 0 2006.281.08:24:20.57#ibcon#about to read 4, iclass 4, count 0 2006.281.08:24:20.57#ibcon#read 4, iclass 4, count 0 2006.281.08:24:20.57#ibcon#about to read 5, iclass 4, count 0 2006.281.08:24:20.57#ibcon#read 5, iclass 4, count 0 2006.281.08:24:20.57#ibcon#about to read 6, iclass 4, count 0 2006.281.08:24:20.57#ibcon#read 6, iclass 4, count 0 2006.281.08:24:20.57#ibcon#end of sib2, iclass 4, count 0 2006.281.08:24:20.57#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:24:20.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:24:20.57#ibcon#[25=USB\r\n] 2006.281.08:24:20.57#ibcon#*before write, iclass 4, count 0 2006.281.08:24:20.57#ibcon#enter sib2, iclass 4, count 0 2006.281.08:24:20.57#ibcon#flushed, iclass 4, count 0 2006.281.08:24:20.57#ibcon#about to write, iclass 4, count 0 2006.281.08:24:20.57#ibcon#wrote, iclass 4, count 0 2006.281.08:24:20.57#ibcon#about to read 3, iclass 4, count 0 2006.281.08:24:20.60#ibcon#read 3, iclass 4, count 0 2006.281.08:24:20.60#ibcon#about to read 4, iclass 4, count 0 2006.281.08:24:20.60#ibcon#read 4, iclass 4, count 0 2006.281.08:24:20.60#ibcon#about to read 5, iclass 4, count 0 2006.281.08:24:20.60#ibcon#read 5, iclass 4, count 0 2006.281.08:24:20.60#ibcon#about to read 6, iclass 4, count 0 2006.281.08:24:20.60#ibcon#read 6, iclass 4, count 0 2006.281.08:24:20.60#ibcon#end of sib2, iclass 4, count 0 2006.281.08:24:20.60#ibcon#*after write, iclass 4, count 0 2006.281.08:24:20.60#ibcon#*before return 0, iclass 4, count 0 2006.281.08:24:20.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:20.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:20.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:24:20.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:24:20.60$vc4f8/valo=5,652.99 2006.281.08:24:20.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:24:20.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:24:20.60#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:20.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:20.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:20.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:20.60#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:24:20.60#ibcon#first serial, iclass 6, count 0 2006.281.08:24:20.60#ibcon#enter sib2, iclass 6, count 0 2006.281.08:24:20.60#ibcon#flushed, iclass 6, count 0 2006.281.08:24:20.60#ibcon#about to write, iclass 6, count 0 2006.281.08:24:20.60#ibcon#wrote, iclass 6, count 0 2006.281.08:24:20.60#ibcon#about to read 3, iclass 6, count 0 2006.281.08:24:20.62#ibcon#read 3, iclass 6, count 0 2006.281.08:24:20.62#ibcon#about to read 4, iclass 6, count 0 2006.281.08:24:20.62#ibcon#read 4, iclass 6, count 0 2006.281.08:24:20.62#ibcon#about to read 5, iclass 6, count 0 2006.281.08:24:20.62#ibcon#read 5, iclass 6, count 0 2006.281.08:24:20.62#ibcon#about to read 6, iclass 6, count 0 2006.281.08:24:20.62#ibcon#read 6, iclass 6, count 0 2006.281.08:24:20.62#ibcon#end of sib2, iclass 6, count 0 2006.281.08:24:20.62#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:24:20.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:24:20.62#ibcon#[26=FRQ=05,652.99\r\n] 2006.281.08:24:20.62#ibcon#*before write, iclass 6, count 0 2006.281.08:24:20.62#ibcon#enter sib2, iclass 6, count 0 2006.281.08:24:20.62#ibcon#flushed, iclass 6, count 0 2006.281.08:24:20.62#ibcon#about to write, iclass 6, count 0 2006.281.08:24:20.62#ibcon#wrote, iclass 6, count 0 2006.281.08:24:20.62#ibcon#about to read 3, iclass 6, count 0 2006.281.08:24:20.66#ibcon#read 3, iclass 6, count 0 2006.281.08:24:20.66#ibcon#about to read 4, iclass 6, count 0 2006.281.08:24:20.66#ibcon#read 4, iclass 6, count 0 2006.281.08:24:20.66#ibcon#about to read 5, iclass 6, count 0 2006.281.08:24:20.66#ibcon#read 5, iclass 6, count 0 2006.281.08:24:20.66#ibcon#about to read 6, iclass 6, count 0 2006.281.08:24:20.66#ibcon#read 6, iclass 6, count 0 2006.281.08:24:20.66#ibcon#end of sib2, iclass 6, count 0 2006.281.08:24:20.66#ibcon#*after write, iclass 6, count 0 2006.281.08:24:20.66#ibcon#*before return 0, iclass 6, count 0 2006.281.08:24:20.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:20.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:20.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:24:20.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:24:20.66$vc4f8/va=5,7 2006.281.08:24:20.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:24:20.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:24:20.66#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:20.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:20.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:20.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:20.72#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:24:20.72#ibcon#first serial, iclass 10, count 2 2006.281.08:24:20.72#ibcon#enter sib2, iclass 10, count 2 2006.281.08:24:20.72#ibcon#flushed, iclass 10, count 2 2006.281.08:24:20.72#ibcon#about to write, iclass 10, count 2 2006.281.08:24:20.72#ibcon#wrote, iclass 10, count 2 2006.281.08:24:20.72#ibcon#about to read 3, iclass 10, count 2 2006.281.08:24:20.74#ibcon#read 3, iclass 10, count 2 2006.281.08:24:20.74#ibcon#about to read 4, iclass 10, count 2 2006.281.08:24:20.74#ibcon#read 4, iclass 10, count 2 2006.281.08:24:20.74#ibcon#about to read 5, iclass 10, count 2 2006.281.08:24:20.74#ibcon#read 5, iclass 10, count 2 2006.281.08:24:20.74#ibcon#about to read 6, iclass 10, count 2 2006.281.08:24:20.74#ibcon#read 6, iclass 10, count 2 2006.281.08:24:20.74#ibcon#end of sib2, iclass 10, count 2 2006.281.08:24:20.74#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:24:20.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:24:20.74#ibcon#[25=AT05-07\r\n] 2006.281.08:24:20.74#ibcon#*before write, iclass 10, count 2 2006.281.08:24:20.74#ibcon#enter sib2, iclass 10, count 2 2006.281.08:24:20.74#ibcon#flushed, iclass 10, count 2 2006.281.08:24:20.74#ibcon#about to write, iclass 10, count 2 2006.281.08:24:20.74#ibcon#wrote, iclass 10, count 2 2006.281.08:24:20.74#ibcon#about to read 3, iclass 10, count 2 2006.281.08:24:20.77#ibcon#read 3, iclass 10, count 2 2006.281.08:24:20.77#ibcon#about to read 4, iclass 10, count 2 2006.281.08:24:20.77#ibcon#read 4, iclass 10, count 2 2006.281.08:24:20.77#ibcon#about to read 5, iclass 10, count 2 2006.281.08:24:20.77#ibcon#read 5, iclass 10, count 2 2006.281.08:24:20.77#ibcon#about to read 6, iclass 10, count 2 2006.281.08:24:20.77#ibcon#read 6, iclass 10, count 2 2006.281.08:24:20.77#ibcon#end of sib2, iclass 10, count 2 2006.281.08:24:20.77#ibcon#*after write, iclass 10, count 2 2006.281.08:24:20.77#ibcon#*before return 0, iclass 10, count 2 2006.281.08:24:20.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:20.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:20.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:24:20.77#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:20.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:20.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:20.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:20.89#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:24:20.89#ibcon#first serial, iclass 10, count 0 2006.281.08:24:20.89#ibcon#enter sib2, iclass 10, count 0 2006.281.08:24:20.89#ibcon#flushed, iclass 10, count 0 2006.281.08:24:20.89#ibcon#about to write, iclass 10, count 0 2006.281.08:24:20.89#ibcon#wrote, iclass 10, count 0 2006.281.08:24:20.89#ibcon#about to read 3, iclass 10, count 0 2006.281.08:24:20.91#ibcon#read 3, iclass 10, count 0 2006.281.08:24:20.91#ibcon#about to read 4, iclass 10, count 0 2006.281.08:24:20.91#ibcon#read 4, iclass 10, count 0 2006.281.08:24:20.91#ibcon#about to read 5, iclass 10, count 0 2006.281.08:24:20.91#ibcon#read 5, iclass 10, count 0 2006.281.08:24:20.91#ibcon#about to read 6, iclass 10, count 0 2006.281.08:24:20.91#ibcon#read 6, iclass 10, count 0 2006.281.08:24:20.91#ibcon#end of sib2, iclass 10, count 0 2006.281.08:24:20.91#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:24:20.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:24:20.91#ibcon#[25=USB\r\n] 2006.281.08:24:20.91#ibcon#*before write, iclass 10, count 0 2006.281.08:24:20.91#ibcon#enter sib2, iclass 10, count 0 2006.281.08:24:20.91#ibcon#flushed, iclass 10, count 0 2006.281.08:24:20.91#ibcon#about to write, iclass 10, count 0 2006.281.08:24:20.91#ibcon#wrote, iclass 10, count 0 2006.281.08:24:20.91#ibcon#about to read 3, iclass 10, count 0 2006.281.08:24:20.94#ibcon#read 3, iclass 10, count 0 2006.281.08:24:20.94#ibcon#about to read 4, iclass 10, count 0 2006.281.08:24:20.94#ibcon#read 4, iclass 10, count 0 2006.281.08:24:20.94#ibcon#about to read 5, iclass 10, count 0 2006.281.08:24:20.94#ibcon#read 5, iclass 10, count 0 2006.281.08:24:20.94#ibcon#about to read 6, iclass 10, count 0 2006.281.08:24:20.94#ibcon#read 6, iclass 10, count 0 2006.281.08:24:20.94#ibcon#end of sib2, iclass 10, count 0 2006.281.08:24:20.94#ibcon#*after write, iclass 10, count 0 2006.281.08:24:20.94#ibcon#*before return 0, iclass 10, count 0 2006.281.08:24:20.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:20.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:20.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:24:20.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:24:20.94$vc4f8/valo=6,772.99 2006.281.08:24:20.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:24:20.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:24:20.94#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:20.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:20.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:20.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:20.94#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:24:20.94#ibcon#first serial, iclass 12, count 0 2006.281.08:24:20.94#ibcon#enter sib2, iclass 12, count 0 2006.281.08:24:20.94#ibcon#flushed, iclass 12, count 0 2006.281.08:24:20.94#ibcon#about to write, iclass 12, count 0 2006.281.08:24:20.94#ibcon#wrote, iclass 12, count 0 2006.281.08:24:20.94#ibcon#about to read 3, iclass 12, count 0 2006.281.08:24:20.96#ibcon#read 3, iclass 12, count 0 2006.281.08:24:20.96#ibcon#about to read 4, iclass 12, count 0 2006.281.08:24:20.96#ibcon#read 4, iclass 12, count 0 2006.281.08:24:20.96#ibcon#about to read 5, iclass 12, count 0 2006.281.08:24:20.96#ibcon#read 5, iclass 12, count 0 2006.281.08:24:20.96#ibcon#about to read 6, iclass 12, count 0 2006.281.08:24:20.96#ibcon#read 6, iclass 12, count 0 2006.281.08:24:20.96#ibcon#end of sib2, iclass 12, count 0 2006.281.08:24:20.96#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:24:20.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:24:20.96#ibcon#[26=FRQ=06,772.99\r\n] 2006.281.08:24:20.96#ibcon#*before write, iclass 12, count 0 2006.281.08:24:20.96#ibcon#enter sib2, iclass 12, count 0 2006.281.08:24:20.96#ibcon#flushed, iclass 12, count 0 2006.281.08:24:20.96#ibcon#about to write, iclass 12, count 0 2006.281.08:24:20.96#ibcon#wrote, iclass 12, count 0 2006.281.08:24:20.96#ibcon#about to read 3, iclass 12, count 0 2006.281.08:24:21.01#ibcon#read 3, iclass 12, count 0 2006.281.08:24:21.01#ibcon#about to read 4, iclass 12, count 0 2006.281.08:24:21.01#ibcon#read 4, iclass 12, count 0 2006.281.08:24:21.01#ibcon#about to read 5, iclass 12, count 0 2006.281.08:24:21.01#ibcon#read 5, iclass 12, count 0 2006.281.08:24:21.01#ibcon#about to read 6, iclass 12, count 0 2006.281.08:24:21.01#ibcon#read 6, iclass 12, count 0 2006.281.08:24:21.01#ibcon#end of sib2, iclass 12, count 0 2006.281.08:24:21.01#ibcon#*after write, iclass 12, count 0 2006.281.08:24:21.01#ibcon#*before return 0, iclass 12, count 0 2006.281.08:24:21.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:21.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:21.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:24:21.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:24:21.01$vc4f8/va=6,6 2006.281.08:24:21.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.281.08:24:21.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.281.08:24:21.01#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:21.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:21.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:21.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:21.05#ibcon#enter wrdev, iclass 14, count 2 2006.281.08:24:21.05#ibcon#first serial, iclass 14, count 2 2006.281.08:24:21.05#ibcon#enter sib2, iclass 14, count 2 2006.281.08:24:21.05#ibcon#flushed, iclass 14, count 2 2006.281.08:24:21.05#ibcon#about to write, iclass 14, count 2 2006.281.08:24:21.05#ibcon#wrote, iclass 14, count 2 2006.281.08:24:21.05#ibcon#about to read 3, iclass 14, count 2 2006.281.08:24:21.07#ibcon#read 3, iclass 14, count 2 2006.281.08:24:21.07#ibcon#about to read 4, iclass 14, count 2 2006.281.08:24:21.07#ibcon#read 4, iclass 14, count 2 2006.281.08:24:21.07#ibcon#about to read 5, iclass 14, count 2 2006.281.08:24:21.07#ibcon#read 5, iclass 14, count 2 2006.281.08:24:21.07#ibcon#about to read 6, iclass 14, count 2 2006.281.08:24:21.07#ibcon#read 6, iclass 14, count 2 2006.281.08:24:21.07#ibcon#end of sib2, iclass 14, count 2 2006.281.08:24:21.07#ibcon#*mode == 0, iclass 14, count 2 2006.281.08:24:21.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.281.08:24:21.07#ibcon#[25=AT06-06\r\n] 2006.281.08:24:21.07#ibcon#*before write, iclass 14, count 2 2006.281.08:24:21.07#ibcon#enter sib2, iclass 14, count 2 2006.281.08:24:21.07#ibcon#flushed, iclass 14, count 2 2006.281.08:24:21.07#ibcon#about to write, iclass 14, count 2 2006.281.08:24:21.07#ibcon#wrote, iclass 14, count 2 2006.281.08:24:21.07#ibcon#about to read 3, iclass 14, count 2 2006.281.08:24:21.11#ibcon#read 3, iclass 14, count 2 2006.281.08:24:21.11#ibcon#about to read 4, iclass 14, count 2 2006.281.08:24:21.11#ibcon#read 4, iclass 14, count 2 2006.281.08:24:21.11#ibcon#about to read 5, iclass 14, count 2 2006.281.08:24:21.11#ibcon#read 5, iclass 14, count 2 2006.281.08:24:21.11#ibcon#about to read 6, iclass 14, count 2 2006.281.08:24:21.11#ibcon#read 6, iclass 14, count 2 2006.281.08:24:21.11#ibcon#end of sib2, iclass 14, count 2 2006.281.08:24:21.11#ibcon#*after write, iclass 14, count 2 2006.281.08:24:21.11#ibcon#*before return 0, iclass 14, count 2 2006.281.08:24:21.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:21.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:21.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.281.08:24:21.11#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:21.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:24:21.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:24:21.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:24:21.22#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:24:21.22#ibcon#first serial, iclass 14, count 0 2006.281.08:24:21.22#ibcon#enter sib2, iclass 14, count 0 2006.281.08:24:21.22#ibcon#flushed, iclass 14, count 0 2006.281.08:24:21.22#ibcon#about to write, iclass 14, count 0 2006.281.08:24:21.22#ibcon#wrote, iclass 14, count 0 2006.281.08:24:21.22#ibcon#about to read 3, iclass 14, count 0 2006.281.08:24:21.24#ibcon#read 3, iclass 14, count 0 2006.281.08:24:21.24#ibcon#about to read 4, iclass 14, count 0 2006.281.08:24:21.24#ibcon#read 4, iclass 14, count 0 2006.281.08:24:21.24#ibcon#about to read 5, iclass 14, count 0 2006.281.08:24:21.24#ibcon#read 5, iclass 14, count 0 2006.281.08:24:21.24#ibcon#about to read 6, iclass 14, count 0 2006.281.08:24:21.24#ibcon#read 6, iclass 14, count 0 2006.281.08:24:21.24#ibcon#end of sib2, iclass 14, count 0 2006.281.08:24:21.24#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:24:21.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:24:21.24#ibcon#[25=USB\r\n] 2006.281.08:24:21.24#ibcon#*before write, iclass 14, count 0 2006.281.08:24:21.24#ibcon#enter sib2, iclass 14, count 0 2006.281.08:24:21.24#ibcon#flushed, iclass 14, count 0 2006.281.08:24:21.24#ibcon#about to write, iclass 14, count 0 2006.281.08:24:21.24#ibcon#wrote, iclass 14, count 0 2006.281.08:24:21.24#ibcon#about to read 3, iclass 14, count 0 2006.281.08:24:21.27#ibcon#read 3, iclass 14, count 0 2006.281.08:24:21.27#ibcon#about to read 4, iclass 14, count 0 2006.281.08:24:21.27#ibcon#read 4, iclass 14, count 0 2006.281.08:24:21.27#ibcon#about to read 5, iclass 14, count 0 2006.281.08:24:21.27#ibcon#read 5, iclass 14, count 0 2006.281.08:24:21.27#ibcon#about to read 6, iclass 14, count 0 2006.281.08:24:21.27#ibcon#read 6, iclass 14, count 0 2006.281.08:24:21.27#ibcon#end of sib2, iclass 14, count 0 2006.281.08:24:21.27#ibcon#*after write, iclass 14, count 0 2006.281.08:24:21.27#ibcon#*before return 0, iclass 14, count 0 2006.281.08:24:21.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:24:21.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.281.08:24:21.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:24:21.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:24:21.27$vc4f8/valo=7,832.99 2006.281.08:24:21.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.281.08:24:21.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.281.08:24:21.27#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:21.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:24:21.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:24:21.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:24:21.27#ibcon#enter wrdev, iclass 16, count 0 2006.281.08:24:21.27#ibcon#first serial, iclass 16, count 0 2006.281.08:24:21.27#ibcon#enter sib2, iclass 16, count 0 2006.281.08:24:21.27#ibcon#flushed, iclass 16, count 0 2006.281.08:24:21.27#ibcon#about to write, iclass 16, count 0 2006.281.08:24:21.27#ibcon#wrote, iclass 16, count 0 2006.281.08:24:21.27#ibcon#about to read 3, iclass 16, count 0 2006.281.08:24:21.29#ibcon#read 3, iclass 16, count 0 2006.281.08:24:21.29#ibcon#about to read 4, iclass 16, count 0 2006.281.08:24:21.29#ibcon#read 4, iclass 16, count 0 2006.281.08:24:21.29#ibcon#about to read 5, iclass 16, count 0 2006.281.08:24:21.29#ibcon#read 5, iclass 16, count 0 2006.281.08:24:21.29#ibcon#about to read 6, iclass 16, count 0 2006.281.08:24:21.29#ibcon#read 6, iclass 16, count 0 2006.281.08:24:21.29#ibcon#end of sib2, iclass 16, count 0 2006.281.08:24:21.29#ibcon#*mode == 0, iclass 16, count 0 2006.281.08:24:21.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.281.08:24:21.31#ibcon#[26=FRQ=07,832.99\r\n] 2006.281.08:24:21.31#ibcon#*before write, iclass 16, count 0 2006.281.08:24:21.31#ibcon#enter sib2, iclass 16, count 0 2006.281.08:24:21.31#ibcon#flushed, iclass 16, count 0 2006.281.08:24:21.31#ibcon#about to write, iclass 16, count 0 2006.281.08:24:21.31#ibcon#wrote, iclass 16, count 0 2006.281.08:24:21.31#ibcon#about to read 3, iclass 16, count 0 2006.281.08:24:21.35#ibcon#read 3, iclass 16, count 0 2006.281.08:24:21.35#ibcon#about to read 4, iclass 16, count 0 2006.281.08:24:21.35#ibcon#read 4, iclass 16, count 0 2006.281.08:24:21.35#ibcon#about to read 5, iclass 16, count 0 2006.281.08:24:21.35#ibcon#read 5, iclass 16, count 0 2006.281.08:24:21.35#ibcon#about to read 6, iclass 16, count 0 2006.281.08:24:21.35#ibcon#read 6, iclass 16, count 0 2006.281.08:24:21.35#ibcon#end of sib2, iclass 16, count 0 2006.281.08:24:21.35#ibcon#*after write, iclass 16, count 0 2006.281.08:24:21.35#ibcon#*before return 0, iclass 16, count 0 2006.281.08:24:21.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:24:21.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.281.08:24:21.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.281.08:24:21.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.281.08:24:21.35$vc4f8/va=7,6 2006.281.08:24:21.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.281.08:24:21.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.281.08:24:21.35#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:21.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:24:21.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:24:21.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:24:21.39#ibcon#enter wrdev, iclass 18, count 2 2006.281.08:24:21.39#ibcon#first serial, iclass 18, count 2 2006.281.08:24:21.39#ibcon#enter sib2, iclass 18, count 2 2006.281.08:24:21.39#ibcon#flushed, iclass 18, count 2 2006.281.08:24:21.39#ibcon#about to write, iclass 18, count 2 2006.281.08:24:21.39#ibcon#wrote, iclass 18, count 2 2006.281.08:24:21.39#ibcon#about to read 3, iclass 18, count 2 2006.281.08:24:21.41#ibcon#read 3, iclass 18, count 2 2006.281.08:24:21.41#ibcon#about to read 4, iclass 18, count 2 2006.281.08:24:21.41#ibcon#read 4, iclass 18, count 2 2006.281.08:24:21.41#ibcon#about to read 5, iclass 18, count 2 2006.281.08:24:21.41#ibcon#read 5, iclass 18, count 2 2006.281.08:24:21.41#ibcon#about to read 6, iclass 18, count 2 2006.281.08:24:21.41#ibcon#read 6, iclass 18, count 2 2006.281.08:24:21.41#ibcon#end of sib2, iclass 18, count 2 2006.281.08:24:21.41#ibcon#*mode == 0, iclass 18, count 2 2006.281.08:24:21.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.281.08:24:21.41#ibcon#[25=AT07-06\r\n] 2006.281.08:24:21.41#ibcon#*before write, iclass 18, count 2 2006.281.08:24:21.41#ibcon#enter sib2, iclass 18, count 2 2006.281.08:24:21.41#ibcon#flushed, iclass 18, count 2 2006.281.08:24:21.41#ibcon#about to write, iclass 18, count 2 2006.281.08:24:21.41#ibcon#wrote, iclass 18, count 2 2006.281.08:24:21.41#ibcon#about to read 3, iclass 18, count 2 2006.281.08:24:21.44#ibcon#read 3, iclass 18, count 2 2006.281.08:24:21.44#ibcon#about to read 4, iclass 18, count 2 2006.281.08:24:21.44#ibcon#read 4, iclass 18, count 2 2006.281.08:24:21.44#ibcon#about to read 5, iclass 18, count 2 2006.281.08:24:21.44#ibcon#read 5, iclass 18, count 2 2006.281.08:24:21.44#ibcon#about to read 6, iclass 18, count 2 2006.281.08:24:21.44#ibcon#read 6, iclass 18, count 2 2006.281.08:24:21.44#ibcon#end of sib2, iclass 18, count 2 2006.281.08:24:21.44#ibcon#*after write, iclass 18, count 2 2006.281.08:24:21.44#ibcon#*before return 0, iclass 18, count 2 2006.281.08:24:21.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:24:21.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.281.08:24:21.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.281.08:24:21.44#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:21.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:24:21.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:24:21.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:24:21.57#ibcon#enter wrdev, iclass 18, count 0 2006.281.08:24:21.57#ibcon#first serial, iclass 18, count 0 2006.281.08:24:21.57#ibcon#enter sib2, iclass 18, count 0 2006.281.08:24:21.57#ibcon#flushed, iclass 18, count 0 2006.281.08:24:21.57#ibcon#about to write, iclass 18, count 0 2006.281.08:24:21.57#ibcon#wrote, iclass 18, count 0 2006.281.08:24:21.57#ibcon#about to read 3, iclass 18, count 0 2006.281.08:24:21.58#ibcon#read 3, iclass 18, count 0 2006.281.08:24:21.58#ibcon#about to read 4, iclass 18, count 0 2006.281.08:24:21.58#ibcon#read 4, iclass 18, count 0 2006.281.08:24:21.58#ibcon#about to read 5, iclass 18, count 0 2006.281.08:24:21.58#ibcon#read 5, iclass 18, count 0 2006.281.08:24:21.58#ibcon#about to read 6, iclass 18, count 0 2006.281.08:24:21.58#ibcon#read 6, iclass 18, count 0 2006.281.08:24:21.58#ibcon#end of sib2, iclass 18, count 0 2006.281.08:24:21.58#ibcon#*mode == 0, iclass 18, count 0 2006.281.08:24:21.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.281.08:24:21.58#ibcon#[25=USB\r\n] 2006.281.08:24:21.58#ibcon#*before write, iclass 18, count 0 2006.281.08:24:21.58#ibcon#enter sib2, iclass 18, count 0 2006.281.08:24:21.58#ibcon#flushed, iclass 18, count 0 2006.281.08:24:21.58#ibcon#about to write, iclass 18, count 0 2006.281.08:24:21.58#ibcon#wrote, iclass 18, count 0 2006.281.08:24:21.58#ibcon#about to read 3, iclass 18, count 0 2006.281.08:24:21.61#ibcon#read 3, iclass 18, count 0 2006.281.08:24:21.61#ibcon#about to read 4, iclass 18, count 0 2006.281.08:24:21.61#ibcon#read 4, iclass 18, count 0 2006.281.08:24:21.61#ibcon#about to read 5, iclass 18, count 0 2006.281.08:24:21.61#ibcon#read 5, iclass 18, count 0 2006.281.08:24:21.61#ibcon#about to read 6, iclass 18, count 0 2006.281.08:24:21.61#ibcon#read 6, iclass 18, count 0 2006.281.08:24:21.61#ibcon#end of sib2, iclass 18, count 0 2006.281.08:24:21.61#ibcon#*after write, iclass 18, count 0 2006.281.08:24:21.61#ibcon#*before return 0, iclass 18, count 0 2006.281.08:24:21.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:24:21.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.281.08:24:21.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.281.08:24:21.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.281.08:24:21.61$vc4f8/valo=8,852.99 2006.281.08:24:21.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.281.08:24:21.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.281.08:24:21.61#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:21.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:24:21.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:24:21.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:24:21.61#ibcon#enter wrdev, iclass 20, count 0 2006.281.08:24:21.61#ibcon#first serial, iclass 20, count 0 2006.281.08:24:21.61#ibcon#enter sib2, iclass 20, count 0 2006.281.08:24:21.61#ibcon#flushed, iclass 20, count 0 2006.281.08:24:21.61#ibcon#about to write, iclass 20, count 0 2006.281.08:24:21.61#ibcon#wrote, iclass 20, count 0 2006.281.08:24:21.61#ibcon#about to read 3, iclass 20, count 0 2006.281.08:24:21.63#ibcon#read 3, iclass 20, count 0 2006.281.08:24:21.63#ibcon#about to read 4, iclass 20, count 0 2006.281.08:24:21.63#ibcon#read 4, iclass 20, count 0 2006.281.08:24:21.63#ibcon#about to read 5, iclass 20, count 0 2006.281.08:24:21.63#ibcon#read 5, iclass 20, count 0 2006.281.08:24:21.63#ibcon#about to read 6, iclass 20, count 0 2006.281.08:24:21.63#ibcon#read 6, iclass 20, count 0 2006.281.08:24:21.63#ibcon#end of sib2, iclass 20, count 0 2006.281.08:24:21.63#ibcon#*mode == 0, iclass 20, count 0 2006.281.08:24:21.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.281.08:24:21.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.281.08:24:21.63#ibcon#*before write, iclass 20, count 0 2006.281.08:24:21.63#ibcon#enter sib2, iclass 20, count 0 2006.281.08:24:21.63#ibcon#flushed, iclass 20, count 0 2006.281.08:24:21.63#ibcon#about to write, iclass 20, count 0 2006.281.08:24:21.63#ibcon#wrote, iclass 20, count 0 2006.281.08:24:21.63#ibcon#about to read 3, iclass 20, count 0 2006.281.08:24:21.67#ibcon#read 3, iclass 20, count 0 2006.281.08:24:21.67#ibcon#about to read 4, iclass 20, count 0 2006.281.08:24:21.67#ibcon#read 4, iclass 20, count 0 2006.281.08:24:21.67#ibcon#about to read 5, iclass 20, count 0 2006.281.08:24:21.67#ibcon#read 5, iclass 20, count 0 2006.281.08:24:21.67#ibcon#about to read 6, iclass 20, count 0 2006.281.08:24:21.67#ibcon#read 6, iclass 20, count 0 2006.281.08:24:21.67#ibcon#end of sib2, iclass 20, count 0 2006.281.08:24:21.67#ibcon#*after write, iclass 20, count 0 2006.281.08:24:21.67#ibcon#*before return 0, iclass 20, count 0 2006.281.08:24:21.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:24:21.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.281.08:24:21.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.281.08:24:21.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.281.08:24:21.67$vc4f8/va=8,6 2006.281.08:24:21.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.281.08:24:21.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.281.08:24:21.67#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:21.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:24:21.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:24:21.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:24:21.73#ibcon#enter wrdev, iclass 22, count 2 2006.281.08:24:21.73#ibcon#first serial, iclass 22, count 2 2006.281.08:24:21.73#ibcon#enter sib2, iclass 22, count 2 2006.281.08:24:21.73#ibcon#flushed, iclass 22, count 2 2006.281.08:24:21.73#ibcon#about to write, iclass 22, count 2 2006.281.08:24:21.73#ibcon#wrote, iclass 22, count 2 2006.281.08:24:21.73#ibcon#about to read 3, iclass 22, count 2 2006.281.08:24:21.76#ibcon#read 3, iclass 22, count 2 2006.281.08:24:21.76#ibcon#about to read 4, iclass 22, count 2 2006.281.08:24:21.76#ibcon#read 4, iclass 22, count 2 2006.281.08:24:21.76#ibcon#about to read 5, iclass 22, count 2 2006.281.08:24:21.76#ibcon#read 5, iclass 22, count 2 2006.281.08:24:21.76#ibcon#about to read 6, iclass 22, count 2 2006.281.08:24:21.76#ibcon#read 6, iclass 22, count 2 2006.281.08:24:21.76#ibcon#end of sib2, iclass 22, count 2 2006.281.08:24:21.76#ibcon#*mode == 0, iclass 22, count 2 2006.281.08:24:21.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.281.08:24:21.76#ibcon#[25=AT08-06\r\n] 2006.281.08:24:21.76#ibcon#*before write, iclass 22, count 2 2006.281.08:24:21.76#ibcon#enter sib2, iclass 22, count 2 2006.281.08:24:21.76#ibcon#flushed, iclass 22, count 2 2006.281.08:24:21.76#ibcon#about to write, iclass 22, count 2 2006.281.08:24:21.76#ibcon#wrote, iclass 22, count 2 2006.281.08:24:21.76#ibcon#about to read 3, iclass 22, count 2 2006.281.08:24:21.78#ibcon#read 3, iclass 22, count 2 2006.281.08:24:21.78#ibcon#about to read 4, iclass 22, count 2 2006.281.08:24:21.78#ibcon#read 4, iclass 22, count 2 2006.281.08:24:21.78#ibcon#about to read 5, iclass 22, count 2 2006.281.08:24:21.78#ibcon#read 5, iclass 22, count 2 2006.281.08:24:21.78#ibcon#about to read 6, iclass 22, count 2 2006.281.08:24:21.78#ibcon#read 6, iclass 22, count 2 2006.281.08:24:21.78#ibcon#end of sib2, iclass 22, count 2 2006.281.08:24:21.78#ibcon#*after write, iclass 22, count 2 2006.281.08:24:21.78#ibcon#*before return 0, iclass 22, count 2 2006.281.08:24:21.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:24:21.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.281.08:24:21.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.281.08:24:21.78#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:21.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:24:21.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:24:21.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:24:21.90#ibcon#enter wrdev, iclass 22, count 0 2006.281.08:24:21.90#ibcon#first serial, iclass 22, count 0 2006.281.08:24:21.90#ibcon#enter sib2, iclass 22, count 0 2006.281.08:24:21.90#ibcon#flushed, iclass 22, count 0 2006.281.08:24:21.90#ibcon#about to write, iclass 22, count 0 2006.281.08:24:21.90#ibcon#wrote, iclass 22, count 0 2006.281.08:24:21.90#ibcon#about to read 3, iclass 22, count 0 2006.281.08:24:21.92#ibcon#read 3, iclass 22, count 0 2006.281.08:24:21.92#ibcon#about to read 4, iclass 22, count 0 2006.281.08:24:21.92#ibcon#read 4, iclass 22, count 0 2006.281.08:24:21.92#ibcon#about to read 5, iclass 22, count 0 2006.281.08:24:21.92#ibcon#read 5, iclass 22, count 0 2006.281.08:24:21.92#ibcon#about to read 6, iclass 22, count 0 2006.281.08:24:21.92#ibcon#read 6, iclass 22, count 0 2006.281.08:24:21.92#ibcon#end of sib2, iclass 22, count 0 2006.281.08:24:21.92#ibcon#*mode == 0, iclass 22, count 0 2006.281.08:24:21.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.281.08:24:21.92#ibcon#[25=USB\r\n] 2006.281.08:24:21.92#ibcon#*before write, iclass 22, count 0 2006.281.08:24:21.92#ibcon#enter sib2, iclass 22, count 0 2006.281.08:24:21.92#ibcon#flushed, iclass 22, count 0 2006.281.08:24:21.92#ibcon#about to write, iclass 22, count 0 2006.281.08:24:21.92#ibcon#wrote, iclass 22, count 0 2006.281.08:24:21.92#ibcon#about to read 3, iclass 22, count 0 2006.281.08:24:21.95#ibcon#read 3, iclass 22, count 0 2006.281.08:24:21.95#ibcon#about to read 4, iclass 22, count 0 2006.281.08:24:21.95#ibcon#read 4, iclass 22, count 0 2006.281.08:24:21.95#ibcon#about to read 5, iclass 22, count 0 2006.281.08:24:21.95#ibcon#read 5, iclass 22, count 0 2006.281.08:24:21.95#ibcon#about to read 6, iclass 22, count 0 2006.281.08:24:21.95#ibcon#read 6, iclass 22, count 0 2006.281.08:24:21.95#ibcon#end of sib2, iclass 22, count 0 2006.281.08:24:21.95#ibcon#*after write, iclass 22, count 0 2006.281.08:24:21.95#ibcon#*before return 0, iclass 22, count 0 2006.281.08:24:21.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:24:21.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.281.08:24:21.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.281.08:24:21.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.281.08:24:21.95$vc4f8/vblo=1,632.99 2006.281.08:24:21.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.281.08:24:21.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.281.08:24:21.95#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:21.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:24:21.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:24:21.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:24:21.95#ibcon#enter wrdev, iclass 24, count 0 2006.281.08:24:21.95#ibcon#first serial, iclass 24, count 0 2006.281.08:24:21.95#ibcon#enter sib2, iclass 24, count 0 2006.281.08:24:21.95#ibcon#flushed, iclass 24, count 0 2006.281.08:24:21.95#ibcon#about to write, iclass 24, count 0 2006.281.08:24:21.95#ibcon#wrote, iclass 24, count 0 2006.281.08:24:21.95#ibcon#about to read 3, iclass 24, count 0 2006.281.08:24:21.97#ibcon#read 3, iclass 24, count 0 2006.281.08:24:21.97#ibcon#about to read 4, iclass 24, count 0 2006.281.08:24:21.97#ibcon#read 4, iclass 24, count 0 2006.281.08:24:21.97#ibcon#about to read 5, iclass 24, count 0 2006.281.08:24:21.97#ibcon#read 5, iclass 24, count 0 2006.281.08:24:21.97#ibcon#about to read 6, iclass 24, count 0 2006.281.08:24:21.97#ibcon#read 6, iclass 24, count 0 2006.281.08:24:21.97#ibcon#end of sib2, iclass 24, count 0 2006.281.08:24:21.97#ibcon#*mode == 0, iclass 24, count 0 2006.281.08:24:21.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.281.08:24:21.99#ibcon#[28=FRQ=01,632.99\r\n] 2006.281.08:24:21.99#ibcon#*before write, iclass 24, count 0 2006.281.08:24:21.99#ibcon#enter sib2, iclass 24, count 0 2006.281.08:24:21.99#ibcon#flushed, iclass 24, count 0 2006.281.08:24:21.99#ibcon#about to write, iclass 24, count 0 2006.281.08:24:21.99#ibcon#wrote, iclass 24, count 0 2006.281.08:24:21.99#ibcon#about to read 3, iclass 24, count 0 2006.281.08:24:22.03#ibcon#read 3, iclass 24, count 0 2006.281.08:24:22.03#ibcon#about to read 4, iclass 24, count 0 2006.281.08:24:22.03#ibcon#read 4, iclass 24, count 0 2006.281.08:24:22.03#ibcon#about to read 5, iclass 24, count 0 2006.281.08:24:22.03#ibcon#read 5, iclass 24, count 0 2006.281.08:24:22.03#ibcon#about to read 6, iclass 24, count 0 2006.281.08:24:22.03#ibcon#read 6, iclass 24, count 0 2006.281.08:24:22.03#ibcon#end of sib2, iclass 24, count 0 2006.281.08:24:22.03#ibcon#*after write, iclass 24, count 0 2006.281.08:24:22.03#ibcon#*before return 0, iclass 24, count 0 2006.281.08:24:22.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:24:22.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.281.08:24:22.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.281.08:24:22.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.281.08:24:22.03$vc4f8/vb=1,4 2006.281.08:24:22.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.281.08:24:22.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.281.08:24:22.03#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:22.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:24:22.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:24:22.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:24:22.03#ibcon#enter wrdev, iclass 26, count 2 2006.281.08:24:22.03#ibcon#first serial, iclass 26, count 2 2006.281.08:24:22.03#ibcon#enter sib2, iclass 26, count 2 2006.281.08:24:22.03#ibcon#flushed, iclass 26, count 2 2006.281.08:24:22.03#ibcon#about to write, iclass 26, count 2 2006.281.08:24:22.03#ibcon#wrote, iclass 26, count 2 2006.281.08:24:22.03#ibcon#about to read 3, iclass 26, count 2 2006.281.08:24:22.05#ibcon#read 3, iclass 26, count 2 2006.281.08:24:22.05#ibcon#about to read 4, iclass 26, count 2 2006.281.08:24:22.05#ibcon#read 4, iclass 26, count 2 2006.281.08:24:22.05#ibcon#about to read 5, iclass 26, count 2 2006.281.08:24:22.05#ibcon#read 5, iclass 26, count 2 2006.281.08:24:22.05#ibcon#about to read 6, iclass 26, count 2 2006.281.08:24:22.05#ibcon#read 6, iclass 26, count 2 2006.281.08:24:22.05#ibcon#end of sib2, iclass 26, count 2 2006.281.08:24:22.05#ibcon#*mode == 0, iclass 26, count 2 2006.281.08:24:22.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.281.08:24:22.05#ibcon#[27=AT01-04\r\n] 2006.281.08:24:22.05#ibcon#*before write, iclass 26, count 2 2006.281.08:24:22.05#ibcon#enter sib2, iclass 26, count 2 2006.281.08:24:22.05#ibcon#flushed, iclass 26, count 2 2006.281.08:24:22.05#ibcon#about to write, iclass 26, count 2 2006.281.08:24:22.05#ibcon#wrote, iclass 26, count 2 2006.281.08:24:22.05#ibcon#about to read 3, iclass 26, count 2 2006.281.08:24:22.09#ibcon#read 3, iclass 26, count 2 2006.281.08:24:22.09#ibcon#about to read 4, iclass 26, count 2 2006.281.08:24:22.09#ibcon#read 4, iclass 26, count 2 2006.281.08:24:22.09#ibcon#about to read 5, iclass 26, count 2 2006.281.08:24:22.09#ibcon#read 5, iclass 26, count 2 2006.281.08:24:22.09#ibcon#about to read 6, iclass 26, count 2 2006.281.08:24:22.09#ibcon#read 6, iclass 26, count 2 2006.281.08:24:22.09#ibcon#end of sib2, iclass 26, count 2 2006.281.08:24:22.09#ibcon#*after write, iclass 26, count 2 2006.281.08:24:22.09#ibcon#*before return 0, iclass 26, count 2 2006.281.08:24:22.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:24:22.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.281.08:24:22.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.281.08:24:22.09#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:22.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:24:22.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:24:22.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:24:22.20#ibcon#enter wrdev, iclass 26, count 0 2006.281.08:24:22.20#ibcon#first serial, iclass 26, count 0 2006.281.08:24:22.20#ibcon#enter sib2, iclass 26, count 0 2006.281.08:24:22.20#ibcon#flushed, iclass 26, count 0 2006.281.08:24:22.20#ibcon#about to write, iclass 26, count 0 2006.281.08:24:22.20#ibcon#wrote, iclass 26, count 0 2006.281.08:24:22.20#ibcon#about to read 3, iclass 26, count 0 2006.281.08:24:22.22#ibcon#read 3, iclass 26, count 0 2006.281.08:24:22.22#ibcon#about to read 4, iclass 26, count 0 2006.281.08:24:22.22#ibcon#read 4, iclass 26, count 0 2006.281.08:24:22.22#ibcon#about to read 5, iclass 26, count 0 2006.281.08:24:22.22#ibcon#read 5, iclass 26, count 0 2006.281.08:24:22.22#ibcon#about to read 6, iclass 26, count 0 2006.281.08:24:22.22#ibcon#read 6, iclass 26, count 0 2006.281.08:24:22.22#ibcon#end of sib2, iclass 26, count 0 2006.281.08:24:22.22#ibcon#*mode == 0, iclass 26, count 0 2006.281.08:24:22.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.281.08:24:22.22#ibcon#[27=USB\r\n] 2006.281.08:24:22.22#ibcon#*before write, iclass 26, count 0 2006.281.08:24:22.22#ibcon#enter sib2, iclass 26, count 0 2006.281.08:24:22.22#ibcon#flushed, iclass 26, count 0 2006.281.08:24:22.22#ibcon#about to write, iclass 26, count 0 2006.281.08:24:22.22#ibcon#wrote, iclass 26, count 0 2006.281.08:24:22.22#ibcon#about to read 3, iclass 26, count 0 2006.281.08:24:22.25#ibcon#read 3, iclass 26, count 0 2006.281.08:24:22.25#ibcon#about to read 4, iclass 26, count 0 2006.281.08:24:22.25#ibcon#read 4, iclass 26, count 0 2006.281.08:24:22.25#ibcon#about to read 5, iclass 26, count 0 2006.281.08:24:22.25#ibcon#read 5, iclass 26, count 0 2006.281.08:24:22.25#ibcon#about to read 6, iclass 26, count 0 2006.281.08:24:22.25#ibcon#read 6, iclass 26, count 0 2006.281.08:24:22.25#ibcon#end of sib2, iclass 26, count 0 2006.281.08:24:22.25#ibcon#*after write, iclass 26, count 0 2006.281.08:24:22.25#ibcon#*before return 0, iclass 26, count 0 2006.281.08:24:22.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:24:22.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.281.08:24:22.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.281.08:24:22.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.281.08:24:22.25$vc4f8/vblo=2,640.99 2006.281.08:24:22.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.281.08:24:22.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.281.08:24:22.25#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:22.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:22.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:22.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:22.25#ibcon#enter wrdev, iclass 28, count 0 2006.281.08:24:22.25#ibcon#first serial, iclass 28, count 0 2006.281.08:24:22.25#ibcon#enter sib2, iclass 28, count 0 2006.281.08:24:22.25#ibcon#flushed, iclass 28, count 0 2006.281.08:24:22.25#ibcon#about to write, iclass 28, count 0 2006.281.08:24:22.25#ibcon#wrote, iclass 28, count 0 2006.281.08:24:22.25#ibcon#about to read 3, iclass 28, count 0 2006.281.08:24:22.27#ibcon#read 3, iclass 28, count 0 2006.281.08:24:22.27#ibcon#about to read 4, iclass 28, count 0 2006.281.08:24:22.27#ibcon#read 4, iclass 28, count 0 2006.281.08:24:22.27#ibcon#about to read 5, iclass 28, count 0 2006.281.08:24:22.27#ibcon#read 5, iclass 28, count 0 2006.281.08:24:22.27#ibcon#about to read 6, iclass 28, count 0 2006.281.08:24:22.27#ibcon#read 6, iclass 28, count 0 2006.281.08:24:22.27#ibcon#end of sib2, iclass 28, count 0 2006.281.08:24:22.27#ibcon#*mode == 0, iclass 28, count 0 2006.281.08:24:22.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.281.08:24:22.29#ibcon#[28=FRQ=02,640.99\r\n] 2006.281.08:24:22.29#ibcon#*before write, iclass 28, count 0 2006.281.08:24:22.29#ibcon#enter sib2, iclass 28, count 0 2006.281.08:24:22.29#ibcon#flushed, iclass 28, count 0 2006.281.08:24:22.29#ibcon#about to write, iclass 28, count 0 2006.281.08:24:22.29#ibcon#wrote, iclass 28, count 0 2006.281.08:24:22.29#ibcon#about to read 3, iclass 28, count 0 2006.281.08:24:22.33#ibcon#read 3, iclass 28, count 0 2006.281.08:24:22.33#ibcon#about to read 4, iclass 28, count 0 2006.281.08:24:22.33#ibcon#read 4, iclass 28, count 0 2006.281.08:24:22.33#ibcon#about to read 5, iclass 28, count 0 2006.281.08:24:22.33#ibcon#read 5, iclass 28, count 0 2006.281.08:24:22.33#ibcon#about to read 6, iclass 28, count 0 2006.281.08:24:22.33#ibcon#read 6, iclass 28, count 0 2006.281.08:24:22.33#ibcon#end of sib2, iclass 28, count 0 2006.281.08:24:22.33#ibcon#*after write, iclass 28, count 0 2006.281.08:24:22.33#ibcon#*before return 0, iclass 28, count 0 2006.281.08:24:22.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:22.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.281.08:24:22.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.281.08:24:22.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.281.08:24:22.33$vc4f8/vb=2,5 2006.281.08:24:22.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.281.08:24:22.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.281.08:24:22.33#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:22.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:22.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:22.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:22.37#ibcon#enter wrdev, iclass 30, count 2 2006.281.08:24:22.37#ibcon#first serial, iclass 30, count 2 2006.281.08:24:22.37#ibcon#enter sib2, iclass 30, count 2 2006.281.08:24:22.37#ibcon#flushed, iclass 30, count 2 2006.281.08:24:22.37#ibcon#about to write, iclass 30, count 2 2006.281.08:24:22.37#ibcon#wrote, iclass 30, count 2 2006.281.08:24:22.37#ibcon#about to read 3, iclass 30, count 2 2006.281.08:24:22.39#ibcon#read 3, iclass 30, count 2 2006.281.08:24:22.39#ibcon#about to read 4, iclass 30, count 2 2006.281.08:24:22.39#ibcon#read 4, iclass 30, count 2 2006.281.08:24:22.39#ibcon#about to read 5, iclass 30, count 2 2006.281.08:24:22.39#ibcon#read 5, iclass 30, count 2 2006.281.08:24:22.39#ibcon#about to read 6, iclass 30, count 2 2006.281.08:24:22.39#ibcon#read 6, iclass 30, count 2 2006.281.08:24:22.39#ibcon#end of sib2, iclass 30, count 2 2006.281.08:24:22.39#ibcon#*mode == 0, iclass 30, count 2 2006.281.08:24:22.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.281.08:24:22.39#ibcon#[27=AT02-05\r\n] 2006.281.08:24:22.39#ibcon#*before write, iclass 30, count 2 2006.281.08:24:22.39#ibcon#enter sib2, iclass 30, count 2 2006.281.08:24:22.39#ibcon#flushed, iclass 30, count 2 2006.281.08:24:22.39#ibcon#about to write, iclass 30, count 2 2006.281.08:24:22.39#ibcon#wrote, iclass 30, count 2 2006.281.08:24:22.39#ibcon#about to read 3, iclass 30, count 2 2006.281.08:24:22.42#ibcon#read 3, iclass 30, count 2 2006.281.08:24:22.42#ibcon#about to read 4, iclass 30, count 2 2006.281.08:24:22.42#ibcon#read 4, iclass 30, count 2 2006.281.08:24:22.42#ibcon#about to read 5, iclass 30, count 2 2006.281.08:24:22.42#ibcon#read 5, iclass 30, count 2 2006.281.08:24:22.42#ibcon#about to read 6, iclass 30, count 2 2006.281.08:24:22.42#ibcon#read 6, iclass 30, count 2 2006.281.08:24:22.42#ibcon#end of sib2, iclass 30, count 2 2006.281.08:24:22.42#ibcon#*after write, iclass 30, count 2 2006.281.08:24:22.42#ibcon#*before return 0, iclass 30, count 2 2006.281.08:24:22.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:22.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.281.08:24:22.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.281.08:24:22.42#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:22.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:22.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:22.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:22.55#ibcon#enter wrdev, iclass 30, count 0 2006.281.08:24:22.55#ibcon#first serial, iclass 30, count 0 2006.281.08:24:22.55#ibcon#enter sib2, iclass 30, count 0 2006.281.08:24:22.55#ibcon#flushed, iclass 30, count 0 2006.281.08:24:22.55#ibcon#about to write, iclass 30, count 0 2006.281.08:24:22.55#ibcon#wrote, iclass 30, count 0 2006.281.08:24:22.55#ibcon#about to read 3, iclass 30, count 0 2006.281.08:24:22.56#ibcon#read 3, iclass 30, count 0 2006.281.08:24:22.56#ibcon#about to read 4, iclass 30, count 0 2006.281.08:24:22.56#ibcon#read 4, iclass 30, count 0 2006.281.08:24:22.56#ibcon#about to read 5, iclass 30, count 0 2006.281.08:24:22.56#ibcon#read 5, iclass 30, count 0 2006.281.08:24:22.56#ibcon#about to read 6, iclass 30, count 0 2006.281.08:24:22.56#ibcon#read 6, iclass 30, count 0 2006.281.08:24:22.56#ibcon#end of sib2, iclass 30, count 0 2006.281.08:24:22.56#ibcon#*mode == 0, iclass 30, count 0 2006.281.08:24:22.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.281.08:24:22.56#ibcon#[27=USB\r\n] 2006.281.08:24:22.56#ibcon#*before write, iclass 30, count 0 2006.281.08:24:22.56#ibcon#enter sib2, iclass 30, count 0 2006.281.08:24:22.56#ibcon#flushed, iclass 30, count 0 2006.281.08:24:22.56#ibcon#about to write, iclass 30, count 0 2006.281.08:24:22.56#ibcon#wrote, iclass 30, count 0 2006.281.08:24:22.56#ibcon#about to read 3, iclass 30, count 0 2006.281.08:24:22.59#ibcon#read 3, iclass 30, count 0 2006.281.08:24:22.59#ibcon#about to read 4, iclass 30, count 0 2006.281.08:24:22.59#ibcon#read 4, iclass 30, count 0 2006.281.08:24:22.59#ibcon#about to read 5, iclass 30, count 0 2006.281.08:24:22.59#ibcon#read 5, iclass 30, count 0 2006.281.08:24:22.59#ibcon#about to read 6, iclass 30, count 0 2006.281.08:24:22.59#ibcon#read 6, iclass 30, count 0 2006.281.08:24:22.59#ibcon#end of sib2, iclass 30, count 0 2006.281.08:24:22.59#ibcon#*after write, iclass 30, count 0 2006.281.08:24:22.59#ibcon#*before return 0, iclass 30, count 0 2006.281.08:24:22.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:22.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.281.08:24:22.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.281.08:24:22.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.281.08:24:22.59$vc4f8/vblo=3,656.99 2006.281.08:24:22.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.281.08:24:22.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.281.08:24:22.59#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:22.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:22.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:22.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:22.59#ibcon#enter wrdev, iclass 32, count 0 2006.281.08:24:22.59#ibcon#first serial, iclass 32, count 0 2006.281.08:24:22.59#ibcon#enter sib2, iclass 32, count 0 2006.281.08:24:22.59#ibcon#flushed, iclass 32, count 0 2006.281.08:24:22.59#ibcon#about to write, iclass 32, count 0 2006.281.08:24:22.59#ibcon#wrote, iclass 32, count 0 2006.281.08:24:22.59#ibcon#about to read 3, iclass 32, count 0 2006.281.08:24:22.61#ibcon#read 3, iclass 32, count 0 2006.281.08:24:22.61#ibcon#about to read 4, iclass 32, count 0 2006.281.08:24:22.61#ibcon#read 4, iclass 32, count 0 2006.281.08:24:22.61#ibcon#about to read 5, iclass 32, count 0 2006.281.08:24:22.61#ibcon#read 5, iclass 32, count 0 2006.281.08:24:22.61#ibcon#about to read 6, iclass 32, count 0 2006.281.08:24:22.61#ibcon#read 6, iclass 32, count 0 2006.281.08:24:22.61#ibcon#end of sib2, iclass 32, count 0 2006.281.08:24:22.61#ibcon#*mode == 0, iclass 32, count 0 2006.281.08:24:22.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.281.08:24:22.61#ibcon#[28=FRQ=03,656.99\r\n] 2006.281.08:24:22.61#ibcon#*before write, iclass 32, count 0 2006.281.08:24:22.61#ibcon#enter sib2, iclass 32, count 0 2006.281.08:24:22.61#ibcon#flushed, iclass 32, count 0 2006.281.08:24:22.61#ibcon#about to write, iclass 32, count 0 2006.281.08:24:22.61#ibcon#wrote, iclass 32, count 0 2006.281.08:24:22.61#ibcon#about to read 3, iclass 32, count 0 2006.281.08:24:22.66#ibcon#read 3, iclass 32, count 0 2006.281.08:24:22.66#ibcon#about to read 4, iclass 32, count 0 2006.281.08:24:22.66#ibcon#read 4, iclass 32, count 0 2006.281.08:24:22.66#ibcon#about to read 5, iclass 32, count 0 2006.281.08:24:22.66#ibcon#read 5, iclass 32, count 0 2006.281.08:24:22.66#ibcon#about to read 6, iclass 32, count 0 2006.281.08:24:22.66#ibcon#read 6, iclass 32, count 0 2006.281.08:24:22.66#ibcon#end of sib2, iclass 32, count 0 2006.281.08:24:22.66#ibcon#*after write, iclass 32, count 0 2006.281.08:24:22.66#ibcon#*before return 0, iclass 32, count 0 2006.281.08:24:22.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:22.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.281.08:24:22.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.281.08:24:22.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.281.08:24:22.66$vc4f8/vb=3,4 2006.281.08:24:22.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.281.08:24:22.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.281.08:24:22.66#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:22.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:22.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:22.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:22.70#ibcon#enter wrdev, iclass 34, count 2 2006.281.08:24:22.70#ibcon#first serial, iclass 34, count 2 2006.281.08:24:22.70#ibcon#enter sib2, iclass 34, count 2 2006.281.08:24:22.70#ibcon#flushed, iclass 34, count 2 2006.281.08:24:22.70#ibcon#about to write, iclass 34, count 2 2006.281.08:24:22.70#ibcon#wrote, iclass 34, count 2 2006.281.08:24:22.70#ibcon#about to read 3, iclass 34, count 2 2006.281.08:24:22.72#ibcon#read 3, iclass 34, count 2 2006.281.08:24:22.72#ibcon#about to read 4, iclass 34, count 2 2006.281.08:24:22.72#ibcon#read 4, iclass 34, count 2 2006.281.08:24:22.72#ibcon#about to read 5, iclass 34, count 2 2006.281.08:24:22.72#ibcon#read 5, iclass 34, count 2 2006.281.08:24:22.72#ibcon#about to read 6, iclass 34, count 2 2006.281.08:24:22.72#ibcon#read 6, iclass 34, count 2 2006.281.08:24:22.72#ibcon#end of sib2, iclass 34, count 2 2006.281.08:24:22.72#ibcon#*mode == 0, iclass 34, count 2 2006.281.08:24:22.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.281.08:24:22.72#ibcon#[27=AT03-04\r\n] 2006.281.08:24:22.72#ibcon#*before write, iclass 34, count 2 2006.281.08:24:22.72#ibcon#enter sib2, iclass 34, count 2 2006.281.08:24:22.72#ibcon#flushed, iclass 34, count 2 2006.281.08:24:22.72#ibcon#about to write, iclass 34, count 2 2006.281.08:24:22.72#ibcon#wrote, iclass 34, count 2 2006.281.08:24:22.72#ibcon#about to read 3, iclass 34, count 2 2006.281.08:24:22.75#ibcon#read 3, iclass 34, count 2 2006.281.08:24:22.75#ibcon#about to read 4, iclass 34, count 2 2006.281.08:24:22.75#ibcon#read 4, iclass 34, count 2 2006.281.08:24:22.75#ibcon#about to read 5, iclass 34, count 2 2006.281.08:24:22.75#ibcon#read 5, iclass 34, count 2 2006.281.08:24:22.75#ibcon#about to read 6, iclass 34, count 2 2006.281.08:24:22.75#ibcon#read 6, iclass 34, count 2 2006.281.08:24:22.75#ibcon#end of sib2, iclass 34, count 2 2006.281.08:24:22.75#ibcon#*after write, iclass 34, count 2 2006.281.08:24:22.75#ibcon#*before return 0, iclass 34, count 2 2006.281.08:24:22.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:22.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.281.08:24:22.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.281.08:24:22.75#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:22.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:22.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:22.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:22.87#ibcon#enter wrdev, iclass 34, count 0 2006.281.08:24:22.87#ibcon#first serial, iclass 34, count 0 2006.281.08:24:22.87#ibcon#enter sib2, iclass 34, count 0 2006.281.08:24:22.87#ibcon#flushed, iclass 34, count 0 2006.281.08:24:22.87#ibcon#about to write, iclass 34, count 0 2006.281.08:24:22.87#ibcon#wrote, iclass 34, count 0 2006.281.08:24:22.87#ibcon#about to read 3, iclass 34, count 0 2006.281.08:24:22.89#ibcon#read 3, iclass 34, count 0 2006.281.08:24:22.89#ibcon#about to read 4, iclass 34, count 0 2006.281.08:24:22.89#ibcon#read 4, iclass 34, count 0 2006.281.08:24:22.89#ibcon#about to read 5, iclass 34, count 0 2006.281.08:24:22.89#ibcon#read 5, iclass 34, count 0 2006.281.08:24:22.89#ibcon#about to read 6, iclass 34, count 0 2006.281.08:24:22.89#ibcon#read 6, iclass 34, count 0 2006.281.08:24:22.89#ibcon#end of sib2, iclass 34, count 0 2006.281.08:24:22.89#ibcon#*mode == 0, iclass 34, count 0 2006.281.08:24:22.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.281.08:24:22.89#ibcon#[27=USB\r\n] 2006.281.08:24:22.89#ibcon#*before write, iclass 34, count 0 2006.281.08:24:22.89#ibcon#enter sib2, iclass 34, count 0 2006.281.08:24:22.89#ibcon#flushed, iclass 34, count 0 2006.281.08:24:22.89#ibcon#about to write, iclass 34, count 0 2006.281.08:24:22.89#ibcon#wrote, iclass 34, count 0 2006.281.08:24:22.89#ibcon#about to read 3, iclass 34, count 0 2006.281.08:24:22.93#ibcon#read 3, iclass 34, count 0 2006.281.08:24:22.93#ibcon#about to read 4, iclass 34, count 0 2006.281.08:24:22.93#ibcon#read 4, iclass 34, count 0 2006.281.08:24:22.93#ibcon#about to read 5, iclass 34, count 0 2006.281.08:24:22.93#ibcon#read 5, iclass 34, count 0 2006.281.08:24:22.93#ibcon#about to read 6, iclass 34, count 0 2006.281.08:24:22.93#ibcon#read 6, iclass 34, count 0 2006.281.08:24:22.93#ibcon#end of sib2, iclass 34, count 0 2006.281.08:24:22.93#ibcon#*after write, iclass 34, count 0 2006.281.08:24:22.93#ibcon#*before return 0, iclass 34, count 0 2006.281.08:24:22.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:22.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.281.08:24:22.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.281.08:24:22.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.281.08:24:22.93$vc4f8/vblo=4,712.99 2006.281.08:24:22.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.281.08:24:22.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.281.08:24:22.93#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:22.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:22.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:22.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:22.93#ibcon#enter wrdev, iclass 36, count 0 2006.281.08:24:22.93#ibcon#first serial, iclass 36, count 0 2006.281.08:24:22.93#ibcon#enter sib2, iclass 36, count 0 2006.281.08:24:22.93#ibcon#flushed, iclass 36, count 0 2006.281.08:24:22.93#ibcon#about to write, iclass 36, count 0 2006.281.08:24:22.93#ibcon#wrote, iclass 36, count 0 2006.281.08:24:22.93#ibcon#about to read 3, iclass 36, count 0 2006.281.08:24:22.94#ibcon#read 3, iclass 36, count 0 2006.281.08:24:22.94#ibcon#about to read 4, iclass 36, count 0 2006.281.08:24:22.94#ibcon#read 4, iclass 36, count 0 2006.281.08:24:22.94#ibcon#about to read 5, iclass 36, count 0 2006.281.08:24:22.94#ibcon#read 5, iclass 36, count 0 2006.281.08:24:22.94#ibcon#about to read 6, iclass 36, count 0 2006.281.08:24:22.94#ibcon#read 6, iclass 36, count 0 2006.281.08:24:22.94#ibcon#end of sib2, iclass 36, count 0 2006.281.08:24:22.94#ibcon#*mode == 0, iclass 36, count 0 2006.281.08:24:22.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.281.08:24:22.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.281.08:24:22.94#ibcon#*before write, iclass 36, count 0 2006.281.08:24:22.94#ibcon#enter sib2, iclass 36, count 0 2006.281.08:24:22.94#ibcon#flushed, iclass 36, count 0 2006.281.08:24:22.94#ibcon#about to write, iclass 36, count 0 2006.281.08:24:22.96#ibcon#wrote, iclass 36, count 0 2006.281.08:24:22.96#ibcon#about to read 3, iclass 36, count 0 2006.281.08:24:23.00#ibcon#read 3, iclass 36, count 0 2006.281.08:24:23.00#ibcon#about to read 4, iclass 36, count 0 2006.281.08:24:23.00#ibcon#read 4, iclass 36, count 0 2006.281.08:24:23.00#ibcon#about to read 5, iclass 36, count 0 2006.281.08:24:23.00#ibcon#read 5, iclass 36, count 0 2006.281.08:24:23.00#ibcon#about to read 6, iclass 36, count 0 2006.281.08:24:23.00#ibcon#read 6, iclass 36, count 0 2006.281.08:24:23.00#ibcon#end of sib2, iclass 36, count 0 2006.281.08:24:23.00#ibcon#*after write, iclass 36, count 0 2006.281.08:24:23.00#ibcon#*before return 0, iclass 36, count 0 2006.281.08:24:23.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:23.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.281.08:24:23.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.281.08:24:23.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.281.08:24:23.00$vc4f8/vb=4,4 2006.281.08:24:23.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.281.08:24:23.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.281.08:24:23.00#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:23.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:23.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:23.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:23.05#ibcon#enter wrdev, iclass 38, count 2 2006.281.08:24:23.05#ibcon#first serial, iclass 38, count 2 2006.281.08:24:23.05#ibcon#enter sib2, iclass 38, count 2 2006.281.08:24:23.05#ibcon#flushed, iclass 38, count 2 2006.281.08:24:23.05#ibcon#about to write, iclass 38, count 2 2006.281.08:24:23.05#ibcon#wrote, iclass 38, count 2 2006.281.08:24:23.05#ibcon#about to read 3, iclass 38, count 2 2006.281.08:24:23.07#ibcon#read 3, iclass 38, count 2 2006.281.08:24:23.07#ibcon#about to read 4, iclass 38, count 2 2006.281.08:24:23.07#ibcon#read 4, iclass 38, count 2 2006.281.08:24:23.07#ibcon#about to read 5, iclass 38, count 2 2006.281.08:24:23.07#ibcon#read 5, iclass 38, count 2 2006.281.08:24:23.07#ibcon#about to read 6, iclass 38, count 2 2006.281.08:24:23.07#ibcon#read 6, iclass 38, count 2 2006.281.08:24:23.07#ibcon#end of sib2, iclass 38, count 2 2006.281.08:24:23.07#ibcon#*mode == 0, iclass 38, count 2 2006.281.08:24:23.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.281.08:24:23.07#ibcon#[27=AT04-04\r\n] 2006.281.08:24:23.07#ibcon#*before write, iclass 38, count 2 2006.281.08:24:23.07#ibcon#enter sib2, iclass 38, count 2 2006.281.08:24:23.07#ibcon#flushed, iclass 38, count 2 2006.281.08:24:23.07#ibcon#about to write, iclass 38, count 2 2006.281.08:24:23.07#ibcon#wrote, iclass 38, count 2 2006.281.08:24:23.07#ibcon#about to read 3, iclass 38, count 2 2006.281.08:24:23.10#ibcon#read 3, iclass 38, count 2 2006.281.08:24:23.10#ibcon#about to read 4, iclass 38, count 2 2006.281.08:24:23.10#ibcon#read 4, iclass 38, count 2 2006.281.08:24:23.10#ibcon#about to read 5, iclass 38, count 2 2006.281.08:24:23.10#ibcon#read 5, iclass 38, count 2 2006.281.08:24:23.10#ibcon#about to read 6, iclass 38, count 2 2006.281.08:24:23.10#ibcon#read 6, iclass 38, count 2 2006.281.08:24:23.10#ibcon#end of sib2, iclass 38, count 2 2006.281.08:24:23.10#ibcon#*after write, iclass 38, count 2 2006.281.08:24:23.10#ibcon#*before return 0, iclass 38, count 2 2006.281.08:24:23.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:23.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.281.08:24:23.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.281.08:24:23.10#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:23.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:23.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:23.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:23.22#ibcon#enter wrdev, iclass 38, count 0 2006.281.08:24:23.22#ibcon#first serial, iclass 38, count 0 2006.281.08:24:23.22#ibcon#enter sib2, iclass 38, count 0 2006.281.08:24:23.22#ibcon#flushed, iclass 38, count 0 2006.281.08:24:23.22#ibcon#about to write, iclass 38, count 0 2006.281.08:24:23.22#ibcon#wrote, iclass 38, count 0 2006.281.08:24:23.22#ibcon#about to read 3, iclass 38, count 0 2006.281.08:24:23.24#ibcon#read 3, iclass 38, count 0 2006.281.08:24:23.24#ibcon#about to read 4, iclass 38, count 0 2006.281.08:24:23.24#ibcon#read 4, iclass 38, count 0 2006.281.08:24:23.24#ibcon#about to read 5, iclass 38, count 0 2006.281.08:24:23.24#ibcon#read 5, iclass 38, count 0 2006.281.08:24:23.24#ibcon#about to read 6, iclass 38, count 0 2006.281.08:24:23.24#ibcon#read 6, iclass 38, count 0 2006.281.08:24:23.24#ibcon#end of sib2, iclass 38, count 0 2006.281.08:24:23.24#ibcon#*mode == 0, iclass 38, count 0 2006.281.08:24:23.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.281.08:24:23.24#ibcon#[27=USB\r\n] 2006.281.08:24:23.24#ibcon#*before write, iclass 38, count 0 2006.281.08:24:23.24#ibcon#enter sib2, iclass 38, count 0 2006.281.08:24:23.24#ibcon#flushed, iclass 38, count 0 2006.281.08:24:23.24#ibcon#about to write, iclass 38, count 0 2006.281.08:24:23.24#ibcon#wrote, iclass 38, count 0 2006.281.08:24:23.24#ibcon#about to read 3, iclass 38, count 0 2006.281.08:24:23.27#ibcon#read 3, iclass 38, count 0 2006.281.08:24:23.27#ibcon#about to read 4, iclass 38, count 0 2006.281.08:24:23.27#ibcon#read 4, iclass 38, count 0 2006.281.08:24:23.27#ibcon#about to read 5, iclass 38, count 0 2006.281.08:24:23.27#ibcon#read 5, iclass 38, count 0 2006.281.08:24:23.27#ibcon#about to read 6, iclass 38, count 0 2006.281.08:24:23.27#ibcon#read 6, iclass 38, count 0 2006.281.08:24:23.27#ibcon#end of sib2, iclass 38, count 0 2006.281.08:24:23.27#ibcon#*after write, iclass 38, count 0 2006.281.08:24:23.27#ibcon#*before return 0, iclass 38, count 0 2006.281.08:24:23.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:23.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.281.08:24:23.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.281.08:24:23.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.281.08:24:23.27$vc4f8/vblo=5,744.99 2006.281.08:24:23.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.281.08:24:23.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.281.08:24:23.27#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:23.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:23.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:23.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:23.27#ibcon#enter wrdev, iclass 40, count 0 2006.281.08:24:23.27#ibcon#first serial, iclass 40, count 0 2006.281.08:24:23.27#ibcon#enter sib2, iclass 40, count 0 2006.281.08:24:23.27#ibcon#flushed, iclass 40, count 0 2006.281.08:24:23.27#ibcon#about to write, iclass 40, count 0 2006.281.08:24:23.27#ibcon#wrote, iclass 40, count 0 2006.281.08:24:23.27#ibcon#about to read 3, iclass 40, count 0 2006.281.08:24:23.29#ibcon#read 3, iclass 40, count 0 2006.281.08:24:23.29#ibcon#about to read 4, iclass 40, count 0 2006.281.08:24:23.29#ibcon#read 4, iclass 40, count 0 2006.281.08:24:23.29#ibcon#about to read 5, iclass 40, count 0 2006.281.08:24:23.29#ibcon#read 5, iclass 40, count 0 2006.281.08:24:23.29#ibcon#about to read 6, iclass 40, count 0 2006.281.08:24:23.29#ibcon#read 6, iclass 40, count 0 2006.281.08:24:23.29#ibcon#end of sib2, iclass 40, count 0 2006.281.08:24:23.29#ibcon#*mode == 0, iclass 40, count 0 2006.281.08:24:23.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.281.08:24:23.29#ibcon#[28=FRQ=05,744.99\r\n] 2006.281.08:24:23.29#ibcon#*before write, iclass 40, count 0 2006.281.08:24:23.29#ibcon#enter sib2, iclass 40, count 0 2006.281.08:24:23.29#ibcon#flushed, iclass 40, count 0 2006.281.08:24:23.29#ibcon#about to write, iclass 40, count 0 2006.281.08:24:23.29#ibcon#wrote, iclass 40, count 0 2006.281.08:24:23.29#ibcon#about to read 3, iclass 40, count 0 2006.281.08:24:23.33#ibcon#read 3, iclass 40, count 0 2006.281.08:24:23.33#ibcon#about to read 4, iclass 40, count 0 2006.281.08:24:23.33#ibcon#read 4, iclass 40, count 0 2006.281.08:24:23.33#ibcon#about to read 5, iclass 40, count 0 2006.281.08:24:23.33#ibcon#read 5, iclass 40, count 0 2006.281.08:24:23.33#ibcon#about to read 6, iclass 40, count 0 2006.281.08:24:23.33#ibcon#read 6, iclass 40, count 0 2006.281.08:24:23.33#ibcon#end of sib2, iclass 40, count 0 2006.281.08:24:23.33#ibcon#*after write, iclass 40, count 0 2006.281.08:24:23.33#ibcon#*before return 0, iclass 40, count 0 2006.281.08:24:23.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:23.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.281.08:24:23.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.281.08:24:23.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.281.08:24:23.33$vc4f8/vb=5,4 2006.281.08:24:23.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.281.08:24:23.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.281.08:24:23.33#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:23.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:23.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:23.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:23.39#ibcon#enter wrdev, iclass 4, count 2 2006.281.08:24:23.39#ibcon#first serial, iclass 4, count 2 2006.281.08:24:23.39#ibcon#enter sib2, iclass 4, count 2 2006.281.08:24:23.39#ibcon#flushed, iclass 4, count 2 2006.281.08:24:23.39#ibcon#about to write, iclass 4, count 2 2006.281.08:24:23.39#ibcon#wrote, iclass 4, count 2 2006.281.08:24:23.39#ibcon#about to read 3, iclass 4, count 2 2006.281.08:24:23.42#ibcon#read 3, iclass 4, count 2 2006.281.08:24:23.42#ibcon#about to read 4, iclass 4, count 2 2006.281.08:24:23.42#ibcon#read 4, iclass 4, count 2 2006.281.08:24:23.42#ibcon#about to read 5, iclass 4, count 2 2006.281.08:24:23.42#ibcon#read 5, iclass 4, count 2 2006.281.08:24:23.42#ibcon#about to read 6, iclass 4, count 2 2006.281.08:24:23.42#ibcon#read 6, iclass 4, count 2 2006.281.08:24:23.42#ibcon#end of sib2, iclass 4, count 2 2006.281.08:24:23.42#ibcon#*mode == 0, iclass 4, count 2 2006.281.08:24:23.42#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.281.08:24:23.42#ibcon#[27=AT05-04\r\n] 2006.281.08:24:23.42#ibcon#*before write, iclass 4, count 2 2006.281.08:24:23.42#ibcon#enter sib2, iclass 4, count 2 2006.281.08:24:23.42#ibcon#flushed, iclass 4, count 2 2006.281.08:24:23.42#ibcon#about to write, iclass 4, count 2 2006.281.08:24:23.42#ibcon#wrote, iclass 4, count 2 2006.281.08:24:23.42#ibcon#about to read 3, iclass 4, count 2 2006.281.08:24:23.45#ibcon#read 3, iclass 4, count 2 2006.281.08:24:23.45#ibcon#about to read 4, iclass 4, count 2 2006.281.08:24:23.45#ibcon#read 4, iclass 4, count 2 2006.281.08:24:23.45#ibcon#about to read 5, iclass 4, count 2 2006.281.08:24:23.45#ibcon#read 5, iclass 4, count 2 2006.281.08:24:23.45#ibcon#about to read 6, iclass 4, count 2 2006.281.08:24:23.45#ibcon#read 6, iclass 4, count 2 2006.281.08:24:23.45#ibcon#end of sib2, iclass 4, count 2 2006.281.08:24:23.45#ibcon#*after write, iclass 4, count 2 2006.281.08:24:23.45#ibcon#*before return 0, iclass 4, count 2 2006.281.08:24:23.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:23.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.281.08:24:23.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.281.08:24:23.45#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:23.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:23.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:23.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:23.57#ibcon#enter wrdev, iclass 4, count 0 2006.281.08:24:23.57#ibcon#first serial, iclass 4, count 0 2006.281.08:24:23.57#ibcon#enter sib2, iclass 4, count 0 2006.281.08:24:23.57#ibcon#flushed, iclass 4, count 0 2006.281.08:24:23.57#ibcon#about to write, iclass 4, count 0 2006.281.08:24:23.57#ibcon#wrote, iclass 4, count 0 2006.281.08:24:23.57#ibcon#about to read 3, iclass 4, count 0 2006.281.08:24:23.59#ibcon#read 3, iclass 4, count 0 2006.281.08:24:23.59#ibcon#about to read 4, iclass 4, count 0 2006.281.08:24:23.59#ibcon#read 4, iclass 4, count 0 2006.281.08:24:23.59#ibcon#about to read 5, iclass 4, count 0 2006.281.08:24:23.59#ibcon#read 5, iclass 4, count 0 2006.281.08:24:23.59#ibcon#about to read 6, iclass 4, count 0 2006.281.08:24:23.59#ibcon#read 6, iclass 4, count 0 2006.281.08:24:23.59#ibcon#end of sib2, iclass 4, count 0 2006.281.08:24:23.59#ibcon#*mode == 0, iclass 4, count 0 2006.281.08:24:23.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.281.08:24:23.59#ibcon#[27=USB\r\n] 2006.281.08:24:23.59#ibcon#*before write, iclass 4, count 0 2006.281.08:24:23.59#ibcon#enter sib2, iclass 4, count 0 2006.281.08:24:23.59#ibcon#flushed, iclass 4, count 0 2006.281.08:24:23.59#ibcon#about to write, iclass 4, count 0 2006.281.08:24:23.59#ibcon#wrote, iclass 4, count 0 2006.281.08:24:23.59#ibcon#about to read 3, iclass 4, count 0 2006.281.08:24:23.62#ibcon#read 3, iclass 4, count 0 2006.281.08:24:23.62#ibcon#about to read 4, iclass 4, count 0 2006.281.08:24:23.62#ibcon#read 4, iclass 4, count 0 2006.281.08:24:23.62#ibcon#about to read 5, iclass 4, count 0 2006.281.08:24:23.62#ibcon#read 5, iclass 4, count 0 2006.281.08:24:23.62#ibcon#about to read 6, iclass 4, count 0 2006.281.08:24:23.62#ibcon#read 6, iclass 4, count 0 2006.281.08:24:23.62#ibcon#end of sib2, iclass 4, count 0 2006.281.08:24:23.62#ibcon#*after write, iclass 4, count 0 2006.281.08:24:23.62#ibcon#*before return 0, iclass 4, count 0 2006.281.08:24:23.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:23.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.281.08:24:23.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.281.08:24:23.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.281.08:24:23.62$vc4f8/vblo=6,752.99 2006.281.08:24:23.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.281.08:24:23.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.281.08:24:23.62#ibcon#ireg 17 cls_cnt 0 2006.281.08:24:23.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:23.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:23.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:23.62#ibcon#enter wrdev, iclass 6, count 0 2006.281.08:24:23.62#ibcon#first serial, iclass 6, count 0 2006.281.08:24:23.62#ibcon#enter sib2, iclass 6, count 0 2006.281.08:24:23.62#ibcon#flushed, iclass 6, count 0 2006.281.08:24:23.62#ibcon#about to write, iclass 6, count 0 2006.281.08:24:23.62#ibcon#wrote, iclass 6, count 0 2006.281.08:24:23.62#ibcon#about to read 3, iclass 6, count 0 2006.281.08:24:23.64#ibcon#read 3, iclass 6, count 0 2006.281.08:24:23.64#ibcon#about to read 4, iclass 6, count 0 2006.281.08:24:23.64#ibcon#read 4, iclass 6, count 0 2006.281.08:24:23.64#ibcon#about to read 5, iclass 6, count 0 2006.281.08:24:23.64#ibcon#read 5, iclass 6, count 0 2006.281.08:24:23.64#ibcon#about to read 6, iclass 6, count 0 2006.281.08:24:23.64#ibcon#read 6, iclass 6, count 0 2006.281.08:24:23.64#ibcon#end of sib2, iclass 6, count 0 2006.281.08:24:23.64#ibcon#*mode == 0, iclass 6, count 0 2006.281.08:24:23.64#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.281.08:24:23.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.281.08:24:23.64#ibcon#*before write, iclass 6, count 0 2006.281.08:24:23.64#ibcon#enter sib2, iclass 6, count 0 2006.281.08:24:23.64#ibcon#flushed, iclass 6, count 0 2006.281.08:24:23.64#ibcon#about to write, iclass 6, count 0 2006.281.08:24:23.64#ibcon#wrote, iclass 6, count 0 2006.281.08:24:23.64#ibcon#about to read 3, iclass 6, count 0 2006.281.08:24:23.68#ibcon#read 3, iclass 6, count 0 2006.281.08:24:23.68#ibcon#about to read 4, iclass 6, count 0 2006.281.08:24:23.68#ibcon#read 4, iclass 6, count 0 2006.281.08:24:23.68#ibcon#about to read 5, iclass 6, count 0 2006.281.08:24:23.68#ibcon#read 5, iclass 6, count 0 2006.281.08:24:23.68#ibcon#about to read 6, iclass 6, count 0 2006.281.08:24:23.68#ibcon#read 6, iclass 6, count 0 2006.281.08:24:23.68#ibcon#end of sib2, iclass 6, count 0 2006.281.08:24:23.68#ibcon#*after write, iclass 6, count 0 2006.281.08:24:23.68#ibcon#*before return 0, iclass 6, count 0 2006.281.08:24:23.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:23.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.281.08:24:23.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.281.08:24:23.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.281.08:24:23.68$vc4f8/vb=6,4 2006.281.08:24:23.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.281.08:24:23.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.281.08:24:23.69#ibcon#ireg 11 cls_cnt 2 2006.281.08:24:23.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:23.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:23.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:23.74#ibcon#enter wrdev, iclass 10, count 2 2006.281.08:24:23.74#ibcon#first serial, iclass 10, count 2 2006.281.08:24:23.74#ibcon#enter sib2, iclass 10, count 2 2006.281.08:24:23.74#ibcon#flushed, iclass 10, count 2 2006.281.08:24:23.74#ibcon#about to write, iclass 10, count 2 2006.281.08:24:23.74#ibcon#wrote, iclass 10, count 2 2006.281.08:24:23.74#ibcon#about to read 3, iclass 10, count 2 2006.281.08:24:23.76#ibcon#read 3, iclass 10, count 2 2006.281.08:24:23.76#ibcon#about to read 4, iclass 10, count 2 2006.281.08:24:23.76#ibcon#read 4, iclass 10, count 2 2006.281.08:24:23.76#ibcon#about to read 5, iclass 10, count 2 2006.281.08:24:23.76#ibcon#read 5, iclass 10, count 2 2006.281.08:24:23.76#ibcon#about to read 6, iclass 10, count 2 2006.281.08:24:23.76#ibcon#read 6, iclass 10, count 2 2006.281.08:24:23.76#ibcon#end of sib2, iclass 10, count 2 2006.281.08:24:23.76#ibcon#*mode == 0, iclass 10, count 2 2006.281.08:24:23.76#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.281.08:24:23.76#ibcon#[27=AT06-04\r\n] 2006.281.08:24:23.76#ibcon#*before write, iclass 10, count 2 2006.281.08:24:23.76#ibcon#enter sib2, iclass 10, count 2 2006.281.08:24:23.76#ibcon#flushed, iclass 10, count 2 2006.281.08:24:23.76#ibcon#about to write, iclass 10, count 2 2006.281.08:24:23.76#ibcon#wrote, iclass 10, count 2 2006.281.08:24:23.76#ibcon#about to read 3, iclass 10, count 2 2006.281.08:24:23.79#ibcon#read 3, iclass 10, count 2 2006.281.08:24:23.79#ibcon#about to read 4, iclass 10, count 2 2006.281.08:24:23.79#ibcon#read 4, iclass 10, count 2 2006.281.08:24:23.79#ibcon#about to read 5, iclass 10, count 2 2006.281.08:24:23.79#ibcon#read 5, iclass 10, count 2 2006.281.08:24:23.79#ibcon#about to read 6, iclass 10, count 2 2006.281.08:24:23.79#ibcon#read 6, iclass 10, count 2 2006.281.08:24:23.79#ibcon#end of sib2, iclass 10, count 2 2006.281.08:24:23.79#ibcon#*after write, iclass 10, count 2 2006.281.08:24:23.79#ibcon#*before return 0, iclass 10, count 2 2006.281.08:24:23.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:23.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.281.08:24:23.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.281.08:24:23.79#ibcon#ireg 7 cls_cnt 0 2006.281.08:24:23.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:23.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:23.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:23.91#ibcon#enter wrdev, iclass 10, count 0 2006.281.08:24:23.91#ibcon#first serial, iclass 10, count 0 2006.281.08:24:23.91#ibcon#enter sib2, iclass 10, count 0 2006.281.08:24:23.91#ibcon#flushed, iclass 10, count 0 2006.281.08:24:23.91#ibcon#about to write, iclass 10, count 0 2006.281.08:24:23.91#ibcon#wrote, iclass 10, count 0 2006.281.08:24:23.91#ibcon#about to read 3, iclass 10, count 0 2006.281.08:24:23.93#ibcon#read 3, iclass 10, count 0 2006.281.08:24:23.93#ibcon#about to read 4, iclass 10, count 0 2006.281.08:24:23.93#ibcon#read 4, iclass 10, count 0 2006.281.08:24:23.93#ibcon#about to read 5, iclass 10, count 0 2006.281.08:24:23.93#ibcon#read 5, iclass 10, count 0 2006.281.08:24:23.93#ibcon#about to read 6, iclass 10, count 0 2006.281.08:24:23.93#ibcon#read 6, iclass 10, count 0 2006.281.08:24:23.93#ibcon#end of sib2, iclass 10, count 0 2006.281.08:24:23.93#ibcon#*mode == 0, iclass 10, count 0 2006.281.08:24:23.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.281.08:24:23.93#ibcon#[27=USB\r\n] 2006.281.08:24:23.93#ibcon#*before write, iclass 10, count 0 2006.281.08:24:23.93#ibcon#enter sib2, iclass 10, count 0 2006.281.08:24:23.93#ibcon#flushed, iclass 10, count 0 2006.281.08:24:23.93#ibcon#about to write, iclass 10, count 0 2006.281.08:24:23.93#ibcon#wrote, iclass 10, count 0 2006.281.08:24:23.93#ibcon#about to read 3, iclass 10, count 0 2006.281.08:24:23.96#ibcon#read 3, iclass 10, count 0 2006.281.08:24:23.96#ibcon#about to read 4, iclass 10, count 0 2006.281.08:24:23.96#ibcon#read 4, iclass 10, count 0 2006.281.08:24:23.96#ibcon#about to read 5, iclass 10, count 0 2006.281.08:24:23.96#ibcon#read 5, iclass 10, count 0 2006.281.08:24:23.96#ibcon#about to read 6, iclass 10, count 0 2006.281.08:24:23.96#ibcon#read 6, iclass 10, count 0 2006.281.08:24:23.96#ibcon#end of sib2, iclass 10, count 0 2006.281.08:24:23.96#ibcon#*after write, iclass 10, count 0 2006.281.08:24:23.96#ibcon#*before return 0, iclass 10, count 0 2006.281.08:24:23.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:23.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.281.08:24:23.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.281.08:24:23.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.281.08:24:23.96$vc4f8/vabw=wide 2006.281.08:24:23.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.281.08:24:23.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.281.08:24:23.96#ibcon#ireg 8 cls_cnt 0 2006.281.08:24:23.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:23.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:23.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:23.96#ibcon#enter wrdev, iclass 12, count 0 2006.281.08:24:23.96#ibcon#first serial, iclass 12, count 0 2006.281.08:24:23.96#ibcon#enter sib2, iclass 12, count 0 2006.281.08:24:23.96#ibcon#flushed, iclass 12, count 0 2006.281.08:24:23.96#ibcon#about to write, iclass 12, count 0 2006.281.08:24:23.96#ibcon#wrote, iclass 12, count 0 2006.281.08:24:23.96#ibcon#about to read 3, iclass 12, count 0 2006.281.08:24:23.98#ibcon#read 3, iclass 12, count 0 2006.281.08:24:23.98#ibcon#about to read 4, iclass 12, count 0 2006.281.08:24:23.98#ibcon#read 4, iclass 12, count 0 2006.281.08:24:23.98#ibcon#about to read 5, iclass 12, count 0 2006.281.08:24:23.98#ibcon#read 5, iclass 12, count 0 2006.281.08:24:23.98#ibcon#about to read 6, iclass 12, count 0 2006.281.08:24:23.98#ibcon#read 6, iclass 12, count 0 2006.281.08:24:23.98#ibcon#end of sib2, iclass 12, count 0 2006.281.08:24:23.98#ibcon#*mode == 0, iclass 12, count 0 2006.281.08:24:23.98#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.281.08:24:23.98#ibcon#[25=BW32\r\n] 2006.281.08:24:23.98#ibcon#*before write, iclass 12, count 0 2006.281.08:24:23.98#ibcon#enter sib2, iclass 12, count 0 2006.281.08:24:23.98#ibcon#flushed, iclass 12, count 0 2006.281.08:24:23.98#ibcon#about to write, iclass 12, count 0 2006.281.08:24:23.98#ibcon#wrote, iclass 12, count 0 2006.281.08:24:23.98#ibcon#about to read 3, iclass 12, count 0 2006.281.08:24:24.01#ibcon#read 3, iclass 12, count 0 2006.281.08:24:24.01#ibcon#about to read 4, iclass 12, count 0 2006.281.08:24:24.01#ibcon#read 4, iclass 12, count 0 2006.281.08:24:24.01#ibcon#about to read 5, iclass 12, count 0 2006.281.08:24:24.01#ibcon#read 5, iclass 12, count 0 2006.281.08:24:24.01#ibcon#about to read 6, iclass 12, count 0 2006.281.08:24:24.01#ibcon#read 6, iclass 12, count 0 2006.281.08:24:24.01#ibcon#end of sib2, iclass 12, count 0 2006.281.08:24:24.01#ibcon#*after write, iclass 12, count 0 2006.281.08:24:24.01#ibcon#*before return 0, iclass 12, count 0 2006.281.08:24:24.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:24.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.281.08:24:24.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.281.08:24:24.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.281.08:24:24.01$vc4f8/vbbw=wide 2006.281.08:24:24.01#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.281.08:24:24.01#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.281.08:24:24.01#ibcon#ireg 8 cls_cnt 0 2006.281.08:24:24.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:24:24.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:24:24.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:24:24.08#ibcon#enter wrdev, iclass 14, count 0 2006.281.08:24:24.08#ibcon#first serial, iclass 14, count 0 2006.281.08:24:24.08#ibcon#enter sib2, iclass 14, count 0 2006.281.08:24:24.08#ibcon#flushed, iclass 14, count 0 2006.281.08:24:24.08#ibcon#about to write, iclass 14, count 0 2006.281.08:24:24.08#ibcon#wrote, iclass 14, count 0 2006.281.08:24:24.08#ibcon#about to read 3, iclass 14, count 0 2006.281.08:24:24.10#ibcon#read 3, iclass 14, count 0 2006.281.08:24:24.10#ibcon#about to read 4, iclass 14, count 0 2006.281.08:24:24.10#ibcon#read 4, iclass 14, count 0 2006.281.08:24:24.10#ibcon#about to read 5, iclass 14, count 0 2006.281.08:24:24.10#ibcon#read 5, iclass 14, count 0 2006.281.08:24:24.10#ibcon#about to read 6, iclass 14, count 0 2006.281.08:24:24.10#ibcon#read 6, iclass 14, count 0 2006.281.08:24:24.10#ibcon#end of sib2, iclass 14, count 0 2006.281.08:24:24.10#ibcon#*mode == 0, iclass 14, count 0 2006.281.08:24:24.10#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.281.08:24:24.10#ibcon#[27=BW32\r\n] 2006.281.08:24:24.10#ibcon#*before write, iclass 14, count 0 2006.281.08:24:24.10#ibcon#enter sib2, iclass 14, count 0 2006.281.08:24:24.10#ibcon#flushed, iclass 14, count 0 2006.281.08:24:24.10#ibcon#about to write, iclass 14, count 0 2006.281.08:24:24.10#ibcon#wrote, iclass 14, count 0 2006.281.08:24:24.10#ibcon#about to read 3, iclass 14, count 0 2006.281.08:24:24.13#ibcon#read 3, iclass 14, count 0 2006.281.08:24:24.13#ibcon#about to read 4, iclass 14, count 0 2006.281.08:24:24.13#ibcon#read 4, iclass 14, count 0 2006.281.08:24:24.13#ibcon#about to read 5, iclass 14, count 0 2006.281.08:24:24.13#ibcon#read 5, iclass 14, count 0 2006.281.08:24:24.13#ibcon#about to read 6, iclass 14, count 0 2006.281.08:24:24.13#ibcon#read 6, iclass 14, count 0 2006.281.08:24:24.13#ibcon#end of sib2, iclass 14, count 0 2006.281.08:24:24.13#ibcon#*after write, iclass 14, count 0 2006.281.08:24:24.13#ibcon#*before return 0, iclass 14, count 0 2006.281.08:24:24.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:24:24.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.281.08:24:24.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.281.08:24:24.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.281.08:24:24.13$4f8m12a/ifd4f 2006.281.08:24:24.13$ifd4f/lo= 2006.281.08:24:24.13$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.281.08:24:24.13$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.281.08:24:24.13$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.281.08:24:24.13$ifd4f/patch= 2006.281.08:24:24.13$ifd4f/patch=lo1,a1,a2,a3,a4 2006.281.08:24:24.13$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.281.08:24:24.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.281.08:24:24.14$4f8m12a/"form=m,16.000,1:2 2006.281.08:24:24.14$4f8m12a/"tpicd 2006.281.08:24:24.14$4f8m12a/echo=off 2006.281.08:24:24.14$4f8m12a/xlog=off 2006.281.08:24:24.14:!2006.281.08:25:00 2006.281.08:24:41.13#trakl#Source acquired 2006.281.08:24:41.13#flagr#flagr/antenna,acquired 2006.281.08:25:00.01:preob 2006.281.08:25:01.13/onsource/TRACKING 2006.281.08:25:01.13:!2006.281.08:25:10 2006.281.08:25:10.00:data_valid=on 2006.281.08:25:10.00:midob 2006.281.08:25:10.13/onsource/TRACKING 2006.281.08:25:10.13/wx/19.86,1001.9,52 2006.281.08:25:10.31/cable/+6.4886E-03 2006.281.08:25:11.40/va/01,07,usb,yes,32,34 2006.281.08:25:11.40/va/02,06,usb,yes,30,31 2006.281.08:25:11.40/va/03,06,usb,yes,28,28 2006.281.08:25:11.40/va/04,06,usb,yes,31,33 2006.281.08:25:11.40/va/05,07,usb,yes,30,32 2006.281.08:25:11.40/va/06,06,usb,yes,29,29 2006.281.08:25:11.40/va/07,06,usb,yes,29,29 2006.281.08:25:11.40/va/08,06,usb,yes,31,31 2006.281.08:25:11.63/valo/01,532.99,yes,locked 2006.281.08:25:11.63/valo/02,572.99,yes,locked 2006.281.08:25:11.63/valo/03,672.99,yes,locked 2006.281.08:25:11.63/valo/04,832.99,yes,locked 2006.281.08:25:11.63/valo/05,652.99,yes,locked 2006.281.08:25:11.63/valo/06,772.99,yes,locked 2006.281.08:25:11.63/valo/07,832.99,yes,locked 2006.281.08:25:11.63/valo/08,852.99,yes,locked 2006.281.08:25:12.72/vb/01,04,usb,yes,30,29 2006.281.08:25:12.72/vb/02,05,usb,yes,28,29 2006.281.08:25:12.72/vb/03,04,usb,yes,28,32 2006.281.08:25:12.72/vb/04,04,usb,yes,29,29 2006.281.08:25:12.72/vb/05,04,usb,yes,27,31 2006.281.08:25:12.72/vb/06,04,usb,yes,28,31 2006.281.08:25:12.72/vb/07,04,usb,yes,30,30 2006.281.08:25:12.72/vb/08,04,usb,yes,28,31 2006.281.08:25:12.95/vblo/01,632.99,yes,locked 2006.281.08:25:12.95/vblo/02,640.99,yes,locked 2006.281.08:25:12.95/vblo/03,656.99,yes,locked 2006.281.08:25:12.95/vblo/04,712.99,yes,locked 2006.281.08:25:12.95/vblo/05,744.99,yes,locked 2006.281.08:25:12.95/vblo/06,752.99,yes,locked 2006.281.08:25:12.95/vblo/07,734.99,yes,locked 2006.281.08:25:12.95/vblo/08,744.99,yes,locked 2006.281.08:25:13.10/vabw/8 2006.281.08:25:13.25/vbbw/8 2006.281.08:25:13.45/xfe/off,on,12.0 2006.281.08:25:13.82/ifatt/23,28,28,28 2006.281.08:25:14.08/fmout-gps/S +3.13E-07 2006.281.08:25:14.11:!2006.281.08:26:10 2006.281.08:25:35.14#trakl#Off source 2006.281.08:25:35.14?ERROR st -7 Antenna off-source! 2006.281.08:25:35.14#trakl#az 343.527 el 38.674 azerr*cos(el) -0.0084 elerr 0.0214 2006.281.08:25:35.14#flagr#flagr/antenna,off-source 2006.281.08:25:47.14#trakl#Source re-acquired 2006.281.08:25:47.14#flagr#flagr/antenna,re-acquired 2006.281.08:26:10.01:data_valid=off 2006.281.08:26:10.01:postob 2006.281.08:26:10.15/cable/+6.4879E-03 2006.281.08:26:10.15/wx/19.84,1001.9,53 2006.281.08:26:11.07/fmout-gps/S +3.14E-07 2006.281.08:26:11.07:checkk5last 2006.281.08:26:11.08&checkk5last/chk_obsdata=1 2006.281.08:26:11.08&checkk5last/chk_obsdata=2 2006.281.08:26:11.08&checkk5last/chk_obsdata=3 2006.281.08:26:11.09&checkk5last/chk_obsdata=4 2006.281.08:26:11.09&checkk5last/k5log=1 2006.281.08:26:11.09&checkk5last/k5log=2 2006.281.08:26:11.09&checkk5last/k5log=3 2006.281.08:26:11.09&checkk5last/k5log=4 2006.281.08:26:11.09&checkk5last/obsinfo 2006.281.08:26:11.54/chk_obsdata//k5ts1/T2810825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:26:11.99/chk_obsdata//k5ts2/T2810825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:26:12.41/chk_obsdata//k5ts3/T2810825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:26:12.81/chk_obsdata//k5ts4/T2810825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.281.08:26:13.51/k5log//k5ts1_log_newline 2006.281.08:26:14.28/k5log//k5ts2_log_newline 2006.281.08:26:15.25/k5log//k5ts3_log_newline 2006.281.08:26:16.22/k5log//k5ts4_log_newline 2006.281.08:26:16.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.281.08:26:16.24:sched_end 2006.281.08:26:16.24&sched_end/stopcheck 2006.281.08:26:16.24&stopcheck/sy=killall check_fsrun.pl 2006.281.08:26:16.24&stopcheck/" sy=killall chmem.sh 2006.281.08:26:16.33:source=idle 2006.281.08:26:18.14#flagr#flagr/antenna,new-source 2006.281.08:26:18.14:stow 2006.281.08:26:18.15&stow/source=idle 2006.281.08:26:18.15&stow/"this is stow command. 2006.281.08:26:18.15&stow/antenna=m3 2006.281.08:26:22.01:!+10m 2006.281.08:36:22.02:standby 2006.281.08:36:22.02&standby/"this is standby command. 2006.281.08:36:22.02&standby/antenna=m0 2006.281.08:36:23.01:checkk5hdd 2006.281.08:36:23.01&checkk5hdd/chk_hdd=1 2006.281.08:36:23.02&checkk5hdd/chk_hdd=2 2006.281.08:36:23.02&checkk5hdd/chk_hdd=3 2006.281.08:36:23.02&checkk5hdd/chk_hdd=4 2006.281.08:36:26.26/chk_hdd//k5ts1/GSI00287:T281073000a.dat~T281082510a.dat[12961382400Byte] 2006.281.08:36:30.00/chk_hdd//k5ts2/GSI00184:T281073000b.dat~T281082510b.dat[12961382400Byte] 2006.281.08:36:33.97/chk_hdd//k5ts3/GSI00270:T281073000c.dat~T281082510c.dat[12961382400Byte] 2006.281.08:36:37.45/chk_hdd//k5ts4/GSI00242:T281073000d.dat~T281082510d.dat[12961382400Byte] 2006.281.08:36:37.45:sy=cp /usr2/log/k06281ts.log /usr2/log_backup/ 2006.281.08:36:37.53:*end of schedule 2006.281.15:50:49.46?ERROR st -97 Trouble decoding pressure data 2006.281.15:50:49.46#wxget#15 0.4 0.9 13.08 891008.2 2006.282.19:10:49.24?ERROR st -97 Trouble decoding pressure data 2006.282.19:10:49.24#wxget#00 0.1 0.3 12.651001017.6 2006.282.23:45:08.74;unstow 2006.282.23:45:31.68;proc=point 2006.282.23:45:36.97;initp 2006.282.23:45:36.97&initp/"setup 2006.282.23:45:36.97&initp/abib=p2,pr 2006.282.23:45:36.97&initp/abib=p1,pr 2006.282.23:45:36.97&initp/!+1s 2006.282.23:45:36.97&initp/abib=p2,ln 2006.282.23:45:36.97&initp/abib=p2,rm3en 2006.282.23:45:36.97&initp/abib=p2,fm2en 2006.282.23:45:36.97&initp/abib=p2,ap 2006.282.23:45:36.97&initp/abib=p2 2006.282.23:45:36.97&initp/abib=p1,ln 2006.282.23:45:36.97&initp/abib=p1,rm3en 2006.282.23:45:36.97&initp/abib=p1,fm2en 2006.282.23:45:36.97&initp/"meter 1 (u6) has s band 2006.282.23:45:36.97&initp/abib=p1,ap 2006.282.23:45:36.97&initp/abib=p1 2006.282.23:45:36.97&initp/caloff 2006.282.23:45:36.97&initp/user_device=u5,7680,usb,rcp,750 2006.282.23:45:36.97&initp/user_device=u6,1600,usb,rcp,750 2006.282.23:45:36.97&initp/sigon 2006.282.23:45:36.97&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.282.23:45:36.97&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.282.23:45:36.97&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.282.23:45:36.97&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.282.23:45:36.97&initp/" for tsukuba 2006.282.23:45:36.97&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.282.23:45:36.97&initp/fivept=azel,-2,7,.3,1,u5,120 2006.282.23:45:36.97&initp/" sample onoff set-up for mark iii/iv 2006.282.23:45:36.97&initp/"onoff=2,1,75,3,120,all 2006.282.23:45:36.97&initp/" sample onoff set-up for vlba/4 2006.282.23:45:36.97&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.282.23:45:36.97&initp/" for tsukuba 2006.282.23:45:36.97&initp/"onoff=2,1,75,3,120,u5,u6 2006.282.23:45:36.97&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.282.23:45:36.97&initp/onoff=2,1,75,3,60,u5,u6 2006.282.23:45:36.97&initp/check= 2006.282.23:45:36.97&initp/sy=go aquir & 2006.282.23:45:38.99/abib/+0.0520E-03 2006.282.23:45:39.90/abib/+0.0440E-03 2006.282.23:45:39.90&caloff/"rx=*,*,*,*,*,*,off 2006.282.23:45:39.90&sigon/ifatt=23,28,28,28 2006.282.23:45:39.90&sigon/!+2s 2006.282.23:45:45.90;oriona 2006.282.23:45:45.90&oriona/source=oriona,053516.,-052322.,2000. 2006.282.23:45:47.14#flagr#flagr/antenna,new-source 2006.282.23:46:03.09;taurusa 2006.282.23:46:03.09&taurusa/source=taurusa,053432.,+220058,2000. 2006.282.23:46:04.13#flagr#flagr/antenna,new-source 2006.282.23:46:27.14#trakl#Source acquired 2006.282.23:46:29.14#flagr#flagr/antenna,acquired 2006.282.23:47:13.05;onoff 2006.282.23:47:13.05?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.282.23:47:13.05#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.282.23:47:13.05#onoff#APR u5 8430.00 -100. 357.5 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.282.23:47:13.05#onoff#APR u6 2350.00 -100. 773.7 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.282.23:47:14.14#onoff#ORIG 85634.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.282.23:47:15.42#onoff#ONSO 1.3 0.00000 0.00000 u5 118 u6 134 2006.282.23:47:27.42#onoff#OFFS 13.3 0.98119 0.00000 u5 56 u6 46 2006.282.23:47:27.42;sigoffnf 2006.282.23:47:27.43&sigoffnf/sigoff 2006.282.23:47:27.43&sigoffnf/sy=go onoff & 2006.282.23:47:27.43&sigoff/ifatt=81,81,81,81 2006.282.23:47:27.44&sigoff/!+2s 2006.282.23:47:30.87;sigonnf 2006.282.23:47:30.87&sigonnf/sigon 2006.282.23:47:30.88&sigonnf/sy=go onoff & 2006.282.23:47:33.08#onoff#ZERO 16.7 0.98119 0.00000 u5 0 u6 0 2006.282.23:47:42.42#onoff#ONSO 28.3 0.00000 0.00000 u5 110 u6 133 2006.282.23:47:52.37#onoff#OFFS 38.2 -0.98119 -0.00000 u5 56 u6 45 2006.282.23:47:53.14#trakl#Off source 2006.282.23:47:53.14?ERROR st -7 Antenna off-source! 2006.282.23:47:53.14#trakl#az 277.538 el 27.069 azerr*cos(el) -0.0088 elerr -0.0003 2006.282.23:48:02.37#onoff#ONSO 48.2 0.00000 0.00000 u5 116 u6 134 2006.282.23:48:02.37#onoff#SIG u5 0.00 0.00 17.2 0.000 0.000 0.00 2006.282.23:48:02.37#onoff#SIG u6 0.00 0.00 10.0 0.000 0.000 0.00 2006.282.23:48:02.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.282.23:48:02.37#onoff#VAL taurusa 278.4 27.2 u5 5 r 8430.00 1.0000 -100. 341.2 0.000 0.0000 2006.282.23:48:02.37?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.282.23:48:02.37#onoff#VAL taurusa 278.4 27.2 u6 6 r 2350.00 1.0000 -100. 399.3 0.000 0.0000 2006.282.23:48:02.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.282.23:48:58.38;virgoa 2006.282.23:48:58.38&virgoa/source=virgoa,123049.42,+122328.0,2000. 2006.282.23:48:59.13#flagr#flagr/antenna,new-source 2006.282.23:49:57.13#trakl#Source acquired 2006.282.23:49:57.13#flagr#flagr/antenna,acquired 2006.282.23:51:11.58;onoff 2006.282.23:51:11.58#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.282.23:51:11.58#onoff#APR u5 8430.00 -100. 42.6 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.282.23:51:11.58#onoff#APR u6 2350.00 -100. 127.0 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.282.23:51:13.14#onoff#ORIG 85873.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.282.23:51:14.39#onoff#ONSO 1.2 0.00000 0.00000 u5 61 u6 60 2006.282.23:51:26.37#onoff#OFFS 13.2 1.41890 0.00000 u5 53 u6 45 2006.282.23:51:26.37;sigoffnf 2006.282.23:51:29.75;sigonnf 2006.282.23:51:31.94#onoff#ZERO 16.6 1.41890 0.00000 u5 0 u6 0 2006.282.23:51:46.37#onoff#ONSO 33.2 0.00000 0.00000 u5 61 u6 59 2006.282.23:51:59.42#onoff#OFFS 46.3 -1.41890 -0.00000 u5 53 u6 42 2006.282.23:52:11.37#onoff#ONSO 58.2 0.00000 0.00000 u5 62 u6 59 2006.282.23:52:11.37#onoff#SIG u5 0.00 0.00 13.4 0.000 0.000 0.00 2006.282.23:52:11.37#onoff#SIG u6 0.00 0.00 64.5 0.000 0.000 0.00 2006.282.23:52:11.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.282.23:52:11.37#onoff#VAL virgoa 122.0 53.1 u5 5 r 8430.00 1.0000 -100. 271.0 0.000 0.0000 2006.282.23:52:11.37#onoff#VAL virgoa 122.0 53.1 u6 6 r 2350.00 1.0000 -100. 349.0 0.000 0.0000 2006.282.23:52:11.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.282.23:52:59.71;stow 2006.282.23:53:00.14#flagr#flagr/antenna,new-source 2006.282.23:55:29.59;cable 2006.282.23:55:29.68/cable/+6.5117E-03