2006.279.06:46:53.29;Log Opened: Mark IV Field System Version 9.7.7 2006.279.06:46:53.29;location,TSUKUB32,-140.09,36.10,61.0 2006.279.06:46:53.29;horizon1,0.,5.,360. 2006.279.06:46:53.29;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.279.06:46:53.29;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.279.06:46:53.29;drivev11,330,270,no 2006.279.06:46:53.29;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.279.06:46:53.29;drivev13,15.000,268,10.000,10.000,10.000 2006.279.06:46:53.29;drivev21,330,270,no 2006.279.06:46:53.29;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.279.06:46:53.29;drivev23,15.000,268,10.000,10.000,10.000 2006.279.06:46:53.29;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.279.06:46:53.29;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.279.06:46:53.29;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.279.06:46:53.29;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.279.06:46:53.29;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.279.06:46:53.29;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.279.06:46:53.29;time,-0.364,101.533,rate 2006.279.06:46:53.29;flagr,200 2006.279.06:46:53.29:" K06280 2006 TSUKUB32 T Ts 2006.279.06:46:53.29:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.279.06:46:53.29:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.279.06:46:53.29:" 108 TSUKUB32 14 17400 2006.279.06:46:53.29:" drudg version 050216 compiled under FS 9.7.07 2006.279.06:46:53.29:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.279.06:46:53.29:exper_initi 2006.279.06:46:53.29&exper_initi/proc_library 2006.279.06:46:53.29&exper_initi/sched_initi 2006.279.06:46:53.29:!2006.280.06:29:50 2006.279.06:46:53.29&proc_library/" k06280 tsukub32 ts 2006.279.06:46:53.29&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.279.06:46:53.29&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.279.06:46:53.29&sched_initi/startcheck 2006.279.06:46:53.29&startcheck/sy=check_fsrun.pl & 2006.279.06:46:53.29&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.279.06:47:03.49;wx 2006.279.06:47:03.49/wx/16.37,989.4,100 2006.279.06:47:11.33;cable 2006.279.06:47:11.54/cable/+6.5048E-03 2006.280.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.280.06:29:50.02:!2006.280.07:19:50 2006.280.07:19:50.00:unstow 2006.280.07:19:50.00&unstow/antenna=e 2006.280.07:19:50.00&unstow/!+10s 2006.280.07:19:50.00&unstow/antenna=m2 2006.280.07:20:02.01:scan_name=280-0730,k06280,60 2006.280.07:20:02.01:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.280.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.280.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.280.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.280.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.280.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.280.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.280.07:20:03.14:ready_k5 2006.280.07:20:03.14&ready_k5/obsinfo=st 2006.280.07:20:03.14&ready_k5/autoobs=1 2006.280.07:20:03.14&ready_k5/autoobs=2 2006.280.07:20:03.14&ready_k5/autoobs=3 2006.280.07:20:03.14&ready_k5/autoobs=4 2006.280.07:20:03.14&ready_k5/obsinfo 2006.280.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.280.07:20:03.14#flagr#flagr/antenna,new-source 2006.280.07:20:06.48/autoobs//k5ts1/ autoobs started! 2006.280.07:20:09.70/autoobs//k5ts2/ autoobs started! 2006.280.07:20:13.04/autoobs//k5ts3/ autoobs started! 2006.280.07:20:16.30/autoobs//k5ts4/ autoobs started! 2006.280.07:20:16.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:20:16.33:4f8m12a=1 2006.280.07:20:16.33&4f8m12a/xlog=on 2006.280.07:20:16.33&4f8m12a/echo=on 2006.280.07:20:16.33&4f8m12a/pcalon 2006.280.07:20:16.33&4f8m12a/"tpicd=stop 2006.280.07:20:16.33&4f8m12a/vc4f8 2006.280.07:20:16.33&4f8m12a/ifd4f 2006.280.07:20:16.33&4f8m12a/"form=m,16.000,1:2 2006.280.07:20:16.33&4f8m12a/"tpicd 2006.280.07:20:16.33&4f8m12a/echo=off 2006.280.07:20:16.33&4f8m12a/xlog=off 2006.280.07:20:16.33$4f8m12a/echo=on 2006.280.07:20:16.33$4f8m12a/pcalon 2006.280.07:20:16.33&pcalon/"no phase cal control is implemented here 2006.280.07:20:16.33$pcalon/"no phase cal control is implemented here 2006.280.07:20:16.33$4f8m12a/"tpicd=stop 2006.280.07:20:16.33$4f8m12a/vc4f8 2006.280.07:20:16.33&vc4f8/valo=1,532.99 2006.280.07:20:16.33&vc4f8/va=1,7 2006.280.07:20:16.33&vc4f8/valo=2,572.99 2006.280.07:20:16.33&vc4f8/va=2,6 2006.280.07:20:16.33&vc4f8/valo=3,672.99 2006.280.07:20:16.33&vc4f8/va=3,6 2006.280.07:20:16.33&vc4f8/valo=4,832.99 2006.280.07:20:16.33&vc4f8/va=4,6 2006.280.07:20:16.33&vc4f8/valo=5,652.99 2006.280.07:20:16.33&vc4f8/va=5,7 2006.280.07:20:16.33&vc4f8/valo=6,772.99 2006.280.07:20:16.33&vc4f8/va=6,6 2006.280.07:20:16.33&vc4f8/valo=7,832.99 2006.280.07:20:16.33&vc4f8/va=7,6 2006.280.07:20:16.33&vc4f8/valo=8,852.99 2006.280.07:20:16.33&vc4f8/va=8,6 2006.280.07:20:16.33&vc4f8/vblo=1,632.99 2006.280.07:20:16.33&vc4f8/vb=1,4 2006.280.07:20:16.33&vc4f8/vblo=2,640.99 2006.280.07:20:16.33&vc4f8/vb=2,5 2006.280.07:20:16.33&vc4f8/vblo=3,656.99 2006.280.07:20:16.33&vc4f8/vb=3,4 2006.280.07:20:16.33&vc4f8/vblo=4,712.99 2006.280.07:20:16.33&vc4f8/vb=4,4 2006.280.07:20:16.33&vc4f8/vblo=5,744.99 2006.280.07:20:16.33&vc4f8/vb=5,4 2006.280.07:20:16.33&vc4f8/vblo=6,752.99 2006.280.07:20:16.33&vc4f8/vb=6,4 2006.280.07:20:16.33&vc4f8/vabw=wide 2006.280.07:20:16.43&vc4f8/vbbw=wide 2006.280.07:20:16.43$vc4f8/valo=1,532.99 2006.280.07:20:16.43#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:20:16.43#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:20:16.43#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:16.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:16.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:16.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:16.43#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:20:16.43#ibcon#first serial, iclass 17, count 0 2006.280.07:20:16.43#ibcon#enter sib2, iclass 17, count 0 2006.280.07:20:16.43#ibcon#flushed, iclass 17, count 0 2006.280.07:20:16.43#ibcon#about to write, iclass 17, count 0 2006.280.07:20:16.43#ibcon#wrote, iclass 17, count 0 2006.280.07:20:16.43#ibcon#about to read 3, iclass 17, count 0 2006.280.07:20:16.45#ibcon#read 3, iclass 17, count 0 2006.280.07:20:16.45#ibcon#about to read 4, iclass 17, count 0 2006.280.07:20:16.45#ibcon#read 4, iclass 17, count 0 2006.280.07:20:16.45#ibcon#about to read 5, iclass 17, count 0 2006.280.07:20:16.45#ibcon#read 5, iclass 17, count 0 2006.280.07:20:16.45#ibcon#about to read 6, iclass 17, count 0 2006.280.07:20:16.45#ibcon#read 6, iclass 17, count 0 2006.280.07:20:16.45#ibcon#end of sib2, iclass 17, count 0 2006.280.07:20:16.45#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:20:16.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:20:16.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:20:16.45#ibcon#*before write, iclass 17, count 0 2006.280.07:20:16.45#ibcon#enter sib2, iclass 17, count 0 2006.280.07:20:16.45#ibcon#flushed, iclass 17, count 0 2006.280.07:20:16.45#ibcon#about to write, iclass 17, count 0 2006.280.07:20:16.45#ibcon#wrote, iclass 17, count 0 2006.280.07:20:16.45#ibcon#about to read 3, iclass 17, count 0 2006.280.07:20:16.51#ibcon#read 3, iclass 17, count 0 2006.280.07:20:16.51#ibcon#about to read 4, iclass 17, count 0 2006.280.07:20:16.51#ibcon#read 4, iclass 17, count 0 2006.280.07:20:16.51#ibcon#about to read 5, iclass 17, count 0 2006.280.07:20:16.51#ibcon#read 5, iclass 17, count 0 2006.280.07:20:16.51#ibcon#about to read 6, iclass 17, count 0 2006.280.07:20:16.51#ibcon#read 6, iclass 17, count 0 2006.280.07:20:16.51#ibcon#end of sib2, iclass 17, count 0 2006.280.07:20:16.51#ibcon#*after write, iclass 17, count 0 2006.280.07:20:16.51#ibcon#*before return 0, iclass 17, count 0 2006.280.07:20:16.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:16.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:16.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:20:16.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:20:16.57$vc4f8/va=1,7 2006.280.07:20:16.57#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:20:16.57#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:20:16.57#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:16.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:16.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:16.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:16.57#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:20:16.57#ibcon#first serial, iclass 19, count 2 2006.280.07:20:16.57#ibcon#enter sib2, iclass 19, count 2 2006.280.07:20:16.57#ibcon#flushed, iclass 19, count 2 2006.280.07:20:16.57#ibcon#about to write, iclass 19, count 2 2006.280.07:20:16.57#ibcon#wrote, iclass 19, count 2 2006.280.07:20:16.57#ibcon#about to read 3, iclass 19, count 2 2006.280.07:20:16.59#ibcon#read 3, iclass 19, count 2 2006.280.07:20:16.59#ibcon#about to read 4, iclass 19, count 2 2006.280.07:20:16.59#ibcon#read 4, iclass 19, count 2 2006.280.07:20:16.59#ibcon#about to read 5, iclass 19, count 2 2006.280.07:20:16.59#ibcon#read 5, iclass 19, count 2 2006.280.07:20:16.59#ibcon#about to read 6, iclass 19, count 2 2006.280.07:20:16.59#ibcon#read 6, iclass 19, count 2 2006.280.07:20:16.59#ibcon#end of sib2, iclass 19, count 2 2006.280.07:20:16.59#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:20:16.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:20:16.59#ibcon#[25=AT01-07\r\n] 2006.280.07:20:16.59#ibcon#*before write, iclass 19, count 2 2006.280.07:20:16.59#ibcon#enter sib2, iclass 19, count 2 2006.280.07:20:16.59#ibcon#flushed, iclass 19, count 2 2006.280.07:20:16.59#ibcon#about to write, iclass 19, count 2 2006.280.07:20:16.59#ibcon#wrote, iclass 19, count 2 2006.280.07:20:16.59#ibcon#about to read 3, iclass 19, count 2 2006.280.07:20:16.63#ibcon#read 3, iclass 19, count 2 2006.280.07:20:16.63#ibcon#about to read 4, iclass 19, count 2 2006.280.07:20:16.63#ibcon#read 4, iclass 19, count 2 2006.280.07:20:16.63#ibcon#about to read 5, iclass 19, count 2 2006.280.07:20:16.63#ibcon#read 5, iclass 19, count 2 2006.280.07:20:16.63#ibcon#about to read 6, iclass 19, count 2 2006.280.07:20:16.63#ibcon#read 6, iclass 19, count 2 2006.280.07:20:16.63#ibcon#end of sib2, iclass 19, count 2 2006.280.07:20:16.63#ibcon#*after write, iclass 19, count 2 2006.280.07:20:16.63#ibcon#*before return 0, iclass 19, count 2 2006.280.07:20:16.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:16.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:16.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:20:16.63#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:16.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:16.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:16.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:16.75#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:20:16.75#ibcon#first serial, iclass 19, count 0 2006.280.07:20:16.75#ibcon#enter sib2, iclass 19, count 0 2006.280.07:20:16.75#ibcon#flushed, iclass 19, count 0 2006.280.07:20:16.75#ibcon#about to write, iclass 19, count 0 2006.280.07:20:16.75#ibcon#wrote, iclass 19, count 0 2006.280.07:20:16.75#ibcon#about to read 3, iclass 19, count 0 2006.280.07:20:16.77#ibcon#read 3, iclass 19, count 0 2006.280.07:20:16.77#ibcon#about to read 4, iclass 19, count 0 2006.280.07:20:16.77#ibcon#read 4, iclass 19, count 0 2006.280.07:20:16.77#ibcon#about to read 5, iclass 19, count 0 2006.280.07:20:16.77#ibcon#read 5, iclass 19, count 0 2006.280.07:20:16.77#ibcon#about to read 6, iclass 19, count 0 2006.280.07:20:16.77#ibcon#read 6, iclass 19, count 0 2006.280.07:20:16.77#ibcon#end of sib2, iclass 19, count 0 2006.280.07:20:16.77#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:20:16.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:20:16.77#ibcon#[25=USB\r\n] 2006.280.07:20:16.77#ibcon#*before write, iclass 19, count 0 2006.280.07:20:16.77#ibcon#enter sib2, iclass 19, count 0 2006.280.07:20:16.77#ibcon#flushed, iclass 19, count 0 2006.280.07:20:16.77#ibcon#about to write, iclass 19, count 0 2006.280.07:20:16.77#ibcon#wrote, iclass 19, count 0 2006.280.07:20:16.77#ibcon#about to read 3, iclass 19, count 0 2006.280.07:20:16.80#ibcon#read 3, iclass 19, count 0 2006.280.07:20:16.80#ibcon#about to read 4, iclass 19, count 0 2006.280.07:20:16.80#ibcon#read 4, iclass 19, count 0 2006.280.07:20:16.80#ibcon#about to read 5, iclass 19, count 0 2006.280.07:20:16.80#ibcon#read 5, iclass 19, count 0 2006.280.07:20:16.80#ibcon#about to read 6, iclass 19, count 0 2006.280.07:20:16.80#ibcon#read 6, iclass 19, count 0 2006.280.07:20:16.80#ibcon#end of sib2, iclass 19, count 0 2006.280.07:20:16.80#ibcon#*after write, iclass 19, count 0 2006.280.07:20:16.80#ibcon#*before return 0, iclass 19, count 0 2006.280.07:20:16.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:16.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:16.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:20:16.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:20:16.80$vc4f8/valo=2,572.99 2006.280.07:20:16.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:20:16.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:20:16.80#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:16.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:16.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:16.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:16.80#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:20:16.80#ibcon#first serial, iclass 21, count 0 2006.280.07:20:16.80#ibcon#enter sib2, iclass 21, count 0 2006.280.07:20:16.80#ibcon#flushed, iclass 21, count 0 2006.280.07:20:16.81#ibcon#about to write, iclass 21, count 0 2006.280.07:20:16.81#ibcon#wrote, iclass 21, count 0 2006.280.07:20:16.81#ibcon#about to read 3, iclass 21, count 0 2006.280.07:20:16.82#ibcon#read 3, iclass 21, count 0 2006.280.07:20:16.82#ibcon#about to read 4, iclass 21, count 0 2006.280.07:20:16.82#ibcon#read 4, iclass 21, count 0 2006.280.07:20:16.82#ibcon#about to read 5, iclass 21, count 0 2006.280.07:20:16.82#ibcon#read 5, iclass 21, count 0 2006.280.07:20:16.82#ibcon#about to read 6, iclass 21, count 0 2006.280.07:20:16.82#ibcon#read 6, iclass 21, count 0 2006.280.07:20:16.82#ibcon#end of sib2, iclass 21, count 0 2006.280.07:20:16.82#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:20:16.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:20:16.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:20:16.82#ibcon#*before write, iclass 21, count 0 2006.280.07:20:16.82#ibcon#enter sib2, iclass 21, count 0 2006.280.07:20:16.82#ibcon#flushed, iclass 21, count 0 2006.280.07:20:16.82#ibcon#about to write, iclass 21, count 0 2006.280.07:20:16.82#ibcon#wrote, iclass 21, count 0 2006.280.07:20:16.82#ibcon#about to read 3, iclass 21, count 0 2006.280.07:20:16.86#ibcon#read 3, iclass 21, count 0 2006.280.07:20:16.86#ibcon#about to read 4, iclass 21, count 0 2006.280.07:20:16.86#ibcon#read 4, iclass 21, count 0 2006.280.07:20:16.86#ibcon#about to read 5, iclass 21, count 0 2006.280.07:20:16.86#ibcon#read 5, iclass 21, count 0 2006.280.07:20:16.86#ibcon#about to read 6, iclass 21, count 0 2006.280.07:20:16.86#ibcon#read 6, iclass 21, count 0 2006.280.07:20:16.86#ibcon#end of sib2, iclass 21, count 0 2006.280.07:20:16.86#ibcon#*after write, iclass 21, count 0 2006.280.07:20:16.86#ibcon#*before return 0, iclass 21, count 0 2006.280.07:20:16.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:16.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:16.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:20:16.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:20:16.90$vc4f8/va=2,6 2006.280.07:20:16.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:20:16.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:20:16.90#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:16.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:16.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:16.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:16.91#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:20:16.91#ibcon#first serial, iclass 23, count 2 2006.280.07:20:16.91#ibcon#enter sib2, iclass 23, count 2 2006.280.07:20:16.91#ibcon#flushed, iclass 23, count 2 2006.280.07:20:16.91#ibcon#about to write, iclass 23, count 2 2006.280.07:20:16.91#ibcon#wrote, iclass 23, count 2 2006.280.07:20:16.91#ibcon#about to read 3, iclass 23, count 2 2006.280.07:20:16.93#ibcon#read 3, iclass 23, count 2 2006.280.07:20:16.93#ibcon#about to read 4, iclass 23, count 2 2006.280.07:20:16.93#ibcon#read 4, iclass 23, count 2 2006.280.07:20:16.93#ibcon#about to read 5, iclass 23, count 2 2006.280.07:20:16.93#ibcon#read 5, iclass 23, count 2 2006.280.07:20:16.93#ibcon#about to read 6, iclass 23, count 2 2006.280.07:20:16.93#ibcon#read 6, iclass 23, count 2 2006.280.07:20:16.93#ibcon#end of sib2, iclass 23, count 2 2006.280.07:20:16.93#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:20:16.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:20:16.93#ibcon#[25=AT02-06\r\n] 2006.280.07:20:16.93#ibcon#*before write, iclass 23, count 2 2006.280.07:20:16.93#ibcon#enter sib2, iclass 23, count 2 2006.280.07:20:16.93#ibcon#flushed, iclass 23, count 2 2006.280.07:20:16.93#ibcon#about to write, iclass 23, count 2 2006.280.07:20:16.93#ibcon#wrote, iclass 23, count 2 2006.280.07:20:16.93#ibcon#about to read 3, iclass 23, count 2 2006.280.07:20:16.96#ibcon#read 3, iclass 23, count 2 2006.280.07:20:16.96#ibcon#about to read 4, iclass 23, count 2 2006.280.07:20:16.96#ibcon#read 4, iclass 23, count 2 2006.280.07:20:16.96#ibcon#about to read 5, iclass 23, count 2 2006.280.07:20:16.96#ibcon#read 5, iclass 23, count 2 2006.280.07:20:16.96#ibcon#about to read 6, iclass 23, count 2 2006.280.07:20:16.96#ibcon#read 6, iclass 23, count 2 2006.280.07:20:16.96#ibcon#end of sib2, iclass 23, count 2 2006.280.07:20:16.96#ibcon#*after write, iclass 23, count 2 2006.280.07:20:16.96#ibcon#*before return 0, iclass 23, count 2 2006.280.07:20:16.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:16.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:16.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:20:16.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:16.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:17.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:17.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:17.08#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:20:17.08#ibcon#first serial, iclass 23, count 0 2006.280.07:20:17.08#ibcon#enter sib2, iclass 23, count 0 2006.280.07:20:17.08#ibcon#flushed, iclass 23, count 0 2006.280.07:20:17.08#ibcon#about to write, iclass 23, count 0 2006.280.07:20:17.08#ibcon#wrote, iclass 23, count 0 2006.280.07:20:17.08#ibcon#about to read 3, iclass 23, count 0 2006.280.07:20:17.10#ibcon#read 3, iclass 23, count 0 2006.280.07:20:17.10#ibcon#about to read 4, iclass 23, count 0 2006.280.07:20:17.10#ibcon#read 4, iclass 23, count 0 2006.280.07:20:17.10#ibcon#about to read 5, iclass 23, count 0 2006.280.07:20:17.10#ibcon#read 5, iclass 23, count 0 2006.280.07:20:17.10#ibcon#about to read 6, iclass 23, count 0 2006.280.07:20:17.10#ibcon#read 6, iclass 23, count 0 2006.280.07:20:17.10#ibcon#end of sib2, iclass 23, count 0 2006.280.07:20:17.10#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:20:17.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:20:17.10#ibcon#[25=USB\r\n] 2006.280.07:20:17.10#ibcon#*before write, iclass 23, count 0 2006.280.07:20:17.10#ibcon#enter sib2, iclass 23, count 0 2006.280.07:20:17.10#ibcon#flushed, iclass 23, count 0 2006.280.07:20:17.10#ibcon#about to write, iclass 23, count 0 2006.280.07:20:17.10#ibcon#wrote, iclass 23, count 0 2006.280.07:20:17.10#ibcon#about to read 3, iclass 23, count 0 2006.280.07:20:17.13#ibcon#read 3, iclass 23, count 0 2006.280.07:20:17.13#ibcon#about to read 4, iclass 23, count 0 2006.280.07:20:17.13#ibcon#read 4, iclass 23, count 0 2006.280.07:20:17.13#ibcon#about to read 5, iclass 23, count 0 2006.280.07:20:17.13#ibcon#read 5, iclass 23, count 0 2006.280.07:20:17.13#ibcon#about to read 6, iclass 23, count 0 2006.280.07:20:17.13#ibcon#read 6, iclass 23, count 0 2006.280.07:20:17.13#ibcon#end of sib2, iclass 23, count 0 2006.280.07:20:17.13#ibcon#*after write, iclass 23, count 0 2006.280.07:20:17.13#ibcon#*before return 0, iclass 23, count 0 2006.280.07:20:17.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:17.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:17.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:20:17.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:20:17.13$vc4f8/valo=3,672.99 2006.280.07:20:17.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:20:17.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:20:17.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:17.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:17.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:17.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:17.13#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:20:17.13#ibcon#first serial, iclass 25, count 0 2006.280.07:20:17.13#ibcon#enter sib2, iclass 25, count 0 2006.280.07:20:17.13#ibcon#flushed, iclass 25, count 0 2006.280.07:20:17.13#ibcon#about to write, iclass 25, count 0 2006.280.07:20:17.13#ibcon#wrote, iclass 25, count 0 2006.280.07:20:17.13#ibcon#about to read 3, iclass 25, count 0 2006.280.07:20:17.15#ibcon#read 3, iclass 25, count 0 2006.280.07:20:17.15#ibcon#about to read 4, iclass 25, count 0 2006.280.07:20:17.15#ibcon#read 4, iclass 25, count 0 2006.280.07:20:17.15#ibcon#about to read 5, iclass 25, count 0 2006.280.07:20:17.15#ibcon#read 5, iclass 25, count 0 2006.280.07:20:17.15#ibcon#about to read 6, iclass 25, count 0 2006.280.07:20:17.15#ibcon#read 6, iclass 25, count 0 2006.280.07:20:17.15#ibcon#end of sib2, iclass 25, count 0 2006.280.07:20:17.15#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:20:17.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:20:17.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:20:17.15#ibcon#*before write, iclass 25, count 0 2006.280.07:20:17.15#ibcon#enter sib2, iclass 25, count 0 2006.280.07:20:17.15#ibcon#flushed, iclass 25, count 0 2006.280.07:20:17.15#ibcon#about to write, iclass 25, count 0 2006.280.07:20:17.15#ibcon#wrote, iclass 25, count 0 2006.280.07:20:17.15#ibcon#about to read 3, iclass 25, count 0 2006.280.07:20:17.19#ibcon#read 3, iclass 25, count 0 2006.280.07:20:17.19#ibcon#about to read 4, iclass 25, count 0 2006.280.07:20:17.19#ibcon#read 4, iclass 25, count 0 2006.280.07:20:17.19#ibcon#about to read 5, iclass 25, count 0 2006.280.07:20:17.19#ibcon#read 5, iclass 25, count 0 2006.280.07:20:17.19#ibcon#about to read 6, iclass 25, count 0 2006.280.07:20:17.19#ibcon#read 6, iclass 25, count 0 2006.280.07:20:17.19#ibcon#end of sib2, iclass 25, count 0 2006.280.07:20:17.19#ibcon#*after write, iclass 25, count 0 2006.280.07:20:17.19#ibcon#*before return 0, iclass 25, count 0 2006.280.07:20:17.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:17.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:17.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:20:17.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:20:17.19$vc4f8/va=3,6 2006.280.07:20:17.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:20:17.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:20:17.21#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:17.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:17.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:17.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:17.24#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:20:17.24#ibcon#first serial, iclass 27, count 2 2006.280.07:20:17.24#ibcon#enter sib2, iclass 27, count 2 2006.280.07:20:17.24#ibcon#flushed, iclass 27, count 2 2006.280.07:20:17.24#ibcon#about to write, iclass 27, count 2 2006.280.07:20:17.24#ibcon#wrote, iclass 27, count 2 2006.280.07:20:17.24#ibcon#about to read 3, iclass 27, count 2 2006.280.07:20:17.26#ibcon#read 3, iclass 27, count 2 2006.280.07:20:17.26#ibcon#about to read 4, iclass 27, count 2 2006.280.07:20:17.26#ibcon#read 4, iclass 27, count 2 2006.280.07:20:17.26#ibcon#about to read 5, iclass 27, count 2 2006.280.07:20:17.26#ibcon#read 5, iclass 27, count 2 2006.280.07:20:17.26#ibcon#about to read 6, iclass 27, count 2 2006.280.07:20:17.26#ibcon#read 6, iclass 27, count 2 2006.280.07:20:17.26#ibcon#end of sib2, iclass 27, count 2 2006.280.07:20:17.26#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:20:17.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:20:17.26#ibcon#[25=AT03-06\r\n] 2006.280.07:20:17.26#ibcon#*before write, iclass 27, count 2 2006.280.07:20:17.26#ibcon#enter sib2, iclass 27, count 2 2006.280.07:20:17.26#ibcon#flushed, iclass 27, count 2 2006.280.07:20:17.26#ibcon#about to write, iclass 27, count 2 2006.280.07:20:17.26#ibcon#wrote, iclass 27, count 2 2006.280.07:20:17.26#ibcon#about to read 3, iclass 27, count 2 2006.280.07:20:17.29#ibcon#read 3, iclass 27, count 2 2006.280.07:20:17.29#ibcon#about to read 4, iclass 27, count 2 2006.280.07:20:17.29#ibcon#read 4, iclass 27, count 2 2006.280.07:20:17.29#ibcon#about to read 5, iclass 27, count 2 2006.280.07:20:17.29#ibcon#read 5, iclass 27, count 2 2006.280.07:20:17.29#ibcon#about to read 6, iclass 27, count 2 2006.280.07:20:17.29#ibcon#read 6, iclass 27, count 2 2006.280.07:20:17.29#ibcon#end of sib2, iclass 27, count 2 2006.280.07:20:17.29#ibcon#*after write, iclass 27, count 2 2006.280.07:20:17.29#ibcon#*before return 0, iclass 27, count 2 2006.280.07:20:17.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:17.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:17.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:20:17.29#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:17.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:17.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:17.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:17.41#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:20:17.41#ibcon#first serial, iclass 27, count 0 2006.280.07:20:17.41#ibcon#enter sib2, iclass 27, count 0 2006.280.07:20:17.41#ibcon#flushed, iclass 27, count 0 2006.280.07:20:17.41#ibcon#about to write, iclass 27, count 0 2006.280.07:20:17.41#ibcon#wrote, iclass 27, count 0 2006.280.07:20:17.41#ibcon#about to read 3, iclass 27, count 0 2006.280.07:20:17.43#ibcon#read 3, iclass 27, count 0 2006.280.07:20:17.43#ibcon#about to read 4, iclass 27, count 0 2006.280.07:20:17.43#ibcon#read 4, iclass 27, count 0 2006.280.07:20:17.43#ibcon#about to read 5, iclass 27, count 0 2006.280.07:20:17.43#ibcon#read 5, iclass 27, count 0 2006.280.07:20:17.43#ibcon#about to read 6, iclass 27, count 0 2006.280.07:20:17.43#ibcon#read 6, iclass 27, count 0 2006.280.07:20:17.43#ibcon#end of sib2, iclass 27, count 0 2006.280.07:20:17.43#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:20:17.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:20:17.43#ibcon#[25=USB\r\n] 2006.280.07:20:17.43#ibcon#*before write, iclass 27, count 0 2006.280.07:20:17.43#ibcon#enter sib2, iclass 27, count 0 2006.280.07:20:17.43#ibcon#flushed, iclass 27, count 0 2006.280.07:20:17.43#ibcon#about to write, iclass 27, count 0 2006.280.07:20:17.43#ibcon#wrote, iclass 27, count 0 2006.280.07:20:17.43#ibcon#about to read 3, iclass 27, count 0 2006.280.07:20:17.46#ibcon#read 3, iclass 27, count 0 2006.280.07:20:17.46#ibcon#about to read 4, iclass 27, count 0 2006.280.07:20:17.46#ibcon#read 4, iclass 27, count 0 2006.280.07:20:17.46#ibcon#about to read 5, iclass 27, count 0 2006.280.07:20:17.46#ibcon#read 5, iclass 27, count 0 2006.280.07:20:17.46#ibcon#about to read 6, iclass 27, count 0 2006.280.07:20:17.46#ibcon#read 6, iclass 27, count 0 2006.280.07:20:17.46#ibcon#end of sib2, iclass 27, count 0 2006.280.07:20:17.46#ibcon#*after write, iclass 27, count 0 2006.280.07:20:17.46#ibcon#*before return 0, iclass 27, count 0 2006.280.07:20:17.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:17.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:17.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:20:17.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:20:17.46$vc4f8/valo=4,832.99 2006.280.07:20:17.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:20:17.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:20:17.46#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:17.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:17.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:17.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:17.46#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:20:17.46#ibcon#first serial, iclass 29, count 0 2006.280.07:20:17.46#ibcon#enter sib2, iclass 29, count 0 2006.280.07:20:17.46#ibcon#flushed, iclass 29, count 0 2006.280.07:20:17.46#ibcon#about to write, iclass 29, count 0 2006.280.07:20:17.46#ibcon#wrote, iclass 29, count 0 2006.280.07:20:17.46#ibcon#about to read 3, iclass 29, count 0 2006.280.07:20:17.48#ibcon#read 3, iclass 29, count 0 2006.280.07:20:17.48#ibcon#about to read 4, iclass 29, count 0 2006.280.07:20:17.48#ibcon#read 4, iclass 29, count 0 2006.280.07:20:17.48#ibcon#about to read 5, iclass 29, count 0 2006.280.07:20:17.48#ibcon#read 5, iclass 29, count 0 2006.280.07:20:17.48#ibcon#about to read 6, iclass 29, count 0 2006.280.07:20:17.48#ibcon#read 6, iclass 29, count 0 2006.280.07:20:17.48#ibcon#end of sib2, iclass 29, count 0 2006.280.07:20:17.48#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:20:17.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:20:17.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:20:17.48#ibcon#*before write, iclass 29, count 0 2006.280.07:20:17.48#ibcon#enter sib2, iclass 29, count 0 2006.280.07:20:17.48#ibcon#flushed, iclass 29, count 0 2006.280.07:20:17.48#ibcon#about to write, iclass 29, count 0 2006.280.07:20:17.48#ibcon#wrote, iclass 29, count 0 2006.280.07:20:17.48#ibcon#about to read 3, iclass 29, count 0 2006.280.07:20:17.52#ibcon#read 3, iclass 29, count 0 2006.280.07:20:17.52#ibcon#about to read 4, iclass 29, count 0 2006.280.07:20:17.52#ibcon#read 4, iclass 29, count 0 2006.280.07:20:17.52#ibcon#about to read 5, iclass 29, count 0 2006.280.07:20:17.52#ibcon#read 5, iclass 29, count 0 2006.280.07:20:17.52#ibcon#about to read 6, iclass 29, count 0 2006.280.07:20:17.52#ibcon#read 6, iclass 29, count 0 2006.280.07:20:17.52#ibcon#end of sib2, iclass 29, count 0 2006.280.07:20:17.52#ibcon#*after write, iclass 29, count 0 2006.280.07:20:17.52#ibcon#*before return 0, iclass 29, count 0 2006.280.07:20:17.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:17.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:17.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:20:17.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:20:17.52$vc4f8/va=4,6 2006.280.07:20:17.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:20:17.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:20:17.53#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:17.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:17.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:17.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:17.57#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:20:17.57#ibcon#first serial, iclass 31, count 2 2006.280.07:20:17.57#ibcon#enter sib2, iclass 31, count 2 2006.280.07:20:17.57#ibcon#flushed, iclass 31, count 2 2006.280.07:20:17.57#ibcon#about to write, iclass 31, count 2 2006.280.07:20:17.57#ibcon#wrote, iclass 31, count 2 2006.280.07:20:17.57#ibcon#about to read 3, iclass 31, count 2 2006.280.07:20:17.59#ibcon#read 3, iclass 31, count 2 2006.280.07:20:17.59#ibcon#about to read 4, iclass 31, count 2 2006.280.07:20:17.59#ibcon#read 4, iclass 31, count 2 2006.280.07:20:17.59#ibcon#about to read 5, iclass 31, count 2 2006.280.07:20:17.59#ibcon#read 5, iclass 31, count 2 2006.280.07:20:17.59#ibcon#about to read 6, iclass 31, count 2 2006.280.07:20:17.59#ibcon#read 6, iclass 31, count 2 2006.280.07:20:17.59#ibcon#end of sib2, iclass 31, count 2 2006.280.07:20:17.59#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:20:17.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:20:17.59#ibcon#[25=AT04-06\r\n] 2006.280.07:20:17.59#ibcon#*before write, iclass 31, count 2 2006.280.07:20:17.59#ibcon#enter sib2, iclass 31, count 2 2006.280.07:20:17.59#ibcon#flushed, iclass 31, count 2 2006.280.07:20:17.59#ibcon#about to write, iclass 31, count 2 2006.280.07:20:17.59#ibcon#wrote, iclass 31, count 2 2006.280.07:20:17.59#ibcon#about to read 3, iclass 31, count 2 2006.280.07:20:17.62#ibcon#read 3, iclass 31, count 2 2006.280.07:20:17.62#ibcon#about to read 4, iclass 31, count 2 2006.280.07:20:17.62#ibcon#read 4, iclass 31, count 2 2006.280.07:20:17.62#ibcon#about to read 5, iclass 31, count 2 2006.280.07:20:17.62#ibcon#read 5, iclass 31, count 2 2006.280.07:20:17.62#ibcon#about to read 6, iclass 31, count 2 2006.280.07:20:17.62#ibcon#read 6, iclass 31, count 2 2006.280.07:20:17.62#ibcon#end of sib2, iclass 31, count 2 2006.280.07:20:17.62#ibcon#*after write, iclass 31, count 2 2006.280.07:20:17.62#ibcon#*before return 0, iclass 31, count 2 2006.280.07:20:17.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:17.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:17.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:20:17.62#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:17.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:17.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:17.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:17.74#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:20:17.74#ibcon#first serial, iclass 31, count 0 2006.280.07:20:17.74#ibcon#enter sib2, iclass 31, count 0 2006.280.07:20:17.74#ibcon#flushed, iclass 31, count 0 2006.280.07:20:17.74#ibcon#about to write, iclass 31, count 0 2006.280.07:20:17.74#ibcon#wrote, iclass 31, count 0 2006.280.07:20:17.74#ibcon#about to read 3, iclass 31, count 0 2006.280.07:20:17.76#ibcon#read 3, iclass 31, count 0 2006.280.07:20:17.76#ibcon#about to read 4, iclass 31, count 0 2006.280.07:20:17.76#ibcon#read 4, iclass 31, count 0 2006.280.07:20:17.76#ibcon#about to read 5, iclass 31, count 0 2006.280.07:20:17.76#ibcon#read 5, iclass 31, count 0 2006.280.07:20:17.76#ibcon#about to read 6, iclass 31, count 0 2006.280.07:20:17.76#ibcon#read 6, iclass 31, count 0 2006.280.07:20:17.76#ibcon#end of sib2, iclass 31, count 0 2006.280.07:20:17.76#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:20:17.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:20:17.76#ibcon#[25=USB\r\n] 2006.280.07:20:17.76#ibcon#*before write, iclass 31, count 0 2006.280.07:20:17.76#ibcon#enter sib2, iclass 31, count 0 2006.280.07:20:17.76#ibcon#flushed, iclass 31, count 0 2006.280.07:20:17.76#ibcon#about to write, iclass 31, count 0 2006.280.07:20:17.76#ibcon#wrote, iclass 31, count 0 2006.280.07:20:17.76#ibcon#about to read 3, iclass 31, count 0 2006.280.07:20:17.79#ibcon#read 3, iclass 31, count 0 2006.280.07:20:17.79#ibcon#about to read 4, iclass 31, count 0 2006.280.07:20:17.79#ibcon#read 4, iclass 31, count 0 2006.280.07:20:17.79#ibcon#about to read 5, iclass 31, count 0 2006.280.07:20:17.79#ibcon#read 5, iclass 31, count 0 2006.280.07:20:17.79#ibcon#about to read 6, iclass 31, count 0 2006.280.07:20:17.79#ibcon#read 6, iclass 31, count 0 2006.280.07:20:17.79#ibcon#end of sib2, iclass 31, count 0 2006.280.07:20:17.79#ibcon#*after write, iclass 31, count 0 2006.280.07:20:17.79#ibcon#*before return 0, iclass 31, count 0 2006.280.07:20:17.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:17.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:17.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:20:17.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:20:17.79$vc4f8/valo=5,652.99 2006.280.07:20:17.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:20:17.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:20:17.79#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:17.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:17.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:17.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:17.79#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:20:17.79#ibcon#first serial, iclass 33, count 0 2006.280.07:20:17.79#ibcon#enter sib2, iclass 33, count 0 2006.280.07:20:17.79#ibcon#flushed, iclass 33, count 0 2006.280.07:20:17.79#ibcon#about to write, iclass 33, count 0 2006.280.07:20:17.79#ibcon#wrote, iclass 33, count 0 2006.280.07:20:17.79#ibcon#about to read 3, iclass 33, count 0 2006.280.07:20:17.82#ibcon#read 3, iclass 33, count 0 2006.280.07:20:17.82#ibcon#about to read 4, iclass 33, count 0 2006.280.07:20:17.82#ibcon#read 4, iclass 33, count 0 2006.280.07:20:17.82#ibcon#about to read 5, iclass 33, count 0 2006.280.07:20:17.82#ibcon#read 5, iclass 33, count 0 2006.280.07:20:17.82#ibcon#about to read 6, iclass 33, count 0 2006.280.07:20:17.82#ibcon#read 6, iclass 33, count 0 2006.280.07:20:17.82#ibcon#end of sib2, iclass 33, count 0 2006.280.07:20:17.82#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:20:17.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:20:17.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:20:17.82#ibcon#*before write, iclass 33, count 0 2006.280.07:20:17.82#ibcon#enter sib2, iclass 33, count 0 2006.280.07:20:17.82#ibcon#flushed, iclass 33, count 0 2006.280.07:20:17.82#ibcon#about to write, iclass 33, count 0 2006.280.07:20:17.82#ibcon#wrote, iclass 33, count 0 2006.280.07:20:17.82#ibcon#about to read 3, iclass 33, count 0 2006.280.07:20:17.86#ibcon#read 3, iclass 33, count 0 2006.280.07:20:17.86#ibcon#about to read 4, iclass 33, count 0 2006.280.07:20:17.86#ibcon#read 4, iclass 33, count 0 2006.280.07:20:17.86#ibcon#about to read 5, iclass 33, count 0 2006.280.07:20:17.86#ibcon#read 5, iclass 33, count 0 2006.280.07:20:17.86#ibcon#about to read 6, iclass 33, count 0 2006.280.07:20:17.86#ibcon#read 6, iclass 33, count 0 2006.280.07:20:17.86#ibcon#end of sib2, iclass 33, count 0 2006.280.07:20:17.86#ibcon#*after write, iclass 33, count 0 2006.280.07:20:17.86#ibcon#*before return 0, iclass 33, count 0 2006.280.07:20:17.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:17.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:17.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:20:17.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:20:17.86$vc4f8/va=5,7 2006.280.07:20:17.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:20:17.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:20:17.86#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:17.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:17.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:17.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:17.91#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:20:17.91#ibcon#first serial, iclass 35, count 2 2006.280.07:20:17.91#ibcon#enter sib2, iclass 35, count 2 2006.280.07:20:17.91#ibcon#flushed, iclass 35, count 2 2006.280.07:20:17.91#ibcon#about to write, iclass 35, count 2 2006.280.07:20:17.91#ibcon#wrote, iclass 35, count 2 2006.280.07:20:17.91#ibcon#about to read 3, iclass 35, count 2 2006.280.07:20:17.93#ibcon#read 3, iclass 35, count 2 2006.280.07:20:17.93#ibcon#about to read 4, iclass 35, count 2 2006.280.07:20:17.93#ibcon#read 4, iclass 35, count 2 2006.280.07:20:17.93#ibcon#about to read 5, iclass 35, count 2 2006.280.07:20:17.93#ibcon#read 5, iclass 35, count 2 2006.280.07:20:17.93#ibcon#about to read 6, iclass 35, count 2 2006.280.07:20:17.93#ibcon#read 6, iclass 35, count 2 2006.280.07:20:17.93#ibcon#end of sib2, iclass 35, count 2 2006.280.07:20:17.93#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:20:17.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:20:17.93#ibcon#[25=AT05-07\r\n] 2006.280.07:20:17.93#ibcon#*before write, iclass 35, count 2 2006.280.07:20:17.93#ibcon#enter sib2, iclass 35, count 2 2006.280.07:20:17.93#ibcon#flushed, iclass 35, count 2 2006.280.07:20:17.93#ibcon#about to write, iclass 35, count 2 2006.280.07:20:17.93#ibcon#wrote, iclass 35, count 2 2006.280.07:20:17.93#ibcon#about to read 3, iclass 35, count 2 2006.280.07:20:17.96#ibcon#read 3, iclass 35, count 2 2006.280.07:20:17.96#ibcon#about to read 4, iclass 35, count 2 2006.280.07:20:17.96#ibcon#read 4, iclass 35, count 2 2006.280.07:20:17.96#ibcon#about to read 5, iclass 35, count 2 2006.280.07:20:17.96#ibcon#read 5, iclass 35, count 2 2006.280.07:20:17.96#ibcon#about to read 6, iclass 35, count 2 2006.280.07:20:17.96#ibcon#read 6, iclass 35, count 2 2006.280.07:20:17.96#ibcon#end of sib2, iclass 35, count 2 2006.280.07:20:17.96#ibcon#*after write, iclass 35, count 2 2006.280.07:20:17.96#ibcon#*before return 0, iclass 35, count 2 2006.280.07:20:17.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:17.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:17.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:20:17.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:17.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:18.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:18.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:18.08#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:20:18.08#ibcon#first serial, iclass 35, count 0 2006.280.07:20:18.08#ibcon#enter sib2, iclass 35, count 0 2006.280.07:20:18.08#ibcon#flushed, iclass 35, count 0 2006.280.07:20:18.08#ibcon#about to write, iclass 35, count 0 2006.280.07:20:18.08#ibcon#wrote, iclass 35, count 0 2006.280.07:20:18.08#ibcon#about to read 3, iclass 35, count 0 2006.280.07:20:18.10#ibcon#read 3, iclass 35, count 0 2006.280.07:20:18.10#ibcon#about to read 4, iclass 35, count 0 2006.280.07:20:18.10#ibcon#read 4, iclass 35, count 0 2006.280.07:20:18.10#ibcon#about to read 5, iclass 35, count 0 2006.280.07:20:18.10#ibcon#read 5, iclass 35, count 0 2006.280.07:20:18.10#ibcon#about to read 6, iclass 35, count 0 2006.280.07:20:18.10#ibcon#read 6, iclass 35, count 0 2006.280.07:20:18.10#ibcon#end of sib2, iclass 35, count 0 2006.280.07:20:18.10#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:20:18.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:20:18.10#ibcon#[25=USB\r\n] 2006.280.07:20:18.10#ibcon#*before write, iclass 35, count 0 2006.280.07:20:18.10#ibcon#enter sib2, iclass 35, count 0 2006.280.07:20:18.10#ibcon#flushed, iclass 35, count 0 2006.280.07:20:18.10#ibcon#about to write, iclass 35, count 0 2006.280.07:20:18.10#ibcon#wrote, iclass 35, count 0 2006.280.07:20:18.10#ibcon#about to read 3, iclass 35, count 0 2006.280.07:20:18.13#ibcon#read 3, iclass 35, count 0 2006.280.07:20:18.13#ibcon#about to read 4, iclass 35, count 0 2006.280.07:20:18.13#ibcon#read 4, iclass 35, count 0 2006.280.07:20:18.13#ibcon#about to read 5, iclass 35, count 0 2006.280.07:20:18.13#ibcon#read 5, iclass 35, count 0 2006.280.07:20:18.13#ibcon#about to read 6, iclass 35, count 0 2006.280.07:20:18.13#ibcon#read 6, iclass 35, count 0 2006.280.07:20:18.13#ibcon#end of sib2, iclass 35, count 0 2006.280.07:20:18.13#ibcon#*after write, iclass 35, count 0 2006.280.07:20:18.13#ibcon#*before return 0, iclass 35, count 0 2006.280.07:20:18.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:18.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:18.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:20:18.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:20:18.13$vc4f8/valo=6,772.99 2006.280.07:20:18.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:20:18.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:18.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:18.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:18.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:18.13#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:20:18.13#ibcon#first serial, iclass 37, count 0 2006.280.07:20:18.13#ibcon#enter sib2, iclass 37, count 0 2006.280.07:20:18.13#ibcon#flushed, iclass 37, count 0 2006.280.07:20:18.13#ibcon#about to write, iclass 37, count 0 2006.280.07:20:18.13#ibcon#wrote, iclass 37, count 0 2006.280.07:20:18.13#ibcon#about to read 3, iclass 37, count 0 2006.280.07:20:18.15#ibcon#read 3, iclass 37, count 0 2006.280.07:20:18.15#ibcon#about to read 4, iclass 37, count 0 2006.280.07:20:18.15#ibcon#read 4, iclass 37, count 0 2006.280.07:20:18.15#ibcon#about to read 5, iclass 37, count 0 2006.280.07:20:18.15#ibcon#read 5, iclass 37, count 0 2006.280.07:20:18.15#ibcon#about to read 6, iclass 37, count 0 2006.280.07:20:18.15#ibcon#read 6, iclass 37, count 0 2006.280.07:20:18.15#ibcon#end of sib2, iclass 37, count 0 2006.280.07:20:18.15#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:20:18.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:20:18.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:20:18.15#ibcon#*before write, iclass 37, count 0 2006.280.07:20:18.15#ibcon#enter sib2, iclass 37, count 0 2006.280.07:20:18.15#ibcon#flushed, iclass 37, count 0 2006.280.07:20:18.15#ibcon#about to write, iclass 37, count 0 2006.280.07:20:18.15#ibcon#wrote, iclass 37, count 0 2006.280.07:20:18.15#ibcon#about to read 3, iclass 37, count 0 2006.280.07:20:18.19#ibcon#read 3, iclass 37, count 0 2006.280.07:20:18.19#ibcon#about to read 4, iclass 37, count 0 2006.280.07:20:18.19#ibcon#read 4, iclass 37, count 0 2006.280.07:20:18.19#ibcon#about to read 5, iclass 37, count 0 2006.280.07:20:18.19#ibcon#read 5, iclass 37, count 0 2006.280.07:20:18.19#ibcon#about to read 6, iclass 37, count 0 2006.280.07:20:18.19#ibcon#read 6, iclass 37, count 0 2006.280.07:20:18.19#ibcon#end of sib2, iclass 37, count 0 2006.280.07:20:18.19#ibcon#*after write, iclass 37, count 0 2006.280.07:20:18.19#ibcon#*before return 0, iclass 37, count 0 2006.280.07:20:18.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:18.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:18.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:20:18.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:20:18.19$vc4f8/va=6,6 2006.280.07:20:18.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:20:18.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:18.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:18.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:18.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:18.25#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:20:18.25#ibcon#first serial, iclass 39, count 2 2006.280.07:20:18.25#ibcon#enter sib2, iclass 39, count 2 2006.280.07:20:18.25#ibcon#flushed, iclass 39, count 2 2006.280.07:20:18.25#ibcon#about to write, iclass 39, count 2 2006.280.07:20:18.25#ibcon#wrote, iclass 39, count 2 2006.280.07:20:18.25#ibcon#about to read 3, iclass 39, count 2 2006.280.07:20:18.27#ibcon#read 3, iclass 39, count 2 2006.280.07:20:18.27#ibcon#about to read 4, iclass 39, count 2 2006.280.07:20:18.27#ibcon#read 4, iclass 39, count 2 2006.280.07:20:18.27#ibcon#about to read 5, iclass 39, count 2 2006.280.07:20:18.27#ibcon#read 5, iclass 39, count 2 2006.280.07:20:18.27#ibcon#about to read 6, iclass 39, count 2 2006.280.07:20:18.27#ibcon#read 6, iclass 39, count 2 2006.280.07:20:18.27#ibcon#end of sib2, iclass 39, count 2 2006.280.07:20:18.27#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:20:18.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:20:18.27#ibcon#[25=AT06-06\r\n] 2006.280.07:20:18.27#ibcon#*before write, iclass 39, count 2 2006.280.07:20:18.27#ibcon#enter sib2, iclass 39, count 2 2006.280.07:20:18.27#ibcon#flushed, iclass 39, count 2 2006.280.07:20:18.27#ibcon#about to write, iclass 39, count 2 2006.280.07:20:18.27#ibcon#wrote, iclass 39, count 2 2006.280.07:20:18.27#ibcon#about to read 3, iclass 39, count 2 2006.280.07:20:18.30#ibcon#read 3, iclass 39, count 2 2006.280.07:20:18.30#ibcon#about to read 4, iclass 39, count 2 2006.280.07:20:18.30#ibcon#read 4, iclass 39, count 2 2006.280.07:20:18.30#ibcon#about to read 5, iclass 39, count 2 2006.280.07:20:18.30#ibcon#read 5, iclass 39, count 2 2006.280.07:20:18.30#ibcon#about to read 6, iclass 39, count 2 2006.280.07:20:18.30#ibcon#read 6, iclass 39, count 2 2006.280.07:20:18.30#ibcon#end of sib2, iclass 39, count 2 2006.280.07:20:18.30#ibcon#*after write, iclass 39, count 2 2006.280.07:20:18.30#ibcon#*before return 0, iclass 39, count 2 2006.280.07:20:18.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:18.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:18.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:20:18.30#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:18.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:20:18.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:20:18.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:20:18.42#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:20:18.42#ibcon#first serial, iclass 39, count 0 2006.280.07:20:18.42#ibcon#enter sib2, iclass 39, count 0 2006.280.07:20:18.42#ibcon#flushed, iclass 39, count 0 2006.280.07:20:18.42#ibcon#about to write, iclass 39, count 0 2006.280.07:20:18.42#ibcon#wrote, iclass 39, count 0 2006.280.07:20:18.42#ibcon#about to read 3, iclass 39, count 0 2006.280.07:20:18.44#ibcon#read 3, iclass 39, count 0 2006.280.07:20:18.44#ibcon#about to read 4, iclass 39, count 0 2006.280.07:20:18.44#ibcon#read 4, iclass 39, count 0 2006.280.07:20:18.44#ibcon#about to read 5, iclass 39, count 0 2006.280.07:20:18.44#ibcon#read 5, iclass 39, count 0 2006.280.07:20:18.44#ibcon#about to read 6, iclass 39, count 0 2006.280.07:20:18.44#ibcon#read 6, iclass 39, count 0 2006.280.07:20:18.44#ibcon#end of sib2, iclass 39, count 0 2006.280.07:20:18.44#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:20:18.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:20:18.44#ibcon#[25=USB\r\n] 2006.280.07:20:18.44#ibcon#*before write, iclass 39, count 0 2006.280.07:20:18.44#ibcon#enter sib2, iclass 39, count 0 2006.280.07:20:18.44#ibcon#flushed, iclass 39, count 0 2006.280.07:20:18.44#ibcon#about to write, iclass 39, count 0 2006.280.07:20:18.44#ibcon#wrote, iclass 39, count 0 2006.280.07:20:18.44#ibcon#about to read 3, iclass 39, count 0 2006.280.07:20:18.47#ibcon#read 3, iclass 39, count 0 2006.280.07:20:18.47#ibcon#about to read 4, iclass 39, count 0 2006.280.07:20:18.47#ibcon#read 4, iclass 39, count 0 2006.280.07:20:18.47#ibcon#about to read 5, iclass 39, count 0 2006.280.07:20:18.47#ibcon#read 5, iclass 39, count 0 2006.280.07:20:18.47#ibcon#about to read 6, iclass 39, count 0 2006.280.07:20:18.47#ibcon#read 6, iclass 39, count 0 2006.280.07:20:18.47#ibcon#end of sib2, iclass 39, count 0 2006.280.07:20:18.47#ibcon#*after write, iclass 39, count 0 2006.280.07:20:18.47#ibcon#*before return 0, iclass 39, count 0 2006.280.07:20:18.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:20:18.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:20:18.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:20:18.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:20:18.47$vc4f8/valo=7,832.99 2006.280.07:20:18.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:20:18.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:20:18.47#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:18.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:20:18.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:20:18.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:20:18.47#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:20:18.47#ibcon#first serial, iclass 3, count 0 2006.280.07:20:18.47#ibcon#enter sib2, iclass 3, count 0 2006.280.07:20:18.47#ibcon#flushed, iclass 3, count 0 2006.280.07:20:18.47#ibcon#about to write, iclass 3, count 0 2006.280.07:20:18.47#ibcon#wrote, iclass 3, count 0 2006.280.07:20:18.47#ibcon#about to read 3, iclass 3, count 0 2006.280.07:20:18.49#ibcon#read 3, iclass 3, count 0 2006.280.07:20:18.49#ibcon#about to read 4, iclass 3, count 0 2006.280.07:20:18.49#ibcon#read 4, iclass 3, count 0 2006.280.07:20:18.49#ibcon#about to read 5, iclass 3, count 0 2006.280.07:20:18.49#ibcon#read 5, iclass 3, count 0 2006.280.07:20:18.49#ibcon#about to read 6, iclass 3, count 0 2006.280.07:20:18.49#ibcon#read 6, iclass 3, count 0 2006.280.07:20:18.49#ibcon#end of sib2, iclass 3, count 0 2006.280.07:20:18.49#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:20:18.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:20:18.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:20:18.49#ibcon#*before write, iclass 3, count 0 2006.280.07:20:18.49#ibcon#enter sib2, iclass 3, count 0 2006.280.07:20:18.49#ibcon#flushed, iclass 3, count 0 2006.280.07:20:18.49#ibcon#about to write, iclass 3, count 0 2006.280.07:20:18.49#ibcon#wrote, iclass 3, count 0 2006.280.07:20:18.49#ibcon#about to read 3, iclass 3, count 0 2006.280.07:20:18.53#ibcon#read 3, iclass 3, count 0 2006.280.07:20:18.53#ibcon#about to read 4, iclass 3, count 0 2006.280.07:20:18.53#ibcon#read 4, iclass 3, count 0 2006.280.07:20:18.53#ibcon#about to read 5, iclass 3, count 0 2006.280.07:20:18.53#ibcon#read 5, iclass 3, count 0 2006.280.07:20:18.53#ibcon#about to read 6, iclass 3, count 0 2006.280.07:20:18.53#ibcon#read 6, iclass 3, count 0 2006.280.07:20:18.53#ibcon#end of sib2, iclass 3, count 0 2006.280.07:20:18.53#ibcon#*after write, iclass 3, count 0 2006.280.07:20:18.53#ibcon#*before return 0, iclass 3, count 0 2006.280.07:20:18.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:20:18.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:20:18.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:20:18.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:20:18.53$vc4f8/va=7,6 2006.280.07:20:18.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:20:18.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:20:18.54#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:18.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:20:18.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:20:18.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:20:18.58#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:20:18.58#ibcon#first serial, iclass 5, count 2 2006.280.07:20:18.58#ibcon#enter sib2, iclass 5, count 2 2006.280.07:20:18.58#ibcon#flushed, iclass 5, count 2 2006.280.07:20:18.58#ibcon#about to write, iclass 5, count 2 2006.280.07:20:18.58#ibcon#wrote, iclass 5, count 2 2006.280.07:20:18.58#ibcon#about to read 3, iclass 5, count 2 2006.280.07:20:18.60#ibcon#read 3, iclass 5, count 2 2006.280.07:20:18.60#ibcon#about to read 4, iclass 5, count 2 2006.280.07:20:18.60#ibcon#read 4, iclass 5, count 2 2006.280.07:20:18.60#ibcon#about to read 5, iclass 5, count 2 2006.280.07:20:18.60#ibcon#read 5, iclass 5, count 2 2006.280.07:20:18.60#ibcon#about to read 6, iclass 5, count 2 2006.280.07:20:18.60#ibcon#read 6, iclass 5, count 2 2006.280.07:20:18.60#ibcon#end of sib2, iclass 5, count 2 2006.280.07:20:18.60#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:20:18.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:20:18.60#ibcon#[25=AT07-06\r\n] 2006.280.07:20:18.60#ibcon#*before write, iclass 5, count 2 2006.280.07:20:18.60#ibcon#enter sib2, iclass 5, count 2 2006.280.07:20:18.60#ibcon#flushed, iclass 5, count 2 2006.280.07:20:18.60#ibcon#about to write, iclass 5, count 2 2006.280.07:20:18.60#ibcon#wrote, iclass 5, count 2 2006.280.07:20:18.60#ibcon#about to read 3, iclass 5, count 2 2006.280.07:20:18.63#ibcon#read 3, iclass 5, count 2 2006.280.07:20:18.63#ibcon#about to read 4, iclass 5, count 2 2006.280.07:20:18.63#ibcon#read 4, iclass 5, count 2 2006.280.07:20:18.63#ibcon#about to read 5, iclass 5, count 2 2006.280.07:20:18.63#ibcon#read 5, iclass 5, count 2 2006.280.07:20:18.63#ibcon#about to read 6, iclass 5, count 2 2006.280.07:20:18.63#ibcon#read 6, iclass 5, count 2 2006.280.07:20:18.63#ibcon#end of sib2, iclass 5, count 2 2006.280.07:20:18.63#ibcon#*after write, iclass 5, count 2 2006.280.07:20:18.63#ibcon#*before return 0, iclass 5, count 2 2006.280.07:20:18.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:20:18.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:20:18.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:20:18.63#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:18.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:20:18.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:20:18.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:20:18.75#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:20:18.75#ibcon#first serial, iclass 5, count 0 2006.280.07:20:18.75#ibcon#enter sib2, iclass 5, count 0 2006.280.07:20:18.75#ibcon#flushed, iclass 5, count 0 2006.280.07:20:18.75#ibcon#about to write, iclass 5, count 0 2006.280.07:20:18.75#ibcon#wrote, iclass 5, count 0 2006.280.07:20:18.75#ibcon#about to read 3, iclass 5, count 0 2006.280.07:20:18.77#ibcon#read 3, iclass 5, count 0 2006.280.07:20:18.77#ibcon#about to read 4, iclass 5, count 0 2006.280.07:20:18.77#ibcon#read 4, iclass 5, count 0 2006.280.07:20:18.77#ibcon#about to read 5, iclass 5, count 0 2006.280.07:20:18.77#ibcon#read 5, iclass 5, count 0 2006.280.07:20:18.77#ibcon#about to read 6, iclass 5, count 0 2006.280.07:20:18.77#ibcon#read 6, iclass 5, count 0 2006.280.07:20:18.77#ibcon#end of sib2, iclass 5, count 0 2006.280.07:20:18.77#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:20:18.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:20:18.77#ibcon#[25=USB\r\n] 2006.280.07:20:18.77#ibcon#*before write, iclass 5, count 0 2006.280.07:20:18.77#ibcon#enter sib2, iclass 5, count 0 2006.280.07:20:18.77#ibcon#flushed, iclass 5, count 0 2006.280.07:20:18.77#ibcon#about to write, iclass 5, count 0 2006.280.07:20:18.77#ibcon#wrote, iclass 5, count 0 2006.280.07:20:18.77#ibcon#about to read 3, iclass 5, count 0 2006.280.07:20:18.80#ibcon#read 3, iclass 5, count 0 2006.280.07:20:18.80#ibcon#about to read 4, iclass 5, count 0 2006.280.07:20:18.80#ibcon#read 4, iclass 5, count 0 2006.280.07:20:18.80#ibcon#about to read 5, iclass 5, count 0 2006.280.07:20:18.80#ibcon#read 5, iclass 5, count 0 2006.280.07:20:18.80#ibcon#about to read 6, iclass 5, count 0 2006.280.07:20:18.80#ibcon#read 6, iclass 5, count 0 2006.280.07:20:18.80#ibcon#end of sib2, iclass 5, count 0 2006.280.07:20:18.80#ibcon#*after write, iclass 5, count 0 2006.280.07:20:18.80#ibcon#*before return 0, iclass 5, count 0 2006.280.07:20:18.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:20:18.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:20:18.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:20:18.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:20:18.80$vc4f8/valo=8,852.99 2006.280.07:20:18.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:20:18.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:20:18.80#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:18.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:20:18.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:20:18.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:20:18.80#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:20:18.80#ibcon#first serial, iclass 7, count 0 2006.280.07:20:18.80#ibcon#enter sib2, iclass 7, count 0 2006.280.07:20:18.80#ibcon#flushed, iclass 7, count 0 2006.280.07:20:18.80#ibcon#about to write, iclass 7, count 0 2006.280.07:20:18.80#ibcon#wrote, iclass 7, count 0 2006.280.07:20:18.80#ibcon#about to read 3, iclass 7, count 0 2006.280.07:20:18.82#ibcon#read 3, iclass 7, count 0 2006.280.07:20:18.82#ibcon#about to read 4, iclass 7, count 0 2006.280.07:20:18.82#ibcon#read 4, iclass 7, count 0 2006.280.07:20:18.82#ibcon#about to read 5, iclass 7, count 0 2006.280.07:20:18.82#ibcon#read 5, iclass 7, count 0 2006.280.07:20:18.82#ibcon#about to read 6, iclass 7, count 0 2006.280.07:20:18.82#ibcon#read 6, iclass 7, count 0 2006.280.07:20:18.82#ibcon#end of sib2, iclass 7, count 0 2006.280.07:20:18.82#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:20:18.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:20:18.82#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:20:18.82#ibcon#*before write, iclass 7, count 0 2006.280.07:20:18.82#ibcon#enter sib2, iclass 7, count 0 2006.280.07:20:18.82#ibcon#flushed, iclass 7, count 0 2006.280.07:20:18.82#ibcon#about to write, iclass 7, count 0 2006.280.07:20:18.82#ibcon#wrote, iclass 7, count 0 2006.280.07:20:18.82#ibcon#about to read 3, iclass 7, count 0 2006.280.07:20:18.86#ibcon#read 3, iclass 7, count 0 2006.280.07:20:18.86#ibcon#about to read 4, iclass 7, count 0 2006.280.07:20:18.86#ibcon#read 4, iclass 7, count 0 2006.280.07:20:18.86#ibcon#about to read 5, iclass 7, count 0 2006.280.07:20:18.86#ibcon#read 5, iclass 7, count 0 2006.280.07:20:18.86#ibcon#about to read 6, iclass 7, count 0 2006.280.07:20:18.86#ibcon#read 6, iclass 7, count 0 2006.280.07:20:18.86#ibcon#end of sib2, iclass 7, count 0 2006.280.07:20:18.86#ibcon#*after write, iclass 7, count 0 2006.280.07:20:18.86#ibcon#*before return 0, iclass 7, count 0 2006.280.07:20:18.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:20:18.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:20:18.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:20:18.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:20:18.86$vc4f8/va=8,6 2006.280.07:20:18.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:20:18.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:20:18.86#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:18.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:20:18.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:20:18.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:20:18.93#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:20:18.93#ibcon#first serial, iclass 11, count 2 2006.280.07:20:18.93#ibcon#enter sib2, iclass 11, count 2 2006.280.07:20:18.93#ibcon#flushed, iclass 11, count 2 2006.280.07:20:18.93#ibcon#about to write, iclass 11, count 2 2006.280.07:20:18.93#ibcon#wrote, iclass 11, count 2 2006.280.07:20:18.93#ibcon#about to read 3, iclass 11, count 2 2006.280.07:20:18.94#ibcon#read 3, iclass 11, count 2 2006.280.07:20:18.94#ibcon#about to read 4, iclass 11, count 2 2006.280.07:20:18.94#ibcon#read 4, iclass 11, count 2 2006.280.07:20:18.94#ibcon#about to read 5, iclass 11, count 2 2006.280.07:20:18.94#ibcon#read 5, iclass 11, count 2 2006.280.07:20:18.94#ibcon#about to read 6, iclass 11, count 2 2006.280.07:20:18.94#ibcon#read 6, iclass 11, count 2 2006.280.07:20:18.94#ibcon#end of sib2, iclass 11, count 2 2006.280.07:20:18.94#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:20:18.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:20:18.94#ibcon#[25=AT08-06\r\n] 2006.280.07:20:18.94#ibcon#*before write, iclass 11, count 2 2006.280.07:20:18.94#ibcon#enter sib2, iclass 11, count 2 2006.280.07:20:18.94#ibcon#flushed, iclass 11, count 2 2006.280.07:20:18.94#ibcon#about to write, iclass 11, count 2 2006.280.07:20:18.94#ibcon#wrote, iclass 11, count 2 2006.280.07:20:18.94#ibcon#about to read 3, iclass 11, count 2 2006.280.07:20:18.97#ibcon#read 3, iclass 11, count 2 2006.280.07:20:18.97#ibcon#about to read 4, iclass 11, count 2 2006.280.07:20:18.97#ibcon#read 4, iclass 11, count 2 2006.280.07:20:18.97#ibcon#about to read 5, iclass 11, count 2 2006.280.07:20:18.97#ibcon#read 5, iclass 11, count 2 2006.280.07:20:18.97#ibcon#about to read 6, iclass 11, count 2 2006.280.07:20:18.97#ibcon#read 6, iclass 11, count 2 2006.280.07:20:18.97#ibcon#end of sib2, iclass 11, count 2 2006.280.07:20:18.97#ibcon#*after write, iclass 11, count 2 2006.280.07:20:18.97#ibcon#*before return 0, iclass 11, count 2 2006.280.07:20:18.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:20:18.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:20:18.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:20:18.97#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:18.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:20:19.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:20:19.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:20:19.09#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:20:19.09#ibcon#first serial, iclass 11, count 0 2006.280.07:20:19.09#ibcon#enter sib2, iclass 11, count 0 2006.280.07:20:19.09#ibcon#flushed, iclass 11, count 0 2006.280.07:20:19.09#ibcon#about to write, iclass 11, count 0 2006.280.07:20:19.09#ibcon#wrote, iclass 11, count 0 2006.280.07:20:19.09#ibcon#about to read 3, iclass 11, count 0 2006.280.07:20:19.11#ibcon#read 3, iclass 11, count 0 2006.280.07:20:19.11#ibcon#about to read 4, iclass 11, count 0 2006.280.07:20:19.11#ibcon#read 4, iclass 11, count 0 2006.280.07:20:19.11#ibcon#about to read 5, iclass 11, count 0 2006.280.07:20:19.11#ibcon#read 5, iclass 11, count 0 2006.280.07:20:19.11#ibcon#about to read 6, iclass 11, count 0 2006.280.07:20:19.11#ibcon#read 6, iclass 11, count 0 2006.280.07:20:19.11#ibcon#end of sib2, iclass 11, count 0 2006.280.07:20:19.11#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:20:19.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:20:19.11#ibcon#[25=USB\r\n] 2006.280.07:20:19.11#ibcon#*before write, iclass 11, count 0 2006.280.07:20:19.11#ibcon#enter sib2, iclass 11, count 0 2006.280.07:20:19.11#ibcon#flushed, iclass 11, count 0 2006.280.07:20:19.11#ibcon#about to write, iclass 11, count 0 2006.280.07:20:19.11#ibcon#wrote, iclass 11, count 0 2006.280.07:20:19.11#ibcon#about to read 3, iclass 11, count 0 2006.280.07:20:19.14#ibcon#read 3, iclass 11, count 0 2006.280.07:20:19.14#ibcon#about to read 4, iclass 11, count 0 2006.280.07:20:19.14#ibcon#read 4, iclass 11, count 0 2006.280.07:20:19.14#ibcon#about to read 5, iclass 11, count 0 2006.280.07:20:19.14#ibcon#read 5, iclass 11, count 0 2006.280.07:20:19.14#ibcon#about to read 6, iclass 11, count 0 2006.280.07:20:19.14#ibcon#read 6, iclass 11, count 0 2006.280.07:20:19.14#ibcon#end of sib2, iclass 11, count 0 2006.280.07:20:19.14#ibcon#*after write, iclass 11, count 0 2006.280.07:20:19.14#ibcon#*before return 0, iclass 11, count 0 2006.280.07:20:19.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:20:19.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:20:19.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:20:19.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:20:19.14$vc4f8/vblo=1,632.99 2006.280.07:20:19.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:20:19.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:20:19.14#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:19.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:20:19.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:20:19.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:20:19.14#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:20:19.14#ibcon#first serial, iclass 13, count 0 2006.280.07:20:19.14#ibcon#enter sib2, iclass 13, count 0 2006.280.07:20:19.14#ibcon#flushed, iclass 13, count 0 2006.280.07:20:19.14#ibcon#about to write, iclass 13, count 0 2006.280.07:20:19.14#ibcon#wrote, iclass 13, count 0 2006.280.07:20:19.14#ibcon#about to read 3, iclass 13, count 0 2006.280.07:20:19.16#ibcon#read 3, iclass 13, count 0 2006.280.07:20:19.16#ibcon#about to read 4, iclass 13, count 0 2006.280.07:20:19.16#ibcon#read 4, iclass 13, count 0 2006.280.07:20:19.16#ibcon#about to read 5, iclass 13, count 0 2006.280.07:20:19.16#ibcon#read 5, iclass 13, count 0 2006.280.07:20:19.16#ibcon#about to read 6, iclass 13, count 0 2006.280.07:20:19.16#ibcon#read 6, iclass 13, count 0 2006.280.07:20:19.16#ibcon#end of sib2, iclass 13, count 0 2006.280.07:20:19.16#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:20:19.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:20:19.16#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:20:19.16#ibcon#*before write, iclass 13, count 0 2006.280.07:20:19.16#ibcon#enter sib2, iclass 13, count 0 2006.280.07:20:19.16#ibcon#flushed, iclass 13, count 0 2006.280.07:20:19.16#ibcon#about to write, iclass 13, count 0 2006.280.07:20:19.16#ibcon#wrote, iclass 13, count 0 2006.280.07:20:19.16#ibcon#about to read 3, iclass 13, count 0 2006.280.07:20:19.22#ibcon#read 3, iclass 13, count 0 2006.280.07:20:19.22#ibcon#about to read 4, iclass 13, count 0 2006.280.07:20:19.22#ibcon#read 4, iclass 13, count 0 2006.280.07:20:19.22#ibcon#about to read 5, iclass 13, count 0 2006.280.07:20:19.22#ibcon#read 5, iclass 13, count 0 2006.280.07:20:19.22#ibcon#about to read 6, iclass 13, count 0 2006.280.07:20:19.22#ibcon#read 6, iclass 13, count 0 2006.280.07:20:19.22#ibcon#end of sib2, iclass 13, count 0 2006.280.07:20:19.22#ibcon#*after write, iclass 13, count 0 2006.280.07:20:19.22#ibcon#*before return 0, iclass 13, count 0 2006.280.07:20:19.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:20:19.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:20:19.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:20:19.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:20:19.22$vc4f8/vb=1,4 2006.280.07:20:19.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:20:19.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:20:19.22#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:19.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:20:19.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:20:19.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:20:19.22#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:20:19.22#ibcon#first serial, iclass 15, count 2 2006.280.07:20:19.22#ibcon#enter sib2, iclass 15, count 2 2006.280.07:20:19.22#ibcon#flushed, iclass 15, count 2 2006.280.07:20:19.22#ibcon#about to write, iclass 15, count 2 2006.280.07:20:19.22#ibcon#wrote, iclass 15, count 2 2006.280.07:20:19.22#ibcon#about to read 3, iclass 15, count 2 2006.280.07:20:19.24#ibcon#read 3, iclass 15, count 2 2006.280.07:20:19.24#ibcon#about to read 4, iclass 15, count 2 2006.280.07:20:19.24#ibcon#read 4, iclass 15, count 2 2006.280.07:20:19.24#ibcon#about to read 5, iclass 15, count 2 2006.280.07:20:19.24#ibcon#read 5, iclass 15, count 2 2006.280.07:20:19.24#ibcon#about to read 6, iclass 15, count 2 2006.280.07:20:19.24#ibcon#read 6, iclass 15, count 2 2006.280.07:20:19.24#ibcon#end of sib2, iclass 15, count 2 2006.280.07:20:19.24#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:20:19.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:20:19.24#ibcon#[27=AT01-04\r\n] 2006.280.07:20:19.24#ibcon#*before write, iclass 15, count 2 2006.280.07:20:19.24#ibcon#enter sib2, iclass 15, count 2 2006.280.07:20:19.24#ibcon#flushed, iclass 15, count 2 2006.280.07:20:19.24#ibcon#about to write, iclass 15, count 2 2006.280.07:20:19.24#ibcon#wrote, iclass 15, count 2 2006.280.07:20:19.24#ibcon#about to read 3, iclass 15, count 2 2006.280.07:20:19.28#ibcon#read 3, iclass 15, count 2 2006.280.07:20:19.28#ibcon#about to read 4, iclass 15, count 2 2006.280.07:20:19.28#ibcon#read 4, iclass 15, count 2 2006.280.07:20:19.28#ibcon#about to read 5, iclass 15, count 2 2006.280.07:20:19.28#ibcon#read 5, iclass 15, count 2 2006.280.07:20:19.28#ibcon#about to read 6, iclass 15, count 2 2006.280.07:20:19.28#ibcon#read 6, iclass 15, count 2 2006.280.07:20:19.28#ibcon#end of sib2, iclass 15, count 2 2006.280.07:20:19.28#ibcon#*after write, iclass 15, count 2 2006.280.07:20:19.28#ibcon#*before return 0, iclass 15, count 2 2006.280.07:20:19.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:20:19.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:20:19.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:20:19.28#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:19.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:20:19.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:20:19.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:20:19.40#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:20:19.40#ibcon#first serial, iclass 15, count 0 2006.280.07:20:19.40#ibcon#enter sib2, iclass 15, count 0 2006.280.07:20:19.40#ibcon#flushed, iclass 15, count 0 2006.280.07:20:19.40#ibcon#about to write, iclass 15, count 0 2006.280.07:20:19.40#ibcon#wrote, iclass 15, count 0 2006.280.07:20:19.40#ibcon#about to read 3, iclass 15, count 0 2006.280.07:20:19.43#ibcon#read 3, iclass 15, count 0 2006.280.07:20:19.43#ibcon#about to read 4, iclass 15, count 0 2006.280.07:20:19.43#ibcon#read 4, iclass 15, count 0 2006.280.07:20:19.43#ibcon#about to read 5, iclass 15, count 0 2006.280.07:20:19.43#ibcon#read 5, iclass 15, count 0 2006.280.07:20:19.43#ibcon#about to read 6, iclass 15, count 0 2006.280.07:20:19.43#ibcon#read 6, iclass 15, count 0 2006.280.07:20:19.43#ibcon#end of sib2, iclass 15, count 0 2006.280.07:20:19.43#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:20:19.43#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:20:19.43#ibcon#[27=USB\r\n] 2006.280.07:20:19.43#ibcon#*before write, iclass 15, count 0 2006.280.07:20:19.43#ibcon#enter sib2, iclass 15, count 0 2006.280.07:20:19.43#ibcon#flushed, iclass 15, count 0 2006.280.07:20:19.43#ibcon#about to write, iclass 15, count 0 2006.280.07:20:19.43#ibcon#wrote, iclass 15, count 0 2006.280.07:20:19.43#ibcon#about to read 3, iclass 15, count 0 2006.280.07:20:19.46#ibcon#read 3, iclass 15, count 0 2006.280.07:20:19.46#ibcon#about to read 4, iclass 15, count 0 2006.280.07:20:19.46#ibcon#read 4, iclass 15, count 0 2006.280.07:20:19.46#ibcon#about to read 5, iclass 15, count 0 2006.280.07:20:19.46#ibcon#read 5, iclass 15, count 0 2006.280.07:20:19.46#ibcon#about to read 6, iclass 15, count 0 2006.280.07:20:19.46#ibcon#read 6, iclass 15, count 0 2006.280.07:20:19.46#ibcon#end of sib2, iclass 15, count 0 2006.280.07:20:19.46#ibcon#*after write, iclass 15, count 0 2006.280.07:20:19.46#ibcon#*before return 0, iclass 15, count 0 2006.280.07:20:19.46#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:20:19.46#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:20:19.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:20:19.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:20:19.46$vc4f8/vblo=2,640.99 2006.280.07:20:19.46#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:20:19.46#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:20:19.46#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:19.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:19.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:19.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:19.46#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:20:19.46#ibcon#first serial, iclass 17, count 0 2006.280.07:20:19.46#ibcon#enter sib2, iclass 17, count 0 2006.280.07:20:19.46#ibcon#flushed, iclass 17, count 0 2006.280.07:20:19.46#ibcon#about to write, iclass 17, count 0 2006.280.07:20:19.46#ibcon#wrote, iclass 17, count 0 2006.280.07:20:19.46#ibcon#about to read 3, iclass 17, count 0 2006.280.07:20:19.48#ibcon#read 3, iclass 17, count 0 2006.280.07:20:19.48#ibcon#about to read 4, iclass 17, count 0 2006.280.07:20:19.48#ibcon#read 4, iclass 17, count 0 2006.280.07:20:19.48#ibcon#about to read 5, iclass 17, count 0 2006.280.07:20:19.48#ibcon#read 5, iclass 17, count 0 2006.280.07:20:19.48#ibcon#about to read 6, iclass 17, count 0 2006.280.07:20:19.48#ibcon#read 6, iclass 17, count 0 2006.280.07:20:19.48#ibcon#end of sib2, iclass 17, count 0 2006.280.07:20:19.48#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:20:19.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:20:19.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:20:19.48#ibcon#*before write, iclass 17, count 0 2006.280.07:20:19.48#ibcon#enter sib2, iclass 17, count 0 2006.280.07:20:19.48#ibcon#flushed, iclass 17, count 0 2006.280.07:20:19.48#ibcon#about to write, iclass 17, count 0 2006.280.07:20:19.48#ibcon#wrote, iclass 17, count 0 2006.280.07:20:19.48#ibcon#about to read 3, iclass 17, count 0 2006.280.07:20:19.52#ibcon#read 3, iclass 17, count 0 2006.280.07:20:19.52#ibcon#about to read 4, iclass 17, count 0 2006.280.07:20:19.52#ibcon#read 4, iclass 17, count 0 2006.280.07:20:19.52#ibcon#about to read 5, iclass 17, count 0 2006.280.07:20:19.52#ibcon#read 5, iclass 17, count 0 2006.280.07:20:19.52#ibcon#about to read 6, iclass 17, count 0 2006.280.07:20:19.52#ibcon#read 6, iclass 17, count 0 2006.280.07:20:19.52#ibcon#end of sib2, iclass 17, count 0 2006.280.07:20:19.52#ibcon#*after write, iclass 17, count 0 2006.280.07:20:19.52#ibcon#*before return 0, iclass 17, count 0 2006.280.07:20:19.52#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:19.52#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:20:19.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:20:19.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:20:19.52$vc4f8/vb=2,5 2006.280.07:20:19.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:20:19.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:20:19.53#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:19.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:19.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:19.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:19.57#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:20:19.57#ibcon#first serial, iclass 19, count 2 2006.280.07:20:19.57#ibcon#enter sib2, iclass 19, count 2 2006.280.07:20:19.57#ibcon#flushed, iclass 19, count 2 2006.280.07:20:19.57#ibcon#about to write, iclass 19, count 2 2006.280.07:20:19.57#ibcon#wrote, iclass 19, count 2 2006.280.07:20:19.57#ibcon#about to read 3, iclass 19, count 2 2006.280.07:20:19.59#ibcon#read 3, iclass 19, count 2 2006.280.07:20:19.59#ibcon#about to read 4, iclass 19, count 2 2006.280.07:20:19.59#ibcon#read 4, iclass 19, count 2 2006.280.07:20:19.59#ibcon#about to read 5, iclass 19, count 2 2006.280.07:20:19.59#ibcon#read 5, iclass 19, count 2 2006.280.07:20:19.59#ibcon#about to read 6, iclass 19, count 2 2006.280.07:20:19.59#ibcon#read 6, iclass 19, count 2 2006.280.07:20:19.59#ibcon#end of sib2, iclass 19, count 2 2006.280.07:20:19.59#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:20:19.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:20:19.59#ibcon#[27=AT02-05\r\n] 2006.280.07:20:19.59#ibcon#*before write, iclass 19, count 2 2006.280.07:20:19.59#ibcon#enter sib2, iclass 19, count 2 2006.280.07:20:19.59#ibcon#flushed, iclass 19, count 2 2006.280.07:20:19.59#ibcon#about to write, iclass 19, count 2 2006.280.07:20:19.59#ibcon#wrote, iclass 19, count 2 2006.280.07:20:19.59#ibcon#about to read 3, iclass 19, count 2 2006.280.07:20:19.62#ibcon#read 3, iclass 19, count 2 2006.280.07:20:19.62#ibcon#about to read 4, iclass 19, count 2 2006.280.07:20:19.62#ibcon#read 4, iclass 19, count 2 2006.280.07:20:19.62#ibcon#about to read 5, iclass 19, count 2 2006.280.07:20:19.62#ibcon#read 5, iclass 19, count 2 2006.280.07:20:19.62#ibcon#about to read 6, iclass 19, count 2 2006.280.07:20:19.62#ibcon#read 6, iclass 19, count 2 2006.280.07:20:19.62#ibcon#end of sib2, iclass 19, count 2 2006.280.07:20:19.62#ibcon#*after write, iclass 19, count 2 2006.280.07:20:19.62#ibcon#*before return 0, iclass 19, count 2 2006.280.07:20:19.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:19.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:20:19.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:20:19.62#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:19.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:19.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:19.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:19.74#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:20:19.74#ibcon#first serial, iclass 19, count 0 2006.280.07:20:19.74#ibcon#enter sib2, iclass 19, count 0 2006.280.07:20:19.74#ibcon#flushed, iclass 19, count 0 2006.280.07:20:19.74#ibcon#about to write, iclass 19, count 0 2006.280.07:20:19.74#ibcon#wrote, iclass 19, count 0 2006.280.07:20:19.74#ibcon#about to read 3, iclass 19, count 0 2006.280.07:20:19.76#ibcon#read 3, iclass 19, count 0 2006.280.07:20:19.76#ibcon#about to read 4, iclass 19, count 0 2006.280.07:20:19.76#ibcon#read 4, iclass 19, count 0 2006.280.07:20:19.76#ibcon#about to read 5, iclass 19, count 0 2006.280.07:20:19.76#ibcon#read 5, iclass 19, count 0 2006.280.07:20:19.76#ibcon#about to read 6, iclass 19, count 0 2006.280.07:20:19.76#ibcon#read 6, iclass 19, count 0 2006.280.07:20:19.76#ibcon#end of sib2, iclass 19, count 0 2006.280.07:20:19.76#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:20:19.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:20:19.76#ibcon#[27=USB\r\n] 2006.280.07:20:19.76#ibcon#*before write, iclass 19, count 0 2006.280.07:20:19.76#ibcon#enter sib2, iclass 19, count 0 2006.280.07:20:19.76#ibcon#flushed, iclass 19, count 0 2006.280.07:20:19.76#ibcon#about to write, iclass 19, count 0 2006.280.07:20:19.76#ibcon#wrote, iclass 19, count 0 2006.280.07:20:19.76#ibcon#about to read 3, iclass 19, count 0 2006.280.07:20:19.79#ibcon#read 3, iclass 19, count 0 2006.280.07:20:19.79#ibcon#about to read 4, iclass 19, count 0 2006.280.07:20:19.79#ibcon#read 4, iclass 19, count 0 2006.280.07:20:19.79#ibcon#about to read 5, iclass 19, count 0 2006.280.07:20:19.79#ibcon#read 5, iclass 19, count 0 2006.280.07:20:19.79#ibcon#about to read 6, iclass 19, count 0 2006.280.07:20:19.79#ibcon#read 6, iclass 19, count 0 2006.280.07:20:19.79#ibcon#end of sib2, iclass 19, count 0 2006.280.07:20:19.79#ibcon#*after write, iclass 19, count 0 2006.280.07:20:19.79#ibcon#*before return 0, iclass 19, count 0 2006.280.07:20:19.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:19.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:20:19.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:20:19.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:20:19.79$vc4f8/vblo=3,656.99 2006.280.07:20:19.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:20:19.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:20:19.79#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:19.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:19.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:19.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:19.79#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:20:19.79#ibcon#first serial, iclass 21, count 0 2006.280.07:20:19.79#ibcon#enter sib2, iclass 21, count 0 2006.280.07:20:19.79#ibcon#flushed, iclass 21, count 0 2006.280.07:20:19.79#ibcon#about to write, iclass 21, count 0 2006.280.07:20:19.79#ibcon#wrote, iclass 21, count 0 2006.280.07:20:19.79#ibcon#about to read 3, iclass 21, count 0 2006.280.07:20:19.81#ibcon#read 3, iclass 21, count 0 2006.280.07:20:19.81#ibcon#about to read 4, iclass 21, count 0 2006.280.07:20:19.81#ibcon#read 4, iclass 21, count 0 2006.280.07:20:19.81#ibcon#about to read 5, iclass 21, count 0 2006.280.07:20:19.81#ibcon#read 5, iclass 21, count 0 2006.280.07:20:19.81#ibcon#about to read 6, iclass 21, count 0 2006.280.07:20:19.81#ibcon#read 6, iclass 21, count 0 2006.280.07:20:19.81#ibcon#end of sib2, iclass 21, count 0 2006.280.07:20:19.81#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:20:19.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:20:19.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:20:19.81#ibcon#*before write, iclass 21, count 0 2006.280.07:20:19.81#ibcon#enter sib2, iclass 21, count 0 2006.280.07:20:19.81#ibcon#flushed, iclass 21, count 0 2006.280.07:20:19.81#ibcon#about to write, iclass 21, count 0 2006.280.07:20:19.81#ibcon#wrote, iclass 21, count 0 2006.280.07:20:19.81#ibcon#about to read 3, iclass 21, count 0 2006.280.07:20:19.85#ibcon#read 3, iclass 21, count 0 2006.280.07:20:19.85#ibcon#about to read 4, iclass 21, count 0 2006.280.07:20:19.85#ibcon#read 4, iclass 21, count 0 2006.280.07:20:19.85#ibcon#about to read 5, iclass 21, count 0 2006.280.07:20:19.85#ibcon#read 5, iclass 21, count 0 2006.280.07:20:19.85#ibcon#about to read 6, iclass 21, count 0 2006.280.07:20:19.85#ibcon#read 6, iclass 21, count 0 2006.280.07:20:19.85#ibcon#end of sib2, iclass 21, count 0 2006.280.07:20:19.85#ibcon#*after write, iclass 21, count 0 2006.280.07:20:19.85#ibcon#*before return 0, iclass 21, count 0 2006.280.07:20:19.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:19.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:20:19.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:20:19.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:20:19.85$vc4f8/vb=3,4 2006.280.07:20:19.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:20:19.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:20:19.85#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:19.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:19.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:19.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:19.91#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:20:19.91#ibcon#first serial, iclass 23, count 2 2006.280.07:20:19.91#ibcon#enter sib2, iclass 23, count 2 2006.280.07:20:19.91#ibcon#flushed, iclass 23, count 2 2006.280.07:20:19.91#ibcon#about to write, iclass 23, count 2 2006.280.07:20:19.91#ibcon#wrote, iclass 23, count 2 2006.280.07:20:19.91#ibcon#about to read 3, iclass 23, count 2 2006.280.07:20:19.93#ibcon#read 3, iclass 23, count 2 2006.280.07:20:19.93#ibcon#about to read 4, iclass 23, count 2 2006.280.07:20:19.93#ibcon#read 4, iclass 23, count 2 2006.280.07:20:19.93#ibcon#about to read 5, iclass 23, count 2 2006.280.07:20:19.93#ibcon#read 5, iclass 23, count 2 2006.280.07:20:19.93#ibcon#about to read 6, iclass 23, count 2 2006.280.07:20:19.93#ibcon#read 6, iclass 23, count 2 2006.280.07:20:19.93#ibcon#end of sib2, iclass 23, count 2 2006.280.07:20:19.93#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:20:19.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:20:19.93#ibcon#[27=AT03-04\r\n] 2006.280.07:20:19.93#ibcon#*before write, iclass 23, count 2 2006.280.07:20:19.93#ibcon#enter sib2, iclass 23, count 2 2006.280.07:20:19.93#ibcon#flushed, iclass 23, count 2 2006.280.07:20:19.93#ibcon#about to write, iclass 23, count 2 2006.280.07:20:19.93#ibcon#wrote, iclass 23, count 2 2006.280.07:20:19.93#ibcon#about to read 3, iclass 23, count 2 2006.280.07:20:19.96#ibcon#read 3, iclass 23, count 2 2006.280.07:20:19.96#ibcon#about to read 4, iclass 23, count 2 2006.280.07:20:19.96#ibcon#read 4, iclass 23, count 2 2006.280.07:20:19.96#ibcon#about to read 5, iclass 23, count 2 2006.280.07:20:19.96#ibcon#read 5, iclass 23, count 2 2006.280.07:20:19.96#ibcon#about to read 6, iclass 23, count 2 2006.280.07:20:19.96#ibcon#read 6, iclass 23, count 2 2006.280.07:20:19.96#ibcon#end of sib2, iclass 23, count 2 2006.280.07:20:19.96#ibcon#*after write, iclass 23, count 2 2006.280.07:20:19.96#ibcon#*before return 0, iclass 23, count 2 2006.280.07:20:19.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:19.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:20:19.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:20:19.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:19.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:20.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:20.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:20.08#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:20:20.08#ibcon#first serial, iclass 23, count 0 2006.280.07:20:20.08#ibcon#enter sib2, iclass 23, count 0 2006.280.07:20:20.08#ibcon#flushed, iclass 23, count 0 2006.280.07:20:20.08#ibcon#about to write, iclass 23, count 0 2006.280.07:20:20.08#ibcon#wrote, iclass 23, count 0 2006.280.07:20:20.08#ibcon#about to read 3, iclass 23, count 0 2006.280.07:20:20.10#ibcon#read 3, iclass 23, count 0 2006.280.07:20:20.10#ibcon#about to read 4, iclass 23, count 0 2006.280.07:20:20.10#ibcon#read 4, iclass 23, count 0 2006.280.07:20:20.10#ibcon#about to read 5, iclass 23, count 0 2006.280.07:20:20.10#ibcon#read 5, iclass 23, count 0 2006.280.07:20:20.10#ibcon#about to read 6, iclass 23, count 0 2006.280.07:20:20.10#ibcon#read 6, iclass 23, count 0 2006.280.07:20:20.10#ibcon#end of sib2, iclass 23, count 0 2006.280.07:20:20.10#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:20:20.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:20:20.10#ibcon#[27=USB\r\n] 2006.280.07:20:20.10#ibcon#*before write, iclass 23, count 0 2006.280.07:20:20.10#ibcon#enter sib2, iclass 23, count 0 2006.280.07:20:20.10#ibcon#flushed, iclass 23, count 0 2006.280.07:20:20.10#ibcon#about to write, iclass 23, count 0 2006.280.07:20:20.10#ibcon#wrote, iclass 23, count 0 2006.280.07:20:20.10#ibcon#about to read 3, iclass 23, count 0 2006.280.07:20:20.13#ibcon#read 3, iclass 23, count 0 2006.280.07:20:20.13#ibcon#about to read 4, iclass 23, count 0 2006.280.07:20:20.13#ibcon#read 4, iclass 23, count 0 2006.280.07:20:20.13#ibcon#about to read 5, iclass 23, count 0 2006.280.07:20:20.13#ibcon#read 5, iclass 23, count 0 2006.280.07:20:20.13#ibcon#about to read 6, iclass 23, count 0 2006.280.07:20:20.13#ibcon#read 6, iclass 23, count 0 2006.280.07:20:20.13#ibcon#end of sib2, iclass 23, count 0 2006.280.07:20:20.13#ibcon#*after write, iclass 23, count 0 2006.280.07:20:20.13#ibcon#*before return 0, iclass 23, count 0 2006.280.07:20:20.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:20.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:20:20.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:20:20.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:20:20.13$vc4f8/vblo=4,712.99 2006.280.07:20:20.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:20:20.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:20:20.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:20.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:20.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:20.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:20.13#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:20:20.13#ibcon#first serial, iclass 25, count 0 2006.280.07:20:20.13#ibcon#enter sib2, iclass 25, count 0 2006.280.07:20:20.13#ibcon#flushed, iclass 25, count 0 2006.280.07:20:20.13#ibcon#about to write, iclass 25, count 0 2006.280.07:20:20.13#ibcon#wrote, iclass 25, count 0 2006.280.07:20:20.13#ibcon#about to read 3, iclass 25, count 0 2006.280.07:20:20.15#ibcon#read 3, iclass 25, count 0 2006.280.07:20:20.15#ibcon#about to read 4, iclass 25, count 0 2006.280.07:20:20.15#ibcon#read 4, iclass 25, count 0 2006.280.07:20:20.15#ibcon#about to read 5, iclass 25, count 0 2006.280.07:20:20.15#ibcon#read 5, iclass 25, count 0 2006.280.07:20:20.15#ibcon#about to read 6, iclass 25, count 0 2006.280.07:20:20.15#ibcon#read 6, iclass 25, count 0 2006.280.07:20:20.15#ibcon#end of sib2, iclass 25, count 0 2006.280.07:20:20.15#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:20:20.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:20:20.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:20:20.15#ibcon#*before write, iclass 25, count 0 2006.280.07:20:20.15#ibcon#enter sib2, iclass 25, count 0 2006.280.07:20:20.15#ibcon#flushed, iclass 25, count 0 2006.280.07:20:20.15#ibcon#about to write, iclass 25, count 0 2006.280.07:20:20.15#ibcon#wrote, iclass 25, count 0 2006.280.07:20:20.15#ibcon#about to read 3, iclass 25, count 0 2006.280.07:20:20.19#ibcon#read 3, iclass 25, count 0 2006.280.07:20:20.19#ibcon#about to read 4, iclass 25, count 0 2006.280.07:20:20.19#ibcon#read 4, iclass 25, count 0 2006.280.07:20:20.19#ibcon#about to read 5, iclass 25, count 0 2006.280.07:20:20.19#ibcon#read 5, iclass 25, count 0 2006.280.07:20:20.19#ibcon#about to read 6, iclass 25, count 0 2006.280.07:20:20.19#ibcon#read 6, iclass 25, count 0 2006.280.07:20:20.19#ibcon#end of sib2, iclass 25, count 0 2006.280.07:20:20.19#ibcon#*after write, iclass 25, count 0 2006.280.07:20:20.19#ibcon#*before return 0, iclass 25, count 0 2006.280.07:20:20.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:20.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:20:20.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:20:20.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:20:20.19$vc4f8/vb=4,4 2006.280.07:20:20.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:20:20.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:20:20.19#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:20.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:20.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:20.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:20.25#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:20:20.25#ibcon#first serial, iclass 27, count 2 2006.280.07:20:20.25#ibcon#enter sib2, iclass 27, count 2 2006.280.07:20:20.25#ibcon#flushed, iclass 27, count 2 2006.280.07:20:20.25#ibcon#about to write, iclass 27, count 2 2006.280.07:20:20.25#ibcon#wrote, iclass 27, count 2 2006.280.07:20:20.25#ibcon#about to read 3, iclass 27, count 2 2006.280.07:20:20.27#ibcon#read 3, iclass 27, count 2 2006.280.07:20:20.27#ibcon#about to read 4, iclass 27, count 2 2006.280.07:20:20.27#ibcon#read 4, iclass 27, count 2 2006.280.07:20:20.27#ibcon#about to read 5, iclass 27, count 2 2006.280.07:20:20.27#ibcon#read 5, iclass 27, count 2 2006.280.07:20:20.27#ibcon#about to read 6, iclass 27, count 2 2006.280.07:20:20.27#ibcon#read 6, iclass 27, count 2 2006.280.07:20:20.27#ibcon#end of sib2, iclass 27, count 2 2006.280.07:20:20.27#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:20:20.27#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:20:20.27#ibcon#[27=AT04-04\r\n] 2006.280.07:20:20.27#ibcon#*before write, iclass 27, count 2 2006.280.07:20:20.27#ibcon#enter sib2, iclass 27, count 2 2006.280.07:20:20.27#ibcon#flushed, iclass 27, count 2 2006.280.07:20:20.27#ibcon#about to write, iclass 27, count 2 2006.280.07:20:20.27#ibcon#wrote, iclass 27, count 2 2006.280.07:20:20.27#ibcon#about to read 3, iclass 27, count 2 2006.280.07:20:20.30#ibcon#read 3, iclass 27, count 2 2006.280.07:20:20.30#ibcon#about to read 4, iclass 27, count 2 2006.280.07:20:20.30#ibcon#read 4, iclass 27, count 2 2006.280.07:20:20.30#ibcon#about to read 5, iclass 27, count 2 2006.280.07:20:20.30#ibcon#read 5, iclass 27, count 2 2006.280.07:20:20.30#ibcon#about to read 6, iclass 27, count 2 2006.280.07:20:20.30#ibcon#read 6, iclass 27, count 2 2006.280.07:20:20.30#ibcon#end of sib2, iclass 27, count 2 2006.280.07:20:20.30#ibcon#*after write, iclass 27, count 2 2006.280.07:20:20.30#ibcon#*before return 0, iclass 27, count 2 2006.280.07:20:20.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:20.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:20:20.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:20:20.30#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:20.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:20.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:20.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:20.42#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:20:20.42#ibcon#first serial, iclass 27, count 0 2006.280.07:20:20.42#ibcon#enter sib2, iclass 27, count 0 2006.280.07:20:20.42#ibcon#flushed, iclass 27, count 0 2006.280.07:20:20.42#ibcon#about to write, iclass 27, count 0 2006.280.07:20:20.42#ibcon#wrote, iclass 27, count 0 2006.280.07:20:20.42#ibcon#about to read 3, iclass 27, count 0 2006.280.07:20:20.44#ibcon#read 3, iclass 27, count 0 2006.280.07:20:20.44#ibcon#about to read 4, iclass 27, count 0 2006.280.07:20:20.44#ibcon#read 4, iclass 27, count 0 2006.280.07:20:20.44#ibcon#about to read 5, iclass 27, count 0 2006.280.07:20:20.44#ibcon#read 5, iclass 27, count 0 2006.280.07:20:20.44#ibcon#about to read 6, iclass 27, count 0 2006.280.07:20:20.44#ibcon#read 6, iclass 27, count 0 2006.280.07:20:20.44#ibcon#end of sib2, iclass 27, count 0 2006.280.07:20:20.44#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:20:20.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:20:20.44#ibcon#[27=USB\r\n] 2006.280.07:20:20.44#ibcon#*before write, iclass 27, count 0 2006.280.07:20:20.44#ibcon#enter sib2, iclass 27, count 0 2006.280.07:20:20.44#ibcon#flushed, iclass 27, count 0 2006.280.07:20:20.44#ibcon#about to write, iclass 27, count 0 2006.280.07:20:20.44#ibcon#wrote, iclass 27, count 0 2006.280.07:20:20.44#ibcon#about to read 3, iclass 27, count 0 2006.280.07:20:20.47#ibcon#read 3, iclass 27, count 0 2006.280.07:20:20.47#ibcon#about to read 4, iclass 27, count 0 2006.280.07:20:20.47#ibcon#read 4, iclass 27, count 0 2006.280.07:20:20.47#ibcon#about to read 5, iclass 27, count 0 2006.280.07:20:20.47#ibcon#read 5, iclass 27, count 0 2006.280.07:20:20.47#ibcon#about to read 6, iclass 27, count 0 2006.280.07:20:20.47#ibcon#read 6, iclass 27, count 0 2006.280.07:20:20.47#ibcon#end of sib2, iclass 27, count 0 2006.280.07:20:20.47#ibcon#*after write, iclass 27, count 0 2006.280.07:20:20.47#ibcon#*before return 0, iclass 27, count 0 2006.280.07:20:20.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:20.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:20:20.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:20:20.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:20:20.47$vc4f8/vblo=5,744.99 2006.280.07:20:20.47#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:20:20.47#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:20:20.47#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:20.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:20.47#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:20.47#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:20.47#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:20:20.47#ibcon#first serial, iclass 29, count 0 2006.280.07:20:20.47#ibcon#enter sib2, iclass 29, count 0 2006.280.07:20:20.47#ibcon#flushed, iclass 29, count 0 2006.280.07:20:20.47#ibcon#about to write, iclass 29, count 0 2006.280.07:20:20.47#ibcon#wrote, iclass 29, count 0 2006.280.07:20:20.47#ibcon#about to read 3, iclass 29, count 0 2006.280.07:20:20.49#ibcon#read 3, iclass 29, count 0 2006.280.07:20:20.49#ibcon#about to read 4, iclass 29, count 0 2006.280.07:20:20.49#ibcon#read 4, iclass 29, count 0 2006.280.07:20:20.49#ibcon#about to read 5, iclass 29, count 0 2006.280.07:20:20.49#ibcon#read 5, iclass 29, count 0 2006.280.07:20:20.49#ibcon#about to read 6, iclass 29, count 0 2006.280.07:20:20.49#ibcon#read 6, iclass 29, count 0 2006.280.07:20:20.49#ibcon#end of sib2, iclass 29, count 0 2006.280.07:20:20.49#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:20:20.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:20:20.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:20:20.49#ibcon#*before write, iclass 29, count 0 2006.280.07:20:20.49#ibcon#enter sib2, iclass 29, count 0 2006.280.07:20:20.49#ibcon#flushed, iclass 29, count 0 2006.280.07:20:20.49#ibcon#about to write, iclass 29, count 0 2006.280.07:20:20.49#ibcon#wrote, iclass 29, count 0 2006.280.07:20:20.49#ibcon#about to read 3, iclass 29, count 0 2006.280.07:20:20.53#ibcon#read 3, iclass 29, count 0 2006.280.07:20:20.53#ibcon#about to read 4, iclass 29, count 0 2006.280.07:20:20.53#ibcon#read 4, iclass 29, count 0 2006.280.07:20:20.53#ibcon#about to read 5, iclass 29, count 0 2006.280.07:20:20.53#ibcon#read 5, iclass 29, count 0 2006.280.07:20:20.53#ibcon#about to read 6, iclass 29, count 0 2006.280.07:20:20.53#ibcon#read 6, iclass 29, count 0 2006.280.07:20:20.53#ibcon#end of sib2, iclass 29, count 0 2006.280.07:20:20.53#ibcon#*after write, iclass 29, count 0 2006.280.07:20:20.53#ibcon#*before return 0, iclass 29, count 0 2006.280.07:20:20.53#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:20.53#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:20:20.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:20:20.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:20:20.53$vc4f8/vb=5,4 2006.280.07:20:20.53#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:20:20.53#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:20:20.53#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:20.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:20.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:20.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:20.59#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:20:20.59#ibcon#first serial, iclass 31, count 2 2006.280.07:20:20.59#ibcon#enter sib2, iclass 31, count 2 2006.280.07:20:20.59#ibcon#flushed, iclass 31, count 2 2006.280.07:20:20.59#ibcon#about to write, iclass 31, count 2 2006.280.07:20:20.59#ibcon#wrote, iclass 31, count 2 2006.280.07:20:20.59#ibcon#about to read 3, iclass 31, count 2 2006.280.07:20:20.61#ibcon#read 3, iclass 31, count 2 2006.280.07:20:20.61#ibcon#about to read 4, iclass 31, count 2 2006.280.07:20:20.61#ibcon#read 4, iclass 31, count 2 2006.280.07:20:20.61#ibcon#about to read 5, iclass 31, count 2 2006.280.07:20:20.61#ibcon#read 5, iclass 31, count 2 2006.280.07:20:20.61#ibcon#about to read 6, iclass 31, count 2 2006.280.07:20:20.61#ibcon#read 6, iclass 31, count 2 2006.280.07:20:20.61#ibcon#end of sib2, iclass 31, count 2 2006.280.07:20:20.61#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:20:20.61#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:20:20.61#ibcon#[27=AT05-04\r\n] 2006.280.07:20:20.61#ibcon#*before write, iclass 31, count 2 2006.280.07:20:20.61#ibcon#enter sib2, iclass 31, count 2 2006.280.07:20:20.61#ibcon#flushed, iclass 31, count 2 2006.280.07:20:20.61#ibcon#about to write, iclass 31, count 2 2006.280.07:20:20.61#ibcon#wrote, iclass 31, count 2 2006.280.07:20:20.61#ibcon#about to read 3, iclass 31, count 2 2006.280.07:20:20.64#ibcon#read 3, iclass 31, count 2 2006.280.07:20:20.64#ibcon#about to read 4, iclass 31, count 2 2006.280.07:20:20.64#ibcon#read 4, iclass 31, count 2 2006.280.07:20:20.64#ibcon#about to read 5, iclass 31, count 2 2006.280.07:20:20.64#ibcon#read 5, iclass 31, count 2 2006.280.07:20:20.64#ibcon#about to read 6, iclass 31, count 2 2006.280.07:20:20.64#ibcon#read 6, iclass 31, count 2 2006.280.07:20:20.64#ibcon#end of sib2, iclass 31, count 2 2006.280.07:20:20.64#ibcon#*after write, iclass 31, count 2 2006.280.07:20:20.64#ibcon#*before return 0, iclass 31, count 2 2006.280.07:20:20.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:20.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:20:20.64#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:20:20.64#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:20.64#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:20.76#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:20.76#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:20.76#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:20:20.76#ibcon#first serial, iclass 31, count 0 2006.280.07:20:20.76#ibcon#enter sib2, iclass 31, count 0 2006.280.07:20:20.76#ibcon#flushed, iclass 31, count 0 2006.280.07:20:20.76#ibcon#about to write, iclass 31, count 0 2006.280.07:20:20.76#ibcon#wrote, iclass 31, count 0 2006.280.07:20:20.76#ibcon#about to read 3, iclass 31, count 0 2006.280.07:20:20.78#ibcon#read 3, iclass 31, count 0 2006.280.07:20:20.78#ibcon#about to read 4, iclass 31, count 0 2006.280.07:20:20.78#ibcon#read 4, iclass 31, count 0 2006.280.07:20:20.78#ibcon#about to read 5, iclass 31, count 0 2006.280.07:20:20.78#ibcon#read 5, iclass 31, count 0 2006.280.07:20:20.78#ibcon#about to read 6, iclass 31, count 0 2006.280.07:20:20.78#ibcon#read 6, iclass 31, count 0 2006.280.07:20:20.78#ibcon#end of sib2, iclass 31, count 0 2006.280.07:20:20.78#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:20:20.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:20:20.78#ibcon#[27=USB\r\n] 2006.280.07:20:20.78#ibcon#*before write, iclass 31, count 0 2006.280.07:20:20.78#ibcon#enter sib2, iclass 31, count 0 2006.280.07:20:20.78#ibcon#flushed, iclass 31, count 0 2006.280.07:20:20.78#ibcon#about to write, iclass 31, count 0 2006.280.07:20:20.78#ibcon#wrote, iclass 31, count 0 2006.280.07:20:20.78#ibcon#about to read 3, iclass 31, count 0 2006.280.07:20:20.81#ibcon#read 3, iclass 31, count 0 2006.280.07:20:20.81#ibcon#about to read 4, iclass 31, count 0 2006.280.07:20:20.81#ibcon#read 4, iclass 31, count 0 2006.280.07:20:20.81#ibcon#about to read 5, iclass 31, count 0 2006.280.07:20:20.81#ibcon#read 5, iclass 31, count 0 2006.280.07:20:20.81#ibcon#about to read 6, iclass 31, count 0 2006.280.07:20:20.81#ibcon#read 6, iclass 31, count 0 2006.280.07:20:20.81#ibcon#end of sib2, iclass 31, count 0 2006.280.07:20:20.81#ibcon#*after write, iclass 31, count 0 2006.280.07:20:20.81#ibcon#*before return 0, iclass 31, count 0 2006.280.07:20:20.81#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:20.81#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:20:20.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:20:20.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:20:20.81$vc4f8/vblo=6,752.99 2006.280.07:20:20.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:20:20.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:20:20.81#ibcon#ireg 17 cls_cnt 0 2006.280.07:20:20.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:20.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:20.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:20.81#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:20:20.81#ibcon#first serial, iclass 33, count 0 2006.280.07:20:20.81#ibcon#enter sib2, iclass 33, count 0 2006.280.07:20:20.81#ibcon#flushed, iclass 33, count 0 2006.280.07:20:20.81#ibcon#about to write, iclass 33, count 0 2006.280.07:20:20.81#ibcon#wrote, iclass 33, count 0 2006.280.07:20:20.81#ibcon#about to read 3, iclass 33, count 0 2006.280.07:20:20.83#ibcon#read 3, iclass 33, count 0 2006.280.07:20:20.83#ibcon#about to read 4, iclass 33, count 0 2006.280.07:20:20.83#ibcon#read 4, iclass 33, count 0 2006.280.07:20:20.83#ibcon#about to read 5, iclass 33, count 0 2006.280.07:20:20.83#ibcon#read 5, iclass 33, count 0 2006.280.07:20:20.83#ibcon#about to read 6, iclass 33, count 0 2006.280.07:20:20.83#ibcon#read 6, iclass 33, count 0 2006.280.07:20:20.83#ibcon#end of sib2, iclass 33, count 0 2006.280.07:20:20.83#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:20:20.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:20:20.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:20:20.83#ibcon#*before write, iclass 33, count 0 2006.280.07:20:20.83#ibcon#enter sib2, iclass 33, count 0 2006.280.07:20:20.83#ibcon#flushed, iclass 33, count 0 2006.280.07:20:20.83#ibcon#about to write, iclass 33, count 0 2006.280.07:20:20.83#ibcon#wrote, iclass 33, count 0 2006.280.07:20:20.83#ibcon#about to read 3, iclass 33, count 0 2006.280.07:20:20.87#ibcon#read 3, iclass 33, count 0 2006.280.07:20:20.87#ibcon#about to read 4, iclass 33, count 0 2006.280.07:20:20.87#ibcon#read 4, iclass 33, count 0 2006.280.07:20:20.87#ibcon#about to read 5, iclass 33, count 0 2006.280.07:20:20.87#ibcon#read 5, iclass 33, count 0 2006.280.07:20:20.87#ibcon#about to read 6, iclass 33, count 0 2006.280.07:20:20.87#ibcon#read 6, iclass 33, count 0 2006.280.07:20:20.87#ibcon#end of sib2, iclass 33, count 0 2006.280.07:20:20.87#ibcon#*after write, iclass 33, count 0 2006.280.07:20:20.87#ibcon#*before return 0, iclass 33, count 0 2006.280.07:20:20.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:20.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:20:20.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:20:20.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:20:20.87$vc4f8/vb=6,4 2006.280.07:20:20.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:20:20.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:20:20.87#ibcon#ireg 11 cls_cnt 2 2006.280.07:20:20.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:20.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:20.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:20.93#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:20:20.93#ibcon#first serial, iclass 35, count 2 2006.280.07:20:20.93#ibcon#enter sib2, iclass 35, count 2 2006.280.07:20:20.93#ibcon#flushed, iclass 35, count 2 2006.280.07:20:20.93#ibcon#about to write, iclass 35, count 2 2006.280.07:20:20.93#ibcon#wrote, iclass 35, count 2 2006.280.07:20:20.93#ibcon#about to read 3, iclass 35, count 2 2006.280.07:20:20.95#ibcon#read 3, iclass 35, count 2 2006.280.07:20:20.95#ibcon#about to read 4, iclass 35, count 2 2006.280.07:20:20.95#ibcon#read 4, iclass 35, count 2 2006.280.07:20:20.95#ibcon#about to read 5, iclass 35, count 2 2006.280.07:20:20.95#ibcon#read 5, iclass 35, count 2 2006.280.07:20:20.95#ibcon#about to read 6, iclass 35, count 2 2006.280.07:20:20.95#ibcon#read 6, iclass 35, count 2 2006.280.07:20:20.95#ibcon#end of sib2, iclass 35, count 2 2006.280.07:20:20.95#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:20:20.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:20:20.95#ibcon#[27=AT06-04\r\n] 2006.280.07:20:20.95#ibcon#*before write, iclass 35, count 2 2006.280.07:20:20.95#ibcon#enter sib2, iclass 35, count 2 2006.280.07:20:20.95#ibcon#flushed, iclass 35, count 2 2006.280.07:20:20.95#ibcon#about to write, iclass 35, count 2 2006.280.07:20:20.95#ibcon#wrote, iclass 35, count 2 2006.280.07:20:20.95#ibcon#about to read 3, iclass 35, count 2 2006.280.07:20:20.98#ibcon#read 3, iclass 35, count 2 2006.280.07:20:20.98#ibcon#about to read 4, iclass 35, count 2 2006.280.07:20:20.98#ibcon#read 4, iclass 35, count 2 2006.280.07:20:20.98#ibcon#about to read 5, iclass 35, count 2 2006.280.07:20:20.98#ibcon#read 5, iclass 35, count 2 2006.280.07:20:20.98#ibcon#about to read 6, iclass 35, count 2 2006.280.07:20:20.98#ibcon#read 6, iclass 35, count 2 2006.280.07:20:20.98#ibcon#end of sib2, iclass 35, count 2 2006.280.07:20:20.98#ibcon#*after write, iclass 35, count 2 2006.280.07:20:20.98#ibcon#*before return 0, iclass 35, count 2 2006.280.07:20:20.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:20.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:20:20.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:20:20.98#ibcon#ireg 7 cls_cnt 0 2006.280.07:20:20.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:21.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:21.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:21.10#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:20:21.10#ibcon#first serial, iclass 35, count 0 2006.280.07:20:21.10#ibcon#enter sib2, iclass 35, count 0 2006.280.07:20:21.10#ibcon#flushed, iclass 35, count 0 2006.280.07:20:21.10#ibcon#about to write, iclass 35, count 0 2006.280.07:20:21.10#ibcon#wrote, iclass 35, count 0 2006.280.07:20:21.10#ibcon#about to read 3, iclass 35, count 0 2006.280.07:20:21.12#ibcon#read 3, iclass 35, count 0 2006.280.07:20:21.12#ibcon#about to read 4, iclass 35, count 0 2006.280.07:20:21.12#ibcon#read 4, iclass 35, count 0 2006.280.07:20:21.12#ibcon#about to read 5, iclass 35, count 0 2006.280.07:20:21.12#ibcon#read 5, iclass 35, count 0 2006.280.07:20:21.12#ibcon#about to read 6, iclass 35, count 0 2006.280.07:20:21.12#ibcon#read 6, iclass 35, count 0 2006.280.07:20:21.12#ibcon#end of sib2, iclass 35, count 0 2006.280.07:20:21.12#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:20:21.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:20:21.12#ibcon#[27=USB\r\n] 2006.280.07:20:21.12#ibcon#*before write, iclass 35, count 0 2006.280.07:20:21.12#ibcon#enter sib2, iclass 35, count 0 2006.280.07:20:21.12#ibcon#flushed, iclass 35, count 0 2006.280.07:20:21.12#ibcon#about to write, iclass 35, count 0 2006.280.07:20:21.12#ibcon#wrote, iclass 35, count 0 2006.280.07:20:21.12#ibcon#about to read 3, iclass 35, count 0 2006.280.07:20:21.15#ibcon#read 3, iclass 35, count 0 2006.280.07:20:21.15#ibcon#about to read 4, iclass 35, count 0 2006.280.07:20:21.15#ibcon#read 4, iclass 35, count 0 2006.280.07:20:21.15#ibcon#about to read 5, iclass 35, count 0 2006.280.07:20:21.15#ibcon#read 5, iclass 35, count 0 2006.280.07:20:21.15#ibcon#about to read 6, iclass 35, count 0 2006.280.07:20:21.15#ibcon#read 6, iclass 35, count 0 2006.280.07:20:21.15#ibcon#end of sib2, iclass 35, count 0 2006.280.07:20:21.15#ibcon#*after write, iclass 35, count 0 2006.280.07:20:21.15#ibcon#*before return 0, iclass 35, count 0 2006.280.07:20:21.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:21.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:20:21.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:20:21.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:20:21.15$vc4f8/vabw=wide 2006.280.07:20:21.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:20:21.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:20:21.15#ibcon#ireg 8 cls_cnt 0 2006.280.07:20:21.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:21.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:21.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:21.15#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:20:21.15#ibcon#first serial, iclass 37, count 0 2006.280.07:20:21.15#ibcon#enter sib2, iclass 37, count 0 2006.280.07:20:21.15#ibcon#flushed, iclass 37, count 0 2006.280.07:20:21.15#ibcon#about to write, iclass 37, count 0 2006.280.07:20:21.15#ibcon#wrote, iclass 37, count 0 2006.280.07:20:21.15#ibcon#about to read 3, iclass 37, count 0 2006.280.07:20:21.17#ibcon#read 3, iclass 37, count 0 2006.280.07:20:21.17#ibcon#about to read 4, iclass 37, count 0 2006.280.07:20:21.17#ibcon#read 4, iclass 37, count 0 2006.280.07:20:21.17#ibcon#about to read 5, iclass 37, count 0 2006.280.07:20:21.17#ibcon#read 5, iclass 37, count 0 2006.280.07:20:21.17#ibcon#about to read 6, iclass 37, count 0 2006.280.07:20:21.17#ibcon#read 6, iclass 37, count 0 2006.280.07:20:21.17#ibcon#end of sib2, iclass 37, count 0 2006.280.07:20:21.17#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:20:21.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:20:21.17#ibcon#[25=BW32\r\n] 2006.280.07:20:21.17#ibcon#*before write, iclass 37, count 0 2006.280.07:20:21.17#ibcon#enter sib2, iclass 37, count 0 2006.280.07:20:21.17#ibcon#flushed, iclass 37, count 0 2006.280.07:20:21.20#ibcon#about to write, iclass 37, count 0 2006.280.07:20:21.20#ibcon#wrote, iclass 37, count 0 2006.280.07:20:21.20#ibcon#about to read 3, iclass 37, count 0 2006.280.07:20:21.23#ibcon#read 3, iclass 37, count 0 2006.280.07:20:21.23#ibcon#about to read 4, iclass 37, count 0 2006.280.07:20:21.23#ibcon#read 4, iclass 37, count 0 2006.280.07:20:21.23#ibcon#about to read 5, iclass 37, count 0 2006.280.07:20:21.23#ibcon#read 5, iclass 37, count 0 2006.280.07:20:21.23#ibcon#about to read 6, iclass 37, count 0 2006.280.07:20:21.23#ibcon#read 6, iclass 37, count 0 2006.280.07:20:21.23#ibcon#end of sib2, iclass 37, count 0 2006.280.07:20:21.23#ibcon#*after write, iclass 37, count 0 2006.280.07:20:21.23#ibcon#*before return 0, iclass 37, count 0 2006.280.07:20:21.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:21.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:20:21.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:20:21.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:20:21.23$vc4f8/vbbw=wide 2006.280.07:20:21.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:20:21.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:20:21.23#ibcon#ireg 8 cls_cnt 0 2006.280.07:20:21.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:20:21.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:20:21.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:20:21.29#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:20:21.29#ibcon#first serial, iclass 39, count 0 2006.280.07:20:21.29#ibcon#enter sib2, iclass 39, count 0 2006.280.07:20:21.29#ibcon#flushed, iclass 39, count 0 2006.280.07:20:21.29#ibcon#about to write, iclass 39, count 0 2006.280.07:20:21.29#ibcon#wrote, iclass 39, count 0 2006.280.07:20:21.29#ibcon#about to read 3, iclass 39, count 0 2006.280.07:20:21.30#ibcon#read 3, iclass 39, count 0 2006.280.07:20:21.30#ibcon#about to read 4, iclass 39, count 0 2006.280.07:20:21.30#ibcon#read 4, iclass 39, count 0 2006.280.07:20:21.30#ibcon#about to read 5, iclass 39, count 0 2006.280.07:20:21.30#ibcon#read 5, iclass 39, count 0 2006.280.07:20:21.30#ibcon#about to read 6, iclass 39, count 0 2006.280.07:20:21.30#ibcon#read 6, iclass 39, count 0 2006.280.07:20:21.30#ibcon#end of sib2, iclass 39, count 0 2006.280.07:20:21.30#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:20:21.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:20:21.31#ibcon#[27=BW32\r\n] 2006.280.07:20:21.31#ibcon#*before write, iclass 39, count 0 2006.280.07:20:21.31#ibcon#enter sib2, iclass 39, count 0 2006.280.07:20:21.31#ibcon#flushed, iclass 39, count 0 2006.280.07:20:21.31#ibcon#about to write, iclass 39, count 0 2006.280.07:20:21.31#ibcon#wrote, iclass 39, count 0 2006.280.07:20:21.31#ibcon#about to read 3, iclass 39, count 0 2006.280.07:20:21.34#ibcon#read 3, iclass 39, count 0 2006.280.07:20:21.34#ibcon#about to read 4, iclass 39, count 0 2006.280.07:20:21.34#ibcon#read 4, iclass 39, count 0 2006.280.07:20:21.34#ibcon#about to read 5, iclass 39, count 0 2006.280.07:20:21.34#ibcon#read 5, iclass 39, count 0 2006.280.07:20:21.34#ibcon#about to read 6, iclass 39, count 0 2006.280.07:20:21.34#ibcon#read 6, iclass 39, count 0 2006.280.07:20:21.34#ibcon#end of sib2, iclass 39, count 0 2006.280.07:20:21.34#ibcon#*after write, iclass 39, count 0 2006.280.07:20:21.34#ibcon#*before return 0, iclass 39, count 0 2006.280.07:20:21.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:20:21.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:20:21.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:20:21.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:20:21.34$4f8m12a/ifd4f 2006.280.07:20:21.34&ifd4f/lo= 2006.280.07:20:21.34&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:20:21.34&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:20:21.34&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:20:21.34&ifd4f/patch= 2006.280.07:20:21.34&ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:20:21.34&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:20:21.34&ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:20:21.34$ifd4f/lo= 2006.280.07:20:21.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:20:21.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:20:21.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:20:21.34$ifd4f/patch= 2006.280.07:20:21.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:20:21.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:20:21.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:20:21.34$4f8m12a/"form=m,16.000,1:2 2006.280.07:20:21.34$4f8m12a/"tpicd 2006.280.07:20:21.34$4f8m12a/echo=off 2006.280.07:20:21.34$4f8m12a/xlog=off 2006.280.07:20:21.34:!2006.280.07:29:50 2006.280.07:20:33.14#trakl#Source acquired 2006.280.07:20:35.14#flagr#flagr/antenna,acquired 2006.280.07:29:50.00:preob 2006.280.07:29:50.00&preob/onsource 2006.280.07:29:51.14/onsource/TRACKING 2006.280.07:29:51.14:!2006.280.07:30:00 2006.280.07:30:00.00:data_valid=on 2006.280.07:30:00.00:midob 2006.280.07:30:00.00&midob/onsource 2006.280.07:30:00.00&midob/wx 2006.280.07:30:00.00&midob/cable 2006.280.07:30:00.00&midob/va 2006.280.07:30:00.00&midob/valo 2006.280.07:30:00.00&midob/vb 2006.280.07:30:00.00&midob/vblo 2006.280.07:30:00.00&midob/vabw 2006.280.07:30:00.00&midob/vbbw 2006.280.07:30:00.00&midob/"form 2006.280.07:30:00.00&midob/xfe 2006.280.07:30:00.00&midob/ifatt 2006.280.07:30:00.00&midob/clockoff 2006.280.07:30:00.00&midob/sy=logmail 2006.280.07:30:00.00&midob/"sy=run setcl adapt & 2006.280.07:30:00.14/onsource/TRACKING 2006.280.07:30:00.14/wx/22.35,986.7,57 2006.280.07:30:00.27/cable/+6.4820E-03 2006.280.07:30:01.36/va/01,07,usb,yes,32,34 2006.280.07:30:01.36/va/02,06,usb,yes,30,32 2006.280.07:30:01.36/va/03,06,usb,yes,28,28 2006.280.07:30:01.36/va/04,06,usb,yes,31,34 2006.280.07:30:01.36/va/05,07,usb,yes,28,30 2006.280.07:30:01.36/va/06,06,usb,yes,27,27 2006.280.07:30:01.36/va/07,06,usb,yes,28,27 2006.280.07:30:01.36/va/08,06,usb,yes,30,29 2006.280.07:30:01.59/valo/01,532.99,yes,locked 2006.280.07:30:01.59/valo/02,572.99,yes,locked 2006.280.07:30:01.59/valo/03,672.99,yes,locked 2006.280.07:30:01.59/valo/04,832.99,yes,locked 2006.280.07:30:01.59/valo/05,652.99,yes,locked 2006.280.07:30:01.59/valo/06,772.99,yes,locked 2006.280.07:30:01.59/valo/07,832.99,yes,locked 2006.280.07:30:01.59/valo/08,852.99,yes,locked 2006.280.07:30:02.68/vb/01,04,usb,yes,30,29 2006.280.07:30:02.68/vb/02,05,usb,yes,28,29 2006.280.07:30:02.68/vb/03,04,usb,yes,28,32 2006.280.07:30:02.68/vb/04,04,usb,yes,29,29 2006.280.07:30:02.68/vb/05,04,usb,yes,27,31 2006.280.07:30:02.68/vb/06,04,usb,yes,28,31 2006.280.07:30:02.68/vb/07,04,usb,yes,30,30 2006.280.07:30:02.68/vb/08,04,usb,yes,28,31 2006.280.07:30:02.92/vblo/01,632.99,yes,locked 2006.280.07:30:02.92/vblo/02,640.99,yes,locked 2006.280.07:30:02.92/vblo/03,656.99,yes,locked 2006.280.07:30:02.92/vblo/04,712.99,yes,locked 2006.280.07:30:02.92/vblo/05,744.99,yes,locked 2006.280.07:30:02.92/vblo/06,752.99,yes,locked 2006.280.07:30:02.92/vblo/07,734.99,yes,locked 2006.280.07:30:02.92/vblo/08,744.99,yes,locked 2006.280.07:30:03.07/vabw/8 2006.280.07:30:03.22/vbbw/8 2006.280.07:30:03.31/xfe/off,on,12.2 2006.280.07:30:03.68/ifatt/23,28,28,28 2006.280.07:30:03.68&clockoff/"gps-fmout=1p 2006.280.07:30:03.68&clockoff/fmout-gps=1p 2006.280.07:30:04.08/fmout-gps/S +2.96E-07 2006.280.07:30:04.10:!2006.280.07:31:00 2006.280.07:31:00.01:data_valid=off 2006.280.07:31:00.01:postob 2006.280.07:31:00.02&postob/cable 2006.280.07:31:00.02&postob/wx 2006.280.07:31:00.02&postob/clockoff 2006.280.07:31:00.26/cable/+6.4822E-03 2006.280.07:31:00.26/wx/22.28,986.6,57 2006.280.07:31:01.08/fmout-gps/S +2.96E-07 2006.280.07:31:01.08:scan_name=280-0733,k06280,60 2006.280.07:31:01.09:source=0133+476,013658.59,475129.1,2000.0,cw 2006.280.07:31:01.14#flagr#flagr/antenna,new-source 2006.280.07:31:02.14:checkk5 2006.280.07:31:02.14&checkk5/chk_autoobs=1 2006.280.07:31:02.15&checkk5/chk_autoobs=2 2006.280.07:31:02.15&checkk5/chk_autoobs=3 2006.280.07:31:02.15&checkk5/chk_autoobs=4 2006.280.07:31:02.16&checkk5/chk_obsdata=1 2006.280.07:31:02.16&checkk5/chk_obsdata=2 2006.280.07:31:02.16&checkk5/chk_obsdata=3 2006.280.07:31:02.17&checkk5/chk_obsdata=4 2006.280.07:31:02.17&checkk5/k5log=1 2006.280.07:31:02.17&checkk5/k5log=2 2006.280.07:31:02.18&checkk5/k5log=3 2006.280.07:31:02.22&checkk5/k5log=4 2006.280.07:31:02.23&checkk5/obsinfo 2006.280.07:31:02.69/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:31:03.08/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:31:03.57/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:31:03.96/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:31:04.36/chk_obsdata//k5ts1/T2800730??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:31:04.87/chk_obsdata//k5ts2/T2800730??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:31:05.24/chk_obsdata//k5ts3/T2800730??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:31:05.68/chk_obsdata//k5ts4/T2800730??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:31:06.41/k5log//k5ts1_log_newline 2006.280.07:31:07.17/k5log//k5ts2_log_newline 2006.280.07:31:08.00/k5log//k5ts3_log_newline 2006.280.07:31:08.78/k5log//k5ts4_log_newline 2006.280.07:31:08.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:31:08.81:4f8m12a=1 2006.280.07:31:08.81$4f8m12a/echo=on 2006.280.07:31:08.81$4f8m12a/pcalon 2006.280.07:31:08.81$pcalon/"no phase cal control is implemented here 2006.280.07:31:08.81$4f8m12a/"tpicd=stop 2006.280.07:31:08.81$4f8m12a/vc4f8 2006.280.07:31:08.81$vc4f8/valo=1,532.99 2006.280.07:31:08.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:31:08.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:31:08.81#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:08.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:08.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:08.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:08.81#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:31:08.81#ibcon#first serial, iclass 3, count 0 2006.280.07:31:08.81#ibcon#enter sib2, iclass 3, count 0 2006.280.07:31:08.81#ibcon#flushed, iclass 3, count 0 2006.280.07:31:08.81#ibcon#about to write, iclass 3, count 0 2006.280.07:31:08.81#ibcon#wrote, iclass 3, count 0 2006.280.07:31:08.81#ibcon#about to read 3, iclass 3, count 0 2006.280.07:31:08.83#ibcon#read 3, iclass 3, count 0 2006.280.07:31:08.83#ibcon#about to read 4, iclass 3, count 0 2006.280.07:31:08.83#ibcon#read 4, iclass 3, count 0 2006.280.07:31:08.83#ibcon#about to read 5, iclass 3, count 0 2006.280.07:31:08.83#ibcon#read 5, iclass 3, count 0 2006.280.07:31:08.83#ibcon#about to read 6, iclass 3, count 0 2006.280.07:31:08.83#ibcon#read 6, iclass 3, count 0 2006.280.07:31:08.83#ibcon#end of sib2, iclass 3, count 0 2006.280.07:31:08.83#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:31:08.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:31:08.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:31:08.83#ibcon#*before write, iclass 3, count 0 2006.280.07:31:08.83#ibcon#enter sib2, iclass 3, count 0 2006.280.07:31:08.83#ibcon#flushed, iclass 3, count 0 2006.280.07:31:08.83#ibcon#about to write, iclass 3, count 0 2006.280.07:31:08.83#ibcon#wrote, iclass 3, count 0 2006.280.07:31:08.83#ibcon#about to read 3, iclass 3, count 0 2006.280.07:31:08.88#ibcon#read 3, iclass 3, count 0 2006.280.07:31:08.88#ibcon#about to read 4, iclass 3, count 0 2006.280.07:31:08.88#ibcon#read 4, iclass 3, count 0 2006.280.07:31:08.88#ibcon#about to read 5, iclass 3, count 0 2006.280.07:31:08.88#ibcon#read 5, iclass 3, count 0 2006.280.07:31:08.88#ibcon#about to read 6, iclass 3, count 0 2006.280.07:31:08.88#ibcon#read 6, iclass 3, count 0 2006.280.07:31:08.88#ibcon#end of sib2, iclass 3, count 0 2006.280.07:31:08.88#ibcon#*after write, iclass 3, count 0 2006.280.07:31:08.88#ibcon#*before return 0, iclass 3, count 0 2006.280.07:31:08.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:08.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:08.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:31:08.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:31:08.88$vc4f8/va=1,7 2006.280.07:31:08.88#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:31:08.88#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:31:08.88#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:08.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:08.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:08.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:08.88#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:31:08.88#ibcon#first serial, iclass 5, count 2 2006.280.07:31:08.88#ibcon#enter sib2, iclass 5, count 2 2006.280.07:31:08.88#ibcon#flushed, iclass 5, count 2 2006.280.07:31:08.88#ibcon#about to write, iclass 5, count 2 2006.280.07:31:08.88#ibcon#wrote, iclass 5, count 2 2006.280.07:31:08.88#ibcon#about to read 3, iclass 5, count 2 2006.280.07:31:08.90#ibcon#read 3, iclass 5, count 2 2006.280.07:31:08.93#ibcon#about to read 4, iclass 5, count 2 2006.280.07:31:08.93#ibcon#read 4, iclass 5, count 2 2006.280.07:31:08.93#ibcon#about to read 5, iclass 5, count 2 2006.280.07:31:08.93#ibcon#read 5, iclass 5, count 2 2006.280.07:31:08.93#ibcon#about to read 6, iclass 5, count 2 2006.280.07:31:08.93#ibcon#read 6, iclass 5, count 2 2006.280.07:31:08.93#ibcon#end of sib2, iclass 5, count 2 2006.280.07:31:08.93#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:31:08.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:31:08.93#ibcon#[25=AT01-07\r\n] 2006.280.07:31:08.93#ibcon#*before write, iclass 5, count 2 2006.280.07:31:08.93#ibcon#enter sib2, iclass 5, count 2 2006.280.07:31:08.93#ibcon#flushed, iclass 5, count 2 2006.280.07:31:08.93#ibcon#about to write, iclass 5, count 2 2006.280.07:31:08.93#ibcon#wrote, iclass 5, count 2 2006.280.07:31:08.93#ibcon#about to read 3, iclass 5, count 2 2006.280.07:31:08.96#ibcon#read 3, iclass 5, count 2 2006.280.07:31:08.96#ibcon#about to read 4, iclass 5, count 2 2006.280.07:31:08.96#ibcon#read 4, iclass 5, count 2 2006.280.07:31:08.96#ibcon#about to read 5, iclass 5, count 2 2006.280.07:31:08.96#ibcon#read 5, iclass 5, count 2 2006.280.07:31:08.96#ibcon#about to read 6, iclass 5, count 2 2006.280.07:31:08.96#ibcon#read 6, iclass 5, count 2 2006.280.07:31:08.96#ibcon#end of sib2, iclass 5, count 2 2006.280.07:31:08.96#ibcon#*after write, iclass 5, count 2 2006.280.07:31:08.96#ibcon#*before return 0, iclass 5, count 2 2006.280.07:31:08.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:08.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:08.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:31:08.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:08.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:09.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:09.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:09.08#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:31:09.08#ibcon#first serial, iclass 5, count 0 2006.280.07:31:09.08#ibcon#enter sib2, iclass 5, count 0 2006.280.07:31:09.08#ibcon#flushed, iclass 5, count 0 2006.280.07:31:09.08#ibcon#about to write, iclass 5, count 0 2006.280.07:31:09.08#ibcon#wrote, iclass 5, count 0 2006.280.07:31:09.08#ibcon#about to read 3, iclass 5, count 0 2006.280.07:31:09.10#ibcon#read 3, iclass 5, count 0 2006.280.07:31:09.10#ibcon#about to read 4, iclass 5, count 0 2006.280.07:31:09.10#ibcon#read 4, iclass 5, count 0 2006.280.07:31:09.10#ibcon#about to read 5, iclass 5, count 0 2006.280.07:31:09.10#ibcon#read 5, iclass 5, count 0 2006.280.07:31:09.10#ibcon#about to read 6, iclass 5, count 0 2006.280.07:31:09.10#ibcon#read 6, iclass 5, count 0 2006.280.07:31:09.10#ibcon#end of sib2, iclass 5, count 0 2006.280.07:31:09.10#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:31:09.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:31:09.10#ibcon#[25=USB\r\n] 2006.280.07:31:09.10#ibcon#*before write, iclass 5, count 0 2006.280.07:31:09.10#ibcon#enter sib2, iclass 5, count 0 2006.280.07:31:09.10#ibcon#flushed, iclass 5, count 0 2006.280.07:31:09.10#ibcon#about to write, iclass 5, count 0 2006.280.07:31:09.10#ibcon#wrote, iclass 5, count 0 2006.280.07:31:09.10#ibcon#about to read 3, iclass 5, count 0 2006.280.07:31:09.13#ibcon#read 3, iclass 5, count 0 2006.280.07:31:09.13#ibcon#about to read 4, iclass 5, count 0 2006.280.07:31:09.13#ibcon#read 4, iclass 5, count 0 2006.280.07:31:09.13#ibcon#about to read 5, iclass 5, count 0 2006.280.07:31:09.13#ibcon#read 5, iclass 5, count 0 2006.280.07:31:09.13#ibcon#about to read 6, iclass 5, count 0 2006.280.07:31:09.13#ibcon#read 6, iclass 5, count 0 2006.280.07:31:09.13#ibcon#end of sib2, iclass 5, count 0 2006.280.07:31:09.13#ibcon#*after write, iclass 5, count 0 2006.280.07:31:09.13#ibcon#*before return 0, iclass 5, count 0 2006.280.07:31:09.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:09.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:09.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:31:09.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:31:09.13$vc4f8/valo=2,572.99 2006.280.07:31:09.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:31:09.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:31:09.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:09.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:09.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:09.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:09.13#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:31:09.13#ibcon#first serial, iclass 7, count 0 2006.280.07:31:09.13#ibcon#enter sib2, iclass 7, count 0 2006.280.07:31:09.13#ibcon#flushed, iclass 7, count 0 2006.280.07:31:09.13#ibcon#about to write, iclass 7, count 0 2006.280.07:31:09.13#ibcon#wrote, iclass 7, count 0 2006.280.07:31:09.13#ibcon#about to read 3, iclass 7, count 0 2006.280.07:31:09.15#ibcon#read 3, iclass 7, count 0 2006.280.07:31:09.15#ibcon#about to read 4, iclass 7, count 0 2006.280.07:31:09.15#ibcon#read 4, iclass 7, count 0 2006.280.07:31:09.15#ibcon#about to read 5, iclass 7, count 0 2006.280.07:31:09.15#ibcon#read 5, iclass 7, count 0 2006.280.07:31:09.15#ibcon#about to read 6, iclass 7, count 0 2006.280.07:31:09.15#ibcon#read 6, iclass 7, count 0 2006.280.07:31:09.15#ibcon#end of sib2, iclass 7, count 0 2006.280.07:31:09.15#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:31:09.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:31:09.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:31:09.15#ibcon#*before write, iclass 7, count 0 2006.280.07:31:09.15#ibcon#enter sib2, iclass 7, count 0 2006.280.07:31:09.15#ibcon#flushed, iclass 7, count 0 2006.280.07:31:09.15#ibcon#about to write, iclass 7, count 0 2006.280.07:31:09.15#ibcon#wrote, iclass 7, count 0 2006.280.07:31:09.15#ibcon#about to read 3, iclass 7, count 0 2006.280.07:31:09.19#ibcon#read 3, iclass 7, count 0 2006.280.07:31:09.19#ibcon#about to read 4, iclass 7, count 0 2006.280.07:31:09.19#ibcon#read 4, iclass 7, count 0 2006.280.07:31:09.19#ibcon#about to read 5, iclass 7, count 0 2006.280.07:31:09.19#ibcon#read 5, iclass 7, count 0 2006.280.07:31:09.19#ibcon#about to read 6, iclass 7, count 0 2006.280.07:31:09.19#ibcon#read 6, iclass 7, count 0 2006.280.07:31:09.19#ibcon#end of sib2, iclass 7, count 0 2006.280.07:31:09.19#ibcon#*after write, iclass 7, count 0 2006.280.07:31:09.19#ibcon#*before return 0, iclass 7, count 0 2006.280.07:31:09.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:09.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:09.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:31:09.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:31:09.19$vc4f8/va=2,6 2006.280.07:31:09.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:31:09.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:31:09.19#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:09.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:09.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:09.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:09.25#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:31:09.25#ibcon#first serial, iclass 11, count 2 2006.280.07:31:09.25#ibcon#enter sib2, iclass 11, count 2 2006.280.07:31:09.25#ibcon#flushed, iclass 11, count 2 2006.280.07:31:09.25#ibcon#about to write, iclass 11, count 2 2006.280.07:31:09.25#ibcon#wrote, iclass 11, count 2 2006.280.07:31:09.25#ibcon#about to read 3, iclass 11, count 2 2006.280.07:31:09.27#ibcon#read 3, iclass 11, count 2 2006.280.07:31:09.27#ibcon#about to read 4, iclass 11, count 2 2006.280.07:31:09.27#ibcon#read 4, iclass 11, count 2 2006.280.07:31:09.27#ibcon#about to read 5, iclass 11, count 2 2006.280.07:31:09.27#ibcon#read 5, iclass 11, count 2 2006.280.07:31:09.27#ibcon#about to read 6, iclass 11, count 2 2006.280.07:31:09.27#ibcon#read 6, iclass 11, count 2 2006.280.07:31:09.27#ibcon#end of sib2, iclass 11, count 2 2006.280.07:31:09.27#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:31:09.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:31:09.27#ibcon#[25=AT02-06\r\n] 2006.280.07:31:09.27#ibcon#*before write, iclass 11, count 2 2006.280.07:31:09.27#ibcon#enter sib2, iclass 11, count 2 2006.280.07:31:09.27#ibcon#flushed, iclass 11, count 2 2006.280.07:31:09.27#ibcon#about to write, iclass 11, count 2 2006.280.07:31:09.27#ibcon#wrote, iclass 11, count 2 2006.280.07:31:09.27#ibcon#about to read 3, iclass 11, count 2 2006.280.07:31:09.30#ibcon#read 3, iclass 11, count 2 2006.280.07:31:09.30#ibcon#about to read 4, iclass 11, count 2 2006.280.07:31:09.30#ibcon#read 4, iclass 11, count 2 2006.280.07:31:09.30#ibcon#about to read 5, iclass 11, count 2 2006.280.07:31:09.30#ibcon#read 5, iclass 11, count 2 2006.280.07:31:09.30#ibcon#about to read 6, iclass 11, count 2 2006.280.07:31:09.30#ibcon#read 6, iclass 11, count 2 2006.280.07:31:09.30#ibcon#end of sib2, iclass 11, count 2 2006.280.07:31:09.30#ibcon#*after write, iclass 11, count 2 2006.280.07:31:09.30#ibcon#*before return 0, iclass 11, count 2 2006.280.07:31:09.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:09.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:09.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:31:09.30#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:09.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:09.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:09.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:09.42#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:31:09.42#ibcon#first serial, iclass 11, count 0 2006.280.07:31:09.42#ibcon#enter sib2, iclass 11, count 0 2006.280.07:31:09.42#ibcon#flushed, iclass 11, count 0 2006.280.07:31:09.42#ibcon#about to write, iclass 11, count 0 2006.280.07:31:09.42#ibcon#wrote, iclass 11, count 0 2006.280.07:31:09.42#ibcon#about to read 3, iclass 11, count 0 2006.280.07:31:09.44#ibcon#read 3, iclass 11, count 0 2006.280.07:31:09.44#ibcon#about to read 4, iclass 11, count 0 2006.280.07:31:09.44#ibcon#read 4, iclass 11, count 0 2006.280.07:31:09.44#ibcon#about to read 5, iclass 11, count 0 2006.280.07:31:09.44#ibcon#read 5, iclass 11, count 0 2006.280.07:31:09.44#ibcon#about to read 6, iclass 11, count 0 2006.280.07:31:09.44#ibcon#read 6, iclass 11, count 0 2006.280.07:31:09.44#ibcon#end of sib2, iclass 11, count 0 2006.280.07:31:09.44#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:31:09.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:31:09.44#ibcon#[25=USB\r\n] 2006.280.07:31:09.44#ibcon#*before write, iclass 11, count 0 2006.280.07:31:09.44#ibcon#enter sib2, iclass 11, count 0 2006.280.07:31:09.44#ibcon#flushed, iclass 11, count 0 2006.280.07:31:09.44#ibcon#about to write, iclass 11, count 0 2006.280.07:31:09.44#ibcon#wrote, iclass 11, count 0 2006.280.07:31:09.44#ibcon#about to read 3, iclass 11, count 0 2006.280.07:31:09.47#ibcon#read 3, iclass 11, count 0 2006.280.07:31:09.47#ibcon#about to read 4, iclass 11, count 0 2006.280.07:31:09.47#ibcon#read 4, iclass 11, count 0 2006.280.07:31:09.47#ibcon#about to read 5, iclass 11, count 0 2006.280.07:31:09.47#ibcon#read 5, iclass 11, count 0 2006.280.07:31:09.47#ibcon#about to read 6, iclass 11, count 0 2006.280.07:31:09.47#ibcon#read 6, iclass 11, count 0 2006.280.07:31:09.47#ibcon#end of sib2, iclass 11, count 0 2006.280.07:31:09.47#ibcon#*after write, iclass 11, count 0 2006.280.07:31:09.47#ibcon#*before return 0, iclass 11, count 0 2006.280.07:31:09.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:09.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:09.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:31:09.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:31:09.47$vc4f8/valo=3,672.99 2006.280.07:31:09.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:31:09.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:31:09.47#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:09.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:09.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:09.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:09.47#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:31:09.47#ibcon#first serial, iclass 13, count 0 2006.280.07:31:09.47#ibcon#enter sib2, iclass 13, count 0 2006.280.07:31:09.47#ibcon#flushed, iclass 13, count 0 2006.280.07:31:09.47#ibcon#about to write, iclass 13, count 0 2006.280.07:31:09.47#ibcon#wrote, iclass 13, count 0 2006.280.07:31:09.47#ibcon#about to read 3, iclass 13, count 0 2006.280.07:31:09.49#ibcon#read 3, iclass 13, count 0 2006.280.07:31:09.49#ibcon#about to read 4, iclass 13, count 0 2006.280.07:31:09.49#ibcon#read 4, iclass 13, count 0 2006.280.07:31:09.49#ibcon#about to read 5, iclass 13, count 0 2006.280.07:31:09.49#ibcon#read 5, iclass 13, count 0 2006.280.07:31:09.49#ibcon#about to read 6, iclass 13, count 0 2006.280.07:31:09.49#ibcon#read 6, iclass 13, count 0 2006.280.07:31:09.49#ibcon#end of sib2, iclass 13, count 0 2006.280.07:31:09.49#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:31:09.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:31:09.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:31:09.49#ibcon#*before write, iclass 13, count 0 2006.280.07:31:09.49#ibcon#enter sib2, iclass 13, count 0 2006.280.07:31:09.49#ibcon#flushed, iclass 13, count 0 2006.280.07:31:09.49#ibcon#about to write, iclass 13, count 0 2006.280.07:31:09.49#ibcon#wrote, iclass 13, count 0 2006.280.07:31:09.49#ibcon#about to read 3, iclass 13, count 0 2006.280.07:31:09.53#ibcon#read 3, iclass 13, count 0 2006.280.07:31:09.53#ibcon#about to read 4, iclass 13, count 0 2006.280.07:31:09.53#ibcon#read 4, iclass 13, count 0 2006.280.07:31:09.53#ibcon#about to read 5, iclass 13, count 0 2006.280.07:31:09.53#ibcon#read 5, iclass 13, count 0 2006.280.07:31:09.53#ibcon#about to read 6, iclass 13, count 0 2006.280.07:31:09.53#ibcon#read 6, iclass 13, count 0 2006.280.07:31:09.53#ibcon#end of sib2, iclass 13, count 0 2006.280.07:31:09.53#ibcon#*after write, iclass 13, count 0 2006.280.07:31:09.53#ibcon#*before return 0, iclass 13, count 0 2006.280.07:31:09.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:09.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:09.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:31:09.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:31:09.53$vc4f8/va=3,6 2006.280.07:31:09.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:31:09.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:31:09.53#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:09.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:09.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:09.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:09.59#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:31:09.59#ibcon#first serial, iclass 15, count 2 2006.280.07:31:09.59#ibcon#enter sib2, iclass 15, count 2 2006.280.07:31:09.59#ibcon#flushed, iclass 15, count 2 2006.280.07:31:09.59#ibcon#about to write, iclass 15, count 2 2006.280.07:31:09.59#ibcon#wrote, iclass 15, count 2 2006.280.07:31:09.59#ibcon#about to read 3, iclass 15, count 2 2006.280.07:31:09.61#ibcon#read 3, iclass 15, count 2 2006.280.07:31:09.61#ibcon#about to read 4, iclass 15, count 2 2006.280.07:31:09.61#ibcon#read 4, iclass 15, count 2 2006.280.07:31:09.61#ibcon#about to read 5, iclass 15, count 2 2006.280.07:31:09.61#ibcon#read 5, iclass 15, count 2 2006.280.07:31:09.61#ibcon#about to read 6, iclass 15, count 2 2006.280.07:31:09.61#ibcon#read 6, iclass 15, count 2 2006.280.07:31:09.61#ibcon#end of sib2, iclass 15, count 2 2006.280.07:31:09.61#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:31:09.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:31:09.61#ibcon#[25=AT03-06\r\n] 2006.280.07:31:09.61#ibcon#*before write, iclass 15, count 2 2006.280.07:31:09.61#ibcon#enter sib2, iclass 15, count 2 2006.280.07:31:09.61#ibcon#flushed, iclass 15, count 2 2006.280.07:31:09.61#ibcon#about to write, iclass 15, count 2 2006.280.07:31:09.61#ibcon#wrote, iclass 15, count 2 2006.280.07:31:09.61#ibcon#about to read 3, iclass 15, count 2 2006.280.07:31:09.64#ibcon#read 3, iclass 15, count 2 2006.280.07:31:09.64#ibcon#about to read 4, iclass 15, count 2 2006.280.07:31:09.64#ibcon#read 4, iclass 15, count 2 2006.280.07:31:09.64#ibcon#about to read 5, iclass 15, count 2 2006.280.07:31:09.64#ibcon#read 5, iclass 15, count 2 2006.280.07:31:09.64#ibcon#about to read 6, iclass 15, count 2 2006.280.07:31:09.64#ibcon#read 6, iclass 15, count 2 2006.280.07:31:09.64#ibcon#end of sib2, iclass 15, count 2 2006.280.07:31:09.64#ibcon#*after write, iclass 15, count 2 2006.280.07:31:09.64#ibcon#*before return 0, iclass 15, count 2 2006.280.07:31:09.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:09.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:09.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:31:09.64#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:09.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:09.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:09.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:09.76#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:31:09.76#ibcon#first serial, iclass 15, count 0 2006.280.07:31:09.76#ibcon#enter sib2, iclass 15, count 0 2006.280.07:31:09.76#ibcon#flushed, iclass 15, count 0 2006.280.07:31:09.76#ibcon#about to write, iclass 15, count 0 2006.280.07:31:09.76#ibcon#wrote, iclass 15, count 0 2006.280.07:31:09.76#ibcon#about to read 3, iclass 15, count 0 2006.280.07:31:09.78#ibcon#read 3, iclass 15, count 0 2006.280.07:31:09.78#ibcon#about to read 4, iclass 15, count 0 2006.280.07:31:09.78#ibcon#read 4, iclass 15, count 0 2006.280.07:31:09.78#ibcon#about to read 5, iclass 15, count 0 2006.280.07:31:09.78#ibcon#read 5, iclass 15, count 0 2006.280.07:31:09.78#ibcon#about to read 6, iclass 15, count 0 2006.280.07:31:09.78#ibcon#read 6, iclass 15, count 0 2006.280.07:31:09.78#ibcon#end of sib2, iclass 15, count 0 2006.280.07:31:09.78#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:31:09.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:31:09.78#ibcon#[25=USB\r\n] 2006.280.07:31:09.78#ibcon#*before write, iclass 15, count 0 2006.280.07:31:09.78#ibcon#enter sib2, iclass 15, count 0 2006.280.07:31:09.78#ibcon#flushed, iclass 15, count 0 2006.280.07:31:09.78#ibcon#about to write, iclass 15, count 0 2006.280.07:31:09.78#ibcon#wrote, iclass 15, count 0 2006.280.07:31:09.78#ibcon#about to read 3, iclass 15, count 0 2006.280.07:31:09.81#ibcon#read 3, iclass 15, count 0 2006.280.07:31:09.81#ibcon#about to read 4, iclass 15, count 0 2006.280.07:31:09.81#ibcon#read 4, iclass 15, count 0 2006.280.07:31:09.81#ibcon#about to read 5, iclass 15, count 0 2006.280.07:31:09.81#ibcon#read 5, iclass 15, count 0 2006.280.07:31:09.81#ibcon#about to read 6, iclass 15, count 0 2006.280.07:31:09.81#ibcon#read 6, iclass 15, count 0 2006.280.07:31:09.81#ibcon#end of sib2, iclass 15, count 0 2006.280.07:31:09.81#ibcon#*after write, iclass 15, count 0 2006.280.07:31:09.81#ibcon#*before return 0, iclass 15, count 0 2006.280.07:31:09.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:09.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:09.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:31:09.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:31:09.81$vc4f8/valo=4,832.99 2006.280.07:31:09.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:31:09.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:31:09.81#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:09.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:09.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:09.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:09.81#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:31:09.81#ibcon#first serial, iclass 17, count 0 2006.280.07:31:09.81#ibcon#enter sib2, iclass 17, count 0 2006.280.07:31:09.81#ibcon#flushed, iclass 17, count 0 2006.280.07:31:09.81#ibcon#about to write, iclass 17, count 0 2006.280.07:31:09.81#ibcon#wrote, iclass 17, count 0 2006.280.07:31:09.81#ibcon#about to read 3, iclass 17, count 0 2006.280.07:31:09.83#ibcon#read 3, iclass 17, count 0 2006.280.07:31:09.83#ibcon#about to read 4, iclass 17, count 0 2006.280.07:31:09.83#ibcon#read 4, iclass 17, count 0 2006.280.07:31:09.83#ibcon#about to read 5, iclass 17, count 0 2006.280.07:31:09.83#ibcon#read 5, iclass 17, count 0 2006.280.07:31:09.83#ibcon#about to read 6, iclass 17, count 0 2006.280.07:31:09.83#ibcon#read 6, iclass 17, count 0 2006.280.07:31:09.83#ibcon#end of sib2, iclass 17, count 0 2006.280.07:31:09.83#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:31:09.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:31:09.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:31:09.83#ibcon#*before write, iclass 17, count 0 2006.280.07:31:09.83#ibcon#enter sib2, iclass 17, count 0 2006.280.07:31:09.83#ibcon#flushed, iclass 17, count 0 2006.280.07:31:09.83#ibcon#about to write, iclass 17, count 0 2006.280.07:31:09.83#ibcon#wrote, iclass 17, count 0 2006.280.07:31:09.83#ibcon#about to read 3, iclass 17, count 0 2006.280.07:31:09.87#ibcon#read 3, iclass 17, count 0 2006.280.07:31:09.87#ibcon#about to read 4, iclass 17, count 0 2006.280.07:31:09.87#ibcon#read 4, iclass 17, count 0 2006.280.07:31:09.87#ibcon#about to read 5, iclass 17, count 0 2006.280.07:31:09.87#ibcon#read 5, iclass 17, count 0 2006.280.07:31:09.87#ibcon#about to read 6, iclass 17, count 0 2006.280.07:31:09.87#ibcon#read 6, iclass 17, count 0 2006.280.07:31:09.87#ibcon#end of sib2, iclass 17, count 0 2006.280.07:31:09.87#ibcon#*after write, iclass 17, count 0 2006.280.07:31:09.87#ibcon#*before return 0, iclass 17, count 0 2006.280.07:31:09.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:09.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:09.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:31:09.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:31:09.87$vc4f8/va=4,6 2006.280.07:31:09.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:31:09.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:31:09.87#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:09.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:09.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:09.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:09.93#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:31:09.93#ibcon#first serial, iclass 19, count 2 2006.280.07:31:09.93#ibcon#enter sib2, iclass 19, count 2 2006.280.07:31:09.93#ibcon#flushed, iclass 19, count 2 2006.280.07:31:09.93#ibcon#about to write, iclass 19, count 2 2006.280.07:31:09.93#ibcon#wrote, iclass 19, count 2 2006.280.07:31:09.93#ibcon#about to read 3, iclass 19, count 2 2006.280.07:31:09.95#ibcon#read 3, iclass 19, count 2 2006.280.07:31:09.95#ibcon#about to read 4, iclass 19, count 2 2006.280.07:31:09.95#ibcon#read 4, iclass 19, count 2 2006.280.07:31:09.95#ibcon#about to read 5, iclass 19, count 2 2006.280.07:31:09.95#ibcon#read 5, iclass 19, count 2 2006.280.07:31:09.95#ibcon#about to read 6, iclass 19, count 2 2006.280.07:31:09.95#ibcon#read 6, iclass 19, count 2 2006.280.07:31:09.95#ibcon#end of sib2, iclass 19, count 2 2006.280.07:31:09.95#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:31:09.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:31:09.95#ibcon#[25=AT04-06\r\n] 2006.280.07:31:09.95#ibcon#*before write, iclass 19, count 2 2006.280.07:31:09.95#ibcon#enter sib2, iclass 19, count 2 2006.280.07:31:09.95#ibcon#flushed, iclass 19, count 2 2006.280.07:31:09.95#ibcon#about to write, iclass 19, count 2 2006.280.07:31:09.95#ibcon#wrote, iclass 19, count 2 2006.280.07:31:09.95#ibcon#about to read 3, iclass 19, count 2 2006.280.07:31:09.98#ibcon#read 3, iclass 19, count 2 2006.280.07:31:09.98#ibcon#about to read 4, iclass 19, count 2 2006.280.07:31:09.98#ibcon#read 4, iclass 19, count 2 2006.280.07:31:09.98#ibcon#about to read 5, iclass 19, count 2 2006.280.07:31:09.98#ibcon#read 5, iclass 19, count 2 2006.280.07:31:09.98#ibcon#about to read 6, iclass 19, count 2 2006.280.07:31:09.98#ibcon#read 6, iclass 19, count 2 2006.280.07:31:09.98#ibcon#end of sib2, iclass 19, count 2 2006.280.07:31:09.98#ibcon#*after write, iclass 19, count 2 2006.280.07:31:09.98#ibcon#*before return 0, iclass 19, count 2 2006.280.07:31:09.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:09.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:09.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:31:09.98#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:09.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:10.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:10.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:10.10#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:31:10.10#ibcon#first serial, iclass 19, count 0 2006.280.07:31:10.10#ibcon#enter sib2, iclass 19, count 0 2006.280.07:31:10.10#ibcon#flushed, iclass 19, count 0 2006.280.07:31:10.10#ibcon#about to write, iclass 19, count 0 2006.280.07:31:10.10#ibcon#wrote, iclass 19, count 0 2006.280.07:31:10.10#ibcon#about to read 3, iclass 19, count 0 2006.280.07:31:10.12#ibcon#read 3, iclass 19, count 0 2006.280.07:31:10.12#ibcon#about to read 4, iclass 19, count 0 2006.280.07:31:10.12#ibcon#read 4, iclass 19, count 0 2006.280.07:31:10.12#ibcon#about to read 5, iclass 19, count 0 2006.280.07:31:10.12#ibcon#read 5, iclass 19, count 0 2006.280.07:31:10.12#ibcon#about to read 6, iclass 19, count 0 2006.280.07:31:10.12#ibcon#read 6, iclass 19, count 0 2006.280.07:31:10.12#ibcon#end of sib2, iclass 19, count 0 2006.280.07:31:10.12#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:31:10.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:31:10.12#ibcon#[25=USB\r\n] 2006.280.07:31:10.12#ibcon#*before write, iclass 19, count 0 2006.280.07:31:10.12#ibcon#enter sib2, iclass 19, count 0 2006.280.07:31:10.12#ibcon#flushed, iclass 19, count 0 2006.280.07:31:10.12#ibcon#about to write, iclass 19, count 0 2006.280.07:31:10.12#ibcon#wrote, iclass 19, count 0 2006.280.07:31:10.12#ibcon#about to read 3, iclass 19, count 0 2006.280.07:31:10.15#ibcon#read 3, iclass 19, count 0 2006.280.07:31:10.15#ibcon#about to read 4, iclass 19, count 0 2006.280.07:31:10.15#ibcon#read 4, iclass 19, count 0 2006.280.07:31:10.15#ibcon#about to read 5, iclass 19, count 0 2006.280.07:31:10.15#ibcon#read 5, iclass 19, count 0 2006.280.07:31:10.15#ibcon#about to read 6, iclass 19, count 0 2006.280.07:31:10.15#ibcon#read 6, iclass 19, count 0 2006.280.07:31:10.15#ibcon#end of sib2, iclass 19, count 0 2006.280.07:31:10.15#ibcon#*after write, iclass 19, count 0 2006.280.07:31:10.15#ibcon#*before return 0, iclass 19, count 0 2006.280.07:31:10.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:10.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:10.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:31:10.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:31:10.15$vc4f8/valo=5,652.99 2006.280.07:31:10.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:31:10.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:31:10.15#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:10.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:10.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:10.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:10.15#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:31:10.15#ibcon#first serial, iclass 21, count 0 2006.280.07:31:10.15#ibcon#enter sib2, iclass 21, count 0 2006.280.07:31:10.15#ibcon#flushed, iclass 21, count 0 2006.280.07:31:10.15#ibcon#about to write, iclass 21, count 0 2006.280.07:31:10.15#ibcon#wrote, iclass 21, count 0 2006.280.07:31:10.15#ibcon#about to read 3, iclass 21, count 0 2006.280.07:31:10.17#ibcon#read 3, iclass 21, count 0 2006.280.07:31:10.17#ibcon#about to read 4, iclass 21, count 0 2006.280.07:31:10.17#ibcon#read 4, iclass 21, count 0 2006.280.07:31:10.17#ibcon#about to read 5, iclass 21, count 0 2006.280.07:31:10.17#ibcon#read 5, iclass 21, count 0 2006.280.07:31:10.17#ibcon#about to read 6, iclass 21, count 0 2006.280.07:31:10.17#ibcon#read 6, iclass 21, count 0 2006.280.07:31:10.17#ibcon#end of sib2, iclass 21, count 0 2006.280.07:31:10.17#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:31:10.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:31:10.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:31:10.17#ibcon#*before write, iclass 21, count 0 2006.280.07:31:10.17#ibcon#enter sib2, iclass 21, count 0 2006.280.07:31:10.17#ibcon#flushed, iclass 21, count 0 2006.280.07:31:10.17#ibcon#about to write, iclass 21, count 0 2006.280.07:31:10.17#ibcon#wrote, iclass 21, count 0 2006.280.07:31:10.17#ibcon#about to read 3, iclass 21, count 0 2006.280.07:31:10.21#ibcon#read 3, iclass 21, count 0 2006.280.07:31:10.21#ibcon#about to read 4, iclass 21, count 0 2006.280.07:31:10.21#ibcon#read 4, iclass 21, count 0 2006.280.07:31:10.21#ibcon#about to read 5, iclass 21, count 0 2006.280.07:31:10.21#ibcon#read 5, iclass 21, count 0 2006.280.07:31:10.21#ibcon#about to read 6, iclass 21, count 0 2006.280.07:31:10.21#ibcon#read 6, iclass 21, count 0 2006.280.07:31:10.21#ibcon#end of sib2, iclass 21, count 0 2006.280.07:31:10.21#ibcon#*after write, iclass 21, count 0 2006.280.07:31:10.21#ibcon#*before return 0, iclass 21, count 0 2006.280.07:31:10.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:10.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:10.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:31:10.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:31:10.21$vc4f8/va=5,7 2006.280.07:31:10.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:31:10.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:31:10.21#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:10.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:10.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:10.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:10.27#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:31:10.27#ibcon#first serial, iclass 23, count 2 2006.280.07:31:10.27#ibcon#enter sib2, iclass 23, count 2 2006.280.07:31:10.27#ibcon#flushed, iclass 23, count 2 2006.280.07:31:10.27#ibcon#about to write, iclass 23, count 2 2006.280.07:31:10.27#ibcon#wrote, iclass 23, count 2 2006.280.07:31:10.27#ibcon#about to read 3, iclass 23, count 2 2006.280.07:31:10.29#ibcon#read 3, iclass 23, count 2 2006.280.07:31:10.29#ibcon#about to read 4, iclass 23, count 2 2006.280.07:31:10.29#ibcon#read 4, iclass 23, count 2 2006.280.07:31:10.29#ibcon#about to read 5, iclass 23, count 2 2006.280.07:31:10.29#ibcon#read 5, iclass 23, count 2 2006.280.07:31:10.29#ibcon#about to read 6, iclass 23, count 2 2006.280.07:31:10.29#ibcon#read 6, iclass 23, count 2 2006.280.07:31:10.29#ibcon#end of sib2, iclass 23, count 2 2006.280.07:31:10.29#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:31:10.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:31:10.29#ibcon#[25=AT05-07\r\n] 2006.280.07:31:10.29#ibcon#*before write, iclass 23, count 2 2006.280.07:31:10.29#ibcon#enter sib2, iclass 23, count 2 2006.280.07:31:10.29#ibcon#flushed, iclass 23, count 2 2006.280.07:31:10.29#ibcon#about to write, iclass 23, count 2 2006.280.07:31:10.29#ibcon#wrote, iclass 23, count 2 2006.280.07:31:10.29#ibcon#about to read 3, iclass 23, count 2 2006.280.07:31:10.32#ibcon#read 3, iclass 23, count 2 2006.280.07:31:10.32#ibcon#about to read 4, iclass 23, count 2 2006.280.07:31:10.32#ibcon#read 4, iclass 23, count 2 2006.280.07:31:10.32#ibcon#about to read 5, iclass 23, count 2 2006.280.07:31:10.32#ibcon#read 5, iclass 23, count 2 2006.280.07:31:10.32#ibcon#about to read 6, iclass 23, count 2 2006.280.07:31:10.32#ibcon#read 6, iclass 23, count 2 2006.280.07:31:10.32#ibcon#end of sib2, iclass 23, count 2 2006.280.07:31:10.32#ibcon#*after write, iclass 23, count 2 2006.280.07:31:10.32#ibcon#*before return 0, iclass 23, count 2 2006.280.07:31:10.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:10.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:10.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:31:10.32#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:10.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:10.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:10.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:10.44#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:31:10.44#ibcon#first serial, iclass 23, count 0 2006.280.07:31:10.44#ibcon#enter sib2, iclass 23, count 0 2006.280.07:31:10.44#ibcon#flushed, iclass 23, count 0 2006.280.07:31:10.44#ibcon#about to write, iclass 23, count 0 2006.280.07:31:10.44#ibcon#wrote, iclass 23, count 0 2006.280.07:31:10.44#ibcon#about to read 3, iclass 23, count 0 2006.280.07:31:10.46#ibcon#read 3, iclass 23, count 0 2006.280.07:31:10.46#ibcon#about to read 4, iclass 23, count 0 2006.280.07:31:10.46#ibcon#read 4, iclass 23, count 0 2006.280.07:31:10.46#ibcon#about to read 5, iclass 23, count 0 2006.280.07:31:10.46#ibcon#read 5, iclass 23, count 0 2006.280.07:31:10.46#ibcon#about to read 6, iclass 23, count 0 2006.280.07:31:10.46#ibcon#read 6, iclass 23, count 0 2006.280.07:31:10.46#ibcon#end of sib2, iclass 23, count 0 2006.280.07:31:10.46#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:31:10.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:31:10.46#ibcon#[25=USB\r\n] 2006.280.07:31:10.46#ibcon#*before write, iclass 23, count 0 2006.280.07:31:10.46#ibcon#enter sib2, iclass 23, count 0 2006.280.07:31:10.46#ibcon#flushed, iclass 23, count 0 2006.280.07:31:10.46#ibcon#about to write, iclass 23, count 0 2006.280.07:31:10.46#ibcon#wrote, iclass 23, count 0 2006.280.07:31:10.46#ibcon#about to read 3, iclass 23, count 0 2006.280.07:31:10.49#ibcon#read 3, iclass 23, count 0 2006.280.07:31:10.49#ibcon#about to read 4, iclass 23, count 0 2006.280.07:31:10.49#ibcon#read 4, iclass 23, count 0 2006.280.07:31:10.49#ibcon#about to read 5, iclass 23, count 0 2006.280.07:31:10.49#ibcon#read 5, iclass 23, count 0 2006.280.07:31:10.49#ibcon#about to read 6, iclass 23, count 0 2006.280.07:31:10.49#ibcon#read 6, iclass 23, count 0 2006.280.07:31:10.49#ibcon#end of sib2, iclass 23, count 0 2006.280.07:31:10.49#ibcon#*after write, iclass 23, count 0 2006.280.07:31:10.49#ibcon#*before return 0, iclass 23, count 0 2006.280.07:31:10.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:10.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:10.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:31:10.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:31:10.49$vc4f8/valo=6,772.99 2006.280.07:31:10.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:31:10.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:31:10.49#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:10.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:10.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:10.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:10.49#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:31:10.49#ibcon#first serial, iclass 25, count 0 2006.280.07:31:10.49#ibcon#enter sib2, iclass 25, count 0 2006.280.07:31:10.49#ibcon#flushed, iclass 25, count 0 2006.280.07:31:10.49#ibcon#about to write, iclass 25, count 0 2006.280.07:31:10.49#ibcon#wrote, iclass 25, count 0 2006.280.07:31:10.49#ibcon#about to read 3, iclass 25, count 0 2006.280.07:31:10.51#ibcon#read 3, iclass 25, count 0 2006.280.07:31:10.51#ibcon#about to read 4, iclass 25, count 0 2006.280.07:31:10.51#ibcon#read 4, iclass 25, count 0 2006.280.07:31:10.51#ibcon#about to read 5, iclass 25, count 0 2006.280.07:31:10.51#ibcon#read 5, iclass 25, count 0 2006.280.07:31:10.51#ibcon#about to read 6, iclass 25, count 0 2006.280.07:31:10.51#ibcon#read 6, iclass 25, count 0 2006.280.07:31:10.51#ibcon#end of sib2, iclass 25, count 0 2006.280.07:31:10.51#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:31:10.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:31:10.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:31:10.51#ibcon#*before write, iclass 25, count 0 2006.280.07:31:10.51#ibcon#enter sib2, iclass 25, count 0 2006.280.07:31:10.51#ibcon#flushed, iclass 25, count 0 2006.280.07:31:10.51#ibcon#about to write, iclass 25, count 0 2006.280.07:31:10.51#ibcon#wrote, iclass 25, count 0 2006.280.07:31:10.51#ibcon#about to read 3, iclass 25, count 0 2006.280.07:31:10.55#ibcon#read 3, iclass 25, count 0 2006.280.07:31:10.55#ibcon#about to read 4, iclass 25, count 0 2006.280.07:31:10.55#ibcon#read 4, iclass 25, count 0 2006.280.07:31:10.55#ibcon#about to read 5, iclass 25, count 0 2006.280.07:31:10.55#ibcon#read 5, iclass 25, count 0 2006.280.07:31:10.55#ibcon#about to read 6, iclass 25, count 0 2006.280.07:31:10.55#ibcon#read 6, iclass 25, count 0 2006.280.07:31:10.55#ibcon#end of sib2, iclass 25, count 0 2006.280.07:31:10.55#ibcon#*after write, iclass 25, count 0 2006.280.07:31:10.55#ibcon#*before return 0, iclass 25, count 0 2006.280.07:31:10.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:10.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:10.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:31:10.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:31:10.55$vc4f8/va=6,6 2006.280.07:31:10.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:31:10.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:31:10.55#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:10.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:10.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:10.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:10.61#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:31:10.61#ibcon#first serial, iclass 27, count 2 2006.280.07:31:10.61#ibcon#enter sib2, iclass 27, count 2 2006.280.07:31:10.61#ibcon#flushed, iclass 27, count 2 2006.280.07:31:10.61#ibcon#about to write, iclass 27, count 2 2006.280.07:31:10.61#ibcon#wrote, iclass 27, count 2 2006.280.07:31:10.61#ibcon#about to read 3, iclass 27, count 2 2006.280.07:31:10.63#ibcon#read 3, iclass 27, count 2 2006.280.07:31:10.63#ibcon#about to read 4, iclass 27, count 2 2006.280.07:31:10.63#ibcon#read 4, iclass 27, count 2 2006.280.07:31:10.63#ibcon#about to read 5, iclass 27, count 2 2006.280.07:31:10.63#ibcon#read 5, iclass 27, count 2 2006.280.07:31:10.63#ibcon#about to read 6, iclass 27, count 2 2006.280.07:31:10.63#ibcon#read 6, iclass 27, count 2 2006.280.07:31:10.63#ibcon#end of sib2, iclass 27, count 2 2006.280.07:31:10.63#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:31:10.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:31:10.63#ibcon#[25=AT06-06\r\n] 2006.280.07:31:10.63#ibcon#*before write, iclass 27, count 2 2006.280.07:31:10.63#ibcon#enter sib2, iclass 27, count 2 2006.280.07:31:10.63#ibcon#flushed, iclass 27, count 2 2006.280.07:31:10.63#ibcon#about to write, iclass 27, count 2 2006.280.07:31:10.63#ibcon#wrote, iclass 27, count 2 2006.280.07:31:10.63#ibcon#about to read 3, iclass 27, count 2 2006.280.07:31:10.66#ibcon#read 3, iclass 27, count 2 2006.280.07:31:10.66#ibcon#about to read 4, iclass 27, count 2 2006.280.07:31:10.66#ibcon#read 4, iclass 27, count 2 2006.280.07:31:10.66#ibcon#about to read 5, iclass 27, count 2 2006.280.07:31:10.66#ibcon#read 5, iclass 27, count 2 2006.280.07:31:10.66#ibcon#about to read 6, iclass 27, count 2 2006.280.07:31:10.66#ibcon#read 6, iclass 27, count 2 2006.280.07:31:10.66#ibcon#end of sib2, iclass 27, count 2 2006.280.07:31:10.66#ibcon#*after write, iclass 27, count 2 2006.280.07:31:10.66#ibcon#*before return 0, iclass 27, count 2 2006.280.07:31:10.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:10.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:10.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:31:10.66#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:10.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:31:10.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:31:10.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:31:10.78#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:31:10.78#ibcon#first serial, iclass 27, count 0 2006.280.07:31:10.78#ibcon#enter sib2, iclass 27, count 0 2006.280.07:31:10.78#ibcon#flushed, iclass 27, count 0 2006.280.07:31:10.78#ibcon#about to write, iclass 27, count 0 2006.280.07:31:10.78#ibcon#wrote, iclass 27, count 0 2006.280.07:31:10.78#ibcon#about to read 3, iclass 27, count 0 2006.280.07:31:10.80#ibcon#read 3, iclass 27, count 0 2006.280.07:31:10.80#ibcon#about to read 4, iclass 27, count 0 2006.280.07:31:10.80#ibcon#read 4, iclass 27, count 0 2006.280.07:31:10.80#ibcon#about to read 5, iclass 27, count 0 2006.280.07:31:10.80#ibcon#read 5, iclass 27, count 0 2006.280.07:31:10.80#ibcon#about to read 6, iclass 27, count 0 2006.280.07:31:10.80#ibcon#read 6, iclass 27, count 0 2006.280.07:31:10.80#ibcon#end of sib2, iclass 27, count 0 2006.280.07:31:10.80#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:31:10.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:31:10.80#ibcon#[25=USB\r\n] 2006.280.07:31:10.80#ibcon#*before write, iclass 27, count 0 2006.280.07:31:10.80#ibcon#enter sib2, iclass 27, count 0 2006.280.07:31:10.80#ibcon#flushed, iclass 27, count 0 2006.280.07:31:10.80#ibcon#about to write, iclass 27, count 0 2006.280.07:31:10.80#ibcon#wrote, iclass 27, count 0 2006.280.07:31:10.80#ibcon#about to read 3, iclass 27, count 0 2006.280.07:31:10.83#ibcon#read 3, iclass 27, count 0 2006.280.07:31:10.83#ibcon#about to read 4, iclass 27, count 0 2006.280.07:31:10.83#ibcon#read 4, iclass 27, count 0 2006.280.07:31:10.83#ibcon#about to read 5, iclass 27, count 0 2006.280.07:31:10.83#ibcon#read 5, iclass 27, count 0 2006.280.07:31:10.83#ibcon#about to read 6, iclass 27, count 0 2006.280.07:31:10.83#ibcon#read 6, iclass 27, count 0 2006.280.07:31:10.83#ibcon#end of sib2, iclass 27, count 0 2006.280.07:31:10.83#ibcon#*after write, iclass 27, count 0 2006.280.07:31:10.83#ibcon#*before return 0, iclass 27, count 0 2006.280.07:31:10.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:31:10.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:31:10.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:31:10.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:31:10.83$vc4f8/valo=7,832.99 2006.280.07:31:10.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:31:10.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:31:10.83#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:10.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:31:10.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:31:10.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:31:10.83#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:31:10.83#ibcon#first serial, iclass 29, count 0 2006.280.07:31:10.83#ibcon#enter sib2, iclass 29, count 0 2006.280.07:31:10.83#ibcon#flushed, iclass 29, count 0 2006.280.07:31:10.83#ibcon#about to write, iclass 29, count 0 2006.280.07:31:10.83#ibcon#wrote, iclass 29, count 0 2006.280.07:31:10.83#ibcon#about to read 3, iclass 29, count 0 2006.280.07:31:10.85#ibcon#read 3, iclass 29, count 0 2006.280.07:31:10.85#ibcon#about to read 4, iclass 29, count 0 2006.280.07:31:10.85#ibcon#read 4, iclass 29, count 0 2006.280.07:31:10.85#ibcon#about to read 5, iclass 29, count 0 2006.280.07:31:10.85#ibcon#read 5, iclass 29, count 0 2006.280.07:31:10.85#ibcon#about to read 6, iclass 29, count 0 2006.280.07:31:10.85#ibcon#read 6, iclass 29, count 0 2006.280.07:31:10.85#ibcon#end of sib2, iclass 29, count 0 2006.280.07:31:10.85#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:31:10.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:31:10.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:31:10.85#ibcon#*before write, iclass 29, count 0 2006.280.07:31:10.85#ibcon#enter sib2, iclass 29, count 0 2006.280.07:31:10.85#ibcon#flushed, iclass 29, count 0 2006.280.07:31:10.85#ibcon#about to write, iclass 29, count 0 2006.280.07:31:10.85#ibcon#wrote, iclass 29, count 0 2006.280.07:31:10.85#ibcon#about to read 3, iclass 29, count 0 2006.280.07:31:10.89#ibcon#read 3, iclass 29, count 0 2006.280.07:31:10.89#ibcon#about to read 4, iclass 29, count 0 2006.280.07:31:10.89#ibcon#read 4, iclass 29, count 0 2006.280.07:31:10.89#ibcon#about to read 5, iclass 29, count 0 2006.280.07:31:10.89#ibcon#read 5, iclass 29, count 0 2006.280.07:31:10.89#ibcon#about to read 6, iclass 29, count 0 2006.280.07:31:10.89#ibcon#read 6, iclass 29, count 0 2006.280.07:31:10.89#ibcon#end of sib2, iclass 29, count 0 2006.280.07:31:10.89#ibcon#*after write, iclass 29, count 0 2006.280.07:31:10.89#ibcon#*before return 0, iclass 29, count 0 2006.280.07:31:10.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:31:10.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:31:10.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:31:10.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:31:10.89$vc4f8/va=7,6 2006.280.07:31:10.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:31:10.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:31:10.89#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:10.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:31:10.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:31:10.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:31:10.95#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:31:10.95#ibcon#first serial, iclass 31, count 2 2006.280.07:31:10.95#ibcon#enter sib2, iclass 31, count 2 2006.280.07:31:10.95#ibcon#flushed, iclass 31, count 2 2006.280.07:31:10.95#ibcon#about to write, iclass 31, count 2 2006.280.07:31:10.95#ibcon#wrote, iclass 31, count 2 2006.280.07:31:10.95#ibcon#about to read 3, iclass 31, count 2 2006.280.07:31:10.97#ibcon#read 3, iclass 31, count 2 2006.280.07:31:10.97#ibcon#about to read 4, iclass 31, count 2 2006.280.07:31:10.97#ibcon#read 4, iclass 31, count 2 2006.280.07:31:10.97#ibcon#about to read 5, iclass 31, count 2 2006.280.07:31:10.97#ibcon#read 5, iclass 31, count 2 2006.280.07:31:10.97#ibcon#about to read 6, iclass 31, count 2 2006.280.07:31:10.97#ibcon#read 6, iclass 31, count 2 2006.280.07:31:10.97#ibcon#end of sib2, iclass 31, count 2 2006.280.07:31:10.97#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:31:10.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:31:10.97#ibcon#[25=AT07-06\r\n] 2006.280.07:31:10.97#ibcon#*before write, iclass 31, count 2 2006.280.07:31:10.97#ibcon#enter sib2, iclass 31, count 2 2006.280.07:31:10.97#ibcon#flushed, iclass 31, count 2 2006.280.07:31:10.97#ibcon#about to write, iclass 31, count 2 2006.280.07:31:10.97#ibcon#wrote, iclass 31, count 2 2006.280.07:31:10.97#ibcon#about to read 3, iclass 31, count 2 2006.280.07:31:11.00#ibcon#read 3, iclass 31, count 2 2006.280.07:31:11.00#ibcon#about to read 4, iclass 31, count 2 2006.280.07:31:11.00#ibcon#read 4, iclass 31, count 2 2006.280.07:31:11.00#ibcon#about to read 5, iclass 31, count 2 2006.280.07:31:11.00#ibcon#read 5, iclass 31, count 2 2006.280.07:31:11.00#ibcon#about to read 6, iclass 31, count 2 2006.280.07:31:11.00#ibcon#read 6, iclass 31, count 2 2006.280.07:31:11.00#ibcon#end of sib2, iclass 31, count 2 2006.280.07:31:11.00#ibcon#*after write, iclass 31, count 2 2006.280.07:31:11.00#ibcon#*before return 0, iclass 31, count 2 2006.280.07:31:11.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:31:11.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:31:11.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:31:11.00#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:11.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:31:11.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:31:11.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:31:11.12#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:31:11.12#ibcon#first serial, iclass 31, count 0 2006.280.07:31:11.12#ibcon#enter sib2, iclass 31, count 0 2006.280.07:31:11.12#ibcon#flushed, iclass 31, count 0 2006.280.07:31:11.12#ibcon#about to write, iclass 31, count 0 2006.280.07:31:11.12#ibcon#wrote, iclass 31, count 0 2006.280.07:31:11.12#ibcon#about to read 3, iclass 31, count 0 2006.280.07:31:11.14#ibcon#read 3, iclass 31, count 0 2006.280.07:31:11.14#ibcon#about to read 4, iclass 31, count 0 2006.280.07:31:11.14#ibcon#read 4, iclass 31, count 0 2006.280.07:31:11.14#ibcon#about to read 5, iclass 31, count 0 2006.280.07:31:11.14#ibcon#read 5, iclass 31, count 0 2006.280.07:31:11.14#ibcon#about to read 6, iclass 31, count 0 2006.280.07:31:11.14#ibcon#read 6, iclass 31, count 0 2006.280.07:31:11.14#ibcon#end of sib2, iclass 31, count 0 2006.280.07:31:11.14#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:31:11.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:31:11.14#ibcon#[25=USB\r\n] 2006.280.07:31:11.14#ibcon#*before write, iclass 31, count 0 2006.280.07:31:11.14#ibcon#enter sib2, iclass 31, count 0 2006.280.07:31:11.14#ibcon#flushed, iclass 31, count 0 2006.280.07:31:11.14#ibcon#about to write, iclass 31, count 0 2006.280.07:31:11.14#ibcon#wrote, iclass 31, count 0 2006.280.07:31:11.14#ibcon#about to read 3, iclass 31, count 0 2006.280.07:31:11.17#ibcon#read 3, iclass 31, count 0 2006.280.07:31:11.17#ibcon#about to read 4, iclass 31, count 0 2006.280.07:31:11.17#ibcon#read 4, iclass 31, count 0 2006.280.07:31:11.17#ibcon#about to read 5, iclass 31, count 0 2006.280.07:31:11.17#ibcon#read 5, iclass 31, count 0 2006.280.07:31:11.17#ibcon#about to read 6, iclass 31, count 0 2006.280.07:31:11.17#ibcon#read 6, iclass 31, count 0 2006.280.07:31:11.17#ibcon#end of sib2, iclass 31, count 0 2006.280.07:31:11.17#ibcon#*after write, iclass 31, count 0 2006.280.07:31:11.17#ibcon#*before return 0, iclass 31, count 0 2006.280.07:31:11.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:31:11.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:31:11.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:31:11.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:31:11.17$vc4f8/valo=8,852.99 2006.280.07:31:11.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:31:11.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:31:11.17#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:11.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:31:11.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:31:11.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:31:11.17#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:31:11.17#ibcon#first serial, iclass 33, count 0 2006.280.07:31:11.17#ibcon#enter sib2, iclass 33, count 0 2006.280.07:31:11.17#ibcon#flushed, iclass 33, count 0 2006.280.07:31:11.17#ibcon#about to write, iclass 33, count 0 2006.280.07:31:11.17#ibcon#wrote, iclass 33, count 0 2006.280.07:31:11.17#ibcon#about to read 3, iclass 33, count 0 2006.280.07:31:11.19#ibcon#read 3, iclass 33, count 0 2006.280.07:31:11.19#ibcon#about to read 4, iclass 33, count 0 2006.280.07:31:11.19#ibcon#read 4, iclass 33, count 0 2006.280.07:31:11.19#ibcon#about to read 5, iclass 33, count 0 2006.280.07:31:11.19#ibcon#read 5, iclass 33, count 0 2006.280.07:31:11.19#ibcon#about to read 6, iclass 33, count 0 2006.280.07:31:11.19#ibcon#read 6, iclass 33, count 0 2006.280.07:31:11.19#ibcon#end of sib2, iclass 33, count 0 2006.280.07:31:11.19#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:31:11.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:31:11.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:31:11.19#ibcon#*before write, iclass 33, count 0 2006.280.07:31:11.19#ibcon#enter sib2, iclass 33, count 0 2006.280.07:31:11.19#ibcon#flushed, iclass 33, count 0 2006.280.07:31:11.19#ibcon#about to write, iclass 33, count 0 2006.280.07:31:11.19#ibcon#wrote, iclass 33, count 0 2006.280.07:31:11.19#ibcon#about to read 3, iclass 33, count 0 2006.280.07:31:11.23#ibcon#read 3, iclass 33, count 0 2006.280.07:31:11.23#ibcon#about to read 4, iclass 33, count 0 2006.280.07:31:11.23#ibcon#read 4, iclass 33, count 0 2006.280.07:31:11.23#ibcon#about to read 5, iclass 33, count 0 2006.280.07:31:11.23#ibcon#read 5, iclass 33, count 0 2006.280.07:31:11.23#ibcon#about to read 6, iclass 33, count 0 2006.280.07:31:11.23#ibcon#read 6, iclass 33, count 0 2006.280.07:31:11.23#ibcon#end of sib2, iclass 33, count 0 2006.280.07:31:11.23#ibcon#*after write, iclass 33, count 0 2006.280.07:31:11.23#ibcon#*before return 0, iclass 33, count 0 2006.280.07:31:11.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:31:11.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:31:11.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:31:11.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:31:11.23$vc4f8/va=8,6 2006.280.07:31:11.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:31:11.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:31:11.23#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:11.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:31:11.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:31:11.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:31:11.29#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:31:11.29#ibcon#first serial, iclass 35, count 2 2006.280.07:31:11.29#ibcon#enter sib2, iclass 35, count 2 2006.280.07:31:11.29#ibcon#flushed, iclass 35, count 2 2006.280.07:31:11.29#ibcon#about to write, iclass 35, count 2 2006.280.07:31:11.29#ibcon#wrote, iclass 35, count 2 2006.280.07:31:11.29#ibcon#about to read 3, iclass 35, count 2 2006.280.07:31:11.31#ibcon#read 3, iclass 35, count 2 2006.280.07:31:11.31#ibcon#about to read 4, iclass 35, count 2 2006.280.07:31:11.31#ibcon#read 4, iclass 35, count 2 2006.280.07:31:11.31#ibcon#about to read 5, iclass 35, count 2 2006.280.07:31:11.31#ibcon#read 5, iclass 35, count 2 2006.280.07:31:11.31#ibcon#about to read 6, iclass 35, count 2 2006.280.07:31:11.31#ibcon#read 6, iclass 35, count 2 2006.280.07:31:11.31#ibcon#end of sib2, iclass 35, count 2 2006.280.07:31:11.31#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:31:11.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:31:11.31#ibcon#[25=AT08-06\r\n] 2006.280.07:31:11.31#ibcon#*before write, iclass 35, count 2 2006.280.07:31:11.31#ibcon#enter sib2, iclass 35, count 2 2006.280.07:31:11.31#ibcon#flushed, iclass 35, count 2 2006.280.07:31:11.31#ibcon#about to write, iclass 35, count 2 2006.280.07:31:11.31#ibcon#wrote, iclass 35, count 2 2006.280.07:31:11.31#ibcon#about to read 3, iclass 35, count 2 2006.280.07:31:11.34#ibcon#read 3, iclass 35, count 2 2006.280.07:31:11.34#ibcon#about to read 4, iclass 35, count 2 2006.280.07:31:11.34#ibcon#read 4, iclass 35, count 2 2006.280.07:31:11.34#ibcon#about to read 5, iclass 35, count 2 2006.280.07:31:11.34#ibcon#read 5, iclass 35, count 2 2006.280.07:31:11.34#ibcon#about to read 6, iclass 35, count 2 2006.280.07:31:11.34#ibcon#read 6, iclass 35, count 2 2006.280.07:31:11.34#ibcon#end of sib2, iclass 35, count 2 2006.280.07:31:11.34#ibcon#*after write, iclass 35, count 2 2006.280.07:31:11.34#ibcon#*before return 0, iclass 35, count 2 2006.280.07:31:11.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:31:11.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:31:11.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:31:11.34#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:11.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:31:11.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:31:11.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:31:11.46#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:31:11.46#ibcon#first serial, iclass 35, count 0 2006.280.07:31:11.46#ibcon#enter sib2, iclass 35, count 0 2006.280.07:31:11.46#ibcon#flushed, iclass 35, count 0 2006.280.07:31:11.46#ibcon#about to write, iclass 35, count 0 2006.280.07:31:11.46#ibcon#wrote, iclass 35, count 0 2006.280.07:31:11.46#ibcon#about to read 3, iclass 35, count 0 2006.280.07:31:11.48#ibcon#read 3, iclass 35, count 0 2006.280.07:31:11.48#ibcon#about to read 4, iclass 35, count 0 2006.280.07:31:11.48#ibcon#read 4, iclass 35, count 0 2006.280.07:31:11.48#ibcon#about to read 5, iclass 35, count 0 2006.280.07:31:11.48#ibcon#read 5, iclass 35, count 0 2006.280.07:31:11.48#ibcon#about to read 6, iclass 35, count 0 2006.280.07:31:11.48#ibcon#read 6, iclass 35, count 0 2006.280.07:31:11.48#ibcon#end of sib2, iclass 35, count 0 2006.280.07:31:11.48#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:31:11.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:31:11.48#ibcon#[25=USB\r\n] 2006.280.07:31:11.48#ibcon#*before write, iclass 35, count 0 2006.280.07:31:11.48#ibcon#enter sib2, iclass 35, count 0 2006.280.07:31:11.48#ibcon#flushed, iclass 35, count 0 2006.280.07:31:11.48#ibcon#about to write, iclass 35, count 0 2006.280.07:31:11.48#ibcon#wrote, iclass 35, count 0 2006.280.07:31:11.48#ibcon#about to read 3, iclass 35, count 0 2006.280.07:31:11.51#ibcon#read 3, iclass 35, count 0 2006.280.07:31:11.51#ibcon#about to read 4, iclass 35, count 0 2006.280.07:31:11.51#ibcon#read 4, iclass 35, count 0 2006.280.07:31:11.51#ibcon#about to read 5, iclass 35, count 0 2006.280.07:31:11.51#ibcon#read 5, iclass 35, count 0 2006.280.07:31:11.51#ibcon#about to read 6, iclass 35, count 0 2006.280.07:31:11.51#ibcon#read 6, iclass 35, count 0 2006.280.07:31:11.51#ibcon#end of sib2, iclass 35, count 0 2006.280.07:31:11.51#ibcon#*after write, iclass 35, count 0 2006.280.07:31:11.51#ibcon#*before return 0, iclass 35, count 0 2006.280.07:31:11.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:31:11.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:31:11.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:31:11.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:31:11.51$vc4f8/vblo=1,632.99 2006.280.07:31:11.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:31:11.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:31:11.51#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:11.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:31:11.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:31:11.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:31:11.51#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:31:11.51#ibcon#first serial, iclass 37, count 0 2006.280.07:31:11.51#ibcon#enter sib2, iclass 37, count 0 2006.280.07:31:11.51#ibcon#flushed, iclass 37, count 0 2006.280.07:31:11.51#ibcon#about to write, iclass 37, count 0 2006.280.07:31:11.51#ibcon#wrote, iclass 37, count 0 2006.280.07:31:11.51#ibcon#about to read 3, iclass 37, count 0 2006.280.07:31:11.53#ibcon#read 3, iclass 37, count 0 2006.280.07:31:11.53#ibcon#about to read 4, iclass 37, count 0 2006.280.07:31:11.53#ibcon#read 4, iclass 37, count 0 2006.280.07:31:11.53#ibcon#about to read 5, iclass 37, count 0 2006.280.07:31:11.53#ibcon#read 5, iclass 37, count 0 2006.280.07:31:11.53#ibcon#about to read 6, iclass 37, count 0 2006.280.07:31:11.53#ibcon#read 6, iclass 37, count 0 2006.280.07:31:11.53#ibcon#end of sib2, iclass 37, count 0 2006.280.07:31:11.53#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:31:11.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:31:11.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:31:11.53#ibcon#*before write, iclass 37, count 0 2006.280.07:31:11.53#ibcon#enter sib2, iclass 37, count 0 2006.280.07:31:11.53#ibcon#flushed, iclass 37, count 0 2006.280.07:31:11.53#ibcon#about to write, iclass 37, count 0 2006.280.07:31:11.53#ibcon#wrote, iclass 37, count 0 2006.280.07:31:11.53#ibcon#about to read 3, iclass 37, count 0 2006.280.07:31:11.57#ibcon#read 3, iclass 37, count 0 2006.280.07:31:11.57#ibcon#about to read 4, iclass 37, count 0 2006.280.07:31:11.57#ibcon#read 4, iclass 37, count 0 2006.280.07:31:11.57#ibcon#about to read 5, iclass 37, count 0 2006.280.07:31:11.57#ibcon#read 5, iclass 37, count 0 2006.280.07:31:11.57#ibcon#about to read 6, iclass 37, count 0 2006.280.07:31:11.57#ibcon#read 6, iclass 37, count 0 2006.280.07:31:11.57#ibcon#end of sib2, iclass 37, count 0 2006.280.07:31:11.57#ibcon#*after write, iclass 37, count 0 2006.280.07:31:11.57#ibcon#*before return 0, iclass 37, count 0 2006.280.07:31:11.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:31:11.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:31:11.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:31:11.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:31:11.57$vc4f8/vb=1,4 2006.280.07:31:11.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:31:11.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:31:11.57#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:11.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:31:11.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:31:11.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:31:11.57#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:31:11.57#ibcon#first serial, iclass 39, count 2 2006.280.07:31:11.57#ibcon#enter sib2, iclass 39, count 2 2006.280.07:31:11.57#ibcon#flushed, iclass 39, count 2 2006.280.07:31:11.57#ibcon#about to write, iclass 39, count 2 2006.280.07:31:11.57#ibcon#wrote, iclass 39, count 2 2006.280.07:31:11.57#ibcon#about to read 3, iclass 39, count 2 2006.280.07:31:11.59#ibcon#read 3, iclass 39, count 2 2006.280.07:31:11.59#ibcon#about to read 4, iclass 39, count 2 2006.280.07:31:11.59#ibcon#read 4, iclass 39, count 2 2006.280.07:31:11.59#ibcon#about to read 5, iclass 39, count 2 2006.280.07:31:11.59#ibcon#read 5, iclass 39, count 2 2006.280.07:31:11.59#ibcon#about to read 6, iclass 39, count 2 2006.280.07:31:11.59#ibcon#read 6, iclass 39, count 2 2006.280.07:31:11.59#ibcon#end of sib2, iclass 39, count 2 2006.280.07:31:11.59#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:31:11.62#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:31:11.62#ibcon#[27=AT01-04\r\n] 2006.280.07:31:11.62#ibcon#*before write, iclass 39, count 2 2006.280.07:31:11.62#ibcon#enter sib2, iclass 39, count 2 2006.280.07:31:11.62#ibcon#flushed, iclass 39, count 2 2006.280.07:31:11.62#ibcon#about to write, iclass 39, count 2 2006.280.07:31:11.62#ibcon#wrote, iclass 39, count 2 2006.280.07:31:11.62#ibcon#about to read 3, iclass 39, count 2 2006.280.07:31:11.65#ibcon#read 3, iclass 39, count 2 2006.280.07:31:11.65#ibcon#about to read 4, iclass 39, count 2 2006.280.07:31:11.65#ibcon#read 4, iclass 39, count 2 2006.280.07:31:11.65#ibcon#about to read 5, iclass 39, count 2 2006.280.07:31:11.65#ibcon#read 5, iclass 39, count 2 2006.280.07:31:11.65#ibcon#about to read 6, iclass 39, count 2 2006.280.07:31:11.65#ibcon#read 6, iclass 39, count 2 2006.280.07:31:11.65#ibcon#end of sib2, iclass 39, count 2 2006.280.07:31:11.65#ibcon#*after write, iclass 39, count 2 2006.280.07:31:11.65#ibcon#*before return 0, iclass 39, count 2 2006.280.07:31:11.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:31:11.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:31:11.65#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:31:11.65#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:11.65#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:31:11.77#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:31:11.77#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:31:11.77#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:31:11.77#ibcon#first serial, iclass 39, count 0 2006.280.07:31:11.77#ibcon#enter sib2, iclass 39, count 0 2006.280.07:31:11.77#ibcon#flushed, iclass 39, count 0 2006.280.07:31:11.77#ibcon#about to write, iclass 39, count 0 2006.280.07:31:11.77#ibcon#wrote, iclass 39, count 0 2006.280.07:31:11.77#ibcon#about to read 3, iclass 39, count 0 2006.280.07:31:11.79#ibcon#read 3, iclass 39, count 0 2006.280.07:31:11.79#ibcon#about to read 4, iclass 39, count 0 2006.280.07:31:11.79#ibcon#read 4, iclass 39, count 0 2006.280.07:31:11.79#ibcon#about to read 5, iclass 39, count 0 2006.280.07:31:11.79#ibcon#read 5, iclass 39, count 0 2006.280.07:31:11.79#ibcon#about to read 6, iclass 39, count 0 2006.280.07:31:11.79#ibcon#read 6, iclass 39, count 0 2006.280.07:31:11.79#ibcon#end of sib2, iclass 39, count 0 2006.280.07:31:11.79#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:31:11.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:31:11.79#ibcon#[27=USB\r\n] 2006.280.07:31:11.79#ibcon#*before write, iclass 39, count 0 2006.280.07:31:11.79#ibcon#enter sib2, iclass 39, count 0 2006.280.07:31:11.79#ibcon#flushed, iclass 39, count 0 2006.280.07:31:11.79#ibcon#about to write, iclass 39, count 0 2006.280.07:31:11.79#ibcon#wrote, iclass 39, count 0 2006.280.07:31:11.79#ibcon#about to read 3, iclass 39, count 0 2006.280.07:31:11.82#ibcon#read 3, iclass 39, count 0 2006.280.07:31:11.82#ibcon#about to read 4, iclass 39, count 0 2006.280.07:31:11.82#ibcon#read 4, iclass 39, count 0 2006.280.07:31:11.82#ibcon#about to read 5, iclass 39, count 0 2006.280.07:31:11.82#ibcon#read 5, iclass 39, count 0 2006.280.07:31:11.82#ibcon#about to read 6, iclass 39, count 0 2006.280.07:31:11.82#ibcon#read 6, iclass 39, count 0 2006.280.07:31:11.82#ibcon#end of sib2, iclass 39, count 0 2006.280.07:31:11.82#ibcon#*after write, iclass 39, count 0 2006.280.07:31:11.82#ibcon#*before return 0, iclass 39, count 0 2006.280.07:31:11.82#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:31:11.82#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:31:11.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:31:11.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:31:11.82$vc4f8/vblo=2,640.99 2006.280.07:31:11.82#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:31:11.82#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:31:11.82#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:11.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:11.82#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:11.82#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:11.82#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:31:11.82#ibcon#first serial, iclass 3, count 0 2006.280.07:31:11.82#ibcon#enter sib2, iclass 3, count 0 2006.280.07:31:11.82#ibcon#flushed, iclass 3, count 0 2006.280.07:31:11.82#ibcon#about to write, iclass 3, count 0 2006.280.07:31:11.82#ibcon#wrote, iclass 3, count 0 2006.280.07:31:11.82#ibcon#about to read 3, iclass 3, count 0 2006.280.07:31:11.84#ibcon#read 3, iclass 3, count 0 2006.280.07:31:11.84#ibcon#about to read 4, iclass 3, count 0 2006.280.07:31:11.84#ibcon#read 4, iclass 3, count 0 2006.280.07:31:11.84#ibcon#about to read 5, iclass 3, count 0 2006.280.07:31:11.84#ibcon#read 5, iclass 3, count 0 2006.280.07:31:11.84#ibcon#about to read 6, iclass 3, count 0 2006.280.07:31:11.84#ibcon#read 6, iclass 3, count 0 2006.280.07:31:11.84#ibcon#end of sib2, iclass 3, count 0 2006.280.07:31:11.84#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:31:11.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:31:11.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:31:11.84#ibcon#*before write, iclass 3, count 0 2006.280.07:31:11.84#ibcon#enter sib2, iclass 3, count 0 2006.280.07:31:11.84#ibcon#flushed, iclass 3, count 0 2006.280.07:31:11.84#ibcon#about to write, iclass 3, count 0 2006.280.07:31:11.84#ibcon#wrote, iclass 3, count 0 2006.280.07:31:11.84#ibcon#about to read 3, iclass 3, count 0 2006.280.07:31:11.88#ibcon#read 3, iclass 3, count 0 2006.280.07:31:11.88#ibcon#about to read 4, iclass 3, count 0 2006.280.07:31:11.88#ibcon#read 4, iclass 3, count 0 2006.280.07:31:11.88#ibcon#about to read 5, iclass 3, count 0 2006.280.07:31:11.88#ibcon#read 5, iclass 3, count 0 2006.280.07:31:11.88#ibcon#about to read 6, iclass 3, count 0 2006.280.07:31:11.88#ibcon#read 6, iclass 3, count 0 2006.280.07:31:11.88#ibcon#end of sib2, iclass 3, count 0 2006.280.07:31:11.88#ibcon#*after write, iclass 3, count 0 2006.280.07:31:11.88#ibcon#*before return 0, iclass 3, count 0 2006.280.07:31:11.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:11.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:31:11.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:31:11.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:31:11.88$vc4f8/vb=2,5 2006.280.07:31:11.88#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:31:11.88#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:31:11.88#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:11.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:11.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:11.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:11.94#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:31:11.94#ibcon#first serial, iclass 5, count 2 2006.280.07:31:11.94#ibcon#enter sib2, iclass 5, count 2 2006.280.07:31:11.94#ibcon#flushed, iclass 5, count 2 2006.280.07:31:11.94#ibcon#about to write, iclass 5, count 2 2006.280.07:31:11.94#ibcon#wrote, iclass 5, count 2 2006.280.07:31:11.94#ibcon#about to read 3, iclass 5, count 2 2006.280.07:31:11.96#ibcon#read 3, iclass 5, count 2 2006.280.07:31:11.96#ibcon#about to read 4, iclass 5, count 2 2006.280.07:31:11.96#ibcon#read 4, iclass 5, count 2 2006.280.07:31:11.96#ibcon#about to read 5, iclass 5, count 2 2006.280.07:31:11.96#ibcon#read 5, iclass 5, count 2 2006.280.07:31:11.96#ibcon#about to read 6, iclass 5, count 2 2006.280.07:31:11.96#ibcon#read 6, iclass 5, count 2 2006.280.07:31:11.96#ibcon#end of sib2, iclass 5, count 2 2006.280.07:31:11.96#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:31:11.96#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:31:11.96#ibcon#[27=AT02-05\r\n] 2006.280.07:31:11.96#ibcon#*before write, iclass 5, count 2 2006.280.07:31:11.96#ibcon#enter sib2, iclass 5, count 2 2006.280.07:31:11.96#ibcon#flushed, iclass 5, count 2 2006.280.07:31:11.96#ibcon#about to write, iclass 5, count 2 2006.280.07:31:11.96#ibcon#wrote, iclass 5, count 2 2006.280.07:31:11.96#ibcon#about to read 3, iclass 5, count 2 2006.280.07:31:11.99#ibcon#read 3, iclass 5, count 2 2006.280.07:31:11.99#ibcon#about to read 4, iclass 5, count 2 2006.280.07:31:11.99#ibcon#read 4, iclass 5, count 2 2006.280.07:31:11.99#ibcon#about to read 5, iclass 5, count 2 2006.280.07:31:11.99#ibcon#read 5, iclass 5, count 2 2006.280.07:31:11.99#ibcon#about to read 6, iclass 5, count 2 2006.280.07:31:11.99#ibcon#read 6, iclass 5, count 2 2006.280.07:31:11.99#ibcon#end of sib2, iclass 5, count 2 2006.280.07:31:11.99#ibcon#*after write, iclass 5, count 2 2006.280.07:31:11.99#ibcon#*before return 0, iclass 5, count 2 2006.280.07:31:11.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:11.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:31:11.99#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:31:11.99#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:11.99#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:12.11#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:12.11#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:12.11#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:31:12.11#ibcon#first serial, iclass 5, count 0 2006.280.07:31:12.11#ibcon#enter sib2, iclass 5, count 0 2006.280.07:31:12.11#ibcon#flushed, iclass 5, count 0 2006.280.07:31:12.11#ibcon#about to write, iclass 5, count 0 2006.280.07:31:12.11#ibcon#wrote, iclass 5, count 0 2006.280.07:31:12.11#ibcon#about to read 3, iclass 5, count 0 2006.280.07:31:12.13#ibcon#read 3, iclass 5, count 0 2006.280.07:31:12.13#ibcon#about to read 4, iclass 5, count 0 2006.280.07:31:12.13#ibcon#read 4, iclass 5, count 0 2006.280.07:31:12.13#ibcon#about to read 5, iclass 5, count 0 2006.280.07:31:12.13#ibcon#read 5, iclass 5, count 0 2006.280.07:31:12.13#ibcon#about to read 6, iclass 5, count 0 2006.280.07:31:12.13#ibcon#read 6, iclass 5, count 0 2006.280.07:31:12.13#ibcon#end of sib2, iclass 5, count 0 2006.280.07:31:12.13#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:31:12.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:31:12.13#ibcon#[27=USB\r\n] 2006.280.07:31:12.13#ibcon#*before write, iclass 5, count 0 2006.280.07:31:12.13#ibcon#enter sib2, iclass 5, count 0 2006.280.07:31:12.13#ibcon#flushed, iclass 5, count 0 2006.280.07:31:12.13#ibcon#about to write, iclass 5, count 0 2006.280.07:31:12.13#ibcon#wrote, iclass 5, count 0 2006.280.07:31:12.13#ibcon#about to read 3, iclass 5, count 0 2006.280.07:31:12.16#ibcon#read 3, iclass 5, count 0 2006.280.07:31:12.16#ibcon#about to read 4, iclass 5, count 0 2006.280.07:31:12.16#ibcon#read 4, iclass 5, count 0 2006.280.07:31:12.16#ibcon#about to read 5, iclass 5, count 0 2006.280.07:31:12.16#ibcon#read 5, iclass 5, count 0 2006.280.07:31:12.16#ibcon#about to read 6, iclass 5, count 0 2006.280.07:31:12.16#ibcon#read 6, iclass 5, count 0 2006.280.07:31:12.16#ibcon#end of sib2, iclass 5, count 0 2006.280.07:31:12.16#ibcon#*after write, iclass 5, count 0 2006.280.07:31:12.16#ibcon#*before return 0, iclass 5, count 0 2006.280.07:31:12.16#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:12.16#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:31:12.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:31:12.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:31:12.16$vc4f8/vblo=3,656.99 2006.280.07:31:12.16#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:31:12.16#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:31:12.16#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:12.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:12.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:12.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:12.16#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:31:12.16#ibcon#first serial, iclass 7, count 0 2006.280.07:31:12.16#ibcon#enter sib2, iclass 7, count 0 2006.280.07:31:12.16#ibcon#flushed, iclass 7, count 0 2006.280.07:31:12.16#ibcon#about to write, iclass 7, count 0 2006.280.07:31:12.16#ibcon#wrote, iclass 7, count 0 2006.280.07:31:12.16#ibcon#about to read 3, iclass 7, count 0 2006.280.07:31:12.18#ibcon#read 3, iclass 7, count 0 2006.280.07:31:12.18#ibcon#about to read 4, iclass 7, count 0 2006.280.07:31:12.18#ibcon#read 4, iclass 7, count 0 2006.280.07:31:12.18#ibcon#about to read 5, iclass 7, count 0 2006.280.07:31:12.18#ibcon#read 5, iclass 7, count 0 2006.280.07:31:12.18#ibcon#about to read 6, iclass 7, count 0 2006.280.07:31:12.18#ibcon#read 6, iclass 7, count 0 2006.280.07:31:12.18#ibcon#end of sib2, iclass 7, count 0 2006.280.07:31:12.18#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:31:12.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:31:12.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:31:12.18#ibcon#*before write, iclass 7, count 0 2006.280.07:31:12.18#ibcon#enter sib2, iclass 7, count 0 2006.280.07:31:12.18#ibcon#flushed, iclass 7, count 0 2006.280.07:31:12.18#ibcon#about to write, iclass 7, count 0 2006.280.07:31:12.18#ibcon#wrote, iclass 7, count 0 2006.280.07:31:12.18#ibcon#about to read 3, iclass 7, count 0 2006.280.07:31:12.22#ibcon#read 3, iclass 7, count 0 2006.280.07:31:12.22#ibcon#about to read 4, iclass 7, count 0 2006.280.07:31:12.22#ibcon#read 4, iclass 7, count 0 2006.280.07:31:12.22#ibcon#about to read 5, iclass 7, count 0 2006.280.07:31:12.22#ibcon#read 5, iclass 7, count 0 2006.280.07:31:12.22#ibcon#about to read 6, iclass 7, count 0 2006.280.07:31:12.22#ibcon#read 6, iclass 7, count 0 2006.280.07:31:12.22#ibcon#end of sib2, iclass 7, count 0 2006.280.07:31:12.22#ibcon#*after write, iclass 7, count 0 2006.280.07:31:12.22#ibcon#*before return 0, iclass 7, count 0 2006.280.07:31:12.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:12.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:31:12.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:31:12.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:31:12.22$vc4f8/vb=3,4 2006.280.07:31:12.22#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:31:12.22#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:31:12.22#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:12.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:12.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:12.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:12.28#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:31:12.28#ibcon#first serial, iclass 11, count 2 2006.280.07:31:12.28#ibcon#enter sib2, iclass 11, count 2 2006.280.07:31:12.28#ibcon#flushed, iclass 11, count 2 2006.280.07:31:12.28#ibcon#about to write, iclass 11, count 2 2006.280.07:31:12.28#ibcon#wrote, iclass 11, count 2 2006.280.07:31:12.28#ibcon#about to read 3, iclass 11, count 2 2006.280.07:31:12.30#ibcon#read 3, iclass 11, count 2 2006.280.07:31:12.30#ibcon#about to read 4, iclass 11, count 2 2006.280.07:31:12.30#ibcon#read 4, iclass 11, count 2 2006.280.07:31:12.30#ibcon#about to read 5, iclass 11, count 2 2006.280.07:31:12.30#ibcon#read 5, iclass 11, count 2 2006.280.07:31:12.30#ibcon#about to read 6, iclass 11, count 2 2006.280.07:31:12.30#ibcon#read 6, iclass 11, count 2 2006.280.07:31:12.30#ibcon#end of sib2, iclass 11, count 2 2006.280.07:31:12.30#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:31:12.30#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:31:12.30#ibcon#[27=AT03-04\r\n] 2006.280.07:31:12.30#ibcon#*before write, iclass 11, count 2 2006.280.07:31:12.30#ibcon#enter sib2, iclass 11, count 2 2006.280.07:31:12.30#ibcon#flushed, iclass 11, count 2 2006.280.07:31:12.30#ibcon#about to write, iclass 11, count 2 2006.280.07:31:12.30#ibcon#wrote, iclass 11, count 2 2006.280.07:31:12.30#ibcon#about to read 3, iclass 11, count 2 2006.280.07:31:12.33#ibcon#read 3, iclass 11, count 2 2006.280.07:31:12.33#ibcon#about to read 4, iclass 11, count 2 2006.280.07:31:12.33#ibcon#read 4, iclass 11, count 2 2006.280.07:31:12.33#ibcon#about to read 5, iclass 11, count 2 2006.280.07:31:12.33#ibcon#read 5, iclass 11, count 2 2006.280.07:31:12.33#ibcon#about to read 6, iclass 11, count 2 2006.280.07:31:12.33#ibcon#read 6, iclass 11, count 2 2006.280.07:31:12.33#ibcon#end of sib2, iclass 11, count 2 2006.280.07:31:12.33#ibcon#*after write, iclass 11, count 2 2006.280.07:31:12.33#ibcon#*before return 0, iclass 11, count 2 2006.280.07:31:12.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:12.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:31:12.33#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:31:12.33#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:12.33#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:12.45#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:12.45#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:12.45#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:31:12.45#ibcon#first serial, iclass 11, count 0 2006.280.07:31:12.45#ibcon#enter sib2, iclass 11, count 0 2006.280.07:31:12.45#ibcon#flushed, iclass 11, count 0 2006.280.07:31:12.45#ibcon#about to write, iclass 11, count 0 2006.280.07:31:12.45#ibcon#wrote, iclass 11, count 0 2006.280.07:31:12.45#ibcon#about to read 3, iclass 11, count 0 2006.280.07:31:12.47#ibcon#read 3, iclass 11, count 0 2006.280.07:31:12.47#ibcon#about to read 4, iclass 11, count 0 2006.280.07:31:12.47#ibcon#read 4, iclass 11, count 0 2006.280.07:31:12.47#ibcon#about to read 5, iclass 11, count 0 2006.280.07:31:12.47#ibcon#read 5, iclass 11, count 0 2006.280.07:31:12.47#ibcon#about to read 6, iclass 11, count 0 2006.280.07:31:12.47#ibcon#read 6, iclass 11, count 0 2006.280.07:31:12.47#ibcon#end of sib2, iclass 11, count 0 2006.280.07:31:12.47#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:31:12.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:31:12.47#ibcon#[27=USB\r\n] 2006.280.07:31:12.47#ibcon#*before write, iclass 11, count 0 2006.280.07:31:12.47#ibcon#enter sib2, iclass 11, count 0 2006.280.07:31:12.47#ibcon#flushed, iclass 11, count 0 2006.280.07:31:12.47#ibcon#about to write, iclass 11, count 0 2006.280.07:31:12.47#ibcon#wrote, iclass 11, count 0 2006.280.07:31:12.47#ibcon#about to read 3, iclass 11, count 0 2006.280.07:31:12.50#ibcon#read 3, iclass 11, count 0 2006.280.07:31:12.50#ibcon#about to read 4, iclass 11, count 0 2006.280.07:31:12.50#ibcon#read 4, iclass 11, count 0 2006.280.07:31:12.50#ibcon#about to read 5, iclass 11, count 0 2006.280.07:31:12.50#ibcon#read 5, iclass 11, count 0 2006.280.07:31:12.50#ibcon#about to read 6, iclass 11, count 0 2006.280.07:31:12.50#ibcon#read 6, iclass 11, count 0 2006.280.07:31:12.50#ibcon#end of sib2, iclass 11, count 0 2006.280.07:31:12.50#ibcon#*after write, iclass 11, count 0 2006.280.07:31:12.50#ibcon#*before return 0, iclass 11, count 0 2006.280.07:31:12.50#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:12.50#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:31:12.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:31:12.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:31:12.50$vc4f8/vblo=4,712.99 2006.280.07:31:12.50#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:31:12.50#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:31:12.50#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:12.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:12.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:12.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:12.50#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:31:12.50#ibcon#first serial, iclass 13, count 0 2006.280.07:31:12.50#ibcon#enter sib2, iclass 13, count 0 2006.280.07:31:12.50#ibcon#flushed, iclass 13, count 0 2006.280.07:31:12.50#ibcon#about to write, iclass 13, count 0 2006.280.07:31:12.50#ibcon#wrote, iclass 13, count 0 2006.280.07:31:12.50#ibcon#about to read 3, iclass 13, count 0 2006.280.07:31:12.52#ibcon#read 3, iclass 13, count 0 2006.280.07:31:12.52#ibcon#about to read 4, iclass 13, count 0 2006.280.07:31:12.52#ibcon#read 4, iclass 13, count 0 2006.280.07:31:12.52#ibcon#about to read 5, iclass 13, count 0 2006.280.07:31:12.52#ibcon#read 5, iclass 13, count 0 2006.280.07:31:12.52#ibcon#about to read 6, iclass 13, count 0 2006.280.07:31:12.52#ibcon#read 6, iclass 13, count 0 2006.280.07:31:12.52#ibcon#end of sib2, iclass 13, count 0 2006.280.07:31:12.52#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:31:12.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:31:12.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:31:12.52#ibcon#*before write, iclass 13, count 0 2006.280.07:31:12.52#ibcon#enter sib2, iclass 13, count 0 2006.280.07:31:12.52#ibcon#flushed, iclass 13, count 0 2006.280.07:31:12.52#ibcon#about to write, iclass 13, count 0 2006.280.07:31:12.52#ibcon#wrote, iclass 13, count 0 2006.280.07:31:12.52#ibcon#about to read 3, iclass 13, count 0 2006.280.07:31:12.56#ibcon#read 3, iclass 13, count 0 2006.280.07:31:12.56#ibcon#about to read 4, iclass 13, count 0 2006.280.07:31:12.56#ibcon#read 4, iclass 13, count 0 2006.280.07:31:12.56#ibcon#about to read 5, iclass 13, count 0 2006.280.07:31:12.56#ibcon#read 5, iclass 13, count 0 2006.280.07:31:12.56#ibcon#about to read 6, iclass 13, count 0 2006.280.07:31:12.56#ibcon#read 6, iclass 13, count 0 2006.280.07:31:12.56#ibcon#end of sib2, iclass 13, count 0 2006.280.07:31:12.56#ibcon#*after write, iclass 13, count 0 2006.280.07:31:12.56#ibcon#*before return 0, iclass 13, count 0 2006.280.07:31:12.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:12.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:31:12.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:31:12.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:31:12.56$vc4f8/vb=4,4 2006.280.07:31:12.56#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:31:12.56#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:31:12.56#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:12.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:12.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:12.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:12.62#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:31:12.62#ibcon#first serial, iclass 15, count 2 2006.280.07:31:12.62#ibcon#enter sib2, iclass 15, count 2 2006.280.07:31:12.62#ibcon#flushed, iclass 15, count 2 2006.280.07:31:12.62#ibcon#about to write, iclass 15, count 2 2006.280.07:31:12.62#ibcon#wrote, iclass 15, count 2 2006.280.07:31:12.62#ibcon#about to read 3, iclass 15, count 2 2006.280.07:31:12.64#ibcon#read 3, iclass 15, count 2 2006.280.07:31:12.64#ibcon#about to read 4, iclass 15, count 2 2006.280.07:31:12.64#ibcon#read 4, iclass 15, count 2 2006.280.07:31:12.64#ibcon#about to read 5, iclass 15, count 2 2006.280.07:31:12.64#ibcon#read 5, iclass 15, count 2 2006.280.07:31:12.64#ibcon#about to read 6, iclass 15, count 2 2006.280.07:31:12.64#ibcon#read 6, iclass 15, count 2 2006.280.07:31:12.64#ibcon#end of sib2, iclass 15, count 2 2006.280.07:31:12.64#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:31:12.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:31:12.64#ibcon#[27=AT04-04\r\n] 2006.280.07:31:12.64#ibcon#*before write, iclass 15, count 2 2006.280.07:31:12.64#ibcon#enter sib2, iclass 15, count 2 2006.280.07:31:12.64#ibcon#flushed, iclass 15, count 2 2006.280.07:31:12.64#ibcon#about to write, iclass 15, count 2 2006.280.07:31:12.64#ibcon#wrote, iclass 15, count 2 2006.280.07:31:12.64#ibcon#about to read 3, iclass 15, count 2 2006.280.07:31:12.67#ibcon#read 3, iclass 15, count 2 2006.280.07:31:12.67#ibcon#about to read 4, iclass 15, count 2 2006.280.07:31:12.67#ibcon#read 4, iclass 15, count 2 2006.280.07:31:12.67#ibcon#about to read 5, iclass 15, count 2 2006.280.07:31:12.67#ibcon#read 5, iclass 15, count 2 2006.280.07:31:12.67#ibcon#about to read 6, iclass 15, count 2 2006.280.07:31:12.67#ibcon#read 6, iclass 15, count 2 2006.280.07:31:12.67#ibcon#end of sib2, iclass 15, count 2 2006.280.07:31:12.67#ibcon#*after write, iclass 15, count 2 2006.280.07:31:12.67#ibcon#*before return 0, iclass 15, count 2 2006.280.07:31:12.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:12.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:31:12.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:31:12.67#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:12.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:12.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:12.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:12.79#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:31:12.79#ibcon#first serial, iclass 15, count 0 2006.280.07:31:12.79#ibcon#enter sib2, iclass 15, count 0 2006.280.07:31:12.79#ibcon#flushed, iclass 15, count 0 2006.280.07:31:12.79#ibcon#about to write, iclass 15, count 0 2006.280.07:31:12.79#ibcon#wrote, iclass 15, count 0 2006.280.07:31:12.79#ibcon#about to read 3, iclass 15, count 0 2006.280.07:31:12.81#ibcon#read 3, iclass 15, count 0 2006.280.07:31:12.81#ibcon#about to read 4, iclass 15, count 0 2006.280.07:31:12.81#ibcon#read 4, iclass 15, count 0 2006.280.07:31:12.81#ibcon#about to read 5, iclass 15, count 0 2006.280.07:31:12.81#ibcon#read 5, iclass 15, count 0 2006.280.07:31:12.81#ibcon#about to read 6, iclass 15, count 0 2006.280.07:31:12.81#ibcon#read 6, iclass 15, count 0 2006.280.07:31:12.81#ibcon#end of sib2, iclass 15, count 0 2006.280.07:31:12.81#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:31:12.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:31:12.81#ibcon#[27=USB\r\n] 2006.280.07:31:12.81#ibcon#*before write, iclass 15, count 0 2006.280.07:31:12.81#ibcon#enter sib2, iclass 15, count 0 2006.280.07:31:12.81#ibcon#flushed, iclass 15, count 0 2006.280.07:31:12.81#ibcon#about to write, iclass 15, count 0 2006.280.07:31:12.81#ibcon#wrote, iclass 15, count 0 2006.280.07:31:12.81#ibcon#about to read 3, iclass 15, count 0 2006.280.07:31:12.84#ibcon#read 3, iclass 15, count 0 2006.280.07:31:12.84#ibcon#about to read 4, iclass 15, count 0 2006.280.07:31:12.84#ibcon#read 4, iclass 15, count 0 2006.280.07:31:12.84#ibcon#about to read 5, iclass 15, count 0 2006.280.07:31:12.84#ibcon#read 5, iclass 15, count 0 2006.280.07:31:12.84#ibcon#about to read 6, iclass 15, count 0 2006.280.07:31:12.84#ibcon#read 6, iclass 15, count 0 2006.280.07:31:12.84#ibcon#end of sib2, iclass 15, count 0 2006.280.07:31:12.84#ibcon#*after write, iclass 15, count 0 2006.280.07:31:12.84#ibcon#*before return 0, iclass 15, count 0 2006.280.07:31:12.84#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:12.84#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:31:12.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:31:12.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:31:12.84$vc4f8/vblo=5,744.99 2006.280.07:31:12.84#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:31:12.84#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:31:12.84#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:12.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:12.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:12.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:12.84#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:31:12.84#ibcon#first serial, iclass 17, count 0 2006.280.07:31:12.84#ibcon#enter sib2, iclass 17, count 0 2006.280.07:31:12.84#ibcon#flushed, iclass 17, count 0 2006.280.07:31:12.84#ibcon#about to write, iclass 17, count 0 2006.280.07:31:12.84#ibcon#wrote, iclass 17, count 0 2006.280.07:31:12.84#ibcon#about to read 3, iclass 17, count 0 2006.280.07:31:12.86#ibcon#read 3, iclass 17, count 0 2006.280.07:31:12.86#ibcon#about to read 4, iclass 17, count 0 2006.280.07:31:12.86#ibcon#read 4, iclass 17, count 0 2006.280.07:31:12.86#ibcon#about to read 5, iclass 17, count 0 2006.280.07:31:12.86#ibcon#read 5, iclass 17, count 0 2006.280.07:31:12.86#ibcon#about to read 6, iclass 17, count 0 2006.280.07:31:12.86#ibcon#read 6, iclass 17, count 0 2006.280.07:31:12.86#ibcon#end of sib2, iclass 17, count 0 2006.280.07:31:12.86#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:31:12.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:31:12.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:31:12.86#ibcon#*before write, iclass 17, count 0 2006.280.07:31:12.86#ibcon#enter sib2, iclass 17, count 0 2006.280.07:31:12.86#ibcon#flushed, iclass 17, count 0 2006.280.07:31:12.86#ibcon#about to write, iclass 17, count 0 2006.280.07:31:12.86#ibcon#wrote, iclass 17, count 0 2006.280.07:31:12.86#ibcon#about to read 3, iclass 17, count 0 2006.280.07:31:12.90#ibcon#read 3, iclass 17, count 0 2006.280.07:31:12.90#ibcon#about to read 4, iclass 17, count 0 2006.280.07:31:12.90#ibcon#read 4, iclass 17, count 0 2006.280.07:31:12.90#ibcon#about to read 5, iclass 17, count 0 2006.280.07:31:12.90#ibcon#read 5, iclass 17, count 0 2006.280.07:31:12.90#ibcon#about to read 6, iclass 17, count 0 2006.280.07:31:12.90#ibcon#read 6, iclass 17, count 0 2006.280.07:31:12.90#ibcon#end of sib2, iclass 17, count 0 2006.280.07:31:12.90#ibcon#*after write, iclass 17, count 0 2006.280.07:31:12.90#ibcon#*before return 0, iclass 17, count 0 2006.280.07:31:12.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:12.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:31:12.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:31:12.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:31:12.90$vc4f8/vb=5,4 2006.280.07:31:12.90#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:31:12.90#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:31:12.90#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:12.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:12.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:12.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:12.96#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:31:12.96#ibcon#first serial, iclass 19, count 2 2006.280.07:31:12.96#ibcon#enter sib2, iclass 19, count 2 2006.280.07:31:12.96#ibcon#flushed, iclass 19, count 2 2006.280.07:31:12.96#ibcon#about to write, iclass 19, count 2 2006.280.07:31:12.96#ibcon#wrote, iclass 19, count 2 2006.280.07:31:12.96#ibcon#about to read 3, iclass 19, count 2 2006.280.07:31:12.98#ibcon#read 3, iclass 19, count 2 2006.280.07:31:12.98#ibcon#about to read 4, iclass 19, count 2 2006.280.07:31:12.98#ibcon#read 4, iclass 19, count 2 2006.280.07:31:12.98#ibcon#about to read 5, iclass 19, count 2 2006.280.07:31:12.98#ibcon#read 5, iclass 19, count 2 2006.280.07:31:12.98#ibcon#about to read 6, iclass 19, count 2 2006.280.07:31:12.98#ibcon#read 6, iclass 19, count 2 2006.280.07:31:12.98#ibcon#end of sib2, iclass 19, count 2 2006.280.07:31:12.98#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:31:12.98#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:31:12.98#ibcon#[27=AT05-04\r\n] 2006.280.07:31:12.98#ibcon#*before write, iclass 19, count 2 2006.280.07:31:12.98#ibcon#enter sib2, iclass 19, count 2 2006.280.07:31:12.98#ibcon#flushed, iclass 19, count 2 2006.280.07:31:12.98#ibcon#about to write, iclass 19, count 2 2006.280.07:31:12.98#ibcon#wrote, iclass 19, count 2 2006.280.07:31:12.98#ibcon#about to read 3, iclass 19, count 2 2006.280.07:31:13.01#ibcon#read 3, iclass 19, count 2 2006.280.07:31:13.01#ibcon#about to read 4, iclass 19, count 2 2006.280.07:31:13.01#ibcon#read 4, iclass 19, count 2 2006.280.07:31:13.01#ibcon#about to read 5, iclass 19, count 2 2006.280.07:31:13.01#ibcon#read 5, iclass 19, count 2 2006.280.07:31:13.01#ibcon#about to read 6, iclass 19, count 2 2006.280.07:31:13.01#ibcon#read 6, iclass 19, count 2 2006.280.07:31:13.01#ibcon#end of sib2, iclass 19, count 2 2006.280.07:31:13.01#ibcon#*after write, iclass 19, count 2 2006.280.07:31:13.01#ibcon#*before return 0, iclass 19, count 2 2006.280.07:31:13.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:13.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:31:13.01#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:31:13.01#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:13.01#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:13.13#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:13.13#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:13.13#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:31:13.13#ibcon#first serial, iclass 19, count 0 2006.280.07:31:13.13#ibcon#enter sib2, iclass 19, count 0 2006.280.07:31:13.13#ibcon#flushed, iclass 19, count 0 2006.280.07:31:13.13#ibcon#about to write, iclass 19, count 0 2006.280.07:31:13.13#ibcon#wrote, iclass 19, count 0 2006.280.07:31:13.13#ibcon#about to read 3, iclass 19, count 0 2006.280.07:31:13.15#ibcon#read 3, iclass 19, count 0 2006.280.07:31:13.15#ibcon#about to read 4, iclass 19, count 0 2006.280.07:31:13.15#ibcon#read 4, iclass 19, count 0 2006.280.07:31:13.15#ibcon#about to read 5, iclass 19, count 0 2006.280.07:31:13.15#ibcon#read 5, iclass 19, count 0 2006.280.07:31:13.15#ibcon#about to read 6, iclass 19, count 0 2006.280.07:31:13.15#ibcon#read 6, iclass 19, count 0 2006.280.07:31:13.15#ibcon#end of sib2, iclass 19, count 0 2006.280.07:31:13.15#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:31:13.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:31:13.15#ibcon#[27=USB\r\n] 2006.280.07:31:13.15#ibcon#*before write, iclass 19, count 0 2006.280.07:31:13.15#ibcon#enter sib2, iclass 19, count 0 2006.280.07:31:13.15#ibcon#flushed, iclass 19, count 0 2006.280.07:31:13.15#ibcon#about to write, iclass 19, count 0 2006.280.07:31:13.15#ibcon#wrote, iclass 19, count 0 2006.280.07:31:13.15#ibcon#about to read 3, iclass 19, count 0 2006.280.07:31:13.18#ibcon#read 3, iclass 19, count 0 2006.280.07:31:13.18#ibcon#about to read 4, iclass 19, count 0 2006.280.07:31:13.18#ibcon#read 4, iclass 19, count 0 2006.280.07:31:13.18#ibcon#about to read 5, iclass 19, count 0 2006.280.07:31:13.18#ibcon#read 5, iclass 19, count 0 2006.280.07:31:13.18#ibcon#about to read 6, iclass 19, count 0 2006.280.07:31:13.18#ibcon#read 6, iclass 19, count 0 2006.280.07:31:13.18#ibcon#end of sib2, iclass 19, count 0 2006.280.07:31:13.18#ibcon#*after write, iclass 19, count 0 2006.280.07:31:13.18#ibcon#*before return 0, iclass 19, count 0 2006.280.07:31:13.18#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:13.18#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:31:13.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:31:13.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:31:13.18$vc4f8/vblo=6,752.99 2006.280.07:31:13.18#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:31:13.18#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:31:13.18#ibcon#ireg 17 cls_cnt 0 2006.280.07:31:13.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:13.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:13.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:13.18#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:31:13.18#ibcon#first serial, iclass 21, count 0 2006.280.07:31:13.18#ibcon#enter sib2, iclass 21, count 0 2006.280.07:31:13.18#ibcon#flushed, iclass 21, count 0 2006.280.07:31:13.18#ibcon#about to write, iclass 21, count 0 2006.280.07:31:13.18#ibcon#wrote, iclass 21, count 0 2006.280.07:31:13.18#ibcon#about to read 3, iclass 21, count 0 2006.280.07:31:13.20#ibcon#read 3, iclass 21, count 0 2006.280.07:31:13.20#ibcon#about to read 4, iclass 21, count 0 2006.280.07:31:13.20#ibcon#read 4, iclass 21, count 0 2006.280.07:31:13.20#ibcon#about to read 5, iclass 21, count 0 2006.280.07:31:13.20#ibcon#read 5, iclass 21, count 0 2006.280.07:31:13.20#ibcon#about to read 6, iclass 21, count 0 2006.280.07:31:13.20#ibcon#read 6, iclass 21, count 0 2006.280.07:31:13.20#ibcon#end of sib2, iclass 21, count 0 2006.280.07:31:13.20#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:31:13.20#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:31:13.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:31:13.20#ibcon#*before write, iclass 21, count 0 2006.280.07:31:13.20#ibcon#enter sib2, iclass 21, count 0 2006.280.07:31:13.20#ibcon#flushed, iclass 21, count 0 2006.280.07:31:13.20#ibcon#about to write, iclass 21, count 0 2006.280.07:31:13.20#ibcon#wrote, iclass 21, count 0 2006.280.07:31:13.20#ibcon#about to read 3, iclass 21, count 0 2006.280.07:31:13.24#ibcon#read 3, iclass 21, count 0 2006.280.07:31:13.24#ibcon#about to read 4, iclass 21, count 0 2006.280.07:31:13.24#ibcon#read 4, iclass 21, count 0 2006.280.07:31:13.24#ibcon#about to read 5, iclass 21, count 0 2006.280.07:31:13.24#ibcon#read 5, iclass 21, count 0 2006.280.07:31:13.24#ibcon#about to read 6, iclass 21, count 0 2006.280.07:31:13.24#ibcon#read 6, iclass 21, count 0 2006.280.07:31:13.24#ibcon#end of sib2, iclass 21, count 0 2006.280.07:31:13.24#ibcon#*after write, iclass 21, count 0 2006.280.07:31:13.24#ibcon#*before return 0, iclass 21, count 0 2006.280.07:31:13.24#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:13.24#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:31:13.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:31:13.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:31:13.24$vc4f8/vb=6,4 2006.280.07:31:13.24#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:31:13.24#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:31:13.24#ibcon#ireg 11 cls_cnt 2 2006.280.07:31:13.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:13.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:13.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:13.30#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:31:13.30#ibcon#first serial, iclass 23, count 2 2006.280.07:31:13.30#ibcon#enter sib2, iclass 23, count 2 2006.280.07:31:13.30#ibcon#flushed, iclass 23, count 2 2006.280.07:31:13.30#ibcon#about to write, iclass 23, count 2 2006.280.07:31:13.30#ibcon#wrote, iclass 23, count 2 2006.280.07:31:13.30#ibcon#about to read 3, iclass 23, count 2 2006.280.07:31:13.32#ibcon#read 3, iclass 23, count 2 2006.280.07:31:13.32#ibcon#about to read 4, iclass 23, count 2 2006.280.07:31:13.32#ibcon#read 4, iclass 23, count 2 2006.280.07:31:13.32#ibcon#about to read 5, iclass 23, count 2 2006.280.07:31:13.32#ibcon#read 5, iclass 23, count 2 2006.280.07:31:13.32#ibcon#about to read 6, iclass 23, count 2 2006.280.07:31:13.32#ibcon#read 6, iclass 23, count 2 2006.280.07:31:13.32#ibcon#end of sib2, iclass 23, count 2 2006.280.07:31:13.32#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:31:13.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:31:13.32#ibcon#[27=AT06-04\r\n] 2006.280.07:31:13.32#ibcon#*before write, iclass 23, count 2 2006.280.07:31:13.32#ibcon#enter sib2, iclass 23, count 2 2006.280.07:31:13.32#ibcon#flushed, iclass 23, count 2 2006.280.07:31:13.32#ibcon#about to write, iclass 23, count 2 2006.280.07:31:13.32#ibcon#wrote, iclass 23, count 2 2006.280.07:31:13.32#ibcon#about to read 3, iclass 23, count 2 2006.280.07:31:13.35#ibcon#read 3, iclass 23, count 2 2006.280.07:31:13.35#ibcon#about to read 4, iclass 23, count 2 2006.280.07:31:13.35#ibcon#read 4, iclass 23, count 2 2006.280.07:31:13.35#ibcon#about to read 5, iclass 23, count 2 2006.280.07:31:13.35#ibcon#read 5, iclass 23, count 2 2006.280.07:31:13.35#ibcon#about to read 6, iclass 23, count 2 2006.280.07:31:13.35#ibcon#read 6, iclass 23, count 2 2006.280.07:31:13.35#ibcon#end of sib2, iclass 23, count 2 2006.280.07:31:13.35#ibcon#*after write, iclass 23, count 2 2006.280.07:31:13.35#ibcon#*before return 0, iclass 23, count 2 2006.280.07:31:13.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:13.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:31:13.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:31:13.35#ibcon#ireg 7 cls_cnt 0 2006.280.07:31:13.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:13.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:13.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:13.47#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:31:13.47#ibcon#first serial, iclass 23, count 0 2006.280.07:31:13.47#ibcon#enter sib2, iclass 23, count 0 2006.280.07:31:13.47#ibcon#flushed, iclass 23, count 0 2006.280.07:31:13.47#ibcon#about to write, iclass 23, count 0 2006.280.07:31:13.47#ibcon#wrote, iclass 23, count 0 2006.280.07:31:13.47#ibcon#about to read 3, iclass 23, count 0 2006.280.07:31:13.49#ibcon#read 3, iclass 23, count 0 2006.280.07:31:13.49#ibcon#about to read 4, iclass 23, count 0 2006.280.07:31:13.49#ibcon#read 4, iclass 23, count 0 2006.280.07:31:13.49#ibcon#about to read 5, iclass 23, count 0 2006.280.07:31:13.49#ibcon#read 5, iclass 23, count 0 2006.280.07:31:13.49#ibcon#about to read 6, iclass 23, count 0 2006.280.07:31:13.49#ibcon#read 6, iclass 23, count 0 2006.280.07:31:13.49#ibcon#end of sib2, iclass 23, count 0 2006.280.07:31:13.49#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:31:13.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:31:13.49#ibcon#[27=USB\r\n] 2006.280.07:31:13.49#ibcon#*before write, iclass 23, count 0 2006.280.07:31:13.49#ibcon#enter sib2, iclass 23, count 0 2006.280.07:31:13.49#ibcon#flushed, iclass 23, count 0 2006.280.07:31:13.49#ibcon#about to write, iclass 23, count 0 2006.280.07:31:13.49#ibcon#wrote, iclass 23, count 0 2006.280.07:31:13.49#ibcon#about to read 3, iclass 23, count 0 2006.280.07:31:13.52#ibcon#read 3, iclass 23, count 0 2006.280.07:31:13.52#ibcon#about to read 4, iclass 23, count 0 2006.280.07:31:13.52#ibcon#read 4, iclass 23, count 0 2006.280.07:31:13.52#ibcon#about to read 5, iclass 23, count 0 2006.280.07:31:13.52#ibcon#read 5, iclass 23, count 0 2006.280.07:31:13.52#ibcon#about to read 6, iclass 23, count 0 2006.280.07:31:13.52#ibcon#read 6, iclass 23, count 0 2006.280.07:31:13.52#ibcon#end of sib2, iclass 23, count 0 2006.280.07:31:13.52#ibcon#*after write, iclass 23, count 0 2006.280.07:31:13.52#ibcon#*before return 0, iclass 23, count 0 2006.280.07:31:13.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:13.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:31:13.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:31:13.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:31:13.52$vc4f8/vabw=wide 2006.280.07:31:13.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:31:13.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:31:13.52#ibcon#ireg 8 cls_cnt 0 2006.280.07:31:13.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:13.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:13.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:13.52#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:31:13.52#ibcon#first serial, iclass 25, count 0 2006.280.07:31:13.52#ibcon#enter sib2, iclass 25, count 0 2006.280.07:31:13.52#ibcon#flushed, iclass 25, count 0 2006.280.07:31:13.52#ibcon#about to write, iclass 25, count 0 2006.280.07:31:13.52#ibcon#wrote, iclass 25, count 0 2006.280.07:31:13.52#ibcon#about to read 3, iclass 25, count 0 2006.280.07:31:13.54#ibcon#read 3, iclass 25, count 0 2006.280.07:31:13.54#ibcon#about to read 4, iclass 25, count 0 2006.280.07:31:13.54#ibcon#read 4, iclass 25, count 0 2006.280.07:31:13.54#ibcon#about to read 5, iclass 25, count 0 2006.280.07:31:13.54#ibcon#read 5, iclass 25, count 0 2006.280.07:31:13.54#ibcon#about to read 6, iclass 25, count 0 2006.280.07:31:13.54#ibcon#read 6, iclass 25, count 0 2006.280.07:31:13.54#ibcon#end of sib2, iclass 25, count 0 2006.280.07:31:13.54#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:31:13.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:31:13.54#ibcon#[25=BW32\r\n] 2006.280.07:31:13.54#ibcon#*before write, iclass 25, count 0 2006.280.07:31:13.54#ibcon#enter sib2, iclass 25, count 0 2006.280.07:31:13.54#ibcon#flushed, iclass 25, count 0 2006.280.07:31:13.54#ibcon#about to write, iclass 25, count 0 2006.280.07:31:13.54#ibcon#wrote, iclass 25, count 0 2006.280.07:31:13.54#ibcon#about to read 3, iclass 25, count 0 2006.280.07:31:13.57#ibcon#read 3, iclass 25, count 0 2006.280.07:31:13.57#ibcon#about to read 4, iclass 25, count 0 2006.280.07:31:13.57#ibcon#read 4, iclass 25, count 0 2006.280.07:31:13.57#ibcon#about to read 5, iclass 25, count 0 2006.280.07:31:13.57#ibcon#read 5, iclass 25, count 0 2006.280.07:31:13.57#ibcon#about to read 6, iclass 25, count 0 2006.280.07:31:13.57#ibcon#read 6, iclass 25, count 0 2006.280.07:31:13.57#ibcon#end of sib2, iclass 25, count 0 2006.280.07:31:13.57#ibcon#*after write, iclass 25, count 0 2006.280.07:31:13.57#ibcon#*before return 0, iclass 25, count 0 2006.280.07:31:13.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:13.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:31:13.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:31:13.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:31:13.57$vc4f8/vbbw=wide 2006.280.07:31:13.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:31:13.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:31:13.57#ibcon#ireg 8 cls_cnt 0 2006.280.07:31:13.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:31:13.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:31:13.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:31:13.64#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:31:13.64#ibcon#first serial, iclass 27, count 0 2006.280.07:31:13.64#ibcon#enter sib2, iclass 27, count 0 2006.280.07:31:13.64#ibcon#flushed, iclass 27, count 0 2006.280.07:31:13.64#ibcon#about to write, iclass 27, count 0 2006.280.07:31:13.64#ibcon#wrote, iclass 27, count 0 2006.280.07:31:13.64#ibcon#about to read 3, iclass 27, count 0 2006.280.07:31:13.66#ibcon#read 3, iclass 27, count 0 2006.280.07:31:13.66#ibcon#about to read 4, iclass 27, count 0 2006.280.07:31:13.66#ibcon#read 4, iclass 27, count 0 2006.280.07:31:13.66#ibcon#about to read 5, iclass 27, count 0 2006.280.07:31:13.66#ibcon#read 5, iclass 27, count 0 2006.280.07:31:13.66#ibcon#about to read 6, iclass 27, count 0 2006.280.07:31:13.66#ibcon#read 6, iclass 27, count 0 2006.280.07:31:13.66#ibcon#end of sib2, iclass 27, count 0 2006.280.07:31:13.66#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:31:13.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:31:13.66#ibcon#[27=BW32\r\n] 2006.280.07:31:13.66#ibcon#*before write, iclass 27, count 0 2006.280.07:31:13.66#ibcon#enter sib2, iclass 27, count 0 2006.280.07:31:13.66#ibcon#flushed, iclass 27, count 0 2006.280.07:31:13.66#ibcon#about to write, iclass 27, count 0 2006.280.07:31:13.66#ibcon#wrote, iclass 27, count 0 2006.280.07:31:13.66#ibcon#about to read 3, iclass 27, count 0 2006.280.07:31:13.69#ibcon#read 3, iclass 27, count 0 2006.280.07:31:13.69#ibcon#about to read 4, iclass 27, count 0 2006.280.07:31:13.69#ibcon#read 4, iclass 27, count 0 2006.280.07:31:13.69#ibcon#about to read 5, iclass 27, count 0 2006.280.07:31:13.69#ibcon#read 5, iclass 27, count 0 2006.280.07:31:13.69#ibcon#about to read 6, iclass 27, count 0 2006.280.07:31:13.69#ibcon#read 6, iclass 27, count 0 2006.280.07:31:13.69#ibcon#end of sib2, iclass 27, count 0 2006.280.07:31:13.69#ibcon#*after write, iclass 27, count 0 2006.280.07:31:13.69#ibcon#*before return 0, iclass 27, count 0 2006.280.07:31:13.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:31:13.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:31:13.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:31:13.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:31:13.69$4f8m12a/ifd4f 2006.280.07:31:13.69$ifd4f/lo= 2006.280.07:31:13.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:31:13.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:31:13.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:31:13.70$ifd4f/patch= 2006.280.07:31:13.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:31:13.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:31:13.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:31:13.70$4f8m12a/"form=m,16.000,1:2 2006.280.07:31:13.70$4f8m12a/"tpicd 2006.280.07:31:13.70$4f8m12a/echo=off 2006.280.07:31:13.70$4f8m12a/xlog=off 2006.280.07:31:13.70:!2006.280.07:33:20 2006.280.07:31:36.14#trakl#Source acquired 2006.280.07:31:37.14#flagr#flagr/antenna,acquired 2006.280.07:33:20.00:preob 2006.280.07:33:20.14/onsource/TRACKING 2006.280.07:33:20.14:!2006.280.07:33:30 2006.280.07:33:30.00:data_valid=on 2006.280.07:33:30.00:midob 2006.280.07:33:31.14/onsource/TRACKING 2006.280.07:33:31.14/wx/22.11,986.6,57 2006.280.07:33:31.30/cable/+6.4800E-03 2006.280.07:33:32.39/va/01,07,usb,yes,37,39 2006.280.07:33:32.39/va/02,06,usb,yes,34,36 2006.280.07:33:32.39/va/03,06,usb,yes,33,32 2006.280.07:33:32.39/va/04,06,usb,yes,36,38 2006.280.07:33:32.39/va/05,07,usb,yes,33,34 2006.280.07:33:32.39/va/06,06,usb,yes,32,31 2006.280.07:33:32.39/va/07,06,usb,yes,32,32 2006.280.07:33:32.39/va/08,06,usb,yes,34,34 2006.280.07:33:32.62/valo/01,532.99,yes,locked 2006.280.07:33:32.62/valo/02,572.99,yes,locked 2006.280.07:33:32.62/valo/03,672.99,yes,locked 2006.280.07:33:32.62/valo/04,832.99,yes,locked 2006.280.07:33:32.62/valo/05,652.99,yes,locked 2006.280.07:33:32.62/valo/06,772.99,yes,locked 2006.280.07:33:32.62/valo/07,832.99,yes,locked 2006.280.07:33:32.62/valo/08,852.99,yes,locked 2006.280.07:33:33.71/vb/01,04,usb,yes,32,31 2006.280.07:33:33.71/vb/02,05,usb,yes,30,31 2006.280.07:33:33.71/vb/03,04,usb,yes,30,34 2006.280.07:33:33.71/vb/04,04,usb,yes,32,32 2006.280.07:33:33.71/vb/05,04,usb,yes,29,34 2006.280.07:33:33.71/vb/06,04,usb,yes,30,34 2006.280.07:33:33.71/vb/07,04,usb,yes,33,34 2006.280.07:33:33.71/vb/08,04,usb,yes,30,34 2006.280.07:33:33.95/vblo/01,632.99,yes,locked 2006.280.07:33:33.95/vblo/02,640.99,yes,locked 2006.280.07:33:33.95/vblo/03,656.99,yes,locked 2006.280.07:33:33.95/vblo/04,712.99,yes,locked 2006.280.07:33:33.95/vblo/05,744.99,yes,locked 2006.280.07:33:33.95/vblo/06,752.99,yes,locked 2006.280.07:33:33.95/vblo/07,734.99,yes,locked 2006.280.07:33:33.95/vblo/08,744.99,yes,locked 2006.280.07:33:34.10/vabw/8 2006.280.07:33:34.25/vbbw/8 2006.280.07:33:34.37/xfe/off,on,12.2 2006.280.07:33:34.74/ifatt/23,28,28,28 2006.280.07:33:35.08/fmout-gps/S +2.93E-07 2006.280.07:33:35.10:!2006.280.07:34:30 2006.280.07:34:30.01:data_valid=off 2006.280.07:34:30.01:postob 2006.280.07:34:30.23/cable/+6.4823E-03 2006.280.07:34:30.23/wx/22.06,986.7,57 2006.280.07:34:31.08/fmout-gps/S +2.93E-07 2006.280.07:34:31.08:scan_name=280-0735,k06280,60 2006.280.07:34:31.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.280.07:34:31.13#flagr#flagr/antenna,new-source 2006.280.07:34:32.13:checkk5 2006.280.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:34:33.38/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:34:33.76/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:34:34.16/chk_obsdata//k5ts1/T2800733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:34:34.53/chk_obsdata//k5ts2/T2800733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:34:34.91/chk_obsdata//k5ts3/T2800733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:34:35.37/chk_obsdata//k5ts4/T2800733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:34:36.17/k5log//k5ts1_log_newline 2006.280.07:34:36.86/k5log//k5ts2_log_newline 2006.280.07:34:37.69/k5log//k5ts3_log_newline 2006.280.07:34:38.39/k5log//k5ts4_log_newline 2006.280.07:34:38.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:34:38.42:4f8m12a=1 2006.280.07:34:38.42$4f8m12a/echo=on 2006.280.07:34:38.42$4f8m12a/pcalon 2006.280.07:34:38.42$pcalon/"no phase cal control is implemented here 2006.280.07:34:38.42$4f8m12a/"tpicd=stop 2006.280.07:34:38.42$4f8m12a/vc4f8 2006.280.07:34:38.42$vc4f8/valo=1,532.99 2006.280.07:34:38.42#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:34:38.42#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:34:38.42#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:38.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:38.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:38.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:38.42#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:34:38.42#ibcon#first serial, iclass 38, count 0 2006.280.07:34:38.42#ibcon#enter sib2, iclass 38, count 0 2006.280.07:34:38.42#ibcon#flushed, iclass 38, count 0 2006.280.07:34:38.42#ibcon#about to write, iclass 38, count 0 2006.280.07:34:38.42#ibcon#wrote, iclass 38, count 0 2006.280.07:34:38.42#ibcon#about to read 3, iclass 38, count 0 2006.280.07:34:38.44#ibcon#read 3, iclass 38, count 0 2006.280.07:34:38.44#ibcon#about to read 4, iclass 38, count 0 2006.280.07:34:38.44#ibcon#read 4, iclass 38, count 0 2006.280.07:34:38.44#ibcon#about to read 5, iclass 38, count 0 2006.280.07:34:38.44#ibcon#read 5, iclass 38, count 0 2006.280.07:34:38.44#ibcon#about to read 6, iclass 38, count 0 2006.280.07:34:38.44#ibcon#read 6, iclass 38, count 0 2006.280.07:34:38.44#ibcon#end of sib2, iclass 38, count 0 2006.280.07:34:38.44#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:34:38.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:34:38.44#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:34:38.44#ibcon#*before write, iclass 38, count 0 2006.280.07:34:38.44#ibcon#enter sib2, iclass 38, count 0 2006.280.07:34:38.44#ibcon#flushed, iclass 38, count 0 2006.280.07:34:38.44#ibcon#about to write, iclass 38, count 0 2006.280.07:34:38.44#ibcon#wrote, iclass 38, count 0 2006.280.07:34:38.44#ibcon#about to read 3, iclass 38, count 0 2006.280.07:34:38.49#ibcon#read 3, iclass 38, count 0 2006.280.07:34:38.49#ibcon#about to read 4, iclass 38, count 0 2006.280.07:34:38.49#ibcon#read 4, iclass 38, count 0 2006.280.07:34:38.49#ibcon#about to read 5, iclass 38, count 0 2006.280.07:34:38.49#ibcon#read 5, iclass 38, count 0 2006.280.07:34:38.49#ibcon#about to read 6, iclass 38, count 0 2006.280.07:34:38.49#ibcon#read 6, iclass 38, count 0 2006.280.07:34:38.49#ibcon#end of sib2, iclass 38, count 0 2006.280.07:34:38.49#ibcon#*after write, iclass 38, count 0 2006.280.07:34:38.49#ibcon#*before return 0, iclass 38, count 0 2006.280.07:34:38.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:38.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:38.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:34:38.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:34:38.49$vc4f8/va=1,7 2006.280.07:34:38.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:34:38.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:34:38.49#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:38.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:38.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:38.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:38.49#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:34:38.49#ibcon#first serial, iclass 40, count 2 2006.280.07:34:38.49#ibcon#enter sib2, iclass 40, count 2 2006.280.07:34:38.49#ibcon#flushed, iclass 40, count 2 2006.280.07:34:38.49#ibcon#about to write, iclass 40, count 2 2006.280.07:34:38.49#ibcon#wrote, iclass 40, count 2 2006.280.07:34:38.49#ibcon#about to read 3, iclass 40, count 2 2006.280.07:34:38.51#ibcon#read 3, iclass 40, count 2 2006.280.07:34:38.51#ibcon#about to read 4, iclass 40, count 2 2006.280.07:34:38.51#ibcon#read 4, iclass 40, count 2 2006.280.07:34:38.51#ibcon#about to read 5, iclass 40, count 2 2006.280.07:34:38.51#ibcon#read 5, iclass 40, count 2 2006.280.07:34:38.51#ibcon#about to read 6, iclass 40, count 2 2006.280.07:34:38.51#ibcon#read 6, iclass 40, count 2 2006.280.07:34:38.51#ibcon#end of sib2, iclass 40, count 2 2006.280.07:34:38.51#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:34:38.51#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:34:38.51#ibcon#[25=AT01-07\r\n] 2006.280.07:34:38.51#ibcon#*before write, iclass 40, count 2 2006.280.07:34:38.51#ibcon#enter sib2, iclass 40, count 2 2006.280.07:34:38.51#ibcon#flushed, iclass 40, count 2 2006.280.07:34:38.51#ibcon#about to write, iclass 40, count 2 2006.280.07:34:38.51#ibcon#wrote, iclass 40, count 2 2006.280.07:34:38.51#ibcon#about to read 3, iclass 40, count 2 2006.280.07:34:38.54#ibcon#read 3, iclass 40, count 2 2006.280.07:34:38.55#ibcon#about to read 4, iclass 40, count 2 2006.280.07:34:38.55#ibcon#read 4, iclass 40, count 2 2006.280.07:34:38.55#ibcon#about to read 5, iclass 40, count 2 2006.280.07:34:38.55#ibcon#read 5, iclass 40, count 2 2006.280.07:34:38.55#ibcon#about to read 6, iclass 40, count 2 2006.280.07:34:38.55#ibcon#read 6, iclass 40, count 2 2006.280.07:34:38.55#ibcon#end of sib2, iclass 40, count 2 2006.280.07:34:38.55#ibcon#*after write, iclass 40, count 2 2006.280.07:34:38.55#ibcon#*before return 0, iclass 40, count 2 2006.280.07:34:38.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:38.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:38.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:34:38.55#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:38.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:38.66#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:38.66#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:38.66#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:34:38.66#ibcon#first serial, iclass 40, count 0 2006.280.07:34:38.66#ibcon#enter sib2, iclass 40, count 0 2006.280.07:34:38.66#ibcon#flushed, iclass 40, count 0 2006.280.07:34:38.66#ibcon#about to write, iclass 40, count 0 2006.280.07:34:38.66#ibcon#wrote, iclass 40, count 0 2006.280.07:34:38.66#ibcon#about to read 3, iclass 40, count 0 2006.280.07:34:38.68#ibcon#read 3, iclass 40, count 0 2006.280.07:34:38.68#ibcon#about to read 4, iclass 40, count 0 2006.280.07:34:38.68#ibcon#read 4, iclass 40, count 0 2006.280.07:34:38.68#ibcon#about to read 5, iclass 40, count 0 2006.280.07:34:38.68#ibcon#read 5, iclass 40, count 0 2006.280.07:34:38.68#ibcon#about to read 6, iclass 40, count 0 2006.280.07:34:38.68#ibcon#read 6, iclass 40, count 0 2006.280.07:34:38.68#ibcon#end of sib2, iclass 40, count 0 2006.280.07:34:38.68#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:34:38.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:34:38.68#ibcon#[25=USB\r\n] 2006.280.07:34:38.68#ibcon#*before write, iclass 40, count 0 2006.280.07:34:38.68#ibcon#enter sib2, iclass 40, count 0 2006.280.07:34:38.68#ibcon#flushed, iclass 40, count 0 2006.280.07:34:38.68#ibcon#about to write, iclass 40, count 0 2006.280.07:34:38.68#ibcon#wrote, iclass 40, count 0 2006.280.07:34:38.68#ibcon#about to read 3, iclass 40, count 0 2006.280.07:34:38.71#ibcon#read 3, iclass 40, count 0 2006.280.07:34:38.71#ibcon#about to read 4, iclass 40, count 0 2006.280.07:34:38.71#ibcon#read 4, iclass 40, count 0 2006.280.07:34:38.71#ibcon#about to read 5, iclass 40, count 0 2006.280.07:34:38.71#ibcon#read 5, iclass 40, count 0 2006.280.07:34:38.71#ibcon#about to read 6, iclass 40, count 0 2006.280.07:34:38.71#ibcon#read 6, iclass 40, count 0 2006.280.07:34:38.71#ibcon#end of sib2, iclass 40, count 0 2006.280.07:34:38.71#ibcon#*after write, iclass 40, count 0 2006.280.07:34:38.71#ibcon#*before return 0, iclass 40, count 0 2006.280.07:34:38.71#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:38.71#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:38.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:34:38.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:34:38.71$vc4f8/valo=2,572.99 2006.280.07:34:38.71#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:34:38.71#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:34:38.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:38.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:38.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:38.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:38.71#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:34:38.71#ibcon#first serial, iclass 4, count 0 2006.280.07:34:38.71#ibcon#enter sib2, iclass 4, count 0 2006.280.07:34:38.71#ibcon#flushed, iclass 4, count 0 2006.280.07:34:38.71#ibcon#about to write, iclass 4, count 0 2006.280.07:34:38.71#ibcon#wrote, iclass 4, count 0 2006.280.07:34:38.71#ibcon#about to read 3, iclass 4, count 0 2006.280.07:34:38.73#ibcon#read 3, iclass 4, count 0 2006.280.07:34:38.73#ibcon#about to read 4, iclass 4, count 0 2006.280.07:34:38.73#ibcon#read 4, iclass 4, count 0 2006.280.07:34:38.73#ibcon#about to read 5, iclass 4, count 0 2006.280.07:34:38.73#ibcon#read 5, iclass 4, count 0 2006.280.07:34:38.73#ibcon#about to read 6, iclass 4, count 0 2006.280.07:34:38.73#ibcon#read 6, iclass 4, count 0 2006.280.07:34:38.73#ibcon#end of sib2, iclass 4, count 0 2006.280.07:34:38.73#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:34:38.73#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:34:38.73#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:34:38.73#ibcon#*before write, iclass 4, count 0 2006.280.07:34:38.73#ibcon#enter sib2, iclass 4, count 0 2006.280.07:34:38.73#ibcon#flushed, iclass 4, count 0 2006.280.07:34:38.73#ibcon#about to write, iclass 4, count 0 2006.280.07:34:38.73#ibcon#wrote, iclass 4, count 0 2006.280.07:34:38.73#ibcon#about to read 3, iclass 4, count 0 2006.280.07:34:38.77#ibcon#read 3, iclass 4, count 0 2006.280.07:34:38.77#ibcon#about to read 4, iclass 4, count 0 2006.280.07:34:38.77#ibcon#read 4, iclass 4, count 0 2006.280.07:34:38.77#ibcon#about to read 5, iclass 4, count 0 2006.280.07:34:38.77#ibcon#read 5, iclass 4, count 0 2006.280.07:34:38.77#ibcon#about to read 6, iclass 4, count 0 2006.280.07:34:38.77#ibcon#read 6, iclass 4, count 0 2006.280.07:34:38.77#ibcon#end of sib2, iclass 4, count 0 2006.280.07:34:38.77#ibcon#*after write, iclass 4, count 0 2006.280.07:34:38.77#ibcon#*before return 0, iclass 4, count 0 2006.280.07:34:38.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:38.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:38.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:34:38.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:34:38.77$vc4f8/va=2,6 2006.280.07:34:38.77#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:34:38.77#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:34:38.77#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:38.77#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:38.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:38.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:38.83#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:34:38.83#ibcon#first serial, iclass 6, count 2 2006.280.07:34:38.83#ibcon#enter sib2, iclass 6, count 2 2006.280.07:34:38.83#ibcon#flushed, iclass 6, count 2 2006.280.07:34:38.83#ibcon#about to write, iclass 6, count 2 2006.280.07:34:38.83#ibcon#wrote, iclass 6, count 2 2006.280.07:34:38.83#ibcon#about to read 3, iclass 6, count 2 2006.280.07:34:38.85#ibcon#read 3, iclass 6, count 2 2006.280.07:34:38.85#ibcon#about to read 4, iclass 6, count 2 2006.280.07:34:38.85#ibcon#read 4, iclass 6, count 2 2006.280.07:34:38.87#ibcon#about to read 5, iclass 6, count 2 2006.280.07:34:38.87#ibcon#read 5, iclass 6, count 2 2006.280.07:34:38.87#ibcon#about to read 6, iclass 6, count 2 2006.280.07:34:38.87#ibcon#read 6, iclass 6, count 2 2006.280.07:34:38.87#ibcon#end of sib2, iclass 6, count 2 2006.280.07:34:38.87#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:34:38.87#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:34:38.87#ibcon#[25=AT02-06\r\n] 2006.280.07:34:38.87#ibcon#*before write, iclass 6, count 2 2006.280.07:34:38.87#ibcon#enter sib2, iclass 6, count 2 2006.280.07:34:38.87#ibcon#flushed, iclass 6, count 2 2006.280.07:34:38.87#ibcon#about to write, iclass 6, count 2 2006.280.07:34:38.87#ibcon#wrote, iclass 6, count 2 2006.280.07:34:38.87#ibcon#about to read 3, iclass 6, count 2 2006.280.07:34:38.90#ibcon#read 3, iclass 6, count 2 2006.280.07:34:38.90#ibcon#about to read 4, iclass 6, count 2 2006.280.07:34:38.90#ibcon#read 4, iclass 6, count 2 2006.280.07:34:38.90#ibcon#about to read 5, iclass 6, count 2 2006.280.07:34:38.90#ibcon#read 5, iclass 6, count 2 2006.280.07:34:38.90#ibcon#about to read 6, iclass 6, count 2 2006.280.07:34:38.90#ibcon#read 6, iclass 6, count 2 2006.280.07:34:38.90#ibcon#end of sib2, iclass 6, count 2 2006.280.07:34:38.90#ibcon#*after write, iclass 6, count 2 2006.280.07:34:38.90#ibcon#*before return 0, iclass 6, count 2 2006.280.07:34:38.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:38.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:38.90#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:34:38.90#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:38.90#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:39.02#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:39.02#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:39.02#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:34:39.02#ibcon#first serial, iclass 6, count 0 2006.280.07:34:39.02#ibcon#enter sib2, iclass 6, count 0 2006.280.07:34:39.02#ibcon#flushed, iclass 6, count 0 2006.280.07:34:39.02#ibcon#about to write, iclass 6, count 0 2006.280.07:34:39.02#ibcon#wrote, iclass 6, count 0 2006.280.07:34:39.02#ibcon#about to read 3, iclass 6, count 0 2006.280.07:34:39.04#ibcon#read 3, iclass 6, count 0 2006.280.07:34:39.04#ibcon#about to read 4, iclass 6, count 0 2006.280.07:34:39.04#ibcon#read 4, iclass 6, count 0 2006.280.07:34:39.04#ibcon#about to read 5, iclass 6, count 0 2006.280.07:34:39.04#ibcon#read 5, iclass 6, count 0 2006.280.07:34:39.04#ibcon#about to read 6, iclass 6, count 0 2006.280.07:34:39.04#ibcon#read 6, iclass 6, count 0 2006.280.07:34:39.04#ibcon#end of sib2, iclass 6, count 0 2006.280.07:34:39.04#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:34:39.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:34:39.04#ibcon#[25=USB\r\n] 2006.280.07:34:39.04#ibcon#*before write, iclass 6, count 0 2006.280.07:34:39.04#ibcon#enter sib2, iclass 6, count 0 2006.280.07:34:39.04#ibcon#flushed, iclass 6, count 0 2006.280.07:34:39.04#ibcon#about to write, iclass 6, count 0 2006.280.07:34:39.04#ibcon#wrote, iclass 6, count 0 2006.280.07:34:39.04#ibcon#about to read 3, iclass 6, count 0 2006.280.07:34:39.07#ibcon#read 3, iclass 6, count 0 2006.280.07:34:39.07#ibcon#about to read 4, iclass 6, count 0 2006.280.07:34:39.07#ibcon#read 4, iclass 6, count 0 2006.280.07:34:39.07#ibcon#about to read 5, iclass 6, count 0 2006.280.07:34:39.07#ibcon#read 5, iclass 6, count 0 2006.280.07:34:39.07#ibcon#about to read 6, iclass 6, count 0 2006.280.07:34:39.07#ibcon#read 6, iclass 6, count 0 2006.280.07:34:39.07#ibcon#end of sib2, iclass 6, count 0 2006.280.07:34:39.07#ibcon#*after write, iclass 6, count 0 2006.280.07:34:39.07#ibcon#*before return 0, iclass 6, count 0 2006.280.07:34:39.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:39.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:39.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:34:39.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:34:39.07$vc4f8/valo=3,672.99 2006.280.07:34:39.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:34:39.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:34:39.07#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:39.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:39.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:39.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:39.07#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:34:39.07#ibcon#first serial, iclass 10, count 0 2006.280.07:34:39.07#ibcon#enter sib2, iclass 10, count 0 2006.280.07:34:39.07#ibcon#flushed, iclass 10, count 0 2006.280.07:34:39.07#ibcon#about to write, iclass 10, count 0 2006.280.07:34:39.07#ibcon#wrote, iclass 10, count 0 2006.280.07:34:39.07#ibcon#about to read 3, iclass 10, count 0 2006.280.07:34:39.09#ibcon#read 3, iclass 10, count 0 2006.280.07:34:39.09#ibcon#about to read 4, iclass 10, count 0 2006.280.07:34:39.09#ibcon#read 4, iclass 10, count 0 2006.280.07:34:39.09#ibcon#about to read 5, iclass 10, count 0 2006.280.07:34:39.09#ibcon#read 5, iclass 10, count 0 2006.280.07:34:39.09#ibcon#about to read 6, iclass 10, count 0 2006.280.07:34:39.09#ibcon#read 6, iclass 10, count 0 2006.280.07:34:39.09#ibcon#end of sib2, iclass 10, count 0 2006.280.07:34:39.09#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:34:39.09#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:34:39.09#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:34:39.09#ibcon#*before write, iclass 10, count 0 2006.280.07:34:39.09#ibcon#enter sib2, iclass 10, count 0 2006.280.07:34:39.09#ibcon#flushed, iclass 10, count 0 2006.280.07:34:39.09#ibcon#about to write, iclass 10, count 0 2006.280.07:34:39.09#ibcon#wrote, iclass 10, count 0 2006.280.07:34:39.09#ibcon#about to read 3, iclass 10, count 0 2006.280.07:34:39.13#ibcon#read 3, iclass 10, count 0 2006.280.07:34:39.13#ibcon#about to read 4, iclass 10, count 0 2006.280.07:34:39.13#ibcon#read 4, iclass 10, count 0 2006.280.07:34:39.13#ibcon#about to read 5, iclass 10, count 0 2006.280.07:34:39.13#ibcon#read 5, iclass 10, count 0 2006.280.07:34:39.13#ibcon#about to read 6, iclass 10, count 0 2006.280.07:34:39.13#ibcon#read 6, iclass 10, count 0 2006.280.07:34:39.13#ibcon#end of sib2, iclass 10, count 0 2006.280.07:34:39.13#ibcon#*after write, iclass 10, count 0 2006.280.07:34:39.13#ibcon#*before return 0, iclass 10, count 0 2006.280.07:34:39.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:39.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:39.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:34:39.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:34:39.13$vc4f8/va=3,6 2006.280.07:34:39.13#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:34:39.13#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:34:39.13#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:39.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:39.19#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:39.19#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:39.19#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:34:39.19#ibcon#first serial, iclass 12, count 2 2006.280.07:34:39.19#ibcon#enter sib2, iclass 12, count 2 2006.280.07:34:39.19#ibcon#flushed, iclass 12, count 2 2006.280.07:34:39.19#ibcon#about to write, iclass 12, count 2 2006.280.07:34:39.19#ibcon#wrote, iclass 12, count 2 2006.280.07:34:39.19#ibcon#about to read 3, iclass 12, count 2 2006.280.07:34:39.21#ibcon#read 3, iclass 12, count 2 2006.280.07:34:39.21#ibcon#about to read 4, iclass 12, count 2 2006.280.07:34:39.21#ibcon#read 4, iclass 12, count 2 2006.280.07:34:39.21#ibcon#about to read 5, iclass 12, count 2 2006.280.07:34:39.21#ibcon#read 5, iclass 12, count 2 2006.280.07:34:39.21#ibcon#about to read 6, iclass 12, count 2 2006.280.07:34:39.21#ibcon#read 6, iclass 12, count 2 2006.280.07:34:39.21#ibcon#end of sib2, iclass 12, count 2 2006.280.07:34:39.21#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:34:39.21#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:34:39.21#ibcon#[25=AT03-06\r\n] 2006.280.07:34:39.21#ibcon#*before write, iclass 12, count 2 2006.280.07:34:39.21#ibcon#enter sib2, iclass 12, count 2 2006.280.07:34:39.21#ibcon#flushed, iclass 12, count 2 2006.280.07:34:39.21#ibcon#about to write, iclass 12, count 2 2006.280.07:34:39.21#ibcon#wrote, iclass 12, count 2 2006.280.07:34:39.21#ibcon#about to read 3, iclass 12, count 2 2006.280.07:34:39.24#ibcon#read 3, iclass 12, count 2 2006.280.07:34:39.24#ibcon#about to read 4, iclass 12, count 2 2006.280.07:34:39.24#ibcon#read 4, iclass 12, count 2 2006.280.07:34:39.24#ibcon#about to read 5, iclass 12, count 2 2006.280.07:34:39.24#ibcon#read 5, iclass 12, count 2 2006.280.07:34:39.24#ibcon#about to read 6, iclass 12, count 2 2006.280.07:34:39.24#ibcon#read 6, iclass 12, count 2 2006.280.07:34:39.24#ibcon#end of sib2, iclass 12, count 2 2006.280.07:34:39.24#ibcon#*after write, iclass 12, count 2 2006.280.07:34:39.24#ibcon#*before return 0, iclass 12, count 2 2006.280.07:34:39.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:39.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:39.24#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:34:39.24#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:39.24#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:39.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:39.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:39.36#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:34:39.36#ibcon#first serial, iclass 12, count 0 2006.280.07:34:39.36#ibcon#enter sib2, iclass 12, count 0 2006.280.07:34:39.36#ibcon#flushed, iclass 12, count 0 2006.280.07:34:39.36#ibcon#about to write, iclass 12, count 0 2006.280.07:34:39.36#ibcon#wrote, iclass 12, count 0 2006.280.07:34:39.36#ibcon#about to read 3, iclass 12, count 0 2006.280.07:34:39.38#ibcon#read 3, iclass 12, count 0 2006.280.07:34:39.38#ibcon#about to read 4, iclass 12, count 0 2006.280.07:34:39.38#ibcon#read 4, iclass 12, count 0 2006.280.07:34:39.38#ibcon#about to read 5, iclass 12, count 0 2006.280.07:34:39.38#ibcon#read 5, iclass 12, count 0 2006.280.07:34:39.38#ibcon#about to read 6, iclass 12, count 0 2006.280.07:34:39.38#ibcon#read 6, iclass 12, count 0 2006.280.07:34:39.38#ibcon#end of sib2, iclass 12, count 0 2006.280.07:34:39.38#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:34:39.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:34:39.38#ibcon#[25=USB\r\n] 2006.280.07:34:39.38#ibcon#*before write, iclass 12, count 0 2006.280.07:34:39.38#ibcon#enter sib2, iclass 12, count 0 2006.280.07:34:39.38#ibcon#flushed, iclass 12, count 0 2006.280.07:34:39.38#ibcon#about to write, iclass 12, count 0 2006.280.07:34:39.38#ibcon#wrote, iclass 12, count 0 2006.280.07:34:39.38#ibcon#about to read 3, iclass 12, count 0 2006.280.07:34:39.41#ibcon#read 3, iclass 12, count 0 2006.280.07:34:39.41#ibcon#about to read 4, iclass 12, count 0 2006.280.07:34:39.41#ibcon#read 4, iclass 12, count 0 2006.280.07:34:39.41#ibcon#about to read 5, iclass 12, count 0 2006.280.07:34:39.41#ibcon#read 5, iclass 12, count 0 2006.280.07:34:39.41#ibcon#about to read 6, iclass 12, count 0 2006.280.07:34:39.41#ibcon#read 6, iclass 12, count 0 2006.280.07:34:39.41#ibcon#end of sib2, iclass 12, count 0 2006.280.07:34:39.41#ibcon#*after write, iclass 12, count 0 2006.280.07:34:39.41#ibcon#*before return 0, iclass 12, count 0 2006.280.07:34:39.41#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:39.41#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:39.41#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:34:39.41#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:34:39.41$vc4f8/valo=4,832.99 2006.280.07:34:39.41#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:34:39.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:34:39.41#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:39.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:39.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:39.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:39.41#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:34:39.41#ibcon#first serial, iclass 14, count 0 2006.280.07:34:39.41#ibcon#enter sib2, iclass 14, count 0 2006.280.07:34:39.41#ibcon#flushed, iclass 14, count 0 2006.280.07:34:39.41#ibcon#about to write, iclass 14, count 0 2006.280.07:34:39.41#ibcon#wrote, iclass 14, count 0 2006.280.07:34:39.41#ibcon#about to read 3, iclass 14, count 0 2006.280.07:34:39.43#ibcon#read 3, iclass 14, count 0 2006.280.07:34:39.43#ibcon#about to read 4, iclass 14, count 0 2006.280.07:34:39.43#ibcon#read 4, iclass 14, count 0 2006.280.07:34:39.43#ibcon#about to read 5, iclass 14, count 0 2006.280.07:34:39.43#ibcon#read 5, iclass 14, count 0 2006.280.07:34:39.43#ibcon#about to read 6, iclass 14, count 0 2006.280.07:34:39.43#ibcon#read 6, iclass 14, count 0 2006.280.07:34:39.43#ibcon#end of sib2, iclass 14, count 0 2006.280.07:34:39.43#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:34:39.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:34:39.43#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:34:39.43#ibcon#*before write, iclass 14, count 0 2006.280.07:34:39.43#ibcon#enter sib2, iclass 14, count 0 2006.280.07:34:39.43#ibcon#flushed, iclass 14, count 0 2006.280.07:34:39.43#ibcon#about to write, iclass 14, count 0 2006.280.07:34:39.43#ibcon#wrote, iclass 14, count 0 2006.280.07:34:39.43#ibcon#about to read 3, iclass 14, count 0 2006.280.07:34:39.47#ibcon#read 3, iclass 14, count 0 2006.280.07:34:39.47#ibcon#about to read 4, iclass 14, count 0 2006.280.07:34:39.47#ibcon#read 4, iclass 14, count 0 2006.280.07:34:39.47#ibcon#about to read 5, iclass 14, count 0 2006.280.07:34:39.47#ibcon#read 5, iclass 14, count 0 2006.280.07:34:39.47#ibcon#about to read 6, iclass 14, count 0 2006.280.07:34:39.47#ibcon#read 6, iclass 14, count 0 2006.280.07:34:39.47#ibcon#end of sib2, iclass 14, count 0 2006.280.07:34:39.47#ibcon#*after write, iclass 14, count 0 2006.280.07:34:39.47#ibcon#*before return 0, iclass 14, count 0 2006.280.07:34:39.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:39.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:39.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:34:39.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:34:39.47$vc4f8/va=4,6 2006.280.07:34:39.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:34:39.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:34:39.48#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:39.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:39.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:39.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:39.53#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:34:39.53#ibcon#first serial, iclass 16, count 2 2006.280.07:34:39.53#ibcon#enter sib2, iclass 16, count 2 2006.280.07:34:39.53#ibcon#flushed, iclass 16, count 2 2006.280.07:34:39.53#ibcon#about to write, iclass 16, count 2 2006.280.07:34:39.53#ibcon#wrote, iclass 16, count 2 2006.280.07:34:39.53#ibcon#about to read 3, iclass 16, count 2 2006.280.07:34:39.55#ibcon#read 3, iclass 16, count 2 2006.280.07:34:39.55#ibcon#about to read 4, iclass 16, count 2 2006.280.07:34:39.55#ibcon#read 4, iclass 16, count 2 2006.280.07:34:39.55#ibcon#about to read 5, iclass 16, count 2 2006.280.07:34:39.55#ibcon#read 5, iclass 16, count 2 2006.280.07:34:39.55#ibcon#about to read 6, iclass 16, count 2 2006.280.07:34:39.55#ibcon#read 6, iclass 16, count 2 2006.280.07:34:39.55#ibcon#end of sib2, iclass 16, count 2 2006.280.07:34:39.55#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:34:39.55#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:34:39.55#ibcon#[25=AT04-06\r\n] 2006.280.07:34:39.55#ibcon#*before write, iclass 16, count 2 2006.280.07:34:39.55#ibcon#enter sib2, iclass 16, count 2 2006.280.07:34:39.55#ibcon#flushed, iclass 16, count 2 2006.280.07:34:39.55#ibcon#about to write, iclass 16, count 2 2006.280.07:34:39.55#ibcon#wrote, iclass 16, count 2 2006.280.07:34:39.55#ibcon#about to read 3, iclass 16, count 2 2006.280.07:34:39.58#ibcon#read 3, iclass 16, count 2 2006.280.07:34:39.58#ibcon#about to read 4, iclass 16, count 2 2006.280.07:34:39.58#ibcon#read 4, iclass 16, count 2 2006.280.07:34:39.58#ibcon#about to read 5, iclass 16, count 2 2006.280.07:34:39.58#ibcon#read 5, iclass 16, count 2 2006.280.07:34:39.58#ibcon#about to read 6, iclass 16, count 2 2006.280.07:34:39.58#ibcon#read 6, iclass 16, count 2 2006.280.07:34:39.58#ibcon#end of sib2, iclass 16, count 2 2006.280.07:34:39.58#ibcon#*after write, iclass 16, count 2 2006.280.07:34:39.58#ibcon#*before return 0, iclass 16, count 2 2006.280.07:34:39.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:39.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:39.58#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:34:39.58#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:39.58#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:39.70#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:39.70#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:39.70#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:34:39.70#ibcon#first serial, iclass 16, count 0 2006.280.07:34:39.70#ibcon#enter sib2, iclass 16, count 0 2006.280.07:34:39.70#ibcon#flushed, iclass 16, count 0 2006.280.07:34:39.70#ibcon#about to write, iclass 16, count 0 2006.280.07:34:39.70#ibcon#wrote, iclass 16, count 0 2006.280.07:34:39.70#ibcon#about to read 3, iclass 16, count 0 2006.280.07:34:39.72#ibcon#read 3, iclass 16, count 0 2006.280.07:34:39.72#ibcon#about to read 4, iclass 16, count 0 2006.280.07:34:39.72#ibcon#read 4, iclass 16, count 0 2006.280.07:34:39.72#ibcon#about to read 5, iclass 16, count 0 2006.280.07:34:39.72#ibcon#read 5, iclass 16, count 0 2006.280.07:34:39.72#ibcon#about to read 6, iclass 16, count 0 2006.280.07:34:39.72#ibcon#read 6, iclass 16, count 0 2006.280.07:34:39.72#ibcon#end of sib2, iclass 16, count 0 2006.280.07:34:39.72#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:34:39.72#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:34:39.72#ibcon#[25=USB\r\n] 2006.280.07:34:39.72#ibcon#*before write, iclass 16, count 0 2006.280.07:34:39.72#ibcon#enter sib2, iclass 16, count 0 2006.280.07:34:39.72#ibcon#flushed, iclass 16, count 0 2006.280.07:34:39.72#ibcon#about to write, iclass 16, count 0 2006.280.07:34:39.72#ibcon#wrote, iclass 16, count 0 2006.280.07:34:39.72#ibcon#about to read 3, iclass 16, count 0 2006.280.07:34:39.75#ibcon#read 3, iclass 16, count 0 2006.280.07:34:39.75#ibcon#about to read 4, iclass 16, count 0 2006.280.07:34:39.75#ibcon#read 4, iclass 16, count 0 2006.280.07:34:39.75#ibcon#about to read 5, iclass 16, count 0 2006.280.07:34:39.75#ibcon#read 5, iclass 16, count 0 2006.280.07:34:39.75#ibcon#about to read 6, iclass 16, count 0 2006.280.07:34:39.75#ibcon#read 6, iclass 16, count 0 2006.280.07:34:39.75#ibcon#end of sib2, iclass 16, count 0 2006.280.07:34:39.75#ibcon#*after write, iclass 16, count 0 2006.280.07:34:39.75#ibcon#*before return 0, iclass 16, count 0 2006.280.07:34:39.75#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:39.75#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:39.75#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:34:39.75#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:34:39.75$vc4f8/valo=5,652.99 2006.280.07:34:39.75#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:34:39.75#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:34:39.75#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:39.75#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:39.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:39.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:39.75#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:34:39.75#ibcon#first serial, iclass 18, count 0 2006.280.07:34:39.75#ibcon#enter sib2, iclass 18, count 0 2006.280.07:34:39.75#ibcon#flushed, iclass 18, count 0 2006.280.07:34:39.75#ibcon#about to write, iclass 18, count 0 2006.280.07:34:39.75#ibcon#wrote, iclass 18, count 0 2006.280.07:34:39.75#ibcon#about to read 3, iclass 18, count 0 2006.280.07:34:39.77#ibcon#read 3, iclass 18, count 0 2006.280.07:34:39.77#ibcon#about to read 4, iclass 18, count 0 2006.280.07:34:39.77#ibcon#read 4, iclass 18, count 0 2006.280.07:34:39.77#ibcon#about to read 5, iclass 18, count 0 2006.280.07:34:39.77#ibcon#read 5, iclass 18, count 0 2006.280.07:34:39.77#ibcon#about to read 6, iclass 18, count 0 2006.280.07:34:39.77#ibcon#read 6, iclass 18, count 0 2006.280.07:34:39.77#ibcon#end of sib2, iclass 18, count 0 2006.280.07:34:39.77#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:34:39.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:34:39.77#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:34:39.77#ibcon#*before write, iclass 18, count 0 2006.280.07:34:39.77#ibcon#enter sib2, iclass 18, count 0 2006.280.07:34:39.77#ibcon#flushed, iclass 18, count 0 2006.280.07:34:39.77#ibcon#about to write, iclass 18, count 0 2006.280.07:34:39.77#ibcon#wrote, iclass 18, count 0 2006.280.07:34:39.77#ibcon#about to read 3, iclass 18, count 0 2006.280.07:34:39.81#ibcon#read 3, iclass 18, count 0 2006.280.07:34:39.81#ibcon#about to read 4, iclass 18, count 0 2006.280.07:34:39.81#ibcon#read 4, iclass 18, count 0 2006.280.07:34:39.81#ibcon#about to read 5, iclass 18, count 0 2006.280.07:34:39.81#ibcon#read 5, iclass 18, count 0 2006.280.07:34:39.81#ibcon#about to read 6, iclass 18, count 0 2006.280.07:34:39.81#ibcon#read 6, iclass 18, count 0 2006.280.07:34:39.81#ibcon#end of sib2, iclass 18, count 0 2006.280.07:34:39.81#ibcon#*after write, iclass 18, count 0 2006.280.07:34:39.81#ibcon#*before return 0, iclass 18, count 0 2006.280.07:34:39.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:39.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:39.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:34:39.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:34:39.81$vc4f8/va=5,7 2006.280.07:34:39.81#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:34:39.81#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:34:39.81#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:39.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:39.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:39.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:39.87#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:34:39.87#ibcon#first serial, iclass 20, count 2 2006.280.07:34:39.87#ibcon#enter sib2, iclass 20, count 2 2006.280.07:34:39.87#ibcon#flushed, iclass 20, count 2 2006.280.07:34:39.87#ibcon#about to write, iclass 20, count 2 2006.280.07:34:39.87#ibcon#wrote, iclass 20, count 2 2006.280.07:34:39.87#ibcon#about to read 3, iclass 20, count 2 2006.280.07:34:39.89#ibcon#read 3, iclass 20, count 2 2006.280.07:34:39.89#ibcon#about to read 4, iclass 20, count 2 2006.280.07:34:39.89#ibcon#read 4, iclass 20, count 2 2006.280.07:34:39.89#ibcon#about to read 5, iclass 20, count 2 2006.280.07:34:39.89#ibcon#read 5, iclass 20, count 2 2006.280.07:34:39.89#ibcon#about to read 6, iclass 20, count 2 2006.280.07:34:39.89#ibcon#read 6, iclass 20, count 2 2006.280.07:34:39.89#ibcon#end of sib2, iclass 20, count 2 2006.280.07:34:39.90#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:34:39.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:34:39.90#ibcon#[25=AT05-07\r\n] 2006.280.07:34:39.90#ibcon#*before write, iclass 20, count 2 2006.280.07:34:39.90#ibcon#enter sib2, iclass 20, count 2 2006.280.07:34:39.90#ibcon#flushed, iclass 20, count 2 2006.280.07:34:39.90#ibcon#about to write, iclass 20, count 2 2006.280.07:34:39.90#ibcon#wrote, iclass 20, count 2 2006.280.07:34:39.90#ibcon#about to read 3, iclass 20, count 2 2006.280.07:34:39.94#ibcon#read 3, iclass 20, count 2 2006.280.07:34:39.94#ibcon#about to read 4, iclass 20, count 2 2006.280.07:34:39.94#ibcon#read 4, iclass 20, count 2 2006.280.07:34:39.94#ibcon#about to read 5, iclass 20, count 2 2006.280.07:34:39.94#ibcon#read 5, iclass 20, count 2 2006.280.07:34:39.94#ibcon#about to read 6, iclass 20, count 2 2006.280.07:34:39.94#ibcon#read 6, iclass 20, count 2 2006.280.07:34:39.94#ibcon#end of sib2, iclass 20, count 2 2006.280.07:34:39.94#ibcon#*after write, iclass 20, count 2 2006.280.07:34:39.94#ibcon#*before return 0, iclass 20, count 2 2006.280.07:34:39.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:39.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:39.94#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:34:39.94#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:39.94#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:39.96#abcon#<5=/15 2.3 5.3 22.05 58 986.6\r\n> 2006.280.07:34:39.98#abcon#{5=INTERFACE CLEAR} 2006.280.07:34:40.04#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:34:40.06#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:40.06#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:40.06#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:34:40.06#ibcon#first serial, iclass 20, count 0 2006.280.07:34:40.06#ibcon#enter sib2, iclass 20, count 0 2006.280.07:34:40.06#ibcon#flushed, iclass 20, count 0 2006.280.07:34:40.06#ibcon#about to write, iclass 20, count 0 2006.280.07:34:40.06#ibcon#wrote, iclass 20, count 0 2006.280.07:34:40.06#ibcon#about to read 3, iclass 20, count 0 2006.280.07:34:40.08#ibcon#read 3, iclass 20, count 0 2006.280.07:34:40.08#ibcon#about to read 4, iclass 20, count 0 2006.280.07:34:40.08#ibcon#read 4, iclass 20, count 0 2006.280.07:34:40.08#ibcon#about to read 5, iclass 20, count 0 2006.280.07:34:40.08#ibcon#read 5, iclass 20, count 0 2006.280.07:34:40.08#ibcon#about to read 6, iclass 20, count 0 2006.280.07:34:40.08#ibcon#read 6, iclass 20, count 0 2006.280.07:34:40.08#ibcon#end of sib2, iclass 20, count 0 2006.280.07:34:40.08#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:34:40.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:34:40.08#ibcon#[25=USB\r\n] 2006.280.07:34:40.08#ibcon#*before write, iclass 20, count 0 2006.280.07:34:40.08#ibcon#enter sib2, iclass 20, count 0 2006.280.07:34:40.08#ibcon#flushed, iclass 20, count 0 2006.280.07:34:40.08#ibcon#about to write, iclass 20, count 0 2006.280.07:34:40.08#ibcon#wrote, iclass 20, count 0 2006.280.07:34:40.08#ibcon#about to read 3, iclass 20, count 0 2006.280.07:34:40.11#ibcon#read 3, iclass 20, count 0 2006.280.07:34:40.11#ibcon#about to read 4, iclass 20, count 0 2006.280.07:34:40.11#ibcon#read 4, iclass 20, count 0 2006.280.07:34:40.11#ibcon#about to read 5, iclass 20, count 0 2006.280.07:34:40.11#ibcon#read 5, iclass 20, count 0 2006.280.07:34:40.11#ibcon#about to read 6, iclass 20, count 0 2006.280.07:34:40.11#ibcon#read 6, iclass 20, count 0 2006.280.07:34:40.11#ibcon#end of sib2, iclass 20, count 0 2006.280.07:34:40.11#ibcon#*after write, iclass 20, count 0 2006.280.07:34:40.11#ibcon#*before return 0, iclass 20, count 0 2006.280.07:34:40.11#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:40.11#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:40.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:34:40.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:34:40.11$vc4f8/valo=6,772.99 2006.280.07:34:40.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:34:40.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:34:40.11#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:40.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:40.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:40.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:40.11#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:34:40.11#ibcon#first serial, iclass 26, count 0 2006.280.07:34:40.11#ibcon#enter sib2, iclass 26, count 0 2006.280.07:34:40.11#ibcon#flushed, iclass 26, count 0 2006.280.07:34:40.11#ibcon#about to write, iclass 26, count 0 2006.280.07:34:40.11#ibcon#wrote, iclass 26, count 0 2006.280.07:34:40.11#ibcon#about to read 3, iclass 26, count 0 2006.280.07:34:40.13#ibcon#read 3, iclass 26, count 0 2006.280.07:34:40.13#ibcon#about to read 4, iclass 26, count 0 2006.280.07:34:40.13#ibcon#read 4, iclass 26, count 0 2006.280.07:34:40.13#ibcon#about to read 5, iclass 26, count 0 2006.280.07:34:40.13#ibcon#read 5, iclass 26, count 0 2006.280.07:34:40.13#ibcon#about to read 6, iclass 26, count 0 2006.280.07:34:40.13#ibcon#read 6, iclass 26, count 0 2006.280.07:34:40.13#ibcon#end of sib2, iclass 26, count 0 2006.280.07:34:40.13#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:34:40.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:34:40.13#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:34:40.13#ibcon#*before write, iclass 26, count 0 2006.280.07:34:40.13#ibcon#enter sib2, iclass 26, count 0 2006.280.07:34:40.13#ibcon#flushed, iclass 26, count 0 2006.280.07:34:40.13#ibcon#about to write, iclass 26, count 0 2006.280.07:34:40.13#ibcon#wrote, iclass 26, count 0 2006.280.07:34:40.13#ibcon#about to read 3, iclass 26, count 0 2006.280.07:34:40.17#ibcon#read 3, iclass 26, count 0 2006.280.07:34:40.17#ibcon#about to read 4, iclass 26, count 0 2006.280.07:34:40.17#ibcon#read 4, iclass 26, count 0 2006.280.07:34:40.17#ibcon#about to read 5, iclass 26, count 0 2006.280.07:34:40.17#ibcon#read 5, iclass 26, count 0 2006.280.07:34:40.17#ibcon#about to read 6, iclass 26, count 0 2006.280.07:34:40.17#ibcon#read 6, iclass 26, count 0 2006.280.07:34:40.17#ibcon#end of sib2, iclass 26, count 0 2006.280.07:34:40.17#ibcon#*after write, iclass 26, count 0 2006.280.07:34:40.17#ibcon#*before return 0, iclass 26, count 0 2006.280.07:34:40.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:40.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:40.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:34:40.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:34:40.17$vc4f8/va=6,6 2006.280.07:34:40.17#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:34:40.17#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:34:40.17#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:40.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:40.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:40.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:40.23#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:34:40.23#ibcon#first serial, iclass 28, count 2 2006.280.07:34:40.23#ibcon#enter sib2, iclass 28, count 2 2006.280.07:34:40.23#ibcon#flushed, iclass 28, count 2 2006.280.07:34:40.23#ibcon#about to write, iclass 28, count 2 2006.280.07:34:40.23#ibcon#wrote, iclass 28, count 2 2006.280.07:34:40.23#ibcon#about to read 3, iclass 28, count 2 2006.280.07:34:40.25#ibcon#read 3, iclass 28, count 2 2006.280.07:34:40.25#ibcon#about to read 4, iclass 28, count 2 2006.280.07:34:40.25#ibcon#read 4, iclass 28, count 2 2006.280.07:34:40.25#ibcon#about to read 5, iclass 28, count 2 2006.280.07:34:40.25#ibcon#read 5, iclass 28, count 2 2006.280.07:34:40.25#ibcon#about to read 6, iclass 28, count 2 2006.280.07:34:40.25#ibcon#read 6, iclass 28, count 2 2006.280.07:34:40.25#ibcon#end of sib2, iclass 28, count 2 2006.280.07:34:40.25#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:34:40.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:34:40.25#ibcon#[25=AT06-06\r\n] 2006.280.07:34:40.25#ibcon#*before write, iclass 28, count 2 2006.280.07:34:40.25#ibcon#enter sib2, iclass 28, count 2 2006.280.07:34:40.25#ibcon#flushed, iclass 28, count 2 2006.280.07:34:40.25#ibcon#about to write, iclass 28, count 2 2006.280.07:34:40.25#ibcon#wrote, iclass 28, count 2 2006.280.07:34:40.25#ibcon#about to read 3, iclass 28, count 2 2006.280.07:34:40.28#ibcon#read 3, iclass 28, count 2 2006.280.07:34:40.28#ibcon#about to read 4, iclass 28, count 2 2006.280.07:34:40.28#ibcon#read 4, iclass 28, count 2 2006.280.07:34:40.28#ibcon#about to read 5, iclass 28, count 2 2006.280.07:34:40.28#ibcon#read 5, iclass 28, count 2 2006.280.07:34:40.28#ibcon#about to read 6, iclass 28, count 2 2006.280.07:34:40.28#ibcon#read 6, iclass 28, count 2 2006.280.07:34:40.28#ibcon#end of sib2, iclass 28, count 2 2006.280.07:34:40.28#ibcon#*after write, iclass 28, count 2 2006.280.07:34:40.28#ibcon#*before return 0, iclass 28, count 2 2006.280.07:34:40.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:40.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:40.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:34:40.28#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:40.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:34:40.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:34:40.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:34:40.40#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:34:40.40#ibcon#first serial, iclass 28, count 0 2006.280.07:34:40.40#ibcon#enter sib2, iclass 28, count 0 2006.280.07:34:40.40#ibcon#flushed, iclass 28, count 0 2006.280.07:34:40.40#ibcon#about to write, iclass 28, count 0 2006.280.07:34:40.40#ibcon#wrote, iclass 28, count 0 2006.280.07:34:40.40#ibcon#about to read 3, iclass 28, count 0 2006.280.07:34:40.42#ibcon#read 3, iclass 28, count 0 2006.280.07:34:40.42#ibcon#about to read 4, iclass 28, count 0 2006.280.07:34:40.42#ibcon#read 4, iclass 28, count 0 2006.280.07:34:40.42#ibcon#about to read 5, iclass 28, count 0 2006.280.07:34:40.42#ibcon#read 5, iclass 28, count 0 2006.280.07:34:40.42#ibcon#about to read 6, iclass 28, count 0 2006.280.07:34:40.42#ibcon#read 6, iclass 28, count 0 2006.280.07:34:40.42#ibcon#end of sib2, iclass 28, count 0 2006.280.07:34:40.42#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:34:40.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:34:40.42#ibcon#[25=USB\r\n] 2006.280.07:34:40.42#ibcon#*before write, iclass 28, count 0 2006.280.07:34:40.42#ibcon#enter sib2, iclass 28, count 0 2006.280.07:34:40.42#ibcon#flushed, iclass 28, count 0 2006.280.07:34:40.42#ibcon#about to write, iclass 28, count 0 2006.280.07:34:40.42#ibcon#wrote, iclass 28, count 0 2006.280.07:34:40.42#ibcon#about to read 3, iclass 28, count 0 2006.280.07:34:40.45#ibcon#read 3, iclass 28, count 0 2006.280.07:34:40.45#ibcon#about to read 4, iclass 28, count 0 2006.280.07:34:40.45#ibcon#read 4, iclass 28, count 0 2006.280.07:34:40.45#ibcon#about to read 5, iclass 28, count 0 2006.280.07:34:40.45#ibcon#read 5, iclass 28, count 0 2006.280.07:34:40.45#ibcon#about to read 6, iclass 28, count 0 2006.280.07:34:40.45#ibcon#read 6, iclass 28, count 0 2006.280.07:34:40.45#ibcon#end of sib2, iclass 28, count 0 2006.280.07:34:40.45#ibcon#*after write, iclass 28, count 0 2006.280.07:34:40.45#ibcon#*before return 0, iclass 28, count 0 2006.280.07:34:40.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:34:40.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:34:40.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:34:40.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:34:40.45$vc4f8/valo=7,832.99 2006.280.07:34:40.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:34:40.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:34:40.45#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:40.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:34:40.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:34:40.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:34:40.45#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:34:40.45#ibcon#first serial, iclass 30, count 0 2006.280.07:34:40.45#ibcon#enter sib2, iclass 30, count 0 2006.280.07:34:40.45#ibcon#flushed, iclass 30, count 0 2006.280.07:34:40.45#ibcon#about to write, iclass 30, count 0 2006.280.07:34:40.45#ibcon#wrote, iclass 30, count 0 2006.280.07:34:40.45#ibcon#about to read 3, iclass 30, count 0 2006.280.07:34:40.47#ibcon#read 3, iclass 30, count 0 2006.280.07:34:40.47#ibcon#about to read 4, iclass 30, count 0 2006.280.07:34:40.47#ibcon#read 4, iclass 30, count 0 2006.280.07:34:40.47#ibcon#about to read 5, iclass 30, count 0 2006.280.07:34:40.47#ibcon#read 5, iclass 30, count 0 2006.280.07:34:40.47#ibcon#about to read 6, iclass 30, count 0 2006.280.07:34:40.47#ibcon#read 6, iclass 30, count 0 2006.280.07:34:40.47#ibcon#end of sib2, iclass 30, count 0 2006.280.07:34:40.47#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:34:40.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:34:40.47#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:34:40.47#ibcon#*before write, iclass 30, count 0 2006.280.07:34:40.47#ibcon#enter sib2, iclass 30, count 0 2006.280.07:34:40.47#ibcon#flushed, iclass 30, count 0 2006.280.07:34:40.47#ibcon#about to write, iclass 30, count 0 2006.280.07:34:40.47#ibcon#wrote, iclass 30, count 0 2006.280.07:34:40.47#ibcon#about to read 3, iclass 30, count 0 2006.280.07:34:40.51#ibcon#read 3, iclass 30, count 0 2006.280.07:34:40.51#ibcon#about to read 4, iclass 30, count 0 2006.280.07:34:40.51#ibcon#read 4, iclass 30, count 0 2006.280.07:34:40.51#ibcon#about to read 5, iclass 30, count 0 2006.280.07:34:40.51#ibcon#read 5, iclass 30, count 0 2006.280.07:34:40.51#ibcon#about to read 6, iclass 30, count 0 2006.280.07:34:40.51#ibcon#read 6, iclass 30, count 0 2006.280.07:34:40.51#ibcon#end of sib2, iclass 30, count 0 2006.280.07:34:40.51#ibcon#*after write, iclass 30, count 0 2006.280.07:34:40.51#ibcon#*before return 0, iclass 30, count 0 2006.280.07:34:40.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:34:40.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:34:40.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:34:40.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:34:40.51$vc4f8/va=7,6 2006.280.07:34:40.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:34:40.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:34:40.51#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:40.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:34:40.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:34:40.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:34:40.57#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:34:40.57#ibcon#first serial, iclass 32, count 2 2006.280.07:34:40.57#ibcon#enter sib2, iclass 32, count 2 2006.280.07:34:40.57#ibcon#flushed, iclass 32, count 2 2006.280.07:34:40.57#ibcon#about to write, iclass 32, count 2 2006.280.07:34:40.57#ibcon#wrote, iclass 32, count 2 2006.280.07:34:40.57#ibcon#about to read 3, iclass 32, count 2 2006.280.07:34:40.59#ibcon#read 3, iclass 32, count 2 2006.280.07:34:40.59#ibcon#about to read 4, iclass 32, count 2 2006.280.07:34:40.59#ibcon#read 4, iclass 32, count 2 2006.280.07:34:40.59#ibcon#about to read 5, iclass 32, count 2 2006.280.07:34:40.59#ibcon#read 5, iclass 32, count 2 2006.280.07:34:40.59#ibcon#about to read 6, iclass 32, count 2 2006.280.07:34:40.59#ibcon#read 6, iclass 32, count 2 2006.280.07:34:40.59#ibcon#end of sib2, iclass 32, count 2 2006.280.07:34:40.59#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:34:40.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:34:40.59#ibcon#[25=AT07-06\r\n] 2006.280.07:34:40.59#ibcon#*before write, iclass 32, count 2 2006.280.07:34:40.59#ibcon#enter sib2, iclass 32, count 2 2006.280.07:34:40.59#ibcon#flushed, iclass 32, count 2 2006.280.07:34:40.59#ibcon#about to write, iclass 32, count 2 2006.280.07:34:40.59#ibcon#wrote, iclass 32, count 2 2006.280.07:34:40.59#ibcon#about to read 3, iclass 32, count 2 2006.280.07:34:40.62#ibcon#read 3, iclass 32, count 2 2006.280.07:34:40.62#ibcon#about to read 4, iclass 32, count 2 2006.280.07:34:40.62#ibcon#read 4, iclass 32, count 2 2006.280.07:34:40.62#ibcon#about to read 5, iclass 32, count 2 2006.280.07:34:40.62#ibcon#read 5, iclass 32, count 2 2006.280.07:34:40.62#ibcon#about to read 6, iclass 32, count 2 2006.280.07:34:40.62#ibcon#read 6, iclass 32, count 2 2006.280.07:34:40.62#ibcon#end of sib2, iclass 32, count 2 2006.280.07:34:40.62#ibcon#*after write, iclass 32, count 2 2006.280.07:34:40.62#ibcon#*before return 0, iclass 32, count 2 2006.280.07:34:40.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:34:40.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:34:40.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:34:40.62#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:40.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:34:40.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:34:40.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:34:40.74#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:34:40.74#ibcon#first serial, iclass 32, count 0 2006.280.07:34:40.74#ibcon#enter sib2, iclass 32, count 0 2006.280.07:34:40.74#ibcon#flushed, iclass 32, count 0 2006.280.07:34:40.74#ibcon#about to write, iclass 32, count 0 2006.280.07:34:40.74#ibcon#wrote, iclass 32, count 0 2006.280.07:34:40.74#ibcon#about to read 3, iclass 32, count 0 2006.280.07:34:40.76#ibcon#read 3, iclass 32, count 0 2006.280.07:34:40.76#ibcon#about to read 4, iclass 32, count 0 2006.280.07:34:40.76#ibcon#read 4, iclass 32, count 0 2006.280.07:34:40.76#ibcon#about to read 5, iclass 32, count 0 2006.280.07:34:40.76#ibcon#read 5, iclass 32, count 0 2006.280.07:34:40.76#ibcon#about to read 6, iclass 32, count 0 2006.280.07:34:40.76#ibcon#read 6, iclass 32, count 0 2006.280.07:34:40.76#ibcon#end of sib2, iclass 32, count 0 2006.280.07:34:40.76#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:34:40.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:34:40.76#ibcon#[25=USB\r\n] 2006.280.07:34:40.76#ibcon#*before write, iclass 32, count 0 2006.280.07:34:40.76#ibcon#enter sib2, iclass 32, count 0 2006.280.07:34:40.76#ibcon#flushed, iclass 32, count 0 2006.280.07:34:40.76#ibcon#about to write, iclass 32, count 0 2006.280.07:34:40.76#ibcon#wrote, iclass 32, count 0 2006.280.07:34:40.76#ibcon#about to read 3, iclass 32, count 0 2006.280.07:34:40.79#ibcon#read 3, iclass 32, count 0 2006.280.07:34:40.79#ibcon#about to read 4, iclass 32, count 0 2006.280.07:34:40.79#ibcon#read 4, iclass 32, count 0 2006.280.07:34:40.79#ibcon#about to read 5, iclass 32, count 0 2006.280.07:34:40.79#ibcon#read 5, iclass 32, count 0 2006.280.07:34:40.79#ibcon#about to read 6, iclass 32, count 0 2006.280.07:34:40.79#ibcon#read 6, iclass 32, count 0 2006.280.07:34:40.79#ibcon#end of sib2, iclass 32, count 0 2006.280.07:34:40.79#ibcon#*after write, iclass 32, count 0 2006.280.07:34:40.79#ibcon#*before return 0, iclass 32, count 0 2006.280.07:34:40.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:34:40.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:34:40.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:34:40.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:34:40.79$vc4f8/valo=8,852.99 2006.280.07:34:40.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:34:40.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:34:40.79#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:40.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:34:40.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:34:40.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:34:40.79#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:34:40.79#ibcon#first serial, iclass 34, count 0 2006.280.07:34:40.79#ibcon#enter sib2, iclass 34, count 0 2006.280.07:34:40.79#ibcon#flushed, iclass 34, count 0 2006.280.07:34:40.79#ibcon#about to write, iclass 34, count 0 2006.280.07:34:40.79#ibcon#wrote, iclass 34, count 0 2006.280.07:34:40.79#ibcon#about to read 3, iclass 34, count 0 2006.280.07:34:40.81#ibcon#read 3, iclass 34, count 0 2006.280.07:34:40.81#ibcon#about to read 4, iclass 34, count 0 2006.280.07:34:40.81#ibcon#read 4, iclass 34, count 0 2006.280.07:34:40.81#ibcon#about to read 5, iclass 34, count 0 2006.280.07:34:40.81#ibcon#read 5, iclass 34, count 0 2006.280.07:34:40.81#ibcon#about to read 6, iclass 34, count 0 2006.280.07:34:40.81#ibcon#read 6, iclass 34, count 0 2006.280.07:34:40.81#ibcon#end of sib2, iclass 34, count 0 2006.280.07:34:40.81#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:34:40.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:34:40.81#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:34:40.81#ibcon#*before write, iclass 34, count 0 2006.280.07:34:40.81#ibcon#enter sib2, iclass 34, count 0 2006.280.07:34:40.81#ibcon#flushed, iclass 34, count 0 2006.280.07:34:40.81#ibcon#about to write, iclass 34, count 0 2006.280.07:34:40.81#ibcon#wrote, iclass 34, count 0 2006.280.07:34:40.81#ibcon#about to read 3, iclass 34, count 0 2006.280.07:34:40.85#ibcon#read 3, iclass 34, count 0 2006.280.07:34:40.85#ibcon#about to read 4, iclass 34, count 0 2006.280.07:34:40.85#ibcon#read 4, iclass 34, count 0 2006.280.07:34:40.85#ibcon#about to read 5, iclass 34, count 0 2006.280.07:34:40.85#ibcon#read 5, iclass 34, count 0 2006.280.07:34:40.85#ibcon#about to read 6, iclass 34, count 0 2006.280.07:34:40.85#ibcon#read 6, iclass 34, count 0 2006.280.07:34:40.85#ibcon#end of sib2, iclass 34, count 0 2006.280.07:34:40.85#ibcon#*after write, iclass 34, count 0 2006.280.07:34:40.85#ibcon#*before return 0, iclass 34, count 0 2006.280.07:34:40.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:34:40.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:34:40.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:34:40.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:34:40.85$vc4f8/va=8,6 2006.280.07:34:40.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:34:40.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:34:40.85#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:40.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:34:40.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:34:40.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:34:40.91#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:34:40.91#ibcon#first serial, iclass 36, count 2 2006.280.07:34:40.91#ibcon#enter sib2, iclass 36, count 2 2006.280.07:34:40.91#ibcon#flushed, iclass 36, count 2 2006.280.07:34:40.91#ibcon#about to write, iclass 36, count 2 2006.280.07:34:40.91#ibcon#wrote, iclass 36, count 2 2006.280.07:34:40.91#ibcon#about to read 3, iclass 36, count 2 2006.280.07:34:40.93#ibcon#read 3, iclass 36, count 2 2006.280.07:34:40.93#ibcon#about to read 4, iclass 36, count 2 2006.280.07:34:40.93#ibcon#read 4, iclass 36, count 2 2006.280.07:34:40.93#ibcon#about to read 5, iclass 36, count 2 2006.280.07:34:40.93#ibcon#read 5, iclass 36, count 2 2006.280.07:34:40.93#ibcon#about to read 6, iclass 36, count 2 2006.280.07:34:40.93#ibcon#read 6, iclass 36, count 2 2006.280.07:34:40.93#ibcon#end of sib2, iclass 36, count 2 2006.280.07:34:40.93#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:34:40.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:34:40.93#ibcon#[25=AT08-06\r\n] 2006.280.07:34:40.93#ibcon#*before write, iclass 36, count 2 2006.280.07:34:40.93#ibcon#enter sib2, iclass 36, count 2 2006.280.07:34:40.93#ibcon#flushed, iclass 36, count 2 2006.280.07:34:40.93#ibcon#about to write, iclass 36, count 2 2006.280.07:34:40.93#ibcon#wrote, iclass 36, count 2 2006.280.07:34:40.93#ibcon#about to read 3, iclass 36, count 2 2006.280.07:34:40.96#ibcon#read 3, iclass 36, count 2 2006.280.07:34:40.96#ibcon#about to read 4, iclass 36, count 2 2006.280.07:34:40.96#ibcon#read 4, iclass 36, count 2 2006.280.07:34:40.96#ibcon#about to read 5, iclass 36, count 2 2006.280.07:34:40.96#ibcon#read 5, iclass 36, count 2 2006.280.07:34:40.96#ibcon#about to read 6, iclass 36, count 2 2006.280.07:34:40.96#ibcon#read 6, iclass 36, count 2 2006.280.07:34:40.96#ibcon#end of sib2, iclass 36, count 2 2006.280.07:34:40.96#ibcon#*after write, iclass 36, count 2 2006.280.07:34:40.96#ibcon#*before return 0, iclass 36, count 2 2006.280.07:34:40.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:34:40.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:34:40.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:34:40.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:40.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:34:41.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:34:41.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:34:41.08#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:34:41.08#ibcon#first serial, iclass 36, count 0 2006.280.07:34:41.08#ibcon#enter sib2, iclass 36, count 0 2006.280.07:34:41.08#ibcon#flushed, iclass 36, count 0 2006.280.07:34:41.08#ibcon#about to write, iclass 36, count 0 2006.280.07:34:41.08#ibcon#wrote, iclass 36, count 0 2006.280.07:34:41.08#ibcon#about to read 3, iclass 36, count 0 2006.280.07:34:41.10#ibcon#read 3, iclass 36, count 0 2006.280.07:34:41.10#ibcon#about to read 4, iclass 36, count 0 2006.280.07:34:41.10#ibcon#read 4, iclass 36, count 0 2006.280.07:34:41.10#ibcon#about to read 5, iclass 36, count 0 2006.280.07:34:41.10#ibcon#read 5, iclass 36, count 0 2006.280.07:34:41.10#ibcon#about to read 6, iclass 36, count 0 2006.280.07:34:41.10#ibcon#read 6, iclass 36, count 0 2006.280.07:34:41.10#ibcon#end of sib2, iclass 36, count 0 2006.280.07:34:41.10#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:34:41.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:34:41.10#ibcon#[25=USB\r\n] 2006.280.07:34:41.10#ibcon#*before write, iclass 36, count 0 2006.280.07:34:41.10#ibcon#enter sib2, iclass 36, count 0 2006.280.07:34:41.10#ibcon#flushed, iclass 36, count 0 2006.280.07:34:41.10#ibcon#about to write, iclass 36, count 0 2006.280.07:34:41.10#ibcon#wrote, iclass 36, count 0 2006.280.07:34:41.10#ibcon#about to read 3, iclass 36, count 0 2006.280.07:34:41.13#ibcon#read 3, iclass 36, count 0 2006.280.07:34:41.13#ibcon#about to read 4, iclass 36, count 0 2006.280.07:34:41.13#ibcon#read 4, iclass 36, count 0 2006.280.07:34:41.13#ibcon#about to read 5, iclass 36, count 0 2006.280.07:34:41.13#ibcon#read 5, iclass 36, count 0 2006.280.07:34:41.13#ibcon#about to read 6, iclass 36, count 0 2006.280.07:34:41.13#ibcon#read 6, iclass 36, count 0 2006.280.07:34:41.13#ibcon#end of sib2, iclass 36, count 0 2006.280.07:34:41.13#ibcon#*after write, iclass 36, count 0 2006.280.07:34:41.13#ibcon#*before return 0, iclass 36, count 0 2006.280.07:34:41.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:34:41.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:34:41.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:34:41.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:34:41.13$vc4f8/vblo=1,632.99 2006.280.07:34:41.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:34:41.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:34:41.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:41.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:41.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:41.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:41.13#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:34:41.13#ibcon#first serial, iclass 38, count 0 2006.280.07:34:41.13#ibcon#enter sib2, iclass 38, count 0 2006.280.07:34:41.13#ibcon#flushed, iclass 38, count 0 2006.280.07:34:41.13#ibcon#about to write, iclass 38, count 0 2006.280.07:34:41.13#ibcon#wrote, iclass 38, count 0 2006.280.07:34:41.13#ibcon#about to read 3, iclass 38, count 0 2006.280.07:34:41.15#ibcon#read 3, iclass 38, count 0 2006.280.07:34:41.15#ibcon#about to read 4, iclass 38, count 0 2006.280.07:34:41.15#ibcon#read 4, iclass 38, count 0 2006.280.07:34:41.15#ibcon#about to read 5, iclass 38, count 0 2006.280.07:34:41.15#ibcon#read 5, iclass 38, count 0 2006.280.07:34:41.15#ibcon#about to read 6, iclass 38, count 0 2006.280.07:34:41.15#ibcon#read 6, iclass 38, count 0 2006.280.07:34:41.15#ibcon#end of sib2, iclass 38, count 0 2006.280.07:34:41.15#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:34:41.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:34:41.15#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:34:41.15#ibcon#*before write, iclass 38, count 0 2006.280.07:34:41.15#ibcon#enter sib2, iclass 38, count 0 2006.280.07:34:41.15#ibcon#flushed, iclass 38, count 0 2006.280.07:34:41.15#ibcon#about to write, iclass 38, count 0 2006.280.07:34:41.15#ibcon#wrote, iclass 38, count 0 2006.280.07:34:41.15#ibcon#about to read 3, iclass 38, count 0 2006.280.07:34:41.19#ibcon#read 3, iclass 38, count 0 2006.280.07:34:41.19#ibcon#about to read 4, iclass 38, count 0 2006.280.07:34:41.19#ibcon#read 4, iclass 38, count 0 2006.280.07:34:41.19#ibcon#about to read 5, iclass 38, count 0 2006.280.07:34:41.19#ibcon#read 5, iclass 38, count 0 2006.280.07:34:41.19#ibcon#about to read 6, iclass 38, count 0 2006.280.07:34:41.19#ibcon#read 6, iclass 38, count 0 2006.280.07:34:41.19#ibcon#end of sib2, iclass 38, count 0 2006.280.07:34:41.19#ibcon#*after write, iclass 38, count 0 2006.280.07:34:41.19#ibcon#*before return 0, iclass 38, count 0 2006.280.07:34:41.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:41.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:34:41.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:34:41.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:34:41.19$vc4f8/vb=1,4 2006.280.07:34:41.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:34:41.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:34:41.19#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:41.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:41.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:41.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:41.19#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:34:41.19#ibcon#first serial, iclass 40, count 2 2006.280.07:34:41.19#ibcon#enter sib2, iclass 40, count 2 2006.280.07:34:41.19#ibcon#flushed, iclass 40, count 2 2006.280.07:34:41.19#ibcon#about to write, iclass 40, count 2 2006.280.07:34:41.19#ibcon#wrote, iclass 40, count 2 2006.280.07:34:41.19#ibcon#about to read 3, iclass 40, count 2 2006.280.07:34:41.21#ibcon#read 3, iclass 40, count 2 2006.280.07:34:41.21#ibcon#about to read 4, iclass 40, count 2 2006.280.07:34:41.21#ibcon#read 4, iclass 40, count 2 2006.280.07:34:41.21#ibcon#about to read 5, iclass 40, count 2 2006.280.07:34:41.21#ibcon#read 5, iclass 40, count 2 2006.280.07:34:41.21#ibcon#about to read 6, iclass 40, count 2 2006.280.07:34:41.21#ibcon#read 6, iclass 40, count 2 2006.280.07:34:41.21#ibcon#end of sib2, iclass 40, count 2 2006.280.07:34:41.21#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:34:41.21#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:34:41.21#ibcon#[27=AT01-04\r\n] 2006.280.07:34:41.21#ibcon#*before write, iclass 40, count 2 2006.280.07:34:41.21#ibcon#enter sib2, iclass 40, count 2 2006.280.07:34:41.21#ibcon#flushed, iclass 40, count 2 2006.280.07:34:41.21#ibcon#about to write, iclass 40, count 2 2006.280.07:34:41.21#ibcon#wrote, iclass 40, count 2 2006.280.07:34:41.21#ibcon#about to read 3, iclass 40, count 2 2006.280.07:34:41.24#ibcon#read 3, iclass 40, count 2 2006.280.07:34:41.25#ibcon#about to read 4, iclass 40, count 2 2006.280.07:34:41.25#ibcon#read 4, iclass 40, count 2 2006.280.07:34:41.25#ibcon#about to read 5, iclass 40, count 2 2006.280.07:34:41.25#ibcon#read 5, iclass 40, count 2 2006.280.07:34:41.25#ibcon#about to read 6, iclass 40, count 2 2006.280.07:34:41.25#ibcon#read 6, iclass 40, count 2 2006.280.07:34:41.25#ibcon#end of sib2, iclass 40, count 2 2006.280.07:34:41.25#ibcon#*after write, iclass 40, count 2 2006.280.07:34:41.25#ibcon#*before return 0, iclass 40, count 2 2006.280.07:34:41.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:41.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:34:41.25#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:34:41.25#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:41.25#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:41.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:41.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:41.36#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:34:41.36#ibcon#first serial, iclass 40, count 0 2006.280.07:34:41.36#ibcon#enter sib2, iclass 40, count 0 2006.280.07:34:41.36#ibcon#flushed, iclass 40, count 0 2006.280.07:34:41.36#ibcon#about to write, iclass 40, count 0 2006.280.07:34:41.36#ibcon#wrote, iclass 40, count 0 2006.280.07:34:41.36#ibcon#about to read 3, iclass 40, count 0 2006.280.07:34:41.38#ibcon#read 3, iclass 40, count 0 2006.280.07:34:41.38#ibcon#about to read 4, iclass 40, count 0 2006.280.07:34:41.38#ibcon#read 4, iclass 40, count 0 2006.280.07:34:41.38#ibcon#about to read 5, iclass 40, count 0 2006.280.07:34:41.38#ibcon#read 5, iclass 40, count 0 2006.280.07:34:41.38#ibcon#about to read 6, iclass 40, count 0 2006.280.07:34:41.38#ibcon#read 6, iclass 40, count 0 2006.280.07:34:41.38#ibcon#end of sib2, iclass 40, count 0 2006.280.07:34:41.38#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:34:41.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:34:41.38#ibcon#[27=USB\r\n] 2006.280.07:34:41.38#ibcon#*before write, iclass 40, count 0 2006.280.07:34:41.38#ibcon#enter sib2, iclass 40, count 0 2006.280.07:34:41.38#ibcon#flushed, iclass 40, count 0 2006.280.07:34:41.38#ibcon#about to write, iclass 40, count 0 2006.280.07:34:41.38#ibcon#wrote, iclass 40, count 0 2006.280.07:34:41.38#ibcon#about to read 3, iclass 40, count 0 2006.280.07:34:41.41#ibcon#read 3, iclass 40, count 0 2006.280.07:34:41.41#ibcon#about to read 4, iclass 40, count 0 2006.280.07:34:41.41#ibcon#read 4, iclass 40, count 0 2006.280.07:34:41.41#ibcon#about to read 5, iclass 40, count 0 2006.280.07:34:41.41#ibcon#read 5, iclass 40, count 0 2006.280.07:34:41.41#ibcon#about to read 6, iclass 40, count 0 2006.280.07:34:41.41#ibcon#read 6, iclass 40, count 0 2006.280.07:34:41.41#ibcon#end of sib2, iclass 40, count 0 2006.280.07:34:41.41#ibcon#*after write, iclass 40, count 0 2006.280.07:34:41.41#ibcon#*before return 0, iclass 40, count 0 2006.280.07:34:41.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:41.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:34:41.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:34:41.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:34:41.41$vc4f8/vblo=2,640.99 2006.280.07:34:41.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:34:41.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:34:41.41#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:41.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:41.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:41.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:41.41#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:34:41.41#ibcon#first serial, iclass 4, count 0 2006.280.07:34:41.41#ibcon#enter sib2, iclass 4, count 0 2006.280.07:34:41.41#ibcon#flushed, iclass 4, count 0 2006.280.07:34:41.41#ibcon#about to write, iclass 4, count 0 2006.280.07:34:41.41#ibcon#wrote, iclass 4, count 0 2006.280.07:34:41.41#ibcon#about to read 3, iclass 4, count 0 2006.280.07:34:41.43#ibcon#read 3, iclass 4, count 0 2006.280.07:34:41.44#ibcon#about to read 4, iclass 4, count 0 2006.280.07:34:41.44#ibcon#read 4, iclass 4, count 0 2006.280.07:34:41.44#ibcon#about to read 5, iclass 4, count 0 2006.280.07:34:41.44#ibcon#read 5, iclass 4, count 0 2006.280.07:34:41.44#ibcon#about to read 6, iclass 4, count 0 2006.280.07:34:41.44#ibcon#read 6, iclass 4, count 0 2006.280.07:34:41.44#ibcon#end of sib2, iclass 4, count 0 2006.280.07:34:41.44#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:34:41.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:34:41.44#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:34:41.44#ibcon#*before write, iclass 4, count 0 2006.280.07:34:41.44#ibcon#enter sib2, iclass 4, count 0 2006.280.07:34:41.44#ibcon#flushed, iclass 4, count 0 2006.280.07:34:41.44#ibcon#about to write, iclass 4, count 0 2006.280.07:34:41.44#ibcon#wrote, iclass 4, count 0 2006.280.07:34:41.44#ibcon#about to read 3, iclass 4, count 0 2006.280.07:34:41.48#ibcon#read 3, iclass 4, count 0 2006.280.07:34:41.48#ibcon#about to read 4, iclass 4, count 0 2006.280.07:34:41.48#ibcon#read 4, iclass 4, count 0 2006.280.07:34:41.48#ibcon#about to read 5, iclass 4, count 0 2006.280.07:34:41.48#ibcon#read 5, iclass 4, count 0 2006.280.07:34:41.48#ibcon#about to read 6, iclass 4, count 0 2006.280.07:34:41.48#ibcon#read 6, iclass 4, count 0 2006.280.07:34:41.48#ibcon#end of sib2, iclass 4, count 0 2006.280.07:34:41.48#ibcon#*after write, iclass 4, count 0 2006.280.07:34:41.48#ibcon#*before return 0, iclass 4, count 0 2006.280.07:34:41.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:41.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:34:41.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:34:41.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:34:41.48$vc4f8/vb=2,5 2006.280.07:34:41.48#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:34:41.48#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:34:41.48#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:41.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:41.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:41.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:41.53#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:34:41.53#ibcon#first serial, iclass 6, count 2 2006.280.07:34:41.53#ibcon#enter sib2, iclass 6, count 2 2006.280.07:34:41.53#ibcon#flushed, iclass 6, count 2 2006.280.07:34:41.53#ibcon#about to write, iclass 6, count 2 2006.280.07:34:41.53#ibcon#wrote, iclass 6, count 2 2006.280.07:34:41.53#ibcon#about to read 3, iclass 6, count 2 2006.280.07:34:41.55#ibcon#read 3, iclass 6, count 2 2006.280.07:34:41.55#ibcon#about to read 4, iclass 6, count 2 2006.280.07:34:41.55#ibcon#read 4, iclass 6, count 2 2006.280.07:34:41.55#ibcon#about to read 5, iclass 6, count 2 2006.280.07:34:41.55#ibcon#read 5, iclass 6, count 2 2006.280.07:34:41.55#ibcon#about to read 6, iclass 6, count 2 2006.280.07:34:41.55#ibcon#read 6, iclass 6, count 2 2006.280.07:34:41.55#ibcon#end of sib2, iclass 6, count 2 2006.280.07:34:41.55#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:34:41.55#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:34:41.55#ibcon#[27=AT02-05\r\n] 2006.280.07:34:41.55#ibcon#*before write, iclass 6, count 2 2006.280.07:34:41.55#ibcon#enter sib2, iclass 6, count 2 2006.280.07:34:41.55#ibcon#flushed, iclass 6, count 2 2006.280.07:34:41.55#ibcon#about to write, iclass 6, count 2 2006.280.07:34:41.55#ibcon#wrote, iclass 6, count 2 2006.280.07:34:41.55#ibcon#about to read 3, iclass 6, count 2 2006.280.07:34:41.58#ibcon#read 3, iclass 6, count 2 2006.280.07:34:41.58#ibcon#about to read 4, iclass 6, count 2 2006.280.07:34:41.58#ibcon#read 4, iclass 6, count 2 2006.280.07:34:41.58#ibcon#about to read 5, iclass 6, count 2 2006.280.07:34:41.58#ibcon#read 5, iclass 6, count 2 2006.280.07:34:41.58#ibcon#about to read 6, iclass 6, count 2 2006.280.07:34:41.58#ibcon#read 6, iclass 6, count 2 2006.280.07:34:41.58#ibcon#end of sib2, iclass 6, count 2 2006.280.07:34:41.58#ibcon#*after write, iclass 6, count 2 2006.280.07:34:41.58#ibcon#*before return 0, iclass 6, count 2 2006.280.07:34:41.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:41.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:34:41.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:34:41.58#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:41.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:41.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:41.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:41.70#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:34:41.70#ibcon#first serial, iclass 6, count 0 2006.280.07:34:41.70#ibcon#enter sib2, iclass 6, count 0 2006.280.07:34:41.70#ibcon#flushed, iclass 6, count 0 2006.280.07:34:41.70#ibcon#about to write, iclass 6, count 0 2006.280.07:34:41.70#ibcon#wrote, iclass 6, count 0 2006.280.07:34:41.70#ibcon#about to read 3, iclass 6, count 0 2006.280.07:34:41.72#ibcon#read 3, iclass 6, count 0 2006.280.07:34:41.72#ibcon#about to read 4, iclass 6, count 0 2006.280.07:34:41.72#ibcon#read 4, iclass 6, count 0 2006.280.07:34:41.72#ibcon#about to read 5, iclass 6, count 0 2006.280.07:34:41.72#ibcon#read 5, iclass 6, count 0 2006.280.07:34:41.72#ibcon#about to read 6, iclass 6, count 0 2006.280.07:34:41.72#ibcon#read 6, iclass 6, count 0 2006.280.07:34:41.72#ibcon#end of sib2, iclass 6, count 0 2006.280.07:34:41.72#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:34:41.72#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:34:41.72#ibcon#[27=USB\r\n] 2006.280.07:34:41.72#ibcon#*before write, iclass 6, count 0 2006.280.07:34:41.72#ibcon#enter sib2, iclass 6, count 0 2006.280.07:34:41.72#ibcon#flushed, iclass 6, count 0 2006.280.07:34:41.72#ibcon#about to write, iclass 6, count 0 2006.280.07:34:41.72#ibcon#wrote, iclass 6, count 0 2006.280.07:34:41.72#ibcon#about to read 3, iclass 6, count 0 2006.280.07:34:41.75#ibcon#read 3, iclass 6, count 0 2006.280.07:34:41.75#ibcon#about to read 4, iclass 6, count 0 2006.280.07:34:41.75#ibcon#read 4, iclass 6, count 0 2006.280.07:34:41.75#ibcon#about to read 5, iclass 6, count 0 2006.280.07:34:41.75#ibcon#read 5, iclass 6, count 0 2006.280.07:34:41.75#ibcon#about to read 6, iclass 6, count 0 2006.280.07:34:41.75#ibcon#read 6, iclass 6, count 0 2006.280.07:34:41.75#ibcon#end of sib2, iclass 6, count 0 2006.280.07:34:41.75#ibcon#*after write, iclass 6, count 0 2006.280.07:34:41.75#ibcon#*before return 0, iclass 6, count 0 2006.280.07:34:41.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:41.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:34:41.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:34:41.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:34:41.75$vc4f8/vblo=3,656.99 2006.280.07:34:41.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:34:41.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:34:41.75#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:41.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:41.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:41.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:41.75#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:34:41.75#ibcon#first serial, iclass 10, count 0 2006.280.07:34:41.75#ibcon#enter sib2, iclass 10, count 0 2006.280.07:34:41.75#ibcon#flushed, iclass 10, count 0 2006.280.07:34:41.75#ibcon#about to write, iclass 10, count 0 2006.280.07:34:41.75#ibcon#wrote, iclass 10, count 0 2006.280.07:34:41.75#ibcon#about to read 3, iclass 10, count 0 2006.280.07:34:41.77#ibcon#read 3, iclass 10, count 0 2006.280.07:34:41.77#ibcon#about to read 4, iclass 10, count 0 2006.280.07:34:41.77#ibcon#read 4, iclass 10, count 0 2006.280.07:34:41.77#ibcon#about to read 5, iclass 10, count 0 2006.280.07:34:41.77#ibcon#read 5, iclass 10, count 0 2006.280.07:34:41.77#ibcon#about to read 6, iclass 10, count 0 2006.280.07:34:41.77#ibcon#read 6, iclass 10, count 0 2006.280.07:34:41.77#ibcon#end of sib2, iclass 10, count 0 2006.280.07:34:41.77#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:34:41.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:34:41.77#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:34:41.77#ibcon#*before write, iclass 10, count 0 2006.280.07:34:41.77#ibcon#enter sib2, iclass 10, count 0 2006.280.07:34:41.77#ibcon#flushed, iclass 10, count 0 2006.280.07:34:41.77#ibcon#about to write, iclass 10, count 0 2006.280.07:34:41.77#ibcon#wrote, iclass 10, count 0 2006.280.07:34:41.77#ibcon#about to read 3, iclass 10, count 0 2006.280.07:34:41.81#ibcon#read 3, iclass 10, count 0 2006.280.07:34:41.81#ibcon#about to read 4, iclass 10, count 0 2006.280.07:34:41.81#ibcon#read 4, iclass 10, count 0 2006.280.07:34:41.81#ibcon#about to read 5, iclass 10, count 0 2006.280.07:34:41.81#ibcon#read 5, iclass 10, count 0 2006.280.07:34:41.81#ibcon#about to read 6, iclass 10, count 0 2006.280.07:34:41.81#ibcon#read 6, iclass 10, count 0 2006.280.07:34:41.81#ibcon#end of sib2, iclass 10, count 0 2006.280.07:34:41.81#ibcon#*after write, iclass 10, count 0 2006.280.07:34:41.81#ibcon#*before return 0, iclass 10, count 0 2006.280.07:34:41.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:41.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:34:41.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:34:41.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:34:41.81$vc4f8/vb=3,4 2006.280.07:34:41.81#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:34:41.81#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:34:41.81#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:41.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:41.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:41.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:41.87#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:34:41.87#ibcon#first serial, iclass 12, count 2 2006.280.07:34:41.87#ibcon#enter sib2, iclass 12, count 2 2006.280.07:34:41.87#ibcon#flushed, iclass 12, count 2 2006.280.07:34:41.87#ibcon#about to write, iclass 12, count 2 2006.280.07:34:41.87#ibcon#wrote, iclass 12, count 2 2006.280.07:34:41.87#ibcon#about to read 3, iclass 12, count 2 2006.280.07:34:41.89#ibcon#read 3, iclass 12, count 2 2006.280.07:34:41.89#ibcon#about to read 4, iclass 12, count 2 2006.280.07:34:41.89#ibcon#read 4, iclass 12, count 2 2006.280.07:34:41.89#ibcon#about to read 5, iclass 12, count 2 2006.280.07:34:41.89#ibcon#read 5, iclass 12, count 2 2006.280.07:34:41.89#ibcon#about to read 6, iclass 12, count 2 2006.280.07:34:41.89#ibcon#read 6, iclass 12, count 2 2006.280.07:34:41.89#ibcon#end of sib2, iclass 12, count 2 2006.280.07:34:41.89#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:34:41.89#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:34:41.89#ibcon#[27=AT03-04\r\n] 2006.280.07:34:41.89#ibcon#*before write, iclass 12, count 2 2006.280.07:34:41.89#ibcon#enter sib2, iclass 12, count 2 2006.280.07:34:41.89#ibcon#flushed, iclass 12, count 2 2006.280.07:34:41.89#ibcon#about to write, iclass 12, count 2 2006.280.07:34:41.89#ibcon#wrote, iclass 12, count 2 2006.280.07:34:41.89#ibcon#about to read 3, iclass 12, count 2 2006.280.07:34:41.92#ibcon#read 3, iclass 12, count 2 2006.280.07:34:41.92#ibcon#about to read 4, iclass 12, count 2 2006.280.07:34:41.92#ibcon#read 4, iclass 12, count 2 2006.280.07:34:41.92#ibcon#about to read 5, iclass 12, count 2 2006.280.07:34:41.92#ibcon#read 5, iclass 12, count 2 2006.280.07:34:41.92#ibcon#about to read 6, iclass 12, count 2 2006.280.07:34:41.92#ibcon#read 6, iclass 12, count 2 2006.280.07:34:41.92#ibcon#end of sib2, iclass 12, count 2 2006.280.07:34:41.92#ibcon#*after write, iclass 12, count 2 2006.280.07:34:41.92#ibcon#*before return 0, iclass 12, count 2 2006.280.07:34:41.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:41.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:34:41.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:34:41.92#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:41.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:42.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:42.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:42.04#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:34:42.04#ibcon#first serial, iclass 12, count 0 2006.280.07:34:42.04#ibcon#enter sib2, iclass 12, count 0 2006.280.07:34:42.04#ibcon#flushed, iclass 12, count 0 2006.280.07:34:42.04#ibcon#about to write, iclass 12, count 0 2006.280.07:34:42.04#ibcon#wrote, iclass 12, count 0 2006.280.07:34:42.04#ibcon#about to read 3, iclass 12, count 0 2006.280.07:34:42.06#ibcon#read 3, iclass 12, count 0 2006.280.07:34:42.06#ibcon#about to read 4, iclass 12, count 0 2006.280.07:34:42.06#ibcon#read 4, iclass 12, count 0 2006.280.07:34:42.06#ibcon#about to read 5, iclass 12, count 0 2006.280.07:34:42.06#ibcon#read 5, iclass 12, count 0 2006.280.07:34:42.06#ibcon#about to read 6, iclass 12, count 0 2006.280.07:34:42.06#ibcon#read 6, iclass 12, count 0 2006.280.07:34:42.06#ibcon#end of sib2, iclass 12, count 0 2006.280.07:34:42.06#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:34:42.06#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:34:42.06#ibcon#[27=USB\r\n] 2006.280.07:34:42.06#ibcon#*before write, iclass 12, count 0 2006.280.07:34:42.06#ibcon#enter sib2, iclass 12, count 0 2006.280.07:34:42.06#ibcon#flushed, iclass 12, count 0 2006.280.07:34:42.06#ibcon#about to write, iclass 12, count 0 2006.280.07:34:42.06#ibcon#wrote, iclass 12, count 0 2006.280.07:34:42.06#ibcon#about to read 3, iclass 12, count 0 2006.280.07:34:42.09#ibcon#read 3, iclass 12, count 0 2006.280.07:34:42.09#ibcon#about to read 4, iclass 12, count 0 2006.280.07:34:42.09#ibcon#read 4, iclass 12, count 0 2006.280.07:34:42.09#ibcon#about to read 5, iclass 12, count 0 2006.280.07:34:42.09#ibcon#read 5, iclass 12, count 0 2006.280.07:34:42.09#ibcon#about to read 6, iclass 12, count 0 2006.280.07:34:42.09#ibcon#read 6, iclass 12, count 0 2006.280.07:34:42.09#ibcon#end of sib2, iclass 12, count 0 2006.280.07:34:42.09#ibcon#*after write, iclass 12, count 0 2006.280.07:34:42.09#ibcon#*before return 0, iclass 12, count 0 2006.280.07:34:42.09#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:42.09#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:34:42.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:34:42.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:34:42.09$vc4f8/vblo=4,712.99 2006.280.07:34:42.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:34:42.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:34:42.09#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:42.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:42.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:42.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:42.09#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:34:42.09#ibcon#first serial, iclass 14, count 0 2006.280.07:34:42.09#ibcon#enter sib2, iclass 14, count 0 2006.280.07:34:42.09#ibcon#flushed, iclass 14, count 0 2006.280.07:34:42.09#ibcon#about to write, iclass 14, count 0 2006.280.07:34:42.09#ibcon#wrote, iclass 14, count 0 2006.280.07:34:42.09#ibcon#about to read 3, iclass 14, count 0 2006.280.07:34:42.11#ibcon#read 3, iclass 14, count 0 2006.280.07:34:42.11#ibcon#about to read 4, iclass 14, count 0 2006.280.07:34:42.11#ibcon#read 4, iclass 14, count 0 2006.280.07:34:42.11#ibcon#about to read 5, iclass 14, count 0 2006.280.07:34:42.11#ibcon#read 5, iclass 14, count 0 2006.280.07:34:42.11#ibcon#about to read 6, iclass 14, count 0 2006.280.07:34:42.11#ibcon#read 6, iclass 14, count 0 2006.280.07:34:42.11#ibcon#end of sib2, iclass 14, count 0 2006.280.07:34:42.11#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:34:42.11#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:34:42.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:34:42.13#ibcon#*before write, iclass 14, count 0 2006.280.07:34:42.13#ibcon#enter sib2, iclass 14, count 0 2006.280.07:34:42.13#ibcon#flushed, iclass 14, count 0 2006.280.07:34:42.13#ibcon#about to write, iclass 14, count 0 2006.280.07:34:42.13#ibcon#wrote, iclass 14, count 0 2006.280.07:34:42.13#ibcon#about to read 3, iclass 14, count 0 2006.280.07:34:42.18#ibcon#read 3, iclass 14, count 0 2006.280.07:34:42.18#ibcon#about to read 4, iclass 14, count 0 2006.280.07:34:42.18#ibcon#read 4, iclass 14, count 0 2006.280.07:34:42.18#ibcon#about to read 5, iclass 14, count 0 2006.280.07:34:42.18#ibcon#read 5, iclass 14, count 0 2006.280.07:34:42.18#ibcon#about to read 6, iclass 14, count 0 2006.280.07:34:42.18#ibcon#read 6, iclass 14, count 0 2006.280.07:34:42.18#ibcon#end of sib2, iclass 14, count 0 2006.280.07:34:42.18#ibcon#*after write, iclass 14, count 0 2006.280.07:34:42.18#ibcon#*before return 0, iclass 14, count 0 2006.280.07:34:42.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:42.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:34:42.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:34:42.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:34:42.18$vc4f8/vb=4,4 2006.280.07:34:42.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:34:42.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:34:42.18#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:42.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:42.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:42.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:42.21#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:34:42.21#ibcon#first serial, iclass 16, count 2 2006.280.07:34:42.21#ibcon#enter sib2, iclass 16, count 2 2006.280.07:34:42.21#ibcon#flushed, iclass 16, count 2 2006.280.07:34:42.21#ibcon#about to write, iclass 16, count 2 2006.280.07:34:42.21#ibcon#wrote, iclass 16, count 2 2006.280.07:34:42.21#ibcon#about to read 3, iclass 16, count 2 2006.280.07:34:42.23#ibcon#read 3, iclass 16, count 2 2006.280.07:34:42.23#ibcon#about to read 4, iclass 16, count 2 2006.280.07:34:42.23#ibcon#read 4, iclass 16, count 2 2006.280.07:34:42.23#ibcon#about to read 5, iclass 16, count 2 2006.280.07:34:42.23#ibcon#read 5, iclass 16, count 2 2006.280.07:34:42.23#ibcon#about to read 6, iclass 16, count 2 2006.280.07:34:42.23#ibcon#read 6, iclass 16, count 2 2006.280.07:34:42.23#ibcon#end of sib2, iclass 16, count 2 2006.280.07:34:42.23#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:34:42.23#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:34:42.23#ibcon#[27=AT04-04\r\n] 2006.280.07:34:42.23#ibcon#*before write, iclass 16, count 2 2006.280.07:34:42.23#ibcon#enter sib2, iclass 16, count 2 2006.280.07:34:42.23#ibcon#flushed, iclass 16, count 2 2006.280.07:34:42.23#ibcon#about to write, iclass 16, count 2 2006.280.07:34:42.23#ibcon#wrote, iclass 16, count 2 2006.280.07:34:42.23#ibcon#about to read 3, iclass 16, count 2 2006.280.07:34:42.26#ibcon#read 3, iclass 16, count 2 2006.280.07:34:42.26#ibcon#about to read 4, iclass 16, count 2 2006.280.07:34:42.26#ibcon#read 4, iclass 16, count 2 2006.280.07:34:42.26#ibcon#about to read 5, iclass 16, count 2 2006.280.07:34:42.26#ibcon#read 5, iclass 16, count 2 2006.280.07:34:42.26#ibcon#about to read 6, iclass 16, count 2 2006.280.07:34:42.26#ibcon#read 6, iclass 16, count 2 2006.280.07:34:42.26#ibcon#end of sib2, iclass 16, count 2 2006.280.07:34:42.26#ibcon#*after write, iclass 16, count 2 2006.280.07:34:42.26#ibcon#*before return 0, iclass 16, count 2 2006.280.07:34:42.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:42.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:34:42.26#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:34:42.26#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:42.26#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:42.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:42.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:42.38#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:34:42.38#ibcon#first serial, iclass 16, count 0 2006.280.07:34:42.38#ibcon#enter sib2, iclass 16, count 0 2006.280.07:34:42.38#ibcon#flushed, iclass 16, count 0 2006.280.07:34:42.38#ibcon#about to write, iclass 16, count 0 2006.280.07:34:42.38#ibcon#wrote, iclass 16, count 0 2006.280.07:34:42.38#ibcon#about to read 3, iclass 16, count 0 2006.280.07:34:42.40#ibcon#read 3, iclass 16, count 0 2006.280.07:34:42.40#ibcon#about to read 4, iclass 16, count 0 2006.280.07:34:42.40#ibcon#read 4, iclass 16, count 0 2006.280.07:34:42.40#ibcon#about to read 5, iclass 16, count 0 2006.280.07:34:42.40#ibcon#read 5, iclass 16, count 0 2006.280.07:34:42.40#ibcon#about to read 6, iclass 16, count 0 2006.280.07:34:42.40#ibcon#read 6, iclass 16, count 0 2006.280.07:34:42.40#ibcon#end of sib2, iclass 16, count 0 2006.280.07:34:42.40#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:34:42.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:34:42.40#ibcon#[27=USB\r\n] 2006.280.07:34:42.40#ibcon#*before write, iclass 16, count 0 2006.280.07:34:42.40#ibcon#enter sib2, iclass 16, count 0 2006.280.07:34:42.40#ibcon#flushed, iclass 16, count 0 2006.280.07:34:42.40#ibcon#about to write, iclass 16, count 0 2006.280.07:34:42.40#ibcon#wrote, iclass 16, count 0 2006.280.07:34:42.40#ibcon#about to read 3, iclass 16, count 0 2006.280.07:34:42.43#ibcon#read 3, iclass 16, count 0 2006.280.07:34:42.43#ibcon#about to read 4, iclass 16, count 0 2006.280.07:34:42.43#ibcon#read 4, iclass 16, count 0 2006.280.07:34:42.43#ibcon#about to read 5, iclass 16, count 0 2006.280.07:34:42.43#ibcon#read 5, iclass 16, count 0 2006.280.07:34:42.43#ibcon#about to read 6, iclass 16, count 0 2006.280.07:34:42.43#ibcon#read 6, iclass 16, count 0 2006.280.07:34:42.43#ibcon#end of sib2, iclass 16, count 0 2006.280.07:34:42.43#ibcon#*after write, iclass 16, count 0 2006.280.07:34:42.43#ibcon#*before return 0, iclass 16, count 0 2006.280.07:34:42.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:42.43#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:34:42.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:34:42.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:34:42.43$vc4f8/vblo=5,744.99 2006.280.07:34:42.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:34:42.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:34:42.43#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:42.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:42.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:42.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:42.43#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:34:42.43#ibcon#first serial, iclass 18, count 0 2006.280.07:34:42.43#ibcon#enter sib2, iclass 18, count 0 2006.280.07:34:42.43#ibcon#flushed, iclass 18, count 0 2006.280.07:34:42.43#ibcon#about to write, iclass 18, count 0 2006.280.07:34:42.43#ibcon#wrote, iclass 18, count 0 2006.280.07:34:42.43#ibcon#about to read 3, iclass 18, count 0 2006.280.07:34:42.45#ibcon#read 3, iclass 18, count 0 2006.280.07:34:42.45#ibcon#about to read 4, iclass 18, count 0 2006.280.07:34:42.45#ibcon#read 4, iclass 18, count 0 2006.280.07:34:42.45#ibcon#about to read 5, iclass 18, count 0 2006.280.07:34:42.45#ibcon#read 5, iclass 18, count 0 2006.280.07:34:42.45#ibcon#about to read 6, iclass 18, count 0 2006.280.07:34:42.45#ibcon#read 6, iclass 18, count 0 2006.280.07:34:42.45#ibcon#end of sib2, iclass 18, count 0 2006.280.07:34:42.45#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:34:42.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:34:42.45#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:34:42.45#ibcon#*before write, iclass 18, count 0 2006.280.07:34:42.45#ibcon#enter sib2, iclass 18, count 0 2006.280.07:34:42.45#ibcon#flushed, iclass 18, count 0 2006.280.07:34:42.45#ibcon#about to write, iclass 18, count 0 2006.280.07:34:42.45#ibcon#wrote, iclass 18, count 0 2006.280.07:34:42.45#ibcon#about to read 3, iclass 18, count 0 2006.280.07:34:42.49#ibcon#read 3, iclass 18, count 0 2006.280.07:34:42.49#ibcon#about to read 4, iclass 18, count 0 2006.280.07:34:42.49#ibcon#read 4, iclass 18, count 0 2006.280.07:34:42.49#ibcon#about to read 5, iclass 18, count 0 2006.280.07:34:42.49#ibcon#read 5, iclass 18, count 0 2006.280.07:34:42.49#ibcon#about to read 6, iclass 18, count 0 2006.280.07:34:42.49#ibcon#read 6, iclass 18, count 0 2006.280.07:34:42.49#ibcon#end of sib2, iclass 18, count 0 2006.280.07:34:42.49#ibcon#*after write, iclass 18, count 0 2006.280.07:34:42.49#ibcon#*before return 0, iclass 18, count 0 2006.280.07:34:42.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:42.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:34:42.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:34:42.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:34:42.49$vc4f8/vb=5,4 2006.280.07:34:42.49#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:34:42.49#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:34:42.49#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:42.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:42.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:42.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:42.55#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:34:42.55#ibcon#first serial, iclass 20, count 2 2006.280.07:34:42.55#ibcon#enter sib2, iclass 20, count 2 2006.280.07:34:42.55#ibcon#flushed, iclass 20, count 2 2006.280.07:34:42.55#ibcon#about to write, iclass 20, count 2 2006.280.07:34:42.55#ibcon#wrote, iclass 20, count 2 2006.280.07:34:42.55#ibcon#about to read 3, iclass 20, count 2 2006.280.07:34:42.57#ibcon#read 3, iclass 20, count 2 2006.280.07:34:42.57#ibcon#about to read 4, iclass 20, count 2 2006.280.07:34:42.57#ibcon#read 4, iclass 20, count 2 2006.280.07:34:42.57#ibcon#about to read 5, iclass 20, count 2 2006.280.07:34:42.57#ibcon#read 5, iclass 20, count 2 2006.280.07:34:42.57#ibcon#about to read 6, iclass 20, count 2 2006.280.07:34:42.57#ibcon#read 6, iclass 20, count 2 2006.280.07:34:42.57#ibcon#end of sib2, iclass 20, count 2 2006.280.07:34:42.57#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:34:42.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:34:42.57#ibcon#[27=AT05-04\r\n] 2006.280.07:34:42.57#ibcon#*before write, iclass 20, count 2 2006.280.07:34:42.57#ibcon#enter sib2, iclass 20, count 2 2006.280.07:34:42.57#ibcon#flushed, iclass 20, count 2 2006.280.07:34:42.57#ibcon#about to write, iclass 20, count 2 2006.280.07:34:42.57#ibcon#wrote, iclass 20, count 2 2006.280.07:34:42.57#ibcon#about to read 3, iclass 20, count 2 2006.280.07:34:42.60#ibcon#read 3, iclass 20, count 2 2006.280.07:34:42.60#ibcon#about to read 4, iclass 20, count 2 2006.280.07:34:42.60#ibcon#read 4, iclass 20, count 2 2006.280.07:34:42.60#ibcon#about to read 5, iclass 20, count 2 2006.280.07:34:42.60#ibcon#read 5, iclass 20, count 2 2006.280.07:34:42.60#ibcon#about to read 6, iclass 20, count 2 2006.280.07:34:42.60#ibcon#read 6, iclass 20, count 2 2006.280.07:34:42.60#ibcon#end of sib2, iclass 20, count 2 2006.280.07:34:42.60#ibcon#*after write, iclass 20, count 2 2006.280.07:34:42.60#ibcon#*before return 0, iclass 20, count 2 2006.280.07:34:42.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:42.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:34:42.60#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:34:42.60#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:42.60#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:42.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:42.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:42.72#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:34:42.72#ibcon#first serial, iclass 20, count 0 2006.280.07:34:42.72#ibcon#enter sib2, iclass 20, count 0 2006.280.07:34:42.72#ibcon#flushed, iclass 20, count 0 2006.280.07:34:42.72#ibcon#about to write, iclass 20, count 0 2006.280.07:34:42.72#ibcon#wrote, iclass 20, count 0 2006.280.07:34:42.72#ibcon#about to read 3, iclass 20, count 0 2006.280.07:34:42.74#ibcon#read 3, iclass 20, count 0 2006.280.07:34:42.74#ibcon#about to read 4, iclass 20, count 0 2006.280.07:34:42.74#ibcon#read 4, iclass 20, count 0 2006.280.07:34:42.74#ibcon#about to read 5, iclass 20, count 0 2006.280.07:34:42.74#ibcon#read 5, iclass 20, count 0 2006.280.07:34:42.74#ibcon#about to read 6, iclass 20, count 0 2006.280.07:34:42.74#ibcon#read 6, iclass 20, count 0 2006.280.07:34:42.74#ibcon#end of sib2, iclass 20, count 0 2006.280.07:34:42.74#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:34:42.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:34:42.74#ibcon#[27=USB\r\n] 2006.280.07:34:42.74#ibcon#*before write, iclass 20, count 0 2006.280.07:34:42.74#ibcon#enter sib2, iclass 20, count 0 2006.280.07:34:42.74#ibcon#flushed, iclass 20, count 0 2006.280.07:34:42.74#ibcon#about to write, iclass 20, count 0 2006.280.07:34:42.74#ibcon#wrote, iclass 20, count 0 2006.280.07:34:42.74#ibcon#about to read 3, iclass 20, count 0 2006.280.07:34:42.77#ibcon#read 3, iclass 20, count 0 2006.280.07:34:42.77#ibcon#about to read 4, iclass 20, count 0 2006.280.07:34:42.77#ibcon#read 4, iclass 20, count 0 2006.280.07:34:42.77#ibcon#about to read 5, iclass 20, count 0 2006.280.07:34:42.77#ibcon#read 5, iclass 20, count 0 2006.280.07:34:42.77#ibcon#about to read 6, iclass 20, count 0 2006.280.07:34:42.77#ibcon#read 6, iclass 20, count 0 2006.280.07:34:42.77#ibcon#end of sib2, iclass 20, count 0 2006.280.07:34:42.77#ibcon#*after write, iclass 20, count 0 2006.280.07:34:42.77#ibcon#*before return 0, iclass 20, count 0 2006.280.07:34:42.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:42.77#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:34:42.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:34:42.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:34:42.77$vc4f8/vblo=6,752.99 2006.280.07:34:42.77#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.07:34:42.77#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.07:34:42.77#ibcon#ireg 17 cls_cnt 0 2006.280.07:34:42.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:34:42.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:34:42.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:34:42.77#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:34:42.77#ibcon#first serial, iclass 22, count 0 2006.280.07:34:42.77#ibcon#enter sib2, iclass 22, count 0 2006.280.07:34:42.77#ibcon#flushed, iclass 22, count 0 2006.280.07:34:42.77#ibcon#about to write, iclass 22, count 0 2006.280.07:34:42.77#ibcon#wrote, iclass 22, count 0 2006.280.07:34:42.77#ibcon#about to read 3, iclass 22, count 0 2006.280.07:34:42.79#ibcon#read 3, iclass 22, count 0 2006.280.07:34:42.79#ibcon#about to read 4, iclass 22, count 0 2006.280.07:34:42.79#ibcon#read 4, iclass 22, count 0 2006.280.07:34:42.79#ibcon#about to read 5, iclass 22, count 0 2006.280.07:34:42.79#ibcon#read 5, iclass 22, count 0 2006.280.07:34:42.79#ibcon#about to read 6, iclass 22, count 0 2006.280.07:34:42.79#ibcon#read 6, iclass 22, count 0 2006.280.07:34:42.79#ibcon#end of sib2, iclass 22, count 0 2006.280.07:34:42.79#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:34:42.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:34:42.79#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:34:42.79#ibcon#*before write, iclass 22, count 0 2006.280.07:34:42.79#ibcon#enter sib2, iclass 22, count 0 2006.280.07:34:42.79#ibcon#flushed, iclass 22, count 0 2006.280.07:34:42.79#ibcon#about to write, iclass 22, count 0 2006.280.07:34:42.79#ibcon#wrote, iclass 22, count 0 2006.280.07:34:42.79#ibcon#about to read 3, iclass 22, count 0 2006.280.07:34:42.83#ibcon#read 3, iclass 22, count 0 2006.280.07:34:42.83#ibcon#about to read 4, iclass 22, count 0 2006.280.07:34:42.83#ibcon#read 4, iclass 22, count 0 2006.280.07:34:42.83#ibcon#about to read 5, iclass 22, count 0 2006.280.07:34:42.83#ibcon#read 5, iclass 22, count 0 2006.280.07:34:42.83#ibcon#about to read 6, iclass 22, count 0 2006.280.07:34:42.83#ibcon#read 6, iclass 22, count 0 2006.280.07:34:42.83#ibcon#end of sib2, iclass 22, count 0 2006.280.07:34:42.83#ibcon#*after write, iclass 22, count 0 2006.280.07:34:42.83#ibcon#*before return 0, iclass 22, count 0 2006.280.07:34:42.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:34:42.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:34:42.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:34:42.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:34:42.83$vc4f8/vb=6,4 2006.280.07:34:42.83#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.07:34:42.83#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.07:34:42.83#ibcon#ireg 11 cls_cnt 2 2006.280.07:34:42.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:34:42.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:34:42.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:34:42.89#ibcon#enter wrdev, iclass 24, count 2 2006.280.07:34:42.89#ibcon#first serial, iclass 24, count 2 2006.280.07:34:42.89#ibcon#enter sib2, iclass 24, count 2 2006.280.07:34:42.89#ibcon#flushed, iclass 24, count 2 2006.280.07:34:42.89#ibcon#about to write, iclass 24, count 2 2006.280.07:34:42.89#ibcon#wrote, iclass 24, count 2 2006.280.07:34:42.89#ibcon#about to read 3, iclass 24, count 2 2006.280.07:34:42.91#ibcon#read 3, iclass 24, count 2 2006.280.07:34:42.91#ibcon#about to read 4, iclass 24, count 2 2006.280.07:34:42.91#ibcon#read 4, iclass 24, count 2 2006.280.07:34:42.91#ibcon#about to read 5, iclass 24, count 2 2006.280.07:34:42.91#ibcon#read 5, iclass 24, count 2 2006.280.07:34:42.91#ibcon#about to read 6, iclass 24, count 2 2006.280.07:34:42.91#ibcon#read 6, iclass 24, count 2 2006.280.07:34:42.91#ibcon#end of sib2, iclass 24, count 2 2006.280.07:34:42.91#ibcon#*mode == 0, iclass 24, count 2 2006.280.07:34:42.91#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.07:34:42.91#ibcon#[27=AT06-04\r\n] 2006.280.07:34:42.91#ibcon#*before write, iclass 24, count 2 2006.280.07:34:42.91#ibcon#enter sib2, iclass 24, count 2 2006.280.07:34:42.91#ibcon#flushed, iclass 24, count 2 2006.280.07:34:42.91#ibcon#about to write, iclass 24, count 2 2006.280.07:34:42.91#ibcon#wrote, iclass 24, count 2 2006.280.07:34:42.91#ibcon#about to read 3, iclass 24, count 2 2006.280.07:34:42.94#ibcon#read 3, iclass 24, count 2 2006.280.07:34:42.94#ibcon#about to read 4, iclass 24, count 2 2006.280.07:34:42.94#ibcon#read 4, iclass 24, count 2 2006.280.07:34:42.94#ibcon#about to read 5, iclass 24, count 2 2006.280.07:34:42.94#ibcon#read 5, iclass 24, count 2 2006.280.07:34:42.94#ibcon#about to read 6, iclass 24, count 2 2006.280.07:34:42.94#ibcon#read 6, iclass 24, count 2 2006.280.07:34:42.94#ibcon#end of sib2, iclass 24, count 2 2006.280.07:34:42.94#ibcon#*after write, iclass 24, count 2 2006.280.07:34:42.94#ibcon#*before return 0, iclass 24, count 2 2006.280.07:34:42.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:34:42.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:34:42.94#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.07:34:42.94#ibcon#ireg 7 cls_cnt 0 2006.280.07:34:42.94#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:34:43.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:34:43.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:34:43.06#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:34:43.06#ibcon#first serial, iclass 24, count 0 2006.280.07:34:43.06#ibcon#enter sib2, iclass 24, count 0 2006.280.07:34:43.06#ibcon#flushed, iclass 24, count 0 2006.280.07:34:43.06#ibcon#about to write, iclass 24, count 0 2006.280.07:34:43.06#ibcon#wrote, iclass 24, count 0 2006.280.07:34:43.06#ibcon#about to read 3, iclass 24, count 0 2006.280.07:34:43.08#ibcon#read 3, iclass 24, count 0 2006.280.07:34:43.08#ibcon#about to read 4, iclass 24, count 0 2006.280.07:34:43.08#ibcon#read 4, iclass 24, count 0 2006.280.07:34:43.08#ibcon#about to read 5, iclass 24, count 0 2006.280.07:34:43.08#ibcon#read 5, iclass 24, count 0 2006.280.07:34:43.08#ibcon#about to read 6, iclass 24, count 0 2006.280.07:34:43.08#ibcon#read 6, iclass 24, count 0 2006.280.07:34:43.08#ibcon#end of sib2, iclass 24, count 0 2006.280.07:34:43.08#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:34:43.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:34:43.08#ibcon#[27=USB\r\n] 2006.280.07:34:43.08#ibcon#*before write, iclass 24, count 0 2006.280.07:34:43.08#ibcon#enter sib2, iclass 24, count 0 2006.280.07:34:43.08#ibcon#flushed, iclass 24, count 0 2006.280.07:34:43.08#ibcon#about to write, iclass 24, count 0 2006.280.07:34:43.08#ibcon#wrote, iclass 24, count 0 2006.280.07:34:43.08#ibcon#about to read 3, iclass 24, count 0 2006.280.07:34:43.11#ibcon#read 3, iclass 24, count 0 2006.280.07:34:43.11#ibcon#about to read 4, iclass 24, count 0 2006.280.07:34:43.11#ibcon#read 4, iclass 24, count 0 2006.280.07:34:43.11#ibcon#about to read 5, iclass 24, count 0 2006.280.07:34:43.11#ibcon#read 5, iclass 24, count 0 2006.280.07:34:43.11#ibcon#about to read 6, iclass 24, count 0 2006.280.07:34:43.11#ibcon#read 6, iclass 24, count 0 2006.280.07:34:43.11#ibcon#end of sib2, iclass 24, count 0 2006.280.07:34:43.11#ibcon#*after write, iclass 24, count 0 2006.280.07:34:43.11#ibcon#*before return 0, iclass 24, count 0 2006.280.07:34:43.11#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:34:43.11#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:34:43.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:34:43.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:34:43.11$vc4f8/vabw=wide 2006.280.07:34:43.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:34:43.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:34:43.11#ibcon#ireg 8 cls_cnt 0 2006.280.07:34:43.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:43.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:43.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:43.11#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:34:43.11#ibcon#first serial, iclass 26, count 0 2006.280.07:34:43.11#ibcon#enter sib2, iclass 26, count 0 2006.280.07:34:43.11#ibcon#flushed, iclass 26, count 0 2006.280.07:34:43.11#ibcon#about to write, iclass 26, count 0 2006.280.07:34:43.11#ibcon#wrote, iclass 26, count 0 2006.280.07:34:43.11#ibcon#about to read 3, iclass 26, count 0 2006.280.07:34:43.13#ibcon#read 3, iclass 26, count 0 2006.280.07:34:43.13#ibcon#about to read 4, iclass 26, count 0 2006.280.07:34:43.13#ibcon#read 4, iclass 26, count 0 2006.280.07:34:43.13#ibcon#about to read 5, iclass 26, count 0 2006.280.07:34:43.13#ibcon#read 5, iclass 26, count 0 2006.280.07:34:43.13#ibcon#about to read 6, iclass 26, count 0 2006.280.07:34:43.13#ibcon#read 6, iclass 26, count 0 2006.280.07:34:43.13#ibcon#end of sib2, iclass 26, count 0 2006.280.07:34:43.13#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:34:43.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:34:43.13#ibcon#[25=BW32\r\n] 2006.280.07:34:43.13#ibcon#*before write, iclass 26, count 0 2006.280.07:34:43.13#ibcon#enter sib2, iclass 26, count 0 2006.280.07:34:43.13#ibcon#flushed, iclass 26, count 0 2006.280.07:34:43.13#ibcon#about to write, iclass 26, count 0 2006.280.07:34:43.13#ibcon#wrote, iclass 26, count 0 2006.280.07:34:43.13#ibcon#about to read 3, iclass 26, count 0 2006.280.07:34:43.16#ibcon#read 3, iclass 26, count 0 2006.280.07:34:43.16#ibcon#about to read 4, iclass 26, count 0 2006.280.07:34:43.16#ibcon#read 4, iclass 26, count 0 2006.280.07:34:43.16#ibcon#about to read 5, iclass 26, count 0 2006.280.07:34:43.16#ibcon#read 5, iclass 26, count 0 2006.280.07:34:43.16#ibcon#about to read 6, iclass 26, count 0 2006.280.07:34:43.16#ibcon#read 6, iclass 26, count 0 2006.280.07:34:43.16#ibcon#end of sib2, iclass 26, count 0 2006.280.07:34:43.16#ibcon#*after write, iclass 26, count 0 2006.280.07:34:43.16#ibcon#*before return 0, iclass 26, count 0 2006.280.07:34:43.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:43.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:34:43.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:34:43.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:34:43.16$vc4f8/vbbw=wide 2006.280.07:34:43.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.07:34:43.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.07:34:43.16#ibcon#ireg 8 cls_cnt 0 2006.280.07:34:43.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:34:43.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:34:43.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:34:43.23#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:34:43.23#ibcon#first serial, iclass 28, count 0 2006.280.07:34:43.23#ibcon#enter sib2, iclass 28, count 0 2006.280.07:34:43.23#ibcon#flushed, iclass 28, count 0 2006.280.07:34:43.23#ibcon#about to write, iclass 28, count 0 2006.280.07:34:43.23#ibcon#wrote, iclass 28, count 0 2006.280.07:34:43.23#ibcon#about to read 3, iclass 28, count 0 2006.280.07:34:43.25#ibcon#read 3, iclass 28, count 0 2006.280.07:34:43.25#ibcon#about to read 4, iclass 28, count 0 2006.280.07:34:43.25#ibcon#read 4, iclass 28, count 0 2006.280.07:34:43.25#ibcon#about to read 5, iclass 28, count 0 2006.280.07:34:43.25#ibcon#read 5, iclass 28, count 0 2006.280.07:34:43.25#ibcon#about to read 6, iclass 28, count 0 2006.280.07:34:43.25#ibcon#read 6, iclass 28, count 0 2006.280.07:34:43.25#ibcon#end of sib2, iclass 28, count 0 2006.280.07:34:43.25#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:34:43.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:34:43.25#ibcon#[27=BW32\r\n] 2006.280.07:34:43.25#ibcon#*before write, iclass 28, count 0 2006.280.07:34:43.25#ibcon#enter sib2, iclass 28, count 0 2006.280.07:34:43.25#ibcon#flushed, iclass 28, count 0 2006.280.07:34:43.25#ibcon#about to write, iclass 28, count 0 2006.280.07:34:43.25#ibcon#wrote, iclass 28, count 0 2006.280.07:34:43.25#ibcon#about to read 3, iclass 28, count 0 2006.280.07:34:43.28#ibcon#read 3, iclass 28, count 0 2006.280.07:34:43.28#ibcon#about to read 4, iclass 28, count 0 2006.280.07:34:43.28#ibcon#read 4, iclass 28, count 0 2006.280.07:34:43.28#ibcon#about to read 5, iclass 28, count 0 2006.280.07:34:43.28#ibcon#read 5, iclass 28, count 0 2006.280.07:34:43.28#ibcon#about to read 6, iclass 28, count 0 2006.280.07:34:43.28#ibcon#read 6, iclass 28, count 0 2006.280.07:34:43.28#ibcon#end of sib2, iclass 28, count 0 2006.280.07:34:43.28#ibcon#*after write, iclass 28, count 0 2006.280.07:34:43.28#ibcon#*before return 0, iclass 28, count 0 2006.280.07:34:43.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:34:43.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:34:43.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:34:43.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:34:43.28$4f8m12a/ifd4f 2006.280.07:34:43.28$ifd4f/lo= 2006.280.07:34:43.28$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:34:43.28$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:34:43.28$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:34:43.28$ifd4f/patch= 2006.280.07:34:43.28$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:34:43.28$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:34:43.28$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:34:43.28$4f8m12a/"form=m,16.000,1:2 2006.280.07:34:43.28$4f8m12a/"tpicd 2006.280.07:34:43.28$4f8m12a/echo=off 2006.280.07:34:43.28$4f8m12a/xlog=off 2006.280.07:34:43.28:!2006.280.07:35:10 2006.280.07:34:54.13#trakl#Source acquired 2006.280.07:34:55.13#flagr#flagr/antenna,acquired 2006.280.07:35:10.00:preob 2006.280.07:35:11.13/onsource/TRACKING 2006.280.07:35:11.13:!2006.280.07:35:20 2006.280.07:35:20.00:data_valid=on 2006.280.07:35:20.00:midob 2006.280.07:35:20.13/onsource/TRACKING 2006.280.07:35:20.13/wx/22.02,986.6,58 2006.280.07:35:20.23/cable/+6.4826E-03 2006.280.07:35:21.32/va/01,07,usb,yes,32,34 2006.280.07:35:21.32/va/02,06,usb,yes,30,31 2006.280.07:35:21.32/va/03,06,usb,yes,28,28 2006.280.07:35:21.32/va/04,06,usb,yes,31,34 2006.280.07:35:21.32/va/05,07,usb,yes,28,30 2006.280.07:35:21.32/va/06,06,usb,yes,27,27 2006.280.07:35:21.32/va/07,06,usb,yes,28,27 2006.280.07:35:21.32/va/08,06,usb,yes,29,29 2006.280.07:35:21.55/valo/01,532.99,yes,locked 2006.280.07:35:21.55/valo/02,572.99,yes,locked 2006.280.07:35:21.55/valo/03,672.99,yes,locked 2006.280.07:35:21.55/valo/04,832.99,yes,locked 2006.280.07:35:21.55/valo/05,652.99,yes,locked 2006.280.07:35:21.55/valo/06,772.99,yes,locked 2006.280.07:35:21.55/valo/07,832.99,yes,locked 2006.280.07:35:21.55/valo/08,852.99,yes,locked 2006.280.07:35:22.64/vb/01,04,usb,yes,30,29 2006.280.07:35:22.64/vb/02,05,usb,yes,28,29 2006.280.07:35:22.64/vb/03,04,usb,yes,28,32 2006.280.07:35:22.64/vb/04,04,usb,yes,29,29 2006.280.07:35:22.64/vb/05,04,usb,yes,27,31 2006.280.07:35:22.64/vb/06,04,usb,yes,28,31 2006.280.07:35:22.64/vb/07,04,usb,yes,30,30 2006.280.07:35:22.64/vb/08,04,usb,yes,28,31 2006.280.07:35:22.87/vblo/01,632.99,yes,locked 2006.280.07:35:22.87/vblo/02,640.99,yes,locked 2006.280.07:35:22.87/vblo/03,656.99,yes,locked 2006.280.07:35:22.87/vblo/04,712.99,yes,locked 2006.280.07:35:22.87/vblo/05,744.99,yes,locked 2006.280.07:35:22.87/vblo/06,752.99,yes,locked 2006.280.07:35:22.87/vblo/07,734.99,yes,locked 2006.280.07:35:22.87/vblo/08,744.99,yes,locked 2006.280.07:35:23.02/vabw/8 2006.280.07:35:23.17/vbbw/8 2006.280.07:35:23.26/xfe/off,on,12.2 2006.280.07:35:23.63/ifatt/23,28,28,28 2006.280.07:35:24.08/fmout-gps/S +2.94E-07 2006.280.07:35:24.10:!2006.280.07:36:20 2006.280.07:36:20.01:data_valid=off 2006.280.07:36:20.01:postob 2006.280.07:36:20.10/cable/+6.4828E-03 2006.280.07:36:20.10/wx/21.96,986.7,60 2006.280.07:36:21.08/fmout-gps/S +2.94E-07 2006.280.07:36:21.08:scan_name=280-0737,k06280,60 2006.280.07:36:21.08:source=1739+522,174036.98,521143.4,2000.0,ccw 2006.280.07:36:21.14#flagr#flagr/antenna,new-source 2006.280.07:36:22.14:checkk5 2006.280.07:36:22.55/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:36:22.93/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:36:23.32/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:36:23.79/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:36:24.16/chk_obsdata//k5ts1/T2800735??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:36:24.58/chk_obsdata//k5ts2/T2800735??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:36:24.96/chk_obsdata//k5ts3/T2800735??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:36:25.34/chk_obsdata//k5ts4/T2800735??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:36:26.15/k5log//k5ts1_log_newline 2006.280.07:36:26.85/k5log//k5ts2_log_newline 2006.280.07:36:27.64/k5log//k5ts3_log_newline 2006.280.07:36:28.44/k5log//k5ts4_log_newline 2006.280.07:36:28.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:36:28.47:4f8m12a=1 2006.280.07:36:28.47$4f8m12a/echo=on 2006.280.07:36:28.47$4f8m12a/pcalon 2006.280.07:36:28.47$pcalon/"no phase cal control is implemented here 2006.280.07:36:28.47$4f8m12a/"tpicd=stop 2006.280.07:36:28.47$4f8m12a/vc4f8 2006.280.07:36:28.47$vc4f8/valo=1,532.99 2006.280.07:36:28.47#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.07:36:28.47#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.07:36:28.47#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:28.47#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:28.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:28.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:28.47#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:36:28.47#ibcon#first serial, iclass 35, count 0 2006.280.07:36:28.47#ibcon#enter sib2, iclass 35, count 0 2006.280.07:36:28.47#ibcon#flushed, iclass 35, count 0 2006.280.07:36:28.47#ibcon#about to write, iclass 35, count 0 2006.280.07:36:28.47#ibcon#wrote, iclass 35, count 0 2006.280.07:36:28.47#ibcon#about to read 3, iclass 35, count 0 2006.280.07:36:28.49#ibcon#read 3, iclass 35, count 0 2006.280.07:36:28.49#ibcon#about to read 4, iclass 35, count 0 2006.280.07:36:28.49#ibcon#read 4, iclass 35, count 0 2006.280.07:36:28.49#ibcon#about to read 5, iclass 35, count 0 2006.280.07:36:28.49#ibcon#read 5, iclass 35, count 0 2006.280.07:36:28.49#ibcon#about to read 6, iclass 35, count 0 2006.280.07:36:28.49#ibcon#read 6, iclass 35, count 0 2006.280.07:36:28.49#ibcon#end of sib2, iclass 35, count 0 2006.280.07:36:28.49#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:36:28.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:36:28.49#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:36:28.49#ibcon#*before write, iclass 35, count 0 2006.280.07:36:28.49#ibcon#enter sib2, iclass 35, count 0 2006.280.07:36:28.49#ibcon#flushed, iclass 35, count 0 2006.280.07:36:28.49#ibcon#about to write, iclass 35, count 0 2006.280.07:36:28.49#ibcon#wrote, iclass 35, count 0 2006.280.07:36:28.49#ibcon#about to read 3, iclass 35, count 0 2006.280.07:36:28.54#ibcon#read 3, iclass 35, count 0 2006.280.07:36:28.54#ibcon#about to read 4, iclass 35, count 0 2006.280.07:36:28.54#ibcon#read 4, iclass 35, count 0 2006.280.07:36:28.54#ibcon#about to read 5, iclass 35, count 0 2006.280.07:36:28.54#ibcon#read 5, iclass 35, count 0 2006.280.07:36:28.54#ibcon#about to read 6, iclass 35, count 0 2006.280.07:36:28.54#ibcon#read 6, iclass 35, count 0 2006.280.07:36:28.54#ibcon#end of sib2, iclass 35, count 0 2006.280.07:36:28.54#ibcon#*after write, iclass 35, count 0 2006.280.07:36:28.54#ibcon#*before return 0, iclass 35, count 0 2006.280.07:36:28.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:28.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:28.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:36:28.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:36:28.54$vc4f8/va=1,7 2006.280.07:36:28.54#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.07:36:28.54#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.07:36:28.54#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:28.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:28.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:28.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:28.54#ibcon#enter wrdev, iclass 37, count 2 2006.280.07:36:28.54#ibcon#first serial, iclass 37, count 2 2006.280.07:36:28.54#ibcon#enter sib2, iclass 37, count 2 2006.280.07:36:28.54#ibcon#flushed, iclass 37, count 2 2006.280.07:36:28.54#ibcon#about to write, iclass 37, count 2 2006.280.07:36:28.54#ibcon#wrote, iclass 37, count 2 2006.280.07:36:28.54#ibcon#about to read 3, iclass 37, count 2 2006.280.07:36:28.56#ibcon#read 3, iclass 37, count 2 2006.280.07:36:28.56#ibcon#about to read 4, iclass 37, count 2 2006.280.07:36:28.56#ibcon#read 4, iclass 37, count 2 2006.280.07:36:28.56#ibcon#about to read 5, iclass 37, count 2 2006.280.07:36:28.56#ibcon#read 5, iclass 37, count 2 2006.280.07:36:28.56#ibcon#about to read 6, iclass 37, count 2 2006.280.07:36:28.56#ibcon#read 6, iclass 37, count 2 2006.280.07:36:28.56#ibcon#end of sib2, iclass 37, count 2 2006.280.07:36:28.56#ibcon#*mode == 0, iclass 37, count 2 2006.280.07:36:28.56#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.07:36:28.56#ibcon#[25=AT01-07\r\n] 2006.280.07:36:28.56#ibcon#*before write, iclass 37, count 2 2006.280.07:36:28.56#ibcon#enter sib2, iclass 37, count 2 2006.280.07:36:28.56#ibcon#flushed, iclass 37, count 2 2006.280.07:36:28.56#ibcon#about to write, iclass 37, count 2 2006.280.07:36:28.56#ibcon#wrote, iclass 37, count 2 2006.280.07:36:28.59#ibcon#about to read 3, iclass 37, count 2 2006.280.07:36:28.59#ibcon#read 3, iclass 37, count 2 2006.280.07:36:28.59#ibcon#about to read 4, iclass 37, count 2 2006.280.07:36:28.59#ibcon#read 4, iclass 37, count 2 2006.280.07:36:28.59#ibcon#about to read 5, iclass 37, count 2 2006.280.07:36:28.59#ibcon#read 5, iclass 37, count 2 2006.280.07:36:28.59#ibcon#about to read 6, iclass 37, count 2 2006.280.07:36:28.59#ibcon#read 6, iclass 37, count 2 2006.280.07:36:28.59#ibcon#end of sib2, iclass 37, count 2 2006.280.07:36:28.60#ibcon#*after write, iclass 37, count 2 2006.280.07:36:28.60#ibcon#*before return 0, iclass 37, count 2 2006.280.07:36:28.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:28.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:28.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.07:36:28.60#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:28.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:28.71#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:28.71#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:28.71#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:36:28.71#ibcon#first serial, iclass 37, count 0 2006.280.07:36:28.71#ibcon#enter sib2, iclass 37, count 0 2006.280.07:36:28.71#ibcon#flushed, iclass 37, count 0 2006.280.07:36:28.71#ibcon#about to write, iclass 37, count 0 2006.280.07:36:28.71#ibcon#wrote, iclass 37, count 0 2006.280.07:36:28.71#ibcon#about to read 3, iclass 37, count 0 2006.280.07:36:28.73#ibcon#read 3, iclass 37, count 0 2006.280.07:36:28.73#ibcon#about to read 4, iclass 37, count 0 2006.280.07:36:28.73#ibcon#read 4, iclass 37, count 0 2006.280.07:36:28.73#ibcon#about to read 5, iclass 37, count 0 2006.280.07:36:28.73#ibcon#read 5, iclass 37, count 0 2006.280.07:36:28.73#ibcon#about to read 6, iclass 37, count 0 2006.280.07:36:28.73#ibcon#read 6, iclass 37, count 0 2006.280.07:36:28.73#ibcon#end of sib2, iclass 37, count 0 2006.280.07:36:28.73#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:36:28.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:36:28.73#ibcon#[25=USB\r\n] 2006.280.07:36:28.73#ibcon#*before write, iclass 37, count 0 2006.280.07:36:28.73#ibcon#enter sib2, iclass 37, count 0 2006.280.07:36:28.73#ibcon#flushed, iclass 37, count 0 2006.280.07:36:28.73#ibcon#about to write, iclass 37, count 0 2006.280.07:36:28.73#ibcon#wrote, iclass 37, count 0 2006.280.07:36:28.73#ibcon#about to read 3, iclass 37, count 0 2006.280.07:36:28.76#ibcon#read 3, iclass 37, count 0 2006.280.07:36:28.76#ibcon#about to read 4, iclass 37, count 0 2006.280.07:36:28.76#ibcon#read 4, iclass 37, count 0 2006.280.07:36:28.76#ibcon#about to read 5, iclass 37, count 0 2006.280.07:36:28.76#ibcon#read 5, iclass 37, count 0 2006.280.07:36:28.76#ibcon#about to read 6, iclass 37, count 0 2006.280.07:36:28.76#ibcon#read 6, iclass 37, count 0 2006.280.07:36:28.76#ibcon#end of sib2, iclass 37, count 0 2006.280.07:36:28.76#ibcon#*after write, iclass 37, count 0 2006.280.07:36:28.76#ibcon#*before return 0, iclass 37, count 0 2006.280.07:36:28.76#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:28.76#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:28.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:36:28.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:36:28.76$vc4f8/valo=2,572.99 2006.280.07:36:28.76#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:36:28.76#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:36:28.76#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:28.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:36:28.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:36:28.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:36:28.76#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:36:28.76#ibcon#first serial, iclass 39, count 0 2006.280.07:36:28.76#ibcon#enter sib2, iclass 39, count 0 2006.280.07:36:28.76#ibcon#flushed, iclass 39, count 0 2006.280.07:36:28.76#ibcon#about to write, iclass 39, count 0 2006.280.07:36:28.76#ibcon#wrote, iclass 39, count 0 2006.280.07:36:28.76#ibcon#about to read 3, iclass 39, count 0 2006.280.07:36:28.78#ibcon#read 3, iclass 39, count 0 2006.280.07:36:28.78#ibcon#about to read 4, iclass 39, count 0 2006.280.07:36:28.78#ibcon#read 4, iclass 39, count 0 2006.280.07:36:28.78#ibcon#about to read 5, iclass 39, count 0 2006.280.07:36:28.78#ibcon#read 5, iclass 39, count 0 2006.280.07:36:28.78#ibcon#about to read 6, iclass 39, count 0 2006.280.07:36:28.78#ibcon#read 6, iclass 39, count 0 2006.280.07:36:28.78#ibcon#end of sib2, iclass 39, count 0 2006.280.07:36:28.78#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:36:28.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:36:28.78#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:36:28.78#ibcon#*before write, iclass 39, count 0 2006.280.07:36:28.78#ibcon#enter sib2, iclass 39, count 0 2006.280.07:36:28.78#ibcon#flushed, iclass 39, count 0 2006.280.07:36:28.78#ibcon#about to write, iclass 39, count 0 2006.280.07:36:28.78#ibcon#wrote, iclass 39, count 0 2006.280.07:36:28.78#ibcon#about to read 3, iclass 39, count 0 2006.280.07:36:28.82#ibcon#read 3, iclass 39, count 0 2006.280.07:36:28.82#ibcon#about to read 4, iclass 39, count 0 2006.280.07:36:28.82#ibcon#read 4, iclass 39, count 0 2006.280.07:36:28.82#ibcon#about to read 5, iclass 39, count 0 2006.280.07:36:28.82#ibcon#read 5, iclass 39, count 0 2006.280.07:36:28.82#ibcon#about to read 6, iclass 39, count 0 2006.280.07:36:28.82#ibcon#read 6, iclass 39, count 0 2006.280.07:36:28.82#ibcon#end of sib2, iclass 39, count 0 2006.280.07:36:28.82#ibcon#*after write, iclass 39, count 0 2006.280.07:36:28.82#ibcon#*before return 0, iclass 39, count 0 2006.280.07:36:28.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:36:28.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:36:28.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:36:28.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:36:28.82$vc4f8/va=2,6 2006.280.07:36:28.82#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.07:36:28.82#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.07:36:28.82#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:28.82#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:36:28.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:36:28.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:36:28.88#ibcon#enter wrdev, iclass 3, count 2 2006.280.07:36:28.88#ibcon#first serial, iclass 3, count 2 2006.280.07:36:28.88#ibcon#enter sib2, iclass 3, count 2 2006.280.07:36:28.88#ibcon#flushed, iclass 3, count 2 2006.280.07:36:28.88#ibcon#about to write, iclass 3, count 2 2006.280.07:36:28.88#ibcon#wrote, iclass 3, count 2 2006.280.07:36:28.88#ibcon#about to read 3, iclass 3, count 2 2006.280.07:36:28.90#ibcon#read 3, iclass 3, count 2 2006.280.07:36:28.90#ibcon#about to read 4, iclass 3, count 2 2006.280.07:36:28.90#ibcon#read 4, iclass 3, count 2 2006.280.07:36:28.90#ibcon#about to read 5, iclass 3, count 2 2006.280.07:36:28.90#ibcon#read 5, iclass 3, count 2 2006.280.07:36:28.90#ibcon#about to read 6, iclass 3, count 2 2006.280.07:36:28.90#ibcon#read 6, iclass 3, count 2 2006.280.07:36:28.90#ibcon#end of sib2, iclass 3, count 2 2006.280.07:36:28.90#ibcon#*mode == 0, iclass 3, count 2 2006.280.07:36:28.90#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.07:36:28.90#ibcon#[25=AT02-06\r\n] 2006.280.07:36:28.90#ibcon#*before write, iclass 3, count 2 2006.280.07:36:28.90#ibcon#enter sib2, iclass 3, count 2 2006.280.07:36:28.90#ibcon#flushed, iclass 3, count 2 2006.280.07:36:28.90#ibcon#about to write, iclass 3, count 2 2006.280.07:36:28.90#ibcon#wrote, iclass 3, count 2 2006.280.07:36:28.90#ibcon#about to read 3, iclass 3, count 2 2006.280.07:36:28.93#ibcon#read 3, iclass 3, count 2 2006.280.07:36:28.93#ibcon#about to read 4, iclass 3, count 2 2006.280.07:36:28.93#ibcon#read 4, iclass 3, count 2 2006.280.07:36:28.93#ibcon#about to read 5, iclass 3, count 2 2006.280.07:36:28.93#ibcon#read 5, iclass 3, count 2 2006.280.07:36:28.93#ibcon#about to read 6, iclass 3, count 2 2006.280.07:36:28.93#ibcon#read 6, iclass 3, count 2 2006.280.07:36:28.93#ibcon#end of sib2, iclass 3, count 2 2006.280.07:36:28.93#ibcon#*after write, iclass 3, count 2 2006.280.07:36:28.93#ibcon#*before return 0, iclass 3, count 2 2006.280.07:36:28.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:36:28.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:36:28.94#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.07:36:28.94#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:28.94#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:36:29.05#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:36:29.05#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:36:29.05#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:36:29.05#ibcon#first serial, iclass 3, count 0 2006.280.07:36:29.05#ibcon#enter sib2, iclass 3, count 0 2006.280.07:36:29.05#ibcon#flushed, iclass 3, count 0 2006.280.07:36:29.05#ibcon#about to write, iclass 3, count 0 2006.280.07:36:29.05#ibcon#wrote, iclass 3, count 0 2006.280.07:36:29.05#ibcon#about to read 3, iclass 3, count 0 2006.280.07:36:29.07#ibcon#read 3, iclass 3, count 0 2006.280.07:36:29.07#ibcon#about to read 4, iclass 3, count 0 2006.280.07:36:29.07#ibcon#read 4, iclass 3, count 0 2006.280.07:36:29.07#ibcon#about to read 5, iclass 3, count 0 2006.280.07:36:29.07#ibcon#read 5, iclass 3, count 0 2006.280.07:36:29.07#ibcon#about to read 6, iclass 3, count 0 2006.280.07:36:29.07#ibcon#read 6, iclass 3, count 0 2006.280.07:36:29.07#ibcon#end of sib2, iclass 3, count 0 2006.280.07:36:29.07#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:36:29.07#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:36:29.07#ibcon#[25=USB\r\n] 2006.280.07:36:29.07#ibcon#*before write, iclass 3, count 0 2006.280.07:36:29.07#ibcon#enter sib2, iclass 3, count 0 2006.280.07:36:29.07#ibcon#flushed, iclass 3, count 0 2006.280.07:36:29.07#ibcon#about to write, iclass 3, count 0 2006.280.07:36:29.07#ibcon#wrote, iclass 3, count 0 2006.280.07:36:29.07#ibcon#about to read 3, iclass 3, count 0 2006.280.07:36:29.10#ibcon#read 3, iclass 3, count 0 2006.280.07:36:29.10#ibcon#about to read 4, iclass 3, count 0 2006.280.07:36:29.10#ibcon#read 4, iclass 3, count 0 2006.280.07:36:29.10#ibcon#about to read 5, iclass 3, count 0 2006.280.07:36:29.10#ibcon#read 5, iclass 3, count 0 2006.280.07:36:29.10#ibcon#about to read 6, iclass 3, count 0 2006.280.07:36:29.10#ibcon#read 6, iclass 3, count 0 2006.280.07:36:29.10#ibcon#end of sib2, iclass 3, count 0 2006.280.07:36:29.10#ibcon#*after write, iclass 3, count 0 2006.280.07:36:29.10#ibcon#*before return 0, iclass 3, count 0 2006.280.07:36:29.10#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:36:29.10#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:36:29.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:36:29.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:36:29.10$vc4f8/valo=3,672.99 2006.280.07:36:29.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.07:36:29.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.07:36:29.10#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:29.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:36:29.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:36:29.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:36:29.10#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:36:29.10#ibcon#first serial, iclass 5, count 0 2006.280.07:36:29.10#ibcon#enter sib2, iclass 5, count 0 2006.280.07:36:29.10#ibcon#flushed, iclass 5, count 0 2006.280.07:36:29.10#ibcon#about to write, iclass 5, count 0 2006.280.07:36:29.10#ibcon#wrote, iclass 5, count 0 2006.280.07:36:29.11#ibcon#about to read 3, iclass 5, count 0 2006.280.07:36:29.12#ibcon#read 3, iclass 5, count 0 2006.280.07:36:29.12#ibcon#about to read 4, iclass 5, count 0 2006.280.07:36:29.12#ibcon#read 4, iclass 5, count 0 2006.280.07:36:29.12#ibcon#about to read 5, iclass 5, count 0 2006.280.07:36:29.12#ibcon#read 5, iclass 5, count 0 2006.280.07:36:29.12#ibcon#about to read 6, iclass 5, count 0 2006.280.07:36:29.12#ibcon#read 6, iclass 5, count 0 2006.280.07:36:29.12#ibcon#end of sib2, iclass 5, count 0 2006.280.07:36:29.12#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:36:29.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:36:29.12#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:36:29.12#ibcon#*before write, iclass 5, count 0 2006.280.07:36:29.12#ibcon#enter sib2, iclass 5, count 0 2006.280.07:36:29.12#ibcon#flushed, iclass 5, count 0 2006.280.07:36:29.12#ibcon#about to write, iclass 5, count 0 2006.280.07:36:29.12#ibcon#wrote, iclass 5, count 0 2006.280.07:36:29.12#ibcon#about to read 3, iclass 5, count 0 2006.280.07:36:29.16#ibcon#read 3, iclass 5, count 0 2006.280.07:36:29.16#ibcon#about to read 4, iclass 5, count 0 2006.280.07:36:29.16#ibcon#read 4, iclass 5, count 0 2006.280.07:36:29.16#ibcon#about to read 5, iclass 5, count 0 2006.280.07:36:29.16#ibcon#read 5, iclass 5, count 0 2006.280.07:36:29.16#ibcon#about to read 6, iclass 5, count 0 2006.280.07:36:29.16#ibcon#read 6, iclass 5, count 0 2006.280.07:36:29.16#ibcon#end of sib2, iclass 5, count 0 2006.280.07:36:29.16#ibcon#*after write, iclass 5, count 0 2006.280.07:36:29.16#ibcon#*before return 0, iclass 5, count 0 2006.280.07:36:29.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:36:29.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:36:29.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:36:29.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:36:29.16$vc4f8/va=3,6 2006.280.07:36:29.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.07:36:29.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.07:36:29.16#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:29.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:29.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:29.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:29.22#ibcon#enter wrdev, iclass 7, count 2 2006.280.07:36:29.22#ibcon#first serial, iclass 7, count 2 2006.280.07:36:29.22#ibcon#enter sib2, iclass 7, count 2 2006.280.07:36:29.22#ibcon#flushed, iclass 7, count 2 2006.280.07:36:29.22#ibcon#about to write, iclass 7, count 2 2006.280.07:36:29.22#ibcon#wrote, iclass 7, count 2 2006.280.07:36:29.22#ibcon#about to read 3, iclass 7, count 2 2006.280.07:36:29.24#ibcon#read 3, iclass 7, count 2 2006.280.07:36:29.24#ibcon#about to read 4, iclass 7, count 2 2006.280.07:36:29.24#ibcon#read 4, iclass 7, count 2 2006.280.07:36:29.24#ibcon#about to read 5, iclass 7, count 2 2006.280.07:36:29.24#ibcon#read 5, iclass 7, count 2 2006.280.07:36:29.24#ibcon#about to read 6, iclass 7, count 2 2006.280.07:36:29.24#ibcon#read 6, iclass 7, count 2 2006.280.07:36:29.24#ibcon#end of sib2, iclass 7, count 2 2006.280.07:36:29.24#ibcon#*mode == 0, iclass 7, count 2 2006.280.07:36:29.24#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.07:36:29.24#ibcon#[25=AT03-06\r\n] 2006.280.07:36:29.24#ibcon#*before write, iclass 7, count 2 2006.280.07:36:29.24#ibcon#enter sib2, iclass 7, count 2 2006.280.07:36:29.24#ibcon#flushed, iclass 7, count 2 2006.280.07:36:29.24#ibcon#about to write, iclass 7, count 2 2006.280.07:36:29.24#ibcon#wrote, iclass 7, count 2 2006.280.07:36:29.24#ibcon#about to read 3, iclass 7, count 2 2006.280.07:36:29.27#ibcon#read 3, iclass 7, count 2 2006.280.07:36:29.27#ibcon#about to read 4, iclass 7, count 2 2006.280.07:36:29.27#ibcon#read 4, iclass 7, count 2 2006.280.07:36:29.27#ibcon#about to read 5, iclass 7, count 2 2006.280.07:36:29.27#ibcon#read 5, iclass 7, count 2 2006.280.07:36:29.27#ibcon#about to read 6, iclass 7, count 2 2006.280.07:36:29.27#ibcon#read 6, iclass 7, count 2 2006.280.07:36:29.27#ibcon#end of sib2, iclass 7, count 2 2006.280.07:36:29.27#ibcon#*after write, iclass 7, count 2 2006.280.07:36:29.27#ibcon#*before return 0, iclass 7, count 2 2006.280.07:36:29.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:29.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:29.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.07:36:29.27#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:29.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:29.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:29.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:29.39#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:36:29.39#ibcon#first serial, iclass 7, count 0 2006.280.07:36:29.39#ibcon#enter sib2, iclass 7, count 0 2006.280.07:36:29.39#ibcon#flushed, iclass 7, count 0 2006.280.07:36:29.39#ibcon#about to write, iclass 7, count 0 2006.280.07:36:29.39#ibcon#wrote, iclass 7, count 0 2006.280.07:36:29.39#ibcon#about to read 3, iclass 7, count 0 2006.280.07:36:29.41#ibcon#read 3, iclass 7, count 0 2006.280.07:36:29.41#ibcon#about to read 4, iclass 7, count 0 2006.280.07:36:29.41#ibcon#read 4, iclass 7, count 0 2006.280.07:36:29.41#ibcon#about to read 5, iclass 7, count 0 2006.280.07:36:29.41#ibcon#read 5, iclass 7, count 0 2006.280.07:36:29.41#ibcon#about to read 6, iclass 7, count 0 2006.280.07:36:29.41#ibcon#read 6, iclass 7, count 0 2006.280.07:36:29.41#ibcon#end of sib2, iclass 7, count 0 2006.280.07:36:29.41#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:36:29.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:36:29.41#ibcon#[25=USB\r\n] 2006.280.07:36:29.41#ibcon#*before write, iclass 7, count 0 2006.280.07:36:29.41#ibcon#enter sib2, iclass 7, count 0 2006.280.07:36:29.41#ibcon#flushed, iclass 7, count 0 2006.280.07:36:29.41#ibcon#about to write, iclass 7, count 0 2006.280.07:36:29.41#ibcon#wrote, iclass 7, count 0 2006.280.07:36:29.41#ibcon#about to read 3, iclass 7, count 0 2006.280.07:36:29.44#ibcon#read 3, iclass 7, count 0 2006.280.07:36:29.44#ibcon#about to read 4, iclass 7, count 0 2006.280.07:36:29.44#ibcon#read 4, iclass 7, count 0 2006.280.07:36:29.44#ibcon#about to read 5, iclass 7, count 0 2006.280.07:36:29.44#ibcon#read 5, iclass 7, count 0 2006.280.07:36:29.44#ibcon#about to read 6, iclass 7, count 0 2006.280.07:36:29.44#ibcon#read 6, iclass 7, count 0 2006.280.07:36:29.44#ibcon#end of sib2, iclass 7, count 0 2006.280.07:36:29.44#ibcon#*after write, iclass 7, count 0 2006.280.07:36:29.44#ibcon#*before return 0, iclass 7, count 0 2006.280.07:36:29.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:29.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:29.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:36:29.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:36:29.44$vc4f8/valo=4,832.99 2006.280.07:36:29.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.07:36:29.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.07:36:29.44#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:29.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:29.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:29.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:29.44#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:36:29.44#ibcon#first serial, iclass 11, count 0 2006.280.07:36:29.44#ibcon#enter sib2, iclass 11, count 0 2006.280.07:36:29.44#ibcon#flushed, iclass 11, count 0 2006.280.07:36:29.44#ibcon#about to write, iclass 11, count 0 2006.280.07:36:29.44#ibcon#wrote, iclass 11, count 0 2006.280.07:36:29.44#ibcon#about to read 3, iclass 11, count 0 2006.280.07:36:29.46#ibcon#read 3, iclass 11, count 0 2006.280.07:36:29.46#ibcon#about to read 4, iclass 11, count 0 2006.280.07:36:29.46#ibcon#read 4, iclass 11, count 0 2006.280.07:36:29.46#ibcon#about to read 5, iclass 11, count 0 2006.280.07:36:29.46#ibcon#read 5, iclass 11, count 0 2006.280.07:36:29.46#ibcon#about to read 6, iclass 11, count 0 2006.280.07:36:29.46#ibcon#read 6, iclass 11, count 0 2006.280.07:36:29.46#ibcon#end of sib2, iclass 11, count 0 2006.280.07:36:29.46#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:36:29.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:36:29.46#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:36:29.46#ibcon#*before write, iclass 11, count 0 2006.280.07:36:29.46#ibcon#enter sib2, iclass 11, count 0 2006.280.07:36:29.46#ibcon#flushed, iclass 11, count 0 2006.280.07:36:29.46#ibcon#about to write, iclass 11, count 0 2006.280.07:36:29.46#ibcon#wrote, iclass 11, count 0 2006.280.07:36:29.46#ibcon#about to read 3, iclass 11, count 0 2006.280.07:36:29.50#ibcon#read 3, iclass 11, count 0 2006.280.07:36:29.50#ibcon#about to read 4, iclass 11, count 0 2006.280.07:36:29.50#ibcon#read 4, iclass 11, count 0 2006.280.07:36:29.50#ibcon#about to read 5, iclass 11, count 0 2006.280.07:36:29.50#ibcon#read 5, iclass 11, count 0 2006.280.07:36:29.50#ibcon#about to read 6, iclass 11, count 0 2006.280.07:36:29.50#ibcon#read 6, iclass 11, count 0 2006.280.07:36:29.50#ibcon#end of sib2, iclass 11, count 0 2006.280.07:36:29.50#ibcon#*after write, iclass 11, count 0 2006.280.07:36:29.50#ibcon#*before return 0, iclass 11, count 0 2006.280.07:36:29.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:29.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:29.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:36:29.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:36:29.50$vc4f8/va=4,6 2006.280.07:36:29.50#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.07:36:29.50#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.07:36:29.50#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:29.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:29.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:29.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:29.56#ibcon#enter wrdev, iclass 13, count 2 2006.280.07:36:29.56#ibcon#first serial, iclass 13, count 2 2006.280.07:36:29.56#ibcon#enter sib2, iclass 13, count 2 2006.280.07:36:29.56#ibcon#flushed, iclass 13, count 2 2006.280.07:36:29.56#ibcon#about to write, iclass 13, count 2 2006.280.07:36:29.56#ibcon#wrote, iclass 13, count 2 2006.280.07:36:29.56#ibcon#about to read 3, iclass 13, count 2 2006.280.07:36:29.58#ibcon#read 3, iclass 13, count 2 2006.280.07:36:29.58#ibcon#about to read 4, iclass 13, count 2 2006.280.07:36:29.58#ibcon#read 4, iclass 13, count 2 2006.280.07:36:29.58#ibcon#about to read 5, iclass 13, count 2 2006.280.07:36:29.58#ibcon#read 5, iclass 13, count 2 2006.280.07:36:29.58#ibcon#about to read 6, iclass 13, count 2 2006.280.07:36:29.58#ibcon#read 6, iclass 13, count 2 2006.280.07:36:29.58#ibcon#end of sib2, iclass 13, count 2 2006.280.07:36:29.58#ibcon#*mode == 0, iclass 13, count 2 2006.280.07:36:29.58#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.07:36:29.58#ibcon#[25=AT04-06\r\n] 2006.280.07:36:29.58#ibcon#*before write, iclass 13, count 2 2006.280.07:36:29.58#ibcon#enter sib2, iclass 13, count 2 2006.280.07:36:29.58#ibcon#flushed, iclass 13, count 2 2006.280.07:36:29.58#ibcon#about to write, iclass 13, count 2 2006.280.07:36:29.58#ibcon#wrote, iclass 13, count 2 2006.280.07:36:29.58#ibcon#about to read 3, iclass 13, count 2 2006.280.07:36:29.61#ibcon#read 3, iclass 13, count 2 2006.280.07:36:29.61#ibcon#about to read 4, iclass 13, count 2 2006.280.07:36:29.61#ibcon#read 4, iclass 13, count 2 2006.280.07:36:29.61#ibcon#about to read 5, iclass 13, count 2 2006.280.07:36:29.61#ibcon#read 5, iclass 13, count 2 2006.280.07:36:29.61#ibcon#about to read 6, iclass 13, count 2 2006.280.07:36:29.61#ibcon#read 6, iclass 13, count 2 2006.280.07:36:29.61#ibcon#end of sib2, iclass 13, count 2 2006.280.07:36:29.61#ibcon#*after write, iclass 13, count 2 2006.280.07:36:29.61#ibcon#*before return 0, iclass 13, count 2 2006.280.07:36:29.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:29.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:29.61#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.07:36:29.61#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:29.61#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:29.73#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:29.73#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:29.73#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:36:29.73#ibcon#first serial, iclass 13, count 0 2006.280.07:36:29.73#ibcon#enter sib2, iclass 13, count 0 2006.280.07:36:29.73#ibcon#flushed, iclass 13, count 0 2006.280.07:36:29.73#ibcon#about to write, iclass 13, count 0 2006.280.07:36:29.73#ibcon#wrote, iclass 13, count 0 2006.280.07:36:29.73#ibcon#about to read 3, iclass 13, count 0 2006.280.07:36:29.75#ibcon#read 3, iclass 13, count 0 2006.280.07:36:29.75#ibcon#about to read 4, iclass 13, count 0 2006.280.07:36:29.75#ibcon#read 4, iclass 13, count 0 2006.280.07:36:29.75#ibcon#about to read 5, iclass 13, count 0 2006.280.07:36:29.75#ibcon#read 5, iclass 13, count 0 2006.280.07:36:29.75#ibcon#about to read 6, iclass 13, count 0 2006.280.07:36:29.75#ibcon#read 6, iclass 13, count 0 2006.280.07:36:29.75#ibcon#end of sib2, iclass 13, count 0 2006.280.07:36:29.75#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:36:29.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:36:29.75#ibcon#[25=USB\r\n] 2006.280.07:36:29.75#ibcon#*before write, iclass 13, count 0 2006.280.07:36:29.75#ibcon#enter sib2, iclass 13, count 0 2006.280.07:36:29.75#ibcon#flushed, iclass 13, count 0 2006.280.07:36:29.75#ibcon#about to write, iclass 13, count 0 2006.280.07:36:29.75#ibcon#wrote, iclass 13, count 0 2006.280.07:36:29.75#ibcon#about to read 3, iclass 13, count 0 2006.280.07:36:29.78#ibcon#read 3, iclass 13, count 0 2006.280.07:36:29.78#ibcon#about to read 4, iclass 13, count 0 2006.280.07:36:29.78#ibcon#read 4, iclass 13, count 0 2006.280.07:36:29.78#ibcon#about to read 5, iclass 13, count 0 2006.280.07:36:29.78#ibcon#read 5, iclass 13, count 0 2006.280.07:36:29.78#ibcon#about to read 6, iclass 13, count 0 2006.280.07:36:29.78#ibcon#read 6, iclass 13, count 0 2006.280.07:36:29.78#ibcon#end of sib2, iclass 13, count 0 2006.280.07:36:29.78#ibcon#*after write, iclass 13, count 0 2006.280.07:36:29.78#ibcon#*before return 0, iclass 13, count 0 2006.280.07:36:29.78#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:29.78#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:29.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:36:29.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:36:29.78$vc4f8/valo=5,652.99 2006.280.07:36:29.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:36:29.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:36:29.78#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:29.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:29.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:29.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:29.78#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:36:29.78#ibcon#first serial, iclass 15, count 0 2006.280.07:36:29.78#ibcon#enter sib2, iclass 15, count 0 2006.280.07:36:29.78#ibcon#flushed, iclass 15, count 0 2006.280.07:36:29.78#ibcon#about to write, iclass 15, count 0 2006.280.07:36:29.78#ibcon#wrote, iclass 15, count 0 2006.280.07:36:29.78#ibcon#about to read 3, iclass 15, count 0 2006.280.07:36:29.80#ibcon#read 3, iclass 15, count 0 2006.280.07:36:29.80#ibcon#about to read 4, iclass 15, count 0 2006.280.07:36:29.80#ibcon#read 4, iclass 15, count 0 2006.280.07:36:29.80#ibcon#about to read 5, iclass 15, count 0 2006.280.07:36:29.80#ibcon#read 5, iclass 15, count 0 2006.280.07:36:29.80#ibcon#about to read 6, iclass 15, count 0 2006.280.07:36:29.80#ibcon#read 6, iclass 15, count 0 2006.280.07:36:29.80#ibcon#end of sib2, iclass 15, count 0 2006.280.07:36:29.80#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:36:29.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:36:29.80#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:36:29.80#ibcon#*before write, iclass 15, count 0 2006.280.07:36:29.80#ibcon#enter sib2, iclass 15, count 0 2006.280.07:36:29.80#ibcon#flushed, iclass 15, count 0 2006.280.07:36:29.80#ibcon#about to write, iclass 15, count 0 2006.280.07:36:29.80#ibcon#wrote, iclass 15, count 0 2006.280.07:36:29.80#ibcon#about to read 3, iclass 15, count 0 2006.280.07:36:29.84#ibcon#read 3, iclass 15, count 0 2006.280.07:36:29.84#ibcon#about to read 4, iclass 15, count 0 2006.280.07:36:29.84#ibcon#read 4, iclass 15, count 0 2006.280.07:36:29.84#ibcon#about to read 5, iclass 15, count 0 2006.280.07:36:29.84#ibcon#read 5, iclass 15, count 0 2006.280.07:36:29.84#ibcon#about to read 6, iclass 15, count 0 2006.280.07:36:29.84#ibcon#read 6, iclass 15, count 0 2006.280.07:36:29.84#ibcon#end of sib2, iclass 15, count 0 2006.280.07:36:29.84#ibcon#*after write, iclass 15, count 0 2006.280.07:36:29.84#ibcon#*before return 0, iclass 15, count 0 2006.280.07:36:29.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:29.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:29.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:36:29.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:36:29.84$vc4f8/va=5,7 2006.280.07:36:29.84#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.07:36:29.84#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.07:36:29.84#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:29.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:29.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:29.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:29.90#ibcon#enter wrdev, iclass 17, count 2 2006.280.07:36:29.90#ibcon#first serial, iclass 17, count 2 2006.280.07:36:29.90#ibcon#enter sib2, iclass 17, count 2 2006.280.07:36:29.90#ibcon#flushed, iclass 17, count 2 2006.280.07:36:29.90#ibcon#about to write, iclass 17, count 2 2006.280.07:36:29.90#ibcon#wrote, iclass 17, count 2 2006.280.07:36:29.90#ibcon#about to read 3, iclass 17, count 2 2006.280.07:36:29.92#ibcon#read 3, iclass 17, count 2 2006.280.07:36:29.92#ibcon#about to read 4, iclass 17, count 2 2006.280.07:36:29.92#ibcon#read 4, iclass 17, count 2 2006.280.07:36:29.92#ibcon#about to read 5, iclass 17, count 2 2006.280.07:36:29.92#ibcon#read 5, iclass 17, count 2 2006.280.07:36:29.92#ibcon#about to read 6, iclass 17, count 2 2006.280.07:36:29.92#ibcon#read 6, iclass 17, count 2 2006.280.07:36:29.92#ibcon#end of sib2, iclass 17, count 2 2006.280.07:36:29.92#ibcon#*mode == 0, iclass 17, count 2 2006.280.07:36:29.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.07:36:29.93#ibcon#[25=AT05-07\r\n] 2006.280.07:36:29.93#ibcon#*before write, iclass 17, count 2 2006.280.07:36:29.93#ibcon#enter sib2, iclass 17, count 2 2006.280.07:36:29.93#ibcon#flushed, iclass 17, count 2 2006.280.07:36:29.93#ibcon#about to write, iclass 17, count 2 2006.280.07:36:29.93#ibcon#wrote, iclass 17, count 2 2006.280.07:36:29.93#ibcon#about to read 3, iclass 17, count 2 2006.280.07:36:29.96#ibcon#read 3, iclass 17, count 2 2006.280.07:36:29.96#ibcon#about to read 4, iclass 17, count 2 2006.280.07:36:29.96#ibcon#read 4, iclass 17, count 2 2006.280.07:36:29.96#ibcon#about to read 5, iclass 17, count 2 2006.280.07:36:29.96#ibcon#read 5, iclass 17, count 2 2006.280.07:36:29.96#ibcon#about to read 6, iclass 17, count 2 2006.280.07:36:29.96#ibcon#read 6, iclass 17, count 2 2006.280.07:36:29.96#ibcon#end of sib2, iclass 17, count 2 2006.280.07:36:29.96#ibcon#*after write, iclass 17, count 2 2006.280.07:36:29.96#ibcon#*before return 0, iclass 17, count 2 2006.280.07:36:29.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:29.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:29.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.07:36:29.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:29.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:30.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:30.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:30.08#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:36:30.08#ibcon#first serial, iclass 17, count 0 2006.280.07:36:30.08#ibcon#enter sib2, iclass 17, count 0 2006.280.07:36:30.08#ibcon#flushed, iclass 17, count 0 2006.280.07:36:30.08#ibcon#about to write, iclass 17, count 0 2006.280.07:36:30.08#ibcon#wrote, iclass 17, count 0 2006.280.07:36:30.08#ibcon#about to read 3, iclass 17, count 0 2006.280.07:36:30.10#ibcon#read 3, iclass 17, count 0 2006.280.07:36:30.10#ibcon#about to read 4, iclass 17, count 0 2006.280.07:36:30.10#ibcon#read 4, iclass 17, count 0 2006.280.07:36:30.10#ibcon#about to read 5, iclass 17, count 0 2006.280.07:36:30.10#ibcon#read 5, iclass 17, count 0 2006.280.07:36:30.10#ibcon#about to read 6, iclass 17, count 0 2006.280.07:36:30.10#ibcon#read 6, iclass 17, count 0 2006.280.07:36:30.10#ibcon#end of sib2, iclass 17, count 0 2006.280.07:36:30.10#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:36:30.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:36:30.10#ibcon#[25=USB\r\n] 2006.280.07:36:30.10#ibcon#*before write, iclass 17, count 0 2006.280.07:36:30.10#ibcon#enter sib2, iclass 17, count 0 2006.280.07:36:30.10#ibcon#flushed, iclass 17, count 0 2006.280.07:36:30.10#ibcon#about to write, iclass 17, count 0 2006.280.07:36:30.10#ibcon#wrote, iclass 17, count 0 2006.280.07:36:30.10#ibcon#about to read 3, iclass 17, count 0 2006.280.07:36:30.13#ibcon#read 3, iclass 17, count 0 2006.280.07:36:30.13#ibcon#about to read 4, iclass 17, count 0 2006.280.07:36:30.13#ibcon#read 4, iclass 17, count 0 2006.280.07:36:30.13#ibcon#about to read 5, iclass 17, count 0 2006.280.07:36:30.13#ibcon#read 5, iclass 17, count 0 2006.280.07:36:30.13#ibcon#about to read 6, iclass 17, count 0 2006.280.07:36:30.13#ibcon#read 6, iclass 17, count 0 2006.280.07:36:30.13#ibcon#end of sib2, iclass 17, count 0 2006.280.07:36:30.13#ibcon#*after write, iclass 17, count 0 2006.280.07:36:30.13#ibcon#*before return 0, iclass 17, count 0 2006.280.07:36:30.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:30.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:30.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:36:30.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:36:30.13$vc4f8/valo=6,772.99 2006.280.07:36:30.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:36:30.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:36:30.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:30.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:30.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:30.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:30.13#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:36:30.13#ibcon#first serial, iclass 19, count 0 2006.280.07:36:30.13#ibcon#enter sib2, iclass 19, count 0 2006.280.07:36:30.13#ibcon#flushed, iclass 19, count 0 2006.280.07:36:30.13#ibcon#about to write, iclass 19, count 0 2006.280.07:36:30.13#ibcon#wrote, iclass 19, count 0 2006.280.07:36:30.13#ibcon#about to read 3, iclass 19, count 0 2006.280.07:36:30.15#ibcon#read 3, iclass 19, count 0 2006.280.07:36:30.15#ibcon#about to read 4, iclass 19, count 0 2006.280.07:36:30.15#ibcon#read 4, iclass 19, count 0 2006.280.07:36:30.15#ibcon#about to read 5, iclass 19, count 0 2006.280.07:36:30.15#ibcon#read 5, iclass 19, count 0 2006.280.07:36:30.15#ibcon#about to read 6, iclass 19, count 0 2006.280.07:36:30.15#ibcon#read 6, iclass 19, count 0 2006.280.07:36:30.15#ibcon#end of sib2, iclass 19, count 0 2006.280.07:36:30.15#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:36:30.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:36:30.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:36:30.15#ibcon#*before write, iclass 19, count 0 2006.280.07:36:30.15#ibcon#enter sib2, iclass 19, count 0 2006.280.07:36:30.15#ibcon#flushed, iclass 19, count 0 2006.280.07:36:30.15#ibcon#about to write, iclass 19, count 0 2006.280.07:36:30.15#ibcon#wrote, iclass 19, count 0 2006.280.07:36:30.15#ibcon#about to read 3, iclass 19, count 0 2006.280.07:36:30.19#ibcon#read 3, iclass 19, count 0 2006.280.07:36:30.19#ibcon#about to read 4, iclass 19, count 0 2006.280.07:36:30.19#ibcon#read 4, iclass 19, count 0 2006.280.07:36:30.19#ibcon#about to read 5, iclass 19, count 0 2006.280.07:36:30.19#ibcon#read 5, iclass 19, count 0 2006.280.07:36:30.19#ibcon#about to read 6, iclass 19, count 0 2006.280.07:36:30.19#ibcon#read 6, iclass 19, count 0 2006.280.07:36:30.19#ibcon#end of sib2, iclass 19, count 0 2006.280.07:36:30.19#ibcon#*after write, iclass 19, count 0 2006.280.07:36:30.19#ibcon#*before return 0, iclass 19, count 0 2006.280.07:36:30.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:30.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:30.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:36:30.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:36:30.19$vc4f8/va=6,6 2006.280.07:36:30.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:36:30.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:36:30.19#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:30.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:30.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:30.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:30.32#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:36:30.32#ibcon#first serial, iclass 21, count 2 2006.280.07:36:30.32#ibcon#enter sib2, iclass 21, count 2 2006.280.07:36:30.32#ibcon#flushed, iclass 21, count 2 2006.280.07:36:30.32#ibcon#about to write, iclass 21, count 2 2006.280.07:36:30.32#ibcon#wrote, iclass 21, count 2 2006.280.07:36:30.32#ibcon#about to read 3, iclass 21, count 2 2006.280.07:36:30.34#ibcon#read 3, iclass 21, count 2 2006.280.07:36:30.34#ibcon#about to read 4, iclass 21, count 2 2006.280.07:36:30.34#ibcon#read 4, iclass 21, count 2 2006.280.07:36:30.34#ibcon#about to read 5, iclass 21, count 2 2006.280.07:36:30.34#ibcon#read 5, iclass 21, count 2 2006.280.07:36:30.34#ibcon#about to read 6, iclass 21, count 2 2006.280.07:36:30.34#ibcon#read 6, iclass 21, count 2 2006.280.07:36:30.34#ibcon#end of sib2, iclass 21, count 2 2006.280.07:36:30.34#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:36:30.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:36:30.34#ibcon#[25=AT06-06\r\n] 2006.280.07:36:30.34#ibcon#*before write, iclass 21, count 2 2006.280.07:36:30.34#ibcon#enter sib2, iclass 21, count 2 2006.280.07:36:30.34#ibcon#flushed, iclass 21, count 2 2006.280.07:36:30.34#ibcon#about to write, iclass 21, count 2 2006.280.07:36:30.34#ibcon#wrote, iclass 21, count 2 2006.280.07:36:30.34#ibcon#about to read 3, iclass 21, count 2 2006.280.07:36:30.37#ibcon#read 3, iclass 21, count 2 2006.280.07:36:30.37#ibcon#about to read 4, iclass 21, count 2 2006.280.07:36:30.37#ibcon#read 4, iclass 21, count 2 2006.280.07:36:30.37#ibcon#about to read 5, iclass 21, count 2 2006.280.07:36:30.37#ibcon#read 5, iclass 21, count 2 2006.280.07:36:30.37#ibcon#about to read 6, iclass 21, count 2 2006.280.07:36:30.37#ibcon#read 6, iclass 21, count 2 2006.280.07:36:30.37#ibcon#end of sib2, iclass 21, count 2 2006.280.07:36:30.37#ibcon#*after write, iclass 21, count 2 2006.280.07:36:30.37#ibcon#*before return 0, iclass 21, count 2 2006.280.07:36:30.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:30.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:30.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:36:30.37#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:30.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:30.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:30.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:30.49#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:36:30.49#ibcon#first serial, iclass 21, count 0 2006.280.07:36:30.49#ibcon#enter sib2, iclass 21, count 0 2006.280.07:36:30.49#ibcon#flushed, iclass 21, count 0 2006.280.07:36:30.49#ibcon#about to write, iclass 21, count 0 2006.280.07:36:30.49#ibcon#wrote, iclass 21, count 0 2006.280.07:36:30.49#ibcon#about to read 3, iclass 21, count 0 2006.280.07:36:30.51#ibcon#read 3, iclass 21, count 0 2006.280.07:36:30.51#ibcon#about to read 4, iclass 21, count 0 2006.280.07:36:30.51#ibcon#read 4, iclass 21, count 0 2006.280.07:36:30.51#ibcon#about to read 5, iclass 21, count 0 2006.280.07:36:30.51#ibcon#read 5, iclass 21, count 0 2006.280.07:36:30.51#ibcon#about to read 6, iclass 21, count 0 2006.280.07:36:30.51#ibcon#read 6, iclass 21, count 0 2006.280.07:36:30.51#ibcon#end of sib2, iclass 21, count 0 2006.280.07:36:30.51#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:36:30.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:36:30.51#ibcon#[25=USB\r\n] 2006.280.07:36:30.51#ibcon#*before write, iclass 21, count 0 2006.280.07:36:30.51#ibcon#enter sib2, iclass 21, count 0 2006.280.07:36:30.51#ibcon#flushed, iclass 21, count 0 2006.280.07:36:30.51#ibcon#about to write, iclass 21, count 0 2006.280.07:36:30.51#ibcon#wrote, iclass 21, count 0 2006.280.07:36:30.51#ibcon#about to read 3, iclass 21, count 0 2006.280.07:36:30.54#ibcon#read 3, iclass 21, count 0 2006.280.07:36:30.54#ibcon#about to read 4, iclass 21, count 0 2006.280.07:36:30.54#ibcon#read 4, iclass 21, count 0 2006.280.07:36:30.54#ibcon#about to read 5, iclass 21, count 0 2006.280.07:36:30.54#ibcon#read 5, iclass 21, count 0 2006.280.07:36:30.54#ibcon#about to read 6, iclass 21, count 0 2006.280.07:36:30.54#ibcon#read 6, iclass 21, count 0 2006.280.07:36:30.54#ibcon#end of sib2, iclass 21, count 0 2006.280.07:36:30.54#ibcon#*after write, iclass 21, count 0 2006.280.07:36:30.54#ibcon#*before return 0, iclass 21, count 0 2006.280.07:36:30.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:30.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:30.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:36:30.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:36:30.54$vc4f8/valo=7,832.99 2006.280.07:36:30.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:36:30.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:36:30.54#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:30.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:30.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:30.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:30.54#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:36:30.54#ibcon#first serial, iclass 23, count 0 2006.280.07:36:30.54#ibcon#enter sib2, iclass 23, count 0 2006.280.07:36:30.54#ibcon#flushed, iclass 23, count 0 2006.280.07:36:30.54#ibcon#about to write, iclass 23, count 0 2006.280.07:36:30.54#ibcon#wrote, iclass 23, count 0 2006.280.07:36:30.54#ibcon#about to read 3, iclass 23, count 0 2006.280.07:36:30.56#ibcon#read 3, iclass 23, count 0 2006.280.07:36:30.56#ibcon#about to read 4, iclass 23, count 0 2006.280.07:36:30.56#ibcon#read 4, iclass 23, count 0 2006.280.07:36:30.56#ibcon#about to read 5, iclass 23, count 0 2006.280.07:36:30.56#ibcon#read 5, iclass 23, count 0 2006.280.07:36:30.56#ibcon#about to read 6, iclass 23, count 0 2006.280.07:36:30.56#ibcon#read 6, iclass 23, count 0 2006.280.07:36:30.56#ibcon#end of sib2, iclass 23, count 0 2006.280.07:36:30.56#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:36:30.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:36:30.56#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:36:30.56#ibcon#*before write, iclass 23, count 0 2006.280.07:36:30.56#ibcon#enter sib2, iclass 23, count 0 2006.280.07:36:30.56#ibcon#flushed, iclass 23, count 0 2006.280.07:36:30.56#ibcon#about to write, iclass 23, count 0 2006.280.07:36:30.56#ibcon#wrote, iclass 23, count 0 2006.280.07:36:30.56#ibcon#about to read 3, iclass 23, count 0 2006.280.07:36:30.60#ibcon#read 3, iclass 23, count 0 2006.280.07:36:30.60#ibcon#about to read 4, iclass 23, count 0 2006.280.07:36:30.60#ibcon#read 4, iclass 23, count 0 2006.280.07:36:30.60#ibcon#about to read 5, iclass 23, count 0 2006.280.07:36:30.60#ibcon#read 5, iclass 23, count 0 2006.280.07:36:30.60#ibcon#about to read 6, iclass 23, count 0 2006.280.07:36:30.60#ibcon#read 6, iclass 23, count 0 2006.280.07:36:30.60#ibcon#end of sib2, iclass 23, count 0 2006.280.07:36:30.60#ibcon#*after write, iclass 23, count 0 2006.280.07:36:30.60#ibcon#*before return 0, iclass 23, count 0 2006.280.07:36:30.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:30.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:30.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:36:30.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:36:30.60$vc4f8/va=7,6 2006.280.07:36:30.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.07:36:30.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.07:36:30.60#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:30.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:30.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:30.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:30.66#ibcon#enter wrdev, iclass 25, count 2 2006.280.07:36:30.66#ibcon#first serial, iclass 25, count 2 2006.280.07:36:30.66#ibcon#enter sib2, iclass 25, count 2 2006.280.07:36:30.66#ibcon#flushed, iclass 25, count 2 2006.280.07:36:30.66#ibcon#about to write, iclass 25, count 2 2006.280.07:36:30.66#ibcon#wrote, iclass 25, count 2 2006.280.07:36:30.66#ibcon#about to read 3, iclass 25, count 2 2006.280.07:36:30.68#ibcon#read 3, iclass 25, count 2 2006.280.07:36:30.68#ibcon#about to read 4, iclass 25, count 2 2006.280.07:36:30.68#ibcon#read 4, iclass 25, count 2 2006.280.07:36:30.68#ibcon#about to read 5, iclass 25, count 2 2006.280.07:36:30.68#ibcon#read 5, iclass 25, count 2 2006.280.07:36:30.68#ibcon#about to read 6, iclass 25, count 2 2006.280.07:36:30.68#ibcon#read 6, iclass 25, count 2 2006.280.07:36:30.68#ibcon#end of sib2, iclass 25, count 2 2006.280.07:36:30.68#ibcon#*mode == 0, iclass 25, count 2 2006.280.07:36:30.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.07:36:30.68#ibcon#[25=AT07-06\r\n] 2006.280.07:36:30.68#ibcon#*before write, iclass 25, count 2 2006.280.07:36:30.68#ibcon#enter sib2, iclass 25, count 2 2006.280.07:36:30.68#ibcon#flushed, iclass 25, count 2 2006.280.07:36:30.68#ibcon#about to write, iclass 25, count 2 2006.280.07:36:30.68#ibcon#wrote, iclass 25, count 2 2006.280.07:36:30.68#ibcon#about to read 3, iclass 25, count 2 2006.280.07:36:30.71#ibcon#read 3, iclass 25, count 2 2006.280.07:36:30.71#ibcon#about to read 4, iclass 25, count 2 2006.280.07:36:30.71#ibcon#read 4, iclass 25, count 2 2006.280.07:36:30.71#ibcon#about to read 5, iclass 25, count 2 2006.280.07:36:30.71#ibcon#read 5, iclass 25, count 2 2006.280.07:36:30.71#ibcon#about to read 6, iclass 25, count 2 2006.280.07:36:30.71#ibcon#read 6, iclass 25, count 2 2006.280.07:36:30.71#ibcon#end of sib2, iclass 25, count 2 2006.280.07:36:30.71#ibcon#*after write, iclass 25, count 2 2006.280.07:36:30.71#ibcon#*before return 0, iclass 25, count 2 2006.280.07:36:30.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:30.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:30.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.07:36:30.71#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:30.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:36:30.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:36:30.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:36:30.83#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:36:30.83#ibcon#first serial, iclass 25, count 0 2006.280.07:36:30.83#ibcon#enter sib2, iclass 25, count 0 2006.280.07:36:30.83#ibcon#flushed, iclass 25, count 0 2006.280.07:36:30.83#ibcon#about to write, iclass 25, count 0 2006.280.07:36:30.83#ibcon#wrote, iclass 25, count 0 2006.280.07:36:30.83#ibcon#about to read 3, iclass 25, count 0 2006.280.07:36:30.85#ibcon#read 3, iclass 25, count 0 2006.280.07:36:30.85#ibcon#about to read 4, iclass 25, count 0 2006.280.07:36:30.85#ibcon#read 4, iclass 25, count 0 2006.280.07:36:30.85#ibcon#about to read 5, iclass 25, count 0 2006.280.07:36:30.85#ibcon#read 5, iclass 25, count 0 2006.280.07:36:30.85#ibcon#about to read 6, iclass 25, count 0 2006.280.07:36:30.85#ibcon#read 6, iclass 25, count 0 2006.280.07:36:30.85#ibcon#end of sib2, iclass 25, count 0 2006.280.07:36:30.85#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:36:30.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:36:30.85#ibcon#[25=USB\r\n] 2006.280.07:36:30.85#ibcon#*before write, iclass 25, count 0 2006.280.07:36:30.85#ibcon#enter sib2, iclass 25, count 0 2006.280.07:36:30.85#ibcon#flushed, iclass 25, count 0 2006.280.07:36:30.85#ibcon#about to write, iclass 25, count 0 2006.280.07:36:30.85#ibcon#wrote, iclass 25, count 0 2006.280.07:36:30.85#ibcon#about to read 3, iclass 25, count 0 2006.280.07:36:30.88#ibcon#read 3, iclass 25, count 0 2006.280.07:36:30.88#ibcon#about to read 4, iclass 25, count 0 2006.280.07:36:30.88#ibcon#read 4, iclass 25, count 0 2006.280.07:36:30.88#ibcon#about to read 5, iclass 25, count 0 2006.280.07:36:30.88#ibcon#read 5, iclass 25, count 0 2006.280.07:36:30.88#ibcon#about to read 6, iclass 25, count 0 2006.280.07:36:30.88#ibcon#read 6, iclass 25, count 0 2006.280.07:36:30.88#ibcon#end of sib2, iclass 25, count 0 2006.280.07:36:30.88#ibcon#*after write, iclass 25, count 0 2006.280.07:36:30.88#ibcon#*before return 0, iclass 25, count 0 2006.280.07:36:30.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:36:30.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:36:30.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:36:30.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:36:30.88$vc4f8/valo=8,852.99 2006.280.07:36:30.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:36:30.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:36:30.88#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:30.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:36:30.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:36:30.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:36:30.88#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:36:30.88#ibcon#first serial, iclass 27, count 0 2006.280.07:36:30.88#ibcon#enter sib2, iclass 27, count 0 2006.280.07:36:30.88#ibcon#flushed, iclass 27, count 0 2006.280.07:36:30.88#ibcon#about to write, iclass 27, count 0 2006.280.07:36:30.88#ibcon#wrote, iclass 27, count 0 2006.280.07:36:30.88#ibcon#about to read 3, iclass 27, count 0 2006.280.07:36:30.90#ibcon#read 3, iclass 27, count 0 2006.280.07:36:30.90#ibcon#about to read 4, iclass 27, count 0 2006.280.07:36:30.90#ibcon#read 4, iclass 27, count 0 2006.280.07:36:30.90#ibcon#about to read 5, iclass 27, count 0 2006.280.07:36:30.90#ibcon#read 5, iclass 27, count 0 2006.280.07:36:30.90#ibcon#about to read 6, iclass 27, count 0 2006.280.07:36:30.90#ibcon#read 6, iclass 27, count 0 2006.280.07:36:30.90#ibcon#end of sib2, iclass 27, count 0 2006.280.07:36:30.90#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:36:30.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:36:30.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:36:30.90#ibcon#*before write, iclass 27, count 0 2006.280.07:36:30.90#ibcon#enter sib2, iclass 27, count 0 2006.280.07:36:30.90#ibcon#flushed, iclass 27, count 0 2006.280.07:36:30.90#ibcon#about to write, iclass 27, count 0 2006.280.07:36:30.90#ibcon#wrote, iclass 27, count 0 2006.280.07:36:30.90#ibcon#about to read 3, iclass 27, count 0 2006.280.07:36:30.94#ibcon#read 3, iclass 27, count 0 2006.280.07:36:30.94#ibcon#about to read 4, iclass 27, count 0 2006.280.07:36:30.94#ibcon#read 4, iclass 27, count 0 2006.280.07:36:30.94#ibcon#about to read 5, iclass 27, count 0 2006.280.07:36:30.94#ibcon#read 5, iclass 27, count 0 2006.280.07:36:30.94#ibcon#about to read 6, iclass 27, count 0 2006.280.07:36:30.94#ibcon#read 6, iclass 27, count 0 2006.280.07:36:30.94#ibcon#end of sib2, iclass 27, count 0 2006.280.07:36:30.94#ibcon#*after write, iclass 27, count 0 2006.280.07:36:30.94#ibcon#*before return 0, iclass 27, count 0 2006.280.07:36:30.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:36:30.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:36:30.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:36:30.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:36:30.94$vc4f8/va=8,6 2006.280.07:36:30.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.07:36:30.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.07:36:30.94#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:30.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:36:31.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:36:31.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:36:31.00#ibcon#enter wrdev, iclass 29, count 2 2006.280.07:36:31.00#ibcon#first serial, iclass 29, count 2 2006.280.07:36:31.00#ibcon#enter sib2, iclass 29, count 2 2006.280.07:36:31.00#ibcon#flushed, iclass 29, count 2 2006.280.07:36:31.00#ibcon#about to write, iclass 29, count 2 2006.280.07:36:31.00#ibcon#wrote, iclass 29, count 2 2006.280.07:36:31.00#ibcon#about to read 3, iclass 29, count 2 2006.280.07:36:31.02#ibcon#read 3, iclass 29, count 2 2006.280.07:36:31.02#ibcon#about to read 4, iclass 29, count 2 2006.280.07:36:31.02#ibcon#read 4, iclass 29, count 2 2006.280.07:36:31.02#ibcon#about to read 5, iclass 29, count 2 2006.280.07:36:31.02#ibcon#read 5, iclass 29, count 2 2006.280.07:36:31.02#ibcon#about to read 6, iclass 29, count 2 2006.280.07:36:31.02#ibcon#read 6, iclass 29, count 2 2006.280.07:36:31.02#ibcon#end of sib2, iclass 29, count 2 2006.280.07:36:31.02#ibcon#*mode == 0, iclass 29, count 2 2006.280.07:36:31.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.07:36:31.02#ibcon#[25=AT08-06\r\n] 2006.280.07:36:31.02#ibcon#*before write, iclass 29, count 2 2006.280.07:36:31.02#ibcon#enter sib2, iclass 29, count 2 2006.280.07:36:31.02#ibcon#flushed, iclass 29, count 2 2006.280.07:36:31.02#ibcon#about to write, iclass 29, count 2 2006.280.07:36:31.02#ibcon#wrote, iclass 29, count 2 2006.280.07:36:31.02#ibcon#about to read 3, iclass 29, count 2 2006.280.07:36:31.05#ibcon#read 3, iclass 29, count 2 2006.280.07:36:31.05#ibcon#about to read 4, iclass 29, count 2 2006.280.07:36:31.05#ibcon#read 4, iclass 29, count 2 2006.280.07:36:31.05#ibcon#about to read 5, iclass 29, count 2 2006.280.07:36:31.05#ibcon#read 5, iclass 29, count 2 2006.280.07:36:31.05#ibcon#about to read 6, iclass 29, count 2 2006.280.07:36:31.05#ibcon#read 6, iclass 29, count 2 2006.280.07:36:31.05#ibcon#end of sib2, iclass 29, count 2 2006.280.07:36:31.05#ibcon#*after write, iclass 29, count 2 2006.280.07:36:31.05#ibcon#*before return 0, iclass 29, count 2 2006.280.07:36:31.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:36:31.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:36:31.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.07:36:31.05#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:31.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:36:31.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:36:31.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:36:31.17#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:36:31.17#ibcon#first serial, iclass 29, count 0 2006.280.07:36:31.17#ibcon#enter sib2, iclass 29, count 0 2006.280.07:36:31.17#ibcon#flushed, iclass 29, count 0 2006.280.07:36:31.17#ibcon#about to write, iclass 29, count 0 2006.280.07:36:31.17#ibcon#wrote, iclass 29, count 0 2006.280.07:36:31.17#ibcon#about to read 3, iclass 29, count 0 2006.280.07:36:31.19#ibcon#read 3, iclass 29, count 0 2006.280.07:36:31.19#ibcon#about to read 4, iclass 29, count 0 2006.280.07:36:31.19#ibcon#read 4, iclass 29, count 0 2006.280.07:36:31.19#ibcon#about to read 5, iclass 29, count 0 2006.280.07:36:31.19#ibcon#read 5, iclass 29, count 0 2006.280.07:36:31.19#ibcon#about to read 6, iclass 29, count 0 2006.280.07:36:31.19#ibcon#read 6, iclass 29, count 0 2006.280.07:36:31.19#ibcon#end of sib2, iclass 29, count 0 2006.280.07:36:31.19#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:36:31.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:36:31.19#ibcon#[25=USB\r\n] 2006.280.07:36:31.19#ibcon#*before write, iclass 29, count 0 2006.280.07:36:31.19#ibcon#enter sib2, iclass 29, count 0 2006.280.07:36:31.19#ibcon#flushed, iclass 29, count 0 2006.280.07:36:31.19#ibcon#about to write, iclass 29, count 0 2006.280.07:36:31.19#ibcon#wrote, iclass 29, count 0 2006.280.07:36:31.19#ibcon#about to read 3, iclass 29, count 0 2006.280.07:36:31.22#ibcon#read 3, iclass 29, count 0 2006.280.07:36:31.22#ibcon#about to read 4, iclass 29, count 0 2006.280.07:36:31.22#ibcon#read 4, iclass 29, count 0 2006.280.07:36:31.22#ibcon#about to read 5, iclass 29, count 0 2006.280.07:36:31.22#ibcon#read 5, iclass 29, count 0 2006.280.07:36:31.22#ibcon#about to read 6, iclass 29, count 0 2006.280.07:36:31.22#ibcon#read 6, iclass 29, count 0 2006.280.07:36:31.22#ibcon#end of sib2, iclass 29, count 0 2006.280.07:36:31.22#ibcon#*after write, iclass 29, count 0 2006.280.07:36:31.22#ibcon#*before return 0, iclass 29, count 0 2006.280.07:36:31.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:36:31.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:36:31.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:36:31.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:36:31.22$vc4f8/vblo=1,632.99 2006.280.07:36:31.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.07:36:31.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.07:36:31.22#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:31.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:36:31.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:36:31.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:36:31.22#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:36:31.22#ibcon#first serial, iclass 31, count 0 2006.280.07:36:31.22#ibcon#enter sib2, iclass 31, count 0 2006.280.07:36:31.22#ibcon#flushed, iclass 31, count 0 2006.280.07:36:31.22#ibcon#about to write, iclass 31, count 0 2006.280.07:36:31.22#ibcon#wrote, iclass 31, count 0 2006.280.07:36:31.22#ibcon#about to read 3, iclass 31, count 0 2006.280.07:36:31.24#ibcon#read 3, iclass 31, count 0 2006.280.07:36:31.25#ibcon#about to read 4, iclass 31, count 0 2006.280.07:36:31.25#ibcon#read 4, iclass 31, count 0 2006.280.07:36:31.25#ibcon#about to read 5, iclass 31, count 0 2006.280.07:36:31.25#ibcon#read 5, iclass 31, count 0 2006.280.07:36:31.25#ibcon#about to read 6, iclass 31, count 0 2006.280.07:36:31.25#ibcon#read 6, iclass 31, count 0 2006.280.07:36:31.25#ibcon#end of sib2, iclass 31, count 0 2006.280.07:36:31.25#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:36:31.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:36:31.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:36:31.25#ibcon#*before write, iclass 31, count 0 2006.280.07:36:31.25#ibcon#enter sib2, iclass 31, count 0 2006.280.07:36:31.25#ibcon#flushed, iclass 31, count 0 2006.280.07:36:31.25#ibcon#about to write, iclass 31, count 0 2006.280.07:36:31.25#ibcon#wrote, iclass 31, count 0 2006.280.07:36:31.25#ibcon#about to read 3, iclass 31, count 0 2006.280.07:36:31.29#ibcon#read 3, iclass 31, count 0 2006.280.07:36:31.29#ibcon#about to read 4, iclass 31, count 0 2006.280.07:36:31.29#ibcon#read 4, iclass 31, count 0 2006.280.07:36:31.29#ibcon#about to read 5, iclass 31, count 0 2006.280.07:36:31.29#ibcon#read 5, iclass 31, count 0 2006.280.07:36:31.29#ibcon#about to read 6, iclass 31, count 0 2006.280.07:36:31.29#ibcon#read 6, iclass 31, count 0 2006.280.07:36:31.29#ibcon#end of sib2, iclass 31, count 0 2006.280.07:36:31.29#ibcon#*after write, iclass 31, count 0 2006.280.07:36:31.29#ibcon#*before return 0, iclass 31, count 0 2006.280.07:36:31.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:36:31.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:36:31.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:36:31.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:36:31.29$vc4f8/vb=1,4 2006.280.07:36:31.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.07:36:31.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.07:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:31.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:36:31.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:36:31.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:36:31.29#ibcon#enter wrdev, iclass 33, count 2 2006.280.07:36:31.29#ibcon#first serial, iclass 33, count 2 2006.280.07:36:31.29#ibcon#enter sib2, iclass 33, count 2 2006.280.07:36:31.29#ibcon#flushed, iclass 33, count 2 2006.280.07:36:31.29#ibcon#about to write, iclass 33, count 2 2006.280.07:36:31.29#ibcon#wrote, iclass 33, count 2 2006.280.07:36:31.29#ibcon#about to read 3, iclass 33, count 2 2006.280.07:36:31.31#ibcon#read 3, iclass 33, count 2 2006.280.07:36:31.31#ibcon#about to read 4, iclass 33, count 2 2006.280.07:36:31.31#ibcon#read 4, iclass 33, count 2 2006.280.07:36:31.31#ibcon#about to read 5, iclass 33, count 2 2006.280.07:36:31.31#ibcon#read 5, iclass 33, count 2 2006.280.07:36:31.31#ibcon#about to read 6, iclass 33, count 2 2006.280.07:36:31.31#ibcon#read 6, iclass 33, count 2 2006.280.07:36:31.31#ibcon#end of sib2, iclass 33, count 2 2006.280.07:36:31.31#ibcon#*mode == 0, iclass 33, count 2 2006.280.07:36:31.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.07:36:31.31#ibcon#[27=AT01-04\r\n] 2006.280.07:36:31.31#ibcon#*before write, iclass 33, count 2 2006.280.07:36:31.31#ibcon#enter sib2, iclass 33, count 2 2006.280.07:36:31.31#ibcon#flushed, iclass 33, count 2 2006.280.07:36:31.31#ibcon#about to write, iclass 33, count 2 2006.280.07:36:31.31#ibcon#wrote, iclass 33, count 2 2006.280.07:36:31.31#ibcon#about to read 3, iclass 33, count 2 2006.280.07:36:31.34#ibcon#read 3, iclass 33, count 2 2006.280.07:36:31.34#ibcon#about to read 4, iclass 33, count 2 2006.280.07:36:31.34#ibcon#read 4, iclass 33, count 2 2006.280.07:36:31.34#ibcon#about to read 5, iclass 33, count 2 2006.280.07:36:31.34#ibcon#read 5, iclass 33, count 2 2006.280.07:36:31.34#ibcon#about to read 6, iclass 33, count 2 2006.280.07:36:31.34#ibcon#read 6, iclass 33, count 2 2006.280.07:36:31.34#ibcon#end of sib2, iclass 33, count 2 2006.280.07:36:31.34#ibcon#*after write, iclass 33, count 2 2006.280.07:36:31.34#ibcon#*before return 0, iclass 33, count 2 2006.280.07:36:31.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:36:31.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:36:31.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.07:36:31.34#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:31.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:36:31.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:36:31.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:36:31.46#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:36:31.46#ibcon#first serial, iclass 33, count 0 2006.280.07:36:31.46#ibcon#enter sib2, iclass 33, count 0 2006.280.07:36:31.46#ibcon#flushed, iclass 33, count 0 2006.280.07:36:31.46#ibcon#about to write, iclass 33, count 0 2006.280.07:36:31.46#ibcon#wrote, iclass 33, count 0 2006.280.07:36:31.46#ibcon#about to read 3, iclass 33, count 0 2006.280.07:36:31.48#ibcon#read 3, iclass 33, count 0 2006.280.07:36:31.48#ibcon#about to read 4, iclass 33, count 0 2006.280.07:36:31.48#ibcon#read 4, iclass 33, count 0 2006.280.07:36:31.48#ibcon#about to read 5, iclass 33, count 0 2006.280.07:36:31.48#ibcon#read 5, iclass 33, count 0 2006.280.07:36:31.48#ibcon#about to read 6, iclass 33, count 0 2006.280.07:36:31.48#ibcon#read 6, iclass 33, count 0 2006.280.07:36:31.48#ibcon#end of sib2, iclass 33, count 0 2006.280.07:36:31.48#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:36:31.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:36:31.48#ibcon#[27=USB\r\n] 2006.280.07:36:31.48#ibcon#*before write, iclass 33, count 0 2006.280.07:36:31.48#ibcon#enter sib2, iclass 33, count 0 2006.280.07:36:31.48#ibcon#flushed, iclass 33, count 0 2006.280.07:36:31.48#ibcon#about to write, iclass 33, count 0 2006.280.07:36:31.48#ibcon#wrote, iclass 33, count 0 2006.280.07:36:31.48#ibcon#about to read 3, iclass 33, count 0 2006.280.07:36:31.51#ibcon#read 3, iclass 33, count 0 2006.280.07:36:31.51#ibcon#about to read 4, iclass 33, count 0 2006.280.07:36:31.51#ibcon#read 4, iclass 33, count 0 2006.280.07:36:31.51#ibcon#about to read 5, iclass 33, count 0 2006.280.07:36:31.51#ibcon#read 5, iclass 33, count 0 2006.280.07:36:31.51#ibcon#about to read 6, iclass 33, count 0 2006.280.07:36:31.51#ibcon#read 6, iclass 33, count 0 2006.280.07:36:31.51#ibcon#end of sib2, iclass 33, count 0 2006.280.07:36:31.51#ibcon#*after write, iclass 33, count 0 2006.280.07:36:31.51#ibcon#*before return 0, iclass 33, count 0 2006.280.07:36:31.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:36:31.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:36:31.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:36:31.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:36:31.51$vc4f8/vblo=2,640.99 2006.280.07:36:31.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.07:36:31.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.07:36:31.51#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:31.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:31.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:31.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:31.51#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:36:31.51#ibcon#first serial, iclass 35, count 0 2006.280.07:36:31.51#ibcon#enter sib2, iclass 35, count 0 2006.280.07:36:31.51#ibcon#flushed, iclass 35, count 0 2006.280.07:36:31.51#ibcon#about to write, iclass 35, count 0 2006.280.07:36:31.51#ibcon#wrote, iclass 35, count 0 2006.280.07:36:31.51#ibcon#about to read 3, iclass 35, count 0 2006.280.07:36:31.53#ibcon#read 3, iclass 35, count 0 2006.280.07:36:31.54#ibcon#about to read 4, iclass 35, count 0 2006.280.07:36:31.54#ibcon#read 4, iclass 35, count 0 2006.280.07:36:31.54#ibcon#about to read 5, iclass 35, count 0 2006.280.07:36:31.54#ibcon#read 5, iclass 35, count 0 2006.280.07:36:31.54#ibcon#about to read 6, iclass 35, count 0 2006.280.07:36:31.54#ibcon#read 6, iclass 35, count 0 2006.280.07:36:31.54#ibcon#end of sib2, iclass 35, count 0 2006.280.07:36:31.54#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:36:31.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:36:31.54#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:36:31.54#ibcon#*before write, iclass 35, count 0 2006.280.07:36:31.54#ibcon#enter sib2, iclass 35, count 0 2006.280.07:36:31.54#ibcon#flushed, iclass 35, count 0 2006.280.07:36:31.54#ibcon#about to write, iclass 35, count 0 2006.280.07:36:31.54#ibcon#wrote, iclass 35, count 0 2006.280.07:36:31.54#ibcon#about to read 3, iclass 35, count 0 2006.280.07:36:31.58#ibcon#read 3, iclass 35, count 0 2006.280.07:36:31.58#ibcon#about to read 4, iclass 35, count 0 2006.280.07:36:31.58#ibcon#read 4, iclass 35, count 0 2006.280.07:36:31.58#ibcon#about to read 5, iclass 35, count 0 2006.280.07:36:31.58#ibcon#read 5, iclass 35, count 0 2006.280.07:36:31.58#ibcon#about to read 6, iclass 35, count 0 2006.280.07:36:31.58#ibcon#read 6, iclass 35, count 0 2006.280.07:36:31.58#ibcon#end of sib2, iclass 35, count 0 2006.280.07:36:31.58#ibcon#*after write, iclass 35, count 0 2006.280.07:36:31.58#ibcon#*before return 0, iclass 35, count 0 2006.280.07:36:31.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:31.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:36:31.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:36:31.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:36:31.58$vc4f8/vb=2,5 2006.280.07:36:31.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.07:36:31.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.07:36:31.58#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:31.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:31.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:31.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:31.63#ibcon#enter wrdev, iclass 37, count 2 2006.280.07:36:31.63#ibcon#first serial, iclass 37, count 2 2006.280.07:36:31.63#ibcon#enter sib2, iclass 37, count 2 2006.280.07:36:31.63#ibcon#flushed, iclass 37, count 2 2006.280.07:36:31.63#ibcon#about to write, iclass 37, count 2 2006.280.07:36:31.63#ibcon#wrote, iclass 37, count 2 2006.280.07:36:31.63#ibcon#about to read 3, iclass 37, count 2 2006.280.07:36:31.65#ibcon#read 3, iclass 37, count 2 2006.280.07:36:31.65#ibcon#about to read 4, iclass 37, count 2 2006.280.07:36:31.65#ibcon#read 4, iclass 37, count 2 2006.280.07:36:31.65#ibcon#about to read 5, iclass 37, count 2 2006.280.07:36:31.65#ibcon#read 5, iclass 37, count 2 2006.280.07:36:31.65#ibcon#about to read 6, iclass 37, count 2 2006.280.07:36:31.65#ibcon#read 6, iclass 37, count 2 2006.280.07:36:31.65#ibcon#end of sib2, iclass 37, count 2 2006.280.07:36:31.65#ibcon#*mode == 0, iclass 37, count 2 2006.280.07:36:31.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.07:36:31.65#ibcon#[27=AT02-05\r\n] 2006.280.07:36:31.65#ibcon#*before write, iclass 37, count 2 2006.280.07:36:31.65#ibcon#enter sib2, iclass 37, count 2 2006.280.07:36:31.65#ibcon#flushed, iclass 37, count 2 2006.280.07:36:31.65#ibcon#about to write, iclass 37, count 2 2006.280.07:36:31.65#ibcon#wrote, iclass 37, count 2 2006.280.07:36:31.65#ibcon#about to read 3, iclass 37, count 2 2006.280.07:36:31.68#ibcon#read 3, iclass 37, count 2 2006.280.07:36:31.68#ibcon#about to read 4, iclass 37, count 2 2006.280.07:36:31.68#ibcon#read 4, iclass 37, count 2 2006.280.07:36:31.68#ibcon#about to read 5, iclass 37, count 2 2006.280.07:36:31.68#ibcon#read 5, iclass 37, count 2 2006.280.07:36:31.68#ibcon#about to read 6, iclass 37, count 2 2006.280.07:36:31.68#ibcon#read 6, iclass 37, count 2 2006.280.07:36:31.68#ibcon#end of sib2, iclass 37, count 2 2006.280.07:36:31.68#ibcon#*after write, iclass 37, count 2 2006.280.07:36:31.68#ibcon#*before return 0, iclass 37, count 2 2006.280.07:36:31.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:31.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:36:31.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.07:36:31.68#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:31.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:31.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:31.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:31.80#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:36:31.80#ibcon#first serial, iclass 37, count 0 2006.280.07:36:31.80#ibcon#enter sib2, iclass 37, count 0 2006.280.07:36:31.80#ibcon#flushed, iclass 37, count 0 2006.280.07:36:31.80#ibcon#about to write, iclass 37, count 0 2006.280.07:36:31.80#ibcon#wrote, iclass 37, count 0 2006.280.07:36:31.80#ibcon#about to read 3, iclass 37, count 0 2006.280.07:36:31.82#ibcon#read 3, iclass 37, count 0 2006.280.07:36:31.82#ibcon#about to read 4, iclass 37, count 0 2006.280.07:36:31.82#ibcon#read 4, iclass 37, count 0 2006.280.07:36:31.82#ibcon#about to read 5, iclass 37, count 0 2006.280.07:36:31.82#ibcon#read 5, iclass 37, count 0 2006.280.07:36:31.82#ibcon#about to read 6, iclass 37, count 0 2006.280.07:36:31.82#ibcon#read 6, iclass 37, count 0 2006.280.07:36:31.82#ibcon#end of sib2, iclass 37, count 0 2006.280.07:36:31.82#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:36:31.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:36:31.82#ibcon#[27=USB\r\n] 2006.280.07:36:31.82#ibcon#*before write, iclass 37, count 0 2006.280.07:36:31.82#ibcon#enter sib2, iclass 37, count 0 2006.280.07:36:31.82#ibcon#flushed, iclass 37, count 0 2006.280.07:36:31.82#ibcon#about to write, iclass 37, count 0 2006.280.07:36:31.82#ibcon#wrote, iclass 37, count 0 2006.280.07:36:31.82#ibcon#about to read 3, iclass 37, count 0 2006.280.07:36:31.83#abcon#<5=/14 2.3 5.3 21.95 60 986.7\r\n> 2006.280.07:36:31.85#abcon#{5=INTERFACE CLEAR} 2006.280.07:36:31.85#ibcon#read 3, iclass 37, count 0 2006.280.07:36:31.85#ibcon#about to read 4, iclass 37, count 0 2006.280.07:36:31.85#ibcon#read 4, iclass 37, count 0 2006.280.07:36:31.85#ibcon#about to read 5, iclass 37, count 0 2006.280.07:36:31.85#ibcon#read 5, iclass 37, count 0 2006.280.07:36:31.85#ibcon#about to read 6, iclass 37, count 0 2006.280.07:36:31.85#ibcon#read 6, iclass 37, count 0 2006.280.07:36:31.85#ibcon#end of sib2, iclass 37, count 0 2006.280.07:36:31.85#ibcon#*after write, iclass 37, count 0 2006.280.07:36:31.85#ibcon#*before return 0, iclass 37, count 0 2006.280.07:36:31.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:31.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:36:31.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:36:31.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:36:31.85$vc4f8/vblo=3,656.99 2006.280.07:36:31.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:36:31.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:36:31.85#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:31.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:36:31.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:36:31.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:36:31.85#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:36:31.85#ibcon#first serial, iclass 4, count 0 2006.280.07:36:31.85#ibcon#enter sib2, iclass 4, count 0 2006.280.07:36:31.85#ibcon#flushed, iclass 4, count 0 2006.280.07:36:31.85#ibcon#about to write, iclass 4, count 0 2006.280.07:36:31.85#ibcon#wrote, iclass 4, count 0 2006.280.07:36:31.85#ibcon#about to read 3, iclass 4, count 0 2006.280.07:36:31.87#ibcon#read 3, iclass 4, count 0 2006.280.07:36:31.87#ibcon#about to read 4, iclass 4, count 0 2006.280.07:36:31.87#ibcon#read 4, iclass 4, count 0 2006.280.07:36:31.87#ibcon#about to read 5, iclass 4, count 0 2006.280.07:36:31.87#ibcon#read 5, iclass 4, count 0 2006.280.07:36:31.87#ibcon#about to read 6, iclass 4, count 0 2006.280.07:36:31.87#ibcon#read 6, iclass 4, count 0 2006.280.07:36:31.87#ibcon#end of sib2, iclass 4, count 0 2006.280.07:36:31.87#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:36:31.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:36:31.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:36:31.87#ibcon#*before write, iclass 4, count 0 2006.280.07:36:31.87#ibcon#enter sib2, iclass 4, count 0 2006.280.07:36:31.87#ibcon#flushed, iclass 4, count 0 2006.280.07:36:31.87#ibcon#about to write, iclass 4, count 0 2006.280.07:36:31.87#ibcon#wrote, iclass 4, count 0 2006.280.07:36:31.87#ibcon#about to read 3, iclass 4, count 0 2006.280.07:36:31.91#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:36:31.91#ibcon#read 3, iclass 4, count 0 2006.280.07:36:31.91#ibcon#about to read 4, iclass 4, count 0 2006.280.07:36:31.91#ibcon#read 4, iclass 4, count 0 2006.280.07:36:31.91#ibcon#about to read 5, iclass 4, count 0 2006.280.07:36:31.91#ibcon#read 5, iclass 4, count 0 2006.280.07:36:31.91#ibcon#about to read 6, iclass 4, count 0 2006.280.07:36:31.91#ibcon#read 6, iclass 4, count 0 2006.280.07:36:31.91#ibcon#end of sib2, iclass 4, count 0 2006.280.07:36:31.91#ibcon#*after write, iclass 4, count 0 2006.280.07:36:31.91#ibcon#*before return 0, iclass 4, count 0 2006.280.07:36:31.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:36:31.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:36:31.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:36:31.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:36:31.91$vc4f8/vb=3,4 2006.280.07:36:31.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.07:36:31.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.07:36:31.91#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:31.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:31.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:31.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:31.97#ibcon#enter wrdev, iclass 7, count 2 2006.280.07:36:31.97#ibcon#first serial, iclass 7, count 2 2006.280.07:36:31.97#ibcon#enter sib2, iclass 7, count 2 2006.280.07:36:31.97#ibcon#flushed, iclass 7, count 2 2006.280.07:36:31.97#ibcon#about to write, iclass 7, count 2 2006.280.07:36:31.97#ibcon#wrote, iclass 7, count 2 2006.280.07:36:31.97#ibcon#about to read 3, iclass 7, count 2 2006.280.07:36:31.99#ibcon#read 3, iclass 7, count 2 2006.280.07:36:31.99#ibcon#about to read 4, iclass 7, count 2 2006.280.07:36:31.99#ibcon#read 4, iclass 7, count 2 2006.280.07:36:31.99#ibcon#about to read 5, iclass 7, count 2 2006.280.07:36:31.99#ibcon#read 5, iclass 7, count 2 2006.280.07:36:31.99#ibcon#about to read 6, iclass 7, count 2 2006.280.07:36:31.99#ibcon#read 6, iclass 7, count 2 2006.280.07:36:31.99#ibcon#end of sib2, iclass 7, count 2 2006.280.07:36:31.99#ibcon#*mode == 0, iclass 7, count 2 2006.280.07:36:31.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.07:36:31.99#ibcon#[27=AT03-04\r\n] 2006.280.07:36:31.99#ibcon#*before write, iclass 7, count 2 2006.280.07:36:31.99#ibcon#enter sib2, iclass 7, count 2 2006.280.07:36:31.99#ibcon#flushed, iclass 7, count 2 2006.280.07:36:31.99#ibcon#about to write, iclass 7, count 2 2006.280.07:36:31.99#ibcon#wrote, iclass 7, count 2 2006.280.07:36:31.99#ibcon#about to read 3, iclass 7, count 2 2006.280.07:36:32.02#ibcon#read 3, iclass 7, count 2 2006.280.07:36:32.02#ibcon#about to read 4, iclass 7, count 2 2006.280.07:36:32.02#ibcon#read 4, iclass 7, count 2 2006.280.07:36:32.02#ibcon#about to read 5, iclass 7, count 2 2006.280.07:36:32.02#ibcon#read 5, iclass 7, count 2 2006.280.07:36:32.02#ibcon#about to read 6, iclass 7, count 2 2006.280.07:36:32.02#ibcon#read 6, iclass 7, count 2 2006.280.07:36:32.02#ibcon#end of sib2, iclass 7, count 2 2006.280.07:36:32.02#ibcon#*after write, iclass 7, count 2 2006.280.07:36:32.02#ibcon#*before return 0, iclass 7, count 2 2006.280.07:36:32.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:32.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:36:32.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.07:36:32.02#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:32.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:32.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:32.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:32.14#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:36:32.14#ibcon#first serial, iclass 7, count 0 2006.280.07:36:32.14#ibcon#enter sib2, iclass 7, count 0 2006.280.07:36:32.14#ibcon#flushed, iclass 7, count 0 2006.280.07:36:32.14#ibcon#about to write, iclass 7, count 0 2006.280.07:36:32.14#ibcon#wrote, iclass 7, count 0 2006.280.07:36:32.14#ibcon#about to read 3, iclass 7, count 0 2006.280.07:36:32.16#ibcon#read 3, iclass 7, count 0 2006.280.07:36:32.16#ibcon#about to read 4, iclass 7, count 0 2006.280.07:36:32.16#ibcon#read 4, iclass 7, count 0 2006.280.07:36:32.16#ibcon#about to read 5, iclass 7, count 0 2006.280.07:36:32.16#ibcon#read 5, iclass 7, count 0 2006.280.07:36:32.16#ibcon#about to read 6, iclass 7, count 0 2006.280.07:36:32.16#ibcon#read 6, iclass 7, count 0 2006.280.07:36:32.16#ibcon#end of sib2, iclass 7, count 0 2006.280.07:36:32.16#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:36:32.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:36:32.16#ibcon#[27=USB\r\n] 2006.280.07:36:32.16#ibcon#*before write, iclass 7, count 0 2006.280.07:36:32.16#ibcon#enter sib2, iclass 7, count 0 2006.280.07:36:32.16#ibcon#flushed, iclass 7, count 0 2006.280.07:36:32.16#ibcon#about to write, iclass 7, count 0 2006.280.07:36:32.16#ibcon#wrote, iclass 7, count 0 2006.280.07:36:32.16#ibcon#about to read 3, iclass 7, count 0 2006.280.07:36:32.19#ibcon#read 3, iclass 7, count 0 2006.280.07:36:32.19#ibcon#about to read 4, iclass 7, count 0 2006.280.07:36:32.19#ibcon#read 4, iclass 7, count 0 2006.280.07:36:32.19#ibcon#about to read 5, iclass 7, count 0 2006.280.07:36:32.19#ibcon#read 5, iclass 7, count 0 2006.280.07:36:32.19#ibcon#about to read 6, iclass 7, count 0 2006.280.07:36:32.19#ibcon#read 6, iclass 7, count 0 2006.280.07:36:32.19#ibcon#end of sib2, iclass 7, count 0 2006.280.07:36:32.19#ibcon#*after write, iclass 7, count 0 2006.280.07:36:32.19#ibcon#*before return 0, iclass 7, count 0 2006.280.07:36:32.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:32.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:36:32.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:36:32.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:36:32.19$vc4f8/vblo=4,712.99 2006.280.07:36:32.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.07:36:32.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.07:36:32.19#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:32.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:32.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:32.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:32.19#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:36:32.19#ibcon#first serial, iclass 11, count 0 2006.280.07:36:32.19#ibcon#enter sib2, iclass 11, count 0 2006.280.07:36:32.19#ibcon#flushed, iclass 11, count 0 2006.280.07:36:32.19#ibcon#about to write, iclass 11, count 0 2006.280.07:36:32.19#ibcon#wrote, iclass 11, count 0 2006.280.07:36:32.19#ibcon#about to read 3, iclass 11, count 0 2006.280.07:36:32.21#ibcon#read 3, iclass 11, count 0 2006.280.07:36:32.21#ibcon#about to read 4, iclass 11, count 0 2006.280.07:36:32.21#ibcon#read 4, iclass 11, count 0 2006.280.07:36:32.21#ibcon#about to read 5, iclass 11, count 0 2006.280.07:36:32.21#ibcon#read 5, iclass 11, count 0 2006.280.07:36:32.21#ibcon#about to read 6, iclass 11, count 0 2006.280.07:36:32.21#ibcon#read 6, iclass 11, count 0 2006.280.07:36:32.21#ibcon#end of sib2, iclass 11, count 0 2006.280.07:36:32.21#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:36:32.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:36:32.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:36:32.21#ibcon#*before write, iclass 11, count 0 2006.280.07:36:32.21#ibcon#enter sib2, iclass 11, count 0 2006.280.07:36:32.21#ibcon#flushed, iclass 11, count 0 2006.280.07:36:32.21#ibcon#about to write, iclass 11, count 0 2006.280.07:36:32.21#ibcon#wrote, iclass 11, count 0 2006.280.07:36:32.21#ibcon#about to read 3, iclass 11, count 0 2006.280.07:36:32.25#ibcon#read 3, iclass 11, count 0 2006.280.07:36:32.25#ibcon#about to read 4, iclass 11, count 0 2006.280.07:36:32.25#ibcon#read 4, iclass 11, count 0 2006.280.07:36:32.25#ibcon#about to read 5, iclass 11, count 0 2006.280.07:36:32.25#ibcon#read 5, iclass 11, count 0 2006.280.07:36:32.25#ibcon#about to read 6, iclass 11, count 0 2006.280.07:36:32.25#ibcon#read 6, iclass 11, count 0 2006.280.07:36:32.25#ibcon#end of sib2, iclass 11, count 0 2006.280.07:36:32.25#ibcon#*after write, iclass 11, count 0 2006.280.07:36:32.25#ibcon#*before return 0, iclass 11, count 0 2006.280.07:36:32.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:32.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:36:32.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:36:32.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:36:32.25$vc4f8/vb=4,4 2006.280.07:36:32.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.07:36:32.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.07:36:32.25#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:32.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:32.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:32.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:32.31#ibcon#enter wrdev, iclass 13, count 2 2006.280.07:36:32.31#ibcon#first serial, iclass 13, count 2 2006.280.07:36:32.31#ibcon#enter sib2, iclass 13, count 2 2006.280.07:36:32.31#ibcon#flushed, iclass 13, count 2 2006.280.07:36:32.31#ibcon#about to write, iclass 13, count 2 2006.280.07:36:32.31#ibcon#wrote, iclass 13, count 2 2006.280.07:36:32.31#ibcon#about to read 3, iclass 13, count 2 2006.280.07:36:32.33#ibcon#read 3, iclass 13, count 2 2006.280.07:36:32.33#ibcon#about to read 4, iclass 13, count 2 2006.280.07:36:32.33#ibcon#read 4, iclass 13, count 2 2006.280.07:36:32.33#ibcon#about to read 5, iclass 13, count 2 2006.280.07:36:32.33#ibcon#read 5, iclass 13, count 2 2006.280.07:36:32.33#ibcon#about to read 6, iclass 13, count 2 2006.280.07:36:32.33#ibcon#read 6, iclass 13, count 2 2006.280.07:36:32.33#ibcon#end of sib2, iclass 13, count 2 2006.280.07:36:32.33#ibcon#*mode == 0, iclass 13, count 2 2006.280.07:36:32.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.07:36:32.33#ibcon#[27=AT04-04\r\n] 2006.280.07:36:32.33#ibcon#*before write, iclass 13, count 2 2006.280.07:36:32.33#ibcon#enter sib2, iclass 13, count 2 2006.280.07:36:32.33#ibcon#flushed, iclass 13, count 2 2006.280.07:36:32.33#ibcon#about to write, iclass 13, count 2 2006.280.07:36:32.33#ibcon#wrote, iclass 13, count 2 2006.280.07:36:32.33#ibcon#about to read 3, iclass 13, count 2 2006.280.07:36:32.37#ibcon#read 3, iclass 13, count 2 2006.280.07:36:32.37#ibcon#about to read 4, iclass 13, count 2 2006.280.07:36:32.37#ibcon#read 4, iclass 13, count 2 2006.280.07:36:32.37#ibcon#about to read 5, iclass 13, count 2 2006.280.07:36:32.37#ibcon#read 5, iclass 13, count 2 2006.280.07:36:32.37#ibcon#about to read 6, iclass 13, count 2 2006.280.07:36:32.37#ibcon#read 6, iclass 13, count 2 2006.280.07:36:32.37#ibcon#end of sib2, iclass 13, count 2 2006.280.07:36:32.37#ibcon#*after write, iclass 13, count 2 2006.280.07:36:32.37#ibcon#*before return 0, iclass 13, count 2 2006.280.07:36:32.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:32.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:36:32.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.07:36:32.37#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:32.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:32.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:32.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:32.49#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:36:32.49#ibcon#first serial, iclass 13, count 0 2006.280.07:36:32.49#ibcon#enter sib2, iclass 13, count 0 2006.280.07:36:32.49#ibcon#flushed, iclass 13, count 0 2006.280.07:36:32.49#ibcon#about to write, iclass 13, count 0 2006.280.07:36:32.49#ibcon#wrote, iclass 13, count 0 2006.280.07:36:32.49#ibcon#about to read 3, iclass 13, count 0 2006.280.07:36:32.51#ibcon#read 3, iclass 13, count 0 2006.280.07:36:32.51#ibcon#about to read 4, iclass 13, count 0 2006.280.07:36:32.51#ibcon#read 4, iclass 13, count 0 2006.280.07:36:32.51#ibcon#about to read 5, iclass 13, count 0 2006.280.07:36:32.51#ibcon#read 5, iclass 13, count 0 2006.280.07:36:32.51#ibcon#about to read 6, iclass 13, count 0 2006.280.07:36:32.51#ibcon#read 6, iclass 13, count 0 2006.280.07:36:32.51#ibcon#end of sib2, iclass 13, count 0 2006.280.07:36:32.51#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:36:32.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:36:32.51#ibcon#[27=USB\r\n] 2006.280.07:36:32.51#ibcon#*before write, iclass 13, count 0 2006.280.07:36:32.51#ibcon#enter sib2, iclass 13, count 0 2006.280.07:36:32.51#ibcon#flushed, iclass 13, count 0 2006.280.07:36:32.51#ibcon#about to write, iclass 13, count 0 2006.280.07:36:32.51#ibcon#wrote, iclass 13, count 0 2006.280.07:36:32.51#ibcon#about to read 3, iclass 13, count 0 2006.280.07:36:32.54#ibcon#read 3, iclass 13, count 0 2006.280.07:36:32.54#ibcon#about to read 4, iclass 13, count 0 2006.280.07:36:32.54#ibcon#read 4, iclass 13, count 0 2006.280.07:36:32.54#ibcon#about to read 5, iclass 13, count 0 2006.280.07:36:32.54#ibcon#read 5, iclass 13, count 0 2006.280.07:36:32.54#ibcon#about to read 6, iclass 13, count 0 2006.280.07:36:32.54#ibcon#read 6, iclass 13, count 0 2006.280.07:36:32.54#ibcon#end of sib2, iclass 13, count 0 2006.280.07:36:32.54#ibcon#*after write, iclass 13, count 0 2006.280.07:36:32.54#ibcon#*before return 0, iclass 13, count 0 2006.280.07:36:32.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:32.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:36:32.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:36:32.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:36:32.54$vc4f8/vblo=5,744.99 2006.280.07:36:32.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:36:32.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:36:32.54#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:32.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:32.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:32.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:32.54#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:36:32.54#ibcon#first serial, iclass 15, count 0 2006.280.07:36:32.54#ibcon#enter sib2, iclass 15, count 0 2006.280.07:36:32.54#ibcon#flushed, iclass 15, count 0 2006.280.07:36:32.54#ibcon#about to write, iclass 15, count 0 2006.280.07:36:32.54#ibcon#wrote, iclass 15, count 0 2006.280.07:36:32.54#ibcon#about to read 3, iclass 15, count 0 2006.280.07:36:32.56#ibcon#read 3, iclass 15, count 0 2006.280.07:36:32.56#ibcon#about to read 4, iclass 15, count 0 2006.280.07:36:32.56#ibcon#read 4, iclass 15, count 0 2006.280.07:36:32.56#ibcon#about to read 5, iclass 15, count 0 2006.280.07:36:32.56#ibcon#read 5, iclass 15, count 0 2006.280.07:36:32.56#ibcon#about to read 6, iclass 15, count 0 2006.280.07:36:32.56#ibcon#read 6, iclass 15, count 0 2006.280.07:36:32.56#ibcon#end of sib2, iclass 15, count 0 2006.280.07:36:32.56#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:36:32.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:36:32.56#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:36:32.56#ibcon#*before write, iclass 15, count 0 2006.280.07:36:32.56#ibcon#enter sib2, iclass 15, count 0 2006.280.07:36:32.56#ibcon#flushed, iclass 15, count 0 2006.280.07:36:32.56#ibcon#about to write, iclass 15, count 0 2006.280.07:36:32.56#ibcon#wrote, iclass 15, count 0 2006.280.07:36:32.56#ibcon#about to read 3, iclass 15, count 0 2006.280.07:36:32.60#ibcon#read 3, iclass 15, count 0 2006.280.07:36:32.60#ibcon#about to read 4, iclass 15, count 0 2006.280.07:36:32.60#ibcon#read 4, iclass 15, count 0 2006.280.07:36:32.60#ibcon#about to read 5, iclass 15, count 0 2006.280.07:36:32.60#ibcon#read 5, iclass 15, count 0 2006.280.07:36:32.60#ibcon#about to read 6, iclass 15, count 0 2006.280.07:36:32.60#ibcon#read 6, iclass 15, count 0 2006.280.07:36:32.60#ibcon#end of sib2, iclass 15, count 0 2006.280.07:36:32.60#ibcon#*after write, iclass 15, count 0 2006.280.07:36:32.60#ibcon#*before return 0, iclass 15, count 0 2006.280.07:36:32.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:32.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:36:32.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:36:32.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:36:32.60$vc4f8/vb=5,4 2006.280.07:36:32.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.07:36:32.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.07:36:32.61#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:32.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:32.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:32.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:32.66#ibcon#enter wrdev, iclass 17, count 2 2006.280.07:36:32.66#ibcon#first serial, iclass 17, count 2 2006.280.07:36:32.66#ibcon#enter sib2, iclass 17, count 2 2006.280.07:36:32.66#ibcon#flushed, iclass 17, count 2 2006.280.07:36:32.66#ibcon#about to write, iclass 17, count 2 2006.280.07:36:32.66#ibcon#wrote, iclass 17, count 2 2006.280.07:36:32.66#ibcon#about to read 3, iclass 17, count 2 2006.280.07:36:32.68#ibcon#read 3, iclass 17, count 2 2006.280.07:36:32.68#ibcon#about to read 4, iclass 17, count 2 2006.280.07:36:32.68#ibcon#read 4, iclass 17, count 2 2006.280.07:36:32.68#ibcon#about to read 5, iclass 17, count 2 2006.280.07:36:32.68#ibcon#read 5, iclass 17, count 2 2006.280.07:36:32.68#ibcon#about to read 6, iclass 17, count 2 2006.280.07:36:32.68#ibcon#read 6, iclass 17, count 2 2006.280.07:36:32.68#ibcon#end of sib2, iclass 17, count 2 2006.280.07:36:32.68#ibcon#*mode == 0, iclass 17, count 2 2006.280.07:36:32.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.07:36:32.68#ibcon#[27=AT05-04\r\n] 2006.280.07:36:32.68#ibcon#*before write, iclass 17, count 2 2006.280.07:36:32.68#ibcon#enter sib2, iclass 17, count 2 2006.280.07:36:32.68#ibcon#flushed, iclass 17, count 2 2006.280.07:36:32.68#ibcon#about to write, iclass 17, count 2 2006.280.07:36:32.68#ibcon#wrote, iclass 17, count 2 2006.280.07:36:32.68#ibcon#about to read 3, iclass 17, count 2 2006.280.07:36:32.71#ibcon#read 3, iclass 17, count 2 2006.280.07:36:32.71#ibcon#about to read 4, iclass 17, count 2 2006.280.07:36:32.71#ibcon#read 4, iclass 17, count 2 2006.280.07:36:32.71#ibcon#about to read 5, iclass 17, count 2 2006.280.07:36:32.71#ibcon#read 5, iclass 17, count 2 2006.280.07:36:32.71#ibcon#about to read 6, iclass 17, count 2 2006.280.07:36:32.71#ibcon#read 6, iclass 17, count 2 2006.280.07:36:32.71#ibcon#end of sib2, iclass 17, count 2 2006.280.07:36:32.71#ibcon#*after write, iclass 17, count 2 2006.280.07:36:32.71#ibcon#*before return 0, iclass 17, count 2 2006.280.07:36:32.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:32.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:36:32.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.07:36:32.71#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:32.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:32.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:32.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:32.83#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:36:32.83#ibcon#first serial, iclass 17, count 0 2006.280.07:36:32.83#ibcon#enter sib2, iclass 17, count 0 2006.280.07:36:32.83#ibcon#flushed, iclass 17, count 0 2006.280.07:36:32.83#ibcon#about to write, iclass 17, count 0 2006.280.07:36:32.83#ibcon#wrote, iclass 17, count 0 2006.280.07:36:32.83#ibcon#about to read 3, iclass 17, count 0 2006.280.07:36:32.85#ibcon#read 3, iclass 17, count 0 2006.280.07:36:32.85#ibcon#about to read 4, iclass 17, count 0 2006.280.07:36:32.85#ibcon#read 4, iclass 17, count 0 2006.280.07:36:32.85#ibcon#about to read 5, iclass 17, count 0 2006.280.07:36:32.85#ibcon#read 5, iclass 17, count 0 2006.280.07:36:32.85#ibcon#about to read 6, iclass 17, count 0 2006.280.07:36:32.85#ibcon#read 6, iclass 17, count 0 2006.280.07:36:32.85#ibcon#end of sib2, iclass 17, count 0 2006.280.07:36:32.85#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:36:32.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:36:32.85#ibcon#[27=USB\r\n] 2006.280.07:36:32.85#ibcon#*before write, iclass 17, count 0 2006.280.07:36:32.85#ibcon#enter sib2, iclass 17, count 0 2006.280.07:36:32.85#ibcon#flushed, iclass 17, count 0 2006.280.07:36:32.85#ibcon#about to write, iclass 17, count 0 2006.280.07:36:32.85#ibcon#wrote, iclass 17, count 0 2006.280.07:36:32.85#ibcon#about to read 3, iclass 17, count 0 2006.280.07:36:32.88#ibcon#read 3, iclass 17, count 0 2006.280.07:36:32.88#ibcon#about to read 4, iclass 17, count 0 2006.280.07:36:32.88#ibcon#read 4, iclass 17, count 0 2006.280.07:36:32.88#ibcon#about to read 5, iclass 17, count 0 2006.280.07:36:32.88#ibcon#read 5, iclass 17, count 0 2006.280.07:36:32.88#ibcon#about to read 6, iclass 17, count 0 2006.280.07:36:32.88#ibcon#read 6, iclass 17, count 0 2006.280.07:36:32.88#ibcon#end of sib2, iclass 17, count 0 2006.280.07:36:32.88#ibcon#*after write, iclass 17, count 0 2006.280.07:36:32.88#ibcon#*before return 0, iclass 17, count 0 2006.280.07:36:32.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:32.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:36:32.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:36:32.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:36:32.88$vc4f8/vblo=6,752.99 2006.280.07:36:32.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:36:32.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:36:32.88#ibcon#ireg 17 cls_cnt 0 2006.280.07:36:32.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:32.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:32.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:32.88#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:36:32.88#ibcon#first serial, iclass 19, count 0 2006.280.07:36:32.88#ibcon#enter sib2, iclass 19, count 0 2006.280.07:36:32.88#ibcon#flushed, iclass 19, count 0 2006.280.07:36:32.88#ibcon#about to write, iclass 19, count 0 2006.280.07:36:32.88#ibcon#wrote, iclass 19, count 0 2006.280.07:36:32.88#ibcon#about to read 3, iclass 19, count 0 2006.280.07:36:32.90#ibcon#read 3, iclass 19, count 0 2006.280.07:36:32.90#ibcon#about to read 4, iclass 19, count 0 2006.280.07:36:32.90#ibcon#read 4, iclass 19, count 0 2006.280.07:36:32.90#ibcon#about to read 5, iclass 19, count 0 2006.280.07:36:32.90#ibcon#read 5, iclass 19, count 0 2006.280.07:36:32.90#ibcon#about to read 6, iclass 19, count 0 2006.280.07:36:32.90#ibcon#read 6, iclass 19, count 0 2006.280.07:36:32.90#ibcon#end of sib2, iclass 19, count 0 2006.280.07:36:32.90#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:36:32.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:36:32.90#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:36:32.90#ibcon#*before write, iclass 19, count 0 2006.280.07:36:32.90#ibcon#enter sib2, iclass 19, count 0 2006.280.07:36:32.90#ibcon#flushed, iclass 19, count 0 2006.280.07:36:32.92#ibcon#about to write, iclass 19, count 0 2006.280.07:36:32.92#ibcon#wrote, iclass 19, count 0 2006.280.07:36:32.92#ibcon#about to read 3, iclass 19, count 0 2006.280.07:36:32.97#ibcon#read 3, iclass 19, count 0 2006.280.07:36:32.97#ibcon#about to read 4, iclass 19, count 0 2006.280.07:36:32.97#ibcon#read 4, iclass 19, count 0 2006.280.07:36:32.97#ibcon#about to read 5, iclass 19, count 0 2006.280.07:36:32.97#ibcon#read 5, iclass 19, count 0 2006.280.07:36:32.97#ibcon#about to read 6, iclass 19, count 0 2006.280.07:36:32.97#ibcon#read 6, iclass 19, count 0 2006.280.07:36:32.97#ibcon#end of sib2, iclass 19, count 0 2006.280.07:36:32.97#ibcon#*after write, iclass 19, count 0 2006.280.07:36:32.97#ibcon#*before return 0, iclass 19, count 0 2006.280.07:36:32.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:32.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:36:32.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:36:32.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:36:32.97$vc4f8/vb=6,4 2006.280.07:36:32.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:36:32.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:36:32.97#ibcon#ireg 11 cls_cnt 2 2006.280.07:36:32.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:33.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:33.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:33.00#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:36:33.00#ibcon#first serial, iclass 21, count 2 2006.280.07:36:33.00#ibcon#enter sib2, iclass 21, count 2 2006.280.07:36:33.00#ibcon#flushed, iclass 21, count 2 2006.280.07:36:33.00#ibcon#about to write, iclass 21, count 2 2006.280.07:36:33.00#ibcon#wrote, iclass 21, count 2 2006.280.07:36:33.00#ibcon#about to read 3, iclass 21, count 2 2006.280.07:36:33.02#ibcon#read 3, iclass 21, count 2 2006.280.07:36:33.02#ibcon#about to read 4, iclass 21, count 2 2006.280.07:36:33.02#ibcon#read 4, iclass 21, count 2 2006.280.07:36:33.02#ibcon#about to read 5, iclass 21, count 2 2006.280.07:36:33.02#ibcon#read 5, iclass 21, count 2 2006.280.07:36:33.02#ibcon#about to read 6, iclass 21, count 2 2006.280.07:36:33.02#ibcon#read 6, iclass 21, count 2 2006.280.07:36:33.02#ibcon#end of sib2, iclass 21, count 2 2006.280.07:36:33.02#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:36:33.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:36:33.02#ibcon#[27=AT06-04\r\n] 2006.280.07:36:33.02#ibcon#*before write, iclass 21, count 2 2006.280.07:36:33.02#ibcon#enter sib2, iclass 21, count 2 2006.280.07:36:33.02#ibcon#flushed, iclass 21, count 2 2006.280.07:36:33.02#ibcon#about to write, iclass 21, count 2 2006.280.07:36:33.02#ibcon#wrote, iclass 21, count 2 2006.280.07:36:33.02#ibcon#about to read 3, iclass 21, count 2 2006.280.07:36:33.05#ibcon#read 3, iclass 21, count 2 2006.280.07:36:33.05#ibcon#about to read 4, iclass 21, count 2 2006.280.07:36:33.05#ibcon#read 4, iclass 21, count 2 2006.280.07:36:33.05#ibcon#about to read 5, iclass 21, count 2 2006.280.07:36:33.05#ibcon#read 5, iclass 21, count 2 2006.280.07:36:33.05#ibcon#about to read 6, iclass 21, count 2 2006.280.07:36:33.05#ibcon#read 6, iclass 21, count 2 2006.280.07:36:33.05#ibcon#end of sib2, iclass 21, count 2 2006.280.07:36:33.05#ibcon#*after write, iclass 21, count 2 2006.280.07:36:33.05#ibcon#*before return 0, iclass 21, count 2 2006.280.07:36:33.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:33.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:36:33.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:36:33.05#ibcon#ireg 7 cls_cnt 0 2006.280.07:36:33.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:33.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:33.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:33.17#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:36:33.17#ibcon#first serial, iclass 21, count 0 2006.280.07:36:33.17#ibcon#enter sib2, iclass 21, count 0 2006.280.07:36:33.17#ibcon#flushed, iclass 21, count 0 2006.280.07:36:33.17#ibcon#about to write, iclass 21, count 0 2006.280.07:36:33.17#ibcon#wrote, iclass 21, count 0 2006.280.07:36:33.17#ibcon#about to read 3, iclass 21, count 0 2006.280.07:36:33.19#ibcon#read 3, iclass 21, count 0 2006.280.07:36:33.19#ibcon#about to read 4, iclass 21, count 0 2006.280.07:36:33.19#ibcon#read 4, iclass 21, count 0 2006.280.07:36:33.19#ibcon#about to read 5, iclass 21, count 0 2006.280.07:36:33.19#ibcon#read 5, iclass 21, count 0 2006.280.07:36:33.19#ibcon#about to read 6, iclass 21, count 0 2006.280.07:36:33.19#ibcon#read 6, iclass 21, count 0 2006.280.07:36:33.19#ibcon#end of sib2, iclass 21, count 0 2006.280.07:36:33.19#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:36:33.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:36:33.19#ibcon#[27=USB\r\n] 2006.280.07:36:33.19#ibcon#*before write, iclass 21, count 0 2006.280.07:36:33.19#ibcon#enter sib2, iclass 21, count 0 2006.280.07:36:33.19#ibcon#flushed, iclass 21, count 0 2006.280.07:36:33.19#ibcon#about to write, iclass 21, count 0 2006.280.07:36:33.19#ibcon#wrote, iclass 21, count 0 2006.280.07:36:33.19#ibcon#about to read 3, iclass 21, count 0 2006.280.07:36:33.22#ibcon#read 3, iclass 21, count 0 2006.280.07:36:33.22#ibcon#about to read 4, iclass 21, count 0 2006.280.07:36:33.22#ibcon#read 4, iclass 21, count 0 2006.280.07:36:33.22#ibcon#about to read 5, iclass 21, count 0 2006.280.07:36:33.22#ibcon#read 5, iclass 21, count 0 2006.280.07:36:33.22#ibcon#about to read 6, iclass 21, count 0 2006.280.07:36:33.22#ibcon#read 6, iclass 21, count 0 2006.280.07:36:33.22#ibcon#end of sib2, iclass 21, count 0 2006.280.07:36:33.22#ibcon#*after write, iclass 21, count 0 2006.280.07:36:33.22#ibcon#*before return 0, iclass 21, count 0 2006.280.07:36:33.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:33.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:36:33.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:36:33.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:36:33.22$vc4f8/vabw=wide 2006.280.07:36:33.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:36:33.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:36:33.22#ibcon#ireg 8 cls_cnt 0 2006.280.07:36:33.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:33.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:33.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:33.22#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:36:33.22#ibcon#first serial, iclass 23, count 0 2006.280.07:36:33.22#ibcon#enter sib2, iclass 23, count 0 2006.280.07:36:33.22#ibcon#flushed, iclass 23, count 0 2006.280.07:36:33.22#ibcon#about to write, iclass 23, count 0 2006.280.07:36:33.22#ibcon#wrote, iclass 23, count 0 2006.280.07:36:33.22#ibcon#about to read 3, iclass 23, count 0 2006.280.07:36:33.24#ibcon#read 3, iclass 23, count 0 2006.280.07:36:33.24#ibcon#about to read 4, iclass 23, count 0 2006.280.07:36:33.24#ibcon#read 4, iclass 23, count 0 2006.280.07:36:33.24#ibcon#about to read 5, iclass 23, count 0 2006.280.07:36:33.24#ibcon#read 5, iclass 23, count 0 2006.280.07:36:33.24#ibcon#about to read 6, iclass 23, count 0 2006.280.07:36:33.24#ibcon#read 6, iclass 23, count 0 2006.280.07:36:33.24#ibcon#end of sib2, iclass 23, count 0 2006.280.07:36:33.24#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:36:33.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:36:33.24#ibcon#[25=BW32\r\n] 2006.280.07:36:33.24#ibcon#*before write, iclass 23, count 0 2006.280.07:36:33.24#ibcon#enter sib2, iclass 23, count 0 2006.280.07:36:33.24#ibcon#flushed, iclass 23, count 0 2006.280.07:36:33.24#ibcon#about to write, iclass 23, count 0 2006.280.07:36:33.24#ibcon#wrote, iclass 23, count 0 2006.280.07:36:33.24#ibcon#about to read 3, iclass 23, count 0 2006.280.07:36:33.27#ibcon#read 3, iclass 23, count 0 2006.280.07:36:33.27#ibcon#about to read 4, iclass 23, count 0 2006.280.07:36:33.27#ibcon#read 4, iclass 23, count 0 2006.280.07:36:33.27#ibcon#about to read 5, iclass 23, count 0 2006.280.07:36:33.27#ibcon#read 5, iclass 23, count 0 2006.280.07:36:33.27#ibcon#about to read 6, iclass 23, count 0 2006.280.07:36:33.27#ibcon#read 6, iclass 23, count 0 2006.280.07:36:33.27#ibcon#end of sib2, iclass 23, count 0 2006.280.07:36:33.27#ibcon#*after write, iclass 23, count 0 2006.280.07:36:33.27#ibcon#*before return 0, iclass 23, count 0 2006.280.07:36:33.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:33.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:36:33.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:36:33.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:36:33.27$vc4f8/vbbw=wide 2006.280.07:36:33.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:36:33.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:36:33.27#ibcon#ireg 8 cls_cnt 0 2006.280.07:36:33.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:36:33.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:36:33.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:36:33.34#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:36:33.34#ibcon#first serial, iclass 25, count 0 2006.280.07:36:33.34#ibcon#enter sib2, iclass 25, count 0 2006.280.07:36:33.34#ibcon#flushed, iclass 25, count 0 2006.280.07:36:33.34#ibcon#about to write, iclass 25, count 0 2006.280.07:36:33.34#ibcon#wrote, iclass 25, count 0 2006.280.07:36:33.34#ibcon#about to read 3, iclass 25, count 0 2006.280.07:36:33.36#ibcon#read 3, iclass 25, count 0 2006.280.07:36:33.36#ibcon#about to read 4, iclass 25, count 0 2006.280.07:36:33.36#ibcon#read 4, iclass 25, count 0 2006.280.07:36:33.36#ibcon#about to read 5, iclass 25, count 0 2006.280.07:36:33.36#ibcon#read 5, iclass 25, count 0 2006.280.07:36:33.36#ibcon#about to read 6, iclass 25, count 0 2006.280.07:36:33.36#ibcon#read 6, iclass 25, count 0 2006.280.07:36:33.36#ibcon#end of sib2, iclass 25, count 0 2006.280.07:36:33.36#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:36:33.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:36:33.36#ibcon#[27=BW32\r\n] 2006.280.07:36:33.36#ibcon#*before write, iclass 25, count 0 2006.280.07:36:33.36#ibcon#enter sib2, iclass 25, count 0 2006.280.07:36:33.36#ibcon#flushed, iclass 25, count 0 2006.280.07:36:33.36#ibcon#about to write, iclass 25, count 0 2006.280.07:36:33.36#ibcon#wrote, iclass 25, count 0 2006.280.07:36:33.36#ibcon#about to read 3, iclass 25, count 0 2006.280.07:36:33.39#ibcon#read 3, iclass 25, count 0 2006.280.07:36:33.39#ibcon#about to read 4, iclass 25, count 0 2006.280.07:36:33.39#ibcon#read 4, iclass 25, count 0 2006.280.07:36:33.39#ibcon#about to read 5, iclass 25, count 0 2006.280.07:36:33.39#ibcon#read 5, iclass 25, count 0 2006.280.07:36:33.39#ibcon#about to read 6, iclass 25, count 0 2006.280.07:36:33.39#ibcon#read 6, iclass 25, count 0 2006.280.07:36:33.39#ibcon#end of sib2, iclass 25, count 0 2006.280.07:36:33.39#ibcon#*after write, iclass 25, count 0 2006.280.07:36:33.39#ibcon#*before return 0, iclass 25, count 0 2006.280.07:36:33.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:36:33.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:36:33.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:36:33.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:36:33.39$4f8m12a/ifd4f 2006.280.07:36:33.39$ifd4f/lo= 2006.280.07:36:33.39$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:36:33.39$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:36:33.39$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:36:33.39$ifd4f/patch= 2006.280.07:36:33.39$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:36:33.39$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:36:33.39$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:36:33.39$4f8m12a/"form=m,16.000,1:2 2006.280.07:36:33.39$4f8m12a/"tpicd 2006.280.07:36:33.39$4f8m12a/echo=off 2006.280.07:36:33.39$4f8m12a/xlog=off 2006.280.07:36:33.39:!2006.280.07:37:00 2006.280.07:36:42.14#trakl#Source acquired 2006.280.07:36:42.14#flagr#flagr/antenna,acquired 2006.280.07:37:00.00:preob 2006.280.07:37:01.14/onsource/TRACKING 2006.280.07:37:01.14:!2006.280.07:37:10 2006.280.07:37:10.00:data_valid=on 2006.280.07:37:10.00:midob 2006.280.07:37:10.14/onsource/TRACKING 2006.280.07:37:10.14/wx/21.92,986.7,60 2006.280.07:37:10.20/cable/+6.4834E-03 2006.280.07:37:11.29/va/01,07,usb,yes,32,34 2006.280.07:37:11.29/va/02,06,usb,yes,30,31 2006.280.07:37:11.29/va/03,06,usb,yes,28,28 2006.280.07:37:11.29/va/04,06,usb,yes,31,33 2006.280.07:37:11.29/va/05,07,usb,yes,28,29 2006.280.07:37:11.29/va/06,06,usb,yes,27,27 2006.280.07:37:11.29/va/07,06,usb,yes,27,27 2006.280.07:37:11.29/va/08,06,usb,yes,29,29 2006.280.07:37:11.52/valo/01,532.99,yes,locked 2006.280.07:37:11.52/valo/02,572.99,yes,locked 2006.280.07:37:11.52/valo/03,672.99,yes,locked 2006.280.07:37:11.52/valo/04,832.99,yes,locked 2006.280.07:37:11.52/valo/05,652.99,yes,locked 2006.280.07:37:11.52/valo/06,772.99,yes,locked 2006.280.07:37:11.52/valo/07,832.99,yes,locked 2006.280.07:37:11.52/valo/08,852.99,yes,locked 2006.280.07:37:12.61/vb/01,04,usb,yes,30,29 2006.280.07:37:12.61/vb/02,05,usb,yes,28,29 2006.280.07:37:12.61/vb/03,04,usb,yes,28,32 2006.280.07:37:12.61/vb/04,04,usb,yes,29,29 2006.280.07:37:12.61/vb/05,04,usb,yes,27,31 2006.280.07:37:12.61/vb/06,04,usb,yes,27,31 2006.280.07:37:12.61/vb/07,04,usb,yes,30,30 2006.280.07:37:12.61/vb/08,04,usb,yes,27,31 2006.280.07:37:12.84/vblo/01,632.99,yes,locked 2006.280.07:37:12.84/vblo/02,640.99,yes,locked 2006.280.07:37:12.84/vblo/03,656.99,yes,locked 2006.280.07:37:12.84/vblo/04,712.99,yes,locked 2006.280.07:37:12.84/vblo/05,744.99,yes,locked 2006.280.07:37:12.84/vblo/06,752.99,yes,locked 2006.280.07:37:12.84/vblo/07,734.99,yes,locked 2006.280.07:37:12.84/vblo/08,744.99,yes,locked 2006.280.07:37:12.99/vabw/8 2006.280.07:37:13.14/vbbw/8 2006.280.07:37:13.24/xfe/off,on,12.2 2006.280.07:37:13.62/ifatt/23,28,28,28 2006.280.07:37:14.08/fmout-gps/S +2.95E-07 2006.280.07:37:14.09:!2006.280.07:38:10 2006.280.07:38:10.00:data_valid=off 2006.280.07:38:10.00:postob 2006.280.07:38:10.20/cable/+6.4836E-03 2006.280.07:38:10.20/wx/21.85,986.7,60 2006.280.07:38:11.08/fmout-gps/S +2.96E-07 2006.280.07:38:11.08:scan_name=280-0739,k06280,60 2006.280.07:38:11.08:source=1053+815,105811.54,811432.7,2000.0,ccw 2006.280.07:38:11.16#flagr#flagr/antenna,new-source 2006.280.07:38:12.14:checkk5 2006.280.07:38:12.56/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:38:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:38:13.31/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:38:13.72/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:38:14.09/chk_obsdata//k5ts1/T2800737??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:38:14.54/chk_obsdata//k5ts2/T2800737??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:38:14.91/chk_obsdata//k5ts3/T2800737??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:38:15.29/chk_obsdata//k5ts4/T2800737??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:38:16.01/k5log//k5ts1_log_newline 2006.280.07:38:16.84/k5log//k5ts2_log_newline 2006.280.07:38:17.61/k5log//k5ts3_log_newline 2006.280.07:38:18.31/k5log//k5ts4_log_newline 2006.280.07:38:18.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:38:18.33:4f8m12a=1 2006.280.07:38:18.33$4f8m12a/echo=on 2006.280.07:38:18.33$4f8m12a/pcalon 2006.280.07:38:18.33$pcalon/"no phase cal control is implemented here 2006.280.07:38:18.33$4f8m12a/"tpicd=stop 2006.280.07:38:18.33$4f8m12a/vc4f8 2006.280.07:38:18.33$vc4f8/valo=1,532.99 2006.280.07:38:18.34#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:38:18.34#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:38:18.34#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:18.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:18.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:18.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:18.34#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:38:18.34#ibcon#first serial, iclass 32, count 0 2006.280.07:38:18.34#ibcon#enter sib2, iclass 32, count 0 2006.280.07:38:18.34#ibcon#flushed, iclass 32, count 0 2006.280.07:38:18.34#ibcon#about to write, iclass 32, count 0 2006.280.07:38:18.34#ibcon#wrote, iclass 32, count 0 2006.280.07:38:18.34#ibcon#about to read 3, iclass 32, count 0 2006.280.07:38:18.36#ibcon#read 3, iclass 32, count 0 2006.280.07:38:18.36#ibcon#about to read 4, iclass 32, count 0 2006.280.07:38:18.36#ibcon#read 4, iclass 32, count 0 2006.280.07:38:18.36#ibcon#about to read 5, iclass 32, count 0 2006.280.07:38:18.36#ibcon#read 5, iclass 32, count 0 2006.280.07:38:18.36#ibcon#about to read 6, iclass 32, count 0 2006.280.07:38:18.36#ibcon#read 6, iclass 32, count 0 2006.280.07:38:18.36#ibcon#end of sib2, iclass 32, count 0 2006.280.07:38:18.36#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:38:18.36#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:38:18.36#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:38:18.36#ibcon#*before write, iclass 32, count 0 2006.280.07:38:18.36#ibcon#enter sib2, iclass 32, count 0 2006.280.07:38:18.36#ibcon#flushed, iclass 32, count 0 2006.280.07:38:18.36#ibcon#about to write, iclass 32, count 0 2006.280.07:38:18.36#ibcon#wrote, iclass 32, count 0 2006.280.07:38:18.36#ibcon#about to read 3, iclass 32, count 0 2006.280.07:38:18.41#ibcon#read 3, iclass 32, count 0 2006.280.07:38:18.41#ibcon#about to read 4, iclass 32, count 0 2006.280.07:38:18.41#ibcon#read 4, iclass 32, count 0 2006.280.07:38:18.41#ibcon#about to read 5, iclass 32, count 0 2006.280.07:38:18.41#ibcon#read 5, iclass 32, count 0 2006.280.07:38:18.41#ibcon#about to read 6, iclass 32, count 0 2006.280.07:38:18.41#ibcon#read 6, iclass 32, count 0 2006.280.07:38:18.41#ibcon#end of sib2, iclass 32, count 0 2006.280.07:38:18.41#ibcon#*after write, iclass 32, count 0 2006.280.07:38:18.41#ibcon#*before return 0, iclass 32, count 0 2006.280.07:38:18.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:18.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:18.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:38:18.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:38:18.41$vc4f8/va=1,7 2006.280.07:38:18.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.07:38:18.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.07:38:18.42#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:18.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:18.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:18.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:18.42#ibcon#enter wrdev, iclass 34, count 2 2006.280.07:38:18.42#ibcon#first serial, iclass 34, count 2 2006.280.07:38:18.42#ibcon#enter sib2, iclass 34, count 2 2006.280.07:38:18.42#ibcon#flushed, iclass 34, count 2 2006.280.07:38:18.42#ibcon#about to write, iclass 34, count 2 2006.280.07:38:18.42#ibcon#wrote, iclass 34, count 2 2006.280.07:38:18.42#ibcon#about to read 3, iclass 34, count 2 2006.280.07:38:18.44#ibcon#read 3, iclass 34, count 2 2006.280.07:38:18.44#ibcon#about to read 4, iclass 34, count 2 2006.280.07:38:18.44#ibcon#read 4, iclass 34, count 2 2006.280.07:38:18.44#ibcon#about to read 5, iclass 34, count 2 2006.280.07:38:18.44#ibcon#read 5, iclass 34, count 2 2006.280.07:38:18.44#ibcon#about to read 6, iclass 34, count 2 2006.280.07:38:18.44#ibcon#read 6, iclass 34, count 2 2006.280.07:38:18.44#ibcon#end of sib2, iclass 34, count 2 2006.280.07:38:18.44#ibcon#*mode == 0, iclass 34, count 2 2006.280.07:38:18.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.07:38:18.44#ibcon#[25=AT01-07\r\n] 2006.280.07:38:18.44#ibcon#*before write, iclass 34, count 2 2006.280.07:38:18.44#ibcon#enter sib2, iclass 34, count 2 2006.280.07:38:18.44#ibcon#flushed, iclass 34, count 2 2006.280.07:38:18.44#ibcon#about to write, iclass 34, count 2 2006.280.07:38:18.44#ibcon#wrote, iclass 34, count 2 2006.280.07:38:18.44#ibcon#about to read 3, iclass 34, count 2 2006.280.07:38:18.47#ibcon#read 3, iclass 34, count 2 2006.280.07:38:18.47#ibcon#about to read 4, iclass 34, count 2 2006.280.07:38:18.47#ibcon#read 4, iclass 34, count 2 2006.280.07:38:18.47#ibcon#about to read 5, iclass 34, count 2 2006.280.07:38:18.47#ibcon#read 5, iclass 34, count 2 2006.280.07:38:18.47#ibcon#about to read 6, iclass 34, count 2 2006.280.07:38:18.47#ibcon#read 6, iclass 34, count 2 2006.280.07:38:18.47#ibcon#end of sib2, iclass 34, count 2 2006.280.07:38:18.47#ibcon#*after write, iclass 34, count 2 2006.280.07:38:18.47#ibcon#*before return 0, iclass 34, count 2 2006.280.07:38:18.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:18.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:18.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.07:38:18.47#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:18.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:18.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:18.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:18.59#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:38:18.59#ibcon#first serial, iclass 34, count 0 2006.280.07:38:18.59#ibcon#enter sib2, iclass 34, count 0 2006.280.07:38:18.59#ibcon#flushed, iclass 34, count 0 2006.280.07:38:18.59#ibcon#about to write, iclass 34, count 0 2006.280.07:38:18.59#ibcon#wrote, iclass 34, count 0 2006.280.07:38:18.59#ibcon#about to read 3, iclass 34, count 0 2006.280.07:38:18.61#ibcon#read 3, iclass 34, count 0 2006.280.07:38:18.61#ibcon#about to read 4, iclass 34, count 0 2006.280.07:38:18.61#ibcon#read 4, iclass 34, count 0 2006.280.07:38:18.61#ibcon#about to read 5, iclass 34, count 0 2006.280.07:38:18.61#ibcon#read 5, iclass 34, count 0 2006.280.07:38:18.61#ibcon#about to read 6, iclass 34, count 0 2006.280.07:38:18.61#ibcon#read 6, iclass 34, count 0 2006.280.07:38:18.61#ibcon#end of sib2, iclass 34, count 0 2006.280.07:38:18.61#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:38:18.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:38:18.61#ibcon#[25=USB\r\n] 2006.280.07:38:18.61#ibcon#*before write, iclass 34, count 0 2006.280.07:38:18.61#ibcon#enter sib2, iclass 34, count 0 2006.280.07:38:18.61#ibcon#flushed, iclass 34, count 0 2006.280.07:38:18.61#ibcon#about to write, iclass 34, count 0 2006.280.07:38:18.61#ibcon#wrote, iclass 34, count 0 2006.280.07:38:18.61#ibcon#about to read 3, iclass 34, count 0 2006.280.07:38:18.64#ibcon#read 3, iclass 34, count 0 2006.280.07:38:18.64#ibcon#about to read 4, iclass 34, count 0 2006.280.07:38:18.64#ibcon#read 4, iclass 34, count 0 2006.280.07:38:18.64#ibcon#about to read 5, iclass 34, count 0 2006.280.07:38:18.64#ibcon#read 5, iclass 34, count 0 2006.280.07:38:18.64#ibcon#about to read 6, iclass 34, count 0 2006.280.07:38:18.64#ibcon#read 6, iclass 34, count 0 2006.280.07:38:18.64#ibcon#end of sib2, iclass 34, count 0 2006.280.07:38:18.64#ibcon#*after write, iclass 34, count 0 2006.280.07:38:18.64#ibcon#*before return 0, iclass 34, count 0 2006.280.07:38:18.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:18.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:18.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:38:18.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:38:18.64$vc4f8/valo=2,572.99 2006.280.07:38:18.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.07:38:18.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.07:38:18.64#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:18.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:18.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:18.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:18.64#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:38:18.64#ibcon#first serial, iclass 36, count 0 2006.280.07:38:18.64#ibcon#enter sib2, iclass 36, count 0 2006.280.07:38:18.64#ibcon#flushed, iclass 36, count 0 2006.280.07:38:18.64#ibcon#about to write, iclass 36, count 0 2006.280.07:38:18.64#ibcon#wrote, iclass 36, count 0 2006.280.07:38:18.64#ibcon#about to read 3, iclass 36, count 0 2006.280.07:38:18.66#ibcon#read 3, iclass 36, count 0 2006.280.07:38:18.66#ibcon#about to read 4, iclass 36, count 0 2006.280.07:38:18.66#ibcon#read 4, iclass 36, count 0 2006.280.07:38:18.66#ibcon#about to read 5, iclass 36, count 0 2006.280.07:38:18.66#ibcon#read 5, iclass 36, count 0 2006.280.07:38:18.66#ibcon#about to read 6, iclass 36, count 0 2006.280.07:38:18.66#ibcon#read 6, iclass 36, count 0 2006.280.07:38:18.66#ibcon#end of sib2, iclass 36, count 0 2006.280.07:38:18.66#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:38:18.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:38:18.66#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:38:18.66#ibcon#*before write, iclass 36, count 0 2006.280.07:38:18.66#ibcon#enter sib2, iclass 36, count 0 2006.280.07:38:18.66#ibcon#flushed, iclass 36, count 0 2006.280.07:38:18.66#ibcon#about to write, iclass 36, count 0 2006.280.07:38:18.66#ibcon#wrote, iclass 36, count 0 2006.280.07:38:18.66#ibcon#about to read 3, iclass 36, count 0 2006.280.07:38:18.70#ibcon#read 3, iclass 36, count 0 2006.280.07:38:18.70#ibcon#about to read 4, iclass 36, count 0 2006.280.07:38:18.70#ibcon#read 4, iclass 36, count 0 2006.280.07:38:18.70#ibcon#about to read 5, iclass 36, count 0 2006.280.07:38:18.70#ibcon#read 5, iclass 36, count 0 2006.280.07:38:18.70#ibcon#about to read 6, iclass 36, count 0 2006.280.07:38:18.70#ibcon#read 6, iclass 36, count 0 2006.280.07:38:18.70#ibcon#end of sib2, iclass 36, count 0 2006.280.07:38:18.70#ibcon#*after write, iclass 36, count 0 2006.280.07:38:18.70#ibcon#*before return 0, iclass 36, count 0 2006.280.07:38:18.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:18.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:18.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:38:18.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:38:18.70$vc4f8/va=2,6 2006.280.07:38:18.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.07:38:18.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.07:38:18.70#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:18.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:18.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:18.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:18.76#ibcon#enter wrdev, iclass 38, count 2 2006.280.07:38:18.76#ibcon#first serial, iclass 38, count 2 2006.280.07:38:18.76#ibcon#enter sib2, iclass 38, count 2 2006.280.07:38:18.76#ibcon#flushed, iclass 38, count 2 2006.280.07:38:18.76#ibcon#about to write, iclass 38, count 2 2006.280.07:38:18.76#ibcon#wrote, iclass 38, count 2 2006.280.07:38:18.76#ibcon#about to read 3, iclass 38, count 2 2006.280.07:38:18.78#ibcon#read 3, iclass 38, count 2 2006.280.07:38:18.78#ibcon#about to read 4, iclass 38, count 2 2006.280.07:38:18.78#ibcon#read 4, iclass 38, count 2 2006.280.07:38:18.78#ibcon#about to read 5, iclass 38, count 2 2006.280.07:38:18.78#ibcon#read 5, iclass 38, count 2 2006.280.07:38:18.78#ibcon#about to read 6, iclass 38, count 2 2006.280.07:38:18.78#ibcon#read 6, iclass 38, count 2 2006.280.07:38:18.78#ibcon#end of sib2, iclass 38, count 2 2006.280.07:38:18.78#ibcon#*mode == 0, iclass 38, count 2 2006.280.07:38:18.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.07:38:18.78#ibcon#[25=AT02-06\r\n] 2006.280.07:38:18.78#ibcon#*before write, iclass 38, count 2 2006.280.07:38:18.78#ibcon#enter sib2, iclass 38, count 2 2006.280.07:38:18.78#ibcon#flushed, iclass 38, count 2 2006.280.07:38:18.78#ibcon#about to write, iclass 38, count 2 2006.280.07:38:18.78#ibcon#wrote, iclass 38, count 2 2006.280.07:38:18.78#ibcon#about to read 3, iclass 38, count 2 2006.280.07:38:18.81#ibcon#read 3, iclass 38, count 2 2006.280.07:38:18.81#ibcon#about to read 4, iclass 38, count 2 2006.280.07:38:18.81#ibcon#read 4, iclass 38, count 2 2006.280.07:38:18.81#ibcon#about to read 5, iclass 38, count 2 2006.280.07:38:18.81#ibcon#read 5, iclass 38, count 2 2006.280.07:38:18.81#ibcon#about to read 6, iclass 38, count 2 2006.280.07:38:18.81#ibcon#read 6, iclass 38, count 2 2006.280.07:38:18.81#ibcon#end of sib2, iclass 38, count 2 2006.280.07:38:18.81#ibcon#*after write, iclass 38, count 2 2006.280.07:38:18.81#ibcon#*before return 0, iclass 38, count 2 2006.280.07:38:18.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:18.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:18.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.07:38:18.81#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:18.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:18.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:18.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:18.93#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:38:18.93#ibcon#first serial, iclass 38, count 0 2006.280.07:38:18.93#ibcon#enter sib2, iclass 38, count 0 2006.280.07:38:18.93#ibcon#flushed, iclass 38, count 0 2006.280.07:38:18.93#ibcon#about to write, iclass 38, count 0 2006.280.07:38:18.93#ibcon#wrote, iclass 38, count 0 2006.280.07:38:18.93#ibcon#about to read 3, iclass 38, count 0 2006.280.07:38:18.95#ibcon#read 3, iclass 38, count 0 2006.280.07:38:18.95#ibcon#about to read 4, iclass 38, count 0 2006.280.07:38:18.95#ibcon#read 4, iclass 38, count 0 2006.280.07:38:18.95#ibcon#about to read 5, iclass 38, count 0 2006.280.07:38:18.95#ibcon#read 5, iclass 38, count 0 2006.280.07:38:18.95#ibcon#about to read 6, iclass 38, count 0 2006.280.07:38:18.95#ibcon#read 6, iclass 38, count 0 2006.280.07:38:18.95#ibcon#end of sib2, iclass 38, count 0 2006.280.07:38:18.95#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:38:18.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:38:18.95#ibcon#[25=USB\r\n] 2006.280.07:38:18.95#ibcon#*before write, iclass 38, count 0 2006.280.07:38:18.95#ibcon#enter sib2, iclass 38, count 0 2006.280.07:38:18.95#ibcon#flushed, iclass 38, count 0 2006.280.07:38:18.95#ibcon#about to write, iclass 38, count 0 2006.280.07:38:18.95#ibcon#wrote, iclass 38, count 0 2006.280.07:38:18.95#ibcon#about to read 3, iclass 38, count 0 2006.280.07:38:18.98#ibcon#read 3, iclass 38, count 0 2006.280.07:38:18.98#ibcon#about to read 4, iclass 38, count 0 2006.280.07:38:18.98#ibcon#read 4, iclass 38, count 0 2006.280.07:38:18.98#ibcon#about to read 5, iclass 38, count 0 2006.280.07:38:18.98#ibcon#read 5, iclass 38, count 0 2006.280.07:38:18.98#ibcon#about to read 6, iclass 38, count 0 2006.280.07:38:18.98#ibcon#read 6, iclass 38, count 0 2006.280.07:38:18.98#ibcon#end of sib2, iclass 38, count 0 2006.280.07:38:18.98#ibcon#*after write, iclass 38, count 0 2006.280.07:38:18.98#ibcon#*before return 0, iclass 38, count 0 2006.280.07:38:18.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:18.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:18.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:38:18.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:38:18.98$vc4f8/valo=3,672.99 2006.280.07:38:18.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:38:18.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:38:18.98#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:18.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:18.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:18.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:18.98#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:38:18.98#ibcon#first serial, iclass 40, count 0 2006.280.07:38:18.98#ibcon#enter sib2, iclass 40, count 0 2006.280.07:38:18.98#ibcon#flushed, iclass 40, count 0 2006.280.07:38:18.98#ibcon#about to write, iclass 40, count 0 2006.280.07:38:18.98#ibcon#wrote, iclass 40, count 0 2006.280.07:38:18.98#ibcon#about to read 3, iclass 40, count 0 2006.280.07:38:19.00#ibcon#read 3, iclass 40, count 0 2006.280.07:38:19.00#ibcon#about to read 4, iclass 40, count 0 2006.280.07:38:19.00#ibcon#read 4, iclass 40, count 0 2006.280.07:38:19.00#ibcon#about to read 5, iclass 40, count 0 2006.280.07:38:19.00#ibcon#read 5, iclass 40, count 0 2006.280.07:38:19.00#ibcon#about to read 6, iclass 40, count 0 2006.280.07:38:19.00#ibcon#read 6, iclass 40, count 0 2006.280.07:38:19.00#ibcon#end of sib2, iclass 40, count 0 2006.280.07:38:19.00#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:38:19.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:38:19.00#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:38:19.00#ibcon#*before write, iclass 40, count 0 2006.280.07:38:19.00#ibcon#enter sib2, iclass 40, count 0 2006.280.07:38:19.00#ibcon#flushed, iclass 40, count 0 2006.280.07:38:19.00#ibcon#about to write, iclass 40, count 0 2006.280.07:38:19.00#ibcon#wrote, iclass 40, count 0 2006.280.07:38:19.00#ibcon#about to read 3, iclass 40, count 0 2006.280.07:38:19.04#ibcon#read 3, iclass 40, count 0 2006.280.07:38:19.04#ibcon#about to read 4, iclass 40, count 0 2006.280.07:38:19.04#ibcon#read 4, iclass 40, count 0 2006.280.07:38:19.04#ibcon#about to read 5, iclass 40, count 0 2006.280.07:38:19.04#ibcon#read 5, iclass 40, count 0 2006.280.07:38:19.04#ibcon#about to read 6, iclass 40, count 0 2006.280.07:38:19.04#ibcon#read 6, iclass 40, count 0 2006.280.07:38:19.04#ibcon#end of sib2, iclass 40, count 0 2006.280.07:38:19.04#ibcon#*after write, iclass 40, count 0 2006.280.07:38:19.04#ibcon#*before return 0, iclass 40, count 0 2006.280.07:38:19.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:19.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:19.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:38:19.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:38:19.04$vc4f8/va=3,6 2006.280.07:38:19.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.07:38:19.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.07:38:19.04#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:19.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:19.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:19.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:19.10#ibcon#enter wrdev, iclass 4, count 2 2006.280.07:38:19.10#ibcon#first serial, iclass 4, count 2 2006.280.07:38:19.10#ibcon#enter sib2, iclass 4, count 2 2006.280.07:38:19.10#ibcon#flushed, iclass 4, count 2 2006.280.07:38:19.10#ibcon#about to write, iclass 4, count 2 2006.280.07:38:19.10#ibcon#wrote, iclass 4, count 2 2006.280.07:38:19.10#ibcon#about to read 3, iclass 4, count 2 2006.280.07:38:19.12#ibcon#read 3, iclass 4, count 2 2006.280.07:38:19.12#ibcon#about to read 4, iclass 4, count 2 2006.280.07:38:19.12#ibcon#read 4, iclass 4, count 2 2006.280.07:38:19.12#ibcon#about to read 5, iclass 4, count 2 2006.280.07:38:19.12#ibcon#read 5, iclass 4, count 2 2006.280.07:38:19.12#ibcon#about to read 6, iclass 4, count 2 2006.280.07:38:19.12#ibcon#read 6, iclass 4, count 2 2006.280.07:38:19.12#ibcon#end of sib2, iclass 4, count 2 2006.280.07:38:19.12#ibcon#*mode == 0, iclass 4, count 2 2006.280.07:38:19.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.07:38:19.12#ibcon#[25=AT03-06\r\n] 2006.280.07:38:19.12#ibcon#*before write, iclass 4, count 2 2006.280.07:38:19.12#ibcon#enter sib2, iclass 4, count 2 2006.280.07:38:19.12#ibcon#flushed, iclass 4, count 2 2006.280.07:38:19.12#ibcon#about to write, iclass 4, count 2 2006.280.07:38:19.12#ibcon#wrote, iclass 4, count 2 2006.280.07:38:19.12#ibcon#about to read 3, iclass 4, count 2 2006.280.07:38:19.16#ibcon#read 3, iclass 4, count 2 2006.280.07:38:19.16#ibcon#about to read 4, iclass 4, count 2 2006.280.07:38:19.16#ibcon#read 4, iclass 4, count 2 2006.280.07:38:19.16#ibcon#about to read 5, iclass 4, count 2 2006.280.07:38:19.16#ibcon#read 5, iclass 4, count 2 2006.280.07:38:19.16#ibcon#about to read 6, iclass 4, count 2 2006.280.07:38:19.16#ibcon#read 6, iclass 4, count 2 2006.280.07:38:19.16#ibcon#end of sib2, iclass 4, count 2 2006.280.07:38:19.16#ibcon#*after write, iclass 4, count 2 2006.280.07:38:19.16#ibcon#*before return 0, iclass 4, count 2 2006.280.07:38:19.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:19.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:19.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.07:38:19.16#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:19.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:19.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:19.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:19.28#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:38:19.28#ibcon#first serial, iclass 4, count 0 2006.280.07:38:19.28#ibcon#enter sib2, iclass 4, count 0 2006.280.07:38:19.28#ibcon#flushed, iclass 4, count 0 2006.280.07:38:19.28#ibcon#about to write, iclass 4, count 0 2006.280.07:38:19.28#ibcon#wrote, iclass 4, count 0 2006.280.07:38:19.28#ibcon#about to read 3, iclass 4, count 0 2006.280.07:38:19.30#ibcon#read 3, iclass 4, count 0 2006.280.07:38:19.30#ibcon#about to read 4, iclass 4, count 0 2006.280.07:38:19.30#ibcon#read 4, iclass 4, count 0 2006.280.07:38:19.30#ibcon#about to read 5, iclass 4, count 0 2006.280.07:38:19.30#ibcon#read 5, iclass 4, count 0 2006.280.07:38:19.30#ibcon#about to read 6, iclass 4, count 0 2006.280.07:38:19.30#ibcon#read 6, iclass 4, count 0 2006.280.07:38:19.30#ibcon#end of sib2, iclass 4, count 0 2006.280.07:38:19.30#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:38:19.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:38:19.30#ibcon#[25=USB\r\n] 2006.280.07:38:19.30#ibcon#*before write, iclass 4, count 0 2006.280.07:38:19.30#ibcon#enter sib2, iclass 4, count 0 2006.280.07:38:19.30#ibcon#flushed, iclass 4, count 0 2006.280.07:38:19.30#ibcon#about to write, iclass 4, count 0 2006.280.07:38:19.30#ibcon#wrote, iclass 4, count 0 2006.280.07:38:19.30#ibcon#about to read 3, iclass 4, count 0 2006.280.07:38:19.33#ibcon#read 3, iclass 4, count 0 2006.280.07:38:19.33#ibcon#about to read 4, iclass 4, count 0 2006.280.07:38:19.33#ibcon#read 4, iclass 4, count 0 2006.280.07:38:19.33#ibcon#about to read 5, iclass 4, count 0 2006.280.07:38:19.33#ibcon#read 5, iclass 4, count 0 2006.280.07:38:19.33#ibcon#about to read 6, iclass 4, count 0 2006.280.07:38:19.33#ibcon#read 6, iclass 4, count 0 2006.280.07:38:19.33#ibcon#end of sib2, iclass 4, count 0 2006.280.07:38:19.33#ibcon#*after write, iclass 4, count 0 2006.280.07:38:19.33#ibcon#*before return 0, iclass 4, count 0 2006.280.07:38:19.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:19.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:19.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:38:19.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:38:19.33$vc4f8/valo=4,832.99 2006.280.07:38:19.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.07:38:19.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.07:38:19.33#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:19.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:19.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:19.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:19.33#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:38:19.33#ibcon#first serial, iclass 6, count 0 2006.280.07:38:19.33#ibcon#enter sib2, iclass 6, count 0 2006.280.07:38:19.33#ibcon#flushed, iclass 6, count 0 2006.280.07:38:19.33#ibcon#about to write, iclass 6, count 0 2006.280.07:38:19.33#ibcon#wrote, iclass 6, count 0 2006.280.07:38:19.33#ibcon#about to read 3, iclass 6, count 0 2006.280.07:38:19.35#ibcon#read 3, iclass 6, count 0 2006.280.07:38:19.35#ibcon#about to read 4, iclass 6, count 0 2006.280.07:38:19.35#ibcon#read 4, iclass 6, count 0 2006.280.07:38:19.35#ibcon#about to read 5, iclass 6, count 0 2006.280.07:38:19.35#ibcon#read 5, iclass 6, count 0 2006.280.07:38:19.35#ibcon#about to read 6, iclass 6, count 0 2006.280.07:38:19.35#ibcon#read 6, iclass 6, count 0 2006.280.07:38:19.35#ibcon#end of sib2, iclass 6, count 0 2006.280.07:38:19.35#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:38:19.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:38:19.35#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:38:19.35#ibcon#*before write, iclass 6, count 0 2006.280.07:38:19.35#ibcon#enter sib2, iclass 6, count 0 2006.280.07:38:19.35#ibcon#flushed, iclass 6, count 0 2006.280.07:38:19.35#ibcon#about to write, iclass 6, count 0 2006.280.07:38:19.35#ibcon#wrote, iclass 6, count 0 2006.280.07:38:19.35#ibcon#about to read 3, iclass 6, count 0 2006.280.07:38:19.39#ibcon#read 3, iclass 6, count 0 2006.280.07:38:19.39#ibcon#about to read 4, iclass 6, count 0 2006.280.07:38:19.39#ibcon#read 4, iclass 6, count 0 2006.280.07:38:19.39#ibcon#about to read 5, iclass 6, count 0 2006.280.07:38:19.39#ibcon#read 5, iclass 6, count 0 2006.280.07:38:19.39#ibcon#about to read 6, iclass 6, count 0 2006.280.07:38:19.39#ibcon#read 6, iclass 6, count 0 2006.280.07:38:19.39#ibcon#end of sib2, iclass 6, count 0 2006.280.07:38:19.39#ibcon#*after write, iclass 6, count 0 2006.280.07:38:19.39#ibcon#*before return 0, iclass 6, count 0 2006.280.07:38:19.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:19.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:19.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:38:19.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:38:19.39$vc4f8/va=4,6 2006.280.07:38:19.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.07:38:19.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.07:38:19.39#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:19.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:19.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:19.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:19.45#ibcon#enter wrdev, iclass 10, count 2 2006.280.07:38:19.45#ibcon#first serial, iclass 10, count 2 2006.280.07:38:19.45#ibcon#enter sib2, iclass 10, count 2 2006.280.07:38:19.45#ibcon#flushed, iclass 10, count 2 2006.280.07:38:19.45#ibcon#about to write, iclass 10, count 2 2006.280.07:38:19.45#ibcon#wrote, iclass 10, count 2 2006.280.07:38:19.45#ibcon#about to read 3, iclass 10, count 2 2006.280.07:38:19.47#ibcon#read 3, iclass 10, count 2 2006.280.07:38:19.47#ibcon#about to read 4, iclass 10, count 2 2006.280.07:38:19.47#ibcon#read 4, iclass 10, count 2 2006.280.07:38:19.47#ibcon#about to read 5, iclass 10, count 2 2006.280.07:38:19.47#ibcon#read 5, iclass 10, count 2 2006.280.07:38:19.47#ibcon#about to read 6, iclass 10, count 2 2006.280.07:38:19.47#ibcon#read 6, iclass 10, count 2 2006.280.07:38:19.47#ibcon#end of sib2, iclass 10, count 2 2006.280.07:38:19.47#ibcon#*mode == 0, iclass 10, count 2 2006.280.07:38:19.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.07:38:19.47#ibcon#[25=AT04-06\r\n] 2006.280.07:38:19.47#ibcon#*before write, iclass 10, count 2 2006.280.07:38:19.47#ibcon#enter sib2, iclass 10, count 2 2006.280.07:38:19.47#ibcon#flushed, iclass 10, count 2 2006.280.07:38:19.47#ibcon#about to write, iclass 10, count 2 2006.280.07:38:19.47#ibcon#wrote, iclass 10, count 2 2006.280.07:38:19.47#ibcon#about to read 3, iclass 10, count 2 2006.280.07:38:19.51#ibcon#read 3, iclass 10, count 2 2006.280.07:38:19.51#ibcon#about to read 4, iclass 10, count 2 2006.280.07:38:19.51#ibcon#read 4, iclass 10, count 2 2006.280.07:38:19.51#ibcon#about to read 5, iclass 10, count 2 2006.280.07:38:19.51#ibcon#read 5, iclass 10, count 2 2006.280.07:38:19.51#ibcon#about to read 6, iclass 10, count 2 2006.280.07:38:19.51#ibcon#read 6, iclass 10, count 2 2006.280.07:38:19.51#ibcon#end of sib2, iclass 10, count 2 2006.280.07:38:19.51#ibcon#*after write, iclass 10, count 2 2006.280.07:38:19.51#ibcon#*before return 0, iclass 10, count 2 2006.280.07:38:19.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:19.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:19.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.07:38:19.51#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:19.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:19.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:19.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:19.63#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:38:19.63#ibcon#first serial, iclass 10, count 0 2006.280.07:38:19.63#ibcon#enter sib2, iclass 10, count 0 2006.280.07:38:19.63#ibcon#flushed, iclass 10, count 0 2006.280.07:38:19.63#ibcon#about to write, iclass 10, count 0 2006.280.07:38:19.63#ibcon#wrote, iclass 10, count 0 2006.280.07:38:19.63#ibcon#about to read 3, iclass 10, count 0 2006.280.07:38:19.65#ibcon#read 3, iclass 10, count 0 2006.280.07:38:19.65#ibcon#about to read 4, iclass 10, count 0 2006.280.07:38:19.65#ibcon#read 4, iclass 10, count 0 2006.280.07:38:19.65#ibcon#about to read 5, iclass 10, count 0 2006.280.07:38:19.65#ibcon#read 5, iclass 10, count 0 2006.280.07:38:19.65#ibcon#about to read 6, iclass 10, count 0 2006.280.07:38:19.65#ibcon#read 6, iclass 10, count 0 2006.280.07:38:19.65#ibcon#end of sib2, iclass 10, count 0 2006.280.07:38:19.65#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:38:19.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:38:19.65#ibcon#[25=USB\r\n] 2006.280.07:38:19.65#ibcon#*before write, iclass 10, count 0 2006.280.07:38:19.65#ibcon#enter sib2, iclass 10, count 0 2006.280.07:38:19.65#ibcon#flushed, iclass 10, count 0 2006.280.07:38:19.65#ibcon#about to write, iclass 10, count 0 2006.280.07:38:19.65#ibcon#wrote, iclass 10, count 0 2006.280.07:38:19.65#ibcon#about to read 3, iclass 10, count 0 2006.280.07:38:19.68#ibcon#read 3, iclass 10, count 0 2006.280.07:38:19.68#ibcon#about to read 4, iclass 10, count 0 2006.280.07:38:19.68#ibcon#read 4, iclass 10, count 0 2006.280.07:38:19.68#ibcon#about to read 5, iclass 10, count 0 2006.280.07:38:19.68#ibcon#read 5, iclass 10, count 0 2006.280.07:38:19.68#ibcon#about to read 6, iclass 10, count 0 2006.280.07:38:19.68#ibcon#read 6, iclass 10, count 0 2006.280.07:38:19.68#ibcon#end of sib2, iclass 10, count 0 2006.280.07:38:19.68#ibcon#*after write, iclass 10, count 0 2006.280.07:38:19.68#ibcon#*before return 0, iclass 10, count 0 2006.280.07:38:19.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:19.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:19.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:38:19.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:38:19.68$vc4f8/valo=5,652.99 2006.280.07:38:19.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.07:38:19.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.07:38:19.68#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:19.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:19.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:19.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:19.68#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:38:19.68#ibcon#first serial, iclass 12, count 0 2006.280.07:38:19.68#ibcon#enter sib2, iclass 12, count 0 2006.280.07:38:19.68#ibcon#flushed, iclass 12, count 0 2006.280.07:38:19.68#ibcon#about to write, iclass 12, count 0 2006.280.07:38:19.68#ibcon#wrote, iclass 12, count 0 2006.280.07:38:19.68#ibcon#about to read 3, iclass 12, count 0 2006.280.07:38:19.70#ibcon#read 3, iclass 12, count 0 2006.280.07:38:19.70#ibcon#about to read 4, iclass 12, count 0 2006.280.07:38:19.70#ibcon#read 4, iclass 12, count 0 2006.280.07:38:19.70#ibcon#about to read 5, iclass 12, count 0 2006.280.07:38:19.70#ibcon#read 5, iclass 12, count 0 2006.280.07:38:19.70#ibcon#about to read 6, iclass 12, count 0 2006.280.07:38:19.70#ibcon#read 6, iclass 12, count 0 2006.280.07:38:19.70#ibcon#end of sib2, iclass 12, count 0 2006.280.07:38:19.70#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:38:19.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:38:19.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:38:19.70#ibcon#*before write, iclass 12, count 0 2006.280.07:38:19.70#ibcon#enter sib2, iclass 12, count 0 2006.280.07:38:19.70#ibcon#flushed, iclass 12, count 0 2006.280.07:38:19.70#ibcon#about to write, iclass 12, count 0 2006.280.07:38:19.70#ibcon#wrote, iclass 12, count 0 2006.280.07:38:19.70#ibcon#about to read 3, iclass 12, count 0 2006.280.07:38:19.74#ibcon#read 3, iclass 12, count 0 2006.280.07:38:19.74#ibcon#about to read 4, iclass 12, count 0 2006.280.07:38:19.74#ibcon#read 4, iclass 12, count 0 2006.280.07:38:19.74#ibcon#about to read 5, iclass 12, count 0 2006.280.07:38:19.74#ibcon#read 5, iclass 12, count 0 2006.280.07:38:19.74#ibcon#about to read 6, iclass 12, count 0 2006.280.07:38:19.74#ibcon#read 6, iclass 12, count 0 2006.280.07:38:19.74#ibcon#end of sib2, iclass 12, count 0 2006.280.07:38:19.74#ibcon#*after write, iclass 12, count 0 2006.280.07:38:19.74#ibcon#*before return 0, iclass 12, count 0 2006.280.07:38:19.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:19.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:19.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:38:19.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:38:19.74$vc4f8/va=5,7 2006.280.07:38:19.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.07:38:19.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.07:38:19.74#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:19.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:19.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:19.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:19.80#ibcon#enter wrdev, iclass 14, count 2 2006.280.07:38:19.80#ibcon#first serial, iclass 14, count 2 2006.280.07:38:19.80#ibcon#enter sib2, iclass 14, count 2 2006.280.07:38:19.80#ibcon#flushed, iclass 14, count 2 2006.280.07:38:19.80#ibcon#about to write, iclass 14, count 2 2006.280.07:38:19.80#ibcon#wrote, iclass 14, count 2 2006.280.07:38:19.80#ibcon#about to read 3, iclass 14, count 2 2006.280.07:38:19.82#ibcon#read 3, iclass 14, count 2 2006.280.07:38:19.82#ibcon#about to read 4, iclass 14, count 2 2006.280.07:38:19.82#ibcon#read 4, iclass 14, count 2 2006.280.07:38:19.82#ibcon#about to read 5, iclass 14, count 2 2006.280.07:38:19.82#ibcon#read 5, iclass 14, count 2 2006.280.07:38:19.82#ibcon#about to read 6, iclass 14, count 2 2006.280.07:38:19.82#ibcon#read 6, iclass 14, count 2 2006.280.07:38:19.82#ibcon#end of sib2, iclass 14, count 2 2006.280.07:38:19.82#ibcon#*mode == 0, iclass 14, count 2 2006.280.07:38:19.82#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.07:38:19.82#ibcon#[25=AT05-07\r\n] 2006.280.07:38:19.82#ibcon#*before write, iclass 14, count 2 2006.280.07:38:19.82#ibcon#enter sib2, iclass 14, count 2 2006.280.07:38:19.82#ibcon#flushed, iclass 14, count 2 2006.280.07:38:19.82#ibcon#about to write, iclass 14, count 2 2006.280.07:38:19.82#ibcon#wrote, iclass 14, count 2 2006.280.07:38:19.82#ibcon#about to read 3, iclass 14, count 2 2006.280.07:38:19.85#ibcon#read 3, iclass 14, count 2 2006.280.07:38:19.85#ibcon#about to read 4, iclass 14, count 2 2006.280.07:38:19.85#ibcon#read 4, iclass 14, count 2 2006.280.07:38:19.85#ibcon#about to read 5, iclass 14, count 2 2006.280.07:38:19.85#ibcon#read 5, iclass 14, count 2 2006.280.07:38:19.85#ibcon#about to read 6, iclass 14, count 2 2006.280.07:38:19.85#ibcon#read 6, iclass 14, count 2 2006.280.07:38:19.85#ibcon#end of sib2, iclass 14, count 2 2006.280.07:38:19.85#ibcon#*after write, iclass 14, count 2 2006.280.07:38:19.85#ibcon#*before return 0, iclass 14, count 2 2006.280.07:38:19.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:19.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:19.85#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.07:38:19.85#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:19.85#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:19.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:19.97#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:19.97#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:38:19.97#ibcon#first serial, iclass 14, count 0 2006.280.07:38:19.97#ibcon#enter sib2, iclass 14, count 0 2006.280.07:38:19.97#ibcon#flushed, iclass 14, count 0 2006.280.07:38:19.97#ibcon#about to write, iclass 14, count 0 2006.280.07:38:19.97#ibcon#wrote, iclass 14, count 0 2006.280.07:38:19.97#ibcon#about to read 3, iclass 14, count 0 2006.280.07:38:19.99#ibcon#read 3, iclass 14, count 0 2006.280.07:38:19.99#ibcon#about to read 4, iclass 14, count 0 2006.280.07:38:19.99#ibcon#read 4, iclass 14, count 0 2006.280.07:38:19.99#ibcon#about to read 5, iclass 14, count 0 2006.280.07:38:19.99#ibcon#read 5, iclass 14, count 0 2006.280.07:38:19.99#ibcon#about to read 6, iclass 14, count 0 2006.280.07:38:19.99#ibcon#read 6, iclass 14, count 0 2006.280.07:38:19.99#ibcon#end of sib2, iclass 14, count 0 2006.280.07:38:19.99#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:38:19.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:38:19.99#ibcon#[25=USB\r\n] 2006.280.07:38:19.99#ibcon#*before write, iclass 14, count 0 2006.280.07:38:19.99#ibcon#enter sib2, iclass 14, count 0 2006.280.07:38:19.99#ibcon#flushed, iclass 14, count 0 2006.280.07:38:19.99#ibcon#about to write, iclass 14, count 0 2006.280.07:38:19.99#ibcon#wrote, iclass 14, count 0 2006.280.07:38:19.99#ibcon#about to read 3, iclass 14, count 0 2006.280.07:38:20.02#ibcon#read 3, iclass 14, count 0 2006.280.07:38:20.02#ibcon#about to read 4, iclass 14, count 0 2006.280.07:38:20.02#ibcon#read 4, iclass 14, count 0 2006.280.07:38:20.02#ibcon#about to read 5, iclass 14, count 0 2006.280.07:38:20.02#ibcon#read 5, iclass 14, count 0 2006.280.07:38:20.02#ibcon#about to read 6, iclass 14, count 0 2006.280.07:38:20.02#ibcon#read 6, iclass 14, count 0 2006.280.07:38:20.02#ibcon#end of sib2, iclass 14, count 0 2006.280.07:38:20.02#ibcon#*after write, iclass 14, count 0 2006.280.07:38:20.02#ibcon#*before return 0, iclass 14, count 0 2006.280.07:38:20.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:20.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:20.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:38:20.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:38:20.02$vc4f8/valo=6,772.99 2006.280.07:38:20.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:38:20.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:38:20.02#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:20.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:20.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:20.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:20.02#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:38:20.02#ibcon#first serial, iclass 16, count 0 2006.280.07:38:20.02#ibcon#enter sib2, iclass 16, count 0 2006.280.07:38:20.02#ibcon#flushed, iclass 16, count 0 2006.280.07:38:20.02#ibcon#about to write, iclass 16, count 0 2006.280.07:38:20.02#ibcon#wrote, iclass 16, count 0 2006.280.07:38:20.02#ibcon#about to read 3, iclass 16, count 0 2006.280.07:38:20.04#ibcon#read 3, iclass 16, count 0 2006.280.07:38:20.04#ibcon#about to read 4, iclass 16, count 0 2006.280.07:38:20.04#ibcon#read 4, iclass 16, count 0 2006.280.07:38:20.04#ibcon#about to read 5, iclass 16, count 0 2006.280.07:38:20.04#ibcon#read 5, iclass 16, count 0 2006.280.07:38:20.04#ibcon#about to read 6, iclass 16, count 0 2006.280.07:38:20.04#ibcon#read 6, iclass 16, count 0 2006.280.07:38:20.04#ibcon#end of sib2, iclass 16, count 0 2006.280.07:38:20.04#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:38:20.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:38:20.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:38:20.04#ibcon#*before write, iclass 16, count 0 2006.280.07:38:20.04#ibcon#enter sib2, iclass 16, count 0 2006.280.07:38:20.04#ibcon#flushed, iclass 16, count 0 2006.280.07:38:20.04#ibcon#about to write, iclass 16, count 0 2006.280.07:38:20.04#ibcon#wrote, iclass 16, count 0 2006.280.07:38:20.04#ibcon#about to read 3, iclass 16, count 0 2006.280.07:38:20.08#ibcon#read 3, iclass 16, count 0 2006.280.07:38:20.08#ibcon#about to read 4, iclass 16, count 0 2006.280.07:38:20.08#ibcon#read 4, iclass 16, count 0 2006.280.07:38:20.08#ibcon#about to read 5, iclass 16, count 0 2006.280.07:38:20.08#ibcon#read 5, iclass 16, count 0 2006.280.07:38:20.08#ibcon#about to read 6, iclass 16, count 0 2006.280.07:38:20.08#ibcon#read 6, iclass 16, count 0 2006.280.07:38:20.08#ibcon#end of sib2, iclass 16, count 0 2006.280.07:38:20.08#ibcon#*after write, iclass 16, count 0 2006.280.07:38:20.08#ibcon#*before return 0, iclass 16, count 0 2006.280.07:38:20.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:20.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:20.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:38:20.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:38:20.08$vc4f8/va=6,6 2006.280.07:38:20.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.07:38:20.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.07:38:20.08#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:20.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:20.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:20.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:20.14#ibcon#enter wrdev, iclass 18, count 2 2006.280.07:38:20.14#ibcon#first serial, iclass 18, count 2 2006.280.07:38:20.14#ibcon#enter sib2, iclass 18, count 2 2006.280.07:38:20.14#ibcon#flushed, iclass 18, count 2 2006.280.07:38:20.14#ibcon#about to write, iclass 18, count 2 2006.280.07:38:20.14#ibcon#wrote, iclass 18, count 2 2006.280.07:38:20.14#ibcon#about to read 3, iclass 18, count 2 2006.280.07:38:20.16#ibcon#read 3, iclass 18, count 2 2006.280.07:38:20.16#ibcon#about to read 4, iclass 18, count 2 2006.280.07:38:20.16#ibcon#read 4, iclass 18, count 2 2006.280.07:38:20.16#ibcon#about to read 5, iclass 18, count 2 2006.280.07:38:20.16#ibcon#read 5, iclass 18, count 2 2006.280.07:38:20.16#ibcon#about to read 6, iclass 18, count 2 2006.280.07:38:20.16#ibcon#read 6, iclass 18, count 2 2006.280.07:38:20.16#ibcon#end of sib2, iclass 18, count 2 2006.280.07:38:20.16#ibcon#*mode == 0, iclass 18, count 2 2006.280.07:38:20.16#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.07:38:20.16#ibcon#[25=AT06-06\r\n] 2006.280.07:38:20.16#ibcon#*before write, iclass 18, count 2 2006.280.07:38:20.16#ibcon#enter sib2, iclass 18, count 2 2006.280.07:38:20.16#ibcon#flushed, iclass 18, count 2 2006.280.07:38:20.16#ibcon#about to write, iclass 18, count 2 2006.280.07:38:20.16#ibcon#wrote, iclass 18, count 2 2006.280.07:38:20.16#ibcon#about to read 3, iclass 18, count 2 2006.280.07:38:20.19#ibcon#read 3, iclass 18, count 2 2006.280.07:38:20.19#ibcon#about to read 4, iclass 18, count 2 2006.280.07:38:20.19#ibcon#read 4, iclass 18, count 2 2006.280.07:38:20.19#ibcon#about to read 5, iclass 18, count 2 2006.280.07:38:20.19#ibcon#read 5, iclass 18, count 2 2006.280.07:38:20.19#ibcon#about to read 6, iclass 18, count 2 2006.280.07:38:20.19#ibcon#read 6, iclass 18, count 2 2006.280.07:38:20.19#ibcon#end of sib2, iclass 18, count 2 2006.280.07:38:20.19#ibcon#*after write, iclass 18, count 2 2006.280.07:38:20.19#ibcon#*before return 0, iclass 18, count 2 2006.280.07:38:20.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:20.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:20.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.07:38:20.19#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:20.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:38:20.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:38:20.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:38:20.31#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:38:20.31#ibcon#first serial, iclass 18, count 0 2006.280.07:38:20.31#ibcon#enter sib2, iclass 18, count 0 2006.280.07:38:20.31#ibcon#flushed, iclass 18, count 0 2006.280.07:38:20.31#ibcon#about to write, iclass 18, count 0 2006.280.07:38:20.31#ibcon#wrote, iclass 18, count 0 2006.280.07:38:20.31#ibcon#about to read 3, iclass 18, count 0 2006.280.07:38:20.33#ibcon#read 3, iclass 18, count 0 2006.280.07:38:20.33#ibcon#about to read 4, iclass 18, count 0 2006.280.07:38:20.33#ibcon#read 4, iclass 18, count 0 2006.280.07:38:20.33#ibcon#about to read 5, iclass 18, count 0 2006.280.07:38:20.33#ibcon#read 5, iclass 18, count 0 2006.280.07:38:20.33#ibcon#about to read 6, iclass 18, count 0 2006.280.07:38:20.33#ibcon#read 6, iclass 18, count 0 2006.280.07:38:20.33#ibcon#end of sib2, iclass 18, count 0 2006.280.07:38:20.33#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:38:20.33#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:38:20.33#ibcon#[25=USB\r\n] 2006.280.07:38:20.33#ibcon#*before write, iclass 18, count 0 2006.280.07:38:20.33#ibcon#enter sib2, iclass 18, count 0 2006.280.07:38:20.33#ibcon#flushed, iclass 18, count 0 2006.280.07:38:20.33#ibcon#about to write, iclass 18, count 0 2006.280.07:38:20.33#ibcon#wrote, iclass 18, count 0 2006.280.07:38:20.33#ibcon#about to read 3, iclass 18, count 0 2006.280.07:38:20.36#ibcon#read 3, iclass 18, count 0 2006.280.07:38:20.36#ibcon#about to read 4, iclass 18, count 0 2006.280.07:38:20.36#ibcon#read 4, iclass 18, count 0 2006.280.07:38:20.36#ibcon#about to read 5, iclass 18, count 0 2006.280.07:38:20.36#ibcon#read 5, iclass 18, count 0 2006.280.07:38:20.36#ibcon#about to read 6, iclass 18, count 0 2006.280.07:38:20.36#ibcon#read 6, iclass 18, count 0 2006.280.07:38:20.36#ibcon#end of sib2, iclass 18, count 0 2006.280.07:38:20.36#ibcon#*after write, iclass 18, count 0 2006.280.07:38:20.36#ibcon#*before return 0, iclass 18, count 0 2006.280.07:38:20.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:38:20.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:38:20.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:38:20.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:38:20.36$vc4f8/valo=7,832.99 2006.280.07:38:20.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.07:38:20.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.07:38:20.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:20.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:38:20.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:38:20.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:38:20.36#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:38:20.36#ibcon#first serial, iclass 20, count 0 2006.280.07:38:20.36#ibcon#enter sib2, iclass 20, count 0 2006.280.07:38:20.36#ibcon#flushed, iclass 20, count 0 2006.280.07:38:20.36#ibcon#about to write, iclass 20, count 0 2006.280.07:38:20.36#ibcon#wrote, iclass 20, count 0 2006.280.07:38:20.36#ibcon#about to read 3, iclass 20, count 0 2006.280.07:38:20.38#ibcon#read 3, iclass 20, count 0 2006.280.07:38:20.38#ibcon#about to read 4, iclass 20, count 0 2006.280.07:38:20.38#ibcon#read 4, iclass 20, count 0 2006.280.07:38:20.38#ibcon#about to read 5, iclass 20, count 0 2006.280.07:38:20.38#ibcon#read 5, iclass 20, count 0 2006.280.07:38:20.38#ibcon#about to read 6, iclass 20, count 0 2006.280.07:38:20.38#ibcon#read 6, iclass 20, count 0 2006.280.07:38:20.38#ibcon#end of sib2, iclass 20, count 0 2006.280.07:38:20.38#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:38:20.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:38:20.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:38:20.38#ibcon#*before write, iclass 20, count 0 2006.280.07:38:20.38#ibcon#enter sib2, iclass 20, count 0 2006.280.07:38:20.38#ibcon#flushed, iclass 20, count 0 2006.280.07:38:20.38#ibcon#about to write, iclass 20, count 0 2006.280.07:38:20.38#ibcon#wrote, iclass 20, count 0 2006.280.07:38:20.38#ibcon#about to read 3, iclass 20, count 0 2006.280.07:38:20.42#ibcon#read 3, iclass 20, count 0 2006.280.07:38:20.42#ibcon#about to read 4, iclass 20, count 0 2006.280.07:38:20.42#ibcon#read 4, iclass 20, count 0 2006.280.07:38:20.42#ibcon#about to read 5, iclass 20, count 0 2006.280.07:38:20.42#ibcon#read 5, iclass 20, count 0 2006.280.07:38:20.42#ibcon#about to read 6, iclass 20, count 0 2006.280.07:38:20.42#ibcon#read 6, iclass 20, count 0 2006.280.07:38:20.42#ibcon#end of sib2, iclass 20, count 0 2006.280.07:38:20.42#ibcon#*after write, iclass 20, count 0 2006.280.07:38:20.42#ibcon#*before return 0, iclass 20, count 0 2006.280.07:38:20.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:38:20.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:38:20.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:38:20.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:38:20.42$vc4f8/va=7,6 2006.280.07:38:20.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.07:38:20.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.07:38:20.42#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:20.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:38:20.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:38:20.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:38:20.48#ibcon#enter wrdev, iclass 22, count 2 2006.280.07:38:20.48#ibcon#first serial, iclass 22, count 2 2006.280.07:38:20.48#ibcon#enter sib2, iclass 22, count 2 2006.280.07:38:20.48#ibcon#flushed, iclass 22, count 2 2006.280.07:38:20.48#ibcon#about to write, iclass 22, count 2 2006.280.07:38:20.48#ibcon#wrote, iclass 22, count 2 2006.280.07:38:20.48#ibcon#about to read 3, iclass 22, count 2 2006.280.07:38:20.50#ibcon#read 3, iclass 22, count 2 2006.280.07:38:20.50#ibcon#about to read 4, iclass 22, count 2 2006.280.07:38:20.50#ibcon#read 4, iclass 22, count 2 2006.280.07:38:20.50#ibcon#about to read 5, iclass 22, count 2 2006.280.07:38:20.50#ibcon#read 5, iclass 22, count 2 2006.280.07:38:20.50#ibcon#about to read 6, iclass 22, count 2 2006.280.07:38:20.50#ibcon#read 6, iclass 22, count 2 2006.280.07:38:20.50#ibcon#end of sib2, iclass 22, count 2 2006.280.07:38:20.50#ibcon#*mode == 0, iclass 22, count 2 2006.280.07:38:20.50#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.07:38:20.50#ibcon#[25=AT07-06\r\n] 2006.280.07:38:20.50#ibcon#*before write, iclass 22, count 2 2006.280.07:38:20.50#ibcon#enter sib2, iclass 22, count 2 2006.280.07:38:20.50#ibcon#flushed, iclass 22, count 2 2006.280.07:38:20.50#ibcon#about to write, iclass 22, count 2 2006.280.07:38:20.50#ibcon#wrote, iclass 22, count 2 2006.280.07:38:20.50#ibcon#about to read 3, iclass 22, count 2 2006.280.07:38:20.54#ibcon#read 3, iclass 22, count 2 2006.280.07:38:20.54#ibcon#about to read 4, iclass 22, count 2 2006.280.07:38:20.54#ibcon#read 4, iclass 22, count 2 2006.280.07:38:20.54#ibcon#about to read 5, iclass 22, count 2 2006.280.07:38:20.54#ibcon#read 5, iclass 22, count 2 2006.280.07:38:20.54#ibcon#about to read 6, iclass 22, count 2 2006.280.07:38:20.54#ibcon#read 6, iclass 22, count 2 2006.280.07:38:20.54#ibcon#end of sib2, iclass 22, count 2 2006.280.07:38:20.54#ibcon#*after write, iclass 22, count 2 2006.280.07:38:20.54#ibcon#*before return 0, iclass 22, count 2 2006.280.07:38:20.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:38:20.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:38:20.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.07:38:20.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:20.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:38:20.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:38:20.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:38:20.66#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:38:20.66#ibcon#first serial, iclass 22, count 0 2006.280.07:38:20.66#ibcon#enter sib2, iclass 22, count 0 2006.280.07:38:20.66#ibcon#flushed, iclass 22, count 0 2006.280.07:38:20.66#ibcon#about to write, iclass 22, count 0 2006.280.07:38:20.66#ibcon#wrote, iclass 22, count 0 2006.280.07:38:20.66#ibcon#about to read 3, iclass 22, count 0 2006.280.07:38:20.68#ibcon#read 3, iclass 22, count 0 2006.280.07:38:20.68#ibcon#about to read 4, iclass 22, count 0 2006.280.07:38:20.68#ibcon#read 4, iclass 22, count 0 2006.280.07:38:20.68#ibcon#about to read 5, iclass 22, count 0 2006.280.07:38:20.68#ibcon#read 5, iclass 22, count 0 2006.280.07:38:20.68#ibcon#about to read 6, iclass 22, count 0 2006.280.07:38:20.68#ibcon#read 6, iclass 22, count 0 2006.280.07:38:20.68#ibcon#end of sib2, iclass 22, count 0 2006.280.07:38:20.68#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:38:20.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:38:20.68#ibcon#[25=USB\r\n] 2006.280.07:38:20.68#ibcon#*before write, iclass 22, count 0 2006.280.07:38:20.68#ibcon#enter sib2, iclass 22, count 0 2006.280.07:38:20.68#ibcon#flushed, iclass 22, count 0 2006.280.07:38:20.68#ibcon#about to write, iclass 22, count 0 2006.280.07:38:20.68#ibcon#wrote, iclass 22, count 0 2006.280.07:38:20.68#ibcon#about to read 3, iclass 22, count 0 2006.280.07:38:20.71#ibcon#read 3, iclass 22, count 0 2006.280.07:38:20.71#ibcon#about to read 4, iclass 22, count 0 2006.280.07:38:20.71#ibcon#read 4, iclass 22, count 0 2006.280.07:38:20.71#ibcon#about to read 5, iclass 22, count 0 2006.280.07:38:20.71#ibcon#read 5, iclass 22, count 0 2006.280.07:38:20.71#ibcon#about to read 6, iclass 22, count 0 2006.280.07:38:20.71#ibcon#read 6, iclass 22, count 0 2006.280.07:38:20.71#ibcon#end of sib2, iclass 22, count 0 2006.280.07:38:20.71#ibcon#*after write, iclass 22, count 0 2006.280.07:38:20.71#ibcon#*before return 0, iclass 22, count 0 2006.280.07:38:20.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:38:20.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:38:20.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:38:20.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:38:20.71$vc4f8/valo=8,852.99 2006.280.07:38:20.71#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.07:38:20.71#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.07:38:20.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:20.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:38:20.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:38:20.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:38:20.71#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:38:20.71#ibcon#first serial, iclass 24, count 0 2006.280.07:38:20.71#ibcon#enter sib2, iclass 24, count 0 2006.280.07:38:20.71#ibcon#flushed, iclass 24, count 0 2006.280.07:38:20.71#ibcon#about to write, iclass 24, count 0 2006.280.07:38:20.71#ibcon#wrote, iclass 24, count 0 2006.280.07:38:20.71#ibcon#about to read 3, iclass 24, count 0 2006.280.07:38:20.73#ibcon#read 3, iclass 24, count 0 2006.280.07:38:20.73#ibcon#about to read 4, iclass 24, count 0 2006.280.07:38:20.73#ibcon#read 4, iclass 24, count 0 2006.280.07:38:20.73#ibcon#about to read 5, iclass 24, count 0 2006.280.07:38:20.73#ibcon#read 5, iclass 24, count 0 2006.280.07:38:20.73#ibcon#about to read 6, iclass 24, count 0 2006.280.07:38:20.73#ibcon#read 6, iclass 24, count 0 2006.280.07:38:20.73#ibcon#end of sib2, iclass 24, count 0 2006.280.07:38:20.73#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:38:20.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:38:20.75#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:38:20.75#ibcon#*before write, iclass 24, count 0 2006.280.07:38:20.75#ibcon#enter sib2, iclass 24, count 0 2006.280.07:38:20.76#ibcon#flushed, iclass 24, count 0 2006.280.07:38:20.76#ibcon#about to write, iclass 24, count 0 2006.280.07:38:20.76#ibcon#wrote, iclass 24, count 0 2006.280.07:38:20.76#ibcon#about to read 3, iclass 24, count 0 2006.280.07:38:20.80#ibcon#read 3, iclass 24, count 0 2006.280.07:38:20.80#ibcon#about to read 4, iclass 24, count 0 2006.280.07:38:20.80#ibcon#read 4, iclass 24, count 0 2006.280.07:38:20.80#ibcon#about to read 5, iclass 24, count 0 2006.280.07:38:20.80#ibcon#read 5, iclass 24, count 0 2006.280.07:38:20.80#ibcon#about to read 6, iclass 24, count 0 2006.280.07:38:20.80#ibcon#read 6, iclass 24, count 0 2006.280.07:38:20.80#ibcon#end of sib2, iclass 24, count 0 2006.280.07:38:20.80#ibcon#*after write, iclass 24, count 0 2006.280.07:38:20.80#ibcon#*before return 0, iclass 24, count 0 2006.280.07:38:20.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:38:20.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:38:20.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:38:20.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:38:20.80$vc4f8/va=8,6 2006.280.07:38:20.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.07:38:20.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.07:38:20.80#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:20.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:38:20.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:38:20.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:38:20.83#ibcon#enter wrdev, iclass 26, count 2 2006.280.07:38:20.83#ibcon#first serial, iclass 26, count 2 2006.280.07:38:20.83#ibcon#enter sib2, iclass 26, count 2 2006.280.07:38:20.83#ibcon#flushed, iclass 26, count 2 2006.280.07:38:20.83#ibcon#about to write, iclass 26, count 2 2006.280.07:38:20.83#ibcon#wrote, iclass 26, count 2 2006.280.07:38:20.83#ibcon#about to read 3, iclass 26, count 2 2006.280.07:38:20.85#ibcon#read 3, iclass 26, count 2 2006.280.07:38:20.85#ibcon#about to read 4, iclass 26, count 2 2006.280.07:38:20.85#ibcon#read 4, iclass 26, count 2 2006.280.07:38:20.85#ibcon#about to read 5, iclass 26, count 2 2006.280.07:38:20.85#ibcon#read 5, iclass 26, count 2 2006.280.07:38:20.85#ibcon#about to read 6, iclass 26, count 2 2006.280.07:38:20.85#ibcon#read 6, iclass 26, count 2 2006.280.07:38:20.85#ibcon#end of sib2, iclass 26, count 2 2006.280.07:38:20.85#ibcon#*mode == 0, iclass 26, count 2 2006.280.07:38:20.85#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.07:38:20.85#ibcon#[25=AT08-06\r\n] 2006.280.07:38:20.85#ibcon#*before write, iclass 26, count 2 2006.280.07:38:20.85#ibcon#enter sib2, iclass 26, count 2 2006.280.07:38:20.85#ibcon#flushed, iclass 26, count 2 2006.280.07:38:20.85#ibcon#about to write, iclass 26, count 2 2006.280.07:38:20.85#ibcon#wrote, iclass 26, count 2 2006.280.07:38:20.85#ibcon#about to read 3, iclass 26, count 2 2006.280.07:38:20.88#ibcon#read 3, iclass 26, count 2 2006.280.07:38:20.88#ibcon#about to read 4, iclass 26, count 2 2006.280.07:38:20.88#ibcon#read 4, iclass 26, count 2 2006.280.07:38:20.88#ibcon#about to read 5, iclass 26, count 2 2006.280.07:38:20.88#ibcon#read 5, iclass 26, count 2 2006.280.07:38:20.88#ibcon#about to read 6, iclass 26, count 2 2006.280.07:38:20.88#ibcon#read 6, iclass 26, count 2 2006.280.07:38:20.88#ibcon#end of sib2, iclass 26, count 2 2006.280.07:38:20.88#ibcon#*after write, iclass 26, count 2 2006.280.07:38:20.88#ibcon#*before return 0, iclass 26, count 2 2006.280.07:38:20.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:38:20.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:38:20.88#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.07:38:20.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:20.88#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:38:21.00#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:38:21.00#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:38:21.00#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:38:21.00#ibcon#first serial, iclass 26, count 0 2006.280.07:38:21.00#ibcon#enter sib2, iclass 26, count 0 2006.280.07:38:21.00#ibcon#flushed, iclass 26, count 0 2006.280.07:38:21.00#ibcon#about to write, iclass 26, count 0 2006.280.07:38:21.00#ibcon#wrote, iclass 26, count 0 2006.280.07:38:21.00#ibcon#about to read 3, iclass 26, count 0 2006.280.07:38:21.02#ibcon#read 3, iclass 26, count 0 2006.280.07:38:21.02#ibcon#about to read 4, iclass 26, count 0 2006.280.07:38:21.02#ibcon#read 4, iclass 26, count 0 2006.280.07:38:21.02#ibcon#about to read 5, iclass 26, count 0 2006.280.07:38:21.02#ibcon#read 5, iclass 26, count 0 2006.280.07:38:21.02#ibcon#about to read 6, iclass 26, count 0 2006.280.07:38:21.02#ibcon#read 6, iclass 26, count 0 2006.280.07:38:21.02#ibcon#end of sib2, iclass 26, count 0 2006.280.07:38:21.02#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:38:21.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:38:21.02#ibcon#[25=USB\r\n] 2006.280.07:38:21.02#ibcon#*before write, iclass 26, count 0 2006.280.07:38:21.02#ibcon#enter sib2, iclass 26, count 0 2006.280.07:38:21.02#ibcon#flushed, iclass 26, count 0 2006.280.07:38:21.02#ibcon#about to write, iclass 26, count 0 2006.280.07:38:21.02#ibcon#wrote, iclass 26, count 0 2006.280.07:38:21.02#ibcon#about to read 3, iclass 26, count 0 2006.280.07:38:21.05#ibcon#read 3, iclass 26, count 0 2006.280.07:38:21.05#ibcon#about to read 4, iclass 26, count 0 2006.280.07:38:21.05#ibcon#read 4, iclass 26, count 0 2006.280.07:38:21.05#ibcon#about to read 5, iclass 26, count 0 2006.280.07:38:21.05#ibcon#read 5, iclass 26, count 0 2006.280.07:38:21.05#ibcon#about to read 6, iclass 26, count 0 2006.280.07:38:21.05#ibcon#read 6, iclass 26, count 0 2006.280.07:38:21.05#ibcon#end of sib2, iclass 26, count 0 2006.280.07:38:21.05#ibcon#*after write, iclass 26, count 0 2006.280.07:38:21.05#ibcon#*before return 0, iclass 26, count 0 2006.280.07:38:21.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:38:21.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:38:21.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:38:21.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:38:21.05$vc4f8/vblo=1,632.99 2006.280.07:38:21.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.07:38:21.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.07:38:21.05#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:21.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:38:21.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:38:21.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:38:21.05#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:38:21.05#ibcon#first serial, iclass 28, count 0 2006.280.07:38:21.05#ibcon#enter sib2, iclass 28, count 0 2006.280.07:38:21.05#ibcon#flushed, iclass 28, count 0 2006.280.07:38:21.05#ibcon#about to write, iclass 28, count 0 2006.280.07:38:21.05#ibcon#wrote, iclass 28, count 0 2006.280.07:38:21.05#ibcon#about to read 3, iclass 28, count 0 2006.280.07:38:21.07#ibcon#read 3, iclass 28, count 0 2006.280.07:38:21.07#ibcon#about to read 4, iclass 28, count 0 2006.280.07:38:21.07#ibcon#read 4, iclass 28, count 0 2006.280.07:38:21.07#ibcon#about to read 5, iclass 28, count 0 2006.280.07:38:21.07#ibcon#read 5, iclass 28, count 0 2006.280.07:38:21.07#ibcon#about to read 6, iclass 28, count 0 2006.280.07:38:21.07#ibcon#read 6, iclass 28, count 0 2006.280.07:38:21.07#ibcon#end of sib2, iclass 28, count 0 2006.280.07:38:21.07#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:38:21.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:38:21.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:38:21.07#ibcon#*before write, iclass 28, count 0 2006.280.07:38:21.07#ibcon#enter sib2, iclass 28, count 0 2006.280.07:38:21.07#ibcon#flushed, iclass 28, count 0 2006.280.07:38:21.07#ibcon#about to write, iclass 28, count 0 2006.280.07:38:21.07#ibcon#wrote, iclass 28, count 0 2006.280.07:38:21.07#ibcon#about to read 3, iclass 28, count 0 2006.280.07:38:21.11#ibcon#read 3, iclass 28, count 0 2006.280.07:38:21.11#ibcon#about to read 4, iclass 28, count 0 2006.280.07:38:21.11#ibcon#read 4, iclass 28, count 0 2006.280.07:38:21.11#ibcon#about to read 5, iclass 28, count 0 2006.280.07:38:21.11#ibcon#read 5, iclass 28, count 0 2006.280.07:38:21.11#ibcon#about to read 6, iclass 28, count 0 2006.280.07:38:21.11#ibcon#read 6, iclass 28, count 0 2006.280.07:38:21.11#ibcon#end of sib2, iclass 28, count 0 2006.280.07:38:21.11#ibcon#*after write, iclass 28, count 0 2006.280.07:38:21.11#ibcon#*before return 0, iclass 28, count 0 2006.280.07:38:21.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:38:21.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:38:21.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:38:21.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:38:21.11$vc4f8/vb=1,4 2006.280.07:38:21.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.07:38:21.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.07:38:21.11#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:21.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:38:21.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:38:21.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:38:21.11#ibcon#enter wrdev, iclass 30, count 2 2006.280.07:38:21.11#ibcon#first serial, iclass 30, count 2 2006.280.07:38:21.11#ibcon#enter sib2, iclass 30, count 2 2006.280.07:38:21.11#ibcon#flushed, iclass 30, count 2 2006.280.07:38:21.11#ibcon#about to write, iclass 30, count 2 2006.280.07:38:21.11#ibcon#wrote, iclass 30, count 2 2006.280.07:38:21.11#ibcon#about to read 3, iclass 30, count 2 2006.280.07:38:21.13#ibcon#read 3, iclass 30, count 2 2006.280.07:38:21.13#ibcon#about to read 4, iclass 30, count 2 2006.280.07:38:21.13#ibcon#read 4, iclass 30, count 2 2006.280.07:38:21.13#ibcon#about to read 5, iclass 30, count 2 2006.280.07:38:21.13#ibcon#read 5, iclass 30, count 2 2006.280.07:38:21.13#ibcon#about to read 6, iclass 30, count 2 2006.280.07:38:21.13#ibcon#read 6, iclass 30, count 2 2006.280.07:38:21.13#ibcon#end of sib2, iclass 30, count 2 2006.280.07:38:21.13#ibcon#*mode == 0, iclass 30, count 2 2006.280.07:38:21.13#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.07:38:21.13#ibcon#[27=AT01-04\r\n] 2006.280.07:38:21.13#ibcon#*before write, iclass 30, count 2 2006.280.07:38:21.13#ibcon#enter sib2, iclass 30, count 2 2006.280.07:38:21.13#ibcon#flushed, iclass 30, count 2 2006.280.07:38:21.13#ibcon#about to write, iclass 30, count 2 2006.280.07:38:21.13#ibcon#wrote, iclass 30, count 2 2006.280.07:38:21.13#ibcon#about to read 3, iclass 30, count 2 2006.280.07:38:21.16#ibcon#read 3, iclass 30, count 2 2006.280.07:38:21.16#ibcon#about to read 4, iclass 30, count 2 2006.280.07:38:21.16#ibcon#read 4, iclass 30, count 2 2006.280.07:38:21.16#ibcon#about to read 5, iclass 30, count 2 2006.280.07:38:21.16#ibcon#read 5, iclass 30, count 2 2006.280.07:38:21.16#ibcon#about to read 6, iclass 30, count 2 2006.280.07:38:21.16#ibcon#read 6, iclass 30, count 2 2006.280.07:38:21.16#ibcon#end of sib2, iclass 30, count 2 2006.280.07:38:21.16#ibcon#*after write, iclass 30, count 2 2006.280.07:38:21.16#ibcon#*before return 0, iclass 30, count 2 2006.280.07:38:21.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:38:21.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:38:21.16#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.07:38:21.16#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:21.16#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:38:21.28#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:38:21.28#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:38:21.28#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:38:21.28#ibcon#first serial, iclass 30, count 0 2006.280.07:38:21.28#ibcon#enter sib2, iclass 30, count 0 2006.280.07:38:21.28#ibcon#flushed, iclass 30, count 0 2006.280.07:38:21.28#ibcon#about to write, iclass 30, count 0 2006.280.07:38:21.28#ibcon#wrote, iclass 30, count 0 2006.280.07:38:21.28#ibcon#about to read 3, iclass 30, count 0 2006.280.07:38:21.30#ibcon#read 3, iclass 30, count 0 2006.280.07:38:21.30#ibcon#about to read 4, iclass 30, count 0 2006.280.07:38:21.30#ibcon#read 4, iclass 30, count 0 2006.280.07:38:21.30#ibcon#about to read 5, iclass 30, count 0 2006.280.07:38:21.30#ibcon#read 5, iclass 30, count 0 2006.280.07:38:21.30#ibcon#about to read 6, iclass 30, count 0 2006.280.07:38:21.30#ibcon#read 6, iclass 30, count 0 2006.280.07:38:21.30#ibcon#end of sib2, iclass 30, count 0 2006.280.07:38:21.30#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:38:21.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:38:21.30#ibcon#[27=USB\r\n] 2006.280.07:38:21.30#ibcon#*before write, iclass 30, count 0 2006.280.07:38:21.30#ibcon#enter sib2, iclass 30, count 0 2006.280.07:38:21.30#ibcon#flushed, iclass 30, count 0 2006.280.07:38:21.30#ibcon#about to write, iclass 30, count 0 2006.280.07:38:21.30#ibcon#wrote, iclass 30, count 0 2006.280.07:38:21.30#ibcon#about to read 3, iclass 30, count 0 2006.280.07:38:21.33#ibcon#read 3, iclass 30, count 0 2006.280.07:38:21.33#ibcon#about to read 4, iclass 30, count 0 2006.280.07:38:21.33#ibcon#read 4, iclass 30, count 0 2006.280.07:38:21.33#ibcon#about to read 5, iclass 30, count 0 2006.280.07:38:21.33#ibcon#read 5, iclass 30, count 0 2006.280.07:38:21.33#ibcon#about to read 6, iclass 30, count 0 2006.280.07:38:21.33#ibcon#read 6, iclass 30, count 0 2006.280.07:38:21.33#ibcon#end of sib2, iclass 30, count 0 2006.280.07:38:21.33#ibcon#*after write, iclass 30, count 0 2006.280.07:38:21.33#ibcon#*before return 0, iclass 30, count 0 2006.280.07:38:21.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:38:21.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:38:21.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:38:21.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:38:21.33$vc4f8/vblo=2,640.99 2006.280.07:38:21.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:38:21.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:38:21.33#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:21.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:21.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:21.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:21.33#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:38:21.33#ibcon#first serial, iclass 32, count 0 2006.280.07:38:21.33#ibcon#enter sib2, iclass 32, count 0 2006.280.07:38:21.33#ibcon#flushed, iclass 32, count 0 2006.280.07:38:21.33#ibcon#about to write, iclass 32, count 0 2006.280.07:38:21.33#ibcon#wrote, iclass 32, count 0 2006.280.07:38:21.33#ibcon#about to read 3, iclass 32, count 0 2006.280.07:38:21.35#ibcon#read 3, iclass 32, count 0 2006.280.07:38:21.35#ibcon#about to read 4, iclass 32, count 0 2006.280.07:38:21.35#ibcon#read 4, iclass 32, count 0 2006.280.07:38:21.35#ibcon#about to read 5, iclass 32, count 0 2006.280.07:38:21.35#ibcon#read 5, iclass 32, count 0 2006.280.07:38:21.35#ibcon#about to read 6, iclass 32, count 0 2006.280.07:38:21.35#ibcon#read 6, iclass 32, count 0 2006.280.07:38:21.35#ibcon#end of sib2, iclass 32, count 0 2006.280.07:38:21.35#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:38:21.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:38:21.39#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:38:21.39#ibcon#*before write, iclass 32, count 0 2006.280.07:38:21.39#ibcon#enter sib2, iclass 32, count 0 2006.280.07:38:21.39#ibcon#flushed, iclass 32, count 0 2006.280.07:38:21.39#ibcon#about to write, iclass 32, count 0 2006.280.07:38:21.39#ibcon#wrote, iclass 32, count 0 2006.280.07:38:21.39#ibcon#about to read 3, iclass 32, count 0 2006.280.07:38:21.44#ibcon#read 3, iclass 32, count 0 2006.280.07:38:21.44#ibcon#about to read 4, iclass 32, count 0 2006.280.07:38:21.44#ibcon#read 4, iclass 32, count 0 2006.280.07:38:21.44#ibcon#about to read 5, iclass 32, count 0 2006.280.07:38:21.44#ibcon#read 5, iclass 32, count 0 2006.280.07:38:21.44#ibcon#about to read 6, iclass 32, count 0 2006.280.07:38:21.44#ibcon#read 6, iclass 32, count 0 2006.280.07:38:21.44#ibcon#end of sib2, iclass 32, count 0 2006.280.07:38:21.44#ibcon#*after write, iclass 32, count 0 2006.280.07:38:21.44#ibcon#*before return 0, iclass 32, count 0 2006.280.07:38:21.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:21.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:38:21.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:38:21.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:38:21.44$vc4f8/vb=2,5 2006.280.07:38:21.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.07:38:21.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.07:38:21.44#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:21.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:21.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:21.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:21.44#ibcon#enter wrdev, iclass 34, count 2 2006.280.07:38:21.44#ibcon#first serial, iclass 34, count 2 2006.280.07:38:21.44#ibcon#enter sib2, iclass 34, count 2 2006.280.07:38:21.44#ibcon#flushed, iclass 34, count 2 2006.280.07:38:21.44#ibcon#about to write, iclass 34, count 2 2006.280.07:38:21.44#ibcon#wrote, iclass 34, count 2 2006.280.07:38:21.44#ibcon#about to read 3, iclass 34, count 2 2006.280.07:38:21.46#ibcon#read 3, iclass 34, count 2 2006.280.07:38:21.46#ibcon#about to read 4, iclass 34, count 2 2006.280.07:38:21.46#ibcon#read 4, iclass 34, count 2 2006.280.07:38:21.46#ibcon#about to read 5, iclass 34, count 2 2006.280.07:38:21.46#ibcon#read 5, iclass 34, count 2 2006.280.07:38:21.46#ibcon#about to read 6, iclass 34, count 2 2006.280.07:38:21.46#ibcon#read 6, iclass 34, count 2 2006.280.07:38:21.46#ibcon#end of sib2, iclass 34, count 2 2006.280.07:38:21.46#ibcon#*mode == 0, iclass 34, count 2 2006.280.07:38:21.46#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.07:38:21.46#ibcon#[27=AT02-05\r\n] 2006.280.07:38:21.46#ibcon#*before write, iclass 34, count 2 2006.280.07:38:21.46#ibcon#enter sib2, iclass 34, count 2 2006.280.07:38:21.46#ibcon#flushed, iclass 34, count 2 2006.280.07:38:21.46#ibcon#about to write, iclass 34, count 2 2006.280.07:38:21.46#ibcon#wrote, iclass 34, count 2 2006.280.07:38:21.46#ibcon#about to read 3, iclass 34, count 2 2006.280.07:38:21.50#ibcon#read 3, iclass 34, count 2 2006.280.07:38:21.50#ibcon#about to read 4, iclass 34, count 2 2006.280.07:38:21.50#ibcon#read 4, iclass 34, count 2 2006.280.07:38:21.50#ibcon#about to read 5, iclass 34, count 2 2006.280.07:38:21.50#ibcon#read 5, iclass 34, count 2 2006.280.07:38:21.50#ibcon#about to read 6, iclass 34, count 2 2006.280.07:38:21.50#ibcon#read 6, iclass 34, count 2 2006.280.07:38:21.50#ibcon#end of sib2, iclass 34, count 2 2006.280.07:38:21.50#ibcon#*after write, iclass 34, count 2 2006.280.07:38:21.50#ibcon#*before return 0, iclass 34, count 2 2006.280.07:38:21.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:21.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:38:21.50#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.07:38:21.50#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:21.50#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:21.62#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:21.62#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:21.62#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:38:21.62#ibcon#first serial, iclass 34, count 0 2006.280.07:38:21.62#ibcon#enter sib2, iclass 34, count 0 2006.280.07:38:21.62#ibcon#flushed, iclass 34, count 0 2006.280.07:38:21.62#ibcon#about to write, iclass 34, count 0 2006.280.07:38:21.62#ibcon#wrote, iclass 34, count 0 2006.280.07:38:21.62#ibcon#about to read 3, iclass 34, count 0 2006.280.07:38:21.64#ibcon#read 3, iclass 34, count 0 2006.280.07:38:21.64#ibcon#about to read 4, iclass 34, count 0 2006.280.07:38:21.64#ibcon#read 4, iclass 34, count 0 2006.280.07:38:21.64#ibcon#about to read 5, iclass 34, count 0 2006.280.07:38:21.64#ibcon#read 5, iclass 34, count 0 2006.280.07:38:21.64#ibcon#about to read 6, iclass 34, count 0 2006.280.07:38:21.64#ibcon#read 6, iclass 34, count 0 2006.280.07:38:21.64#ibcon#end of sib2, iclass 34, count 0 2006.280.07:38:21.64#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:38:21.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:38:21.64#ibcon#[27=USB\r\n] 2006.280.07:38:21.64#ibcon#*before write, iclass 34, count 0 2006.280.07:38:21.64#ibcon#enter sib2, iclass 34, count 0 2006.280.07:38:21.64#ibcon#flushed, iclass 34, count 0 2006.280.07:38:21.64#ibcon#about to write, iclass 34, count 0 2006.280.07:38:21.64#ibcon#wrote, iclass 34, count 0 2006.280.07:38:21.64#ibcon#about to read 3, iclass 34, count 0 2006.280.07:38:21.67#ibcon#read 3, iclass 34, count 0 2006.280.07:38:21.67#ibcon#about to read 4, iclass 34, count 0 2006.280.07:38:21.67#ibcon#read 4, iclass 34, count 0 2006.280.07:38:21.67#ibcon#about to read 5, iclass 34, count 0 2006.280.07:38:21.67#ibcon#read 5, iclass 34, count 0 2006.280.07:38:21.67#ibcon#about to read 6, iclass 34, count 0 2006.280.07:38:21.67#ibcon#read 6, iclass 34, count 0 2006.280.07:38:21.67#ibcon#end of sib2, iclass 34, count 0 2006.280.07:38:21.67#ibcon#*after write, iclass 34, count 0 2006.280.07:38:21.67#ibcon#*before return 0, iclass 34, count 0 2006.280.07:38:21.67#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:21.67#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:38:21.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:38:21.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:38:21.67$vc4f8/vblo=3,656.99 2006.280.07:38:21.67#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.07:38:21.67#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.07:38:21.67#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:21.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:21.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:21.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:21.67#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:38:21.67#ibcon#first serial, iclass 36, count 0 2006.280.07:38:21.67#ibcon#enter sib2, iclass 36, count 0 2006.280.07:38:21.67#ibcon#flushed, iclass 36, count 0 2006.280.07:38:21.67#ibcon#about to write, iclass 36, count 0 2006.280.07:38:21.67#ibcon#wrote, iclass 36, count 0 2006.280.07:38:21.67#ibcon#about to read 3, iclass 36, count 0 2006.280.07:38:21.69#ibcon#read 3, iclass 36, count 0 2006.280.07:38:21.69#ibcon#about to read 4, iclass 36, count 0 2006.280.07:38:21.69#ibcon#read 4, iclass 36, count 0 2006.280.07:38:21.69#ibcon#about to read 5, iclass 36, count 0 2006.280.07:38:21.69#ibcon#read 5, iclass 36, count 0 2006.280.07:38:21.69#ibcon#about to read 6, iclass 36, count 0 2006.280.07:38:21.69#ibcon#read 6, iclass 36, count 0 2006.280.07:38:21.69#ibcon#end of sib2, iclass 36, count 0 2006.280.07:38:21.69#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:38:21.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:38:21.71#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:38:21.71#ibcon#*before write, iclass 36, count 0 2006.280.07:38:21.71#ibcon#enter sib2, iclass 36, count 0 2006.280.07:38:21.71#ibcon#flushed, iclass 36, count 0 2006.280.07:38:21.71#ibcon#about to write, iclass 36, count 0 2006.280.07:38:21.72#ibcon#wrote, iclass 36, count 0 2006.280.07:38:21.72#ibcon#about to read 3, iclass 36, count 0 2006.280.07:38:21.76#ibcon#read 3, iclass 36, count 0 2006.280.07:38:21.76#ibcon#about to read 4, iclass 36, count 0 2006.280.07:38:21.76#ibcon#read 4, iclass 36, count 0 2006.280.07:38:21.76#ibcon#about to read 5, iclass 36, count 0 2006.280.07:38:21.76#ibcon#read 5, iclass 36, count 0 2006.280.07:38:21.76#ibcon#about to read 6, iclass 36, count 0 2006.280.07:38:21.76#ibcon#read 6, iclass 36, count 0 2006.280.07:38:21.76#ibcon#end of sib2, iclass 36, count 0 2006.280.07:38:21.76#ibcon#*after write, iclass 36, count 0 2006.280.07:38:21.76#ibcon#*before return 0, iclass 36, count 0 2006.280.07:38:21.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:21.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:38:21.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:38:21.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:38:21.76$vc4f8/vb=3,4 2006.280.07:38:21.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.07:38:21.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.07:38:21.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:21.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:21.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:21.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:21.79#ibcon#enter wrdev, iclass 38, count 2 2006.280.07:38:21.79#ibcon#first serial, iclass 38, count 2 2006.280.07:38:21.79#ibcon#enter sib2, iclass 38, count 2 2006.280.07:38:21.79#ibcon#flushed, iclass 38, count 2 2006.280.07:38:21.79#ibcon#about to write, iclass 38, count 2 2006.280.07:38:21.79#ibcon#wrote, iclass 38, count 2 2006.280.07:38:21.79#ibcon#about to read 3, iclass 38, count 2 2006.280.07:38:21.81#ibcon#read 3, iclass 38, count 2 2006.280.07:38:21.81#ibcon#about to read 4, iclass 38, count 2 2006.280.07:38:21.81#ibcon#read 4, iclass 38, count 2 2006.280.07:38:21.81#ibcon#about to read 5, iclass 38, count 2 2006.280.07:38:21.81#ibcon#read 5, iclass 38, count 2 2006.280.07:38:21.81#ibcon#about to read 6, iclass 38, count 2 2006.280.07:38:21.81#ibcon#read 6, iclass 38, count 2 2006.280.07:38:21.81#ibcon#end of sib2, iclass 38, count 2 2006.280.07:38:21.81#ibcon#*mode == 0, iclass 38, count 2 2006.280.07:38:21.81#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.07:38:21.81#ibcon#[27=AT03-04\r\n] 2006.280.07:38:21.81#ibcon#*before write, iclass 38, count 2 2006.280.07:38:21.81#ibcon#enter sib2, iclass 38, count 2 2006.280.07:38:21.81#ibcon#flushed, iclass 38, count 2 2006.280.07:38:21.81#ibcon#about to write, iclass 38, count 2 2006.280.07:38:21.81#ibcon#wrote, iclass 38, count 2 2006.280.07:38:21.81#ibcon#about to read 3, iclass 38, count 2 2006.280.07:38:21.84#ibcon#read 3, iclass 38, count 2 2006.280.07:38:21.84#ibcon#about to read 4, iclass 38, count 2 2006.280.07:38:21.84#ibcon#read 4, iclass 38, count 2 2006.280.07:38:21.84#ibcon#about to read 5, iclass 38, count 2 2006.280.07:38:21.84#ibcon#read 5, iclass 38, count 2 2006.280.07:38:21.84#ibcon#about to read 6, iclass 38, count 2 2006.280.07:38:21.84#ibcon#read 6, iclass 38, count 2 2006.280.07:38:21.84#ibcon#end of sib2, iclass 38, count 2 2006.280.07:38:21.84#ibcon#*after write, iclass 38, count 2 2006.280.07:38:21.84#ibcon#*before return 0, iclass 38, count 2 2006.280.07:38:21.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:21.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:38:21.84#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.07:38:21.84#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:21.84#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:21.96#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:21.96#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:21.96#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:38:21.96#ibcon#first serial, iclass 38, count 0 2006.280.07:38:21.96#ibcon#enter sib2, iclass 38, count 0 2006.280.07:38:21.96#ibcon#flushed, iclass 38, count 0 2006.280.07:38:21.96#ibcon#about to write, iclass 38, count 0 2006.280.07:38:21.96#ibcon#wrote, iclass 38, count 0 2006.280.07:38:21.96#ibcon#about to read 3, iclass 38, count 0 2006.280.07:38:21.98#ibcon#read 3, iclass 38, count 0 2006.280.07:38:21.98#ibcon#about to read 4, iclass 38, count 0 2006.280.07:38:21.98#ibcon#read 4, iclass 38, count 0 2006.280.07:38:21.98#ibcon#about to read 5, iclass 38, count 0 2006.280.07:38:21.98#ibcon#read 5, iclass 38, count 0 2006.280.07:38:21.98#ibcon#about to read 6, iclass 38, count 0 2006.280.07:38:21.98#ibcon#read 6, iclass 38, count 0 2006.280.07:38:21.98#ibcon#end of sib2, iclass 38, count 0 2006.280.07:38:21.98#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:38:21.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:38:21.98#ibcon#[27=USB\r\n] 2006.280.07:38:21.98#ibcon#*before write, iclass 38, count 0 2006.280.07:38:21.98#ibcon#enter sib2, iclass 38, count 0 2006.280.07:38:21.98#ibcon#flushed, iclass 38, count 0 2006.280.07:38:21.98#ibcon#about to write, iclass 38, count 0 2006.280.07:38:21.98#ibcon#wrote, iclass 38, count 0 2006.280.07:38:21.98#ibcon#about to read 3, iclass 38, count 0 2006.280.07:38:22.01#ibcon#read 3, iclass 38, count 0 2006.280.07:38:22.01#ibcon#about to read 4, iclass 38, count 0 2006.280.07:38:22.01#ibcon#read 4, iclass 38, count 0 2006.280.07:38:22.01#ibcon#about to read 5, iclass 38, count 0 2006.280.07:38:22.01#ibcon#read 5, iclass 38, count 0 2006.280.07:38:22.01#ibcon#about to read 6, iclass 38, count 0 2006.280.07:38:22.01#ibcon#read 6, iclass 38, count 0 2006.280.07:38:22.01#ibcon#end of sib2, iclass 38, count 0 2006.280.07:38:22.01#ibcon#*after write, iclass 38, count 0 2006.280.07:38:22.01#ibcon#*before return 0, iclass 38, count 0 2006.280.07:38:22.01#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:22.01#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:38:22.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:38:22.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:38:22.01$vc4f8/vblo=4,712.99 2006.280.07:38:22.01#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:38:22.01#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:38:22.01#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:22.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:22.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:22.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:22.01#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:38:22.01#ibcon#first serial, iclass 40, count 0 2006.280.07:38:22.01#ibcon#enter sib2, iclass 40, count 0 2006.280.07:38:22.01#ibcon#flushed, iclass 40, count 0 2006.280.07:38:22.01#ibcon#about to write, iclass 40, count 0 2006.280.07:38:22.01#ibcon#wrote, iclass 40, count 0 2006.280.07:38:22.01#ibcon#about to read 3, iclass 40, count 0 2006.280.07:38:22.03#ibcon#read 3, iclass 40, count 0 2006.280.07:38:22.03#ibcon#about to read 4, iclass 40, count 0 2006.280.07:38:22.03#ibcon#read 4, iclass 40, count 0 2006.280.07:38:22.03#ibcon#about to read 5, iclass 40, count 0 2006.280.07:38:22.03#ibcon#read 5, iclass 40, count 0 2006.280.07:38:22.03#ibcon#about to read 6, iclass 40, count 0 2006.280.07:38:22.03#ibcon#read 6, iclass 40, count 0 2006.280.07:38:22.03#ibcon#end of sib2, iclass 40, count 0 2006.280.07:38:22.03#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:38:22.03#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:38:22.03#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:38:22.03#ibcon#*before write, iclass 40, count 0 2006.280.07:38:22.03#ibcon#enter sib2, iclass 40, count 0 2006.280.07:38:22.03#ibcon#flushed, iclass 40, count 0 2006.280.07:38:22.03#ibcon#about to write, iclass 40, count 0 2006.280.07:38:22.03#ibcon#wrote, iclass 40, count 0 2006.280.07:38:22.03#ibcon#about to read 3, iclass 40, count 0 2006.280.07:38:22.07#ibcon#read 3, iclass 40, count 0 2006.280.07:38:22.07#ibcon#about to read 4, iclass 40, count 0 2006.280.07:38:22.07#ibcon#read 4, iclass 40, count 0 2006.280.07:38:22.07#ibcon#about to read 5, iclass 40, count 0 2006.280.07:38:22.07#ibcon#read 5, iclass 40, count 0 2006.280.07:38:22.07#ibcon#about to read 6, iclass 40, count 0 2006.280.07:38:22.07#ibcon#read 6, iclass 40, count 0 2006.280.07:38:22.07#ibcon#end of sib2, iclass 40, count 0 2006.280.07:38:22.07#ibcon#*after write, iclass 40, count 0 2006.280.07:38:22.07#ibcon#*before return 0, iclass 40, count 0 2006.280.07:38:22.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:22.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:38:22.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:38:22.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:38:22.07$vc4f8/vb=4,4 2006.280.07:38:22.07#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.07:38:22.07#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.07:38:22.07#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:22.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:22.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:22.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:22.13#ibcon#enter wrdev, iclass 4, count 2 2006.280.07:38:22.13#ibcon#first serial, iclass 4, count 2 2006.280.07:38:22.13#ibcon#enter sib2, iclass 4, count 2 2006.280.07:38:22.13#ibcon#flushed, iclass 4, count 2 2006.280.07:38:22.13#ibcon#about to write, iclass 4, count 2 2006.280.07:38:22.13#ibcon#wrote, iclass 4, count 2 2006.280.07:38:22.13#ibcon#about to read 3, iclass 4, count 2 2006.280.07:38:22.15#ibcon#read 3, iclass 4, count 2 2006.280.07:38:22.15#ibcon#about to read 4, iclass 4, count 2 2006.280.07:38:22.15#ibcon#read 4, iclass 4, count 2 2006.280.07:38:22.15#ibcon#about to read 5, iclass 4, count 2 2006.280.07:38:22.15#ibcon#read 5, iclass 4, count 2 2006.280.07:38:22.15#ibcon#about to read 6, iclass 4, count 2 2006.280.07:38:22.15#ibcon#read 6, iclass 4, count 2 2006.280.07:38:22.15#ibcon#end of sib2, iclass 4, count 2 2006.280.07:38:22.15#ibcon#*mode == 0, iclass 4, count 2 2006.280.07:38:22.15#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.07:38:22.15#ibcon#[27=AT04-04\r\n] 2006.280.07:38:22.15#ibcon#*before write, iclass 4, count 2 2006.280.07:38:22.15#ibcon#enter sib2, iclass 4, count 2 2006.280.07:38:22.15#ibcon#flushed, iclass 4, count 2 2006.280.07:38:22.15#ibcon#about to write, iclass 4, count 2 2006.280.07:38:22.15#ibcon#wrote, iclass 4, count 2 2006.280.07:38:22.15#ibcon#about to read 3, iclass 4, count 2 2006.280.07:38:22.18#ibcon#read 3, iclass 4, count 2 2006.280.07:38:22.18#ibcon#about to read 4, iclass 4, count 2 2006.280.07:38:22.18#ibcon#read 4, iclass 4, count 2 2006.280.07:38:22.18#ibcon#about to read 5, iclass 4, count 2 2006.280.07:38:22.18#ibcon#read 5, iclass 4, count 2 2006.280.07:38:22.18#ibcon#about to read 6, iclass 4, count 2 2006.280.07:38:22.18#ibcon#read 6, iclass 4, count 2 2006.280.07:38:22.18#ibcon#end of sib2, iclass 4, count 2 2006.280.07:38:22.18#ibcon#*after write, iclass 4, count 2 2006.280.07:38:22.18#ibcon#*before return 0, iclass 4, count 2 2006.280.07:38:22.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:22.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:38:22.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.07:38:22.18#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:22.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:22.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:22.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:22.30#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:38:22.30#ibcon#first serial, iclass 4, count 0 2006.280.07:38:22.30#ibcon#enter sib2, iclass 4, count 0 2006.280.07:38:22.30#ibcon#flushed, iclass 4, count 0 2006.280.07:38:22.30#ibcon#about to write, iclass 4, count 0 2006.280.07:38:22.30#ibcon#wrote, iclass 4, count 0 2006.280.07:38:22.30#ibcon#about to read 3, iclass 4, count 0 2006.280.07:38:22.32#ibcon#read 3, iclass 4, count 0 2006.280.07:38:22.32#ibcon#about to read 4, iclass 4, count 0 2006.280.07:38:22.32#ibcon#read 4, iclass 4, count 0 2006.280.07:38:22.32#ibcon#about to read 5, iclass 4, count 0 2006.280.07:38:22.32#ibcon#read 5, iclass 4, count 0 2006.280.07:38:22.32#ibcon#about to read 6, iclass 4, count 0 2006.280.07:38:22.32#ibcon#read 6, iclass 4, count 0 2006.280.07:38:22.32#ibcon#end of sib2, iclass 4, count 0 2006.280.07:38:22.32#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:38:22.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:38:22.32#ibcon#[27=USB\r\n] 2006.280.07:38:22.32#ibcon#*before write, iclass 4, count 0 2006.280.07:38:22.32#ibcon#enter sib2, iclass 4, count 0 2006.280.07:38:22.32#ibcon#flushed, iclass 4, count 0 2006.280.07:38:22.32#ibcon#about to write, iclass 4, count 0 2006.280.07:38:22.32#ibcon#wrote, iclass 4, count 0 2006.280.07:38:22.32#ibcon#about to read 3, iclass 4, count 0 2006.280.07:38:22.35#ibcon#read 3, iclass 4, count 0 2006.280.07:38:22.35#ibcon#about to read 4, iclass 4, count 0 2006.280.07:38:22.35#ibcon#read 4, iclass 4, count 0 2006.280.07:38:22.35#ibcon#about to read 5, iclass 4, count 0 2006.280.07:38:22.35#ibcon#read 5, iclass 4, count 0 2006.280.07:38:22.35#ibcon#about to read 6, iclass 4, count 0 2006.280.07:38:22.35#ibcon#read 6, iclass 4, count 0 2006.280.07:38:22.35#ibcon#end of sib2, iclass 4, count 0 2006.280.07:38:22.35#ibcon#*after write, iclass 4, count 0 2006.280.07:38:22.35#ibcon#*before return 0, iclass 4, count 0 2006.280.07:38:22.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:22.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:38:22.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:38:22.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:38:22.35$vc4f8/vblo=5,744.99 2006.280.07:38:22.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.07:38:22.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.07:38:22.35#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:22.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:22.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:22.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:22.35#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:38:22.35#ibcon#first serial, iclass 6, count 0 2006.280.07:38:22.35#ibcon#enter sib2, iclass 6, count 0 2006.280.07:38:22.35#ibcon#flushed, iclass 6, count 0 2006.280.07:38:22.35#ibcon#about to write, iclass 6, count 0 2006.280.07:38:22.35#ibcon#wrote, iclass 6, count 0 2006.280.07:38:22.35#ibcon#about to read 3, iclass 6, count 0 2006.280.07:38:22.37#ibcon#read 3, iclass 6, count 0 2006.280.07:38:22.37#ibcon#about to read 4, iclass 6, count 0 2006.280.07:38:22.37#ibcon#read 4, iclass 6, count 0 2006.280.07:38:22.37#ibcon#about to read 5, iclass 6, count 0 2006.280.07:38:22.37#ibcon#read 5, iclass 6, count 0 2006.280.07:38:22.37#ibcon#about to read 6, iclass 6, count 0 2006.280.07:38:22.37#ibcon#read 6, iclass 6, count 0 2006.280.07:38:22.37#ibcon#end of sib2, iclass 6, count 0 2006.280.07:38:22.37#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:38:22.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:38:22.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:38:22.37#ibcon#*before write, iclass 6, count 0 2006.280.07:38:22.37#ibcon#enter sib2, iclass 6, count 0 2006.280.07:38:22.37#ibcon#flushed, iclass 6, count 0 2006.280.07:38:22.37#ibcon#about to write, iclass 6, count 0 2006.280.07:38:22.37#ibcon#wrote, iclass 6, count 0 2006.280.07:38:22.37#ibcon#about to read 3, iclass 6, count 0 2006.280.07:38:22.41#ibcon#read 3, iclass 6, count 0 2006.280.07:38:22.41#ibcon#about to read 4, iclass 6, count 0 2006.280.07:38:22.41#ibcon#read 4, iclass 6, count 0 2006.280.07:38:22.41#ibcon#about to read 5, iclass 6, count 0 2006.280.07:38:22.41#ibcon#read 5, iclass 6, count 0 2006.280.07:38:22.41#ibcon#about to read 6, iclass 6, count 0 2006.280.07:38:22.41#ibcon#read 6, iclass 6, count 0 2006.280.07:38:22.41#ibcon#end of sib2, iclass 6, count 0 2006.280.07:38:22.41#ibcon#*after write, iclass 6, count 0 2006.280.07:38:22.41#ibcon#*before return 0, iclass 6, count 0 2006.280.07:38:22.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:22.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:38:22.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:38:22.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:38:22.41$vc4f8/vb=5,4 2006.280.07:38:22.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.07:38:22.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.07:38:22.41#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:22.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:22.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:22.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:22.47#ibcon#enter wrdev, iclass 10, count 2 2006.280.07:38:22.47#ibcon#first serial, iclass 10, count 2 2006.280.07:38:22.47#ibcon#enter sib2, iclass 10, count 2 2006.280.07:38:22.47#ibcon#flushed, iclass 10, count 2 2006.280.07:38:22.47#ibcon#about to write, iclass 10, count 2 2006.280.07:38:22.47#ibcon#wrote, iclass 10, count 2 2006.280.07:38:22.47#ibcon#about to read 3, iclass 10, count 2 2006.280.07:38:22.49#ibcon#read 3, iclass 10, count 2 2006.280.07:38:22.49#ibcon#about to read 4, iclass 10, count 2 2006.280.07:38:22.49#ibcon#read 4, iclass 10, count 2 2006.280.07:38:22.49#ibcon#about to read 5, iclass 10, count 2 2006.280.07:38:22.49#ibcon#read 5, iclass 10, count 2 2006.280.07:38:22.49#ibcon#about to read 6, iclass 10, count 2 2006.280.07:38:22.49#ibcon#read 6, iclass 10, count 2 2006.280.07:38:22.49#ibcon#end of sib2, iclass 10, count 2 2006.280.07:38:22.49#ibcon#*mode == 0, iclass 10, count 2 2006.280.07:38:22.49#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.07:38:22.49#ibcon#[27=AT05-04\r\n] 2006.280.07:38:22.49#ibcon#*before write, iclass 10, count 2 2006.280.07:38:22.49#ibcon#enter sib2, iclass 10, count 2 2006.280.07:38:22.49#ibcon#flushed, iclass 10, count 2 2006.280.07:38:22.49#ibcon#about to write, iclass 10, count 2 2006.280.07:38:22.49#ibcon#wrote, iclass 10, count 2 2006.280.07:38:22.49#ibcon#about to read 3, iclass 10, count 2 2006.280.07:38:22.52#ibcon#read 3, iclass 10, count 2 2006.280.07:38:22.52#ibcon#about to read 4, iclass 10, count 2 2006.280.07:38:22.52#ibcon#read 4, iclass 10, count 2 2006.280.07:38:22.52#ibcon#about to read 5, iclass 10, count 2 2006.280.07:38:22.52#ibcon#read 5, iclass 10, count 2 2006.280.07:38:22.52#ibcon#about to read 6, iclass 10, count 2 2006.280.07:38:22.52#ibcon#read 6, iclass 10, count 2 2006.280.07:38:22.52#ibcon#end of sib2, iclass 10, count 2 2006.280.07:38:22.52#ibcon#*after write, iclass 10, count 2 2006.280.07:38:22.52#ibcon#*before return 0, iclass 10, count 2 2006.280.07:38:22.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:22.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:38:22.52#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.07:38:22.52#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:22.52#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:22.64#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:22.64#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:22.64#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:38:22.64#ibcon#first serial, iclass 10, count 0 2006.280.07:38:22.64#ibcon#enter sib2, iclass 10, count 0 2006.280.07:38:22.64#ibcon#flushed, iclass 10, count 0 2006.280.07:38:22.64#ibcon#about to write, iclass 10, count 0 2006.280.07:38:22.64#ibcon#wrote, iclass 10, count 0 2006.280.07:38:22.64#ibcon#about to read 3, iclass 10, count 0 2006.280.07:38:22.66#ibcon#read 3, iclass 10, count 0 2006.280.07:38:22.66#ibcon#about to read 4, iclass 10, count 0 2006.280.07:38:22.66#ibcon#read 4, iclass 10, count 0 2006.280.07:38:22.66#ibcon#about to read 5, iclass 10, count 0 2006.280.07:38:22.66#ibcon#read 5, iclass 10, count 0 2006.280.07:38:22.66#ibcon#about to read 6, iclass 10, count 0 2006.280.07:38:22.66#ibcon#read 6, iclass 10, count 0 2006.280.07:38:22.66#ibcon#end of sib2, iclass 10, count 0 2006.280.07:38:22.66#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:38:22.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:38:22.66#ibcon#[27=USB\r\n] 2006.280.07:38:22.66#ibcon#*before write, iclass 10, count 0 2006.280.07:38:22.66#ibcon#enter sib2, iclass 10, count 0 2006.280.07:38:22.66#ibcon#flushed, iclass 10, count 0 2006.280.07:38:22.66#ibcon#about to write, iclass 10, count 0 2006.280.07:38:22.66#ibcon#wrote, iclass 10, count 0 2006.280.07:38:22.66#ibcon#about to read 3, iclass 10, count 0 2006.280.07:38:22.69#ibcon#read 3, iclass 10, count 0 2006.280.07:38:22.69#ibcon#about to read 4, iclass 10, count 0 2006.280.07:38:22.69#ibcon#read 4, iclass 10, count 0 2006.280.07:38:22.69#ibcon#about to read 5, iclass 10, count 0 2006.280.07:38:22.69#ibcon#read 5, iclass 10, count 0 2006.280.07:38:22.69#ibcon#about to read 6, iclass 10, count 0 2006.280.07:38:22.69#ibcon#read 6, iclass 10, count 0 2006.280.07:38:22.69#ibcon#end of sib2, iclass 10, count 0 2006.280.07:38:22.69#ibcon#*after write, iclass 10, count 0 2006.280.07:38:22.69#ibcon#*before return 0, iclass 10, count 0 2006.280.07:38:22.69#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:22.69#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:38:22.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:38:22.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:38:22.69$vc4f8/vblo=6,752.99 2006.280.07:38:22.69#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.07:38:22.69#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.07:38:22.69#ibcon#ireg 17 cls_cnt 0 2006.280.07:38:22.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:22.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:22.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:22.69#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:38:22.69#ibcon#first serial, iclass 12, count 0 2006.280.07:38:22.69#ibcon#enter sib2, iclass 12, count 0 2006.280.07:38:22.69#ibcon#flushed, iclass 12, count 0 2006.280.07:38:22.69#ibcon#about to write, iclass 12, count 0 2006.280.07:38:22.69#ibcon#wrote, iclass 12, count 0 2006.280.07:38:22.69#ibcon#about to read 3, iclass 12, count 0 2006.280.07:38:22.71#ibcon#read 3, iclass 12, count 0 2006.280.07:38:22.71#ibcon#about to read 4, iclass 12, count 0 2006.280.07:38:22.71#ibcon#read 4, iclass 12, count 0 2006.280.07:38:22.71#ibcon#about to read 5, iclass 12, count 0 2006.280.07:38:22.71#ibcon#read 5, iclass 12, count 0 2006.280.07:38:22.71#ibcon#about to read 6, iclass 12, count 0 2006.280.07:38:22.71#ibcon#read 6, iclass 12, count 0 2006.280.07:38:22.71#ibcon#end of sib2, iclass 12, count 0 2006.280.07:38:22.71#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:38:22.71#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:38:22.71#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:38:22.71#ibcon#*before write, iclass 12, count 0 2006.280.07:38:22.71#ibcon#enter sib2, iclass 12, count 0 2006.280.07:38:22.71#ibcon#flushed, iclass 12, count 0 2006.280.07:38:22.71#ibcon#about to write, iclass 12, count 0 2006.280.07:38:22.71#ibcon#wrote, iclass 12, count 0 2006.280.07:38:22.71#ibcon#about to read 3, iclass 12, count 0 2006.280.07:38:22.75#ibcon#read 3, iclass 12, count 0 2006.280.07:38:22.75#ibcon#about to read 4, iclass 12, count 0 2006.280.07:38:22.75#ibcon#read 4, iclass 12, count 0 2006.280.07:38:22.75#ibcon#about to read 5, iclass 12, count 0 2006.280.07:38:22.75#ibcon#read 5, iclass 12, count 0 2006.280.07:38:22.75#ibcon#about to read 6, iclass 12, count 0 2006.280.07:38:22.75#ibcon#read 6, iclass 12, count 0 2006.280.07:38:22.75#ibcon#end of sib2, iclass 12, count 0 2006.280.07:38:22.75#ibcon#*after write, iclass 12, count 0 2006.280.07:38:22.75#ibcon#*before return 0, iclass 12, count 0 2006.280.07:38:22.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:22.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:38:22.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:38:22.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:38:22.75$vc4f8/vb=6,4 2006.280.07:38:22.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.07:38:22.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.07:38:22.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:38:22.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:22.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:22.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:22.81#ibcon#enter wrdev, iclass 14, count 2 2006.280.07:38:22.81#ibcon#first serial, iclass 14, count 2 2006.280.07:38:22.81#ibcon#enter sib2, iclass 14, count 2 2006.280.07:38:22.81#ibcon#flushed, iclass 14, count 2 2006.280.07:38:22.81#ibcon#about to write, iclass 14, count 2 2006.280.07:38:22.81#ibcon#wrote, iclass 14, count 2 2006.280.07:38:22.81#ibcon#about to read 3, iclass 14, count 2 2006.280.07:38:22.83#ibcon#read 3, iclass 14, count 2 2006.280.07:38:22.83#ibcon#about to read 4, iclass 14, count 2 2006.280.07:38:22.83#ibcon#read 4, iclass 14, count 2 2006.280.07:38:22.83#ibcon#about to read 5, iclass 14, count 2 2006.280.07:38:22.83#ibcon#read 5, iclass 14, count 2 2006.280.07:38:22.83#ibcon#about to read 6, iclass 14, count 2 2006.280.07:38:22.83#ibcon#read 6, iclass 14, count 2 2006.280.07:38:22.83#ibcon#end of sib2, iclass 14, count 2 2006.280.07:38:22.83#ibcon#*mode == 0, iclass 14, count 2 2006.280.07:38:22.83#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.07:38:22.83#ibcon#[27=AT06-04\r\n] 2006.280.07:38:22.83#ibcon#*before write, iclass 14, count 2 2006.280.07:38:22.83#ibcon#enter sib2, iclass 14, count 2 2006.280.07:38:22.83#ibcon#flushed, iclass 14, count 2 2006.280.07:38:22.83#ibcon#about to write, iclass 14, count 2 2006.280.07:38:22.83#ibcon#wrote, iclass 14, count 2 2006.280.07:38:22.83#ibcon#about to read 3, iclass 14, count 2 2006.280.07:38:22.86#ibcon#read 3, iclass 14, count 2 2006.280.07:38:22.86#ibcon#about to read 4, iclass 14, count 2 2006.280.07:38:22.86#ibcon#read 4, iclass 14, count 2 2006.280.07:38:22.86#ibcon#about to read 5, iclass 14, count 2 2006.280.07:38:22.86#ibcon#read 5, iclass 14, count 2 2006.280.07:38:22.86#ibcon#about to read 6, iclass 14, count 2 2006.280.07:38:22.86#ibcon#read 6, iclass 14, count 2 2006.280.07:38:22.86#ibcon#end of sib2, iclass 14, count 2 2006.280.07:38:22.86#ibcon#*after write, iclass 14, count 2 2006.280.07:38:22.86#ibcon#*before return 0, iclass 14, count 2 2006.280.07:38:22.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:22.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:38:22.86#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.07:38:22.86#ibcon#ireg 7 cls_cnt 0 2006.280.07:38:22.86#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:22.98#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:22.98#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:22.98#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:38:22.98#ibcon#first serial, iclass 14, count 0 2006.280.07:38:22.98#ibcon#enter sib2, iclass 14, count 0 2006.280.07:38:22.98#ibcon#flushed, iclass 14, count 0 2006.280.07:38:22.98#ibcon#about to write, iclass 14, count 0 2006.280.07:38:22.98#ibcon#wrote, iclass 14, count 0 2006.280.07:38:22.98#ibcon#about to read 3, iclass 14, count 0 2006.280.07:38:23.00#ibcon#read 3, iclass 14, count 0 2006.280.07:38:23.00#ibcon#about to read 4, iclass 14, count 0 2006.280.07:38:23.00#ibcon#read 4, iclass 14, count 0 2006.280.07:38:23.00#ibcon#about to read 5, iclass 14, count 0 2006.280.07:38:23.00#ibcon#read 5, iclass 14, count 0 2006.280.07:38:23.00#ibcon#about to read 6, iclass 14, count 0 2006.280.07:38:23.00#ibcon#read 6, iclass 14, count 0 2006.280.07:38:23.00#ibcon#end of sib2, iclass 14, count 0 2006.280.07:38:23.00#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:38:23.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:38:23.00#ibcon#[27=USB\r\n] 2006.280.07:38:23.00#ibcon#*before write, iclass 14, count 0 2006.280.07:38:23.00#ibcon#enter sib2, iclass 14, count 0 2006.280.07:38:23.00#ibcon#flushed, iclass 14, count 0 2006.280.07:38:23.00#ibcon#about to write, iclass 14, count 0 2006.280.07:38:23.00#ibcon#wrote, iclass 14, count 0 2006.280.07:38:23.00#ibcon#about to read 3, iclass 14, count 0 2006.280.07:38:23.03#ibcon#read 3, iclass 14, count 0 2006.280.07:38:23.03#ibcon#about to read 4, iclass 14, count 0 2006.280.07:38:23.03#ibcon#read 4, iclass 14, count 0 2006.280.07:38:23.03#ibcon#about to read 5, iclass 14, count 0 2006.280.07:38:23.03#ibcon#read 5, iclass 14, count 0 2006.280.07:38:23.03#ibcon#about to read 6, iclass 14, count 0 2006.280.07:38:23.03#ibcon#read 6, iclass 14, count 0 2006.280.07:38:23.03#ibcon#end of sib2, iclass 14, count 0 2006.280.07:38:23.03#ibcon#*after write, iclass 14, count 0 2006.280.07:38:23.03#ibcon#*before return 0, iclass 14, count 0 2006.280.07:38:23.03#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:23.03#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:38:23.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:38:23.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:38:23.03$vc4f8/vabw=wide 2006.280.07:38:23.03#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:38:23.03#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:38:23.03#ibcon#ireg 8 cls_cnt 0 2006.280.07:38:23.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:23.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:23.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:23.03#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:38:23.03#ibcon#first serial, iclass 16, count 0 2006.280.07:38:23.03#ibcon#enter sib2, iclass 16, count 0 2006.280.07:38:23.03#ibcon#flushed, iclass 16, count 0 2006.280.07:38:23.03#ibcon#about to write, iclass 16, count 0 2006.280.07:38:23.03#ibcon#wrote, iclass 16, count 0 2006.280.07:38:23.03#ibcon#about to read 3, iclass 16, count 0 2006.280.07:38:23.05#ibcon#read 3, iclass 16, count 0 2006.280.07:38:23.05#ibcon#about to read 4, iclass 16, count 0 2006.280.07:38:23.05#ibcon#read 4, iclass 16, count 0 2006.280.07:38:23.05#ibcon#about to read 5, iclass 16, count 0 2006.280.07:38:23.05#ibcon#read 5, iclass 16, count 0 2006.280.07:38:23.05#ibcon#about to read 6, iclass 16, count 0 2006.280.07:38:23.05#ibcon#read 6, iclass 16, count 0 2006.280.07:38:23.05#ibcon#end of sib2, iclass 16, count 0 2006.280.07:38:23.05#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:38:23.05#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:38:23.05#ibcon#[25=BW32\r\n] 2006.280.07:38:23.05#ibcon#*before write, iclass 16, count 0 2006.280.07:38:23.05#ibcon#enter sib2, iclass 16, count 0 2006.280.07:38:23.05#ibcon#flushed, iclass 16, count 0 2006.280.07:38:23.05#ibcon#about to write, iclass 16, count 0 2006.280.07:38:23.05#ibcon#wrote, iclass 16, count 0 2006.280.07:38:23.05#ibcon#about to read 3, iclass 16, count 0 2006.280.07:38:23.08#ibcon#read 3, iclass 16, count 0 2006.280.07:38:23.08#ibcon#about to read 4, iclass 16, count 0 2006.280.07:38:23.08#ibcon#read 4, iclass 16, count 0 2006.280.07:38:23.08#ibcon#about to read 5, iclass 16, count 0 2006.280.07:38:23.08#ibcon#read 5, iclass 16, count 0 2006.280.07:38:23.08#ibcon#about to read 6, iclass 16, count 0 2006.280.07:38:23.08#ibcon#read 6, iclass 16, count 0 2006.280.07:38:23.08#ibcon#end of sib2, iclass 16, count 0 2006.280.07:38:23.08#ibcon#*after write, iclass 16, count 0 2006.280.07:38:23.08#ibcon#*before return 0, iclass 16, count 0 2006.280.07:38:23.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:23.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:38:23.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:38:23.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:38:23.08$vc4f8/vbbw=wide 2006.280.07:38:23.09#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:38:23.09#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:38:23.09#ibcon#ireg 8 cls_cnt 0 2006.280.07:38:23.09#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:38:23.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:38:23.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:38:23.15#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:38:23.15#ibcon#first serial, iclass 18, count 0 2006.280.07:38:23.15#ibcon#enter sib2, iclass 18, count 0 2006.280.07:38:23.15#ibcon#flushed, iclass 18, count 0 2006.280.07:38:23.15#ibcon#about to write, iclass 18, count 0 2006.280.07:38:23.15#ibcon#wrote, iclass 18, count 0 2006.280.07:38:23.15#ibcon#about to read 3, iclass 18, count 0 2006.280.07:38:23.17#ibcon#read 3, iclass 18, count 0 2006.280.07:38:23.17#ibcon#about to read 4, iclass 18, count 0 2006.280.07:38:23.17#ibcon#read 4, iclass 18, count 0 2006.280.07:38:23.17#ibcon#about to read 5, iclass 18, count 0 2006.280.07:38:23.17#ibcon#read 5, iclass 18, count 0 2006.280.07:38:23.17#ibcon#about to read 6, iclass 18, count 0 2006.280.07:38:23.17#ibcon#read 6, iclass 18, count 0 2006.280.07:38:23.17#ibcon#end of sib2, iclass 18, count 0 2006.280.07:38:23.17#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:38:23.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:38:23.17#ibcon#[27=BW32\r\n] 2006.280.07:38:23.17#ibcon#*before write, iclass 18, count 0 2006.280.07:38:23.17#ibcon#enter sib2, iclass 18, count 0 2006.280.07:38:23.17#ibcon#flushed, iclass 18, count 0 2006.280.07:38:23.17#ibcon#about to write, iclass 18, count 0 2006.280.07:38:23.17#ibcon#wrote, iclass 18, count 0 2006.280.07:38:23.17#ibcon#about to read 3, iclass 18, count 0 2006.280.07:38:23.20#ibcon#read 3, iclass 18, count 0 2006.280.07:38:23.20#ibcon#about to read 4, iclass 18, count 0 2006.280.07:38:23.20#ibcon#read 4, iclass 18, count 0 2006.280.07:38:23.20#ibcon#about to read 5, iclass 18, count 0 2006.280.07:38:23.20#ibcon#read 5, iclass 18, count 0 2006.280.07:38:23.20#ibcon#about to read 6, iclass 18, count 0 2006.280.07:38:23.20#ibcon#read 6, iclass 18, count 0 2006.280.07:38:23.20#ibcon#end of sib2, iclass 18, count 0 2006.280.07:38:23.20#ibcon#*after write, iclass 18, count 0 2006.280.07:38:23.20#ibcon#*before return 0, iclass 18, count 0 2006.280.07:38:23.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:38:23.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:38:23.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:38:23.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:38:23.20$4f8m12a/ifd4f 2006.280.07:38:23.20$ifd4f/lo= 2006.280.07:38:23.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:38:23.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:38:23.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:38:23.20$ifd4f/patch= 2006.280.07:38:23.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:38:23.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:38:23.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:38:23.20$4f8m12a/"form=m,16.000,1:2 2006.280.07:38:23.20$4f8m12a/"tpicd 2006.280.07:38:23.20$4f8m12a/echo=off 2006.280.07:38:23.20$4f8m12a/xlog=off 2006.280.07:38:23.20:!2006.280.07:38:50 2006.280.07:38:36.14#trakl#Source acquired 2006.280.07:38:38.14#flagr#flagr/antenna,acquired 2006.280.07:38:50.00:preob 2006.280.07:38:51.14/onsource/TRACKING 2006.280.07:38:51.14:!2006.280.07:39:00 2006.280.07:39:00.00:data_valid=on 2006.280.07:39:00.00:midob 2006.280.07:39:00.14/onsource/TRACKING 2006.280.07:39:00.14/wx/21.79,986.7,61 2006.280.07:39:00.27/cable/+6.4827E-03 2006.280.07:39:01.36/va/01,07,usb,yes,33,35 2006.280.07:39:01.36/va/02,06,usb,yes,30,32 2006.280.07:39:01.36/va/03,06,usb,yes,29,29 2006.280.07:39:01.36/va/04,06,usb,yes,32,34 2006.280.07:39:01.36/va/05,07,usb,yes,29,30 2006.280.07:39:01.36/va/06,06,usb,yes,28,28 2006.280.07:39:01.36/va/07,06,usb,yes,28,28 2006.280.07:39:01.36/va/08,06,usb,yes,30,30 2006.280.07:39:01.59/valo/01,532.99,yes,locked 2006.280.07:39:01.59/valo/02,572.99,yes,locked 2006.280.07:39:01.59/valo/03,672.99,yes,locked 2006.280.07:39:01.59/valo/04,832.99,yes,locked 2006.280.07:39:01.59/valo/05,652.99,yes,locked 2006.280.07:39:01.59/valo/06,772.99,yes,locked 2006.280.07:39:01.59/valo/07,832.99,yes,locked 2006.280.07:39:01.59/valo/08,852.99,yes,locked 2006.280.07:39:02.68/vb/01,04,usb,yes,30,29 2006.280.07:39:02.68/vb/02,05,usb,yes,28,30 2006.280.07:39:02.68/vb/03,04,usb,yes,29,32 2006.280.07:39:02.68/vb/04,04,usb,yes,29,29 2006.280.07:39:02.68/vb/05,04,usb,yes,27,32 2006.280.07:39:02.68/vb/06,04,usb,yes,28,31 2006.280.07:39:02.68/vb/07,04,usb,yes,31,31 2006.280.07:39:02.68/vb/08,04,usb,yes,28,32 2006.280.07:39:02.91/vblo/01,632.99,yes,locked 2006.280.07:39:02.91/vblo/02,640.99,yes,locked 2006.280.07:39:02.91/vblo/03,656.99,yes,locked 2006.280.07:39:02.91/vblo/04,712.99,yes,locked 2006.280.07:39:02.91/vblo/05,744.99,yes,locked 2006.280.07:39:02.91/vblo/06,752.99,yes,locked 2006.280.07:39:02.91/vblo/07,734.99,yes,locked 2006.280.07:39:02.91/vblo/08,744.99,yes,locked 2006.280.07:39:03.06/vabw/8 2006.280.07:39:03.21/vbbw/8 2006.280.07:39:03.30/xfe/off,on,12.2 2006.280.07:39:03.67/ifatt/23,28,28,28 2006.280.07:39:04.08/fmout-gps/S +2.98E-07 2006.280.07:39:04.10:!2006.280.07:40:00 2006.280.07:40:00.02:data_valid=off 2006.280.07:40:00.02:postob 2006.280.07:40:00.15/cable/+6.4827E-03 2006.280.07:40:00.15/wx/21.73,986.7,59 2006.280.07:40:01.07/fmout-gps/S +2.99E-07 2006.280.07:40:01.08:scan_name=280-0740,k06280,60 2006.280.07:40:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.280.07:40:01.15#flagr#flagr/antenna,new-source 2006.280.07:40:02.15:checkk5 2006.280.07:40:02.59/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:40:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:40:03.35/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:40:03.79/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:40:04.16/chk_obsdata//k5ts1/T2800739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:40:04.60/chk_obsdata//k5ts2/T2800739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:40:04.98/chk_obsdata//k5ts3/T2800739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:40:05.46/chk_obsdata//k5ts4/T2800739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:40:06.16/k5log//k5ts1_log_newline 2006.280.07:40:06.94/k5log//k5ts2_log_newline 2006.280.07:40:07.70/k5log//k5ts3_log_newline 2006.280.07:40:08.39/k5log//k5ts4_log_newline 2006.280.07:40:08.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:40:08.42:4f8m12a=1 2006.280.07:40:08.42$4f8m12a/echo=on 2006.280.07:40:08.42$4f8m12a/pcalon 2006.280.07:40:08.42$pcalon/"no phase cal control is implemented here 2006.280.07:40:08.42$4f8m12a/"tpicd=stop 2006.280.07:40:08.42$4f8m12a/vc4f8 2006.280.07:40:08.42$vc4f8/valo=1,532.99 2006.280.07:40:08.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:40:08.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:40:08.42#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:08.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:08.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:08.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:08.42#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:40:08.42#ibcon#first serial, iclass 29, count 0 2006.280.07:40:08.42#ibcon#enter sib2, iclass 29, count 0 2006.280.07:40:08.42#ibcon#flushed, iclass 29, count 0 2006.280.07:40:08.42#ibcon#about to write, iclass 29, count 0 2006.280.07:40:08.42#ibcon#wrote, iclass 29, count 0 2006.280.07:40:08.42#ibcon#about to read 3, iclass 29, count 0 2006.280.07:40:08.43#ibcon#read 3, iclass 29, count 0 2006.280.07:40:08.43#ibcon#about to read 4, iclass 29, count 0 2006.280.07:40:08.43#ibcon#read 4, iclass 29, count 0 2006.280.07:40:08.43#ibcon#about to read 5, iclass 29, count 0 2006.280.07:40:08.43#ibcon#read 5, iclass 29, count 0 2006.280.07:40:08.43#ibcon#about to read 6, iclass 29, count 0 2006.280.07:40:08.43#ibcon#read 6, iclass 29, count 0 2006.280.07:40:08.43#ibcon#end of sib2, iclass 29, count 0 2006.280.07:40:08.43#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:40:08.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:40:08.43#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:40:08.43#ibcon#*before write, iclass 29, count 0 2006.280.07:40:08.44#ibcon#enter sib2, iclass 29, count 0 2006.280.07:40:08.44#ibcon#flushed, iclass 29, count 0 2006.280.07:40:08.44#ibcon#about to write, iclass 29, count 0 2006.280.07:40:08.44#ibcon#wrote, iclass 29, count 0 2006.280.07:40:08.44#ibcon#about to read 3, iclass 29, count 0 2006.280.07:40:08.48#ibcon#read 3, iclass 29, count 0 2006.280.07:40:08.48#ibcon#about to read 4, iclass 29, count 0 2006.280.07:40:08.48#ibcon#read 4, iclass 29, count 0 2006.280.07:40:08.48#ibcon#about to read 5, iclass 29, count 0 2006.280.07:40:08.48#ibcon#read 5, iclass 29, count 0 2006.280.07:40:08.48#ibcon#about to read 6, iclass 29, count 0 2006.280.07:40:08.48#ibcon#read 6, iclass 29, count 0 2006.280.07:40:08.48#ibcon#end of sib2, iclass 29, count 0 2006.280.07:40:08.48#ibcon#*after write, iclass 29, count 0 2006.280.07:40:08.48#ibcon#*before return 0, iclass 29, count 0 2006.280.07:40:08.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:08.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:08.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:40:08.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:40:08.49$vc4f8/va=1,7 2006.280.07:40:08.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:40:08.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:40:08.49#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:08.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:08.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:08.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:08.49#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:40:08.49#ibcon#first serial, iclass 31, count 2 2006.280.07:40:08.49#ibcon#enter sib2, iclass 31, count 2 2006.280.07:40:08.49#ibcon#flushed, iclass 31, count 2 2006.280.07:40:08.49#ibcon#about to write, iclass 31, count 2 2006.280.07:40:08.49#ibcon#wrote, iclass 31, count 2 2006.280.07:40:08.49#ibcon#about to read 3, iclass 31, count 2 2006.280.07:40:08.50#ibcon#read 3, iclass 31, count 2 2006.280.07:40:08.50#ibcon#about to read 4, iclass 31, count 2 2006.280.07:40:08.50#ibcon#read 4, iclass 31, count 2 2006.280.07:40:08.50#ibcon#about to read 5, iclass 31, count 2 2006.280.07:40:08.50#ibcon#read 5, iclass 31, count 2 2006.280.07:40:08.50#ibcon#about to read 6, iclass 31, count 2 2006.280.07:40:08.50#ibcon#read 6, iclass 31, count 2 2006.280.07:40:08.50#ibcon#end of sib2, iclass 31, count 2 2006.280.07:40:08.51#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:40:08.51#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:40:08.51#ibcon#[25=AT01-07\r\n] 2006.280.07:40:08.51#ibcon#*before write, iclass 31, count 2 2006.280.07:40:08.51#ibcon#enter sib2, iclass 31, count 2 2006.280.07:40:08.51#ibcon#flushed, iclass 31, count 2 2006.280.07:40:08.51#ibcon#about to write, iclass 31, count 2 2006.280.07:40:08.51#ibcon#wrote, iclass 31, count 2 2006.280.07:40:08.51#ibcon#about to read 3, iclass 31, count 2 2006.280.07:40:08.53#ibcon#read 3, iclass 31, count 2 2006.280.07:40:08.53#ibcon#about to read 4, iclass 31, count 2 2006.280.07:40:08.53#ibcon#read 4, iclass 31, count 2 2006.280.07:40:08.53#ibcon#about to read 5, iclass 31, count 2 2006.280.07:40:08.53#ibcon#read 5, iclass 31, count 2 2006.280.07:40:08.53#ibcon#about to read 6, iclass 31, count 2 2006.280.07:40:08.53#ibcon#read 6, iclass 31, count 2 2006.280.07:40:08.53#ibcon#end of sib2, iclass 31, count 2 2006.280.07:40:08.53#ibcon#*after write, iclass 31, count 2 2006.280.07:40:08.54#ibcon#*before return 0, iclass 31, count 2 2006.280.07:40:08.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:08.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:08.54#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:40:08.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:08.54#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:08.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:08.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:08.65#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:40:08.65#ibcon#first serial, iclass 31, count 0 2006.280.07:40:08.65#ibcon#enter sib2, iclass 31, count 0 2006.280.07:40:08.65#ibcon#flushed, iclass 31, count 0 2006.280.07:40:08.65#ibcon#about to write, iclass 31, count 0 2006.280.07:40:08.65#ibcon#wrote, iclass 31, count 0 2006.280.07:40:08.65#ibcon#about to read 3, iclass 31, count 0 2006.280.07:40:08.67#ibcon#read 3, iclass 31, count 0 2006.280.07:40:08.67#ibcon#about to read 4, iclass 31, count 0 2006.280.07:40:08.67#ibcon#read 4, iclass 31, count 0 2006.280.07:40:08.67#ibcon#about to read 5, iclass 31, count 0 2006.280.07:40:08.67#ibcon#read 5, iclass 31, count 0 2006.280.07:40:08.67#ibcon#about to read 6, iclass 31, count 0 2006.280.07:40:08.67#ibcon#read 6, iclass 31, count 0 2006.280.07:40:08.67#ibcon#end of sib2, iclass 31, count 0 2006.280.07:40:08.67#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:40:08.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:40:08.68#ibcon#[25=USB\r\n] 2006.280.07:40:08.68#ibcon#*before write, iclass 31, count 0 2006.280.07:40:08.68#ibcon#enter sib2, iclass 31, count 0 2006.280.07:40:08.68#ibcon#flushed, iclass 31, count 0 2006.280.07:40:08.68#ibcon#about to write, iclass 31, count 0 2006.280.07:40:08.68#ibcon#wrote, iclass 31, count 0 2006.280.07:40:08.68#ibcon#about to read 3, iclass 31, count 0 2006.280.07:40:08.70#ibcon#read 3, iclass 31, count 0 2006.280.07:40:08.70#ibcon#about to read 4, iclass 31, count 0 2006.280.07:40:08.70#ibcon#read 4, iclass 31, count 0 2006.280.07:40:08.70#ibcon#about to read 5, iclass 31, count 0 2006.280.07:40:08.70#ibcon#read 5, iclass 31, count 0 2006.280.07:40:08.70#ibcon#about to read 6, iclass 31, count 0 2006.280.07:40:08.70#ibcon#read 6, iclass 31, count 0 2006.280.07:40:08.70#ibcon#end of sib2, iclass 31, count 0 2006.280.07:40:08.70#ibcon#*after write, iclass 31, count 0 2006.280.07:40:08.70#ibcon#*before return 0, iclass 31, count 0 2006.280.07:40:08.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:08.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:08.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:40:08.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:40:08.71$vc4f8/valo=2,572.99 2006.280.07:40:08.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:40:08.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:40:08.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:08.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:08.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:08.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:08.71#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:40:08.71#ibcon#first serial, iclass 33, count 0 2006.280.07:40:08.71#ibcon#enter sib2, iclass 33, count 0 2006.280.07:40:08.71#ibcon#flushed, iclass 33, count 0 2006.280.07:40:08.71#ibcon#about to write, iclass 33, count 0 2006.280.07:40:08.71#ibcon#wrote, iclass 33, count 0 2006.280.07:40:08.71#ibcon#about to read 3, iclass 33, count 0 2006.280.07:40:08.72#ibcon#read 3, iclass 33, count 0 2006.280.07:40:08.73#ibcon#about to read 4, iclass 33, count 0 2006.280.07:40:08.73#ibcon#read 4, iclass 33, count 0 2006.280.07:40:08.73#ibcon#about to read 5, iclass 33, count 0 2006.280.07:40:08.73#ibcon#read 5, iclass 33, count 0 2006.280.07:40:08.73#ibcon#about to read 6, iclass 33, count 0 2006.280.07:40:08.73#ibcon#read 6, iclass 33, count 0 2006.280.07:40:08.73#ibcon#end of sib2, iclass 33, count 0 2006.280.07:40:08.73#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:40:08.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:40:08.73#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:40:08.73#ibcon#*before write, iclass 33, count 0 2006.280.07:40:08.73#ibcon#enter sib2, iclass 33, count 0 2006.280.07:40:08.73#ibcon#flushed, iclass 33, count 0 2006.280.07:40:08.73#ibcon#about to write, iclass 33, count 0 2006.280.07:40:08.73#ibcon#wrote, iclass 33, count 0 2006.280.07:40:08.73#ibcon#about to read 3, iclass 33, count 0 2006.280.07:40:08.76#ibcon#read 3, iclass 33, count 0 2006.280.07:40:08.76#ibcon#about to read 4, iclass 33, count 0 2006.280.07:40:08.76#ibcon#read 4, iclass 33, count 0 2006.280.07:40:08.76#ibcon#about to read 5, iclass 33, count 0 2006.280.07:40:08.76#ibcon#read 5, iclass 33, count 0 2006.280.07:40:08.76#ibcon#about to read 6, iclass 33, count 0 2006.280.07:40:08.76#ibcon#read 6, iclass 33, count 0 2006.280.07:40:08.76#ibcon#end of sib2, iclass 33, count 0 2006.280.07:40:08.76#ibcon#*after write, iclass 33, count 0 2006.280.07:40:08.76#ibcon#*before return 0, iclass 33, count 0 2006.280.07:40:08.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:08.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:08.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:40:08.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:40:08.77$vc4f8/va=2,6 2006.280.07:40:08.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:40:08.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:40:08.77#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:08.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:08.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:08.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:08.83#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:40:08.83#ibcon#first serial, iclass 35, count 2 2006.280.07:40:08.83#ibcon#enter sib2, iclass 35, count 2 2006.280.07:40:08.83#ibcon#flushed, iclass 35, count 2 2006.280.07:40:08.83#ibcon#about to write, iclass 35, count 2 2006.280.07:40:08.83#ibcon#wrote, iclass 35, count 2 2006.280.07:40:08.83#ibcon#about to read 3, iclass 35, count 2 2006.280.07:40:08.84#ibcon#read 3, iclass 35, count 2 2006.280.07:40:08.84#ibcon#about to read 4, iclass 35, count 2 2006.280.07:40:08.84#ibcon#read 4, iclass 35, count 2 2006.280.07:40:08.84#ibcon#about to read 5, iclass 35, count 2 2006.280.07:40:08.84#ibcon#read 5, iclass 35, count 2 2006.280.07:40:08.85#ibcon#about to read 6, iclass 35, count 2 2006.280.07:40:08.85#ibcon#read 6, iclass 35, count 2 2006.280.07:40:08.85#ibcon#end of sib2, iclass 35, count 2 2006.280.07:40:08.85#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:40:08.85#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:40:08.85#ibcon#[25=AT02-06\r\n] 2006.280.07:40:08.85#ibcon#*before write, iclass 35, count 2 2006.280.07:40:08.85#ibcon#enter sib2, iclass 35, count 2 2006.280.07:40:08.85#ibcon#flushed, iclass 35, count 2 2006.280.07:40:08.85#ibcon#about to write, iclass 35, count 2 2006.280.07:40:08.85#ibcon#wrote, iclass 35, count 2 2006.280.07:40:08.85#ibcon#about to read 3, iclass 35, count 2 2006.280.07:40:08.87#ibcon#read 3, iclass 35, count 2 2006.280.07:40:08.87#ibcon#about to read 4, iclass 35, count 2 2006.280.07:40:08.87#ibcon#read 4, iclass 35, count 2 2006.280.07:40:08.87#ibcon#about to read 5, iclass 35, count 2 2006.280.07:40:08.87#ibcon#read 5, iclass 35, count 2 2006.280.07:40:08.87#ibcon#about to read 6, iclass 35, count 2 2006.280.07:40:08.87#ibcon#read 6, iclass 35, count 2 2006.280.07:40:08.87#ibcon#end of sib2, iclass 35, count 2 2006.280.07:40:08.87#ibcon#*after write, iclass 35, count 2 2006.280.07:40:08.87#ibcon#*before return 0, iclass 35, count 2 2006.280.07:40:08.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:08.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:08.88#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:40:08.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:08.88#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:09.00#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:09.00#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:09.00#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:40:09.00#ibcon#first serial, iclass 35, count 0 2006.280.07:40:09.00#ibcon#enter sib2, iclass 35, count 0 2006.280.07:40:09.00#ibcon#flushed, iclass 35, count 0 2006.280.07:40:09.00#ibcon#about to write, iclass 35, count 0 2006.280.07:40:09.00#ibcon#wrote, iclass 35, count 0 2006.280.07:40:09.00#ibcon#about to read 3, iclass 35, count 0 2006.280.07:40:09.01#ibcon#read 3, iclass 35, count 0 2006.280.07:40:09.01#ibcon#about to read 4, iclass 35, count 0 2006.280.07:40:09.01#ibcon#read 4, iclass 35, count 0 2006.280.07:40:09.01#ibcon#about to read 5, iclass 35, count 0 2006.280.07:40:09.01#ibcon#read 5, iclass 35, count 0 2006.280.07:40:09.01#ibcon#about to read 6, iclass 35, count 0 2006.280.07:40:09.01#ibcon#read 6, iclass 35, count 0 2006.280.07:40:09.01#ibcon#end of sib2, iclass 35, count 0 2006.280.07:40:09.01#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:40:09.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:40:09.01#ibcon#[25=USB\r\n] 2006.280.07:40:09.01#ibcon#*before write, iclass 35, count 0 2006.280.07:40:09.01#ibcon#enter sib2, iclass 35, count 0 2006.280.07:40:09.02#ibcon#flushed, iclass 35, count 0 2006.280.07:40:09.02#ibcon#about to write, iclass 35, count 0 2006.280.07:40:09.02#ibcon#wrote, iclass 35, count 0 2006.280.07:40:09.02#ibcon#about to read 3, iclass 35, count 0 2006.280.07:40:09.04#ibcon#read 3, iclass 35, count 0 2006.280.07:40:09.04#ibcon#about to read 4, iclass 35, count 0 2006.280.07:40:09.04#ibcon#read 4, iclass 35, count 0 2006.280.07:40:09.04#ibcon#about to read 5, iclass 35, count 0 2006.280.07:40:09.04#ibcon#read 5, iclass 35, count 0 2006.280.07:40:09.05#ibcon#about to read 6, iclass 35, count 0 2006.280.07:40:09.05#ibcon#read 6, iclass 35, count 0 2006.280.07:40:09.05#ibcon#end of sib2, iclass 35, count 0 2006.280.07:40:09.05#ibcon#*after write, iclass 35, count 0 2006.280.07:40:09.05#ibcon#*before return 0, iclass 35, count 0 2006.280.07:40:09.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:09.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:09.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:40:09.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:40:09.05$vc4f8/valo=3,672.99 2006.280.07:40:09.05#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:40:09.05#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:40:09.05#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:09.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:09.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:09.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:09.05#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:40:09.05#ibcon#first serial, iclass 37, count 0 2006.280.07:40:09.05#ibcon#enter sib2, iclass 37, count 0 2006.280.07:40:09.05#ibcon#flushed, iclass 37, count 0 2006.280.07:40:09.05#ibcon#about to write, iclass 37, count 0 2006.280.07:40:09.05#ibcon#wrote, iclass 37, count 0 2006.280.07:40:09.05#ibcon#about to read 3, iclass 37, count 0 2006.280.07:40:09.06#ibcon#read 3, iclass 37, count 0 2006.280.07:40:09.06#ibcon#about to read 4, iclass 37, count 0 2006.280.07:40:09.06#ibcon#read 4, iclass 37, count 0 2006.280.07:40:09.06#ibcon#about to read 5, iclass 37, count 0 2006.280.07:40:09.06#ibcon#read 5, iclass 37, count 0 2006.280.07:40:09.06#ibcon#about to read 6, iclass 37, count 0 2006.280.07:40:09.06#ibcon#read 6, iclass 37, count 0 2006.280.07:40:09.06#ibcon#end of sib2, iclass 37, count 0 2006.280.07:40:09.06#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:40:09.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:40:09.06#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:40:09.07#ibcon#*before write, iclass 37, count 0 2006.280.07:40:09.07#ibcon#enter sib2, iclass 37, count 0 2006.280.07:40:09.07#ibcon#flushed, iclass 37, count 0 2006.280.07:40:09.07#ibcon#about to write, iclass 37, count 0 2006.280.07:40:09.07#ibcon#wrote, iclass 37, count 0 2006.280.07:40:09.07#ibcon#about to read 3, iclass 37, count 0 2006.280.07:40:09.11#ibcon#read 3, iclass 37, count 0 2006.280.07:40:09.11#ibcon#about to read 4, iclass 37, count 0 2006.280.07:40:09.11#ibcon#read 4, iclass 37, count 0 2006.280.07:40:09.11#ibcon#about to read 5, iclass 37, count 0 2006.280.07:40:09.11#ibcon#read 5, iclass 37, count 0 2006.280.07:40:09.11#ibcon#about to read 6, iclass 37, count 0 2006.280.07:40:09.11#ibcon#read 6, iclass 37, count 0 2006.280.07:40:09.11#ibcon#end of sib2, iclass 37, count 0 2006.280.07:40:09.11#ibcon#*after write, iclass 37, count 0 2006.280.07:40:09.11#ibcon#*before return 0, iclass 37, count 0 2006.280.07:40:09.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:09.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:09.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:40:09.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:40:09.11$vc4f8/va=3,6 2006.280.07:40:09.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:40:09.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:40:09.11#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:09.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:09.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:09.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:09.16#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:40:09.16#ibcon#first serial, iclass 39, count 2 2006.280.07:40:09.16#ibcon#enter sib2, iclass 39, count 2 2006.280.07:40:09.16#ibcon#flushed, iclass 39, count 2 2006.280.07:40:09.16#ibcon#about to write, iclass 39, count 2 2006.280.07:40:09.16#ibcon#wrote, iclass 39, count 2 2006.280.07:40:09.16#ibcon#about to read 3, iclass 39, count 2 2006.280.07:40:09.18#ibcon#read 3, iclass 39, count 2 2006.280.07:40:09.18#ibcon#about to read 4, iclass 39, count 2 2006.280.07:40:09.18#ibcon#read 4, iclass 39, count 2 2006.280.07:40:09.18#ibcon#about to read 5, iclass 39, count 2 2006.280.07:40:09.18#ibcon#read 5, iclass 39, count 2 2006.280.07:40:09.18#ibcon#about to read 6, iclass 39, count 2 2006.280.07:40:09.18#ibcon#read 6, iclass 39, count 2 2006.280.07:40:09.18#ibcon#end of sib2, iclass 39, count 2 2006.280.07:40:09.18#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:40:09.18#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:40:09.18#ibcon#[25=AT03-06\r\n] 2006.280.07:40:09.19#ibcon#*before write, iclass 39, count 2 2006.280.07:40:09.19#ibcon#enter sib2, iclass 39, count 2 2006.280.07:40:09.19#ibcon#flushed, iclass 39, count 2 2006.280.07:40:09.19#ibcon#about to write, iclass 39, count 2 2006.280.07:40:09.19#ibcon#wrote, iclass 39, count 2 2006.280.07:40:09.19#ibcon#about to read 3, iclass 39, count 2 2006.280.07:40:09.22#ibcon#read 3, iclass 39, count 2 2006.280.07:40:09.22#ibcon#about to read 4, iclass 39, count 2 2006.280.07:40:09.22#ibcon#read 4, iclass 39, count 2 2006.280.07:40:09.22#ibcon#about to read 5, iclass 39, count 2 2006.280.07:40:09.22#ibcon#read 5, iclass 39, count 2 2006.280.07:40:09.22#ibcon#about to read 6, iclass 39, count 2 2006.280.07:40:09.22#ibcon#read 6, iclass 39, count 2 2006.280.07:40:09.22#ibcon#end of sib2, iclass 39, count 2 2006.280.07:40:09.22#ibcon#*after write, iclass 39, count 2 2006.280.07:40:09.22#ibcon#*before return 0, iclass 39, count 2 2006.280.07:40:09.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:09.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:09.22#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:40:09.22#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:09.22#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:09.34#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:09.34#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:09.34#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:40:09.34#ibcon#first serial, iclass 39, count 0 2006.280.07:40:09.34#ibcon#enter sib2, iclass 39, count 0 2006.280.07:40:09.34#ibcon#flushed, iclass 39, count 0 2006.280.07:40:09.34#ibcon#about to write, iclass 39, count 0 2006.280.07:40:09.34#ibcon#wrote, iclass 39, count 0 2006.280.07:40:09.34#ibcon#about to read 3, iclass 39, count 0 2006.280.07:40:09.35#ibcon#read 3, iclass 39, count 0 2006.280.07:40:09.35#ibcon#about to read 4, iclass 39, count 0 2006.280.07:40:09.35#ibcon#read 4, iclass 39, count 0 2006.280.07:40:09.35#ibcon#about to read 5, iclass 39, count 0 2006.280.07:40:09.35#ibcon#read 5, iclass 39, count 0 2006.280.07:40:09.35#ibcon#about to read 6, iclass 39, count 0 2006.280.07:40:09.35#ibcon#read 6, iclass 39, count 0 2006.280.07:40:09.35#ibcon#end of sib2, iclass 39, count 0 2006.280.07:40:09.35#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:40:09.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:40:09.35#ibcon#[25=USB\r\n] 2006.280.07:40:09.35#ibcon#*before write, iclass 39, count 0 2006.280.07:40:09.36#ibcon#enter sib2, iclass 39, count 0 2006.280.07:40:09.36#ibcon#flushed, iclass 39, count 0 2006.280.07:40:09.36#ibcon#about to write, iclass 39, count 0 2006.280.07:40:09.36#ibcon#wrote, iclass 39, count 0 2006.280.07:40:09.36#ibcon#about to read 3, iclass 39, count 0 2006.280.07:40:09.38#ibcon#read 3, iclass 39, count 0 2006.280.07:40:09.38#ibcon#about to read 4, iclass 39, count 0 2006.280.07:40:09.38#ibcon#read 4, iclass 39, count 0 2006.280.07:40:09.38#ibcon#about to read 5, iclass 39, count 0 2006.280.07:40:09.38#ibcon#read 5, iclass 39, count 0 2006.280.07:40:09.38#ibcon#about to read 6, iclass 39, count 0 2006.280.07:40:09.38#ibcon#read 6, iclass 39, count 0 2006.280.07:40:09.38#ibcon#end of sib2, iclass 39, count 0 2006.280.07:40:09.38#ibcon#*after write, iclass 39, count 0 2006.280.07:40:09.38#ibcon#*before return 0, iclass 39, count 0 2006.280.07:40:09.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:09.39#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:09.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:40:09.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:40:09.39$vc4f8/valo=4,832.99 2006.280.07:40:09.39#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:40:09.39#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:40:09.39#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:09.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:09.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:09.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:09.39#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:40:09.39#ibcon#first serial, iclass 3, count 0 2006.280.07:40:09.39#ibcon#enter sib2, iclass 3, count 0 2006.280.07:40:09.39#ibcon#flushed, iclass 3, count 0 2006.280.07:40:09.39#ibcon#about to write, iclass 3, count 0 2006.280.07:40:09.39#ibcon#wrote, iclass 3, count 0 2006.280.07:40:09.39#ibcon#about to read 3, iclass 3, count 0 2006.280.07:40:09.40#ibcon#read 3, iclass 3, count 0 2006.280.07:40:09.40#ibcon#about to read 4, iclass 3, count 0 2006.280.07:40:09.40#ibcon#read 4, iclass 3, count 0 2006.280.07:40:09.40#ibcon#about to read 5, iclass 3, count 0 2006.280.07:40:09.40#ibcon#read 5, iclass 3, count 0 2006.280.07:40:09.40#ibcon#about to read 6, iclass 3, count 0 2006.280.07:40:09.40#ibcon#read 6, iclass 3, count 0 2006.280.07:40:09.40#ibcon#end of sib2, iclass 3, count 0 2006.280.07:40:09.40#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:40:09.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:40:09.40#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:40:09.41#ibcon#*before write, iclass 3, count 0 2006.280.07:40:09.41#ibcon#enter sib2, iclass 3, count 0 2006.280.07:40:09.41#ibcon#flushed, iclass 3, count 0 2006.280.07:40:09.41#ibcon#about to write, iclass 3, count 0 2006.280.07:40:09.41#ibcon#wrote, iclass 3, count 0 2006.280.07:40:09.41#ibcon#about to read 3, iclass 3, count 0 2006.280.07:40:09.44#ibcon#read 3, iclass 3, count 0 2006.280.07:40:09.44#ibcon#about to read 4, iclass 3, count 0 2006.280.07:40:09.44#ibcon#read 4, iclass 3, count 0 2006.280.07:40:09.44#ibcon#about to read 5, iclass 3, count 0 2006.280.07:40:09.44#ibcon#read 5, iclass 3, count 0 2006.280.07:40:09.44#ibcon#about to read 6, iclass 3, count 0 2006.280.07:40:09.44#ibcon#read 6, iclass 3, count 0 2006.280.07:40:09.44#ibcon#end of sib2, iclass 3, count 0 2006.280.07:40:09.44#ibcon#*after write, iclass 3, count 0 2006.280.07:40:09.44#ibcon#*before return 0, iclass 3, count 0 2006.280.07:40:09.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:09.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:09.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:40:09.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:40:09.45$vc4f8/va=4,6 2006.280.07:40:09.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:40:09.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:40:09.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:09.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:09.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:09.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:09.50#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:40:09.50#ibcon#first serial, iclass 5, count 2 2006.280.07:40:09.50#ibcon#enter sib2, iclass 5, count 2 2006.280.07:40:09.50#ibcon#flushed, iclass 5, count 2 2006.280.07:40:09.50#ibcon#about to write, iclass 5, count 2 2006.280.07:40:09.50#ibcon#wrote, iclass 5, count 2 2006.280.07:40:09.50#ibcon#about to read 3, iclass 5, count 2 2006.280.07:40:09.53#ibcon#read 3, iclass 5, count 2 2006.280.07:40:09.53#ibcon#about to read 4, iclass 5, count 2 2006.280.07:40:09.53#ibcon#read 4, iclass 5, count 2 2006.280.07:40:09.53#ibcon#about to read 5, iclass 5, count 2 2006.280.07:40:09.53#ibcon#read 5, iclass 5, count 2 2006.280.07:40:09.53#ibcon#about to read 6, iclass 5, count 2 2006.280.07:40:09.53#ibcon#read 6, iclass 5, count 2 2006.280.07:40:09.53#ibcon#end of sib2, iclass 5, count 2 2006.280.07:40:09.53#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:40:09.53#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:40:09.53#ibcon#[25=AT04-06\r\n] 2006.280.07:40:09.53#ibcon#*before write, iclass 5, count 2 2006.280.07:40:09.53#ibcon#enter sib2, iclass 5, count 2 2006.280.07:40:09.53#ibcon#flushed, iclass 5, count 2 2006.280.07:40:09.53#ibcon#about to write, iclass 5, count 2 2006.280.07:40:09.53#ibcon#wrote, iclass 5, count 2 2006.280.07:40:09.53#ibcon#about to read 3, iclass 5, count 2 2006.280.07:40:09.56#ibcon#read 3, iclass 5, count 2 2006.280.07:40:09.56#ibcon#about to read 4, iclass 5, count 2 2006.280.07:40:09.56#ibcon#read 4, iclass 5, count 2 2006.280.07:40:09.56#ibcon#about to read 5, iclass 5, count 2 2006.280.07:40:09.56#ibcon#read 5, iclass 5, count 2 2006.280.07:40:09.56#ibcon#about to read 6, iclass 5, count 2 2006.280.07:40:09.56#ibcon#read 6, iclass 5, count 2 2006.280.07:40:09.56#ibcon#end of sib2, iclass 5, count 2 2006.280.07:40:09.56#ibcon#*after write, iclass 5, count 2 2006.280.07:40:09.56#ibcon#*before return 0, iclass 5, count 2 2006.280.07:40:09.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:09.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:09.57#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:40:09.57#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:09.57#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:09.68#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:09.68#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:09.68#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:40:09.68#ibcon#first serial, iclass 5, count 0 2006.280.07:40:09.68#ibcon#enter sib2, iclass 5, count 0 2006.280.07:40:09.68#ibcon#flushed, iclass 5, count 0 2006.280.07:40:09.68#ibcon#about to write, iclass 5, count 0 2006.280.07:40:09.68#ibcon#wrote, iclass 5, count 0 2006.280.07:40:09.68#ibcon#about to read 3, iclass 5, count 0 2006.280.07:40:09.70#ibcon#read 3, iclass 5, count 0 2006.280.07:40:09.70#ibcon#about to read 4, iclass 5, count 0 2006.280.07:40:09.70#ibcon#read 4, iclass 5, count 0 2006.280.07:40:09.70#ibcon#about to read 5, iclass 5, count 0 2006.280.07:40:09.70#ibcon#read 5, iclass 5, count 0 2006.280.07:40:09.70#ibcon#about to read 6, iclass 5, count 0 2006.280.07:40:09.70#ibcon#read 6, iclass 5, count 0 2006.280.07:40:09.70#ibcon#end of sib2, iclass 5, count 0 2006.280.07:40:09.70#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:40:09.70#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:40:09.70#ibcon#[25=USB\r\n] 2006.280.07:40:09.71#ibcon#*before write, iclass 5, count 0 2006.280.07:40:09.71#ibcon#enter sib2, iclass 5, count 0 2006.280.07:40:09.71#ibcon#flushed, iclass 5, count 0 2006.280.07:40:09.71#ibcon#about to write, iclass 5, count 0 2006.280.07:40:09.71#ibcon#wrote, iclass 5, count 0 2006.280.07:40:09.71#ibcon#about to read 3, iclass 5, count 0 2006.280.07:40:09.74#ibcon#read 3, iclass 5, count 0 2006.280.07:40:09.74#ibcon#about to read 4, iclass 5, count 0 2006.280.07:40:09.74#ibcon#read 4, iclass 5, count 0 2006.280.07:40:09.74#ibcon#about to read 5, iclass 5, count 0 2006.280.07:40:09.74#ibcon#read 5, iclass 5, count 0 2006.280.07:40:09.74#ibcon#about to read 6, iclass 5, count 0 2006.280.07:40:09.74#ibcon#read 6, iclass 5, count 0 2006.280.07:40:09.74#ibcon#end of sib2, iclass 5, count 0 2006.280.07:40:09.74#ibcon#*after write, iclass 5, count 0 2006.280.07:40:09.74#ibcon#*before return 0, iclass 5, count 0 2006.280.07:40:09.74#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:09.74#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:09.74#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:40:09.74#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:40:09.74$vc4f8/valo=5,652.99 2006.280.07:40:09.74#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:40:09.74#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:40:09.74#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:09.74#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:09.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:09.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:09.74#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:40:09.74#ibcon#first serial, iclass 7, count 0 2006.280.07:40:09.74#ibcon#enter sib2, iclass 7, count 0 2006.280.07:40:09.74#ibcon#flushed, iclass 7, count 0 2006.280.07:40:09.74#ibcon#about to write, iclass 7, count 0 2006.280.07:40:09.74#ibcon#wrote, iclass 7, count 0 2006.280.07:40:09.74#ibcon#about to read 3, iclass 7, count 0 2006.280.07:40:09.76#ibcon#read 3, iclass 7, count 0 2006.280.07:40:09.76#ibcon#about to read 4, iclass 7, count 0 2006.280.07:40:09.76#ibcon#read 4, iclass 7, count 0 2006.280.07:40:09.76#ibcon#about to read 5, iclass 7, count 0 2006.280.07:40:09.76#ibcon#read 5, iclass 7, count 0 2006.280.07:40:09.76#ibcon#about to read 6, iclass 7, count 0 2006.280.07:40:09.76#ibcon#read 6, iclass 7, count 0 2006.280.07:40:09.76#ibcon#end of sib2, iclass 7, count 0 2006.280.07:40:09.76#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:40:09.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:40:09.76#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:40:09.76#ibcon#*before write, iclass 7, count 0 2006.280.07:40:09.76#ibcon#enter sib2, iclass 7, count 0 2006.280.07:40:09.76#ibcon#flushed, iclass 7, count 0 2006.280.07:40:09.76#ibcon#about to write, iclass 7, count 0 2006.280.07:40:09.76#ibcon#wrote, iclass 7, count 0 2006.280.07:40:09.76#ibcon#about to read 3, iclass 7, count 0 2006.280.07:40:09.79#ibcon#read 3, iclass 7, count 0 2006.280.07:40:09.79#ibcon#about to read 4, iclass 7, count 0 2006.280.07:40:09.79#ibcon#read 4, iclass 7, count 0 2006.280.07:40:09.79#ibcon#about to read 5, iclass 7, count 0 2006.280.07:40:09.79#ibcon#read 5, iclass 7, count 0 2006.280.07:40:09.79#ibcon#about to read 6, iclass 7, count 0 2006.280.07:40:09.79#ibcon#read 6, iclass 7, count 0 2006.280.07:40:09.79#ibcon#end of sib2, iclass 7, count 0 2006.280.07:40:09.79#ibcon#*after write, iclass 7, count 0 2006.280.07:40:09.79#ibcon#*before return 0, iclass 7, count 0 2006.280.07:40:09.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:09.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:09.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:40:09.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:40:09.80$vc4f8/va=5,7 2006.280.07:40:09.81#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:40:09.81#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:40:09.81#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:09.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:09.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:09.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:09.85#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:40:09.85#ibcon#first serial, iclass 11, count 2 2006.280.07:40:09.85#ibcon#enter sib2, iclass 11, count 2 2006.280.07:40:09.85#ibcon#flushed, iclass 11, count 2 2006.280.07:40:09.86#ibcon#about to write, iclass 11, count 2 2006.280.07:40:09.86#ibcon#wrote, iclass 11, count 2 2006.280.07:40:09.86#ibcon#about to read 3, iclass 11, count 2 2006.280.07:40:09.87#ibcon#read 3, iclass 11, count 2 2006.280.07:40:09.87#ibcon#about to read 4, iclass 11, count 2 2006.280.07:40:09.87#ibcon#read 4, iclass 11, count 2 2006.280.07:40:09.87#ibcon#about to read 5, iclass 11, count 2 2006.280.07:40:09.87#ibcon#read 5, iclass 11, count 2 2006.280.07:40:09.87#ibcon#about to read 6, iclass 11, count 2 2006.280.07:40:09.87#ibcon#read 6, iclass 11, count 2 2006.280.07:40:09.87#ibcon#end of sib2, iclass 11, count 2 2006.280.07:40:09.87#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:40:09.88#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:40:09.88#ibcon#[25=AT05-07\r\n] 2006.280.07:40:09.88#ibcon#*before write, iclass 11, count 2 2006.280.07:40:09.88#ibcon#enter sib2, iclass 11, count 2 2006.280.07:40:09.88#ibcon#flushed, iclass 11, count 2 2006.280.07:40:09.88#ibcon#about to write, iclass 11, count 2 2006.280.07:40:09.88#ibcon#wrote, iclass 11, count 2 2006.280.07:40:09.88#ibcon#about to read 3, iclass 11, count 2 2006.280.07:40:09.90#ibcon#read 3, iclass 11, count 2 2006.280.07:40:09.90#ibcon#about to read 4, iclass 11, count 2 2006.280.07:40:09.90#ibcon#read 4, iclass 11, count 2 2006.280.07:40:09.90#ibcon#about to read 5, iclass 11, count 2 2006.280.07:40:09.90#ibcon#read 5, iclass 11, count 2 2006.280.07:40:09.91#ibcon#about to read 6, iclass 11, count 2 2006.280.07:40:09.91#ibcon#read 6, iclass 11, count 2 2006.280.07:40:09.91#ibcon#end of sib2, iclass 11, count 2 2006.280.07:40:09.91#ibcon#*after write, iclass 11, count 2 2006.280.07:40:09.91#ibcon#*before return 0, iclass 11, count 2 2006.280.07:40:09.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:09.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:09.91#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:40:09.91#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:09.91#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:10.02#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:10.02#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:10.02#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:40:10.02#ibcon#first serial, iclass 11, count 0 2006.280.07:40:10.02#ibcon#enter sib2, iclass 11, count 0 2006.280.07:40:10.02#ibcon#flushed, iclass 11, count 0 2006.280.07:40:10.02#ibcon#about to write, iclass 11, count 0 2006.280.07:40:10.02#ibcon#wrote, iclass 11, count 0 2006.280.07:40:10.02#ibcon#about to read 3, iclass 11, count 0 2006.280.07:40:10.04#ibcon#read 3, iclass 11, count 0 2006.280.07:40:10.04#ibcon#about to read 4, iclass 11, count 0 2006.280.07:40:10.04#ibcon#read 4, iclass 11, count 0 2006.280.07:40:10.04#ibcon#about to read 5, iclass 11, count 0 2006.280.07:40:10.04#ibcon#read 5, iclass 11, count 0 2006.280.07:40:10.04#ibcon#about to read 6, iclass 11, count 0 2006.280.07:40:10.04#ibcon#read 6, iclass 11, count 0 2006.280.07:40:10.04#ibcon#end of sib2, iclass 11, count 0 2006.280.07:40:10.04#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:40:10.04#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:40:10.05#ibcon#[25=USB\r\n] 2006.280.07:40:10.05#ibcon#*before write, iclass 11, count 0 2006.280.07:40:10.05#ibcon#enter sib2, iclass 11, count 0 2006.280.07:40:10.05#ibcon#flushed, iclass 11, count 0 2006.280.07:40:10.05#ibcon#about to write, iclass 11, count 0 2006.280.07:40:10.05#ibcon#wrote, iclass 11, count 0 2006.280.07:40:10.05#ibcon#about to read 3, iclass 11, count 0 2006.280.07:40:10.07#ibcon#read 3, iclass 11, count 0 2006.280.07:40:10.07#ibcon#about to read 4, iclass 11, count 0 2006.280.07:40:10.07#ibcon#read 4, iclass 11, count 0 2006.280.07:40:10.07#ibcon#about to read 5, iclass 11, count 0 2006.280.07:40:10.07#ibcon#read 5, iclass 11, count 0 2006.280.07:40:10.07#ibcon#about to read 6, iclass 11, count 0 2006.280.07:40:10.07#ibcon#read 6, iclass 11, count 0 2006.280.07:40:10.07#ibcon#end of sib2, iclass 11, count 0 2006.280.07:40:10.07#ibcon#*after write, iclass 11, count 0 2006.280.07:40:10.07#ibcon#*before return 0, iclass 11, count 0 2006.280.07:40:10.07#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:10.08#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:10.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:40:10.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:40:10.08$vc4f8/valo=6,772.99 2006.280.07:40:10.08#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:40:10.08#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:40:10.08#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:10.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:10.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:10.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:10.08#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:40:10.08#ibcon#first serial, iclass 13, count 0 2006.280.07:40:10.08#ibcon#enter sib2, iclass 13, count 0 2006.280.07:40:10.08#ibcon#flushed, iclass 13, count 0 2006.280.07:40:10.08#ibcon#about to write, iclass 13, count 0 2006.280.07:40:10.08#ibcon#wrote, iclass 13, count 0 2006.280.07:40:10.08#ibcon#about to read 3, iclass 13, count 0 2006.280.07:40:10.09#ibcon#read 3, iclass 13, count 0 2006.280.07:40:10.10#ibcon#about to read 4, iclass 13, count 0 2006.280.07:40:10.10#ibcon#read 4, iclass 13, count 0 2006.280.07:40:10.10#ibcon#about to read 5, iclass 13, count 0 2006.280.07:40:10.10#ibcon#read 5, iclass 13, count 0 2006.280.07:40:10.10#ibcon#about to read 6, iclass 13, count 0 2006.280.07:40:10.10#ibcon#read 6, iclass 13, count 0 2006.280.07:40:10.10#ibcon#end of sib2, iclass 13, count 0 2006.280.07:40:10.10#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:40:10.10#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:40:10.10#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:40:10.10#ibcon#*before write, iclass 13, count 0 2006.280.07:40:10.10#ibcon#enter sib2, iclass 13, count 0 2006.280.07:40:10.10#ibcon#flushed, iclass 13, count 0 2006.280.07:40:10.10#ibcon#about to write, iclass 13, count 0 2006.280.07:40:10.10#ibcon#wrote, iclass 13, count 0 2006.280.07:40:10.10#ibcon#about to read 3, iclass 13, count 0 2006.280.07:40:10.13#ibcon#read 3, iclass 13, count 0 2006.280.07:40:10.13#ibcon#about to read 4, iclass 13, count 0 2006.280.07:40:10.13#ibcon#read 4, iclass 13, count 0 2006.280.07:40:10.13#ibcon#about to read 5, iclass 13, count 0 2006.280.07:40:10.13#ibcon#read 5, iclass 13, count 0 2006.280.07:40:10.13#ibcon#about to read 6, iclass 13, count 0 2006.280.07:40:10.13#ibcon#read 6, iclass 13, count 0 2006.280.07:40:10.13#ibcon#end of sib2, iclass 13, count 0 2006.280.07:40:10.13#ibcon#*after write, iclass 13, count 0 2006.280.07:40:10.13#ibcon#*before return 0, iclass 13, count 0 2006.280.07:40:10.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:10.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:10.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:40:10.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:40:10.14$vc4f8/va=6,6 2006.280.07:40:10.14#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:40:10.14#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:40:10.14#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:10.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:10.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:10.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:10.19#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:40:10.19#ibcon#first serial, iclass 15, count 2 2006.280.07:40:10.19#ibcon#enter sib2, iclass 15, count 2 2006.280.07:40:10.19#ibcon#flushed, iclass 15, count 2 2006.280.07:40:10.19#ibcon#about to write, iclass 15, count 2 2006.280.07:40:10.19#ibcon#wrote, iclass 15, count 2 2006.280.07:40:10.19#ibcon#about to read 3, iclass 15, count 2 2006.280.07:40:10.20#ibcon#read 3, iclass 15, count 2 2006.280.07:40:10.20#ibcon#about to read 4, iclass 15, count 2 2006.280.07:40:10.20#ibcon#read 4, iclass 15, count 2 2006.280.07:40:10.20#ibcon#about to read 5, iclass 15, count 2 2006.280.07:40:10.20#ibcon#read 5, iclass 15, count 2 2006.280.07:40:10.20#ibcon#about to read 6, iclass 15, count 2 2006.280.07:40:10.20#ibcon#read 6, iclass 15, count 2 2006.280.07:40:10.20#ibcon#end of sib2, iclass 15, count 2 2006.280.07:40:10.20#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:40:10.20#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:40:10.20#ibcon#[25=AT06-06\r\n] 2006.280.07:40:10.20#ibcon#*before write, iclass 15, count 2 2006.280.07:40:10.21#ibcon#enter sib2, iclass 15, count 2 2006.280.07:40:10.21#ibcon#flushed, iclass 15, count 2 2006.280.07:40:10.21#ibcon#about to write, iclass 15, count 2 2006.280.07:40:10.21#ibcon#wrote, iclass 15, count 2 2006.280.07:40:10.21#ibcon#about to read 3, iclass 15, count 2 2006.280.07:40:10.23#ibcon#read 3, iclass 15, count 2 2006.280.07:40:10.23#ibcon#about to read 4, iclass 15, count 2 2006.280.07:40:10.23#ibcon#read 4, iclass 15, count 2 2006.280.07:40:10.23#ibcon#about to read 5, iclass 15, count 2 2006.280.07:40:10.23#ibcon#read 5, iclass 15, count 2 2006.280.07:40:10.23#ibcon#about to read 6, iclass 15, count 2 2006.280.07:40:10.23#ibcon#read 6, iclass 15, count 2 2006.280.07:40:10.23#ibcon#end of sib2, iclass 15, count 2 2006.280.07:40:10.23#ibcon#*after write, iclass 15, count 2 2006.280.07:40:10.23#ibcon#*before return 0, iclass 15, count 2 2006.280.07:40:10.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:10.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:10.24#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:40:10.24#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:10.24#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:40:10.36#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:40:10.36#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:40:10.36#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:40:10.36#ibcon#first serial, iclass 15, count 0 2006.280.07:40:10.36#ibcon#enter sib2, iclass 15, count 0 2006.280.07:40:10.36#ibcon#flushed, iclass 15, count 0 2006.280.07:40:10.36#ibcon#about to write, iclass 15, count 0 2006.280.07:40:10.36#ibcon#wrote, iclass 15, count 0 2006.280.07:40:10.36#ibcon#about to read 3, iclass 15, count 0 2006.280.07:40:10.37#ibcon#read 3, iclass 15, count 0 2006.280.07:40:10.37#ibcon#about to read 4, iclass 15, count 0 2006.280.07:40:10.37#ibcon#read 4, iclass 15, count 0 2006.280.07:40:10.37#ibcon#about to read 5, iclass 15, count 0 2006.280.07:40:10.37#ibcon#read 5, iclass 15, count 0 2006.280.07:40:10.37#ibcon#about to read 6, iclass 15, count 0 2006.280.07:40:10.37#ibcon#read 6, iclass 15, count 0 2006.280.07:40:10.37#ibcon#end of sib2, iclass 15, count 0 2006.280.07:40:10.37#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:40:10.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:40:10.37#ibcon#[25=USB\r\n] 2006.280.07:40:10.37#ibcon#*before write, iclass 15, count 0 2006.280.07:40:10.38#ibcon#enter sib2, iclass 15, count 0 2006.280.07:40:10.38#ibcon#flushed, iclass 15, count 0 2006.280.07:40:10.38#ibcon#about to write, iclass 15, count 0 2006.280.07:40:10.38#ibcon#wrote, iclass 15, count 0 2006.280.07:40:10.38#ibcon#about to read 3, iclass 15, count 0 2006.280.07:40:10.40#ibcon#read 3, iclass 15, count 0 2006.280.07:40:10.40#ibcon#about to read 4, iclass 15, count 0 2006.280.07:40:10.40#ibcon#read 4, iclass 15, count 0 2006.280.07:40:10.40#ibcon#about to read 5, iclass 15, count 0 2006.280.07:40:10.40#ibcon#read 5, iclass 15, count 0 2006.280.07:40:10.40#ibcon#about to read 6, iclass 15, count 0 2006.280.07:40:10.40#ibcon#read 6, iclass 15, count 0 2006.280.07:40:10.40#ibcon#end of sib2, iclass 15, count 0 2006.280.07:40:10.40#ibcon#*after write, iclass 15, count 0 2006.280.07:40:10.40#ibcon#*before return 0, iclass 15, count 0 2006.280.07:40:10.41#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:40:10.41#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:40:10.41#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:40:10.41#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:40:10.41$vc4f8/valo=7,832.99 2006.280.07:40:10.41#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:40:10.41#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:40:10.41#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:10.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:40:10.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:40:10.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:40:10.41#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:40:10.41#ibcon#first serial, iclass 17, count 0 2006.280.07:40:10.41#ibcon#enter sib2, iclass 17, count 0 2006.280.07:40:10.41#ibcon#flushed, iclass 17, count 0 2006.280.07:40:10.41#ibcon#about to write, iclass 17, count 0 2006.280.07:40:10.41#ibcon#wrote, iclass 17, count 0 2006.280.07:40:10.41#ibcon#about to read 3, iclass 17, count 0 2006.280.07:40:10.42#ibcon#read 3, iclass 17, count 0 2006.280.07:40:10.42#ibcon#about to read 4, iclass 17, count 0 2006.280.07:40:10.42#ibcon#read 4, iclass 17, count 0 2006.280.07:40:10.42#ibcon#about to read 5, iclass 17, count 0 2006.280.07:40:10.42#ibcon#read 5, iclass 17, count 0 2006.280.07:40:10.42#ibcon#about to read 6, iclass 17, count 0 2006.280.07:40:10.42#ibcon#read 6, iclass 17, count 0 2006.280.07:40:10.42#ibcon#end of sib2, iclass 17, count 0 2006.280.07:40:10.42#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:40:10.42#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:40:10.42#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:40:10.43#ibcon#*before write, iclass 17, count 0 2006.280.07:40:10.43#ibcon#enter sib2, iclass 17, count 0 2006.280.07:40:10.43#ibcon#flushed, iclass 17, count 0 2006.280.07:40:10.43#ibcon#about to write, iclass 17, count 0 2006.280.07:40:10.43#ibcon#wrote, iclass 17, count 0 2006.280.07:40:10.43#ibcon#about to read 3, iclass 17, count 0 2006.280.07:40:10.46#ibcon#read 3, iclass 17, count 0 2006.280.07:40:10.46#ibcon#about to read 4, iclass 17, count 0 2006.280.07:40:10.46#ibcon#read 4, iclass 17, count 0 2006.280.07:40:10.46#ibcon#about to read 5, iclass 17, count 0 2006.280.07:40:10.46#ibcon#read 5, iclass 17, count 0 2006.280.07:40:10.46#ibcon#about to read 6, iclass 17, count 0 2006.280.07:40:10.46#ibcon#read 6, iclass 17, count 0 2006.280.07:40:10.46#ibcon#end of sib2, iclass 17, count 0 2006.280.07:40:10.46#ibcon#*after write, iclass 17, count 0 2006.280.07:40:10.47#ibcon#*before return 0, iclass 17, count 0 2006.280.07:40:10.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:40:10.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:40:10.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:40:10.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:40:10.47$vc4f8/va=7,6 2006.280.07:40:10.47#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:40:10.47#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:40:10.47#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:10.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:40:10.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:40:10.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:40:10.52#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:40:10.52#ibcon#first serial, iclass 19, count 2 2006.280.07:40:10.52#ibcon#enter sib2, iclass 19, count 2 2006.280.07:40:10.52#ibcon#flushed, iclass 19, count 2 2006.280.07:40:10.52#ibcon#about to write, iclass 19, count 2 2006.280.07:40:10.53#ibcon#wrote, iclass 19, count 2 2006.280.07:40:10.53#ibcon#about to read 3, iclass 19, count 2 2006.280.07:40:10.54#ibcon#read 3, iclass 19, count 2 2006.280.07:40:10.54#ibcon#about to read 4, iclass 19, count 2 2006.280.07:40:10.54#ibcon#read 4, iclass 19, count 2 2006.280.07:40:10.54#ibcon#about to read 5, iclass 19, count 2 2006.280.07:40:10.54#ibcon#read 5, iclass 19, count 2 2006.280.07:40:10.54#ibcon#about to read 6, iclass 19, count 2 2006.280.07:40:10.54#ibcon#read 6, iclass 19, count 2 2006.280.07:40:10.54#ibcon#end of sib2, iclass 19, count 2 2006.280.07:40:10.54#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:40:10.54#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:40:10.54#ibcon#[25=AT07-06\r\n] 2006.280.07:40:10.55#ibcon#*before write, iclass 19, count 2 2006.280.07:40:10.55#ibcon#enter sib2, iclass 19, count 2 2006.280.07:40:10.55#ibcon#flushed, iclass 19, count 2 2006.280.07:40:10.55#ibcon#about to write, iclass 19, count 2 2006.280.07:40:10.55#ibcon#wrote, iclass 19, count 2 2006.280.07:40:10.55#ibcon#about to read 3, iclass 19, count 2 2006.280.07:40:10.58#ibcon#read 3, iclass 19, count 2 2006.280.07:40:10.58#ibcon#about to read 4, iclass 19, count 2 2006.280.07:40:10.58#ibcon#read 4, iclass 19, count 2 2006.280.07:40:10.58#ibcon#about to read 5, iclass 19, count 2 2006.280.07:40:10.58#ibcon#read 5, iclass 19, count 2 2006.280.07:40:10.58#ibcon#about to read 6, iclass 19, count 2 2006.280.07:40:10.58#ibcon#read 6, iclass 19, count 2 2006.280.07:40:10.58#ibcon#end of sib2, iclass 19, count 2 2006.280.07:40:10.58#ibcon#*after write, iclass 19, count 2 2006.280.07:40:10.58#ibcon#*before return 0, iclass 19, count 2 2006.280.07:40:10.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:40:10.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:40:10.58#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:40:10.58#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:10.58#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:40:10.69#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:40:10.69#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:40:10.69#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:40:10.69#ibcon#first serial, iclass 19, count 0 2006.280.07:40:10.69#ibcon#enter sib2, iclass 19, count 0 2006.280.07:40:10.69#ibcon#flushed, iclass 19, count 0 2006.280.07:40:10.69#ibcon#about to write, iclass 19, count 0 2006.280.07:40:10.69#ibcon#wrote, iclass 19, count 0 2006.280.07:40:10.69#ibcon#about to read 3, iclass 19, count 0 2006.280.07:40:10.71#ibcon#read 3, iclass 19, count 0 2006.280.07:40:10.71#ibcon#about to read 4, iclass 19, count 0 2006.280.07:40:10.71#ibcon#read 4, iclass 19, count 0 2006.280.07:40:10.71#ibcon#about to read 5, iclass 19, count 0 2006.280.07:40:10.71#ibcon#read 5, iclass 19, count 0 2006.280.07:40:10.71#ibcon#about to read 6, iclass 19, count 0 2006.280.07:40:10.71#ibcon#read 6, iclass 19, count 0 2006.280.07:40:10.71#ibcon#end of sib2, iclass 19, count 0 2006.280.07:40:10.71#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:40:10.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:40:10.71#ibcon#[25=USB\r\n] 2006.280.07:40:10.71#ibcon#*before write, iclass 19, count 0 2006.280.07:40:10.72#ibcon#enter sib2, iclass 19, count 0 2006.280.07:40:10.72#ibcon#flushed, iclass 19, count 0 2006.280.07:40:10.72#ibcon#about to write, iclass 19, count 0 2006.280.07:40:10.72#ibcon#wrote, iclass 19, count 0 2006.280.07:40:10.72#ibcon#about to read 3, iclass 19, count 0 2006.280.07:40:10.74#ibcon#read 3, iclass 19, count 0 2006.280.07:40:10.74#ibcon#about to read 4, iclass 19, count 0 2006.280.07:40:10.74#ibcon#read 4, iclass 19, count 0 2006.280.07:40:10.74#ibcon#about to read 5, iclass 19, count 0 2006.280.07:40:10.74#ibcon#read 5, iclass 19, count 0 2006.280.07:40:10.74#ibcon#about to read 6, iclass 19, count 0 2006.280.07:40:10.74#ibcon#read 6, iclass 19, count 0 2006.280.07:40:10.74#ibcon#end of sib2, iclass 19, count 0 2006.280.07:40:10.74#ibcon#*after write, iclass 19, count 0 2006.280.07:40:10.74#ibcon#*before return 0, iclass 19, count 0 2006.280.07:40:10.74#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:40:10.75#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:40:10.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:40:10.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:40:10.75$vc4f8/valo=8,852.99 2006.280.07:40:10.75#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:40:10.75#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:40:10.75#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:10.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:40:10.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:40:10.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:40:10.75#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:40:10.75#ibcon#first serial, iclass 21, count 0 2006.280.07:40:10.75#ibcon#enter sib2, iclass 21, count 0 2006.280.07:40:10.75#ibcon#flushed, iclass 21, count 0 2006.280.07:40:10.75#ibcon#about to write, iclass 21, count 0 2006.280.07:40:10.75#ibcon#wrote, iclass 21, count 0 2006.280.07:40:10.75#ibcon#about to read 3, iclass 21, count 0 2006.280.07:40:10.76#ibcon#read 3, iclass 21, count 0 2006.280.07:40:10.76#ibcon#about to read 4, iclass 21, count 0 2006.280.07:40:10.76#ibcon#read 4, iclass 21, count 0 2006.280.07:40:10.76#ibcon#about to read 5, iclass 21, count 0 2006.280.07:40:10.76#ibcon#read 5, iclass 21, count 0 2006.280.07:40:10.76#ibcon#about to read 6, iclass 21, count 0 2006.280.07:40:10.76#ibcon#read 6, iclass 21, count 0 2006.280.07:40:10.76#ibcon#end of sib2, iclass 21, count 0 2006.280.07:40:10.76#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:40:10.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:40:10.76#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:40:10.76#ibcon#*before write, iclass 21, count 0 2006.280.07:40:10.77#ibcon#enter sib2, iclass 21, count 0 2006.280.07:40:10.77#ibcon#flushed, iclass 21, count 0 2006.280.07:40:10.77#ibcon#about to write, iclass 21, count 0 2006.280.07:40:10.77#ibcon#wrote, iclass 21, count 0 2006.280.07:40:10.77#ibcon#about to read 3, iclass 21, count 0 2006.280.07:40:10.80#ibcon#read 3, iclass 21, count 0 2006.280.07:40:10.80#ibcon#about to read 4, iclass 21, count 0 2006.280.07:40:10.80#ibcon#read 4, iclass 21, count 0 2006.280.07:40:10.80#ibcon#about to read 5, iclass 21, count 0 2006.280.07:40:10.80#ibcon#read 5, iclass 21, count 0 2006.280.07:40:10.80#ibcon#about to read 6, iclass 21, count 0 2006.280.07:40:10.81#ibcon#read 6, iclass 21, count 0 2006.280.07:40:10.81#ibcon#end of sib2, iclass 21, count 0 2006.280.07:40:10.81#ibcon#*after write, iclass 21, count 0 2006.280.07:40:10.81#ibcon#*before return 0, iclass 21, count 0 2006.280.07:40:10.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:40:10.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:40:10.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:40:10.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:40:10.81$vc4f8/va=8,6 2006.280.07:40:10.82#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:40:10.82#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:40:10.82#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:10.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:40:10.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:40:10.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:40:10.88#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:40:10.88#ibcon#first serial, iclass 23, count 2 2006.280.07:40:10.88#ibcon#enter sib2, iclass 23, count 2 2006.280.07:40:10.88#ibcon#flushed, iclass 23, count 2 2006.280.07:40:10.88#ibcon#about to write, iclass 23, count 2 2006.280.07:40:10.88#ibcon#wrote, iclass 23, count 2 2006.280.07:40:10.88#ibcon#about to read 3, iclass 23, count 2 2006.280.07:40:10.89#ibcon#read 3, iclass 23, count 2 2006.280.07:40:10.89#ibcon#about to read 4, iclass 23, count 2 2006.280.07:40:10.89#ibcon#read 4, iclass 23, count 2 2006.280.07:40:10.89#ibcon#about to read 5, iclass 23, count 2 2006.280.07:40:10.89#ibcon#read 5, iclass 23, count 2 2006.280.07:40:10.89#ibcon#about to read 6, iclass 23, count 2 2006.280.07:40:10.89#ibcon#read 6, iclass 23, count 2 2006.280.07:40:10.89#ibcon#end of sib2, iclass 23, count 2 2006.280.07:40:10.89#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:40:10.89#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:40:10.90#ibcon#[25=AT08-06\r\n] 2006.280.07:40:10.90#ibcon#*before write, iclass 23, count 2 2006.280.07:40:10.90#ibcon#enter sib2, iclass 23, count 2 2006.280.07:40:10.90#ibcon#flushed, iclass 23, count 2 2006.280.07:40:10.90#ibcon#about to write, iclass 23, count 2 2006.280.07:40:10.90#ibcon#wrote, iclass 23, count 2 2006.280.07:40:10.90#ibcon#about to read 3, iclass 23, count 2 2006.280.07:40:10.92#ibcon#read 3, iclass 23, count 2 2006.280.07:40:10.92#ibcon#about to read 4, iclass 23, count 2 2006.280.07:40:10.92#ibcon#read 4, iclass 23, count 2 2006.280.07:40:10.92#ibcon#about to read 5, iclass 23, count 2 2006.280.07:40:10.92#ibcon#read 5, iclass 23, count 2 2006.280.07:40:10.92#ibcon#about to read 6, iclass 23, count 2 2006.280.07:40:10.92#ibcon#read 6, iclass 23, count 2 2006.280.07:40:10.92#ibcon#end of sib2, iclass 23, count 2 2006.280.07:40:10.92#ibcon#*after write, iclass 23, count 2 2006.280.07:40:10.92#ibcon#*before return 0, iclass 23, count 2 2006.280.07:40:10.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:40:10.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:40:10.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:40:10.93#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:10.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:40:11.03#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:40:11.03#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:40:11.03#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:40:11.03#ibcon#first serial, iclass 23, count 0 2006.280.07:40:11.03#ibcon#enter sib2, iclass 23, count 0 2006.280.07:40:11.03#ibcon#flushed, iclass 23, count 0 2006.280.07:40:11.03#ibcon#about to write, iclass 23, count 0 2006.280.07:40:11.03#ibcon#wrote, iclass 23, count 0 2006.280.07:40:11.03#ibcon#about to read 3, iclass 23, count 0 2006.280.07:40:11.05#ibcon#read 3, iclass 23, count 0 2006.280.07:40:11.05#ibcon#about to read 4, iclass 23, count 0 2006.280.07:40:11.05#ibcon#read 4, iclass 23, count 0 2006.280.07:40:11.05#ibcon#about to read 5, iclass 23, count 0 2006.280.07:40:11.05#ibcon#read 5, iclass 23, count 0 2006.280.07:40:11.05#ibcon#about to read 6, iclass 23, count 0 2006.280.07:40:11.05#ibcon#read 6, iclass 23, count 0 2006.280.07:40:11.05#ibcon#end of sib2, iclass 23, count 0 2006.280.07:40:11.05#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:40:11.05#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:40:11.05#ibcon#[25=USB\r\n] 2006.280.07:40:11.05#ibcon#*before write, iclass 23, count 0 2006.280.07:40:11.06#ibcon#enter sib2, iclass 23, count 0 2006.280.07:40:11.06#ibcon#flushed, iclass 23, count 0 2006.280.07:40:11.06#ibcon#about to write, iclass 23, count 0 2006.280.07:40:11.06#ibcon#wrote, iclass 23, count 0 2006.280.07:40:11.06#ibcon#about to read 3, iclass 23, count 0 2006.280.07:40:11.08#ibcon#read 3, iclass 23, count 0 2006.280.07:40:11.08#ibcon#about to read 4, iclass 23, count 0 2006.280.07:40:11.08#ibcon#read 4, iclass 23, count 0 2006.280.07:40:11.08#ibcon#about to read 5, iclass 23, count 0 2006.280.07:40:11.08#ibcon#read 5, iclass 23, count 0 2006.280.07:40:11.08#ibcon#about to read 6, iclass 23, count 0 2006.280.07:40:11.08#ibcon#read 6, iclass 23, count 0 2006.280.07:40:11.08#ibcon#end of sib2, iclass 23, count 0 2006.280.07:40:11.08#ibcon#*after write, iclass 23, count 0 2006.280.07:40:11.08#ibcon#*before return 0, iclass 23, count 0 2006.280.07:40:11.09#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:40:11.09#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:40:11.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:40:11.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:40:11.09$vc4f8/vblo=1,632.99 2006.280.07:40:11.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:40:11.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:40:11.09#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:11.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:40:11.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:40:11.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:40:11.09#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:40:11.09#ibcon#first serial, iclass 25, count 0 2006.280.07:40:11.09#ibcon#enter sib2, iclass 25, count 0 2006.280.07:40:11.09#ibcon#flushed, iclass 25, count 0 2006.280.07:40:11.09#ibcon#about to write, iclass 25, count 0 2006.280.07:40:11.09#ibcon#wrote, iclass 25, count 0 2006.280.07:40:11.09#ibcon#about to read 3, iclass 25, count 0 2006.280.07:40:11.10#ibcon#read 3, iclass 25, count 0 2006.280.07:40:11.10#ibcon#about to read 4, iclass 25, count 0 2006.280.07:40:11.10#ibcon#read 4, iclass 25, count 0 2006.280.07:40:11.10#ibcon#about to read 5, iclass 25, count 0 2006.280.07:40:11.10#ibcon#read 5, iclass 25, count 0 2006.280.07:40:11.10#ibcon#about to read 6, iclass 25, count 0 2006.280.07:40:11.10#ibcon#read 6, iclass 25, count 0 2006.280.07:40:11.10#ibcon#end of sib2, iclass 25, count 0 2006.280.07:40:11.10#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:40:11.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:40:11.11#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:40:11.11#ibcon#*before write, iclass 25, count 0 2006.280.07:40:11.11#ibcon#enter sib2, iclass 25, count 0 2006.280.07:40:11.11#ibcon#flushed, iclass 25, count 0 2006.280.07:40:11.11#ibcon#about to write, iclass 25, count 0 2006.280.07:40:11.11#ibcon#wrote, iclass 25, count 0 2006.280.07:40:11.11#ibcon#about to read 3, iclass 25, count 0 2006.280.07:40:11.15#ibcon#read 3, iclass 25, count 0 2006.280.07:40:11.15#ibcon#about to read 4, iclass 25, count 0 2006.280.07:40:11.15#ibcon#read 4, iclass 25, count 0 2006.280.07:40:11.15#ibcon#about to read 5, iclass 25, count 0 2006.280.07:40:11.15#ibcon#read 5, iclass 25, count 0 2006.280.07:40:11.15#ibcon#about to read 6, iclass 25, count 0 2006.280.07:40:11.15#ibcon#read 6, iclass 25, count 0 2006.280.07:40:11.15#ibcon#end of sib2, iclass 25, count 0 2006.280.07:40:11.15#ibcon#*after write, iclass 25, count 0 2006.280.07:40:11.15#ibcon#*before return 0, iclass 25, count 0 2006.280.07:40:11.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:40:11.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:40:11.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:40:11.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:40:11.15$vc4f8/vb=1,4 2006.280.07:40:11.15#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:40:11.15#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:40:11.15#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:11.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:40:11.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:40:11.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:40:11.15#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:40:11.15#ibcon#first serial, iclass 27, count 2 2006.280.07:40:11.15#ibcon#enter sib2, iclass 27, count 2 2006.280.07:40:11.15#ibcon#flushed, iclass 27, count 2 2006.280.07:40:11.15#ibcon#about to write, iclass 27, count 2 2006.280.07:40:11.15#ibcon#wrote, iclass 27, count 2 2006.280.07:40:11.15#ibcon#about to read 3, iclass 27, count 2 2006.280.07:40:11.16#ibcon#read 3, iclass 27, count 2 2006.280.07:40:11.17#ibcon#about to read 4, iclass 27, count 2 2006.280.07:40:11.17#ibcon#read 4, iclass 27, count 2 2006.280.07:40:11.17#ibcon#about to read 5, iclass 27, count 2 2006.280.07:40:11.17#ibcon#read 5, iclass 27, count 2 2006.280.07:40:11.17#ibcon#about to read 6, iclass 27, count 2 2006.280.07:40:11.17#ibcon#read 6, iclass 27, count 2 2006.280.07:40:11.17#ibcon#end of sib2, iclass 27, count 2 2006.280.07:40:11.17#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:40:11.17#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:40:11.17#ibcon#[27=AT01-04\r\n] 2006.280.07:40:11.17#ibcon#*before write, iclass 27, count 2 2006.280.07:40:11.17#ibcon#enter sib2, iclass 27, count 2 2006.280.07:40:11.17#ibcon#flushed, iclass 27, count 2 2006.280.07:40:11.17#ibcon#about to write, iclass 27, count 2 2006.280.07:40:11.17#ibcon#wrote, iclass 27, count 2 2006.280.07:40:11.17#ibcon#about to read 3, iclass 27, count 2 2006.280.07:40:11.20#ibcon#read 3, iclass 27, count 2 2006.280.07:40:11.20#ibcon#about to read 4, iclass 27, count 2 2006.280.07:40:11.20#ibcon#read 4, iclass 27, count 2 2006.280.07:40:11.20#ibcon#about to read 5, iclass 27, count 2 2006.280.07:40:11.20#ibcon#read 5, iclass 27, count 2 2006.280.07:40:11.20#ibcon#about to read 6, iclass 27, count 2 2006.280.07:40:11.20#ibcon#read 6, iclass 27, count 2 2006.280.07:40:11.20#ibcon#end of sib2, iclass 27, count 2 2006.280.07:40:11.20#ibcon#*after write, iclass 27, count 2 2006.280.07:40:11.20#ibcon#*before return 0, iclass 27, count 2 2006.280.07:40:11.20#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:40:11.20#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:40:11.20#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:40:11.20#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:11.20#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:40:11.32#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:40:11.32#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:40:11.32#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:40:11.32#ibcon#first serial, iclass 27, count 0 2006.280.07:40:11.32#ibcon#enter sib2, iclass 27, count 0 2006.280.07:40:11.32#ibcon#flushed, iclass 27, count 0 2006.280.07:40:11.32#ibcon#about to write, iclass 27, count 0 2006.280.07:40:11.32#ibcon#wrote, iclass 27, count 0 2006.280.07:40:11.32#ibcon#about to read 3, iclass 27, count 0 2006.280.07:40:11.34#ibcon#read 3, iclass 27, count 0 2006.280.07:40:11.34#ibcon#about to read 4, iclass 27, count 0 2006.280.07:40:11.34#ibcon#read 4, iclass 27, count 0 2006.280.07:40:11.34#ibcon#about to read 5, iclass 27, count 0 2006.280.07:40:11.34#ibcon#read 5, iclass 27, count 0 2006.280.07:40:11.34#ibcon#about to read 6, iclass 27, count 0 2006.280.07:40:11.34#ibcon#read 6, iclass 27, count 0 2006.280.07:40:11.34#ibcon#end of sib2, iclass 27, count 0 2006.280.07:40:11.34#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:40:11.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:40:11.34#ibcon#[27=USB\r\n] 2006.280.07:40:11.34#ibcon#*before write, iclass 27, count 0 2006.280.07:40:11.34#ibcon#enter sib2, iclass 27, count 0 2006.280.07:40:11.34#ibcon#flushed, iclass 27, count 0 2006.280.07:40:11.34#ibcon#about to write, iclass 27, count 0 2006.280.07:40:11.34#ibcon#wrote, iclass 27, count 0 2006.280.07:40:11.34#ibcon#about to read 3, iclass 27, count 0 2006.280.07:40:11.36#ibcon#read 3, iclass 27, count 0 2006.280.07:40:11.36#ibcon#about to read 4, iclass 27, count 0 2006.280.07:40:11.36#ibcon#read 4, iclass 27, count 0 2006.280.07:40:11.36#ibcon#about to read 5, iclass 27, count 0 2006.280.07:40:11.36#ibcon#read 5, iclass 27, count 0 2006.280.07:40:11.36#ibcon#about to read 6, iclass 27, count 0 2006.280.07:40:11.36#ibcon#read 6, iclass 27, count 0 2006.280.07:40:11.37#ibcon#end of sib2, iclass 27, count 0 2006.280.07:40:11.37#ibcon#*after write, iclass 27, count 0 2006.280.07:40:11.37#ibcon#*before return 0, iclass 27, count 0 2006.280.07:40:11.37#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:40:11.37#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:40:11.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:40:11.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:40:11.37$vc4f8/vblo=2,640.99 2006.280.07:40:11.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:40:11.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:40:11.37#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:11.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:11.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:11.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:11.37#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:40:11.37#ibcon#first serial, iclass 29, count 0 2006.280.07:40:11.37#ibcon#enter sib2, iclass 29, count 0 2006.280.07:40:11.37#ibcon#flushed, iclass 29, count 0 2006.280.07:40:11.37#ibcon#about to write, iclass 29, count 0 2006.280.07:40:11.37#ibcon#wrote, iclass 29, count 0 2006.280.07:40:11.37#ibcon#about to read 3, iclass 29, count 0 2006.280.07:40:11.38#ibcon#read 3, iclass 29, count 0 2006.280.07:40:11.38#ibcon#about to read 4, iclass 29, count 0 2006.280.07:40:11.38#ibcon#read 4, iclass 29, count 0 2006.280.07:40:11.38#ibcon#about to read 5, iclass 29, count 0 2006.280.07:40:11.38#ibcon#read 5, iclass 29, count 0 2006.280.07:40:11.38#ibcon#about to read 6, iclass 29, count 0 2006.280.07:40:11.38#ibcon#read 6, iclass 29, count 0 2006.280.07:40:11.38#ibcon#end of sib2, iclass 29, count 0 2006.280.07:40:11.38#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:40:11.38#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:40:11.38#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:40:11.38#ibcon#*before write, iclass 29, count 0 2006.280.07:40:11.38#ibcon#enter sib2, iclass 29, count 0 2006.280.07:40:11.39#ibcon#flushed, iclass 29, count 0 2006.280.07:40:11.39#ibcon#about to write, iclass 29, count 0 2006.280.07:40:11.39#ibcon#wrote, iclass 29, count 0 2006.280.07:40:11.39#ibcon#about to read 3, iclass 29, count 0 2006.280.07:40:11.43#ibcon#read 3, iclass 29, count 0 2006.280.07:40:11.43#ibcon#about to read 4, iclass 29, count 0 2006.280.07:40:11.43#ibcon#read 4, iclass 29, count 0 2006.280.07:40:11.43#ibcon#about to read 5, iclass 29, count 0 2006.280.07:40:11.43#ibcon#read 5, iclass 29, count 0 2006.280.07:40:11.43#ibcon#about to read 6, iclass 29, count 0 2006.280.07:40:11.43#ibcon#read 6, iclass 29, count 0 2006.280.07:40:11.43#ibcon#end of sib2, iclass 29, count 0 2006.280.07:40:11.43#ibcon#*after write, iclass 29, count 0 2006.280.07:40:11.43#ibcon#*before return 0, iclass 29, count 0 2006.280.07:40:11.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:11.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:40:11.43#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:40:11.43#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:40:11.43$vc4f8/vb=2,5 2006.280.07:40:11.43#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:40:11.43#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:40:11.43#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:11.43#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:11.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:11.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:11.49#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:40:11.49#ibcon#first serial, iclass 31, count 2 2006.280.07:40:11.49#ibcon#enter sib2, iclass 31, count 2 2006.280.07:40:11.49#ibcon#flushed, iclass 31, count 2 2006.280.07:40:11.49#ibcon#about to write, iclass 31, count 2 2006.280.07:40:11.49#ibcon#wrote, iclass 31, count 2 2006.280.07:40:11.49#ibcon#about to read 3, iclass 31, count 2 2006.280.07:40:11.51#ibcon#read 3, iclass 31, count 2 2006.280.07:40:11.51#ibcon#about to read 4, iclass 31, count 2 2006.280.07:40:11.51#ibcon#read 4, iclass 31, count 2 2006.280.07:40:11.51#ibcon#about to read 5, iclass 31, count 2 2006.280.07:40:11.51#ibcon#read 5, iclass 31, count 2 2006.280.07:40:11.51#ibcon#about to read 6, iclass 31, count 2 2006.280.07:40:11.51#ibcon#read 6, iclass 31, count 2 2006.280.07:40:11.51#ibcon#end of sib2, iclass 31, count 2 2006.280.07:40:11.51#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:40:11.51#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:40:11.51#ibcon#[27=AT02-05\r\n] 2006.280.07:40:11.51#ibcon#*before write, iclass 31, count 2 2006.280.07:40:11.51#ibcon#enter sib2, iclass 31, count 2 2006.280.07:40:11.51#ibcon#flushed, iclass 31, count 2 2006.280.07:40:11.51#ibcon#about to write, iclass 31, count 2 2006.280.07:40:11.51#ibcon#wrote, iclass 31, count 2 2006.280.07:40:11.51#ibcon#about to read 3, iclass 31, count 2 2006.280.07:40:11.54#ibcon#read 3, iclass 31, count 2 2006.280.07:40:11.54#ibcon#about to read 4, iclass 31, count 2 2006.280.07:40:11.54#ibcon#read 4, iclass 31, count 2 2006.280.07:40:11.54#ibcon#about to read 5, iclass 31, count 2 2006.280.07:40:11.54#ibcon#read 5, iclass 31, count 2 2006.280.07:40:11.54#ibcon#about to read 6, iclass 31, count 2 2006.280.07:40:11.54#ibcon#read 6, iclass 31, count 2 2006.280.07:40:11.54#ibcon#end of sib2, iclass 31, count 2 2006.280.07:40:11.54#ibcon#*after write, iclass 31, count 2 2006.280.07:40:11.54#ibcon#*before return 0, iclass 31, count 2 2006.280.07:40:11.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:11.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:40:11.54#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:40:11.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:11.54#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:11.66#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:11.66#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:11.66#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:40:11.66#ibcon#first serial, iclass 31, count 0 2006.280.07:40:11.66#ibcon#enter sib2, iclass 31, count 0 2006.280.07:40:11.66#ibcon#flushed, iclass 31, count 0 2006.280.07:40:11.66#ibcon#about to write, iclass 31, count 0 2006.280.07:40:11.66#ibcon#wrote, iclass 31, count 0 2006.280.07:40:11.66#ibcon#about to read 3, iclass 31, count 0 2006.280.07:40:11.67#ibcon#read 3, iclass 31, count 0 2006.280.07:40:11.67#ibcon#about to read 4, iclass 31, count 0 2006.280.07:40:11.67#ibcon#read 4, iclass 31, count 0 2006.280.07:40:11.67#ibcon#about to read 5, iclass 31, count 0 2006.280.07:40:11.67#ibcon#read 5, iclass 31, count 0 2006.280.07:40:11.67#ibcon#about to read 6, iclass 31, count 0 2006.280.07:40:11.67#ibcon#read 6, iclass 31, count 0 2006.280.07:40:11.67#ibcon#end of sib2, iclass 31, count 0 2006.280.07:40:11.68#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:40:11.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:40:11.68#ibcon#[27=USB\r\n] 2006.280.07:40:11.68#ibcon#*before write, iclass 31, count 0 2006.280.07:40:11.68#ibcon#enter sib2, iclass 31, count 0 2006.280.07:40:11.68#ibcon#flushed, iclass 31, count 0 2006.280.07:40:11.68#ibcon#about to write, iclass 31, count 0 2006.280.07:40:11.68#ibcon#wrote, iclass 31, count 0 2006.280.07:40:11.68#ibcon#about to read 3, iclass 31, count 0 2006.280.07:40:11.71#ibcon#read 3, iclass 31, count 0 2006.280.07:40:11.71#ibcon#about to read 4, iclass 31, count 0 2006.280.07:40:11.71#ibcon#read 4, iclass 31, count 0 2006.280.07:40:11.71#ibcon#about to read 5, iclass 31, count 0 2006.280.07:40:11.71#ibcon#read 5, iclass 31, count 0 2006.280.07:40:11.71#ibcon#about to read 6, iclass 31, count 0 2006.280.07:40:11.71#ibcon#read 6, iclass 31, count 0 2006.280.07:40:11.71#ibcon#end of sib2, iclass 31, count 0 2006.280.07:40:11.71#ibcon#*after write, iclass 31, count 0 2006.280.07:40:11.71#ibcon#*before return 0, iclass 31, count 0 2006.280.07:40:11.71#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:11.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:40:11.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:40:11.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:40:11.71$vc4f8/vblo=3,656.99 2006.280.07:40:11.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:40:11.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:40:11.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:11.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:11.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:11.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:11.71#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:40:11.71#ibcon#first serial, iclass 33, count 0 2006.280.07:40:11.71#ibcon#enter sib2, iclass 33, count 0 2006.280.07:40:11.71#ibcon#flushed, iclass 33, count 0 2006.280.07:40:11.71#ibcon#about to write, iclass 33, count 0 2006.280.07:40:11.71#ibcon#wrote, iclass 33, count 0 2006.280.07:40:11.71#ibcon#about to read 3, iclass 33, count 0 2006.280.07:40:11.73#ibcon#read 3, iclass 33, count 0 2006.280.07:40:11.73#ibcon#about to read 4, iclass 33, count 0 2006.280.07:40:11.73#ibcon#read 4, iclass 33, count 0 2006.280.07:40:11.73#ibcon#about to read 5, iclass 33, count 0 2006.280.07:40:11.73#ibcon#read 5, iclass 33, count 0 2006.280.07:40:11.73#ibcon#about to read 6, iclass 33, count 0 2006.280.07:40:11.73#ibcon#read 6, iclass 33, count 0 2006.280.07:40:11.73#ibcon#end of sib2, iclass 33, count 0 2006.280.07:40:11.73#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:40:11.73#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:40:11.73#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:40:11.73#ibcon#*before write, iclass 33, count 0 2006.280.07:40:11.73#ibcon#enter sib2, iclass 33, count 0 2006.280.07:40:11.73#ibcon#flushed, iclass 33, count 0 2006.280.07:40:11.73#ibcon#about to write, iclass 33, count 0 2006.280.07:40:11.73#ibcon#wrote, iclass 33, count 0 2006.280.07:40:11.73#ibcon#about to read 3, iclass 33, count 0 2006.280.07:40:11.77#ibcon#read 3, iclass 33, count 0 2006.280.07:40:11.77#ibcon#about to read 4, iclass 33, count 0 2006.280.07:40:11.77#ibcon#read 4, iclass 33, count 0 2006.280.07:40:11.77#ibcon#about to read 5, iclass 33, count 0 2006.280.07:40:11.77#ibcon#read 5, iclass 33, count 0 2006.280.07:40:11.77#ibcon#about to read 6, iclass 33, count 0 2006.280.07:40:11.77#ibcon#read 6, iclass 33, count 0 2006.280.07:40:11.77#ibcon#end of sib2, iclass 33, count 0 2006.280.07:40:11.78#ibcon#*after write, iclass 33, count 0 2006.280.07:40:11.78#ibcon#*before return 0, iclass 33, count 0 2006.280.07:40:11.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:11.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:40:11.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:40:11.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:40:11.78$vc4f8/vb=3,4 2006.280.07:40:11.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:40:11.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:40:11.78#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:11.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:11.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:11.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:11.82#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:40:11.82#ibcon#first serial, iclass 35, count 2 2006.280.07:40:11.82#ibcon#enter sib2, iclass 35, count 2 2006.280.07:40:11.82#ibcon#flushed, iclass 35, count 2 2006.280.07:40:11.82#ibcon#about to write, iclass 35, count 2 2006.280.07:40:11.82#ibcon#wrote, iclass 35, count 2 2006.280.07:40:11.82#ibcon#about to read 3, iclass 35, count 2 2006.280.07:40:11.85#ibcon#read 3, iclass 35, count 2 2006.280.07:40:11.85#ibcon#about to read 4, iclass 35, count 2 2006.280.07:40:11.85#ibcon#read 4, iclass 35, count 2 2006.280.07:40:11.85#ibcon#about to read 5, iclass 35, count 2 2006.280.07:40:11.85#ibcon#read 5, iclass 35, count 2 2006.280.07:40:11.85#ibcon#about to read 6, iclass 35, count 2 2006.280.07:40:11.85#ibcon#read 6, iclass 35, count 2 2006.280.07:40:11.85#ibcon#end of sib2, iclass 35, count 2 2006.280.07:40:11.85#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:40:11.85#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:40:11.85#ibcon#[27=AT03-04\r\n] 2006.280.07:40:11.85#ibcon#*before write, iclass 35, count 2 2006.280.07:40:11.85#ibcon#enter sib2, iclass 35, count 2 2006.280.07:40:11.85#ibcon#flushed, iclass 35, count 2 2006.280.07:40:11.85#ibcon#about to write, iclass 35, count 2 2006.280.07:40:11.85#ibcon#wrote, iclass 35, count 2 2006.280.07:40:11.85#ibcon#about to read 3, iclass 35, count 2 2006.280.07:40:11.88#ibcon#read 3, iclass 35, count 2 2006.280.07:40:11.88#ibcon#about to read 4, iclass 35, count 2 2006.280.07:40:11.88#ibcon#read 4, iclass 35, count 2 2006.280.07:40:11.88#ibcon#about to read 5, iclass 35, count 2 2006.280.07:40:11.88#ibcon#read 5, iclass 35, count 2 2006.280.07:40:11.88#ibcon#about to read 6, iclass 35, count 2 2006.280.07:40:11.88#ibcon#read 6, iclass 35, count 2 2006.280.07:40:11.88#ibcon#end of sib2, iclass 35, count 2 2006.280.07:40:11.89#ibcon#*after write, iclass 35, count 2 2006.280.07:40:11.89#ibcon#*before return 0, iclass 35, count 2 2006.280.07:40:11.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:11.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:40:11.89#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:40:11.89#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:11.89#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:12.01#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:12.01#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:12.01#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:40:12.01#ibcon#first serial, iclass 35, count 0 2006.280.07:40:12.01#ibcon#enter sib2, iclass 35, count 0 2006.280.07:40:12.01#ibcon#flushed, iclass 35, count 0 2006.280.07:40:12.01#ibcon#about to write, iclass 35, count 0 2006.280.07:40:12.01#ibcon#wrote, iclass 35, count 0 2006.280.07:40:12.01#ibcon#about to read 3, iclass 35, count 0 2006.280.07:40:12.02#ibcon#read 3, iclass 35, count 0 2006.280.07:40:12.02#ibcon#about to read 4, iclass 35, count 0 2006.280.07:40:12.02#ibcon#read 4, iclass 35, count 0 2006.280.07:40:12.02#ibcon#about to read 5, iclass 35, count 0 2006.280.07:40:12.02#ibcon#read 5, iclass 35, count 0 2006.280.07:40:12.02#ibcon#about to read 6, iclass 35, count 0 2006.280.07:40:12.02#ibcon#read 6, iclass 35, count 0 2006.280.07:40:12.02#ibcon#end of sib2, iclass 35, count 0 2006.280.07:40:12.02#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:40:12.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:40:12.02#ibcon#[27=USB\r\n] 2006.280.07:40:12.02#ibcon#*before write, iclass 35, count 0 2006.280.07:40:12.03#ibcon#enter sib2, iclass 35, count 0 2006.280.07:40:12.03#ibcon#flushed, iclass 35, count 0 2006.280.07:40:12.03#ibcon#about to write, iclass 35, count 0 2006.280.07:40:12.03#ibcon#wrote, iclass 35, count 0 2006.280.07:40:12.03#ibcon#about to read 3, iclass 35, count 0 2006.280.07:40:12.05#ibcon#read 3, iclass 35, count 0 2006.280.07:40:12.05#ibcon#about to read 4, iclass 35, count 0 2006.280.07:40:12.05#ibcon#read 4, iclass 35, count 0 2006.280.07:40:12.05#ibcon#about to read 5, iclass 35, count 0 2006.280.07:40:12.05#ibcon#read 5, iclass 35, count 0 2006.280.07:40:12.05#ibcon#about to read 6, iclass 35, count 0 2006.280.07:40:12.05#ibcon#read 6, iclass 35, count 0 2006.280.07:40:12.05#ibcon#end of sib2, iclass 35, count 0 2006.280.07:40:12.05#ibcon#*after write, iclass 35, count 0 2006.280.07:40:12.05#ibcon#*before return 0, iclass 35, count 0 2006.280.07:40:12.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:12.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:40:12.06#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:40:12.06#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:40:12.06$vc4f8/vblo=4,712.99 2006.280.07:40:12.06#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:40:12.06#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:40:12.06#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:12.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:12.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:12.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:12.06#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:40:12.06#ibcon#first serial, iclass 37, count 0 2006.280.07:40:12.06#ibcon#enter sib2, iclass 37, count 0 2006.280.07:40:12.06#ibcon#flushed, iclass 37, count 0 2006.280.07:40:12.06#ibcon#about to write, iclass 37, count 0 2006.280.07:40:12.06#ibcon#wrote, iclass 37, count 0 2006.280.07:40:12.06#ibcon#about to read 3, iclass 37, count 0 2006.280.07:40:12.07#ibcon#read 3, iclass 37, count 0 2006.280.07:40:12.08#ibcon#about to read 4, iclass 37, count 0 2006.280.07:40:12.08#ibcon#read 4, iclass 37, count 0 2006.280.07:40:12.08#ibcon#about to read 5, iclass 37, count 0 2006.280.07:40:12.08#ibcon#read 5, iclass 37, count 0 2006.280.07:40:12.08#ibcon#about to read 6, iclass 37, count 0 2006.280.07:40:12.08#ibcon#read 6, iclass 37, count 0 2006.280.07:40:12.08#ibcon#end of sib2, iclass 37, count 0 2006.280.07:40:12.08#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:40:12.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:40:12.08#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:40:12.08#ibcon#*before write, iclass 37, count 0 2006.280.07:40:12.08#ibcon#enter sib2, iclass 37, count 0 2006.280.07:40:12.08#ibcon#flushed, iclass 37, count 0 2006.280.07:40:12.08#ibcon#about to write, iclass 37, count 0 2006.280.07:40:12.08#ibcon#wrote, iclass 37, count 0 2006.280.07:40:12.08#ibcon#about to read 3, iclass 37, count 0 2006.280.07:40:12.13#ibcon#read 3, iclass 37, count 0 2006.280.07:40:12.13#ibcon#about to read 4, iclass 37, count 0 2006.280.07:40:12.13#ibcon#read 4, iclass 37, count 0 2006.280.07:40:12.13#ibcon#about to read 5, iclass 37, count 0 2006.280.07:40:12.13#ibcon#read 5, iclass 37, count 0 2006.280.07:40:12.13#ibcon#about to read 6, iclass 37, count 0 2006.280.07:40:12.13#ibcon#read 6, iclass 37, count 0 2006.280.07:40:12.13#ibcon#end of sib2, iclass 37, count 0 2006.280.07:40:12.13#ibcon#*after write, iclass 37, count 0 2006.280.07:40:12.13#ibcon#*before return 0, iclass 37, count 0 2006.280.07:40:12.13#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:12.13#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:40:12.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:40:12.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:40:12.13$vc4f8/vb=4,4 2006.280.07:40:12.13#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:40:12.13#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:40:12.13#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:12.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:12.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:12.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:12.16#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:40:12.16#ibcon#first serial, iclass 39, count 2 2006.280.07:40:12.16#ibcon#enter sib2, iclass 39, count 2 2006.280.07:40:12.16#ibcon#flushed, iclass 39, count 2 2006.280.07:40:12.16#ibcon#about to write, iclass 39, count 2 2006.280.07:40:12.16#ibcon#wrote, iclass 39, count 2 2006.280.07:40:12.16#ibcon#about to read 3, iclass 39, count 2 2006.280.07:40:12.18#ibcon#read 3, iclass 39, count 2 2006.280.07:40:12.18#ibcon#about to read 4, iclass 39, count 2 2006.280.07:40:12.18#ibcon#read 4, iclass 39, count 2 2006.280.07:40:12.18#ibcon#about to read 5, iclass 39, count 2 2006.280.07:40:12.18#ibcon#read 5, iclass 39, count 2 2006.280.07:40:12.18#ibcon#about to read 6, iclass 39, count 2 2006.280.07:40:12.18#ibcon#read 6, iclass 39, count 2 2006.280.07:40:12.18#ibcon#end of sib2, iclass 39, count 2 2006.280.07:40:12.18#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:40:12.19#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:40:12.19#ibcon#[27=AT04-04\r\n] 2006.280.07:40:12.19#ibcon#*before write, iclass 39, count 2 2006.280.07:40:12.20#ibcon#enter sib2, iclass 39, count 2 2006.280.07:40:12.20#ibcon#flushed, iclass 39, count 2 2006.280.07:40:12.20#ibcon#about to write, iclass 39, count 2 2006.280.07:40:12.20#ibcon#wrote, iclass 39, count 2 2006.280.07:40:12.20#ibcon#about to read 3, iclass 39, count 2 2006.280.07:40:12.22#ibcon#read 3, iclass 39, count 2 2006.280.07:40:12.22#ibcon#about to read 4, iclass 39, count 2 2006.280.07:40:12.22#ibcon#read 4, iclass 39, count 2 2006.280.07:40:12.22#ibcon#about to read 5, iclass 39, count 2 2006.280.07:40:12.22#ibcon#read 5, iclass 39, count 2 2006.280.07:40:12.22#ibcon#about to read 6, iclass 39, count 2 2006.280.07:40:12.22#ibcon#read 6, iclass 39, count 2 2006.280.07:40:12.22#ibcon#end of sib2, iclass 39, count 2 2006.280.07:40:12.22#ibcon#*after write, iclass 39, count 2 2006.280.07:40:12.22#ibcon#*before return 0, iclass 39, count 2 2006.280.07:40:12.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:12.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:40:12.23#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:40:12.23#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:12.23#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:12.34#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:12.34#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:12.34#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:40:12.34#ibcon#first serial, iclass 39, count 0 2006.280.07:40:12.34#ibcon#enter sib2, iclass 39, count 0 2006.280.07:40:12.34#ibcon#flushed, iclass 39, count 0 2006.280.07:40:12.34#ibcon#about to write, iclass 39, count 0 2006.280.07:40:12.34#ibcon#wrote, iclass 39, count 0 2006.280.07:40:12.34#ibcon#about to read 3, iclass 39, count 0 2006.280.07:40:12.35#ibcon#read 3, iclass 39, count 0 2006.280.07:40:12.35#ibcon#about to read 4, iclass 39, count 0 2006.280.07:40:12.35#ibcon#read 4, iclass 39, count 0 2006.280.07:40:12.35#ibcon#about to read 5, iclass 39, count 0 2006.280.07:40:12.35#ibcon#read 5, iclass 39, count 0 2006.280.07:40:12.35#ibcon#about to read 6, iclass 39, count 0 2006.280.07:40:12.35#ibcon#read 6, iclass 39, count 0 2006.280.07:40:12.35#ibcon#end of sib2, iclass 39, count 0 2006.280.07:40:12.35#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:40:12.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:40:12.35#ibcon#[27=USB\r\n] 2006.280.07:40:12.35#ibcon#*before write, iclass 39, count 0 2006.280.07:40:12.35#ibcon#enter sib2, iclass 39, count 0 2006.280.07:40:12.36#ibcon#flushed, iclass 39, count 0 2006.280.07:40:12.36#ibcon#about to write, iclass 39, count 0 2006.280.07:40:12.36#ibcon#wrote, iclass 39, count 0 2006.280.07:40:12.36#ibcon#about to read 3, iclass 39, count 0 2006.280.07:40:12.38#ibcon#read 3, iclass 39, count 0 2006.280.07:40:12.38#ibcon#about to read 4, iclass 39, count 0 2006.280.07:40:12.38#ibcon#read 4, iclass 39, count 0 2006.280.07:40:12.38#ibcon#about to read 5, iclass 39, count 0 2006.280.07:40:12.38#ibcon#read 5, iclass 39, count 0 2006.280.07:40:12.38#ibcon#about to read 6, iclass 39, count 0 2006.280.07:40:12.38#ibcon#read 6, iclass 39, count 0 2006.280.07:40:12.38#ibcon#end of sib2, iclass 39, count 0 2006.280.07:40:12.38#ibcon#*after write, iclass 39, count 0 2006.280.07:40:12.38#ibcon#*before return 0, iclass 39, count 0 2006.280.07:40:12.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:12.39#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:40:12.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:40:12.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:40:12.39$vc4f8/vblo=5,744.99 2006.280.07:40:12.39#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:40:12.39#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:40:12.39#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:12.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:12.39#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:12.39#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:12.39#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:40:12.39#ibcon#first serial, iclass 3, count 0 2006.280.07:40:12.39#ibcon#enter sib2, iclass 3, count 0 2006.280.07:40:12.39#ibcon#flushed, iclass 3, count 0 2006.280.07:40:12.39#ibcon#about to write, iclass 3, count 0 2006.280.07:40:12.39#ibcon#wrote, iclass 3, count 0 2006.280.07:40:12.39#ibcon#about to read 3, iclass 3, count 0 2006.280.07:40:12.40#ibcon#read 3, iclass 3, count 0 2006.280.07:40:12.40#ibcon#about to read 4, iclass 3, count 0 2006.280.07:40:12.40#ibcon#read 4, iclass 3, count 0 2006.280.07:40:12.40#ibcon#about to read 5, iclass 3, count 0 2006.280.07:40:12.40#ibcon#read 5, iclass 3, count 0 2006.280.07:40:12.40#ibcon#about to read 6, iclass 3, count 0 2006.280.07:40:12.40#ibcon#read 6, iclass 3, count 0 2006.280.07:40:12.40#ibcon#end of sib2, iclass 3, count 0 2006.280.07:40:12.40#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:40:12.40#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:40:12.40#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:40:12.40#ibcon#*before write, iclass 3, count 0 2006.280.07:40:12.41#ibcon#enter sib2, iclass 3, count 0 2006.280.07:40:12.41#ibcon#flushed, iclass 3, count 0 2006.280.07:40:12.41#ibcon#about to write, iclass 3, count 0 2006.280.07:40:12.41#ibcon#wrote, iclass 3, count 0 2006.280.07:40:12.41#ibcon#about to read 3, iclass 3, count 0 2006.280.07:40:12.44#ibcon#read 3, iclass 3, count 0 2006.280.07:40:12.44#ibcon#about to read 4, iclass 3, count 0 2006.280.07:40:12.44#ibcon#read 4, iclass 3, count 0 2006.280.07:40:12.44#ibcon#about to read 5, iclass 3, count 0 2006.280.07:40:12.44#ibcon#read 5, iclass 3, count 0 2006.280.07:40:12.44#ibcon#about to read 6, iclass 3, count 0 2006.280.07:40:12.44#ibcon#read 6, iclass 3, count 0 2006.280.07:40:12.44#ibcon#end of sib2, iclass 3, count 0 2006.280.07:40:12.44#ibcon#*after write, iclass 3, count 0 2006.280.07:40:12.44#ibcon#*before return 0, iclass 3, count 0 2006.280.07:40:12.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:12.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:40:12.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:40:12.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:40:12.45$vc4f8/vb=5,4 2006.280.07:40:12.45#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:40:12.45#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:40:12.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:12.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:12.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:12.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:12.50#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:40:12.50#ibcon#first serial, iclass 5, count 2 2006.280.07:40:12.50#ibcon#enter sib2, iclass 5, count 2 2006.280.07:40:12.50#ibcon#flushed, iclass 5, count 2 2006.280.07:40:12.50#ibcon#about to write, iclass 5, count 2 2006.280.07:40:12.50#ibcon#wrote, iclass 5, count 2 2006.280.07:40:12.50#ibcon#about to read 3, iclass 5, count 2 2006.280.07:40:12.52#ibcon#read 3, iclass 5, count 2 2006.280.07:40:12.52#ibcon#about to read 4, iclass 5, count 2 2006.280.07:40:12.52#ibcon#read 4, iclass 5, count 2 2006.280.07:40:12.52#ibcon#about to read 5, iclass 5, count 2 2006.280.07:40:12.52#ibcon#read 5, iclass 5, count 2 2006.280.07:40:12.52#ibcon#about to read 6, iclass 5, count 2 2006.280.07:40:12.52#ibcon#read 6, iclass 5, count 2 2006.280.07:40:12.52#ibcon#end of sib2, iclass 5, count 2 2006.280.07:40:12.52#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:40:12.52#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:40:12.52#ibcon#[27=AT05-04\r\n] 2006.280.07:40:12.53#ibcon#*before write, iclass 5, count 2 2006.280.07:40:12.53#ibcon#enter sib2, iclass 5, count 2 2006.280.07:40:12.53#ibcon#flushed, iclass 5, count 2 2006.280.07:40:12.53#ibcon#about to write, iclass 5, count 2 2006.280.07:40:12.53#ibcon#wrote, iclass 5, count 2 2006.280.07:40:12.53#ibcon#about to read 3, iclass 5, count 2 2006.280.07:40:12.56#ibcon#read 3, iclass 5, count 2 2006.280.07:40:12.56#ibcon#about to read 4, iclass 5, count 2 2006.280.07:40:12.56#ibcon#read 4, iclass 5, count 2 2006.280.07:40:12.56#ibcon#about to read 5, iclass 5, count 2 2006.280.07:40:12.56#ibcon#read 5, iclass 5, count 2 2006.280.07:40:12.56#ibcon#about to read 6, iclass 5, count 2 2006.280.07:40:12.56#ibcon#read 6, iclass 5, count 2 2006.280.07:40:12.56#ibcon#end of sib2, iclass 5, count 2 2006.280.07:40:12.56#ibcon#*after write, iclass 5, count 2 2006.280.07:40:12.56#ibcon#*before return 0, iclass 5, count 2 2006.280.07:40:12.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:12.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:40:12.56#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:40:12.56#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:12.56#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:12.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:12.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:12.67#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:40:12.67#ibcon#first serial, iclass 5, count 0 2006.280.07:40:12.67#ibcon#enter sib2, iclass 5, count 0 2006.280.07:40:12.67#ibcon#flushed, iclass 5, count 0 2006.280.07:40:12.67#ibcon#about to write, iclass 5, count 0 2006.280.07:40:12.68#ibcon#wrote, iclass 5, count 0 2006.280.07:40:12.68#ibcon#about to read 3, iclass 5, count 0 2006.280.07:40:12.69#ibcon#read 3, iclass 5, count 0 2006.280.07:40:12.69#ibcon#about to read 4, iclass 5, count 0 2006.280.07:40:12.69#ibcon#read 4, iclass 5, count 0 2006.280.07:40:12.69#ibcon#about to read 5, iclass 5, count 0 2006.280.07:40:12.69#ibcon#read 5, iclass 5, count 0 2006.280.07:40:12.69#ibcon#about to read 6, iclass 5, count 0 2006.280.07:40:12.69#ibcon#read 6, iclass 5, count 0 2006.280.07:40:12.69#ibcon#end of sib2, iclass 5, count 0 2006.280.07:40:12.69#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:40:12.69#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:40:12.69#ibcon#[27=USB\r\n] 2006.280.07:40:12.69#ibcon#*before write, iclass 5, count 0 2006.280.07:40:12.70#ibcon#enter sib2, iclass 5, count 0 2006.280.07:40:12.70#ibcon#flushed, iclass 5, count 0 2006.280.07:40:12.70#ibcon#about to write, iclass 5, count 0 2006.280.07:40:12.70#ibcon#wrote, iclass 5, count 0 2006.280.07:40:12.70#ibcon#about to read 3, iclass 5, count 0 2006.280.07:40:12.72#ibcon#read 3, iclass 5, count 0 2006.280.07:40:12.72#ibcon#about to read 4, iclass 5, count 0 2006.280.07:40:12.72#ibcon#read 4, iclass 5, count 0 2006.280.07:40:12.72#ibcon#about to read 5, iclass 5, count 0 2006.280.07:40:12.72#ibcon#read 5, iclass 5, count 0 2006.280.07:40:12.72#ibcon#about to read 6, iclass 5, count 0 2006.280.07:40:12.72#ibcon#read 6, iclass 5, count 0 2006.280.07:40:12.72#ibcon#end of sib2, iclass 5, count 0 2006.280.07:40:12.72#ibcon#*after write, iclass 5, count 0 2006.280.07:40:12.72#ibcon#*before return 0, iclass 5, count 0 2006.280.07:40:12.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:12.73#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:40:12.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:40:12.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:40:12.73$vc4f8/vblo=6,752.99 2006.280.07:40:12.73#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:40:12.73#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:40:12.73#ibcon#ireg 17 cls_cnt 0 2006.280.07:40:12.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:12.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:12.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:12.73#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:40:12.73#ibcon#first serial, iclass 7, count 0 2006.280.07:40:12.73#ibcon#enter sib2, iclass 7, count 0 2006.280.07:40:12.73#ibcon#flushed, iclass 7, count 0 2006.280.07:40:12.73#ibcon#about to write, iclass 7, count 0 2006.280.07:40:12.73#ibcon#wrote, iclass 7, count 0 2006.280.07:40:12.73#ibcon#about to read 3, iclass 7, count 0 2006.280.07:40:12.74#ibcon#read 3, iclass 7, count 0 2006.280.07:40:12.74#ibcon#about to read 4, iclass 7, count 0 2006.280.07:40:12.74#ibcon#read 4, iclass 7, count 0 2006.280.07:40:12.74#ibcon#about to read 5, iclass 7, count 0 2006.280.07:40:12.74#ibcon#read 5, iclass 7, count 0 2006.280.07:40:12.74#ibcon#about to read 6, iclass 7, count 0 2006.280.07:40:12.74#ibcon#read 6, iclass 7, count 0 2006.280.07:40:12.74#ibcon#end of sib2, iclass 7, count 0 2006.280.07:40:12.74#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:40:12.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:40:12.74#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:40:12.75#ibcon#*before write, iclass 7, count 0 2006.280.07:40:12.75#ibcon#enter sib2, iclass 7, count 0 2006.280.07:40:12.75#ibcon#flushed, iclass 7, count 0 2006.280.07:40:12.75#ibcon#about to write, iclass 7, count 0 2006.280.07:40:12.75#ibcon#wrote, iclass 7, count 0 2006.280.07:40:12.75#ibcon#about to read 3, iclass 7, count 0 2006.280.07:40:12.78#ibcon#read 3, iclass 7, count 0 2006.280.07:40:12.78#ibcon#about to read 4, iclass 7, count 0 2006.280.07:40:12.78#ibcon#read 4, iclass 7, count 0 2006.280.07:40:12.78#ibcon#about to read 5, iclass 7, count 0 2006.280.07:40:12.78#ibcon#read 5, iclass 7, count 0 2006.280.07:40:12.78#ibcon#about to read 6, iclass 7, count 0 2006.280.07:40:12.78#ibcon#read 6, iclass 7, count 0 2006.280.07:40:12.78#ibcon#end of sib2, iclass 7, count 0 2006.280.07:40:12.78#ibcon#*after write, iclass 7, count 0 2006.280.07:40:12.78#ibcon#*before return 0, iclass 7, count 0 2006.280.07:40:12.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:12.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:40:12.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:40:12.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:40:12.79$vc4f8/vb=6,4 2006.280.07:40:12.79#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:40:12.79#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:40:12.79#ibcon#ireg 11 cls_cnt 2 2006.280.07:40:12.79#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:12.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:12.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:12.84#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:40:12.84#ibcon#first serial, iclass 11, count 2 2006.280.07:40:12.84#ibcon#enter sib2, iclass 11, count 2 2006.280.07:40:12.84#ibcon#flushed, iclass 11, count 2 2006.280.07:40:12.84#ibcon#about to write, iclass 11, count 2 2006.280.07:40:12.84#ibcon#wrote, iclass 11, count 2 2006.280.07:40:12.84#ibcon#about to read 3, iclass 11, count 2 2006.280.07:40:12.87#ibcon#read 3, iclass 11, count 2 2006.280.07:40:12.87#ibcon#about to read 4, iclass 11, count 2 2006.280.07:40:12.87#ibcon#read 4, iclass 11, count 2 2006.280.07:40:12.87#ibcon#about to read 5, iclass 11, count 2 2006.280.07:40:12.87#ibcon#read 5, iclass 11, count 2 2006.280.07:40:12.87#ibcon#about to read 6, iclass 11, count 2 2006.280.07:40:12.87#ibcon#read 6, iclass 11, count 2 2006.280.07:40:12.87#ibcon#end of sib2, iclass 11, count 2 2006.280.07:40:12.87#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:40:12.87#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:40:12.87#ibcon#[27=AT06-04\r\n] 2006.280.07:40:12.87#ibcon#*before write, iclass 11, count 2 2006.280.07:40:12.87#ibcon#enter sib2, iclass 11, count 2 2006.280.07:40:12.87#ibcon#flushed, iclass 11, count 2 2006.280.07:40:12.87#ibcon#about to write, iclass 11, count 2 2006.280.07:40:12.87#ibcon#wrote, iclass 11, count 2 2006.280.07:40:12.87#ibcon#about to read 3, iclass 11, count 2 2006.280.07:40:12.90#ibcon#read 3, iclass 11, count 2 2006.280.07:40:12.90#ibcon#about to read 4, iclass 11, count 2 2006.280.07:40:12.90#ibcon#read 4, iclass 11, count 2 2006.280.07:40:12.90#ibcon#about to read 5, iclass 11, count 2 2006.280.07:40:12.90#ibcon#read 5, iclass 11, count 2 2006.280.07:40:12.90#ibcon#about to read 6, iclass 11, count 2 2006.280.07:40:12.90#ibcon#read 6, iclass 11, count 2 2006.280.07:40:12.90#ibcon#end of sib2, iclass 11, count 2 2006.280.07:40:12.90#ibcon#*after write, iclass 11, count 2 2006.280.07:40:12.90#ibcon#*before return 0, iclass 11, count 2 2006.280.07:40:12.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:12.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:40:12.91#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:40:12.91#ibcon#ireg 7 cls_cnt 0 2006.280.07:40:12.91#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:13.02#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:13.02#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:13.02#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:40:13.02#ibcon#first serial, iclass 11, count 0 2006.280.07:40:13.02#ibcon#enter sib2, iclass 11, count 0 2006.280.07:40:13.02#ibcon#flushed, iclass 11, count 0 2006.280.07:40:13.02#ibcon#about to write, iclass 11, count 0 2006.280.07:40:13.02#ibcon#wrote, iclass 11, count 0 2006.280.07:40:13.02#ibcon#about to read 3, iclass 11, count 0 2006.280.07:40:13.03#ibcon#read 3, iclass 11, count 0 2006.280.07:40:13.03#ibcon#about to read 4, iclass 11, count 0 2006.280.07:40:13.03#ibcon#read 4, iclass 11, count 0 2006.280.07:40:13.03#ibcon#about to read 5, iclass 11, count 0 2006.280.07:40:13.03#ibcon#read 5, iclass 11, count 0 2006.280.07:40:13.03#ibcon#about to read 6, iclass 11, count 0 2006.280.07:40:13.03#ibcon#read 6, iclass 11, count 0 2006.280.07:40:13.03#ibcon#end of sib2, iclass 11, count 0 2006.280.07:40:13.03#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:40:13.03#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:40:13.03#ibcon#[27=USB\r\n] 2006.280.07:40:13.03#ibcon#*before write, iclass 11, count 0 2006.280.07:40:13.04#ibcon#enter sib2, iclass 11, count 0 2006.280.07:40:13.04#ibcon#flushed, iclass 11, count 0 2006.280.07:40:13.04#ibcon#about to write, iclass 11, count 0 2006.280.07:40:13.04#ibcon#wrote, iclass 11, count 0 2006.280.07:40:13.04#ibcon#about to read 3, iclass 11, count 0 2006.280.07:40:13.07#ibcon#read 3, iclass 11, count 0 2006.280.07:40:13.07#ibcon#about to read 4, iclass 11, count 0 2006.280.07:40:13.07#ibcon#read 4, iclass 11, count 0 2006.280.07:40:13.07#ibcon#about to read 5, iclass 11, count 0 2006.280.07:40:13.07#ibcon#read 5, iclass 11, count 0 2006.280.07:40:13.07#ibcon#about to read 6, iclass 11, count 0 2006.280.07:40:13.07#ibcon#read 6, iclass 11, count 0 2006.280.07:40:13.07#ibcon#end of sib2, iclass 11, count 0 2006.280.07:40:13.07#ibcon#*after write, iclass 11, count 0 2006.280.07:40:13.07#ibcon#*before return 0, iclass 11, count 0 2006.280.07:40:13.07#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:13.07#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:40:13.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:40:13.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:40:13.07$vc4f8/vabw=wide 2006.280.07:40:13.07#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:40:13.07#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:40:13.07#ibcon#ireg 8 cls_cnt 0 2006.280.07:40:13.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:13.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:13.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:13.07#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:40:13.07#ibcon#first serial, iclass 13, count 0 2006.280.07:40:13.07#ibcon#enter sib2, iclass 13, count 0 2006.280.07:40:13.07#ibcon#flushed, iclass 13, count 0 2006.280.07:40:13.07#ibcon#about to write, iclass 13, count 0 2006.280.07:40:13.07#ibcon#wrote, iclass 13, count 0 2006.280.07:40:13.07#ibcon#about to read 3, iclass 13, count 0 2006.280.07:40:13.09#ibcon#read 3, iclass 13, count 0 2006.280.07:40:13.09#ibcon#about to read 4, iclass 13, count 0 2006.280.07:40:13.09#ibcon#read 4, iclass 13, count 0 2006.280.07:40:13.09#ibcon#about to read 5, iclass 13, count 0 2006.280.07:40:13.09#ibcon#read 5, iclass 13, count 0 2006.280.07:40:13.09#ibcon#about to read 6, iclass 13, count 0 2006.280.07:40:13.09#ibcon#read 6, iclass 13, count 0 2006.280.07:40:13.09#ibcon#end of sib2, iclass 13, count 0 2006.280.07:40:13.09#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:40:13.09#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:40:13.09#ibcon#[25=BW32\r\n] 2006.280.07:40:13.09#ibcon#*before write, iclass 13, count 0 2006.280.07:40:13.11#ibcon#enter sib2, iclass 13, count 0 2006.280.07:40:13.11#ibcon#flushed, iclass 13, count 0 2006.280.07:40:13.11#ibcon#about to write, iclass 13, count 0 2006.280.07:40:13.11#ibcon#wrote, iclass 13, count 0 2006.280.07:40:13.11#ibcon#about to read 3, iclass 13, count 0 2006.280.07:40:13.14#ibcon#read 3, iclass 13, count 0 2006.280.07:40:13.14#ibcon#about to read 4, iclass 13, count 0 2006.280.07:40:13.14#ibcon#read 4, iclass 13, count 0 2006.280.07:40:13.14#ibcon#about to read 5, iclass 13, count 0 2006.280.07:40:13.14#ibcon#read 5, iclass 13, count 0 2006.280.07:40:13.14#ibcon#about to read 6, iclass 13, count 0 2006.280.07:40:13.14#ibcon#read 6, iclass 13, count 0 2006.280.07:40:13.14#ibcon#end of sib2, iclass 13, count 0 2006.280.07:40:13.14#ibcon#*after write, iclass 13, count 0 2006.280.07:40:13.14#ibcon#*before return 0, iclass 13, count 0 2006.280.07:40:13.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:13.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:40:13.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:40:13.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:40:13.15$vc4f8/vbbw=wide 2006.280.07:40:13.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:40:13.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:40:13.15#ibcon#ireg 8 cls_cnt 0 2006.280.07:40:13.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:40:13.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:40:13.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:40:13.19#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:40:13.19#ibcon#first serial, iclass 15, count 0 2006.280.07:40:13.19#ibcon#enter sib2, iclass 15, count 0 2006.280.07:40:13.19#ibcon#flushed, iclass 15, count 0 2006.280.07:40:13.19#ibcon#about to write, iclass 15, count 0 2006.280.07:40:13.19#ibcon#wrote, iclass 15, count 0 2006.280.07:40:13.19#ibcon#about to read 3, iclass 15, count 0 2006.280.07:40:13.20#ibcon#read 3, iclass 15, count 0 2006.280.07:40:13.20#ibcon#about to read 4, iclass 15, count 0 2006.280.07:40:13.20#ibcon#read 4, iclass 15, count 0 2006.280.07:40:13.20#ibcon#about to read 5, iclass 15, count 0 2006.280.07:40:13.20#ibcon#read 5, iclass 15, count 0 2006.280.07:40:13.20#ibcon#about to read 6, iclass 15, count 0 2006.280.07:40:13.20#ibcon#read 6, iclass 15, count 0 2006.280.07:40:13.20#ibcon#end of sib2, iclass 15, count 0 2006.280.07:40:13.20#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:40:13.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:40:13.22#ibcon#[27=BW32\r\n] 2006.280.07:40:13.22#ibcon#*before write, iclass 15, count 0 2006.280.07:40:13.22#ibcon#enter sib2, iclass 15, count 0 2006.280.07:40:13.22#ibcon#flushed, iclass 15, count 0 2006.280.07:40:13.22#ibcon#about to write, iclass 15, count 0 2006.280.07:40:13.22#ibcon#wrote, iclass 15, count 0 2006.280.07:40:13.22#ibcon#about to read 3, iclass 15, count 0 2006.280.07:40:13.24#ibcon#read 3, iclass 15, count 0 2006.280.07:40:13.24#ibcon#about to read 4, iclass 15, count 0 2006.280.07:40:13.24#ibcon#read 4, iclass 15, count 0 2006.280.07:40:13.24#ibcon#about to read 5, iclass 15, count 0 2006.280.07:40:13.24#ibcon#read 5, iclass 15, count 0 2006.280.07:40:13.24#ibcon#about to read 6, iclass 15, count 0 2006.280.07:40:13.24#ibcon#read 6, iclass 15, count 0 2006.280.07:40:13.24#ibcon#end of sib2, iclass 15, count 0 2006.280.07:40:13.24#ibcon#*after write, iclass 15, count 0 2006.280.07:40:13.24#ibcon#*before return 0, iclass 15, count 0 2006.280.07:40:13.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:40:13.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:40:13.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:40:13.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:40:13.25$4f8m12a/ifd4f 2006.280.07:40:13.25$ifd4f/lo= 2006.280.07:40:13.25$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:40:13.25$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:40:13.25$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:40:13.25$ifd4f/patch= 2006.280.07:40:13.25$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:40:13.25$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:40:13.25$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:40:13.25$4f8m12a/"form=m,16.000,1:2 2006.280.07:40:13.25$4f8m12a/"tpicd 2006.280.07:40:13.25$4f8m12a/echo=off 2006.280.07:40:13.25$4f8m12a/xlog=off 2006.280.07:40:13.25:!2006.280.07:40:40 2006.280.07:40:23.14#trakl#Source acquired 2006.280.07:40:25.15#flagr#flagr/antenna,acquired 2006.280.07:40:40.02:preob 2006.280.07:40:41.15/onsource/TRACKING 2006.280.07:40:41.15:!2006.280.07:40:50 2006.280.07:40:50.02:data_valid=on 2006.280.07:40:50.02:midob 2006.280.07:40:51.15/onsource/TRACKING 2006.280.07:40:51.15/wx/21.67,986.7,58 2006.280.07:40:51.31/cable/+6.4813E-03 2006.280.07:40:52.40/va/01,07,usb,yes,32,34 2006.280.07:40:52.40/va/02,06,usb,yes,30,31 2006.280.07:40:52.40/va/03,06,usb,yes,28,28 2006.280.07:40:52.40/va/04,06,usb,yes,31,33 2006.280.07:40:52.40/va/05,07,usb,yes,28,30 2006.280.07:40:52.40/va/06,06,usb,yes,27,27 2006.280.07:40:52.40/va/07,06,usb,yes,28,27 2006.280.07:40:52.40/va/08,06,usb,yes,30,29 2006.280.07:40:52.63/valo/01,532.99,yes,locked 2006.280.07:40:52.63/valo/02,572.99,yes,locked 2006.280.07:40:52.63/valo/03,672.99,yes,locked 2006.280.07:40:52.63/valo/04,832.99,yes,locked 2006.280.07:40:52.63/valo/05,652.99,yes,locked 2006.280.07:40:52.63/valo/06,772.99,yes,locked 2006.280.07:40:52.63/valo/07,832.99,yes,locked 2006.280.07:40:52.63/valo/08,852.99,yes,locked 2006.280.07:40:53.72/vb/01,04,usb,yes,30,28 2006.280.07:40:53.72/vb/02,05,usb,yes,28,29 2006.280.07:40:53.72/vb/03,04,usb,yes,28,32 2006.280.07:40:53.72/vb/04,04,usb,yes,29,29 2006.280.07:40:53.72/vb/05,04,usb,yes,27,31 2006.280.07:40:53.72/vb/06,04,usb,yes,27,31 2006.280.07:40:53.72/vb/07,04,usb,yes,30,30 2006.280.07:40:53.72/vb/08,04,usb,yes,27,31 2006.280.07:40:53.95/vblo/01,632.99,yes,locked 2006.280.07:40:53.95/vblo/02,640.99,yes,locked 2006.280.07:40:53.95/vblo/03,656.99,yes,locked 2006.280.07:40:53.95/vblo/04,712.99,yes,locked 2006.280.07:40:53.95/vblo/05,744.99,yes,locked 2006.280.07:40:53.95/vblo/06,752.99,yes,locked 2006.280.07:40:53.95/vblo/07,734.99,yes,locked 2006.280.07:40:53.95/vblo/08,744.99,yes,locked 2006.280.07:40:54.10/vabw/8 2006.280.07:40:54.25/vbbw/8 2006.280.07:40:54.34/xfe/off,on,12.2 2006.280.07:40:54.72/ifatt/23,28,28,28 2006.280.07:40:55.07/fmout-gps/S +3.02E-07 2006.280.07:40:55.09:!2006.280.07:41:50 2006.280.07:41:50.01:data_valid=off 2006.280.07:41:50.02:postob 2006.280.07:41:50.19/cable/+6.4829E-03 2006.280.07:41:50.20/wx/21.60,986.8,59 2006.280.07:41:51.07/fmout-gps/S +3.02E-07 2006.280.07:41:51.08:scan_name=280-0742,k06280,60 2006.280.07:41:51.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.280.07:41:52.15#flagr#flagr/antenna,new-source 2006.280.07:41:52.15:checkk5 2006.280.07:41:52.64/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:41:53.01/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:41:53.39/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:41:53.83/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:41:54.20/chk_obsdata//k5ts1/T2800740??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:41:54.70/chk_obsdata//k5ts2/T2800740??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:41:55.07/chk_obsdata//k5ts3/T2800740??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:41:55.45/chk_obsdata//k5ts4/T2800740??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:41:56.15/k5log//k5ts1_log_newline 2006.280.07:41:56.95/k5log//k5ts2_log_newline 2006.280.07:41:57.69/k5log//k5ts3_log_newline 2006.280.07:41:58.40/k5log//k5ts4_log_newline 2006.280.07:41:58.42/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:41:58.42:4f8m12a=1 2006.280.07:41:58.42$4f8m12a/echo=on 2006.280.07:41:58.43$4f8m12a/pcalon 2006.280.07:41:58.43$pcalon/"no phase cal control is implemented here 2006.280.07:41:58.43$4f8m12a/"tpicd=stop 2006.280.07:41:58.43$4f8m12a/vc4f8 2006.280.07:41:58.43$vc4f8/valo=1,532.99 2006.280.07:41:58.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:41:58.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:41:58.45#ibcon#ireg 17 cls_cnt 0 2006.280.07:41:58.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:41:58.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:41:58.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:41:58.45#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:41:58.45#ibcon#first serial, iclass 26, count 0 2006.280.07:41:58.45#ibcon#enter sib2, iclass 26, count 0 2006.280.07:41:58.45#ibcon#flushed, iclass 26, count 0 2006.280.07:41:58.45#ibcon#about to write, iclass 26, count 0 2006.280.07:41:58.45#ibcon#wrote, iclass 26, count 0 2006.280.07:41:58.45#ibcon#about to read 3, iclass 26, count 0 2006.280.07:41:58.47#ibcon#read 3, iclass 26, count 0 2006.280.07:41:58.47#ibcon#about to read 4, iclass 26, count 0 2006.280.07:41:58.47#ibcon#read 4, iclass 26, count 0 2006.280.07:41:58.47#ibcon#about to read 5, iclass 26, count 0 2006.280.07:41:58.47#ibcon#read 5, iclass 26, count 0 2006.280.07:41:58.47#ibcon#about to read 6, iclass 26, count 0 2006.280.07:41:58.47#ibcon#read 6, iclass 26, count 0 2006.280.07:41:58.47#ibcon#end of sib2, iclass 26, count 0 2006.280.07:41:58.47#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:41:58.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:41:58.47#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:41:58.47#ibcon#*before write, iclass 26, count 0 2006.280.07:41:58.47#ibcon#enter sib2, iclass 26, count 0 2006.280.07:41:58.47#ibcon#flushed, iclass 26, count 0 2006.280.07:41:58.47#ibcon#about to write, iclass 26, count 0 2006.280.07:41:58.47#ibcon#wrote, iclass 26, count 0 2006.280.07:41:58.47#ibcon#about to read 3, iclass 26, count 0 2006.280.07:41:58.51#ibcon#read 3, iclass 26, count 0 2006.280.07:41:58.51#ibcon#about to read 4, iclass 26, count 0 2006.280.07:41:58.51#ibcon#read 4, iclass 26, count 0 2006.280.07:41:58.51#ibcon#about to read 5, iclass 26, count 0 2006.280.07:41:58.51#ibcon#read 5, iclass 26, count 0 2006.280.07:41:58.51#ibcon#about to read 6, iclass 26, count 0 2006.280.07:41:58.51#ibcon#read 6, iclass 26, count 0 2006.280.07:41:58.51#ibcon#end of sib2, iclass 26, count 0 2006.280.07:41:58.51#ibcon#*after write, iclass 26, count 0 2006.280.07:41:58.51#ibcon#*before return 0, iclass 26, count 0 2006.280.07:41:58.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:41:58.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:41:58.51#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:41:58.51#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:41:58.51$vc4f8/va=1,7 2006.280.07:41:58.52#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:41:58.52#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:41:58.52#ibcon#ireg 11 cls_cnt 2 2006.280.07:41:58.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:41:58.52#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:41:58.52#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:41:58.52#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:41:58.52#ibcon#first serial, iclass 28, count 2 2006.280.07:41:58.52#ibcon#enter sib2, iclass 28, count 2 2006.280.07:41:58.52#ibcon#flushed, iclass 28, count 2 2006.280.07:41:58.52#ibcon#about to write, iclass 28, count 2 2006.280.07:41:58.52#ibcon#wrote, iclass 28, count 2 2006.280.07:41:58.52#ibcon#about to read 3, iclass 28, count 2 2006.280.07:41:58.53#ibcon#read 3, iclass 28, count 2 2006.280.07:41:58.53#ibcon#about to read 4, iclass 28, count 2 2006.280.07:41:58.53#ibcon#read 4, iclass 28, count 2 2006.280.07:41:58.53#ibcon#about to read 5, iclass 28, count 2 2006.280.07:41:58.53#ibcon#read 5, iclass 28, count 2 2006.280.07:41:58.53#ibcon#about to read 6, iclass 28, count 2 2006.280.07:41:58.53#ibcon#read 6, iclass 28, count 2 2006.280.07:41:58.53#ibcon#end of sib2, iclass 28, count 2 2006.280.07:41:58.53#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:41:58.53#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:41:58.53#ibcon#[25=AT01-07\r\n] 2006.280.07:41:58.53#ibcon#*before write, iclass 28, count 2 2006.280.07:41:58.53#ibcon#enter sib2, iclass 28, count 2 2006.280.07:41:58.53#ibcon#flushed, iclass 28, count 2 2006.280.07:41:58.53#ibcon#about to write, iclass 28, count 2 2006.280.07:41:58.53#ibcon#wrote, iclass 28, count 2 2006.280.07:41:58.53#ibcon#about to read 3, iclass 28, count 2 2006.280.07:41:58.57#ibcon#read 3, iclass 28, count 2 2006.280.07:41:58.57#ibcon#about to read 4, iclass 28, count 2 2006.280.07:41:58.57#ibcon#read 4, iclass 28, count 2 2006.280.07:41:58.57#ibcon#about to read 5, iclass 28, count 2 2006.280.07:41:58.57#ibcon#read 5, iclass 28, count 2 2006.280.07:41:58.57#ibcon#about to read 6, iclass 28, count 2 2006.280.07:41:58.57#ibcon#read 6, iclass 28, count 2 2006.280.07:41:58.57#ibcon#end of sib2, iclass 28, count 2 2006.280.07:41:58.57#ibcon#*after write, iclass 28, count 2 2006.280.07:41:58.57#ibcon#*before return 0, iclass 28, count 2 2006.280.07:41:58.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:41:58.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:41:58.57#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:41:58.57#ibcon#ireg 7 cls_cnt 0 2006.280.07:41:58.57#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:41:58.68#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:41:58.68#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:41:58.68#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:41:58.68#ibcon#first serial, iclass 28, count 0 2006.280.07:41:58.68#ibcon#enter sib2, iclass 28, count 0 2006.280.07:41:58.68#ibcon#flushed, iclass 28, count 0 2006.280.07:41:58.68#ibcon#about to write, iclass 28, count 0 2006.280.07:41:58.68#ibcon#wrote, iclass 28, count 0 2006.280.07:41:58.68#ibcon#about to read 3, iclass 28, count 0 2006.280.07:41:58.71#ibcon#read 3, iclass 28, count 0 2006.280.07:41:58.71#ibcon#about to read 4, iclass 28, count 0 2006.280.07:41:58.71#ibcon#read 4, iclass 28, count 0 2006.280.07:41:58.71#ibcon#about to read 5, iclass 28, count 0 2006.280.07:41:58.71#ibcon#read 5, iclass 28, count 0 2006.280.07:41:58.71#ibcon#about to read 6, iclass 28, count 0 2006.280.07:41:58.71#ibcon#read 6, iclass 28, count 0 2006.280.07:41:58.71#ibcon#end of sib2, iclass 28, count 0 2006.280.07:41:58.71#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:41:58.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:41:58.71#ibcon#[25=USB\r\n] 2006.280.07:41:58.71#ibcon#*before write, iclass 28, count 0 2006.280.07:41:58.71#ibcon#enter sib2, iclass 28, count 0 2006.280.07:41:58.71#ibcon#flushed, iclass 28, count 0 2006.280.07:41:58.71#ibcon#about to write, iclass 28, count 0 2006.280.07:41:58.71#ibcon#wrote, iclass 28, count 0 2006.280.07:41:58.71#ibcon#about to read 3, iclass 28, count 0 2006.280.07:41:58.73#ibcon#read 3, iclass 28, count 0 2006.280.07:41:58.73#ibcon#about to read 4, iclass 28, count 0 2006.280.07:41:58.73#ibcon#read 4, iclass 28, count 0 2006.280.07:41:58.73#ibcon#about to read 5, iclass 28, count 0 2006.280.07:41:58.73#ibcon#read 5, iclass 28, count 0 2006.280.07:41:58.73#ibcon#about to read 6, iclass 28, count 0 2006.280.07:41:58.73#ibcon#read 6, iclass 28, count 0 2006.280.07:41:58.73#ibcon#end of sib2, iclass 28, count 0 2006.280.07:41:58.73#ibcon#*after write, iclass 28, count 0 2006.280.07:41:58.73#ibcon#*before return 0, iclass 28, count 0 2006.280.07:41:58.73#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:41:58.73#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:41:58.73#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:41:58.73#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:41:58.73$vc4f8/valo=2,572.99 2006.280.07:41:58.74#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:41:58.74#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:41:58.74#ibcon#ireg 17 cls_cnt 0 2006.280.07:41:58.74#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:41:58.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:41:58.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:41:58.74#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:41:58.74#ibcon#first serial, iclass 30, count 0 2006.280.07:41:58.74#ibcon#enter sib2, iclass 30, count 0 2006.280.07:41:58.74#ibcon#flushed, iclass 30, count 0 2006.280.07:41:58.74#ibcon#about to write, iclass 30, count 0 2006.280.07:41:58.74#ibcon#wrote, iclass 30, count 0 2006.280.07:41:58.74#ibcon#about to read 3, iclass 30, count 0 2006.280.07:41:58.75#ibcon#read 3, iclass 30, count 0 2006.280.07:41:58.75#ibcon#about to read 4, iclass 30, count 0 2006.280.07:41:58.75#ibcon#read 4, iclass 30, count 0 2006.280.07:41:58.75#ibcon#about to read 5, iclass 30, count 0 2006.280.07:41:58.75#ibcon#read 5, iclass 30, count 0 2006.280.07:41:58.75#ibcon#about to read 6, iclass 30, count 0 2006.280.07:41:58.75#ibcon#read 6, iclass 30, count 0 2006.280.07:41:58.75#ibcon#end of sib2, iclass 30, count 0 2006.280.07:41:58.75#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:41:58.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:41:58.75#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:41:58.75#ibcon#*before write, iclass 30, count 0 2006.280.07:41:58.75#ibcon#enter sib2, iclass 30, count 0 2006.280.07:41:58.75#ibcon#flushed, iclass 30, count 0 2006.280.07:41:58.75#ibcon#about to write, iclass 30, count 0 2006.280.07:41:58.75#ibcon#wrote, iclass 30, count 0 2006.280.07:41:58.75#ibcon#about to read 3, iclass 30, count 0 2006.280.07:41:58.80#ibcon#read 3, iclass 30, count 0 2006.280.07:41:58.80#ibcon#about to read 4, iclass 30, count 0 2006.280.07:41:58.80#ibcon#read 4, iclass 30, count 0 2006.280.07:41:58.80#ibcon#about to read 5, iclass 30, count 0 2006.280.07:41:58.80#ibcon#read 5, iclass 30, count 0 2006.280.07:41:58.80#ibcon#about to read 6, iclass 30, count 0 2006.280.07:41:58.80#ibcon#read 6, iclass 30, count 0 2006.280.07:41:58.80#ibcon#end of sib2, iclass 30, count 0 2006.280.07:41:58.80#ibcon#*after write, iclass 30, count 0 2006.280.07:41:58.80#ibcon#*before return 0, iclass 30, count 0 2006.280.07:41:58.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:41:58.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:41:58.80#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:41:58.80#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:41:58.80$vc4f8/va=2,6 2006.280.07:41:58.80#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:41:58.80#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:41:58.80#ibcon#ireg 11 cls_cnt 2 2006.280.07:41:58.80#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:41:58.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:41:58.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:41:58.84#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:41:58.84#ibcon#first serial, iclass 32, count 2 2006.280.07:41:58.84#ibcon#enter sib2, iclass 32, count 2 2006.280.07:41:58.84#ibcon#flushed, iclass 32, count 2 2006.280.07:41:58.84#ibcon#about to write, iclass 32, count 2 2006.280.07:41:58.84#ibcon#wrote, iclass 32, count 2 2006.280.07:41:58.84#ibcon#about to read 3, iclass 32, count 2 2006.280.07:41:58.86#ibcon#read 3, iclass 32, count 2 2006.280.07:41:58.86#ibcon#about to read 4, iclass 32, count 2 2006.280.07:41:58.86#ibcon#read 4, iclass 32, count 2 2006.280.07:41:58.86#ibcon#about to read 5, iclass 32, count 2 2006.280.07:41:58.86#ibcon#read 5, iclass 32, count 2 2006.280.07:41:58.86#ibcon#about to read 6, iclass 32, count 2 2006.280.07:41:58.86#ibcon#read 6, iclass 32, count 2 2006.280.07:41:58.86#ibcon#end of sib2, iclass 32, count 2 2006.280.07:41:58.86#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:41:58.86#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:41:58.86#ibcon#[25=AT02-06\r\n] 2006.280.07:41:58.86#ibcon#*before write, iclass 32, count 2 2006.280.07:41:58.86#ibcon#enter sib2, iclass 32, count 2 2006.280.07:41:58.86#ibcon#flushed, iclass 32, count 2 2006.280.07:41:58.86#ibcon#about to write, iclass 32, count 2 2006.280.07:41:58.86#ibcon#wrote, iclass 32, count 2 2006.280.07:41:58.86#ibcon#about to read 3, iclass 32, count 2 2006.280.07:41:58.89#ibcon#read 3, iclass 32, count 2 2006.280.07:41:58.89#ibcon#about to read 4, iclass 32, count 2 2006.280.07:41:58.89#ibcon#read 4, iclass 32, count 2 2006.280.07:41:58.89#ibcon#about to read 5, iclass 32, count 2 2006.280.07:41:58.89#ibcon#read 5, iclass 32, count 2 2006.280.07:41:58.89#ibcon#about to read 6, iclass 32, count 2 2006.280.07:41:58.89#ibcon#read 6, iclass 32, count 2 2006.280.07:41:58.89#ibcon#end of sib2, iclass 32, count 2 2006.280.07:41:58.89#ibcon#*after write, iclass 32, count 2 2006.280.07:41:58.89#ibcon#*before return 0, iclass 32, count 2 2006.280.07:41:58.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:41:58.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:41:58.89#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:41:58.89#ibcon#ireg 7 cls_cnt 0 2006.280.07:41:58.89#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:41:59.02#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:41:59.02#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:41:59.02#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:41:59.02#ibcon#first serial, iclass 32, count 0 2006.280.07:41:59.02#ibcon#enter sib2, iclass 32, count 0 2006.280.07:41:59.02#ibcon#flushed, iclass 32, count 0 2006.280.07:41:59.02#ibcon#about to write, iclass 32, count 0 2006.280.07:41:59.02#ibcon#wrote, iclass 32, count 0 2006.280.07:41:59.02#ibcon#about to read 3, iclass 32, count 0 2006.280.07:41:59.03#ibcon#read 3, iclass 32, count 0 2006.280.07:41:59.03#ibcon#about to read 4, iclass 32, count 0 2006.280.07:41:59.03#ibcon#read 4, iclass 32, count 0 2006.280.07:41:59.03#ibcon#about to read 5, iclass 32, count 0 2006.280.07:41:59.03#ibcon#read 5, iclass 32, count 0 2006.280.07:41:59.03#ibcon#about to read 6, iclass 32, count 0 2006.280.07:41:59.03#ibcon#read 6, iclass 32, count 0 2006.280.07:41:59.03#ibcon#end of sib2, iclass 32, count 0 2006.280.07:41:59.03#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:41:59.03#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:41:59.03#ibcon#[25=USB\r\n] 2006.280.07:41:59.03#ibcon#*before write, iclass 32, count 0 2006.280.07:41:59.03#ibcon#enter sib2, iclass 32, count 0 2006.280.07:41:59.03#ibcon#flushed, iclass 32, count 0 2006.280.07:41:59.03#ibcon#about to write, iclass 32, count 0 2006.280.07:41:59.03#ibcon#wrote, iclass 32, count 0 2006.280.07:41:59.03#ibcon#about to read 3, iclass 32, count 0 2006.280.07:41:59.06#ibcon#read 3, iclass 32, count 0 2006.280.07:41:59.06#ibcon#about to read 4, iclass 32, count 0 2006.280.07:41:59.06#ibcon#read 4, iclass 32, count 0 2006.280.07:41:59.06#ibcon#about to read 5, iclass 32, count 0 2006.280.07:41:59.06#ibcon#read 5, iclass 32, count 0 2006.280.07:41:59.06#ibcon#about to read 6, iclass 32, count 0 2006.280.07:41:59.06#ibcon#read 6, iclass 32, count 0 2006.280.07:41:59.06#ibcon#end of sib2, iclass 32, count 0 2006.280.07:41:59.06#ibcon#*after write, iclass 32, count 0 2006.280.07:41:59.06#ibcon#*before return 0, iclass 32, count 0 2006.280.07:41:59.06#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:41:59.06#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:41:59.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:41:59.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:41:59.06$vc4f8/valo=3,672.99 2006.280.07:41:59.07#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:41:59.07#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:41:59.07#ibcon#ireg 17 cls_cnt 0 2006.280.07:41:59.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:41:59.07#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:41:59.07#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:41:59.07#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:41:59.07#ibcon#first serial, iclass 34, count 0 2006.280.07:41:59.07#ibcon#enter sib2, iclass 34, count 0 2006.280.07:41:59.07#ibcon#flushed, iclass 34, count 0 2006.280.07:41:59.07#ibcon#about to write, iclass 34, count 0 2006.280.07:41:59.07#ibcon#wrote, iclass 34, count 0 2006.280.07:41:59.07#ibcon#about to read 3, iclass 34, count 0 2006.280.07:41:59.08#ibcon#read 3, iclass 34, count 0 2006.280.07:41:59.08#ibcon#about to read 4, iclass 34, count 0 2006.280.07:41:59.08#ibcon#read 4, iclass 34, count 0 2006.280.07:41:59.08#ibcon#about to read 5, iclass 34, count 0 2006.280.07:41:59.08#ibcon#read 5, iclass 34, count 0 2006.280.07:41:59.08#ibcon#about to read 6, iclass 34, count 0 2006.280.07:41:59.08#ibcon#read 6, iclass 34, count 0 2006.280.07:41:59.08#ibcon#end of sib2, iclass 34, count 0 2006.280.07:41:59.08#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:41:59.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:41:59.08#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:41:59.08#ibcon#*before write, iclass 34, count 0 2006.280.07:41:59.08#ibcon#enter sib2, iclass 34, count 0 2006.280.07:41:59.08#ibcon#flushed, iclass 34, count 0 2006.280.07:41:59.08#ibcon#about to write, iclass 34, count 0 2006.280.07:41:59.08#ibcon#wrote, iclass 34, count 0 2006.280.07:41:59.08#ibcon#about to read 3, iclass 34, count 0 2006.280.07:41:59.12#ibcon#read 3, iclass 34, count 0 2006.280.07:41:59.12#ibcon#about to read 4, iclass 34, count 0 2006.280.07:41:59.12#ibcon#read 4, iclass 34, count 0 2006.280.07:41:59.12#ibcon#about to read 5, iclass 34, count 0 2006.280.07:41:59.12#ibcon#read 5, iclass 34, count 0 2006.280.07:41:59.12#ibcon#about to read 6, iclass 34, count 0 2006.280.07:41:59.12#ibcon#read 6, iclass 34, count 0 2006.280.07:41:59.12#ibcon#end of sib2, iclass 34, count 0 2006.280.07:41:59.12#ibcon#*after write, iclass 34, count 0 2006.280.07:41:59.12#ibcon#*before return 0, iclass 34, count 0 2006.280.07:41:59.12#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:41:59.12#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:41:59.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:41:59.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:41:59.12$vc4f8/va=3,6 2006.280.07:41:59.13#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:41:59.13#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:41:59.13#ibcon#ireg 11 cls_cnt 2 2006.280.07:41:59.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:41:59.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:41:59.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:41:59.17#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:41:59.17#ibcon#first serial, iclass 36, count 2 2006.280.07:41:59.17#ibcon#enter sib2, iclass 36, count 2 2006.280.07:41:59.17#ibcon#flushed, iclass 36, count 2 2006.280.07:41:59.17#ibcon#about to write, iclass 36, count 2 2006.280.07:41:59.17#ibcon#wrote, iclass 36, count 2 2006.280.07:41:59.17#ibcon#about to read 3, iclass 36, count 2 2006.280.07:41:59.19#ibcon#read 3, iclass 36, count 2 2006.280.07:41:59.20#ibcon#about to read 4, iclass 36, count 2 2006.280.07:41:59.20#ibcon#read 4, iclass 36, count 2 2006.280.07:41:59.20#ibcon#about to read 5, iclass 36, count 2 2006.280.07:41:59.20#ibcon#read 5, iclass 36, count 2 2006.280.07:41:59.20#ibcon#about to read 6, iclass 36, count 2 2006.280.07:41:59.20#ibcon#read 6, iclass 36, count 2 2006.280.07:41:59.20#ibcon#end of sib2, iclass 36, count 2 2006.280.07:41:59.20#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:41:59.20#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:41:59.20#ibcon#[25=AT03-06\r\n] 2006.280.07:41:59.20#ibcon#*before write, iclass 36, count 2 2006.280.07:41:59.20#ibcon#enter sib2, iclass 36, count 2 2006.280.07:41:59.20#ibcon#flushed, iclass 36, count 2 2006.280.07:41:59.20#ibcon#about to write, iclass 36, count 2 2006.280.07:41:59.20#ibcon#wrote, iclass 36, count 2 2006.280.07:41:59.20#ibcon#about to read 3, iclass 36, count 2 2006.280.07:41:59.22#ibcon#read 3, iclass 36, count 2 2006.280.07:41:59.22#ibcon#about to read 4, iclass 36, count 2 2006.280.07:41:59.22#ibcon#read 4, iclass 36, count 2 2006.280.07:41:59.22#ibcon#about to read 5, iclass 36, count 2 2006.280.07:41:59.22#ibcon#read 5, iclass 36, count 2 2006.280.07:41:59.22#ibcon#about to read 6, iclass 36, count 2 2006.280.07:41:59.22#ibcon#read 6, iclass 36, count 2 2006.280.07:41:59.22#ibcon#end of sib2, iclass 36, count 2 2006.280.07:41:59.22#ibcon#*after write, iclass 36, count 2 2006.280.07:41:59.22#ibcon#*before return 0, iclass 36, count 2 2006.280.07:41:59.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:41:59.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:41:59.22#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:41:59.22#ibcon#ireg 7 cls_cnt 0 2006.280.07:41:59.22#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:41:59.34#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:41:59.34#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:41:59.34#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:41:59.34#ibcon#first serial, iclass 36, count 0 2006.280.07:41:59.34#ibcon#enter sib2, iclass 36, count 0 2006.280.07:41:59.34#ibcon#flushed, iclass 36, count 0 2006.280.07:41:59.34#ibcon#about to write, iclass 36, count 0 2006.280.07:41:59.34#ibcon#wrote, iclass 36, count 0 2006.280.07:41:59.34#ibcon#about to read 3, iclass 36, count 0 2006.280.07:41:59.36#ibcon#read 3, iclass 36, count 0 2006.280.07:41:59.36#ibcon#about to read 4, iclass 36, count 0 2006.280.07:41:59.36#ibcon#read 4, iclass 36, count 0 2006.280.07:41:59.36#ibcon#about to read 5, iclass 36, count 0 2006.280.07:41:59.36#ibcon#read 5, iclass 36, count 0 2006.280.07:41:59.36#ibcon#about to read 6, iclass 36, count 0 2006.280.07:41:59.36#ibcon#read 6, iclass 36, count 0 2006.280.07:41:59.36#ibcon#end of sib2, iclass 36, count 0 2006.280.07:41:59.36#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:41:59.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:41:59.36#ibcon#[25=USB\r\n] 2006.280.07:41:59.36#ibcon#*before write, iclass 36, count 0 2006.280.07:41:59.36#ibcon#enter sib2, iclass 36, count 0 2006.280.07:41:59.36#ibcon#flushed, iclass 36, count 0 2006.280.07:41:59.36#ibcon#about to write, iclass 36, count 0 2006.280.07:41:59.36#ibcon#wrote, iclass 36, count 0 2006.280.07:41:59.36#ibcon#about to read 3, iclass 36, count 0 2006.280.07:41:59.39#ibcon#read 3, iclass 36, count 0 2006.280.07:41:59.39#ibcon#about to read 4, iclass 36, count 0 2006.280.07:41:59.39#ibcon#read 4, iclass 36, count 0 2006.280.07:41:59.39#ibcon#about to read 5, iclass 36, count 0 2006.280.07:41:59.39#ibcon#read 5, iclass 36, count 0 2006.280.07:41:59.39#ibcon#about to read 6, iclass 36, count 0 2006.280.07:41:59.39#ibcon#read 6, iclass 36, count 0 2006.280.07:41:59.39#ibcon#end of sib2, iclass 36, count 0 2006.280.07:41:59.39#ibcon#*after write, iclass 36, count 0 2006.280.07:41:59.39#ibcon#*before return 0, iclass 36, count 0 2006.280.07:41:59.39#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:41:59.39#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:41:59.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:41:59.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:41:59.39$vc4f8/valo=4,832.99 2006.280.07:41:59.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:41:59.40#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:41:59.40#ibcon#ireg 17 cls_cnt 0 2006.280.07:41:59.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:41:59.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:41:59.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:41:59.40#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:41:59.40#ibcon#first serial, iclass 38, count 0 2006.280.07:41:59.40#ibcon#enter sib2, iclass 38, count 0 2006.280.07:41:59.40#ibcon#flushed, iclass 38, count 0 2006.280.07:41:59.40#ibcon#about to write, iclass 38, count 0 2006.280.07:41:59.40#ibcon#wrote, iclass 38, count 0 2006.280.07:41:59.40#ibcon#about to read 3, iclass 38, count 0 2006.280.07:41:59.41#ibcon#read 3, iclass 38, count 0 2006.280.07:41:59.41#ibcon#about to read 4, iclass 38, count 0 2006.280.07:41:59.41#ibcon#read 4, iclass 38, count 0 2006.280.07:41:59.41#ibcon#about to read 5, iclass 38, count 0 2006.280.07:41:59.41#ibcon#read 5, iclass 38, count 0 2006.280.07:41:59.41#ibcon#about to read 6, iclass 38, count 0 2006.280.07:41:59.41#ibcon#read 6, iclass 38, count 0 2006.280.07:41:59.41#ibcon#end of sib2, iclass 38, count 0 2006.280.07:41:59.41#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:41:59.41#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:41:59.41#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:41:59.41#ibcon#*before write, iclass 38, count 0 2006.280.07:41:59.41#ibcon#enter sib2, iclass 38, count 0 2006.280.07:41:59.41#ibcon#flushed, iclass 38, count 0 2006.280.07:41:59.41#ibcon#about to write, iclass 38, count 0 2006.280.07:41:59.41#ibcon#wrote, iclass 38, count 0 2006.280.07:41:59.41#ibcon#about to read 3, iclass 38, count 0 2006.280.07:41:59.45#ibcon#read 3, iclass 38, count 0 2006.280.07:41:59.45#ibcon#about to read 4, iclass 38, count 0 2006.280.07:41:59.45#ibcon#read 4, iclass 38, count 0 2006.280.07:41:59.45#ibcon#about to read 5, iclass 38, count 0 2006.280.07:41:59.45#ibcon#read 5, iclass 38, count 0 2006.280.07:41:59.45#ibcon#about to read 6, iclass 38, count 0 2006.280.07:41:59.45#ibcon#read 6, iclass 38, count 0 2006.280.07:41:59.45#ibcon#end of sib2, iclass 38, count 0 2006.280.07:41:59.45#ibcon#*after write, iclass 38, count 0 2006.280.07:41:59.45#ibcon#*before return 0, iclass 38, count 0 2006.280.07:41:59.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:41:59.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:41:59.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:41:59.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:41:59.45$vc4f8/va=4,6 2006.280.07:41:59.45#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:41:59.45#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:41:59.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:41:59.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:41:59.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:41:59.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:41:59.50#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:41:59.50#ibcon#first serial, iclass 40, count 2 2006.280.07:41:59.50#ibcon#enter sib2, iclass 40, count 2 2006.280.07:41:59.50#ibcon#flushed, iclass 40, count 2 2006.280.07:41:59.50#ibcon#about to write, iclass 40, count 2 2006.280.07:41:59.50#ibcon#wrote, iclass 40, count 2 2006.280.07:41:59.50#ibcon#about to read 3, iclass 40, count 2 2006.280.07:41:59.52#ibcon#read 3, iclass 40, count 2 2006.280.07:41:59.52#ibcon#about to read 4, iclass 40, count 2 2006.280.07:41:59.52#ibcon#read 4, iclass 40, count 2 2006.280.07:41:59.52#ibcon#about to read 5, iclass 40, count 2 2006.280.07:41:59.52#ibcon#read 5, iclass 40, count 2 2006.280.07:41:59.52#ibcon#about to read 6, iclass 40, count 2 2006.280.07:41:59.52#ibcon#read 6, iclass 40, count 2 2006.280.07:41:59.52#ibcon#end of sib2, iclass 40, count 2 2006.280.07:41:59.52#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:41:59.52#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:41:59.52#ibcon#[25=AT04-06\r\n] 2006.280.07:41:59.52#ibcon#*before write, iclass 40, count 2 2006.280.07:41:59.52#ibcon#enter sib2, iclass 40, count 2 2006.280.07:41:59.52#ibcon#flushed, iclass 40, count 2 2006.280.07:41:59.52#ibcon#about to write, iclass 40, count 2 2006.280.07:41:59.52#ibcon#wrote, iclass 40, count 2 2006.280.07:41:59.52#ibcon#about to read 3, iclass 40, count 2 2006.280.07:41:59.55#ibcon#read 3, iclass 40, count 2 2006.280.07:41:59.55#ibcon#about to read 4, iclass 40, count 2 2006.280.07:41:59.55#ibcon#read 4, iclass 40, count 2 2006.280.07:41:59.55#ibcon#about to read 5, iclass 40, count 2 2006.280.07:41:59.55#ibcon#read 5, iclass 40, count 2 2006.280.07:41:59.55#ibcon#about to read 6, iclass 40, count 2 2006.280.07:41:59.55#ibcon#read 6, iclass 40, count 2 2006.280.07:41:59.55#ibcon#end of sib2, iclass 40, count 2 2006.280.07:41:59.55#ibcon#*after write, iclass 40, count 2 2006.280.07:41:59.55#ibcon#*before return 0, iclass 40, count 2 2006.280.07:41:59.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:41:59.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:41:59.55#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:41:59.55#ibcon#ireg 7 cls_cnt 0 2006.280.07:41:59.55#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:41:59.67#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:41:59.67#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:41:59.67#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:41:59.67#ibcon#first serial, iclass 40, count 0 2006.280.07:41:59.67#ibcon#enter sib2, iclass 40, count 0 2006.280.07:41:59.67#ibcon#flushed, iclass 40, count 0 2006.280.07:41:59.67#ibcon#about to write, iclass 40, count 0 2006.280.07:41:59.67#ibcon#wrote, iclass 40, count 0 2006.280.07:41:59.67#ibcon#about to read 3, iclass 40, count 0 2006.280.07:41:59.69#ibcon#read 3, iclass 40, count 0 2006.280.07:41:59.69#ibcon#about to read 4, iclass 40, count 0 2006.280.07:41:59.69#ibcon#read 4, iclass 40, count 0 2006.280.07:41:59.69#ibcon#about to read 5, iclass 40, count 0 2006.280.07:41:59.69#ibcon#read 5, iclass 40, count 0 2006.280.07:41:59.69#ibcon#about to read 6, iclass 40, count 0 2006.280.07:41:59.69#ibcon#read 6, iclass 40, count 0 2006.280.07:41:59.69#ibcon#end of sib2, iclass 40, count 0 2006.280.07:41:59.69#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:41:59.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:41:59.69#ibcon#[25=USB\r\n] 2006.280.07:41:59.69#ibcon#*before write, iclass 40, count 0 2006.280.07:41:59.69#ibcon#enter sib2, iclass 40, count 0 2006.280.07:41:59.69#ibcon#flushed, iclass 40, count 0 2006.280.07:41:59.69#ibcon#about to write, iclass 40, count 0 2006.280.07:41:59.69#ibcon#wrote, iclass 40, count 0 2006.280.07:41:59.69#ibcon#about to read 3, iclass 40, count 0 2006.280.07:41:59.73#ibcon#read 3, iclass 40, count 0 2006.280.07:41:59.73#ibcon#about to read 4, iclass 40, count 0 2006.280.07:41:59.73#ibcon#read 4, iclass 40, count 0 2006.280.07:41:59.73#ibcon#about to read 5, iclass 40, count 0 2006.280.07:41:59.73#ibcon#read 5, iclass 40, count 0 2006.280.07:41:59.73#ibcon#about to read 6, iclass 40, count 0 2006.280.07:41:59.73#ibcon#read 6, iclass 40, count 0 2006.280.07:41:59.73#ibcon#end of sib2, iclass 40, count 0 2006.280.07:41:59.73#ibcon#*after write, iclass 40, count 0 2006.280.07:41:59.73#ibcon#*before return 0, iclass 40, count 0 2006.280.07:41:59.73#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:41:59.73#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:41:59.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:41:59.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:41:59.73$vc4f8/valo=5,652.99 2006.280.07:41:59.73#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:41:59.73#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:41:59.73#ibcon#ireg 17 cls_cnt 0 2006.280.07:41:59.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:41:59.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:41:59.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:41:59.73#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:41:59.73#ibcon#first serial, iclass 4, count 0 2006.280.07:41:59.73#ibcon#enter sib2, iclass 4, count 0 2006.280.07:41:59.73#ibcon#flushed, iclass 4, count 0 2006.280.07:41:59.73#ibcon#about to write, iclass 4, count 0 2006.280.07:41:59.73#ibcon#wrote, iclass 4, count 0 2006.280.07:41:59.73#ibcon#about to read 3, iclass 4, count 0 2006.280.07:41:59.74#ibcon#read 3, iclass 4, count 0 2006.280.07:41:59.74#ibcon#about to read 4, iclass 4, count 0 2006.280.07:41:59.74#ibcon#read 4, iclass 4, count 0 2006.280.07:41:59.74#ibcon#about to read 5, iclass 4, count 0 2006.280.07:41:59.74#ibcon#read 5, iclass 4, count 0 2006.280.07:41:59.74#ibcon#about to read 6, iclass 4, count 0 2006.280.07:41:59.74#ibcon#read 6, iclass 4, count 0 2006.280.07:41:59.74#ibcon#end of sib2, iclass 4, count 0 2006.280.07:41:59.74#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:41:59.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:41:59.74#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:41:59.74#ibcon#*before write, iclass 4, count 0 2006.280.07:41:59.74#ibcon#enter sib2, iclass 4, count 0 2006.280.07:41:59.74#ibcon#flushed, iclass 4, count 0 2006.280.07:41:59.74#ibcon#about to write, iclass 4, count 0 2006.280.07:41:59.74#ibcon#wrote, iclass 4, count 0 2006.280.07:41:59.74#ibcon#about to read 3, iclass 4, count 0 2006.280.07:41:59.78#ibcon#read 3, iclass 4, count 0 2006.280.07:41:59.78#ibcon#about to read 4, iclass 4, count 0 2006.280.07:41:59.78#ibcon#read 4, iclass 4, count 0 2006.280.07:41:59.78#ibcon#about to read 5, iclass 4, count 0 2006.280.07:41:59.78#ibcon#read 5, iclass 4, count 0 2006.280.07:41:59.78#ibcon#about to read 6, iclass 4, count 0 2006.280.07:41:59.78#ibcon#read 6, iclass 4, count 0 2006.280.07:41:59.78#ibcon#end of sib2, iclass 4, count 0 2006.280.07:41:59.78#ibcon#*after write, iclass 4, count 0 2006.280.07:41:59.78#ibcon#*before return 0, iclass 4, count 0 2006.280.07:41:59.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:41:59.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:41:59.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:41:59.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:41:59.78$vc4f8/va=5,7 2006.280.07:41:59.79#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:41:59.79#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:41:59.79#ibcon#ireg 11 cls_cnt 2 2006.280.07:41:59.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:41:59.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:41:59.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:41:59.85#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:41:59.85#ibcon#first serial, iclass 6, count 2 2006.280.07:41:59.85#ibcon#enter sib2, iclass 6, count 2 2006.280.07:41:59.85#ibcon#flushed, iclass 6, count 2 2006.280.07:41:59.85#ibcon#about to write, iclass 6, count 2 2006.280.07:41:59.85#ibcon#wrote, iclass 6, count 2 2006.280.07:41:59.85#ibcon#about to read 3, iclass 6, count 2 2006.280.07:41:59.86#ibcon#read 3, iclass 6, count 2 2006.280.07:41:59.86#ibcon#about to read 4, iclass 6, count 2 2006.280.07:41:59.86#ibcon#read 4, iclass 6, count 2 2006.280.07:41:59.86#ibcon#about to read 5, iclass 6, count 2 2006.280.07:41:59.86#ibcon#read 5, iclass 6, count 2 2006.280.07:41:59.86#ibcon#about to read 6, iclass 6, count 2 2006.280.07:41:59.86#ibcon#read 6, iclass 6, count 2 2006.280.07:41:59.86#ibcon#end of sib2, iclass 6, count 2 2006.280.07:41:59.86#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:41:59.86#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:41:59.86#ibcon#[25=AT05-07\r\n] 2006.280.07:41:59.86#ibcon#*before write, iclass 6, count 2 2006.280.07:41:59.86#ibcon#enter sib2, iclass 6, count 2 2006.280.07:41:59.86#ibcon#flushed, iclass 6, count 2 2006.280.07:41:59.86#ibcon#about to write, iclass 6, count 2 2006.280.07:41:59.86#ibcon#wrote, iclass 6, count 2 2006.280.07:41:59.86#ibcon#about to read 3, iclass 6, count 2 2006.280.07:41:59.89#ibcon#read 3, iclass 6, count 2 2006.280.07:41:59.89#ibcon#about to read 4, iclass 6, count 2 2006.280.07:41:59.89#ibcon#read 4, iclass 6, count 2 2006.280.07:41:59.89#ibcon#about to read 5, iclass 6, count 2 2006.280.07:41:59.89#ibcon#read 5, iclass 6, count 2 2006.280.07:41:59.89#ibcon#about to read 6, iclass 6, count 2 2006.280.07:41:59.89#ibcon#read 6, iclass 6, count 2 2006.280.07:41:59.89#ibcon#end of sib2, iclass 6, count 2 2006.280.07:41:59.89#ibcon#*after write, iclass 6, count 2 2006.280.07:41:59.89#ibcon#*before return 0, iclass 6, count 2 2006.280.07:41:59.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:41:59.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:41:59.89#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:41:59.89#ibcon#ireg 7 cls_cnt 0 2006.280.07:41:59.89#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:00.01#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:00.01#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:00.01#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:42:00.01#ibcon#first serial, iclass 6, count 0 2006.280.07:42:00.01#ibcon#enter sib2, iclass 6, count 0 2006.280.07:42:00.01#ibcon#flushed, iclass 6, count 0 2006.280.07:42:00.01#ibcon#about to write, iclass 6, count 0 2006.280.07:42:00.01#ibcon#wrote, iclass 6, count 0 2006.280.07:42:00.01#ibcon#about to read 3, iclass 6, count 0 2006.280.07:42:00.04#ibcon#read 3, iclass 6, count 0 2006.280.07:42:00.04#ibcon#about to read 4, iclass 6, count 0 2006.280.07:42:00.04#ibcon#read 4, iclass 6, count 0 2006.280.07:42:00.04#ibcon#about to read 5, iclass 6, count 0 2006.280.07:42:00.04#ibcon#read 5, iclass 6, count 0 2006.280.07:42:00.04#ibcon#about to read 6, iclass 6, count 0 2006.280.07:42:00.04#ibcon#read 6, iclass 6, count 0 2006.280.07:42:00.04#ibcon#end of sib2, iclass 6, count 0 2006.280.07:42:00.04#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:42:00.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:42:00.04#ibcon#[25=USB\r\n] 2006.280.07:42:00.04#ibcon#*before write, iclass 6, count 0 2006.280.07:42:00.04#ibcon#enter sib2, iclass 6, count 0 2006.280.07:42:00.04#ibcon#flushed, iclass 6, count 0 2006.280.07:42:00.04#ibcon#about to write, iclass 6, count 0 2006.280.07:42:00.04#ibcon#wrote, iclass 6, count 0 2006.280.07:42:00.04#ibcon#about to read 3, iclass 6, count 0 2006.280.07:42:00.07#ibcon#read 3, iclass 6, count 0 2006.280.07:42:00.07#ibcon#about to read 4, iclass 6, count 0 2006.280.07:42:00.07#ibcon#read 4, iclass 6, count 0 2006.280.07:42:00.07#ibcon#about to read 5, iclass 6, count 0 2006.280.07:42:00.07#ibcon#read 5, iclass 6, count 0 2006.280.07:42:00.07#ibcon#about to read 6, iclass 6, count 0 2006.280.07:42:00.07#ibcon#read 6, iclass 6, count 0 2006.280.07:42:00.07#ibcon#end of sib2, iclass 6, count 0 2006.280.07:42:00.07#ibcon#*after write, iclass 6, count 0 2006.280.07:42:00.07#ibcon#*before return 0, iclass 6, count 0 2006.280.07:42:00.07#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:00.07#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:00.07#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:42:00.07#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:42:00.07$vc4f8/valo=6,772.99 2006.280.07:42:00.07#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:42:00.07#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:42:00.07#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:00.07#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:00.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:00.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:00.07#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:42:00.07#ibcon#first serial, iclass 10, count 0 2006.280.07:42:00.07#ibcon#enter sib2, iclass 10, count 0 2006.280.07:42:00.07#ibcon#flushed, iclass 10, count 0 2006.280.07:42:00.07#ibcon#about to write, iclass 10, count 0 2006.280.07:42:00.07#ibcon#wrote, iclass 10, count 0 2006.280.07:42:00.07#ibcon#about to read 3, iclass 10, count 0 2006.280.07:42:00.08#ibcon#read 3, iclass 10, count 0 2006.280.07:42:00.08#ibcon#about to read 4, iclass 10, count 0 2006.280.07:42:00.08#ibcon#read 4, iclass 10, count 0 2006.280.07:42:00.08#ibcon#about to read 5, iclass 10, count 0 2006.280.07:42:00.08#ibcon#read 5, iclass 10, count 0 2006.280.07:42:00.08#ibcon#about to read 6, iclass 10, count 0 2006.280.07:42:00.08#ibcon#read 6, iclass 10, count 0 2006.280.07:42:00.10#ibcon#end of sib2, iclass 10, count 0 2006.280.07:42:00.10#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:42:00.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:42:00.10#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:42:00.10#ibcon#*before write, iclass 10, count 0 2006.280.07:42:00.10#ibcon#enter sib2, iclass 10, count 0 2006.280.07:42:00.10#ibcon#flushed, iclass 10, count 0 2006.280.07:42:00.10#ibcon#about to write, iclass 10, count 0 2006.280.07:42:00.10#ibcon#wrote, iclass 10, count 0 2006.280.07:42:00.10#ibcon#about to read 3, iclass 10, count 0 2006.280.07:42:00.13#ibcon#read 3, iclass 10, count 0 2006.280.07:42:00.13#ibcon#about to read 4, iclass 10, count 0 2006.280.07:42:00.13#ibcon#read 4, iclass 10, count 0 2006.280.07:42:00.13#ibcon#about to read 5, iclass 10, count 0 2006.280.07:42:00.13#ibcon#read 5, iclass 10, count 0 2006.280.07:42:00.13#ibcon#about to read 6, iclass 10, count 0 2006.280.07:42:00.13#ibcon#read 6, iclass 10, count 0 2006.280.07:42:00.13#ibcon#end of sib2, iclass 10, count 0 2006.280.07:42:00.13#ibcon#*after write, iclass 10, count 0 2006.280.07:42:00.13#ibcon#*before return 0, iclass 10, count 0 2006.280.07:42:00.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:00.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:00.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:42:00.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:42:00.13$vc4f8/va=6,6 2006.280.07:42:00.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:42:00.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:42:00.14#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:00.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:00.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:00.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:00.18#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:42:00.18#ibcon#first serial, iclass 12, count 2 2006.280.07:42:00.18#ibcon#enter sib2, iclass 12, count 2 2006.280.07:42:00.18#ibcon#flushed, iclass 12, count 2 2006.280.07:42:00.18#ibcon#about to write, iclass 12, count 2 2006.280.07:42:00.18#ibcon#wrote, iclass 12, count 2 2006.280.07:42:00.18#ibcon#about to read 3, iclass 12, count 2 2006.280.07:42:00.20#ibcon#read 3, iclass 12, count 2 2006.280.07:42:00.20#ibcon#about to read 4, iclass 12, count 2 2006.280.07:42:00.20#ibcon#read 4, iclass 12, count 2 2006.280.07:42:00.20#ibcon#about to read 5, iclass 12, count 2 2006.280.07:42:00.20#ibcon#read 5, iclass 12, count 2 2006.280.07:42:00.20#ibcon#about to read 6, iclass 12, count 2 2006.280.07:42:00.20#ibcon#read 6, iclass 12, count 2 2006.280.07:42:00.20#ibcon#end of sib2, iclass 12, count 2 2006.280.07:42:00.20#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:42:00.20#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:42:00.20#ibcon#[25=AT06-06\r\n] 2006.280.07:42:00.20#ibcon#*before write, iclass 12, count 2 2006.280.07:42:00.20#ibcon#enter sib2, iclass 12, count 2 2006.280.07:42:00.20#ibcon#flushed, iclass 12, count 2 2006.280.07:42:00.20#ibcon#about to write, iclass 12, count 2 2006.280.07:42:00.20#ibcon#wrote, iclass 12, count 2 2006.280.07:42:00.20#ibcon#about to read 3, iclass 12, count 2 2006.280.07:42:00.23#ibcon#read 3, iclass 12, count 2 2006.280.07:42:00.23#ibcon#about to read 4, iclass 12, count 2 2006.280.07:42:00.23#ibcon#read 4, iclass 12, count 2 2006.280.07:42:00.23#ibcon#about to read 5, iclass 12, count 2 2006.280.07:42:00.23#ibcon#read 5, iclass 12, count 2 2006.280.07:42:00.23#ibcon#about to read 6, iclass 12, count 2 2006.280.07:42:00.23#ibcon#read 6, iclass 12, count 2 2006.280.07:42:00.23#ibcon#end of sib2, iclass 12, count 2 2006.280.07:42:00.23#ibcon#*after write, iclass 12, count 2 2006.280.07:42:00.23#ibcon#*before return 0, iclass 12, count 2 2006.280.07:42:00.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:00.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:00.23#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:42:00.23#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:00.23#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:42:00.36#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:42:00.36#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:42:00.36#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:42:00.36#ibcon#first serial, iclass 12, count 0 2006.280.07:42:00.36#ibcon#enter sib2, iclass 12, count 0 2006.280.07:42:00.36#ibcon#flushed, iclass 12, count 0 2006.280.07:42:00.36#ibcon#about to write, iclass 12, count 0 2006.280.07:42:00.36#ibcon#wrote, iclass 12, count 0 2006.280.07:42:00.36#ibcon#about to read 3, iclass 12, count 0 2006.280.07:42:00.37#ibcon#read 3, iclass 12, count 0 2006.280.07:42:00.37#ibcon#about to read 4, iclass 12, count 0 2006.280.07:42:00.37#ibcon#read 4, iclass 12, count 0 2006.280.07:42:00.37#ibcon#about to read 5, iclass 12, count 0 2006.280.07:42:00.37#ibcon#read 5, iclass 12, count 0 2006.280.07:42:00.37#ibcon#about to read 6, iclass 12, count 0 2006.280.07:42:00.37#ibcon#read 6, iclass 12, count 0 2006.280.07:42:00.37#ibcon#end of sib2, iclass 12, count 0 2006.280.07:42:00.37#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:42:00.37#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:42:00.37#ibcon#[25=USB\r\n] 2006.280.07:42:00.37#ibcon#*before write, iclass 12, count 0 2006.280.07:42:00.37#ibcon#enter sib2, iclass 12, count 0 2006.280.07:42:00.37#ibcon#flushed, iclass 12, count 0 2006.280.07:42:00.37#ibcon#about to write, iclass 12, count 0 2006.280.07:42:00.37#ibcon#wrote, iclass 12, count 0 2006.280.07:42:00.37#ibcon#about to read 3, iclass 12, count 0 2006.280.07:42:00.40#ibcon#read 3, iclass 12, count 0 2006.280.07:42:00.40#ibcon#about to read 4, iclass 12, count 0 2006.280.07:42:00.40#ibcon#read 4, iclass 12, count 0 2006.280.07:42:00.40#ibcon#about to read 5, iclass 12, count 0 2006.280.07:42:00.40#ibcon#read 5, iclass 12, count 0 2006.280.07:42:00.40#ibcon#about to read 6, iclass 12, count 0 2006.280.07:42:00.40#ibcon#read 6, iclass 12, count 0 2006.280.07:42:00.40#ibcon#end of sib2, iclass 12, count 0 2006.280.07:42:00.40#ibcon#*after write, iclass 12, count 0 2006.280.07:42:00.40#ibcon#*before return 0, iclass 12, count 0 2006.280.07:42:00.40#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:42:00.40#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:42:00.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:42:00.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:42:00.40$vc4f8/valo=7,832.99 2006.280.07:42:00.40#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:42:00.41#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:42:00.41#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:00.41#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:42:00.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:42:00.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:42:00.41#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:42:00.41#ibcon#first serial, iclass 14, count 0 2006.280.07:42:00.41#ibcon#enter sib2, iclass 14, count 0 2006.280.07:42:00.41#ibcon#flushed, iclass 14, count 0 2006.280.07:42:00.41#ibcon#about to write, iclass 14, count 0 2006.280.07:42:00.41#ibcon#wrote, iclass 14, count 0 2006.280.07:42:00.41#ibcon#about to read 3, iclass 14, count 0 2006.280.07:42:00.42#ibcon#read 3, iclass 14, count 0 2006.280.07:42:00.43#ibcon#about to read 4, iclass 14, count 0 2006.280.07:42:00.43#ibcon#read 4, iclass 14, count 0 2006.280.07:42:00.43#ibcon#about to read 5, iclass 14, count 0 2006.280.07:42:00.43#ibcon#read 5, iclass 14, count 0 2006.280.07:42:00.43#ibcon#about to read 6, iclass 14, count 0 2006.280.07:42:00.43#ibcon#read 6, iclass 14, count 0 2006.280.07:42:00.43#ibcon#end of sib2, iclass 14, count 0 2006.280.07:42:00.43#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:42:00.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:42:00.43#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:42:00.43#ibcon#*before write, iclass 14, count 0 2006.280.07:42:00.43#ibcon#enter sib2, iclass 14, count 0 2006.280.07:42:00.43#ibcon#flushed, iclass 14, count 0 2006.280.07:42:00.43#ibcon#about to write, iclass 14, count 0 2006.280.07:42:00.43#ibcon#wrote, iclass 14, count 0 2006.280.07:42:00.43#ibcon#about to read 3, iclass 14, count 0 2006.280.07:42:00.46#ibcon#read 3, iclass 14, count 0 2006.280.07:42:00.46#ibcon#about to read 4, iclass 14, count 0 2006.280.07:42:00.46#ibcon#read 4, iclass 14, count 0 2006.280.07:42:00.46#ibcon#about to read 5, iclass 14, count 0 2006.280.07:42:00.46#ibcon#read 5, iclass 14, count 0 2006.280.07:42:00.46#ibcon#about to read 6, iclass 14, count 0 2006.280.07:42:00.46#ibcon#read 6, iclass 14, count 0 2006.280.07:42:00.46#ibcon#end of sib2, iclass 14, count 0 2006.280.07:42:00.46#ibcon#*after write, iclass 14, count 0 2006.280.07:42:00.46#ibcon#*before return 0, iclass 14, count 0 2006.280.07:42:00.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:42:00.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:42:00.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:42:00.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:42:00.47$vc4f8/va=7,6 2006.280.07:42:00.47#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:42:00.47#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:42:00.47#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:00.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:42:00.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:42:00.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:42:00.51#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:42:00.51#ibcon#first serial, iclass 16, count 2 2006.280.07:42:00.51#ibcon#enter sib2, iclass 16, count 2 2006.280.07:42:00.51#ibcon#flushed, iclass 16, count 2 2006.280.07:42:00.51#ibcon#about to write, iclass 16, count 2 2006.280.07:42:00.51#ibcon#wrote, iclass 16, count 2 2006.280.07:42:00.51#ibcon#about to read 3, iclass 16, count 2 2006.280.07:42:00.53#ibcon#read 3, iclass 16, count 2 2006.280.07:42:00.53#ibcon#about to read 4, iclass 16, count 2 2006.280.07:42:00.53#ibcon#read 4, iclass 16, count 2 2006.280.07:42:00.53#ibcon#about to read 5, iclass 16, count 2 2006.280.07:42:00.53#ibcon#read 5, iclass 16, count 2 2006.280.07:42:00.53#ibcon#about to read 6, iclass 16, count 2 2006.280.07:42:00.53#ibcon#read 6, iclass 16, count 2 2006.280.07:42:00.53#ibcon#end of sib2, iclass 16, count 2 2006.280.07:42:00.53#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:42:00.53#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:42:00.53#ibcon#[25=AT07-06\r\n] 2006.280.07:42:00.53#ibcon#*before write, iclass 16, count 2 2006.280.07:42:00.53#ibcon#enter sib2, iclass 16, count 2 2006.280.07:42:00.53#ibcon#flushed, iclass 16, count 2 2006.280.07:42:00.53#ibcon#about to write, iclass 16, count 2 2006.280.07:42:00.53#ibcon#wrote, iclass 16, count 2 2006.280.07:42:00.53#ibcon#about to read 3, iclass 16, count 2 2006.280.07:42:00.56#ibcon#read 3, iclass 16, count 2 2006.280.07:42:00.56#ibcon#about to read 4, iclass 16, count 2 2006.280.07:42:00.56#ibcon#read 4, iclass 16, count 2 2006.280.07:42:00.56#ibcon#about to read 5, iclass 16, count 2 2006.280.07:42:00.56#ibcon#read 5, iclass 16, count 2 2006.280.07:42:00.56#ibcon#about to read 6, iclass 16, count 2 2006.280.07:42:00.56#ibcon#read 6, iclass 16, count 2 2006.280.07:42:00.56#ibcon#end of sib2, iclass 16, count 2 2006.280.07:42:00.56#ibcon#*after write, iclass 16, count 2 2006.280.07:42:00.56#ibcon#*before return 0, iclass 16, count 2 2006.280.07:42:00.56#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:42:00.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:42:00.56#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:42:00.56#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:00.56#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:42:00.68#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:42:00.68#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:42:00.68#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:42:00.68#ibcon#first serial, iclass 16, count 0 2006.280.07:42:00.68#ibcon#enter sib2, iclass 16, count 0 2006.280.07:42:00.68#ibcon#flushed, iclass 16, count 0 2006.280.07:42:00.68#ibcon#about to write, iclass 16, count 0 2006.280.07:42:00.68#ibcon#wrote, iclass 16, count 0 2006.280.07:42:00.68#ibcon#about to read 3, iclass 16, count 0 2006.280.07:42:00.70#ibcon#read 3, iclass 16, count 0 2006.280.07:42:00.70#ibcon#about to read 4, iclass 16, count 0 2006.280.07:42:00.70#ibcon#read 4, iclass 16, count 0 2006.280.07:42:00.70#ibcon#about to read 5, iclass 16, count 0 2006.280.07:42:00.70#ibcon#read 5, iclass 16, count 0 2006.280.07:42:00.70#ibcon#about to read 6, iclass 16, count 0 2006.280.07:42:00.70#ibcon#read 6, iclass 16, count 0 2006.280.07:42:00.70#ibcon#end of sib2, iclass 16, count 0 2006.280.07:42:00.70#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:42:00.70#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:42:00.70#ibcon#[25=USB\r\n] 2006.280.07:42:00.70#ibcon#*before write, iclass 16, count 0 2006.280.07:42:00.70#ibcon#enter sib2, iclass 16, count 0 2006.280.07:42:00.70#ibcon#flushed, iclass 16, count 0 2006.280.07:42:00.70#ibcon#about to write, iclass 16, count 0 2006.280.07:42:00.70#ibcon#wrote, iclass 16, count 0 2006.280.07:42:00.70#ibcon#about to read 3, iclass 16, count 0 2006.280.07:42:00.73#ibcon#read 3, iclass 16, count 0 2006.280.07:42:00.73#ibcon#about to read 4, iclass 16, count 0 2006.280.07:42:00.73#ibcon#read 4, iclass 16, count 0 2006.280.07:42:00.73#ibcon#about to read 5, iclass 16, count 0 2006.280.07:42:00.73#ibcon#read 5, iclass 16, count 0 2006.280.07:42:00.73#ibcon#about to read 6, iclass 16, count 0 2006.280.07:42:00.73#ibcon#read 6, iclass 16, count 0 2006.280.07:42:00.73#ibcon#end of sib2, iclass 16, count 0 2006.280.07:42:00.73#ibcon#*after write, iclass 16, count 0 2006.280.07:42:00.73#ibcon#*before return 0, iclass 16, count 0 2006.280.07:42:00.73#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:42:00.73#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:42:00.73#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:42:00.73#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:42:00.73$vc4f8/valo=8,852.99 2006.280.07:42:00.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:42:00.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:42:00.74#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:00.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:42:00.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:42:00.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:42:00.74#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:42:00.74#ibcon#first serial, iclass 18, count 0 2006.280.07:42:00.74#ibcon#enter sib2, iclass 18, count 0 2006.280.07:42:00.74#ibcon#flushed, iclass 18, count 0 2006.280.07:42:00.74#ibcon#about to write, iclass 18, count 0 2006.280.07:42:00.74#ibcon#wrote, iclass 18, count 0 2006.280.07:42:00.74#ibcon#about to read 3, iclass 18, count 0 2006.280.07:42:00.75#ibcon#read 3, iclass 18, count 0 2006.280.07:42:00.75#ibcon#about to read 4, iclass 18, count 0 2006.280.07:42:00.75#ibcon#read 4, iclass 18, count 0 2006.280.07:42:00.75#ibcon#about to read 5, iclass 18, count 0 2006.280.07:42:00.75#ibcon#read 5, iclass 18, count 0 2006.280.07:42:00.75#ibcon#about to read 6, iclass 18, count 0 2006.280.07:42:00.75#ibcon#read 6, iclass 18, count 0 2006.280.07:42:00.75#ibcon#end of sib2, iclass 18, count 0 2006.280.07:42:00.75#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:42:00.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:42:00.75#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:42:00.75#ibcon#*before write, iclass 18, count 0 2006.280.07:42:00.75#ibcon#enter sib2, iclass 18, count 0 2006.280.07:42:00.75#ibcon#flushed, iclass 18, count 0 2006.280.07:42:00.75#ibcon#about to write, iclass 18, count 0 2006.280.07:42:00.75#ibcon#wrote, iclass 18, count 0 2006.280.07:42:00.75#ibcon#about to read 3, iclass 18, count 0 2006.280.07:42:00.80#ibcon#read 3, iclass 18, count 0 2006.280.07:42:00.80#ibcon#about to read 4, iclass 18, count 0 2006.280.07:42:00.80#ibcon#read 4, iclass 18, count 0 2006.280.07:42:00.80#ibcon#about to read 5, iclass 18, count 0 2006.280.07:42:00.80#ibcon#read 5, iclass 18, count 0 2006.280.07:42:00.80#ibcon#about to read 6, iclass 18, count 0 2006.280.07:42:00.80#ibcon#read 6, iclass 18, count 0 2006.280.07:42:00.80#ibcon#end of sib2, iclass 18, count 0 2006.280.07:42:00.80#ibcon#*after write, iclass 18, count 0 2006.280.07:42:00.80#ibcon#*before return 0, iclass 18, count 0 2006.280.07:42:00.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:42:00.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:42:00.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:42:00.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:42:00.80$vc4f8/va=8,6 2006.280.07:42:00.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:42:00.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:42:00.80#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:00.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:42:00.84#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:42:00.84#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:42:00.84#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:42:00.84#ibcon#first serial, iclass 20, count 2 2006.280.07:42:00.84#ibcon#enter sib2, iclass 20, count 2 2006.280.07:42:00.84#ibcon#flushed, iclass 20, count 2 2006.280.07:42:00.84#ibcon#about to write, iclass 20, count 2 2006.280.07:42:00.84#ibcon#wrote, iclass 20, count 2 2006.280.07:42:00.84#ibcon#about to read 3, iclass 20, count 2 2006.280.07:42:00.86#ibcon#read 3, iclass 20, count 2 2006.280.07:42:00.86#ibcon#about to read 4, iclass 20, count 2 2006.280.07:42:00.86#ibcon#read 4, iclass 20, count 2 2006.280.07:42:00.86#ibcon#about to read 5, iclass 20, count 2 2006.280.07:42:00.86#ibcon#read 5, iclass 20, count 2 2006.280.07:42:00.86#ibcon#about to read 6, iclass 20, count 2 2006.280.07:42:00.86#ibcon#read 6, iclass 20, count 2 2006.280.07:42:00.86#ibcon#end of sib2, iclass 20, count 2 2006.280.07:42:00.86#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:42:00.86#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:42:00.86#ibcon#[25=AT08-06\r\n] 2006.280.07:42:00.86#ibcon#*before write, iclass 20, count 2 2006.280.07:42:00.86#ibcon#enter sib2, iclass 20, count 2 2006.280.07:42:00.86#ibcon#flushed, iclass 20, count 2 2006.280.07:42:00.86#ibcon#about to write, iclass 20, count 2 2006.280.07:42:00.86#ibcon#wrote, iclass 20, count 2 2006.280.07:42:00.86#ibcon#about to read 3, iclass 20, count 2 2006.280.07:42:00.89#ibcon#read 3, iclass 20, count 2 2006.280.07:42:00.89#ibcon#about to read 4, iclass 20, count 2 2006.280.07:42:00.89#ibcon#read 4, iclass 20, count 2 2006.280.07:42:00.89#ibcon#about to read 5, iclass 20, count 2 2006.280.07:42:00.89#ibcon#read 5, iclass 20, count 2 2006.280.07:42:00.89#ibcon#about to read 6, iclass 20, count 2 2006.280.07:42:00.89#ibcon#read 6, iclass 20, count 2 2006.280.07:42:00.89#ibcon#end of sib2, iclass 20, count 2 2006.280.07:42:00.89#ibcon#*after write, iclass 20, count 2 2006.280.07:42:00.89#ibcon#*before return 0, iclass 20, count 2 2006.280.07:42:00.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:42:00.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:42:00.89#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:42:00.89#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:00.89#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:42:01.02#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:42:01.02#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:42:01.02#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:42:01.02#ibcon#first serial, iclass 20, count 0 2006.280.07:42:01.02#ibcon#enter sib2, iclass 20, count 0 2006.280.07:42:01.02#ibcon#flushed, iclass 20, count 0 2006.280.07:42:01.02#ibcon#about to write, iclass 20, count 0 2006.280.07:42:01.02#ibcon#wrote, iclass 20, count 0 2006.280.07:42:01.02#ibcon#about to read 3, iclass 20, count 0 2006.280.07:42:01.03#ibcon#read 3, iclass 20, count 0 2006.280.07:42:01.03#ibcon#about to read 4, iclass 20, count 0 2006.280.07:42:01.03#ibcon#read 4, iclass 20, count 0 2006.280.07:42:01.03#ibcon#about to read 5, iclass 20, count 0 2006.280.07:42:01.03#ibcon#read 5, iclass 20, count 0 2006.280.07:42:01.03#ibcon#about to read 6, iclass 20, count 0 2006.280.07:42:01.03#ibcon#read 6, iclass 20, count 0 2006.280.07:42:01.03#ibcon#end of sib2, iclass 20, count 0 2006.280.07:42:01.03#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:42:01.03#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:42:01.03#ibcon#[25=USB\r\n] 2006.280.07:42:01.03#ibcon#*before write, iclass 20, count 0 2006.280.07:42:01.03#ibcon#enter sib2, iclass 20, count 0 2006.280.07:42:01.03#ibcon#flushed, iclass 20, count 0 2006.280.07:42:01.03#ibcon#about to write, iclass 20, count 0 2006.280.07:42:01.03#ibcon#wrote, iclass 20, count 0 2006.280.07:42:01.03#ibcon#about to read 3, iclass 20, count 0 2006.280.07:42:01.06#ibcon#read 3, iclass 20, count 0 2006.280.07:42:01.06#ibcon#about to read 4, iclass 20, count 0 2006.280.07:42:01.06#ibcon#read 4, iclass 20, count 0 2006.280.07:42:01.06#ibcon#about to read 5, iclass 20, count 0 2006.280.07:42:01.06#ibcon#read 5, iclass 20, count 0 2006.280.07:42:01.06#ibcon#about to read 6, iclass 20, count 0 2006.280.07:42:01.06#ibcon#read 6, iclass 20, count 0 2006.280.07:42:01.06#ibcon#end of sib2, iclass 20, count 0 2006.280.07:42:01.06#ibcon#*after write, iclass 20, count 0 2006.280.07:42:01.06#ibcon#*before return 0, iclass 20, count 0 2006.280.07:42:01.06#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:42:01.06#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:42:01.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:42:01.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:42:01.06$vc4f8/vblo=1,632.99 2006.280.07:42:01.06#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.07:42:01.07#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.07:42:01.07#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:01.07#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:42:01.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:42:01.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:42:01.07#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:42:01.07#ibcon#first serial, iclass 22, count 0 2006.280.07:42:01.07#ibcon#enter sib2, iclass 22, count 0 2006.280.07:42:01.07#ibcon#flushed, iclass 22, count 0 2006.280.07:42:01.07#ibcon#about to write, iclass 22, count 0 2006.280.07:42:01.07#ibcon#wrote, iclass 22, count 0 2006.280.07:42:01.07#ibcon#about to read 3, iclass 22, count 0 2006.280.07:42:01.08#ibcon#read 3, iclass 22, count 0 2006.280.07:42:01.08#ibcon#about to read 4, iclass 22, count 0 2006.280.07:42:01.08#ibcon#read 4, iclass 22, count 0 2006.280.07:42:01.08#ibcon#about to read 5, iclass 22, count 0 2006.280.07:42:01.08#ibcon#read 5, iclass 22, count 0 2006.280.07:42:01.08#ibcon#about to read 6, iclass 22, count 0 2006.280.07:42:01.08#ibcon#read 6, iclass 22, count 0 2006.280.07:42:01.08#ibcon#end of sib2, iclass 22, count 0 2006.280.07:42:01.08#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:42:01.08#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:42:01.08#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:42:01.08#ibcon#*before write, iclass 22, count 0 2006.280.07:42:01.08#ibcon#enter sib2, iclass 22, count 0 2006.280.07:42:01.08#ibcon#flushed, iclass 22, count 0 2006.280.07:42:01.08#ibcon#about to write, iclass 22, count 0 2006.280.07:42:01.08#ibcon#wrote, iclass 22, count 0 2006.280.07:42:01.08#ibcon#about to read 3, iclass 22, count 0 2006.280.07:42:01.12#ibcon#read 3, iclass 22, count 0 2006.280.07:42:01.12#ibcon#about to read 4, iclass 22, count 0 2006.280.07:42:01.12#ibcon#read 4, iclass 22, count 0 2006.280.07:42:01.12#ibcon#about to read 5, iclass 22, count 0 2006.280.07:42:01.12#ibcon#read 5, iclass 22, count 0 2006.280.07:42:01.12#ibcon#about to read 6, iclass 22, count 0 2006.280.07:42:01.12#ibcon#read 6, iclass 22, count 0 2006.280.07:42:01.12#ibcon#end of sib2, iclass 22, count 0 2006.280.07:42:01.12#ibcon#*after write, iclass 22, count 0 2006.280.07:42:01.12#ibcon#*before return 0, iclass 22, count 0 2006.280.07:42:01.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:42:01.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:42:01.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:42:01.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:42:01.12$vc4f8/vb=1,4 2006.280.07:42:01.14#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.07:42:01.14#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.07:42:01.14#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:01.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:42:01.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:42:01.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:42:01.14#ibcon#enter wrdev, iclass 24, count 2 2006.280.07:42:01.14#ibcon#first serial, iclass 24, count 2 2006.280.07:42:01.14#ibcon#enter sib2, iclass 24, count 2 2006.280.07:42:01.14#ibcon#flushed, iclass 24, count 2 2006.280.07:42:01.14#ibcon#about to write, iclass 24, count 2 2006.280.07:42:01.14#ibcon#wrote, iclass 24, count 2 2006.280.07:42:01.14#ibcon#about to read 3, iclass 24, count 2 2006.280.07:42:01.15#ibcon#read 3, iclass 24, count 2 2006.280.07:42:01.16#ibcon#about to read 4, iclass 24, count 2 2006.280.07:42:01.16#ibcon#read 4, iclass 24, count 2 2006.280.07:42:01.16#ibcon#about to read 5, iclass 24, count 2 2006.280.07:42:01.16#ibcon#read 5, iclass 24, count 2 2006.280.07:42:01.16#ibcon#about to read 6, iclass 24, count 2 2006.280.07:42:01.16#ibcon#read 6, iclass 24, count 2 2006.280.07:42:01.16#ibcon#end of sib2, iclass 24, count 2 2006.280.07:42:01.16#ibcon#*mode == 0, iclass 24, count 2 2006.280.07:42:01.16#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.07:42:01.16#ibcon#[27=AT01-04\r\n] 2006.280.07:42:01.16#ibcon#*before write, iclass 24, count 2 2006.280.07:42:01.16#ibcon#enter sib2, iclass 24, count 2 2006.280.07:42:01.16#ibcon#flushed, iclass 24, count 2 2006.280.07:42:01.16#ibcon#about to write, iclass 24, count 2 2006.280.07:42:01.16#ibcon#wrote, iclass 24, count 2 2006.280.07:42:01.16#ibcon#about to read 3, iclass 24, count 2 2006.280.07:42:01.18#ibcon#read 3, iclass 24, count 2 2006.280.07:42:01.18#ibcon#about to read 4, iclass 24, count 2 2006.280.07:42:01.18#ibcon#read 4, iclass 24, count 2 2006.280.07:42:01.18#ibcon#about to read 5, iclass 24, count 2 2006.280.07:42:01.18#ibcon#read 5, iclass 24, count 2 2006.280.07:42:01.18#ibcon#about to read 6, iclass 24, count 2 2006.280.07:42:01.18#ibcon#read 6, iclass 24, count 2 2006.280.07:42:01.18#ibcon#end of sib2, iclass 24, count 2 2006.280.07:42:01.18#ibcon#*after write, iclass 24, count 2 2006.280.07:42:01.18#ibcon#*before return 0, iclass 24, count 2 2006.280.07:42:01.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:42:01.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:42:01.18#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.07:42:01.18#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:01.18#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:42:01.30#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:42:01.30#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:42:01.30#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:42:01.30#ibcon#first serial, iclass 24, count 0 2006.280.07:42:01.30#ibcon#enter sib2, iclass 24, count 0 2006.280.07:42:01.30#ibcon#flushed, iclass 24, count 0 2006.280.07:42:01.30#ibcon#about to write, iclass 24, count 0 2006.280.07:42:01.30#ibcon#wrote, iclass 24, count 0 2006.280.07:42:01.30#ibcon#about to read 3, iclass 24, count 0 2006.280.07:42:01.33#ibcon#read 3, iclass 24, count 0 2006.280.07:42:01.33#ibcon#about to read 4, iclass 24, count 0 2006.280.07:42:01.33#ibcon#read 4, iclass 24, count 0 2006.280.07:42:01.33#ibcon#about to read 5, iclass 24, count 0 2006.280.07:42:01.33#ibcon#read 5, iclass 24, count 0 2006.280.07:42:01.33#ibcon#about to read 6, iclass 24, count 0 2006.280.07:42:01.33#ibcon#read 6, iclass 24, count 0 2006.280.07:42:01.33#ibcon#end of sib2, iclass 24, count 0 2006.280.07:42:01.33#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:42:01.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:42:01.33#ibcon#[27=USB\r\n] 2006.280.07:42:01.33#ibcon#*before write, iclass 24, count 0 2006.280.07:42:01.33#ibcon#enter sib2, iclass 24, count 0 2006.280.07:42:01.33#ibcon#flushed, iclass 24, count 0 2006.280.07:42:01.33#ibcon#about to write, iclass 24, count 0 2006.280.07:42:01.33#ibcon#wrote, iclass 24, count 0 2006.280.07:42:01.33#ibcon#about to read 3, iclass 24, count 0 2006.280.07:42:01.35#ibcon#read 3, iclass 24, count 0 2006.280.07:42:01.35#ibcon#about to read 4, iclass 24, count 0 2006.280.07:42:01.35#ibcon#read 4, iclass 24, count 0 2006.280.07:42:01.35#ibcon#about to read 5, iclass 24, count 0 2006.280.07:42:01.35#ibcon#read 5, iclass 24, count 0 2006.280.07:42:01.35#ibcon#about to read 6, iclass 24, count 0 2006.280.07:42:01.35#ibcon#read 6, iclass 24, count 0 2006.280.07:42:01.35#ibcon#end of sib2, iclass 24, count 0 2006.280.07:42:01.35#ibcon#*after write, iclass 24, count 0 2006.280.07:42:01.35#ibcon#*before return 0, iclass 24, count 0 2006.280.07:42:01.35#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:42:01.35#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:42:01.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:42:01.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:42:01.35$vc4f8/vblo=2,640.99 2006.280.07:42:01.35#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:42:01.35#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:42:01.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:01.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:42:01.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:42:01.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:42:01.36#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:42:01.36#ibcon#first serial, iclass 26, count 0 2006.280.07:42:01.36#ibcon#enter sib2, iclass 26, count 0 2006.280.07:42:01.36#ibcon#flushed, iclass 26, count 0 2006.280.07:42:01.36#ibcon#about to write, iclass 26, count 0 2006.280.07:42:01.36#ibcon#wrote, iclass 26, count 0 2006.280.07:42:01.36#ibcon#about to read 3, iclass 26, count 0 2006.280.07:42:01.37#ibcon#read 3, iclass 26, count 0 2006.280.07:42:01.37#ibcon#about to read 4, iclass 26, count 0 2006.280.07:42:01.37#ibcon#read 4, iclass 26, count 0 2006.280.07:42:01.37#ibcon#about to read 5, iclass 26, count 0 2006.280.07:42:01.37#ibcon#read 5, iclass 26, count 0 2006.280.07:42:01.37#ibcon#about to read 6, iclass 26, count 0 2006.280.07:42:01.37#ibcon#read 6, iclass 26, count 0 2006.280.07:42:01.37#ibcon#end of sib2, iclass 26, count 0 2006.280.07:42:01.37#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:42:01.37#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:42:01.37#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:42:01.37#ibcon#*before write, iclass 26, count 0 2006.280.07:42:01.37#ibcon#enter sib2, iclass 26, count 0 2006.280.07:42:01.37#ibcon#flushed, iclass 26, count 0 2006.280.07:42:01.37#ibcon#about to write, iclass 26, count 0 2006.280.07:42:01.37#ibcon#wrote, iclass 26, count 0 2006.280.07:42:01.37#ibcon#about to read 3, iclass 26, count 0 2006.280.07:42:01.42#ibcon#read 3, iclass 26, count 0 2006.280.07:42:01.42#ibcon#about to read 4, iclass 26, count 0 2006.280.07:42:01.42#ibcon#read 4, iclass 26, count 0 2006.280.07:42:01.42#ibcon#about to read 5, iclass 26, count 0 2006.280.07:42:01.42#ibcon#read 5, iclass 26, count 0 2006.280.07:42:01.42#ibcon#about to read 6, iclass 26, count 0 2006.280.07:42:01.42#ibcon#read 6, iclass 26, count 0 2006.280.07:42:01.42#ibcon#end of sib2, iclass 26, count 0 2006.280.07:42:01.42#ibcon#*after write, iclass 26, count 0 2006.280.07:42:01.42#ibcon#*before return 0, iclass 26, count 0 2006.280.07:42:01.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:42:01.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:42:01.42#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:42:01.42#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:42:01.42$vc4f8/vb=2,5 2006.280.07:42:01.42#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:42:01.42#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:42:01.42#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:01.42#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:42:01.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:42:01.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:42:01.46#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:42:01.46#ibcon#first serial, iclass 28, count 2 2006.280.07:42:01.46#ibcon#enter sib2, iclass 28, count 2 2006.280.07:42:01.46#ibcon#flushed, iclass 28, count 2 2006.280.07:42:01.46#ibcon#about to write, iclass 28, count 2 2006.280.07:42:01.46#ibcon#wrote, iclass 28, count 2 2006.280.07:42:01.46#ibcon#about to read 3, iclass 28, count 2 2006.280.07:42:01.48#ibcon#read 3, iclass 28, count 2 2006.280.07:42:01.48#ibcon#about to read 4, iclass 28, count 2 2006.280.07:42:01.48#ibcon#read 4, iclass 28, count 2 2006.280.07:42:01.48#ibcon#about to read 5, iclass 28, count 2 2006.280.07:42:01.48#ibcon#read 5, iclass 28, count 2 2006.280.07:42:01.48#ibcon#about to read 6, iclass 28, count 2 2006.280.07:42:01.48#ibcon#read 6, iclass 28, count 2 2006.280.07:42:01.48#ibcon#end of sib2, iclass 28, count 2 2006.280.07:42:01.48#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:42:01.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:42:01.48#ibcon#[27=AT02-05\r\n] 2006.280.07:42:01.48#ibcon#*before write, iclass 28, count 2 2006.280.07:42:01.48#ibcon#enter sib2, iclass 28, count 2 2006.280.07:42:01.48#ibcon#flushed, iclass 28, count 2 2006.280.07:42:01.48#ibcon#about to write, iclass 28, count 2 2006.280.07:42:01.48#ibcon#wrote, iclass 28, count 2 2006.280.07:42:01.48#ibcon#about to read 3, iclass 28, count 2 2006.280.07:42:01.51#ibcon#read 3, iclass 28, count 2 2006.280.07:42:01.51#ibcon#about to read 4, iclass 28, count 2 2006.280.07:42:01.51#ibcon#read 4, iclass 28, count 2 2006.280.07:42:01.51#ibcon#about to read 5, iclass 28, count 2 2006.280.07:42:01.51#ibcon#read 5, iclass 28, count 2 2006.280.07:42:01.51#ibcon#about to read 6, iclass 28, count 2 2006.280.07:42:01.51#ibcon#read 6, iclass 28, count 2 2006.280.07:42:01.51#ibcon#end of sib2, iclass 28, count 2 2006.280.07:42:01.51#ibcon#*after write, iclass 28, count 2 2006.280.07:42:01.51#ibcon#*before return 0, iclass 28, count 2 2006.280.07:42:01.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:42:01.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:42:01.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:42:01.51#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:01.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:42:01.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:42:01.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:42:01.63#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:42:01.63#ibcon#first serial, iclass 28, count 0 2006.280.07:42:01.63#ibcon#enter sib2, iclass 28, count 0 2006.280.07:42:01.63#ibcon#flushed, iclass 28, count 0 2006.280.07:42:01.63#ibcon#about to write, iclass 28, count 0 2006.280.07:42:01.63#ibcon#wrote, iclass 28, count 0 2006.280.07:42:01.63#ibcon#about to read 3, iclass 28, count 0 2006.280.07:42:01.65#ibcon#read 3, iclass 28, count 0 2006.280.07:42:01.65#ibcon#about to read 4, iclass 28, count 0 2006.280.07:42:01.65#ibcon#read 4, iclass 28, count 0 2006.280.07:42:01.65#ibcon#about to read 5, iclass 28, count 0 2006.280.07:42:01.65#ibcon#read 5, iclass 28, count 0 2006.280.07:42:01.65#ibcon#about to read 6, iclass 28, count 0 2006.280.07:42:01.65#ibcon#read 6, iclass 28, count 0 2006.280.07:42:01.65#ibcon#end of sib2, iclass 28, count 0 2006.280.07:42:01.65#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:42:01.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:42:01.65#ibcon#[27=USB\r\n] 2006.280.07:42:01.65#ibcon#*before write, iclass 28, count 0 2006.280.07:42:01.65#ibcon#enter sib2, iclass 28, count 0 2006.280.07:42:01.65#ibcon#flushed, iclass 28, count 0 2006.280.07:42:01.65#ibcon#about to write, iclass 28, count 0 2006.280.07:42:01.65#ibcon#wrote, iclass 28, count 0 2006.280.07:42:01.65#ibcon#about to read 3, iclass 28, count 0 2006.280.07:42:01.68#ibcon#read 3, iclass 28, count 0 2006.280.07:42:01.68#ibcon#about to read 4, iclass 28, count 0 2006.280.07:42:01.68#ibcon#read 4, iclass 28, count 0 2006.280.07:42:01.68#ibcon#about to read 5, iclass 28, count 0 2006.280.07:42:01.68#ibcon#read 5, iclass 28, count 0 2006.280.07:42:01.68#ibcon#about to read 6, iclass 28, count 0 2006.280.07:42:01.68#ibcon#read 6, iclass 28, count 0 2006.280.07:42:01.68#ibcon#end of sib2, iclass 28, count 0 2006.280.07:42:01.68#ibcon#*after write, iclass 28, count 0 2006.280.07:42:01.68#ibcon#*before return 0, iclass 28, count 0 2006.280.07:42:01.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:42:01.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:42:01.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:42:01.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:42:01.68$vc4f8/vblo=3,656.99 2006.280.07:42:01.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:42:01.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:42:01.69#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:01.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:42:01.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:42:01.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:42:01.69#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:42:01.69#ibcon#first serial, iclass 30, count 0 2006.280.07:42:01.69#ibcon#enter sib2, iclass 30, count 0 2006.280.07:42:01.69#ibcon#flushed, iclass 30, count 0 2006.280.07:42:01.69#ibcon#about to write, iclass 30, count 0 2006.280.07:42:01.69#ibcon#wrote, iclass 30, count 0 2006.280.07:42:01.69#ibcon#about to read 3, iclass 30, count 0 2006.280.07:42:01.70#ibcon#read 3, iclass 30, count 0 2006.280.07:42:01.70#ibcon#about to read 4, iclass 30, count 0 2006.280.07:42:01.70#ibcon#read 4, iclass 30, count 0 2006.280.07:42:01.70#ibcon#about to read 5, iclass 30, count 0 2006.280.07:42:01.70#ibcon#read 5, iclass 30, count 0 2006.280.07:42:01.70#ibcon#about to read 6, iclass 30, count 0 2006.280.07:42:01.70#ibcon#read 6, iclass 30, count 0 2006.280.07:42:01.70#ibcon#end of sib2, iclass 30, count 0 2006.280.07:42:01.70#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:42:01.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:42:01.70#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:42:01.70#ibcon#*before write, iclass 30, count 0 2006.280.07:42:01.70#ibcon#enter sib2, iclass 30, count 0 2006.280.07:42:01.70#ibcon#flushed, iclass 30, count 0 2006.280.07:42:01.70#ibcon#about to write, iclass 30, count 0 2006.280.07:42:01.70#ibcon#wrote, iclass 30, count 0 2006.280.07:42:01.70#ibcon#about to read 3, iclass 30, count 0 2006.280.07:42:01.74#ibcon#read 3, iclass 30, count 0 2006.280.07:42:01.74#ibcon#about to read 4, iclass 30, count 0 2006.280.07:42:01.74#ibcon#read 4, iclass 30, count 0 2006.280.07:42:01.74#ibcon#about to read 5, iclass 30, count 0 2006.280.07:42:01.74#ibcon#read 5, iclass 30, count 0 2006.280.07:42:01.74#ibcon#about to read 6, iclass 30, count 0 2006.280.07:42:01.74#ibcon#read 6, iclass 30, count 0 2006.280.07:42:01.74#ibcon#end of sib2, iclass 30, count 0 2006.280.07:42:01.74#ibcon#*after write, iclass 30, count 0 2006.280.07:42:01.74#ibcon#*before return 0, iclass 30, count 0 2006.280.07:42:01.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:42:01.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:42:01.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:42:01.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:42:01.74$vc4f8/vb=3,4 2006.280.07:42:01.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:42:01.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:42:01.74#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:01.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:42:01.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:42:01.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:42:01.80#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:42:01.80#ibcon#first serial, iclass 32, count 2 2006.280.07:42:01.80#ibcon#enter sib2, iclass 32, count 2 2006.280.07:42:01.80#ibcon#flushed, iclass 32, count 2 2006.280.07:42:01.80#ibcon#about to write, iclass 32, count 2 2006.280.07:42:01.80#ibcon#wrote, iclass 32, count 2 2006.280.07:42:01.80#ibcon#about to read 3, iclass 32, count 2 2006.280.07:42:01.82#ibcon#read 3, iclass 32, count 2 2006.280.07:42:01.82#ibcon#about to read 4, iclass 32, count 2 2006.280.07:42:01.82#ibcon#read 4, iclass 32, count 2 2006.280.07:42:01.82#ibcon#about to read 5, iclass 32, count 2 2006.280.07:42:01.82#ibcon#read 5, iclass 32, count 2 2006.280.07:42:01.82#ibcon#about to read 6, iclass 32, count 2 2006.280.07:42:01.82#ibcon#read 6, iclass 32, count 2 2006.280.07:42:01.82#ibcon#end of sib2, iclass 32, count 2 2006.280.07:42:01.82#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:42:01.82#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:42:01.82#ibcon#[27=AT03-04\r\n] 2006.280.07:42:01.82#ibcon#*before write, iclass 32, count 2 2006.280.07:42:01.82#ibcon#enter sib2, iclass 32, count 2 2006.280.07:42:01.82#ibcon#flushed, iclass 32, count 2 2006.280.07:42:01.82#ibcon#about to write, iclass 32, count 2 2006.280.07:42:01.82#ibcon#wrote, iclass 32, count 2 2006.280.07:42:01.82#ibcon#about to read 3, iclass 32, count 2 2006.280.07:42:01.85#ibcon#read 3, iclass 32, count 2 2006.280.07:42:01.85#ibcon#about to read 4, iclass 32, count 2 2006.280.07:42:01.85#ibcon#read 4, iclass 32, count 2 2006.280.07:42:01.85#ibcon#about to read 5, iclass 32, count 2 2006.280.07:42:01.85#ibcon#read 5, iclass 32, count 2 2006.280.07:42:01.85#ibcon#about to read 6, iclass 32, count 2 2006.280.07:42:01.85#ibcon#read 6, iclass 32, count 2 2006.280.07:42:01.85#ibcon#end of sib2, iclass 32, count 2 2006.280.07:42:01.85#ibcon#*after write, iclass 32, count 2 2006.280.07:42:01.85#ibcon#*before return 0, iclass 32, count 2 2006.280.07:42:01.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:42:01.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:42:01.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:42:01.85#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:01.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:42:01.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:42:01.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:42:01.97#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:42:01.97#ibcon#first serial, iclass 32, count 0 2006.280.07:42:01.97#ibcon#enter sib2, iclass 32, count 0 2006.280.07:42:01.97#ibcon#flushed, iclass 32, count 0 2006.280.07:42:01.97#ibcon#about to write, iclass 32, count 0 2006.280.07:42:01.97#ibcon#wrote, iclass 32, count 0 2006.280.07:42:01.97#ibcon#about to read 3, iclass 32, count 0 2006.280.07:42:01.99#ibcon#read 3, iclass 32, count 0 2006.280.07:42:01.99#ibcon#about to read 4, iclass 32, count 0 2006.280.07:42:01.99#ibcon#read 4, iclass 32, count 0 2006.280.07:42:01.99#ibcon#about to read 5, iclass 32, count 0 2006.280.07:42:01.99#ibcon#read 5, iclass 32, count 0 2006.280.07:42:01.99#ibcon#about to read 6, iclass 32, count 0 2006.280.07:42:01.99#ibcon#read 6, iclass 32, count 0 2006.280.07:42:01.99#ibcon#end of sib2, iclass 32, count 0 2006.280.07:42:01.99#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:42:01.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:42:01.99#ibcon#[27=USB\r\n] 2006.280.07:42:01.99#ibcon#*before write, iclass 32, count 0 2006.280.07:42:01.99#ibcon#enter sib2, iclass 32, count 0 2006.280.07:42:01.99#ibcon#flushed, iclass 32, count 0 2006.280.07:42:01.99#ibcon#about to write, iclass 32, count 0 2006.280.07:42:01.99#ibcon#wrote, iclass 32, count 0 2006.280.07:42:01.99#ibcon#about to read 3, iclass 32, count 0 2006.280.07:42:02.02#ibcon#read 3, iclass 32, count 0 2006.280.07:42:02.02#ibcon#about to read 4, iclass 32, count 0 2006.280.07:42:02.02#ibcon#read 4, iclass 32, count 0 2006.280.07:42:02.02#ibcon#about to read 5, iclass 32, count 0 2006.280.07:42:02.02#ibcon#read 5, iclass 32, count 0 2006.280.07:42:02.02#ibcon#about to read 6, iclass 32, count 0 2006.280.07:42:02.02#ibcon#read 6, iclass 32, count 0 2006.280.07:42:02.02#ibcon#end of sib2, iclass 32, count 0 2006.280.07:42:02.02#ibcon#*after write, iclass 32, count 0 2006.280.07:42:02.02#ibcon#*before return 0, iclass 32, count 0 2006.280.07:42:02.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:42:02.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:42:02.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:42:02.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:42:02.02$vc4f8/vblo=4,712.99 2006.280.07:42:02.03#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:42:02.03#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:42:02.03#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:02.03#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:42:02.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:42:02.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:42:02.03#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:42:02.03#ibcon#first serial, iclass 34, count 0 2006.280.07:42:02.03#ibcon#enter sib2, iclass 34, count 0 2006.280.07:42:02.03#ibcon#flushed, iclass 34, count 0 2006.280.07:42:02.03#ibcon#about to write, iclass 34, count 0 2006.280.07:42:02.03#ibcon#wrote, iclass 34, count 0 2006.280.07:42:02.03#ibcon#about to read 3, iclass 34, count 0 2006.280.07:42:02.04#ibcon#read 3, iclass 34, count 0 2006.280.07:42:02.04#ibcon#about to read 4, iclass 34, count 0 2006.280.07:42:02.04#ibcon#read 4, iclass 34, count 0 2006.280.07:42:02.04#ibcon#about to read 5, iclass 34, count 0 2006.280.07:42:02.04#ibcon#read 5, iclass 34, count 0 2006.280.07:42:02.04#ibcon#about to read 6, iclass 34, count 0 2006.280.07:42:02.04#ibcon#read 6, iclass 34, count 0 2006.280.07:42:02.04#ibcon#end of sib2, iclass 34, count 0 2006.280.07:42:02.04#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:42:02.04#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:42:02.04#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:42:02.04#ibcon#*before write, iclass 34, count 0 2006.280.07:42:02.04#ibcon#enter sib2, iclass 34, count 0 2006.280.07:42:02.04#ibcon#flushed, iclass 34, count 0 2006.280.07:42:02.04#ibcon#about to write, iclass 34, count 0 2006.280.07:42:02.04#ibcon#wrote, iclass 34, count 0 2006.280.07:42:02.04#ibcon#about to read 3, iclass 34, count 0 2006.280.07:42:02.08#ibcon#read 3, iclass 34, count 0 2006.280.07:42:02.08#ibcon#about to read 4, iclass 34, count 0 2006.280.07:42:02.08#ibcon#read 4, iclass 34, count 0 2006.280.07:42:02.08#ibcon#about to read 5, iclass 34, count 0 2006.280.07:42:02.08#ibcon#read 5, iclass 34, count 0 2006.280.07:42:02.08#ibcon#about to read 6, iclass 34, count 0 2006.280.07:42:02.08#ibcon#read 6, iclass 34, count 0 2006.280.07:42:02.08#ibcon#end of sib2, iclass 34, count 0 2006.280.07:42:02.08#ibcon#*after write, iclass 34, count 0 2006.280.07:42:02.08#ibcon#*before return 0, iclass 34, count 0 2006.280.07:42:02.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:42:02.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:42:02.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:42:02.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:42:02.08$vc4f8/vb=4,4 2006.280.07:42:02.09#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:42:02.09#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:42:02.09#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:02.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:42:02.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:42:02.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:42:02.13#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:42:02.13#ibcon#first serial, iclass 36, count 2 2006.280.07:42:02.13#ibcon#enter sib2, iclass 36, count 2 2006.280.07:42:02.13#ibcon#flushed, iclass 36, count 2 2006.280.07:42:02.13#ibcon#about to write, iclass 36, count 2 2006.280.07:42:02.13#ibcon#wrote, iclass 36, count 2 2006.280.07:42:02.13#ibcon#about to read 3, iclass 36, count 2 2006.280.07:42:02.16#ibcon#read 3, iclass 36, count 2 2006.280.07:42:02.16#ibcon#about to read 4, iclass 36, count 2 2006.280.07:42:02.16#ibcon#read 4, iclass 36, count 2 2006.280.07:42:02.16#ibcon#about to read 5, iclass 36, count 2 2006.280.07:42:02.16#ibcon#read 5, iclass 36, count 2 2006.280.07:42:02.16#ibcon#about to read 6, iclass 36, count 2 2006.280.07:42:02.16#ibcon#read 6, iclass 36, count 2 2006.280.07:42:02.16#ibcon#end of sib2, iclass 36, count 2 2006.280.07:42:02.16#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:42:02.16#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:42:02.16#ibcon#[27=AT04-04\r\n] 2006.280.07:42:02.16#ibcon#*before write, iclass 36, count 2 2006.280.07:42:02.16#ibcon#enter sib2, iclass 36, count 2 2006.280.07:42:02.16#ibcon#flushed, iclass 36, count 2 2006.280.07:42:02.16#ibcon#about to write, iclass 36, count 2 2006.280.07:42:02.16#ibcon#wrote, iclass 36, count 2 2006.280.07:42:02.16#ibcon#about to read 3, iclass 36, count 2 2006.280.07:42:02.19#ibcon#read 3, iclass 36, count 2 2006.280.07:42:02.19#ibcon#about to read 4, iclass 36, count 2 2006.280.07:42:02.19#ibcon#read 4, iclass 36, count 2 2006.280.07:42:02.19#ibcon#about to read 5, iclass 36, count 2 2006.280.07:42:02.19#ibcon#read 5, iclass 36, count 2 2006.280.07:42:02.19#ibcon#about to read 6, iclass 36, count 2 2006.280.07:42:02.19#ibcon#read 6, iclass 36, count 2 2006.280.07:42:02.19#ibcon#end of sib2, iclass 36, count 2 2006.280.07:42:02.19#ibcon#*after write, iclass 36, count 2 2006.280.07:42:02.19#ibcon#*before return 0, iclass 36, count 2 2006.280.07:42:02.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:42:02.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:42:02.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:42:02.19#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:02.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:42:02.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:42:02.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:42:02.31#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:42:02.31#ibcon#first serial, iclass 36, count 0 2006.280.07:42:02.31#ibcon#enter sib2, iclass 36, count 0 2006.280.07:42:02.31#ibcon#flushed, iclass 36, count 0 2006.280.07:42:02.31#ibcon#about to write, iclass 36, count 0 2006.280.07:42:02.31#ibcon#wrote, iclass 36, count 0 2006.280.07:42:02.31#ibcon#about to read 3, iclass 36, count 0 2006.280.07:42:02.33#ibcon#read 3, iclass 36, count 0 2006.280.07:42:02.33#ibcon#about to read 4, iclass 36, count 0 2006.280.07:42:02.33#ibcon#read 4, iclass 36, count 0 2006.280.07:42:02.33#ibcon#about to read 5, iclass 36, count 0 2006.280.07:42:02.33#ibcon#read 5, iclass 36, count 0 2006.280.07:42:02.33#ibcon#about to read 6, iclass 36, count 0 2006.280.07:42:02.33#ibcon#read 6, iclass 36, count 0 2006.280.07:42:02.33#ibcon#end of sib2, iclass 36, count 0 2006.280.07:42:02.33#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:42:02.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:42:02.33#ibcon#[27=USB\r\n] 2006.280.07:42:02.33#ibcon#*before write, iclass 36, count 0 2006.280.07:42:02.33#ibcon#enter sib2, iclass 36, count 0 2006.280.07:42:02.33#ibcon#flushed, iclass 36, count 0 2006.280.07:42:02.33#ibcon#about to write, iclass 36, count 0 2006.280.07:42:02.33#ibcon#wrote, iclass 36, count 0 2006.280.07:42:02.33#ibcon#about to read 3, iclass 36, count 0 2006.280.07:42:02.36#ibcon#read 3, iclass 36, count 0 2006.280.07:42:02.36#ibcon#about to read 4, iclass 36, count 0 2006.280.07:42:02.36#ibcon#read 4, iclass 36, count 0 2006.280.07:42:02.36#ibcon#about to read 5, iclass 36, count 0 2006.280.07:42:02.36#ibcon#read 5, iclass 36, count 0 2006.280.07:42:02.36#ibcon#about to read 6, iclass 36, count 0 2006.280.07:42:02.36#ibcon#read 6, iclass 36, count 0 2006.280.07:42:02.36#ibcon#end of sib2, iclass 36, count 0 2006.280.07:42:02.36#ibcon#*after write, iclass 36, count 0 2006.280.07:42:02.36#ibcon#*before return 0, iclass 36, count 0 2006.280.07:42:02.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:42:02.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:42:02.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:42:02.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:42:02.36$vc4f8/vblo=5,744.99 2006.280.07:42:02.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:42:02.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:42:02.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:02.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:42:02.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:42:02.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:42:02.37#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:42:02.37#ibcon#first serial, iclass 38, count 0 2006.280.07:42:02.37#ibcon#enter sib2, iclass 38, count 0 2006.280.07:42:02.37#ibcon#flushed, iclass 38, count 0 2006.280.07:42:02.37#ibcon#about to write, iclass 38, count 0 2006.280.07:42:02.37#ibcon#wrote, iclass 38, count 0 2006.280.07:42:02.37#ibcon#about to read 3, iclass 38, count 0 2006.280.07:42:02.38#ibcon#read 3, iclass 38, count 0 2006.280.07:42:02.39#ibcon#about to read 4, iclass 38, count 0 2006.280.07:42:02.39#ibcon#read 4, iclass 38, count 0 2006.280.07:42:02.39#ibcon#about to read 5, iclass 38, count 0 2006.280.07:42:02.39#ibcon#read 5, iclass 38, count 0 2006.280.07:42:02.39#ibcon#about to read 6, iclass 38, count 0 2006.280.07:42:02.39#ibcon#read 6, iclass 38, count 0 2006.280.07:42:02.39#ibcon#end of sib2, iclass 38, count 0 2006.280.07:42:02.39#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:42:02.39#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:42:02.39#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:42:02.39#ibcon#*before write, iclass 38, count 0 2006.280.07:42:02.39#ibcon#enter sib2, iclass 38, count 0 2006.280.07:42:02.39#ibcon#flushed, iclass 38, count 0 2006.280.07:42:02.39#ibcon#about to write, iclass 38, count 0 2006.280.07:42:02.39#ibcon#wrote, iclass 38, count 0 2006.280.07:42:02.39#ibcon#about to read 3, iclass 38, count 0 2006.280.07:42:02.42#ibcon#read 3, iclass 38, count 0 2006.280.07:42:02.42#ibcon#about to read 4, iclass 38, count 0 2006.280.07:42:02.42#ibcon#read 4, iclass 38, count 0 2006.280.07:42:02.42#ibcon#about to read 5, iclass 38, count 0 2006.280.07:42:02.42#ibcon#read 5, iclass 38, count 0 2006.280.07:42:02.42#ibcon#about to read 6, iclass 38, count 0 2006.280.07:42:02.42#ibcon#read 6, iclass 38, count 0 2006.280.07:42:02.42#ibcon#end of sib2, iclass 38, count 0 2006.280.07:42:02.42#ibcon#*after write, iclass 38, count 0 2006.280.07:42:02.42#ibcon#*before return 0, iclass 38, count 0 2006.280.07:42:02.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:42:02.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:42:02.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:42:02.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:42:02.42$vc4f8/vb=5,4 2006.280.07:42:02.42#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:42:02.43#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:42:02.43#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:02.43#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:42:02.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:42:02.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:42:02.47#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:42:02.47#ibcon#first serial, iclass 40, count 2 2006.280.07:42:02.47#ibcon#enter sib2, iclass 40, count 2 2006.280.07:42:02.47#ibcon#flushed, iclass 40, count 2 2006.280.07:42:02.47#ibcon#about to write, iclass 40, count 2 2006.280.07:42:02.47#ibcon#wrote, iclass 40, count 2 2006.280.07:42:02.47#ibcon#about to read 3, iclass 40, count 2 2006.280.07:42:02.49#ibcon#read 3, iclass 40, count 2 2006.280.07:42:02.49#ibcon#about to read 4, iclass 40, count 2 2006.280.07:42:02.49#ibcon#read 4, iclass 40, count 2 2006.280.07:42:02.49#ibcon#about to read 5, iclass 40, count 2 2006.280.07:42:02.49#ibcon#read 5, iclass 40, count 2 2006.280.07:42:02.49#ibcon#about to read 6, iclass 40, count 2 2006.280.07:42:02.49#ibcon#read 6, iclass 40, count 2 2006.280.07:42:02.49#ibcon#end of sib2, iclass 40, count 2 2006.280.07:42:02.49#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:42:02.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:42:02.49#ibcon#[27=AT05-04\r\n] 2006.280.07:42:02.49#ibcon#*before write, iclass 40, count 2 2006.280.07:42:02.49#ibcon#enter sib2, iclass 40, count 2 2006.280.07:42:02.49#ibcon#flushed, iclass 40, count 2 2006.280.07:42:02.49#ibcon#about to write, iclass 40, count 2 2006.280.07:42:02.49#ibcon#wrote, iclass 40, count 2 2006.280.07:42:02.49#ibcon#about to read 3, iclass 40, count 2 2006.280.07:42:02.52#ibcon#read 3, iclass 40, count 2 2006.280.07:42:02.52#ibcon#about to read 4, iclass 40, count 2 2006.280.07:42:02.52#ibcon#read 4, iclass 40, count 2 2006.280.07:42:02.52#ibcon#about to read 5, iclass 40, count 2 2006.280.07:42:02.52#ibcon#read 5, iclass 40, count 2 2006.280.07:42:02.52#ibcon#about to read 6, iclass 40, count 2 2006.280.07:42:02.52#ibcon#read 6, iclass 40, count 2 2006.280.07:42:02.52#ibcon#end of sib2, iclass 40, count 2 2006.280.07:42:02.52#ibcon#*after write, iclass 40, count 2 2006.280.07:42:02.52#ibcon#*before return 0, iclass 40, count 2 2006.280.07:42:02.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:42:02.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:42:02.52#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:42:02.52#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:02.52#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:42:02.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:42:02.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:42:02.64#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:42:02.64#ibcon#first serial, iclass 40, count 0 2006.280.07:42:02.64#ibcon#enter sib2, iclass 40, count 0 2006.280.07:42:02.64#ibcon#flushed, iclass 40, count 0 2006.280.07:42:02.64#ibcon#about to write, iclass 40, count 0 2006.280.07:42:02.64#ibcon#wrote, iclass 40, count 0 2006.280.07:42:02.64#ibcon#about to read 3, iclass 40, count 0 2006.280.07:42:02.66#ibcon#read 3, iclass 40, count 0 2006.280.07:42:02.66#ibcon#about to read 4, iclass 40, count 0 2006.280.07:42:02.66#ibcon#read 4, iclass 40, count 0 2006.280.07:42:02.66#ibcon#about to read 5, iclass 40, count 0 2006.280.07:42:02.66#ibcon#read 5, iclass 40, count 0 2006.280.07:42:02.66#ibcon#about to read 6, iclass 40, count 0 2006.280.07:42:02.66#ibcon#read 6, iclass 40, count 0 2006.280.07:42:02.66#ibcon#end of sib2, iclass 40, count 0 2006.280.07:42:02.66#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:42:02.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:42:02.66#ibcon#[27=USB\r\n] 2006.280.07:42:02.66#ibcon#*before write, iclass 40, count 0 2006.280.07:42:02.66#ibcon#enter sib2, iclass 40, count 0 2006.280.07:42:02.66#ibcon#flushed, iclass 40, count 0 2006.280.07:42:02.66#ibcon#about to write, iclass 40, count 0 2006.280.07:42:02.66#ibcon#wrote, iclass 40, count 0 2006.280.07:42:02.66#ibcon#about to read 3, iclass 40, count 0 2006.280.07:42:02.69#ibcon#read 3, iclass 40, count 0 2006.280.07:42:02.69#ibcon#about to read 4, iclass 40, count 0 2006.280.07:42:02.69#ibcon#read 4, iclass 40, count 0 2006.280.07:42:02.69#ibcon#about to read 5, iclass 40, count 0 2006.280.07:42:02.69#ibcon#read 5, iclass 40, count 0 2006.280.07:42:02.69#ibcon#about to read 6, iclass 40, count 0 2006.280.07:42:02.69#ibcon#read 6, iclass 40, count 0 2006.280.07:42:02.69#ibcon#end of sib2, iclass 40, count 0 2006.280.07:42:02.69#ibcon#*after write, iclass 40, count 0 2006.280.07:42:02.69#ibcon#*before return 0, iclass 40, count 0 2006.280.07:42:02.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:42:02.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:42:02.69#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:42:02.69#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:42:02.69$vc4f8/vblo=6,752.99 2006.280.07:42:02.69#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:42:02.69#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:42:02.70#ibcon#ireg 17 cls_cnt 0 2006.280.07:42:02.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:42:02.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:42:02.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:42:02.70#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:42:02.70#ibcon#first serial, iclass 4, count 0 2006.280.07:42:02.70#ibcon#enter sib2, iclass 4, count 0 2006.280.07:42:02.70#ibcon#flushed, iclass 4, count 0 2006.280.07:42:02.70#ibcon#about to write, iclass 4, count 0 2006.280.07:42:02.70#ibcon#wrote, iclass 4, count 0 2006.280.07:42:02.70#ibcon#about to read 3, iclass 4, count 0 2006.280.07:42:02.71#ibcon#read 3, iclass 4, count 0 2006.280.07:42:02.71#ibcon#about to read 4, iclass 4, count 0 2006.280.07:42:02.71#ibcon#read 4, iclass 4, count 0 2006.280.07:42:02.71#ibcon#about to read 5, iclass 4, count 0 2006.280.07:42:02.71#ibcon#read 5, iclass 4, count 0 2006.280.07:42:02.71#ibcon#about to read 6, iclass 4, count 0 2006.280.07:42:02.71#ibcon#read 6, iclass 4, count 0 2006.280.07:42:02.71#ibcon#end of sib2, iclass 4, count 0 2006.280.07:42:02.71#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:42:02.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:42:02.71#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:42:02.71#ibcon#*before write, iclass 4, count 0 2006.280.07:42:02.71#ibcon#enter sib2, iclass 4, count 0 2006.280.07:42:02.71#ibcon#flushed, iclass 4, count 0 2006.280.07:42:02.71#ibcon#about to write, iclass 4, count 0 2006.280.07:42:02.71#ibcon#wrote, iclass 4, count 0 2006.280.07:42:02.71#ibcon#about to read 3, iclass 4, count 0 2006.280.07:42:02.75#ibcon#read 3, iclass 4, count 0 2006.280.07:42:02.75#ibcon#about to read 4, iclass 4, count 0 2006.280.07:42:02.75#ibcon#read 4, iclass 4, count 0 2006.280.07:42:02.75#ibcon#about to read 5, iclass 4, count 0 2006.280.07:42:02.75#ibcon#read 5, iclass 4, count 0 2006.280.07:42:02.75#ibcon#about to read 6, iclass 4, count 0 2006.280.07:42:02.75#ibcon#read 6, iclass 4, count 0 2006.280.07:42:02.75#ibcon#end of sib2, iclass 4, count 0 2006.280.07:42:02.75#ibcon#*after write, iclass 4, count 0 2006.280.07:42:02.75#ibcon#*before return 0, iclass 4, count 0 2006.280.07:42:02.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:42:02.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:42:02.75#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:42:02.75#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:42:02.75$vc4f8/vb=6,4 2006.280.07:42:02.75#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:42:02.75#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:42:02.75#ibcon#ireg 11 cls_cnt 2 2006.280.07:42:02.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:42:02.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:42:02.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:42:02.81#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:42:02.81#ibcon#first serial, iclass 6, count 2 2006.280.07:42:02.81#ibcon#enter sib2, iclass 6, count 2 2006.280.07:42:02.81#ibcon#flushed, iclass 6, count 2 2006.280.07:42:02.81#ibcon#about to write, iclass 6, count 2 2006.280.07:42:02.81#ibcon#wrote, iclass 6, count 2 2006.280.07:42:02.81#ibcon#about to read 3, iclass 6, count 2 2006.280.07:42:02.83#ibcon#read 3, iclass 6, count 2 2006.280.07:42:02.83#ibcon#about to read 4, iclass 6, count 2 2006.280.07:42:02.83#ibcon#read 4, iclass 6, count 2 2006.280.07:42:02.83#ibcon#about to read 5, iclass 6, count 2 2006.280.07:42:02.83#ibcon#read 5, iclass 6, count 2 2006.280.07:42:02.83#ibcon#about to read 6, iclass 6, count 2 2006.280.07:42:02.83#ibcon#read 6, iclass 6, count 2 2006.280.07:42:02.83#ibcon#end of sib2, iclass 6, count 2 2006.280.07:42:02.83#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:42:02.83#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:42:02.83#ibcon#[27=AT06-04\r\n] 2006.280.07:42:02.83#ibcon#*before write, iclass 6, count 2 2006.280.07:42:02.83#ibcon#enter sib2, iclass 6, count 2 2006.280.07:42:02.83#ibcon#flushed, iclass 6, count 2 2006.280.07:42:02.83#ibcon#about to write, iclass 6, count 2 2006.280.07:42:02.83#ibcon#wrote, iclass 6, count 2 2006.280.07:42:02.83#ibcon#about to read 3, iclass 6, count 2 2006.280.07:42:02.87#ibcon#read 3, iclass 6, count 2 2006.280.07:42:02.87#ibcon#about to read 4, iclass 6, count 2 2006.280.07:42:02.87#ibcon#read 4, iclass 6, count 2 2006.280.07:42:02.87#ibcon#about to read 5, iclass 6, count 2 2006.280.07:42:02.87#ibcon#read 5, iclass 6, count 2 2006.280.07:42:02.87#ibcon#about to read 6, iclass 6, count 2 2006.280.07:42:02.87#ibcon#read 6, iclass 6, count 2 2006.280.07:42:02.87#ibcon#end of sib2, iclass 6, count 2 2006.280.07:42:02.87#ibcon#*after write, iclass 6, count 2 2006.280.07:42:02.87#ibcon#*before return 0, iclass 6, count 2 2006.280.07:42:02.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:42:02.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:42:02.87#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:42:02.87#ibcon#ireg 7 cls_cnt 0 2006.280.07:42:02.87#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:02.98#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:02.98#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:02.98#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:42:02.98#ibcon#first serial, iclass 6, count 0 2006.280.07:42:02.98#ibcon#enter sib2, iclass 6, count 0 2006.280.07:42:02.98#ibcon#flushed, iclass 6, count 0 2006.280.07:42:02.98#ibcon#about to write, iclass 6, count 0 2006.280.07:42:02.98#ibcon#wrote, iclass 6, count 0 2006.280.07:42:02.98#ibcon#about to read 3, iclass 6, count 0 2006.280.07:42:03.00#ibcon#read 3, iclass 6, count 0 2006.280.07:42:03.00#ibcon#about to read 4, iclass 6, count 0 2006.280.07:42:03.00#ibcon#read 4, iclass 6, count 0 2006.280.07:42:03.00#ibcon#about to read 5, iclass 6, count 0 2006.280.07:42:03.00#ibcon#read 5, iclass 6, count 0 2006.280.07:42:03.00#ibcon#about to read 6, iclass 6, count 0 2006.280.07:42:03.00#ibcon#read 6, iclass 6, count 0 2006.280.07:42:03.00#ibcon#end of sib2, iclass 6, count 0 2006.280.07:42:03.00#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:42:03.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:42:03.00#ibcon#[27=USB\r\n] 2006.280.07:42:03.00#ibcon#*before write, iclass 6, count 0 2006.280.07:42:03.00#ibcon#enter sib2, iclass 6, count 0 2006.280.07:42:03.00#ibcon#flushed, iclass 6, count 0 2006.280.07:42:03.00#ibcon#about to write, iclass 6, count 0 2006.280.07:42:03.00#ibcon#wrote, iclass 6, count 0 2006.280.07:42:03.00#ibcon#about to read 3, iclass 6, count 0 2006.280.07:42:03.03#ibcon#read 3, iclass 6, count 0 2006.280.07:42:03.03#ibcon#about to read 4, iclass 6, count 0 2006.280.07:42:03.03#ibcon#read 4, iclass 6, count 0 2006.280.07:42:03.03#ibcon#about to read 5, iclass 6, count 0 2006.280.07:42:03.03#ibcon#read 5, iclass 6, count 0 2006.280.07:42:03.03#ibcon#about to read 6, iclass 6, count 0 2006.280.07:42:03.03#ibcon#read 6, iclass 6, count 0 2006.280.07:42:03.03#ibcon#end of sib2, iclass 6, count 0 2006.280.07:42:03.03#ibcon#*after write, iclass 6, count 0 2006.280.07:42:03.03#ibcon#*before return 0, iclass 6, count 0 2006.280.07:42:03.03#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:03.03#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:42:03.03#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:42:03.03#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:42:03.03$vc4f8/vabw=wide 2006.280.07:42:03.03#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:42:03.03#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:42:03.03#ibcon#ireg 8 cls_cnt 0 2006.280.07:42:03.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:03.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:03.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:03.04#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:42:03.04#ibcon#first serial, iclass 10, count 0 2006.280.07:42:03.04#ibcon#enter sib2, iclass 10, count 0 2006.280.07:42:03.04#ibcon#flushed, iclass 10, count 0 2006.280.07:42:03.04#ibcon#about to write, iclass 10, count 0 2006.280.07:42:03.04#ibcon#wrote, iclass 10, count 0 2006.280.07:42:03.04#ibcon#about to read 3, iclass 10, count 0 2006.280.07:42:03.05#ibcon#read 3, iclass 10, count 0 2006.280.07:42:03.05#ibcon#about to read 4, iclass 10, count 0 2006.280.07:42:03.05#ibcon#read 4, iclass 10, count 0 2006.280.07:42:03.05#ibcon#about to read 5, iclass 10, count 0 2006.280.07:42:03.05#ibcon#read 5, iclass 10, count 0 2006.280.07:42:03.05#ibcon#about to read 6, iclass 10, count 0 2006.280.07:42:03.05#ibcon#read 6, iclass 10, count 0 2006.280.07:42:03.05#ibcon#end of sib2, iclass 10, count 0 2006.280.07:42:03.05#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:42:03.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:42:03.05#ibcon#[25=BW32\r\n] 2006.280.07:42:03.05#ibcon#*before write, iclass 10, count 0 2006.280.07:42:03.05#ibcon#enter sib2, iclass 10, count 0 2006.280.07:42:03.05#ibcon#flushed, iclass 10, count 0 2006.280.07:42:03.05#ibcon#about to write, iclass 10, count 0 2006.280.07:42:03.05#ibcon#wrote, iclass 10, count 0 2006.280.07:42:03.05#ibcon#about to read 3, iclass 10, count 0 2006.280.07:42:03.08#ibcon#read 3, iclass 10, count 0 2006.280.07:42:03.08#ibcon#about to read 4, iclass 10, count 0 2006.280.07:42:03.08#ibcon#read 4, iclass 10, count 0 2006.280.07:42:03.08#ibcon#about to read 5, iclass 10, count 0 2006.280.07:42:03.08#ibcon#read 5, iclass 10, count 0 2006.280.07:42:03.08#ibcon#about to read 6, iclass 10, count 0 2006.280.07:42:03.08#ibcon#read 6, iclass 10, count 0 2006.280.07:42:03.08#ibcon#end of sib2, iclass 10, count 0 2006.280.07:42:03.08#ibcon#*after write, iclass 10, count 0 2006.280.07:42:03.08#ibcon#*before return 0, iclass 10, count 0 2006.280.07:42:03.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:03.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:42:03.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:42:03.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:42:03.08$vc4f8/vbbw=wide 2006.280.07:42:03.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.07:42:03.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.07:42:03.11#ibcon#ireg 8 cls_cnt 0 2006.280.07:42:03.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:42:03.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:42:03.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:42:03.15#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:42:03.15#ibcon#first serial, iclass 12, count 0 2006.280.07:42:03.15#ibcon#enter sib2, iclass 12, count 0 2006.280.07:42:03.15#ibcon#flushed, iclass 12, count 0 2006.280.07:42:03.15#ibcon#about to write, iclass 12, count 0 2006.280.07:42:03.15#ibcon#wrote, iclass 12, count 0 2006.280.07:42:03.15#ibcon#about to read 3, iclass 12, count 0 2006.280.07:42:03.16#ibcon#read 3, iclass 12, count 0 2006.280.07:42:03.16#ibcon#about to read 4, iclass 12, count 0 2006.280.07:42:03.16#ibcon#read 4, iclass 12, count 0 2006.280.07:42:03.16#ibcon#about to read 5, iclass 12, count 0 2006.280.07:42:03.16#ibcon#read 5, iclass 12, count 0 2006.280.07:42:03.16#ibcon#about to read 6, iclass 12, count 0 2006.280.07:42:03.16#ibcon#read 6, iclass 12, count 0 2006.280.07:42:03.16#ibcon#end of sib2, iclass 12, count 0 2006.280.07:42:03.16#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:42:03.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:42:03.16#ibcon#[27=BW32\r\n] 2006.280.07:42:03.16#ibcon#*before write, iclass 12, count 0 2006.280.07:42:03.16#ibcon#enter sib2, iclass 12, count 0 2006.280.07:42:03.16#ibcon#flushed, iclass 12, count 0 2006.280.07:42:03.16#ibcon#about to write, iclass 12, count 0 2006.280.07:42:03.16#ibcon#wrote, iclass 12, count 0 2006.280.07:42:03.16#ibcon#about to read 3, iclass 12, count 0 2006.280.07:42:03.19#ibcon#read 3, iclass 12, count 0 2006.280.07:42:03.19#ibcon#about to read 4, iclass 12, count 0 2006.280.07:42:03.19#ibcon#read 4, iclass 12, count 0 2006.280.07:42:03.19#ibcon#about to read 5, iclass 12, count 0 2006.280.07:42:03.19#ibcon#read 5, iclass 12, count 0 2006.280.07:42:03.19#ibcon#about to read 6, iclass 12, count 0 2006.280.07:42:03.19#ibcon#read 6, iclass 12, count 0 2006.280.07:42:03.19#ibcon#end of sib2, iclass 12, count 0 2006.280.07:42:03.19#ibcon#*after write, iclass 12, count 0 2006.280.07:42:03.19#ibcon#*before return 0, iclass 12, count 0 2006.280.07:42:03.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:42:03.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:42:03.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:42:03.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:42:03.19$4f8m12a/ifd4f 2006.280.07:42:03.20$ifd4f/lo= 2006.280.07:42:03.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:42:03.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:42:03.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:42:03.20$ifd4f/patch= 2006.280.07:42:03.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:42:03.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:42:03.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:42:03.20$4f8m12a/"form=m,16.000,1:2 2006.280.07:42:03.20$4f8m12a/"tpicd 2006.280.07:42:03.20$4f8m12a/echo=off 2006.280.07:42:03.20$4f8m12a/xlog=off 2006.280.07:42:03.20:!2006.280.07:42:30 2006.280.07:42:17.14#trakl#Source acquired 2006.280.07:42:18.14#flagr#flagr/antenna,acquired 2006.280.07:42:30.01:preob 2006.280.07:42:31.14/onsource/TRACKING 2006.280.07:42:31.14:!2006.280.07:42:40 2006.280.07:42:40.01:data_valid=on 2006.280.07:42:40.02:midob 2006.280.07:42:41.13/onsource/TRACKING 2006.280.07:42:41.14/wx/21.55,986.8,59 2006.280.07:42:41.26/cable/+6.4826E-03 2006.280.07:42:42.35/va/01,07,usb,yes,39,41 2006.280.07:42:42.35/va/02,06,usb,yes,37,38 2006.280.07:42:42.35/va/03,06,usb,yes,35,35 2006.280.07:42:42.35/va/04,06,usb,yes,38,41 2006.280.07:42:42.35/va/05,07,usb,yes,35,37 2006.280.07:42:42.35/va/06,06,usb,yes,34,34 2006.280.07:42:42.35/va/07,06,usb,yes,35,34 2006.280.07:42:42.35/va/08,06,usb,yes,37,36 2006.280.07:42:42.58/valo/01,532.99,yes,locked 2006.280.07:42:42.58/valo/02,572.99,yes,locked 2006.280.07:42:42.58/valo/03,672.99,yes,locked 2006.280.07:42:42.58/valo/04,832.99,yes,locked 2006.280.07:42:42.58/valo/05,652.99,yes,locked 2006.280.07:42:42.58/valo/06,772.99,yes,locked 2006.280.07:42:42.58/valo/07,832.99,yes,locked 2006.280.07:42:42.58/valo/08,852.99,yes,locked 2006.280.07:42:43.67/vb/01,04,usb,yes,34,32 2006.280.07:42:43.67/vb/02,05,usb,yes,32,33 2006.280.07:42:43.67/vb/03,04,usb,yes,32,36 2006.280.07:42:43.67/vb/04,04,usb,yes,33,33 2006.280.07:42:43.67/vb/05,04,usb,yes,31,36 2006.280.07:42:43.67/vb/06,04,usb,yes,32,35 2006.280.07:42:43.67/vb/07,04,usb,yes,35,35 2006.280.07:42:43.67/vb/08,04,usb,yes,31,35 2006.280.07:42:43.90/vblo/01,632.99,yes,locked 2006.280.07:42:43.90/vblo/02,640.99,yes,locked 2006.280.07:42:43.90/vblo/03,656.99,yes,locked 2006.280.07:42:43.90/vblo/04,712.99,yes,locked 2006.280.07:42:43.90/vblo/05,744.99,yes,locked 2006.280.07:42:43.90/vblo/06,752.99,yes,locked 2006.280.07:42:43.90/vblo/07,734.99,yes,locked 2006.280.07:42:43.90/vblo/08,744.99,yes,locked 2006.280.07:42:44.05/vabw/8 2006.280.07:42:44.20/vbbw/8 2006.280.07:42:44.29/xfe/off,on,12.2 2006.280.07:42:44.66/ifatt/23,28,28,28 2006.280.07:42:45.07/fmout-gps/S +3.04E-07 2006.280.07:42:45.10:!2006.280.07:43:40 2006.280.07:43:40.01:data_valid=off 2006.280.07:43:40.02:postob 2006.280.07:43:40.18/cable/+6.4821E-03 2006.280.07:43:40.19/wx/21.50,986.8,59 2006.280.07:43:41.07/fmout-gps/S +3.05E-07 2006.280.07:43:41.08:scan_name=280-0744,k06280,60 2006.280.07:43:41.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.280.07:43:42.13#flagr#flagr/antenna,new-source 2006.280.07:43:42.14:checkk5 2006.280.07:43:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:43:42.94/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:43:43.31/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:43:43.75/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:43:44.12/chk_obsdata//k5ts1/T2800742??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:43:44.56/chk_obsdata//k5ts2/T2800742??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:43:44.93/chk_obsdata//k5ts3/T2800742??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:43:45.31/chk_obsdata//k5ts4/T2800742??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:43:46.09/k5log//k5ts1_log_newline 2006.280.07:43:46.79/k5log//k5ts2_log_newline 2006.280.07:43:47.50/k5log//k5ts3_log_newline 2006.280.07:43:48.27/k5log//k5ts4_log_newline 2006.280.07:43:48.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:43:48.29:4f8m12a=1 2006.280.07:43:48.29$4f8m12a/echo=on 2006.280.07:43:48.29$4f8m12a/pcalon 2006.280.07:43:48.29$pcalon/"no phase cal control is implemented here 2006.280.07:43:48.29$4f8m12a/"tpicd=stop 2006.280.07:43:48.29$4f8m12a/vc4f8 2006.280.07:43:48.29$vc4f8/valo=1,532.99 2006.280.07:43:48.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:43:48.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:43:48.30#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:48.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:48.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:48.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:48.30#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:43:48.30#ibcon#first serial, iclass 19, count 0 2006.280.07:43:48.30#ibcon#enter sib2, iclass 19, count 0 2006.280.07:43:48.30#ibcon#flushed, iclass 19, count 0 2006.280.07:43:48.30#ibcon#about to write, iclass 19, count 0 2006.280.07:43:48.30#ibcon#wrote, iclass 19, count 0 2006.280.07:43:48.30#ibcon#about to read 3, iclass 19, count 0 2006.280.07:43:48.31#ibcon#read 3, iclass 19, count 0 2006.280.07:43:48.32#ibcon#about to read 4, iclass 19, count 0 2006.280.07:43:48.32#ibcon#read 4, iclass 19, count 0 2006.280.07:43:48.32#ibcon#about to read 5, iclass 19, count 0 2006.280.07:43:48.32#ibcon#read 5, iclass 19, count 0 2006.280.07:43:48.32#ibcon#about to read 6, iclass 19, count 0 2006.280.07:43:48.32#ibcon#read 6, iclass 19, count 0 2006.280.07:43:48.32#ibcon#end of sib2, iclass 19, count 0 2006.280.07:43:48.32#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:43:48.32#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:43:48.32#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:43:48.32#ibcon#*before write, iclass 19, count 0 2006.280.07:43:48.32#ibcon#enter sib2, iclass 19, count 0 2006.280.07:43:48.32#ibcon#flushed, iclass 19, count 0 2006.280.07:43:48.32#ibcon#about to write, iclass 19, count 0 2006.280.07:43:48.32#ibcon#wrote, iclass 19, count 0 2006.280.07:43:48.32#ibcon#about to read 3, iclass 19, count 0 2006.280.07:43:48.36#ibcon#read 3, iclass 19, count 0 2006.280.07:43:48.36#ibcon#about to read 4, iclass 19, count 0 2006.280.07:43:48.36#ibcon#read 4, iclass 19, count 0 2006.280.07:43:48.36#ibcon#about to read 5, iclass 19, count 0 2006.280.07:43:48.36#ibcon#read 5, iclass 19, count 0 2006.280.07:43:48.36#ibcon#about to read 6, iclass 19, count 0 2006.280.07:43:48.36#ibcon#read 6, iclass 19, count 0 2006.280.07:43:48.36#ibcon#end of sib2, iclass 19, count 0 2006.280.07:43:48.36#ibcon#*after write, iclass 19, count 0 2006.280.07:43:48.36#ibcon#*before return 0, iclass 19, count 0 2006.280.07:43:48.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:48.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:48.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:43:48.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:43:48.36$vc4f8/va=1,7 2006.280.07:43:48.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:43:48.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:43:48.36#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:48.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:48.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:48.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:48.36#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:43:48.36#ibcon#first serial, iclass 21, count 2 2006.280.07:43:48.36#ibcon#enter sib2, iclass 21, count 2 2006.280.07:43:48.36#ibcon#flushed, iclass 21, count 2 2006.280.07:43:48.36#ibcon#about to write, iclass 21, count 2 2006.280.07:43:48.36#ibcon#wrote, iclass 21, count 2 2006.280.07:43:48.36#ibcon#about to read 3, iclass 21, count 2 2006.280.07:43:48.38#ibcon#read 3, iclass 21, count 2 2006.280.07:43:48.38#ibcon#about to read 4, iclass 21, count 2 2006.280.07:43:48.38#ibcon#read 4, iclass 21, count 2 2006.280.07:43:48.38#ibcon#about to read 5, iclass 21, count 2 2006.280.07:43:48.38#ibcon#read 5, iclass 21, count 2 2006.280.07:43:48.38#ibcon#about to read 6, iclass 21, count 2 2006.280.07:43:48.38#ibcon#read 6, iclass 21, count 2 2006.280.07:43:48.38#ibcon#end of sib2, iclass 21, count 2 2006.280.07:43:48.38#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:43:48.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:43:48.38#ibcon#[25=AT01-07\r\n] 2006.280.07:43:48.38#ibcon#*before write, iclass 21, count 2 2006.280.07:43:48.38#ibcon#enter sib2, iclass 21, count 2 2006.280.07:43:48.38#ibcon#flushed, iclass 21, count 2 2006.280.07:43:48.38#ibcon#about to write, iclass 21, count 2 2006.280.07:43:48.38#ibcon#wrote, iclass 21, count 2 2006.280.07:43:48.38#ibcon#about to read 3, iclass 21, count 2 2006.280.07:43:48.41#ibcon#read 3, iclass 21, count 2 2006.280.07:43:48.41#ibcon#about to read 4, iclass 21, count 2 2006.280.07:43:48.41#ibcon#read 4, iclass 21, count 2 2006.280.07:43:48.41#ibcon#about to read 5, iclass 21, count 2 2006.280.07:43:48.41#ibcon#read 5, iclass 21, count 2 2006.280.07:43:48.41#ibcon#about to read 6, iclass 21, count 2 2006.280.07:43:48.41#ibcon#read 6, iclass 21, count 2 2006.280.07:43:48.41#ibcon#end of sib2, iclass 21, count 2 2006.280.07:43:48.41#ibcon#*after write, iclass 21, count 2 2006.280.07:43:48.41#ibcon#*before return 0, iclass 21, count 2 2006.280.07:43:48.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:48.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:48.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:43:48.41#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:48.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:48.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:48.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:48.53#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:43:48.53#ibcon#first serial, iclass 21, count 0 2006.280.07:43:48.53#ibcon#enter sib2, iclass 21, count 0 2006.280.07:43:48.53#ibcon#flushed, iclass 21, count 0 2006.280.07:43:48.53#ibcon#about to write, iclass 21, count 0 2006.280.07:43:48.53#ibcon#wrote, iclass 21, count 0 2006.280.07:43:48.53#ibcon#about to read 3, iclass 21, count 0 2006.280.07:43:48.55#ibcon#read 3, iclass 21, count 0 2006.280.07:43:48.55#ibcon#about to read 4, iclass 21, count 0 2006.280.07:43:48.55#ibcon#read 4, iclass 21, count 0 2006.280.07:43:48.55#ibcon#about to read 5, iclass 21, count 0 2006.280.07:43:48.55#ibcon#read 5, iclass 21, count 0 2006.280.07:43:48.55#ibcon#about to read 6, iclass 21, count 0 2006.280.07:43:48.55#ibcon#read 6, iclass 21, count 0 2006.280.07:43:48.55#ibcon#end of sib2, iclass 21, count 0 2006.280.07:43:48.55#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:43:48.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:43:48.55#ibcon#[25=USB\r\n] 2006.280.07:43:48.55#ibcon#*before write, iclass 21, count 0 2006.280.07:43:48.55#ibcon#enter sib2, iclass 21, count 0 2006.280.07:43:48.55#ibcon#flushed, iclass 21, count 0 2006.280.07:43:48.55#ibcon#about to write, iclass 21, count 0 2006.280.07:43:48.55#ibcon#wrote, iclass 21, count 0 2006.280.07:43:48.55#ibcon#about to read 3, iclass 21, count 0 2006.280.07:43:48.58#ibcon#read 3, iclass 21, count 0 2006.280.07:43:48.58#ibcon#about to read 4, iclass 21, count 0 2006.280.07:43:48.58#ibcon#read 4, iclass 21, count 0 2006.280.07:43:48.58#ibcon#about to read 5, iclass 21, count 0 2006.280.07:43:48.58#ibcon#read 5, iclass 21, count 0 2006.280.07:43:48.58#ibcon#about to read 6, iclass 21, count 0 2006.280.07:43:48.58#ibcon#read 6, iclass 21, count 0 2006.280.07:43:48.58#ibcon#end of sib2, iclass 21, count 0 2006.280.07:43:48.58#ibcon#*after write, iclass 21, count 0 2006.280.07:43:48.58#ibcon#*before return 0, iclass 21, count 0 2006.280.07:43:48.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:48.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:48.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:43:48.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:43:48.58$vc4f8/valo=2,572.99 2006.280.07:43:48.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:43:48.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:43:48.58#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:48.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:48.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:48.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:48.58#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:43:48.58#ibcon#first serial, iclass 23, count 0 2006.280.07:43:48.58#ibcon#enter sib2, iclass 23, count 0 2006.280.07:43:48.58#ibcon#flushed, iclass 23, count 0 2006.280.07:43:48.58#ibcon#about to write, iclass 23, count 0 2006.280.07:43:48.58#ibcon#wrote, iclass 23, count 0 2006.280.07:43:48.58#ibcon#about to read 3, iclass 23, count 0 2006.280.07:43:48.60#ibcon#read 3, iclass 23, count 0 2006.280.07:43:48.60#ibcon#about to read 4, iclass 23, count 0 2006.280.07:43:48.61#ibcon#read 4, iclass 23, count 0 2006.280.07:43:48.61#ibcon#about to read 5, iclass 23, count 0 2006.280.07:43:48.61#ibcon#read 5, iclass 23, count 0 2006.280.07:43:48.61#ibcon#about to read 6, iclass 23, count 0 2006.280.07:43:48.61#ibcon#read 6, iclass 23, count 0 2006.280.07:43:48.61#ibcon#end of sib2, iclass 23, count 0 2006.280.07:43:48.61#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:43:48.61#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:43:48.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:43:48.61#ibcon#*before write, iclass 23, count 0 2006.280.07:43:48.61#ibcon#enter sib2, iclass 23, count 0 2006.280.07:43:48.61#ibcon#flushed, iclass 23, count 0 2006.280.07:43:48.61#ibcon#about to write, iclass 23, count 0 2006.280.07:43:48.61#ibcon#wrote, iclass 23, count 0 2006.280.07:43:48.61#ibcon#about to read 3, iclass 23, count 0 2006.280.07:43:48.64#ibcon#read 3, iclass 23, count 0 2006.280.07:43:48.64#ibcon#about to read 4, iclass 23, count 0 2006.280.07:43:48.64#ibcon#read 4, iclass 23, count 0 2006.280.07:43:48.64#ibcon#about to read 5, iclass 23, count 0 2006.280.07:43:48.64#ibcon#read 5, iclass 23, count 0 2006.280.07:43:48.64#ibcon#about to read 6, iclass 23, count 0 2006.280.07:43:48.64#ibcon#read 6, iclass 23, count 0 2006.280.07:43:48.64#ibcon#end of sib2, iclass 23, count 0 2006.280.07:43:48.64#ibcon#*after write, iclass 23, count 0 2006.280.07:43:48.64#ibcon#*before return 0, iclass 23, count 0 2006.280.07:43:48.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:48.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:48.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:43:48.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:43:48.64$vc4f8/va=2,6 2006.280.07:43:48.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.07:43:48.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.07:43:48.64#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:48.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:48.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:48.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:48.71#ibcon#enter wrdev, iclass 25, count 2 2006.280.07:43:48.71#ibcon#first serial, iclass 25, count 2 2006.280.07:43:48.71#ibcon#enter sib2, iclass 25, count 2 2006.280.07:43:48.71#ibcon#flushed, iclass 25, count 2 2006.280.07:43:48.71#ibcon#about to write, iclass 25, count 2 2006.280.07:43:48.71#ibcon#wrote, iclass 25, count 2 2006.280.07:43:48.71#ibcon#about to read 3, iclass 25, count 2 2006.280.07:43:48.72#ibcon#read 3, iclass 25, count 2 2006.280.07:43:48.72#ibcon#about to read 4, iclass 25, count 2 2006.280.07:43:48.72#ibcon#read 4, iclass 25, count 2 2006.280.07:43:48.72#ibcon#about to read 5, iclass 25, count 2 2006.280.07:43:48.72#ibcon#read 5, iclass 25, count 2 2006.280.07:43:48.72#ibcon#about to read 6, iclass 25, count 2 2006.280.07:43:48.72#ibcon#read 6, iclass 25, count 2 2006.280.07:43:48.72#ibcon#end of sib2, iclass 25, count 2 2006.280.07:43:48.72#ibcon#*mode == 0, iclass 25, count 2 2006.280.07:43:48.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.07:43:48.72#ibcon#[25=AT02-06\r\n] 2006.280.07:43:48.72#ibcon#*before write, iclass 25, count 2 2006.280.07:43:48.72#ibcon#enter sib2, iclass 25, count 2 2006.280.07:43:48.72#ibcon#flushed, iclass 25, count 2 2006.280.07:43:48.72#ibcon#about to write, iclass 25, count 2 2006.280.07:43:48.72#ibcon#wrote, iclass 25, count 2 2006.280.07:43:48.72#ibcon#about to read 3, iclass 25, count 2 2006.280.07:43:48.76#ibcon#read 3, iclass 25, count 2 2006.280.07:43:48.76#ibcon#about to read 4, iclass 25, count 2 2006.280.07:43:48.76#ibcon#read 4, iclass 25, count 2 2006.280.07:43:48.76#ibcon#about to read 5, iclass 25, count 2 2006.280.07:43:48.76#ibcon#read 5, iclass 25, count 2 2006.280.07:43:48.76#ibcon#about to read 6, iclass 25, count 2 2006.280.07:43:48.76#ibcon#read 6, iclass 25, count 2 2006.280.07:43:48.76#ibcon#end of sib2, iclass 25, count 2 2006.280.07:43:48.76#ibcon#*after write, iclass 25, count 2 2006.280.07:43:48.76#ibcon#*before return 0, iclass 25, count 2 2006.280.07:43:48.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:48.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:48.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.07:43:48.76#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:48.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:48.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:48.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:48.88#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:43:48.88#ibcon#first serial, iclass 25, count 0 2006.280.07:43:48.88#ibcon#enter sib2, iclass 25, count 0 2006.280.07:43:48.88#ibcon#flushed, iclass 25, count 0 2006.280.07:43:48.88#ibcon#about to write, iclass 25, count 0 2006.280.07:43:48.88#ibcon#wrote, iclass 25, count 0 2006.280.07:43:48.88#ibcon#about to read 3, iclass 25, count 0 2006.280.07:43:48.89#ibcon#read 3, iclass 25, count 0 2006.280.07:43:48.89#ibcon#about to read 4, iclass 25, count 0 2006.280.07:43:48.89#ibcon#read 4, iclass 25, count 0 2006.280.07:43:48.89#ibcon#about to read 5, iclass 25, count 0 2006.280.07:43:48.89#ibcon#read 5, iclass 25, count 0 2006.280.07:43:48.89#ibcon#about to read 6, iclass 25, count 0 2006.280.07:43:48.89#ibcon#read 6, iclass 25, count 0 2006.280.07:43:48.89#ibcon#end of sib2, iclass 25, count 0 2006.280.07:43:48.89#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:43:48.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:43:48.89#ibcon#[25=USB\r\n] 2006.280.07:43:48.89#ibcon#*before write, iclass 25, count 0 2006.280.07:43:48.89#ibcon#enter sib2, iclass 25, count 0 2006.280.07:43:48.89#ibcon#flushed, iclass 25, count 0 2006.280.07:43:48.89#ibcon#about to write, iclass 25, count 0 2006.280.07:43:48.89#ibcon#wrote, iclass 25, count 0 2006.280.07:43:48.89#ibcon#about to read 3, iclass 25, count 0 2006.280.07:43:48.92#ibcon#read 3, iclass 25, count 0 2006.280.07:43:48.92#ibcon#about to read 4, iclass 25, count 0 2006.280.07:43:48.92#ibcon#read 4, iclass 25, count 0 2006.280.07:43:48.92#ibcon#about to read 5, iclass 25, count 0 2006.280.07:43:48.92#ibcon#read 5, iclass 25, count 0 2006.280.07:43:48.92#ibcon#about to read 6, iclass 25, count 0 2006.280.07:43:48.92#ibcon#read 6, iclass 25, count 0 2006.280.07:43:48.92#ibcon#end of sib2, iclass 25, count 0 2006.280.07:43:48.92#ibcon#*after write, iclass 25, count 0 2006.280.07:43:48.92#ibcon#*before return 0, iclass 25, count 0 2006.280.07:43:48.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:48.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:48.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:43:48.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:43:48.92$vc4f8/valo=3,672.99 2006.280.07:43:48.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:43:48.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:43:48.92#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:48.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:48.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:48.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:48.92#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:43:48.92#ibcon#first serial, iclass 27, count 0 2006.280.07:43:48.92#ibcon#enter sib2, iclass 27, count 0 2006.280.07:43:48.92#ibcon#flushed, iclass 27, count 0 2006.280.07:43:48.92#ibcon#about to write, iclass 27, count 0 2006.280.07:43:48.92#ibcon#wrote, iclass 27, count 0 2006.280.07:43:48.92#ibcon#about to read 3, iclass 27, count 0 2006.280.07:43:48.94#ibcon#read 3, iclass 27, count 0 2006.280.07:43:48.94#ibcon#about to read 4, iclass 27, count 0 2006.280.07:43:48.94#ibcon#read 4, iclass 27, count 0 2006.280.07:43:48.94#ibcon#about to read 5, iclass 27, count 0 2006.280.07:43:48.94#ibcon#read 5, iclass 27, count 0 2006.280.07:43:48.94#ibcon#about to read 6, iclass 27, count 0 2006.280.07:43:48.94#ibcon#read 6, iclass 27, count 0 2006.280.07:43:48.94#ibcon#end of sib2, iclass 27, count 0 2006.280.07:43:48.94#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:43:48.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:43:48.94#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:43:48.94#ibcon#*before write, iclass 27, count 0 2006.280.07:43:48.94#ibcon#enter sib2, iclass 27, count 0 2006.280.07:43:48.94#ibcon#flushed, iclass 27, count 0 2006.280.07:43:48.94#ibcon#about to write, iclass 27, count 0 2006.280.07:43:48.94#ibcon#wrote, iclass 27, count 0 2006.280.07:43:48.94#ibcon#about to read 3, iclass 27, count 0 2006.280.07:43:48.98#ibcon#read 3, iclass 27, count 0 2006.280.07:43:48.98#ibcon#about to read 4, iclass 27, count 0 2006.280.07:43:48.98#ibcon#read 4, iclass 27, count 0 2006.280.07:43:48.98#ibcon#about to read 5, iclass 27, count 0 2006.280.07:43:48.98#ibcon#read 5, iclass 27, count 0 2006.280.07:43:48.98#ibcon#about to read 6, iclass 27, count 0 2006.280.07:43:48.98#ibcon#read 6, iclass 27, count 0 2006.280.07:43:48.98#ibcon#end of sib2, iclass 27, count 0 2006.280.07:43:48.98#ibcon#*after write, iclass 27, count 0 2006.280.07:43:48.98#ibcon#*before return 0, iclass 27, count 0 2006.280.07:43:48.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:48.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:48.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:43:48.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:43:48.98$vc4f8/va=3,6 2006.280.07:43:48.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.07:43:48.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.07:43:48.98#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:48.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:49.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:49.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:49.04#ibcon#enter wrdev, iclass 29, count 2 2006.280.07:43:49.04#ibcon#first serial, iclass 29, count 2 2006.280.07:43:49.04#ibcon#enter sib2, iclass 29, count 2 2006.280.07:43:49.04#ibcon#flushed, iclass 29, count 2 2006.280.07:43:49.04#ibcon#about to write, iclass 29, count 2 2006.280.07:43:49.04#ibcon#wrote, iclass 29, count 2 2006.280.07:43:49.04#ibcon#about to read 3, iclass 29, count 2 2006.280.07:43:49.06#ibcon#read 3, iclass 29, count 2 2006.280.07:43:49.06#ibcon#about to read 4, iclass 29, count 2 2006.280.07:43:49.06#ibcon#read 4, iclass 29, count 2 2006.280.07:43:49.06#ibcon#about to read 5, iclass 29, count 2 2006.280.07:43:49.06#ibcon#read 5, iclass 29, count 2 2006.280.07:43:49.06#ibcon#about to read 6, iclass 29, count 2 2006.280.07:43:49.06#ibcon#read 6, iclass 29, count 2 2006.280.07:43:49.06#ibcon#end of sib2, iclass 29, count 2 2006.280.07:43:49.06#ibcon#*mode == 0, iclass 29, count 2 2006.280.07:43:49.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.07:43:49.06#ibcon#[25=AT03-06\r\n] 2006.280.07:43:49.06#ibcon#*before write, iclass 29, count 2 2006.280.07:43:49.06#ibcon#enter sib2, iclass 29, count 2 2006.280.07:43:49.06#ibcon#flushed, iclass 29, count 2 2006.280.07:43:49.06#ibcon#about to write, iclass 29, count 2 2006.280.07:43:49.06#ibcon#wrote, iclass 29, count 2 2006.280.07:43:49.06#ibcon#about to read 3, iclass 29, count 2 2006.280.07:43:49.09#ibcon#read 3, iclass 29, count 2 2006.280.07:43:49.09#ibcon#about to read 4, iclass 29, count 2 2006.280.07:43:49.09#ibcon#read 4, iclass 29, count 2 2006.280.07:43:49.09#ibcon#about to read 5, iclass 29, count 2 2006.280.07:43:49.09#ibcon#read 5, iclass 29, count 2 2006.280.07:43:49.09#ibcon#about to read 6, iclass 29, count 2 2006.280.07:43:49.09#ibcon#read 6, iclass 29, count 2 2006.280.07:43:49.09#ibcon#end of sib2, iclass 29, count 2 2006.280.07:43:49.09#ibcon#*after write, iclass 29, count 2 2006.280.07:43:49.09#ibcon#*before return 0, iclass 29, count 2 2006.280.07:43:49.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:49.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:49.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.07:43:49.09#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:49.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:49.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:49.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:49.21#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:43:49.21#ibcon#first serial, iclass 29, count 0 2006.280.07:43:49.21#ibcon#enter sib2, iclass 29, count 0 2006.280.07:43:49.21#ibcon#flushed, iclass 29, count 0 2006.280.07:43:49.21#ibcon#about to write, iclass 29, count 0 2006.280.07:43:49.21#ibcon#wrote, iclass 29, count 0 2006.280.07:43:49.21#ibcon#about to read 3, iclass 29, count 0 2006.280.07:43:49.23#ibcon#read 3, iclass 29, count 0 2006.280.07:43:49.23#ibcon#about to read 4, iclass 29, count 0 2006.280.07:43:49.23#ibcon#read 4, iclass 29, count 0 2006.280.07:43:49.23#ibcon#about to read 5, iclass 29, count 0 2006.280.07:43:49.23#ibcon#read 5, iclass 29, count 0 2006.280.07:43:49.23#ibcon#about to read 6, iclass 29, count 0 2006.280.07:43:49.23#ibcon#read 6, iclass 29, count 0 2006.280.07:43:49.23#ibcon#end of sib2, iclass 29, count 0 2006.280.07:43:49.23#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:43:49.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:43:49.23#ibcon#[25=USB\r\n] 2006.280.07:43:49.23#ibcon#*before write, iclass 29, count 0 2006.280.07:43:49.23#ibcon#enter sib2, iclass 29, count 0 2006.280.07:43:49.23#ibcon#flushed, iclass 29, count 0 2006.280.07:43:49.23#ibcon#about to write, iclass 29, count 0 2006.280.07:43:49.23#ibcon#wrote, iclass 29, count 0 2006.280.07:43:49.23#ibcon#about to read 3, iclass 29, count 0 2006.280.07:43:49.26#ibcon#read 3, iclass 29, count 0 2006.280.07:43:49.26#ibcon#about to read 4, iclass 29, count 0 2006.280.07:43:49.26#ibcon#read 4, iclass 29, count 0 2006.280.07:43:49.26#ibcon#about to read 5, iclass 29, count 0 2006.280.07:43:49.26#ibcon#read 5, iclass 29, count 0 2006.280.07:43:49.26#ibcon#about to read 6, iclass 29, count 0 2006.280.07:43:49.26#ibcon#read 6, iclass 29, count 0 2006.280.07:43:49.26#ibcon#end of sib2, iclass 29, count 0 2006.280.07:43:49.26#ibcon#*after write, iclass 29, count 0 2006.280.07:43:49.26#ibcon#*before return 0, iclass 29, count 0 2006.280.07:43:49.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:49.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:49.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:43:49.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:43:49.26$vc4f8/valo=4,832.99 2006.280.07:43:49.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:43:49.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:43:49.26#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:49.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:43:49.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:43:49.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:43:49.26#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:43:49.26#ibcon#first serial, iclass 32, count 0 2006.280.07:43:49.26#ibcon#enter sib2, iclass 32, count 0 2006.280.07:43:49.26#ibcon#flushed, iclass 32, count 0 2006.280.07:43:49.26#ibcon#about to write, iclass 32, count 0 2006.280.07:43:49.26#ibcon#wrote, iclass 32, count 0 2006.280.07:43:49.26#ibcon#about to read 3, iclass 32, count 0 2006.280.07:43:49.28#ibcon#read 3, iclass 32, count 0 2006.280.07:43:49.28#ibcon#about to read 4, iclass 32, count 0 2006.280.07:43:49.28#ibcon#read 4, iclass 32, count 0 2006.280.07:43:49.28#ibcon#about to read 5, iclass 32, count 0 2006.280.07:43:49.28#ibcon#read 5, iclass 32, count 0 2006.280.07:43:49.28#ibcon#about to read 6, iclass 32, count 0 2006.280.07:43:49.28#ibcon#read 6, iclass 32, count 0 2006.280.07:43:49.28#ibcon#end of sib2, iclass 32, count 0 2006.280.07:43:49.28#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:43:49.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:43:49.28#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:43:49.28#ibcon#*before write, iclass 32, count 0 2006.280.07:43:49.28#ibcon#enter sib2, iclass 32, count 0 2006.280.07:43:49.28#ibcon#flushed, iclass 32, count 0 2006.280.07:43:49.28#ibcon#about to write, iclass 32, count 0 2006.280.07:43:49.28#ibcon#wrote, iclass 32, count 0 2006.280.07:43:49.28#ibcon#about to read 3, iclass 32, count 0 2006.280.07:43:49.28#abcon#<5=/15 2.6 5.8 21.49 59 986.7\r\n> 2006.280.07:43:49.31#abcon#{5=INTERFACE CLEAR} 2006.280.07:43:49.32#ibcon#read 3, iclass 32, count 0 2006.280.07:43:49.32#ibcon#about to read 4, iclass 32, count 0 2006.280.07:43:49.32#ibcon#read 4, iclass 32, count 0 2006.280.07:43:49.32#ibcon#about to read 5, iclass 32, count 0 2006.280.07:43:49.32#ibcon#read 5, iclass 32, count 0 2006.280.07:43:49.32#ibcon#about to read 6, iclass 32, count 0 2006.280.07:43:49.32#ibcon#read 6, iclass 32, count 0 2006.280.07:43:49.32#ibcon#end of sib2, iclass 32, count 0 2006.280.07:43:49.32#ibcon#*after write, iclass 32, count 0 2006.280.07:43:49.32#ibcon#*before return 0, iclass 32, count 0 2006.280.07:43:49.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:43:49.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:43:49.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:43:49.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:43:49.32$vc4f8/va=4,6 2006.280.07:43:49.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:43:49.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:43:49.32#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:49.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:43:49.37#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:43:49.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:43:49.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:43:49.38#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:43:49.38#ibcon#first serial, iclass 36, count 2 2006.280.07:43:49.38#ibcon#enter sib2, iclass 36, count 2 2006.280.07:43:49.38#ibcon#flushed, iclass 36, count 2 2006.280.07:43:49.38#ibcon#about to write, iclass 36, count 2 2006.280.07:43:49.38#ibcon#wrote, iclass 36, count 2 2006.280.07:43:49.38#ibcon#about to read 3, iclass 36, count 2 2006.280.07:43:49.41#ibcon#read 3, iclass 36, count 2 2006.280.07:43:49.41#ibcon#about to read 4, iclass 36, count 2 2006.280.07:43:49.41#ibcon#read 4, iclass 36, count 2 2006.280.07:43:49.41#ibcon#about to read 5, iclass 36, count 2 2006.280.07:43:49.41#ibcon#read 5, iclass 36, count 2 2006.280.07:43:49.41#ibcon#about to read 6, iclass 36, count 2 2006.280.07:43:49.41#ibcon#read 6, iclass 36, count 2 2006.280.07:43:49.41#ibcon#end of sib2, iclass 36, count 2 2006.280.07:43:49.41#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:43:49.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:43:49.41#ibcon#[25=AT04-06\r\n] 2006.280.07:43:49.41#ibcon#*before write, iclass 36, count 2 2006.280.07:43:49.41#ibcon#enter sib2, iclass 36, count 2 2006.280.07:43:49.41#ibcon#flushed, iclass 36, count 2 2006.280.07:43:49.41#ibcon#about to write, iclass 36, count 2 2006.280.07:43:49.41#ibcon#wrote, iclass 36, count 2 2006.280.07:43:49.41#ibcon#about to read 3, iclass 36, count 2 2006.280.07:43:49.44#ibcon#read 3, iclass 36, count 2 2006.280.07:43:49.44#ibcon#about to read 4, iclass 36, count 2 2006.280.07:43:49.44#ibcon#read 4, iclass 36, count 2 2006.280.07:43:49.44#ibcon#about to read 5, iclass 36, count 2 2006.280.07:43:49.44#ibcon#read 5, iclass 36, count 2 2006.280.07:43:49.44#ibcon#about to read 6, iclass 36, count 2 2006.280.07:43:49.44#ibcon#read 6, iclass 36, count 2 2006.280.07:43:49.44#ibcon#end of sib2, iclass 36, count 2 2006.280.07:43:49.44#ibcon#*after write, iclass 36, count 2 2006.280.07:43:49.44#ibcon#*before return 0, iclass 36, count 2 2006.280.07:43:49.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:43:49.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:43:49.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:43:49.44#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:49.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:43:49.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:43:49.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:43:49.55#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:43:49.55#ibcon#first serial, iclass 36, count 0 2006.280.07:43:49.55#ibcon#enter sib2, iclass 36, count 0 2006.280.07:43:49.55#ibcon#flushed, iclass 36, count 0 2006.280.07:43:49.55#ibcon#about to write, iclass 36, count 0 2006.280.07:43:49.55#ibcon#wrote, iclass 36, count 0 2006.280.07:43:49.55#ibcon#about to read 3, iclass 36, count 0 2006.280.07:43:49.57#ibcon#read 3, iclass 36, count 0 2006.280.07:43:49.57#ibcon#about to read 4, iclass 36, count 0 2006.280.07:43:49.57#ibcon#read 4, iclass 36, count 0 2006.280.07:43:49.57#ibcon#about to read 5, iclass 36, count 0 2006.280.07:43:49.57#ibcon#read 5, iclass 36, count 0 2006.280.07:43:49.57#ibcon#about to read 6, iclass 36, count 0 2006.280.07:43:49.57#ibcon#read 6, iclass 36, count 0 2006.280.07:43:49.57#ibcon#end of sib2, iclass 36, count 0 2006.280.07:43:49.57#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:43:49.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:43:49.57#ibcon#[25=USB\r\n] 2006.280.07:43:49.57#ibcon#*before write, iclass 36, count 0 2006.280.07:43:49.57#ibcon#enter sib2, iclass 36, count 0 2006.280.07:43:49.57#ibcon#flushed, iclass 36, count 0 2006.280.07:43:49.57#ibcon#about to write, iclass 36, count 0 2006.280.07:43:49.57#ibcon#wrote, iclass 36, count 0 2006.280.07:43:49.57#ibcon#about to read 3, iclass 36, count 0 2006.280.07:43:49.60#ibcon#read 3, iclass 36, count 0 2006.280.07:43:49.60#ibcon#about to read 4, iclass 36, count 0 2006.280.07:43:49.60#ibcon#read 4, iclass 36, count 0 2006.280.07:43:49.60#ibcon#about to read 5, iclass 36, count 0 2006.280.07:43:49.60#ibcon#read 5, iclass 36, count 0 2006.280.07:43:49.60#ibcon#about to read 6, iclass 36, count 0 2006.280.07:43:49.60#ibcon#read 6, iclass 36, count 0 2006.280.07:43:49.60#ibcon#end of sib2, iclass 36, count 0 2006.280.07:43:49.60#ibcon#*after write, iclass 36, count 0 2006.280.07:43:49.60#ibcon#*before return 0, iclass 36, count 0 2006.280.07:43:49.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:43:49.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:43:49.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:43:49.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:43:49.60$vc4f8/valo=5,652.99 2006.280.07:43:49.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:43:49.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:43:49.60#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:49.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:49.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:49.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:49.60#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:43:49.60#ibcon#first serial, iclass 39, count 0 2006.280.07:43:49.60#ibcon#enter sib2, iclass 39, count 0 2006.280.07:43:49.60#ibcon#flushed, iclass 39, count 0 2006.280.07:43:49.60#ibcon#about to write, iclass 39, count 0 2006.280.07:43:49.60#ibcon#wrote, iclass 39, count 0 2006.280.07:43:49.60#ibcon#about to read 3, iclass 39, count 0 2006.280.07:43:49.62#ibcon#read 3, iclass 39, count 0 2006.280.07:43:49.62#ibcon#about to read 4, iclass 39, count 0 2006.280.07:43:49.62#ibcon#read 4, iclass 39, count 0 2006.280.07:43:49.62#ibcon#about to read 5, iclass 39, count 0 2006.280.07:43:49.62#ibcon#read 5, iclass 39, count 0 2006.280.07:43:49.62#ibcon#about to read 6, iclass 39, count 0 2006.280.07:43:49.62#ibcon#read 6, iclass 39, count 0 2006.280.07:43:49.62#ibcon#end of sib2, iclass 39, count 0 2006.280.07:43:49.62#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:43:49.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:43:49.65#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:43:49.65#ibcon#*before write, iclass 39, count 0 2006.280.07:43:49.65#ibcon#enter sib2, iclass 39, count 0 2006.280.07:43:49.65#ibcon#flushed, iclass 39, count 0 2006.280.07:43:49.65#ibcon#about to write, iclass 39, count 0 2006.280.07:43:49.65#ibcon#wrote, iclass 39, count 0 2006.280.07:43:49.65#ibcon#about to read 3, iclass 39, count 0 2006.280.07:43:49.69#ibcon#read 3, iclass 39, count 0 2006.280.07:43:49.69#ibcon#about to read 4, iclass 39, count 0 2006.280.07:43:49.69#ibcon#read 4, iclass 39, count 0 2006.280.07:43:49.69#ibcon#about to read 5, iclass 39, count 0 2006.280.07:43:49.69#ibcon#read 5, iclass 39, count 0 2006.280.07:43:49.69#ibcon#about to read 6, iclass 39, count 0 2006.280.07:43:49.69#ibcon#read 6, iclass 39, count 0 2006.280.07:43:49.69#ibcon#end of sib2, iclass 39, count 0 2006.280.07:43:49.69#ibcon#*after write, iclass 39, count 0 2006.280.07:43:49.69#ibcon#*before return 0, iclass 39, count 0 2006.280.07:43:49.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:49.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:49.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:43:49.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:43:49.69$vc4f8/va=5,7 2006.280.07:43:49.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.07:43:49.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.07:43:49.69#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:49.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:49.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:49.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:49.72#ibcon#enter wrdev, iclass 3, count 2 2006.280.07:43:49.72#ibcon#first serial, iclass 3, count 2 2006.280.07:43:49.72#ibcon#enter sib2, iclass 3, count 2 2006.280.07:43:49.72#ibcon#flushed, iclass 3, count 2 2006.280.07:43:49.72#ibcon#about to write, iclass 3, count 2 2006.280.07:43:49.72#ibcon#wrote, iclass 3, count 2 2006.280.07:43:49.72#ibcon#about to read 3, iclass 3, count 2 2006.280.07:43:49.74#ibcon#read 3, iclass 3, count 2 2006.280.07:43:49.74#ibcon#about to read 4, iclass 3, count 2 2006.280.07:43:49.74#ibcon#read 4, iclass 3, count 2 2006.280.07:43:49.74#ibcon#about to read 5, iclass 3, count 2 2006.280.07:43:49.74#ibcon#read 5, iclass 3, count 2 2006.280.07:43:49.74#ibcon#about to read 6, iclass 3, count 2 2006.280.07:43:49.74#ibcon#read 6, iclass 3, count 2 2006.280.07:43:49.74#ibcon#end of sib2, iclass 3, count 2 2006.280.07:43:49.74#ibcon#*mode == 0, iclass 3, count 2 2006.280.07:43:49.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.07:43:49.74#ibcon#[25=AT05-07\r\n] 2006.280.07:43:49.74#ibcon#*before write, iclass 3, count 2 2006.280.07:43:49.74#ibcon#enter sib2, iclass 3, count 2 2006.280.07:43:49.74#ibcon#flushed, iclass 3, count 2 2006.280.07:43:49.74#ibcon#about to write, iclass 3, count 2 2006.280.07:43:49.74#ibcon#wrote, iclass 3, count 2 2006.280.07:43:49.74#ibcon#about to read 3, iclass 3, count 2 2006.280.07:43:49.77#ibcon#read 3, iclass 3, count 2 2006.280.07:43:49.77#ibcon#about to read 4, iclass 3, count 2 2006.280.07:43:49.77#ibcon#read 4, iclass 3, count 2 2006.280.07:43:49.77#ibcon#about to read 5, iclass 3, count 2 2006.280.07:43:49.77#ibcon#read 5, iclass 3, count 2 2006.280.07:43:49.77#ibcon#about to read 6, iclass 3, count 2 2006.280.07:43:49.77#ibcon#read 6, iclass 3, count 2 2006.280.07:43:49.77#ibcon#end of sib2, iclass 3, count 2 2006.280.07:43:49.77#ibcon#*after write, iclass 3, count 2 2006.280.07:43:49.77#ibcon#*before return 0, iclass 3, count 2 2006.280.07:43:49.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:49.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:49.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.07:43:49.77#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:49.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:49.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:49.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:49.89#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:43:49.89#ibcon#first serial, iclass 3, count 0 2006.280.07:43:49.89#ibcon#enter sib2, iclass 3, count 0 2006.280.07:43:49.89#ibcon#flushed, iclass 3, count 0 2006.280.07:43:49.89#ibcon#about to write, iclass 3, count 0 2006.280.07:43:49.89#ibcon#wrote, iclass 3, count 0 2006.280.07:43:49.89#ibcon#about to read 3, iclass 3, count 0 2006.280.07:43:49.91#ibcon#read 3, iclass 3, count 0 2006.280.07:43:49.91#ibcon#about to read 4, iclass 3, count 0 2006.280.07:43:49.91#ibcon#read 4, iclass 3, count 0 2006.280.07:43:49.91#ibcon#about to read 5, iclass 3, count 0 2006.280.07:43:49.91#ibcon#read 5, iclass 3, count 0 2006.280.07:43:49.91#ibcon#about to read 6, iclass 3, count 0 2006.280.07:43:49.91#ibcon#read 6, iclass 3, count 0 2006.280.07:43:49.91#ibcon#end of sib2, iclass 3, count 0 2006.280.07:43:49.91#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:43:49.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:43:49.91#ibcon#[25=USB\r\n] 2006.280.07:43:49.91#ibcon#*before write, iclass 3, count 0 2006.280.07:43:49.91#ibcon#enter sib2, iclass 3, count 0 2006.280.07:43:49.91#ibcon#flushed, iclass 3, count 0 2006.280.07:43:49.91#ibcon#about to write, iclass 3, count 0 2006.280.07:43:49.91#ibcon#wrote, iclass 3, count 0 2006.280.07:43:49.91#ibcon#about to read 3, iclass 3, count 0 2006.280.07:43:49.94#ibcon#read 3, iclass 3, count 0 2006.280.07:43:49.94#ibcon#about to read 4, iclass 3, count 0 2006.280.07:43:49.94#ibcon#read 4, iclass 3, count 0 2006.280.07:43:49.94#ibcon#about to read 5, iclass 3, count 0 2006.280.07:43:49.94#ibcon#read 5, iclass 3, count 0 2006.280.07:43:49.94#ibcon#about to read 6, iclass 3, count 0 2006.280.07:43:49.94#ibcon#read 6, iclass 3, count 0 2006.280.07:43:49.94#ibcon#end of sib2, iclass 3, count 0 2006.280.07:43:49.94#ibcon#*after write, iclass 3, count 0 2006.280.07:43:49.94#ibcon#*before return 0, iclass 3, count 0 2006.280.07:43:49.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:49.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:49.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:43:49.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:43:49.94$vc4f8/valo=6,772.99 2006.280.07:43:49.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.07:43:49.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.07:43:49.94#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:49.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:49.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:49.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:49.94#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:43:49.94#ibcon#first serial, iclass 5, count 0 2006.280.07:43:49.94#ibcon#enter sib2, iclass 5, count 0 2006.280.07:43:49.94#ibcon#flushed, iclass 5, count 0 2006.280.07:43:49.94#ibcon#about to write, iclass 5, count 0 2006.280.07:43:49.94#ibcon#wrote, iclass 5, count 0 2006.280.07:43:49.94#ibcon#about to read 3, iclass 5, count 0 2006.280.07:43:49.96#ibcon#read 3, iclass 5, count 0 2006.280.07:43:49.96#ibcon#about to read 4, iclass 5, count 0 2006.280.07:43:49.97#ibcon#read 4, iclass 5, count 0 2006.280.07:43:49.97#ibcon#about to read 5, iclass 5, count 0 2006.280.07:43:49.97#ibcon#read 5, iclass 5, count 0 2006.280.07:43:49.97#ibcon#about to read 6, iclass 5, count 0 2006.280.07:43:49.97#ibcon#read 6, iclass 5, count 0 2006.280.07:43:49.97#ibcon#end of sib2, iclass 5, count 0 2006.280.07:43:49.97#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:43:49.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:43:49.97#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:43:49.97#ibcon#*before write, iclass 5, count 0 2006.280.07:43:49.97#ibcon#enter sib2, iclass 5, count 0 2006.280.07:43:49.97#ibcon#flushed, iclass 5, count 0 2006.280.07:43:49.97#ibcon#about to write, iclass 5, count 0 2006.280.07:43:49.97#ibcon#wrote, iclass 5, count 0 2006.280.07:43:49.97#ibcon#about to read 3, iclass 5, count 0 2006.280.07:43:50.00#ibcon#read 3, iclass 5, count 0 2006.280.07:43:50.00#ibcon#about to read 4, iclass 5, count 0 2006.280.07:43:50.00#ibcon#read 4, iclass 5, count 0 2006.280.07:43:50.00#ibcon#about to read 5, iclass 5, count 0 2006.280.07:43:50.00#ibcon#read 5, iclass 5, count 0 2006.280.07:43:50.00#ibcon#about to read 6, iclass 5, count 0 2006.280.07:43:50.00#ibcon#read 6, iclass 5, count 0 2006.280.07:43:50.00#ibcon#end of sib2, iclass 5, count 0 2006.280.07:43:50.00#ibcon#*after write, iclass 5, count 0 2006.280.07:43:50.00#ibcon#*before return 0, iclass 5, count 0 2006.280.07:43:50.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:50.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:50.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:43:50.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:43:50.00$vc4f8/va=6,6 2006.280.07:43:50.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.07:43:50.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.07:43:50.00#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:50.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:50.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:50.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:50.06#ibcon#enter wrdev, iclass 7, count 2 2006.280.07:43:50.06#ibcon#first serial, iclass 7, count 2 2006.280.07:43:50.06#ibcon#enter sib2, iclass 7, count 2 2006.280.07:43:50.06#ibcon#flushed, iclass 7, count 2 2006.280.07:43:50.06#ibcon#about to write, iclass 7, count 2 2006.280.07:43:50.06#ibcon#wrote, iclass 7, count 2 2006.280.07:43:50.06#ibcon#about to read 3, iclass 7, count 2 2006.280.07:43:50.08#ibcon#read 3, iclass 7, count 2 2006.280.07:43:50.08#ibcon#about to read 4, iclass 7, count 2 2006.280.07:43:50.08#ibcon#read 4, iclass 7, count 2 2006.280.07:43:50.08#ibcon#about to read 5, iclass 7, count 2 2006.280.07:43:50.08#ibcon#read 5, iclass 7, count 2 2006.280.07:43:50.08#ibcon#about to read 6, iclass 7, count 2 2006.280.07:43:50.08#ibcon#read 6, iclass 7, count 2 2006.280.07:43:50.08#ibcon#end of sib2, iclass 7, count 2 2006.280.07:43:50.08#ibcon#*mode == 0, iclass 7, count 2 2006.280.07:43:50.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.07:43:50.08#ibcon#[25=AT06-06\r\n] 2006.280.07:43:50.08#ibcon#*before write, iclass 7, count 2 2006.280.07:43:50.08#ibcon#enter sib2, iclass 7, count 2 2006.280.07:43:50.08#ibcon#flushed, iclass 7, count 2 2006.280.07:43:50.08#ibcon#about to write, iclass 7, count 2 2006.280.07:43:50.08#ibcon#wrote, iclass 7, count 2 2006.280.07:43:50.08#ibcon#about to read 3, iclass 7, count 2 2006.280.07:43:50.11#ibcon#read 3, iclass 7, count 2 2006.280.07:43:50.11#ibcon#about to read 4, iclass 7, count 2 2006.280.07:43:50.11#ibcon#read 4, iclass 7, count 2 2006.280.07:43:50.11#ibcon#about to read 5, iclass 7, count 2 2006.280.07:43:50.11#ibcon#read 5, iclass 7, count 2 2006.280.07:43:50.11#ibcon#about to read 6, iclass 7, count 2 2006.280.07:43:50.11#ibcon#read 6, iclass 7, count 2 2006.280.07:43:50.11#ibcon#end of sib2, iclass 7, count 2 2006.280.07:43:50.11#ibcon#*after write, iclass 7, count 2 2006.280.07:43:50.11#ibcon#*before return 0, iclass 7, count 2 2006.280.07:43:50.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:50.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:50.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.07:43:50.11#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:50.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:43:50.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:43:50.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:43:50.24#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:43:50.24#ibcon#first serial, iclass 7, count 0 2006.280.07:43:50.24#ibcon#enter sib2, iclass 7, count 0 2006.280.07:43:50.24#ibcon#flushed, iclass 7, count 0 2006.280.07:43:50.24#ibcon#about to write, iclass 7, count 0 2006.280.07:43:50.24#ibcon#wrote, iclass 7, count 0 2006.280.07:43:50.24#ibcon#about to read 3, iclass 7, count 0 2006.280.07:43:50.25#ibcon#read 3, iclass 7, count 0 2006.280.07:43:50.25#ibcon#about to read 4, iclass 7, count 0 2006.280.07:43:50.25#ibcon#read 4, iclass 7, count 0 2006.280.07:43:50.25#ibcon#about to read 5, iclass 7, count 0 2006.280.07:43:50.25#ibcon#read 5, iclass 7, count 0 2006.280.07:43:50.25#ibcon#about to read 6, iclass 7, count 0 2006.280.07:43:50.25#ibcon#read 6, iclass 7, count 0 2006.280.07:43:50.25#ibcon#end of sib2, iclass 7, count 0 2006.280.07:43:50.25#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:43:50.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:43:50.25#ibcon#[25=USB\r\n] 2006.280.07:43:50.25#ibcon#*before write, iclass 7, count 0 2006.280.07:43:50.25#ibcon#enter sib2, iclass 7, count 0 2006.280.07:43:50.25#ibcon#flushed, iclass 7, count 0 2006.280.07:43:50.25#ibcon#about to write, iclass 7, count 0 2006.280.07:43:50.25#ibcon#wrote, iclass 7, count 0 2006.280.07:43:50.25#ibcon#about to read 3, iclass 7, count 0 2006.280.07:43:50.28#ibcon#read 3, iclass 7, count 0 2006.280.07:43:50.28#ibcon#about to read 4, iclass 7, count 0 2006.280.07:43:50.28#ibcon#read 4, iclass 7, count 0 2006.280.07:43:50.28#ibcon#about to read 5, iclass 7, count 0 2006.280.07:43:50.28#ibcon#read 5, iclass 7, count 0 2006.280.07:43:50.28#ibcon#about to read 6, iclass 7, count 0 2006.280.07:43:50.28#ibcon#read 6, iclass 7, count 0 2006.280.07:43:50.28#ibcon#end of sib2, iclass 7, count 0 2006.280.07:43:50.28#ibcon#*after write, iclass 7, count 0 2006.280.07:43:50.28#ibcon#*before return 0, iclass 7, count 0 2006.280.07:43:50.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:43:50.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:43:50.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:43:50.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:43:50.28$vc4f8/valo=7,832.99 2006.280.07:43:50.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.07:43:50.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.07:43:50.28#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:50.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:43:50.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:43:50.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:43:50.28#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:43:50.28#ibcon#first serial, iclass 11, count 0 2006.280.07:43:50.28#ibcon#enter sib2, iclass 11, count 0 2006.280.07:43:50.28#ibcon#flushed, iclass 11, count 0 2006.280.07:43:50.28#ibcon#about to write, iclass 11, count 0 2006.280.07:43:50.28#ibcon#wrote, iclass 11, count 0 2006.280.07:43:50.28#ibcon#about to read 3, iclass 11, count 0 2006.280.07:43:50.30#ibcon#read 3, iclass 11, count 0 2006.280.07:43:50.30#ibcon#about to read 4, iclass 11, count 0 2006.280.07:43:50.30#ibcon#read 4, iclass 11, count 0 2006.280.07:43:50.30#ibcon#about to read 5, iclass 11, count 0 2006.280.07:43:50.30#ibcon#read 5, iclass 11, count 0 2006.280.07:43:50.30#ibcon#about to read 6, iclass 11, count 0 2006.280.07:43:50.30#ibcon#read 6, iclass 11, count 0 2006.280.07:43:50.30#ibcon#end of sib2, iclass 11, count 0 2006.280.07:43:50.30#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:43:50.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:43:50.30#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:43:50.30#ibcon#*before write, iclass 11, count 0 2006.280.07:43:50.30#ibcon#enter sib2, iclass 11, count 0 2006.280.07:43:50.30#ibcon#flushed, iclass 11, count 0 2006.280.07:43:50.30#ibcon#about to write, iclass 11, count 0 2006.280.07:43:50.30#ibcon#wrote, iclass 11, count 0 2006.280.07:43:50.30#ibcon#about to read 3, iclass 11, count 0 2006.280.07:43:50.35#ibcon#read 3, iclass 11, count 0 2006.280.07:43:50.35#ibcon#about to read 4, iclass 11, count 0 2006.280.07:43:50.35#ibcon#read 4, iclass 11, count 0 2006.280.07:43:50.35#ibcon#about to read 5, iclass 11, count 0 2006.280.07:43:50.35#ibcon#read 5, iclass 11, count 0 2006.280.07:43:50.35#ibcon#about to read 6, iclass 11, count 0 2006.280.07:43:50.35#ibcon#read 6, iclass 11, count 0 2006.280.07:43:50.35#ibcon#end of sib2, iclass 11, count 0 2006.280.07:43:50.35#ibcon#*after write, iclass 11, count 0 2006.280.07:43:50.35#ibcon#*before return 0, iclass 11, count 0 2006.280.07:43:50.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:43:50.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:43:50.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:43:50.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:43:50.35$vc4f8/va=7,6 2006.280.07:43:50.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.07:43:50.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.07:43:50.35#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:50.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:43:50.39#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:43:50.39#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:43:50.39#ibcon#enter wrdev, iclass 13, count 2 2006.280.07:43:50.39#ibcon#first serial, iclass 13, count 2 2006.280.07:43:50.39#ibcon#enter sib2, iclass 13, count 2 2006.280.07:43:50.39#ibcon#flushed, iclass 13, count 2 2006.280.07:43:50.39#ibcon#about to write, iclass 13, count 2 2006.280.07:43:50.39#ibcon#wrote, iclass 13, count 2 2006.280.07:43:50.39#ibcon#about to read 3, iclass 13, count 2 2006.280.07:43:50.41#ibcon#read 3, iclass 13, count 2 2006.280.07:43:50.41#ibcon#about to read 4, iclass 13, count 2 2006.280.07:43:50.41#ibcon#read 4, iclass 13, count 2 2006.280.07:43:50.41#ibcon#about to read 5, iclass 13, count 2 2006.280.07:43:50.41#ibcon#read 5, iclass 13, count 2 2006.280.07:43:50.41#ibcon#about to read 6, iclass 13, count 2 2006.280.07:43:50.41#ibcon#read 6, iclass 13, count 2 2006.280.07:43:50.41#ibcon#end of sib2, iclass 13, count 2 2006.280.07:43:50.41#ibcon#*mode == 0, iclass 13, count 2 2006.280.07:43:50.41#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.07:43:50.41#ibcon#[25=AT07-06\r\n] 2006.280.07:43:50.41#ibcon#*before write, iclass 13, count 2 2006.280.07:43:50.41#ibcon#enter sib2, iclass 13, count 2 2006.280.07:43:50.41#ibcon#flushed, iclass 13, count 2 2006.280.07:43:50.41#ibcon#about to write, iclass 13, count 2 2006.280.07:43:50.41#ibcon#wrote, iclass 13, count 2 2006.280.07:43:50.41#ibcon#about to read 3, iclass 13, count 2 2006.280.07:43:50.44#ibcon#read 3, iclass 13, count 2 2006.280.07:43:50.44#ibcon#about to read 4, iclass 13, count 2 2006.280.07:43:50.44#ibcon#read 4, iclass 13, count 2 2006.280.07:43:50.44#ibcon#about to read 5, iclass 13, count 2 2006.280.07:43:50.44#ibcon#read 5, iclass 13, count 2 2006.280.07:43:50.44#ibcon#about to read 6, iclass 13, count 2 2006.280.07:43:50.44#ibcon#read 6, iclass 13, count 2 2006.280.07:43:50.44#ibcon#end of sib2, iclass 13, count 2 2006.280.07:43:50.44#ibcon#*after write, iclass 13, count 2 2006.280.07:43:50.44#ibcon#*before return 0, iclass 13, count 2 2006.280.07:43:50.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:43:50.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:43:50.44#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.07:43:50.44#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:50.44#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:43:50.56#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:43:50.56#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:43:50.56#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:43:50.56#ibcon#first serial, iclass 13, count 0 2006.280.07:43:50.56#ibcon#enter sib2, iclass 13, count 0 2006.280.07:43:50.56#ibcon#flushed, iclass 13, count 0 2006.280.07:43:50.56#ibcon#about to write, iclass 13, count 0 2006.280.07:43:50.56#ibcon#wrote, iclass 13, count 0 2006.280.07:43:50.56#ibcon#about to read 3, iclass 13, count 0 2006.280.07:43:50.58#ibcon#read 3, iclass 13, count 0 2006.280.07:43:50.58#ibcon#about to read 4, iclass 13, count 0 2006.280.07:43:50.58#ibcon#read 4, iclass 13, count 0 2006.280.07:43:50.58#ibcon#about to read 5, iclass 13, count 0 2006.280.07:43:50.58#ibcon#read 5, iclass 13, count 0 2006.280.07:43:50.58#ibcon#about to read 6, iclass 13, count 0 2006.280.07:43:50.58#ibcon#read 6, iclass 13, count 0 2006.280.07:43:50.58#ibcon#end of sib2, iclass 13, count 0 2006.280.07:43:50.58#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:43:50.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:43:50.58#ibcon#[25=USB\r\n] 2006.280.07:43:50.58#ibcon#*before write, iclass 13, count 0 2006.280.07:43:50.58#ibcon#enter sib2, iclass 13, count 0 2006.280.07:43:50.58#ibcon#flushed, iclass 13, count 0 2006.280.07:43:50.58#ibcon#about to write, iclass 13, count 0 2006.280.07:43:50.58#ibcon#wrote, iclass 13, count 0 2006.280.07:43:50.58#ibcon#about to read 3, iclass 13, count 0 2006.280.07:43:50.61#ibcon#read 3, iclass 13, count 0 2006.280.07:43:50.61#ibcon#about to read 4, iclass 13, count 0 2006.280.07:43:50.61#ibcon#read 4, iclass 13, count 0 2006.280.07:43:50.61#ibcon#about to read 5, iclass 13, count 0 2006.280.07:43:50.61#ibcon#read 5, iclass 13, count 0 2006.280.07:43:50.61#ibcon#about to read 6, iclass 13, count 0 2006.280.07:43:50.61#ibcon#read 6, iclass 13, count 0 2006.280.07:43:50.61#ibcon#end of sib2, iclass 13, count 0 2006.280.07:43:50.61#ibcon#*after write, iclass 13, count 0 2006.280.07:43:50.61#ibcon#*before return 0, iclass 13, count 0 2006.280.07:43:50.61#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:43:50.61#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:43:50.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:43:50.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:43:50.61$vc4f8/valo=8,852.99 2006.280.07:43:50.61#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:43:50.61#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:43:50.61#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:50.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:43:50.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:43:50.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:43:50.61#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:43:50.61#ibcon#first serial, iclass 15, count 0 2006.280.07:43:50.61#ibcon#enter sib2, iclass 15, count 0 2006.280.07:43:50.61#ibcon#flushed, iclass 15, count 0 2006.280.07:43:50.61#ibcon#about to write, iclass 15, count 0 2006.280.07:43:50.61#ibcon#wrote, iclass 15, count 0 2006.280.07:43:50.61#ibcon#about to read 3, iclass 15, count 0 2006.280.07:43:50.63#ibcon#read 3, iclass 15, count 0 2006.280.07:43:50.63#ibcon#about to read 4, iclass 15, count 0 2006.280.07:43:50.63#ibcon#read 4, iclass 15, count 0 2006.280.07:43:50.63#ibcon#about to read 5, iclass 15, count 0 2006.280.07:43:50.63#ibcon#read 5, iclass 15, count 0 2006.280.07:43:50.63#ibcon#about to read 6, iclass 15, count 0 2006.280.07:43:50.63#ibcon#read 6, iclass 15, count 0 2006.280.07:43:50.63#ibcon#end of sib2, iclass 15, count 0 2006.280.07:43:50.63#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:43:50.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:43:50.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:43:50.63#ibcon#*before write, iclass 15, count 0 2006.280.07:43:50.63#ibcon#enter sib2, iclass 15, count 0 2006.280.07:43:50.63#ibcon#flushed, iclass 15, count 0 2006.280.07:43:50.63#ibcon#about to write, iclass 15, count 0 2006.280.07:43:50.63#ibcon#wrote, iclass 15, count 0 2006.280.07:43:50.63#ibcon#about to read 3, iclass 15, count 0 2006.280.07:43:50.67#ibcon#read 3, iclass 15, count 0 2006.280.07:43:50.67#ibcon#about to read 4, iclass 15, count 0 2006.280.07:43:50.67#ibcon#read 4, iclass 15, count 0 2006.280.07:43:50.67#ibcon#about to read 5, iclass 15, count 0 2006.280.07:43:50.67#ibcon#read 5, iclass 15, count 0 2006.280.07:43:50.67#ibcon#about to read 6, iclass 15, count 0 2006.280.07:43:50.67#ibcon#read 6, iclass 15, count 0 2006.280.07:43:50.67#ibcon#end of sib2, iclass 15, count 0 2006.280.07:43:50.67#ibcon#*after write, iclass 15, count 0 2006.280.07:43:50.67#ibcon#*before return 0, iclass 15, count 0 2006.280.07:43:50.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:43:50.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:43:50.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:43:50.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:43:50.67$vc4f8/va=8,6 2006.280.07:43:50.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.07:43:50.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.07:43:50.69#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:50.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:43:50.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:43:50.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:43:50.72#ibcon#enter wrdev, iclass 17, count 2 2006.280.07:43:50.72#ibcon#first serial, iclass 17, count 2 2006.280.07:43:50.72#ibcon#enter sib2, iclass 17, count 2 2006.280.07:43:50.72#ibcon#flushed, iclass 17, count 2 2006.280.07:43:50.72#ibcon#about to write, iclass 17, count 2 2006.280.07:43:50.72#ibcon#wrote, iclass 17, count 2 2006.280.07:43:50.72#ibcon#about to read 3, iclass 17, count 2 2006.280.07:43:50.74#ibcon#read 3, iclass 17, count 2 2006.280.07:43:50.74#ibcon#about to read 4, iclass 17, count 2 2006.280.07:43:50.74#ibcon#read 4, iclass 17, count 2 2006.280.07:43:50.74#ibcon#about to read 5, iclass 17, count 2 2006.280.07:43:50.74#ibcon#read 5, iclass 17, count 2 2006.280.07:43:50.74#ibcon#about to read 6, iclass 17, count 2 2006.280.07:43:50.74#ibcon#read 6, iclass 17, count 2 2006.280.07:43:50.74#ibcon#end of sib2, iclass 17, count 2 2006.280.07:43:50.74#ibcon#*mode == 0, iclass 17, count 2 2006.280.07:43:50.74#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.07:43:50.74#ibcon#[25=AT08-06\r\n] 2006.280.07:43:50.74#ibcon#*before write, iclass 17, count 2 2006.280.07:43:50.74#ibcon#enter sib2, iclass 17, count 2 2006.280.07:43:50.74#ibcon#flushed, iclass 17, count 2 2006.280.07:43:50.74#ibcon#about to write, iclass 17, count 2 2006.280.07:43:50.74#ibcon#wrote, iclass 17, count 2 2006.280.07:43:50.74#ibcon#about to read 3, iclass 17, count 2 2006.280.07:43:50.77#ibcon#read 3, iclass 17, count 2 2006.280.07:43:50.77#ibcon#about to read 4, iclass 17, count 2 2006.280.07:43:50.77#ibcon#read 4, iclass 17, count 2 2006.280.07:43:50.77#ibcon#about to read 5, iclass 17, count 2 2006.280.07:43:50.77#ibcon#read 5, iclass 17, count 2 2006.280.07:43:50.77#ibcon#about to read 6, iclass 17, count 2 2006.280.07:43:50.77#ibcon#read 6, iclass 17, count 2 2006.280.07:43:50.77#ibcon#end of sib2, iclass 17, count 2 2006.280.07:43:50.77#ibcon#*after write, iclass 17, count 2 2006.280.07:43:50.77#ibcon#*before return 0, iclass 17, count 2 2006.280.07:43:50.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:43:50.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:43:50.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.07:43:50.77#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:50.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:43:50.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:43:50.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:43:50.89#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:43:50.89#ibcon#first serial, iclass 17, count 0 2006.280.07:43:50.89#ibcon#enter sib2, iclass 17, count 0 2006.280.07:43:50.89#ibcon#flushed, iclass 17, count 0 2006.280.07:43:50.89#ibcon#about to write, iclass 17, count 0 2006.280.07:43:50.89#ibcon#wrote, iclass 17, count 0 2006.280.07:43:50.89#ibcon#about to read 3, iclass 17, count 0 2006.280.07:43:50.91#ibcon#read 3, iclass 17, count 0 2006.280.07:43:50.91#ibcon#about to read 4, iclass 17, count 0 2006.280.07:43:50.91#ibcon#read 4, iclass 17, count 0 2006.280.07:43:50.91#ibcon#about to read 5, iclass 17, count 0 2006.280.07:43:50.91#ibcon#read 5, iclass 17, count 0 2006.280.07:43:50.91#ibcon#about to read 6, iclass 17, count 0 2006.280.07:43:50.91#ibcon#read 6, iclass 17, count 0 2006.280.07:43:50.91#ibcon#end of sib2, iclass 17, count 0 2006.280.07:43:50.91#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:43:50.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:43:50.91#ibcon#[25=USB\r\n] 2006.280.07:43:50.91#ibcon#*before write, iclass 17, count 0 2006.280.07:43:50.91#ibcon#enter sib2, iclass 17, count 0 2006.280.07:43:50.91#ibcon#flushed, iclass 17, count 0 2006.280.07:43:50.91#ibcon#about to write, iclass 17, count 0 2006.280.07:43:50.91#ibcon#wrote, iclass 17, count 0 2006.280.07:43:50.91#ibcon#about to read 3, iclass 17, count 0 2006.280.07:43:50.94#ibcon#read 3, iclass 17, count 0 2006.280.07:43:50.94#ibcon#about to read 4, iclass 17, count 0 2006.280.07:43:50.94#ibcon#read 4, iclass 17, count 0 2006.280.07:43:50.94#ibcon#about to read 5, iclass 17, count 0 2006.280.07:43:50.94#ibcon#read 5, iclass 17, count 0 2006.280.07:43:50.94#ibcon#about to read 6, iclass 17, count 0 2006.280.07:43:50.94#ibcon#read 6, iclass 17, count 0 2006.280.07:43:50.94#ibcon#end of sib2, iclass 17, count 0 2006.280.07:43:50.94#ibcon#*after write, iclass 17, count 0 2006.280.07:43:50.94#ibcon#*before return 0, iclass 17, count 0 2006.280.07:43:50.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:43:50.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:43:50.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:43:50.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:43:50.94$vc4f8/vblo=1,632.99 2006.280.07:43:50.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:43:50.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:43:50.94#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:50.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:50.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:50.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:50.94#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:43:50.94#ibcon#first serial, iclass 19, count 0 2006.280.07:43:50.94#ibcon#enter sib2, iclass 19, count 0 2006.280.07:43:50.94#ibcon#flushed, iclass 19, count 0 2006.280.07:43:50.94#ibcon#about to write, iclass 19, count 0 2006.280.07:43:50.94#ibcon#wrote, iclass 19, count 0 2006.280.07:43:50.94#ibcon#about to read 3, iclass 19, count 0 2006.280.07:43:50.96#ibcon#read 3, iclass 19, count 0 2006.280.07:43:50.96#ibcon#about to read 4, iclass 19, count 0 2006.280.07:43:50.96#ibcon#read 4, iclass 19, count 0 2006.280.07:43:50.96#ibcon#about to read 5, iclass 19, count 0 2006.280.07:43:50.96#ibcon#read 5, iclass 19, count 0 2006.280.07:43:50.96#ibcon#about to read 6, iclass 19, count 0 2006.280.07:43:50.96#ibcon#read 6, iclass 19, count 0 2006.280.07:43:50.96#ibcon#end of sib2, iclass 19, count 0 2006.280.07:43:50.96#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:43:50.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:43:50.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:43:50.96#ibcon#*before write, iclass 19, count 0 2006.280.07:43:50.96#ibcon#enter sib2, iclass 19, count 0 2006.280.07:43:50.96#ibcon#flushed, iclass 19, count 0 2006.280.07:43:50.96#ibcon#about to write, iclass 19, count 0 2006.280.07:43:50.96#ibcon#wrote, iclass 19, count 0 2006.280.07:43:50.96#ibcon#about to read 3, iclass 19, count 0 2006.280.07:43:51.00#ibcon#read 3, iclass 19, count 0 2006.280.07:43:51.00#ibcon#about to read 4, iclass 19, count 0 2006.280.07:43:51.00#ibcon#read 4, iclass 19, count 0 2006.280.07:43:51.00#ibcon#about to read 5, iclass 19, count 0 2006.280.07:43:51.00#ibcon#read 5, iclass 19, count 0 2006.280.07:43:51.00#ibcon#about to read 6, iclass 19, count 0 2006.280.07:43:51.00#ibcon#read 6, iclass 19, count 0 2006.280.07:43:51.00#ibcon#end of sib2, iclass 19, count 0 2006.280.07:43:51.00#ibcon#*after write, iclass 19, count 0 2006.280.07:43:51.00#ibcon#*before return 0, iclass 19, count 0 2006.280.07:43:51.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:51.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:43:51.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:43:51.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:43:51.00$vc4f8/vb=1,4 2006.280.07:43:51.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:43:51.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:43:51.00#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:51.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:51.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:51.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:51.00#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:43:51.00#ibcon#first serial, iclass 21, count 2 2006.280.07:43:51.00#ibcon#enter sib2, iclass 21, count 2 2006.280.07:43:51.00#ibcon#flushed, iclass 21, count 2 2006.280.07:43:51.00#ibcon#about to write, iclass 21, count 2 2006.280.07:43:51.00#ibcon#wrote, iclass 21, count 2 2006.280.07:43:51.00#ibcon#about to read 3, iclass 21, count 2 2006.280.07:43:51.02#ibcon#read 3, iclass 21, count 2 2006.280.07:43:51.02#ibcon#about to read 4, iclass 21, count 2 2006.280.07:43:51.02#ibcon#read 4, iclass 21, count 2 2006.280.07:43:51.02#ibcon#about to read 5, iclass 21, count 2 2006.280.07:43:51.02#ibcon#read 5, iclass 21, count 2 2006.280.07:43:51.02#ibcon#about to read 6, iclass 21, count 2 2006.280.07:43:51.02#ibcon#read 6, iclass 21, count 2 2006.280.07:43:51.02#ibcon#end of sib2, iclass 21, count 2 2006.280.07:43:51.02#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:43:51.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:43:51.02#ibcon#[27=AT01-04\r\n] 2006.280.07:43:51.02#ibcon#*before write, iclass 21, count 2 2006.280.07:43:51.02#ibcon#enter sib2, iclass 21, count 2 2006.280.07:43:51.02#ibcon#flushed, iclass 21, count 2 2006.280.07:43:51.02#ibcon#about to write, iclass 21, count 2 2006.280.07:43:51.02#ibcon#wrote, iclass 21, count 2 2006.280.07:43:51.02#ibcon#about to read 3, iclass 21, count 2 2006.280.07:43:51.05#ibcon#read 3, iclass 21, count 2 2006.280.07:43:51.05#ibcon#about to read 4, iclass 21, count 2 2006.280.07:43:51.05#ibcon#read 4, iclass 21, count 2 2006.280.07:43:51.05#ibcon#about to read 5, iclass 21, count 2 2006.280.07:43:51.05#ibcon#read 5, iclass 21, count 2 2006.280.07:43:51.05#ibcon#about to read 6, iclass 21, count 2 2006.280.07:43:51.05#ibcon#read 6, iclass 21, count 2 2006.280.07:43:51.05#ibcon#end of sib2, iclass 21, count 2 2006.280.07:43:51.05#ibcon#*after write, iclass 21, count 2 2006.280.07:43:51.05#ibcon#*before return 0, iclass 21, count 2 2006.280.07:43:51.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:51.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:43:51.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:43:51.05#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:51.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:51.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:51.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:51.17#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:43:51.17#ibcon#first serial, iclass 21, count 0 2006.280.07:43:51.17#ibcon#enter sib2, iclass 21, count 0 2006.280.07:43:51.17#ibcon#flushed, iclass 21, count 0 2006.280.07:43:51.17#ibcon#about to write, iclass 21, count 0 2006.280.07:43:51.17#ibcon#wrote, iclass 21, count 0 2006.280.07:43:51.17#ibcon#about to read 3, iclass 21, count 0 2006.280.07:43:51.19#ibcon#read 3, iclass 21, count 0 2006.280.07:43:51.19#ibcon#about to read 4, iclass 21, count 0 2006.280.07:43:51.19#ibcon#read 4, iclass 21, count 0 2006.280.07:43:51.19#ibcon#about to read 5, iclass 21, count 0 2006.280.07:43:51.19#ibcon#read 5, iclass 21, count 0 2006.280.07:43:51.19#ibcon#about to read 6, iclass 21, count 0 2006.280.07:43:51.19#ibcon#read 6, iclass 21, count 0 2006.280.07:43:51.19#ibcon#end of sib2, iclass 21, count 0 2006.280.07:43:51.19#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:43:51.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:43:51.19#ibcon#[27=USB\r\n] 2006.280.07:43:51.19#ibcon#*before write, iclass 21, count 0 2006.280.07:43:51.19#ibcon#enter sib2, iclass 21, count 0 2006.280.07:43:51.19#ibcon#flushed, iclass 21, count 0 2006.280.07:43:51.19#ibcon#about to write, iclass 21, count 0 2006.280.07:43:51.19#ibcon#wrote, iclass 21, count 0 2006.280.07:43:51.19#ibcon#about to read 3, iclass 21, count 0 2006.280.07:43:51.22#ibcon#read 3, iclass 21, count 0 2006.280.07:43:51.22#ibcon#about to read 4, iclass 21, count 0 2006.280.07:43:51.22#ibcon#read 4, iclass 21, count 0 2006.280.07:43:51.22#ibcon#about to read 5, iclass 21, count 0 2006.280.07:43:51.22#ibcon#read 5, iclass 21, count 0 2006.280.07:43:51.22#ibcon#about to read 6, iclass 21, count 0 2006.280.07:43:51.22#ibcon#read 6, iclass 21, count 0 2006.280.07:43:51.22#ibcon#end of sib2, iclass 21, count 0 2006.280.07:43:51.22#ibcon#*after write, iclass 21, count 0 2006.280.07:43:51.22#ibcon#*before return 0, iclass 21, count 0 2006.280.07:43:51.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:51.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:43:51.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:43:51.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:43:51.22$vc4f8/vblo=2,640.99 2006.280.07:43:51.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:43:51.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:43:51.22#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:51.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:51.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:51.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:51.22#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:43:51.22#ibcon#first serial, iclass 23, count 0 2006.280.07:43:51.22#ibcon#enter sib2, iclass 23, count 0 2006.280.07:43:51.22#ibcon#flushed, iclass 23, count 0 2006.280.07:43:51.22#ibcon#about to write, iclass 23, count 0 2006.280.07:43:51.22#ibcon#wrote, iclass 23, count 0 2006.280.07:43:51.22#ibcon#about to read 3, iclass 23, count 0 2006.280.07:43:51.24#ibcon#read 3, iclass 23, count 0 2006.280.07:43:51.24#ibcon#about to read 4, iclass 23, count 0 2006.280.07:43:51.24#ibcon#read 4, iclass 23, count 0 2006.280.07:43:51.24#ibcon#about to read 5, iclass 23, count 0 2006.280.07:43:51.24#ibcon#read 5, iclass 23, count 0 2006.280.07:43:51.24#ibcon#about to read 6, iclass 23, count 0 2006.280.07:43:51.24#ibcon#read 6, iclass 23, count 0 2006.280.07:43:51.24#ibcon#end of sib2, iclass 23, count 0 2006.280.07:43:51.24#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:43:51.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:43:51.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:43:51.24#ibcon#*before write, iclass 23, count 0 2006.280.07:43:51.24#ibcon#enter sib2, iclass 23, count 0 2006.280.07:43:51.24#ibcon#flushed, iclass 23, count 0 2006.280.07:43:51.24#ibcon#about to write, iclass 23, count 0 2006.280.07:43:51.24#ibcon#wrote, iclass 23, count 0 2006.280.07:43:51.24#ibcon#about to read 3, iclass 23, count 0 2006.280.07:43:51.28#ibcon#read 3, iclass 23, count 0 2006.280.07:43:51.28#ibcon#about to read 4, iclass 23, count 0 2006.280.07:43:51.28#ibcon#read 4, iclass 23, count 0 2006.280.07:43:51.28#ibcon#about to read 5, iclass 23, count 0 2006.280.07:43:51.28#ibcon#read 5, iclass 23, count 0 2006.280.07:43:51.28#ibcon#about to read 6, iclass 23, count 0 2006.280.07:43:51.28#ibcon#read 6, iclass 23, count 0 2006.280.07:43:51.28#ibcon#end of sib2, iclass 23, count 0 2006.280.07:43:51.28#ibcon#*after write, iclass 23, count 0 2006.280.07:43:51.28#ibcon#*before return 0, iclass 23, count 0 2006.280.07:43:51.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:51.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:43:51.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:43:51.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:43:51.28$vc4f8/vb=2,5 2006.280.07:43:51.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.07:43:51.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.07:43:51.28#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:51.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:51.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:51.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:51.34#ibcon#enter wrdev, iclass 25, count 2 2006.280.07:43:51.34#ibcon#first serial, iclass 25, count 2 2006.280.07:43:51.34#ibcon#enter sib2, iclass 25, count 2 2006.280.07:43:51.34#ibcon#flushed, iclass 25, count 2 2006.280.07:43:51.34#ibcon#about to write, iclass 25, count 2 2006.280.07:43:51.34#ibcon#wrote, iclass 25, count 2 2006.280.07:43:51.34#ibcon#about to read 3, iclass 25, count 2 2006.280.07:43:51.37#ibcon#read 3, iclass 25, count 2 2006.280.07:43:51.37#ibcon#about to read 4, iclass 25, count 2 2006.280.07:43:51.37#ibcon#read 4, iclass 25, count 2 2006.280.07:43:51.37#ibcon#about to read 5, iclass 25, count 2 2006.280.07:43:51.37#ibcon#read 5, iclass 25, count 2 2006.280.07:43:51.37#ibcon#about to read 6, iclass 25, count 2 2006.280.07:43:51.37#ibcon#read 6, iclass 25, count 2 2006.280.07:43:51.37#ibcon#end of sib2, iclass 25, count 2 2006.280.07:43:51.37#ibcon#*mode == 0, iclass 25, count 2 2006.280.07:43:51.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.07:43:51.37#ibcon#[27=AT02-05\r\n] 2006.280.07:43:51.37#ibcon#*before write, iclass 25, count 2 2006.280.07:43:51.37#ibcon#enter sib2, iclass 25, count 2 2006.280.07:43:51.37#ibcon#flushed, iclass 25, count 2 2006.280.07:43:51.37#ibcon#about to write, iclass 25, count 2 2006.280.07:43:51.37#ibcon#wrote, iclass 25, count 2 2006.280.07:43:51.37#ibcon#about to read 3, iclass 25, count 2 2006.280.07:43:51.39#ibcon#read 3, iclass 25, count 2 2006.280.07:43:51.39#ibcon#about to read 4, iclass 25, count 2 2006.280.07:43:51.39#ibcon#read 4, iclass 25, count 2 2006.280.07:43:51.39#ibcon#about to read 5, iclass 25, count 2 2006.280.07:43:51.39#ibcon#read 5, iclass 25, count 2 2006.280.07:43:51.40#ibcon#about to read 6, iclass 25, count 2 2006.280.07:43:51.40#ibcon#read 6, iclass 25, count 2 2006.280.07:43:51.40#ibcon#end of sib2, iclass 25, count 2 2006.280.07:43:51.40#ibcon#*after write, iclass 25, count 2 2006.280.07:43:51.40#ibcon#*before return 0, iclass 25, count 2 2006.280.07:43:51.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:51.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:43:51.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.07:43:51.40#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:51.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:51.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:51.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:51.51#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:43:51.51#ibcon#first serial, iclass 25, count 0 2006.280.07:43:51.51#ibcon#enter sib2, iclass 25, count 0 2006.280.07:43:51.51#ibcon#flushed, iclass 25, count 0 2006.280.07:43:51.51#ibcon#about to write, iclass 25, count 0 2006.280.07:43:51.51#ibcon#wrote, iclass 25, count 0 2006.280.07:43:51.51#ibcon#about to read 3, iclass 25, count 0 2006.280.07:43:51.53#ibcon#read 3, iclass 25, count 0 2006.280.07:43:51.53#ibcon#about to read 4, iclass 25, count 0 2006.280.07:43:51.53#ibcon#read 4, iclass 25, count 0 2006.280.07:43:51.53#ibcon#about to read 5, iclass 25, count 0 2006.280.07:43:51.53#ibcon#read 5, iclass 25, count 0 2006.280.07:43:51.53#ibcon#about to read 6, iclass 25, count 0 2006.280.07:43:51.53#ibcon#read 6, iclass 25, count 0 2006.280.07:43:51.53#ibcon#end of sib2, iclass 25, count 0 2006.280.07:43:51.53#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:43:51.53#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:43:51.53#ibcon#[27=USB\r\n] 2006.280.07:43:51.53#ibcon#*before write, iclass 25, count 0 2006.280.07:43:51.53#ibcon#enter sib2, iclass 25, count 0 2006.280.07:43:51.53#ibcon#flushed, iclass 25, count 0 2006.280.07:43:51.53#ibcon#about to write, iclass 25, count 0 2006.280.07:43:51.53#ibcon#wrote, iclass 25, count 0 2006.280.07:43:51.53#ibcon#about to read 3, iclass 25, count 0 2006.280.07:43:51.56#ibcon#read 3, iclass 25, count 0 2006.280.07:43:51.56#ibcon#about to read 4, iclass 25, count 0 2006.280.07:43:51.56#ibcon#read 4, iclass 25, count 0 2006.280.07:43:51.56#ibcon#about to read 5, iclass 25, count 0 2006.280.07:43:51.56#ibcon#read 5, iclass 25, count 0 2006.280.07:43:51.56#ibcon#about to read 6, iclass 25, count 0 2006.280.07:43:51.56#ibcon#read 6, iclass 25, count 0 2006.280.07:43:51.56#ibcon#end of sib2, iclass 25, count 0 2006.280.07:43:51.56#ibcon#*after write, iclass 25, count 0 2006.280.07:43:51.56#ibcon#*before return 0, iclass 25, count 0 2006.280.07:43:51.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:51.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:43:51.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:43:51.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:43:51.56$vc4f8/vblo=3,656.99 2006.280.07:43:51.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:43:51.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:43:51.56#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:51.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:51.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:51.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:51.56#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:43:51.56#ibcon#first serial, iclass 27, count 0 2006.280.07:43:51.56#ibcon#enter sib2, iclass 27, count 0 2006.280.07:43:51.56#ibcon#flushed, iclass 27, count 0 2006.280.07:43:51.56#ibcon#about to write, iclass 27, count 0 2006.280.07:43:51.56#ibcon#wrote, iclass 27, count 0 2006.280.07:43:51.56#ibcon#about to read 3, iclass 27, count 0 2006.280.07:43:51.58#ibcon#read 3, iclass 27, count 0 2006.280.07:43:51.58#ibcon#about to read 4, iclass 27, count 0 2006.280.07:43:51.58#ibcon#read 4, iclass 27, count 0 2006.280.07:43:51.58#ibcon#about to read 5, iclass 27, count 0 2006.280.07:43:51.58#ibcon#read 5, iclass 27, count 0 2006.280.07:43:51.58#ibcon#about to read 6, iclass 27, count 0 2006.280.07:43:51.58#ibcon#read 6, iclass 27, count 0 2006.280.07:43:51.58#ibcon#end of sib2, iclass 27, count 0 2006.280.07:43:51.58#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:43:51.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:43:51.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:43:51.58#ibcon#*before write, iclass 27, count 0 2006.280.07:43:51.58#ibcon#enter sib2, iclass 27, count 0 2006.280.07:43:51.58#ibcon#flushed, iclass 27, count 0 2006.280.07:43:51.58#ibcon#about to write, iclass 27, count 0 2006.280.07:43:51.58#ibcon#wrote, iclass 27, count 0 2006.280.07:43:51.58#ibcon#about to read 3, iclass 27, count 0 2006.280.07:43:51.62#ibcon#read 3, iclass 27, count 0 2006.280.07:43:51.62#ibcon#about to read 4, iclass 27, count 0 2006.280.07:43:51.62#ibcon#read 4, iclass 27, count 0 2006.280.07:43:51.62#ibcon#about to read 5, iclass 27, count 0 2006.280.07:43:51.62#ibcon#read 5, iclass 27, count 0 2006.280.07:43:51.62#ibcon#about to read 6, iclass 27, count 0 2006.280.07:43:51.62#ibcon#read 6, iclass 27, count 0 2006.280.07:43:51.62#ibcon#end of sib2, iclass 27, count 0 2006.280.07:43:51.62#ibcon#*after write, iclass 27, count 0 2006.280.07:43:51.62#ibcon#*before return 0, iclass 27, count 0 2006.280.07:43:51.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:51.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:43:51.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:43:51.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:43:51.62$vc4f8/vb=3,4 2006.280.07:43:51.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.07:43:51.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.07:43:51.64#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:51.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:51.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:51.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:51.67#ibcon#enter wrdev, iclass 29, count 2 2006.280.07:43:51.67#ibcon#first serial, iclass 29, count 2 2006.280.07:43:51.67#ibcon#enter sib2, iclass 29, count 2 2006.280.07:43:51.67#ibcon#flushed, iclass 29, count 2 2006.280.07:43:51.67#ibcon#about to write, iclass 29, count 2 2006.280.07:43:51.67#ibcon#wrote, iclass 29, count 2 2006.280.07:43:51.67#ibcon#about to read 3, iclass 29, count 2 2006.280.07:43:51.69#ibcon#read 3, iclass 29, count 2 2006.280.07:43:51.69#ibcon#about to read 4, iclass 29, count 2 2006.280.07:43:51.69#ibcon#read 4, iclass 29, count 2 2006.280.07:43:51.69#ibcon#about to read 5, iclass 29, count 2 2006.280.07:43:51.69#ibcon#read 5, iclass 29, count 2 2006.280.07:43:51.69#ibcon#about to read 6, iclass 29, count 2 2006.280.07:43:51.69#ibcon#read 6, iclass 29, count 2 2006.280.07:43:51.69#ibcon#end of sib2, iclass 29, count 2 2006.280.07:43:51.69#ibcon#*mode == 0, iclass 29, count 2 2006.280.07:43:51.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.07:43:51.69#ibcon#[27=AT03-04\r\n] 2006.280.07:43:51.69#ibcon#*before write, iclass 29, count 2 2006.280.07:43:51.69#ibcon#enter sib2, iclass 29, count 2 2006.280.07:43:51.69#ibcon#flushed, iclass 29, count 2 2006.280.07:43:51.69#ibcon#about to write, iclass 29, count 2 2006.280.07:43:51.69#ibcon#wrote, iclass 29, count 2 2006.280.07:43:51.69#ibcon#about to read 3, iclass 29, count 2 2006.280.07:43:51.72#ibcon#read 3, iclass 29, count 2 2006.280.07:43:51.72#ibcon#about to read 4, iclass 29, count 2 2006.280.07:43:51.72#ibcon#read 4, iclass 29, count 2 2006.280.07:43:51.72#ibcon#about to read 5, iclass 29, count 2 2006.280.07:43:51.72#ibcon#read 5, iclass 29, count 2 2006.280.07:43:51.72#ibcon#about to read 6, iclass 29, count 2 2006.280.07:43:51.72#ibcon#read 6, iclass 29, count 2 2006.280.07:43:51.72#ibcon#end of sib2, iclass 29, count 2 2006.280.07:43:51.72#ibcon#*after write, iclass 29, count 2 2006.280.07:43:51.72#ibcon#*before return 0, iclass 29, count 2 2006.280.07:43:51.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:51.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:43:51.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.07:43:51.72#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:51.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:51.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:51.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:51.84#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:43:51.84#ibcon#first serial, iclass 29, count 0 2006.280.07:43:51.84#ibcon#enter sib2, iclass 29, count 0 2006.280.07:43:51.84#ibcon#flushed, iclass 29, count 0 2006.280.07:43:51.84#ibcon#about to write, iclass 29, count 0 2006.280.07:43:51.84#ibcon#wrote, iclass 29, count 0 2006.280.07:43:51.84#ibcon#about to read 3, iclass 29, count 0 2006.280.07:43:51.86#ibcon#read 3, iclass 29, count 0 2006.280.07:43:51.86#ibcon#about to read 4, iclass 29, count 0 2006.280.07:43:51.86#ibcon#read 4, iclass 29, count 0 2006.280.07:43:51.86#ibcon#about to read 5, iclass 29, count 0 2006.280.07:43:51.86#ibcon#read 5, iclass 29, count 0 2006.280.07:43:51.86#ibcon#about to read 6, iclass 29, count 0 2006.280.07:43:51.86#ibcon#read 6, iclass 29, count 0 2006.280.07:43:51.86#ibcon#end of sib2, iclass 29, count 0 2006.280.07:43:51.86#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:43:51.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:43:51.86#ibcon#[27=USB\r\n] 2006.280.07:43:51.86#ibcon#*before write, iclass 29, count 0 2006.280.07:43:51.86#ibcon#enter sib2, iclass 29, count 0 2006.280.07:43:51.86#ibcon#flushed, iclass 29, count 0 2006.280.07:43:51.86#ibcon#about to write, iclass 29, count 0 2006.280.07:43:51.86#ibcon#wrote, iclass 29, count 0 2006.280.07:43:51.86#ibcon#about to read 3, iclass 29, count 0 2006.280.07:43:51.89#ibcon#read 3, iclass 29, count 0 2006.280.07:43:51.89#ibcon#about to read 4, iclass 29, count 0 2006.280.07:43:51.89#ibcon#read 4, iclass 29, count 0 2006.280.07:43:51.89#ibcon#about to read 5, iclass 29, count 0 2006.280.07:43:51.89#ibcon#read 5, iclass 29, count 0 2006.280.07:43:51.89#ibcon#about to read 6, iclass 29, count 0 2006.280.07:43:51.89#ibcon#read 6, iclass 29, count 0 2006.280.07:43:51.89#ibcon#end of sib2, iclass 29, count 0 2006.280.07:43:51.89#ibcon#*after write, iclass 29, count 0 2006.280.07:43:51.89#ibcon#*before return 0, iclass 29, count 0 2006.280.07:43:51.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:51.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:43:51.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:43:51.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:43:51.89$vc4f8/vblo=4,712.99 2006.280.07:43:51.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.07:43:51.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.07:43:51.89#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:51.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:43:51.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:43:51.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:43:51.89#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:43:51.89#ibcon#first serial, iclass 31, count 0 2006.280.07:43:51.89#ibcon#enter sib2, iclass 31, count 0 2006.280.07:43:51.89#ibcon#flushed, iclass 31, count 0 2006.280.07:43:51.89#ibcon#about to write, iclass 31, count 0 2006.280.07:43:51.89#ibcon#wrote, iclass 31, count 0 2006.280.07:43:51.89#ibcon#about to read 3, iclass 31, count 0 2006.280.07:43:51.91#ibcon#read 3, iclass 31, count 0 2006.280.07:43:51.91#ibcon#about to read 4, iclass 31, count 0 2006.280.07:43:51.91#ibcon#read 4, iclass 31, count 0 2006.280.07:43:51.91#ibcon#about to read 5, iclass 31, count 0 2006.280.07:43:51.91#ibcon#read 5, iclass 31, count 0 2006.280.07:43:51.91#ibcon#about to read 6, iclass 31, count 0 2006.280.07:43:51.91#ibcon#read 6, iclass 31, count 0 2006.280.07:43:51.91#ibcon#end of sib2, iclass 31, count 0 2006.280.07:43:51.91#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:43:51.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:43:51.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:43:51.91#ibcon#*before write, iclass 31, count 0 2006.280.07:43:51.91#ibcon#enter sib2, iclass 31, count 0 2006.280.07:43:51.91#ibcon#flushed, iclass 31, count 0 2006.280.07:43:51.91#ibcon#about to write, iclass 31, count 0 2006.280.07:43:51.91#ibcon#wrote, iclass 31, count 0 2006.280.07:43:51.91#ibcon#about to read 3, iclass 31, count 0 2006.280.07:43:51.95#ibcon#read 3, iclass 31, count 0 2006.280.07:43:51.95#ibcon#about to read 4, iclass 31, count 0 2006.280.07:43:51.95#ibcon#read 4, iclass 31, count 0 2006.280.07:43:51.95#ibcon#about to read 5, iclass 31, count 0 2006.280.07:43:51.95#ibcon#read 5, iclass 31, count 0 2006.280.07:43:51.95#ibcon#about to read 6, iclass 31, count 0 2006.280.07:43:51.95#ibcon#read 6, iclass 31, count 0 2006.280.07:43:51.95#ibcon#end of sib2, iclass 31, count 0 2006.280.07:43:51.95#ibcon#*after write, iclass 31, count 0 2006.280.07:43:51.95#ibcon#*before return 0, iclass 31, count 0 2006.280.07:43:51.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:43:51.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:43:51.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:43:51.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:43:51.95$vc4f8/vb=4,4 2006.280.07:43:51.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.07:43:51.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.07:43:51.95#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:51.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:43:52.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:43:52.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:43:52.01#ibcon#enter wrdev, iclass 33, count 2 2006.280.07:43:52.01#ibcon#first serial, iclass 33, count 2 2006.280.07:43:52.01#ibcon#enter sib2, iclass 33, count 2 2006.280.07:43:52.01#ibcon#flushed, iclass 33, count 2 2006.280.07:43:52.01#ibcon#about to write, iclass 33, count 2 2006.280.07:43:52.01#ibcon#wrote, iclass 33, count 2 2006.280.07:43:52.01#ibcon#about to read 3, iclass 33, count 2 2006.280.07:43:52.03#ibcon#read 3, iclass 33, count 2 2006.280.07:43:52.03#ibcon#about to read 4, iclass 33, count 2 2006.280.07:43:52.03#ibcon#read 4, iclass 33, count 2 2006.280.07:43:52.03#ibcon#about to read 5, iclass 33, count 2 2006.280.07:43:52.03#ibcon#read 5, iclass 33, count 2 2006.280.07:43:52.03#ibcon#about to read 6, iclass 33, count 2 2006.280.07:43:52.03#ibcon#read 6, iclass 33, count 2 2006.280.07:43:52.03#ibcon#end of sib2, iclass 33, count 2 2006.280.07:43:52.03#ibcon#*mode == 0, iclass 33, count 2 2006.280.07:43:52.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.07:43:52.03#ibcon#[27=AT04-04\r\n] 2006.280.07:43:52.03#ibcon#*before write, iclass 33, count 2 2006.280.07:43:52.03#ibcon#enter sib2, iclass 33, count 2 2006.280.07:43:52.03#ibcon#flushed, iclass 33, count 2 2006.280.07:43:52.03#ibcon#about to write, iclass 33, count 2 2006.280.07:43:52.03#ibcon#wrote, iclass 33, count 2 2006.280.07:43:52.03#ibcon#about to read 3, iclass 33, count 2 2006.280.07:43:52.06#ibcon#read 3, iclass 33, count 2 2006.280.07:43:52.06#ibcon#about to read 4, iclass 33, count 2 2006.280.07:43:52.06#ibcon#read 4, iclass 33, count 2 2006.280.07:43:52.06#ibcon#about to read 5, iclass 33, count 2 2006.280.07:43:52.06#ibcon#read 5, iclass 33, count 2 2006.280.07:43:52.06#ibcon#about to read 6, iclass 33, count 2 2006.280.07:43:52.06#ibcon#read 6, iclass 33, count 2 2006.280.07:43:52.06#ibcon#end of sib2, iclass 33, count 2 2006.280.07:43:52.06#ibcon#*after write, iclass 33, count 2 2006.280.07:43:52.06#ibcon#*before return 0, iclass 33, count 2 2006.280.07:43:52.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:43:52.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:43:52.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.07:43:52.06#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:52.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:43:52.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:43:52.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:43:52.18#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:43:52.18#ibcon#first serial, iclass 33, count 0 2006.280.07:43:52.18#ibcon#enter sib2, iclass 33, count 0 2006.280.07:43:52.18#ibcon#flushed, iclass 33, count 0 2006.280.07:43:52.18#ibcon#about to write, iclass 33, count 0 2006.280.07:43:52.18#ibcon#wrote, iclass 33, count 0 2006.280.07:43:52.18#ibcon#about to read 3, iclass 33, count 0 2006.280.07:43:52.20#ibcon#read 3, iclass 33, count 0 2006.280.07:43:52.20#ibcon#about to read 4, iclass 33, count 0 2006.280.07:43:52.20#ibcon#read 4, iclass 33, count 0 2006.280.07:43:52.20#ibcon#about to read 5, iclass 33, count 0 2006.280.07:43:52.20#ibcon#read 5, iclass 33, count 0 2006.280.07:43:52.20#ibcon#about to read 6, iclass 33, count 0 2006.280.07:43:52.20#ibcon#read 6, iclass 33, count 0 2006.280.07:43:52.20#ibcon#end of sib2, iclass 33, count 0 2006.280.07:43:52.20#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:43:52.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:43:52.20#ibcon#[27=USB\r\n] 2006.280.07:43:52.20#ibcon#*before write, iclass 33, count 0 2006.280.07:43:52.20#ibcon#enter sib2, iclass 33, count 0 2006.280.07:43:52.20#ibcon#flushed, iclass 33, count 0 2006.280.07:43:52.20#ibcon#about to write, iclass 33, count 0 2006.280.07:43:52.20#ibcon#wrote, iclass 33, count 0 2006.280.07:43:52.20#ibcon#about to read 3, iclass 33, count 0 2006.280.07:43:52.23#ibcon#read 3, iclass 33, count 0 2006.280.07:43:52.23#ibcon#about to read 4, iclass 33, count 0 2006.280.07:43:52.23#ibcon#read 4, iclass 33, count 0 2006.280.07:43:52.23#ibcon#about to read 5, iclass 33, count 0 2006.280.07:43:52.23#ibcon#read 5, iclass 33, count 0 2006.280.07:43:52.23#ibcon#about to read 6, iclass 33, count 0 2006.280.07:43:52.23#ibcon#read 6, iclass 33, count 0 2006.280.07:43:52.23#ibcon#end of sib2, iclass 33, count 0 2006.280.07:43:52.23#ibcon#*after write, iclass 33, count 0 2006.280.07:43:52.23#ibcon#*before return 0, iclass 33, count 0 2006.280.07:43:52.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:43:52.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:43:52.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:43:52.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:43:52.23$vc4f8/vblo=5,744.99 2006.280.07:43:52.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.07:43:52.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.07:43:52.23#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:52.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:43:52.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:43:52.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:43:52.23#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:43:52.23#ibcon#first serial, iclass 35, count 0 2006.280.07:43:52.23#ibcon#enter sib2, iclass 35, count 0 2006.280.07:43:52.23#ibcon#flushed, iclass 35, count 0 2006.280.07:43:52.23#ibcon#about to write, iclass 35, count 0 2006.280.07:43:52.23#ibcon#wrote, iclass 35, count 0 2006.280.07:43:52.23#ibcon#about to read 3, iclass 35, count 0 2006.280.07:43:52.25#ibcon#read 3, iclass 35, count 0 2006.280.07:43:52.27#ibcon#about to read 4, iclass 35, count 0 2006.280.07:43:52.27#ibcon#read 4, iclass 35, count 0 2006.280.07:43:52.27#ibcon#about to read 5, iclass 35, count 0 2006.280.07:43:52.27#ibcon#read 5, iclass 35, count 0 2006.280.07:43:52.27#ibcon#about to read 6, iclass 35, count 0 2006.280.07:43:52.27#ibcon#read 6, iclass 35, count 0 2006.280.07:43:52.27#ibcon#end of sib2, iclass 35, count 0 2006.280.07:43:52.27#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:43:52.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:43:52.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:43:52.27#ibcon#*before write, iclass 35, count 0 2006.280.07:43:52.27#ibcon#enter sib2, iclass 35, count 0 2006.280.07:43:52.27#ibcon#flushed, iclass 35, count 0 2006.280.07:43:52.27#ibcon#about to write, iclass 35, count 0 2006.280.07:43:52.27#ibcon#wrote, iclass 35, count 0 2006.280.07:43:52.27#ibcon#about to read 3, iclass 35, count 0 2006.280.07:43:52.30#ibcon#read 3, iclass 35, count 0 2006.280.07:43:52.30#ibcon#about to read 4, iclass 35, count 0 2006.280.07:43:52.30#ibcon#read 4, iclass 35, count 0 2006.280.07:43:52.30#ibcon#about to read 5, iclass 35, count 0 2006.280.07:43:52.30#ibcon#read 5, iclass 35, count 0 2006.280.07:43:52.30#ibcon#about to read 6, iclass 35, count 0 2006.280.07:43:52.30#ibcon#read 6, iclass 35, count 0 2006.280.07:43:52.30#ibcon#end of sib2, iclass 35, count 0 2006.280.07:43:52.30#ibcon#*after write, iclass 35, count 0 2006.280.07:43:52.30#ibcon#*before return 0, iclass 35, count 0 2006.280.07:43:52.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:43:52.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:43:52.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:43:52.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:43:52.30$vc4f8/vb=5,4 2006.280.07:43:52.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.07:43:52.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.07:43:52.30#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:52.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:43:52.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:43:52.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:43:52.35#ibcon#enter wrdev, iclass 37, count 2 2006.280.07:43:52.35#ibcon#first serial, iclass 37, count 2 2006.280.07:43:52.35#ibcon#enter sib2, iclass 37, count 2 2006.280.07:43:52.35#ibcon#flushed, iclass 37, count 2 2006.280.07:43:52.35#ibcon#about to write, iclass 37, count 2 2006.280.07:43:52.35#ibcon#wrote, iclass 37, count 2 2006.280.07:43:52.35#ibcon#about to read 3, iclass 37, count 2 2006.280.07:43:52.37#ibcon#read 3, iclass 37, count 2 2006.280.07:43:52.37#ibcon#about to read 4, iclass 37, count 2 2006.280.07:43:52.37#ibcon#read 4, iclass 37, count 2 2006.280.07:43:52.37#ibcon#about to read 5, iclass 37, count 2 2006.280.07:43:52.37#ibcon#read 5, iclass 37, count 2 2006.280.07:43:52.37#ibcon#about to read 6, iclass 37, count 2 2006.280.07:43:52.37#ibcon#read 6, iclass 37, count 2 2006.280.07:43:52.37#ibcon#end of sib2, iclass 37, count 2 2006.280.07:43:52.37#ibcon#*mode == 0, iclass 37, count 2 2006.280.07:43:52.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.07:43:52.37#ibcon#[27=AT05-04\r\n] 2006.280.07:43:52.37#ibcon#*before write, iclass 37, count 2 2006.280.07:43:52.37#ibcon#enter sib2, iclass 37, count 2 2006.280.07:43:52.37#ibcon#flushed, iclass 37, count 2 2006.280.07:43:52.37#ibcon#about to write, iclass 37, count 2 2006.280.07:43:52.37#ibcon#wrote, iclass 37, count 2 2006.280.07:43:52.37#ibcon#about to read 3, iclass 37, count 2 2006.280.07:43:52.40#ibcon#read 3, iclass 37, count 2 2006.280.07:43:52.40#ibcon#about to read 4, iclass 37, count 2 2006.280.07:43:52.40#ibcon#read 4, iclass 37, count 2 2006.280.07:43:52.40#ibcon#about to read 5, iclass 37, count 2 2006.280.07:43:52.40#ibcon#read 5, iclass 37, count 2 2006.280.07:43:52.40#ibcon#about to read 6, iclass 37, count 2 2006.280.07:43:52.40#ibcon#read 6, iclass 37, count 2 2006.280.07:43:52.40#ibcon#end of sib2, iclass 37, count 2 2006.280.07:43:52.40#ibcon#*after write, iclass 37, count 2 2006.280.07:43:52.40#ibcon#*before return 0, iclass 37, count 2 2006.280.07:43:52.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:43:52.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:43:52.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.07:43:52.40#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:52.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:43:52.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:43:52.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:43:52.52#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:43:52.52#ibcon#first serial, iclass 37, count 0 2006.280.07:43:52.52#ibcon#enter sib2, iclass 37, count 0 2006.280.07:43:52.52#ibcon#flushed, iclass 37, count 0 2006.280.07:43:52.52#ibcon#about to write, iclass 37, count 0 2006.280.07:43:52.52#ibcon#wrote, iclass 37, count 0 2006.280.07:43:52.52#ibcon#about to read 3, iclass 37, count 0 2006.280.07:43:52.54#ibcon#read 3, iclass 37, count 0 2006.280.07:43:52.54#ibcon#about to read 4, iclass 37, count 0 2006.280.07:43:52.54#ibcon#read 4, iclass 37, count 0 2006.280.07:43:52.54#ibcon#about to read 5, iclass 37, count 0 2006.280.07:43:52.54#ibcon#read 5, iclass 37, count 0 2006.280.07:43:52.54#ibcon#about to read 6, iclass 37, count 0 2006.280.07:43:52.54#ibcon#read 6, iclass 37, count 0 2006.280.07:43:52.54#ibcon#end of sib2, iclass 37, count 0 2006.280.07:43:52.54#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:43:52.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:43:52.54#ibcon#[27=USB\r\n] 2006.280.07:43:52.54#ibcon#*before write, iclass 37, count 0 2006.280.07:43:52.54#ibcon#enter sib2, iclass 37, count 0 2006.280.07:43:52.54#ibcon#flushed, iclass 37, count 0 2006.280.07:43:52.54#ibcon#about to write, iclass 37, count 0 2006.280.07:43:52.54#ibcon#wrote, iclass 37, count 0 2006.280.07:43:52.54#ibcon#about to read 3, iclass 37, count 0 2006.280.07:43:52.57#ibcon#read 3, iclass 37, count 0 2006.280.07:43:52.57#ibcon#about to read 4, iclass 37, count 0 2006.280.07:43:52.57#ibcon#read 4, iclass 37, count 0 2006.280.07:43:52.57#ibcon#about to read 5, iclass 37, count 0 2006.280.07:43:52.57#ibcon#read 5, iclass 37, count 0 2006.280.07:43:52.57#ibcon#about to read 6, iclass 37, count 0 2006.280.07:43:52.57#ibcon#read 6, iclass 37, count 0 2006.280.07:43:52.57#ibcon#end of sib2, iclass 37, count 0 2006.280.07:43:52.57#ibcon#*after write, iclass 37, count 0 2006.280.07:43:52.57#ibcon#*before return 0, iclass 37, count 0 2006.280.07:43:52.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:43:52.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:43:52.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:43:52.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:43:52.57$vc4f8/vblo=6,752.99 2006.280.07:43:52.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:43:52.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:43:52.57#ibcon#ireg 17 cls_cnt 0 2006.280.07:43:52.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:52.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:52.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:52.57#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:43:52.57#ibcon#first serial, iclass 39, count 0 2006.280.07:43:52.57#ibcon#enter sib2, iclass 39, count 0 2006.280.07:43:52.57#ibcon#flushed, iclass 39, count 0 2006.280.07:43:52.57#ibcon#about to write, iclass 39, count 0 2006.280.07:43:52.57#ibcon#wrote, iclass 39, count 0 2006.280.07:43:52.57#ibcon#about to read 3, iclass 39, count 0 2006.280.07:43:52.59#ibcon#read 3, iclass 39, count 0 2006.280.07:43:52.59#ibcon#about to read 4, iclass 39, count 0 2006.280.07:43:52.59#ibcon#read 4, iclass 39, count 0 2006.280.07:43:52.59#ibcon#about to read 5, iclass 39, count 0 2006.280.07:43:52.59#ibcon#read 5, iclass 39, count 0 2006.280.07:43:52.59#ibcon#about to read 6, iclass 39, count 0 2006.280.07:43:52.59#ibcon#read 6, iclass 39, count 0 2006.280.07:43:52.59#ibcon#end of sib2, iclass 39, count 0 2006.280.07:43:52.59#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:43:52.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:43:52.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:43:52.59#ibcon#*before write, iclass 39, count 0 2006.280.07:43:52.59#ibcon#enter sib2, iclass 39, count 0 2006.280.07:43:52.59#ibcon#flushed, iclass 39, count 0 2006.280.07:43:52.59#ibcon#about to write, iclass 39, count 0 2006.280.07:43:52.59#ibcon#wrote, iclass 39, count 0 2006.280.07:43:52.59#ibcon#about to read 3, iclass 39, count 0 2006.280.07:43:52.63#ibcon#read 3, iclass 39, count 0 2006.280.07:43:52.63#ibcon#about to read 4, iclass 39, count 0 2006.280.07:43:52.63#ibcon#read 4, iclass 39, count 0 2006.280.07:43:52.63#ibcon#about to read 5, iclass 39, count 0 2006.280.07:43:52.63#ibcon#read 5, iclass 39, count 0 2006.280.07:43:52.63#ibcon#about to read 6, iclass 39, count 0 2006.280.07:43:52.63#ibcon#read 6, iclass 39, count 0 2006.280.07:43:52.63#ibcon#end of sib2, iclass 39, count 0 2006.280.07:43:52.63#ibcon#*after write, iclass 39, count 0 2006.280.07:43:52.63#ibcon#*before return 0, iclass 39, count 0 2006.280.07:43:52.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:52.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:43:52.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:43:52.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:43:52.63$vc4f8/vb=6,4 2006.280.07:43:52.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.07:43:52.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.07:43:52.63#ibcon#ireg 11 cls_cnt 2 2006.280.07:43:52.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:52.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:52.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:52.69#ibcon#enter wrdev, iclass 3, count 2 2006.280.07:43:52.69#ibcon#first serial, iclass 3, count 2 2006.280.07:43:52.69#ibcon#enter sib2, iclass 3, count 2 2006.280.07:43:52.69#ibcon#flushed, iclass 3, count 2 2006.280.07:43:52.69#ibcon#about to write, iclass 3, count 2 2006.280.07:43:52.69#ibcon#wrote, iclass 3, count 2 2006.280.07:43:52.69#ibcon#about to read 3, iclass 3, count 2 2006.280.07:43:52.71#ibcon#read 3, iclass 3, count 2 2006.280.07:43:52.71#ibcon#about to read 4, iclass 3, count 2 2006.280.07:43:52.71#ibcon#read 4, iclass 3, count 2 2006.280.07:43:52.71#ibcon#about to read 5, iclass 3, count 2 2006.280.07:43:52.71#ibcon#read 5, iclass 3, count 2 2006.280.07:43:52.71#ibcon#about to read 6, iclass 3, count 2 2006.280.07:43:52.71#ibcon#read 6, iclass 3, count 2 2006.280.07:43:52.71#ibcon#end of sib2, iclass 3, count 2 2006.280.07:43:52.71#ibcon#*mode == 0, iclass 3, count 2 2006.280.07:43:52.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.07:43:52.71#ibcon#[27=AT06-04\r\n] 2006.280.07:43:52.71#ibcon#*before write, iclass 3, count 2 2006.280.07:43:52.71#ibcon#enter sib2, iclass 3, count 2 2006.280.07:43:52.71#ibcon#flushed, iclass 3, count 2 2006.280.07:43:52.71#ibcon#about to write, iclass 3, count 2 2006.280.07:43:52.71#ibcon#wrote, iclass 3, count 2 2006.280.07:43:52.71#ibcon#about to read 3, iclass 3, count 2 2006.280.07:43:52.74#ibcon#read 3, iclass 3, count 2 2006.280.07:43:52.74#ibcon#about to read 4, iclass 3, count 2 2006.280.07:43:52.74#ibcon#read 4, iclass 3, count 2 2006.280.07:43:52.75#ibcon#about to read 5, iclass 3, count 2 2006.280.07:43:52.75#ibcon#read 5, iclass 3, count 2 2006.280.07:43:52.75#ibcon#about to read 6, iclass 3, count 2 2006.280.07:43:52.75#ibcon#read 6, iclass 3, count 2 2006.280.07:43:52.75#ibcon#end of sib2, iclass 3, count 2 2006.280.07:43:52.75#ibcon#*after write, iclass 3, count 2 2006.280.07:43:52.75#ibcon#*before return 0, iclass 3, count 2 2006.280.07:43:52.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:52.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:43:52.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.07:43:52.75#ibcon#ireg 7 cls_cnt 0 2006.280.07:43:52.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:52.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:52.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:52.86#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:43:52.86#ibcon#first serial, iclass 3, count 0 2006.280.07:43:52.86#ibcon#enter sib2, iclass 3, count 0 2006.280.07:43:52.86#ibcon#flushed, iclass 3, count 0 2006.280.07:43:52.86#ibcon#about to write, iclass 3, count 0 2006.280.07:43:52.86#ibcon#wrote, iclass 3, count 0 2006.280.07:43:52.86#ibcon#about to read 3, iclass 3, count 0 2006.280.07:43:52.88#ibcon#read 3, iclass 3, count 0 2006.280.07:43:52.88#ibcon#about to read 4, iclass 3, count 0 2006.280.07:43:52.88#ibcon#read 4, iclass 3, count 0 2006.280.07:43:52.88#ibcon#about to read 5, iclass 3, count 0 2006.280.07:43:52.88#ibcon#read 5, iclass 3, count 0 2006.280.07:43:52.88#ibcon#about to read 6, iclass 3, count 0 2006.280.07:43:52.88#ibcon#read 6, iclass 3, count 0 2006.280.07:43:52.88#ibcon#end of sib2, iclass 3, count 0 2006.280.07:43:52.88#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:43:52.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:43:52.88#ibcon#[27=USB\r\n] 2006.280.07:43:52.88#ibcon#*before write, iclass 3, count 0 2006.280.07:43:52.88#ibcon#enter sib2, iclass 3, count 0 2006.280.07:43:52.88#ibcon#flushed, iclass 3, count 0 2006.280.07:43:52.88#ibcon#about to write, iclass 3, count 0 2006.280.07:43:52.88#ibcon#wrote, iclass 3, count 0 2006.280.07:43:52.88#ibcon#about to read 3, iclass 3, count 0 2006.280.07:43:52.91#ibcon#read 3, iclass 3, count 0 2006.280.07:43:52.91#ibcon#about to read 4, iclass 3, count 0 2006.280.07:43:52.91#ibcon#read 4, iclass 3, count 0 2006.280.07:43:52.91#ibcon#about to read 5, iclass 3, count 0 2006.280.07:43:52.91#ibcon#read 5, iclass 3, count 0 2006.280.07:43:52.91#ibcon#about to read 6, iclass 3, count 0 2006.280.07:43:52.91#ibcon#read 6, iclass 3, count 0 2006.280.07:43:52.91#ibcon#end of sib2, iclass 3, count 0 2006.280.07:43:52.91#ibcon#*after write, iclass 3, count 0 2006.280.07:43:52.91#ibcon#*before return 0, iclass 3, count 0 2006.280.07:43:52.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:52.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:43:52.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:43:52.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:43:52.91$vc4f8/vabw=wide 2006.280.07:43:52.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.07:43:52.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.07:43:52.91#ibcon#ireg 8 cls_cnt 0 2006.280.07:43:52.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:52.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:52.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:52.91#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:43:52.91#ibcon#first serial, iclass 5, count 0 2006.280.07:43:52.91#ibcon#enter sib2, iclass 5, count 0 2006.280.07:43:52.91#ibcon#flushed, iclass 5, count 0 2006.280.07:43:52.91#ibcon#about to write, iclass 5, count 0 2006.280.07:43:52.91#ibcon#wrote, iclass 5, count 0 2006.280.07:43:52.91#ibcon#about to read 3, iclass 5, count 0 2006.280.07:43:52.93#ibcon#read 3, iclass 5, count 0 2006.280.07:43:52.93#ibcon#about to read 4, iclass 5, count 0 2006.280.07:43:52.93#ibcon#read 4, iclass 5, count 0 2006.280.07:43:52.93#ibcon#about to read 5, iclass 5, count 0 2006.280.07:43:52.93#ibcon#read 5, iclass 5, count 0 2006.280.07:43:52.93#ibcon#about to read 6, iclass 5, count 0 2006.280.07:43:52.93#ibcon#read 6, iclass 5, count 0 2006.280.07:43:52.93#ibcon#end of sib2, iclass 5, count 0 2006.280.07:43:52.93#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:43:52.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:43:52.93#ibcon#[25=BW32\r\n] 2006.280.07:43:52.93#ibcon#*before write, iclass 5, count 0 2006.280.07:43:52.93#ibcon#enter sib2, iclass 5, count 0 2006.280.07:43:52.93#ibcon#flushed, iclass 5, count 0 2006.280.07:43:52.93#ibcon#about to write, iclass 5, count 0 2006.280.07:43:52.93#ibcon#wrote, iclass 5, count 0 2006.280.07:43:52.93#ibcon#about to read 3, iclass 5, count 0 2006.280.07:43:52.97#ibcon#read 3, iclass 5, count 0 2006.280.07:43:52.97#ibcon#about to read 4, iclass 5, count 0 2006.280.07:43:52.97#ibcon#read 4, iclass 5, count 0 2006.280.07:43:52.97#ibcon#about to read 5, iclass 5, count 0 2006.280.07:43:52.97#ibcon#read 5, iclass 5, count 0 2006.280.07:43:52.97#ibcon#about to read 6, iclass 5, count 0 2006.280.07:43:52.97#ibcon#read 6, iclass 5, count 0 2006.280.07:43:52.97#ibcon#end of sib2, iclass 5, count 0 2006.280.07:43:52.97#ibcon#*after write, iclass 5, count 0 2006.280.07:43:52.97#ibcon#*before return 0, iclass 5, count 0 2006.280.07:43:52.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:52.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:43:52.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:43:52.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:43:52.97$vc4f8/vbbw=wide 2006.280.07:43:52.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:43:52.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:43:52.97#ibcon#ireg 8 cls_cnt 0 2006.280.07:43:52.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:43:53.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:43:53.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:43:53.02#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:43:53.02#ibcon#first serial, iclass 7, count 0 2006.280.07:43:53.02#ibcon#enter sib2, iclass 7, count 0 2006.280.07:43:53.02#ibcon#flushed, iclass 7, count 0 2006.280.07:43:53.02#ibcon#about to write, iclass 7, count 0 2006.280.07:43:53.02#ibcon#wrote, iclass 7, count 0 2006.280.07:43:53.02#ibcon#about to read 3, iclass 7, count 0 2006.280.07:43:53.04#ibcon#read 3, iclass 7, count 0 2006.280.07:43:53.04#ibcon#about to read 4, iclass 7, count 0 2006.280.07:43:53.04#ibcon#read 4, iclass 7, count 0 2006.280.07:43:53.04#ibcon#about to read 5, iclass 7, count 0 2006.280.07:43:53.04#ibcon#read 5, iclass 7, count 0 2006.280.07:43:53.04#ibcon#about to read 6, iclass 7, count 0 2006.280.07:43:53.04#ibcon#read 6, iclass 7, count 0 2006.280.07:43:53.04#ibcon#end of sib2, iclass 7, count 0 2006.280.07:43:53.04#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:43:53.04#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:43:53.04#ibcon#[27=BW32\r\n] 2006.280.07:43:53.04#ibcon#*before write, iclass 7, count 0 2006.280.07:43:53.04#ibcon#enter sib2, iclass 7, count 0 2006.280.07:43:53.04#ibcon#flushed, iclass 7, count 0 2006.280.07:43:53.04#ibcon#about to write, iclass 7, count 0 2006.280.07:43:53.04#ibcon#wrote, iclass 7, count 0 2006.280.07:43:53.04#ibcon#about to read 3, iclass 7, count 0 2006.280.07:43:53.08#ibcon#read 3, iclass 7, count 0 2006.280.07:43:53.08#ibcon#about to read 4, iclass 7, count 0 2006.280.07:43:53.08#ibcon#read 4, iclass 7, count 0 2006.280.07:43:53.08#ibcon#about to read 5, iclass 7, count 0 2006.280.07:43:53.08#ibcon#read 5, iclass 7, count 0 2006.280.07:43:53.08#ibcon#about to read 6, iclass 7, count 0 2006.280.07:43:53.08#ibcon#read 6, iclass 7, count 0 2006.280.07:43:53.08#ibcon#end of sib2, iclass 7, count 0 2006.280.07:43:53.08#ibcon#*after write, iclass 7, count 0 2006.280.07:43:53.08#ibcon#*before return 0, iclass 7, count 0 2006.280.07:43:53.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:43:53.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:43:53.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:43:53.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:43:53.08$4f8m12a/ifd4f 2006.280.07:43:53.08$ifd4f/lo= 2006.280.07:43:53.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:43:53.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:43:53.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:43:53.08$ifd4f/patch= 2006.280.07:43:53.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:43:53.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:43:53.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:43:53.08$4f8m12a/"form=m,16.000,1:2 2006.280.07:43:53.08$4f8m12a/"tpicd 2006.280.07:43:53.08$4f8m12a/echo=off 2006.280.07:43:53.08$4f8m12a/xlog=off 2006.280.07:43:53.08:!2006.280.07:44:20 2006.280.07:43:57.13#trakl#Source acquired 2006.280.07:43:59.13#flagr#flagr/antenna,acquired 2006.280.07:44:20.01:preob 2006.280.07:44:21.13/onsource/TRACKING 2006.280.07:44:21.13:!2006.280.07:44:30 2006.280.07:44:30.00:data_valid=on 2006.280.07:44:30.00:midob 2006.280.07:44:30.13/onsource/TRACKING 2006.280.07:44:30.13/wx/21.46,986.8,60 2006.280.07:44:30.19/cable/+6.4816E-03 2006.280.07:44:31.28/va/01,07,usb,yes,40,42 2006.280.07:44:31.28/va/02,06,usb,yes,37,39 2006.280.07:44:31.28/va/03,06,usb,yes,35,35 2006.280.07:44:31.28/va/04,06,usb,yes,38,41 2006.280.07:44:31.28/va/05,07,usb,yes,36,38 2006.280.07:44:31.28/va/06,06,usb,yes,35,34 2006.280.07:44:31.28/va/07,06,usb,yes,35,35 2006.280.07:44:31.28/va/08,06,usb,yes,37,36 2006.280.07:44:31.51/valo/01,532.99,yes,locked 2006.280.07:44:31.51/valo/02,572.99,yes,locked 2006.280.07:44:31.51/valo/03,672.99,yes,locked 2006.280.07:44:31.51/valo/04,832.99,yes,locked 2006.280.07:44:31.51/valo/05,652.99,yes,locked 2006.280.07:44:31.51/valo/06,772.99,yes,locked 2006.280.07:44:31.51/valo/07,832.99,yes,locked 2006.280.07:44:31.51/valo/08,852.99,yes,locked 2006.280.07:44:32.60/vb/01,04,usb,yes,33,32 2006.280.07:44:32.60/vb/02,05,usb,yes,31,32 2006.280.07:44:32.60/vb/03,04,usb,yes,31,36 2006.280.07:44:32.60/vb/04,04,usb,yes,32,33 2006.280.07:44:32.60/vb/05,04,usb,yes,30,35 2006.280.07:44:32.60/vb/06,04,usb,yes,31,35 2006.280.07:44:32.60/vb/07,04,usb,yes,34,34 2006.280.07:44:32.60/vb/08,04,usb,yes,31,35 2006.280.07:44:32.83/vblo/01,632.99,yes,locked 2006.280.07:44:32.83/vblo/02,640.99,yes,locked 2006.280.07:44:32.83/vblo/03,656.99,yes,locked 2006.280.07:44:32.83/vblo/04,712.99,yes,locked 2006.280.07:44:32.83/vblo/05,744.99,yes,locked 2006.280.07:44:32.83/vblo/06,752.99,yes,locked 2006.280.07:44:32.83/vblo/07,734.99,yes,locked 2006.280.07:44:32.83/vblo/08,744.99,yes,locked 2006.280.07:44:32.98/vabw/8 2006.280.07:44:33.13/vbbw/8 2006.280.07:44:33.22/xfe/off,on,12.2 2006.280.07:44:33.59/ifatt/23,28,28,28 2006.280.07:44:34.07/fmout-gps/S +3.06E-07 2006.280.07:44:34.10:!2006.280.07:45:30 2006.280.07:45:30.01:data_valid=off 2006.280.07:45:30.02:postob 2006.280.07:45:30.10/cable/+6.4830E-03 2006.280.07:45:30.11/wx/21.42,986.9,60 2006.280.07:45:31.07/fmout-gps/S +3.08E-07 2006.280.07:45:31.08:scan_name=280-0746,k06280,60 2006.280.07:45:31.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.280.07:45:31.14#flagr#flagr/antenna,new-source 2006.280.07:45:32.14:checkk5 2006.280.07:45:32.62/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:45:33.00/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:45:33.37/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:45:33.87/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:45:34.27/chk_obsdata//k5ts1/T2800744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:45:34.71/chk_obsdata//k5ts2/T2800744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:45:35.08/chk_obsdata//k5ts3/T2800744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:45:35.52/chk_obsdata//k5ts4/T2800744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:45:36.23/k5log//k5ts1_log_newline 2006.280.07:45:36.99/k5log//k5ts2_log_newline 2006.280.07:45:37.76/k5log//k5ts3_log_newline 2006.280.07:45:38.56/k5log//k5ts4_log_newline 2006.280.07:45:38.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:45:38.59:4f8m12a=1 2006.280.07:45:38.59$4f8m12a/echo=on 2006.280.07:45:38.59$4f8m12a/pcalon 2006.280.07:45:38.59$pcalon/"no phase cal control is implemented here 2006.280.07:45:38.59$4f8m12a/"tpicd=stop 2006.280.07:45:38.59$4f8m12a/vc4f8 2006.280.07:45:38.59$vc4f8/valo=1,532.99 2006.280.07:45:38.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:45:38.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:45:38.59#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:38.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:38.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:38.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:38.59#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:45:38.59#ibcon#first serial, iclass 16, count 0 2006.280.07:45:38.59#ibcon#enter sib2, iclass 16, count 0 2006.280.07:45:38.59#ibcon#flushed, iclass 16, count 0 2006.280.07:45:38.59#ibcon#about to write, iclass 16, count 0 2006.280.07:45:38.59#ibcon#wrote, iclass 16, count 0 2006.280.07:45:38.59#ibcon#about to read 3, iclass 16, count 0 2006.280.07:45:38.60#ibcon#read 3, iclass 16, count 0 2006.280.07:45:38.60#ibcon#about to read 4, iclass 16, count 0 2006.280.07:45:38.60#ibcon#read 4, iclass 16, count 0 2006.280.07:45:38.60#ibcon#about to read 5, iclass 16, count 0 2006.280.07:45:38.60#ibcon#read 5, iclass 16, count 0 2006.280.07:45:38.60#ibcon#about to read 6, iclass 16, count 0 2006.280.07:45:38.60#ibcon#read 6, iclass 16, count 0 2006.280.07:45:38.60#ibcon#end of sib2, iclass 16, count 0 2006.280.07:45:38.60#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:45:38.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:45:38.60#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:45:38.60#ibcon#*before write, iclass 16, count 0 2006.280.07:45:38.60#ibcon#enter sib2, iclass 16, count 0 2006.280.07:45:38.60#ibcon#flushed, iclass 16, count 0 2006.280.07:45:38.60#ibcon#about to write, iclass 16, count 0 2006.280.07:45:38.60#ibcon#wrote, iclass 16, count 0 2006.280.07:45:38.60#ibcon#about to read 3, iclass 16, count 0 2006.280.07:45:38.65#ibcon#read 3, iclass 16, count 0 2006.280.07:45:38.65#ibcon#about to read 4, iclass 16, count 0 2006.280.07:45:38.65#ibcon#read 4, iclass 16, count 0 2006.280.07:45:38.65#ibcon#about to read 5, iclass 16, count 0 2006.280.07:45:38.65#ibcon#read 5, iclass 16, count 0 2006.280.07:45:38.65#ibcon#about to read 6, iclass 16, count 0 2006.280.07:45:38.65#ibcon#read 6, iclass 16, count 0 2006.280.07:45:38.65#ibcon#end of sib2, iclass 16, count 0 2006.280.07:45:38.65#ibcon#*after write, iclass 16, count 0 2006.280.07:45:38.65#ibcon#*before return 0, iclass 16, count 0 2006.280.07:45:38.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:38.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:38.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:45:38.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:45:38.65$vc4f8/va=1,7 2006.280.07:45:38.65#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.07:45:38.65#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.07:45:38.65#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:38.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:38.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:38.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:38.65#ibcon#enter wrdev, iclass 18, count 2 2006.280.07:45:38.65#ibcon#first serial, iclass 18, count 2 2006.280.07:45:38.65#ibcon#enter sib2, iclass 18, count 2 2006.280.07:45:38.65#ibcon#flushed, iclass 18, count 2 2006.280.07:45:38.65#ibcon#about to write, iclass 18, count 2 2006.280.07:45:38.65#ibcon#wrote, iclass 18, count 2 2006.280.07:45:38.65#ibcon#about to read 3, iclass 18, count 2 2006.280.07:45:38.67#ibcon#read 3, iclass 18, count 2 2006.280.07:45:38.67#ibcon#about to read 4, iclass 18, count 2 2006.280.07:45:38.68#ibcon#read 4, iclass 18, count 2 2006.280.07:45:38.68#ibcon#about to read 5, iclass 18, count 2 2006.280.07:45:38.68#ibcon#read 5, iclass 18, count 2 2006.280.07:45:38.68#ibcon#about to read 6, iclass 18, count 2 2006.280.07:45:38.68#ibcon#read 6, iclass 18, count 2 2006.280.07:45:38.68#ibcon#end of sib2, iclass 18, count 2 2006.280.07:45:38.68#ibcon#*mode == 0, iclass 18, count 2 2006.280.07:45:38.68#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.07:45:38.68#ibcon#[25=AT01-07\r\n] 2006.280.07:45:38.68#ibcon#*before write, iclass 18, count 2 2006.280.07:45:38.68#ibcon#enter sib2, iclass 18, count 2 2006.280.07:45:38.68#ibcon#flushed, iclass 18, count 2 2006.280.07:45:38.68#ibcon#about to write, iclass 18, count 2 2006.280.07:45:38.68#ibcon#wrote, iclass 18, count 2 2006.280.07:45:38.68#ibcon#about to read 3, iclass 18, count 2 2006.280.07:45:38.71#ibcon#read 3, iclass 18, count 2 2006.280.07:45:38.71#ibcon#about to read 4, iclass 18, count 2 2006.280.07:45:38.71#ibcon#read 4, iclass 18, count 2 2006.280.07:45:38.71#ibcon#about to read 5, iclass 18, count 2 2006.280.07:45:38.71#ibcon#read 5, iclass 18, count 2 2006.280.07:45:38.71#ibcon#about to read 6, iclass 18, count 2 2006.280.07:45:38.71#ibcon#read 6, iclass 18, count 2 2006.280.07:45:38.71#ibcon#end of sib2, iclass 18, count 2 2006.280.07:45:38.71#ibcon#*after write, iclass 18, count 2 2006.280.07:45:38.71#ibcon#*before return 0, iclass 18, count 2 2006.280.07:45:38.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:38.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:38.71#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.07:45:38.71#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:38.71#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:38.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:38.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:38.83#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:45:38.83#ibcon#first serial, iclass 18, count 0 2006.280.07:45:38.83#ibcon#enter sib2, iclass 18, count 0 2006.280.07:45:38.83#ibcon#flushed, iclass 18, count 0 2006.280.07:45:38.83#ibcon#about to write, iclass 18, count 0 2006.280.07:45:38.83#ibcon#wrote, iclass 18, count 0 2006.280.07:45:38.83#ibcon#about to read 3, iclass 18, count 0 2006.280.07:45:38.85#ibcon#read 3, iclass 18, count 0 2006.280.07:45:38.85#ibcon#about to read 4, iclass 18, count 0 2006.280.07:45:38.85#ibcon#read 4, iclass 18, count 0 2006.280.07:45:38.85#ibcon#about to read 5, iclass 18, count 0 2006.280.07:45:38.85#ibcon#read 5, iclass 18, count 0 2006.280.07:45:38.85#ibcon#about to read 6, iclass 18, count 0 2006.280.07:45:38.85#ibcon#read 6, iclass 18, count 0 2006.280.07:45:38.85#ibcon#end of sib2, iclass 18, count 0 2006.280.07:45:38.85#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:45:38.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:45:38.85#ibcon#[25=USB\r\n] 2006.280.07:45:38.85#ibcon#*before write, iclass 18, count 0 2006.280.07:45:38.85#ibcon#enter sib2, iclass 18, count 0 2006.280.07:45:38.85#ibcon#flushed, iclass 18, count 0 2006.280.07:45:38.85#ibcon#about to write, iclass 18, count 0 2006.280.07:45:38.85#ibcon#wrote, iclass 18, count 0 2006.280.07:45:38.85#ibcon#about to read 3, iclass 18, count 0 2006.280.07:45:38.88#ibcon#read 3, iclass 18, count 0 2006.280.07:45:38.88#ibcon#about to read 4, iclass 18, count 0 2006.280.07:45:38.88#ibcon#read 4, iclass 18, count 0 2006.280.07:45:38.88#ibcon#about to read 5, iclass 18, count 0 2006.280.07:45:38.88#ibcon#read 5, iclass 18, count 0 2006.280.07:45:38.88#ibcon#about to read 6, iclass 18, count 0 2006.280.07:45:38.88#ibcon#read 6, iclass 18, count 0 2006.280.07:45:38.88#ibcon#end of sib2, iclass 18, count 0 2006.280.07:45:38.88#ibcon#*after write, iclass 18, count 0 2006.280.07:45:38.88#ibcon#*before return 0, iclass 18, count 0 2006.280.07:45:38.88#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:38.88#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:38.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:45:38.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:45:38.88$vc4f8/valo=2,572.99 2006.280.07:45:38.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.07:45:38.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.07:45:38.88#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:38.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:38.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:38.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:38.88#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:45:38.88#ibcon#first serial, iclass 20, count 0 2006.280.07:45:38.88#ibcon#enter sib2, iclass 20, count 0 2006.280.07:45:38.88#ibcon#flushed, iclass 20, count 0 2006.280.07:45:38.88#ibcon#about to write, iclass 20, count 0 2006.280.07:45:38.88#ibcon#wrote, iclass 20, count 0 2006.280.07:45:38.88#ibcon#about to read 3, iclass 20, count 0 2006.280.07:45:38.90#ibcon#read 3, iclass 20, count 0 2006.280.07:45:38.91#ibcon#about to read 4, iclass 20, count 0 2006.280.07:45:38.91#ibcon#read 4, iclass 20, count 0 2006.280.07:45:38.91#ibcon#about to read 5, iclass 20, count 0 2006.280.07:45:38.91#ibcon#read 5, iclass 20, count 0 2006.280.07:45:38.91#ibcon#about to read 6, iclass 20, count 0 2006.280.07:45:38.91#ibcon#read 6, iclass 20, count 0 2006.280.07:45:38.91#ibcon#end of sib2, iclass 20, count 0 2006.280.07:45:38.91#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:45:38.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:45:38.91#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:45:38.91#ibcon#*before write, iclass 20, count 0 2006.280.07:45:38.91#ibcon#enter sib2, iclass 20, count 0 2006.280.07:45:38.91#ibcon#flushed, iclass 20, count 0 2006.280.07:45:38.91#ibcon#about to write, iclass 20, count 0 2006.280.07:45:38.91#ibcon#wrote, iclass 20, count 0 2006.280.07:45:38.91#ibcon#about to read 3, iclass 20, count 0 2006.280.07:45:38.94#ibcon#read 3, iclass 20, count 0 2006.280.07:45:38.94#ibcon#about to read 4, iclass 20, count 0 2006.280.07:45:38.94#ibcon#read 4, iclass 20, count 0 2006.280.07:45:38.94#ibcon#about to read 5, iclass 20, count 0 2006.280.07:45:38.94#ibcon#read 5, iclass 20, count 0 2006.280.07:45:38.94#ibcon#about to read 6, iclass 20, count 0 2006.280.07:45:38.94#ibcon#read 6, iclass 20, count 0 2006.280.07:45:38.94#ibcon#end of sib2, iclass 20, count 0 2006.280.07:45:38.94#ibcon#*after write, iclass 20, count 0 2006.280.07:45:38.94#ibcon#*before return 0, iclass 20, count 0 2006.280.07:45:38.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:38.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:38.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:45:38.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:45:38.94$vc4f8/va=2,6 2006.280.07:45:38.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.07:45:38.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.07:45:38.94#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:38.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:39.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:39.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:39.00#ibcon#enter wrdev, iclass 22, count 2 2006.280.07:45:39.00#ibcon#first serial, iclass 22, count 2 2006.280.07:45:39.00#ibcon#enter sib2, iclass 22, count 2 2006.280.07:45:39.00#ibcon#flushed, iclass 22, count 2 2006.280.07:45:39.00#ibcon#about to write, iclass 22, count 2 2006.280.07:45:39.00#ibcon#wrote, iclass 22, count 2 2006.280.07:45:39.00#ibcon#about to read 3, iclass 22, count 2 2006.280.07:45:39.02#ibcon#read 3, iclass 22, count 2 2006.280.07:45:39.02#ibcon#about to read 4, iclass 22, count 2 2006.280.07:45:39.02#ibcon#read 4, iclass 22, count 2 2006.280.07:45:39.02#ibcon#about to read 5, iclass 22, count 2 2006.280.07:45:39.02#ibcon#read 5, iclass 22, count 2 2006.280.07:45:39.02#ibcon#about to read 6, iclass 22, count 2 2006.280.07:45:39.02#ibcon#read 6, iclass 22, count 2 2006.280.07:45:39.02#ibcon#end of sib2, iclass 22, count 2 2006.280.07:45:39.02#ibcon#*mode == 0, iclass 22, count 2 2006.280.07:45:39.02#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.07:45:39.02#ibcon#[25=AT02-06\r\n] 2006.280.07:45:39.02#ibcon#*before write, iclass 22, count 2 2006.280.07:45:39.02#ibcon#enter sib2, iclass 22, count 2 2006.280.07:45:39.02#ibcon#flushed, iclass 22, count 2 2006.280.07:45:39.02#ibcon#about to write, iclass 22, count 2 2006.280.07:45:39.02#ibcon#wrote, iclass 22, count 2 2006.280.07:45:39.02#ibcon#about to read 3, iclass 22, count 2 2006.280.07:45:39.05#ibcon#read 3, iclass 22, count 2 2006.280.07:45:39.05#ibcon#about to read 4, iclass 22, count 2 2006.280.07:45:39.05#ibcon#read 4, iclass 22, count 2 2006.280.07:45:39.05#ibcon#about to read 5, iclass 22, count 2 2006.280.07:45:39.05#ibcon#read 5, iclass 22, count 2 2006.280.07:45:39.05#ibcon#about to read 6, iclass 22, count 2 2006.280.07:45:39.05#ibcon#read 6, iclass 22, count 2 2006.280.07:45:39.05#ibcon#end of sib2, iclass 22, count 2 2006.280.07:45:39.05#ibcon#*after write, iclass 22, count 2 2006.280.07:45:39.05#ibcon#*before return 0, iclass 22, count 2 2006.280.07:45:39.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:39.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:39.05#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.07:45:39.05#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:39.05#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:39.18#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:39.18#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:39.18#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:45:39.18#ibcon#first serial, iclass 22, count 0 2006.280.07:45:39.18#ibcon#enter sib2, iclass 22, count 0 2006.280.07:45:39.18#ibcon#flushed, iclass 22, count 0 2006.280.07:45:39.18#ibcon#about to write, iclass 22, count 0 2006.280.07:45:39.18#ibcon#wrote, iclass 22, count 0 2006.280.07:45:39.18#ibcon#about to read 3, iclass 22, count 0 2006.280.07:45:39.19#ibcon#read 3, iclass 22, count 0 2006.280.07:45:39.19#ibcon#about to read 4, iclass 22, count 0 2006.280.07:45:39.19#ibcon#read 4, iclass 22, count 0 2006.280.07:45:39.19#ibcon#about to read 5, iclass 22, count 0 2006.280.07:45:39.19#ibcon#read 5, iclass 22, count 0 2006.280.07:45:39.19#ibcon#about to read 6, iclass 22, count 0 2006.280.07:45:39.19#ibcon#read 6, iclass 22, count 0 2006.280.07:45:39.19#ibcon#end of sib2, iclass 22, count 0 2006.280.07:45:39.19#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:45:39.19#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:45:39.19#ibcon#[25=USB\r\n] 2006.280.07:45:39.19#ibcon#*before write, iclass 22, count 0 2006.280.07:45:39.19#ibcon#enter sib2, iclass 22, count 0 2006.280.07:45:39.19#ibcon#flushed, iclass 22, count 0 2006.280.07:45:39.19#ibcon#about to write, iclass 22, count 0 2006.280.07:45:39.19#ibcon#wrote, iclass 22, count 0 2006.280.07:45:39.19#ibcon#about to read 3, iclass 22, count 0 2006.280.07:45:39.22#ibcon#read 3, iclass 22, count 0 2006.280.07:45:39.22#ibcon#about to read 4, iclass 22, count 0 2006.280.07:45:39.22#ibcon#read 4, iclass 22, count 0 2006.280.07:45:39.22#ibcon#about to read 5, iclass 22, count 0 2006.280.07:45:39.22#ibcon#read 5, iclass 22, count 0 2006.280.07:45:39.22#ibcon#about to read 6, iclass 22, count 0 2006.280.07:45:39.22#ibcon#read 6, iclass 22, count 0 2006.280.07:45:39.22#ibcon#end of sib2, iclass 22, count 0 2006.280.07:45:39.22#ibcon#*after write, iclass 22, count 0 2006.280.07:45:39.22#ibcon#*before return 0, iclass 22, count 0 2006.280.07:45:39.22#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:39.22#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:39.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:45:39.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:45:39.22$vc4f8/valo=3,672.99 2006.280.07:45:39.22#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.07:45:39.22#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.07:45:39.22#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:39.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:39.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:39.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:39.22#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:45:39.22#ibcon#first serial, iclass 24, count 0 2006.280.07:45:39.22#ibcon#enter sib2, iclass 24, count 0 2006.280.07:45:39.22#ibcon#flushed, iclass 24, count 0 2006.280.07:45:39.22#ibcon#about to write, iclass 24, count 0 2006.280.07:45:39.22#ibcon#wrote, iclass 24, count 0 2006.280.07:45:39.22#ibcon#about to read 3, iclass 24, count 0 2006.280.07:45:39.24#ibcon#read 3, iclass 24, count 0 2006.280.07:45:39.24#ibcon#about to read 4, iclass 24, count 0 2006.280.07:45:39.24#ibcon#read 4, iclass 24, count 0 2006.280.07:45:39.24#ibcon#about to read 5, iclass 24, count 0 2006.280.07:45:39.24#ibcon#read 5, iclass 24, count 0 2006.280.07:45:39.24#ibcon#about to read 6, iclass 24, count 0 2006.280.07:45:39.24#ibcon#read 6, iclass 24, count 0 2006.280.07:45:39.24#ibcon#end of sib2, iclass 24, count 0 2006.280.07:45:39.24#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:45:39.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:45:39.24#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:45:39.24#ibcon#*before write, iclass 24, count 0 2006.280.07:45:39.24#ibcon#enter sib2, iclass 24, count 0 2006.280.07:45:39.24#ibcon#flushed, iclass 24, count 0 2006.280.07:45:39.24#ibcon#about to write, iclass 24, count 0 2006.280.07:45:39.24#ibcon#wrote, iclass 24, count 0 2006.280.07:45:39.24#ibcon#about to read 3, iclass 24, count 0 2006.280.07:45:39.28#ibcon#read 3, iclass 24, count 0 2006.280.07:45:39.28#ibcon#about to read 4, iclass 24, count 0 2006.280.07:45:39.28#ibcon#read 4, iclass 24, count 0 2006.280.07:45:39.28#ibcon#about to read 5, iclass 24, count 0 2006.280.07:45:39.28#ibcon#read 5, iclass 24, count 0 2006.280.07:45:39.28#ibcon#about to read 6, iclass 24, count 0 2006.280.07:45:39.28#ibcon#read 6, iclass 24, count 0 2006.280.07:45:39.28#ibcon#end of sib2, iclass 24, count 0 2006.280.07:45:39.28#ibcon#*after write, iclass 24, count 0 2006.280.07:45:39.28#ibcon#*before return 0, iclass 24, count 0 2006.280.07:45:39.28#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:39.28#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:39.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:45:39.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:45:39.28$vc4f8/va=3,6 2006.280.07:45:39.28#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.07:45:39.28#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.07:45:39.28#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:39.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:39.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:39.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:39.34#ibcon#enter wrdev, iclass 26, count 2 2006.280.07:45:39.34#ibcon#first serial, iclass 26, count 2 2006.280.07:45:39.34#ibcon#enter sib2, iclass 26, count 2 2006.280.07:45:39.34#ibcon#flushed, iclass 26, count 2 2006.280.07:45:39.34#ibcon#about to write, iclass 26, count 2 2006.280.07:45:39.34#ibcon#wrote, iclass 26, count 2 2006.280.07:45:39.34#ibcon#about to read 3, iclass 26, count 2 2006.280.07:45:39.37#ibcon#read 3, iclass 26, count 2 2006.280.07:45:39.37#ibcon#about to read 4, iclass 26, count 2 2006.280.07:45:39.37#ibcon#read 4, iclass 26, count 2 2006.280.07:45:39.37#ibcon#about to read 5, iclass 26, count 2 2006.280.07:45:39.37#ibcon#read 5, iclass 26, count 2 2006.280.07:45:39.37#ibcon#about to read 6, iclass 26, count 2 2006.280.07:45:39.37#ibcon#read 6, iclass 26, count 2 2006.280.07:45:39.37#ibcon#end of sib2, iclass 26, count 2 2006.280.07:45:39.37#ibcon#*mode == 0, iclass 26, count 2 2006.280.07:45:39.37#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.07:45:39.37#ibcon#[25=AT03-06\r\n] 2006.280.07:45:39.37#ibcon#*before write, iclass 26, count 2 2006.280.07:45:39.37#ibcon#enter sib2, iclass 26, count 2 2006.280.07:45:39.37#ibcon#flushed, iclass 26, count 2 2006.280.07:45:39.37#ibcon#about to write, iclass 26, count 2 2006.280.07:45:39.37#ibcon#wrote, iclass 26, count 2 2006.280.07:45:39.37#ibcon#about to read 3, iclass 26, count 2 2006.280.07:45:39.40#ibcon#read 3, iclass 26, count 2 2006.280.07:45:39.40#ibcon#about to read 4, iclass 26, count 2 2006.280.07:45:39.40#ibcon#read 4, iclass 26, count 2 2006.280.07:45:39.40#ibcon#about to read 5, iclass 26, count 2 2006.280.07:45:39.40#ibcon#read 5, iclass 26, count 2 2006.280.07:45:39.40#ibcon#about to read 6, iclass 26, count 2 2006.280.07:45:39.40#ibcon#read 6, iclass 26, count 2 2006.280.07:45:39.40#ibcon#end of sib2, iclass 26, count 2 2006.280.07:45:39.40#ibcon#*after write, iclass 26, count 2 2006.280.07:45:39.40#ibcon#*before return 0, iclass 26, count 2 2006.280.07:45:39.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:39.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:39.40#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.07:45:39.40#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:39.40#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:39.52#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:39.52#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:39.52#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:45:39.52#ibcon#first serial, iclass 26, count 0 2006.280.07:45:39.52#ibcon#enter sib2, iclass 26, count 0 2006.280.07:45:39.52#ibcon#flushed, iclass 26, count 0 2006.280.07:45:39.52#ibcon#about to write, iclass 26, count 0 2006.280.07:45:39.52#ibcon#wrote, iclass 26, count 0 2006.280.07:45:39.52#ibcon#about to read 3, iclass 26, count 0 2006.280.07:45:39.54#ibcon#read 3, iclass 26, count 0 2006.280.07:45:39.54#ibcon#about to read 4, iclass 26, count 0 2006.280.07:45:39.54#ibcon#read 4, iclass 26, count 0 2006.280.07:45:39.54#ibcon#about to read 5, iclass 26, count 0 2006.280.07:45:39.54#ibcon#read 5, iclass 26, count 0 2006.280.07:45:39.54#ibcon#about to read 6, iclass 26, count 0 2006.280.07:45:39.54#ibcon#read 6, iclass 26, count 0 2006.280.07:45:39.54#ibcon#end of sib2, iclass 26, count 0 2006.280.07:45:39.54#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:45:39.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:45:39.54#ibcon#[25=USB\r\n] 2006.280.07:45:39.54#ibcon#*before write, iclass 26, count 0 2006.280.07:45:39.54#ibcon#enter sib2, iclass 26, count 0 2006.280.07:45:39.54#ibcon#flushed, iclass 26, count 0 2006.280.07:45:39.54#ibcon#about to write, iclass 26, count 0 2006.280.07:45:39.54#ibcon#wrote, iclass 26, count 0 2006.280.07:45:39.54#ibcon#about to read 3, iclass 26, count 0 2006.280.07:45:39.58#ibcon#read 3, iclass 26, count 0 2006.280.07:45:39.58#ibcon#about to read 4, iclass 26, count 0 2006.280.07:45:39.58#ibcon#read 4, iclass 26, count 0 2006.280.07:45:39.58#ibcon#about to read 5, iclass 26, count 0 2006.280.07:45:39.58#ibcon#read 5, iclass 26, count 0 2006.280.07:45:39.58#ibcon#about to read 6, iclass 26, count 0 2006.280.07:45:39.58#ibcon#read 6, iclass 26, count 0 2006.280.07:45:39.58#ibcon#end of sib2, iclass 26, count 0 2006.280.07:45:39.58#ibcon#*after write, iclass 26, count 0 2006.280.07:45:39.58#ibcon#*before return 0, iclass 26, count 0 2006.280.07:45:39.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:39.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:39.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:45:39.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:45:39.58$vc4f8/valo=4,832.99 2006.280.07:45:39.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.07:45:39.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.07:45:39.58#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:39.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:39.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:39.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:39.58#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:45:39.58#ibcon#first serial, iclass 28, count 0 2006.280.07:45:39.58#ibcon#enter sib2, iclass 28, count 0 2006.280.07:45:39.58#ibcon#flushed, iclass 28, count 0 2006.280.07:45:39.58#ibcon#about to write, iclass 28, count 0 2006.280.07:45:39.58#ibcon#wrote, iclass 28, count 0 2006.280.07:45:39.58#ibcon#about to read 3, iclass 28, count 0 2006.280.07:45:39.59#ibcon#read 3, iclass 28, count 0 2006.280.07:45:39.59#ibcon#about to read 4, iclass 28, count 0 2006.280.07:45:39.59#ibcon#read 4, iclass 28, count 0 2006.280.07:45:39.59#ibcon#about to read 5, iclass 28, count 0 2006.280.07:45:39.59#ibcon#read 5, iclass 28, count 0 2006.280.07:45:39.59#ibcon#about to read 6, iclass 28, count 0 2006.280.07:45:39.59#ibcon#read 6, iclass 28, count 0 2006.280.07:45:39.59#ibcon#end of sib2, iclass 28, count 0 2006.280.07:45:39.59#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:45:39.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:45:39.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:45:39.59#ibcon#*before write, iclass 28, count 0 2006.280.07:45:39.59#ibcon#enter sib2, iclass 28, count 0 2006.280.07:45:39.59#ibcon#flushed, iclass 28, count 0 2006.280.07:45:39.62#ibcon#about to write, iclass 28, count 0 2006.280.07:45:39.62#ibcon#wrote, iclass 28, count 0 2006.280.07:45:39.62#ibcon#about to read 3, iclass 28, count 0 2006.280.07:45:39.67#ibcon#read 3, iclass 28, count 0 2006.280.07:45:39.67#ibcon#about to read 4, iclass 28, count 0 2006.280.07:45:39.67#ibcon#read 4, iclass 28, count 0 2006.280.07:45:39.67#ibcon#about to read 5, iclass 28, count 0 2006.280.07:45:39.67#ibcon#read 5, iclass 28, count 0 2006.280.07:45:39.67#ibcon#about to read 6, iclass 28, count 0 2006.280.07:45:39.67#ibcon#read 6, iclass 28, count 0 2006.280.07:45:39.67#ibcon#end of sib2, iclass 28, count 0 2006.280.07:45:39.67#ibcon#*after write, iclass 28, count 0 2006.280.07:45:39.67#ibcon#*before return 0, iclass 28, count 0 2006.280.07:45:39.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:39.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:39.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:45:39.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:45:39.67$vc4f8/va=4,6 2006.280.07:45:39.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.07:45:39.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.07:45:39.67#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:39.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:39.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:39.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:39.69#ibcon#enter wrdev, iclass 30, count 2 2006.280.07:45:39.69#ibcon#first serial, iclass 30, count 2 2006.280.07:45:39.69#ibcon#enter sib2, iclass 30, count 2 2006.280.07:45:39.69#ibcon#flushed, iclass 30, count 2 2006.280.07:45:39.69#ibcon#about to write, iclass 30, count 2 2006.280.07:45:39.69#ibcon#wrote, iclass 30, count 2 2006.280.07:45:39.69#ibcon#about to read 3, iclass 30, count 2 2006.280.07:45:39.72#ibcon#read 3, iclass 30, count 2 2006.280.07:45:39.72#ibcon#about to read 4, iclass 30, count 2 2006.280.07:45:39.72#ibcon#read 4, iclass 30, count 2 2006.280.07:45:39.72#ibcon#about to read 5, iclass 30, count 2 2006.280.07:45:39.72#ibcon#read 5, iclass 30, count 2 2006.280.07:45:39.72#ibcon#about to read 6, iclass 30, count 2 2006.280.07:45:39.72#ibcon#read 6, iclass 30, count 2 2006.280.07:45:39.72#ibcon#end of sib2, iclass 30, count 2 2006.280.07:45:39.72#ibcon#*mode == 0, iclass 30, count 2 2006.280.07:45:39.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.07:45:39.72#ibcon#[25=AT04-06\r\n] 2006.280.07:45:39.72#ibcon#*before write, iclass 30, count 2 2006.280.07:45:39.72#ibcon#enter sib2, iclass 30, count 2 2006.280.07:45:39.72#ibcon#flushed, iclass 30, count 2 2006.280.07:45:39.72#ibcon#about to write, iclass 30, count 2 2006.280.07:45:39.72#ibcon#wrote, iclass 30, count 2 2006.280.07:45:39.72#ibcon#about to read 3, iclass 30, count 2 2006.280.07:45:39.74#ibcon#read 3, iclass 30, count 2 2006.280.07:45:39.74#ibcon#about to read 4, iclass 30, count 2 2006.280.07:45:39.74#ibcon#read 4, iclass 30, count 2 2006.280.07:45:39.74#ibcon#about to read 5, iclass 30, count 2 2006.280.07:45:39.74#ibcon#read 5, iclass 30, count 2 2006.280.07:45:39.74#ibcon#about to read 6, iclass 30, count 2 2006.280.07:45:39.74#ibcon#read 6, iclass 30, count 2 2006.280.07:45:39.74#ibcon#end of sib2, iclass 30, count 2 2006.280.07:45:39.74#ibcon#*after write, iclass 30, count 2 2006.280.07:45:39.74#ibcon#*before return 0, iclass 30, count 2 2006.280.07:45:39.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:39.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:39.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.07:45:39.74#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:39.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:39.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:39.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:39.86#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:45:39.86#ibcon#first serial, iclass 30, count 0 2006.280.07:45:39.86#ibcon#enter sib2, iclass 30, count 0 2006.280.07:45:39.86#ibcon#flushed, iclass 30, count 0 2006.280.07:45:39.86#ibcon#about to write, iclass 30, count 0 2006.280.07:45:39.86#ibcon#wrote, iclass 30, count 0 2006.280.07:45:39.86#ibcon#about to read 3, iclass 30, count 0 2006.280.07:45:39.88#ibcon#read 3, iclass 30, count 0 2006.280.07:45:39.88#ibcon#about to read 4, iclass 30, count 0 2006.280.07:45:39.88#ibcon#read 4, iclass 30, count 0 2006.280.07:45:39.88#ibcon#about to read 5, iclass 30, count 0 2006.280.07:45:39.88#ibcon#read 5, iclass 30, count 0 2006.280.07:45:39.88#ibcon#about to read 6, iclass 30, count 0 2006.280.07:45:39.88#ibcon#read 6, iclass 30, count 0 2006.280.07:45:39.88#ibcon#end of sib2, iclass 30, count 0 2006.280.07:45:39.88#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:45:39.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:45:39.88#ibcon#[25=USB\r\n] 2006.280.07:45:39.88#ibcon#*before write, iclass 30, count 0 2006.280.07:45:39.88#ibcon#enter sib2, iclass 30, count 0 2006.280.07:45:39.88#ibcon#flushed, iclass 30, count 0 2006.280.07:45:39.88#ibcon#about to write, iclass 30, count 0 2006.280.07:45:39.88#ibcon#wrote, iclass 30, count 0 2006.280.07:45:39.88#ibcon#about to read 3, iclass 30, count 0 2006.280.07:45:39.91#ibcon#read 3, iclass 30, count 0 2006.280.07:45:39.91#ibcon#about to read 4, iclass 30, count 0 2006.280.07:45:39.91#ibcon#read 4, iclass 30, count 0 2006.280.07:45:39.91#ibcon#about to read 5, iclass 30, count 0 2006.280.07:45:39.91#ibcon#read 5, iclass 30, count 0 2006.280.07:45:39.91#ibcon#about to read 6, iclass 30, count 0 2006.280.07:45:39.91#ibcon#read 6, iclass 30, count 0 2006.280.07:45:39.91#ibcon#end of sib2, iclass 30, count 0 2006.280.07:45:39.91#ibcon#*after write, iclass 30, count 0 2006.280.07:45:39.91#ibcon#*before return 0, iclass 30, count 0 2006.280.07:45:39.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:39.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:39.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:45:39.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:45:39.91$vc4f8/valo=5,652.99 2006.280.07:45:39.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:45:39.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:45:39.91#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:39.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:39.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:39.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:39.91#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:45:39.91#ibcon#first serial, iclass 32, count 0 2006.280.07:45:39.91#ibcon#enter sib2, iclass 32, count 0 2006.280.07:45:39.91#ibcon#flushed, iclass 32, count 0 2006.280.07:45:39.91#ibcon#about to write, iclass 32, count 0 2006.280.07:45:39.91#ibcon#wrote, iclass 32, count 0 2006.280.07:45:39.91#ibcon#about to read 3, iclass 32, count 0 2006.280.07:45:39.93#ibcon#read 3, iclass 32, count 0 2006.280.07:45:39.94#ibcon#about to read 4, iclass 32, count 0 2006.280.07:45:39.94#ibcon#read 4, iclass 32, count 0 2006.280.07:45:39.94#ibcon#about to read 5, iclass 32, count 0 2006.280.07:45:39.94#ibcon#read 5, iclass 32, count 0 2006.280.07:45:39.94#ibcon#about to read 6, iclass 32, count 0 2006.280.07:45:39.94#ibcon#read 6, iclass 32, count 0 2006.280.07:45:39.94#ibcon#end of sib2, iclass 32, count 0 2006.280.07:45:39.94#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:45:39.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:45:39.94#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:45:39.94#ibcon#*before write, iclass 32, count 0 2006.280.07:45:39.94#ibcon#enter sib2, iclass 32, count 0 2006.280.07:45:39.94#ibcon#flushed, iclass 32, count 0 2006.280.07:45:39.94#ibcon#about to write, iclass 32, count 0 2006.280.07:45:39.94#ibcon#wrote, iclass 32, count 0 2006.280.07:45:39.94#ibcon#about to read 3, iclass 32, count 0 2006.280.07:45:39.97#ibcon#read 3, iclass 32, count 0 2006.280.07:45:39.97#ibcon#about to read 4, iclass 32, count 0 2006.280.07:45:39.97#ibcon#read 4, iclass 32, count 0 2006.280.07:45:39.97#ibcon#about to read 5, iclass 32, count 0 2006.280.07:45:39.97#ibcon#read 5, iclass 32, count 0 2006.280.07:45:39.97#ibcon#about to read 6, iclass 32, count 0 2006.280.07:45:39.97#ibcon#read 6, iclass 32, count 0 2006.280.07:45:39.97#ibcon#end of sib2, iclass 32, count 0 2006.280.07:45:39.97#ibcon#*after write, iclass 32, count 0 2006.280.07:45:39.97#ibcon#*before return 0, iclass 32, count 0 2006.280.07:45:39.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:39.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:39.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:45:39.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:45:39.97$vc4f8/va=5,7 2006.280.07:45:39.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.07:45:39.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.07:45:39.97#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:39.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:40.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:40.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:40.04#ibcon#enter wrdev, iclass 34, count 2 2006.280.07:45:40.04#ibcon#first serial, iclass 34, count 2 2006.280.07:45:40.04#ibcon#enter sib2, iclass 34, count 2 2006.280.07:45:40.04#ibcon#flushed, iclass 34, count 2 2006.280.07:45:40.04#ibcon#about to write, iclass 34, count 2 2006.280.07:45:40.04#ibcon#wrote, iclass 34, count 2 2006.280.07:45:40.04#ibcon#about to read 3, iclass 34, count 2 2006.280.07:45:40.05#ibcon#read 3, iclass 34, count 2 2006.280.07:45:40.05#ibcon#about to read 4, iclass 34, count 2 2006.280.07:45:40.05#ibcon#read 4, iclass 34, count 2 2006.280.07:45:40.05#ibcon#about to read 5, iclass 34, count 2 2006.280.07:45:40.05#ibcon#read 5, iclass 34, count 2 2006.280.07:45:40.05#ibcon#about to read 6, iclass 34, count 2 2006.280.07:45:40.05#ibcon#read 6, iclass 34, count 2 2006.280.07:45:40.05#ibcon#end of sib2, iclass 34, count 2 2006.280.07:45:40.05#ibcon#*mode == 0, iclass 34, count 2 2006.280.07:45:40.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.07:45:40.05#ibcon#[25=AT05-07\r\n] 2006.280.07:45:40.05#ibcon#*before write, iclass 34, count 2 2006.280.07:45:40.05#ibcon#enter sib2, iclass 34, count 2 2006.280.07:45:40.05#ibcon#flushed, iclass 34, count 2 2006.280.07:45:40.05#ibcon#about to write, iclass 34, count 2 2006.280.07:45:40.05#ibcon#wrote, iclass 34, count 2 2006.280.07:45:40.05#ibcon#about to read 3, iclass 34, count 2 2006.280.07:45:40.08#ibcon#read 3, iclass 34, count 2 2006.280.07:45:40.08#ibcon#about to read 4, iclass 34, count 2 2006.280.07:45:40.08#ibcon#read 4, iclass 34, count 2 2006.280.07:45:40.08#ibcon#about to read 5, iclass 34, count 2 2006.280.07:45:40.08#ibcon#read 5, iclass 34, count 2 2006.280.07:45:40.08#ibcon#about to read 6, iclass 34, count 2 2006.280.07:45:40.08#ibcon#read 6, iclass 34, count 2 2006.280.07:45:40.08#ibcon#end of sib2, iclass 34, count 2 2006.280.07:45:40.08#ibcon#*after write, iclass 34, count 2 2006.280.07:45:40.08#ibcon#*before return 0, iclass 34, count 2 2006.280.07:45:40.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:40.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:40.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.07:45:40.08#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:40.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:40.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:40.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:40.20#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:45:40.20#ibcon#first serial, iclass 34, count 0 2006.280.07:45:40.20#ibcon#enter sib2, iclass 34, count 0 2006.280.07:45:40.20#ibcon#flushed, iclass 34, count 0 2006.280.07:45:40.20#ibcon#about to write, iclass 34, count 0 2006.280.07:45:40.20#ibcon#wrote, iclass 34, count 0 2006.280.07:45:40.20#ibcon#about to read 3, iclass 34, count 0 2006.280.07:45:40.22#ibcon#read 3, iclass 34, count 0 2006.280.07:45:40.22#ibcon#about to read 4, iclass 34, count 0 2006.280.07:45:40.22#ibcon#read 4, iclass 34, count 0 2006.280.07:45:40.22#ibcon#about to read 5, iclass 34, count 0 2006.280.07:45:40.22#ibcon#read 5, iclass 34, count 0 2006.280.07:45:40.22#ibcon#about to read 6, iclass 34, count 0 2006.280.07:45:40.22#ibcon#read 6, iclass 34, count 0 2006.280.07:45:40.22#ibcon#end of sib2, iclass 34, count 0 2006.280.07:45:40.22#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:45:40.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:45:40.22#ibcon#[25=USB\r\n] 2006.280.07:45:40.22#ibcon#*before write, iclass 34, count 0 2006.280.07:45:40.22#ibcon#enter sib2, iclass 34, count 0 2006.280.07:45:40.22#ibcon#flushed, iclass 34, count 0 2006.280.07:45:40.22#ibcon#about to write, iclass 34, count 0 2006.280.07:45:40.22#ibcon#wrote, iclass 34, count 0 2006.280.07:45:40.22#ibcon#about to read 3, iclass 34, count 0 2006.280.07:45:40.25#ibcon#read 3, iclass 34, count 0 2006.280.07:45:40.25#ibcon#about to read 4, iclass 34, count 0 2006.280.07:45:40.25#ibcon#read 4, iclass 34, count 0 2006.280.07:45:40.25#ibcon#about to read 5, iclass 34, count 0 2006.280.07:45:40.25#ibcon#read 5, iclass 34, count 0 2006.280.07:45:40.25#ibcon#about to read 6, iclass 34, count 0 2006.280.07:45:40.25#ibcon#read 6, iclass 34, count 0 2006.280.07:45:40.25#ibcon#end of sib2, iclass 34, count 0 2006.280.07:45:40.25#ibcon#*after write, iclass 34, count 0 2006.280.07:45:40.25#ibcon#*before return 0, iclass 34, count 0 2006.280.07:45:40.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:40.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:40.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:45:40.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:45:40.25$vc4f8/valo=6,772.99 2006.280.07:45:40.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.07:45:40.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.07:45:40.25#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:40.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:40.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:40.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:40.25#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:45:40.25#ibcon#first serial, iclass 36, count 0 2006.280.07:45:40.25#ibcon#enter sib2, iclass 36, count 0 2006.280.07:45:40.25#ibcon#flushed, iclass 36, count 0 2006.280.07:45:40.25#ibcon#about to write, iclass 36, count 0 2006.280.07:45:40.25#ibcon#wrote, iclass 36, count 0 2006.280.07:45:40.25#ibcon#about to read 3, iclass 36, count 0 2006.280.07:45:40.27#ibcon#read 3, iclass 36, count 0 2006.280.07:45:40.28#ibcon#about to read 4, iclass 36, count 0 2006.280.07:45:40.28#ibcon#read 4, iclass 36, count 0 2006.280.07:45:40.28#ibcon#about to read 5, iclass 36, count 0 2006.280.07:45:40.28#ibcon#read 5, iclass 36, count 0 2006.280.07:45:40.28#ibcon#about to read 6, iclass 36, count 0 2006.280.07:45:40.28#ibcon#read 6, iclass 36, count 0 2006.280.07:45:40.28#ibcon#end of sib2, iclass 36, count 0 2006.280.07:45:40.28#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:45:40.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:45:40.28#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:45:40.28#ibcon#*before write, iclass 36, count 0 2006.280.07:45:40.28#ibcon#enter sib2, iclass 36, count 0 2006.280.07:45:40.28#ibcon#flushed, iclass 36, count 0 2006.280.07:45:40.28#ibcon#about to write, iclass 36, count 0 2006.280.07:45:40.28#ibcon#wrote, iclass 36, count 0 2006.280.07:45:40.28#ibcon#about to read 3, iclass 36, count 0 2006.280.07:45:40.31#ibcon#read 3, iclass 36, count 0 2006.280.07:45:40.31#ibcon#about to read 4, iclass 36, count 0 2006.280.07:45:40.31#ibcon#read 4, iclass 36, count 0 2006.280.07:45:40.31#ibcon#about to read 5, iclass 36, count 0 2006.280.07:45:40.31#ibcon#read 5, iclass 36, count 0 2006.280.07:45:40.31#ibcon#about to read 6, iclass 36, count 0 2006.280.07:45:40.31#ibcon#read 6, iclass 36, count 0 2006.280.07:45:40.31#ibcon#end of sib2, iclass 36, count 0 2006.280.07:45:40.31#ibcon#*after write, iclass 36, count 0 2006.280.07:45:40.31#ibcon#*before return 0, iclass 36, count 0 2006.280.07:45:40.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:40.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:40.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:45:40.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:45:40.31$vc4f8/va=6,6 2006.280.07:45:40.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.07:45:40.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.07:45:40.31#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:40.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:40.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:40.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:40.37#ibcon#enter wrdev, iclass 38, count 2 2006.280.07:45:40.37#ibcon#first serial, iclass 38, count 2 2006.280.07:45:40.37#ibcon#enter sib2, iclass 38, count 2 2006.280.07:45:40.37#ibcon#flushed, iclass 38, count 2 2006.280.07:45:40.37#ibcon#about to write, iclass 38, count 2 2006.280.07:45:40.37#ibcon#wrote, iclass 38, count 2 2006.280.07:45:40.37#ibcon#about to read 3, iclass 38, count 2 2006.280.07:45:40.39#ibcon#read 3, iclass 38, count 2 2006.280.07:45:40.39#ibcon#about to read 4, iclass 38, count 2 2006.280.07:45:40.39#ibcon#read 4, iclass 38, count 2 2006.280.07:45:40.39#ibcon#about to read 5, iclass 38, count 2 2006.280.07:45:40.39#ibcon#read 5, iclass 38, count 2 2006.280.07:45:40.39#ibcon#about to read 6, iclass 38, count 2 2006.280.07:45:40.39#ibcon#read 6, iclass 38, count 2 2006.280.07:45:40.39#ibcon#end of sib2, iclass 38, count 2 2006.280.07:45:40.39#ibcon#*mode == 0, iclass 38, count 2 2006.280.07:45:40.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.07:45:40.39#ibcon#[25=AT06-06\r\n] 2006.280.07:45:40.39#ibcon#*before write, iclass 38, count 2 2006.280.07:45:40.39#ibcon#enter sib2, iclass 38, count 2 2006.280.07:45:40.39#ibcon#flushed, iclass 38, count 2 2006.280.07:45:40.39#ibcon#about to write, iclass 38, count 2 2006.280.07:45:40.39#ibcon#wrote, iclass 38, count 2 2006.280.07:45:40.39#ibcon#about to read 3, iclass 38, count 2 2006.280.07:45:40.42#ibcon#read 3, iclass 38, count 2 2006.280.07:45:40.42#ibcon#about to read 4, iclass 38, count 2 2006.280.07:45:40.42#ibcon#read 4, iclass 38, count 2 2006.280.07:45:40.42#ibcon#about to read 5, iclass 38, count 2 2006.280.07:45:40.42#ibcon#read 5, iclass 38, count 2 2006.280.07:45:40.42#ibcon#about to read 6, iclass 38, count 2 2006.280.07:45:40.42#ibcon#read 6, iclass 38, count 2 2006.280.07:45:40.42#ibcon#end of sib2, iclass 38, count 2 2006.280.07:45:40.42#ibcon#*after write, iclass 38, count 2 2006.280.07:45:40.42#ibcon#*before return 0, iclass 38, count 2 2006.280.07:45:40.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:40.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:40.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.07:45:40.42#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:40.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:40.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:40.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:40.55#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:45:40.55#ibcon#first serial, iclass 38, count 0 2006.280.07:45:40.55#ibcon#enter sib2, iclass 38, count 0 2006.280.07:45:40.55#ibcon#flushed, iclass 38, count 0 2006.280.07:45:40.55#ibcon#about to write, iclass 38, count 0 2006.280.07:45:40.55#ibcon#wrote, iclass 38, count 0 2006.280.07:45:40.55#ibcon#about to read 3, iclass 38, count 0 2006.280.07:45:40.57#ibcon#read 3, iclass 38, count 0 2006.280.07:45:40.57#ibcon#about to read 4, iclass 38, count 0 2006.280.07:45:40.57#ibcon#read 4, iclass 38, count 0 2006.280.07:45:40.57#ibcon#about to read 5, iclass 38, count 0 2006.280.07:45:40.57#ibcon#read 5, iclass 38, count 0 2006.280.07:45:40.57#ibcon#about to read 6, iclass 38, count 0 2006.280.07:45:40.57#ibcon#read 6, iclass 38, count 0 2006.280.07:45:40.57#ibcon#end of sib2, iclass 38, count 0 2006.280.07:45:40.57#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:45:40.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:45:40.57#ibcon#[25=USB\r\n] 2006.280.07:45:40.57#ibcon#*before write, iclass 38, count 0 2006.280.07:45:40.57#ibcon#enter sib2, iclass 38, count 0 2006.280.07:45:40.57#ibcon#flushed, iclass 38, count 0 2006.280.07:45:40.57#ibcon#about to write, iclass 38, count 0 2006.280.07:45:40.57#ibcon#wrote, iclass 38, count 0 2006.280.07:45:40.57#ibcon#about to read 3, iclass 38, count 0 2006.280.07:45:40.59#ibcon#read 3, iclass 38, count 0 2006.280.07:45:40.59#ibcon#about to read 4, iclass 38, count 0 2006.280.07:45:40.59#ibcon#read 4, iclass 38, count 0 2006.280.07:45:40.59#ibcon#about to read 5, iclass 38, count 0 2006.280.07:45:40.59#ibcon#read 5, iclass 38, count 0 2006.280.07:45:40.59#ibcon#about to read 6, iclass 38, count 0 2006.280.07:45:40.59#ibcon#read 6, iclass 38, count 0 2006.280.07:45:40.59#ibcon#end of sib2, iclass 38, count 0 2006.280.07:45:40.59#ibcon#*after write, iclass 38, count 0 2006.280.07:45:40.59#ibcon#*before return 0, iclass 38, count 0 2006.280.07:45:40.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:40.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:40.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:45:40.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:45:40.59$vc4f8/valo=7,832.99 2006.280.07:45:40.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:45:40.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:45:40.59#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:40.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:40.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:40.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:40.59#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:45:40.59#ibcon#first serial, iclass 40, count 0 2006.280.07:45:40.59#ibcon#enter sib2, iclass 40, count 0 2006.280.07:45:40.59#ibcon#flushed, iclass 40, count 0 2006.280.07:45:40.59#ibcon#about to write, iclass 40, count 0 2006.280.07:45:40.59#ibcon#wrote, iclass 40, count 0 2006.280.07:45:40.59#ibcon#about to read 3, iclass 40, count 0 2006.280.07:45:40.61#ibcon#read 3, iclass 40, count 0 2006.280.07:45:40.61#ibcon#about to read 4, iclass 40, count 0 2006.280.07:45:40.61#ibcon#read 4, iclass 40, count 0 2006.280.07:45:40.61#ibcon#about to read 5, iclass 40, count 0 2006.280.07:45:40.61#ibcon#read 5, iclass 40, count 0 2006.280.07:45:40.61#ibcon#about to read 6, iclass 40, count 0 2006.280.07:45:40.61#ibcon#read 6, iclass 40, count 0 2006.280.07:45:40.61#ibcon#end of sib2, iclass 40, count 0 2006.280.07:45:40.61#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:45:40.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:45:40.61#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:45:40.61#ibcon#*before write, iclass 40, count 0 2006.280.07:45:40.61#ibcon#enter sib2, iclass 40, count 0 2006.280.07:45:40.61#ibcon#flushed, iclass 40, count 0 2006.280.07:45:40.61#ibcon#about to write, iclass 40, count 0 2006.280.07:45:40.61#ibcon#wrote, iclass 40, count 0 2006.280.07:45:40.61#ibcon#about to read 3, iclass 40, count 0 2006.280.07:45:40.65#ibcon#read 3, iclass 40, count 0 2006.280.07:45:40.65#ibcon#about to read 4, iclass 40, count 0 2006.280.07:45:40.65#ibcon#read 4, iclass 40, count 0 2006.280.07:45:40.65#ibcon#about to read 5, iclass 40, count 0 2006.280.07:45:40.65#ibcon#read 5, iclass 40, count 0 2006.280.07:45:40.65#ibcon#about to read 6, iclass 40, count 0 2006.280.07:45:40.65#ibcon#read 6, iclass 40, count 0 2006.280.07:45:40.65#ibcon#end of sib2, iclass 40, count 0 2006.280.07:45:40.65#ibcon#*after write, iclass 40, count 0 2006.280.07:45:40.65#ibcon#*before return 0, iclass 40, count 0 2006.280.07:45:40.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:40.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:40.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:45:40.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:45:40.65$vc4f8/va=7,6 2006.280.07:45:40.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.07:45:40.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.07:45:40.65#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:40.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:40.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:40.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:40.71#ibcon#enter wrdev, iclass 4, count 2 2006.280.07:45:40.71#ibcon#first serial, iclass 4, count 2 2006.280.07:45:40.71#ibcon#enter sib2, iclass 4, count 2 2006.280.07:45:40.71#ibcon#flushed, iclass 4, count 2 2006.280.07:45:40.71#ibcon#about to write, iclass 4, count 2 2006.280.07:45:40.71#ibcon#wrote, iclass 4, count 2 2006.280.07:45:40.71#ibcon#about to read 3, iclass 4, count 2 2006.280.07:45:40.73#ibcon#read 3, iclass 4, count 2 2006.280.07:45:40.73#ibcon#about to read 4, iclass 4, count 2 2006.280.07:45:40.73#ibcon#read 4, iclass 4, count 2 2006.280.07:45:40.73#ibcon#about to read 5, iclass 4, count 2 2006.280.07:45:40.73#ibcon#read 5, iclass 4, count 2 2006.280.07:45:40.73#ibcon#about to read 6, iclass 4, count 2 2006.280.07:45:40.73#ibcon#read 6, iclass 4, count 2 2006.280.07:45:40.73#ibcon#end of sib2, iclass 4, count 2 2006.280.07:45:40.73#ibcon#*mode == 0, iclass 4, count 2 2006.280.07:45:40.73#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.07:45:40.73#ibcon#[25=AT07-06\r\n] 2006.280.07:45:40.73#ibcon#*before write, iclass 4, count 2 2006.280.07:45:40.73#ibcon#enter sib2, iclass 4, count 2 2006.280.07:45:40.73#ibcon#flushed, iclass 4, count 2 2006.280.07:45:40.73#ibcon#about to write, iclass 4, count 2 2006.280.07:45:40.73#ibcon#wrote, iclass 4, count 2 2006.280.07:45:40.73#ibcon#about to read 3, iclass 4, count 2 2006.280.07:45:40.76#ibcon#read 3, iclass 4, count 2 2006.280.07:45:40.76#ibcon#about to read 4, iclass 4, count 2 2006.280.07:45:40.76#ibcon#read 4, iclass 4, count 2 2006.280.07:45:40.76#ibcon#about to read 5, iclass 4, count 2 2006.280.07:45:40.76#ibcon#read 5, iclass 4, count 2 2006.280.07:45:40.76#ibcon#about to read 6, iclass 4, count 2 2006.280.07:45:40.76#ibcon#read 6, iclass 4, count 2 2006.280.07:45:40.76#ibcon#end of sib2, iclass 4, count 2 2006.280.07:45:40.76#ibcon#*after write, iclass 4, count 2 2006.280.07:45:40.76#ibcon#*before return 0, iclass 4, count 2 2006.280.07:45:40.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:40.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:40.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.07:45:40.76#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:40.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:45:40.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:45:40.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:45:40.88#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:45:40.88#ibcon#first serial, iclass 4, count 0 2006.280.07:45:40.88#ibcon#enter sib2, iclass 4, count 0 2006.280.07:45:40.88#ibcon#flushed, iclass 4, count 0 2006.280.07:45:40.88#ibcon#about to write, iclass 4, count 0 2006.280.07:45:40.88#ibcon#wrote, iclass 4, count 0 2006.280.07:45:40.88#ibcon#about to read 3, iclass 4, count 0 2006.280.07:45:40.90#ibcon#read 3, iclass 4, count 0 2006.280.07:45:40.90#ibcon#about to read 4, iclass 4, count 0 2006.280.07:45:40.90#ibcon#read 4, iclass 4, count 0 2006.280.07:45:40.90#ibcon#about to read 5, iclass 4, count 0 2006.280.07:45:40.90#ibcon#read 5, iclass 4, count 0 2006.280.07:45:40.90#ibcon#about to read 6, iclass 4, count 0 2006.280.07:45:40.90#ibcon#read 6, iclass 4, count 0 2006.280.07:45:40.90#ibcon#end of sib2, iclass 4, count 0 2006.280.07:45:40.90#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:45:40.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:45:40.90#ibcon#[25=USB\r\n] 2006.280.07:45:40.90#ibcon#*before write, iclass 4, count 0 2006.280.07:45:40.90#ibcon#enter sib2, iclass 4, count 0 2006.280.07:45:40.90#ibcon#flushed, iclass 4, count 0 2006.280.07:45:40.90#ibcon#about to write, iclass 4, count 0 2006.280.07:45:40.90#ibcon#wrote, iclass 4, count 0 2006.280.07:45:40.90#ibcon#about to read 3, iclass 4, count 0 2006.280.07:45:40.93#ibcon#read 3, iclass 4, count 0 2006.280.07:45:40.93#ibcon#about to read 4, iclass 4, count 0 2006.280.07:45:40.93#ibcon#read 4, iclass 4, count 0 2006.280.07:45:40.93#ibcon#about to read 5, iclass 4, count 0 2006.280.07:45:40.93#ibcon#read 5, iclass 4, count 0 2006.280.07:45:40.93#ibcon#about to read 6, iclass 4, count 0 2006.280.07:45:40.93#ibcon#read 6, iclass 4, count 0 2006.280.07:45:40.93#ibcon#end of sib2, iclass 4, count 0 2006.280.07:45:40.93#ibcon#*after write, iclass 4, count 0 2006.280.07:45:40.93#ibcon#*before return 0, iclass 4, count 0 2006.280.07:45:40.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:45:40.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:45:40.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:45:40.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:45:40.93$vc4f8/valo=8,852.99 2006.280.07:45:40.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.07:45:40.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.07:45:40.93#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:40.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:45:40.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:45:40.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:45:40.93#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:45:40.93#ibcon#first serial, iclass 6, count 0 2006.280.07:45:40.93#ibcon#enter sib2, iclass 6, count 0 2006.280.07:45:40.93#ibcon#flushed, iclass 6, count 0 2006.280.07:45:40.93#ibcon#about to write, iclass 6, count 0 2006.280.07:45:40.93#ibcon#wrote, iclass 6, count 0 2006.280.07:45:40.93#ibcon#about to read 3, iclass 6, count 0 2006.280.07:45:40.95#ibcon#read 3, iclass 6, count 0 2006.280.07:45:40.95#ibcon#about to read 4, iclass 6, count 0 2006.280.07:45:40.95#ibcon#read 4, iclass 6, count 0 2006.280.07:45:40.95#ibcon#about to read 5, iclass 6, count 0 2006.280.07:45:40.95#ibcon#read 5, iclass 6, count 0 2006.280.07:45:40.95#ibcon#about to read 6, iclass 6, count 0 2006.280.07:45:40.95#ibcon#read 6, iclass 6, count 0 2006.280.07:45:40.95#ibcon#end of sib2, iclass 6, count 0 2006.280.07:45:40.95#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:45:40.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:45:40.95#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:45:40.95#ibcon#*before write, iclass 6, count 0 2006.280.07:45:40.95#ibcon#enter sib2, iclass 6, count 0 2006.280.07:45:40.95#ibcon#flushed, iclass 6, count 0 2006.280.07:45:40.95#ibcon#about to write, iclass 6, count 0 2006.280.07:45:40.95#ibcon#wrote, iclass 6, count 0 2006.280.07:45:40.95#ibcon#about to read 3, iclass 6, count 0 2006.280.07:45:40.99#ibcon#read 3, iclass 6, count 0 2006.280.07:45:40.99#ibcon#about to read 4, iclass 6, count 0 2006.280.07:45:40.99#ibcon#read 4, iclass 6, count 0 2006.280.07:45:40.99#ibcon#about to read 5, iclass 6, count 0 2006.280.07:45:40.99#ibcon#read 5, iclass 6, count 0 2006.280.07:45:40.99#ibcon#about to read 6, iclass 6, count 0 2006.280.07:45:40.99#ibcon#read 6, iclass 6, count 0 2006.280.07:45:40.99#ibcon#end of sib2, iclass 6, count 0 2006.280.07:45:40.99#ibcon#*after write, iclass 6, count 0 2006.280.07:45:40.99#ibcon#*before return 0, iclass 6, count 0 2006.280.07:45:40.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:45:40.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:45:40.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:45:40.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:45:40.99$vc4f8/va=8,6 2006.280.07:45:40.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.07:45:40.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.07:45:40.99#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:40.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:45:41.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:45:41.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:45:41.05#ibcon#enter wrdev, iclass 10, count 2 2006.280.07:45:41.05#ibcon#first serial, iclass 10, count 2 2006.280.07:45:41.05#ibcon#enter sib2, iclass 10, count 2 2006.280.07:45:41.05#ibcon#flushed, iclass 10, count 2 2006.280.07:45:41.05#ibcon#about to write, iclass 10, count 2 2006.280.07:45:41.05#ibcon#wrote, iclass 10, count 2 2006.280.07:45:41.05#ibcon#about to read 3, iclass 10, count 2 2006.280.07:45:41.07#ibcon#read 3, iclass 10, count 2 2006.280.07:45:41.07#ibcon#about to read 4, iclass 10, count 2 2006.280.07:45:41.07#ibcon#read 4, iclass 10, count 2 2006.280.07:45:41.07#ibcon#about to read 5, iclass 10, count 2 2006.280.07:45:41.07#ibcon#read 5, iclass 10, count 2 2006.280.07:45:41.07#ibcon#about to read 6, iclass 10, count 2 2006.280.07:45:41.07#ibcon#read 6, iclass 10, count 2 2006.280.07:45:41.07#ibcon#end of sib2, iclass 10, count 2 2006.280.07:45:41.07#ibcon#*mode == 0, iclass 10, count 2 2006.280.07:45:41.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.07:45:41.07#ibcon#[25=AT08-06\r\n] 2006.280.07:45:41.07#ibcon#*before write, iclass 10, count 2 2006.280.07:45:41.07#ibcon#enter sib2, iclass 10, count 2 2006.280.07:45:41.07#ibcon#flushed, iclass 10, count 2 2006.280.07:45:41.07#ibcon#about to write, iclass 10, count 2 2006.280.07:45:41.07#ibcon#wrote, iclass 10, count 2 2006.280.07:45:41.07#ibcon#about to read 3, iclass 10, count 2 2006.280.07:45:41.10#ibcon#read 3, iclass 10, count 2 2006.280.07:45:41.10#ibcon#about to read 4, iclass 10, count 2 2006.280.07:45:41.10#ibcon#read 4, iclass 10, count 2 2006.280.07:45:41.10#ibcon#about to read 5, iclass 10, count 2 2006.280.07:45:41.10#ibcon#read 5, iclass 10, count 2 2006.280.07:45:41.10#ibcon#about to read 6, iclass 10, count 2 2006.280.07:45:41.10#ibcon#read 6, iclass 10, count 2 2006.280.07:45:41.10#ibcon#end of sib2, iclass 10, count 2 2006.280.07:45:41.10#ibcon#*after write, iclass 10, count 2 2006.280.07:45:41.10#ibcon#*before return 0, iclass 10, count 2 2006.280.07:45:41.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:45:41.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:45:41.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.07:45:41.10#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:41.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:45:41.16#abcon#<5=/15 2.9 5.8 21.41 59 986.9\r\n> 2006.280.07:45:41.19#abcon#{5=INTERFACE CLEAR} 2006.280.07:45:41.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:45:41.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:45:41.22#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:45:41.22#ibcon#first serial, iclass 10, count 0 2006.280.07:45:41.22#ibcon#enter sib2, iclass 10, count 0 2006.280.07:45:41.22#ibcon#flushed, iclass 10, count 0 2006.280.07:45:41.22#ibcon#about to write, iclass 10, count 0 2006.280.07:45:41.22#ibcon#wrote, iclass 10, count 0 2006.280.07:45:41.22#ibcon#about to read 3, iclass 10, count 0 2006.280.07:45:41.24#ibcon#read 3, iclass 10, count 0 2006.280.07:45:41.24#ibcon#about to read 4, iclass 10, count 0 2006.280.07:45:41.24#ibcon#read 4, iclass 10, count 0 2006.280.07:45:41.24#ibcon#about to read 5, iclass 10, count 0 2006.280.07:45:41.24#ibcon#read 5, iclass 10, count 0 2006.280.07:45:41.24#ibcon#about to read 6, iclass 10, count 0 2006.280.07:45:41.24#ibcon#read 6, iclass 10, count 0 2006.280.07:45:41.24#ibcon#end of sib2, iclass 10, count 0 2006.280.07:45:41.24#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:45:41.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:45:41.24#ibcon#[25=USB\r\n] 2006.280.07:45:41.24#ibcon#*before write, iclass 10, count 0 2006.280.07:45:41.24#ibcon#enter sib2, iclass 10, count 0 2006.280.07:45:41.24#ibcon#flushed, iclass 10, count 0 2006.280.07:45:41.24#ibcon#about to write, iclass 10, count 0 2006.280.07:45:41.24#ibcon#wrote, iclass 10, count 0 2006.280.07:45:41.24#ibcon#about to read 3, iclass 10, count 0 2006.280.07:45:41.24#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:45:41.27#ibcon#read 3, iclass 10, count 0 2006.280.07:45:41.27#ibcon#about to read 4, iclass 10, count 0 2006.280.07:45:41.27#ibcon#read 4, iclass 10, count 0 2006.280.07:45:41.27#ibcon#about to read 5, iclass 10, count 0 2006.280.07:45:41.27#ibcon#read 5, iclass 10, count 0 2006.280.07:45:41.27#ibcon#about to read 6, iclass 10, count 0 2006.280.07:45:41.27#ibcon#read 6, iclass 10, count 0 2006.280.07:45:41.27#ibcon#end of sib2, iclass 10, count 0 2006.280.07:45:41.27#ibcon#*after write, iclass 10, count 0 2006.280.07:45:41.27#ibcon#*before return 0, iclass 10, count 0 2006.280.07:45:41.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:45:41.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:45:41.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:45:41.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:45:41.27$vc4f8/vblo=1,632.99 2006.280.07:45:41.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:45:41.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:45:41.27#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:41.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:41.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:41.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:41.27#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:45:41.27#ibcon#first serial, iclass 16, count 0 2006.280.07:45:41.27#ibcon#enter sib2, iclass 16, count 0 2006.280.07:45:41.27#ibcon#flushed, iclass 16, count 0 2006.280.07:45:41.27#ibcon#about to write, iclass 16, count 0 2006.280.07:45:41.27#ibcon#wrote, iclass 16, count 0 2006.280.07:45:41.27#ibcon#about to read 3, iclass 16, count 0 2006.280.07:45:41.29#ibcon#read 3, iclass 16, count 0 2006.280.07:45:41.31#ibcon#about to read 4, iclass 16, count 0 2006.280.07:45:41.31#ibcon#read 4, iclass 16, count 0 2006.280.07:45:41.31#ibcon#about to read 5, iclass 16, count 0 2006.280.07:45:41.31#ibcon#read 5, iclass 16, count 0 2006.280.07:45:41.31#ibcon#about to read 6, iclass 16, count 0 2006.280.07:45:41.31#ibcon#read 6, iclass 16, count 0 2006.280.07:45:41.31#ibcon#end of sib2, iclass 16, count 0 2006.280.07:45:41.31#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:45:41.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:45:41.31#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:45:41.31#ibcon#*before write, iclass 16, count 0 2006.280.07:45:41.31#ibcon#enter sib2, iclass 16, count 0 2006.280.07:45:41.31#ibcon#flushed, iclass 16, count 0 2006.280.07:45:41.31#ibcon#about to write, iclass 16, count 0 2006.280.07:45:41.31#ibcon#wrote, iclass 16, count 0 2006.280.07:45:41.31#ibcon#about to read 3, iclass 16, count 0 2006.280.07:45:41.35#ibcon#read 3, iclass 16, count 0 2006.280.07:45:41.35#ibcon#about to read 4, iclass 16, count 0 2006.280.07:45:41.35#ibcon#read 4, iclass 16, count 0 2006.280.07:45:41.35#ibcon#about to read 5, iclass 16, count 0 2006.280.07:45:41.35#ibcon#read 5, iclass 16, count 0 2006.280.07:45:41.35#ibcon#about to read 6, iclass 16, count 0 2006.280.07:45:41.35#ibcon#read 6, iclass 16, count 0 2006.280.07:45:41.35#ibcon#end of sib2, iclass 16, count 0 2006.280.07:45:41.35#ibcon#*after write, iclass 16, count 0 2006.280.07:45:41.35#ibcon#*before return 0, iclass 16, count 0 2006.280.07:45:41.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:41.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:45:41.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:45:41.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:45:41.35$vc4f8/vb=1,4 2006.280.07:45:41.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.07:45:41.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.07:45:41.35#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:41.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:41.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:41.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:41.35#ibcon#enter wrdev, iclass 18, count 2 2006.280.07:45:41.35#ibcon#first serial, iclass 18, count 2 2006.280.07:45:41.35#ibcon#enter sib2, iclass 18, count 2 2006.280.07:45:41.35#ibcon#flushed, iclass 18, count 2 2006.280.07:45:41.35#ibcon#about to write, iclass 18, count 2 2006.280.07:45:41.35#ibcon#wrote, iclass 18, count 2 2006.280.07:45:41.35#ibcon#about to read 3, iclass 18, count 2 2006.280.07:45:41.37#ibcon#read 3, iclass 18, count 2 2006.280.07:45:41.37#ibcon#about to read 4, iclass 18, count 2 2006.280.07:45:41.37#ibcon#read 4, iclass 18, count 2 2006.280.07:45:41.37#ibcon#about to read 5, iclass 18, count 2 2006.280.07:45:41.37#ibcon#read 5, iclass 18, count 2 2006.280.07:45:41.37#ibcon#about to read 6, iclass 18, count 2 2006.280.07:45:41.37#ibcon#read 6, iclass 18, count 2 2006.280.07:45:41.37#ibcon#end of sib2, iclass 18, count 2 2006.280.07:45:41.37#ibcon#*mode == 0, iclass 18, count 2 2006.280.07:45:41.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.07:45:41.37#ibcon#[27=AT01-04\r\n] 2006.280.07:45:41.37#ibcon#*before write, iclass 18, count 2 2006.280.07:45:41.37#ibcon#enter sib2, iclass 18, count 2 2006.280.07:45:41.37#ibcon#flushed, iclass 18, count 2 2006.280.07:45:41.37#ibcon#about to write, iclass 18, count 2 2006.280.07:45:41.37#ibcon#wrote, iclass 18, count 2 2006.280.07:45:41.37#ibcon#about to read 3, iclass 18, count 2 2006.280.07:45:41.40#ibcon#read 3, iclass 18, count 2 2006.280.07:45:41.40#ibcon#about to read 4, iclass 18, count 2 2006.280.07:45:41.40#ibcon#read 4, iclass 18, count 2 2006.280.07:45:41.40#ibcon#about to read 5, iclass 18, count 2 2006.280.07:45:41.40#ibcon#read 5, iclass 18, count 2 2006.280.07:45:41.40#ibcon#about to read 6, iclass 18, count 2 2006.280.07:45:41.40#ibcon#read 6, iclass 18, count 2 2006.280.07:45:41.40#ibcon#end of sib2, iclass 18, count 2 2006.280.07:45:41.40#ibcon#*after write, iclass 18, count 2 2006.280.07:45:41.40#ibcon#*before return 0, iclass 18, count 2 2006.280.07:45:41.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:41.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:45:41.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.07:45:41.40#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:41.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:41.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:41.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:41.52#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:45:41.52#ibcon#first serial, iclass 18, count 0 2006.280.07:45:41.52#ibcon#enter sib2, iclass 18, count 0 2006.280.07:45:41.52#ibcon#flushed, iclass 18, count 0 2006.280.07:45:41.52#ibcon#about to write, iclass 18, count 0 2006.280.07:45:41.52#ibcon#wrote, iclass 18, count 0 2006.280.07:45:41.52#ibcon#about to read 3, iclass 18, count 0 2006.280.07:45:41.54#ibcon#read 3, iclass 18, count 0 2006.280.07:45:41.54#ibcon#about to read 4, iclass 18, count 0 2006.280.07:45:41.54#ibcon#read 4, iclass 18, count 0 2006.280.07:45:41.54#ibcon#about to read 5, iclass 18, count 0 2006.280.07:45:41.54#ibcon#read 5, iclass 18, count 0 2006.280.07:45:41.54#ibcon#about to read 6, iclass 18, count 0 2006.280.07:45:41.54#ibcon#read 6, iclass 18, count 0 2006.280.07:45:41.54#ibcon#end of sib2, iclass 18, count 0 2006.280.07:45:41.54#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:45:41.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:45:41.54#ibcon#[27=USB\r\n] 2006.280.07:45:41.54#ibcon#*before write, iclass 18, count 0 2006.280.07:45:41.54#ibcon#enter sib2, iclass 18, count 0 2006.280.07:45:41.54#ibcon#flushed, iclass 18, count 0 2006.280.07:45:41.54#ibcon#about to write, iclass 18, count 0 2006.280.07:45:41.54#ibcon#wrote, iclass 18, count 0 2006.280.07:45:41.54#ibcon#about to read 3, iclass 18, count 0 2006.280.07:45:41.57#ibcon#read 3, iclass 18, count 0 2006.280.07:45:41.57#ibcon#about to read 4, iclass 18, count 0 2006.280.07:45:41.57#ibcon#read 4, iclass 18, count 0 2006.280.07:45:41.57#ibcon#about to read 5, iclass 18, count 0 2006.280.07:45:41.57#ibcon#read 5, iclass 18, count 0 2006.280.07:45:41.57#ibcon#about to read 6, iclass 18, count 0 2006.280.07:45:41.57#ibcon#read 6, iclass 18, count 0 2006.280.07:45:41.57#ibcon#end of sib2, iclass 18, count 0 2006.280.07:45:41.57#ibcon#*after write, iclass 18, count 0 2006.280.07:45:41.57#ibcon#*before return 0, iclass 18, count 0 2006.280.07:45:41.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:41.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:45:41.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:45:41.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:45:41.57$vc4f8/vblo=2,640.99 2006.280.07:45:41.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.07:45:41.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.07:45:41.57#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:41.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:41.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:41.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:41.57#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:45:41.57#ibcon#first serial, iclass 20, count 0 2006.280.07:45:41.57#ibcon#enter sib2, iclass 20, count 0 2006.280.07:45:41.57#ibcon#flushed, iclass 20, count 0 2006.280.07:45:41.57#ibcon#about to write, iclass 20, count 0 2006.280.07:45:41.57#ibcon#wrote, iclass 20, count 0 2006.280.07:45:41.57#ibcon#about to read 3, iclass 20, count 0 2006.280.07:45:41.60#ibcon#read 3, iclass 20, count 0 2006.280.07:45:41.60#ibcon#about to read 4, iclass 20, count 0 2006.280.07:45:41.60#ibcon#read 4, iclass 20, count 0 2006.280.07:45:41.60#ibcon#about to read 5, iclass 20, count 0 2006.280.07:45:41.60#ibcon#read 5, iclass 20, count 0 2006.280.07:45:41.60#ibcon#about to read 6, iclass 20, count 0 2006.280.07:45:41.60#ibcon#read 6, iclass 20, count 0 2006.280.07:45:41.60#ibcon#end of sib2, iclass 20, count 0 2006.280.07:45:41.60#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:45:41.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:45:41.63#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:45:41.63#ibcon#*before write, iclass 20, count 0 2006.280.07:45:41.63#ibcon#enter sib2, iclass 20, count 0 2006.280.07:45:41.63#ibcon#flushed, iclass 20, count 0 2006.280.07:45:41.63#ibcon#about to write, iclass 20, count 0 2006.280.07:45:41.63#ibcon#wrote, iclass 20, count 0 2006.280.07:45:41.63#ibcon#about to read 3, iclass 20, count 0 2006.280.07:45:41.66#ibcon#read 3, iclass 20, count 0 2006.280.07:45:41.66#ibcon#about to read 4, iclass 20, count 0 2006.280.07:45:41.66#ibcon#read 4, iclass 20, count 0 2006.280.07:45:41.66#ibcon#about to read 5, iclass 20, count 0 2006.280.07:45:41.66#ibcon#read 5, iclass 20, count 0 2006.280.07:45:41.66#ibcon#about to read 6, iclass 20, count 0 2006.280.07:45:41.66#ibcon#read 6, iclass 20, count 0 2006.280.07:45:41.66#ibcon#end of sib2, iclass 20, count 0 2006.280.07:45:41.66#ibcon#*after write, iclass 20, count 0 2006.280.07:45:41.66#ibcon#*before return 0, iclass 20, count 0 2006.280.07:45:41.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:41.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:45:41.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:45:41.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:45:41.66$vc4f8/vb=2,5 2006.280.07:45:41.66#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.07:45:41.66#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.07:45:41.66#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:41.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:41.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:41.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:41.69#ibcon#enter wrdev, iclass 22, count 2 2006.280.07:45:41.69#ibcon#first serial, iclass 22, count 2 2006.280.07:45:41.69#ibcon#enter sib2, iclass 22, count 2 2006.280.07:45:41.69#ibcon#flushed, iclass 22, count 2 2006.280.07:45:41.69#ibcon#about to write, iclass 22, count 2 2006.280.07:45:41.69#ibcon#wrote, iclass 22, count 2 2006.280.07:45:41.69#ibcon#about to read 3, iclass 22, count 2 2006.280.07:45:41.71#ibcon#read 3, iclass 22, count 2 2006.280.07:45:41.71#ibcon#about to read 4, iclass 22, count 2 2006.280.07:45:41.71#ibcon#read 4, iclass 22, count 2 2006.280.07:45:41.71#ibcon#about to read 5, iclass 22, count 2 2006.280.07:45:41.71#ibcon#read 5, iclass 22, count 2 2006.280.07:45:41.71#ibcon#about to read 6, iclass 22, count 2 2006.280.07:45:41.71#ibcon#read 6, iclass 22, count 2 2006.280.07:45:41.71#ibcon#end of sib2, iclass 22, count 2 2006.280.07:45:41.71#ibcon#*mode == 0, iclass 22, count 2 2006.280.07:45:41.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.07:45:41.71#ibcon#[27=AT02-05\r\n] 2006.280.07:45:41.71#ibcon#*before write, iclass 22, count 2 2006.280.07:45:41.71#ibcon#enter sib2, iclass 22, count 2 2006.280.07:45:41.71#ibcon#flushed, iclass 22, count 2 2006.280.07:45:41.71#ibcon#about to write, iclass 22, count 2 2006.280.07:45:41.71#ibcon#wrote, iclass 22, count 2 2006.280.07:45:41.71#ibcon#about to read 3, iclass 22, count 2 2006.280.07:45:41.74#ibcon#read 3, iclass 22, count 2 2006.280.07:45:41.74#ibcon#about to read 4, iclass 22, count 2 2006.280.07:45:41.74#ibcon#read 4, iclass 22, count 2 2006.280.07:45:41.74#ibcon#about to read 5, iclass 22, count 2 2006.280.07:45:41.74#ibcon#read 5, iclass 22, count 2 2006.280.07:45:41.74#ibcon#about to read 6, iclass 22, count 2 2006.280.07:45:41.74#ibcon#read 6, iclass 22, count 2 2006.280.07:45:41.74#ibcon#end of sib2, iclass 22, count 2 2006.280.07:45:41.74#ibcon#*after write, iclass 22, count 2 2006.280.07:45:41.74#ibcon#*before return 0, iclass 22, count 2 2006.280.07:45:41.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:41.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:45:41.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.07:45:41.74#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:41.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:41.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:41.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:41.86#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:45:41.86#ibcon#first serial, iclass 22, count 0 2006.280.07:45:41.86#ibcon#enter sib2, iclass 22, count 0 2006.280.07:45:41.86#ibcon#flushed, iclass 22, count 0 2006.280.07:45:41.86#ibcon#about to write, iclass 22, count 0 2006.280.07:45:41.86#ibcon#wrote, iclass 22, count 0 2006.280.07:45:41.86#ibcon#about to read 3, iclass 22, count 0 2006.280.07:45:41.88#ibcon#read 3, iclass 22, count 0 2006.280.07:45:41.88#ibcon#about to read 4, iclass 22, count 0 2006.280.07:45:41.88#ibcon#read 4, iclass 22, count 0 2006.280.07:45:41.88#ibcon#about to read 5, iclass 22, count 0 2006.280.07:45:41.88#ibcon#read 5, iclass 22, count 0 2006.280.07:45:41.88#ibcon#about to read 6, iclass 22, count 0 2006.280.07:45:41.88#ibcon#read 6, iclass 22, count 0 2006.280.07:45:41.88#ibcon#end of sib2, iclass 22, count 0 2006.280.07:45:41.88#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:45:41.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:45:41.88#ibcon#[27=USB\r\n] 2006.280.07:45:41.88#ibcon#*before write, iclass 22, count 0 2006.280.07:45:41.88#ibcon#enter sib2, iclass 22, count 0 2006.280.07:45:41.88#ibcon#flushed, iclass 22, count 0 2006.280.07:45:41.88#ibcon#about to write, iclass 22, count 0 2006.280.07:45:41.88#ibcon#wrote, iclass 22, count 0 2006.280.07:45:41.88#ibcon#about to read 3, iclass 22, count 0 2006.280.07:45:41.91#ibcon#read 3, iclass 22, count 0 2006.280.07:45:41.91#ibcon#about to read 4, iclass 22, count 0 2006.280.07:45:41.91#ibcon#read 4, iclass 22, count 0 2006.280.07:45:41.91#ibcon#about to read 5, iclass 22, count 0 2006.280.07:45:41.91#ibcon#read 5, iclass 22, count 0 2006.280.07:45:41.91#ibcon#about to read 6, iclass 22, count 0 2006.280.07:45:41.91#ibcon#read 6, iclass 22, count 0 2006.280.07:45:41.91#ibcon#end of sib2, iclass 22, count 0 2006.280.07:45:41.91#ibcon#*after write, iclass 22, count 0 2006.280.07:45:41.91#ibcon#*before return 0, iclass 22, count 0 2006.280.07:45:41.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:41.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:45:41.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:45:41.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:45:41.91$vc4f8/vblo=3,656.99 2006.280.07:45:41.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.07:45:41.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.07:45:41.91#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:41.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:41.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:41.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:41.91#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:45:41.91#ibcon#first serial, iclass 24, count 0 2006.280.07:45:41.91#ibcon#enter sib2, iclass 24, count 0 2006.280.07:45:41.91#ibcon#flushed, iclass 24, count 0 2006.280.07:45:41.91#ibcon#about to write, iclass 24, count 0 2006.280.07:45:41.91#ibcon#wrote, iclass 24, count 0 2006.280.07:45:41.91#ibcon#about to read 3, iclass 24, count 0 2006.280.07:45:41.93#ibcon#read 3, iclass 24, count 0 2006.280.07:45:41.94#ibcon#about to read 4, iclass 24, count 0 2006.280.07:45:41.94#ibcon#read 4, iclass 24, count 0 2006.280.07:45:41.94#ibcon#about to read 5, iclass 24, count 0 2006.280.07:45:41.94#ibcon#read 5, iclass 24, count 0 2006.280.07:45:41.94#ibcon#about to read 6, iclass 24, count 0 2006.280.07:45:41.94#ibcon#read 6, iclass 24, count 0 2006.280.07:45:41.94#ibcon#end of sib2, iclass 24, count 0 2006.280.07:45:41.94#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:45:41.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:45:41.94#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:45:41.94#ibcon#*before write, iclass 24, count 0 2006.280.07:45:41.94#ibcon#enter sib2, iclass 24, count 0 2006.280.07:45:41.94#ibcon#flushed, iclass 24, count 0 2006.280.07:45:41.94#ibcon#about to write, iclass 24, count 0 2006.280.07:45:41.94#ibcon#wrote, iclass 24, count 0 2006.280.07:45:41.94#ibcon#about to read 3, iclass 24, count 0 2006.280.07:45:41.97#ibcon#read 3, iclass 24, count 0 2006.280.07:45:41.97#ibcon#about to read 4, iclass 24, count 0 2006.280.07:45:41.97#ibcon#read 4, iclass 24, count 0 2006.280.07:45:41.97#ibcon#about to read 5, iclass 24, count 0 2006.280.07:45:41.97#ibcon#read 5, iclass 24, count 0 2006.280.07:45:41.97#ibcon#about to read 6, iclass 24, count 0 2006.280.07:45:41.97#ibcon#read 6, iclass 24, count 0 2006.280.07:45:41.97#ibcon#end of sib2, iclass 24, count 0 2006.280.07:45:41.97#ibcon#*after write, iclass 24, count 0 2006.280.07:45:41.97#ibcon#*before return 0, iclass 24, count 0 2006.280.07:45:41.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:41.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:45:41.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:45:41.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:45:41.97$vc4f8/vb=3,4 2006.280.07:45:41.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.07:45:41.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.07:45:41.97#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:41.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:42.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:42.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:42.03#ibcon#enter wrdev, iclass 26, count 2 2006.280.07:45:42.03#ibcon#first serial, iclass 26, count 2 2006.280.07:45:42.03#ibcon#enter sib2, iclass 26, count 2 2006.280.07:45:42.03#ibcon#flushed, iclass 26, count 2 2006.280.07:45:42.03#ibcon#about to write, iclass 26, count 2 2006.280.07:45:42.03#ibcon#wrote, iclass 26, count 2 2006.280.07:45:42.03#ibcon#about to read 3, iclass 26, count 2 2006.280.07:45:42.05#ibcon#read 3, iclass 26, count 2 2006.280.07:45:42.05#ibcon#about to read 4, iclass 26, count 2 2006.280.07:45:42.05#ibcon#read 4, iclass 26, count 2 2006.280.07:45:42.05#ibcon#about to read 5, iclass 26, count 2 2006.280.07:45:42.05#ibcon#read 5, iclass 26, count 2 2006.280.07:45:42.05#ibcon#about to read 6, iclass 26, count 2 2006.280.07:45:42.05#ibcon#read 6, iclass 26, count 2 2006.280.07:45:42.05#ibcon#end of sib2, iclass 26, count 2 2006.280.07:45:42.05#ibcon#*mode == 0, iclass 26, count 2 2006.280.07:45:42.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.07:45:42.05#ibcon#[27=AT03-04\r\n] 2006.280.07:45:42.05#ibcon#*before write, iclass 26, count 2 2006.280.07:45:42.05#ibcon#enter sib2, iclass 26, count 2 2006.280.07:45:42.05#ibcon#flushed, iclass 26, count 2 2006.280.07:45:42.05#ibcon#about to write, iclass 26, count 2 2006.280.07:45:42.05#ibcon#wrote, iclass 26, count 2 2006.280.07:45:42.05#ibcon#about to read 3, iclass 26, count 2 2006.280.07:45:42.08#ibcon#read 3, iclass 26, count 2 2006.280.07:45:42.08#ibcon#about to read 4, iclass 26, count 2 2006.280.07:45:42.08#ibcon#read 4, iclass 26, count 2 2006.280.07:45:42.08#ibcon#about to read 5, iclass 26, count 2 2006.280.07:45:42.08#ibcon#read 5, iclass 26, count 2 2006.280.07:45:42.08#ibcon#about to read 6, iclass 26, count 2 2006.280.07:45:42.08#ibcon#read 6, iclass 26, count 2 2006.280.07:45:42.08#ibcon#end of sib2, iclass 26, count 2 2006.280.07:45:42.08#ibcon#*after write, iclass 26, count 2 2006.280.07:45:42.08#ibcon#*before return 0, iclass 26, count 2 2006.280.07:45:42.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:42.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:45:42.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.07:45:42.08#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:42.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:42.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:42.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:42.20#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:45:42.20#ibcon#first serial, iclass 26, count 0 2006.280.07:45:42.20#ibcon#enter sib2, iclass 26, count 0 2006.280.07:45:42.20#ibcon#flushed, iclass 26, count 0 2006.280.07:45:42.20#ibcon#about to write, iclass 26, count 0 2006.280.07:45:42.20#ibcon#wrote, iclass 26, count 0 2006.280.07:45:42.20#ibcon#about to read 3, iclass 26, count 0 2006.280.07:45:42.22#ibcon#read 3, iclass 26, count 0 2006.280.07:45:42.22#ibcon#about to read 4, iclass 26, count 0 2006.280.07:45:42.22#ibcon#read 4, iclass 26, count 0 2006.280.07:45:42.22#ibcon#about to read 5, iclass 26, count 0 2006.280.07:45:42.22#ibcon#read 5, iclass 26, count 0 2006.280.07:45:42.22#ibcon#about to read 6, iclass 26, count 0 2006.280.07:45:42.22#ibcon#read 6, iclass 26, count 0 2006.280.07:45:42.22#ibcon#end of sib2, iclass 26, count 0 2006.280.07:45:42.22#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:45:42.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:45:42.22#ibcon#[27=USB\r\n] 2006.280.07:45:42.22#ibcon#*before write, iclass 26, count 0 2006.280.07:45:42.22#ibcon#enter sib2, iclass 26, count 0 2006.280.07:45:42.22#ibcon#flushed, iclass 26, count 0 2006.280.07:45:42.22#ibcon#about to write, iclass 26, count 0 2006.280.07:45:42.22#ibcon#wrote, iclass 26, count 0 2006.280.07:45:42.22#ibcon#about to read 3, iclass 26, count 0 2006.280.07:45:42.25#ibcon#read 3, iclass 26, count 0 2006.280.07:45:42.25#ibcon#about to read 4, iclass 26, count 0 2006.280.07:45:42.25#ibcon#read 4, iclass 26, count 0 2006.280.07:45:42.25#ibcon#about to read 5, iclass 26, count 0 2006.280.07:45:42.25#ibcon#read 5, iclass 26, count 0 2006.280.07:45:42.25#ibcon#about to read 6, iclass 26, count 0 2006.280.07:45:42.25#ibcon#read 6, iclass 26, count 0 2006.280.07:45:42.25#ibcon#end of sib2, iclass 26, count 0 2006.280.07:45:42.25#ibcon#*after write, iclass 26, count 0 2006.280.07:45:42.25#ibcon#*before return 0, iclass 26, count 0 2006.280.07:45:42.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:42.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:45:42.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:45:42.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:45:42.25$vc4f8/vblo=4,712.99 2006.280.07:45:42.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.07:45:42.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.07:45:42.25#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:42.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:42.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:42.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:42.25#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:45:42.25#ibcon#first serial, iclass 28, count 0 2006.280.07:45:42.25#ibcon#enter sib2, iclass 28, count 0 2006.280.07:45:42.25#ibcon#flushed, iclass 28, count 0 2006.280.07:45:42.25#ibcon#about to write, iclass 28, count 0 2006.280.07:45:42.25#ibcon#wrote, iclass 28, count 0 2006.280.07:45:42.25#ibcon#about to read 3, iclass 28, count 0 2006.280.07:45:42.27#ibcon#read 3, iclass 28, count 0 2006.280.07:45:42.27#ibcon#about to read 4, iclass 28, count 0 2006.280.07:45:42.27#ibcon#read 4, iclass 28, count 0 2006.280.07:45:42.27#ibcon#about to read 5, iclass 28, count 0 2006.280.07:45:42.27#ibcon#read 5, iclass 28, count 0 2006.280.07:45:42.27#ibcon#about to read 6, iclass 28, count 0 2006.280.07:45:42.27#ibcon#read 6, iclass 28, count 0 2006.280.07:45:42.27#ibcon#end of sib2, iclass 28, count 0 2006.280.07:45:42.27#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:45:42.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:45:42.27#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:45:42.27#ibcon#*before write, iclass 28, count 0 2006.280.07:45:42.27#ibcon#enter sib2, iclass 28, count 0 2006.280.07:45:42.27#ibcon#flushed, iclass 28, count 0 2006.280.07:45:42.27#ibcon#about to write, iclass 28, count 0 2006.280.07:45:42.27#ibcon#wrote, iclass 28, count 0 2006.280.07:45:42.27#ibcon#about to read 3, iclass 28, count 0 2006.280.07:45:42.32#ibcon#read 3, iclass 28, count 0 2006.280.07:45:42.32#ibcon#about to read 4, iclass 28, count 0 2006.280.07:45:42.32#ibcon#read 4, iclass 28, count 0 2006.280.07:45:42.32#ibcon#about to read 5, iclass 28, count 0 2006.280.07:45:42.32#ibcon#read 5, iclass 28, count 0 2006.280.07:45:42.32#ibcon#about to read 6, iclass 28, count 0 2006.280.07:45:42.32#ibcon#read 6, iclass 28, count 0 2006.280.07:45:42.32#ibcon#end of sib2, iclass 28, count 0 2006.280.07:45:42.32#ibcon#*after write, iclass 28, count 0 2006.280.07:45:42.32#ibcon#*before return 0, iclass 28, count 0 2006.280.07:45:42.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:42.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:45:42.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:45:42.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:45:42.32$vc4f8/vb=4,4 2006.280.07:45:42.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.07:45:42.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.07:45:42.32#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:42.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:42.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:42.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:42.36#ibcon#enter wrdev, iclass 30, count 2 2006.280.07:45:42.36#ibcon#first serial, iclass 30, count 2 2006.280.07:45:42.36#ibcon#enter sib2, iclass 30, count 2 2006.280.07:45:42.36#ibcon#flushed, iclass 30, count 2 2006.280.07:45:42.36#ibcon#about to write, iclass 30, count 2 2006.280.07:45:42.36#ibcon#wrote, iclass 30, count 2 2006.280.07:45:42.36#ibcon#about to read 3, iclass 30, count 2 2006.280.07:45:42.38#ibcon#read 3, iclass 30, count 2 2006.280.07:45:42.38#ibcon#about to read 4, iclass 30, count 2 2006.280.07:45:42.38#ibcon#read 4, iclass 30, count 2 2006.280.07:45:42.38#ibcon#about to read 5, iclass 30, count 2 2006.280.07:45:42.38#ibcon#read 5, iclass 30, count 2 2006.280.07:45:42.38#ibcon#about to read 6, iclass 30, count 2 2006.280.07:45:42.38#ibcon#read 6, iclass 30, count 2 2006.280.07:45:42.38#ibcon#end of sib2, iclass 30, count 2 2006.280.07:45:42.38#ibcon#*mode == 0, iclass 30, count 2 2006.280.07:45:42.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.07:45:42.38#ibcon#[27=AT04-04\r\n] 2006.280.07:45:42.38#ibcon#*before write, iclass 30, count 2 2006.280.07:45:42.38#ibcon#enter sib2, iclass 30, count 2 2006.280.07:45:42.38#ibcon#flushed, iclass 30, count 2 2006.280.07:45:42.38#ibcon#about to write, iclass 30, count 2 2006.280.07:45:42.38#ibcon#wrote, iclass 30, count 2 2006.280.07:45:42.38#ibcon#about to read 3, iclass 30, count 2 2006.280.07:45:42.42#ibcon#read 3, iclass 30, count 2 2006.280.07:45:42.42#ibcon#about to read 4, iclass 30, count 2 2006.280.07:45:42.42#ibcon#read 4, iclass 30, count 2 2006.280.07:45:42.42#ibcon#about to read 5, iclass 30, count 2 2006.280.07:45:42.42#ibcon#read 5, iclass 30, count 2 2006.280.07:45:42.42#ibcon#about to read 6, iclass 30, count 2 2006.280.07:45:42.42#ibcon#read 6, iclass 30, count 2 2006.280.07:45:42.42#ibcon#end of sib2, iclass 30, count 2 2006.280.07:45:42.42#ibcon#*after write, iclass 30, count 2 2006.280.07:45:42.42#ibcon#*before return 0, iclass 30, count 2 2006.280.07:45:42.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:42.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:45:42.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.07:45:42.42#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:42.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:42.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:42.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:42.53#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:45:42.53#ibcon#first serial, iclass 30, count 0 2006.280.07:45:42.53#ibcon#enter sib2, iclass 30, count 0 2006.280.07:45:42.53#ibcon#flushed, iclass 30, count 0 2006.280.07:45:42.53#ibcon#about to write, iclass 30, count 0 2006.280.07:45:42.53#ibcon#wrote, iclass 30, count 0 2006.280.07:45:42.53#ibcon#about to read 3, iclass 30, count 0 2006.280.07:45:42.56#ibcon#read 3, iclass 30, count 0 2006.280.07:45:42.56#ibcon#about to read 4, iclass 30, count 0 2006.280.07:45:42.56#ibcon#read 4, iclass 30, count 0 2006.280.07:45:42.56#ibcon#about to read 5, iclass 30, count 0 2006.280.07:45:42.56#ibcon#read 5, iclass 30, count 0 2006.280.07:45:42.56#ibcon#about to read 6, iclass 30, count 0 2006.280.07:45:42.56#ibcon#read 6, iclass 30, count 0 2006.280.07:45:42.56#ibcon#end of sib2, iclass 30, count 0 2006.280.07:45:42.56#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:45:42.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:45:42.56#ibcon#[27=USB\r\n] 2006.280.07:45:42.56#ibcon#*before write, iclass 30, count 0 2006.280.07:45:42.56#ibcon#enter sib2, iclass 30, count 0 2006.280.07:45:42.56#ibcon#flushed, iclass 30, count 0 2006.280.07:45:42.56#ibcon#about to write, iclass 30, count 0 2006.280.07:45:42.56#ibcon#wrote, iclass 30, count 0 2006.280.07:45:42.56#ibcon#about to read 3, iclass 30, count 0 2006.280.07:45:42.58#ibcon#read 3, iclass 30, count 0 2006.280.07:45:42.58#ibcon#about to read 4, iclass 30, count 0 2006.280.07:45:42.58#ibcon#read 4, iclass 30, count 0 2006.280.07:45:42.58#ibcon#about to read 5, iclass 30, count 0 2006.280.07:45:42.58#ibcon#read 5, iclass 30, count 0 2006.280.07:45:42.58#ibcon#about to read 6, iclass 30, count 0 2006.280.07:45:42.58#ibcon#read 6, iclass 30, count 0 2006.280.07:45:42.58#ibcon#end of sib2, iclass 30, count 0 2006.280.07:45:42.58#ibcon#*after write, iclass 30, count 0 2006.280.07:45:42.58#ibcon#*before return 0, iclass 30, count 0 2006.280.07:45:42.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:42.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:45:42.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:45:42.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:45:42.58$vc4f8/vblo=5,744.99 2006.280.07:45:42.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:45:42.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:45:42.58#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:42.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:42.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:42.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:42.58#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:45:42.58#ibcon#first serial, iclass 32, count 0 2006.280.07:45:42.58#ibcon#enter sib2, iclass 32, count 0 2006.280.07:45:42.58#ibcon#flushed, iclass 32, count 0 2006.280.07:45:42.58#ibcon#about to write, iclass 32, count 0 2006.280.07:45:42.58#ibcon#wrote, iclass 32, count 0 2006.280.07:45:42.58#ibcon#about to read 3, iclass 32, count 0 2006.280.07:45:42.60#ibcon#read 3, iclass 32, count 0 2006.280.07:45:42.60#ibcon#about to read 4, iclass 32, count 0 2006.280.07:45:42.60#ibcon#read 4, iclass 32, count 0 2006.280.07:45:42.60#ibcon#about to read 5, iclass 32, count 0 2006.280.07:45:42.60#ibcon#read 5, iclass 32, count 0 2006.280.07:45:42.60#ibcon#about to read 6, iclass 32, count 0 2006.280.07:45:42.60#ibcon#read 6, iclass 32, count 0 2006.280.07:45:42.60#ibcon#end of sib2, iclass 32, count 0 2006.280.07:45:42.60#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:45:42.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:45:42.60#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:45:42.60#ibcon#*before write, iclass 32, count 0 2006.280.07:45:42.60#ibcon#enter sib2, iclass 32, count 0 2006.280.07:45:42.60#ibcon#flushed, iclass 32, count 0 2006.280.07:45:42.60#ibcon#about to write, iclass 32, count 0 2006.280.07:45:42.60#ibcon#wrote, iclass 32, count 0 2006.280.07:45:42.60#ibcon#about to read 3, iclass 32, count 0 2006.280.07:45:42.64#ibcon#read 3, iclass 32, count 0 2006.280.07:45:42.64#ibcon#about to read 4, iclass 32, count 0 2006.280.07:45:42.64#ibcon#read 4, iclass 32, count 0 2006.280.07:45:42.64#ibcon#about to read 5, iclass 32, count 0 2006.280.07:45:42.64#ibcon#read 5, iclass 32, count 0 2006.280.07:45:42.64#ibcon#about to read 6, iclass 32, count 0 2006.280.07:45:42.64#ibcon#read 6, iclass 32, count 0 2006.280.07:45:42.64#ibcon#end of sib2, iclass 32, count 0 2006.280.07:45:42.64#ibcon#*after write, iclass 32, count 0 2006.280.07:45:42.64#ibcon#*before return 0, iclass 32, count 0 2006.280.07:45:42.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:42.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:45:42.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:45:42.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:45:42.64$vc4f8/vb=5,4 2006.280.07:45:42.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.07:45:42.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.07:45:42.64#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:42.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:42.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:42.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:42.70#ibcon#enter wrdev, iclass 34, count 2 2006.280.07:45:42.70#ibcon#first serial, iclass 34, count 2 2006.280.07:45:42.70#ibcon#enter sib2, iclass 34, count 2 2006.280.07:45:42.70#ibcon#flushed, iclass 34, count 2 2006.280.07:45:42.70#ibcon#about to write, iclass 34, count 2 2006.280.07:45:42.70#ibcon#wrote, iclass 34, count 2 2006.280.07:45:42.70#ibcon#about to read 3, iclass 34, count 2 2006.280.07:45:42.72#ibcon#read 3, iclass 34, count 2 2006.280.07:45:42.72#ibcon#about to read 4, iclass 34, count 2 2006.280.07:45:42.72#ibcon#read 4, iclass 34, count 2 2006.280.07:45:42.72#ibcon#about to read 5, iclass 34, count 2 2006.280.07:45:42.72#ibcon#read 5, iclass 34, count 2 2006.280.07:45:42.72#ibcon#about to read 6, iclass 34, count 2 2006.280.07:45:42.72#ibcon#read 6, iclass 34, count 2 2006.280.07:45:42.72#ibcon#end of sib2, iclass 34, count 2 2006.280.07:45:42.72#ibcon#*mode == 0, iclass 34, count 2 2006.280.07:45:42.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.07:45:42.72#ibcon#[27=AT05-04\r\n] 2006.280.07:45:42.72#ibcon#*before write, iclass 34, count 2 2006.280.07:45:42.72#ibcon#enter sib2, iclass 34, count 2 2006.280.07:45:42.72#ibcon#flushed, iclass 34, count 2 2006.280.07:45:42.72#ibcon#about to write, iclass 34, count 2 2006.280.07:45:42.72#ibcon#wrote, iclass 34, count 2 2006.280.07:45:42.72#ibcon#about to read 3, iclass 34, count 2 2006.280.07:45:42.75#ibcon#read 3, iclass 34, count 2 2006.280.07:45:42.75#ibcon#about to read 4, iclass 34, count 2 2006.280.07:45:42.75#ibcon#read 4, iclass 34, count 2 2006.280.07:45:42.75#ibcon#about to read 5, iclass 34, count 2 2006.280.07:45:42.75#ibcon#read 5, iclass 34, count 2 2006.280.07:45:42.75#ibcon#about to read 6, iclass 34, count 2 2006.280.07:45:42.75#ibcon#read 6, iclass 34, count 2 2006.280.07:45:42.75#ibcon#end of sib2, iclass 34, count 2 2006.280.07:45:42.75#ibcon#*after write, iclass 34, count 2 2006.280.07:45:42.75#ibcon#*before return 0, iclass 34, count 2 2006.280.07:45:42.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:42.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:45:42.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.07:45:42.75#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:42.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:42.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:42.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:42.87#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:45:42.87#ibcon#first serial, iclass 34, count 0 2006.280.07:45:42.87#ibcon#enter sib2, iclass 34, count 0 2006.280.07:45:42.87#ibcon#flushed, iclass 34, count 0 2006.280.07:45:42.87#ibcon#about to write, iclass 34, count 0 2006.280.07:45:42.87#ibcon#wrote, iclass 34, count 0 2006.280.07:45:42.87#ibcon#about to read 3, iclass 34, count 0 2006.280.07:45:42.89#ibcon#read 3, iclass 34, count 0 2006.280.07:45:42.89#ibcon#about to read 4, iclass 34, count 0 2006.280.07:45:42.89#ibcon#read 4, iclass 34, count 0 2006.280.07:45:42.89#ibcon#about to read 5, iclass 34, count 0 2006.280.07:45:42.89#ibcon#read 5, iclass 34, count 0 2006.280.07:45:42.89#ibcon#about to read 6, iclass 34, count 0 2006.280.07:45:42.89#ibcon#read 6, iclass 34, count 0 2006.280.07:45:42.89#ibcon#end of sib2, iclass 34, count 0 2006.280.07:45:42.89#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:45:42.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:45:42.89#ibcon#[27=USB\r\n] 2006.280.07:45:42.89#ibcon#*before write, iclass 34, count 0 2006.280.07:45:42.89#ibcon#enter sib2, iclass 34, count 0 2006.280.07:45:42.89#ibcon#flushed, iclass 34, count 0 2006.280.07:45:42.89#ibcon#about to write, iclass 34, count 0 2006.280.07:45:42.89#ibcon#wrote, iclass 34, count 0 2006.280.07:45:42.89#ibcon#about to read 3, iclass 34, count 0 2006.280.07:45:42.92#ibcon#read 3, iclass 34, count 0 2006.280.07:45:42.92#ibcon#about to read 4, iclass 34, count 0 2006.280.07:45:42.92#ibcon#read 4, iclass 34, count 0 2006.280.07:45:42.92#ibcon#about to read 5, iclass 34, count 0 2006.280.07:45:42.92#ibcon#read 5, iclass 34, count 0 2006.280.07:45:42.92#ibcon#about to read 6, iclass 34, count 0 2006.280.07:45:42.92#ibcon#read 6, iclass 34, count 0 2006.280.07:45:42.92#ibcon#end of sib2, iclass 34, count 0 2006.280.07:45:42.92#ibcon#*after write, iclass 34, count 0 2006.280.07:45:42.92#ibcon#*before return 0, iclass 34, count 0 2006.280.07:45:42.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:42.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:45:42.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:45:42.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:45:42.92$vc4f8/vblo=6,752.99 2006.280.07:45:42.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.07:45:42.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.07:45:42.92#ibcon#ireg 17 cls_cnt 0 2006.280.07:45:42.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:42.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:42.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:42.92#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:45:42.92#ibcon#first serial, iclass 36, count 0 2006.280.07:45:42.92#ibcon#enter sib2, iclass 36, count 0 2006.280.07:45:42.92#ibcon#flushed, iclass 36, count 0 2006.280.07:45:42.92#ibcon#about to write, iclass 36, count 0 2006.280.07:45:42.92#ibcon#wrote, iclass 36, count 0 2006.280.07:45:42.92#ibcon#about to read 3, iclass 36, count 0 2006.280.07:45:42.94#ibcon#read 3, iclass 36, count 0 2006.280.07:45:42.94#ibcon#about to read 4, iclass 36, count 0 2006.280.07:45:42.94#ibcon#read 4, iclass 36, count 0 2006.280.07:45:42.94#ibcon#about to read 5, iclass 36, count 0 2006.280.07:45:42.94#ibcon#read 5, iclass 36, count 0 2006.280.07:45:42.94#ibcon#about to read 6, iclass 36, count 0 2006.280.07:45:42.94#ibcon#read 6, iclass 36, count 0 2006.280.07:45:42.94#ibcon#end of sib2, iclass 36, count 0 2006.280.07:45:42.94#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:45:42.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:45:42.94#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:45:42.94#ibcon#*before write, iclass 36, count 0 2006.280.07:45:42.94#ibcon#enter sib2, iclass 36, count 0 2006.280.07:45:42.94#ibcon#flushed, iclass 36, count 0 2006.280.07:45:42.94#ibcon#about to write, iclass 36, count 0 2006.280.07:45:42.94#ibcon#wrote, iclass 36, count 0 2006.280.07:45:42.94#ibcon#about to read 3, iclass 36, count 0 2006.280.07:45:42.98#ibcon#read 3, iclass 36, count 0 2006.280.07:45:42.98#ibcon#about to read 4, iclass 36, count 0 2006.280.07:45:42.98#ibcon#read 4, iclass 36, count 0 2006.280.07:45:42.98#ibcon#about to read 5, iclass 36, count 0 2006.280.07:45:42.98#ibcon#read 5, iclass 36, count 0 2006.280.07:45:42.98#ibcon#about to read 6, iclass 36, count 0 2006.280.07:45:42.98#ibcon#read 6, iclass 36, count 0 2006.280.07:45:42.98#ibcon#end of sib2, iclass 36, count 0 2006.280.07:45:42.98#ibcon#*after write, iclass 36, count 0 2006.280.07:45:42.98#ibcon#*before return 0, iclass 36, count 0 2006.280.07:45:42.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:42.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:45:42.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:45:42.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:45:42.98$vc4f8/vb=6,4 2006.280.07:45:42.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.07:45:42.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.07:45:42.98#ibcon#ireg 11 cls_cnt 2 2006.280.07:45:42.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:43.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:43.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:43.04#ibcon#enter wrdev, iclass 38, count 2 2006.280.07:45:43.04#ibcon#first serial, iclass 38, count 2 2006.280.07:45:43.04#ibcon#enter sib2, iclass 38, count 2 2006.280.07:45:43.04#ibcon#flushed, iclass 38, count 2 2006.280.07:45:43.04#ibcon#about to write, iclass 38, count 2 2006.280.07:45:43.04#ibcon#wrote, iclass 38, count 2 2006.280.07:45:43.04#ibcon#about to read 3, iclass 38, count 2 2006.280.07:45:43.06#ibcon#read 3, iclass 38, count 2 2006.280.07:45:43.06#ibcon#about to read 4, iclass 38, count 2 2006.280.07:45:43.06#ibcon#read 4, iclass 38, count 2 2006.280.07:45:43.06#ibcon#about to read 5, iclass 38, count 2 2006.280.07:45:43.06#ibcon#read 5, iclass 38, count 2 2006.280.07:45:43.06#ibcon#about to read 6, iclass 38, count 2 2006.280.07:45:43.06#ibcon#read 6, iclass 38, count 2 2006.280.07:45:43.06#ibcon#end of sib2, iclass 38, count 2 2006.280.07:45:43.06#ibcon#*mode == 0, iclass 38, count 2 2006.280.07:45:43.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.07:45:43.06#ibcon#[27=AT06-04\r\n] 2006.280.07:45:43.06#ibcon#*before write, iclass 38, count 2 2006.280.07:45:43.06#ibcon#enter sib2, iclass 38, count 2 2006.280.07:45:43.06#ibcon#flushed, iclass 38, count 2 2006.280.07:45:43.06#ibcon#about to write, iclass 38, count 2 2006.280.07:45:43.06#ibcon#wrote, iclass 38, count 2 2006.280.07:45:43.06#ibcon#about to read 3, iclass 38, count 2 2006.280.07:45:43.09#ibcon#read 3, iclass 38, count 2 2006.280.07:45:43.09#ibcon#about to read 4, iclass 38, count 2 2006.280.07:45:43.09#ibcon#read 4, iclass 38, count 2 2006.280.07:45:43.09#ibcon#about to read 5, iclass 38, count 2 2006.280.07:45:43.09#ibcon#read 5, iclass 38, count 2 2006.280.07:45:43.09#ibcon#about to read 6, iclass 38, count 2 2006.280.07:45:43.09#ibcon#read 6, iclass 38, count 2 2006.280.07:45:43.09#ibcon#end of sib2, iclass 38, count 2 2006.280.07:45:43.09#ibcon#*after write, iclass 38, count 2 2006.280.07:45:43.09#ibcon#*before return 0, iclass 38, count 2 2006.280.07:45:43.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:43.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:45:43.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.07:45:43.09#ibcon#ireg 7 cls_cnt 0 2006.280.07:45:43.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:43.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:43.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:43.21#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:45:43.21#ibcon#first serial, iclass 38, count 0 2006.280.07:45:43.21#ibcon#enter sib2, iclass 38, count 0 2006.280.07:45:43.21#ibcon#flushed, iclass 38, count 0 2006.280.07:45:43.21#ibcon#about to write, iclass 38, count 0 2006.280.07:45:43.21#ibcon#wrote, iclass 38, count 0 2006.280.07:45:43.21#ibcon#about to read 3, iclass 38, count 0 2006.280.07:45:43.23#ibcon#read 3, iclass 38, count 0 2006.280.07:45:43.23#ibcon#about to read 4, iclass 38, count 0 2006.280.07:45:43.23#ibcon#read 4, iclass 38, count 0 2006.280.07:45:43.23#ibcon#about to read 5, iclass 38, count 0 2006.280.07:45:43.23#ibcon#read 5, iclass 38, count 0 2006.280.07:45:43.23#ibcon#about to read 6, iclass 38, count 0 2006.280.07:45:43.23#ibcon#read 6, iclass 38, count 0 2006.280.07:45:43.23#ibcon#end of sib2, iclass 38, count 0 2006.280.07:45:43.23#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:45:43.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:45:43.23#ibcon#[27=USB\r\n] 2006.280.07:45:43.23#ibcon#*before write, iclass 38, count 0 2006.280.07:45:43.23#ibcon#enter sib2, iclass 38, count 0 2006.280.07:45:43.23#ibcon#flushed, iclass 38, count 0 2006.280.07:45:43.23#ibcon#about to write, iclass 38, count 0 2006.280.07:45:43.23#ibcon#wrote, iclass 38, count 0 2006.280.07:45:43.23#ibcon#about to read 3, iclass 38, count 0 2006.280.07:45:43.26#ibcon#read 3, iclass 38, count 0 2006.280.07:45:43.26#ibcon#about to read 4, iclass 38, count 0 2006.280.07:45:43.26#ibcon#read 4, iclass 38, count 0 2006.280.07:45:43.26#ibcon#about to read 5, iclass 38, count 0 2006.280.07:45:43.26#ibcon#read 5, iclass 38, count 0 2006.280.07:45:43.26#ibcon#about to read 6, iclass 38, count 0 2006.280.07:45:43.26#ibcon#read 6, iclass 38, count 0 2006.280.07:45:43.26#ibcon#end of sib2, iclass 38, count 0 2006.280.07:45:43.26#ibcon#*after write, iclass 38, count 0 2006.280.07:45:43.26#ibcon#*before return 0, iclass 38, count 0 2006.280.07:45:43.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:43.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:45:43.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:45:43.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:45:43.26$vc4f8/vabw=wide 2006.280.07:45:43.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:45:43.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:45:43.26#ibcon#ireg 8 cls_cnt 0 2006.280.07:45:43.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:43.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:43.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:43.26#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:45:43.26#ibcon#first serial, iclass 40, count 0 2006.280.07:45:43.26#ibcon#enter sib2, iclass 40, count 0 2006.280.07:45:43.26#ibcon#flushed, iclass 40, count 0 2006.280.07:45:43.26#ibcon#about to write, iclass 40, count 0 2006.280.07:45:43.26#ibcon#wrote, iclass 40, count 0 2006.280.07:45:43.26#ibcon#about to read 3, iclass 40, count 0 2006.280.07:45:43.28#ibcon#read 3, iclass 40, count 0 2006.280.07:45:43.30#ibcon#about to read 4, iclass 40, count 0 2006.280.07:45:43.30#ibcon#read 4, iclass 40, count 0 2006.280.07:45:43.30#ibcon#about to read 5, iclass 40, count 0 2006.280.07:45:43.30#ibcon#read 5, iclass 40, count 0 2006.280.07:45:43.30#ibcon#about to read 6, iclass 40, count 0 2006.280.07:45:43.30#ibcon#read 6, iclass 40, count 0 2006.280.07:45:43.30#ibcon#end of sib2, iclass 40, count 0 2006.280.07:45:43.30#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:45:43.30#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:45:43.30#ibcon#[25=BW32\r\n] 2006.280.07:45:43.30#ibcon#*before write, iclass 40, count 0 2006.280.07:45:43.30#ibcon#enter sib2, iclass 40, count 0 2006.280.07:45:43.30#ibcon#flushed, iclass 40, count 0 2006.280.07:45:43.30#ibcon#about to write, iclass 40, count 0 2006.280.07:45:43.30#ibcon#wrote, iclass 40, count 0 2006.280.07:45:43.30#ibcon#about to read 3, iclass 40, count 0 2006.280.07:45:43.32#ibcon#read 3, iclass 40, count 0 2006.280.07:45:43.32#ibcon#about to read 4, iclass 40, count 0 2006.280.07:45:43.32#ibcon#read 4, iclass 40, count 0 2006.280.07:45:43.32#ibcon#about to read 5, iclass 40, count 0 2006.280.07:45:43.32#ibcon#read 5, iclass 40, count 0 2006.280.07:45:43.32#ibcon#about to read 6, iclass 40, count 0 2006.280.07:45:43.32#ibcon#read 6, iclass 40, count 0 2006.280.07:45:43.32#ibcon#end of sib2, iclass 40, count 0 2006.280.07:45:43.32#ibcon#*after write, iclass 40, count 0 2006.280.07:45:43.32#ibcon#*before return 0, iclass 40, count 0 2006.280.07:45:43.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:43.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:45:43.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:45:43.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:45:43.32$vc4f8/vbbw=wide 2006.280.07:45:43.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:45:43.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:45:43.32#ibcon#ireg 8 cls_cnt 0 2006.280.07:45:43.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:45:43.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:45:43.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:45:43.38#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:45:43.38#ibcon#first serial, iclass 4, count 0 2006.280.07:45:43.38#ibcon#enter sib2, iclass 4, count 0 2006.280.07:45:43.38#ibcon#flushed, iclass 4, count 0 2006.280.07:45:43.38#ibcon#about to write, iclass 4, count 0 2006.280.07:45:43.38#ibcon#wrote, iclass 4, count 0 2006.280.07:45:43.38#ibcon#about to read 3, iclass 4, count 0 2006.280.07:45:43.40#ibcon#read 3, iclass 4, count 0 2006.280.07:45:43.40#ibcon#about to read 4, iclass 4, count 0 2006.280.07:45:43.40#ibcon#read 4, iclass 4, count 0 2006.280.07:45:43.40#ibcon#about to read 5, iclass 4, count 0 2006.280.07:45:43.40#ibcon#read 5, iclass 4, count 0 2006.280.07:45:43.40#ibcon#about to read 6, iclass 4, count 0 2006.280.07:45:43.40#ibcon#read 6, iclass 4, count 0 2006.280.07:45:43.40#ibcon#end of sib2, iclass 4, count 0 2006.280.07:45:43.40#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:45:43.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:45:43.40#ibcon#[27=BW32\r\n] 2006.280.07:45:43.40#ibcon#*before write, iclass 4, count 0 2006.280.07:45:43.40#ibcon#enter sib2, iclass 4, count 0 2006.280.07:45:43.40#ibcon#flushed, iclass 4, count 0 2006.280.07:45:43.40#ibcon#about to write, iclass 4, count 0 2006.280.07:45:43.40#ibcon#wrote, iclass 4, count 0 2006.280.07:45:43.40#ibcon#about to read 3, iclass 4, count 0 2006.280.07:45:43.43#ibcon#read 3, iclass 4, count 0 2006.280.07:45:43.43#ibcon#about to read 4, iclass 4, count 0 2006.280.07:45:43.43#ibcon#read 4, iclass 4, count 0 2006.280.07:45:43.43#ibcon#about to read 5, iclass 4, count 0 2006.280.07:45:43.43#ibcon#read 5, iclass 4, count 0 2006.280.07:45:43.43#ibcon#about to read 6, iclass 4, count 0 2006.280.07:45:43.43#ibcon#read 6, iclass 4, count 0 2006.280.07:45:43.43#ibcon#end of sib2, iclass 4, count 0 2006.280.07:45:43.43#ibcon#*after write, iclass 4, count 0 2006.280.07:45:43.43#ibcon#*before return 0, iclass 4, count 0 2006.280.07:45:43.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:45:43.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:45:43.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:45:43.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:45:43.43$4f8m12a/ifd4f 2006.280.07:45:43.43$ifd4f/lo= 2006.280.07:45:43.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:45:43.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:45:43.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:45:43.43$ifd4f/patch= 2006.280.07:45:43.44$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:45:43.44$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:45:43.44$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:45:43.44$4f8m12a/"form=m,16.000,1:2 2006.280.07:45:43.44$4f8m12a/"tpicd 2006.280.07:45:43.44$4f8m12a/echo=off 2006.280.07:45:43.44$4f8m12a/xlog=off 2006.280.07:45:43.44:!2006.280.07:46:10 2006.280.07:45:52.14#trakl#Source acquired 2006.280.07:45:52.14#flagr#flagr/antenna,acquired 2006.280.07:46:10.01:preob 2006.280.07:46:11.14/onsource/TRACKING 2006.280.07:46:11.14:!2006.280.07:46:20 2006.280.07:46:20.00:data_valid=on 2006.280.07:46:20.00:midob 2006.280.07:46:20.14/onsource/TRACKING 2006.280.07:46:20.14/wx/21.39,986.9,59 2006.280.07:46:20.31/cable/+6.4831E-03 2006.280.07:46:21.40/va/01,07,usb,yes,32,34 2006.280.07:46:21.40/va/02,06,usb,yes,30,31 2006.280.07:46:21.40/va/03,06,usb,yes,28,28 2006.280.07:46:21.40/va/04,06,usb,yes,31,34 2006.280.07:46:21.40/va/05,07,usb,yes,29,30 2006.280.07:46:21.40/va/06,06,usb,yes,28,27 2006.280.07:46:21.40/va/07,06,usb,yes,28,28 2006.280.07:46:21.40/va/08,06,usb,yes,30,30 2006.280.07:46:21.63/valo/01,532.99,yes,locked 2006.280.07:46:21.63/valo/02,572.99,yes,locked 2006.280.07:46:21.63/valo/03,672.99,yes,locked 2006.280.07:46:21.63/valo/04,832.99,yes,locked 2006.280.07:46:21.63/valo/05,652.99,yes,locked 2006.280.07:46:21.63/valo/06,772.99,yes,locked 2006.280.07:46:21.63/valo/07,832.99,yes,locked 2006.280.07:46:21.63/valo/08,852.99,yes,locked 2006.280.07:46:22.72/vb/01,04,usb,yes,30,29 2006.280.07:46:22.72/vb/02,05,usb,yes,28,29 2006.280.07:46:22.72/vb/03,04,usb,yes,28,32 2006.280.07:46:22.72/vb/04,04,usb,yes,29,29 2006.280.07:46:22.72/vb/05,04,usb,yes,27,31 2006.280.07:46:22.72/vb/06,04,usb,yes,28,31 2006.280.07:46:22.72/vb/07,04,usb,yes,30,30 2006.280.07:46:22.72/vb/08,04,usb,yes,28,31 2006.280.07:46:22.95/vblo/01,632.99,yes,locked 2006.280.07:46:22.95/vblo/02,640.99,yes,locked 2006.280.07:46:22.95/vblo/03,656.99,yes,locked 2006.280.07:46:22.95/vblo/04,712.99,yes,locked 2006.280.07:46:22.95/vblo/05,744.99,yes,locked 2006.280.07:46:22.95/vblo/06,752.99,yes,locked 2006.280.07:46:22.95/vblo/07,734.99,yes,locked 2006.280.07:46:22.95/vblo/08,744.99,yes,locked 2006.280.07:46:23.10/vabw/8 2006.280.07:46:23.25/vbbw/8 2006.280.07:46:23.41/xfe/off,on,12.2 2006.280.07:46:23.78/ifatt/23,28,28,28 2006.280.07:46:24.07/fmout-gps/S +3.12E-07 2006.280.07:46:24.10:!2006.280.07:47:20 2006.280.07:47:20.01:data_valid=off 2006.280.07:47:20.02:postob 2006.280.07:47:20.07/cable/+6.4835E-03 2006.280.07:47:20.08/wx/21.35,986.9,59 2006.280.07:47:21.07/fmout-gps/S +3.12E-07 2006.280.07:47:21.08:scan_name=280-0748,k06280,60 2006.280.07:47:21.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.280.07:47:21.14#flagr#flagr/antenna,new-source 2006.280.07:47:22.14:checkk5 2006.280.07:47:22.55/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:47:22.94/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:47:23.32/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:47:23.81/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:47:24.18/chk_obsdata//k5ts1/T2800746??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:47:24.65/chk_obsdata//k5ts2/T2800746??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:47:25.02/chk_obsdata//k5ts3/T2800746??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:47:25.39/chk_obsdata//k5ts4/T2800746??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:47:26.14/k5log//k5ts1_log_newline 2006.280.07:47:26.96/k5log//k5ts2_log_newline 2006.280.07:47:27.75/k5log//k5ts3_log_newline 2006.280.07:47:28.55/k5log//k5ts4_log_newline 2006.280.07:47:28.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:47:28.57:4f8m12a=1 2006.280.07:47:28.57$4f8m12a/echo=on 2006.280.07:47:28.57$4f8m12a/pcalon 2006.280.07:47:28.57$pcalon/"no phase cal control is implemented here 2006.280.07:47:28.57$4f8m12a/"tpicd=stop 2006.280.07:47:28.57$4f8m12a/vc4f8 2006.280.07:47:28.57$vc4f8/valo=1,532.99 2006.280.07:47:28.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:47:28.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:47:28.58#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:28.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:28.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:28.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:28.58#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:47:28.58#ibcon#first serial, iclass 13, count 0 2006.280.07:47:28.58#ibcon#enter sib2, iclass 13, count 0 2006.280.07:47:28.58#ibcon#flushed, iclass 13, count 0 2006.280.07:47:28.58#ibcon#about to write, iclass 13, count 0 2006.280.07:47:28.58#ibcon#wrote, iclass 13, count 0 2006.280.07:47:28.58#ibcon#about to read 3, iclass 13, count 0 2006.280.07:47:28.59#ibcon#read 3, iclass 13, count 0 2006.280.07:47:28.59#ibcon#about to read 4, iclass 13, count 0 2006.280.07:47:28.59#ibcon#read 4, iclass 13, count 0 2006.280.07:47:28.59#ibcon#about to read 5, iclass 13, count 0 2006.280.07:47:28.59#ibcon#read 5, iclass 13, count 0 2006.280.07:47:28.59#ibcon#about to read 6, iclass 13, count 0 2006.280.07:47:28.59#ibcon#read 6, iclass 13, count 0 2006.280.07:47:28.59#ibcon#end of sib2, iclass 13, count 0 2006.280.07:47:28.59#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:47:28.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:47:28.59#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:47:28.59#ibcon#*before write, iclass 13, count 0 2006.280.07:47:28.59#ibcon#enter sib2, iclass 13, count 0 2006.280.07:47:28.59#ibcon#flushed, iclass 13, count 0 2006.280.07:47:28.59#ibcon#about to write, iclass 13, count 0 2006.280.07:47:28.59#ibcon#wrote, iclass 13, count 0 2006.280.07:47:28.59#ibcon#about to read 3, iclass 13, count 0 2006.280.07:47:28.65#ibcon#read 3, iclass 13, count 0 2006.280.07:47:28.65#ibcon#about to read 4, iclass 13, count 0 2006.280.07:47:28.65#ibcon#read 4, iclass 13, count 0 2006.280.07:47:28.65#ibcon#about to read 5, iclass 13, count 0 2006.280.07:47:28.65#ibcon#read 5, iclass 13, count 0 2006.280.07:47:28.65#ibcon#about to read 6, iclass 13, count 0 2006.280.07:47:28.65#ibcon#read 6, iclass 13, count 0 2006.280.07:47:28.65#ibcon#end of sib2, iclass 13, count 0 2006.280.07:47:28.65#ibcon#*after write, iclass 13, count 0 2006.280.07:47:28.65#ibcon#*before return 0, iclass 13, count 0 2006.280.07:47:28.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:28.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:28.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:47:28.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:47:28.65$vc4f8/va=1,7 2006.280.07:47:28.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:47:28.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:47:28.65#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:28.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:28.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:28.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:28.65#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:47:28.65#ibcon#first serial, iclass 15, count 2 2006.280.07:47:28.65#ibcon#enter sib2, iclass 15, count 2 2006.280.07:47:28.65#ibcon#flushed, iclass 15, count 2 2006.280.07:47:28.65#ibcon#about to write, iclass 15, count 2 2006.280.07:47:28.65#ibcon#wrote, iclass 15, count 2 2006.280.07:47:28.65#ibcon#about to read 3, iclass 15, count 2 2006.280.07:47:28.66#ibcon#read 3, iclass 15, count 2 2006.280.07:47:28.66#ibcon#about to read 4, iclass 15, count 2 2006.280.07:47:28.66#ibcon#read 4, iclass 15, count 2 2006.280.07:47:28.66#ibcon#about to read 5, iclass 15, count 2 2006.280.07:47:28.66#ibcon#read 5, iclass 15, count 2 2006.280.07:47:28.66#ibcon#about to read 6, iclass 15, count 2 2006.280.07:47:28.66#ibcon#read 6, iclass 15, count 2 2006.280.07:47:28.66#ibcon#end of sib2, iclass 15, count 2 2006.280.07:47:28.66#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:47:28.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:47:28.66#ibcon#[25=AT01-07\r\n] 2006.280.07:47:28.66#ibcon#*before write, iclass 15, count 2 2006.280.07:47:28.66#ibcon#enter sib2, iclass 15, count 2 2006.280.07:47:28.66#ibcon#flushed, iclass 15, count 2 2006.280.07:47:28.66#ibcon#about to write, iclass 15, count 2 2006.280.07:47:28.66#ibcon#wrote, iclass 15, count 2 2006.280.07:47:28.66#ibcon#about to read 3, iclass 15, count 2 2006.280.07:47:28.69#ibcon#read 3, iclass 15, count 2 2006.280.07:47:28.69#ibcon#about to read 4, iclass 15, count 2 2006.280.07:47:28.69#ibcon#read 4, iclass 15, count 2 2006.280.07:47:28.69#ibcon#about to read 5, iclass 15, count 2 2006.280.07:47:28.69#ibcon#read 5, iclass 15, count 2 2006.280.07:47:28.69#ibcon#about to read 6, iclass 15, count 2 2006.280.07:47:28.69#ibcon#read 6, iclass 15, count 2 2006.280.07:47:28.69#ibcon#end of sib2, iclass 15, count 2 2006.280.07:47:28.69#ibcon#*after write, iclass 15, count 2 2006.280.07:47:28.69#ibcon#*before return 0, iclass 15, count 2 2006.280.07:47:28.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:28.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:28.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:47:28.69#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:28.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:28.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:28.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:28.82#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:47:28.82#ibcon#first serial, iclass 15, count 0 2006.280.07:47:28.82#ibcon#enter sib2, iclass 15, count 0 2006.280.07:47:28.82#ibcon#flushed, iclass 15, count 0 2006.280.07:47:28.82#ibcon#about to write, iclass 15, count 0 2006.280.07:47:28.82#ibcon#wrote, iclass 15, count 0 2006.280.07:47:28.82#ibcon#about to read 3, iclass 15, count 0 2006.280.07:47:28.83#ibcon#read 3, iclass 15, count 0 2006.280.07:47:28.83#ibcon#about to read 4, iclass 15, count 0 2006.280.07:47:28.83#ibcon#read 4, iclass 15, count 0 2006.280.07:47:28.83#ibcon#about to read 5, iclass 15, count 0 2006.280.07:47:28.83#ibcon#read 5, iclass 15, count 0 2006.280.07:47:28.83#ibcon#about to read 6, iclass 15, count 0 2006.280.07:47:28.83#ibcon#read 6, iclass 15, count 0 2006.280.07:47:28.83#ibcon#end of sib2, iclass 15, count 0 2006.280.07:47:28.83#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:47:28.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:47:28.83#ibcon#[25=USB\r\n] 2006.280.07:47:28.83#ibcon#*before write, iclass 15, count 0 2006.280.07:47:28.83#ibcon#enter sib2, iclass 15, count 0 2006.280.07:47:28.83#ibcon#flushed, iclass 15, count 0 2006.280.07:47:28.83#ibcon#about to write, iclass 15, count 0 2006.280.07:47:28.83#ibcon#wrote, iclass 15, count 0 2006.280.07:47:28.83#ibcon#about to read 3, iclass 15, count 0 2006.280.07:47:28.86#ibcon#read 3, iclass 15, count 0 2006.280.07:47:28.86#ibcon#about to read 4, iclass 15, count 0 2006.280.07:47:28.86#ibcon#read 4, iclass 15, count 0 2006.280.07:47:28.86#ibcon#about to read 5, iclass 15, count 0 2006.280.07:47:28.86#ibcon#read 5, iclass 15, count 0 2006.280.07:47:28.86#ibcon#about to read 6, iclass 15, count 0 2006.280.07:47:28.86#ibcon#read 6, iclass 15, count 0 2006.280.07:47:28.86#ibcon#end of sib2, iclass 15, count 0 2006.280.07:47:28.86#ibcon#*after write, iclass 15, count 0 2006.280.07:47:28.86#ibcon#*before return 0, iclass 15, count 0 2006.280.07:47:28.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:28.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:28.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:47:28.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:47:28.86$vc4f8/valo=2,572.99 2006.280.07:47:28.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:47:28.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:47:28.86#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:28.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:28.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:28.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:28.86#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:47:28.86#ibcon#first serial, iclass 17, count 0 2006.280.07:47:28.86#ibcon#enter sib2, iclass 17, count 0 2006.280.07:47:28.86#ibcon#flushed, iclass 17, count 0 2006.280.07:47:28.86#ibcon#about to write, iclass 17, count 0 2006.280.07:47:28.86#ibcon#wrote, iclass 17, count 0 2006.280.07:47:28.86#ibcon#about to read 3, iclass 17, count 0 2006.280.07:47:28.88#ibcon#read 3, iclass 17, count 0 2006.280.07:47:28.88#ibcon#about to read 4, iclass 17, count 0 2006.280.07:47:28.88#ibcon#read 4, iclass 17, count 0 2006.280.07:47:28.88#ibcon#about to read 5, iclass 17, count 0 2006.280.07:47:28.88#ibcon#read 5, iclass 17, count 0 2006.280.07:47:28.88#ibcon#about to read 6, iclass 17, count 0 2006.280.07:47:28.88#ibcon#read 6, iclass 17, count 0 2006.280.07:47:28.88#ibcon#end of sib2, iclass 17, count 0 2006.280.07:47:28.88#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:47:28.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:47:28.88#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:47:28.88#ibcon#*before write, iclass 17, count 0 2006.280.07:47:28.88#ibcon#enter sib2, iclass 17, count 0 2006.280.07:47:28.88#ibcon#flushed, iclass 17, count 0 2006.280.07:47:28.88#ibcon#about to write, iclass 17, count 0 2006.280.07:47:28.88#ibcon#wrote, iclass 17, count 0 2006.280.07:47:28.88#ibcon#about to read 3, iclass 17, count 0 2006.280.07:47:28.92#ibcon#read 3, iclass 17, count 0 2006.280.07:47:28.92#ibcon#about to read 4, iclass 17, count 0 2006.280.07:47:28.92#ibcon#read 4, iclass 17, count 0 2006.280.07:47:28.92#ibcon#about to read 5, iclass 17, count 0 2006.280.07:47:28.92#ibcon#read 5, iclass 17, count 0 2006.280.07:47:28.92#ibcon#about to read 6, iclass 17, count 0 2006.280.07:47:28.92#ibcon#read 6, iclass 17, count 0 2006.280.07:47:28.92#ibcon#end of sib2, iclass 17, count 0 2006.280.07:47:28.92#ibcon#*after write, iclass 17, count 0 2006.280.07:47:28.92#ibcon#*before return 0, iclass 17, count 0 2006.280.07:47:28.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:28.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:28.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:47:28.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:47:28.92$vc4f8/va=2,6 2006.280.07:47:28.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:47:28.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:47:28.92#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:28.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:28.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:28.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:28.98#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:47:28.98#ibcon#first serial, iclass 19, count 2 2006.280.07:47:28.98#ibcon#enter sib2, iclass 19, count 2 2006.280.07:47:28.98#ibcon#flushed, iclass 19, count 2 2006.280.07:47:28.98#ibcon#about to write, iclass 19, count 2 2006.280.07:47:28.98#ibcon#wrote, iclass 19, count 2 2006.280.07:47:28.98#ibcon#about to read 3, iclass 19, count 2 2006.280.07:47:29.00#ibcon#read 3, iclass 19, count 2 2006.280.07:47:29.00#ibcon#about to read 4, iclass 19, count 2 2006.280.07:47:29.00#ibcon#read 4, iclass 19, count 2 2006.280.07:47:29.00#ibcon#about to read 5, iclass 19, count 2 2006.280.07:47:29.00#ibcon#read 5, iclass 19, count 2 2006.280.07:47:29.00#ibcon#about to read 6, iclass 19, count 2 2006.280.07:47:29.00#ibcon#read 6, iclass 19, count 2 2006.280.07:47:29.00#ibcon#end of sib2, iclass 19, count 2 2006.280.07:47:29.00#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:47:29.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:47:29.00#ibcon#[25=AT02-06\r\n] 2006.280.07:47:29.00#ibcon#*before write, iclass 19, count 2 2006.280.07:47:29.00#ibcon#enter sib2, iclass 19, count 2 2006.280.07:47:29.00#ibcon#flushed, iclass 19, count 2 2006.280.07:47:29.00#ibcon#about to write, iclass 19, count 2 2006.280.07:47:29.00#ibcon#wrote, iclass 19, count 2 2006.280.07:47:29.00#ibcon#about to read 3, iclass 19, count 2 2006.280.07:47:29.03#ibcon#read 3, iclass 19, count 2 2006.280.07:47:29.03#ibcon#about to read 4, iclass 19, count 2 2006.280.07:47:29.03#ibcon#read 4, iclass 19, count 2 2006.280.07:47:29.03#ibcon#about to read 5, iclass 19, count 2 2006.280.07:47:29.03#ibcon#read 5, iclass 19, count 2 2006.280.07:47:29.03#ibcon#about to read 6, iclass 19, count 2 2006.280.07:47:29.03#ibcon#read 6, iclass 19, count 2 2006.280.07:47:29.03#ibcon#end of sib2, iclass 19, count 2 2006.280.07:47:29.03#ibcon#*after write, iclass 19, count 2 2006.280.07:47:29.03#ibcon#*before return 0, iclass 19, count 2 2006.280.07:47:29.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:29.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:29.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:47:29.03#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:29.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:29.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:29.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:29.15#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:47:29.15#ibcon#first serial, iclass 19, count 0 2006.280.07:47:29.15#ibcon#enter sib2, iclass 19, count 0 2006.280.07:47:29.15#ibcon#flushed, iclass 19, count 0 2006.280.07:47:29.15#ibcon#about to write, iclass 19, count 0 2006.280.07:47:29.15#ibcon#wrote, iclass 19, count 0 2006.280.07:47:29.15#ibcon#about to read 3, iclass 19, count 0 2006.280.07:47:29.17#ibcon#read 3, iclass 19, count 0 2006.280.07:47:29.17#ibcon#about to read 4, iclass 19, count 0 2006.280.07:47:29.17#ibcon#read 4, iclass 19, count 0 2006.280.07:47:29.17#ibcon#about to read 5, iclass 19, count 0 2006.280.07:47:29.17#ibcon#read 5, iclass 19, count 0 2006.280.07:47:29.17#ibcon#about to read 6, iclass 19, count 0 2006.280.07:47:29.17#ibcon#read 6, iclass 19, count 0 2006.280.07:47:29.17#ibcon#end of sib2, iclass 19, count 0 2006.280.07:47:29.17#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:47:29.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:47:29.17#ibcon#[25=USB\r\n] 2006.280.07:47:29.17#ibcon#*before write, iclass 19, count 0 2006.280.07:47:29.17#ibcon#enter sib2, iclass 19, count 0 2006.280.07:47:29.17#ibcon#flushed, iclass 19, count 0 2006.280.07:47:29.17#ibcon#about to write, iclass 19, count 0 2006.280.07:47:29.17#ibcon#wrote, iclass 19, count 0 2006.280.07:47:29.17#ibcon#about to read 3, iclass 19, count 0 2006.280.07:47:29.20#ibcon#read 3, iclass 19, count 0 2006.280.07:47:29.20#ibcon#about to read 4, iclass 19, count 0 2006.280.07:47:29.20#ibcon#read 4, iclass 19, count 0 2006.280.07:47:29.20#ibcon#about to read 5, iclass 19, count 0 2006.280.07:47:29.20#ibcon#read 5, iclass 19, count 0 2006.280.07:47:29.20#ibcon#about to read 6, iclass 19, count 0 2006.280.07:47:29.20#ibcon#read 6, iclass 19, count 0 2006.280.07:47:29.20#ibcon#end of sib2, iclass 19, count 0 2006.280.07:47:29.20#ibcon#*after write, iclass 19, count 0 2006.280.07:47:29.20#ibcon#*before return 0, iclass 19, count 0 2006.280.07:47:29.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:29.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:29.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:47:29.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:47:29.20$vc4f8/valo=3,672.99 2006.280.07:47:29.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:47:29.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:47:29.20#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:29.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:29.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:29.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:29.20#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:47:29.20#ibcon#first serial, iclass 21, count 0 2006.280.07:47:29.20#ibcon#enter sib2, iclass 21, count 0 2006.280.07:47:29.20#ibcon#flushed, iclass 21, count 0 2006.280.07:47:29.20#ibcon#about to write, iclass 21, count 0 2006.280.07:47:29.20#ibcon#wrote, iclass 21, count 0 2006.280.07:47:29.20#ibcon#about to read 3, iclass 21, count 0 2006.280.07:47:29.22#ibcon#read 3, iclass 21, count 0 2006.280.07:47:29.22#ibcon#about to read 4, iclass 21, count 0 2006.280.07:47:29.22#ibcon#read 4, iclass 21, count 0 2006.280.07:47:29.22#ibcon#about to read 5, iclass 21, count 0 2006.280.07:47:29.22#ibcon#read 5, iclass 21, count 0 2006.280.07:47:29.22#ibcon#about to read 6, iclass 21, count 0 2006.280.07:47:29.22#ibcon#read 6, iclass 21, count 0 2006.280.07:47:29.22#ibcon#end of sib2, iclass 21, count 0 2006.280.07:47:29.22#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:47:29.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:47:29.22#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:47:29.22#ibcon#*before write, iclass 21, count 0 2006.280.07:47:29.22#ibcon#enter sib2, iclass 21, count 0 2006.280.07:47:29.22#ibcon#flushed, iclass 21, count 0 2006.280.07:47:29.22#ibcon#about to write, iclass 21, count 0 2006.280.07:47:29.22#ibcon#wrote, iclass 21, count 0 2006.280.07:47:29.22#ibcon#about to read 3, iclass 21, count 0 2006.280.07:47:29.26#ibcon#read 3, iclass 21, count 0 2006.280.07:47:29.26#ibcon#about to read 4, iclass 21, count 0 2006.280.07:47:29.26#ibcon#read 4, iclass 21, count 0 2006.280.07:47:29.26#ibcon#about to read 5, iclass 21, count 0 2006.280.07:47:29.26#ibcon#read 5, iclass 21, count 0 2006.280.07:47:29.26#ibcon#about to read 6, iclass 21, count 0 2006.280.07:47:29.26#ibcon#read 6, iclass 21, count 0 2006.280.07:47:29.26#ibcon#end of sib2, iclass 21, count 0 2006.280.07:47:29.26#ibcon#*after write, iclass 21, count 0 2006.280.07:47:29.26#ibcon#*before return 0, iclass 21, count 0 2006.280.07:47:29.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:29.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:29.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:47:29.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:47:29.26$vc4f8/va=3,6 2006.280.07:47:29.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:47:29.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:47:29.28#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:29.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:29.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:29.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:29.32#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:47:29.33#ibcon#first serial, iclass 23, count 2 2006.280.07:47:29.33#ibcon#enter sib2, iclass 23, count 2 2006.280.07:47:29.33#ibcon#flushed, iclass 23, count 2 2006.280.07:47:29.33#ibcon#about to write, iclass 23, count 2 2006.280.07:47:29.33#ibcon#wrote, iclass 23, count 2 2006.280.07:47:29.33#ibcon#about to read 3, iclass 23, count 2 2006.280.07:47:29.35#ibcon#read 3, iclass 23, count 2 2006.280.07:47:29.35#ibcon#about to read 4, iclass 23, count 2 2006.280.07:47:29.35#ibcon#read 4, iclass 23, count 2 2006.280.07:47:29.35#ibcon#about to read 5, iclass 23, count 2 2006.280.07:47:29.35#ibcon#read 5, iclass 23, count 2 2006.280.07:47:29.35#ibcon#about to read 6, iclass 23, count 2 2006.280.07:47:29.35#ibcon#read 6, iclass 23, count 2 2006.280.07:47:29.35#ibcon#end of sib2, iclass 23, count 2 2006.280.07:47:29.35#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:47:29.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:47:29.35#ibcon#[25=AT03-06\r\n] 2006.280.07:47:29.35#ibcon#*before write, iclass 23, count 2 2006.280.07:47:29.35#ibcon#enter sib2, iclass 23, count 2 2006.280.07:47:29.35#ibcon#flushed, iclass 23, count 2 2006.280.07:47:29.35#ibcon#about to write, iclass 23, count 2 2006.280.07:47:29.35#ibcon#wrote, iclass 23, count 2 2006.280.07:47:29.35#ibcon#about to read 3, iclass 23, count 2 2006.280.07:47:29.37#ibcon#read 3, iclass 23, count 2 2006.280.07:47:29.37#ibcon#about to read 4, iclass 23, count 2 2006.280.07:47:29.37#ibcon#read 4, iclass 23, count 2 2006.280.07:47:29.37#ibcon#about to read 5, iclass 23, count 2 2006.280.07:47:29.37#ibcon#read 5, iclass 23, count 2 2006.280.07:47:29.37#ibcon#about to read 6, iclass 23, count 2 2006.280.07:47:29.37#ibcon#read 6, iclass 23, count 2 2006.280.07:47:29.37#ibcon#end of sib2, iclass 23, count 2 2006.280.07:47:29.37#ibcon#*after write, iclass 23, count 2 2006.280.07:47:29.37#ibcon#*before return 0, iclass 23, count 2 2006.280.07:47:29.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:29.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:29.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:47:29.37#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:29.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:29.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:29.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:29.49#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:47:29.49#ibcon#first serial, iclass 23, count 0 2006.280.07:47:29.49#ibcon#enter sib2, iclass 23, count 0 2006.280.07:47:29.49#ibcon#flushed, iclass 23, count 0 2006.280.07:47:29.49#ibcon#about to write, iclass 23, count 0 2006.280.07:47:29.49#ibcon#wrote, iclass 23, count 0 2006.280.07:47:29.49#ibcon#about to read 3, iclass 23, count 0 2006.280.07:47:29.51#ibcon#read 3, iclass 23, count 0 2006.280.07:47:29.51#ibcon#about to read 4, iclass 23, count 0 2006.280.07:47:29.51#ibcon#read 4, iclass 23, count 0 2006.280.07:47:29.51#ibcon#about to read 5, iclass 23, count 0 2006.280.07:47:29.51#ibcon#read 5, iclass 23, count 0 2006.280.07:47:29.51#ibcon#about to read 6, iclass 23, count 0 2006.280.07:47:29.51#ibcon#read 6, iclass 23, count 0 2006.280.07:47:29.51#ibcon#end of sib2, iclass 23, count 0 2006.280.07:47:29.51#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:47:29.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:47:29.51#ibcon#[25=USB\r\n] 2006.280.07:47:29.51#ibcon#*before write, iclass 23, count 0 2006.280.07:47:29.51#ibcon#enter sib2, iclass 23, count 0 2006.280.07:47:29.51#ibcon#flushed, iclass 23, count 0 2006.280.07:47:29.51#ibcon#about to write, iclass 23, count 0 2006.280.07:47:29.51#ibcon#wrote, iclass 23, count 0 2006.280.07:47:29.51#ibcon#about to read 3, iclass 23, count 0 2006.280.07:47:29.55#ibcon#read 3, iclass 23, count 0 2006.280.07:47:29.55#ibcon#about to read 4, iclass 23, count 0 2006.280.07:47:29.55#ibcon#read 4, iclass 23, count 0 2006.280.07:47:29.55#ibcon#about to read 5, iclass 23, count 0 2006.280.07:47:29.55#ibcon#read 5, iclass 23, count 0 2006.280.07:47:29.55#ibcon#about to read 6, iclass 23, count 0 2006.280.07:47:29.55#ibcon#read 6, iclass 23, count 0 2006.280.07:47:29.55#ibcon#end of sib2, iclass 23, count 0 2006.280.07:47:29.55#ibcon#*after write, iclass 23, count 0 2006.280.07:47:29.55#ibcon#*before return 0, iclass 23, count 0 2006.280.07:47:29.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:29.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:29.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:47:29.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:47:29.55$vc4f8/valo=4,832.99 2006.280.07:47:29.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:47:29.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:47:29.55#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:29.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:29.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:29.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:29.55#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:47:29.55#ibcon#first serial, iclass 25, count 0 2006.280.07:47:29.55#ibcon#enter sib2, iclass 25, count 0 2006.280.07:47:29.55#ibcon#flushed, iclass 25, count 0 2006.280.07:47:29.55#ibcon#about to write, iclass 25, count 0 2006.280.07:47:29.55#ibcon#wrote, iclass 25, count 0 2006.280.07:47:29.55#ibcon#about to read 3, iclass 25, count 0 2006.280.07:47:29.57#ibcon#read 3, iclass 25, count 0 2006.280.07:47:29.57#ibcon#about to read 4, iclass 25, count 0 2006.280.07:47:29.57#ibcon#read 4, iclass 25, count 0 2006.280.07:47:29.57#ibcon#about to read 5, iclass 25, count 0 2006.280.07:47:29.57#ibcon#read 5, iclass 25, count 0 2006.280.07:47:29.57#ibcon#about to read 6, iclass 25, count 0 2006.280.07:47:29.57#ibcon#read 6, iclass 25, count 0 2006.280.07:47:29.57#ibcon#end of sib2, iclass 25, count 0 2006.280.07:47:29.57#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:47:29.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:47:29.57#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:47:29.57#ibcon#*before write, iclass 25, count 0 2006.280.07:47:29.59#ibcon#enter sib2, iclass 25, count 0 2006.280.07:47:29.59#ibcon#flushed, iclass 25, count 0 2006.280.07:47:29.59#ibcon#about to write, iclass 25, count 0 2006.280.07:47:29.59#ibcon#wrote, iclass 25, count 0 2006.280.07:47:29.59#ibcon#about to read 3, iclass 25, count 0 2006.280.07:47:29.63#ibcon#read 3, iclass 25, count 0 2006.280.07:47:29.63#ibcon#about to read 4, iclass 25, count 0 2006.280.07:47:29.63#ibcon#read 4, iclass 25, count 0 2006.280.07:47:29.63#ibcon#about to read 5, iclass 25, count 0 2006.280.07:47:29.63#ibcon#read 5, iclass 25, count 0 2006.280.07:47:29.63#ibcon#about to read 6, iclass 25, count 0 2006.280.07:47:29.63#ibcon#read 6, iclass 25, count 0 2006.280.07:47:29.63#ibcon#end of sib2, iclass 25, count 0 2006.280.07:47:29.63#ibcon#*after write, iclass 25, count 0 2006.280.07:47:29.63#ibcon#*before return 0, iclass 25, count 0 2006.280.07:47:29.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:29.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:29.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:47:29.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:47:29.63$vc4f8/va=4,6 2006.280.07:47:29.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:47:29.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:47:29.63#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:29.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:29.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:29.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:29.67#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:47:29.67#ibcon#first serial, iclass 27, count 2 2006.280.07:47:29.67#ibcon#enter sib2, iclass 27, count 2 2006.280.07:47:29.67#ibcon#flushed, iclass 27, count 2 2006.280.07:47:29.67#ibcon#about to write, iclass 27, count 2 2006.280.07:47:29.67#ibcon#wrote, iclass 27, count 2 2006.280.07:47:29.67#ibcon#about to read 3, iclass 27, count 2 2006.280.07:47:29.69#ibcon#read 3, iclass 27, count 2 2006.280.07:47:29.69#ibcon#about to read 4, iclass 27, count 2 2006.280.07:47:29.69#ibcon#read 4, iclass 27, count 2 2006.280.07:47:29.69#ibcon#about to read 5, iclass 27, count 2 2006.280.07:47:29.69#ibcon#read 5, iclass 27, count 2 2006.280.07:47:29.69#ibcon#about to read 6, iclass 27, count 2 2006.280.07:47:29.69#ibcon#read 6, iclass 27, count 2 2006.280.07:47:29.69#ibcon#end of sib2, iclass 27, count 2 2006.280.07:47:29.69#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:47:29.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:47:29.69#ibcon#[25=AT04-06\r\n] 2006.280.07:47:29.69#ibcon#*before write, iclass 27, count 2 2006.280.07:47:29.69#ibcon#enter sib2, iclass 27, count 2 2006.280.07:47:29.69#ibcon#flushed, iclass 27, count 2 2006.280.07:47:29.69#ibcon#about to write, iclass 27, count 2 2006.280.07:47:29.69#ibcon#wrote, iclass 27, count 2 2006.280.07:47:29.69#ibcon#about to read 3, iclass 27, count 2 2006.280.07:47:29.72#ibcon#read 3, iclass 27, count 2 2006.280.07:47:29.72#ibcon#about to read 4, iclass 27, count 2 2006.280.07:47:29.72#ibcon#read 4, iclass 27, count 2 2006.280.07:47:29.72#ibcon#about to read 5, iclass 27, count 2 2006.280.07:47:29.72#ibcon#read 5, iclass 27, count 2 2006.280.07:47:29.72#ibcon#about to read 6, iclass 27, count 2 2006.280.07:47:29.72#ibcon#read 6, iclass 27, count 2 2006.280.07:47:29.72#ibcon#end of sib2, iclass 27, count 2 2006.280.07:47:29.72#ibcon#*after write, iclass 27, count 2 2006.280.07:47:29.72#ibcon#*before return 0, iclass 27, count 2 2006.280.07:47:29.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:29.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:29.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:47:29.72#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:29.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:29.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:29.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:29.84#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:47:29.84#ibcon#first serial, iclass 27, count 0 2006.280.07:47:29.84#ibcon#enter sib2, iclass 27, count 0 2006.280.07:47:29.84#ibcon#flushed, iclass 27, count 0 2006.280.07:47:29.84#ibcon#about to write, iclass 27, count 0 2006.280.07:47:29.84#ibcon#wrote, iclass 27, count 0 2006.280.07:47:29.84#ibcon#about to read 3, iclass 27, count 0 2006.280.07:47:29.86#ibcon#read 3, iclass 27, count 0 2006.280.07:47:29.86#ibcon#about to read 4, iclass 27, count 0 2006.280.07:47:29.86#ibcon#read 4, iclass 27, count 0 2006.280.07:47:29.86#ibcon#about to read 5, iclass 27, count 0 2006.280.07:47:29.86#ibcon#read 5, iclass 27, count 0 2006.280.07:47:29.86#ibcon#about to read 6, iclass 27, count 0 2006.280.07:47:29.86#ibcon#read 6, iclass 27, count 0 2006.280.07:47:29.86#ibcon#end of sib2, iclass 27, count 0 2006.280.07:47:29.86#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:47:29.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:47:29.86#ibcon#[25=USB\r\n] 2006.280.07:47:29.86#ibcon#*before write, iclass 27, count 0 2006.280.07:47:29.86#ibcon#enter sib2, iclass 27, count 0 2006.280.07:47:29.86#ibcon#flushed, iclass 27, count 0 2006.280.07:47:29.86#ibcon#about to write, iclass 27, count 0 2006.280.07:47:29.86#ibcon#wrote, iclass 27, count 0 2006.280.07:47:29.86#ibcon#about to read 3, iclass 27, count 0 2006.280.07:47:29.89#ibcon#read 3, iclass 27, count 0 2006.280.07:47:29.89#ibcon#about to read 4, iclass 27, count 0 2006.280.07:47:29.89#ibcon#read 4, iclass 27, count 0 2006.280.07:47:29.89#ibcon#about to read 5, iclass 27, count 0 2006.280.07:47:29.89#ibcon#read 5, iclass 27, count 0 2006.280.07:47:29.89#ibcon#about to read 6, iclass 27, count 0 2006.280.07:47:29.89#ibcon#read 6, iclass 27, count 0 2006.280.07:47:29.89#ibcon#end of sib2, iclass 27, count 0 2006.280.07:47:29.89#ibcon#*after write, iclass 27, count 0 2006.280.07:47:29.89#ibcon#*before return 0, iclass 27, count 0 2006.280.07:47:29.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:29.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:29.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:47:29.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:47:29.89$vc4f8/valo=5,652.99 2006.280.07:47:29.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:47:29.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:47:29.89#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:29.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:29.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:29.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:29.89#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:47:29.89#ibcon#first serial, iclass 29, count 0 2006.280.07:47:29.89#ibcon#enter sib2, iclass 29, count 0 2006.280.07:47:29.89#ibcon#flushed, iclass 29, count 0 2006.280.07:47:29.89#ibcon#about to write, iclass 29, count 0 2006.280.07:47:29.89#ibcon#wrote, iclass 29, count 0 2006.280.07:47:29.89#ibcon#about to read 3, iclass 29, count 0 2006.280.07:47:29.91#ibcon#read 3, iclass 29, count 0 2006.280.07:47:29.91#ibcon#about to read 4, iclass 29, count 0 2006.280.07:47:29.91#ibcon#read 4, iclass 29, count 0 2006.280.07:47:29.91#ibcon#about to read 5, iclass 29, count 0 2006.280.07:47:29.91#ibcon#read 5, iclass 29, count 0 2006.280.07:47:29.91#ibcon#about to read 6, iclass 29, count 0 2006.280.07:47:29.91#ibcon#read 6, iclass 29, count 0 2006.280.07:47:29.91#ibcon#end of sib2, iclass 29, count 0 2006.280.07:47:29.91#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:47:29.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:47:29.91#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:47:29.91#ibcon#*before write, iclass 29, count 0 2006.280.07:47:29.91#ibcon#enter sib2, iclass 29, count 0 2006.280.07:47:29.91#ibcon#flushed, iclass 29, count 0 2006.280.07:47:29.91#ibcon#about to write, iclass 29, count 0 2006.280.07:47:29.91#ibcon#wrote, iclass 29, count 0 2006.280.07:47:29.91#ibcon#about to read 3, iclass 29, count 0 2006.280.07:47:29.95#ibcon#read 3, iclass 29, count 0 2006.280.07:47:29.95#ibcon#about to read 4, iclass 29, count 0 2006.280.07:47:29.95#ibcon#read 4, iclass 29, count 0 2006.280.07:47:29.95#ibcon#about to read 5, iclass 29, count 0 2006.280.07:47:29.95#ibcon#read 5, iclass 29, count 0 2006.280.07:47:29.95#ibcon#about to read 6, iclass 29, count 0 2006.280.07:47:29.95#ibcon#read 6, iclass 29, count 0 2006.280.07:47:29.95#ibcon#end of sib2, iclass 29, count 0 2006.280.07:47:29.95#ibcon#*after write, iclass 29, count 0 2006.280.07:47:29.95#ibcon#*before return 0, iclass 29, count 0 2006.280.07:47:29.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:29.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:29.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:47:29.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:47:29.95$vc4f8/va=5,7 2006.280.07:47:29.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:47:29.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:47:29.95#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:29.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:30.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:30.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:30.01#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:47:30.01#ibcon#first serial, iclass 31, count 2 2006.280.07:47:30.01#ibcon#enter sib2, iclass 31, count 2 2006.280.07:47:30.01#ibcon#flushed, iclass 31, count 2 2006.280.07:47:30.01#ibcon#about to write, iclass 31, count 2 2006.280.07:47:30.01#ibcon#wrote, iclass 31, count 2 2006.280.07:47:30.01#ibcon#about to read 3, iclass 31, count 2 2006.280.07:47:30.03#ibcon#read 3, iclass 31, count 2 2006.280.07:47:30.03#ibcon#about to read 4, iclass 31, count 2 2006.280.07:47:30.03#ibcon#read 4, iclass 31, count 2 2006.280.07:47:30.03#ibcon#about to read 5, iclass 31, count 2 2006.280.07:47:30.03#ibcon#read 5, iclass 31, count 2 2006.280.07:47:30.03#ibcon#about to read 6, iclass 31, count 2 2006.280.07:47:30.03#ibcon#read 6, iclass 31, count 2 2006.280.07:47:30.03#ibcon#end of sib2, iclass 31, count 2 2006.280.07:47:30.03#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:47:30.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:47:30.03#ibcon#[25=AT05-07\r\n] 2006.280.07:47:30.03#ibcon#*before write, iclass 31, count 2 2006.280.07:47:30.03#ibcon#enter sib2, iclass 31, count 2 2006.280.07:47:30.03#ibcon#flushed, iclass 31, count 2 2006.280.07:47:30.03#ibcon#about to write, iclass 31, count 2 2006.280.07:47:30.03#ibcon#wrote, iclass 31, count 2 2006.280.07:47:30.03#ibcon#about to read 3, iclass 31, count 2 2006.280.07:47:30.06#ibcon#read 3, iclass 31, count 2 2006.280.07:47:30.06#ibcon#about to read 4, iclass 31, count 2 2006.280.07:47:30.06#ibcon#read 4, iclass 31, count 2 2006.280.07:47:30.06#ibcon#about to read 5, iclass 31, count 2 2006.280.07:47:30.06#ibcon#read 5, iclass 31, count 2 2006.280.07:47:30.06#ibcon#about to read 6, iclass 31, count 2 2006.280.07:47:30.06#ibcon#read 6, iclass 31, count 2 2006.280.07:47:30.06#ibcon#end of sib2, iclass 31, count 2 2006.280.07:47:30.06#ibcon#*after write, iclass 31, count 2 2006.280.07:47:30.06#ibcon#*before return 0, iclass 31, count 2 2006.280.07:47:30.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:30.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:30.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:47:30.06#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:30.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:30.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:30.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:30.18#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:47:30.18#ibcon#first serial, iclass 31, count 0 2006.280.07:47:30.18#ibcon#enter sib2, iclass 31, count 0 2006.280.07:47:30.18#ibcon#flushed, iclass 31, count 0 2006.280.07:47:30.18#ibcon#about to write, iclass 31, count 0 2006.280.07:47:30.18#ibcon#wrote, iclass 31, count 0 2006.280.07:47:30.18#ibcon#about to read 3, iclass 31, count 0 2006.280.07:47:30.20#ibcon#read 3, iclass 31, count 0 2006.280.07:47:30.20#ibcon#about to read 4, iclass 31, count 0 2006.280.07:47:30.20#ibcon#read 4, iclass 31, count 0 2006.280.07:47:30.20#ibcon#about to read 5, iclass 31, count 0 2006.280.07:47:30.20#ibcon#read 5, iclass 31, count 0 2006.280.07:47:30.20#ibcon#about to read 6, iclass 31, count 0 2006.280.07:47:30.20#ibcon#read 6, iclass 31, count 0 2006.280.07:47:30.20#ibcon#end of sib2, iclass 31, count 0 2006.280.07:47:30.20#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:47:30.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:47:30.20#ibcon#[25=USB\r\n] 2006.280.07:47:30.20#ibcon#*before write, iclass 31, count 0 2006.280.07:47:30.20#ibcon#enter sib2, iclass 31, count 0 2006.280.07:47:30.20#ibcon#flushed, iclass 31, count 0 2006.280.07:47:30.20#ibcon#about to write, iclass 31, count 0 2006.280.07:47:30.20#ibcon#wrote, iclass 31, count 0 2006.280.07:47:30.20#ibcon#about to read 3, iclass 31, count 0 2006.280.07:47:30.23#ibcon#read 3, iclass 31, count 0 2006.280.07:47:30.23#ibcon#about to read 4, iclass 31, count 0 2006.280.07:47:30.23#ibcon#read 4, iclass 31, count 0 2006.280.07:47:30.23#ibcon#about to read 5, iclass 31, count 0 2006.280.07:47:30.23#ibcon#read 5, iclass 31, count 0 2006.280.07:47:30.23#ibcon#about to read 6, iclass 31, count 0 2006.280.07:47:30.23#ibcon#read 6, iclass 31, count 0 2006.280.07:47:30.23#ibcon#end of sib2, iclass 31, count 0 2006.280.07:47:30.23#ibcon#*after write, iclass 31, count 0 2006.280.07:47:30.23#ibcon#*before return 0, iclass 31, count 0 2006.280.07:47:30.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:30.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:30.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:47:30.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:47:30.23$vc4f8/valo=6,772.99 2006.280.07:47:30.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:47:30.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:47:30.23#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:30.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:47:30.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:47:30.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:47:30.23#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:47:30.23#ibcon#first serial, iclass 33, count 0 2006.280.07:47:30.23#ibcon#enter sib2, iclass 33, count 0 2006.280.07:47:30.23#ibcon#flushed, iclass 33, count 0 2006.280.07:47:30.23#ibcon#about to write, iclass 33, count 0 2006.280.07:47:30.23#ibcon#wrote, iclass 33, count 0 2006.280.07:47:30.23#ibcon#about to read 3, iclass 33, count 0 2006.280.07:47:30.25#ibcon#read 3, iclass 33, count 0 2006.280.07:47:30.25#ibcon#about to read 4, iclass 33, count 0 2006.280.07:47:30.25#ibcon#read 4, iclass 33, count 0 2006.280.07:47:30.25#ibcon#about to read 5, iclass 33, count 0 2006.280.07:47:30.25#ibcon#read 5, iclass 33, count 0 2006.280.07:47:30.25#ibcon#about to read 6, iclass 33, count 0 2006.280.07:47:30.25#ibcon#read 6, iclass 33, count 0 2006.280.07:47:30.25#ibcon#end of sib2, iclass 33, count 0 2006.280.07:47:30.25#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:47:30.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:47:30.25#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:47:30.25#ibcon#*before write, iclass 33, count 0 2006.280.07:47:30.25#ibcon#enter sib2, iclass 33, count 0 2006.280.07:47:30.25#ibcon#flushed, iclass 33, count 0 2006.280.07:47:30.25#ibcon#about to write, iclass 33, count 0 2006.280.07:47:30.25#ibcon#wrote, iclass 33, count 0 2006.280.07:47:30.25#ibcon#about to read 3, iclass 33, count 0 2006.280.07:47:30.29#ibcon#read 3, iclass 33, count 0 2006.280.07:47:30.29#ibcon#about to read 4, iclass 33, count 0 2006.280.07:47:30.29#ibcon#read 4, iclass 33, count 0 2006.280.07:47:30.29#ibcon#about to read 5, iclass 33, count 0 2006.280.07:47:30.29#ibcon#read 5, iclass 33, count 0 2006.280.07:47:30.29#ibcon#about to read 6, iclass 33, count 0 2006.280.07:47:30.29#ibcon#read 6, iclass 33, count 0 2006.280.07:47:30.29#ibcon#end of sib2, iclass 33, count 0 2006.280.07:47:30.29#ibcon#*after write, iclass 33, count 0 2006.280.07:47:30.29#ibcon#*before return 0, iclass 33, count 0 2006.280.07:47:30.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:47:30.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:47:30.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:47:30.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:47:30.29$vc4f8/va=6,6 2006.280.07:47:30.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:47:30.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:47:30.31#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:30.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:47:30.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:47:30.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:47:30.34#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:47:30.34#ibcon#first serial, iclass 35, count 2 2006.280.07:47:30.34#ibcon#enter sib2, iclass 35, count 2 2006.280.07:47:30.34#ibcon#flushed, iclass 35, count 2 2006.280.07:47:30.34#ibcon#about to write, iclass 35, count 2 2006.280.07:47:30.34#ibcon#wrote, iclass 35, count 2 2006.280.07:47:30.34#ibcon#about to read 3, iclass 35, count 2 2006.280.07:47:30.36#ibcon#read 3, iclass 35, count 2 2006.280.07:47:30.36#ibcon#about to read 4, iclass 35, count 2 2006.280.07:47:30.36#ibcon#read 4, iclass 35, count 2 2006.280.07:47:30.36#ibcon#about to read 5, iclass 35, count 2 2006.280.07:47:30.36#ibcon#read 5, iclass 35, count 2 2006.280.07:47:30.36#ibcon#about to read 6, iclass 35, count 2 2006.280.07:47:30.36#ibcon#read 6, iclass 35, count 2 2006.280.07:47:30.36#ibcon#end of sib2, iclass 35, count 2 2006.280.07:47:30.36#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:47:30.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:47:30.36#ibcon#[25=AT06-06\r\n] 2006.280.07:47:30.36#ibcon#*before write, iclass 35, count 2 2006.280.07:47:30.36#ibcon#enter sib2, iclass 35, count 2 2006.280.07:47:30.36#ibcon#flushed, iclass 35, count 2 2006.280.07:47:30.36#ibcon#about to write, iclass 35, count 2 2006.280.07:47:30.36#ibcon#wrote, iclass 35, count 2 2006.280.07:47:30.36#ibcon#about to read 3, iclass 35, count 2 2006.280.07:47:30.39#ibcon#read 3, iclass 35, count 2 2006.280.07:47:30.39#ibcon#about to read 4, iclass 35, count 2 2006.280.07:47:30.39#ibcon#read 4, iclass 35, count 2 2006.280.07:47:30.39#ibcon#about to read 5, iclass 35, count 2 2006.280.07:47:30.39#ibcon#read 5, iclass 35, count 2 2006.280.07:47:30.39#ibcon#about to read 6, iclass 35, count 2 2006.280.07:47:30.39#ibcon#read 6, iclass 35, count 2 2006.280.07:47:30.39#ibcon#end of sib2, iclass 35, count 2 2006.280.07:47:30.39#ibcon#*after write, iclass 35, count 2 2006.280.07:47:30.39#ibcon#*before return 0, iclass 35, count 2 2006.280.07:47:30.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:47:30.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:47:30.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:47:30.39#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:30.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:47:30.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:47:30.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:47:30.51#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:47:30.51#ibcon#first serial, iclass 35, count 0 2006.280.07:47:30.51#ibcon#enter sib2, iclass 35, count 0 2006.280.07:47:30.51#ibcon#flushed, iclass 35, count 0 2006.280.07:47:30.51#ibcon#about to write, iclass 35, count 0 2006.280.07:47:30.51#ibcon#wrote, iclass 35, count 0 2006.280.07:47:30.51#ibcon#about to read 3, iclass 35, count 0 2006.280.07:47:30.53#ibcon#read 3, iclass 35, count 0 2006.280.07:47:30.53#ibcon#about to read 4, iclass 35, count 0 2006.280.07:47:30.53#ibcon#read 4, iclass 35, count 0 2006.280.07:47:30.53#ibcon#about to read 5, iclass 35, count 0 2006.280.07:47:30.53#ibcon#read 5, iclass 35, count 0 2006.280.07:47:30.53#ibcon#about to read 6, iclass 35, count 0 2006.280.07:47:30.53#ibcon#read 6, iclass 35, count 0 2006.280.07:47:30.53#ibcon#end of sib2, iclass 35, count 0 2006.280.07:47:30.53#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:47:30.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:47:30.53#ibcon#[25=USB\r\n] 2006.280.07:47:30.53#ibcon#*before write, iclass 35, count 0 2006.280.07:47:30.53#ibcon#enter sib2, iclass 35, count 0 2006.280.07:47:30.53#ibcon#flushed, iclass 35, count 0 2006.280.07:47:30.53#ibcon#about to write, iclass 35, count 0 2006.280.07:47:30.53#ibcon#wrote, iclass 35, count 0 2006.280.07:47:30.53#ibcon#about to read 3, iclass 35, count 0 2006.280.07:47:30.56#ibcon#read 3, iclass 35, count 0 2006.280.07:47:30.56#ibcon#about to read 4, iclass 35, count 0 2006.280.07:47:30.56#ibcon#read 4, iclass 35, count 0 2006.280.07:47:30.56#ibcon#about to read 5, iclass 35, count 0 2006.280.07:47:30.56#ibcon#read 5, iclass 35, count 0 2006.280.07:47:30.56#ibcon#about to read 6, iclass 35, count 0 2006.280.07:47:30.56#ibcon#read 6, iclass 35, count 0 2006.280.07:47:30.56#ibcon#end of sib2, iclass 35, count 0 2006.280.07:47:30.56#ibcon#*after write, iclass 35, count 0 2006.280.07:47:30.56#ibcon#*before return 0, iclass 35, count 0 2006.280.07:47:30.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:47:30.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:47:30.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:47:30.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:47:30.57$vc4f8/valo=7,832.99 2006.280.07:47:30.57#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:47:30.57#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:47:30.57#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:30.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:30.57#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:30.57#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:30.57#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:47:30.57#ibcon#first serial, iclass 37, count 0 2006.280.07:47:30.57#ibcon#enter sib2, iclass 37, count 0 2006.280.07:47:30.57#ibcon#flushed, iclass 37, count 0 2006.280.07:47:30.57#ibcon#about to write, iclass 37, count 0 2006.280.07:47:30.57#ibcon#wrote, iclass 37, count 0 2006.280.07:47:30.57#ibcon#about to read 3, iclass 37, count 0 2006.280.07:47:30.58#ibcon#read 3, iclass 37, count 0 2006.280.07:47:30.58#ibcon#about to read 4, iclass 37, count 0 2006.280.07:47:30.58#ibcon#read 4, iclass 37, count 0 2006.280.07:47:30.58#ibcon#about to read 5, iclass 37, count 0 2006.280.07:47:30.58#ibcon#read 5, iclass 37, count 0 2006.280.07:47:30.58#ibcon#about to read 6, iclass 37, count 0 2006.280.07:47:30.58#ibcon#read 6, iclass 37, count 0 2006.280.07:47:30.58#ibcon#end of sib2, iclass 37, count 0 2006.280.07:47:30.58#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:47:30.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:47:30.58#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:47:30.58#ibcon#*before write, iclass 37, count 0 2006.280.07:47:30.58#ibcon#enter sib2, iclass 37, count 0 2006.280.07:47:30.58#ibcon#flushed, iclass 37, count 0 2006.280.07:47:30.58#ibcon#about to write, iclass 37, count 0 2006.280.07:47:30.58#ibcon#wrote, iclass 37, count 0 2006.280.07:47:30.58#ibcon#about to read 3, iclass 37, count 0 2006.280.07:47:30.62#ibcon#read 3, iclass 37, count 0 2006.280.07:47:30.62#ibcon#about to read 4, iclass 37, count 0 2006.280.07:47:30.62#ibcon#read 4, iclass 37, count 0 2006.280.07:47:30.62#ibcon#about to read 5, iclass 37, count 0 2006.280.07:47:30.62#ibcon#read 5, iclass 37, count 0 2006.280.07:47:30.62#ibcon#about to read 6, iclass 37, count 0 2006.280.07:47:30.62#ibcon#read 6, iclass 37, count 0 2006.280.07:47:30.62#ibcon#end of sib2, iclass 37, count 0 2006.280.07:47:30.62#ibcon#*after write, iclass 37, count 0 2006.280.07:47:30.62#ibcon#*before return 0, iclass 37, count 0 2006.280.07:47:30.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:30.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:30.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:47:30.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:47:30.62$vc4f8/va=7,6 2006.280.07:47:30.63#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:47:30.63#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:47:30.63#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:30.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:30.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:30.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:30.68#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:47:30.68#ibcon#first serial, iclass 39, count 2 2006.280.07:47:30.68#ibcon#enter sib2, iclass 39, count 2 2006.280.07:47:30.68#ibcon#flushed, iclass 39, count 2 2006.280.07:47:30.68#ibcon#about to write, iclass 39, count 2 2006.280.07:47:30.68#ibcon#wrote, iclass 39, count 2 2006.280.07:47:30.68#ibcon#about to read 3, iclass 39, count 2 2006.280.07:47:30.69#ibcon#read 3, iclass 39, count 2 2006.280.07:47:30.69#ibcon#about to read 4, iclass 39, count 2 2006.280.07:47:30.69#ibcon#read 4, iclass 39, count 2 2006.280.07:47:30.69#ibcon#about to read 5, iclass 39, count 2 2006.280.07:47:30.69#ibcon#read 5, iclass 39, count 2 2006.280.07:47:30.69#ibcon#about to read 6, iclass 39, count 2 2006.280.07:47:30.69#ibcon#read 6, iclass 39, count 2 2006.280.07:47:30.69#ibcon#end of sib2, iclass 39, count 2 2006.280.07:47:30.69#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:47:30.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:47:30.69#ibcon#[25=AT07-06\r\n] 2006.280.07:47:30.69#ibcon#*before write, iclass 39, count 2 2006.280.07:47:30.69#ibcon#enter sib2, iclass 39, count 2 2006.280.07:47:30.69#ibcon#flushed, iclass 39, count 2 2006.280.07:47:30.69#ibcon#about to write, iclass 39, count 2 2006.280.07:47:30.69#ibcon#wrote, iclass 39, count 2 2006.280.07:47:30.69#ibcon#about to read 3, iclass 39, count 2 2006.280.07:47:30.72#ibcon#read 3, iclass 39, count 2 2006.280.07:47:30.72#ibcon#about to read 4, iclass 39, count 2 2006.280.07:47:30.72#ibcon#read 4, iclass 39, count 2 2006.280.07:47:30.72#ibcon#about to read 5, iclass 39, count 2 2006.280.07:47:30.72#ibcon#read 5, iclass 39, count 2 2006.280.07:47:30.72#ibcon#about to read 6, iclass 39, count 2 2006.280.07:47:30.72#ibcon#read 6, iclass 39, count 2 2006.280.07:47:30.72#ibcon#end of sib2, iclass 39, count 2 2006.280.07:47:30.72#ibcon#*after write, iclass 39, count 2 2006.280.07:47:30.72#ibcon#*before return 0, iclass 39, count 2 2006.280.07:47:30.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:30.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:30.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:47:30.72#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:30.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:47:30.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:47:30.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:47:30.84#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:47:30.84#ibcon#first serial, iclass 39, count 0 2006.280.07:47:30.84#ibcon#enter sib2, iclass 39, count 0 2006.280.07:47:30.84#ibcon#flushed, iclass 39, count 0 2006.280.07:47:30.84#ibcon#about to write, iclass 39, count 0 2006.280.07:47:30.84#ibcon#wrote, iclass 39, count 0 2006.280.07:47:30.84#ibcon#about to read 3, iclass 39, count 0 2006.280.07:47:30.86#ibcon#read 3, iclass 39, count 0 2006.280.07:47:30.86#ibcon#about to read 4, iclass 39, count 0 2006.280.07:47:30.86#ibcon#read 4, iclass 39, count 0 2006.280.07:47:30.86#ibcon#about to read 5, iclass 39, count 0 2006.280.07:47:30.86#ibcon#read 5, iclass 39, count 0 2006.280.07:47:30.86#ibcon#about to read 6, iclass 39, count 0 2006.280.07:47:30.86#ibcon#read 6, iclass 39, count 0 2006.280.07:47:30.86#ibcon#end of sib2, iclass 39, count 0 2006.280.07:47:30.86#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:47:30.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:47:30.86#ibcon#[25=USB\r\n] 2006.280.07:47:30.86#ibcon#*before write, iclass 39, count 0 2006.280.07:47:30.86#ibcon#enter sib2, iclass 39, count 0 2006.280.07:47:30.86#ibcon#flushed, iclass 39, count 0 2006.280.07:47:30.86#ibcon#about to write, iclass 39, count 0 2006.280.07:47:30.86#ibcon#wrote, iclass 39, count 0 2006.280.07:47:30.86#ibcon#about to read 3, iclass 39, count 0 2006.280.07:47:30.89#ibcon#read 3, iclass 39, count 0 2006.280.07:47:30.89#ibcon#about to read 4, iclass 39, count 0 2006.280.07:47:30.89#ibcon#read 4, iclass 39, count 0 2006.280.07:47:30.89#ibcon#about to read 5, iclass 39, count 0 2006.280.07:47:30.89#ibcon#read 5, iclass 39, count 0 2006.280.07:47:30.89#ibcon#about to read 6, iclass 39, count 0 2006.280.07:47:30.89#ibcon#read 6, iclass 39, count 0 2006.280.07:47:30.89#ibcon#end of sib2, iclass 39, count 0 2006.280.07:47:30.89#ibcon#*after write, iclass 39, count 0 2006.280.07:47:30.89#ibcon#*before return 0, iclass 39, count 0 2006.280.07:47:30.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:47:30.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:47:30.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:47:30.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:47:30.89$vc4f8/valo=8,852.99 2006.280.07:47:30.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:47:30.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:47:30.89#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:30.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:47:30.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:47:30.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:47:30.89#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:47:30.89#ibcon#first serial, iclass 3, count 0 2006.280.07:47:30.89#ibcon#enter sib2, iclass 3, count 0 2006.280.07:47:30.89#ibcon#flushed, iclass 3, count 0 2006.280.07:47:30.89#ibcon#about to write, iclass 3, count 0 2006.280.07:47:30.89#ibcon#wrote, iclass 3, count 0 2006.280.07:47:30.89#ibcon#about to read 3, iclass 3, count 0 2006.280.07:47:30.91#ibcon#read 3, iclass 3, count 0 2006.280.07:47:30.91#ibcon#about to read 4, iclass 3, count 0 2006.280.07:47:30.91#ibcon#read 4, iclass 3, count 0 2006.280.07:47:30.91#ibcon#about to read 5, iclass 3, count 0 2006.280.07:47:30.91#ibcon#read 5, iclass 3, count 0 2006.280.07:47:30.91#ibcon#about to read 6, iclass 3, count 0 2006.280.07:47:30.91#ibcon#read 6, iclass 3, count 0 2006.280.07:47:30.91#ibcon#end of sib2, iclass 3, count 0 2006.280.07:47:30.91#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:47:30.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:47:30.94#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:47:30.94#ibcon#*before write, iclass 3, count 0 2006.280.07:47:30.94#ibcon#enter sib2, iclass 3, count 0 2006.280.07:47:30.94#ibcon#flushed, iclass 3, count 0 2006.280.07:47:30.94#ibcon#about to write, iclass 3, count 0 2006.280.07:47:30.94#ibcon#wrote, iclass 3, count 0 2006.280.07:47:30.94#ibcon#about to read 3, iclass 3, count 0 2006.280.07:47:30.98#ibcon#read 3, iclass 3, count 0 2006.280.07:47:30.98#ibcon#about to read 4, iclass 3, count 0 2006.280.07:47:30.98#ibcon#read 4, iclass 3, count 0 2006.280.07:47:30.98#ibcon#about to read 5, iclass 3, count 0 2006.280.07:47:30.98#ibcon#read 5, iclass 3, count 0 2006.280.07:47:30.98#ibcon#about to read 6, iclass 3, count 0 2006.280.07:47:30.98#ibcon#read 6, iclass 3, count 0 2006.280.07:47:30.98#ibcon#end of sib2, iclass 3, count 0 2006.280.07:47:30.98#ibcon#*after write, iclass 3, count 0 2006.280.07:47:30.98#ibcon#*before return 0, iclass 3, count 0 2006.280.07:47:30.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:47:30.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:47:30.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:47:30.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:47:30.98$vc4f8/va=8,6 2006.280.07:47:30.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:47:30.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:47:30.98#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:30.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:47:31.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:47:31.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:47:31.01#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:47:31.01#ibcon#first serial, iclass 5, count 2 2006.280.07:47:31.01#ibcon#enter sib2, iclass 5, count 2 2006.280.07:47:31.01#ibcon#flushed, iclass 5, count 2 2006.280.07:47:31.01#ibcon#about to write, iclass 5, count 2 2006.280.07:47:31.01#ibcon#wrote, iclass 5, count 2 2006.280.07:47:31.01#ibcon#about to read 3, iclass 5, count 2 2006.280.07:47:31.03#ibcon#read 3, iclass 5, count 2 2006.280.07:47:31.03#ibcon#about to read 4, iclass 5, count 2 2006.280.07:47:31.03#ibcon#read 4, iclass 5, count 2 2006.280.07:47:31.03#ibcon#about to read 5, iclass 5, count 2 2006.280.07:47:31.03#ibcon#read 5, iclass 5, count 2 2006.280.07:47:31.03#ibcon#about to read 6, iclass 5, count 2 2006.280.07:47:31.03#ibcon#read 6, iclass 5, count 2 2006.280.07:47:31.03#ibcon#end of sib2, iclass 5, count 2 2006.280.07:47:31.03#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:47:31.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:47:31.03#ibcon#[25=AT08-06\r\n] 2006.280.07:47:31.03#ibcon#*before write, iclass 5, count 2 2006.280.07:47:31.03#ibcon#enter sib2, iclass 5, count 2 2006.280.07:47:31.03#ibcon#flushed, iclass 5, count 2 2006.280.07:47:31.03#ibcon#about to write, iclass 5, count 2 2006.280.07:47:31.03#ibcon#wrote, iclass 5, count 2 2006.280.07:47:31.03#ibcon#about to read 3, iclass 5, count 2 2006.280.07:47:31.06#ibcon#read 3, iclass 5, count 2 2006.280.07:47:31.06#ibcon#about to read 4, iclass 5, count 2 2006.280.07:47:31.06#ibcon#read 4, iclass 5, count 2 2006.280.07:47:31.06#ibcon#about to read 5, iclass 5, count 2 2006.280.07:47:31.06#ibcon#read 5, iclass 5, count 2 2006.280.07:47:31.06#ibcon#about to read 6, iclass 5, count 2 2006.280.07:47:31.06#ibcon#read 6, iclass 5, count 2 2006.280.07:47:31.06#ibcon#end of sib2, iclass 5, count 2 2006.280.07:47:31.06#ibcon#*after write, iclass 5, count 2 2006.280.07:47:31.06#ibcon#*before return 0, iclass 5, count 2 2006.280.07:47:31.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:47:31.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:47:31.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:47:31.06#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:31.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:47:31.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:47:31.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:47:31.18#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:47:31.18#ibcon#first serial, iclass 5, count 0 2006.280.07:47:31.18#ibcon#enter sib2, iclass 5, count 0 2006.280.07:47:31.18#ibcon#flushed, iclass 5, count 0 2006.280.07:47:31.18#ibcon#about to write, iclass 5, count 0 2006.280.07:47:31.18#ibcon#wrote, iclass 5, count 0 2006.280.07:47:31.18#ibcon#about to read 3, iclass 5, count 0 2006.280.07:47:31.20#ibcon#read 3, iclass 5, count 0 2006.280.07:47:31.20#ibcon#about to read 4, iclass 5, count 0 2006.280.07:47:31.20#ibcon#read 4, iclass 5, count 0 2006.280.07:47:31.20#ibcon#about to read 5, iclass 5, count 0 2006.280.07:47:31.20#ibcon#read 5, iclass 5, count 0 2006.280.07:47:31.20#ibcon#about to read 6, iclass 5, count 0 2006.280.07:47:31.20#ibcon#read 6, iclass 5, count 0 2006.280.07:47:31.20#ibcon#end of sib2, iclass 5, count 0 2006.280.07:47:31.20#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:47:31.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:47:31.20#ibcon#[25=USB\r\n] 2006.280.07:47:31.20#ibcon#*before write, iclass 5, count 0 2006.280.07:47:31.20#ibcon#enter sib2, iclass 5, count 0 2006.280.07:47:31.20#ibcon#flushed, iclass 5, count 0 2006.280.07:47:31.20#ibcon#about to write, iclass 5, count 0 2006.280.07:47:31.20#ibcon#wrote, iclass 5, count 0 2006.280.07:47:31.20#ibcon#about to read 3, iclass 5, count 0 2006.280.07:47:31.23#ibcon#read 3, iclass 5, count 0 2006.280.07:47:31.23#ibcon#about to read 4, iclass 5, count 0 2006.280.07:47:31.23#ibcon#read 4, iclass 5, count 0 2006.280.07:47:31.23#ibcon#about to read 5, iclass 5, count 0 2006.280.07:47:31.23#ibcon#read 5, iclass 5, count 0 2006.280.07:47:31.23#ibcon#about to read 6, iclass 5, count 0 2006.280.07:47:31.23#ibcon#read 6, iclass 5, count 0 2006.280.07:47:31.23#ibcon#end of sib2, iclass 5, count 0 2006.280.07:47:31.23#ibcon#*after write, iclass 5, count 0 2006.280.07:47:31.23#ibcon#*before return 0, iclass 5, count 0 2006.280.07:47:31.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:47:31.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:47:31.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:47:31.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:47:31.23$vc4f8/vblo=1,632.99 2006.280.07:47:31.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:47:31.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:47:31.23#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:31.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:47:31.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:47:31.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:47:31.23#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:47:31.23#ibcon#first serial, iclass 7, count 0 2006.280.07:47:31.23#ibcon#enter sib2, iclass 7, count 0 2006.280.07:47:31.23#ibcon#flushed, iclass 7, count 0 2006.280.07:47:31.23#ibcon#about to write, iclass 7, count 0 2006.280.07:47:31.23#ibcon#wrote, iclass 7, count 0 2006.280.07:47:31.23#ibcon#about to read 3, iclass 7, count 0 2006.280.07:47:31.25#ibcon#read 3, iclass 7, count 0 2006.280.07:47:31.25#ibcon#about to read 4, iclass 7, count 0 2006.280.07:47:31.26#ibcon#read 4, iclass 7, count 0 2006.280.07:47:31.26#ibcon#about to read 5, iclass 7, count 0 2006.280.07:47:31.26#ibcon#read 5, iclass 7, count 0 2006.280.07:47:31.26#ibcon#about to read 6, iclass 7, count 0 2006.280.07:47:31.26#ibcon#read 6, iclass 7, count 0 2006.280.07:47:31.26#ibcon#end of sib2, iclass 7, count 0 2006.280.07:47:31.26#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:47:31.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:47:31.26#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:47:31.26#ibcon#*before write, iclass 7, count 0 2006.280.07:47:31.26#ibcon#enter sib2, iclass 7, count 0 2006.280.07:47:31.26#ibcon#flushed, iclass 7, count 0 2006.280.07:47:31.26#ibcon#about to write, iclass 7, count 0 2006.280.07:47:31.26#ibcon#wrote, iclass 7, count 0 2006.280.07:47:31.26#ibcon#about to read 3, iclass 7, count 0 2006.280.07:47:31.29#ibcon#read 3, iclass 7, count 0 2006.280.07:47:31.29#ibcon#about to read 4, iclass 7, count 0 2006.280.07:47:31.29#ibcon#read 4, iclass 7, count 0 2006.280.07:47:31.29#ibcon#about to read 5, iclass 7, count 0 2006.280.07:47:31.29#ibcon#read 5, iclass 7, count 0 2006.280.07:47:31.29#ibcon#about to read 6, iclass 7, count 0 2006.280.07:47:31.29#ibcon#read 6, iclass 7, count 0 2006.280.07:47:31.29#ibcon#end of sib2, iclass 7, count 0 2006.280.07:47:31.29#ibcon#*after write, iclass 7, count 0 2006.280.07:47:31.29#ibcon#*before return 0, iclass 7, count 0 2006.280.07:47:31.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:47:31.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:47:31.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:47:31.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:47:31.29$vc4f8/vb=1,4 2006.280.07:47:31.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:47:31.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:47:31.29#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:31.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:47:31.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:47:31.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:47:31.29#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:47:31.29#ibcon#first serial, iclass 11, count 2 2006.280.07:47:31.29#ibcon#enter sib2, iclass 11, count 2 2006.280.07:47:31.29#ibcon#flushed, iclass 11, count 2 2006.280.07:47:31.29#ibcon#about to write, iclass 11, count 2 2006.280.07:47:31.29#ibcon#wrote, iclass 11, count 2 2006.280.07:47:31.29#ibcon#about to read 3, iclass 11, count 2 2006.280.07:47:31.32#ibcon#read 3, iclass 11, count 2 2006.280.07:47:31.32#ibcon#about to read 4, iclass 11, count 2 2006.280.07:47:31.32#ibcon#read 4, iclass 11, count 2 2006.280.07:47:31.32#ibcon#about to read 5, iclass 11, count 2 2006.280.07:47:31.32#ibcon#read 5, iclass 11, count 2 2006.280.07:47:31.32#ibcon#about to read 6, iclass 11, count 2 2006.280.07:47:31.32#ibcon#read 6, iclass 11, count 2 2006.280.07:47:31.32#ibcon#end of sib2, iclass 11, count 2 2006.280.07:47:31.32#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:47:31.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:47:31.32#ibcon#[27=AT01-04\r\n] 2006.280.07:47:31.32#ibcon#*before write, iclass 11, count 2 2006.280.07:47:31.32#ibcon#enter sib2, iclass 11, count 2 2006.280.07:47:31.32#ibcon#flushed, iclass 11, count 2 2006.280.07:47:31.32#ibcon#about to write, iclass 11, count 2 2006.280.07:47:31.32#ibcon#wrote, iclass 11, count 2 2006.280.07:47:31.32#ibcon#about to read 3, iclass 11, count 2 2006.280.07:47:31.34#ibcon#read 3, iclass 11, count 2 2006.280.07:47:31.34#ibcon#about to read 4, iclass 11, count 2 2006.280.07:47:31.34#ibcon#read 4, iclass 11, count 2 2006.280.07:47:31.34#ibcon#about to read 5, iclass 11, count 2 2006.280.07:47:31.34#ibcon#read 5, iclass 11, count 2 2006.280.07:47:31.34#ibcon#about to read 6, iclass 11, count 2 2006.280.07:47:31.35#ibcon#read 6, iclass 11, count 2 2006.280.07:47:31.35#ibcon#end of sib2, iclass 11, count 2 2006.280.07:47:31.35#ibcon#*after write, iclass 11, count 2 2006.280.07:47:31.35#ibcon#*before return 0, iclass 11, count 2 2006.280.07:47:31.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:47:31.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:47:31.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:47:31.35#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:31.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:47:31.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:47:31.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:47:31.46#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:47:31.46#ibcon#first serial, iclass 11, count 0 2006.280.07:47:31.46#ibcon#enter sib2, iclass 11, count 0 2006.280.07:47:31.46#ibcon#flushed, iclass 11, count 0 2006.280.07:47:31.46#ibcon#about to write, iclass 11, count 0 2006.280.07:47:31.46#ibcon#wrote, iclass 11, count 0 2006.280.07:47:31.46#ibcon#about to read 3, iclass 11, count 0 2006.280.07:47:31.48#ibcon#read 3, iclass 11, count 0 2006.280.07:47:31.48#ibcon#about to read 4, iclass 11, count 0 2006.280.07:47:31.48#ibcon#read 4, iclass 11, count 0 2006.280.07:47:31.48#ibcon#about to read 5, iclass 11, count 0 2006.280.07:47:31.48#ibcon#read 5, iclass 11, count 0 2006.280.07:47:31.48#ibcon#about to read 6, iclass 11, count 0 2006.280.07:47:31.48#ibcon#read 6, iclass 11, count 0 2006.280.07:47:31.48#ibcon#end of sib2, iclass 11, count 0 2006.280.07:47:31.48#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:47:31.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:47:31.48#ibcon#[27=USB\r\n] 2006.280.07:47:31.48#ibcon#*before write, iclass 11, count 0 2006.280.07:47:31.48#ibcon#enter sib2, iclass 11, count 0 2006.280.07:47:31.48#ibcon#flushed, iclass 11, count 0 2006.280.07:47:31.48#ibcon#about to write, iclass 11, count 0 2006.280.07:47:31.48#ibcon#wrote, iclass 11, count 0 2006.280.07:47:31.48#ibcon#about to read 3, iclass 11, count 0 2006.280.07:47:31.51#ibcon#read 3, iclass 11, count 0 2006.280.07:47:31.51#ibcon#about to read 4, iclass 11, count 0 2006.280.07:47:31.51#ibcon#read 4, iclass 11, count 0 2006.280.07:47:31.51#ibcon#about to read 5, iclass 11, count 0 2006.280.07:47:31.51#ibcon#read 5, iclass 11, count 0 2006.280.07:47:31.51#ibcon#about to read 6, iclass 11, count 0 2006.280.07:47:31.51#ibcon#read 6, iclass 11, count 0 2006.280.07:47:31.51#ibcon#end of sib2, iclass 11, count 0 2006.280.07:47:31.51#ibcon#*after write, iclass 11, count 0 2006.280.07:47:31.51#ibcon#*before return 0, iclass 11, count 0 2006.280.07:47:31.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:47:31.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:47:31.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:47:31.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:47:31.51$vc4f8/vblo=2,640.99 2006.280.07:47:31.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:47:31.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:47:31.51#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:31.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:31.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:31.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:31.51#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:47:31.51#ibcon#first serial, iclass 13, count 0 2006.280.07:47:31.51#ibcon#enter sib2, iclass 13, count 0 2006.280.07:47:31.51#ibcon#flushed, iclass 13, count 0 2006.280.07:47:31.51#ibcon#about to write, iclass 13, count 0 2006.280.07:47:31.51#ibcon#wrote, iclass 13, count 0 2006.280.07:47:31.51#ibcon#about to read 3, iclass 13, count 0 2006.280.07:47:31.53#ibcon#read 3, iclass 13, count 0 2006.280.07:47:31.53#ibcon#about to read 4, iclass 13, count 0 2006.280.07:47:31.53#ibcon#read 4, iclass 13, count 0 2006.280.07:47:31.53#ibcon#about to read 5, iclass 13, count 0 2006.280.07:47:31.53#ibcon#read 5, iclass 13, count 0 2006.280.07:47:31.53#ibcon#about to read 6, iclass 13, count 0 2006.280.07:47:31.53#ibcon#read 6, iclass 13, count 0 2006.280.07:47:31.53#ibcon#end of sib2, iclass 13, count 0 2006.280.07:47:31.53#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:47:31.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:47:31.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:47:31.53#ibcon#*before write, iclass 13, count 0 2006.280.07:47:31.53#ibcon#enter sib2, iclass 13, count 0 2006.280.07:47:31.53#ibcon#flushed, iclass 13, count 0 2006.280.07:47:31.53#ibcon#about to write, iclass 13, count 0 2006.280.07:47:31.53#ibcon#wrote, iclass 13, count 0 2006.280.07:47:31.53#ibcon#about to read 3, iclass 13, count 0 2006.280.07:47:31.57#ibcon#read 3, iclass 13, count 0 2006.280.07:47:31.57#ibcon#about to read 4, iclass 13, count 0 2006.280.07:47:31.57#ibcon#read 4, iclass 13, count 0 2006.280.07:47:31.57#ibcon#about to read 5, iclass 13, count 0 2006.280.07:47:31.57#ibcon#read 5, iclass 13, count 0 2006.280.07:47:31.57#ibcon#about to read 6, iclass 13, count 0 2006.280.07:47:31.57#ibcon#read 6, iclass 13, count 0 2006.280.07:47:31.57#ibcon#end of sib2, iclass 13, count 0 2006.280.07:47:31.57#ibcon#*after write, iclass 13, count 0 2006.280.07:47:31.57#ibcon#*before return 0, iclass 13, count 0 2006.280.07:47:31.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:31.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:47:31.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:47:31.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:47:31.57$vc4f8/vb=2,5 2006.280.07:47:31.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:47:31.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:47:31.58#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:31.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:31.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:31.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:31.62#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:47:31.62#ibcon#first serial, iclass 15, count 2 2006.280.07:47:31.62#ibcon#enter sib2, iclass 15, count 2 2006.280.07:47:31.62#ibcon#flushed, iclass 15, count 2 2006.280.07:47:31.62#ibcon#about to write, iclass 15, count 2 2006.280.07:47:31.62#ibcon#wrote, iclass 15, count 2 2006.280.07:47:31.62#ibcon#about to read 3, iclass 15, count 2 2006.280.07:47:31.64#ibcon#read 3, iclass 15, count 2 2006.280.07:47:31.64#ibcon#about to read 4, iclass 15, count 2 2006.280.07:47:31.64#ibcon#read 4, iclass 15, count 2 2006.280.07:47:31.64#ibcon#about to read 5, iclass 15, count 2 2006.280.07:47:31.64#ibcon#read 5, iclass 15, count 2 2006.280.07:47:31.64#ibcon#about to read 6, iclass 15, count 2 2006.280.07:47:31.64#ibcon#read 6, iclass 15, count 2 2006.280.07:47:31.64#ibcon#end of sib2, iclass 15, count 2 2006.280.07:47:31.64#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:47:31.64#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:47:31.64#ibcon#[27=AT02-05\r\n] 2006.280.07:47:31.64#ibcon#*before write, iclass 15, count 2 2006.280.07:47:31.64#ibcon#enter sib2, iclass 15, count 2 2006.280.07:47:31.64#ibcon#flushed, iclass 15, count 2 2006.280.07:47:31.64#ibcon#about to write, iclass 15, count 2 2006.280.07:47:31.64#ibcon#wrote, iclass 15, count 2 2006.280.07:47:31.64#ibcon#about to read 3, iclass 15, count 2 2006.280.07:47:31.67#ibcon#read 3, iclass 15, count 2 2006.280.07:47:31.67#ibcon#about to read 4, iclass 15, count 2 2006.280.07:47:31.67#ibcon#read 4, iclass 15, count 2 2006.280.07:47:31.67#ibcon#about to read 5, iclass 15, count 2 2006.280.07:47:31.67#ibcon#read 5, iclass 15, count 2 2006.280.07:47:31.67#ibcon#about to read 6, iclass 15, count 2 2006.280.07:47:31.67#ibcon#read 6, iclass 15, count 2 2006.280.07:47:31.67#ibcon#end of sib2, iclass 15, count 2 2006.280.07:47:31.67#ibcon#*after write, iclass 15, count 2 2006.280.07:47:31.67#ibcon#*before return 0, iclass 15, count 2 2006.280.07:47:31.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:31.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:47:31.67#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:47:31.67#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:31.67#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:31.79#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:31.79#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:31.79#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:47:31.79#ibcon#first serial, iclass 15, count 0 2006.280.07:47:31.79#ibcon#enter sib2, iclass 15, count 0 2006.280.07:47:31.79#ibcon#flushed, iclass 15, count 0 2006.280.07:47:31.79#ibcon#about to write, iclass 15, count 0 2006.280.07:47:31.79#ibcon#wrote, iclass 15, count 0 2006.280.07:47:31.79#ibcon#about to read 3, iclass 15, count 0 2006.280.07:47:31.81#ibcon#read 3, iclass 15, count 0 2006.280.07:47:31.81#ibcon#about to read 4, iclass 15, count 0 2006.280.07:47:31.81#ibcon#read 4, iclass 15, count 0 2006.280.07:47:31.81#ibcon#about to read 5, iclass 15, count 0 2006.280.07:47:31.81#ibcon#read 5, iclass 15, count 0 2006.280.07:47:31.81#ibcon#about to read 6, iclass 15, count 0 2006.280.07:47:31.81#ibcon#read 6, iclass 15, count 0 2006.280.07:47:31.81#ibcon#end of sib2, iclass 15, count 0 2006.280.07:47:31.81#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:47:31.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:47:31.81#ibcon#[27=USB\r\n] 2006.280.07:47:31.81#ibcon#*before write, iclass 15, count 0 2006.280.07:47:31.81#ibcon#enter sib2, iclass 15, count 0 2006.280.07:47:31.81#ibcon#flushed, iclass 15, count 0 2006.280.07:47:31.81#ibcon#about to write, iclass 15, count 0 2006.280.07:47:31.81#ibcon#wrote, iclass 15, count 0 2006.280.07:47:31.81#ibcon#about to read 3, iclass 15, count 0 2006.280.07:47:31.85#ibcon#read 3, iclass 15, count 0 2006.280.07:47:31.85#ibcon#about to read 4, iclass 15, count 0 2006.280.07:47:31.85#ibcon#read 4, iclass 15, count 0 2006.280.07:47:31.85#ibcon#about to read 5, iclass 15, count 0 2006.280.07:47:31.85#ibcon#read 5, iclass 15, count 0 2006.280.07:47:31.85#ibcon#about to read 6, iclass 15, count 0 2006.280.07:47:31.85#ibcon#read 6, iclass 15, count 0 2006.280.07:47:31.85#ibcon#end of sib2, iclass 15, count 0 2006.280.07:47:31.85#ibcon#*after write, iclass 15, count 0 2006.280.07:47:31.85#ibcon#*before return 0, iclass 15, count 0 2006.280.07:47:31.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:31.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:47:31.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:47:31.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:47:31.85$vc4f8/vblo=3,656.99 2006.280.07:47:31.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:47:31.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:47:31.85#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:31.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:31.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:31.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:31.85#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:47:31.85#ibcon#first serial, iclass 17, count 0 2006.280.07:47:31.85#ibcon#enter sib2, iclass 17, count 0 2006.280.07:47:31.85#ibcon#flushed, iclass 17, count 0 2006.280.07:47:31.85#ibcon#about to write, iclass 17, count 0 2006.280.07:47:31.85#ibcon#wrote, iclass 17, count 0 2006.280.07:47:31.85#ibcon#about to read 3, iclass 17, count 0 2006.280.07:47:31.86#ibcon#read 3, iclass 17, count 0 2006.280.07:47:31.86#ibcon#about to read 4, iclass 17, count 0 2006.280.07:47:31.86#ibcon#read 4, iclass 17, count 0 2006.280.07:47:31.86#ibcon#about to read 5, iclass 17, count 0 2006.280.07:47:31.86#ibcon#read 5, iclass 17, count 0 2006.280.07:47:31.86#ibcon#about to read 6, iclass 17, count 0 2006.280.07:47:31.86#ibcon#read 6, iclass 17, count 0 2006.280.07:47:31.86#ibcon#end of sib2, iclass 17, count 0 2006.280.07:47:31.86#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:47:31.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:47:31.89#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:47:31.89#ibcon#*before write, iclass 17, count 0 2006.280.07:47:31.89#ibcon#enter sib2, iclass 17, count 0 2006.280.07:47:31.89#ibcon#flushed, iclass 17, count 0 2006.280.07:47:31.89#ibcon#about to write, iclass 17, count 0 2006.280.07:47:31.89#ibcon#wrote, iclass 17, count 0 2006.280.07:47:31.89#ibcon#about to read 3, iclass 17, count 0 2006.280.07:47:31.93#ibcon#read 3, iclass 17, count 0 2006.280.07:47:31.93#ibcon#about to read 4, iclass 17, count 0 2006.280.07:47:31.93#ibcon#read 4, iclass 17, count 0 2006.280.07:47:31.93#ibcon#about to read 5, iclass 17, count 0 2006.280.07:47:31.93#ibcon#read 5, iclass 17, count 0 2006.280.07:47:31.93#ibcon#about to read 6, iclass 17, count 0 2006.280.07:47:31.93#ibcon#read 6, iclass 17, count 0 2006.280.07:47:31.93#ibcon#end of sib2, iclass 17, count 0 2006.280.07:47:31.93#ibcon#*after write, iclass 17, count 0 2006.280.07:47:31.93#ibcon#*before return 0, iclass 17, count 0 2006.280.07:47:31.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:31.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:47:31.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:47:31.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:47:31.93$vc4f8/vb=3,4 2006.280.07:47:31.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:47:31.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:47:31.93#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:31.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:31.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:31.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:31.97#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:47:31.97#ibcon#first serial, iclass 19, count 2 2006.280.07:47:31.97#ibcon#enter sib2, iclass 19, count 2 2006.280.07:47:31.97#ibcon#flushed, iclass 19, count 2 2006.280.07:47:31.97#ibcon#about to write, iclass 19, count 2 2006.280.07:47:31.97#ibcon#wrote, iclass 19, count 2 2006.280.07:47:31.97#ibcon#about to read 3, iclass 19, count 2 2006.280.07:47:31.99#ibcon#read 3, iclass 19, count 2 2006.280.07:47:31.99#ibcon#about to read 4, iclass 19, count 2 2006.280.07:47:31.99#ibcon#read 4, iclass 19, count 2 2006.280.07:47:31.99#ibcon#about to read 5, iclass 19, count 2 2006.280.07:47:31.99#ibcon#read 5, iclass 19, count 2 2006.280.07:47:31.99#ibcon#about to read 6, iclass 19, count 2 2006.280.07:47:31.99#ibcon#read 6, iclass 19, count 2 2006.280.07:47:31.99#ibcon#end of sib2, iclass 19, count 2 2006.280.07:47:31.99#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:47:31.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:47:31.99#ibcon#[27=AT03-04\r\n] 2006.280.07:47:31.99#ibcon#*before write, iclass 19, count 2 2006.280.07:47:31.99#ibcon#enter sib2, iclass 19, count 2 2006.280.07:47:31.99#ibcon#flushed, iclass 19, count 2 2006.280.07:47:31.99#ibcon#about to write, iclass 19, count 2 2006.280.07:47:31.99#ibcon#wrote, iclass 19, count 2 2006.280.07:47:31.99#ibcon#about to read 3, iclass 19, count 2 2006.280.07:47:32.02#ibcon#read 3, iclass 19, count 2 2006.280.07:47:32.02#ibcon#about to read 4, iclass 19, count 2 2006.280.07:47:32.02#ibcon#read 4, iclass 19, count 2 2006.280.07:47:32.02#ibcon#about to read 5, iclass 19, count 2 2006.280.07:47:32.02#ibcon#read 5, iclass 19, count 2 2006.280.07:47:32.02#ibcon#about to read 6, iclass 19, count 2 2006.280.07:47:32.02#ibcon#read 6, iclass 19, count 2 2006.280.07:47:32.02#ibcon#end of sib2, iclass 19, count 2 2006.280.07:47:32.02#ibcon#*after write, iclass 19, count 2 2006.280.07:47:32.02#ibcon#*before return 0, iclass 19, count 2 2006.280.07:47:32.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:32.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:47:32.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:47:32.02#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:32.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:32.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:32.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:32.14#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:47:32.14#ibcon#first serial, iclass 19, count 0 2006.280.07:47:32.14#ibcon#enter sib2, iclass 19, count 0 2006.280.07:47:32.14#ibcon#flushed, iclass 19, count 0 2006.280.07:47:32.14#ibcon#about to write, iclass 19, count 0 2006.280.07:47:32.14#ibcon#wrote, iclass 19, count 0 2006.280.07:47:32.14#ibcon#about to read 3, iclass 19, count 0 2006.280.07:47:32.16#ibcon#read 3, iclass 19, count 0 2006.280.07:47:32.16#ibcon#about to read 4, iclass 19, count 0 2006.280.07:47:32.16#ibcon#read 4, iclass 19, count 0 2006.280.07:47:32.16#ibcon#about to read 5, iclass 19, count 0 2006.280.07:47:32.16#ibcon#read 5, iclass 19, count 0 2006.280.07:47:32.16#ibcon#about to read 6, iclass 19, count 0 2006.280.07:47:32.16#ibcon#read 6, iclass 19, count 0 2006.280.07:47:32.16#ibcon#end of sib2, iclass 19, count 0 2006.280.07:47:32.16#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:47:32.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:47:32.16#ibcon#[27=USB\r\n] 2006.280.07:47:32.16#ibcon#*before write, iclass 19, count 0 2006.280.07:47:32.16#ibcon#enter sib2, iclass 19, count 0 2006.280.07:47:32.16#ibcon#flushed, iclass 19, count 0 2006.280.07:47:32.16#ibcon#about to write, iclass 19, count 0 2006.280.07:47:32.16#ibcon#wrote, iclass 19, count 0 2006.280.07:47:32.16#ibcon#about to read 3, iclass 19, count 0 2006.280.07:47:32.19#ibcon#read 3, iclass 19, count 0 2006.280.07:47:32.19#ibcon#about to read 4, iclass 19, count 0 2006.280.07:47:32.19#ibcon#read 4, iclass 19, count 0 2006.280.07:47:32.19#ibcon#about to read 5, iclass 19, count 0 2006.280.07:47:32.19#ibcon#read 5, iclass 19, count 0 2006.280.07:47:32.19#ibcon#about to read 6, iclass 19, count 0 2006.280.07:47:32.19#ibcon#read 6, iclass 19, count 0 2006.280.07:47:32.19#ibcon#end of sib2, iclass 19, count 0 2006.280.07:47:32.19#ibcon#*after write, iclass 19, count 0 2006.280.07:47:32.19#ibcon#*before return 0, iclass 19, count 0 2006.280.07:47:32.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:32.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:47:32.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:47:32.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:47:32.19$vc4f8/vblo=4,712.99 2006.280.07:47:32.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.07:47:32.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.07:47:32.19#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:32.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:32.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:32.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:32.19#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:47:32.19#ibcon#first serial, iclass 21, count 0 2006.280.07:47:32.19#ibcon#enter sib2, iclass 21, count 0 2006.280.07:47:32.19#ibcon#flushed, iclass 21, count 0 2006.280.07:47:32.19#ibcon#about to write, iclass 21, count 0 2006.280.07:47:32.19#ibcon#wrote, iclass 21, count 0 2006.280.07:47:32.19#ibcon#about to read 3, iclass 21, count 0 2006.280.07:47:32.21#ibcon#read 3, iclass 21, count 0 2006.280.07:47:32.21#ibcon#about to read 4, iclass 21, count 0 2006.280.07:47:32.21#ibcon#read 4, iclass 21, count 0 2006.280.07:47:32.21#ibcon#about to read 5, iclass 21, count 0 2006.280.07:47:32.21#ibcon#read 5, iclass 21, count 0 2006.280.07:47:32.21#ibcon#about to read 6, iclass 21, count 0 2006.280.07:47:32.21#ibcon#read 6, iclass 21, count 0 2006.280.07:47:32.21#ibcon#end of sib2, iclass 21, count 0 2006.280.07:47:32.21#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:47:32.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:47:32.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:47:32.21#ibcon#*before write, iclass 21, count 0 2006.280.07:47:32.21#ibcon#enter sib2, iclass 21, count 0 2006.280.07:47:32.21#ibcon#flushed, iclass 21, count 0 2006.280.07:47:32.21#ibcon#about to write, iclass 21, count 0 2006.280.07:47:32.21#ibcon#wrote, iclass 21, count 0 2006.280.07:47:32.21#ibcon#about to read 3, iclass 21, count 0 2006.280.07:47:32.25#ibcon#read 3, iclass 21, count 0 2006.280.07:47:32.25#ibcon#about to read 4, iclass 21, count 0 2006.280.07:47:32.25#ibcon#read 4, iclass 21, count 0 2006.280.07:47:32.25#ibcon#about to read 5, iclass 21, count 0 2006.280.07:47:32.25#ibcon#read 5, iclass 21, count 0 2006.280.07:47:32.25#ibcon#about to read 6, iclass 21, count 0 2006.280.07:47:32.25#ibcon#read 6, iclass 21, count 0 2006.280.07:47:32.25#ibcon#end of sib2, iclass 21, count 0 2006.280.07:47:32.25#ibcon#*after write, iclass 21, count 0 2006.280.07:47:32.25#ibcon#*before return 0, iclass 21, count 0 2006.280.07:47:32.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:32.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.07:47:32.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:47:32.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:47:32.25$vc4f8/vb=4,4 2006.280.07:47:32.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.07:47:32.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.07:47:32.25#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:32.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:32.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:32.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:32.31#ibcon#enter wrdev, iclass 23, count 2 2006.280.07:47:32.31#ibcon#first serial, iclass 23, count 2 2006.280.07:47:32.31#ibcon#enter sib2, iclass 23, count 2 2006.280.07:47:32.31#ibcon#flushed, iclass 23, count 2 2006.280.07:47:32.31#ibcon#about to write, iclass 23, count 2 2006.280.07:47:32.31#ibcon#wrote, iclass 23, count 2 2006.280.07:47:32.31#ibcon#about to read 3, iclass 23, count 2 2006.280.07:47:32.33#ibcon#read 3, iclass 23, count 2 2006.280.07:47:32.33#ibcon#about to read 4, iclass 23, count 2 2006.280.07:47:32.33#ibcon#read 4, iclass 23, count 2 2006.280.07:47:32.33#ibcon#about to read 5, iclass 23, count 2 2006.280.07:47:32.33#ibcon#read 5, iclass 23, count 2 2006.280.07:47:32.33#ibcon#about to read 6, iclass 23, count 2 2006.280.07:47:32.33#ibcon#read 6, iclass 23, count 2 2006.280.07:47:32.33#ibcon#end of sib2, iclass 23, count 2 2006.280.07:47:32.33#ibcon#*mode == 0, iclass 23, count 2 2006.280.07:47:32.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.07:47:32.33#ibcon#[27=AT04-04\r\n] 2006.280.07:47:32.33#ibcon#*before write, iclass 23, count 2 2006.280.07:47:32.33#ibcon#enter sib2, iclass 23, count 2 2006.280.07:47:32.33#ibcon#flushed, iclass 23, count 2 2006.280.07:47:32.33#ibcon#about to write, iclass 23, count 2 2006.280.07:47:32.33#ibcon#wrote, iclass 23, count 2 2006.280.07:47:32.33#ibcon#about to read 3, iclass 23, count 2 2006.280.07:47:32.37#ibcon#read 3, iclass 23, count 2 2006.280.07:47:32.37#ibcon#about to read 4, iclass 23, count 2 2006.280.07:47:32.37#ibcon#read 4, iclass 23, count 2 2006.280.07:47:32.37#ibcon#about to read 5, iclass 23, count 2 2006.280.07:47:32.37#ibcon#read 5, iclass 23, count 2 2006.280.07:47:32.37#ibcon#about to read 6, iclass 23, count 2 2006.280.07:47:32.37#ibcon#read 6, iclass 23, count 2 2006.280.07:47:32.37#ibcon#end of sib2, iclass 23, count 2 2006.280.07:47:32.37#ibcon#*after write, iclass 23, count 2 2006.280.07:47:32.37#ibcon#*before return 0, iclass 23, count 2 2006.280.07:47:32.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:32.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.07:47:32.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.07:47:32.37#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:32.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:32.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:32.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:32.48#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:47:32.48#ibcon#first serial, iclass 23, count 0 2006.280.07:47:32.48#ibcon#enter sib2, iclass 23, count 0 2006.280.07:47:32.48#ibcon#flushed, iclass 23, count 0 2006.280.07:47:32.48#ibcon#about to write, iclass 23, count 0 2006.280.07:47:32.48#ibcon#wrote, iclass 23, count 0 2006.280.07:47:32.48#ibcon#about to read 3, iclass 23, count 0 2006.280.07:47:32.50#ibcon#read 3, iclass 23, count 0 2006.280.07:47:32.50#ibcon#about to read 4, iclass 23, count 0 2006.280.07:47:32.50#ibcon#read 4, iclass 23, count 0 2006.280.07:47:32.50#ibcon#about to read 5, iclass 23, count 0 2006.280.07:47:32.50#ibcon#read 5, iclass 23, count 0 2006.280.07:47:32.50#ibcon#about to read 6, iclass 23, count 0 2006.280.07:47:32.50#ibcon#read 6, iclass 23, count 0 2006.280.07:47:32.50#ibcon#end of sib2, iclass 23, count 0 2006.280.07:47:32.50#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:47:32.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:47:32.50#ibcon#[27=USB\r\n] 2006.280.07:47:32.50#ibcon#*before write, iclass 23, count 0 2006.280.07:47:32.50#ibcon#enter sib2, iclass 23, count 0 2006.280.07:47:32.50#ibcon#flushed, iclass 23, count 0 2006.280.07:47:32.50#ibcon#about to write, iclass 23, count 0 2006.280.07:47:32.50#ibcon#wrote, iclass 23, count 0 2006.280.07:47:32.50#ibcon#about to read 3, iclass 23, count 0 2006.280.07:47:32.53#ibcon#read 3, iclass 23, count 0 2006.280.07:47:32.53#ibcon#about to read 4, iclass 23, count 0 2006.280.07:47:32.53#ibcon#read 4, iclass 23, count 0 2006.280.07:47:32.53#ibcon#about to read 5, iclass 23, count 0 2006.280.07:47:32.53#ibcon#read 5, iclass 23, count 0 2006.280.07:47:32.53#ibcon#about to read 6, iclass 23, count 0 2006.280.07:47:32.53#ibcon#read 6, iclass 23, count 0 2006.280.07:47:32.53#ibcon#end of sib2, iclass 23, count 0 2006.280.07:47:32.53#ibcon#*after write, iclass 23, count 0 2006.280.07:47:32.53#ibcon#*before return 0, iclass 23, count 0 2006.280.07:47:32.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:32.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.07:47:32.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:47:32.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:47:32.53$vc4f8/vblo=5,744.99 2006.280.07:47:32.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:47:32.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:47:32.53#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:32.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:32.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:32.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:32.53#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:47:32.53#ibcon#first serial, iclass 25, count 0 2006.280.07:47:32.53#ibcon#enter sib2, iclass 25, count 0 2006.280.07:47:32.53#ibcon#flushed, iclass 25, count 0 2006.280.07:47:32.53#ibcon#about to write, iclass 25, count 0 2006.280.07:47:32.53#ibcon#wrote, iclass 25, count 0 2006.280.07:47:32.53#ibcon#about to read 3, iclass 25, count 0 2006.280.07:47:32.55#ibcon#read 3, iclass 25, count 0 2006.280.07:47:32.55#ibcon#about to read 4, iclass 25, count 0 2006.280.07:47:32.55#ibcon#read 4, iclass 25, count 0 2006.280.07:47:32.55#ibcon#about to read 5, iclass 25, count 0 2006.280.07:47:32.55#ibcon#read 5, iclass 25, count 0 2006.280.07:47:32.55#ibcon#about to read 6, iclass 25, count 0 2006.280.07:47:32.55#ibcon#read 6, iclass 25, count 0 2006.280.07:47:32.55#ibcon#end of sib2, iclass 25, count 0 2006.280.07:47:32.55#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:47:32.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:47:32.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:47:32.55#ibcon#*before write, iclass 25, count 0 2006.280.07:47:32.55#ibcon#enter sib2, iclass 25, count 0 2006.280.07:47:32.55#ibcon#flushed, iclass 25, count 0 2006.280.07:47:32.55#ibcon#about to write, iclass 25, count 0 2006.280.07:47:32.55#ibcon#wrote, iclass 25, count 0 2006.280.07:47:32.55#ibcon#about to read 3, iclass 25, count 0 2006.280.07:47:32.59#ibcon#read 3, iclass 25, count 0 2006.280.07:47:32.59#ibcon#about to read 4, iclass 25, count 0 2006.280.07:47:32.59#ibcon#read 4, iclass 25, count 0 2006.280.07:47:32.59#ibcon#about to read 5, iclass 25, count 0 2006.280.07:47:32.59#ibcon#read 5, iclass 25, count 0 2006.280.07:47:32.59#ibcon#about to read 6, iclass 25, count 0 2006.280.07:47:32.59#ibcon#read 6, iclass 25, count 0 2006.280.07:47:32.59#ibcon#end of sib2, iclass 25, count 0 2006.280.07:47:32.59#ibcon#*after write, iclass 25, count 0 2006.280.07:47:32.59#ibcon#*before return 0, iclass 25, count 0 2006.280.07:47:32.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:32.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:47:32.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:47:32.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:47:32.59$vc4f8/vb=5,4 2006.280.07:47:32.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:47:32.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:47:32.61#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:32.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:32.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:32.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:32.64#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:47:32.64#ibcon#first serial, iclass 27, count 2 2006.280.07:47:32.64#ibcon#enter sib2, iclass 27, count 2 2006.280.07:47:32.64#ibcon#flushed, iclass 27, count 2 2006.280.07:47:32.64#ibcon#about to write, iclass 27, count 2 2006.280.07:47:32.64#ibcon#wrote, iclass 27, count 2 2006.280.07:47:32.64#ibcon#about to read 3, iclass 27, count 2 2006.280.07:47:32.66#ibcon#read 3, iclass 27, count 2 2006.280.07:47:32.66#ibcon#about to read 4, iclass 27, count 2 2006.280.07:47:32.66#ibcon#read 4, iclass 27, count 2 2006.280.07:47:32.66#ibcon#about to read 5, iclass 27, count 2 2006.280.07:47:32.66#ibcon#read 5, iclass 27, count 2 2006.280.07:47:32.66#ibcon#about to read 6, iclass 27, count 2 2006.280.07:47:32.66#ibcon#read 6, iclass 27, count 2 2006.280.07:47:32.66#ibcon#end of sib2, iclass 27, count 2 2006.280.07:47:32.66#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:47:32.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:47:32.66#ibcon#[27=AT05-04\r\n] 2006.280.07:47:32.66#ibcon#*before write, iclass 27, count 2 2006.280.07:47:32.66#ibcon#enter sib2, iclass 27, count 2 2006.280.07:47:32.66#ibcon#flushed, iclass 27, count 2 2006.280.07:47:32.66#ibcon#about to write, iclass 27, count 2 2006.280.07:47:32.66#ibcon#wrote, iclass 27, count 2 2006.280.07:47:32.66#ibcon#about to read 3, iclass 27, count 2 2006.280.07:47:32.69#ibcon#read 3, iclass 27, count 2 2006.280.07:47:32.69#ibcon#about to read 4, iclass 27, count 2 2006.280.07:47:32.69#ibcon#read 4, iclass 27, count 2 2006.280.07:47:32.69#ibcon#about to read 5, iclass 27, count 2 2006.280.07:47:32.69#ibcon#read 5, iclass 27, count 2 2006.280.07:47:32.69#ibcon#about to read 6, iclass 27, count 2 2006.280.07:47:32.69#ibcon#read 6, iclass 27, count 2 2006.280.07:47:32.69#ibcon#end of sib2, iclass 27, count 2 2006.280.07:47:32.69#ibcon#*after write, iclass 27, count 2 2006.280.07:47:32.69#ibcon#*before return 0, iclass 27, count 2 2006.280.07:47:32.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:32.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:47:32.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:47:32.69#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:32.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:32.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:32.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:32.81#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:47:32.81#ibcon#first serial, iclass 27, count 0 2006.280.07:47:32.81#ibcon#enter sib2, iclass 27, count 0 2006.280.07:47:32.81#ibcon#flushed, iclass 27, count 0 2006.280.07:47:32.81#ibcon#about to write, iclass 27, count 0 2006.280.07:47:32.81#ibcon#wrote, iclass 27, count 0 2006.280.07:47:32.81#ibcon#about to read 3, iclass 27, count 0 2006.280.07:47:32.83#ibcon#read 3, iclass 27, count 0 2006.280.07:47:32.83#ibcon#about to read 4, iclass 27, count 0 2006.280.07:47:32.83#ibcon#read 4, iclass 27, count 0 2006.280.07:47:32.83#ibcon#about to read 5, iclass 27, count 0 2006.280.07:47:32.83#ibcon#read 5, iclass 27, count 0 2006.280.07:47:32.83#ibcon#about to read 6, iclass 27, count 0 2006.280.07:47:32.83#ibcon#read 6, iclass 27, count 0 2006.280.07:47:32.83#ibcon#end of sib2, iclass 27, count 0 2006.280.07:47:32.83#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:47:32.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:47:32.83#ibcon#[27=USB\r\n] 2006.280.07:47:32.83#ibcon#*before write, iclass 27, count 0 2006.280.07:47:32.83#ibcon#enter sib2, iclass 27, count 0 2006.280.07:47:32.83#ibcon#flushed, iclass 27, count 0 2006.280.07:47:32.83#ibcon#about to write, iclass 27, count 0 2006.280.07:47:32.83#ibcon#wrote, iclass 27, count 0 2006.280.07:47:32.83#ibcon#about to read 3, iclass 27, count 0 2006.280.07:47:32.86#ibcon#read 3, iclass 27, count 0 2006.280.07:47:32.86#ibcon#about to read 4, iclass 27, count 0 2006.280.07:47:32.86#ibcon#read 4, iclass 27, count 0 2006.280.07:47:32.86#ibcon#about to read 5, iclass 27, count 0 2006.280.07:47:32.86#ibcon#read 5, iclass 27, count 0 2006.280.07:47:32.86#ibcon#about to read 6, iclass 27, count 0 2006.280.07:47:32.86#ibcon#read 6, iclass 27, count 0 2006.280.07:47:32.86#ibcon#end of sib2, iclass 27, count 0 2006.280.07:47:32.86#ibcon#*after write, iclass 27, count 0 2006.280.07:47:32.86#ibcon#*before return 0, iclass 27, count 0 2006.280.07:47:32.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:32.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:47:32.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:47:32.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:47:32.86$vc4f8/vblo=6,752.99 2006.280.07:47:32.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:47:32.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:47:32.86#ibcon#ireg 17 cls_cnt 0 2006.280.07:47:32.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:32.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:32.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:32.86#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:47:32.86#ibcon#first serial, iclass 29, count 0 2006.280.07:47:32.86#ibcon#enter sib2, iclass 29, count 0 2006.280.07:47:32.86#ibcon#flushed, iclass 29, count 0 2006.280.07:47:32.86#ibcon#about to write, iclass 29, count 0 2006.280.07:47:32.86#ibcon#wrote, iclass 29, count 0 2006.280.07:47:32.86#ibcon#about to read 3, iclass 29, count 0 2006.280.07:47:32.88#ibcon#read 3, iclass 29, count 0 2006.280.07:47:32.88#ibcon#about to read 4, iclass 29, count 0 2006.280.07:47:32.88#ibcon#read 4, iclass 29, count 0 2006.280.07:47:32.88#ibcon#about to read 5, iclass 29, count 0 2006.280.07:47:32.88#ibcon#read 5, iclass 29, count 0 2006.280.07:47:32.88#ibcon#about to read 6, iclass 29, count 0 2006.280.07:47:32.88#ibcon#read 6, iclass 29, count 0 2006.280.07:47:32.88#ibcon#end of sib2, iclass 29, count 0 2006.280.07:47:32.88#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:47:32.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:47:32.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:47:32.88#ibcon#*before write, iclass 29, count 0 2006.280.07:47:32.88#ibcon#enter sib2, iclass 29, count 0 2006.280.07:47:32.88#ibcon#flushed, iclass 29, count 0 2006.280.07:47:32.88#ibcon#about to write, iclass 29, count 0 2006.280.07:47:32.88#ibcon#wrote, iclass 29, count 0 2006.280.07:47:32.88#ibcon#about to read 3, iclass 29, count 0 2006.280.07:47:32.92#ibcon#read 3, iclass 29, count 0 2006.280.07:47:32.92#ibcon#about to read 4, iclass 29, count 0 2006.280.07:47:32.92#ibcon#read 4, iclass 29, count 0 2006.280.07:47:32.92#ibcon#about to read 5, iclass 29, count 0 2006.280.07:47:32.92#ibcon#read 5, iclass 29, count 0 2006.280.07:47:32.92#ibcon#about to read 6, iclass 29, count 0 2006.280.07:47:32.92#ibcon#read 6, iclass 29, count 0 2006.280.07:47:32.92#ibcon#end of sib2, iclass 29, count 0 2006.280.07:47:32.92#ibcon#*after write, iclass 29, count 0 2006.280.07:47:32.92#ibcon#*before return 0, iclass 29, count 0 2006.280.07:47:32.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:32.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:47:32.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:47:32.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:47:32.92$vc4f8/vb=6,4 2006.280.07:47:32.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:47:32.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:47:32.92#ibcon#ireg 11 cls_cnt 2 2006.280.07:47:32.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:32.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:32.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:32.98#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:47:32.98#ibcon#first serial, iclass 31, count 2 2006.280.07:47:32.98#ibcon#enter sib2, iclass 31, count 2 2006.280.07:47:32.98#ibcon#flushed, iclass 31, count 2 2006.280.07:47:32.98#ibcon#about to write, iclass 31, count 2 2006.280.07:47:32.98#ibcon#wrote, iclass 31, count 2 2006.280.07:47:32.98#ibcon#about to read 3, iclass 31, count 2 2006.280.07:47:33.00#ibcon#read 3, iclass 31, count 2 2006.280.07:47:33.00#ibcon#about to read 4, iclass 31, count 2 2006.280.07:47:33.00#ibcon#read 4, iclass 31, count 2 2006.280.07:47:33.00#ibcon#about to read 5, iclass 31, count 2 2006.280.07:47:33.00#ibcon#read 5, iclass 31, count 2 2006.280.07:47:33.00#ibcon#about to read 6, iclass 31, count 2 2006.280.07:47:33.00#ibcon#read 6, iclass 31, count 2 2006.280.07:47:33.00#ibcon#end of sib2, iclass 31, count 2 2006.280.07:47:33.00#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:47:33.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:47:33.00#ibcon#[27=AT06-04\r\n] 2006.280.07:47:33.00#ibcon#*before write, iclass 31, count 2 2006.280.07:47:33.00#ibcon#enter sib2, iclass 31, count 2 2006.280.07:47:33.00#ibcon#flushed, iclass 31, count 2 2006.280.07:47:33.00#ibcon#about to write, iclass 31, count 2 2006.280.07:47:33.00#ibcon#wrote, iclass 31, count 2 2006.280.07:47:33.00#ibcon#about to read 3, iclass 31, count 2 2006.280.07:47:33.03#abcon#<5=/15 2.9 5.8 21.34 59 986.9\r\n> 2006.280.07:47:33.03#ibcon#read 3, iclass 31, count 2 2006.280.07:47:33.03#ibcon#about to read 4, iclass 31, count 2 2006.280.07:47:33.03#ibcon#read 4, iclass 31, count 2 2006.280.07:47:33.03#ibcon#about to read 5, iclass 31, count 2 2006.280.07:47:33.03#ibcon#read 5, iclass 31, count 2 2006.280.07:47:33.03#ibcon#about to read 6, iclass 31, count 2 2006.280.07:47:33.03#ibcon#read 6, iclass 31, count 2 2006.280.07:47:33.03#ibcon#end of sib2, iclass 31, count 2 2006.280.07:47:33.03#ibcon#*after write, iclass 31, count 2 2006.280.07:47:33.03#ibcon#*before return 0, iclass 31, count 2 2006.280.07:47:33.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:33.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:47:33.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:47:33.03#ibcon#ireg 7 cls_cnt 0 2006.280.07:47:33.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:33.05#abcon#{5=INTERFACE CLEAR} 2006.280.07:47:33.11#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:47:33.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:33.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:33.15#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:47:33.15#ibcon#first serial, iclass 31, count 0 2006.280.07:47:33.15#ibcon#enter sib2, iclass 31, count 0 2006.280.07:47:33.15#ibcon#flushed, iclass 31, count 0 2006.280.07:47:33.15#ibcon#about to write, iclass 31, count 0 2006.280.07:47:33.15#ibcon#wrote, iclass 31, count 0 2006.280.07:47:33.15#ibcon#about to read 3, iclass 31, count 0 2006.280.07:47:33.18#ibcon#read 3, iclass 31, count 0 2006.280.07:47:33.18#ibcon#about to read 4, iclass 31, count 0 2006.280.07:47:33.18#ibcon#read 4, iclass 31, count 0 2006.280.07:47:33.18#ibcon#about to read 5, iclass 31, count 0 2006.280.07:47:33.18#ibcon#read 5, iclass 31, count 0 2006.280.07:47:33.18#ibcon#about to read 6, iclass 31, count 0 2006.280.07:47:33.18#ibcon#read 6, iclass 31, count 0 2006.280.07:47:33.18#ibcon#end of sib2, iclass 31, count 0 2006.280.07:47:33.18#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:47:33.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:47:33.18#ibcon#[27=USB\r\n] 2006.280.07:47:33.18#ibcon#*before write, iclass 31, count 0 2006.280.07:47:33.18#ibcon#enter sib2, iclass 31, count 0 2006.280.07:47:33.18#ibcon#flushed, iclass 31, count 0 2006.280.07:47:33.18#ibcon#about to write, iclass 31, count 0 2006.280.07:47:33.18#ibcon#wrote, iclass 31, count 0 2006.280.07:47:33.18#ibcon#about to read 3, iclass 31, count 0 2006.280.07:47:33.20#ibcon#read 3, iclass 31, count 0 2006.280.07:47:33.20#ibcon#about to read 4, iclass 31, count 0 2006.280.07:47:33.20#ibcon#read 4, iclass 31, count 0 2006.280.07:47:33.20#ibcon#about to read 5, iclass 31, count 0 2006.280.07:47:33.20#ibcon#read 5, iclass 31, count 0 2006.280.07:47:33.20#ibcon#about to read 6, iclass 31, count 0 2006.280.07:47:33.20#ibcon#read 6, iclass 31, count 0 2006.280.07:47:33.20#ibcon#end of sib2, iclass 31, count 0 2006.280.07:47:33.20#ibcon#*after write, iclass 31, count 0 2006.280.07:47:33.20#ibcon#*before return 0, iclass 31, count 0 2006.280.07:47:33.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:33.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:47:33.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:47:33.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:47:33.20$vc4f8/vabw=wide 2006.280.07:47:33.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:47:33.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:47:33.20#ibcon#ireg 8 cls_cnt 0 2006.280.07:47:33.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:33.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:33.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:33.20#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:47:33.20#ibcon#first serial, iclass 37, count 0 2006.280.07:47:33.20#ibcon#enter sib2, iclass 37, count 0 2006.280.07:47:33.20#ibcon#flushed, iclass 37, count 0 2006.280.07:47:33.20#ibcon#about to write, iclass 37, count 0 2006.280.07:47:33.20#ibcon#wrote, iclass 37, count 0 2006.280.07:47:33.20#ibcon#about to read 3, iclass 37, count 0 2006.280.07:47:33.22#ibcon#read 3, iclass 37, count 0 2006.280.07:47:33.23#ibcon#about to read 4, iclass 37, count 0 2006.280.07:47:33.23#ibcon#read 4, iclass 37, count 0 2006.280.07:47:33.23#ibcon#about to read 5, iclass 37, count 0 2006.280.07:47:33.23#ibcon#read 5, iclass 37, count 0 2006.280.07:47:33.23#ibcon#about to read 6, iclass 37, count 0 2006.280.07:47:33.23#ibcon#read 6, iclass 37, count 0 2006.280.07:47:33.23#ibcon#end of sib2, iclass 37, count 0 2006.280.07:47:33.23#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:47:33.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:47:33.23#ibcon#[25=BW32\r\n] 2006.280.07:47:33.23#ibcon#*before write, iclass 37, count 0 2006.280.07:47:33.23#ibcon#enter sib2, iclass 37, count 0 2006.280.07:47:33.23#ibcon#flushed, iclass 37, count 0 2006.280.07:47:33.23#ibcon#about to write, iclass 37, count 0 2006.280.07:47:33.23#ibcon#wrote, iclass 37, count 0 2006.280.07:47:33.23#ibcon#about to read 3, iclass 37, count 0 2006.280.07:47:33.26#ibcon#read 3, iclass 37, count 0 2006.280.07:47:33.26#ibcon#about to read 4, iclass 37, count 0 2006.280.07:47:33.26#ibcon#read 4, iclass 37, count 0 2006.280.07:47:33.26#ibcon#about to read 5, iclass 37, count 0 2006.280.07:47:33.26#ibcon#read 5, iclass 37, count 0 2006.280.07:47:33.26#ibcon#about to read 6, iclass 37, count 0 2006.280.07:47:33.26#ibcon#read 6, iclass 37, count 0 2006.280.07:47:33.26#ibcon#end of sib2, iclass 37, count 0 2006.280.07:47:33.26#ibcon#*after write, iclass 37, count 0 2006.280.07:47:33.26#ibcon#*before return 0, iclass 37, count 0 2006.280.07:47:33.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:33.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:47:33.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:47:33.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:47:33.26$vc4f8/vbbw=wide 2006.280.07:47:33.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:47:33.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:47:33.26#ibcon#ireg 8 cls_cnt 0 2006.280.07:47:33.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:47:33.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:47:33.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:47:33.32#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:47:33.32#ibcon#first serial, iclass 39, count 0 2006.280.07:47:33.32#ibcon#enter sib2, iclass 39, count 0 2006.280.07:47:33.32#ibcon#flushed, iclass 39, count 0 2006.280.07:47:33.32#ibcon#about to write, iclass 39, count 0 2006.280.07:47:33.32#ibcon#wrote, iclass 39, count 0 2006.280.07:47:33.32#ibcon#about to read 3, iclass 39, count 0 2006.280.07:47:33.34#ibcon#read 3, iclass 39, count 0 2006.280.07:47:33.34#ibcon#about to read 4, iclass 39, count 0 2006.280.07:47:33.34#ibcon#read 4, iclass 39, count 0 2006.280.07:47:33.34#ibcon#about to read 5, iclass 39, count 0 2006.280.07:47:33.34#ibcon#read 5, iclass 39, count 0 2006.280.07:47:33.34#ibcon#about to read 6, iclass 39, count 0 2006.280.07:47:33.34#ibcon#read 6, iclass 39, count 0 2006.280.07:47:33.34#ibcon#end of sib2, iclass 39, count 0 2006.280.07:47:33.34#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:47:33.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:47:33.34#ibcon#[27=BW32\r\n] 2006.280.07:47:33.34#ibcon#*before write, iclass 39, count 0 2006.280.07:47:33.34#ibcon#enter sib2, iclass 39, count 0 2006.280.07:47:33.34#ibcon#flushed, iclass 39, count 0 2006.280.07:47:33.34#ibcon#about to write, iclass 39, count 0 2006.280.07:47:33.34#ibcon#wrote, iclass 39, count 0 2006.280.07:47:33.34#ibcon#about to read 3, iclass 39, count 0 2006.280.07:47:33.37#ibcon#read 3, iclass 39, count 0 2006.280.07:47:33.37#ibcon#about to read 4, iclass 39, count 0 2006.280.07:47:33.37#ibcon#read 4, iclass 39, count 0 2006.280.07:47:33.37#ibcon#about to read 5, iclass 39, count 0 2006.280.07:47:33.37#ibcon#read 5, iclass 39, count 0 2006.280.07:47:33.37#ibcon#about to read 6, iclass 39, count 0 2006.280.07:47:33.37#ibcon#read 6, iclass 39, count 0 2006.280.07:47:33.37#ibcon#end of sib2, iclass 39, count 0 2006.280.07:47:33.37#ibcon#*after write, iclass 39, count 0 2006.280.07:47:33.37#ibcon#*before return 0, iclass 39, count 0 2006.280.07:47:33.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:47:33.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:47:33.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:47:33.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:47:33.37$4f8m12a/ifd4f 2006.280.07:47:33.37$ifd4f/lo= 2006.280.07:47:33.37$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:47:33.37$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:47:33.37$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:47:33.37$ifd4f/patch= 2006.280.07:47:33.37$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:47:33.37$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:47:33.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:47:33.38$4f8m12a/"form=m,16.000,1:2 2006.280.07:47:33.38$4f8m12a/"tpicd 2006.280.07:47:33.38$4f8m12a/echo=off 2006.280.07:47:33.38$4f8m12a/xlog=off 2006.280.07:47:33.38:!2006.280.07:48:00 2006.280.07:47:44.14#trakl#Source acquired 2006.280.07:47:45.14#flagr#flagr/antenna,acquired 2006.280.07:48:00.01:preob 2006.280.07:48:01.14/onsource/TRACKING 2006.280.07:48:01.14:!2006.280.07:48:10 2006.280.07:48:10.00:data_valid=on 2006.280.07:48:10.00:midob 2006.280.07:48:10.14/onsource/TRACKING 2006.280.07:48:10.14/wx/21.32,986.9,59 2006.280.07:48:10.23/cable/+6.4833E-03 2006.280.07:48:11.32/va/01,07,usb,yes,34,36 2006.280.07:48:11.32/va/02,06,usb,yes,32,33 2006.280.07:48:11.32/va/03,06,usb,yes,30,30 2006.280.07:48:11.32/va/04,06,usb,yes,33,36 2006.280.07:48:11.32/va/05,07,usb,yes,30,32 2006.280.07:48:11.32/va/06,06,usb,yes,29,29 2006.280.07:48:11.32/va/07,06,usb,yes,30,30 2006.280.07:48:11.32/va/08,06,usb,yes,32,32 2006.280.07:48:11.55/valo/01,532.99,yes,locked 2006.280.07:48:11.55/valo/02,572.99,yes,locked 2006.280.07:48:11.55/valo/03,672.99,yes,locked 2006.280.07:48:11.55/valo/04,832.99,yes,locked 2006.280.07:48:11.55/valo/05,652.99,yes,locked 2006.280.07:48:11.55/valo/06,772.99,yes,locked 2006.280.07:48:11.55/valo/07,832.99,yes,locked 2006.280.07:48:11.55/valo/08,852.99,yes,locked 2006.280.07:48:12.64/vb/01,04,usb,yes,31,30 2006.280.07:48:12.64/vb/02,05,usb,yes,29,31 2006.280.07:48:12.64/vb/03,04,usb,yes,30,33 2006.280.07:48:12.64/vb/04,04,usb,yes,30,31 2006.280.07:48:12.64/vb/05,04,usb,yes,28,33 2006.280.07:48:12.64/vb/06,04,usb,yes,29,32 2006.280.07:48:12.64/vb/07,04,usb,yes,32,32 2006.280.07:48:12.64/vb/08,04,usb,yes,29,33 2006.280.07:48:12.87/vblo/01,632.99,yes,locked 2006.280.07:48:12.87/vblo/02,640.99,yes,locked 2006.280.07:48:12.87/vblo/03,656.99,yes,locked 2006.280.07:48:12.87/vblo/04,712.99,yes,locked 2006.280.07:48:12.87/vblo/05,744.99,yes,locked 2006.280.07:48:12.87/vblo/06,752.99,yes,locked 2006.280.07:48:12.87/vblo/07,734.99,yes,locked 2006.280.07:48:12.87/vblo/08,744.99,yes,locked 2006.280.07:48:13.02/vabw/8 2006.280.07:48:13.17/vbbw/8 2006.280.07:48:13.26/xfe/off,on,12.2 2006.280.07:48:13.63/ifatt/23,28,28,28 2006.280.07:48:14.07/fmout-gps/S +3.13E-07 2006.280.07:48:14.10:!2006.280.07:49:10 2006.280.07:49:10.01:data_valid=off 2006.280.07:49:10.02:postob 2006.280.07:49:10.06/cable/+6.4837E-03 2006.280.07:49:10.07/wx/21.29,986.9,59 2006.280.07:49:11.07/fmout-gps/S +3.14E-07 2006.280.07:49:11.08:scan_name=280-0750,k06280,60 2006.280.07:49:11.08:source=1538+149,154049.49,144745.9,2000.0,ccw 2006.280.07:49:11.14#flagr#flagr/antenna,new-source 2006.280.07:49:12.14:checkk5 2006.280.07:49:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:49:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:49:13.37/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:49:13.75/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:49:14.16/chk_obsdata//k5ts1/T2800748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:49:14.53/chk_obsdata//k5ts2/T2800748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:49:14.91/chk_obsdata//k5ts3/T2800748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:49:15.33/chk_obsdata//k5ts4/T2800748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:49:16.12/k5log//k5ts1_log_newline 2006.280.07:49:16.83/k5log//k5ts2_log_newline 2006.280.07:49:17.60/k5log//k5ts3_log_newline 2006.280.07:49:18.33/k5log//k5ts4_log_newline 2006.280.07:49:18.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:49:18.35:4f8m12a=1 2006.280.07:49:18.35$4f8m12a/echo=on 2006.280.07:49:18.35$4f8m12a/pcalon 2006.280.07:49:18.35$pcalon/"no phase cal control is implemented here 2006.280.07:49:18.35$4f8m12a/"tpicd=stop 2006.280.07:49:18.35$4f8m12a/vc4f8 2006.280.07:49:18.35$vc4f8/valo=1,532.99 2006.280.07:49:18.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:49:18.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:49:18.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:18.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:18.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:18.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:18.36#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:49:18.36#ibcon#first serial, iclass 10, count 0 2006.280.07:49:18.36#ibcon#enter sib2, iclass 10, count 0 2006.280.07:49:18.36#ibcon#flushed, iclass 10, count 0 2006.280.07:49:18.36#ibcon#about to write, iclass 10, count 0 2006.280.07:49:18.36#ibcon#wrote, iclass 10, count 0 2006.280.07:49:18.36#ibcon#about to read 3, iclass 10, count 0 2006.280.07:49:18.38#ibcon#read 3, iclass 10, count 0 2006.280.07:49:18.38#ibcon#about to read 4, iclass 10, count 0 2006.280.07:49:18.38#ibcon#read 4, iclass 10, count 0 2006.280.07:49:18.38#ibcon#about to read 5, iclass 10, count 0 2006.280.07:49:18.38#ibcon#read 5, iclass 10, count 0 2006.280.07:49:18.38#ibcon#about to read 6, iclass 10, count 0 2006.280.07:49:18.38#ibcon#read 6, iclass 10, count 0 2006.280.07:49:18.38#ibcon#end of sib2, iclass 10, count 0 2006.280.07:49:18.38#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:49:18.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:49:18.38#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:49:18.38#ibcon#*before write, iclass 10, count 0 2006.280.07:49:18.38#ibcon#enter sib2, iclass 10, count 0 2006.280.07:49:18.38#ibcon#flushed, iclass 10, count 0 2006.280.07:49:18.38#ibcon#about to write, iclass 10, count 0 2006.280.07:49:18.38#ibcon#wrote, iclass 10, count 0 2006.280.07:49:18.38#ibcon#about to read 3, iclass 10, count 0 2006.280.07:49:18.43#ibcon#read 3, iclass 10, count 0 2006.280.07:49:18.43#ibcon#about to read 4, iclass 10, count 0 2006.280.07:49:18.43#ibcon#read 4, iclass 10, count 0 2006.280.07:49:18.43#ibcon#about to read 5, iclass 10, count 0 2006.280.07:49:18.43#ibcon#read 5, iclass 10, count 0 2006.280.07:49:18.43#ibcon#about to read 6, iclass 10, count 0 2006.280.07:49:18.43#ibcon#read 6, iclass 10, count 0 2006.280.07:49:18.43#ibcon#end of sib2, iclass 10, count 0 2006.280.07:49:18.43#ibcon#*after write, iclass 10, count 0 2006.280.07:49:18.43#ibcon#*before return 0, iclass 10, count 0 2006.280.07:49:18.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:18.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:18.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:49:18.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:49:18.43$vc4f8/va=1,7 2006.280.07:49:18.43#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:49:18.43#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:49:18.43#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:18.43#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:18.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:18.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:18.43#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:49:18.43#ibcon#first serial, iclass 12, count 2 2006.280.07:49:18.43#ibcon#enter sib2, iclass 12, count 2 2006.280.07:49:18.43#ibcon#flushed, iclass 12, count 2 2006.280.07:49:18.43#ibcon#about to write, iclass 12, count 2 2006.280.07:49:18.43#ibcon#wrote, iclass 12, count 2 2006.280.07:49:18.43#ibcon#about to read 3, iclass 12, count 2 2006.280.07:49:18.45#ibcon#read 3, iclass 12, count 2 2006.280.07:49:18.45#ibcon#about to read 4, iclass 12, count 2 2006.280.07:49:18.45#ibcon#read 4, iclass 12, count 2 2006.280.07:49:18.46#ibcon#about to read 5, iclass 12, count 2 2006.280.07:49:18.46#ibcon#read 5, iclass 12, count 2 2006.280.07:49:18.46#ibcon#about to read 6, iclass 12, count 2 2006.280.07:49:18.46#ibcon#read 6, iclass 12, count 2 2006.280.07:49:18.46#ibcon#end of sib2, iclass 12, count 2 2006.280.07:49:18.46#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:49:18.46#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:49:18.46#ibcon#[25=AT01-07\r\n] 2006.280.07:49:18.46#ibcon#*before write, iclass 12, count 2 2006.280.07:49:18.46#ibcon#enter sib2, iclass 12, count 2 2006.280.07:49:18.46#ibcon#flushed, iclass 12, count 2 2006.280.07:49:18.46#ibcon#about to write, iclass 12, count 2 2006.280.07:49:18.46#ibcon#wrote, iclass 12, count 2 2006.280.07:49:18.46#ibcon#about to read 3, iclass 12, count 2 2006.280.07:49:18.49#ibcon#read 3, iclass 12, count 2 2006.280.07:49:18.49#ibcon#about to read 4, iclass 12, count 2 2006.280.07:49:18.49#ibcon#read 4, iclass 12, count 2 2006.280.07:49:18.49#ibcon#about to read 5, iclass 12, count 2 2006.280.07:49:18.49#ibcon#read 5, iclass 12, count 2 2006.280.07:49:18.49#ibcon#about to read 6, iclass 12, count 2 2006.280.07:49:18.49#ibcon#read 6, iclass 12, count 2 2006.280.07:49:18.49#ibcon#end of sib2, iclass 12, count 2 2006.280.07:49:18.49#ibcon#*after write, iclass 12, count 2 2006.280.07:49:18.49#ibcon#*before return 0, iclass 12, count 2 2006.280.07:49:18.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:18.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:18.49#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:49:18.49#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:18.49#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:18.62#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:18.62#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:18.62#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:49:18.62#ibcon#first serial, iclass 12, count 0 2006.280.07:49:18.62#ibcon#enter sib2, iclass 12, count 0 2006.280.07:49:18.62#ibcon#flushed, iclass 12, count 0 2006.280.07:49:18.62#ibcon#about to write, iclass 12, count 0 2006.280.07:49:18.62#ibcon#wrote, iclass 12, count 0 2006.280.07:49:18.62#ibcon#about to read 3, iclass 12, count 0 2006.280.07:49:18.63#ibcon#read 3, iclass 12, count 0 2006.280.07:49:18.63#ibcon#about to read 4, iclass 12, count 0 2006.280.07:49:18.63#ibcon#read 4, iclass 12, count 0 2006.280.07:49:18.63#ibcon#about to read 5, iclass 12, count 0 2006.280.07:49:18.63#ibcon#read 5, iclass 12, count 0 2006.280.07:49:18.63#ibcon#about to read 6, iclass 12, count 0 2006.280.07:49:18.63#ibcon#read 6, iclass 12, count 0 2006.280.07:49:18.63#ibcon#end of sib2, iclass 12, count 0 2006.280.07:49:18.63#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:49:18.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:49:18.63#ibcon#[25=USB\r\n] 2006.280.07:49:18.63#ibcon#*before write, iclass 12, count 0 2006.280.07:49:18.63#ibcon#enter sib2, iclass 12, count 0 2006.280.07:49:18.63#ibcon#flushed, iclass 12, count 0 2006.280.07:49:18.63#ibcon#about to write, iclass 12, count 0 2006.280.07:49:18.63#ibcon#wrote, iclass 12, count 0 2006.280.07:49:18.63#ibcon#about to read 3, iclass 12, count 0 2006.280.07:49:18.66#ibcon#read 3, iclass 12, count 0 2006.280.07:49:18.66#ibcon#about to read 4, iclass 12, count 0 2006.280.07:49:18.66#ibcon#read 4, iclass 12, count 0 2006.280.07:49:18.66#ibcon#about to read 5, iclass 12, count 0 2006.280.07:49:18.66#ibcon#read 5, iclass 12, count 0 2006.280.07:49:18.66#ibcon#about to read 6, iclass 12, count 0 2006.280.07:49:18.66#ibcon#read 6, iclass 12, count 0 2006.280.07:49:18.66#ibcon#end of sib2, iclass 12, count 0 2006.280.07:49:18.66#ibcon#*after write, iclass 12, count 0 2006.280.07:49:18.66#ibcon#*before return 0, iclass 12, count 0 2006.280.07:49:18.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:18.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:18.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:49:18.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:49:18.66$vc4f8/valo=2,572.99 2006.280.07:49:18.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:49:18.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:49:18.66#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:18.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:18.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:18.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:18.66#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:49:18.66#ibcon#first serial, iclass 14, count 0 2006.280.07:49:18.66#ibcon#enter sib2, iclass 14, count 0 2006.280.07:49:18.66#ibcon#flushed, iclass 14, count 0 2006.280.07:49:18.66#ibcon#about to write, iclass 14, count 0 2006.280.07:49:18.66#ibcon#wrote, iclass 14, count 0 2006.280.07:49:18.66#ibcon#about to read 3, iclass 14, count 0 2006.280.07:49:18.68#ibcon#read 3, iclass 14, count 0 2006.280.07:49:18.68#ibcon#about to read 4, iclass 14, count 0 2006.280.07:49:18.68#ibcon#read 4, iclass 14, count 0 2006.280.07:49:18.68#ibcon#about to read 5, iclass 14, count 0 2006.280.07:49:18.68#ibcon#read 5, iclass 14, count 0 2006.280.07:49:18.68#ibcon#about to read 6, iclass 14, count 0 2006.280.07:49:18.68#ibcon#read 6, iclass 14, count 0 2006.280.07:49:18.68#ibcon#end of sib2, iclass 14, count 0 2006.280.07:49:18.68#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:49:18.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:49:18.68#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:49:18.68#ibcon#*before write, iclass 14, count 0 2006.280.07:49:18.68#ibcon#enter sib2, iclass 14, count 0 2006.280.07:49:18.68#ibcon#flushed, iclass 14, count 0 2006.280.07:49:18.68#ibcon#about to write, iclass 14, count 0 2006.280.07:49:18.68#ibcon#wrote, iclass 14, count 0 2006.280.07:49:18.68#ibcon#about to read 3, iclass 14, count 0 2006.280.07:49:18.73#ibcon#read 3, iclass 14, count 0 2006.280.07:49:18.73#ibcon#about to read 4, iclass 14, count 0 2006.280.07:49:18.73#ibcon#read 4, iclass 14, count 0 2006.280.07:49:18.73#ibcon#about to read 5, iclass 14, count 0 2006.280.07:49:18.73#ibcon#read 5, iclass 14, count 0 2006.280.07:49:18.73#ibcon#about to read 6, iclass 14, count 0 2006.280.07:49:18.73#ibcon#read 6, iclass 14, count 0 2006.280.07:49:18.73#ibcon#end of sib2, iclass 14, count 0 2006.280.07:49:18.73#ibcon#*after write, iclass 14, count 0 2006.280.07:49:18.73#ibcon#*before return 0, iclass 14, count 0 2006.280.07:49:18.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:18.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:18.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:49:18.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:49:18.73$vc4f8/va=2,6 2006.280.07:49:18.73#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:49:18.73#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:49:18.73#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:18.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:18.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:18.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:18.77#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:49:18.77#ibcon#first serial, iclass 16, count 2 2006.280.07:49:18.77#ibcon#enter sib2, iclass 16, count 2 2006.280.07:49:18.77#ibcon#flushed, iclass 16, count 2 2006.280.07:49:18.77#ibcon#about to write, iclass 16, count 2 2006.280.07:49:18.77#ibcon#wrote, iclass 16, count 2 2006.280.07:49:18.77#ibcon#about to read 3, iclass 16, count 2 2006.280.07:49:18.79#ibcon#read 3, iclass 16, count 2 2006.280.07:49:18.79#ibcon#about to read 4, iclass 16, count 2 2006.280.07:49:18.79#ibcon#read 4, iclass 16, count 2 2006.280.07:49:18.79#ibcon#about to read 5, iclass 16, count 2 2006.280.07:49:18.79#ibcon#read 5, iclass 16, count 2 2006.280.07:49:18.79#ibcon#about to read 6, iclass 16, count 2 2006.280.07:49:18.79#ibcon#read 6, iclass 16, count 2 2006.280.07:49:18.79#ibcon#end of sib2, iclass 16, count 2 2006.280.07:49:18.79#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:49:18.79#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:49:18.79#ibcon#[25=AT02-06\r\n] 2006.280.07:49:18.79#ibcon#*before write, iclass 16, count 2 2006.280.07:49:18.79#ibcon#enter sib2, iclass 16, count 2 2006.280.07:49:18.79#ibcon#flushed, iclass 16, count 2 2006.280.07:49:18.79#ibcon#about to write, iclass 16, count 2 2006.280.07:49:18.79#ibcon#wrote, iclass 16, count 2 2006.280.07:49:18.79#ibcon#about to read 3, iclass 16, count 2 2006.280.07:49:18.82#ibcon#read 3, iclass 16, count 2 2006.280.07:49:18.82#ibcon#about to read 4, iclass 16, count 2 2006.280.07:49:18.82#ibcon#read 4, iclass 16, count 2 2006.280.07:49:18.82#ibcon#about to read 5, iclass 16, count 2 2006.280.07:49:18.82#ibcon#read 5, iclass 16, count 2 2006.280.07:49:18.82#ibcon#about to read 6, iclass 16, count 2 2006.280.07:49:18.82#ibcon#read 6, iclass 16, count 2 2006.280.07:49:18.82#ibcon#end of sib2, iclass 16, count 2 2006.280.07:49:18.82#ibcon#*after write, iclass 16, count 2 2006.280.07:49:18.82#ibcon#*before return 0, iclass 16, count 2 2006.280.07:49:18.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:18.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:18.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:49:18.82#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:18.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:18.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:18.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:18.94#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:49:18.94#ibcon#first serial, iclass 16, count 0 2006.280.07:49:18.94#ibcon#enter sib2, iclass 16, count 0 2006.280.07:49:18.94#ibcon#flushed, iclass 16, count 0 2006.280.07:49:18.94#ibcon#about to write, iclass 16, count 0 2006.280.07:49:18.94#ibcon#wrote, iclass 16, count 0 2006.280.07:49:18.94#ibcon#about to read 3, iclass 16, count 0 2006.280.07:49:18.96#ibcon#read 3, iclass 16, count 0 2006.280.07:49:18.96#ibcon#about to read 4, iclass 16, count 0 2006.280.07:49:18.96#ibcon#read 4, iclass 16, count 0 2006.280.07:49:18.96#ibcon#about to read 5, iclass 16, count 0 2006.280.07:49:18.96#ibcon#read 5, iclass 16, count 0 2006.280.07:49:18.96#ibcon#about to read 6, iclass 16, count 0 2006.280.07:49:18.96#ibcon#read 6, iclass 16, count 0 2006.280.07:49:18.96#ibcon#end of sib2, iclass 16, count 0 2006.280.07:49:18.96#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:49:18.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:49:18.96#ibcon#[25=USB\r\n] 2006.280.07:49:18.96#ibcon#*before write, iclass 16, count 0 2006.280.07:49:18.96#ibcon#enter sib2, iclass 16, count 0 2006.280.07:49:18.96#ibcon#flushed, iclass 16, count 0 2006.280.07:49:18.96#ibcon#about to write, iclass 16, count 0 2006.280.07:49:18.96#ibcon#wrote, iclass 16, count 0 2006.280.07:49:18.96#ibcon#about to read 3, iclass 16, count 0 2006.280.07:49:18.99#ibcon#read 3, iclass 16, count 0 2006.280.07:49:18.99#ibcon#about to read 4, iclass 16, count 0 2006.280.07:49:18.99#ibcon#read 4, iclass 16, count 0 2006.280.07:49:18.99#ibcon#about to read 5, iclass 16, count 0 2006.280.07:49:18.99#ibcon#read 5, iclass 16, count 0 2006.280.07:49:18.99#ibcon#about to read 6, iclass 16, count 0 2006.280.07:49:18.99#ibcon#read 6, iclass 16, count 0 2006.280.07:49:18.99#ibcon#end of sib2, iclass 16, count 0 2006.280.07:49:18.99#ibcon#*after write, iclass 16, count 0 2006.280.07:49:18.99#ibcon#*before return 0, iclass 16, count 0 2006.280.07:49:18.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:18.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:18.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:49:18.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:49:18.99$vc4f8/valo=3,672.99 2006.280.07:49:18.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:49:18.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:49:18.99#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:18.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:18.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:18.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:18.99#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:49:18.99#ibcon#first serial, iclass 18, count 0 2006.280.07:49:18.99#ibcon#enter sib2, iclass 18, count 0 2006.280.07:49:18.99#ibcon#flushed, iclass 18, count 0 2006.280.07:49:18.99#ibcon#about to write, iclass 18, count 0 2006.280.07:49:18.99#ibcon#wrote, iclass 18, count 0 2006.280.07:49:18.99#ibcon#about to read 3, iclass 18, count 0 2006.280.07:49:19.01#ibcon#read 3, iclass 18, count 0 2006.280.07:49:19.01#ibcon#about to read 4, iclass 18, count 0 2006.280.07:49:19.01#ibcon#read 4, iclass 18, count 0 2006.280.07:49:19.01#ibcon#about to read 5, iclass 18, count 0 2006.280.07:49:19.01#ibcon#read 5, iclass 18, count 0 2006.280.07:49:19.01#ibcon#about to read 6, iclass 18, count 0 2006.280.07:49:19.01#ibcon#read 6, iclass 18, count 0 2006.280.07:49:19.01#ibcon#end of sib2, iclass 18, count 0 2006.280.07:49:19.01#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:49:19.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:49:19.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:49:19.01#ibcon#*before write, iclass 18, count 0 2006.280.07:49:19.01#ibcon#enter sib2, iclass 18, count 0 2006.280.07:49:19.01#ibcon#flushed, iclass 18, count 0 2006.280.07:49:19.01#ibcon#about to write, iclass 18, count 0 2006.280.07:49:19.01#ibcon#wrote, iclass 18, count 0 2006.280.07:49:19.01#ibcon#about to read 3, iclass 18, count 0 2006.280.07:49:19.05#ibcon#read 3, iclass 18, count 0 2006.280.07:49:19.05#ibcon#about to read 4, iclass 18, count 0 2006.280.07:49:19.05#ibcon#read 4, iclass 18, count 0 2006.280.07:49:19.05#ibcon#about to read 5, iclass 18, count 0 2006.280.07:49:19.05#ibcon#read 5, iclass 18, count 0 2006.280.07:49:19.05#ibcon#about to read 6, iclass 18, count 0 2006.280.07:49:19.05#ibcon#read 6, iclass 18, count 0 2006.280.07:49:19.05#ibcon#end of sib2, iclass 18, count 0 2006.280.07:49:19.05#ibcon#*after write, iclass 18, count 0 2006.280.07:49:19.05#ibcon#*before return 0, iclass 18, count 0 2006.280.07:49:19.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:19.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:19.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:49:19.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:49:19.05$vc4f8/va=3,6 2006.280.07:49:19.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:49:19.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:49:19.05#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:19.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:19.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:19.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:19.11#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:49:19.11#ibcon#first serial, iclass 20, count 2 2006.280.07:49:19.11#ibcon#enter sib2, iclass 20, count 2 2006.280.07:49:19.11#ibcon#flushed, iclass 20, count 2 2006.280.07:49:19.11#ibcon#about to write, iclass 20, count 2 2006.280.07:49:19.11#ibcon#wrote, iclass 20, count 2 2006.280.07:49:19.11#ibcon#about to read 3, iclass 20, count 2 2006.280.07:49:19.14#ibcon#read 3, iclass 20, count 2 2006.280.07:49:19.14#ibcon#about to read 4, iclass 20, count 2 2006.280.07:49:19.14#ibcon#read 4, iclass 20, count 2 2006.280.07:49:19.14#ibcon#about to read 5, iclass 20, count 2 2006.280.07:49:19.14#ibcon#read 5, iclass 20, count 2 2006.280.07:49:19.14#ibcon#about to read 6, iclass 20, count 2 2006.280.07:49:19.14#ibcon#read 6, iclass 20, count 2 2006.280.07:49:19.14#ibcon#end of sib2, iclass 20, count 2 2006.280.07:49:19.14#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:49:19.14#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:49:19.14#ibcon#[25=AT03-06\r\n] 2006.280.07:49:19.14#ibcon#*before write, iclass 20, count 2 2006.280.07:49:19.14#ibcon#enter sib2, iclass 20, count 2 2006.280.07:49:19.14#ibcon#flushed, iclass 20, count 2 2006.280.07:49:19.14#ibcon#about to write, iclass 20, count 2 2006.280.07:49:19.14#ibcon#wrote, iclass 20, count 2 2006.280.07:49:19.14#ibcon#about to read 3, iclass 20, count 2 2006.280.07:49:19.17#ibcon#read 3, iclass 20, count 2 2006.280.07:49:19.17#ibcon#about to read 4, iclass 20, count 2 2006.280.07:49:19.17#ibcon#read 4, iclass 20, count 2 2006.280.07:49:19.17#ibcon#about to read 5, iclass 20, count 2 2006.280.07:49:19.17#ibcon#read 5, iclass 20, count 2 2006.280.07:49:19.17#ibcon#about to read 6, iclass 20, count 2 2006.280.07:49:19.17#ibcon#read 6, iclass 20, count 2 2006.280.07:49:19.17#ibcon#end of sib2, iclass 20, count 2 2006.280.07:49:19.17#ibcon#*after write, iclass 20, count 2 2006.280.07:49:19.17#ibcon#*before return 0, iclass 20, count 2 2006.280.07:49:19.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:19.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:19.17#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:49:19.17#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:19.17#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:19.29#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:19.29#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:19.29#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:49:19.29#ibcon#first serial, iclass 20, count 0 2006.280.07:49:19.29#ibcon#enter sib2, iclass 20, count 0 2006.280.07:49:19.29#ibcon#flushed, iclass 20, count 0 2006.280.07:49:19.29#ibcon#about to write, iclass 20, count 0 2006.280.07:49:19.29#ibcon#wrote, iclass 20, count 0 2006.280.07:49:19.29#ibcon#about to read 3, iclass 20, count 0 2006.280.07:49:19.31#ibcon#read 3, iclass 20, count 0 2006.280.07:49:19.31#ibcon#about to read 4, iclass 20, count 0 2006.280.07:49:19.31#ibcon#read 4, iclass 20, count 0 2006.280.07:49:19.31#ibcon#about to read 5, iclass 20, count 0 2006.280.07:49:19.31#ibcon#read 5, iclass 20, count 0 2006.280.07:49:19.31#ibcon#about to read 6, iclass 20, count 0 2006.280.07:49:19.31#ibcon#read 6, iclass 20, count 0 2006.280.07:49:19.31#ibcon#end of sib2, iclass 20, count 0 2006.280.07:49:19.31#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:49:19.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:49:19.31#ibcon#[25=USB\r\n] 2006.280.07:49:19.31#ibcon#*before write, iclass 20, count 0 2006.280.07:49:19.31#ibcon#enter sib2, iclass 20, count 0 2006.280.07:49:19.31#ibcon#flushed, iclass 20, count 0 2006.280.07:49:19.31#ibcon#about to write, iclass 20, count 0 2006.280.07:49:19.31#ibcon#wrote, iclass 20, count 0 2006.280.07:49:19.31#ibcon#about to read 3, iclass 20, count 0 2006.280.07:49:19.35#ibcon#read 3, iclass 20, count 0 2006.280.07:49:19.35#ibcon#about to read 4, iclass 20, count 0 2006.280.07:49:19.35#ibcon#read 4, iclass 20, count 0 2006.280.07:49:19.35#ibcon#about to read 5, iclass 20, count 0 2006.280.07:49:19.35#ibcon#read 5, iclass 20, count 0 2006.280.07:49:19.35#ibcon#about to read 6, iclass 20, count 0 2006.280.07:49:19.35#ibcon#read 6, iclass 20, count 0 2006.280.07:49:19.35#ibcon#end of sib2, iclass 20, count 0 2006.280.07:49:19.35#ibcon#*after write, iclass 20, count 0 2006.280.07:49:19.35#ibcon#*before return 0, iclass 20, count 0 2006.280.07:49:19.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:19.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:19.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:49:19.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:49:19.35$vc4f8/valo=4,832.99 2006.280.07:49:19.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.07:49:19.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.07:49:19.35#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:19.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:19.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:19.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:19.35#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:49:19.35#ibcon#first serial, iclass 22, count 0 2006.280.07:49:19.35#ibcon#enter sib2, iclass 22, count 0 2006.280.07:49:19.35#ibcon#flushed, iclass 22, count 0 2006.280.07:49:19.35#ibcon#about to write, iclass 22, count 0 2006.280.07:49:19.35#ibcon#wrote, iclass 22, count 0 2006.280.07:49:19.35#ibcon#about to read 3, iclass 22, count 0 2006.280.07:49:19.37#ibcon#read 3, iclass 22, count 0 2006.280.07:49:19.37#ibcon#about to read 4, iclass 22, count 0 2006.280.07:49:19.37#ibcon#read 4, iclass 22, count 0 2006.280.07:49:19.37#ibcon#about to read 5, iclass 22, count 0 2006.280.07:49:19.37#ibcon#read 5, iclass 22, count 0 2006.280.07:49:19.37#ibcon#about to read 6, iclass 22, count 0 2006.280.07:49:19.37#ibcon#read 6, iclass 22, count 0 2006.280.07:49:19.37#ibcon#end of sib2, iclass 22, count 0 2006.280.07:49:19.37#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:49:19.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:49:19.37#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:49:19.37#ibcon#*before write, iclass 22, count 0 2006.280.07:49:19.37#ibcon#enter sib2, iclass 22, count 0 2006.280.07:49:19.37#ibcon#flushed, iclass 22, count 0 2006.280.07:49:19.39#ibcon#about to write, iclass 22, count 0 2006.280.07:49:19.39#ibcon#wrote, iclass 22, count 0 2006.280.07:49:19.39#ibcon#about to read 3, iclass 22, count 0 2006.280.07:49:19.43#ibcon#read 3, iclass 22, count 0 2006.280.07:49:19.43#ibcon#about to read 4, iclass 22, count 0 2006.280.07:49:19.43#ibcon#read 4, iclass 22, count 0 2006.280.07:49:19.43#ibcon#about to read 5, iclass 22, count 0 2006.280.07:49:19.43#ibcon#read 5, iclass 22, count 0 2006.280.07:49:19.43#ibcon#about to read 6, iclass 22, count 0 2006.280.07:49:19.43#ibcon#read 6, iclass 22, count 0 2006.280.07:49:19.43#ibcon#end of sib2, iclass 22, count 0 2006.280.07:49:19.43#ibcon#*after write, iclass 22, count 0 2006.280.07:49:19.43#ibcon#*before return 0, iclass 22, count 0 2006.280.07:49:19.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:19.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:19.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:49:19.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:49:19.43$vc4f8/va=4,6 2006.280.07:49:19.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.07:49:19.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.07:49:19.43#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:19.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:19.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:19.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:19.47#ibcon#enter wrdev, iclass 24, count 2 2006.280.07:49:19.47#ibcon#first serial, iclass 24, count 2 2006.280.07:49:19.47#ibcon#enter sib2, iclass 24, count 2 2006.280.07:49:19.47#ibcon#flushed, iclass 24, count 2 2006.280.07:49:19.47#ibcon#about to write, iclass 24, count 2 2006.280.07:49:19.47#ibcon#wrote, iclass 24, count 2 2006.280.07:49:19.47#ibcon#about to read 3, iclass 24, count 2 2006.280.07:49:19.49#ibcon#read 3, iclass 24, count 2 2006.280.07:49:19.49#ibcon#about to read 4, iclass 24, count 2 2006.280.07:49:19.49#ibcon#read 4, iclass 24, count 2 2006.280.07:49:19.49#ibcon#about to read 5, iclass 24, count 2 2006.280.07:49:19.49#ibcon#read 5, iclass 24, count 2 2006.280.07:49:19.49#ibcon#about to read 6, iclass 24, count 2 2006.280.07:49:19.49#ibcon#read 6, iclass 24, count 2 2006.280.07:49:19.49#ibcon#end of sib2, iclass 24, count 2 2006.280.07:49:19.49#ibcon#*mode == 0, iclass 24, count 2 2006.280.07:49:19.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.07:49:19.49#ibcon#[25=AT04-06\r\n] 2006.280.07:49:19.49#ibcon#*before write, iclass 24, count 2 2006.280.07:49:19.49#ibcon#enter sib2, iclass 24, count 2 2006.280.07:49:19.49#ibcon#flushed, iclass 24, count 2 2006.280.07:49:19.49#ibcon#about to write, iclass 24, count 2 2006.280.07:49:19.49#ibcon#wrote, iclass 24, count 2 2006.280.07:49:19.49#ibcon#about to read 3, iclass 24, count 2 2006.280.07:49:19.52#ibcon#read 3, iclass 24, count 2 2006.280.07:49:19.52#ibcon#about to read 4, iclass 24, count 2 2006.280.07:49:19.52#ibcon#read 4, iclass 24, count 2 2006.280.07:49:19.52#ibcon#about to read 5, iclass 24, count 2 2006.280.07:49:19.52#ibcon#read 5, iclass 24, count 2 2006.280.07:49:19.52#ibcon#about to read 6, iclass 24, count 2 2006.280.07:49:19.52#ibcon#read 6, iclass 24, count 2 2006.280.07:49:19.52#ibcon#end of sib2, iclass 24, count 2 2006.280.07:49:19.52#ibcon#*after write, iclass 24, count 2 2006.280.07:49:19.52#ibcon#*before return 0, iclass 24, count 2 2006.280.07:49:19.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:19.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:19.52#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.07:49:19.52#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:19.52#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:19.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:19.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:19.64#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:49:19.64#ibcon#first serial, iclass 24, count 0 2006.280.07:49:19.64#ibcon#enter sib2, iclass 24, count 0 2006.280.07:49:19.64#ibcon#flushed, iclass 24, count 0 2006.280.07:49:19.64#ibcon#about to write, iclass 24, count 0 2006.280.07:49:19.64#ibcon#wrote, iclass 24, count 0 2006.280.07:49:19.64#ibcon#about to read 3, iclass 24, count 0 2006.280.07:49:19.66#ibcon#read 3, iclass 24, count 0 2006.280.07:49:19.66#ibcon#about to read 4, iclass 24, count 0 2006.280.07:49:19.66#ibcon#read 4, iclass 24, count 0 2006.280.07:49:19.66#ibcon#about to read 5, iclass 24, count 0 2006.280.07:49:19.66#ibcon#read 5, iclass 24, count 0 2006.280.07:49:19.66#ibcon#about to read 6, iclass 24, count 0 2006.280.07:49:19.66#ibcon#read 6, iclass 24, count 0 2006.280.07:49:19.66#ibcon#end of sib2, iclass 24, count 0 2006.280.07:49:19.66#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:49:19.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:49:19.66#ibcon#[25=USB\r\n] 2006.280.07:49:19.66#ibcon#*before write, iclass 24, count 0 2006.280.07:49:19.66#ibcon#enter sib2, iclass 24, count 0 2006.280.07:49:19.66#ibcon#flushed, iclass 24, count 0 2006.280.07:49:19.66#ibcon#about to write, iclass 24, count 0 2006.280.07:49:19.66#ibcon#wrote, iclass 24, count 0 2006.280.07:49:19.66#ibcon#about to read 3, iclass 24, count 0 2006.280.07:49:19.69#ibcon#read 3, iclass 24, count 0 2006.280.07:49:19.69#ibcon#about to read 4, iclass 24, count 0 2006.280.07:49:19.69#ibcon#read 4, iclass 24, count 0 2006.280.07:49:19.69#ibcon#about to read 5, iclass 24, count 0 2006.280.07:49:19.69#ibcon#read 5, iclass 24, count 0 2006.280.07:49:19.69#ibcon#about to read 6, iclass 24, count 0 2006.280.07:49:19.69#ibcon#read 6, iclass 24, count 0 2006.280.07:49:19.69#ibcon#end of sib2, iclass 24, count 0 2006.280.07:49:19.69#ibcon#*after write, iclass 24, count 0 2006.280.07:49:19.69#ibcon#*before return 0, iclass 24, count 0 2006.280.07:49:19.69#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:19.69#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:19.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:49:19.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:49:19.69$vc4f8/valo=5,652.99 2006.280.07:49:19.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:49:19.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:49:19.69#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:19.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:19.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:19.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:19.69#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:49:19.69#ibcon#first serial, iclass 26, count 0 2006.280.07:49:19.69#ibcon#enter sib2, iclass 26, count 0 2006.280.07:49:19.69#ibcon#flushed, iclass 26, count 0 2006.280.07:49:19.69#ibcon#about to write, iclass 26, count 0 2006.280.07:49:19.69#ibcon#wrote, iclass 26, count 0 2006.280.07:49:19.69#ibcon#about to read 3, iclass 26, count 0 2006.280.07:49:19.71#ibcon#read 3, iclass 26, count 0 2006.280.07:49:19.71#ibcon#about to read 4, iclass 26, count 0 2006.280.07:49:19.71#ibcon#read 4, iclass 26, count 0 2006.280.07:49:19.71#ibcon#about to read 5, iclass 26, count 0 2006.280.07:49:19.71#ibcon#read 5, iclass 26, count 0 2006.280.07:49:19.71#ibcon#about to read 6, iclass 26, count 0 2006.280.07:49:19.71#ibcon#read 6, iclass 26, count 0 2006.280.07:49:19.71#ibcon#end of sib2, iclass 26, count 0 2006.280.07:49:19.71#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:49:19.71#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:49:19.71#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:49:19.71#ibcon#*before write, iclass 26, count 0 2006.280.07:49:19.71#ibcon#enter sib2, iclass 26, count 0 2006.280.07:49:19.71#ibcon#flushed, iclass 26, count 0 2006.280.07:49:19.71#ibcon#about to write, iclass 26, count 0 2006.280.07:49:19.71#ibcon#wrote, iclass 26, count 0 2006.280.07:49:19.71#ibcon#about to read 3, iclass 26, count 0 2006.280.07:49:19.75#ibcon#read 3, iclass 26, count 0 2006.280.07:49:19.75#ibcon#about to read 4, iclass 26, count 0 2006.280.07:49:19.75#ibcon#read 4, iclass 26, count 0 2006.280.07:49:19.75#ibcon#about to read 5, iclass 26, count 0 2006.280.07:49:19.75#ibcon#read 5, iclass 26, count 0 2006.280.07:49:19.75#ibcon#about to read 6, iclass 26, count 0 2006.280.07:49:19.75#ibcon#read 6, iclass 26, count 0 2006.280.07:49:19.75#ibcon#end of sib2, iclass 26, count 0 2006.280.07:49:19.75#ibcon#*after write, iclass 26, count 0 2006.280.07:49:19.75#ibcon#*before return 0, iclass 26, count 0 2006.280.07:49:19.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:19.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:19.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:49:19.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:49:19.75$vc4f8/va=5,7 2006.280.07:49:19.75#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:49:19.75#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:49:19.75#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:19.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:19.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:19.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:19.81#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:49:19.81#ibcon#first serial, iclass 28, count 2 2006.280.07:49:19.81#ibcon#enter sib2, iclass 28, count 2 2006.280.07:49:19.81#ibcon#flushed, iclass 28, count 2 2006.280.07:49:19.81#ibcon#about to write, iclass 28, count 2 2006.280.07:49:19.81#ibcon#wrote, iclass 28, count 2 2006.280.07:49:19.81#ibcon#about to read 3, iclass 28, count 2 2006.280.07:49:19.83#ibcon#read 3, iclass 28, count 2 2006.280.07:49:19.83#ibcon#about to read 4, iclass 28, count 2 2006.280.07:49:19.83#ibcon#read 4, iclass 28, count 2 2006.280.07:49:19.83#ibcon#about to read 5, iclass 28, count 2 2006.280.07:49:19.83#ibcon#read 5, iclass 28, count 2 2006.280.07:49:19.83#ibcon#about to read 6, iclass 28, count 2 2006.280.07:49:19.83#ibcon#read 6, iclass 28, count 2 2006.280.07:49:19.83#ibcon#end of sib2, iclass 28, count 2 2006.280.07:49:19.83#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:49:19.83#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:49:19.83#ibcon#[25=AT05-07\r\n] 2006.280.07:49:19.83#ibcon#*before write, iclass 28, count 2 2006.280.07:49:19.83#ibcon#enter sib2, iclass 28, count 2 2006.280.07:49:19.83#ibcon#flushed, iclass 28, count 2 2006.280.07:49:19.83#ibcon#about to write, iclass 28, count 2 2006.280.07:49:19.83#ibcon#wrote, iclass 28, count 2 2006.280.07:49:19.83#ibcon#about to read 3, iclass 28, count 2 2006.280.07:49:19.86#ibcon#read 3, iclass 28, count 2 2006.280.07:49:19.86#ibcon#about to read 4, iclass 28, count 2 2006.280.07:49:19.86#ibcon#read 4, iclass 28, count 2 2006.280.07:49:19.86#ibcon#about to read 5, iclass 28, count 2 2006.280.07:49:19.86#ibcon#read 5, iclass 28, count 2 2006.280.07:49:19.86#ibcon#about to read 6, iclass 28, count 2 2006.280.07:49:19.86#ibcon#read 6, iclass 28, count 2 2006.280.07:49:19.86#ibcon#end of sib2, iclass 28, count 2 2006.280.07:49:19.86#ibcon#*after write, iclass 28, count 2 2006.280.07:49:19.86#ibcon#*before return 0, iclass 28, count 2 2006.280.07:49:19.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:19.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:19.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:49:19.86#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:19.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:19.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:19.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:19.98#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:49:19.98#ibcon#first serial, iclass 28, count 0 2006.280.07:49:19.98#ibcon#enter sib2, iclass 28, count 0 2006.280.07:49:19.98#ibcon#flushed, iclass 28, count 0 2006.280.07:49:19.98#ibcon#about to write, iclass 28, count 0 2006.280.07:49:19.98#ibcon#wrote, iclass 28, count 0 2006.280.07:49:19.98#ibcon#about to read 3, iclass 28, count 0 2006.280.07:49:20.00#ibcon#read 3, iclass 28, count 0 2006.280.07:49:20.00#ibcon#about to read 4, iclass 28, count 0 2006.280.07:49:20.00#ibcon#read 4, iclass 28, count 0 2006.280.07:49:20.00#ibcon#about to read 5, iclass 28, count 0 2006.280.07:49:20.00#ibcon#read 5, iclass 28, count 0 2006.280.07:49:20.00#ibcon#about to read 6, iclass 28, count 0 2006.280.07:49:20.00#ibcon#read 6, iclass 28, count 0 2006.280.07:49:20.00#ibcon#end of sib2, iclass 28, count 0 2006.280.07:49:20.00#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:49:20.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:49:20.00#ibcon#[25=USB\r\n] 2006.280.07:49:20.00#ibcon#*before write, iclass 28, count 0 2006.280.07:49:20.00#ibcon#enter sib2, iclass 28, count 0 2006.280.07:49:20.00#ibcon#flushed, iclass 28, count 0 2006.280.07:49:20.00#ibcon#about to write, iclass 28, count 0 2006.280.07:49:20.00#ibcon#wrote, iclass 28, count 0 2006.280.07:49:20.00#ibcon#about to read 3, iclass 28, count 0 2006.280.07:49:20.03#ibcon#read 3, iclass 28, count 0 2006.280.07:49:20.03#ibcon#about to read 4, iclass 28, count 0 2006.280.07:49:20.03#ibcon#read 4, iclass 28, count 0 2006.280.07:49:20.03#ibcon#about to read 5, iclass 28, count 0 2006.280.07:49:20.03#ibcon#read 5, iclass 28, count 0 2006.280.07:49:20.03#ibcon#about to read 6, iclass 28, count 0 2006.280.07:49:20.03#ibcon#read 6, iclass 28, count 0 2006.280.07:49:20.03#ibcon#end of sib2, iclass 28, count 0 2006.280.07:49:20.03#ibcon#*after write, iclass 28, count 0 2006.280.07:49:20.03#ibcon#*before return 0, iclass 28, count 0 2006.280.07:49:20.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:20.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:20.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:49:20.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:49:20.03$vc4f8/valo=6,772.99 2006.280.07:49:20.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:49:20.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:49:20.03#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:20.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:20.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:20.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:20.03#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:49:20.03#ibcon#first serial, iclass 30, count 0 2006.280.07:49:20.03#ibcon#enter sib2, iclass 30, count 0 2006.280.07:49:20.03#ibcon#flushed, iclass 30, count 0 2006.280.07:49:20.03#ibcon#about to write, iclass 30, count 0 2006.280.07:49:20.03#ibcon#wrote, iclass 30, count 0 2006.280.07:49:20.03#ibcon#about to read 3, iclass 30, count 0 2006.280.07:49:20.05#ibcon#read 3, iclass 30, count 0 2006.280.07:49:20.05#ibcon#about to read 4, iclass 30, count 0 2006.280.07:49:20.05#ibcon#read 4, iclass 30, count 0 2006.280.07:49:20.05#ibcon#about to read 5, iclass 30, count 0 2006.280.07:49:20.05#ibcon#read 5, iclass 30, count 0 2006.280.07:49:20.05#ibcon#about to read 6, iclass 30, count 0 2006.280.07:49:20.05#ibcon#read 6, iclass 30, count 0 2006.280.07:49:20.05#ibcon#end of sib2, iclass 30, count 0 2006.280.07:49:20.05#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:49:20.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:49:20.05#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:49:20.05#ibcon#*before write, iclass 30, count 0 2006.280.07:49:20.05#ibcon#enter sib2, iclass 30, count 0 2006.280.07:49:20.05#ibcon#flushed, iclass 30, count 0 2006.280.07:49:20.05#ibcon#about to write, iclass 30, count 0 2006.280.07:49:20.05#ibcon#wrote, iclass 30, count 0 2006.280.07:49:20.05#ibcon#about to read 3, iclass 30, count 0 2006.280.07:49:20.09#ibcon#read 3, iclass 30, count 0 2006.280.07:49:20.09#ibcon#about to read 4, iclass 30, count 0 2006.280.07:49:20.09#ibcon#read 4, iclass 30, count 0 2006.280.07:49:20.09#ibcon#about to read 5, iclass 30, count 0 2006.280.07:49:20.09#ibcon#read 5, iclass 30, count 0 2006.280.07:49:20.09#ibcon#about to read 6, iclass 30, count 0 2006.280.07:49:20.09#ibcon#read 6, iclass 30, count 0 2006.280.07:49:20.09#ibcon#end of sib2, iclass 30, count 0 2006.280.07:49:20.09#ibcon#*after write, iclass 30, count 0 2006.280.07:49:20.09#ibcon#*before return 0, iclass 30, count 0 2006.280.07:49:20.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:20.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:20.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:49:20.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:49:20.09$vc4f8/va=6,6 2006.280.07:49:20.11#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:49:20.11#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:49:20.11#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:20.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:20.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:20.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:20.14#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:49:20.14#ibcon#first serial, iclass 32, count 2 2006.280.07:49:20.14#ibcon#enter sib2, iclass 32, count 2 2006.280.07:49:20.14#ibcon#flushed, iclass 32, count 2 2006.280.07:49:20.14#ibcon#about to write, iclass 32, count 2 2006.280.07:49:20.14#ibcon#wrote, iclass 32, count 2 2006.280.07:49:20.14#ibcon#about to read 3, iclass 32, count 2 2006.280.07:49:20.16#ibcon#read 3, iclass 32, count 2 2006.280.07:49:20.16#ibcon#about to read 4, iclass 32, count 2 2006.280.07:49:20.16#ibcon#read 4, iclass 32, count 2 2006.280.07:49:20.16#ibcon#about to read 5, iclass 32, count 2 2006.280.07:49:20.16#ibcon#read 5, iclass 32, count 2 2006.280.07:49:20.16#ibcon#about to read 6, iclass 32, count 2 2006.280.07:49:20.16#ibcon#read 6, iclass 32, count 2 2006.280.07:49:20.16#ibcon#end of sib2, iclass 32, count 2 2006.280.07:49:20.16#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:49:20.16#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:49:20.16#ibcon#[25=AT06-06\r\n] 2006.280.07:49:20.16#ibcon#*before write, iclass 32, count 2 2006.280.07:49:20.16#ibcon#enter sib2, iclass 32, count 2 2006.280.07:49:20.16#ibcon#flushed, iclass 32, count 2 2006.280.07:49:20.16#ibcon#about to write, iclass 32, count 2 2006.280.07:49:20.16#ibcon#wrote, iclass 32, count 2 2006.280.07:49:20.16#ibcon#about to read 3, iclass 32, count 2 2006.280.07:49:20.19#ibcon#read 3, iclass 32, count 2 2006.280.07:49:20.19#ibcon#about to read 4, iclass 32, count 2 2006.280.07:49:20.19#ibcon#read 4, iclass 32, count 2 2006.280.07:49:20.19#ibcon#about to read 5, iclass 32, count 2 2006.280.07:49:20.19#ibcon#read 5, iclass 32, count 2 2006.280.07:49:20.19#ibcon#about to read 6, iclass 32, count 2 2006.280.07:49:20.19#ibcon#read 6, iclass 32, count 2 2006.280.07:49:20.19#ibcon#end of sib2, iclass 32, count 2 2006.280.07:49:20.19#ibcon#*after write, iclass 32, count 2 2006.280.07:49:20.19#ibcon#*before return 0, iclass 32, count 2 2006.280.07:49:20.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:20.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:20.19#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:49:20.19#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:20.19#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:49:20.31#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:49:20.31#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:49:20.31#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:49:20.31#ibcon#first serial, iclass 32, count 0 2006.280.07:49:20.31#ibcon#enter sib2, iclass 32, count 0 2006.280.07:49:20.31#ibcon#flushed, iclass 32, count 0 2006.280.07:49:20.31#ibcon#about to write, iclass 32, count 0 2006.280.07:49:20.31#ibcon#wrote, iclass 32, count 0 2006.280.07:49:20.31#ibcon#about to read 3, iclass 32, count 0 2006.280.07:49:20.33#ibcon#read 3, iclass 32, count 0 2006.280.07:49:20.33#ibcon#about to read 4, iclass 32, count 0 2006.280.07:49:20.33#ibcon#read 4, iclass 32, count 0 2006.280.07:49:20.33#ibcon#about to read 5, iclass 32, count 0 2006.280.07:49:20.33#ibcon#read 5, iclass 32, count 0 2006.280.07:49:20.33#ibcon#about to read 6, iclass 32, count 0 2006.280.07:49:20.33#ibcon#read 6, iclass 32, count 0 2006.280.07:49:20.33#ibcon#end of sib2, iclass 32, count 0 2006.280.07:49:20.33#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:49:20.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:49:20.33#ibcon#[25=USB\r\n] 2006.280.07:49:20.33#ibcon#*before write, iclass 32, count 0 2006.280.07:49:20.33#ibcon#enter sib2, iclass 32, count 0 2006.280.07:49:20.33#ibcon#flushed, iclass 32, count 0 2006.280.07:49:20.33#ibcon#about to write, iclass 32, count 0 2006.280.07:49:20.33#ibcon#wrote, iclass 32, count 0 2006.280.07:49:20.33#ibcon#about to read 3, iclass 32, count 0 2006.280.07:49:20.36#ibcon#read 3, iclass 32, count 0 2006.280.07:49:20.36#ibcon#about to read 4, iclass 32, count 0 2006.280.07:49:20.36#ibcon#read 4, iclass 32, count 0 2006.280.07:49:20.36#ibcon#about to read 5, iclass 32, count 0 2006.280.07:49:20.36#ibcon#read 5, iclass 32, count 0 2006.280.07:49:20.36#ibcon#about to read 6, iclass 32, count 0 2006.280.07:49:20.36#ibcon#read 6, iclass 32, count 0 2006.280.07:49:20.36#ibcon#end of sib2, iclass 32, count 0 2006.280.07:49:20.36#ibcon#*after write, iclass 32, count 0 2006.280.07:49:20.36#ibcon#*before return 0, iclass 32, count 0 2006.280.07:49:20.36#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:49:20.36#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:49:20.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:49:20.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:49:20.36$vc4f8/valo=7,832.99 2006.280.07:49:20.36#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:49:20.36#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:49:20.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:20.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:49:20.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:49:20.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:49:20.36#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:49:20.36#ibcon#first serial, iclass 34, count 0 2006.280.07:49:20.36#ibcon#enter sib2, iclass 34, count 0 2006.280.07:49:20.36#ibcon#flushed, iclass 34, count 0 2006.280.07:49:20.36#ibcon#about to write, iclass 34, count 0 2006.280.07:49:20.36#ibcon#wrote, iclass 34, count 0 2006.280.07:49:20.36#ibcon#about to read 3, iclass 34, count 0 2006.280.07:49:20.38#ibcon#read 3, iclass 34, count 0 2006.280.07:49:20.38#ibcon#about to read 4, iclass 34, count 0 2006.280.07:49:20.38#ibcon#read 4, iclass 34, count 0 2006.280.07:49:20.38#ibcon#about to read 5, iclass 34, count 0 2006.280.07:49:20.38#ibcon#read 5, iclass 34, count 0 2006.280.07:49:20.38#ibcon#about to read 6, iclass 34, count 0 2006.280.07:49:20.38#ibcon#read 6, iclass 34, count 0 2006.280.07:49:20.38#ibcon#end of sib2, iclass 34, count 0 2006.280.07:49:20.38#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:49:20.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:49:20.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:49:20.38#ibcon#*before write, iclass 34, count 0 2006.280.07:49:20.38#ibcon#enter sib2, iclass 34, count 0 2006.280.07:49:20.38#ibcon#flushed, iclass 34, count 0 2006.280.07:49:20.38#ibcon#about to write, iclass 34, count 0 2006.280.07:49:20.38#ibcon#wrote, iclass 34, count 0 2006.280.07:49:20.38#ibcon#about to read 3, iclass 34, count 0 2006.280.07:49:20.42#ibcon#read 3, iclass 34, count 0 2006.280.07:49:20.42#ibcon#about to read 4, iclass 34, count 0 2006.280.07:49:20.42#ibcon#read 4, iclass 34, count 0 2006.280.07:49:20.42#ibcon#about to read 5, iclass 34, count 0 2006.280.07:49:20.42#ibcon#read 5, iclass 34, count 0 2006.280.07:49:20.42#ibcon#about to read 6, iclass 34, count 0 2006.280.07:49:20.42#ibcon#read 6, iclass 34, count 0 2006.280.07:49:20.42#ibcon#end of sib2, iclass 34, count 0 2006.280.07:49:20.42#ibcon#*after write, iclass 34, count 0 2006.280.07:49:20.42#ibcon#*before return 0, iclass 34, count 0 2006.280.07:49:20.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:49:20.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:49:20.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:49:20.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:49:20.42$vc4f8/va=7,6 2006.280.07:49:20.42#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:49:20.42#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:49:20.42#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:20.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:49:20.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:49:20.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:49:20.48#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:49:20.48#ibcon#first serial, iclass 36, count 2 2006.280.07:49:20.48#ibcon#enter sib2, iclass 36, count 2 2006.280.07:49:20.48#ibcon#flushed, iclass 36, count 2 2006.280.07:49:20.48#ibcon#about to write, iclass 36, count 2 2006.280.07:49:20.48#ibcon#wrote, iclass 36, count 2 2006.280.07:49:20.48#ibcon#about to read 3, iclass 36, count 2 2006.280.07:49:20.51#ibcon#read 3, iclass 36, count 2 2006.280.07:49:20.51#ibcon#about to read 4, iclass 36, count 2 2006.280.07:49:20.51#ibcon#read 4, iclass 36, count 2 2006.280.07:49:20.51#ibcon#about to read 5, iclass 36, count 2 2006.280.07:49:20.51#ibcon#read 5, iclass 36, count 2 2006.280.07:49:20.51#ibcon#about to read 6, iclass 36, count 2 2006.280.07:49:20.51#ibcon#read 6, iclass 36, count 2 2006.280.07:49:20.51#ibcon#end of sib2, iclass 36, count 2 2006.280.07:49:20.51#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:49:20.51#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:49:20.51#ibcon#[25=AT07-06\r\n] 2006.280.07:49:20.51#ibcon#*before write, iclass 36, count 2 2006.280.07:49:20.51#ibcon#enter sib2, iclass 36, count 2 2006.280.07:49:20.51#ibcon#flushed, iclass 36, count 2 2006.280.07:49:20.51#ibcon#about to write, iclass 36, count 2 2006.280.07:49:20.51#ibcon#wrote, iclass 36, count 2 2006.280.07:49:20.51#ibcon#about to read 3, iclass 36, count 2 2006.280.07:49:20.54#ibcon#read 3, iclass 36, count 2 2006.280.07:49:20.54#ibcon#about to read 4, iclass 36, count 2 2006.280.07:49:20.54#ibcon#read 4, iclass 36, count 2 2006.280.07:49:20.54#ibcon#about to read 5, iclass 36, count 2 2006.280.07:49:20.54#ibcon#read 5, iclass 36, count 2 2006.280.07:49:20.54#ibcon#about to read 6, iclass 36, count 2 2006.280.07:49:20.54#ibcon#read 6, iclass 36, count 2 2006.280.07:49:20.54#ibcon#end of sib2, iclass 36, count 2 2006.280.07:49:20.54#ibcon#*after write, iclass 36, count 2 2006.280.07:49:20.54#ibcon#*before return 0, iclass 36, count 2 2006.280.07:49:20.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:49:20.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:49:20.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:49:20.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:20.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:49:20.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:49:20.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:49:20.66#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:49:20.66#ibcon#first serial, iclass 36, count 0 2006.280.07:49:20.66#ibcon#enter sib2, iclass 36, count 0 2006.280.07:49:20.66#ibcon#flushed, iclass 36, count 0 2006.280.07:49:20.66#ibcon#about to write, iclass 36, count 0 2006.280.07:49:20.66#ibcon#wrote, iclass 36, count 0 2006.280.07:49:20.66#ibcon#about to read 3, iclass 36, count 0 2006.280.07:49:20.68#ibcon#read 3, iclass 36, count 0 2006.280.07:49:20.68#ibcon#about to read 4, iclass 36, count 0 2006.280.07:49:20.68#ibcon#read 4, iclass 36, count 0 2006.280.07:49:20.68#ibcon#about to read 5, iclass 36, count 0 2006.280.07:49:20.68#ibcon#read 5, iclass 36, count 0 2006.280.07:49:20.68#ibcon#about to read 6, iclass 36, count 0 2006.280.07:49:20.68#ibcon#read 6, iclass 36, count 0 2006.280.07:49:20.68#ibcon#end of sib2, iclass 36, count 0 2006.280.07:49:20.68#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:49:20.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:49:20.68#ibcon#[25=USB\r\n] 2006.280.07:49:20.68#ibcon#*before write, iclass 36, count 0 2006.280.07:49:20.68#ibcon#enter sib2, iclass 36, count 0 2006.280.07:49:20.68#ibcon#flushed, iclass 36, count 0 2006.280.07:49:20.68#ibcon#about to write, iclass 36, count 0 2006.280.07:49:20.68#ibcon#wrote, iclass 36, count 0 2006.280.07:49:20.68#ibcon#about to read 3, iclass 36, count 0 2006.280.07:49:20.71#ibcon#read 3, iclass 36, count 0 2006.280.07:49:20.71#ibcon#about to read 4, iclass 36, count 0 2006.280.07:49:20.71#ibcon#read 4, iclass 36, count 0 2006.280.07:49:20.71#ibcon#about to read 5, iclass 36, count 0 2006.280.07:49:20.71#ibcon#read 5, iclass 36, count 0 2006.280.07:49:20.71#ibcon#about to read 6, iclass 36, count 0 2006.280.07:49:20.71#ibcon#read 6, iclass 36, count 0 2006.280.07:49:20.71#ibcon#end of sib2, iclass 36, count 0 2006.280.07:49:20.71#ibcon#*after write, iclass 36, count 0 2006.280.07:49:20.71#ibcon#*before return 0, iclass 36, count 0 2006.280.07:49:20.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:49:20.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:49:20.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:49:20.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:49:20.71$vc4f8/valo=8,852.99 2006.280.07:49:20.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:49:20.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:49:20.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:20.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:49:20.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:49:20.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:49:20.71#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:49:20.71#ibcon#first serial, iclass 38, count 0 2006.280.07:49:20.71#ibcon#enter sib2, iclass 38, count 0 2006.280.07:49:20.71#ibcon#flushed, iclass 38, count 0 2006.280.07:49:20.71#ibcon#about to write, iclass 38, count 0 2006.280.07:49:20.71#ibcon#wrote, iclass 38, count 0 2006.280.07:49:20.71#ibcon#about to read 3, iclass 38, count 0 2006.280.07:49:20.73#ibcon#read 3, iclass 38, count 0 2006.280.07:49:20.73#ibcon#about to read 4, iclass 38, count 0 2006.280.07:49:20.73#ibcon#read 4, iclass 38, count 0 2006.280.07:49:20.73#ibcon#about to read 5, iclass 38, count 0 2006.280.07:49:20.73#ibcon#read 5, iclass 38, count 0 2006.280.07:49:20.73#ibcon#about to read 6, iclass 38, count 0 2006.280.07:49:20.73#ibcon#read 6, iclass 38, count 0 2006.280.07:49:20.73#ibcon#end of sib2, iclass 38, count 0 2006.280.07:49:20.73#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:49:20.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:49:20.73#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:49:20.73#ibcon#*before write, iclass 38, count 0 2006.280.07:49:20.73#ibcon#enter sib2, iclass 38, count 0 2006.280.07:49:20.73#ibcon#flushed, iclass 38, count 0 2006.280.07:49:20.73#ibcon#about to write, iclass 38, count 0 2006.280.07:49:20.73#ibcon#wrote, iclass 38, count 0 2006.280.07:49:20.73#ibcon#about to read 3, iclass 38, count 0 2006.280.07:49:20.77#ibcon#read 3, iclass 38, count 0 2006.280.07:49:20.77#ibcon#about to read 4, iclass 38, count 0 2006.280.07:49:20.77#ibcon#read 4, iclass 38, count 0 2006.280.07:49:20.77#ibcon#about to read 5, iclass 38, count 0 2006.280.07:49:20.77#ibcon#read 5, iclass 38, count 0 2006.280.07:49:20.77#ibcon#about to read 6, iclass 38, count 0 2006.280.07:49:20.77#ibcon#read 6, iclass 38, count 0 2006.280.07:49:20.77#ibcon#end of sib2, iclass 38, count 0 2006.280.07:49:20.77#ibcon#*after write, iclass 38, count 0 2006.280.07:49:20.77#ibcon#*before return 0, iclass 38, count 0 2006.280.07:49:20.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:49:20.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:49:20.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:49:20.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:49:20.77$vc4f8/va=8,6 2006.280.07:49:20.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:49:20.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:49:20.77#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:20.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:49:20.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:49:20.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:49:20.83#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:49:20.84#ibcon#first serial, iclass 40, count 2 2006.280.07:49:20.84#ibcon#enter sib2, iclass 40, count 2 2006.280.07:49:20.84#ibcon#flushed, iclass 40, count 2 2006.280.07:49:20.84#ibcon#about to write, iclass 40, count 2 2006.280.07:49:20.84#ibcon#wrote, iclass 40, count 2 2006.280.07:49:20.84#ibcon#about to read 3, iclass 40, count 2 2006.280.07:49:20.85#ibcon#read 3, iclass 40, count 2 2006.280.07:49:20.85#ibcon#about to read 4, iclass 40, count 2 2006.280.07:49:20.85#ibcon#read 4, iclass 40, count 2 2006.280.07:49:20.85#ibcon#about to read 5, iclass 40, count 2 2006.280.07:49:20.85#ibcon#read 5, iclass 40, count 2 2006.280.07:49:20.85#ibcon#about to read 6, iclass 40, count 2 2006.280.07:49:20.85#ibcon#read 6, iclass 40, count 2 2006.280.07:49:20.85#ibcon#end of sib2, iclass 40, count 2 2006.280.07:49:20.85#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:49:20.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:49:20.85#ibcon#[25=AT08-06\r\n] 2006.280.07:49:20.85#ibcon#*before write, iclass 40, count 2 2006.280.07:49:20.85#ibcon#enter sib2, iclass 40, count 2 2006.280.07:49:20.85#ibcon#flushed, iclass 40, count 2 2006.280.07:49:20.85#ibcon#about to write, iclass 40, count 2 2006.280.07:49:20.85#ibcon#wrote, iclass 40, count 2 2006.280.07:49:20.85#ibcon#about to read 3, iclass 40, count 2 2006.280.07:49:20.88#ibcon#read 3, iclass 40, count 2 2006.280.07:49:20.88#ibcon#about to read 4, iclass 40, count 2 2006.280.07:49:20.88#ibcon#read 4, iclass 40, count 2 2006.280.07:49:20.88#ibcon#about to read 5, iclass 40, count 2 2006.280.07:49:20.88#ibcon#read 5, iclass 40, count 2 2006.280.07:49:20.88#ibcon#about to read 6, iclass 40, count 2 2006.280.07:49:20.88#ibcon#read 6, iclass 40, count 2 2006.280.07:49:20.88#ibcon#end of sib2, iclass 40, count 2 2006.280.07:49:20.88#ibcon#*after write, iclass 40, count 2 2006.280.07:49:20.88#ibcon#*before return 0, iclass 40, count 2 2006.280.07:49:20.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:49:20.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:49:20.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:49:20.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:20.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:49:21.01#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:49:21.01#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:49:21.01#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:49:21.01#ibcon#first serial, iclass 40, count 0 2006.280.07:49:21.01#ibcon#enter sib2, iclass 40, count 0 2006.280.07:49:21.01#ibcon#flushed, iclass 40, count 0 2006.280.07:49:21.01#ibcon#about to write, iclass 40, count 0 2006.280.07:49:21.01#ibcon#wrote, iclass 40, count 0 2006.280.07:49:21.01#ibcon#about to read 3, iclass 40, count 0 2006.280.07:49:21.02#ibcon#read 3, iclass 40, count 0 2006.280.07:49:21.02#ibcon#about to read 4, iclass 40, count 0 2006.280.07:49:21.02#ibcon#read 4, iclass 40, count 0 2006.280.07:49:21.02#ibcon#about to read 5, iclass 40, count 0 2006.280.07:49:21.02#ibcon#read 5, iclass 40, count 0 2006.280.07:49:21.02#ibcon#about to read 6, iclass 40, count 0 2006.280.07:49:21.02#ibcon#read 6, iclass 40, count 0 2006.280.07:49:21.02#ibcon#end of sib2, iclass 40, count 0 2006.280.07:49:21.02#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:49:21.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:49:21.02#ibcon#[25=USB\r\n] 2006.280.07:49:21.02#ibcon#*before write, iclass 40, count 0 2006.280.07:49:21.02#ibcon#enter sib2, iclass 40, count 0 2006.280.07:49:21.02#ibcon#flushed, iclass 40, count 0 2006.280.07:49:21.02#ibcon#about to write, iclass 40, count 0 2006.280.07:49:21.02#ibcon#wrote, iclass 40, count 0 2006.280.07:49:21.02#ibcon#about to read 3, iclass 40, count 0 2006.280.07:49:21.05#ibcon#read 3, iclass 40, count 0 2006.280.07:49:21.05#ibcon#about to read 4, iclass 40, count 0 2006.280.07:49:21.05#ibcon#read 4, iclass 40, count 0 2006.280.07:49:21.05#ibcon#about to read 5, iclass 40, count 0 2006.280.07:49:21.05#ibcon#read 5, iclass 40, count 0 2006.280.07:49:21.05#ibcon#about to read 6, iclass 40, count 0 2006.280.07:49:21.05#ibcon#read 6, iclass 40, count 0 2006.280.07:49:21.05#ibcon#end of sib2, iclass 40, count 0 2006.280.07:49:21.05#ibcon#*after write, iclass 40, count 0 2006.280.07:49:21.05#ibcon#*before return 0, iclass 40, count 0 2006.280.07:49:21.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:49:21.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:49:21.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:49:21.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:49:21.05$vc4f8/vblo=1,632.99 2006.280.07:49:21.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:49:21.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:49:21.05#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:21.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:49:21.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:49:21.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:49:21.05#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:49:21.05#ibcon#first serial, iclass 4, count 0 2006.280.07:49:21.05#ibcon#enter sib2, iclass 4, count 0 2006.280.07:49:21.05#ibcon#flushed, iclass 4, count 0 2006.280.07:49:21.05#ibcon#about to write, iclass 4, count 0 2006.280.07:49:21.05#ibcon#wrote, iclass 4, count 0 2006.280.07:49:21.05#ibcon#about to read 3, iclass 4, count 0 2006.280.07:49:21.07#ibcon#read 3, iclass 4, count 0 2006.280.07:49:21.07#ibcon#about to read 4, iclass 4, count 0 2006.280.07:49:21.07#ibcon#read 4, iclass 4, count 0 2006.280.07:49:21.07#ibcon#about to read 5, iclass 4, count 0 2006.280.07:49:21.07#ibcon#read 5, iclass 4, count 0 2006.280.07:49:21.07#ibcon#about to read 6, iclass 4, count 0 2006.280.07:49:21.07#ibcon#read 6, iclass 4, count 0 2006.280.07:49:21.07#ibcon#end of sib2, iclass 4, count 0 2006.280.07:49:21.07#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:49:21.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:49:21.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:49:21.07#ibcon#*before write, iclass 4, count 0 2006.280.07:49:21.07#ibcon#enter sib2, iclass 4, count 0 2006.280.07:49:21.07#ibcon#flushed, iclass 4, count 0 2006.280.07:49:21.07#ibcon#about to write, iclass 4, count 0 2006.280.07:49:21.07#ibcon#wrote, iclass 4, count 0 2006.280.07:49:21.07#ibcon#about to read 3, iclass 4, count 0 2006.280.07:49:21.11#ibcon#read 3, iclass 4, count 0 2006.280.07:49:21.11#ibcon#about to read 4, iclass 4, count 0 2006.280.07:49:21.11#ibcon#read 4, iclass 4, count 0 2006.280.07:49:21.11#ibcon#about to read 5, iclass 4, count 0 2006.280.07:49:21.11#ibcon#read 5, iclass 4, count 0 2006.280.07:49:21.11#ibcon#about to read 6, iclass 4, count 0 2006.280.07:49:21.11#ibcon#read 6, iclass 4, count 0 2006.280.07:49:21.11#ibcon#end of sib2, iclass 4, count 0 2006.280.07:49:21.11#ibcon#*after write, iclass 4, count 0 2006.280.07:49:21.11#ibcon#*before return 0, iclass 4, count 0 2006.280.07:49:21.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:49:21.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:49:21.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:49:21.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:49:21.11$vc4f8/vb=1,4 2006.280.07:49:21.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:49:21.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:49:21.11#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:21.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:49:21.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:49:21.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:49:21.11#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:49:21.11#ibcon#first serial, iclass 6, count 2 2006.280.07:49:21.11#ibcon#enter sib2, iclass 6, count 2 2006.280.07:49:21.11#ibcon#flushed, iclass 6, count 2 2006.280.07:49:21.11#ibcon#about to write, iclass 6, count 2 2006.280.07:49:21.11#ibcon#wrote, iclass 6, count 2 2006.280.07:49:21.11#ibcon#about to read 3, iclass 6, count 2 2006.280.07:49:21.13#ibcon#read 3, iclass 6, count 2 2006.280.07:49:21.13#ibcon#about to read 4, iclass 6, count 2 2006.280.07:49:21.13#ibcon#read 4, iclass 6, count 2 2006.280.07:49:21.13#ibcon#about to read 5, iclass 6, count 2 2006.280.07:49:21.13#ibcon#read 5, iclass 6, count 2 2006.280.07:49:21.13#ibcon#about to read 6, iclass 6, count 2 2006.280.07:49:21.13#ibcon#read 6, iclass 6, count 2 2006.280.07:49:21.13#ibcon#end of sib2, iclass 6, count 2 2006.280.07:49:21.17#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:49:21.17#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:49:21.17#ibcon#[27=AT01-04\r\n] 2006.280.07:49:21.17#ibcon#*before write, iclass 6, count 2 2006.280.07:49:21.17#ibcon#enter sib2, iclass 6, count 2 2006.280.07:49:21.17#ibcon#flushed, iclass 6, count 2 2006.280.07:49:21.17#ibcon#about to write, iclass 6, count 2 2006.280.07:49:21.17#ibcon#wrote, iclass 6, count 2 2006.280.07:49:21.17#ibcon#about to read 3, iclass 6, count 2 2006.280.07:49:21.20#ibcon#read 3, iclass 6, count 2 2006.280.07:49:21.20#ibcon#about to read 4, iclass 6, count 2 2006.280.07:49:21.20#ibcon#read 4, iclass 6, count 2 2006.280.07:49:21.20#ibcon#about to read 5, iclass 6, count 2 2006.280.07:49:21.20#ibcon#read 5, iclass 6, count 2 2006.280.07:49:21.20#ibcon#about to read 6, iclass 6, count 2 2006.280.07:49:21.20#ibcon#read 6, iclass 6, count 2 2006.280.07:49:21.20#ibcon#end of sib2, iclass 6, count 2 2006.280.07:49:21.20#ibcon#*after write, iclass 6, count 2 2006.280.07:49:21.20#ibcon#*before return 0, iclass 6, count 2 2006.280.07:49:21.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:49:21.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:49:21.20#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:49:21.20#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:21.20#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:49:21.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:49:21.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:49:21.33#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:49:21.33#ibcon#first serial, iclass 6, count 0 2006.280.07:49:21.33#ibcon#enter sib2, iclass 6, count 0 2006.280.07:49:21.33#ibcon#flushed, iclass 6, count 0 2006.280.07:49:21.33#ibcon#about to write, iclass 6, count 0 2006.280.07:49:21.33#ibcon#wrote, iclass 6, count 0 2006.280.07:49:21.33#ibcon#about to read 3, iclass 6, count 0 2006.280.07:49:21.34#ibcon#read 3, iclass 6, count 0 2006.280.07:49:21.34#ibcon#about to read 4, iclass 6, count 0 2006.280.07:49:21.34#ibcon#read 4, iclass 6, count 0 2006.280.07:49:21.34#ibcon#about to read 5, iclass 6, count 0 2006.280.07:49:21.34#ibcon#read 5, iclass 6, count 0 2006.280.07:49:21.34#ibcon#about to read 6, iclass 6, count 0 2006.280.07:49:21.34#ibcon#read 6, iclass 6, count 0 2006.280.07:49:21.34#ibcon#end of sib2, iclass 6, count 0 2006.280.07:49:21.34#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:49:21.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:49:21.34#ibcon#[27=USB\r\n] 2006.280.07:49:21.34#ibcon#*before write, iclass 6, count 0 2006.280.07:49:21.34#ibcon#enter sib2, iclass 6, count 0 2006.280.07:49:21.34#ibcon#flushed, iclass 6, count 0 2006.280.07:49:21.34#ibcon#about to write, iclass 6, count 0 2006.280.07:49:21.34#ibcon#wrote, iclass 6, count 0 2006.280.07:49:21.34#ibcon#about to read 3, iclass 6, count 0 2006.280.07:49:21.37#ibcon#read 3, iclass 6, count 0 2006.280.07:49:21.37#ibcon#about to read 4, iclass 6, count 0 2006.280.07:49:21.37#ibcon#read 4, iclass 6, count 0 2006.280.07:49:21.37#ibcon#about to read 5, iclass 6, count 0 2006.280.07:49:21.37#ibcon#read 5, iclass 6, count 0 2006.280.07:49:21.37#ibcon#about to read 6, iclass 6, count 0 2006.280.07:49:21.37#ibcon#read 6, iclass 6, count 0 2006.280.07:49:21.37#ibcon#end of sib2, iclass 6, count 0 2006.280.07:49:21.37#ibcon#*after write, iclass 6, count 0 2006.280.07:49:21.37#ibcon#*before return 0, iclass 6, count 0 2006.280.07:49:21.37#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:49:21.37#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:49:21.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:49:21.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:49:21.37$vc4f8/vblo=2,640.99 2006.280.07:49:21.37#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:49:21.37#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:49:21.37#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:21.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:21.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:21.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:21.37#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:49:21.37#ibcon#first serial, iclass 10, count 0 2006.280.07:49:21.37#ibcon#enter sib2, iclass 10, count 0 2006.280.07:49:21.37#ibcon#flushed, iclass 10, count 0 2006.280.07:49:21.37#ibcon#about to write, iclass 10, count 0 2006.280.07:49:21.37#ibcon#wrote, iclass 10, count 0 2006.280.07:49:21.37#ibcon#about to read 3, iclass 10, count 0 2006.280.07:49:21.39#ibcon#read 3, iclass 10, count 0 2006.280.07:49:21.39#ibcon#about to read 4, iclass 10, count 0 2006.280.07:49:21.39#ibcon#read 4, iclass 10, count 0 2006.280.07:49:21.39#ibcon#about to read 5, iclass 10, count 0 2006.280.07:49:21.39#ibcon#read 5, iclass 10, count 0 2006.280.07:49:21.39#ibcon#about to read 6, iclass 10, count 0 2006.280.07:49:21.39#ibcon#read 6, iclass 10, count 0 2006.280.07:49:21.39#ibcon#end of sib2, iclass 10, count 0 2006.280.07:49:21.39#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:49:21.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:49:21.39#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:49:21.39#ibcon#*before write, iclass 10, count 0 2006.280.07:49:21.39#ibcon#enter sib2, iclass 10, count 0 2006.280.07:49:21.39#ibcon#flushed, iclass 10, count 0 2006.280.07:49:21.39#ibcon#about to write, iclass 10, count 0 2006.280.07:49:21.39#ibcon#wrote, iclass 10, count 0 2006.280.07:49:21.39#ibcon#about to read 3, iclass 10, count 0 2006.280.07:49:21.44#ibcon#read 3, iclass 10, count 0 2006.280.07:49:21.44#ibcon#about to read 4, iclass 10, count 0 2006.280.07:49:21.44#ibcon#read 4, iclass 10, count 0 2006.280.07:49:21.44#ibcon#about to read 5, iclass 10, count 0 2006.280.07:49:21.44#ibcon#read 5, iclass 10, count 0 2006.280.07:49:21.44#ibcon#about to read 6, iclass 10, count 0 2006.280.07:49:21.44#ibcon#read 6, iclass 10, count 0 2006.280.07:49:21.44#ibcon#end of sib2, iclass 10, count 0 2006.280.07:49:21.44#ibcon#*after write, iclass 10, count 0 2006.280.07:49:21.44#ibcon#*before return 0, iclass 10, count 0 2006.280.07:49:21.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:21.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:49:21.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:49:21.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:49:21.44$vc4f8/vb=2,5 2006.280.07:49:21.44#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:49:21.44#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:49:21.44#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:21.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:21.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:21.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:21.48#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:49:21.48#ibcon#first serial, iclass 12, count 2 2006.280.07:49:21.48#ibcon#enter sib2, iclass 12, count 2 2006.280.07:49:21.48#ibcon#flushed, iclass 12, count 2 2006.280.07:49:21.48#ibcon#about to write, iclass 12, count 2 2006.280.07:49:21.48#ibcon#wrote, iclass 12, count 2 2006.280.07:49:21.48#ibcon#about to read 3, iclass 12, count 2 2006.280.07:49:21.50#ibcon#read 3, iclass 12, count 2 2006.280.07:49:21.50#ibcon#about to read 4, iclass 12, count 2 2006.280.07:49:21.50#ibcon#read 4, iclass 12, count 2 2006.280.07:49:21.50#ibcon#about to read 5, iclass 12, count 2 2006.280.07:49:21.50#ibcon#read 5, iclass 12, count 2 2006.280.07:49:21.50#ibcon#about to read 6, iclass 12, count 2 2006.280.07:49:21.50#ibcon#read 6, iclass 12, count 2 2006.280.07:49:21.50#ibcon#end of sib2, iclass 12, count 2 2006.280.07:49:21.50#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:49:21.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:49:21.50#ibcon#[27=AT02-05\r\n] 2006.280.07:49:21.50#ibcon#*before write, iclass 12, count 2 2006.280.07:49:21.50#ibcon#enter sib2, iclass 12, count 2 2006.280.07:49:21.50#ibcon#flushed, iclass 12, count 2 2006.280.07:49:21.50#ibcon#about to write, iclass 12, count 2 2006.280.07:49:21.50#ibcon#wrote, iclass 12, count 2 2006.280.07:49:21.50#ibcon#about to read 3, iclass 12, count 2 2006.280.07:49:21.53#ibcon#read 3, iclass 12, count 2 2006.280.07:49:21.53#ibcon#about to read 4, iclass 12, count 2 2006.280.07:49:21.53#ibcon#read 4, iclass 12, count 2 2006.280.07:49:21.53#ibcon#about to read 5, iclass 12, count 2 2006.280.07:49:21.53#ibcon#read 5, iclass 12, count 2 2006.280.07:49:21.53#ibcon#about to read 6, iclass 12, count 2 2006.280.07:49:21.53#ibcon#read 6, iclass 12, count 2 2006.280.07:49:21.53#ibcon#end of sib2, iclass 12, count 2 2006.280.07:49:21.53#ibcon#*after write, iclass 12, count 2 2006.280.07:49:21.53#ibcon#*before return 0, iclass 12, count 2 2006.280.07:49:21.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:21.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:49:21.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:49:21.53#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:21.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:21.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:21.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:21.65#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:49:21.65#ibcon#first serial, iclass 12, count 0 2006.280.07:49:21.65#ibcon#enter sib2, iclass 12, count 0 2006.280.07:49:21.65#ibcon#flushed, iclass 12, count 0 2006.280.07:49:21.65#ibcon#about to write, iclass 12, count 0 2006.280.07:49:21.65#ibcon#wrote, iclass 12, count 0 2006.280.07:49:21.65#ibcon#about to read 3, iclass 12, count 0 2006.280.07:49:21.67#ibcon#read 3, iclass 12, count 0 2006.280.07:49:21.67#ibcon#about to read 4, iclass 12, count 0 2006.280.07:49:21.67#ibcon#read 4, iclass 12, count 0 2006.280.07:49:21.67#ibcon#about to read 5, iclass 12, count 0 2006.280.07:49:21.67#ibcon#read 5, iclass 12, count 0 2006.280.07:49:21.67#ibcon#about to read 6, iclass 12, count 0 2006.280.07:49:21.67#ibcon#read 6, iclass 12, count 0 2006.280.07:49:21.67#ibcon#end of sib2, iclass 12, count 0 2006.280.07:49:21.67#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:49:21.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:49:21.67#ibcon#[27=USB\r\n] 2006.280.07:49:21.67#ibcon#*before write, iclass 12, count 0 2006.280.07:49:21.67#ibcon#enter sib2, iclass 12, count 0 2006.280.07:49:21.67#ibcon#flushed, iclass 12, count 0 2006.280.07:49:21.67#ibcon#about to write, iclass 12, count 0 2006.280.07:49:21.67#ibcon#wrote, iclass 12, count 0 2006.280.07:49:21.67#ibcon#about to read 3, iclass 12, count 0 2006.280.07:49:21.70#ibcon#read 3, iclass 12, count 0 2006.280.07:49:21.70#ibcon#about to read 4, iclass 12, count 0 2006.280.07:49:21.70#ibcon#read 4, iclass 12, count 0 2006.280.07:49:21.70#ibcon#about to read 5, iclass 12, count 0 2006.280.07:49:21.70#ibcon#read 5, iclass 12, count 0 2006.280.07:49:21.70#ibcon#about to read 6, iclass 12, count 0 2006.280.07:49:21.70#ibcon#read 6, iclass 12, count 0 2006.280.07:49:21.70#ibcon#end of sib2, iclass 12, count 0 2006.280.07:49:21.70#ibcon#*after write, iclass 12, count 0 2006.280.07:49:21.70#ibcon#*before return 0, iclass 12, count 0 2006.280.07:49:21.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:21.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:49:21.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:49:21.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:49:21.70$vc4f8/vblo=3,656.99 2006.280.07:49:21.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:49:21.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:49:21.70#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:21.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:21.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:21.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:21.70#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:49:21.70#ibcon#first serial, iclass 14, count 0 2006.280.07:49:21.70#ibcon#enter sib2, iclass 14, count 0 2006.280.07:49:21.70#ibcon#flushed, iclass 14, count 0 2006.280.07:49:21.70#ibcon#about to write, iclass 14, count 0 2006.280.07:49:21.70#ibcon#wrote, iclass 14, count 0 2006.280.07:49:21.70#ibcon#about to read 3, iclass 14, count 0 2006.280.07:49:21.72#ibcon#read 3, iclass 14, count 0 2006.280.07:49:21.72#ibcon#about to read 4, iclass 14, count 0 2006.280.07:49:21.72#ibcon#read 4, iclass 14, count 0 2006.280.07:49:21.72#ibcon#about to read 5, iclass 14, count 0 2006.280.07:49:21.72#ibcon#read 5, iclass 14, count 0 2006.280.07:49:21.72#ibcon#about to read 6, iclass 14, count 0 2006.280.07:49:21.72#ibcon#read 6, iclass 14, count 0 2006.280.07:49:21.72#ibcon#end of sib2, iclass 14, count 0 2006.280.07:49:21.72#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:49:21.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:49:21.72#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:49:21.72#ibcon#*before write, iclass 14, count 0 2006.280.07:49:21.72#ibcon#enter sib2, iclass 14, count 0 2006.280.07:49:21.72#ibcon#flushed, iclass 14, count 0 2006.280.07:49:21.72#ibcon#about to write, iclass 14, count 0 2006.280.07:49:21.72#ibcon#wrote, iclass 14, count 0 2006.280.07:49:21.72#ibcon#about to read 3, iclass 14, count 0 2006.280.07:49:21.76#ibcon#read 3, iclass 14, count 0 2006.280.07:49:21.76#ibcon#about to read 4, iclass 14, count 0 2006.280.07:49:21.76#ibcon#read 4, iclass 14, count 0 2006.280.07:49:21.76#ibcon#about to read 5, iclass 14, count 0 2006.280.07:49:21.76#ibcon#read 5, iclass 14, count 0 2006.280.07:49:21.76#ibcon#about to read 6, iclass 14, count 0 2006.280.07:49:21.76#ibcon#read 6, iclass 14, count 0 2006.280.07:49:21.76#ibcon#end of sib2, iclass 14, count 0 2006.280.07:49:21.76#ibcon#*after write, iclass 14, count 0 2006.280.07:49:21.76#ibcon#*before return 0, iclass 14, count 0 2006.280.07:49:21.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:21.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:49:21.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:49:21.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:49:21.76$vc4f8/vb=3,4 2006.280.07:49:21.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:49:21.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:49:21.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:21.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:21.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:21.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:21.82#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:49:21.82#ibcon#first serial, iclass 16, count 2 2006.280.07:49:21.82#ibcon#enter sib2, iclass 16, count 2 2006.280.07:49:21.82#ibcon#flushed, iclass 16, count 2 2006.280.07:49:21.82#ibcon#about to write, iclass 16, count 2 2006.280.07:49:21.82#ibcon#wrote, iclass 16, count 2 2006.280.07:49:21.82#ibcon#about to read 3, iclass 16, count 2 2006.280.07:49:21.85#ibcon#read 3, iclass 16, count 2 2006.280.07:49:21.85#ibcon#about to read 4, iclass 16, count 2 2006.280.07:49:21.85#ibcon#read 4, iclass 16, count 2 2006.280.07:49:21.85#ibcon#about to read 5, iclass 16, count 2 2006.280.07:49:21.85#ibcon#read 5, iclass 16, count 2 2006.280.07:49:21.85#ibcon#about to read 6, iclass 16, count 2 2006.280.07:49:21.85#ibcon#read 6, iclass 16, count 2 2006.280.07:49:21.85#ibcon#end of sib2, iclass 16, count 2 2006.280.07:49:21.85#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:49:21.85#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:49:21.85#ibcon#[27=AT03-04\r\n] 2006.280.07:49:21.85#ibcon#*before write, iclass 16, count 2 2006.280.07:49:21.85#ibcon#enter sib2, iclass 16, count 2 2006.280.07:49:21.85#ibcon#flushed, iclass 16, count 2 2006.280.07:49:21.85#ibcon#about to write, iclass 16, count 2 2006.280.07:49:21.85#ibcon#wrote, iclass 16, count 2 2006.280.07:49:21.85#ibcon#about to read 3, iclass 16, count 2 2006.280.07:49:21.88#ibcon#read 3, iclass 16, count 2 2006.280.07:49:21.88#ibcon#about to read 4, iclass 16, count 2 2006.280.07:49:21.88#ibcon#read 4, iclass 16, count 2 2006.280.07:49:21.88#ibcon#about to read 5, iclass 16, count 2 2006.280.07:49:21.88#ibcon#read 5, iclass 16, count 2 2006.280.07:49:21.88#ibcon#about to read 6, iclass 16, count 2 2006.280.07:49:21.88#ibcon#read 6, iclass 16, count 2 2006.280.07:49:21.88#ibcon#end of sib2, iclass 16, count 2 2006.280.07:49:21.88#ibcon#*after write, iclass 16, count 2 2006.280.07:49:21.88#ibcon#*before return 0, iclass 16, count 2 2006.280.07:49:21.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:21.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:49:21.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:49:21.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:21.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:22.00#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:22.00#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:22.00#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:49:22.00#ibcon#first serial, iclass 16, count 0 2006.280.07:49:22.00#ibcon#enter sib2, iclass 16, count 0 2006.280.07:49:22.00#ibcon#flushed, iclass 16, count 0 2006.280.07:49:22.00#ibcon#about to write, iclass 16, count 0 2006.280.07:49:22.00#ibcon#wrote, iclass 16, count 0 2006.280.07:49:22.00#ibcon#about to read 3, iclass 16, count 0 2006.280.07:49:22.02#ibcon#read 3, iclass 16, count 0 2006.280.07:49:22.02#ibcon#about to read 4, iclass 16, count 0 2006.280.07:49:22.02#ibcon#read 4, iclass 16, count 0 2006.280.07:49:22.02#ibcon#about to read 5, iclass 16, count 0 2006.280.07:49:22.02#ibcon#read 5, iclass 16, count 0 2006.280.07:49:22.02#ibcon#about to read 6, iclass 16, count 0 2006.280.07:49:22.02#ibcon#read 6, iclass 16, count 0 2006.280.07:49:22.02#ibcon#end of sib2, iclass 16, count 0 2006.280.07:49:22.02#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:49:22.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:49:22.02#ibcon#[27=USB\r\n] 2006.280.07:49:22.02#ibcon#*before write, iclass 16, count 0 2006.280.07:49:22.02#ibcon#enter sib2, iclass 16, count 0 2006.280.07:49:22.02#ibcon#flushed, iclass 16, count 0 2006.280.07:49:22.02#ibcon#about to write, iclass 16, count 0 2006.280.07:49:22.02#ibcon#wrote, iclass 16, count 0 2006.280.07:49:22.02#ibcon#about to read 3, iclass 16, count 0 2006.280.07:49:22.05#ibcon#read 3, iclass 16, count 0 2006.280.07:49:22.05#ibcon#about to read 4, iclass 16, count 0 2006.280.07:49:22.05#ibcon#read 4, iclass 16, count 0 2006.280.07:49:22.05#ibcon#about to read 5, iclass 16, count 0 2006.280.07:49:22.05#ibcon#read 5, iclass 16, count 0 2006.280.07:49:22.05#ibcon#about to read 6, iclass 16, count 0 2006.280.07:49:22.05#ibcon#read 6, iclass 16, count 0 2006.280.07:49:22.05#ibcon#end of sib2, iclass 16, count 0 2006.280.07:49:22.05#ibcon#*after write, iclass 16, count 0 2006.280.07:49:22.05#ibcon#*before return 0, iclass 16, count 0 2006.280.07:49:22.05#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:22.05#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:49:22.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:49:22.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:49:22.05$vc4f8/vblo=4,712.99 2006.280.07:49:22.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:49:22.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:49:22.05#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:22.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:22.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:22.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:22.05#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:49:22.05#ibcon#first serial, iclass 18, count 0 2006.280.07:49:22.05#ibcon#enter sib2, iclass 18, count 0 2006.280.07:49:22.05#ibcon#flushed, iclass 18, count 0 2006.280.07:49:22.05#ibcon#about to write, iclass 18, count 0 2006.280.07:49:22.05#ibcon#wrote, iclass 18, count 0 2006.280.07:49:22.05#ibcon#about to read 3, iclass 18, count 0 2006.280.07:49:22.07#ibcon#read 3, iclass 18, count 0 2006.280.07:49:22.07#ibcon#about to read 4, iclass 18, count 0 2006.280.07:49:22.07#ibcon#read 4, iclass 18, count 0 2006.280.07:49:22.07#ibcon#about to read 5, iclass 18, count 0 2006.280.07:49:22.07#ibcon#read 5, iclass 18, count 0 2006.280.07:49:22.07#ibcon#about to read 6, iclass 18, count 0 2006.280.07:49:22.07#ibcon#read 6, iclass 18, count 0 2006.280.07:49:22.07#ibcon#end of sib2, iclass 18, count 0 2006.280.07:49:22.07#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:49:22.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:49:22.07#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:49:22.07#ibcon#*before write, iclass 18, count 0 2006.280.07:49:22.07#ibcon#enter sib2, iclass 18, count 0 2006.280.07:49:22.07#ibcon#flushed, iclass 18, count 0 2006.280.07:49:22.07#ibcon#about to write, iclass 18, count 0 2006.280.07:49:22.07#ibcon#wrote, iclass 18, count 0 2006.280.07:49:22.07#ibcon#about to read 3, iclass 18, count 0 2006.280.07:49:22.11#ibcon#read 3, iclass 18, count 0 2006.280.07:49:22.11#ibcon#about to read 4, iclass 18, count 0 2006.280.07:49:22.11#ibcon#read 4, iclass 18, count 0 2006.280.07:49:22.11#ibcon#about to read 5, iclass 18, count 0 2006.280.07:49:22.11#ibcon#read 5, iclass 18, count 0 2006.280.07:49:22.11#ibcon#about to read 6, iclass 18, count 0 2006.280.07:49:22.11#ibcon#read 6, iclass 18, count 0 2006.280.07:49:22.11#ibcon#end of sib2, iclass 18, count 0 2006.280.07:49:22.11#ibcon#*after write, iclass 18, count 0 2006.280.07:49:22.11#ibcon#*before return 0, iclass 18, count 0 2006.280.07:49:22.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:22.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:49:22.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:49:22.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:49:22.11$vc4f8/vb=4,4 2006.280.07:49:22.13#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:49:22.13#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:49:22.13#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:22.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:22.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:22.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:22.16#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:49:22.16#ibcon#first serial, iclass 20, count 2 2006.280.07:49:22.16#ibcon#enter sib2, iclass 20, count 2 2006.280.07:49:22.16#ibcon#flushed, iclass 20, count 2 2006.280.07:49:22.16#ibcon#about to write, iclass 20, count 2 2006.280.07:49:22.16#ibcon#wrote, iclass 20, count 2 2006.280.07:49:22.16#ibcon#about to read 3, iclass 20, count 2 2006.280.07:49:22.18#ibcon#read 3, iclass 20, count 2 2006.280.07:49:22.18#ibcon#about to read 4, iclass 20, count 2 2006.280.07:49:22.18#ibcon#read 4, iclass 20, count 2 2006.280.07:49:22.18#ibcon#about to read 5, iclass 20, count 2 2006.280.07:49:22.18#ibcon#read 5, iclass 20, count 2 2006.280.07:49:22.18#ibcon#about to read 6, iclass 20, count 2 2006.280.07:49:22.18#ibcon#read 6, iclass 20, count 2 2006.280.07:49:22.18#ibcon#end of sib2, iclass 20, count 2 2006.280.07:49:22.18#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:49:22.18#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:49:22.18#ibcon#[27=AT04-04\r\n] 2006.280.07:49:22.18#ibcon#*before write, iclass 20, count 2 2006.280.07:49:22.18#ibcon#enter sib2, iclass 20, count 2 2006.280.07:49:22.18#ibcon#flushed, iclass 20, count 2 2006.280.07:49:22.18#ibcon#about to write, iclass 20, count 2 2006.280.07:49:22.18#ibcon#wrote, iclass 20, count 2 2006.280.07:49:22.18#ibcon#about to read 3, iclass 20, count 2 2006.280.07:49:22.21#ibcon#read 3, iclass 20, count 2 2006.280.07:49:22.21#ibcon#about to read 4, iclass 20, count 2 2006.280.07:49:22.21#ibcon#read 4, iclass 20, count 2 2006.280.07:49:22.21#ibcon#about to read 5, iclass 20, count 2 2006.280.07:49:22.21#ibcon#read 5, iclass 20, count 2 2006.280.07:49:22.21#ibcon#about to read 6, iclass 20, count 2 2006.280.07:49:22.21#ibcon#read 6, iclass 20, count 2 2006.280.07:49:22.21#ibcon#end of sib2, iclass 20, count 2 2006.280.07:49:22.21#ibcon#*after write, iclass 20, count 2 2006.280.07:49:22.21#ibcon#*before return 0, iclass 20, count 2 2006.280.07:49:22.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:22.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:49:22.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:49:22.21#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:22.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:22.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:22.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:22.33#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:49:22.33#ibcon#first serial, iclass 20, count 0 2006.280.07:49:22.33#ibcon#enter sib2, iclass 20, count 0 2006.280.07:49:22.33#ibcon#flushed, iclass 20, count 0 2006.280.07:49:22.33#ibcon#about to write, iclass 20, count 0 2006.280.07:49:22.33#ibcon#wrote, iclass 20, count 0 2006.280.07:49:22.33#ibcon#about to read 3, iclass 20, count 0 2006.280.07:49:22.35#ibcon#read 3, iclass 20, count 0 2006.280.07:49:22.35#ibcon#about to read 4, iclass 20, count 0 2006.280.07:49:22.35#ibcon#read 4, iclass 20, count 0 2006.280.07:49:22.35#ibcon#about to read 5, iclass 20, count 0 2006.280.07:49:22.35#ibcon#read 5, iclass 20, count 0 2006.280.07:49:22.35#ibcon#about to read 6, iclass 20, count 0 2006.280.07:49:22.35#ibcon#read 6, iclass 20, count 0 2006.280.07:49:22.35#ibcon#end of sib2, iclass 20, count 0 2006.280.07:49:22.35#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:49:22.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:49:22.35#ibcon#[27=USB\r\n] 2006.280.07:49:22.35#ibcon#*before write, iclass 20, count 0 2006.280.07:49:22.35#ibcon#enter sib2, iclass 20, count 0 2006.280.07:49:22.35#ibcon#flushed, iclass 20, count 0 2006.280.07:49:22.35#ibcon#about to write, iclass 20, count 0 2006.280.07:49:22.35#ibcon#wrote, iclass 20, count 0 2006.280.07:49:22.35#ibcon#about to read 3, iclass 20, count 0 2006.280.07:49:22.38#ibcon#read 3, iclass 20, count 0 2006.280.07:49:22.38#ibcon#about to read 4, iclass 20, count 0 2006.280.07:49:22.38#ibcon#read 4, iclass 20, count 0 2006.280.07:49:22.38#ibcon#about to read 5, iclass 20, count 0 2006.280.07:49:22.38#ibcon#read 5, iclass 20, count 0 2006.280.07:49:22.38#ibcon#about to read 6, iclass 20, count 0 2006.280.07:49:22.38#ibcon#read 6, iclass 20, count 0 2006.280.07:49:22.38#ibcon#end of sib2, iclass 20, count 0 2006.280.07:49:22.38#ibcon#*after write, iclass 20, count 0 2006.280.07:49:22.38#ibcon#*before return 0, iclass 20, count 0 2006.280.07:49:22.38#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:22.38#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:49:22.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:49:22.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:49:22.38$vc4f8/vblo=5,744.99 2006.280.07:49:22.38#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.07:49:22.38#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.07:49:22.38#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:22.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:22.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:22.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:22.38#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:49:22.38#ibcon#first serial, iclass 22, count 0 2006.280.07:49:22.38#ibcon#enter sib2, iclass 22, count 0 2006.280.07:49:22.38#ibcon#flushed, iclass 22, count 0 2006.280.07:49:22.38#ibcon#about to write, iclass 22, count 0 2006.280.07:49:22.39#ibcon#wrote, iclass 22, count 0 2006.280.07:49:22.39#ibcon#about to read 3, iclass 22, count 0 2006.280.07:49:22.40#ibcon#read 3, iclass 22, count 0 2006.280.07:49:22.40#ibcon#about to read 4, iclass 22, count 0 2006.280.07:49:22.40#ibcon#read 4, iclass 22, count 0 2006.280.07:49:22.40#ibcon#about to read 5, iclass 22, count 0 2006.280.07:49:22.40#ibcon#read 5, iclass 22, count 0 2006.280.07:49:22.40#ibcon#about to read 6, iclass 22, count 0 2006.280.07:49:22.40#ibcon#read 6, iclass 22, count 0 2006.280.07:49:22.40#ibcon#end of sib2, iclass 22, count 0 2006.280.07:49:22.40#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:49:22.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:49:22.40#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:49:22.40#ibcon#*before write, iclass 22, count 0 2006.280.07:49:22.40#ibcon#enter sib2, iclass 22, count 0 2006.280.07:49:22.40#ibcon#flushed, iclass 22, count 0 2006.280.07:49:22.40#ibcon#about to write, iclass 22, count 0 2006.280.07:49:22.40#ibcon#wrote, iclass 22, count 0 2006.280.07:49:22.40#ibcon#about to read 3, iclass 22, count 0 2006.280.07:49:22.44#ibcon#read 3, iclass 22, count 0 2006.280.07:49:22.44#ibcon#about to read 4, iclass 22, count 0 2006.280.07:49:22.44#ibcon#read 4, iclass 22, count 0 2006.280.07:49:22.44#ibcon#about to read 5, iclass 22, count 0 2006.280.07:49:22.44#ibcon#read 5, iclass 22, count 0 2006.280.07:49:22.44#ibcon#about to read 6, iclass 22, count 0 2006.280.07:49:22.44#ibcon#read 6, iclass 22, count 0 2006.280.07:49:22.44#ibcon#end of sib2, iclass 22, count 0 2006.280.07:49:22.44#ibcon#*after write, iclass 22, count 0 2006.280.07:49:22.44#ibcon#*before return 0, iclass 22, count 0 2006.280.07:49:22.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:22.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.07:49:22.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:49:22.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:49:22.44$vc4f8/vb=5,4 2006.280.07:49:22.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.07:49:22.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.07:49:22.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:22.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:22.49#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:22.49#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:22.49#ibcon#enter wrdev, iclass 24, count 2 2006.280.07:49:22.49#ibcon#first serial, iclass 24, count 2 2006.280.07:49:22.49#ibcon#enter sib2, iclass 24, count 2 2006.280.07:49:22.49#ibcon#flushed, iclass 24, count 2 2006.280.07:49:22.49#ibcon#about to write, iclass 24, count 2 2006.280.07:49:22.49#ibcon#wrote, iclass 24, count 2 2006.280.07:49:22.49#ibcon#about to read 3, iclass 24, count 2 2006.280.07:49:22.52#ibcon#read 3, iclass 24, count 2 2006.280.07:49:22.52#ibcon#about to read 4, iclass 24, count 2 2006.280.07:49:22.52#ibcon#read 4, iclass 24, count 2 2006.280.07:49:22.52#ibcon#about to read 5, iclass 24, count 2 2006.280.07:49:22.52#ibcon#read 5, iclass 24, count 2 2006.280.07:49:22.52#ibcon#about to read 6, iclass 24, count 2 2006.280.07:49:22.52#ibcon#read 6, iclass 24, count 2 2006.280.07:49:22.52#ibcon#end of sib2, iclass 24, count 2 2006.280.07:49:22.52#ibcon#*mode == 0, iclass 24, count 2 2006.280.07:49:22.52#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.07:49:22.52#ibcon#[27=AT05-04\r\n] 2006.280.07:49:22.52#ibcon#*before write, iclass 24, count 2 2006.280.07:49:22.52#ibcon#enter sib2, iclass 24, count 2 2006.280.07:49:22.52#ibcon#flushed, iclass 24, count 2 2006.280.07:49:22.52#ibcon#about to write, iclass 24, count 2 2006.280.07:49:22.52#ibcon#wrote, iclass 24, count 2 2006.280.07:49:22.52#ibcon#about to read 3, iclass 24, count 2 2006.280.07:49:22.54#ibcon#read 3, iclass 24, count 2 2006.280.07:49:22.54#ibcon#about to read 4, iclass 24, count 2 2006.280.07:49:22.54#ibcon#read 4, iclass 24, count 2 2006.280.07:49:22.54#ibcon#about to read 5, iclass 24, count 2 2006.280.07:49:22.54#ibcon#read 5, iclass 24, count 2 2006.280.07:49:22.54#ibcon#about to read 6, iclass 24, count 2 2006.280.07:49:22.54#ibcon#read 6, iclass 24, count 2 2006.280.07:49:22.54#ibcon#end of sib2, iclass 24, count 2 2006.280.07:49:22.54#ibcon#*after write, iclass 24, count 2 2006.280.07:49:22.54#ibcon#*before return 0, iclass 24, count 2 2006.280.07:49:22.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:22.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.07:49:22.54#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.07:49:22.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:22.54#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:22.66#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:22.66#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:22.66#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:49:22.66#ibcon#first serial, iclass 24, count 0 2006.280.07:49:22.66#ibcon#enter sib2, iclass 24, count 0 2006.280.07:49:22.66#ibcon#flushed, iclass 24, count 0 2006.280.07:49:22.66#ibcon#about to write, iclass 24, count 0 2006.280.07:49:22.66#ibcon#wrote, iclass 24, count 0 2006.280.07:49:22.66#ibcon#about to read 3, iclass 24, count 0 2006.280.07:49:22.68#ibcon#read 3, iclass 24, count 0 2006.280.07:49:22.68#ibcon#about to read 4, iclass 24, count 0 2006.280.07:49:22.68#ibcon#read 4, iclass 24, count 0 2006.280.07:49:22.68#ibcon#about to read 5, iclass 24, count 0 2006.280.07:49:22.68#ibcon#read 5, iclass 24, count 0 2006.280.07:49:22.68#ibcon#about to read 6, iclass 24, count 0 2006.280.07:49:22.68#ibcon#read 6, iclass 24, count 0 2006.280.07:49:22.68#ibcon#end of sib2, iclass 24, count 0 2006.280.07:49:22.68#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:49:22.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:49:22.68#ibcon#[27=USB\r\n] 2006.280.07:49:22.68#ibcon#*before write, iclass 24, count 0 2006.280.07:49:22.68#ibcon#enter sib2, iclass 24, count 0 2006.280.07:49:22.68#ibcon#flushed, iclass 24, count 0 2006.280.07:49:22.68#ibcon#about to write, iclass 24, count 0 2006.280.07:49:22.68#ibcon#wrote, iclass 24, count 0 2006.280.07:49:22.68#ibcon#about to read 3, iclass 24, count 0 2006.280.07:49:22.71#ibcon#read 3, iclass 24, count 0 2006.280.07:49:22.71#ibcon#about to read 4, iclass 24, count 0 2006.280.07:49:22.71#ibcon#read 4, iclass 24, count 0 2006.280.07:49:22.71#ibcon#about to read 5, iclass 24, count 0 2006.280.07:49:22.71#ibcon#read 5, iclass 24, count 0 2006.280.07:49:22.71#ibcon#about to read 6, iclass 24, count 0 2006.280.07:49:22.71#ibcon#read 6, iclass 24, count 0 2006.280.07:49:22.71#ibcon#end of sib2, iclass 24, count 0 2006.280.07:49:22.71#ibcon#*after write, iclass 24, count 0 2006.280.07:49:22.71#ibcon#*before return 0, iclass 24, count 0 2006.280.07:49:22.71#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:22.71#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.07:49:22.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:49:22.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:49:22.71$vc4f8/vblo=6,752.99 2006.280.07:49:22.71#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:49:22.71#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:49:22.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:49:22.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:22.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:22.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:22.71#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:49:22.71#ibcon#first serial, iclass 26, count 0 2006.280.07:49:22.71#ibcon#enter sib2, iclass 26, count 0 2006.280.07:49:22.71#ibcon#flushed, iclass 26, count 0 2006.280.07:49:22.71#ibcon#about to write, iclass 26, count 0 2006.280.07:49:22.71#ibcon#wrote, iclass 26, count 0 2006.280.07:49:22.71#ibcon#about to read 3, iclass 26, count 0 2006.280.07:49:22.73#ibcon#read 3, iclass 26, count 0 2006.280.07:49:22.75#ibcon#about to read 4, iclass 26, count 0 2006.280.07:49:22.75#ibcon#read 4, iclass 26, count 0 2006.280.07:49:22.75#ibcon#about to read 5, iclass 26, count 0 2006.280.07:49:22.75#ibcon#read 5, iclass 26, count 0 2006.280.07:49:22.75#ibcon#about to read 6, iclass 26, count 0 2006.280.07:49:22.75#ibcon#read 6, iclass 26, count 0 2006.280.07:49:22.75#ibcon#end of sib2, iclass 26, count 0 2006.280.07:49:22.75#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:49:22.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:49:22.75#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:49:22.75#ibcon#*before write, iclass 26, count 0 2006.280.07:49:22.75#ibcon#enter sib2, iclass 26, count 0 2006.280.07:49:22.75#ibcon#flushed, iclass 26, count 0 2006.280.07:49:22.75#ibcon#about to write, iclass 26, count 0 2006.280.07:49:22.75#ibcon#wrote, iclass 26, count 0 2006.280.07:49:22.75#ibcon#about to read 3, iclass 26, count 0 2006.280.07:49:22.79#ibcon#read 3, iclass 26, count 0 2006.280.07:49:22.79#ibcon#about to read 4, iclass 26, count 0 2006.280.07:49:22.79#ibcon#read 4, iclass 26, count 0 2006.280.07:49:22.79#ibcon#about to read 5, iclass 26, count 0 2006.280.07:49:22.79#ibcon#read 5, iclass 26, count 0 2006.280.07:49:22.79#ibcon#about to read 6, iclass 26, count 0 2006.280.07:49:22.79#ibcon#read 6, iclass 26, count 0 2006.280.07:49:22.79#ibcon#end of sib2, iclass 26, count 0 2006.280.07:49:22.79#ibcon#*after write, iclass 26, count 0 2006.280.07:49:22.79#ibcon#*before return 0, iclass 26, count 0 2006.280.07:49:22.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:22.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:49:22.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:49:22.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:49:22.79$vc4f8/vb=6,4 2006.280.07:49:22.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:49:22.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:49:22.79#ibcon#ireg 11 cls_cnt 2 2006.280.07:49:22.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:22.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:22.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:22.83#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:49:22.83#ibcon#first serial, iclass 28, count 2 2006.280.07:49:22.83#ibcon#enter sib2, iclass 28, count 2 2006.280.07:49:22.83#ibcon#flushed, iclass 28, count 2 2006.280.07:49:22.83#ibcon#about to write, iclass 28, count 2 2006.280.07:49:22.83#ibcon#wrote, iclass 28, count 2 2006.280.07:49:22.83#ibcon#about to read 3, iclass 28, count 2 2006.280.07:49:22.85#ibcon#read 3, iclass 28, count 2 2006.280.07:49:22.85#ibcon#about to read 4, iclass 28, count 2 2006.280.07:49:22.85#ibcon#read 4, iclass 28, count 2 2006.280.07:49:22.85#ibcon#about to read 5, iclass 28, count 2 2006.280.07:49:22.85#ibcon#read 5, iclass 28, count 2 2006.280.07:49:22.85#ibcon#about to read 6, iclass 28, count 2 2006.280.07:49:22.85#ibcon#read 6, iclass 28, count 2 2006.280.07:49:22.85#ibcon#end of sib2, iclass 28, count 2 2006.280.07:49:22.85#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:49:22.85#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:49:22.85#ibcon#[27=AT06-04\r\n] 2006.280.07:49:22.85#ibcon#*before write, iclass 28, count 2 2006.280.07:49:22.85#ibcon#enter sib2, iclass 28, count 2 2006.280.07:49:22.85#ibcon#flushed, iclass 28, count 2 2006.280.07:49:22.85#ibcon#about to write, iclass 28, count 2 2006.280.07:49:22.85#ibcon#wrote, iclass 28, count 2 2006.280.07:49:22.85#ibcon#about to read 3, iclass 28, count 2 2006.280.07:49:22.88#ibcon#read 3, iclass 28, count 2 2006.280.07:49:22.88#ibcon#about to read 4, iclass 28, count 2 2006.280.07:49:22.88#ibcon#read 4, iclass 28, count 2 2006.280.07:49:22.88#ibcon#about to read 5, iclass 28, count 2 2006.280.07:49:22.88#ibcon#read 5, iclass 28, count 2 2006.280.07:49:22.88#ibcon#about to read 6, iclass 28, count 2 2006.280.07:49:22.88#ibcon#read 6, iclass 28, count 2 2006.280.07:49:22.88#ibcon#end of sib2, iclass 28, count 2 2006.280.07:49:22.88#ibcon#*after write, iclass 28, count 2 2006.280.07:49:22.88#ibcon#*before return 0, iclass 28, count 2 2006.280.07:49:22.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:22.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:49:22.88#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:49:22.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:49:22.88#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:23.00#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:23.00#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:23.00#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:49:23.00#ibcon#first serial, iclass 28, count 0 2006.280.07:49:23.00#ibcon#enter sib2, iclass 28, count 0 2006.280.07:49:23.00#ibcon#flushed, iclass 28, count 0 2006.280.07:49:23.00#ibcon#about to write, iclass 28, count 0 2006.280.07:49:23.00#ibcon#wrote, iclass 28, count 0 2006.280.07:49:23.00#ibcon#about to read 3, iclass 28, count 0 2006.280.07:49:23.02#ibcon#read 3, iclass 28, count 0 2006.280.07:49:23.02#ibcon#about to read 4, iclass 28, count 0 2006.280.07:49:23.02#ibcon#read 4, iclass 28, count 0 2006.280.07:49:23.02#ibcon#about to read 5, iclass 28, count 0 2006.280.07:49:23.02#ibcon#read 5, iclass 28, count 0 2006.280.07:49:23.02#ibcon#about to read 6, iclass 28, count 0 2006.280.07:49:23.02#ibcon#read 6, iclass 28, count 0 2006.280.07:49:23.02#ibcon#end of sib2, iclass 28, count 0 2006.280.07:49:23.02#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:49:23.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:49:23.02#ibcon#[27=USB\r\n] 2006.280.07:49:23.02#ibcon#*before write, iclass 28, count 0 2006.280.07:49:23.02#ibcon#enter sib2, iclass 28, count 0 2006.280.07:49:23.02#ibcon#flushed, iclass 28, count 0 2006.280.07:49:23.02#ibcon#about to write, iclass 28, count 0 2006.280.07:49:23.02#ibcon#wrote, iclass 28, count 0 2006.280.07:49:23.02#ibcon#about to read 3, iclass 28, count 0 2006.280.07:49:23.05#ibcon#read 3, iclass 28, count 0 2006.280.07:49:23.05#ibcon#about to read 4, iclass 28, count 0 2006.280.07:49:23.05#ibcon#read 4, iclass 28, count 0 2006.280.07:49:23.05#ibcon#about to read 5, iclass 28, count 0 2006.280.07:49:23.05#ibcon#read 5, iclass 28, count 0 2006.280.07:49:23.05#ibcon#about to read 6, iclass 28, count 0 2006.280.07:49:23.05#ibcon#read 6, iclass 28, count 0 2006.280.07:49:23.05#ibcon#end of sib2, iclass 28, count 0 2006.280.07:49:23.05#ibcon#*after write, iclass 28, count 0 2006.280.07:49:23.05#ibcon#*before return 0, iclass 28, count 0 2006.280.07:49:23.05#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:23.05#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:49:23.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:49:23.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:49:23.05$vc4f8/vabw=wide 2006.280.07:49:23.05#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:49:23.05#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:49:23.05#ibcon#ireg 8 cls_cnt 0 2006.280.07:49:23.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:23.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:23.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:23.05#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:49:23.05#ibcon#first serial, iclass 30, count 0 2006.280.07:49:23.05#ibcon#enter sib2, iclass 30, count 0 2006.280.07:49:23.05#ibcon#flushed, iclass 30, count 0 2006.280.07:49:23.05#ibcon#about to write, iclass 30, count 0 2006.280.07:49:23.05#ibcon#wrote, iclass 30, count 0 2006.280.07:49:23.05#ibcon#about to read 3, iclass 30, count 0 2006.280.07:49:23.07#ibcon#read 3, iclass 30, count 0 2006.280.07:49:23.07#ibcon#about to read 4, iclass 30, count 0 2006.280.07:49:23.07#ibcon#read 4, iclass 30, count 0 2006.280.07:49:23.07#ibcon#about to read 5, iclass 30, count 0 2006.280.07:49:23.07#ibcon#read 5, iclass 30, count 0 2006.280.07:49:23.07#ibcon#about to read 6, iclass 30, count 0 2006.280.07:49:23.07#ibcon#read 6, iclass 30, count 0 2006.280.07:49:23.07#ibcon#end of sib2, iclass 30, count 0 2006.280.07:49:23.07#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:49:23.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:49:23.07#ibcon#[25=BW32\r\n] 2006.280.07:49:23.07#ibcon#*before write, iclass 30, count 0 2006.280.07:49:23.07#ibcon#enter sib2, iclass 30, count 0 2006.280.07:49:23.07#ibcon#flushed, iclass 30, count 0 2006.280.07:49:23.07#ibcon#about to write, iclass 30, count 0 2006.280.07:49:23.07#ibcon#wrote, iclass 30, count 0 2006.280.07:49:23.07#ibcon#about to read 3, iclass 30, count 0 2006.280.07:49:23.10#ibcon#read 3, iclass 30, count 0 2006.280.07:49:23.10#ibcon#about to read 4, iclass 30, count 0 2006.280.07:49:23.10#ibcon#read 4, iclass 30, count 0 2006.280.07:49:23.10#ibcon#about to read 5, iclass 30, count 0 2006.280.07:49:23.10#ibcon#read 5, iclass 30, count 0 2006.280.07:49:23.10#ibcon#about to read 6, iclass 30, count 0 2006.280.07:49:23.10#ibcon#read 6, iclass 30, count 0 2006.280.07:49:23.10#ibcon#end of sib2, iclass 30, count 0 2006.280.07:49:23.10#ibcon#*after write, iclass 30, count 0 2006.280.07:49:23.10#ibcon#*before return 0, iclass 30, count 0 2006.280.07:49:23.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:23.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:49:23.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:49:23.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:49:23.10$vc4f8/vbbw=wide 2006.280.07:49:23.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:49:23.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:49:23.10#ibcon#ireg 8 cls_cnt 0 2006.280.07:49:23.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:49:23.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:49:23.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:49:23.17#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:49:23.17#ibcon#first serial, iclass 32, count 0 2006.280.07:49:23.17#ibcon#enter sib2, iclass 32, count 0 2006.280.07:49:23.17#ibcon#flushed, iclass 32, count 0 2006.280.07:49:23.17#ibcon#about to write, iclass 32, count 0 2006.280.07:49:23.17#ibcon#wrote, iclass 32, count 0 2006.280.07:49:23.17#ibcon#about to read 3, iclass 32, count 0 2006.280.07:49:23.19#ibcon#read 3, iclass 32, count 0 2006.280.07:49:23.19#ibcon#about to read 4, iclass 32, count 0 2006.280.07:49:23.19#ibcon#read 4, iclass 32, count 0 2006.280.07:49:23.19#ibcon#about to read 5, iclass 32, count 0 2006.280.07:49:23.19#ibcon#read 5, iclass 32, count 0 2006.280.07:49:23.19#ibcon#about to read 6, iclass 32, count 0 2006.280.07:49:23.19#ibcon#read 6, iclass 32, count 0 2006.280.07:49:23.19#ibcon#end of sib2, iclass 32, count 0 2006.280.07:49:23.19#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:49:23.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:49:23.19#ibcon#[27=BW32\r\n] 2006.280.07:49:23.19#ibcon#*before write, iclass 32, count 0 2006.280.07:49:23.19#ibcon#enter sib2, iclass 32, count 0 2006.280.07:49:23.19#ibcon#flushed, iclass 32, count 0 2006.280.07:49:23.19#ibcon#about to write, iclass 32, count 0 2006.280.07:49:23.19#ibcon#wrote, iclass 32, count 0 2006.280.07:49:23.19#ibcon#about to read 3, iclass 32, count 0 2006.280.07:49:23.22#ibcon#read 3, iclass 32, count 0 2006.280.07:49:23.22#ibcon#about to read 4, iclass 32, count 0 2006.280.07:49:23.22#ibcon#read 4, iclass 32, count 0 2006.280.07:49:23.22#ibcon#about to read 5, iclass 32, count 0 2006.280.07:49:23.22#ibcon#read 5, iclass 32, count 0 2006.280.07:49:23.22#ibcon#about to read 6, iclass 32, count 0 2006.280.07:49:23.22#ibcon#read 6, iclass 32, count 0 2006.280.07:49:23.22#ibcon#end of sib2, iclass 32, count 0 2006.280.07:49:23.22#ibcon#*after write, iclass 32, count 0 2006.280.07:49:23.22#ibcon#*before return 0, iclass 32, count 0 2006.280.07:49:23.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:49:23.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:49:23.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:49:23.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:49:23.22$4f8m12a/ifd4f 2006.280.07:49:23.22$ifd4f/lo= 2006.280.07:49:23.22$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:49:23.22$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:49:23.22$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:49:23.22$ifd4f/patch= 2006.280.07:49:23.22$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:49:23.22$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:49:23.22$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:49:23.22$4f8m12a/"form=m,16.000,1:2 2006.280.07:49:23.22$4f8m12a/"tpicd 2006.280.07:49:23.23$4f8m12a/echo=off 2006.280.07:49:23.23$4f8m12a/xlog=off 2006.280.07:49:23.23:!2006.280.07:49:50 2006.280.07:49:32.14#trakl#Source acquired 2006.280.07:49:32.14#flagr#flagr/antenna,acquired 2006.280.07:49:50.01:preob 2006.280.07:49:51.14/onsource/TRACKING 2006.280.07:49:51.14:!2006.280.07:50:00 2006.280.07:50:00.00:data_valid=on 2006.280.07:50:00.00:midob 2006.280.07:50:00.14/onsource/TRACKING 2006.280.07:50:00.14/wx/21.27,986.9,60 2006.280.07:50:00.23/cable/+6.4823E-03 2006.280.07:50:01.32/va/01,07,usb,yes,32,34 2006.280.07:50:01.32/va/02,06,usb,yes,30,31 2006.280.07:50:01.32/va/03,06,usb,yes,28,28 2006.280.07:50:01.32/va/04,06,usb,yes,31,33 2006.280.07:50:01.32/va/05,07,usb,yes,28,30 2006.280.07:50:01.32/va/06,06,usb,yes,27,27 2006.280.07:50:01.32/va/07,06,usb,yes,28,28 2006.280.07:50:01.32/va/08,06,usb,yes,30,29 2006.280.07:50:01.55/valo/01,532.99,yes,locked 2006.280.07:50:01.55/valo/02,572.99,yes,locked 2006.280.07:50:01.55/valo/03,672.99,yes,locked 2006.280.07:50:01.55/valo/04,832.99,yes,locked 2006.280.07:50:01.55/valo/05,652.99,yes,locked 2006.280.07:50:01.55/valo/06,772.99,yes,locked 2006.280.07:50:01.55/valo/07,832.99,yes,locked 2006.280.07:50:01.55/valo/08,852.99,yes,locked 2006.280.07:50:02.64/vb/01,04,usb,yes,30,28 2006.280.07:50:02.64/vb/02,05,usb,yes,28,29 2006.280.07:50:02.64/vb/03,04,usb,yes,28,32 2006.280.07:50:02.64/vb/04,04,usb,yes,29,29 2006.280.07:50:02.64/vb/05,04,usb,yes,27,31 2006.280.07:50:02.64/vb/06,04,usb,yes,27,31 2006.280.07:50:02.64/vb/07,04,usb,yes,30,30 2006.280.07:50:02.64/vb/08,04,usb,yes,27,31 2006.280.07:50:02.88/vblo/01,632.99,yes,locked 2006.280.07:50:02.88/vblo/02,640.99,yes,locked 2006.280.07:50:02.88/vblo/03,656.99,yes,locked 2006.280.07:50:02.88/vblo/04,712.99,yes,locked 2006.280.07:50:02.88/vblo/05,744.99,yes,locked 2006.280.07:50:02.88/vblo/06,752.99,yes,locked 2006.280.07:50:02.88/vblo/07,734.99,yes,locked 2006.280.07:50:02.88/vblo/08,744.99,yes,locked 2006.280.07:50:03.03/vabw/8 2006.280.07:50:03.18/vbbw/8 2006.280.07:50:03.27/xfe/off,on,12.2 2006.280.07:50:03.65/ifatt/23,28,28,28 2006.280.07:50:04.08/fmout-gps/S +3.17E-07 2006.280.07:50:04.11:!2006.280.07:51:00 2006.280.07:51:00.01:data_valid=off 2006.280.07:51:00.02:postob 2006.280.07:51:00.19/cable/+6.4827E-03 2006.280.07:51:00.20/wx/21.23,986.9,60 2006.280.07:51:01.07/fmout-gps/S +3.17E-07 2006.280.07:51:01.08:scan_name=280-0751,k06280,60 2006.280.07:51:01.08:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.280.07:51:01.14#flagr#flagr/antenna,new-source 2006.280.07:51:02.14:checkk5 2006.280.07:51:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:51:02.95/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:51:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:51:03.75/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:51:04.12/chk_obsdata//k5ts1/T2800750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:51:04.55/chk_obsdata//k5ts2/T2800750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:51:04.93/chk_obsdata//k5ts3/T2800750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:51:05.31/chk_obsdata//k5ts4/T2800750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:51:06.06/k5log//k5ts1_log_newline 2006.280.07:51:06.86/k5log//k5ts2_log_newline 2006.280.07:51:07.68/k5log//k5ts3_log_newline 2006.280.07:51:08.38/k5log//k5ts4_log_newline 2006.280.07:51:08.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:51:08.40:4f8m12a=1 2006.280.07:51:08.40$4f8m12a/echo=on 2006.280.07:51:08.40$4f8m12a/pcalon 2006.280.07:51:08.40$pcalon/"no phase cal control is implemented here 2006.280.07:51:08.40$4f8m12a/"tpicd=stop 2006.280.07:51:08.40$4f8m12a/vc4f8 2006.280.07:51:08.40$vc4f8/valo=1,532.99 2006.280.07:51:08.41#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.07:51:08.41#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.07:51:08.41#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:08.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:08.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:08.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:08.41#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:51:08.41#ibcon#first serial, iclass 5, count 0 2006.280.07:51:08.41#ibcon#enter sib2, iclass 5, count 0 2006.280.07:51:08.41#ibcon#flushed, iclass 5, count 0 2006.280.07:51:08.41#ibcon#about to write, iclass 5, count 0 2006.280.07:51:08.41#ibcon#wrote, iclass 5, count 0 2006.280.07:51:08.41#ibcon#about to read 3, iclass 5, count 0 2006.280.07:51:08.43#ibcon#read 3, iclass 5, count 0 2006.280.07:51:08.43#ibcon#about to read 4, iclass 5, count 0 2006.280.07:51:08.43#ibcon#read 4, iclass 5, count 0 2006.280.07:51:08.43#ibcon#about to read 5, iclass 5, count 0 2006.280.07:51:08.43#ibcon#read 5, iclass 5, count 0 2006.280.07:51:08.43#ibcon#about to read 6, iclass 5, count 0 2006.280.07:51:08.43#ibcon#read 6, iclass 5, count 0 2006.280.07:51:08.43#ibcon#end of sib2, iclass 5, count 0 2006.280.07:51:08.43#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:51:08.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:51:08.43#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:51:08.43#ibcon#*before write, iclass 5, count 0 2006.280.07:51:08.43#ibcon#enter sib2, iclass 5, count 0 2006.280.07:51:08.43#ibcon#flushed, iclass 5, count 0 2006.280.07:51:08.43#ibcon#about to write, iclass 5, count 0 2006.280.07:51:08.43#ibcon#wrote, iclass 5, count 0 2006.280.07:51:08.43#ibcon#about to read 3, iclass 5, count 0 2006.280.07:51:08.48#ibcon#read 3, iclass 5, count 0 2006.280.07:51:08.48#ibcon#about to read 4, iclass 5, count 0 2006.280.07:51:08.48#ibcon#read 4, iclass 5, count 0 2006.280.07:51:08.48#ibcon#about to read 5, iclass 5, count 0 2006.280.07:51:08.48#ibcon#read 5, iclass 5, count 0 2006.280.07:51:08.48#ibcon#about to read 6, iclass 5, count 0 2006.280.07:51:08.48#ibcon#read 6, iclass 5, count 0 2006.280.07:51:08.48#ibcon#end of sib2, iclass 5, count 0 2006.280.07:51:08.48#ibcon#*after write, iclass 5, count 0 2006.280.07:51:08.48#ibcon#*before return 0, iclass 5, count 0 2006.280.07:51:08.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:08.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:08.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:51:08.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:51:08.48$vc4f8/va=1,7 2006.280.07:51:08.48#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.07:51:08.48#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.07:51:08.48#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:08.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:08.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:08.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:08.48#ibcon#enter wrdev, iclass 7, count 2 2006.280.07:51:08.48#ibcon#first serial, iclass 7, count 2 2006.280.07:51:08.48#ibcon#enter sib2, iclass 7, count 2 2006.280.07:51:08.48#ibcon#flushed, iclass 7, count 2 2006.280.07:51:08.48#ibcon#about to write, iclass 7, count 2 2006.280.07:51:08.48#ibcon#wrote, iclass 7, count 2 2006.280.07:51:08.48#ibcon#about to read 3, iclass 7, count 2 2006.280.07:51:08.50#ibcon#read 3, iclass 7, count 2 2006.280.07:51:08.50#ibcon#about to read 4, iclass 7, count 2 2006.280.07:51:08.50#ibcon#read 4, iclass 7, count 2 2006.280.07:51:08.51#ibcon#about to read 5, iclass 7, count 2 2006.280.07:51:08.51#ibcon#read 5, iclass 7, count 2 2006.280.07:51:08.51#ibcon#about to read 6, iclass 7, count 2 2006.280.07:51:08.51#ibcon#read 6, iclass 7, count 2 2006.280.07:51:08.51#ibcon#end of sib2, iclass 7, count 2 2006.280.07:51:08.51#ibcon#*mode == 0, iclass 7, count 2 2006.280.07:51:08.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.07:51:08.51#ibcon#[25=AT01-07\r\n] 2006.280.07:51:08.51#ibcon#*before write, iclass 7, count 2 2006.280.07:51:08.51#ibcon#enter sib2, iclass 7, count 2 2006.280.07:51:08.51#ibcon#flushed, iclass 7, count 2 2006.280.07:51:08.51#ibcon#about to write, iclass 7, count 2 2006.280.07:51:08.51#ibcon#wrote, iclass 7, count 2 2006.280.07:51:08.51#ibcon#about to read 3, iclass 7, count 2 2006.280.07:51:08.54#ibcon#read 3, iclass 7, count 2 2006.280.07:51:08.54#ibcon#about to read 4, iclass 7, count 2 2006.280.07:51:08.54#ibcon#read 4, iclass 7, count 2 2006.280.07:51:08.54#ibcon#about to read 5, iclass 7, count 2 2006.280.07:51:08.54#ibcon#read 5, iclass 7, count 2 2006.280.07:51:08.54#ibcon#about to read 6, iclass 7, count 2 2006.280.07:51:08.54#ibcon#read 6, iclass 7, count 2 2006.280.07:51:08.54#ibcon#end of sib2, iclass 7, count 2 2006.280.07:51:08.54#ibcon#*after write, iclass 7, count 2 2006.280.07:51:08.54#ibcon#*before return 0, iclass 7, count 2 2006.280.07:51:08.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:08.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:08.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.07:51:08.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:08.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:08.67#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:08.67#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:08.67#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:51:08.67#ibcon#first serial, iclass 7, count 0 2006.280.07:51:08.67#ibcon#enter sib2, iclass 7, count 0 2006.280.07:51:08.67#ibcon#flushed, iclass 7, count 0 2006.280.07:51:08.67#ibcon#about to write, iclass 7, count 0 2006.280.07:51:08.67#ibcon#wrote, iclass 7, count 0 2006.280.07:51:08.67#ibcon#about to read 3, iclass 7, count 0 2006.280.07:51:08.68#ibcon#read 3, iclass 7, count 0 2006.280.07:51:08.68#ibcon#about to read 4, iclass 7, count 0 2006.280.07:51:08.68#ibcon#read 4, iclass 7, count 0 2006.280.07:51:08.68#ibcon#about to read 5, iclass 7, count 0 2006.280.07:51:08.68#ibcon#read 5, iclass 7, count 0 2006.280.07:51:08.68#ibcon#about to read 6, iclass 7, count 0 2006.280.07:51:08.68#ibcon#read 6, iclass 7, count 0 2006.280.07:51:08.68#ibcon#end of sib2, iclass 7, count 0 2006.280.07:51:08.68#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:51:08.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:51:08.68#ibcon#[25=USB\r\n] 2006.280.07:51:08.68#ibcon#*before write, iclass 7, count 0 2006.280.07:51:08.68#ibcon#enter sib2, iclass 7, count 0 2006.280.07:51:08.68#ibcon#flushed, iclass 7, count 0 2006.280.07:51:08.68#ibcon#about to write, iclass 7, count 0 2006.280.07:51:08.68#ibcon#wrote, iclass 7, count 0 2006.280.07:51:08.68#ibcon#about to read 3, iclass 7, count 0 2006.280.07:51:08.71#ibcon#read 3, iclass 7, count 0 2006.280.07:51:08.71#ibcon#about to read 4, iclass 7, count 0 2006.280.07:51:08.71#ibcon#read 4, iclass 7, count 0 2006.280.07:51:08.71#ibcon#about to read 5, iclass 7, count 0 2006.280.07:51:08.71#ibcon#read 5, iclass 7, count 0 2006.280.07:51:08.71#ibcon#about to read 6, iclass 7, count 0 2006.280.07:51:08.71#ibcon#read 6, iclass 7, count 0 2006.280.07:51:08.71#ibcon#end of sib2, iclass 7, count 0 2006.280.07:51:08.71#ibcon#*after write, iclass 7, count 0 2006.280.07:51:08.71#ibcon#*before return 0, iclass 7, count 0 2006.280.07:51:08.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:08.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:08.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:51:08.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:51:08.71$vc4f8/valo=2,572.99 2006.280.07:51:08.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.07:51:08.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.07:51:08.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:08.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:08.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:08.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:08.71#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:51:08.71#ibcon#first serial, iclass 11, count 0 2006.280.07:51:08.71#ibcon#enter sib2, iclass 11, count 0 2006.280.07:51:08.71#ibcon#flushed, iclass 11, count 0 2006.280.07:51:08.71#ibcon#about to write, iclass 11, count 0 2006.280.07:51:08.71#ibcon#wrote, iclass 11, count 0 2006.280.07:51:08.71#ibcon#about to read 3, iclass 11, count 0 2006.280.07:51:08.73#ibcon#read 3, iclass 11, count 0 2006.280.07:51:08.73#ibcon#about to read 4, iclass 11, count 0 2006.280.07:51:08.73#ibcon#read 4, iclass 11, count 0 2006.280.07:51:08.73#ibcon#about to read 5, iclass 11, count 0 2006.280.07:51:08.73#ibcon#read 5, iclass 11, count 0 2006.280.07:51:08.73#ibcon#about to read 6, iclass 11, count 0 2006.280.07:51:08.73#ibcon#read 6, iclass 11, count 0 2006.280.07:51:08.73#ibcon#end of sib2, iclass 11, count 0 2006.280.07:51:08.73#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:51:08.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:51:08.73#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:51:08.73#ibcon#*before write, iclass 11, count 0 2006.280.07:51:08.73#ibcon#enter sib2, iclass 11, count 0 2006.280.07:51:08.73#ibcon#flushed, iclass 11, count 0 2006.280.07:51:08.73#ibcon#about to write, iclass 11, count 0 2006.280.07:51:08.73#ibcon#wrote, iclass 11, count 0 2006.280.07:51:08.73#ibcon#about to read 3, iclass 11, count 0 2006.280.07:51:08.78#ibcon#read 3, iclass 11, count 0 2006.280.07:51:08.78#ibcon#about to read 4, iclass 11, count 0 2006.280.07:51:08.78#ibcon#read 4, iclass 11, count 0 2006.280.07:51:08.78#ibcon#about to read 5, iclass 11, count 0 2006.280.07:51:08.78#ibcon#read 5, iclass 11, count 0 2006.280.07:51:08.78#ibcon#about to read 6, iclass 11, count 0 2006.280.07:51:08.78#ibcon#read 6, iclass 11, count 0 2006.280.07:51:08.78#ibcon#end of sib2, iclass 11, count 0 2006.280.07:51:08.78#ibcon#*after write, iclass 11, count 0 2006.280.07:51:08.78#ibcon#*before return 0, iclass 11, count 0 2006.280.07:51:08.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:08.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:08.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:51:08.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:51:08.78$vc4f8/va=2,6 2006.280.07:51:08.78#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.07:51:08.78#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.07:51:08.78#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:08.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:08.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:08.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:08.82#ibcon#enter wrdev, iclass 13, count 2 2006.280.07:51:08.82#ibcon#first serial, iclass 13, count 2 2006.280.07:51:08.82#ibcon#enter sib2, iclass 13, count 2 2006.280.07:51:08.82#ibcon#flushed, iclass 13, count 2 2006.280.07:51:08.82#ibcon#about to write, iclass 13, count 2 2006.280.07:51:08.82#ibcon#wrote, iclass 13, count 2 2006.280.07:51:08.82#ibcon#about to read 3, iclass 13, count 2 2006.280.07:51:08.84#ibcon#read 3, iclass 13, count 2 2006.280.07:51:08.84#ibcon#about to read 4, iclass 13, count 2 2006.280.07:51:08.84#ibcon#read 4, iclass 13, count 2 2006.280.07:51:08.84#ibcon#about to read 5, iclass 13, count 2 2006.280.07:51:08.84#ibcon#read 5, iclass 13, count 2 2006.280.07:51:08.84#ibcon#about to read 6, iclass 13, count 2 2006.280.07:51:08.84#ibcon#read 6, iclass 13, count 2 2006.280.07:51:08.84#ibcon#end of sib2, iclass 13, count 2 2006.280.07:51:08.84#ibcon#*mode == 0, iclass 13, count 2 2006.280.07:51:08.84#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.07:51:08.84#ibcon#[25=AT02-06\r\n] 2006.280.07:51:08.84#ibcon#*before write, iclass 13, count 2 2006.280.07:51:08.84#ibcon#enter sib2, iclass 13, count 2 2006.280.07:51:08.84#ibcon#flushed, iclass 13, count 2 2006.280.07:51:08.84#ibcon#about to write, iclass 13, count 2 2006.280.07:51:08.84#ibcon#wrote, iclass 13, count 2 2006.280.07:51:08.84#ibcon#about to read 3, iclass 13, count 2 2006.280.07:51:08.87#ibcon#read 3, iclass 13, count 2 2006.280.07:51:08.87#ibcon#about to read 4, iclass 13, count 2 2006.280.07:51:08.87#ibcon#read 4, iclass 13, count 2 2006.280.07:51:08.87#ibcon#about to read 5, iclass 13, count 2 2006.280.07:51:08.87#ibcon#read 5, iclass 13, count 2 2006.280.07:51:08.87#ibcon#about to read 6, iclass 13, count 2 2006.280.07:51:08.87#ibcon#read 6, iclass 13, count 2 2006.280.07:51:08.87#ibcon#end of sib2, iclass 13, count 2 2006.280.07:51:08.87#ibcon#*after write, iclass 13, count 2 2006.280.07:51:08.87#ibcon#*before return 0, iclass 13, count 2 2006.280.07:51:08.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:08.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:08.87#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.07:51:08.87#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:08.87#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:08.99#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:08.99#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:08.99#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:51:08.99#ibcon#first serial, iclass 13, count 0 2006.280.07:51:08.99#ibcon#enter sib2, iclass 13, count 0 2006.280.07:51:08.99#ibcon#flushed, iclass 13, count 0 2006.280.07:51:08.99#ibcon#about to write, iclass 13, count 0 2006.280.07:51:08.99#ibcon#wrote, iclass 13, count 0 2006.280.07:51:08.99#ibcon#about to read 3, iclass 13, count 0 2006.280.07:51:09.01#ibcon#read 3, iclass 13, count 0 2006.280.07:51:09.01#ibcon#about to read 4, iclass 13, count 0 2006.280.07:51:09.01#ibcon#read 4, iclass 13, count 0 2006.280.07:51:09.01#ibcon#about to read 5, iclass 13, count 0 2006.280.07:51:09.01#ibcon#read 5, iclass 13, count 0 2006.280.07:51:09.01#ibcon#about to read 6, iclass 13, count 0 2006.280.07:51:09.01#ibcon#read 6, iclass 13, count 0 2006.280.07:51:09.01#ibcon#end of sib2, iclass 13, count 0 2006.280.07:51:09.01#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:51:09.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:51:09.01#ibcon#[25=USB\r\n] 2006.280.07:51:09.01#ibcon#*before write, iclass 13, count 0 2006.280.07:51:09.01#ibcon#enter sib2, iclass 13, count 0 2006.280.07:51:09.01#ibcon#flushed, iclass 13, count 0 2006.280.07:51:09.01#ibcon#about to write, iclass 13, count 0 2006.280.07:51:09.01#ibcon#wrote, iclass 13, count 0 2006.280.07:51:09.01#ibcon#about to read 3, iclass 13, count 0 2006.280.07:51:09.04#ibcon#read 3, iclass 13, count 0 2006.280.07:51:09.04#ibcon#about to read 4, iclass 13, count 0 2006.280.07:51:09.04#ibcon#read 4, iclass 13, count 0 2006.280.07:51:09.04#ibcon#about to read 5, iclass 13, count 0 2006.280.07:51:09.04#ibcon#read 5, iclass 13, count 0 2006.280.07:51:09.04#ibcon#about to read 6, iclass 13, count 0 2006.280.07:51:09.04#ibcon#read 6, iclass 13, count 0 2006.280.07:51:09.04#ibcon#end of sib2, iclass 13, count 0 2006.280.07:51:09.04#ibcon#*after write, iclass 13, count 0 2006.280.07:51:09.04#ibcon#*before return 0, iclass 13, count 0 2006.280.07:51:09.04#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:09.04#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:09.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:51:09.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:51:09.04$vc4f8/valo=3,672.99 2006.280.07:51:09.04#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:51:09.04#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:51:09.04#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:09.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:09.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:09.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:09.04#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:51:09.04#ibcon#first serial, iclass 15, count 0 2006.280.07:51:09.04#ibcon#enter sib2, iclass 15, count 0 2006.280.07:51:09.04#ibcon#flushed, iclass 15, count 0 2006.280.07:51:09.04#ibcon#about to write, iclass 15, count 0 2006.280.07:51:09.04#ibcon#wrote, iclass 15, count 0 2006.280.07:51:09.04#ibcon#about to read 3, iclass 15, count 0 2006.280.07:51:09.06#ibcon#read 3, iclass 15, count 0 2006.280.07:51:09.06#ibcon#about to read 4, iclass 15, count 0 2006.280.07:51:09.06#ibcon#read 4, iclass 15, count 0 2006.280.07:51:09.06#ibcon#about to read 5, iclass 15, count 0 2006.280.07:51:09.06#ibcon#read 5, iclass 15, count 0 2006.280.07:51:09.06#ibcon#about to read 6, iclass 15, count 0 2006.280.07:51:09.06#ibcon#read 6, iclass 15, count 0 2006.280.07:51:09.06#ibcon#end of sib2, iclass 15, count 0 2006.280.07:51:09.06#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:51:09.06#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:51:09.06#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:51:09.06#ibcon#*before write, iclass 15, count 0 2006.280.07:51:09.06#ibcon#enter sib2, iclass 15, count 0 2006.280.07:51:09.06#ibcon#flushed, iclass 15, count 0 2006.280.07:51:09.06#ibcon#about to write, iclass 15, count 0 2006.280.07:51:09.06#ibcon#wrote, iclass 15, count 0 2006.280.07:51:09.06#ibcon#about to read 3, iclass 15, count 0 2006.280.07:51:09.10#ibcon#read 3, iclass 15, count 0 2006.280.07:51:09.10#ibcon#about to read 4, iclass 15, count 0 2006.280.07:51:09.10#ibcon#read 4, iclass 15, count 0 2006.280.07:51:09.10#ibcon#about to read 5, iclass 15, count 0 2006.280.07:51:09.10#ibcon#read 5, iclass 15, count 0 2006.280.07:51:09.10#ibcon#about to read 6, iclass 15, count 0 2006.280.07:51:09.10#ibcon#read 6, iclass 15, count 0 2006.280.07:51:09.10#ibcon#end of sib2, iclass 15, count 0 2006.280.07:51:09.10#ibcon#*after write, iclass 15, count 0 2006.280.07:51:09.10#ibcon#*before return 0, iclass 15, count 0 2006.280.07:51:09.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:09.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:09.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:51:09.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:51:09.10$vc4f8/va=3,6 2006.280.07:51:09.10#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.07:51:09.10#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.07:51:09.10#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:09.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:09.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:09.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:09.16#ibcon#enter wrdev, iclass 17, count 2 2006.280.07:51:09.16#ibcon#first serial, iclass 17, count 2 2006.280.07:51:09.16#ibcon#enter sib2, iclass 17, count 2 2006.280.07:51:09.16#ibcon#flushed, iclass 17, count 2 2006.280.07:51:09.16#ibcon#about to write, iclass 17, count 2 2006.280.07:51:09.16#ibcon#wrote, iclass 17, count 2 2006.280.07:51:09.16#ibcon#about to read 3, iclass 17, count 2 2006.280.07:51:09.18#ibcon#read 3, iclass 17, count 2 2006.280.07:51:09.18#ibcon#about to read 4, iclass 17, count 2 2006.280.07:51:09.18#ibcon#read 4, iclass 17, count 2 2006.280.07:51:09.18#ibcon#about to read 5, iclass 17, count 2 2006.280.07:51:09.18#ibcon#read 5, iclass 17, count 2 2006.280.07:51:09.18#ibcon#about to read 6, iclass 17, count 2 2006.280.07:51:09.18#ibcon#read 6, iclass 17, count 2 2006.280.07:51:09.18#ibcon#end of sib2, iclass 17, count 2 2006.280.07:51:09.18#ibcon#*mode == 0, iclass 17, count 2 2006.280.07:51:09.18#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.07:51:09.18#ibcon#[25=AT03-06\r\n] 2006.280.07:51:09.18#ibcon#*before write, iclass 17, count 2 2006.280.07:51:09.18#ibcon#enter sib2, iclass 17, count 2 2006.280.07:51:09.18#ibcon#flushed, iclass 17, count 2 2006.280.07:51:09.18#ibcon#about to write, iclass 17, count 2 2006.280.07:51:09.18#ibcon#wrote, iclass 17, count 2 2006.280.07:51:09.18#ibcon#about to read 3, iclass 17, count 2 2006.280.07:51:09.21#ibcon#read 3, iclass 17, count 2 2006.280.07:51:09.21#ibcon#about to read 4, iclass 17, count 2 2006.280.07:51:09.21#ibcon#read 4, iclass 17, count 2 2006.280.07:51:09.21#ibcon#about to read 5, iclass 17, count 2 2006.280.07:51:09.21#ibcon#read 5, iclass 17, count 2 2006.280.07:51:09.21#ibcon#about to read 6, iclass 17, count 2 2006.280.07:51:09.21#ibcon#read 6, iclass 17, count 2 2006.280.07:51:09.21#ibcon#end of sib2, iclass 17, count 2 2006.280.07:51:09.21#ibcon#*after write, iclass 17, count 2 2006.280.07:51:09.21#ibcon#*before return 0, iclass 17, count 2 2006.280.07:51:09.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:09.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:09.21#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.07:51:09.21#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:09.21#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:09.33#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:09.33#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:09.33#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:51:09.33#ibcon#first serial, iclass 17, count 0 2006.280.07:51:09.33#ibcon#enter sib2, iclass 17, count 0 2006.280.07:51:09.33#ibcon#flushed, iclass 17, count 0 2006.280.07:51:09.33#ibcon#about to write, iclass 17, count 0 2006.280.07:51:09.33#ibcon#wrote, iclass 17, count 0 2006.280.07:51:09.33#ibcon#about to read 3, iclass 17, count 0 2006.280.07:51:09.35#ibcon#read 3, iclass 17, count 0 2006.280.07:51:09.35#ibcon#about to read 4, iclass 17, count 0 2006.280.07:51:09.35#ibcon#read 4, iclass 17, count 0 2006.280.07:51:09.35#ibcon#about to read 5, iclass 17, count 0 2006.280.07:51:09.35#ibcon#read 5, iclass 17, count 0 2006.280.07:51:09.35#ibcon#about to read 6, iclass 17, count 0 2006.280.07:51:09.35#ibcon#read 6, iclass 17, count 0 2006.280.07:51:09.35#ibcon#end of sib2, iclass 17, count 0 2006.280.07:51:09.35#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:51:09.35#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:51:09.35#ibcon#[25=USB\r\n] 2006.280.07:51:09.35#ibcon#*before write, iclass 17, count 0 2006.280.07:51:09.35#ibcon#enter sib2, iclass 17, count 0 2006.280.07:51:09.35#ibcon#flushed, iclass 17, count 0 2006.280.07:51:09.35#ibcon#about to write, iclass 17, count 0 2006.280.07:51:09.35#ibcon#wrote, iclass 17, count 0 2006.280.07:51:09.35#ibcon#about to read 3, iclass 17, count 0 2006.280.07:51:09.38#ibcon#read 3, iclass 17, count 0 2006.280.07:51:09.38#ibcon#about to read 4, iclass 17, count 0 2006.280.07:51:09.38#ibcon#read 4, iclass 17, count 0 2006.280.07:51:09.38#ibcon#about to read 5, iclass 17, count 0 2006.280.07:51:09.38#ibcon#read 5, iclass 17, count 0 2006.280.07:51:09.38#ibcon#about to read 6, iclass 17, count 0 2006.280.07:51:09.38#ibcon#read 6, iclass 17, count 0 2006.280.07:51:09.38#ibcon#end of sib2, iclass 17, count 0 2006.280.07:51:09.38#ibcon#*after write, iclass 17, count 0 2006.280.07:51:09.38#ibcon#*before return 0, iclass 17, count 0 2006.280.07:51:09.38#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:09.38#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:09.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:51:09.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:51:09.38$vc4f8/valo=4,832.99 2006.280.07:51:09.38#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:51:09.38#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:51:09.38#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:09.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:09.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:09.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:09.38#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:51:09.38#ibcon#first serial, iclass 19, count 0 2006.280.07:51:09.38#ibcon#enter sib2, iclass 19, count 0 2006.280.07:51:09.38#ibcon#flushed, iclass 19, count 0 2006.280.07:51:09.38#ibcon#about to write, iclass 19, count 0 2006.280.07:51:09.38#ibcon#wrote, iclass 19, count 0 2006.280.07:51:09.38#ibcon#about to read 3, iclass 19, count 0 2006.280.07:51:09.40#ibcon#read 3, iclass 19, count 0 2006.280.07:51:09.40#ibcon#about to read 4, iclass 19, count 0 2006.280.07:51:09.40#ibcon#read 4, iclass 19, count 0 2006.280.07:51:09.40#ibcon#about to read 5, iclass 19, count 0 2006.280.07:51:09.40#ibcon#read 5, iclass 19, count 0 2006.280.07:51:09.40#ibcon#about to read 6, iclass 19, count 0 2006.280.07:51:09.40#ibcon#read 6, iclass 19, count 0 2006.280.07:51:09.40#ibcon#end of sib2, iclass 19, count 0 2006.280.07:51:09.40#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:51:09.40#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:51:09.40#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:51:09.40#ibcon#*before write, iclass 19, count 0 2006.280.07:51:09.40#ibcon#enter sib2, iclass 19, count 0 2006.280.07:51:09.40#ibcon#flushed, iclass 19, count 0 2006.280.07:51:09.40#ibcon#about to write, iclass 19, count 0 2006.280.07:51:09.40#ibcon#wrote, iclass 19, count 0 2006.280.07:51:09.40#ibcon#about to read 3, iclass 19, count 0 2006.280.07:51:09.44#ibcon#read 3, iclass 19, count 0 2006.280.07:51:09.44#ibcon#about to read 4, iclass 19, count 0 2006.280.07:51:09.44#ibcon#read 4, iclass 19, count 0 2006.280.07:51:09.44#ibcon#about to read 5, iclass 19, count 0 2006.280.07:51:09.44#ibcon#read 5, iclass 19, count 0 2006.280.07:51:09.44#ibcon#about to read 6, iclass 19, count 0 2006.280.07:51:09.44#ibcon#read 6, iclass 19, count 0 2006.280.07:51:09.44#ibcon#end of sib2, iclass 19, count 0 2006.280.07:51:09.44#ibcon#*after write, iclass 19, count 0 2006.280.07:51:09.44#ibcon#*before return 0, iclass 19, count 0 2006.280.07:51:09.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:09.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:09.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:51:09.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:51:09.44$vc4f8/va=4,6 2006.280.07:51:09.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:51:09.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:51:09.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:09.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:09.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:09.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:09.49#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:51:09.49#ibcon#first serial, iclass 21, count 2 2006.280.07:51:09.49#ibcon#enter sib2, iclass 21, count 2 2006.280.07:51:09.49#ibcon#flushed, iclass 21, count 2 2006.280.07:51:09.49#ibcon#about to write, iclass 21, count 2 2006.280.07:51:09.49#ibcon#wrote, iclass 21, count 2 2006.280.07:51:09.49#ibcon#about to read 3, iclass 21, count 2 2006.280.07:51:09.52#ibcon#read 3, iclass 21, count 2 2006.280.07:51:09.52#ibcon#about to read 4, iclass 21, count 2 2006.280.07:51:09.52#ibcon#read 4, iclass 21, count 2 2006.280.07:51:09.52#ibcon#about to read 5, iclass 21, count 2 2006.280.07:51:09.52#ibcon#read 5, iclass 21, count 2 2006.280.07:51:09.52#ibcon#about to read 6, iclass 21, count 2 2006.280.07:51:09.52#ibcon#read 6, iclass 21, count 2 2006.280.07:51:09.52#ibcon#end of sib2, iclass 21, count 2 2006.280.07:51:09.52#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:51:09.52#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:51:09.52#ibcon#[25=AT04-06\r\n] 2006.280.07:51:09.52#ibcon#*before write, iclass 21, count 2 2006.280.07:51:09.52#ibcon#enter sib2, iclass 21, count 2 2006.280.07:51:09.52#ibcon#flushed, iclass 21, count 2 2006.280.07:51:09.52#ibcon#about to write, iclass 21, count 2 2006.280.07:51:09.52#ibcon#wrote, iclass 21, count 2 2006.280.07:51:09.52#ibcon#about to read 3, iclass 21, count 2 2006.280.07:51:09.54#ibcon#read 3, iclass 21, count 2 2006.280.07:51:09.54#ibcon#about to read 4, iclass 21, count 2 2006.280.07:51:09.54#ibcon#read 4, iclass 21, count 2 2006.280.07:51:09.54#ibcon#about to read 5, iclass 21, count 2 2006.280.07:51:09.54#ibcon#read 5, iclass 21, count 2 2006.280.07:51:09.54#ibcon#about to read 6, iclass 21, count 2 2006.280.07:51:09.54#ibcon#read 6, iclass 21, count 2 2006.280.07:51:09.54#ibcon#end of sib2, iclass 21, count 2 2006.280.07:51:09.54#ibcon#*after write, iclass 21, count 2 2006.280.07:51:09.54#ibcon#*before return 0, iclass 21, count 2 2006.280.07:51:09.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:09.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:09.54#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:51:09.54#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:09.54#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:09.66#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:09.66#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:09.66#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:51:09.66#ibcon#first serial, iclass 21, count 0 2006.280.07:51:09.66#ibcon#enter sib2, iclass 21, count 0 2006.280.07:51:09.66#ibcon#flushed, iclass 21, count 0 2006.280.07:51:09.66#ibcon#about to write, iclass 21, count 0 2006.280.07:51:09.66#ibcon#wrote, iclass 21, count 0 2006.280.07:51:09.66#ibcon#about to read 3, iclass 21, count 0 2006.280.07:51:09.68#ibcon#read 3, iclass 21, count 0 2006.280.07:51:09.68#ibcon#about to read 4, iclass 21, count 0 2006.280.07:51:09.68#ibcon#read 4, iclass 21, count 0 2006.280.07:51:09.68#ibcon#about to read 5, iclass 21, count 0 2006.280.07:51:09.68#ibcon#read 5, iclass 21, count 0 2006.280.07:51:09.68#ibcon#about to read 6, iclass 21, count 0 2006.280.07:51:09.68#ibcon#read 6, iclass 21, count 0 2006.280.07:51:09.68#ibcon#end of sib2, iclass 21, count 0 2006.280.07:51:09.68#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:51:09.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:51:09.68#ibcon#[25=USB\r\n] 2006.280.07:51:09.68#ibcon#*before write, iclass 21, count 0 2006.280.07:51:09.68#ibcon#enter sib2, iclass 21, count 0 2006.280.07:51:09.68#ibcon#flushed, iclass 21, count 0 2006.280.07:51:09.68#ibcon#about to write, iclass 21, count 0 2006.280.07:51:09.68#ibcon#wrote, iclass 21, count 0 2006.280.07:51:09.68#ibcon#about to read 3, iclass 21, count 0 2006.280.07:51:09.71#ibcon#read 3, iclass 21, count 0 2006.280.07:51:09.71#ibcon#about to read 4, iclass 21, count 0 2006.280.07:51:09.71#ibcon#read 4, iclass 21, count 0 2006.280.07:51:09.71#ibcon#about to read 5, iclass 21, count 0 2006.280.07:51:09.71#ibcon#read 5, iclass 21, count 0 2006.280.07:51:09.71#ibcon#about to read 6, iclass 21, count 0 2006.280.07:51:09.71#ibcon#read 6, iclass 21, count 0 2006.280.07:51:09.71#ibcon#end of sib2, iclass 21, count 0 2006.280.07:51:09.71#ibcon#*after write, iclass 21, count 0 2006.280.07:51:09.71#ibcon#*before return 0, iclass 21, count 0 2006.280.07:51:09.71#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:09.71#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:09.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:51:09.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:51:09.71$vc4f8/valo=5,652.99 2006.280.07:51:09.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:51:09.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:51:09.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:09.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:09.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:09.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:09.71#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:51:09.71#ibcon#first serial, iclass 23, count 0 2006.280.07:51:09.71#ibcon#enter sib2, iclass 23, count 0 2006.280.07:51:09.71#ibcon#flushed, iclass 23, count 0 2006.280.07:51:09.71#ibcon#about to write, iclass 23, count 0 2006.280.07:51:09.71#ibcon#wrote, iclass 23, count 0 2006.280.07:51:09.71#ibcon#about to read 3, iclass 23, count 0 2006.280.07:51:09.73#ibcon#read 3, iclass 23, count 0 2006.280.07:51:09.75#ibcon#about to read 4, iclass 23, count 0 2006.280.07:51:09.75#ibcon#read 4, iclass 23, count 0 2006.280.07:51:09.75#ibcon#about to read 5, iclass 23, count 0 2006.280.07:51:09.75#ibcon#read 5, iclass 23, count 0 2006.280.07:51:09.75#ibcon#about to read 6, iclass 23, count 0 2006.280.07:51:09.75#ibcon#read 6, iclass 23, count 0 2006.280.07:51:09.75#ibcon#end of sib2, iclass 23, count 0 2006.280.07:51:09.75#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:51:09.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:51:09.75#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:51:09.75#ibcon#*before write, iclass 23, count 0 2006.280.07:51:09.75#ibcon#enter sib2, iclass 23, count 0 2006.280.07:51:09.75#ibcon#flushed, iclass 23, count 0 2006.280.07:51:09.75#ibcon#about to write, iclass 23, count 0 2006.280.07:51:09.75#ibcon#wrote, iclass 23, count 0 2006.280.07:51:09.75#ibcon#about to read 3, iclass 23, count 0 2006.280.07:51:09.79#ibcon#read 3, iclass 23, count 0 2006.280.07:51:09.79#ibcon#about to read 4, iclass 23, count 0 2006.280.07:51:09.79#ibcon#read 4, iclass 23, count 0 2006.280.07:51:09.79#ibcon#about to read 5, iclass 23, count 0 2006.280.07:51:09.79#ibcon#read 5, iclass 23, count 0 2006.280.07:51:09.79#ibcon#about to read 6, iclass 23, count 0 2006.280.07:51:09.79#ibcon#read 6, iclass 23, count 0 2006.280.07:51:09.79#ibcon#end of sib2, iclass 23, count 0 2006.280.07:51:09.79#ibcon#*after write, iclass 23, count 0 2006.280.07:51:09.79#ibcon#*before return 0, iclass 23, count 0 2006.280.07:51:09.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:09.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:09.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:51:09.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:51:09.79$vc4f8/va=5,7 2006.280.07:51:09.79#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.07:51:09.79#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.07:51:09.79#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:09.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:09.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:09.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:09.83#ibcon#enter wrdev, iclass 25, count 2 2006.280.07:51:09.83#ibcon#first serial, iclass 25, count 2 2006.280.07:51:09.83#ibcon#enter sib2, iclass 25, count 2 2006.280.07:51:09.83#ibcon#flushed, iclass 25, count 2 2006.280.07:51:09.83#ibcon#about to write, iclass 25, count 2 2006.280.07:51:09.83#ibcon#wrote, iclass 25, count 2 2006.280.07:51:09.83#ibcon#about to read 3, iclass 25, count 2 2006.280.07:51:09.85#ibcon#read 3, iclass 25, count 2 2006.280.07:51:09.85#ibcon#about to read 4, iclass 25, count 2 2006.280.07:51:09.85#ibcon#read 4, iclass 25, count 2 2006.280.07:51:09.85#ibcon#about to read 5, iclass 25, count 2 2006.280.07:51:09.85#ibcon#read 5, iclass 25, count 2 2006.280.07:51:09.85#ibcon#about to read 6, iclass 25, count 2 2006.280.07:51:09.85#ibcon#read 6, iclass 25, count 2 2006.280.07:51:09.85#ibcon#end of sib2, iclass 25, count 2 2006.280.07:51:09.85#ibcon#*mode == 0, iclass 25, count 2 2006.280.07:51:09.85#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.07:51:09.85#ibcon#[25=AT05-07\r\n] 2006.280.07:51:09.85#ibcon#*before write, iclass 25, count 2 2006.280.07:51:09.85#ibcon#enter sib2, iclass 25, count 2 2006.280.07:51:09.85#ibcon#flushed, iclass 25, count 2 2006.280.07:51:09.85#ibcon#about to write, iclass 25, count 2 2006.280.07:51:09.85#ibcon#wrote, iclass 25, count 2 2006.280.07:51:09.85#ibcon#about to read 3, iclass 25, count 2 2006.280.07:51:09.88#ibcon#read 3, iclass 25, count 2 2006.280.07:51:09.88#ibcon#about to read 4, iclass 25, count 2 2006.280.07:51:09.88#ibcon#read 4, iclass 25, count 2 2006.280.07:51:09.88#ibcon#about to read 5, iclass 25, count 2 2006.280.07:51:09.88#ibcon#read 5, iclass 25, count 2 2006.280.07:51:09.88#ibcon#about to read 6, iclass 25, count 2 2006.280.07:51:09.88#ibcon#read 6, iclass 25, count 2 2006.280.07:51:09.88#ibcon#end of sib2, iclass 25, count 2 2006.280.07:51:09.88#ibcon#*after write, iclass 25, count 2 2006.280.07:51:09.88#ibcon#*before return 0, iclass 25, count 2 2006.280.07:51:09.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:09.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:09.88#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.07:51:09.88#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:09.88#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:10.00#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:10.00#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:10.00#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:51:10.00#ibcon#first serial, iclass 25, count 0 2006.280.07:51:10.00#ibcon#enter sib2, iclass 25, count 0 2006.280.07:51:10.00#ibcon#flushed, iclass 25, count 0 2006.280.07:51:10.00#ibcon#about to write, iclass 25, count 0 2006.280.07:51:10.00#ibcon#wrote, iclass 25, count 0 2006.280.07:51:10.00#ibcon#about to read 3, iclass 25, count 0 2006.280.07:51:10.02#ibcon#read 3, iclass 25, count 0 2006.280.07:51:10.02#ibcon#about to read 4, iclass 25, count 0 2006.280.07:51:10.02#ibcon#read 4, iclass 25, count 0 2006.280.07:51:10.02#ibcon#about to read 5, iclass 25, count 0 2006.280.07:51:10.02#ibcon#read 5, iclass 25, count 0 2006.280.07:51:10.02#ibcon#about to read 6, iclass 25, count 0 2006.280.07:51:10.02#ibcon#read 6, iclass 25, count 0 2006.280.07:51:10.02#ibcon#end of sib2, iclass 25, count 0 2006.280.07:51:10.02#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:51:10.02#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:51:10.02#ibcon#[25=USB\r\n] 2006.280.07:51:10.02#ibcon#*before write, iclass 25, count 0 2006.280.07:51:10.02#ibcon#enter sib2, iclass 25, count 0 2006.280.07:51:10.02#ibcon#flushed, iclass 25, count 0 2006.280.07:51:10.02#ibcon#about to write, iclass 25, count 0 2006.280.07:51:10.02#ibcon#wrote, iclass 25, count 0 2006.280.07:51:10.02#ibcon#about to read 3, iclass 25, count 0 2006.280.07:51:10.05#ibcon#read 3, iclass 25, count 0 2006.280.07:51:10.05#ibcon#about to read 4, iclass 25, count 0 2006.280.07:51:10.05#ibcon#read 4, iclass 25, count 0 2006.280.07:51:10.05#ibcon#about to read 5, iclass 25, count 0 2006.280.07:51:10.05#ibcon#read 5, iclass 25, count 0 2006.280.07:51:10.05#ibcon#about to read 6, iclass 25, count 0 2006.280.07:51:10.05#ibcon#read 6, iclass 25, count 0 2006.280.07:51:10.05#ibcon#end of sib2, iclass 25, count 0 2006.280.07:51:10.05#ibcon#*after write, iclass 25, count 0 2006.280.07:51:10.05#ibcon#*before return 0, iclass 25, count 0 2006.280.07:51:10.05#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:10.05#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:10.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:51:10.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:51:10.05$vc4f8/valo=6,772.99 2006.280.07:51:10.05#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:51:10.05#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:51:10.05#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:10.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:10.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:10.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:10.05#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:51:10.05#ibcon#first serial, iclass 27, count 0 2006.280.07:51:10.05#ibcon#enter sib2, iclass 27, count 0 2006.280.07:51:10.05#ibcon#flushed, iclass 27, count 0 2006.280.07:51:10.05#ibcon#about to write, iclass 27, count 0 2006.280.07:51:10.05#ibcon#wrote, iclass 27, count 0 2006.280.07:51:10.05#ibcon#about to read 3, iclass 27, count 0 2006.280.07:51:10.07#ibcon#read 3, iclass 27, count 0 2006.280.07:51:10.07#ibcon#about to read 4, iclass 27, count 0 2006.280.07:51:10.07#ibcon#read 4, iclass 27, count 0 2006.280.07:51:10.07#ibcon#about to read 5, iclass 27, count 0 2006.280.07:51:10.07#ibcon#read 5, iclass 27, count 0 2006.280.07:51:10.07#ibcon#about to read 6, iclass 27, count 0 2006.280.07:51:10.07#ibcon#read 6, iclass 27, count 0 2006.280.07:51:10.07#ibcon#end of sib2, iclass 27, count 0 2006.280.07:51:10.07#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:51:10.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:51:10.07#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:51:10.07#ibcon#*before write, iclass 27, count 0 2006.280.07:51:10.07#ibcon#enter sib2, iclass 27, count 0 2006.280.07:51:10.07#ibcon#flushed, iclass 27, count 0 2006.280.07:51:10.07#ibcon#about to write, iclass 27, count 0 2006.280.07:51:10.07#ibcon#wrote, iclass 27, count 0 2006.280.07:51:10.07#ibcon#about to read 3, iclass 27, count 0 2006.280.07:51:10.11#ibcon#read 3, iclass 27, count 0 2006.280.07:51:10.11#ibcon#about to read 4, iclass 27, count 0 2006.280.07:51:10.11#ibcon#read 4, iclass 27, count 0 2006.280.07:51:10.11#ibcon#about to read 5, iclass 27, count 0 2006.280.07:51:10.11#ibcon#read 5, iclass 27, count 0 2006.280.07:51:10.11#ibcon#about to read 6, iclass 27, count 0 2006.280.07:51:10.11#ibcon#read 6, iclass 27, count 0 2006.280.07:51:10.11#ibcon#end of sib2, iclass 27, count 0 2006.280.07:51:10.11#ibcon#*after write, iclass 27, count 0 2006.280.07:51:10.11#ibcon#*before return 0, iclass 27, count 0 2006.280.07:51:10.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:10.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:10.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:51:10.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:51:10.11$vc4f8/va=6,6 2006.280.07:51:10.11#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.07:51:10.11#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.07:51:10.11#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:10.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:10.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:10.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:10.17#ibcon#enter wrdev, iclass 29, count 2 2006.280.07:51:10.17#ibcon#first serial, iclass 29, count 2 2006.280.07:51:10.17#ibcon#enter sib2, iclass 29, count 2 2006.280.07:51:10.17#ibcon#flushed, iclass 29, count 2 2006.280.07:51:10.17#ibcon#about to write, iclass 29, count 2 2006.280.07:51:10.17#ibcon#wrote, iclass 29, count 2 2006.280.07:51:10.17#ibcon#about to read 3, iclass 29, count 2 2006.280.07:51:10.19#ibcon#read 3, iclass 29, count 2 2006.280.07:51:10.19#ibcon#about to read 4, iclass 29, count 2 2006.280.07:51:10.19#ibcon#read 4, iclass 29, count 2 2006.280.07:51:10.19#ibcon#about to read 5, iclass 29, count 2 2006.280.07:51:10.19#ibcon#read 5, iclass 29, count 2 2006.280.07:51:10.19#ibcon#about to read 6, iclass 29, count 2 2006.280.07:51:10.19#ibcon#read 6, iclass 29, count 2 2006.280.07:51:10.19#ibcon#end of sib2, iclass 29, count 2 2006.280.07:51:10.19#ibcon#*mode == 0, iclass 29, count 2 2006.280.07:51:10.19#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.07:51:10.19#ibcon#[25=AT06-06\r\n] 2006.280.07:51:10.19#ibcon#*before write, iclass 29, count 2 2006.280.07:51:10.19#ibcon#enter sib2, iclass 29, count 2 2006.280.07:51:10.19#ibcon#flushed, iclass 29, count 2 2006.280.07:51:10.19#ibcon#about to write, iclass 29, count 2 2006.280.07:51:10.19#ibcon#wrote, iclass 29, count 2 2006.280.07:51:10.19#ibcon#about to read 3, iclass 29, count 2 2006.280.07:51:10.23#ibcon#read 3, iclass 29, count 2 2006.280.07:51:10.23#ibcon#about to read 4, iclass 29, count 2 2006.280.07:51:10.23#ibcon#read 4, iclass 29, count 2 2006.280.07:51:10.23#ibcon#about to read 5, iclass 29, count 2 2006.280.07:51:10.23#ibcon#read 5, iclass 29, count 2 2006.280.07:51:10.23#ibcon#about to read 6, iclass 29, count 2 2006.280.07:51:10.23#ibcon#read 6, iclass 29, count 2 2006.280.07:51:10.23#ibcon#end of sib2, iclass 29, count 2 2006.280.07:51:10.23#ibcon#*after write, iclass 29, count 2 2006.280.07:51:10.23#ibcon#*before return 0, iclass 29, count 2 2006.280.07:51:10.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:10.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:10.23#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.07:51:10.23#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:10.23#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:51:10.34#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:51:10.34#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:51:10.34#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:51:10.34#ibcon#first serial, iclass 29, count 0 2006.280.07:51:10.34#ibcon#enter sib2, iclass 29, count 0 2006.280.07:51:10.34#ibcon#flushed, iclass 29, count 0 2006.280.07:51:10.34#ibcon#about to write, iclass 29, count 0 2006.280.07:51:10.34#ibcon#wrote, iclass 29, count 0 2006.280.07:51:10.34#ibcon#about to read 3, iclass 29, count 0 2006.280.07:51:10.36#ibcon#read 3, iclass 29, count 0 2006.280.07:51:10.36#ibcon#about to read 4, iclass 29, count 0 2006.280.07:51:10.36#ibcon#read 4, iclass 29, count 0 2006.280.07:51:10.36#ibcon#about to read 5, iclass 29, count 0 2006.280.07:51:10.36#ibcon#read 5, iclass 29, count 0 2006.280.07:51:10.36#ibcon#about to read 6, iclass 29, count 0 2006.280.07:51:10.36#ibcon#read 6, iclass 29, count 0 2006.280.07:51:10.36#ibcon#end of sib2, iclass 29, count 0 2006.280.07:51:10.36#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:51:10.36#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:51:10.36#ibcon#[25=USB\r\n] 2006.280.07:51:10.36#ibcon#*before write, iclass 29, count 0 2006.280.07:51:10.36#ibcon#enter sib2, iclass 29, count 0 2006.280.07:51:10.36#ibcon#flushed, iclass 29, count 0 2006.280.07:51:10.36#ibcon#about to write, iclass 29, count 0 2006.280.07:51:10.36#ibcon#wrote, iclass 29, count 0 2006.280.07:51:10.36#ibcon#about to read 3, iclass 29, count 0 2006.280.07:51:10.39#ibcon#read 3, iclass 29, count 0 2006.280.07:51:10.39#ibcon#about to read 4, iclass 29, count 0 2006.280.07:51:10.39#ibcon#read 4, iclass 29, count 0 2006.280.07:51:10.39#ibcon#about to read 5, iclass 29, count 0 2006.280.07:51:10.39#ibcon#read 5, iclass 29, count 0 2006.280.07:51:10.39#ibcon#about to read 6, iclass 29, count 0 2006.280.07:51:10.39#ibcon#read 6, iclass 29, count 0 2006.280.07:51:10.39#ibcon#end of sib2, iclass 29, count 0 2006.280.07:51:10.39#ibcon#*after write, iclass 29, count 0 2006.280.07:51:10.39#ibcon#*before return 0, iclass 29, count 0 2006.280.07:51:10.39#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:51:10.39#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.07:51:10.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:51:10.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:51:10.39$vc4f8/valo=7,832.99 2006.280.07:51:10.39#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.07:51:10.39#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.07:51:10.39#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:10.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:51:10.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:51:10.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:51:10.39#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:51:10.39#ibcon#first serial, iclass 31, count 0 2006.280.07:51:10.39#ibcon#enter sib2, iclass 31, count 0 2006.280.07:51:10.39#ibcon#flushed, iclass 31, count 0 2006.280.07:51:10.39#ibcon#about to write, iclass 31, count 0 2006.280.07:51:10.39#ibcon#wrote, iclass 31, count 0 2006.280.07:51:10.39#ibcon#about to read 3, iclass 31, count 0 2006.280.07:51:10.41#ibcon#read 3, iclass 31, count 0 2006.280.07:51:10.41#ibcon#about to read 4, iclass 31, count 0 2006.280.07:51:10.41#ibcon#read 4, iclass 31, count 0 2006.280.07:51:10.41#ibcon#about to read 5, iclass 31, count 0 2006.280.07:51:10.41#ibcon#read 5, iclass 31, count 0 2006.280.07:51:10.41#ibcon#about to read 6, iclass 31, count 0 2006.280.07:51:10.41#ibcon#read 6, iclass 31, count 0 2006.280.07:51:10.41#ibcon#end of sib2, iclass 31, count 0 2006.280.07:51:10.41#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:51:10.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:51:10.41#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:51:10.41#ibcon#*before write, iclass 31, count 0 2006.280.07:51:10.41#ibcon#enter sib2, iclass 31, count 0 2006.280.07:51:10.41#ibcon#flushed, iclass 31, count 0 2006.280.07:51:10.41#ibcon#about to write, iclass 31, count 0 2006.280.07:51:10.41#ibcon#wrote, iclass 31, count 0 2006.280.07:51:10.41#ibcon#about to read 3, iclass 31, count 0 2006.280.07:51:10.45#ibcon#read 3, iclass 31, count 0 2006.280.07:51:10.45#ibcon#about to read 4, iclass 31, count 0 2006.280.07:51:10.45#ibcon#read 4, iclass 31, count 0 2006.280.07:51:10.45#ibcon#about to read 5, iclass 31, count 0 2006.280.07:51:10.45#ibcon#read 5, iclass 31, count 0 2006.280.07:51:10.45#ibcon#about to read 6, iclass 31, count 0 2006.280.07:51:10.45#ibcon#read 6, iclass 31, count 0 2006.280.07:51:10.45#ibcon#end of sib2, iclass 31, count 0 2006.280.07:51:10.45#ibcon#*after write, iclass 31, count 0 2006.280.07:51:10.45#ibcon#*before return 0, iclass 31, count 0 2006.280.07:51:10.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:51:10.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.07:51:10.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:51:10.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:51:10.45$vc4f8/va=7,6 2006.280.07:51:10.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.07:51:10.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.07:51:10.47#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:10.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:51:10.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:51:10.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:51:10.50#ibcon#enter wrdev, iclass 33, count 2 2006.280.07:51:10.50#ibcon#first serial, iclass 33, count 2 2006.280.07:51:10.50#ibcon#enter sib2, iclass 33, count 2 2006.280.07:51:10.50#ibcon#flushed, iclass 33, count 2 2006.280.07:51:10.50#ibcon#about to write, iclass 33, count 2 2006.280.07:51:10.50#ibcon#wrote, iclass 33, count 2 2006.280.07:51:10.50#ibcon#about to read 3, iclass 33, count 2 2006.280.07:51:10.52#ibcon#read 3, iclass 33, count 2 2006.280.07:51:10.52#ibcon#about to read 4, iclass 33, count 2 2006.280.07:51:10.52#ibcon#read 4, iclass 33, count 2 2006.280.07:51:10.52#ibcon#about to read 5, iclass 33, count 2 2006.280.07:51:10.52#ibcon#read 5, iclass 33, count 2 2006.280.07:51:10.52#ibcon#about to read 6, iclass 33, count 2 2006.280.07:51:10.52#ibcon#read 6, iclass 33, count 2 2006.280.07:51:10.52#ibcon#end of sib2, iclass 33, count 2 2006.280.07:51:10.52#ibcon#*mode == 0, iclass 33, count 2 2006.280.07:51:10.52#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.07:51:10.52#ibcon#[25=AT07-06\r\n] 2006.280.07:51:10.52#ibcon#*before write, iclass 33, count 2 2006.280.07:51:10.52#ibcon#enter sib2, iclass 33, count 2 2006.280.07:51:10.52#ibcon#flushed, iclass 33, count 2 2006.280.07:51:10.52#ibcon#about to write, iclass 33, count 2 2006.280.07:51:10.52#ibcon#wrote, iclass 33, count 2 2006.280.07:51:10.52#ibcon#about to read 3, iclass 33, count 2 2006.280.07:51:10.55#ibcon#read 3, iclass 33, count 2 2006.280.07:51:10.55#ibcon#about to read 4, iclass 33, count 2 2006.280.07:51:10.55#ibcon#read 4, iclass 33, count 2 2006.280.07:51:10.55#ibcon#about to read 5, iclass 33, count 2 2006.280.07:51:10.55#ibcon#read 5, iclass 33, count 2 2006.280.07:51:10.55#ibcon#about to read 6, iclass 33, count 2 2006.280.07:51:10.55#ibcon#read 6, iclass 33, count 2 2006.280.07:51:10.55#ibcon#end of sib2, iclass 33, count 2 2006.280.07:51:10.55#ibcon#*after write, iclass 33, count 2 2006.280.07:51:10.55#ibcon#*before return 0, iclass 33, count 2 2006.280.07:51:10.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:51:10.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.07:51:10.55#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.07:51:10.55#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:10.55#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:51:10.67#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:51:10.67#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:51:10.67#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:51:10.67#ibcon#first serial, iclass 33, count 0 2006.280.07:51:10.67#ibcon#enter sib2, iclass 33, count 0 2006.280.07:51:10.67#ibcon#flushed, iclass 33, count 0 2006.280.07:51:10.67#ibcon#about to write, iclass 33, count 0 2006.280.07:51:10.67#ibcon#wrote, iclass 33, count 0 2006.280.07:51:10.67#ibcon#about to read 3, iclass 33, count 0 2006.280.07:51:10.69#ibcon#read 3, iclass 33, count 0 2006.280.07:51:10.69#ibcon#about to read 4, iclass 33, count 0 2006.280.07:51:10.69#ibcon#read 4, iclass 33, count 0 2006.280.07:51:10.69#ibcon#about to read 5, iclass 33, count 0 2006.280.07:51:10.69#ibcon#read 5, iclass 33, count 0 2006.280.07:51:10.69#ibcon#about to read 6, iclass 33, count 0 2006.280.07:51:10.69#ibcon#read 6, iclass 33, count 0 2006.280.07:51:10.69#ibcon#end of sib2, iclass 33, count 0 2006.280.07:51:10.69#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:51:10.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:51:10.69#ibcon#[25=USB\r\n] 2006.280.07:51:10.69#ibcon#*before write, iclass 33, count 0 2006.280.07:51:10.69#ibcon#enter sib2, iclass 33, count 0 2006.280.07:51:10.69#ibcon#flushed, iclass 33, count 0 2006.280.07:51:10.69#ibcon#about to write, iclass 33, count 0 2006.280.07:51:10.69#ibcon#wrote, iclass 33, count 0 2006.280.07:51:10.69#ibcon#about to read 3, iclass 33, count 0 2006.280.07:51:10.72#ibcon#read 3, iclass 33, count 0 2006.280.07:51:10.72#ibcon#about to read 4, iclass 33, count 0 2006.280.07:51:10.72#ibcon#read 4, iclass 33, count 0 2006.280.07:51:10.72#ibcon#about to read 5, iclass 33, count 0 2006.280.07:51:10.72#ibcon#read 5, iclass 33, count 0 2006.280.07:51:10.72#ibcon#about to read 6, iclass 33, count 0 2006.280.07:51:10.72#ibcon#read 6, iclass 33, count 0 2006.280.07:51:10.72#ibcon#end of sib2, iclass 33, count 0 2006.280.07:51:10.72#ibcon#*after write, iclass 33, count 0 2006.280.07:51:10.72#ibcon#*before return 0, iclass 33, count 0 2006.280.07:51:10.72#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:51:10.72#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.07:51:10.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:51:10.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:51:10.72$vc4f8/valo=8,852.99 2006.280.07:51:10.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.07:51:10.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.07:51:10.72#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:10.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:51:10.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:51:10.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:51:10.72#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:51:10.72#ibcon#first serial, iclass 35, count 0 2006.280.07:51:10.72#ibcon#enter sib2, iclass 35, count 0 2006.280.07:51:10.72#ibcon#flushed, iclass 35, count 0 2006.280.07:51:10.72#ibcon#about to write, iclass 35, count 0 2006.280.07:51:10.72#ibcon#wrote, iclass 35, count 0 2006.280.07:51:10.72#ibcon#about to read 3, iclass 35, count 0 2006.280.07:51:10.74#ibcon#read 3, iclass 35, count 0 2006.280.07:51:10.74#ibcon#about to read 4, iclass 35, count 0 2006.280.07:51:10.74#ibcon#read 4, iclass 35, count 0 2006.280.07:51:10.74#ibcon#about to read 5, iclass 35, count 0 2006.280.07:51:10.74#ibcon#read 5, iclass 35, count 0 2006.280.07:51:10.74#ibcon#about to read 6, iclass 35, count 0 2006.280.07:51:10.74#ibcon#read 6, iclass 35, count 0 2006.280.07:51:10.74#ibcon#end of sib2, iclass 35, count 0 2006.280.07:51:10.74#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:51:10.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:51:10.74#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:51:10.74#ibcon#*before write, iclass 35, count 0 2006.280.07:51:10.74#ibcon#enter sib2, iclass 35, count 0 2006.280.07:51:10.74#ibcon#flushed, iclass 35, count 0 2006.280.07:51:10.74#ibcon#about to write, iclass 35, count 0 2006.280.07:51:10.74#ibcon#wrote, iclass 35, count 0 2006.280.07:51:10.74#ibcon#about to read 3, iclass 35, count 0 2006.280.07:51:10.78#ibcon#read 3, iclass 35, count 0 2006.280.07:51:10.78#ibcon#about to read 4, iclass 35, count 0 2006.280.07:51:10.78#ibcon#read 4, iclass 35, count 0 2006.280.07:51:10.78#ibcon#about to read 5, iclass 35, count 0 2006.280.07:51:10.78#ibcon#read 5, iclass 35, count 0 2006.280.07:51:10.78#ibcon#about to read 6, iclass 35, count 0 2006.280.07:51:10.78#ibcon#read 6, iclass 35, count 0 2006.280.07:51:10.78#ibcon#end of sib2, iclass 35, count 0 2006.280.07:51:10.78#ibcon#*after write, iclass 35, count 0 2006.280.07:51:10.78#ibcon#*before return 0, iclass 35, count 0 2006.280.07:51:10.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:51:10.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.07:51:10.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:51:10.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:51:10.78$vc4f8/va=8,6 2006.280.07:51:10.78#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.07:51:10.78#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.07:51:10.78#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:10.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:51:10.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:51:10.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:51:10.84#ibcon#enter wrdev, iclass 37, count 2 2006.280.07:51:10.84#ibcon#first serial, iclass 37, count 2 2006.280.07:51:10.84#ibcon#enter sib2, iclass 37, count 2 2006.280.07:51:10.84#ibcon#flushed, iclass 37, count 2 2006.280.07:51:10.84#ibcon#about to write, iclass 37, count 2 2006.280.07:51:10.84#ibcon#wrote, iclass 37, count 2 2006.280.07:51:10.84#ibcon#about to read 3, iclass 37, count 2 2006.280.07:51:10.86#ibcon#read 3, iclass 37, count 2 2006.280.07:51:10.86#ibcon#about to read 4, iclass 37, count 2 2006.280.07:51:10.86#ibcon#read 4, iclass 37, count 2 2006.280.07:51:10.86#ibcon#about to read 5, iclass 37, count 2 2006.280.07:51:10.86#ibcon#read 5, iclass 37, count 2 2006.280.07:51:10.86#ibcon#about to read 6, iclass 37, count 2 2006.280.07:51:10.86#ibcon#read 6, iclass 37, count 2 2006.280.07:51:10.86#ibcon#end of sib2, iclass 37, count 2 2006.280.07:51:10.86#ibcon#*mode == 0, iclass 37, count 2 2006.280.07:51:10.86#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.07:51:10.86#ibcon#[25=AT08-06\r\n] 2006.280.07:51:10.86#ibcon#*before write, iclass 37, count 2 2006.280.07:51:10.86#ibcon#enter sib2, iclass 37, count 2 2006.280.07:51:10.86#ibcon#flushed, iclass 37, count 2 2006.280.07:51:10.86#ibcon#about to write, iclass 37, count 2 2006.280.07:51:10.86#ibcon#wrote, iclass 37, count 2 2006.280.07:51:10.86#ibcon#about to read 3, iclass 37, count 2 2006.280.07:51:10.89#ibcon#read 3, iclass 37, count 2 2006.280.07:51:10.89#ibcon#about to read 4, iclass 37, count 2 2006.280.07:51:10.89#ibcon#read 4, iclass 37, count 2 2006.280.07:51:10.89#ibcon#about to read 5, iclass 37, count 2 2006.280.07:51:10.89#ibcon#read 5, iclass 37, count 2 2006.280.07:51:10.89#ibcon#about to read 6, iclass 37, count 2 2006.280.07:51:10.89#ibcon#read 6, iclass 37, count 2 2006.280.07:51:10.89#ibcon#end of sib2, iclass 37, count 2 2006.280.07:51:10.89#ibcon#*after write, iclass 37, count 2 2006.280.07:51:10.89#ibcon#*before return 0, iclass 37, count 2 2006.280.07:51:10.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:51:10.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.07:51:10.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.07:51:10.89#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:10.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:51:11.01#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:51:11.01#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:51:11.01#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:51:11.01#ibcon#first serial, iclass 37, count 0 2006.280.07:51:11.01#ibcon#enter sib2, iclass 37, count 0 2006.280.07:51:11.01#ibcon#flushed, iclass 37, count 0 2006.280.07:51:11.01#ibcon#about to write, iclass 37, count 0 2006.280.07:51:11.01#ibcon#wrote, iclass 37, count 0 2006.280.07:51:11.01#ibcon#about to read 3, iclass 37, count 0 2006.280.07:51:11.03#ibcon#read 3, iclass 37, count 0 2006.280.07:51:11.03#ibcon#about to read 4, iclass 37, count 0 2006.280.07:51:11.03#ibcon#read 4, iclass 37, count 0 2006.280.07:51:11.03#ibcon#about to read 5, iclass 37, count 0 2006.280.07:51:11.03#ibcon#read 5, iclass 37, count 0 2006.280.07:51:11.03#ibcon#about to read 6, iclass 37, count 0 2006.280.07:51:11.03#ibcon#read 6, iclass 37, count 0 2006.280.07:51:11.03#ibcon#end of sib2, iclass 37, count 0 2006.280.07:51:11.03#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:51:11.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:51:11.03#ibcon#[25=USB\r\n] 2006.280.07:51:11.03#ibcon#*before write, iclass 37, count 0 2006.280.07:51:11.03#ibcon#enter sib2, iclass 37, count 0 2006.280.07:51:11.03#ibcon#flushed, iclass 37, count 0 2006.280.07:51:11.03#ibcon#about to write, iclass 37, count 0 2006.280.07:51:11.03#ibcon#wrote, iclass 37, count 0 2006.280.07:51:11.03#ibcon#about to read 3, iclass 37, count 0 2006.280.07:51:11.06#ibcon#read 3, iclass 37, count 0 2006.280.07:51:11.06#ibcon#about to read 4, iclass 37, count 0 2006.280.07:51:11.06#ibcon#read 4, iclass 37, count 0 2006.280.07:51:11.06#ibcon#about to read 5, iclass 37, count 0 2006.280.07:51:11.06#ibcon#read 5, iclass 37, count 0 2006.280.07:51:11.06#ibcon#about to read 6, iclass 37, count 0 2006.280.07:51:11.06#ibcon#read 6, iclass 37, count 0 2006.280.07:51:11.06#ibcon#end of sib2, iclass 37, count 0 2006.280.07:51:11.06#ibcon#*after write, iclass 37, count 0 2006.280.07:51:11.06#ibcon#*before return 0, iclass 37, count 0 2006.280.07:51:11.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:51:11.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.07:51:11.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:51:11.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:51:11.06$vc4f8/vblo=1,632.99 2006.280.07:51:11.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.07:51:11.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.07:51:11.06#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:11.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:51:11.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:51:11.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:51:11.06#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:51:11.06#ibcon#first serial, iclass 39, count 0 2006.280.07:51:11.06#ibcon#enter sib2, iclass 39, count 0 2006.280.07:51:11.06#ibcon#flushed, iclass 39, count 0 2006.280.07:51:11.06#ibcon#about to write, iclass 39, count 0 2006.280.07:51:11.06#ibcon#wrote, iclass 39, count 0 2006.280.07:51:11.06#ibcon#about to read 3, iclass 39, count 0 2006.280.07:51:11.08#ibcon#read 3, iclass 39, count 0 2006.280.07:51:11.08#ibcon#about to read 4, iclass 39, count 0 2006.280.07:51:11.08#ibcon#read 4, iclass 39, count 0 2006.280.07:51:11.08#ibcon#about to read 5, iclass 39, count 0 2006.280.07:51:11.08#ibcon#read 5, iclass 39, count 0 2006.280.07:51:11.08#ibcon#about to read 6, iclass 39, count 0 2006.280.07:51:11.08#ibcon#read 6, iclass 39, count 0 2006.280.07:51:11.08#ibcon#end of sib2, iclass 39, count 0 2006.280.07:51:11.08#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:51:11.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:51:11.08#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:51:11.08#ibcon#*before write, iclass 39, count 0 2006.280.07:51:11.08#ibcon#enter sib2, iclass 39, count 0 2006.280.07:51:11.08#ibcon#flushed, iclass 39, count 0 2006.280.07:51:11.08#ibcon#about to write, iclass 39, count 0 2006.280.07:51:11.08#ibcon#wrote, iclass 39, count 0 2006.280.07:51:11.08#ibcon#about to read 3, iclass 39, count 0 2006.280.07:51:11.12#ibcon#read 3, iclass 39, count 0 2006.280.07:51:11.12#ibcon#about to read 4, iclass 39, count 0 2006.280.07:51:11.12#ibcon#read 4, iclass 39, count 0 2006.280.07:51:11.12#ibcon#about to read 5, iclass 39, count 0 2006.280.07:51:11.12#ibcon#read 5, iclass 39, count 0 2006.280.07:51:11.12#ibcon#about to read 6, iclass 39, count 0 2006.280.07:51:11.12#ibcon#read 6, iclass 39, count 0 2006.280.07:51:11.12#ibcon#end of sib2, iclass 39, count 0 2006.280.07:51:11.12#ibcon#*after write, iclass 39, count 0 2006.280.07:51:11.12#ibcon#*before return 0, iclass 39, count 0 2006.280.07:51:11.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:51:11.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.07:51:11.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:51:11.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:51:11.12$vc4f8/vb=1,4 2006.280.07:51:11.12#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.07:51:11.12#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.07:51:11.12#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:11.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:51:11.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:51:11.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:51:11.12#ibcon#enter wrdev, iclass 3, count 2 2006.280.07:51:11.12#ibcon#first serial, iclass 3, count 2 2006.280.07:51:11.12#ibcon#enter sib2, iclass 3, count 2 2006.280.07:51:11.12#ibcon#flushed, iclass 3, count 2 2006.280.07:51:11.12#ibcon#about to write, iclass 3, count 2 2006.280.07:51:11.12#ibcon#wrote, iclass 3, count 2 2006.280.07:51:11.12#ibcon#about to read 3, iclass 3, count 2 2006.280.07:51:11.14#ibcon#read 3, iclass 3, count 2 2006.280.07:51:11.15#ibcon#about to read 4, iclass 3, count 2 2006.280.07:51:11.15#ibcon#read 4, iclass 3, count 2 2006.280.07:51:11.15#ibcon#about to read 5, iclass 3, count 2 2006.280.07:51:11.15#ibcon#read 5, iclass 3, count 2 2006.280.07:51:11.15#ibcon#about to read 6, iclass 3, count 2 2006.280.07:51:11.15#ibcon#read 6, iclass 3, count 2 2006.280.07:51:11.15#ibcon#end of sib2, iclass 3, count 2 2006.280.07:51:11.15#ibcon#*mode == 0, iclass 3, count 2 2006.280.07:51:11.15#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.07:51:11.15#ibcon#[27=AT01-04\r\n] 2006.280.07:51:11.15#ibcon#*before write, iclass 3, count 2 2006.280.07:51:11.15#ibcon#enter sib2, iclass 3, count 2 2006.280.07:51:11.15#ibcon#flushed, iclass 3, count 2 2006.280.07:51:11.15#ibcon#about to write, iclass 3, count 2 2006.280.07:51:11.15#ibcon#wrote, iclass 3, count 2 2006.280.07:51:11.15#ibcon#about to read 3, iclass 3, count 2 2006.280.07:51:11.17#ibcon#read 3, iclass 3, count 2 2006.280.07:51:11.17#ibcon#about to read 4, iclass 3, count 2 2006.280.07:51:11.17#ibcon#read 4, iclass 3, count 2 2006.280.07:51:11.17#ibcon#about to read 5, iclass 3, count 2 2006.280.07:51:11.17#ibcon#read 5, iclass 3, count 2 2006.280.07:51:11.17#ibcon#about to read 6, iclass 3, count 2 2006.280.07:51:11.17#ibcon#read 6, iclass 3, count 2 2006.280.07:51:11.17#ibcon#end of sib2, iclass 3, count 2 2006.280.07:51:11.17#ibcon#*after write, iclass 3, count 2 2006.280.07:51:11.17#ibcon#*before return 0, iclass 3, count 2 2006.280.07:51:11.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:51:11.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.07:51:11.17#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.07:51:11.17#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:11.17#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:51:11.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:51:11.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:51:11.29#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:51:11.29#ibcon#first serial, iclass 3, count 0 2006.280.07:51:11.29#ibcon#enter sib2, iclass 3, count 0 2006.280.07:51:11.29#ibcon#flushed, iclass 3, count 0 2006.280.07:51:11.29#ibcon#about to write, iclass 3, count 0 2006.280.07:51:11.29#ibcon#wrote, iclass 3, count 0 2006.280.07:51:11.29#ibcon#about to read 3, iclass 3, count 0 2006.280.07:51:11.31#ibcon#read 3, iclass 3, count 0 2006.280.07:51:11.31#ibcon#about to read 4, iclass 3, count 0 2006.280.07:51:11.31#ibcon#read 4, iclass 3, count 0 2006.280.07:51:11.31#ibcon#about to read 5, iclass 3, count 0 2006.280.07:51:11.31#ibcon#read 5, iclass 3, count 0 2006.280.07:51:11.31#ibcon#about to read 6, iclass 3, count 0 2006.280.07:51:11.31#ibcon#read 6, iclass 3, count 0 2006.280.07:51:11.31#ibcon#end of sib2, iclass 3, count 0 2006.280.07:51:11.31#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:51:11.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:51:11.31#ibcon#[27=USB\r\n] 2006.280.07:51:11.31#ibcon#*before write, iclass 3, count 0 2006.280.07:51:11.31#ibcon#enter sib2, iclass 3, count 0 2006.280.07:51:11.31#ibcon#flushed, iclass 3, count 0 2006.280.07:51:11.31#ibcon#about to write, iclass 3, count 0 2006.280.07:51:11.31#ibcon#wrote, iclass 3, count 0 2006.280.07:51:11.31#ibcon#about to read 3, iclass 3, count 0 2006.280.07:51:11.34#ibcon#read 3, iclass 3, count 0 2006.280.07:51:11.34#ibcon#about to read 4, iclass 3, count 0 2006.280.07:51:11.34#ibcon#read 4, iclass 3, count 0 2006.280.07:51:11.34#ibcon#about to read 5, iclass 3, count 0 2006.280.07:51:11.34#ibcon#read 5, iclass 3, count 0 2006.280.07:51:11.34#ibcon#about to read 6, iclass 3, count 0 2006.280.07:51:11.34#ibcon#read 6, iclass 3, count 0 2006.280.07:51:11.34#ibcon#end of sib2, iclass 3, count 0 2006.280.07:51:11.34#ibcon#*after write, iclass 3, count 0 2006.280.07:51:11.34#ibcon#*before return 0, iclass 3, count 0 2006.280.07:51:11.34#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:51:11.34#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.07:51:11.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:51:11.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:51:11.34$vc4f8/vblo=2,640.99 2006.280.07:51:11.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.07:51:11.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.07:51:11.34#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:11.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:11.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:11.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:11.34#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:51:11.34#ibcon#first serial, iclass 5, count 0 2006.280.07:51:11.34#ibcon#enter sib2, iclass 5, count 0 2006.280.07:51:11.34#ibcon#flushed, iclass 5, count 0 2006.280.07:51:11.34#ibcon#about to write, iclass 5, count 0 2006.280.07:51:11.34#ibcon#wrote, iclass 5, count 0 2006.280.07:51:11.34#ibcon#about to read 3, iclass 5, count 0 2006.280.07:51:11.36#ibcon#read 3, iclass 5, count 0 2006.280.07:51:11.36#ibcon#about to read 4, iclass 5, count 0 2006.280.07:51:11.36#ibcon#read 4, iclass 5, count 0 2006.280.07:51:11.36#ibcon#about to read 5, iclass 5, count 0 2006.280.07:51:11.36#ibcon#read 5, iclass 5, count 0 2006.280.07:51:11.36#ibcon#about to read 6, iclass 5, count 0 2006.280.07:51:11.36#ibcon#read 6, iclass 5, count 0 2006.280.07:51:11.36#ibcon#end of sib2, iclass 5, count 0 2006.280.07:51:11.36#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:51:11.36#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:51:11.36#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:51:11.36#ibcon#*before write, iclass 5, count 0 2006.280.07:51:11.36#ibcon#enter sib2, iclass 5, count 0 2006.280.07:51:11.36#ibcon#flushed, iclass 5, count 0 2006.280.07:51:11.36#ibcon#about to write, iclass 5, count 0 2006.280.07:51:11.36#ibcon#wrote, iclass 5, count 0 2006.280.07:51:11.36#ibcon#about to read 3, iclass 5, count 0 2006.280.07:51:11.40#ibcon#read 3, iclass 5, count 0 2006.280.07:51:11.40#ibcon#about to read 4, iclass 5, count 0 2006.280.07:51:11.40#ibcon#read 4, iclass 5, count 0 2006.280.07:51:11.40#ibcon#about to read 5, iclass 5, count 0 2006.280.07:51:11.40#ibcon#read 5, iclass 5, count 0 2006.280.07:51:11.40#ibcon#about to read 6, iclass 5, count 0 2006.280.07:51:11.40#ibcon#read 6, iclass 5, count 0 2006.280.07:51:11.40#ibcon#end of sib2, iclass 5, count 0 2006.280.07:51:11.40#ibcon#*after write, iclass 5, count 0 2006.280.07:51:11.40#ibcon#*before return 0, iclass 5, count 0 2006.280.07:51:11.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:11.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.07:51:11.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:51:11.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:51:11.40$vc4f8/vb=2,5 2006.280.07:51:11.41#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.07:51:11.41#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.07:51:11.41#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:11.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:11.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:11.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:11.45#ibcon#enter wrdev, iclass 7, count 2 2006.280.07:51:11.45#ibcon#first serial, iclass 7, count 2 2006.280.07:51:11.45#ibcon#enter sib2, iclass 7, count 2 2006.280.07:51:11.45#ibcon#flushed, iclass 7, count 2 2006.280.07:51:11.45#ibcon#about to write, iclass 7, count 2 2006.280.07:51:11.45#ibcon#wrote, iclass 7, count 2 2006.280.07:51:11.45#ibcon#about to read 3, iclass 7, count 2 2006.280.07:51:11.47#ibcon#read 3, iclass 7, count 2 2006.280.07:51:11.47#ibcon#about to read 4, iclass 7, count 2 2006.280.07:51:11.47#ibcon#read 4, iclass 7, count 2 2006.280.07:51:11.47#ibcon#about to read 5, iclass 7, count 2 2006.280.07:51:11.47#ibcon#read 5, iclass 7, count 2 2006.280.07:51:11.47#ibcon#about to read 6, iclass 7, count 2 2006.280.07:51:11.47#ibcon#read 6, iclass 7, count 2 2006.280.07:51:11.47#ibcon#end of sib2, iclass 7, count 2 2006.280.07:51:11.47#ibcon#*mode == 0, iclass 7, count 2 2006.280.07:51:11.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.07:51:11.47#ibcon#[27=AT02-05\r\n] 2006.280.07:51:11.47#ibcon#*before write, iclass 7, count 2 2006.280.07:51:11.47#ibcon#enter sib2, iclass 7, count 2 2006.280.07:51:11.47#ibcon#flushed, iclass 7, count 2 2006.280.07:51:11.47#ibcon#about to write, iclass 7, count 2 2006.280.07:51:11.47#ibcon#wrote, iclass 7, count 2 2006.280.07:51:11.47#ibcon#about to read 3, iclass 7, count 2 2006.280.07:51:11.50#ibcon#read 3, iclass 7, count 2 2006.280.07:51:11.50#ibcon#about to read 4, iclass 7, count 2 2006.280.07:51:11.50#ibcon#read 4, iclass 7, count 2 2006.280.07:51:11.50#ibcon#about to read 5, iclass 7, count 2 2006.280.07:51:11.50#ibcon#read 5, iclass 7, count 2 2006.280.07:51:11.50#ibcon#about to read 6, iclass 7, count 2 2006.280.07:51:11.50#ibcon#read 6, iclass 7, count 2 2006.280.07:51:11.50#ibcon#end of sib2, iclass 7, count 2 2006.280.07:51:11.50#ibcon#*after write, iclass 7, count 2 2006.280.07:51:11.50#ibcon#*before return 0, iclass 7, count 2 2006.280.07:51:11.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:11.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.07:51:11.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.07:51:11.50#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:11.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:11.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:11.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:11.62#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:51:11.62#ibcon#first serial, iclass 7, count 0 2006.280.07:51:11.62#ibcon#enter sib2, iclass 7, count 0 2006.280.07:51:11.62#ibcon#flushed, iclass 7, count 0 2006.280.07:51:11.62#ibcon#about to write, iclass 7, count 0 2006.280.07:51:11.62#ibcon#wrote, iclass 7, count 0 2006.280.07:51:11.62#ibcon#about to read 3, iclass 7, count 0 2006.280.07:51:11.64#ibcon#read 3, iclass 7, count 0 2006.280.07:51:11.64#ibcon#about to read 4, iclass 7, count 0 2006.280.07:51:11.64#ibcon#read 4, iclass 7, count 0 2006.280.07:51:11.64#ibcon#about to read 5, iclass 7, count 0 2006.280.07:51:11.64#ibcon#read 5, iclass 7, count 0 2006.280.07:51:11.64#ibcon#about to read 6, iclass 7, count 0 2006.280.07:51:11.64#ibcon#read 6, iclass 7, count 0 2006.280.07:51:11.64#ibcon#end of sib2, iclass 7, count 0 2006.280.07:51:11.64#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:51:11.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:51:11.64#ibcon#[27=USB\r\n] 2006.280.07:51:11.64#ibcon#*before write, iclass 7, count 0 2006.280.07:51:11.64#ibcon#enter sib2, iclass 7, count 0 2006.280.07:51:11.64#ibcon#flushed, iclass 7, count 0 2006.280.07:51:11.64#ibcon#about to write, iclass 7, count 0 2006.280.07:51:11.64#ibcon#wrote, iclass 7, count 0 2006.280.07:51:11.64#ibcon#about to read 3, iclass 7, count 0 2006.280.07:51:11.68#ibcon#read 3, iclass 7, count 0 2006.280.07:51:11.68#ibcon#about to read 4, iclass 7, count 0 2006.280.07:51:11.68#ibcon#read 4, iclass 7, count 0 2006.280.07:51:11.68#ibcon#about to read 5, iclass 7, count 0 2006.280.07:51:11.68#ibcon#read 5, iclass 7, count 0 2006.280.07:51:11.68#ibcon#about to read 6, iclass 7, count 0 2006.280.07:51:11.68#ibcon#read 6, iclass 7, count 0 2006.280.07:51:11.68#ibcon#end of sib2, iclass 7, count 0 2006.280.07:51:11.68#ibcon#*after write, iclass 7, count 0 2006.280.07:51:11.68#ibcon#*before return 0, iclass 7, count 0 2006.280.07:51:11.68#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:11.68#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.07:51:11.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:51:11.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:51:11.68$vc4f8/vblo=3,656.99 2006.280.07:51:11.68#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.07:51:11.68#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.07:51:11.68#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:11.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:11.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:11.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:11.68#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:51:11.68#ibcon#first serial, iclass 11, count 0 2006.280.07:51:11.68#ibcon#enter sib2, iclass 11, count 0 2006.280.07:51:11.68#ibcon#flushed, iclass 11, count 0 2006.280.07:51:11.68#ibcon#about to write, iclass 11, count 0 2006.280.07:51:11.68#ibcon#wrote, iclass 11, count 0 2006.280.07:51:11.68#ibcon#about to read 3, iclass 11, count 0 2006.280.07:51:11.70#ibcon#read 3, iclass 11, count 0 2006.280.07:51:11.70#ibcon#about to read 4, iclass 11, count 0 2006.280.07:51:11.70#ibcon#read 4, iclass 11, count 0 2006.280.07:51:11.70#ibcon#about to read 5, iclass 11, count 0 2006.280.07:51:11.70#ibcon#read 5, iclass 11, count 0 2006.280.07:51:11.70#ibcon#about to read 6, iclass 11, count 0 2006.280.07:51:11.70#ibcon#read 6, iclass 11, count 0 2006.280.07:51:11.70#ibcon#end of sib2, iclass 11, count 0 2006.280.07:51:11.70#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:51:11.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:51:11.70#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:51:11.70#ibcon#*before write, iclass 11, count 0 2006.280.07:51:11.72#ibcon#enter sib2, iclass 11, count 0 2006.280.07:51:11.72#ibcon#flushed, iclass 11, count 0 2006.280.07:51:11.72#ibcon#about to write, iclass 11, count 0 2006.280.07:51:11.72#ibcon#wrote, iclass 11, count 0 2006.280.07:51:11.72#ibcon#about to read 3, iclass 11, count 0 2006.280.07:51:11.76#ibcon#read 3, iclass 11, count 0 2006.280.07:51:11.76#ibcon#about to read 4, iclass 11, count 0 2006.280.07:51:11.76#ibcon#read 4, iclass 11, count 0 2006.280.07:51:11.76#ibcon#about to read 5, iclass 11, count 0 2006.280.07:51:11.76#ibcon#read 5, iclass 11, count 0 2006.280.07:51:11.76#ibcon#about to read 6, iclass 11, count 0 2006.280.07:51:11.76#ibcon#read 6, iclass 11, count 0 2006.280.07:51:11.76#ibcon#end of sib2, iclass 11, count 0 2006.280.07:51:11.76#ibcon#*after write, iclass 11, count 0 2006.280.07:51:11.76#ibcon#*before return 0, iclass 11, count 0 2006.280.07:51:11.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:11.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.07:51:11.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:51:11.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:51:11.76$vc4f8/vb=3,4 2006.280.07:51:11.76#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.07:51:11.76#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.07:51:11.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:11.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:11.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:11.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:11.80#ibcon#enter wrdev, iclass 13, count 2 2006.280.07:51:11.80#ibcon#first serial, iclass 13, count 2 2006.280.07:51:11.80#ibcon#enter sib2, iclass 13, count 2 2006.280.07:51:11.80#ibcon#flushed, iclass 13, count 2 2006.280.07:51:11.80#ibcon#about to write, iclass 13, count 2 2006.280.07:51:11.80#ibcon#wrote, iclass 13, count 2 2006.280.07:51:11.80#ibcon#about to read 3, iclass 13, count 2 2006.280.07:51:11.82#ibcon#read 3, iclass 13, count 2 2006.280.07:51:11.82#ibcon#about to read 4, iclass 13, count 2 2006.280.07:51:11.82#ibcon#read 4, iclass 13, count 2 2006.280.07:51:11.82#ibcon#about to read 5, iclass 13, count 2 2006.280.07:51:11.82#ibcon#read 5, iclass 13, count 2 2006.280.07:51:11.82#ibcon#about to read 6, iclass 13, count 2 2006.280.07:51:11.82#ibcon#read 6, iclass 13, count 2 2006.280.07:51:11.82#ibcon#end of sib2, iclass 13, count 2 2006.280.07:51:11.82#ibcon#*mode == 0, iclass 13, count 2 2006.280.07:51:11.82#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.07:51:11.82#ibcon#[27=AT03-04\r\n] 2006.280.07:51:11.82#ibcon#*before write, iclass 13, count 2 2006.280.07:51:11.82#ibcon#enter sib2, iclass 13, count 2 2006.280.07:51:11.82#ibcon#flushed, iclass 13, count 2 2006.280.07:51:11.82#ibcon#about to write, iclass 13, count 2 2006.280.07:51:11.82#ibcon#wrote, iclass 13, count 2 2006.280.07:51:11.82#ibcon#about to read 3, iclass 13, count 2 2006.280.07:51:11.85#ibcon#read 3, iclass 13, count 2 2006.280.07:51:11.85#ibcon#about to read 4, iclass 13, count 2 2006.280.07:51:11.85#ibcon#read 4, iclass 13, count 2 2006.280.07:51:11.85#ibcon#about to read 5, iclass 13, count 2 2006.280.07:51:11.85#ibcon#read 5, iclass 13, count 2 2006.280.07:51:11.85#ibcon#about to read 6, iclass 13, count 2 2006.280.07:51:11.85#ibcon#read 6, iclass 13, count 2 2006.280.07:51:11.85#ibcon#end of sib2, iclass 13, count 2 2006.280.07:51:11.85#ibcon#*after write, iclass 13, count 2 2006.280.07:51:11.85#ibcon#*before return 0, iclass 13, count 2 2006.280.07:51:11.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:11.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.07:51:11.85#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.07:51:11.85#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:11.85#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:11.97#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:11.97#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:11.97#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:51:11.97#ibcon#first serial, iclass 13, count 0 2006.280.07:51:11.97#ibcon#enter sib2, iclass 13, count 0 2006.280.07:51:11.97#ibcon#flushed, iclass 13, count 0 2006.280.07:51:11.97#ibcon#about to write, iclass 13, count 0 2006.280.07:51:11.97#ibcon#wrote, iclass 13, count 0 2006.280.07:51:11.97#ibcon#about to read 3, iclass 13, count 0 2006.280.07:51:11.99#ibcon#read 3, iclass 13, count 0 2006.280.07:51:11.99#ibcon#about to read 4, iclass 13, count 0 2006.280.07:51:11.99#ibcon#read 4, iclass 13, count 0 2006.280.07:51:11.99#ibcon#about to read 5, iclass 13, count 0 2006.280.07:51:11.99#ibcon#read 5, iclass 13, count 0 2006.280.07:51:11.99#ibcon#about to read 6, iclass 13, count 0 2006.280.07:51:11.99#ibcon#read 6, iclass 13, count 0 2006.280.07:51:11.99#ibcon#end of sib2, iclass 13, count 0 2006.280.07:51:11.99#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:51:11.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:51:11.99#ibcon#[27=USB\r\n] 2006.280.07:51:11.99#ibcon#*before write, iclass 13, count 0 2006.280.07:51:11.99#ibcon#enter sib2, iclass 13, count 0 2006.280.07:51:11.99#ibcon#flushed, iclass 13, count 0 2006.280.07:51:11.99#ibcon#about to write, iclass 13, count 0 2006.280.07:51:11.99#ibcon#wrote, iclass 13, count 0 2006.280.07:51:11.99#ibcon#about to read 3, iclass 13, count 0 2006.280.07:51:12.02#ibcon#read 3, iclass 13, count 0 2006.280.07:51:12.02#ibcon#about to read 4, iclass 13, count 0 2006.280.07:51:12.02#ibcon#read 4, iclass 13, count 0 2006.280.07:51:12.02#ibcon#about to read 5, iclass 13, count 0 2006.280.07:51:12.02#ibcon#read 5, iclass 13, count 0 2006.280.07:51:12.02#ibcon#about to read 6, iclass 13, count 0 2006.280.07:51:12.02#ibcon#read 6, iclass 13, count 0 2006.280.07:51:12.02#ibcon#end of sib2, iclass 13, count 0 2006.280.07:51:12.02#ibcon#*after write, iclass 13, count 0 2006.280.07:51:12.02#ibcon#*before return 0, iclass 13, count 0 2006.280.07:51:12.02#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:12.02#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.07:51:12.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:51:12.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:51:12.02$vc4f8/vblo=4,712.99 2006.280.07:51:12.02#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:51:12.02#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:51:12.02#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:12.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:12.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:12.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:12.02#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:51:12.02#ibcon#first serial, iclass 15, count 0 2006.280.07:51:12.02#ibcon#enter sib2, iclass 15, count 0 2006.280.07:51:12.02#ibcon#flushed, iclass 15, count 0 2006.280.07:51:12.02#ibcon#about to write, iclass 15, count 0 2006.280.07:51:12.02#ibcon#wrote, iclass 15, count 0 2006.280.07:51:12.02#ibcon#about to read 3, iclass 15, count 0 2006.280.07:51:12.04#ibcon#read 3, iclass 15, count 0 2006.280.07:51:12.04#ibcon#about to read 4, iclass 15, count 0 2006.280.07:51:12.04#ibcon#read 4, iclass 15, count 0 2006.280.07:51:12.04#ibcon#about to read 5, iclass 15, count 0 2006.280.07:51:12.04#ibcon#read 5, iclass 15, count 0 2006.280.07:51:12.04#ibcon#about to read 6, iclass 15, count 0 2006.280.07:51:12.04#ibcon#read 6, iclass 15, count 0 2006.280.07:51:12.04#ibcon#end of sib2, iclass 15, count 0 2006.280.07:51:12.04#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:51:12.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:51:12.04#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:51:12.04#ibcon#*before write, iclass 15, count 0 2006.280.07:51:12.04#ibcon#enter sib2, iclass 15, count 0 2006.280.07:51:12.04#ibcon#flushed, iclass 15, count 0 2006.280.07:51:12.04#ibcon#about to write, iclass 15, count 0 2006.280.07:51:12.04#ibcon#wrote, iclass 15, count 0 2006.280.07:51:12.04#ibcon#about to read 3, iclass 15, count 0 2006.280.07:51:12.08#ibcon#read 3, iclass 15, count 0 2006.280.07:51:12.08#ibcon#about to read 4, iclass 15, count 0 2006.280.07:51:12.08#ibcon#read 4, iclass 15, count 0 2006.280.07:51:12.08#ibcon#about to read 5, iclass 15, count 0 2006.280.07:51:12.08#ibcon#read 5, iclass 15, count 0 2006.280.07:51:12.08#ibcon#about to read 6, iclass 15, count 0 2006.280.07:51:12.08#ibcon#read 6, iclass 15, count 0 2006.280.07:51:12.08#ibcon#end of sib2, iclass 15, count 0 2006.280.07:51:12.08#ibcon#*after write, iclass 15, count 0 2006.280.07:51:12.08#ibcon#*before return 0, iclass 15, count 0 2006.280.07:51:12.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:12.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:51:12.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:51:12.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:51:12.08$vc4f8/vb=4,4 2006.280.07:51:12.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.07:51:12.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.07:51:12.08#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:12.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:12.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:12.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:12.14#ibcon#enter wrdev, iclass 17, count 2 2006.280.07:51:12.14#ibcon#first serial, iclass 17, count 2 2006.280.07:51:12.14#ibcon#enter sib2, iclass 17, count 2 2006.280.07:51:12.14#ibcon#flushed, iclass 17, count 2 2006.280.07:51:12.14#ibcon#about to write, iclass 17, count 2 2006.280.07:51:12.14#ibcon#wrote, iclass 17, count 2 2006.280.07:51:12.14#ibcon#about to read 3, iclass 17, count 2 2006.280.07:51:12.16#ibcon#read 3, iclass 17, count 2 2006.280.07:51:12.16#ibcon#about to read 4, iclass 17, count 2 2006.280.07:51:12.16#ibcon#read 4, iclass 17, count 2 2006.280.07:51:12.16#ibcon#about to read 5, iclass 17, count 2 2006.280.07:51:12.16#ibcon#read 5, iclass 17, count 2 2006.280.07:51:12.16#ibcon#about to read 6, iclass 17, count 2 2006.280.07:51:12.16#ibcon#read 6, iclass 17, count 2 2006.280.07:51:12.16#ibcon#end of sib2, iclass 17, count 2 2006.280.07:51:12.16#ibcon#*mode == 0, iclass 17, count 2 2006.280.07:51:12.16#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.07:51:12.16#ibcon#[27=AT04-04\r\n] 2006.280.07:51:12.16#ibcon#*before write, iclass 17, count 2 2006.280.07:51:12.16#ibcon#enter sib2, iclass 17, count 2 2006.280.07:51:12.16#ibcon#flushed, iclass 17, count 2 2006.280.07:51:12.16#ibcon#about to write, iclass 17, count 2 2006.280.07:51:12.16#ibcon#wrote, iclass 17, count 2 2006.280.07:51:12.16#ibcon#about to read 3, iclass 17, count 2 2006.280.07:51:12.20#ibcon#read 3, iclass 17, count 2 2006.280.07:51:12.20#ibcon#about to read 4, iclass 17, count 2 2006.280.07:51:12.20#ibcon#read 4, iclass 17, count 2 2006.280.07:51:12.20#ibcon#about to read 5, iclass 17, count 2 2006.280.07:51:12.20#ibcon#read 5, iclass 17, count 2 2006.280.07:51:12.20#ibcon#about to read 6, iclass 17, count 2 2006.280.07:51:12.20#ibcon#read 6, iclass 17, count 2 2006.280.07:51:12.20#ibcon#end of sib2, iclass 17, count 2 2006.280.07:51:12.20#ibcon#*after write, iclass 17, count 2 2006.280.07:51:12.20#ibcon#*before return 0, iclass 17, count 2 2006.280.07:51:12.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:12.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.07:51:12.20#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.07:51:12.20#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:12.20#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:12.31#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:12.31#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:12.31#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:51:12.31#ibcon#first serial, iclass 17, count 0 2006.280.07:51:12.31#ibcon#enter sib2, iclass 17, count 0 2006.280.07:51:12.31#ibcon#flushed, iclass 17, count 0 2006.280.07:51:12.31#ibcon#about to write, iclass 17, count 0 2006.280.07:51:12.31#ibcon#wrote, iclass 17, count 0 2006.280.07:51:12.31#ibcon#about to read 3, iclass 17, count 0 2006.280.07:51:12.33#ibcon#read 3, iclass 17, count 0 2006.280.07:51:12.33#ibcon#about to read 4, iclass 17, count 0 2006.280.07:51:12.33#ibcon#read 4, iclass 17, count 0 2006.280.07:51:12.33#ibcon#about to read 5, iclass 17, count 0 2006.280.07:51:12.33#ibcon#read 5, iclass 17, count 0 2006.280.07:51:12.33#ibcon#about to read 6, iclass 17, count 0 2006.280.07:51:12.33#ibcon#read 6, iclass 17, count 0 2006.280.07:51:12.33#ibcon#end of sib2, iclass 17, count 0 2006.280.07:51:12.33#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:51:12.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:51:12.33#ibcon#[27=USB\r\n] 2006.280.07:51:12.33#ibcon#*before write, iclass 17, count 0 2006.280.07:51:12.33#ibcon#enter sib2, iclass 17, count 0 2006.280.07:51:12.33#ibcon#flushed, iclass 17, count 0 2006.280.07:51:12.33#ibcon#about to write, iclass 17, count 0 2006.280.07:51:12.33#ibcon#wrote, iclass 17, count 0 2006.280.07:51:12.33#ibcon#about to read 3, iclass 17, count 0 2006.280.07:51:12.36#ibcon#read 3, iclass 17, count 0 2006.280.07:51:12.36#ibcon#about to read 4, iclass 17, count 0 2006.280.07:51:12.36#ibcon#read 4, iclass 17, count 0 2006.280.07:51:12.36#ibcon#about to read 5, iclass 17, count 0 2006.280.07:51:12.36#ibcon#read 5, iclass 17, count 0 2006.280.07:51:12.36#ibcon#about to read 6, iclass 17, count 0 2006.280.07:51:12.36#ibcon#read 6, iclass 17, count 0 2006.280.07:51:12.36#ibcon#end of sib2, iclass 17, count 0 2006.280.07:51:12.36#ibcon#*after write, iclass 17, count 0 2006.280.07:51:12.36#ibcon#*before return 0, iclass 17, count 0 2006.280.07:51:12.36#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:12.36#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.07:51:12.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:51:12.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:51:12.36$vc4f8/vblo=5,744.99 2006.280.07:51:12.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.07:51:12.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.07:51:12.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:12.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:12.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:12.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:12.36#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:51:12.36#ibcon#first serial, iclass 19, count 0 2006.280.07:51:12.36#ibcon#enter sib2, iclass 19, count 0 2006.280.07:51:12.36#ibcon#flushed, iclass 19, count 0 2006.280.07:51:12.36#ibcon#about to write, iclass 19, count 0 2006.280.07:51:12.36#ibcon#wrote, iclass 19, count 0 2006.280.07:51:12.36#ibcon#about to read 3, iclass 19, count 0 2006.280.07:51:12.38#ibcon#read 3, iclass 19, count 0 2006.280.07:51:12.38#ibcon#about to read 4, iclass 19, count 0 2006.280.07:51:12.38#ibcon#read 4, iclass 19, count 0 2006.280.07:51:12.38#ibcon#about to read 5, iclass 19, count 0 2006.280.07:51:12.38#ibcon#read 5, iclass 19, count 0 2006.280.07:51:12.38#ibcon#about to read 6, iclass 19, count 0 2006.280.07:51:12.38#ibcon#read 6, iclass 19, count 0 2006.280.07:51:12.38#ibcon#end of sib2, iclass 19, count 0 2006.280.07:51:12.38#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:51:12.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:51:12.38#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:51:12.38#ibcon#*before write, iclass 19, count 0 2006.280.07:51:12.38#ibcon#enter sib2, iclass 19, count 0 2006.280.07:51:12.38#ibcon#flushed, iclass 19, count 0 2006.280.07:51:12.38#ibcon#about to write, iclass 19, count 0 2006.280.07:51:12.38#ibcon#wrote, iclass 19, count 0 2006.280.07:51:12.38#ibcon#about to read 3, iclass 19, count 0 2006.280.07:51:12.42#ibcon#read 3, iclass 19, count 0 2006.280.07:51:12.42#ibcon#about to read 4, iclass 19, count 0 2006.280.07:51:12.42#ibcon#read 4, iclass 19, count 0 2006.280.07:51:12.42#ibcon#about to read 5, iclass 19, count 0 2006.280.07:51:12.42#ibcon#read 5, iclass 19, count 0 2006.280.07:51:12.42#ibcon#about to read 6, iclass 19, count 0 2006.280.07:51:12.42#ibcon#read 6, iclass 19, count 0 2006.280.07:51:12.42#ibcon#end of sib2, iclass 19, count 0 2006.280.07:51:12.42#ibcon#*after write, iclass 19, count 0 2006.280.07:51:12.42#ibcon#*before return 0, iclass 19, count 0 2006.280.07:51:12.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:12.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.07:51:12.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:51:12.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:51:12.42$vc4f8/vb=5,4 2006.280.07:51:12.44#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.07:51:12.44#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.07:51:12.44#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:12.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:12.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:12.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:12.47#ibcon#enter wrdev, iclass 21, count 2 2006.280.07:51:12.47#ibcon#first serial, iclass 21, count 2 2006.280.07:51:12.47#ibcon#enter sib2, iclass 21, count 2 2006.280.07:51:12.47#ibcon#flushed, iclass 21, count 2 2006.280.07:51:12.47#ibcon#about to write, iclass 21, count 2 2006.280.07:51:12.47#ibcon#wrote, iclass 21, count 2 2006.280.07:51:12.47#ibcon#about to read 3, iclass 21, count 2 2006.280.07:51:12.49#ibcon#read 3, iclass 21, count 2 2006.280.07:51:12.49#ibcon#about to read 4, iclass 21, count 2 2006.280.07:51:12.49#ibcon#read 4, iclass 21, count 2 2006.280.07:51:12.49#ibcon#about to read 5, iclass 21, count 2 2006.280.07:51:12.49#ibcon#read 5, iclass 21, count 2 2006.280.07:51:12.49#ibcon#about to read 6, iclass 21, count 2 2006.280.07:51:12.49#ibcon#read 6, iclass 21, count 2 2006.280.07:51:12.49#ibcon#end of sib2, iclass 21, count 2 2006.280.07:51:12.49#ibcon#*mode == 0, iclass 21, count 2 2006.280.07:51:12.49#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.07:51:12.49#ibcon#[27=AT05-04\r\n] 2006.280.07:51:12.49#ibcon#*before write, iclass 21, count 2 2006.280.07:51:12.49#ibcon#enter sib2, iclass 21, count 2 2006.280.07:51:12.49#ibcon#flushed, iclass 21, count 2 2006.280.07:51:12.49#ibcon#about to write, iclass 21, count 2 2006.280.07:51:12.49#ibcon#wrote, iclass 21, count 2 2006.280.07:51:12.49#ibcon#about to read 3, iclass 21, count 2 2006.280.07:51:12.52#ibcon#read 3, iclass 21, count 2 2006.280.07:51:12.52#ibcon#about to read 4, iclass 21, count 2 2006.280.07:51:12.52#ibcon#read 4, iclass 21, count 2 2006.280.07:51:12.52#ibcon#about to read 5, iclass 21, count 2 2006.280.07:51:12.52#ibcon#read 5, iclass 21, count 2 2006.280.07:51:12.52#ibcon#about to read 6, iclass 21, count 2 2006.280.07:51:12.52#ibcon#read 6, iclass 21, count 2 2006.280.07:51:12.52#ibcon#end of sib2, iclass 21, count 2 2006.280.07:51:12.52#ibcon#*after write, iclass 21, count 2 2006.280.07:51:12.52#ibcon#*before return 0, iclass 21, count 2 2006.280.07:51:12.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:12.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.07:51:12.52#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.07:51:12.52#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:12.52#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:12.64#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:12.64#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:12.64#ibcon#enter wrdev, iclass 21, count 0 2006.280.07:51:12.64#ibcon#first serial, iclass 21, count 0 2006.280.07:51:12.64#ibcon#enter sib2, iclass 21, count 0 2006.280.07:51:12.64#ibcon#flushed, iclass 21, count 0 2006.280.07:51:12.64#ibcon#about to write, iclass 21, count 0 2006.280.07:51:12.64#ibcon#wrote, iclass 21, count 0 2006.280.07:51:12.64#ibcon#about to read 3, iclass 21, count 0 2006.280.07:51:12.66#ibcon#read 3, iclass 21, count 0 2006.280.07:51:12.66#ibcon#about to read 4, iclass 21, count 0 2006.280.07:51:12.66#ibcon#read 4, iclass 21, count 0 2006.280.07:51:12.66#ibcon#about to read 5, iclass 21, count 0 2006.280.07:51:12.66#ibcon#read 5, iclass 21, count 0 2006.280.07:51:12.66#ibcon#about to read 6, iclass 21, count 0 2006.280.07:51:12.66#ibcon#read 6, iclass 21, count 0 2006.280.07:51:12.66#ibcon#end of sib2, iclass 21, count 0 2006.280.07:51:12.66#ibcon#*mode == 0, iclass 21, count 0 2006.280.07:51:12.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.07:51:12.66#ibcon#[27=USB\r\n] 2006.280.07:51:12.66#ibcon#*before write, iclass 21, count 0 2006.280.07:51:12.66#ibcon#enter sib2, iclass 21, count 0 2006.280.07:51:12.66#ibcon#flushed, iclass 21, count 0 2006.280.07:51:12.66#ibcon#about to write, iclass 21, count 0 2006.280.07:51:12.66#ibcon#wrote, iclass 21, count 0 2006.280.07:51:12.66#ibcon#about to read 3, iclass 21, count 0 2006.280.07:51:12.69#ibcon#read 3, iclass 21, count 0 2006.280.07:51:12.69#ibcon#about to read 4, iclass 21, count 0 2006.280.07:51:12.69#ibcon#read 4, iclass 21, count 0 2006.280.07:51:12.69#ibcon#about to read 5, iclass 21, count 0 2006.280.07:51:12.69#ibcon#read 5, iclass 21, count 0 2006.280.07:51:12.69#ibcon#about to read 6, iclass 21, count 0 2006.280.07:51:12.69#ibcon#read 6, iclass 21, count 0 2006.280.07:51:12.69#ibcon#end of sib2, iclass 21, count 0 2006.280.07:51:12.69#ibcon#*after write, iclass 21, count 0 2006.280.07:51:12.69#ibcon#*before return 0, iclass 21, count 0 2006.280.07:51:12.69#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:12.69#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.07:51:12.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.07:51:12.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.07:51:12.69$vc4f8/vblo=6,752.99 2006.280.07:51:12.69#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.07:51:12.69#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.07:51:12.69#ibcon#ireg 17 cls_cnt 0 2006.280.07:51:12.69#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:12.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:12.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:12.69#ibcon#enter wrdev, iclass 23, count 0 2006.280.07:51:12.69#ibcon#first serial, iclass 23, count 0 2006.280.07:51:12.69#ibcon#enter sib2, iclass 23, count 0 2006.280.07:51:12.69#ibcon#flushed, iclass 23, count 0 2006.280.07:51:12.69#ibcon#about to write, iclass 23, count 0 2006.280.07:51:12.69#ibcon#wrote, iclass 23, count 0 2006.280.07:51:12.69#ibcon#about to read 3, iclass 23, count 0 2006.280.07:51:12.71#ibcon#read 3, iclass 23, count 0 2006.280.07:51:12.71#ibcon#about to read 4, iclass 23, count 0 2006.280.07:51:12.71#ibcon#read 4, iclass 23, count 0 2006.280.07:51:12.71#ibcon#about to read 5, iclass 23, count 0 2006.280.07:51:12.71#ibcon#read 5, iclass 23, count 0 2006.280.07:51:12.71#ibcon#about to read 6, iclass 23, count 0 2006.280.07:51:12.71#ibcon#read 6, iclass 23, count 0 2006.280.07:51:12.71#ibcon#end of sib2, iclass 23, count 0 2006.280.07:51:12.71#ibcon#*mode == 0, iclass 23, count 0 2006.280.07:51:12.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.07:51:12.71#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:51:12.71#ibcon#*before write, iclass 23, count 0 2006.280.07:51:12.71#ibcon#enter sib2, iclass 23, count 0 2006.280.07:51:12.71#ibcon#flushed, iclass 23, count 0 2006.280.07:51:12.71#ibcon#about to write, iclass 23, count 0 2006.280.07:51:12.71#ibcon#wrote, iclass 23, count 0 2006.280.07:51:12.71#ibcon#about to read 3, iclass 23, count 0 2006.280.07:51:12.75#ibcon#read 3, iclass 23, count 0 2006.280.07:51:12.75#ibcon#about to read 4, iclass 23, count 0 2006.280.07:51:12.75#ibcon#read 4, iclass 23, count 0 2006.280.07:51:12.75#ibcon#about to read 5, iclass 23, count 0 2006.280.07:51:12.75#ibcon#read 5, iclass 23, count 0 2006.280.07:51:12.75#ibcon#about to read 6, iclass 23, count 0 2006.280.07:51:12.75#ibcon#read 6, iclass 23, count 0 2006.280.07:51:12.75#ibcon#end of sib2, iclass 23, count 0 2006.280.07:51:12.75#ibcon#*after write, iclass 23, count 0 2006.280.07:51:12.75#ibcon#*before return 0, iclass 23, count 0 2006.280.07:51:12.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:12.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.07:51:12.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.07:51:12.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.07:51:12.75$vc4f8/vb=6,4 2006.280.07:51:12.75#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.07:51:12.75#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.07:51:12.75#ibcon#ireg 11 cls_cnt 2 2006.280.07:51:12.75#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:12.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:12.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:12.81#ibcon#enter wrdev, iclass 25, count 2 2006.280.07:51:12.81#ibcon#first serial, iclass 25, count 2 2006.280.07:51:12.81#ibcon#enter sib2, iclass 25, count 2 2006.280.07:51:12.81#ibcon#flushed, iclass 25, count 2 2006.280.07:51:12.81#ibcon#about to write, iclass 25, count 2 2006.280.07:51:12.81#ibcon#wrote, iclass 25, count 2 2006.280.07:51:12.81#ibcon#about to read 3, iclass 25, count 2 2006.280.07:51:12.83#ibcon#read 3, iclass 25, count 2 2006.280.07:51:12.83#ibcon#about to read 4, iclass 25, count 2 2006.280.07:51:12.83#ibcon#read 4, iclass 25, count 2 2006.280.07:51:12.83#ibcon#about to read 5, iclass 25, count 2 2006.280.07:51:12.83#ibcon#read 5, iclass 25, count 2 2006.280.07:51:12.83#ibcon#about to read 6, iclass 25, count 2 2006.280.07:51:12.83#ibcon#read 6, iclass 25, count 2 2006.280.07:51:12.83#ibcon#end of sib2, iclass 25, count 2 2006.280.07:51:12.83#ibcon#*mode == 0, iclass 25, count 2 2006.280.07:51:12.83#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.07:51:12.83#ibcon#[27=AT06-04\r\n] 2006.280.07:51:12.83#ibcon#*before write, iclass 25, count 2 2006.280.07:51:12.83#ibcon#enter sib2, iclass 25, count 2 2006.280.07:51:12.83#ibcon#flushed, iclass 25, count 2 2006.280.07:51:12.83#ibcon#about to write, iclass 25, count 2 2006.280.07:51:12.83#ibcon#wrote, iclass 25, count 2 2006.280.07:51:12.83#ibcon#about to read 3, iclass 25, count 2 2006.280.07:51:12.86#ibcon#read 3, iclass 25, count 2 2006.280.07:51:12.86#ibcon#about to read 4, iclass 25, count 2 2006.280.07:51:12.86#ibcon#read 4, iclass 25, count 2 2006.280.07:51:12.86#ibcon#about to read 5, iclass 25, count 2 2006.280.07:51:12.86#ibcon#read 5, iclass 25, count 2 2006.280.07:51:12.86#ibcon#about to read 6, iclass 25, count 2 2006.280.07:51:12.86#ibcon#read 6, iclass 25, count 2 2006.280.07:51:12.86#ibcon#end of sib2, iclass 25, count 2 2006.280.07:51:12.86#ibcon#*after write, iclass 25, count 2 2006.280.07:51:12.86#ibcon#*before return 0, iclass 25, count 2 2006.280.07:51:12.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:12.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.07:51:12.86#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.07:51:12.86#ibcon#ireg 7 cls_cnt 0 2006.280.07:51:12.86#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:12.98#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:12.98#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:12.98#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:51:12.98#ibcon#first serial, iclass 25, count 0 2006.280.07:51:12.98#ibcon#enter sib2, iclass 25, count 0 2006.280.07:51:12.98#ibcon#flushed, iclass 25, count 0 2006.280.07:51:12.98#ibcon#about to write, iclass 25, count 0 2006.280.07:51:12.98#ibcon#wrote, iclass 25, count 0 2006.280.07:51:12.98#ibcon#about to read 3, iclass 25, count 0 2006.280.07:51:13.00#ibcon#read 3, iclass 25, count 0 2006.280.07:51:13.00#ibcon#about to read 4, iclass 25, count 0 2006.280.07:51:13.00#ibcon#read 4, iclass 25, count 0 2006.280.07:51:13.00#ibcon#about to read 5, iclass 25, count 0 2006.280.07:51:13.00#ibcon#read 5, iclass 25, count 0 2006.280.07:51:13.00#ibcon#about to read 6, iclass 25, count 0 2006.280.07:51:13.00#ibcon#read 6, iclass 25, count 0 2006.280.07:51:13.00#ibcon#end of sib2, iclass 25, count 0 2006.280.07:51:13.00#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:51:13.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:51:13.00#ibcon#[27=USB\r\n] 2006.280.07:51:13.00#ibcon#*before write, iclass 25, count 0 2006.280.07:51:13.00#ibcon#enter sib2, iclass 25, count 0 2006.280.07:51:13.00#ibcon#flushed, iclass 25, count 0 2006.280.07:51:13.00#ibcon#about to write, iclass 25, count 0 2006.280.07:51:13.00#ibcon#wrote, iclass 25, count 0 2006.280.07:51:13.00#ibcon#about to read 3, iclass 25, count 0 2006.280.07:51:13.03#ibcon#read 3, iclass 25, count 0 2006.280.07:51:13.03#ibcon#about to read 4, iclass 25, count 0 2006.280.07:51:13.03#ibcon#read 4, iclass 25, count 0 2006.280.07:51:13.03#ibcon#about to read 5, iclass 25, count 0 2006.280.07:51:13.03#ibcon#read 5, iclass 25, count 0 2006.280.07:51:13.03#ibcon#about to read 6, iclass 25, count 0 2006.280.07:51:13.03#ibcon#read 6, iclass 25, count 0 2006.280.07:51:13.03#ibcon#end of sib2, iclass 25, count 0 2006.280.07:51:13.03#ibcon#*after write, iclass 25, count 0 2006.280.07:51:13.03#ibcon#*before return 0, iclass 25, count 0 2006.280.07:51:13.03#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:13.03#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.07:51:13.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:51:13.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:51:13.03$vc4f8/vabw=wide 2006.280.07:51:13.03#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.07:51:13.03#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.07:51:13.03#ibcon#ireg 8 cls_cnt 0 2006.280.07:51:13.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:13.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:13.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:13.03#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:51:13.03#ibcon#first serial, iclass 27, count 0 2006.280.07:51:13.03#ibcon#enter sib2, iclass 27, count 0 2006.280.07:51:13.03#ibcon#flushed, iclass 27, count 0 2006.280.07:51:13.03#ibcon#about to write, iclass 27, count 0 2006.280.07:51:13.03#ibcon#wrote, iclass 27, count 0 2006.280.07:51:13.03#ibcon#about to read 3, iclass 27, count 0 2006.280.07:51:13.05#ibcon#read 3, iclass 27, count 0 2006.280.07:51:13.05#ibcon#about to read 4, iclass 27, count 0 2006.280.07:51:13.05#ibcon#read 4, iclass 27, count 0 2006.280.07:51:13.05#ibcon#about to read 5, iclass 27, count 0 2006.280.07:51:13.05#ibcon#read 5, iclass 27, count 0 2006.280.07:51:13.05#ibcon#about to read 6, iclass 27, count 0 2006.280.07:51:13.05#ibcon#read 6, iclass 27, count 0 2006.280.07:51:13.05#ibcon#end of sib2, iclass 27, count 0 2006.280.07:51:13.05#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:51:13.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:51:13.05#ibcon#[25=BW32\r\n] 2006.280.07:51:13.05#ibcon#*before write, iclass 27, count 0 2006.280.07:51:13.05#ibcon#enter sib2, iclass 27, count 0 2006.280.07:51:13.05#ibcon#flushed, iclass 27, count 0 2006.280.07:51:13.05#ibcon#about to write, iclass 27, count 0 2006.280.07:51:13.05#ibcon#wrote, iclass 27, count 0 2006.280.07:51:13.05#ibcon#about to read 3, iclass 27, count 0 2006.280.07:51:13.08#ibcon#read 3, iclass 27, count 0 2006.280.07:51:13.08#ibcon#about to read 4, iclass 27, count 0 2006.280.07:51:13.08#ibcon#read 4, iclass 27, count 0 2006.280.07:51:13.08#ibcon#about to read 5, iclass 27, count 0 2006.280.07:51:13.08#ibcon#read 5, iclass 27, count 0 2006.280.07:51:13.08#ibcon#about to read 6, iclass 27, count 0 2006.280.07:51:13.08#ibcon#read 6, iclass 27, count 0 2006.280.07:51:13.08#ibcon#end of sib2, iclass 27, count 0 2006.280.07:51:13.08#ibcon#*after write, iclass 27, count 0 2006.280.07:51:13.08#ibcon#*before return 0, iclass 27, count 0 2006.280.07:51:13.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:13.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.07:51:13.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:51:13.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:51:13.08$vc4f8/vbbw=wide 2006.280.07:51:13.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:51:13.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:51:13.08#ibcon#ireg 8 cls_cnt 0 2006.280.07:51:13.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:51:13.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:51:13.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:51:13.15#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:51:13.15#ibcon#first serial, iclass 29, count 0 2006.280.07:51:13.15#ibcon#enter sib2, iclass 29, count 0 2006.280.07:51:13.15#ibcon#flushed, iclass 29, count 0 2006.280.07:51:13.15#ibcon#about to write, iclass 29, count 0 2006.280.07:51:13.15#ibcon#wrote, iclass 29, count 0 2006.280.07:51:13.15#ibcon#about to read 3, iclass 29, count 0 2006.280.07:51:13.17#ibcon#read 3, iclass 29, count 0 2006.280.07:51:13.17#ibcon#about to read 4, iclass 29, count 0 2006.280.07:51:13.17#ibcon#read 4, iclass 29, count 0 2006.280.07:51:13.17#ibcon#about to read 5, iclass 29, count 0 2006.280.07:51:13.17#ibcon#read 5, iclass 29, count 0 2006.280.07:51:13.17#ibcon#about to read 6, iclass 29, count 0 2006.280.07:51:13.17#ibcon#read 6, iclass 29, count 0 2006.280.07:51:13.17#ibcon#end of sib2, iclass 29, count 0 2006.280.07:51:13.17#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:51:13.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:51:13.17#ibcon#[27=BW32\r\n] 2006.280.07:51:13.17#ibcon#*before write, iclass 29, count 0 2006.280.07:51:13.17#ibcon#enter sib2, iclass 29, count 0 2006.280.07:51:13.17#ibcon#flushed, iclass 29, count 0 2006.280.07:51:13.17#ibcon#about to write, iclass 29, count 0 2006.280.07:51:13.17#ibcon#wrote, iclass 29, count 0 2006.280.07:51:13.17#ibcon#about to read 3, iclass 29, count 0 2006.280.07:51:13.20#ibcon#read 3, iclass 29, count 0 2006.280.07:51:13.20#ibcon#about to read 4, iclass 29, count 0 2006.280.07:51:13.20#ibcon#read 4, iclass 29, count 0 2006.280.07:51:13.20#ibcon#about to read 5, iclass 29, count 0 2006.280.07:51:13.20#ibcon#read 5, iclass 29, count 0 2006.280.07:51:13.20#ibcon#about to read 6, iclass 29, count 0 2006.280.07:51:13.20#ibcon#read 6, iclass 29, count 0 2006.280.07:51:13.20#ibcon#end of sib2, iclass 29, count 0 2006.280.07:51:13.20#ibcon#*after write, iclass 29, count 0 2006.280.07:51:13.20#ibcon#*before return 0, iclass 29, count 0 2006.280.07:51:13.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:51:13.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:51:13.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:51:13.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:51:13.20$4f8m12a/ifd4f 2006.280.07:51:13.20$ifd4f/lo= 2006.280.07:51:13.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:51:13.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:51:13.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:51:13.20$ifd4f/patch= 2006.280.07:51:13.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:51:13.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:51:13.21$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:51:13.21$4f8m12a/"form=m,16.000,1:2 2006.280.07:51:13.21$4f8m12a/"tpicd 2006.280.07:51:13.21$4f8m12a/echo=off 2006.280.07:51:13.21$4f8m12a/xlog=off 2006.280.07:51:13.21:!2006.280.07:51:40 2006.280.07:51:24.13#trakl#Source acquired 2006.280.07:51:25.13#flagr#flagr/antenna,acquired 2006.280.07:51:40.01:preob 2006.280.07:51:41.13/onsource/TRACKING 2006.280.07:51:41.13:!2006.280.07:51:50 2006.280.07:51:50.00:data_valid=on 2006.280.07:51:50.00:midob 2006.280.07:51:50.13/onsource/TRACKING 2006.280.07:51:50.13/wx/21.19,987.0,59 2006.280.07:51:50.32/cable/+6.4845E-03 2006.280.07:51:51.41/va/01,07,usb,yes,32,33 2006.280.07:51:51.41/va/02,06,usb,yes,29,31 2006.280.07:51:51.41/va/03,06,usb,yes,28,28 2006.280.07:51:51.41/va/04,06,usb,yes,31,33 2006.280.07:51:51.41/va/05,07,usb,yes,28,30 2006.280.07:51:51.41/va/06,06,usb,yes,27,27 2006.280.07:51:51.41/va/07,06,usb,yes,28,27 2006.280.07:51:51.41/va/08,06,usb,yes,30,29 2006.280.07:51:51.64/valo/01,532.99,yes,locked 2006.280.07:51:51.64/valo/02,572.99,yes,locked 2006.280.07:51:51.64/valo/03,672.99,yes,locked 2006.280.07:51:51.64/valo/04,832.99,yes,locked 2006.280.07:51:51.64/valo/05,652.99,yes,locked 2006.280.07:51:51.64/valo/06,772.99,yes,locked 2006.280.07:51:51.64/valo/07,832.99,yes,locked 2006.280.07:51:51.64/valo/08,852.99,yes,locked 2006.280.07:51:52.73/vb/01,04,usb,yes,30,29 2006.280.07:51:52.73/vb/02,05,usb,yes,28,29 2006.280.07:51:52.73/vb/03,04,usb,yes,28,32 2006.280.07:51:52.73/vb/04,04,usb,yes,29,29 2006.280.07:51:52.73/vb/05,04,usb,yes,27,31 2006.280.07:51:52.73/vb/06,04,usb,yes,27,31 2006.280.07:51:52.73/vb/07,04,usb,yes,30,30 2006.280.07:51:52.73/vb/08,04,usb,yes,27,31 2006.280.07:51:52.96/vblo/01,632.99,yes,locked 2006.280.07:51:52.96/vblo/02,640.99,yes,locked 2006.280.07:51:52.96/vblo/03,656.99,yes,locked 2006.280.07:51:52.96/vblo/04,712.99,yes,locked 2006.280.07:51:52.96/vblo/05,744.99,yes,locked 2006.280.07:51:52.96/vblo/06,752.99,yes,locked 2006.280.07:51:52.96/vblo/07,734.99,yes,locked 2006.280.07:51:52.96/vblo/08,744.99,yes,locked 2006.280.07:51:53.11/vabw/8 2006.280.07:51:53.26/vbbw/8 2006.280.07:51:53.42/xfe/off,on,12.2 2006.280.07:51:53.80/ifatt/23,28,28,28 2006.280.07:51:54.08/fmout-gps/S +3.18E-07 2006.280.07:51:54.11:!2006.280.07:52:50 2006.280.07:52:50.01:data_valid=off 2006.280.07:52:50.02:postob 2006.280.07:52:50.10/cable/+6.4830E-03 2006.280.07:52:50.11/wx/21.15,987.0,60 2006.280.07:52:51.07/fmout-gps/S +3.20E-07 2006.280.07:52:51.08:scan_name=280-0754,k06280,60 2006.280.07:52:51.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.280.07:52:51.13#flagr#flagr/antenna,new-source 2006.280.07:52:52.13:checkk5 2006.280.07:52:52.60/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:52:53.04/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:52:53.44/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:52:53.81/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:52:54.25/chk_obsdata//k5ts1/T2800751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:52:54.65/chk_obsdata//k5ts2/T2800751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:52:55.25/chk_obsdata//k5ts3/T2800751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:52:55.65/chk_obsdata//k5ts4/T2800751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.07:52:56.88/k5log//k5ts1_log_newline 2006.280.07:52:57.59/k5log//k5ts2_log_newline 2006.280.07:52:58.40/k5log//k5ts3_log_newline 2006.280.07:52:59.21/k5log//k5ts4_log_newline 2006.280.07:52:59.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:52:59.24:4f8m12a=2 2006.280.07:52:59.24$4f8m12a/echo=on 2006.280.07:52:59.24$4f8m12a/pcalon 2006.280.07:52:59.24$pcalon/"no phase cal control is implemented here 2006.280.07:52:59.24$4f8m12a/"tpicd=stop 2006.280.07:52:59.24$4f8m12a/vc4f8 2006.280.07:52:59.24$vc4f8/valo=1,532.99 2006.280.07:52:59.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:52:59.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:52:59.25#ibcon#ireg 17 cls_cnt 0 2006.280.07:52:59.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:52:59.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:52:59.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:52:59.25#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:52:59.25#ibcon#first serial, iclass 40, count 0 2006.280.07:52:59.25#ibcon#enter sib2, iclass 40, count 0 2006.280.07:52:59.25#ibcon#flushed, iclass 40, count 0 2006.280.07:52:59.25#ibcon#about to write, iclass 40, count 0 2006.280.07:52:59.25#ibcon#wrote, iclass 40, count 0 2006.280.07:52:59.25#ibcon#about to read 3, iclass 40, count 0 2006.280.07:52:59.26#ibcon#read 3, iclass 40, count 0 2006.280.07:52:59.26#ibcon#about to read 4, iclass 40, count 0 2006.280.07:52:59.26#ibcon#read 4, iclass 40, count 0 2006.280.07:52:59.26#ibcon#about to read 5, iclass 40, count 0 2006.280.07:52:59.26#ibcon#read 5, iclass 40, count 0 2006.280.07:52:59.26#ibcon#about to read 6, iclass 40, count 0 2006.280.07:52:59.26#ibcon#read 6, iclass 40, count 0 2006.280.07:52:59.26#ibcon#end of sib2, iclass 40, count 0 2006.280.07:52:59.26#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:52:59.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:52:59.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:52:59.26#ibcon#*before write, iclass 40, count 0 2006.280.07:52:59.26#ibcon#enter sib2, iclass 40, count 0 2006.280.07:52:59.26#ibcon#flushed, iclass 40, count 0 2006.280.07:52:59.26#ibcon#about to write, iclass 40, count 0 2006.280.07:52:59.26#ibcon#wrote, iclass 40, count 0 2006.280.07:52:59.26#ibcon#about to read 3, iclass 40, count 0 2006.280.07:52:59.32#ibcon#read 3, iclass 40, count 0 2006.280.07:52:59.32#ibcon#about to read 4, iclass 40, count 0 2006.280.07:52:59.32#ibcon#read 4, iclass 40, count 0 2006.280.07:52:59.32#ibcon#about to read 5, iclass 40, count 0 2006.280.07:52:59.32#ibcon#read 5, iclass 40, count 0 2006.280.07:52:59.32#ibcon#about to read 6, iclass 40, count 0 2006.280.07:52:59.32#ibcon#read 6, iclass 40, count 0 2006.280.07:52:59.32#ibcon#end of sib2, iclass 40, count 0 2006.280.07:52:59.32#ibcon#*after write, iclass 40, count 0 2006.280.07:52:59.32#ibcon#*before return 0, iclass 40, count 0 2006.280.07:52:59.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:52:59.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:52:59.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:52:59.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:52:59.32$vc4f8/va=1,7 2006.280.07:52:59.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.07:52:59.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.07:52:59.36#ibcon#ireg 11 cls_cnt 2 2006.280.07:52:59.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:52:59.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:52:59.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:52:59.36#ibcon#enter wrdev, iclass 4, count 2 2006.280.07:52:59.36#ibcon#first serial, iclass 4, count 2 2006.280.07:52:59.36#ibcon#enter sib2, iclass 4, count 2 2006.280.07:52:59.36#ibcon#flushed, iclass 4, count 2 2006.280.07:52:59.36#ibcon#about to write, iclass 4, count 2 2006.280.07:52:59.36#ibcon#wrote, iclass 4, count 2 2006.280.07:52:59.36#ibcon#about to read 3, iclass 4, count 2 2006.280.07:52:59.37#ibcon#read 3, iclass 4, count 2 2006.280.07:52:59.37#ibcon#about to read 4, iclass 4, count 2 2006.280.07:52:59.37#ibcon#read 4, iclass 4, count 2 2006.280.07:52:59.37#ibcon#about to read 5, iclass 4, count 2 2006.280.07:52:59.37#ibcon#read 5, iclass 4, count 2 2006.280.07:52:59.37#ibcon#about to read 6, iclass 4, count 2 2006.280.07:52:59.37#ibcon#read 6, iclass 4, count 2 2006.280.07:52:59.37#ibcon#end of sib2, iclass 4, count 2 2006.280.07:52:59.37#ibcon#*mode == 0, iclass 4, count 2 2006.280.07:52:59.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.07:52:59.37#ibcon#[25=AT01-07\r\n] 2006.280.07:52:59.37#ibcon#*before write, iclass 4, count 2 2006.280.07:52:59.37#ibcon#enter sib2, iclass 4, count 2 2006.280.07:52:59.37#ibcon#flushed, iclass 4, count 2 2006.280.07:52:59.37#ibcon#about to write, iclass 4, count 2 2006.280.07:52:59.37#ibcon#wrote, iclass 4, count 2 2006.280.07:52:59.37#ibcon#about to read 3, iclass 4, count 2 2006.280.07:52:59.40#ibcon#read 3, iclass 4, count 2 2006.280.07:52:59.40#ibcon#about to read 4, iclass 4, count 2 2006.280.07:52:59.40#ibcon#read 4, iclass 4, count 2 2006.280.07:52:59.40#ibcon#about to read 5, iclass 4, count 2 2006.280.07:52:59.40#ibcon#read 5, iclass 4, count 2 2006.280.07:52:59.40#ibcon#about to read 6, iclass 4, count 2 2006.280.07:52:59.40#ibcon#read 6, iclass 4, count 2 2006.280.07:52:59.40#ibcon#end of sib2, iclass 4, count 2 2006.280.07:52:59.40#ibcon#*after write, iclass 4, count 2 2006.280.07:52:59.40#ibcon#*before return 0, iclass 4, count 2 2006.280.07:52:59.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:52:59.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:52:59.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.07:52:59.40#ibcon#ireg 7 cls_cnt 0 2006.280.07:52:59.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:52:59.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:52:59.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:52:59.53#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:52:59.53#ibcon#first serial, iclass 4, count 0 2006.280.07:52:59.53#ibcon#enter sib2, iclass 4, count 0 2006.280.07:52:59.53#ibcon#flushed, iclass 4, count 0 2006.280.07:52:59.53#ibcon#about to write, iclass 4, count 0 2006.280.07:52:59.53#ibcon#wrote, iclass 4, count 0 2006.280.07:52:59.53#ibcon#about to read 3, iclass 4, count 0 2006.280.07:52:59.54#ibcon#read 3, iclass 4, count 0 2006.280.07:52:59.54#ibcon#about to read 4, iclass 4, count 0 2006.280.07:52:59.54#ibcon#read 4, iclass 4, count 0 2006.280.07:52:59.54#ibcon#about to read 5, iclass 4, count 0 2006.280.07:52:59.54#ibcon#read 5, iclass 4, count 0 2006.280.07:52:59.54#ibcon#about to read 6, iclass 4, count 0 2006.280.07:52:59.54#ibcon#read 6, iclass 4, count 0 2006.280.07:52:59.54#ibcon#end of sib2, iclass 4, count 0 2006.280.07:52:59.54#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:52:59.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:52:59.54#ibcon#[25=USB\r\n] 2006.280.07:52:59.54#ibcon#*before write, iclass 4, count 0 2006.280.07:52:59.54#ibcon#enter sib2, iclass 4, count 0 2006.280.07:52:59.54#ibcon#flushed, iclass 4, count 0 2006.280.07:52:59.54#ibcon#about to write, iclass 4, count 0 2006.280.07:52:59.54#ibcon#wrote, iclass 4, count 0 2006.280.07:52:59.54#ibcon#about to read 3, iclass 4, count 0 2006.280.07:52:59.57#ibcon#read 3, iclass 4, count 0 2006.280.07:52:59.57#ibcon#about to read 4, iclass 4, count 0 2006.280.07:52:59.57#ibcon#read 4, iclass 4, count 0 2006.280.07:52:59.57#ibcon#about to read 5, iclass 4, count 0 2006.280.07:52:59.57#ibcon#read 5, iclass 4, count 0 2006.280.07:52:59.57#ibcon#about to read 6, iclass 4, count 0 2006.280.07:52:59.57#ibcon#read 6, iclass 4, count 0 2006.280.07:52:59.57#ibcon#end of sib2, iclass 4, count 0 2006.280.07:52:59.57#ibcon#*after write, iclass 4, count 0 2006.280.07:52:59.57#ibcon#*before return 0, iclass 4, count 0 2006.280.07:52:59.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:52:59.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:52:59.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:52:59.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:52:59.57$vc4f8/valo=2,572.99 2006.280.07:52:59.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.07:52:59.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.07:52:59.57#ibcon#ireg 17 cls_cnt 0 2006.280.07:52:59.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:52:59.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:52:59.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:52:59.57#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:52:59.57#ibcon#first serial, iclass 6, count 0 2006.280.07:52:59.57#ibcon#enter sib2, iclass 6, count 0 2006.280.07:52:59.57#ibcon#flushed, iclass 6, count 0 2006.280.07:52:59.57#ibcon#about to write, iclass 6, count 0 2006.280.07:52:59.57#ibcon#wrote, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to read 3, iclass 6, count 0 2006.280.07:52:59.60#ibcon#read 3, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to read 4, iclass 6, count 0 2006.280.07:52:59.60#ibcon#read 4, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to read 5, iclass 6, count 0 2006.280.07:52:59.60#ibcon#read 5, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to read 6, iclass 6, count 0 2006.280.07:52:59.60#ibcon#read 6, iclass 6, count 0 2006.280.07:52:59.60#ibcon#end of sib2, iclass 6, count 0 2006.280.07:52:59.60#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:52:59.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:52:59.60#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:52:59.60#ibcon#*before write, iclass 6, count 0 2006.280.07:52:59.60#ibcon#enter sib2, iclass 6, count 0 2006.280.07:52:59.60#ibcon#flushed, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to write, iclass 6, count 0 2006.280.07:52:59.60#ibcon#wrote, iclass 6, count 0 2006.280.07:52:59.60#ibcon#about to read 3, iclass 6, count 0 2006.280.07:52:59.64#ibcon#read 3, iclass 6, count 0 2006.280.07:52:59.64#ibcon#about to read 4, iclass 6, count 0 2006.280.07:52:59.64#ibcon#read 4, iclass 6, count 0 2006.280.07:52:59.64#ibcon#about to read 5, iclass 6, count 0 2006.280.07:52:59.64#ibcon#read 5, iclass 6, count 0 2006.280.07:52:59.64#ibcon#about to read 6, iclass 6, count 0 2006.280.07:52:59.64#ibcon#read 6, iclass 6, count 0 2006.280.07:52:59.64#ibcon#end of sib2, iclass 6, count 0 2006.280.07:52:59.64#ibcon#*after write, iclass 6, count 0 2006.280.07:52:59.64#ibcon#*before return 0, iclass 6, count 0 2006.280.07:52:59.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:52:59.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:52:59.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:52:59.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:52:59.64$vc4f8/va=2,6 2006.280.07:52:59.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.07:52:59.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.07:52:59.64#ibcon#ireg 11 cls_cnt 2 2006.280.07:52:59.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:52:59.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:52:59.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:52:59.70#ibcon#enter wrdev, iclass 10, count 2 2006.280.07:52:59.70#ibcon#first serial, iclass 10, count 2 2006.280.07:52:59.70#ibcon#enter sib2, iclass 10, count 2 2006.280.07:52:59.70#ibcon#flushed, iclass 10, count 2 2006.280.07:52:59.70#ibcon#about to write, iclass 10, count 2 2006.280.07:52:59.70#ibcon#wrote, iclass 10, count 2 2006.280.07:52:59.70#ibcon#about to read 3, iclass 10, count 2 2006.280.07:52:59.71#ibcon#read 3, iclass 10, count 2 2006.280.07:52:59.71#ibcon#about to read 4, iclass 10, count 2 2006.280.07:52:59.71#ibcon#read 4, iclass 10, count 2 2006.280.07:52:59.71#ibcon#about to read 5, iclass 10, count 2 2006.280.07:52:59.71#ibcon#read 5, iclass 10, count 2 2006.280.07:52:59.71#ibcon#about to read 6, iclass 10, count 2 2006.280.07:52:59.72#ibcon#read 6, iclass 10, count 2 2006.280.07:52:59.72#ibcon#end of sib2, iclass 10, count 2 2006.280.07:52:59.72#ibcon#*mode == 0, iclass 10, count 2 2006.280.07:52:59.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.07:52:59.72#ibcon#[25=AT02-06\r\n] 2006.280.07:52:59.72#ibcon#*before write, iclass 10, count 2 2006.280.07:52:59.72#ibcon#enter sib2, iclass 10, count 2 2006.280.07:52:59.72#ibcon#flushed, iclass 10, count 2 2006.280.07:52:59.72#ibcon#about to write, iclass 10, count 2 2006.280.07:52:59.72#ibcon#wrote, iclass 10, count 2 2006.280.07:52:59.72#ibcon#about to read 3, iclass 10, count 2 2006.280.07:52:59.75#ibcon#read 3, iclass 10, count 2 2006.280.07:52:59.75#ibcon#about to read 4, iclass 10, count 2 2006.280.07:52:59.75#ibcon#read 4, iclass 10, count 2 2006.280.07:52:59.75#ibcon#about to read 5, iclass 10, count 2 2006.280.07:52:59.75#ibcon#read 5, iclass 10, count 2 2006.280.07:52:59.75#ibcon#about to read 6, iclass 10, count 2 2006.280.07:52:59.75#ibcon#read 6, iclass 10, count 2 2006.280.07:52:59.75#ibcon#end of sib2, iclass 10, count 2 2006.280.07:52:59.75#ibcon#*after write, iclass 10, count 2 2006.280.07:52:59.75#ibcon#*before return 0, iclass 10, count 2 2006.280.07:52:59.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:52:59.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:52:59.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.07:52:59.75#ibcon#ireg 7 cls_cnt 0 2006.280.07:52:59.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:52:59.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:52:59.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:52:59.87#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:52:59.87#ibcon#first serial, iclass 10, count 0 2006.280.07:52:59.87#ibcon#enter sib2, iclass 10, count 0 2006.280.07:52:59.87#ibcon#flushed, iclass 10, count 0 2006.280.07:52:59.87#ibcon#about to write, iclass 10, count 0 2006.280.07:52:59.87#ibcon#wrote, iclass 10, count 0 2006.280.07:52:59.87#ibcon#about to read 3, iclass 10, count 0 2006.280.07:52:59.89#ibcon#read 3, iclass 10, count 0 2006.280.07:52:59.89#ibcon#about to read 4, iclass 10, count 0 2006.280.07:52:59.89#ibcon#read 4, iclass 10, count 0 2006.280.07:52:59.89#ibcon#about to read 5, iclass 10, count 0 2006.280.07:52:59.89#ibcon#read 5, iclass 10, count 0 2006.280.07:52:59.89#ibcon#about to read 6, iclass 10, count 0 2006.280.07:52:59.89#ibcon#read 6, iclass 10, count 0 2006.280.07:52:59.89#ibcon#end of sib2, iclass 10, count 0 2006.280.07:52:59.89#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:52:59.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:52:59.89#ibcon#[25=USB\r\n] 2006.280.07:52:59.89#ibcon#*before write, iclass 10, count 0 2006.280.07:52:59.89#ibcon#enter sib2, iclass 10, count 0 2006.280.07:52:59.89#ibcon#flushed, iclass 10, count 0 2006.280.07:52:59.89#ibcon#about to write, iclass 10, count 0 2006.280.07:52:59.89#ibcon#wrote, iclass 10, count 0 2006.280.07:52:59.89#ibcon#about to read 3, iclass 10, count 0 2006.280.07:52:59.92#ibcon#read 3, iclass 10, count 0 2006.280.07:52:59.92#ibcon#about to read 4, iclass 10, count 0 2006.280.07:52:59.92#ibcon#read 4, iclass 10, count 0 2006.280.07:52:59.92#ibcon#about to read 5, iclass 10, count 0 2006.280.07:52:59.92#ibcon#read 5, iclass 10, count 0 2006.280.07:52:59.92#ibcon#about to read 6, iclass 10, count 0 2006.280.07:52:59.92#ibcon#read 6, iclass 10, count 0 2006.280.07:52:59.92#ibcon#end of sib2, iclass 10, count 0 2006.280.07:52:59.92#ibcon#*after write, iclass 10, count 0 2006.280.07:52:59.92#ibcon#*before return 0, iclass 10, count 0 2006.280.07:52:59.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:52:59.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:52:59.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:52:59.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:52:59.92$vc4f8/valo=3,672.99 2006.280.07:52:59.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.07:52:59.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.07:52:59.92#ibcon#ireg 17 cls_cnt 0 2006.280.07:52:59.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:52:59.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:52:59.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:52:59.92#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:52:59.92#ibcon#first serial, iclass 12, count 0 2006.280.07:52:59.92#ibcon#enter sib2, iclass 12, count 0 2006.280.07:52:59.92#ibcon#flushed, iclass 12, count 0 2006.280.07:52:59.92#ibcon#about to write, iclass 12, count 0 2006.280.07:52:59.92#ibcon#wrote, iclass 12, count 0 2006.280.07:52:59.92#ibcon#about to read 3, iclass 12, count 0 2006.280.07:52:59.94#ibcon#read 3, iclass 12, count 0 2006.280.07:52:59.94#ibcon#about to read 4, iclass 12, count 0 2006.280.07:52:59.94#ibcon#read 4, iclass 12, count 0 2006.280.07:52:59.95#ibcon#about to read 5, iclass 12, count 0 2006.280.07:52:59.95#ibcon#read 5, iclass 12, count 0 2006.280.07:52:59.95#ibcon#about to read 6, iclass 12, count 0 2006.280.07:52:59.95#ibcon#read 6, iclass 12, count 0 2006.280.07:52:59.95#ibcon#end of sib2, iclass 12, count 0 2006.280.07:52:59.95#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:52:59.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:52:59.95#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:52:59.95#ibcon#*before write, iclass 12, count 0 2006.280.07:52:59.95#ibcon#enter sib2, iclass 12, count 0 2006.280.07:52:59.95#ibcon#flushed, iclass 12, count 0 2006.280.07:52:59.95#ibcon#about to write, iclass 12, count 0 2006.280.07:52:59.95#ibcon#wrote, iclass 12, count 0 2006.280.07:52:59.95#ibcon#about to read 3, iclass 12, count 0 2006.280.07:52:59.99#ibcon#read 3, iclass 12, count 0 2006.280.07:52:59.99#ibcon#about to read 4, iclass 12, count 0 2006.280.07:52:59.99#ibcon#read 4, iclass 12, count 0 2006.280.07:52:59.99#ibcon#about to read 5, iclass 12, count 0 2006.280.07:52:59.99#ibcon#read 5, iclass 12, count 0 2006.280.07:52:59.99#ibcon#about to read 6, iclass 12, count 0 2006.280.07:52:59.99#ibcon#read 6, iclass 12, count 0 2006.280.07:52:59.99#ibcon#end of sib2, iclass 12, count 0 2006.280.07:52:59.99#ibcon#*after write, iclass 12, count 0 2006.280.07:52:59.99#ibcon#*before return 0, iclass 12, count 0 2006.280.07:52:59.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:52:59.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:52:59.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:52:59.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:52:59.99$vc4f8/va=3,6 2006.280.07:52:59.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.07:52:59.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.07:52:59.99#ibcon#ireg 11 cls_cnt 2 2006.280.07:52:59.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:00.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:00.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:00.04#ibcon#enter wrdev, iclass 14, count 2 2006.280.07:53:00.04#ibcon#first serial, iclass 14, count 2 2006.280.07:53:00.04#ibcon#enter sib2, iclass 14, count 2 2006.280.07:53:00.04#ibcon#flushed, iclass 14, count 2 2006.280.07:53:00.04#ibcon#about to write, iclass 14, count 2 2006.280.07:53:00.04#ibcon#wrote, iclass 14, count 2 2006.280.07:53:00.04#ibcon#about to read 3, iclass 14, count 2 2006.280.07:53:00.06#ibcon#read 3, iclass 14, count 2 2006.280.07:53:00.06#ibcon#about to read 4, iclass 14, count 2 2006.280.07:53:00.06#ibcon#read 4, iclass 14, count 2 2006.280.07:53:00.06#ibcon#about to read 5, iclass 14, count 2 2006.280.07:53:00.06#ibcon#read 5, iclass 14, count 2 2006.280.07:53:00.06#ibcon#about to read 6, iclass 14, count 2 2006.280.07:53:00.06#ibcon#read 6, iclass 14, count 2 2006.280.07:53:00.06#ibcon#end of sib2, iclass 14, count 2 2006.280.07:53:00.06#ibcon#*mode == 0, iclass 14, count 2 2006.280.07:53:00.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.07:53:00.06#ibcon#[25=AT03-06\r\n] 2006.280.07:53:00.06#ibcon#*before write, iclass 14, count 2 2006.280.07:53:00.06#ibcon#enter sib2, iclass 14, count 2 2006.280.07:53:00.06#ibcon#flushed, iclass 14, count 2 2006.280.07:53:00.06#ibcon#about to write, iclass 14, count 2 2006.280.07:53:00.06#ibcon#wrote, iclass 14, count 2 2006.280.07:53:00.06#ibcon#about to read 3, iclass 14, count 2 2006.280.07:53:00.09#ibcon#read 3, iclass 14, count 2 2006.280.07:53:00.09#ibcon#about to read 4, iclass 14, count 2 2006.280.07:53:00.09#ibcon#read 4, iclass 14, count 2 2006.280.07:53:00.09#ibcon#about to read 5, iclass 14, count 2 2006.280.07:53:00.09#ibcon#read 5, iclass 14, count 2 2006.280.07:53:00.09#ibcon#about to read 6, iclass 14, count 2 2006.280.07:53:00.09#ibcon#read 6, iclass 14, count 2 2006.280.07:53:00.09#ibcon#end of sib2, iclass 14, count 2 2006.280.07:53:00.09#ibcon#*after write, iclass 14, count 2 2006.280.07:53:00.09#ibcon#*before return 0, iclass 14, count 2 2006.280.07:53:00.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:00.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:00.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.07:53:00.09#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:00.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:00.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:00.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:00.21#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:53:00.21#ibcon#first serial, iclass 14, count 0 2006.280.07:53:00.21#ibcon#enter sib2, iclass 14, count 0 2006.280.07:53:00.21#ibcon#flushed, iclass 14, count 0 2006.280.07:53:00.21#ibcon#about to write, iclass 14, count 0 2006.280.07:53:00.21#ibcon#wrote, iclass 14, count 0 2006.280.07:53:00.21#ibcon#about to read 3, iclass 14, count 0 2006.280.07:53:00.23#ibcon#read 3, iclass 14, count 0 2006.280.07:53:00.23#ibcon#about to read 4, iclass 14, count 0 2006.280.07:53:00.23#ibcon#read 4, iclass 14, count 0 2006.280.07:53:00.23#ibcon#about to read 5, iclass 14, count 0 2006.280.07:53:00.23#ibcon#read 5, iclass 14, count 0 2006.280.07:53:00.23#ibcon#about to read 6, iclass 14, count 0 2006.280.07:53:00.23#ibcon#read 6, iclass 14, count 0 2006.280.07:53:00.23#ibcon#end of sib2, iclass 14, count 0 2006.280.07:53:00.23#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:53:00.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:53:00.23#ibcon#[25=USB\r\n] 2006.280.07:53:00.23#ibcon#*before write, iclass 14, count 0 2006.280.07:53:00.23#ibcon#enter sib2, iclass 14, count 0 2006.280.07:53:00.23#ibcon#flushed, iclass 14, count 0 2006.280.07:53:00.23#ibcon#about to write, iclass 14, count 0 2006.280.07:53:00.23#ibcon#wrote, iclass 14, count 0 2006.280.07:53:00.23#ibcon#about to read 3, iclass 14, count 0 2006.280.07:53:00.26#ibcon#read 3, iclass 14, count 0 2006.280.07:53:00.26#ibcon#about to read 4, iclass 14, count 0 2006.280.07:53:00.26#ibcon#read 4, iclass 14, count 0 2006.280.07:53:00.26#ibcon#about to read 5, iclass 14, count 0 2006.280.07:53:00.26#ibcon#read 5, iclass 14, count 0 2006.280.07:53:00.26#ibcon#about to read 6, iclass 14, count 0 2006.280.07:53:00.26#ibcon#read 6, iclass 14, count 0 2006.280.07:53:00.26#ibcon#end of sib2, iclass 14, count 0 2006.280.07:53:00.26#ibcon#*after write, iclass 14, count 0 2006.280.07:53:00.26#ibcon#*before return 0, iclass 14, count 0 2006.280.07:53:00.26#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:00.26#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:00.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:53:00.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:53:00.26$vc4f8/valo=4,832.99 2006.280.07:53:00.26#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:53:00.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:53:00.27#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:00.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:00.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:00.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:00.27#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:53:00.27#ibcon#first serial, iclass 16, count 0 2006.280.07:53:00.27#ibcon#enter sib2, iclass 16, count 0 2006.280.07:53:00.27#ibcon#flushed, iclass 16, count 0 2006.280.07:53:00.27#ibcon#about to write, iclass 16, count 0 2006.280.07:53:00.27#ibcon#wrote, iclass 16, count 0 2006.280.07:53:00.27#ibcon#about to read 3, iclass 16, count 0 2006.280.07:53:00.29#ibcon#read 3, iclass 16, count 0 2006.280.07:53:00.29#ibcon#about to read 4, iclass 16, count 0 2006.280.07:53:00.29#ibcon#read 4, iclass 16, count 0 2006.280.07:53:00.29#ibcon#about to read 5, iclass 16, count 0 2006.280.07:53:00.29#ibcon#read 5, iclass 16, count 0 2006.280.07:53:00.29#ibcon#about to read 6, iclass 16, count 0 2006.280.07:53:00.29#ibcon#read 6, iclass 16, count 0 2006.280.07:53:00.29#ibcon#end of sib2, iclass 16, count 0 2006.280.07:53:00.29#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:53:00.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:53:00.29#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:53:00.29#ibcon#*before write, iclass 16, count 0 2006.280.07:53:00.29#ibcon#enter sib2, iclass 16, count 0 2006.280.07:53:00.29#ibcon#flushed, iclass 16, count 0 2006.280.07:53:00.29#ibcon#about to write, iclass 16, count 0 2006.280.07:53:00.29#ibcon#wrote, iclass 16, count 0 2006.280.07:53:00.29#ibcon#about to read 3, iclass 16, count 0 2006.280.07:53:00.34#ibcon#read 3, iclass 16, count 0 2006.280.07:53:00.34#ibcon#about to read 4, iclass 16, count 0 2006.280.07:53:00.34#ibcon#read 4, iclass 16, count 0 2006.280.07:53:00.34#ibcon#about to read 5, iclass 16, count 0 2006.280.07:53:00.34#ibcon#read 5, iclass 16, count 0 2006.280.07:53:00.34#ibcon#about to read 6, iclass 16, count 0 2006.280.07:53:00.34#ibcon#read 6, iclass 16, count 0 2006.280.07:53:00.34#ibcon#end of sib2, iclass 16, count 0 2006.280.07:53:00.34#ibcon#*after write, iclass 16, count 0 2006.280.07:53:00.34#ibcon#*before return 0, iclass 16, count 0 2006.280.07:53:00.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:00.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:00.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:53:00.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:53:00.34$vc4f8/va=4,6 2006.280.07:53:00.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.07:53:00.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.07:53:00.34#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:00.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:00.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:00.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:00.37#ibcon#enter wrdev, iclass 18, count 2 2006.280.07:53:00.37#ibcon#first serial, iclass 18, count 2 2006.280.07:53:00.37#ibcon#enter sib2, iclass 18, count 2 2006.280.07:53:00.37#ibcon#flushed, iclass 18, count 2 2006.280.07:53:00.37#ibcon#about to write, iclass 18, count 2 2006.280.07:53:00.37#ibcon#wrote, iclass 18, count 2 2006.280.07:53:00.37#ibcon#about to read 3, iclass 18, count 2 2006.280.07:53:00.39#ibcon#read 3, iclass 18, count 2 2006.280.07:53:00.39#ibcon#about to read 4, iclass 18, count 2 2006.280.07:53:00.39#ibcon#read 4, iclass 18, count 2 2006.280.07:53:00.39#ibcon#about to read 5, iclass 18, count 2 2006.280.07:53:00.39#ibcon#read 5, iclass 18, count 2 2006.280.07:53:00.39#ibcon#about to read 6, iclass 18, count 2 2006.280.07:53:00.39#ibcon#read 6, iclass 18, count 2 2006.280.07:53:00.39#ibcon#end of sib2, iclass 18, count 2 2006.280.07:53:00.39#ibcon#*mode == 0, iclass 18, count 2 2006.280.07:53:00.39#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.07:53:00.40#ibcon#[25=AT04-06\r\n] 2006.280.07:53:00.40#ibcon#*before write, iclass 18, count 2 2006.280.07:53:00.40#ibcon#enter sib2, iclass 18, count 2 2006.280.07:53:00.40#ibcon#flushed, iclass 18, count 2 2006.280.07:53:00.40#ibcon#about to write, iclass 18, count 2 2006.280.07:53:00.40#ibcon#wrote, iclass 18, count 2 2006.280.07:53:00.40#ibcon#about to read 3, iclass 18, count 2 2006.280.07:53:00.42#ibcon#read 3, iclass 18, count 2 2006.280.07:53:00.42#ibcon#about to read 4, iclass 18, count 2 2006.280.07:53:00.42#ibcon#read 4, iclass 18, count 2 2006.280.07:53:00.42#ibcon#about to read 5, iclass 18, count 2 2006.280.07:53:00.42#ibcon#read 5, iclass 18, count 2 2006.280.07:53:00.42#ibcon#about to read 6, iclass 18, count 2 2006.280.07:53:00.42#ibcon#read 6, iclass 18, count 2 2006.280.07:53:00.42#ibcon#end of sib2, iclass 18, count 2 2006.280.07:53:00.42#ibcon#*after write, iclass 18, count 2 2006.280.07:53:00.42#ibcon#*before return 0, iclass 18, count 2 2006.280.07:53:00.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:00.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:00.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.07:53:00.42#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:00.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:00.55#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:00.55#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:00.55#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:53:00.55#ibcon#first serial, iclass 18, count 0 2006.280.07:53:00.55#ibcon#enter sib2, iclass 18, count 0 2006.280.07:53:00.55#ibcon#flushed, iclass 18, count 0 2006.280.07:53:00.55#ibcon#about to write, iclass 18, count 0 2006.280.07:53:00.55#ibcon#wrote, iclass 18, count 0 2006.280.07:53:00.55#ibcon#about to read 3, iclass 18, count 0 2006.280.07:53:00.56#ibcon#read 3, iclass 18, count 0 2006.280.07:53:00.56#ibcon#about to read 4, iclass 18, count 0 2006.280.07:53:00.56#ibcon#read 4, iclass 18, count 0 2006.280.07:53:00.56#ibcon#about to read 5, iclass 18, count 0 2006.280.07:53:00.56#ibcon#read 5, iclass 18, count 0 2006.280.07:53:00.56#ibcon#about to read 6, iclass 18, count 0 2006.280.07:53:00.56#ibcon#read 6, iclass 18, count 0 2006.280.07:53:00.56#ibcon#end of sib2, iclass 18, count 0 2006.280.07:53:00.56#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:53:00.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:53:00.56#ibcon#[25=USB\r\n] 2006.280.07:53:00.56#ibcon#*before write, iclass 18, count 0 2006.280.07:53:00.56#ibcon#enter sib2, iclass 18, count 0 2006.280.07:53:00.56#ibcon#flushed, iclass 18, count 0 2006.280.07:53:00.56#ibcon#about to write, iclass 18, count 0 2006.280.07:53:00.56#ibcon#wrote, iclass 18, count 0 2006.280.07:53:00.56#ibcon#about to read 3, iclass 18, count 0 2006.280.07:53:00.59#ibcon#read 3, iclass 18, count 0 2006.280.07:53:00.59#ibcon#about to read 4, iclass 18, count 0 2006.280.07:53:00.59#ibcon#read 4, iclass 18, count 0 2006.280.07:53:00.59#ibcon#about to read 5, iclass 18, count 0 2006.280.07:53:00.59#ibcon#read 5, iclass 18, count 0 2006.280.07:53:00.59#ibcon#about to read 6, iclass 18, count 0 2006.280.07:53:00.59#ibcon#read 6, iclass 18, count 0 2006.280.07:53:00.59#ibcon#end of sib2, iclass 18, count 0 2006.280.07:53:00.59#ibcon#*after write, iclass 18, count 0 2006.280.07:53:00.59#ibcon#*before return 0, iclass 18, count 0 2006.280.07:53:00.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:00.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:00.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:53:00.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:53:00.59$vc4f8/valo=5,652.99 2006.280.07:53:00.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.07:53:00.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.07:53:00.59#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:00.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:00.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:00.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:00.59#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:53:00.59#ibcon#first serial, iclass 20, count 0 2006.280.07:53:00.59#ibcon#enter sib2, iclass 20, count 0 2006.280.07:53:00.59#ibcon#flushed, iclass 20, count 0 2006.280.07:53:00.59#ibcon#about to write, iclass 20, count 0 2006.280.07:53:00.59#ibcon#wrote, iclass 20, count 0 2006.280.07:53:00.59#ibcon#about to read 3, iclass 20, count 0 2006.280.07:53:00.61#ibcon#read 3, iclass 20, count 0 2006.280.07:53:00.61#ibcon#about to read 4, iclass 20, count 0 2006.280.07:53:00.61#ibcon#read 4, iclass 20, count 0 2006.280.07:53:00.61#ibcon#about to read 5, iclass 20, count 0 2006.280.07:53:00.61#ibcon#read 5, iclass 20, count 0 2006.280.07:53:00.61#ibcon#about to read 6, iclass 20, count 0 2006.280.07:53:00.61#ibcon#read 6, iclass 20, count 0 2006.280.07:53:00.61#ibcon#end of sib2, iclass 20, count 0 2006.280.07:53:00.61#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:53:00.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:53:00.63#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:53:00.63#ibcon#*before write, iclass 20, count 0 2006.280.07:53:00.63#ibcon#enter sib2, iclass 20, count 0 2006.280.07:53:00.63#ibcon#flushed, iclass 20, count 0 2006.280.07:53:00.63#ibcon#about to write, iclass 20, count 0 2006.280.07:53:00.63#ibcon#wrote, iclass 20, count 0 2006.280.07:53:00.63#ibcon#about to read 3, iclass 20, count 0 2006.280.07:53:00.67#ibcon#read 3, iclass 20, count 0 2006.280.07:53:00.67#ibcon#about to read 4, iclass 20, count 0 2006.280.07:53:00.67#ibcon#read 4, iclass 20, count 0 2006.280.07:53:00.67#ibcon#about to read 5, iclass 20, count 0 2006.280.07:53:00.67#ibcon#read 5, iclass 20, count 0 2006.280.07:53:00.67#ibcon#about to read 6, iclass 20, count 0 2006.280.07:53:00.67#ibcon#read 6, iclass 20, count 0 2006.280.07:53:00.67#ibcon#end of sib2, iclass 20, count 0 2006.280.07:53:00.67#ibcon#*after write, iclass 20, count 0 2006.280.07:53:00.67#ibcon#*before return 0, iclass 20, count 0 2006.280.07:53:00.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:00.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:00.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:53:00.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:53:00.67$vc4f8/va=5,7 2006.280.07:53:00.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.07:53:00.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.07:53:00.67#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:00.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:00.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:00.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:00.71#ibcon#enter wrdev, iclass 22, count 2 2006.280.07:53:00.71#ibcon#first serial, iclass 22, count 2 2006.280.07:53:00.71#ibcon#enter sib2, iclass 22, count 2 2006.280.07:53:00.71#ibcon#flushed, iclass 22, count 2 2006.280.07:53:00.71#ibcon#about to write, iclass 22, count 2 2006.280.07:53:00.71#ibcon#wrote, iclass 22, count 2 2006.280.07:53:00.71#ibcon#about to read 3, iclass 22, count 2 2006.280.07:53:00.73#ibcon#read 3, iclass 22, count 2 2006.280.07:53:00.73#ibcon#about to read 4, iclass 22, count 2 2006.280.07:53:00.73#ibcon#read 4, iclass 22, count 2 2006.280.07:53:00.73#ibcon#about to read 5, iclass 22, count 2 2006.280.07:53:00.73#ibcon#read 5, iclass 22, count 2 2006.280.07:53:00.73#ibcon#about to read 6, iclass 22, count 2 2006.280.07:53:00.73#ibcon#read 6, iclass 22, count 2 2006.280.07:53:00.73#ibcon#end of sib2, iclass 22, count 2 2006.280.07:53:00.73#ibcon#*mode == 0, iclass 22, count 2 2006.280.07:53:00.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.07:53:00.73#ibcon#[25=AT05-07\r\n] 2006.280.07:53:00.73#ibcon#*before write, iclass 22, count 2 2006.280.07:53:00.73#ibcon#enter sib2, iclass 22, count 2 2006.280.07:53:00.73#ibcon#flushed, iclass 22, count 2 2006.280.07:53:00.73#ibcon#about to write, iclass 22, count 2 2006.280.07:53:00.73#ibcon#wrote, iclass 22, count 2 2006.280.07:53:00.73#ibcon#about to read 3, iclass 22, count 2 2006.280.07:53:00.77#ibcon#read 3, iclass 22, count 2 2006.280.07:53:00.77#ibcon#about to read 4, iclass 22, count 2 2006.280.07:53:00.77#ibcon#read 4, iclass 22, count 2 2006.280.07:53:00.77#ibcon#about to read 5, iclass 22, count 2 2006.280.07:53:00.77#ibcon#read 5, iclass 22, count 2 2006.280.07:53:00.77#ibcon#about to read 6, iclass 22, count 2 2006.280.07:53:00.77#ibcon#read 6, iclass 22, count 2 2006.280.07:53:00.77#ibcon#end of sib2, iclass 22, count 2 2006.280.07:53:00.77#ibcon#*after write, iclass 22, count 2 2006.280.07:53:00.77#ibcon#*before return 0, iclass 22, count 2 2006.280.07:53:00.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:00.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:00.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.07:53:00.77#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:00.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:00.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:00.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:00.89#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:53:00.89#ibcon#first serial, iclass 22, count 0 2006.280.07:53:00.89#ibcon#enter sib2, iclass 22, count 0 2006.280.07:53:00.89#ibcon#flushed, iclass 22, count 0 2006.280.07:53:00.89#ibcon#about to write, iclass 22, count 0 2006.280.07:53:00.89#ibcon#wrote, iclass 22, count 0 2006.280.07:53:00.89#ibcon#about to read 3, iclass 22, count 0 2006.280.07:53:00.90#ibcon#read 3, iclass 22, count 0 2006.280.07:53:00.90#ibcon#about to read 4, iclass 22, count 0 2006.280.07:53:00.90#ibcon#read 4, iclass 22, count 0 2006.280.07:53:00.90#ibcon#about to read 5, iclass 22, count 0 2006.280.07:53:00.90#ibcon#read 5, iclass 22, count 0 2006.280.07:53:00.90#ibcon#about to read 6, iclass 22, count 0 2006.280.07:53:00.90#ibcon#read 6, iclass 22, count 0 2006.280.07:53:00.90#ibcon#end of sib2, iclass 22, count 0 2006.280.07:53:00.90#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:53:00.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:53:00.90#ibcon#[25=USB\r\n] 2006.280.07:53:00.90#ibcon#*before write, iclass 22, count 0 2006.280.07:53:00.90#ibcon#enter sib2, iclass 22, count 0 2006.280.07:53:00.90#ibcon#flushed, iclass 22, count 0 2006.280.07:53:00.90#ibcon#about to write, iclass 22, count 0 2006.280.07:53:00.90#ibcon#wrote, iclass 22, count 0 2006.280.07:53:00.90#ibcon#about to read 3, iclass 22, count 0 2006.280.07:53:00.93#ibcon#read 3, iclass 22, count 0 2006.280.07:53:00.93#ibcon#about to read 4, iclass 22, count 0 2006.280.07:53:00.93#ibcon#read 4, iclass 22, count 0 2006.280.07:53:00.93#ibcon#about to read 5, iclass 22, count 0 2006.280.07:53:00.93#ibcon#read 5, iclass 22, count 0 2006.280.07:53:00.93#ibcon#about to read 6, iclass 22, count 0 2006.280.07:53:00.93#ibcon#read 6, iclass 22, count 0 2006.280.07:53:00.93#ibcon#end of sib2, iclass 22, count 0 2006.280.07:53:00.93#ibcon#*after write, iclass 22, count 0 2006.280.07:53:00.93#ibcon#*before return 0, iclass 22, count 0 2006.280.07:53:00.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:00.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:00.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:53:00.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:53:00.93$vc4f8/valo=6,772.99 2006.280.07:53:00.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.07:53:00.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.07:53:00.93#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:00.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:00.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:00.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:00.93#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:53:00.93#ibcon#first serial, iclass 24, count 0 2006.280.07:53:00.93#ibcon#enter sib2, iclass 24, count 0 2006.280.07:53:00.93#ibcon#flushed, iclass 24, count 0 2006.280.07:53:00.93#ibcon#about to write, iclass 24, count 0 2006.280.07:53:00.93#ibcon#wrote, iclass 24, count 0 2006.280.07:53:00.93#ibcon#about to read 3, iclass 24, count 0 2006.280.07:53:00.95#ibcon#read 3, iclass 24, count 0 2006.280.07:53:00.95#ibcon#about to read 4, iclass 24, count 0 2006.280.07:53:00.95#ibcon#read 4, iclass 24, count 0 2006.280.07:53:00.95#ibcon#about to read 5, iclass 24, count 0 2006.280.07:53:00.95#ibcon#read 5, iclass 24, count 0 2006.280.07:53:00.95#ibcon#about to read 6, iclass 24, count 0 2006.280.07:53:00.95#ibcon#read 6, iclass 24, count 0 2006.280.07:53:00.95#ibcon#end of sib2, iclass 24, count 0 2006.280.07:53:00.95#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:53:00.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:53:00.95#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:53:00.95#ibcon#*before write, iclass 24, count 0 2006.280.07:53:00.95#ibcon#enter sib2, iclass 24, count 0 2006.280.07:53:00.95#ibcon#flushed, iclass 24, count 0 2006.280.07:53:00.95#ibcon#about to write, iclass 24, count 0 2006.280.07:53:00.95#ibcon#wrote, iclass 24, count 0 2006.280.07:53:00.95#ibcon#about to read 3, iclass 24, count 0 2006.280.07:53:00.99#ibcon#read 3, iclass 24, count 0 2006.280.07:53:00.99#ibcon#about to read 4, iclass 24, count 0 2006.280.07:53:00.99#ibcon#read 4, iclass 24, count 0 2006.280.07:53:00.99#ibcon#about to read 5, iclass 24, count 0 2006.280.07:53:00.99#ibcon#read 5, iclass 24, count 0 2006.280.07:53:00.99#ibcon#about to read 6, iclass 24, count 0 2006.280.07:53:00.99#ibcon#read 6, iclass 24, count 0 2006.280.07:53:00.99#ibcon#end of sib2, iclass 24, count 0 2006.280.07:53:00.99#ibcon#*after write, iclass 24, count 0 2006.280.07:53:00.99#ibcon#*before return 0, iclass 24, count 0 2006.280.07:53:00.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:00.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:00.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:53:00.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:53:00.99$vc4f8/va=6,6 2006.280.07:53:00.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.07:53:00.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.07:53:00.99#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:00.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:01.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:01.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:01.05#ibcon#enter wrdev, iclass 26, count 2 2006.280.07:53:01.05#ibcon#first serial, iclass 26, count 2 2006.280.07:53:01.05#ibcon#enter sib2, iclass 26, count 2 2006.280.07:53:01.05#ibcon#flushed, iclass 26, count 2 2006.280.07:53:01.05#ibcon#about to write, iclass 26, count 2 2006.280.07:53:01.05#ibcon#wrote, iclass 26, count 2 2006.280.07:53:01.05#ibcon#about to read 3, iclass 26, count 2 2006.280.07:53:01.07#ibcon#read 3, iclass 26, count 2 2006.280.07:53:01.08#ibcon#about to read 4, iclass 26, count 2 2006.280.07:53:01.08#ibcon#read 4, iclass 26, count 2 2006.280.07:53:01.08#ibcon#about to read 5, iclass 26, count 2 2006.280.07:53:01.08#ibcon#read 5, iclass 26, count 2 2006.280.07:53:01.08#ibcon#about to read 6, iclass 26, count 2 2006.280.07:53:01.08#ibcon#read 6, iclass 26, count 2 2006.280.07:53:01.08#ibcon#end of sib2, iclass 26, count 2 2006.280.07:53:01.08#ibcon#*mode == 0, iclass 26, count 2 2006.280.07:53:01.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.07:53:01.08#ibcon#[25=AT06-06\r\n] 2006.280.07:53:01.08#ibcon#*before write, iclass 26, count 2 2006.280.07:53:01.08#ibcon#enter sib2, iclass 26, count 2 2006.280.07:53:01.08#ibcon#flushed, iclass 26, count 2 2006.280.07:53:01.08#ibcon#about to write, iclass 26, count 2 2006.280.07:53:01.08#ibcon#wrote, iclass 26, count 2 2006.280.07:53:01.08#ibcon#about to read 3, iclass 26, count 2 2006.280.07:53:01.11#ibcon#read 3, iclass 26, count 2 2006.280.07:53:01.11#ibcon#about to read 4, iclass 26, count 2 2006.280.07:53:01.11#ibcon#read 4, iclass 26, count 2 2006.280.07:53:01.11#ibcon#about to read 5, iclass 26, count 2 2006.280.07:53:01.11#ibcon#read 5, iclass 26, count 2 2006.280.07:53:01.11#ibcon#about to read 6, iclass 26, count 2 2006.280.07:53:01.11#ibcon#read 6, iclass 26, count 2 2006.280.07:53:01.11#ibcon#end of sib2, iclass 26, count 2 2006.280.07:53:01.11#ibcon#*after write, iclass 26, count 2 2006.280.07:53:01.11#ibcon#*before return 0, iclass 26, count 2 2006.280.07:53:01.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:01.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:01.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.07:53:01.11#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:01.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:53:01.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:53:01.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:53:01.24#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:53:01.24#ibcon#first serial, iclass 26, count 0 2006.280.07:53:01.24#ibcon#enter sib2, iclass 26, count 0 2006.280.07:53:01.24#ibcon#flushed, iclass 26, count 0 2006.280.07:53:01.24#ibcon#about to write, iclass 26, count 0 2006.280.07:53:01.24#ibcon#wrote, iclass 26, count 0 2006.280.07:53:01.24#ibcon#about to read 3, iclass 26, count 0 2006.280.07:53:01.25#ibcon#read 3, iclass 26, count 0 2006.280.07:53:01.25#ibcon#about to read 4, iclass 26, count 0 2006.280.07:53:01.25#ibcon#read 4, iclass 26, count 0 2006.280.07:53:01.25#ibcon#about to read 5, iclass 26, count 0 2006.280.07:53:01.25#ibcon#read 5, iclass 26, count 0 2006.280.07:53:01.25#ibcon#about to read 6, iclass 26, count 0 2006.280.07:53:01.25#ibcon#read 6, iclass 26, count 0 2006.280.07:53:01.25#ibcon#end of sib2, iclass 26, count 0 2006.280.07:53:01.25#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:53:01.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:53:01.25#ibcon#[25=USB\r\n] 2006.280.07:53:01.25#ibcon#*before write, iclass 26, count 0 2006.280.07:53:01.25#ibcon#enter sib2, iclass 26, count 0 2006.280.07:53:01.25#ibcon#flushed, iclass 26, count 0 2006.280.07:53:01.25#ibcon#about to write, iclass 26, count 0 2006.280.07:53:01.25#ibcon#wrote, iclass 26, count 0 2006.280.07:53:01.25#ibcon#about to read 3, iclass 26, count 0 2006.280.07:53:01.28#ibcon#read 3, iclass 26, count 0 2006.280.07:53:01.28#ibcon#about to read 4, iclass 26, count 0 2006.280.07:53:01.28#ibcon#read 4, iclass 26, count 0 2006.280.07:53:01.28#ibcon#about to read 5, iclass 26, count 0 2006.280.07:53:01.28#ibcon#read 5, iclass 26, count 0 2006.280.07:53:01.28#ibcon#about to read 6, iclass 26, count 0 2006.280.07:53:01.28#ibcon#read 6, iclass 26, count 0 2006.280.07:53:01.28#ibcon#end of sib2, iclass 26, count 0 2006.280.07:53:01.28#ibcon#*after write, iclass 26, count 0 2006.280.07:53:01.28#ibcon#*before return 0, iclass 26, count 0 2006.280.07:53:01.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:53:01.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.07:53:01.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:53:01.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:53:01.28$vc4f8/valo=7,832.99 2006.280.07:53:01.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.07:53:01.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.07:53:01.29#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:01.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:53:01.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:53:01.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:53:01.29#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:53:01.29#ibcon#first serial, iclass 28, count 0 2006.280.07:53:01.29#ibcon#enter sib2, iclass 28, count 0 2006.280.07:53:01.29#ibcon#flushed, iclass 28, count 0 2006.280.07:53:01.29#ibcon#about to write, iclass 28, count 0 2006.280.07:53:01.29#ibcon#wrote, iclass 28, count 0 2006.280.07:53:01.29#ibcon#about to read 3, iclass 28, count 0 2006.280.07:53:01.31#ibcon#read 3, iclass 28, count 0 2006.280.07:53:01.31#ibcon#about to read 4, iclass 28, count 0 2006.280.07:53:01.31#ibcon#read 4, iclass 28, count 0 2006.280.07:53:01.31#ibcon#about to read 5, iclass 28, count 0 2006.280.07:53:01.31#ibcon#read 5, iclass 28, count 0 2006.280.07:53:01.31#ibcon#about to read 6, iclass 28, count 0 2006.280.07:53:01.31#ibcon#read 6, iclass 28, count 0 2006.280.07:53:01.31#ibcon#end of sib2, iclass 28, count 0 2006.280.07:53:01.31#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:53:01.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:53:01.31#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:53:01.31#ibcon#*before write, iclass 28, count 0 2006.280.07:53:01.31#ibcon#enter sib2, iclass 28, count 0 2006.280.07:53:01.31#ibcon#flushed, iclass 28, count 0 2006.280.07:53:01.31#ibcon#about to write, iclass 28, count 0 2006.280.07:53:01.31#ibcon#wrote, iclass 28, count 0 2006.280.07:53:01.31#ibcon#about to read 3, iclass 28, count 0 2006.280.07:53:01.35#ibcon#read 3, iclass 28, count 0 2006.280.07:53:01.35#ibcon#about to read 4, iclass 28, count 0 2006.280.07:53:01.35#ibcon#read 4, iclass 28, count 0 2006.280.07:53:01.35#ibcon#about to read 5, iclass 28, count 0 2006.280.07:53:01.35#ibcon#read 5, iclass 28, count 0 2006.280.07:53:01.35#ibcon#about to read 6, iclass 28, count 0 2006.280.07:53:01.35#ibcon#read 6, iclass 28, count 0 2006.280.07:53:01.35#ibcon#end of sib2, iclass 28, count 0 2006.280.07:53:01.35#ibcon#*after write, iclass 28, count 0 2006.280.07:53:01.35#ibcon#*before return 0, iclass 28, count 0 2006.280.07:53:01.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:53:01.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.07:53:01.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:53:01.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:53:01.35$vc4f8/va=7,6 2006.280.07:53:01.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.07:53:01.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.07:53:01.35#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:01.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:53:01.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:53:01.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:53:01.43#ibcon#enter wrdev, iclass 30, count 2 2006.280.07:53:01.43#ibcon#first serial, iclass 30, count 2 2006.280.07:53:01.43#ibcon#enter sib2, iclass 30, count 2 2006.280.07:53:01.43#ibcon#flushed, iclass 30, count 2 2006.280.07:53:01.43#ibcon#about to write, iclass 30, count 2 2006.280.07:53:01.43#ibcon#wrote, iclass 30, count 2 2006.280.07:53:01.43#ibcon#about to read 3, iclass 30, count 2 2006.280.07:53:01.46#ibcon#read 3, iclass 30, count 2 2006.280.07:53:01.47#ibcon#about to read 4, iclass 30, count 2 2006.280.07:53:01.47#ibcon#read 4, iclass 30, count 2 2006.280.07:53:01.47#ibcon#about to read 5, iclass 30, count 2 2006.280.07:53:01.47#ibcon#read 5, iclass 30, count 2 2006.280.07:53:01.47#ibcon#about to read 6, iclass 30, count 2 2006.280.07:53:01.47#ibcon#read 6, iclass 30, count 2 2006.280.07:53:01.47#ibcon#end of sib2, iclass 30, count 2 2006.280.07:53:01.47#ibcon#*mode == 0, iclass 30, count 2 2006.280.07:53:01.47#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.07:53:01.47#ibcon#[25=AT07-06\r\n] 2006.280.07:53:01.47#ibcon#*before write, iclass 30, count 2 2006.280.07:53:01.47#ibcon#enter sib2, iclass 30, count 2 2006.280.07:53:01.47#ibcon#flushed, iclass 30, count 2 2006.280.07:53:01.47#ibcon#about to write, iclass 30, count 2 2006.280.07:53:01.47#ibcon#wrote, iclass 30, count 2 2006.280.07:53:01.47#ibcon#about to read 3, iclass 30, count 2 2006.280.07:53:01.50#ibcon#read 3, iclass 30, count 2 2006.280.07:53:01.60#ibcon#about to read 4, iclass 30, count 2 2006.280.07:53:01.60#ibcon#read 4, iclass 30, count 2 2006.280.07:53:01.60#ibcon#about to read 5, iclass 30, count 2 2006.280.07:53:01.60#ibcon#read 5, iclass 30, count 2 2006.280.07:53:01.60#ibcon#about to read 6, iclass 30, count 2 2006.280.07:53:01.60#ibcon#read 6, iclass 30, count 2 2006.280.07:53:01.60#ibcon#end of sib2, iclass 30, count 2 2006.280.07:53:01.60#ibcon#*after write, iclass 30, count 2 2006.280.07:53:01.60#ibcon#*before return 0, iclass 30, count 2 2006.280.07:53:01.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:53:01.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.07:53:01.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.07:53:01.60#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:01.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:53:01.71#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:53:01.71#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:53:01.71#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:53:01.71#ibcon#first serial, iclass 30, count 0 2006.280.07:53:01.71#ibcon#enter sib2, iclass 30, count 0 2006.280.07:53:01.71#ibcon#flushed, iclass 30, count 0 2006.280.07:53:01.71#ibcon#about to write, iclass 30, count 0 2006.280.07:53:01.71#ibcon#wrote, iclass 30, count 0 2006.280.07:53:01.71#ibcon#about to read 3, iclass 30, count 0 2006.280.07:53:01.73#ibcon#read 3, iclass 30, count 0 2006.280.07:53:01.73#ibcon#about to read 4, iclass 30, count 0 2006.280.07:53:01.73#ibcon#read 4, iclass 30, count 0 2006.280.07:53:01.73#ibcon#about to read 5, iclass 30, count 0 2006.280.07:53:01.73#ibcon#read 5, iclass 30, count 0 2006.280.07:53:01.73#ibcon#about to read 6, iclass 30, count 0 2006.280.07:53:01.73#ibcon#read 6, iclass 30, count 0 2006.280.07:53:01.73#ibcon#end of sib2, iclass 30, count 0 2006.280.07:53:01.73#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:53:01.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:53:01.73#ibcon#[25=USB\r\n] 2006.280.07:53:01.73#ibcon#*before write, iclass 30, count 0 2006.280.07:53:01.73#ibcon#enter sib2, iclass 30, count 0 2006.280.07:53:01.73#ibcon#flushed, iclass 30, count 0 2006.280.07:53:01.73#ibcon#about to write, iclass 30, count 0 2006.280.07:53:01.73#ibcon#wrote, iclass 30, count 0 2006.280.07:53:01.73#ibcon#about to read 3, iclass 30, count 0 2006.280.07:53:01.76#ibcon#read 3, iclass 30, count 0 2006.280.07:53:01.76#ibcon#about to read 4, iclass 30, count 0 2006.280.07:53:01.76#ibcon#read 4, iclass 30, count 0 2006.280.07:53:01.76#ibcon#about to read 5, iclass 30, count 0 2006.280.07:53:01.76#ibcon#read 5, iclass 30, count 0 2006.280.07:53:01.76#ibcon#about to read 6, iclass 30, count 0 2006.280.07:53:01.76#ibcon#read 6, iclass 30, count 0 2006.280.07:53:01.76#ibcon#end of sib2, iclass 30, count 0 2006.280.07:53:01.76#ibcon#*after write, iclass 30, count 0 2006.280.07:53:01.76#ibcon#*before return 0, iclass 30, count 0 2006.280.07:53:01.76#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:53:01.76#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.07:53:01.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:53:01.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:53:01.76$vc4f8/valo=8,852.99 2006.280.07:53:01.76#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.07:53:01.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.07:53:01.82#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:01.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:53:01.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:53:01.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:53:01.82#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:53:01.82#ibcon#first serial, iclass 32, count 0 2006.280.07:53:01.82#ibcon#enter sib2, iclass 32, count 0 2006.280.07:53:01.82#ibcon#flushed, iclass 32, count 0 2006.280.07:53:01.82#ibcon#about to write, iclass 32, count 0 2006.280.07:53:01.82#ibcon#wrote, iclass 32, count 0 2006.280.07:53:01.82#ibcon#about to read 3, iclass 32, count 0 2006.280.07:53:01.83#ibcon#read 3, iclass 32, count 0 2006.280.07:53:01.83#ibcon#about to read 4, iclass 32, count 0 2006.280.07:53:01.83#ibcon#read 4, iclass 32, count 0 2006.280.07:53:01.83#ibcon#about to read 5, iclass 32, count 0 2006.280.07:53:01.83#ibcon#read 5, iclass 32, count 0 2006.280.07:53:01.83#ibcon#about to read 6, iclass 32, count 0 2006.280.07:53:01.83#ibcon#read 6, iclass 32, count 0 2006.280.07:53:01.84#ibcon#end of sib2, iclass 32, count 0 2006.280.07:53:01.84#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:53:01.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:53:01.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:53:01.84#ibcon#*before write, iclass 32, count 0 2006.280.07:53:01.84#ibcon#enter sib2, iclass 32, count 0 2006.280.07:53:01.84#ibcon#flushed, iclass 32, count 0 2006.280.07:53:01.84#ibcon#about to write, iclass 32, count 0 2006.280.07:53:01.84#ibcon#wrote, iclass 32, count 0 2006.280.07:53:01.84#ibcon#about to read 3, iclass 32, count 0 2006.280.07:53:01.87#ibcon#read 3, iclass 32, count 0 2006.280.07:53:01.87#ibcon#about to read 4, iclass 32, count 0 2006.280.07:53:01.87#ibcon#read 4, iclass 32, count 0 2006.280.07:53:01.87#ibcon#about to read 5, iclass 32, count 0 2006.280.07:53:01.87#ibcon#read 5, iclass 32, count 0 2006.280.07:53:01.87#ibcon#about to read 6, iclass 32, count 0 2006.280.07:53:01.87#ibcon#read 6, iclass 32, count 0 2006.280.07:53:01.87#ibcon#end of sib2, iclass 32, count 0 2006.280.07:53:01.87#ibcon#*after write, iclass 32, count 0 2006.280.07:53:01.87#ibcon#*before return 0, iclass 32, count 0 2006.280.07:53:01.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:53:01.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.07:53:01.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:53:01.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:53:01.87$vc4f8/va=8,6 2006.280.07:53:01.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.07:53:01.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.07:53:01.87#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:01.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:53:01.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:53:01.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:53:01.87#ibcon#enter wrdev, iclass 34, count 2 2006.280.07:53:01.87#ibcon#first serial, iclass 34, count 2 2006.280.07:53:01.87#ibcon#enter sib2, iclass 34, count 2 2006.280.07:53:01.87#ibcon#flushed, iclass 34, count 2 2006.280.07:53:01.92#ibcon#about to write, iclass 34, count 2 2006.280.07:53:01.92#ibcon#wrote, iclass 34, count 2 2006.280.07:53:01.92#ibcon#about to read 3, iclass 34, count 2 2006.280.07:53:01.93#ibcon#read 3, iclass 34, count 2 2006.280.07:53:01.94#ibcon#about to read 4, iclass 34, count 2 2006.280.07:53:01.94#ibcon#read 4, iclass 34, count 2 2006.280.07:53:01.94#ibcon#about to read 5, iclass 34, count 2 2006.280.07:53:01.94#ibcon#read 5, iclass 34, count 2 2006.280.07:53:01.94#ibcon#about to read 6, iclass 34, count 2 2006.280.07:53:01.94#ibcon#read 6, iclass 34, count 2 2006.280.07:53:01.94#ibcon#end of sib2, iclass 34, count 2 2006.280.07:53:01.94#ibcon#*mode == 0, iclass 34, count 2 2006.280.07:53:01.94#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.07:53:01.94#ibcon#[25=AT08-06\r\n] 2006.280.07:53:01.94#ibcon#*before write, iclass 34, count 2 2006.280.07:53:01.94#ibcon#enter sib2, iclass 34, count 2 2006.280.07:53:01.94#ibcon#flushed, iclass 34, count 2 2006.280.07:53:01.94#ibcon#about to write, iclass 34, count 2 2006.280.07:53:01.94#ibcon#wrote, iclass 34, count 2 2006.280.07:53:01.94#ibcon#about to read 3, iclass 34, count 2 2006.280.07:53:01.97#ibcon#read 3, iclass 34, count 2 2006.280.07:53:01.97#ibcon#about to read 4, iclass 34, count 2 2006.280.07:53:01.97#ibcon#read 4, iclass 34, count 2 2006.280.07:53:01.97#ibcon#about to read 5, iclass 34, count 2 2006.280.07:53:01.97#ibcon#read 5, iclass 34, count 2 2006.280.07:53:01.97#ibcon#about to read 6, iclass 34, count 2 2006.280.07:53:01.97#ibcon#read 6, iclass 34, count 2 2006.280.07:53:01.97#ibcon#end of sib2, iclass 34, count 2 2006.280.07:53:01.97#ibcon#*after write, iclass 34, count 2 2006.280.07:53:01.97#ibcon#*before return 0, iclass 34, count 2 2006.280.07:53:01.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:53:01.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.07:53:01.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.07:53:01.97#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:01.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:53:02.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:53:02.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:53:02.09#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:53:02.09#ibcon#first serial, iclass 34, count 0 2006.280.07:53:02.09#ibcon#enter sib2, iclass 34, count 0 2006.280.07:53:02.09#ibcon#flushed, iclass 34, count 0 2006.280.07:53:02.09#ibcon#about to write, iclass 34, count 0 2006.280.07:53:02.09#ibcon#wrote, iclass 34, count 0 2006.280.07:53:02.09#ibcon#about to read 3, iclass 34, count 0 2006.280.07:53:02.11#ibcon#read 3, iclass 34, count 0 2006.280.07:53:02.11#ibcon#about to read 4, iclass 34, count 0 2006.280.07:53:02.11#ibcon#read 4, iclass 34, count 0 2006.280.07:53:02.11#ibcon#about to read 5, iclass 34, count 0 2006.280.07:53:02.11#ibcon#read 5, iclass 34, count 0 2006.280.07:53:02.11#ibcon#about to read 6, iclass 34, count 0 2006.280.07:53:02.11#ibcon#read 6, iclass 34, count 0 2006.280.07:53:02.11#ibcon#end of sib2, iclass 34, count 0 2006.280.07:53:02.11#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:53:02.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:53:02.11#ibcon#[25=USB\r\n] 2006.280.07:53:02.11#ibcon#*before write, iclass 34, count 0 2006.280.07:53:02.11#ibcon#enter sib2, iclass 34, count 0 2006.280.07:53:02.11#ibcon#flushed, iclass 34, count 0 2006.280.07:53:02.11#ibcon#about to write, iclass 34, count 0 2006.280.07:53:02.11#ibcon#wrote, iclass 34, count 0 2006.280.07:53:02.11#ibcon#about to read 3, iclass 34, count 0 2006.280.07:53:02.14#ibcon#read 3, iclass 34, count 0 2006.280.07:53:02.14#ibcon#about to read 4, iclass 34, count 0 2006.280.07:53:02.14#ibcon#read 4, iclass 34, count 0 2006.280.07:53:02.14#ibcon#about to read 5, iclass 34, count 0 2006.280.07:53:02.14#ibcon#read 5, iclass 34, count 0 2006.280.07:53:02.14#ibcon#about to read 6, iclass 34, count 0 2006.280.07:53:02.14#ibcon#read 6, iclass 34, count 0 2006.280.07:53:02.14#ibcon#end of sib2, iclass 34, count 0 2006.280.07:53:02.14#ibcon#*after write, iclass 34, count 0 2006.280.07:53:02.14#ibcon#*before return 0, iclass 34, count 0 2006.280.07:53:02.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:53:02.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.07:53:02.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:53:02.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:53:02.14$vc4f8/vblo=1,632.99 2006.280.07:53:02.14#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.07:53:02.14#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.07:53:02.14#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:02.14#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:53:02.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:53:02.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:53:02.14#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:53:02.14#ibcon#first serial, iclass 36, count 0 2006.280.07:53:02.14#ibcon#enter sib2, iclass 36, count 0 2006.280.07:53:02.14#ibcon#flushed, iclass 36, count 0 2006.280.07:53:02.14#ibcon#about to write, iclass 36, count 0 2006.280.07:53:02.14#ibcon#wrote, iclass 36, count 0 2006.280.07:53:02.14#ibcon#about to read 3, iclass 36, count 0 2006.280.07:53:02.16#ibcon#read 3, iclass 36, count 0 2006.280.07:53:02.16#ibcon#about to read 4, iclass 36, count 0 2006.280.07:53:02.16#ibcon#read 4, iclass 36, count 0 2006.280.07:53:02.16#ibcon#about to read 5, iclass 36, count 0 2006.280.07:53:02.16#ibcon#read 5, iclass 36, count 0 2006.280.07:53:02.16#ibcon#about to read 6, iclass 36, count 0 2006.280.07:53:02.16#ibcon#read 6, iclass 36, count 0 2006.280.07:53:02.16#ibcon#end of sib2, iclass 36, count 0 2006.280.07:53:02.16#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:53:02.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:53:02.16#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:53:02.16#ibcon#*before write, iclass 36, count 0 2006.280.07:53:02.16#ibcon#enter sib2, iclass 36, count 0 2006.280.07:53:02.16#ibcon#flushed, iclass 36, count 0 2006.280.07:53:02.16#ibcon#about to write, iclass 36, count 0 2006.280.07:53:02.16#ibcon#wrote, iclass 36, count 0 2006.280.07:53:02.16#ibcon#about to read 3, iclass 36, count 0 2006.280.07:53:02.20#ibcon#read 3, iclass 36, count 0 2006.280.07:53:02.20#ibcon#about to read 4, iclass 36, count 0 2006.280.07:53:02.20#ibcon#read 4, iclass 36, count 0 2006.280.07:53:02.20#ibcon#about to read 5, iclass 36, count 0 2006.280.07:53:02.20#ibcon#read 5, iclass 36, count 0 2006.280.07:53:02.20#ibcon#about to read 6, iclass 36, count 0 2006.280.07:53:02.20#ibcon#read 6, iclass 36, count 0 2006.280.07:53:02.20#ibcon#end of sib2, iclass 36, count 0 2006.280.07:53:02.20#ibcon#*after write, iclass 36, count 0 2006.280.07:53:02.20#ibcon#*before return 0, iclass 36, count 0 2006.280.07:53:02.20#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:53:02.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.07:53:02.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:53:02.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:53:02.20$vc4f8/vb=1,4 2006.280.07:53:02.20#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.07:53:02.20#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.07:53:02.20#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:02.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:53:02.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:53:02.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:53:02.20#ibcon#enter wrdev, iclass 38, count 2 2006.280.07:53:02.20#ibcon#first serial, iclass 38, count 2 2006.280.07:53:02.20#ibcon#enter sib2, iclass 38, count 2 2006.280.07:53:02.20#ibcon#flushed, iclass 38, count 2 2006.280.07:53:02.20#ibcon#about to write, iclass 38, count 2 2006.280.07:53:02.20#ibcon#wrote, iclass 38, count 2 2006.280.07:53:02.20#ibcon#about to read 3, iclass 38, count 2 2006.280.07:53:02.23#ibcon#read 3, iclass 38, count 2 2006.280.07:53:02.25#ibcon#about to read 4, iclass 38, count 2 2006.280.07:53:02.25#ibcon#read 4, iclass 38, count 2 2006.280.07:53:02.25#ibcon#about to read 5, iclass 38, count 2 2006.280.07:53:02.25#ibcon#read 5, iclass 38, count 2 2006.280.07:53:02.25#ibcon#about to read 6, iclass 38, count 2 2006.280.07:53:02.25#ibcon#read 6, iclass 38, count 2 2006.280.07:53:02.25#ibcon#end of sib2, iclass 38, count 2 2006.280.07:53:02.25#ibcon#*mode == 0, iclass 38, count 2 2006.280.07:53:02.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.07:53:02.25#ibcon#[27=AT01-04\r\n] 2006.280.07:53:02.25#ibcon#*before write, iclass 38, count 2 2006.280.07:53:02.25#ibcon#enter sib2, iclass 38, count 2 2006.280.07:53:02.25#ibcon#flushed, iclass 38, count 2 2006.280.07:53:02.25#ibcon#about to write, iclass 38, count 2 2006.280.07:53:02.25#ibcon#wrote, iclass 38, count 2 2006.280.07:53:02.25#ibcon#about to read 3, iclass 38, count 2 2006.280.07:53:02.28#ibcon#read 3, iclass 38, count 2 2006.280.07:53:02.28#ibcon#about to read 4, iclass 38, count 2 2006.280.07:53:02.28#ibcon#read 4, iclass 38, count 2 2006.280.07:53:02.28#ibcon#about to read 5, iclass 38, count 2 2006.280.07:53:02.28#ibcon#read 5, iclass 38, count 2 2006.280.07:53:02.28#ibcon#about to read 6, iclass 38, count 2 2006.280.07:53:02.28#ibcon#read 6, iclass 38, count 2 2006.280.07:53:02.28#ibcon#end of sib2, iclass 38, count 2 2006.280.07:53:02.28#ibcon#*after write, iclass 38, count 2 2006.280.07:53:02.28#ibcon#*before return 0, iclass 38, count 2 2006.280.07:53:02.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:53:02.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.07:53:02.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.07:53:02.28#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:02.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:53:02.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:53:02.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:53:02.40#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:53:02.40#ibcon#first serial, iclass 38, count 0 2006.280.07:53:02.40#ibcon#enter sib2, iclass 38, count 0 2006.280.07:53:02.40#ibcon#flushed, iclass 38, count 0 2006.280.07:53:02.40#ibcon#about to write, iclass 38, count 0 2006.280.07:53:02.40#ibcon#wrote, iclass 38, count 0 2006.280.07:53:02.40#ibcon#about to read 3, iclass 38, count 0 2006.280.07:53:02.42#ibcon#read 3, iclass 38, count 0 2006.280.07:53:02.42#ibcon#about to read 4, iclass 38, count 0 2006.280.07:53:02.42#ibcon#read 4, iclass 38, count 0 2006.280.07:53:02.42#ibcon#about to read 5, iclass 38, count 0 2006.280.07:53:02.42#ibcon#read 5, iclass 38, count 0 2006.280.07:53:02.42#ibcon#about to read 6, iclass 38, count 0 2006.280.07:53:02.42#ibcon#read 6, iclass 38, count 0 2006.280.07:53:02.42#ibcon#end of sib2, iclass 38, count 0 2006.280.07:53:02.42#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:53:02.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:53:02.42#ibcon#[27=USB\r\n] 2006.280.07:53:02.42#ibcon#*before write, iclass 38, count 0 2006.280.07:53:02.42#ibcon#enter sib2, iclass 38, count 0 2006.280.07:53:02.42#ibcon#flushed, iclass 38, count 0 2006.280.07:53:02.42#ibcon#about to write, iclass 38, count 0 2006.280.07:53:02.42#ibcon#wrote, iclass 38, count 0 2006.280.07:53:02.42#ibcon#about to read 3, iclass 38, count 0 2006.280.07:53:02.45#ibcon#read 3, iclass 38, count 0 2006.280.07:53:02.45#ibcon#about to read 4, iclass 38, count 0 2006.280.07:53:02.45#ibcon#read 4, iclass 38, count 0 2006.280.07:53:02.45#ibcon#about to read 5, iclass 38, count 0 2006.280.07:53:02.45#ibcon#read 5, iclass 38, count 0 2006.280.07:53:02.45#ibcon#about to read 6, iclass 38, count 0 2006.280.07:53:02.45#ibcon#read 6, iclass 38, count 0 2006.280.07:53:02.45#ibcon#end of sib2, iclass 38, count 0 2006.280.07:53:02.45#ibcon#*after write, iclass 38, count 0 2006.280.07:53:02.45#ibcon#*before return 0, iclass 38, count 0 2006.280.07:53:02.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:53:02.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.07:53:02.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:53:02.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:53:02.45$vc4f8/vblo=2,640.99 2006.280.07:53:02.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.07:53:02.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.07:53:02.46#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:02.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:53:02.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:53:02.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:53:02.47#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:53:02.47#ibcon#first serial, iclass 40, count 0 2006.280.07:53:02.47#ibcon#enter sib2, iclass 40, count 0 2006.280.07:53:02.47#ibcon#flushed, iclass 40, count 0 2006.280.07:53:02.47#ibcon#about to write, iclass 40, count 0 2006.280.07:53:02.47#ibcon#wrote, iclass 40, count 0 2006.280.07:53:02.47#ibcon#about to read 3, iclass 40, count 0 2006.280.07:53:02.48#ibcon#read 3, iclass 40, count 0 2006.280.07:53:02.48#ibcon#about to read 4, iclass 40, count 0 2006.280.07:53:02.48#ibcon#read 4, iclass 40, count 0 2006.280.07:53:02.48#ibcon#about to read 5, iclass 40, count 0 2006.280.07:53:02.48#ibcon#read 5, iclass 40, count 0 2006.280.07:53:02.48#ibcon#about to read 6, iclass 40, count 0 2006.280.07:53:02.48#ibcon#read 6, iclass 40, count 0 2006.280.07:53:02.48#ibcon#end of sib2, iclass 40, count 0 2006.280.07:53:02.48#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:53:02.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:53:02.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:53:02.48#ibcon#*before write, iclass 40, count 0 2006.280.07:53:02.48#ibcon#enter sib2, iclass 40, count 0 2006.280.07:53:02.48#ibcon#flushed, iclass 40, count 0 2006.280.07:53:02.48#ibcon#about to write, iclass 40, count 0 2006.280.07:53:02.48#ibcon#wrote, iclass 40, count 0 2006.280.07:53:02.48#ibcon#about to read 3, iclass 40, count 0 2006.280.07:53:02.52#ibcon#read 3, iclass 40, count 0 2006.280.07:53:02.52#ibcon#about to read 4, iclass 40, count 0 2006.280.07:53:02.52#ibcon#read 4, iclass 40, count 0 2006.280.07:53:02.52#ibcon#about to read 5, iclass 40, count 0 2006.280.07:53:02.52#ibcon#read 5, iclass 40, count 0 2006.280.07:53:02.52#ibcon#about to read 6, iclass 40, count 0 2006.280.07:53:02.52#ibcon#read 6, iclass 40, count 0 2006.280.07:53:02.52#ibcon#end of sib2, iclass 40, count 0 2006.280.07:53:02.52#ibcon#*after write, iclass 40, count 0 2006.280.07:53:02.52#ibcon#*before return 0, iclass 40, count 0 2006.280.07:53:02.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:53:02.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.07:53:02.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:53:02.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:53:02.52$vc4f8/vb=2,5 2006.280.07:53:02.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.07:53:02.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.07:53:02.52#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:02.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:53:02.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:53:02.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:53:02.59#ibcon#enter wrdev, iclass 4, count 2 2006.280.07:53:02.59#ibcon#first serial, iclass 4, count 2 2006.280.07:53:02.59#ibcon#enter sib2, iclass 4, count 2 2006.280.07:53:02.59#ibcon#flushed, iclass 4, count 2 2006.280.07:53:02.59#ibcon#about to write, iclass 4, count 2 2006.280.07:53:02.59#ibcon#wrote, iclass 4, count 2 2006.280.07:53:02.59#ibcon#about to read 3, iclass 4, count 2 2006.280.07:53:02.61#ibcon#read 3, iclass 4, count 2 2006.280.07:53:02.61#ibcon#about to read 4, iclass 4, count 2 2006.280.07:53:02.62#ibcon#read 4, iclass 4, count 2 2006.280.07:53:02.62#ibcon#about to read 5, iclass 4, count 2 2006.280.07:53:02.62#ibcon#read 5, iclass 4, count 2 2006.280.07:53:02.62#ibcon#about to read 6, iclass 4, count 2 2006.280.07:53:02.62#ibcon#read 6, iclass 4, count 2 2006.280.07:53:02.62#ibcon#end of sib2, iclass 4, count 2 2006.280.07:53:02.62#ibcon#*mode == 0, iclass 4, count 2 2006.280.07:53:02.62#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.07:53:02.62#ibcon#[27=AT02-05\r\n] 2006.280.07:53:02.62#ibcon#*before write, iclass 4, count 2 2006.280.07:53:02.62#ibcon#enter sib2, iclass 4, count 2 2006.280.07:53:02.62#ibcon#flushed, iclass 4, count 2 2006.280.07:53:02.62#ibcon#about to write, iclass 4, count 2 2006.280.07:53:02.62#ibcon#wrote, iclass 4, count 2 2006.280.07:53:02.62#ibcon#about to read 3, iclass 4, count 2 2006.280.07:53:02.64#ibcon#read 3, iclass 4, count 2 2006.280.07:53:02.64#ibcon#about to read 4, iclass 4, count 2 2006.280.07:53:02.64#ibcon#read 4, iclass 4, count 2 2006.280.07:53:02.64#ibcon#about to read 5, iclass 4, count 2 2006.280.07:53:02.64#ibcon#read 5, iclass 4, count 2 2006.280.07:53:02.64#ibcon#about to read 6, iclass 4, count 2 2006.280.07:53:02.64#ibcon#read 6, iclass 4, count 2 2006.280.07:53:02.64#ibcon#end of sib2, iclass 4, count 2 2006.280.07:53:02.64#ibcon#*after write, iclass 4, count 2 2006.280.07:53:02.64#ibcon#*before return 0, iclass 4, count 2 2006.280.07:53:02.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:53:02.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.07:53:02.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.07:53:02.64#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:02.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:53:02.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:53:02.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:53:02.76#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:53:02.76#ibcon#first serial, iclass 4, count 0 2006.280.07:53:02.76#ibcon#enter sib2, iclass 4, count 0 2006.280.07:53:02.76#ibcon#flushed, iclass 4, count 0 2006.280.07:53:02.76#ibcon#about to write, iclass 4, count 0 2006.280.07:53:02.76#ibcon#wrote, iclass 4, count 0 2006.280.07:53:02.76#ibcon#about to read 3, iclass 4, count 0 2006.280.07:53:02.79#ibcon#read 3, iclass 4, count 0 2006.280.07:53:02.79#ibcon#about to read 4, iclass 4, count 0 2006.280.07:53:02.79#ibcon#read 4, iclass 4, count 0 2006.280.07:53:02.79#ibcon#about to read 5, iclass 4, count 0 2006.280.07:53:02.79#ibcon#read 5, iclass 4, count 0 2006.280.07:53:02.79#ibcon#about to read 6, iclass 4, count 0 2006.280.07:53:02.79#ibcon#read 6, iclass 4, count 0 2006.280.07:53:02.79#ibcon#end of sib2, iclass 4, count 0 2006.280.07:53:02.79#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:53:02.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:53:02.79#ibcon#[27=USB\r\n] 2006.280.07:53:02.79#ibcon#*before write, iclass 4, count 0 2006.280.07:53:02.79#ibcon#enter sib2, iclass 4, count 0 2006.280.07:53:02.79#ibcon#flushed, iclass 4, count 0 2006.280.07:53:02.79#ibcon#about to write, iclass 4, count 0 2006.280.07:53:02.79#ibcon#wrote, iclass 4, count 0 2006.280.07:53:02.79#ibcon#about to read 3, iclass 4, count 0 2006.280.07:53:02.81#ibcon#read 3, iclass 4, count 0 2006.280.07:53:02.81#ibcon#about to read 4, iclass 4, count 0 2006.280.07:53:02.81#ibcon#read 4, iclass 4, count 0 2006.280.07:53:02.81#ibcon#about to read 5, iclass 4, count 0 2006.280.07:53:02.81#ibcon#read 5, iclass 4, count 0 2006.280.07:53:02.81#ibcon#about to read 6, iclass 4, count 0 2006.280.07:53:02.81#ibcon#read 6, iclass 4, count 0 2006.280.07:53:02.81#ibcon#end of sib2, iclass 4, count 0 2006.280.07:53:02.81#ibcon#*after write, iclass 4, count 0 2006.280.07:53:02.81#ibcon#*before return 0, iclass 4, count 0 2006.280.07:53:02.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:53:02.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.07:53:02.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:53:02.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:53:02.81$vc4f8/vblo=3,656.99 2006.280.07:53:02.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.07:53:02.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.07:53:02.85#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:02.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:53:02.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:53:02.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:53:02.85#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:53:02.85#ibcon#first serial, iclass 6, count 0 2006.280.07:53:02.85#ibcon#enter sib2, iclass 6, count 0 2006.280.07:53:02.85#ibcon#flushed, iclass 6, count 0 2006.280.07:53:02.85#ibcon#about to write, iclass 6, count 0 2006.280.07:53:02.85#ibcon#wrote, iclass 6, count 0 2006.280.07:53:02.85#ibcon#about to read 3, iclass 6, count 0 2006.280.07:53:02.86#ibcon#read 3, iclass 6, count 0 2006.280.07:53:02.86#ibcon#about to read 4, iclass 6, count 0 2006.280.07:53:02.86#ibcon#read 4, iclass 6, count 0 2006.280.07:53:02.86#ibcon#about to read 5, iclass 6, count 0 2006.280.07:53:02.86#ibcon#read 5, iclass 6, count 0 2006.280.07:53:02.86#ibcon#about to read 6, iclass 6, count 0 2006.280.07:53:02.86#ibcon#read 6, iclass 6, count 0 2006.280.07:53:02.86#ibcon#end of sib2, iclass 6, count 0 2006.280.07:53:02.86#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:53:02.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:53:02.86#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:53:02.86#ibcon#*before write, iclass 6, count 0 2006.280.07:53:02.86#ibcon#enter sib2, iclass 6, count 0 2006.280.07:53:02.86#ibcon#flushed, iclass 6, count 0 2006.280.07:53:02.86#ibcon#about to write, iclass 6, count 0 2006.280.07:53:02.86#ibcon#wrote, iclass 6, count 0 2006.280.07:53:02.86#ibcon#about to read 3, iclass 6, count 0 2006.280.07:53:02.90#ibcon#read 3, iclass 6, count 0 2006.280.07:53:02.90#ibcon#about to read 4, iclass 6, count 0 2006.280.07:53:02.90#ibcon#read 4, iclass 6, count 0 2006.280.07:53:02.90#ibcon#about to read 5, iclass 6, count 0 2006.280.07:53:02.90#ibcon#read 5, iclass 6, count 0 2006.280.07:53:02.90#ibcon#about to read 6, iclass 6, count 0 2006.280.07:53:02.90#ibcon#read 6, iclass 6, count 0 2006.280.07:53:02.90#ibcon#end of sib2, iclass 6, count 0 2006.280.07:53:02.90#ibcon#*after write, iclass 6, count 0 2006.280.07:53:02.90#ibcon#*before return 0, iclass 6, count 0 2006.280.07:53:02.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:53:02.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.07:53:02.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:53:02.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:53:02.90$vc4f8/vb=3,4 2006.280.07:53:02.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.07:53:02.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.07:53:02.90#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:02.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:53:02.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:53:02.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:53:02.93#ibcon#enter wrdev, iclass 10, count 2 2006.280.07:53:02.93#ibcon#first serial, iclass 10, count 2 2006.280.07:53:02.93#ibcon#enter sib2, iclass 10, count 2 2006.280.07:53:02.93#ibcon#flushed, iclass 10, count 2 2006.280.07:53:02.93#ibcon#about to write, iclass 10, count 2 2006.280.07:53:02.93#ibcon#wrote, iclass 10, count 2 2006.280.07:53:02.93#ibcon#about to read 3, iclass 10, count 2 2006.280.07:53:02.95#ibcon#read 3, iclass 10, count 2 2006.280.07:53:02.95#ibcon#about to read 4, iclass 10, count 2 2006.280.07:53:02.95#ibcon#read 4, iclass 10, count 2 2006.280.07:53:02.95#ibcon#about to read 5, iclass 10, count 2 2006.280.07:53:02.95#ibcon#read 5, iclass 10, count 2 2006.280.07:53:02.95#ibcon#about to read 6, iclass 10, count 2 2006.280.07:53:02.95#ibcon#read 6, iclass 10, count 2 2006.280.07:53:02.95#ibcon#end of sib2, iclass 10, count 2 2006.280.07:53:02.95#ibcon#*mode == 0, iclass 10, count 2 2006.280.07:53:02.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.07:53:02.95#ibcon#[27=AT03-04\r\n] 2006.280.07:53:02.95#ibcon#*before write, iclass 10, count 2 2006.280.07:53:02.95#ibcon#enter sib2, iclass 10, count 2 2006.280.07:53:02.95#ibcon#flushed, iclass 10, count 2 2006.280.07:53:02.95#ibcon#about to write, iclass 10, count 2 2006.280.07:53:02.95#ibcon#wrote, iclass 10, count 2 2006.280.07:53:02.95#ibcon#about to read 3, iclass 10, count 2 2006.280.07:53:02.98#ibcon#read 3, iclass 10, count 2 2006.280.07:53:02.98#ibcon#about to read 4, iclass 10, count 2 2006.280.07:53:02.98#ibcon#read 4, iclass 10, count 2 2006.280.07:53:02.98#ibcon#about to read 5, iclass 10, count 2 2006.280.07:53:02.98#ibcon#read 5, iclass 10, count 2 2006.280.07:53:02.98#ibcon#about to read 6, iclass 10, count 2 2006.280.07:53:02.98#ibcon#read 6, iclass 10, count 2 2006.280.07:53:02.98#ibcon#end of sib2, iclass 10, count 2 2006.280.07:53:02.98#ibcon#*after write, iclass 10, count 2 2006.280.07:53:02.98#ibcon#*before return 0, iclass 10, count 2 2006.280.07:53:02.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:53:02.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.07:53:02.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.07:53:02.98#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:02.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:53:03.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:53:03.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:53:03.10#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:53:03.10#ibcon#first serial, iclass 10, count 0 2006.280.07:53:03.10#ibcon#enter sib2, iclass 10, count 0 2006.280.07:53:03.10#ibcon#flushed, iclass 10, count 0 2006.280.07:53:03.10#ibcon#about to write, iclass 10, count 0 2006.280.07:53:03.10#ibcon#wrote, iclass 10, count 0 2006.280.07:53:03.10#ibcon#about to read 3, iclass 10, count 0 2006.280.07:53:03.12#ibcon#read 3, iclass 10, count 0 2006.280.07:53:03.12#ibcon#about to read 4, iclass 10, count 0 2006.280.07:53:03.12#ibcon#read 4, iclass 10, count 0 2006.280.07:53:03.12#ibcon#about to read 5, iclass 10, count 0 2006.280.07:53:03.12#ibcon#read 5, iclass 10, count 0 2006.280.07:53:03.12#ibcon#about to read 6, iclass 10, count 0 2006.280.07:53:03.12#ibcon#read 6, iclass 10, count 0 2006.280.07:53:03.12#ibcon#end of sib2, iclass 10, count 0 2006.280.07:53:03.12#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:53:03.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:53:03.12#ibcon#[27=USB\r\n] 2006.280.07:53:03.12#ibcon#*before write, iclass 10, count 0 2006.280.07:53:03.12#ibcon#enter sib2, iclass 10, count 0 2006.280.07:53:03.12#ibcon#flushed, iclass 10, count 0 2006.280.07:53:03.12#ibcon#about to write, iclass 10, count 0 2006.280.07:53:03.12#ibcon#wrote, iclass 10, count 0 2006.280.07:53:03.12#ibcon#about to read 3, iclass 10, count 0 2006.280.07:53:03.15#ibcon#read 3, iclass 10, count 0 2006.280.07:53:03.15#ibcon#about to read 4, iclass 10, count 0 2006.280.07:53:03.15#ibcon#read 4, iclass 10, count 0 2006.280.07:53:03.15#ibcon#about to read 5, iclass 10, count 0 2006.280.07:53:03.15#ibcon#read 5, iclass 10, count 0 2006.280.07:53:03.15#ibcon#about to read 6, iclass 10, count 0 2006.280.07:53:03.15#ibcon#read 6, iclass 10, count 0 2006.280.07:53:03.15#ibcon#end of sib2, iclass 10, count 0 2006.280.07:53:03.15#ibcon#*after write, iclass 10, count 0 2006.280.07:53:03.15#ibcon#*before return 0, iclass 10, count 0 2006.280.07:53:03.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:53:03.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.07:53:03.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:53:03.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:53:03.15$vc4f8/vblo=4,712.99 2006.280.07:53:03.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.07:53:03.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.07:53:03.15#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:03.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:53:03.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:53:03.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:53:03.15#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:53:03.15#ibcon#first serial, iclass 12, count 0 2006.280.07:53:03.15#ibcon#enter sib2, iclass 12, count 0 2006.280.07:53:03.15#ibcon#flushed, iclass 12, count 0 2006.280.07:53:03.15#ibcon#about to write, iclass 12, count 0 2006.280.07:53:03.15#ibcon#wrote, iclass 12, count 0 2006.280.07:53:03.15#ibcon#about to read 3, iclass 12, count 0 2006.280.07:53:03.17#ibcon#read 3, iclass 12, count 0 2006.280.07:53:03.18#ibcon#about to read 4, iclass 12, count 0 2006.280.07:53:03.18#ibcon#read 4, iclass 12, count 0 2006.280.07:53:03.18#ibcon#about to read 5, iclass 12, count 0 2006.280.07:53:03.18#ibcon#read 5, iclass 12, count 0 2006.280.07:53:03.18#ibcon#about to read 6, iclass 12, count 0 2006.280.07:53:03.18#ibcon#read 6, iclass 12, count 0 2006.280.07:53:03.18#ibcon#end of sib2, iclass 12, count 0 2006.280.07:53:03.18#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:53:03.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:53:03.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:53:03.18#ibcon#*before write, iclass 12, count 0 2006.280.07:53:03.18#ibcon#enter sib2, iclass 12, count 0 2006.280.07:53:03.18#ibcon#flushed, iclass 12, count 0 2006.280.07:53:03.18#ibcon#about to write, iclass 12, count 0 2006.280.07:53:03.18#ibcon#wrote, iclass 12, count 0 2006.280.07:53:03.18#ibcon#about to read 3, iclass 12, count 0 2006.280.07:53:03.22#ibcon#read 3, iclass 12, count 0 2006.280.07:53:03.22#ibcon#about to read 4, iclass 12, count 0 2006.280.07:53:03.22#ibcon#read 4, iclass 12, count 0 2006.280.07:53:03.22#ibcon#about to read 5, iclass 12, count 0 2006.280.07:53:03.22#ibcon#read 5, iclass 12, count 0 2006.280.07:53:03.22#ibcon#about to read 6, iclass 12, count 0 2006.280.07:53:03.22#ibcon#read 6, iclass 12, count 0 2006.280.07:53:03.22#ibcon#end of sib2, iclass 12, count 0 2006.280.07:53:03.22#ibcon#*after write, iclass 12, count 0 2006.280.07:53:03.22#ibcon#*before return 0, iclass 12, count 0 2006.280.07:53:03.22#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:53:03.22#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.07:53:03.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:53:03.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:53:03.22$vc4f8/vb=4,4 2006.280.07:53:03.22#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.07:53:03.22#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.07:53:03.22#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:03.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:03.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:03.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:03.28#ibcon#enter wrdev, iclass 14, count 2 2006.280.07:53:03.28#ibcon#first serial, iclass 14, count 2 2006.280.07:53:03.28#ibcon#enter sib2, iclass 14, count 2 2006.280.07:53:03.28#ibcon#flushed, iclass 14, count 2 2006.280.07:53:03.28#ibcon#about to write, iclass 14, count 2 2006.280.07:53:03.28#ibcon#wrote, iclass 14, count 2 2006.280.07:53:03.28#ibcon#about to read 3, iclass 14, count 2 2006.280.07:53:03.29#ibcon#read 3, iclass 14, count 2 2006.280.07:53:03.29#ibcon#about to read 4, iclass 14, count 2 2006.280.07:53:03.29#ibcon#read 4, iclass 14, count 2 2006.280.07:53:03.29#ibcon#about to read 5, iclass 14, count 2 2006.280.07:53:03.29#ibcon#read 5, iclass 14, count 2 2006.280.07:53:03.29#ibcon#about to read 6, iclass 14, count 2 2006.280.07:53:03.29#ibcon#read 6, iclass 14, count 2 2006.280.07:53:03.29#ibcon#end of sib2, iclass 14, count 2 2006.280.07:53:03.29#ibcon#*mode == 0, iclass 14, count 2 2006.280.07:53:03.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.07:53:03.31#ibcon#[27=AT04-04\r\n] 2006.280.07:53:03.31#ibcon#*before write, iclass 14, count 2 2006.280.07:53:03.31#ibcon#enter sib2, iclass 14, count 2 2006.280.07:53:03.31#ibcon#flushed, iclass 14, count 2 2006.280.07:53:03.31#ibcon#about to write, iclass 14, count 2 2006.280.07:53:03.31#ibcon#wrote, iclass 14, count 2 2006.280.07:53:03.31#ibcon#about to read 3, iclass 14, count 2 2006.280.07:53:03.34#ibcon#read 3, iclass 14, count 2 2006.280.07:53:03.34#ibcon#about to read 4, iclass 14, count 2 2006.280.07:53:03.34#ibcon#read 4, iclass 14, count 2 2006.280.07:53:03.34#ibcon#about to read 5, iclass 14, count 2 2006.280.07:53:03.34#ibcon#read 5, iclass 14, count 2 2006.280.07:53:03.34#ibcon#about to read 6, iclass 14, count 2 2006.280.07:53:03.34#ibcon#read 6, iclass 14, count 2 2006.280.07:53:03.34#ibcon#end of sib2, iclass 14, count 2 2006.280.07:53:03.34#ibcon#*after write, iclass 14, count 2 2006.280.07:53:03.34#ibcon#*before return 0, iclass 14, count 2 2006.280.07:53:03.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:03.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.07:53:03.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.07:53:03.34#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:03.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:03.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:03.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:03.46#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:53:03.46#ibcon#first serial, iclass 14, count 0 2006.280.07:53:03.46#ibcon#enter sib2, iclass 14, count 0 2006.280.07:53:03.46#ibcon#flushed, iclass 14, count 0 2006.280.07:53:03.46#ibcon#about to write, iclass 14, count 0 2006.280.07:53:03.46#ibcon#wrote, iclass 14, count 0 2006.280.07:53:03.46#ibcon#about to read 3, iclass 14, count 0 2006.280.07:53:03.48#ibcon#read 3, iclass 14, count 0 2006.280.07:53:03.48#ibcon#about to read 4, iclass 14, count 0 2006.280.07:53:03.48#ibcon#read 4, iclass 14, count 0 2006.280.07:53:03.48#ibcon#about to read 5, iclass 14, count 0 2006.280.07:53:03.48#ibcon#read 5, iclass 14, count 0 2006.280.07:53:03.48#ibcon#about to read 6, iclass 14, count 0 2006.280.07:53:03.48#ibcon#read 6, iclass 14, count 0 2006.280.07:53:03.48#ibcon#end of sib2, iclass 14, count 0 2006.280.07:53:03.48#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:53:03.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:53:03.48#ibcon#[27=USB\r\n] 2006.280.07:53:03.48#ibcon#*before write, iclass 14, count 0 2006.280.07:53:03.48#ibcon#enter sib2, iclass 14, count 0 2006.280.07:53:03.48#ibcon#flushed, iclass 14, count 0 2006.280.07:53:03.48#ibcon#about to write, iclass 14, count 0 2006.280.07:53:03.48#ibcon#wrote, iclass 14, count 0 2006.280.07:53:03.48#ibcon#about to read 3, iclass 14, count 0 2006.280.07:53:03.51#ibcon#read 3, iclass 14, count 0 2006.280.07:53:03.51#ibcon#about to read 4, iclass 14, count 0 2006.280.07:53:03.51#ibcon#read 4, iclass 14, count 0 2006.280.07:53:03.51#ibcon#about to read 5, iclass 14, count 0 2006.280.07:53:03.51#ibcon#read 5, iclass 14, count 0 2006.280.07:53:03.51#ibcon#about to read 6, iclass 14, count 0 2006.280.07:53:03.51#ibcon#read 6, iclass 14, count 0 2006.280.07:53:03.51#ibcon#end of sib2, iclass 14, count 0 2006.280.07:53:03.51#ibcon#*after write, iclass 14, count 0 2006.280.07:53:03.51#ibcon#*before return 0, iclass 14, count 0 2006.280.07:53:03.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:03.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.07:53:03.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:53:03.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:53:03.51$vc4f8/vblo=5,744.99 2006.280.07:53:03.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:53:03.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:53:03.51#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:03.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:03.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:03.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:03.51#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:53:03.51#ibcon#first serial, iclass 16, count 0 2006.280.07:53:03.51#ibcon#enter sib2, iclass 16, count 0 2006.280.07:53:03.51#ibcon#flushed, iclass 16, count 0 2006.280.07:53:03.51#ibcon#about to write, iclass 16, count 0 2006.280.07:53:03.51#ibcon#wrote, iclass 16, count 0 2006.280.07:53:03.51#ibcon#about to read 3, iclass 16, count 0 2006.280.07:53:03.53#ibcon#read 3, iclass 16, count 0 2006.280.07:53:03.53#ibcon#about to read 4, iclass 16, count 0 2006.280.07:53:03.53#ibcon#read 4, iclass 16, count 0 2006.280.07:53:03.53#ibcon#about to read 5, iclass 16, count 0 2006.280.07:53:03.53#ibcon#read 5, iclass 16, count 0 2006.280.07:53:03.53#ibcon#about to read 6, iclass 16, count 0 2006.280.07:53:03.53#ibcon#read 6, iclass 16, count 0 2006.280.07:53:03.53#ibcon#end of sib2, iclass 16, count 0 2006.280.07:53:03.53#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:53:03.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:53:03.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:53:03.53#ibcon#*before write, iclass 16, count 0 2006.280.07:53:03.53#ibcon#enter sib2, iclass 16, count 0 2006.280.07:53:03.53#ibcon#flushed, iclass 16, count 0 2006.280.07:53:03.53#ibcon#about to write, iclass 16, count 0 2006.280.07:53:03.53#ibcon#wrote, iclass 16, count 0 2006.280.07:53:03.53#ibcon#about to read 3, iclass 16, count 0 2006.280.07:53:03.57#ibcon#read 3, iclass 16, count 0 2006.280.07:53:03.57#ibcon#about to read 4, iclass 16, count 0 2006.280.07:53:03.57#ibcon#read 4, iclass 16, count 0 2006.280.07:53:03.57#ibcon#about to read 5, iclass 16, count 0 2006.280.07:53:03.57#ibcon#read 5, iclass 16, count 0 2006.280.07:53:03.57#ibcon#about to read 6, iclass 16, count 0 2006.280.07:53:03.57#ibcon#read 6, iclass 16, count 0 2006.280.07:53:03.57#ibcon#end of sib2, iclass 16, count 0 2006.280.07:53:03.57#ibcon#*after write, iclass 16, count 0 2006.280.07:53:03.57#ibcon#*before return 0, iclass 16, count 0 2006.280.07:53:03.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:03.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:53:03.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:53:03.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:53:03.57$vc4f8/vb=5,4 2006.280.07:53:03.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.07:53:03.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.07:53:03.57#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:03.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:03.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:03.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:03.63#ibcon#enter wrdev, iclass 18, count 2 2006.280.07:53:03.63#ibcon#first serial, iclass 18, count 2 2006.280.07:53:03.63#ibcon#enter sib2, iclass 18, count 2 2006.280.07:53:03.63#ibcon#flushed, iclass 18, count 2 2006.280.07:53:03.63#ibcon#about to write, iclass 18, count 2 2006.280.07:53:03.63#ibcon#wrote, iclass 18, count 2 2006.280.07:53:03.63#ibcon#about to read 3, iclass 18, count 2 2006.280.07:53:03.65#ibcon#read 3, iclass 18, count 2 2006.280.07:53:03.65#ibcon#about to read 4, iclass 18, count 2 2006.280.07:53:03.65#ibcon#read 4, iclass 18, count 2 2006.280.07:53:03.65#ibcon#about to read 5, iclass 18, count 2 2006.280.07:53:03.65#ibcon#read 5, iclass 18, count 2 2006.280.07:53:03.65#ibcon#about to read 6, iclass 18, count 2 2006.280.07:53:03.65#ibcon#read 6, iclass 18, count 2 2006.280.07:53:03.65#ibcon#end of sib2, iclass 18, count 2 2006.280.07:53:03.65#ibcon#*mode == 0, iclass 18, count 2 2006.280.07:53:03.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.07:53:03.65#ibcon#[27=AT05-04\r\n] 2006.280.07:53:03.65#ibcon#*before write, iclass 18, count 2 2006.280.07:53:03.65#ibcon#enter sib2, iclass 18, count 2 2006.280.07:53:03.65#ibcon#flushed, iclass 18, count 2 2006.280.07:53:03.65#ibcon#about to write, iclass 18, count 2 2006.280.07:53:03.65#ibcon#wrote, iclass 18, count 2 2006.280.07:53:03.65#ibcon#about to read 3, iclass 18, count 2 2006.280.07:53:03.68#ibcon#read 3, iclass 18, count 2 2006.280.07:53:03.68#ibcon#about to read 4, iclass 18, count 2 2006.280.07:53:03.68#ibcon#read 4, iclass 18, count 2 2006.280.07:53:03.68#ibcon#about to read 5, iclass 18, count 2 2006.280.07:53:03.68#ibcon#read 5, iclass 18, count 2 2006.280.07:53:03.68#ibcon#about to read 6, iclass 18, count 2 2006.280.07:53:03.68#ibcon#read 6, iclass 18, count 2 2006.280.07:53:03.68#ibcon#end of sib2, iclass 18, count 2 2006.280.07:53:03.68#ibcon#*after write, iclass 18, count 2 2006.280.07:53:03.68#ibcon#*before return 0, iclass 18, count 2 2006.280.07:53:03.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:03.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.07:53:03.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.07:53:03.68#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:03.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:03.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:03.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:03.80#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:53:03.80#ibcon#first serial, iclass 18, count 0 2006.280.07:53:03.80#ibcon#enter sib2, iclass 18, count 0 2006.280.07:53:03.80#ibcon#flushed, iclass 18, count 0 2006.280.07:53:03.80#ibcon#about to write, iclass 18, count 0 2006.280.07:53:03.80#ibcon#wrote, iclass 18, count 0 2006.280.07:53:03.80#ibcon#about to read 3, iclass 18, count 0 2006.280.07:53:03.82#ibcon#read 3, iclass 18, count 0 2006.280.07:53:03.82#ibcon#about to read 4, iclass 18, count 0 2006.280.07:53:03.82#ibcon#read 4, iclass 18, count 0 2006.280.07:53:03.82#ibcon#about to read 5, iclass 18, count 0 2006.280.07:53:03.82#ibcon#read 5, iclass 18, count 0 2006.280.07:53:03.82#ibcon#about to read 6, iclass 18, count 0 2006.280.07:53:03.82#ibcon#read 6, iclass 18, count 0 2006.280.07:53:03.82#ibcon#end of sib2, iclass 18, count 0 2006.280.07:53:03.82#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:53:03.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:53:03.82#ibcon#[27=USB\r\n] 2006.280.07:53:03.82#ibcon#*before write, iclass 18, count 0 2006.280.07:53:03.82#ibcon#enter sib2, iclass 18, count 0 2006.280.07:53:03.82#ibcon#flushed, iclass 18, count 0 2006.280.07:53:03.82#ibcon#about to write, iclass 18, count 0 2006.280.07:53:03.82#ibcon#wrote, iclass 18, count 0 2006.280.07:53:03.82#ibcon#about to read 3, iclass 18, count 0 2006.280.07:53:03.85#ibcon#read 3, iclass 18, count 0 2006.280.07:53:03.85#ibcon#about to read 4, iclass 18, count 0 2006.280.07:53:03.85#ibcon#read 4, iclass 18, count 0 2006.280.07:53:03.85#ibcon#about to read 5, iclass 18, count 0 2006.280.07:53:03.85#ibcon#read 5, iclass 18, count 0 2006.280.07:53:03.85#ibcon#about to read 6, iclass 18, count 0 2006.280.07:53:03.85#ibcon#read 6, iclass 18, count 0 2006.280.07:53:03.85#ibcon#end of sib2, iclass 18, count 0 2006.280.07:53:03.85#ibcon#*after write, iclass 18, count 0 2006.280.07:53:03.85#ibcon#*before return 0, iclass 18, count 0 2006.280.07:53:03.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:03.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.07:53:03.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:53:03.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:53:03.85$vc4f8/vblo=6,752.99 2006.280.07:53:03.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.07:53:03.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.07:53:03.85#ibcon#ireg 17 cls_cnt 0 2006.280.07:53:03.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:03.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:03.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:03.85#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:53:03.85#ibcon#first serial, iclass 20, count 0 2006.280.07:53:03.85#ibcon#enter sib2, iclass 20, count 0 2006.280.07:53:03.85#ibcon#flushed, iclass 20, count 0 2006.280.07:53:03.85#ibcon#about to write, iclass 20, count 0 2006.280.07:53:03.85#ibcon#wrote, iclass 20, count 0 2006.280.07:53:03.85#ibcon#about to read 3, iclass 20, count 0 2006.280.07:53:03.87#ibcon#read 3, iclass 20, count 0 2006.280.07:53:03.87#ibcon#about to read 4, iclass 20, count 0 2006.280.07:53:03.87#ibcon#read 4, iclass 20, count 0 2006.280.07:53:03.87#ibcon#about to read 5, iclass 20, count 0 2006.280.07:53:03.87#ibcon#read 5, iclass 20, count 0 2006.280.07:53:03.87#ibcon#about to read 6, iclass 20, count 0 2006.280.07:53:03.87#ibcon#read 6, iclass 20, count 0 2006.280.07:53:03.87#ibcon#end of sib2, iclass 20, count 0 2006.280.07:53:03.87#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:53:03.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:53:03.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:53:03.87#ibcon#*before write, iclass 20, count 0 2006.280.07:53:03.87#ibcon#enter sib2, iclass 20, count 0 2006.280.07:53:03.87#ibcon#flushed, iclass 20, count 0 2006.280.07:53:03.87#ibcon#about to write, iclass 20, count 0 2006.280.07:53:03.87#ibcon#wrote, iclass 20, count 0 2006.280.07:53:03.87#ibcon#about to read 3, iclass 20, count 0 2006.280.07:53:03.91#ibcon#read 3, iclass 20, count 0 2006.280.07:53:03.91#ibcon#about to read 4, iclass 20, count 0 2006.280.07:53:03.91#ibcon#read 4, iclass 20, count 0 2006.280.07:53:03.91#ibcon#about to read 5, iclass 20, count 0 2006.280.07:53:03.91#ibcon#read 5, iclass 20, count 0 2006.280.07:53:03.91#ibcon#about to read 6, iclass 20, count 0 2006.280.07:53:03.91#ibcon#read 6, iclass 20, count 0 2006.280.07:53:03.91#ibcon#end of sib2, iclass 20, count 0 2006.280.07:53:03.91#ibcon#*after write, iclass 20, count 0 2006.280.07:53:03.91#ibcon#*before return 0, iclass 20, count 0 2006.280.07:53:03.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:03.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.07:53:03.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:53:03.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:53:03.91$vc4f8/vb=6,4 2006.280.07:53:03.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.07:53:03.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.07:53:03.91#ibcon#ireg 11 cls_cnt 2 2006.280.07:53:03.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:03.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:03.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:03.97#ibcon#enter wrdev, iclass 22, count 2 2006.280.07:53:03.97#ibcon#first serial, iclass 22, count 2 2006.280.07:53:03.97#ibcon#enter sib2, iclass 22, count 2 2006.280.07:53:03.97#ibcon#flushed, iclass 22, count 2 2006.280.07:53:03.97#ibcon#about to write, iclass 22, count 2 2006.280.07:53:03.97#ibcon#wrote, iclass 22, count 2 2006.280.07:53:03.97#ibcon#about to read 3, iclass 22, count 2 2006.280.07:53:03.99#ibcon#read 3, iclass 22, count 2 2006.280.07:53:03.99#ibcon#about to read 4, iclass 22, count 2 2006.280.07:53:03.99#ibcon#read 4, iclass 22, count 2 2006.280.07:53:03.99#ibcon#about to read 5, iclass 22, count 2 2006.280.07:53:03.99#ibcon#read 5, iclass 22, count 2 2006.280.07:53:03.99#ibcon#about to read 6, iclass 22, count 2 2006.280.07:53:03.99#ibcon#read 6, iclass 22, count 2 2006.280.07:53:03.99#ibcon#end of sib2, iclass 22, count 2 2006.280.07:53:03.99#ibcon#*mode == 0, iclass 22, count 2 2006.280.07:53:03.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.07:53:03.99#ibcon#[27=AT06-04\r\n] 2006.280.07:53:03.99#ibcon#*before write, iclass 22, count 2 2006.280.07:53:03.99#ibcon#enter sib2, iclass 22, count 2 2006.280.07:53:03.99#ibcon#flushed, iclass 22, count 2 2006.280.07:53:03.99#ibcon#about to write, iclass 22, count 2 2006.280.07:53:03.99#ibcon#wrote, iclass 22, count 2 2006.280.07:53:03.99#ibcon#about to read 3, iclass 22, count 2 2006.280.07:53:04.02#ibcon#read 3, iclass 22, count 2 2006.280.07:53:04.02#ibcon#about to read 4, iclass 22, count 2 2006.280.07:53:04.02#ibcon#read 4, iclass 22, count 2 2006.280.07:53:04.02#ibcon#about to read 5, iclass 22, count 2 2006.280.07:53:04.02#ibcon#read 5, iclass 22, count 2 2006.280.07:53:04.02#ibcon#about to read 6, iclass 22, count 2 2006.280.07:53:04.02#ibcon#read 6, iclass 22, count 2 2006.280.07:53:04.02#ibcon#end of sib2, iclass 22, count 2 2006.280.07:53:04.02#ibcon#*after write, iclass 22, count 2 2006.280.07:53:04.02#ibcon#*before return 0, iclass 22, count 2 2006.280.07:53:04.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:04.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.07:53:04.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.07:53:04.02#ibcon#ireg 7 cls_cnt 0 2006.280.07:53:04.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:04.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:04.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:04.14#ibcon#enter wrdev, iclass 22, count 0 2006.280.07:53:04.14#ibcon#first serial, iclass 22, count 0 2006.280.07:53:04.14#ibcon#enter sib2, iclass 22, count 0 2006.280.07:53:04.14#ibcon#flushed, iclass 22, count 0 2006.280.07:53:04.14#ibcon#about to write, iclass 22, count 0 2006.280.07:53:04.14#ibcon#wrote, iclass 22, count 0 2006.280.07:53:04.14#ibcon#about to read 3, iclass 22, count 0 2006.280.07:53:04.16#ibcon#read 3, iclass 22, count 0 2006.280.07:53:04.16#ibcon#about to read 4, iclass 22, count 0 2006.280.07:53:04.16#ibcon#read 4, iclass 22, count 0 2006.280.07:53:04.16#ibcon#about to read 5, iclass 22, count 0 2006.280.07:53:04.16#ibcon#read 5, iclass 22, count 0 2006.280.07:53:04.16#ibcon#about to read 6, iclass 22, count 0 2006.280.07:53:04.16#ibcon#read 6, iclass 22, count 0 2006.280.07:53:04.16#ibcon#end of sib2, iclass 22, count 0 2006.280.07:53:04.16#ibcon#*mode == 0, iclass 22, count 0 2006.280.07:53:04.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.07:53:04.16#ibcon#[27=USB\r\n] 2006.280.07:53:04.16#ibcon#*before write, iclass 22, count 0 2006.280.07:53:04.16#ibcon#enter sib2, iclass 22, count 0 2006.280.07:53:04.16#ibcon#flushed, iclass 22, count 0 2006.280.07:53:04.16#ibcon#about to write, iclass 22, count 0 2006.280.07:53:04.16#ibcon#wrote, iclass 22, count 0 2006.280.07:53:04.16#ibcon#about to read 3, iclass 22, count 0 2006.280.07:53:04.19#ibcon#read 3, iclass 22, count 0 2006.280.07:53:04.19#ibcon#about to read 4, iclass 22, count 0 2006.280.07:53:04.19#ibcon#read 4, iclass 22, count 0 2006.280.07:53:04.19#ibcon#about to read 5, iclass 22, count 0 2006.280.07:53:04.19#ibcon#read 5, iclass 22, count 0 2006.280.07:53:04.20#ibcon#about to read 6, iclass 22, count 0 2006.280.07:53:04.20#ibcon#read 6, iclass 22, count 0 2006.280.07:53:04.20#ibcon#end of sib2, iclass 22, count 0 2006.280.07:53:04.20#ibcon#*after write, iclass 22, count 0 2006.280.07:53:04.20#ibcon#*before return 0, iclass 22, count 0 2006.280.07:53:04.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:04.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.07:53:04.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.07:53:04.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.07:53:04.20$vc4f8/vabw=wide 2006.280.07:53:04.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.07:53:04.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.07:53:04.20#ibcon#ireg 8 cls_cnt 0 2006.280.07:53:04.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:04.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:04.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:04.20#ibcon#enter wrdev, iclass 24, count 0 2006.280.07:53:04.20#ibcon#first serial, iclass 24, count 0 2006.280.07:53:04.20#ibcon#enter sib2, iclass 24, count 0 2006.280.07:53:04.20#ibcon#flushed, iclass 24, count 0 2006.280.07:53:04.20#ibcon#about to write, iclass 24, count 0 2006.280.07:53:04.20#ibcon#wrote, iclass 24, count 0 2006.280.07:53:04.20#ibcon#about to read 3, iclass 24, count 0 2006.280.07:53:04.21#ibcon#read 3, iclass 24, count 0 2006.280.07:53:04.21#ibcon#about to read 4, iclass 24, count 0 2006.280.07:53:04.21#ibcon#read 4, iclass 24, count 0 2006.280.07:53:04.21#ibcon#about to read 5, iclass 24, count 0 2006.280.07:53:04.21#ibcon#read 5, iclass 24, count 0 2006.280.07:53:04.21#ibcon#about to read 6, iclass 24, count 0 2006.280.07:53:04.21#ibcon#read 6, iclass 24, count 0 2006.280.07:53:04.21#ibcon#end of sib2, iclass 24, count 0 2006.280.07:53:04.21#ibcon#*mode == 0, iclass 24, count 0 2006.280.07:53:04.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.07:53:04.21#ibcon#[25=BW32\r\n] 2006.280.07:53:04.21#ibcon#*before write, iclass 24, count 0 2006.280.07:53:04.21#ibcon#enter sib2, iclass 24, count 0 2006.280.07:53:04.21#ibcon#flushed, iclass 24, count 0 2006.280.07:53:04.21#ibcon#about to write, iclass 24, count 0 2006.280.07:53:04.21#ibcon#wrote, iclass 24, count 0 2006.280.07:53:04.21#ibcon#about to read 3, iclass 24, count 0 2006.280.07:53:04.24#ibcon#read 3, iclass 24, count 0 2006.280.07:53:04.24#ibcon#about to read 4, iclass 24, count 0 2006.280.07:53:04.24#ibcon#read 4, iclass 24, count 0 2006.280.07:53:04.24#ibcon#about to read 5, iclass 24, count 0 2006.280.07:53:04.24#ibcon#read 5, iclass 24, count 0 2006.280.07:53:04.24#ibcon#about to read 6, iclass 24, count 0 2006.280.07:53:04.24#ibcon#read 6, iclass 24, count 0 2006.280.07:53:04.24#ibcon#end of sib2, iclass 24, count 0 2006.280.07:53:04.24#ibcon#*after write, iclass 24, count 0 2006.280.07:53:04.24#ibcon#*before return 0, iclass 24, count 0 2006.280.07:53:04.24#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:04.24#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.07:53:04.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.07:53:04.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.07:53:04.25$vc4f8/vbbw=wide 2006.280.07:53:04.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:53:04.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:53:04.28#ibcon#ireg 8 cls_cnt 0 2006.280.07:53:04.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:53:04.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:53:04.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:53:04.31#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:53:04.31#ibcon#first serial, iclass 26, count 0 2006.280.07:53:04.31#ibcon#enter sib2, iclass 26, count 0 2006.280.07:53:04.31#ibcon#flushed, iclass 26, count 0 2006.280.07:53:04.31#ibcon#about to write, iclass 26, count 0 2006.280.07:53:04.31#ibcon#wrote, iclass 26, count 0 2006.280.07:53:04.31#ibcon#about to read 3, iclass 26, count 0 2006.280.07:53:04.34#ibcon#read 3, iclass 26, count 0 2006.280.07:53:04.34#ibcon#about to read 4, iclass 26, count 0 2006.280.07:53:04.34#ibcon#read 4, iclass 26, count 0 2006.280.07:53:04.34#ibcon#about to read 5, iclass 26, count 0 2006.280.07:53:04.34#ibcon#read 5, iclass 26, count 0 2006.280.07:53:04.34#ibcon#about to read 6, iclass 26, count 0 2006.280.07:53:04.34#ibcon#read 6, iclass 26, count 0 2006.280.07:53:04.34#ibcon#end of sib2, iclass 26, count 0 2006.280.07:53:04.34#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:53:04.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:53:04.34#ibcon#[27=BW32\r\n] 2006.280.07:53:04.34#ibcon#*before write, iclass 26, count 0 2006.280.07:53:04.34#ibcon#enter sib2, iclass 26, count 0 2006.280.07:53:04.34#ibcon#flushed, iclass 26, count 0 2006.280.07:53:04.34#ibcon#about to write, iclass 26, count 0 2006.280.07:53:04.34#ibcon#wrote, iclass 26, count 0 2006.280.07:53:04.34#ibcon#about to read 3, iclass 26, count 0 2006.280.07:53:04.37#ibcon#read 3, iclass 26, count 0 2006.280.07:53:04.37#ibcon#about to read 4, iclass 26, count 0 2006.280.07:53:04.37#ibcon#read 4, iclass 26, count 0 2006.280.07:53:04.37#ibcon#about to read 5, iclass 26, count 0 2006.280.07:53:04.37#ibcon#read 5, iclass 26, count 0 2006.280.07:53:04.37#ibcon#about to read 6, iclass 26, count 0 2006.280.07:53:04.37#ibcon#read 6, iclass 26, count 0 2006.280.07:53:04.37#ibcon#end of sib2, iclass 26, count 0 2006.280.07:53:04.37#ibcon#*after write, iclass 26, count 0 2006.280.07:53:04.37#ibcon#*before return 0, iclass 26, count 0 2006.280.07:53:04.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:53:04.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:53:04.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:53:04.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:53:04.37$4f8m12a/ifd4f 2006.280.07:53:04.38$ifd4f/lo= 2006.280.07:53:04.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:53:04.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:53:04.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:53:04.38$ifd4f/patch= 2006.280.07:53:04.39$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:53:04.39$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:53:04.39$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:53:04.39$4f8m12a/"form=m,16.000,1:2 2006.280.07:53:04.39$4f8m12a/"tpicd 2006.280.07:53:04.39$4f8m12a/echo=off 2006.280.07:53:04.39$4f8m12a/xlog=off 2006.280.07:53:04.39:!2006.280.07:54:40 2006.280.07:53:34.14#trakl#Source acquired 2006.280.07:53:36.14#flagr#flagr/antenna,acquired 2006.280.07:54:40.01:preob 2006.280.07:54:41.14/onsource/TRACKING 2006.280.07:54:41.14:!2006.280.07:54:50 2006.280.07:54:50.00:data_valid=on 2006.280.07:54:50.00:midob 2006.280.07:54:50.14/onsource/TRACKING 2006.280.07:54:50.14/wx/21.07,987.0,59 2006.280.07:54:50.20/cable/+6.4821E-03 2006.280.07:54:51.29/va/01,07,usb,yes,34,35 2006.280.07:54:51.29/va/02,06,usb,yes,31,33 2006.280.07:54:51.29/va/03,06,usb,yes,30,29 2006.280.07:54:51.29/va/04,06,usb,yes,32,35 2006.280.07:54:51.29/va/05,07,usb,yes,30,32 2006.280.07:54:51.29/va/06,06,usb,yes,29,29 2006.280.07:54:51.29/va/07,06,usb,yes,30,29 2006.280.07:54:51.29/va/08,06,usb,yes,32,31 2006.280.07:54:51.52/valo/01,532.99,yes,locked 2006.280.07:54:51.52/valo/02,572.99,yes,locked 2006.280.07:54:51.52/valo/03,672.99,yes,locked 2006.280.07:54:51.52/valo/04,832.99,yes,locked 2006.280.07:54:51.52/valo/05,652.99,yes,locked 2006.280.07:54:51.52/valo/06,772.99,yes,locked 2006.280.07:54:51.52/valo/07,832.99,yes,locked 2006.280.07:54:51.52/valo/08,852.99,yes,locked 2006.280.07:54:52.61/vb/01,04,usb,yes,30,29 2006.280.07:54:52.61/vb/02,05,usb,yes,29,30 2006.280.07:54:52.61/vb/03,04,usb,yes,29,33 2006.280.07:54:52.61/vb/04,04,usb,yes,29,30 2006.280.07:54:52.61/vb/05,04,usb,yes,27,32 2006.280.07:54:52.61/vb/06,04,usb,yes,28,31 2006.280.07:54:52.61/vb/07,04,usb,yes,31,31 2006.280.07:54:52.61/vb/08,04,usb,yes,28,32 2006.280.07:54:52.84/vblo/01,632.99,yes,locked 2006.280.07:54:52.84/vblo/02,640.99,yes,locked 2006.280.07:54:52.84/vblo/03,656.99,yes,locked 2006.280.07:54:52.84/vblo/04,712.99,yes,locked 2006.280.07:54:52.84/vblo/05,744.99,yes,locked 2006.280.07:54:52.84/vblo/06,752.99,yes,locked 2006.280.07:54:52.84/vblo/07,734.99,yes,locked 2006.280.07:54:52.84/vblo/08,744.99,yes,locked 2006.280.07:54:52.99/vabw/8 2006.280.07:54:53.14/vbbw/8 2006.280.07:54:53.25/xfe/off,on,12.2 2006.280.07:54:53.63/ifatt/23,28,28,28 2006.280.07:54:54.07/fmout-gps/S +3.22E-07 2006.280.07:54:54.10:!2006.280.07:55:50 2006.280.07:55:50.01:data_valid=off 2006.280.07:55:50.02:postob 2006.280.07:55:50.15/cable/+6.4827E-03 2006.280.07:55:50.15/wx/21.04,987.0,60 2006.280.07:55:51.07/fmout-gps/S +3.24E-07 2006.280.07:55:51.07:scan_name=280-0758,k06280,60 2006.280.07:55:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.280.07:55:52.14#flagr#flagr/antenna,new-source 2006.280.07:55:52.15:checkk5 2006.280.07:55:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:55:52.96/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:55:53.40/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:55:53.85/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:55:54.27/chk_obsdata//k5ts1/T2800754??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:55:54.73/chk_obsdata//k5ts2/T2800754??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:55:55.18/chk_obsdata//k5ts3/T2800754??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:55:55.60/chk_obsdata//k5ts4/T2800754??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:55:56.41/k5log//k5ts1_log_newline 2006.280.07:55:57.18/k5log//k5ts2_log_newline 2006.280.07:55:58.27/k5log//k5ts3_log_newline 2006.280.07:55:59.07/k5log//k5ts4_log_newline 2006.280.07:55:59.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:55:59.09:4f8m12a=2 2006.280.07:55:59.09$4f8m12a/echo=on 2006.280.07:55:59.09$4f8m12a/pcalon 2006.280.07:55:59.09$pcalon/"no phase cal control is implemented here 2006.280.07:55:59.09$4f8m12a/"tpicd=stop 2006.280.07:55:59.09$4f8m12a/vc4f8 2006.280.07:55:59.10$vc4f8/valo=1,532.99 2006.280.07:55:59.10#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:55:59.10#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:55:59.10#ibcon#ireg 17 cls_cnt 0 2006.280.07:55:59.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:55:59.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:55:59.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:55:59.10#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:55:59.10#ibcon#first serial, iclass 25, count 0 2006.280.07:55:59.10#ibcon#enter sib2, iclass 25, count 0 2006.280.07:55:59.10#ibcon#flushed, iclass 25, count 0 2006.280.07:55:59.10#ibcon#about to write, iclass 25, count 0 2006.280.07:55:59.10#ibcon#wrote, iclass 25, count 0 2006.280.07:55:59.10#ibcon#about to read 3, iclass 25, count 0 2006.280.07:55:59.11#ibcon#read 3, iclass 25, count 0 2006.280.07:55:59.11#ibcon#about to read 4, iclass 25, count 0 2006.280.07:55:59.11#ibcon#read 4, iclass 25, count 0 2006.280.07:55:59.11#ibcon#about to read 5, iclass 25, count 0 2006.280.07:55:59.11#ibcon#read 5, iclass 25, count 0 2006.280.07:55:59.11#ibcon#about to read 6, iclass 25, count 0 2006.280.07:55:59.11#ibcon#read 6, iclass 25, count 0 2006.280.07:55:59.11#ibcon#end of sib2, iclass 25, count 0 2006.280.07:55:59.11#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:55:59.11#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:55:59.11#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:55:59.11#ibcon#*before write, iclass 25, count 0 2006.280.07:55:59.11#ibcon#enter sib2, iclass 25, count 0 2006.280.07:55:59.11#ibcon#flushed, iclass 25, count 0 2006.280.07:55:59.11#ibcon#about to write, iclass 25, count 0 2006.280.07:55:59.11#ibcon#wrote, iclass 25, count 0 2006.280.07:55:59.11#ibcon#about to read 3, iclass 25, count 0 2006.280.07:55:59.16#ibcon#read 3, iclass 25, count 0 2006.280.07:55:59.16#ibcon#about to read 4, iclass 25, count 0 2006.280.07:55:59.16#ibcon#read 4, iclass 25, count 0 2006.280.07:55:59.16#ibcon#about to read 5, iclass 25, count 0 2006.280.07:55:59.16#ibcon#read 5, iclass 25, count 0 2006.280.07:55:59.16#ibcon#about to read 6, iclass 25, count 0 2006.280.07:55:59.16#ibcon#read 6, iclass 25, count 0 2006.280.07:55:59.16#ibcon#end of sib2, iclass 25, count 0 2006.280.07:55:59.16#ibcon#*after write, iclass 25, count 0 2006.280.07:55:59.16#ibcon#*before return 0, iclass 25, count 0 2006.280.07:55:59.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:55:59.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:55:59.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:55:59.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:55:59.16$vc4f8/va=1,7 2006.280.07:55:59.16#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:55:59.16#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:55:59.16#ibcon#ireg 11 cls_cnt 2 2006.280.07:55:59.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:55:59.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:55:59.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:55:59.16#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:55:59.16#ibcon#first serial, iclass 27, count 2 2006.280.07:55:59.16#ibcon#enter sib2, iclass 27, count 2 2006.280.07:55:59.16#ibcon#flushed, iclass 27, count 2 2006.280.07:55:59.16#ibcon#about to write, iclass 27, count 2 2006.280.07:55:59.16#ibcon#wrote, iclass 27, count 2 2006.280.07:55:59.16#ibcon#about to read 3, iclass 27, count 2 2006.280.07:55:59.18#ibcon#read 3, iclass 27, count 2 2006.280.07:55:59.18#ibcon#about to read 4, iclass 27, count 2 2006.280.07:55:59.18#ibcon#read 4, iclass 27, count 2 2006.280.07:55:59.18#ibcon#about to read 5, iclass 27, count 2 2006.280.07:55:59.18#ibcon#read 5, iclass 27, count 2 2006.280.07:55:59.18#ibcon#about to read 6, iclass 27, count 2 2006.280.07:55:59.18#ibcon#read 6, iclass 27, count 2 2006.280.07:55:59.18#ibcon#end of sib2, iclass 27, count 2 2006.280.07:55:59.18#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:55:59.18#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:55:59.18#ibcon#[25=AT01-07\r\n] 2006.280.07:55:59.18#ibcon#*before write, iclass 27, count 2 2006.280.07:55:59.18#ibcon#enter sib2, iclass 27, count 2 2006.280.07:55:59.18#ibcon#flushed, iclass 27, count 2 2006.280.07:55:59.18#ibcon#about to write, iclass 27, count 2 2006.280.07:55:59.18#ibcon#wrote, iclass 27, count 2 2006.280.07:55:59.18#ibcon#about to read 3, iclass 27, count 2 2006.280.07:55:59.21#ibcon#read 3, iclass 27, count 2 2006.280.07:55:59.21#ibcon#about to read 4, iclass 27, count 2 2006.280.07:55:59.21#ibcon#read 4, iclass 27, count 2 2006.280.07:55:59.21#ibcon#about to read 5, iclass 27, count 2 2006.280.07:55:59.21#ibcon#read 5, iclass 27, count 2 2006.280.07:55:59.21#ibcon#about to read 6, iclass 27, count 2 2006.280.07:55:59.21#ibcon#read 6, iclass 27, count 2 2006.280.07:55:59.21#ibcon#end of sib2, iclass 27, count 2 2006.280.07:55:59.22#ibcon#*after write, iclass 27, count 2 2006.280.07:55:59.22#ibcon#*before return 0, iclass 27, count 2 2006.280.07:55:59.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:55:59.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:55:59.22#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:55:59.22#ibcon#ireg 7 cls_cnt 0 2006.280.07:55:59.22#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:55:59.33#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:55:59.33#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:55:59.33#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:55:59.33#ibcon#first serial, iclass 27, count 0 2006.280.07:55:59.33#ibcon#enter sib2, iclass 27, count 0 2006.280.07:55:59.33#ibcon#flushed, iclass 27, count 0 2006.280.07:55:59.33#ibcon#about to write, iclass 27, count 0 2006.280.07:55:59.33#ibcon#wrote, iclass 27, count 0 2006.280.07:55:59.33#ibcon#about to read 3, iclass 27, count 0 2006.280.07:55:59.35#ibcon#read 3, iclass 27, count 0 2006.280.07:55:59.35#ibcon#about to read 4, iclass 27, count 0 2006.280.07:55:59.35#ibcon#read 4, iclass 27, count 0 2006.280.07:55:59.35#ibcon#about to read 5, iclass 27, count 0 2006.280.07:55:59.35#ibcon#read 5, iclass 27, count 0 2006.280.07:55:59.35#ibcon#about to read 6, iclass 27, count 0 2006.280.07:55:59.35#ibcon#read 6, iclass 27, count 0 2006.280.07:55:59.35#ibcon#end of sib2, iclass 27, count 0 2006.280.07:55:59.35#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:55:59.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:55:59.35#ibcon#[25=USB\r\n] 2006.280.07:55:59.35#ibcon#*before write, iclass 27, count 0 2006.280.07:55:59.35#ibcon#enter sib2, iclass 27, count 0 2006.280.07:55:59.35#ibcon#flushed, iclass 27, count 0 2006.280.07:55:59.35#ibcon#about to write, iclass 27, count 0 2006.280.07:55:59.35#ibcon#wrote, iclass 27, count 0 2006.280.07:55:59.35#ibcon#about to read 3, iclass 27, count 0 2006.280.07:55:59.38#ibcon#read 3, iclass 27, count 0 2006.280.07:55:59.38#ibcon#about to read 4, iclass 27, count 0 2006.280.07:55:59.38#ibcon#read 4, iclass 27, count 0 2006.280.07:55:59.38#ibcon#about to read 5, iclass 27, count 0 2006.280.07:55:59.38#ibcon#read 5, iclass 27, count 0 2006.280.07:55:59.38#ibcon#about to read 6, iclass 27, count 0 2006.280.07:55:59.38#ibcon#read 6, iclass 27, count 0 2006.280.07:55:59.38#ibcon#end of sib2, iclass 27, count 0 2006.280.07:55:59.38#ibcon#*after write, iclass 27, count 0 2006.280.07:55:59.38#ibcon#*before return 0, iclass 27, count 0 2006.280.07:55:59.38#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:55:59.38#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:55:59.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:55:59.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:55:59.38$vc4f8/valo=2,572.99 2006.280.07:55:59.38#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:55:59.38#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:55:59.38#ibcon#ireg 17 cls_cnt 0 2006.280.07:55:59.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:55:59.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:55:59.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:55:59.38#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:55:59.38#ibcon#first serial, iclass 29, count 0 2006.280.07:55:59.38#ibcon#enter sib2, iclass 29, count 0 2006.280.07:55:59.38#ibcon#flushed, iclass 29, count 0 2006.280.07:55:59.38#ibcon#about to write, iclass 29, count 0 2006.280.07:55:59.38#ibcon#wrote, iclass 29, count 0 2006.280.07:55:59.38#ibcon#about to read 3, iclass 29, count 0 2006.280.07:55:59.41#ibcon#read 3, iclass 29, count 0 2006.280.07:55:59.42#ibcon#about to read 4, iclass 29, count 0 2006.280.07:55:59.42#ibcon#read 4, iclass 29, count 0 2006.280.07:55:59.42#ibcon#about to read 5, iclass 29, count 0 2006.280.07:55:59.42#ibcon#read 5, iclass 29, count 0 2006.280.07:55:59.42#ibcon#about to read 6, iclass 29, count 0 2006.280.07:55:59.42#ibcon#read 6, iclass 29, count 0 2006.280.07:55:59.42#ibcon#end of sib2, iclass 29, count 0 2006.280.07:55:59.42#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:55:59.42#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:55:59.42#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:55:59.42#ibcon#*before write, iclass 29, count 0 2006.280.07:55:59.42#ibcon#enter sib2, iclass 29, count 0 2006.280.07:55:59.42#ibcon#flushed, iclass 29, count 0 2006.280.07:55:59.42#ibcon#about to write, iclass 29, count 0 2006.280.07:55:59.42#ibcon#wrote, iclass 29, count 0 2006.280.07:55:59.42#ibcon#about to read 3, iclass 29, count 0 2006.280.07:55:59.46#ibcon#read 3, iclass 29, count 0 2006.280.07:55:59.46#ibcon#about to read 4, iclass 29, count 0 2006.280.07:55:59.46#ibcon#read 4, iclass 29, count 0 2006.280.07:55:59.46#ibcon#about to read 5, iclass 29, count 0 2006.280.07:55:59.46#ibcon#read 5, iclass 29, count 0 2006.280.07:55:59.46#ibcon#about to read 6, iclass 29, count 0 2006.280.07:55:59.46#ibcon#read 6, iclass 29, count 0 2006.280.07:55:59.46#ibcon#end of sib2, iclass 29, count 0 2006.280.07:55:59.46#ibcon#*after write, iclass 29, count 0 2006.280.07:55:59.46#ibcon#*before return 0, iclass 29, count 0 2006.280.07:55:59.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:55:59.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:55:59.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:55:59.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:55:59.46$vc4f8/va=2,6 2006.280.07:55:59.46#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:55:59.46#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:55:59.46#ibcon#ireg 11 cls_cnt 2 2006.280.07:55:59.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:55:59.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:55:59.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:55:59.50#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:55:59.50#ibcon#first serial, iclass 31, count 2 2006.280.07:55:59.50#ibcon#enter sib2, iclass 31, count 2 2006.280.07:55:59.50#ibcon#flushed, iclass 31, count 2 2006.280.07:55:59.50#ibcon#about to write, iclass 31, count 2 2006.280.07:55:59.50#ibcon#wrote, iclass 31, count 2 2006.280.07:55:59.50#ibcon#about to read 3, iclass 31, count 2 2006.280.07:55:59.52#ibcon#read 3, iclass 31, count 2 2006.280.07:55:59.52#ibcon#about to read 4, iclass 31, count 2 2006.280.07:55:59.52#ibcon#read 4, iclass 31, count 2 2006.280.07:55:59.52#ibcon#about to read 5, iclass 31, count 2 2006.280.07:55:59.52#ibcon#read 5, iclass 31, count 2 2006.280.07:55:59.52#ibcon#about to read 6, iclass 31, count 2 2006.280.07:55:59.52#ibcon#read 6, iclass 31, count 2 2006.280.07:55:59.52#ibcon#end of sib2, iclass 31, count 2 2006.280.07:55:59.52#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:55:59.52#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:55:59.53#ibcon#[25=AT02-06\r\n] 2006.280.07:55:59.53#ibcon#*before write, iclass 31, count 2 2006.280.07:55:59.53#ibcon#enter sib2, iclass 31, count 2 2006.280.07:55:59.53#ibcon#flushed, iclass 31, count 2 2006.280.07:55:59.53#ibcon#about to write, iclass 31, count 2 2006.280.07:55:59.53#ibcon#wrote, iclass 31, count 2 2006.280.07:55:59.53#ibcon#about to read 3, iclass 31, count 2 2006.280.07:55:59.56#ibcon#read 3, iclass 31, count 2 2006.280.07:55:59.56#ibcon#about to read 4, iclass 31, count 2 2006.280.07:55:59.56#ibcon#read 4, iclass 31, count 2 2006.280.07:55:59.56#ibcon#about to read 5, iclass 31, count 2 2006.280.07:55:59.56#ibcon#read 5, iclass 31, count 2 2006.280.07:55:59.56#ibcon#about to read 6, iclass 31, count 2 2006.280.07:55:59.56#ibcon#read 6, iclass 31, count 2 2006.280.07:55:59.56#ibcon#end of sib2, iclass 31, count 2 2006.280.07:55:59.56#ibcon#*after write, iclass 31, count 2 2006.280.07:55:59.56#ibcon#*before return 0, iclass 31, count 2 2006.280.07:55:59.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:55:59.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:55:59.56#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:55:59.56#ibcon#ireg 7 cls_cnt 0 2006.280.07:55:59.56#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:55:59.68#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:55:59.68#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:55:59.68#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:55:59.68#ibcon#first serial, iclass 31, count 0 2006.280.07:55:59.68#ibcon#enter sib2, iclass 31, count 0 2006.280.07:55:59.68#ibcon#flushed, iclass 31, count 0 2006.280.07:55:59.68#ibcon#about to write, iclass 31, count 0 2006.280.07:55:59.68#ibcon#wrote, iclass 31, count 0 2006.280.07:55:59.68#ibcon#about to read 3, iclass 31, count 0 2006.280.07:55:59.71#ibcon#read 3, iclass 31, count 0 2006.280.07:55:59.71#ibcon#about to read 4, iclass 31, count 0 2006.280.07:55:59.71#ibcon#read 4, iclass 31, count 0 2006.280.07:55:59.71#ibcon#about to read 5, iclass 31, count 0 2006.280.07:55:59.71#ibcon#read 5, iclass 31, count 0 2006.280.07:55:59.71#ibcon#about to read 6, iclass 31, count 0 2006.280.07:55:59.71#ibcon#read 6, iclass 31, count 0 2006.280.07:55:59.71#ibcon#end of sib2, iclass 31, count 0 2006.280.07:55:59.71#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:55:59.71#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:55:59.71#ibcon#[25=USB\r\n] 2006.280.07:55:59.71#ibcon#*before write, iclass 31, count 0 2006.280.07:55:59.71#ibcon#enter sib2, iclass 31, count 0 2006.280.07:55:59.71#ibcon#flushed, iclass 31, count 0 2006.280.07:55:59.71#ibcon#about to write, iclass 31, count 0 2006.280.07:55:59.71#ibcon#wrote, iclass 31, count 0 2006.280.07:55:59.71#ibcon#about to read 3, iclass 31, count 0 2006.280.07:55:59.74#ibcon#read 3, iclass 31, count 0 2006.280.07:55:59.74#ibcon#about to read 4, iclass 31, count 0 2006.280.07:55:59.74#ibcon#read 4, iclass 31, count 0 2006.280.07:55:59.74#ibcon#about to read 5, iclass 31, count 0 2006.280.07:55:59.74#ibcon#read 5, iclass 31, count 0 2006.280.07:55:59.74#ibcon#about to read 6, iclass 31, count 0 2006.280.07:55:59.74#ibcon#read 6, iclass 31, count 0 2006.280.07:55:59.74#ibcon#end of sib2, iclass 31, count 0 2006.280.07:55:59.74#ibcon#*after write, iclass 31, count 0 2006.280.07:55:59.74#ibcon#*before return 0, iclass 31, count 0 2006.280.07:55:59.74#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:55:59.74#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:55:59.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:55:59.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:55:59.74$vc4f8/valo=3,672.99 2006.280.07:55:59.74#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:55:59.74#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:55:59.74#ibcon#ireg 17 cls_cnt 0 2006.280.07:55:59.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:55:59.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:55:59.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:55:59.74#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:55:59.74#ibcon#first serial, iclass 33, count 0 2006.280.07:55:59.74#ibcon#enter sib2, iclass 33, count 0 2006.280.07:55:59.74#ibcon#flushed, iclass 33, count 0 2006.280.07:55:59.74#ibcon#about to write, iclass 33, count 0 2006.280.07:55:59.74#ibcon#wrote, iclass 33, count 0 2006.280.07:55:59.74#ibcon#about to read 3, iclass 33, count 0 2006.280.07:55:59.76#ibcon#read 3, iclass 33, count 0 2006.280.07:55:59.76#ibcon#about to read 4, iclass 33, count 0 2006.280.07:55:59.76#ibcon#read 4, iclass 33, count 0 2006.280.07:55:59.76#ibcon#about to read 5, iclass 33, count 0 2006.280.07:55:59.76#ibcon#read 5, iclass 33, count 0 2006.280.07:55:59.76#ibcon#about to read 6, iclass 33, count 0 2006.280.07:55:59.76#ibcon#read 6, iclass 33, count 0 2006.280.07:55:59.76#ibcon#end of sib2, iclass 33, count 0 2006.280.07:55:59.76#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:55:59.76#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:55:59.76#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:55:59.76#ibcon#*before write, iclass 33, count 0 2006.280.07:55:59.76#ibcon#enter sib2, iclass 33, count 0 2006.280.07:55:59.76#ibcon#flushed, iclass 33, count 0 2006.280.07:55:59.76#ibcon#about to write, iclass 33, count 0 2006.280.07:55:59.76#ibcon#wrote, iclass 33, count 0 2006.280.07:55:59.76#ibcon#about to read 3, iclass 33, count 0 2006.280.07:55:59.81#ibcon#read 3, iclass 33, count 0 2006.280.07:55:59.81#ibcon#about to read 4, iclass 33, count 0 2006.280.07:55:59.81#ibcon#read 4, iclass 33, count 0 2006.280.07:55:59.81#ibcon#about to read 5, iclass 33, count 0 2006.280.07:55:59.81#ibcon#read 5, iclass 33, count 0 2006.280.07:55:59.81#ibcon#about to read 6, iclass 33, count 0 2006.280.07:55:59.81#ibcon#read 6, iclass 33, count 0 2006.280.07:55:59.81#ibcon#end of sib2, iclass 33, count 0 2006.280.07:55:59.81#ibcon#*after write, iclass 33, count 0 2006.280.07:55:59.81#ibcon#*before return 0, iclass 33, count 0 2006.280.07:55:59.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:55:59.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:55:59.81#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:55:59.81#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:55:59.81$vc4f8/va=3,6 2006.280.07:55:59.81#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:55:59.81#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:55:59.81#ibcon#ireg 11 cls_cnt 2 2006.280.07:55:59.81#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:55:59.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:55:59.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:55:59.85#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:55:59.85#ibcon#first serial, iclass 35, count 2 2006.280.07:55:59.85#ibcon#enter sib2, iclass 35, count 2 2006.280.07:55:59.85#ibcon#flushed, iclass 35, count 2 2006.280.07:55:59.85#ibcon#about to write, iclass 35, count 2 2006.280.07:55:59.85#ibcon#wrote, iclass 35, count 2 2006.280.07:55:59.85#ibcon#about to read 3, iclass 35, count 2 2006.280.07:55:59.87#ibcon#read 3, iclass 35, count 2 2006.280.07:55:59.87#ibcon#about to read 4, iclass 35, count 2 2006.280.07:55:59.87#ibcon#read 4, iclass 35, count 2 2006.280.07:55:59.87#ibcon#about to read 5, iclass 35, count 2 2006.280.07:55:59.87#ibcon#read 5, iclass 35, count 2 2006.280.07:55:59.87#ibcon#about to read 6, iclass 35, count 2 2006.280.07:55:59.87#ibcon#read 6, iclass 35, count 2 2006.280.07:55:59.87#ibcon#end of sib2, iclass 35, count 2 2006.280.07:55:59.87#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:55:59.87#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:55:59.87#ibcon#[25=AT03-06\r\n] 2006.280.07:55:59.87#ibcon#*before write, iclass 35, count 2 2006.280.07:55:59.87#ibcon#enter sib2, iclass 35, count 2 2006.280.07:55:59.87#ibcon#flushed, iclass 35, count 2 2006.280.07:55:59.87#ibcon#about to write, iclass 35, count 2 2006.280.07:55:59.87#ibcon#wrote, iclass 35, count 2 2006.280.07:55:59.87#ibcon#about to read 3, iclass 35, count 2 2006.280.07:55:59.90#ibcon#read 3, iclass 35, count 2 2006.280.07:55:59.90#ibcon#about to read 4, iclass 35, count 2 2006.280.07:55:59.90#ibcon#read 4, iclass 35, count 2 2006.280.07:55:59.90#ibcon#about to read 5, iclass 35, count 2 2006.280.07:55:59.90#ibcon#read 5, iclass 35, count 2 2006.280.07:55:59.90#ibcon#about to read 6, iclass 35, count 2 2006.280.07:55:59.90#ibcon#read 6, iclass 35, count 2 2006.280.07:55:59.90#ibcon#end of sib2, iclass 35, count 2 2006.280.07:55:59.90#ibcon#*after write, iclass 35, count 2 2006.280.07:55:59.90#ibcon#*before return 0, iclass 35, count 2 2006.280.07:55:59.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:55:59.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:55:59.90#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:55:59.90#ibcon#ireg 7 cls_cnt 0 2006.280.07:55:59.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:00.01#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:00.01#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:00.01#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:56:00.01#ibcon#first serial, iclass 35, count 0 2006.280.07:56:00.01#ibcon#enter sib2, iclass 35, count 0 2006.280.07:56:00.01#ibcon#flushed, iclass 35, count 0 2006.280.07:56:00.01#ibcon#about to write, iclass 35, count 0 2006.280.07:56:00.01#ibcon#wrote, iclass 35, count 0 2006.280.07:56:00.01#ibcon#about to read 3, iclass 35, count 0 2006.280.07:56:00.04#ibcon#read 3, iclass 35, count 0 2006.280.07:56:00.04#ibcon#about to read 4, iclass 35, count 0 2006.280.07:56:00.04#ibcon#read 4, iclass 35, count 0 2006.280.07:56:00.04#ibcon#about to read 5, iclass 35, count 0 2006.280.07:56:00.04#ibcon#read 5, iclass 35, count 0 2006.280.07:56:00.04#ibcon#about to read 6, iclass 35, count 0 2006.280.07:56:00.04#ibcon#read 6, iclass 35, count 0 2006.280.07:56:00.04#ibcon#end of sib2, iclass 35, count 0 2006.280.07:56:00.04#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:56:00.04#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:56:00.04#ibcon#[25=USB\r\n] 2006.280.07:56:00.04#ibcon#*before write, iclass 35, count 0 2006.280.07:56:00.04#ibcon#enter sib2, iclass 35, count 0 2006.280.07:56:00.04#ibcon#flushed, iclass 35, count 0 2006.280.07:56:00.04#ibcon#about to write, iclass 35, count 0 2006.280.07:56:00.04#ibcon#wrote, iclass 35, count 0 2006.280.07:56:00.04#ibcon#about to read 3, iclass 35, count 0 2006.280.07:56:00.07#ibcon#read 3, iclass 35, count 0 2006.280.07:56:00.07#ibcon#about to read 4, iclass 35, count 0 2006.280.07:56:00.07#ibcon#read 4, iclass 35, count 0 2006.280.07:56:00.07#ibcon#about to read 5, iclass 35, count 0 2006.280.07:56:00.07#ibcon#read 5, iclass 35, count 0 2006.280.07:56:00.07#ibcon#about to read 6, iclass 35, count 0 2006.280.07:56:00.07#ibcon#read 6, iclass 35, count 0 2006.280.07:56:00.07#ibcon#end of sib2, iclass 35, count 0 2006.280.07:56:00.07#ibcon#*after write, iclass 35, count 0 2006.280.07:56:00.07#ibcon#*before return 0, iclass 35, count 0 2006.280.07:56:00.07#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:00.07#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:00.07#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:56:00.07#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:56:00.07$vc4f8/valo=4,832.99 2006.280.07:56:00.07#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:56:00.07#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:56:00.07#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:00.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:00.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:00.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:00.07#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:56:00.07#ibcon#first serial, iclass 37, count 0 2006.280.07:56:00.07#ibcon#enter sib2, iclass 37, count 0 2006.280.07:56:00.07#ibcon#flushed, iclass 37, count 0 2006.280.07:56:00.07#ibcon#about to write, iclass 37, count 0 2006.280.07:56:00.07#ibcon#wrote, iclass 37, count 0 2006.280.07:56:00.07#ibcon#about to read 3, iclass 37, count 0 2006.280.07:56:00.09#ibcon#read 3, iclass 37, count 0 2006.280.07:56:00.09#ibcon#about to read 4, iclass 37, count 0 2006.280.07:56:00.09#ibcon#read 4, iclass 37, count 0 2006.280.07:56:00.09#ibcon#about to read 5, iclass 37, count 0 2006.280.07:56:00.09#ibcon#read 5, iclass 37, count 0 2006.280.07:56:00.09#ibcon#about to read 6, iclass 37, count 0 2006.280.07:56:00.09#ibcon#read 6, iclass 37, count 0 2006.280.07:56:00.09#ibcon#end of sib2, iclass 37, count 0 2006.280.07:56:00.09#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:56:00.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:56:00.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:56:00.16#ibcon#*before write, iclass 37, count 0 2006.280.07:56:00.16#ibcon#enter sib2, iclass 37, count 0 2006.280.07:56:00.16#ibcon#flushed, iclass 37, count 0 2006.280.07:56:00.16#ibcon#about to write, iclass 37, count 0 2006.280.07:56:00.16#ibcon#wrote, iclass 37, count 0 2006.280.07:56:00.16#ibcon#about to read 3, iclass 37, count 0 2006.280.07:56:00.20#ibcon#read 3, iclass 37, count 0 2006.280.07:56:00.20#ibcon#about to read 4, iclass 37, count 0 2006.280.07:56:00.20#ibcon#read 4, iclass 37, count 0 2006.280.07:56:00.20#ibcon#about to read 5, iclass 37, count 0 2006.280.07:56:00.20#ibcon#read 5, iclass 37, count 0 2006.280.07:56:00.20#ibcon#about to read 6, iclass 37, count 0 2006.280.07:56:00.20#ibcon#read 6, iclass 37, count 0 2006.280.07:56:00.20#ibcon#end of sib2, iclass 37, count 0 2006.280.07:56:00.20#ibcon#*after write, iclass 37, count 0 2006.280.07:56:00.20#ibcon#*before return 0, iclass 37, count 0 2006.280.07:56:00.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:00.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:00.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:56:00.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:56:00.20$vc4f8/va=4,6 2006.280.07:56:00.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:56:00.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:56:00.20#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:00.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:00.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:00.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:00.20#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:56:00.20#ibcon#first serial, iclass 39, count 2 2006.280.07:56:00.20#ibcon#enter sib2, iclass 39, count 2 2006.280.07:56:00.20#ibcon#flushed, iclass 39, count 2 2006.280.07:56:00.20#ibcon#about to write, iclass 39, count 2 2006.280.07:56:00.20#ibcon#wrote, iclass 39, count 2 2006.280.07:56:00.20#ibcon#about to read 3, iclass 39, count 2 2006.280.07:56:00.22#ibcon#read 3, iclass 39, count 2 2006.280.07:56:00.22#ibcon#about to read 4, iclass 39, count 2 2006.280.07:56:00.22#ibcon#read 4, iclass 39, count 2 2006.280.07:56:00.22#ibcon#about to read 5, iclass 39, count 2 2006.280.07:56:00.22#ibcon#read 5, iclass 39, count 2 2006.280.07:56:00.22#ibcon#about to read 6, iclass 39, count 2 2006.280.07:56:00.22#ibcon#read 6, iclass 39, count 2 2006.280.07:56:00.22#ibcon#end of sib2, iclass 39, count 2 2006.280.07:56:00.22#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:56:00.22#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:56:00.22#ibcon#[25=AT04-06\r\n] 2006.280.07:56:00.22#ibcon#*before write, iclass 39, count 2 2006.280.07:56:00.22#ibcon#enter sib2, iclass 39, count 2 2006.280.07:56:00.22#ibcon#flushed, iclass 39, count 2 2006.280.07:56:00.22#ibcon#about to write, iclass 39, count 2 2006.280.07:56:00.22#ibcon#wrote, iclass 39, count 2 2006.280.07:56:00.22#ibcon#about to read 3, iclass 39, count 2 2006.280.07:56:00.26#ibcon#read 3, iclass 39, count 2 2006.280.07:56:00.26#ibcon#about to read 4, iclass 39, count 2 2006.280.07:56:00.26#ibcon#read 4, iclass 39, count 2 2006.280.07:56:00.26#ibcon#about to read 5, iclass 39, count 2 2006.280.07:56:00.26#ibcon#read 5, iclass 39, count 2 2006.280.07:56:00.26#ibcon#about to read 6, iclass 39, count 2 2006.280.07:56:00.26#ibcon#read 6, iclass 39, count 2 2006.280.07:56:00.26#ibcon#end of sib2, iclass 39, count 2 2006.280.07:56:00.26#ibcon#*after write, iclass 39, count 2 2006.280.07:56:00.26#ibcon#*before return 0, iclass 39, count 2 2006.280.07:56:00.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:00.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:00.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:56:00.26#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:00.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:00.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:00.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:00.37#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:56:00.37#ibcon#first serial, iclass 39, count 0 2006.280.07:56:00.37#ibcon#enter sib2, iclass 39, count 0 2006.280.07:56:00.37#ibcon#flushed, iclass 39, count 0 2006.280.07:56:00.37#ibcon#about to write, iclass 39, count 0 2006.280.07:56:00.37#ibcon#wrote, iclass 39, count 0 2006.280.07:56:00.37#ibcon#about to read 3, iclass 39, count 0 2006.280.07:56:00.39#ibcon#read 3, iclass 39, count 0 2006.280.07:56:00.39#ibcon#about to read 4, iclass 39, count 0 2006.280.07:56:00.39#ibcon#read 4, iclass 39, count 0 2006.280.07:56:00.39#ibcon#about to read 5, iclass 39, count 0 2006.280.07:56:00.39#ibcon#read 5, iclass 39, count 0 2006.280.07:56:00.39#ibcon#about to read 6, iclass 39, count 0 2006.280.07:56:00.39#ibcon#read 6, iclass 39, count 0 2006.280.07:56:00.39#ibcon#end of sib2, iclass 39, count 0 2006.280.07:56:00.39#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:56:00.39#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:56:00.39#ibcon#[25=USB\r\n] 2006.280.07:56:00.39#ibcon#*before write, iclass 39, count 0 2006.280.07:56:00.39#ibcon#enter sib2, iclass 39, count 0 2006.280.07:56:00.39#ibcon#flushed, iclass 39, count 0 2006.280.07:56:00.39#ibcon#about to write, iclass 39, count 0 2006.280.07:56:00.39#ibcon#wrote, iclass 39, count 0 2006.280.07:56:00.39#ibcon#about to read 3, iclass 39, count 0 2006.280.07:56:00.42#ibcon#read 3, iclass 39, count 0 2006.280.07:56:00.42#ibcon#about to read 4, iclass 39, count 0 2006.280.07:56:00.42#ibcon#read 4, iclass 39, count 0 2006.280.07:56:00.42#ibcon#about to read 5, iclass 39, count 0 2006.280.07:56:00.42#ibcon#read 5, iclass 39, count 0 2006.280.07:56:00.42#ibcon#about to read 6, iclass 39, count 0 2006.280.07:56:00.42#ibcon#read 6, iclass 39, count 0 2006.280.07:56:00.42#ibcon#end of sib2, iclass 39, count 0 2006.280.07:56:00.42#ibcon#*after write, iclass 39, count 0 2006.280.07:56:00.42#ibcon#*before return 0, iclass 39, count 0 2006.280.07:56:00.42#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:00.42#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:00.42#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:56:00.42#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:56:00.42$vc4f8/valo=5,652.99 2006.280.07:56:00.42#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:56:00.42#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:56:00.42#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:00.42#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:00.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:00.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:00.42#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:56:00.42#ibcon#first serial, iclass 3, count 0 2006.280.07:56:00.42#ibcon#enter sib2, iclass 3, count 0 2006.280.07:56:00.42#ibcon#flushed, iclass 3, count 0 2006.280.07:56:00.42#ibcon#about to write, iclass 3, count 0 2006.280.07:56:00.42#ibcon#wrote, iclass 3, count 0 2006.280.07:56:00.42#ibcon#about to read 3, iclass 3, count 0 2006.280.07:56:00.44#ibcon#read 3, iclass 3, count 0 2006.280.07:56:00.44#ibcon#about to read 4, iclass 3, count 0 2006.280.07:56:00.44#ibcon#read 4, iclass 3, count 0 2006.280.07:56:00.44#ibcon#about to read 5, iclass 3, count 0 2006.280.07:56:00.44#ibcon#read 5, iclass 3, count 0 2006.280.07:56:00.44#ibcon#about to read 6, iclass 3, count 0 2006.280.07:56:00.44#ibcon#read 6, iclass 3, count 0 2006.280.07:56:00.44#ibcon#end of sib2, iclass 3, count 0 2006.280.07:56:00.44#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:56:00.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:56:00.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:56:00.44#ibcon#*before write, iclass 3, count 0 2006.280.07:56:00.47#ibcon#enter sib2, iclass 3, count 0 2006.280.07:56:00.47#ibcon#flushed, iclass 3, count 0 2006.280.07:56:00.47#ibcon#about to write, iclass 3, count 0 2006.280.07:56:00.47#ibcon#wrote, iclass 3, count 0 2006.280.07:56:00.47#ibcon#about to read 3, iclass 3, count 0 2006.280.07:56:00.51#ibcon#read 3, iclass 3, count 0 2006.280.07:56:00.51#ibcon#about to read 4, iclass 3, count 0 2006.280.07:56:00.51#ibcon#read 4, iclass 3, count 0 2006.280.07:56:00.51#ibcon#about to read 5, iclass 3, count 0 2006.280.07:56:00.51#ibcon#read 5, iclass 3, count 0 2006.280.07:56:00.51#ibcon#about to read 6, iclass 3, count 0 2006.280.07:56:00.51#ibcon#read 6, iclass 3, count 0 2006.280.07:56:00.51#ibcon#end of sib2, iclass 3, count 0 2006.280.07:56:00.51#ibcon#*after write, iclass 3, count 0 2006.280.07:56:00.51#ibcon#*before return 0, iclass 3, count 0 2006.280.07:56:00.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:00.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:00.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:56:00.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:56:00.51$vc4f8/va=5,7 2006.280.07:56:00.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:56:00.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:56:00.51#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:00.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:00.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:00.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:00.55#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:56:00.55#ibcon#first serial, iclass 5, count 2 2006.280.07:56:00.55#ibcon#enter sib2, iclass 5, count 2 2006.280.07:56:00.55#ibcon#flushed, iclass 5, count 2 2006.280.07:56:00.55#ibcon#about to write, iclass 5, count 2 2006.280.07:56:00.55#ibcon#wrote, iclass 5, count 2 2006.280.07:56:00.55#ibcon#about to read 3, iclass 5, count 2 2006.280.07:56:00.56#ibcon#read 3, iclass 5, count 2 2006.280.07:56:00.56#ibcon#about to read 4, iclass 5, count 2 2006.280.07:56:00.56#ibcon#read 4, iclass 5, count 2 2006.280.07:56:00.56#ibcon#about to read 5, iclass 5, count 2 2006.280.07:56:00.56#ibcon#read 5, iclass 5, count 2 2006.280.07:56:00.56#ibcon#about to read 6, iclass 5, count 2 2006.280.07:56:00.56#ibcon#read 6, iclass 5, count 2 2006.280.07:56:00.56#ibcon#end of sib2, iclass 5, count 2 2006.280.07:56:00.56#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:56:00.56#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:56:00.57#ibcon#[25=AT05-07\r\n] 2006.280.07:56:00.57#ibcon#*before write, iclass 5, count 2 2006.280.07:56:00.57#ibcon#enter sib2, iclass 5, count 2 2006.280.07:56:00.57#ibcon#flushed, iclass 5, count 2 2006.280.07:56:00.57#ibcon#about to write, iclass 5, count 2 2006.280.07:56:00.57#ibcon#wrote, iclass 5, count 2 2006.280.07:56:00.57#ibcon#about to read 3, iclass 5, count 2 2006.280.07:56:00.60#ibcon#read 3, iclass 5, count 2 2006.280.07:56:00.60#ibcon#about to read 4, iclass 5, count 2 2006.280.07:56:00.60#ibcon#read 4, iclass 5, count 2 2006.280.07:56:00.60#ibcon#about to read 5, iclass 5, count 2 2006.280.07:56:00.60#ibcon#read 5, iclass 5, count 2 2006.280.07:56:00.60#ibcon#about to read 6, iclass 5, count 2 2006.280.07:56:00.60#ibcon#read 6, iclass 5, count 2 2006.280.07:56:00.60#ibcon#end of sib2, iclass 5, count 2 2006.280.07:56:00.60#ibcon#*after write, iclass 5, count 2 2006.280.07:56:00.60#ibcon#*before return 0, iclass 5, count 2 2006.280.07:56:00.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:00.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:00.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:56:00.60#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:00.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:00.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:00.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:00.72#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:56:00.72#ibcon#first serial, iclass 5, count 0 2006.280.07:56:00.72#ibcon#enter sib2, iclass 5, count 0 2006.280.07:56:00.72#ibcon#flushed, iclass 5, count 0 2006.280.07:56:00.72#ibcon#about to write, iclass 5, count 0 2006.280.07:56:00.72#ibcon#wrote, iclass 5, count 0 2006.280.07:56:00.72#ibcon#about to read 3, iclass 5, count 0 2006.280.07:56:00.74#ibcon#read 3, iclass 5, count 0 2006.280.07:56:00.74#ibcon#about to read 4, iclass 5, count 0 2006.280.07:56:00.74#ibcon#read 4, iclass 5, count 0 2006.280.07:56:00.74#ibcon#about to read 5, iclass 5, count 0 2006.280.07:56:00.74#ibcon#read 5, iclass 5, count 0 2006.280.07:56:00.74#ibcon#about to read 6, iclass 5, count 0 2006.280.07:56:00.74#ibcon#read 6, iclass 5, count 0 2006.280.07:56:00.74#ibcon#end of sib2, iclass 5, count 0 2006.280.07:56:00.74#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:56:00.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:56:00.74#ibcon#[25=USB\r\n] 2006.280.07:56:00.74#ibcon#*before write, iclass 5, count 0 2006.280.07:56:00.74#ibcon#enter sib2, iclass 5, count 0 2006.280.07:56:00.74#ibcon#flushed, iclass 5, count 0 2006.280.07:56:00.74#ibcon#about to write, iclass 5, count 0 2006.280.07:56:00.74#ibcon#wrote, iclass 5, count 0 2006.280.07:56:00.74#ibcon#about to read 3, iclass 5, count 0 2006.280.07:56:00.77#ibcon#read 3, iclass 5, count 0 2006.280.07:56:00.77#ibcon#about to read 4, iclass 5, count 0 2006.280.07:56:00.77#ibcon#read 4, iclass 5, count 0 2006.280.07:56:00.77#ibcon#about to read 5, iclass 5, count 0 2006.280.07:56:00.77#ibcon#read 5, iclass 5, count 0 2006.280.07:56:00.77#ibcon#about to read 6, iclass 5, count 0 2006.280.07:56:00.77#ibcon#read 6, iclass 5, count 0 2006.280.07:56:00.77#ibcon#end of sib2, iclass 5, count 0 2006.280.07:56:00.77#ibcon#*after write, iclass 5, count 0 2006.280.07:56:00.77#ibcon#*before return 0, iclass 5, count 0 2006.280.07:56:00.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:00.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:00.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:56:00.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:56:00.77$vc4f8/valo=6,772.99 2006.280.07:56:00.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:56:00.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:56:00.77#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:00.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:00.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:00.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:00.77#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:56:00.77#ibcon#first serial, iclass 7, count 0 2006.280.07:56:00.77#ibcon#enter sib2, iclass 7, count 0 2006.280.07:56:00.77#ibcon#flushed, iclass 7, count 0 2006.280.07:56:00.77#ibcon#about to write, iclass 7, count 0 2006.280.07:56:00.77#ibcon#wrote, iclass 7, count 0 2006.280.07:56:00.77#ibcon#about to read 3, iclass 7, count 0 2006.280.07:56:00.79#ibcon#read 3, iclass 7, count 0 2006.280.07:56:00.79#ibcon#about to read 4, iclass 7, count 0 2006.280.07:56:00.79#ibcon#read 4, iclass 7, count 0 2006.280.07:56:00.79#ibcon#about to read 5, iclass 7, count 0 2006.280.07:56:00.79#ibcon#read 5, iclass 7, count 0 2006.280.07:56:00.79#ibcon#about to read 6, iclass 7, count 0 2006.280.07:56:00.79#ibcon#read 6, iclass 7, count 0 2006.280.07:56:00.79#ibcon#end of sib2, iclass 7, count 0 2006.280.07:56:00.79#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:56:00.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:56:00.82#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:56:00.82#ibcon#*before write, iclass 7, count 0 2006.280.07:56:00.82#ibcon#enter sib2, iclass 7, count 0 2006.280.07:56:00.82#ibcon#flushed, iclass 7, count 0 2006.280.07:56:00.82#ibcon#about to write, iclass 7, count 0 2006.280.07:56:00.82#ibcon#wrote, iclass 7, count 0 2006.280.07:56:00.82#ibcon#about to read 3, iclass 7, count 0 2006.280.07:56:00.86#ibcon#read 3, iclass 7, count 0 2006.280.07:56:00.86#ibcon#about to read 4, iclass 7, count 0 2006.280.07:56:00.86#ibcon#read 4, iclass 7, count 0 2006.280.07:56:00.86#ibcon#about to read 5, iclass 7, count 0 2006.280.07:56:00.86#ibcon#read 5, iclass 7, count 0 2006.280.07:56:00.86#ibcon#about to read 6, iclass 7, count 0 2006.280.07:56:00.86#ibcon#read 6, iclass 7, count 0 2006.280.07:56:00.86#ibcon#end of sib2, iclass 7, count 0 2006.280.07:56:00.86#ibcon#*after write, iclass 7, count 0 2006.280.07:56:00.86#ibcon#*before return 0, iclass 7, count 0 2006.280.07:56:00.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:00.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:00.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:56:00.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:56:00.86$vc4f8/va=6,6 2006.280.07:56:00.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:56:00.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:56:00.86#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:00.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:00.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:00.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:00.89#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:56:00.89#ibcon#first serial, iclass 11, count 2 2006.280.07:56:00.89#ibcon#enter sib2, iclass 11, count 2 2006.280.07:56:00.89#ibcon#flushed, iclass 11, count 2 2006.280.07:56:00.89#ibcon#about to write, iclass 11, count 2 2006.280.07:56:00.89#ibcon#wrote, iclass 11, count 2 2006.280.07:56:00.89#ibcon#about to read 3, iclass 11, count 2 2006.280.07:56:00.91#ibcon#read 3, iclass 11, count 2 2006.280.07:56:00.91#ibcon#about to read 4, iclass 11, count 2 2006.280.07:56:00.91#ibcon#read 4, iclass 11, count 2 2006.280.07:56:00.91#ibcon#about to read 5, iclass 11, count 2 2006.280.07:56:00.91#ibcon#read 5, iclass 11, count 2 2006.280.07:56:00.91#ibcon#about to read 6, iclass 11, count 2 2006.280.07:56:00.91#ibcon#read 6, iclass 11, count 2 2006.280.07:56:00.91#ibcon#end of sib2, iclass 11, count 2 2006.280.07:56:00.91#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:56:00.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:56:00.93#ibcon#[25=AT06-06\r\n] 2006.280.07:56:00.93#ibcon#*before write, iclass 11, count 2 2006.280.07:56:00.93#ibcon#enter sib2, iclass 11, count 2 2006.280.07:56:00.93#ibcon#flushed, iclass 11, count 2 2006.280.07:56:00.93#ibcon#about to write, iclass 11, count 2 2006.280.07:56:00.93#ibcon#wrote, iclass 11, count 2 2006.280.07:56:00.93#ibcon#about to read 3, iclass 11, count 2 2006.280.07:56:00.96#ibcon#read 3, iclass 11, count 2 2006.280.07:56:00.96#ibcon#about to read 4, iclass 11, count 2 2006.280.07:56:00.96#ibcon#read 4, iclass 11, count 2 2006.280.07:56:00.96#ibcon#about to read 5, iclass 11, count 2 2006.280.07:56:00.96#ibcon#read 5, iclass 11, count 2 2006.280.07:56:00.96#ibcon#about to read 6, iclass 11, count 2 2006.280.07:56:00.96#ibcon#read 6, iclass 11, count 2 2006.280.07:56:00.96#ibcon#end of sib2, iclass 11, count 2 2006.280.07:56:00.96#ibcon#*after write, iclass 11, count 2 2006.280.07:56:00.96#ibcon#*before return 0, iclass 11, count 2 2006.280.07:56:00.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:00.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:00.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:56:00.96#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:00.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:01.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:01.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:01.08#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:56:01.08#ibcon#first serial, iclass 11, count 0 2006.280.07:56:01.08#ibcon#enter sib2, iclass 11, count 0 2006.280.07:56:01.08#ibcon#flushed, iclass 11, count 0 2006.280.07:56:01.08#ibcon#about to write, iclass 11, count 0 2006.280.07:56:01.08#ibcon#wrote, iclass 11, count 0 2006.280.07:56:01.08#ibcon#about to read 3, iclass 11, count 0 2006.280.07:56:01.10#ibcon#read 3, iclass 11, count 0 2006.280.07:56:01.10#ibcon#about to read 4, iclass 11, count 0 2006.280.07:56:01.10#ibcon#read 4, iclass 11, count 0 2006.280.07:56:01.10#ibcon#about to read 5, iclass 11, count 0 2006.280.07:56:01.10#ibcon#read 5, iclass 11, count 0 2006.280.07:56:01.10#ibcon#about to read 6, iclass 11, count 0 2006.280.07:56:01.10#ibcon#read 6, iclass 11, count 0 2006.280.07:56:01.10#ibcon#end of sib2, iclass 11, count 0 2006.280.07:56:01.10#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:56:01.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:56:01.10#ibcon#[25=USB\r\n] 2006.280.07:56:01.10#ibcon#*before write, iclass 11, count 0 2006.280.07:56:01.10#ibcon#enter sib2, iclass 11, count 0 2006.280.07:56:01.10#ibcon#flushed, iclass 11, count 0 2006.280.07:56:01.10#ibcon#about to write, iclass 11, count 0 2006.280.07:56:01.10#ibcon#wrote, iclass 11, count 0 2006.280.07:56:01.10#ibcon#about to read 3, iclass 11, count 0 2006.280.07:56:01.13#ibcon#read 3, iclass 11, count 0 2006.280.07:56:01.13#ibcon#about to read 4, iclass 11, count 0 2006.280.07:56:01.13#ibcon#read 4, iclass 11, count 0 2006.280.07:56:01.13#ibcon#about to read 5, iclass 11, count 0 2006.280.07:56:01.13#ibcon#read 5, iclass 11, count 0 2006.280.07:56:01.13#ibcon#about to read 6, iclass 11, count 0 2006.280.07:56:01.13#ibcon#read 6, iclass 11, count 0 2006.280.07:56:01.13#ibcon#end of sib2, iclass 11, count 0 2006.280.07:56:01.13#ibcon#*after write, iclass 11, count 0 2006.280.07:56:01.13#ibcon#*before return 0, iclass 11, count 0 2006.280.07:56:01.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:01.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:01.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:56:01.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:56:01.13$vc4f8/valo=7,832.99 2006.280.07:56:01.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:56:01.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:56:01.13#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:01.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:01.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:01.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:01.13#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:56:01.13#ibcon#first serial, iclass 13, count 0 2006.280.07:56:01.13#ibcon#enter sib2, iclass 13, count 0 2006.280.07:56:01.13#ibcon#flushed, iclass 13, count 0 2006.280.07:56:01.13#ibcon#about to write, iclass 13, count 0 2006.280.07:56:01.13#ibcon#wrote, iclass 13, count 0 2006.280.07:56:01.13#ibcon#about to read 3, iclass 13, count 0 2006.280.07:56:01.15#ibcon#read 3, iclass 13, count 0 2006.280.07:56:01.17#ibcon#about to read 4, iclass 13, count 0 2006.280.07:56:01.17#ibcon#read 4, iclass 13, count 0 2006.280.07:56:01.17#ibcon#about to read 5, iclass 13, count 0 2006.280.07:56:01.17#ibcon#read 5, iclass 13, count 0 2006.280.07:56:01.17#ibcon#about to read 6, iclass 13, count 0 2006.280.07:56:01.17#ibcon#read 6, iclass 13, count 0 2006.280.07:56:01.17#ibcon#end of sib2, iclass 13, count 0 2006.280.07:56:01.17#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:56:01.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:56:01.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:56:01.17#ibcon#*before write, iclass 13, count 0 2006.280.07:56:01.17#ibcon#enter sib2, iclass 13, count 0 2006.280.07:56:01.17#ibcon#flushed, iclass 13, count 0 2006.280.07:56:01.17#ibcon#about to write, iclass 13, count 0 2006.280.07:56:01.17#ibcon#wrote, iclass 13, count 0 2006.280.07:56:01.17#ibcon#about to read 3, iclass 13, count 0 2006.280.07:56:01.21#ibcon#read 3, iclass 13, count 0 2006.280.07:56:01.21#ibcon#about to read 4, iclass 13, count 0 2006.280.07:56:01.21#ibcon#read 4, iclass 13, count 0 2006.280.07:56:01.21#ibcon#about to read 5, iclass 13, count 0 2006.280.07:56:01.21#ibcon#read 5, iclass 13, count 0 2006.280.07:56:01.21#ibcon#about to read 6, iclass 13, count 0 2006.280.07:56:01.21#ibcon#read 6, iclass 13, count 0 2006.280.07:56:01.21#ibcon#end of sib2, iclass 13, count 0 2006.280.07:56:01.21#ibcon#*after write, iclass 13, count 0 2006.280.07:56:01.21#ibcon#*before return 0, iclass 13, count 0 2006.280.07:56:01.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:01.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:01.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:56:01.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:56:01.21$vc4f8/va=7,6 2006.280.07:56:01.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.07:56:01.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.07:56:01.21#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:01.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:01.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:01.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:01.25#ibcon#enter wrdev, iclass 15, count 2 2006.280.07:56:01.25#ibcon#first serial, iclass 15, count 2 2006.280.07:56:01.25#ibcon#enter sib2, iclass 15, count 2 2006.280.07:56:01.25#ibcon#flushed, iclass 15, count 2 2006.280.07:56:01.25#ibcon#about to write, iclass 15, count 2 2006.280.07:56:01.25#ibcon#wrote, iclass 15, count 2 2006.280.07:56:01.25#ibcon#about to read 3, iclass 15, count 2 2006.280.07:56:01.27#ibcon#read 3, iclass 15, count 2 2006.280.07:56:01.27#ibcon#about to read 4, iclass 15, count 2 2006.280.07:56:01.27#ibcon#read 4, iclass 15, count 2 2006.280.07:56:01.27#ibcon#about to read 5, iclass 15, count 2 2006.280.07:56:01.27#ibcon#read 5, iclass 15, count 2 2006.280.07:56:01.27#ibcon#about to read 6, iclass 15, count 2 2006.280.07:56:01.27#ibcon#read 6, iclass 15, count 2 2006.280.07:56:01.27#ibcon#end of sib2, iclass 15, count 2 2006.280.07:56:01.27#ibcon#*mode == 0, iclass 15, count 2 2006.280.07:56:01.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.07:56:01.29#ibcon#[25=AT07-06\r\n] 2006.280.07:56:01.29#ibcon#*before write, iclass 15, count 2 2006.280.07:56:01.29#ibcon#enter sib2, iclass 15, count 2 2006.280.07:56:01.29#ibcon#flushed, iclass 15, count 2 2006.280.07:56:01.29#ibcon#about to write, iclass 15, count 2 2006.280.07:56:01.29#ibcon#wrote, iclass 15, count 2 2006.280.07:56:01.29#ibcon#about to read 3, iclass 15, count 2 2006.280.07:56:01.32#ibcon#read 3, iclass 15, count 2 2006.280.07:56:01.32#ibcon#about to read 4, iclass 15, count 2 2006.280.07:56:01.32#ibcon#read 4, iclass 15, count 2 2006.280.07:56:01.32#ibcon#about to read 5, iclass 15, count 2 2006.280.07:56:01.32#ibcon#read 5, iclass 15, count 2 2006.280.07:56:01.32#ibcon#about to read 6, iclass 15, count 2 2006.280.07:56:01.32#ibcon#read 6, iclass 15, count 2 2006.280.07:56:01.32#ibcon#end of sib2, iclass 15, count 2 2006.280.07:56:01.32#ibcon#*after write, iclass 15, count 2 2006.280.07:56:01.32#ibcon#*before return 0, iclass 15, count 2 2006.280.07:56:01.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:01.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:01.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.07:56:01.32#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:01.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:56:01.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:56:01.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:56:01.44#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:56:01.44#ibcon#first serial, iclass 15, count 0 2006.280.07:56:01.44#ibcon#enter sib2, iclass 15, count 0 2006.280.07:56:01.44#ibcon#flushed, iclass 15, count 0 2006.280.07:56:01.44#ibcon#about to write, iclass 15, count 0 2006.280.07:56:01.44#ibcon#wrote, iclass 15, count 0 2006.280.07:56:01.44#ibcon#about to read 3, iclass 15, count 0 2006.280.07:56:01.47#ibcon#read 3, iclass 15, count 0 2006.280.07:56:01.47#ibcon#about to read 4, iclass 15, count 0 2006.280.07:56:01.47#ibcon#read 4, iclass 15, count 0 2006.280.07:56:01.47#ibcon#about to read 5, iclass 15, count 0 2006.280.07:56:01.47#ibcon#read 5, iclass 15, count 0 2006.280.07:56:01.47#ibcon#about to read 6, iclass 15, count 0 2006.280.07:56:01.47#ibcon#read 6, iclass 15, count 0 2006.280.07:56:01.47#ibcon#end of sib2, iclass 15, count 0 2006.280.07:56:01.47#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:56:01.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:56:01.47#ibcon#[25=USB\r\n] 2006.280.07:56:01.47#ibcon#*before write, iclass 15, count 0 2006.280.07:56:01.47#ibcon#enter sib2, iclass 15, count 0 2006.280.07:56:01.47#ibcon#flushed, iclass 15, count 0 2006.280.07:56:01.47#ibcon#about to write, iclass 15, count 0 2006.280.07:56:01.47#ibcon#wrote, iclass 15, count 0 2006.280.07:56:01.47#ibcon#about to read 3, iclass 15, count 0 2006.280.07:56:01.49#ibcon#read 3, iclass 15, count 0 2006.280.07:56:01.49#ibcon#about to read 4, iclass 15, count 0 2006.280.07:56:01.49#ibcon#read 4, iclass 15, count 0 2006.280.07:56:01.49#ibcon#about to read 5, iclass 15, count 0 2006.280.07:56:01.49#ibcon#read 5, iclass 15, count 0 2006.280.07:56:01.49#ibcon#about to read 6, iclass 15, count 0 2006.280.07:56:01.49#ibcon#read 6, iclass 15, count 0 2006.280.07:56:01.49#ibcon#end of sib2, iclass 15, count 0 2006.280.07:56:01.49#ibcon#*after write, iclass 15, count 0 2006.280.07:56:01.49#ibcon#*before return 0, iclass 15, count 0 2006.280.07:56:01.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:56:01.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.07:56:01.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:56:01.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:56:01.49$vc4f8/valo=8,852.99 2006.280.07:56:01.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.07:56:01.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.07:56:01.49#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:01.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:56:01.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:56:01.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:56:01.49#ibcon#enter wrdev, iclass 17, count 0 2006.280.07:56:01.49#ibcon#first serial, iclass 17, count 0 2006.280.07:56:01.49#ibcon#enter sib2, iclass 17, count 0 2006.280.07:56:01.49#ibcon#flushed, iclass 17, count 0 2006.280.07:56:01.49#ibcon#about to write, iclass 17, count 0 2006.280.07:56:01.49#ibcon#wrote, iclass 17, count 0 2006.280.07:56:01.49#ibcon#about to read 3, iclass 17, count 0 2006.280.07:56:01.51#ibcon#read 3, iclass 17, count 0 2006.280.07:56:01.52#ibcon#about to read 4, iclass 17, count 0 2006.280.07:56:01.52#ibcon#read 4, iclass 17, count 0 2006.280.07:56:01.52#ibcon#about to read 5, iclass 17, count 0 2006.280.07:56:01.52#ibcon#read 5, iclass 17, count 0 2006.280.07:56:01.52#ibcon#about to read 6, iclass 17, count 0 2006.280.07:56:01.52#ibcon#read 6, iclass 17, count 0 2006.280.07:56:01.52#ibcon#end of sib2, iclass 17, count 0 2006.280.07:56:01.52#ibcon#*mode == 0, iclass 17, count 0 2006.280.07:56:01.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.07:56:01.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:56:01.52#ibcon#*before write, iclass 17, count 0 2006.280.07:56:01.52#ibcon#enter sib2, iclass 17, count 0 2006.280.07:56:01.52#ibcon#flushed, iclass 17, count 0 2006.280.07:56:01.52#ibcon#about to write, iclass 17, count 0 2006.280.07:56:01.52#ibcon#wrote, iclass 17, count 0 2006.280.07:56:01.52#ibcon#about to read 3, iclass 17, count 0 2006.280.07:56:01.56#ibcon#read 3, iclass 17, count 0 2006.280.07:56:01.56#ibcon#about to read 4, iclass 17, count 0 2006.280.07:56:01.56#ibcon#read 4, iclass 17, count 0 2006.280.07:56:01.56#ibcon#about to read 5, iclass 17, count 0 2006.280.07:56:01.56#ibcon#read 5, iclass 17, count 0 2006.280.07:56:01.56#ibcon#about to read 6, iclass 17, count 0 2006.280.07:56:01.56#ibcon#read 6, iclass 17, count 0 2006.280.07:56:01.56#ibcon#end of sib2, iclass 17, count 0 2006.280.07:56:01.56#ibcon#*after write, iclass 17, count 0 2006.280.07:56:01.56#ibcon#*before return 0, iclass 17, count 0 2006.280.07:56:01.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:56:01.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.07:56:01.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.07:56:01.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.07:56:01.56$vc4f8/va=8,6 2006.280.07:56:01.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.07:56:01.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.07:56:01.56#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:01.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:56:01.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:56:01.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:56:01.61#ibcon#enter wrdev, iclass 19, count 2 2006.280.07:56:01.61#ibcon#first serial, iclass 19, count 2 2006.280.07:56:01.61#ibcon#enter sib2, iclass 19, count 2 2006.280.07:56:01.61#ibcon#flushed, iclass 19, count 2 2006.280.07:56:01.61#ibcon#about to write, iclass 19, count 2 2006.280.07:56:01.61#ibcon#wrote, iclass 19, count 2 2006.280.07:56:01.61#ibcon#about to read 3, iclass 19, count 2 2006.280.07:56:01.63#ibcon#read 3, iclass 19, count 2 2006.280.07:56:01.63#ibcon#about to read 4, iclass 19, count 2 2006.280.07:56:01.63#ibcon#read 4, iclass 19, count 2 2006.280.07:56:01.63#ibcon#about to read 5, iclass 19, count 2 2006.280.07:56:01.63#ibcon#read 5, iclass 19, count 2 2006.280.07:56:01.63#ibcon#about to read 6, iclass 19, count 2 2006.280.07:56:01.63#ibcon#read 6, iclass 19, count 2 2006.280.07:56:01.63#ibcon#end of sib2, iclass 19, count 2 2006.280.07:56:01.63#ibcon#*mode == 0, iclass 19, count 2 2006.280.07:56:01.63#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.07:56:01.63#ibcon#[25=AT08-06\r\n] 2006.280.07:56:01.63#ibcon#*before write, iclass 19, count 2 2006.280.07:56:01.63#ibcon#enter sib2, iclass 19, count 2 2006.280.07:56:01.63#ibcon#flushed, iclass 19, count 2 2006.280.07:56:01.63#ibcon#about to write, iclass 19, count 2 2006.280.07:56:01.63#ibcon#wrote, iclass 19, count 2 2006.280.07:56:01.63#ibcon#about to read 3, iclass 19, count 2 2006.280.07:56:01.66#ibcon#read 3, iclass 19, count 2 2006.280.07:56:01.66#ibcon#about to read 4, iclass 19, count 2 2006.280.07:56:01.66#ibcon#read 4, iclass 19, count 2 2006.280.07:56:01.66#ibcon#about to read 5, iclass 19, count 2 2006.280.07:56:01.66#ibcon#read 5, iclass 19, count 2 2006.280.07:56:01.66#ibcon#about to read 6, iclass 19, count 2 2006.280.07:56:01.66#ibcon#read 6, iclass 19, count 2 2006.280.07:56:01.66#ibcon#end of sib2, iclass 19, count 2 2006.280.07:56:01.66#ibcon#*after write, iclass 19, count 2 2006.280.07:56:01.66#ibcon#*before return 0, iclass 19, count 2 2006.280.07:56:01.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:56:01.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.07:56:01.66#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.07:56:01.66#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:01.66#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:56:01.74#abcon#<5=/14 1.7 4.9 21.03 59 987.0\r\n> 2006.280.07:56:01.76#abcon#{5=INTERFACE CLEAR} 2006.280.07:56:01.78#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:56:01.78#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:56:01.78#ibcon#enter wrdev, iclass 19, count 0 2006.280.07:56:01.78#ibcon#first serial, iclass 19, count 0 2006.280.07:56:01.78#ibcon#enter sib2, iclass 19, count 0 2006.280.07:56:01.78#ibcon#flushed, iclass 19, count 0 2006.280.07:56:01.78#ibcon#about to write, iclass 19, count 0 2006.280.07:56:01.78#ibcon#wrote, iclass 19, count 0 2006.280.07:56:01.78#ibcon#about to read 3, iclass 19, count 0 2006.280.07:56:01.80#ibcon#read 3, iclass 19, count 0 2006.280.07:56:01.80#ibcon#about to read 4, iclass 19, count 0 2006.280.07:56:01.80#ibcon#read 4, iclass 19, count 0 2006.280.07:56:01.80#ibcon#about to read 5, iclass 19, count 0 2006.280.07:56:01.80#ibcon#read 5, iclass 19, count 0 2006.280.07:56:01.80#ibcon#about to read 6, iclass 19, count 0 2006.280.07:56:01.80#ibcon#read 6, iclass 19, count 0 2006.280.07:56:01.80#ibcon#end of sib2, iclass 19, count 0 2006.280.07:56:01.80#ibcon#*mode == 0, iclass 19, count 0 2006.280.07:56:01.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.07:56:01.80#ibcon#[25=USB\r\n] 2006.280.07:56:01.80#ibcon#*before write, iclass 19, count 0 2006.280.07:56:01.80#ibcon#enter sib2, iclass 19, count 0 2006.280.07:56:01.80#ibcon#flushed, iclass 19, count 0 2006.280.07:56:01.80#ibcon#about to write, iclass 19, count 0 2006.280.07:56:01.80#ibcon#wrote, iclass 19, count 0 2006.280.07:56:01.80#ibcon#about to read 3, iclass 19, count 0 2006.280.07:56:01.83#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:56:01.83#ibcon#read 3, iclass 19, count 0 2006.280.07:56:01.83#ibcon#about to read 4, iclass 19, count 0 2006.280.07:56:01.83#ibcon#read 4, iclass 19, count 0 2006.280.07:56:01.83#ibcon#about to read 5, iclass 19, count 0 2006.280.07:56:01.83#ibcon#read 5, iclass 19, count 0 2006.280.07:56:01.83#ibcon#about to read 6, iclass 19, count 0 2006.280.07:56:01.83#ibcon#read 6, iclass 19, count 0 2006.280.07:56:01.83#ibcon#end of sib2, iclass 19, count 0 2006.280.07:56:01.83#ibcon#*after write, iclass 19, count 0 2006.280.07:56:01.83#ibcon#*before return 0, iclass 19, count 0 2006.280.07:56:01.83#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:56:01.83#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.07:56:01.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.07:56:01.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.07:56:01.83$vc4f8/vblo=1,632.99 2006.280.07:56:01.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.07:56:01.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.07:56:01.83#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:01.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:56:01.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:56:01.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:56:01.83#ibcon#enter wrdev, iclass 25, count 0 2006.280.07:56:01.83#ibcon#first serial, iclass 25, count 0 2006.280.07:56:01.83#ibcon#enter sib2, iclass 25, count 0 2006.280.07:56:01.83#ibcon#flushed, iclass 25, count 0 2006.280.07:56:01.83#ibcon#about to write, iclass 25, count 0 2006.280.07:56:01.83#ibcon#wrote, iclass 25, count 0 2006.280.07:56:01.83#ibcon#about to read 3, iclass 25, count 0 2006.280.07:56:01.85#ibcon#read 3, iclass 25, count 0 2006.280.07:56:01.85#ibcon#about to read 4, iclass 25, count 0 2006.280.07:56:01.85#ibcon#read 4, iclass 25, count 0 2006.280.07:56:01.85#ibcon#about to read 5, iclass 25, count 0 2006.280.07:56:01.85#ibcon#read 5, iclass 25, count 0 2006.280.07:56:01.85#ibcon#about to read 6, iclass 25, count 0 2006.280.07:56:01.85#ibcon#read 6, iclass 25, count 0 2006.280.07:56:01.85#ibcon#end of sib2, iclass 25, count 0 2006.280.07:56:01.85#ibcon#*mode == 0, iclass 25, count 0 2006.280.07:56:01.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.07:56:01.85#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:56:01.85#ibcon#*before write, iclass 25, count 0 2006.280.07:56:01.85#ibcon#enter sib2, iclass 25, count 0 2006.280.07:56:01.85#ibcon#flushed, iclass 25, count 0 2006.280.07:56:01.85#ibcon#about to write, iclass 25, count 0 2006.280.07:56:01.85#ibcon#wrote, iclass 25, count 0 2006.280.07:56:01.85#ibcon#about to read 3, iclass 25, count 0 2006.280.07:56:01.89#ibcon#read 3, iclass 25, count 0 2006.280.07:56:01.89#ibcon#about to read 4, iclass 25, count 0 2006.280.07:56:01.89#ibcon#read 4, iclass 25, count 0 2006.280.07:56:01.89#ibcon#about to read 5, iclass 25, count 0 2006.280.07:56:01.89#ibcon#read 5, iclass 25, count 0 2006.280.07:56:01.89#ibcon#about to read 6, iclass 25, count 0 2006.280.07:56:01.90#ibcon#read 6, iclass 25, count 0 2006.280.07:56:01.90#ibcon#end of sib2, iclass 25, count 0 2006.280.07:56:01.90#ibcon#*after write, iclass 25, count 0 2006.280.07:56:01.90#ibcon#*before return 0, iclass 25, count 0 2006.280.07:56:01.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:56:01.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.07:56:01.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.07:56:01.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.07:56:01.90$vc4f8/vb=1,4 2006.280.07:56:01.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.07:56:01.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.07:56:01.90#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:01.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:56:01.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:56:01.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:56:01.90#ibcon#enter wrdev, iclass 27, count 2 2006.280.07:56:01.90#ibcon#first serial, iclass 27, count 2 2006.280.07:56:01.90#ibcon#enter sib2, iclass 27, count 2 2006.280.07:56:01.90#ibcon#flushed, iclass 27, count 2 2006.280.07:56:01.90#ibcon#about to write, iclass 27, count 2 2006.280.07:56:01.90#ibcon#wrote, iclass 27, count 2 2006.280.07:56:01.90#ibcon#about to read 3, iclass 27, count 2 2006.280.07:56:01.92#ibcon#read 3, iclass 27, count 2 2006.280.07:56:01.92#ibcon#about to read 4, iclass 27, count 2 2006.280.07:56:01.92#ibcon#read 4, iclass 27, count 2 2006.280.07:56:01.92#ibcon#about to read 5, iclass 27, count 2 2006.280.07:56:01.92#ibcon#read 5, iclass 27, count 2 2006.280.07:56:01.92#ibcon#about to read 6, iclass 27, count 2 2006.280.07:56:01.92#ibcon#read 6, iclass 27, count 2 2006.280.07:56:01.92#ibcon#end of sib2, iclass 27, count 2 2006.280.07:56:01.92#ibcon#*mode == 0, iclass 27, count 2 2006.280.07:56:01.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.07:56:01.92#ibcon#[27=AT01-04\r\n] 2006.280.07:56:01.92#ibcon#*before write, iclass 27, count 2 2006.280.07:56:01.98#ibcon#enter sib2, iclass 27, count 2 2006.280.07:56:01.98#ibcon#flushed, iclass 27, count 2 2006.280.07:56:01.98#ibcon#about to write, iclass 27, count 2 2006.280.07:56:01.98#ibcon#wrote, iclass 27, count 2 2006.280.07:56:01.98#ibcon#about to read 3, iclass 27, count 2 2006.280.07:56:02.01#ibcon#read 3, iclass 27, count 2 2006.280.07:56:02.01#ibcon#about to read 4, iclass 27, count 2 2006.280.07:56:02.01#ibcon#read 4, iclass 27, count 2 2006.280.07:56:02.01#ibcon#about to read 5, iclass 27, count 2 2006.280.07:56:02.01#ibcon#read 5, iclass 27, count 2 2006.280.07:56:02.01#ibcon#about to read 6, iclass 27, count 2 2006.280.07:56:02.01#ibcon#read 6, iclass 27, count 2 2006.280.07:56:02.01#ibcon#end of sib2, iclass 27, count 2 2006.280.07:56:02.01#ibcon#*after write, iclass 27, count 2 2006.280.07:56:02.01#ibcon#*before return 0, iclass 27, count 2 2006.280.07:56:02.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:56:02.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.07:56:02.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.07:56:02.01#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:02.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:56:02.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:56:02.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:56:02.13#ibcon#enter wrdev, iclass 27, count 0 2006.280.07:56:02.13#ibcon#first serial, iclass 27, count 0 2006.280.07:56:02.13#ibcon#enter sib2, iclass 27, count 0 2006.280.07:56:02.13#ibcon#flushed, iclass 27, count 0 2006.280.07:56:02.13#ibcon#about to write, iclass 27, count 0 2006.280.07:56:02.13#ibcon#wrote, iclass 27, count 0 2006.280.07:56:02.13#ibcon#about to read 3, iclass 27, count 0 2006.280.07:56:02.15#ibcon#read 3, iclass 27, count 0 2006.280.07:56:02.15#ibcon#about to read 4, iclass 27, count 0 2006.280.07:56:02.15#ibcon#read 4, iclass 27, count 0 2006.280.07:56:02.15#ibcon#about to read 5, iclass 27, count 0 2006.280.07:56:02.15#ibcon#read 5, iclass 27, count 0 2006.280.07:56:02.15#ibcon#about to read 6, iclass 27, count 0 2006.280.07:56:02.15#ibcon#read 6, iclass 27, count 0 2006.280.07:56:02.15#ibcon#end of sib2, iclass 27, count 0 2006.280.07:56:02.15#ibcon#*mode == 0, iclass 27, count 0 2006.280.07:56:02.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.07:56:02.15#ibcon#[27=USB\r\n] 2006.280.07:56:02.15#ibcon#*before write, iclass 27, count 0 2006.280.07:56:02.15#ibcon#enter sib2, iclass 27, count 0 2006.280.07:56:02.15#ibcon#flushed, iclass 27, count 0 2006.280.07:56:02.15#ibcon#about to write, iclass 27, count 0 2006.280.07:56:02.15#ibcon#wrote, iclass 27, count 0 2006.280.07:56:02.15#ibcon#about to read 3, iclass 27, count 0 2006.280.07:56:02.18#ibcon#read 3, iclass 27, count 0 2006.280.07:56:02.18#ibcon#about to read 4, iclass 27, count 0 2006.280.07:56:02.18#ibcon#read 4, iclass 27, count 0 2006.280.07:56:02.18#ibcon#about to read 5, iclass 27, count 0 2006.280.07:56:02.18#ibcon#read 5, iclass 27, count 0 2006.280.07:56:02.18#ibcon#about to read 6, iclass 27, count 0 2006.280.07:56:02.18#ibcon#read 6, iclass 27, count 0 2006.280.07:56:02.18#ibcon#end of sib2, iclass 27, count 0 2006.280.07:56:02.18#ibcon#*after write, iclass 27, count 0 2006.280.07:56:02.18#ibcon#*before return 0, iclass 27, count 0 2006.280.07:56:02.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:56:02.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.07:56:02.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.07:56:02.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.07:56:02.18$vc4f8/vblo=2,640.99 2006.280.07:56:02.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.07:56:02.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.07:56:02.18#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:02.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:56:02.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:56:02.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:56:02.18#ibcon#enter wrdev, iclass 29, count 0 2006.280.07:56:02.18#ibcon#first serial, iclass 29, count 0 2006.280.07:56:02.18#ibcon#enter sib2, iclass 29, count 0 2006.280.07:56:02.18#ibcon#flushed, iclass 29, count 0 2006.280.07:56:02.18#ibcon#about to write, iclass 29, count 0 2006.280.07:56:02.18#ibcon#wrote, iclass 29, count 0 2006.280.07:56:02.18#ibcon#about to read 3, iclass 29, count 0 2006.280.07:56:02.20#ibcon#read 3, iclass 29, count 0 2006.280.07:56:02.20#ibcon#about to read 4, iclass 29, count 0 2006.280.07:56:02.20#ibcon#read 4, iclass 29, count 0 2006.280.07:56:02.20#ibcon#about to read 5, iclass 29, count 0 2006.280.07:56:02.20#ibcon#read 5, iclass 29, count 0 2006.280.07:56:02.20#ibcon#about to read 6, iclass 29, count 0 2006.280.07:56:02.20#ibcon#read 6, iclass 29, count 0 2006.280.07:56:02.20#ibcon#end of sib2, iclass 29, count 0 2006.280.07:56:02.20#ibcon#*mode == 0, iclass 29, count 0 2006.280.07:56:02.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.07:56:02.20#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:56:02.20#ibcon#*before write, iclass 29, count 0 2006.280.07:56:02.20#ibcon#enter sib2, iclass 29, count 0 2006.280.07:56:02.20#ibcon#flushed, iclass 29, count 0 2006.280.07:56:02.20#ibcon#about to write, iclass 29, count 0 2006.280.07:56:02.20#ibcon#wrote, iclass 29, count 0 2006.280.07:56:02.20#ibcon#about to read 3, iclass 29, count 0 2006.280.07:56:02.24#ibcon#read 3, iclass 29, count 0 2006.280.07:56:02.24#ibcon#about to read 4, iclass 29, count 0 2006.280.07:56:02.24#ibcon#read 4, iclass 29, count 0 2006.280.07:56:02.24#ibcon#about to read 5, iclass 29, count 0 2006.280.07:56:02.24#ibcon#read 5, iclass 29, count 0 2006.280.07:56:02.24#ibcon#about to read 6, iclass 29, count 0 2006.280.07:56:02.24#ibcon#read 6, iclass 29, count 0 2006.280.07:56:02.24#ibcon#end of sib2, iclass 29, count 0 2006.280.07:56:02.24#ibcon#*after write, iclass 29, count 0 2006.280.07:56:02.24#ibcon#*before return 0, iclass 29, count 0 2006.280.07:56:02.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:56:02.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.07:56:02.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.07:56:02.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.07:56:02.24$vc4f8/vb=2,5 2006.280.07:56:02.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.07:56:02.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.07:56:02.24#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:02.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:56:02.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:56:02.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:56:02.30#ibcon#enter wrdev, iclass 31, count 2 2006.280.07:56:02.30#ibcon#first serial, iclass 31, count 2 2006.280.07:56:02.30#ibcon#enter sib2, iclass 31, count 2 2006.280.07:56:02.30#ibcon#flushed, iclass 31, count 2 2006.280.07:56:02.30#ibcon#about to write, iclass 31, count 2 2006.280.07:56:02.30#ibcon#wrote, iclass 31, count 2 2006.280.07:56:02.30#ibcon#about to read 3, iclass 31, count 2 2006.280.07:56:02.32#ibcon#read 3, iclass 31, count 2 2006.280.07:56:02.32#ibcon#about to read 4, iclass 31, count 2 2006.280.07:56:02.32#ibcon#read 4, iclass 31, count 2 2006.280.07:56:02.32#ibcon#about to read 5, iclass 31, count 2 2006.280.07:56:02.32#ibcon#read 5, iclass 31, count 2 2006.280.07:56:02.32#ibcon#about to read 6, iclass 31, count 2 2006.280.07:56:02.32#ibcon#read 6, iclass 31, count 2 2006.280.07:56:02.32#ibcon#end of sib2, iclass 31, count 2 2006.280.07:56:02.32#ibcon#*mode == 0, iclass 31, count 2 2006.280.07:56:02.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.07:56:02.32#ibcon#[27=AT02-05\r\n] 2006.280.07:56:02.32#ibcon#*before write, iclass 31, count 2 2006.280.07:56:02.32#ibcon#enter sib2, iclass 31, count 2 2006.280.07:56:02.32#ibcon#flushed, iclass 31, count 2 2006.280.07:56:02.32#ibcon#about to write, iclass 31, count 2 2006.280.07:56:02.32#ibcon#wrote, iclass 31, count 2 2006.280.07:56:02.32#ibcon#about to read 3, iclass 31, count 2 2006.280.07:56:02.35#ibcon#read 3, iclass 31, count 2 2006.280.07:56:02.35#ibcon#about to read 4, iclass 31, count 2 2006.280.07:56:02.35#ibcon#read 4, iclass 31, count 2 2006.280.07:56:02.35#ibcon#about to read 5, iclass 31, count 2 2006.280.07:56:02.35#ibcon#read 5, iclass 31, count 2 2006.280.07:56:02.35#ibcon#about to read 6, iclass 31, count 2 2006.280.07:56:02.35#ibcon#read 6, iclass 31, count 2 2006.280.07:56:02.35#ibcon#end of sib2, iclass 31, count 2 2006.280.07:56:02.35#ibcon#*after write, iclass 31, count 2 2006.280.07:56:02.35#ibcon#*before return 0, iclass 31, count 2 2006.280.07:56:02.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:56:02.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.07:56:02.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.07:56:02.35#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:02.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:56:02.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:56:02.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:56:02.47#ibcon#enter wrdev, iclass 31, count 0 2006.280.07:56:02.47#ibcon#first serial, iclass 31, count 0 2006.280.07:56:02.47#ibcon#enter sib2, iclass 31, count 0 2006.280.07:56:02.47#ibcon#flushed, iclass 31, count 0 2006.280.07:56:02.47#ibcon#about to write, iclass 31, count 0 2006.280.07:56:02.47#ibcon#wrote, iclass 31, count 0 2006.280.07:56:02.47#ibcon#about to read 3, iclass 31, count 0 2006.280.07:56:02.49#ibcon#read 3, iclass 31, count 0 2006.280.07:56:02.49#ibcon#about to read 4, iclass 31, count 0 2006.280.07:56:02.49#ibcon#read 4, iclass 31, count 0 2006.280.07:56:02.49#ibcon#about to read 5, iclass 31, count 0 2006.280.07:56:02.49#ibcon#read 5, iclass 31, count 0 2006.280.07:56:02.49#ibcon#about to read 6, iclass 31, count 0 2006.280.07:56:02.49#ibcon#read 6, iclass 31, count 0 2006.280.07:56:02.49#ibcon#end of sib2, iclass 31, count 0 2006.280.07:56:02.49#ibcon#*mode == 0, iclass 31, count 0 2006.280.07:56:02.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.07:56:02.49#ibcon#[27=USB\r\n] 2006.280.07:56:02.49#ibcon#*before write, iclass 31, count 0 2006.280.07:56:02.49#ibcon#enter sib2, iclass 31, count 0 2006.280.07:56:02.49#ibcon#flushed, iclass 31, count 0 2006.280.07:56:02.49#ibcon#about to write, iclass 31, count 0 2006.280.07:56:02.49#ibcon#wrote, iclass 31, count 0 2006.280.07:56:02.49#ibcon#about to read 3, iclass 31, count 0 2006.280.07:56:02.52#ibcon#read 3, iclass 31, count 0 2006.280.07:56:02.52#ibcon#about to read 4, iclass 31, count 0 2006.280.07:56:02.52#ibcon#read 4, iclass 31, count 0 2006.280.07:56:02.52#ibcon#about to read 5, iclass 31, count 0 2006.280.07:56:02.52#ibcon#read 5, iclass 31, count 0 2006.280.07:56:02.52#ibcon#about to read 6, iclass 31, count 0 2006.280.07:56:02.52#ibcon#read 6, iclass 31, count 0 2006.280.07:56:02.52#ibcon#end of sib2, iclass 31, count 0 2006.280.07:56:02.52#ibcon#*after write, iclass 31, count 0 2006.280.07:56:02.52#ibcon#*before return 0, iclass 31, count 0 2006.280.07:56:02.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:56:02.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.07:56:02.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.07:56:02.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.07:56:02.52$vc4f8/vblo=3,656.99 2006.280.07:56:02.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.07:56:02.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.07:56:02.52#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:02.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:56:02.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:56:02.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:56:02.52#ibcon#enter wrdev, iclass 33, count 0 2006.280.07:56:02.52#ibcon#first serial, iclass 33, count 0 2006.280.07:56:02.52#ibcon#enter sib2, iclass 33, count 0 2006.280.07:56:02.52#ibcon#flushed, iclass 33, count 0 2006.280.07:56:02.52#ibcon#about to write, iclass 33, count 0 2006.280.07:56:02.52#ibcon#wrote, iclass 33, count 0 2006.280.07:56:02.52#ibcon#about to read 3, iclass 33, count 0 2006.280.07:56:02.54#ibcon#read 3, iclass 33, count 0 2006.280.07:56:02.56#ibcon#about to read 4, iclass 33, count 0 2006.280.07:56:02.56#ibcon#read 4, iclass 33, count 0 2006.280.07:56:02.56#ibcon#about to read 5, iclass 33, count 0 2006.280.07:56:02.56#ibcon#read 5, iclass 33, count 0 2006.280.07:56:02.56#ibcon#about to read 6, iclass 33, count 0 2006.280.07:56:02.56#ibcon#read 6, iclass 33, count 0 2006.280.07:56:02.56#ibcon#end of sib2, iclass 33, count 0 2006.280.07:56:02.56#ibcon#*mode == 0, iclass 33, count 0 2006.280.07:56:02.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.07:56:02.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:56:02.56#ibcon#*before write, iclass 33, count 0 2006.280.07:56:02.56#ibcon#enter sib2, iclass 33, count 0 2006.280.07:56:02.56#ibcon#flushed, iclass 33, count 0 2006.280.07:56:02.56#ibcon#about to write, iclass 33, count 0 2006.280.07:56:02.56#ibcon#wrote, iclass 33, count 0 2006.280.07:56:02.56#ibcon#about to read 3, iclass 33, count 0 2006.280.07:56:02.60#ibcon#read 3, iclass 33, count 0 2006.280.07:56:02.60#ibcon#about to read 4, iclass 33, count 0 2006.280.07:56:02.63#ibcon#read 4, iclass 33, count 0 2006.280.07:56:02.63#ibcon#about to read 5, iclass 33, count 0 2006.280.07:56:02.63#ibcon#read 5, iclass 33, count 0 2006.280.07:56:02.63#ibcon#about to read 6, iclass 33, count 0 2006.280.07:56:02.63#ibcon#read 6, iclass 33, count 0 2006.280.07:56:02.63#ibcon#end of sib2, iclass 33, count 0 2006.280.07:56:02.63#ibcon#*after write, iclass 33, count 0 2006.280.07:56:02.63#ibcon#*before return 0, iclass 33, count 0 2006.280.07:56:02.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:56:02.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.07:56:02.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.07:56:02.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.07:56:02.63$vc4f8/vb=3,4 2006.280.07:56:02.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.07:56:02.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.07:56:02.63#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:02.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:56:02.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:56:02.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:56:02.63#ibcon#enter wrdev, iclass 35, count 2 2006.280.07:56:02.63#ibcon#first serial, iclass 35, count 2 2006.280.07:56:02.63#ibcon#enter sib2, iclass 35, count 2 2006.280.07:56:02.63#ibcon#flushed, iclass 35, count 2 2006.280.07:56:02.63#ibcon#about to write, iclass 35, count 2 2006.280.07:56:02.63#ibcon#wrote, iclass 35, count 2 2006.280.07:56:02.63#ibcon#about to read 3, iclass 35, count 2 2006.280.07:56:02.64#ibcon#read 3, iclass 35, count 2 2006.280.07:56:02.64#ibcon#about to read 4, iclass 35, count 2 2006.280.07:56:02.64#ibcon#read 4, iclass 35, count 2 2006.280.07:56:02.64#ibcon#about to read 5, iclass 35, count 2 2006.280.07:56:02.64#ibcon#read 5, iclass 35, count 2 2006.280.07:56:02.64#ibcon#about to read 6, iclass 35, count 2 2006.280.07:56:02.64#ibcon#read 6, iclass 35, count 2 2006.280.07:56:02.64#ibcon#end of sib2, iclass 35, count 2 2006.280.07:56:02.64#ibcon#*mode == 0, iclass 35, count 2 2006.280.07:56:02.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.07:56:02.64#ibcon#[27=AT03-04\r\n] 2006.280.07:56:02.64#ibcon#*before write, iclass 35, count 2 2006.280.07:56:02.64#ibcon#enter sib2, iclass 35, count 2 2006.280.07:56:02.64#ibcon#flushed, iclass 35, count 2 2006.280.07:56:02.64#ibcon#about to write, iclass 35, count 2 2006.280.07:56:02.64#ibcon#wrote, iclass 35, count 2 2006.280.07:56:02.64#ibcon#about to read 3, iclass 35, count 2 2006.280.07:56:02.67#ibcon#read 3, iclass 35, count 2 2006.280.07:56:02.67#ibcon#about to read 4, iclass 35, count 2 2006.280.07:56:02.67#ibcon#read 4, iclass 35, count 2 2006.280.07:56:02.67#ibcon#about to read 5, iclass 35, count 2 2006.280.07:56:02.67#ibcon#read 5, iclass 35, count 2 2006.280.07:56:02.67#ibcon#about to read 6, iclass 35, count 2 2006.280.07:56:02.67#ibcon#read 6, iclass 35, count 2 2006.280.07:56:02.67#ibcon#end of sib2, iclass 35, count 2 2006.280.07:56:02.67#ibcon#*after write, iclass 35, count 2 2006.280.07:56:02.67#ibcon#*before return 0, iclass 35, count 2 2006.280.07:56:02.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:56:02.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.07:56:02.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.07:56:02.67#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:02.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:02.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:02.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:02.79#ibcon#enter wrdev, iclass 35, count 0 2006.280.07:56:02.79#ibcon#first serial, iclass 35, count 0 2006.280.07:56:02.79#ibcon#enter sib2, iclass 35, count 0 2006.280.07:56:02.79#ibcon#flushed, iclass 35, count 0 2006.280.07:56:02.79#ibcon#about to write, iclass 35, count 0 2006.280.07:56:02.79#ibcon#wrote, iclass 35, count 0 2006.280.07:56:02.79#ibcon#about to read 3, iclass 35, count 0 2006.280.07:56:02.81#ibcon#read 3, iclass 35, count 0 2006.280.07:56:02.81#ibcon#about to read 4, iclass 35, count 0 2006.280.07:56:02.81#ibcon#read 4, iclass 35, count 0 2006.280.07:56:02.81#ibcon#about to read 5, iclass 35, count 0 2006.280.07:56:02.81#ibcon#read 5, iclass 35, count 0 2006.280.07:56:02.81#ibcon#about to read 6, iclass 35, count 0 2006.280.07:56:02.81#ibcon#read 6, iclass 35, count 0 2006.280.07:56:02.81#ibcon#end of sib2, iclass 35, count 0 2006.280.07:56:02.81#ibcon#*mode == 0, iclass 35, count 0 2006.280.07:56:02.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.07:56:02.81#ibcon#[27=USB\r\n] 2006.280.07:56:02.81#ibcon#*before write, iclass 35, count 0 2006.280.07:56:02.81#ibcon#enter sib2, iclass 35, count 0 2006.280.07:56:02.81#ibcon#flushed, iclass 35, count 0 2006.280.07:56:02.81#ibcon#about to write, iclass 35, count 0 2006.280.07:56:02.81#ibcon#wrote, iclass 35, count 0 2006.280.07:56:02.81#ibcon#about to read 3, iclass 35, count 0 2006.280.07:56:02.84#ibcon#read 3, iclass 35, count 0 2006.280.07:56:02.84#ibcon#about to read 4, iclass 35, count 0 2006.280.07:56:02.84#ibcon#read 4, iclass 35, count 0 2006.280.07:56:02.84#ibcon#about to read 5, iclass 35, count 0 2006.280.07:56:02.84#ibcon#read 5, iclass 35, count 0 2006.280.07:56:02.84#ibcon#about to read 6, iclass 35, count 0 2006.280.07:56:02.84#ibcon#read 6, iclass 35, count 0 2006.280.07:56:02.84#ibcon#end of sib2, iclass 35, count 0 2006.280.07:56:02.84#ibcon#*after write, iclass 35, count 0 2006.280.07:56:02.84#ibcon#*before return 0, iclass 35, count 0 2006.280.07:56:02.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:02.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.07:56:02.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.07:56:02.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.07:56:02.84$vc4f8/vblo=4,712.99 2006.280.07:56:02.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.07:56:02.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.07:56:02.84#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:02.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:02.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:02.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:02.84#ibcon#enter wrdev, iclass 37, count 0 2006.280.07:56:02.84#ibcon#first serial, iclass 37, count 0 2006.280.07:56:02.84#ibcon#enter sib2, iclass 37, count 0 2006.280.07:56:02.84#ibcon#flushed, iclass 37, count 0 2006.280.07:56:02.84#ibcon#about to write, iclass 37, count 0 2006.280.07:56:02.84#ibcon#wrote, iclass 37, count 0 2006.280.07:56:02.84#ibcon#about to read 3, iclass 37, count 0 2006.280.07:56:02.86#ibcon#read 3, iclass 37, count 0 2006.280.07:56:02.89#ibcon#about to read 4, iclass 37, count 0 2006.280.07:56:02.89#ibcon#read 4, iclass 37, count 0 2006.280.07:56:02.89#ibcon#about to read 5, iclass 37, count 0 2006.280.07:56:02.89#ibcon#read 5, iclass 37, count 0 2006.280.07:56:02.89#ibcon#about to read 6, iclass 37, count 0 2006.280.07:56:02.89#ibcon#read 6, iclass 37, count 0 2006.280.07:56:02.89#ibcon#end of sib2, iclass 37, count 0 2006.280.07:56:02.89#ibcon#*mode == 0, iclass 37, count 0 2006.280.07:56:02.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.07:56:02.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:56:02.89#ibcon#*before write, iclass 37, count 0 2006.280.07:56:02.89#ibcon#enter sib2, iclass 37, count 0 2006.280.07:56:02.89#ibcon#flushed, iclass 37, count 0 2006.280.07:56:02.89#ibcon#about to write, iclass 37, count 0 2006.280.07:56:02.89#ibcon#wrote, iclass 37, count 0 2006.280.07:56:02.89#ibcon#about to read 3, iclass 37, count 0 2006.280.07:56:02.94#ibcon#read 3, iclass 37, count 0 2006.280.07:56:02.94#ibcon#about to read 4, iclass 37, count 0 2006.280.07:56:02.94#ibcon#read 4, iclass 37, count 0 2006.280.07:56:02.94#ibcon#about to read 5, iclass 37, count 0 2006.280.07:56:02.94#ibcon#read 5, iclass 37, count 0 2006.280.07:56:02.94#ibcon#about to read 6, iclass 37, count 0 2006.280.07:56:02.94#ibcon#read 6, iclass 37, count 0 2006.280.07:56:02.94#ibcon#end of sib2, iclass 37, count 0 2006.280.07:56:02.94#ibcon#*after write, iclass 37, count 0 2006.280.07:56:02.94#ibcon#*before return 0, iclass 37, count 0 2006.280.07:56:02.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:02.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.07:56:02.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.07:56:02.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.07:56:02.94$vc4f8/vb=4,4 2006.280.07:56:02.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.07:56:02.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.07:56:02.94#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:02.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:02.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:02.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:02.95#ibcon#enter wrdev, iclass 39, count 2 2006.280.07:56:02.95#ibcon#first serial, iclass 39, count 2 2006.280.07:56:02.95#ibcon#enter sib2, iclass 39, count 2 2006.280.07:56:02.95#ibcon#flushed, iclass 39, count 2 2006.280.07:56:02.95#ibcon#about to write, iclass 39, count 2 2006.280.07:56:02.95#ibcon#wrote, iclass 39, count 2 2006.280.07:56:02.95#ibcon#about to read 3, iclass 39, count 2 2006.280.07:56:02.97#ibcon#read 3, iclass 39, count 2 2006.280.07:56:02.97#ibcon#about to read 4, iclass 39, count 2 2006.280.07:56:02.97#ibcon#read 4, iclass 39, count 2 2006.280.07:56:02.97#ibcon#about to read 5, iclass 39, count 2 2006.280.07:56:02.97#ibcon#read 5, iclass 39, count 2 2006.280.07:56:02.97#ibcon#about to read 6, iclass 39, count 2 2006.280.07:56:02.97#ibcon#read 6, iclass 39, count 2 2006.280.07:56:02.97#ibcon#end of sib2, iclass 39, count 2 2006.280.07:56:02.97#ibcon#*mode == 0, iclass 39, count 2 2006.280.07:56:02.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.07:56:02.99#ibcon#[27=AT04-04\r\n] 2006.280.07:56:02.99#ibcon#*before write, iclass 39, count 2 2006.280.07:56:02.99#ibcon#enter sib2, iclass 39, count 2 2006.280.07:56:02.99#ibcon#flushed, iclass 39, count 2 2006.280.07:56:02.99#ibcon#about to write, iclass 39, count 2 2006.280.07:56:02.99#ibcon#wrote, iclass 39, count 2 2006.280.07:56:02.99#ibcon#about to read 3, iclass 39, count 2 2006.280.07:56:03.02#ibcon#read 3, iclass 39, count 2 2006.280.07:56:03.02#ibcon#about to read 4, iclass 39, count 2 2006.280.07:56:03.02#ibcon#read 4, iclass 39, count 2 2006.280.07:56:03.02#ibcon#about to read 5, iclass 39, count 2 2006.280.07:56:03.02#ibcon#read 5, iclass 39, count 2 2006.280.07:56:03.02#ibcon#about to read 6, iclass 39, count 2 2006.280.07:56:03.02#ibcon#read 6, iclass 39, count 2 2006.280.07:56:03.02#ibcon#end of sib2, iclass 39, count 2 2006.280.07:56:03.02#ibcon#*after write, iclass 39, count 2 2006.280.07:56:03.02#ibcon#*before return 0, iclass 39, count 2 2006.280.07:56:03.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:03.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.07:56:03.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.07:56:03.02#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:03.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:03.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:03.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:03.14#ibcon#enter wrdev, iclass 39, count 0 2006.280.07:56:03.14#ibcon#first serial, iclass 39, count 0 2006.280.07:56:03.14#ibcon#enter sib2, iclass 39, count 0 2006.280.07:56:03.14#ibcon#flushed, iclass 39, count 0 2006.280.07:56:03.14#ibcon#about to write, iclass 39, count 0 2006.280.07:56:03.14#ibcon#wrote, iclass 39, count 0 2006.280.07:56:03.14#ibcon#about to read 3, iclass 39, count 0 2006.280.07:56:03.16#ibcon#read 3, iclass 39, count 0 2006.280.07:56:03.16#ibcon#about to read 4, iclass 39, count 0 2006.280.07:56:03.16#ibcon#read 4, iclass 39, count 0 2006.280.07:56:03.16#ibcon#about to read 5, iclass 39, count 0 2006.280.07:56:03.16#ibcon#read 5, iclass 39, count 0 2006.280.07:56:03.16#ibcon#about to read 6, iclass 39, count 0 2006.280.07:56:03.16#ibcon#read 6, iclass 39, count 0 2006.280.07:56:03.16#ibcon#end of sib2, iclass 39, count 0 2006.280.07:56:03.16#ibcon#*mode == 0, iclass 39, count 0 2006.280.07:56:03.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.07:56:03.16#ibcon#[27=USB\r\n] 2006.280.07:56:03.16#ibcon#*before write, iclass 39, count 0 2006.280.07:56:03.16#ibcon#enter sib2, iclass 39, count 0 2006.280.07:56:03.16#ibcon#flushed, iclass 39, count 0 2006.280.07:56:03.16#ibcon#about to write, iclass 39, count 0 2006.280.07:56:03.16#ibcon#wrote, iclass 39, count 0 2006.280.07:56:03.16#ibcon#about to read 3, iclass 39, count 0 2006.280.07:56:03.19#ibcon#read 3, iclass 39, count 0 2006.280.07:56:03.19#ibcon#about to read 4, iclass 39, count 0 2006.280.07:56:03.19#ibcon#read 4, iclass 39, count 0 2006.280.07:56:03.19#ibcon#about to read 5, iclass 39, count 0 2006.280.07:56:03.19#ibcon#read 5, iclass 39, count 0 2006.280.07:56:03.19#ibcon#about to read 6, iclass 39, count 0 2006.280.07:56:03.19#ibcon#read 6, iclass 39, count 0 2006.280.07:56:03.19#ibcon#end of sib2, iclass 39, count 0 2006.280.07:56:03.19#ibcon#*after write, iclass 39, count 0 2006.280.07:56:03.19#ibcon#*before return 0, iclass 39, count 0 2006.280.07:56:03.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:03.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.07:56:03.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.07:56:03.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.07:56:03.19$vc4f8/vblo=5,744.99 2006.280.07:56:03.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.07:56:03.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.07:56:03.19#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:03.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:03.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:03.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:03.19#ibcon#enter wrdev, iclass 3, count 0 2006.280.07:56:03.19#ibcon#first serial, iclass 3, count 0 2006.280.07:56:03.19#ibcon#enter sib2, iclass 3, count 0 2006.280.07:56:03.19#ibcon#flushed, iclass 3, count 0 2006.280.07:56:03.19#ibcon#about to write, iclass 3, count 0 2006.280.07:56:03.19#ibcon#wrote, iclass 3, count 0 2006.280.07:56:03.19#ibcon#about to read 3, iclass 3, count 0 2006.280.07:56:03.21#ibcon#read 3, iclass 3, count 0 2006.280.07:56:03.21#ibcon#about to read 4, iclass 3, count 0 2006.280.07:56:03.21#ibcon#read 4, iclass 3, count 0 2006.280.07:56:03.21#ibcon#about to read 5, iclass 3, count 0 2006.280.07:56:03.21#ibcon#read 5, iclass 3, count 0 2006.280.07:56:03.21#ibcon#about to read 6, iclass 3, count 0 2006.280.07:56:03.21#ibcon#read 6, iclass 3, count 0 2006.280.07:56:03.21#ibcon#end of sib2, iclass 3, count 0 2006.280.07:56:03.21#ibcon#*mode == 0, iclass 3, count 0 2006.280.07:56:03.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.07:56:03.21#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:56:03.21#ibcon#*before write, iclass 3, count 0 2006.280.07:56:03.21#ibcon#enter sib2, iclass 3, count 0 2006.280.07:56:03.21#ibcon#flushed, iclass 3, count 0 2006.280.07:56:03.21#ibcon#about to write, iclass 3, count 0 2006.280.07:56:03.21#ibcon#wrote, iclass 3, count 0 2006.280.07:56:03.21#ibcon#about to read 3, iclass 3, count 0 2006.280.07:56:03.25#ibcon#read 3, iclass 3, count 0 2006.280.07:56:03.25#ibcon#about to read 4, iclass 3, count 0 2006.280.07:56:03.25#ibcon#read 4, iclass 3, count 0 2006.280.07:56:03.25#ibcon#about to read 5, iclass 3, count 0 2006.280.07:56:03.25#ibcon#read 5, iclass 3, count 0 2006.280.07:56:03.25#ibcon#about to read 6, iclass 3, count 0 2006.280.07:56:03.25#ibcon#read 6, iclass 3, count 0 2006.280.07:56:03.25#ibcon#end of sib2, iclass 3, count 0 2006.280.07:56:03.25#ibcon#*after write, iclass 3, count 0 2006.280.07:56:03.25#ibcon#*before return 0, iclass 3, count 0 2006.280.07:56:03.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:03.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.07:56:03.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.07:56:03.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.07:56:03.25$vc4f8/vb=5,4 2006.280.07:56:03.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.07:56:03.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.07:56:03.25#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:03.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:03.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:03.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:03.31#ibcon#enter wrdev, iclass 5, count 2 2006.280.07:56:03.31#ibcon#first serial, iclass 5, count 2 2006.280.07:56:03.31#ibcon#enter sib2, iclass 5, count 2 2006.280.07:56:03.31#ibcon#flushed, iclass 5, count 2 2006.280.07:56:03.31#ibcon#about to write, iclass 5, count 2 2006.280.07:56:03.31#ibcon#wrote, iclass 5, count 2 2006.280.07:56:03.31#ibcon#about to read 3, iclass 5, count 2 2006.280.07:56:03.33#ibcon#read 3, iclass 5, count 2 2006.280.07:56:03.33#ibcon#about to read 4, iclass 5, count 2 2006.280.07:56:03.33#ibcon#read 4, iclass 5, count 2 2006.280.07:56:03.33#ibcon#about to read 5, iclass 5, count 2 2006.280.07:56:03.33#ibcon#read 5, iclass 5, count 2 2006.280.07:56:03.33#ibcon#about to read 6, iclass 5, count 2 2006.280.07:56:03.33#ibcon#read 6, iclass 5, count 2 2006.280.07:56:03.33#ibcon#end of sib2, iclass 5, count 2 2006.280.07:56:03.33#ibcon#*mode == 0, iclass 5, count 2 2006.280.07:56:03.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.07:56:03.33#ibcon#[27=AT05-04\r\n] 2006.280.07:56:03.33#ibcon#*before write, iclass 5, count 2 2006.280.07:56:03.33#ibcon#enter sib2, iclass 5, count 2 2006.280.07:56:03.33#ibcon#flushed, iclass 5, count 2 2006.280.07:56:03.33#ibcon#about to write, iclass 5, count 2 2006.280.07:56:03.33#ibcon#wrote, iclass 5, count 2 2006.280.07:56:03.33#ibcon#about to read 3, iclass 5, count 2 2006.280.07:56:03.36#ibcon#read 3, iclass 5, count 2 2006.280.07:56:03.36#ibcon#about to read 4, iclass 5, count 2 2006.280.07:56:03.36#ibcon#read 4, iclass 5, count 2 2006.280.07:56:03.36#ibcon#about to read 5, iclass 5, count 2 2006.280.07:56:03.36#ibcon#read 5, iclass 5, count 2 2006.280.07:56:03.36#ibcon#about to read 6, iclass 5, count 2 2006.280.07:56:03.36#ibcon#read 6, iclass 5, count 2 2006.280.07:56:03.36#ibcon#end of sib2, iclass 5, count 2 2006.280.07:56:03.36#ibcon#*after write, iclass 5, count 2 2006.280.07:56:03.36#ibcon#*before return 0, iclass 5, count 2 2006.280.07:56:03.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:03.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.07:56:03.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.07:56:03.36#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:03.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:03.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:03.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:03.48#ibcon#enter wrdev, iclass 5, count 0 2006.280.07:56:03.48#ibcon#first serial, iclass 5, count 0 2006.280.07:56:03.48#ibcon#enter sib2, iclass 5, count 0 2006.280.07:56:03.48#ibcon#flushed, iclass 5, count 0 2006.280.07:56:03.48#ibcon#about to write, iclass 5, count 0 2006.280.07:56:03.48#ibcon#wrote, iclass 5, count 0 2006.280.07:56:03.48#ibcon#about to read 3, iclass 5, count 0 2006.280.07:56:03.50#ibcon#read 3, iclass 5, count 0 2006.280.07:56:03.50#ibcon#about to read 4, iclass 5, count 0 2006.280.07:56:03.50#ibcon#read 4, iclass 5, count 0 2006.280.07:56:03.50#ibcon#about to read 5, iclass 5, count 0 2006.280.07:56:03.50#ibcon#read 5, iclass 5, count 0 2006.280.07:56:03.50#ibcon#about to read 6, iclass 5, count 0 2006.280.07:56:03.50#ibcon#read 6, iclass 5, count 0 2006.280.07:56:03.50#ibcon#end of sib2, iclass 5, count 0 2006.280.07:56:03.50#ibcon#*mode == 0, iclass 5, count 0 2006.280.07:56:03.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.07:56:03.50#ibcon#[27=USB\r\n] 2006.280.07:56:03.50#ibcon#*before write, iclass 5, count 0 2006.280.07:56:03.50#ibcon#enter sib2, iclass 5, count 0 2006.280.07:56:03.50#ibcon#flushed, iclass 5, count 0 2006.280.07:56:03.50#ibcon#about to write, iclass 5, count 0 2006.280.07:56:03.50#ibcon#wrote, iclass 5, count 0 2006.280.07:56:03.50#ibcon#about to read 3, iclass 5, count 0 2006.280.07:56:03.53#ibcon#read 3, iclass 5, count 0 2006.280.07:56:03.53#ibcon#about to read 4, iclass 5, count 0 2006.280.07:56:03.53#ibcon#read 4, iclass 5, count 0 2006.280.07:56:03.53#ibcon#about to read 5, iclass 5, count 0 2006.280.07:56:03.53#ibcon#read 5, iclass 5, count 0 2006.280.07:56:03.53#ibcon#about to read 6, iclass 5, count 0 2006.280.07:56:03.53#ibcon#read 6, iclass 5, count 0 2006.280.07:56:03.53#ibcon#end of sib2, iclass 5, count 0 2006.280.07:56:03.53#ibcon#*after write, iclass 5, count 0 2006.280.07:56:03.53#ibcon#*before return 0, iclass 5, count 0 2006.280.07:56:03.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:03.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.07:56:03.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.07:56:03.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.07:56:03.53$vc4f8/vblo=6,752.99 2006.280.07:56:03.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.07:56:03.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.07:56:03.62#ibcon#ireg 17 cls_cnt 0 2006.280.07:56:03.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:03.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:03.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:03.62#ibcon#enter wrdev, iclass 7, count 0 2006.280.07:56:03.62#ibcon#first serial, iclass 7, count 0 2006.280.07:56:03.62#ibcon#enter sib2, iclass 7, count 0 2006.280.07:56:03.62#ibcon#flushed, iclass 7, count 0 2006.280.07:56:03.62#ibcon#about to write, iclass 7, count 0 2006.280.07:56:03.62#ibcon#wrote, iclass 7, count 0 2006.280.07:56:03.62#ibcon#about to read 3, iclass 7, count 0 2006.280.07:56:03.64#ibcon#read 3, iclass 7, count 0 2006.280.07:56:03.64#ibcon#about to read 4, iclass 7, count 0 2006.280.07:56:03.64#ibcon#read 4, iclass 7, count 0 2006.280.07:56:03.64#ibcon#about to read 5, iclass 7, count 0 2006.280.07:56:03.64#ibcon#read 5, iclass 7, count 0 2006.280.07:56:03.64#ibcon#about to read 6, iclass 7, count 0 2006.280.07:56:03.64#ibcon#read 6, iclass 7, count 0 2006.280.07:56:03.64#ibcon#end of sib2, iclass 7, count 0 2006.280.07:56:03.64#ibcon#*mode == 0, iclass 7, count 0 2006.280.07:56:03.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.07:56:03.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:56:03.64#ibcon#*before write, iclass 7, count 0 2006.280.07:56:03.64#ibcon#enter sib2, iclass 7, count 0 2006.280.07:56:03.64#ibcon#flushed, iclass 7, count 0 2006.280.07:56:03.64#ibcon#about to write, iclass 7, count 0 2006.280.07:56:03.64#ibcon#wrote, iclass 7, count 0 2006.280.07:56:03.64#ibcon#about to read 3, iclass 7, count 0 2006.280.07:56:03.68#ibcon#read 3, iclass 7, count 0 2006.280.07:56:03.68#ibcon#about to read 4, iclass 7, count 0 2006.280.07:56:03.68#ibcon#read 4, iclass 7, count 0 2006.280.07:56:03.68#ibcon#about to read 5, iclass 7, count 0 2006.280.07:56:03.68#ibcon#read 5, iclass 7, count 0 2006.280.07:56:03.68#ibcon#about to read 6, iclass 7, count 0 2006.280.07:56:03.68#ibcon#read 6, iclass 7, count 0 2006.280.07:56:03.68#ibcon#end of sib2, iclass 7, count 0 2006.280.07:56:03.68#ibcon#*after write, iclass 7, count 0 2006.280.07:56:03.68#ibcon#*before return 0, iclass 7, count 0 2006.280.07:56:03.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:03.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.07:56:03.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.07:56:03.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.07:56:03.68$vc4f8/vb=6,4 2006.280.07:56:03.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.07:56:03.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.07:56:03.68#ibcon#ireg 11 cls_cnt 2 2006.280.07:56:03.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:03.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:03.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:03.68#ibcon#enter wrdev, iclass 11, count 2 2006.280.07:56:03.68#ibcon#first serial, iclass 11, count 2 2006.280.07:56:03.68#ibcon#enter sib2, iclass 11, count 2 2006.280.07:56:03.68#ibcon#flushed, iclass 11, count 2 2006.280.07:56:03.68#ibcon#about to write, iclass 11, count 2 2006.280.07:56:03.68#ibcon#wrote, iclass 11, count 2 2006.280.07:56:03.68#ibcon#about to read 3, iclass 11, count 2 2006.280.07:56:03.70#ibcon#read 3, iclass 11, count 2 2006.280.07:56:03.84#ibcon#about to read 4, iclass 11, count 2 2006.280.07:56:03.84#ibcon#read 4, iclass 11, count 2 2006.280.07:56:03.84#ibcon#about to read 5, iclass 11, count 2 2006.280.07:56:03.84#ibcon#read 5, iclass 11, count 2 2006.280.07:56:03.84#ibcon#about to read 6, iclass 11, count 2 2006.280.07:56:03.84#ibcon#read 6, iclass 11, count 2 2006.280.07:56:03.84#ibcon#end of sib2, iclass 11, count 2 2006.280.07:56:03.84#ibcon#*mode == 0, iclass 11, count 2 2006.280.07:56:03.84#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.07:56:03.84#ibcon#[27=AT06-04\r\n] 2006.280.07:56:03.84#ibcon#*before write, iclass 11, count 2 2006.280.07:56:03.84#ibcon#enter sib2, iclass 11, count 2 2006.280.07:56:03.84#ibcon#flushed, iclass 11, count 2 2006.280.07:56:03.84#ibcon#about to write, iclass 11, count 2 2006.280.07:56:03.84#ibcon#wrote, iclass 11, count 2 2006.280.07:56:03.84#ibcon#about to read 3, iclass 11, count 2 2006.280.07:56:03.87#ibcon#read 3, iclass 11, count 2 2006.280.07:56:03.87#ibcon#about to read 4, iclass 11, count 2 2006.280.07:56:03.91#ibcon#read 4, iclass 11, count 2 2006.280.07:56:03.91#ibcon#about to read 5, iclass 11, count 2 2006.280.07:56:03.91#ibcon#read 5, iclass 11, count 2 2006.280.07:56:03.91#ibcon#about to read 6, iclass 11, count 2 2006.280.07:56:03.91#ibcon#read 6, iclass 11, count 2 2006.280.07:56:03.91#ibcon#end of sib2, iclass 11, count 2 2006.280.07:56:03.91#ibcon#*after write, iclass 11, count 2 2006.280.07:56:03.91#ibcon#*before return 0, iclass 11, count 2 2006.280.07:56:03.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:03.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.07:56:03.91#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.07:56:03.91#ibcon#ireg 7 cls_cnt 0 2006.280.07:56:03.91#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:04.03#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:04.03#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:04.03#ibcon#enter wrdev, iclass 11, count 0 2006.280.07:56:04.03#ibcon#first serial, iclass 11, count 0 2006.280.07:56:04.03#ibcon#enter sib2, iclass 11, count 0 2006.280.07:56:04.03#ibcon#flushed, iclass 11, count 0 2006.280.07:56:04.03#ibcon#about to write, iclass 11, count 0 2006.280.07:56:04.03#ibcon#wrote, iclass 11, count 0 2006.280.07:56:04.03#ibcon#about to read 3, iclass 11, count 0 2006.280.07:56:04.05#ibcon#read 3, iclass 11, count 0 2006.280.07:56:04.05#ibcon#about to read 4, iclass 11, count 0 2006.280.07:56:04.05#ibcon#read 4, iclass 11, count 0 2006.280.07:56:04.05#ibcon#about to read 5, iclass 11, count 0 2006.280.07:56:04.05#ibcon#read 5, iclass 11, count 0 2006.280.07:56:04.05#ibcon#about to read 6, iclass 11, count 0 2006.280.07:56:04.05#ibcon#read 6, iclass 11, count 0 2006.280.07:56:04.05#ibcon#end of sib2, iclass 11, count 0 2006.280.07:56:04.05#ibcon#*mode == 0, iclass 11, count 0 2006.280.07:56:04.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.07:56:04.05#ibcon#[27=USB\r\n] 2006.280.07:56:04.05#ibcon#*before write, iclass 11, count 0 2006.280.07:56:04.05#ibcon#enter sib2, iclass 11, count 0 2006.280.07:56:04.05#ibcon#flushed, iclass 11, count 0 2006.280.07:56:04.05#ibcon#about to write, iclass 11, count 0 2006.280.07:56:04.05#ibcon#wrote, iclass 11, count 0 2006.280.07:56:04.05#ibcon#about to read 3, iclass 11, count 0 2006.280.07:56:04.08#ibcon#read 3, iclass 11, count 0 2006.280.07:56:04.08#ibcon#about to read 4, iclass 11, count 0 2006.280.07:56:04.08#ibcon#read 4, iclass 11, count 0 2006.280.07:56:04.08#ibcon#about to read 5, iclass 11, count 0 2006.280.07:56:04.08#ibcon#read 5, iclass 11, count 0 2006.280.07:56:04.08#ibcon#about to read 6, iclass 11, count 0 2006.280.07:56:04.08#ibcon#read 6, iclass 11, count 0 2006.280.07:56:04.08#ibcon#end of sib2, iclass 11, count 0 2006.280.07:56:04.08#ibcon#*after write, iclass 11, count 0 2006.280.07:56:04.08#ibcon#*before return 0, iclass 11, count 0 2006.280.07:56:04.08#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:04.08#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.07:56:04.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.07:56:04.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.07:56:04.08$vc4f8/vabw=wide 2006.280.07:56:04.08#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.07:56:04.08#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.07:56:04.08#ibcon#ireg 8 cls_cnt 0 2006.280.07:56:04.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:04.08#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:04.08#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:04.08#ibcon#enter wrdev, iclass 13, count 0 2006.280.07:56:04.08#ibcon#first serial, iclass 13, count 0 2006.280.07:56:04.08#ibcon#enter sib2, iclass 13, count 0 2006.280.07:56:04.08#ibcon#flushed, iclass 13, count 0 2006.280.07:56:04.08#ibcon#about to write, iclass 13, count 0 2006.280.07:56:04.08#ibcon#wrote, iclass 13, count 0 2006.280.07:56:04.08#ibcon#about to read 3, iclass 13, count 0 2006.280.07:56:04.10#ibcon#read 3, iclass 13, count 0 2006.280.07:56:04.10#ibcon#about to read 4, iclass 13, count 0 2006.280.07:56:04.14#ibcon#read 4, iclass 13, count 0 2006.280.07:56:04.14#ibcon#about to read 5, iclass 13, count 0 2006.280.07:56:04.14#ibcon#read 5, iclass 13, count 0 2006.280.07:56:04.14#ibcon#about to read 6, iclass 13, count 0 2006.280.07:56:04.14#ibcon#read 6, iclass 13, count 0 2006.280.07:56:04.14#ibcon#end of sib2, iclass 13, count 0 2006.280.07:56:04.14#ibcon#*mode == 0, iclass 13, count 0 2006.280.07:56:04.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.07:56:04.14#ibcon#[25=BW32\r\n] 2006.280.07:56:04.14#ibcon#*before write, iclass 13, count 0 2006.280.07:56:04.14#ibcon#enter sib2, iclass 13, count 0 2006.280.07:56:04.14#ibcon#flushed, iclass 13, count 0 2006.280.07:56:04.14#ibcon#about to write, iclass 13, count 0 2006.280.07:56:04.14#ibcon#wrote, iclass 13, count 0 2006.280.07:56:04.14#ibcon#about to read 3, iclass 13, count 0 2006.280.07:56:04.17#ibcon#read 3, iclass 13, count 0 2006.280.07:56:04.17#ibcon#about to read 4, iclass 13, count 0 2006.280.07:56:04.17#ibcon#read 4, iclass 13, count 0 2006.280.07:56:04.17#ibcon#about to read 5, iclass 13, count 0 2006.280.07:56:04.17#ibcon#read 5, iclass 13, count 0 2006.280.07:56:04.17#ibcon#about to read 6, iclass 13, count 0 2006.280.07:56:04.17#ibcon#read 6, iclass 13, count 0 2006.280.07:56:04.17#ibcon#end of sib2, iclass 13, count 0 2006.280.07:56:04.17#ibcon#*after write, iclass 13, count 0 2006.280.07:56:04.17#ibcon#*before return 0, iclass 13, count 0 2006.280.07:56:04.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:04.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.07:56:04.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.07:56:04.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.07:56:04.17$vc4f8/vbbw=wide 2006.280.07:56:04.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.07:56:04.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.07:56:04.17#ibcon#ireg 8 cls_cnt 0 2006.280.07:56:04.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:56:04.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:56:04.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:56:04.20#ibcon#enter wrdev, iclass 15, count 0 2006.280.07:56:04.20#ibcon#first serial, iclass 15, count 0 2006.280.07:56:04.20#ibcon#enter sib2, iclass 15, count 0 2006.280.07:56:04.20#ibcon#flushed, iclass 15, count 0 2006.280.07:56:04.20#ibcon#about to write, iclass 15, count 0 2006.280.07:56:04.20#ibcon#wrote, iclass 15, count 0 2006.280.07:56:04.20#ibcon#about to read 3, iclass 15, count 0 2006.280.07:56:04.22#ibcon#read 3, iclass 15, count 0 2006.280.07:56:04.36#ibcon#about to read 4, iclass 15, count 0 2006.280.07:56:04.36#ibcon#read 4, iclass 15, count 0 2006.280.07:56:04.36#ibcon#about to read 5, iclass 15, count 0 2006.280.07:56:04.36#ibcon#read 5, iclass 15, count 0 2006.280.07:56:04.36#ibcon#about to read 6, iclass 15, count 0 2006.280.07:56:04.36#ibcon#read 6, iclass 15, count 0 2006.280.07:56:04.36#ibcon#end of sib2, iclass 15, count 0 2006.280.07:56:04.36#ibcon#*mode == 0, iclass 15, count 0 2006.280.07:56:04.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.07:56:04.36#ibcon#[27=BW32\r\n] 2006.280.07:56:04.36#ibcon#*before write, iclass 15, count 0 2006.280.07:56:04.36#ibcon#enter sib2, iclass 15, count 0 2006.280.07:56:04.36#ibcon#flushed, iclass 15, count 0 2006.280.07:56:04.36#ibcon#about to write, iclass 15, count 0 2006.280.07:56:04.36#ibcon#wrote, iclass 15, count 0 2006.280.07:56:04.36#ibcon#about to read 3, iclass 15, count 0 2006.280.07:56:04.39#ibcon#read 3, iclass 15, count 0 2006.280.07:56:04.43#ibcon#about to read 4, iclass 15, count 0 2006.280.07:56:04.43#ibcon#read 4, iclass 15, count 0 2006.280.07:56:04.43#ibcon#about to read 5, iclass 15, count 0 2006.280.07:56:04.43#ibcon#read 5, iclass 15, count 0 2006.280.07:56:04.43#ibcon#about to read 6, iclass 15, count 0 2006.280.07:56:04.43#ibcon#read 6, iclass 15, count 0 2006.280.07:56:04.43#ibcon#end of sib2, iclass 15, count 0 2006.280.07:56:04.43#ibcon#*after write, iclass 15, count 0 2006.280.07:56:04.43#ibcon#*before return 0, iclass 15, count 0 2006.280.07:56:04.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:56:04.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.07:56:04.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.07:56:04.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.07:56:04.43$4f8m12a/ifd4f 2006.280.07:56:04.43$ifd4f/lo= 2006.280.07:56:04.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:56:04.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:56:04.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:56:04.43$ifd4f/patch= 2006.280.07:56:04.45$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:56:04.45$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:56:04.45$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:56:04.45$4f8m12a/"form=m,16.000,1:2 2006.280.07:56:04.45$4f8m12a/"tpicd 2006.280.07:56:04.45$4f8m12a/echo=off 2006.280.07:56:04.45$4f8m12a/xlog=off 2006.280.07:56:04.45:!2006.280.07:58:10 2006.280.07:56:29.14#trakl#Source acquired 2006.280.07:56:29.14#flagr#flagr/antenna,acquired 2006.280.07:58:10.00:preob 2006.280.07:58:10.14/onsource/TRACKING 2006.280.07:58:10.14:!2006.280.07:58:20 2006.280.07:58:20.00:data_valid=on 2006.280.07:58:20.00:midob 2006.280.07:58:20.14/onsource/TRACKING 2006.280.07:58:20.14/wx/20.98,987.1,60 2006.280.07:58:20.31/cable/+6.4839E-03 2006.280.07:58:21.40/va/01,07,usb,yes,46,48 2006.280.07:58:21.40/va/02,06,usb,yes,43,45 2006.280.07:58:21.40/va/03,06,usb,yes,40,40 2006.280.07:58:21.40/va/04,06,usb,yes,44,47 2006.280.07:58:21.40/va/05,07,usb,yes,41,44 2006.280.07:58:21.40/va/06,06,usb,yes,41,40 2006.280.07:58:21.40/va/07,06,usb,yes,40,40 2006.280.07:58:21.40/va/08,06,usb,yes,42,42 2006.280.07:58:21.63/valo/01,532.99,yes,locked 2006.280.07:58:21.63/valo/02,572.99,yes,locked 2006.280.07:58:21.63/valo/03,672.99,yes,locked 2006.280.07:58:21.63/valo/04,832.99,yes,locked 2006.280.07:58:21.63/valo/05,652.99,yes,locked 2006.280.07:58:21.63/valo/06,772.99,yes,locked 2006.280.07:58:21.63/valo/07,832.99,yes,locked 2006.280.07:58:21.63/valo/08,852.99,yes,locked 2006.280.07:58:22.72/vb/01,04,usb,yes,37,35 2006.280.07:58:22.72/vb/02,05,usb,yes,34,36 2006.280.07:58:22.72/vb/03,04,usb,yes,35,39 2006.280.07:58:22.72/vb/04,04,usb,yes,36,36 2006.280.07:58:22.72/vb/05,04,usb,yes,33,39 2006.280.07:58:22.72/vb/06,04,usb,yes,34,38 2006.280.07:58:22.72/vb/07,04,usb,yes,38,38 2006.280.07:58:22.72/vb/08,04,usb,yes,34,38 2006.280.07:58:22.96/vblo/01,632.99,yes,locked 2006.280.07:58:22.96/vblo/02,640.99,yes,locked 2006.280.07:58:22.96/vblo/03,656.99,yes,locked 2006.280.07:58:22.96/vblo/04,712.99,yes,locked 2006.280.07:58:22.96/vblo/05,744.99,yes,locked 2006.280.07:58:22.96/vblo/06,752.99,yes,locked 2006.280.07:58:22.96/vblo/07,734.99,yes,locked 2006.280.07:58:22.96/vblo/08,744.99,yes,locked 2006.280.07:58:23.11/vabw/8 2006.280.07:58:23.26/vbbw/8 2006.280.07:58:23.35/xfe/off,on,12.2 2006.280.07:58:23.74/ifatt/23,28,28,28 2006.280.07:58:24.08/fmout-gps/S +3.21E-07 2006.280.07:58:24.11:!2006.280.07:59:20 2006.280.07:59:20.00:data_valid=off 2006.280.07:59:20.00:postob 2006.280.07:59:20.08/cable/+6.4846E-03 2006.280.07:59:20.08/wx/20.96,987.1,60 2006.280.07:59:21.08/fmout-gps/S +3.21E-07 2006.280.07:59:21.08:scan_name=280-0800,k06280,60 2006.280.07:59:21.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.280.07:59:21.14#flagr#flagr/antenna,new-source 2006.280.07:59:22.14:checkk5 2006.280.07:59:23.88/chk_autoobs//k5ts1/ autoobs is running! 2006.280.07:59:24.26/chk_autoobs//k5ts2/ autoobs is running! 2006.280.07:59:24.72/chk_autoobs//k5ts3/ autoobs is running! 2006.280.07:59:25.53/chk_autoobs//k5ts4/ autoobs is running! 2006.280.07:59:26.05/chk_obsdata//k5ts1/T2800758??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:59:26.80/chk_obsdata//k5ts2/T2800758??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:59:27.62/chk_obsdata//k5ts3/T2800758??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:59:28.06/chk_obsdata//k5ts4/T2800758??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.07:59:29.23/k5log//k5ts1_log_newline 2006.280.07:59:30.13/k5log//k5ts2_log_newline 2006.280.07:59:31.45/k5log//k5ts3_log_newline 2006.280.07:59:32.68/k5log//k5ts4_log_newline 2006.280.07:59:32.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.07:59:32.70:4f8m12a=2 2006.280.07:59:32.70$4f8m12a/echo=on 2006.280.07:59:32.70$4f8m12a/pcalon 2006.280.07:59:32.70$pcalon/"no phase cal control is implemented here 2006.280.07:59:32.70$4f8m12a/"tpicd=stop 2006.280.07:59:32.70$4f8m12a/vc4f8 2006.280.07:59:32.70$vc4f8/valo=1,532.99 2006.280.07:59:32.71#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:59:32.71#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:59:32.71#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:32.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:32.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:32.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:32.71#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:59:32.71#ibcon#first serial, iclass 26, count 0 2006.280.07:59:32.71#ibcon#enter sib2, iclass 26, count 0 2006.280.07:59:32.71#ibcon#flushed, iclass 26, count 0 2006.280.07:59:32.71#ibcon#about to write, iclass 26, count 0 2006.280.07:59:32.71#ibcon#wrote, iclass 26, count 0 2006.280.07:59:32.71#ibcon#about to read 3, iclass 26, count 0 2006.280.07:59:32.73#ibcon#read 3, iclass 26, count 0 2006.280.07:59:32.73#ibcon#about to read 4, iclass 26, count 0 2006.280.07:59:32.73#ibcon#read 4, iclass 26, count 0 2006.280.07:59:32.73#ibcon#about to read 5, iclass 26, count 0 2006.280.07:59:32.73#ibcon#read 5, iclass 26, count 0 2006.280.07:59:32.73#ibcon#about to read 6, iclass 26, count 0 2006.280.07:59:32.73#ibcon#read 6, iclass 26, count 0 2006.280.07:59:32.73#ibcon#end of sib2, iclass 26, count 0 2006.280.07:59:32.73#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:59:32.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:59:32.73#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.07:59:32.73#ibcon#*before write, iclass 26, count 0 2006.280.07:59:32.73#ibcon#enter sib2, iclass 26, count 0 2006.280.07:59:32.73#ibcon#flushed, iclass 26, count 0 2006.280.07:59:32.73#ibcon#about to write, iclass 26, count 0 2006.280.07:59:32.73#ibcon#wrote, iclass 26, count 0 2006.280.07:59:32.73#ibcon#about to read 3, iclass 26, count 0 2006.280.07:59:32.78#ibcon#read 3, iclass 26, count 0 2006.280.07:59:32.78#ibcon#about to read 4, iclass 26, count 0 2006.280.07:59:32.78#ibcon#read 4, iclass 26, count 0 2006.280.07:59:32.78#ibcon#about to read 5, iclass 26, count 0 2006.280.07:59:32.78#ibcon#read 5, iclass 26, count 0 2006.280.07:59:32.78#ibcon#about to read 6, iclass 26, count 0 2006.280.07:59:32.78#ibcon#read 6, iclass 26, count 0 2006.280.07:59:32.78#ibcon#end of sib2, iclass 26, count 0 2006.280.07:59:32.78#ibcon#*after write, iclass 26, count 0 2006.280.07:59:32.78#ibcon#*before return 0, iclass 26, count 0 2006.280.07:59:32.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:32.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:32.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:59:32.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:59:32.79$vc4f8/va=1,7 2006.280.07:59:32.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:59:32.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:59:32.79#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:32.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:32.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:32.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:32.79#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:59:32.79#ibcon#first serial, iclass 28, count 2 2006.280.07:59:32.79#ibcon#enter sib2, iclass 28, count 2 2006.280.07:59:32.79#ibcon#flushed, iclass 28, count 2 2006.280.07:59:32.79#ibcon#about to write, iclass 28, count 2 2006.280.07:59:32.79#ibcon#wrote, iclass 28, count 2 2006.280.07:59:32.79#ibcon#about to read 3, iclass 28, count 2 2006.280.07:59:32.80#ibcon#read 3, iclass 28, count 2 2006.280.07:59:32.80#ibcon#about to read 4, iclass 28, count 2 2006.280.07:59:32.80#ibcon#read 4, iclass 28, count 2 2006.280.07:59:32.80#ibcon#about to read 5, iclass 28, count 2 2006.280.07:59:32.80#ibcon#read 5, iclass 28, count 2 2006.280.07:59:32.80#ibcon#about to read 6, iclass 28, count 2 2006.280.07:59:32.80#ibcon#read 6, iclass 28, count 2 2006.280.07:59:32.80#ibcon#end of sib2, iclass 28, count 2 2006.280.07:59:32.80#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:59:32.80#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:59:32.80#ibcon#[25=AT01-07\r\n] 2006.280.07:59:32.80#ibcon#*before write, iclass 28, count 2 2006.280.07:59:32.80#ibcon#enter sib2, iclass 28, count 2 2006.280.07:59:32.80#ibcon#flushed, iclass 28, count 2 2006.280.07:59:32.80#ibcon#about to write, iclass 28, count 2 2006.280.07:59:32.80#ibcon#wrote, iclass 28, count 2 2006.280.07:59:32.80#ibcon#about to read 3, iclass 28, count 2 2006.280.07:59:32.83#ibcon#read 3, iclass 28, count 2 2006.280.07:59:32.83#ibcon#about to read 4, iclass 28, count 2 2006.280.07:59:32.83#ibcon#read 4, iclass 28, count 2 2006.280.07:59:32.83#ibcon#about to read 5, iclass 28, count 2 2006.280.07:59:32.83#ibcon#read 5, iclass 28, count 2 2006.280.07:59:32.83#ibcon#about to read 6, iclass 28, count 2 2006.280.07:59:32.83#ibcon#read 6, iclass 28, count 2 2006.280.07:59:32.83#ibcon#end of sib2, iclass 28, count 2 2006.280.07:59:32.83#ibcon#*after write, iclass 28, count 2 2006.280.07:59:32.83#ibcon#*before return 0, iclass 28, count 2 2006.280.07:59:32.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:32.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:32.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:59:32.83#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:32.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:32.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:32.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:32.95#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:59:32.96#ibcon#first serial, iclass 28, count 0 2006.280.07:59:32.96#ibcon#enter sib2, iclass 28, count 0 2006.280.07:59:32.96#ibcon#flushed, iclass 28, count 0 2006.280.07:59:32.96#ibcon#about to write, iclass 28, count 0 2006.280.07:59:32.96#ibcon#wrote, iclass 28, count 0 2006.280.07:59:32.96#ibcon#about to read 3, iclass 28, count 0 2006.280.07:59:32.97#ibcon#read 3, iclass 28, count 0 2006.280.07:59:32.97#ibcon#about to read 4, iclass 28, count 0 2006.280.07:59:32.97#ibcon#read 4, iclass 28, count 0 2006.280.07:59:32.97#ibcon#about to read 5, iclass 28, count 0 2006.280.07:59:32.97#ibcon#read 5, iclass 28, count 0 2006.280.07:59:32.97#ibcon#about to read 6, iclass 28, count 0 2006.280.07:59:32.97#ibcon#read 6, iclass 28, count 0 2006.280.07:59:32.97#ibcon#end of sib2, iclass 28, count 0 2006.280.07:59:32.97#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:59:32.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:59:32.97#ibcon#[25=USB\r\n] 2006.280.07:59:32.97#ibcon#*before write, iclass 28, count 0 2006.280.07:59:32.97#ibcon#enter sib2, iclass 28, count 0 2006.280.07:59:32.97#ibcon#flushed, iclass 28, count 0 2006.280.07:59:32.97#ibcon#about to write, iclass 28, count 0 2006.280.07:59:32.97#ibcon#wrote, iclass 28, count 0 2006.280.07:59:32.97#ibcon#about to read 3, iclass 28, count 0 2006.280.07:59:33.00#ibcon#read 3, iclass 28, count 0 2006.280.07:59:33.00#ibcon#about to read 4, iclass 28, count 0 2006.280.07:59:33.00#ibcon#read 4, iclass 28, count 0 2006.280.07:59:33.00#ibcon#about to read 5, iclass 28, count 0 2006.280.07:59:33.00#ibcon#read 5, iclass 28, count 0 2006.280.07:59:33.00#ibcon#about to read 6, iclass 28, count 0 2006.280.07:59:33.00#ibcon#read 6, iclass 28, count 0 2006.280.07:59:33.00#ibcon#end of sib2, iclass 28, count 0 2006.280.07:59:33.00#ibcon#*after write, iclass 28, count 0 2006.280.07:59:33.00#ibcon#*before return 0, iclass 28, count 0 2006.280.07:59:33.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:33.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:33.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:59:33.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:59:33.00$vc4f8/valo=2,572.99 2006.280.07:59:33.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:59:33.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:59:33.00#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:33.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:33.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:33.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:33.00#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:59:33.00#ibcon#first serial, iclass 30, count 0 2006.280.07:59:33.00#ibcon#enter sib2, iclass 30, count 0 2006.280.07:59:33.00#ibcon#flushed, iclass 30, count 0 2006.280.07:59:33.00#ibcon#about to write, iclass 30, count 0 2006.280.07:59:33.00#ibcon#wrote, iclass 30, count 0 2006.280.07:59:33.00#ibcon#about to read 3, iclass 30, count 0 2006.280.07:59:33.02#ibcon#read 3, iclass 30, count 0 2006.280.07:59:33.02#ibcon#about to read 4, iclass 30, count 0 2006.280.07:59:33.02#ibcon#read 4, iclass 30, count 0 2006.280.07:59:33.02#ibcon#about to read 5, iclass 30, count 0 2006.280.07:59:33.02#ibcon#read 5, iclass 30, count 0 2006.280.07:59:33.02#ibcon#about to read 6, iclass 30, count 0 2006.280.07:59:33.02#ibcon#read 6, iclass 30, count 0 2006.280.07:59:33.02#ibcon#end of sib2, iclass 30, count 0 2006.280.07:59:33.02#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:59:33.02#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:59:33.02#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.07:59:33.02#ibcon#*before write, iclass 30, count 0 2006.280.07:59:33.02#ibcon#enter sib2, iclass 30, count 0 2006.280.07:59:33.02#ibcon#flushed, iclass 30, count 0 2006.280.07:59:33.02#ibcon#about to write, iclass 30, count 0 2006.280.07:59:33.02#ibcon#wrote, iclass 30, count 0 2006.280.07:59:33.02#ibcon#about to read 3, iclass 30, count 0 2006.280.07:59:33.06#ibcon#read 3, iclass 30, count 0 2006.280.07:59:33.06#ibcon#about to read 4, iclass 30, count 0 2006.280.07:59:33.06#ibcon#read 4, iclass 30, count 0 2006.280.07:59:33.06#ibcon#about to read 5, iclass 30, count 0 2006.280.07:59:33.06#ibcon#read 5, iclass 30, count 0 2006.280.07:59:33.06#ibcon#about to read 6, iclass 30, count 0 2006.280.07:59:33.06#ibcon#read 6, iclass 30, count 0 2006.280.07:59:33.06#ibcon#end of sib2, iclass 30, count 0 2006.280.07:59:33.06#ibcon#*after write, iclass 30, count 0 2006.280.07:59:33.06#ibcon#*before return 0, iclass 30, count 0 2006.280.07:59:33.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:33.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:33.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:59:33.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:59:33.06$vc4f8/va=2,6 2006.280.07:59:33.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:59:33.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:59:33.06#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:33.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:33.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:33.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:33.12#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:59:33.12#ibcon#first serial, iclass 32, count 2 2006.280.07:59:33.12#ibcon#enter sib2, iclass 32, count 2 2006.280.07:59:33.12#ibcon#flushed, iclass 32, count 2 2006.280.07:59:33.12#ibcon#about to write, iclass 32, count 2 2006.280.07:59:33.12#ibcon#wrote, iclass 32, count 2 2006.280.07:59:33.12#ibcon#about to read 3, iclass 32, count 2 2006.280.07:59:33.14#ibcon#read 3, iclass 32, count 2 2006.280.07:59:33.14#ibcon#about to read 4, iclass 32, count 2 2006.280.07:59:33.14#ibcon#read 4, iclass 32, count 2 2006.280.07:59:33.14#ibcon#about to read 5, iclass 32, count 2 2006.280.07:59:33.14#ibcon#read 5, iclass 32, count 2 2006.280.07:59:33.14#ibcon#about to read 6, iclass 32, count 2 2006.280.07:59:33.14#ibcon#read 6, iclass 32, count 2 2006.280.07:59:33.14#ibcon#end of sib2, iclass 32, count 2 2006.280.07:59:33.14#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:59:33.14#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:59:33.14#ibcon#[25=AT02-06\r\n] 2006.280.07:59:33.14#ibcon#*before write, iclass 32, count 2 2006.280.07:59:33.14#ibcon#enter sib2, iclass 32, count 2 2006.280.07:59:33.14#ibcon#flushed, iclass 32, count 2 2006.280.07:59:33.14#ibcon#about to write, iclass 32, count 2 2006.280.07:59:33.14#ibcon#wrote, iclass 32, count 2 2006.280.07:59:33.14#ibcon#about to read 3, iclass 32, count 2 2006.280.07:59:33.17#ibcon#read 3, iclass 32, count 2 2006.280.07:59:33.17#ibcon#about to read 4, iclass 32, count 2 2006.280.07:59:33.17#ibcon#read 4, iclass 32, count 2 2006.280.07:59:33.17#ibcon#about to read 5, iclass 32, count 2 2006.280.07:59:33.17#ibcon#read 5, iclass 32, count 2 2006.280.07:59:33.17#ibcon#about to read 6, iclass 32, count 2 2006.280.07:59:33.17#ibcon#read 6, iclass 32, count 2 2006.280.07:59:33.17#ibcon#end of sib2, iclass 32, count 2 2006.280.07:59:33.17#ibcon#*after write, iclass 32, count 2 2006.280.07:59:33.17#ibcon#*before return 0, iclass 32, count 2 2006.280.07:59:33.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:33.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:33.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:59:33.17#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:33.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:33.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:33.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:33.29#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:59:33.29#ibcon#first serial, iclass 32, count 0 2006.280.07:59:33.29#ibcon#enter sib2, iclass 32, count 0 2006.280.07:59:33.29#ibcon#flushed, iclass 32, count 0 2006.280.07:59:33.29#ibcon#about to write, iclass 32, count 0 2006.280.07:59:33.29#ibcon#wrote, iclass 32, count 0 2006.280.07:59:33.29#ibcon#about to read 3, iclass 32, count 0 2006.280.07:59:33.31#ibcon#read 3, iclass 32, count 0 2006.280.07:59:33.31#ibcon#about to read 4, iclass 32, count 0 2006.280.07:59:33.31#ibcon#read 4, iclass 32, count 0 2006.280.07:59:33.31#ibcon#about to read 5, iclass 32, count 0 2006.280.07:59:33.31#ibcon#read 5, iclass 32, count 0 2006.280.07:59:33.31#ibcon#about to read 6, iclass 32, count 0 2006.280.07:59:33.31#ibcon#read 6, iclass 32, count 0 2006.280.07:59:33.31#ibcon#end of sib2, iclass 32, count 0 2006.280.07:59:33.31#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:59:33.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:59:33.31#ibcon#[25=USB\r\n] 2006.280.07:59:33.31#ibcon#*before write, iclass 32, count 0 2006.280.07:59:33.31#ibcon#enter sib2, iclass 32, count 0 2006.280.07:59:33.31#ibcon#flushed, iclass 32, count 0 2006.280.07:59:33.31#ibcon#about to write, iclass 32, count 0 2006.280.07:59:33.31#ibcon#wrote, iclass 32, count 0 2006.280.07:59:33.31#ibcon#about to read 3, iclass 32, count 0 2006.280.07:59:33.34#ibcon#read 3, iclass 32, count 0 2006.280.07:59:33.34#ibcon#about to read 4, iclass 32, count 0 2006.280.07:59:33.34#ibcon#read 4, iclass 32, count 0 2006.280.07:59:33.34#ibcon#about to read 5, iclass 32, count 0 2006.280.07:59:33.34#ibcon#read 5, iclass 32, count 0 2006.280.07:59:33.34#ibcon#about to read 6, iclass 32, count 0 2006.280.07:59:33.34#ibcon#read 6, iclass 32, count 0 2006.280.07:59:33.34#ibcon#end of sib2, iclass 32, count 0 2006.280.07:59:33.34#ibcon#*after write, iclass 32, count 0 2006.280.07:59:33.34#ibcon#*before return 0, iclass 32, count 0 2006.280.07:59:33.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:33.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:33.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:59:33.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:59:33.34$vc4f8/valo=3,672.99 2006.280.07:59:33.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:59:33.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:59:33.34#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:33.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:33.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:33.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:33.34#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:59:33.34#ibcon#first serial, iclass 34, count 0 2006.280.07:59:33.34#ibcon#enter sib2, iclass 34, count 0 2006.280.07:59:33.34#ibcon#flushed, iclass 34, count 0 2006.280.07:59:33.34#ibcon#about to write, iclass 34, count 0 2006.280.07:59:33.34#ibcon#wrote, iclass 34, count 0 2006.280.07:59:33.34#ibcon#about to read 3, iclass 34, count 0 2006.280.07:59:33.36#ibcon#read 3, iclass 34, count 0 2006.280.07:59:33.36#ibcon#about to read 4, iclass 34, count 0 2006.280.07:59:33.36#ibcon#read 4, iclass 34, count 0 2006.280.07:59:33.36#ibcon#about to read 5, iclass 34, count 0 2006.280.07:59:33.36#ibcon#read 5, iclass 34, count 0 2006.280.07:59:33.36#ibcon#about to read 6, iclass 34, count 0 2006.280.07:59:33.36#ibcon#read 6, iclass 34, count 0 2006.280.07:59:33.36#ibcon#end of sib2, iclass 34, count 0 2006.280.07:59:33.36#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:59:33.36#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:59:33.36#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.07:59:33.36#ibcon#*before write, iclass 34, count 0 2006.280.07:59:33.36#ibcon#enter sib2, iclass 34, count 0 2006.280.07:59:33.36#ibcon#flushed, iclass 34, count 0 2006.280.07:59:33.36#ibcon#about to write, iclass 34, count 0 2006.280.07:59:33.36#ibcon#wrote, iclass 34, count 0 2006.280.07:59:33.36#ibcon#about to read 3, iclass 34, count 0 2006.280.07:59:33.40#ibcon#read 3, iclass 34, count 0 2006.280.07:59:33.40#ibcon#about to read 4, iclass 34, count 0 2006.280.07:59:33.40#ibcon#read 4, iclass 34, count 0 2006.280.07:59:33.40#ibcon#about to read 5, iclass 34, count 0 2006.280.07:59:33.40#ibcon#read 5, iclass 34, count 0 2006.280.07:59:33.40#ibcon#about to read 6, iclass 34, count 0 2006.280.07:59:33.40#ibcon#read 6, iclass 34, count 0 2006.280.07:59:33.40#ibcon#end of sib2, iclass 34, count 0 2006.280.07:59:33.40#ibcon#*after write, iclass 34, count 0 2006.280.07:59:33.40#ibcon#*before return 0, iclass 34, count 0 2006.280.07:59:33.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:33.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:33.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:59:33.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:59:33.40$vc4f8/va=3,6 2006.280.07:59:33.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:59:33.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:59:33.40#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:33.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:33.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:33.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:33.46#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:59:33.46#ibcon#first serial, iclass 36, count 2 2006.280.07:59:33.46#ibcon#enter sib2, iclass 36, count 2 2006.280.07:59:33.46#ibcon#flushed, iclass 36, count 2 2006.280.07:59:33.46#ibcon#about to write, iclass 36, count 2 2006.280.07:59:33.46#ibcon#wrote, iclass 36, count 2 2006.280.07:59:33.46#ibcon#about to read 3, iclass 36, count 2 2006.280.07:59:33.48#ibcon#read 3, iclass 36, count 2 2006.280.07:59:33.48#ibcon#about to read 4, iclass 36, count 2 2006.280.07:59:33.48#ibcon#read 4, iclass 36, count 2 2006.280.07:59:33.48#ibcon#about to read 5, iclass 36, count 2 2006.280.07:59:33.48#ibcon#read 5, iclass 36, count 2 2006.280.07:59:33.48#ibcon#about to read 6, iclass 36, count 2 2006.280.07:59:33.48#ibcon#read 6, iclass 36, count 2 2006.280.07:59:33.48#ibcon#end of sib2, iclass 36, count 2 2006.280.07:59:33.48#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:59:33.48#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:59:33.48#ibcon#[25=AT03-06\r\n] 2006.280.07:59:33.48#ibcon#*before write, iclass 36, count 2 2006.280.07:59:33.48#ibcon#enter sib2, iclass 36, count 2 2006.280.07:59:33.48#ibcon#flushed, iclass 36, count 2 2006.280.07:59:33.48#ibcon#about to write, iclass 36, count 2 2006.280.07:59:33.48#ibcon#wrote, iclass 36, count 2 2006.280.07:59:33.48#ibcon#about to read 3, iclass 36, count 2 2006.280.07:59:33.51#ibcon#read 3, iclass 36, count 2 2006.280.07:59:33.51#ibcon#about to read 4, iclass 36, count 2 2006.280.07:59:33.51#ibcon#read 4, iclass 36, count 2 2006.280.07:59:33.51#ibcon#about to read 5, iclass 36, count 2 2006.280.07:59:33.51#ibcon#read 5, iclass 36, count 2 2006.280.07:59:33.51#ibcon#about to read 6, iclass 36, count 2 2006.280.07:59:33.51#ibcon#read 6, iclass 36, count 2 2006.280.07:59:33.51#ibcon#end of sib2, iclass 36, count 2 2006.280.07:59:33.51#ibcon#*after write, iclass 36, count 2 2006.280.07:59:33.51#ibcon#*before return 0, iclass 36, count 2 2006.280.07:59:33.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:33.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:33.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:59:33.51#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:33.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:33.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:33.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:33.63#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:59:33.63#ibcon#first serial, iclass 36, count 0 2006.280.07:59:33.63#ibcon#enter sib2, iclass 36, count 0 2006.280.07:59:33.63#ibcon#flushed, iclass 36, count 0 2006.280.07:59:33.63#ibcon#about to write, iclass 36, count 0 2006.280.07:59:33.63#ibcon#wrote, iclass 36, count 0 2006.280.07:59:33.63#ibcon#about to read 3, iclass 36, count 0 2006.280.07:59:33.65#ibcon#read 3, iclass 36, count 0 2006.280.07:59:33.65#ibcon#about to read 4, iclass 36, count 0 2006.280.07:59:33.65#ibcon#read 4, iclass 36, count 0 2006.280.07:59:33.65#ibcon#about to read 5, iclass 36, count 0 2006.280.07:59:33.65#ibcon#read 5, iclass 36, count 0 2006.280.07:59:33.65#ibcon#about to read 6, iclass 36, count 0 2006.280.07:59:33.65#ibcon#read 6, iclass 36, count 0 2006.280.07:59:33.65#ibcon#end of sib2, iclass 36, count 0 2006.280.07:59:33.65#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:59:33.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:59:33.65#ibcon#[25=USB\r\n] 2006.280.07:59:33.65#ibcon#*before write, iclass 36, count 0 2006.280.07:59:33.65#ibcon#enter sib2, iclass 36, count 0 2006.280.07:59:33.65#ibcon#flushed, iclass 36, count 0 2006.280.07:59:33.65#ibcon#about to write, iclass 36, count 0 2006.280.07:59:33.65#ibcon#wrote, iclass 36, count 0 2006.280.07:59:33.65#ibcon#about to read 3, iclass 36, count 0 2006.280.07:59:33.68#ibcon#read 3, iclass 36, count 0 2006.280.07:59:33.68#ibcon#about to read 4, iclass 36, count 0 2006.280.07:59:33.68#ibcon#read 4, iclass 36, count 0 2006.280.07:59:33.68#ibcon#about to read 5, iclass 36, count 0 2006.280.07:59:33.68#ibcon#read 5, iclass 36, count 0 2006.280.07:59:33.68#ibcon#about to read 6, iclass 36, count 0 2006.280.07:59:33.68#ibcon#read 6, iclass 36, count 0 2006.280.07:59:33.68#ibcon#end of sib2, iclass 36, count 0 2006.280.07:59:33.68#ibcon#*after write, iclass 36, count 0 2006.280.07:59:33.68#ibcon#*before return 0, iclass 36, count 0 2006.280.07:59:33.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:33.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:33.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:59:33.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:59:33.68$vc4f8/valo=4,832.99 2006.280.07:59:33.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:59:33.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:59:33.68#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:33.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:33.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:33.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:33.68#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:59:33.68#ibcon#first serial, iclass 38, count 0 2006.280.07:59:33.68#ibcon#enter sib2, iclass 38, count 0 2006.280.07:59:33.68#ibcon#flushed, iclass 38, count 0 2006.280.07:59:33.68#ibcon#about to write, iclass 38, count 0 2006.280.07:59:33.68#ibcon#wrote, iclass 38, count 0 2006.280.07:59:33.68#ibcon#about to read 3, iclass 38, count 0 2006.280.07:59:33.70#ibcon#read 3, iclass 38, count 0 2006.280.07:59:33.70#ibcon#about to read 4, iclass 38, count 0 2006.280.07:59:33.70#ibcon#read 4, iclass 38, count 0 2006.280.07:59:33.70#ibcon#about to read 5, iclass 38, count 0 2006.280.07:59:33.70#ibcon#read 5, iclass 38, count 0 2006.280.07:59:33.70#ibcon#about to read 6, iclass 38, count 0 2006.280.07:59:33.70#ibcon#read 6, iclass 38, count 0 2006.280.07:59:33.70#ibcon#end of sib2, iclass 38, count 0 2006.280.07:59:33.70#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:59:33.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:59:33.70#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.07:59:33.70#ibcon#*before write, iclass 38, count 0 2006.280.07:59:33.70#ibcon#enter sib2, iclass 38, count 0 2006.280.07:59:33.70#ibcon#flushed, iclass 38, count 0 2006.280.07:59:33.70#ibcon#about to write, iclass 38, count 0 2006.280.07:59:33.70#ibcon#wrote, iclass 38, count 0 2006.280.07:59:33.70#ibcon#about to read 3, iclass 38, count 0 2006.280.07:59:33.74#ibcon#read 3, iclass 38, count 0 2006.280.07:59:33.74#ibcon#about to read 4, iclass 38, count 0 2006.280.07:59:33.74#ibcon#read 4, iclass 38, count 0 2006.280.07:59:33.74#ibcon#about to read 5, iclass 38, count 0 2006.280.07:59:33.74#ibcon#read 5, iclass 38, count 0 2006.280.07:59:33.74#ibcon#about to read 6, iclass 38, count 0 2006.280.07:59:33.74#ibcon#read 6, iclass 38, count 0 2006.280.07:59:33.74#ibcon#end of sib2, iclass 38, count 0 2006.280.07:59:33.74#ibcon#*after write, iclass 38, count 0 2006.280.07:59:33.74#ibcon#*before return 0, iclass 38, count 0 2006.280.07:59:33.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:33.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:33.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:59:33.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:59:33.74$vc4f8/va=4,6 2006.280.07:59:33.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:59:33.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:59:33.74#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:33.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:33.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:33.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:33.80#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:59:33.80#ibcon#first serial, iclass 40, count 2 2006.280.07:59:33.80#ibcon#enter sib2, iclass 40, count 2 2006.280.07:59:33.80#ibcon#flushed, iclass 40, count 2 2006.280.07:59:33.80#ibcon#about to write, iclass 40, count 2 2006.280.07:59:33.80#ibcon#wrote, iclass 40, count 2 2006.280.07:59:33.80#ibcon#about to read 3, iclass 40, count 2 2006.280.07:59:33.82#ibcon#read 3, iclass 40, count 2 2006.280.07:59:33.82#ibcon#about to read 4, iclass 40, count 2 2006.280.07:59:33.82#ibcon#read 4, iclass 40, count 2 2006.280.07:59:33.82#ibcon#about to read 5, iclass 40, count 2 2006.280.07:59:33.82#ibcon#read 5, iclass 40, count 2 2006.280.07:59:33.82#ibcon#about to read 6, iclass 40, count 2 2006.280.07:59:33.82#ibcon#read 6, iclass 40, count 2 2006.280.07:59:33.82#ibcon#end of sib2, iclass 40, count 2 2006.280.07:59:33.82#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:59:33.82#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:59:33.82#ibcon#[25=AT04-06\r\n] 2006.280.07:59:33.82#ibcon#*before write, iclass 40, count 2 2006.280.07:59:33.82#ibcon#enter sib2, iclass 40, count 2 2006.280.07:59:33.82#ibcon#flushed, iclass 40, count 2 2006.280.07:59:33.82#ibcon#about to write, iclass 40, count 2 2006.280.07:59:33.82#ibcon#wrote, iclass 40, count 2 2006.280.07:59:33.82#ibcon#about to read 3, iclass 40, count 2 2006.280.07:59:33.85#ibcon#read 3, iclass 40, count 2 2006.280.07:59:33.85#ibcon#about to read 4, iclass 40, count 2 2006.280.07:59:33.85#ibcon#read 4, iclass 40, count 2 2006.280.07:59:33.85#ibcon#about to read 5, iclass 40, count 2 2006.280.07:59:33.85#ibcon#read 5, iclass 40, count 2 2006.280.07:59:33.85#ibcon#about to read 6, iclass 40, count 2 2006.280.07:59:33.85#ibcon#read 6, iclass 40, count 2 2006.280.07:59:33.85#ibcon#end of sib2, iclass 40, count 2 2006.280.07:59:33.85#ibcon#*after write, iclass 40, count 2 2006.280.07:59:33.85#ibcon#*before return 0, iclass 40, count 2 2006.280.07:59:33.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:33.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:33.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:59:33.85#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:33.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:33.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:33.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:33.97#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:59:33.97#ibcon#first serial, iclass 40, count 0 2006.280.07:59:33.97#ibcon#enter sib2, iclass 40, count 0 2006.280.07:59:33.97#ibcon#flushed, iclass 40, count 0 2006.280.07:59:33.97#ibcon#about to write, iclass 40, count 0 2006.280.07:59:33.97#ibcon#wrote, iclass 40, count 0 2006.280.07:59:33.97#ibcon#about to read 3, iclass 40, count 0 2006.280.07:59:33.99#ibcon#read 3, iclass 40, count 0 2006.280.07:59:33.99#ibcon#about to read 4, iclass 40, count 0 2006.280.07:59:33.99#ibcon#read 4, iclass 40, count 0 2006.280.07:59:33.99#ibcon#about to read 5, iclass 40, count 0 2006.280.07:59:33.99#ibcon#read 5, iclass 40, count 0 2006.280.07:59:33.99#ibcon#about to read 6, iclass 40, count 0 2006.280.07:59:33.99#ibcon#read 6, iclass 40, count 0 2006.280.07:59:33.99#ibcon#end of sib2, iclass 40, count 0 2006.280.07:59:33.99#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:59:33.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:59:33.99#ibcon#[25=USB\r\n] 2006.280.07:59:33.99#ibcon#*before write, iclass 40, count 0 2006.280.07:59:33.99#ibcon#enter sib2, iclass 40, count 0 2006.280.07:59:33.99#ibcon#flushed, iclass 40, count 0 2006.280.07:59:33.99#ibcon#about to write, iclass 40, count 0 2006.280.07:59:33.99#ibcon#wrote, iclass 40, count 0 2006.280.07:59:33.99#ibcon#about to read 3, iclass 40, count 0 2006.280.07:59:34.02#ibcon#read 3, iclass 40, count 0 2006.280.07:59:34.02#ibcon#about to read 4, iclass 40, count 0 2006.280.07:59:34.02#ibcon#read 4, iclass 40, count 0 2006.280.07:59:34.02#ibcon#about to read 5, iclass 40, count 0 2006.280.07:59:34.02#ibcon#read 5, iclass 40, count 0 2006.280.07:59:34.02#ibcon#about to read 6, iclass 40, count 0 2006.280.07:59:34.02#ibcon#read 6, iclass 40, count 0 2006.280.07:59:34.02#ibcon#end of sib2, iclass 40, count 0 2006.280.07:59:34.02#ibcon#*after write, iclass 40, count 0 2006.280.07:59:34.02#ibcon#*before return 0, iclass 40, count 0 2006.280.07:59:34.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:34.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:34.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:59:34.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:59:34.02$vc4f8/valo=5,652.99 2006.280.07:59:34.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:59:34.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:59:34.02#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:34.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:34.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:34.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:34.02#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:59:34.02#ibcon#first serial, iclass 4, count 0 2006.280.07:59:34.02#ibcon#enter sib2, iclass 4, count 0 2006.280.07:59:34.02#ibcon#flushed, iclass 4, count 0 2006.280.07:59:34.02#ibcon#about to write, iclass 4, count 0 2006.280.07:59:34.02#ibcon#wrote, iclass 4, count 0 2006.280.07:59:34.02#ibcon#about to read 3, iclass 4, count 0 2006.280.07:59:34.04#ibcon#read 3, iclass 4, count 0 2006.280.07:59:34.04#ibcon#about to read 4, iclass 4, count 0 2006.280.07:59:34.04#ibcon#read 4, iclass 4, count 0 2006.280.07:59:34.04#ibcon#about to read 5, iclass 4, count 0 2006.280.07:59:34.04#ibcon#read 5, iclass 4, count 0 2006.280.07:59:34.04#ibcon#about to read 6, iclass 4, count 0 2006.280.07:59:34.04#ibcon#read 6, iclass 4, count 0 2006.280.07:59:34.04#ibcon#end of sib2, iclass 4, count 0 2006.280.07:59:34.04#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:59:34.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:59:34.04#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.07:59:34.04#ibcon#*before write, iclass 4, count 0 2006.280.07:59:34.04#ibcon#enter sib2, iclass 4, count 0 2006.280.07:59:34.04#ibcon#flushed, iclass 4, count 0 2006.280.07:59:34.04#ibcon#about to write, iclass 4, count 0 2006.280.07:59:34.04#ibcon#wrote, iclass 4, count 0 2006.280.07:59:34.04#ibcon#about to read 3, iclass 4, count 0 2006.280.07:59:34.08#ibcon#read 3, iclass 4, count 0 2006.280.07:59:34.08#ibcon#about to read 4, iclass 4, count 0 2006.280.07:59:34.08#ibcon#read 4, iclass 4, count 0 2006.280.07:59:34.08#ibcon#about to read 5, iclass 4, count 0 2006.280.07:59:34.08#ibcon#read 5, iclass 4, count 0 2006.280.07:59:34.08#ibcon#about to read 6, iclass 4, count 0 2006.280.07:59:34.08#ibcon#read 6, iclass 4, count 0 2006.280.07:59:34.08#ibcon#end of sib2, iclass 4, count 0 2006.280.07:59:34.08#ibcon#*after write, iclass 4, count 0 2006.280.07:59:34.08#ibcon#*before return 0, iclass 4, count 0 2006.280.07:59:34.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:34.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:34.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:59:34.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:59:34.08$vc4f8/va=5,7 2006.280.07:59:34.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:59:34.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:59:34.08#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:34.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:34.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:34.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:34.14#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:59:34.14#ibcon#first serial, iclass 6, count 2 2006.280.07:59:34.14#ibcon#enter sib2, iclass 6, count 2 2006.280.07:59:34.14#ibcon#flushed, iclass 6, count 2 2006.280.07:59:34.14#ibcon#about to write, iclass 6, count 2 2006.280.07:59:34.14#ibcon#wrote, iclass 6, count 2 2006.280.07:59:34.14#ibcon#about to read 3, iclass 6, count 2 2006.280.07:59:34.16#ibcon#read 3, iclass 6, count 2 2006.280.07:59:34.16#ibcon#about to read 4, iclass 6, count 2 2006.280.07:59:34.16#ibcon#read 4, iclass 6, count 2 2006.280.07:59:34.16#ibcon#about to read 5, iclass 6, count 2 2006.280.07:59:34.16#ibcon#read 5, iclass 6, count 2 2006.280.07:59:34.16#ibcon#about to read 6, iclass 6, count 2 2006.280.07:59:34.16#ibcon#read 6, iclass 6, count 2 2006.280.07:59:34.16#ibcon#end of sib2, iclass 6, count 2 2006.280.07:59:34.16#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:59:34.16#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:59:34.16#ibcon#[25=AT05-07\r\n] 2006.280.07:59:34.16#ibcon#*before write, iclass 6, count 2 2006.280.07:59:34.16#ibcon#enter sib2, iclass 6, count 2 2006.280.07:59:34.16#ibcon#flushed, iclass 6, count 2 2006.280.07:59:34.16#ibcon#about to write, iclass 6, count 2 2006.280.07:59:34.16#ibcon#wrote, iclass 6, count 2 2006.280.07:59:34.16#ibcon#about to read 3, iclass 6, count 2 2006.280.07:59:34.19#ibcon#read 3, iclass 6, count 2 2006.280.07:59:34.19#ibcon#about to read 4, iclass 6, count 2 2006.280.07:59:34.19#ibcon#read 4, iclass 6, count 2 2006.280.07:59:34.19#ibcon#about to read 5, iclass 6, count 2 2006.280.07:59:34.19#ibcon#read 5, iclass 6, count 2 2006.280.07:59:34.19#ibcon#about to read 6, iclass 6, count 2 2006.280.07:59:34.19#ibcon#read 6, iclass 6, count 2 2006.280.07:59:34.19#ibcon#end of sib2, iclass 6, count 2 2006.280.07:59:34.19#ibcon#*after write, iclass 6, count 2 2006.280.07:59:34.19#ibcon#*before return 0, iclass 6, count 2 2006.280.07:59:34.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:34.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:34.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:59:34.19#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:34.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:34.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:34.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:34.31#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:59:34.31#ibcon#first serial, iclass 6, count 0 2006.280.07:59:34.31#ibcon#enter sib2, iclass 6, count 0 2006.280.07:59:34.31#ibcon#flushed, iclass 6, count 0 2006.280.07:59:34.31#ibcon#about to write, iclass 6, count 0 2006.280.07:59:34.31#ibcon#wrote, iclass 6, count 0 2006.280.07:59:34.31#ibcon#about to read 3, iclass 6, count 0 2006.280.07:59:34.33#ibcon#read 3, iclass 6, count 0 2006.280.07:59:34.33#ibcon#about to read 4, iclass 6, count 0 2006.280.07:59:34.33#ibcon#read 4, iclass 6, count 0 2006.280.07:59:34.33#ibcon#about to read 5, iclass 6, count 0 2006.280.07:59:34.33#ibcon#read 5, iclass 6, count 0 2006.280.07:59:34.33#ibcon#about to read 6, iclass 6, count 0 2006.280.07:59:34.33#ibcon#read 6, iclass 6, count 0 2006.280.07:59:34.33#ibcon#end of sib2, iclass 6, count 0 2006.280.07:59:34.33#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:59:34.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:59:34.33#ibcon#[25=USB\r\n] 2006.280.07:59:34.33#ibcon#*before write, iclass 6, count 0 2006.280.07:59:34.33#ibcon#enter sib2, iclass 6, count 0 2006.280.07:59:34.33#ibcon#flushed, iclass 6, count 0 2006.280.07:59:34.33#ibcon#about to write, iclass 6, count 0 2006.280.07:59:34.33#ibcon#wrote, iclass 6, count 0 2006.280.07:59:34.33#ibcon#about to read 3, iclass 6, count 0 2006.280.07:59:34.36#ibcon#read 3, iclass 6, count 0 2006.280.07:59:34.36#ibcon#about to read 4, iclass 6, count 0 2006.280.07:59:34.36#ibcon#read 4, iclass 6, count 0 2006.280.07:59:34.36#ibcon#about to read 5, iclass 6, count 0 2006.280.07:59:34.36#ibcon#read 5, iclass 6, count 0 2006.280.07:59:34.36#ibcon#about to read 6, iclass 6, count 0 2006.280.07:59:34.36#ibcon#read 6, iclass 6, count 0 2006.280.07:59:34.36#ibcon#end of sib2, iclass 6, count 0 2006.280.07:59:34.36#ibcon#*after write, iclass 6, count 0 2006.280.07:59:34.36#ibcon#*before return 0, iclass 6, count 0 2006.280.07:59:34.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:34.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:34.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:59:34.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:59:34.36$vc4f8/valo=6,772.99 2006.280.07:59:34.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:59:34.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:59:34.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:34.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:34.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:34.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:34.36#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:59:34.36#ibcon#first serial, iclass 10, count 0 2006.280.07:59:34.36#ibcon#enter sib2, iclass 10, count 0 2006.280.07:59:34.36#ibcon#flushed, iclass 10, count 0 2006.280.07:59:34.36#ibcon#about to write, iclass 10, count 0 2006.280.07:59:34.36#ibcon#wrote, iclass 10, count 0 2006.280.07:59:34.36#ibcon#about to read 3, iclass 10, count 0 2006.280.07:59:34.38#ibcon#read 3, iclass 10, count 0 2006.280.07:59:34.38#ibcon#about to read 4, iclass 10, count 0 2006.280.07:59:34.38#ibcon#read 4, iclass 10, count 0 2006.280.07:59:34.38#ibcon#about to read 5, iclass 10, count 0 2006.280.07:59:34.38#ibcon#read 5, iclass 10, count 0 2006.280.07:59:34.38#ibcon#about to read 6, iclass 10, count 0 2006.280.07:59:34.38#ibcon#read 6, iclass 10, count 0 2006.280.07:59:34.38#ibcon#end of sib2, iclass 10, count 0 2006.280.07:59:34.38#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:59:34.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:59:34.38#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.07:59:34.38#ibcon#*before write, iclass 10, count 0 2006.280.07:59:34.38#ibcon#enter sib2, iclass 10, count 0 2006.280.07:59:34.38#ibcon#flushed, iclass 10, count 0 2006.280.07:59:34.38#ibcon#about to write, iclass 10, count 0 2006.280.07:59:34.38#ibcon#wrote, iclass 10, count 0 2006.280.07:59:34.38#ibcon#about to read 3, iclass 10, count 0 2006.280.07:59:34.42#ibcon#read 3, iclass 10, count 0 2006.280.07:59:34.42#ibcon#about to read 4, iclass 10, count 0 2006.280.07:59:34.42#ibcon#read 4, iclass 10, count 0 2006.280.07:59:34.42#ibcon#about to read 5, iclass 10, count 0 2006.280.07:59:34.42#ibcon#read 5, iclass 10, count 0 2006.280.07:59:34.42#ibcon#about to read 6, iclass 10, count 0 2006.280.07:59:34.42#ibcon#read 6, iclass 10, count 0 2006.280.07:59:34.42#ibcon#end of sib2, iclass 10, count 0 2006.280.07:59:34.42#ibcon#*after write, iclass 10, count 0 2006.280.07:59:34.42#ibcon#*before return 0, iclass 10, count 0 2006.280.07:59:34.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:34.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:34.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:59:34.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:59:34.42$vc4f8/va=6,6 2006.280.07:59:34.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:59:34.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:59:34.42#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:34.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:34.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:34.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:34.48#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:59:34.48#ibcon#first serial, iclass 12, count 2 2006.280.07:59:34.48#ibcon#enter sib2, iclass 12, count 2 2006.280.07:59:34.48#ibcon#flushed, iclass 12, count 2 2006.280.07:59:34.48#ibcon#about to write, iclass 12, count 2 2006.280.07:59:34.48#ibcon#wrote, iclass 12, count 2 2006.280.07:59:34.48#ibcon#about to read 3, iclass 12, count 2 2006.280.07:59:34.50#ibcon#read 3, iclass 12, count 2 2006.280.07:59:34.50#ibcon#about to read 4, iclass 12, count 2 2006.280.07:59:34.50#ibcon#read 4, iclass 12, count 2 2006.280.07:59:34.50#ibcon#about to read 5, iclass 12, count 2 2006.280.07:59:34.50#ibcon#read 5, iclass 12, count 2 2006.280.07:59:34.50#ibcon#about to read 6, iclass 12, count 2 2006.280.07:59:34.50#ibcon#read 6, iclass 12, count 2 2006.280.07:59:34.50#ibcon#end of sib2, iclass 12, count 2 2006.280.07:59:34.50#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:59:34.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:59:34.50#ibcon#[25=AT06-06\r\n] 2006.280.07:59:34.50#ibcon#*before write, iclass 12, count 2 2006.280.07:59:34.50#ibcon#enter sib2, iclass 12, count 2 2006.280.07:59:34.50#ibcon#flushed, iclass 12, count 2 2006.280.07:59:34.50#ibcon#about to write, iclass 12, count 2 2006.280.07:59:34.50#ibcon#wrote, iclass 12, count 2 2006.280.07:59:34.50#ibcon#about to read 3, iclass 12, count 2 2006.280.07:59:34.53#ibcon#read 3, iclass 12, count 2 2006.280.07:59:34.53#ibcon#about to read 4, iclass 12, count 2 2006.280.07:59:34.53#ibcon#read 4, iclass 12, count 2 2006.280.07:59:34.53#ibcon#about to read 5, iclass 12, count 2 2006.280.07:59:34.53#ibcon#read 5, iclass 12, count 2 2006.280.07:59:34.53#ibcon#about to read 6, iclass 12, count 2 2006.280.07:59:34.53#ibcon#read 6, iclass 12, count 2 2006.280.07:59:34.53#ibcon#end of sib2, iclass 12, count 2 2006.280.07:59:34.53#ibcon#*after write, iclass 12, count 2 2006.280.07:59:34.53#ibcon#*before return 0, iclass 12, count 2 2006.280.07:59:34.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:34.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:34.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:59:34.53#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:34.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:34.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:34.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:34.65#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:59:34.65#ibcon#first serial, iclass 12, count 0 2006.280.07:59:34.65#ibcon#enter sib2, iclass 12, count 0 2006.280.07:59:34.65#ibcon#flushed, iclass 12, count 0 2006.280.07:59:34.65#ibcon#about to write, iclass 12, count 0 2006.280.07:59:34.65#ibcon#wrote, iclass 12, count 0 2006.280.07:59:34.65#ibcon#about to read 3, iclass 12, count 0 2006.280.07:59:34.67#ibcon#read 3, iclass 12, count 0 2006.280.07:59:34.67#ibcon#about to read 4, iclass 12, count 0 2006.280.07:59:34.67#ibcon#read 4, iclass 12, count 0 2006.280.07:59:34.67#ibcon#about to read 5, iclass 12, count 0 2006.280.07:59:34.67#ibcon#read 5, iclass 12, count 0 2006.280.07:59:34.67#ibcon#about to read 6, iclass 12, count 0 2006.280.07:59:34.67#ibcon#read 6, iclass 12, count 0 2006.280.07:59:34.67#ibcon#end of sib2, iclass 12, count 0 2006.280.07:59:34.67#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:59:34.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:59:34.67#ibcon#[25=USB\r\n] 2006.280.07:59:34.67#ibcon#*before write, iclass 12, count 0 2006.280.07:59:34.67#ibcon#enter sib2, iclass 12, count 0 2006.280.07:59:34.67#ibcon#flushed, iclass 12, count 0 2006.280.07:59:34.67#ibcon#about to write, iclass 12, count 0 2006.280.07:59:34.67#ibcon#wrote, iclass 12, count 0 2006.280.07:59:34.67#ibcon#about to read 3, iclass 12, count 0 2006.280.07:59:34.70#ibcon#read 3, iclass 12, count 0 2006.280.07:59:34.70#ibcon#about to read 4, iclass 12, count 0 2006.280.07:59:34.70#ibcon#read 4, iclass 12, count 0 2006.280.07:59:34.70#ibcon#about to read 5, iclass 12, count 0 2006.280.07:59:34.70#ibcon#read 5, iclass 12, count 0 2006.280.07:59:34.70#ibcon#about to read 6, iclass 12, count 0 2006.280.07:59:34.70#ibcon#read 6, iclass 12, count 0 2006.280.07:59:34.70#ibcon#end of sib2, iclass 12, count 0 2006.280.07:59:34.70#ibcon#*after write, iclass 12, count 0 2006.280.07:59:34.70#ibcon#*before return 0, iclass 12, count 0 2006.280.07:59:34.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:34.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:34.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:59:34.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:59:34.70$vc4f8/valo=7,832.99 2006.280.07:59:34.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:59:34.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:59:34.70#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:34.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:34.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:34.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:34.70#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:59:34.70#ibcon#first serial, iclass 14, count 0 2006.280.07:59:34.70#ibcon#enter sib2, iclass 14, count 0 2006.280.07:59:34.70#ibcon#flushed, iclass 14, count 0 2006.280.07:59:34.70#ibcon#about to write, iclass 14, count 0 2006.280.07:59:34.70#ibcon#wrote, iclass 14, count 0 2006.280.07:59:34.70#ibcon#about to read 3, iclass 14, count 0 2006.280.07:59:34.72#ibcon#read 3, iclass 14, count 0 2006.280.07:59:34.72#ibcon#about to read 4, iclass 14, count 0 2006.280.07:59:34.72#ibcon#read 4, iclass 14, count 0 2006.280.07:59:34.72#ibcon#about to read 5, iclass 14, count 0 2006.280.07:59:34.72#ibcon#read 5, iclass 14, count 0 2006.280.07:59:34.72#ibcon#about to read 6, iclass 14, count 0 2006.280.07:59:34.72#ibcon#read 6, iclass 14, count 0 2006.280.07:59:34.72#ibcon#end of sib2, iclass 14, count 0 2006.280.07:59:34.72#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:59:34.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:59:34.72#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.07:59:34.72#ibcon#*before write, iclass 14, count 0 2006.280.07:59:34.72#ibcon#enter sib2, iclass 14, count 0 2006.280.07:59:34.72#ibcon#flushed, iclass 14, count 0 2006.280.07:59:34.72#ibcon#about to write, iclass 14, count 0 2006.280.07:59:34.72#ibcon#wrote, iclass 14, count 0 2006.280.07:59:34.72#ibcon#about to read 3, iclass 14, count 0 2006.280.07:59:34.76#ibcon#read 3, iclass 14, count 0 2006.280.07:59:34.76#ibcon#about to read 4, iclass 14, count 0 2006.280.07:59:34.76#ibcon#read 4, iclass 14, count 0 2006.280.07:59:34.76#ibcon#about to read 5, iclass 14, count 0 2006.280.07:59:34.76#ibcon#read 5, iclass 14, count 0 2006.280.07:59:34.76#ibcon#about to read 6, iclass 14, count 0 2006.280.07:59:34.76#ibcon#read 6, iclass 14, count 0 2006.280.07:59:34.76#ibcon#end of sib2, iclass 14, count 0 2006.280.07:59:34.76#ibcon#*after write, iclass 14, count 0 2006.280.07:59:34.76#ibcon#*before return 0, iclass 14, count 0 2006.280.07:59:34.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:34.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:34.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:59:34.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:59:34.76$vc4f8/va=7,6 2006.280.07:59:34.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.07:59:34.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.07:59:34.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:34.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:34.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:34.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:34.82#ibcon#enter wrdev, iclass 16, count 2 2006.280.07:59:34.82#ibcon#first serial, iclass 16, count 2 2006.280.07:59:34.82#ibcon#enter sib2, iclass 16, count 2 2006.280.07:59:34.82#ibcon#flushed, iclass 16, count 2 2006.280.07:59:34.82#ibcon#about to write, iclass 16, count 2 2006.280.07:59:34.82#ibcon#wrote, iclass 16, count 2 2006.280.07:59:34.82#ibcon#about to read 3, iclass 16, count 2 2006.280.07:59:34.84#ibcon#read 3, iclass 16, count 2 2006.280.07:59:34.84#ibcon#about to read 4, iclass 16, count 2 2006.280.07:59:34.84#ibcon#read 4, iclass 16, count 2 2006.280.07:59:34.84#ibcon#about to read 5, iclass 16, count 2 2006.280.07:59:34.84#ibcon#read 5, iclass 16, count 2 2006.280.07:59:34.84#ibcon#about to read 6, iclass 16, count 2 2006.280.07:59:34.84#ibcon#read 6, iclass 16, count 2 2006.280.07:59:34.84#ibcon#end of sib2, iclass 16, count 2 2006.280.07:59:34.84#ibcon#*mode == 0, iclass 16, count 2 2006.280.07:59:34.84#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.07:59:34.84#ibcon#[25=AT07-06\r\n] 2006.280.07:59:34.84#ibcon#*before write, iclass 16, count 2 2006.280.07:59:34.84#ibcon#enter sib2, iclass 16, count 2 2006.280.07:59:34.84#ibcon#flushed, iclass 16, count 2 2006.280.07:59:34.84#ibcon#about to write, iclass 16, count 2 2006.280.07:59:34.84#ibcon#wrote, iclass 16, count 2 2006.280.07:59:34.84#ibcon#about to read 3, iclass 16, count 2 2006.280.07:59:34.87#ibcon#read 3, iclass 16, count 2 2006.280.07:59:34.87#ibcon#about to read 4, iclass 16, count 2 2006.280.07:59:34.87#ibcon#read 4, iclass 16, count 2 2006.280.07:59:34.87#ibcon#about to read 5, iclass 16, count 2 2006.280.07:59:34.87#ibcon#read 5, iclass 16, count 2 2006.280.07:59:34.87#ibcon#about to read 6, iclass 16, count 2 2006.280.07:59:34.87#ibcon#read 6, iclass 16, count 2 2006.280.07:59:34.87#ibcon#end of sib2, iclass 16, count 2 2006.280.07:59:34.87#ibcon#*after write, iclass 16, count 2 2006.280.07:59:34.87#ibcon#*before return 0, iclass 16, count 2 2006.280.07:59:34.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:34.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:34.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.07:59:34.87#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:34.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:59:34.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:59:34.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:59:34.99#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:59:34.99#ibcon#first serial, iclass 16, count 0 2006.280.07:59:34.99#ibcon#enter sib2, iclass 16, count 0 2006.280.07:59:34.99#ibcon#flushed, iclass 16, count 0 2006.280.07:59:34.99#ibcon#about to write, iclass 16, count 0 2006.280.07:59:34.99#ibcon#wrote, iclass 16, count 0 2006.280.07:59:34.99#ibcon#about to read 3, iclass 16, count 0 2006.280.07:59:35.01#ibcon#read 3, iclass 16, count 0 2006.280.07:59:35.01#ibcon#about to read 4, iclass 16, count 0 2006.280.07:59:35.01#ibcon#read 4, iclass 16, count 0 2006.280.07:59:35.01#ibcon#about to read 5, iclass 16, count 0 2006.280.07:59:35.01#ibcon#read 5, iclass 16, count 0 2006.280.07:59:35.01#ibcon#about to read 6, iclass 16, count 0 2006.280.07:59:35.01#ibcon#read 6, iclass 16, count 0 2006.280.07:59:35.01#ibcon#end of sib2, iclass 16, count 0 2006.280.07:59:35.01#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:59:35.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:59:35.01#ibcon#[25=USB\r\n] 2006.280.07:59:35.01#ibcon#*before write, iclass 16, count 0 2006.280.07:59:35.01#ibcon#enter sib2, iclass 16, count 0 2006.280.07:59:35.01#ibcon#flushed, iclass 16, count 0 2006.280.07:59:35.01#ibcon#about to write, iclass 16, count 0 2006.280.07:59:35.01#ibcon#wrote, iclass 16, count 0 2006.280.07:59:35.01#ibcon#about to read 3, iclass 16, count 0 2006.280.07:59:35.04#ibcon#read 3, iclass 16, count 0 2006.280.07:59:35.04#ibcon#about to read 4, iclass 16, count 0 2006.280.07:59:35.04#ibcon#read 4, iclass 16, count 0 2006.280.07:59:35.04#ibcon#about to read 5, iclass 16, count 0 2006.280.07:59:35.04#ibcon#read 5, iclass 16, count 0 2006.280.07:59:35.04#ibcon#about to read 6, iclass 16, count 0 2006.280.07:59:35.04#ibcon#read 6, iclass 16, count 0 2006.280.07:59:35.04#ibcon#end of sib2, iclass 16, count 0 2006.280.07:59:35.04#ibcon#*after write, iclass 16, count 0 2006.280.07:59:35.04#ibcon#*before return 0, iclass 16, count 0 2006.280.07:59:35.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:59:35.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.07:59:35.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:59:35.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:59:35.04$vc4f8/valo=8,852.99 2006.280.07:59:35.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.07:59:35.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.07:59:35.04#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:35.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:59:35.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:59:35.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:59:35.04#ibcon#enter wrdev, iclass 18, count 0 2006.280.07:59:35.04#ibcon#first serial, iclass 18, count 0 2006.280.07:59:35.04#ibcon#enter sib2, iclass 18, count 0 2006.280.07:59:35.04#ibcon#flushed, iclass 18, count 0 2006.280.07:59:35.04#ibcon#about to write, iclass 18, count 0 2006.280.07:59:35.04#ibcon#wrote, iclass 18, count 0 2006.280.07:59:35.04#ibcon#about to read 3, iclass 18, count 0 2006.280.07:59:35.06#ibcon#read 3, iclass 18, count 0 2006.280.07:59:35.06#ibcon#about to read 4, iclass 18, count 0 2006.280.07:59:35.06#ibcon#read 4, iclass 18, count 0 2006.280.07:59:35.06#ibcon#about to read 5, iclass 18, count 0 2006.280.07:59:35.06#ibcon#read 5, iclass 18, count 0 2006.280.07:59:35.06#ibcon#about to read 6, iclass 18, count 0 2006.280.07:59:35.06#ibcon#read 6, iclass 18, count 0 2006.280.07:59:35.06#ibcon#end of sib2, iclass 18, count 0 2006.280.07:59:35.06#ibcon#*mode == 0, iclass 18, count 0 2006.280.07:59:35.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.07:59:35.06#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.07:59:35.06#ibcon#*before write, iclass 18, count 0 2006.280.07:59:35.06#ibcon#enter sib2, iclass 18, count 0 2006.280.07:59:35.06#ibcon#flushed, iclass 18, count 0 2006.280.07:59:35.06#ibcon#about to write, iclass 18, count 0 2006.280.07:59:35.06#ibcon#wrote, iclass 18, count 0 2006.280.07:59:35.06#ibcon#about to read 3, iclass 18, count 0 2006.280.07:59:35.10#ibcon#read 3, iclass 18, count 0 2006.280.07:59:35.10#ibcon#about to read 4, iclass 18, count 0 2006.280.07:59:35.10#ibcon#read 4, iclass 18, count 0 2006.280.07:59:35.10#ibcon#about to read 5, iclass 18, count 0 2006.280.07:59:35.10#ibcon#read 5, iclass 18, count 0 2006.280.07:59:35.10#ibcon#about to read 6, iclass 18, count 0 2006.280.07:59:35.10#ibcon#read 6, iclass 18, count 0 2006.280.07:59:35.10#ibcon#end of sib2, iclass 18, count 0 2006.280.07:59:35.10#ibcon#*after write, iclass 18, count 0 2006.280.07:59:35.10#ibcon#*before return 0, iclass 18, count 0 2006.280.07:59:35.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:59:35.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.07:59:35.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.07:59:35.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.07:59:35.10$vc4f8/va=8,6 2006.280.07:59:35.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.07:59:35.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.07:59:35.10#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:35.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:59:35.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:59:35.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:59:35.16#ibcon#enter wrdev, iclass 20, count 2 2006.280.07:59:35.16#ibcon#first serial, iclass 20, count 2 2006.280.07:59:35.16#ibcon#enter sib2, iclass 20, count 2 2006.280.07:59:35.16#ibcon#flushed, iclass 20, count 2 2006.280.07:59:35.16#ibcon#about to write, iclass 20, count 2 2006.280.07:59:35.16#ibcon#wrote, iclass 20, count 2 2006.280.07:59:35.16#ibcon#about to read 3, iclass 20, count 2 2006.280.07:59:35.18#ibcon#read 3, iclass 20, count 2 2006.280.07:59:35.18#ibcon#about to read 4, iclass 20, count 2 2006.280.07:59:35.18#ibcon#read 4, iclass 20, count 2 2006.280.07:59:35.18#ibcon#about to read 5, iclass 20, count 2 2006.280.07:59:35.18#ibcon#read 5, iclass 20, count 2 2006.280.07:59:35.18#ibcon#about to read 6, iclass 20, count 2 2006.280.07:59:35.18#ibcon#read 6, iclass 20, count 2 2006.280.07:59:35.18#ibcon#end of sib2, iclass 20, count 2 2006.280.07:59:35.18#ibcon#*mode == 0, iclass 20, count 2 2006.280.07:59:35.18#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.07:59:35.18#ibcon#[25=AT08-06\r\n] 2006.280.07:59:35.18#ibcon#*before write, iclass 20, count 2 2006.280.07:59:35.18#ibcon#enter sib2, iclass 20, count 2 2006.280.07:59:35.18#ibcon#flushed, iclass 20, count 2 2006.280.07:59:35.18#ibcon#about to write, iclass 20, count 2 2006.280.07:59:35.18#ibcon#wrote, iclass 20, count 2 2006.280.07:59:35.18#ibcon#about to read 3, iclass 20, count 2 2006.280.07:59:35.21#ibcon#read 3, iclass 20, count 2 2006.280.07:59:35.21#ibcon#about to read 4, iclass 20, count 2 2006.280.07:59:35.21#ibcon#read 4, iclass 20, count 2 2006.280.07:59:35.21#ibcon#about to read 5, iclass 20, count 2 2006.280.07:59:35.21#ibcon#read 5, iclass 20, count 2 2006.280.07:59:35.21#ibcon#about to read 6, iclass 20, count 2 2006.280.07:59:35.21#ibcon#read 6, iclass 20, count 2 2006.280.07:59:35.21#ibcon#end of sib2, iclass 20, count 2 2006.280.07:59:35.21#ibcon#*after write, iclass 20, count 2 2006.280.07:59:35.21#ibcon#*before return 0, iclass 20, count 2 2006.280.07:59:35.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:59:35.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.07:59:35.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.07:59:35.21#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:35.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:59:35.32#abcon#<5=/14 1.7 4.9 20.95 61 987.1\r\n> 2006.280.07:59:35.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:59:35.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:59:35.33#ibcon#enter wrdev, iclass 20, count 0 2006.280.07:59:35.33#ibcon#first serial, iclass 20, count 0 2006.280.07:59:35.33#ibcon#enter sib2, iclass 20, count 0 2006.280.07:59:35.33#ibcon#flushed, iclass 20, count 0 2006.280.07:59:35.33#ibcon#about to write, iclass 20, count 0 2006.280.07:59:35.33#ibcon#wrote, iclass 20, count 0 2006.280.07:59:35.33#ibcon#about to read 3, iclass 20, count 0 2006.280.07:59:35.34#abcon#{5=INTERFACE CLEAR} 2006.280.07:59:35.36#ibcon#read 3, iclass 20, count 0 2006.280.07:59:35.36#ibcon#about to read 4, iclass 20, count 0 2006.280.07:59:35.36#ibcon#read 4, iclass 20, count 0 2006.280.07:59:35.36#ibcon#about to read 5, iclass 20, count 0 2006.280.07:59:35.36#ibcon#read 5, iclass 20, count 0 2006.280.07:59:35.36#ibcon#about to read 6, iclass 20, count 0 2006.280.07:59:35.36#ibcon#read 6, iclass 20, count 0 2006.280.07:59:35.36#ibcon#end of sib2, iclass 20, count 0 2006.280.07:59:35.36#ibcon#*mode == 0, iclass 20, count 0 2006.280.07:59:35.36#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.07:59:35.36#ibcon#[25=USB\r\n] 2006.280.07:59:35.36#ibcon#*before write, iclass 20, count 0 2006.280.07:59:35.36#ibcon#enter sib2, iclass 20, count 0 2006.280.07:59:35.36#ibcon#flushed, iclass 20, count 0 2006.280.07:59:35.36#ibcon#about to write, iclass 20, count 0 2006.280.07:59:35.36#ibcon#wrote, iclass 20, count 0 2006.280.07:59:35.36#ibcon#about to read 3, iclass 20, count 0 2006.280.07:59:35.39#ibcon#read 3, iclass 20, count 0 2006.280.07:59:35.39#ibcon#about to read 4, iclass 20, count 0 2006.280.07:59:35.39#ibcon#read 4, iclass 20, count 0 2006.280.07:59:35.39#ibcon#about to read 5, iclass 20, count 0 2006.280.07:59:35.39#ibcon#read 5, iclass 20, count 0 2006.280.07:59:35.39#ibcon#about to read 6, iclass 20, count 0 2006.280.07:59:35.39#ibcon#read 6, iclass 20, count 0 2006.280.07:59:35.39#ibcon#end of sib2, iclass 20, count 0 2006.280.07:59:35.39#ibcon#*after write, iclass 20, count 0 2006.280.07:59:35.39#ibcon#*before return 0, iclass 20, count 0 2006.280.07:59:35.39#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:59:35.39#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.07:59:35.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.07:59:35.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.07:59:35.39$vc4f8/vblo=1,632.99 2006.280.07:59:35.39#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.07:59:35.39#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.07:59:35.39#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:35.39#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:35.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:35.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:35.39#ibcon#enter wrdev, iclass 26, count 0 2006.280.07:59:35.39#ibcon#first serial, iclass 26, count 0 2006.280.07:59:35.39#ibcon#enter sib2, iclass 26, count 0 2006.280.07:59:35.39#ibcon#flushed, iclass 26, count 0 2006.280.07:59:35.39#ibcon#about to write, iclass 26, count 0 2006.280.07:59:35.39#ibcon#wrote, iclass 26, count 0 2006.280.07:59:35.39#ibcon#about to read 3, iclass 26, count 0 2006.280.07:59:35.40#abcon#[5=S1D000X0/0*\r\n] 2006.280.07:59:35.41#ibcon#read 3, iclass 26, count 0 2006.280.07:59:35.41#ibcon#about to read 4, iclass 26, count 0 2006.280.07:59:35.41#ibcon#read 4, iclass 26, count 0 2006.280.07:59:35.41#ibcon#about to read 5, iclass 26, count 0 2006.280.07:59:35.41#ibcon#read 5, iclass 26, count 0 2006.280.07:59:35.41#ibcon#about to read 6, iclass 26, count 0 2006.280.07:59:35.41#ibcon#read 6, iclass 26, count 0 2006.280.07:59:35.41#ibcon#end of sib2, iclass 26, count 0 2006.280.07:59:35.41#ibcon#*mode == 0, iclass 26, count 0 2006.280.07:59:35.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.07:59:35.41#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.07:59:35.41#ibcon#*before write, iclass 26, count 0 2006.280.07:59:35.41#ibcon#enter sib2, iclass 26, count 0 2006.280.07:59:35.41#ibcon#flushed, iclass 26, count 0 2006.280.07:59:35.41#ibcon#about to write, iclass 26, count 0 2006.280.07:59:35.41#ibcon#wrote, iclass 26, count 0 2006.280.07:59:35.41#ibcon#about to read 3, iclass 26, count 0 2006.280.07:59:35.45#ibcon#read 3, iclass 26, count 0 2006.280.07:59:35.45#ibcon#about to read 4, iclass 26, count 0 2006.280.07:59:35.45#ibcon#read 4, iclass 26, count 0 2006.280.07:59:35.45#ibcon#about to read 5, iclass 26, count 0 2006.280.07:59:35.45#ibcon#read 5, iclass 26, count 0 2006.280.07:59:35.45#ibcon#about to read 6, iclass 26, count 0 2006.280.07:59:35.45#ibcon#read 6, iclass 26, count 0 2006.280.07:59:35.45#ibcon#end of sib2, iclass 26, count 0 2006.280.07:59:35.45#ibcon#*after write, iclass 26, count 0 2006.280.07:59:35.45#ibcon#*before return 0, iclass 26, count 0 2006.280.07:59:35.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:35.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.07:59:35.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.07:59:35.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.07:59:35.45$vc4f8/vb=1,4 2006.280.07:59:35.45#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.07:59:35.45#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.07:59:35.45#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:35.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:35.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:35.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:35.45#ibcon#enter wrdev, iclass 28, count 2 2006.280.07:59:35.45#ibcon#first serial, iclass 28, count 2 2006.280.07:59:35.45#ibcon#enter sib2, iclass 28, count 2 2006.280.07:59:35.45#ibcon#flushed, iclass 28, count 2 2006.280.07:59:35.45#ibcon#about to write, iclass 28, count 2 2006.280.07:59:35.45#ibcon#wrote, iclass 28, count 2 2006.280.07:59:35.45#ibcon#about to read 3, iclass 28, count 2 2006.280.07:59:35.47#ibcon#read 3, iclass 28, count 2 2006.280.07:59:35.48#ibcon#about to read 4, iclass 28, count 2 2006.280.07:59:35.48#ibcon#read 4, iclass 28, count 2 2006.280.07:59:35.48#ibcon#about to read 5, iclass 28, count 2 2006.280.07:59:35.48#ibcon#read 5, iclass 28, count 2 2006.280.07:59:35.48#ibcon#about to read 6, iclass 28, count 2 2006.280.07:59:35.48#ibcon#read 6, iclass 28, count 2 2006.280.07:59:35.48#ibcon#end of sib2, iclass 28, count 2 2006.280.07:59:35.48#ibcon#*mode == 0, iclass 28, count 2 2006.280.07:59:35.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.07:59:35.48#ibcon#[27=AT01-04\r\n] 2006.280.07:59:35.48#ibcon#*before write, iclass 28, count 2 2006.280.07:59:35.48#ibcon#enter sib2, iclass 28, count 2 2006.280.07:59:35.48#ibcon#flushed, iclass 28, count 2 2006.280.07:59:35.48#ibcon#about to write, iclass 28, count 2 2006.280.07:59:35.48#ibcon#wrote, iclass 28, count 2 2006.280.07:59:35.48#ibcon#about to read 3, iclass 28, count 2 2006.280.07:59:35.51#ibcon#read 3, iclass 28, count 2 2006.280.07:59:35.51#ibcon#about to read 4, iclass 28, count 2 2006.280.07:59:35.51#ibcon#read 4, iclass 28, count 2 2006.280.07:59:35.51#ibcon#about to read 5, iclass 28, count 2 2006.280.07:59:35.51#ibcon#read 5, iclass 28, count 2 2006.280.07:59:35.51#ibcon#about to read 6, iclass 28, count 2 2006.280.07:59:35.51#ibcon#read 6, iclass 28, count 2 2006.280.07:59:35.51#ibcon#end of sib2, iclass 28, count 2 2006.280.07:59:35.51#ibcon#*after write, iclass 28, count 2 2006.280.07:59:35.51#ibcon#*before return 0, iclass 28, count 2 2006.280.07:59:35.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:35.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.07:59:35.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.07:59:35.51#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:35.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:35.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:35.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:35.63#ibcon#enter wrdev, iclass 28, count 0 2006.280.07:59:35.63#ibcon#first serial, iclass 28, count 0 2006.280.07:59:35.63#ibcon#enter sib2, iclass 28, count 0 2006.280.07:59:35.63#ibcon#flushed, iclass 28, count 0 2006.280.07:59:35.63#ibcon#about to write, iclass 28, count 0 2006.280.07:59:35.63#ibcon#wrote, iclass 28, count 0 2006.280.07:59:35.63#ibcon#about to read 3, iclass 28, count 0 2006.280.07:59:35.65#ibcon#read 3, iclass 28, count 0 2006.280.07:59:35.65#ibcon#about to read 4, iclass 28, count 0 2006.280.07:59:35.65#ibcon#read 4, iclass 28, count 0 2006.280.07:59:35.65#ibcon#about to read 5, iclass 28, count 0 2006.280.07:59:35.65#ibcon#read 5, iclass 28, count 0 2006.280.07:59:35.65#ibcon#about to read 6, iclass 28, count 0 2006.280.07:59:35.65#ibcon#read 6, iclass 28, count 0 2006.280.07:59:35.65#ibcon#end of sib2, iclass 28, count 0 2006.280.07:59:35.65#ibcon#*mode == 0, iclass 28, count 0 2006.280.07:59:35.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.07:59:35.65#ibcon#[27=USB\r\n] 2006.280.07:59:35.65#ibcon#*before write, iclass 28, count 0 2006.280.07:59:35.65#ibcon#enter sib2, iclass 28, count 0 2006.280.07:59:35.65#ibcon#flushed, iclass 28, count 0 2006.280.07:59:35.65#ibcon#about to write, iclass 28, count 0 2006.280.07:59:35.65#ibcon#wrote, iclass 28, count 0 2006.280.07:59:35.65#ibcon#about to read 3, iclass 28, count 0 2006.280.07:59:35.68#ibcon#read 3, iclass 28, count 0 2006.280.07:59:35.68#ibcon#about to read 4, iclass 28, count 0 2006.280.07:59:35.68#ibcon#read 4, iclass 28, count 0 2006.280.07:59:35.68#ibcon#about to read 5, iclass 28, count 0 2006.280.07:59:35.68#ibcon#read 5, iclass 28, count 0 2006.280.07:59:35.68#ibcon#about to read 6, iclass 28, count 0 2006.280.07:59:35.68#ibcon#read 6, iclass 28, count 0 2006.280.07:59:35.68#ibcon#end of sib2, iclass 28, count 0 2006.280.07:59:35.68#ibcon#*after write, iclass 28, count 0 2006.280.07:59:35.68#ibcon#*before return 0, iclass 28, count 0 2006.280.07:59:35.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:35.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.07:59:35.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.07:59:35.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.07:59:35.68$vc4f8/vblo=2,640.99 2006.280.07:59:35.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.07:59:35.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.07:59:35.68#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:35.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:35.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:35.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:35.68#ibcon#enter wrdev, iclass 30, count 0 2006.280.07:59:35.68#ibcon#first serial, iclass 30, count 0 2006.280.07:59:35.68#ibcon#enter sib2, iclass 30, count 0 2006.280.07:59:35.68#ibcon#flushed, iclass 30, count 0 2006.280.07:59:35.68#ibcon#about to write, iclass 30, count 0 2006.280.07:59:35.68#ibcon#wrote, iclass 30, count 0 2006.280.07:59:35.68#ibcon#about to read 3, iclass 30, count 0 2006.280.07:59:35.70#ibcon#read 3, iclass 30, count 0 2006.280.07:59:35.70#ibcon#about to read 4, iclass 30, count 0 2006.280.07:59:35.70#ibcon#read 4, iclass 30, count 0 2006.280.07:59:35.70#ibcon#about to read 5, iclass 30, count 0 2006.280.07:59:35.70#ibcon#read 5, iclass 30, count 0 2006.280.07:59:35.70#ibcon#about to read 6, iclass 30, count 0 2006.280.07:59:35.70#ibcon#read 6, iclass 30, count 0 2006.280.07:59:35.70#ibcon#end of sib2, iclass 30, count 0 2006.280.07:59:35.70#ibcon#*mode == 0, iclass 30, count 0 2006.280.07:59:35.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.07:59:35.70#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.07:59:35.70#ibcon#*before write, iclass 30, count 0 2006.280.07:59:35.70#ibcon#enter sib2, iclass 30, count 0 2006.280.07:59:35.70#ibcon#flushed, iclass 30, count 0 2006.280.07:59:35.70#ibcon#about to write, iclass 30, count 0 2006.280.07:59:35.70#ibcon#wrote, iclass 30, count 0 2006.280.07:59:35.70#ibcon#about to read 3, iclass 30, count 0 2006.280.07:59:35.74#ibcon#read 3, iclass 30, count 0 2006.280.07:59:35.74#ibcon#about to read 4, iclass 30, count 0 2006.280.07:59:35.74#ibcon#read 4, iclass 30, count 0 2006.280.07:59:35.74#ibcon#about to read 5, iclass 30, count 0 2006.280.07:59:35.74#ibcon#read 5, iclass 30, count 0 2006.280.07:59:35.74#ibcon#about to read 6, iclass 30, count 0 2006.280.07:59:35.74#ibcon#read 6, iclass 30, count 0 2006.280.07:59:35.74#ibcon#end of sib2, iclass 30, count 0 2006.280.07:59:35.74#ibcon#*after write, iclass 30, count 0 2006.280.07:59:35.74#ibcon#*before return 0, iclass 30, count 0 2006.280.07:59:35.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:35.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.07:59:35.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.07:59:35.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.07:59:35.75$vc4f8/vb=2,5 2006.280.07:59:35.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.07:59:35.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.07:59:35.75#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:35.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:35.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:35.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:35.79#ibcon#enter wrdev, iclass 32, count 2 2006.280.07:59:35.79#ibcon#first serial, iclass 32, count 2 2006.280.07:59:35.79#ibcon#enter sib2, iclass 32, count 2 2006.280.07:59:35.79#ibcon#flushed, iclass 32, count 2 2006.280.07:59:35.79#ibcon#about to write, iclass 32, count 2 2006.280.07:59:35.79#ibcon#wrote, iclass 32, count 2 2006.280.07:59:35.79#ibcon#about to read 3, iclass 32, count 2 2006.280.07:59:35.81#ibcon#read 3, iclass 32, count 2 2006.280.07:59:35.81#ibcon#about to read 4, iclass 32, count 2 2006.280.07:59:35.81#ibcon#read 4, iclass 32, count 2 2006.280.07:59:35.81#ibcon#about to read 5, iclass 32, count 2 2006.280.07:59:35.81#ibcon#read 5, iclass 32, count 2 2006.280.07:59:35.81#ibcon#about to read 6, iclass 32, count 2 2006.280.07:59:35.81#ibcon#read 6, iclass 32, count 2 2006.280.07:59:35.81#ibcon#end of sib2, iclass 32, count 2 2006.280.07:59:35.81#ibcon#*mode == 0, iclass 32, count 2 2006.280.07:59:35.81#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.07:59:35.81#ibcon#[27=AT02-05\r\n] 2006.280.07:59:35.81#ibcon#*before write, iclass 32, count 2 2006.280.07:59:35.81#ibcon#enter sib2, iclass 32, count 2 2006.280.07:59:35.81#ibcon#flushed, iclass 32, count 2 2006.280.07:59:35.81#ibcon#about to write, iclass 32, count 2 2006.280.07:59:35.81#ibcon#wrote, iclass 32, count 2 2006.280.07:59:35.81#ibcon#about to read 3, iclass 32, count 2 2006.280.07:59:35.84#ibcon#read 3, iclass 32, count 2 2006.280.07:59:35.84#ibcon#about to read 4, iclass 32, count 2 2006.280.07:59:35.84#ibcon#read 4, iclass 32, count 2 2006.280.07:59:35.84#ibcon#about to read 5, iclass 32, count 2 2006.280.07:59:35.84#ibcon#read 5, iclass 32, count 2 2006.280.07:59:35.84#ibcon#about to read 6, iclass 32, count 2 2006.280.07:59:35.84#ibcon#read 6, iclass 32, count 2 2006.280.07:59:35.84#ibcon#end of sib2, iclass 32, count 2 2006.280.07:59:35.84#ibcon#*after write, iclass 32, count 2 2006.280.07:59:35.84#ibcon#*before return 0, iclass 32, count 2 2006.280.07:59:35.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:35.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.07:59:35.84#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.07:59:35.84#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:35.84#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:35.96#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:35.96#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:35.96#ibcon#enter wrdev, iclass 32, count 0 2006.280.07:59:35.96#ibcon#first serial, iclass 32, count 0 2006.280.07:59:35.96#ibcon#enter sib2, iclass 32, count 0 2006.280.07:59:35.96#ibcon#flushed, iclass 32, count 0 2006.280.07:59:35.96#ibcon#about to write, iclass 32, count 0 2006.280.07:59:35.96#ibcon#wrote, iclass 32, count 0 2006.280.07:59:35.96#ibcon#about to read 3, iclass 32, count 0 2006.280.07:59:35.98#ibcon#read 3, iclass 32, count 0 2006.280.07:59:35.98#ibcon#about to read 4, iclass 32, count 0 2006.280.07:59:35.98#ibcon#read 4, iclass 32, count 0 2006.280.07:59:35.98#ibcon#about to read 5, iclass 32, count 0 2006.280.07:59:35.98#ibcon#read 5, iclass 32, count 0 2006.280.07:59:35.98#ibcon#about to read 6, iclass 32, count 0 2006.280.07:59:35.98#ibcon#read 6, iclass 32, count 0 2006.280.07:59:35.98#ibcon#end of sib2, iclass 32, count 0 2006.280.07:59:35.98#ibcon#*mode == 0, iclass 32, count 0 2006.280.07:59:35.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.07:59:35.98#ibcon#[27=USB\r\n] 2006.280.07:59:35.98#ibcon#*before write, iclass 32, count 0 2006.280.07:59:35.98#ibcon#enter sib2, iclass 32, count 0 2006.280.07:59:35.98#ibcon#flushed, iclass 32, count 0 2006.280.07:59:35.98#ibcon#about to write, iclass 32, count 0 2006.280.07:59:35.98#ibcon#wrote, iclass 32, count 0 2006.280.07:59:35.98#ibcon#about to read 3, iclass 32, count 0 2006.280.07:59:36.01#ibcon#read 3, iclass 32, count 0 2006.280.07:59:36.01#ibcon#about to read 4, iclass 32, count 0 2006.280.07:59:36.01#ibcon#read 4, iclass 32, count 0 2006.280.07:59:36.01#ibcon#about to read 5, iclass 32, count 0 2006.280.07:59:36.01#ibcon#read 5, iclass 32, count 0 2006.280.07:59:36.01#ibcon#about to read 6, iclass 32, count 0 2006.280.07:59:36.01#ibcon#read 6, iclass 32, count 0 2006.280.07:59:36.01#ibcon#end of sib2, iclass 32, count 0 2006.280.07:59:36.01#ibcon#*after write, iclass 32, count 0 2006.280.07:59:36.01#ibcon#*before return 0, iclass 32, count 0 2006.280.07:59:36.01#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:36.01#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.07:59:36.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.07:59:36.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.07:59:36.01$vc4f8/vblo=3,656.99 2006.280.07:59:36.01#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.07:59:36.01#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.07:59:36.01#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:36.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:36.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:36.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:36.01#ibcon#enter wrdev, iclass 34, count 0 2006.280.07:59:36.01#ibcon#first serial, iclass 34, count 0 2006.280.07:59:36.01#ibcon#enter sib2, iclass 34, count 0 2006.280.07:59:36.01#ibcon#flushed, iclass 34, count 0 2006.280.07:59:36.01#ibcon#about to write, iclass 34, count 0 2006.280.07:59:36.01#ibcon#wrote, iclass 34, count 0 2006.280.07:59:36.01#ibcon#about to read 3, iclass 34, count 0 2006.280.07:59:36.03#ibcon#read 3, iclass 34, count 0 2006.280.07:59:36.03#ibcon#about to read 4, iclass 34, count 0 2006.280.07:59:36.03#ibcon#read 4, iclass 34, count 0 2006.280.07:59:36.03#ibcon#about to read 5, iclass 34, count 0 2006.280.07:59:36.03#ibcon#read 5, iclass 34, count 0 2006.280.07:59:36.03#ibcon#about to read 6, iclass 34, count 0 2006.280.07:59:36.03#ibcon#read 6, iclass 34, count 0 2006.280.07:59:36.03#ibcon#end of sib2, iclass 34, count 0 2006.280.07:59:36.03#ibcon#*mode == 0, iclass 34, count 0 2006.280.07:59:36.03#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.07:59:36.03#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.07:59:36.03#ibcon#*before write, iclass 34, count 0 2006.280.07:59:36.03#ibcon#enter sib2, iclass 34, count 0 2006.280.07:59:36.03#ibcon#flushed, iclass 34, count 0 2006.280.07:59:36.03#ibcon#about to write, iclass 34, count 0 2006.280.07:59:36.03#ibcon#wrote, iclass 34, count 0 2006.280.07:59:36.03#ibcon#about to read 3, iclass 34, count 0 2006.280.07:59:36.07#ibcon#read 3, iclass 34, count 0 2006.280.07:59:36.07#ibcon#about to read 4, iclass 34, count 0 2006.280.07:59:36.07#ibcon#read 4, iclass 34, count 0 2006.280.07:59:36.07#ibcon#about to read 5, iclass 34, count 0 2006.280.07:59:36.07#ibcon#read 5, iclass 34, count 0 2006.280.07:59:36.07#ibcon#about to read 6, iclass 34, count 0 2006.280.07:59:36.07#ibcon#read 6, iclass 34, count 0 2006.280.07:59:36.07#ibcon#end of sib2, iclass 34, count 0 2006.280.07:59:36.07#ibcon#*after write, iclass 34, count 0 2006.280.07:59:36.07#ibcon#*before return 0, iclass 34, count 0 2006.280.07:59:36.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:36.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.07:59:36.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.07:59:36.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.07:59:36.07$vc4f8/vb=3,4 2006.280.07:59:36.09#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.07:59:36.09#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.07:59:36.09#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:36.09#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:36.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:36.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:36.13#ibcon#enter wrdev, iclass 36, count 2 2006.280.07:59:36.13#ibcon#first serial, iclass 36, count 2 2006.280.07:59:36.13#ibcon#enter sib2, iclass 36, count 2 2006.280.07:59:36.13#ibcon#flushed, iclass 36, count 2 2006.280.07:59:36.13#ibcon#about to write, iclass 36, count 2 2006.280.07:59:36.13#ibcon#wrote, iclass 36, count 2 2006.280.07:59:36.13#ibcon#about to read 3, iclass 36, count 2 2006.280.07:59:36.15#ibcon#read 3, iclass 36, count 2 2006.280.07:59:36.15#ibcon#about to read 4, iclass 36, count 2 2006.280.07:59:36.15#ibcon#read 4, iclass 36, count 2 2006.280.07:59:36.15#ibcon#about to read 5, iclass 36, count 2 2006.280.07:59:36.15#ibcon#read 5, iclass 36, count 2 2006.280.07:59:36.15#ibcon#about to read 6, iclass 36, count 2 2006.280.07:59:36.15#ibcon#read 6, iclass 36, count 2 2006.280.07:59:36.15#ibcon#end of sib2, iclass 36, count 2 2006.280.07:59:36.15#ibcon#*mode == 0, iclass 36, count 2 2006.280.07:59:36.15#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.07:59:36.15#ibcon#[27=AT03-04\r\n] 2006.280.07:59:36.15#ibcon#*before write, iclass 36, count 2 2006.280.07:59:36.15#ibcon#enter sib2, iclass 36, count 2 2006.280.07:59:36.15#ibcon#flushed, iclass 36, count 2 2006.280.07:59:36.15#ibcon#about to write, iclass 36, count 2 2006.280.07:59:36.15#ibcon#wrote, iclass 36, count 2 2006.280.07:59:36.15#ibcon#about to read 3, iclass 36, count 2 2006.280.07:59:36.18#ibcon#read 3, iclass 36, count 2 2006.280.07:59:36.18#ibcon#about to read 4, iclass 36, count 2 2006.280.07:59:36.18#ibcon#read 4, iclass 36, count 2 2006.280.07:59:36.18#ibcon#about to read 5, iclass 36, count 2 2006.280.07:59:36.18#ibcon#read 5, iclass 36, count 2 2006.280.07:59:36.18#ibcon#about to read 6, iclass 36, count 2 2006.280.07:59:36.18#ibcon#read 6, iclass 36, count 2 2006.280.07:59:36.18#ibcon#end of sib2, iclass 36, count 2 2006.280.07:59:36.18#ibcon#*after write, iclass 36, count 2 2006.280.07:59:36.18#ibcon#*before return 0, iclass 36, count 2 2006.280.07:59:36.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:36.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.07:59:36.18#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.07:59:36.18#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:36.18#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:36.30#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:36.30#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:36.30#ibcon#enter wrdev, iclass 36, count 0 2006.280.07:59:36.30#ibcon#first serial, iclass 36, count 0 2006.280.07:59:36.30#ibcon#enter sib2, iclass 36, count 0 2006.280.07:59:36.30#ibcon#flushed, iclass 36, count 0 2006.280.07:59:36.30#ibcon#about to write, iclass 36, count 0 2006.280.07:59:36.30#ibcon#wrote, iclass 36, count 0 2006.280.07:59:36.30#ibcon#about to read 3, iclass 36, count 0 2006.280.07:59:36.32#ibcon#read 3, iclass 36, count 0 2006.280.07:59:36.32#ibcon#about to read 4, iclass 36, count 0 2006.280.07:59:36.32#ibcon#read 4, iclass 36, count 0 2006.280.07:59:36.32#ibcon#about to read 5, iclass 36, count 0 2006.280.07:59:36.32#ibcon#read 5, iclass 36, count 0 2006.280.07:59:36.32#ibcon#about to read 6, iclass 36, count 0 2006.280.07:59:36.32#ibcon#read 6, iclass 36, count 0 2006.280.07:59:36.32#ibcon#end of sib2, iclass 36, count 0 2006.280.07:59:36.32#ibcon#*mode == 0, iclass 36, count 0 2006.280.07:59:36.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.07:59:36.32#ibcon#[27=USB\r\n] 2006.280.07:59:36.32#ibcon#*before write, iclass 36, count 0 2006.280.07:59:36.32#ibcon#enter sib2, iclass 36, count 0 2006.280.07:59:36.32#ibcon#flushed, iclass 36, count 0 2006.280.07:59:36.32#ibcon#about to write, iclass 36, count 0 2006.280.07:59:36.32#ibcon#wrote, iclass 36, count 0 2006.280.07:59:36.32#ibcon#about to read 3, iclass 36, count 0 2006.280.07:59:36.36#ibcon#read 3, iclass 36, count 0 2006.280.07:59:36.36#ibcon#about to read 4, iclass 36, count 0 2006.280.07:59:36.36#ibcon#read 4, iclass 36, count 0 2006.280.07:59:36.36#ibcon#about to read 5, iclass 36, count 0 2006.280.07:59:36.36#ibcon#read 5, iclass 36, count 0 2006.280.07:59:36.36#ibcon#about to read 6, iclass 36, count 0 2006.280.07:59:36.36#ibcon#read 6, iclass 36, count 0 2006.280.07:59:36.36#ibcon#end of sib2, iclass 36, count 0 2006.280.07:59:36.36#ibcon#*after write, iclass 36, count 0 2006.280.07:59:36.36#ibcon#*before return 0, iclass 36, count 0 2006.280.07:59:36.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:36.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.07:59:36.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.07:59:36.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.07:59:36.36$vc4f8/vblo=4,712.99 2006.280.07:59:36.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.07:59:36.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.07:59:36.36#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:36.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:36.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:36.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:36.36#ibcon#enter wrdev, iclass 38, count 0 2006.280.07:59:36.36#ibcon#first serial, iclass 38, count 0 2006.280.07:59:36.36#ibcon#enter sib2, iclass 38, count 0 2006.280.07:59:36.36#ibcon#flushed, iclass 38, count 0 2006.280.07:59:36.36#ibcon#about to write, iclass 38, count 0 2006.280.07:59:36.36#ibcon#wrote, iclass 38, count 0 2006.280.07:59:36.36#ibcon#about to read 3, iclass 38, count 0 2006.280.07:59:36.37#ibcon#read 3, iclass 38, count 0 2006.280.07:59:36.37#ibcon#about to read 4, iclass 38, count 0 2006.280.07:59:36.37#ibcon#read 4, iclass 38, count 0 2006.280.07:59:36.37#ibcon#about to read 5, iclass 38, count 0 2006.280.07:59:36.37#ibcon#read 5, iclass 38, count 0 2006.280.07:59:36.37#ibcon#about to read 6, iclass 38, count 0 2006.280.07:59:36.37#ibcon#read 6, iclass 38, count 0 2006.280.07:59:36.37#ibcon#end of sib2, iclass 38, count 0 2006.280.07:59:36.37#ibcon#*mode == 0, iclass 38, count 0 2006.280.07:59:36.37#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.07:59:36.37#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.07:59:36.39#ibcon#*before write, iclass 38, count 0 2006.280.07:59:36.39#ibcon#enter sib2, iclass 38, count 0 2006.280.07:59:36.39#ibcon#flushed, iclass 38, count 0 2006.280.07:59:36.39#ibcon#about to write, iclass 38, count 0 2006.280.07:59:36.39#ibcon#wrote, iclass 38, count 0 2006.280.07:59:36.39#ibcon#about to read 3, iclass 38, count 0 2006.280.07:59:36.44#ibcon#read 3, iclass 38, count 0 2006.280.07:59:36.44#ibcon#about to read 4, iclass 38, count 0 2006.280.07:59:36.44#ibcon#read 4, iclass 38, count 0 2006.280.07:59:36.44#ibcon#about to read 5, iclass 38, count 0 2006.280.07:59:36.44#ibcon#read 5, iclass 38, count 0 2006.280.07:59:36.44#ibcon#about to read 6, iclass 38, count 0 2006.280.07:59:36.44#ibcon#read 6, iclass 38, count 0 2006.280.07:59:36.44#ibcon#end of sib2, iclass 38, count 0 2006.280.07:59:36.44#ibcon#*after write, iclass 38, count 0 2006.280.07:59:36.44#ibcon#*before return 0, iclass 38, count 0 2006.280.07:59:36.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:36.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.07:59:36.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.07:59:36.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.07:59:36.44$vc4f8/vb=4,4 2006.280.07:59:36.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.07:59:36.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.07:59:36.44#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:36.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:36.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:36.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:36.48#ibcon#enter wrdev, iclass 40, count 2 2006.280.07:59:36.48#ibcon#first serial, iclass 40, count 2 2006.280.07:59:36.48#ibcon#enter sib2, iclass 40, count 2 2006.280.07:59:36.48#ibcon#flushed, iclass 40, count 2 2006.280.07:59:36.48#ibcon#about to write, iclass 40, count 2 2006.280.07:59:36.48#ibcon#wrote, iclass 40, count 2 2006.280.07:59:36.48#ibcon#about to read 3, iclass 40, count 2 2006.280.07:59:36.50#ibcon#read 3, iclass 40, count 2 2006.280.07:59:36.50#ibcon#about to read 4, iclass 40, count 2 2006.280.07:59:36.50#ibcon#read 4, iclass 40, count 2 2006.280.07:59:36.50#ibcon#about to read 5, iclass 40, count 2 2006.280.07:59:36.50#ibcon#read 5, iclass 40, count 2 2006.280.07:59:36.50#ibcon#about to read 6, iclass 40, count 2 2006.280.07:59:36.50#ibcon#read 6, iclass 40, count 2 2006.280.07:59:36.50#ibcon#end of sib2, iclass 40, count 2 2006.280.07:59:36.50#ibcon#*mode == 0, iclass 40, count 2 2006.280.07:59:36.50#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.07:59:36.50#ibcon#[27=AT04-04\r\n] 2006.280.07:59:36.50#ibcon#*before write, iclass 40, count 2 2006.280.07:59:36.50#ibcon#enter sib2, iclass 40, count 2 2006.280.07:59:36.50#ibcon#flushed, iclass 40, count 2 2006.280.07:59:36.50#ibcon#about to write, iclass 40, count 2 2006.280.07:59:36.50#ibcon#wrote, iclass 40, count 2 2006.280.07:59:36.50#ibcon#about to read 3, iclass 40, count 2 2006.280.07:59:36.53#ibcon#read 3, iclass 40, count 2 2006.280.07:59:36.53#ibcon#about to read 4, iclass 40, count 2 2006.280.07:59:36.53#ibcon#read 4, iclass 40, count 2 2006.280.07:59:36.53#ibcon#about to read 5, iclass 40, count 2 2006.280.07:59:36.53#ibcon#read 5, iclass 40, count 2 2006.280.07:59:36.53#ibcon#about to read 6, iclass 40, count 2 2006.280.07:59:36.53#ibcon#read 6, iclass 40, count 2 2006.280.07:59:36.53#ibcon#end of sib2, iclass 40, count 2 2006.280.07:59:36.53#ibcon#*after write, iclass 40, count 2 2006.280.07:59:36.53#ibcon#*before return 0, iclass 40, count 2 2006.280.07:59:36.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:36.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.07:59:36.53#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.07:59:36.53#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:36.53#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:36.65#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:36.65#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:36.65#ibcon#enter wrdev, iclass 40, count 0 2006.280.07:59:36.65#ibcon#first serial, iclass 40, count 0 2006.280.07:59:36.65#ibcon#enter sib2, iclass 40, count 0 2006.280.07:59:36.65#ibcon#flushed, iclass 40, count 0 2006.280.07:59:36.65#ibcon#about to write, iclass 40, count 0 2006.280.07:59:36.65#ibcon#wrote, iclass 40, count 0 2006.280.07:59:36.65#ibcon#about to read 3, iclass 40, count 0 2006.280.07:59:36.67#ibcon#read 3, iclass 40, count 0 2006.280.07:59:36.67#ibcon#about to read 4, iclass 40, count 0 2006.280.07:59:36.67#ibcon#read 4, iclass 40, count 0 2006.280.07:59:36.67#ibcon#about to read 5, iclass 40, count 0 2006.280.07:59:36.67#ibcon#read 5, iclass 40, count 0 2006.280.07:59:36.67#ibcon#about to read 6, iclass 40, count 0 2006.280.07:59:36.67#ibcon#read 6, iclass 40, count 0 2006.280.07:59:36.67#ibcon#end of sib2, iclass 40, count 0 2006.280.07:59:36.67#ibcon#*mode == 0, iclass 40, count 0 2006.280.07:59:36.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.07:59:36.67#ibcon#[27=USB\r\n] 2006.280.07:59:36.67#ibcon#*before write, iclass 40, count 0 2006.280.07:59:36.67#ibcon#enter sib2, iclass 40, count 0 2006.280.07:59:36.67#ibcon#flushed, iclass 40, count 0 2006.280.07:59:36.67#ibcon#about to write, iclass 40, count 0 2006.280.07:59:36.67#ibcon#wrote, iclass 40, count 0 2006.280.07:59:36.67#ibcon#about to read 3, iclass 40, count 0 2006.280.07:59:36.70#ibcon#read 3, iclass 40, count 0 2006.280.07:59:36.70#ibcon#about to read 4, iclass 40, count 0 2006.280.07:59:36.70#ibcon#read 4, iclass 40, count 0 2006.280.07:59:36.70#ibcon#about to read 5, iclass 40, count 0 2006.280.07:59:36.70#ibcon#read 5, iclass 40, count 0 2006.280.07:59:36.70#ibcon#about to read 6, iclass 40, count 0 2006.280.07:59:36.70#ibcon#read 6, iclass 40, count 0 2006.280.07:59:36.70#ibcon#end of sib2, iclass 40, count 0 2006.280.07:59:36.70#ibcon#*after write, iclass 40, count 0 2006.280.07:59:36.70#ibcon#*before return 0, iclass 40, count 0 2006.280.07:59:36.70#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:36.70#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.07:59:36.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.07:59:36.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.07:59:36.70$vc4f8/vblo=5,744.99 2006.280.07:59:36.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.07:59:36.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.07:59:36.70#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:36.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:36.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:36.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:36.70#ibcon#enter wrdev, iclass 4, count 0 2006.280.07:59:36.70#ibcon#first serial, iclass 4, count 0 2006.280.07:59:36.70#ibcon#enter sib2, iclass 4, count 0 2006.280.07:59:36.70#ibcon#flushed, iclass 4, count 0 2006.280.07:59:36.70#ibcon#about to write, iclass 4, count 0 2006.280.07:59:36.70#ibcon#wrote, iclass 4, count 0 2006.280.07:59:36.70#ibcon#about to read 3, iclass 4, count 0 2006.280.07:59:36.72#ibcon#read 3, iclass 4, count 0 2006.280.07:59:36.72#ibcon#about to read 4, iclass 4, count 0 2006.280.07:59:36.72#ibcon#read 4, iclass 4, count 0 2006.280.07:59:36.72#ibcon#about to read 5, iclass 4, count 0 2006.280.07:59:36.72#ibcon#read 5, iclass 4, count 0 2006.280.07:59:36.72#ibcon#about to read 6, iclass 4, count 0 2006.280.07:59:36.72#ibcon#read 6, iclass 4, count 0 2006.280.07:59:36.72#ibcon#end of sib2, iclass 4, count 0 2006.280.07:59:36.72#ibcon#*mode == 0, iclass 4, count 0 2006.280.07:59:36.72#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.07:59:36.72#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.07:59:36.72#ibcon#*before write, iclass 4, count 0 2006.280.07:59:36.72#ibcon#enter sib2, iclass 4, count 0 2006.280.07:59:36.72#ibcon#flushed, iclass 4, count 0 2006.280.07:59:36.72#ibcon#about to write, iclass 4, count 0 2006.280.07:59:36.72#ibcon#wrote, iclass 4, count 0 2006.280.07:59:36.72#ibcon#about to read 3, iclass 4, count 0 2006.280.07:59:36.76#ibcon#read 3, iclass 4, count 0 2006.280.07:59:36.76#ibcon#about to read 4, iclass 4, count 0 2006.280.07:59:36.76#ibcon#read 4, iclass 4, count 0 2006.280.07:59:36.76#ibcon#about to read 5, iclass 4, count 0 2006.280.07:59:36.76#ibcon#read 5, iclass 4, count 0 2006.280.07:59:36.76#ibcon#about to read 6, iclass 4, count 0 2006.280.07:59:36.76#ibcon#read 6, iclass 4, count 0 2006.280.07:59:36.76#ibcon#end of sib2, iclass 4, count 0 2006.280.07:59:36.76#ibcon#*after write, iclass 4, count 0 2006.280.07:59:36.76#ibcon#*before return 0, iclass 4, count 0 2006.280.07:59:36.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:36.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.07:59:36.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.07:59:36.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.07:59:36.76$vc4f8/vb=5,4 2006.280.07:59:36.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.07:59:36.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.07:59:36.76#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:36.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:36.82#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:36.82#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:36.82#ibcon#enter wrdev, iclass 6, count 2 2006.280.07:59:36.82#ibcon#first serial, iclass 6, count 2 2006.280.07:59:36.82#ibcon#enter sib2, iclass 6, count 2 2006.280.07:59:36.82#ibcon#flushed, iclass 6, count 2 2006.280.07:59:36.82#ibcon#about to write, iclass 6, count 2 2006.280.07:59:36.82#ibcon#wrote, iclass 6, count 2 2006.280.07:59:36.82#ibcon#about to read 3, iclass 6, count 2 2006.280.07:59:36.84#ibcon#read 3, iclass 6, count 2 2006.280.07:59:36.84#ibcon#about to read 4, iclass 6, count 2 2006.280.07:59:36.84#ibcon#read 4, iclass 6, count 2 2006.280.07:59:36.84#ibcon#about to read 5, iclass 6, count 2 2006.280.07:59:36.84#ibcon#read 5, iclass 6, count 2 2006.280.07:59:36.84#ibcon#about to read 6, iclass 6, count 2 2006.280.07:59:36.84#ibcon#read 6, iclass 6, count 2 2006.280.07:59:36.84#ibcon#end of sib2, iclass 6, count 2 2006.280.07:59:36.84#ibcon#*mode == 0, iclass 6, count 2 2006.280.07:59:36.84#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.07:59:36.84#ibcon#[27=AT05-04\r\n] 2006.280.07:59:36.84#ibcon#*before write, iclass 6, count 2 2006.280.07:59:36.84#ibcon#enter sib2, iclass 6, count 2 2006.280.07:59:36.84#ibcon#flushed, iclass 6, count 2 2006.280.07:59:36.84#ibcon#about to write, iclass 6, count 2 2006.280.07:59:36.84#ibcon#wrote, iclass 6, count 2 2006.280.07:59:36.84#ibcon#about to read 3, iclass 6, count 2 2006.280.07:59:36.87#ibcon#read 3, iclass 6, count 2 2006.280.07:59:36.87#ibcon#about to read 4, iclass 6, count 2 2006.280.07:59:36.87#ibcon#read 4, iclass 6, count 2 2006.280.07:59:36.87#ibcon#about to read 5, iclass 6, count 2 2006.280.07:59:36.87#ibcon#read 5, iclass 6, count 2 2006.280.07:59:36.87#ibcon#about to read 6, iclass 6, count 2 2006.280.07:59:36.87#ibcon#read 6, iclass 6, count 2 2006.280.07:59:36.87#ibcon#end of sib2, iclass 6, count 2 2006.280.07:59:36.87#ibcon#*after write, iclass 6, count 2 2006.280.07:59:36.87#ibcon#*before return 0, iclass 6, count 2 2006.280.07:59:36.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:36.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.07:59:36.87#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.07:59:36.87#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:36.87#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:36.99#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:36.99#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:36.99#ibcon#enter wrdev, iclass 6, count 0 2006.280.07:59:36.99#ibcon#first serial, iclass 6, count 0 2006.280.07:59:36.99#ibcon#enter sib2, iclass 6, count 0 2006.280.07:59:36.99#ibcon#flushed, iclass 6, count 0 2006.280.07:59:36.99#ibcon#about to write, iclass 6, count 0 2006.280.07:59:36.99#ibcon#wrote, iclass 6, count 0 2006.280.07:59:36.99#ibcon#about to read 3, iclass 6, count 0 2006.280.07:59:37.01#ibcon#read 3, iclass 6, count 0 2006.280.07:59:37.01#ibcon#about to read 4, iclass 6, count 0 2006.280.07:59:37.01#ibcon#read 4, iclass 6, count 0 2006.280.07:59:37.01#ibcon#about to read 5, iclass 6, count 0 2006.280.07:59:37.01#ibcon#read 5, iclass 6, count 0 2006.280.07:59:37.01#ibcon#about to read 6, iclass 6, count 0 2006.280.07:59:37.01#ibcon#read 6, iclass 6, count 0 2006.280.07:59:37.01#ibcon#end of sib2, iclass 6, count 0 2006.280.07:59:37.01#ibcon#*mode == 0, iclass 6, count 0 2006.280.07:59:37.01#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.07:59:37.01#ibcon#[27=USB\r\n] 2006.280.07:59:37.01#ibcon#*before write, iclass 6, count 0 2006.280.07:59:37.01#ibcon#enter sib2, iclass 6, count 0 2006.280.07:59:37.01#ibcon#flushed, iclass 6, count 0 2006.280.07:59:37.01#ibcon#about to write, iclass 6, count 0 2006.280.07:59:37.01#ibcon#wrote, iclass 6, count 0 2006.280.07:59:37.01#ibcon#about to read 3, iclass 6, count 0 2006.280.07:59:37.04#ibcon#read 3, iclass 6, count 0 2006.280.07:59:37.04#ibcon#about to read 4, iclass 6, count 0 2006.280.07:59:37.04#ibcon#read 4, iclass 6, count 0 2006.280.07:59:37.04#ibcon#about to read 5, iclass 6, count 0 2006.280.07:59:37.04#ibcon#read 5, iclass 6, count 0 2006.280.07:59:37.04#ibcon#about to read 6, iclass 6, count 0 2006.280.07:59:37.04#ibcon#read 6, iclass 6, count 0 2006.280.07:59:37.04#ibcon#end of sib2, iclass 6, count 0 2006.280.07:59:37.04#ibcon#*after write, iclass 6, count 0 2006.280.07:59:37.04#ibcon#*before return 0, iclass 6, count 0 2006.280.07:59:37.04#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:37.04#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.07:59:37.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.07:59:37.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.07:59:37.04$vc4f8/vblo=6,752.99 2006.280.07:59:37.04#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.07:59:37.04#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.07:59:37.04#ibcon#ireg 17 cls_cnt 0 2006.280.07:59:37.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:37.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:37.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:37.04#ibcon#enter wrdev, iclass 10, count 0 2006.280.07:59:37.04#ibcon#first serial, iclass 10, count 0 2006.280.07:59:37.04#ibcon#enter sib2, iclass 10, count 0 2006.280.07:59:37.04#ibcon#flushed, iclass 10, count 0 2006.280.07:59:37.04#ibcon#about to write, iclass 10, count 0 2006.280.07:59:37.04#ibcon#wrote, iclass 10, count 0 2006.280.07:59:37.04#ibcon#about to read 3, iclass 10, count 0 2006.280.07:59:37.06#ibcon#read 3, iclass 10, count 0 2006.280.07:59:37.06#ibcon#about to read 4, iclass 10, count 0 2006.280.07:59:37.06#ibcon#read 4, iclass 10, count 0 2006.280.07:59:37.06#ibcon#about to read 5, iclass 10, count 0 2006.280.07:59:37.06#ibcon#read 5, iclass 10, count 0 2006.280.07:59:37.06#ibcon#about to read 6, iclass 10, count 0 2006.280.07:59:37.06#ibcon#read 6, iclass 10, count 0 2006.280.07:59:37.06#ibcon#end of sib2, iclass 10, count 0 2006.280.07:59:37.06#ibcon#*mode == 0, iclass 10, count 0 2006.280.07:59:37.06#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.07:59:37.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.07:59:37.06#ibcon#*before write, iclass 10, count 0 2006.280.07:59:37.06#ibcon#enter sib2, iclass 10, count 0 2006.280.07:59:37.06#ibcon#flushed, iclass 10, count 0 2006.280.07:59:37.06#ibcon#about to write, iclass 10, count 0 2006.280.07:59:37.06#ibcon#wrote, iclass 10, count 0 2006.280.07:59:37.06#ibcon#about to read 3, iclass 10, count 0 2006.280.07:59:37.10#ibcon#read 3, iclass 10, count 0 2006.280.07:59:37.10#ibcon#about to read 4, iclass 10, count 0 2006.280.07:59:37.10#ibcon#read 4, iclass 10, count 0 2006.280.07:59:37.10#ibcon#about to read 5, iclass 10, count 0 2006.280.07:59:37.10#ibcon#read 5, iclass 10, count 0 2006.280.07:59:37.10#ibcon#about to read 6, iclass 10, count 0 2006.280.07:59:37.10#ibcon#read 6, iclass 10, count 0 2006.280.07:59:37.10#ibcon#end of sib2, iclass 10, count 0 2006.280.07:59:37.10#ibcon#*after write, iclass 10, count 0 2006.280.07:59:37.10#ibcon#*before return 0, iclass 10, count 0 2006.280.07:59:37.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:37.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.07:59:37.10#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.07:59:37.10#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.07:59:37.10$vc4f8/vb=6,4 2006.280.07:59:37.10#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.07:59:37.10#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.07:59:37.10#ibcon#ireg 11 cls_cnt 2 2006.280.07:59:37.10#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:37.16#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:37.16#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:37.16#ibcon#enter wrdev, iclass 12, count 2 2006.280.07:59:37.16#ibcon#first serial, iclass 12, count 2 2006.280.07:59:37.16#ibcon#enter sib2, iclass 12, count 2 2006.280.07:59:37.16#ibcon#flushed, iclass 12, count 2 2006.280.07:59:37.16#ibcon#about to write, iclass 12, count 2 2006.280.07:59:37.16#ibcon#wrote, iclass 12, count 2 2006.280.07:59:37.16#ibcon#about to read 3, iclass 12, count 2 2006.280.07:59:37.18#ibcon#read 3, iclass 12, count 2 2006.280.07:59:37.18#ibcon#about to read 4, iclass 12, count 2 2006.280.07:59:37.18#ibcon#read 4, iclass 12, count 2 2006.280.07:59:37.18#ibcon#about to read 5, iclass 12, count 2 2006.280.07:59:37.18#ibcon#read 5, iclass 12, count 2 2006.280.07:59:37.18#ibcon#about to read 6, iclass 12, count 2 2006.280.07:59:37.18#ibcon#read 6, iclass 12, count 2 2006.280.07:59:37.18#ibcon#end of sib2, iclass 12, count 2 2006.280.07:59:37.18#ibcon#*mode == 0, iclass 12, count 2 2006.280.07:59:37.18#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.07:59:37.18#ibcon#[27=AT06-04\r\n] 2006.280.07:59:37.18#ibcon#*before write, iclass 12, count 2 2006.280.07:59:37.18#ibcon#enter sib2, iclass 12, count 2 2006.280.07:59:37.18#ibcon#flushed, iclass 12, count 2 2006.280.07:59:37.18#ibcon#about to write, iclass 12, count 2 2006.280.07:59:37.18#ibcon#wrote, iclass 12, count 2 2006.280.07:59:37.18#ibcon#about to read 3, iclass 12, count 2 2006.280.07:59:37.21#ibcon#read 3, iclass 12, count 2 2006.280.07:59:37.21#ibcon#about to read 4, iclass 12, count 2 2006.280.07:59:37.21#ibcon#read 4, iclass 12, count 2 2006.280.07:59:37.21#ibcon#about to read 5, iclass 12, count 2 2006.280.07:59:37.21#ibcon#read 5, iclass 12, count 2 2006.280.07:59:37.21#ibcon#about to read 6, iclass 12, count 2 2006.280.07:59:37.21#ibcon#read 6, iclass 12, count 2 2006.280.07:59:37.21#ibcon#end of sib2, iclass 12, count 2 2006.280.07:59:37.21#ibcon#*after write, iclass 12, count 2 2006.280.07:59:37.21#ibcon#*before return 0, iclass 12, count 2 2006.280.07:59:37.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:37.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.07:59:37.21#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.07:59:37.21#ibcon#ireg 7 cls_cnt 0 2006.280.07:59:37.21#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:37.33#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:37.33#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:37.33#ibcon#enter wrdev, iclass 12, count 0 2006.280.07:59:37.33#ibcon#first serial, iclass 12, count 0 2006.280.07:59:37.33#ibcon#enter sib2, iclass 12, count 0 2006.280.07:59:37.33#ibcon#flushed, iclass 12, count 0 2006.280.07:59:37.33#ibcon#about to write, iclass 12, count 0 2006.280.07:59:37.33#ibcon#wrote, iclass 12, count 0 2006.280.07:59:37.33#ibcon#about to read 3, iclass 12, count 0 2006.280.07:59:37.35#ibcon#read 3, iclass 12, count 0 2006.280.07:59:37.35#ibcon#about to read 4, iclass 12, count 0 2006.280.07:59:37.35#ibcon#read 4, iclass 12, count 0 2006.280.07:59:37.35#ibcon#about to read 5, iclass 12, count 0 2006.280.07:59:37.35#ibcon#read 5, iclass 12, count 0 2006.280.07:59:37.35#ibcon#about to read 6, iclass 12, count 0 2006.280.07:59:37.35#ibcon#read 6, iclass 12, count 0 2006.280.07:59:37.35#ibcon#end of sib2, iclass 12, count 0 2006.280.07:59:37.35#ibcon#*mode == 0, iclass 12, count 0 2006.280.07:59:37.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.07:59:37.35#ibcon#[27=USB\r\n] 2006.280.07:59:37.35#ibcon#*before write, iclass 12, count 0 2006.280.07:59:37.35#ibcon#enter sib2, iclass 12, count 0 2006.280.07:59:37.35#ibcon#flushed, iclass 12, count 0 2006.280.07:59:37.35#ibcon#about to write, iclass 12, count 0 2006.280.07:59:37.35#ibcon#wrote, iclass 12, count 0 2006.280.07:59:37.35#ibcon#about to read 3, iclass 12, count 0 2006.280.07:59:37.38#ibcon#read 3, iclass 12, count 0 2006.280.07:59:37.38#ibcon#about to read 4, iclass 12, count 0 2006.280.07:59:37.38#ibcon#read 4, iclass 12, count 0 2006.280.07:59:37.38#ibcon#about to read 5, iclass 12, count 0 2006.280.07:59:37.38#ibcon#read 5, iclass 12, count 0 2006.280.07:59:37.38#ibcon#about to read 6, iclass 12, count 0 2006.280.07:59:37.38#ibcon#read 6, iclass 12, count 0 2006.280.07:59:37.38#ibcon#end of sib2, iclass 12, count 0 2006.280.07:59:37.38#ibcon#*after write, iclass 12, count 0 2006.280.07:59:37.38#ibcon#*before return 0, iclass 12, count 0 2006.280.07:59:37.38#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:37.38#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.07:59:37.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.07:59:37.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.07:59:37.38$vc4f8/vabw=wide 2006.280.07:59:37.38#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.07:59:37.38#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.07:59:37.38#ibcon#ireg 8 cls_cnt 0 2006.280.07:59:37.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:37.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:37.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:37.38#ibcon#enter wrdev, iclass 14, count 0 2006.280.07:59:37.38#ibcon#first serial, iclass 14, count 0 2006.280.07:59:37.38#ibcon#enter sib2, iclass 14, count 0 2006.280.07:59:37.38#ibcon#flushed, iclass 14, count 0 2006.280.07:59:37.38#ibcon#about to write, iclass 14, count 0 2006.280.07:59:37.38#ibcon#wrote, iclass 14, count 0 2006.280.07:59:37.38#ibcon#about to read 3, iclass 14, count 0 2006.280.07:59:37.40#ibcon#read 3, iclass 14, count 0 2006.280.07:59:37.40#ibcon#about to read 4, iclass 14, count 0 2006.280.07:59:37.40#ibcon#read 4, iclass 14, count 0 2006.280.07:59:37.40#ibcon#about to read 5, iclass 14, count 0 2006.280.07:59:37.40#ibcon#read 5, iclass 14, count 0 2006.280.07:59:37.40#ibcon#about to read 6, iclass 14, count 0 2006.280.07:59:37.40#ibcon#read 6, iclass 14, count 0 2006.280.07:59:37.40#ibcon#end of sib2, iclass 14, count 0 2006.280.07:59:37.40#ibcon#*mode == 0, iclass 14, count 0 2006.280.07:59:37.40#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.07:59:37.40#ibcon#[25=BW32\r\n] 2006.280.07:59:37.40#ibcon#*before write, iclass 14, count 0 2006.280.07:59:37.40#ibcon#enter sib2, iclass 14, count 0 2006.280.07:59:37.40#ibcon#flushed, iclass 14, count 0 2006.280.07:59:37.40#ibcon#about to write, iclass 14, count 0 2006.280.07:59:37.40#ibcon#wrote, iclass 14, count 0 2006.280.07:59:37.40#ibcon#about to read 3, iclass 14, count 0 2006.280.07:59:37.43#ibcon#read 3, iclass 14, count 0 2006.280.07:59:37.44#ibcon#about to read 4, iclass 14, count 0 2006.280.07:59:37.44#ibcon#read 4, iclass 14, count 0 2006.280.07:59:37.44#ibcon#about to read 5, iclass 14, count 0 2006.280.07:59:37.44#ibcon#read 5, iclass 14, count 0 2006.280.07:59:37.44#ibcon#about to read 6, iclass 14, count 0 2006.280.07:59:37.44#ibcon#read 6, iclass 14, count 0 2006.280.07:59:37.44#ibcon#end of sib2, iclass 14, count 0 2006.280.07:59:37.44#ibcon#*after write, iclass 14, count 0 2006.280.07:59:37.44#ibcon#*before return 0, iclass 14, count 0 2006.280.07:59:37.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:37.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.07:59:37.44#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.07:59:37.44#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.07:59:37.44$vc4f8/vbbw=wide 2006.280.07:59:37.44#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.07:59:37.44#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.07:59:37.44#ibcon#ireg 8 cls_cnt 0 2006.280.07:59:37.44#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:59:37.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:59:37.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:59:37.49#ibcon#enter wrdev, iclass 16, count 0 2006.280.07:59:37.49#ibcon#first serial, iclass 16, count 0 2006.280.07:59:37.49#ibcon#enter sib2, iclass 16, count 0 2006.280.07:59:37.49#ibcon#flushed, iclass 16, count 0 2006.280.07:59:37.49#ibcon#about to write, iclass 16, count 0 2006.280.07:59:37.49#ibcon#wrote, iclass 16, count 0 2006.280.07:59:37.49#ibcon#about to read 3, iclass 16, count 0 2006.280.07:59:37.51#ibcon#read 3, iclass 16, count 0 2006.280.07:59:37.51#ibcon#about to read 4, iclass 16, count 0 2006.280.07:59:37.51#ibcon#read 4, iclass 16, count 0 2006.280.07:59:37.51#ibcon#about to read 5, iclass 16, count 0 2006.280.07:59:37.51#ibcon#read 5, iclass 16, count 0 2006.280.07:59:37.51#ibcon#about to read 6, iclass 16, count 0 2006.280.07:59:37.51#ibcon#read 6, iclass 16, count 0 2006.280.07:59:37.51#ibcon#end of sib2, iclass 16, count 0 2006.280.07:59:37.51#ibcon#*mode == 0, iclass 16, count 0 2006.280.07:59:37.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.07:59:37.51#ibcon#[27=BW32\r\n] 2006.280.07:59:37.51#ibcon#*before write, iclass 16, count 0 2006.280.07:59:37.51#ibcon#enter sib2, iclass 16, count 0 2006.280.07:59:37.51#ibcon#flushed, iclass 16, count 0 2006.280.07:59:37.51#ibcon#about to write, iclass 16, count 0 2006.280.07:59:37.51#ibcon#wrote, iclass 16, count 0 2006.280.07:59:37.51#ibcon#about to read 3, iclass 16, count 0 2006.280.07:59:37.54#ibcon#read 3, iclass 16, count 0 2006.280.07:59:37.54#ibcon#about to read 4, iclass 16, count 0 2006.280.07:59:37.54#ibcon#read 4, iclass 16, count 0 2006.280.07:59:37.54#ibcon#about to read 5, iclass 16, count 0 2006.280.07:59:37.54#ibcon#read 5, iclass 16, count 0 2006.280.07:59:37.54#ibcon#about to read 6, iclass 16, count 0 2006.280.07:59:37.54#ibcon#read 6, iclass 16, count 0 2006.280.07:59:37.54#ibcon#end of sib2, iclass 16, count 0 2006.280.07:59:37.54#ibcon#*after write, iclass 16, count 0 2006.280.07:59:37.54#ibcon#*before return 0, iclass 16, count 0 2006.280.07:59:37.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:59:37.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.07:59:37.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.07:59:37.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.07:59:37.54$4f8m12a/ifd4f 2006.280.07:59:37.54$ifd4f/lo= 2006.280.07:59:37.54$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.07:59:37.54$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.07:59:37.54$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.07:59:37.54$ifd4f/patch= 2006.280.07:59:37.54$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.07:59:37.54$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.07:59:37.54$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.07:59:37.54$4f8m12a/"form=m,16.000,1:2 2006.280.07:59:37.54$4f8m12a/"tpicd 2006.280.07:59:37.54$4f8m12a/echo=off 2006.280.07:59:37.54$4f8m12a/xlog=off 2006.280.07:59:37.54:!2006.280.08:00:00 2006.280.07:59:42.13#trakl#Source acquired 2006.280.07:59:42.13#flagr#flagr/antenna,acquired 2006.280.08:00:00.00:preob 2006.280.08:00:01.13/onsource/TRACKING 2006.280.08:00:01.13:!2006.280.08:00:10 2006.280.08:00:10.00:data_valid=on 2006.280.08:00:10.00:midob 2006.280.08:00:10.13/onsource/TRACKING 2006.280.08:00:10.13/wx/20.94,987.1,61 2006.280.08:00:10.31/cable/+6.4836E-03 2006.280.08:00:11.40/va/01,07,usb,yes,32,34 2006.280.08:00:11.40/va/02,06,usb,yes,30,31 2006.280.08:00:11.40/va/03,06,usb,yes,28,28 2006.280.08:00:11.40/va/04,06,usb,yes,31,34 2006.280.08:00:11.40/va/05,07,usb,yes,29,31 2006.280.08:00:11.40/va/06,06,usb,yes,28,28 2006.280.08:00:11.40/va/07,06,usb,yes,29,28 2006.280.08:00:11.40/va/08,06,usb,yes,30,30 2006.280.08:00:11.63/valo/01,532.99,yes,locked 2006.280.08:00:11.63/valo/02,572.99,yes,locked 2006.280.08:00:11.63/valo/03,672.99,yes,locked 2006.280.08:00:11.63/valo/04,832.99,yes,locked 2006.280.08:00:11.63/valo/05,652.99,yes,locked 2006.280.08:00:11.63/valo/06,772.99,yes,locked 2006.280.08:00:11.63/valo/07,832.99,yes,locked 2006.280.08:00:11.63/valo/08,852.99,yes,locked 2006.280.08:00:12.72/vb/01,04,usb,yes,30,29 2006.280.08:00:12.72/vb/02,05,usb,yes,28,29 2006.280.08:00:12.72/vb/03,04,usb,yes,28,32 2006.280.08:00:12.72/vb/04,04,usb,yes,29,29 2006.280.08:00:12.72/vb/05,04,usb,yes,27,31 2006.280.08:00:12.72/vb/06,04,usb,yes,28,31 2006.280.08:00:12.72/vb/07,04,usb,yes,30,30 2006.280.08:00:12.72/vb/08,04,usb,yes,28,31 2006.280.08:00:12.96/vblo/01,632.99,yes,locked 2006.280.08:00:12.96/vblo/02,640.99,yes,locked 2006.280.08:00:12.96/vblo/03,656.99,yes,locked 2006.280.08:00:12.96/vblo/04,712.99,yes,locked 2006.280.08:00:12.96/vblo/05,744.99,yes,locked 2006.280.08:00:12.96/vblo/06,752.99,yes,locked 2006.280.08:00:12.96/vblo/07,734.99,yes,locked 2006.280.08:00:12.96/vblo/08,744.99,yes,locked 2006.280.08:00:13.11/vabw/8 2006.280.08:00:13.26/vbbw/8 2006.280.08:00:13.37/xfe/off,on,12.2 2006.280.08:00:13.74/ifatt/23,28,28,28 2006.280.08:00:14.07/fmout-gps/S +3.22E-07 2006.280.08:00:14.10:!2006.280.08:01:10 2006.280.08:01:10.01:data_valid=off 2006.280.08:01:10.01:postob 2006.280.08:01:10.11/cable/+6.4840E-03 2006.280.08:01:10.11/wx/20.91,987.2,62 2006.280.08:01:11.07/fmout-gps/S +3.23E-07 2006.280.08:01:11.07:scan_name=280-0802,k06280,60 2006.280.08:01:11.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.280.08:01:11.13#flagr#flagr/antenna,new-source 2006.280.08:01:12.13:checkk5 2006.280.08:01:12.67/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:01:13.15/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:01:13.58/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:01:14.30/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:01:15.25/chk_obsdata//k5ts1/T2800800??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:01:15.65/chk_obsdata//k5ts2/T2800800??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:01:16.67/chk_obsdata//k5ts3/T2800800??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:01:17.10/chk_obsdata//k5ts4/T2800800??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:01:23.92/k5log//k5ts1_log_newline 2006.280.08:01:25.19/k5log//k5ts2_log_newline 2006.280.08:01:26.42/k5log//k5ts3_log_newline 2006.280.08:01:27.49/k5log//k5ts4_log_newline 2006.280.08:01:27.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:01:27.52:4f8m12a=2 2006.280.08:01:27.52$4f8m12a/echo=on 2006.280.08:01:27.52$4f8m12a/pcalon 2006.280.08:01:27.52$pcalon/"no phase cal control is implemented here 2006.280.08:01:27.52$4f8m12a/"tpicd=stop 2006.280.08:01:27.52$4f8m12a/vc4f8 2006.280.08:01:27.52$vc4f8/valo=1,532.99 2006.280.08:01:27.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:01:27.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:01:27.52#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:27.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:27.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:27.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:27.52#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:01:27.52#ibcon#first serial, iclass 18, count 0 2006.280.08:01:27.52#ibcon#enter sib2, iclass 18, count 0 2006.280.08:01:27.52#ibcon#flushed, iclass 18, count 0 2006.280.08:01:27.52#ibcon#about to write, iclass 18, count 0 2006.280.08:01:27.52#ibcon#wrote, iclass 18, count 0 2006.280.08:01:27.52#ibcon#about to read 3, iclass 18, count 0 2006.280.08:01:27.54#ibcon#read 3, iclass 18, count 0 2006.280.08:01:27.54#ibcon#about to read 4, iclass 18, count 0 2006.280.08:01:27.54#ibcon#read 4, iclass 18, count 0 2006.280.08:01:27.54#ibcon#about to read 5, iclass 18, count 0 2006.280.08:01:27.54#ibcon#read 5, iclass 18, count 0 2006.280.08:01:27.54#ibcon#about to read 6, iclass 18, count 0 2006.280.08:01:27.54#ibcon#read 6, iclass 18, count 0 2006.280.08:01:27.54#ibcon#end of sib2, iclass 18, count 0 2006.280.08:01:27.54#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:01:27.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:01:27.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:01:27.54#ibcon#*before write, iclass 18, count 0 2006.280.08:01:27.54#ibcon#enter sib2, iclass 18, count 0 2006.280.08:01:27.54#ibcon#flushed, iclass 18, count 0 2006.280.08:01:27.54#ibcon#about to write, iclass 18, count 0 2006.280.08:01:27.54#ibcon#wrote, iclass 18, count 0 2006.280.08:01:27.54#ibcon#about to read 3, iclass 18, count 0 2006.280.08:01:27.59#ibcon#read 3, iclass 18, count 0 2006.280.08:01:27.59#ibcon#about to read 4, iclass 18, count 0 2006.280.08:01:27.59#ibcon#read 4, iclass 18, count 0 2006.280.08:01:27.59#ibcon#about to read 5, iclass 18, count 0 2006.280.08:01:27.59#ibcon#read 5, iclass 18, count 0 2006.280.08:01:27.59#ibcon#about to read 6, iclass 18, count 0 2006.280.08:01:27.59#ibcon#read 6, iclass 18, count 0 2006.280.08:01:27.59#ibcon#end of sib2, iclass 18, count 0 2006.280.08:01:27.59#ibcon#*after write, iclass 18, count 0 2006.280.08:01:27.59#ibcon#*before return 0, iclass 18, count 0 2006.280.08:01:27.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:27.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:27.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:01:27.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:01:27.59$vc4f8/va=1,7 2006.280.08:01:27.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:01:27.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:01:27.59#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:27.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:27.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:27.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:27.59#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:01:27.59#ibcon#first serial, iclass 20, count 2 2006.280.08:01:27.59#ibcon#enter sib2, iclass 20, count 2 2006.280.08:01:27.59#ibcon#flushed, iclass 20, count 2 2006.280.08:01:27.59#ibcon#about to write, iclass 20, count 2 2006.280.08:01:27.59#ibcon#wrote, iclass 20, count 2 2006.280.08:01:27.59#ibcon#about to read 3, iclass 20, count 2 2006.280.08:01:27.61#ibcon#read 3, iclass 20, count 2 2006.280.08:01:27.61#ibcon#about to read 4, iclass 20, count 2 2006.280.08:01:27.61#ibcon#read 4, iclass 20, count 2 2006.280.08:01:27.61#ibcon#about to read 5, iclass 20, count 2 2006.280.08:01:27.61#ibcon#read 5, iclass 20, count 2 2006.280.08:01:27.61#ibcon#about to read 6, iclass 20, count 2 2006.280.08:01:27.61#ibcon#read 6, iclass 20, count 2 2006.280.08:01:27.61#ibcon#end of sib2, iclass 20, count 2 2006.280.08:01:27.61#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:01:27.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:01:27.61#ibcon#[25=AT01-07\r\n] 2006.280.08:01:27.61#ibcon#*before write, iclass 20, count 2 2006.280.08:01:27.61#ibcon#enter sib2, iclass 20, count 2 2006.280.08:01:27.61#ibcon#flushed, iclass 20, count 2 2006.280.08:01:27.61#ibcon#about to write, iclass 20, count 2 2006.280.08:01:27.61#ibcon#wrote, iclass 20, count 2 2006.280.08:01:27.61#ibcon#about to read 3, iclass 20, count 2 2006.280.08:01:27.64#ibcon#read 3, iclass 20, count 2 2006.280.08:01:27.64#ibcon#about to read 4, iclass 20, count 2 2006.280.08:01:27.64#ibcon#read 4, iclass 20, count 2 2006.280.08:01:27.64#ibcon#about to read 5, iclass 20, count 2 2006.280.08:01:27.64#ibcon#read 5, iclass 20, count 2 2006.280.08:01:27.64#ibcon#about to read 6, iclass 20, count 2 2006.280.08:01:27.64#ibcon#read 6, iclass 20, count 2 2006.280.08:01:27.64#ibcon#end of sib2, iclass 20, count 2 2006.280.08:01:27.64#ibcon#*after write, iclass 20, count 2 2006.280.08:01:27.64#ibcon#*before return 0, iclass 20, count 2 2006.280.08:01:27.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:27.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:27.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:01:27.64#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:27.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:27.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:27.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:27.76#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:01:27.76#ibcon#first serial, iclass 20, count 0 2006.280.08:01:27.76#ibcon#enter sib2, iclass 20, count 0 2006.280.08:01:27.76#ibcon#flushed, iclass 20, count 0 2006.280.08:01:27.76#ibcon#about to write, iclass 20, count 0 2006.280.08:01:27.76#ibcon#wrote, iclass 20, count 0 2006.280.08:01:27.76#ibcon#about to read 3, iclass 20, count 0 2006.280.08:01:27.78#ibcon#read 3, iclass 20, count 0 2006.280.08:01:27.78#ibcon#about to read 4, iclass 20, count 0 2006.280.08:01:27.78#ibcon#read 4, iclass 20, count 0 2006.280.08:01:27.78#ibcon#about to read 5, iclass 20, count 0 2006.280.08:01:27.78#ibcon#read 5, iclass 20, count 0 2006.280.08:01:27.78#ibcon#about to read 6, iclass 20, count 0 2006.280.08:01:27.78#ibcon#read 6, iclass 20, count 0 2006.280.08:01:27.78#ibcon#end of sib2, iclass 20, count 0 2006.280.08:01:27.78#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:01:27.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:01:27.78#ibcon#[25=USB\r\n] 2006.280.08:01:27.78#ibcon#*before write, iclass 20, count 0 2006.280.08:01:27.78#ibcon#enter sib2, iclass 20, count 0 2006.280.08:01:27.78#ibcon#flushed, iclass 20, count 0 2006.280.08:01:27.78#ibcon#about to write, iclass 20, count 0 2006.280.08:01:27.78#ibcon#wrote, iclass 20, count 0 2006.280.08:01:27.78#ibcon#about to read 3, iclass 20, count 0 2006.280.08:01:27.81#ibcon#read 3, iclass 20, count 0 2006.280.08:01:27.81#ibcon#about to read 4, iclass 20, count 0 2006.280.08:01:27.81#ibcon#read 4, iclass 20, count 0 2006.280.08:01:27.81#ibcon#about to read 5, iclass 20, count 0 2006.280.08:01:27.81#ibcon#read 5, iclass 20, count 0 2006.280.08:01:27.81#ibcon#about to read 6, iclass 20, count 0 2006.280.08:01:27.81#ibcon#read 6, iclass 20, count 0 2006.280.08:01:27.81#ibcon#end of sib2, iclass 20, count 0 2006.280.08:01:27.81#ibcon#*after write, iclass 20, count 0 2006.280.08:01:27.81#ibcon#*before return 0, iclass 20, count 0 2006.280.08:01:27.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:27.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:27.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:01:27.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:01:27.81$vc4f8/valo=2,572.99 2006.280.08:01:27.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:01:27.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:01:27.81#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:27.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:27.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:27.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:27.81#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:01:27.81#ibcon#first serial, iclass 22, count 0 2006.280.08:01:27.81#ibcon#enter sib2, iclass 22, count 0 2006.280.08:01:27.81#ibcon#flushed, iclass 22, count 0 2006.280.08:01:27.81#ibcon#about to write, iclass 22, count 0 2006.280.08:01:27.81#ibcon#wrote, iclass 22, count 0 2006.280.08:01:27.81#ibcon#about to read 3, iclass 22, count 0 2006.280.08:01:27.83#ibcon#read 3, iclass 22, count 0 2006.280.08:01:27.83#ibcon#about to read 4, iclass 22, count 0 2006.280.08:01:27.83#ibcon#read 4, iclass 22, count 0 2006.280.08:01:27.83#ibcon#about to read 5, iclass 22, count 0 2006.280.08:01:27.83#ibcon#read 5, iclass 22, count 0 2006.280.08:01:27.83#ibcon#about to read 6, iclass 22, count 0 2006.280.08:01:27.83#ibcon#read 6, iclass 22, count 0 2006.280.08:01:27.83#ibcon#end of sib2, iclass 22, count 0 2006.280.08:01:27.83#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:01:27.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:01:27.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:01:27.83#ibcon#*before write, iclass 22, count 0 2006.280.08:01:27.83#ibcon#enter sib2, iclass 22, count 0 2006.280.08:01:27.83#ibcon#flushed, iclass 22, count 0 2006.280.08:01:27.83#ibcon#about to write, iclass 22, count 0 2006.280.08:01:27.83#ibcon#wrote, iclass 22, count 0 2006.280.08:01:27.83#ibcon#about to read 3, iclass 22, count 0 2006.280.08:01:27.87#ibcon#read 3, iclass 22, count 0 2006.280.08:01:27.87#ibcon#about to read 4, iclass 22, count 0 2006.280.08:01:27.87#ibcon#read 4, iclass 22, count 0 2006.280.08:01:27.87#ibcon#about to read 5, iclass 22, count 0 2006.280.08:01:27.87#ibcon#read 5, iclass 22, count 0 2006.280.08:01:27.87#ibcon#about to read 6, iclass 22, count 0 2006.280.08:01:27.87#ibcon#read 6, iclass 22, count 0 2006.280.08:01:27.87#ibcon#end of sib2, iclass 22, count 0 2006.280.08:01:27.87#ibcon#*after write, iclass 22, count 0 2006.280.08:01:27.87#ibcon#*before return 0, iclass 22, count 0 2006.280.08:01:27.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:27.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:27.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:01:27.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:01:27.87$vc4f8/va=2,6 2006.280.08:01:27.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:01:27.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:01:27.87#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:27.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:27.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:27.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:27.93#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:01:27.93#ibcon#first serial, iclass 24, count 2 2006.280.08:01:27.93#ibcon#enter sib2, iclass 24, count 2 2006.280.08:01:27.93#ibcon#flushed, iclass 24, count 2 2006.280.08:01:27.93#ibcon#about to write, iclass 24, count 2 2006.280.08:01:27.93#ibcon#wrote, iclass 24, count 2 2006.280.08:01:27.93#ibcon#about to read 3, iclass 24, count 2 2006.280.08:01:27.95#ibcon#read 3, iclass 24, count 2 2006.280.08:01:27.95#ibcon#about to read 4, iclass 24, count 2 2006.280.08:01:27.95#ibcon#read 4, iclass 24, count 2 2006.280.08:01:27.95#ibcon#about to read 5, iclass 24, count 2 2006.280.08:01:27.95#ibcon#read 5, iclass 24, count 2 2006.280.08:01:27.95#ibcon#about to read 6, iclass 24, count 2 2006.280.08:01:27.95#ibcon#read 6, iclass 24, count 2 2006.280.08:01:27.95#ibcon#end of sib2, iclass 24, count 2 2006.280.08:01:27.95#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:01:27.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:01:27.95#ibcon#[25=AT02-06\r\n] 2006.280.08:01:27.95#ibcon#*before write, iclass 24, count 2 2006.280.08:01:27.95#ibcon#enter sib2, iclass 24, count 2 2006.280.08:01:27.95#ibcon#flushed, iclass 24, count 2 2006.280.08:01:27.95#ibcon#about to write, iclass 24, count 2 2006.280.08:01:27.95#ibcon#wrote, iclass 24, count 2 2006.280.08:01:27.95#ibcon#about to read 3, iclass 24, count 2 2006.280.08:01:27.98#ibcon#read 3, iclass 24, count 2 2006.280.08:01:27.98#ibcon#about to read 4, iclass 24, count 2 2006.280.08:01:27.98#ibcon#read 4, iclass 24, count 2 2006.280.08:01:27.98#ibcon#about to read 5, iclass 24, count 2 2006.280.08:01:27.98#ibcon#read 5, iclass 24, count 2 2006.280.08:01:27.98#ibcon#about to read 6, iclass 24, count 2 2006.280.08:01:27.98#ibcon#read 6, iclass 24, count 2 2006.280.08:01:27.98#ibcon#end of sib2, iclass 24, count 2 2006.280.08:01:27.98#ibcon#*after write, iclass 24, count 2 2006.280.08:01:27.98#ibcon#*before return 0, iclass 24, count 2 2006.280.08:01:27.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:27.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:27.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:01:27.98#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:27.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:28.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:28.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:28.10#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:01:28.10#ibcon#first serial, iclass 24, count 0 2006.280.08:01:28.10#ibcon#enter sib2, iclass 24, count 0 2006.280.08:01:28.10#ibcon#flushed, iclass 24, count 0 2006.280.08:01:28.10#ibcon#about to write, iclass 24, count 0 2006.280.08:01:28.10#ibcon#wrote, iclass 24, count 0 2006.280.08:01:28.10#ibcon#about to read 3, iclass 24, count 0 2006.280.08:01:28.12#ibcon#read 3, iclass 24, count 0 2006.280.08:01:28.12#ibcon#about to read 4, iclass 24, count 0 2006.280.08:01:28.12#ibcon#read 4, iclass 24, count 0 2006.280.08:01:28.12#ibcon#about to read 5, iclass 24, count 0 2006.280.08:01:28.12#ibcon#read 5, iclass 24, count 0 2006.280.08:01:28.12#ibcon#about to read 6, iclass 24, count 0 2006.280.08:01:28.12#ibcon#read 6, iclass 24, count 0 2006.280.08:01:28.12#ibcon#end of sib2, iclass 24, count 0 2006.280.08:01:28.12#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:01:28.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:01:28.12#ibcon#[25=USB\r\n] 2006.280.08:01:28.12#ibcon#*before write, iclass 24, count 0 2006.280.08:01:28.12#ibcon#enter sib2, iclass 24, count 0 2006.280.08:01:28.12#ibcon#flushed, iclass 24, count 0 2006.280.08:01:28.12#ibcon#about to write, iclass 24, count 0 2006.280.08:01:28.12#ibcon#wrote, iclass 24, count 0 2006.280.08:01:28.12#ibcon#about to read 3, iclass 24, count 0 2006.280.08:01:28.15#ibcon#read 3, iclass 24, count 0 2006.280.08:01:28.15#ibcon#about to read 4, iclass 24, count 0 2006.280.08:01:28.15#ibcon#read 4, iclass 24, count 0 2006.280.08:01:28.15#ibcon#about to read 5, iclass 24, count 0 2006.280.08:01:28.15#ibcon#read 5, iclass 24, count 0 2006.280.08:01:28.15#ibcon#about to read 6, iclass 24, count 0 2006.280.08:01:28.15#ibcon#read 6, iclass 24, count 0 2006.280.08:01:28.15#ibcon#end of sib2, iclass 24, count 0 2006.280.08:01:28.15#ibcon#*after write, iclass 24, count 0 2006.280.08:01:28.15#ibcon#*before return 0, iclass 24, count 0 2006.280.08:01:28.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:28.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:28.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:01:28.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:01:28.15$vc4f8/valo=3,672.99 2006.280.08:01:28.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:01:28.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:01:28.15#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:28.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:28.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:28.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:28.15#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:01:28.15#ibcon#first serial, iclass 26, count 0 2006.280.08:01:28.15#ibcon#enter sib2, iclass 26, count 0 2006.280.08:01:28.15#ibcon#flushed, iclass 26, count 0 2006.280.08:01:28.15#ibcon#about to write, iclass 26, count 0 2006.280.08:01:28.15#ibcon#wrote, iclass 26, count 0 2006.280.08:01:28.15#ibcon#about to read 3, iclass 26, count 0 2006.280.08:01:28.17#ibcon#read 3, iclass 26, count 0 2006.280.08:01:28.17#ibcon#about to read 4, iclass 26, count 0 2006.280.08:01:28.17#ibcon#read 4, iclass 26, count 0 2006.280.08:01:28.17#ibcon#about to read 5, iclass 26, count 0 2006.280.08:01:28.17#ibcon#read 5, iclass 26, count 0 2006.280.08:01:28.17#ibcon#about to read 6, iclass 26, count 0 2006.280.08:01:28.17#ibcon#read 6, iclass 26, count 0 2006.280.08:01:28.17#ibcon#end of sib2, iclass 26, count 0 2006.280.08:01:28.17#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:01:28.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:01:28.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:01:28.17#ibcon#*before write, iclass 26, count 0 2006.280.08:01:28.17#ibcon#enter sib2, iclass 26, count 0 2006.280.08:01:28.17#ibcon#flushed, iclass 26, count 0 2006.280.08:01:28.17#ibcon#about to write, iclass 26, count 0 2006.280.08:01:28.17#ibcon#wrote, iclass 26, count 0 2006.280.08:01:28.17#ibcon#about to read 3, iclass 26, count 0 2006.280.08:01:28.21#ibcon#read 3, iclass 26, count 0 2006.280.08:01:28.21#ibcon#about to read 4, iclass 26, count 0 2006.280.08:01:28.21#ibcon#read 4, iclass 26, count 0 2006.280.08:01:28.21#ibcon#about to read 5, iclass 26, count 0 2006.280.08:01:28.21#ibcon#read 5, iclass 26, count 0 2006.280.08:01:28.21#ibcon#about to read 6, iclass 26, count 0 2006.280.08:01:28.21#ibcon#read 6, iclass 26, count 0 2006.280.08:01:28.21#ibcon#end of sib2, iclass 26, count 0 2006.280.08:01:28.21#ibcon#*after write, iclass 26, count 0 2006.280.08:01:28.21#ibcon#*before return 0, iclass 26, count 0 2006.280.08:01:28.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:28.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:28.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:01:28.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:01:28.21$vc4f8/va=3,6 2006.280.08:01:28.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:01:28.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:01:28.21#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:28.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:28.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:28.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:28.27#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:01:28.27#ibcon#first serial, iclass 28, count 2 2006.280.08:01:28.27#ibcon#enter sib2, iclass 28, count 2 2006.280.08:01:28.27#ibcon#flushed, iclass 28, count 2 2006.280.08:01:28.27#ibcon#about to write, iclass 28, count 2 2006.280.08:01:28.27#ibcon#wrote, iclass 28, count 2 2006.280.08:01:28.27#ibcon#about to read 3, iclass 28, count 2 2006.280.08:01:28.29#ibcon#read 3, iclass 28, count 2 2006.280.08:01:28.29#ibcon#about to read 4, iclass 28, count 2 2006.280.08:01:28.29#ibcon#read 4, iclass 28, count 2 2006.280.08:01:28.29#ibcon#about to read 5, iclass 28, count 2 2006.280.08:01:28.29#ibcon#read 5, iclass 28, count 2 2006.280.08:01:28.29#ibcon#about to read 6, iclass 28, count 2 2006.280.08:01:28.29#ibcon#read 6, iclass 28, count 2 2006.280.08:01:28.29#ibcon#end of sib2, iclass 28, count 2 2006.280.08:01:28.29#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:01:28.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:01:28.29#ibcon#[25=AT03-06\r\n] 2006.280.08:01:28.29#ibcon#*before write, iclass 28, count 2 2006.280.08:01:28.29#ibcon#enter sib2, iclass 28, count 2 2006.280.08:01:28.29#ibcon#flushed, iclass 28, count 2 2006.280.08:01:28.29#ibcon#about to write, iclass 28, count 2 2006.280.08:01:28.29#ibcon#wrote, iclass 28, count 2 2006.280.08:01:28.29#ibcon#about to read 3, iclass 28, count 2 2006.280.08:01:28.32#ibcon#read 3, iclass 28, count 2 2006.280.08:01:28.32#ibcon#about to read 4, iclass 28, count 2 2006.280.08:01:28.32#ibcon#read 4, iclass 28, count 2 2006.280.08:01:28.32#ibcon#about to read 5, iclass 28, count 2 2006.280.08:01:28.32#ibcon#read 5, iclass 28, count 2 2006.280.08:01:28.32#ibcon#about to read 6, iclass 28, count 2 2006.280.08:01:28.32#ibcon#read 6, iclass 28, count 2 2006.280.08:01:28.32#ibcon#end of sib2, iclass 28, count 2 2006.280.08:01:28.32#ibcon#*after write, iclass 28, count 2 2006.280.08:01:28.32#ibcon#*before return 0, iclass 28, count 2 2006.280.08:01:28.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:28.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:28.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:01:28.32#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:28.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:28.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:28.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:28.44#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:01:28.44#ibcon#first serial, iclass 28, count 0 2006.280.08:01:28.44#ibcon#enter sib2, iclass 28, count 0 2006.280.08:01:28.44#ibcon#flushed, iclass 28, count 0 2006.280.08:01:28.44#ibcon#about to write, iclass 28, count 0 2006.280.08:01:28.44#ibcon#wrote, iclass 28, count 0 2006.280.08:01:28.44#ibcon#about to read 3, iclass 28, count 0 2006.280.08:01:28.46#ibcon#read 3, iclass 28, count 0 2006.280.08:01:28.46#ibcon#about to read 4, iclass 28, count 0 2006.280.08:01:28.46#ibcon#read 4, iclass 28, count 0 2006.280.08:01:28.46#ibcon#about to read 5, iclass 28, count 0 2006.280.08:01:28.46#ibcon#read 5, iclass 28, count 0 2006.280.08:01:28.46#ibcon#about to read 6, iclass 28, count 0 2006.280.08:01:28.46#ibcon#read 6, iclass 28, count 0 2006.280.08:01:28.46#ibcon#end of sib2, iclass 28, count 0 2006.280.08:01:28.46#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:01:28.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:01:28.46#ibcon#[25=USB\r\n] 2006.280.08:01:28.46#ibcon#*before write, iclass 28, count 0 2006.280.08:01:28.46#ibcon#enter sib2, iclass 28, count 0 2006.280.08:01:28.46#ibcon#flushed, iclass 28, count 0 2006.280.08:01:28.46#ibcon#about to write, iclass 28, count 0 2006.280.08:01:28.46#ibcon#wrote, iclass 28, count 0 2006.280.08:01:28.46#ibcon#about to read 3, iclass 28, count 0 2006.280.08:01:28.49#ibcon#read 3, iclass 28, count 0 2006.280.08:01:28.49#ibcon#about to read 4, iclass 28, count 0 2006.280.08:01:28.49#ibcon#read 4, iclass 28, count 0 2006.280.08:01:28.49#ibcon#about to read 5, iclass 28, count 0 2006.280.08:01:28.49#ibcon#read 5, iclass 28, count 0 2006.280.08:01:28.49#ibcon#about to read 6, iclass 28, count 0 2006.280.08:01:28.49#ibcon#read 6, iclass 28, count 0 2006.280.08:01:28.49#ibcon#end of sib2, iclass 28, count 0 2006.280.08:01:28.49#ibcon#*after write, iclass 28, count 0 2006.280.08:01:28.49#ibcon#*before return 0, iclass 28, count 0 2006.280.08:01:28.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:28.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:28.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:01:28.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:01:28.49$vc4f8/valo=4,832.99 2006.280.08:01:28.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:01:28.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:01:28.49#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:28.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:28.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:28.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:28.49#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:01:28.49#ibcon#first serial, iclass 30, count 0 2006.280.08:01:28.49#ibcon#enter sib2, iclass 30, count 0 2006.280.08:01:28.49#ibcon#flushed, iclass 30, count 0 2006.280.08:01:28.49#ibcon#about to write, iclass 30, count 0 2006.280.08:01:28.49#ibcon#wrote, iclass 30, count 0 2006.280.08:01:28.49#ibcon#about to read 3, iclass 30, count 0 2006.280.08:01:28.51#ibcon#read 3, iclass 30, count 0 2006.280.08:01:28.51#ibcon#about to read 4, iclass 30, count 0 2006.280.08:01:28.51#ibcon#read 4, iclass 30, count 0 2006.280.08:01:28.51#ibcon#about to read 5, iclass 30, count 0 2006.280.08:01:28.51#ibcon#read 5, iclass 30, count 0 2006.280.08:01:28.51#ibcon#about to read 6, iclass 30, count 0 2006.280.08:01:28.51#ibcon#read 6, iclass 30, count 0 2006.280.08:01:28.51#ibcon#end of sib2, iclass 30, count 0 2006.280.08:01:28.51#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:01:28.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:01:28.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:01:28.51#ibcon#*before write, iclass 30, count 0 2006.280.08:01:28.51#ibcon#enter sib2, iclass 30, count 0 2006.280.08:01:28.51#ibcon#flushed, iclass 30, count 0 2006.280.08:01:28.51#ibcon#about to write, iclass 30, count 0 2006.280.08:01:28.51#ibcon#wrote, iclass 30, count 0 2006.280.08:01:28.51#ibcon#about to read 3, iclass 30, count 0 2006.280.08:01:28.55#ibcon#read 3, iclass 30, count 0 2006.280.08:01:28.55#ibcon#about to read 4, iclass 30, count 0 2006.280.08:01:28.55#ibcon#read 4, iclass 30, count 0 2006.280.08:01:28.55#ibcon#about to read 5, iclass 30, count 0 2006.280.08:01:28.55#ibcon#read 5, iclass 30, count 0 2006.280.08:01:28.55#ibcon#about to read 6, iclass 30, count 0 2006.280.08:01:28.55#ibcon#read 6, iclass 30, count 0 2006.280.08:01:28.55#ibcon#end of sib2, iclass 30, count 0 2006.280.08:01:28.55#ibcon#*after write, iclass 30, count 0 2006.280.08:01:28.55#ibcon#*before return 0, iclass 30, count 0 2006.280.08:01:28.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:28.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:28.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:01:28.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:01:28.55$vc4f8/va=4,6 2006.280.08:01:28.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:01:28.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:01:28.56#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:28.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:28.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:28.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:28.60#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:01:28.60#ibcon#first serial, iclass 32, count 2 2006.280.08:01:28.60#ibcon#enter sib2, iclass 32, count 2 2006.280.08:01:28.60#ibcon#flushed, iclass 32, count 2 2006.280.08:01:28.60#ibcon#about to write, iclass 32, count 2 2006.280.08:01:28.60#ibcon#wrote, iclass 32, count 2 2006.280.08:01:28.60#ibcon#about to read 3, iclass 32, count 2 2006.280.08:01:28.62#ibcon#read 3, iclass 32, count 2 2006.280.08:01:28.62#ibcon#about to read 4, iclass 32, count 2 2006.280.08:01:28.62#ibcon#read 4, iclass 32, count 2 2006.280.08:01:28.62#ibcon#about to read 5, iclass 32, count 2 2006.280.08:01:28.62#ibcon#read 5, iclass 32, count 2 2006.280.08:01:28.62#ibcon#about to read 6, iclass 32, count 2 2006.280.08:01:28.62#ibcon#read 6, iclass 32, count 2 2006.280.08:01:28.62#ibcon#end of sib2, iclass 32, count 2 2006.280.08:01:28.62#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:01:28.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:01:28.62#ibcon#[25=AT04-06\r\n] 2006.280.08:01:28.62#ibcon#*before write, iclass 32, count 2 2006.280.08:01:28.62#ibcon#enter sib2, iclass 32, count 2 2006.280.08:01:28.62#ibcon#flushed, iclass 32, count 2 2006.280.08:01:28.62#ibcon#about to write, iclass 32, count 2 2006.280.08:01:28.62#ibcon#wrote, iclass 32, count 2 2006.280.08:01:28.62#ibcon#about to read 3, iclass 32, count 2 2006.280.08:01:28.66#ibcon#read 3, iclass 32, count 2 2006.280.08:01:28.66#ibcon#about to read 4, iclass 32, count 2 2006.280.08:01:28.66#ibcon#read 4, iclass 32, count 2 2006.280.08:01:28.66#ibcon#about to read 5, iclass 32, count 2 2006.280.08:01:28.66#ibcon#read 5, iclass 32, count 2 2006.280.08:01:28.66#ibcon#about to read 6, iclass 32, count 2 2006.280.08:01:28.66#ibcon#read 6, iclass 32, count 2 2006.280.08:01:28.66#ibcon#end of sib2, iclass 32, count 2 2006.280.08:01:28.66#ibcon#*after write, iclass 32, count 2 2006.280.08:01:28.66#ibcon#*before return 0, iclass 32, count 2 2006.280.08:01:28.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:28.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:28.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:01:28.66#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:28.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:28.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:28.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:28.78#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:01:28.78#ibcon#first serial, iclass 32, count 0 2006.280.08:01:28.78#ibcon#enter sib2, iclass 32, count 0 2006.280.08:01:28.78#ibcon#flushed, iclass 32, count 0 2006.280.08:01:28.78#ibcon#about to write, iclass 32, count 0 2006.280.08:01:28.78#ibcon#wrote, iclass 32, count 0 2006.280.08:01:28.78#ibcon#about to read 3, iclass 32, count 0 2006.280.08:01:28.80#ibcon#read 3, iclass 32, count 0 2006.280.08:01:28.80#ibcon#about to read 4, iclass 32, count 0 2006.280.08:01:28.80#ibcon#read 4, iclass 32, count 0 2006.280.08:01:28.80#ibcon#about to read 5, iclass 32, count 0 2006.280.08:01:28.80#ibcon#read 5, iclass 32, count 0 2006.280.08:01:28.80#ibcon#about to read 6, iclass 32, count 0 2006.280.08:01:28.80#ibcon#read 6, iclass 32, count 0 2006.280.08:01:28.80#ibcon#end of sib2, iclass 32, count 0 2006.280.08:01:28.80#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:01:28.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:01:28.80#ibcon#[25=USB\r\n] 2006.280.08:01:28.80#ibcon#*before write, iclass 32, count 0 2006.280.08:01:28.80#ibcon#enter sib2, iclass 32, count 0 2006.280.08:01:28.80#ibcon#flushed, iclass 32, count 0 2006.280.08:01:28.80#ibcon#about to write, iclass 32, count 0 2006.280.08:01:28.80#ibcon#wrote, iclass 32, count 0 2006.280.08:01:28.80#ibcon#about to read 3, iclass 32, count 0 2006.280.08:01:28.83#ibcon#read 3, iclass 32, count 0 2006.280.08:01:28.83#ibcon#about to read 4, iclass 32, count 0 2006.280.08:01:28.83#ibcon#read 4, iclass 32, count 0 2006.280.08:01:28.83#ibcon#about to read 5, iclass 32, count 0 2006.280.08:01:28.83#ibcon#read 5, iclass 32, count 0 2006.280.08:01:28.83#ibcon#about to read 6, iclass 32, count 0 2006.280.08:01:28.83#ibcon#read 6, iclass 32, count 0 2006.280.08:01:28.83#ibcon#end of sib2, iclass 32, count 0 2006.280.08:01:28.83#ibcon#*after write, iclass 32, count 0 2006.280.08:01:28.83#ibcon#*before return 0, iclass 32, count 0 2006.280.08:01:28.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:28.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:28.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:01:28.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:01:28.83$vc4f8/valo=5,652.99 2006.280.08:01:28.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:01:28.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:01:28.83#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:28.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:28.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:28.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:28.83#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:01:28.83#ibcon#first serial, iclass 34, count 0 2006.280.08:01:28.83#ibcon#enter sib2, iclass 34, count 0 2006.280.08:01:28.83#ibcon#flushed, iclass 34, count 0 2006.280.08:01:28.83#ibcon#about to write, iclass 34, count 0 2006.280.08:01:28.83#ibcon#wrote, iclass 34, count 0 2006.280.08:01:28.83#ibcon#about to read 3, iclass 34, count 0 2006.280.08:01:28.85#ibcon#read 3, iclass 34, count 0 2006.280.08:01:28.85#ibcon#about to read 4, iclass 34, count 0 2006.280.08:01:28.85#ibcon#read 4, iclass 34, count 0 2006.280.08:01:28.85#ibcon#about to read 5, iclass 34, count 0 2006.280.08:01:28.85#ibcon#read 5, iclass 34, count 0 2006.280.08:01:28.85#ibcon#about to read 6, iclass 34, count 0 2006.280.08:01:28.85#ibcon#read 6, iclass 34, count 0 2006.280.08:01:28.85#ibcon#end of sib2, iclass 34, count 0 2006.280.08:01:28.85#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:01:28.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:01:28.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:01:28.85#ibcon#*before write, iclass 34, count 0 2006.280.08:01:28.85#ibcon#enter sib2, iclass 34, count 0 2006.280.08:01:28.85#ibcon#flushed, iclass 34, count 0 2006.280.08:01:28.85#ibcon#about to write, iclass 34, count 0 2006.280.08:01:28.85#ibcon#wrote, iclass 34, count 0 2006.280.08:01:28.85#ibcon#about to read 3, iclass 34, count 0 2006.280.08:01:28.89#ibcon#read 3, iclass 34, count 0 2006.280.08:01:28.89#ibcon#about to read 4, iclass 34, count 0 2006.280.08:01:28.89#ibcon#read 4, iclass 34, count 0 2006.280.08:01:28.89#ibcon#about to read 5, iclass 34, count 0 2006.280.08:01:28.89#ibcon#read 5, iclass 34, count 0 2006.280.08:01:28.89#ibcon#about to read 6, iclass 34, count 0 2006.280.08:01:28.89#ibcon#read 6, iclass 34, count 0 2006.280.08:01:28.89#ibcon#end of sib2, iclass 34, count 0 2006.280.08:01:28.89#ibcon#*after write, iclass 34, count 0 2006.280.08:01:28.89#ibcon#*before return 0, iclass 34, count 0 2006.280.08:01:28.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:28.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:28.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:01:28.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:01:28.89$vc4f8/va=5,7 2006.280.08:01:28.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:01:28.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:01:28.89#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:28.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:28.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:28.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:28.95#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:01:28.95#ibcon#first serial, iclass 36, count 2 2006.280.08:01:28.95#ibcon#enter sib2, iclass 36, count 2 2006.280.08:01:28.95#ibcon#flushed, iclass 36, count 2 2006.280.08:01:28.95#ibcon#about to write, iclass 36, count 2 2006.280.08:01:28.95#ibcon#wrote, iclass 36, count 2 2006.280.08:01:28.95#ibcon#about to read 3, iclass 36, count 2 2006.280.08:01:28.97#ibcon#read 3, iclass 36, count 2 2006.280.08:01:28.97#ibcon#about to read 4, iclass 36, count 2 2006.280.08:01:28.97#ibcon#read 4, iclass 36, count 2 2006.280.08:01:28.97#ibcon#about to read 5, iclass 36, count 2 2006.280.08:01:28.97#ibcon#read 5, iclass 36, count 2 2006.280.08:01:28.97#ibcon#about to read 6, iclass 36, count 2 2006.280.08:01:28.97#ibcon#read 6, iclass 36, count 2 2006.280.08:01:28.97#ibcon#end of sib2, iclass 36, count 2 2006.280.08:01:28.97#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:01:28.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:01:28.97#ibcon#[25=AT05-07\r\n] 2006.280.08:01:28.97#ibcon#*before write, iclass 36, count 2 2006.280.08:01:28.97#ibcon#enter sib2, iclass 36, count 2 2006.280.08:01:28.97#ibcon#flushed, iclass 36, count 2 2006.280.08:01:28.97#ibcon#about to write, iclass 36, count 2 2006.280.08:01:28.97#ibcon#wrote, iclass 36, count 2 2006.280.08:01:28.97#ibcon#about to read 3, iclass 36, count 2 2006.280.08:01:29.00#ibcon#read 3, iclass 36, count 2 2006.280.08:01:29.00#ibcon#about to read 4, iclass 36, count 2 2006.280.08:01:29.00#ibcon#read 4, iclass 36, count 2 2006.280.08:01:29.00#ibcon#about to read 5, iclass 36, count 2 2006.280.08:01:29.00#ibcon#read 5, iclass 36, count 2 2006.280.08:01:29.00#ibcon#about to read 6, iclass 36, count 2 2006.280.08:01:29.00#ibcon#read 6, iclass 36, count 2 2006.280.08:01:29.00#ibcon#end of sib2, iclass 36, count 2 2006.280.08:01:29.00#ibcon#*after write, iclass 36, count 2 2006.280.08:01:29.00#ibcon#*before return 0, iclass 36, count 2 2006.280.08:01:29.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:29.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:29.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:01:29.00#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:29.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:29.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:29.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:29.12#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:01:29.12#ibcon#first serial, iclass 36, count 0 2006.280.08:01:29.12#ibcon#enter sib2, iclass 36, count 0 2006.280.08:01:29.12#ibcon#flushed, iclass 36, count 0 2006.280.08:01:29.12#ibcon#about to write, iclass 36, count 0 2006.280.08:01:29.12#ibcon#wrote, iclass 36, count 0 2006.280.08:01:29.12#ibcon#about to read 3, iclass 36, count 0 2006.280.08:01:29.14#ibcon#read 3, iclass 36, count 0 2006.280.08:01:29.14#ibcon#about to read 4, iclass 36, count 0 2006.280.08:01:29.14#ibcon#read 4, iclass 36, count 0 2006.280.08:01:29.14#ibcon#about to read 5, iclass 36, count 0 2006.280.08:01:29.14#ibcon#read 5, iclass 36, count 0 2006.280.08:01:29.14#ibcon#about to read 6, iclass 36, count 0 2006.280.08:01:29.14#ibcon#read 6, iclass 36, count 0 2006.280.08:01:29.14#ibcon#end of sib2, iclass 36, count 0 2006.280.08:01:29.14#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:01:29.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:01:29.14#ibcon#[25=USB\r\n] 2006.280.08:01:29.14#ibcon#*before write, iclass 36, count 0 2006.280.08:01:29.14#ibcon#enter sib2, iclass 36, count 0 2006.280.08:01:29.14#ibcon#flushed, iclass 36, count 0 2006.280.08:01:29.14#ibcon#about to write, iclass 36, count 0 2006.280.08:01:29.14#ibcon#wrote, iclass 36, count 0 2006.280.08:01:29.14#ibcon#about to read 3, iclass 36, count 0 2006.280.08:01:29.17#ibcon#read 3, iclass 36, count 0 2006.280.08:01:29.17#ibcon#about to read 4, iclass 36, count 0 2006.280.08:01:29.17#ibcon#read 4, iclass 36, count 0 2006.280.08:01:29.17#ibcon#about to read 5, iclass 36, count 0 2006.280.08:01:29.17#ibcon#read 5, iclass 36, count 0 2006.280.08:01:29.17#ibcon#about to read 6, iclass 36, count 0 2006.280.08:01:29.17#ibcon#read 6, iclass 36, count 0 2006.280.08:01:29.17#ibcon#end of sib2, iclass 36, count 0 2006.280.08:01:29.17#ibcon#*after write, iclass 36, count 0 2006.280.08:01:29.17#ibcon#*before return 0, iclass 36, count 0 2006.280.08:01:29.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:29.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:29.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:01:29.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:01:29.17$vc4f8/valo=6,772.99 2006.280.08:01:29.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:01:29.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:01:29.17#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:29.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:29.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:29.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:29.17#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:01:29.17#ibcon#first serial, iclass 38, count 0 2006.280.08:01:29.17#ibcon#enter sib2, iclass 38, count 0 2006.280.08:01:29.17#ibcon#flushed, iclass 38, count 0 2006.280.08:01:29.17#ibcon#about to write, iclass 38, count 0 2006.280.08:01:29.17#ibcon#wrote, iclass 38, count 0 2006.280.08:01:29.17#ibcon#about to read 3, iclass 38, count 0 2006.280.08:01:29.19#ibcon#read 3, iclass 38, count 0 2006.280.08:01:29.19#ibcon#about to read 4, iclass 38, count 0 2006.280.08:01:29.19#ibcon#read 4, iclass 38, count 0 2006.280.08:01:29.19#ibcon#about to read 5, iclass 38, count 0 2006.280.08:01:29.19#ibcon#read 5, iclass 38, count 0 2006.280.08:01:29.19#ibcon#about to read 6, iclass 38, count 0 2006.280.08:01:29.19#ibcon#read 6, iclass 38, count 0 2006.280.08:01:29.19#ibcon#end of sib2, iclass 38, count 0 2006.280.08:01:29.19#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:01:29.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:01:29.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:01:29.19#ibcon#*before write, iclass 38, count 0 2006.280.08:01:29.19#ibcon#enter sib2, iclass 38, count 0 2006.280.08:01:29.19#ibcon#flushed, iclass 38, count 0 2006.280.08:01:29.19#ibcon#about to write, iclass 38, count 0 2006.280.08:01:29.19#ibcon#wrote, iclass 38, count 0 2006.280.08:01:29.19#ibcon#about to read 3, iclass 38, count 0 2006.280.08:01:29.23#ibcon#read 3, iclass 38, count 0 2006.280.08:01:29.23#ibcon#about to read 4, iclass 38, count 0 2006.280.08:01:29.23#ibcon#read 4, iclass 38, count 0 2006.280.08:01:29.23#ibcon#about to read 5, iclass 38, count 0 2006.280.08:01:29.23#ibcon#read 5, iclass 38, count 0 2006.280.08:01:29.23#ibcon#about to read 6, iclass 38, count 0 2006.280.08:01:29.23#ibcon#read 6, iclass 38, count 0 2006.280.08:01:29.23#ibcon#end of sib2, iclass 38, count 0 2006.280.08:01:29.23#ibcon#*after write, iclass 38, count 0 2006.280.08:01:29.23#ibcon#*before return 0, iclass 38, count 0 2006.280.08:01:29.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:29.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:29.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:01:29.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:01:29.23$vc4f8/va=6,6 2006.280.08:01:29.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:01:29.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:01:29.23#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:29.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:29.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:29.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:29.29#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:01:29.29#ibcon#first serial, iclass 40, count 2 2006.280.08:01:29.29#ibcon#enter sib2, iclass 40, count 2 2006.280.08:01:29.29#ibcon#flushed, iclass 40, count 2 2006.280.08:01:29.29#ibcon#about to write, iclass 40, count 2 2006.280.08:01:29.29#ibcon#wrote, iclass 40, count 2 2006.280.08:01:29.29#ibcon#about to read 3, iclass 40, count 2 2006.280.08:01:29.31#ibcon#read 3, iclass 40, count 2 2006.280.08:01:29.31#ibcon#about to read 4, iclass 40, count 2 2006.280.08:01:29.31#ibcon#read 4, iclass 40, count 2 2006.280.08:01:29.31#ibcon#about to read 5, iclass 40, count 2 2006.280.08:01:29.31#ibcon#read 5, iclass 40, count 2 2006.280.08:01:29.31#ibcon#about to read 6, iclass 40, count 2 2006.280.08:01:29.31#ibcon#read 6, iclass 40, count 2 2006.280.08:01:29.31#ibcon#end of sib2, iclass 40, count 2 2006.280.08:01:29.31#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:01:29.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:01:29.31#ibcon#[25=AT06-06\r\n] 2006.280.08:01:29.31#ibcon#*before write, iclass 40, count 2 2006.280.08:01:29.31#ibcon#enter sib2, iclass 40, count 2 2006.280.08:01:29.31#ibcon#flushed, iclass 40, count 2 2006.280.08:01:29.31#ibcon#about to write, iclass 40, count 2 2006.280.08:01:29.31#ibcon#wrote, iclass 40, count 2 2006.280.08:01:29.31#ibcon#about to read 3, iclass 40, count 2 2006.280.08:01:29.34#ibcon#read 3, iclass 40, count 2 2006.280.08:01:29.34#ibcon#about to read 4, iclass 40, count 2 2006.280.08:01:29.34#ibcon#read 4, iclass 40, count 2 2006.280.08:01:29.34#ibcon#about to read 5, iclass 40, count 2 2006.280.08:01:29.34#ibcon#read 5, iclass 40, count 2 2006.280.08:01:29.34#ibcon#about to read 6, iclass 40, count 2 2006.280.08:01:29.34#ibcon#read 6, iclass 40, count 2 2006.280.08:01:29.34#ibcon#end of sib2, iclass 40, count 2 2006.280.08:01:29.34#ibcon#*after write, iclass 40, count 2 2006.280.08:01:29.34#ibcon#*before return 0, iclass 40, count 2 2006.280.08:01:29.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:29.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:29.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:01:29.34#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:29.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:29.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:29.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:29.46#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:01:29.46#ibcon#first serial, iclass 40, count 0 2006.280.08:01:29.46#ibcon#enter sib2, iclass 40, count 0 2006.280.08:01:29.46#ibcon#flushed, iclass 40, count 0 2006.280.08:01:29.46#ibcon#about to write, iclass 40, count 0 2006.280.08:01:29.46#ibcon#wrote, iclass 40, count 0 2006.280.08:01:29.46#ibcon#about to read 3, iclass 40, count 0 2006.280.08:01:29.48#ibcon#read 3, iclass 40, count 0 2006.280.08:01:29.48#ibcon#about to read 4, iclass 40, count 0 2006.280.08:01:29.48#ibcon#read 4, iclass 40, count 0 2006.280.08:01:29.48#ibcon#about to read 5, iclass 40, count 0 2006.280.08:01:29.48#ibcon#read 5, iclass 40, count 0 2006.280.08:01:29.48#ibcon#about to read 6, iclass 40, count 0 2006.280.08:01:29.48#ibcon#read 6, iclass 40, count 0 2006.280.08:01:29.48#ibcon#end of sib2, iclass 40, count 0 2006.280.08:01:29.48#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:01:29.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:01:29.48#ibcon#[25=USB\r\n] 2006.280.08:01:29.48#ibcon#*before write, iclass 40, count 0 2006.280.08:01:29.48#ibcon#enter sib2, iclass 40, count 0 2006.280.08:01:29.48#ibcon#flushed, iclass 40, count 0 2006.280.08:01:29.48#ibcon#about to write, iclass 40, count 0 2006.280.08:01:29.48#ibcon#wrote, iclass 40, count 0 2006.280.08:01:29.48#ibcon#about to read 3, iclass 40, count 0 2006.280.08:01:29.51#ibcon#read 3, iclass 40, count 0 2006.280.08:01:29.51#ibcon#about to read 4, iclass 40, count 0 2006.280.08:01:29.51#ibcon#read 4, iclass 40, count 0 2006.280.08:01:29.51#ibcon#about to read 5, iclass 40, count 0 2006.280.08:01:29.51#ibcon#read 5, iclass 40, count 0 2006.280.08:01:29.51#ibcon#about to read 6, iclass 40, count 0 2006.280.08:01:29.51#ibcon#read 6, iclass 40, count 0 2006.280.08:01:29.51#ibcon#end of sib2, iclass 40, count 0 2006.280.08:01:29.51#ibcon#*after write, iclass 40, count 0 2006.280.08:01:29.51#ibcon#*before return 0, iclass 40, count 0 2006.280.08:01:29.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:29.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:29.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:01:29.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:01:29.51$vc4f8/valo=7,832.99 2006.280.08:01:29.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:01:29.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:01:29.51#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:29.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:29.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:29.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:29.51#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:01:29.51#ibcon#first serial, iclass 4, count 0 2006.280.08:01:29.51#ibcon#enter sib2, iclass 4, count 0 2006.280.08:01:29.51#ibcon#flushed, iclass 4, count 0 2006.280.08:01:29.51#ibcon#about to write, iclass 4, count 0 2006.280.08:01:29.51#ibcon#wrote, iclass 4, count 0 2006.280.08:01:29.51#ibcon#about to read 3, iclass 4, count 0 2006.280.08:01:29.53#ibcon#read 3, iclass 4, count 0 2006.280.08:01:29.53#ibcon#about to read 4, iclass 4, count 0 2006.280.08:01:29.53#ibcon#read 4, iclass 4, count 0 2006.280.08:01:29.53#ibcon#about to read 5, iclass 4, count 0 2006.280.08:01:29.53#ibcon#read 5, iclass 4, count 0 2006.280.08:01:29.53#ibcon#about to read 6, iclass 4, count 0 2006.280.08:01:29.53#ibcon#read 6, iclass 4, count 0 2006.280.08:01:29.53#ibcon#end of sib2, iclass 4, count 0 2006.280.08:01:29.53#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:01:29.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:01:29.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:01:29.53#ibcon#*before write, iclass 4, count 0 2006.280.08:01:29.53#ibcon#enter sib2, iclass 4, count 0 2006.280.08:01:29.53#ibcon#flushed, iclass 4, count 0 2006.280.08:01:29.53#ibcon#about to write, iclass 4, count 0 2006.280.08:01:29.53#ibcon#wrote, iclass 4, count 0 2006.280.08:01:29.53#ibcon#about to read 3, iclass 4, count 0 2006.280.08:01:29.57#ibcon#read 3, iclass 4, count 0 2006.280.08:01:29.57#ibcon#about to read 4, iclass 4, count 0 2006.280.08:01:29.57#ibcon#read 4, iclass 4, count 0 2006.280.08:01:29.57#ibcon#about to read 5, iclass 4, count 0 2006.280.08:01:29.57#ibcon#read 5, iclass 4, count 0 2006.280.08:01:29.57#ibcon#about to read 6, iclass 4, count 0 2006.280.08:01:29.57#ibcon#read 6, iclass 4, count 0 2006.280.08:01:29.57#ibcon#end of sib2, iclass 4, count 0 2006.280.08:01:29.57#ibcon#*after write, iclass 4, count 0 2006.280.08:01:29.57#ibcon#*before return 0, iclass 4, count 0 2006.280.08:01:29.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:29.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:29.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:01:29.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:01:29.57$vc4f8/va=7,6 2006.280.08:01:29.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:01:29.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:01:29.57#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:29.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:29.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:29.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:29.63#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:01:29.63#ibcon#first serial, iclass 6, count 2 2006.280.08:01:29.63#ibcon#enter sib2, iclass 6, count 2 2006.280.08:01:29.63#ibcon#flushed, iclass 6, count 2 2006.280.08:01:29.63#ibcon#about to write, iclass 6, count 2 2006.280.08:01:29.63#ibcon#wrote, iclass 6, count 2 2006.280.08:01:29.63#ibcon#about to read 3, iclass 6, count 2 2006.280.08:01:29.65#ibcon#read 3, iclass 6, count 2 2006.280.08:01:29.65#ibcon#about to read 4, iclass 6, count 2 2006.280.08:01:29.65#ibcon#read 4, iclass 6, count 2 2006.280.08:01:29.65#ibcon#about to read 5, iclass 6, count 2 2006.280.08:01:29.65#ibcon#read 5, iclass 6, count 2 2006.280.08:01:29.65#ibcon#about to read 6, iclass 6, count 2 2006.280.08:01:29.65#ibcon#read 6, iclass 6, count 2 2006.280.08:01:29.65#ibcon#end of sib2, iclass 6, count 2 2006.280.08:01:29.65#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:01:29.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:01:29.65#ibcon#[25=AT07-06\r\n] 2006.280.08:01:29.65#ibcon#*before write, iclass 6, count 2 2006.280.08:01:29.65#ibcon#enter sib2, iclass 6, count 2 2006.280.08:01:29.65#ibcon#flushed, iclass 6, count 2 2006.280.08:01:29.65#ibcon#about to write, iclass 6, count 2 2006.280.08:01:29.65#ibcon#wrote, iclass 6, count 2 2006.280.08:01:29.65#ibcon#about to read 3, iclass 6, count 2 2006.280.08:01:29.69#ibcon#read 3, iclass 6, count 2 2006.280.08:01:29.69#ibcon#about to read 4, iclass 6, count 2 2006.280.08:01:29.69#ibcon#read 4, iclass 6, count 2 2006.280.08:01:29.69#ibcon#about to read 5, iclass 6, count 2 2006.280.08:01:29.69#ibcon#read 5, iclass 6, count 2 2006.280.08:01:29.69#ibcon#about to read 6, iclass 6, count 2 2006.280.08:01:29.69#ibcon#read 6, iclass 6, count 2 2006.280.08:01:29.69#ibcon#end of sib2, iclass 6, count 2 2006.280.08:01:29.69#ibcon#*after write, iclass 6, count 2 2006.280.08:01:29.69#ibcon#*before return 0, iclass 6, count 2 2006.280.08:01:29.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:29.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:29.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:01:29.69#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:29.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:01:29.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:01:29.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:01:29.81#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:01:29.81#ibcon#first serial, iclass 6, count 0 2006.280.08:01:29.81#ibcon#enter sib2, iclass 6, count 0 2006.280.08:01:29.81#ibcon#flushed, iclass 6, count 0 2006.280.08:01:29.81#ibcon#about to write, iclass 6, count 0 2006.280.08:01:29.81#ibcon#wrote, iclass 6, count 0 2006.280.08:01:29.81#ibcon#about to read 3, iclass 6, count 0 2006.280.08:01:29.83#ibcon#read 3, iclass 6, count 0 2006.280.08:01:29.83#ibcon#about to read 4, iclass 6, count 0 2006.280.08:01:29.83#ibcon#read 4, iclass 6, count 0 2006.280.08:01:29.83#ibcon#about to read 5, iclass 6, count 0 2006.280.08:01:29.83#ibcon#read 5, iclass 6, count 0 2006.280.08:01:29.83#ibcon#about to read 6, iclass 6, count 0 2006.280.08:01:29.83#ibcon#read 6, iclass 6, count 0 2006.280.08:01:29.83#ibcon#end of sib2, iclass 6, count 0 2006.280.08:01:29.83#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:01:29.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:01:29.83#ibcon#[25=USB\r\n] 2006.280.08:01:29.83#ibcon#*before write, iclass 6, count 0 2006.280.08:01:29.83#ibcon#enter sib2, iclass 6, count 0 2006.280.08:01:29.83#ibcon#flushed, iclass 6, count 0 2006.280.08:01:29.83#ibcon#about to write, iclass 6, count 0 2006.280.08:01:29.83#ibcon#wrote, iclass 6, count 0 2006.280.08:01:29.83#ibcon#about to read 3, iclass 6, count 0 2006.280.08:01:29.86#ibcon#read 3, iclass 6, count 0 2006.280.08:01:29.86#ibcon#about to read 4, iclass 6, count 0 2006.280.08:01:29.86#ibcon#read 4, iclass 6, count 0 2006.280.08:01:29.86#ibcon#about to read 5, iclass 6, count 0 2006.280.08:01:29.86#ibcon#read 5, iclass 6, count 0 2006.280.08:01:29.86#ibcon#about to read 6, iclass 6, count 0 2006.280.08:01:29.86#ibcon#read 6, iclass 6, count 0 2006.280.08:01:29.86#ibcon#end of sib2, iclass 6, count 0 2006.280.08:01:29.86#ibcon#*after write, iclass 6, count 0 2006.280.08:01:29.86#ibcon#*before return 0, iclass 6, count 0 2006.280.08:01:29.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:01:29.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:01:29.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:01:29.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:01:29.86$vc4f8/valo=8,852.99 2006.280.08:01:29.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:01:29.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:01:29.86#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:29.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:01:29.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:01:29.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:01:29.86#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:01:29.86#ibcon#first serial, iclass 10, count 0 2006.280.08:01:29.86#ibcon#enter sib2, iclass 10, count 0 2006.280.08:01:29.86#ibcon#flushed, iclass 10, count 0 2006.280.08:01:29.86#ibcon#about to write, iclass 10, count 0 2006.280.08:01:29.86#ibcon#wrote, iclass 10, count 0 2006.280.08:01:29.86#ibcon#about to read 3, iclass 10, count 0 2006.280.08:01:29.88#ibcon#read 3, iclass 10, count 0 2006.280.08:01:29.88#ibcon#about to read 4, iclass 10, count 0 2006.280.08:01:29.88#ibcon#read 4, iclass 10, count 0 2006.280.08:01:29.88#ibcon#about to read 5, iclass 10, count 0 2006.280.08:01:29.88#ibcon#read 5, iclass 10, count 0 2006.280.08:01:29.88#ibcon#about to read 6, iclass 10, count 0 2006.280.08:01:29.88#ibcon#read 6, iclass 10, count 0 2006.280.08:01:29.88#ibcon#end of sib2, iclass 10, count 0 2006.280.08:01:29.88#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:01:29.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:01:29.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:01:29.88#ibcon#*before write, iclass 10, count 0 2006.280.08:01:29.88#ibcon#enter sib2, iclass 10, count 0 2006.280.08:01:29.88#ibcon#flushed, iclass 10, count 0 2006.280.08:01:29.88#ibcon#about to write, iclass 10, count 0 2006.280.08:01:29.88#ibcon#wrote, iclass 10, count 0 2006.280.08:01:29.88#ibcon#about to read 3, iclass 10, count 0 2006.280.08:01:29.92#ibcon#read 3, iclass 10, count 0 2006.280.08:01:29.92#ibcon#about to read 4, iclass 10, count 0 2006.280.08:01:29.92#ibcon#read 4, iclass 10, count 0 2006.280.08:01:29.92#ibcon#about to read 5, iclass 10, count 0 2006.280.08:01:29.92#ibcon#read 5, iclass 10, count 0 2006.280.08:01:29.92#ibcon#about to read 6, iclass 10, count 0 2006.280.08:01:29.92#ibcon#read 6, iclass 10, count 0 2006.280.08:01:29.92#ibcon#end of sib2, iclass 10, count 0 2006.280.08:01:29.92#ibcon#*after write, iclass 10, count 0 2006.280.08:01:29.92#ibcon#*before return 0, iclass 10, count 0 2006.280.08:01:29.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:01:29.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:01:29.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:01:29.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:01:29.92$vc4f8/va=8,6 2006.280.08:01:29.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:01:29.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:01:29.93#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:29.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:01:29.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:01:29.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:01:29.97#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:01:29.97#ibcon#first serial, iclass 12, count 2 2006.280.08:01:29.97#ibcon#enter sib2, iclass 12, count 2 2006.280.08:01:29.97#ibcon#flushed, iclass 12, count 2 2006.280.08:01:29.97#ibcon#about to write, iclass 12, count 2 2006.280.08:01:29.97#ibcon#wrote, iclass 12, count 2 2006.280.08:01:29.97#ibcon#about to read 3, iclass 12, count 2 2006.280.08:01:29.99#ibcon#read 3, iclass 12, count 2 2006.280.08:01:29.99#ibcon#about to read 4, iclass 12, count 2 2006.280.08:01:29.99#ibcon#read 4, iclass 12, count 2 2006.280.08:01:29.99#ibcon#about to read 5, iclass 12, count 2 2006.280.08:01:29.99#ibcon#read 5, iclass 12, count 2 2006.280.08:01:29.99#ibcon#about to read 6, iclass 12, count 2 2006.280.08:01:29.99#ibcon#read 6, iclass 12, count 2 2006.280.08:01:29.99#ibcon#end of sib2, iclass 12, count 2 2006.280.08:01:29.99#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:01:29.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:01:29.99#ibcon#[25=AT08-06\r\n] 2006.280.08:01:29.99#ibcon#*before write, iclass 12, count 2 2006.280.08:01:29.99#ibcon#enter sib2, iclass 12, count 2 2006.280.08:01:29.99#ibcon#flushed, iclass 12, count 2 2006.280.08:01:29.99#ibcon#about to write, iclass 12, count 2 2006.280.08:01:29.99#ibcon#wrote, iclass 12, count 2 2006.280.08:01:29.99#ibcon#about to read 3, iclass 12, count 2 2006.280.08:01:30.02#abcon#<5=/14 1.8 4.9 20.90 62 987.2\r\n> 2006.280.08:01:30.02#ibcon#read 3, iclass 12, count 2 2006.280.08:01:30.02#ibcon#about to read 4, iclass 12, count 2 2006.280.08:01:30.02#ibcon#read 4, iclass 12, count 2 2006.280.08:01:30.02#ibcon#about to read 5, iclass 12, count 2 2006.280.08:01:30.02#ibcon#read 5, iclass 12, count 2 2006.280.08:01:30.02#ibcon#about to read 6, iclass 12, count 2 2006.280.08:01:30.02#ibcon#read 6, iclass 12, count 2 2006.280.08:01:30.02#ibcon#end of sib2, iclass 12, count 2 2006.280.08:01:30.02#ibcon#*after write, iclass 12, count 2 2006.280.08:01:30.02#ibcon#*before return 0, iclass 12, count 2 2006.280.08:01:30.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:01:30.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:01:30.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:01:30.03#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:30.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:01:30.04#abcon#{5=INTERFACE CLEAR} 2006.280.08:01:30.10#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:01:30.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:01:30.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:01:30.13#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:01:30.13#ibcon#first serial, iclass 12, count 0 2006.280.08:01:30.13#ibcon#enter sib2, iclass 12, count 0 2006.280.08:01:30.13#ibcon#flushed, iclass 12, count 0 2006.280.08:01:30.13#ibcon#about to write, iclass 12, count 0 2006.280.08:01:30.13#ibcon#wrote, iclass 12, count 0 2006.280.08:01:30.13#ibcon#about to read 3, iclass 12, count 0 2006.280.08:01:30.15#ibcon#read 3, iclass 12, count 0 2006.280.08:01:30.15#ibcon#about to read 4, iclass 12, count 0 2006.280.08:01:30.15#ibcon#read 4, iclass 12, count 0 2006.280.08:01:30.15#ibcon#about to read 5, iclass 12, count 0 2006.280.08:01:30.15#ibcon#read 5, iclass 12, count 0 2006.280.08:01:30.15#ibcon#about to read 6, iclass 12, count 0 2006.280.08:01:30.15#ibcon#read 6, iclass 12, count 0 2006.280.08:01:30.15#ibcon#end of sib2, iclass 12, count 0 2006.280.08:01:30.15#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:01:30.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:01:30.15#ibcon#[25=USB\r\n] 2006.280.08:01:30.15#ibcon#*before write, iclass 12, count 0 2006.280.08:01:30.15#ibcon#enter sib2, iclass 12, count 0 2006.280.08:01:30.15#ibcon#flushed, iclass 12, count 0 2006.280.08:01:30.15#ibcon#about to write, iclass 12, count 0 2006.280.08:01:30.15#ibcon#wrote, iclass 12, count 0 2006.280.08:01:30.15#ibcon#about to read 3, iclass 12, count 0 2006.280.08:01:30.19#ibcon#read 3, iclass 12, count 0 2006.280.08:01:30.19#ibcon#about to read 4, iclass 12, count 0 2006.280.08:01:30.19#ibcon#read 4, iclass 12, count 0 2006.280.08:01:30.19#ibcon#about to read 5, iclass 12, count 0 2006.280.08:01:30.19#ibcon#read 5, iclass 12, count 0 2006.280.08:01:30.19#ibcon#about to read 6, iclass 12, count 0 2006.280.08:01:30.19#ibcon#read 6, iclass 12, count 0 2006.280.08:01:30.19#ibcon#end of sib2, iclass 12, count 0 2006.280.08:01:30.19#ibcon#*after write, iclass 12, count 0 2006.280.08:01:30.19#ibcon#*before return 0, iclass 12, count 0 2006.280.08:01:30.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:01:30.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:01:30.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:01:30.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:01:30.19$vc4f8/vblo=1,632.99 2006.280.08:01:30.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:01:30.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:01:30.19#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:30.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:30.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:30.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:30.19#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:01:30.19#ibcon#first serial, iclass 18, count 0 2006.280.08:01:30.19#ibcon#enter sib2, iclass 18, count 0 2006.280.08:01:30.19#ibcon#flushed, iclass 18, count 0 2006.280.08:01:30.19#ibcon#about to write, iclass 18, count 0 2006.280.08:01:30.19#ibcon#wrote, iclass 18, count 0 2006.280.08:01:30.19#ibcon#about to read 3, iclass 18, count 0 2006.280.08:01:30.20#ibcon#read 3, iclass 18, count 0 2006.280.08:01:30.20#ibcon#about to read 4, iclass 18, count 0 2006.280.08:01:30.20#ibcon#read 4, iclass 18, count 0 2006.280.08:01:30.20#ibcon#about to read 5, iclass 18, count 0 2006.280.08:01:30.20#ibcon#read 5, iclass 18, count 0 2006.280.08:01:30.20#ibcon#about to read 6, iclass 18, count 0 2006.280.08:01:30.20#ibcon#read 6, iclass 18, count 0 2006.280.08:01:30.20#ibcon#end of sib2, iclass 18, count 0 2006.280.08:01:30.20#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:01:30.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:01:30.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:01:30.20#ibcon#*before write, iclass 18, count 0 2006.280.08:01:30.20#ibcon#enter sib2, iclass 18, count 0 2006.280.08:01:30.20#ibcon#flushed, iclass 18, count 0 2006.280.08:01:30.20#ibcon#about to write, iclass 18, count 0 2006.280.08:01:30.20#ibcon#wrote, iclass 18, count 0 2006.280.08:01:30.20#ibcon#about to read 3, iclass 18, count 0 2006.280.08:01:30.24#ibcon#read 3, iclass 18, count 0 2006.280.08:01:30.24#ibcon#about to read 4, iclass 18, count 0 2006.280.08:01:30.24#ibcon#read 4, iclass 18, count 0 2006.280.08:01:30.24#ibcon#about to read 5, iclass 18, count 0 2006.280.08:01:30.24#ibcon#read 5, iclass 18, count 0 2006.280.08:01:30.24#ibcon#about to read 6, iclass 18, count 0 2006.280.08:01:30.24#ibcon#read 6, iclass 18, count 0 2006.280.08:01:30.24#ibcon#end of sib2, iclass 18, count 0 2006.280.08:01:30.24#ibcon#*after write, iclass 18, count 0 2006.280.08:01:30.24#ibcon#*before return 0, iclass 18, count 0 2006.280.08:01:30.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:30.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:01:30.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:01:30.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:01:30.24$vc4f8/vb=1,4 2006.280.08:01:30.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:01:30.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:01:30.24#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:30.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:30.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:30.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:30.24#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:01:30.24#ibcon#first serial, iclass 20, count 2 2006.280.08:01:30.24#ibcon#enter sib2, iclass 20, count 2 2006.280.08:01:30.24#ibcon#flushed, iclass 20, count 2 2006.280.08:01:30.24#ibcon#about to write, iclass 20, count 2 2006.280.08:01:30.24#ibcon#wrote, iclass 20, count 2 2006.280.08:01:30.24#ibcon#about to read 3, iclass 20, count 2 2006.280.08:01:30.26#ibcon#read 3, iclass 20, count 2 2006.280.08:01:30.26#ibcon#about to read 4, iclass 20, count 2 2006.280.08:01:30.26#ibcon#read 4, iclass 20, count 2 2006.280.08:01:30.26#ibcon#about to read 5, iclass 20, count 2 2006.280.08:01:30.26#ibcon#read 5, iclass 20, count 2 2006.280.08:01:30.26#ibcon#about to read 6, iclass 20, count 2 2006.280.08:01:30.26#ibcon#read 6, iclass 20, count 2 2006.280.08:01:30.26#ibcon#end of sib2, iclass 20, count 2 2006.280.08:01:30.26#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:01:30.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:01:30.26#ibcon#[27=AT01-04\r\n] 2006.280.08:01:30.26#ibcon#*before write, iclass 20, count 2 2006.280.08:01:30.26#ibcon#enter sib2, iclass 20, count 2 2006.280.08:01:30.26#ibcon#flushed, iclass 20, count 2 2006.280.08:01:30.26#ibcon#about to write, iclass 20, count 2 2006.280.08:01:30.26#ibcon#wrote, iclass 20, count 2 2006.280.08:01:30.26#ibcon#about to read 3, iclass 20, count 2 2006.280.08:01:30.29#ibcon#read 3, iclass 20, count 2 2006.280.08:01:30.29#ibcon#about to read 4, iclass 20, count 2 2006.280.08:01:30.29#ibcon#read 4, iclass 20, count 2 2006.280.08:01:30.29#ibcon#about to read 5, iclass 20, count 2 2006.280.08:01:30.29#ibcon#read 5, iclass 20, count 2 2006.280.08:01:30.29#ibcon#about to read 6, iclass 20, count 2 2006.280.08:01:30.29#ibcon#read 6, iclass 20, count 2 2006.280.08:01:30.29#ibcon#end of sib2, iclass 20, count 2 2006.280.08:01:30.29#ibcon#*after write, iclass 20, count 2 2006.280.08:01:30.29#ibcon#*before return 0, iclass 20, count 2 2006.280.08:01:30.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:30.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:01:30.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:01:30.29#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:30.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:30.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:30.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:30.41#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:01:30.41#ibcon#first serial, iclass 20, count 0 2006.280.08:01:30.41#ibcon#enter sib2, iclass 20, count 0 2006.280.08:01:30.41#ibcon#flushed, iclass 20, count 0 2006.280.08:01:30.41#ibcon#about to write, iclass 20, count 0 2006.280.08:01:30.41#ibcon#wrote, iclass 20, count 0 2006.280.08:01:30.41#ibcon#about to read 3, iclass 20, count 0 2006.280.08:01:30.43#ibcon#read 3, iclass 20, count 0 2006.280.08:01:30.43#ibcon#about to read 4, iclass 20, count 0 2006.280.08:01:30.43#ibcon#read 4, iclass 20, count 0 2006.280.08:01:30.43#ibcon#about to read 5, iclass 20, count 0 2006.280.08:01:30.43#ibcon#read 5, iclass 20, count 0 2006.280.08:01:30.43#ibcon#about to read 6, iclass 20, count 0 2006.280.08:01:30.43#ibcon#read 6, iclass 20, count 0 2006.280.08:01:30.43#ibcon#end of sib2, iclass 20, count 0 2006.280.08:01:30.43#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:01:30.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:01:30.43#ibcon#[27=USB\r\n] 2006.280.08:01:30.43#ibcon#*before write, iclass 20, count 0 2006.280.08:01:30.43#ibcon#enter sib2, iclass 20, count 0 2006.280.08:01:30.43#ibcon#flushed, iclass 20, count 0 2006.280.08:01:30.43#ibcon#about to write, iclass 20, count 0 2006.280.08:01:30.43#ibcon#wrote, iclass 20, count 0 2006.280.08:01:30.43#ibcon#about to read 3, iclass 20, count 0 2006.280.08:01:30.46#ibcon#read 3, iclass 20, count 0 2006.280.08:01:30.46#ibcon#about to read 4, iclass 20, count 0 2006.280.08:01:30.46#ibcon#read 4, iclass 20, count 0 2006.280.08:01:30.46#ibcon#about to read 5, iclass 20, count 0 2006.280.08:01:30.46#ibcon#read 5, iclass 20, count 0 2006.280.08:01:30.46#ibcon#about to read 6, iclass 20, count 0 2006.280.08:01:30.46#ibcon#read 6, iclass 20, count 0 2006.280.08:01:30.46#ibcon#end of sib2, iclass 20, count 0 2006.280.08:01:30.46#ibcon#*after write, iclass 20, count 0 2006.280.08:01:30.46#ibcon#*before return 0, iclass 20, count 0 2006.280.08:01:30.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:30.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:01:30.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:01:30.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:01:30.46$vc4f8/vblo=2,640.99 2006.280.08:01:30.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:01:30.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:01:30.46#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:30.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:30.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:30.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:30.46#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:01:30.46#ibcon#first serial, iclass 22, count 0 2006.280.08:01:30.46#ibcon#enter sib2, iclass 22, count 0 2006.280.08:01:30.46#ibcon#flushed, iclass 22, count 0 2006.280.08:01:30.46#ibcon#about to write, iclass 22, count 0 2006.280.08:01:30.46#ibcon#wrote, iclass 22, count 0 2006.280.08:01:30.46#ibcon#about to read 3, iclass 22, count 0 2006.280.08:01:30.48#ibcon#read 3, iclass 22, count 0 2006.280.08:01:30.48#ibcon#about to read 4, iclass 22, count 0 2006.280.08:01:30.48#ibcon#read 4, iclass 22, count 0 2006.280.08:01:30.48#ibcon#about to read 5, iclass 22, count 0 2006.280.08:01:30.48#ibcon#read 5, iclass 22, count 0 2006.280.08:01:30.48#ibcon#about to read 6, iclass 22, count 0 2006.280.08:01:30.48#ibcon#read 6, iclass 22, count 0 2006.280.08:01:30.48#ibcon#end of sib2, iclass 22, count 0 2006.280.08:01:30.48#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:01:30.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:01:30.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:01:30.48#ibcon#*before write, iclass 22, count 0 2006.280.08:01:30.48#ibcon#enter sib2, iclass 22, count 0 2006.280.08:01:30.48#ibcon#flushed, iclass 22, count 0 2006.280.08:01:30.48#ibcon#about to write, iclass 22, count 0 2006.280.08:01:30.48#ibcon#wrote, iclass 22, count 0 2006.280.08:01:30.48#ibcon#about to read 3, iclass 22, count 0 2006.280.08:01:30.52#ibcon#read 3, iclass 22, count 0 2006.280.08:01:30.52#ibcon#about to read 4, iclass 22, count 0 2006.280.08:01:30.52#ibcon#read 4, iclass 22, count 0 2006.280.08:01:30.52#ibcon#about to read 5, iclass 22, count 0 2006.280.08:01:30.52#ibcon#read 5, iclass 22, count 0 2006.280.08:01:30.52#ibcon#about to read 6, iclass 22, count 0 2006.280.08:01:30.52#ibcon#read 6, iclass 22, count 0 2006.280.08:01:30.52#ibcon#end of sib2, iclass 22, count 0 2006.280.08:01:30.52#ibcon#*after write, iclass 22, count 0 2006.280.08:01:30.52#ibcon#*before return 0, iclass 22, count 0 2006.280.08:01:30.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:30.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:01:30.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:01:30.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:01:30.52$vc4f8/vb=2,5 2006.280.08:01:30.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:01:30.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:01:30.52#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:30.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:30.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:30.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:30.58#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:01:30.58#ibcon#first serial, iclass 24, count 2 2006.280.08:01:30.58#ibcon#enter sib2, iclass 24, count 2 2006.280.08:01:30.58#ibcon#flushed, iclass 24, count 2 2006.280.08:01:30.58#ibcon#about to write, iclass 24, count 2 2006.280.08:01:30.58#ibcon#wrote, iclass 24, count 2 2006.280.08:01:30.58#ibcon#about to read 3, iclass 24, count 2 2006.280.08:01:30.60#ibcon#read 3, iclass 24, count 2 2006.280.08:01:30.60#ibcon#about to read 4, iclass 24, count 2 2006.280.08:01:30.60#ibcon#read 4, iclass 24, count 2 2006.280.08:01:30.60#ibcon#about to read 5, iclass 24, count 2 2006.280.08:01:30.60#ibcon#read 5, iclass 24, count 2 2006.280.08:01:30.60#ibcon#about to read 6, iclass 24, count 2 2006.280.08:01:30.60#ibcon#read 6, iclass 24, count 2 2006.280.08:01:30.60#ibcon#end of sib2, iclass 24, count 2 2006.280.08:01:30.60#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:01:30.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:01:30.60#ibcon#[27=AT02-05\r\n] 2006.280.08:01:30.60#ibcon#*before write, iclass 24, count 2 2006.280.08:01:30.60#ibcon#enter sib2, iclass 24, count 2 2006.280.08:01:30.60#ibcon#flushed, iclass 24, count 2 2006.280.08:01:30.60#ibcon#about to write, iclass 24, count 2 2006.280.08:01:30.60#ibcon#wrote, iclass 24, count 2 2006.280.08:01:30.60#ibcon#about to read 3, iclass 24, count 2 2006.280.08:01:30.64#ibcon#read 3, iclass 24, count 2 2006.280.08:01:30.64#ibcon#about to read 4, iclass 24, count 2 2006.280.08:01:30.64#ibcon#read 4, iclass 24, count 2 2006.280.08:01:30.64#ibcon#about to read 5, iclass 24, count 2 2006.280.08:01:30.64#ibcon#read 5, iclass 24, count 2 2006.280.08:01:30.64#ibcon#about to read 6, iclass 24, count 2 2006.280.08:01:30.64#ibcon#read 6, iclass 24, count 2 2006.280.08:01:30.64#ibcon#end of sib2, iclass 24, count 2 2006.280.08:01:30.64#ibcon#*after write, iclass 24, count 2 2006.280.08:01:30.64#ibcon#*before return 0, iclass 24, count 2 2006.280.08:01:30.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:30.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:01:30.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:01:30.64#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:30.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:30.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:30.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:30.75#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:01:30.75#ibcon#first serial, iclass 24, count 0 2006.280.08:01:30.75#ibcon#enter sib2, iclass 24, count 0 2006.280.08:01:30.75#ibcon#flushed, iclass 24, count 0 2006.280.08:01:30.75#ibcon#about to write, iclass 24, count 0 2006.280.08:01:30.75#ibcon#wrote, iclass 24, count 0 2006.280.08:01:30.75#ibcon#about to read 3, iclass 24, count 0 2006.280.08:01:30.77#ibcon#read 3, iclass 24, count 0 2006.280.08:01:30.77#ibcon#about to read 4, iclass 24, count 0 2006.280.08:01:30.77#ibcon#read 4, iclass 24, count 0 2006.280.08:01:30.77#ibcon#about to read 5, iclass 24, count 0 2006.280.08:01:30.77#ibcon#read 5, iclass 24, count 0 2006.280.08:01:30.77#ibcon#about to read 6, iclass 24, count 0 2006.280.08:01:30.77#ibcon#read 6, iclass 24, count 0 2006.280.08:01:30.77#ibcon#end of sib2, iclass 24, count 0 2006.280.08:01:30.77#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:01:30.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:01:30.77#ibcon#[27=USB\r\n] 2006.280.08:01:30.77#ibcon#*before write, iclass 24, count 0 2006.280.08:01:30.77#ibcon#enter sib2, iclass 24, count 0 2006.280.08:01:30.77#ibcon#flushed, iclass 24, count 0 2006.280.08:01:30.77#ibcon#about to write, iclass 24, count 0 2006.280.08:01:30.77#ibcon#wrote, iclass 24, count 0 2006.280.08:01:30.77#ibcon#about to read 3, iclass 24, count 0 2006.280.08:01:30.80#ibcon#read 3, iclass 24, count 0 2006.280.08:01:30.80#ibcon#about to read 4, iclass 24, count 0 2006.280.08:01:30.80#ibcon#read 4, iclass 24, count 0 2006.280.08:01:30.80#ibcon#about to read 5, iclass 24, count 0 2006.280.08:01:30.80#ibcon#read 5, iclass 24, count 0 2006.280.08:01:30.80#ibcon#about to read 6, iclass 24, count 0 2006.280.08:01:30.80#ibcon#read 6, iclass 24, count 0 2006.280.08:01:30.80#ibcon#end of sib2, iclass 24, count 0 2006.280.08:01:30.80#ibcon#*after write, iclass 24, count 0 2006.280.08:01:30.80#ibcon#*before return 0, iclass 24, count 0 2006.280.08:01:30.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:30.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:01:30.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:01:30.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:01:30.80$vc4f8/vblo=3,656.99 2006.280.08:01:30.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:01:30.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:01:30.80#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:30.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:30.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:30.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:30.80#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:01:30.80#ibcon#first serial, iclass 26, count 0 2006.280.08:01:30.80#ibcon#enter sib2, iclass 26, count 0 2006.280.08:01:30.80#ibcon#flushed, iclass 26, count 0 2006.280.08:01:30.80#ibcon#about to write, iclass 26, count 0 2006.280.08:01:30.80#ibcon#wrote, iclass 26, count 0 2006.280.08:01:30.80#ibcon#about to read 3, iclass 26, count 0 2006.280.08:01:30.82#ibcon#read 3, iclass 26, count 0 2006.280.08:01:30.82#ibcon#about to read 4, iclass 26, count 0 2006.280.08:01:30.82#ibcon#read 4, iclass 26, count 0 2006.280.08:01:30.82#ibcon#about to read 5, iclass 26, count 0 2006.280.08:01:30.82#ibcon#read 5, iclass 26, count 0 2006.280.08:01:30.82#ibcon#about to read 6, iclass 26, count 0 2006.280.08:01:30.82#ibcon#read 6, iclass 26, count 0 2006.280.08:01:30.82#ibcon#end of sib2, iclass 26, count 0 2006.280.08:01:30.82#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:01:30.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:01:30.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:01:30.82#ibcon#*before write, iclass 26, count 0 2006.280.08:01:30.82#ibcon#enter sib2, iclass 26, count 0 2006.280.08:01:30.82#ibcon#flushed, iclass 26, count 0 2006.280.08:01:30.82#ibcon#about to write, iclass 26, count 0 2006.280.08:01:30.82#ibcon#wrote, iclass 26, count 0 2006.280.08:01:30.82#ibcon#about to read 3, iclass 26, count 0 2006.280.08:01:30.86#ibcon#read 3, iclass 26, count 0 2006.280.08:01:30.86#ibcon#about to read 4, iclass 26, count 0 2006.280.08:01:30.86#ibcon#read 4, iclass 26, count 0 2006.280.08:01:30.86#ibcon#about to read 5, iclass 26, count 0 2006.280.08:01:30.86#ibcon#read 5, iclass 26, count 0 2006.280.08:01:30.86#ibcon#about to read 6, iclass 26, count 0 2006.280.08:01:30.86#ibcon#read 6, iclass 26, count 0 2006.280.08:01:30.86#ibcon#end of sib2, iclass 26, count 0 2006.280.08:01:30.86#ibcon#*after write, iclass 26, count 0 2006.280.08:01:30.86#ibcon#*before return 0, iclass 26, count 0 2006.280.08:01:30.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:30.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:01:30.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:01:30.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:01:30.86$vc4f8/vb=3,4 2006.280.08:01:30.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:01:30.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:01:30.88#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:30.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:30.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:30.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:30.91#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:01:30.91#ibcon#first serial, iclass 28, count 2 2006.280.08:01:30.91#ibcon#enter sib2, iclass 28, count 2 2006.280.08:01:30.91#ibcon#flushed, iclass 28, count 2 2006.280.08:01:30.91#ibcon#about to write, iclass 28, count 2 2006.280.08:01:30.91#ibcon#wrote, iclass 28, count 2 2006.280.08:01:30.91#ibcon#about to read 3, iclass 28, count 2 2006.280.08:01:30.93#ibcon#read 3, iclass 28, count 2 2006.280.08:01:30.93#ibcon#about to read 4, iclass 28, count 2 2006.280.08:01:30.93#ibcon#read 4, iclass 28, count 2 2006.280.08:01:30.93#ibcon#about to read 5, iclass 28, count 2 2006.280.08:01:30.93#ibcon#read 5, iclass 28, count 2 2006.280.08:01:30.93#ibcon#about to read 6, iclass 28, count 2 2006.280.08:01:30.93#ibcon#read 6, iclass 28, count 2 2006.280.08:01:30.93#ibcon#end of sib2, iclass 28, count 2 2006.280.08:01:30.93#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:01:30.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:01:30.93#ibcon#[27=AT03-04\r\n] 2006.280.08:01:30.93#ibcon#*before write, iclass 28, count 2 2006.280.08:01:30.93#ibcon#enter sib2, iclass 28, count 2 2006.280.08:01:30.93#ibcon#flushed, iclass 28, count 2 2006.280.08:01:30.93#ibcon#about to write, iclass 28, count 2 2006.280.08:01:30.93#ibcon#wrote, iclass 28, count 2 2006.280.08:01:30.93#ibcon#about to read 3, iclass 28, count 2 2006.280.08:01:30.96#ibcon#read 3, iclass 28, count 2 2006.280.08:01:30.96#ibcon#about to read 4, iclass 28, count 2 2006.280.08:01:30.96#ibcon#read 4, iclass 28, count 2 2006.280.08:01:30.96#ibcon#about to read 5, iclass 28, count 2 2006.280.08:01:30.96#ibcon#read 5, iclass 28, count 2 2006.280.08:01:30.96#ibcon#about to read 6, iclass 28, count 2 2006.280.08:01:30.96#ibcon#read 6, iclass 28, count 2 2006.280.08:01:30.96#ibcon#end of sib2, iclass 28, count 2 2006.280.08:01:30.96#ibcon#*after write, iclass 28, count 2 2006.280.08:01:30.96#ibcon#*before return 0, iclass 28, count 2 2006.280.08:01:30.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:30.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:01:30.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:01:30.96#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:30.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:31.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:31.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:31.08#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:01:31.08#ibcon#first serial, iclass 28, count 0 2006.280.08:01:31.08#ibcon#enter sib2, iclass 28, count 0 2006.280.08:01:31.08#ibcon#flushed, iclass 28, count 0 2006.280.08:01:31.08#ibcon#about to write, iclass 28, count 0 2006.280.08:01:31.08#ibcon#wrote, iclass 28, count 0 2006.280.08:01:31.08#ibcon#about to read 3, iclass 28, count 0 2006.280.08:01:31.10#ibcon#read 3, iclass 28, count 0 2006.280.08:01:31.10#ibcon#about to read 4, iclass 28, count 0 2006.280.08:01:31.10#ibcon#read 4, iclass 28, count 0 2006.280.08:01:31.10#ibcon#about to read 5, iclass 28, count 0 2006.280.08:01:31.10#ibcon#read 5, iclass 28, count 0 2006.280.08:01:31.10#ibcon#about to read 6, iclass 28, count 0 2006.280.08:01:31.10#ibcon#read 6, iclass 28, count 0 2006.280.08:01:31.10#ibcon#end of sib2, iclass 28, count 0 2006.280.08:01:31.10#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:01:31.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:01:31.10#ibcon#[27=USB\r\n] 2006.280.08:01:31.10#ibcon#*before write, iclass 28, count 0 2006.280.08:01:31.10#ibcon#enter sib2, iclass 28, count 0 2006.280.08:01:31.10#ibcon#flushed, iclass 28, count 0 2006.280.08:01:31.10#ibcon#about to write, iclass 28, count 0 2006.280.08:01:31.10#ibcon#wrote, iclass 28, count 0 2006.280.08:01:31.10#ibcon#about to read 3, iclass 28, count 0 2006.280.08:01:31.13#ibcon#read 3, iclass 28, count 0 2006.280.08:01:31.13#ibcon#about to read 4, iclass 28, count 0 2006.280.08:01:31.13#ibcon#read 4, iclass 28, count 0 2006.280.08:01:31.13#ibcon#about to read 5, iclass 28, count 0 2006.280.08:01:31.13#ibcon#read 5, iclass 28, count 0 2006.280.08:01:31.13#ibcon#about to read 6, iclass 28, count 0 2006.280.08:01:31.13#ibcon#read 6, iclass 28, count 0 2006.280.08:01:31.13#ibcon#end of sib2, iclass 28, count 0 2006.280.08:01:31.13#ibcon#*after write, iclass 28, count 0 2006.280.08:01:31.13#ibcon#*before return 0, iclass 28, count 0 2006.280.08:01:31.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:31.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:01:31.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:01:31.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:01:31.13$vc4f8/vblo=4,712.99 2006.280.08:01:31.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:01:31.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:01:31.13#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:31.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:31.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:31.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:31.13#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:01:31.13#ibcon#first serial, iclass 30, count 0 2006.280.08:01:31.13#ibcon#enter sib2, iclass 30, count 0 2006.280.08:01:31.13#ibcon#flushed, iclass 30, count 0 2006.280.08:01:31.13#ibcon#about to write, iclass 30, count 0 2006.280.08:01:31.13#ibcon#wrote, iclass 30, count 0 2006.280.08:01:31.13#ibcon#about to read 3, iclass 30, count 0 2006.280.08:01:31.15#ibcon#read 3, iclass 30, count 0 2006.280.08:01:31.15#ibcon#about to read 4, iclass 30, count 0 2006.280.08:01:31.15#ibcon#read 4, iclass 30, count 0 2006.280.08:01:31.15#ibcon#about to read 5, iclass 30, count 0 2006.280.08:01:31.15#ibcon#read 5, iclass 30, count 0 2006.280.08:01:31.15#ibcon#about to read 6, iclass 30, count 0 2006.280.08:01:31.15#ibcon#read 6, iclass 30, count 0 2006.280.08:01:31.15#ibcon#end of sib2, iclass 30, count 0 2006.280.08:01:31.15#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:01:31.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:01:31.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:01:31.15#ibcon#*before write, iclass 30, count 0 2006.280.08:01:31.15#ibcon#enter sib2, iclass 30, count 0 2006.280.08:01:31.15#ibcon#flushed, iclass 30, count 0 2006.280.08:01:31.15#ibcon#about to write, iclass 30, count 0 2006.280.08:01:31.15#ibcon#wrote, iclass 30, count 0 2006.280.08:01:31.15#ibcon#about to read 3, iclass 30, count 0 2006.280.08:01:31.19#ibcon#read 3, iclass 30, count 0 2006.280.08:01:31.19#ibcon#about to read 4, iclass 30, count 0 2006.280.08:01:31.19#ibcon#read 4, iclass 30, count 0 2006.280.08:01:31.19#ibcon#about to read 5, iclass 30, count 0 2006.280.08:01:31.19#ibcon#read 5, iclass 30, count 0 2006.280.08:01:31.19#ibcon#about to read 6, iclass 30, count 0 2006.280.08:01:31.19#ibcon#read 6, iclass 30, count 0 2006.280.08:01:31.19#ibcon#end of sib2, iclass 30, count 0 2006.280.08:01:31.19#ibcon#*after write, iclass 30, count 0 2006.280.08:01:31.19#ibcon#*before return 0, iclass 30, count 0 2006.280.08:01:31.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:31.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:01:31.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:01:31.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:01:31.19$vc4f8/vb=4,4 2006.280.08:01:31.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:01:31.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:01:31.20#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:31.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:31.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:31.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:31.25#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:01:31.25#ibcon#first serial, iclass 32, count 2 2006.280.08:01:31.25#ibcon#enter sib2, iclass 32, count 2 2006.280.08:01:31.25#ibcon#flushed, iclass 32, count 2 2006.280.08:01:31.25#ibcon#about to write, iclass 32, count 2 2006.280.08:01:31.25#ibcon#wrote, iclass 32, count 2 2006.280.08:01:31.25#ibcon#about to read 3, iclass 32, count 2 2006.280.08:01:31.27#ibcon#read 3, iclass 32, count 2 2006.280.08:01:31.27#ibcon#about to read 4, iclass 32, count 2 2006.280.08:01:31.27#ibcon#read 4, iclass 32, count 2 2006.280.08:01:31.27#ibcon#about to read 5, iclass 32, count 2 2006.280.08:01:31.27#ibcon#read 5, iclass 32, count 2 2006.280.08:01:31.27#ibcon#about to read 6, iclass 32, count 2 2006.280.08:01:31.27#ibcon#read 6, iclass 32, count 2 2006.280.08:01:31.27#ibcon#end of sib2, iclass 32, count 2 2006.280.08:01:31.27#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:01:31.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:01:31.27#ibcon#[27=AT04-04\r\n] 2006.280.08:01:31.27#ibcon#*before write, iclass 32, count 2 2006.280.08:01:31.27#ibcon#enter sib2, iclass 32, count 2 2006.280.08:01:31.27#ibcon#flushed, iclass 32, count 2 2006.280.08:01:31.27#ibcon#about to write, iclass 32, count 2 2006.280.08:01:31.27#ibcon#wrote, iclass 32, count 2 2006.280.08:01:31.27#ibcon#about to read 3, iclass 32, count 2 2006.280.08:01:31.30#ibcon#read 3, iclass 32, count 2 2006.280.08:01:31.30#ibcon#about to read 4, iclass 32, count 2 2006.280.08:01:31.30#ibcon#read 4, iclass 32, count 2 2006.280.08:01:31.30#ibcon#about to read 5, iclass 32, count 2 2006.280.08:01:31.30#ibcon#read 5, iclass 32, count 2 2006.280.08:01:31.30#ibcon#about to read 6, iclass 32, count 2 2006.280.08:01:31.30#ibcon#read 6, iclass 32, count 2 2006.280.08:01:31.30#ibcon#end of sib2, iclass 32, count 2 2006.280.08:01:31.30#ibcon#*after write, iclass 32, count 2 2006.280.08:01:31.30#ibcon#*before return 0, iclass 32, count 2 2006.280.08:01:31.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:31.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:01:31.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:01:31.30#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:31.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:31.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:31.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:31.42#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:01:31.42#ibcon#first serial, iclass 32, count 0 2006.280.08:01:31.42#ibcon#enter sib2, iclass 32, count 0 2006.280.08:01:31.42#ibcon#flushed, iclass 32, count 0 2006.280.08:01:31.42#ibcon#about to write, iclass 32, count 0 2006.280.08:01:31.42#ibcon#wrote, iclass 32, count 0 2006.280.08:01:31.42#ibcon#about to read 3, iclass 32, count 0 2006.280.08:01:31.44#ibcon#read 3, iclass 32, count 0 2006.280.08:01:31.44#ibcon#about to read 4, iclass 32, count 0 2006.280.08:01:31.44#ibcon#read 4, iclass 32, count 0 2006.280.08:01:31.44#ibcon#about to read 5, iclass 32, count 0 2006.280.08:01:31.44#ibcon#read 5, iclass 32, count 0 2006.280.08:01:31.44#ibcon#about to read 6, iclass 32, count 0 2006.280.08:01:31.44#ibcon#read 6, iclass 32, count 0 2006.280.08:01:31.44#ibcon#end of sib2, iclass 32, count 0 2006.280.08:01:31.44#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:01:31.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:01:31.44#ibcon#[27=USB\r\n] 2006.280.08:01:31.44#ibcon#*before write, iclass 32, count 0 2006.280.08:01:31.44#ibcon#enter sib2, iclass 32, count 0 2006.280.08:01:31.44#ibcon#flushed, iclass 32, count 0 2006.280.08:01:31.44#ibcon#about to write, iclass 32, count 0 2006.280.08:01:31.44#ibcon#wrote, iclass 32, count 0 2006.280.08:01:31.44#ibcon#about to read 3, iclass 32, count 0 2006.280.08:01:31.47#ibcon#read 3, iclass 32, count 0 2006.280.08:01:31.47#ibcon#about to read 4, iclass 32, count 0 2006.280.08:01:31.47#ibcon#read 4, iclass 32, count 0 2006.280.08:01:31.47#ibcon#about to read 5, iclass 32, count 0 2006.280.08:01:31.47#ibcon#read 5, iclass 32, count 0 2006.280.08:01:31.47#ibcon#about to read 6, iclass 32, count 0 2006.280.08:01:31.47#ibcon#read 6, iclass 32, count 0 2006.280.08:01:31.47#ibcon#end of sib2, iclass 32, count 0 2006.280.08:01:31.47#ibcon#*after write, iclass 32, count 0 2006.280.08:01:31.47#ibcon#*before return 0, iclass 32, count 0 2006.280.08:01:31.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:31.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:01:31.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:01:31.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:01:31.47$vc4f8/vblo=5,744.99 2006.280.08:01:31.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:01:31.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:01:31.47#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:31.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:31.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:31.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:31.47#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:01:31.47#ibcon#first serial, iclass 34, count 0 2006.280.08:01:31.47#ibcon#enter sib2, iclass 34, count 0 2006.280.08:01:31.47#ibcon#flushed, iclass 34, count 0 2006.280.08:01:31.47#ibcon#about to write, iclass 34, count 0 2006.280.08:01:31.47#ibcon#wrote, iclass 34, count 0 2006.280.08:01:31.47#ibcon#about to read 3, iclass 34, count 0 2006.280.08:01:31.49#ibcon#read 3, iclass 34, count 0 2006.280.08:01:31.49#ibcon#about to read 4, iclass 34, count 0 2006.280.08:01:31.49#ibcon#read 4, iclass 34, count 0 2006.280.08:01:31.49#ibcon#about to read 5, iclass 34, count 0 2006.280.08:01:31.49#ibcon#read 5, iclass 34, count 0 2006.280.08:01:31.49#ibcon#about to read 6, iclass 34, count 0 2006.280.08:01:31.49#ibcon#read 6, iclass 34, count 0 2006.280.08:01:31.49#ibcon#end of sib2, iclass 34, count 0 2006.280.08:01:31.49#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:01:31.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:01:31.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:01:31.49#ibcon#*before write, iclass 34, count 0 2006.280.08:01:31.49#ibcon#enter sib2, iclass 34, count 0 2006.280.08:01:31.49#ibcon#flushed, iclass 34, count 0 2006.280.08:01:31.49#ibcon#about to write, iclass 34, count 0 2006.280.08:01:31.49#ibcon#wrote, iclass 34, count 0 2006.280.08:01:31.49#ibcon#about to read 3, iclass 34, count 0 2006.280.08:01:31.53#ibcon#read 3, iclass 34, count 0 2006.280.08:01:31.53#ibcon#about to read 4, iclass 34, count 0 2006.280.08:01:31.53#ibcon#read 4, iclass 34, count 0 2006.280.08:01:31.53#ibcon#about to read 5, iclass 34, count 0 2006.280.08:01:31.53#ibcon#read 5, iclass 34, count 0 2006.280.08:01:31.53#ibcon#about to read 6, iclass 34, count 0 2006.280.08:01:31.53#ibcon#read 6, iclass 34, count 0 2006.280.08:01:31.53#ibcon#end of sib2, iclass 34, count 0 2006.280.08:01:31.53#ibcon#*after write, iclass 34, count 0 2006.280.08:01:31.53#ibcon#*before return 0, iclass 34, count 0 2006.280.08:01:31.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:31.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:01:31.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:01:31.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:01:31.53$vc4f8/vb=5,4 2006.280.08:01:31.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:01:31.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:01:31.53#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:31.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:31.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:31.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:31.59#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:01:31.59#ibcon#first serial, iclass 36, count 2 2006.280.08:01:31.59#ibcon#enter sib2, iclass 36, count 2 2006.280.08:01:31.59#ibcon#flushed, iclass 36, count 2 2006.280.08:01:31.59#ibcon#about to write, iclass 36, count 2 2006.280.08:01:31.59#ibcon#wrote, iclass 36, count 2 2006.280.08:01:31.59#ibcon#about to read 3, iclass 36, count 2 2006.280.08:01:31.61#ibcon#read 3, iclass 36, count 2 2006.280.08:01:31.61#ibcon#about to read 4, iclass 36, count 2 2006.280.08:01:31.61#ibcon#read 4, iclass 36, count 2 2006.280.08:01:31.61#ibcon#about to read 5, iclass 36, count 2 2006.280.08:01:31.61#ibcon#read 5, iclass 36, count 2 2006.280.08:01:31.61#ibcon#about to read 6, iclass 36, count 2 2006.280.08:01:31.61#ibcon#read 6, iclass 36, count 2 2006.280.08:01:31.61#ibcon#end of sib2, iclass 36, count 2 2006.280.08:01:31.61#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:01:31.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:01:31.61#ibcon#[27=AT05-04\r\n] 2006.280.08:01:31.61#ibcon#*before write, iclass 36, count 2 2006.280.08:01:31.61#ibcon#enter sib2, iclass 36, count 2 2006.280.08:01:31.61#ibcon#flushed, iclass 36, count 2 2006.280.08:01:31.61#ibcon#about to write, iclass 36, count 2 2006.280.08:01:31.61#ibcon#wrote, iclass 36, count 2 2006.280.08:01:31.61#ibcon#about to read 3, iclass 36, count 2 2006.280.08:01:31.64#ibcon#read 3, iclass 36, count 2 2006.280.08:01:31.64#ibcon#about to read 4, iclass 36, count 2 2006.280.08:01:31.64#ibcon#read 4, iclass 36, count 2 2006.280.08:01:31.64#ibcon#about to read 5, iclass 36, count 2 2006.280.08:01:31.64#ibcon#read 5, iclass 36, count 2 2006.280.08:01:31.64#ibcon#about to read 6, iclass 36, count 2 2006.280.08:01:31.64#ibcon#read 6, iclass 36, count 2 2006.280.08:01:31.64#ibcon#end of sib2, iclass 36, count 2 2006.280.08:01:31.64#ibcon#*after write, iclass 36, count 2 2006.280.08:01:31.64#ibcon#*before return 0, iclass 36, count 2 2006.280.08:01:31.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:31.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:01:31.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:01:31.64#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:31.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:31.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:31.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:31.76#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:01:31.76#ibcon#first serial, iclass 36, count 0 2006.280.08:01:31.76#ibcon#enter sib2, iclass 36, count 0 2006.280.08:01:31.76#ibcon#flushed, iclass 36, count 0 2006.280.08:01:31.76#ibcon#about to write, iclass 36, count 0 2006.280.08:01:31.76#ibcon#wrote, iclass 36, count 0 2006.280.08:01:31.76#ibcon#about to read 3, iclass 36, count 0 2006.280.08:01:31.78#ibcon#read 3, iclass 36, count 0 2006.280.08:01:31.78#ibcon#about to read 4, iclass 36, count 0 2006.280.08:01:31.78#ibcon#read 4, iclass 36, count 0 2006.280.08:01:31.78#ibcon#about to read 5, iclass 36, count 0 2006.280.08:01:31.78#ibcon#read 5, iclass 36, count 0 2006.280.08:01:31.78#ibcon#about to read 6, iclass 36, count 0 2006.280.08:01:31.78#ibcon#read 6, iclass 36, count 0 2006.280.08:01:31.78#ibcon#end of sib2, iclass 36, count 0 2006.280.08:01:31.78#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:01:31.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:01:31.78#ibcon#[27=USB\r\n] 2006.280.08:01:31.78#ibcon#*before write, iclass 36, count 0 2006.280.08:01:31.78#ibcon#enter sib2, iclass 36, count 0 2006.280.08:01:31.78#ibcon#flushed, iclass 36, count 0 2006.280.08:01:31.78#ibcon#about to write, iclass 36, count 0 2006.280.08:01:31.78#ibcon#wrote, iclass 36, count 0 2006.280.08:01:31.78#ibcon#about to read 3, iclass 36, count 0 2006.280.08:01:31.81#ibcon#read 3, iclass 36, count 0 2006.280.08:01:31.81#ibcon#about to read 4, iclass 36, count 0 2006.280.08:01:31.81#ibcon#read 4, iclass 36, count 0 2006.280.08:01:31.81#ibcon#about to read 5, iclass 36, count 0 2006.280.08:01:31.81#ibcon#read 5, iclass 36, count 0 2006.280.08:01:31.81#ibcon#about to read 6, iclass 36, count 0 2006.280.08:01:31.81#ibcon#read 6, iclass 36, count 0 2006.280.08:01:31.81#ibcon#end of sib2, iclass 36, count 0 2006.280.08:01:31.81#ibcon#*after write, iclass 36, count 0 2006.280.08:01:31.81#ibcon#*before return 0, iclass 36, count 0 2006.280.08:01:31.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:31.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:01:31.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:01:31.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:01:31.81$vc4f8/vblo=6,752.99 2006.280.08:01:31.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:01:31.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:01:31.81#ibcon#ireg 17 cls_cnt 0 2006.280.08:01:31.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:31.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:31.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:31.81#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:01:31.81#ibcon#first serial, iclass 38, count 0 2006.280.08:01:31.81#ibcon#enter sib2, iclass 38, count 0 2006.280.08:01:31.81#ibcon#flushed, iclass 38, count 0 2006.280.08:01:31.81#ibcon#about to write, iclass 38, count 0 2006.280.08:01:31.81#ibcon#wrote, iclass 38, count 0 2006.280.08:01:31.81#ibcon#about to read 3, iclass 38, count 0 2006.280.08:01:31.83#ibcon#read 3, iclass 38, count 0 2006.280.08:01:31.83#ibcon#about to read 4, iclass 38, count 0 2006.280.08:01:31.83#ibcon#read 4, iclass 38, count 0 2006.280.08:01:31.83#ibcon#about to read 5, iclass 38, count 0 2006.280.08:01:31.83#ibcon#read 5, iclass 38, count 0 2006.280.08:01:31.83#ibcon#about to read 6, iclass 38, count 0 2006.280.08:01:31.83#ibcon#read 6, iclass 38, count 0 2006.280.08:01:31.83#ibcon#end of sib2, iclass 38, count 0 2006.280.08:01:31.83#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:01:31.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:01:31.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:01:31.83#ibcon#*before write, iclass 38, count 0 2006.280.08:01:31.83#ibcon#enter sib2, iclass 38, count 0 2006.280.08:01:31.83#ibcon#flushed, iclass 38, count 0 2006.280.08:01:31.83#ibcon#about to write, iclass 38, count 0 2006.280.08:01:31.83#ibcon#wrote, iclass 38, count 0 2006.280.08:01:31.83#ibcon#about to read 3, iclass 38, count 0 2006.280.08:01:31.87#ibcon#read 3, iclass 38, count 0 2006.280.08:01:31.87#ibcon#about to read 4, iclass 38, count 0 2006.280.08:01:31.87#ibcon#read 4, iclass 38, count 0 2006.280.08:01:31.87#ibcon#about to read 5, iclass 38, count 0 2006.280.08:01:31.87#ibcon#read 5, iclass 38, count 0 2006.280.08:01:31.87#ibcon#about to read 6, iclass 38, count 0 2006.280.08:01:31.87#ibcon#read 6, iclass 38, count 0 2006.280.08:01:31.87#ibcon#end of sib2, iclass 38, count 0 2006.280.08:01:31.87#ibcon#*after write, iclass 38, count 0 2006.280.08:01:31.87#ibcon#*before return 0, iclass 38, count 0 2006.280.08:01:31.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:31.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:01:31.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:01:31.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:01:31.87$vc4f8/vb=6,4 2006.280.08:01:31.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:01:31.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:01:31.87#ibcon#ireg 11 cls_cnt 2 2006.280.08:01:31.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:31.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:31.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:31.93#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:01:31.93#ibcon#first serial, iclass 40, count 2 2006.280.08:01:31.93#ibcon#enter sib2, iclass 40, count 2 2006.280.08:01:31.93#ibcon#flushed, iclass 40, count 2 2006.280.08:01:31.93#ibcon#about to write, iclass 40, count 2 2006.280.08:01:31.93#ibcon#wrote, iclass 40, count 2 2006.280.08:01:31.93#ibcon#about to read 3, iclass 40, count 2 2006.280.08:01:31.95#ibcon#read 3, iclass 40, count 2 2006.280.08:01:31.95#ibcon#about to read 4, iclass 40, count 2 2006.280.08:01:31.95#ibcon#read 4, iclass 40, count 2 2006.280.08:01:31.95#ibcon#about to read 5, iclass 40, count 2 2006.280.08:01:31.95#ibcon#read 5, iclass 40, count 2 2006.280.08:01:31.95#ibcon#about to read 6, iclass 40, count 2 2006.280.08:01:31.95#ibcon#read 6, iclass 40, count 2 2006.280.08:01:31.95#ibcon#end of sib2, iclass 40, count 2 2006.280.08:01:31.95#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:01:31.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:01:31.95#ibcon#[27=AT06-04\r\n] 2006.280.08:01:31.95#ibcon#*before write, iclass 40, count 2 2006.280.08:01:31.95#ibcon#enter sib2, iclass 40, count 2 2006.280.08:01:31.95#ibcon#flushed, iclass 40, count 2 2006.280.08:01:31.95#ibcon#about to write, iclass 40, count 2 2006.280.08:01:31.95#ibcon#wrote, iclass 40, count 2 2006.280.08:01:31.95#ibcon#about to read 3, iclass 40, count 2 2006.280.08:01:31.98#ibcon#read 3, iclass 40, count 2 2006.280.08:01:31.98#ibcon#about to read 4, iclass 40, count 2 2006.280.08:01:31.98#ibcon#read 4, iclass 40, count 2 2006.280.08:01:31.98#ibcon#about to read 5, iclass 40, count 2 2006.280.08:01:31.98#ibcon#read 5, iclass 40, count 2 2006.280.08:01:31.98#ibcon#about to read 6, iclass 40, count 2 2006.280.08:01:31.98#ibcon#read 6, iclass 40, count 2 2006.280.08:01:31.98#ibcon#end of sib2, iclass 40, count 2 2006.280.08:01:31.98#ibcon#*after write, iclass 40, count 2 2006.280.08:01:31.98#ibcon#*before return 0, iclass 40, count 2 2006.280.08:01:31.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:31.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:01:31.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:01:31.98#ibcon#ireg 7 cls_cnt 0 2006.280.08:01:31.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:32.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:32.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:32.10#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:01:32.10#ibcon#first serial, iclass 40, count 0 2006.280.08:01:32.10#ibcon#enter sib2, iclass 40, count 0 2006.280.08:01:32.10#ibcon#flushed, iclass 40, count 0 2006.280.08:01:32.10#ibcon#about to write, iclass 40, count 0 2006.280.08:01:32.10#ibcon#wrote, iclass 40, count 0 2006.280.08:01:32.10#ibcon#about to read 3, iclass 40, count 0 2006.280.08:01:32.12#ibcon#read 3, iclass 40, count 0 2006.280.08:01:32.12#ibcon#about to read 4, iclass 40, count 0 2006.280.08:01:32.12#ibcon#read 4, iclass 40, count 0 2006.280.08:01:32.12#ibcon#about to read 5, iclass 40, count 0 2006.280.08:01:32.12#ibcon#read 5, iclass 40, count 0 2006.280.08:01:32.12#ibcon#about to read 6, iclass 40, count 0 2006.280.08:01:32.12#ibcon#read 6, iclass 40, count 0 2006.280.08:01:32.12#ibcon#end of sib2, iclass 40, count 0 2006.280.08:01:32.12#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:01:32.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:01:32.12#ibcon#[27=USB\r\n] 2006.280.08:01:32.12#ibcon#*before write, iclass 40, count 0 2006.280.08:01:32.12#ibcon#enter sib2, iclass 40, count 0 2006.280.08:01:32.12#ibcon#flushed, iclass 40, count 0 2006.280.08:01:32.12#ibcon#about to write, iclass 40, count 0 2006.280.08:01:32.12#ibcon#wrote, iclass 40, count 0 2006.280.08:01:32.12#ibcon#about to read 3, iclass 40, count 0 2006.280.08:01:32.15#ibcon#read 3, iclass 40, count 0 2006.280.08:01:32.15#ibcon#about to read 4, iclass 40, count 0 2006.280.08:01:32.15#ibcon#read 4, iclass 40, count 0 2006.280.08:01:32.15#ibcon#about to read 5, iclass 40, count 0 2006.280.08:01:32.15#ibcon#read 5, iclass 40, count 0 2006.280.08:01:32.15#ibcon#about to read 6, iclass 40, count 0 2006.280.08:01:32.15#ibcon#read 6, iclass 40, count 0 2006.280.08:01:32.15#ibcon#end of sib2, iclass 40, count 0 2006.280.08:01:32.15#ibcon#*after write, iclass 40, count 0 2006.280.08:01:32.15#ibcon#*before return 0, iclass 40, count 0 2006.280.08:01:32.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:32.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:01:32.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:01:32.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:01:32.15$vc4f8/vabw=wide 2006.280.08:01:32.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:01:32.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:01:32.15#ibcon#ireg 8 cls_cnt 0 2006.280.08:01:32.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:32.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:32.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:32.15#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:01:32.15#ibcon#first serial, iclass 4, count 0 2006.280.08:01:32.15#ibcon#enter sib2, iclass 4, count 0 2006.280.08:01:32.15#ibcon#flushed, iclass 4, count 0 2006.280.08:01:32.15#ibcon#about to write, iclass 4, count 0 2006.280.08:01:32.15#ibcon#wrote, iclass 4, count 0 2006.280.08:01:32.15#ibcon#about to read 3, iclass 4, count 0 2006.280.08:01:32.17#ibcon#read 3, iclass 4, count 0 2006.280.08:01:32.17#ibcon#about to read 4, iclass 4, count 0 2006.280.08:01:32.17#ibcon#read 4, iclass 4, count 0 2006.280.08:01:32.17#ibcon#about to read 5, iclass 4, count 0 2006.280.08:01:32.17#ibcon#read 5, iclass 4, count 0 2006.280.08:01:32.17#ibcon#about to read 6, iclass 4, count 0 2006.280.08:01:32.17#ibcon#read 6, iclass 4, count 0 2006.280.08:01:32.17#ibcon#end of sib2, iclass 4, count 0 2006.280.08:01:32.17#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:01:32.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:01:32.17#ibcon#[25=BW32\r\n] 2006.280.08:01:32.17#ibcon#*before write, iclass 4, count 0 2006.280.08:01:32.17#ibcon#enter sib2, iclass 4, count 0 2006.280.08:01:32.17#ibcon#flushed, iclass 4, count 0 2006.280.08:01:32.17#ibcon#about to write, iclass 4, count 0 2006.280.08:01:32.17#ibcon#wrote, iclass 4, count 0 2006.280.08:01:32.17#ibcon#about to read 3, iclass 4, count 0 2006.280.08:01:32.20#ibcon#read 3, iclass 4, count 0 2006.280.08:01:32.20#ibcon#about to read 4, iclass 4, count 0 2006.280.08:01:32.20#ibcon#read 4, iclass 4, count 0 2006.280.08:01:32.20#ibcon#about to read 5, iclass 4, count 0 2006.280.08:01:32.20#ibcon#read 5, iclass 4, count 0 2006.280.08:01:32.20#ibcon#about to read 6, iclass 4, count 0 2006.280.08:01:32.20#ibcon#read 6, iclass 4, count 0 2006.280.08:01:32.20#ibcon#end of sib2, iclass 4, count 0 2006.280.08:01:32.20#ibcon#*after write, iclass 4, count 0 2006.280.08:01:32.20#ibcon#*before return 0, iclass 4, count 0 2006.280.08:01:32.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:32.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:01:32.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:01:32.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:01:32.20$vc4f8/vbbw=wide 2006.280.08:01:32.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:01:32.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:01:32.20#ibcon#ireg 8 cls_cnt 0 2006.280.08:01:32.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:01:32.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:01:32.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:01:32.27#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:01:32.27#ibcon#first serial, iclass 6, count 0 2006.280.08:01:32.27#ibcon#enter sib2, iclass 6, count 0 2006.280.08:01:32.27#ibcon#flushed, iclass 6, count 0 2006.280.08:01:32.27#ibcon#about to write, iclass 6, count 0 2006.280.08:01:32.27#ibcon#wrote, iclass 6, count 0 2006.280.08:01:32.27#ibcon#about to read 3, iclass 6, count 0 2006.280.08:01:32.29#ibcon#read 3, iclass 6, count 0 2006.280.08:01:32.29#ibcon#about to read 4, iclass 6, count 0 2006.280.08:01:32.29#ibcon#read 4, iclass 6, count 0 2006.280.08:01:32.29#ibcon#about to read 5, iclass 6, count 0 2006.280.08:01:32.29#ibcon#read 5, iclass 6, count 0 2006.280.08:01:32.29#ibcon#about to read 6, iclass 6, count 0 2006.280.08:01:32.29#ibcon#read 6, iclass 6, count 0 2006.280.08:01:32.29#ibcon#end of sib2, iclass 6, count 0 2006.280.08:01:32.29#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:01:32.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:01:32.29#ibcon#[27=BW32\r\n] 2006.280.08:01:32.29#ibcon#*before write, iclass 6, count 0 2006.280.08:01:32.29#ibcon#enter sib2, iclass 6, count 0 2006.280.08:01:32.29#ibcon#flushed, iclass 6, count 0 2006.280.08:01:32.29#ibcon#about to write, iclass 6, count 0 2006.280.08:01:32.29#ibcon#wrote, iclass 6, count 0 2006.280.08:01:32.29#ibcon#about to read 3, iclass 6, count 0 2006.280.08:01:32.32#ibcon#read 3, iclass 6, count 0 2006.280.08:01:32.32#ibcon#about to read 4, iclass 6, count 0 2006.280.08:01:32.32#ibcon#read 4, iclass 6, count 0 2006.280.08:01:32.32#ibcon#about to read 5, iclass 6, count 0 2006.280.08:01:32.32#ibcon#read 5, iclass 6, count 0 2006.280.08:01:32.32#ibcon#about to read 6, iclass 6, count 0 2006.280.08:01:32.32#ibcon#read 6, iclass 6, count 0 2006.280.08:01:32.32#ibcon#end of sib2, iclass 6, count 0 2006.280.08:01:32.32#ibcon#*after write, iclass 6, count 0 2006.280.08:01:32.32#ibcon#*before return 0, iclass 6, count 0 2006.280.08:01:32.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:01:32.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:01:32.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:01:32.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:01:32.33$4f8m12a/ifd4f 2006.280.08:01:32.33$ifd4f/lo= 2006.280.08:01:32.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:01:32.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:01:32.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:01:32.33$ifd4f/patch= 2006.280.08:01:32.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:01:32.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:01:32.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:01:32.34$4f8m12a/"form=m,16.000,1:2 2006.280.08:01:32.34$4f8m12a/"tpicd 2006.280.08:01:32.34$4f8m12a/echo=off 2006.280.08:01:32.34$4f8m12a/xlog=off 2006.280.08:01:32.34:!2006.280.08:01:50 2006.280.08:01:33.13#trakl#Source acquired 2006.280.08:01:35.13#flagr#flagr/antenna,acquired 2006.280.08:01:50.01:preob 2006.280.08:01:51.14/onsource/TRACKING 2006.280.08:01:51.14:!2006.280.08:02:00 2006.280.08:02:00.00:data_valid=on 2006.280.08:02:00.00:midob 2006.280.08:02:00.14/onsource/TRACKING 2006.280.08:02:00.14/wx/20.89,987.2,62 2006.280.08:02:00.36/cable/+6.4833E-03 2006.280.08:02:01.45/va/01,07,usb,yes,35,37 2006.280.08:02:01.45/va/02,06,usb,yes,32,34 2006.280.08:02:01.45/va/03,06,usb,yes,31,31 2006.280.08:02:01.45/va/04,06,usb,yes,34,36 2006.280.08:02:01.45/va/05,07,usb,yes,31,33 2006.280.08:02:01.45/va/06,06,usb,yes,30,30 2006.280.08:02:01.45/va/07,06,usb,yes,31,31 2006.280.08:02:01.45/va/08,06,usb,yes,33,33 2006.280.08:02:01.68/valo/01,532.99,yes,locked 2006.280.08:02:01.68/valo/02,572.99,yes,locked 2006.280.08:02:01.68/valo/03,672.99,yes,locked 2006.280.08:02:01.68/valo/04,832.99,yes,locked 2006.280.08:02:01.68/valo/05,652.99,yes,locked 2006.280.08:02:01.68/valo/06,772.99,yes,locked 2006.280.08:02:01.68/valo/07,832.99,yes,locked 2006.280.08:02:01.68/valo/08,852.99,yes,locked 2006.280.08:02:02.77/vb/01,04,usb,yes,31,30 2006.280.08:02:02.77/vb/02,05,usb,yes,29,30 2006.280.08:02:02.77/vb/03,04,usb,yes,29,33 2006.280.08:02:02.77/vb/04,04,usb,yes,30,30 2006.280.08:02:02.77/vb/05,04,usb,yes,28,32 2006.280.08:02:02.77/vb/06,04,usb,yes,29,32 2006.280.08:02:02.77/vb/07,04,usb,yes,32,31 2006.280.08:02:02.77/vb/08,04,usb,yes,29,32 2006.280.08:02:03.00/vblo/01,632.99,yes,locked 2006.280.08:02:03.00/vblo/02,640.99,yes,locked 2006.280.08:02:03.00/vblo/03,656.99,yes,locked 2006.280.08:02:03.00/vblo/04,712.99,yes,locked 2006.280.08:02:03.00/vblo/05,744.99,yes,locked 2006.280.08:02:03.00/vblo/06,752.99,yes,locked 2006.280.08:02:03.00/vblo/07,734.99,yes,locked 2006.280.08:02:03.00/vblo/08,744.99,yes,locked 2006.280.08:02:03.15/vabw/8 2006.280.08:02:03.30/vbbw/8 2006.280.08:02:03.39/xfe/off,on,12.2 2006.280.08:02:03.77/ifatt/23,28,28,28 2006.280.08:02:04.07/fmout-gps/S +3.22E-07 2006.280.08:02:04.09:!2006.280.08:03:00 2006.280.08:03:00.01:data_valid=off 2006.280.08:03:00.01:postob 2006.280.08:03:00.23/cable/+6.4844E-03 2006.280.08:03:00.23/wx/20.85,987.2,62 2006.280.08:03:01.07/fmout-gps/S +3.23E-07 2006.280.08:03:01.07:scan_name=280-0803,k06280,60 2006.280.08:03:01.07:source=1538+149,154049.49,144745.9,2000.0,ccw 2006.280.08:03:01.14#flagr#flagr/antenna,new-source 2006.280.08:03:02.14:checkk5 2006.280.08:03:03.29/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:03:03.73/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:03:04.44/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:03:05.14/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:03:05.78/chk_obsdata//k5ts1/T2800802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:03:06.27/chk_obsdata//k5ts2/T2800802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:03:07.08/chk_obsdata//k5ts3/T2800802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:03:07.68/chk_obsdata//k5ts4/T2800802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:03:08.95/k5log//k5ts1_log_newline 2006.280.08:03:10.15/k5log//k5ts2_log_newline 2006.280.08:03:11.36/k5log//k5ts3_log_newline 2006.280.08:03:12.32/k5log//k5ts4_log_newline 2006.280.08:03:12.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:03:12.34:4f8m12a=2 2006.280.08:03:12.34$4f8m12a/echo=on 2006.280.08:03:12.34$4f8m12a/pcalon 2006.280.08:03:12.34$pcalon/"no phase cal control is implemented here 2006.280.08:03:12.34$4f8m12a/"tpicd=stop 2006.280.08:03:12.34$4f8m12a/vc4f8 2006.280.08:03:12.34$vc4f8/valo=1,532.99 2006.280.08:03:12.35#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:03:12.35#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:03:12.35#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:12.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:12.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:12.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:12.35#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:03:12.35#ibcon#first serial, iclass 15, count 0 2006.280.08:03:12.35#ibcon#enter sib2, iclass 15, count 0 2006.280.08:03:12.35#ibcon#flushed, iclass 15, count 0 2006.280.08:03:12.35#ibcon#about to write, iclass 15, count 0 2006.280.08:03:12.35#ibcon#wrote, iclass 15, count 0 2006.280.08:03:12.35#ibcon#about to read 3, iclass 15, count 0 2006.280.08:03:12.37#ibcon#read 3, iclass 15, count 0 2006.280.08:03:12.37#ibcon#about to read 4, iclass 15, count 0 2006.280.08:03:12.37#ibcon#read 4, iclass 15, count 0 2006.280.08:03:12.37#ibcon#about to read 5, iclass 15, count 0 2006.280.08:03:12.37#ibcon#read 5, iclass 15, count 0 2006.280.08:03:12.37#ibcon#about to read 6, iclass 15, count 0 2006.280.08:03:12.37#ibcon#read 6, iclass 15, count 0 2006.280.08:03:12.37#ibcon#end of sib2, iclass 15, count 0 2006.280.08:03:12.37#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:03:12.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:03:12.37#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:03:12.37#ibcon#*before write, iclass 15, count 0 2006.280.08:03:12.37#ibcon#enter sib2, iclass 15, count 0 2006.280.08:03:12.37#ibcon#flushed, iclass 15, count 0 2006.280.08:03:12.37#ibcon#about to write, iclass 15, count 0 2006.280.08:03:12.37#ibcon#wrote, iclass 15, count 0 2006.280.08:03:12.37#ibcon#about to read 3, iclass 15, count 0 2006.280.08:03:12.42#ibcon#read 3, iclass 15, count 0 2006.280.08:03:12.42#ibcon#about to read 4, iclass 15, count 0 2006.280.08:03:12.42#ibcon#read 4, iclass 15, count 0 2006.280.08:03:12.42#ibcon#about to read 5, iclass 15, count 0 2006.280.08:03:12.42#ibcon#read 5, iclass 15, count 0 2006.280.08:03:12.42#ibcon#about to read 6, iclass 15, count 0 2006.280.08:03:12.42#ibcon#read 6, iclass 15, count 0 2006.280.08:03:12.42#ibcon#end of sib2, iclass 15, count 0 2006.280.08:03:12.42#ibcon#*after write, iclass 15, count 0 2006.280.08:03:12.42#ibcon#*before return 0, iclass 15, count 0 2006.280.08:03:12.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:12.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:12.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:03:12.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:03:12.42$vc4f8/va=1,7 2006.280.08:03:12.42#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:03:12.42#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:03:12.42#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:12.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:12.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:12.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:12.42#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:03:12.42#ibcon#first serial, iclass 17, count 2 2006.280.08:03:12.42#ibcon#enter sib2, iclass 17, count 2 2006.280.08:03:12.42#ibcon#flushed, iclass 17, count 2 2006.280.08:03:12.42#ibcon#about to write, iclass 17, count 2 2006.280.08:03:12.42#ibcon#wrote, iclass 17, count 2 2006.280.08:03:12.42#ibcon#about to read 3, iclass 17, count 2 2006.280.08:03:12.44#ibcon#read 3, iclass 17, count 2 2006.280.08:03:12.45#ibcon#about to read 4, iclass 17, count 2 2006.280.08:03:12.45#ibcon#read 4, iclass 17, count 2 2006.280.08:03:12.45#ibcon#about to read 5, iclass 17, count 2 2006.280.08:03:12.45#ibcon#read 5, iclass 17, count 2 2006.280.08:03:12.45#ibcon#about to read 6, iclass 17, count 2 2006.280.08:03:12.45#ibcon#read 6, iclass 17, count 2 2006.280.08:03:12.45#ibcon#end of sib2, iclass 17, count 2 2006.280.08:03:12.45#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:03:12.45#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:03:12.45#ibcon#[25=AT01-07\r\n] 2006.280.08:03:12.45#ibcon#*before write, iclass 17, count 2 2006.280.08:03:12.45#ibcon#enter sib2, iclass 17, count 2 2006.280.08:03:12.45#ibcon#flushed, iclass 17, count 2 2006.280.08:03:12.45#ibcon#about to write, iclass 17, count 2 2006.280.08:03:12.45#ibcon#wrote, iclass 17, count 2 2006.280.08:03:12.45#ibcon#about to read 3, iclass 17, count 2 2006.280.08:03:12.48#ibcon#read 3, iclass 17, count 2 2006.280.08:03:12.48#ibcon#about to read 4, iclass 17, count 2 2006.280.08:03:12.48#ibcon#read 4, iclass 17, count 2 2006.280.08:03:12.48#ibcon#about to read 5, iclass 17, count 2 2006.280.08:03:12.48#ibcon#read 5, iclass 17, count 2 2006.280.08:03:12.48#ibcon#about to read 6, iclass 17, count 2 2006.280.08:03:12.48#ibcon#read 6, iclass 17, count 2 2006.280.08:03:12.48#ibcon#end of sib2, iclass 17, count 2 2006.280.08:03:12.48#ibcon#*after write, iclass 17, count 2 2006.280.08:03:12.48#ibcon#*before return 0, iclass 17, count 2 2006.280.08:03:12.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:12.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:12.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:03:12.48#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:12.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:12.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:12.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:12.60#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:03:12.60#ibcon#first serial, iclass 17, count 0 2006.280.08:03:12.60#ibcon#enter sib2, iclass 17, count 0 2006.280.08:03:12.60#ibcon#flushed, iclass 17, count 0 2006.280.08:03:12.60#ibcon#about to write, iclass 17, count 0 2006.280.08:03:12.60#ibcon#wrote, iclass 17, count 0 2006.280.08:03:12.60#ibcon#about to read 3, iclass 17, count 0 2006.280.08:03:12.62#ibcon#read 3, iclass 17, count 0 2006.280.08:03:12.62#ibcon#about to read 4, iclass 17, count 0 2006.280.08:03:12.62#ibcon#read 4, iclass 17, count 0 2006.280.08:03:12.62#ibcon#about to read 5, iclass 17, count 0 2006.280.08:03:12.62#ibcon#read 5, iclass 17, count 0 2006.280.08:03:12.62#ibcon#about to read 6, iclass 17, count 0 2006.280.08:03:12.62#ibcon#read 6, iclass 17, count 0 2006.280.08:03:12.62#ibcon#end of sib2, iclass 17, count 0 2006.280.08:03:12.62#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:03:12.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:03:12.62#ibcon#[25=USB\r\n] 2006.280.08:03:12.62#ibcon#*before write, iclass 17, count 0 2006.280.08:03:12.62#ibcon#enter sib2, iclass 17, count 0 2006.280.08:03:12.62#ibcon#flushed, iclass 17, count 0 2006.280.08:03:12.62#ibcon#about to write, iclass 17, count 0 2006.280.08:03:12.62#ibcon#wrote, iclass 17, count 0 2006.280.08:03:12.62#ibcon#about to read 3, iclass 17, count 0 2006.280.08:03:12.65#ibcon#read 3, iclass 17, count 0 2006.280.08:03:12.65#ibcon#about to read 4, iclass 17, count 0 2006.280.08:03:12.65#ibcon#read 4, iclass 17, count 0 2006.280.08:03:12.65#ibcon#about to read 5, iclass 17, count 0 2006.280.08:03:12.65#ibcon#read 5, iclass 17, count 0 2006.280.08:03:12.65#ibcon#about to read 6, iclass 17, count 0 2006.280.08:03:12.65#ibcon#read 6, iclass 17, count 0 2006.280.08:03:12.65#ibcon#end of sib2, iclass 17, count 0 2006.280.08:03:12.65#ibcon#*after write, iclass 17, count 0 2006.280.08:03:12.65#ibcon#*before return 0, iclass 17, count 0 2006.280.08:03:12.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:12.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:12.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:03:12.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:03:12.65$vc4f8/valo=2,572.99 2006.280.08:03:12.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:03:12.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:03:12.65#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:12.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:12.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:12.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:12.65#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:03:12.65#ibcon#first serial, iclass 19, count 0 2006.280.08:03:12.65#ibcon#enter sib2, iclass 19, count 0 2006.280.08:03:12.65#ibcon#flushed, iclass 19, count 0 2006.280.08:03:12.65#ibcon#about to write, iclass 19, count 0 2006.280.08:03:12.65#ibcon#wrote, iclass 19, count 0 2006.280.08:03:12.65#ibcon#about to read 3, iclass 19, count 0 2006.280.08:03:12.67#ibcon#read 3, iclass 19, count 0 2006.280.08:03:12.67#ibcon#about to read 4, iclass 19, count 0 2006.280.08:03:12.67#ibcon#read 4, iclass 19, count 0 2006.280.08:03:12.67#ibcon#about to read 5, iclass 19, count 0 2006.280.08:03:12.67#ibcon#read 5, iclass 19, count 0 2006.280.08:03:12.67#ibcon#about to read 6, iclass 19, count 0 2006.280.08:03:12.67#ibcon#read 6, iclass 19, count 0 2006.280.08:03:12.67#ibcon#end of sib2, iclass 19, count 0 2006.280.08:03:12.67#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:03:12.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:03:12.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:03:12.67#ibcon#*before write, iclass 19, count 0 2006.280.08:03:12.67#ibcon#enter sib2, iclass 19, count 0 2006.280.08:03:12.67#ibcon#flushed, iclass 19, count 0 2006.280.08:03:12.67#ibcon#about to write, iclass 19, count 0 2006.280.08:03:12.67#ibcon#wrote, iclass 19, count 0 2006.280.08:03:12.67#ibcon#about to read 3, iclass 19, count 0 2006.280.08:03:12.71#ibcon#read 3, iclass 19, count 0 2006.280.08:03:12.71#ibcon#about to read 4, iclass 19, count 0 2006.280.08:03:12.71#ibcon#read 4, iclass 19, count 0 2006.280.08:03:12.71#ibcon#about to read 5, iclass 19, count 0 2006.280.08:03:12.71#ibcon#read 5, iclass 19, count 0 2006.280.08:03:12.71#ibcon#about to read 6, iclass 19, count 0 2006.280.08:03:12.71#ibcon#read 6, iclass 19, count 0 2006.280.08:03:12.71#ibcon#end of sib2, iclass 19, count 0 2006.280.08:03:12.71#ibcon#*after write, iclass 19, count 0 2006.280.08:03:12.71#ibcon#*before return 0, iclass 19, count 0 2006.280.08:03:12.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:12.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:12.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:03:12.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:03:12.71$vc4f8/va=2,6 2006.280.08:03:12.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:03:12.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:03:12.71#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:12.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:12.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:12.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:12.77#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:03:12.77#ibcon#first serial, iclass 21, count 2 2006.280.08:03:12.77#ibcon#enter sib2, iclass 21, count 2 2006.280.08:03:12.77#ibcon#flushed, iclass 21, count 2 2006.280.08:03:12.77#ibcon#about to write, iclass 21, count 2 2006.280.08:03:12.77#ibcon#wrote, iclass 21, count 2 2006.280.08:03:12.77#ibcon#about to read 3, iclass 21, count 2 2006.280.08:03:12.79#ibcon#read 3, iclass 21, count 2 2006.280.08:03:12.79#ibcon#about to read 4, iclass 21, count 2 2006.280.08:03:12.79#ibcon#read 4, iclass 21, count 2 2006.280.08:03:12.79#ibcon#about to read 5, iclass 21, count 2 2006.280.08:03:12.79#ibcon#read 5, iclass 21, count 2 2006.280.08:03:12.79#ibcon#about to read 6, iclass 21, count 2 2006.280.08:03:12.79#ibcon#read 6, iclass 21, count 2 2006.280.08:03:12.79#ibcon#end of sib2, iclass 21, count 2 2006.280.08:03:12.79#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:03:12.79#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:03:12.79#ibcon#[25=AT02-06\r\n] 2006.280.08:03:12.79#ibcon#*before write, iclass 21, count 2 2006.280.08:03:12.79#ibcon#enter sib2, iclass 21, count 2 2006.280.08:03:12.79#ibcon#flushed, iclass 21, count 2 2006.280.08:03:12.79#ibcon#about to write, iclass 21, count 2 2006.280.08:03:12.79#ibcon#wrote, iclass 21, count 2 2006.280.08:03:12.79#ibcon#about to read 3, iclass 21, count 2 2006.280.08:03:12.82#ibcon#read 3, iclass 21, count 2 2006.280.08:03:12.82#ibcon#about to read 4, iclass 21, count 2 2006.280.08:03:12.82#ibcon#read 4, iclass 21, count 2 2006.280.08:03:12.82#ibcon#about to read 5, iclass 21, count 2 2006.280.08:03:12.82#ibcon#read 5, iclass 21, count 2 2006.280.08:03:12.82#ibcon#about to read 6, iclass 21, count 2 2006.280.08:03:12.82#ibcon#read 6, iclass 21, count 2 2006.280.08:03:12.82#ibcon#end of sib2, iclass 21, count 2 2006.280.08:03:12.82#ibcon#*after write, iclass 21, count 2 2006.280.08:03:12.82#ibcon#*before return 0, iclass 21, count 2 2006.280.08:03:12.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:12.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:12.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:03:12.82#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:12.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:12.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:12.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:12.94#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:03:12.94#ibcon#first serial, iclass 21, count 0 2006.280.08:03:12.94#ibcon#enter sib2, iclass 21, count 0 2006.280.08:03:12.94#ibcon#flushed, iclass 21, count 0 2006.280.08:03:12.94#ibcon#about to write, iclass 21, count 0 2006.280.08:03:12.94#ibcon#wrote, iclass 21, count 0 2006.280.08:03:12.94#ibcon#about to read 3, iclass 21, count 0 2006.280.08:03:12.96#ibcon#read 3, iclass 21, count 0 2006.280.08:03:12.96#ibcon#about to read 4, iclass 21, count 0 2006.280.08:03:12.96#ibcon#read 4, iclass 21, count 0 2006.280.08:03:12.96#ibcon#about to read 5, iclass 21, count 0 2006.280.08:03:12.96#ibcon#read 5, iclass 21, count 0 2006.280.08:03:12.96#ibcon#about to read 6, iclass 21, count 0 2006.280.08:03:12.96#ibcon#read 6, iclass 21, count 0 2006.280.08:03:12.96#ibcon#end of sib2, iclass 21, count 0 2006.280.08:03:12.96#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:03:12.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:03:12.96#ibcon#[25=USB\r\n] 2006.280.08:03:12.96#ibcon#*before write, iclass 21, count 0 2006.280.08:03:12.96#ibcon#enter sib2, iclass 21, count 0 2006.280.08:03:12.96#ibcon#flushed, iclass 21, count 0 2006.280.08:03:12.96#ibcon#about to write, iclass 21, count 0 2006.280.08:03:12.96#ibcon#wrote, iclass 21, count 0 2006.280.08:03:12.96#ibcon#about to read 3, iclass 21, count 0 2006.280.08:03:12.99#ibcon#read 3, iclass 21, count 0 2006.280.08:03:12.99#ibcon#about to read 4, iclass 21, count 0 2006.280.08:03:12.99#ibcon#read 4, iclass 21, count 0 2006.280.08:03:12.99#ibcon#about to read 5, iclass 21, count 0 2006.280.08:03:12.99#ibcon#read 5, iclass 21, count 0 2006.280.08:03:12.99#ibcon#about to read 6, iclass 21, count 0 2006.280.08:03:12.99#ibcon#read 6, iclass 21, count 0 2006.280.08:03:12.99#ibcon#end of sib2, iclass 21, count 0 2006.280.08:03:12.99#ibcon#*after write, iclass 21, count 0 2006.280.08:03:12.99#ibcon#*before return 0, iclass 21, count 0 2006.280.08:03:12.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:12.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:12.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:03:12.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:03:12.99$vc4f8/valo=3,672.99 2006.280.08:03:12.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:03:12.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:03:12.99#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:12.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:12.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:12.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:12.99#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:03:12.99#ibcon#first serial, iclass 23, count 0 2006.280.08:03:12.99#ibcon#enter sib2, iclass 23, count 0 2006.280.08:03:12.99#ibcon#flushed, iclass 23, count 0 2006.280.08:03:12.99#ibcon#about to write, iclass 23, count 0 2006.280.08:03:12.99#ibcon#wrote, iclass 23, count 0 2006.280.08:03:12.99#ibcon#about to read 3, iclass 23, count 0 2006.280.08:03:13.01#ibcon#read 3, iclass 23, count 0 2006.280.08:03:13.01#ibcon#about to read 4, iclass 23, count 0 2006.280.08:03:13.01#ibcon#read 4, iclass 23, count 0 2006.280.08:03:13.01#ibcon#about to read 5, iclass 23, count 0 2006.280.08:03:13.01#ibcon#read 5, iclass 23, count 0 2006.280.08:03:13.01#ibcon#about to read 6, iclass 23, count 0 2006.280.08:03:13.01#ibcon#read 6, iclass 23, count 0 2006.280.08:03:13.01#ibcon#end of sib2, iclass 23, count 0 2006.280.08:03:13.01#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:03:13.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:03:13.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:03:13.01#ibcon#*before write, iclass 23, count 0 2006.280.08:03:13.01#ibcon#enter sib2, iclass 23, count 0 2006.280.08:03:13.01#ibcon#flushed, iclass 23, count 0 2006.280.08:03:13.01#ibcon#about to write, iclass 23, count 0 2006.280.08:03:13.01#ibcon#wrote, iclass 23, count 0 2006.280.08:03:13.01#ibcon#about to read 3, iclass 23, count 0 2006.280.08:03:13.05#ibcon#read 3, iclass 23, count 0 2006.280.08:03:13.05#ibcon#about to read 4, iclass 23, count 0 2006.280.08:03:13.05#ibcon#read 4, iclass 23, count 0 2006.280.08:03:13.05#ibcon#about to read 5, iclass 23, count 0 2006.280.08:03:13.05#ibcon#read 5, iclass 23, count 0 2006.280.08:03:13.05#ibcon#about to read 6, iclass 23, count 0 2006.280.08:03:13.05#ibcon#read 6, iclass 23, count 0 2006.280.08:03:13.05#ibcon#end of sib2, iclass 23, count 0 2006.280.08:03:13.05#ibcon#*after write, iclass 23, count 0 2006.280.08:03:13.05#ibcon#*before return 0, iclass 23, count 0 2006.280.08:03:13.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:13.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:13.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:03:13.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:03:13.05$vc4f8/va=3,6 2006.280.08:03:13.07#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.08:03:13.07#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.08:03:13.07#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:13.07#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:13.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:13.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:13.10#ibcon#enter wrdev, iclass 25, count 2 2006.280.08:03:13.10#ibcon#first serial, iclass 25, count 2 2006.280.08:03:13.10#ibcon#enter sib2, iclass 25, count 2 2006.280.08:03:13.10#ibcon#flushed, iclass 25, count 2 2006.280.08:03:13.10#ibcon#about to write, iclass 25, count 2 2006.280.08:03:13.10#ibcon#wrote, iclass 25, count 2 2006.280.08:03:13.10#ibcon#about to read 3, iclass 25, count 2 2006.280.08:03:13.12#ibcon#read 3, iclass 25, count 2 2006.280.08:03:13.12#ibcon#about to read 4, iclass 25, count 2 2006.280.08:03:13.12#ibcon#read 4, iclass 25, count 2 2006.280.08:03:13.12#ibcon#about to read 5, iclass 25, count 2 2006.280.08:03:13.12#ibcon#read 5, iclass 25, count 2 2006.280.08:03:13.12#ibcon#about to read 6, iclass 25, count 2 2006.280.08:03:13.12#ibcon#read 6, iclass 25, count 2 2006.280.08:03:13.12#ibcon#end of sib2, iclass 25, count 2 2006.280.08:03:13.12#ibcon#*mode == 0, iclass 25, count 2 2006.280.08:03:13.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.08:03:13.12#ibcon#[25=AT03-06\r\n] 2006.280.08:03:13.12#ibcon#*before write, iclass 25, count 2 2006.280.08:03:13.12#ibcon#enter sib2, iclass 25, count 2 2006.280.08:03:13.12#ibcon#flushed, iclass 25, count 2 2006.280.08:03:13.12#ibcon#about to write, iclass 25, count 2 2006.280.08:03:13.12#ibcon#wrote, iclass 25, count 2 2006.280.08:03:13.12#ibcon#about to read 3, iclass 25, count 2 2006.280.08:03:13.15#ibcon#read 3, iclass 25, count 2 2006.280.08:03:13.15#ibcon#about to read 4, iclass 25, count 2 2006.280.08:03:13.15#ibcon#read 4, iclass 25, count 2 2006.280.08:03:13.15#ibcon#about to read 5, iclass 25, count 2 2006.280.08:03:13.15#ibcon#read 5, iclass 25, count 2 2006.280.08:03:13.15#ibcon#about to read 6, iclass 25, count 2 2006.280.08:03:13.15#ibcon#read 6, iclass 25, count 2 2006.280.08:03:13.15#ibcon#end of sib2, iclass 25, count 2 2006.280.08:03:13.15#ibcon#*after write, iclass 25, count 2 2006.280.08:03:13.15#ibcon#*before return 0, iclass 25, count 2 2006.280.08:03:13.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:13.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:13.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.08:03:13.15#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:13.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:13.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:13.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:13.27#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:03:13.27#ibcon#first serial, iclass 25, count 0 2006.280.08:03:13.27#ibcon#enter sib2, iclass 25, count 0 2006.280.08:03:13.27#ibcon#flushed, iclass 25, count 0 2006.280.08:03:13.27#ibcon#about to write, iclass 25, count 0 2006.280.08:03:13.27#ibcon#wrote, iclass 25, count 0 2006.280.08:03:13.27#ibcon#about to read 3, iclass 25, count 0 2006.280.08:03:13.29#ibcon#read 3, iclass 25, count 0 2006.280.08:03:13.29#ibcon#about to read 4, iclass 25, count 0 2006.280.08:03:13.29#ibcon#read 4, iclass 25, count 0 2006.280.08:03:13.29#ibcon#about to read 5, iclass 25, count 0 2006.280.08:03:13.29#ibcon#read 5, iclass 25, count 0 2006.280.08:03:13.29#ibcon#about to read 6, iclass 25, count 0 2006.280.08:03:13.29#ibcon#read 6, iclass 25, count 0 2006.280.08:03:13.29#ibcon#end of sib2, iclass 25, count 0 2006.280.08:03:13.29#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:03:13.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:03:13.29#ibcon#[25=USB\r\n] 2006.280.08:03:13.29#ibcon#*before write, iclass 25, count 0 2006.280.08:03:13.29#ibcon#enter sib2, iclass 25, count 0 2006.280.08:03:13.29#ibcon#flushed, iclass 25, count 0 2006.280.08:03:13.29#ibcon#about to write, iclass 25, count 0 2006.280.08:03:13.29#ibcon#wrote, iclass 25, count 0 2006.280.08:03:13.29#ibcon#about to read 3, iclass 25, count 0 2006.280.08:03:13.32#ibcon#read 3, iclass 25, count 0 2006.280.08:03:13.32#ibcon#about to read 4, iclass 25, count 0 2006.280.08:03:13.32#ibcon#read 4, iclass 25, count 0 2006.280.08:03:13.32#ibcon#about to read 5, iclass 25, count 0 2006.280.08:03:13.32#ibcon#read 5, iclass 25, count 0 2006.280.08:03:13.32#ibcon#about to read 6, iclass 25, count 0 2006.280.08:03:13.32#ibcon#read 6, iclass 25, count 0 2006.280.08:03:13.32#ibcon#end of sib2, iclass 25, count 0 2006.280.08:03:13.32#ibcon#*after write, iclass 25, count 0 2006.280.08:03:13.32#ibcon#*before return 0, iclass 25, count 0 2006.280.08:03:13.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:13.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:13.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:03:13.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:03:13.32$vc4f8/valo=4,832.99 2006.280.08:03:13.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.08:03:13.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.08:03:13.32#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:13.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:13.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:13.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:13.32#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:03:13.32#ibcon#first serial, iclass 27, count 0 2006.280.08:03:13.32#ibcon#enter sib2, iclass 27, count 0 2006.280.08:03:13.32#ibcon#flushed, iclass 27, count 0 2006.280.08:03:13.32#ibcon#about to write, iclass 27, count 0 2006.280.08:03:13.32#ibcon#wrote, iclass 27, count 0 2006.280.08:03:13.32#ibcon#about to read 3, iclass 27, count 0 2006.280.08:03:13.34#ibcon#read 3, iclass 27, count 0 2006.280.08:03:13.34#ibcon#about to read 4, iclass 27, count 0 2006.280.08:03:13.34#ibcon#read 4, iclass 27, count 0 2006.280.08:03:13.34#ibcon#about to read 5, iclass 27, count 0 2006.280.08:03:13.34#ibcon#read 5, iclass 27, count 0 2006.280.08:03:13.34#ibcon#about to read 6, iclass 27, count 0 2006.280.08:03:13.34#ibcon#read 6, iclass 27, count 0 2006.280.08:03:13.34#ibcon#end of sib2, iclass 27, count 0 2006.280.08:03:13.34#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:03:13.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:03:13.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:03:13.34#ibcon#*before write, iclass 27, count 0 2006.280.08:03:13.34#ibcon#enter sib2, iclass 27, count 0 2006.280.08:03:13.34#ibcon#flushed, iclass 27, count 0 2006.280.08:03:13.34#ibcon#about to write, iclass 27, count 0 2006.280.08:03:13.34#ibcon#wrote, iclass 27, count 0 2006.280.08:03:13.34#ibcon#about to read 3, iclass 27, count 0 2006.280.08:03:13.38#ibcon#read 3, iclass 27, count 0 2006.280.08:03:13.38#ibcon#about to read 4, iclass 27, count 0 2006.280.08:03:13.38#ibcon#read 4, iclass 27, count 0 2006.280.08:03:13.38#ibcon#about to read 5, iclass 27, count 0 2006.280.08:03:13.38#ibcon#read 5, iclass 27, count 0 2006.280.08:03:13.38#ibcon#about to read 6, iclass 27, count 0 2006.280.08:03:13.38#ibcon#read 6, iclass 27, count 0 2006.280.08:03:13.38#ibcon#end of sib2, iclass 27, count 0 2006.280.08:03:13.38#ibcon#*after write, iclass 27, count 0 2006.280.08:03:13.38#ibcon#*before return 0, iclass 27, count 0 2006.280.08:03:13.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:13.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:13.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:03:13.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:03:13.38$vc4f8/va=4,6 2006.280.08:03:13.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.08:03:13.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.08:03:13.39#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:13.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:13.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:13.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:13.43#ibcon#enter wrdev, iclass 29, count 2 2006.280.08:03:13.43#ibcon#first serial, iclass 29, count 2 2006.280.08:03:13.43#ibcon#enter sib2, iclass 29, count 2 2006.280.08:03:13.43#ibcon#flushed, iclass 29, count 2 2006.280.08:03:13.43#ibcon#about to write, iclass 29, count 2 2006.280.08:03:13.43#ibcon#wrote, iclass 29, count 2 2006.280.08:03:13.43#ibcon#about to read 3, iclass 29, count 2 2006.280.08:03:13.45#ibcon#read 3, iclass 29, count 2 2006.280.08:03:13.45#ibcon#about to read 4, iclass 29, count 2 2006.280.08:03:13.45#ibcon#read 4, iclass 29, count 2 2006.280.08:03:13.45#ibcon#about to read 5, iclass 29, count 2 2006.280.08:03:13.45#ibcon#read 5, iclass 29, count 2 2006.280.08:03:13.45#ibcon#about to read 6, iclass 29, count 2 2006.280.08:03:13.45#ibcon#read 6, iclass 29, count 2 2006.280.08:03:13.45#ibcon#end of sib2, iclass 29, count 2 2006.280.08:03:13.45#ibcon#*mode == 0, iclass 29, count 2 2006.280.08:03:13.45#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.08:03:13.45#ibcon#[25=AT04-06\r\n] 2006.280.08:03:13.45#ibcon#*before write, iclass 29, count 2 2006.280.08:03:13.45#ibcon#enter sib2, iclass 29, count 2 2006.280.08:03:13.45#ibcon#flushed, iclass 29, count 2 2006.280.08:03:13.45#ibcon#about to write, iclass 29, count 2 2006.280.08:03:13.45#ibcon#wrote, iclass 29, count 2 2006.280.08:03:13.45#ibcon#about to read 3, iclass 29, count 2 2006.280.08:03:13.48#ibcon#read 3, iclass 29, count 2 2006.280.08:03:13.48#ibcon#about to read 4, iclass 29, count 2 2006.280.08:03:13.48#ibcon#read 4, iclass 29, count 2 2006.280.08:03:13.48#ibcon#about to read 5, iclass 29, count 2 2006.280.08:03:13.48#ibcon#read 5, iclass 29, count 2 2006.280.08:03:13.48#ibcon#about to read 6, iclass 29, count 2 2006.280.08:03:13.48#ibcon#read 6, iclass 29, count 2 2006.280.08:03:13.48#ibcon#end of sib2, iclass 29, count 2 2006.280.08:03:13.48#ibcon#*after write, iclass 29, count 2 2006.280.08:03:13.48#ibcon#*before return 0, iclass 29, count 2 2006.280.08:03:13.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:13.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:13.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.08:03:13.48#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:13.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:13.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:13.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:13.60#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:03:13.60#ibcon#first serial, iclass 29, count 0 2006.280.08:03:13.60#ibcon#enter sib2, iclass 29, count 0 2006.280.08:03:13.60#ibcon#flushed, iclass 29, count 0 2006.280.08:03:13.60#ibcon#about to write, iclass 29, count 0 2006.280.08:03:13.60#ibcon#wrote, iclass 29, count 0 2006.280.08:03:13.60#ibcon#about to read 3, iclass 29, count 0 2006.280.08:03:13.62#ibcon#read 3, iclass 29, count 0 2006.280.08:03:13.62#ibcon#about to read 4, iclass 29, count 0 2006.280.08:03:13.62#ibcon#read 4, iclass 29, count 0 2006.280.08:03:13.62#ibcon#about to read 5, iclass 29, count 0 2006.280.08:03:13.62#ibcon#read 5, iclass 29, count 0 2006.280.08:03:13.62#ibcon#about to read 6, iclass 29, count 0 2006.280.08:03:13.62#ibcon#read 6, iclass 29, count 0 2006.280.08:03:13.62#ibcon#end of sib2, iclass 29, count 0 2006.280.08:03:13.62#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:03:13.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:03:13.62#ibcon#[25=USB\r\n] 2006.280.08:03:13.62#ibcon#*before write, iclass 29, count 0 2006.280.08:03:13.62#ibcon#enter sib2, iclass 29, count 0 2006.280.08:03:13.62#ibcon#flushed, iclass 29, count 0 2006.280.08:03:13.62#ibcon#about to write, iclass 29, count 0 2006.280.08:03:13.62#ibcon#wrote, iclass 29, count 0 2006.280.08:03:13.62#ibcon#about to read 3, iclass 29, count 0 2006.280.08:03:13.65#ibcon#read 3, iclass 29, count 0 2006.280.08:03:13.65#ibcon#about to read 4, iclass 29, count 0 2006.280.08:03:13.65#ibcon#read 4, iclass 29, count 0 2006.280.08:03:13.65#ibcon#about to read 5, iclass 29, count 0 2006.280.08:03:13.65#ibcon#read 5, iclass 29, count 0 2006.280.08:03:13.65#ibcon#about to read 6, iclass 29, count 0 2006.280.08:03:13.65#ibcon#read 6, iclass 29, count 0 2006.280.08:03:13.65#ibcon#end of sib2, iclass 29, count 0 2006.280.08:03:13.65#ibcon#*after write, iclass 29, count 0 2006.280.08:03:13.65#ibcon#*before return 0, iclass 29, count 0 2006.280.08:03:13.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:13.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:13.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:03:13.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:03:13.65$vc4f8/valo=5,652.99 2006.280.08:03:13.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.08:03:13.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.08:03:13.65#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:13.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:13.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:13.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:13.65#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:03:13.65#ibcon#first serial, iclass 31, count 0 2006.280.08:03:13.65#ibcon#enter sib2, iclass 31, count 0 2006.280.08:03:13.65#ibcon#flushed, iclass 31, count 0 2006.280.08:03:13.65#ibcon#about to write, iclass 31, count 0 2006.280.08:03:13.65#ibcon#wrote, iclass 31, count 0 2006.280.08:03:13.65#ibcon#about to read 3, iclass 31, count 0 2006.280.08:03:13.67#ibcon#read 3, iclass 31, count 0 2006.280.08:03:13.68#ibcon#about to read 4, iclass 31, count 0 2006.280.08:03:13.68#ibcon#read 4, iclass 31, count 0 2006.280.08:03:13.68#ibcon#about to read 5, iclass 31, count 0 2006.280.08:03:13.68#ibcon#read 5, iclass 31, count 0 2006.280.08:03:13.68#ibcon#about to read 6, iclass 31, count 0 2006.280.08:03:13.68#ibcon#read 6, iclass 31, count 0 2006.280.08:03:13.68#ibcon#end of sib2, iclass 31, count 0 2006.280.08:03:13.68#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:03:13.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:03:13.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:03:13.68#ibcon#*before write, iclass 31, count 0 2006.280.08:03:13.68#ibcon#enter sib2, iclass 31, count 0 2006.280.08:03:13.68#ibcon#flushed, iclass 31, count 0 2006.280.08:03:13.68#ibcon#about to write, iclass 31, count 0 2006.280.08:03:13.68#ibcon#wrote, iclass 31, count 0 2006.280.08:03:13.68#ibcon#about to read 3, iclass 31, count 0 2006.280.08:03:13.73#ibcon#read 3, iclass 31, count 0 2006.280.08:03:13.73#ibcon#about to read 4, iclass 31, count 0 2006.280.08:03:13.73#ibcon#read 4, iclass 31, count 0 2006.280.08:03:13.73#ibcon#about to read 5, iclass 31, count 0 2006.280.08:03:13.73#ibcon#read 5, iclass 31, count 0 2006.280.08:03:13.73#ibcon#about to read 6, iclass 31, count 0 2006.280.08:03:13.73#ibcon#read 6, iclass 31, count 0 2006.280.08:03:13.73#ibcon#end of sib2, iclass 31, count 0 2006.280.08:03:13.73#ibcon#*after write, iclass 31, count 0 2006.280.08:03:13.73#ibcon#*before return 0, iclass 31, count 0 2006.280.08:03:13.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:13.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:13.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:03:13.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:03:13.73$vc4f8/va=5,7 2006.280.08:03:13.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.08:03:13.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.08:03:13.73#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:13.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:13.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:13.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:13.77#ibcon#enter wrdev, iclass 33, count 2 2006.280.08:03:13.77#ibcon#first serial, iclass 33, count 2 2006.280.08:03:13.77#ibcon#enter sib2, iclass 33, count 2 2006.280.08:03:13.77#ibcon#flushed, iclass 33, count 2 2006.280.08:03:13.77#ibcon#about to write, iclass 33, count 2 2006.280.08:03:13.77#ibcon#wrote, iclass 33, count 2 2006.280.08:03:13.77#ibcon#about to read 3, iclass 33, count 2 2006.280.08:03:13.79#ibcon#read 3, iclass 33, count 2 2006.280.08:03:13.79#ibcon#about to read 4, iclass 33, count 2 2006.280.08:03:13.79#ibcon#read 4, iclass 33, count 2 2006.280.08:03:13.79#ibcon#about to read 5, iclass 33, count 2 2006.280.08:03:13.79#ibcon#read 5, iclass 33, count 2 2006.280.08:03:13.79#ibcon#about to read 6, iclass 33, count 2 2006.280.08:03:13.79#ibcon#read 6, iclass 33, count 2 2006.280.08:03:13.79#ibcon#end of sib2, iclass 33, count 2 2006.280.08:03:13.79#ibcon#*mode == 0, iclass 33, count 2 2006.280.08:03:13.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.08:03:13.79#ibcon#[25=AT05-07\r\n] 2006.280.08:03:13.79#ibcon#*before write, iclass 33, count 2 2006.280.08:03:13.79#ibcon#enter sib2, iclass 33, count 2 2006.280.08:03:13.79#ibcon#flushed, iclass 33, count 2 2006.280.08:03:13.79#ibcon#about to write, iclass 33, count 2 2006.280.08:03:13.79#ibcon#wrote, iclass 33, count 2 2006.280.08:03:13.79#ibcon#about to read 3, iclass 33, count 2 2006.280.08:03:13.82#ibcon#read 3, iclass 33, count 2 2006.280.08:03:13.82#ibcon#about to read 4, iclass 33, count 2 2006.280.08:03:13.82#ibcon#read 4, iclass 33, count 2 2006.280.08:03:13.82#ibcon#about to read 5, iclass 33, count 2 2006.280.08:03:13.82#ibcon#read 5, iclass 33, count 2 2006.280.08:03:13.82#ibcon#about to read 6, iclass 33, count 2 2006.280.08:03:13.82#ibcon#read 6, iclass 33, count 2 2006.280.08:03:13.82#ibcon#end of sib2, iclass 33, count 2 2006.280.08:03:13.82#ibcon#*after write, iclass 33, count 2 2006.280.08:03:13.82#ibcon#*before return 0, iclass 33, count 2 2006.280.08:03:13.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:13.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:13.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.08:03:13.82#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:13.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:13.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:13.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:13.94#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:03:13.94#ibcon#first serial, iclass 33, count 0 2006.280.08:03:13.94#ibcon#enter sib2, iclass 33, count 0 2006.280.08:03:13.94#ibcon#flushed, iclass 33, count 0 2006.280.08:03:13.94#ibcon#about to write, iclass 33, count 0 2006.280.08:03:13.94#ibcon#wrote, iclass 33, count 0 2006.280.08:03:13.94#ibcon#about to read 3, iclass 33, count 0 2006.280.08:03:13.96#ibcon#read 3, iclass 33, count 0 2006.280.08:03:13.96#ibcon#about to read 4, iclass 33, count 0 2006.280.08:03:13.96#ibcon#read 4, iclass 33, count 0 2006.280.08:03:13.96#ibcon#about to read 5, iclass 33, count 0 2006.280.08:03:13.96#ibcon#read 5, iclass 33, count 0 2006.280.08:03:13.96#ibcon#about to read 6, iclass 33, count 0 2006.280.08:03:13.96#ibcon#read 6, iclass 33, count 0 2006.280.08:03:13.96#ibcon#end of sib2, iclass 33, count 0 2006.280.08:03:13.96#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:03:13.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:03:13.96#ibcon#[25=USB\r\n] 2006.280.08:03:13.96#ibcon#*before write, iclass 33, count 0 2006.280.08:03:13.96#ibcon#enter sib2, iclass 33, count 0 2006.280.08:03:13.96#ibcon#flushed, iclass 33, count 0 2006.280.08:03:13.96#ibcon#about to write, iclass 33, count 0 2006.280.08:03:13.96#ibcon#wrote, iclass 33, count 0 2006.280.08:03:13.96#ibcon#about to read 3, iclass 33, count 0 2006.280.08:03:13.99#ibcon#read 3, iclass 33, count 0 2006.280.08:03:13.99#ibcon#about to read 4, iclass 33, count 0 2006.280.08:03:13.99#ibcon#read 4, iclass 33, count 0 2006.280.08:03:13.99#ibcon#about to read 5, iclass 33, count 0 2006.280.08:03:13.99#ibcon#read 5, iclass 33, count 0 2006.280.08:03:13.99#ibcon#about to read 6, iclass 33, count 0 2006.280.08:03:13.99#ibcon#read 6, iclass 33, count 0 2006.280.08:03:13.99#ibcon#end of sib2, iclass 33, count 0 2006.280.08:03:13.99#ibcon#*after write, iclass 33, count 0 2006.280.08:03:13.99#ibcon#*before return 0, iclass 33, count 0 2006.280.08:03:13.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:13.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:13.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:03:13.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:03:13.99$vc4f8/valo=6,772.99 2006.280.08:03:13.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.08:03:13.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.08:03:13.99#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:13.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:13.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:13.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:13.99#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:03:13.99#ibcon#first serial, iclass 35, count 0 2006.280.08:03:13.99#ibcon#enter sib2, iclass 35, count 0 2006.280.08:03:13.99#ibcon#flushed, iclass 35, count 0 2006.280.08:03:13.99#ibcon#about to write, iclass 35, count 0 2006.280.08:03:13.99#ibcon#wrote, iclass 35, count 0 2006.280.08:03:13.99#ibcon#about to read 3, iclass 35, count 0 2006.280.08:03:14.01#ibcon#read 3, iclass 35, count 0 2006.280.08:03:14.01#ibcon#about to read 4, iclass 35, count 0 2006.280.08:03:14.01#ibcon#read 4, iclass 35, count 0 2006.280.08:03:14.01#ibcon#about to read 5, iclass 35, count 0 2006.280.08:03:14.01#ibcon#read 5, iclass 35, count 0 2006.280.08:03:14.01#ibcon#about to read 6, iclass 35, count 0 2006.280.08:03:14.01#ibcon#read 6, iclass 35, count 0 2006.280.08:03:14.01#ibcon#end of sib2, iclass 35, count 0 2006.280.08:03:14.01#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:03:14.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:03:14.01#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:03:14.01#ibcon#*before write, iclass 35, count 0 2006.280.08:03:14.01#ibcon#enter sib2, iclass 35, count 0 2006.280.08:03:14.01#ibcon#flushed, iclass 35, count 0 2006.280.08:03:14.01#ibcon#about to write, iclass 35, count 0 2006.280.08:03:14.01#ibcon#wrote, iclass 35, count 0 2006.280.08:03:14.01#ibcon#about to read 3, iclass 35, count 0 2006.280.08:03:14.05#ibcon#read 3, iclass 35, count 0 2006.280.08:03:14.05#ibcon#about to read 4, iclass 35, count 0 2006.280.08:03:14.05#ibcon#read 4, iclass 35, count 0 2006.280.08:03:14.05#ibcon#about to read 5, iclass 35, count 0 2006.280.08:03:14.05#ibcon#read 5, iclass 35, count 0 2006.280.08:03:14.05#ibcon#about to read 6, iclass 35, count 0 2006.280.08:03:14.05#ibcon#read 6, iclass 35, count 0 2006.280.08:03:14.05#ibcon#end of sib2, iclass 35, count 0 2006.280.08:03:14.05#ibcon#*after write, iclass 35, count 0 2006.280.08:03:14.05#ibcon#*before return 0, iclass 35, count 0 2006.280.08:03:14.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:14.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:14.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:03:14.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:03:14.05$vc4f8/va=6,6 2006.280.08:03:14.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.08:03:14.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.08:03:14.05#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:14.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:14.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:14.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:14.11#ibcon#enter wrdev, iclass 37, count 2 2006.280.08:03:14.11#ibcon#first serial, iclass 37, count 2 2006.280.08:03:14.11#ibcon#enter sib2, iclass 37, count 2 2006.280.08:03:14.11#ibcon#flushed, iclass 37, count 2 2006.280.08:03:14.11#ibcon#about to write, iclass 37, count 2 2006.280.08:03:14.11#ibcon#wrote, iclass 37, count 2 2006.280.08:03:14.11#ibcon#about to read 3, iclass 37, count 2 2006.280.08:03:14.13#ibcon#read 3, iclass 37, count 2 2006.280.08:03:14.13#ibcon#about to read 4, iclass 37, count 2 2006.280.08:03:14.13#ibcon#read 4, iclass 37, count 2 2006.280.08:03:14.13#ibcon#about to read 5, iclass 37, count 2 2006.280.08:03:14.13#ibcon#read 5, iclass 37, count 2 2006.280.08:03:14.13#ibcon#about to read 6, iclass 37, count 2 2006.280.08:03:14.13#ibcon#read 6, iclass 37, count 2 2006.280.08:03:14.13#ibcon#end of sib2, iclass 37, count 2 2006.280.08:03:14.13#ibcon#*mode == 0, iclass 37, count 2 2006.280.08:03:14.13#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.08:03:14.13#ibcon#[25=AT06-06\r\n] 2006.280.08:03:14.13#ibcon#*before write, iclass 37, count 2 2006.280.08:03:14.13#ibcon#enter sib2, iclass 37, count 2 2006.280.08:03:14.13#ibcon#flushed, iclass 37, count 2 2006.280.08:03:14.13#ibcon#about to write, iclass 37, count 2 2006.280.08:03:14.13#ibcon#wrote, iclass 37, count 2 2006.280.08:03:14.13#ibcon#about to read 3, iclass 37, count 2 2006.280.08:03:14.16#ibcon#read 3, iclass 37, count 2 2006.280.08:03:14.16#ibcon#about to read 4, iclass 37, count 2 2006.280.08:03:14.16#ibcon#read 4, iclass 37, count 2 2006.280.08:03:14.16#ibcon#about to read 5, iclass 37, count 2 2006.280.08:03:14.16#ibcon#read 5, iclass 37, count 2 2006.280.08:03:14.16#ibcon#about to read 6, iclass 37, count 2 2006.280.08:03:14.16#ibcon#read 6, iclass 37, count 2 2006.280.08:03:14.16#ibcon#end of sib2, iclass 37, count 2 2006.280.08:03:14.16#ibcon#*after write, iclass 37, count 2 2006.280.08:03:14.16#ibcon#*before return 0, iclass 37, count 2 2006.280.08:03:14.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:14.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:14.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.08:03:14.16#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:14.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:03:14.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:03:14.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:03:14.28#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:03:14.28#ibcon#first serial, iclass 37, count 0 2006.280.08:03:14.28#ibcon#enter sib2, iclass 37, count 0 2006.280.08:03:14.28#ibcon#flushed, iclass 37, count 0 2006.280.08:03:14.28#ibcon#about to write, iclass 37, count 0 2006.280.08:03:14.28#ibcon#wrote, iclass 37, count 0 2006.280.08:03:14.28#ibcon#about to read 3, iclass 37, count 0 2006.280.08:03:14.30#ibcon#read 3, iclass 37, count 0 2006.280.08:03:14.30#ibcon#about to read 4, iclass 37, count 0 2006.280.08:03:14.30#ibcon#read 4, iclass 37, count 0 2006.280.08:03:14.30#ibcon#about to read 5, iclass 37, count 0 2006.280.08:03:14.30#ibcon#read 5, iclass 37, count 0 2006.280.08:03:14.30#ibcon#about to read 6, iclass 37, count 0 2006.280.08:03:14.30#ibcon#read 6, iclass 37, count 0 2006.280.08:03:14.30#ibcon#end of sib2, iclass 37, count 0 2006.280.08:03:14.30#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:03:14.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:03:14.30#ibcon#[25=USB\r\n] 2006.280.08:03:14.30#ibcon#*before write, iclass 37, count 0 2006.280.08:03:14.30#ibcon#enter sib2, iclass 37, count 0 2006.280.08:03:14.30#ibcon#flushed, iclass 37, count 0 2006.280.08:03:14.30#ibcon#about to write, iclass 37, count 0 2006.280.08:03:14.30#ibcon#wrote, iclass 37, count 0 2006.280.08:03:14.30#ibcon#about to read 3, iclass 37, count 0 2006.280.08:03:14.33#ibcon#read 3, iclass 37, count 0 2006.280.08:03:14.33#ibcon#about to read 4, iclass 37, count 0 2006.280.08:03:14.33#ibcon#read 4, iclass 37, count 0 2006.280.08:03:14.33#ibcon#about to read 5, iclass 37, count 0 2006.280.08:03:14.33#ibcon#read 5, iclass 37, count 0 2006.280.08:03:14.33#ibcon#about to read 6, iclass 37, count 0 2006.280.08:03:14.33#ibcon#read 6, iclass 37, count 0 2006.280.08:03:14.33#ibcon#end of sib2, iclass 37, count 0 2006.280.08:03:14.33#ibcon#*after write, iclass 37, count 0 2006.280.08:03:14.33#ibcon#*before return 0, iclass 37, count 0 2006.280.08:03:14.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:03:14.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:03:14.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:03:14.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:03:14.33$vc4f8/valo=7,832.99 2006.280.08:03:14.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.08:03:14.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.08:03:14.33#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:14.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:03:14.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:03:14.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:03:14.33#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:03:14.33#ibcon#first serial, iclass 39, count 0 2006.280.08:03:14.33#ibcon#enter sib2, iclass 39, count 0 2006.280.08:03:14.33#ibcon#flushed, iclass 39, count 0 2006.280.08:03:14.33#ibcon#about to write, iclass 39, count 0 2006.280.08:03:14.33#ibcon#wrote, iclass 39, count 0 2006.280.08:03:14.33#ibcon#about to read 3, iclass 39, count 0 2006.280.08:03:14.35#ibcon#read 3, iclass 39, count 0 2006.280.08:03:14.35#ibcon#about to read 4, iclass 39, count 0 2006.280.08:03:14.35#ibcon#read 4, iclass 39, count 0 2006.280.08:03:14.35#ibcon#about to read 5, iclass 39, count 0 2006.280.08:03:14.35#ibcon#read 5, iclass 39, count 0 2006.280.08:03:14.35#ibcon#about to read 6, iclass 39, count 0 2006.280.08:03:14.35#ibcon#read 6, iclass 39, count 0 2006.280.08:03:14.35#ibcon#end of sib2, iclass 39, count 0 2006.280.08:03:14.35#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:03:14.35#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:03:14.35#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:03:14.35#ibcon#*before write, iclass 39, count 0 2006.280.08:03:14.35#ibcon#enter sib2, iclass 39, count 0 2006.280.08:03:14.35#ibcon#flushed, iclass 39, count 0 2006.280.08:03:14.35#ibcon#about to write, iclass 39, count 0 2006.280.08:03:14.35#ibcon#wrote, iclass 39, count 0 2006.280.08:03:14.35#ibcon#about to read 3, iclass 39, count 0 2006.280.08:03:14.39#ibcon#read 3, iclass 39, count 0 2006.280.08:03:14.39#ibcon#about to read 4, iclass 39, count 0 2006.280.08:03:14.39#ibcon#read 4, iclass 39, count 0 2006.280.08:03:14.39#ibcon#about to read 5, iclass 39, count 0 2006.280.08:03:14.39#ibcon#read 5, iclass 39, count 0 2006.280.08:03:14.39#ibcon#about to read 6, iclass 39, count 0 2006.280.08:03:14.39#ibcon#read 6, iclass 39, count 0 2006.280.08:03:14.39#ibcon#end of sib2, iclass 39, count 0 2006.280.08:03:14.39#ibcon#*after write, iclass 39, count 0 2006.280.08:03:14.39#ibcon#*before return 0, iclass 39, count 0 2006.280.08:03:14.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:03:14.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:03:14.39#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:03:14.39#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:03:14.39$vc4f8/va=7,6 2006.280.08:03:14.41#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.08:03:14.41#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.08:03:14.41#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:14.41#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:03:14.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:03:14.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:03:14.44#ibcon#enter wrdev, iclass 3, count 2 2006.280.08:03:14.44#ibcon#first serial, iclass 3, count 2 2006.280.08:03:14.44#ibcon#enter sib2, iclass 3, count 2 2006.280.08:03:14.44#ibcon#flushed, iclass 3, count 2 2006.280.08:03:14.44#ibcon#about to write, iclass 3, count 2 2006.280.08:03:14.44#ibcon#wrote, iclass 3, count 2 2006.280.08:03:14.44#ibcon#about to read 3, iclass 3, count 2 2006.280.08:03:14.46#ibcon#read 3, iclass 3, count 2 2006.280.08:03:14.46#ibcon#about to read 4, iclass 3, count 2 2006.280.08:03:14.46#ibcon#read 4, iclass 3, count 2 2006.280.08:03:14.46#ibcon#about to read 5, iclass 3, count 2 2006.280.08:03:14.46#ibcon#read 5, iclass 3, count 2 2006.280.08:03:14.46#ibcon#about to read 6, iclass 3, count 2 2006.280.08:03:14.46#ibcon#read 6, iclass 3, count 2 2006.280.08:03:14.46#ibcon#end of sib2, iclass 3, count 2 2006.280.08:03:14.46#ibcon#*mode == 0, iclass 3, count 2 2006.280.08:03:14.46#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.08:03:14.46#ibcon#[25=AT07-06\r\n] 2006.280.08:03:14.46#ibcon#*before write, iclass 3, count 2 2006.280.08:03:14.46#ibcon#enter sib2, iclass 3, count 2 2006.280.08:03:14.46#ibcon#flushed, iclass 3, count 2 2006.280.08:03:14.46#ibcon#about to write, iclass 3, count 2 2006.280.08:03:14.46#ibcon#wrote, iclass 3, count 2 2006.280.08:03:14.46#ibcon#about to read 3, iclass 3, count 2 2006.280.08:03:14.49#ibcon#read 3, iclass 3, count 2 2006.280.08:03:14.49#ibcon#about to read 4, iclass 3, count 2 2006.280.08:03:14.49#ibcon#read 4, iclass 3, count 2 2006.280.08:03:14.49#ibcon#about to read 5, iclass 3, count 2 2006.280.08:03:14.49#ibcon#read 5, iclass 3, count 2 2006.280.08:03:14.49#ibcon#about to read 6, iclass 3, count 2 2006.280.08:03:14.49#ibcon#read 6, iclass 3, count 2 2006.280.08:03:14.49#ibcon#end of sib2, iclass 3, count 2 2006.280.08:03:14.49#ibcon#*after write, iclass 3, count 2 2006.280.08:03:14.49#ibcon#*before return 0, iclass 3, count 2 2006.280.08:03:14.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:03:14.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:03:14.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.08:03:14.49#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:14.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:03:14.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:03:14.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:03:14.61#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:03:14.61#ibcon#first serial, iclass 3, count 0 2006.280.08:03:14.61#ibcon#enter sib2, iclass 3, count 0 2006.280.08:03:14.61#ibcon#flushed, iclass 3, count 0 2006.280.08:03:14.61#ibcon#about to write, iclass 3, count 0 2006.280.08:03:14.61#ibcon#wrote, iclass 3, count 0 2006.280.08:03:14.61#ibcon#about to read 3, iclass 3, count 0 2006.280.08:03:14.63#ibcon#read 3, iclass 3, count 0 2006.280.08:03:14.63#ibcon#about to read 4, iclass 3, count 0 2006.280.08:03:14.63#ibcon#read 4, iclass 3, count 0 2006.280.08:03:14.63#ibcon#about to read 5, iclass 3, count 0 2006.280.08:03:14.63#ibcon#read 5, iclass 3, count 0 2006.280.08:03:14.63#ibcon#about to read 6, iclass 3, count 0 2006.280.08:03:14.63#ibcon#read 6, iclass 3, count 0 2006.280.08:03:14.63#ibcon#end of sib2, iclass 3, count 0 2006.280.08:03:14.63#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:03:14.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:03:14.63#ibcon#[25=USB\r\n] 2006.280.08:03:14.63#ibcon#*before write, iclass 3, count 0 2006.280.08:03:14.63#ibcon#enter sib2, iclass 3, count 0 2006.280.08:03:14.63#ibcon#flushed, iclass 3, count 0 2006.280.08:03:14.63#ibcon#about to write, iclass 3, count 0 2006.280.08:03:14.63#ibcon#wrote, iclass 3, count 0 2006.280.08:03:14.63#ibcon#about to read 3, iclass 3, count 0 2006.280.08:03:14.66#ibcon#read 3, iclass 3, count 0 2006.280.08:03:14.66#ibcon#about to read 4, iclass 3, count 0 2006.280.08:03:14.66#ibcon#read 4, iclass 3, count 0 2006.280.08:03:14.66#ibcon#about to read 5, iclass 3, count 0 2006.280.08:03:14.66#ibcon#read 5, iclass 3, count 0 2006.280.08:03:14.66#ibcon#about to read 6, iclass 3, count 0 2006.280.08:03:14.66#ibcon#read 6, iclass 3, count 0 2006.280.08:03:14.66#ibcon#end of sib2, iclass 3, count 0 2006.280.08:03:14.66#ibcon#*after write, iclass 3, count 0 2006.280.08:03:14.66#ibcon#*before return 0, iclass 3, count 0 2006.280.08:03:14.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:03:14.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:03:14.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:03:14.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:03:14.66$vc4f8/valo=8,852.99 2006.280.08:03:14.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.08:03:14.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.08:03:14.66#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:14.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:03:14.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:03:14.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:03:14.66#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:03:14.66#ibcon#first serial, iclass 5, count 0 2006.280.08:03:14.66#ibcon#enter sib2, iclass 5, count 0 2006.280.08:03:14.66#ibcon#flushed, iclass 5, count 0 2006.280.08:03:14.66#ibcon#about to write, iclass 5, count 0 2006.280.08:03:14.66#ibcon#wrote, iclass 5, count 0 2006.280.08:03:14.66#ibcon#about to read 3, iclass 5, count 0 2006.280.08:03:14.68#ibcon#read 3, iclass 5, count 0 2006.280.08:03:14.68#ibcon#about to read 4, iclass 5, count 0 2006.280.08:03:14.68#ibcon#read 4, iclass 5, count 0 2006.280.08:03:14.68#ibcon#about to read 5, iclass 5, count 0 2006.280.08:03:14.68#ibcon#read 5, iclass 5, count 0 2006.280.08:03:14.68#ibcon#about to read 6, iclass 5, count 0 2006.280.08:03:14.68#ibcon#read 6, iclass 5, count 0 2006.280.08:03:14.68#ibcon#end of sib2, iclass 5, count 0 2006.280.08:03:14.68#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:03:14.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:03:14.68#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:03:14.68#ibcon#*before write, iclass 5, count 0 2006.280.08:03:14.68#ibcon#enter sib2, iclass 5, count 0 2006.280.08:03:14.68#ibcon#flushed, iclass 5, count 0 2006.280.08:03:14.68#ibcon#about to write, iclass 5, count 0 2006.280.08:03:14.68#ibcon#wrote, iclass 5, count 0 2006.280.08:03:14.68#ibcon#about to read 3, iclass 5, count 0 2006.280.08:03:14.72#ibcon#read 3, iclass 5, count 0 2006.280.08:03:14.72#ibcon#about to read 4, iclass 5, count 0 2006.280.08:03:14.72#ibcon#read 4, iclass 5, count 0 2006.280.08:03:14.72#ibcon#about to read 5, iclass 5, count 0 2006.280.08:03:14.72#ibcon#read 5, iclass 5, count 0 2006.280.08:03:14.72#ibcon#about to read 6, iclass 5, count 0 2006.280.08:03:14.72#ibcon#read 6, iclass 5, count 0 2006.280.08:03:14.72#ibcon#end of sib2, iclass 5, count 0 2006.280.08:03:14.72#ibcon#*after write, iclass 5, count 0 2006.280.08:03:14.72#ibcon#*before return 0, iclass 5, count 0 2006.280.08:03:14.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:03:14.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:03:14.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:03:14.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:03:14.72$vc4f8/va=8,6 2006.280.08:03:14.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.08:03:14.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.08:03:14.72#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:14.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:03:14.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:03:14.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:03:14.79#ibcon#enter wrdev, iclass 7, count 2 2006.280.08:03:14.79#ibcon#first serial, iclass 7, count 2 2006.280.08:03:14.79#ibcon#enter sib2, iclass 7, count 2 2006.280.08:03:14.79#ibcon#flushed, iclass 7, count 2 2006.280.08:03:14.79#ibcon#about to write, iclass 7, count 2 2006.280.08:03:14.79#ibcon#wrote, iclass 7, count 2 2006.280.08:03:14.79#ibcon#about to read 3, iclass 7, count 2 2006.280.08:03:14.80#ibcon#read 3, iclass 7, count 2 2006.280.08:03:14.80#ibcon#about to read 4, iclass 7, count 2 2006.280.08:03:14.80#ibcon#read 4, iclass 7, count 2 2006.280.08:03:14.80#ibcon#about to read 5, iclass 7, count 2 2006.280.08:03:14.80#ibcon#read 5, iclass 7, count 2 2006.280.08:03:14.80#ibcon#about to read 6, iclass 7, count 2 2006.280.08:03:14.80#ibcon#read 6, iclass 7, count 2 2006.280.08:03:14.80#ibcon#end of sib2, iclass 7, count 2 2006.280.08:03:14.80#ibcon#*mode == 0, iclass 7, count 2 2006.280.08:03:14.80#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.08:03:14.80#ibcon#[25=AT08-06\r\n] 2006.280.08:03:14.80#ibcon#*before write, iclass 7, count 2 2006.280.08:03:14.80#ibcon#enter sib2, iclass 7, count 2 2006.280.08:03:14.80#ibcon#flushed, iclass 7, count 2 2006.280.08:03:14.80#ibcon#about to write, iclass 7, count 2 2006.280.08:03:14.80#ibcon#wrote, iclass 7, count 2 2006.280.08:03:14.80#ibcon#about to read 3, iclass 7, count 2 2006.280.08:03:14.83#ibcon#read 3, iclass 7, count 2 2006.280.08:03:14.83#ibcon#about to read 4, iclass 7, count 2 2006.280.08:03:14.83#ibcon#read 4, iclass 7, count 2 2006.280.08:03:14.83#ibcon#about to read 5, iclass 7, count 2 2006.280.08:03:14.83#ibcon#read 5, iclass 7, count 2 2006.280.08:03:14.83#ibcon#about to read 6, iclass 7, count 2 2006.280.08:03:14.83#ibcon#read 6, iclass 7, count 2 2006.280.08:03:14.83#ibcon#end of sib2, iclass 7, count 2 2006.280.08:03:14.83#ibcon#*after write, iclass 7, count 2 2006.280.08:03:14.83#ibcon#*before return 0, iclass 7, count 2 2006.280.08:03:14.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:03:14.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:03:14.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.08:03:14.83#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:14.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:03:14.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:03:14.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:03:14.95#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:03:14.95#ibcon#first serial, iclass 7, count 0 2006.280.08:03:14.95#ibcon#enter sib2, iclass 7, count 0 2006.280.08:03:14.95#ibcon#flushed, iclass 7, count 0 2006.280.08:03:14.95#ibcon#about to write, iclass 7, count 0 2006.280.08:03:14.95#ibcon#wrote, iclass 7, count 0 2006.280.08:03:14.95#ibcon#about to read 3, iclass 7, count 0 2006.280.08:03:14.97#ibcon#read 3, iclass 7, count 0 2006.280.08:03:14.97#ibcon#about to read 4, iclass 7, count 0 2006.280.08:03:14.97#ibcon#read 4, iclass 7, count 0 2006.280.08:03:14.97#ibcon#about to read 5, iclass 7, count 0 2006.280.08:03:14.97#ibcon#read 5, iclass 7, count 0 2006.280.08:03:14.97#ibcon#about to read 6, iclass 7, count 0 2006.280.08:03:14.97#ibcon#read 6, iclass 7, count 0 2006.280.08:03:14.97#ibcon#end of sib2, iclass 7, count 0 2006.280.08:03:14.97#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:03:14.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:03:14.97#ibcon#[25=USB\r\n] 2006.280.08:03:14.97#ibcon#*before write, iclass 7, count 0 2006.280.08:03:14.97#ibcon#enter sib2, iclass 7, count 0 2006.280.08:03:14.97#ibcon#flushed, iclass 7, count 0 2006.280.08:03:14.97#ibcon#about to write, iclass 7, count 0 2006.280.08:03:14.97#ibcon#wrote, iclass 7, count 0 2006.280.08:03:14.97#ibcon#about to read 3, iclass 7, count 0 2006.280.08:03:15.00#ibcon#read 3, iclass 7, count 0 2006.280.08:03:15.00#ibcon#about to read 4, iclass 7, count 0 2006.280.08:03:15.00#ibcon#read 4, iclass 7, count 0 2006.280.08:03:15.00#ibcon#about to read 5, iclass 7, count 0 2006.280.08:03:15.00#ibcon#read 5, iclass 7, count 0 2006.280.08:03:15.00#ibcon#about to read 6, iclass 7, count 0 2006.280.08:03:15.00#ibcon#read 6, iclass 7, count 0 2006.280.08:03:15.00#ibcon#end of sib2, iclass 7, count 0 2006.280.08:03:15.00#ibcon#*after write, iclass 7, count 0 2006.280.08:03:15.00#ibcon#*before return 0, iclass 7, count 0 2006.280.08:03:15.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:03:15.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:03:15.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:03:15.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:03:15.00$vc4f8/vblo=1,632.99 2006.280.08:03:15.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.08:03:15.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.08:03:15.00#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:15.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:03:15.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:03:15.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:03:15.00#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:03:15.00#ibcon#first serial, iclass 11, count 0 2006.280.08:03:15.00#ibcon#enter sib2, iclass 11, count 0 2006.280.08:03:15.00#ibcon#flushed, iclass 11, count 0 2006.280.08:03:15.00#ibcon#about to write, iclass 11, count 0 2006.280.08:03:15.00#ibcon#wrote, iclass 11, count 0 2006.280.08:03:15.00#ibcon#about to read 3, iclass 11, count 0 2006.280.08:03:15.02#ibcon#read 3, iclass 11, count 0 2006.280.08:03:15.03#ibcon#about to read 4, iclass 11, count 0 2006.280.08:03:15.03#ibcon#read 4, iclass 11, count 0 2006.280.08:03:15.03#ibcon#about to read 5, iclass 11, count 0 2006.280.08:03:15.03#ibcon#read 5, iclass 11, count 0 2006.280.08:03:15.03#ibcon#about to read 6, iclass 11, count 0 2006.280.08:03:15.03#ibcon#read 6, iclass 11, count 0 2006.280.08:03:15.03#ibcon#end of sib2, iclass 11, count 0 2006.280.08:03:15.03#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:03:15.03#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:03:15.03#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:03:15.03#ibcon#*before write, iclass 11, count 0 2006.280.08:03:15.03#ibcon#enter sib2, iclass 11, count 0 2006.280.08:03:15.03#ibcon#flushed, iclass 11, count 0 2006.280.08:03:15.03#ibcon#about to write, iclass 11, count 0 2006.280.08:03:15.03#ibcon#wrote, iclass 11, count 0 2006.280.08:03:15.03#ibcon#about to read 3, iclass 11, count 0 2006.280.08:03:15.07#ibcon#read 3, iclass 11, count 0 2006.280.08:03:15.07#ibcon#about to read 4, iclass 11, count 0 2006.280.08:03:15.07#ibcon#read 4, iclass 11, count 0 2006.280.08:03:15.07#ibcon#about to read 5, iclass 11, count 0 2006.280.08:03:15.07#ibcon#read 5, iclass 11, count 0 2006.280.08:03:15.07#ibcon#about to read 6, iclass 11, count 0 2006.280.08:03:15.07#ibcon#read 6, iclass 11, count 0 2006.280.08:03:15.07#ibcon#end of sib2, iclass 11, count 0 2006.280.08:03:15.07#ibcon#*after write, iclass 11, count 0 2006.280.08:03:15.07#ibcon#*before return 0, iclass 11, count 0 2006.280.08:03:15.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:03:15.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:03:15.07#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:03:15.07#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:03:15.07$vc4f8/vb=1,4 2006.280.08:03:15.07#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.08:03:15.07#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.08:03:15.07#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:15.07#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:03:15.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:03:15.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:03:15.07#ibcon#enter wrdev, iclass 13, count 2 2006.280.08:03:15.07#ibcon#first serial, iclass 13, count 2 2006.280.08:03:15.07#ibcon#enter sib2, iclass 13, count 2 2006.280.08:03:15.07#ibcon#flushed, iclass 13, count 2 2006.280.08:03:15.07#ibcon#about to write, iclass 13, count 2 2006.280.08:03:15.07#ibcon#wrote, iclass 13, count 2 2006.280.08:03:15.07#ibcon#about to read 3, iclass 13, count 2 2006.280.08:03:15.09#ibcon#read 3, iclass 13, count 2 2006.280.08:03:15.09#ibcon#about to read 4, iclass 13, count 2 2006.280.08:03:15.09#ibcon#read 4, iclass 13, count 2 2006.280.08:03:15.09#ibcon#about to read 5, iclass 13, count 2 2006.280.08:03:15.09#ibcon#read 5, iclass 13, count 2 2006.280.08:03:15.09#ibcon#about to read 6, iclass 13, count 2 2006.280.08:03:15.09#ibcon#read 6, iclass 13, count 2 2006.280.08:03:15.09#ibcon#end of sib2, iclass 13, count 2 2006.280.08:03:15.09#ibcon#*mode == 0, iclass 13, count 2 2006.280.08:03:15.09#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.08:03:15.09#ibcon#[27=AT01-04\r\n] 2006.280.08:03:15.09#ibcon#*before write, iclass 13, count 2 2006.280.08:03:15.09#ibcon#enter sib2, iclass 13, count 2 2006.280.08:03:15.09#ibcon#flushed, iclass 13, count 2 2006.280.08:03:15.09#ibcon#about to write, iclass 13, count 2 2006.280.08:03:15.09#ibcon#wrote, iclass 13, count 2 2006.280.08:03:15.09#ibcon#about to read 3, iclass 13, count 2 2006.280.08:03:15.12#ibcon#read 3, iclass 13, count 2 2006.280.08:03:15.12#ibcon#about to read 4, iclass 13, count 2 2006.280.08:03:15.12#ibcon#read 4, iclass 13, count 2 2006.280.08:03:15.12#ibcon#about to read 5, iclass 13, count 2 2006.280.08:03:15.12#ibcon#read 5, iclass 13, count 2 2006.280.08:03:15.12#ibcon#about to read 6, iclass 13, count 2 2006.280.08:03:15.12#ibcon#read 6, iclass 13, count 2 2006.280.08:03:15.12#ibcon#end of sib2, iclass 13, count 2 2006.280.08:03:15.12#ibcon#*after write, iclass 13, count 2 2006.280.08:03:15.12#ibcon#*before return 0, iclass 13, count 2 2006.280.08:03:15.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:03:15.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:03:15.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.08:03:15.12#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:15.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:03:15.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:03:15.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:03:15.24#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:03:15.24#ibcon#first serial, iclass 13, count 0 2006.280.08:03:15.24#ibcon#enter sib2, iclass 13, count 0 2006.280.08:03:15.24#ibcon#flushed, iclass 13, count 0 2006.280.08:03:15.24#ibcon#about to write, iclass 13, count 0 2006.280.08:03:15.24#ibcon#wrote, iclass 13, count 0 2006.280.08:03:15.24#ibcon#about to read 3, iclass 13, count 0 2006.280.08:03:15.26#ibcon#read 3, iclass 13, count 0 2006.280.08:03:15.26#ibcon#about to read 4, iclass 13, count 0 2006.280.08:03:15.26#ibcon#read 4, iclass 13, count 0 2006.280.08:03:15.26#ibcon#about to read 5, iclass 13, count 0 2006.280.08:03:15.26#ibcon#read 5, iclass 13, count 0 2006.280.08:03:15.26#ibcon#about to read 6, iclass 13, count 0 2006.280.08:03:15.26#ibcon#read 6, iclass 13, count 0 2006.280.08:03:15.26#ibcon#end of sib2, iclass 13, count 0 2006.280.08:03:15.26#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:03:15.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:03:15.26#ibcon#[27=USB\r\n] 2006.280.08:03:15.26#ibcon#*before write, iclass 13, count 0 2006.280.08:03:15.26#ibcon#enter sib2, iclass 13, count 0 2006.280.08:03:15.26#ibcon#flushed, iclass 13, count 0 2006.280.08:03:15.26#ibcon#about to write, iclass 13, count 0 2006.280.08:03:15.26#ibcon#wrote, iclass 13, count 0 2006.280.08:03:15.26#ibcon#about to read 3, iclass 13, count 0 2006.280.08:03:15.29#ibcon#read 3, iclass 13, count 0 2006.280.08:03:15.29#ibcon#about to read 4, iclass 13, count 0 2006.280.08:03:15.29#ibcon#read 4, iclass 13, count 0 2006.280.08:03:15.29#ibcon#about to read 5, iclass 13, count 0 2006.280.08:03:15.29#ibcon#read 5, iclass 13, count 0 2006.280.08:03:15.29#ibcon#about to read 6, iclass 13, count 0 2006.280.08:03:15.29#ibcon#read 6, iclass 13, count 0 2006.280.08:03:15.29#ibcon#end of sib2, iclass 13, count 0 2006.280.08:03:15.29#ibcon#*after write, iclass 13, count 0 2006.280.08:03:15.29#ibcon#*before return 0, iclass 13, count 0 2006.280.08:03:15.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:03:15.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:03:15.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:03:15.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:03:15.29$vc4f8/vblo=2,640.99 2006.280.08:03:15.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:03:15.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:03:15.29#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:15.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:15.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:15.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:15.29#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:03:15.29#ibcon#first serial, iclass 15, count 0 2006.280.08:03:15.29#ibcon#enter sib2, iclass 15, count 0 2006.280.08:03:15.29#ibcon#flushed, iclass 15, count 0 2006.280.08:03:15.29#ibcon#about to write, iclass 15, count 0 2006.280.08:03:15.29#ibcon#wrote, iclass 15, count 0 2006.280.08:03:15.29#ibcon#about to read 3, iclass 15, count 0 2006.280.08:03:15.31#ibcon#read 3, iclass 15, count 0 2006.280.08:03:15.31#ibcon#about to read 4, iclass 15, count 0 2006.280.08:03:15.31#ibcon#read 4, iclass 15, count 0 2006.280.08:03:15.31#ibcon#about to read 5, iclass 15, count 0 2006.280.08:03:15.31#ibcon#read 5, iclass 15, count 0 2006.280.08:03:15.31#ibcon#about to read 6, iclass 15, count 0 2006.280.08:03:15.31#ibcon#read 6, iclass 15, count 0 2006.280.08:03:15.31#ibcon#end of sib2, iclass 15, count 0 2006.280.08:03:15.31#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:03:15.31#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:03:15.31#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:03:15.31#ibcon#*before write, iclass 15, count 0 2006.280.08:03:15.31#ibcon#enter sib2, iclass 15, count 0 2006.280.08:03:15.31#ibcon#flushed, iclass 15, count 0 2006.280.08:03:15.31#ibcon#about to write, iclass 15, count 0 2006.280.08:03:15.31#ibcon#wrote, iclass 15, count 0 2006.280.08:03:15.31#ibcon#about to read 3, iclass 15, count 0 2006.280.08:03:15.35#ibcon#read 3, iclass 15, count 0 2006.280.08:03:15.35#ibcon#about to read 4, iclass 15, count 0 2006.280.08:03:15.35#ibcon#read 4, iclass 15, count 0 2006.280.08:03:15.35#ibcon#about to read 5, iclass 15, count 0 2006.280.08:03:15.35#ibcon#read 5, iclass 15, count 0 2006.280.08:03:15.35#ibcon#about to read 6, iclass 15, count 0 2006.280.08:03:15.35#ibcon#read 6, iclass 15, count 0 2006.280.08:03:15.35#ibcon#end of sib2, iclass 15, count 0 2006.280.08:03:15.35#ibcon#*after write, iclass 15, count 0 2006.280.08:03:15.35#ibcon#*before return 0, iclass 15, count 0 2006.280.08:03:15.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:15.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:03:15.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:03:15.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:03:15.35$vc4f8/vb=2,5 2006.280.08:03:15.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:03:15.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:03:15.36#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:15.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:15.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:15.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:15.42#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:03:15.42#ibcon#first serial, iclass 17, count 2 2006.280.08:03:15.42#ibcon#enter sib2, iclass 17, count 2 2006.280.08:03:15.42#ibcon#flushed, iclass 17, count 2 2006.280.08:03:15.42#ibcon#about to write, iclass 17, count 2 2006.280.08:03:15.42#ibcon#wrote, iclass 17, count 2 2006.280.08:03:15.42#ibcon#about to read 3, iclass 17, count 2 2006.280.08:03:15.43#ibcon#read 3, iclass 17, count 2 2006.280.08:03:15.43#ibcon#about to read 4, iclass 17, count 2 2006.280.08:03:15.43#ibcon#read 4, iclass 17, count 2 2006.280.08:03:15.43#ibcon#about to read 5, iclass 17, count 2 2006.280.08:03:15.43#ibcon#read 5, iclass 17, count 2 2006.280.08:03:15.43#ibcon#about to read 6, iclass 17, count 2 2006.280.08:03:15.43#ibcon#read 6, iclass 17, count 2 2006.280.08:03:15.43#ibcon#end of sib2, iclass 17, count 2 2006.280.08:03:15.43#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:03:15.43#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:03:15.43#ibcon#[27=AT02-05\r\n] 2006.280.08:03:15.43#ibcon#*before write, iclass 17, count 2 2006.280.08:03:15.43#ibcon#enter sib2, iclass 17, count 2 2006.280.08:03:15.43#ibcon#flushed, iclass 17, count 2 2006.280.08:03:15.43#ibcon#about to write, iclass 17, count 2 2006.280.08:03:15.43#ibcon#wrote, iclass 17, count 2 2006.280.08:03:15.43#ibcon#about to read 3, iclass 17, count 2 2006.280.08:03:15.46#ibcon#read 3, iclass 17, count 2 2006.280.08:03:15.46#ibcon#about to read 4, iclass 17, count 2 2006.280.08:03:15.46#ibcon#read 4, iclass 17, count 2 2006.280.08:03:15.46#ibcon#about to read 5, iclass 17, count 2 2006.280.08:03:15.46#ibcon#read 5, iclass 17, count 2 2006.280.08:03:15.46#ibcon#about to read 6, iclass 17, count 2 2006.280.08:03:15.46#ibcon#read 6, iclass 17, count 2 2006.280.08:03:15.46#ibcon#end of sib2, iclass 17, count 2 2006.280.08:03:15.46#ibcon#*after write, iclass 17, count 2 2006.280.08:03:15.46#ibcon#*before return 0, iclass 17, count 2 2006.280.08:03:15.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:15.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:03:15.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:03:15.46#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:15.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:15.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:15.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:15.58#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:03:15.58#ibcon#first serial, iclass 17, count 0 2006.280.08:03:15.58#ibcon#enter sib2, iclass 17, count 0 2006.280.08:03:15.58#ibcon#flushed, iclass 17, count 0 2006.280.08:03:15.58#ibcon#about to write, iclass 17, count 0 2006.280.08:03:15.58#ibcon#wrote, iclass 17, count 0 2006.280.08:03:15.58#ibcon#about to read 3, iclass 17, count 0 2006.280.08:03:15.60#ibcon#read 3, iclass 17, count 0 2006.280.08:03:15.60#ibcon#about to read 4, iclass 17, count 0 2006.280.08:03:15.60#ibcon#read 4, iclass 17, count 0 2006.280.08:03:15.60#ibcon#about to read 5, iclass 17, count 0 2006.280.08:03:15.60#ibcon#read 5, iclass 17, count 0 2006.280.08:03:15.60#ibcon#about to read 6, iclass 17, count 0 2006.280.08:03:15.60#ibcon#read 6, iclass 17, count 0 2006.280.08:03:15.60#ibcon#end of sib2, iclass 17, count 0 2006.280.08:03:15.60#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:03:15.60#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:03:15.60#ibcon#[27=USB\r\n] 2006.280.08:03:15.60#ibcon#*before write, iclass 17, count 0 2006.280.08:03:15.60#ibcon#enter sib2, iclass 17, count 0 2006.280.08:03:15.60#ibcon#flushed, iclass 17, count 0 2006.280.08:03:15.60#ibcon#about to write, iclass 17, count 0 2006.280.08:03:15.60#ibcon#wrote, iclass 17, count 0 2006.280.08:03:15.60#ibcon#about to read 3, iclass 17, count 0 2006.280.08:03:15.63#ibcon#read 3, iclass 17, count 0 2006.280.08:03:15.63#ibcon#about to read 4, iclass 17, count 0 2006.280.08:03:15.63#ibcon#read 4, iclass 17, count 0 2006.280.08:03:15.63#ibcon#about to read 5, iclass 17, count 0 2006.280.08:03:15.63#ibcon#read 5, iclass 17, count 0 2006.280.08:03:15.64#ibcon#about to read 6, iclass 17, count 0 2006.280.08:03:15.64#ibcon#read 6, iclass 17, count 0 2006.280.08:03:15.64#ibcon#end of sib2, iclass 17, count 0 2006.280.08:03:15.64#ibcon#*after write, iclass 17, count 0 2006.280.08:03:15.64#ibcon#*before return 0, iclass 17, count 0 2006.280.08:03:15.64#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:15.64#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:03:15.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:03:15.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:03:15.64$vc4f8/vblo=3,656.99 2006.280.08:03:15.64#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:03:15.64#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:03:15.64#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:15.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:15.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:15.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:15.64#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:03:15.64#ibcon#first serial, iclass 19, count 0 2006.280.08:03:15.64#ibcon#enter sib2, iclass 19, count 0 2006.280.08:03:15.64#ibcon#flushed, iclass 19, count 0 2006.280.08:03:15.64#ibcon#about to write, iclass 19, count 0 2006.280.08:03:15.64#ibcon#wrote, iclass 19, count 0 2006.280.08:03:15.64#ibcon#about to read 3, iclass 19, count 0 2006.280.08:03:15.65#ibcon#read 3, iclass 19, count 0 2006.280.08:03:15.65#ibcon#about to read 4, iclass 19, count 0 2006.280.08:03:15.65#ibcon#read 4, iclass 19, count 0 2006.280.08:03:15.65#ibcon#about to read 5, iclass 19, count 0 2006.280.08:03:15.65#ibcon#read 5, iclass 19, count 0 2006.280.08:03:15.66#ibcon#about to read 6, iclass 19, count 0 2006.280.08:03:15.67#ibcon#read 6, iclass 19, count 0 2006.280.08:03:15.67#ibcon#end of sib2, iclass 19, count 0 2006.280.08:03:15.67#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:03:15.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:03:15.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:03:15.67#ibcon#*before write, iclass 19, count 0 2006.280.08:03:15.67#ibcon#enter sib2, iclass 19, count 0 2006.280.08:03:15.67#ibcon#flushed, iclass 19, count 0 2006.280.08:03:15.67#ibcon#about to write, iclass 19, count 0 2006.280.08:03:15.67#ibcon#wrote, iclass 19, count 0 2006.280.08:03:15.67#ibcon#about to read 3, iclass 19, count 0 2006.280.08:03:15.71#ibcon#read 3, iclass 19, count 0 2006.280.08:03:15.71#ibcon#about to read 4, iclass 19, count 0 2006.280.08:03:15.71#ibcon#read 4, iclass 19, count 0 2006.280.08:03:15.71#ibcon#about to read 5, iclass 19, count 0 2006.280.08:03:15.71#ibcon#read 5, iclass 19, count 0 2006.280.08:03:15.71#ibcon#about to read 6, iclass 19, count 0 2006.280.08:03:15.71#ibcon#read 6, iclass 19, count 0 2006.280.08:03:15.71#ibcon#end of sib2, iclass 19, count 0 2006.280.08:03:15.71#ibcon#*after write, iclass 19, count 0 2006.280.08:03:15.71#ibcon#*before return 0, iclass 19, count 0 2006.280.08:03:15.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:15.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:03:15.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:03:15.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:03:15.71$vc4f8/vb=3,4 2006.280.08:03:15.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:03:15.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:03:15.71#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:15.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:15.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:15.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:15.76#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:03:15.76#ibcon#first serial, iclass 21, count 2 2006.280.08:03:15.76#ibcon#enter sib2, iclass 21, count 2 2006.280.08:03:15.76#ibcon#flushed, iclass 21, count 2 2006.280.08:03:15.76#ibcon#about to write, iclass 21, count 2 2006.280.08:03:15.76#ibcon#wrote, iclass 21, count 2 2006.280.08:03:15.76#ibcon#about to read 3, iclass 21, count 2 2006.280.08:03:15.78#ibcon#read 3, iclass 21, count 2 2006.280.08:03:15.78#ibcon#about to read 4, iclass 21, count 2 2006.280.08:03:15.78#ibcon#read 4, iclass 21, count 2 2006.280.08:03:15.78#ibcon#about to read 5, iclass 21, count 2 2006.280.08:03:15.78#ibcon#read 5, iclass 21, count 2 2006.280.08:03:15.78#ibcon#about to read 6, iclass 21, count 2 2006.280.08:03:15.78#ibcon#read 6, iclass 21, count 2 2006.280.08:03:15.78#ibcon#end of sib2, iclass 21, count 2 2006.280.08:03:15.78#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:03:15.78#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:03:15.78#ibcon#[27=AT03-04\r\n] 2006.280.08:03:15.78#ibcon#*before write, iclass 21, count 2 2006.280.08:03:15.78#ibcon#enter sib2, iclass 21, count 2 2006.280.08:03:15.78#ibcon#flushed, iclass 21, count 2 2006.280.08:03:15.78#ibcon#about to write, iclass 21, count 2 2006.280.08:03:15.78#ibcon#wrote, iclass 21, count 2 2006.280.08:03:15.78#ibcon#about to read 3, iclass 21, count 2 2006.280.08:03:15.81#ibcon#read 3, iclass 21, count 2 2006.280.08:03:15.81#ibcon#about to read 4, iclass 21, count 2 2006.280.08:03:15.81#ibcon#read 4, iclass 21, count 2 2006.280.08:03:15.81#ibcon#about to read 5, iclass 21, count 2 2006.280.08:03:15.81#ibcon#read 5, iclass 21, count 2 2006.280.08:03:15.81#ibcon#about to read 6, iclass 21, count 2 2006.280.08:03:15.81#ibcon#read 6, iclass 21, count 2 2006.280.08:03:15.81#ibcon#end of sib2, iclass 21, count 2 2006.280.08:03:15.81#ibcon#*after write, iclass 21, count 2 2006.280.08:03:15.81#ibcon#*before return 0, iclass 21, count 2 2006.280.08:03:15.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:15.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:03:15.81#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:03:15.81#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:15.81#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:15.93#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:15.93#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:15.93#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:03:15.93#ibcon#first serial, iclass 21, count 0 2006.280.08:03:15.93#ibcon#enter sib2, iclass 21, count 0 2006.280.08:03:15.93#ibcon#flushed, iclass 21, count 0 2006.280.08:03:15.93#ibcon#about to write, iclass 21, count 0 2006.280.08:03:15.93#ibcon#wrote, iclass 21, count 0 2006.280.08:03:15.93#ibcon#about to read 3, iclass 21, count 0 2006.280.08:03:15.95#ibcon#read 3, iclass 21, count 0 2006.280.08:03:15.95#ibcon#about to read 4, iclass 21, count 0 2006.280.08:03:15.95#ibcon#read 4, iclass 21, count 0 2006.280.08:03:15.95#ibcon#about to read 5, iclass 21, count 0 2006.280.08:03:15.95#ibcon#read 5, iclass 21, count 0 2006.280.08:03:15.95#ibcon#about to read 6, iclass 21, count 0 2006.280.08:03:15.95#ibcon#read 6, iclass 21, count 0 2006.280.08:03:15.95#ibcon#end of sib2, iclass 21, count 0 2006.280.08:03:15.95#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:03:15.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:03:15.95#ibcon#[27=USB\r\n] 2006.280.08:03:15.95#ibcon#*before write, iclass 21, count 0 2006.280.08:03:15.95#ibcon#enter sib2, iclass 21, count 0 2006.280.08:03:15.95#ibcon#flushed, iclass 21, count 0 2006.280.08:03:15.95#ibcon#about to write, iclass 21, count 0 2006.280.08:03:15.95#ibcon#wrote, iclass 21, count 0 2006.280.08:03:15.95#ibcon#about to read 3, iclass 21, count 0 2006.280.08:03:15.98#ibcon#read 3, iclass 21, count 0 2006.280.08:03:15.98#ibcon#about to read 4, iclass 21, count 0 2006.280.08:03:15.98#ibcon#read 4, iclass 21, count 0 2006.280.08:03:15.98#ibcon#about to read 5, iclass 21, count 0 2006.280.08:03:15.98#ibcon#read 5, iclass 21, count 0 2006.280.08:03:15.98#ibcon#about to read 6, iclass 21, count 0 2006.280.08:03:15.98#ibcon#read 6, iclass 21, count 0 2006.280.08:03:15.98#ibcon#end of sib2, iclass 21, count 0 2006.280.08:03:15.98#ibcon#*after write, iclass 21, count 0 2006.280.08:03:15.98#ibcon#*before return 0, iclass 21, count 0 2006.280.08:03:15.98#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:15.98#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:03:15.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:03:15.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:03:15.98$vc4f8/vblo=4,712.99 2006.280.08:03:15.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:03:15.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:03:15.98#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:15.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:15.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:15.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:15.98#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:03:15.98#ibcon#first serial, iclass 23, count 0 2006.280.08:03:15.98#ibcon#enter sib2, iclass 23, count 0 2006.280.08:03:15.98#ibcon#flushed, iclass 23, count 0 2006.280.08:03:15.98#ibcon#about to write, iclass 23, count 0 2006.280.08:03:15.98#ibcon#wrote, iclass 23, count 0 2006.280.08:03:15.98#ibcon#about to read 3, iclass 23, count 0 2006.280.08:03:16.00#ibcon#read 3, iclass 23, count 0 2006.280.08:03:16.00#ibcon#about to read 4, iclass 23, count 0 2006.280.08:03:16.00#ibcon#read 4, iclass 23, count 0 2006.280.08:03:16.00#ibcon#about to read 5, iclass 23, count 0 2006.280.08:03:16.00#ibcon#read 5, iclass 23, count 0 2006.280.08:03:16.00#ibcon#about to read 6, iclass 23, count 0 2006.280.08:03:16.00#ibcon#read 6, iclass 23, count 0 2006.280.08:03:16.00#ibcon#end of sib2, iclass 23, count 0 2006.280.08:03:16.00#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:03:16.00#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:03:16.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:03:16.00#ibcon#*before write, iclass 23, count 0 2006.280.08:03:16.00#ibcon#enter sib2, iclass 23, count 0 2006.280.08:03:16.00#ibcon#flushed, iclass 23, count 0 2006.280.08:03:16.00#ibcon#about to write, iclass 23, count 0 2006.280.08:03:16.00#ibcon#wrote, iclass 23, count 0 2006.280.08:03:16.00#ibcon#about to read 3, iclass 23, count 0 2006.280.08:03:16.04#ibcon#read 3, iclass 23, count 0 2006.280.08:03:16.04#ibcon#about to read 4, iclass 23, count 0 2006.280.08:03:16.04#ibcon#read 4, iclass 23, count 0 2006.280.08:03:16.04#ibcon#about to read 5, iclass 23, count 0 2006.280.08:03:16.04#ibcon#read 5, iclass 23, count 0 2006.280.08:03:16.04#ibcon#about to read 6, iclass 23, count 0 2006.280.08:03:16.04#ibcon#read 6, iclass 23, count 0 2006.280.08:03:16.04#ibcon#end of sib2, iclass 23, count 0 2006.280.08:03:16.04#ibcon#*after write, iclass 23, count 0 2006.280.08:03:16.04#ibcon#*before return 0, iclass 23, count 0 2006.280.08:03:16.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:16.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:03:16.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:03:16.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:03:16.04$vc4f8/vb=4,4 2006.280.08:03:16.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.08:03:16.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.08:03:16.04#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:16.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:16.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:16.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:16.10#ibcon#enter wrdev, iclass 25, count 2 2006.280.08:03:16.10#ibcon#first serial, iclass 25, count 2 2006.280.08:03:16.10#ibcon#enter sib2, iclass 25, count 2 2006.280.08:03:16.10#ibcon#flushed, iclass 25, count 2 2006.280.08:03:16.10#ibcon#about to write, iclass 25, count 2 2006.280.08:03:16.10#ibcon#wrote, iclass 25, count 2 2006.280.08:03:16.10#ibcon#about to read 3, iclass 25, count 2 2006.280.08:03:16.12#ibcon#read 3, iclass 25, count 2 2006.280.08:03:16.12#ibcon#about to read 4, iclass 25, count 2 2006.280.08:03:16.12#ibcon#read 4, iclass 25, count 2 2006.280.08:03:16.12#ibcon#about to read 5, iclass 25, count 2 2006.280.08:03:16.12#ibcon#read 5, iclass 25, count 2 2006.280.08:03:16.12#ibcon#about to read 6, iclass 25, count 2 2006.280.08:03:16.12#ibcon#read 6, iclass 25, count 2 2006.280.08:03:16.12#ibcon#end of sib2, iclass 25, count 2 2006.280.08:03:16.12#ibcon#*mode == 0, iclass 25, count 2 2006.280.08:03:16.12#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.08:03:16.12#ibcon#[27=AT04-04\r\n] 2006.280.08:03:16.12#ibcon#*before write, iclass 25, count 2 2006.280.08:03:16.12#ibcon#enter sib2, iclass 25, count 2 2006.280.08:03:16.12#ibcon#flushed, iclass 25, count 2 2006.280.08:03:16.12#ibcon#about to write, iclass 25, count 2 2006.280.08:03:16.12#ibcon#wrote, iclass 25, count 2 2006.280.08:03:16.12#ibcon#about to read 3, iclass 25, count 2 2006.280.08:03:16.15#ibcon#read 3, iclass 25, count 2 2006.280.08:03:16.15#ibcon#about to read 4, iclass 25, count 2 2006.280.08:03:16.15#ibcon#read 4, iclass 25, count 2 2006.280.08:03:16.15#ibcon#about to read 5, iclass 25, count 2 2006.280.08:03:16.15#ibcon#read 5, iclass 25, count 2 2006.280.08:03:16.15#ibcon#about to read 6, iclass 25, count 2 2006.280.08:03:16.15#ibcon#read 6, iclass 25, count 2 2006.280.08:03:16.15#ibcon#end of sib2, iclass 25, count 2 2006.280.08:03:16.15#ibcon#*after write, iclass 25, count 2 2006.280.08:03:16.15#ibcon#*before return 0, iclass 25, count 2 2006.280.08:03:16.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:16.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:03:16.15#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.08:03:16.15#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:16.15#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:16.27#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:16.27#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:16.27#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:03:16.27#ibcon#first serial, iclass 25, count 0 2006.280.08:03:16.27#ibcon#enter sib2, iclass 25, count 0 2006.280.08:03:16.27#ibcon#flushed, iclass 25, count 0 2006.280.08:03:16.27#ibcon#about to write, iclass 25, count 0 2006.280.08:03:16.27#ibcon#wrote, iclass 25, count 0 2006.280.08:03:16.27#ibcon#about to read 3, iclass 25, count 0 2006.280.08:03:16.29#ibcon#read 3, iclass 25, count 0 2006.280.08:03:16.29#ibcon#about to read 4, iclass 25, count 0 2006.280.08:03:16.29#ibcon#read 4, iclass 25, count 0 2006.280.08:03:16.29#ibcon#about to read 5, iclass 25, count 0 2006.280.08:03:16.29#ibcon#read 5, iclass 25, count 0 2006.280.08:03:16.29#ibcon#about to read 6, iclass 25, count 0 2006.280.08:03:16.29#ibcon#read 6, iclass 25, count 0 2006.280.08:03:16.29#ibcon#end of sib2, iclass 25, count 0 2006.280.08:03:16.29#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:03:16.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:03:16.29#ibcon#[27=USB\r\n] 2006.280.08:03:16.29#ibcon#*before write, iclass 25, count 0 2006.280.08:03:16.29#ibcon#enter sib2, iclass 25, count 0 2006.280.08:03:16.29#ibcon#flushed, iclass 25, count 0 2006.280.08:03:16.29#ibcon#about to write, iclass 25, count 0 2006.280.08:03:16.29#ibcon#wrote, iclass 25, count 0 2006.280.08:03:16.29#ibcon#about to read 3, iclass 25, count 0 2006.280.08:03:16.32#ibcon#read 3, iclass 25, count 0 2006.280.08:03:16.32#ibcon#about to read 4, iclass 25, count 0 2006.280.08:03:16.32#ibcon#read 4, iclass 25, count 0 2006.280.08:03:16.32#ibcon#about to read 5, iclass 25, count 0 2006.280.08:03:16.32#ibcon#read 5, iclass 25, count 0 2006.280.08:03:16.32#ibcon#about to read 6, iclass 25, count 0 2006.280.08:03:16.32#ibcon#read 6, iclass 25, count 0 2006.280.08:03:16.32#ibcon#end of sib2, iclass 25, count 0 2006.280.08:03:16.32#ibcon#*after write, iclass 25, count 0 2006.280.08:03:16.32#ibcon#*before return 0, iclass 25, count 0 2006.280.08:03:16.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:16.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:03:16.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:03:16.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:03:16.32$vc4f8/vblo=5,744.99 2006.280.08:03:16.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.08:03:16.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.08:03:16.32#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:16.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:16.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:16.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:16.32#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:03:16.32#ibcon#first serial, iclass 27, count 0 2006.280.08:03:16.32#ibcon#enter sib2, iclass 27, count 0 2006.280.08:03:16.32#ibcon#flushed, iclass 27, count 0 2006.280.08:03:16.32#ibcon#about to write, iclass 27, count 0 2006.280.08:03:16.32#ibcon#wrote, iclass 27, count 0 2006.280.08:03:16.32#ibcon#about to read 3, iclass 27, count 0 2006.280.08:03:16.34#ibcon#read 3, iclass 27, count 0 2006.280.08:03:16.34#ibcon#about to read 4, iclass 27, count 0 2006.280.08:03:16.34#ibcon#read 4, iclass 27, count 0 2006.280.08:03:16.34#ibcon#about to read 5, iclass 27, count 0 2006.280.08:03:16.34#ibcon#read 5, iclass 27, count 0 2006.280.08:03:16.34#ibcon#about to read 6, iclass 27, count 0 2006.280.08:03:16.34#ibcon#read 6, iclass 27, count 0 2006.280.08:03:16.34#ibcon#end of sib2, iclass 27, count 0 2006.280.08:03:16.34#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:03:16.34#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:03:16.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:03:16.34#ibcon#*before write, iclass 27, count 0 2006.280.08:03:16.34#ibcon#enter sib2, iclass 27, count 0 2006.280.08:03:16.34#ibcon#flushed, iclass 27, count 0 2006.280.08:03:16.34#ibcon#about to write, iclass 27, count 0 2006.280.08:03:16.34#ibcon#wrote, iclass 27, count 0 2006.280.08:03:16.34#ibcon#about to read 3, iclass 27, count 0 2006.280.08:03:16.38#ibcon#read 3, iclass 27, count 0 2006.280.08:03:16.38#ibcon#about to read 4, iclass 27, count 0 2006.280.08:03:16.38#ibcon#read 4, iclass 27, count 0 2006.280.08:03:16.38#ibcon#about to read 5, iclass 27, count 0 2006.280.08:03:16.38#ibcon#read 5, iclass 27, count 0 2006.280.08:03:16.38#ibcon#about to read 6, iclass 27, count 0 2006.280.08:03:16.38#ibcon#read 6, iclass 27, count 0 2006.280.08:03:16.38#ibcon#end of sib2, iclass 27, count 0 2006.280.08:03:16.38#ibcon#*after write, iclass 27, count 0 2006.280.08:03:16.38#ibcon#*before return 0, iclass 27, count 0 2006.280.08:03:16.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:16.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:03:16.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:03:16.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:03:16.38$vc4f8/vb=5,4 2006.280.08:03:16.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.08:03:16.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.08:03:16.38#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:16.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:16.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:16.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:16.44#ibcon#enter wrdev, iclass 29, count 2 2006.280.08:03:16.44#ibcon#first serial, iclass 29, count 2 2006.280.08:03:16.44#ibcon#enter sib2, iclass 29, count 2 2006.280.08:03:16.44#ibcon#flushed, iclass 29, count 2 2006.280.08:03:16.44#ibcon#about to write, iclass 29, count 2 2006.280.08:03:16.44#ibcon#wrote, iclass 29, count 2 2006.280.08:03:16.44#ibcon#about to read 3, iclass 29, count 2 2006.280.08:03:16.46#ibcon#read 3, iclass 29, count 2 2006.280.08:03:16.46#ibcon#about to read 4, iclass 29, count 2 2006.280.08:03:16.46#ibcon#read 4, iclass 29, count 2 2006.280.08:03:16.46#ibcon#about to read 5, iclass 29, count 2 2006.280.08:03:16.46#ibcon#read 5, iclass 29, count 2 2006.280.08:03:16.46#ibcon#about to read 6, iclass 29, count 2 2006.280.08:03:16.46#ibcon#read 6, iclass 29, count 2 2006.280.08:03:16.46#ibcon#end of sib2, iclass 29, count 2 2006.280.08:03:16.46#ibcon#*mode == 0, iclass 29, count 2 2006.280.08:03:16.46#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.08:03:16.46#ibcon#[27=AT05-04\r\n] 2006.280.08:03:16.46#ibcon#*before write, iclass 29, count 2 2006.280.08:03:16.46#ibcon#enter sib2, iclass 29, count 2 2006.280.08:03:16.46#ibcon#flushed, iclass 29, count 2 2006.280.08:03:16.46#ibcon#about to write, iclass 29, count 2 2006.280.08:03:16.46#ibcon#wrote, iclass 29, count 2 2006.280.08:03:16.46#ibcon#about to read 3, iclass 29, count 2 2006.280.08:03:16.50#ibcon#read 3, iclass 29, count 2 2006.280.08:03:16.50#ibcon#about to read 4, iclass 29, count 2 2006.280.08:03:16.50#ibcon#read 4, iclass 29, count 2 2006.280.08:03:16.50#ibcon#about to read 5, iclass 29, count 2 2006.280.08:03:16.50#ibcon#read 5, iclass 29, count 2 2006.280.08:03:16.50#ibcon#about to read 6, iclass 29, count 2 2006.280.08:03:16.50#ibcon#read 6, iclass 29, count 2 2006.280.08:03:16.50#ibcon#end of sib2, iclass 29, count 2 2006.280.08:03:16.50#ibcon#*after write, iclass 29, count 2 2006.280.08:03:16.50#ibcon#*before return 0, iclass 29, count 2 2006.280.08:03:16.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:16.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:03:16.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.08:03:16.50#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:16.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:16.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:16.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:16.62#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:03:16.62#ibcon#first serial, iclass 29, count 0 2006.280.08:03:16.62#ibcon#enter sib2, iclass 29, count 0 2006.280.08:03:16.62#ibcon#flushed, iclass 29, count 0 2006.280.08:03:16.62#ibcon#about to write, iclass 29, count 0 2006.280.08:03:16.62#ibcon#wrote, iclass 29, count 0 2006.280.08:03:16.62#ibcon#about to read 3, iclass 29, count 0 2006.280.08:03:16.64#ibcon#read 3, iclass 29, count 0 2006.280.08:03:16.64#ibcon#about to read 4, iclass 29, count 0 2006.280.08:03:16.64#ibcon#read 4, iclass 29, count 0 2006.280.08:03:16.64#ibcon#about to read 5, iclass 29, count 0 2006.280.08:03:16.64#ibcon#read 5, iclass 29, count 0 2006.280.08:03:16.64#ibcon#about to read 6, iclass 29, count 0 2006.280.08:03:16.64#ibcon#read 6, iclass 29, count 0 2006.280.08:03:16.64#ibcon#end of sib2, iclass 29, count 0 2006.280.08:03:16.64#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:03:16.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:03:16.64#ibcon#[27=USB\r\n] 2006.280.08:03:16.64#ibcon#*before write, iclass 29, count 0 2006.280.08:03:16.64#ibcon#enter sib2, iclass 29, count 0 2006.280.08:03:16.64#ibcon#flushed, iclass 29, count 0 2006.280.08:03:16.64#ibcon#about to write, iclass 29, count 0 2006.280.08:03:16.64#ibcon#wrote, iclass 29, count 0 2006.280.08:03:16.64#ibcon#about to read 3, iclass 29, count 0 2006.280.08:03:16.67#ibcon#read 3, iclass 29, count 0 2006.280.08:03:16.67#ibcon#about to read 4, iclass 29, count 0 2006.280.08:03:16.67#ibcon#read 4, iclass 29, count 0 2006.280.08:03:16.67#ibcon#about to read 5, iclass 29, count 0 2006.280.08:03:16.67#ibcon#read 5, iclass 29, count 0 2006.280.08:03:16.67#ibcon#about to read 6, iclass 29, count 0 2006.280.08:03:16.67#ibcon#read 6, iclass 29, count 0 2006.280.08:03:16.67#ibcon#end of sib2, iclass 29, count 0 2006.280.08:03:16.67#ibcon#*after write, iclass 29, count 0 2006.280.08:03:16.67#ibcon#*before return 0, iclass 29, count 0 2006.280.08:03:16.67#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:16.67#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:03:16.67#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:03:16.67#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:03:16.67$vc4f8/vblo=6,752.99 2006.280.08:03:16.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.08:03:16.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.08:03:16.67#ibcon#ireg 17 cls_cnt 0 2006.280.08:03:16.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:16.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:16.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:16.67#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:03:16.67#ibcon#first serial, iclass 31, count 0 2006.280.08:03:16.67#ibcon#enter sib2, iclass 31, count 0 2006.280.08:03:16.67#ibcon#flushed, iclass 31, count 0 2006.280.08:03:16.67#ibcon#about to write, iclass 31, count 0 2006.280.08:03:16.67#ibcon#wrote, iclass 31, count 0 2006.280.08:03:16.67#ibcon#about to read 3, iclass 31, count 0 2006.280.08:03:16.69#ibcon#read 3, iclass 31, count 0 2006.280.08:03:16.69#ibcon#about to read 4, iclass 31, count 0 2006.280.08:03:16.69#ibcon#read 4, iclass 31, count 0 2006.280.08:03:16.69#ibcon#about to read 5, iclass 31, count 0 2006.280.08:03:16.69#ibcon#read 5, iclass 31, count 0 2006.280.08:03:16.69#ibcon#about to read 6, iclass 31, count 0 2006.280.08:03:16.69#ibcon#read 6, iclass 31, count 0 2006.280.08:03:16.69#ibcon#end of sib2, iclass 31, count 0 2006.280.08:03:16.69#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:03:16.69#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:03:16.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:03:16.69#ibcon#*before write, iclass 31, count 0 2006.280.08:03:16.69#ibcon#enter sib2, iclass 31, count 0 2006.280.08:03:16.69#ibcon#flushed, iclass 31, count 0 2006.280.08:03:16.69#ibcon#about to write, iclass 31, count 0 2006.280.08:03:16.69#ibcon#wrote, iclass 31, count 0 2006.280.08:03:16.69#ibcon#about to read 3, iclass 31, count 0 2006.280.08:03:16.73#ibcon#read 3, iclass 31, count 0 2006.280.08:03:16.73#ibcon#about to read 4, iclass 31, count 0 2006.280.08:03:16.73#ibcon#read 4, iclass 31, count 0 2006.280.08:03:16.73#ibcon#about to read 5, iclass 31, count 0 2006.280.08:03:16.73#ibcon#read 5, iclass 31, count 0 2006.280.08:03:16.73#ibcon#about to read 6, iclass 31, count 0 2006.280.08:03:16.73#ibcon#read 6, iclass 31, count 0 2006.280.08:03:16.73#ibcon#end of sib2, iclass 31, count 0 2006.280.08:03:16.73#ibcon#*after write, iclass 31, count 0 2006.280.08:03:16.73#ibcon#*before return 0, iclass 31, count 0 2006.280.08:03:16.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:16.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:03:16.73#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:03:16.73#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:03:16.73$vc4f8/vb=6,4 2006.280.08:03:16.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.08:03:16.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.08:03:16.75#ibcon#ireg 11 cls_cnt 2 2006.280.08:03:16.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:16.78#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:16.78#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:16.78#ibcon#enter wrdev, iclass 33, count 2 2006.280.08:03:16.78#ibcon#first serial, iclass 33, count 2 2006.280.08:03:16.78#ibcon#enter sib2, iclass 33, count 2 2006.280.08:03:16.78#ibcon#flushed, iclass 33, count 2 2006.280.08:03:16.78#ibcon#about to write, iclass 33, count 2 2006.280.08:03:16.78#ibcon#wrote, iclass 33, count 2 2006.280.08:03:16.78#ibcon#about to read 3, iclass 33, count 2 2006.280.08:03:16.80#ibcon#read 3, iclass 33, count 2 2006.280.08:03:16.80#ibcon#about to read 4, iclass 33, count 2 2006.280.08:03:16.80#ibcon#read 4, iclass 33, count 2 2006.280.08:03:16.80#ibcon#about to read 5, iclass 33, count 2 2006.280.08:03:16.80#ibcon#read 5, iclass 33, count 2 2006.280.08:03:16.80#ibcon#about to read 6, iclass 33, count 2 2006.280.08:03:16.80#ibcon#read 6, iclass 33, count 2 2006.280.08:03:16.80#ibcon#end of sib2, iclass 33, count 2 2006.280.08:03:16.80#ibcon#*mode == 0, iclass 33, count 2 2006.280.08:03:16.80#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.08:03:16.80#ibcon#[27=AT06-04\r\n] 2006.280.08:03:16.80#ibcon#*before write, iclass 33, count 2 2006.280.08:03:16.80#ibcon#enter sib2, iclass 33, count 2 2006.280.08:03:16.80#ibcon#flushed, iclass 33, count 2 2006.280.08:03:16.80#ibcon#about to write, iclass 33, count 2 2006.280.08:03:16.80#ibcon#wrote, iclass 33, count 2 2006.280.08:03:16.80#ibcon#about to read 3, iclass 33, count 2 2006.280.08:03:16.83#ibcon#read 3, iclass 33, count 2 2006.280.08:03:16.83#ibcon#about to read 4, iclass 33, count 2 2006.280.08:03:16.83#ibcon#read 4, iclass 33, count 2 2006.280.08:03:16.83#ibcon#about to read 5, iclass 33, count 2 2006.280.08:03:16.83#ibcon#read 5, iclass 33, count 2 2006.280.08:03:16.83#ibcon#about to read 6, iclass 33, count 2 2006.280.08:03:16.83#ibcon#read 6, iclass 33, count 2 2006.280.08:03:16.83#ibcon#end of sib2, iclass 33, count 2 2006.280.08:03:16.83#ibcon#*after write, iclass 33, count 2 2006.280.08:03:16.83#ibcon#*before return 0, iclass 33, count 2 2006.280.08:03:16.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:16.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:03:16.83#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.08:03:16.83#ibcon#ireg 7 cls_cnt 0 2006.280.08:03:16.83#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:16.95#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:16.95#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:16.95#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:03:16.95#ibcon#first serial, iclass 33, count 0 2006.280.08:03:16.95#ibcon#enter sib2, iclass 33, count 0 2006.280.08:03:16.95#ibcon#flushed, iclass 33, count 0 2006.280.08:03:16.95#ibcon#about to write, iclass 33, count 0 2006.280.08:03:16.95#ibcon#wrote, iclass 33, count 0 2006.280.08:03:16.95#ibcon#about to read 3, iclass 33, count 0 2006.280.08:03:16.97#ibcon#read 3, iclass 33, count 0 2006.280.08:03:16.97#ibcon#about to read 4, iclass 33, count 0 2006.280.08:03:16.97#ibcon#read 4, iclass 33, count 0 2006.280.08:03:16.97#ibcon#about to read 5, iclass 33, count 0 2006.280.08:03:16.97#ibcon#read 5, iclass 33, count 0 2006.280.08:03:16.97#ibcon#about to read 6, iclass 33, count 0 2006.280.08:03:16.97#ibcon#read 6, iclass 33, count 0 2006.280.08:03:16.97#ibcon#end of sib2, iclass 33, count 0 2006.280.08:03:16.97#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:03:16.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:03:16.97#ibcon#[27=USB\r\n] 2006.280.08:03:16.97#ibcon#*before write, iclass 33, count 0 2006.280.08:03:16.97#ibcon#enter sib2, iclass 33, count 0 2006.280.08:03:16.97#ibcon#flushed, iclass 33, count 0 2006.280.08:03:16.97#ibcon#about to write, iclass 33, count 0 2006.280.08:03:16.97#ibcon#wrote, iclass 33, count 0 2006.280.08:03:16.97#ibcon#about to read 3, iclass 33, count 0 2006.280.08:03:17.00#ibcon#read 3, iclass 33, count 0 2006.280.08:03:17.00#ibcon#about to read 4, iclass 33, count 0 2006.280.08:03:17.00#ibcon#read 4, iclass 33, count 0 2006.280.08:03:17.00#ibcon#about to read 5, iclass 33, count 0 2006.280.08:03:17.00#ibcon#read 5, iclass 33, count 0 2006.280.08:03:17.00#ibcon#about to read 6, iclass 33, count 0 2006.280.08:03:17.00#ibcon#read 6, iclass 33, count 0 2006.280.08:03:17.00#ibcon#end of sib2, iclass 33, count 0 2006.280.08:03:17.00#ibcon#*after write, iclass 33, count 0 2006.280.08:03:17.00#ibcon#*before return 0, iclass 33, count 0 2006.280.08:03:17.00#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:17.00#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:03:17.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:03:17.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:03:17.00$vc4f8/vabw=wide 2006.280.08:03:17.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.08:03:17.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.08:03:17.00#ibcon#ireg 8 cls_cnt 0 2006.280.08:03:17.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:17.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:17.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:17.00#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:03:17.00#ibcon#first serial, iclass 35, count 0 2006.280.08:03:17.00#ibcon#enter sib2, iclass 35, count 0 2006.280.08:03:17.00#ibcon#flushed, iclass 35, count 0 2006.280.08:03:17.00#ibcon#about to write, iclass 35, count 0 2006.280.08:03:17.00#ibcon#wrote, iclass 35, count 0 2006.280.08:03:17.00#ibcon#about to read 3, iclass 35, count 0 2006.280.08:03:17.02#ibcon#read 3, iclass 35, count 0 2006.280.08:03:17.02#ibcon#about to read 4, iclass 35, count 0 2006.280.08:03:17.02#ibcon#read 4, iclass 35, count 0 2006.280.08:03:17.02#ibcon#about to read 5, iclass 35, count 0 2006.280.08:03:17.02#ibcon#read 5, iclass 35, count 0 2006.280.08:03:17.02#ibcon#about to read 6, iclass 35, count 0 2006.280.08:03:17.02#ibcon#read 6, iclass 35, count 0 2006.280.08:03:17.02#ibcon#end of sib2, iclass 35, count 0 2006.280.08:03:17.02#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:03:17.02#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:03:17.02#ibcon#[25=BW32\r\n] 2006.280.08:03:17.02#ibcon#*before write, iclass 35, count 0 2006.280.08:03:17.02#ibcon#enter sib2, iclass 35, count 0 2006.280.08:03:17.02#ibcon#flushed, iclass 35, count 0 2006.280.08:03:17.02#ibcon#about to write, iclass 35, count 0 2006.280.08:03:17.02#ibcon#wrote, iclass 35, count 0 2006.280.08:03:17.02#ibcon#about to read 3, iclass 35, count 0 2006.280.08:03:17.05#ibcon#read 3, iclass 35, count 0 2006.280.08:03:17.05#ibcon#about to read 4, iclass 35, count 0 2006.280.08:03:17.05#ibcon#read 4, iclass 35, count 0 2006.280.08:03:17.05#ibcon#about to read 5, iclass 35, count 0 2006.280.08:03:17.05#ibcon#read 5, iclass 35, count 0 2006.280.08:03:17.05#ibcon#about to read 6, iclass 35, count 0 2006.280.08:03:17.05#ibcon#read 6, iclass 35, count 0 2006.280.08:03:17.05#ibcon#end of sib2, iclass 35, count 0 2006.280.08:03:17.05#ibcon#*after write, iclass 35, count 0 2006.280.08:03:17.05#ibcon#*before return 0, iclass 35, count 0 2006.280.08:03:17.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:17.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:03:17.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:03:17.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:03:17.05$vc4f8/vbbw=wide 2006.280.08:03:17.07#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.08:03:17.07#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.08:03:17.07#ibcon#ireg 8 cls_cnt 0 2006.280.08:03:17.07#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:03:17.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:03:17.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:03:17.12#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:03:17.12#ibcon#first serial, iclass 37, count 0 2006.280.08:03:17.12#ibcon#enter sib2, iclass 37, count 0 2006.280.08:03:17.12#ibcon#flushed, iclass 37, count 0 2006.280.08:03:17.12#ibcon#about to write, iclass 37, count 0 2006.280.08:03:17.12#ibcon#wrote, iclass 37, count 0 2006.280.08:03:17.12#ibcon#about to read 3, iclass 37, count 0 2006.280.08:03:17.14#ibcon#read 3, iclass 37, count 0 2006.280.08:03:17.14#ibcon#about to read 4, iclass 37, count 0 2006.280.08:03:17.14#ibcon#read 4, iclass 37, count 0 2006.280.08:03:17.14#ibcon#about to read 5, iclass 37, count 0 2006.280.08:03:17.14#ibcon#read 5, iclass 37, count 0 2006.280.08:03:17.14#ibcon#about to read 6, iclass 37, count 0 2006.280.08:03:17.14#ibcon#read 6, iclass 37, count 0 2006.280.08:03:17.14#ibcon#end of sib2, iclass 37, count 0 2006.280.08:03:17.14#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:03:17.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:03:17.14#ibcon#[27=BW32\r\n] 2006.280.08:03:17.14#ibcon#*before write, iclass 37, count 0 2006.280.08:03:17.14#ibcon#enter sib2, iclass 37, count 0 2006.280.08:03:17.14#ibcon#flushed, iclass 37, count 0 2006.280.08:03:17.14#ibcon#about to write, iclass 37, count 0 2006.280.08:03:17.14#ibcon#wrote, iclass 37, count 0 2006.280.08:03:17.14#ibcon#about to read 3, iclass 37, count 0 2006.280.08:03:17.17#ibcon#read 3, iclass 37, count 0 2006.280.08:03:17.17#ibcon#about to read 4, iclass 37, count 0 2006.280.08:03:17.17#ibcon#read 4, iclass 37, count 0 2006.280.08:03:17.17#ibcon#about to read 5, iclass 37, count 0 2006.280.08:03:17.17#ibcon#read 5, iclass 37, count 0 2006.280.08:03:17.17#ibcon#about to read 6, iclass 37, count 0 2006.280.08:03:17.17#ibcon#read 6, iclass 37, count 0 2006.280.08:03:17.17#ibcon#end of sib2, iclass 37, count 0 2006.280.08:03:17.17#ibcon#*after write, iclass 37, count 0 2006.280.08:03:17.17#ibcon#*before return 0, iclass 37, count 0 2006.280.08:03:17.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:03:17.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:03:17.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:03:17.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:03:17.17$4f8m12a/ifd4f 2006.280.08:03:17.17$ifd4f/lo= 2006.280.08:03:17.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:03:17.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:03:17.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:03:17.17$ifd4f/patch= 2006.280.08:03:17.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:03:17.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:03:17.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:03:17.17$4f8m12a/"form=m,16.000,1:2 2006.280.08:03:17.17$4f8m12a/"tpicd 2006.280.08:03:17.17$4f8m12a/echo=off 2006.280.08:03:17.17$4f8m12a/xlog=off 2006.280.08:03:17.17:!2006.280.08:03:40 2006.280.08:03:21.14#trakl#Source acquired 2006.280.08:03:22.14#flagr#flagr/antenna,acquired 2006.280.08:03:40.00:preob 2006.280.08:03:41.14/onsource/TRACKING 2006.280.08:03:41.14:!2006.280.08:03:50 2006.280.08:03:50.00:data_valid=on 2006.280.08:03:50.00:midob 2006.280.08:03:50.14/onsource/TRACKING 2006.280.08:03:50.14/wx/20.81,987.3,62 2006.280.08:03:50.27/cable/+6.4852E-03 2006.280.08:03:51.36/va/01,07,usb,yes,32,34 2006.280.08:03:51.36/va/02,06,usb,yes,30,31 2006.280.08:03:51.36/va/03,06,usb,yes,28,28 2006.280.08:03:51.36/va/04,06,usb,yes,31,33 2006.280.08:03:51.36/va/05,07,usb,yes,29,30 2006.280.08:03:51.36/va/06,06,usb,yes,28,28 2006.280.08:03:51.36/va/07,06,usb,yes,28,28 2006.280.08:03:51.36/va/08,06,usb,yes,30,30 2006.280.08:03:51.59/valo/01,532.99,yes,locked 2006.280.08:03:51.59/valo/02,572.99,yes,locked 2006.280.08:03:51.59/valo/03,672.99,yes,locked 2006.280.08:03:51.59/valo/04,832.99,yes,locked 2006.280.08:03:51.59/valo/05,652.99,yes,locked 2006.280.08:03:51.59/valo/06,772.99,yes,locked 2006.280.08:03:51.59/valo/07,832.99,yes,locked 2006.280.08:03:51.59/valo/08,852.99,yes,locked 2006.280.08:03:52.68/vb/01,04,usb,yes,30,28 2006.280.08:03:52.68/vb/02,05,usb,yes,28,29 2006.280.08:03:52.68/vb/03,04,usb,yes,28,32 2006.280.08:03:52.68/vb/04,04,usb,yes,29,29 2006.280.08:03:52.68/vb/05,04,usb,yes,27,31 2006.280.08:03:52.68/vb/06,04,usb,yes,27,31 2006.280.08:03:52.68/vb/07,04,usb,yes,30,30 2006.280.08:03:52.68/vb/08,04,usb,yes,27,31 2006.280.08:03:52.91/vblo/01,632.99,yes,locked 2006.280.08:03:52.91/vblo/02,640.99,yes,locked 2006.280.08:03:52.91/vblo/03,656.99,yes,locked 2006.280.08:03:52.91/vblo/04,712.99,yes,locked 2006.280.08:03:52.91/vblo/05,744.99,yes,locked 2006.280.08:03:52.91/vblo/06,752.99,yes,locked 2006.280.08:03:52.91/vblo/07,734.99,yes,locked 2006.280.08:03:52.91/vblo/08,744.99,yes,locked 2006.280.08:03:53.06/vabw/8 2006.280.08:03:53.21/vbbw/8 2006.280.08:03:53.30/xfe/off,on,12.2 2006.280.08:03:53.67/ifatt/23,28,28,28 2006.280.08:03:54.07/fmout-gps/S +3.22E-07 2006.280.08:03:54.09:!2006.280.08:04:50 2006.280.08:04:50.01:data_valid=off 2006.280.08:04:50.01:postob 2006.280.08:04:50.20/cable/+6.4839E-03 2006.280.08:04:50.20/wx/20.76,987.3,62 2006.280.08:04:51.08/fmout-gps/S +3.20E-07 2006.280.08:04:51.08:scan_name=280-0805,k06280,60 2006.280.08:04:51.09:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.280.08:04:51.14#flagr#flagr/antenna,new-source 2006.280.08:04:52.14:checkk5 2006.280.08:04:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:04:53.14/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:04:53.70/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:04:54.19/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:04:54.61/chk_obsdata//k5ts1/T2800803??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:04:55.25/chk_obsdata//k5ts2/T2800803??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:04:56.01/chk_obsdata//k5ts3/T2800803??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:04:56.38/chk_obsdata//k5ts4/T2800803??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:04:57.46/k5log//k5ts1_log_newline 2006.280.08:04:58.42/k5log//k5ts2_log_newline 2006.280.08:04:59.60/k5log//k5ts3_log_newline 2006.280.08:05:01.01/k5log//k5ts4_log_newline 2006.280.08:05:01.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:05:01.03:4f8m12a=2 2006.280.08:05:01.03$4f8m12a/echo=on 2006.280.08:05:01.03$4f8m12a/pcalon 2006.280.08:05:01.03$pcalon/"no phase cal control is implemented here 2006.280.08:05:01.03$4f8m12a/"tpicd=stop 2006.280.08:05:01.03$4f8m12a/vc4f8 2006.280.08:05:01.04$vc4f8/valo=1,532.99 2006.280.08:05:01.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:05:01.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:05:01.04#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:01.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:01.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:01.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:01.04#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:05:01.04#ibcon#first serial, iclass 6, count 0 2006.280.08:05:01.04#ibcon#enter sib2, iclass 6, count 0 2006.280.08:05:01.04#ibcon#flushed, iclass 6, count 0 2006.280.08:05:01.04#ibcon#about to write, iclass 6, count 0 2006.280.08:05:01.04#ibcon#wrote, iclass 6, count 0 2006.280.08:05:01.04#ibcon#about to read 3, iclass 6, count 0 2006.280.08:05:01.06#ibcon#read 3, iclass 6, count 0 2006.280.08:05:01.06#ibcon#about to read 4, iclass 6, count 0 2006.280.08:05:01.06#ibcon#read 4, iclass 6, count 0 2006.280.08:05:01.06#ibcon#about to read 5, iclass 6, count 0 2006.280.08:05:01.06#ibcon#read 5, iclass 6, count 0 2006.280.08:05:01.06#ibcon#about to read 6, iclass 6, count 0 2006.280.08:05:01.06#ibcon#read 6, iclass 6, count 0 2006.280.08:05:01.06#ibcon#end of sib2, iclass 6, count 0 2006.280.08:05:01.06#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:05:01.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:05:01.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:05:01.06#ibcon#*before write, iclass 6, count 0 2006.280.08:05:01.06#ibcon#enter sib2, iclass 6, count 0 2006.280.08:05:01.06#ibcon#flushed, iclass 6, count 0 2006.280.08:05:01.06#ibcon#about to write, iclass 6, count 0 2006.280.08:05:01.06#ibcon#wrote, iclass 6, count 0 2006.280.08:05:01.06#ibcon#about to read 3, iclass 6, count 0 2006.280.08:05:01.11#ibcon#read 3, iclass 6, count 0 2006.280.08:05:01.11#ibcon#about to read 4, iclass 6, count 0 2006.280.08:05:01.11#ibcon#read 4, iclass 6, count 0 2006.280.08:05:01.11#ibcon#about to read 5, iclass 6, count 0 2006.280.08:05:01.11#ibcon#read 5, iclass 6, count 0 2006.280.08:05:01.11#ibcon#about to read 6, iclass 6, count 0 2006.280.08:05:01.11#ibcon#read 6, iclass 6, count 0 2006.280.08:05:01.11#ibcon#end of sib2, iclass 6, count 0 2006.280.08:05:01.11#ibcon#*after write, iclass 6, count 0 2006.280.08:05:01.11#ibcon#*before return 0, iclass 6, count 0 2006.280.08:05:01.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:01.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:01.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:05:01.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:05:01.11$vc4f8/va=1,7 2006.280.08:05:01.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.08:05:01.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.08:05:01.12#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:01.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:01.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:01.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:01.12#ibcon#enter wrdev, iclass 10, count 2 2006.280.08:05:01.12#ibcon#first serial, iclass 10, count 2 2006.280.08:05:01.12#ibcon#enter sib2, iclass 10, count 2 2006.280.08:05:01.12#ibcon#flushed, iclass 10, count 2 2006.280.08:05:01.12#ibcon#about to write, iclass 10, count 2 2006.280.08:05:01.12#ibcon#wrote, iclass 10, count 2 2006.280.08:05:01.12#ibcon#about to read 3, iclass 10, count 2 2006.280.08:05:01.14#ibcon#read 3, iclass 10, count 2 2006.280.08:05:01.14#ibcon#about to read 4, iclass 10, count 2 2006.280.08:05:01.14#ibcon#read 4, iclass 10, count 2 2006.280.08:05:01.14#ibcon#about to read 5, iclass 10, count 2 2006.280.08:05:01.14#ibcon#read 5, iclass 10, count 2 2006.280.08:05:01.14#ibcon#about to read 6, iclass 10, count 2 2006.280.08:05:01.14#ibcon#read 6, iclass 10, count 2 2006.280.08:05:01.14#ibcon#end of sib2, iclass 10, count 2 2006.280.08:05:01.14#ibcon#*mode == 0, iclass 10, count 2 2006.280.08:05:01.14#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.08:05:01.14#ibcon#[25=AT01-07\r\n] 2006.280.08:05:01.14#ibcon#*before write, iclass 10, count 2 2006.280.08:05:01.14#ibcon#enter sib2, iclass 10, count 2 2006.280.08:05:01.14#ibcon#flushed, iclass 10, count 2 2006.280.08:05:01.14#ibcon#about to write, iclass 10, count 2 2006.280.08:05:01.14#ibcon#wrote, iclass 10, count 2 2006.280.08:05:01.14#ibcon#about to read 3, iclass 10, count 2 2006.280.08:05:01.17#ibcon#read 3, iclass 10, count 2 2006.280.08:05:01.17#ibcon#about to read 4, iclass 10, count 2 2006.280.08:05:01.17#ibcon#read 4, iclass 10, count 2 2006.280.08:05:01.17#ibcon#about to read 5, iclass 10, count 2 2006.280.08:05:01.17#ibcon#read 5, iclass 10, count 2 2006.280.08:05:01.17#ibcon#about to read 6, iclass 10, count 2 2006.280.08:05:01.17#ibcon#read 6, iclass 10, count 2 2006.280.08:05:01.17#ibcon#end of sib2, iclass 10, count 2 2006.280.08:05:01.17#ibcon#*after write, iclass 10, count 2 2006.280.08:05:01.17#ibcon#*before return 0, iclass 10, count 2 2006.280.08:05:01.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:01.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:01.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.08:05:01.17#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:01.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:01.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:01.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:01.29#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:05:01.29#ibcon#first serial, iclass 10, count 0 2006.280.08:05:01.29#ibcon#enter sib2, iclass 10, count 0 2006.280.08:05:01.29#ibcon#flushed, iclass 10, count 0 2006.280.08:05:01.29#ibcon#about to write, iclass 10, count 0 2006.280.08:05:01.29#ibcon#wrote, iclass 10, count 0 2006.280.08:05:01.29#ibcon#about to read 3, iclass 10, count 0 2006.280.08:05:01.31#ibcon#read 3, iclass 10, count 0 2006.280.08:05:01.31#ibcon#about to read 4, iclass 10, count 0 2006.280.08:05:01.31#ibcon#read 4, iclass 10, count 0 2006.280.08:05:01.31#ibcon#about to read 5, iclass 10, count 0 2006.280.08:05:01.31#ibcon#read 5, iclass 10, count 0 2006.280.08:05:01.31#ibcon#about to read 6, iclass 10, count 0 2006.280.08:05:01.31#ibcon#read 6, iclass 10, count 0 2006.280.08:05:01.31#ibcon#end of sib2, iclass 10, count 0 2006.280.08:05:01.31#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:05:01.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:05:01.31#ibcon#[25=USB\r\n] 2006.280.08:05:01.31#ibcon#*before write, iclass 10, count 0 2006.280.08:05:01.31#ibcon#enter sib2, iclass 10, count 0 2006.280.08:05:01.31#ibcon#flushed, iclass 10, count 0 2006.280.08:05:01.31#ibcon#about to write, iclass 10, count 0 2006.280.08:05:01.31#ibcon#wrote, iclass 10, count 0 2006.280.08:05:01.31#ibcon#about to read 3, iclass 10, count 0 2006.280.08:05:01.34#ibcon#read 3, iclass 10, count 0 2006.280.08:05:01.34#ibcon#about to read 4, iclass 10, count 0 2006.280.08:05:01.34#ibcon#read 4, iclass 10, count 0 2006.280.08:05:01.34#ibcon#about to read 5, iclass 10, count 0 2006.280.08:05:01.34#ibcon#read 5, iclass 10, count 0 2006.280.08:05:01.34#ibcon#about to read 6, iclass 10, count 0 2006.280.08:05:01.34#ibcon#read 6, iclass 10, count 0 2006.280.08:05:01.34#ibcon#end of sib2, iclass 10, count 0 2006.280.08:05:01.34#ibcon#*after write, iclass 10, count 0 2006.280.08:05:01.34#ibcon#*before return 0, iclass 10, count 0 2006.280.08:05:01.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:01.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:01.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:05:01.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:05:01.34$vc4f8/valo=2,572.99 2006.280.08:05:01.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:05:01.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:05:01.34#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:01.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:01.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:01.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:01.34#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:05:01.34#ibcon#first serial, iclass 12, count 0 2006.280.08:05:01.34#ibcon#enter sib2, iclass 12, count 0 2006.280.08:05:01.34#ibcon#flushed, iclass 12, count 0 2006.280.08:05:01.34#ibcon#about to write, iclass 12, count 0 2006.280.08:05:01.34#ibcon#wrote, iclass 12, count 0 2006.280.08:05:01.34#ibcon#about to read 3, iclass 12, count 0 2006.280.08:05:01.36#ibcon#read 3, iclass 12, count 0 2006.280.08:05:01.36#ibcon#about to read 4, iclass 12, count 0 2006.280.08:05:01.36#ibcon#read 4, iclass 12, count 0 2006.280.08:05:01.36#ibcon#about to read 5, iclass 12, count 0 2006.280.08:05:01.36#ibcon#read 5, iclass 12, count 0 2006.280.08:05:01.36#ibcon#about to read 6, iclass 12, count 0 2006.280.08:05:01.36#ibcon#read 6, iclass 12, count 0 2006.280.08:05:01.36#ibcon#end of sib2, iclass 12, count 0 2006.280.08:05:01.36#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:05:01.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:05:01.36#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:05:01.36#ibcon#*before write, iclass 12, count 0 2006.280.08:05:01.36#ibcon#enter sib2, iclass 12, count 0 2006.280.08:05:01.36#ibcon#flushed, iclass 12, count 0 2006.280.08:05:01.36#ibcon#about to write, iclass 12, count 0 2006.280.08:05:01.36#ibcon#wrote, iclass 12, count 0 2006.280.08:05:01.36#ibcon#about to read 3, iclass 12, count 0 2006.280.08:05:01.40#ibcon#read 3, iclass 12, count 0 2006.280.08:05:01.40#ibcon#about to read 4, iclass 12, count 0 2006.280.08:05:01.40#ibcon#read 4, iclass 12, count 0 2006.280.08:05:01.40#ibcon#about to read 5, iclass 12, count 0 2006.280.08:05:01.40#ibcon#read 5, iclass 12, count 0 2006.280.08:05:01.40#ibcon#about to read 6, iclass 12, count 0 2006.280.08:05:01.40#ibcon#read 6, iclass 12, count 0 2006.280.08:05:01.40#ibcon#end of sib2, iclass 12, count 0 2006.280.08:05:01.40#ibcon#*after write, iclass 12, count 0 2006.280.08:05:01.40#ibcon#*before return 0, iclass 12, count 0 2006.280.08:05:01.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:01.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:01.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:05:01.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:05:01.40$vc4f8/va=2,6 2006.280.08:05:01.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:05:01.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:05:01.40#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:01.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:01.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:01.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:01.46#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:05:01.46#ibcon#first serial, iclass 14, count 2 2006.280.08:05:01.46#ibcon#enter sib2, iclass 14, count 2 2006.280.08:05:01.46#ibcon#flushed, iclass 14, count 2 2006.280.08:05:01.46#ibcon#about to write, iclass 14, count 2 2006.280.08:05:01.46#ibcon#wrote, iclass 14, count 2 2006.280.08:05:01.46#ibcon#about to read 3, iclass 14, count 2 2006.280.08:05:01.48#ibcon#read 3, iclass 14, count 2 2006.280.08:05:01.48#ibcon#about to read 4, iclass 14, count 2 2006.280.08:05:01.48#ibcon#read 4, iclass 14, count 2 2006.280.08:05:01.48#ibcon#about to read 5, iclass 14, count 2 2006.280.08:05:01.48#ibcon#read 5, iclass 14, count 2 2006.280.08:05:01.48#ibcon#about to read 6, iclass 14, count 2 2006.280.08:05:01.48#ibcon#read 6, iclass 14, count 2 2006.280.08:05:01.48#ibcon#end of sib2, iclass 14, count 2 2006.280.08:05:01.48#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:05:01.48#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:05:01.48#ibcon#[25=AT02-06\r\n] 2006.280.08:05:01.48#ibcon#*before write, iclass 14, count 2 2006.280.08:05:01.48#ibcon#enter sib2, iclass 14, count 2 2006.280.08:05:01.48#ibcon#flushed, iclass 14, count 2 2006.280.08:05:01.48#ibcon#about to write, iclass 14, count 2 2006.280.08:05:01.48#ibcon#wrote, iclass 14, count 2 2006.280.08:05:01.48#ibcon#about to read 3, iclass 14, count 2 2006.280.08:05:01.51#ibcon#read 3, iclass 14, count 2 2006.280.08:05:01.51#ibcon#about to read 4, iclass 14, count 2 2006.280.08:05:01.51#ibcon#read 4, iclass 14, count 2 2006.280.08:05:01.51#ibcon#about to read 5, iclass 14, count 2 2006.280.08:05:01.51#ibcon#read 5, iclass 14, count 2 2006.280.08:05:01.51#ibcon#about to read 6, iclass 14, count 2 2006.280.08:05:01.51#ibcon#read 6, iclass 14, count 2 2006.280.08:05:01.51#ibcon#end of sib2, iclass 14, count 2 2006.280.08:05:01.51#ibcon#*after write, iclass 14, count 2 2006.280.08:05:01.51#ibcon#*before return 0, iclass 14, count 2 2006.280.08:05:01.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:01.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:01.51#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:05:01.51#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:01.51#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:01.64#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:01.64#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:01.64#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:05:01.64#ibcon#first serial, iclass 14, count 0 2006.280.08:05:01.64#ibcon#enter sib2, iclass 14, count 0 2006.280.08:05:01.64#ibcon#flushed, iclass 14, count 0 2006.280.08:05:01.64#ibcon#about to write, iclass 14, count 0 2006.280.08:05:01.64#ibcon#wrote, iclass 14, count 0 2006.280.08:05:01.64#ibcon#about to read 3, iclass 14, count 0 2006.280.08:05:01.65#ibcon#read 3, iclass 14, count 0 2006.280.08:05:01.65#ibcon#about to read 4, iclass 14, count 0 2006.280.08:05:01.65#ibcon#read 4, iclass 14, count 0 2006.280.08:05:01.65#ibcon#about to read 5, iclass 14, count 0 2006.280.08:05:01.65#ibcon#read 5, iclass 14, count 0 2006.280.08:05:01.65#ibcon#about to read 6, iclass 14, count 0 2006.280.08:05:01.65#ibcon#read 6, iclass 14, count 0 2006.280.08:05:01.65#ibcon#end of sib2, iclass 14, count 0 2006.280.08:05:01.65#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:05:01.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:05:01.65#ibcon#[25=USB\r\n] 2006.280.08:05:01.65#ibcon#*before write, iclass 14, count 0 2006.280.08:05:01.65#ibcon#enter sib2, iclass 14, count 0 2006.280.08:05:01.65#ibcon#flushed, iclass 14, count 0 2006.280.08:05:01.65#ibcon#about to write, iclass 14, count 0 2006.280.08:05:01.65#ibcon#wrote, iclass 14, count 0 2006.280.08:05:01.65#ibcon#about to read 3, iclass 14, count 0 2006.280.08:05:01.68#ibcon#read 3, iclass 14, count 0 2006.280.08:05:01.68#ibcon#about to read 4, iclass 14, count 0 2006.280.08:05:01.68#ibcon#read 4, iclass 14, count 0 2006.280.08:05:01.68#ibcon#about to read 5, iclass 14, count 0 2006.280.08:05:01.68#ibcon#read 5, iclass 14, count 0 2006.280.08:05:01.68#ibcon#about to read 6, iclass 14, count 0 2006.280.08:05:01.68#ibcon#read 6, iclass 14, count 0 2006.280.08:05:01.68#ibcon#end of sib2, iclass 14, count 0 2006.280.08:05:01.68#ibcon#*after write, iclass 14, count 0 2006.280.08:05:01.68#ibcon#*before return 0, iclass 14, count 0 2006.280.08:05:01.68#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:01.68#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:01.68#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:05:01.68#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:05:01.68$vc4f8/valo=3,672.99 2006.280.08:05:01.68#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:05:01.68#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:05:01.68#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:01.68#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:01.68#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:01.68#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:01.68#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:05:01.68#ibcon#first serial, iclass 16, count 0 2006.280.08:05:01.68#ibcon#enter sib2, iclass 16, count 0 2006.280.08:05:01.68#ibcon#flushed, iclass 16, count 0 2006.280.08:05:01.68#ibcon#about to write, iclass 16, count 0 2006.280.08:05:01.68#ibcon#wrote, iclass 16, count 0 2006.280.08:05:01.68#ibcon#about to read 3, iclass 16, count 0 2006.280.08:05:01.70#ibcon#read 3, iclass 16, count 0 2006.280.08:05:01.70#ibcon#about to read 4, iclass 16, count 0 2006.280.08:05:01.70#ibcon#read 4, iclass 16, count 0 2006.280.08:05:01.70#ibcon#about to read 5, iclass 16, count 0 2006.280.08:05:01.70#ibcon#read 5, iclass 16, count 0 2006.280.08:05:01.70#ibcon#about to read 6, iclass 16, count 0 2006.280.08:05:01.70#ibcon#read 6, iclass 16, count 0 2006.280.08:05:01.70#ibcon#end of sib2, iclass 16, count 0 2006.280.08:05:01.70#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:05:01.70#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:05:01.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:05:01.70#ibcon#*before write, iclass 16, count 0 2006.280.08:05:01.70#ibcon#enter sib2, iclass 16, count 0 2006.280.08:05:01.70#ibcon#flushed, iclass 16, count 0 2006.280.08:05:01.70#ibcon#about to write, iclass 16, count 0 2006.280.08:05:01.70#ibcon#wrote, iclass 16, count 0 2006.280.08:05:01.70#ibcon#about to read 3, iclass 16, count 0 2006.280.08:05:01.74#ibcon#read 3, iclass 16, count 0 2006.280.08:05:01.74#ibcon#about to read 4, iclass 16, count 0 2006.280.08:05:01.74#ibcon#read 4, iclass 16, count 0 2006.280.08:05:01.74#ibcon#about to read 5, iclass 16, count 0 2006.280.08:05:01.74#ibcon#read 5, iclass 16, count 0 2006.280.08:05:01.74#ibcon#about to read 6, iclass 16, count 0 2006.280.08:05:01.74#ibcon#read 6, iclass 16, count 0 2006.280.08:05:01.74#ibcon#end of sib2, iclass 16, count 0 2006.280.08:05:01.74#ibcon#*after write, iclass 16, count 0 2006.280.08:05:01.74#ibcon#*before return 0, iclass 16, count 0 2006.280.08:05:01.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:01.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:01.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:05:01.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:05:01.74$vc4f8/va=3,6 2006.280.08:05:01.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:05:01.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:05:01.74#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:01.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:01.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:01.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:01.80#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:05:01.80#ibcon#first serial, iclass 18, count 2 2006.280.08:05:01.80#ibcon#enter sib2, iclass 18, count 2 2006.280.08:05:01.80#ibcon#flushed, iclass 18, count 2 2006.280.08:05:01.80#ibcon#about to write, iclass 18, count 2 2006.280.08:05:01.80#ibcon#wrote, iclass 18, count 2 2006.280.08:05:01.80#ibcon#about to read 3, iclass 18, count 2 2006.280.08:05:01.82#ibcon#read 3, iclass 18, count 2 2006.280.08:05:01.82#ibcon#about to read 4, iclass 18, count 2 2006.280.08:05:01.82#ibcon#read 4, iclass 18, count 2 2006.280.08:05:01.82#ibcon#about to read 5, iclass 18, count 2 2006.280.08:05:01.82#ibcon#read 5, iclass 18, count 2 2006.280.08:05:01.82#ibcon#about to read 6, iclass 18, count 2 2006.280.08:05:01.82#ibcon#read 6, iclass 18, count 2 2006.280.08:05:01.82#ibcon#end of sib2, iclass 18, count 2 2006.280.08:05:01.82#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:05:01.82#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:05:01.82#ibcon#[25=AT03-06\r\n] 2006.280.08:05:01.82#ibcon#*before write, iclass 18, count 2 2006.280.08:05:01.82#ibcon#enter sib2, iclass 18, count 2 2006.280.08:05:01.82#ibcon#flushed, iclass 18, count 2 2006.280.08:05:01.82#ibcon#about to write, iclass 18, count 2 2006.280.08:05:01.82#ibcon#wrote, iclass 18, count 2 2006.280.08:05:01.82#ibcon#about to read 3, iclass 18, count 2 2006.280.08:05:01.85#ibcon#read 3, iclass 18, count 2 2006.280.08:05:01.85#ibcon#about to read 4, iclass 18, count 2 2006.280.08:05:01.85#ibcon#read 4, iclass 18, count 2 2006.280.08:05:01.85#ibcon#about to read 5, iclass 18, count 2 2006.280.08:05:01.85#ibcon#read 5, iclass 18, count 2 2006.280.08:05:01.85#ibcon#about to read 6, iclass 18, count 2 2006.280.08:05:01.85#ibcon#read 6, iclass 18, count 2 2006.280.08:05:01.85#ibcon#end of sib2, iclass 18, count 2 2006.280.08:05:01.85#ibcon#*after write, iclass 18, count 2 2006.280.08:05:01.85#ibcon#*before return 0, iclass 18, count 2 2006.280.08:05:01.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:01.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:01.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:05:01.85#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:01.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:01.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:01.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:01.97#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:05:01.97#ibcon#first serial, iclass 18, count 0 2006.280.08:05:01.97#ibcon#enter sib2, iclass 18, count 0 2006.280.08:05:01.97#ibcon#flushed, iclass 18, count 0 2006.280.08:05:01.97#ibcon#about to write, iclass 18, count 0 2006.280.08:05:01.97#ibcon#wrote, iclass 18, count 0 2006.280.08:05:01.97#ibcon#about to read 3, iclass 18, count 0 2006.280.08:05:01.99#ibcon#read 3, iclass 18, count 0 2006.280.08:05:01.99#ibcon#about to read 4, iclass 18, count 0 2006.280.08:05:01.99#ibcon#read 4, iclass 18, count 0 2006.280.08:05:01.99#ibcon#about to read 5, iclass 18, count 0 2006.280.08:05:01.99#ibcon#read 5, iclass 18, count 0 2006.280.08:05:01.99#ibcon#about to read 6, iclass 18, count 0 2006.280.08:05:01.99#ibcon#read 6, iclass 18, count 0 2006.280.08:05:01.99#ibcon#end of sib2, iclass 18, count 0 2006.280.08:05:01.99#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:05:01.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:05:01.99#ibcon#[25=USB\r\n] 2006.280.08:05:01.99#ibcon#*before write, iclass 18, count 0 2006.280.08:05:01.99#ibcon#enter sib2, iclass 18, count 0 2006.280.08:05:01.99#ibcon#flushed, iclass 18, count 0 2006.280.08:05:01.99#ibcon#about to write, iclass 18, count 0 2006.280.08:05:01.99#ibcon#wrote, iclass 18, count 0 2006.280.08:05:01.99#ibcon#about to read 3, iclass 18, count 0 2006.280.08:05:02.02#ibcon#read 3, iclass 18, count 0 2006.280.08:05:02.02#ibcon#about to read 4, iclass 18, count 0 2006.280.08:05:02.02#ibcon#read 4, iclass 18, count 0 2006.280.08:05:02.02#ibcon#about to read 5, iclass 18, count 0 2006.280.08:05:02.02#ibcon#read 5, iclass 18, count 0 2006.280.08:05:02.02#ibcon#about to read 6, iclass 18, count 0 2006.280.08:05:02.02#ibcon#read 6, iclass 18, count 0 2006.280.08:05:02.02#ibcon#end of sib2, iclass 18, count 0 2006.280.08:05:02.02#ibcon#*after write, iclass 18, count 0 2006.280.08:05:02.02#ibcon#*before return 0, iclass 18, count 0 2006.280.08:05:02.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:02.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:02.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:05:02.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:05:02.02$vc4f8/valo=4,832.99 2006.280.08:05:02.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:05:02.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:05:02.02#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:02.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:02.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:02.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:02.02#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:05:02.02#ibcon#first serial, iclass 20, count 0 2006.280.08:05:02.02#ibcon#enter sib2, iclass 20, count 0 2006.280.08:05:02.02#ibcon#flushed, iclass 20, count 0 2006.280.08:05:02.02#ibcon#about to write, iclass 20, count 0 2006.280.08:05:02.02#ibcon#wrote, iclass 20, count 0 2006.280.08:05:02.02#ibcon#about to read 3, iclass 20, count 0 2006.280.08:05:02.04#ibcon#read 3, iclass 20, count 0 2006.280.08:05:02.04#ibcon#about to read 4, iclass 20, count 0 2006.280.08:05:02.04#ibcon#read 4, iclass 20, count 0 2006.280.08:05:02.04#ibcon#about to read 5, iclass 20, count 0 2006.280.08:05:02.04#ibcon#read 5, iclass 20, count 0 2006.280.08:05:02.04#ibcon#about to read 6, iclass 20, count 0 2006.280.08:05:02.04#ibcon#read 6, iclass 20, count 0 2006.280.08:05:02.04#ibcon#end of sib2, iclass 20, count 0 2006.280.08:05:02.04#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:05:02.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:05:02.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:05:02.04#ibcon#*before write, iclass 20, count 0 2006.280.08:05:02.04#ibcon#enter sib2, iclass 20, count 0 2006.280.08:05:02.04#ibcon#flushed, iclass 20, count 0 2006.280.08:05:02.04#ibcon#about to write, iclass 20, count 0 2006.280.08:05:02.04#ibcon#wrote, iclass 20, count 0 2006.280.08:05:02.04#ibcon#about to read 3, iclass 20, count 0 2006.280.08:05:02.08#ibcon#read 3, iclass 20, count 0 2006.280.08:05:02.08#ibcon#about to read 4, iclass 20, count 0 2006.280.08:05:02.08#ibcon#read 4, iclass 20, count 0 2006.280.08:05:02.08#ibcon#about to read 5, iclass 20, count 0 2006.280.08:05:02.08#ibcon#read 5, iclass 20, count 0 2006.280.08:05:02.08#ibcon#about to read 6, iclass 20, count 0 2006.280.08:05:02.08#ibcon#read 6, iclass 20, count 0 2006.280.08:05:02.08#ibcon#end of sib2, iclass 20, count 0 2006.280.08:05:02.08#ibcon#*after write, iclass 20, count 0 2006.280.08:05:02.08#ibcon#*before return 0, iclass 20, count 0 2006.280.08:05:02.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:02.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:02.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:05:02.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:05:02.08$vc4f8/va=4,6 2006.280.08:05:02.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.08:05:02.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.08:05:02.08#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:02.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:02.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:02.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:02.14#ibcon#enter wrdev, iclass 22, count 2 2006.280.08:05:02.14#ibcon#first serial, iclass 22, count 2 2006.280.08:05:02.14#ibcon#enter sib2, iclass 22, count 2 2006.280.08:05:02.14#ibcon#flushed, iclass 22, count 2 2006.280.08:05:02.14#ibcon#about to write, iclass 22, count 2 2006.280.08:05:02.14#ibcon#wrote, iclass 22, count 2 2006.280.08:05:02.14#ibcon#about to read 3, iclass 22, count 2 2006.280.08:05:02.16#ibcon#read 3, iclass 22, count 2 2006.280.08:05:02.16#ibcon#about to read 4, iclass 22, count 2 2006.280.08:05:02.16#ibcon#read 4, iclass 22, count 2 2006.280.08:05:02.16#ibcon#about to read 5, iclass 22, count 2 2006.280.08:05:02.17#ibcon#read 5, iclass 22, count 2 2006.280.08:05:02.17#ibcon#about to read 6, iclass 22, count 2 2006.280.08:05:02.17#ibcon#read 6, iclass 22, count 2 2006.280.08:05:02.17#ibcon#end of sib2, iclass 22, count 2 2006.280.08:05:02.17#ibcon#*mode == 0, iclass 22, count 2 2006.280.08:05:02.17#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.08:05:02.17#ibcon#[25=AT04-06\r\n] 2006.280.08:05:02.17#ibcon#*before write, iclass 22, count 2 2006.280.08:05:02.17#ibcon#enter sib2, iclass 22, count 2 2006.280.08:05:02.17#ibcon#flushed, iclass 22, count 2 2006.280.08:05:02.17#ibcon#about to write, iclass 22, count 2 2006.280.08:05:02.17#ibcon#wrote, iclass 22, count 2 2006.280.08:05:02.17#ibcon#about to read 3, iclass 22, count 2 2006.280.08:05:02.20#ibcon#read 3, iclass 22, count 2 2006.280.08:05:02.20#ibcon#about to read 4, iclass 22, count 2 2006.280.08:05:02.20#ibcon#read 4, iclass 22, count 2 2006.280.08:05:02.20#ibcon#about to read 5, iclass 22, count 2 2006.280.08:05:02.20#ibcon#read 5, iclass 22, count 2 2006.280.08:05:02.20#ibcon#about to read 6, iclass 22, count 2 2006.280.08:05:02.20#ibcon#read 6, iclass 22, count 2 2006.280.08:05:02.20#ibcon#end of sib2, iclass 22, count 2 2006.280.08:05:02.20#ibcon#*after write, iclass 22, count 2 2006.280.08:05:02.20#ibcon#*before return 0, iclass 22, count 2 2006.280.08:05:02.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:02.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:02.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.08:05:02.20#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:02.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:02.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:02.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:02.32#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:05:02.32#ibcon#first serial, iclass 22, count 0 2006.280.08:05:02.32#ibcon#enter sib2, iclass 22, count 0 2006.280.08:05:02.32#ibcon#flushed, iclass 22, count 0 2006.280.08:05:02.32#ibcon#about to write, iclass 22, count 0 2006.280.08:05:02.32#ibcon#wrote, iclass 22, count 0 2006.280.08:05:02.32#ibcon#about to read 3, iclass 22, count 0 2006.280.08:05:02.34#ibcon#read 3, iclass 22, count 0 2006.280.08:05:02.34#ibcon#about to read 4, iclass 22, count 0 2006.280.08:05:02.34#ibcon#read 4, iclass 22, count 0 2006.280.08:05:02.34#ibcon#about to read 5, iclass 22, count 0 2006.280.08:05:02.34#ibcon#read 5, iclass 22, count 0 2006.280.08:05:02.34#ibcon#about to read 6, iclass 22, count 0 2006.280.08:05:02.34#ibcon#read 6, iclass 22, count 0 2006.280.08:05:02.34#ibcon#end of sib2, iclass 22, count 0 2006.280.08:05:02.34#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:05:02.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:05:02.34#ibcon#[25=USB\r\n] 2006.280.08:05:02.34#ibcon#*before write, iclass 22, count 0 2006.280.08:05:02.34#ibcon#enter sib2, iclass 22, count 0 2006.280.08:05:02.34#ibcon#flushed, iclass 22, count 0 2006.280.08:05:02.34#ibcon#about to write, iclass 22, count 0 2006.280.08:05:02.34#ibcon#wrote, iclass 22, count 0 2006.280.08:05:02.34#ibcon#about to read 3, iclass 22, count 0 2006.280.08:05:02.37#ibcon#read 3, iclass 22, count 0 2006.280.08:05:02.37#ibcon#about to read 4, iclass 22, count 0 2006.280.08:05:02.37#ibcon#read 4, iclass 22, count 0 2006.280.08:05:02.37#ibcon#about to read 5, iclass 22, count 0 2006.280.08:05:02.37#ibcon#read 5, iclass 22, count 0 2006.280.08:05:02.37#ibcon#about to read 6, iclass 22, count 0 2006.280.08:05:02.37#ibcon#read 6, iclass 22, count 0 2006.280.08:05:02.37#ibcon#end of sib2, iclass 22, count 0 2006.280.08:05:02.37#ibcon#*after write, iclass 22, count 0 2006.280.08:05:02.37#ibcon#*before return 0, iclass 22, count 0 2006.280.08:05:02.37#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:02.37#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:02.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:05:02.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:05:02.37$vc4f8/valo=5,652.99 2006.280.08:05:02.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:05:02.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:05:02.37#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:02.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:02.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:02.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:02.37#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:05:02.37#ibcon#first serial, iclass 24, count 0 2006.280.08:05:02.37#ibcon#enter sib2, iclass 24, count 0 2006.280.08:05:02.37#ibcon#flushed, iclass 24, count 0 2006.280.08:05:02.37#ibcon#about to write, iclass 24, count 0 2006.280.08:05:02.37#ibcon#wrote, iclass 24, count 0 2006.280.08:05:02.37#ibcon#about to read 3, iclass 24, count 0 2006.280.08:05:02.39#ibcon#read 3, iclass 24, count 0 2006.280.08:05:02.39#ibcon#about to read 4, iclass 24, count 0 2006.280.08:05:02.39#ibcon#read 4, iclass 24, count 0 2006.280.08:05:02.39#ibcon#about to read 5, iclass 24, count 0 2006.280.08:05:02.39#ibcon#read 5, iclass 24, count 0 2006.280.08:05:02.39#ibcon#about to read 6, iclass 24, count 0 2006.280.08:05:02.39#ibcon#read 6, iclass 24, count 0 2006.280.08:05:02.39#ibcon#end of sib2, iclass 24, count 0 2006.280.08:05:02.39#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:05:02.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:05:02.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:05:02.39#ibcon#*before write, iclass 24, count 0 2006.280.08:05:02.39#ibcon#enter sib2, iclass 24, count 0 2006.280.08:05:02.39#ibcon#flushed, iclass 24, count 0 2006.280.08:05:02.39#ibcon#about to write, iclass 24, count 0 2006.280.08:05:02.39#ibcon#wrote, iclass 24, count 0 2006.280.08:05:02.39#ibcon#about to read 3, iclass 24, count 0 2006.280.08:05:02.43#ibcon#read 3, iclass 24, count 0 2006.280.08:05:02.43#ibcon#about to read 4, iclass 24, count 0 2006.280.08:05:02.43#ibcon#read 4, iclass 24, count 0 2006.280.08:05:02.43#ibcon#about to read 5, iclass 24, count 0 2006.280.08:05:02.43#ibcon#read 5, iclass 24, count 0 2006.280.08:05:02.43#ibcon#about to read 6, iclass 24, count 0 2006.280.08:05:02.43#ibcon#read 6, iclass 24, count 0 2006.280.08:05:02.43#ibcon#end of sib2, iclass 24, count 0 2006.280.08:05:02.43#ibcon#*after write, iclass 24, count 0 2006.280.08:05:02.43#ibcon#*before return 0, iclass 24, count 0 2006.280.08:05:02.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:02.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:02.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:05:02.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:05:02.43$vc4f8/va=5,7 2006.280.08:05:02.43#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:05:02.43#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:05:02.43#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:02.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:02.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:02.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:02.49#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:05:02.49#ibcon#first serial, iclass 26, count 2 2006.280.08:05:02.49#ibcon#enter sib2, iclass 26, count 2 2006.280.08:05:02.49#ibcon#flushed, iclass 26, count 2 2006.280.08:05:02.49#ibcon#about to write, iclass 26, count 2 2006.280.08:05:02.49#ibcon#wrote, iclass 26, count 2 2006.280.08:05:02.49#ibcon#about to read 3, iclass 26, count 2 2006.280.08:05:02.51#ibcon#read 3, iclass 26, count 2 2006.280.08:05:02.51#ibcon#about to read 4, iclass 26, count 2 2006.280.08:05:02.51#ibcon#read 4, iclass 26, count 2 2006.280.08:05:02.51#ibcon#about to read 5, iclass 26, count 2 2006.280.08:05:02.51#ibcon#read 5, iclass 26, count 2 2006.280.08:05:02.51#ibcon#about to read 6, iclass 26, count 2 2006.280.08:05:02.51#ibcon#read 6, iclass 26, count 2 2006.280.08:05:02.51#ibcon#end of sib2, iclass 26, count 2 2006.280.08:05:02.51#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:05:02.51#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:05:02.51#ibcon#[25=AT05-07\r\n] 2006.280.08:05:02.51#ibcon#*before write, iclass 26, count 2 2006.280.08:05:02.51#ibcon#enter sib2, iclass 26, count 2 2006.280.08:05:02.51#ibcon#flushed, iclass 26, count 2 2006.280.08:05:02.51#ibcon#about to write, iclass 26, count 2 2006.280.08:05:02.51#ibcon#wrote, iclass 26, count 2 2006.280.08:05:02.51#ibcon#about to read 3, iclass 26, count 2 2006.280.08:05:02.54#ibcon#read 3, iclass 26, count 2 2006.280.08:05:02.54#ibcon#about to read 4, iclass 26, count 2 2006.280.08:05:02.54#ibcon#read 4, iclass 26, count 2 2006.280.08:05:02.54#ibcon#about to read 5, iclass 26, count 2 2006.280.08:05:02.54#ibcon#read 5, iclass 26, count 2 2006.280.08:05:02.54#ibcon#about to read 6, iclass 26, count 2 2006.280.08:05:02.54#ibcon#read 6, iclass 26, count 2 2006.280.08:05:02.54#ibcon#end of sib2, iclass 26, count 2 2006.280.08:05:02.54#ibcon#*after write, iclass 26, count 2 2006.280.08:05:02.54#ibcon#*before return 0, iclass 26, count 2 2006.280.08:05:02.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:02.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:02.54#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:05:02.54#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:02.54#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:02.66#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:02.66#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:02.66#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:05:02.66#ibcon#first serial, iclass 26, count 0 2006.280.08:05:02.66#ibcon#enter sib2, iclass 26, count 0 2006.280.08:05:02.66#ibcon#flushed, iclass 26, count 0 2006.280.08:05:02.66#ibcon#about to write, iclass 26, count 0 2006.280.08:05:02.66#ibcon#wrote, iclass 26, count 0 2006.280.08:05:02.66#ibcon#about to read 3, iclass 26, count 0 2006.280.08:05:02.68#ibcon#read 3, iclass 26, count 0 2006.280.08:05:02.68#ibcon#about to read 4, iclass 26, count 0 2006.280.08:05:02.68#ibcon#read 4, iclass 26, count 0 2006.280.08:05:02.68#ibcon#about to read 5, iclass 26, count 0 2006.280.08:05:02.68#ibcon#read 5, iclass 26, count 0 2006.280.08:05:02.68#ibcon#about to read 6, iclass 26, count 0 2006.280.08:05:02.68#ibcon#read 6, iclass 26, count 0 2006.280.08:05:02.68#ibcon#end of sib2, iclass 26, count 0 2006.280.08:05:02.68#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:05:02.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:05:02.68#ibcon#[25=USB\r\n] 2006.280.08:05:02.68#ibcon#*before write, iclass 26, count 0 2006.280.08:05:02.68#ibcon#enter sib2, iclass 26, count 0 2006.280.08:05:02.68#ibcon#flushed, iclass 26, count 0 2006.280.08:05:02.68#ibcon#about to write, iclass 26, count 0 2006.280.08:05:02.68#ibcon#wrote, iclass 26, count 0 2006.280.08:05:02.68#ibcon#about to read 3, iclass 26, count 0 2006.280.08:05:02.71#ibcon#read 3, iclass 26, count 0 2006.280.08:05:02.71#ibcon#about to read 4, iclass 26, count 0 2006.280.08:05:02.71#ibcon#read 4, iclass 26, count 0 2006.280.08:05:02.71#ibcon#about to read 5, iclass 26, count 0 2006.280.08:05:02.71#ibcon#read 5, iclass 26, count 0 2006.280.08:05:02.71#ibcon#about to read 6, iclass 26, count 0 2006.280.08:05:02.71#ibcon#read 6, iclass 26, count 0 2006.280.08:05:02.71#ibcon#end of sib2, iclass 26, count 0 2006.280.08:05:02.71#ibcon#*after write, iclass 26, count 0 2006.280.08:05:02.71#ibcon#*before return 0, iclass 26, count 0 2006.280.08:05:02.71#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:02.71#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:02.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:05:02.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:05:02.71$vc4f8/valo=6,772.99 2006.280.08:05:02.71#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:05:02.71#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:05:02.71#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:02.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:02.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:02.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:02.71#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:05:02.71#ibcon#first serial, iclass 28, count 0 2006.280.08:05:02.71#ibcon#enter sib2, iclass 28, count 0 2006.280.08:05:02.71#ibcon#flushed, iclass 28, count 0 2006.280.08:05:02.71#ibcon#about to write, iclass 28, count 0 2006.280.08:05:02.71#ibcon#wrote, iclass 28, count 0 2006.280.08:05:02.71#ibcon#about to read 3, iclass 28, count 0 2006.280.08:05:02.73#ibcon#read 3, iclass 28, count 0 2006.280.08:05:02.73#ibcon#about to read 4, iclass 28, count 0 2006.280.08:05:02.73#ibcon#read 4, iclass 28, count 0 2006.280.08:05:02.73#ibcon#about to read 5, iclass 28, count 0 2006.280.08:05:02.73#ibcon#read 5, iclass 28, count 0 2006.280.08:05:02.73#ibcon#about to read 6, iclass 28, count 0 2006.280.08:05:02.73#ibcon#read 6, iclass 28, count 0 2006.280.08:05:02.73#ibcon#end of sib2, iclass 28, count 0 2006.280.08:05:02.73#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:05:02.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:05:02.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:05:02.73#ibcon#*before write, iclass 28, count 0 2006.280.08:05:02.73#ibcon#enter sib2, iclass 28, count 0 2006.280.08:05:02.73#ibcon#flushed, iclass 28, count 0 2006.280.08:05:02.73#ibcon#about to write, iclass 28, count 0 2006.280.08:05:02.73#ibcon#wrote, iclass 28, count 0 2006.280.08:05:02.73#ibcon#about to read 3, iclass 28, count 0 2006.280.08:05:02.77#ibcon#read 3, iclass 28, count 0 2006.280.08:05:02.77#ibcon#about to read 4, iclass 28, count 0 2006.280.08:05:02.77#ibcon#read 4, iclass 28, count 0 2006.280.08:05:02.77#ibcon#about to read 5, iclass 28, count 0 2006.280.08:05:02.77#ibcon#read 5, iclass 28, count 0 2006.280.08:05:02.77#ibcon#about to read 6, iclass 28, count 0 2006.280.08:05:02.77#ibcon#read 6, iclass 28, count 0 2006.280.08:05:02.77#ibcon#end of sib2, iclass 28, count 0 2006.280.08:05:02.77#ibcon#*after write, iclass 28, count 0 2006.280.08:05:02.77#ibcon#*before return 0, iclass 28, count 0 2006.280.08:05:02.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:02.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:02.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:05:02.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:05:02.77$vc4f8/va=6,6 2006.280.08:05:02.77#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.08:05:02.77#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.08:05:02.77#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:02.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:02.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:02.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:02.83#ibcon#enter wrdev, iclass 30, count 2 2006.280.08:05:02.83#ibcon#first serial, iclass 30, count 2 2006.280.08:05:02.83#ibcon#enter sib2, iclass 30, count 2 2006.280.08:05:02.83#ibcon#flushed, iclass 30, count 2 2006.280.08:05:02.83#ibcon#about to write, iclass 30, count 2 2006.280.08:05:02.83#ibcon#wrote, iclass 30, count 2 2006.280.08:05:02.83#ibcon#about to read 3, iclass 30, count 2 2006.280.08:05:02.85#ibcon#read 3, iclass 30, count 2 2006.280.08:05:02.85#ibcon#about to read 4, iclass 30, count 2 2006.280.08:05:02.85#ibcon#read 4, iclass 30, count 2 2006.280.08:05:02.85#ibcon#about to read 5, iclass 30, count 2 2006.280.08:05:02.85#ibcon#read 5, iclass 30, count 2 2006.280.08:05:02.85#ibcon#about to read 6, iclass 30, count 2 2006.280.08:05:02.85#ibcon#read 6, iclass 30, count 2 2006.280.08:05:02.85#ibcon#end of sib2, iclass 30, count 2 2006.280.08:05:02.85#ibcon#*mode == 0, iclass 30, count 2 2006.280.08:05:02.85#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.08:05:02.85#ibcon#[25=AT06-06\r\n] 2006.280.08:05:02.85#ibcon#*before write, iclass 30, count 2 2006.280.08:05:02.85#ibcon#enter sib2, iclass 30, count 2 2006.280.08:05:02.85#ibcon#flushed, iclass 30, count 2 2006.280.08:05:02.85#ibcon#about to write, iclass 30, count 2 2006.280.08:05:02.85#ibcon#wrote, iclass 30, count 2 2006.280.08:05:02.85#ibcon#about to read 3, iclass 30, count 2 2006.280.08:05:02.88#ibcon#read 3, iclass 30, count 2 2006.280.08:05:02.88#ibcon#about to read 4, iclass 30, count 2 2006.280.08:05:02.88#ibcon#read 4, iclass 30, count 2 2006.280.08:05:02.88#ibcon#about to read 5, iclass 30, count 2 2006.280.08:05:02.88#ibcon#read 5, iclass 30, count 2 2006.280.08:05:02.88#ibcon#about to read 6, iclass 30, count 2 2006.280.08:05:02.88#ibcon#read 6, iclass 30, count 2 2006.280.08:05:02.88#ibcon#end of sib2, iclass 30, count 2 2006.280.08:05:02.88#ibcon#*after write, iclass 30, count 2 2006.280.08:05:02.88#ibcon#*before return 0, iclass 30, count 2 2006.280.08:05:02.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:02.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:02.88#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.08:05:02.88#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:02.88#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:03.00#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:03.00#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:03.00#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:05:03.00#ibcon#first serial, iclass 30, count 0 2006.280.08:05:03.00#ibcon#enter sib2, iclass 30, count 0 2006.280.08:05:03.00#ibcon#flushed, iclass 30, count 0 2006.280.08:05:03.00#ibcon#about to write, iclass 30, count 0 2006.280.08:05:03.00#ibcon#wrote, iclass 30, count 0 2006.280.08:05:03.00#ibcon#about to read 3, iclass 30, count 0 2006.280.08:05:03.02#ibcon#read 3, iclass 30, count 0 2006.280.08:05:03.02#ibcon#about to read 4, iclass 30, count 0 2006.280.08:05:03.02#ibcon#read 4, iclass 30, count 0 2006.280.08:05:03.02#ibcon#about to read 5, iclass 30, count 0 2006.280.08:05:03.02#ibcon#read 5, iclass 30, count 0 2006.280.08:05:03.02#ibcon#about to read 6, iclass 30, count 0 2006.280.08:05:03.02#ibcon#read 6, iclass 30, count 0 2006.280.08:05:03.02#ibcon#end of sib2, iclass 30, count 0 2006.280.08:05:03.02#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:05:03.02#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:05:03.02#ibcon#[25=USB\r\n] 2006.280.08:05:03.02#ibcon#*before write, iclass 30, count 0 2006.280.08:05:03.02#ibcon#enter sib2, iclass 30, count 0 2006.280.08:05:03.02#ibcon#flushed, iclass 30, count 0 2006.280.08:05:03.02#ibcon#about to write, iclass 30, count 0 2006.280.08:05:03.02#ibcon#wrote, iclass 30, count 0 2006.280.08:05:03.02#ibcon#about to read 3, iclass 30, count 0 2006.280.08:05:03.05#ibcon#read 3, iclass 30, count 0 2006.280.08:05:03.05#ibcon#about to read 4, iclass 30, count 0 2006.280.08:05:03.05#ibcon#read 4, iclass 30, count 0 2006.280.08:05:03.05#ibcon#about to read 5, iclass 30, count 0 2006.280.08:05:03.05#ibcon#read 5, iclass 30, count 0 2006.280.08:05:03.05#ibcon#about to read 6, iclass 30, count 0 2006.280.08:05:03.05#ibcon#read 6, iclass 30, count 0 2006.280.08:05:03.05#ibcon#end of sib2, iclass 30, count 0 2006.280.08:05:03.05#ibcon#*after write, iclass 30, count 0 2006.280.08:05:03.05#ibcon#*before return 0, iclass 30, count 0 2006.280.08:05:03.05#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:03.05#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:03.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:05:03.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:05:03.05$vc4f8/valo=7,832.99 2006.280.08:05:03.05#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.08:05:03.05#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.08:05:03.05#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:03.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:03.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:03.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:03.05#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:05:03.05#ibcon#first serial, iclass 32, count 0 2006.280.08:05:03.05#ibcon#enter sib2, iclass 32, count 0 2006.280.08:05:03.05#ibcon#flushed, iclass 32, count 0 2006.280.08:05:03.05#ibcon#about to write, iclass 32, count 0 2006.280.08:05:03.05#ibcon#wrote, iclass 32, count 0 2006.280.08:05:03.05#ibcon#about to read 3, iclass 32, count 0 2006.280.08:05:03.07#ibcon#read 3, iclass 32, count 0 2006.280.08:05:03.07#ibcon#about to read 4, iclass 32, count 0 2006.280.08:05:03.07#ibcon#read 4, iclass 32, count 0 2006.280.08:05:03.07#ibcon#about to read 5, iclass 32, count 0 2006.280.08:05:03.07#ibcon#read 5, iclass 32, count 0 2006.280.08:05:03.07#ibcon#about to read 6, iclass 32, count 0 2006.280.08:05:03.07#ibcon#read 6, iclass 32, count 0 2006.280.08:05:03.07#ibcon#end of sib2, iclass 32, count 0 2006.280.08:05:03.07#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:05:03.07#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:05:03.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:05:03.07#ibcon#*before write, iclass 32, count 0 2006.280.08:05:03.07#ibcon#enter sib2, iclass 32, count 0 2006.280.08:05:03.07#ibcon#flushed, iclass 32, count 0 2006.280.08:05:03.07#ibcon#about to write, iclass 32, count 0 2006.280.08:05:03.07#ibcon#wrote, iclass 32, count 0 2006.280.08:05:03.07#ibcon#about to read 3, iclass 32, count 0 2006.280.08:05:03.11#ibcon#read 3, iclass 32, count 0 2006.280.08:05:03.11#ibcon#about to read 4, iclass 32, count 0 2006.280.08:05:03.11#ibcon#read 4, iclass 32, count 0 2006.280.08:05:03.11#ibcon#about to read 5, iclass 32, count 0 2006.280.08:05:03.11#ibcon#read 5, iclass 32, count 0 2006.280.08:05:03.11#ibcon#about to read 6, iclass 32, count 0 2006.280.08:05:03.11#ibcon#read 6, iclass 32, count 0 2006.280.08:05:03.11#ibcon#end of sib2, iclass 32, count 0 2006.280.08:05:03.11#ibcon#*after write, iclass 32, count 0 2006.280.08:05:03.11#ibcon#*before return 0, iclass 32, count 0 2006.280.08:05:03.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:03.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:03.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:05:03.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:05:03.11$vc4f8/va=7,6 2006.280.08:05:03.11#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.08:05:03.11#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.08:05:03.11#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:03.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:03.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:03.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:03.17#ibcon#enter wrdev, iclass 34, count 2 2006.280.08:05:03.17#ibcon#first serial, iclass 34, count 2 2006.280.08:05:03.17#ibcon#enter sib2, iclass 34, count 2 2006.280.08:05:03.17#ibcon#flushed, iclass 34, count 2 2006.280.08:05:03.17#ibcon#about to write, iclass 34, count 2 2006.280.08:05:03.17#ibcon#wrote, iclass 34, count 2 2006.280.08:05:03.17#ibcon#about to read 3, iclass 34, count 2 2006.280.08:05:03.19#ibcon#read 3, iclass 34, count 2 2006.280.08:05:03.19#ibcon#about to read 4, iclass 34, count 2 2006.280.08:05:03.19#ibcon#read 4, iclass 34, count 2 2006.280.08:05:03.20#ibcon#about to read 5, iclass 34, count 2 2006.280.08:05:03.20#ibcon#read 5, iclass 34, count 2 2006.280.08:05:03.20#ibcon#about to read 6, iclass 34, count 2 2006.280.08:05:03.20#ibcon#read 6, iclass 34, count 2 2006.280.08:05:03.20#ibcon#end of sib2, iclass 34, count 2 2006.280.08:05:03.20#ibcon#*mode == 0, iclass 34, count 2 2006.280.08:05:03.20#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.08:05:03.20#ibcon#[25=AT07-06\r\n] 2006.280.08:05:03.20#ibcon#*before write, iclass 34, count 2 2006.280.08:05:03.20#ibcon#enter sib2, iclass 34, count 2 2006.280.08:05:03.20#ibcon#flushed, iclass 34, count 2 2006.280.08:05:03.20#ibcon#about to write, iclass 34, count 2 2006.280.08:05:03.20#ibcon#wrote, iclass 34, count 2 2006.280.08:05:03.20#ibcon#about to read 3, iclass 34, count 2 2006.280.08:05:03.23#ibcon#read 3, iclass 34, count 2 2006.280.08:05:03.23#ibcon#about to read 4, iclass 34, count 2 2006.280.08:05:03.23#ibcon#read 4, iclass 34, count 2 2006.280.08:05:03.23#ibcon#about to read 5, iclass 34, count 2 2006.280.08:05:03.23#ibcon#read 5, iclass 34, count 2 2006.280.08:05:03.23#ibcon#about to read 6, iclass 34, count 2 2006.280.08:05:03.23#ibcon#read 6, iclass 34, count 2 2006.280.08:05:03.23#ibcon#end of sib2, iclass 34, count 2 2006.280.08:05:03.23#ibcon#*after write, iclass 34, count 2 2006.280.08:05:03.23#ibcon#*before return 0, iclass 34, count 2 2006.280.08:05:03.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:03.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:03.23#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.08:05:03.23#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:03.23#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:05:03.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:05:03.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:05:03.35#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:05:03.35#ibcon#first serial, iclass 34, count 0 2006.280.08:05:03.35#ibcon#enter sib2, iclass 34, count 0 2006.280.08:05:03.35#ibcon#flushed, iclass 34, count 0 2006.280.08:05:03.35#ibcon#about to write, iclass 34, count 0 2006.280.08:05:03.35#ibcon#wrote, iclass 34, count 0 2006.280.08:05:03.35#ibcon#about to read 3, iclass 34, count 0 2006.280.08:05:03.37#ibcon#read 3, iclass 34, count 0 2006.280.08:05:03.37#ibcon#about to read 4, iclass 34, count 0 2006.280.08:05:03.37#ibcon#read 4, iclass 34, count 0 2006.280.08:05:03.37#ibcon#about to read 5, iclass 34, count 0 2006.280.08:05:03.37#ibcon#read 5, iclass 34, count 0 2006.280.08:05:03.37#ibcon#about to read 6, iclass 34, count 0 2006.280.08:05:03.37#ibcon#read 6, iclass 34, count 0 2006.280.08:05:03.37#ibcon#end of sib2, iclass 34, count 0 2006.280.08:05:03.37#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:05:03.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:05:03.37#ibcon#[25=USB\r\n] 2006.280.08:05:03.37#ibcon#*before write, iclass 34, count 0 2006.280.08:05:03.37#ibcon#enter sib2, iclass 34, count 0 2006.280.08:05:03.37#ibcon#flushed, iclass 34, count 0 2006.280.08:05:03.37#ibcon#about to write, iclass 34, count 0 2006.280.08:05:03.37#ibcon#wrote, iclass 34, count 0 2006.280.08:05:03.37#ibcon#about to read 3, iclass 34, count 0 2006.280.08:05:03.40#ibcon#read 3, iclass 34, count 0 2006.280.08:05:03.40#ibcon#about to read 4, iclass 34, count 0 2006.280.08:05:03.40#ibcon#read 4, iclass 34, count 0 2006.280.08:05:03.40#ibcon#about to read 5, iclass 34, count 0 2006.280.08:05:03.40#ibcon#read 5, iclass 34, count 0 2006.280.08:05:03.40#ibcon#about to read 6, iclass 34, count 0 2006.280.08:05:03.40#ibcon#read 6, iclass 34, count 0 2006.280.08:05:03.40#ibcon#end of sib2, iclass 34, count 0 2006.280.08:05:03.40#ibcon#*after write, iclass 34, count 0 2006.280.08:05:03.40#ibcon#*before return 0, iclass 34, count 0 2006.280.08:05:03.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:05:03.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:05:03.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:05:03.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:05:03.40$vc4f8/valo=8,852.99 2006.280.08:05:03.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.08:05:03.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.08:05:03.40#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:03.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:05:03.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:05:03.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:05:03.40#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:05:03.40#ibcon#first serial, iclass 36, count 0 2006.280.08:05:03.40#ibcon#enter sib2, iclass 36, count 0 2006.280.08:05:03.40#ibcon#flushed, iclass 36, count 0 2006.280.08:05:03.40#ibcon#about to write, iclass 36, count 0 2006.280.08:05:03.40#ibcon#wrote, iclass 36, count 0 2006.280.08:05:03.40#ibcon#about to read 3, iclass 36, count 0 2006.280.08:05:03.42#ibcon#read 3, iclass 36, count 0 2006.280.08:05:03.42#ibcon#about to read 4, iclass 36, count 0 2006.280.08:05:03.42#ibcon#read 4, iclass 36, count 0 2006.280.08:05:03.42#ibcon#about to read 5, iclass 36, count 0 2006.280.08:05:03.42#ibcon#read 5, iclass 36, count 0 2006.280.08:05:03.42#ibcon#about to read 6, iclass 36, count 0 2006.280.08:05:03.42#ibcon#read 6, iclass 36, count 0 2006.280.08:05:03.42#ibcon#end of sib2, iclass 36, count 0 2006.280.08:05:03.42#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:05:03.42#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:05:03.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:05:03.42#ibcon#*before write, iclass 36, count 0 2006.280.08:05:03.42#ibcon#enter sib2, iclass 36, count 0 2006.280.08:05:03.42#ibcon#flushed, iclass 36, count 0 2006.280.08:05:03.42#ibcon#about to write, iclass 36, count 0 2006.280.08:05:03.42#ibcon#wrote, iclass 36, count 0 2006.280.08:05:03.42#ibcon#about to read 3, iclass 36, count 0 2006.280.08:05:03.46#ibcon#read 3, iclass 36, count 0 2006.280.08:05:03.46#ibcon#about to read 4, iclass 36, count 0 2006.280.08:05:03.46#ibcon#read 4, iclass 36, count 0 2006.280.08:05:03.46#ibcon#about to read 5, iclass 36, count 0 2006.280.08:05:03.46#ibcon#read 5, iclass 36, count 0 2006.280.08:05:03.46#ibcon#about to read 6, iclass 36, count 0 2006.280.08:05:03.46#ibcon#read 6, iclass 36, count 0 2006.280.08:05:03.46#ibcon#end of sib2, iclass 36, count 0 2006.280.08:05:03.46#ibcon#*after write, iclass 36, count 0 2006.280.08:05:03.46#ibcon#*before return 0, iclass 36, count 0 2006.280.08:05:03.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:05:03.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:05:03.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:05:03.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:05:03.46$vc4f8/va=8,6 2006.280.08:05:03.46#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.08:05:03.46#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.08:05:03.46#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:03.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:05:03.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:05:03.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:05:03.52#ibcon#enter wrdev, iclass 38, count 2 2006.280.08:05:03.52#ibcon#first serial, iclass 38, count 2 2006.280.08:05:03.52#ibcon#enter sib2, iclass 38, count 2 2006.280.08:05:03.52#ibcon#flushed, iclass 38, count 2 2006.280.08:05:03.52#ibcon#about to write, iclass 38, count 2 2006.280.08:05:03.52#ibcon#wrote, iclass 38, count 2 2006.280.08:05:03.52#ibcon#about to read 3, iclass 38, count 2 2006.280.08:05:03.54#ibcon#read 3, iclass 38, count 2 2006.280.08:05:03.54#ibcon#about to read 4, iclass 38, count 2 2006.280.08:05:03.54#ibcon#read 4, iclass 38, count 2 2006.280.08:05:03.54#ibcon#about to read 5, iclass 38, count 2 2006.280.08:05:03.54#ibcon#read 5, iclass 38, count 2 2006.280.08:05:03.54#ibcon#about to read 6, iclass 38, count 2 2006.280.08:05:03.54#ibcon#read 6, iclass 38, count 2 2006.280.08:05:03.54#ibcon#end of sib2, iclass 38, count 2 2006.280.08:05:03.54#ibcon#*mode == 0, iclass 38, count 2 2006.280.08:05:03.54#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.08:05:03.54#ibcon#[25=AT08-06\r\n] 2006.280.08:05:03.54#ibcon#*before write, iclass 38, count 2 2006.280.08:05:03.54#ibcon#enter sib2, iclass 38, count 2 2006.280.08:05:03.54#ibcon#flushed, iclass 38, count 2 2006.280.08:05:03.54#ibcon#about to write, iclass 38, count 2 2006.280.08:05:03.54#ibcon#wrote, iclass 38, count 2 2006.280.08:05:03.54#ibcon#about to read 3, iclass 38, count 2 2006.280.08:05:03.57#ibcon#read 3, iclass 38, count 2 2006.280.08:05:03.57#ibcon#about to read 4, iclass 38, count 2 2006.280.08:05:03.57#ibcon#read 4, iclass 38, count 2 2006.280.08:05:03.57#ibcon#about to read 5, iclass 38, count 2 2006.280.08:05:03.57#ibcon#read 5, iclass 38, count 2 2006.280.08:05:03.57#ibcon#about to read 6, iclass 38, count 2 2006.280.08:05:03.57#ibcon#read 6, iclass 38, count 2 2006.280.08:05:03.57#ibcon#end of sib2, iclass 38, count 2 2006.280.08:05:03.57#ibcon#*after write, iclass 38, count 2 2006.280.08:05:03.57#ibcon#*before return 0, iclass 38, count 2 2006.280.08:05:03.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:05:03.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:05:03.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.08:05:03.57#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:03.57#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:05:03.60#abcon#<5=/14 1.7 4.9 20.74 62 987.3\r\n> 2006.280.08:05:03.62#abcon#{5=INTERFACE CLEAR} 2006.280.08:05:03.68#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:05:03.69#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:05:03.69#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:05:03.69#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:05:03.69#ibcon#first serial, iclass 38, count 0 2006.280.08:05:03.69#ibcon#enter sib2, iclass 38, count 0 2006.280.08:05:03.69#ibcon#flushed, iclass 38, count 0 2006.280.08:05:03.69#ibcon#about to write, iclass 38, count 0 2006.280.08:05:03.69#ibcon#wrote, iclass 38, count 0 2006.280.08:05:03.69#ibcon#about to read 3, iclass 38, count 0 2006.280.08:05:03.71#ibcon#read 3, iclass 38, count 0 2006.280.08:05:03.71#ibcon#about to read 4, iclass 38, count 0 2006.280.08:05:03.71#ibcon#read 4, iclass 38, count 0 2006.280.08:05:03.71#ibcon#about to read 5, iclass 38, count 0 2006.280.08:05:03.71#ibcon#read 5, iclass 38, count 0 2006.280.08:05:03.71#ibcon#about to read 6, iclass 38, count 0 2006.280.08:05:03.71#ibcon#read 6, iclass 38, count 0 2006.280.08:05:03.71#ibcon#end of sib2, iclass 38, count 0 2006.280.08:05:03.71#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:05:03.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:05:03.71#ibcon#[25=USB\r\n] 2006.280.08:05:03.71#ibcon#*before write, iclass 38, count 0 2006.280.08:05:03.71#ibcon#enter sib2, iclass 38, count 0 2006.280.08:05:03.71#ibcon#flushed, iclass 38, count 0 2006.280.08:05:03.71#ibcon#about to write, iclass 38, count 0 2006.280.08:05:03.71#ibcon#wrote, iclass 38, count 0 2006.280.08:05:03.71#ibcon#about to read 3, iclass 38, count 0 2006.280.08:05:03.74#ibcon#read 3, iclass 38, count 0 2006.280.08:05:03.74#ibcon#about to read 4, iclass 38, count 0 2006.280.08:05:03.74#ibcon#read 4, iclass 38, count 0 2006.280.08:05:03.74#ibcon#about to read 5, iclass 38, count 0 2006.280.08:05:03.74#ibcon#read 5, iclass 38, count 0 2006.280.08:05:03.74#ibcon#about to read 6, iclass 38, count 0 2006.280.08:05:03.74#ibcon#read 6, iclass 38, count 0 2006.280.08:05:03.74#ibcon#end of sib2, iclass 38, count 0 2006.280.08:05:03.74#ibcon#*after write, iclass 38, count 0 2006.280.08:05:03.74#ibcon#*before return 0, iclass 38, count 0 2006.280.08:05:03.74#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:05:03.74#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:05:03.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:05:03.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:05:03.74$vc4f8/vblo=1,632.99 2006.280.08:05:03.74#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:05:03.74#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:05:03.74#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:03.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:03.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:03.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:03.74#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:05:03.74#ibcon#first serial, iclass 6, count 0 2006.280.08:05:03.74#ibcon#enter sib2, iclass 6, count 0 2006.280.08:05:03.74#ibcon#flushed, iclass 6, count 0 2006.280.08:05:03.74#ibcon#about to write, iclass 6, count 0 2006.280.08:05:03.74#ibcon#wrote, iclass 6, count 0 2006.280.08:05:03.74#ibcon#about to read 3, iclass 6, count 0 2006.280.08:05:03.76#ibcon#read 3, iclass 6, count 0 2006.280.08:05:03.76#ibcon#about to read 4, iclass 6, count 0 2006.280.08:05:03.76#ibcon#read 4, iclass 6, count 0 2006.280.08:05:03.76#ibcon#about to read 5, iclass 6, count 0 2006.280.08:05:03.76#ibcon#read 5, iclass 6, count 0 2006.280.08:05:03.76#ibcon#about to read 6, iclass 6, count 0 2006.280.08:05:03.76#ibcon#read 6, iclass 6, count 0 2006.280.08:05:03.76#ibcon#end of sib2, iclass 6, count 0 2006.280.08:05:03.76#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:05:03.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:05:03.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:05:03.76#ibcon#*before write, iclass 6, count 0 2006.280.08:05:03.76#ibcon#enter sib2, iclass 6, count 0 2006.280.08:05:03.76#ibcon#flushed, iclass 6, count 0 2006.280.08:05:03.76#ibcon#about to write, iclass 6, count 0 2006.280.08:05:03.76#ibcon#wrote, iclass 6, count 0 2006.280.08:05:03.76#ibcon#about to read 3, iclass 6, count 0 2006.280.08:05:03.80#ibcon#read 3, iclass 6, count 0 2006.280.08:05:03.80#ibcon#about to read 4, iclass 6, count 0 2006.280.08:05:03.80#ibcon#read 4, iclass 6, count 0 2006.280.08:05:03.80#ibcon#about to read 5, iclass 6, count 0 2006.280.08:05:03.80#ibcon#read 5, iclass 6, count 0 2006.280.08:05:03.80#ibcon#about to read 6, iclass 6, count 0 2006.280.08:05:03.80#ibcon#read 6, iclass 6, count 0 2006.280.08:05:03.80#ibcon#end of sib2, iclass 6, count 0 2006.280.08:05:03.80#ibcon#*after write, iclass 6, count 0 2006.280.08:05:03.80#ibcon#*before return 0, iclass 6, count 0 2006.280.08:05:03.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:03.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:05:03.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:05:03.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:05:03.80$vc4f8/vb=1,4 2006.280.08:05:03.80#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.08:05:03.80#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.08:05:03.80#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:03.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:03.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:03.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:03.80#ibcon#enter wrdev, iclass 10, count 2 2006.280.08:05:03.80#ibcon#first serial, iclass 10, count 2 2006.280.08:05:03.80#ibcon#enter sib2, iclass 10, count 2 2006.280.08:05:03.80#ibcon#flushed, iclass 10, count 2 2006.280.08:05:03.80#ibcon#about to write, iclass 10, count 2 2006.280.08:05:03.80#ibcon#wrote, iclass 10, count 2 2006.280.08:05:03.80#ibcon#about to read 3, iclass 10, count 2 2006.280.08:05:03.82#ibcon#read 3, iclass 10, count 2 2006.280.08:05:03.86#ibcon#about to read 4, iclass 10, count 2 2006.280.08:05:03.86#ibcon#read 4, iclass 10, count 2 2006.280.08:05:03.86#ibcon#about to read 5, iclass 10, count 2 2006.280.08:05:03.86#ibcon#read 5, iclass 10, count 2 2006.280.08:05:03.86#ibcon#about to read 6, iclass 10, count 2 2006.280.08:05:03.86#ibcon#read 6, iclass 10, count 2 2006.280.08:05:03.86#ibcon#end of sib2, iclass 10, count 2 2006.280.08:05:03.86#ibcon#*mode == 0, iclass 10, count 2 2006.280.08:05:03.86#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.08:05:03.86#ibcon#[27=AT01-04\r\n] 2006.280.08:05:03.86#ibcon#*before write, iclass 10, count 2 2006.280.08:05:03.86#ibcon#enter sib2, iclass 10, count 2 2006.280.08:05:03.86#ibcon#flushed, iclass 10, count 2 2006.280.08:05:03.86#ibcon#about to write, iclass 10, count 2 2006.280.08:05:03.86#ibcon#wrote, iclass 10, count 2 2006.280.08:05:03.86#ibcon#about to read 3, iclass 10, count 2 2006.280.08:05:03.89#ibcon#read 3, iclass 10, count 2 2006.280.08:05:03.89#ibcon#about to read 4, iclass 10, count 2 2006.280.08:05:03.89#ibcon#read 4, iclass 10, count 2 2006.280.08:05:03.89#ibcon#about to read 5, iclass 10, count 2 2006.280.08:05:03.89#ibcon#read 5, iclass 10, count 2 2006.280.08:05:03.89#ibcon#about to read 6, iclass 10, count 2 2006.280.08:05:03.89#ibcon#read 6, iclass 10, count 2 2006.280.08:05:03.89#ibcon#end of sib2, iclass 10, count 2 2006.280.08:05:03.89#ibcon#*after write, iclass 10, count 2 2006.280.08:05:03.89#ibcon#*before return 0, iclass 10, count 2 2006.280.08:05:03.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:03.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:05:03.89#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.08:05:03.89#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:03.89#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:04.01#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:04.01#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:04.01#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:05:04.01#ibcon#first serial, iclass 10, count 0 2006.280.08:05:04.01#ibcon#enter sib2, iclass 10, count 0 2006.280.08:05:04.01#ibcon#flushed, iclass 10, count 0 2006.280.08:05:04.01#ibcon#about to write, iclass 10, count 0 2006.280.08:05:04.01#ibcon#wrote, iclass 10, count 0 2006.280.08:05:04.01#ibcon#about to read 3, iclass 10, count 0 2006.280.08:05:04.03#ibcon#read 3, iclass 10, count 0 2006.280.08:05:04.03#ibcon#about to read 4, iclass 10, count 0 2006.280.08:05:04.03#ibcon#read 4, iclass 10, count 0 2006.280.08:05:04.03#ibcon#about to read 5, iclass 10, count 0 2006.280.08:05:04.03#ibcon#read 5, iclass 10, count 0 2006.280.08:05:04.03#ibcon#about to read 6, iclass 10, count 0 2006.280.08:05:04.03#ibcon#read 6, iclass 10, count 0 2006.280.08:05:04.03#ibcon#end of sib2, iclass 10, count 0 2006.280.08:05:04.03#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:05:04.03#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:05:04.03#ibcon#[27=USB\r\n] 2006.280.08:05:04.03#ibcon#*before write, iclass 10, count 0 2006.280.08:05:04.03#ibcon#enter sib2, iclass 10, count 0 2006.280.08:05:04.03#ibcon#flushed, iclass 10, count 0 2006.280.08:05:04.03#ibcon#about to write, iclass 10, count 0 2006.280.08:05:04.03#ibcon#wrote, iclass 10, count 0 2006.280.08:05:04.03#ibcon#about to read 3, iclass 10, count 0 2006.280.08:05:04.06#ibcon#read 3, iclass 10, count 0 2006.280.08:05:04.06#ibcon#about to read 4, iclass 10, count 0 2006.280.08:05:04.06#ibcon#read 4, iclass 10, count 0 2006.280.08:05:04.06#ibcon#about to read 5, iclass 10, count 0 2006.280.08:05:04.06#ibcon#read 5, iclass 10, count 0 2006.280.08:05:04.06#ibcon#about to read 6, iclass 10, count 0 2006.280.08:05:04.06#ibcon#read 6, iclass 10, count 0 2006.280.08:05:04.06#ibcon#end of sib2, iclass 10, count 0 2006.280.08:05:04.06#ibcon#*after write, iclass 10, count 0 2006.280.08:05:04.06#ibcon#*before return 0, iclass 10, count 0 2006.280.08:05:04.06#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:04.06#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:05:04.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:05:04.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:05:04.06$vc4f8/vblo=2,640.99 2006.280.08:05:04.06#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:05:04.06#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:05:04.06#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:04.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:04.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:04.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:04.06#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:05:04.06#ibcon#first serial, iclass 12, count 0 2006.280.08:05:04.06#ibcon#enter sib2, iclass 12, count 0 2006.280.08:05:04.06#ibcon#flushed, iclass 12, count 0 2006.280.08:05:04.06#ibcon#about to write, iclass 12, count 0 2006.280.08:05:04.06#ibcon#wrote, iclass 12, count 0 2006.280.08:05:04.06#ibcon#about to read 3, iclass 12, count 0 2006.280.08:05:04.08#ibcon#read 3, iclass 12, count 0 2006.280.08:05:04.08#ibcon#about to read 4, iclass 12, count 0 2006.280.08:05:04.08#ibcon#read 4, iclass 12, count 0 2006.280.08:05:04.08#ibcon#about to read 5, iclass 12, count 0 2006.280.08:05:04.08#ibcon#read 5, iclass 12, count 0 2006.280.08:05:04.08#ibcon#about to read 6, iclass 12, count 0 2006.280.08:05:04.08#ibcon#read 6, iclass 12, count 0 2006.280.08:05:04.08#ibcon#end of sib2, iclass 12, count 0 2006.280.08:05:04.08#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:05:04.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:05:04.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:05:04.08#ibcon#*before write, iclass 12, count 0 2006.280.08:05:04.08#ibcon#enter sib2, iclass 12, count 0 2006.280.08:05:04.08#ibcon#flushed, iclass 12, count 0 2006.280.08:05:04.08#ibcon#about to write, iclass 12, count 0 2006.280.08:05:04.08#ibcon#wrote, iclass 12, count 0 2006.280.08:05:04.08#ibcon#about to read 3, iclass 12, count 0 2006.280.08:05:04.12#ibcon#read 3, iclass 12, count 0 2006.280.08:05:04.12#ibcon#about to read 4, iclass 12, count 0 2006.280.08:05:04.12#ibcon#read 4, iclass 12, count 0 2006.280.08:05:04.12#ibcon#about to read 5, iclass 12, count 0 2006.280.08:05:04.12#ibcon#read 5, iclass 12, count 0 2006.280.08:05:04.12#ibcon#about to read 6, iclass 12, count 0 2006.280.08:05:04.12#ibcon#read 6, iclass 12, count 0 2006.280.08:05:04.12#ibcon#end of sib2, iclass 12, count 0 2006.280.08:05:04.12#ibcon#*after write, iclass 12, count 0 2006.280.08:05:04.12#ibcon#*before return 0, iclass 12, count 0 2006.280.08:05:04.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:04.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:05:04.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:05:04.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:05:04.12$vc4f8/vb=2,5 2006.280.08:05:04.12#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:05:04.12#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:05:04.12#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:04.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:04.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:04.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:04.18#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:05:04.18#ibcon#first serial, iclass 14, count 2 2006.280.08:05:04.18#ibcon#enter sib2, iclass 14, count 2 2006.280.08:05:04.18#ibcon#flushed, iclass 14, count 2 2006.280.08:05:04.18#ibcon#about to write, iclass 14, count 2 2006.280.08:05:04.18#ibcon#wrote, iclass 14, count 2 2006.280.08:05:04.18#ibcon#about to read 3, iclass 14, count 2 2006.280.08:05:04.20#ibcon#read 3, iclass 14, count 2 2006.280.08:05:04.20#ibcon#about to read 4, iclass 14, count 2 2006.280.08:05:04.20#ibcon#read 4, iclass 14, count 2 2006.280.08:05:04.20#ibcon#about to read 5, iclass 14, count 2 2006.280.08:05:04.20#ibcon#read 5, iclass 14, count 2 2006.280.08:05:04.20#ibcon#about to read 6, iclass 14, count 2 2006.280.08:05:04.20#ibcon#read 6, iclass 14, count 2 2006.280.08:05:04.20#ibcon#end of sib2, iclass 14, count 2 2006.280.08:05:04.20#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:05:04.20#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:05:04.20#ibcon#[27=AT02-05\r\n] 2006.280.08:05:04.20#ibcon#*before write, iclass 14, count 2 2006.280.08:05:04.20#ibcon#enter sib2, iclass 14, count 2 2006.280.08:05:04.20#ibcon#flushed, iclass 14, count 2 2006.280.08:05:04.20#ibcon#about to write, iclass 14, count 2 2006.280.08:05:04.20#ibcon#wrote, iclass 14, count 2 2006.280.08:05:04.20#ibcon#about to read 3, iclass 14, count 2 2006.280.08:05:04.23#ibcon#read 3, iclass 14, count 2 2006.280.08:05:04.23#ibcon#about to read 4, iclass 14, count 2 2006.280.08:05:04.23#ibcon#read 4, iclass 14, count 2 2006.280.08:05:04.23#ibcon#about to read 5, iclass 14, count 2 2006.280.08:05:04.23#ibcon#read 5, iclass 14, count 2 2006.280.08:05:04.23#ibcon#about to read 6, iclass 14, count 2 2006.280.08:05:04.23#ibcon#read 6, iclass 14, count 2 2006.280.08:05:04.23#ibcon#end of sib2, iclass 14, count 2 2006.280.08:05:04.23#ibcon#*after write, iclass 14, count 2 2006.280.08:05:04.23#ibcon#*before return 0, iclass 14, count 2 2006.280.08:05:04.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:04.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:05:04.23#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:05:04.23#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:04.23#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:04.35#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:04.35#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:04.35#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:05:04.35#ibcon#first serial, iclass 14, count 0 2006.280.08:05:04.35#ibcon#enter sib2, iclass 14, count 0 2006.280.08:05:04.35#ibcon#flushed, iclass 14, count 0 2006.280.08:05:04.35#ibcon#about to write, iclass 14, count 0 2006.280.08:05:04.35#ibcon#wrote, iclass 14, count 0 2006.280.08:05:04.35#ibcon#about to read 3, iclass 14, count 0 2006.280.08:05:04.37#ibcon#read 3, iclass 14, count 0 2006.280.08:05:04.37#ibcon#about to read 4, iclass 14, count 0 2006.280.08:05:04.37#ibcon#read 4, iclass 14, count 0 2006.280.08:05:04.37#ibcon#about to read 5, iclass 14, count 0 2006.280.08:05:04.37#ibcon#read 5, iclass 14, count 0 2006.280.08:05:04.37#ibcon#about to read 6, iclass 14, count 0 2006.280.08:05:04.37#ibcon#read 6, iclass 14, count 0 2006.280.08:05:04.37#ibcon#end of sib2, iclass 14, count 0 2006.280.08:05:04.37#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:05:04.37#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:05:04.37#ibcon#[27=USB\r\n] 2006.280.08:05:04.37#ibcon#*before write, iclass 14, count 0 2006.280.08:05:04.37#ibcon#enter sib2, iclass 14, count 0 2006.280.08:05:04.37#ibcon#flushed, iclass 14, count 0 2006.280.08:05:04.37#ibcon#about to write, iclass 14, count 0 2006.280.08:05:04.37#ibcon#wrote, iclass 14, count 0 2006.280.08:05:04.37#ibcon#about to read 3, iclass 14, count 0 2006.280.08:05:04.40#ibcon#read 3, iclass 14, count 0 2006.280.08:05:04.40#ibcon#about to read 4, iclass 14, count 0 2006.280.08:05:04.40#ibcon#read 4, iclass 14, count 0 2006.280.08:05:04.40#ibcon#about to read 5, iclass 14, count 0 2006.280.08:05:04.40#ibcon#read 5, iclass 14, count 0 2006.280.08:05:04.40#ibcon#about to read 6, iclass 14, count 0 2006.280.08:05:04.40#ibcon#read 6, iclass 14, count 0 2006.280.08:05:04.40#ibcon#end of sib2, iclass 14, count 0 2006.280.08:05:04.40#ibcon#*after write, iclass 14, count 0 2006.280.08:05:04.40#ibcon#*before return 0, iclass 14, count 0 2006.280.08:05:04.40#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:04.40#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:05:04.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:05:04.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:05:04.40$vc4f8/vblo=3,656.99 2006.280.08:05:04.40#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:05:04.40#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:05:04.40#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:04.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:04.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:04.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:04.40#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:05:04.40#ibcon#first serial, iclass 16, count 0 2006.280.08:05:04.40#ibcon#enter sib2, iclass 16, count 0 2006.280.08:05:04.40#ibcon#flushed, iclass 16, count 0 2006.280.08:05:04.40#ibcon#about to write, iclass 16, count 0 2006.280.08:05:04.40#ibcon#wrote, iclass 16, count 0 2006.280.08:05:04.40#ibcon#about to read 3, iclass 16, count 0 2006.280.08:05:04.42#ibcon#read 3, iclass 16, count 0 2006.280.08:05:04.42#ibcon#about to read 4, iclass 16, count 0 2006.280.08:05:04.42#ibcon#read 4, iclass 16, count 0 2006.280.08:05:04.42#ibcon#about to read 5, iclass 16, count 0 2006.280.08:05:04.42#ibcon#read 5, iclass 16, count 0 2006.280.08:05:04.42#ibcon#about to read 6, iclass 16, count 0 2006.280.08:05:04.42#ibcon#read 6, iclass 16, count 0 2006.280.08:05:04.42#ibcon#end of sib2, iclass 16, count 0 2006.280.08:05:04.42#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:05:04.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:05:04.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:05:04.42#ibcon#*before write, iclass 16, count 0 2006.280.08:05:04.42#ibcon#enter sib2, iclass 16, count 0 2006.280.08:05:04.42#ibcon#flushed, iclass 16, count 0 2006.280.08:05:04.42#ibcon#about to write, iclass 16, count 0 2006.280.08:05:04.42#ibcon#wrote, iclass 16, count 0 2006.280.08:05:04.42#ibcon#about to read 3, iclass 16, count 0 2006.280.08:05:04.46#ibcon#read 3, iclass 16, count 0 2006.280.08:05:04.46#ibcon#about to read 4, iclass 16, count 0 2006.280.08:05:04.46#ibcon#read 4, iclass 16, count 0 2006.280.08:05:04.46#ibcon#about to read 5, iclass 16, count 0 2006.280.08:05:04.46#ibcon#read 5, iclass 16, count 0 2006.280.08:05:04.46#ibcon#about to read 6, iclass 16, count 0 2006.280.08:05:04.46#ibcon#read 6, iclass 16, count 0 2006.280.08:05:04.46#ibcon#end of sib2, iclass 16, count 0 2006.280.08:05:04.46#ibcon#*after write, iclass 16, count 0 2006.280.08:05:04.46#ibcon#*before return 0, iclass 16, count 0 2006.280.08:05:04.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:04.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:05:04.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:05:04.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:05:04.46$vc4f8/vb=3,4 2006.280.08:05:04.46#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:05:04.46#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:05:04.46#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:04.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:04.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:04.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:04.52#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:05:04.52#ibcon#first serial, iclass 18, count 2 2006.280.08:05:04.52#ibcon#enter sib2, iclass 18, count 2 2006.280.08:05:04.52#ibcon#flushed, iclass 18, count 2 2006.280.08:05:04.52#ibcon#about to write, iclass 18, count 2 2006.280.08:05:04.52#ibcon#wrote, iclass 18, count 2 2006.280.08:05:04.52#ibcon#about to read 3, iclass 18, count 2 2006.280.08:05:04.55#ibcon#read 3, iclass 18, count 2 2006.280.08:05:04.55#ibcon#about to read 4, iclass 18, count 2 2006.280.08:05:04.55#ibcon#read 4, iclass 18, count 2 2006.280.08:05:04.55#ibcon#about to read 5, iclass 18, count 2 2006.280.08:05:04.55#ibcon#read 5, iclass 18, count 2 2006.280.08:05:04.55#ibcon#about to read 6, iclass 18, count 2 2006.280.08:05:04.55#ibcon#read 6, iclass 18, count 2 2006.280.08:05:04.55#ibcon#end of sib2, iclass 18, count 2 2006.280.08:05:04.55#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:05:04.55#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:05:04.55#ibcon#[27=AT03-04\r\n] 2006.280.08:05:04.55#ibcon#*before write, iclass 18, count 2 2006.280.08:05:04.55#ibcon#enter sib2, iclass 18, count 2 2006.280.08:05:04.55#ibcon#flushed, iclass 18, count 2 2006.280.08:05:04.55#ibcon#about to write, iclass 18, count 2 2006.280.08:05:04.55#ibcon#wrote, iclass 18, count 2 2006.280.08:05:04.55#ibcon#about to read 3, iclass 18, count 2 2006.280.08:05:04.58#ibcon#read 3, iclass 18, count 2 2006.280.08:05:04.58#ibcon#about to read 4, iclass 18, count 2 2006.280.08:05:04.58#ibcon#read 4, iclass 18, count 2 2006.280.08:05:04.58#ibcon#about to read 5, iclass 18, count 2 2006.280.08:05:04.58#ibcon#read 5, iclass 18, count 2 2006.280.08:05:04.58#ibcon#about to read 6, iclass 18, count 2 2006.280.08:05:04.58#ibcon#read 6, iclass 18, count 2 2006.280.08:05:04.58#ibcon#end of sib2, iclass 18, count 2 2006.280.08:05:04.58#ibcon#*after write, iclass 18, count 2 2006.280.08:05:04.58#ibcon#*before return 0, iclass 18, count 2 2006.280.08:05:04.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:04.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:05:04.58#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:05:04.58#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:04.58#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:04.70#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:04.70#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:04.70#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:05:04.70#ibcon#first serial, iclass 18, count 0 2006.280.08:05:04.70#ibcon#enter sib2, iclass 18, count 0 2006.280.08:05:04.70#ibcon#flushed, iclass 18, count 0 2006.280.08:05:04.70#ibcon#about to write, iclass 18, count 0 2006.280.08:05:04.70#ibcon#wrote, iclass 18, count 0 2006.280.08:05:04.70#ibcon#about to read 3, iclass 18, count 0 2006.280.08:05:04.72#ibcon#read 3, iclass 18, count 0 2006.280.08:05:04.72#ibcon#about to read 4, iclass 18, count 0 2006.280.08:05:04.72#ibcon#read 4, iclass 18, count 0 2006.280.08:05:04.72#ibcon#about to read 5, iclass 18, count 0 2006.280.08:05:04.72#ibcon#read 5, iclass 18, count 0 2006.280.08:05:04.72#ibcon#about to read 6, iclass 18, count 0 2006.280.08:05:04.72#ibcon#read 6, iclass 18, count 0 2006.280.08:05:04.72#ibcon#end of sib2, iclass 18, count 0 2006.280.08:05:04.72#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:05:04.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:05:04.72#ibcon#[27=USB\r\n] 2006.280.08:05:04.72#ibcon#*before write, iclass 18, count 0 2006.280.08:05:04.72#ibcon#enter sib2, iclass 18, count 0 2006.280.08:05:04.72#ibcon#flushed, iclass 18, count 0 2006.280.08:05:04.72#ibcon#about to write, iclass 18, count 0 2006.280.08:05:04.72#ibcon#wrote, iclass 18, count 0 2006.280.08:05:04.72#ibcon#about to read 3, iclass 18, count 0 2006.280.08:05:04.75#ibcon#read 3, iclass 18, count 0 2006.280.08:05:04.75#ibcon#about to read 4, iclass 18, count 0 2006.280.08:05:04.75#ibcon#read 4, iclass 18, count 0 2006.280.08:05:04.75#ibcon#about to read 5, iclass 18, count 0 2006.280.08:05:04.75#ibcon#read 5, iclass 18, count 0 2006.280.08:05:04.75#ibcon#about to read 6, iclass 18, count 0 2006.280.08:05:04.75#ibcon#read 6, iclass 18, count 0 2006.280.08:05:04.75#ibcon#end of sib2, iclass 18, count 0 2006.280.08:05:04.75#ibcon#*after write, iclass 18, count 0 2006.280.08:05:04.75#ibcon#*before return 0, iclass 18, count 0 2006.280.08:05:04.75#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:04.75#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:05:04.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:05:04.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:05:04.75$vc4f8/vblo=4,712.99 2006.280.08:05:04.75#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:05:04.75#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:05:04.75#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:04.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:04.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:04.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:04.75#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:05:04.75#ibcon#first serial, iclass 20, count 0 2006.280.08:05:04.75#ibcon#enter sib2, iclass 20, count 0 2006.280.08:05:04.75#ibcon#flushed, iclass 20, count 0 2006.280.08:05:04.75#ibcon#about to write, iclass 20, count 0 2006.280.08:05:04.75#ibcon#wrote, iclass 20, count 0 2006.280.08:05:04.75#ibcon#about to read 3, iclass 20, count 0 2006.280.08:05:04.77#ibcon#read 3, iclass 20, count 0 2006.280.08:05:04.77#ibcon#about to read 4, iclass 20, count 0 2006.280.08:05:04.77#ibcon#read 4, iclass 20, count 0 2006.280.08:05:04.77#ibcon#about to read 5, iclass 20, count 0 2006.280.08:05:04.77#ibcon#read 5, iclass 20, count 0 2006.280.08:05:04.77#ibcon#about to read 6, iclass 20, count 0 2006.280.08:05:04.77#ibcon#read 6, iclass 20, count 0 2006.280.08:05:04.77#ibcon#end of sib2, iclass 20, count 0 2006.280.08:05:04.77#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:05:04.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:05:04.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:05:04.77#ibcon#*before write, iclass 20, count 0 2006.280.08:05:04.77#ibcon#enter sib2, iclass 20, count 0 2006.280.08:05:04.77#ibcon#flushed, iclass 20, count 0 2006.280.08:05:04.77#ibcon#about to write, iclass 20, count 0 2006.280.08:05:04.77#ibcon#wrote, iclass 20, count 0 2006.280.08:05:04.77#ibcon#about to read 3, iclass 20, count 0 2006.280.08:05:04.81#ibcon#read 3, iclass 20, count 0 2006.280.08:05:04.81#ibcon#about to read 4, iclass 20, count 0 2006.280.08:05:04.81#ibcon#read 4, iclass 20, count 0 2006.280.08:05:04.81#ibcon#about to read 5, iclass 20, count 0 2006.280.08:05:04.81#ibcon#read 5, iclass 20, count 0 2006.280.08:05:04.81#ibcon#about to read 6, iclass 20, count 0 2006.280.08:05:04.81#ibcon#read 6, iclass 20, count 0 2006.280.08:05:04.81#ibcon#end of sib2, iclass 20, count 0 2006.280.08:05:04.81#ibcon#*after write, iclass 20, count 0 2006.280.08:05:04.81#ibcon#*before return 0, iclass 20, count 0 2006.280.08:05:04.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:04.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:05:04.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:05:04.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:05:04.81$vc4f8/vb=4,4 2006.280.08:05:04.81#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.08:05:04.81#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.08:05:04.81#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:04.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:04.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:04.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:04.87#ibcon#enter wrdev, iclass 22, count 2 2006.280.08:05:04.87#ibcon#first serial, iclass 22, count 2 2006.280.08:05:04.87#ibcon#enter sib2, iclass 22, count 2 2006.280.08:05:04.87#ibcon#flushed, iclass 22, count 2 2006.280.08:05:04.87#ibcon#about to write, iclass 22, count 2 2006.280.08:05:04.87#ibcon#wrote, iclass 22, count 2 2006.280.08:05:04.87#ibcon#about to read 3, iclass 22, count 2 2006.280.08:05:04.89#ibcon#read 3, iclass 22, count 2 2006.280.08:05:04.89#ibcon#about to read 4, iclass 22, count 2 2006.280.08:05:04.89#ibcon#read 4, iclass 22, count 2 2006.280.08:05:04.89#ibcon#about to read 5, iclass 22, count 2 2006.280.08:05:04.89#ibcon#read 5, iclass 22, count 2 2006.280.08:05:04.89#ibcon#about to read 6, iclass 22, count 2 2006.280.08:05:04.89#ibcon#read 6, iclass 22, count 2 2006.280.08:05:04.89#ibcon#end of sib2, iclass 22, count 2 2006.280.08:05:04.89#ibcon#*mode == 0, iclass 22, count 2 2006.280.08:05:04.89#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.08:05:04.89#ibcon#[27=AT04-04\r\n] 2006.280.08:05:04.89#ibcon#*before write, iclass 22, count 2 2006.280.08:05:04.89#ibcon#enter sib2, iclass 22, count 2 2006.280.08:05:04.89#ibcon#flushed, iclass 22, count 2 2006.280.08:05:04.89#ibcon#about to write, iclass 22, count 2 2006.280.08:05:04.89#ibcon#wrote, iclass 22, count 2 2006.280.08:05:04.89#ibcon#about to read 3, iclass 22, count 2 2006.280.08:05:04.92#ibcon#read 3, iclass 22, count 2 2006.280.08:05:04.92#ibcon#about to read 4, iclass 22, count 2 2006.280.08:05:04.92#ibcon#read 4, iclass 22, count 2 2006.280.08:05:04.92#ibcon#about to read 5, iclass 22, count 2 2006.280.08:05:04.92#ibcon#read 5, iclass 22, count 2 2006.280.08:05:04.92#ibcon#about to read 6, iclass 22, count 2 2006.280.08:05:04.92#ibcon#read 6, iclass 22, count 2 2006.280.08:05:04.92#ibcon#end of sib2, iclass 22, count 2 2006.280.08:05:04.92#ibcon#*after write, iclass 22, count 2 2006.280.08:05:04.92#ibcon#*before return 0, iclass 22, count 2 2006.280.08:05:04.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:04.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:05:04.92#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.08:05:04.92#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:04.92#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:05.04#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:05.04#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:05.04#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:05:05.04#ibcon#first serial, iclass 22, count 0 2006.280.08:05:05.04#ibcon#enter sib2, iclass 22, count 0 2006.280.08:05:05.04#ibcon#flushed, iclass 22, count 0 2006.280.08:05:05.04#ibcon#about to write, iclass 22, count 0 2006.280.08:05:05.04#ibcon#wrote, iclass 22, count 0 2006.280.08:05:05.04#ibcon#about to read 3, iclass 22, count 0 2006.280.08:05:05.06#ibcon#read 3, iclass 22, count 0 2006.280.08:05:05.06#ibcon#about to read 4, iclass 22, count 0 2006.280.08:05:05.06#ibcon#read 4, iclass 22, count 0 2006.280.08:05:05.06#ibcon#about to read 5, iclass 22, count 0 2006.280.08:05:05.06#ibcon#read 5, iclass 22, count 0 2006.280.08:05:05.06#ibcon#about to read 6, iclass 22, count 0 2006.280.08:05:05.06#ibcon#read 6, iclass 22, count 0 2006.280.08:05:05.06#ibcon#end of sib2, iclass 22, count 0 2006.280.08:05:05.06#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:05:05.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:05:05.06#ibcon#[27=USB\r\n] 2006.280.08:05:05.06#ibcon#*before write, iclass 22, count 0 2006.280.08:05:05.06#ibcon#enter sib2, iclass 22, count 0 2006.280.08:05:05.06#ibcon#flushed, iclass 22, count 0 2006.280.08:05:05.06#ibcon#about to write, iclass 22, count 0 2006.280.08:05:05.06#ibcon#wrote, iclass 22, count 0 2006.280.08:05:05.06#ibcon#about to read 3, iclass 22, count 0 2006.280.08:05:05.09#ibcon#read 3, iclass 22, count 0 2006.280.08:05:05.09#ibcon#about to read 4, iclass 22, count 0 2006.280.08:05:05.09#ibcon#read 4, iclass 22, count 0 2006.280.08:05:05.09#ibcon#about to read 5, iclass 22, count 0 2006.280.08:05:05.09#ibcon#read 5, iclass 22, count 0 2006.280.08:05:05.09#ibcon#about to read 6, iclass 22, count 0 2006.280.08:05:05.09#ibcon#read 6, iclass 22, count 0 2006.280.08:05:05.09#ibcon#end of sib2, iclass 22, count 0 2006.280.08:05:05.09#ibcon#*after write, iclass 22, count 0 2006.280.08:05:05.09#ibcon#*before return 0, iclass 22, count 0 2006.280.08:05:05.09#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:05.09#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:05:05.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:05:05.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:05:05.09$vc4f8/vblo=5,744.99 2006.280.08:05:05.09#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:05:05.09#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:05:05.09#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:05.09#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:05.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:05.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:05.09#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:05:05.09#ibcon#first serial, iclass 24, count 0 2006.280.08:05:05.09#ibcon#enter sib2, iclass 24, count 0 2006.280.08:05:05.09#ibcon#flushed, iclass 24, count 0 2006.280.08:05:05.09#ibcon#about to write, iclass 24, count 0 2006.280.08:05:05.09#ibcon#wrote, iclass 24, count 0 2006.280.08:05:05.09#ibcon#about to read 3, iclass 24, count 0 2006.280.08:05:05.11#ibcon#read 3, iclass 24, count 0 2006.280.08:05:05.11#ibcon#about to read 4, iclass 24, count 0 2006.280.08:05:05.11#ibcon#read 4, iclass 24, count 0 2006.280.08:05:05.11#ibcon#about to read 5, iclass 24, count 0 2006.280.08:05:05.11#ibcon#read 5, iclass 24, count 0 2006.280.08:05:05.11#ibcon#about to read 6, iclass 24, count 0 2006.280.08:05:05.11#ibcon#read 6, iclass 24, count 0 2006.280.08:05:05.11#ibcon#end of sib2, iclass 24, count 0 2006.280.08:05:05.11#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:05:05.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:05:05.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:05:05.11#ibcon#*before write, iclass 24, count 0 2006.280.08:05:05.11#ibcon#enter sib2, iclass 24, count 0 2006.280.08:05:05.11#ibcon#flushed, iclass 24, count 0 2006.280.08:05:05.11#ibcon#about to write, iclass 24, count 0 2006.280.08:05:05.11#ibcon#wrote, iclass 24, count 0 2006.280.08:05:05.11#ibcon#about to read 3, iclass 24, count 0 2006.280.08:05:05.15#ibcon#read 3, iclass 24, count 0 2006.280.08:05:05.15#ibcon#about to read 4, iclass 24, count 0 2006.280.08:05:05.15#ibcon#read 4, iclass 24, count 0 2006.280.08:05:05.15#ibcon#about to read 5, iclass 24, count 0 2006.280.08:05:05.15#ibcon#read 5, iclass 24, count 0 2006.280.08:05:05.15#ibcon#about to read 6, iclass 24, count 0 2006.280.08:05:05.15#ibcon#read 6, iclass 24, count 0 2006.280.08:05:05.15#ibcon#end of sib2, iclass 24, count 0 2006.280.08:05:05.15#ibcon#*after write, iclass 24, count 0 2006.280.08:05:05.15#ibcon#*before return 0, iclass 24, count 0 2006.280.08:05:05.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:05.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:05:05.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:05:05.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:05:05.15$vc4f8/vb=5,4 2006.280.08:05:05.15#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:05:05.15#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:05:05.15#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:05.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:05.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:05.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:05.21#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:05:05.21#ibcon#first serial, iclass 26, count 2 2006.280.08:05:05.21#ibcon#enter sib2, iclass 26, count 2 2006.280.08:05:05.21#ibcon#flushed, iclass 26, count 2 2006.280.08:05:05.21#ibcon#about to write, iclass 26, count 2 2006.280.08:05:05.21#ibcon#wrote, iclass 26, count 2 2006.280.08:05:05.21#ibcon#about to read 3, iclass 26, count 2 2006.280.08:05:05.23#ibcon#read 3, iclass 26, count 2 2006.280.08:05:05.23#ibcon#about to read 4, iclass 26, count 2 2006.280.08:05:05.23#ibcon#read 4, iclass 26, count 2 2006.280.08:05:05.23#ibcon#about to read 5, iclass 26, count 2 2006.280.08:05:05.23#ibcon#read 5, iclass 26, count 2 2006.280.08:05:05.23#ibcon#about to read 6, iclass 26, count 2 2006.280.08:05:05.23#ibcon#read 6, iclass 26, count 2 2006.280.08:05:05.23#ibcon#end of sib2, iclass 26, count 2 2006.280.08:05:05.23#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:05:05.23#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:05:05.23#ibcon#[27=AT05-04\r\n] 2006.280.08:05:05.23#ibcon#*before write, iclass 26, count 2 2006.280.08:05:05.23#ibcon#enter sib2, iclass 26, count 2 2006.280.08:05:05.23#ibcon#flushed, iclass 26, count 2 2006.280.08:05:05.23#ibcon#about to write, iclass 26, count 2 2006.280.08:05:05.23#ibcon#wrote, iclass 26, count 2 2006.280.08:05:05.23#ibcon#about to read 3, iclass 26, count 2 2006.280.08:05:05.26#ibcon#read 3, iclass 26, count 2 2006.280.08:05:05.26#ibcon#about to read 4, iclass 26, count 2 2006.280.08:05:05.26#ibcon#read 4, iclass 26, count 2 2006.280.08:05:05.26#ibcon#about to read 5, iclass 26, count 2 2006.280.08:05:05.26#ibcon#read 5, iclass 26, count 2 2006.280.08:05:05.26#ibcon#about to read 6, iclass 26, count 2 2006.280.08:05:05.26#ibcon#read 6, iclass 26, count 2 2006.280.08:05:05.26#ibcon#end of sib2, iclass 26, count 2 2006.280.08:05:05.26#ibcon#*after write, iclass 26, count 2 2006.280.08:05:05.26#ibcon#*before return 0, iclass 26, count 2 2006.280.08:05:05.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:05.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:05:05.26#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:05:05.26#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:05.26#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:05.38#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:05.38#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:05.38#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:05:05.38#ibcon#first serial, iclass 26, count 0 2006.280.08:05:05.38#ibcon#enter sib2, iclass 26, count 0 2006.280.08:05:05.38#ibcon#flushed, iclass 26, count 0 2006.280.08:05:05.38#ibcon#about to write, iclass 26, count 0 2006.280.08:05:05.38#ibcon#wrote, iclass 26, count 0 2006.280.08:05:05.38#ibcon#about to read 3, iclass 26, count 0 2006.280.08:05:05.40#ibcon#read 3, iclass 26, count 0 2006.280.08:05:05.40#ibcon#about to read 4, iclass 26, count 0 2006.280.08:05:05.40#ibcon#read 4, iclass 26, count 0 2006.280.08:05:05.40#ibcon#about to read 5, iclass 26, count 0 2006.280.08:05:05.40#ibcon#read 5, iclass 26, count 0 2006.280.08:05:05.40#ibcon#about to read 6, iclass 26, count 0 2006.280.08:05:05.40#ibcon#read 6, iclass 26, count 0 2006.280.08:05:05.40#ibcon#end of sib2, iclass 26, count 0 2006.280.08:05:05.40#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:05:05.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:05:05.40#ibcon#[27=USB\r\n] 2006.280.08:05:05.40#ibcon#*before write, iclass 26, count 0 2006.280.08:05:05.40#ibcon#enter sib2, iclass 26, count 0 2006.280.08:05:05.40#ibcon#flushed, iclass 26, count 0 2006.280.08:05:05.40#ibcon#about to write, iclass 26, count 0 2006.280.08:05:05.40#ibcon#wrote, iclass 26, count 0 2006.280.08:05:05.40#ibcon#about to read 3, iclass 26, count 0 2006.280.08:05:05.43#ibcon#read 3, iclass 26, count 0 2006.280.08:05:05.43#ibcon#about to read 4, iclass 26, count 0 2006.280.08:05:05.43#ibcon#read 4, iclass 26, count 0 2006.280.08:05:05.43#ibcon#about to read 5, iclass 26, count 0 2006.280.08:05:05.43#ibcon#read 5, iclass 26, count 0 2006.280.08:05:05.43#ibcon#about to read 6, iclass 26, count 0 2006.280.08:05:05.43#ibcon#read 6, iclass 26, count 0 2006.280.08:05:05.43#ibcon#end of sib2, iclass 26, count 0 2006.280.08:05:05.43#ibcon#*after write, iclass 26, count 0 2006.280.08:05:05.43#ibcon#*before return 0, iclass 26, count 0 2006.280.08:05:05.43#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:05.43#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:05:05.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:05:05.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:05:05.43$vc4f8/vblo=6,752.99 2006.280.08:05:05.43#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:05:05.43#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:05:05.43#ibcon#ireg 17 cls_cnt 0 2006.280.08:05:05.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:05.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:05.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:05.43#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:05:05.43#ibcon#first serial, iclass 28, count 0 2006.280.08:05:05.43#ibcon#enter sib2, iclass 28, count 0 2006.280.08:05:05.43#ibcon#flushed, iclass 28, count 0 2006.280.08:05:05.43#ibcon#about to write, iclass 28, count 0 2006.280.08:05:05.43#ibcon#wrote, iclass 28, count 0 2006.280.08:05:05.43#ibcon#about to read 3, iclass 28, count 0 2006.280.08:05:05.45#ibcon#read 3, iclass 28, count 0 2006.280.08:05:05.45#ibcon#about to read 4, iclass 28, count 0 2006.280.08:05:05.45#ibcon#read 4, iclass 28, count 0 2006.280.08:05:05.45#ibcon#about to read 5, iclass 28, count 0 2006.280.08:05:05.45#ibcon#read 5, iclass 28, count 0 2006.280.08:05:05.45#ibcon#about to read 6, iclass 28, count 0 2006.280.08:05:05.45#ibcon#read 6, iclass 28, count 0 2006.280.08:05:05.45#ibcon#end of sib2, iclass 28, count 0 2006.280.08:05:05.45#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:05:05.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:05:05.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:05:05.45#ibcon#*before write, iclass 28, count 0 2006.280.08:05:05.45#ibcon#enter sib2, iclass 28, count 0 2006.280.08:05:05.45#ibcon#flushed, iclass 28, count 0 2006.280.08:05:05.45#ibcon#about to write, iclass 28, count 0 2006.280.08:05:05.45#ibcon#wrote, iclass 28, count 0 2006.280.08:05:05.45#ibcon#about to read 3, iclass 28, count 0 2006.280.08:05:05.49#ibcon#read 3, iclass 28, count 0 2006.280.08:05:05.49#ibcon#about to read 4, iclass 28, count 0 2006.280.08:05:05.49#ibcon#read 4, iclass 28, count 0 2006.280.08:05:05.49#ibcon#about to read 5, iclass 28, count 0 2006.280.08:05:05.49#ibcon#read 5, iclass 28, count 0 2006.280.08:05:05.49#ibcon#about to read 6, iclass 28, count 0 2006.280.08:05:05.49#ibcon#read 6, iclass 28, count 0 2006.280.08:05:05.49#ibcon#end of sib2, iclass 28, count 0 2006.280.08:05:05.49#ibcon#*after write, iclass 28, count 0 2006.280.08:05:05.49#ibcon#*before return 0, iclass 28, count 0 2006.280.08:05:05.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:05.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:05:05.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:05:05.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:05:05.49$vc4f8/vb=6,4 2006.280.08:05:05.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.08:05:05.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.08:05:05.50#ibcon#ireg 11 cls_cnt 2 2006.280.08:05:05.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:05.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:05.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:05.54#ibcon#enter wrdev, iclass 30, count 2 2006.280.08:05:05.54#ibcon#first serial, iclass 30, count 2 2006.280.08:05:05.54#ibcon#enter sib2, iclass 30, count 2 2006.280.08:05:05.54#ibcon#flushed, iclass 30, count 2 2006.280.08:05:05.54#ibcon#about to write, iclass 30, count 2 2006.280.08:05:05.54#ibcon#wrote, iclass 30, count 2 2006.280.08:05:05.54#ibcon#about to read 3, iclass 30, count 2 2006.280.08:05:05.56#ibcon#read 3, iclass 30, count 2 2006.280.08:05:05.56#ibcon#about to read 4, iclass 30, count 2 2006.280.08:05:05.56#ibcon#read 4, iclass 30, count 2 2006.280.08:05:05.56#ibcon#about to read 5, iclass 30, count 2 2006.280.08:05:05.56#ibcon#read 5, iclass 30, count 2 2006.280.08:05:05.56#ibcon#about to read 6, iclass 30, count 2 2006.280.08:05:05.56#ibcon#read 6, iclass 30, count 2 2006.280.08:05:05.56#ibcon#end of sib2, iclass 30, count 2 2006.280.08:05:05.56#ibcon#*mode == 0, iclass 30, count 2 2006.280.08:05:05.56#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.08:05:05.56#ibcon#[27=AT06-04\r\n] 2006.280.08:05:05.56#ibcon#*before write, iclass 30, count 2 2006.280.08:05:05.56#ibcon#enter sib2, iclass 30, count 2 2006.280.08:05:05.56#ibcon#flushed, iclass 30, count 2 2006.280.08:05:05.56#ibcon#about to write, iclass 30, count 2 2006.280.08:05:05.56#ibcon#wrote, iclass 30, count 2 2006.280.08:05:05.56#ibcon#about to read 3, iclass 30, count 2 2006.280.08:05:05.59#ibcon#read 3, iclass 30, count 2 2006.280.08:05:05.59#ibcon#about to read 4, iclass 30, count 2 2006.280.08:05:05.59#ibcon#read 4, iclass 30, count 2 2006.280.08:05:05.59#ibcon#about to read 5, iclass 30, count 2 2006.280.08:05:05.59#ibcon#read 5, iclass 30, count 2 2006.280.08:05:05.59#ibcon#about to read 6, iclass 30, count 2 2006.280.08:05:05.59#ibcon#read 6, iclass 30, count 2 2006.280.08:05:05.59#ibcon#end of sib2, iclass 30, count 2 2006.280.08:05:05.59#ibcon#*after write, iclass 30, count 2 2006.280.08:05:05.59#ibcon#*before return 0, iclass 30, count 2 2006.280.08:05:05.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:05.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:05:05.59#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.08:05:05.59#ibcon#ireg 7 cls_cnt 0 2006.280.08:05:05.59#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:05.71#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:05.71#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:05.71#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:05:05.71#ibcon#first serial, iclass 30, count 0 2006.280.08:05:05.71#ibcon#enter sib2, iclass 30, count 0 2006.280.08:05:05.71#ibcon#flushed, iclass 30, count 0 2006.280.08:05:05.71#ibcon#about to write, iclass 30, count 0 2006.280.08:05:05.71#ibcon#wrote, iclass 30, count 0 2006.280.08:05:05.71#ibcon#about to read 3, iclass 30, count 0 2006.280.08:05:05.73#ibcon#read 3, iclass 30, count 0 2006.280.08:05:05.73#ibcon#about to read 4, iclass 30, count 0 2006.280.08:05:05.73#ibcon#read 4, iclass 30, count 0 2006.280.08:05:05.73#ibcon#about to read 5, iclass 30, count 0 2006.280.08:05:05.73#ibcon#read 5, iclass 30, count 0 2006.280.08:05:05.73#ibcon#about to read 6, iclass 30, count 0 2006.280.08:05:05.73#ibcon#read 6, iclass 30, count 0 2006.280.08:05:05.73#ibcon#end of sib2, iclass 30, count 0 2006.280.08:05:05.73#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:05:05.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:05:05.73#ibcon#[27=USB\r\n] 2006.280.08:05:05.73#ibcon#*before write, iclass 30, count 0 2006.280.08:05:05.73#ibcon#enter sib2, iclass 30, count 0 2006.280.08:05:05.73#ibcon#flushed, iclass 30, count 0 2006.280.08:05:05.73#ibcon#about to write, iclass 30, count 0 2006.280.08:05:05.73#ibcon#wrote, iclass 30, count 0 2006.280.08:05:05.73#ibcon#about to read 3, iclass 30, count 0 2006.280.08:05:05.76#ibcon#read 3, iclass 30, count 0 2006.280.08:05:05.76#ibcon#about to read 4, iclass 30, count 0 2006.280.08:05:05.76#ibcon#read 4, iclass 30, count 0 2006.280.08:05:05.76#ibcon#about to read 5, iclass 30, count 0 2006.280.08:05:05.76#ibcon#read 5, iclass 30, count 0 2006.280.08:05:05.76#ibcon#about to read 6, iclass 30, count 0 2006.280.08:05:05.76#ibcon#read 6, iclass 30, count 0 2006.280.08:05:05.76#ibcon#end of sib2, iclass 30, count 0 2006.280.08:05:05.76#ibcon#*after write, iclass 30, count 0 2006.280.08:05:05.76#ibcon#*before return 0, iclass 30, count 0 2006.280.08:05:05.76#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:05.76#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:05:05.76#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:05:05.76#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:05:05.76$vc4f8/vabw=wide 2006.280.08:05:05.76#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.08:05:05.76#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.08:05:05.76#ibcon#ireg 8 cls_cnt 0 2006.280.08:05:05.76#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:05.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:05.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:05.76#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:05:05.76#ibcon#first serial, iclass 32, count 0 2006.280.08:05:05.76#ibcon#enter sib2, iclass 32, count 0 2006.280.08:05:05.77#ibcon#flushed, iclass 32, count 0 2006.280.08:05:05.77#ibcon#about to write, iclass 32, count 0 2006.280.08:05:05.77#ibcon#wrote, iclass 32, count 0 2006.280.08:05:05.77#ibcon#about to read 3, iclass 32, count 0 2006.280.08:05:05.78#ibcon#read 3, iclass 32, count 0 2006.280.08:05:05.78#ibcon#about to read 4, iclass 32, count 0 2006.280.08:05:05.78#ibcon#read 4, iclass 32, count 0 2006.280.08:05:05.78#ibcon#about to read 5, iclass 32, count 0 2006.280.08:05:05.78#ibcon#read 5, iclass 32, count 0 2006.280.08:05:05.78#ibcon#about to read 6, iclass 32, count 0 2006.280.08:05:05.78#ibcon#read 6, iclass 32, count 0 2006.280.08:05:05.78#ibcon#end of sib2, iclass 32, count 0 2006.280.08:05:05.79#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:05:05.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:05:05.79#ibcon#[25=BW32\r\n] 2006.280.08:05:05.79#ibcon#*before write, iclass 32, count 0 2006.280.08:05:05.79#ibcon#enter sib2, iclass 32, count 0 2006.280.08:05:05.79#ibcon#flushed, iclass 32, count 0 2006.280.08:05:05.79#ibcon#about to write, iclass 32, count 0 2006.280.08:05:05.79#ibcon#wrote, iclass 32, count 0 2006.280.08:05:05.79#ibcon#about to read 3, iclass 32, count 0 2006.280.08:05:05.82#ibcon#read 3, iclass 32, count 0 2006.280.08:05:05.82#ibcon#about to read 4, iclass 32, count 0 2006.280.08:05:05.82#ibcon#read 4, iclass 32, count 0 2006.280.08:05:05.82#ibcon#about to read 5, iclass 32, count 0 2006.280.08:05:05.82#ibcon#read 5, iclass 32, count 0 2006.280.08:05:05.82#ibcon#about to read 6, iclass 32, count 0 2006.280.08:05:05.82#ibcon#read 6, iclass 32, count 0 2006.280.08:05:05.82#ibcon#end of sib2, iclass 32, count 0 2006.280.08:05:05.82#ibcon#*after write, iclass 32, count 0 2006.280.08:05:05.82#ibcon#*before return 0, iclass 32, count 0 2006.280.08:05:05.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:05.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:05:05.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:05:05.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:05:05.82$vc4f8/vbbw=wide 2006.280.08:05:05.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:05:05.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:05:05.82#ibcon#ireg 8 cls_cnt 0 2006.280.08:05:05.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:05:05.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:05:05.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:05:05.88#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:05:05.88#ibcon#first serial, iclass 34, count 0 2006.280.08:05:05.88#ibcon#enter sib2, iclass 34, count 0 2006.280.08:05:05.88#ibcon#flushed, iclass 34, count 0 2006.280.08:05:05.88#ibcon#about to write, iclass 34, count 0 2006.280.08:05:05.88#ibcon#wrote, iclass 34, count 0 2006.280.08:05:05.88#ibcon#about to read 3, iclass 34, count 0 2006.280.08:05:05.90#ibcon#read 3, iclass 34, count 0 2006.280.08:05:05.90#ibcon#about to read 4, iclass 34, count 0 2006.280.08:05:05.90#ibcon#read 4, iclass 34, count 0 2006.280.08:05:05.90#ibcon#about to read 5, iclass 34, count 0 2006.280.08:05:05.90#ibcon#read 5, iclass 34, count 0 2006.280.08:05:05.90#ibcon#about to read 6, iclass 34, count 0 2006.280.08:05:05.90#ibcon#read 6, iclass 34, count 0 2006.280.08:05:05.90#ibcon#end of sib2, iclass 34, count 0 2006.280.08:05:05.90#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:05:05.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:05:05.90#ibcon#[27=BW32\r\n] 2006.280.08:05:05.90#ibcon#*before write, iclass 34, count 0 2006.280.08:05:05.90#ibcon#enter sib2, iclass 34, count 0 2006.280.08:05:05.90#ibcon#flushed, iclass 34, count 0 2006.280.08:05:05.90#ibcon#about to write, iclass 34, count 0 2006.280.08:05:05.90#ibcon#wrote, iclass 34, count 0 2006.280.08:05:05.90#ibcon#about to read 3, iclass 34, count 0 2006.280.08:05:05.93#ibcon#read 3, iclass 34, count 0 2006.280.08:05:05.93#ibcon#about to read 4, iclass 34, count 0 2006.280.08:05:05.93#ibcon#read 4, iclass 34, count 0 2006.280.08:05:05.93#ibcon#about to read 5, iclass 34, count 0 2006.280.08:05:05.93#ibcon#read 5, iclass 34, count 0 2006.280.08:05:05.93#ibcon#about to read 6, iclass 34, count 0 2006.280.08:05:05.93#ibcon#read 6, iclass 34, count 0 2006.280.08:05:05.93#ibcon#end of sib2, iclass 34, count 0 2006.280.08:05:05.93#ibcon#*after write, iclass 34, count 0 2006.280.08:05:05.93#ibcon#*before return 0, iclass 34, count 0 2006.280.08:05:05.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:05:05.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:05:05.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:05:05.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:05:05.93$4f8m12a/ifd4f 2006.280.08:05:05.93$ifd4f/lo= 2006.280.08:05:05.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:05:05.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:05:05.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:05:05.93$ifd4f/patch= 2006.280.08:05:05.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:05:05.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:05:05.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:05:05.93$4f8m12a/"form=m,16.000,1:2 2006.280.08:05:05.93$4f8m12a/"tpicd 2006.280.08:05:05.93$4f8m12a/echo=off 2006.280.08:05:05.93$4f8m12a/xlog=off 2006.280.08:05:05.93:!2006.280.08:05:30 2006.280.08:05:13.14#trakl#Source acquired 2006.280.08:05:15.14#flagr#flagr/antenna,acquired 2006.280.08:05:30.00:preob 2006.280.08:05:31.14/onsource/TRACKING 2006.280.08:05:31.14:!2006.280.08:05:40 2006.280.08:05:40.00:data_valid=on 2006.280.08:05:40.00:midob 2006.280.08:05:40.14/onsource/TRACKING 2006.280.08:05:40.14/wx/20.71,987.4,62 2006.280.08:05:40.35/cable/+6.4850E-03 2006.280.08:05:41.44/va/01,07,usb,yes,32,33 2006.280.08:05:41.44/va/02,06,usb,yes,29,31 2006.280.08:05:41.44/va/03,06,usb,yes,28,28 2006.280.08:05:41.44/va/04,06,usb,yes,31,33 2006.280.08:05:41.44/va/05,07,usb,yes,29,30 2006.280.08:05:41.44/va/06,06,usb,yes,28,28 2006.280.08:05:41.44/va/07,06,usb,yes,28,28 2006.280.08:05:41.44/va/08,06,usb,yes,30,30 2006.280.08:05:41.67/valo/01,532.99,yes,locked 2006.280.08:05:41.67/valo/02,572.99,yes,locked 2006.280.08:05:41.67/valo/03,672.99,yes,locked 2006.280.08:05:41.67/valo/04,832.99,yes,locked 2006.280.08:05:41.67/valo/05,652.99,yes,locked 2006.280.08:05:41.67/valo/06,772.99,yes,locked 2006.280.08:05:41.67/valo/07,832.99,yes,locked 2006.280.08:05:41.67/valo/08,852.99,yes,locked 2006.280.08:05:42.76/vb/01,04,usb,yes,30,29 2006.280.08:05:42.76/vb/02,05,usb,yes,28,29 2006.280.08:05:42.76/vb/03,04,usb,yes,28,32 2006.280.08:05:42.76/vb/04,04,usb,yes,29,29 2006.280.08:05:42.76/vb/05,04,usb,yes,27,31 2006.280.08:05:42.76/vb/06,04,usb,yes,27,31 2006.280.08:05:42.76/vb/07,04,usb,yes,30,30 2006.280.08:05:42.76/vb/08,04,usb,yes,27,31 2006.280.08:05:43.00/vblo/01,632.99,yes,locked 2006.280.08:05:43.00/vblo/02,640.99,yes,locked 2006.280.08:05:43.00/vblo/03,656.99,yes,locked 2006.280.08:05:43.00/vblo/04,712.99,yes,locked 2006.280.08:05:43.00/vblo/05,744.99,yes,locked 2006.280.08:05:43.00/vblo/06,752.99,yes,locked 2006.280.08:05:43.00/vblo/07,734.99,yes,locked 2006.280.08:05:43.00/vblo/08,744.99,yes,locked 2006.280.08:05:43.15/vabw/8 2006.280.08:05:43.30/vbbw/8 2006.280.08:05:43.39/xfe/off,on,12.2 2006.280.08:05:43.77/ifatt/23,28,28,28 2006.280.08:05:44.08/fmout-gps/S +3.18E-07 2006.280.08:05:44.10:!2006.280.08:06:40 2006.280.08:06:40.01:data_valid=off 2006.280.08:06:40.01:postob 2006.280.08:06:40.14/cable/+6.4840E-03 2006.280.08:06:40.14/wx/20.66,987.4,63 2006.280.08:06:41.08/fmout-gps/S +3.19E-07 2006.280.08:06:41.08:scan_name=280-0807,k06280,60 2006.280.08:06:41.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.280.08:06:41.14#flagr#flagr/antenna,new-source 2006.280.08:06:42.14:checkk5 2006.280.08:06:42.57/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:06:43.27/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:06:44.02/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:06:44.44/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:06:45.19/chk_obsdata//k5ts1/T2800805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:06:45.65/chk_obsdata//k5ts2/T2800805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:06:46.32/chk_obsdata//k5ts3/T2800805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:06:47.09/chk_obsdata//k5ts4/T2800805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:06:48.04/k5log//k5ts1_log_newline 2006.280.08:06:49.12/k5log//k5ts2_log_newline 2006.280.08:06:50.36/k5log//k5ts3_log_newline 2006.280.08:06:51.22/k5log//k5ts4_log_newline 2006.280.08:06:51.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:06:51.24:4f8m12a=2 2006.280.08:06:51.24$4f8m12a/echo=on 2006.280.08:06:51.24$4f8m12a/pcalon 2006.280.08:06:51.24$pcalon/"no phase cal control is implemented here 2006.280.08:06:51.24$4f8m12a/"tpicd=stop 2006.280.08:06:51.24$4f8m12a/vc4f8 2006.280.08:06:51.24$vc4f8/valo=1,532.99 2006.280.08:06:51.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.08:06:51.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.08:06:51.25#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:51.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:51.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:51.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:51.25#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:06:51.25#ibcon#first serial, iclass 3, count 0 2006.280.08:06:51.25#ibcon#enter sib2, iclass 3, count 0 2006.280.08:06:51.25#ibcon#flushed, iclass 3, count 0 2006.280.08:06:51.25#ibcon#about to write, iclass 3, count 0 2006.280.08:06:51.25#ibcon#wrote, iclass 3, count 0 2006.280.08:06:51.25#ibcon#about to read 3, iclass 3, count 0 2006.280.08:06:51.27#ibcon#read 3, iclass 3, count 0 2006.280.08:06:51.27#ibcon#about to read 4, iclass 3, count 0 2006.280.08:06:51.27#ibcon#read 4, iclass 3, count 0 2006.280.08:06:51.27#ibcon#about to read 5, iclass 3, count 0 2006.280.08:06:51.27#ibcon#read 5, iclass 3, count 0 2006.280.08:06:51.27#ibcon#about to read 6, iclass 3, count 0 2006.280.08:06:51.27#ibcon#read 6, iclass 3, count 0 2006.280.08:06:51.27#ibcon#end of sib2, iclass 3, count 0 2006.280.08:06:51.27#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:06:51.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:06:51.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:06:51.27#ibcon#*before write, iclass 3, count 0 2006.280.08:06:51.27#ibcon#enter sib2, iclass 3, count 0 2006.280.08:06:51.27#ibcon#flushed, iclass 3, count 0 2006.280.08:06:51.27#ibcon#about to write, iclass 3, count 0 2006.280.08:06:51.27#ibcon#wrote, iclass 3, count 0 2006.280.08:06:51.27#ibcon#about to read 3, iclass 3, count 0 2006.280.08:06:51.32#ibcon#read 3, iclass 3, count 0 2006.280.08:06:51.32#ibcon#about to read 4, iclass 3, count 0 2006.280.08:06:51.32#ibcon#read 4, iclass 3, count 0 2006.280.08:06:51.32#ibcon#about to read 5, iclass 3, count 0 2006.280.08:06:51.32#ibcon#read 5, iclass 3, count 0 2006.280.08:06:51.32#ibcon#about to read 6, iclass 3, count 0 2006.280.08:06:51.32#ibcon#read 6, iclass 3, count 0 2006.280.08:06:51.32#ibcon#end of sib2, iclass 3, count 0 2006.280.08:06:51.32#ibcon#*after write, iclass 3, count 0 2006.280.08:06:51.32#ibcon#*before return 0, iclass 3, count 0 2006.280.08:06:51.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:51.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:51.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:06:51.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:06:51.32$vc4f8/va=1,7 2006.280.08:06:51.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.08:06:51.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.08:06:51.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:51.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:51.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:51.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:51.33#ibcon#enter wrdev, iclass 5, count 2 2006.280.08:06:51.33#ibcon#first serial, iclass 5, count 2 2006.280.08:06:51.33#ibcon#enter sib2, iclass 5, count 2 2006.280.08:06:51.33#ibcon#flushed, iclass 5, count 2 2006.280.08:06:51.33#ibcon#about to write, iclass 5, count 2 2006.280.08:06:51.33#ibcon#wrote, iclass 5, count 2 2006.280.08:06:51.33#ibcon#about to read 3, iclass 5, count 2 2006.280.08:06:51.35#ibcon#read 3, iclass 5, count 2 2006.280.08:06:51.35#ibcon#about to read 4, iclass 5, count 2 2006.280.08:06:51.35#ibcon#read 4, iclass 5, count 2 2006.280.08:06:51.35#ibcon#about to read 5, iclass 5, count 2 2006.280.08:06:51.35#ibcon#read 5, iclass 5, count 2 2006.280.08:06:51.35#ibcon#about to read 6, iclass 5, count 2 2006.280.08:06:51.35#ibcon#read 6, iclass 5, count 2 2006.280.08:06:51.35#ibcon#end of sib2, iclass 5, count 2 2006.280.08:06:51.35#ibcon#*mode == 0, iclass 5, count 2 2006.280.08:06:51.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.08:06:51.35#ibcon#[25=AT01-07\r\n] 2006.280.08:06:51.35#ibcon#*before write, iclass 5, count 2 2006.280.08:06:51.35#ibcon#enter sib2, iclass 5, count 2 2006.280.08:06:51.35#ibcon#flushed, iclass 5, count 2 2006.280.08:06:51.35#ibcon#about to write, iclass 5, count 2 2006.280.08:06:51.35#ibcon#wrote, iclass 5, count 2 2006.280.08:06:51.35#ibcon#about to read 3, iclass 5, count 2 2006.280.08:06:51.38#ibcon#read 3, iclass 5, count 2 2006.280.08:06:51.38#ibcon#about to read 4, iclass 5, count 2 2006.280.08:06:51.38#ibcon#read 4, iclass 5, count 2 2006.280.08:06:51.38#ibcon#about to read 5, iclass 5, count 2 2006.280.08:06:51.38#ibcon#read 5, iclass 5, count 2 2006.280.08:06:51.38#ibcon#about to read 6, iclass 5, count 2 2006.280.08:06:51.38#ibcon#read 6, iclass 5, count 2 2006.280.08:06:51.38#ibcon#end of sib2, iclass 5, count 2 2006.280.08:06:51.38#ibcon#*after write, iclass 5, count 2 2006.280.08:06:51.38#ibcon#*before return 0, iclass 5, count 2 2006.280.08:06:51.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:51.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:51.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.08:06:51.38#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:51.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:51.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:51.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:51.50#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:06:51.50#ibcon#first serial, iclass 5, count 0 2006.280.08:06:51.50#ibcon#enter sib2, iclass 5, count 0 2006.280.08:06:51.50#ibcon#flushed, iclass 5, count 0 2006.280.08:06:51.50#ibcon#about to write, iclass 5, count 0 2006.280.08:06:51.50#ibcon#wrote, iclass 5, count 0 2006.280.08:06:51.50#ibcon#about to read 3, iclass 5, count 0 2006.280.08:06:51.52#ibcon#read 3, iclass 5, count 0 2006.280.08:06:51.52#ibcon#about to read 4, iclass 5, count 0 2006.280.08:06:51.52#ibcon#read 4, iclass 5, count 0 2006.280.08:06:51.52#ibcon#about to read 5, iclass 5, count 0 2006.280.08:06:51.52#ibcon#read 5, iclass 5, count 0 2006.280.08:06:51.52#ibcon#about to read 6, iclass 5, count 0 2006.280.08:06:51.52#ibcon#read 6, iclass 5, count 0 2006.280.08:06:51.52#ibcon#end of sib2, iclass 5, count 0 2006.280.08:06:51.52#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:06:51.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:06:51.52#ibcon#[25=USB\r\n] 2006.280.08:06:51.52#ibcon#*before write, iclass 5, count 0 2006.280.08:06:51.52#ibcon#enter sib2, iclass 5, count 0 2006.280.08:06:51.52#ibcon#flushed, iclass 5, count 0 2006.280.08:06:51.52#ibcon#about to write, iclass 5, count 0 2006.280.08:06:51.52#ibcon#wrote, iclass 5, count 0 2006.280.08:06:51.52#ibcon#about to read 3, iclass 5, count 0 2006.280.08:06:51.55#ibcon#read 3, iclass 5, count 0 2006.280.08:06:51.55#ibcon#about to read 4, iclass 5, count 0 2006.280.08:06:51.55#ibcon#read 4, iclass 5, count 0 2006.280.08:06:51.55#ibcon#about to read 5, iclass 5, count 0 2006.280.08:06:51.55#ibcon#read 5, iclass 5, count 0 2006.280.08:06:51.55#ibcon#about to read 6, iclass 5, count 0 2006.280.08:06:51.55#ibcon#read 6, iclass 5, count 0 2006.280.08:06:51.55#ibcon#end of sib2, iclass 5, count 0 2006.280.08:06:51.55#ibcon#*after write, iclass 5, count 0 2006.280.08:06:51.55#ibcon#*before return 0, iclass 5, count 0 2006.280.08:06:51.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:51.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:51.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:06:51.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:06:51.55$vc4f8/valo=2,572.99 2006.280.08:06:51.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.08:06:51.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.08:06:51.55#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:51.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:51.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:51.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:51.55#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:06:51.55#ibcon#first serial, iclass 7, count 0 2006.280.08:06:51.55#ibcon#enter sib2, iclass 7, count 0 2006.280.08:06:51.55#ibcon#flushed, iclass 7, count 0 2006.280.08:06:51.55#ibcon#about to write, iclass 7, count 0 2006.280.08:06:51.55#ibcon#wrote, iclass 7, count 0 2006.280.08:06:51.55#ibcon#about to read 3, iclass 7, count 0 2006.280.08:06:51.57#ibcon#read 3, iclass 7, count 0 2006.280.08:06:51.57#ibcon#about to read 4, iclass 7, count 0 2006.280.08:06:51.57#ibcon#read 4, iclass 7, count 0 2006.280.08:06:51.57#ibcon#about to read 5, iclass 7, count 0 2006.280.08:06:51.57#ibcon#read 5, iclass 7, count 0 2006.280.08:06:51.57#ibcon#about to read 6, iclass 7, count 0 2006.280.08:06:51.57#ibcon#read 6, iclass 7, count 0 2006.280.08:06:51.57#ibcon#end of sib2, iclass 7, count 0 2006.280.08:06:51.57#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:06:51.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:06:51.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:06:51.57#ibcon#*before write, iclass 7, count 0 2006.280.08:06:51.57#ibcon#enter sib2, iclass 7, count 0 2006.280.08:06:51.57#ibcon#flushed, iclass 7, count 0 2006.280.08:06:51.57#ibcon#about to write, iclass 7, count 0 2006.280.08:06:51.57#ibcon#wrote, iclass 7, count 0 2006.280.08:06:51.57#ibcon#about to read 3, iclass 7, count 0 2006.280.08:06:51.61#ibcon#read 3, iclass 7, count 0 2006.280.08:06:51.61#ibcon#about to read 4, iclass 7, count 0 2006.280.08:06:51.61#ibcon#read 4, iclass 7, count 0 2006.280.08:06:51.61#ibcon#about to read 5, iclass 7, count 0 2006.280.08:06:51.61#ibcon#read 5, iclass 7, count 0 2006.280.08:06:51.61#ibcon#about to read 6, iclass 7, count 0 2006.280.08:06:51.61#ibcon#read 6, iclass 7, count 0 2006.280.08:06:51.61#ibcon#end of sib2, iclass 7, count 0 2006.280.08:06:51.61#ibcon#*after write, iclass 7, count 0 2006.280.08:06:51.61#ibcon#*before return 0, iclass 7, count 0 2006.280.08:06:51.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:51.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:51.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:06:51.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:06:51.61$vc4f8/va=2,6 2006.280.08:06:51.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.08:06:51.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.08:06:51.61#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:51.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:51.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:51.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:51.67#ibcon#enter wrdev, iclass 11, count 2 2006.280.08:06:51.67#ibcon#first serial, iclass 11, count 2 2006.280.08:06:51.67#ibcon#enter sib2, iclass 11, count 2 2006.280.08:06:51.67#ibcon#flushed, iclass 11, count 2 2006.280.08:06:51.67#ibcon#about to write, iclass 11, count 2 2006.280.08:06:51.67#ibcon#wrote, iclass 11, count 2 2006.280.08:06:51.67#ibcon#about to read 3, iclass 11, count 2 2006.280.08:06:51.69#ibcon#read 3, iclass 11, count 2 2006.280.08:06:51.69#ibcon#about to read 4, iclass 11, count 2 2006.280.08:06:51.69#ibcon#read 4, iclass 11, count 2 2006.280.08:06:51.69#ibcon#about to read 5, iclass 11, count 2 2006.280.08:06:51.69#ibcon#read 5, iclass 11, count 2 2006.280.08:06:51.69#ibcon#about to read 6, iclass 11, count 2 2006.280.08:06:51.69#ibcon#read 6, iclass 11, count 2 2006.280.08:06:51.69#ibcon#end of sib2, iclass 11, count 2 2006.280.08:06:51.69#ibcon#*mode == 0, iclass 11, count 2 2006.280.08:06:51.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.08:06:51.69#ibcon#[25=AT02-06\r\n] 2006.280.08:06:51.69#ibcon#*before write, iclass 11, count 2 2006.280.08:06:51.69#ibcon#enter sib2, iclass 11, count 2 2006.280.08:06:51.69#ibcon#flushed, iclass 11, count 2 2006.280.08:06:51.69#ibcon#about to write, iclass 11, count 2 2006.280.08:06:51.69#ibcon#wrote, iclass 11, count 2 2006.280.08:06:51.69#ibcon#about to read 3, iclass 11, count 2 2006.280.08:06:51.72#ibcon#read 3, iclass 11, count 2 2006.280.08:06:51.72#ibcon#about to read 4, iclass 11, count 2 2006.280.08:06:51.72#ibcon#read 4, iclass 11, count 2 2006.280.08:06:51.73#ibcon#about to read 5, iclass 11, count 2 2006.280.08:06:51.73#ibcon#read 5, iclass 11, count 2 2006.280.08:06:51.73#ibcon#about to read 6, iclass 11, count 2 2006.280.08:06:51.73#ibcon#read 6, iclass 11, count 2 2006.280.08:06:51.73#ibcon#end of sib2, iclass 11, count 2 2006.280.08:06:51.73#ibcon#*after write, iclass 11, count 2 2006.280.08:06:51.73#ibcon#*before return 0, iclass 11, count 2 2006.280.08:06:51.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:51.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:51.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.08:06:51.73#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:51.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:51.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:51.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:51.84#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:06:51.84#ibcon#first serial, iclass 11, count 0 2006.280.08:06:51.84#ibcon#enter sib2, iclass 11, count 0 2006.280.08:06:51.84#ibcon#flushed, iclass 11, count 0 2006.280.08:06:51.84#ibcon#about to write, iclass 11, count 0 2006.280.08:06:51.84#ibcon#wrote, iclass 11, count 0 2006.280.08:06:51.84#ibcon#about to read 3, iclass 11, count 0 2006.280.08:06:51.86#ibcon#read 3, iclass 11, count 0 2006.280.08:06:51.86#ibcon#about to read 4, iclass 11, count 0 2006.280.08:06:51.86#ibcon#read 4, iclass 11, count 0 2006.280.08:06:51.86#ibcon#about to read 5, iclass 11, count 0 2006.280.08:06:51.86#ibcon#read 5, iclass 11, count 0 2006.280.08:06:51.86#ibcon#about to read 6, iclass 11, count 0 2006.280.08:06:51.86#ibcon#read 6, iclass 11, count 0 2006.280.08:06:51.86#ibcon#end of sib2, iclass 11, count 0 2006.280.08:06:51.86#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:06:51.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:06:51.86#ibcon#[25=USB\r\n] 2006.280.08:06:51.86#ibcon#*before write, iclass 11, count 0 2006.280.08:06:51.86#ibcon#enter sib2, iclass 11, count 0 2006.280.08:06:51.86#ibcon#flushed, iclass 11, count 0 2006.280.08:06:51.86#ibcon#about to write, iclass 11, count 0 2006.280.08:06:51.86#ibcon#wrote, iclass 11, count 0 2006.280.08:06:51.86#ibcon#about to read 3, iclass 11, count 0 2006.280.08:06:51.89#ibcon#read 3, iclass 11, count 0 2006.280.08:06:51.89#ibcon#about to read 4, iclass 11, count 0 2006.280.08:06:51.89#ibcon#read 4, iclass 11, count 0 2006.280.08:06:51.89#ibcon#about to read 5, iclass 11, count 0 2006.280.08:06:51.89#ibcon#read 5, iclass 11, count 0 2006.280.08:06:51.89#ibcon#about to read 6, iclass 11, count 0 2006.280.08:06:51.89#ibcon#read 6, iclass 11, count 0 2006.280.08:06:51.89#ibcon#end of sib2, iclass 11, count 0 2006.280.08:06:51.89#ibcon#*after write, iclass 11, count 0 2006.280.08:06:51.89#ibcon#*before return 0, iclass 11, count 0 2006.280.08:06:51.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:51.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:51.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:06:51.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:06:51.89$vc4f8/valo=3,672.99 2006.280.08:06:51.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.08:06:51.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.08:06:51.89#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:51.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:51.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:51.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:51.89#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:06:51.89#ibcon#first serial, iclass 13, count 0 2006.280.08:06:51.89#ibcon#enter sib2, iclass 13, count 0 2006.280.08:06:51.89#ibcon#flushed, iclass 13, count 0 2006.280.08:06:51.89#ibcon#about to write, iclass 13, count 0 2006.280.08:06:51.89#ibcon#wrote, iclass 13, count 0 2006.280.08:06:51.89#ibcon#about to read 3, iclass 13, count 0 2006.280.08:06:51.91#ibcon#read 3, iclass 13, count 0 2006.280.08:06:51.91#ibcon#about to read 4, iclass 13, count 0 2006.280.08:06:51.91#ibcon#read 4, iclass 13, count 0 2006.280.08:06:51.91#ibcon#about to read 5, iclass 13, count 0 2006.280.08:06:51.91#ibcon#read 5, iclass 13, count 0 2006.280.08:06:51.91#ibcon#about to read 6, iclass 13, count 0 2006.280.08:06:51.91#ibcon#read 6, iclass 13, count 0 2006.280.08:06:51.91#ibcon#end of sib2, iclass 13, count 0 2006.280.08:06:51.91#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:06:51.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:06:51.91#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:06:51.91#ibcon#*before write, iclass 13, count 0 2006.280.08:06:51.91#ibcon#enter sib2, iclass 13, count 0 2006.280.08:06:51.91#ibcon#flushed, iclass 13, count 0 2006.280.08:06:51.91#ibcon#about to write, iclass 13, count 0 2006.280.08:06:51.91#ibcon#wrote, iclass 13, count 0 2006.280.08:06:51.91#ibcon#about to read 3, iclass 13, count 0 2006.280.08:06:51.95#ibcon#read 3, iclass 13, count 0 2006.280.08:06:51.95#ibcon#about to read 4, iclass 13, count 0 2006.280.08:06:51.95#ibcon#read 4, iclass 13, count 0 2006.280.08:06:51.95#ibcon#about to read 5, iclass 13, count 0 2006.280.08:06:51.95#ibcon#read 5, iclass 13, count 0 2006.280.08:06:51.95#ibcon#about to read 6, iclass 13, count 0 2006.280.08:06:51.95#ibcon#read 6, iclass 13, count 0 2006.280.08:06:51.95#ibcon#end of sib2, iclass 13, count 0 2006.280.08:06:51.95#ibcon#*after write, iclass 13, count 0 2006.280.08:06:51.95#ibcon#*before return 0, iclass 13, count 0 2006.280.08:06:51.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:51.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:51.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:06:51.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:06:51.95$vc4f8/va=3,6 2006.280.08:06:51.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.08:06:51.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.08:06:51.97#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:51.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:52.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:52.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:52.00#ibcon#enter wrdev, iclass 15, count 2 2006.280.08:06:52.00#ibcon#first serial, iclass 15, count 2 2006.280.08:06:52.00#ibcon#enter sib2, iclass 15, count 2 2006.280.08:06:52.00#ibcon#flushed, iclass 15, count 2 2006.280.08:06:52.00#ibcon#about to write, iclass 15, count 2 2006.280.08:06:52.00#ibcon#wrote, iclass 15, count 2 2006.280.08:06:52.00#ibcon#about to read 3, iclass 15, count 2 2006.280.08:06:52.02#ibcon#read 3, iclass 15, count 2 2006.280.08:06:52.02#ibcon#about to read 4, iclass 15, count 2 2006.280.08:06:52.02#ibcon#read 4, iclass 15, count 2 2006.280.08:06:52.02#ibcon#about to read 5, iclass 15, count 2 2006.280.08:06:52.02#ibcon#read 5, iclass 15, count 2 2006.280.08:06:52.02#ibcon#about to read 6, iclass 15, count 2 2006.280.08:06:52.02#ibcon#read 6, iclass 15, count 2 2006.280.08:06:52.02#ibcon#end of sib2, iclass 15, count 2 2006.280.08:06:52.02#ibcon#*mode == 0, iclass 15, count 2 2006.280.08:06:52.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.08:06:52.02#ibcon#[25=AT03-06\r\n] 2006.280.08:06:52.02#ibcon#*before write, iclass 15, count 2 2006.280.08:06:52.02#ibcon#enter sib2, iclass 15, count 2 2006.280.08:06:52.02#ibcon#flushed, iclass 15, count 2 2006.280.08:06:52.02#ibcon#about to write, iclass 15, count 2 2006.280.08:06:52.02#ibcon#wrote, iclass 15, count 2 2006.280.08:06:52.02#ibcon#about to read 3, iclass 15, count 2 2006.280.08:06:52.05#ibcon#read 3, iclass 15, count 2 2006.280.08:06:52.05#ibcon#about to read 4, iclass 15, count 2 2006.280.08:06:52.05#ibcon#read 4, iclass 15, count 2 2006.280.08:06:52.05#ibcon#about to read 5, iclass 15, count 2 2006.280.08:06:52.05#ibcon#read 5, iclass 15, count 2 2006.280.08:06:52.05#ibcon#about to read 6, iclass 15, count 2 2006.280.08:06:52.05#ibcon#read 6, iclass 15, count 2 2006.280.08:06:52.05#ibcon#end of sib2, iclass 15, count 2 2006.280.08:06:52.05#ibcon#*after write, iclass 15, count 2 2006.280.08:06:52.05#ibcon#*before return 0, iclass 15, count 2 2006.280.08:06:52.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:52.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:52.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.08:06:52.05#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:52.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:52.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:52.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:52.17#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:06:52.17#ibcon#first serial, iclass 15, count 0 2006.280.08:06:52.17#ibcon#enter sib2, iclass 15, count 0 2006.280.08:06:52.17#ibcon#flushed, iclass 15, count 0 2006.280.08:06:52.17#ibcon#about to write, iclass 15, count 0 2006.280.08:06:52.17#ibcon#wrote, iclass 15, count 0 2006.280.08:06:52.17#ibcon#about to read 3, iclass 15, count 0 2006.280.08:06:52.19#ibcon#read 3, iclass 15, count 0 2006.280.08:06:52.19#ibcon#about to read 4, iclass 15, count 0 2006.280.08:06:52.19#ibcon#read 4, iclass 15, count 0 2006.280.08:06:52.19#ibcon#about to read 5, iclass 15, count 0 2006.280.08:06:52.19#ibcon#read 5, iclass 15, count 0 2006.280.08:06:52.19#ibcon#about to read 6, iclass 15, count 0 2006.280.08:06:52.19#ibcon#read 6, iclass 15, count 0 2006.280.08:06:52.19#ibcon#end of sib2, iclass 15, count 0 2006.280.08:06:52.19#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:06:52.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:06:52.19#ibcon#[25=USB\r\n] 2006.280.08:06:52.19#ibcon#*before write, iclass 15, count 0 2006.280.08:06:52.19#ibcon#enter sib2, iclass 15, count 0 2006.280.08:06:52.19#ibcon#flushed, iclass 15, count 0 2006.280.08:06:52.19#ibcon#about to write, iclass 15, count 0 2006.280.08:06:52.19#ibcon#wrote, iclass 15, count 0 2006.280.08:06:52.19#ibcon#about to read 3, iclass 15, count 0 2006.280.08:06:52.22#ibcon#read 3, iclass 15, count 0 2006.280.08:06:52.22#ibcon#about to read 4, iclass 15, count 0 2006.280.08:06:52.22#ibcon#read 4, iclass 15, count 0 2006.280.08:06:52.22#ibcon#about to read 5, iclass 15, count 0 2006.280.08:06:52.22#ibcon#read 5, iclass 15, count 0 2006.280.08:06:52.22#ibcon#about to read 6, iclass 15, count 0 2006.280.08:06:52.22#ibcon#read 6, iclass 15, count 0 2006.280.08:06:52.22#ibcon#end of sib2, iclass 15, count 0 2006.280.08:06:52.22#ibcon#*after write, iclass 15, count 0 2006.280.08:06:52.22#ibcon#*before return 0, iclass 15, count 0 2006.280.08:06:52.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:52.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:52.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:06:52.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:06:52.22$vc4f8/valo=4,832.99 2006.280.08:06:52.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.08:06:52.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.08:06:52.22#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:52.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:52.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:52.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:52.22#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:06:52.22#ibcon#first serial, iclass 17, count 0 2006.280.08:06:52.22#ibcon#enter sib2, iclass 17, count 0 2006.280.08:06:52.22#ibcon#flushed, iclass 17, count 0 2006.280.08:06:52.22#ibcon#about to write, iclass 17, count 0 2006.280.08:06:52.22#ibcon#wrote, iclass 17, count 0 2006.280.08:06:52.22#ibcon#about to read 3, iclass 17, count 0 2006.280.08:06:52.24#ibcon#read 3, iclass 17, count 0 2006.280.08:06:52.24#ibcon#about to read 4, iclass 17, count 0 2006.280.08:06:52.24#ibcon#read 4, iclass 17, count 0 2006.280.08:06:52.24#ibcon#about to read 5, iclass 17, count 0 2006.280.08:06:52.24#ibcon#read 5, iclass 17, count 0 2006.280.08:06:52.24#ibcon#about to read 6, iclass 17, count 0 2006.280.08:06:52.24#ibcon#read 6, iclass 17, count 0 2006.280.08:06:52.24#ibcon#end of sib2, iclass 17, count 0 2006.280.08:06:52.24#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:06:52.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:06:52.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:06:52.24#ibcon#*before write, iclass 17, count 0 2006.280.08:06:52.24#ibcon#enter sib2, iclass 17, count 0 2006.280.08:06:52.24#ibcon#flushed, iclass 17, count 0 2006.280.08:06:52.24#ibcon#about to write, iclass 17, count 0 2006.280.08:06:52.24#ibcon#wrote, iclass 17, count 0 2006.280.08:06:52.24#ibcon#about to read 3, iclass 17, count 0 2006.280.08:06:52.28#ibcon#read 3, iclass 17, count 0 2006.280.08:06:52.28#ibcon#about to read 4, iclass 17, count 0 2006.280.08:06:52.28#ibcon#read 4, iclass 17, count 0 2006.280.08:06:52.28#ibcon#about to read 5, iclass 17, count 0 2006.280.08:06:52.28#ibcon#read 5, iclass 17, count 0 2006.280.08:06:52.28#ibcon#about to read 6, iclass 17, count 0 2006.280.08:06:52.28#ibcon#read 6, iclass 17, count 0 2006.280.08:06:52.28#ibcon#end of sib2, iclass 17, count 0 2006.280.08:06:52.28#ibcon#*after write, iclass 17, count 0 2006.280.08:06:52.28#ibcon#*before return 0, iclass 17, count 0 2006.280.08:06:52.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:52.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:52.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:06:52.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:06:52.28$vc4f8/va=4,6 2006.280.08:06:52.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.08:06:52.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.08:06:52.29#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:52.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:52.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:52.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:52.34#ibcon#enter wrdev, iclass 19, count 2 2006.280.08:06:52.34#ibcon#first serial, iclass 19, count 2 2006.280.08:06:52.34#ibcon#enter sib2, iclass 19, count 2 2006.280.08:06:52.34#ibcon#flushed, iclass 19, count 2 2006.280.08:06:52.34#ibcon#about to write, iclass 19, count 2 2006.280.08:06:52.34#ibcon#wrote, iclass 19, count 2 2006.280.08:06:52.34#ibcon#about to read 3, iclass 19, count 2 2006.280.08:06:52.36#ibcon#read 3, iclass 19, count 2 2006.280.08:06:52.36#ibcon#about to read 4, iclass 19, count 2 2006.280.08:06:52.36#ibcon#read 4, iclass 19, count 2 2006.280.08:06:52.36#ibcon#about to read 5, iclass 19, count 2 2006.280.08:06:52.36#ibcon#read 5, iclass 19, count 2 2006.280.08:06:52.36#ibcon#about to read 6, iclass 19, count 2 2006.280.08:06:52.36#ibcon#read 6, iclass 19, count 2 2006.280.08:06:52.36#ibcon#end of sib2, iclass 19, count 2 2006.280.08:06:52.36#ibcon#*mode == 0, iclass 19, count 2 2006.280.08:06:52.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.08:06:52.36#ibcon#[25=AT04-06\r\n] 2006.280.08:06:52.36#ibcon#*before write, iclass 19, count 2 2006.280.08:06:52.36#ibcon#enter sib2, iclass 19, count 2 2006.280.08:06:52.36#ibcon#flushed, iclass 19, count 2 2006.280.08:06:52.36#ibcon#about to write, iclass 19, count 2 2006.280.08:06:52.36#ibcon#wrote, iclass 19, count 2 2006.280.08:06:52.36#ibcon#about to read 3, iclass 19, count 2 2006.280.08:06:52.39#ibcon#read 3, iclass 19, count 2 2006.280.08:06:52.39#ibcon#about to read 4, iclass 19, count 2 2006.280.08:06:52.39#ibcon#read 4, iclass 19, count 2 2006.280.08:06:52.39#ibcon#about to read 5, iclass 19, count 2 2006.280.08:06:52.39#ibcon#read 5, iclass 19, count 2 2006.280.08:06:52.39#ibcon#about to read 6, iclass 19, count 2 2006.280.08:06:52.39#ibcon#read 6, iclass 19, count 2 2006.280.08:06:52.39#ibcon#end of sib2, iclass 19, count 2 2006.280.08:06:52.39#ibcon#*after write, iclass 19, count 2 2006.280.08:06:52.39#ibcon#*before return 0, iclass 19, count 2 2006.280.08:06:52.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:52.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:52.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.08:06:52.39#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:52.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:52.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:52.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:52.51#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:06:52.51#ibcon#first serial, iclass 19, count 0 2006.280.08:06:52.51#ibcon#enter sib2, iclass 19, count 0 2006.280.08:06:52.51#ibcon#flushed, iclass 19, count 0 2006.280.08:06:52.51#ibcon#about to write, iclass 19, count 0 2006.280.08:06:52.51#ibcon#wrote, iclass 19, count 0 2006.280.08:06:52.51#ibcon#about to read 3, iclass 19, count 0 2006.280.08:06:52.53#ibcon#read 3, iclass 19, count 0 2006.280.08:06:52.53#ibcon#about to read 4, iclass 19, count 0 2006.280.08:06:52.53#ibcon#read 4, iclass 19, count 0 2006.280.08:06:52.53#ibcon#about to read 5, iclass 19, count 0 2006.280.08:06:52.53#ibcon#read 5, iclass 19, count 0 2006.280.08:06:52.53#ibcon#about to read 6, iclass 19, count 0 2006.280.08:06:52.53#ibcon#read 6, iclass 19, count 0 2006.280.08:06:52.53#ibcon#end of sib2, iclass 19, count 0 2006.280.08:06:52.53#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:06:52.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:06:52.53#ibcon#[25=USB\r\n] 2006.280.08:06:52.53#ibcon#*before write, iclass 19, count 0 2006.280.08:06:52.53#ibcon#enter sib2, iclass 19, count 0 2006.280.08:06:52.53#ibcon#flushed, iclass 19, count 0 2006.280.08:06:52.53#ibcon#about to write, iclass 19, count 0 2006.280.08:06:52.53#ibcon#wrote, iclass 19, count 0 2006.280.08:06:52.53#ibcon#about to read 3, iclass 19, count 0 2006.280.08:06:52.56#ibcon#read 3, iclass 19, count 0 2006.280.08:06:52.56#ibcon#about to read 4, iclass 19, count 0 2006.280.08:06:52.56#ibcon#read 4, iclass 19, count 0 2006.280.08:06:52.56#ibcon#about to read 5, iclass 19, count 0 2006.280.08:06:52.56#ibcon#read 5, iclass 19, count 0 2006.280.08:06:52.56#ibcon#about to read 6, iclass 19, count 0 2006.280.08:06:52.56#ibcon#read 6, iclass 19, count 0 2006.280.08:06:52.56#ibcon#end of sib2, iclass 19, count 0 2006.280.08:06:52.56#ibcon#*after write, iclass 19, count 0 2006.280.08:06:52.56#ibcon#*before return 0, iclass 19, count 0 2006.280.08:06:52.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:52.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:52.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:06:52.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:06:52.56$vc4f8/valo=5,652.99 2006.280.08:06:52.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.08:06:52.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.08:06:52.56#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:52.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:06:52.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:06:52.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:06:52.56#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:06:52.56#ibcon#first serial, iclass 21, count 0 2006.280.08:06:52.56#ibcon#enter sib2, iclass 21, count 0 2006.280.08:06:52.56#ibcon#flushed, iclass 21, count 0 2006.280.08:06:52.56#ibcon#about to write, iclass 21, count 0 2006.280.08:06:52.56#ibcon#wrote, iclass 21, count 0 2006.280.08:06:52.56#ibcon#about to read 3, iclass 21, count 0 2006.280.08:06:52.58#ibcon#read 3, iclass 21, count 0 2006.280.08:06:52.58#ibcon#about to read 4, iclass 21, count 0 2006.280.08:06:52.58#ibcon#read 4, iclass 21, count 0 2006.280.08:06:52.58#ibcon#about to read 5, iclass 21, count 0 2006.280.08:06:52.58#ibcon#read 5, iclass 21, count 0 2006.280.08:06:52.58#ibcon#about to read 6, iclass 21, count 0 2006.280.08:06:52.58#ibcon#read 6, iclass 21, count 0 2006.280.08:06:52.58#ibcon#end of sib2, iclass 21, count 0 2006.280.08:06:52.58#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:06:52.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:06:52.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:06:52.58#ibcon#*before write, iclass 21, count 0 2006.280.08:06:52.58#ibcon#enter sib2, iclass 21, count 0 2006.280.08:06:52.58#ibcon#flushed, iclass 21, count 0 2006.280.08:06:52.58#ibcon#about to write, iclass 21, count 0 2006.280.08:06:52.58#ibcon#wrote, iclass 21, count 0 2006.280.08:06:52.58#ibcon#about to read 3, iclass 21, count 0 2006.280.08:06:52.62#ibcon#read 3, iclass 21, count 0 2006.280.08:06:52.62#ibcon#about to read 4, iclass 21, count 0 2006.280.08:06:52.62#ibcon#read 4, iclass 21, count 0 2006.280.08:06:52.62#ibcon#about to read 5, iclass 21, count 0 2006.280.08:06:52.62#ibcon#read 5, iclass 21, count 0 2006.280.08:06:52.62#ibcon#about to read 6, iclass 21, count 0 2006.280.08:06:52.62#ibcon#read 6, iclass 21, count 0 2006.280.08:06:52.62#ibcon#end of sib2, iclass 21, count 0 2006.280.08:06:52.62#ibcon#*after write, iclass 21, count 0 2006.280.08:06:52.62#ibcon#*before return 0, iclass 21, count 0 2006.280.08:06:52.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:06:52.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:06:52.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:06:52.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:06:52.62$vc4f8/va=5,7 2006.280.08:06:52.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.08:06:52.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.08:06:52.62#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:52.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:06:52.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:06:52.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:06:52.68#ibcon#enter wrdev, iclass 23, count 2 2006.280.08:06:52.68#ibcon#first serial, iclass 23, count 2 2006.280.08:06:52.68#ibcon#enter sib2, iclass 23, count 2 2006.280.08:06:52.68#ibcon#flushed, iclass 23, count 2 2006.280.08:06:52.68#ibcon#about to write, iclass 23, count 2 2006.280.08:06:52.68#ibcon#wrote, iclass 23, count 2 2006.280.08:06:52.68#ibcon#about to read 3, iclass 23, count 2 2006.280.08:06:52.70#ibcon#read 3, iclass 23, count 2 2006.280.08:06:52.70#ibcon#about to read 4, iclass 23, count 2 2006.280.08:06:52.70#ibcon#read 4, iclass 23, count 2 2006.280.08:06:52.70#ibcon#about to read 5, iclass 23, count 2 2006.280.08:06:52.70#ibcon#read 5, iclass 23, count 2 2006.280.08:06:52.70#ibcon#about to read 6, iclass 23, count 2 2006.280.08:06:52.70#ibcon#read 6, iclass 23, count 2 2006.280.08:06:52.70#ibcon#end of sib2, iclass 23, count 2 2006.280.08:06:52.70#ibcon#*mode == 0, iclass 23, count 2 2006.280.08:06:52.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.08:06:52.70#ibcon#[25=AT05-07\r\n] 2006.280.08:06:52.70#ibcon#*before write, iclass 23, count 2 2006.280.08:06:52.70#ibcon#enter sib2, iclass 23, count 2 2006.280.08:06:52.70#ibcon#flushed, iclass 23, count 2 2006.280.08:06:52.70#ibcon#about to write, iclass 23, count 2 2006.280.08:06:52.70#ibcon#wrote, iclass 23, count 2 2006.280.08:06:52.70#ibcon#about to read 3, iclass 23, count 2 2006.280.08:06:52.73#ibcon#read 3, iclass 23, count 2 2006.280.08:06:52.73#ibcon#about to read 4, iclass 23, count 2 2006.280.08:06:52.73#ibcon#read 4, iclass 23, count 2 2006.280.08:06:52.73#ibcon#about to read 5, iclass 23, count 2 2006.280.08:06:52.73#ibcon#read 5, iclass 23, count 2 2006.280.08:06:52.73#ibcon#about to read 6, iclass 23, count 2 2006.280.08:06:52.73#ibcon#read 6, iclass 23, count 2 2006.280.08:06:52.73#ibcon#end of sib2, iclass 23, count 2 2006.280.08:06:52.73#ibcon#*after write, iclass 23, count 2 2006.280.08:06:52.73#ibcon#*before return 0, iclass 23, count 2 2006.280.08:06:52.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:06:52.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:06:52.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.08:06:52.73#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:52.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:06:52.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:06:52.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:06:52.85#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:06:52.85#ibcon#first serial, iclass 23, count 0 2006.280.08:06:52.85#ibcon#enter sib2, iclass 23, count 0 2006.280.08:06:52.85#ibcon#flushed, iclass 23, count 0 2006.280.08:06:52.85#ibcon#about to write, iclass 23, count 0 2006.280.08:06:52.85#ibcon#wrote, iclass 23, count 0 2006.280.08:06:52.85#ibcon#about to read 3, iclass 23, count 0 2006.280.08:06:52.87#ibcon#read 3, iclass 23, count 0 2006.280.08:06:52.87#ibcon#about to read 4, iclass 23, count 0 2006.280.08:06:52.87#ibcon#read 4, iclass 23, count 0 2006.280.08:06:52.87#ibcon#about to read 5, iclass 23, count 0 2006.280.08:06:52.87#ibcon#read 5, iclass 23, count 0 2006.280.08:06:52.87#ibcon#about to read 6, iclass 23, count 0 2006.280.08:06:52.87#ibcon#read 6, iclass 23, count 0 2006.280.08:06:52.87#ibcon#end of sib2, iclass 23, count 0 2006.280.08:06:52.87#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:06:52.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:06:52.87#ibcon#[25=USB\r\n] 2006.280.08:06:52.87#ibcon#*before write, iclass 23, count 0 2006.280.08:06:52.87#ibcon#enter sib2, iclass 23, count 0 2006.280.08:06:52.87#ibcon#flushed, iclass 23, count 0 2006.280.08:06:52.87#ibcon#about to write, iclass 23, count 0 2006.280.08:06:52.87#ibcon#wrote, iclass 23, count 0 2006.280.08:06:52.87#ibcon#about to read 3, iclass 23, count 0 2006.280.08:06:52.90#ibcon#read 3, iclass 23, count 0 2006.280.08:06:52.90#ibcon#about to read 4, iclass 23, count 0 2006.280.08:06:52.90#ibcon#read 4, iclass 23, count 0 2006.280.08:06:52.90#ibcon#about to read 5, iclass 23, count 0 2006.280.08:06:52.90#ibcon#read 5, iclass 23, count 0 2006.280.08:06:52.90#ibcon#about to read 6, iclass 23, count 0 2006.280.08:06:52.90#ibcon#read 6, iclass 23, count 0 2006.280.08:06:52.90#ibcon#end of sib2, iclass 23, count 0 2006.280.08:06:52.90#ibcon#*after write, iclass 23, count 0 2006.280.08:06:52.90#ibcon#*before return 0, iclass 23, count 0 2006.280.08:06:52.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:06:52.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:06:52.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:06:52.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:06:52.90$vc4f8/valo=6,772.99 2006.280.08:06:52.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.08:06:52.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.08:06:52.90#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:52.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:06:52.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:06:52.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:06:52.90#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:06:52.90#ibcon#first serial, iclass 25, count 0 2006.280.08:06:52.90#ibcon#enter sib2, iclass 25, count 0 2006.280.08:06:52.90#ibcon#flushed, iclass 25, count 0 2006.280.08:06:52.90#ibcon#about to write, iclass 25, count 0 2006.280.08:06:52.90#ibcon#wrote, iclass 25, count 0 2006.280.08:06:52.90#ibcon#about to read 3, iclass 25, count 0 2006.280.08:06:52.92#ibcon#read 3, iclass 25, count 0 2006.280.08:06:52.92#ibcon#about to read 4, iclass 25, count 0 2006.280.08:06:52.92#ibcon#read 4, iclass 25, count 0 2006.280.08:06:52.92#ibcon#about to read 5, iclass 25, count 0 2006.280.08:06:52.92#ibcon#read 5, iclass 25, count 0 2006.280.08:06:52.92#ibcon#about to read 6, iclass 25, count 0 2006.280.08:06:52.92#ibcon#read 6, iclass 25, count 0 2006.280.08:06:52.92#ibcon#end of sib2, iclass 25, count 0 2006.280.08:06:52.92#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:06:52.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:06:52.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:06:52.92#ibcon#*before write, iclass 25, count 0 2006.280.08:06:52.92#ibcon#enter sib2, iclass 25, count 0 2006.280.08:06:52.92#ibcon#flushed, iclass 25, count 0 2006.280.08:06:52.92#ibcon#about to write, iclass 25, count 0 2006.280.08:06:52.92#ibcon#wrote, iclass 25, count 0 2006.280.08:06:52.92#ibcon#about to read 3, iclass 25, count 0 2006.280.08:06:52.96#ibcon#read 3, iclass 25, count 0 2006.280.08:06:52.96#ibcon#about to read 4, iclass 25, count 0 2006.280.08:06:52.96#ibcon#read 4, iclass 25, count 0 2006.280.08:06:52.96#ibcon#about to read 5, iclass 25, count 0 2006.280.08:06:52.96#ibcon#read 5, iclass 25, count 0 2006.280.08:06:52.96#ibcon#about to read 6, iclass 25, count 0 2006.280.08:06:52.96#ibcon#read 6, iclass 25, count 0 2006.280.08:06:52.96#ibcon#end of sib2, iclass 25, count 0 2006.280.08:06:52.96#ibcon#*after write, iclass 25, count 0 2006.280.08:06:52.96#ibcon#*before return 0, iclass 25, count 0 2006.280.08:06:52.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:06:52.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:06:52.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:06:52.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:06:52.96$vc4f8/va=6,6 2006.280.08:06:52.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.08:06:52.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.08:06:52.96#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:52.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:06:53.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:06:53.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:06:53.02#ibcon#enter wrdev, iclass 27, count 2 2006.280.08:06:53.02#ibcon#first serial, iclass 27, count 2 2006.280.08:06:53.02#ibcon#enter sib2, iclass 27, count 2 2006.280.08:06:53.02#ibcon#flushed, iclass 27, count 2 2006.280.08:06:53.02#ibcon#about to write, iclass 27, count 2 2006.280.08:06:53.02#ibcon#wrote, iclass 27, count 2 2006.280.08:06:53.02#ibcon#about to read 3, iclass 27, count 2 2006.280.08:06:53.04#ibcon#read 3, iclass 27, count 2 2006.280.08:06:53.04#ibcon#about to read 4, iclass 27, count 2 2006.280.08:06:53.04#ibcon#read 4, iclass 27, count 2 2006.280.08:06:53.04#ibcon#about to read 5, iclass 27, count 2 2006.280.08:06:53.04#ibcon#read 5, iclass 27, count 2 2006.280.08:06:53.04#ibcon#about to read 6, iclass 27, count 2 2006.280.08:06:53.04#ibcon#read 6, iclass 27, count 2 2006.280.08:06:53.04#ibcon#end of sib2, iclass 27, count 2 2006.280.08:06:53.04#ibcon#*mode == 0, iclass 27, count 2 2006.280.08:06:53.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.08:06:53.04#ibcon#[25=AT06-06\r\n] 2006.280.08:06:53.04#ibcon#*before write, iclass 27, count 2 2006.280.08:06:53.04#ibcon#enter sib2, iclass 27, count 2 2006.280.08:06:53.04#ibcon#flushed, iclass 27, count 2 2006.280.08:06:53.04#ibcon#about to write, iclass 27, count 2 2006.280.08:06:53.04#ibcon#wrote, iclass 27, count 2 2006.280.08:06:53.04#ibcon#about to read 3, iclass 27, count 2 2006.280.08:06:53.07#ibcon#read 3, iclass 27, count 2 2006.280.08:06:53.07#ibcon#about to read 4, iclass 27, count 2 2006.280.08:06:53.07#ibcon#read 4, iclass 27, count 2 2006.280.08:06:53.07#ibcon#about to read 5, iclass 27, count 2 2006.280.08:06:53.07#ibcon#read 5, iclass 27, count 2 2006.280.08:06:53.07#ibcon#about to read 6, iclass 27, count 2 2006.280.08:06:53.07#ibcon#read 6, iclass 27, count 2 2006.280.08:06:53.07#ibcon#end of sib2, iclass 27, count 2 2006.280.08:06:53.07#ibcon#*after write, iclass 27, count 2 2006.280.08:06:53.07#ibcon#*before return 0, iclass 27, count 2 2006.280.08:06:53.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:06:53.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:06:53.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.08:06:53.07#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:53.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:06:53.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:06:53.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:06:53.19#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:06:53.19#ibcon#first serial, iclass 27, count 0 2006.280.08:06:53.19#ibcon#enter sib2, iclass 27, count 0 2006.280.08:06:53.19#ibcon#flushed, iclass 27, count 0 2006.280.08:06:53.19#ibcon#about to write, iclass 27, count 0 2006.280.08:06:53.19#ibcon#wrote, iclass 27, count 0 2006.280.08:06:53.19#ibcon#about to read 3, iclass 27, count 0 2006.280.08:06:53.21#ibcon#read 3, iclass 27, count 0 2006.280.08:06:53.21#ibcon#about to read 4, iclass 27, count 0 2006.280.08:06:53.21#ibcon#read 4, iclass 27, count 0 2006.280.08:06:53.21#ibcon#about to read 5, iclass 27, count 0 2006.280.08:06:53.21#ibcon#read 5, iclass 27, count 0 2006.280.08:06:53.21#ibcon#about to read 6, iclass 27, count 0 2006.280.08:06:53.21#ibcon#read 6, iclass 27, count 0 2006.280.08:06:53.21#ibcon#end of sib2, iclass 27, count 0 2006.280.08:06:53.21#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:06:53.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:06:53.21#ibcon#[25=USB\r\n] 2006.280.08:06:53.21#ibcon#*before write, iclass 27, count 0 2006.280.08:06:53.21#ibcon#enter sib2, iclass 27, count 0 2006.280.08:06:53.21#ibcon#flushed, iclass 27, count 0 2006.280.08:06:53.21#ibcon#about to write, iclass 27, count 0 2006.280.08:06:53.21#ibcon#wrote, iclass 27, count 0 2006.280.08:06:53.21#ibcon#about to read 3, iclass 27, count 0 2006.280.08:06:53.24#ibcon#read 3, iclass 27, count 0 2006.280.08:06:53.24#ibcon#about to read 4, iclass 27, count 0 2006.280.08:06:53.24#ibcon#read 4, iclass 27, count 0 2006.280.08:06:53.24#ibcon#about to read 5, iclass 27, count 0 2006.280.08:06:53.24#ibcon#read 5, iclass 27, count 0 2006.280.08:06:53.24#ibcon#about to read 6, iclass 27, count 0 2006.280.08:06:53.24#ibcon#read 6, iclass 27, count 0 2006.280.08:06:53.24#ibcon#end of sib2, iclass 27, count 0 2006.280.08:06:53.24#ibcon#*after write, iclass 27, count 0 2006.280.08:06:53.24#ibcon#*before return 0, iclass 27, count 0 2006.280.08:06:53.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:06:53.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:06:53.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:06:53.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:06:53.24$vc4f8/valo=7,832.99 2006.280.08:06:53.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.08:06:53.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.08:06:53.24#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:53.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:53.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:53.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:53.24#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:06:53.24#ibcon#first serial, iclass 29, count 0 2006.280.08:06:53.24#ibcon#enter sib2, iclass 29, count 0 2006.280.08:06:53.24#ibcon#flushed, iclass 29, count 0 2006.280.08:06:53.24#ibcon#about to write, iclass 29, count 0 2006.280.08:06:53.24#ibcon#wrote, iclass 29, count 0 2006.280.08:06:53.24#ibcon#about to read 3, iclass 29, count 0 2006.280.08:06:53.26#ibcon#read 3, iclass 29, count 0 2006.280.08:06:53.26#ibcon#about to read 4, iclass 29, count 0 2006.280.08:06:53.26#ibcon#read 4, iclass 29, count 0 2006.280.08:06:53.26#ibcon#about to read 5, iclass 29, count 0 2006.280.08:06:53.26#ibcon#read 5, iclass 29, count 0 2006.280.08:06:53.26#ibcon#about to read 6, iclass 29, count 0 2006.280.08:06:53.26#ibcon#read 6, iclass 29, count 0 2006.280.08:06:53.26#ibcon#end of sib2, iclass 29, count 0 2006.280.08:06:53.26#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:06:53.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:06:53.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:06:53.26#ibcon#*before write, iclass 29, count 0 2006.280.08:06:53.26#ibcon#enter sib2, iclass 29, count 0 2006.280.08:06:53.26#ibcon#flushed, iclass 29, count 0 2006.280.08:06:53.26#ibcon#about to write, iclass 29, count 0 2006.280.08:06:53.26#ibcon#wrote, iclass 29, count 0 2006.280.08:06:53.26#ibcon#about to read 3, iclass 29, count 0 2006.280.08:06:53.30#ibcon#read 3, iclass 29, count 0 2006.280.08:06:53.30#ibcon#about to read 4, iclass 29, count 0 2006.280.08:06:53.30#ibcon#read 4, iclass 29, count 0 2006.280.08:06:53.30#ibcon#about to read 5, iclass 29, count 0 2006.280.08:06:53.30#ibcon#read 5, iclass 29, count 0 2006.280.08:06:53.30#ibcon#about to read 6, iclass 29, count 0 2006.280.08:06:53.30#ibcon#read 6, iclass 29, count 0 2006.280.08:06:53.30#ibcon#end of sib2, iclass 29, count 0 2006.280.08:06:53.30#ibcon#*after write, iclass 29, count 0 2006.280.08:06:53.30#ibcon#*before return 0, iclass 29, count 0 2006.280.08:06:53.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:53.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:53.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:06:53.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:06:53.30$vc4f8/va=7,6 2006.280.08:06:53.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.280.08:06:53.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.280.08:06:53.30#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:53.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:53.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:53.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:53.36#ibcon#enter wrdev, iclass 31, count 2 2006.280.08:06:53.36#ibcon#first serial, iclass 31, count 2 2006.280.08:06:53.36#ibcon#enter sib2, iclass 31, count 2 2006.280.08:06:53.36#ibcon#flushed, iclass 31, count 2 2006.280.08:06:53.36#ibcon#about to write, iclass 31, count 2 2006.280.08:06:53.36#ibcon#wrote, iclass 31, count 2 2006.280.08:06:53.36#ibcon#about to read 3, iclass 31, count 2 2006.280.08:06:53.38#ibcon#read 3, iclass 31, count 2 2006.280.08:06:53.38#ibcon#about to read 4, iclass 31, count 2 2006.280.08:06:53.38#ibcon#read 4, iclass 31, count 2 2006.280.08:06:53.38#ibcon#about to read 5, iclass 31, count 2 2006.280.08:06:53.38#ibcon#read 5, iclass 31, count 2 2006.280.08:06:53.38#ibcon#about to read 6, iclass 31, count 2 2006.280.08:06:53.38#ibcon#read 6, iclass 31, count 2 2006.280.08:06:53.38#ibcon#end of sib2, iclass 31, count 2 2006.280.08:06:53.38#ibcon#*mode == 0, iclass 31, count 2 2006.280.08:06:53.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.280.08:06:53.38#ibcon#[25=AT07-06\r\n] 2006.280.08:06:53.38#ibcon#*before write, iclass 31, count 2 2006.280.08:06:53.38#ibcon#enter sib2, iclass 31, count 2 2006.280.08:06:53.38#ibcon#flushed, iclass 31, count 2 2006.280.08:06:53.38#ibcon#about to write, iclass 31, count 2 2006.280.08:06:53.38#ibcon#wrote, iclass 31, count 2 2006.280.08:06:53.38#ibcon#about to read 3, iclass 31, count 2 2006.280.08:06:53.42#ibcon#read 3, iclass 31, count 2 2006.280.08:06:53.42#ibcon#about to read 4, iclass 31, count 2 2006.280.08:06:53.42#ibcon#read 4, iclass 31, count 2 2006.280.08:06:53.42#ibcon#about to read 5, iclass 31, count 2 2006.280.08:06:53.42#ibcon#read 5, iclass 31, count 2 2006.280.08:06:53.42#ibcon#about to read 6, iclass 31, count 2 2006.280.08:06:53.42#ibcon#read 6, iclass 31, count 2 2006.280.08:06:53.42#ibcon#end of sib2, iclass 31, count 2 2006.280.08:06:53.42#ibcon#*after write, iclass 31, count 2 2006.280.08:06:53.42#ibcon#*before return 0, iclass 31, count 2 2006.280.08:06:53.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:53.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:53.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.280.08:06:53.42#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:53.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.08:06:53.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.280.08:06:53.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.08:06:53.54#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:06:53.54#ibcon#first serial, iclass 31, count 0 2006.280.08:06:53.54#ibcon#enter sib2, iclass 31, count 0 2006.280.08:06:53.54#ibcon#flushed, iclass 31, count 0 2006.280.08:06:53.54#ibcon#about to write, iclass 31, count 0 2006.280.08:06:53.54#ibcon#wrote, iclass 31, count 0 2006.280.08:06:53.54#ibcon#about to read 3, iclass 31, count 0 2006.280.08:06:53.56#ibcon#read 3, iclass 31, count 0 2006.280.08:06:53.56#ibcon#about to read 4, iclass 31, count 0 2006.280.08:06:53.56#ibcon#read 4, iclass 31, count 0 2006.280.08:06:53.56#ibcon#about to read 5, iclass 31, count 0 2006.280.08:06:53.56#ibcon#read 5, iclass 31, count 0 2006.280.08:06:53.56#ibcon#about to read 6, iclass 31, count 0 2006.280.08:06:53.56#ibcon#read 6, iclass 31, count 0 2006.280.08:06:53.56#ibcon#end of sib2, iclass 31, count 0 2006.280.08:06:53.56#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:06:53.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:06:53.56#ibcon#[25=USB\r\n] 2006.280.08:06:53.56#ibcon#*before write, iclass 31, count 0 2006.280.08:06:53.56#ibcon#enter sib2, iclass 31, count 0 2006.280.08:06:53.56#ibcon#flushed, iclass 31, count 0 2006.280.08:06:53.56#ibcon#about to write, iclass 31, count 0 2006.280.08:06:53.56#ibcon#wrote, iclass 31, count 0 2006.280.08:06:53.56#ibcon#about to read 3, iclass 31, count 0 2006.280.08:06:53.59#ibcon#read 3, iclass 31, count 0 2006.280.08:06:53.59#ibcon#about to read 4, iclass 31, count 0 2006.280.08:06:53.59#ibcon#read 4, iclass 31, count 0 2006.280.08:06:53.59#ibcon#about to read 5, iclass 31, count 0 2006.280.08:06:53.59#ibcon#read 5, iclass 31, count 0 2006.280.08:06:53.59#ibcon#about to read 6, iclass 31, count 0 2006.280.08:06:53.59#ibcon#read 6, iclass 31, count 0 2006.280.08:06:53.59#ibcon#end of sib2, iclass 31, count 0 2006.280.08:06:53.59#ibcon#*after write, iclass 31, count 0 2006.280.08:06:53.59#ibcon#*before return 0, iclass 31, count 0 2006.280.08:06:53.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.280.08:06:53.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.280.08:06:53.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:06:53.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:06:53.59$vc4f8/valo=8,852.99 2006.280.08:06:53.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.08:06:53.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.08:06:53.59#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:53.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:06:53.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:06:53.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:06:53.59#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:06:53.59#ibcon#first serial, iclass 33, count 0 2006.280.08:06:53.59#ibcon#enter sib2, iclass 33, count 0 2006.280.08:06:53.59#ibcon#flushed, iclass 33, count 0 2006.280.08:06:53.59#ibcon#about to write, iclass 33, count 0 2006.280.08:06:53.59#ibcon#wrote, iclass 33, count 0 2006.280.08:06:53.59#ibcon#about to read 3, iclass 33, count 0 2006.280.08:06:53.61#ibcon#read 3, iclass 33, count 0 2006.280.08:06:53.61#ibcon#about to read 4, iclass 33, count 0 2006.280.08:06:53.61#ibcon#read 4, iclass 33, count 0 2006.280.08:06:53.61#ibcon#about to read 5, iclass 33, count 0 2006.280.08:06:53.61#ibcon#read 5, iclass 33, count 0 2006.280.08:06:53.61#ibcon#about to read 6, iclass 33, count 0 2006.280.08:06:53.61#ibcon#read 6, iclass 33, count 0 2006.280.08:06:53.61#ibcon#end of sib2, iclass 33, count 0 2006.280.08:06:53.61#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:06:53.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:06:53.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:06:53.63#ibcon#*before write, iclass 33, count 0 2006.280.08:06:53.63#ibcon#enter sib2, iclass 33, count 0 2006.280.08:06:53.63#ibcon#flushed, iclass 33, count 0 2006.280.08:06:53.63#ibcon#about to write, iclass 33, count 0 2006.280.08:06:53.63#ibcon#wrote, iclass 33, count 0 2006.280.08:06:53.63#ibcon#about to read 3, iclass 33, count 0 2006.280.08:06:53.68#ibcon#read 3, iclass 33, count 0 2006.280.08:06:53.68#ibcon#about to read 4, iclass 33, count 0 2006.280.08:06:53.68#ibcon#read 4, iclass 33, count 0 2006.280.08:06:53.68#ibcon#about to read 5, iclass 33, count 0 2006.280.08:06:53.68#ibcon#read 5, iclass 33, count 0 2006.280.08:06:53.68#ibcon#about to read 6, iclass 33, count 0 2006.280.08:06:53.68#ibcon#read 6, iclass 33, count 0 2006.280.08:06:53.68#ibcon#end of sib2, iclass 33, count 0 2006.280.08:06:53.68#ibcon#*after write, iclass 33, count 0 2006.280.08:06:53.68#ibcon#*before return 0, iclass 33, count 0 2006.280.08:06:53.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:06:53.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:06:53.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:06:53.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:06:53.68$vc4f8/va=8,6 2006.280.08:06:53.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.08:06:53.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.08:06:53.68#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:53.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:06:53.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:06:53.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:06:53.71#ibcon#enter wrdev, iclass 35, count 2 2006.280.08:06:53.71#ibcon#first serial, iclass 35, count 2 2006.280.08:06:53.71#ibcon#enter sib2, iclass 35, count 2 2006.280.08:06:53.71#ibcon#flushed, iclass 35, count 2 2006.280.08:06:53.71#ibcon#about to write, iclass 35, count 2 2006.280.08:06:53.71#ibcon#wrote, iclass 35, count 2 2006.280.08:06:53.71#ibcon#about to read 3, iclass 35, count 2 2006.280.08:06:53.73#ibcon#read 3, iclass 35, count 2 2006.280.08:06:53.73#ibcon#about to read 4, iclass 35, count 2 2006.280.08:06:53.73#ibcon#read 4, iclass 35, count 2 2006.280.08:06:53.73#ibcon#about to read 5, iclass 35, count 2 2006.280.08:06:53.73#ibcon#read 5, iclass 35, count 2 2006.280.08:06:53.73#ibcon#about to read 6, iclass 35, count 2 2006.280.08:06:53.73#ibcon#read 6, iclass 35, count 2 2006.280.08:06:53.73#ibcon#end of sib2, iclass 35, count 2 2006.280.08:06:53.73#ibcon#*mode == 0, iclass 35, count 2 2006.280.08:06:53.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.08:06:53.73#ibcon#[25=AT08-06\r\n] 2006.280.08:06:53.73#ibcon#*before write, iclass 35, count 2 2006.280.08:06:53.73#ibcon#enter sib2, iclass 35, count 2 2006.280.08:06:53.73#ibcon#flushed, iclass 35, count 2 2006.280.08:06:53.73#ibcon#about to write, iclass 35, count 2 2006.280.08:06:53.73#ibcon#wrote, iclass 35, count 2 2006.280.08:06:53.73#ibcon#about to read 3, iclass 35, count 2 2006.280.08:06:53.76#ibcon#read 3, iclass 35, count 2 2006.280.08:06:53.76#ibcon#about to read 4, iclass 35, count 2 2006.280.08:06:53.76#ibcon#read 4, iclass 35, count 2 2006.280.08:06:53.76#ibcon#about to read 5, iclass 35, count 2 2006.280.08:06:53.76#ibcon#read 5, iclass 35, count 2 2006.280.08:06:53.76#ibcon#about to read 6, iclass 35, count 2 2006.280.08:06:53.76#ibcon#read 6, iclass 35, count 2 2006.280.08:06:53.76#ibcon#end of sib2, iclass 35, count 2 2006.280.08:06:53.76#ibcon#*after write, iclass 35, count 2 2006.280.08:06:53.76#ibcon#*before return 0, iclass 35, count 2 2006.280.08:06:53.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:06:53.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:06:53.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.08:06:53.76#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:53.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:06:53.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:06:53.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:06:53.88#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:06:53.88#ibcon#first serial, iclass 35, count 0 2006.280.08:06:53.88#ibcon#enter sib2, iclass 35, count 0 2006.280.08:06:53.88#ibcon#flushed, iclass 35, count 0 2006.280.08:06:53.88#ibcon#about to write, iclass 35, count 0 2006.280.08:06:53.88#ibcon#wrote, iclass 35, count 0 2006.280.08:06:53.88#ibcon#about to read 3, iclass 35, count 0 2006.280.08:06:53.90#ibcon#read 3, iclass 35, count 0 2006.280.08:06:53.90#ibcon#about to read 4, iclass 35, count 0 2006.280.08:06:53.90#ibcon#read 4, iclass 35, count 0 2006.280.08:06:53.90#ibcon#about to read 5, iclass 35, count 0 2006.280.08:06:53.90#ibcon#read 5, iclass 35, count 0 2006.280.08:06:53.90#ibcon#about to read 6, iclass 35, count 0 2006.280.08:06:53.90#ibcon#read 6, iclass 35, count 0 2006.280.08:06:53.90#ibcon#end of sib2, iclass 35, count 0 2006.280.08:06:53.90#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:06:53.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:06:53.90#ibcon#[25=USB\r\n] 2006.280.08:06:53.90#ibcon#*before write, iclass 35, count 0 2006.280.08:06:53.90#ibcon#enter sib2, iclass 35, count 0 2006.280.08:06:53.90#ibcon#flushed, iclass 35, count 0 2006.280.08:06:53.90#ibcon#about to write, iclass 35, count 0 2006.280.08:06:53.90#ibcon#wrote, iclass 35, count 0 2006.280.08:06:53.90#ibcon#about to read 3, iclass 35, count 0 2006.280.08:06:53.93#ibcon#read 3, iclass 35, count 0 2006.280.08:06:53.93#ibcon#about to read 4, iclass 35, count 0 2006.280.08:06:53.93#ibcon#read 4, iclass 35, count 0 2006.280.08:06:53.93#ibcon#about to read 5, iclass 35, count 0 2006.280.08:06:53.93#ibcon#read 5, iclass 35, count 0 2006.280.08:06:53.93#ibcon#about to read 6, iclass 35, count 0 2006.280.08:06:53.93#ibcon#read 6, iclass 35, count 0 2006.280.08:06:53.93#ibcon#end of sib2, iclass 35, count 0 2006.280.08:06:53.93#ibcon#*after write, iclass 35, count 0 2006.280.08:06:53.93#ibcon#*before return 0, iclass 35, count 0 2006.280.08:06:53.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:06:53.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:06:53.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:06:53.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:06:53.93$vc4f8/vblo=1,632.99 2006.280.08:06:53.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.08:06:53.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.08:06:53.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:53.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:06:53.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:06:53.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:06:53.93#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:06:53.93#ibcon#first serial, iclass 37, count 0 2006.280.08:06:53.93#ibcon#enter sib2, iclass 37, count 0 2006.280.08:06:53.93#ibcon#flushed, iclass 37, count 0 2006.280.08:06:53.93#ibcon#about to write, iclass 37, count 0 2006.280.08:06:53.93#ibcon#wrote, iclass 37, count 0 2006.280.08:06:53.93#ibcon#about to read 3, iclass 37, count 0 2006.280.08:06:53.95#ibcon#read 3, iclass 37, count 0 2006.280.08:06:53.95#ibcon#about to read 4, iclass 37, count 0 2006.280.08:06:53.95#ibcon#read 4, iclass 37, count 0 2006.280.08:06:53.95#ibcon#about to read 5, iclass 37, count 0 2006.280.08:06:53.95#ibcon#read 5, iclass 37, count 0 2006.280.08:06:53.95#ibcon#about to read 6, iclass 37, count 0 2006.280.08:06:53.95#ibcon#read 6, iclass 37, count 0 2006.280.08:06:53.95#ibcon#end of sib2, iclass 37, count 0 2006.280.08:06:53.95#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:06:53.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:06:53.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:06:53.95#ibcon#*before write, iclass 37, count 0 2006.280.08:06:53.95#ibcon#enter sib2, iclass 37, count 0 2006.280.08:06:53.95#ibcon#flushed, iclass 37, count 0 2006.280.08:06:53.95#ibcon#about to write, iclass 37, count 0 2006.280.08:06:53.95#ibcon#wrote, iclass 37, count 0 2006.280.08:06:53.95#ibcon#about to read 3, iclass 37, count 0 2006.280.08:06:53.99#ibcon#read 3, iclass 37, count 0 2006.280.08:06:53.99#ibcon#about to read 4, iclass 37, count 0 2006.280.08:06:53.99#ibcon#read 4, iclass 37, count 0 2006.280.08:06:53.99#ibcon#about to read 5, iclass 37, count 0 2006.280.08:06:53.99#ibcon#read 5, iclass 37, count 0 2006.280.08:06:53.99#ibcon#about to read 6, iclass 37, count 0 2006.280.08:06:53.99#ibcon#read 6, iclass 37, count 0 2006.280.08:06:53.99#ibcon#end of sib2, iclass 37, count 0 2006.280.08:06:53.99#ibcon#*after write, iclass 37, count 0 2006.280.08:06:53.99#ibcon#*before return 0, iclass 37, count 0 2006.280.08:06:53.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:06:53.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:06:53.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:06:53.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:06:53.99$vc4f8/vb=1,4 2006.280.08:06:53.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.08:06:53.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.08:06:53.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:53.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:06:53.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:06:53.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:06:53.99#ibcon#enter wrdev, iclass 39, count 2 2006.280.08:06:53.99#ibcon#first serial, iclass 39, count 2 2006.280.08:06:53.99#ibcon#enter sib2, iclass 39, count 2 2006.280.08:06:53.99#ibcon#flushed, iclass 39, count 2 2006.280.08:06:53.99#ibcon#about to write, iclass 39, count 2 2006.280.08:06:53.99#ibcon#wrote, iclass 39, count 2 2006.280.08:06:53.99#ibcon#about to read 3, iclass 39, count 2 2006.280.08:06:54.01#ibcon#read 3, iclass 39, count 2 2006.280.08:06:54.01#ibcon#about to read 4, iclass 39, count 2 2006.280.08:06:54.01#ibcon#read 4, iclass 39, count 2 2006.280.08:06:54.01#ibcon#about to read 5, iclass 39, count 2 2006.280.08:06:54.01#ibcon#read 5, iclass 39, count 2 2006.280.08:06:54.01#ibcon#about to read 6, iclass 39, count 2 2006.280.08:06:54.01#ibcon#read 6, iclass 39, count 2 2006.280.08:06:54.01#ibcon#end of sib2, iclass 39, count 2 2006.280.08:06:54.01#ibcon#*mode == 0, iclass 39, count 2 2006.280.08:06:54.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.08:06:54.01#ibcon#[27=AT01-04\r\n] 2006.280.08:06:54.01#ibcon#*before write, iclass 39, count 2 2006.280.08:06:54.01#ibcon#enter sib2, iclass 39, count 2 2006.280.08:06:54.01#ibcon#flushed, iclass 39, count 2 2006.280.08:06:54.01#ibcon#about to write, iclass 39, count 2 2006.280.08:06:54.01#ibcon#wrote, iclass 39, count 2 2006.280.08:06:54.01#ibcon#about to read 3, iclass 39, count 2 2006.280.08:06:54.04#ibcon#read 3, iclass 39, count 2 2006.280.08:06:54.04#ibcon#about to read 4, iclass 39, count 2 2006.280.08:06:54.04#ibcon#read 4, iclass 39, count 2 2006.280.08:06:54.04#ibcon#about to read 5, iclass 39, count 2 2006.280.08:06:54.04#ibcon#read 5, iclass 39, count 2 2006.280.08:06:54.04#ibcon#about to read 6, iclass 39, count 2 2006.280.08:06:54.04#ibcon#read 6, iclass 39, count 2 2006.280.08:06:54.04#ibcon#end of sib2, iclass 39, count 2 2006.280.08:06:54.04#ibcon#*after write, iclass 39, count 2 2006.280.08:06:54.04#ibcon#*before return 0, iclass 39, count 2 2006.280.08:06:54.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:06:54.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:06:54.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.08:06:54.04#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:54.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:06:54.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:06:54.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:06:54.16#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:06:54.16#ibcon#first serial, iclass 39, count 0 2006.280.08:06:54.16#ibcon#enter sib2, iclass 39, count 0 2006.280.08:06:54.16#ibcon#flushed, iclass 39, count 0 2006.280.08:06:54.16#ibcon#about to write, iclass 39, count 0 2006.280.08:06:54.16#ibcon#wrote, iclass 39, count 0 2006.280.08:06:54.16#ibcon#about to read 3, iclass 39, count 0 2006.280.08:06:54.18#ibcon#read 3, iclass 39, count 0 2006.280.08:06:54.18#ibcon#about to read 4, iclass 39, count 0 2006.280.08:06:54.18#ibcon#read 4, iclass 39, count 0 2006.280.08:06:54.18#ibcon#about to read 5, iclass 39, count 0 2006.280.08:06:54.18#ibcon#read 5, iclass 39, count 0 2006.280.08:06:54.18#ibcon#about to read 6, iclass 39, count 0 2006.280.08:06:54.18#ibcon#read 6, iclass 39, count 0 2006.280.08:06:54.18#ibcon#end of sib2, iclass 39, count 0 2006.280.08:06:54.18#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:06:54.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:06:54.18#ibcon#[27=USB\r\n] 2006.280.08:06:54.18#ibcon#*before write, iclass 39, count 0 2006.280.08:06:54.18#ibcon#enter sib2, iclass 39, count 0 2006.280.08:06:54.18#ibcon#flushed, iclass 39, count 0 2006.280.08:06:54.18#ibcon#about to write, iclass 39, count 0 2006.280.08:06:54.18#ibcon#wrote, iclass 39, count 0 2006.280.08:06:54.18#ibcon#about to read 3, iclass 39, count 0 2006.280.08:06:54.21#ibcon#read 3, iclass 39, count 0 2006.280.08:06:54.21#ibcon#about to read 4, iclass 39, count 0 2006.280.08:06:54.21#ibcon#read 4, iclass 39, count 0 2006.280.08:06:54.21#ibcon#about to read 5, iclass 39, count 0 2006.280.08:06:54.21#ibcon#read 5, iclass 39, count 0 2006.280.08:06:54.21#ibcon#about to read 6, iclass 39, count 0 2006.280.08:06:54.21#ibcon#read 6, iclass 39, count 0 2006.280.08:06:54.21#ibcon#end of sib2, iclass 39, count 0 2006.280.08:06:54.21#ibcon#*after write, iclass 39, count 0 2006.280.08:06:54.21#ibcon#*before return 0, iclass 39, count 0 2006.280.08:06:54.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:06:54.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:06:54.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:06:54.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:06:54.21$vc4f8/vblo=2,640.99 2006.280.08:06:54.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.08:06:54.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.08:06:54.21#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:54.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:54.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:54.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:54.21#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:06:54.21#ibcon#first serial, iclass 3, count 0 2006.280.08:06:54.21#ibcon#enter sib2, iclass 3, count 0 2006.280.08:06:54.21#ibcon#flushed, iclass 3, count 0 2006.280.08:06:54.21#ibcon#about to write, iclass 3, count 0 2006.280.08:06:54.21#ibcon#wrote, iclass 3, count 0 2006.280.08:06:54.21#ibcon#about to read 3, iclass 3, count 0 2006.280.08:06:54.23#ibcon#read 3, iclass 3, count 0 2006.280.08:06:54.23#ibcon#about to read 4, iclass 3, count 0 2006.280.08:06:54.23#ibcon#read 4, iclass 3, count 0 2006.280.08:06:54.23#ibcon#about to read 5, iclass 3, count 0 2006.280.08:06:54.23#ibcon#read 5, iclass 3, count 0 2006.280.08:06:54.23#ibcon#about to read 6, iclass 3, count 0 2006.280.08:06:54.23#ibcon#read 6, iclass 3, count 0 2006.280.08:06:54.23#ibcon#end of sib2, iclass 3, count 0 2006.280.08:06:54.23#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:06:54.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:06:54.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:06:54.23#ibcon#*before write, iclass 3, count 0 2006.280.08:06:54.23#ibcon#enter sib2, iclass 3, count 0 2006.280.08:06:54.23#ibcon#flushed, iclass 3, count 0 2006.280.08:06:54.23#ibcon#about to write, iclass 3, count 0 2006.280.08:06:54.23#ibcon#wrote, iclass 3, count 0 2006.280.08:06:54.23#ibcon#about to read 3, iclass 3, count 0 2006.280.08:06:54.27#ibcon#read 3, iclass 3, count 0 2006.280.08:06:54.27#ibcon#about to read 4, iclass 3, count 0 2006.280.08:06:54.27#ibcon#read 4, iclass 3, count 0 2006.280.08:06:54.27#ibcon#about to read 5, iclass 3, count 0 2006.280.08:06:54.27#ibcon#read 5, iclass 3, count 0 2006.280.08:06:54.27#ibcon#about to read 6, iclass 3, count 0 2006.280.08:06:54.27#ibcon#read 6, iclass 3, count 0 2006.280.08:06:54.27#ibcon#end of sib2, iclass 3, count 0 2006.280.08:06:54.27#ibcon#*after write, iclass 3, count 0 2006.280.08:06:54.27#ibcon#*before return 0, iclass 3, count 0 2006.280.08:06:54.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:54.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:06:54.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:06:54.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:06:54.27$vc4f8/vb=2,5 2006.280.08:06:54.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.08:06:54.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.08:06:54.28#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:54.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:54.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:54.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:54.32#ibcon#enter wrdev, iclass 5, count 2 2006.280.08:06:54.32#ibcon#first serial, iclass 5, count 2 2006.280.08:06:54.32#ibcon#enter sib2, iclass 5, count 2 2006.280.08:06:54.32#ibcon#flushed, iclass 5, count 2 2006.280.08:06:54.32#ibcon#about to write, iclass 5, count 2 2006.280.08:06:54.32#ibcon#wrote, iclass 5, count 2 2006.280.08:06:54.32#ibcon#about to read 3, iclass 5, count 2 2006.280.08:06:54.34#ibcon#read 3, iclass 5, count 2 2006.280.08:06:54.34#ibcon#about to read 4, iclass 5, count 2 2006.280.08:06:54.34#ibcon#read 4, iclass 5, count 2 2006.280.08:06:54.34#ibcon#about to read 5, iclass 5, count 2 2006.280.08:06:54.34#ibcon#read 5, iclass 5, count 2 2006.280.08:06:54.34#ibcon#about to read 6, iclass 5, count 2 2006.280.08:06:54.34#ibcon#read 6, iclass 5, count 2 2006.280.08:06:54.34#ibcon#end of sib2, iclass 5, count 2 2006.280.08:06:54.34#ibcon#*mode == 0, iclass 5, count 2 2006.280.08:06:54.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.08:06:54.34#ibcon#[27=AT02-05\r\n] 2006.280.08:06:54.34#ibcon#*before write, iclass 5, count 2 2006.280.08:06:54.34#ibcon#enter sib2, iclass 5, count 2 2006.280.08:06:54.34#ibcon#flushed, iclass 5, count 2 2006.280.08:06:54.34#ibcon#about to write, iclass 5, count 2 2006.280.08:06:54.34#ibcon#wrote, iclass 5, count 2 2006.280.08:06:54.34#ibcon#about to read 3, iclass 5, count 2 2006.280.08:06:54.37#ibcon#read 3, iclass 5, count 2 2006.280.08:06:54.37#ibcon#about to read 4, iclass 5, count 2 2006.280.08:06:54.37#ibcon#read 4, iclass 5, count 2 2006.280.08:06:54.37#ibcon#about to read 5, iclass 5, count 2 2006.280.08:06:54.37#ibcon#read 5, iclass 5, count 2 2006.280.08:06:54.37#ibcon#about to read 6, iclass 5, count 2 2006.280.08:06:54.37#ibcon#read 6, iclass 5, count 2 2006.280.08:06:54.37#ibcon#end of sib2, iclass 5, count 2 2006.280.08:06:54.37#ibcon#*after write, iclass 5, count 2 2006.280.08:06:54.37#ibcon#*before return 0, iclass 5, count 2 2006.280.08:06:54.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:54.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:06:54.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.08:06:54.37#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:54.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:54.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:54.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:54.49#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:06:54.49#ibcon#first serial, iclass 5, count 0 2006.280.08:06:54.49#ibcon#enter sib2, iclass 5, count 0 2006.280.08:06:54.49#ibcon#flushed, iclass 5, count 0 2006.280.08:06:54.49#ibcon#about to write, iclass 5, count 0 2006.280.08:06:54.49#ibcon#wrote, iclass 5, count 0 2006.280.08:06:54.49#ibcon#about to read 3, iclass 5, count 0 2006.280.08:06:54.51#ibcon#read 3, iclass 5, count 0 2006.280.08:06:54.51#ibcon#about to read 4, iclass 5, count 0 2006.280.08:06:54.51#ibcon#read 4, iclass 5, count 0 2006.280.08:06:54.51#ibcon#about to read 5, iclass 5, count 0 2006.280.08:06:54.51#ibcon#read 5, iclass 5, count 0 2006.280.08:06:54.51#ibcon#about to read 6, iclass 5, count 0 2006.280.08:06:54.51#ibcon#read 6, iclass 5, count 0 2006.280.08:06:54.51#ibcon#end of sib2, iclass 5, count 0 2006.280.08:06:54.51#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:06:54.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:06:54.51#ibcon#[27=USB\r\n] 2006.280.08:06:54.51#ibcon#*before write, iclass 5, count 0 2006.280.08:06:54.51#ibcon#enter sib2, iclass 5, count 0 2006.280.08:06:54.51#ibcon#flushed, iclass 5, count 0 2006.280.08:06:54.51#ibcon#about to write, iclass 5, count 0 2006.280.08:06:54.51#ibcon#wrote, iclass 5, count 0 2006.280.08:06:54.51#ibcon#about to read 3, iclass 5, count 0 2006.280.08:06:54.54#ibcon#read 3, iclass 5, count 0 2006.280.08:06:54.54#ibcon#about to read 4, iclass 5, count 0 2006.280.08:06:54.54#ibcon#read 4, iclass 5, count 0 2006.280.08:06:54.54#ibcon#about to read 5, iclass 5, count 0 2006.280.08:06:54.54#ibcon#read 5, iclass 5, count 0 2006.280.08:06:54.54#ibcon#about to read 6, iclass 5, count 0 2006.280.08:06:54.54#ibcon#read 6, iclass 5, count 0 2006.280.08:06:54.54#ibcon#end of sib2, iclass 5, count 0 2006.280.08:06:54.54#ibcon#*after write, iclass 5, count 0 2006.280.08:06:54.54#ibcon#*before return 0, iclass 5, count 0 2006.280.08:06:54.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:54.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:06:54.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:06:54.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:06:54.54$vc4f8/vblo=3,656.99 2006.280.08:06:54.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.08:06:54.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.08:06:54.54#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:54.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:54.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:54.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:54.54#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:06:54.54#ibcon#first serial, iclass 7, count 0 2006.280.08:06:54.54#ibcon#enter sib2, iclass 7, count 0 2006.280.08:06:54.54#ibcon#flushed, iclass 7, count 0 2006.280.08:06:54.54#ibcon#about to write, iclass 7, count 0 2006.280.08:06:54.54#ibcon#wrote, iclass 7, count 0 2006.280.08:06:54.54#ibcon#about to read 3, iclass 7, count 0 2006.280.08:06:54.56#ibcon#read 3, iclass 7, count 0 2006.280.08:06:54.56#ibcon#about to read 4, iclass 7, count 0 2006.280.08:06:54.56#ibcon#read 4, iclass 7, count 0 2006.280.08:06:54.56#ibcon#about to read 5, iclass 7, count 0 2006.280.08:06:54.56#ibcon#read 5, iclass 7, count 0 2006.280.08:06:54.56#ibcon#about to read 6, iclass 7, count 0 2006.280.08:06:54.56#ibcon#read 6, iclass 7, count 0 2006.280.08:06:54.56#ibcon#end of sib2, iclass 7, count 0 2006.280.08:06:54.56#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:06:54.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:06:54.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:06:54.58#ibcon#*before write, iclass 7, count 0 2006.280.08:06:54.58#ibcon#enter sib2, iclass 7, count 0 2006.280.08:06:54.58#ibcon#flushed, iclass 7, count 0 2006.280.08:06:54.58#ibcon#about to write, iclass 7, count 0 2006.280.08:06:54.58#ibcon#wrote, iclass 7, count 0 2006.280.08:06:54.58#ibcon#about to read 3, iclass 7, count 0 2006.280.08:06:54.63#ibcon#read 3, iclass 7, count 0 2006.280.08:06:54.63#ibcon#about to read 4, iclass 7, count 0 2006.280.08:06:54.63#ibcon#read 4, iclass 7, count 0 2006.280.08:06:54.63#ibcon#about to read 5, iclass 7, count 0 2006.280.08:06:54.63#ibcon#read 5, iclass 7, count 0 2006.280.08:06:54.63#ibcon#about to read 6, iclass 7, count 0 2006.280.08:06:54.63#ibcon#read 6, iclass 7, count 0 2006.280.08:06:54.63#ibcon#end of sib2, iclass 7, count 0 2006.280.08:06:54.63#ibcon#*after write, iclass 7, count 0 2006.280.08:06:54.63#ibcon#*before return 0, iclass 7, count 0 2006.280.08:06:54.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:54.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:06:54.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:06:54.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:06:54.63$vc4f8/vb=3,4 2006.280.08:06:54.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.08:06:54.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.08:06:54.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:54.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:54.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:54.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:54.66#ibcon#enter wrdev, iclass 11, count 2 2006.280.08:06:54.66#ibcon#first serial, iclass 11, count 2 2006.280.08:06:54.66#ibcon#enter sib2, iclass 11, count 2 2006.280.08:06:54.66#ibcon#flushed, iclass 11, count 2 2006.280.08:06:54.66#ibcon#about to write, iclass 11, count 2 2006.280.08:06:54.66#ibcon#wrote, iclass 11, count 2 2006.280.08:06:54.66#ibcon#about to read 3, iclass 11, count 2 2006.280.08:06:54.68#ibcon#read 3, iclass 11, count 2 2006.280.08:06:54.68#ibcon#about to read 4, iclass 11, count 2 2006.280.08:06:54.68#ibcon#read 4, iclass 11, count 2 2006.280.08:06:54.68#ibcon#about to read 5, iclass 11, count 2 2006.280.08:06:54.68#ibcon#read 5, iclass 11, count 2 2006.280.08:06:54.68#ibcon#about to read 6, iclass 11, count 2 2006.280.08:06:54.68#ibcon#read 6, iclass 11, count 2 2006.280.08:06:54.68#ibcon#end of sib2, iclass 11, count 2 2006.280.08:06:54.68#ibcon#*mode == 0, iclass 11, count 2 2006.280.08:06:54.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.08:06:54.68#ibcon#[27=AT03-04\r\n] 2006.280.08:06:54.68#ibcon#*before write, iclass 11, count 2 2006.280.08:06:54.68#ibcon#enter sib2, iclass 11, count 2 2006.280.08:06:54.68#ibcon#flushed, iclass 11, count 2 2006.280.08:06:54.68#ibcon#about to write, iclass 11, count 2 2006.280.08:06:54.68#ibcon#wrote, iclass 11, count 2 2006.280.08:06:54.68#ibcon#about to read 3, iclass 11, count 2 2006.280.08:06:54.71#ibcon#read 3, iclass 11, count 2 2006.280.08:06:54.71#ibcon#about to read 4, iclass 11, count 2 2006.280.08:06:54.71#ibcon#read 4, iclass 11, count 2 2006.280.08:06:54.71#ibcon#about to read 5, iclass 11, count 2 2006.280.08:06:54.71#ibcon#read 5, iclass 11, count 2 2006.280.08:06:54.71#ibcon#about to read 6, iclass 11, count 2 2006.280.08:06:54.71#ibcon#read 6, iclass 11, count 2 2006.280.08:06:54.71#ibcon#end of sib2, iclass 11, count 2 2006.280.08:06:54.71#ibcon#*after write, iclass 11, count 2 2006.280.08:06:54.71#ibcon#*before return 0, iclass 11, count 2 2006.280.08:06:54.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:54.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:06:54.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.08:06:54.71#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:54.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:54.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:54.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:54.83#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:06:54.83#ibcon#first serial, iclass 11, count 0 2006.280.08:06:54.83#ibcon#enter sib2, iclass 11, count 0 2006.280.08:06:54.83#ibcon#flushed, iclass 11, count 0 2006.280.08:06:54.83#ibcon#about to write, iclass 11, count 0 2006.280.08:06:54.83#ibcon#wrote, iclass 11, count 0 2006.280.08:06:54.83#ibcon#about to read 3, iclass 11, count 0 2006.280.08:06:54.85#ibcon#read 3, iclass 11, count 0 2006.280.08:06:54.85#ibcon#about to read 4, iclass 11, count 0 2006.280.08:06:54.85#ibcon#read 4, iclass 11, count 0 2006.280.08:06:54.85#ibcon#about to read 5, iclass 11, count 0 2006.280.08:06:54.85#ibcon#read 5, iclass 11, count 0 2006.280.08:06:54.85#ibcon#about to read 6, iclass 11, count 0 2006.280.08:06:54.85#ibcon#read 6, iclass 11, count 0 2006.280.08:06:54.85#ibcon#end of sib2, iclass 11, count 0 2006.280.08:06:54.85#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:06:54.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:06:54.85#ibcon#[27=USB\r\n] 2006.280.08:06:54.85#ibcon#*before write, iclass 11, count 0 2006.280.08:06:54.85#ibcon#enter sib2, iclass 11, count 0 2006.280.08:06:54.85#ibcon#flushed, iclass 11, count 0 2006.280.08:06:54.85#ibcon#about to write, iclass 11, count 0 2006.280.08:06:54.85#ibcon#wrote, iclass 11, count 0 2006.280.08:06:54.85#ibcon#about to read 3, iclass 11, count 0 2006.280.08:06:54.88#ibcon#read 3, iclass 11, count 0 2006.280.08:06:54.88#ibcon#about to read 4, iclass 11, count 0 2006.280.08:06:54.88#ibcon#read 4, iclass 11, count 0 2006.280.08:06:54.88#ibcon#about to read 5, iclass 11, count 0 2006.280.08:06:54.88#ibcon#read 5, iclass 11, count 0 2006.280.08:06:54.88#ibcon#about to read 6, iclass 11, count 0 2006.280.08:06:54.88#ibcon#read 6, iclass 11, count 0 2006.280.08:06:54.88#ibcon#end of sib2, iclass 11, count 0 2006.280.08:06:54.88#ibcon#*after write, iclass 11, count 0 2006.280.08:06:54.88#ibcon#*before return 0, iclass 11, count 0 2006.280.08:06:54.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:54.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:06:54.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:06:54.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:06:54.88$vc4f8/vblo=4,712.99 2006.280.08:06:54.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.08:06:54.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.08:06:54.88#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:54.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:54.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:54.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:54.88#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:06:54.88#ibcon#first serial, iclass 13, count 0 2006.280.08:06:54.88#ibcon#enter sib2, iclass 13, count 0 2006.280.08:06:54.88#ibcon#flushed, iclass 13, count 0 2006.280.08:06:54.88#ibcon#about to write, iclass 13, count 0 2006.280.08:06:54.88#ibcon#wrote, iclass 13, count 0 2006.280.08:06:54.88#ibcon#about to read 3, iclass 13, count 0 2006.280.08:06:54.90#ibcon#read 3, iclass 13, count 0 2006.280.08:06:54.90#ibcon#about to read 4, iclass 13, count 0 2006.280.08:06:54.90#ibcon#read 4, iclass 13, count 0 2006.280.08:06:54.90#ibcon#about to read 5, iclass 13, count 0 2006.280.08:06:54.90#ibcon#read 5, iclass 13, count 0 2006.280.08:06:54.90#ibcon#about to read 6, iclass 13, count 0 2006.280.08:06:54.90#ibcon#read 6, iclass 13, count 0 2006.280.08:06:54.90#ibcon#end of sib2, iclass 13, count 0 2006.280.08:06:54.90#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:06:54.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:06:54.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:06:54.90#ibcon#*before write, iclass 13, count 0 2006.280.08:06:54.90#ibcon#enter sib2, iclass 13, count 0 2006.280.08:06:54.90#ibcon#flushed, iclass 13, count 0 2006.280.08:06:54.90#ibcon#about to write, iclass 13, count 0 2006.280.08:06:54.90#ibcon#wrote, iclass 13, count 0 2006.280.08:06:54.90#ibcon#about to read 3, iclass 13, count 0 2006.280.08:06:54.94#ibcon#read 3, iclass 13, count 0 2006.280.08:06:54.94#ibcon#about to read 4, iclass 13, count 0 2006.280.08:06:54.94#ibcon#read 4, iclass 13, count 0 2006.280.08:06:54.94#ibcon#about to read 5, iclass 13, count 0 2006.280.08:06:54.94#ibcon#read 5, iclass 13, count 0 2006.280.08:06:54.94#ibcon#about to read 6, iclass 13, count 0 2006.280.08:06:54.94#ibcon#read 6, iclass 13, count 0 2006.280.08:06:54.94#ibcon#end of sib2, iclass 13, count 0 2006.280.08:06:54.94#ibcon#*after write, iclass 13, count 0 2006.280.08:06:54.94#ibcon#*before return 0, iclass 13, count 0 2006.280.08:06:54.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:54.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:06:54.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:06:54.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:06:54.94$vc4f8/vb=4,4 2006.280.08:06:54.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.08:06:54.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.08:06:54.94#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:54.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:55.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:55.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:55.00#ibcon#enter wrdev, iclass 15, count 2 2006.280.08:06:55.00#ibcon#first serial, iclass 15, count 2 2006.280.08:06:55.00#ibcon#enter sib2, iclass 15, count 2 2006.280.08:06:55.00#ibcon#flushed, iclass 15, count 2 2006.280.08:06:55.00#ibcon#about to write, iclass 15, count 2 2006.280.08:06:55.00#ibcon#wrote, iclass 15, count 2 2006.280.08:06:55.00#ibcon#about to read 3, iclass 15, count 2 2006.280.08:06:55.02#ibcon#read 3, iclass 15, count 2 2006.280.08:06:55.02#ibcon#about to read 4, iclass 15, count 2 2006.280.08:06:55.02#ibcon#read 4, iclass 15, count 2 2006.280.08:06:55.02#ibcon#about to read 5, iclass 15, count 2 2006.280.08:06:55.02#ibcon#read 5, iclass 15, count 2 2006.280.08:06:55.02#ibcon#about to read 6, iclass 15, count 2 2006.280.08:06:55.02#ibcon#read 6, iclass 15, count 2 2006.280.08:06:55.02#ibcon#end of sib2, iclass 15, count 2 2006.280.08:06:55.02#ibcon#*mode == 0, iclass 15, count 2 2006.280.08:06:55.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.08:06:55.02#ibcon#[27=AT04-04\r\n] 2006.280.08:06:55.02#ibcon#*before write, iclass 15, count 2 2006.280.08:06:55.02#ibcon#enter sib2, iclass 15, count 2 2006.280.08:06:55.02#ibcon#flushed, iclass 15, count 2 2006.280.08:06:55.02#ibcon#about to write, iclass 15, count 2 2006.280.08:06:55.02#ibcon#wrote, iclass 15, count 2 2006.280.08:06:55.02#ibcon#about to read 3, iclass 15, count 2 2006.280.08:06:55.05#ibcon#read 3, iclass 15, count 2 2006.280.08:06:55.05#ibcon#about to read 4, iclass 15, count 2 2006.280.08:06:55.05#ibcon#read 4, iclass 15, count 2 2006.280.08:06:55.05#ibcon#about to read 5, iclass 15, count 2 2006.280.08:06:55.05#ibcon#read 5, iclass 15, count 2 2006.280.08:06:55.05#ibcon#about to read 6, iclass 15, count 2 2006.280.08:06:55.05#ibcon#read 6, iclass 15, count 2 2006.280.08:06:55.05#ibcon#end of sib2, iclass 15, count 2 2006.280.08:06:55.05#ibcon#*after write, iclass 15, count 2 2006.280.08:06:55.05#ibcon#*before return 0, iclass 15, count 2 2006.280.08:06:55.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:55.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:06:55.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.08:06:55.05#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:55.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:55.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:55.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:55.17#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:06:55.17#ibcon#first serial, iclass 15, count 0 2006.280.08:06:55.17#ibcon#enter sib2, iclass 15, count 0 2006.280.08:06:55.17#ibcon#flushed, iclass 15, count 0 2006.280.08:06:55.17#ibcon#about to write, iclass 15, count 0 2006.280.08:06:55.17#ibcon#wrote, iclass 15, count 0 2006.280.08:06:55.17#ibcon#about to read 3, iclass 15, count 0 2006.280.08:06:55.19#ibcon#read 3, iclass 15, count 0 2006.280.08:06:55.19#ibcon#about to read 4, iclass 15, count 0 2006.280.08:06:55.19#ibcon#read 4, iclass 15, count 0 2006.280.08:06:55.19#ibcon#about to read 5, iclass 15, count 0 2006.280.08:06:55.19#ibcon#read 5, iclass 15, count 0 2006.280.08:06:55.19#ibcon#about to read 6, iclass 15, count 0 2006.280.08:06:55.19#ibcon#read 6, iclass 15, count 0 2006.280.08:06:55.19#ibcon#end of sib2, iclass 15, count 0 2006.280.08:06:55.19#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:06:55.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:06:55.19#ibcon#[27=USB\r\n] 2006.280.08:06:55.19#ibcon#*before write, iclass 15, count 0 2006.280.08:06:55.19#ibcon#enter sib2, iclass 15, count 0 2006.280.08:06:55.19#ibcon#flushed, iclass 15, count 0 2006.280.08:06:55.19#ibcon#about to write, iclass 15, count 0 2006.280.08:06:55.19#ibcon#wrote, iclass 15, count 0 2006.280.08:06:55.19#ibcon#about to read 3, iclass 15, count 0 2006.280.08:06:55.22#ibcon#read 3, iclass 15, count 0 2006.280.08:06:55.22#ibcon#about to read 4, iclass 15, count 0 2006.280.08:06:55.22#ibcon#read 4, iclass 15, count 0 2006.280.08:06:55.22#ibcon#about to read 5, iclass 15, count 0 2006.280.08:06:55.22#ibcon#read 5, iclass 15, count 0 2006.280.08:06:55.22#ibcon#about to read 6, iclass 15, count 0 2006.280.08:06:55.22#ibcon#read 6, iclass 15, count 0 2006.280.08:06:55.22#ibcon#end of sib2, iclass 15, count 0 2006.280.08:06:55.22#ibcon#*after write, iclass 15, count 0 2006.280.08:06:55.22#ibcon#*before return 0, iclass 15, count 0 2006.280.08:06:55.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:55.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:06:55.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:06:55.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:06:55.22$vc4f8/vblo=5,744.99 2006.280.08:06:55.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.08:06:55.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.08:06:55.22#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:55.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:55.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:55.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:55.22#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:06:55.22#ibcon#first serial, iclass 17, count 0 2006.280.08:06:55.22#ibcon#enter sib2, iclass 17, count 0 2006.280.08:06:55.22#ibcon#flushed, iclass 17, count 0 2006.280.08:06:55.22#ibcon#about to write, iclass 17, count 0 2006.280.08:06:55.22#ibcon#wrote, iclass 17, count 0 2006.280.08:06:55.22#ibcon#about to read 3, iclass 17, count 0 2006.280.08:06:55.24#ibcon#read 3, iclass 17, count 0 2006.280.08:06:55.24#ibcon#about to read 4, iclass 17, count 0 2006.280.08:06:55.24#ibcon#read 4, iclass 17, count 0 2006.280.08:06:55.24#ibcon#about to read 5, iclass 17, count 0 2006.280.08:06:55.24#ibcon#read 5, iclass 17, count 0 2006.280.08:06:55.24#ibcon#about to read 6, iclass 17, count 0 2006.280.08:06:55.24#ibcon#read 6, iclass 17, count 0 2006.280.08:06:55.24#ibcon#end of sib2, iclass 17, count 0 2006.280.08:06:55.24#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:06:55.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:06:55.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:06:55.24#ibcon#*before write, iclass 17, count 0 2006.280.08:06:55.24#ibcon#enter sib2, iclass 17, count 0 2006.280.08:06:55.24#ibcon#flushed, iclass 17, count 0 2006.280.08:06:55.24#ibcon#about to write, iclass 17, count 0 2006.280.08:06:55.24#ibcon#wrote, iclass 17, count 0 2006.280.08:06:55.24#ibcon#about to read 3, iclass 17, count 0 2006.280.08:06:55.28#ibcon#read 3, iclass 17, count 0 2006.280.08:06:55.28#ibcon#about to read 4, iclass 17, count 0 2006.280.08:06:55.28#ibcon#read 4, iclass 17, count 0 2006.280.08:06:55.28#ibcon#about to read 5, iclass 17, count 0 2006.280.08:06:55.28#ibcon#read 5, iclass 17, count 0 2006.280.08:06:55.28#ibcon#about to read 6, iclass 17, count 0 2006.280.08:06:55.28#ibcon#read 6, iclass 17, count 0 2006.280.08:06:55.28#ibcon#end of sib2, iclass 17, count 0 2006.280.08:06:55.28#ibcon#*after write, iclass 17, count 0 2006.280.08:06:55.28#ibcon#*before return 0, iclass 17, count 0 2006.280.08:06:55.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:55.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:06:55.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:06:55.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:06:55.28$vc4f8/vb=5,4 2006.280.08:06:55.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.08:06:55.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.08:06:55.28#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:55.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:55.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:55.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:55.34#ibcon#enter wrdev, iclass 19, count 2 2006.280.08:06:55.34#ibcon#first serial, iclass 19, count 2 2006.280.08:06:55.34#ibcon#enter sib2, iclass 19, count 2 2006.280.08:06:55.34#ibcon#flushed, iclass 19, count 2 2006.280.08:06:55.34#ibcon#about to write, iclass 19, count 2 2006.280.08:06:55.34#ibcon#wrote, iclass 19, count 2 2006.280.08:06:55.34#ibcon#about to read 3, iclass 19, count 2 2006.280.08:06:55.36#ibcon#read 3, iclass 19, count 2 2006.280.08:06:55.36#ibcon#about to read 4, iclass 19, count 2 2006.280.08:06:55.36#ibcon#read 4, iclass 19, count 2 2006.280.08:06:55.36#ibcon#about to read 5, iclass 19, count 2 2006.280.08:06:55.36#ibcon#read 5, iclass 19, count 2 2006.280.08:06:55.36#ibcon#about to read 6, iclass 19, count 2 2006.280.08:06:55.36#ibcon#read 6, iclass 19, count 2 2006.280.08:06:55.36#ibcon#end of sib2, iclass 19, count 2 2006.280.08:06:55.36#ibcon#*mode == 0, iclass 19, count 2 2006.280.08:06:55.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.08:06:55.36#ibcon#[27=AT05-04\r\n] 2006.280.08:06:55.36#ibcon#*before write, iclass 19, count 2 2006.280.08:06:55.36#ibcon#enter sib2, iclass 19, count 2 2006.280.08:06:55.36#ibcon#flushed, iclass 19, count 2 2006.280.08:06:55.36#ibcon#about to write, iclass 19, count 2 2006.280.08:06:55.36#ibcon#wrote, iclass 19, count 2 2006.280.08:06:55.36#ibcon#about to read 3, iclass 19, count 2 2006.280.08:06:55.39#ibcon#read 3, iclass 19, count 2 2006.280.08:06:55.39#ibcon#about to read 4, iclass 19, count 2 2006.280.08:06:55.39#ibcon#read 4, iclass 19, count 2 2006.280.08:06:55.39#ibcon#about to read 5, iclass 19, count 2 2006.280.08:06:55.39#ibcon#read 5, iclass 19, count 2 2006.280.08:06:55.39#ibcon#about to read 6, iclass 19, count 2 2006.280.08:06:55.39#ibcon#read 6, iclass 19, count 2 2006.280.08:06:55.39#ibcon#end of sib2, iclass 19, count 2 2006.280.08:06:55.39#ibcon#*after write, iclass 19, count 2 2006.280.08:06:55.39#ibcon#*before return 0, iclass 19, count 2 2006.280.08:06:55.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:55.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:06:55.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.08:06:55.39#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:55.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:55.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:55.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:55.51#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:06:55.51#ibcon#first serial, iclass 19, count 0 2006.280.08:06:55.51#ibcon#enter sib2, iclass 19, count 0 2006.280.08:06:55.51#ibcon#flushed, iclass 19, count 0 2006.280.08:06:55.51#ibcon#about to write, iclass 19, count 0 2006.280.08:06:55.51#ibcon#wrote, iclass 19, count 0 2006.280.08:06:55.51#ibcon#about to read 3, iclass 19, count 0 2006.280.08:06:55.53#ibcon#read 3, iclass 19, count 0 2006.280.08:06:55.53#ibcon#about to read 4, iclass 19, count 0 2006.280.08:06:55.53#ibcon#read 4, iclass 19, count 0 2006.280.08:06:55.53#ibcon#about to read 5, iclass 19, count 0 2006.280.08:06:55.53#ibcon#read 5, iclass 19, count 0 2006.280.08:06:55.53#ibcon#about to read 6, iclass 19, count 0 2006.280.08:06:55.53#ibcon#read 6, iclass 19, count 0 2006.280.08:06:55.53#ibcon#end of sib2, iclass 19, count 0 2006.280.08:06:55.53#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:06:55.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:06:55.53#ibcon#[27=USB\r\n] 2006.280.08:06:55.53#ibcon#*before write, iclass 19, count 0 2006.280.08:06:55.53#ibcon#enter sib2, iclass 19, count 0 2006.280.08:06:55.53#ibcon#flushed, iclass 19, count 0 2006.280.08:06:55.53#ibcon#about to write, iclass 19, count 0 2006.280.08:06:55.53#ibcon#wrote, iclass 19, count 0 2006.280.08:06:55.53#ibcon#about to read 3, iclass 19, count 0 2006.280.08:06:55.56#abcon#<5=/14 1.5 3.4 20.64 62 987.4\r\n> 2006.280.08:06:55.56#ibcon#read 3, iclass 19, count 0 2006.280.08:06:55.56#ibcon#about to read 4, iclass 19, count 0 2006.280.08:06:55.56#ibcon#read 4, iclass 19, count 0 2006.280.08:06:55.56#ibcon#about to read 5, iclass 19, count 0 2006.280.08:06:55.56#ibcon#read 5, iclass 19, count 0 2006.280.08:06:55.56#ibcon#about to read 6, iclass 19, count 0 2006.280.08:06:55.56#ibcon#read 6, iclass 19, count 0 2006.280.08:06:55.56#ibcon#end of sib2, iclass 19, count 0 2006.280.08:06:55.56#ibcon#*after write, iclass 19, count 0 2006.280.08:06:55.56#ibcon#*before return 0, iclass 19, count 0 2006.280.08:06:55.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:55.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:06:55.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:06:55.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:06:55.56$vc4f8/vblo=6,752.99 2006.280.08:06:55.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:06:55.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:06:55.56#ibcon#ireg 17 cls_cnt 0 2006.280.08:06:55.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:06:55.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:06:55.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:06:55.56#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:06:55.56#ibcon#first serial, iclass 24, count 0 2006.280.08:06:55.56#ibcon#enter sib2, iclass 24, count 0 2006.280.08:06:55.56#ibcon#flushed, iclass 24, count 0 2006.280.08:06:55.56#ibcon#about to write, iclass 24, count 0 2006.280.08:06:55.56#ibcon#wrote, iclass 24, count 0 2006.280.08:06:55.56#ibcon#about to read 3, iclass 24, count 0 2006.280.08:06:55.58#abcon#{5=INTERFACE CLEAR} 2006.280.08:06:55.58#ibcon#read 3, iclass 24, count 0 2006.280.08:06:55.58#ibcon#about to read 4, iclass 24, count 0 2006.280.08:06:55.58#ibcon#read 4, iclass 24, count 0 2006.280.08:06:55.58#ibcon#about to read 5, iclass 24, count 0 2006.280.08:06:55.58#ibcon#read 5, iclass 24, count 0 2006.280.08:06:55.58#ibcon#about to read 6, iclass 24, count 0 2006.280.08:06:55.58#ibcon#read 6, iclass 24, count 0 2006.280.08:06:55.58#ibcon#end of sib2, iclass 24, count 0 2006.280.08:06:55.58#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:06:55.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:06:55.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:06:55.58#ibcon#*before write, iclass 24, count 0 2006.280.08:06:55.58#ibcon#enter sib2, iclass 24, count 0 2006.280.08:06:55.58#ibcon#flushed, iclass 24, count 0 2006.280.08:06:55.58#ibcon#about to write, iclass 24, count 0 2006.280.08:06:55.58#ibcon#wrote, iclass 24, count 0 2006.280.08:06:55.58#ibcon#about to read 3, iclass 24, count 0 2006.280.08:06:55.62#ibcon#read 3, iclass 24, count 0 2006.280.08:06:55.62#ibcon#about to read 4, iclass 24, count 0 2006.280.08:06:55.62#ibcon#read 4, iclass 24, count 0 2006.280.08:06:55.62#ibcon#about to read 5, iclass 24, count 0 2006.280.08:06:55.62#ibcon#read 5, iclass 24, count 0 2006.280.08:06:55.62#ibcon#about to read 6, iclass 24, count 0 2006.280.08:06:55.62#ibcon#read 6, iclass 24, count 0 2006.280.08:06:55.62#ibcon#end of sib2, iclass 24, count 0 2006.280.08:06:55.62#ibcon#*after write, iclass 24, count 0 2006.280.08:06:55.62#ibcon#*before return 0, iclass 24, count 0 2006.280.08:06:55.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:06:55.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:06:55.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:06:55.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:06:55.62$vc4f8/vb=6,4 2006.280.08:06:55.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:06:55.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:06:55.64#ibcon#ireg 11 cls_cnt 2 2006.280.08:06:55.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:06:55.66#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:06:55.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:06:55.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:06:55.68#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:06:55.68#ibcon#first serial, iclass 26, count 2 2006.280.08:06:55.68#ibcon#enter sib2, iclass 26, count 2 2006.280.08:06:55.68#ibcon#flushed, iclass 26, count 2 2006.280.08:06:55.68#ibcon#about to write, iclass 26, count 2 2006.280.08:06:55.68#ibcon#wrote, iclass 26, count 2 2006.280.08:06:55.68#ibcon#about to read 3, iclass 26, count 2 2006.280.08:06:55.70#ibcon#read 3, iclass 26, count 2 2006.280.08:06:55.70#ibcon#about to read 4, iclass 26, count 2 2006.280.08:06:55.70#ibcon#read 4, iclass 26, count 2 2006.280.08:06:55.70#ibcon#about to read 5, iclass 26, count 2 2006.280.08:06:55.70#ibcon#read 5, iclass 26, count 2 2006.280.08:06:55.70#ibcon#about to read 6, iclass 26, count 2 2006.280.08:06:55.70#ibcon#read 6, iclass 26, count 2 2006.280.08:06:55.70#ibcon#end of sib2, iclass 26, count 2 2006.280.08:06:55.70#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:06:55.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:06:55.70#ibcon#[27=AT06-04\r\n] 2006.280.08:06:55.70#ibcon#*before write, iclass 26, count 2 2006.280.08:06:55.70#ibcon#enter sib2, iclass 26, count 2 2006.280.08:06:55.70#ibcon#flushed, iclass 26, count 2 2006.280.08:06:55.70#ibcon#about to write, iclass 26, count 2 2006.280.08:06:55.70#ibcon#wrote, iclass 26, count 2 2006.280.08:06:55.70#ibcon#about to read 3, iclass 26, count 2 2006.280.08:06:55.74#ibcon#read 3, iclass 26, count 2 2006.280.08:06:55.74#ibcon#about to read 4, iclass 26, count 2 2006.280.08:06:55.74#ibcon#read 4, iclass 26, count 2 2006.280.08:06:55.74#ibcon#about to read 5, iclass 26, count 2 2006.280.08:06:55.74#ibcon#read 5, iclass 26, count 2 2006.280.08:06:55.74#ibcon#about to read 6, iclass 26, count 2 2006.280.08:06:55.74#ibcon#read 6, iclass 26, count 2 2006.280.08:06:55.74#ibcon#end of sib2, iclass 26, count 2 2006.280.08:06:55.74#ibcon#*after write, iclass 26, count 2 2006.280.08:06:55.74#ibcon#*before return 0, iclass 26, count 2 2006.280.08:06:55.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:06:55.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:06:55.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:06:55.74#ibcon#ireg 7 cls_cnt 0 2006.280.08:06:55.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:06:55.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:06:55.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:06:55.86#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:06:55.86#ibcon#first serial, iclass 26, count 0 2006.280.08:06:55.86#ibcon#enter sib2, iclass 26, count 0 2006.280.08:06:55.86#ibcon#flushed, iclass 26, count 0 2006.280.08:06:55.86#ibcon#about to write, iclass 26, count 0 2006.280.08:06:55.86#ibcon#wrote, iclass 26, count 0 2006.280.08:06:55.86#ibcon#about to read 3, iclass 26, count 0 2006.280.08:06:55.88#ibcon#read 3, iclass 26, count 0 2006.280.08:06:55.88#ibcon#about to read 4, iclass 26, count 0 2006.280.08:06:55.88#ibcon#read 4, iclass 26, count 0 2006.280.08:06:55.88#ibcon#about to read 5, iclass 26, count 0 2006.280.08:06:55.88#ibcon#read 5, iclass 26, count 0 2006.280.08:06:55.88#ibcon#about to read 6, iclass 26, count 0 2006.280.08:06:55.88#ibcon#read 6, iclass 26, count 0 2006.280.08:06:55.88#ibcon#end of sib2, iclass 26, count 0 2006.280.08:06:55.88#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:06:55.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:06:55.88#ibcon#[27=USB\r\n] 2006.280.08:06:55.88#ibcon#*before write, iclass 26, count 0 2006.280.08:06:55.88#ibcon#enter sib2, iclass 26, count 0 2006.280.08:06:55.88#ibcon#flushed, iclass 26, count 0 2006.280.08:06:55.88#ibcon#about to write, iclass 26, count 0 2006.280.08:06:55.88#ibcon#wrote, iclass 26, count 0 2006.280.08:06:55.88#ibcon#about to read 3, iclass 26, count 0 2006.280.08:06:55.91#ibcon#read 3, iclass 26, count 0 2006.280.08:06:55.91#ibcon#about to read 4, iclass 26, count 0 2006.280.08:06:55.91#ibcon#read 4, iclass 26, count 0 2006.280.08:06:55.91#ibcon#about to read 5, iclass 26, count 0 2006.280.08:06:55.91#ibcon#read 5, iclass 26, count 0 2006.280.08:06:55.91#ibcon#about to read 6, iclass 26, count 0 2006.280.08:06:55.91#ibcon#read 6, iclass 26, count 0 2006.280.08:06:55.91#ibcon#end of sib2, iclass 26, count 0 2006.280.08:06:55.91#ibcon#*after write, iclass 26, count 0 2006.280.08:06:55.91#ibcon#*before return 0, iclass 26, count 0 2006.280.08:06:55.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:06:55.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:06:55.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:06:55.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:06:55.91$vc4f8/vabw=wide 2006.280.08:06:55.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.08:06:55.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.08:06:55.91#ibcon#ireg 8 cls_cnt 0 2006.280.08:06:55.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:55.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:55.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:55.91#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:06:55.91#ibcon#first serial, iclass 29, count 0 2006.280.08:06:55.91#ibcon#enter sib2, iclass 29, count 0 2006.280.08:06:55.91#ibcon#flushed, iclass 29, count 0 2006.280.08:06:55.91#ibcon#about to write, iclass 29, count 0 2006.280.08:06:55.91#ibcon#wrote, iclass 29, count 0 2006.280.08:06:55.91#ibcon#about to read 3, iclass 29, count 0 2006.280.08:06:55.93#ibcon#read 3, iclass 29, count 0 2006.280.08:06:55.93#ibcon#about to read 4, iclass 29, count 0 2006.280.08:06:55.93#ibcon#read 4, iclass 29, count 0 2006.280.08:06:55.93#ibcon#about to read 5, iclass 29, count 0 2006.280.08:06:55.93#ibcon#read 5, iclass 29, count 0 2006.280.08:06:55.93#ibcon#about to read 6, iclass 29, count 0 2006.280.08:06:55.93#ibcon#read 6, iclass 29, count 0 2006.280.08:06:55.93#ibcon#end of sib2, iclass 29, count 0 2006.280.08:06:55.93#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:06:55.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:06:55.93#ibcon#[25=BW32\r\n] 2006.280.08:06:55.96#ibcon#*before write, iclass 29, count 0 2006.280.08:06:55.96#ibcon#enter sib2, iclass 29, count 0 2006.280.08:06:55.96#ibcon#flushed, iclass 29, count 0 2006.280.08:06:55.96#ibcon#about to write, iclass 29, count 0 2006.280.08:06:55.96#ibcon#wrote, iclass 29, count 0 2006.280.08:06:55.96#ibcon#about to read 3, iclass 29, count 0 2006.280.08:06:55.99#ibcon#read 3, iclass 29, count 0 2006.280.08:06:55.99#ibcon#about to read 4, iclass 29, count 0 2006.280.08:06:55.99#ibcon#read 4, iclass 29, count 0 2006.280.08:06:55.99#ibcon#about to read 5, iclass 29, count 0 2006.280.08:06:55.99#ibcon#read 5, iclass 29, count 0 2006.280.08:06:55.99#ibcon#about to read 6, iclass 29, count 0 2006.280.08:06:55.99#ibcon#read 6, iclass 29, count 0 2006.280.08:06:55.99#ibcon#end of sib2, iclass 29, count 0 2006.280.08:06:55.99#ibcon#*after write, iclass 29, count 0 2006.280.08:06:55.99#ibcon#*before return 0, iclass 29, count 0 2006.280.08:06:55.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:55.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:06:55.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:06:55.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:06:55.99$vc4f8/vbbw=wide 2006.280.08:06:55.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.08:06:55.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.08:06:55.99#ibcon#ireg 8 cls_cnt 0 2006.280.08:06:55.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:06:56.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:06:56.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:06:56.03#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:06:56.03#ibcon#first serial, iclass 31, count 0 2006.280.08:06:56.03#ibcon#enter sib2, iclass 31, count 0 2006.280.08:06:56.03#ibcon#flushed, iclass 31, count 0 2006.280.08:06:56.03#ibcon#about to write, iclass 31, count 0 2006.280.08:06:56.03#ibcon#wrote, iclass 31, count 0 2006.280.08:06:56.03#ibcon#about to read 3, iclass 31, count 0 2006.280.08:06:56.05#ibcon#read 3, iclass 31, count 0 2006.280.08:06:56.05#ibcon#about to read 4, iclass 31, count 0 2006.280.08:06:56.05#ibcon#read 4, iclass 31, count 0 2006.280.08:06:56.05#ibcon#about to read 5, iclass 31, count 0 2006.280.08:06:56.05#ibcon#read 5, iclass 31, count 0 2006.280.08:06:56.05#ibcon#about to read 6, iclass 31, count 0 2006.280.08:06:56.05#ibcon#read 6, iclass 31, count 0 2006.280.08:06:56.05#ibcon#end of sib2, iclass 31, count 0 2006.280.08:06:56.05#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:06:56.05#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:06:56.05#ibcon#[27=BW32\r\n] 2006.280.08:06:56.05#ibcon#*before write, iclass 31, count 0 2006.280.08:06:56.05#ibcon#enter sib2, iclass 31, count 0 2006.280.08:06:56.05#ibcon#flushed, iclass 31, count 0 2006.280.08:06:56.05#ibcon#about to write, iclass 31, count 0 2006.280.08:06:56.05#ibcon#wrote, iclass 31, count 0 2006.280.08:06:56.05#ibcon#about to read 3, iclass 31, count 0 2006.280.08:06:56.08#ibcon#read 3, iclass 31, count 0 2006.280.08:06:56.08#ibcon#about to read 4, iclass 31, count 0 2006.280.08:06:56.08#ibcon#read 4, iclass 31, count 0 2006.280.08:06:56.08#ibcon#about to read 5, iclass 31, count 0 2006.280.08:06:56.08#ibcon#read 5, iclass 31, count 0 2006.280.08:06:56.08#ibcon#about to read 6, iclass 31, count 0 2006.280.08:06:56.08#ibcon#read 6, iclass 31, count 0 2006.280.08:06:56.08#ibcon#end of sib2, iclass 31, count 0 2006.280.08:06:56.08#ibcon#*after write, iclass 31, count 0 2006.280.08:06:56.08#ibcon#*before return 0, iclass 31, count 0 2006.280.08:06:56.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:06:56.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:06:56.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:06:56.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:06:56.08$4f8m12a/ifd4f 2006.280.08:06:56.08$ifd4f/lo= 2006.280.08:06:56.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:06:56.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:06:56.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:06:56.08$ifd4f/patch= 2006.280.08:06:56.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:06:56.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:06:56.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:06:56.08$4f8m12a/"form=m,16.000,1:2 2006.280.08:06:56.08$4f8m12a/"tpicd 2006.280.08:06:56.08$4f8m12a/echo=off 2006.280.08:06:56.08$4f8m12a/xlog=off 2006.280.08:06:56.08:!2006.280.08:07:30 2006.280.08:07:13.14#trakl#Source acquired 2006.280.08:07:14.14#flagr#flagr/antenna,acquired 2006.280.08:07:30.00:preob 2006.280.08:07:30.14/onsource/TRACKING 2006.280.08:07:30.14:!2006.280.08:07:40 2006.280.08:07:40.00:data_valid=on 2006.280.08:07:40.00:midob 2006.280.08:07:41.14/onsource/TRACKING 2006.280.08:07:41.14/wx/20.61,987.4,62 2006.280.08:07:41.24/cable/+6.4839E-03 2006.280.08:07:42.33/va/01,07,usb,yes,34,35 2006.280.08:07:42.33/va/02,06,usb,yes,31,33 2006.280.08:07:42.33/va/03,06,usb,yes,29,29 2006.280.08:07:42.33/va/04,06,usb,yes,32,35 2006.280.08:07:42.33/va/05,07,usb,yes,30,32 2006.280.08:07:42.33/va/06,06,usb,yes,29,29 2006.280.08:07:42.33/va/07,06,usb,yes,30,29 2006.280.08:07:42.33/va/08,06,usb,yes,32,31 2006.280.08:07:42.56/valo/01,532.99,yes,locked 2006.280.08:07:42.56/valo/02,572.99,yes,locked 2006.280.08:07:42.56/valo/03,672.99,yes,locked 2006.280.08:07:42.56/valo/04,832.99,yes,locked 2006.280.08:07:42.56/valo/05,652.99,yes,locked 2006.280.08:07:42.56/valo/06,772.99,yes,locked 2006.280.08:07:42.56/valo/07,832.99,yes,locked 2006.280.08:07:42.56/valo/08,852.99,yes,locked 2006.280.08:07:43.65/vb/01,04,usb,yes,30,29 2006.280.08:07:43.65/vb/02,05,usb,yes,28,29 2006.280.08:07:43.65/vb/03,04,usb,yes,28,32 2006.280.08:07:43.65/vb/04,04,usb,yes,29,29 2006.280.08:07:43.65/vb/05,04,usb,yes,27,31 2006.280.08:07:43.65/vb/06,04,usb,yes,28,31 2006.280.08:07:43.65/vb/07,04,usb,yes,30,30 2006.280.08:07:43.65/vb/08,04,usb,yes,28,31 2006.280.08:07:43.88/vblo/01,632.99,yes,locked 2006.280.08:07:43.88/vblo/02,640.99,yes,locked 2006.280.08:07:43.88/vblo/03,656.99,yes,locked 2006.280.08:07:43.88/vblo/04,712.99,yes,locked 2006.280.08:07:43.88/vblo/05,744.99,yes,locked 2006.280.08:07:43.88/vblo/06,752.99,yes,locked 2006.280.08:07:43.88/vblo/07,734.99,yes,locked 2006.280.08:07:43.88/vblo/08,744.99,yes,locked 2006.280.08:07:44.03/vabw/8 2006.280.08:07:44.18/vbbw/8 2006.280.08:07:44.27/xfe/off,on,12.2 2006.280.08:07:44.66/ifatt/23,28,28,28 2006.280.08:07:45.08/fmout-gps/S +3.20E-07 2006.280.08:07:45.10:!2006.280.08:08:40 2006.280.08:08:40.01:data_valid=off 2006.280.08:08:40.01:postob 2006.280.08:08:40.19/cable/+6.4833E-03 2006.280.08:08:40.19/wx/20.56,987.4,63 2006.280.08:08:41.08/fmout-gps/S +3.20E-07 2006.280.08:08:41.08:scan_name=280-0809,k06280,60 2006.280.08:08:41.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.280.08:08:41.13#flagr#flagr/antenna,new-source 2006.280.08:08:42.13:checkk5 2006.280.08:08:42.85/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:08:43.31/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:08:43.75/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:08:44.45/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:08:45.11/chk_obsdata//k5ts1/T2800807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:08:45.62/chk_obsdata//k5ts2/T2800807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:08:46.29/chk_obsdata//k5ts3/T2800807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:08:46.75/chk_obsdata//k5ts4/T2800807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:08:47.79/k5log//k5ts1_log_newline 2006.280.08:08:48.95/k5log//k5ts2_log_newline 2006.280.08:08:50.05/k5log//k5ts3_log_newline 2006.280.08:08:51.16/k5log//k5ts4_log_newline 2006.280.08:08:51.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:08:51.23:4f8m12a=2 2006.280.08:08:51.23$4f8m12a/echo=on 2006.280.08:08:51.23$4f8m12a/pcalon 2006.280.08:08:51.23$pcalon/"no phase cal control is implemented here 2006.280.08:08:51.23$4f8m12a/"tpicd=stop 2006.280.08:08:51.23$4f8m12a/vc4f8 2006.280.08:08:51.23$vc4f8/valo=1,532.99 2006.280.08:08:51.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:08:51.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:08:51.23#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:51.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:51.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:51.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:51.23#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:08:51.23#ibcon#first serial, iclass 4, count 0 2006.280.08:08:51.23#ibcon#enter sib2, iclass 4, count 0 2006.280.08:08:51.23#ibcon#flushed, iclass 4, count 0 2006.280.08:08:51.23#ibcon#about to write, iclass 4, count 0 2006.280.08:08:51.23#ibcon#wrote, iclass 4, count 0 2006.280.08:08:51.23#ibcon#about to read 3, iclass 4, count 0 2006.280.08:08:51.25#ibcon#read 3, iclass 4, count 0 2006.280.08:08:51.25#ibcon#about to read 4, iclass 4, count 0 2006.280.08:08:51.25#ibcon#read 4, iclass 4, count 0 2006.280.08:08:51.25#ibcon#about to read 5, iclass 4, count 0 2006.280.08:08:51.25#ibcon#read 5, iclass 4, count 0 2006.280.08:08:51.25#ibcon#about to read 6, iclass 4, count 0 2006.280.08:08:51.25#ibcon#read 6, iclass 4, count 0 2006.280.08:08:51.25#ibcon#end of sib2, iclass 4, count 0 2006.280.08:08:51.25#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:08:51.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:08:51.25#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:08:51.25#ibcon#*before write, iclass 4, count 0 2006.280.08:08:51.25#ibcon#enter sib2, iclass 4, count 0 2006.280.08:08:51.25#ibcon#flushed, iclass 4, count 0 2006.280.08:08:51.25#ibcon#about to write, iclass 4, count 0 2006.280.08:08:51.25#ibcon#wrote, iclass 4, count 0 2006.280.08:08:51.25#ibcon#about to read 3, iclass 4, count 0 2006.280.08:08:51.30#ibcon#read 3, iclass 4, count 0 2006.280.08:08:51.30#ibcon#about to read 4, iclass 4, count 0 2006.280.08:08:51.30#ibcon#read 4, iclass 4, count 0 2006.280.08:08:51.30#ibcon#about to read 5, iclass 4, count 0 2006.280.08:08:51.30#ibcon#read 5, iclass 4, count 0 2006.280.08:08:51.30#ibcon#about to read 6, iclass 4, count 0 2006.280.08:08:51.30#ibcon#read 6, iclass 4, count 0 2006.280.08:08:51.30#ibcon#end of sib2, iclass 4, count 0 2006.280.08:08:51.30#ibcon#*after write, iclass 4, count 0 2006.280.08:08:51.30#ibcon#*before return 0, iclass 4, count 0 2006.280.08:08:51.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:51.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:51.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:08:51.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:08:51.30$vc4f8/va=1,7 2006.280.08:08:51.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:08:51.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:08:51.30#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:51.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:51.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:51.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:51.30#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:08:51.30#ibcon#first serial, iclass 6, count 2 2006.280.08:08:51.30#ibcon#enter sib2, iclass 6, count 2 2006.280.08:08:51.30#ibcon#flushed, iclass 6, count 2 2006.280.08:08:51.30#ibcon#about to write, iclass 6, count 2 2006.280.08:08:51.30#ibcon#wrote, iclass 6, count 2 2006.280.08:08:51.30#ibcon#about to read 3, iclass 6, count 2 2006.280.08:08:51.32#ibcon#read 3, iclass 6, count 2 2006.280.08:08:51.32#ibcon#about to read 4, iclass 6, count 2 2006.280.08:08:51.32#ibcon#read 4, iclass 6, count 2 2006.280.08:08:51.32#ibcon#about to read 5, iclass 6, count 2 2006.280.08:08:51.32#ibcon#read 5, iclass 6, count 2 2006.280.08:08:51.32#ibcon#about to read 6, iclass 6, count 2 2006.280.08:08:51.32#ibcon#read 6, iclass 6, count 2 2006.280.08:08:51.32#ibcon#end of sib2, iclass 6, count 2 2006.280.08:08:51.32#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:08:51.32#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:08:51.32#ibcon#[25=AT01-07\r\n] 2006.280.08:08:51.32#ibcon#*before write, iclass 6, count 2 2006.280.08:08:51.32#ibcon#enter sib2, iclass 6, count 2 2006.280.08:08:51.32#ibcon#flushed, iclass 6, count 2 2006.280.08:08:51.32#ibcon#about to write, iclass 6, count 2 2006.280.08:08:51.32#ibcon#wrote, iclass 6, count 2 2006.280.08:08:51.32#ibcon#about to read 3, iclass 6, count 2 2006.280.08:08:51.35#ibcon#read 3, iclass 6, count 2 2006.280.08:08:51.35#ibcon#about to read 4, iclass 6, count 2 2006.280.08:08:51.35#ibcon#read 4, iclass 6, count 2 2006.280.08:08:51.35#ibcon#about to read 5, iclass 6, count 2 2006.280.08:08:51.35#ibcon#read 5, iclass 6, count 2 2006.280.08:08:51.35#ibcon#about to read 6, iclass 6, count 2 2006.280.08:08:51.35#ibcon#read 6, iclass 6, count 2 2006.280.08:08:51.35#ibcon#end of sib2, iclass 6, count 2 2006.280.08:08:51.35#ibcon#*after write, iclass 6, count 2 2006.280.08:08:51.35#ibcon#*before return 0, iclass 6, count 2 2006.280.08:08:51.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:51.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:51.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:08:51.35#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:51.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:51.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:51.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:51.47#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:08:51.47#ibcon#first serial, iclass 6, count 0 2006.280.08:08:51.47#ibcon#enter sib2, iclass 6, count 0 2006.280.08:08:51.47#ibcon#flushed, iclass 6, count 0 2006.280.08:08:51.47#ibcon#about to write, iclass 6, count 0 2006.280.08:08:51.47#ibcon#wrote, iclass 6, count 0 2006.280.08:08:51.47#ibcon#about to read 3, iclass 6, count 0 2006.280.08:08:51.49#ibcon#read 3, iclass 6, count 0 2006.280.08:08:51.49#ibcon#about to read 4, iclass 6, count 0 2006.280.08:08:51.49#ibcon#read 4, iclass 6, count 0 2006.280.08:08:51.49#ibcon#about to read 5, iclass 6, count 0 2006.280.08:08:51.49#ibcon#read 5, iclass 6, count 0 2006.280.08:08:51.49#ibcon#about to read 6, iclass 6, count 0 2006.280.08:08:51.49#ibcon#read 6, iclass 6, count 0 2006.280.08:08:51.49#ibcon#end of sib2, iclass 6, count 0 2006.280.08:08:51.49#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:08:51.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:08:51.49#ibcon#[25=USB\r\n] 2006.280.08:08:51.49#ibcon#*before write, iclass 6, count 0 2006.280.08:08:51.49#ibcon#enter sib2, iclass 6, count 0 2006.280.08:08:51.49#ibcon#flushed, iclass 6, count 0 2006.280.08:08:51.49#ibcon#about to write, iclass 6, count 0 2006.280.08:08:51.49#ibcon#wrote, iclass 6, count 0 2006.280.08:08:51.49#ibcon#about to read 3, iclass 6, count 0 2006.280.08:08:51.52#ibcon#read 3, iclass 6, count 0 2006.280.08:08:51.52#ibcon#about to read 4, iclass 6, count 0 2006.280.08:08:51.52#ibcon#read 4, iclass 6, count 0 2006.280.08:08:51.52#ibcon#about to read 5, iclass 6, count 0 2006.280.08:08:51.52#ibcon#read 5, iclass 6, count 0 2006.280.08:08:51.52#ibcon#about to read 6, iclass 6, count 0 2006.280.08:08:51.52#ibcon#read 6, iclass 6, count 0 2006.280.08:08:51.52#ibcon#end of sib2, iclass 6, count 0 2006.280.08:08:51.52#ibcon#*after write, iclass 6, count 0 2006.280.08:08:51.52#ibcon#*before return 0, iclass 6, count 0 2006.280.08:08:51.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:51.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:51.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:08:51.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:08:51.52$vc4f8/valo=2,572.99 2006.280.08:08:51.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:08:51.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:08:51.52#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:51.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:51.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:51.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:51.52#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:08:51.52#ibcon#first serial, iclass 10, count 0 2006.280.08:08:51.52#ibcon#enter sib2, iclass 10, count 0 2006.280.08:08:51.52#ibcon#flushed, iclass 10, count 0 2006.280.08:08:51.52#ibcon#about to write, iclass 10, count 0 2006.280.08:08:51.52#ibcon#wrote, iclass 10, count 0 2006.280.08:08:51.52#ibcon#about to read 3, iclass 10, count 0 2006.280.08:08:51.54#ibcon#read 3, iclass 10, count 0 2006.280.08:08:51.54#ibcon#about to read 4, iclass 10, count 0 2006.280.08:08:51.54#ibcon#read 4, iclass 10, count 0 2006.280.08:08:51.54#ibcon#about to read 5, iclass 10, count 0 2006.280.08:08:51.54#ibcon#read 5, iclass 10, count 0 2006.280.08:08:51.54#ibcon#about to read 6, iclass 10, count 0 2006.280.08:08:51.54#ibcon#read 6, iclass 10, count 0 2006.280.08:08:51.54#ibcon#end of sib2, iclass 10, count 0 2006.280.08:08:51.54#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:08:51.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:08:51.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:08:51.54#ibcon#*before write, iclass 10, count 0 2006.280.08:08:51.54#ibcon#enter sib2, iclass 10, count 0 2006.280.08:08:51.54#ibcon#flushed, iclass 10, count 0 2006.280.08:08:51.54#ibcon#about to write, iclass 10, count 0 2006.280.08:08:51.54#ibcon#wrote, iclass 10, count 0 2006.280.08:08:51.54#ibcon#about to read 3, iclass 10, count 0 2006.280.08:08:51.58#ibcon#read 3, iclass 10, count 0 2006.280.08:08:51.58#ibcon#about to read 4, iclass 10, count 0 2006.280.08:08:51.58#ibcon#read 4, iclass 10, count 0 2006.280.08:08:51.58#ibcon#about to read 5, iclass 10, count 0 2006.280.08:08:51.58#ibcon#read 5, iclass 10, count 0 2006.280.08:08:51.58#ibcon#about to read 6, iclass 10, count 0 2006.280.08:08:51.58#ibcon#read 6, iclass 10, count 0 2006.280.08:08:51.58#ibcon#end of sib2, iclass 10, count 0 2006.280.08:08:51.58#ibcon#*after write, iclass 10, count 0 2006.280.08:08:51.58#ibcon#*before return 0, iclass 10, count 0 2006.280.08:08:51.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:51.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:51.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:08:51.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:08:51.58$vc4f8/va=2,6 2006.280.08:08:51.58#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:08:51.58#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:08:51.58#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:51.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:51.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:51.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:51.64#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:08:51.64#ibcon#first serial, iclass 12, count 2 2006.280.08:08:51.64#ibcon#enter sib2, iclass 12, count 2 2006.280.08:08:51.64#ibcon#flushed, iclass 12, count 2 2006.280.08:08:51.64#ibcon#about to write, iclass 12, count 2 2006.280.08:08:51.64#ibcon#wrote, iclass 12, count 2 2006.280.08:08:51.64#ibcon#about to read 3, iclass 12, count 2 2006.280.08:08:51.66#ibcon#read 3, iclass 12, count 2 2006.280.08:08:51.66#ibcon#about to read 4, iclass 12, count 2 2006.280.08:08:51.66#ibcon#read 4, iclass 12, count 2 2006.280.08:08:51.66#ibcon#about to read 5, iclass 12, count 2 2006.280.08:08:51.66#ibcon#read 5, iclass 12, count 2 2006.280.08:08:51.66#ibcon#about to read 6, iclass 12, count 2 2006.280.08:08:51.66#ibcon#read 6, iclass 12, count 2 2006.280.08:08:51.66#ibcon#end of sib2, iclass 12, count 2 2006.280.08:08:51.66#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:08:51.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:08:51.66#ibcon#[25=AT02-06\r\n] 2006.280.08:08:51.66#ibcon#*before write, iclass 12, count 2 2006.280.08:08:51.66#ibcon#enter sib2, iclass 12, count 2 2006.280.08:08:51.66#ibcon#flushed, iclass 12, count 2 2006.280.08:08:51.66#ibcon#about to write, iclass 12, count 2 2006.280.08:08:51.66#ibcon#wrote, iclass 12, count 2 2006.280.08:08:51.66#ibcon#about to read 3, iclass 12, count 2 2006.280.08:08:51.69#ibcon#read 3, iclass 12, count 2 2006.280.08:08:51.69#ibcon#about to read 4, iclass 12, count 2 2006.280.08:08:51.69#ibcon#read 4, iclass 12, count 2 2006.280.08:08:51.69#ibcon#about to read 5, iclass 12, count 2 2006.280.08:08:51.69#ibcon#read 5, iclass 12, count 2 2006.280.08:08:51.69#ibcon#about to read 6, iclass 12, count 2 2006.280.08:08:51.69#ibcon#read 6, iclass 12, count 2 2006.280.08:08:51.69#ibcon#end of sib2, iclass 12, count 2 2006.280.08:08:51.69#ibcon#*after write, iclass 12, count 2 2006.280.08:08:51.69#ibcon#*before return 0, iclass 12, count 2 2006.280.08:08:51.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:51.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:51.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:08:51.69#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:51.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:51.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:51.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:51.81#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:08:51.81#ibcon#first serial, iclass 12, count 0 2006.280.08:08:51.81#ibcon#enter sib2, iclass 12, count 0 2006.280.08:08:51.81#ibcon#flushed, iclass 12, count 0 2006.280.08:08:51.81#ibcon#about to write, iclass 12, count 0 2006.280.08:08:51.81#ibcon#wrote, iclass 12, count 0 2006.280.08:08:51.81#ibcon#about to read 3, iclass 12, count 0 2006.280.08:08:51.83#ibcon#read 3, iclass 12, count 0 2006.280.08:08:51.83#ibcon#about to read 4, iclass 12, count 0 2006.280.08:08:51.83#ibcon#read 4, iclass 12, count 0 2006.280.08:08:51.83#ibcon#about to read 5, iclass 12, count 0 2006.280.08:08:51.83#ibcon#read 5, iclass 12, count 0 2006.280.08:08:51.83#ibcon#about to read 6, iclass 12, count 0 2006.280.08:08:51.83#ibcon#read 6, iclass 12, count 0 2006.280.08:08:51.83#ibcon#end of sib2, iclass 12, count 0 2006.280.08:08:51.83#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:08:51.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:08:51.83#ibcon#[25=USB\r\n] 2006.280.08:08:51.83#ibcon#*before write, iclass 12, count 0 2006.280.08:08:51.83#ibcon#enter sib2, iclass 12, count 0 2006.280.08:08:51.83#ibcon#flushed, iclass 12, count 0 2006.280.08:08:51.83#ibcon#about to write, iclass 12, count 0 2006.280.08:08:51.83#ibcon#wrote, iclass 12, count 0 2006.280.08:08:51.83#ibcon#about to read 3, iclass 12, count 0 2006.280.08:08:51.86#ibcon#read 3, iclass 12, count 0 2006.280.08:08:51.86#ibcon#about to read 4, iclass 12, count 0 2006.280.08:08:51.86#ibcon#read 4, iclass 12, count 0 2006.280.08:08:51.86#ibcon#about to read 5, iclass 12, count 0 2006.280.08:08:51.86#ibcon#read 5, iclass 12, count 0 2006.280.08:08:51.86#ibcon#about to read 6, iclass 12, count 0 2006.280.08:08:51.86#ibcon#read 6, iclass 12, count 0 2006.280.08:08:51.86#ibcon#end of sib2, iclass 12, count 0 2006.280.08:08:51.86#ibcon#*after write, iclass 12, count 0 2006.280.08:08:51.86#ibcon#*before return 0, iclass 12, count 0 2006.280.08:08:51.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:51.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:51.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:08:51.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:08:51.86$vc4f8/valo=3,672.99 2006.280.08:08:51.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.08:08:51.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.08:08:51.86#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:51.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:51.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:51.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:51.86#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:08:51.86#ibcon#first serial, iclass 14, count 0 2006.280.08:08:51.86#ibcon#enter sib2, iclass 14, count 0 2006.280.08:08:51.86#ibcon#flushed, iclass 14, count 0 2006.280.08:08:51.86#ibcon#about to write, iclass 14, count 0 2006.280.08:08:51.86#ibcon#wrote, iclass 14, count 0 2006.280.08:08:51.86#ibcon#about to read 3, iclass 14, count 0 2006.280.08:08:51.88#ibcon#read 3, iclass 14, count 0 2006.280.08:08:51.88#ibcon#about to read 4, iclass 14, count 0 2006.280.08:08:51.88#ibcon#read 4, iclass 14, count 0 2006.280.08:08:51.88#ibcon#about to read 5, iclass 14, count 0 2006.280.08:08:51.88#ibcon#read 5, iclass 14, count 0 2006.280.08:08:51.88#ibcon#about to read 6, iclass 14, count 0 2006.280.08:08:51.88#ibcon#read 6, iclass 14, count 0 2006.280.08:08:51.88#ibcon#end of sib2, iclass 14, count 0 2006.280.08:08:51.88#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:08:51.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:08:51.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:08:51.88#ibcon#*before write, iclass 14, count 0 2006.280.08:08:51.88#ibcon#enter sib2, iclass 14, count 0 2006.280.08:08:51.88#ibcon#flushed, iclass 14, count 0 2006.280.08:08:51.88#ibcon#about to write, iclass 14, count 0 2006.280.08:08:51.88#ibcon#wrote, iclass 14, count 0 2006.280.08:08:51.88#ibcon#about to read 3, iclass 14, count 0 2006.280.08:08:51.92#ibcon#read 3, iclass 14, count 0 2006.280.08:08:51.92#ibcon#about to read 4, iclass 14, count 0 2006.280.08:08:51.92#ibcon#read 4, iclass 14, count 0 2006.280.08:08:51.92#ibcon#about to read 5, iclass 14, count 0 2006.280.08:08:51.92#ibcon#read 5, iclass 14, count 0 2006.280.08:08:51.92#ibcon#about to read 6, iclass 14, count 0 2006.280.08:08:51.92#ibcon#read 6, iclass 14, count 0 2006.280.08:08:51.92#ibcon#end of sib2, iclass 14, count 0 2006.280.08:08:51.92#ibcon#*after write, iclass 14, count 0 2006.280.08:08:51.92#ibcon#*before return 0, iclass 14, count 0 2006.280.08:08:51.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:51.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:51.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:08:51.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:08:51.92$vc4f8/va=3,6 2006.280.08:08:51.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.08:08:51.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.08:08:51.92#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:51.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:51.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:51.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:51.98#ibcon#enter wrdev, iclass 16, count 2 2006.280.08:08:51.98#ibcon#first serial, iclass 16, count 2 2006.280.08:08:51.98#ibcon#enter sib2, iclass 16, count 2 2006.280.08:08:51.98#ibcon#flushed, iclass 16, count 2 2006.280.08:08:51.98#ibcon#about to write, iclass 16, count 2 2006.280.08:08:51.98#ibcon#wrote, iclass 16, count 2 2006.280.08:08:51.98#ibcon#about to read 3, iclass 16, count 2 2006.280.08:08:52.00#ibcon#read 3, iclass 16, count 2 2006.280.08:08:52.00#ibcon#about to read 4, iclass 16, count 2 2006.280.08:08:52.00#ibcon#read 4, iclass 16, count 2 2006.280.08:08:52.00#ibcon#about to read 5, iclass 16, count 2 2006.280.08:08:52.00#ibcon#read 5, iclass 16, count 2 2006.280.08:08:52.00#ibcon#about to read 6, iclass 16, count 2 2006.280.08:08:52.00#ibcon#read 6, iclass 16, count 2 2006.280.08:08:52.00#ibcon#end of sib2, iclass 16, count 2 2006.280.08:08:52.00#ibcon#*mode == 0, iclass 16, count 2 2006.280.08:08:52.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.08:08:52.00#ibcon#[25=AT03-06\r\n] 2006.280.08:08:52.00#ibcon#*before write, iclass 16, count 2 2006.280.08:08:52.00#ibcon#enter sib2, iclass 16, count 2 2006.280.08:08:52.00#ibcon#flushed, iclass 16, count 2 2006.280.08:08:52.00#ibcon#about to write, iclass 16, count 2 2006.280.08:08:52.00#ibcon#wrote, iclass 16, count 2 2006.280.08:08:52.00#ibcon#about to read 3, iclass 16, count 2 2006.280.08:08:52.03#ibcon#read 3, iclass 16, count 2 2006.280.08:08:52.03#ibcon#about to read 4, iclass 16, count 2 2006.280.08:08:52.03#ibcon#read 4, iclass 16, count 2 2006.280.08:08:52.03#ibcon#about to read 5, iclass 16, count 2 2006.280.08:08:52.03#ibcon#read 5, iclass 16, count 2 2006.280.08:08:52.03#ibcon#about to read 6, iclass 16, count 2 2006.280.08:08:52.03#ibcon#read 6, iclass 16, count 2 2006.280.08:08:52.03#ibcon#end of sib2, iclass 16, count 2 2006.280.08:08:52.03#ibcon#*after write, iclass 16, count 2 2006.280.08:08:52.03#ibcon#*before return 0, iclass 16, count 2 2006.280.08:08:52.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:52.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:52.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.08:08:52.03#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:52.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:52.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:52.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:52.15#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:08:52.15#ibcon#first serial, iclass 16, count 0 2006.280.08:08:52.15#ibcon#enter sib2, iclass 16, count 0 2006.280.08:08:52.15#ibcon#flushed, iclass 16, count 0 2006.280.08:08:52.15#ibcon#about to write, iclass 16, count 0 2006.280.08:08:52.15#ibcon#wrote, iclass 16, count 0 2006.280.08:08:52.15#ibcon#about to read 3, iclass 16, count 0 2006.280.08:08:52.17#ibcon#read 3, iclass 16, count 0 2006.280.08:08:52.17#ibcon#about to read 4, iclass 16, count 0 2006.280.08:08:52.17#ibcon#read 4, iclass 16, count 0 2006.280.08:08:52.17#ibcon#about to read 5, iclass 16, count 0 2006.280.08:08:52.17#ibcon#read 5, iclass 16, count 0 2006.280.08:08:52.17#ibcon#about to read 6, iclass 16, count 0 2006.280.08:08:52.17#ibcon#read 6, iclass 16, count 0 2006.280.08:08:52.17#ibcon#end of sib2, iclass 16, count 0 2006.280.08:08:52.17#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:08:52.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:08:52.17#ibcon#[25=USB\r\n] 2006.280.08:08:52.17#ibcon#*before write, iclass 16, count 0 2006.280.08:08:52.17#ibcon#enter sib2, iclass 16, count 0 2006.280.08:08:52.17#ibcon#flushed, iclass 16, count 0 2006.280.08:08:52.17#ibcon#about to write, iclass 16, count 0 2006.280.08:08:52.17#ibcon#wrote, iclass 16, count 0 2006.280.08:08:52.17#ibcon#about to read 3, iclass 16, count 0 2006.280.08:08:52.20#ibcon#read 3, iclass 16, count 0 2006.280.08:08:52.20#ibcon#about to read 4, iclass 16, count 0 2006.280.08:08:52.20#ibcon#read 4, iclass 16, count 0 2006.280.08:08:52.20#ibcon#about to read 5, iclass 16, count 0 2006.280.08:08:52.20#ibcon#read 5, iclass 16, count 0 2006.280.08:08:52.20#ibcon#about to read 6, iclass 16, count 0 2006.280.08:08:52.20#ibcon#read 6, iclass 16, count 0 2006.280.08:08:52.20#ibcon#end of sib2, iclass 16, count 0 2006.280.08:08:52.20#ibcon#*after write, iclass 16, count 0 2006.280.08:08:52.20#ibcon#*before return 0, iclass 16, count 0 2006.280.08:08:52.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:52.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:52.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:08:52.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:08:52.20$vc4f8/valo=4,832.99 2006.280.08:08:52.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:08:52.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:08:52.20#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:52.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:52.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:52.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:52.20#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:08:52.20#ibcon#first serial, iclass 18, count 0 2006.280.08:08:52.20#ibcon#enter sib2, iclass 18, count 0 2006.280.08:08:52.20#ibcon#flushed, iclass 18, count 0 2006.280.08:08:52.20#ibcon#about to write, iclass 18, count 0 2006.280.08:08:52.20#ibcon#wrote, iclass 18, count 0 2006.280.08:08:52.20#ibcon#about to read 3, iclass 18, count 0 2006.280.08:08:52.22#ibcon#read 3, iclass 18, count 0 2006.280.08:08:52.22#ibcon#about to read 4, iclass 18, count 0 2006.280.08:08:52.22#ibcon#read 4, iclass 18, count 0 2006.280.08:08:52.22#ibcon#about to read 5, iclass 18, count 0 2006.280.08:08:52.22#ibcon#read 5, iclass 18, count 0 2006.280.08:08:52.22#ibcon#about to read 6, iclass 18, count 0 2006.280.08:08:52.22#ibcon#read 6, iclass 18, count 0 2006.280.08:08:52.22#ibcon#end of sib2, iclass 18, count 0 2006.280.08:08:52.22#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:08:52.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:08:52.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:08:52.22#ibcon#*before write, iclass 18, count 0 2006.280.08:08:52.22#ibcon#enter sib2, iclass 18, count 0 2006.280.08:08:52.22#ibcon#flushed, iclass 18, count 0 2006.280.08:08:52.22#ibcon#about to write, iclass 18, count 0 2006.280.08:08:52.22#ibcon#wrote, iclass 18, count 0 2006.280.08:08:52.22#ibcon#about to read 3, iclass 18, count 0 2006.280.08:08:52.26#ibcon#read 3, iclass 18, count 0 2006.280.08:08:52.26#ibcon#about to read 4, iclass 18, count 0 2006.280.08:08:52.26#ibcon#read 4, iclass 18, count 0 2006.280.08:08:52.26#ibcon#about to read 5, iclass 18, count 0 2006.280.08:08:52.26#ibcon#read 5, iclass 18, count 0 2006.280.08:08:52.26#ibcon#about to read 6, iclass 18, count 0 2006.280.08:08:52.26#ibcon#read 6, iclass 18, count 0 2006.280.08:08:52.26#ibcon#end of sib2, iclass 18, count 0 2006.280.08:08:52.26#ibcon#*after write, iclass 18, count 0 2006.280.08:08:52.26#ibcon#*before return 0, iclass 18, count 0 2006.280.08:08:52.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:52.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:52.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:08:52.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:08:52.26$vc4f8/va=4,6 2006.280.08:08:52.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:08:52.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:08:52.26#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:52.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:52.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:52.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:52.32#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:08:52.32#ibcon#first serial, iclass 20, count 2 2006.280.08:08:52.32#ibcon#enter sib2, iclass 20, count 2 2006.280.08:08:52.32#ibcon#flushed, iclass 20, count 2 2006.280.08:08:52.32#ibcon#about to write, iclass 20, count 2 2006.280.08:08:52.32#ibcon#wrote, iclass 20, count 2 2006.280.08:08:52.32#ibcon#about to read 3, iclass 20, count 2 2006.280.08:08:52.34#ibcon#read 3, iclass 20, count 2 2006.280.08:08:52.34#ibcon#about to read 4, iclass 20, count 2 2006.280.08:08:52.34#ibcon#read 4, iclass 20, count 2 2006.280.08:08:52.34#ibcon#about to read 5, iclass 20, count 2 2006.280.08:08:52.34#ibcon#read 5, iclass 20, count 2 2006.280.08:08:52.34#ibcon#about to read 6, iclass 20, count 2 2006.280.08:08:52.34#ibcon#read 6, iclass 20, count 2 2006.280.08:08:52.34#ibcon#end of sib2, iclass 20, count 2 2006.280.08:08:52.34#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:08:52.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:08:52.34#ibcon#[25=AT04-06\r\n] 2006.280.08:08:52.34#ibcon#*before write, iclass 20, count 2 2006.280.08:08:52.34#ibcon#enter sib2, iclass 20, count 2 2006.280.08:08:52.34#ibcon#flushed, iclass 20, count 2 2006.280.08:08:52.34#ibcon#about to write, iclass 20, count 2 2006.280.08:08:52.34#ibcon#wrote, iclass 20, count 2 2006.280.08:08:52.34#ibcon#about to read 3, iclass 20, count 2 2006.280.08:08:52.38#ibcon#read 3, iclass 20, count 2 2006.280.08:08:52.38#ibcon#about to read 4, iclass 20, count 2 2006.280.08:08:52.38#ibcon#read 4, iclass 20, count 2 2006.280.08:08:52.38#ibcon#about to read 5, iclass 20, count 2 2006.280.08:08:52.38#ibcon#read 5, iclass 20, count 2 2006.280.08:08:52.38#ibcon#about to read 6, iclass 20, count 2 2006.280.08:08:52.38#ibcon#read 6, iclass 20, count 2 2006.280.08:08:52.38#ibcon#end of sib2, iclass 20, count 2 2006.280.08:08:52.38#ibcon#*after write, iclass 20, count 2 2006.280.08:08:52.38#ibcon#*before return 0, iclass 20, count 2 2006.280.08:08:52.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:52.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:52.38#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:08:52.38#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:52.38#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:52.50#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:52.50#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:52.50#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:08:52.50#ibcon#first serial, iclass 20, count 0 2006.280.08:08:52.50#ibcon#enter sib2, iclass 20, count 0 2006.280.08:08:52.50#ibcon#flushed, iclass 20, count 0 2006.280.08:08:52.50#ibcon#about to write, iclass 20, count 0 2006.280.08:08:52.50#ibcon#wrote, iclass 20, count 0 2006.280.08:08:52.50#ibcon#about to read 3, iclass 20, count 0 2006.280.08:08:52.52#ibcon#read 3, iclass 20, count 0 2006.280.08:08:52.52#ibcon#about to read 4, iclass 20, count 0 2006.280.08:08:52.52#ibcon#read 4, iclass 20, count 0 2006.280.08:08:52.52#ibcon#about to read 5, iclass 20, count 0 2006.280.08:08:52.52#ibcon#read 5, iclass 20, count 0 2006.280.08:08:52.52#ibcon#about to read 6, iclass 20, count 0 2006.280.08:08:52.52#ibcon#read 6, iclass 20, count 0 2006.280.08:08:52.52#ibcon#end of sib2, iclass 20, count 0 2006.280.08:08:52.52#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:08:52.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:08:52.52#ibcon#[25=USB\r\n] 2006.280.08:08:52.52#ibcon#*before write, iclass 20, count 0 2006.280.08:08:52.52#ibcon#enter sib2, iclass 20, count 0 2006.280.08:08:52.52#ibcon#flushed, iclass 20, count 0 2006.280.08:08:52.52#ibcon#about to write, iclass 20, count 0 2006.280.08:08:52.52#ibcon#wrote, iclass 20, count 0 2006.280.08:08:52.52#ibcon#about to read 3, iclass 20, count 0 2006.280.08:08:52.55#ibcon#read 3, iclass 20, count 0 2006.280.08:08:52.55#ibcon#about to read 4, iclass 20, count 0 2006.280.08:08:52.55#ibcon#read 4, iclass 20, count 0 2006.280.08:08:52.55#ibcon#about to read 5, iclass 20, count 0 2006.280.08:08:52.55#ibcon#read 5, iclass 20, count 0 2006.280.08:08:52.55#ibcon#about to read 6, iclass 20, count 0 2006.280.08:08:52.55#ibcon#read 6, iclass 20, count 0 2006.280.08:08:52.55#ibcon#end of sib2, iclass 20, count 0 2006.280.08:08:52.55#ibcon#*after write, iclass 20, count 0 2006.280.08:08:52.55#ibcon#*before return 0, iclass 20, count 0 2006.280.08:08:52.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:52.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:52.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:08:52.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:08:52.55$vc4f8/valo=5,652.99 2006.280.08:08:52.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:08:52.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:08:52.55#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:52.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:52.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:52.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:52.55#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:08:52.55#ibcon#first serial, iclass 22, count 0 2006.280.08:08:52.55#ibcon#enter sib2, iclass 22, count 0 2006.280.08:08:52.55#ibcon#flushed, iclass 22, count 0 2006.280.08:08:52.55#ibcon#about to write, iclass 22, count 0 2006.280.08:08:52.55#ibcon#wrote, iclass 22, count 0 2006.280.08:08:52.55#ibcon#about to read 3, iclass 22, count 0 2006.280.08:08:52.57#ibcon#read 3, iclass 22, count 0 2006.280.08:08:52.58#ibcon#about to read 4, iclass 22, count 0 2006.280.08:08:52.58#ibcon#read 4, iclass 22, count 0 2006.280.08:08:52.58#ibcon#about to read 5, iclass 22, count 0 2006.280.08:08:52.58#ibcon#read 5, iclass 22, count 0 2006.280.08:08:52.58#ibcon#about to read 6, iclass 22, count 0 2006.280.08:08:52.58#ibcon#read 6, iclass 22, count 0 2006.280.08:08:52.58#ibcon#end of sib2, iclass 22, count 0 2006.280.08:08:52.58#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:08:52.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:08:52.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:08:52.58#ibcon#*before write, iclass 22, count 0 2006.280.08:08:52.58#ibcon#enter sib2, iclass 22, count 0 2006.280.08:08:52.58#ibcon#flushed, iclass 22, count 0 2006.280.08:08:52.58#ibcon#about to write, iclass 22, count 0 2006.280.08:08:52.58#ibcon#wrote, iclass 22, count 0 2006.280.08:08:52.58#ibcon#about to read 3, iclass 22, count 0 2006.280.08:08:52.62#ibcon#read 3, iclass 22, count 0 2006.280.08:08:52.62#ibcon#about to read 4, iclass 22, count 0 2006.280.08:08:52.62#ibcon#read 4, iclass 22, count 0 2006.280.08:08:52.62#ibcon#about to read 5, iclass 22, count 0 2006.280.08:08:52.62#ibcon#read 5, iclass 22, count 0 2006.280.08:08:52.62#ibcon#about to read 6, iclass 22, count 0 2006.280.08:08:52.62#ibcon#read 6, iclass 22, count 0 2006.280.08:08:52.62#ibcon#end of sib2, iclass 22, count 0 2006.280.08:08:52.62#ibcon#*after write, iclass 22, count 0 2006.280.08:08:52.62#ibcon#*before return 0, iclass 22, count 0 2006.280.08:08:52.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:52.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:52.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:08:52.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:08:52.62$vc4f8/va=5,7 2006.280.08:08:52.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:08:52.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:08:52.62#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:52.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:52.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:52.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:52.67#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:08:52.67#ibcon#first serial, iclass 24, count 2 2006.280.08:08:52.67#ibcon#enter sib2, iclass 24, count 2 2006.280.08:08:52.67#ibcon#flushed, iclass 24, count 2 2006.280.08:08:52.67#ibcon#about to write, iclass 24, count 2 2006.280.08:08:52.67#ibcon#wrote, iclass 24, count 2 2006.280.08:08:52.67#ibcon#about to read 3, iclass 24, count 2 2006.280.08:08:52.69#ibcon#read 3, iclass 24, count 2 2006.280.08:08:52.69#ibcon#about to read 4, iclass 24, count 2 2006.280.08:08:52.69#ibcon#read 4, iclass 24, count 2 2006.280.08:08:52.69#ibcon#about to read 5, iclass 24, count 2 2006.280.08:08:52.69#ibcon#read 5, iclass 24, count 2 2006.280.08:08:52.69#ibcon#about to read 6, iclass 24, count 2 2006.280.08:08:52.69#ibcon#read 6, iclass 24, count 2 2006.280.08:08:52.69#ibcon#end of sib2, iclass 24, count 2 2006.280.08:08:52.69#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:08:52.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:08:52.69#ibcon#[25=AT05-07\r\n] 2006.280.08:08:52.69#ibcon#*before write, iclass 24, count 2 2006.280.08:08:52.69#ibcon#enter sib2, iclass 24, count 2 2006.280.08:08:52.69#ibcon#flushed, iclass 24, count 2 2006.280.08:08:52.69#ibcon#about to write, iclass 24, count 2 2006.280.08:08:52.69#ibcon#wrote, iclass 24, count 2 2006.280.08:08:52.69#ibcon#about to read 3, iclass 24, count 2 2006.280.08:08:52.72#ibcon#read 3, iclass 24, count 2 2006.280.08:08:52.72#ibcon#about to read 4, iclass 24, count 2 2006.280.08:08:52.72#ibcon#read 4, iclass 24, count 2 2006.280.08:08:52.72#ibcon#about to read 5, iclass 24, count 2 2006.280.08:08:52.72#ibcon#read 5, iclass 24, count 2 2006.280.08:08:52.72#ibcon#about to read 6, iclass 24, count 2 2006.280.08:08:52.72#ibcon#read 6, iclass 24, count 2 2006.280.08:08:52.72#ibcon#end of sib2, iclass 24, count 2 2006.280.08:08:52.72#ibcon#*after write, iclass 24, count 2 2006.280.08:08:52.72#ibcon#*before return 0, iclass 24, count 2 2006.280.08:08:52.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:52.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:52.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:08:52.72#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:52.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:52.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:52.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:52.84#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:08:52.84#ibcon#first serial, iclass 24, count 0 2006.280.08:08:52.84#ibcon#enter sib2, iclass 24, count 0 2006.280.08:08:52.84#ibcon#flushed, iclass 24, count 0 2006.280.08:08:52.84#ibcon#about to write, iclass 24, count 0 2006.280.08:08:52.84#ibcon#wrote, iclass 24, count 0 2006.280.08:08:52.84#ibcon#about to read 3, iclass 24, count 0 2006.280.08:08:52.86#ibcon#read 3, iclass 24, count 0 2006.280.08:08:52.86#ibcon#about to read 4, iclass 24, count 0 2006.280.08:08:52.86#ibcon#read 4, iclass 24, count 0 2006.280.08:08:52.86#ibcon#about to read 5, iclass 24, count 0 2006.280.08:08:52.86#ibcon#read 5, iclass 24, count 0 2006.280.08:08:52.86#ibcon#about to read 6, iclass 24, count 0 2006.280.08:08:52.86#ibcon#read 6, iclass 24, count 0 2006.280.08:08:52.86#ibcon#end of sib2, iclass 24, count 0 2006.280.08:08:52.86#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:08:52.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:08:52.86#ibcon#[25=USB\r\n] 2006.280.08:08:52.86#ibcon#*before write, iclass 24, count 0 2006.280.08:08:52.86#ibcon#enter sib2, iclass 24, count 0 2006.280.08:08:52.86#ibcon#flushed, iclass 24, count 0 2006.280.08:08:52.86#ibcon#about to write, iclass 24, count 0 2006.280.08:08:52.86#ibcon#wrote, iclass 24, count 0 2006.280.08:08:52.86#ibcon#about to read 3, iclass 24, count 0 2006.280.08:08:52.89#ibcon#read 3, iclass 24, count 0 2006.280.08:08:52.89#ibcon#about to read 4, iclass 24, count 0 2006.280.08:08:52.89#ibcon#read 4, iclass 24, count 0 2006.280.08:08:52.89#ibcon#about to read 5, iclass 24, count 0 2006.280.08:08:52.89#ibcon#read 5, iclass 24, count 0 2006.280.08:08:52.89#ibcon#about to read 6, iclass 24, count 0 2006.280.08:08:52.89#ibcon#read 6, iclass 24, count 0 2006.280.08:08:52.89#ibcon#end of sib2, iclass 24, count 0 2006.280.08:08:52.89#ibcon#*after write, iclass 24, count 0 2006.280.08:08:52.89#ibcon#*before return 0, iclass 24, count 0 2006.280.08:08:52.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:52.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:52.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:08:52.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:08:52.89$vc4f8/valo=6,772.99 2006.280.08:08:52.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:08:52.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:08:52.89#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:52.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:52.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:52.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:52.89#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:08:52.89#ibcon#first serial, iclass 26, count 0 2006.280.08:08:52.89#ibcon#enter sib2, iclass 26, count 0 2006.280.08:08:52.89#ibcon#flushed, iclass 26, count 0 2006.280.08:08:52.89#ibcon#about to write, iclass 26, count 0 2006.280.08:08:52.89#ibcon#wrote, iclass 26, count 0 2006.280.08:08:52.89#ibcon#about to read 3, iclass 26, count 0 2006.280.08:08:52.91#ibcon#read 3, iclass 26, count 0 2006.280.08:08:52.91#ibcon#about to read 4, iclass 26, count 0 2006.280.08:08:52.91#ibcon#read 4, iclass 26, count 0 2006.280.08:08:52.91#ibcon#about to read 5, iclass 26, count 0 2006.280.08:08:52.91#ibcon#read 5, iclass 26, count 0 2006.280.08:08:52.91#ibcon#about to read 6, iclass 26, count 0 2006.280.08:08:52.91#ibcon#read 6, iclass 26, count 0 2006.280.08:08:52.91#ibcon#end of sib2, iclass 26, count 0 2006.280.08:08:52.91#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:08:52.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:08:52.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:08:52.91#ibcon#*before write, iclass 26, count 0 2006.280.08:08:52.91#ibcon#enter sib2, iclass 26, count 0 2006.280.08:08:52.91#ibcon#flushed, iclass 26, count 0 2006.280.08:08:52.91#ibcon#about to write, iclass 26, count 0 2006.280.08:08:52.91#ibcon#wrote, iclass 26, count 0 2006.280.08:08:52.91#ibcon#about to read 3, iclass 26, count 0 2006.280.08:08:52.95#ibcon#read 3, iclass 26, count 0 2006.280.08:08:52.95#ibcon#about to read 4, iclass 26, count 0 2006.280.08:08:52.95#ibcon#read 4, iclass 26, count 0 2006.280.08:08:52.95#ibcon#about to read 5, iclass 26, count 0 2006.280.08:08:52.95#ibcon#read 5, iclass 26, count 0 2006.280.08:08:52.95#ibcon#about to read 6, iclass 26, count 0 2006.280.08:08:52.95#ibcon#read 6, iclass 26, count 0 2006.280.08:08:52.95#ibcon#end of sib2, iclass 26, count 0 2006.280.08:08:52.95#ibcon#*after write, iclass 26, count 0 2006.280.08:08:52.95#ibcon#*before return 0, iclass 26, count 0 2006.280.08:08:52.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:52.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:52.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:08:52.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:08:52.95$vc4f8/va=6,6 2006.280.08:08:52.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:08:52.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:08:52.95#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:52.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:53.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:53.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:53.01#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:08:53.01#ibcon#first serial, iclass 28, count 2 2006.280.08:08:53.01#ibcon#enter sib2, iclass 28, count 2 2006.280.08:08:53.01#ibcon#flushed, iclass 28, count 2 2006.280.08:08:53.01#ibcon#about to write, iclass 28, count 2 2006.280.08:08:53.01#ibcon#wrote, iclass 28, count 2 2006.280.08:08:53.01#ibcon#about to read 3, iclass 28, count 2 2006.280.08:08:53.03#ibcon#read 3, iclass 28, count 2 2006.280.08:08:53.03#ibcon#about to read 4, iclass 28, count 2 2006.280.08:08:53.03#ibcon#read 4, iclass 28, count 2 2006.280.08:08:53.03#ibcon#about to read 5, iclass 28, count 2 2006.280.08:08:53.03#ibcon#read 5, iclass 28, count 2 2006.280.08:08:53.03#ibcon#about to read 6, iclass 28, count 2 2006.280.08:08:53.03#ibcon#read 6, iclass 28, count 2 2006.280.08:08:53.03#ibcon#end of sib2, iclass 28, count 2 2006.280.08:08:53.03#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:08:53.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:08:53.03#ibcon#[25=AT06-06\r\n] 2006.280.08:08:53.03#ibcon#*before write, iclass 28, count 2 2006.280.08:08:53.03#ibcon#enter sib2, iclass 28, count 2 2006.280.08:08:53.03#ibcon#flushed, iclass 28, count 2 2006.280.08:08:53.03#ibcon#about to write, iclass 28, count 2 2006.280.08:08:53.03#ibcon#wrote, iclass 28, count 2 2006.280.08:08:53.03#ibcon#about to read 3, iclass 28, count 2 2006.280.08:08:53.06#ibcon#read 3, iclass 28, count 2 2006.280.08:08:53.06#ibcon#about to read 4, iclass 28, count 2 2006.280.08:08:53.06#ibcon#read 4, iclass 28, count 2 2006.280.08:08:53.06#ibcon#about to read 5, iclass 28, count 2 2006.280.08:08:53.06#ibcon#read 5, iclass 28, count 2 2006.280.08:08:53.06#ibcon#about to read 6, iclass 28, count 2 2006.280.08:08:53.06#ibcon#read 6, iclass 28, count 2 2006.280.08:08:53.06#ibcon#end of sib2, iclass 28, count 2 2006.280.08:08:53.06#ibcon#*after write, iclass 28, count 2 2006.280.08:08:53.06#ibcon#*before return 0, iclass 28, count 2 2006.280.08:08:53.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:53.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:53.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:08:53.06#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:53.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:08:53.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:08:53.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:08:53.18#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:08:53.18#ibcon#first serial, iclass 28, count 0 2006.280.08:08:53.18#ibcon#enter sib2, iclass 28, count 0 2006.280.08:08:53.18#ibcon#flushed, iclass 28, count 0 2006.280.08:08:53.18#ibcon#about to write, iclass 28, count 0 2006.280.08:08:53.18#ibcon#wrote, iclass 28, count 0 2006.280.08:08:53.18#ibcon#about to read 3, iclass 28, count 0 2006.280.08:08:53.20#ibcon#read 3, iclass 28, count 0 2006.280.08:08:53.20#ibcon#about to read 4, iclass 28, count 0 2006.280.08:08:53.20#ibcon#read 4, iclass 28, count 0 2006.280.08:08:53.20#ibcon#about to read 5, iclass 28, count 0 2006.280.08:08:53.20#ibcon#read 5, iclass 28, count 0 2006.280.08:08:53.20#ibcon#about to read 6, iclass 28, count 0 2006.280.08:08:53.20#ibcon#read 6, iclass 28, count 0 2006.280.08:08:53.20#ibcon#end of sib2, iclass 28, count 0 2006.280.08:08:53.20#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:08:53.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:08:53.20#ibcon#[25=USB\r\n] 2006.280.08:08:53.20#ibcon#*before write, iclass 28, count 0 2006.280.08:08:53.20#ibcon#enter sib2, iclass 28, count 0 2006.280.08:08:53.20#ibcon#flushed, iclass 28, count 0 2006.280.08:08:53.20#ibcon#about to write, iclass 28, count 0 2006.280.08:08:53.20#ibcon#wrote, iclass 28, count 0 2006.280.08:08:53.20#ibcon#about to read 3, iclass 28, count 0 2006.280.08:08:53.23#ibcon#read 3, iclass 28, count 0 2006.280.08:08:53.23#ibcon#about to read 4, iclass 28, count 0 2006.280.08:08:53.23#ibcon#read 4, iclass 28, count 0 2006.280.08:08:53.23#ibcon#about to read 5, iclass 28, count 0 2006.280.08:08:53.23#ibcon#read 5, iclass 28, count 0 2006.280.08:08:53.23#ibcon#about to read 6, iclass 28, count 0 2006.280.08:08:53.23#ibcon#read 6, iclass 28, count 0 2006.280.08:08:53.23#ibcon#end of sib2, iclass 28, count 0 2006.280.08:08:53.23#ibcon#*after write, iclass 28, count 0 2006.280.08:08:53.23#ibcon#*before return 0, iclass 28, count 0 2006.280.08:08:53.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:08:53.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:08:53.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:08:53.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:08:53.23$vc4f8/valo=7,832.99 2006.280.08:08:53.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:08:53.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:08:53.23#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:53.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:08:53.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:08:53.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:08:53.23#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:08:53.23#ibcon#first serial, iclass 30, count 0 2006.280.08:08:53.23#ibcon#enter sib2, iclass 30, count 0 2006.280.08:08:53.23#ibcon#flushed, iclass 30, count 0 2006.280.08:08:53.23#ibcon#about to write, iclass 30, count 0 2006.280.08:08:53.23#ibcon#wrote, iclass 30, count 0 2006.280.08:08:53.23#ibcon#about to read 3, iclass 30, count 0 2006.280.08:08:53.25#ibcon#read 3, iclass 30, count 0 2006.280.08:08:53.25#ibcon#about to read 4, iclass 30, count 0 2006.280.08:08:53.25#ibcon#read 4, iclass 30, count 0 2006.280.08:08:53.25#ibcon#about to read 5, iclass 30, count 0 2006.280.08:08:53.25#ibcon#read 5, iclass 30, count 0 2006.280.08:08:53.25#ibcon#about to read 6, iclass 30, count 0 2006.280.08:08:53.25#ibcon#read 6, iclass 30, count 0 2006.280.08:08:53.25#ibcon#end of sib2, iclass 30, count 0 2006.280.08:08:53.25#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:08:53.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:08:53.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:08:53.25#ibcon#*before write, iclass 30, count 0 2006.280.08:08:53.25#ibcon#enter sib2, iclass 30, count 0 2006.280.08:08:53.25#ibcon#flushed, iclass 30, count 0 2006.280.08:08:53.25#ibcon#about to write, iclass 30, count 0 2006.280.08:08:53.25#ibcon#wrote, iclass 30, count 0 2006.280.08:08:53.25#ibcon#about to read 3, iclass 30, count 0 2006.280.08:08:53.29#ibcon#read 3, iclass 30, count 0 2006.280.08:08:53.29#ibcon#about to read 4, iclass 30, count 0 2006.280.08:08:53.29#ibcon#read 4, iclass 30, count 0 2006.280.08:08:53.29#ibcon#about to read 5, iclass 30, count 0 2006.280.08:08:53.29#ibcon#read 5, iclass 30, count 0 2006.280.08:08:53.29#ibcon#about to read 6, iclass 30, count 0 2006.280.08:08:53.29#ibcon#read 6, iclass 30, count 0 2006.280.08:08:53.29#ibcon#end of sib2, iclass 30, count 0 2006.280.08:08:53.29#ibcon#*after write, iclass 30, count 0 2006.280.08:08:53.29#ibcon#*before return 0, iclass 30, count 0 2006.280.08:08:53.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:08:53.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:08:53.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:08:53.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:08:53.29$vc4f8/va=7,6 2006.280.08:08:53.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:08:53.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:08:53.29#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:53.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:08:53.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:08:53.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:08:53.35#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:08:53.35#ibcon#first serial, iclass 32, count 2 2006.280.08:08:53.35#ibcon#enter sib2, iclass 32, count 2 2006.280.08:08:53.35#ibcon#flushed, iclass 32, count 2 2006.280.08:08:53.35#ibcon#about to write, iclass 32, count 2 2006.280.08:08:53.35#ibcon#wrote, iclass 32, count 2 2006.280.08:08:53.35#ibcon#about to read 3, iclass 32, count 2 2006.280.08:08:53.37#ibcon#read 3, iclass 32, count 2 2006.280.08:08:53.37#ibcon#about to read 4, iclass 32, count 2 2006.280.08:08:53.37#ibcon#read 4, iclass 32, count 2 2006.280.08:08:53.37#ibcon#about to read 5, iclass 32, count 2 2006.280.08:08:53.37#ibcon#read 5, iclass 32, count 2 2006.280.08:08:53.37#ibcon#about to read 6, iclass 32, count 2 2006.280.08:08:53.37#ibcon#read 6, iclass 32, count 2 2006.280.08:08:53.37#ibcon#end of sib2, iclass 32, count 2 2006.280.08:08:53.37#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:08:53.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:08:53.37#ibcon#[25=AT07-06\r\n] 2006.280.08:08:53.37#ibcon#*before write, iclass 32, count 2 2006.280.08:08:53.37#ibcon#enter sib2, iclass 32, count 2 2006.280.08:08:53.37#ibcon#flushed, iclass 32, count 2 2006.280.08:08:53.37#ibcon#about to write, iclass 32, count 2 2006.280.08:08:53.37#ibcon#wrote, iclass 32, count 2 2006.280.08:08:53.37#ibcon#about to read 3, iclass 32, count 2 2006.280.08:08:53.40#ibcon#read 3, iclass 32, count 2 2006.280.08:08:53.40#ibcon#about to read 4, iclass 32, count 2 2006.280.08:08:53.40#ibcon#read 4, iclass 32, count 2 2006.280.08:08:53.40#ibcon#about to read 5, iclass 32, count 2 2006.280.08:08:53.40#ibcon#read 5, iclass 32, count 2 2006.280.08:08:53.40#ibcon#about to read 6, iclass 32, count 2 2006.280.08:08:53.40#ibcon#read 6, iclass 32, count 2 2006.280.08:08:53.40#ibcon#end of sib2, iclass 32, count 2 2006.280.08:08:53.40#ibcon#*after write, iclass 32, count 2 2006.280.08:08:53.40#ibcon#*before return 0, iclass 32, count 2 2006.280.08:08:53.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:08:53.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:08:53.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:08:53.40#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:53.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:08:53.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:08:53.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:08:53.52#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:08:53.52#ibcon#first serial, iclass 32, count 0 2006.280.08:08:53.52#ibcon#enter sib2, iclass 32, count 0 2006.280.08:08:53.52#ibcon#flushed, iclass 32, count 0 2006.280.08:08:53.52#ibcon#about to write, iclass 32, count 0 2006.280.08:08:53.52#ibcon#wrote, iclass 32, count 0 2006.280.08:08:53.52#ibcon#about to read 3, iclass 32, count 0 2006.280.08:08:53.54#ibcon#read 3, iclass 32, count 0 2006.280.08:08:53.54#ibcon#about to read 4, iclass 32, count 0 2006.280.08:08:53.54#ibcon#read 4, iclass 32, count 0 2006.280.08:08:53.54#ibcon#about to read 5, iclass 32, count 0 2006.280.08:08:53.54#ibcon#read 5, iclass 32, count 0 2006.280.08:08:53.54#ibcon#about to read 6, iclass 32, count 0 2006.280.08:08:53.54#ibcon#read 6, iclass 32, count 0 2006.280.08:08:53.54#ibcon#end of sib2, iclass 32, count 0 2006.280.08:08:53.54#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:08:53.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:08:53.54#ibcon#[25=USB\r\n] 2006.280.08:08:53.54#ibcon#*before write, iclass 32, count 0 2006.280.08:08:53.54#ibcon#enter sib2, iclass 32, count 0 2006.280.08:08:53.54#ibcon#flushed, iclass 32, count 0 2006.280.08:08:53.54#ibcon#about to write, iclass 32, count 0 2006.280.08:08:53.54#ibcon#wrote, iclass 32, count 0 2006.280.08:08:53.54#ibcon#about to read 3, iclass 32, count 0 2006.280.08:08:53.57#ibcon#read 3, iclass 32, count 0 2006.280.08:08:53.57#ibcon#about to read 4, iclass 32, count 0 2006.280.08:08:53.57#ibcon#read 4, iclass 32, count 0 2006.280.08:08:53.57#ibcon#about to read 5, iclass 32, count 0 2006.280.08:08:53.57#ibcon#read 5, iclass 32, count 0 2006.280.08:08:53.57#ibcon#about to read 6, iclass 32, count 0 2006.280.08:08:53.57#ibcon#read 6, iclass 32, count 0 2006.280.08:08:53.57#ibcon#end of sib2, iclass 32, count 0 2006.280.08:08:53.57#ibcon#*after write, iclass 32, count 0 2006.280.08:08:53.57#ibcon#*before return 0, iclass 32, count 0 2006.280.08:08:53.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:08:53.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:08:53.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:08:53.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:08:53.57$vc4f8/valo=8,852.99 2006.280.08:08:53.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:08:53.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:08:53.57#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:53.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:08:53.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:08:53.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:08:53.57#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:08:53.57#ibcon#first serial, iclass 34, count 0 2006.280.08:08:53.57#ibcon#enter sib2, iclass 34, count 0 2006.280.08:08:53.57#ibcon#flushed, iclass 34, count 0 2006.280.08:08:53.57#ibcon#about to write, iclass 34, count 0 2006.280.08:08:53.57#ibcon#wrote, iclass 34, count 0 2006.280.08:08:53.57#ibcon#about to read 3, iclass 34, count 0 2006.280.08:08:53.59#ibcon#read 3, iclass 34, count 0 2006.280.08:08:53.59#ibcon#about to read 4, iclass 34, count 0 2006.280.08:08:53.59#ibcon#read 4, iclass 34, count 0 2006.280.08:08:53.59#ibcon#about to read 5, iclass 34, count 0 2006.280.08:08:53.59#ibcon#read 5, iclass 34, count 0 2006.280.08:08:53.59#ibcon#about to read 6, iclass 34, count 0 2006.280.08:08:53.59#ibcon#read 6, iclass 34, count 0 2006.280.08:08:53.59#ibcon#end of sib2, iclass 34, count 0 2006.280.08:08:53.59#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:08:53.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:08:53.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:08:53.59#ibcon#*before write, iclass 34, count 0 2006.280.08:08:53.59#ibcon#enter sib2, iclass 34, count 0 2006.280.08:08:53.59#ibcon#flushed, iclass 34, count 0 2006.280.08:08:53.59#ibcon#about to write, iclass 34, count 0 2006.280.08:08:53.59#ibcon#wrote, iclass 34, count 0 2006.280.08:08:53.59#ibcon#about to read 3, iclass 34, count 0 2006.280.08:08:53.63#ibcon#read 3, iclass 34, count 0 2006.280.08:08:53.63#ibcon#about to read 4, iclass 34, count 0 2006.280.08:08:53.63#ibcon#read 4, iclass 34, count 0 2006.280.08:08:53.63#ibcon#about to read 5, iclass 34, count 0 2006.280.08:08:53.63#ibcon#read 5, iclass 34, count 0 2006.280.08:08:53.63#ibcon#about to read 6, iclass 34, count 0 2006.280.08:08:53.63#ibcon#read 6, iclass 34, count 0 2006.280.08:08:53.63#ibcon#end of sib2, iclass 34, count 0 2006.280.08:08:53.63#ibcon#*after write, iclass 34, count 0 2006.280.08:08:53.63#ibcon#*before return 0, iclass 34, count 0 2006.280.08:08:53.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:08:53.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:08:53.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:08:53.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:08:53.63$vc4f8/va=8,6 2006.280.08:08:53.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:08:53.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:08:53.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:53.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:08:53.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:08:53.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:08:53.69#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:08:53.69#ibcon#first serial, iclass 36, count 2 2006.280.08:08:53.69#ibcon#enter sib2, iclass 36, count 2 2006.280.08:08:53.69#ibcon#flushed, iclass 36, count 2 2006.280.08:08:53.69#ibcon#about to write, iclass 36, count 2 2006.280.08:08:53.69#ibcon#wrote, iclass 36, count 2 2006.280.08:08:53.69#ibcon#about to read 3, iclass 36, count 2 2006.280.08:08:53.71#ibcon#read 3, iclass 36, count 2 2006.280.08:08:53.71#ibcon#about to read 4, iclass 36, count 2 2006.280.08:08:53.71#ibcon#read 4, iclass 36, count 2 2006.280.08:08:53.71#ibcon#about to read 5, iclass 36, count 2 2006.280.08:08:53.71#ibcon#read 5, iclass 36, count 2 2006.280.08:08:53.71#ibcon#about to read 6, iclass 36, count 2 2006.280.08:08:53.71#ibcon#read 6, iclass 36, count 2 2006.280.08:08:53.71#ibcon#end of sib2, iclass 36, count 2 2006.280.08:08:53.71#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:08:53.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:08:53.71#ibcon#[25=AT08-06\r\n] 2006.280.08:08:53.71#ibcon#*before write, iclass 36, count 2 2006.280.08:08:53.71#ibcon#enter sib2, iclass 36, count 2 2006.280.08:08:53.71#ibcon#flushed, iclass 36, count 2 2006.280.08:08:53.71#ibcon#about to write, iclass 36, count 2 2006.280.08:08:53.71#ibcon#wrote, iclass 36, count 2 2006.280.08:08:53.71#ibcon#about to read 3, iclass 36, count 2 2006.280.08:08:53.74#ibcon#read 3, iclass 36, count 2 2006.280.08:08:53.74#ibcon#about to read 4, iclass 36, count 2 2006.280.08:08:53.74#ibcon#read 4, iclass 36, count 2 2006.280.08:08:53.74#ibcon#about to read 5, iclass 36, count 2 2006.280.08:08:53.74#ibcon#read 5, iclass 36, count 2 2006.280.08:08:53.74#ibcon#about to read 6, iclass 36, count 2 2006.280.08:08:53.74#ibcon#read 6, iclass 36, count 2 2006.280.08:08:53.74#ibcon#end of sib2, iclass 36, count 2 2006.280.08:08:53.74#ibcon#*after write, iclass 36, count 2 2006.280.08:08:53.74#ibcon#*before return 0, iclass 36, count 2 2006.280.08:08:53.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:08:53.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:08:53.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:08:53.74#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:53.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:08:53.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:08:53.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:08:53.86#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:08:53.86#ibcon#first serial, iclass 36, count 0 2006.280.08:08:53.86#ibcon#enter sib2, iclass 36, count 0 2006.280.08:08:53.86#ibcon#flushed, iclass 36, count 0 2006.280.08:08:53.86#ibcon#about to write, iclass 36, count 0 2006.280.08:08:53.86#ibcon#wrote, iclass 36, count 0 2006.280.08:08:53.86#ibcon#about to read 3, iclass 36, count 0 2006.280.08:08:53.88#ibcon#read 3, iclass 36, count 0 2006.280.08:08:53.88#ibcon#about to read 4, iclass 36, count 0 2006.280.08:08:53.88#ibcon#read 4, iclass 36, count 0 2006.280.08:08:53.88#ibcon#about to read 5, iclass 36, count 0 2006.280.08:08:53.88#ibcon#read 5, iclass 36, count 0 2006.280.08:08:53.88#ibcon#about to read 6, iclass 36, count 0 2006.280.08:08:53.88#ibcon#read 6, iclass 36, count 0 2006.280.08:08:53.88#ibcon#end of sib2, iclass 36, count 0 2006.280.08:08:53.88#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:08:53.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:08:53.88#ibcon#[25=USB\r\n] 2006.280.08:08:53.88#ibcon#*before write, iclass 36, count 0 2006.280.08:08:53.88#ibcon#enter sib2, iclass 36, count 0 2006.280.08:08:53.88#ibcon#flushed, iclass 36, count 0 2006.280.08:08:53.88#ibcon#about to write, iclass 36, count 0 2006.280.08:08:53.88#ibcon#wrote, iclass 36, count 0 2006.280.08:08:53.88#ibcon#about to read 3, iclass 36, count 0 2006.280.08:08:53.91#ibcon#read 3, iclass 36, count 0 2006.280.08:08:53.91#ibcon#about to read 4, iclass 36, count 0 2006.280.08:08:53.91#ibcon#read 4, iclass 36, count 0 2006.280.08:08:53.91#ibcon#about to read 5, iclass 36, count 0 2006.280.08:08:53.91#ibcon#read 5, iclass 36, count 0 2006.280.08:08:53.91#ibcon#about to read 6, iclass 36, count 0 2006.280.08:08:53.91#ibcon#read 6, iclass 36, count 0 2006.280.08:08:53.91#ibcon#end of sib2, iclass 36, count 0 2006.280.08:08:53.91#ibcon#*after write, iclass 36, count 0 2006.280.08:08:53.91#ibcon#*before return 0, iclass 36, count 0 2006.280.08:08:53.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:08:53.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:08:53.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:08:53.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:08:53.91$vc4f8/vblo=1,632.99 2006.280.08:08:53.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:08:53.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:08:53.91#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:53.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:08:53.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:08:53.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:08:53.91#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:08:53.91#ibcon#first serial, iclass 38, count 0 2006.280.08:08:53.91#ibcon#enter sib2, iclass 38, count 0 2006.280.08:08:53.91#ibcon#flushed, iclass 38, count 0 2006.280.08:08:53.91#ibcon#about to write, iclass 38, count 0 2006.280.08:08:53.91#ibcon#wrote, iclass 38, count 0 2006.280.08:08:53.91#ibcon#about to read 3, iclass 38, count 0 2006.280.08:08:53.93#ibcon#read 3, iclass 38, count 0 2006.280.08:08:53.93#ibcon#about to read 4, iclass 38, count 0 2006.280.08:08:53.93#ibcon#read 4, iclass 38, count 0 2006.280.08:08:53.93#ibcon#about to read 5, iclass 38, count 0 2006.280.08:08:53.93#ibcon#read 5, iclass 38, count 0 2006.280.08:08:53.93#ibcon#about to read 6, iclass 38, count 0 2006.280.08:08:53.93#ibcon#read 6, iclass 38, count 0 2006.280.08:08:53.93#ibcon#end of sib2, iclass 38, count 0 2006.280.08:08:53.93#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:08:53.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:08:53.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:08:53.93#ibcon#*before write, iclass 38, count 0 2006.280.08:08:53.93#ibcon#enter sib2, iclass 38, count 0 2006.280.08:08:53.93#ibcon#flushed, iclass 38, count 0 2006.280.08:08:53.93#ibcon#about to write, iclass 38, count 0 2006.280.08:08:53.93#ibcon#wrote, iclass 38, count 0 2006.280.08:08:53.93#ibcon#about to read 3, iclass 38, count 0 2006.280.08:08:53.97#ibcon#read 3, iclass 38, count 0 2006.280.08:08:53.97#ibcon#about to read 4, iclass 38, count 0 2006.280.08:08:53.97#ibcon#read 4, iclass 38, count 0 2006.280.08:08:53.97#ibcon#about to read 5, iclass 38, count 0 2006.280.08:08:53.97#ibcon#read 5, iclass 38, count 0 2006.280.08:08:53.97#ibcon#about to read 6, iclass 38, count 0 2006.280.08:08:53.97#ibcon#read 6, iclass 38, count 0 2006.280.08:08:53.97#ibcon#end of sib2, iclass 38, count 0 2006.280.08:08:53.97#ibcon#*after write, iclass 38, count 0 2006.280.08:08:53.97#ibcon#*before return 0, iclass 38, count 0 2006.280.08:08:53.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:08:53.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:08:53.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:08:53.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:08:53.97$vc4f8/vb=1,4 2006.280.08:08:53.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:08:53.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:08:53.97#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:53.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:08:53.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:08:53.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:08:53.97#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:08:53.97#ibcon#first serial, iclass 40, count 2 2006.280.08:08:53.97#ibcon#enter sib2, iclass 40, count 2 2006.280.08:08:53.97#ibcon#flushed, iclass 40, count 2 2006.280.08:08:53.97#ibcon#about to write, iclass 40, count 2 2006.280.08:08:53.97#ibcon#wrote, iclass 40, count 2 2006.280.08:08:53.97#ibcon#about to read 3, iclass 40, count 2 2006.280.08:08:53.99#ibcon#read 3, iclass 40, count 2 2006.280.08:08:53.99#ibcon#about to read 4, iclass 40, count 2 2006.280.08:08:53.99#ibcon#read 4, iclass 40, count 2 2006.280.08:08:53.99#ibcon#about to read 5, iclass 40, count 2 2006.280.08:08:53.99#ibcon#read 5, iclass 40, count 2 2006.280.08:08:53.99#ibcon#about to read 6, iclass 40, count 2 2006.280.08:08:53.99#ibcon#read 6, iclass 40, count 2 2006.280.08:08:53.99#ibcon#end of sib2, iclass 40, count 2 2006.280.08:08:53.99#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:08:53.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:08:53.99#ibcon#[27=AT01-04\r\n] 2006.280.08:08:53.99#ibcon#*before write, iclass 40, count 2 2006.280.08:08:53.99#ibcon#enter sib2, iclass 40, count 2 2006.280.08:08:53.99#ibcon#flushed, iclass 40, count 2 2006.280.08:08:53.99#ibcon#about to write, iclass 40, count 2 2006.280.08:08:53.99#ibcon#wrote, iclass 40, count 2 2006.280.08:08:53.99#ibcon#about to read 3, iclass 40, count 2 2006.280.08:08:54.02#ibcon#read 3, iclass 40, count 2 2006.280.08:08:54.02#ibcon#about to read 4, iclass 40, count 2 2006.280.08:08:54.02#ibcon#read 4, iclass 40, count 2 2006.280.08:08:54.02#ibcon#about to read 5, iclass 40, count 2 2006.280.08:08:54.02#ibcon#read 5, iclass 40, count 2 2006.280.08:08:54.02#ibcon#about to read 6, iclass 40, count 2 2006.280.08:08:54.02#ibcon#read 6, iclass 40, count 2 2006.280.08:08:54.02#ibcon#end of sib2, iclass 40, count 2 2006.280.08:08:54.02#ibcon#*after write, iclass 40, count 2 2006.280.08:08:54.02#ibcon#*before return 0, iclass 40, count 2 2006.280.08:08:54.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:08:54.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:08:54.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:08:54.02#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:54.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:08:54.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:08:54.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:08:54.14#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:08:54.14#ibcon#first serial, iclass 40, count 0 2006.280.08:08:54.14#ibcon#enter sib2, iclass 40, count 0 2006.280.08:08:54.14#ibcon#flushed, iclass 40, count 0 2006.280.08:08:54.14#ibcon#about to write, iclass 40, count 0 2006.280.08:08:54.14#ibcon#wrote, iclass 40, count 0 2006.280.08:08:54.14#ibcon#about to read 3, iclass 40, count 0 2006.280.08:08:54.16#ibcon#read 3, iclass 40, count 0 2006.280.08:08:54.16#ibcon#about to read 4, iclass 40, count 0 2006.280.08:08:54.16#ibcon#read 4, iclass 40, count 0 2006.280.08:08:54.16#ibcon#about to read 5, iclass 40, count 0 2006.280.08:08:54.16#ibcon#read 5, iclass 40, count 0 2006.280.08:08:54.16#ibcon#about to read 6, iclass 40, count 0 2006.280.08:08:54.16#ibcon#read 6, iclass 40, count 0 2006.280.08:08:54.16#ibcon#end of sib2, iclass 40, count 0 2006.280.08:08:54.16#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:08:54.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:08:54.16#ibcon#[27=USB\r\n] 2006.280.08:08:54.16#ibcon#*before write, iclass 40, count 0 2006.280.08:08:54.16#ibcon#enter sib2, iclass 40, count 0 2006.280.08:08:54.16#ibcon#flushed, iclass 40, count 0 2006.280.08:08:54.16#ibcon#about to write, iclass 40, count 0 2006.280.08:08:54.16#ibcon#wrote, iclass 40, count 0 2006.280.08:08:54.16#ibcon#about to read 3, iclass 40, count 0 2006.280.08:08:54.19#ibcon#read 3, iclass 40, count 0 2006.280.08:08:54.19#ibcon#about to read 4, iclass 40, count 0 2006.280.08:08:54.19#ibcon#read 4, iclass 40, count 0 2006.280.08:08:54.19#ibcon#about to read 5, iclass 40, count 0 2006.280.08:08:54.19#ibcon#read 5, iclass 40, count 0 2006.280.08:08:54.19#ibcon#about to read 6, iclass 40, count 0 2006.280.08:08:54.19#ibcon#read 6, iclass 40, count 0 2006.280.08:08:54.19#ibcon#end of sib2, iclass 40, count 0 2006.280.08:08:54.19#ibcon#*after write, iclass 40, count 0 2006.280.08:08:54.19#ibcon#*before return 0, iclass 40, count 0 2006.280.08:08:54.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:08:54.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:08:54.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:08:54.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:08:54.19$vc4f8/vblo=2,640.99 2006.280.08:08:54.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:08:54.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:08:54.19#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:54.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:54.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:54.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:54.19#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:08:54.19#ibcon#first serial, iclass 4, count 0 2006.280.08:08:54.19#ibcon#enter sib2, iclass 4, count 0 2006.280.08:08:54.19#ibcon#flushed, iclass 4, count 0 2006.280.08:08:54.19#ibcon#about to write, iclass 4, count 0 2006.280.08:08:54.19#ibcon#wrote, iclass 4, count 0 2006.280.08:08:54.19#ibcon#about to read 3, iclass 4, count 0 2006.280.08:08:54.21#ibcon#read 3, iclass 4, count 0 2006.280.08:08:54.21#ibcon#about to read 4, iclass 4, count 0 2006.280.08:08:54.21#ibcon#read 4, iclass 4, count 0 2006.280.08:08:54.21#ibcon#about to read 5, iclass 4, count 0 2006.280.08:08:54.21#ibcon#read 5, iclass 4, count 0 2006.280.08:08:54.21#ibcon#about to read 6, iclass 4, count 0 2006.280.08:08:54.21#ibcon#read 6, iclass 4, count 0 2006.280.08:08:54.21#ibcon#end of sib2, iclass 4, count 0 2006.280.08:08:54.21#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:08:54.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:08:54.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:08:54.21#ibcon#*before write, iclass 4, count 0 2006.280.08:08:54.21#ibcon#enter sib2, iclass 4, count 0 2006.280.08:08:54.21#ibcon#flushed, iclass 4, count 0 2006.280.08:08:54.21#ibcon#about to write, iclass 4, count 0 2006.280.08:08:54.21#ibcon#wrote, iclass 4, count 0 2006.280.08:08:54.21#ibcon#about to read 3, iclass 4, count 0 2006.280.08:08:54.25#ibcon#read 3, iclass 4, count 0 2006.280.08:08:54.25#ibcon#about to read 4, iclass 4, count 0 2006.280.08:08:54.25#ibcon#read 4, iclass 4, count 0 2006.280.08:08:54.25#ibcon#about to read 5, iclass 4, count 0 2006.280.08:08:54.25#ibcon#read 5, iclass 4, count 0 2006.280.08:08:54.25#ibcon#about to read 6, iclass 4, count 0 2006.280.08:08:54.25#ibcon#read 6, iclass 4, count 0 2006.280.08:08:54.25#ibcon#end of sib2, iclass 4, count 0 2006.280.08:08:54.25#ibcon#*after write, iclass 4, count 0 2006.280.08:08:54.25#ibcon#*before return 0, iclass 4, count 0 2006.280.08:08:54.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:54.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:08:54.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:08:54.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:08:54.25$vc4f8/vb=2,5 2006.280.08:08:54.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:08:54.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:08:54.26#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:54.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:54.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:54.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:54.31#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:08:54.31#ibcon#first serial, iclass 6, count 2 2006.280.08:08:54.31#ibcon#enter sib2, iclass 6, count 2 2006.280.08:08:54.31#ibcon#flushed, iclass 6, count 2 2006.280.08:08:54.31#ibcon#about to write, iclass 6, count 2 2006.280.08:08:54.31#ibcon#wrote, iclass 6, count 2 2006.280.08:08:54.31#ibcon#about to read 3, iclass 6, count 2 2006.280.08:08:54.33#ibcon#read 3, iclass 6, count 2 2006.280.08:08:54.33#ibcon#about to read 4, iclass 6, count 2 2006.280.08:08:54.33#ibcon#read 4, iclass 6, count 2 2006.280.08:08:54.33#ibcon#about to read 5, iclass 6, count 2 2006.280.08:08:54.33#ibcon#read 5, iclass 6, count 2 2006.280.08:08:54.33#ibcon#about to read 6, iclass 6, count 2 2006.280.08:08:54.33#ibcon#read 6, iclass 6, count 2 2006.280.08:08:54.33#ibcon#end of sib2, iclass 6, count 2 2006.280.08:08:54.33#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:08:54.33#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:08:54.33#ibcon#[27=AT02-05\r\n] 2006.280.08:08:54.33#ibcon#*before write, iclass 6, count 2 2006.280.08:08:54.33#ibcon#enter sib2, iclass 6, count 2 2006.280.08:08:54.33#ibcon#flushed, iclass 6, count 2 2006.280.08:08:54.33#ibcon#about to write, iclass 6, count 2 2006.280.08:08:54.33#ibcon#wrote, iclass 6, count 2 2006.280.08:08:54.33#ibcon#about to read 3, iclass 6, count 2 2006.280.08:08:54.36#ibcon#read 3, iclass 6, count 2 2006.280.08:08:54.36#ibcon#about to read 4, iclass 6, count 2 2006.280.08:08:54.36#ibcon#read 4, iclass 6, count 2 2006.280.08:08:54.36#ibcon#about to read 5, iclass 6, count 2 2006.280.08:08:54.36#ibcon#read 5, iclass 6, count 2 2006.280.08:08:54.36#ibcon#about to read 6, iclass 6, count 2 2006.280.08:08:54.36#ibcon#read 6, iclass 6, count 2 2006.280.08:08:54.36#ibcon#end of sib2, iclass 6, count 2 2006.280.08:08:54.36#ibcon#*after write, iclass 6, count 2 2006.280.08:08:54.36#ibcon#*before return 0, iclass 6, count 2 2006.280.08:08:54.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:54.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:08:54.36#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:08:54.36#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:54.36#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:54.48#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:54.48#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:54.48#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:08:54.48#ibcon#first serial, iclass 6, count 0 2006.280.08:08:54.48#ibcon#enter sib2, iclass 6, count 0 2006.280.08:08:54.48#ibcon#flushed, iclass 6, count 0 2006.280.08:08:54.48#ibcon#about to write, iclass 6, count 0 2006.280.08:08:54.48#ibcon#wrote, iclass 6, count 0 2006.280.08:08:54.48#ibcon#about to read 3, iclass 6, count 0 2006.280.08:08:54.50#ibcon#read 3, iclass 6, count 0 2006.280.08:08:54.50#ibcon#about to read 4, iclass 6, count 0 2006.280.08:08:54.50#ibcon#read 4, iclass 6, count 0 2006.280.08:08:54.50#ibcon#about to read 5, iclass 6, count 0 2006.280.08:08:54.50#ibcon#read 5, iclass 6, count 0 2006.280.08:08:54.50#ibcon#about to read 6, iclass 6, count 0 2006.280.08:08:54.50#ibcon#read 6, iclass 6, count 0 2006.280.08:08:54.50#ibcon#end of sib2, iclass 6, count 0 2006.280.08:08:54.50#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:08:54.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:08:54.50#ibcon#[27=USB\r\n] 2006.280.08:08:54.50#ibcon#*before write, iclass 6, count 0 2006.280.08:08:54.50#ibcon#enter sib2, iclass 6, count 0 2006.280.08:08:54.50#ibcon#flushed, iclass 6, count 0 2006.280.08:08:54.50#ibcon#about to write, iclass 6, count 0 2006.280.08:08:54.50#ibcon#wrote, iclass 6, count 0 2006.280.08:08:54.50#ibcon#about to read 3, iclass 6, count 0 2006.280.08:08:54.53#ibcon#read 3, iclass 6, count 0 2006.280.08:08:54.53#ibcon#about to read 4, iclass 6, count 0 2006.280.08:08:54.53#ibcon#read 4, iclass 6, count 0 2006.280.08:08:54.53#ibcon#about to read 5, iclass 6, count 0 2006.280.08:08:54.53#ibcon#read 5, iclass 6, count 0 2006.280.08:08:54.53#ibcon#about to read 6, iclass 6, count 0 2006.280.08:08:54.53#ibcon#read 6, iclass 6, count 0 2006.280.08:08:54.53#ibcon#end of sib2, iclass 6, count 0 2006.280.08:08:54.53#ibcon#*after write, iclass 6, count 0 2006.280.08:08:54.53#ibcon#*before return 0, iclass 6, count 0 2006.280.08:08:54.53#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:54.53#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:08:54.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:08:54.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:08:54.53$vc4f8/vblo=3,656.99 2006.280.08:08:54.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:08:54.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:08:54.53#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:54.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:54.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:54.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:54.53#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:08:54.53#ibcon#first serial, iclass 10, count 0 2006.280.08:08:54.53#ibcon#enter sib2, iclass 10, count 0 2006.280.08:08:54.53#ibcon#flushed, iclass 10, count 0 2006.280.08:08:54.53#ibcon#about to write, iclass 10, count 0 2006.280.08:08:54.53#ibcon#wrote, iclass 10, count 0 2006.280.08:08:54.53#ibcon#about to read 3, iclass 10, count 0 2006.280.08:08:54.55#ibcon#read 3, iclass 10, count 0 2006.280.08:08:54.55#ibcon#about to read 4, iclass 10, count 0 2006.280.08:08:54.55#ibcon#read 4, iclass 10, count 0 2006.280.08:08:54.55#ibcon#about to read 5, iclass 10, count 0 2006.280.08:08:54.55#ibcon#read 5, iclass 10, count 0 2006.280.08:08:54.56#ibcon#about to read 6, iclass 10, count 0 2006.280.08:08:54.56#ibcon#read 6, iclass 10, count 0 2006.280.08:08:54.56#ibcon#end of sib2, iclass 10, count 0 2006.280.08:08:54.56#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:08:54.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:08:54.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:08:54.56#ibcon#*before write, iclass 10, count 0 2006.280.08:08:54.56#ibcon#enter sib2, iclass 10, count 0 2006.280.08:08:54.56#ibcon#flushed, iclass 10, count 0 2006.280.08:08:54.56#ibcon#about to write, iclass 10, count 0 2006.280.08:08:54.56#ibcon#wrote, iclass 10, count 0 2006.280.08:08:54.56#ibcon#about to read 3, iclass 10, count 0 2006.280.08:08:54.60#ibcon#read 3, iclass 10, count 0 2006.280.08:08:54.60#ibcon#about to read 4, iclass 10, count 0 2006.280.08:08:54.60#ibcon#read 4, iclass 10, count 0 2006.280.08:08:54.60#ibcon#about to read 5, iclass 10, count 0 2006.280.08:08:54.60#ibcon#read 5, iclass 10, count 0 2006.280.08:08:54.60#ibcon#about to read 6, iclass 10, count 0 2006.280.08:08:54.60#ibcon#read 6, iclass 10, count 0 2006.280.08:08:54.60#ibcon#end of sib2, iclass 10, count 0 2006.280.08:08:54.60#ibcon#*after write, iclass 10, count 0 2006.280.08:08:54.60#ibcon#*before return 0, iclass 10, count 0 2006.280.08:08:54.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:54.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:08:54.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:08:54.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:08:54.60$vc4f8/vb=3,4 2006.280.08:08:54.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:08:54.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:08:54.60#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:54.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:54.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:54.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:54.65#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:08:54.65#ibcon#first serial, iclass 12, count 2 2006.280.08:08:54.65#ibcon#enter sib2, iclass 12, count 2 2006.280.08:08:54.65#ibcon#flushed, iclass 12, count 2 2006.280.08:08:54.65#ibcon#about to write, iclass 12, count 2 2006.280.08:08:54.65#ibcon#wrote, iclass 12, count 2 2006.280.08:08:54.65#ibcon#about to read 3, iclass 12, count 2 2006.280.08:08:54.67#ibcon#read 3, iclass 12, count 2 2006.280.08:08:54.67#ibcon#about to read 4, iclass 12, count 2 2006.280.08:08:54.67#ibcon#read 4, iclass 12, count 2 2006.280.08:08:54.67#ibcon#about to read 5, iclass 12, count 2 2006.280.08:08:54.67#ibcon#read 5, iclass 12, count 2 2006.280.08:08:54.67#ibcon#about to read 6, iclass 12, count 2 2006.280.08:08:54.67#ibcon#read 6, iclass 12, count 2 2006.280.08:08:54.67#ibcon#end of sib2, iclass 12, count 2 2006.280.08:08:54.67#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:08:54.67#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:08:54.67#ibcon#[27=AT03-04\r\n] 2006.280.08:08:54.67#ibcon#*before write, iclass 12, count 2 2006.280.08:08:54.67#ibcon#enter sib2, iclass 12, count 2 2006.280.08:08:54.67#ibcon#flushed, iclass 12, count 2 2006.280.08:08:54.67#ibcon#about to write, iclass 12, count 2 2006.280.08:08:54.67#ibcon#wrote, iclass 12, count 2 2006.280.08:08:54.67#ibcon#about to read 3, iclass 12, count 2 2006.280.08:08:54.70#ibcon#read 3, iclass 12, count 2 2006.280.08:08:54.70#ibcon#about to read 4, iclass 12, count 2 2006.280.08:08:54.70#ibcon#read 4, iclass 12, count 2 2006.280.08:08:54.70#ibcon#about to read 5, iclass 12, count 2 2006.280.08:08:54.70#ibcon#read 5, iclass 12, count 2 2006.280.08:08:54.70#ibcon#about to read 6, iclass 12, count 2 2006.280.08:08:54.70#ibcon#read 6, iclass 12, count 2 2006.280.08:08:54.70#ibcon#end of sib2, iclass 12, count 2 2006.280.08:08:54.70#ibcon#*after write, iclass 12, count 2 2006.280.08:08:54.70#ibcon#*before return 0, iclass 12, count 2 2006.280.08:08:54.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:54.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:08:54.70#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:08:54.70#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:54.70#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:54.82#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:54.82#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:54.82#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:08:54.82#ibcon#first serial, iclass 12, count 0 2006.280.08:08:54.82#ibcon#enter sib2, iclass 12, count 0 2006.280.08:08:54.82#ibcon#flushed, iclass 12, count 0 2006.280.08:08:54.82#ibcon#about to write, iclass 12, count 0 2006.280.08:08:54.82#ibcon#wrote, iclass 12, count 0 2006.280.08:08:54.82#ibcon#about to read 3, iclass 12, count 0 2006.280.08:08:54.84#ibcon#read 3, iclass 12, count 0 2006.280.08:08:54.84#ibcon#about to read 4, iclass 12, count 0 2006.280.08:08:54.84#ibcon#read 4, iclass 12, count 0 2006.280.08:08:54.84#ibcon#about to read 5, iclass 12, count 0 2006.280.08:08:54.84#ibcon#read 5, iclass 12, count 0 2006.280.08:08:54.84#ibcon#about to read 6, iclass 12, count 0 2006.280.08:08:54.84#ibcon#read 6, iclass 12, count 0 2006.280.08:08:54.84#ibcon#end of sib2, iclass 12, count 0 2006.280.08:08:54.84#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:08:54.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:08:54.84#ibcon#[27=USB\r\n] 2006.280.08:08:54.84#ibcon#*before write, iclass 12, count 0 2006.280.08:08:54.84#ibcon#enter sib2, iclass 12, count 0 2006.280.08:08:54.84#ibcon#flushed, iclass 12, count 0 2006.280.08:08:54.84#ibcon#about to write, iclass 12, count 0 2006.280.08:08:54.84#ibcon#wrote, iclass 12, count 0 2006.280.08:08:54.84#ibcon#about to read 3, iclass 12, count 0 2006.280.08:08:54.87#ibcon#read 3, iclass 12, count 0 2006.280.08:08:54.87#ibcon#about to read 4, iclass 12, count 0 2006.280.08:08:54.87#ibcon#read 4, iclass 12, count 0 2006.280.08:08:54.87#ibcon#about to read 5, iclass 12, count 0 2006.280.08:08:54.87#ibcon#read 5, iclass 12, count 0 2006.280.08:08:54.87#ibcon#about to read 6, iclass 12, count 0 2006.280.08:08:54.87#ibcon#read 6, iclass 12, count 0 2006.280.08:08:54.87#ibcon#end of sib2, iclass 12, count 0 2006.280.08:08:54.87#ibcon#*after write, iclass 12, count 0 2006.280.08:08:54.87#ibcon#*before return 0, iclass 12, count 0 2006.280.08:08:54.87#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:54.87#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:08:54.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:08:54.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:08:54.87$vc4f8/vblo=4,712.99 2006.280.08:08:54.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.08:08:54.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.08:08:54.87#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:54.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:54.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:54.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:54.87#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:08:54.87#ibcon#first serial, iclass 14, count 0 2006.280.08:08:54.87#ibcon#enter sib2, iclass 14, count 0 2006.280.08:08:54.87#ibcon#flushed, iclass 14, count 0 2006.280.08:08:54.87#ibcon#about to write, iclass 14, count 0 2006.280.08:08:54.87#ibcon#wrote, iclass 14, count 0 2006.280.08:08:54.87#ibcon#about to read 3, iclass 14, count 0 2006.280.08:08:54.89#ibcon#read 3, iclass 14, count 0 2006.280.08:08:54.89#ibcon#about to read 4, iclass 14, count 0 2006.280.08:08:54.89#ibcon#read 4, iclass 14, count 0 2006.280.08:08:54.89#ibcon#about to read 5, iclass 14, count 0 2006.280.08:08:54.89#ibcon#read 5, iclass 14, count 0 2006.280.08:08:54.89#ibcon#about to read 6, iclass 14, count 0 2006.280.08:08:54.89#ibcon#read 6, iclass 14, count 0 2006.280.08:08:54.89#ibcon#end of sib2, iclass 14, count 0 2006.280.08:08:54.89#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:08:54.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:08:54.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:08:54.89#ibcon#*before write, iclass 14, count 0 2006.280.08:08:54.89#ibcon#enter sib2, iclass 14, count 0 2006.280.08:08:54.89#ibcon#flushed, iclass 14, count 0 2006.280.08:08:54.89#ibcon#about to write, iclass 14, count 0 2006.280.08:08:54.89#ibcon#wrote, iclass 14, count 0 2006.280.08:08:54.89#ibcon#about to read 3, iclass 14, count 0 2006.280.08:08:54.93#ibcon#read 3, iclass 14, count 0 2006.280.08:08:54.93#ibcon#about to read 4, iclass 14, count 0 2006.280.08:08:54.93#ibcon#read 4, iclass 14, count 0 2006.280.08:08:54.93#ibcon#about to read 5, iclass 14, count 0 2006.280.08:08:54.93#ibcon#read 5, iclass 14, count 0 2006.280.08:08:54.93#ibcon#about to read 6, iclass 14, count 0 2006.280.08:08:54.93#ibcon#read 6, iclass 14, count 0 2006.280.08:08:54.93#ibcon#end of sib2, iclass 14, count 0 2006.280.08:08:54.93#ibcon#*after write, iclass 14, count 0 2006.280.08:08:54.93#ibcon#*before return 0, iclass 14, count 0 2006.280.08:08:54.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:54.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:08:54.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:08:54.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:08:54.93$vc4f8/vb=4,4 2006.280.08:08:54.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.08:08:54.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.08:08:54.93#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:54.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:54.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:54.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:54.99#ibcon#enter wrdev, iclass 16, count 2 2006.280.08:08:54.99#ibcon#first serial, iclass 16, count 2 2006.280.08:08:54.99#ibcon#enter sib2, iclass 16, count 2 2006.280.08:08:54.99#ibcon#flushed, iclass 16, count 2 2006.280.08:08:54.99#ibcon#about to write, iclass 16, count 2 2006.280.08:08:54.99#ibcon#wrote, iclass 16, count 2 2006.280.08:08:54.99#ibcon#about to read 3, iclass 16, count 2 2006.280.08:08:55.01#ibcon#read 3, iclass 16, count 2 2006.280.08:08:55.01#ibcon#about to read 4, iclass 16, count 2 2006.280.08:08:55.01#ibcon#read 4, iclass 16, count 2 2006.280.08:08:55.01#ibcon#about to read 5, iclass 16, count 2 2006.280.08:08:55.01#ibcon#read 5, iclass 16, count 2 2006.280.08:08:55.01#ibcon#about to read 6, iclass 16, count 2 2006.280.08:08:55.01#ibcon#read 6, iclass 16, count 2 2006.280.08:08:55.01#ibcon#end of sib2, iclass 16, count 2 2006.280.08:08:55.01#ibcon#*mode == 0, iclass 16, count 2 2006.280.08:08:55.01#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.08:08:55.01#ibcon#[27=AT04-04\r\n] 2006.280.08:08:55.01#ibcon#*before write, iclass 16, count 2 2006.280.08:08:55.01#ibcon#enter sib2, iclass 16, count 2 2006.280.08:08:55.01#ibcon#flushed, iclass 16, count 2 2006.280.08:08:55.01#ibcon#about to write, iclass 16, count 2 2006.280.08:08:55.01#ibcon#wrote, iclass 16, count 2 2006.280.08:08:55.01#ibcon#about to read 3, iclass 16, count 2 2006.280.08:08:55.04#ibcon#read 3, iclass 16, count 2 2006.280.08:08:55.04#ibcon#about to read 4, iclass 16, count 2 2006.280.08:08:55.04#ibcon#read 4, iclass 16, count 2 2006.280.08:08:55.04#ibcon#about to read 5, iclass 16, count 2 2006.280.08:08:55.04#ibcon#read 5, iclass 16, count 2 2006.280.08:08:55.04#ibcon#about to read 6, iclass 16, count 2 2006.280.08:08:55.04#ibcon#read 6, iclass 16, count 2 2006.280.08:08:55.04#ibcon#end of sib2, iclass 16, count 2 2006.280.08:08:55.04#ibcon#*after write, iclass 16, count 2 2006.280.08:08:55.04#ibcon#*before return 0, iclass 16, count 2 2006.280.08:08:55.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:55.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:08:55.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.08:08:55.04#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:55.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:55.16#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:55.16#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:55.16#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:08:55.16#ibcon#first serial, iclass 16, count 0 2006.280.08:08:55.16#ibcon#enter sib2, iclass 16, count 0 2006.280.08:08:55.16#ibcon#flushed, iclass 16, count 0 2006.280.08:08:55.16#ibcon#about to write, iclass 16, count 0 2006.280.08:08:55.16#ibcon#wrote, iclass 16, count 0 2006.280.08:08:55.16#ibcon#about to read 3, iclass 16, count 0 2006.280.08:08:55.18#ibcon#read 3, iclass 16, count 0 2006.280.08:08:55.18#ibcon#about to read 4, iclass 16, count 0 2006.280.08:08:55.18#ibcon#read 4, iclass 16, count 0 2006.280.08:08:55.18#ibcon#about to read 5, iclass 16, count 0 2006.280.08:08:55.18#ibcon#read 5, iclass 16, count 0 2006.280.08:08:55.18#ibcon#about to read 6, iclass 16, count 0 2006.280.08:08:55.18#ibcon#read 6, iclass 16, count 0 2006.280.08:08:55.18#ibcon#end of sib2, iclass 16, count 0 2006.280.08:08:55.18#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:08:55.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:08:55.18#ibcon#[27=USB\r\n] 2006.280.08:08:55.18#ibcon#*before write, iclass 16, count 0 2006.280.08:08:55.18#ibcon#enter sib2, iclass 16, count 0 2006.280.08:08:55.18#ibcon#flushed, iclass 16, count 0 2006.280.08:08:55.18#ibcon#about to write, iclass 16, count 0 2006.280.08:08:55.18#ibcon#wrote, iclass 16, count 0 2006.280.08:08:55.18#ibcon#about to read 3, iclass 16, count 0 2006.280.08:08:55.21#ibcon#read 3, iclass 16, count 0 2006.280.08:08:55.21#ibcon#about to read 4, iclass 16, count 0 2006.280.08:08:55.21#ibcon#read 4, iclass 16, count 0 2006.280.08:08:55.21#ibcon#about to read 5, iclass 16, count 0 2006.280.08:08:55.21#ibcon#read 5, iclass 16, count 0 2006.280.08:08:55.21#ibcon#about to read 6, iclass 16, count 0 2006.280.08:08:55.21#ibcon#read 6, iclass 16, count 0 2006.280.08:08:55.21#ibcon#end of sib2, iclass 16, count 0 2006.280.08:08:55.21#ibcon#*after write, iclass 16, count 0 2006.280.08:08:55.21#ibcon#*before return 0, iclass 16, count 0 2006.280.08:08:55.21#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:55.21#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:08:55.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:08:55.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:08:55.21$vc4f8/vblo=5,744.99 2006.280.08:08:55.21#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:08:55.21#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:08:55.21#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:55.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:55.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:55.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:55.21#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:08:55.21#ibcon#first serial, iclass 18, count 0 2006.280.08:08:55.21#ibcon#enter sib2, iclass 18, count 0 2006.280.08:08:55.21#ibcon#flushed, iclass 18, count 0 2006.280.08:08:55.21#ibcon#about to write, iclass 18, count 0 2006.280.08:08:55.21#ibcon#wrote, iclass 18, count 0 2006.280.08:08:55.21#ibcon#about to read 3, iclass 18, count 0 2006.280.08:08:55.23#ibcon#read 3, iclass 18, count 0 2006.280.08:08:55.23#ibcon#about to read 4, iclass 18, count 0 2006.280.08:08:55.23#ibcon#read 4, iclass 18, count 0 2006.280.08:08:55.23#ibcon#about to read 5, iclass 18, count 0 2006.280.08:08:55.23#ibcon#read 5, iclass 18, count 0 2006.280.08:08:55.23#ibcon#about to read 6, iclass 18, count 0 2006.280.08:08:55.23#ibcon#read 6, iclass 18, count 0 2006.280.08:08:55.23#ibcon#end of sib2, iclass 18, count 0 2006.280.08:08:55.23#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:08:55.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:08:55.23#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:08:55.23#ibcon#*before write, iclass 18, count 0 2006.280.08:08:55.23#ibcon#enter sib2, iclass 18, count 0 2006.280.08:08:55.23#ibcon#flushed, iclass 18, count 0 2006.280.08:08:55.23#ibcon#about to write, iclass 18, count 0 2006.280.08:08:55.23#ibcon#wrote, iclass 18, count 0 2006.280.08:08:55.23#ibcon#about to read 3, iclass 18, count 0 2006.280.08:08:55.27#ibcon#read 3, iclass 18, count 0 2006.280.08:08:55.27#ibcon#about to read 4, iclass 18, count 0 2006.280.08:08:55.27#ibcon#read 4, iclass 18, count 0 2006.280.08:08:55.27#ibcon#about to read 5, iclass 18, count 0 2006.280.08:08:55.27#ibcon#read 5, iclass 18, count 0 2006.280.08:08:55.27#ibcon#about to read 6, iclass 18, count 0 2006.280.08:08:55.27#ibcon#read 6, iclass 18, count 0 2006.280.08:08:55.27#ibcon#end of sib2, iclass 18, count 0 2006.280.08:08:55.27#ibcon#*after write, iclass 18, count 0 2006.280.08:08:55.27#ibcon#*before return 0, iclass 18, count 0 2006.280.08:08:55.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:55.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:08:55.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:08:55.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:08:55.27$vc4f8/vb=5,4 2006.280.08:08:55.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:08:55.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:08:55.29#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:55.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:55.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:55.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:55.32#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:08:55.32#ibcon#first serial, iclass 20, count 2 2006.280.08:08:55.32#ibcon#enter sib2, iclass 20, count 2 2006.280.08:08:55.32#ibcon#flushed, iclass 20, count 2 2006.280.08:08:55.32#ibcon#about to write, iclass 20, count 2 2006.280.08:08:55.32#ibcon#wrote, iclass 20, count 2 2006.280.08:08:55.32#ibcon#about to read 3, iclass 20, count 2 2006.280.08:08:55.34#ibcon#read 3, iclass 20, count 2 2006.280.08:08:55.34#ibcon#about to read 4, iclass 20, count 2 2006.280.08:08:55.34#ibcon#read 4, iclass 20, count 2 2006.280.08:08:55.34#ibcon#about to read 5, iclass 20, count 2 2006.280.08:08:55.34#ibcon#read 5, iclass 20, count 2 2006.280.08:08:55.34#ibcon#about to read 6, iclass 20, count 2 2006.280.08:08:55.34#ibcon#read 6, iclass 20, count 2 2006.280.08:08:55.34#ibcon#end of sib2, iclass 20, count 2 2006.280.08:08:55.34#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:08:55.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:08:55.34#ibcon#[27=AT05-04\r\n] 2006.280.08:08:55.34#ibcon#*before write, iclass 20, count 2 2006.280.08:08:55.34#ibcon#enter sib2, iclass 20, count 2 2006.280.08:08:55.34#ibcon#flushed, iclass 20, count 2 2006.280.08:08:55.34#ibcon#about to write, iclass 20, count 2 2006.280.08:08:55.34#ibcon#wrote, iclass 20, count 2 2006.280.08:08:55.34#ibcon#about to read 3, iclass 20, count 2 2006.280.08:08:55.37#ibcon#read 3, iclass 20, count 2 2006.280.08:08:55.37#ibcon#about to read 4, iclass 20, count 2 2006.280.08:08:55.37#ibcon#read 4, iclass 20, count 2 2006.280.08:08:55.37#ibcon#about to read 5, iclass 20, count 2 2006.280.08:08:55.37#ibcon#read 5, iclass 20, count 2 2006.280.08:08:55.37#ibcon#about to read 6, iclass 20, count 2 2006.280.08:08:55.37#ibcon#read 6, iclass 20, count 2 2006.280.08:08:55.37#ibcon#end of sib2, iclass 20, count 2 2006.280.08:08:55.37#ibcon#*after write, iclass 20, count 2 2006.280.08:08:55.37#ibcon#*before return 0, iclass 20, count 2 2006.280.08:08:55.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:55.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:08:55.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:08:55.37#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:55.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:55.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:55.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:55.49#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:08:55.49#ibcon#first serial, iclass 20, count 0 2006.280.08:08:55.49#ibcon#enter sib2, iclass 20, count 0 2006.280.08:08:55.49#ibcon#flushed, iclass 20, count 0 2006.280.08:08:55.49#ibcon#about to write, iclass 20, count 0 2006.280.08:08:55.49#ibcon#wrote, iclass 20, count 0 2006.280.08:08:55.49#ibcon#about to read 3, iclass 20, count 0 2006.280.08:08:55.51#ibcon#read 3, iclass 20, count 0 2006.280.08:08:55.51#ibcon#about to read 4, iclass 20, count 0 2006.280.08:08:55.51#ibcon#read 4, iclass 20, count 0 2006.280.08:08:55.51#ibcon#about to read 5, iclass 20, count 0 2006.280.08:08:55.51#ibcon#read 5, iclass 20, count 0 2006.280.08:08:55.51#ibcon#about to read 6, iclass 20, count 0 2006.280.08:08:55.51#ibcon#read 6, iclass 20, count 0 2006.280.08:08:55.51#ibcon#end of sib2, iclass 20, count 0 2006.280.08:08:55.51#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:08:55.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:08:55.51#ibcon#[27=USB\r\n] 2006.280.08:08:55.51#ibcon#*before write, iclass 20, count 0 2006.280.08:08:55.51#ibcon#enter sib2, iclass 20, count 0 2006.280.08:08:55.51#ibcon#flushed, iclass 20, count 0 2006.280.08:08:55.51#ibcon#about to write, iclass 20, count 0 2006.280.08:08:55.51#ibcon#wrote, iclass 20, count 0 2006.280.08:08:55.51#ibcon#about to read 3, iclass 20, count 0 2006.280.08:08:55.54#ibcon#read 3, iclass 20, count 0 2006.280.08:08:55.54#ibcon#about to read 4, iclass 20, count 0 2006.280.08:08:55.54#ibcon#read 4, iclass 20, count 0 2006.280.08:08:55.54#ibcon#about to read 5, iclass 20, count 0 2006.280.08:08:55.54#ibcon#read 5, iclass 20, count 0 2006.280.08:08:55.54#ibcon#about to read 6, iclass 20, count 0 2006.280.08:08:55.54#ibcon#read 6, iclass 20, count 0 2006.280.08:08:55.54#ibcon#end of sib2, iclass 20, count 0 2006.280.08:08:55.54#ibcon#*after write, iclass 20, count 0 2006.280.08:08:55.54#ibcon#*before return 0, iclass 20, count 0 2006.280.08:08:55.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:55.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:08:55.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:08:55.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:08:55.54$vc4f8/vblo=6,752.99 2006.280.08:08:55.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:08:55.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:08:55.54#ibcon#ireg 17 cls_cnt 0 2006.280.08:08:55.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:55.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:55.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:55.54#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:08:55.54#ibcon#first serial, iclass 22, count 0 2006.280.08:08:55.54#ibcon#enter sib2, iclass 22, count 0 2006.280.08:08:55.54#ibcon#flushed, iclass 22, count 0 2006.280.08:08:55.54#ibcon#about to write, iclass 22, count 0 2006.280.08:08:55.54#ibcon#wrote, iclass 22, count 0 2006.280.08:08:55.54#ibcon#about to read 3, iclass 22, count 0 2006.280.08:08:55.56#ibcon#read 3, iclass 22, count 0 2006.280.08:08:55.56#ibcon#about to read 4, iclass 22, count 0 2006.280.08:08:55.56#ibcon#read 4, iclass 22, count 0 2006.280.08:08:55.56#ibcon#about to read 5, iclass 22, count 0 2006.280.08:08:55.56#ibcon#read 5, iclass 22, count 0 2006.280.08:08:55.56#ibcon#about to read 6, iclass 22, count 0 2006.280.08:08:55.56#ibcon#read 6, iclass 22, count 0 2006.280.08:08:55.56#ibcon#end of sib2, iclass 22, count 0 2006.280.08:08:55.56#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:08:55.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:08:55.56#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:08:55.56#ibcon#*before write, iclass 22, count 0 2006.280.08:08:55.56#ibcon#enter sib2, iclass 22, count 0 2006.280.08:08:55.56#ibcon#flushed, iclass 22, count 0 2006.280.08:08:55.56#ibcon#about to write, iclass 22, count 0 2006.280.08:08:55.56#ibcon#wrote, iclass 22, count 0 2006.280.08:08:55.56#ibcon#about to read 3, iclass 22, count 0 2006.280.08:08:55.60#ibcon#read 3, iclass 22, count 0 2006.280.08:08:55.60#ibcon#about to read 4, iclass 22, count 0 2006.280.08:08:55.60#ibcon#read 4, iclass 22, count 0 2006.280.08:08:55.60#ibcon#about to read 5, iclass 22, count 0 2006.280.08:08:55.60#ibcon#read 5, iclass 22, count 0 2006.280.08:08:55.60#ibcon#about to read 6, iclass 22, count 0 2006.280.08:08:55.60#ibcon#read 6, iclass 22, count 0 2006.280.08:08:55.60#ibcon#end of sib2, iclass 22, count 0 2006.280.08:08:55.60#ibcon#*after write, iclass 22, count 0 2006.280.08:08:55.60#ibcon#*before return 0, iclass 22, count 0 2006.280.08:08:55.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:55.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:08:55.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:08:55.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:08:55.60$vc4f8/vb=6,4 2006.280.08:08:55.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:08:55.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:08:55.60#ibcon#ireg 11 cls_cnt 2 2006.280.08:08:55.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:55.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:55.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:55.66#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:08:55.66#ibcon#first serial, iclass 24, count 2 2006.280.08:08:55.66#ibcon#enter sib2, iclass 24, count 2 2006.280.08:08:55.66#ibcon#flushed, iclass 24, count 2 2006.280.08:08:55.66#ibcon#about to write, iclass 24, count 2 2006.280.08:08:55.66#ibcon#wrote, iclass 24, count 2 2006.280.08:08:55.66#ibcon#about to read 3, iclass 24, count 2 2006.280.08:08:55.68#ibcon#read 3, iclass 24, count 2 2006.280.08:08:55.68#ibcon#about to read 4, iclass 24, count 2 2006.280.08:08:55.68#ibcon#read 4, iclass 24, count 2 2006.280.08:08:55.68#ibcon#about to read 5, iclass 24, count 2 2006.280.08:08:55.68#ibcon#read 5, iclass 24, count 2 2006.280.08:08:55.68#ibcon#about to read 6, iclass 24, count 2 2006.280.08:08:55.68#ibcon#read 6, iclass 24, count 2 2006.280.08:08:55.68#ibcon#end of sib2, iclass 24, count 2 2006.280.08:08:55.68#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:08:55.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:08:55.68#ibcon#[27=AT06-04\r\n] 2006.280.08:08:55.68#ibcon#*before write, iclass 24, count 2 2006.280.08:08:55.68#ibcon#enter sib2, iclass 24, count 2 2006.280.08:08:55.68#ibcon#flushed, iclass 24, count 2 2006.280.08:08:55.68#ibcon#about to write, iclass 24, count 2 2006.280.08:08:55.68#ibcon#wrote, iclass 24, count 2 2006.280.08:08:55.68#ibcon#about to read 3, iclass 24, count 2 2006.280.08:08:55.72#ibcon#read 3, iclass 24, count 2 2006.280.08:08:55.72#ibcon#about to read 4, iclass 24, count 2 2006.280.08:08:55.72#ibcon#read 4, iclass 24, count 2 2006.280.08:08:55.72#ibcon#about to read 5, iclass 24, count 2 2006.280.08:08:55.72#ibcon#read 5, iclass 24, count 2 2006.280.08:08:55.72#ibcon#about to read 6, iclass 24, count 2 2006.280.08:08:55.72#ibcon#read 6, iclass 24, count 2 2006.280.08:08:55.72#ibcon#end of sib2, iclass 24, count 2 2006.280.08:08:55.72#ibcon#*after write, iclass 24, count 2 2006.280.08:08:55.72#ibcon#*before return 0, iclass 24, count 2 2006.280.08:08:55.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:55.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:08:55.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:08:55.72#ibcon#ireg 7 cls_cnt 0 2006.280.08:08:55.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:55.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:55.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:55.84#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:08:55.84#ibcon#first serial, iclass 24, count 0 2006.280.08:08:55.84#ibcon#enter sib2, iclass 24, count 0 2006.280.08:08:55.84#ibcon#flushed, iclass 24, count 0 2006.280.08:08:55.84#ibcon#about to write, iclass 24, count 0 2006.280.08:08:55.84#ibcon#wrote, iclass 24, count 0 2006.280.08:08:55.84#ibcon#about to read 3, iclass 24, count 0 2006.280.08:08:55.86#ibcon#read 3, iclass 24, count 0 2006.280.08:08:55.86#ibcon#about to read 4, iclass 24, count 0 2006.280.08:08:55.86#ibcon#read 4, iclass 24, count 0 2006.280.08:08:55.86#ibcon#about to read 5, iclass 24, count 0 2006.280.08:08:55.86#ibcon#read 5, iclass 24, count 0 2006.280.08:08:55.86#ibcon#about to read 6, iclass 24, count 0 2006.280.08:08:55.86#ibcon#read 6, iclass 24, count 0 2006.280.08:08:55.86#ibcon#end of sib2, iclass 24, count 0 2006.280.08:08:55.86#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:08:55.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:08:55.86#ibcon#[27=USB\r\n] 2006.280.08:08:55.86#ibcon#*before write, iclass 24, count 0 2006.280.08:08:55.86#ibcon#enter sib2, iclass 24, count 0 2006.280.08:08:55.86#ibcon#flushed, iclass 24, count 0 2006.280.08:08:55.86#ibcon#about to write, iclass 24, count 0 2006.280.08:08:55.86#ibcon#wrote, iclass 24, count 0 2006.280.08:08:55.86#ibcon#about to read 3, iclass 24, count 0 2006.280.08:08:55.89#ibcon#read 3, iclass 24, count 0 2006.280.08:08:55.89#ibcon#about to read 4, iclass 24, count 0 2006.280.08:08:55.89#ibcon#read 4, iclass 24, count 0 2006.280.08:08:55.89#ibcon#about to read 5, iclass 24, count 0 2006.280.08:08:55.89#ibcon#read 5, iclass 24, count 0 2006.280.08:08:55.89#ibcon#about to read 6, iclass 24, count 0 2006.280.08:08:55.89#ibcon#read 6, iclass 24, count 0 2006.280.08:08:55.89#ibcon#end of sib2, iclass 24, count 0 2006.280.08:08:55.89#ibcon#*after write, iclass 24, count 0 2006.280.08:08:55.89#ibcon#*before return 0, iclass 24, count 0 2006.280.08:08:55.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:55.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:08:55.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:08:55.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:08:55.89$vc4f8/vabw=wide 2006.280.08:08:55.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:08:55.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:08:55.89#ibcon#ireg 8 cls_cnt 0 2006.280.08:08:55.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:55.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:55.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:55.89#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:08:55.89#ibcon#first serial, iclass 26, count 0 2006.280.08:08:55.89#ibcon#enter sib2, iclass 26, count 0 2006.280.08:08:55.89#ibcon#flushed, iclass 26, count 0 2006.280.08:08:55.89#ibcon#about to write, iclass 26, count 0 2006.280.08:08:55.89#ibcon#wrote, iclass 26, count 0 2006.280.08:08:55.89#ibcon#about to read 3, iclass 26, count 0 2006.280.08:08:55.91#ibcon#read 3, iclass 26, count 0 2006.280.08:08:55.91#ibcon#about to read 4, iclass 26, count 0 2006.280.08:08:55.91#ibcon#read 4, iclass 26, count 0 2006.280.08:08:55.91#ibcon#about to read 5, iclass 26, count 0 2006.280.08:08:55.91#ibcon#read 5, iclass 26, count 0 2006.280.08:08:55.91#ibcon#about to read 6, iclass 26, count 0 2006.280.08:08:55.91#ibcon#read 6, iclass 26, count 0 2006.280.08:08:55.91#ibcon#end of sib2, iclass 26, count 0 2006.280.08:08:55.91#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:08:55.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:08:55.91#ibcon#[25=BW32\r\n] 2006.280.08:08:55.91#ibcon#*before write, iclass 26, count 0 2006.280.08:08:55.91#ibcon#enter sib2, iclass 26, count 0 2006.280.08:08:55.91#ibcon#flushed, iclass 26, count 0 2006.280.08:08:55.91#ibcon#about to write, iclass 26, count 0 2006.280.08:08:55.91#ibcon#wrote, iclass 26, count 0 2006.280.08:08:55.91#ibcon#about to read 3, iclass 26, count 0 2006.280.08:08:55.94#ibcon#read 3, iclass 26, count 0 2006.280.08:08:55.94#ibcon#about to read 4, iclass 26, count 0 2006.280.08:08:55.94#ibcon#read 4, iclass 26, count 0 2006.280.08:08:55.94#ibcon#about to read 5, iclass 26, count 0 2006.280.08:08:55.94#ibcon#read 5, iclass 26, count 0 2006.280.08:08:55.94#ibcon#about to read 6, iclass 26, count 0 2006.280.08:08:55.94#ibcon#read 6, iclass 26, count 0 2006.280.08:08:55.94#ibcon#end of sib2, iclass 26, count 0 2006.280.08:08:55.94#ibcon#*after write, iclass 26, count 0 2006.280.08:08:55.94#ibcon#*before return 0, iclass 26, count 0 2006.280.08:08:55.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:55.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:08:55.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:08:55.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:08:55.94$vc4f8/vbbw=wide 2006.280.08:08:55.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:08:55.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:08:55.94#ibcon#ireg 8 cls_cnt 0 2006.280.08:08:55.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:08:56.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:08:56.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:08:56.01#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:08:56.01#ibcon#first serial, iclass 28, count 0 2006.280.08:08:56.01#ibcon#enter sib2, iclass 28, count 0 2006.280.08:08:56.01#ibcon#flushed, iclass 28, count 0 2006.280.08:08:56.01#ibcon#about to write, iclass 28, count 0 2006.280.08:08:56.01#ibcon#wrote, iclass 28, count 0 2006.280.08:08:56.01#ibcon#about to read 3, iclass 28, count 0 2006.280.08:08:56.03#ibcon#read 3, iclass 28, count 0 2006.280.08:08:56.03#ibcon#about to read 4, iclass 28, count 0 2006.280.08:08:56.03#ibcon#read 4, iclass 28, count 0 2006.280.08:08:56.03#ibcon#about to read 5, iclass 28, count 0 2006.280.08:08:56.03#ibcon#read 5, iclass 28, count 0 2006.280.08:08:56.03#ibcon#about to read 6, iclass 28, count 0 2006.280.08:08:56.03#ibcon#read 6, iclass 28, count 0 2006.280.08:08:56.03#ibcon#end of sib2, iclass 28, count 0 2006.280.08:08:56.03#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:08:56.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:08:56.03#ibcon#[27=BW32\r\n] 2006.280.08:08:56.03#ibcon#*before write, iclass 28, count 0 2006.280.08:08:56.03#ibcon#enter sib2, iclass 28, count 0 2006.280.08:08:56.03#ibcon#flushed, iclass 28, count 0 2006.280.08:08:56.03#ibcon#about to write, iclass 28, count 0 2006.280.08:08:56.03#ibcon#wrote, iclass 28, count 0 2006.280.08:08:56.03#ibcon#about to read 3, iclass 28, count 0 2006.280.08:08:56.06#ibcon#read 3, iclass 28, count 0 2006.280.08:08:56.06#ibcon#about to read 4, iclass 28, count 0 2006.280.08:08:56.06#ibcon#read 4, iclass 28, count 0 2006.280.08:08:56.06#ibcon#about to read 5, iclass 28, count 0 2006.280.08:08:56.06#ibcon#read 5, iclass 28, count 0 2006.280.08:08:56.06#ibcon#about to read 6, iclass 28, count 0 2006.280.08:08:56.06#ibcon#read 6, iclass 28, count 0 2006.280.08:08:56.06#ibcon#end of sib2, iclass 28, count 0 2006.280.08:08:56.06#ibcon#*after write, iclass 28, count 0 2006.280.08:08:56.06#ibcon#*before return 0, iclass 28, count 0 2006.280.08:08:56.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:08:56.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:08:56.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:08:56.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:08:56.06$4f8m12a/ifd4f 2006.280.08:08:56.06$ifd4f/lo= 2006.280.08:08:56.06$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:08:56.06$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:08:56.06$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:08:56.06$ifd4f/patch= 2006.280.08:08:56.06$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:08:56.06$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:08:56.06$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:08:56.06$4f8m12a/"form=m,16.000,1:2 2006.280.08:08:56.06$4f8m12a/"tpicd 2006.280.08:08:56.06$4f8m12a/echo=off 2006.280.08:08:56.06$4f8m12a/xlog=off 2006.280.08:08:56.06:!2006.280.08:09:20 2006.280.08:09:04.13#trakl#Source acquired 2006.280.08:09:05.13#flagr#flagr/antenna,acquired 2006.280.08:09:20.00:preob 2006.280.08:09:21.13/onsource/TRACKING 2006.280.08:09:21.13:!2006.280.08:09:30 2006.280.08:09:30.00:data_valid=on 2006.280.08:09:30.00:midob 2006.280.08:09:30.13/onsource/TRACKING 2006.280.08:09:30.13/wx/20.52,987.4,62 2006.280.08:09:30.32/cable/+6.4837E-03 2006.280.08:09:31.41/va/01,07,usb,yes,33,35 2006.280.08:09:31.41/va/02,06,usb,yes,31,32 2006.280.08:09:31.41/va/03,06,usb,yes,29,29 2006.280.08:09:31.41/va/04,06,usb,yes,32,35 2006.280.08:09:31.41/va/05,07,usb,yes,30,32 2006.280.08:09:31.41/va/06,06,usb,yes,29,29 2006.280.08:09:31.41/va/07,06,usb,yes,30,30 2006.280.08:09:31.41/va/08,06,usb,yes,32,32 2006.280.08:09:31.64/valo/01,532.99,yes,locked 2006.280.08:09:31.64/valo/02,572.99,yes,locked 2006.280.08:09:31.64/valo/03,672.99,yes,locked 2006.280.08:09:31.64/valo/04,832.99,yes,locked 2006.280.08:09:31.64/valo/05,652.99,yes,locked 2006.280.08:09:31.64/valo/06,772.99,yes,locked 2006.280.08:09:31.64/valo/07,832.99,yes,locked 2006.280.08:09:31.64/valo/08,852.99,yes,locked 2006.280.08:09:32.73/vb/01,04,usb,yes,31,29 2006.280.08:09:32.73/vb/02,05,usb,yes,30,30 2006.280.08:09:32.73/vb/03,04,usb,yes,29,34 2006.280.08:09:32.73/vb/04,04,usb,yes,29,30 2006.280.08:09:32.73/vb/05,04,usb,yes,27,32 2006.280.08:09:32.73/vb/06,04,usb,yes,28,31 2006.280.08:09:32.73/vb/07,04,usb,yes,31,31 2006.280.08:09:32.73/vb/08,04,usb,yes,28,32 2006.280.08:09:32.96/vblo/01,632.99,yes,locked 2006.280.08:09:32.96/vblo/02,640.99,yes,locked 2006.280.08:09:32.96/vblo/03,656.99,yes,locked 2006.280.08:09:32.96/vblo/04,712.99,yes,locked 2006.280.08:09:32.96/vblo/05,744.99,yes,locked 2006.280.08:09:32.96/vblo/06,752.99,yes,locked 2006.280.08:09:32.96/vblo/07,734.99,yes,locked 2006.280.08:09:32.96/vblo/08,744.99,yes,locked 2006.280.08:09:33.11/vabw/8 2006.280.08:09:33.26/vbbw/8 2006.280.08:09:33.35/xfe/off,on,12.0 2006.280.08:09:33.72/ifatt/23,28,28,28 2006.280.08:09:34.08/fmout-gps/S +3.18E-07 2006.280.08:09:34.10:!2006.280.08:10:30 2006.280.08:10:30.01:data_valid=off 2006.280.08:10:30.01:postob 2006.280.08:10:30.20/cable/+6.4818E-03 2006.280.08:10:30.20/wx/20.48,987.4,61 2006.280.08:10:31.08/fmout-gps/S +3.17E-07 2006.280.08:10:31.08:scan_name=280-0811,k06280,60 2006.280.08:10:31.08:source=0133+476,013658.59,475129.1,2000.0,cw 2006.280.08:10:31.14#flagr#flagr/antenna,new-source 2006.280.08:10:32.14:checkk5 2006.280.08:10:32.55/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:10:33.05/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:10:33.52/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:10:34.09/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:10:34.78/chk_obsdata//k5ts1/T2800809??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:10:35.25/chk_obsdata//k5ts2/T2800809??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:10:35.65/chk_obsdata//k5ts3/T2800809??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:10:36.33/chk_obsdata//k5ts4/T2800809??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:10:37.26/k5log//k5ts1_log_newline 2006.280.08:10:38.33/k5log//k5ts2_log_newline 2006.280.08:10:39.83/k5log//k5ts3_log_newline 2006.280.08:10:40.84/k5log//k5ts4_log_newline 2006.280.08:10:40.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:10:40.86:4f8m12a=2 2006.280.08:10:40.86$4f8m12a/echo=on 2006.280.08:10:40.86$4f8m12a/pcalon 2006.280.08:10:40.86$pcalon/"no phase cal control is implemented here 2006.280.08:10:40.87$4f8m12a/"tpicd=stop 2006.280.08:10:40.87$4f8m12a/vc4f8 2006.280.08:10:40.87$vc4f8/valo=1,532.99 2006.280.08:10:40.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.08:10:40.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.08:10:40.87#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:40.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:40.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:40.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:40.87#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:10:40.87#ibcon#first serial, iclass 39, count 0 2006.280.08:10:40.87#ibcon#enter sib2, iclass 39, count 0 2006.280.08:10:40.87#ibcon#flushed, iclass 39, count 0 2006.280.08:10:40.87#ibcon#about to write, iclass 39, count 0 2006.280.08:10:40.87#ibcon#wrote, iclass 39, count 0 2006.280.08:10:40.87#ibcon#about to read 3, iclass 39, count 0 2006.280.08:10:40.89#ibcon#read 3, iclass 39, count 0 2006.280.08:10:40.89#ibcon#about to read 4, iclass 39, count 0 2006.280.08:10:40.89#ibcon#read 4, iclass 39, count 0 2006.280.08:10:40.89#ibcon#about to read 5, iclass 39, count 0 2006.280.08:10:40.89#ibcon#read 5, iclass 39, count 0 2006.280.08:10:40.89#ibcon#about to read 6, iclass 39, count 0 2006.280.08:10:40.89#ibcon#read 6, iclass 39, count 0 2006.280.08:10:40.89#ibcon#end of sib2, iclass 39, count 0 2006.280.08:10:40.89#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:10:40.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:10:40.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:10:40.89#ibcon#*before write, iclass 39, count 0 2006.280.08:10:40.89#ibcon#enter sib2, iclass 39, count 0 2006.280.08:10:40.89#ibcon#flushed, iclass 39, count 0 2006.280.08:10:40.89#ibcon#about to write, iclass 39, count 0 2006.280.08:10:40.89#ibcon#wrote, iclass 39, count 0 2006.280.08:10:40.89#ibcon#about to read 3, iclass 39, count 0 2006.280.08:10:40.94#ibcon#read 3, iclass 39, count 0 2006.280.08:10:40.94#ibcon#about to read 4, iclass 39, count 0 2006.280.08:10:40.94#ibcon#read 4, iclass 39, count 0 2006.280.08:10:40.94#ibcon#about to read 5, iclass 39, count 0 2006.280.08:10:40.94#ibcon#read 5, iclass 39, count 0 2006.280.08:10:40.94#ibcon#about to read 6, iclass 39, count 0 2006.280.08:10:40.94#ibcon#read 6, iclass 39, count 0 2006.280.08:10:40.94#ibcon#end of sib2, iclass 39, count 0 2006.280.08:10:40.94#ibcon#*after write, iclass 39, count 0 2006.280.08:10:40.94#ibcon#*before return 0, iclass 39, count 0 2006.280.08:10:40.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:40.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:40.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:10:40.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:10:40.94$vc4f8/va=1,7 2006.280.08:10:40.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.08:10:40.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.08:10:40.94#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:40.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:40.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:40.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:40.94#ibcon#enter wrdev, iclass 3, count 2 2006.280.08:10:40.94#ibcon#first serial, iclass 3, count 2 2006.280.08:10:40.94#ibcon#enter sib2, iclass 3, count 2 2006.280.08:10:40.94#ibcon#flushed, iclass 3, count 2 2006.280.08:10:40.94#ibcon#about to write, iclass 3, count 2 2006.280.08:10:40.94#ibcon#wrote, iclass 3, count 2 2006.280.08:10:40.94#ibcon#about to read 3, iclass 3, count 2 2006.280.08:10:40.96#ibcon#read 3, iclass 3, count 2 2006.280.08:10:40.96#ibcon#about to read 4, iclass 3, count 2 2006.280.08:10:40.96#ibcon#read 4, iclass 3, count 2 2006.280.08:10:40.96#ibcon#about to read 5, iclass 3, count 2 2006.280.08:10:40.96#ibcon#read 5, iclass 3, count 2 2006.280.08:10:40.96#ibcon#about to read 6, iclass 3, count 2 2006.280.08:10:40.96#ibcon#read 6, iclass 3, count 2 2006.280.08:10:40.96#ibcon#end of sib2, iclass 3, count 2 2006.280.08:10:40.96#ibcon#*mode == 0, iclass 3, count 2 2006.280.08:10:40.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.08:10:40.96#ibcon#[25=AT01-07\r\n] 2006.280.08:10:40.96#ibcon#*before write, iclass 3, count 2 2006.280.08:10:40.96#ibcon#enter sib2, iclass 3, count 2 2006.280.08:10:40.96#ibcon#flushed, iclass 3, count 2 2006.280.08:10:40.96#ibcon#about to write, iclass 3, count 2 2006.280.08:10:40.96#ibcon#wrote, iclass 3, count 2 2006.280.08:10:40.96#ibcon#about to read 3, iclass 3, count 2 2006.280.08:10:40.99#ibcon#read 3, iclass 3, count 2 2006.280.08:10:40.99#ibcon#about to read 4, iclass 3, count 2 2006.280.08:10:40.99#ibcon#read 4, iclass 3, count 2 2006.280.08:10:40.99#ibcon#about to read 5, iclass 3, count 2 2006.280.08:10:40.99#ibcon#read 5, iclass 3, count 2 2006.280.08:10:40.99#ibcon#about to read 6, iclass 3, count 2 2006.280.08:10:40.99#ibcon#read 6, iclass 3, count 2 2006.280.08:10:40.99#ibcon#end of sib2, iclass 3, count 2 2006.280.08:10:40.99#ibcon#*after write, iclass 3, count 2 2006.280.08:10:40.99#ibcon#*before return 0, iclass 3, count 2 2006.280.08:10:40.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:40.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:40.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.08:10:40.99#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:40.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:41.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:41.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:41.11#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:10:41.11#ibcon#first serial, iclass 3, count 0 2006.280.08:10:41.11#ibcon#enter sib2, iclass 3, count 0 2006.280.08:10:41.11#ibcon#flushed, iclass 3, count 0 2006.280.08:10:41.11#ibcon#about to write, iclass 3, count 0 2006.280.08:10:41.11#ibcon#wrote, iclass 3, count 0 2006.280.08:10:41.11#ibcon#about to read 3, iclass 3, count 0 2006.280.08:10:41.13#ibcon#read 3, iclass 3, count 0 2006.280.08:10:41.13#ibcon#about to read 4, iclass 3, count 0 2006.280.08:10:41.13#ibcon#read 4, iclass 3, count 0 2006.280.08:10:41.13#ibcon#about to read 5, iclass 3, count 0 2006.280.08:10:41.13#ibcon#read 5, iclass 3, count 0 2006.280.08:10:41.13#ibcon#about to read 6, iclass 3, count 0 2006.280.08:10:41.13#ibcon#read 6, iclass 3, count 0 2006.280.08:10:41.13#ibcon#end of sib2, iclass 3, count 0 2006.280.08:10:41.13#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:10:41.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:10:41.13#ibcon#[25=USB\r\n] 2006.280.08:10:41.13#ibcon#*before write, iclass 3, count 0 2006.280.08:10:41.13#ibcon#enter sib2, iclass 3, count 0 2006.280.08:10:41.13#ibcon#flushed, iclass 3, count 0 2006.280.08:10:41.13#ibcon#about to write, iclass 3, count 0 2006.280.08:10:41.13#ibcon#wrote, iclass 3, count 0 2006.280.08:10:41.13#ibcon#about to read 3, iclass 3, count 0 2006.280.08:10:41.16#ibcon#read 3, iclass 3, count 0 2006.280.08:10:41.16#ibcon#about to read 4, iclass 3, count 0 2006.280.08:10:41.16#ibcon#read 4, iclass 3, count 0 2006.280.08:10:41.16#ibcon#about to read 5, iclass 3, count 0 2006.280.08:10:41.16#ibcon#read 5, iclass 3, count 0 2006.280.08:10:41.16#ibcon#about to read 6, iclass 3, count 0 2006.280.08:10:41.16#ibcon#read 6, iclass 3, count 0 2006.280.08:10:41.16#ibcon#end of sib2, iclass 3, count 0 2006.280.08:10:41.16#ibcon#*after write, iclass 3, count 0 2006.280.08:10:41.16#ibcon#*before return 0, iclass 3, count 0 2006.280.08:10:41.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:41.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:41.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:10:41.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:10:41.16$vc4f8/valo=2,572.99 2006.280.08:10:41.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.08:10:41.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.08:10:41.16#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:41.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:41.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:41.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:41.16#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:10:41.16#ibcon#first serial, iclass 5, count 0 2006.280.08:10:41.16#ibcon#enter sib2, iclass 5, count 0 2006.280.08:10:41.16#ibcon#flushed, iclass 5, count 0 2006.280.08:10:41.16#ibcon#about to write, iclass 5, count 0 2006.280.08:10:41.16#ibcon#wrote, iclass 5, count 0 2006.280.08:10:41.16#ibcon#about to read 3, iclass 5, count 0 2006.280.08:10:41.18#ibcon#read 3, iclass 5, count 0 2006.280.08:10:41.18#ibcon#about to read 4, iclass 5, count 0 2006.280.08:10:41.18#ibcon#read 4, iclass 5, count 0 2006.280.08:10:41.18#ibcon#about to read 5, iclass 5, count 0 2006.280.08:10:41.18#ibcon#read 5, iclass 5, count 0 2006.280.08:10:41.18#ibcon#about to read 6, iclass 5, count 0 2006.280.08:10:41.18#ibcon#read 6, iclass 5, count 0 2006.280.08:10:41.18#ibcon#end of sib2, iclass 5, count 0 2006.280.08:10:41.18#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:10:41.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:10:41.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:10:41.18#ibcon#*before write, iclass 5, count 0 2006.280.08:10:41.18#ibcon#enter sib2, iclass 5, count 0 2006.280.08:10:41.18#ibcon#flushed, iclass 5, count 0 2006.280.08:10:41.18#ibcon#about to write, iclass 5, count 0 2006.280.08:10:41.18#ibcon#wrote, iclass 5, count 0 2006.280.08:10:41.18#ibcon#about to read 3, iclass 5, count 0 2006.280.08:10:41.22#ibcon#read 3, iclass 5, count 0 2006.280.08:10:41.22#ibcon#about to read 4, iclass 5, count 0 2006.280.08:10:41.22#ibcon#read 4, iclass 5, count 0 2006.280.08:10:41.22#ibcon#about to read 5, iclass 5, count 0 2006.280.08:10:41.22#ibcon#read 5, iclass 5, count 0 2006.280.08:10:41.22#ibcon#about to read 6, iclass 5, count 0 2006.280.08:10:41.22#ibcon#read 6, iclass 5, count 0 2006.280.08:10:41.22#ibcon#end of sib2, iclass 5, count 0 2006.280.08:10:41.22#ibcon#*after write, iclass 5, count 0 2006.280.08:10:41.22#ibcon#*before return 0, iclass 5, count 0 2006.280.08:10:41.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:41.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:41.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:10:41.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:10:41.22$vc4f8/va=2,6 2006.280.08:10:41.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.08:10:41.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.08:10:41.22#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:41.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:41.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:41.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:41.28#ibcon#enter wrdev, iclass 7, count 2 2006.280.08:10:41.28#ibcon#first serial, iclass 7, count 2 2006.280.08:10:41.28#ibcon#enter sib2, iclass 7, count 2 2006.280.08:10:41.28#ibcon#flushed, iclass 7, count 2 2006.280.08:10:41.28#ibcon#about to write, iclass 7, count 2 2006.280.08:10:41.28#ibcon#wrote, iclass 7, count 2 2006.280.08:10:41.28#ibcon#about to read 3, iclass 7, count 2 2006.280.08:10:41.30#ibcon#read 3, iclass 7, count 2 2006.280.08:10:41.30#ibcon#about to read 4, iclass 7, count 2 2006.280.08:10:41.30#ibcon#read 4, iclass 7, count 2 2006.280.08:10:41.30#ibcon#about to read 5, iclass 7, count 2 2006.280.08:10:41.30#ibcon#read 5, iclass 7, count 2 2006.280.08:10:41.30#ibcon#about to read 6, iclass 7, count 2 2006.280.08:10:41.30#ibcon#read 6, iclass 7, count 2 2006.280.08:10:41.30#ibcon#end of sib2, iclass 7, count 2 2006.280.08:10:41.30#ibcon#*mode == 0, iclass 7, count 2 2006.280.08:10:41.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.08:10:41.30#ibcon#[25=AT02-06\r\n] 2006.280.08:10:41.30#ibcon#*before write, iclass 7, count 2 2006.280.08:10:41.30#ibcon#enter sib2, iclass 7, count 2 2006.280.08:10:41.30#ibcon#flushed, iclass 7, count 2 2006.280.08:10:41.30#ibcon#about to write, iclass 7, count 2 2006.280.08:10:41.30#ibcon#wrote, iclass 7, count 2 2006.280.08:10:41.30#ibcon#about to read 3, iclass 7, count 2 2006.280.08:10:41.33#ibcon#read 3, iclass 7, count 2 2006.280.08:10:41.33#ibcon#about to read 4, iclass 7, count 2 2006.280.08:10:41.33#ibcon#read 4, iclass 7, count 2 2006.280.08:10:41.33#ibcon#about to read 5, iclass 7, count 2 2006.280.08:10:41.33#ibcon#read 5, iclass 7, count 2 2006.280.08:10:41.33#ibcon#about to read 6, iclass 7, count 2 2006.280.08:10:41.33#ibcon#read 6, iclass 7, count 2 2006.280.08:10:41.33#ibcon#end of sib2, iclass 7, count 2 2006.280.08:10:41.33#ibcon#*after write, iclass 7, count 2 2006.280.08:10:41.33#ibcon#*before return 0, iclass 7, count 2 2006.280.08:10:41.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:41.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:41.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.08:10:41.33#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:41.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:41.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:41.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:41.45#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:10:41.45#ibcon#first serial, iclass 7, count 0 2006.280.08:10:41.45#ibcon#enter sib2, iclass 7, count 0 2006.280.08:10:41.45#ibcon#flushed, iclass 7, count 0 2006.280.08:10:41.45#ibcon#about to write, iclass 7, count 0 2006.280.08:10:41.45#ibcon#wrote, iclass 7, count 0 2006.280.08:10:41.45#ibcon#about to read 3, iclass 7, count 0 2006.280.08:10:41.47#ibcon#read 3, iclass 7, count 0 2006.280.08:10:41.47#ibcon#about to read 4, iclass 7, count 0 2006.280.08:10:41.47#ibcon#read 4, iclass 7, count 0 2006.280.08:10:41.47#ibcon#about to read 5, iclass 7, count 0 2006.280.08:10:41.47#ibcon#read 5, iclass 7, count 0 2006.280.08:10:41.47#ibcon#about to read 6, iclass 7, count 0 2006.280.08:10:41.47#ibcon#read 6, iclass 7, count 0 2006.280.08:10:41.47#ibcon#end of sib2, iclass 7, count 0 2006.280.08:10:41.47#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:10:41.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:10:41.47#ibcon#[25=USB\r\n] 2006.280.08:10:41.47#ibcon#*before write, iclass 7, count 0 2006.280.08:10:41.47#ibcon#enter sib2, iclass 7, count 0 2006.280.08:10:41.47#ibcon#flushed, iclass 7, count 0 2006.280.08:10:41.47#ibcon#about to write, iclass 7, count 0 2006.280.08:10:41.47#ibcon#wrote, iclass 7, count 0 2006.280.08:10:41.47#ibcon#about to read 3, iclass 7, count 0 2006.280.08:10:41.50#ibcon#read 3, iclass 7, count 0 2006.280.08:10:41.50#ibcon#about to read 4, iclass 7, count 0 2006.280.08:10:41.50#ibcon#read 4, iclass 7, count 0 2006.280.08:10:41.50#ibcon#about to read 5, iclass 7, count 0 2006.280.08:10:41.50#ibcon#read 5, iclass 7, count 0 2006.280.08:10:41.50#ibcon#about to read 6, iclass 7, count 0 2006.280.08:10:41.50#ibcon#read 6, iclass 7, count 0 2006.280.08:10:41.50#ibcon#end of sib2, iclass 7, count 0 2006.280.08:10:41.50#ibcon#*after write, iclass 7, count 0 2006.280.08:10:41.50#ibcon#*before return 0, iclass 7, count 0 2006.280.08:10:41.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:41.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:41.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:10:41.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:10:41.50$vc4f8/valo=3,672.99 2006.280.08:10:41.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.08:10:41.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.08:10:41.50#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:41.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:41.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:41.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:41.50#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:10:41.50#ibcon#first serial, iclass 11, count 0 2006.280.08:10:41.50#ibcon#enter sib2, iclass 11, count 0 2006.280.08:10:41.50#ibcon#flushed, iclass 11, count 0 2006.280.08:10:41.50#ibcon#about to write, iclass 11, count 0 2006.280.08:10:41.50#ibcon#wrote, iclass 11, count 0 2006.280.08:10:41.50#ibcon#about to read 3, iclass 11, count 0 2006.280.08:10:41.52#ibcon#read 3, iclass 11, count 0 2006.280.08:10:41.52#ibcon#about to read 4, iclass 11, count 0 2006.280.08:10:41.52#ibcon#read 4, iclass 11, count 0 2006.280.08:10:41.52#ibcon#about to read 5, iclass 11, count 0 2006.280.08:10:41.52#ibcon#read 5, iclass 11, count 0 2006.280.08:10:41.52#ibcon#about to read 6, iclass 11, count 0 2006.280.08:10:41.52#ibcon#read 6, iclass 11, count 0 2006.280.08:10:41.52#ibcon#end of sib2, iclass 11, count 0 2006.280.08:10:41.52#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:10:41.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:10:41.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:10:41.52#ibcon#*before write, iclass 11, count 0 2006.280.08:10:41.52#ibcon#enter sib2, iclass 11, count 0 2006.280.08:10:41.52#ibcon#flushed, iclass 11, count 0 2006.280.08:10:41.52#ibcon#about to write, iclass 11, count 0 2006.280.08:10:41.52#ibcon#wrote, iclass 11, count 0 2006.280.08:10:41.52#ibcon#about to read 3, iclass 11, count 0 2006.280.08:10:41.56#ibcon#read 3, iclass 11, count 0 2006.280.08:10:41.56#ibcon#about to read 4, iclass 11, count 0 2006.280.08:10:41.56#ibcon#read 4, iclass 11, count 0 2006.280.08:10:41.56#ibcon#about to read 5, iclass 11, count 0 2006.280.08:10:41.56#ibcon#read 5, iclass 11, count 0 2006.280.08:10:41.56#ibcon#about to read 6, iclass 11, count 0 2006.280.08:10:41.56#ibcon#read 6, iclass 11, count 0 2006.280.08:10:41.56#ibcon#end of sib2, iclass 11, count 0 2006.280.08:10:41.56#ibcon#*after write, iclass 11, count 0 2006.280.08:10:41.56#ibcon#*before return 0, iclass 11, count 0 2006.280.08:10:41.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:41.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:41.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:10:41.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:10:41.56$vc4f8/va=3,6 2006.280.08:10:41.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.08:10:41.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.08:10:41.56#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:41.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:41.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:41.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:41.62#ibcon#enter wrdev, iclass 13, count 2 2006.280.08:10:41.62#ibcon#first serial, iclass 13, count 2 2006.280.08:10:41.62#ibcon#enter sib2, iclass 13, count 2 2006.280.08:10:41.62#ibcon#flushed, iclass 13, count 2 2006.280.08:10:41.62#ibcon#about to write, iclass 13, count 2 2006.280.08:10:41.62#ibcon#wrote, iclass 13, count 2 2006.280.08:10:41.62#ibcon#about to read 3, iclass 13, count 2 2006.280.08:10:41.64#ibcon#read 3, iclass 13, count 2 2006.280.08:10:41.64#ibcon#about to read 4, iclass 13, count 2 2006.280.08:10:41.64#ibcon#read 4, iclass 13, count 2 2006.280.08:10:41.64#ibcon#about to read 5, iclass 13, count 2 2006.280.08:10:41.64#ibcon#read 5, iclass 13, count 2 2006.280.08:10:41.64#ibcon#about to read 6, iclass 13, count 2 2006.280.08:10:41.64#ibcon#read 6, iclass 13, count 2 2006.280.08:10:41.64#ibcon#end of sib2, iclass 13, count 2 2006.280.08:10:41.64#ibcon#*mode == 0, iclass 13, count 2 2006.280.08:10:41.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.08:10:41.64#ibcon#[25=AT03-06\r\n] 2006.280.08:10:41.64#ibcon#*before write, iclass 13, count 2 2006.280.08:10:41.64#ibcon#enter sib2, iclass 13, count 2 2006.280.08:10:41.64#ibcon#flushed, iclass 13, count 2 2006.280.08:10:41.64#ibcon#about to write, iclass 13, count 2 2006.280.08:10:41.64#ibcon#wrote, iclass 13, count 2 2006.280.08:10:41.64#ibcon#about to read 3, iclass 13, count 2 2006.280.08:10:41.67#ibcon#read 3, iclass 13, count 2 2006.280.08:10:41.67#ibcon#about to read 4, iclass 13, count 2 2006.280.08:10:41.67#ibcon#read 4, iclass 13, count 2 2006.280.08:10:41.67#ibcon#about to read 5, iclass 13, count 2 2006.280.08:10:41.67#ibcon#read 5, iclass 13, count 2 2006.280.08:10:41.67#ibcon#about to read 6, iclass 13, count 2 2006.280.08:10:41.67#ibcon#read 6, iclass 13, count 2 2006.280.08:10:41.67#ibcon#end of sib2, iclass 13, count 2 2006.280.08:10:41.67#ibcon#*after write, iclass 13, count 2 2006.280.08:10:41.67#ibcon#*before return 0, iclass 13, count 2 2006.280.08:10:41.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:41.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:41.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.08:10:41.67#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:41.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:41.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:41.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:41.79#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:10:41.79#ibcon#first serial, iclass 13, count 0 2006.280.08:10:41.79#ibcon#enter sib2, iclass 13, count 0 2006.280.08:10:41.79#ibcon#flushed, iclass 13, count 0 2006.280.08:10:41.79#ibcon#about to write, iclass 13, count 0 2006.280.08:10:41.79#ibcon#wrote, iclass 13, count 0 2006.280.08:10:41.79#ibcon#about to read 3, iclass 13, count 0 2006.280.08:10:41.81#ibcon#read 3, iclass 13, count 0 2006.280.08:10:41.81#ibcon#about to read 4, iclass 13, count 0 2006.280.08:10:41.81#ibcon#read 4, iclass 13, count 0 2006.280.08:10:41.81#ibcon#about to read 5, iclass 13, count 0 2006.280.08:10:41.81#ibcon#read 5, iclass 13, count 0 2006.280.08:10:41.81#ibcon#about to read 6, iclass 13, count 0 2006.280.08:10:41.81#ibcon#read 6, iclass 13, count 0 2006.280.08:10:41.81#ibcon#end of sib2, iclass 13, count 0 2006.280.08:10:41.81#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:10:41.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:10:41.81#ibcon#[25=USB\r\n] 2006.280.08:10:41.81#ibcon#*before write, iclass 13, count 0 2006.280.08:10:41.81#ibcon#enter sib2, iclass 13, count 0 2006.280.08:10:41.81#ibcon#flushed, iclass 13, count 0 2006.280.08:10:41.81#ibcon#about to write, iclass 13, count 0 2006.280.08:10:41.81#ibcon#wrote, iclass 13, count 0 2006.280.08:10:41.81#ibcon#about to read 3, iclass 13, count 0 2006.280.08:10:41.84#ibcon#read 3, iclass 13, count 0 2006.280.08:10:41.84#ibcon#about to read 4, iclass 13, count 0 2006.280.08:10:41.84#ibcon#read 4, iclass 13, count 0 2006.280.08:10:41.84#ibcon#about to read 5, iclass 13, count 0 2006.280.08:10:41.84#ibcon#read 5, iclass 13, count 0 2006.280.08:10:41.84#ibcon#about to read 6, iclass 13, count 0 2006.280.08:10:41.84#ibcon#read 6, iclass 13, count 0 2006.280.08:10:41.84#ibcon#end of sib2, iclass 13, count 0 2006.280.08:10:41.84#ibcon#*after write, iclass 13, count 0 2006.280.08:10:41.84#ibcon#*before return 0, iclass 13, count 0 2006.280.08:10:41.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:41.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:41.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:10:41.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:10:41.84$vc4f8/valo=4,832.99 2006.280.08:10:41.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:10:41.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:10:41.84#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:41.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:41.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:41.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:41.84#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:10:41.84#ibcon#first serial, iclass 15, count 0 2006.280.08:10:41.84#ibcon#enter sib2, iclass 15, count 0 2006.280.08:10:41.84#ibcon#flushed, iclass 15, count 0 2006.280.08:10:41.84#ibcon#about to write, iclass 15, count 0 2006.280.08:10:41.84#ibcon#wrote, iclass 15, count 0 2006.280.08:10:41.84#ibcon#about to read 3, iclass 15, count 0 2006.280.08:10:41.86#ibcon#read 3, iclass 15, count 0 2006.280.08:10:41.86#ibcon#about to read 4, iclass 15, count 0 2006.280.08:10:41.86#ibcon#read 4, iclass 15, count 0 2006.280.08:10:41.86#ibcon#about to read 5, iclass 15, count 0 2006.280.08:10:41.86#ibcon#read 5, iclass 15, count 0 2006.280.08:10:41.86#ibcon#about to read 6, iclass 15, count 0 2006.280.08:10:41.86#ibcon#read 6, iclass 15, count 0 2006.280.08:10:41.86#ibcon#end of sib2, iclass 15, count 0 2006.280.08:10:41.86#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:10:41.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:10:41.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:10:41.86#ibcon#*before write, iclass 15, count 0 2006.280.08:10:41.86#ibcon#enter sib2, iclass 15, count 0 2006.280.08:10:41.86#ibcon#flushed, iclass 15, count 0 2006.280.08:10:41.86#ibcon#about to write, iclass 15, count 0 2006.280.08:10:41.86#ibcon#wrote, iclass 15, count 0 2006.280.08:10:41.86#ibcon#about to read 3, iclass 15, count 0 2006.280.08:10:41.90#ibcon#read 3, iclass 15, count 0 2006.280.08:10:41.90#ibcon#about to read 4, iclass 15, count 0 2006.280.08:10:41.90#ibcon#read 4, iclass 15, count 0 2006.280.08:10:41.90#ibcon#about to read 5, iclass 15, count 0 2006.280.08:10:41.90#ibcon#read 5, iclass 15, count 0 2006.280.08:10:41.90#ibcon#about to read 6, iclass 15, count 0 2006.280.08:10:41.90#ibcon#read 6, iclass 15, count 0 2006.280.08:10:41.90#ibcon#end of sib2, iclass 15, count 0 2006.280.08:10:41.90#ibcon#*after write, iclass 15, count 0 2006.280.08:10:41.90#ibcon#*before return 0, iclass 15, count 0 2006.280.08:10:41.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:41.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:41.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:10:41.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:10:41.90$vc4f8/va=4,6 2006.280.08:10:41.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:10:41.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:10:41.90#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:41.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:41.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:41.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:41.96#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:10:41.96#ibcon#first serial, iclass 17, count 2 2006.280.08:10:41.96#ibcon#enter sib2, iclass 17, count 2 2006.280.08:10:41.96#ibcon#flushed, iclass 17, count 2 2006.280.08:10:41.96#ibcon#about to write, iclass 17, count 2 2006.280.08:10:41.96#ibcon#wrote, iclass 17, count 2 2006.280.08:10:41.96#ibcon#about to read 3, iclass 17, count 2 2006.280.08:10:41.98#ibcon#read 3, iclass 17, count 2 2006.280.08:10:41.98#ibcon#about to read 4, iclass 17, count 2 2006.280.08:10:41.98#ibcon#read 4, iclass 17, count 2 2006.280.08:10:41.98#ibcon#about to read 5, iclass 17, count 2 2006.280.08:10:41.98#ibcon#read 5, iclass 17, count 2 2006.280.08:10:41.98#ibcon#about to read 6, iclass 17, count 2 2006.280.08:10:41.98#ibcon#read 6, iclass 17, count 2 2006.280.08:10:41.98#ibcon#end of sib2, iclass 17, count 2 2006.280.08:10:41.98#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:10:41.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:10:41.98#ibcon#[25=AT04-06\r\n] 2006.280.08:10:41.98#ibcon#*before write, iclass 17, count 2 2006.280.08:10:41.98#ibcon#enter sib2, iclass 17, count 2 2006.280.08:10:41.98#ibcon#flushed, iclass 17, count 2 2006.280.08:10:41.98#ibcon#about to write, iclass 17, count 2 2006.280.08:10:41.98#ibcon#wrote, iclass 17, count 2 2006.280.08:10:41.98#ibcon#about to read 3, iclass 17, count 2 2006.280.08:10:42.02#ibcon#read 3, iclass 17, count 2 2006.280.08:10:42.02#ibcon#about to read 4, iclass 17, count 2 2006.280.08:10:42.02#ibcon#read 4, iclass 17, count 2 2006.280.08:10:42.02#ibcon#about to read 5, iclass 17, count 2 2006.280.08:10:42.02#ibcon#read 5, iclass 17, count 2 2006.280.08:10:42.02#ibcon#about to read 6, iclass 17, count 2 2006.280.08:10:42.02#ibcon#read 6, iclass 17, count 2 2006.280.08:10:42.02#ibcon#end of sib2, iclass 17, count 2 2006.280.08:10:42.02#ibcon#*after write, iclass 17, count 2 2006.280.08:10:42.02#ibcon#*before return 0, iclass 17, count 2 2006.280.08:10:42.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:42.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:42.02#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:10:42.02#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:42.02#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:42.14#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:42.14#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:42.14#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:10:42.14#ibcon#first serial, iclass 17, count 0 2006.280.08:10:42.14#ibcon#enter sib2, iclass 17, count 0 2006.280.08:10:42.14#ibcon#flushed, iclass 17, count 0 2006.280.08:10:42.14#ibcon#about to write, iclass 17, count 0 2006.280.08:10:42.14#ibcon#wrote, iclass 17, count 0 2006.280.08:10:42.14#ibcon#about to read 3, iclass 17, count 0 2006.280.08:10:42.16#ibcon#read 3, iclass 17, count 0 2006.280.08:10:42.16#ibcon#about to read 4, iclass 17, count 0 2006.280.08:10:42.16#ibcon#read 4, iclass 17, count 0 2006.280.08:10:42.16#ibcon#about to read 5, iclass 17, count 0 2006.280.08:10:42.16#ibcon#read 5, iclass 17, count 0 2006.280.08:10:42.16#ibcon#about to read 6, iclass 17, count 0 2006.280.08:10:42.16#ibcon#read 6, iclass 17, count 0 2006.280.08:10:42.16#ibcon#end of sib2, iclass 17, count 0 2006.280.08:10:42.16#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:10:42.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:10:42.16#ibcon#[25=USB\r\n] 2006.280.08:10:42.16#ibcon#*before write, iclass 17, count 0 2006.280.08:10:42.16#ibcon#enter sib2, iclass 17, count 0 2006.280.08:10:42.16#ibcon#flushed, iclass 17, count 0 2006.280.08:10:42.16#ibcon#about to write, iclass 17, count 0 2006.280.08:10:42.16#ibcon#wrote, iclass 17, count 0 2006.280.08:10:42.16#ibcon#about to read 3, iclass 17, count 0 2006.280.08:10:42.19#ibcon#read 3, iclass 17, count 0 2006.280.08:10:42.19#ibcon#about to read 4, iclass 17, count 0 2006.280.08:10:42.19#ibcon#read 4, iclass 17, count 0 2006.280.08:10:42.19#ibcon#about to read 5, iclass 17, count 0 2006.280.08:10:42.19#ibcon#read 5, iclass 17, count 0 2006.280.08:10:42.19#ibcon#about to read 6, iclass 17, count 0 2006.280.08:10:42.19#ibcon#read 6, iclass 17, count 0 2006.280.08:10:42.19#ibcon#end of sib2, iclass 17, count 0 2006.280.08:10:42.19#ibcon#*after write, iclass 17, count 0 2006.280.08:10:42.19#ibcon#*before return 0, iclass 17, count 0 2006.280.08:10:42.19#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:42.19#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:42.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:10:42.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:10:42.19$vc4f8/valo=5,652.99 2006.280.08:10:42.19#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:10:42.19#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:10:42.19#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:42.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:42.19#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:42.19#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:42.19#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:10:42.19#ibcon#first serial, iclass 19, count 0 2006.280.08:10:42.19#ibcon#enter sib2, iclass 19, count 0 2006.280.08:10:42.19#ibcon#flushed, iclass 19, count 0 2006.280.08:10:42.19#ibcon#about to write, iclass 19, count 0 2006.280.08:10:42.19#ibcon#wrote, iclass 19, count 0 2006.280.08:10:42.19#ibcon#about to read 3, iclass 19, count 0 2006.280.08:10:42.21#ibcon#read 3, iclass 19, count 0 2006.280.08:10:42.21#ibcon#about to read 4, iclass 19, count 0 2006.280.08:10:42.21#ibcon#read 4, iclass 19, count 0 2006.280.08:10:42.21#ibcon#about to read 5, iclass 19, count 0 2006.280.08:10:42.21#ibcon#read 5, iclass 19, count 0 2006.280.08:10:42.21#ibcon#about to read 6, iclass 19, count 0 2006.280.08:10:42.21#ibcon#read 6, iclass 19, count 0 2006.280.08:10:42.21#ibcon#end of sib2, iclass 19, count 0 2006.280.08:10:42.21#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:10:42.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:10:42.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:10:42.21#ibcon#*before write, iclass 19, count 0 2006.280.08:10:42.21#ibcon#enter sib2, iclass 19, count 0 2006.280.08:10:42.21#ibcon#flushed, iclass 19, count 0 2006.280.08:10:42.21#ibcon#about to write, iclass 19, count 0 2006.280.08:10:42.21#ibcon#wrote, iclass 19, count 0 2006.280.08:10:42.21#ibcon#about to read 3, iclass 19, count 0 2006.280.08:10:42.25#ibcon#read 3, iclass 19, count 0 2006.280.08:10:42.25#ibcon#about to read 4, iclass 19, count 0 2006.280.08:10:42.25#ibcon#read 4, iclass 19, count 0 2006.280.08:10:42.25#ibcon#about to read 5, iclass 19, count 0 2006.280.08:10:42.25#ibcon#read 5, iclass 19, count 0 2006.280.08:10:42.25#ibcon#about to read 6, iclass 19, count 0 2006.280.08:10:42.25#ibcon#read 6, iclass 19, count 0 2006.280.08:10:42.25#ibcon#end of sib2, iclass 19, count 0 2006.280.08:10:42.25#ibcon#*after write, iclass 19, count 0 2006.280.08:10:42.25#ibcon#*before return 0, iclass 19, count 0 2006.280.08:10:42.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:42.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:42.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:10:42.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:10:42.25$vc4f8/va=5,7 2006.280.08:10:42.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:10:42.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:10:42.27#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:42.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:42.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:42.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:42.30#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:10:42.30#ibcon#first serial, iclass 21, count 2 2006.280.08:10:42.30#ibcon#enter sib2, iclass 21, count 2 2006.280.08:10:42.30#ibcon#flushed, iclass 21, count 2 2006.280.08:10:42.30#ibcon#about to write, iclass 21, count 2 2006.280.08:10:42.30#ibcon#wrote, iclass 21, count 2 2006.280.08:10:42.30#ibcon#about to read 3, iclass 21, count 2 2006.280.08:10:42.32#ibcon#read 3, iclass 21, count 2 2006.280.08:10:42.32#ibcon#about to read 4, iclass 21, count 2 2006.280.08:10:42.32#ibcon#read 4, iclass 21, count 2 2006.280.08:10:42.32#ibcon#about to read 5, iclass 21, count 2 2006.280.08:10:42.32#ibcon#read 5, iclass 21, count 2 2006.280.08:10:42.32#ibcon#about to read 6, iclass 21, count 2 2006.280.08:10:42.32#ibcon#read 6, iclass 21, count 2 2006.280.08:10:42.32#ibcon#end of sib2, iclass 21, count 2 2006.280.08:10:42.32#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:10:42.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:10:42.32#ibcon#[25=AT05-07\r\n] 2006.280.08:10:42.32#ibcon#*before write, iclass 21, count 2 2006.280.08:10:42.32#ibcon#enter sib2, iclass 21, count 2 2006.280.08:10:42.32#ibcon#flushed, iclass 21, count 2 2006.280.08:10:42.32#ibcon#about to write, iclass 21, count 2 2006.280.08:10:42.32#ibcon#wrote, iclass 21, count 2 2006.280.08:10:42.32#ibcon#about to read 3, iclass 21, count 2 2006.280.08:10:42.35#ibcon#read 3, iclass 21, count 2 2006.280.08:10:42.35#ibcon#about to read 4, iclass 21, count 2 2006.280.08:10:42.35#ibcon#read 4, iclass 21, count 2 2006.280.08:10:42.35#ibcon#about to read 5, iclass 21, count 2 2006.280.08:10:42.35#ibcon#read 5, iclass 21, count 2 2006.280.08:10:42.35#ibcon#about to read 6, iclass 21, count 2 2006.280.08:10:42.35#ibcon#read 6, iclass 21, count 2 2006.280.08:10:42.35#ibcon#end of sib2, iclass 21, count 2 2006.280.08:10:42.35#ibcon#*after write, iclass 21, count 2 2006.280.08:10:42.35#ibcon#*before return 0, iclass 21, count 2 2006.280.08:10:42.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:42.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:42.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:10:42.35#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:42.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:42.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:42.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:42.47#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:10:42.47#ibcon#first serial, iclass 21, count 0 2006.280.08:10:42.47#ibcon#enter sib2, iclass 21, count 0 2006.280.08:10:42.47#ibcon#flushed, iclass 21, count 0 2006.280.08:10:42.47#ibcon#about to write, iclass 21, count 0 2006.280.08:10:42.47#ibcon#wrote, iclass 21, count 0 2006.280.08:10:42.47#ibcon#about to read 3, iclass 21, count 0 2006.280.08:10:42.49#ibcon#read 3, iclass 21, count 0 2006.280.08:10:42.49#ibcon#about to read 4, iclass 21, count 0 2006.280.08:10:42.49#ibcon#read 4, iclass 21, count 0 2006.280.08:10:42.49#ibcon#about to read 5, iclass 21, count 0 2006.280.08:10:42.49#ibcon#read 5, iclass 21, count 0 2006.280.08:10:42.49#ibcon#about to read 6, iclass 21, count 0 2006.280.08:10:42.49#ibcon#read 6, iclass 21, count 0 2006.280.08:10:42.49#ibcon#end of sib2, iclass 21, count 0 2006.280.08:10:42.49#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:10:42.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:10:42.49#ibcon#[25=USB\r\n] 2006.280.08:10:42.49#ibcon#*before write, iclass 21, count 0 2006.280.08:10:42.49#ibcon#enter sib2, iclass 21, count 0 2006.280.08:10:42.49#ibcon#flushed, iclass 21, count 0 2006.280.08:10:42.49#ibcon#about to write, iclass 21, count 0 2006.280.08:10:42.49#ibcon#wrote, iclass 21, count 0 2006.280.08:10:42.49#ibcon#about to read 3, iclass 21, count 0 2006.280.08:10:42.52#ibcon#read 3, iclass 21, count 0 2006.280.08:10:42.52#ibcon#about to read 4, iclass 21, count 0 2006.280.08:10:42.52#ibcon#read 4, iclass 21, count 0 2006.280.08:10:42.52#ibcon#about to read 5, iclass 21, count 0 2006.280.08:10:42.52#ibcon#read 5, iclass 21, count 0 2006.280.08:10:42.52#ibcon#about to read 6, iclass 21, count 0 2006.280.08:10:42.52#ibcon#read 6, iclass 21, count 0 2006.280.08:10:42.52#ibcon#end of sib2, iclass 21, count 0 2006.280.08:10:42.52#ibcon#*after write, iclass 21, count 0 2006.280.08:10:42.52#ibcon#*before return 0, iclass 21, count 0 2006.280.08:10:42.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:42.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:42.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:10:42.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:10:42.52$vc4f8/valo=6,772.99 2006.280.08:10:42.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:10:42.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:10:42.52#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:42.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:42.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:42.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:42.52#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:10:42.52#ibcon#first serial, iclass 23, count 0 2006.280.08:10:42.52#ibcon#enter sib2, iclass 23, count 0 2006.280.08:10:42.52#ibcon#flushed, iclass 23, count 0 2006.280.08:10:42.52#ibcon#about to write, iclass 23, count 0 2006.280.08:10:42.52#ibcon#wrote, iclass 23, count 0 2006.280.08:10:42.52#ibcon#about to read 3, iclass 23, count 0 2006.280.08:10:42.54#ibcon#read 3, iclass 23, count 0 2006.280.08:10:42.54#ibcon#about to read 4, iclass 23, count 0 2006.280.08:10:42.54#ibcon#read 4, iclass 23, count 0 2006.280.08:10:42.54#ibcon#about to read 5, iclass 23, count 0 2006.280.08:10:42.54#ibcon#read 5, iclass 23, count 0 2006.280.08:10:42.54#ibcon#about to read 6, iclass 23, count 0 2006.280.08:10:42.54#ibcon#read 6, iclass 23, count 0 2006.280.08:10:42.54#ibcon#end of sib2, iclass 23, count 0 2006.280.08:10:42.54#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:10:42.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:10:42.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:10:42.54#ibcon#*before write, iclass 23, count 0 2006.280.08:10:42.54#ibcon#enter sib2, iclass 23, count 0 2006.280.08:10:42.54#ibcon#flushed, iclass 23, count 0 2006.280.08:10:42.54#ibcon#about to write, iclass 23, count 0 2006.280.08:10:42.54#ibcon#wrote, iclass 23, count 0 2006.280.08:10:42.54#ibcon#about to read 3, iclass 23, count 0 2006.280.08:10:42.58#ibcon#read 3, iclass 23, count 0 2006.280.08:10:42.58#ibcon#about to read 4, iclass 23, count 0 2006.280.08:10:42.58#ibcon#read 4, iclass 23, count 0 2006.280.08:10:42.58#ibcon#about to read 5, iclass 23, count 0 2006.280.08:10:42.58#ibcon#read 5, iclass 23, count 0 2006.280.08:10:42.58#ibcon#about to read 6, iclass 23, count 0 2006.280.08:10:42.58#ibcon#read 6, iclass 23, count 0 2006.280.08:10:42.58#ibcon#end of sib2, iclass 23, count 0 2006.280.08:10:42.58#ibcon#*after write, iclass 23, count 0 2006.280.08:10:42.58#ibcon#*before return 0, iclass 23, count 0 2006.280.08:10:42.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:42.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:42.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:10:42.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:10:42.58$vc4f8/va=6,6 2006.280.08:10:42.59#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.08:10:42.59#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.08:10:42.59#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:42.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:42.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:42.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:42.63#ibcon#enter wrdev, iclass 25, count 2 2006.280.08:10:42.63#ibcon#first serial, iclass 25, count 2 2006.280.08:10:42.63#ibcon#enter sib2, iclass 25, count 2 2006.280.08:10:42.63#ibcon#flushed, iclass 25, count 2 2006.280.08:10:42.63#ibcon#about to write, iclass 25, count 2 2006.280.08:10:42.63#ibcon#wrote, iclass 25, count 2 2006.280.08:10:42.63#ibcon#about to read 3, iclass 25, count 2 2006.280.08:10:42.65#ibcon#read 3, iclass 25, count 2 2006.280.08:10:42.65#ibcon#about to read 4, iclass 25, count 2 2006.280.08:10:42.65#ibcon#read 4, iclass 25, count 2 2006.280.08:10:42.65#ibcon#about to read 5, iclass 25, count 2 2006.280.08:10:42.65#ibcon#read 5, iclass 25, count 2 2006.280.08:10:42.65#ibcon#about to read 6, iclass 25, count 2 2006.280.08:10:42.65#ibcon#read 6, iclass 25, count 2 2006.280.08:10:42.65#ibcon#end of sib2, iclass 25, count 2 2006.280.08:10:42.65#ibcon#*mode == 0, iclass 25, count 2 2006.280.08:10:42.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.08:10:42.65#ibcon#[25=AT06-06\r\n] 2006.280.08:10:42.65#ibcon#*before write, iclass 25, count 2 2006.280.08:10:42.65#ibcon#enter sib2, iclass 25, count 2 2006.280.08:10:42.65#ibcon#flushed, iclass 25, count 2 2006.280.08:10:42.65#ibcon#about to write, iclass 25, count 2 2006.280.08:10:42.65#ibcon#wrote, iclass 25, count 2 2006.280.08:10:42.65#ibcon#about to read 3, iclass 25, count 2 2006.280.08:10:42.68#ibcon#read 3, iclass 25, count 2 2006.280.08:10:42.68#ibcon#about to read 4, iclass 25, count 2 2006.280.08:10:42.68#ibcon#read 4, iclass 25, count 2 2006.280.08:10:42.68#ibcon#about to read 5, iclass 25, count 2 2006.280.08:10:42.68#ibcon#read 5, iclass 25, count 2 2006.280.08:10:42.68#ibcon#about to read 6, iclass 25, count 2 2006.280.08:10:42.68#ibcon#read 6, iclass 25, count 2 2006.280.08:10:42.68#ibcon#end of sib2, iclass 25, count 2 2006.280.08:10:42.68#ibcon#*after write, iclass 25, count 2 2006.280.08:10:42.68#ibcon#*before return 0, iclass 25, count 2 2006.280.08:10:42.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:42.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:42.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.08:10:42.68#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:42.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:10:42.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:10:42.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:10:42.80#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:10:42.80#ibcon#first serial, iclass 25, count 0 2006.280.08:10:42.80#ibcon#enter sib2, iclass 25, count 0 2006.280.08:10:42.80#ibcon#flushed, iclass 25, count 0 2006.280.08:10:42.80#ibcon#about to write, iclass 25, count 0 2006.280.08:10:42.80#ibcon#wrote, iclass 25, count 0 2006.280.08:10:42.80#ibcon#about to read 3, iclass 25, count 0 2006.280.08:10:42.82#ibcon#read 3, iclass 25, count 0 2006.280.08:10:42.82#ibcon#about to read 4, iclass 25, count 0 2006.280.08:10:42.82#ibcon#read 4, iclass 25, count 0 2006.280.08:10:42.82#ibcon#about to read 5, iclass 25, count 0 2006.280.08:10:42.82#ibcon#read 5, iclass 25, count 0 2006.280.08:10:42.82#ibcon#about to read 6, iclass 25, count 0 2006.280.08:10:42.82#ibcon#read 6, iclass 25, count 0 2006.280.08:10:42.82#ibcon#end of sib2, iclass 25, count 0 2006.280.08:10:42.82#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:10:42.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:10:42.82#ibcon#[25=USB\r\n] 2006.280.08:10:42.82#ibcon#*before write, iclass 25, count 0 2006.280.08:10:42.82#ibcon#enter sib2, iclass 25, count 0 2006.280.08:10:42.82#ibcon#flushed, iclass 25, count 0 2006.280.08:10:42.82#ibcon#about to write, iclass 25, count 0 2006.280.08:10:42.82#ibcon#wrote, iclass 25, count 0 2006.280.08:10:42.82#ibcon#about to read 3, iclass 25, count 0 2006.280.08:10:42.85#ibcon#read 3, iclass 25, count 0 2006.280.08:10:42.85#ibcon#about to read 4, iclass 25, count 0 2006.280.08:10:42.85#ibcon#read 4, iclass 25, count 0 2006.280.08:10:42.85#ibcon#about to read 5, iclass 25, count 0 2006.280.08:10:42.85#ibcon#read 5, iclass 25, count 0 2006.280.08:10:42.85#ibcon#about to read 6, iclass 25, count 0 2006.280.08:10:42.85#ibcon#read 6, iclass 25, count 0 2006.280.08:10:42.85#ibcon#end of sib2, iclass 25, count 0 2006.280.08:10:42.85#ibcon#*after write, iclass 25, count 0 2006.280.08:10:42.85#ibcon#*before return 0, iclass 25, count 0 2006.280.08:10:42.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:10:42.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:10:42.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:10:42.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:10:42.85$vc4f8/valo=7,832.99 2006.280.08:10:42.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.08:10:42.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.08:10:42.85#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:42.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:10:42.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:10:42.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:10:42.85#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:10:42.85#ibcon#first serial, iclass 27, count 0 2006.280.08:10:42.85#ibcon#enter sib2, iclass 27, count 0 2006.280.08:10:42.85#ibcon#flushed, iclass 27, count 0 2006.280.08:10:42.85#ibcon#about to write, iclass 27, count 0 2006.280.08:10:42.85#ibcon#wrote, iclass 27, count 0 2006.280.08:10:42.85#ibcon#about to read 3, iclass 27, count 0 2006.280.08:10:42.87#ibcon#read 3, iclass 27, count 0 2006.280.08:10:42.88#ibcon#about to read 4, iclass 27, count 0 2006.280.08:10:42.88#ibcon#read 4, iclass 27, count 0 2006.280.08:10:42.88#ibcon#about to read 5, iclass 27, count 0 2006.280.08:10:42.88#ibcon#read 5, iclass 27, count 0 2006.280.08:10:42.88#ibcon#about to read 6, iclass 27, count 0 2006.280.08:10:42.88#ibcon#read 6, iclass 27, count 0 2006.280.08:10:42.88#ibcon#end of sib2, iclass 27, count 0 2006.280.08:10:42.88#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:10:42.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:10:42.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:10:42.88#ibcon#*before write, iclass 27, count 0 2006.280.08:10:42.88#ibcon#enter sib2, iclass 27, count 0 2006.280.08:10:42.88#ibcon#flushed, iclass 27, count 0 2006.280.08:10:42.88#ibcon#about to write, iclass 27, count 0 2006.280.08:10:42.88#ibcon#wrote, iclass 27, count 0 2006.280.08:10:42.88#ibcon#about to read 3, iclass 27, count 0 2006.280.08:10:42.93#ibcon#read 3, iclass 27, count 0 2006.280.08:10:42.93#ibcon#about to read 4, iclass 27, count 0 2006.280.08:10:42.93#ibcon#read 4, iclass 27, count 0 2006.280.08:10:42.93#ibcon#about to read 5, iclass 27, count 0 2006.280.08:10:42.93#ibcon#read 5, iclass 27, count 0 2006.280.08:10:42.93#ibcon#about to read 6, iclass 27, count 0 2006.280.08:10:42.93#ibcon#read 6, iclass 27, count 0 2006.280.08:10:42.93#ibcon#end of sib2, iclass 27, count 0 2006.280.08:10:42.93#ibcon#*after write, iclass 27, count 0 2006.280.08:10:42.93#ibcon#*before return 0, iclass 27, count 0 2006.280.08:10:42.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:10:42.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:10:42.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:10:42.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:10:42.93$vc4f8/va=7,6 2006.280.08:10:42.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.08:10:42.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.08:10:42.93#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:42.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:10:42.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:10:42.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:10:42.97#ibcon#enter wrdev, iclass 29, count 2 2006.280.08:10:42.97#ibcon#first serial, iclass 29, count 2 2006.280.08:10:42.97#ibcon#enter sib2, iclass 29, count 2 2006.280.08:10:42.97#ibcon#flushed, iclass 29, count 2 2006.280.08:10:42.97#ibcon#about to write, iclass 29, count 2 2006.280.08:10:42.97#ibcon#wrote, iclass 29, count 2 2006.280.08:10:42.97#ibcon#about to read 3, iclass 29, count 2 2006.280.08:10:42.99#ibcon#read 3, iclass 29, count 2 2006.280.08:10:42.99#ibcon#about to read 4, iclass 29, count 2 2006.280.08:10:42.99#ibcon#read 4, iclass 29, count 2 2006.280.08:10:42.99#ibcon#about to read 5, iclass 29, count 2 2006.280.08:10:42.99#ibcon#read 5, iclass 29, count 2 2006.280.08:10:42.99#ibcon#about to read 6, iclass 29, count 2 2006.280.08:10:42.99#ibcon#read 6, iclass 29, count 2 2006.280.08:10:42.99#ibcon#end of sib2, iclass 29, count 2 2006.280.08:10:42.99#ibcon#*mode == 0, iclass 29, count 2 2006.280.08:10:42.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.08:10:42.99#ibcon#[25=AT07-06\r\n] 2006.280.08:10:42.99#ibcon#*before write, iclass 29, count 2 2006.280.08:10:42.99#ibcon#enter sib2, iclass 29, count 2 2006.280.08:10:42.99#ibcon#flushed, iclass 29, count 2 2006.280.08:10:42.99#ibcon#about to write, iclass 29, count 2 2006.280.08:10:42.99#ibcon#wrote, iclass 29, count 2 2006.280.08:10:42.99#ibcon#about to read 3, iclass 29, count 2 2006.280.08:10:43.02#ibcon#read 3, iclass 29, count 2 2006.280.08:10:43.02#ibcon#about to read 4, iclass 29, count 2 2006.280.08:10:43.02#ibcon#read 4, iclass 29, count 2 2006.280.08:10:43.02#ibcon#about to read 5, iclass 29, count 2 2006.280.08:10:43.02#ibcon#read 5, iclass 29, count 2 2006.280.08:10:43.02#ibcon#about to read 6, iclass 29, count 2 2006.280.08:10:43.02#ibcon#read 6, iclass 29, count 2 2006.280.08:10:43.02#ibcon#end of sib2, iclass 29, count 2 2006.280.08:10:43.02#ibcon#*after write, iclass 29, count 2 2006.280.08:10:43.02#ibcon#*before return 0, iclass 29, count 2 2006.280.08:10:43.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:10:43.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:10:43.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.08:10:43.02#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:43.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:10:43.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:10:43.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:10:43.14#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:10:43.14#ibcon#first serial, iclass 29, count 0 2006.280.08:10:43.14#ibcon#enter sib2, iclass 29, count 0 2006.280.08:10:43.14#ibcon#flushed, iclass 29, count 0 2006.280.08:10:43.14#ibcon#about to write, iclass 29, count 0 2006.280.08:10:43.14#ibcon#wrote, iclass 29, count 0 2006.280.08:10:43.14#ibcon#about to read 3, iclass 29, count 0 2006.280.08:10:43.16#ibcon#read 3, iclass 29, count 0 2006.280.08:10:43.16#ibcon#about to read 4, iclass 29, count 0 2006.280.08:10:43.16#ibcon#read 4, iclass 29, count 0 2006.280.08:10:43.16#ibcon#about to read 5, iclass 29, count 0 2006.280.08:10:43.16#ibcon#read 5, iclass 29, count 0 2006.280.08:10:43.16#ibcon#about to read 6, iclass 29, count 0 2006.280.08:10:43.16#ibcon#read 6, iclass 29, count 0 2006.280.08:10:43.16#ibcon#end of sib2, iclass 29, count 0 2006.280.08:10:43.16#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:10:43.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:10:43.16#ibcon#[25=USB\r\n] 2006.280.08:10:43.16#ibcon#*before write, iclass 29, count 0 2006.280.08:10:43.16#ibcon#enter sib2, iclass 29, count 0 2006.280.08:10:43.16#ibcon#flushed, iclass 29, count 0 2006.280.08:10:43.16#ibcon#about to write, iclass 29, count 0 2006.280.08:10:43.16#ibcon#wrote, iclass 29, count 0 2006.280.08:10:43.16#ibcon#about to read 3, iclass 29, count 0 2006.280.08:10:43.19#ibcon#read 3, iclass 29, count 0 2006.280.08:10:43.19#ibcon#about to read 4, iclass 29, count 0 2006.280.08:10:43.19#ibcon#read 4, iclass 29, count 0 2006.280.08:10:43.19#ibcon#about to read 5, iclass 29, count 0 2006.280.08:10:43.19#ibcon#read 5, iclass 29, count 0 2006.280.08:10:43.19#ibcon#about to read 6, iclass 29, count 0 2006.280.08:10:43.19#ibcon#read 6, iclass 29, count 0 2006.280.08:10:43.19#ibcon#end of sib2, iclass 29, count 0 2006.280.08:10:43.19#ibcon#*after write, iclass 29, count 0 2006.280.08:10:43.19#ibcon#*before return 0, iclass 29, count 0 2006.280.08:10:43.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:10:43.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:10:43.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:10:43.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:10:43.19$vc4f8/valo=8,852.99 2006.280.08:10:43.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.08:10:43.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.08:10:43.19#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:43.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:10:43.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:10:43.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:10:43.19#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:10:43.19#ibcon#first serial, iclass 31, count 0 2006.280.08:10:43.19#ibcon#enter sib2, iclass 31, count 0 2006.280.08:10:43.19#ibcon#flushed, iclass 31, count 0 2006.280.08:10:43.19#ibcon#about to write, iclass 31, count 0 2006.280.08:10:43.19#ibcon#wrote, iclass 31, count 0 2006.280.08:10:43.19#ibcon#about to read 3, iclass 31, count 0 2006.280.08:10:43.21#ibcon#read 3, iclass 31, count 0 2006.280.08:10:43.21#ibcon#about to read 4, iclass 31, count 0 2006.280.08:10:43.21#ibcon#read 4, iclass 31, count 0 2006.280.08:10:43.21#ibcon#about to read 5, iclass 31, count 0 2006.280.08:10:43.21#ibcon#read 5, iclass 31, count 0 2006.280.08:10:43.21#ibcon#about to read 6, iclass 31, count 0 2006.280.08:10:43.21#ibcon#read 6, iclass 31, count 0 2006.280.08:10:43.21#ibcon#end of sib2, iclass 31, count 0 2006.280.08:10:43.21#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:10:43.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:10:43.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:10:43.21#ibcon#*before write, iclass 31, count 0 2006.280.08:10:43.21#ibcon#enter sib2, iclass 31, count 0 2006.280.08:10:43.21#ibcon#flushed, iclass 31, count 0 2006.280.08:10:43.21#ibcon#about to write, iclass 31, count 0 2006.280.08:10:43.21#ibcon#wrote, iclass 31, count 0 2006.280.08:10:43.21#ibcon#about to read 3, iclass 31, count 0 2006.280.08:10:43.25#ibcon#read 3, iclass 31, count 0 2006.280.08:10:43.25#ibcon#about to read 4, iclass 31, count 0 2006.280.08:10:43.25#ibcon#read 4, iclass 31, count 0 2006.280.08:10:43.25#ibcon#about to read 5, iclass 31, count 0 2006.280.08:10:43.25#ibcon#read 5, iclass 31, count 0 2006.280.08:10:43.25#ibcon#about to read 6, iclass 31, count 0 2006.280.08:10:43.25#ibcon#read 6, iclass 31, count 0 2006.280.08:10:43.25#ibcon#end of sib2, iclass 31, count 0 2006.280.08:10:43.25#ibcon#*after write, iclass 31, count 0 2006.280.08:10:43.25#ibcon#*before return 0, iclass 31, count 0 2006.280.08:10:43.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:10:43.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:10:43.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:10:43.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:10:43.25$vc4f8/va=8,6 2006.280.08:10:43.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.280.08:10:43.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.280.08:10:43.25#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:43.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:10:43.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:10:43.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:10:43.31#ibcon#enter wrdev, iclass 33, count 2 2006.280.08:10:43.31#ibcon#first serial, iclass 33, count 2 2006.280.08:10:43.31#ibcon#enter sib2, iclass 33, count 2 2006.280.08:10:43.31#ibcon#flushed, iclass 33, count 2 2006.280.08:10:43.31#ibcon#about to write, iclass 33, count 2 2006.280.08:10:43.31#ibcon#wrote, iclass 33, count 2 2006.280.08:10:43.31#ibcon#about to read 3, iclass 33, count 2 2006.280.08:10:43.33#ibcon#read 3, iclass 33, count 2 2006.280.08:10:43.33#ibcon#about to read 4, iclass 33, count 2 2006.280.08:10:43.33#ibcon#read 4, iclass 33, count 2 2006.280.08:10:43.33#ibcon#about to read 5, iclass 33, count 2 2006.280.08:10:43.33#ibcon#read 5, iclass 33, count 2 2006.280.08:10:43.33#ibcon#about to read 6, iclass 33, count 2 2006.280.08:10:43.33#ibcon#read 6, iclass 33, count 2 2006.280.08:10:43.33#ibcon#end of sib2, iclass 33, count 2 2006.280.08:10:43.33#ibcon#*mode == 0, iclass 33, count 2 2006.280.08:10:43.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.280.08:10:43.33#ibcon#[25=AT08-06\r\n] 2006.280.08:10:43.33#ibcon#*before write, iclass 33, count 2 2006.280.08:10:43.33#ibcon#enter sib2, iclass 33, count 2 2006.280.08:10:43.33#ibcon#flushed, iclass 33, count 2 2006.280.08:10:43.33#ibcon#about to write, iclass 33, count 2 2006.280.08:10:43.33#ibcon#wrote, iclass 33, count 2 2006.280.08:10:43.33#ibcon#about to read 3, iclass 33, count 2 2006.280.08:10:43.36#ibcon#read 3, iclass 33, count 2 2006.280.08:10:43.36#ibcon#about to read 4, iclass 33, count 2 2006.280.08:10:43.36#ibcon#read 4, iclass 33, count 2 2006.280.08:10:43.36#ibcon#about to read 5, iclass 33, count 2 2006.280.08:10:43.36#ibcon#read 5, iclass 33, count 2 2006.280.08:10:43.36#ibcon#about to read 6, iclass 33, count 2 2006.280.08:10:43.36#ibcon#read 6, iclass 33, count 2 2006.280.08:10:43.36#ibcon#end of sib2, iclass 33, count 2 2006.280.08:10:43.36#ibcon#*after write, iclass 33, count 2 2006.280.08:10:43.36#ibcon#*before return 0, iclass 33, count 2 2006.280.08:10:43.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:10:43.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.280.08:10:43.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.280.08:10:43.36#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:43.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:10:43.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:10:43.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:10:43.48#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:10:43.48#ibcon#first serial, iclass 33, count 0 2006.280.08:10:43.48#ibcon#enter sib2, iclass 33, count 0 2006.280.08:10:43.48#ibcon#flushed, iclass 33, count 0 2006.280.08:10:43.48#ibcon#about to write, iclass 33, count 0 2006.280.08:10:43.48#ibcon#wrote, iclass 33, count 0 2006.280.08:10:43.48#ibcon#about to read 3, iclass 33, count 0 2006.280.08:10:43.50#ibcon#read 3, iclass 33, count 0 2006.280.08:10:43.50#ibcon#about to read 4, iclass 33, count 0 2006.280.08:10:43.50#ibcon#read 4, iclass 33, count 0 2006.280.08:10:43.50#ibcon#about to read 5, iclass 33, count 0 2006.280.08:10:43.50#ibcon#read 5, iclass 33, count 0 2006.280.08:10:43.50#ibcon#about to read 6, iclass 33, count 0 2006.280.08:10:43.50#ibcon#read 6, iclass 33, count 0 2006.280.08:10:43.50#ibcon#end of sib2, iclass 33, count 0 2006.280.08:10:43.50#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:10:43.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:10:43.50#ibcon#[25=USB\r\n] 2006.280.08:10:43.50#ibcon#*before write, iclass 33, count 0 2006.280.08:10:43.50#ibcon#enter sib2, iclass 33, count 0 2006.280.08:10:43.50#ibcon#flushed, iclass 33, count 0 2006.280.08:10:43.50#ibcon#about to write, iclass 33, count 0 2006.280.08:10:43.50#ibcon#wrote, iclass 33, count 0 2006.280.08:10:43.50#ibcon#about to read 3, iclass 33, count 0 2006.280.08:10:43.53#ibcon#read 3, iclass 33, count 0 2006.280.08:10:43.53#ibcon#about to read 4, iclass 33, count 0 2006.280.08:10:43.53#ibcon#read 4, iclass 33, count 0 2006.280.08:10:43.53#ibcon#about to read 5, iclass 33, count 0 2006.280.08:10:43.53#ibcon#read 5, iclass 33, count 0 2006.280.08:10:43.53#ibcon#about to read 6, iclass 33, count 0 2006.280.08:10:43.53#ibcon#read 6, iclass 33, count 0 2006.280.08:10:43.53#ibcon#end of sib2, iclass 33, count 0 2006.280.08:10:43.53#ibcon#*after write, iclass 33, count 0 2006.280.08:10:43.53#ibcon#*before return 0, iclass 33, count 0 2006.280.08:10:43.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:10:43.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.280.08:10:43.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:10:43.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:10:43.53$vc4f8/vblo=1,632.99 2006.280.08:10:43.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.08:10:43.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.08:10:43.53#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:43.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:10:43.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:10:43.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:10:43.53#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:10:43.53#ibcon#first serial, iclass 35, count 0 2006.280.08:10:43.53#ibcon#enter sib2, iclass 35, count 0 2006.280.08:10:43.53#ibcon#flushed, iclass 35, count 0 2006.280.08:10:43.53#ibcon#about to write, iclass 35, count 0 2006.280.08:10:43.53#ibcon#wrote, iclass 35, count 0 2006.280.08:10:43.53#ibcon#about to read 3, iclass 35, count 0 2006.280.08:10:43.55#ibcon#read 3, iclass 35, count 0 2006.280.08:10:43.55#ibcon#about to read 4, iclass 35, count 0 2006.280.08:10:43.55#ibcon#read 4, iclass 35, count 0 2006.280.08:10:43.55#ibcon#about to read 5, iclass 35, count 0 2006.280.08:10:43.55#ibcon#read 5, iclass 35, count 0 2006.280.08:10:43.55#ibcon#about to read 6, iclass 35, count 0 2006.280.08:10:43.55#ibcon#read 6, iclass 35, count 0 2006.280.08:10:43.55#ibcon#end of sib2, iclass 35, count 0 2006.280.08:10:43.55#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:10:43.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:10:43.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:10:43.55#ibcon#*before write, iclass 35, count 0 2006.280.08:10:43.55#ibcon#enter sib2, iclass 35, count 0 2006.280.08:10:43.55#ibcon#flushed, iclass 35, count 0 2006.280.08:10:43.55#ibcon#about to write, iclass 35, count 0 2006.280.08:10:43.55#ibcon#wrote, iclass 35, count 0 2006.280.08:10:43.55#ibcon#about to read 3, iclass 35, count 0 2006.280.08:10:43.59#ibcon#read 3, iclass 35, count 0 2006.280.08:10:43.59#ibcon#about to read 4, iclass 35, count 0 2006.280.08:10:43.59#ibcon#read 4, iclass 35, count 0 2006.280.08:10:43.59#ibcon#about to read 5, iclass 35, count 0 2006.280.08:10:43.59#ibcon#read 5, iclass 35, count 0 2006.280.08:10:43.59#ibcon#about to read 6, iclass 35, count 0 2006.280.08:10:43.59#ibcon#read 6, iclass 35, count 0 2006.280.08:10:43.59#ibcon#end of sib2, iclass 35, count 0 2006.280.08:10:43.59#ibcon#*after write, iclass 35, count 0 2006.280.08:10:43.59#ibcon#*before return 0, iclass 35, count 0 2006.280.08:10:43.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:10:43.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:10:43.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:10:43.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:10:43.59$vc4f8/vb=1,4 2006.280.08:10:43.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.08:10:43.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.08:10:43.59#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:43.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:10:43.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:10:43.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:10:43.59#ibcon#enter wrdev, iclass 37, count 2 2006.280.08:10:43.59#ibcon#first serial, iclass 37, count 2 2006.280.08:10:43.59#ibcon#enter sib2, iclass 37, count 2 2006.280.08:10:43.59#ibcon#flushed, iclass 37, count 2 2006.280.08:10:43.59#ibcon#about to write, iclass 37, count 2 2006.280.08:10:43.59#ibcon#wrote, iclass 37, count 2 2006.280.08:10:43.59#ibcon#about to read 3, iclass 37, count 2 2006.280.08:10:43.61#ibcon#read 3, iclass 37, count 2 2006.280.08:10:43.62#ibcon#about to read 4, iclass 37, count 2 2006.280.08:10:43.62#ibcon#read 4, iclass 37, count 2 2006.280.08:10:43.62#ibcon#about to read 5, iclass 37, count 2 2006.280.08:10:43.62#ibcon#read 5, iclass 37, count 2 2006.280.08:10:43.62#ibcon#about to read 6, iclass 37, count 2 2006.280.08:10:43.62#ibcon#read 6, iclass 37, count 2 2006.280.08:10:43.62#ibcon#end of sib2, iclass 37, count 2 2006.280.08:10:43.62#ibcon#*mode == 0, iclass 37, count 2 2006.280.08:10:43.62#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.08:10:43.62#ibcon#[27=AT01-04\r\n] 2006.280.08:10:43.62#ibcon#*before write, iclass 37, count 2 2006.280.08:10:43.62#ibcon#enter sib2, iclass 37, count 2 2006.280.08:10:43.62#ibcon#flushed, iclass 37, count 2 2006.280.08:10:43.62#ibcon#about to write, iclass 37, count 2 2006.280.08:10:43.62#ibcon#wrote, iclass 37, count 2 2006.280.08:10:43.62#ibcon#about to read 3, iclass 37, count 2 2006.280.08:10:43.65#ibcon#read 3, iclass 37, count 2 2006.280.08:10:43.65#ibcon#about to read 4, iclass 37, count 2 2006.280.08:10:43.65#ibcon#read 4, iclass 37, count 2 2006.280.08:10:43.65#ibcon#about to read 5, iclass 37, count 2 2006.280.08:10:43.65#ibcon#read 5, iclass 37, count 2 2006.280.08:10:43.65#ibcon#about to read 6, iclass 37, count 2 2006.280.08:10:43.65#ibcon#read 6, iclass 37, count 2 2006.280.08:10:43.65#ibcon#end of sib2, iclass 37, count 2 2006.280.08:10:43.65#ibcon#*after write, iclass 37, count 2 2006.280.08:10:43.65#ibcon#*before return 0, iclass 37, count 2 2006.280.08:10:43.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:10:43.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:10:43.65#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.08:10:43.65#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:43.65#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:10:43.77#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:10:43.77#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:10:43.77#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:10:43.77#ibcon#first serial, iclass 37, count 0 2006.280.08:10:43.77#ibcon#enter sib2, iclass 37, count 0 2006.280.08:10:43.77#ibcon#flushed, iclass 37, count 0 2006.280.08:10:43.77#ibcon#about to write, iclass 37, count 0 2006.280.08:10:43.77#ibcon#wrote, iclass 37, count 0 2006.280.08:10:43.77#ibcon#about to read 3, iclass 37, count 0 2006.280.08:10:43.79#ibcon#read 3, iclass 37, count 0 2006.280.08:10:43.79#ibcon#about to read 4, iclass 37, count 0 2006.280.08:10:43.79#ibcon#read 4, iclass 37, count 0 2006.280.08:10:43.79#ibcon#about to read 5, iclass 37, count 0 2006.280.08:10:43.79#ibcon#read 5, iclass 37, count 0 2006.280.08:10:43.79#ibcon#about to read 6, iclass 37, count 0 2006.280.08:10:43.79#ibcon#read 6, iclass 37, count 0 2006.280.08:10:43.79#ibcon#end of sib2, iclass 37, count 0 2006.280.08:10:43.79#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:10:43.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:10:43.79#ibcon#[27=USB\r\n] 2006.280.08:10:43.79#ibcon#*before write, iclass 37, count 0 2006.280.08:10:43.79#ibcon#enter sib2, iclass 37, count 0 2006.280.08:10:43.79#ibcon#flushed, iclass 37, count 0 2006.280.08:10:43.79#ibcon#about to write, iclass 37, count 0 2006.280.08:10:43.79#ibcon#wrote, iclass 37, count 0 2006.280.08:10:43.79#ibcon#about to read 3, iclass 37, count 0 2006.280.08:10:43.82#ibcon#read 3, iclass 37, count 0 2006.280.08:10:43.82#ibcon#about to read 4, iclass 37, count 0 2006.280.08:10:43.82#ibcon#read 4, iclass 37, count 0 2006.280.08:10:43.82#ibcon#about to read 5, iclass 37, count 0 2006.280.08:10:43.82#ibcon#read 5, iclass 37, count 0 2006.280.08:10:43.82#ibcon#about to read 6, iclass 37, count 0 2006.280.08:10:43.82#ibcon#read 6, iclass 37, count 0 2006.280.08:10:43.82#ibcon#end of sib2, iclass 37, count 0 2006.280.08:10:43.82#ibcon#*after write, iclass 37, count 0 2006.280.08:10:43.82#ibcon#*before return 0, iclass 37, count 0 2006.280.08:10:43.82#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:10:43.82#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:10:43.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:10:43.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:10:43.82$vc4f8/vblo=2,640.99 2006.280.08:10:43.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.08:10:43.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.08:10:43.82#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:43.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:43.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:43.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:43.82#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:10:43.82#ibcon#first serial, iclass 39, count 0 2006.280.08:10:43.82#ibcon#enter sib2, iclass 39, count 0 2006.280.08:10:43.82#ibcon#flushed, iclass 39, count 0 2006.280.08:10:43.82#ibcon#about to write, iclass 39, count 0 2006.280.08:10:43.82#ibcon#wrote, iclass 39, count 0 2006.280.08:10:43.82#ibcon#about to read 3, iclass 39, count 0 2006.280.08:10:43.84#ibcon#read 3, iclass 39, count 0 2006.280.08:10:43.84#ibcon#about to read 4, iclass 39, count 0 2006.280.08:10:43.84#ibcon#read 4, iclass 39, count 0 2006.280.08:10:43.84#ibcon#about to read 5, iclass 39, count 0 2006.280.08:10:43.84#ibcon#read 5, iclass 39, count 0 2006.280.08:10:43.84#ibcon#about to read 6, iclass 39, count 0 2006.280.08:10:43.84#ibcon#read 6, iclass 39, count 0 2006.280.08:10:43.84#ibcon#end of sib2, iclass 39, count 0 2006.280.08:10:43.84#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:10:43.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:10:43.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:10:43.84#ibcon#*before write, iclass 39, count 0 2006.280.08:10:43.84#ibcon#enter sib2, iclass 39, count 0 2006.280.08:10:43.84#ibcon#flushed, iclass 39, count 0 2006.280.08:10:43.84#ibcon#about to write, iclass 39, count 0 2006.280.08:10:43.84#ibcon#wrote, iclass 39, count 0 2006.280.08:10:43.84#ibcon#about to read 3, iclass 39, count 0 2006.280.08:10:43.88#ibcon#read 3, iclass 39, count 0 2006.280.08:10:43.88#ibcon#about to read 4, iclass 39, count 0 2006.280.08:10:43.88#ibcon#read 4, iclass 39, count 0 2006.280.08:10:43.88#ibcon#about to read 5, iclass 39, count 0 2006.280.08:10:43.88#ibcon#read 5, iclass 39, count 0 2006.280.08:10:43.88#ibcon#about to read 6, iclass 39, count 0 2006.280.08:10:43.88#ibcon#read 6, iclass 39, count 0 2006.280.08:10:43.88#ibcon#end of sib2, iclass 39, count 0 2006.280.08:10:43.88#ibcon#*after write, iclass 39, count 0 2006.280.08:10:43.88#ibcon#*before return 0, iclass 39, count 0 2006.280.08:10:43.88#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:43.88#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:10:43.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:10:43.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:10:43.88$vc4f8/vb=2,5 2006.280.08:10:43.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.08:10:43.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.08:10:43.88#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:43.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:43.94#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:43.94#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:43.94#ibcon#enter wrdev, iclass 3, count 2 2006.280.08:10:43.94#ibcon#first serial, iclass 3, count 2 2006.280.08:10:43.94#ibcon#enter sib2, iclass 3, count 2 2006.280.08:10:43.94#ibcon#flushed, iclass 3, count 2 2006.280.08:10:43.94#ibcon#about to write, iclass 3, count 2 2006.280.08:10:43.94#ibcon#wrote, iclass 3, count 2 2006.280.08:10:43.94#ibcon#about to read 3, iclass 3, count 2 2006.280.08:10:43.96#ibcon#read 3, iclass 3, count 2 2006.280.08:10:43.96#ibcon#about to read 4, iclass 3, count 2 2006.280.08:10:43.96#ibcon#read 4, iclass 3, count 2 2006.280.08:10:43.96#ibcon#about to read 5, iclass 3, count 2 2006.280.08:10:43.96#ibcon#read 5, iclass 3, count 2 2006.280.08:10:43.96#ibcon#about to read 6, iclass 3, count 2 2006.280.08:10:43.96#ibcon#read 6, iclass 3, count 2 2006.280.08:10:43.96#ibcon#end of sib2, iclass 3, count 2 2006.280.08:10:43.96#ibcon#*mode == 0, iclass 3, count 2 2006.280.08:10:43.96#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.08:10:43.96#ibcon#[27=AT02-05\r\n] 2006.280.08:10:43.96#ibcon#*before write, iclass 3, count 2 2006.280.08:10:43.96#ibcon#enter sib2, iclass 3, count 2 2006.280.08:10:43.96#ibcon#flushed, iclass 3, count 2 2006.280.08:10:43.96#ibcon#about to write, iclass 3, count 2 2006.280.08:10:43.96#ibcon#wrote, iclass 3, count 2 2006.280.08:10:43.96#ibcon#about to read 3, iclass 3, count 2 2006.280.08:10:43.99#ibcon#read 3, iclass 3, count 2 2006.280.08:10:43.99#ibcon#about to read 4, iclass 3, count 2 2006.280.08:10:43.99#ibcon#read 4, iclass 3, count 2 2006.280.08:10:43.99#ibcon#about to read 5, iclass 3, count 2 2006.280.08:10:43.99#ibcon#read 5, iclass 3, count 2 2006.280.08:10:43.99#ibcon#about to read 6, iclass 3, count 2 2006.280.08:10:43.99#ibcon#read 6, iclass 3, count 2 2006.280.08:10:43.99#ibcon#end of sib2, iclass 3, count 2 2006.280.08:10:43.99#ibcon#*after write, iclass 3, count 2 2006.280.08:10:43.99#ibcon#*before return 0, iclass 3, count 2 2006.280.08:10:43.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:43.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:10:43.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.08:10:43.99#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:43.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:44.11#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:44.11#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:44.11#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:10:44.11#ibcon#first serial, iclass 3, count 0 2006.280.08:10:44.11#ibcon#enter sib2, iclass 3, count 0 2006.280.08:10:44.11#ibcon#flushed, iclass 3, count 0 2006.280.08:10:44.11#ibcon#about to write, iclass 3, count 0 2006.280.08:10:44.11#ibcon#wrote, iclass 3, count 0 2006.280.08:10:44.11#ibcon#about to read 3, iclass 3, count 0 2006.280.08:10:44.13#ibcon#read 3, iclass 3, count 0 2006.280.08:10:44.13#ibcon#about to read 4, iclass 3, count 0 2006.280.08:10:44.13#ibcon#read 4, iclass 3, count 0 2006.280.08:10:44.13#ibcon#about to read 5, iclass 3, count 0 2006.280.08:10:44.13#ibcon#read 5, iclass 3, count 0 2006.280.08:10:44.13#ibcon#about to read 6, iclass 3, count 0 2006.280.08:10:44.13#ibcon#read 6, iclass 3, count 0 2006.280.08:10:44.13#ibcon#end of sib2, iclass 3, count 0 2006.280.08:10:44.13#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:10:44.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:10:44.13#ibcon#[27=USB\r\n] 2006.280.08:10:44.13#ibcon#*before write, iclass 3, count 0 2006.280.08:10:44.13#ibcon#enter sib2, iclass 3, count 0 2006.280.08:10:44.13#ibcon#flushed, iclass 3, count 0 2006.280.08:10:44.13#ibcon#about to write, iclass 3, count 0 2006.280.08:10:44.13#ibcon#wrote, iclass 3, count 0 2006.280.08:10:44.13#ibcon#about to read 3, iclass 3, count 0 2006.280.08:10:44.16#ibcon#read 3, iclass 3, count 0 2006.280.08:10:44.16#ibcon#about to read 4, iclass 3, count 0 2006.280.08:10:44.16#ibcon#read 4, iclass 3, count 0 2006.280.08:10:44.16#ibcon#about to read 5, iclass 3, count 0 2006.280.08:10:44.16#ibcon#read 5, iclass 3, count 0 2006.280.08:10:44.16#ibcon#about to read 6, iclass 3, count 0 2006.280.08:10:44.16#ibcon#read 6, iclass 3, count 0 2006.280.08:10:44.16#ibcon#end of sib2, iclass 3, count 0 2006.280.08:10:44.16#ibcon#*after write, iclass 3, count 0 2006.280.08:10:44.16#ibcon#*before return 0, iclass 3, count 0 2006.280.08:10:44.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:44.16#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:10:44.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:10:44.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:10:44.16$vc4f8/vblo=3,656.99 2006.280.08:10:44.16#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.08:10:44.16#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.08:10:44.16#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:44.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:44.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:44.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:44.16#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:10:44.16#ibcon#first serial, iclass 5, count 0 2006.280.08:10:44.16#ibcon#enter sib2, iclass 5, count 0 2006.280.08:10:44.16#ibcon#flushed, iclass 5, count 0 2006.280.08:10:44.16#ibcon#about to write, iclass 5, count 0 2006.280.08:10:44.16#ibcon#wrote, iclass 5, count 0 2006.280.08:10:44.16#ibcon#about to read 3, iclass 5, count 0 2006.280.08:10:44.18#ibcon#read 3, iclass 5, count 0 2006.280.08:10:44.18#ibcon#about to read 4, iclass 5, count 0 2006.280.08:10:44.18#ibcon#read 4, iclass 5, count 0 2006.280.08:10:44.18#ibcon#about to read 5, iclass 5, count 0 2006.280.08:10:44.18#ibcon#read 5, iclass 5, count 0 2006.280.08:10:44.18#ibcon#about to read 6, iclass 5, count 0 2006.280.08:10:44.18#ibcon#read 6, iclass 5, count 0 2006.280.08:10:44.18#ibcon#end of sib2, iclass 5, count 0 2006.280.08:10:44.18#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:10:44.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:10:44.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:10:44.18#ibcon#*before write, iclass 5, count 0 2006.280.08:10:44.18#ibcon#enter sib2, iclass 5, count 0 2006.280.08:10:44.18#ibcon#flushed, iclass 5, count 0 2006.280.08:10:44.18#ibcon#about to write, iclass 5, count 0 2006.280.08:10:44.18#ibcon#wrote, iclass 5, count 0 2006.280.08:10:44.18#ibcon#about to read 3, iclass 5, count 0 2006.280.08:10:44.22#ibcon#read 3, iclass 5, count 0 2006.280.08:10:44.22#ibcon#about to read 4, iclass 5, count 0 2006.280.08:10:44.22#ibcon#read 4, iclass 5, count 0 2006.280.08:10:44.22#ibcon#about to read 5, iclass 5, count 0 2006.280.08:10:44.22#ibcon#read 5, iclass 5, count 0 2006.280.08:10:44.22#ibcon#about to read 6, iclass 5, count 0 2006.280.08:10:44.22#ibcon#read 6, iclass 5, count 0 2006.280.08:10:44.22#ibcon#end of sib2, iclass 5, count 0 2006.280.08:10:44.22#ibcon#*after write, iclass 5, count 0 2006.280.08:10:44.22#ibcon#*before return 0, iclass 5, count 0 2006.280.08:10:44.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:44.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:10:44.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:10:44.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:10:44.22$vc4f8/vb=3,4 2006.280.08:10:44.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.08:10:44.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.08:10:44.22#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:44.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:44.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:44.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:44.28#ibcon#enter wrdev, iclass 7, count 2 2006.280.08:10:44.28#ibcon#first serial, iclass 7, count 2 2006.280.08:10:44.28#ibcon#enter sib2, iclass 7, count 2 2006.280.08:10:44.28#ibcon#flushed, iclass 7, count 2 2006.280.08:10:44.28#ibcon#about to write, iclass 7, count 2 2006.280.08:10:44.28#ibcon#wrote, iclass 7, count 2 2006.280.08:10:44.28#ibcon#about to read 3, iclass 7, count 2 2006.280.08:10:44.30#ibcon#read 3, iclass 7, count 2 2006.280.08:10:44.30#ibcon#about to read 4, iclass 7, count 2 2006.280.08:10:44.30#ibcon#read 4, iclass 7, count 2 2006.280.08:10:44.30#ibcon#about to read 5, iclass 7, count 2 2006.280.08:10:44.30#ibcon#read 5, iclass 7, count 2 2006.280.08:10:44.30#ibcon#about to read 6, iclass 7, count 2 2006.280.08:10:44.30#ibcon#read 6, iclass 7, count 2 2006.280.08:10:44.30#ibcon#end of sib2, iclass 7, count 2 2006.280.08:10:44.30#ibcon#*mode == 0, iclass 7, count 2 2006.280.08:10:44.30#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.08:10:44.30#ibcon#[27=AT03-04\r\n] 2006.280.08:10:44.30#ibcon#*before write, iclass 7, count 2 2006.280.08:10:44.30#ibcon#enter sib2, iclass 7, count 2 2006.280.08:10:44.30#ibcon#flushed, iclass 7, count 2 2006.280.08:10:44.30#ibcon#about to write, iclass 7, count 2 2006.280.08:10:44.30#ibcon#wrote, iclass 7, count 2 2006.280.08:10:44.30#ibcon#about to read 3, iclass 7, count 2 2006.280.08:10:44.33#ibcon#read 3, iclass 7, count 2 2006.280.08:10:44.33#ibcon#about to read 4, iclass 7, count 2 2006.280.08:10:44.33#ibcon#read 4, iclass 7, count 2 2006.280.08:10:44.33#ibcon#about to read 5, iclass 7, count 2 2006.280.08:10:44.33#ibcon#read 5, iclass 7, count 2 2006.280.08:10:44.33#ibcon#about to read 6, iclass 7, count 2 2006.280.08:10:44.33#ibcon#read 6, iclass 7, count 2 2006.280.08:10:44.33#ibcon#end of sib2, iclass 7, count 2 2006.280.08:10:44.33#ibcon#*after write, iclass 7, count 2 2006.280.08:10:44.33#ibcon#*before return 0, iclass 7, count 2 2006.280.08:10:44.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:44.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:10:44.33#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.08:10:44.33#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:44.33#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:44.45#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:44.45#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:44.45#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:10:44.45#ibcon#first serial, iclass 7, count 0 2006.280.08:10:44.45#ibcon#enter sib2, iclass 7, count 0 2006.280.08:10:44.45#ibcon#flushed, iclass 7, count 0 2006.280.08:10:44.45#ibcon#about to write, iclass 7, count 0 2006.280.08:10:44.45#ibcon#wrote, iclass 7, count 0 2006.280.08:10:44.45#ibcon#about to read 3, iclass 7, count 0 2006.280.08:10:44.47#ibcon#read 3, iclass 7, count 0 2006.280.08:10:44.47#ibcon#about to read 4, iclass 7, count 0 2006.280.08:10:44.47#ibcon#read 4, iclass 7, count 0 2006.280.08:10:44.47#ibcon#about to read 5, iclass 7, count 0 2006.280.08:10:44.47#ibcon#read 5, iclass 7, count 0 2006.280.08:10:44.47#ibcon#about to read 6, iclass 7, count 0 2006.280.08:10:44.47#ibcon#read 6, iclass 7, count 0 2006.280.08:10:44.47#ibcon#end of sib2, iclass 7, count 0 2006.280.08:10:44.47#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:10:44.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:10:44.47#ibcon#[27=USB\r\n] 2006.280.08:10:44.47#ibcon#*before write, iclass 7, count 0 2006.280.08:10:44.47#ibcon#enter sib2, iclass 7, count 0 2006.280.08:10:44.47#ibcon#flushed, iclass 7, count 0 2006.280.08:10:44.47#ibcon#about to write, iclass 7, count 0 2006.280.08:10:44.47#ibcon#wrote, iclass 7, count 0 2006.280.08:10:44.47#ibcon#about to read 3, iclass 7, count 0 2006.280.08:10:44.50#ibcon#read 3, iclass 7, count 0 2006.280.08:10:44.50#ibcon#about to read 4, iclass 7, count 0 2006.280.08:10:44.50#ibcon#read 4, iclass 7, count 0 2006.280.08:10:44.50#ibcon#about to read 5, iclass 7, count 0 2006.280.08:10:44.50#ibcon#read 5, iclass 7, count 0 2006.280.08:10:44.50#ibcon#about to read 6, iclass 7, count 0 2006.280.08:10:44.50#ibcon#read 6, iclass 7, count 0 2006.280.08:10:44.50#ibcon#end of sib2, iclass 7, count 0 2006.280.08:10:44.50#ibcon#*after write, iclass 7, count 0 2006.280.08:10:44.50#ibcon#*before return 0, iclass 7, count 0 2006.280.08:10:44.50#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:44.50#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:10:44.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:10:44.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:10:44.50$vc4f8/vblo=4,712.99 2006.280.08:10:44.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.08:10:44.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.08:10:44.50#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:44.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:44.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:44.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:44.50#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:10:44.50#ibcon#first serial, iclass 11, count 0 2006.280.08:10:44.50#ibcon#enter sib2, iclass 11, count 0 2006.280.08:10:44.50#ibcon#flushed, iclass 11, count 0 2006.280.08:10:44.50#ibcon#about to write, iclass 11, count 0 2006.280.08:10:44.50#ibcon#wrote, iclass 11, count 0 2006.280.08:10:44.50#ibcon#about to read 3, iclass 11, count 0 2006.280.08:10:44.52#ibcon#read 3, iclass 11, count 0 2006.280.08:10:44.52#ibcon#about to read 4, iclass 11, count 0 2006.280.08:10:44.52#ibcon#read 4, iclass 11, count 0 2006.280.08:10:44.52#ibcon#about to read 5, iclass 11, count 0 2006.280.08:10:44.52#ibcon#read 5, iclass 11, count 0 2006.280.08:10:44.52#ibcon#about to read 6, iclass 11, count 0 2006.280.08:10:44.52#ibcon#read 6, iclass 11, count 0 2006.280.08:10:44.52#ibcon#end of sib2, iclass 11, count 0 2006.280.08:10:44.52#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:10:44.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:10:44.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:10:44.52#ibcon#*before write, iclass 11, count 0 2006.280.08:10:44.52#ibcon#enter sib2, iclass 11, count 0 2006.280.08:10:44.52#ibcon#flushed, iclass 11, count 0 2006.280.08:10:44.52#ibcon#about to write, iclass 11, count 0 2006.280.08:10:44.52#ibcon#wrote, iclass 11, count 0 2006.280.08:10:44.52#ibcon#about to read 3, iclass 11, count 0 2006.280.08:10:44.56#ibcon#read 3, iclass 11, count 0 2006.280.08:10:44.56#ibcon#about to read 4, iclass 11, count 0 2006.280.08:10:44.56#ibcon#read 4, iclass 11, count 0 2006.280.08:10:44.56#ibcon#about to read 5, iclass 11, count 0 2006.280.08:10:44.56#ibcon#read 5, iclass 11, count 0 2006.280.08:10:44.56#ibcon#about to read 6, iclass 11, count 0 2006.280.08:10:44.56#ibcon#read 6, iclass 11, count 0 2006.280.08:10:44.56#ibcon#end of sib2, iclass 11, count 0 2006.280.08:10:44.56#ibcon#*after write, iclass 11, count 0 2006.280.08:10:44.56#ibcon#*before return 0, iclass 11, count 0 2006.280.08:10:44.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:44.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:10:44.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:10:44.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:10:44.56$vc4f8/vb=4,4 2006.280.08:10:44.56#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.08:10:44.56#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.08:10:44.56#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:44.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:44.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:44.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:44.62#ibcon#enter wrdev, iclass 13, count 2 2006.280.08:10:44.62#ibcon#first serial, iclass 13, count 2 2006.280.08:10:44.62#ibcon#enter sib2, iclass 13, count 2 2006.280.08:10:44.62#ibcon#flushed, iclass 13, count 2 2006.280.08:10:44.62#ibcon#about to write, iclass 13, count 2 2006.280.08:10:44.62#ibcon#wrote, iclass 13, count 2 2006.280.08:10:44.62#ibcon#about to read 3, iclass 13, count 2 2006.280.08:10:44.64#ibcon#read 3, iclass 13, count 2 2006.280.08:10:44.64#ibcon#about to read 4, iclass 13, count 2 2006.280.08:10:44.64#ibcon#read 4, iclass 13, count 2 2006.280.08:10:44.64#ibcon#about to read 5, iclass 13, count 2 2006.280.08:10:44.64#ibcon#read 5, iclass 13, count 2 2006.280.08:10:44.64#ibcon#about to read 6, iclass 13, count 2 2006.280.08:10:44.64#ibcon#read 6, iclass 13, count 2 2006.280.08:10:44.64#ibcon#end of sib2, iclass 13, count 2 2006.280.08:10:44.64#ibcon#*mode == 0, iclass 13, count 2 2006.280.08:10:44.64#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.08:10:44.64#ibcon#[27=AT04-04\r\n] 2006.280.08:10:44.64#ibcon#*before write, iclass 13, count 2 2006.280.08:10:44.64#ibcon#enter sib2, iclass 13, count 2 2006.280.08:10:44.64#ibcon#flushed, iclass 13, count 2 2006.280.08:10:44.64#ibcon#about to write, iclass 13, count 2 2006.280.08:10:44.64#ibcon#wrote, iclass 13, count 2 2006.280.08:10:44.64#ibcon#about to read 3, iclass 13, count 2 2006.280.08:10:44.67#ibcon#read 3, iclass 13, count 2 2006.280.08:10:44.67#ibcon#about to read 4, iclass 13, count 2 2006.280.08:10:44.67#ibcon#read 4, iclass 13, count 2 2006.280.08:10:44.67#ibcon#about to read 5, iclass 13, count 2 2006.280.08:10:44.67#ibcon#read 5, iclass 13, count 2 2006.280.08:10:44.67#ibcon#about to read 6, iclass 13, count 2 2006.280.08:10:44.67#ibcon#read 6, iclass 13, count 2 2006.280.08:10:44.67#ibcon#end of sib2, iclass 13, count 2 2006.280.08:10:44.67#ibcon#*after write, iclass 13, count 2 2006.280.08:10:44.67#ibcon#*before return 0, iclass 13, count 2 2006.280.08:10:44.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:44.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:10:44.67#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.08:10:44.67#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:44.67#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:44.79#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:44.79#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:44.79#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:10:44.79#ibcon#first serial, iclass 13, count 0 2006.280.08:10:44.79#ibcon#enter sib2, iclass 13, count 0 2006.280.08:10:44.79#ibcon#flushed, iclass 13, count 0 2006.280.08:10:44.79#ibcon#about to write, iclass 13, count 0 2006.280.08:10:44.79#ibcon#wrote, iclass 13, count 0 2006.280.08:10:44.79#ibcon#about to read 3, iclass 13, count 0 2006.280.08:10:44.81#ibcon#read 3, iclass 13, count 0 2006.280.08:10:44.81#ibcon#about to read 4, iclass 13, count 0 2006.280.08:10:44.81#ibcon#read 4, iclass 13, count 0 2006.280.08:10:44.81#ibcon#about to read 5, iclass 13, count 0 2006.280.08:10:44.81#ibcon#read 5, iclass 13, count 0 2006.280.08:10:44.81#ibcon#about to read 6, iclass 13, count 0 2006.280.08:10:44.81#ibcon#read 6, iclass 13, count 0 2006.280.08:10:44.81#ibcon#end of sib2, iclass 13, count 0 2006.280.08:10:44.81#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:10:44.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:10:44.81#ibcon#[27=USB\r\n] 2006.280.08:10:44.81#ibcon#*before write, iclass 13, count 0 2006.280.08:10:44.81#ibcon#enter sib2, iclass 13, count 0 2006.280.08:10:44.81#ibcon#flushed, iclass 13, count 0 2006.280.08:10:44.81#ibcon#about to write, iclass 13, count 0 2006.280.08:10:44.81#ibcon#wrote, iclass 13, count 0 2006.280.08:10:44.81#ibcon#about to read 3, iclass 13, count 0 2006.280.08:10:44.84#ibcon#read 3, iclass 13, count 0 2006.280.08:10:44.84#ibcon#about to read 4, iclass 13, count 0 2006.280.08:10:44.84#ibcon#read 4, iclass 13, count 0 2006.280.08:10:44.84#ibcon#about to read 5, iclass 13, count 0 2006.280.08:10:44.84#ibcon#read 5, iclass 13, count 0 2006.280.08:10:44.84#ibcon#about to read 6, iclass 13, count 0 2006.280.08:10:44.84#ibcon#read 6, iclass 13, count 0 2006.280.08:10:44.84#ibcon#end of sib2, iclass 13, count 0 2006.280.08:10:44.84#ibcon#*after write, iclass 13, count 0 2006.280.08:10:44.84#ibcon#*before return 0, iclass 13, count 0 2006.280.08:10:44.84#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:44.84#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:10:44.84#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:10:44.84#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:10:44.84$vc4f8/vblo=5,744.99 2006.280.08:10:44.84#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:10:44.84#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:10:44.84#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:44.84#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:44.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:44.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:44.84#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:10:44.84#ibcon#first serial, iclass 15, count 0 2006.280.08:10:44.84#ibcon#enter sib2, iclass 15, count 0 2006.280.08:10:44.84#ibcon#flushed, iclass 15, count 0 2006.280.08:10:44.84#ibcon#about to write, iclass 15, count 0 2006.280.08:10:44.84#ibcon#wrote, iclass 15, count 0 2006.280.08:10:44.84#ibcon#about to read 3, iclass 15, count 0 2006.280.08:10:44.86#ibcon#read 3, iclass 15, count 0 2006.280.08:10:44.86#ibcon#about to read 4, iclass 15, count 0 2006.280.08:10:44.86#ibcon#read 4, iclass 15, count 0 2006.280.08:10:44.86#ibcon#about to read 5, iclass 15, count 0 2006.280.08:10:44.86#ibcon#read 5, iclass 15, count 0 2006.280.08:10:44.86#ibcon#about to read 6, iclass 15, count 0 2006.280.08:10:44.86#ibcon#read 6, iclass 15, count 0 2006.280.08:10:44.86#ibcon#end of sib2, iclass 15, count 0 2006.280.08:10:44.86#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:10:44.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:10:44.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:10:44.86#ibcon#*before write, iclass 15, count 0 2006.280.08:10:44.86#ibcon#enter sib2, iclass 15, count 0 2006.280.08:10:44.86#ibcon#flushed, iclass 15, count 0 2006.280.08:10:44.86#ibcon#about to write, iclass 15, count 0 2006.280.08:10:44.86#ibcon#wrote, iclass 15, count 0 2006.280.08:10:44.86#ibcon#about to read 3, iclass 15, count 0 2006.280.08:10:44.90#ibcon#read 3, iclass 15, count 0 2006.280.08:10:44.90#ibcon#about to read 4, iclass 15, count 0 2006.280.08:10:44.90#ibcon#read 4, iclass 15, count 0 2006.280.08:10:44.90#ibcon#about to read 5, iclass 15, count 0 2006.280.08:10:44.90#ibcon#read 5, iclass 15, count 0 2006.280.08:10:44.90#ibcon#about to read 6, iclass 15, count 0 2006.280.08:10:44.90#ibcon#read 6, iclass 15, count 0 2006.280.08:10:44.90#ibcon#end of sib2, iclass 15, count 0 2006.280.08:10:44.90#ibcon#*after write, iclass 15, count 0 2006.280.08:10:44.90#ibcon#*before return 0, iclass 15, count 0 2006.280.08:10:44.90#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:44.90#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:10:44.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:10:44.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:10:44.90$vc4f8/vb=5,4 2006.280.08:10:44.90#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:10:44.90#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:10:44.90#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:44.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:44.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:44.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:44.96#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:10:44.96#ibcon#first serial, iclass 17, count 2 2006.280.08:10:44.96#ibcon#enter sib2, iclass 17, count 2 2006.280.08:10:44.96#ibcon#flushed, iclass 17, count 2 2006.280.08:10:44.96#ibcon#about to write, iclass 17, count 2 2006.280.08:10:44.96#ibcon#wrote, iclass 17, count 2 2006.280.08:10:44.96#ibcon#about to read 3, iclass 17, count 2 2006.280.08:10:44.98#ibcon#read 3, iclass 17, count 2 2006.280.08:10:44.98#ibcon#about to read 4, iclass 17, count 2 2006.280.08:10:44.98#ibcon#read 4, iclass 17, count 2 2006.280.08:10:44.98#ibcon#about to read 5, iclass 17, count 2 2006.280.08:10:44.98#ibcon#read 5, iclass 17, count 2 2006.280.08:10:44.98#ibcon#about to read 6, iclass 17, count 2 2006.280.08:10:44.98#ibcon#read 6, iclass 17, count 2 2006.280.08:10:44.98#ibcon#end of sib2, iclass 17, count 2 2006.280.08:10:44.98#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:10:44.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:10:44.98#ibcon#[27=AT05-04\r\n] 2006.280.08:10:44.98#ibcon#*before write, iclass 17, count 2 2006.280.08:10:44.98#ibcon#enter sib2, iclass 17, count 2 2006.280.08:10:44.98#ibcon#flushed, iclass 17, count 2 2006.280.08:10:44.98#ibcon#about to write, iclass 17, count 2 2006.280.08:10:44.98#ibcon#wrote, iclass 17, count 2 2006.280.08:10:44.98#ibcon#about to read 3, iclass 17, count 2 2006.280.08:10:45.01#ibcon#read 3, iclass 17, count 2 2006.280.08:10:45.01#ibcon#about to read 4, iclass 17, count 2 2006.280.08:10:45.01#ibcon#read 4, iclass 17, count 2 2006.280.08:10:45.01#ibcon#about to read 5, iclass 17, count 2 2006.280.08:10:45.01#ibcon#read 5, iclass 17, count 2 2006.280.08:10:45.01#ibcon#about to read 6, iclass 17, count 2 2006.280.08:10:45.01#ibcon#read 6, iclass 17, count 2 2006.280.08:10:45.01#ibcon#end of sib2, iclass 17, count 2 2006.280.08:10:45.01#ibcon#*after write, iclass 17, count 2 2006.280.08:10:45.01#ibcon#*before return 0, iclass 17, count 2 2006.280.08:10:45.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:45.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:10:45.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:10:45.01#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:45.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:45.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:45.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:45.13#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:10:45.13#ibcon#first serial, iclass 17, count 0 2006.280.08:10:45.13#ibcon#enter sib2, iclass 17, count 0 2006.280.08:10:45.13#ibcon#flushed, iclass 17, count 0 2006.280.08:10:45.13#ibcon#about to write, iclass 17, count 0 2006.280.08:10:45.13#ibcon#wrote, iclass 17, count 0 2006.280.08:10:45.13#ibcon#about to read 3, iclass 17, count 0 2006.280.08:10:45.15#ibcon#read 3, iclass 17, count 0 2006.280.08:10:45.15#ibcon#about to read 4, iclass 17, count 0 2006.280.08:10:45.15#ibcon#read 4, iclass 17, count 0 2006.280.08:10:45.15#ibcon#about to read 5, iclass 17, count 0 2006.280.08:10:45.15#ibcon#read 5, iclass 17, count 0 2006.280.08:10:45.15#ibcon#about to read 6, iclass 17, count 0 2006.280.08:10:45.15#ibcon#read 6, iclass 17, count 0 2006.280.08:10:45.15#ibcon#end of sib2, iclass 17, count 0 2006.280.08:10:45.15#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:10:45.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:10:45.15#ibcon#[27=USB\r\n] 2006.280.08:10:45.15#ibcon#*before write, iclass 17, count 0 2006.280.08:10:45.15#ibcon#enter sib2, iclass 17, count 0 2006.280.08:10:45.15#ibcon#flushed, iclass 17, count 0 2006.280.08:10:45.15#ibcon#about to write, iclass 17, count 0 2006.280.08:10:45.15#ibcon#wrote, iclass 17, count 0 2006.280.08:10:45.15#ibcon#about to read 3, iclass 17, count 0 2006.280.08:10:45.18#ibcon#read 3, iclass 17, count 0 2006.280.08:10:45.18#ibcon#about to read 4, iclass 17, count 0 2006.280.08:10:45.18#ibcon#read 4, iclass 17, count 0 2006.280.08:10:45.18#ibcon#about to read 5, iclass 17, count 0 2006.280.08:10:45.18#ibcon#read 5, iclass 17, count 0 2006.280.08:10:45.18#ibcon#about to read 6, iclass 17, count 0 2006.280.08:10:45.18#ibcon#read 6, iclass 17, count 0 2006.280.08:10:45.18#ibcon#end of sib2, iclass 17, count 0 2006.280.08:10:45.18#ibcon#*after write, iclass 17, count 0 2006.280.08:10:45.18#ibcon#*before return 0, iclass 17, count 0 2006.280.08:10:45.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:45.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:10:45.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:10:45.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:10:45.18$vc4f8/vblo=6,752.99 2006.280.08:10:45.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:10:45.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:10:45.18#ibcon#ireg 17 cls_cnt 0 2006.280.08:10:45.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:45.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:45.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:45.18#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:10:45.18#ibcon#first serial, iclass 19, count 0 2006.280.08:10:45.18#ibcon#enter sib2, iclass 19, count 0 2006.280.08:10:45.18#ibcon#flushed, iclass 19, count 0 2006.280.08:10:45.18#ibcon#about to write, iclass 19, count 0 2006.280.08:10:45.18#ibcon#wrote, iclass 19, count 0 2006.280.08:10:45.18#ibcon#about to read 3, iclass 19, count 0 2006.280.08:10:45.20#ibcon#read 3, iclass 19, count 0 2006.280.08:10:45.20#ibcon#about to read 4, iclass 19, count 0 2006.280.08:10:45.20#ibcon#read 4, iclass 19, count 0 2006.280.08:10:45.20#ibcon#about to read 5, iclass 19, count 0 2006.280.08:10:45.20#ibcon#read 5, iclass 19, count 0 2006.280.08:10:45.20#ibcon#about to read 6, iclass 19, count 0 2006.280.08:10:45.20#ibcon#read 6, iclass 19, count 0 2006.280.08:10:45.20#ibcon#end of sib2, iclass 19, count 0 2006.280.08:10:45.20#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:10:45.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:10:45.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:10:45.20#ibcon#*before write, iclass 19, count 0 2006.280.08:10:45.20#ibcon#enter sib2, iclass 19, count 0 2006.280.08:10:45.20#ibcon#flushed, iclass 19, count 0 2006.280.08:10:45.20#ibcon#about to write, iclass 19, count 0 2006.280.08:10:45.20#ibcon#wrote, iclass 19, count 0 2006.280.08:10:45.20#ibcon#about to read 3, iclass 19, count 0 2006.280.08:10:45.24#ibcon#read 3, iclass 19, count 0 2006.280.08:10:45.24#ibcon#about to read 4, iclass 19, count 0 2006.280.08:10:45.24#ibcon#read 4, iclass 19, count 0 2006.280.08:10:45.24#ibcon#about to read 5, iclass 19, count 0 2006.280.08:10:45.24#ibcon#read 5, iclass 19, count 0 2006.280.08:10:45.24#ibcon#about to read 6, iclass 19, count 0 2006.280.08:10:45.24#ibcon#read 6, iclass 19, count 0 2006.280.08:10:45.24#ibcon#end of sib2, iclass 19, count 0 2006.280.08:10:45.24#ibcon#*after write, iclass 19, count 0 2006.280.08:10:45.24#ibcon#*before return 0, iclass 19, count 0 2006.280.08:10:45.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:45.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:10:45.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:10:45.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:10:45.24$vc4f8/vb=6,4 2006.280.08:10:45.25#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:10:45.25#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:10:45.25#ibcon#ireg 11 cls_cnt 2 2006.280.08:10:45.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:45.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:45.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:45.30#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:10:45.30#ibcon#first serial, iclass 21, count 2 2006.280.08:10:45.30#ibcon#enter sib2, iclass 21, count 2 2006.280.08:10:45.30#ibcon#flushed, iclass 21, count 2 2006.280.08:10:45.30#ibcon#about to write, iclass 21, count 2 2006.280.08:10:45.30#ibcon#wrote, iclass 21, count 2 2006.280.08:10:45.30#ibcon#about to read 3, iclass 21, count 2 2006.280.08:10:45.32#ibcon#read 3, iclass 21, count 2 2006.280.08:10:45.32#ibcon#about to read 4, iclass 21, count 2 2006.280.08:10:45.32#ibcon#read 4, iclass 21, count 2 2006.280.08:10:45.32#ibcon#about to read 5, iclass 21, count 2 2006.280.08:10:45.32#ibcon#read 5, iclass 21, count 2 2006.280.08:10:45.32#ibcon#about to read 6, iclass 21, count 2 2006.280.08:10:45.32#ibcon#read 6, iclass 21, count 2 2006.280.08:10:45.32#ibcon#end of sib2, iclass 21, count 2 2006.280.08:10:45.32#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:10:45.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:10:45.32#ibcon#[27=AT06-04\r\n] 2006.280.08:10:45.32#ibcon#*before write, iclass 21, count 2 2006.280.08:10:45.32#ibcon#enter sib2, iclass 21, count 2 2006.280.08:10:45.32#ibcon#flushed, iclass 21, count 2 2006.280.08:10:45.32#ibcon#about to write, iclass 21, count 2 2006.280.08:10:45.32#ibcon#wrote, iclass 21, count 2 2006.280.08:10:45.32#ibcon#about to read 3, iclass 21, count 2 2006.280.08:10:45.35#ibcon#read 3, iclass 21, count 2 2006.280.08:10:45.35#ibcon#about to read 4, iclass 21, count 2 2006.280.08:10:45.35#ibcon#read 4, iclass 21, count 2 2006.280.08:10:45.35#ibcon#about to read 5, iclass 21, count 2 2006.280.08:10:45.35#ibcon#read 5, iclass 21, count 2 2006.280.08:10:45.35#ibcon#about to read 6, iclass 21, count 2 2006.280.08:10:45.35#ibcon#read 6, iclass 21, count 2 2006.280.08:10:45.35#ibcon#end of sib2, iclass 21, count 2 2006.280.08:10:45.35#ibcon#*after write, iclass 21, count 2 2006.280.08:10:45.35#ibcon#*before return 0, iclass 21, count 2 2006.280.08:10:45.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:45.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:10:45.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:10:45.35#ibcon#ireg 7 cls_cnt 0 2006.280.08:10:45.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:45.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:45.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:45.47#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:10:45.47#ibcon#first serial, iclass 21, count 0 2006.280.08:10:45.47#ibcon#enter sib2, iclass 21, count 0 2006.280.08:10:45.47#ibcon#flushed, iclass 21, count 0 2006.280.08:10:45.47#ibcon#about to write, iclass 21, count 0 2006.280.08:10:45.47#ibcon#wrote, iclass 21, count 0 2006.280.08:10:45.47#ibcon#about to read 3, iclass 21, count 0 2006.280.08:10:45.49#ibcon#read 3, iclass 21, count 0 2006.280.08:10:45.49#ibcon#about to read 4, iclass 21, count 0 2006.280.08:10:45.49#ibcon#read 4, iclass 21, count 0 2006.280.08:10:45.49#ibcon#about to read 5, iclass 21, count 0 2006.280.08:10:45.49#ibcon#read 5, iclass 21, count 0 2006.280.08:10:45.49#ibcon#about to read 6, iclass 21, count 0 2006.280.08:10:45.49#ibcon#read 6, iclass 21, count 0 2006.280.08:10:45.49#ibcon#end of sib2, iclass 21, count 0 2006.280.08:10:45.49#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:10:45.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:10:45.49#ibcon#[27=USB\r\n] 2006.280.08:10:45.49#ibcon#*before write, iclass 21, count 0 2006.280.08:10:45.49#ibcon#enter sib2, iclass 21, count 0 2006.280.08:10:45.49#ibcon#flushed, iclass 21, count 0 2006.280.08:10:45.49#ibcon#about to write, iclass 21, count 0 2006.280.08:10:45.49#ibcon#wrote, iclass 21, count 0 2006.280.08:10:45.49#ibcon#about to read 3, iclass 21, count 0 2006.280.08:10:45.52#ibcon#read 3, iclass 21, count 0 2006.280.08:10:45.52#ibcon#about to read 4, iclass 21, count 0 2006.280.08:10:45.52#ibcon#read 4, iclass 21, count 0 2006.280.08:10:45.52#ibcon#about to read 5, iclass 21, count 0 2006.280.08:10:45.52#ibcon#read 5, iclass 21, count 0 2006.280.08:10:45.52#ibcon#about to read 6, iclass 21, count 0 2006.280.08:10:45.52#ibcon#read 6, iclass 21, count 0 2006.280.08:10:45.52#ibcon#end of sib2, iclass 21, count 0 2006.280.08:10:45.52#ibcon#*after write, iclass 21, count 0 2006.280.08:10:45.52#ibcon#*before return 0, iclass 21, count 0 2006.280.08:10:45.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:45.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:10:45.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:10:45.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:10:45.52$vc4f8/vabw=wide 2006.280.08:10:45.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:10:45.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:10:45.52#ibcon#ireg 8 cls_cnt 0 2006.280.08:10:45.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:45.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:45.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:45.52#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:10:45.52#ibcon#first serial, iclass 23, count 0 2006.280.08:10:45.52#ibcon#enter sib2, iclass 23, count 0 2006.280.08:10:45.52#ibcon#flushed, iclass 23, count 0 2006.280.08:10:45.52#ibcon#about to write, iclass 23, count 0 2006.280.08:10:45.52#ibcon#wrote, iclass 23, count 0 2006.280.08:10:45.52#ibcon#about to read 3, iclass 23, count 0 2006.280.08:10:45.54#ibcon#read 3, iclass 23, count 0 2006.280.08:10:45.54#ibcon#about to read 4, iclass 23, count 0 2006.280.08:10:45.54#ibcon#read 4, iclass 23, count 0 2006.280.08:10:45.54#ibcon#about to read 5, iclass 23, count 0 2006.280.08:10:45.54#ibcon#read 5, iclass 23, count 0 2006.280.08:10:45.54#ibcon#about to read 6, iclass 23, count 0 2006.280.08:10:45.54#ibcon#read 6, iclass 23, count 0 2006.280.08:10:45.54#ibcon#end of sib2, iclass 23, count 0 2006.280.08:10:45.54#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:10:45.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:10:45.54#ibcon#[25=BW32\r\n] 2006.280.08:10:45.54#ibcon#*before write, iclass 23, count 0 2006.280.08:10:45.54#ibcon#enter sib2, iclass 23, count 0 2006.280.08:10:45.54#ibcon#flushed, iclass 23, count 0 2006.280.08:10:45.54#ibcon#about to write, iclass 23, count 0 2006.280.08:10:45.54#ibcon#wrote, iclass 23, count 0 2006.280.08:10:45.54#ibcon#about to read 3, iclass 23, count 0 2006.280.08:10:45.57#ibcon#read 3, iclass 23, count 0 2006.280.08:10:45.57#ibcon#about to read 4, iclass 23, count 0 2006.280.08:10:45.57#ibcon#read 4, iclass 23, count 0 2006.280.08:10:45.57#ibcon#about to read 5, iclass 23, count 0 2006.280.08:10:45.57#ibcon#read 5, iclass 23, count 0 2006.280.08:10:45.57#ibcon#about to read 6, iclass 23, count 0 2006.280.08:10:45.57#ibcon#read 6, iclass 23, count 0 2006.280.08:10:45.57#ibcon#end of sib2, iclass 23, count 0 2006.280.08:10:45.57#ibcon#*after write, iclass 23, count 0 2006.280.08:10:45.57#ibcon#*before return 0, iclass 23, count 0 2006.280.08:10:45.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:45.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:10:45.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:10:45.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:10:45.57$vc4f8/vbbw=wide 2006.280.08:10:45.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.08:10:45.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.08:10:45.57#ibcon#ireg 8 cls_cnt 0 2006.280.08:10:45.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:10:45.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:10:45.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:10:45.64#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:10:45.64#ibcon#first serial, iclass 25, count 0 2006.280.08:10:45.64#ibcon#enter sib2, iclass 25, count 0 2006.280.08:10:45.64#ibcon#flushed, iclass 25, count 0 2006.280.08:10:45.64#ibcon#about to write, iclass 25, count 0 2006.280.08:10:45.64#ibcon#wrote, iclass 25, count 0 2006.280.08:10:45.64#ibcon#about to read 3, iclass 25, count 0 2006.280.08:10:45.66#ibcon#read 3, iclass 25, count 0 2006.280.08:10:45.66#ibcon#about to read 4, iclass 25, count 0 2006.280.08:10:45.66#ibcon#read 4, iclass 25, count 0 2006.280.08:10:45.66#ibcon#about to read 5, iclass 25, count 0 2006.280.08:10:45.66#ibcon#read 5, iclass 25, count 0 2006.280.08:10:45.66#ibcon#about to read 6, iclass 25, count 0 2006.280.08:10:45.66#ibcon#read 6, iclass 25, count 0 2006.280.08:10:45.66#ibcon#end of sib2, iclass 25, count 0 2006.280.08:10:45.66#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:10:45.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:10:45.66#ibcon#[27=BW32\r\n] 2006.280.08:10:45.66#ibcon#*before write, iclass 25, count 0 2006.280.08:10:45.66#ibcon#enter sib2, iclass 25, count 0 2006.280.08:10:45.66#ibcon#flushed, iclass 25, count 0 2006.280.08:10:45.66#ibcon#about to write, iclass 25, count 0 2006.280.08:10:45.66#ibcon#wrote, iclass 25, count 0 2006.280.08:10:45.66#ibcon#about to read 3, iclass 25, count 0 2006.280.08:10:45.69#ibcon#read 3, iclass 25, count 0 2006.280.08:10:45.69#ibcon#about to read 4, iclass 25, count 0 2006.280.08:10:45.69#ibcon#read 4, iclass 25, count 0 2006.280.08:10:45.69#ibcon#about to read 5, iclass 25, count 0 2006.280.08:10:45.69#ibcon#read 5, iclass 25, count 0 2006.280.08:10:45.69#ibcon#about to read 6, iclass 25, count 0 2006.280.08:10:45.69#ibcon#read 6, iclass 25, count 0 2006.280.08:10:45.69#ibcon#end of sib2, iclass 25, count 0 2006.280.08:10:45.69#ibcon#*after write, iclass 25, count 0 2006.280.08:10:45.69#ibcon#*before return 0, iclass 25, count 0 2006.280.08:10:45.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:10:45.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:10:45.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:10:45.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:10:45.69$4f8m12a/ifd4f 2006.280.08:10:45.69$ifd4f/lo= 2006.280.08:10:45.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:10:45.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:10:45.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:10:45.69$ifd4f/patch= 2006.280.08:10:45.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:10:45.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:10:45.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:10:45.69$4f8m12a/"form=m,16.000,1:2 2006.280.08:10:45.69$4f8m12a/"tpicd 2006.280.08:10:45.69$4f8m12a/echo=off 2006.280.08:10:45.69$4f8m12a/xlog=off 2006.280.08:10:45.69:!2006.280.08:11:10 2006.280.08:10:47.14#trakl#Source acquired 2006.280.08:10:49.14#flagr#flagr/antenna,acquired 2006.280.08:11:10.00:preob 2006.280.08:11:11.14/onsource/TRACKING 2006.280.08:11:11.14:!2006.280.08:11:20 2006.280.08:11:20.00:data_valid=on 2006.280.08:11:20.00:midob 2006.280.08:11:20.14/onsource/TRACKING 2006.280.08:11:20.14/wx/20.45,987.4,62 2006.280.08:11:20.19/cable/+6.4837E-03 2006.280.08:11:21.28/va/01,07,usb,yes,35,37 2006.280.08:11:21.28/va/02,06,usb,yes,32,34 2006.280.08:11:21.28/va/03,06,usb,yes,31,31 2006.280.08:11:21.28/va/04,06,usb,yes,34,36 2006.280.08:11:21.28/va/05,07,usb,yes,32,34 2006.280.08:11:21.28/va/06,06,usb,yes,31,31 2006.280.08:11:21.28/va/07,06,usb,yes,31,31 2006.280.08:11:21.28/va/08,06,usb,yes,34,33 2006.280.08:11:21.51/valo/01,532.99,yes,locked 2006.280.08:11:21.51/valo/02,572.99,yes,locked 2006.280.08:11:21.51/valo/03,672.99,yes,locked 2006.280.08:11:21.51/valo/04,832.99,yes,locked 2006.280.08:11:21.51/valo/05,652.99,yes,locked 2006.280.08:11:21.51/valo/06,772.99,yes,locked 2006.280.08:11:21.51/valo/07,832.99,yes,locked 2006.280.08:11:21.51/valo/08,852.99,yes,locked 2006.280.08:11:22.60/vb/01,04,usb,yes,31,30 2006.280.08:11:22.60/vb/02,05,usb,yes,29,31 2006.280.08:11:22.60/vb/03,04,usb,yes,30,34 2006.280.08:11:22.60/vb/04,04,usb,yes,30,31 2006.280.08:11:22.60/vb/05,04,usb,yes,28,33 2006.280.08:11:22.60/vb/06,04,usb,yes,29,32 2006.280.08:11:22.60/vb/07,04,usb,yes,32,32 2006.280.08:11:22.60/vb/08,04,usb,yes,29,33 2006.280.08:11:22.84/vblo/01,632.99,yes,locked 2006.280.08:11:22.84/vblo/02,640.99,yes,locked 2006.280.08:11:22.84/vblo/03,656.99,yes,locked 2006.280.08:11:22.84/vblo/04,712.99,yes,locked 2006.280.08:11:22.84/vblo/05,744.99,yes,locked 2006.280.08:11:22.84/vblo/06,752.99,yes,locked 2006.280.08:11:22.84/vblo/07,734.99,yes,locked 2006.280.08:11:22.84/vblo/08,744.99,yes,locked 2006.280.08:11:22.99/vabw/8 2006.280.08:11:23.14/vbbw/8 2006.280.08:11:23.37/xfe/off,on,12.2 2006.280.08:11:23.76/ifatt/23,28,28,28 2006.280.08:11:24.08/fmout-gps/S +3.16E-07 2006.280.08:11:24.10:!2006.280.08:12:20 2006.280.08:12:20.01:data_valid=off 2006.280.08:12:20.01:postob 2006.280.08:12:20.09/cable/+6.4832E-03 2006.280.08:12:20.10/wx/20.44,987.5,61 2006.280.08:12:21.08/fmout-gps/S +3.14E-07 2006.280.08:12:21.08:scan_name=280-0813,k06280,60 2006.280.08:12:21.08:source=1739+522,174036.98,521143.4,2000.0,ccw 2006.280.08:12:21.14#flagr#flagr/antenna,new-source 2006.280.08:12:22.14:checkk5 2006.280.08:12:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:12:23.32/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:12:23.79/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:12:24.23/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:12:24.63/chk_obsdata//k5ts1/T2800811??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:12:25.26/chk_obsdata//k5ts2/T2800811??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:12:26.01/chk_obsdata//k5ts3/T2800811??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:12:26.39/chk_obsdata//k5ts4/T2800811??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:12:27.64/k5log//k5ts1_log_newline 2006.280.08:12:28.56/k5log//k5ts2_log_newline 2006.280.08:12:29.63/k5log//k5ts3_log_newline 2006.280.08:12:30.57/k5log//k5ts4_log_newline 2006.280.08:12:30.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:12:30.60:4f8m12a=2 2006.280.08:12:30.60$4f8m12a/echo=on 2006.280.08:12:30.60$4f8m12a/pcalon 2006.280.08:12:30.60$pcalon/"no phase cal control is implemented here 2006.280.08:12:30.60$4f8m12a/"tpicd=stop 2006.280.08:12:30.60$4f8m12a/vc4f8 2006.280.08:12:30.60$vc4f8/valo=1,532.99 2006.280.08:12:30.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.08:12:30.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.08:12:30.60#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:30.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:30.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:30.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:30.60#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:12:30.60#ibcon#first serial, iclass 32, count 0 2006.280.08:12:30.60#ibcon#enter sib2, iclass 32, count 0 2006.280.08:12:30.60#ibcon#flushed, iclass 32, count 0 2006.280.08:12:30.60#ibcon#about to write, iclass 32, count 0 2006.280.08:12:30.60#ibcon#wrote, iclass 32, count 0 2006.280.08:12:30.60#ibcon#about to read 3, iclass 32, count 0 2006.280.08:12:30.62#ibcon#read 3, iclass 32, count 0 2006.280.08:12:30.62#ibcon#about to read 4, iclass 32, count 0 2006.280.08:12:30.62#ibcon#read 4, iclass 32, count 0 2006.280.08:12:30.62#ibcon#about to read 5, iclass 32, count 0 2006.280.08:12:30.62#ibcon#read 5, iclass 32, count 0 2006.280.08:12:30.62#ibcon#about to read 6, iclass 32, count 0 2006.280.08:12:30.62#ibcon#read 6, iclass 32, count 0 2006.280.08:12:30.62#ibcon#end of sib2, iclass 32, count 0 2006.280.08:12:30.62#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:12:30.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:12:30.62#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:12:30.62#ibcon#*before write, iclass 32, count 0 2006.280.08:12:30.62#ibcon#enter sib2, iclass 32, count 0 2006.280.08:12:30.62#ibcon#flushed, iclass 32, count 0 2006.280.08:12:30.62#ibcon#about to write, iclass 32, count 0 2006.280.08:12:30.62#ibcon#wrote, iclass 32, count 0 2006.280.08:12:30.62#ibcon#about to read 3, iclass 32, count 0 2006.280.08:12:30.67#ibcon#read 3, iclass 32, count 0 2006.280.08:12:30.67#ibcon#about to read 4, iclass 32, count 0 2006.280.08:12:30.67#ibcon#read 4, iclass 32, count 0 2006.280.08:12:30.67#ibcon#about to read 5, iclass 32, count 0 2006.280.08:12:30.67#ibcon#read 5, iclass 32, count 0 2006.280.08:12:30.67#ibcon#about to read 6, iclass 32, count 0 2006.280.08:12:30.67#ibcon#read 6, iclass 32, count 0 2006.280.08:12:30.67#ibcon#end of sib2, iclass 32, count 0 2006.280.08:12:30.67#ibcon#*after write, iclass 32, count 0 2006.280.08:12:30.67#ibcon#*before return 0, iclass 32, count 0 2006.280.08:12:30.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:30.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:30.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:12:30.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:12:30.67$vc4f8/va=1,7 2006.280.08:12:30.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.08:12:30.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.08:12:30.67#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:30.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:30.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:30.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:30.67#ibcon#enter wrdev, iclass 34, count 2 2006.280.08:12:30.67#ibcon#first serial, iclass 34, count 2 2006.280.08:12:30.67#ibcon#enter sib2, iclass 34, count 2 2006.280.08:12:30.67#ibcon#flushed, iclass 34, count 2 2006.280.08:12:30.67#ibcon#about to write, iclass 34, count 2 2006.280.08:12:30.67#ibcon#wrote, iclass 34, count 2 2006.280.08:12:30.67#ibcon#about to read 3, iclass 34, count 2 2006.280.08:12:30.69#ibcon#read 3, iclass 34, count 2 2006.280.08:12:30.69#ibcon#about to read 4, iclass 34, count 2 2006.280.08:12:30.69#ibcon#read 4, iclass 34, count 2 2006.280.08:12:30.69#ibcon#about to read 5, iclass 34, count 2 2006.280.08:12:30.69#ibcon#read 5, iclass 34, count 2 2006.280.08:12:30.69#ibcon#about to read 6, iclass 34, count 2 2006.280.08:12:30.69#ibcon#read 6, iclass 34, count 2 2006.280.08:12:30.69#ibcon#end of sib2, iclass 34, count 2 2006.280.08:12:30.69#ibcon#*mode == 0, iclass 34, count 2 2006.280.08:12:30.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.08:12:30.69#ibcon#[25=AT01-07\r\n] 2006.280.08:12:30.69#ibcon#*before write, iclass 34, count 2 2006.280.08:12:30.69#ibcon#enter sib2, iclass 34, count 2 2006.280.08:12:30.69#ibcon#flushed, iclass 34, count 2 2006.280.08:12:30.69#ibcon#about to write, iclass 34, count 2 2006.280.08:12:30.69#ibcon#wrote, iclass 34, count 2 2006.280.08:12:30.69#ibcon#about to read 3, iclass 34, count 2 2006.280.08:12:30.72#ibcon#read 3, iclass 34, count 2 2006.280.08:12:30.72#ibcon#about to read 4, iclass 34, count 2 2006.280.08:12:30.72#ibcon#read 4, iclass 34, count 2 2006.280.08:12:30.72#ibcon#about to read 5, iclass 34, count 2 2006.280.08:12:30.72#ibcon#read 5, iclass 34, count 2 2006.280.08:12:30.72#ibcon#about to read 6, iclass 34, count 2 2006.280.08:12:30.72#ibcon#read 6, iclass 34, count 2 2006.280.08:12:30.72#ibcon#end of sib2, iclass 34, count 2 2006.280.08:12:30.72#ibcon#*after write, iclass 34, count 2 2006.280.08:12:30.72#ibcon#*before return 0, iclass 34, count 2 2006.280.08:12:30.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:30.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:30.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.08:12:30.72#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:30.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:30.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:30.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:30.84#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:12:30.84#ibcon#first serial, iclass 34, count 0 2006.280.08:12:30.84#ibcon#enter sib2, iclass 34, count 0 2006.280.08:12:30.84#ibcon#flushed, iclass 34, count 0 2006.280.08:12:30.84#ibcon#about to write, iclass 34, count 0 2006.280.08:12:30.84#ibcon#wrote, iclass 34, count 0 2006.280.08:12:30.84#ibcon#about to read 3, iclass 34, count 0 2006.280.08:12:30.86#ibcon#read 3, iclass 34, count 0 2006.280.08:12:30.86#ibcon#about to read 4, iclass 34, count 0 2006.280.08:12:30.86#ibcon#read 4, iclass 34, count 0 2006.280.08:12:30.86#ibcon#about to read 5, iclass 34, count 0 2006.280.08:12:30.86#ibcon#read 5, iclass 34, count 0 2006.280.08:12:30.86#ibcon#about to read 6, iclass 34, count 0 2006.280.08:12:30.86#ibcon#read 6, iclass 34, count 0 2006.280.08:12:30.86#ibcon#end of sib2, iclass 34, count 0 2006.280.08:12:30.86#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:12:30.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:12:30.86#ibcon#[25=USB\r\n] 2006.280.08:12:30.86#ibcon#*before write, iclass 34, count 0 2006.280.08:12:30.86#ibcon#enter sib2, iclass 34, count 0 2006.280.08:12:30.86#ibcon#flushed, iclass 34, count 0 2006.280.08:12:30.86#ibcon#about to write, iclass 34, count 0 2006.280.08:12:30.86#ibcon#wrote, iclass 34, count 0 2006.280.08:12:30.86#ibcon#about to read 3, iclass 34, count 0 2006.280.08:12:30.89#ibcon#read 3, iclass 34, count 0 2006.280.08:12:30.89#ibcon#about to read 4, iclass 34, count 0 2006.280.08:12:30.89#ibcon#read 4, iclass 34, count 0 2006.280.08:12:30.89#ibcon#about to read 5, iclass 34, count 0 2006.280.08:12:30.89#ibcon#read 5, iclass 34, count 0 2006.280.08:12:30.89#ibcon#about to read 6, iclass 34, count 0 2006.280.08:12:30.89#ibcon#read 6, iclass 34, count 0 2006.280.08:12:30.89#ibcon#end of sib2, iclass 34, count 0 2006.280.08:12:30.89#ibcon#*after write, iclass 34, count 0 2006.280.08:12:30.89#ibcon#*before return 0, iclass 34, count 0 2006.280.08:12:30.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:30.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:30.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:12:30.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:12:30.89$vc4f8/valo=2,572.99 2006.280.08:12:30.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.08:12:30.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.08:12:30.89#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:30.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:30.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:30.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:30.89#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:12:30.89#ibcon#first serial, iclass 36, count 0 2006.280.08:12:30.89#ibcon#enter sib2, iclass 36, count 0 2006.280.08:12:30.89#ibcon#flushed, iclass 36, count 0 2006.280.08:12:30.89#ibcon#about to write, iclass 36, count 0 2006.280.08:12:30.89#ibcon#wrote, iclass 36, count 0 2006.280.08:12:30.89#ibcon#about to read 3, iclass 36, count 0 2006.280.08:12:30.91#ibcon#read 3, iclass 36, count 0 2006.280.08:12:30.91#ibcon#about to read 4, iclass 36, count 0 2006.280.08:12:30.91#ibcon#read 4, iclass 36, count 0 2006.280.08:12:30.91#ibcon#about to read 5, iclass 36, count 0 2006.280.08:12:30.91#ibcon#read 5, iclass 36, count 0 2006.280.08:12:30.91#ibcon#about to read 6, iclass 36, count 0 2006.280.08:12:30.91#ibcon#read 6, iclass 36, count 0 2006.280.08:12:30.91#ibcon#end of sib2, iclass 36, count 0 2006.280.08:12:30.91#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:12:30.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:12:30.91#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:12:30.91#ibcon#*before write, iclass 36, count 0 2006.280.08:12:30.91#ibcon#enter sib2, iclass 36, count 0 2006.280.08:12:30.91#ibcon#flushed, iclass 36, count 0 2006.280.08:12:30.91#ibcon#about to write, iclass 36, count 0 2006.280.08:12:30.91#ibcon#wrote, iclass 36, count 0 2006.280.08:12:30.91#ibcon#about to read 3, iclass 36, count 0 2006.280.08:12:30.95#ibcon#read 3, iclass 36, count 0 2006.280.08:12:30.95#ibcon#about to read 4, iclass 36, count 0 2006.280.08:12:30.95#ibcon#read 4, iclass 36, count 0 2006.280.08:12:30.95#ibcon#about to read 5, iclass 36, count 0 2006.280.08:12:30.95#ibcon#read 5, iclass 36, count 0 2006.280.08:12:30.95#ibcon#about to read 6, iclass 36, count 0 2006.280.08:12:30.95#ibcon#read 6, iclass 36, count 0 2006.280.08:12:30.95#ibcon#end of sib2, iclass 36, count 0 2006.280.08:12:30.95#ibcon#*after write, iclass 36, count 0 2006.280.08:12:30.95#ibcon#*before return 0, iclass 36, count 0 2006.280.08:12:30.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:30.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:30.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:12:30.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:12:30.95$vc4f8/va=2,6 2006.280.08:12:30.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.08:12:30.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.08:12:30.95#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:30.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:31.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:31.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:31.01#ibcon#enter wrdev, iclass 38, count 2 2006.280.08:12:31.01#ibcon#first serial, iclass 38, count 2 2006.280.08:12:31.01#ibcon#enter sib2, iclass 38, count 2 2006.280.08:12:31.01#ibcon#flushed, iclass 38, count 2 2006.280.08:12:31.01#ibcon#about to write, iclass 38, count 2 2006.280.08:12:31.01#ibcon#wrote, iclass 38, count 2 2006.280.08:12:31.01#ibcon#about to read 3, iclass 38, count 2 2006.280.08:12:31.03#ibcon#read 3, iclass 38, count 2 2006.280.08:12:31.03#ibcon#about to read 4, iclass 38, count 2 2006.280.08:12:31.03#ibcon#read 4, iclass 38, count 2 2006.280.08:12:31.03#ibcon#about to read 5, iclass 38, count 2 2006.280.08:12:31.03#ibcon#read 5, iclass 38, count 2 2006.280.08:12:31.03#ibcon#about to read 6, iclass 38, count 2 2006.280.08:12:31.03#ibcon#read 6, iclass 38, count 2 2006.280.08:12:31.03#ibcon#end of sib2, iclass 38, count 2 2006.280.08:12:31.03#ibcon#*mode == 0, iclass 38, count 2 2006.280.08:12:31.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.08:12:31.03#ibcon#[25=AT02-06\r\n] 2006.280.08:12:31.03#ibcon#*before write, iclass 38, count 2 2006.280.08:12:31.03#ibcon#enter sib2, iclass 38, count 2 2006.280.08:12:31.03#ibcon#flushed, iclass 38, count 2 2006.280.08:12:31.03#ibcon#about to write, iclass 38, count 2 2006.280.08:12:31.03#ibcon#wrote, iclass 38, count 2 2006.280.08:12:31.03#ibcon#about to read 3, iclass 38, count 2 2006.280.08:12:31.06#ibcon#read 3, iclass 38, count 2 2006.280.08:12:31.06#ibcon#about to read 4, iclass 38, count 2 2006.280.08:12:31.06#ibcon#read 4, iclass 38, count 2 2006.280.08:12:31.06#ibcon#about to read 5, iclass 38, count 2 2006.280.08:12:31.06#ibcon#read 5, iclass 38, count 2 2006.280.08:12:31.06#ibcon#about to read 6, iclass 38, count 2 2006.280.08:12:31.06#ibcon#read 6, iclass 38, count 2 2006.280.08:12:31.06#ibcon#end of sib2, iclass 38, count 2 2006.280.08:12:31.06#ibcon#*after write, iclass 38, count 2 2006.280.08:12:31.06#ibcon#*before return 0, iclass 38, count 2 2006.280.08:12:31.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:31.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:31.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.08:12:31.06#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:31.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:31.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:31.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:31.18#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:12:31.18#ibcon#first serial, iclass 38, count 0 2006.280.08:12:31.18#ibcon#enter sib2, iclass 38, count 0 2006.280.08:12:31.18#ibcon#flushed, iclass 38, count 0 2006.280.08:12:31.18#ibcon#about to write, iclass 38, count 0 2006.280.08:12:31.18#ibcon#wrote, iclass 38, count 0 2006.280.08:12:31.18#ibcon#about to read 3, iclass 38, count 0 2006.280.08:12:31.20#ibcon#read 3, iclass 38, count 0 2006.280.08:12:31.20#ibcon#about to read 4, iclass 38, count 0 2006.280.08:12:31.20#ibcon#read 4, iclass 38, count 0 2006.280.08:12:31.20#ibcon#about to read 5, iclass 38, count 0 2006.280.08:12:31.20#ibcon#read 5, iclass 38, count 0 2006.280.08:12:31.20#ibcon#about to read 6, iclass 38, count 0 2006.280.08:12:31.20#ibcon#read 6, iclass 38, count 0 2006.280.08:12:31.20#ibcon#end of sib2, iclass 38, count 0 2006.280.08:12:31.20#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:12:31.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:12:31.20#ibcon#[25=USB\r\n] 2006.280.08:12:31.20#ibcon#*before write, iclass 38, count 0 2006.280.08:12:31.20#ibcon#enter sib2, iclass 38, count 0 2006.280.08:12:31.20#ibcon#flushed, iclass 38, count 0 2006.280.08:12:31.20#ibcon#about to write, iclass 38, count 0 2006.280.08:12:31.20#ibcon#wrote, iclass 38, count 0 2006.280.08:12:31.20#ibcon#about to read 3, iclass 38, count 0 2006.280.08:12:31.23#ibcon#read 3, iclass 38, count 0 2006.280.08:12:31.23#ibcon#about to read 4, iclass 38, count 0 2006.280.08:12:31.23#ibcon#read 4, iclass 38, count 0 2006.280.08:12:31.23#ibcon#about to read 5, iclass 38, count 0 2006.280.08:12:31.23#ibcon#read 5, iclass 38, count 0 2006.280.08:12:31.23#ibcon#about to read 6, iclass 38, count 0 2006.280.08:12:31.23#ibcon#read 6, iclass 38, count 0 2006.280.08:12:31.23#ibcon#end of sib2, iclass 38, count 0 2006.280.08:12:31.23#ibcon#*after write, iclass 38, count 0 2006.280.08:12:31.23#ibcon#*before return 0, iclass 38, count 0 2006.280.08:12:31.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:31.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:31.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:12:31.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:12:31.23$vc4f8/valo=3,672.99 2006.280.08:12:31.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.08:12:31.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.08:12:31.23#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:31.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:31.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:31.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:31.23#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:12:31.23#ibcon#first serial, iclass 40, count 0 2006.280.08:12:31.23#ibcon#enter sib2, iclass 40, count 0 2006.280.08:12:31.23#ibcon#flushed, iclass 40, count 0 2006.280.08:12:31.23#ibcon#about to write, iclass 40, count 0 2006.280.08:12:31.23#ibcon#wrote, iclass 40, count 0 2006.280.08:12:31.23#ibcon#about to read 3, iclass 40, count 0 2006.280.08:12:31.25#ibcon#read 3, iclass 40, count 0 2006.280.08:12:31.25#ibcon#about to read 4, iclass 40, count 0 2006.280.08:12:31.25#ibcon#read 4, iclass 40, count 0 2006.280.08:12:31.25#ibcon#about to read 5, iclass 40, count 0 2006.280.08:12:31.25#ibcon#read 5, iclass 40, count 0 2006.280.08:12:31.25#ibcon#about to read 6, iclass 40, count 0 2006.280.08:12:31.25#ibcon#read 6, iclass 40, count 0 2006.280.08:12:31.25#ibcon#end of sib2, iclass 40, count 0 2006.280.08:12:31.25#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:12:31.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:12:31.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:12:31.25#ibcon#*before write, iclass 40, count 0 2006.280.08:12:31.25#ibcon#enter sib2, iclass 40, count 0 2006.280.08:12:31.25#ibcon#flushed, iclass 40, count 0 2006.280.08:12:31.25#ibcon#about to write, iclass 40, count 0 2006.280.08:12:31.25#ibcon#wrote, iclass 40, count 0 2006.280.08:12:31.25#ibcon#about to read 3, iclass 40, count 0 2006.280.08:12:31.29#ibcon#read 3, iclass 40, count 0 2006.280.08:12:31.29#ibcon#about to read 4, iclass 40, count 0 2006.280.08:12:31.29#ibcon#read 4, iclass 40, count 0 2006.280.08:12:31.29#ibcon#about to read 5, iclass 40, count 0 2006.280.08:12:31.29#ibcon#read 5, iclass 40, count 0 2006.280.08:12:31.29#ibcon#about to read 6, iclass 40, count 0 2006.280.08:12:31.29#ibcon#read 6, iclass 40, count 0 2006.280.08:12:31.29#ibcon#end of sib2, iclass 40, count 0 2006.280.08:12:31.29#ibcon#*after write, iclass 40, count 0 2006.280.08:12:31.29#ibcon#*before return 0, iclass 40, count 0 2006.280.08:12:31.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:31.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:31.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:12:31.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:12:31.29$vc4f8/va=3,6 2006.280.08:12:31.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.08:12:31.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.08:12:31.31#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:31.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:12:31.32#abcon#<5=/14 1.4 3.4 20.43 61 987.5\r\n> 2006.280.08:12:31.34#abcon#{5=INTERFACE CLEAR} 2006.280.08:12:31.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:12:31.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:12:31.35#ibcon#enter wrdev, iclass 5, count 2 2006.280.08:12:31.35#ibcon#first serial, iclass 5, count 2 2006.280.08:12:31.35#ibcon#enter sib2, iclass 5, count 2 2006.280.08:12:31.35#ibcon#flushed, iclass 5, count 2 2006.280.08:12:31.35#ibcon#about to write, iclass 5, count 2 2006.280.08:12:31.35#ibcon#wrote, iclass 5, count 2 2006.280.08:12:31.35#ibcon#about to read 3, iclass 5, count 2 2006.280.08:12:31.37#ibcon#read 3, iclass 5, count 2 2006.280.08:12:31.37#ibcon#about to read 4, iclass 5, count 2 2006.280.08:12:31.37#ibcon#read 4, iclass 5, count 2 2006.280.08:12:31.37#ibcon#about to read 5, iclass 5, count 2 2006.280.08:12:31.37#ibcon#read 5, iclass 5, count 2 2006.280.08:12:31.37#ibcon#about to read 6, iclass 5, count 2 2006.280.08:12:31.37#ibcon#read 6, iclass 5, count 2 2006.280.08:12:31.37#ibcon#end of sib2, iclass 5, count 2 2006.280.08:12:31.37#ibcon#*mode == 0, iclass 5, count 2 2006.280.08:12:31.37#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.08:12:31.37#ibcon#[25=AT03-06\r\n] 2006.280.08:12:31.37#ibcon#*before write, iclass 5, count 2 2006.280.08:12:31.37#ibcon#enter sib2, iclass 5, count 2 2006.280.08:12:31.37#ibcon#flushed, iclass 5, count 2 2006.280.08:12:31.37#ibcon#about to write, iclass 5, count 2 2006.280.08:12:31.37#ibcon#wrote, iclass 5, count 2 2006.280.08:12:31.37#ibcon#about to read 3, iclass 5, count 2 2006.280.08:12:31.40#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:12:31.40#ibcon#read 3, iclass 5, count 2 2006.280.08:12:31.40#ibcon#about to read 4, iclass 5, count 2 2006.280.08:12:31.40#ibcon#read 4, iclass 5, count 2 2006.280.08:12:31.40#ibcon#about to read 5, iclass 5, count 2 2006.280.08:12:31.40#ibcon#read 5, iclass 5, count 2 2006.280.08:12:31.40#ibcon#about to read 6, iclass 5, count 2 2006.280.08:12:31.40#ibcon#read 6, iclass 5, count 2 2006.280.08:12:31.40#ibcon#end of sib2, iclass 5, count 2 2006.280.08:12:31.40#ibcon#*after write, iclass 5, count 2 2006.280.08:12:31.40#ibcon#*before return 0, iclass 5, count 2 2006.280.08:12:31.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:12:31.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:12:31.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.08:12:31.40#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:31.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:12:31.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:12:31.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:12:31.52#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:12:31.52#ibcon#first serial, iclass 5, count 0 2006.280.08:12:31.52#ibcon#enter sib2, iclass 5, count 0 2006.280.08:12:31.52#ibcon#flushed, iclass 5, count 0 2006.280.08:12:31.52#ibcon#about to write, iclass 5, count 0 2006.280.08:12:31.52#ibcon#wrote, iclass 5, count 0 2006.280.08:12:31.52#ibcon#about to read 3, iclass 5, count 0 2006.280.08:12:31.54#ibcon#read 3, iclass 5, count 0 2006.280.08:12:31.54#ibcon#about to read 4, iclass 5, count 0 2006.280.08:12:31.54#ibcon#read 4, iclass 5, count 0 2006.280.08:12:31.54#ibcon#about to read 5, iclass 5, count 0 2006.280.08:12:31.54#ibcon#read 5, iclass 5, count 0 2006.280.08:12:31.54#ibcon#about to read 6, iclass 5, count 0 2006.280.08:12:31.54#ibcon#read 6, iclass 5, count 0 2006.280.08:12:31.54#ibcon#end of sib2, iclass 5, count 0 2006.280.08:12:31.54#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:12:31.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:12:31.54#ibcon#[25=USB\r\n] 2006.280.08:12:31.54#ibcon#*before write, iclass 5, count 0 2006.280.08:12:31.54#ibcon#enter sib2, iclass 5, count 0 2006.280.08:12:31.54#ibcon#flushed, iclass 5, count 0 2006.280.08:12:31.54#ibcon#about to write, iclass 5, count 0 2006.280.08:12:31.54#ibcon#wrote, iclass 5, count 0 2006.280.08:12:31.54#ibcon#about to read 3, iclass 5, count 0 2006.280.08:12:31.57#ibcon#read 3, iclass 5, count 0 2006.280.08:12:31.57#ibcon#about to read 4, iclass 5, count 0 2006.280.08:12:31.57#ibcon#read 4, iclass 5, count 0 2006.280.08:12:31.57#ibcon#about to read 5, iclass 5, count 0 2006.280.08:12:31.57#ibcon#read 5, iclass 5, count 0 2006.280.08:12:31.57#ibcon#about to read 6, iclass 5, count 0 2006.280.08:12:31.57#ibcon#read 6, iclass 5, count 0 2006.280.08:12:31.57#ibcon#end of sib2, iclass 5, count 0 2006.280.08:12:31.57#ibcon#*after write, iclass 5, count 0 2006.280.08:12:31.57#ibcon#*before return 0, iclass 5, count 0 2006.280.08:12:31.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:12:31.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:12:31.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:12:31.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:12:31.57$vc4f8/valo=4,832.99 2006.280.08:12:31.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:12:31.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:12:31.57#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:31.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:31.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:31.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:31.57#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:12:31.57#ibcon#first serial, iclass 12, count 0 2006.280.08:12:31.57#ibcon#enter sib2, iclass 12, count 0 2006.280.08:12:31.57#ibcon#flushed, iclass 12, count 0 2006.280.08:12:31.57#ibcon#about to write, iclass 12, count 0 2006.280.08:12:31.57#ibcon#wrote, iclass 12, count 0 2006.280.08:12:31.57#ibcon#about to read 3, iclass 12, count 0 2006.280.08:12:31.59#ibcon#read 3, iclass 12, count 0 2006.280.08:12:31.59#ibcon#about to read 4, iclass 12, count 0 2006.280.08:12:31.59#ibcon#read 4, iclass 12, count 0 2006.280.08:12:31.59#ibcon#about to read 5, iclass 12, count 0 2006.280.08:12:31.59#ibcon#read 5, iclass 12, count 0 2006.280.08:12:31.59#ibcon#about to read 6, iclass 12, count 0 2006.280.08:12:31.59#ibcon#read 6, iclass 12, count 0 2006.280.08:12:31.59#ibcon#end of sib2, iclass 12, count 0 2006.280.08:12:31.59#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:12:31.59#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:12:31.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:12:31.59#ibcon#*before write, iclass 12, count 0 2006.280.08:12:31.59#ibcon#enter sib2, iclass 12, count 0 2006.280.08:12:31.59#ibcon#flushed, iclass 12, count 0 2006.280.08:12:31.59#ibcon#about to write, iclass 12, count 0 2006.280.08:12:31.59#ibcon#wrote, iclass 12, count 0 2006.280.08:12:31.59#ibcon#about to read 3, iclass 12, count 0 2006.280.08:12:31.63#ibcon#read 3, iclass 12, count 0 2006.280.08:12:31.63#ibcon#about to read 4, iclass 12, count 0 2006.280.08:12:31.63#ibcon#read 4, iclass 12, count 0 2006.280.08:12:31.63#ibcon#about to read 5, iclass 12, count 0 2006.280.08:12:31.63#ibcon#read 5, iclass 12, count 0 2006.280.08:12:31.63#ibcon#about to read 6, iclass 12, count 0 2006.280.08:12:31.63#ibcon#read 6, iclass 12, count 0 2006.280.08:12:31.63#ibcon#end of sib2, iclass 12, count 0 2006.280.08:12:31.63#ibcon#*after write, iclass 12, count 0 2006.280.08:12:31.63#ibcon#*before return 0, iclass 12, count 0 2006.280.08:12:31.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:31.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:31.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:12:31.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:12:31.63$vc4f8/va=4,6 2006.280.08:12:31.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:12:31.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:12:31.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:31.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:31.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:31.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:31.69#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:12:31.69#ibcon#first serial, iclass 14, count 2 2006.280.08:12:31.69#ibcon#enter sib2, iclass 14, count 2 2006.280.08:12:31.69#ibcon#flushed, iclass 14, count 2 2006.280.08:12:31.69#ibcon#about to write, iclass 14, count 2 2006.280.08:12:31.69#ibcon#wrote, iclass 14, count 2 2006.280.08:12:31.69#ibcon#about to read 3, iclass 14, count 2 2006.280.08:12:31.71#ibcon#read 3, iclass 14, count 2 2006.280.08:12:31.71#ibcon#about to read 4, iclass 14, count 2 2006.280.08:12:31.71#ibcon#read 4, iclass 14, count 2 2006.280.08:12:31.71#ibcon#about to read 5, iclass 14, count 2 2006.280.08:12:31.71#ibcon#read 5, iclass 14, count 2 2006.280.08:12:31.71#ibcon#about to read 6, iclass 14, count 2 2006.280.08:12:31.71#ibcon#read 6, iclass 14, count 2 2006.280.08:12:31.71#ibcon#end of sib2, iclass 14, count 2 2006.280.08:12:31.71#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:12:31.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:12:31.71#ibcon#[25=AT04-06\r\n] 2006.280.08:12:31.71#ibcon#*before write, iclass 14, count 2 2006.280.08:12:31.71#ibcon#enter sib2, iclass 14, count 2 2006.280.08:12:31.71#ibcon#flushed, iclass 14, count 2 2006.280.08:12:31.71#ibcon#about to write, iclass 14, count 2 2006.280.08:12:31.71#ibcon#wrote, iclass 14, count 2 2006.280.08:12:31.71#ibcon#about to read 3, iclass 14, count 2 2006.280.08:12:31.75#ibcon#read 3, iclass 14, count 2 2006.280.08:12:31.75#ibcon#about to read 4, iclass 14, count 2 2006.280.08:12:31.75#ibcon#read 4, iclass 14, count 2 2006.280.08:12:31.75#ibcon#about to read 5, iclass 14, count 2 2006.280.08:12:31.75#ibcon#read 5, iclass 14, count 2 2006.280.08:12:31.75#ibcon#about to read 6, iclass 14, count 2 2006.280.08:12:31.75#ibcon#read 6, iclass 14, count 2 2006.280.08:12:31.75#ibcon#end of sib2, iclass 14, count 2 2006.280.08:12:31.75#ibcon#*after write, iclass 14, count 2 2006.280.08:12:31.75#ibcon#*before return 0, iclass 14, count 2 2006.280.08:12:31.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:31.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:31.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:12:31.75#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:31.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:31.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:31.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:31.87#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:12:31.87#ibcon#first serial, iclass 14, count 0 2006.280.08:12:31.87#ibcon#enter sib2, iclass 14, count 0 2006.280.08:12:31.87#ibcon#flushed, iclass 14, count 0 2006.280.08:12:31.87#ibcon#about to write, iclass 14, count 0 2006.280.08:12:31.87#ibcon#wrote, iclass 14, count 0 2006.280.08:12:31.87#ibcon#about to read 3, iclass 14, count 0 2006.280.08:12:31.89#ibcon#read 3, iclass 14, count 0 2006.280.08:12:31.89#ibcon#about to read 4, iclass 14, count 0 2006.280.08:12:31.89#ibcon#read 4, iclass 14, count 0 2006.280.08:12:31.89#ibcon#about to read 5, iclass 14, count 0 2006.280.08:12:31.89#ibcon#read 5, iclass 14, count 0 2006.280.08:12:31.89#ibcon#about to read 6, iclass 14, count 0 2006.280.08:12:31.89#ibcon#read 6, iclass 14, count 0 2006.280.08:12:31.89#ibcon#end of sib2, iclass 14, count 0 2006.280.08:12:31.89#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:12:31.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:12:31.89#ibcon#[25=USB\r\n] 2006.280.08:12:31.89#ibcon#*before write, iclass 14, count 0 2006.280.08:12:31.89#ibcon#enter sib2, iclass 14, count 0 2006.280.08:12:31.89#ibcon#flushed, iclass 14, count 0 2006.280.08:12:31.89#ibcon#about to write, iclass 14, count 0 2006.280.08:12:31.89#ibcon#wrote, iclass 14, count 0 2006.280.08:12:31.89#ibcon#about to read 3, iclass 14, count 0 2006.280.08:12:31.92#ibcon#read 3, iclass 14, count 0 2006.280.08:12:31.92#ibcon#about to read 4, iclass 14, count 0 2006.280.08:12:31.92#ibcon#read 4, iclass 14, count 0 2006.280.08:12:31.92#ibcon#about to read 5, iclass 14, count 0 2006.280.08:12:31.92#ibcon#read 5, iclass 14, count 0 2006.280.08:12:31.92#ibcon#about to read 6, iclass 14, count 0 2006.280.08:12:31.92#ibcon#read 6, iclass 14, count 0 2006.280.08:12:31.92#ibcon#end of sib2, iclass 14, count 0 2006.280.08:12:31.92#ibcon#*after write, iclass 14, count 0 2006.280.08:12:31.92#ibcon#*before return 0, iclass 14, count 0 2006.280.08:12:31.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:31.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:31.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:12:31.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:12:31.92$vc4f8/valo=5,652.99 2006.280.08:12:31.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:12:31.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:12:31.92#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:31.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:31.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:31.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:31.92#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:12:31.92#ibcon#first serial, iclass 16, count 0 2006.280.08:12:31.92#ibcon#enter sib2, iclass 16, count 0 2006.280.08:12:31.92#ibcon#flushed, iclass 16, count 0 2006.280.08:12:31.92#ibcon#about to write, iclass 16, count 0 2006.280.08:12:31.92#ibcon#wrote, iclass 16, count 0 2006.280.08:12:31.92#ibcon#about to read 3, iclass 16, count 0 2006.280.08:12:31.94#ibcon#read 3, iclass 16, count 0 2006.280.08:12:31.94#ibcon#about to read 4, iclass 16, count 0 2006.280.08:12:31.94#ibcon#read 4, iclass 16, count 0 2006.280.08:12:31.94#ibcon#about to read 5, iclass 16, count 0 2006.280.08:12:31.94#ibcon#read 5, iclass 16, count 0 2006.280.08:12:31.94#ibcon#about to read 6, iclass 16, count 0 2006.280.08:12:31.94#ibcon#read 6, iclass 16, count 0 2006.280.08:12:31.94#ibcon#end of sib2, iclass 16, count 0 2006.280.08:12:31.94#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:12:31.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:12:31.94#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:12:31.94#ibcon#*before write, iclass 16, count 0 2006.280.08:12:31.94#ibcon#enter sib2, iclass 16, count 0 2006.280.08:12:31.94#ibcon#flushed, iclass 16, count 0 2006.280.08:12:31.94#ibcon#about to write, iclass 16, count 0 2006.280.08:12:31.94#ibcon#wrote, iclass 16, count 0 2006.280.08:12:31.94#ibcon#about to read 3, iclass 16, count 0 2006.280.08:12:31.98#ibcon#read 3, iclass 16, count 0 2006.280.08:12:31.98#ibcon#about to read 4, iclass 16, count 0 2006.280.08:12:31.98#ibcon#read 4, iclass 16, count 0 2006.280.08:12:31.98#ibcon#about to read 5, iclass 16, count 0 2006.280.08:12:31.98#ibcon#read 5, iclass 16, count 0 2006.280.08:12:31.98#ibcon#about to read 6, iclass 16, count 0 2006.280.08:12:31.98#ibcon#read 6, iclass 16, count 0 2006.280.08:12:31.98#ibcon#end of sib2, iclass 16, count 0 2006.280.08:12:31.98#ibcon#*after write, iclass 16, count 0 2006.280.08:12:31.98#ibcon#*before return 0, iclass 16, count 0 2006.280.08:12:31.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:31.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:31.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:12:31.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:12:31.98$vc4f8/va=5,7 2006.280.08:12:31.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:12:31.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:12:31.98#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:31.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:32.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:32.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:32.04#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:12:32.04#ibcon#first serial, iclass 18, count 2 2006.280.08:12:32.04#ibcon#enter sib2, iclass 18, count 2 2006.280.08:12:32.04#ibcon#flushed, iclass 18, count 2 2006.280.08:12:32.04#ibcon#about to write, iclass 18, count 2 2006.280.08:12:32.04#ibcon#wrote, iclass 18, count 2 2006.280.08:12:32.04#ibcon#about to read 3, iclass 18, count 2 2006.280.08:12:32.06#ibcon#read 3, iclass 18, count 2 2006.280.08:12:32.06#ibcon#about to read 4, iclass 18, count 2 2006.280.08:12:32.06#ibcon#read 4, iclass 18, count 2 2006.280.08:12:32.06#ibcon#about to read 5, iclass 18, count 2 2006.280.08:12:32.06#ibcon#read 5, iclass 18, count 2 2006.280.08:12:32.06#ibcon#about to read 6, iclass 18, count 2 2006.280.08:12:32.06#ibcon#read 6, iclass 18, count 2 2006.280.08:12:32.06#ibcon#end of sib2, iclass 18, count 2 2006.280.08:12:32.06#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:12:32.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:12:32.06#ibcon#[25=AT05-07\r\n] 2006.280.08:12:32.06#ibcon#*before write, iclass 18, count 2 2006.280.08:12:32.06#ibcon#enter sib2, iclass 18, count 2 2006.280.08:12:32.06#ibcon#flushed, iclass 18, count 2 2006.280.08:12:32.06#ibcon#about to write, iclass 18, count 2 2006.280.08:12:32.06#ibcon#wrote, iclass 18, count 2 2006.280.08:12:32.06#ibcon#about to read 3, iclass 18, count 2 2006.280.08:12:32.09#ibcon#read 3, iclass 18, count 2 2006.280.08:12:32.09#ibcon#about to read 4, iclass 18, count 2 2006.280.08:12:32.09#ibcon#read 4, iclass 18, count 2 2006.280.08:12:32.09#ibcon#about to read 5, iclass 18, count 2 2006.280.08:12:32.09#ibcon#read 5, iclass 18, count 2 2006.280.08:12:32.09#ibcon#about to read 6, iclass 18, count 2 2006.280.08:12:32.09#ibcon#read 6, iclass 18, count 2 2006.280.08:12:32.09#ibcon#end of sib2, iclass 18, count 2 2006.280.08:12:32.09#ibcon#*after write, iclass 18, count 2 2006.280.08:12:32.09#ibcon#*before return 0, iclass 18, count 2 2006.280.08:12:32.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:32.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:32.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:12:32.09#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:32.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:32.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:32.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:32.21#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:12:32.21#ibcon#first serial, iclass 18, count 0 2006.280.08:12:32.21#ibcon#enter sib2, iclass 18, count 0 2006.280.08:12:32.21#ibcon#flushed, iclass 18, count 0 2006.280.08:12:32.21#ibcon#about to write, iclass 18, count 0 2006.280.08:12:32.21#ibcon#wrote, iclass 18, count 0 2006.280.08:12:32.21#ibcon#about to read 3, iclass 18, count 0 2006.280.08:12:32.23#ibcon#read 3, iclass 18, count 0 2006.280.08:12:32.23#ibcon#about to read 4, iclass 18, count 0 2006.280.08:12:32.23#ibcon#read 4, iclass 18, count 0 2006.280.08:12:32.23#ibcon#about to read 5, iclass 18, count 0 2006.280.08:12:32.23#ibcon#read 5, iclass 18, count 0 2006.280.08:12:32.23#ibcon#about to read 6, iclass 18, count 0 2006.280.08:12:32.23#ibcon#read 6, iclass 18, count 0 2006.280.08:12:32.23#ibcon#end of sib2, iclass 18, count 0 2006.280.08:12:32.23#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:12:32.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:12:32.23#ibcon#[25=USB\r\n] 2006.280.08:12:32.23#ibcon#*before write, iclass 18, count 0 2006.280.08:12:32.23#ibcon#enter sib2, iclass 18, count 0 2006.280.08:12:32.23#ibcon#flushed, iclass 18, count 0 2006.280.08:12:32.23#ibcon#about to write, iclass 18, count 0 2006.280.08:12:32.23#ibcon#wrote, iclass 18, count 0 2006.280.08:12:32.23#ibcon#about to read 3, iclass 18, count 0 2006.280.08:12:32.26#ibcon#read 3, iclass 18, count 0 2006.280.08:12:32.26#ibcon#about to read 4, iclass 18, count 0 2006.280.08:12:32.26#ibcon#read 4, iclass 18, count 0 2006.280.08:12:32.26#ibcon#about to read 5, iclass 18, count 0 2006.280.08:12:32.26#ibcon#read 5, iclass 18, count 0 2006.280.08:12:32.26#ibcon#about to read 6, iclass 18, count 0 2006.280.08:12:32.26#ibcon#read 6, iclass 18, count 0 2006.280.08:12:32.26#ibcon#end of sib2, iclass 18, count 0 2006.280.08:12:32.26#ibcon#*after write, iclass 18, count 0 2006.280.08:12:32.26#ibcon#*before return 0, iclass 18, count 0 2006.280.08:12:32.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:32.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:32.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:12:32.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:12:32.26$vc4f8/valo=6,772.99 2006.280.08:12:32.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:12:32.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:12:32.26#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:32.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:32.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:32.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:32.26#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:12:32.26#ibcon#first serial, iclass 20, count 0 2006.280.08:12:32.26#ibcon#enter sib2, iclass 20, count 0 2006.280.08:12:32.26#ibcon#flushed, iclass 20, count 0 2006.280.08:12:32.26#ibcon#about to write, iclass 20, count 0 2006.280.08:12:32.26#ibcon#wrote, iclass 20, count 0 2006.280.08:12:32.26#ibcon#about to read 3, iclass 20, count 0 2006.280.08:12:32.28#ibcon#read 3, iclass 20, count 0 2006.280.08:12:32.28#ibcon#about to read 4, iclass 20, count 0 2006.280.08:12:32.28#ibcon#read 4, iclass 20, count 0 2006.280.08:12:32.28#ibcon#about to read 5, iclass 20, count 0 2006.280.08:12:32.28#ibcon#read 5, iclass 20, count 0 2006.280.08:12:32.28#ibcon#about to read 6, iclass 20, count 0 2006.280.08:12:32.28#ibcon#read 6, iclass 20, count 0 2006.280.08:12:32.28#ibcon#end of sib2, iclass 20, count 0 2006.280.08:12:32.28#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:12:32.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:12:32.28#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:12:32.28#ibcon#*before write, iclass 20, count 0 2006.280.08:12:32.28#ibcon#enter sib2, iclass 20, count 0 2006.280.08:12:32.28#ibcon#flushed, iclass 20, count 0 2006.280.08:12:32.28#ibcon#about to write, iclass 20, count 0 2006.280.08:12:32.28#ibcon#wrote, iclass 20, count 0 2006.280.08:12:32.28#ibcon#about to read 3, iclass 20, count 0 2006.280.08:12:32.32#ibcon#read 3, iclass 20, count 0 2006.280.08:12:32.32#ibcon#about to read 4, iclass 20, count 0 2006.280.08:12:32.32#ibcon#read 4, iclass 20, count 0 2006.280.08:12:32.32#ibcon#about to read 5, iclass 20, count 0 2006.280.08:12:32.32#ibcon#read 5, iclass 20, count 0 2006.280.08:12:32.32#ibcon#about to read 6, iclass 20, count 0 2006.280.08:12:32.32#ibcon#read 6, iclass 20, count 0 2006.280.08:12:32.32#ibcon#end of sib2, iclass 20, count 0 2006.280.08:12:32.32#ibcon#*after write, iclass 20, count 0 2006.280.08:12:32.32#ibcon#*before return 0, iclass 20, count 0 2006.280.08:12:32.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:32.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:32.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:12:32.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:12:32.32$vc4f8/va=6,6 2006.280.08:12:32.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.08:12:32.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.08:12:32.32#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:32.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:32.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:32.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:32.38#ibcon#enter wrdev, iclass 22, count 2 2006.280.08:12:32.38#ibcon#first serial, iclass 22, count 2 2006.280.08:12:32.38#ibcon#enter sib2, iclass 22, count 2 2006.280.08:12:32.38#ibcon#flushed, iclass 22, count 2 2006.280.08:12:32.38#ibcon#about to write, iclass 22, count 2 2006.280.08:12:32.38#ibcon#wrote, iclass 22, count 2 2006.280.08:12:32.38#ibcon#about to read 3, iclass 22, count 2 2006.280.08:12:32.40#ibcon#read 3, iclass 22, count 2 2006.280.08:12:32.40#ibcon#about to read 4, iclass 22, count 2 2006.280.08:12:32.40#ibcon#read 4, iclass 22, count 2 2006.280.08:12:32.40#ibcon#about to read 5, iclass 22, count 2 2006.280.08:12:32.40#ibcon#read 5, iclass 22, count 2 2006.280.08:12:32.40#ibcon#about to read 6, iclass 22, count 2 2006.280.08:12:32.40#ibcon#read 6, iclass 22, count 2 2006.280.08:12:32.40#ibcon#end of sib2, iclass 22, count 2 2006.280.08:12:32.40#ibcon#*mode == 0, iclass 22, count 2 2006.280.08:12:32.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.08:12:32.40#ibcon#[25=AT06-06\r\n] 2006.280.08:12:32.40#ibcon#*before write, iclass 22, count 2 2006.280.08:12:32.40#ibcon#enter sib2, iclass 22, count 2 2006.280.08:12:32.40#ibcon#flushed, iclass 22, count 2 2006.280.08:12:32.40#ibcon#about to write, iclass 22, count 2 2006.280.08:12:32.40#ibcon#wrote, iclass 22, count 2 2006.280.08:12:32.40#ibcon#about to read 3, iclass 22, count 2 2006.280.08:12:32.43#ibcon#read 3, iclass 22, count 2 2006.280.08:12:32.43#ibcon#about to read 4, iclass 22, count 2 2006.280.08:12:32.43#ibcon#read 4, iclass 22, count 2 2006.280.08:12:32.43#ibcon#about to read 5, iclass 22, count 2 2006.280.08:12:32.43#ibcon#read 5, iclass 22, count 2 2006.280.08:12:32.43#ibcon#about to read 6, iclass 22, count 2 2006.280.08:12:32.43#ibcon#read 6, iclass 22, count 2 2006.280.08:12:32.43#ibcon#end of sib2, iclass 22, count 2 2006.280.08:12:32.43#ibcon#*after write, iclass 22, count 2 2006.280.08:12:32.43#ibcon#*before return 0, iclass 22, count 2 2006.280.08:12:32.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:32.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:32.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.08:12:32.43#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:32.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:12:32.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:12:32.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:12:32.55#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:12:32.55#ibcon#first serial, iclass 22, count 0 2006.280.08:12:32.55#ibcon#enter sib2, iclass 22, count 0 2006.280.08:12:32.55#ibcon#flushed, iclass 22, count 0 2006.280.08:12:32.55#ibcon#about to write, iclass 22, count 0 2006.280.08:12:32.55#ibcon#wrote, iclass 22, count 0 2006.280.08:12:32.55#ibcon#about to read 3, iclass 22, count 0 2006.280.08:12:32.57#ibcon#read 3, iclass 22, count 0 2006.280.08:12:32.57#ibcon#about to read 4, iclass 22, count 0 2006.280.08:12:32.57#ibcon#read 4, iclass 22, count 0 2006.280.08:12:32.57#ibcon#about to read 5, iclass 22, count 0 2006.280.08:12:32.57#ibcon#read 5, iclass 22, count 0 2006.280.08:12:32.57#ibcon#about to read 6, iclass 22, count 0 2006.280.08:12:32.57#ibcon#read 6, iclass 22, count 0 2006.280.08:12:32.57#ibcon#end of sib2, iclass 22, count 0 2006.280.08:12:32.57#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:12:32.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:12:32.57#ibcon#[25=USB\r\n] 2006.280.08:12:32.57#ibcon#*before write, iclass 22, count 0 2006.280.08:12:32.57#ibcon#enter sib2, iclass 22, count 0 2006.280.08:12:32.57#ibcon#flushed, iclass 22, count 0 2006.280.08:12:32.57#ibcon#about to write, iclass 22, count 0 2006.280.08:12:32.57#ibcon#wrote, iclass 22, count 0 2006.280.08:12:32.57#ibcon#about to read 3, iclass 22, count 0 2006.280.08:12:32.60#ibcon#read 3, iclass 22, count 0 2006.280.08:12:32.60#ibcon#about to read 4, iclass 22, count 0 2006.280.08:12:32.60#ibcon#read 4, iclass 22, count 0 2006.280.08:12:32.60#ibcon#about to read 5, iclass 22, count 0 2006.280.08:12:32.60#ibcon#read 5, iclass 22, count 0 2006.280.08:12:32.60#ibcon#about to read 6, iclass 22, count 0 2006.280.08:12:32.60#ibcon#read 6, iclass 22, count 0 2006.280.08:12:32.60#ibcon#end of sib2, iclass 22, count 0 2006.280.08:12:32.60#ibcon#*after write, iclass 22, count 0 2006.280.08:12:32.60#ibcon#*before return 0, iclass 22, count 0 2006.280.08:12:32.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:12:32.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:12:32.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:12:32.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:12:32.60$vc4f8/valo=7,832.99 2006.280.08:12:32.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:12:32.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:12:32.60#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:32.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:12:32.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:12:32.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:12:32.60#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:12:32.60#ibcon#first serial, iclass 24, count 0 2006.280.08:12:32.60#ibcon#enter sib2, iclass 24, count 0 2006.280.08:12:32.60#ibcon#flushed, iclass 24, count 0 2006.280.08:12:32.60#ibcon#about to write, iclass 24, count 0 2006.280.08:12:32.60#ibcon#wrote, iclass 24, count 0 2006.280.08:12:32.60#ibcon#about to read 3, iclass 24, count 0 2006.280.08:12:32.62#ibcon#read 3, iclass 24, count 0 2006.280.08:12:32.62#ibcon#about to read 4, iclass 24, count 0 2006.280.08:12:32.62#ibcon#read 4, iclass 24, count 0 2006.280.08:12:32.62#ibcon#about to read 5, iclass 24, count 0 2006.280.08:12:32.62#ibcon#read 5, iclass 24, count 0 2006.280.08:12:32.62#ibcon#about to read 6, iclass 24, count 0 2006.280.08:12:32.62#ibcon#read 6, iclass 24, count 0 2006.280.08:12:32.62#ibcon#end of sib2, iclass 24, count 0 2006.280.08:12:32.62#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:12:32.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:12:32.62#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:12:32.62#ibcon#*before write, iclass 24, count 0 2006.280.08:12:32.62#ibcon#enter sib2, iclass 24, count 0 2006.280.08:12:32.62#ibcon#flushed, iclass 24, count 0 2006.280.08:12:32.62#ibcon#about to write, iclass 24, count 0 2006.280.08:12:32.62#ibcon#wrote, iclass 24, count 0 2006.280.08:12:32.62#ibcon#about to read 3, iclass 24, count 0 2006.280.08:12:32.66#ibcon#read 3, iclass 24, count 0 2006.280.08:12:32.66#ibcon#about to read 4, iclass 24, count 0 2006.280.08:12:32.66#ibcon#read 4, iclass 24, count 0 2006.280.08:12:32.66#ibcon#about to read 5, iclass 24, count 0 2006.280.08:12:32.66#ibcon#read 5, iclass 24, count 0 2006.280.08:12:32.66#ibcon#about to read 6, iclass 24, count 0 2006.280.08:12:32.66#ibcon#read 6, iclass 24, count 0 2006.280.08:12:32.66#ibcon#end of sib2, iclass 24, count 0 2006.280.08:12:32.66#ibcon#*after write, iclass 24, count 0 2006.280.08:12:32.66#ibcon#*before return 0, iclass 24, count 0 2006.280.08:12:32.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:12:32.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:12:32.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:12:32.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:12:32.66$vc4f8/va=7,6 2006.280.08:12:32.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:12:32.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:12:32.66#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:32.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:12:32.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:12:32.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:12:32.72#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:12:32.72#ibcon#first serial, iclass 26, count 2 2006.280.08:12:32.72#ibcon#enter sib2, iclass 26, count 2 2006.280.08:12:32.72#ibcon#flushed, iclass 26, count 2 2006.280.08:12:32.72#ibcon#about to write, iclass 26, count 2 2006.280.08:12:32.72#ibcon#wrote, iclass 26, count 2 2006.280.08:12:32.72#ibcon#about to read 3, iclass 26, count 2 2006.280.08:12:32.74#ibcon#read 3, iclass 26, count 2 2006.280.08:12:32.74#ibcon#about to read 4, iclass 26, count 2 2006.280.08:12:32.74#ibcon#read 4, iclass 26, count 2 2006.280.08:12:32.74#ibcon#about to read 5, iclass 26, count 2 2006.280.08:12:32.74#ibcon#read 5, iclass 26, count 2 2006.280.08:12:32.74#ibcon#about to read 6, iclass 26, count 2 2006.280.08:12:32.74#ibcon#read 6, iclass 26, count 2 2006.280.08:12:32.74#ibcon#end of sib2, iclass 26, count 2 2006.280.08:12:32.74#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:12:32.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:12:32.74#ibcon#[25=AT07-06\r\n] 2006.280.08:12:32.74#ibcon#*before write, iclass 26, count 2 2006.280.08:12:32.74#ibcon#enter sib2, iclass 26, count 2 2006.280.08:12:32.74#ibcon#flushed, iclass 26, count 2 2006.280.08:12:32.74#ibcon#about to write, iclass 26, count 2 2006.280.08:12:32.74#ibcon#wrote, iclass 26, count 2 2006.280.08:12:32.74#ibcon#about to read 3, iclass 26, count 2 2006.280.08:12:32.78#ibcon#read 3, iclass 26, count 2 2006.280.08:12:32.78#ibcon#about to read 4, iclass 26, count 2 2006.280.08:12:32.78#ibcon#read 4, iclass 26, count 2 2006.280.08:12:32.78#ibcon#about to read 5, iclass 26, count 2 2006.280.08:12:32.78#ibcon#read 5, iclass 26, count 2 2006.280.08:12:32.78#ibcon#about to read 6, iclass 26, count 2 2006.280.08:12:32.78#ibcon#read 6, iclass 26, count 2 2006.280.08:12:32.78#ibcon#end of sib2, iclass 26, count 2 2006.280.08:12:32.78#ibcon#*after write, iclass 26, count 2 2006.280.08:12:32.78#ibcon#*before return 0, iclass 26, count 2 2006.280.08:12:32.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:12:32.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:12:32.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:12:32.78#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:32.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:12:32.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:12:32.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:12:32.90#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:12:32.90#ibcon#first serial, iclass 26, count 0 2006.280.08:12:32.90#ibcon#enter sib2, iclass 26, count 0 2006.280.08:12:32.90#ibcon#flushed, iclass 26, count 0 2006.280.08:12:32.90#ibcon#about to write, iclass 26, count 0 2006.280.08:12:32.90#ibcon#wrote, iclass 26, count 0 2006.280.08:12:32.90#ibcon#about to read 3, iclass 26, count 0 2006.280.08:12:32.92#ibcon#read 3, iclass 26, count 0 2006.280.08:12:32.92#ibcon#about to read 4, iclass 26, count 0 2006.280.08:12:32.92#ibcon#read 4, iclass 26, count 0 2006.280.08:12:32.92#ibcon#about to read 5, iclass 26, count 0 2006.280.08:12:32.92#ibcon#read 5, iclass 26, count 0 2006.280.08:12:32.92#ibcon#about to read 6, iclass 26, count 0 2006.280.08:12:32.92#ibcon#read 6, iclass 26, count 0 2006.280.08:12:32.92#ibcon#end of sib2, iclass 26, count 0 2006.280.08:12:32.92#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:12:32.92#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:12:32.92#ibcon#[25=USB\r\n] 2006.280.08:12:32.92#ibcon#*before write, iclass 26, count 0 2006.280.08:12:32.92#ibcon#enter sib2, iclass 26, count 0 2006.280.08:12:32.92#ibcon#flushed, iclass 26, count 0 2006.280.08:12:32.92#ibcon#about to write, iclass 26, count 0 2006.280.08:12:32.92#ibcon#wrote, iclass 26, count 0 2006.280.08:12:32.92#ibcon#about to read 3, iclass 26, count 0 2006.280.08:12:32.95#ibcon#read 3, iclass 26, count 0 2006.280.08:12:32.95#ibcon#about to read 4, iclass 26, count 0 2006.280.08:12:32.95#ibcon#read 4, iclass 26, count 0 2006.280.08:12:32.95#ibcon#about to read 5, iclass 26, count 0 2006.280.08:12:32.95#ibcon#read 5, iclass 26, count 0 2006.280.08:12:32.95#ibcon#about to read 6, iclass 26, count 0 2006.280.08:12:32.95#ibcon#read 6, iclass 26, count 0 2006.280.08:12:32.95#ibcon#end of sib2, iclass 26, count 0 2006.280.08:12:32.95#ibcon#*after write, iclass 26, count 0 2006.280.08:12:32.95#ibcon#*before return 0, iclass 26, count 0 2006.280.08:12:32.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:12:32.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:12:32.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:12:32.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:12:32.95$vc4f8/valo=8,852.99 2006.280.08:12:32.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:12:32.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:12:32.95#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:32.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:12:32.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:12:32.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:12:32.95#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:12:32.95#ibcon#first serial, iclass 28, count 0 2006.280.08:12:32.95#ibcon#enter sib2, iclass 28, count 0 2006.280.08:12:32.95#ibcon#flushed, iclass 28, count 0 2006.280.08:12:32.95#ibcon#about to write, iclass 28, count 0 2006.280.08:12:32.95#ibcon#wrote, iclass 28, count 0 2006.280.08:12:32.95#ibcon#about to read 3, iclass 28, count 0 2006.280.08:12:32.97#ibcon#read 3, iclass 28, count 0 2006.280.08:12:32.97#ibcon#about to read 4, iclass 28, count 0 2006.280.08:12:32.97#ibcon#read 4, iclass 28, count 0 2006.280.08:12:32.97#ibcon#about to read 5, iclass 28, count 0 2006.280.08:12:32.98#ibcon#read 5, iclass 28, count 0 2006.280.08:12:32.98#ibcon#about to read 6, iclass 28, count 0 2006.280.08:12:32.98#ibcon#read 6, iclass 28, count 0 2006.280.08:12:32.98#ibcon#end of sib2, iclass 28, count 0 2006.280.08:12:32.98#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:12:32.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:12:32.98#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:12:32.98#ibcon#*before write, iclass 28, count 0 2006.280.08:12:32.98#ibcon#enter sib2, iclass 28, count 0 2006.280.08:12:32.98#ibcon#flushed, iclass 28, count 0 2006.280.08:12:32.98#ibcon#about to write, iclass 28, count 0 2006.280.08:12:32.98#ibcon#wrote, iclass 28, count 0 2006.280.08:12:32.98#ibcon#about to read 3, iclass 28, count 0 2006.280.08:12:33.03#ibcon#read 3, iclass 28, count 0 2006.280.08:12:33.03#ibcon#about to read 4, iclass 28, count 0 2006.280.08:12:33.03#ibcon#read 4, iclass 28, count 0 2006.280.08:12:33.03#ibcon#about to read 5, iclass 28, count 0 2006.280.08:12:33.03#ibcon#read 5, iclass 28, count 0 2006.280.08:12:33.03#ibcon#about to read 6, iclass 28, count 0 2006.280.08:12:33.03#ibcon#read 6, iclass 28, count 0 2006.280.08:12:33.03#ibcon#end of sib2, iclass 28, count 0 2006.280.08:12:33.03#ibcon#*after write, iclass 28, count 0 2006.280.08:12:33.03#ibcon#*before return 0, iclass 28, count 0 2006.280.08:12:33.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:12:33.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:12:33.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:12:33.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:12:33.03$vc4f8/va=8,6 2006.280.08:12:33.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.08:12:33.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.08:12:33.03#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:33.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:12:33.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:12:33.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:12:33.07#ibcon#enter wrdev, iclass 30, count 2 2006.280.08:12:33.07#ibcon#first serial, iclass 30, count 2 2006.280.08:12:33.07#ibcon#enter sib2, iclass 30, count 2 2006.280.08:12:33.07#ibcon#flushed, iclass 30, count 2 2006.280.08:12:33.07#ibcon#about to write, iclass 30, count 2 2006.280.08:12:33.07#ibcon#wrote, iclass 30, count 2 2006.280.08:12:33.07#ibcon#about to read 3, iclass 30, count 2 2006.280.08:12:33.09#ibcon#read 3, iclass 30, count 2 2006.280.08:12:33.09#ibcon#about to read 4, iclass 30, count 2 2006.280.08:12:33.09#ibcon#read 4, iclass 30, count 2 2006.280.08:12:33.09#ibcon#about to read 5, iclass 30, count 2 2006.280.08:12:33.09#ibcon#read 5, iclass 30, count 2 2006.280.08:12:33.09#ibcon#about to read 6, iclass 30, count 2 2006.280.08:12:33.09#ibcon#read 6, iclass 30, count 2 2006.280.08:12:33.09#ibcon#end of sib2, iclass 30, count 2 2006.280.08:12:33.09#ibcon#*mode == 0, iclass 30, count 2 2006.280.08:12:33.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.08:12:33.09#ibcon#[25=AT08-06\r\n] 2006.280.08:12:33.09#ibcon#*before write, iclass 30, count 2 2006.280.08:12:33.09#ibcon#enter sib2, iclass 30, count 2 2006.280.08:12:33.09#ibcon#flushed, iclass 30, count 2 2006.280.08:12:33.09#ibcon#about to write, iclass 30, count 2 2006.280.08:12:33.09#ibcon#wrote, iclass 30, count 2 2006.280.08:12:33.09#ibcon#about to read 3, iclass 30, count 2 2006.280.08:12:33.12#ibcon#read 3, iclass 30, count 2 2006.280.08:12:33.12#ibcon#about to read 4, iclass 30, count 2 2006.280.08:12:33.12#ibcon#read 4, iclass 30, count 2 2006.280.08:12:33.12#ibcon#about to read 5, iclass 30, count 2 2006.280.08:12:33.12#ibcon#read 5, iclass 30, count 2 2006.280.08:12:33.12#ibcon#about to read 6, iclass 30, count 2 2006.280.08:12:33.12#ibcon#read 6, iclass 30, count 2 2006.280.08:12:33.12#ibcon#end of sib2, iclass 30, count 2 2006.280.08:12:33.12#ibcon#*after write, iclass 30, count 2 2006.280.08:12:33.12#ibcon#*before return 0, iclass 30, count 2 2006.280.08:12:33.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:12:33.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:12:33.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.08:12:33.12#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:33.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:12:33.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:12:33.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:12:33.24#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:12:33.24#ibcon#first serial, iclass 30, count 0 2006.280.08:12:33.24#ibcon#enter sib2, iclass 30, count 0 2006.280.08:12:33.24#ibcon#flushed, iclass 30, count 0 2006.280.08:12:33.24#ibcon#about to write, iclass 30, count 0 2006.280.08:12:33.24#ibcon#wrote, iclass 30, count 0 2006.280.08:12:33.24#ibcon#about to read 3, iclass 30, count 0 2006.280.08:12:33.26#ibcon#read 3, iclass 30, count 0 2006.280.08:12:33.26#ibcon#about to read 4, iclass 30, count 0 2006.280.08:12:33.26#ibcon#read 4, iclass 30, count 0 2006.280.08:12:33.26#ibcon#about to read 5, iclass 30, count 0 2006.280.08:12:33.26#ibcon#read 5, iclass 30, count 0 2006.280.08:12:33.26#ibcon#about to read 6, iclass 30, count 0 2006.280.08:12:33.26#ibcon#read 6, iclass 30, count 0 2006.280.08:12:33.26#ibcon#end of sib2, iclass 30, count 0 2006.280.08:12:33.26#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:12:33.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:12:33.26#ibcon#[25=USB\r\n] 2006.280.08:12:33.26#ibcon#*before write, iclass 30, count 0 2006.280.08:12:33.26#ibcon#enter sib2, iclass 30, count 0 2006.280.08:12:33.26#ibcon#flushed, iclass 30, count 0 2006.280.08:12:33.26#ibcon#about to write, iclass 30, count 0 2006.280.08:12:33.26#ibcon#wrote, iclass 30, count 0 2006.280.08:12:33.26#ibcon#about to read 3, iclass 30, count 0 2006.280.08:12:33.29#ibcon#read 3, iclass 30, count 0 2006.280.08:12:33.29#ibcon#about to read 4, iclass 30, count 0 2006.280.08:12:33.29#ibcon#read 4, iclass 30, count 0 2006.280.08:12:33.29#ibcon#about to read 5, iclass 30, count 0 2006.280.08:12:33.29#ibcon#read 5, iclass 30, count 0 2006.280.08:12:33.29#ibcon#about to read 6, iclass 30, count 0 2006.280.08:12:33.29#ibcon#read 6, iclass 30, count 0 2006.280.08:12:33.29#ibcon#end of sib2, iclass 30, count 0 2006.280.08:12:33.29#ibcon#*after write, iclass 30, count 0 2006.280.08:12:33.29#ibcon#*before return 0, iclass 30, count 0 2006.280.08:12:33.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:12:33.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:12:33.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:12:33.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:12:33.29$vc4f8/vblo=1,632.99 2006.280.08:12:33.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.08:12:33.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.08:12:33.29#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:33.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:33.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:33.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:33.29#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:12:33.29#ibcon#first serial, iclass 32, count 0 2006.280.08:12:33.29#ibcon#enter sib2, iclass 32, count 0 2006.280.08:12:33.29#ibcon#flushed, iclass 32, count 0 2006.280.08:12:33.29#ibcon#about to write, iclass 32, count 0 2006.280.08:12:33.29#ibcon#wrote, iclass 32, count 0 2006.280.08:12:33.29#ibcon#about to read 3, iclass 32, count 0 2006.280.08:12:33.31#ibcon#read 3, iclass 32, count 0 2006.280.08:12:33.31#ibcon#about to read 4, iclass 32, count 0 2006.280.08:12:33.31#ibcon#read 4, iclass 32, count 0 2006.280.08:12:33.31#ibcon#about to read 5, iclass 32, count 0 2006.280.08:12:33.31#ibcon#read 5, iclass 32, count 0 2006.280.08:12:33.31#ibcon#about to read 6, iclass 32, count 0 2006.280.08:12:33.31#ibcon#read 6, iclass 32, count 0 2006.280.08:12:33.31#ibcon#end of sib2, iclass 32, count 0 2006.280.08:12:33.31#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:12:33.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:12:33.31#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:12:33.31#ibcon#*before write, iclass 32, count 0 2006.280.08:12:33.31#ibcon#enter sib2, iclass 32, count 0 2006.280.08:12:33.31#ibcon#flushed, iclass 32, count 0 2006.280.08:12:33.31#ibcon#about to write, iclass 32, count 0 2006.280.08:12:33.31#ibcon#wrote, iclass 32, count 0 2006.280.08:12:33.31#ibcon#about to read 3, iclass 32, count 0 2006.280.08:12:33.35#ibcon#read 3, iclass 32, count 0 2006.280.08:12:33.35#ibcon#about to read 4, iclass 32, count 0 2006.280.08:12:33.35#ibcon#read 4, iclass 32, count 0 2006.280.08:12:33.35#ibcon#about to read 5, iclass 32, count 0 2006.280.08:12:33.35#ibcon#read 5, iclass 32, count 0 2006.280.08:12:33.35#ibcon#about to read 6, iclass 32, count 0 2006.280.08:12:33.35#ibcon#read 6, iclass 32, count 0 2006.280.08:12:33.35#ibcon#end of sib2, iclass 32, count 0 2006.280.08:12:33.35#ibcon#*after write, iclass 32, count 0 2006.280.08:12:33.35#ibcon#*before return 0, iclass 32, count 0 2006.280.08:12:33.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:33.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:12:33.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:12:33.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:12:33.35$vc4f8/vb=1,4 2006.280.08:12:33.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.08:12:33.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.08:12:33.35#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:33.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:33.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:33.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:33.35#ibcon#enter wrdev, iclass 34, count 2 2006.280.08:12:33.35#ibcon#first serial, iclass 34, count 2 2006.280.08:12:33.35#ibcon#enter sib2, iclass 34, count 2 2006.280.08:12:33.35#ibcon#flushed, iclass 34, count 2 2006.280.08:12:33.35#ibcon#about to write, iclass 34, count 2 2006.280.08:12:33.35#ibcon#wrote, iclass 34, count 2 2006.280.08:12:33.35#ibcon#about to read 3, iclass 34, count 2 2006.280.08:12:33.37#ibcon#read 3, iclass 34, count 2 2006.280.08:12:33.37#ibcon#about to read 4, iclass 34, count 2 2006.280.08:12:33.37#ibcon#read 4, iclass 34, count 2 2006.280.08:12:33.37#ibcon#about to read 5, iclass 34, count 2 2006.280.08:12:33.37#ibcon#read 5, iclass 34, count 2 2006.280.08:12:33.37#ibcon#about to read 6, iclass 34, count 2 2006.280.08:12:33.37#ibcon#read 6, iclass 34, count 2 2006.280.08:12:33.37#ibcon#end of sib2, iclass 34, count 2 2006.280.08:12:33.37#ibcon#*mode == 0, iclass 34, count 2 2006.280.08:12:33.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.08:12:33.37#ibcon#[27=AT01-04\r\n] 2006.280.08:12:33.37#ibcon#*before write, iclass 34, count 2 2006.280.08:12:33.37#ibcon#enter sib2, iclass 34, count 2 2006.280.08:12:33.37#ibcon#flushed, iclass 34, count 2 2006.280.08:12:33.37#ibcon#about to write, iclass 34, count 2 2006.280.08:12:33.37#ibcon#wrote, iclass 34, count 2 2006.280.08:12:33.37#ibcon#about to read 3, iclass 34, count 2 2006.280.08:12:33.40#ibcon#read 3, iclass 34, count 2 2006.280.08:12:33.40#ibcon#about to read 4, iclass 34, count 2 2006.280.08:12:33.40#ibcon#read 4, iclass 34, count 2 2006.280.08:12:33.40#ibcon#about to read 5, iclass 34, count 2 2006.280.08:12:33.40#ibcon#read 5, iclass 34, count 2 2006.280.08:12:33.40#ibcon#about to read 6, iclass 34, count 2 2006.280.08:12:33.40#ibcon#read 6, iclass 34, count 2 2006.280.08:12:33.40#ibcon#end of sib2, iclass 34, count 2 2006.280.08:12:33.40#ibcon#*after write, iclass 34, count 2 2006.280.08:12:33.40#ibcon#*before return 0, iclass 34, count 2 2006.280.08:12:33.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:33.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:12:33.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.08:12:33.40#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:33.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:33.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:33.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:33.52#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:12:33.52#ibcon#first serial, iclass 34, count 0 2006.280.08:12:33.52#ibcon#enter sib2, iclass 34, count 0 2006.280.08:12:33.52#ibcon#flushed, iclass 34, count 0 2006.280.08:12:33.52#ibcon#about to write, iclass 34, count 0 2006.280.08:12:33.52#ibcon#wrote, iclass 34, count 0 2006.280.08:12:33.52#ibcon#about to read 3, iclass 34, count 0 2006.280.08:12:33.54#ibcon#read 3, iclass 34, count 0 2006.280.08:12:33.54#ibcon#about to read 4, iclass 34, count 0 2006.280.08:12:33.54#ibcon#read 4, iclass 34, count 0 2006.280.08:12:33.54#ibcon#about to read 5, iclass 34, count 0 2006.280.08:12:33.54#ibcon#read 5, iclass 34, count 0 2006.280.08:12:33.54#ibcon#about to read 6, iclass 34, count 0 2006.280.08:12:33.54#ibcon#read 6, iclass 34, count 0 2006.280.08:12:33.54#ibcon#end of sib2, iclass 34, count 0 2006.280.08:12:33.54#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:12:33.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:12:33.54#ibcon#[27=USB\r\n] 2006.280.08:12:33.54#ibcon#*before write, iclass 34, count 0 2006.280.08:12:33.54#ibcon#enter sib2, iclass 34, count 0 2006.280.08:12:33.54#ibcon#flushed, iclass 34, count 0 2006.280.08:12:33.54#ibcon#about to write, iclass 34, count 0 2006.280.08:12:33.54#ibcon#wrote, iclass 34, count 0 2006.280.08:12:33.54#ibcon#about to read 3, iclass 34, count 0 2006.280.08:12:33.57#ibcon#read 3, iclass 34, count 0 2006.280.08:12:33.57#ibcon#about to read 4, iclass 34, count 0 2006.280.08:12:33.57#ibcon#read 4, iclass 34, count 0 2006.280.08:12:33.57#ibcon#about to read 5, iclass 34, count 0 2006.280.08:12:33.57#ibcon#read 5, iclass 34, count 0 2006.280.08:12:33.57#ibcon#about to read 6, iclass 34, count 0 2006.280.08:12:33.57#ibcon#read 6, iclass 34, count 0 2006.280.08:12:33.57#ibcon#end of sib2, iclass 34, count 0 2006.280.08:12:33.57#ibcon#*after write, iclass 34, count 0 2006.280.08:12:33.57#ibcon#*before return 0, iclass 34, count 0 2006.280.08:12:33.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:33.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:12:33.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:12:33.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:12:33.57$vc4f8/vblo=2,640.99 2006.280.08:12:33.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.08:12:33.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.08:12:33.57#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:33.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:33.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:33.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:33.57#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:12:33.57#ibcon#first serial, iclass 36, count 0 2006.280.08:12:33.57#ibcon#enter sib2, iclass 36, count 0 2006.280.08:12:33.57#ibcon#flushed, iclass 36, count 0 2006.280.08:12:33.57#ibcon#about to write, iclass 36, count 0 2006.280.08:12:33.57#ibcon#wrote, iclass 36, count 0 2006.280.08:12:33.57#ibcon#about to read 3, iclass 36, count 0 2006.280.08:12:33.59#ibcon#read 3, iclass 36, count 0 2006.280.08:12:33.60#ibcon#about to read 4, iclass 36, count 0 2006.280.08:12:33.60#ibcon#read 4, iclass 36, count 0 2006.280.08:12:33.60#ibcon#about to read 5, iclass 36, count 0 2006.280.08:12:33.60#ibcon#read 5, iclass 36, count 0 2006.280.08:12:33.60#ibcon#about to read 6, iclass 36, count 0 2006.280.08:12:33.60#ibcon#read 6, iclass 36, count 0 2006.280.08:12:33.60#ibcon#end of sib2, iclass 36, count 0 2006.280.08:12:33.60#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:12:33.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:12:33.60#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:12:33.60#ibcon#*before write, iclass 36, count 0 2006.280.08:12:33.60#ibcon#enter sib2, iclass 36, count 0 2006.280.08:12:33.60#ibcon#flushed, iclass 36, count 0 2006.280.08:12:33.60#ibcon#about to write, iclass 36, count 0 2006.280.08:12:33.60#ibcon#wrote, iclass 36, count 0 2006.280.08:12:33.60#ibcon#about to read 3, iclass 36, count 0 2006.280.08:12:33.65#ibcon#read 3, iclass 36, count 0 2006.280.08:12:33.65#ibcon#about to read 4, iclass 36, count 0 2006.280.08:12:33.65#ibcon#read 4, iclass 36, count 0 2006.280.08:12:33.65#ibcon#about to read 5, iclass 36, count 0 2006.280.08:12:33.65#ibcon#read 5, iclass 36, count 0 2006.280.08:12:33.65#ibcon#about to read 6, iclass 36, count 0 2006.280.08:12:33.65#ibcon#read 6, iclass 36, count 0 2006.280.08:12:33.65#ibcon#end of sib2, iclass 36, count 0 2006.280.08:12:33.65#ibcon#*after write, iclass 36, count 0 2006.280.08:12:33.65#ibcon#*before return 0, iclass 36, count 0 2006.280.08:12:33.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:33.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:12:33.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:12:33.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:12:33.65$vc4f8/vb=2,5 2006.280.08:12:33.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.08:12:33.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.08:12:33.65#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:33.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:33.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:33.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:33.69#ibcon#enter wrdev, iclass 38, count 2 2006.280.08:12:33.69#ibcon#first serial, iclass 38, count 2 2006.280.08:12:33.69#ibcon#enter sib2, iclass 38, count 2 2006.280.08:12:33.69#ibcon#flushed, iclass 38, count 2 2006.280.08:12:33.69#ibcon#about to write, iclass 38, count 2 2006.280.08:12:33.69#ibcon#wrote, iclass 38, count 2 2006.280.08:12:33.69#ibcon#about to read 3, iclass 38, count 2 2006.280.08:12:33.71#ibcon#read 3, iclass 38, count 2 2006.280.08:12:33.71#ibcon#about to read 4, iclass 38, count 2 2006.280.08:12:33.71#ibcon#read 4, iclass 38, count 2 2006.280.08:12:33.71#ibcon#about to read 5, iclass 38, count 2 2006.280.08:12:33.71#ibcon#read 5, iclass 38, count 2 2006.280.08:12:33.71#ibcon#about to read 6, iclass 38, count 2 2006.280.08:12:33.71#ibcon#read 6, iclass 38, count 2 2006.280.08:12:33.71#ibcon#end of sib2, iclass 38, count 2 2006.280.08:12:33.71#ibcon#*mode == 0, iclass 38, count 2 2006.280.08:12:33.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.08:12:33.71#ibcon#[27=AT02-05\r\n] 2006.280.08:12:33.71#ibcon#*before write, iclass 38, count 2 2006.280.08:12:33.71#ibcon#enter sib2, iclass 38, count 2 2006.280.08:12:33.71#ibcon#flushed, iclass 38, count 2 2006.280.08:12:33.71#ibcon#about to write, iclass 38, count 2 2006.280.08:12:33.71#ibcon#wrote, iclass 38, count 2 2006.280.08:12:33.71#ibcon#about to read 3, iclass 38, count 2 2006.280.08:12:33.74#ibcon#read 3, iclass 38, count 2 2006.280.08:12:33.74#ibcon#about to read 4, iclass 38, count 2 2006.280.08:12:33.74#ibcon#read 4, iclass 38, count 2 2006.280.08:12:33.74#ibcon#about to read 5, iclass 38, count 2 2006.280.08:12:33.74#ibcon#read 5, iclass 38, count 2 2006.280.08:12:33.74#ibcon#about to read 6, iclass 38, count 2 2006.280.08:12:33.74#ibcon#read 6, iclass 38, count 2 2006.280.08:12:33.74#ibcon#end of sib2, iclass 38, count 2 2006.280.08:12:33.74#ibcon#*after write, iclass 38, count 2 2006.280.08:12:33.74#ibcon#*before return 0, iclass 38, count 2 2006.280.08:12:33.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:33.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:12:33.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.08:12:33.74#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:33.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:33.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:33.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:33.86#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:12:33.86#ibcon#first serial, iclass 38, count 0 2006.280.08:12:33.86#ibcon#enter sib2, iclass 38, count 0 2006.280.08:12:33.86#ibcon#flushed, iclass 38, count 0 2006.280.08:12:33.86#ibcon#about to write, iclass 38, count 0 2006.280.08:12:33.86#ibcon#wrote, iclass 38, count 0 2006.280.08:12:33.86#ibcon#about to read 3, iclass 38, count 0 2006.280.08:12:33.88#ibcon#read 3, iclass 38, count 0 2006.280.08:12:33.88#ibcon#about to read 4, iclass 38, count 0 2006.280.08:12:33.88#ibcon#read 4, iclass 38, count 0 2006.280.08:12:33.88#ibcon#about to read 5, iclass 38, count 0 2006.280.08:12:33.88#ibcon#read 5, iclass 38, count 0 2006.280.08:12:33.88#ibcon#about to read 6, iclass 38, count 0 2006.280.08:12:33.88#ibcon#read 6, iclass 38, count 0 2006.280.08:12:33.88#ibcon#end of sib2, iclass 38, count 0 2006.280.08:12:33.88#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:12:33.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:12:33.88#ibcon#[27=USB\r\n] 2006.280.08:12:33.88#ibcon#*before write, iclass 38, count 0 2006.280.08:12:33.88#ibcon#enter sib2, iclass 38, count 0 2006.280.08:12:33.88#ibcon#flushed, iclass 38, count 0 2006.280.08:12:33.88#ibcon#about to write, iclass 38, count 0 2006.280.08:12:33.88#ibcon#wrote, iclass 38, count 0 2006.280.08:12:33.88#ibcon#about to read 3, iclass 38, count 0 2006.280.08:12:33.91#ibcon#read 3, iclass 38, count 0 2006.280.08:12:33.91#ibcon#about to read 4, iclass 38, count 0 2006.280.08:12:33.91#ibcon#read 4, iclass 38, count 0 2006.280.08:12:33.91#ibcon#about to read 5, iclass 38, count 0 2006.280.08:12:33.91#ibcon#read 5, iclass 38, count 0 2006.280.08:12:33.91#ibcon#about to read 6, iclass 38, count 0 2006.280.08:12:33.91#ibcon#read 6, iclass 38, count 0 2006.280.08:12:33.91#ibcon#end of sib2, iclass 38, count 0 2006.280.08:12:33.91#ibcon#*after write, iclass 38, count 0 2006.280.08:12:33.91#ibcon#*before return 0, iclass 38, count 0 2006.280.08:12:33.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:33.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:12:33.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:12:33.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:12:33.91$vc4f8/vblo=3,656.99 2006.280.08:12:33.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.08:12:33.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.08:12:33.91#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:33.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:33.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:33.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:33.91#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:12:33.91#ibcon#first serial, iclass 40, count 0 2006.280.08:12:33.91#ibcon#enter sib2, iclass 40, count 0 2006.280.08:12:33.91#ibcon#flushed, iclass 40, count 0 2006.280.08:12:33.91#ibcon#about to write, iclass 40, count 0 2006.280.08:12:33.91#ibcon#wrote, iclass 40, count 0 2006.280.08:12:33.91#ibcon#about to read 3, iclass 40, count 0 2006.280.08:12:33.93#ibcon#read 3, iclass 40, count 0 2006.280.08:12:33.93#ibcon#about to read 4, iclass 40, count 0 2006.280.08:12:33.93#ibcon#read 4, iclass 40, count 0 2006.280.08:12:33.93#ibcon#about to read 5, iclass 40, count 0 2006.280.08:12:33.93#ibcon#read 5, iclass 40, count 0 2006.280.08:12:33.93#ibcon#about to read 6, iclass 40, count 0 2006.280.08:12:33.93#ibcon#read 6, iclass 40, count 0 2006.280.08:12:33.93#ibcon#end of sib2, iclass 40, count 0 2006.280.08:12:33.93#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:12:33.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:12:33.93#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:12:33.93#ibcon#*before write, iclass 40, count 0 2006.280.08:12:33.93#ibcon#enter sib2, iclass 40, count 0 2006.280.08:12:33.93#ibcon#flushed, iclass 40, count 0 2006.280.08:12:33.93#ibcon#about to write, iclass 40, count 0 2006.280.08:12:33.93#ibcon#wrote, iclass 40, count 0 2006.280.08:12:33.93#ibcon#about to read 3, iclass 40, count 0 2006.280.08:12:33.97#ibcon#read 3, iclass 40, count 0 2006.280.08:12:33.97#ibcon#about to read 4, iclass 40, count 0 2006.280.08:12:33.97#ibcon#read 4, iclass 40, count 0 2006.280.08:12:33.97#ibcon#about to read 5, iclass 40, count 0 2006.280.08:12:33.97#ibcon#read 5, iclass 40, count 0 2006.280.08:12:33.97#ibcon#about to read 6, iclass 40, count 0 2006.280.08:12:33.97#ibcon#read 6, iclass 40, count 0 2006.280.08:12:33.97#ibcon#end of sib2, iclass 40, count 0 2006.280.08:12:33.97#ibcon#*after write, iclass 40, count 0 2006.280.08:12:33.97#ibcon#*before return 0, iclass 40, count 0 2006.280.08:12:33.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:33.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:12:33.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:12:33.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:12:33.97$vc4f8/vb=3,4 2006.280.08:12:33.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.08:12:33.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.08:12:33.97#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:33.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:12:34.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:12:34.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:12:34.03#ibcon#enter wrdev, iclass 4, count 2 2006.280.08:12:34.03#ibcon#first serial, iclass 4, count 2 2006.280.08:12:34.03#ibcon#enter sib2, iclass 4, count 2 2006.280.08:12:34.03#ibcon#flushed, iclass 4, count 2 2006.280.08:12:34.03#ibcon#about to write, iclass 4, count 2 2006.280.08:12:34.03#ibcon#wrote, iclass 4, count 2 2006.280.08:12:34.03#ibcon#about to read 3, iclass 4, count 2 2006.280.08:12:34.05#ibcon#read 3, iclass 4, count 2 2006.280.08:12:34.05#ibcon#about to read 4, iclass 4, count 2 2006.280.08:12:34.05#ibcon#read 4, iclass 4, count 2 2006.280.08:12:34.05#ibcon#about to read 5, iclass 4, count 2 2006.280.08:12:34.05#ibcon#read 5, iclass 4, count 2 2006.280.08:12:34.05#ibcon#about to read 6, iclass 4, count 2 2006.280.08:12:34.05#ibcon#read 6, iclass 4, count 2 2006.280.08:12:34.05#ibcon#end of sib2, iclass 4, count 2 2006.280.08:12:34.05#ibcon#*mode == 0, iclass 4, count 2 2006.280.08:12:34.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.08:12:34.05#ibcon#[27=AT03-04\r\n] 2006.280.08:12:34.05#ibcon#*before write, iclass 4, count 2 2006.280.08:12:34.05#ibcon#enter sib2, iclass 4, count 2 2006.280.08:12:34.05#ibcon#flushed, iclass 4, count 2 2006.280.08:12:34.05#ibcon#about to write, iclass 4, count 2 2006.280.08:12:34.05#ibcon#wrote, iclass 4, count 2 2006.280.08:12:34.05#ibcon#about to read 3, iclass 4, count 2 2006.280.08:12:34.08#ibcon#read 3, iclass 4, count 2 2006.280.08:12:34.08#ibcon#about to read 4, iclass 4, count 2 2006.280.08:12:34.08#ibcon#read 4, iclass 4, count 2 2006.280.08:12:34.08#ibcon#about to read 5, iclass 4, count 2 2006.280.08:12:34.08#ibcon#read 5, iclass 4, count 2 2006.280.08:12:34.08#ibcon#about to read 6, iclass 4, count 2 2006.280.08:12:34.08#ibcon#read 6, iclass 4, count 2 2006.280.08:12:34.08#ibcon#end of sib2, iclass 4, count 2 2006.280.08:12:34.08#ibcon#*after write, iclass 4, count 2 2006.280.08:12:34.08#ibcon#*before return 0, iclass 4, count 2 2006.280.08:12:34.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:12:34.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:12:34.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.08:12:34.08#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:34.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:12:34.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:12:34.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:12:34.20#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:12:34.20#ibcon#first serial, iclass 4, count 0 2006.280.08:12:34.20#ibcon#enter sib2, iclass 4, count 0 2006.280.08:12:34.20#ibcon#flushed, iclass 4, count 0 2006.280.08:12:34.20#ibcon#about to write, iclass 4, count 0 2006.280.08:12:34.20#ibcon#wrote, iclass 4, count 0 2006.280.08:12:34.20#ibcon#about to read 3, iclass 4, count 0 2006.280.08:12:34.22#ibcon#read 3, iclass 4, count 0 2006.280.08:12:34.22#ibcon#about to read 4, iclass 4, count 0 2006.280.08:12:34.22#ibcon#read 4, iclass 4, count 0 2006.280.08:12:34.22#ibcon#about to read 5, iclass 4, count 0 2006.280.08:12:34.22#ibcon#read 5, iclass 4, count 0 2006.280.08:12:34.22#ibcon#about to read 6, iclass 4, count 0 2006.280.08:12:34.22#ibcon#read 6, iclass 4, count 0 2006.280.08:12:34.22#ibcon#end of sib2, iclass 4, count 0 2006.280.08:12:34.22#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:12:34.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:12:34.22#ibcon#[27=USB\r\n] 2006.280.08:12:34.22#ibcon#*before write, iclass 4, count 0 2006.280.08:12:34.22#ibcon#enter sib2, iclass 4, count 0 2006.280.08:12:34.22#ibcon#flushed, iclass 4, count 0 2006.280.08:12:34.22#ibcon#about to write, iclass 4, count 0 2006.280.08:12:34.22#ibcon#wrote, iclass 4, count 0 2006.280.08:12:34.22#ibcon#about to read 3, iclass 4, count 0 2006.280.08:12:34.25#ibcon#read 3, iclass 4, count 0 2006.280.08:12:34.25#ibcon#about to read 4, iclass 4, count 0 2006.280.08:12:34.25#ibcon#read 4, iclass 4, count 0 2006.280.08:12:34.25#ibcon#about to read 5, iclass 4, count 0 2006.280.08:12:34.25#ibcon#read 5, iclass 4, count 0 2006.280.08:12:34.25#ibcon#about to read 6, iclass 4, count 0 2006.280.08:12:34.25#ibcon#read 6, iclass 4, count 0 2006.280.08:12:34.25#ibcon#end of sib2, iclass 4, count 0 2006.280.08:12:34.25#ibcon#*after write, iclass 4, count 0 2006.280.08:12:34.25#ibcon#*before return 0, iclass 4, count 0 2006.280.08:12:34.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:12:34.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:12:34.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:12:34.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:12:34.25$vc4f8/vblo=4,712.99 2006.280.08:12:34.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:12:34.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:12:34.25#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:34.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:12:34.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:12:34.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:12:34.25#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:12:34.25#ibcon#first serial, iclass 6, count 0 2006.280.08:12:34.25#ibcon#enter sib2, iclass 6, count 0 2006.280.08:12:34.25#ibcon#flushed, iclass 6, count 0 2006.280.08:12:34.25#ibcon#about to write, iclass 6, count 0 2006.280.08:12:34.25#ibcon#wrote, iclass 6, count 0 2006.280.08:12:34.25#ibcon#about to read 3, iclass 6, count 0 2006.280.08:12:34.27#ibcon#read 3, iclass 6, count 0 2006.280.08:12:34.27#ibcon#about to read 4, iclass 6, count 0 2006.280.08:12:34.27#ibcon#read 4, iclass 6, count 0 2006.280.08:12:34.27#ibcon#about to read 5, iclass 6, count 0 2006.280.08:12:34.27#ibcon#read 5, iclass 6, count 0 2006.280.08:12:34.27#ibcon#about to read 6, iclass 6, count 0 2006.280.08:12:34.27#ibcon#read 6, iclass 6, count 0 2006.280.08:12:34.27#ibcon#end of sib2, iclass 6, count 0 2006.280.08:12:34.27#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:12:34.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:12:34.27#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:12:34.27#ibcon#*before write, iclass 6, count 0 2006.280.08:12:34.27#ibcon#enter sib2, iclass 6, count 0 2006.280.08:12:34.27#ibcon#flushed, iclass 6, count 0 2006.280.08:12:34.27#ibcon#about to write, iclass 6, count 0 2006.280.08:12:34.27#ibcon#wrote, iclass 6, count 0 2006.280.08:12:34.27#ibcon#about to read 3, iclass 6, count 0 2006.280.08:12:34.31#ibcon#read 3, iclass 6, count 0 2006.280.08:12:34.31#ibcon#about to read 4, iclass 6, count 0 2006.280.08:12:34.31#ibcon#read 4, iclass 6, count 0 2006.280.08:12:34.31#ibcon#about to read 5, iclass 6, count 0 2006.280.08:12:34.31#ibcon#read 5, iclass 6, count 0 2006.280.08:12:34.31#ibcon#about to read 6, iclass 6, count 0 2006.280.08:12:34.31#ibcon#read 6, iclass 6, count 0 2006.280.08:12:34.31#ibcon#end of sib2, iclass 6, count 0 2006.280.08:12:34.31#ibcon#*after write, iclass 6, count 0 2006.280.08:12:34.31#ibcon#*before return 0, iclass 6, count 0 2006.280.08:12:34.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:12:34.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:12:34.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:12:34.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:12:34.31$vc4f8/vb=4,4 2006.280.08:12:34.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.08:12:34.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.08:12:34.31#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:34.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:12:34.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:12:34.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:12:34.37#ibcon#enter wrdev, iclass 10, count 2 2006.280.08:12:34.37#ibcon#first serial, iclass 10, count 2 2006.280.08:12:34.37#ibcon#enter sib2, iclass 10, count 2 2006.280.08:12:34.37#ibcon#flushed, iclass 10, count 2 2006.280.08:12:34.37#ibcon#about to write, iclass 10, count 2 2006.280.08:12:34.37#ibcon#wrote, iclass 10, count 2 2006.280.08:12:34.37#ibcon#about to read 3, iclass 10, count 2 2006.280.08:12:34.39#ibcon#read 3, iclass 10, count 2 2006.280.08:12:34.39#ibcon#about to read 4, iclass 10, count 2 2006.280.08:12:34.39#ibcon#read 4, iclass 10, count 2 2006.280.08:12:34.39#ibcon#about to read 5, iclass 10, count 2 2006.280.08:12:34.39#ibcon#read 5, iclass 10, count 2 2006.280.08:12:34.39#ibcon#about to read 6, iclass 10, count 2 2006.280.08:12:34.39#ibcon#read 6, iclass 10, count 2 2006.280.08:12:34.39#ibcon#end of sib2, iclass 10, count 2 2006.280.08:12:34.39#ibcon#*mode == 0, iclass 10, count 2 2006.280.08:12:34.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.08:12:34.39#ibcon#[27=AT04-04\r\n] 2006.280.08:12:34.39#ibcon#*before write, iclass 10, count 2 2006.280.08:12:34.39#ibcon#enter sib2, iclass 10, count 2 2006.280.08:12:34.39#ibcon#flushed, iclass 10, count 2 2006.280.08:12:34.39#ibcon#about to write, iclass 10, count 2 2006.280.08:12:34.39#ibcon#wrote, iclass 10, count 2 2006.280.08:12:34.39#ibcon#about to read 3, iclass 10, count 2 2006.280.08:12:34.42#ibcon#read 3, iclass 10, count 2 2006.280.08:12:34.42#ibcon#about to read 4, iclass 10, count 2 2006.280.08:12:34.42#ibcon#read 4, iclass 10, count 2 2006.280.08:12:34.42#ibcon#about to read 5, iclass 10, count 2 2006.280.08:12:34.42#ibcon#read 5, iclass 10, count 2 2006.280.08:12:34.42#ibcon#about to read 6, iclass 10, count 2 2006.280.08:12:34.42#ibcon#read 6, iclass 10, count 2 2006.280.08:12:34.42#ibcon#end of sib2, iclass 10, count 2 2006.280.08:12:34.42#ibcon#*after write, iclass 10, count 2 2006.280.08:12:34.42#ibcon#*before return 0, iclass 10, count 2 2006.280.08:12:34.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:12:34.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:12:34.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.08:12:34.42#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:34.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:12:34.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:12:34.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:12:34.54#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:12:34.54#ibcon#first serial, iclass 10, count 0 2006.280.08:12:34.54#ibcon#enter sib2, iclass 10, count 0 2006.280.08:12:34.54#ibcon#flushed, iclass 10, count 0 2006.280.08:12:34.54#ibcon#about to write, iclass 10, count 0 2006.280.08:12:34.54#ibcon#wrote, iclass 10, count 0 2006.280.08:12:34.54#ibcon#about to read 3, iclass 10, count 0 2006.280.08:12:34.56#ibcon#read 3, iclass 10, count 0 2006.280.08:12:34.56#ibcon#about to read 4, iclass 10, count 0 2006.280.08:12:34.56#ibcon#read 4, iclass 10, count 0 2006.280.08:12:34.56#ibcon#about to read 5, iclass 10, count 0 2006.280.08:12:34.56#ibcon#read 5, iclass 10, count 0 2006.280.08:12:34.56#ibcon#about to read 6, iclass 10, count 0 2006.280.08:12:34.56#ibcon#read 6, iclass 10, count 0 2006.280.08:12:34.56#ibcon#end of sib2, iclass 10, count 0 2006.280.08:12:34.56#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:12:34.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:12:34.56#ibcon#[27=USB\r\n] 2006.280.08:12:34.56#ibcon#*before write, iclass 10, count 0 2006.280.08:12:34.56#ibcon#enter sib2, iclass 10, count 0 2006.280.08:12:34.56#ibcon#flushed, iclass 10, count 0 2006.280.08:12:34.56#ibcon#about to write, iclass 10, count 0 2006.280.08:12:34.56#ibcon#wrote, iclass 10, count 0 2006.280.08:12:34.56#ibcon#about to read 3, iclass 10, count 0 2006.280.08:12:34.59#ibcon#read 3, iclass 10, count 0 2006.280.08:12:34.59#ibcon#about to read 4, iclass 10, count 0 2006.280.08:12:34.59#ibcon#read 4, iclass 10, count 0 2006.280.08:12:34.59#ibcon#about to read 5, iclass 10, count 0 2006.280.08:12:34.59#ibcon#read 5, iclass 10, count 0 2006.280.08:12:34.59#ibcon#about to read 6, iclass 10, count 0 2006.280.08:12:34.59#ibcon#read 6, iclass 10, count 0 2006.280.08:12:34.59#ibcon#end of sib2, iclass 10, count 0 2006.280.08:12:34.59#ibcon#*after write, iclass 10, count 0 2006.280.08:12:34.59#ibcon#*before return 0, iclass 10, count 0 2006.280.08:12:34.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:12:34.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:12:34.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:12:34.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:12:34.59$vc4f8/vblo=5,744.99 2006.280.08:12:34.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:12:34.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:12:34.59#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:34.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:34.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:34.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:34.59#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:12:34.59#ibcon#first serial, iclass 12, count 0 2006.280.08:12:34.59#ibcon#enter sib2, iclass 12, count 0 2006.280.08:12:34.59#ibcon#flushed, iclass 12, count 0 2006.280.08:12:34.59#ibcon#about to write, iclass 12, count 0 2006.280.08:12:34.59#ibcon#wrote, iclass 12, count 0 2006.280.08:12:34.59#ibcon#about to read 3, iclass 12, count 0 2006.280.08:12:34.61#ibcon#read 3, iclass 12, count 0 2006.280.08:12:34.61#ibcon#about to read 4, iclass 12, count 0 2006.280.08:12:34.61#ibcon#read 4, iclass 12, count 0 2006.280.08:12:34.61#ibcon#about to read 5, iclass 12, count 0 2006.280.08:12:34.61#ibcon#read 5, iclass 12, count 0 2006.280.08:12:34.61#ibcon#about to read 6, iclass 12, count 0 2006.280.08:12:34.61#ibcon#read 6, iclass 12, count 0 2006.280.08:12:34.61#ibcon#end of sib2, iclass 12, count 0 2006.280.08:12:34.61#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:12:34.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:12:34.61#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:12:34.61#ibcon#*before write, iclass 12, count 0 2006.280.08:12:34.61#ibcon#enter sib2, iclass 12, count 0 2006.280.08:12:34.61#ibcon#flushed, iclass 12, count 0 2006.280.08:12:34.61#ibcon#about to write, iclass 12, count 0 2006.280.08:12:34.61#ibcon#wrote, iclass 12, count 0 2006.280.08:12:34.61#ibcon#about to read 3, iclass 12, count 0 2006.280.08:12:34.65#ibcon#read 3, iclass 12, count 0 2006.280.08:12:34.65#ibcon#about to read 4, iclass 12, count 0 2006.280.08:12:34.65#ibcon#read 4, iclass 12, count 0 2006.280.08:12:34.65#ibcon#about to read 5, iclass 12, count 0 2006.280.08:12:34.65#ibcon#read 5, iclass 12, count 0 2006.280.08:12:34.65#ibcon#about to read 6, iclass 12, count 0 2006.280.08:12:34.65#ibcon#read 6, iclass 12, count 0 2006.280.08:12:34.65#ibcon#end of sib2, iclass 12, count 0 2006.280.08:12:34.65#ibcon#*after write, iclass 12, count 0 2006.280.08:12:34.65#ibcon#*before return 0, iclass 12, count 0 2006.280.08:12:34.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:34.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:12:34.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:12:34.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:12:34.65$vc4f8/vb=5,4 2006.280.08:12:34.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:12:34.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:12:34.66#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:34.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:34.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:34.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:34.71#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:12:34.71#ibcon#first serial, iclass 14, count 2 2006.280.08:12:34.71#ibcon#enter sib2, iclass 14, count 2 2006.280.08:12:34.71#ibcon#flushed, iclass 14, count 2 2006.280.08:12:34.71#ibcon#about to write, iclass 14, count 2 2006.280.08:12:34.71#ibcon#wrote, iclass 14, count 2 2006.280.08:12:34.71#ibcon#about to read 3, iclass 14, count 2 2006.280.08:12:34.73#ibcon#read 3, iclass 14, count 2 2006.280.08:12:34.73#ibcon#about to read 4, iclass 14, count 2 2006.280.08:12:34.73#ibcon#read 4, iclass 14, count 2 2006.280.08:12:34.73#ibcon#about to read 5, iclass 14, count 2 2006.280.08:12:34.73#ibcon#read 5, iclass 14, count 2 2006.280.08:12:34.73#ibcon#about to read 6, iclass 14, count 2 2006.280.08:12:34.73#ibcon#read 6, iclass 14, count 2 2006.280.08:12:34.73#ibcon#end of sib2, iclass 14, count 2 2006.280.08:12:34.73#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:12:34.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:12:34.73#ibcon#[27=AT05-04\r\n] 2006.280.08:12:34.73#ibcon#*before write, iclass 14, count 2 2006.280.08:12:34.73#ibcon#enter sib2, iclass 14, count 2 2006.280.08:12:34.73#ibcon#flushed, iclass 14, count 2 2006.280.08:12:34.73#ibcon#about to write, iclass 14, count 2 2006.280.08:12:34.73#ibcon#wrote, iclass 14, count 2 2006.280.08:12:34.73#ibcon#about to read 3, iclass 14, count 2 2006.280.08:12:34.76#ibcon#read 3, iclass 14, count 2 2006.280.08:12:34.76#ibcon#about to read 4, iclass 14, count 2 2006.280.08:12:34.76#ibcon#read 4, iclass 14, count 2 2006.280.08:12:34.76#ibcon#about to read 5, iclass 14, count 2 2006.280.08:12:34.76#ibcon#read 5, iclass 14, count 2 2006.280.08:12:34.76#ibcon#about to read 6, iclass 14, count 2 2006.280.08:12:34.76#ibcon#read 6, iclass 14, count 2 2006.280.08:12:34.76#ibcon#end of sib2, iclass 14, count 2 2006.280.08:12:34.76#ibcon#*after write, iclass 14, count 2 2006.280.08:12:34.76#ibcon#*before return 0, iclass 14, count 2 2006.280.08:12:34.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:34.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:12:34.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:12:34.76#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:34.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:34.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:34.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:34.88#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:12:34.88#ibcon#first serial, iclass 14, count 0 2006.280.08:12:34.88#ibcon#enter sib2, iclass 14, count 0 2006.280.08:12:34.88#ibcon#flushed, iclass 14, count 0 2006.280.08:12:34.88#ibcon#about to write, iclass 14, count 0 2006.280.08:12:34.88#ibcon#wrote, iclass 14, count 0 2006.280.08:12:34.88#ibcon#about to read 3, iclass 14, count 0 2006.280.08:12:34.90#ibcon#read 3, iclass 14, count 0 2006.280.08:12:34.90#ibcon#about to read 4, iclass 14, count 0 2006.280.08:12:34.90#ibcon#read 4, iclass 14, count 0 2006.280.08:12:34.90#ibcon#about to read 5, iclass 14, count 0 2006.280.08:12:34.90#ibcon#read 5, iclass 14, count 0 2006.280.08:12:34.90#ibcon#about to read 6, iclass 14, count 0 2006.280.08:12:34.90#ibcon#read 6, iclass 14, count 0 2006.280.08:12:34.90#ibcon#end of sib2, iclass 14, count 0 2006.280.08:12:34.90#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:12:34.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:12:34.90#ibcon#[27=USB\r\n] 2006.280.08:12:34.90#ibcon#*before write, iclass 14, count 0 2006.280.08:12:34.90#ibcon#enter sib2, iclass 14, count 0 2006.280.08:12:34.90#ibcon#flushed, iclass 14, count 0 2006.280.08:12:34.90#ibcon#about to write, iclass 14, count 0 2006.280.08:12:34.90#ibcon#wrote, iclass 14, count 0 2006.280.08:12:34.90#ibcon#about to read 3, iclass 14, count 0 2006.280.08:12:34.93#ibcon#read 3, iclass 14, count 0 2006.280.08:12:34.93#ibcon#about to read 4, iclass 14, count 0 2006.280.08:12:34.93#ibcon#read 4, iclass 14, count 0 2006.280.08:12:34.93#ibcon#about to read 5, iclass 14, count 0 2006.280.08:12:34.93#ibcon#read 5, iclass 14, count 0 2006.280.08:12:34.93#ibcon#about to read 6, iclass 14, count 0 2006.280.08:12:34.93#ibcon#read 6, iclass 14, count 0 2006.280.08:12:34.93#ibcon#end of sib2, iclass 14, count 0 2006.280.08:12:34.93#ibcon#*after write, iclass 14, count 0 2006.280.08:12:34.93#ibcon#*before return 0, iclass 14, count 0 2006.280.08:12:34.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:34.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:12:34.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:12:34.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:12:34.93$vc4f8/vblo=6,752.99 2006.280.08:12:34.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:12:34.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:12:34.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:12:34.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:34.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:34.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:34.93#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:12:34.93#ibcon#first serial, iclass 16, count 0 2006.280.08:12:34.93#ibcon#enter sib2, iclass 16, count 0 2006.280.08:12:34.93#ibcon#flushed, iclass 16, count 0 2006.280.08:12:34.93#ibcon#about to write, iclass 16, count 0 2006.280.08:12:34.93#ibcon#wrote, iclass 16, count 0 2006.280.08:12:34.93#ibcon#about to read 3, iclass 16, count 0 2006.280.08:12:34.95#ibcon#read 3, iclass 16, count 0 2006.280.08:12:34.95#ibcon#about to read 4, iclass 16, count 0 2006.280.08:12:34.95#ibcon#read 4, iclass 16, count 0 2006.280.08:12:34.95#ibcon#about to read 5, iclass 16, count 0 2006.280.08:12:34.95#ibcon#read 5, iclass 16, count 0 2006.280.08:12:34.95#ibcon#about to read 6, iclass 16, count 0 2006.280.08:12:34.95#ibcon#read 6, iclass 16, count 0 2006.280.08:12:34.95#ibcon#end of sib2, iclass 16, count 0 2006.280.08:12:34.95#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:12:34.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:12:34.95#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:12:34.95#ibcon#*before write, iclass 16, count 0 2006.280.08:12:34.95#ibcon#enter sib2, iclass 16, count 0 2006.280.08:12:34.95#ibcon#flushed, iclass 16, count 0 2006.280.08:12:34.95#ibcon#about to write, iclass 16, count 0 2006.280.08:12:34.95#ibcon#wrote, iclass 16, count 0 2006.280.08:12:34.95#ibcon#about to read 3, iclass 16, count 0 2006.280.08:12:34.99#ibcon#read 3, iclass 16, count 0 2006.280.08:12:34.99#ibcon#about to read 4, iclass 16, count 0 2006.280.08:12:34.99#ibcon#read 4, iclass 16, count 0 2006.280.08:12:34.99#ibcon#about to read 5, iclass 16, count 0 2006.280.08:12:34.99#ibcon#read 5, iclass 16, count 0 2006.280.08:12:34.99#ibcon#about to read 6, iclass 16, count 0 2006.280.08:12:34.99#ibcon#read 6, iclass 16, count 0 2006.280.08:12:34.99#ibcon#end of sib2, iclass 16, count 0 2006.280.08:12:34.99#ibcon#*after write, iclass 16, count 0 2006.280.08:12:34.99#ibcon#*before return 0, iclass 16, count 0 2006.280.08:12:34.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:34.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:12:34.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:12:34.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:12:34.99$vc4f8/vb=6,4 2006.280.08:12:34.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:12:34.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:12:34.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:12:34.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:35.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:35.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:35.05#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:12:35.05#ibcon#first serial, iclass 18, count 2 2006.280.08:12:35.05#ibcon#enter sib2, iclass 18, count 2 2006.280.08:12:35.05#ibcon#flushed, iclass 18, count 2 2006.280.08:12:35.05#ibcon#about to write, iclass 18, count 2 2006.280.08:12:35.05#ibcon#wrote, iclass 18, count 2 2006.280.08:12:35.05#ibcon#about to read 3, iclass 18, count 2 2006.280.08:12:35.07#ibcon#read 3, iclass 18, count 2 2006.280.08:12:35.07#ibcon#about to read 4, iclass 18, count 2 2006.280.08:12:35.07#ibcon#read 4, iclass 18, count 2 2006.280.08:12:35.07#ibcon#about to read 5, iclass 18, count 2 2006.280.08:12:35.07#ibcon#read 5, iclass 18, count 2 2006.280.08:12:35.07#ibcon#about to read 6, iclass 18, count 2 2006.280.08:12:35.07#ibcon#read 6, iclass 18, count 2 2006.280.08:12:35.07#ibcon#end of sib2, iclass 18, count 2 2006.280.08:12:35.07#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:12:35.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:12:35.07#ibcon#[27=AT06-04\r\n] 2006.280.08:12:35.07#ibcon#*before write, iclass 18, count 2 2006.280.08:12:35.07#ibcon#enter sib2, iclass 18, count 2 2006.280.08:12:35.07#ibcon#flushed, iclass 18, count 2 2006.280.08:12:35.07#ibcon#about to write, iclass 18, count 2 2006.280.08:12:35.07#ibcon#wrote, iclass 18, count 2 2006.280.08:12:35.07#ibcon#about to read 3, iclass 18, count 2 2006.280.08:12:35.10#ibcon#read 3, iclass 18, count 2 2006.280.08:12:35.10#ibcon#about to read 4, iclass 18, count 2 2006.280.08:12:35.10#ibcon#read 4, iclass 18, count 2 2006.280.08:12:35.10#ibcon#about to read 5, iclass 18, count 2 2006.280.08:12:35.10#ibcon#read 5, iclass 18, count 2 2006.280.08:12:35.10#ibcon#about to read 6, iclass 18, count 2 2006.280.08:12:35.10#ibcon#read 6, iclass 18, count 2 2006.280.08:12:35.10#ibcon#end of sib2, iclass 18, count 2 2006.280.08:12:35.10#ibcon#*after write, iclass 18, count 2 2006.280.08:12:35.10#ibcon#*before return 0, iclass 18, count 2 2006.280.08:12:35.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:35.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:12:35.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:12:35.10#ibcon#ireg 7 cls_cnt 0 2006.280.08:12:35.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:35.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:35.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:35.22#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:12:35.22#ibcon#first serial, iclass 18, count 0 2006.280.08:12:35.22#ibcon#enter sib2, iclass 18, count 0 2006.280.08:12:35.22#ibcon#flushed, iclass 18, count 0 2006.280.08:12:35.22#ibcon#about to write, iclass 18, count 0 2006.280.08:12:35.22#ibcon#wrote, iclass 18, count 0 2006.280.08:12:35.22#ibcon#about to read 3, iclass 18, count 0 2006.280.08:12:35.24#ibcon#read 3, iclass 18, count 0 2006.280.08:12:35.24#ibcon#about to read 4, iclass 18, count 0 2006.280.08:12:35.24#ibcon#read 4, iclass 18, count 0 2006.280.08:12:35.24#ibcon#about to read 5, iclass 18, count 0 2006.280.08:12:35.24#ibcon#read 5, iclass 18, count 0 2006.280.08:12:35.24#ibcon#about to read 6, iclass 18, count 0 2006.280.08:12:35.24#ibcon#read 6, iclass 18, count 0 2006.280.08:12:35.24#ibcon#end of sib2, iclass 18, count 0 2006.280.08:12:35.24#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:12:35.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:12:35.24#ibcon#[27=USB\r\n] 2006.280.08:12:35.24#ibcon#*before write, iclass 18, count 0 2006.280.08:12:35.24#ibcon#enter sib2, iclass 18, count 0 2006.280.08:12:35.24#ibcon#flushed, iclass 18, count 0 2006.280.08:12:35.24#ibcon#about to write, iclass 18, count 0 2006.280.08:12:35.24#ibcon#wrote, iclass 18, count 0 2006.280.08:12:35.24#ibcon#about to read 3, iclass 18, count 0 2006.280.08:12:35.27#ibcon#read 3, iclass 18, count 0 2006.280.08:12:35.27#ibcon#about to read 4, iclass 18, count 0 2006.280.08:12:35.27#ibcon#read 4, iclass 18, count 0 2006.280.08:12:35.27#ibcon#about to read 5, iclass 18, count 0 2006.280.08:12:35.27#ibcon#read 5, iclass 18, count 0 2006.280.08:12:35.27#ibcon#about to read 6, iclass 18, count 0 2006.280.08:12:35.27#ibcon#read 6, iclass 18, count 0 2006.280.08:12:35.27#ibcon#end of sib2, iclass 18, count 0 2006.280.08:12:35.27#ibcon#*after write, iclass 18, count 0 2006.280.08:12:35.27#ibcon#*before return 0, iclass 18, count 0 2006.280.08:12:35.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:35.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:12:35.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:12:35.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:12:35.27$vc4f8/vabw=wide 2006.280.08:12:35.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:12:35.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:12:35.27#ibcon#ireg 8 cls_cnt 0 2006.280.08:12:35.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:35.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:35.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:35.27#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:12:35.27#ibcon#first serial, iclass 20, count 0 2006.280.08:12:35.27#ibcon#enter sib2, iclass 20, count 0 2006.280.08:12:35.27#ibcon#flushed, iclass 20, count 0 2006.280.08:12:35.27#ibcon#about to write, iclass 20, count 0 2006.280.08:12:35.27#ibcon#wrote, iclass 20, count 0 2006.280.08:12:35.27#ibcon#about to read 3, iclass 20, count 0 2006.280.08:12:35.29#ibcon#read 3, iclass 20, count 0 2006.280.08:12:35.29#ibcon#about to read 4, iclass 20, count 0 2006.280.08:12:35.29#ibcon#read 4, iclass 20, count 0 2006.280.08:12:35.29#ibcon#about to read 5, iclass 20, count 0 2006.280.08:12:35.29#ibcon#read 5, iclass 20, count 0 2006.280.08:12:35.29#ibcon#about to read 6, iclass 20, count 0 2006.280.08:12:35.29#ibcon#read 6, iclass 20, count 0 2006.280.08:12:35.29#ibcon#end of sib2, iclass 20, count 0 2006.280.08:12:35.29#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:12:35.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:12:35.29#ibcon#[25=BW32\r\n] 2006.280.08:12:35.29#ibcon#*before write, iclass 20, count 0 2006.280.08:12:35.29#ibcon#enter sib2, iclass 20, count 0 2006.280.08:12:35.29#ibcon#flushed, iclass 20, count 0 2006.280.08:12:35.29#ibcon#about to write, iclass 20, count 0 2006.280.08:12:35.29#ibcon#wrote, iclass 20, count 0 2006.280.08:12:35.29#ibcon#about to read 3, iclass 20, count 0 2006.280.08:12:35.32#ibcon#read 3, iclass 20, count 0 2006.280.08:12:35.32#ibcon#about to read 4, iclass 20, count 0 2006.280.08:12:35.32#ibcon#read 4, iclass 20, count 0 2006.280.08:12:35.32#ibcon#about to read 5, iclass 20, count 0 2006.280.08:12:35.32#ibcon#read 5, iclass 20, count 0 2006.280.08:12:35.32#ibcon#about to read 6, iclass 20, count 0 2006.280.08:12:35.32#ibcon#read 6, iclass 20, count 0 2006.280.08:12:35.32#ibcon#end of sib2, iclass 20, count 0 2006.280.08:12:35.32#ibcon#*after write, iclass 20, count 0 2006.280.08:12:35.32#ibcon#*before return 0, iclass 20, count 0 2006.280.08:12:35.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:35.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:12:35.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:12:35.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:12:35.32$vc4f8/vbbw=wide 2006.280.08:12:35.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:12:35.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:12:35.32#ibcon#ireg 8 cls_cnt 0 2006.280.08:12:35.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:12:35.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:12:35.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:12:35.39#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:12:35.39#ibcon#first serial, iclass 22, count 0 2006.280.08:12:35.39#ibcon#enter sib2, iclass 22, count 0 2006.280.08:12:35.39#ibcon#flushed, iclass 22, count 0 2006.280.08:12:35.39#ibcon#about to write, iclass 22, count 0 2006.280.08:12:35.39#ibcon#wrote, iclass 22, count 0 2006.280.08:12:35.39#ibcon#about to read 3, iclass 22, count 0 2006.280.08:12:35.41#ibcon#read 3, iclass 22, count 0 2006.280.08:12:35.41#ibcon#about to read 4, iclass 22, count 0 2006.280.08:12:35.41#ibcon#read 4, iclass 22, count 0 2006.280.08:12:35.41#ibcon#about to read 5, iclass 22, count 0 2006.280.08:12:35.41#ibcon#read 5, iclass 22, count 0 2006.280.08:12:35.41#ibcon#about to read 6, iclass 22, count 0 2006.280.08:12:35.41#ibcon#read 6, iclass 22, count 0 2006.280.08:12:35.41#ibcon#end of sib2, iclass 22, count 0 2006.280.08:12:35.41#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:12:35.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:12:35.41#ibcon#[27=BW32\r\n] 2006.280.08:12:35.41#ibcon#*before write, iclass 22, count 0 2006.280.08:12:35.41#ibcon#enter sib2, iclass 22, count 0 2006.280.08:12:35.41#ibcon#flushed, iclass 22, count 0 2006.280.08:12:35.41#ibcon#about to write, iclass 22, count 0 2006.280.08:12:35.41#ibcon#wrote, iclass 22, count 0 2006.280.08:12:35.41#ibcon#about to read 3, iclass 22, count 0 2006.280.08:12:35.44#ibcon#read 3, iclass 22, count 0 2006.280.08:12:35.44#ibcon#about to read 4, iclass 22, count 0 2006.280.08:12:35.44#ibcon#read 4, iclass 22, count 0 2006.280.08:12:35.44#ibcon#about to read 5, iclass 22, count 0 2006.280.08:12:35.44#ibcon#read 5, iclass 22, count 0 2006.280.08:12:35.44#ibcon#about to read 6, iclass 22, count 0 2006.280.08:12:35.44#ibcon#read 6, iclass 22, count 0 2006.280.08:12:35.44#ibcon#end of sib2, iclass 22, count 0 2006.280.08:12:35.44#ibcon#*after write, iclass 22, count 0 2006.280.08:12:35.44#ibcon#*before return 0, iclass 22, count 0 2006.280.08:12:35.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:12:35.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:12:35.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:12:35.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:12:35.44$4f8m12a/ifd4f 2006.280.08:12:35.44$ifd4f/lo= 2006.280.08:12:35.44$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:12:35.44$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:12:35.44$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:12:35.44$ifd4f/patch= 2006.280.08:12:35.44$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:12:35.44$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:12:35.44$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:12:35.44$4f8m12a/"form=m,16.000,1:2 2006.280.08:12:35.44$4f8m12a/"tpicd 2006.280.08:12:35.44$4f8m12a/echo=off 2006.280.08:12:35.44$4f8m12a/xlog=off 2006.280.08:12:35.44:!2006.280.08:13:10 2006.280.08:12:53.14#trakl#Source acquired 2006.280.08:12:54.14#flagr#flagr/antenna,acquired 2006.280.08:13:10.00:preob 2006.280.08:13:10.14/onsource/TRACKING 2006.280.08:13:10.14:!2006.280.08:13:20 2006.280.08:13:20.00:data_valid=on 2006.280.08:13:20.00:midob 2006.280.08:13:21.14/onsource/TRACKING 2006.280.08:13:21.14/wx/20.42,987.6,62 2006.280.08:13:21.31/cable/+6.4850E-03 2006.280.08:13:22.40/va/01,07,usb,yes,32,34 2006.280.08:13:22.40/va/02,06,usb,yes,30,31 2006.280.08:13:22.40/va/03,06,usb,yes,28,28 2006.280.08:13:22.40/va/04,06,usb,yes,31,33 2006.280.08:13:22.40/va/05,07,usb,yes,29,31 2006.280.08:13:22.40/va/06,06,usb,yes,28,28 2006.280.08:13:22.40/va/07,06,usb,yes,28,28 2006.280.08:13:22.40/va/08,06,usb,yes,30,30 2006.280.08:13:22.63/valo/01,532.99,yes,locked 2006.280.08:13:22.63/valo/02,572.99,yes,locked 2006.280.08:13:22.63/valo/03,672.99,yes,locked 2006.280.08:13:22.63/valo/04,832.99,yes,locked 2006.280.08:13:22.63/valo/05,652.99,yes,locked 2006.280.08:13:22.63/valo/06,772.99,yes,locked 2006.280.08:13:22.63/valo/07,832.99,yes,locked 2006.280.08:13:22.63/valo/08,852.99,yes,locked 2006.280.08:13:23.72/vb/01,04,usb,yes,30,28 2006.280.08:13:23.72/vb/02,05,usb,yes,28,29 2006.280.08:13:23.72/vb/03,04,usb,yes,28,32 2006.280.08:13:23.72/vb/04,04,usb,yes,29,29 2006.280.08:13:23.72/vb/05,04,usb,yes,27,31 2006.280.08:13:23.72/vb/06,04,usb,yes,27,30 2006.280.08:13:23.72/vb/07,04,usb,yes,30,30 2006.280.08:13:23.72/vb/08,04,usb,yes,27,31 2006.280.08:13:23.95/vblo/01,632.99,yes,locked 2006.280.08:13:23.95/vblo/02,640.99,yes,locked 2006.280.08:13:23.95/vblo/03,656.99,yes,locked 2006.280.08:13:23.95/vblo/04,712.99,yes,locked 2006.280.08:13:23.95/vblo/05,744.99,yes,locked 2006.280.08:13:23.95/vblo/06,752.99,yes,locked 2006.280.08:13:23.95/vblo/07,734.99,yes,locked 2006.280.08:13:23.95/vblo/08,744.99,yes,locked 2006.280.08:13:24.10/vabw/8 2006.280.08:13:24.25/vbbw/8 2006.280.08:13:24.34/xfe/off,on,12.2 2006.280.08:13:24.72/ifatt/23,28,28,28 2006.280.08:13:25.08/fmout-gps/S +3.14E-07 2006.280.08:13:25.10:!2006.280.08:14:20 2006.280.08:14:20.02:data_valid=off 2006.280.08:14:20.02:postob 2006.280.08:14:20.15/cable/+6.4831E-03 2006.280.08:14:20.15/wx/20.42,987.6,63 2006.280.08:14:21.08/fmout-gps/S +3.12E-07 2006.280.08:14:21.08:scan_name=280-0815,k06280,60 2006.280.08:14:21.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.280.08:14:21.14#flagr#flagr/antenna,new-source 2006.280.08:14:22.14:checkk5 2006.280.08:14:23.09/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:14:23.53/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:14:24.01/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:14:24.43/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:14:24.83/chk_obsdata//k5ts1/T2800813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:14:25.29/chk_obsdata//k5ts2/T2800813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:14:25.94/chk_obsdata//k5ts3/T2800813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:14:26.48/chk_obsdata//k5ts4/T2800813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:14:27.87/k5log//k5ts1_log_newline 2006.280.08:14:28.77/k5log//k5ts2_log_newline 2006.280.08:14:29.66/k5log//k5ts3_log_newline 2006.280.08:14:30.53/k5log//k5ts4_log_newline 2006.280.08:14:30.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:14:30.55:4f8m12a=2 2006.280.08:14:30.55$4f8m12a/echo=on 2006.280.08:14:30.55$4f8m12a/pcalon 2006.280.08:14:30.55$pcalon/"no phase cal control is implemented here 2006.280.08:14:30.55$4f8m12a/"tpicd=stop 2006.280.08:14:30.55$4f8m12a/vc4f8 2006.280.08:14:30.55$vc4f8/valo=1,532.99 2006.280.08:14:30.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.08:14:30.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.08:14:30.56#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:30.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:14:30.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:14:30.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:14:30.56#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:14:30.56#ibcon#first serial, iclass 33, count 0 2006.280.08:14:30.56#ibcon#enter sib2, iclass 33, count 0 2006.280.08:14:30.56#ibcon#flushed, iclass 33, count 0 2006.280.08:14:30.56#ibcon#about to write, iclass 33, count 0 2006.280.08:14:30.56#ibcon#wrote, iclass 33, count 0 2006.280.08:14:30.56#ibcon#about to read 3, iclass 33, count 0 2006.280.08:14:30.58#ibcon#read 3, iclass 33, count 0 2006.280.08:14:30.58#ibcon#about to read 4, iclass 33, count 0 2006.280.08:14:30.58#ibcon#read 4, iclass 33, count 0 2006.280.08:14:30.58#ibcon#about to read 5, iclass 33, count 0 2006.280.08:14:30.58#ibcon#read 5, iclass 33, count 0 2006.280.08:14:30.58#ibcon#about to read 6, iclass 33, count 0 2006.280.08:14:30.58#ibcon#read 6, iclass 33, count 0 2006.280.08:14:30.58#ibcon#end of sib2, iclass 33, count 0 2006.280.08:14:30.58#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:14:30.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:14:30.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:14:30.58#ibcon#*before write, iclass 33, count 0 2006.280.08:14:30.58#ibcon#enter sib2, iclass 33, count 0 2006.280.08:14:30.58#ibcon#flushed, iclass 33, count 0 2006.280.08:14:30.58#ibcon#about to write, iclass 33, count 0 2006.280.08:14:30.58#ibcon#wrote, iclass 33, count 0 2006.280.08:14:30.58#ibcon#about to read 3, iclass 33, count 0 2006.280.08:14:30.63#ibcon#read 3, iclass 33, count 0 2006.280.08:14:30.64#ibcon#about to read 4, iclass 33, count 0 2006.280.08:14:30.64#ibcon#read 4, iclass 33, count 0 2006.280.08:14:30.64#ibcon#about to read 5, iclass 33, count 0 2006.280.08:14:30.64#ibcon#read 5, iclass 33, count 0 2006.280.08:14:30.64#ibcon#about to read 6, iclass 33, count 0 2006.280.08:14:30.64#ibcon#read 6, iclass 33, count 0 2006.280.08:14:30.64#ibcon#end of sib2, iclass 33, count 0 2006.280.08:14:30.64#ibcon#*after write, iclass 33, count 0 2006.280.08:14:30.64#ibcon#*before return 0, iclass 33, count 0 2006.280.08:14:30.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:14:30.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:14:30.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:14:30.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:14:30.64$vc4f8/va=1,7 2006.280.08:14:30.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.280.08:14:30.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.280.08:14:30.64#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:30.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:14:30.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:14:30.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:14:30.64#ibcon#enter wrdev, iclass 35, count 2 2006.280.08:14:30.64#ibcon#first serial, iclass 35, count 2 2006.280.08:14:30.64#ibcon#enter sib2, iclass 35, count 2 2006.280.08:14:30.64#ibcon#flushed, iclass 35, count 2 2006.280.08:14:30.65#ibcon#about to write, iclass 35, count 2 2006.280.08:14:30.65#ibcon#wrote, iclass 35, count 2 2006.280.08:14:30.65#ibcon#about to read 3, iclass 35, count 2 2006.280.08:14:30.66#ibcon#read 3, iclass 35, count 2 2006.280.08:14:30.66#ibcon#about to read 4, iclass 35, count 2 2006.280.08:14:30.66#ibcon#read 4, iclass 35, count 2 2006.280.08:14:30.66#ibcon#about to read 5, iclass 35, count 2 2006.280.08:14:30.66#ibcon#read 5, iclass 35, count 2 2006.280.08:14:30.66#ibcon#about to read 6, iclass 35, count 2 2006.280.08:14:30.67#ibcon#read 6, iclass 35, count 2 2006.280.08:14:30.67#ibcon#end of sib2, iclass 35, count 2 2006.280.08:14:30.67#ibcon#*mode == 0, iclass 35, count 2 2006.280.08:14:30.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.280.08:14:30.67#ibcon#[25=AT01-07\r\n] 2006.280.08:14:30.67#ibcon#*before write, iclass 35, count 2 2006.280.08:14:30.67#ibcon#enter sib2, iclass 35, count 2 2006.280.08:14:30.67#ibcon#flushed, iclass 35, count 2 2006.280.08:14:30.67#ibcon#about to write, iclass 35, count 2 2006.280.08:14:30.67#ibcon#wrote, iclass 35, count 2 2006.280.08:14:30.67#ibcon#about to read 3, iclass 35, count 2 2006.280.08:14:30.69#ibcon#read 3, iclass 35, count 2 2006.280.08:14:30.69#ibcon#about to read 4, iclass 35, count 2 2006.280.08:14:30.69#ibcon#read 4, iclass 35, count 2 2006.280.08:14:30.69#ibcon#about to read 5, iclass 35, count 2 2006.280.08:14:30.69#ibcon#read 5, iclass 35, count 2 2006.280.08:14:30.69#ibcon#about to read 6, iclass 35, count 2 2006.280.08:14:30.69#ibcon#read 6, iclass 35, count 2 2006.280.08:14:30.70#ibcon#end of sib2, iclass 35, count 2 2006.280.08:14:30.70#ibcon#*after write, iclass 35, count 2 2006.280.08:14:30.70#ibcon#*before return 0, iclass 35, count 2 2006.280.08:14:30.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:14:30.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.280.08:14:30.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.280.08:14:30.70#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:30.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:14:30.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:14:30.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:14:30.82#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:14:30.82#ibcon#first serial, iclass 35, count 0 2006.280.08:14:30.82#ibcon#enter sib2, iclass 35, count 0 2006.280.08:14:30.82#ibcon#flushed, iclass 35, count 0 2006.280.08:14:30.82#ibcon#about to write, iclass 35, count 0 2006.280.08:14:30.82#ibcon#wrote, iclass 35, count 0 2006.280.08:14:30.82#ibcon#about to read 3, iclass 35, count 0 2006.280.08:14:30.83#ibcon#read 3, iclass 35, count 0 2006.280.08:14:30.83#ibcon#about to read 4, iclass 35, count 0 2006.280.08:14:30.83#ibcon#read 4, iclass 35, count 0 2006.280.08:14:30.83#ibcon#about to read 5, iclass 35, count 0 2006.280.08:14:30.84#ibcon#read 5, iclass 35, count 0 2006.280.08:14:30.84#ibcon#about to read 6, iclass 35, count 0 2006.280.08:14:30.84#ibcon#read 6, iclass 35, count 0 2006.280.08:14:30.84#ibcon#end of sib2, iclass 35, count 0 2006.280.08:14:30.84#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:14:30.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:14:30.84#ibcon#[25=USB\r\n] 2006.280.08:14:30.84#ibcon#*before write, iclass 35, count 0 2006.280.08:14:30.84#ibcon#enter sib2, iclass 35, count 0 2006.280.08:14:30.84#ibcon#flushed, iclass 35, count 0 2006.280.08:14:30.84#ibcon#about to write, iclass 35, count 0 2006.280.08:14:30.84#ibcon#wrote, iclass 35, count 0 2006.280.08:14:30.84#ibcon#about to read 3, iclass 35, count 0 2006.280.08:14:30.86#ibcon#read 3, iclass 35, count 0 2006.280.08:14:30.87#ibcon#about to read 4, iclass 35, count 0 2006.280.08:14:30.87#ibcon#read 4, iclass 35, count 0 2006.280.08:14:30.87#ibcon#about to read 5, iclass 35, count 0 2006.280.08:14:30.87#ibcon#read 5, iclass 35, count 0 2006.280.08:14:30.87#ibcon#about to read 6, iclass 35, count 0 2006.280.08:14:30.87#ibcon#read 6, iclass 35, count 0 2006.280.08:14:30.87#ibcon#end of sib2, iclass 35, count 0 2006.280.08:14:30.87#ibcon#*after write, iclass 35, count 0 2006.280.08:14:30.87#ibcon#*before return 0, iclass 35, count 0 2006.280.08:14:30.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:14:30.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.280.08:14:30.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:14:30.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:14:30.87$vc4f8/valo=2,572.99 2006.280.08:14:30.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.08:14:30.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.08:14:30.87#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:30.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:30.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:30.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:30.87#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:14:30.87#ibcon#first serial, iclass 37, count 0 2006.280.08:14:30.87#ibcon#enter sib2, iclass 37, count 0 2006.280.08:14:30.87#ibcon#flushed, iclass 37, count 0 2006.280.08:14:30.87#ibcon#about to write, iclass 37, count 0 2006.280.08:14:30.87#ibcon#wrote, iclass 37, count 0 2006.280.08:14:30.87#ibcon#about to read 3, iclass 37, count 0 2006.280.08:14:30.88#ibcon#read 3, iclass 37, count 0 2006.280.08:14:30.88#ibcon#about to read 4, iclass 37, count 0 2006.280.08:14:30.88#ibcon#read 4, iclass 37, count 0 2006.280.08:14:30.88#ibcon#about to read 5, iclass 37, count 0 2006.280.08:14:30.88#ibcon#read 5, iclass 37, count 0 2006.280.08:14:30.88#ibcon#about to read 6, iclass 37, count 0 2006.280.08:14:30.89#ibcon#read 6, iclass 37, count 0 2006.280.08:14:30.89#ibcon#end of sib2, iclass 37, count 0 2006.280.08:14:30.89#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:14:30.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:14:30.89#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:14:30.89#ibcon#*before write, iclass 37, count 0 2006.280.08:14:30.89#ibcon#enter sib2, iclass 37, count 0 2006.280.08:14:30.89#ibcon#flushed, iclass 37, count 0 2006.280.08:14:30.89#ibcon#about to write, iclass 37, count 0 2006.280.08:14:30.89#ibcon#wrote, iclass 37, count 0 2006.280.08:14:30.89#ibcon#about to read 3, iclass 37, count 0 2006.280.08:14:30.93#ibcon#read 3, iclass 37, count 0 2006.280.08:14:30.93#ibcon#about to read 4, iclass 37, count 0 2006.280.08:14:30.93#ibcon#read 4, iclass 37, count 0 2006.280.08:14:30.93#ibcon#about to read 5, iclass 37, count 0 2006.280.08:14:30.93#ibcon#read 5, iclass 37, count 0 2006.280.08:14:30.93#ibcon#about to read 6, iclass 37, count 0 2006.280.08:14:30.93#ibcon#read 6, iclass 37, count 0 2006.280.08:14:30.93#ibcon#end of sib2, iclass 37, count 0 2006.280.08:14:30.93#ibcon#*after write, iclass 37, count 0 2006.280.08:14:30.93#ibcon#*before return 0, iclass 37, count 0 2006.280.08:14:30.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:30.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:30.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:14:30.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:14:30.93$vc4f8/va=2,6 2006.280.08:14:30.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.08:14:30.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.08:14:30.93#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:30.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:30.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:30.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:30.98#ibcon#enter wrdev, iclass 39, count 2 2006.280.08:14:30.98#ibcon#first serial, iclass 39, count 2 2006.280.08:14:30.98#ibcon#enter sib2, iclass 39, count 2 2006.280.08:14:30.98#ibcon#flushed, iclass 39, count 2 2006.280.08:14:30.98#ibcon#about to write, iclass 39, count 2 2006.280.08:14:30.99#ibcon#wrote, iclass 39, count 2 2006.280.08:14:30.99#ibcon#about to read 3, iclass 39, count 2 2006.280.08:14:31.01#ibcon#read 3, iclass 39, count 2 2006.280.08:14:31.01#ibcon#about to read 4, iclass 39, count 2 2006.280.08:14:31.01#ibcon#read 4, iclass 39, count 2 2006.280.08:14:31.01#ibcon#about to read 5, iclass 39, count 2 2006.280.08:14:31.01#ibcon#read 5, iclass 39, count 2 2006.280.08:14:31.01#ibcon#about to read 6, iclass 39, count 2 2006.280.08:14:31.01#ibcon#read 6, iclass 39, count 2 2006.280.08:14:31.01#ibcon#end of sib2, iclass 39, count 2 2006.280.08:14:31.01#ibcon#*mode == 0, iclass 39, count 2 2006.280.08:14:31.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.08:14:31.01#ibcon#[25=AT02-06\r\n] 2006.280.08:14:31.01#ibcon#*before write, iclass 39, count 2 2006.280.08:14:31.01#ibcon#enter sib2, iclass 39, count 2 2006.280.08:14:31.01#ibcon#flushed, iclass 39, count 2 2006.280.08:14:31.01#ibcon#about to write, iclass 39, count 2 2006.280.08:14:31.01#ibcon#wrote, iclass 39, count 2 2006.280.08:14:31.01#ibcon#about to read 3, iclass 39, count 2 2006.280.08:14:31.03#ibcon#read 3, iclass 39, count 2 2006.280.08:14:31.03#ibcon#about to read 4, iclass 39, count 2 2006.280.08:14:31.03#ibcon#read 4, iclass 39, count 2 2006.280.08:14:31.03#ibcon#about to read 5, iclass 39, count 2 2006.280.08:14:31.04#ibcon#read 5, iclass 39, count 2 2006.280.08:14:31.04#ibcon#about to read 6, iclass 39, count 2 2006.280.08:14:31.04#ibcon#read 6, iclass 39, count 2 2006.280.08:14:31.04#ibcon#end of sib2, iclass 39, count 2 2006.280.08:14:31.04#ibcon#*after write, iclass 39, count 2 2006.280.08:14:31.04#ibcon#*before return 0, iclass 39, count 2 2006.280.08:14:31.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:31.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:31.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.08:14:31.04#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:31.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:31.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:31.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:31.16#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:14:31.16#ibcon#first serial, iclass 39, count 0 2006.280.08:14:31.16#ibcon#enter sib2, iclass 39, count 0 2006.280.08:14:31.16#ibcon#flushed, iclass 39, count 0 2006.280.08:14:31.16#ibcon#about to write, iclass 39, count 0 2006.280.08:14:31.16#ibcon#wrote, iclass 39, count 0 2006.280.08:14:31.16#ibcon#about to read 3, iclass 39, count 0 2006.280.08:14:31.17#ibcon#read 3, iclass 39, count 0 2006.280.08:14:31.17#ibcon#about to read 4, iclass 39, count 0 2006.280.08:14:31.17#ibcon#read 4, iclass 39, count 0 2006.280.08:14:31.17#ibcon#about to read 5, iclass 39, count 0 2006.280.08:14:31.17#ibcon#read 5, iclass 39, count 0 2006.280.08:14:31.18#ibcon#about to read 6, iclass 39, count 0 2006.280.08:14:31.18#ibcon#read 6, iclass 39, count 0 2006.280.08:14:31.18#ibcon#end of sib2, iclass 39, count 0 2006.280.08:14:31.18#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:14:31.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:14:31.18#ibcon#[25=USB\r\n] 2006.280.08:14:31.18#ibcon#*before write, iclass 39, count 0 2006.280.08:14:31.18#ibcon#enter sib2, iclass 39, count 0 2006.280.08:14:31.18#ibcon#flushed, iclass 39, count 0 2006.280.08:14:31.18#ibcon#about to write, iclass 39, count 0 2006.280.08:14:31.18#ibcon#wrote, iclass 39, count 0 2006.280.08:14:31.18#ibcon#about to read 3, iclass 39, count 0 2006.280.08:14:31.20#ibcon#read 3, iclass 39, count 0 2006.280.08:14:31.20#ibcon#about to read 4, iclass 39, count 0 2006.280.08:14:31.20#ibcon#read 4, iclass 39, count 0 2006.280.08:14:31.20#ibcon#about to read 5, iclass 39, count 0 2006.280.08:14:31.20#ibcon#read 5, iclass 39, count 0 2006.280.08:14:31.20#ibcon#about to read 6, iclass 39, count 0 2006.280.08:14:31.21#ibcon#read 6, iclass 39, count 0 2006.280.08:14:31.21#ibcon#end of sib2, iclass 39, count 0 2006.280.08:14:31.21#ibcon#*after write, iclass 39, count 0 2006.280.08:14:31.21#ibcon#*before return 0, iclass 39, count 0 2006.280.08:14:31.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:31.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:31.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:14:31.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:14:31.21$vc4f8/valo=3,672.99 2006.280.08:14:31.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.08:14:31.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.08:14:31.21#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:31.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:31.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:31.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:31.21#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:14:31.21#ibcon#first serial, iclass 3, count 0 2006.280.08:14:31.21#ibcon#enter sib2, iclass 3, count 0 2006.280.08:14:31.21#ibcon#flushed, iclass 3, count 0 2006.280.08:14:31.21#ibcon#about to write, iclass 3, count 0 2006.280.08:14:31.21#ibcon#wrote, iclass 3, count 0 2006.280.08:14:31.21#ibcon#about to read 3, iclass 3, count 0 2006.280.08:14:31.22#ibcon#read 3, iclass 3, count 0 2006.280.08:14:31.22#ibcon#about to read 4, iclass 3, count 0 2006.280.08:14:31.22#ibcon#read 4, iclass 3, count 0 2006.280.08:14:31.22#ibcon#about to read 5, iclass 3, count 0 2006.280.08:14:31.22#ibcon#read 5, iclass 3, count 0 2006.280.08:14:31.22#ibcon#about to read 6, iclass 3, count 0 2006.280.08:14:31.22#ibcon#read 6, iclass 3, count 0 2006.280.08:14:31.23#ibcon#end of sib2, iclass 3, count 0 2006.280.08:14:31.23#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:14:31.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:14:31.23#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:14:31.23#ibcon#*before write, iclass 3, count 0 2006.280.08:14:31.23#ibcon#enter sib2, iclass 3, count 0 2006.280.08:14:31.23#ibcon#flushed, iclass 3, count 0 2006.280.08:14:31.23#ibcon#about to write, iclass 3, count 0 2006.280.08:14:31.23#ibcon#wrote, iclass 3, count 0 2006.280.08:14:31.23#ibcon#about to read 3, iclass 3, count 0 2006.280.08:14:31.26#ibcon#read 3, iclass 3, count 0 2006.280.08:14:31.26#ibcon#about to read 4, iclass 3, count 0 2006.280.08:14:31.26#ibcon#read 4, iclass 3, count 0 2006.280.08:14:31.26#ibcon#about to read 5, iclass 3, count 0 2006.280.08:14:31.26#ibcon#read 5, iclass 3, count 0 2006.280.08:14:31.26#ibcon#about to read 6, iclass 3, count 0 2006.280.08:14:31.26#ibcon#read 6, iclass 3, count 0 2006.280.08:14:31.27#ibcon#end of sib2, iclass 3, count 0 2006.280.08:14:31.27#ibcon#*after write, iclass 3, count 0 2006.280.08:14:31.27#ibcon#*before return 0, iclass 3, count 0 2006.280.08:14:31.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:31.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:31.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:14:31.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:14:31.27$vc4f8/va=3,6 2006.280.08:14:31.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.08:14:31.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.08:14:31.27#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:31.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:31.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:31.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:31.33#ibcon#enter wrdev, iclass 5, count 2 2006.280.08:14:31.33#ibcon#first serial, iclass 5, count 2 2006.280.08:14:31.33#ibcon#enter sib2, iclass 5, count 2 2006.280.08:14:31.33#ibcon#flushed, iclass 5, count 2 2006.280.08:14:31.33#ibcon#about to write, iclass 5, count 2 2006.280.08:14:31.33#ibcon#wrote, iclass 5, count 2 2006.280.08:14:31.33#ibcon#about to read 3, iclass 5, count 2 2006.280.08:14:31.35#ibcon#read 3, iclass 5, count 2 2006.280.08:14:31.35#ibcon#about to read 4, iclass 5, count 2 2006.280.08:14:31.35#ibcon#read 4, iclass 5, count 2 2006.280.08:14:31.35#ibcon#about to read 5, iclass 5, count 2 2006.280.08:14:31.35#ibcon#read 5, iclass 5, count 2 2006.280.08:14:31.35#ibcon#about to read 6, iclass 5, count 2 2006.280.08:14:31.35#ibcon#read 6, iclass 5, count 2 2006.280.08:14:31.35#ibcon#end of sib2, iclass 5, count 2 2006.280.08:14:31.35#ibcon#*mode == 0, iclass 5, count 2 2006.280.08:14:31.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.08:14:31.35#ibcon#[25=AT03-06\r\n] 2006.280.08:14:31.35#ibcon#*before write, iclass 5, count 2 2006.280.08:14:31.35#ibcon#enter sib2, iclass 5, count 2 2006.280.08:14:31.35#ibcon#flushed, iclass 5, count 2 2006.280.08:14:31.35#ibcon#about to write, iclass 5, count 2 2006.280.08:14:31.35#ibcon#wrote, iclass 5, count 2 2006.280.08:14:31.35#ibcon#about to read 3, iclass 5, count 2 2006.280.08:14:31.37#ibcon#read 3, iclass 5, count 2 2006.280.08:14:31.37#ibcon#about to read 4, iclass 5, count 2 2006.280.08:14:31.37#ibcon#read 4, iclass 5, count 2 2006.280.08:14:31.37#ibcon#about to read 5, iclass 5, count 2 2006.280.08:14:31.37#ibcon#read 5, iclass 5, count 2 2006.280.08:14:31.37#ibcon#about to read 6, iclass 5, count 2 2006.280.08:14:31.37#ibcon#read 6, iclass 5, count 2 2006.280.08:14:31.38#ibcon#end of sib2, iclass 5, count 2 2006.280.08:14:31.38#ibcon#*after write, iclass 5, count 2 2006.280.08:14:31.38#ibcon#*before return 0, iclass 5, count 2 2006.280.08:14:31.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:31.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:31.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.08:14:31.38#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:31.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:31.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:31.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:31.49#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:14:31.49#ibcon#first serial, iclass 5, count 0 2006.280.08:14:31.49#ibcon#enter sib2, iclass 5, count 0 2006.280.08:14:31.49#ibcon#flushed, iclass 5, count 0 2006.280.08:14:31.50#ibcon#about to write, iclass 5, count 0 2006.280.08:14:31.50#ibcon#wrote, iclass 5, count 0 2006.280.08:14:31.50#ibcon#about to read 3, iclass 5, count 0 2006.280.08:14:31.51#ibcon#read 3, iclass 5, count 0 2006.280.08:14:31.51#ibcon#about to read 4, iclass 5, count 0 2006.280.08:14:31.51#ibcon#read 4, iclass 5, count 0 2006.280.08:14:31.51#ibcon#about to read 5, iclass 5, count 0 2006.280.08:14:31.51#ibcon#read 5, iclass 5, count 0 2006.280.08:14:31.51#ibcon#about to read 6, iclass 5, count 0 2006.280.08:14:31.52#ibcon#read 6, iclass 5, count 0 2006.280.08:14:31.52#ibcon#end of sib2, iclass 5, count 0 2006.280.08:14:31.52#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:14:31.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:14:31.52#ibcon#[25=USB\r\n] 2006.280.08:14:31.52#ibcon#*before write, iclass 5, count 0 2006.280.08:14:31.52#ibcon#enter sib2, iclass 5, count 0 2006.280.08:14:31.52#ibcon#flushed, iclass 5, count 0 2006.280.08:14:31.52#ibcon#about to write, iclass 5, count 0 2006.280.08:14:31.52#ibcon#wrote, iclass 5, count 0 2006.280.08:14:31.52#ibcon#about to read 3, iclass 5, count 0 2006.280.08:14:31.54#ibcon#read 3, iclass 5, count 0 2006.280.08:14:31.54#ibcon#about to read 4, iclass 5, count 0 2006.280.08:14:31.54#ibcon#read 4, iclass 5, count 0 2006.280.08:14:31.54#ibcon#about to read 5, iclass 5, count 0 2006.280.08:14:31.55#ibcon#read 5, iclass 5, count 0 2006.280.08:14:31.55#ibcon#about to read 6, iclass 5, count 0 2006.280.08:14:31.55#ibcon#read 6, iclass 5, count 0 2006.280.08:14:31.55#ibcon#end of sib2, iclass 5, count 0 2006.280.08:14:31.55#ibcon#*after write, iclass 5, count 0 2006.280.08:14:31.55#ibcon#*before return 0, iclass 5, count 0 2006.280.08:14:31.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:31.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:31.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:14:31.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:14:31.55$vc4f8/valo=4,832.99 2006.280.08:14:31.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.08:14:31.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.08:14:31.55#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:31.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:31.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:31.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:31.55#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:14:31.55#ibcon#first serial, iclass 7, count 0 2006.280.08:14:31.55#ibcon#enter sib2, iclass 7, count 0 2006.280.08:14:31.55#ibcon#flushed, iclass 7, count 0 2006.280.08:14:31.55#ibcon#about to write, iclass 7, count 0 2006.280.08:14:31.55#ibcon#wrote, iclass 7, count 0 2006.280.08:14:31.55#ibcon#about to read 3, iclass 7, count 0 2006.280.08:14:31.56#ibcon#read 3, iclass 7, count 0 2006.280.08:14:31.56#ibcon#about to read 4, iclass 7, count 0 2006.280.08:14:31.56#ibcon#read 4, iclass 7, count 0 2006.280.08:14:31.56#ibcon#about to read 5, iclass 7, count 0 2006.280.08:14:31.57#ibcon#read 5, iclass 7, count 0 2006.280.08:14:31.57#ibcon#about to read 6, iclass 7, count 0 2006.280.08:14:31.57#ibcon#read 6, iclass 7, count 0 2006.280.08:14:31.57#ibcon#end of sib2, iclass 7, count 0 2006.280.08:14:31.57#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:14:31.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:14:31.57#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:14:31.57#ibcon#*before write, iclass 7, count 0 2006.280.08:14:31.57#ibcon#enter sib2, iclass 7, count 0 2006.280.08:14:31.57#ibcon#flushed, iclass 7, count 0 2006.280.08:14:31.57#ibcon#about to write, iclass 7, count 0 2006.280.08:14:31.57#ibcon#wrote, iclass 7, count 0 2006.280.08:14:31.57#ibcon#about to read 3, iclass 7, count 0 2006.280.08:14:31.60#ibcon#read 3, iclass 7, count 0 2006.280.08:14:31.60#ibcon#about to read 4, iclass 7, count 0 2006.280.08:14:31.61#ibcon#read 4, iclass 7, count 0 2006.280.08:14:31.61#ibcon#about to read 5, iclass 7, count 0 2006.280.08:14:31.61#ibcon#read 5, iclass 7, count 0 2006.280.08:14:31.61#ibcon#about to read 6, iclass 7, count 0 2006.280.08:14:31.61#ibcon#read 6, iclass 7, count 0 2006.280.08:14:31.61#ibcon#end of sib2, iclass 7, count 0 2006.280.08:14:31.61#ibcon#*after write, iclass 7, count 0 2006.280.08:14:31.61#ibcon#*before return 0, iclass 7, count 0 2006.280.08:14:31.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:31.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:31.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:14:31.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:14:31.61$vc4f8/va=4,6 2006.280.08:14:31.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.08:14:31.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.08:14:31.61#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:31.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:31.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:31.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:31.66#ibcon#enter wrdev, iclass 11, count 2 2006.280.08:14:31.66#ibcon#first serial, iclass 11, count 2 2006.280.08:14:31.66#ibcon#enter sib2, iclass 11, count 2 2006.280.08:14:31.66#ibcon#flushed, iclass 11, count 2 2006.280.08:14:31.66#ibcon#about to write, iclass 11, count 2 2006.280.08:14:31.67#ibcon#wrote, iclass 11, count 2 2006.280.08:14:31.67#ibcon#about to read 3, iclass 11, count 2 2006.280.08:14:31.69#ibcon#read 3, iclass 11, count 2 2006.280.08:14:31.69#ibcon#about to read 4, iclass 11, count 2 2006.280.08:14:31.69#ibcon#read 4, iclass 11, count 2 2006.280.08:14:31.69#ibcon#about to read 5, iclass 11, count 2 2006.280.08:14:31.69#ibcon#read 5, iclass 11, count 2 2006.280.08:14:31.69#ibcon#about to read 6, iclass 11, count 2 2006.280.08:14:31.69#ibcon#read 6, iclass 11, count 2 2006.280.08:14:31.69#ibcon#end of sib2, iclass 11, count 2 2006.280.08:14:31.69#ibcon#*mode == 0, iclass 11, count 2 2006.280.08:14:31.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.08:14:31.69#ibcon#[25=AT04-06\r\n] 2006.280.08:14:31.69#ibcon#*before write, iclass 11, count 2 2006.280.08:14:31.69#ibcon#enter sib2, iclass 11, count 2 2006.280.08:14:31.69#ibcon#flushed, iclass 11, count 2 2006.280.08:14:31.69#ibcon#about to write, iclass 11, count 2 2006.280.08:14:31.69#ibcon#wrote, iclass 11, count 2 2006.280.08:14:31.69#ibcon#about to read 3, iclass 11, count 2 2006.280.08:14:31.72#ibcon#read 3, iclass 11, count 2 2006.280.08:14:31.72#ibcon#about to read 4, iclass 11, count 2 2006.280.08:14:31.72#ibcon#read 4, iclass 11, count 2 2006.280.08:14:31.72#ibcon#about to read 5, iclass 11, count 2 2006.280.08:14:31.72#ibcon#read 5, iclass 11, count 2 2006.280.08:14:31.72#ibcon#about to read 6, iclass 11, count 2 2006.280.08:14:31.73#ibcon#read 6, iclass 11, count 2 2006.280.08:14:31.73#ibcon#end of sib2, iclass 11, count 2 2006.280.08:14:31.73#ibcon#*after write, iclass 11, count 2 2006.280.08:14:31.73#ibcon#*before return 0, iclass 11, count 2 2006.280.08:14:31.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:31.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:31.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.08:14:31.73#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:31.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:31.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:31.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:31.84#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:14:31.84#ibcon#first serial, iclass 11, count 0 2006.280.08:14:31.84#ibcon#enter sib2, iclass 11, count 0 2006.280.08:14:31.84#ibcon#flushed, iclass 11, count 0 2006.280.08:14:31.84#ibcon#about to write, iclass 11, count 0 2006.280.08:14:31.85#ibcon#wrote, iclass 11, count 0 2006.280.08:14:31.85#ibcon#about to read 3, iclass 11, count 0 2006.280.08:14:31.86#ibcon#read 3, iclass 11, count 0 2006.280.08:14:31.86#ibcon#about to read 4, iclass 11, count 0 2006.280.08:14:31.86#ibcon#read 4, iclass 11, count 0 2006.280.08:14:31.86#ibcon#about to read 5, iclass 11, count 0 2006.280.08:14:31.86#ibcon#read 5, iclass 11, count 0 2006.280.08:14:31.86#ibcon#about to read 6, iclass 11, count 0 2006.280.08:14:31.86#ibcon#read 6, iclass 11, count 0 2006.280.08:14:31.87#ibcon#end of sib2, iclass 11, count 0 2006.280.08:14:31.87#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:14:31.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:14:31.87#ibcon#[25=USB\r\n] 2006.280.08:14:31.87#ibcon#*before write, iclass 11, count 0 2006.280.08:14:31.87#ibcon#enter sib2, iclass 11, count 0 2006.280.08:14:31.87#ibcon#flushed, iclass 11, count 0 2006.280.08:14:31.87#ibcon#about to write, iclass 11, count 0 2006.280.08:14:31.87#ibcon#wrote, iclass 11, count 0 2006.280.08:14:31.87#ibcon#about to read 3, iclass 11, count 0 2006.280.08:14:31.89#ibcon#read 3, iclass 11, count 0 2006.280.08:14:31.89#ibcon#about to read 4, iclass 11, count 0 2006.280.08:14:31.89#ibcon#read 4, iclass 11, count 0 2006.280.08:14:31.89#ibcon#about to read 5, iclass 11, count 0 2006.280.08:14:31.89#ibcon#read 5, iclass 11, count 0 2006.280.08:14:31.89#ibcon#about to read 6, iclass 11, count 0 2006.280.08:14:31.89#ibcon#read 6, iclass 11, count 0 2006.280.08:14:31.89#ibcon#end of sib2, iclass 11, count 0 2006.280.08:14:31.90#ibcon#*after write, iclass 11, count 0 2006.280.08:14:31.90#ibcon#*before return 0, iclass 11, count 0 2006.280.08:14:31.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:31.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:31.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:14:31.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:14:31.90$vc4f8/valo=5,652.99 2006.280.08:14:31.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.08:14:31.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.08:14:31.90#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:31.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:31.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:31.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:31.90#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:14:31.90#ibcon#first serial, iclass 13, count 0 2006.280.08:14:31.90#ibcon#enter sib2, iclass 13, count 0 2006.280.08:14:31.90#ibcon#flushed, iclass 13, count 0 2006.280.08:14:31.90#ibcon#about to write, iclass 13, count 0 2006.280.08:14:31.90#ibcon#wrote, iclass 13, count 0 2006.280.08:14:31.90#ibcon#about to read 3, iclass 13, count 0 2006.280.08:14:31.91#ibcon#read 3, iclass 13, count 0 2006.280.08:14:31.92#ibcon#about to read 4, iclass 13, count 0 2006.280.08:14:31.92#ibcon#read 4, iclass 13, count 0 2006.280.08:14:31.92#ibcon#about to read 5, iclass 13, count 0 2006.280.08:14:31.92#ibcon#read 5, iclass 13, count 0 2006.280.08:14:31.92#ibcon#about to read 6, iclass 13, count 0 2006.280.08:14:31.92#ibcon#read 6, iclass 13, count 0 2006.280.08:14:31.92#ibcon#end of sib2, iclass 13, count 0 2006.280.08:14:31.92#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:14:31.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:14:31.92#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:14:31.92#ibcon#*before write, iclass 13, count 0 2006.280.08:14:31.92#ibcon#enter sib2, iclass 13, count 0 2006.280.08:14:31.92#ibcon#flushed, iclass 13, count 0 2006.280.08:14:31.92#ibcon#about to write, iclass 13, count 0 2006.280.08:14:31.92#ibcon#wrote, iclass 13, count 0 2006.280.08:14:31.92#ibcon#about to read 3, iclass 13, count 0 2006.280.08:14:31.95#ibcon#read 3, iclass 13, count 0 2006.280.08:14:31.95#ibcon#about to read 4, iclass 13, count 0 2006.280.08:14:31.95#ibcon#read 4, iclass 13, count 0 2006.280.08:14:31.95#ibcon#about to read 5, iclass 13, count 0 2006.280.08:14:31.95#ibcon#read 5, iclass 13, count 0 2006.280.08:14:31.95#ibcon#about to read 6, iclass 13, count 0 2006.280.08:14:31.95#ibcon#read 6, iclass 13, count 0 2006.280.08:14:31.96#ibcon#end of sib2, iclass 13, count 0 2006.280.08:14:31.96#ibcon#*after write, iclass 13, count 0 2006.280.08:14:31.96#ibcon#*before return 0, iclass 13, count 0 2006.280.08:14:31.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:31.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:31.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:14:31.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:14:31.96$vc4f8/va=5,7 2006.280.08:14:31.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.08:14:31.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.08:14:31.96#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:31.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:32.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:32.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:32.02#ibcon#enter wrdev, iclass 15, count 2 2006.280.08:14:32.02#ibcon#first serial, iclass 15, count 2 2006.280.08:14:32.02#ibcon#enter sib2, iclass 15, count 2 2006.280.08:14:32.02#ibcon#flushed, iclass 15, count 2 2006.280.08:14:32.02#ibcon#about to write, iclass 15, count 2 2006.280.08:14:32.02#ibcon#wrote, iclass 15, count 2 2006.280.08:14:32.02#ibcon#about to read 3, iclass 15, count 2 2006.280.08:14:32.03#ibcon#read 3, iclass 15, count 2 2006.280.08:14:32.03#ibcon#about to read 4, iclass 15, count 2 2006.280.08:14:32.04#ibcon#read 4, iclass 15, count 2 2006.280.08:14:32.04#ibcon#about to read 5, iclass 15, count 2 2006.280.08:14:32.04#ibcon#read 5, iclass 15, count 2 2006.280.08:14:32.04#ibcon#about to read 6, iclass 15, count 2 2006.280.08:14:32.04#ibcon#read 6, iclass 15, count 2 2006.280.08:14:32.04#ibcon#end of sib2, iclass 15, count 2 2006.280.08:14:32.04#ibcon#*mode == 0, iclass 15, count 2 2006.280.08:14:32.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.08:14:32.04#ibcon#[25=AT05-07\r\n] 2006.280.08:14:32.04#ibcon#*before write, iclass 15, count 2 2006.280.08:14:32.04#ibcon#enter sib2, iclass 15, count 2 2006.280.08:14:32.04#ibcon#flushed, iclass 15, count 2 2006.280.08:14:32.04#ibcon#about to write, iclass 15, count 2 2006.280.08:14:32.04#ibcon#wrote, iclass 15, count 2 2006.280.08:14:32.04#ibcon#about to read 3, iclass 15, count 2 2006.280.08:14:32.07#ibcon#read 3, iclass 15, count 2 2006.280.08:14:32.07#ibcon#about to read 4, iclass 15, count 2 2006.280.08:14:32.07#ibcon#read 4, iclass 15, count 2 2006.280.08:14:32.07#ibcon#about to read 5, iclass 15, count 2 2006.280.08:14:32.07#ibcon#read 5, iclass 15, count 2 2006.280.08:14:32.07#ibcon#about to read 6, iclass 15, count 2 2006.280.08:14:32.07#ibcon#read 6, iclass 15, count 2 2006.280.08:14:32.07#ibcon#end of sib2, iclass 15, count 2 2006.280.08:14:32.07#ibcon#*after write, iclass 15, count 2 2006.280.08:14:32.07#ibcon#*before return 0, iclass 15, count 2 2006.280.08:14:32.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:32.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:32.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.08:14:32.07#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:32.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:32.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:32.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:32.19#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:14:32.19#ibcon#first serial, iclass 15, count 0 2006.280.08:14:32.19#ibcon#enter sib2, iclass 15, count 0 2006.280.08:14:32.19#ibcon#flushed, iclass 15, count 0 2006.280.08:14:32.19#ibcon#about to write, iclass 15, count 0 2006.280.08:14:32.19#ibcon#wrote, iclass 15, count 0 2006.280.08:14:32.19#ibcon#about to read 3, iclass 15, count 0 2006.280.08:14:32.20#ibcon#read 3, iclass 15, count 0 2006.280.08:14:32.20#ibcon#about to read 4, iclass 15, count 0 2006.280.08:14:32.20#ibcon#read 4, iclass 15, count 0 2006.280.08:14:32.20#ibcon#about to read 5, iclass 15, count 0 2006.280.08:14:32.20#ibcon#read 5, iclass 15, count 0 2006.280.08:14:32.20#ibcon#about to read 6, iclass 15, count 0 2006.280.08:14:32.20#ibcon#read 6, iclass 15, count 0 2006.280.08:14:32.21#ibcon#end of sib2, iclass 15, count 0 2006.280.08:14:32.21#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:14:32.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:14:32.21#ibcon#[25=USB\r\n] 2006.280.08:14:32.21#ibcon#*before write, iclass 15, count 0 2006.280.08:14:32.21#ibcon#enter sib2, iclass 15, count 0 2006.280.08:14:32.21#ibcon#flushed, iclass 15, count 0 2006.280.08:14:32.21#ibcon#about to write, iclass 15, count 0 2006.280.08:14:32.21#ibcon#wrote, iclass 15, count 0 2006.280.08:14:32.21#ibcon#about to read 3, iclass 15, count 0 2006.280.08:14:32.23#ibcon#read 3, iclass 15, count 0 2006.280.08:14:32.24#ibcon#about to read 4, iclass 15, count 0 2006.280.08:14:32.24#ibcon#read 4, iclass 15, count 0 2006.280.08:14:32.24#ibcon#about to read 5, iclass 15, count 0 2006.280.08:14:32.24#ibcon#read 5, iclass 15, count 0 2006.280.08:14:32.24#ibcon#about to read 6, iclass 15, count 0 2006.280.08:14:32.24#ibcon#read 6, iclass 15, count 0 2006.280.08:14:32.24#ibcon#end of sib2, iclass 15, count 0 2006.280.08:14:32.24#ibcon#*after write, iclass 15, count 0 2006.280.08:14:32.24#ibcon#*before return 0, iclass 15, count 0 2006.280.08:14:32.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:32.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:32.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:14:32.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:14:32.24$vc4f8/valo=6,772.99 2006.280.08:14:32.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.08:14:32.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.08:14:32.24#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:32.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:32.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:32.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:32.24#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:14:32.24#ibcon#first serial, iclass 17, count 0 2006.280.08:14:32.24#ibcon#enter sib2, iclass 17, count 0 2006.280.08:14:32.24#ibcon#flushed, iclass 17, count 0 2006.280.08:14:32.24#ibcon#about to write, iclass 17, count 0 2006.280.08:14:32.24#ibcon#wrote, iclass 17, count 0 2006.280.08:14:32.24#ibcon#about to read 3, iclass 17, count 0 2006.280.08:14:32.25#ibcon#read 3, iclass 17, count 0 2006.280.08:14:32.25#ibcon#about to read 4, iclass 17, count 0 2006.280.08:14:32.25#ibcon#read 4, iclass 17, count 0 2006.280.08:14:32.25#ibcon#about to read 5, iclass 17, count 0 2006.280.08:14:32.25#ibcon#read 5, iclass 17, count 0 2006.280.08:14:32.25#ibcon#about to read 6, iclass 17, count 0 2006.280.08:14:32.25#ibcon#read 6, iclass 17, count 0 2006.280.08:14:32.26#ibcon#end of sib2, iclass 17, count 0 2006.280.08:14:32.26#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:14:32.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:14:32.26#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:14:32.26#ibcon#*before write, iclass 17, count 0 2006.280.08:14:32.26#ibcon#enter sib2, iclass 17, count 0 2006.280.08:14:32.26#ibcon#flushed, iclass 17, count 0 2006.280.08:14:32.26#ibcon#about to write, iclass 17, count 0 2006.280.08:14:32.26#ibcon#wrote, iclass 17, count 0 2006.280.08:14:32.26#ibcon#about to read 3, iclass 17, count 0 2006.280.08:14:32.29#ibcon#read 3, iclass 17, count 0 2006.280.08:14:32.30#ibcon#about to read 4, iclass 17, count 0 2006.280.08:14:32.30#ibcon#read 4, iclass 17, count 0 2006.280.08:14:32.30#ibcon#about to read 5, iclass 17, count 0 2006.280.08:14:32.30#ibcon#read 5, iclass 17, count 0 2006.280.08:14:32.30#ibcon#about to read 6, iclass 17, count 0 2006.280.08:14:32.30#ibcon#read 6, iclass 17, count 0 2006.280.08:14:32.30#ibcon#end of sib2, iclass 17, count 0 2006.280.08:14:32.30#ibcon#*after write, iclass 17, count 0 2006.280.08:14:32.30#ibcon#*before return 0, iclass 17, count 0 2006.280.08:14:32.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:32.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:32.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:14:32.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:14:32.30$vc4f8/va=6,6 2006.280.08:14:32.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.08:14:32.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.08:14:32.30#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:32.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:32.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:32.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:32.35#ibcon#enter wrdev, iclass 19, count 2 2006.280.08:14:32.35#ibcon#first serial, iclass 19, count 2 2006.280.08:14:32.35#ibcon#enter sib2, iclass 19, count 2 2006.280.08:14:32.35#ibcon#flushed, iclass 19, count 2 2006.280.08:14:32.35#ibcon#about to write, iclass 19, count 2 2006.280.08:14:32.36#ibcon#wrote, iclass 19, count 2 2006.280.08:14:32.36#ibcon#about to read 3, iclass 19, count 2 2006.280.08:14:32.37#ibcon#read 3, iclass 19, count 2 2006.280.08:14:32.37#ibcon#about to read 4, iclass 19, count 2 2006.280.08:14:32.37#ibcon#read 4, iclass 19, count 2 2006.280.08:14:32.37#ibcon#about to read 5, iclass 19, count 2 2006.280.08:14:32.37#ibcon#read 5, iclass 19, count 2 2006.280.08:14:32.37#ibcon#about to read 6, iclass 19, count 2 2006.280.08:14:32.37#ibcon#read 6, iclass 19, count 2 2006.280.08:14:32.38#ibcon#end of sib2, iclass 19, count 2 2006.280.08:14:32.38#ibcon#*mode == 0, iclass 19, count 2 2006.280.08:14:32.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.08:14:32.38#ibcon#[25=AT06-06\r\n] 2006.280.08:14:32.38#ibcon#*before write, iclass 19, count 2 2006.280.08:14:32.38#ibcon#enter sib2, iclass 19, count 2 2006.280.08:14:32.38#ibcon#flushed, iclass 19, count 2 2006.280.08:14:32.38#ibcon#about to write, iclass 19, count 2 2006.280.08:14:32.38#ibcon#wrote, iclass 19, count 2 2006.280.08:14:32.38#ibcon#about to read 3, iclass 19, count 2 2006.280.08:14:32.40#ibcon#read 3, iclass 19, count 2 2006.280.08:14:32.40#ibcon#about to read 4, iclass 19, count 2 2006.280.08:14:32.40#ibcon#read 4, iclass 19, count 2 2006.280.08:14:32.40#ibcon#about to read 5, iclass 19, count 2 2006.280.08:14:32.40#ibcon#read 5, iclass 19, count 2 2006.280.08:14:32.40#ibcon#about to read 6, iclass 19, count 2 2006.280.08:14:32.40#ibcon#read 6, iclass 19, count 2 2006.280.08:14:32.41#ibcon#end of sib2, iclass 19, count 2 2006.280.08:14:32.41#ibcon#*after write, iclass 19, count 2 2006.280.08:14:32.41#ibcon#*before return 0, iclass 19, count 2 2006.280.08:14:32.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:32.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:32.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.08:14:32.41#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:32.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:32.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:32.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:32.53#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:14:32.53#ibcon#first serial, iclass 19, count 0 2006.280.08:14:32.53#ibcon#enter sib2, iclass 19, count 0 2006.280.08:14:32.53#ibcon#flushed, iclass 19, count 0 2006.280.08:14:32.53#ibcon#about to write, iclass 19, count 0 2006.280.08:14:32.53#ibcon#wrote, iclass 19, count 0 2006.280.08:14:32.53#ibcon#about to read 3, iclass 19, count 0 2006.280.08:14:32.54#ibcon#read 3, iclass 19, count 0 2006.280.08:14:32.54#ibcon#about to read 4, iclass 19, count 0 2006.280.08:14:32.55#ibcon#read 4, iclass 19, count 0 2006.280.08:14:32.55#ibcon#about to read 5, iclass 19, count 0 2006.280.08:14:32.55#ibcon#read 5, iclass 19, count 0 2006.280.08:14:32.55#ibcon#about to read 6, iclass 19, count 0 2006.280.08:14:32.55#ibcon#read 6, iclass 19, count 0 2006.280.08:14:32.55#ibcon#end of sib2, iclass 19, count 0 2006.280.08:14:32.55#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:14:32.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:14:32.55#ibcon#[25=USB\r\n] 2006.280.08:14:32.55#ibcon#*before write, iclass 19, count 0 2006.280.08:14:32.55#ibcon#enter sib2, iclass 19, count 0 2006.280.08:14:32.55#ibcon#flushed, iclass 19, count 0 2006.280.08:14:32.55#ibcon#about to write, iclass 19, count 0 2006.280.08:14:32.55#ibcon#wrote, iclass 19, count 0 2006.280.08:14:32.55#ibcon#about to read 3, iclass 19, count 0 2006.280.08:14:32.57#ibcon#read 3, iclass 19, count 0 2006.280.08:14:32.57#ibcon#about to read 4, iclass 19, count 0 2006.280.08:14:32.57#ibcon#read 4, iclass 19, count 0 2006.280.08:14:32.57#ibcon#about to read 5, iclass 19, count 0 2006.280.08:14:32.57#ibcon#read 5, iclass 19, count 0 2006.280.08:14:32.57#ibcon#about to read 6, iclass 19, count 0 2006.280.08:14:32.57#ibcon#read 6, iclass 19, count 0 2006.280.08:14:32.58#ibcon#end of sib2, iclass 19, count 0 2006.280.08:14:32.58#ibcon#*after write, iclass 19, count 0 2006.280.08:14:32.58#ibcon#*before return 0, iclass 19, count 0 2006.280.08:14:32.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:32.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:32.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:14:32.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:14:32.58$vc4f8/valo=7,832.99 2006.280.08:14:32.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.08:14:32.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.08:14:32.58#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:32.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:32.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:32.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:32.58#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:14:32.58#ibcon#first serial, iclass 21, count 0 2006.280.08:14:32.58#ibcon#enter sib2, iclass 21, count 0 2006.280.08:14:32.58#ibcon#flushed, iclass 21, count 0 2006.280.08:14:32.58#ibcon#about to write, iclass 21, count 0 2006.280.08:14:32.58#ibcon#wrote, iclass 21, count 0 2006.280.08:14:32.58#ibcon#about to read 3, iclass 21, count 0 2006.280.08:14:32.59#ibcon#read 3, iclass 21, count 0 2006.280.08:14:32.59#ibcon#about to read 4, iclass 21, count 0 2006.280.08:14:32.59#ibcon#read 4, iclass 21, count 0 2006.280.08:14:32.59#ibcon#about to read 5, iclass 21, count 0 2006.280.08:14:32.59#ibcon#read 5, iclass 21, count 0 2006.280.08:14:32.59#ibcon#about to read 6, iclass 21, count 0 2006.280.08:14:32.59#ibcon#read 6, iclass 21, count 0 2006.280.08:14:32.60#ibcon#end of sib2, iclass 21, count 0 2006.280.08:14:32.60#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:14:32.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:14:32.60#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:14:32.60#ibcon#*before write, iclass 21, count 0 2006.280.08:14:32.60#ibcon#enter sib2, iclass 21, count 0 2006.280.08:14:32.60#ibcon#flushed, iclass 21, count 0 2006.280.08:14:32.60#ibcon#about to write, iclass 21, count 0 2006.280.08:14:32.60#ibcon#wrote, iclass 21, count 0 2006.280.08:14:32.60#ibcon#about to read 3, iclass 21, count 0 2006.280.08:14:32.63#ibcon#read 3, iclass 21, count 0 2006.280.08:14:32.63#ibcon#about to read 4, iclass 21, count 0 2006.280.08:14:32.63#ibcon#read 4, iclass 21, count 0 2006.280.08:14:32.63#ibcon#about to read 5, iclass 21, count 0 2006.280.08:14:32.63#ibcon#read 5, iclass 21, count 0 2006.280.08:14:32.63#ibcon#about to read 6, iclass 21, count 0 2006.280.08:14:32.63#ibcon#read 6, iclass 21, count 0 2006.280.08:14:32.64#ibcon#end of sib2, iclass 21, count 0 2006.280.08:14:32.64#ibcon#*after write, iclass 21, count 0 2006.280.08:14:32.64#ibcon#*before return 0, iclass 21, count 0 2006.280.08:14:32.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:32.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:32.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:14:32.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:14:32.64$vc4f8/va=7,6 2006.280.08:14:32.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.280.08:14:32.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.280.08:14:32.64#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:32.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:32.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:32.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:32.69#ibcon#enter wrdev, iclass 23, count 2 2006.280.08:14:32.69#ibcon#first serial, iclass 23, count 2 2006.280.08:14:32.69#ibcon#enter sib2, iclass 23, count 2 2006.280.08:14:32.69#ibcon#flushed, iclass 23, count 2 2006.280.08:14:32.69#ibcon#about to write, iclass 23, count 2 2006.280.08:14:32.70#ibcon#wrote, iclass 23, count 2 2006.280.08:14:32.70#ibcon#about to read 3, iclass 23, count 2 2006.280.08:14:32.72#ibcon#read 3, iclass 23, count 2 2006.280.08:14:32.72#ibcon#about to read 4, iclass 23, count 2 2006.280.08:14:32.72#ibcon#read 4, iclass 23, count 2 2006.280.08:14:32.72#ibcon#about to read 5, iclass 23, count 2 2006.280.08:14:32.72#ibcon#read 5, iclass 23, count 2 2006.280.08:14:32.72#ibcon#about to read 6, iclass 23, count 2 2006.280.08:14:32.72#ibcon#read 6, iclass 23, count 2 2006.280.08:14:32.72#ibcon#end of sib2, iclass 23, count 2 2006.280.08:14:32.72#ibcon#*mode == 0, iclass 23, count 2 2006.280.08:14:32.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.280.08:14:32.72#ibcon#[25=AT07-06\r\n] 2006.280.08:14:32.72#ibcon#*before write, iclass 23, count 2 2006.280.08:14:32.72#ibcon#enter sib2, iclass 23, count 2 2006.280.08:14:32.72#ibcon#flushed, iclass 23, count 2 2006.280.08:14:32.72#ibcon#about to write, iclass 23, count 2 2006.280.08:14:32.72#ibcon#wrote, iclass 23, count 2 2006.280.08:14:32.72#ibcon#about to read 3, iclass 23, count 2 2006.280.08:14:32.75#ibcon#read 3, iclass 23, count 2 2006.280.08:14:32.75#ibcon#about to read 4, iclass 23, count 2 2006.280.08:14:32.75#ibcon#read 4, iclass 23, count 2 2006.280.08:14:32.75#ibcon#about to read 5, iclass 23, count 2 2006.280.08:14:32.75#ibcon#read 5, iclass 23, count 2 2006.280.08:14:32.76#ibcon#about to read 6, iclass 23, count 2 2006.280.08:14:32.76#ibcon#read 6, iclass 23, count 2 2006.280.08:14:32.76#ibcon#end of sib2, iclass 23, count 2 2006.280.08:14:32.76#ibcon#*after write, iclass 23, count 2 2006.280.08:14:32.76#ibcon#*before return 0, iclass 23, count 2 2006.280.08:14:32.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:32.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:32.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.280.08:14:32.76#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:32.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:14:32.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:14:32.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:14:32.87#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:14:32.87#ibcon#first serial, iclass 23, count 0 2006.280.08:14:32.87#ibcon#enter sib2, iclass 23, count 0 2006.280.08:14:32.87#ibcon#flushed, iclass 23, count 0 2006.280.08:14:32.87#ibcon#about to write, iclass 23, count 0 2006.280.08:14:32.88#ibcon#wrote, iclass 23, count 0 2006.280.08:14:32.88#ibcon#about to read 3, iclass 23, count 0 2006.280.08:14:32.89#ibcon#read 3, iclass 23, count 0 2006.280.08:14:32.89#ibcon#about to read 4, iclass 23, count 0 2006.280.08:14:32.89#ibcon#read 4, iclass 23, count 0 2006.280.08:14:32.89#ibcon#about to read 5, iclass 23, count 0 2006.280.08:14:32.89#ibcon#read 5, iclass 23, count 0 2006.280.08:14:32.89#ibcon#about to read 6, iclass 23, count 0 2006.280.08:14:32.89#ibcon#read 6, iclass 23, count 0 2006.280.08:14:32.90#ibcon#end of sib2, iclass 23, count 0 2006.280.08:14:32.90#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:14:32.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:14:32.90#ibcon#[25=USB\r\n] 2006.280.08:14:32.90#ibcon#*before write, iclass 23, count 0 2006.280.08:14:32.90#ibcon#enter sib2, iclass 23, count 0 2006.280.08:14:32.90#ibcon#flushed, iclass 23, count 0 2006.280.08:14:32.90#ibcon#about to write, iclass 23, count 0 2006.280.08:14:32.90#ibcon#wrote, iclass 23, count 0 2006.280.08:14:32.90#ibcon#about to read 3, iclass 23, count 0 2006.280.08:14:32.93#ibcon#read 3, iclass 23, count 0 2006.280.08:14:32.93#ibcon#about to read 4, iclass 23, count 0 2006.280.08:14:32.93#ibcon#read 4, iclass 23, count 0 2006.280.08:14:32.93#ibcon#about to read 5, iclass 23, count 0 2006.280.08:14:32.93#ibcon#read 5, iclass 23, count 0 2006.280.08:14:32.93#ibcon#about to read 6, iclass 23, count 0 2006.280.08:14:32.93#ibcon#read 6, iclass 23, count 0 2006.280.08:14:32.93#ibcon#end of sib2, iclass 23, count 0 2006.280.08:14:32.93#ibcon#*after write, iclass 23, count 0 2006.280.08:14:32.93#ibcon#*before return 0, iclass 23, count 0 2006.280.08:14:32.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:14:32.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.280.08:14:32.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:14:32.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:14:32.93$vc4f8/valo=8,852.99 2006.280.08:14:32.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.280.08:14:32.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.280.08:14:32.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:32.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:14:32.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:14:32.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:14:32.93#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:14:32.93#ibcon#first serial, iclass 25, count 0 2006.280.08:14:32.93#ibcon#enter sib2, iclass 25, count 0 2006.280.08:14:32.93#ibcon#flushed, iclass 25, count 0 2006.280.08:14:32.93#ibcon#about to write, iclass 25, count 0 2006.280.08:14:32.93#ibcon#wrote, iclass 25, count 0 2006.280.08:14:32.93#ibcon#about to read 3, iclass 25, count 0 2006.280.08:14:32.95#ibcon#read 3, iclass 25, count 0 2006.280.08:14:32.95#ibcon#about to read 4, iclass 25, count 0 2006.280.08:14:32.95#ibcon#read 4, iclass 25, count 0 2006.280.08:14:32.95#ibcon#about to read 5, iclass 25, count 0 2006.280.08:14:32.95#ibcon#read 5, iclass 25, count 0 2006.280.08:14:32.95#ibcon#about to read 6, iclass 25, count 0 2006.280.08:14:32.95#ibcon#read 6, iclass 25, count 0 2006.280.08:14:32.95#ibcon#end of sib2, iclass 25, count 0 2006.280.08:14:32.95#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:14:32.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:14:32.95#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:14:32.95#ibcon#*before write, iclass 25, count 0 2006.280.08:14:32.95#ibcon#enter sib2, iclass 25, count 0 2006.280.08:14:32.95#ibcon#flushed, iclass 25, count 0 2006.280.08:14:32.95#ibcon#about to write, iclass 25, count 0 2006.280.08:14:32.95#ibcon#wrote, iclass 25, count 0 2006.280.08:14:32.95#ibcon#about to read 3, iclass 25, count 0 2006.280.08:14:32.98#ibcon#read 3, iclass 25, count 0 2006.280.08:14:32.98#ibcon#about to read 4, iclass 25, count 0 2006.280.08:14:32.98#ibcon#read 4, iclass 25, count 0 2006.280.08:14:32.98#ibcon#about to read 5, iclass 25, count 0 2006.280.08:14:32.98#ibcon#read 5, iclass 25, count 0 2006.280.08:14:32.98#ibcon#about to read 6, iclass 25, count 0 2006.280.08:14:32.99#ibcon#read 6, iclass 25, count 0 2006.280.08:14:32.99#ibcon#end of sib2, iclass 25, count 0 2006.280.08:14:32.99#ibcon#*after write, iclass 25, count 0 2006.280.08:14:32.99#ibcon#*before return 0, iclass 25, count 0 2006.280.08:14:32.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:14:32.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.280.08:14:32.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:14:32.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:14:32.99$vc4f8/va=8,6 2006.280.08:14:32.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.280.08:14:32.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.280.08:14:32.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:32.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:14:33.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:14:33.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:14:33.05#ibcon#enter wrdev, iclass 27, count 2 2006.280.08:14:33.05#ibcon#first serial, iclass 27, count 2 2006.280.08:14:33.05#ibcon#enter sib2, iclass 27, count 2 2006.280.08:14:33.05#ibcon#flushed, iclass 27, count 2 2006.280.08:14:33.05#ibcon#about to write, iclass 27, count 2 2006.280.08:14:33.05#ibcon#wrote, iclass 27, count 2 2006.280.08:14:33.05#ibcon#about to read 3, iclass 27, count 2 2006.280.08:14:33.07#ibcon#read 3, iclass 27, count 2 2006.280.08:14:33.07#ibcon#about to read 4, iclass 27, count 2 2006.280.08:14:33.07#ibcon#read 4, iclass 27, count 2 2006.280.08:14:33.07#ibcon#about to read 5, iclass 27, count 2 2006.280.08:14:33.07#ibcon#read 5, iclass 27, count 2 2006.280.08:14:33.07#ibcon#about to read 6, iclass 27, count 2 2006.280.08:14:33.07#ibcon#read 6, iclass 27, count 2 2006.280.08:14:33.07#ibcon#end of sib2, iclass 27, count 2 2006.280.08:14:33.07#ibcon#*mode == 0, iclass 27, count 2 2006.280.08:14:33.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.280.08:14:33.07#ibcon#[25=AT08-06\r\n] 2006.280.08:14:33.07#ibcon#*before write, iclass 27, count 2 2006.280.08:14:33.07#ibcon#enter sib2, iclass 27, count 2 2006.280.08:14:33.07#ibcon#flushed, iclass 27, count 2 2006.280.08:14:33.07#ibcon#about to write, iclass 27, count 2 2006.280.08:14:33.07#ibcon#wrote, iclass 27, count 2 2006.280.08:14:33.07#ibcon#about to read 3, iclass 27, count 2 2006.280.08:14:33.09#ibcon#read 3, iclass 27, count 2 2006.280.08:14:33.09#ibcon#about to read 4, iclass 27, count 2 2006.280.08:14:33.09#ibcon#read 4, iclass 27, count 2 2006.280.08:14:33.09#ibcon#about to read 5, iclass 27, count 2 2006.280.08:14:33.09#ibcon#read 5, iclass 27, count 2 2006.280.08:14:33.09#ibcon#about to read 6, iclass 27, count 2 2006.280.08:14:33.10#ibcon#read 6, iclass 27, count 2 2006.280.08:14:33.10#ibcon#end of sib2, iclass 27, count 2 2006.280.08:14:33.10#ibcon#*after write, iclass 27, count 2 2006.280.08:14:33.10#ibcon#*before return 0, iclass 27, count 2 2006.280.08:14:33.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:14:33.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.280.08:14:33.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.280.08:14:33.10#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:33.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:14:33.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:14:33.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:14:33.21#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:14:33.21#ibcon#first serial, iclass 27, count 0 2006.280.08:14:33.21#ibcon#enter sib2, iclass 27, count 0 2006.280.08:14:33.21#ibcon#flushed, iclass 27, count 0 2006.280.08:14:33.21#ibcon#about to write, iclass 27, count 0 2006.280.08:14:33.22#ibcon#wrote, iclass 27, count 0 2006.280.08:14:33.22#ibcon#about to read 3, iclass 27, count 0 2006.280.08:14:33.23#ibcon#read 3, iclass 27, count 0 2006.280.08:14:33.23#ibcon#about to read 4, iclass 27, count 0 2006.280.08:14:33.23#ibcon#read 4, iclass 27, count 0 2006.280.08:14:33.23#ibcon#about to read 5, iclass 27, count 0 2006.280.08:14:33.23#ibcon#read 5, iclass 27, count 0 2006.280.08:14:33.23#ibcon#about to read 6, iclass 27, count 0 2006.280.08:14:33.23#ibcon#read 6, iclass 27, count 0 2006.280.08:14:33.24#ibcon#end of sib2, iclass 27, count 0 2006.280.08:14:33.24#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:14:33.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:14:33.24#ibcon#[25=USB\r\n] 2006.280.08:14:33.24#ibcon#*before write, iclass 27, count 0 2006.280.08:14:33.24#ibcon#enter sib2, iclass 27, count 0 2006.280.08:14:33.24#ibcon#flushed, iclass 27, count 0 2006.280.08:14:33.24#ibcon#about to write, iclass 27, count 0 2006.280.08:14:33.24#ibcon#wrote, iclass 27, count 0 2006.280.08:14:33.24#ibcon#about to read 3, iclass 27, count 0 2006.280.08:14:33.26#ibcon#read 3, iclass 27, count 0 2006.280.08:14:33.26#ibcon#about to read 4, iclass 27, count 0 2006.280.08:14:33.26#ibcon#read 4, iclass 27, count 0 2006.280.08:14:33.26#ibcon#about to read 5, iclass 27, count 0 2006.280.08:14:33.26#ibcon#read 5, iclass 27, count 0 2006.280.08:14:33.26#ibcon#about to read 6, iclass 27, count 0 2006.280.08:14:33.26#ibcon#read 6, iclass 27, count 0 2006.280.08:14:33.27#ibcon#end of sib2, iclass 27, count 0 2006.280.08:14:33.27#ibcon#*after write, iclass 27, count 0 2006.280.08:14:33.27#ibcon#*before return 0, iclass 27, count 0 2006.280.08:14:33.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:14:33.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.280.08:14:33.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:14:33.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:14:33.27$vc4f8/vblo=1,632.99 2006.280.08:14:33.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.280.08:14:33.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.280.08:14:33.27#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:33.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:14:33.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:14:33.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:14:33.27#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:14:33.27#ibcon#first serial, iclass 29, count 0 2006.280.08:14:33.27#ibcon#enter sib2, iclass 29, count 0 2006.280.08:14:33.27#ibcon#flushed, iclass 29, count 0 2006.280.08:14:33.27#ibcon#about to write, iclass 29, count 0 2006.280.08:14:33.27#ibcon#wrote, iclass 29, count 0 2006.280.08:14:33.27#ibcon#about to read 3, iclass 29, count 0 2006.280.08:14:33.28#ibcon#read 3, iclass 29, count 0 2006.280.08:14:33.30#ibcon#about to read 4, iclass 29, count 0 2006.280.08:14:33.30#ibcon#read 4, iclass 29, count 0 2006.280.08:14:33.30#ibcon#about to read 5, iclass 29, count 0 2006.280.08:14:33.30#ibcon#read 5, iclass 29, count 0 2006.280.08:14:33.30#ibcon#about to read 6, iclass 29, count 0 2006.280.08:14:33.30#ibcon#read 6, iclass 29, count 0 2006.280.08:14:33.30#ibcon#end of sib2, iclass 29, count 0 2006.280.08:14:33.30#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:14:33.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:14:33.30#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:14:33.30#ibcon#*before write, iclass 29, count 0 2006.280.08:14:33.30#ibcon#enter sib2, iclass 29, count 0 2006.280.08:14:33.30#ibcon#flushed, iclass 29, count 0 2006.280.08:14:33.30#ibcon#about to write, iclass 29, count 0 2006.280.08:14:33.30#ibcon#wrote, iclass 29, count 0 2006.280.08:14:33.30#ibcon#about to read 3, iclass 29, count 0 2006.280.08:14:33.34#ibcon#read 3, iclass 29, count 0 2006.280.08:14:33.34#ibcon#about to read 4, iclass 29, count 0 2006.280.08:14:33.34#ibcon#read 4, iclass 29, count 0 2006.280.08:14:33.34#ibcon#about to read 5, iclass 29, count 0 2006.280.08:14:33.34#ibcon#read 5, iclass 29, count 0 2006.280.08:14:33.35#ibcon#about to read 6, iclass 29, count 0 2006.280.08:14:33.35#ibcon#read 6, iclass 29, count 0 2006.280.08:14:33.35#ibcon#end of sib2, iclass 29, count 0 2006.280.08:14:33.35#ibcon#*after write, iclass 29, count 0 2006.280.08:14:33.35#ibcon#*before return 0, iclass 29, count 0 2006.280.08:14:33.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:14:33.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.280.08:14:33.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:14:33.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:14:33.35$vc4f8/vb=1,4 2006.280.08:14:33.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:14:33.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:14:33.35#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:33.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:14:33.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:14:33.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:14:33.35#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:14:33.35#ibcon#first serial, iclass 32, count 2 2006.280.08:14:33.35#ibcon#enter sib2, iclass 32, count 2 2006.280.08:14:33.35#ibcon#flushed, iclass 32, count 2 2006.280.08:14:33.35#ibcon#about to write, iclass 32, count 2 2006.280.08:14:33.35#ibcon#wrote, iclass 32, count 2 2006.280.08:14:33.35#ibcon#about to read 3, iclass 32, count 2 2006.280.08:14:33.37#ibcon#read 3, iclass 32, count 2 2006.280.08:14:33.37#ibcon#about to read 4, iclass 32, count 2 2006.280.08:14:33.37#ibcon#read 4, iclass 32, count 2 2006.280.08:14:33.37#ibcon#about to read 5, iclass 32, count 2 2006.280.08:14:33.37#ibcon#read 5, iclass 32, count 2 2006.280.08:14:33.37#ibcon#about to read 6, iclass 32, count 2 2006.280.08:14:33.37#ibcon#read 6, iclass 32, count 2 2006.280.08:14:33.37#ibcon#end of sib2, iclass 32, count 2 2006.280.08:14:33.37#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:14:33.41#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:14:33.41#ibcon#[27=AT01-04\r\n] 2006.280.08:14:33.41#ibcon#*before write, iclass 32, count 2 2006.280.08:14:33.41#ibcon#enter sib2, iclass 32, count 2 2006.280.08:14:33.41#ibcon#flushed, iclass 32, count 2 2006.280.08:14:33.41#ibcon#about to write, iclass 32, count 2 2006.280.08:14:33.41#ibcon#wrote, iclass 32, count 2 2006.280.08:14:33.41#ibcon#about to read 3, iclass 32, count 2 2006.280.08:14:33.38#abcon#<5=/14 1.3 3.4 20.41 63 987.6\r\n> 2006.280.08:14:33.43#abcon#{5=INTERFACE CLEAR} 2006.280.08:14:33.45#ibcon#read 3, iclass 32, count 2 2006.280.08:14:33.45#ibcon#about to read 4, iclass 32, count 2 2006.280.08:14:33.45#ibcon#read 4, iclass 32, count 2 2006.280.08:14:33.45#ibcon#about to read 5, iclass 32, count 2 2006.280.08:14:33.45#ibcon#read 5, iclass 32, count 2 2006.280.08:14:33.45#ibcon#about to read 6, iclass 32, count 2 2006.280.08:14:33.45#ibcon#read 6, iclass 32, count 2 2006.280.08:14:33.45#ibcon#end of sib2, iclass 32, count 2 2006.280.08:14:33.45#ibcon#*after write, iclass 32, count 2 2006.280.08:14:33.45#ibcon#*before return 0, iclass 32, count 2 2006.280.08:14:33.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:14:33.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:14:33.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:14:33.45#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:33.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:14:33.50#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:14:33.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:14:33.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:14:33.57#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:14:33.57#ibcon#first serial, iclass 32, count 0 2006.280.08:14:33.57#ibcon#enter sib2, iclass 32, count 0 2006.280.08:14:33.57#ibcon#flushed, iclass 32, count 0 2006.280.08:14:33.57#ibcon#about to write, iclass 32, count 0 2006.280.08:14:33.57#ibcon#wrote, iclass 32, count 0 2006.280.08:14:33.57#ibcon#about to read 3, iclass 32, count 0 2006.280.08:14:33.58#ibcon#read 3, iclass 32, count 0 2006.280.08:14:33.58#ibcon#about to read 4, iclass 32, count 0 2006.280.08:14:33.58#ibcon#read 4, iclass 32, count 0 2006.280.08:14:33.58#ibcon#about to read 5, iclass 32, count 0 2006.280.08:14:33.58#ibcon#read 5, iclass 32, count 0 2006.280.08:14:33.58#ibcon#about to read 6, iclass 32, count 0 2006.280.08:14:33.58#ibcon#read 6, iclass 32, count 0 2006.280.08:14:33.59#ibcon#end of sib2, iclass 32, count 0 2006.280.08:14:33.59#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:14:33.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:14:33.59#ibcon#[27=USB\r\n] 2006.280.08:14:33.59#ibcon#*before write, iclass 32, count 0 2006.280.08:14:33.59#ibcon#enter sib2, iclass 32, count 0 2006.280.08:14:33.59#ibcon#flushed, iclass 32, count 0 2006.280.08:14:33.59#ibcon#about to write, iclass 32, count 0 2006.280.08:14:33.59#ibcon#wrote, iclass 32, count 0 2006.280.08:14:33.59#ibcon#about to read 3, iclass 32, count 0 2006.280.08:14:33.61#ibcon#read 3, iclass 32, count 0 2006.280.08:14:33.61#ibcon#about to read 4, iclass 32, count 0 2006.280.08:14:33.62#ibcon#read 4, iclass 32, count 0 2006.280.08:14:33.62#ibcon#about to read 5, iclass 32, count 0 2006.280.08:14:33.62#ibcon#read 5, iclass 32, count 0 2006.280.08:14:33.62#ibcon#about to read 6, iclass 32, count 0 2006.280.08:14:33.62#ibcon#read 6, iclass 32, count 0 2006.280.08:14:33.62#ibcon#end of sib2, iclass 32, count 0 2006.280.08:14:33.62#ibcon#*after write, iclass 32, count 0 2006.280.08:14:33.62#ibcon#*before return 0, iclass 32, count 0 2006.280.08:14:33.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:14:33.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:14:33.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:14:33.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:14:33.62$vc4f8/vblo=2,640.99 2006.280.08:14:33.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.280.08:14:33.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.280.08:14:33.62#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:33.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:33.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:33.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:33.62#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:14:33.62#ibcon#first serial, iclass 37, count 0 2006.280.08:14:33.62#ibcon#enter sib2, iclass 37, count 0 2006.280.08:14:33.62#ibcon#flushed, iclass 37, count 0 2006.280.08:14:33.62#ibcon#about to write, iclass 37, count 0 2006.280.08:14:33.62#ibcon#wrote, iclass 37, count 0 2006.280.08:14:33.62#ibcon#about to read 3, iclass 37, count 0 2006.280.08:14:33.63#ibcon#read 3, iclass 37, count 0 2006.280.08:14:33.63#ibcon#about to read 4, iclass 37, count 0 2006.280.08:14:33.63#ibcon#read 4, iclass 37, count 0 2006.280.08:14:33.63#ibcon#about to read 5, iclass 37, count 0 2006.280.08:14:33.63#ibcon#read 5, iclass 37, count 0 2006.280.08:14:33.63#ibcon#about to read 6, iclass 37, count 0 2006.280.08:14:33.63#ibcon#read 6, iclass 37, count 0 2006.280.08:14:33.64#ibcon#end of sib2, iclass 37, count 0 2006.280.08:14:33.64#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:14:33.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:14:33.64#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:14:33.64#ibcon#*before write, iclass 37, count 0 2006.280.08:14:33.64#ibcon#enter sib2, iclass 37, count 0 2006.280.08:14:33.64#ibcon#flushed, iclass 37, count 0 2006.280.08:14:33.64#ibcon#about to write, iclass 37, count 0 2006.280.08:14:33.64#ibcon#wrote, iclass 37, count 0 2006.280.08:14:33.64#ibcon#about to read 3, iclass 37, count 0 2006.280.08:14:33.68#ibcon#read 3, iclass 37, count 0 2006.280.08:14:33.68#ibcon#about to read 4, iclass 37, count 0 2006.280.08:14:33.68#ibcon#read 4, iclass 37, count 0 2006.280.08:14:33.68#ibcon#about to read 5, iclass 37, count 0 2006.280.08:14:33.68#ibcon#read 5, iclass 37, count 0 2006.280.08:14:33.68#ibcon#about to read 6, iclass 37, count 0 2006.280.08:14:33.68#ibcon#read 6, iclass 37, count 0 2006.280.08:14:33.68#ibcon#end of sib2, iclass 37, count 0 2006.280.08:14:33.68#ibcon#*after write, iclass 37, count 0 2006.280.08:14:33.68#ibcon#*before return 0, iclass 37, count 0 2006.280.08:14:33.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:33.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.280.08:14:33.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:14:33.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:14:33.68$vc4f8/vb=2,5 2006.280.08:14:33.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.08:14:33.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.08:14:33.68#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:33.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:33.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:33.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:33.73#ibcon#enter wrdev, iclass 39, count 2 2006.280.08:14:33.73#ibcon#first serial, iclass 39, count 2 2006.280.08:14:33.73#ibcon#enter sib2, iclass 39, count 2 2006.280.08:14:33.73#ibcon#flushed, iclass 39, count 2 2006.280.08:14:33.73#ibcon#about to write, iclass 39, count 2 2006.280.08:14:33.74#ibcon#wrote, iclass 39, count 2 2006.280.08:14:33.74#ibcon#about to read 3, iclass 39, count 2 2006.280.08:14:33.75#ibcon#read 3, iclass 39, count 2 2006.280.08:14:33.75#ibcon#about to read 4, iclass 39, count 2 2006.280.08:14:33.75#ibcon#read 4, iclass 39, count 2 2006.280.08:14:33.75#ibcon#about to read 5, iclass 39, count 2 2006.280.08:14:33.75#ibcon#read 5, iclass 39, count 2 2006.280.08:14:33.75#ibcon#about to read 6, iclass 39, count 2 2006.280.08:14:33.75#ibcon#read 6, iclass 39, count 2 2006.280.08:14:33.76#ibcon#end of sib2, iclass 39, count 2 2006.280.08:14:33.76#ibcon#*mode == 0, iclass 39, count 2 2006.280.08:14:33.76#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.08:14:33.76#ibcon#[27=AT02-05\r\n] 2006.280.08:14:33.76#ibcon#*before write, iclass 39, count 2 2006.280.08:14:33.76#ibcon#enter sib2, iclass 39, count 2 2006.280.08:14:33.76#ibcon#flushed, iclass 39, count 2 2006.280.08:14:33.76#ibcon#about to write, iclass 39, count 2 2006.280.08:14:33.76#ibcon#wrote, iclass 39, count 2 2006.280.08:14:33.76#ibcon#about to read 3, iclass 39, count 2 2006.280.08:14:33.78#ibcon#read 3, iclass 39, count 2 2006.280.08:14:33.78#ibcon#about to read 4, iclass 39, count 2 2006.280.08:14:33.78#ibcon#read 4, iclass 39, count 2 2006.280.08:14:33.78#ibcon#about to read 5, iclass 39, count 2 2006.280.08:14:33.78#ibcon#read 5, iclass 39, count 2 2006.280.08:14:33.78#ibcon#about to read 6, iclass 39, count 2 2006.280.08:14:33.78#ibcon#read 6, iclass 39, count 2 2006.280.08:14:33.79#ibcon#end of sib2, iclass 39, count 2 2006.280.08:14:33.79#ibcon#*after write, iclass 39, count 2 2006.280.08:14:33.79#ibcon#*before return 0, iclass 39, count 2 2006.280.08:14:33.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:33.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:14:33.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.08:14:33.79#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:33.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:33.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:33.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:33.91#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:14:33.91#ibcon#first serial, iclass 39, count 0 2006.280.08:14:33.91#ibcon#enter sib2, iclass 39, count 0 2006.280.08:14:33.91#ibcon#flushed, iclass 39, count 0 2006.280.08:14:33.91#ibcon#about to write, iclass 39, count 0 2006.280.08:14:33.91#ibcon#wrote, iclass 39, count 0 2006.280.08:14:33.91#ibcon#about to read 3, iclass 39, count 0 2006.280.08:14:33.92#ibcon#read 3, iclass 39, count 0 2006.280.08:14:33.92#ibcon#about to read 4, iclass 39, count 0 2006.280.08:14:33.92#ibcon#read 4, iclass 39, count 0 2006.280.08:14:33.92#ibcon#about to read 5, iclass 39, count 0 2006.280.08:14:33.92#ibcon#read 5, iclass 39, count 0 2006.280.08:14:33.93#ibcon#about to read 6, iclass 39, count 0 2006.280.08:14:33.93#ibcon#read 6, iclass 39, count 0 2006.280.08:14:33.93#ibcon#end of sib2, iclass 39, count 0 2006.280.08:14:33.93#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:14:33.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:14:33.93#ibcon#[27=USB\r\n] 2006.280.08:14:33.93#ibcon#*before write, iclass 39, count 0 2006.280.08:14:33.93#ibcon#enter sib2, iclass 39, count 0 2006.280.08:14:33.93#ibcon#flushed, iclass 39, count 0 2006.280.08:14:33.93#ibcon#about to write, iclass 39, count 0 2006.280.08:14:33.93#ibcon#wrote, iclass 39, count 0 2006.280.08:14:33.93#ibcon#about to read 3, iclass 39, count 0 2006.280.08:14:33.95#ibcon#read 3, iclass 39, count 0 2006.280.08:14:33.95#ibcon#about to read 4, iclass 39, count 0 2006.280.08:14:33.95#ibcon#read 4, iclass 39, count 0 2006.280.08:14:33.95#ibcon#about to read 5, iclass 39, count 0 2006.280.08:14:33.95#ibcon#read 5, iclass 39, count 0 2006.280.08:14:33.95#ibcon#about to read 6, iclass 39, count 0 2006.280.08:14:33.95#ibcon#read 6, iclass 39, count 0 2006.280.08:14:33.96#ibcon#end of sib2, iclass 39, count 0 2006.280.08:14:33.96#ibcon#*after write, iclass 39, count 0 2006.280.08:14:33.96#ibcon#*before return 0, iclass 39, count 0 2006.280.08:14:33.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:33.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:14:33.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:14:33.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:14:33.96$vc4f8/vblo=3,656.99 2006.280.08:14:33.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.280.08:14:33.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.280.08:14:33.96#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:33.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:33.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:33.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:33.96#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:14:33.96#ibcon#first serial, iclass 3, count 0 2006.280.08:14:33.96#ibcon#enter sib2, iclass 3, count 0 2006.280.08:14:33.96#ibcon#flushed, iclass 3, count 0 2006.280.08:14:33.96#ibcon#about to write, iclass 3, count 0 2006.280.08:14:33.96#ibcon#wrote, iclass 3, count 0 2006.280.08:14:33.96#ibcon#about to read 3, iclass 3, count 0 2006.280.08:14:33.97#ibcon#read 3, iclass 3, count 0 2006.280.08:14:33.97#ibcon#about to read 4, iclass 3, count 0 2006.280.08:14:33.97#ibcon#read 4, iclass 3, count 0 2006.280.08:14:33.97#ibcon#about to read 5, iclass 3, count 0 2006.280.08:14:33.97#ibcon#read 5, iclass 3, count 0 2006.280.08:14:33.98#ibcon#about to read 6, iclass 3, count 0 2006.280.08:14:33.98#ibcon#read 6, iclass 3, count 0 2006.280.08:14:33.98#ibcon#end of sib2, iclass 3, count 0 2006.280.08:14:33.98#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:14:33.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:14:33.98#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:14:33.98#ibcon#*before write, iclass 3, count 0 2006.280.08:14:33.98#ibcon#enter sib2, iclass 3, count 0 2006.280.08:14:33.98#ibcon#flushed, iclass 3, count 0 2006.280.08:14:33.98#ibcon#about to write, iclass 3, count 0 2006.280.08:14:33.98#ibcon#wrote, iclass 3, count 0 2006.280.08:14:33.98#ibcon#about to read 3, iclass 3, count 0 2006.280.08:14:34.01#ibcon#read 3, iclass 3, count 0 2006.280.08:14:34.01#ibcon#about to read 4, iclass 3, count 0 2006.280.08:14:34.01#ibcon#read 4, iclass 3, count 0 2006.280.08:14:34.01#ibcon#about to read 5, iclass 3, count 0 2006.280.08:14:34.01#ibcon#read 5, iclass 3, count 0 2006.280.08:14:34.01#ibcon#about to read 6, iclass 3, count 0 2006.280.08:14:34.01#ibcon#read 6, iclass 3, count 0 2006.280.08:14:34.01#ibcon#end of sib2, iclass 3, count 0 2006.280.08:14:34.02#ibcon#*after write, iclass 3, count 0 2006.280.08:14:34.02#ibcon#*before return 0, iclass 3, count 0 2006.280.08:14:34.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:34.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.280.08:14:34.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:14:34.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:14:34.02$vc4f8/vb=3,4 2006.280.08:14:34.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.280.08:14:34.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.280.08:14:34.02#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:34.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:34.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:34.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:34.07#ibcon#enter wrdev, iclass 5, count 2 2006.280.08:14:34.07#ibcon#first serial, iclass 5, count 2 2006.280.08:14:34.07#ibcon#enter sib2, iclass 5, count 2 2006.280.08:14:34.07#ibcon#flushed, iclass 5, count 2 2006.280.08:14:34.07#ibcon#about to write, iclass 5, count 2 2006.280.08:14:34.08#ibcon#wrote, iclass 5, count 2 2006.280.08:14:34.08#ibcon#about to read 3, iclass 5, count 2 2006.280.08:14:34.10#ibcon#read 3, iclass 5, count 2 2006.280.08:14:34.10#ibcon#about to read 4, iclass 5, count 2 2006.280.08:14:34.10#ibcon#read 4, iclass 5, count 2 2006.280.08:14:34.10#ibcon#about to read 5, iclass 5, count 2 2006.280.08:14:34.10#ibcon#read 5, iclass 5, count 2 2006.280.08:14:34.10#ibcon#about to read 6, iclass 5, count 2 2006.280.08:14:34.10#ibcon#read 6, iclass 5, count 2 2006.280.08:14:34.10#ibcon#end of sib2, iclass 5, count 2 2006.280.08:14:34.10#ibcon#*mode == 0, iclass 5, count 2 2006.280.08:14:34.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.280.08:14:34.10#ibcon#[27=AT03-04\r\n] 2006.280.08:14:34.10#ibcon#*before write, iclass 5, count 2 2006.280.08:14:34.10#ibcon#enter sib2, iclass 5, count 2 2006.280.08:14:34.10#ibcon#flushed, iclass 5, count 2 2006.280.08:14:34.10#ibcon#about to write, iclass 5, count 2 2006.280.08:14:34.10#ibcon#wrote, iclass 5, count 2 2006.280.08:14:34.10#ibcon#about to read 3, iclass 5, count 2 2006.280.08:14:34.13#ibcon#read 3, iclass 5, count 2 2006.280.08:14:34.13#ibcon#about to read 4, iclass 5, count 2 2006.280.08:14:34.13#ibcon#read 4, iclass 5, count 2 2006.280.08:14:34.13#ibcon#about to read 5, iclass 5, count 2 2006.280.08:14:34.13#ibcon#read 5, iclass 5, count 2 2006.280.08:14:34.13#ibcon#about to read 6, iclass 5, count 2 2006.280.08:14:34.13#ibcon#read 6, iclass 5, count 2 2006.280.08:14:34.14#ibcon#end of sib2, iclass 5, count 2 2006.280.08:14:34.14#ibcon#*after write, iclass 5, count 2 2006.280.08:14:34.14#ibcon#*before return 0, iclass 5, count 2 2006.280.08:14:34.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:34.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.280.08:14:34.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.280.08:14:34.14#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:34.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:34.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:34.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:34.25#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:14:34.25#ibcon#first serial, iclass 5, count 0 2006.280.08:14:34.25#ibcon#enter sib2, iclass 5, count 0 2006.280.08:14:34.25#ibcon#flushed, iclass 5, count 0 2006.280.08:14:34.26#ibcon#about to write, iclass 5, count 0 2006.280.08:14:34.26#ibcon#wrote, iclass 5, count 0 2006.280.08:14:34.26#ibcon#about to read 3, iclass 5, count 0 2006.280.08:14:34.27#ibcon#read 3, iclass 5, count 0 2006.280.08:14:34.27#ibcon#about to read 4, iclass 5, count 0 2006.280.08:14:34.27#ibcon#read 4, iclass 5, count 0 2006.280.08:14:34.27#ibcon#about to read 5, iclass 5, count 0 2006.280.08:14:34.27#ibcon#read 5, iclass 5, count 0 2006.280.08:14:34.27#ibcon#about to read 6, iclass 5, count 0 2006.280.08:14:34.27#ibcon#read 6, iclass 5, count 0 2006.280.08:14:34.28#ibcon#end of sib2, iclass 5, count 0 2006.280.08:14:34.28#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:14:34.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:14:34.28#ibcon#[27=USB\r\n] 2006.280.08:14:34.28#ibcon#*before write, iclass 5, count 0 2006.280.08:14:34.28#ibcon#enter sib2, iclass 5, count 0 2006.280.08:14:34.28#ibcon#flushed, iclass 5, count 0 2006.280.08:14:34.28#ibcon#about to write, iclass 5, count 0 2006.280.08:14:34.28#ibcon#wrote, iclass 5, count 0 2006.280.08:14:34.28#ibcon#about to read 3, iclass 5, count 0 2006.280.08:14:34.31#ibcon#read 3, iclass 5, count 0 2006.280.08:14:34.31#ibcon#about to read 4, iclass 5, count 0 2006.280.08:14:34.31#ibcon#read 4, iclass 5, count 0 2006.280.08:14:34.31#ibcon#about to read 5, iclass 5, count 0 2006.280.08:14:34.31#ibcon#read 5, iclass 5, count 0 2006.280.08:14:34.31#ibcon#about to read 6, iclass 5, count 0 2006.280.08:14:34.31#ibcon#read 6, iclass 5, count 0 2006.280.08:14:34.31#ibcon#end of sib2, iclass 5, count 0 2006.280.08:14:34.31#ibcon#*after write, iclass 5, count 0 2006.280.08:14:34.31#ibcon#*before return 0, iclass 5, count 0 2006.280.08:14:34.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:34.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.280.08:14:34.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:14:34.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:14:34.31$vc4f8/vblo=4,712.99 2006.280.08:14:34.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.280.08:14:34.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.280.08:14:34.31#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:34.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:34.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:34.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:34.31#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:14:34.31#ibcon#first serial, iclass 7, count 0 2006.280.08:14:34.31#ibcon#enter sib2, iclass 7, count 0 2006.280.08:14:34.31#ibcon#flushed, iclass 7, count 0 2006.280.08:14:34.31#ibcon#about to write, iclass 7, count 0 2006.280.08:14:34.31#ibcon#wrote, iclass 7, count 0 2006.280.08:14:34.31#ibcon#about to read 3, iclass 7, count 0 2006.280.08:14:34.32#ibcon#read 3, iclass 7, count 0 2006.280.08:14:34.32#ibcon#about to read 4, iclass 7, count 0 2006.280.08:14:34.32#ibcon#read 4, iclass 7, count 0 2006.280.08:14:34.32#ibcon#about to read 5, iclass 7, count 0 2006.280.08:14:34.32#ibcon#read 5, iclass 7, count 0 2006.280.08:14:34.32#ibcon#about to read 6, iclass 7, count 0 2006.280.08:14:34.32#ibcon#read 6, iclass 7, count 0 2006.280.08:14:34.33#ibcon#end of sib2, iclass 7, count 0 2006.280.08:14:34.33#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:14:34.33#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:14:34.33#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:14:34.33#ibcon#*before write, iclass 7, count 0 2006.280.08:14:34.33#ibcon#enter sib2, iclass 7, count 0 2006.280.08:14:34.35#ibcon#flushed, iclass 7, count 0 2006.280.08:14:34.35#ibcon#about to write, iclass 7, count 0 2006.280.08:14:34.35#ibcon#wrote, iclass 7, count 0 2006.280.08:14:34.35#ibcon#about to read 3, iclass 7, count 0 2006.280.08:14:34.40#ibcon#read 3, iclass 7, count 0 2006.280.08:14:34.40#ibcon#about to read 4, iclass 7, count 0 2006.280.08:14:34.40#ibcon#read 4, iclass 7, count 0 2006.280.08:14:34.40#ibcon#about to read 5, iclass 7, count 0 2006.280.08:14:34.40#ibcon#read 5, iclass 7, count 0 2006.280.08:14:34.40#ibcon#about to read 6, iclass 7, count 0 2006.280.08:14:34.40#ibcon#read 6, iclass 7, count 0 2006.280.08:14:34.40#ibcon#end of sib2, iclass 7, count 0 2006.280.08:14:34.40#ibcon#*after write, iclass 7, count 0 2006.280.08:14:34.40#ibcon#*before return 0, iclass 7, count 0 2006.280.08:14:34.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:34.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.280.08:14:34.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:14:34.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:14:34.40$vc4f8/vb=4,4 2006.280.08:14:34.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.280.08:14:34.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.280.08:14:34.40#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:34.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:34.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:34.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:34.42#ibcon#enter wrdev, iclass 11, count 2 2006.280.08:14:34.42#ibcon#first serial, iclass 11, count 2 2006.280.08:14:34.42#ibcon#enter sib2, iclass 11, count 2 2006.280.08:14:34.42#ibcon#flushed, iclass 11, count 2 2006.280.08:14:34.43#ibcon#about to write, iclass 11, count 2 2006.280.08:14:34.43#ibcon#wrote, iclass 11, count 2 2006.280.08:14:34.43#ibcon#about to read 3, iclass 11, count 2 2006.280.08:14:34.45#ibcon#read 3, iclass 11, count 2 2006.280.08:14:34.45#ibcon#about to read 4, iclass 11, count 2 2006.280.08:14:34.45#ibcon#read 4, iclass 11, count 2 2006.280.08:14:34.45#ibcon#about to read 5, iclass 11, count 2 2006.280.08:14:34.45#ibcon#read 5, iclass 11, count 2 2006.280.08:14:34.45#ibcon#about to read 6, iclass 11, count 2 2006.280.08:14:34.45#ibcon#read 6, iclass 11, count 2 2006.280.08:14:34.45#ibcon#end of sib2, iclass 11, count 2 2006.280.08:14:34.45#ibcon#*mode == 0, iclass 11, count 2 2006.280.08:14:34.45#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.280.08:14:34.45#ibcon#[27=AT04-04\r\n] 2006.280.08:14:34.45#ibcon#*before write, iclass 11, count 2 2006.280.08:14:34.45#ibcon#enter sib2, iclass 11, count 2 2006.280.08:14:34.45#ibcon#flushed, iclass 11, count 2 2006.280.08:14:34.45#ibcon#about to write, iclass 11, count 2 2006.280.08:14:34.45#ibcon#wrote, iclass 11, count 2 2006.280.08:14:34.45#ibcon#about to read 3, iclass 11, count 2 2006.280.08:14:34.48#ibcon#read 3, iclass 11, count 2 2006.280.08:14:34.48#ibcon#about to read 4, iclass 11, count 2 2006.280.08:14:34.48#ibcon#read 4, iclass 11, count 2 2006.280.08:14:34.48#ibcon#about to read 5, iclass 11, count 2 2006.280.08:14:34.48#ibcon#read 5, iclass 11, count 2 2006.280.08:14:34.48#ibcon#about to read 6, iclass 11, count 2 2006.280.08:14:34.48#ibcon#read 6, iclass 11, count 2 2006.280.08:14:34.49#ibcon#end of sib2, iclass 11, count 2 2006.280.08:14:34.49#ibcon#*after write, iclass 11, count 2 2006.280.08:14:34.49#ibcon#*before return 0, iclass 11, count 2 2006.280.08:14:34.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:34.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.280.08:14:34.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.280.08:14:34.49#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:34.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:34.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:34.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:34.60#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:14:34.60#ibcon#first serial, iclass 11, count 0 2006.280.08:14:34.60#ibcon#enter sib2, iclass 11, count 0 2006.280.08:14:34.60#ibcon#flushed, iclass 11, count 0 2006.280.08:14:34.60#ibcon#about to write, iclass 11, count 0 2006.280.08:14:34.61#ibcon#wrote, iclass 11, count 0 2006.280.08:14:34.61#ibcon#about to read 3, iclass 11, count 0 2006.280.08:14:34.62#ibcon#read 3, iclass 11, count 0 2006.280.08:14:34.62#ibcon#about to read 4, iclass 11, count 0 2006.280.08:14:34.62#ibcon#read 4, iclass 11, count 0 2006.280.08:14:34.62#ibcon#about to read 5, iclass 11, count 0 2006.280.08:14:34.62#ibcon#read 5, iclass 11, count 0 2006.280.08:14:34.62#ibcon#about to read 6, iclass 11, count 0 2006.280.08:14:34.62#ibcon#read 6, iclass 11, count 0 2006.280.08:14:34.63#ibcon#end of sib2, iclass 11, count 0 2006.280.08:14:34.63#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:14:34.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:14:34.63#ibcon#[27=USB\r\n] 2006.280.08:14:34.63#ibcon#*before write, iclass 11, count 0 2006.280.08:14:34.63#ibcon#enter sib2, iclass 11, count 0 2006.280.08:14:34.63#ibcon#flushed, iclass 11, count 0 2006.280.08:14:34.63#ibcon#about to write, iclass 11, count 0 2006.280.08:14:34.63#ibcon#wrote, iclass 11, count 0 2006.280.08:14:34.63#ibcon#about to read 3, iclass 11, count 0 2006.280.08:14:34.65#ibcon#read 3, iclass 11, count 0 2006.280.08:14:34.65#ibcon#about to read 4, iclass 11, count 0 2006.280.08:14:34.65#ibcon#read 4, iclass 11, count 0 2006.280.08:14:34.65#ibcon#about to read 5, iclass 11, count 0 2006.280.08:14:34.65#ibcon#read 5, iclass 11, count 0 2006.280.08:14:34.65#ibcon#about to read 6, iclass 11, count 0 2006.280.08:14:34.65#ibcon#read 6, iclass 11, count 0 2006.280.08:14:34.66#ibcon#end of sib2, iclass 11, count 0 2006.280.08:14:34.66#ibcon#*after write, iclass 11, count 0 2006.280.08:14:34.66#ibcon#*before return 0, iclass 11, count 0 2006.280.08:14:34.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:34.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.280.08:14:34.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:14:34.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:14:34.66$vc4f8/vblo=5,744.99 2006.280.08:14:34.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.280.08:14:34.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.280.08:14:34.66#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:34.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:34.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:34.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:34.66#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:14:34.66#ibcon#first serial, iclass 13, count 0 2006.280.08:14:34.66#ibcon#enter sib2, iclass 13, count 0 2006.280.08:14:34.66#ibcon#flushed, iclass 13, count 0 2006.280.08:14:34.66#ibcon#about to write, iclass 13, count 0 2006.280.08:14:34.66#ibcon#wrote, iclass 13, count 0 2006.280.08:14:34.66#ibcon#about to read 3, iclass 13, count 0 2006.280.08:14:34.67#ibcon#read 3, iclass 13, count 0 2006.280.08:14:34.68#ibcon#about to read 4, iclass 13, count 0 2006.280.08:14:34.68#ibcon#read 4, iclass 13, count 0 2006.280.08:14:34.68#ibcon#about to read 5, iclass 13, count 0 2006.280.08:14:34.68#ibcon#read 5, iclass 13, count 0 2006.280.08:14:34.68#ibcon#about to read 6, iclass 13, count 0 2006.280.08:14:34.68#ibcon#read 6, iclass 13, count 0 2006.280.08:14:34.68#ibcon#end of sib2, iclass 13, count 0 2006.280.08:14:34.68#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:14:34.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:14:34.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:14:34.68#ibcon#*before write, iclass 13, count 0 2006.280.08:14:34.68#ibcon#enter sib2, iclass 13, count 0 2006.280.08:14:34.68#ibcon#flushed, iclass 13, count 0 2006.280.08:14:34.68#ibcon#about to write, iclass 13, count 0 2006.280.08:14:34.68#ibcon#wrote, iclass 13, count 0 2006.280.08:14:34.68#ibcon#about to read 3, iclass 13, count 0 2006.280.08:14:34.71#ibcon#read 3, iclass 13, count 0 2006.280.08:14:34.71#ibcon#about to read 4, iclass 13, count 0 2006.280.08:14:34.71#ibcon#read 4, iclass 13, count 0 2006.280.08:14:34.71#ibcon#about to read 5, iclass 13, count 0 2006.280.08:14:34.71#ibcon#read 5, iclass 13, count 0 2006.280.08:14:34.71#ibcon#about to read 6, iclass 13, count 0 2006.280.08:14:34.71#ibcon#read 6, iclass 13, count 0 2006.280.08:14:34.72#ibcon#end of sib2, iclass 13, count 0 2006.280.08:14:34.72#ibcon#*after write, iclass 13, count 0 2006.280.08:14:34.72#ibcon#*before return 0, iclass 13, count 0 2006.280.08:14:34.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:34.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.280.08:14:34.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:14:34.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:14:34.72$vc4f8/vb=5,4 2006.280.08:14:34.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.280.08:14:34.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.280.08:14:34.72#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:34.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:34.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:34.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:34.78#ibcon#enter wrdev, iclass 15, count 2 2006.280.08:14:34.78#ibcon#first serial, iclass 15, count 2 2006.280.08:14:34.78#ibcon#enter sib2, iclass 15, count 2 2006.280.08:14:34.78#ibcon#flushed, iclass 15, count 2 2006.280.08:14:34.78#ibcon#about to write, iclass 15, count 2 2006.280.08:14:34.78#ibcon#wrote, iclass 15, count 2 2006.280.08:14:34.78#ibcon#about to read 3, iclass 15, count 2 2006.280.08:14:34.80#ibcon#read 3, iclass 15, count 2 2006.280.08:14:34.80#ibcon#about to read 4, iclass 15, count 2 2006.280.08:14:34.80#ibcon#read 4, iclass 15, count 2 2006.280.08:14:34.80#ibcon#about to read 5, iclass 15, count 2 2006.280.08:14:34.80#ibcon#read 5, iclass 15, count 2 2006.280.08:14:34.80#ibcon#about to read 6, iclass 15, count 2 2006.280.08:14:34.80#ibcon#read 6, iclass 15, count 2 2006.280.08:14:34.80#ibcon#end of sib2, iclass 15, count 2 2006.280.08:14:34.80#ibcon#*mode == 0, iclass 15, count 2 2006.280.08:14:34.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.280.08:14:34.80#ibcon#[27=AT05-04\r\n] 2006.280.08:14:34.80#ibcon#*before write, iclass 15, count 2 2006.280.08:14:34.80#ibcon#enter sib2, iclass 15, count 2 2006.280.08:14:34.80#ibcon#flushed, iclass 15, count 2 2006.280.08:14:34.80#ibcon#about to write, iclass 15, count 2 2006.280.08:14:34.80#ibcon#wrote, iclass 15, count 2 2006.280.08:14:34.80#ibcon#about to read 3, iclass 15, count 2 2006.280.08:14:34.82#ibcon#read 3, iclass 15, count 2 2006.280.08:14:34.82#ibcon#about to read 4, iclass 15, count 2 2006.280.08:14:34.82#ibcon#read 4, iclass 15, count 2 2006.280.08:14:34.82#ibcon#about to read 5, iclass 15, count 2 2006.280.08:14:34.82#ibcon#read 5, iclass 15, count 2 2006.280.08:14:34.82#ibcon#about to read 6, iclass 15, count 2 2006.280.08:14:34.82#ibcon#read 6, iclass 15, count 2 2006.280.08:14:34.83#ibcon#end of sib2, iclass 15, count 2 2006.280.08:14:34.83#ibcon#*after write, iclass 15, count 2 2006.280.08:14:34.83#ibcon#*before return 0, iclass 15, count 2 2006.280.08:14:34.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:34.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.280.08:14:34.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.280.08:14:34.83#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:34.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:34.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:34.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:34.95#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:14:34.95#ibcon#first serial, iclass 15, count 0 2006.280.08:14:34.95#ibcon#enter sib2, iclass 15, count 0 2006.280.08:14:34.95#ibcon#flushed, iclass 15, count 0 2006.280.08:14:34.95#ibcon#about to write, iclass 15, count 0 2006.280.08:14:34.95#ibcon#wrote, iclass 15, count 0 2006.280.08:14:34.95#ibcon#about to read 3, iclass 15, count 0 2006.280.08:14:34.96#ibcon#read 3, iclass 15, count 0 2006.280.08:14:34.96#ibcon#about to read 4, iclass 15, count 0 2006.280.08:14:34.96#ibcon#read 4, iclass 15, count 0 2006.280.08:14:34.96#ibcon#about to read 5, iclass 15, count 0 2006.280.08:14:34.96#ibcon#read 5, iclass 15, count 0 2006.280.08:14:34.96#ibcon#about to read 6, iclass 15, count 0 2006.280.08:14:34.96#ibcon#read 6, iclass 15, count 0 2006.280.08:14:34.96#ibcon#end of sib2, iclass 15, count 0 2006.280.08:14:34.97#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:14:34.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:14:34.97#ibcon#[27=USB\r\n] 2006.280.08:14:34.97#ibcon#*before write, iclass 15, count 0 2006.280.08:14:34.97#ibcon#enter sib2, iclass 15, count 0 2006.280.08:14:34.97#ibcon#flushed, iclass 15, count 0 2006.280.08:14:34.97#ibcon#about to write, iclass 15, count 0 2006.280.08:14:34.97#ibcon#wrote, iclass 15, count 0 2006.280.08:14:34.97#ibcon#about to read 3, iclass 15, count 0 2006.280.08:14:34.99#ibcon#read 3, iclass 15, count 0 2006.280.08:14:34.99#ibcon#about to read 4, iclass 15, count 0 2006.280.08:14:34.99#ibcon#read 4, iclass 15, count 0 2006.280.08:14:34.99#ibcon#about to read 5, iclass 15, count 0 2006.280.08:14:34.99#ibcon#read 5, iclass 15, count 0 2006.280.08:14:34.99#ibcon#about to read 6, iclass 15, count 0 2006.280.08:14:34.99#ibcon#read 6, iclass 15, count 0 2006.280.08:14:35.00#ibcon#end of sib2, iclass 15, count 0 2006.280.08:14:35.00#ibcon#*after write, iclass 15, count 0 2006.280.08:14:35.00#ibcon#*before return 0, iclass 15, count 0 2006.280.08:14:35.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:35.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.280.08:14:35.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:14:35.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:14:35.00$vc4f8/vblo=6,752.99 2006.280.08:14:35.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.280.08:14:35.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.280.08:14:35.00#ibcon#ireg 17 cls_cnt 0 2006.280.08:14:35.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:35.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:35.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:35.00#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:14:35.00#ibcon#first serial, iclass 17, count 0 2006.280.08:14:35.00#ibcon#enter sib2, iclass 17, count 0 2006.280.08:14:35.00#ibcon#flushed, iclass 17, count 0 2006.280.08:14:35.00#ibcon#about to write, iclass 17, count 0 2006.280.08:14:35.00#ibcon#wrote, iclass 17, count 0 2006.280.08:14:35.00#ibcon#about to read 3, iclass 17, count 0 2006.280.08:14:35.01#ibcon#read 3, iclass 17, count 0 2006.280.08:14:35.02#ibcon#about to read 4, iclass 17, count 0 2006.280.08:14:35.02#ibcon#read 4, iclass 17, count 0 2006.280.08:14:35.02#ibcon#about to read 5, iclass 17, count 0 2006.280.08:14:35.02#ibcon#read 5, iclass 17, count 0 2006.280.08:14:35.02#ibcon#about to read 6, iclass 17, count 0 2006.280.08:14:35.02#ibcon#read 6, iclass 17, count 0 2006.280.08:14:35.02#ibcon#end of sib2, iclass 17, count 0 2006.280.08:14:35.02#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:14:35.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:14:35.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:14:35.02#ibcon#*before write, iclass 17, count 0 2006.280.08:14:35.02#ibcon#enter sib2, iclass 17, count 0 2006.280.08:14:35.02#ibcon#flushed, iclass 17, count 0 2006.280.08:14:35.02#ibcon#about to write, iclass 17, count 0 2006.280.08:14:35.02#ibcon#wrote, iclass 17, count 0 2006.280.08:14:35.02#ibcon#about to read 3, iclass 17, count 0 2006.280.08:14:35.06#ibcon#read 3, iclass 17, count 0 2006.280.08:14:35.06#ibcon#about to read 4, iclass 17, count 0 2006.280.08:14:35.06#ibcon#read 4, iclass 17, count 0 2006.280.08:14:35.06#ibcon#about to read 5, iclass 17, count 0 2006.280.08:14:35.06#ibcon#read 5, iclass 17, count 0 2006.280.08:14:35.06#ibcon#about to read 6, iclass 17, count 0 2006.280.08:14:35.06#ibcon#read 6, iclass 17, count 0 2006.280.08:14:35.06#ibcon#end of sib2, iclass 17, count 0 2006.280.08:14:35.06#ibcon#*after write, iclass 17, count 0 2006.280.08:14:35.06#ibcon#*before return 0, iclass 17, count 0 2006.280.08:14:35.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:35.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.280.08:14:35.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:14:35.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:14:35.06$vc4f8/vb=6,4 2006.280.08:14:35.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.280.08:14:35.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.280.08:14:35.06#ibcon#ireg 11 cls_cnt 2 2006.280.08:14:35.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:35.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:35.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:35.11#ibcon#enter wrdev, iclass 19, count 2 2006.280.08:14:35.11#ibcon#first serial, iclass 19, count 2 2006.280.08:14:35.11#ibcon#enter sib2, iclass 19, count 2 2006.280.08:14:35.11#ibcon#flushed, iclass 19, count 2 2006.280.08:14:35.12#ibcon#about to write, iclass 19, count 2 2006.280.08:14:35.12#ibcon#wrote, iclass 19, count 2 2006.280.08:14:35.12#ibcon#about to read 3, iclass 19, count 2 2006.280.08:14:35.13#ibcon#read 3, iclass 19, count 2 2006.280.08:14:35.13#ibcon#about to read 4, iclass 19, count 2 2006.280.08:14:35.13#ibcon#read 4, iclass 19, count 2 2006.280.08:14:35.13#ibcon#about to read 5, iclass 19, count 2 2006.280.08:14:35.13#ibcon#read 5, iclass 19, count 2 2006.280.08:14:35.13#ibcon#about to read 6, iclass 19, count 2 2006.280.08:14:35.14#ibcon#read 6, iclass 19, count 2 2006.280.08:14:35.14#ibcon#end of sib2, iclass 19, count 2 2006.280.08:14:35.14#ibcon#*mode == 0, iclass 19, count 2 2006.280.08:14:35.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.280.08:14:35.14#ibcon#[27=AT06-04\r\n] 2006.280.08:14:35.14#ibcon#*before write, iclass 19, count 2 2006.280.08:14:35.14#ibcon#enter sib2, iclass 19, count 2 2006.280.08:14:35.14#ibcon#flushed, iclass 19, count 2 2006.280.08:14:35.14#ibcon#about to write, iclass 19, count 2 2006.280.08:14:35.14#ibcon#wrote, iclass 19, count 2 2006.280.08:14:35.14#ibcon#about to read 3, iclass 19, count 2 2006.280.08:14:35.16#ibcon#read 3, iclass 19, count 2 2006.280.08:14:35.16#ibcon#about to read 4, iclass 19, count 2 2006.280.08:14:35.16#ibcon#read 4, iclass 19, count 2 2006.280.08:14:35.16#ibcon#about to read 5, iclass 19, count 2 2006.280.08:14:35.16#ibcon#read 5, iclass 19, count 2 2006.280.08:14:35.16#ibcon#about to read 6, iclass 19, count 2 2006.280.08:14:35.16#ibcon#read 6, iclass 19, count 2 2006.280.08:14:35.17#ibcon#end of sib2, iclass 19, count 2 2006.280.08:14:35.17#ibcon#*after write, iclass 19, count 2 2006.280.08:14:35.17#ibcon#*before return 0, iclass 19, count 2 2006.280.08:14:35.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:35.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.280.08:14:35.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.280.08:14:35.17#ibcon#ireg 7 cls_cnt 0 2006.280.08:14:35.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:35.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:35.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:35.28#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:14:35.28#ibcon#first serial, iclass 19, count 0 2006.280.08:14:35.28#ibcon#enter sib2, iclass 19, count 0 2006.280.08:14:35.28#ibcon#flushed, iclass 19, count 0 2006.280.08:14:35.28#ibcon#about to write, iclass 19, count 0 2006.280.08:14:35.29#ibcon#wrote, iclass 19, count 0 2006.280.08:14:35.29#ibcon#about to read 3, iclass 19, count 0 2006.280.08:14:35.31#ibcon#read 3, iclass 19, count 0 2006.280.08:14:35.31#ibcon#about to read 4, iclass 19, count 0 2006.280.08:14:35.31#ibcon#read 4, iclass 19, count 0 2006.280.08:14:35.31#ibcon#about to read 5, iclass 19, count 0 2006.280.08:14:35.31#ibcon#read 5, iclass 19, count 0 2006.280.08:14:35.31#ibcon#about to read 6, iclass 19, count 0 2006.280.08:14:35.31#ibcon#read 6, iclass 19, count 0 2006.280.08:14:35.31#ibcon#end of sib2, iclass 19, count 0 2006.280.08:14:35.31#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:14:35.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:14:35.31#ibcon#[27=USB\r\n] 2006.280.08:14:35.31#ibcon#*before write, iclass 19, count 0 2006.280.08:14:35.31#ibcon#enter sib2, iclass 19, count 0 2006.280.08:14:35.31#ibcon#flushed, iclass 19, count 0 2006.280.08:14:35.31#ibcon#about to write, iclass 19, count 0 2006.280.08:14:35.31#ibcon#wrote, iclass 19, count 0 2006.280.08:14:35.31#ibcon#about to read 3, iclass 19, count 0 2006.280.08:14:35.33#ibcon#read 3, iclass 19, count 0 2006.280.08:14:35.33#ibcon#about to read 4, iclass 19, count 0 2006.280.08:14:35.33#ibcon#read 4, iclass 19, count 0 2006.280.08:14:35.33#ibcon#about to read 5, iclass 19, count 0 2006.280.08:14:35.33#ibcon#read 5, iclass 19, count 0 2006.280.08:14:35.33#ibcon#about to read 6, iclass 19, count 0 2006.280.08:14:35.33#ibcon#read 6, iclass 19, count 0 2006.280.08:14:35.34#ibcon#end of sib2, iclass 19, count 0 2006.280.08:14:35.34#ibcon#*after write, iclass 19, count 0 2006.280.08:14:35.34#ibcon#*before return 0, iclass 19, count 0 2006.280.08:14:35.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:35.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.280.08:14:35.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:14:35.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:14:35.34$vc4f8/vabw=wide 2006.280.08:14:35.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.280.08:14:35.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.280.08:14:35.34#ibcon#ireg 8 cls_cnt 0 2006.280.08:14:35.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:35.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:35.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:35.34#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:14:35.34#ibcon#first serial, iclass 21, count 0 2006.280.08:14:35.34#ibcon#enter sib2, iclass 21, count 0 2006.280.08:14:35.34#ibcon#flushed, iclass 21, count 0 2006.280.08:14:35.34#ibcon#about to write, iclass 21, count 0 2006.280.08:14:35.34#ibcon#wrote, iclass 21, count 0 2006.280.08:14:35.34#ibcon#about to read 3, iclass 21, count 0 2006.280.08:14:35.35#ibcon#read 3, iclass 21, count 0 2006.280.08:14:35.36#ibcon#about to read 4, iclass 21, count 0 2006.280.08:14:35.36#ibcon#read 4, iclass 21, count 0 2006.280.08:14:35.36#ibcon#about to read 5, iclass 21, count 0 2006.280.08:14:35.36#ibcon#read 5, iclass 21, count 0 2006.280.08:14:35.36#ibcon#about to read 6, iclass 21, count 0 2006.280.08:14:35.36#ibcon#read 6, iclass 21, count 0 2006.280.08:14:35.36#ibcon#end of sib2, iclass 21, count 0 2006.280.08:14:35.36#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:14:35.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:14:35.36#ibcon#[25=BW32\r\n] 2006.280.08:14:35.36#ibcon#*before write, iclass 21, count 0 2006.280.08:14:35.36#ibcon#enter sib2, iclass 21, count 0 2006.280.08:14:35.36#ibcon#flushed, iclass 21, count 0 2006.280.08:14:35.36#ibcon#about to write, iclass 21, count 0 2006.280.08:14:35.36#ibcon#wrote, iclass 21, count 0 2006.280.08:14:35.36#ibcon#about to read 3, iclass 21, count 0 2006.280.08:14:35.39#ibcon#read 3, iclass 21, count 0 2006.280.08:14:35.39#ibcon#about to read 4, iclass 21, count 0 2006.280.08:14:35.39#ibcon#read 4, iclass 21, count 0 2006.280.08:14:35.39#ibcon#about to read 5, iclass 21, count 0 2006.280.08:14:35.39#ibcon#read 5, iclass 21, count 0 2006.280.08:14:35.39#ibcon#about to read 6, iclass 21, count 0 2006.280.08:14:35.39#ibcon#read 6, iclass 21, count 0 2006.280.08:14:35.39#ibcon#end of sib2, iclass 21, count 0 2006.280.08:14:35.39#ibcon#*after write, iclass 21, count 0 2006.280.08:14:35.39#ibcon#*before return 0, iclass 21, count 0 2006.280.08:14:35.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:35.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.280.08:14:35.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:14:35.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:14:35.39$vc4f8/vbbw=wide 2006.280.08:14:35.39#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:14:35.39#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:14:35.39#ibcon#ireg 8 cls_cnt 0 2006.280.08:14:35.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:14:35.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:14:35.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:14:35.45#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:14:35.45#ibcon#first serial, iclass 23, count 0 2006.280.08:14:35.45#ibcon#enter sib2, iclass 23, count 0 2006.280.08:14:35.45#ibcon#flushed, iclass 23, count 0 2006.280.08:14:35.45#ibcon#about to write, iclass 23, count 0 2006.280.08:14:35.46#ibcon#wrote, iclass 23, count 0 2006.280.08:14:35.46#ibcon#about to read 3, iclass 23, count 0 2006.280.08:14:35.48#ibcon#read 3, iclass 23, count 0 2006.280.08:14:35.48#ibcon#about to read 4, iclass 23, count 0 2006.280.08:14:35.48#ibcon#read 4, iclass 23, count 0 2006.280.08:14:35.48#ibcon#about to read 5, iclass 23, count 0 2006.280.08:14:35.48#ibcon#read 5, iclass 23, count 0 2006.280.08:14:35.48#ibcon#about to read 6, iclass 23, count 0 2006.280.08:14:35.48#ibcon#read 6, iclass 23, count 0 2006.280.08:14:35.48#ibcon#end of sib2, iclass 23, count 0 2006.280.08:14:35.48#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:14:35.48#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:14:35.48#ibcon#[27=BW32\r\n] 2006.280.08:14:35.48#ibcon#*before write, iclass 23, count 0 2006.280.08:14:35.48#ibcon#enter sib2, iclass 23, count 0 2006.280.08:14:35.48#ibcon#flushed, iclass 23, count 0 2006.280.08:14:35.48#ibcon#about to write, iclass 23, count 0 2006.280.08:14:35.48#ibcon#wrote, iclass 23, count 0 2006.280.08:14:35.48#ibcon#about to read 3, iclass 23, count 0 2006.280.08:14:35.51#ibcon#read 3, iclass 23, count 0 2006.280.08:14:35.52#ibcon#about to read 4, iclass 23, count 0 2006.280.08:14:35.52#ibcon#read 4, iclass 23, count 0 2006.280.08:14:35.52#ibcon#about to read 5, iclass 23, count 0 2006.280.08:14:35.52#ibcon#read 5, iclass 23, count 0 2006.280.08:14:35.52#ibcon#about to read 6, iclass 23, count 0 2006.280.08:14:35.52#ibcon#read 6, iclass 23, count 0 2006.280.08:14:35.52#ibcon#end of sib2, iclass 23, count 0 2006.280.08:14:35.52#ibcon#*after write, iclass 23, count 0 2006.280.08:14:35.52#ibcon#*before return 0, iclass 23, count 0 2006.280.08:14:35.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:14:35.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:14:35.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:14:35.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:14:35.52$4f8m12a/ifd4f 2006.280.08:14:35.52$ifd4f/lo= 2006.280.08:14:35.52$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:14:35.52$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:14:35.52$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:14:35.52$ifd4f/patch= 2006.280.08:14:35.53$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:14:35.53$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:14:35.53$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:14:35.53$4f8m12a/"form=m,16.000,1:2 2006.280.08:14:35.53$4f8m12a/"tpicd 2006.280.08:14:35.53$4f8m12a/echo=off 2006.280.08:14:35.53$4f8m12a/xlog=off 2006.280.08:14:35.53:!2006.280.08:15:00 2006.280.08:14:44.14#trakl#Source acquired 2006.280.08:14:45.15#flagr#flagr/antenna,acquired 2006.280.08:15:00.02:preob 2006.280.08:15:01.15/onsource/TRACKING 2006.280.08:15:01.15:!2006.280.08:15:10 2006.280.08:15:10.01:data_valid=on 2006.280.08:15:10.02:midob 2006.280.08:15:11.15/onsource/TRACKING 2006.280.08:15:11.15/wx/20.41,987.6,63 2006.280.08:15:11.30/cable/+6.4845E-03 2006.280.08:15:12.39/va/01,07,usb,yes,33,34 2006.280.08:15:12.39/va/02,06,usb,yes,30,32 2006.280.08:15:12.39/va/03,06,usb,yes,28,28 2006.280.08:15:12.39/va/04,06,usb,yes,31,34 2006.280.08:15:12.39/va/05,07,usb,yes,30,31 2006.280.08:15:12.39/va/06,06,usb,yes,29,28 2006.280.08:15:12.39/va/07,06,usb,yes,29,29 2006.280.08:15:12.39/va/08,06,usb,yes,31,31 2006.280.08:15:12.62/valo/01,532.99,yes,locked 2006.280.08:15:12.62/valo/02,572.99,yes,locked 2006.280.08:15:12.62/valo/03,672.99,yes,locked 2006.280.08:15:12.62/valo/04,832.99,yes,locked 2006.280.08:15:12.62/valo/05,652.99,yes,locked 2006.280.08:15:12.62/valo/06,772.99,yes,locked 2006.280.08:15:12.62/valo/07,832.99,yes,locked 2006.280.08:15:12.62/valo/08,852.99,yes,locked 2006.280.08:15:13.71/vb/01,04,usb,yes,30,29 2006.280.08:15:13.71/vb/02,05,usb,yes,28,29 2006.280.08:15:13.71/vb/03,04,usb,yes,28,32 2006.280.08:15:13.71/vb/04,04,usb,yes,29,29 2006.280.08:15:13.71/vb/05,04,usb,yes,27,31 2006.280.08:15:13.71/vb/06,04,usb,yes,28,31 2006.280.08:15:13.71/vb/07,04,usb,yes,31,31 2006.280.08:15:13.71/vb/08,04,usb,yes,28,31 2006.280.08:15:13.94/vblo/01,632.99,yes,locked 2006.280.08:15:13.94/vblo/02,640.99,yes,locked 2006.280.08:15:13.94/vblo/03,656.99,yes,locked 2006.280.08:15:13.94/vblo/04,712.99,yes,locked 2006.280.08:15:13.94/vblo/05,744.99,yes,locked 2006.280.08:15:13.94/vblo/06,752.99,yes,locked 2006.280.08:15:13.94/vblo/07,734.99,yes,locked 2006.280.08:15:13.94/vblo/08,744.99,yes,locked 2006.280.08:15:14.09/vabw/8 2006.280.08:15:14.24/vbbw/8 2006.280.08:15:14.33/xfe/off,on,12.2 2006.280.08:15:14.70/ifatt/23,28,28,28 2006.280.08:15:15.07/fmout-gps/S +3.13E-07 2006.280.08:15:15.09:!2006.280.08:16:10 2006.280.08:16:10.02:data_valid=off 2006.280.08:16:10.02:postob 2006.280.08:16:10.15/cable/+6.4832E-03 2006.280.08:16:10.15/wx/20.40,987.6,64 2006.280.08:16:11.07/fmout-gps/S +3.13E-07 2006.280.08:16:11.08:scan_name=280-0817,k06280,60 2006.280.08:16:11.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.280.08:16:12.15#flagr#flagr/antenna,new-source 2006.280.08:16:12.15:checkk5 2006.280.08:16:12.71/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:16:13.12/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:16:13.93/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:16:14.49/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:16:15.34/chk_obsdata//k5ts1/T2800815??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:16:15.82/chk_obsdata//k5ts2/T2800815??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:16:16.51/chk_obsdata//k5ts3/T2800815??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:16:17.06/chk_obsdata//k5ts4/T2800815??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:16:17.85/k5log//k5ts1_log_newline 2006.280.08:16:19.75/k5log//k5ts2_log_newline 2006.280.08:16:20.82/k5log//k5ts3_log_newline 2006.280.08:16:21.99/k5log//k5ts4_log_newline 2006.280.08:16:22.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:16:22.02:4f8m12a=2 2006.280.08:16:22.02$4f8m12a/echo=on 2006.280.08:16:22.02$4f8m12a/pcalon 2006.280.08:16:22.02$pcalon/"no phase cal control is implemented here 2006.280.08:16:22.02$4f8m12a/"tpicd=stop 2006.280.08:16:22.02$4f8m12a/vc4f8 2006.280.08:16:22.02$vc4f8/valo=1,532.99 2006.280.08:16:22.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:16:22.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:16:22.03#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:22.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:22.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:22.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:22.03#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:16:22.03#ibcon#first serial, iclass 30, count 0 2006.280.08:16:22.03#ibcon#enter sib2, iclass 30, count 0 2006.280.08:16:22.03#ibcon#flushed, iclass 30, count 0 2006.280.08:16:22.03#ibcon#about to write, iclass 30, count 0 2006.280.08:16:22.03#ibcon#wrote, iclass 30, count 0 2006.280.08:16:22.03#ibcon#about to read 3, iclass 30, count 0 2006.280.08:16:22.05#ibcon#read 3, iclass 30, count 0 2006.280.08:16:22.05#ibcon#about to read 4, iclass 30, count 0 2006.280.08:16:22.05#ibcon#read 4, iclass 30, count 0 2006.280.08:16:22.05#ibcon#about to read 5, iclass 30, count 0 2006.280.08:16:22.05#ibcon#read 5, iclass 30, count 0 2006.280.08:16:22.05#ibcon#about to read 6, iclass 30, count 0 2006.280.08:16:22.05#ibcon#read 6, iclass 30, count 0 2006.280.08:16:22.05#ibcon#end of sib2, iclass 30, count 0 2006.280.08:16:22.05#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:16:22.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:16:22.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:16:22.05#ibcon#*before write, iclass 30, count 0 2006.280.08:16:22.05#ibcon#enter sib2, iclass 30, count 0 2006.280.08:16:22.05#ibcon#flushed, iclass 30, count 0 2006.280.08:16:22.05#ibcon#about to write, iclass 30, count 0 2006.280.08:16:22.05#ibcon#wrote, iclass 30, count 0 2006.280.08:16:22.05#ibcon#about to read 3, iclass 30, count 0 2006.280.08:16:22.10#ibcon#read 3, iclass 30, count 0 2006.280.08:16:22.10#ibcon#about to read 4, iclass 30, count 0 2006.280.08:16:22.10#ibcon#read 4, iclass 30, count 0 2006.280.08:16:22.10#ibcon#about to read 5, iclass 30, count 0 2006.280.08:16:22.10#ibcon#read 5, iclass 30, count 0 2006.280.08:16:22.10#ibcon#about to read 6, iclass 30, count 0 2006.280.08:16:22.10#ibcon#read 6, iclass 30, count 0 2006.280.08:16:22.10#ibcon#end of sib2, iclass 30, count 0 2006.280.08:16:22.10#ibcon#*after write, iclass 30, count 0 2006.280.08:16:22.10#ibcon#*before return 0, iclass 30, count 0 2006.280.08:16:22.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:22.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:22.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:16:22.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:16:22.10$vc4f8/va=1,7 2006.280.08:16:22.10#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:16:22.10#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:16:22.11#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:22.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:22.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:22.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:22.11#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:16:22.11#ibcon#first serial, iclass 32, count 2 2006.280.08:16:22.11#ibcon#enter sib2, iclass 32, count 2 2006.280.08:16:22.11#ibcon#flushed, iclass 32, count 2 2006.280.08:16:22.11#ibcon#about to write, iclass 32, count 2 2006.280.08:16:22.11#ibcon#wrote, iclass 32, count 2 2006.280.08:16:22.11#ibcon#about to read 3, iclass 32, count 2 2006.280.08:16:22.12#ibcon#read 3, iclass 32, count 2 2006.280.08:16:22.12#ibcon#about to read 4, iclass 32, count 2 2006.280.08:16:22.12#ibcon#read 4, iclass 32, count 2 2006.280.08:16:22.12#ibcon#about to read 5, iclass 32, count 2 2006.280.08:16:22.12#ibcon#read 5, iclass 32, count 2 2006.280.08:16:22.12#ibcon#about to read 6, iclass 32, count 2 2006.280.08:16:22.12#ibcon#read 6, iclass 32, count 2 2006.280.08:16:22.12#ibcon#end of sib2, iclass 32, count 2 2006.280.08:16:22.12#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:16:22.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:16:22.12#ibcon#[25=AT01-07\r\n] 2006.280.08:16:22.12#ibcon#*before write, iclass 32, count 2 2006.280.08:16:22.12#ibcon#enter sib2, iclass 32, count 2 2006.280.08:16:22.12#ibcon#flushed, iclass 32, count 2 2006.280.08:16:22.12#ibcon#about to write, iclass 32, count 2 2006.280.08:16:22.12#ibcon#wrote, iclass 32, count 2 2006.280.08:16:22.12#ibcon#about to read 3, iclass 32, count 2 2006.280.08:16:22.15#ibcon#read 3, iclass 32, count 2 2006.280.08:16:22.15#ibcon#about to read 4, iclass 32, count 2 2006.280.08:16:22.15#ibcon#read 4, iclass 32, count 2 2006.280.08:16:22.15#ibcon#about to read 5, iclass 32, count 2 2006.280.08:16:22.15#ibcon#read 5, iclass 32, count 2 2006.280.08:16:22.15#ibcon#about to read 6, iclass 32, count 2 2006.280.08:16:22.15#ibcon#read 6, iclass 32, count 2 2006.280.08:16:22.15#ibcon#end of sib2, iclass 32, count 2 2006.280.08:16:22.15#ibcon#*after write, iclass 32, count 2 2006.280.08:16:22.15#ibcon#*before return 0, iclass 32, count 2 2006.280.08:16:22.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:22.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:22.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:16:22.15#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:22.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:22.28#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:22.28#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:22.28#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:16:22.28#ibcon#first serial, iclass 32, count 0 2006.280.08:16:22.28#ibcon#enter sib2, iclass 32, count 0 2006.280.08:16:22.28#ibcon#flushed, iclass 32, count 0 2006.280.08:16:22.28#ibcon#about to write, iclass 32, count 0 2006.280.08:16:22.28#ibcon#wrote, iclass 32, count 0 2006.280.08:16:22.28#ibcon#about to read 3, iclass 32, count 0 2006.280.08:16:22.29#ibcon#read 3, iclass 32, count 0 2006.280.08:16:22.29#ibcon#about to read 4, iclass 32, count 0 2006.280.08:16:22.29#ibcon#read 4, iclass 32, count 0 2006.280.08:16:22.29#ibcon#about to read 5, iclass 32, count 0 2006.280.08:16:22.29#ibcon#read 5, iclass 32, count 0 2006.280.08:16:22.29#ibcon#about to read 6, iclass 32, count 0 2006.280.08:16:22.29#ibcon#read 6, iclass 32, count 0 2006.280.08:16:22.29#ibcon#end of sib2, iclass 32, count 0 2006.280.08:16:22.29#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:16:22.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:16:22.29#ibcon#[25=USB\r\n] 2006.280.08:16:22.29#ibcon#*before write, iclass 32, count 0 2006.280.08:16:22.29#ibcon#enter sib2, iclass 32, count 0 2006.280.08:16:22.29#ibcon#flushed, iclass 32, count 0 2006.280.08:16:22.29#ibcon#about to write, iclass 32, count 0 2006.280.08:16:22.29#ibcon#wrote, iclass 32, count 0 2006.280.08:16:22.29#ibcon#about to read 3, iclass 32, count 0 2006.280.08:16:22.32#ibcon#read 3, iclass 32, count 0 2006.280.08:16:22.32#ibcon#about to read 4, iclass 32, count 0 2006.280.08:16:22.32#ibcon#read 4, iclass 32, count 0 2006.280.08:16:22.32#ibcon#about to read 5, iclass 32, count 0 2006.280.08:16:22.32#ibcon#read 5, iclass 32, count 0 2006.280.08:16:22.32#ibcon#about to read 6, iclass 32, count 0 2006.280.08:16:22.32#ibcon#read 6, iclass 32, count 0 2006.280.08:16:22.32#ibcon#end of sib2, iclass 32, count 0 2006.280.08:16:22.32#ibcon#*after write, iclass 32, count 0 2006.280.08:16:22.32#ibcon#*before return 0, iclass 32, count 0 2006.280.08:16:22.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:22.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:22.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:16:22.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:16:22.33$vc4f8/valo=2,572.99 2006.280.08:16:22.33#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:16:22.33#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:16:22.33#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:22.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:16:22.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:16:22.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:16:22.33#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:16:22.33#ibcon#first serial, iclass 34, count 0 2006.280.08:16:22.33#ibcon#enter sib2, iclass 34, count 0 2006.280.08:16:22.33#ibcon#flushed, iclass 34, count 0 2006.280.08:16:22.33#ibcon#about to write, iclass 34, count 0 2006.280.08:16:22.33#ibcon#wrote, iclass 34, count 0 2006.280.08:16:22.33#ibcon#about to read 3, iclass 34, count 0 2006.280.08:16:22.34#ibcon#read 3, iclass 34, count 0 2006.280.08:16:22.34#ibcon#about to read 4, iclass 34, count 0 2006.280.08:16:22.34#ibcon#read 4, iclass 34, count 0 2006.280.08:16:22.34#ibcon#about to read 5, iclass 34, count 0 2006.280.08:16:22.34#ibcon#read 5, iclass 34, count 0 2006.280.08:16:22.34#ibcon#about to read 6, iclass 34, count 0 2006.280.08:16:22.34#ibcon#read 6, iclass 34, count 0 2006.280.08:16:22.34#ibcon#end of sib2, iclass 34, count 0 2006.280.08:16:22.34#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:16:22.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:16:22.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:16:22.34#ibcon#*before write, iclass 34, count 0 2006.280.08:16:22.34#ibcon#enter sib2, iclass 34, count 0 2006.280.08:16:22.34#ibcon#flushed, iclass 34, count 0 2006.280.08:16:22.34#ibcon#about to write, iclass 34, count 0 2006.280.08:16:22.34#ibcon#wrote, iclass 34, count 0 2006.280.08:16:22.34#ibcon#about to read 3, iclass 34, count 0 2006.280.08:16:22.39#ibcon#read 3, iclass 34, count 0 2006.280.08:16:22.39#ibcon#about to read 4, iclass 34, count 0 2006.280.08:16:22.39#ibcon#read 4, iclass 34, count 0 2006.280.08:16:22.39#ibcon#about to read 5, iclass 34, count 0 2006.280.08:16:22.39#ibcon#read 5, iclass 34, count 0 2006.280.08:16:22.39#ibcon#about to read 6, iclass 34, count 0 2006.280.08:16:22.39#ibcon#read 6, iclass 34, count 0 2006.280.08:16:22.39#ibcon#end of sib2, iclass 34, count 0 2006.280.08:16:22.39#ibcon#*after write, iclass 34, count 0 2006.280.08:16:22.39#ibcon#*before return 0, iclass 34, count 0 2006.280.08:16:22.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:16:22.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:16:22.39#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:16:22.39#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:16:22.39$vc4f8/va=2,6 2006.280.08:16:22.39#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:16:22.39#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:16:22.39#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:22.39#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:16:22.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:16:22.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:16:22.43#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:16:22.43#ibcon#first serial, iclass 36, count 2 2006.280.08:16:22.43#ibcon#enter sib2, iclass 36, count 2 2006.280.08:16:22.43#ibcon#flushed, iclass 36, count 2 2006.280.08:16:22.43#ibcon#about to write, iclass 36, count 2 2006.280.08:16:22.43#ibcon#wrote, iclass 36, count 2 2006.280.08:16:22.43#ibcon#about to read 3, iclass 36, count 2 2006.280.08:16:22.45#ibcon#read 3, iclass 36, count 2 2006.280.08:16:22.45#ibcon#about to read 4, iclass 36, count 2 2006.280.08:16:22.45#ibcon#read 4, iclass 36, count 2 2006.280.08:16:22.45#ibcon#about to read 5, iclass 36, count 2 2006.280.08:16:22.45#ibcon#read 5, iclass 36, count 2 2006.280.08:16:22.45#ibcon#about to read 6, iclass 36, count 2 2006.280.08:16:22.45#ibcon#read 6, iclass 36, count 2 2006.280.08:16:22.45#ibcon#end of sib2, iclass 36, count 2 2006.280.08:16:22.45#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:16:22.45#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:16:22.45#ibcon#[25=AT02-06\r\n] 2006.280.08:16:22.45#ibcon#*before write, iclass 36, count 2 2006.280.08:16:22.45#ibcon#enter sib2, iclass 36, count 2 2006.280.08:16:22.45#ibcon#flushed, iclass 36, count 2 2006.280.08:16:22.45#ibcon#about to write, iclass 36, count 2 2006.280.08:16:22.45#ibcon#wrote, iclass 36, count 2 2006.280.08:16:22.45#ibcon#about to read 3, iclass 36, count 2 2006.280.08:16:22.49#ibcon#read 3, iclass 36, count 2 2006.280.08:16:22.49#ibcon#about to read 4, iclass 36, count 2 2006.280.08:16:22.49#ibcon#read 4, iclass 36, count 2 2006.280.08:16:22.49#ibcon#about to read 5, iclass 36, count 2 2006.280.08:16:22.49#ibcon#read 5, iclass 36, count 2 2006.280.08:16:22.49#ibcon#about to read 6, iclass 36, count 2 2006.280.08:16:22.49#ibcon#read 6, iclass 36, count 2 2006.280.08:16:22.49#ibcon#end of sib2, iclass 36, count 2 2006.280.08:16:22.49#ibcon#*after write, iclass 36, count 2 2006.280.08:16:22.49#ibcon#*before return 0, iclass 36, count 2 2006.280.08:16:22.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:16:22.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:16:22.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:16:22.49#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:22.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:16:22.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:16:22.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:16:22.61#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:16:22.61#ibcon#first serial, iclass 36, count 0 2006.280.08:16:22.61#ibcon#enter sib2, iclass 36, count 0 2006.280.08:16:22.61#ibcon#flushed, iclass 36, count 0 2006.280.08:16:22.61#ibcon#about to write, iclass 36, count 0 2006.280.08:16:22.61#ibcon#wrote, iclass 36, count 0 2006.280.08:16:22.61#ibcon#about to read 3, iclass 36, count 0 2006.280.08:16:22.63#ibcon#read 3, iclass 36, count 0 2006.280.08:16:22.63#ibcon#about to read 4, iclass 36, count 0 2006.280.08:16:22.63#ibcon#read 4, iclass 36, count 0 2006.280.08:16:22.63#ibcon#about to read 5, iclass 36, count 0 2006.280.08:16:22.63#ibcon#read 5, iclass 36, count 0 2006.280.08:16:22.63#ibcon#about to read 6, iclass 36, count 0 2006.280.08:16:22.63#ibcon#read 6, iclass 36, count 0 2006.280.08:16:22.63#ibcon#end of sib2, iclass 36, count 0 2006.280.08:16:22.63#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:16:22.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:16:22.63#ibcon#[25=USB\r\n] 2006.280.08:16:22.63#ibcon#*before write, iclass 36, count 0 2006.280.08:16:22.63#ibcon#enter sib2, iclass 36, count 0 2006.280.08:16:22.63#ibcon#flushed, iclass 36, count 0 2006.280.08:16:22.63#ibcon#about to write, iclass 36, count 0 2006.280.08:16:22.63#ibcon#wrote, iclass 36, count 0 2006.280.08:16:22.63#ibcon#about to read 3, iclass 36, count 0 2006.280.08:16:22.65#ibcon#read 3, iclass 36, count 0 2006.280.08:16:22.65#ibcon#about to read 4, iclass 36, count 0 2006.280.08:16:22.65#ibcon#read 4, iclass 36, count 0 2006.280.08:16:22.65#ibcon#about to read 5, iclass 36, count 0 2006.280.08:16:22.65#ibcon#read 5, iclass 36, count 0 2006.280.08:16:22.65#ibcon#about to read 6, iclass 36, count 0 2006.280.08:16:22.65#ibcon#read 6, iclass 36, count 0 2006.280.08:16:22.65#ibcon#end of sib2, iclass 36, count 0 2006.280.08:16:22.65#ibcon#*after write, iclass 36, count 0 2006.280.08:16:22.65#ibcon#*before return 0, iclass 36, count 0 2006.280.08:16:22.65#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:16:22.65#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:16:22.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:16:22.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:16:22.65$vc4f8/valo=3,672.99 2006.280.08:16:22.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:16:22.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:16:22.66#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:22.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:16:22.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:16:22.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:16:22.66#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:16:22.66#ibcon#first serial, iclass 38, count 0 2006.280.08:16:22.66#ibcon#enter sib2, iclass 38, count 0 2006.280.08:16:22.66#ibcon#flushed, iclass 38, count 0 2006.280.08:16:22.66#ibcon#about to write, iclass 38, count 0 2006.280.08:16:22.66#ibcon#wrote, iclass 38, count 0 2006.280.08:16:22.66#ibcon#about to read 3, iclass 38, count 0 2006.280.08:16:22.67#ibcon#read 3, iclass 38, count 0 2006.280.08:16:22.67#ibcon#about to read 4, iclass 38, count 0 2006.280.08:16:22.67#ibcon#read 4, iclass 38, count 0 2006.280.08:16:22.67#ibcon#about to read 5, iclass 38, count 0 2006.280.08:16:22.67#ibcon#read 5, iclass 38, count 0 2006.280.08:16:22.67#ibcon#about to read 6, iclass 38, count 0 2006.280.08:16:22.67#ibcon#read 6, iclass 38, count 0 2006.280.08:16:22.67#ibcon#end of sib2, iclass 38, count 0 2006.280.08:16:22.67#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:16:22.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:16:22.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:16:22.67#ibcon#*before write, iclass 38, count 0 2006.280.08:16:22.67#ibcon#enter sib2, iclass 38, count 0 2006.280.08:16:22.67#ibcon#flushed, iclass 38, count 0 2006.280.08:16:22.67#ibcon#about to write, iclass 38, count 0 2006.280.08:16:22.67#ibcon#wrote, iclass 38, count 0 2006.280.08:16:22.67#ibcon#about to read 3, iclass 38, count 0 2006.280.08:16:22.72#ibcon#read 3, iclass 38, count 0 2006.280.08:16:22.72#ibcon#about to read 4, iclass 38, count 0 2006.280.08:16:22.72#ibcon#read 4, iclass 38, count 0 2006.280.08:16:22.72#ibcon#about to read 5, iclass 38, count 0 2006.280.08:16:22.72#ibcon#read 5, iclass 38, count 0 2006.280.08:16:22.72#ibcon#about to read 6, iclass 38, count 0 2006.280.08:16:22.72#ibcon#read 6, iclass 38, count 0 2006.280.08:16:22.72#ibcon#end of sib2, iclass 38, count 0 2006.280.08:16:22.72#ibcon#*after write, iclass 38, count 0 2006.280.08:16:22.72#ibcon#*before return 0, iclass 38, count 0 2006.280.08:16:22.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:16:22.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:16:22.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:16:22.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:16:22.72$vc4f8/va=3,6 2006.280.08:16:22.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:16:22.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:16:22.72#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:22.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:16:22.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:16:22.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:16:22.76#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:16:22.76#ibcon#first serial, iclass 40, count 2 2006.280.08:16:22.76#ibcon#enter sib2, iclass 40, count 2 2006.280.08:16:22.76#ibcon#flushed, iclass 40, count 2 2006.280.08:16:22.76#ibcon#about to write, iclass 40, count 2 2006.280.08:16:22.76#ibcon#wrote, iclass 40, count 2 2006.280.08:16:22.76#ibcon#about to read 3, iclass 40, count 2 2006.280.08:16:22.78#ibcon#read 3, iclass 40, count 2 2006.280.08:16:22.78#ibcon#about to read 4, iclass 40, count 2 2006.280.08:16:22.79#ibcon#read 4, iclass 40, count 2 2006.280.08:16:22.79#ibcon#about to read 5, iclass 40, count 2 2006.280.08:16:22.79#ibcon#read 5, iclass 40, count 2 2006.280.08:16:22.79#ibcon#about to read 6, iclass 40, count 2 2006.280.08:16:22.79#ibcon#read 6, iclass 40, count 2 2006.280.08:16:22.79#ibcon#end of sib2, iclass 40, count 2 2006.280.08:16:22.79#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:16:22.79#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:16:22.79#ibcon#[25=AT03-06\r\n] 2006.280.08:16:22.79#ibcon#*before write, iclass 40, count 2 2006.280.08:16:22.79#ibcon#enter sib2, iclass 40, count 2 2006.280.08:16:22.79#ibcon#flushed, iclass 40, count 2 2006.280.08:16:22.79#ibcon#about to write, iclass 40, count 2 2006.280.08:16:22.79#ibcon#wrote, iclass 40, count 2 2006.280.08:16:22.79#ibcon#about to read 3, iclass 40, count 2 2006.280.08:16:22.81#ibcon#read 3, iclass 40, count 2 2006.280.08:16:22.81#ibcon#about to read 4, iclass 40, count 2 2006.280.08:16:22.81#ibcon#read 4, iclass 40, count 2 2006.280.08:16:22.81#ibcon#about to read 5, iclass 40, count 2 2006.280.08:16:22.81#ibcon#read 5, iclass 40, count 2 2006.280.08:16:22.81#ibcon#about to read 6, iclass 40, count 2 2006.280.08:16:22.81#ibcon#read 6, iclass 40, count 2 2006.280.08:16:22.81#ibcon#end of sib2, iclass 40, count 2 2006.280.08:16:22.81#ibcon#*after write, iclass 40, count 2 2006.280.08:16:22.81#ibcon#*before return 0, iclass 40, count 2 2006.280.08:16:22.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:16:22.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:16:22.81#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:16:22.81#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:22.81#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:16:22.93#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:16:22.93#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:16:22.93#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:16:22.93#ibcon#first serial, iclass 40, count 0 2006.280.08:16:22.93#ibcon#enter sib2, iclass 40, count 0 2006.280.08:16:22.93#ibcon#flushed, iclass 40, count 0 2006.280.08:16:22.93#ibcon#about to write, iclass 40, count 0 2006.280.08:16:22.93#ibcon#wrote, iclass 40, count 0 2006.280.08:16:22.93#ibcon#about to read 3, iclass 40, count 0 2006.280.08:16:22.95#ibcon#read 3, iclass 40, count 0 2006.280.08:16:22.95#ibcon#about to read 4, iclass 40, count 0 2006.280.08:16:22.95#ibcon#read 4, iclass 40, count 0 2006.280.08:16:22.95#ibcon#about to read 5, iclass 40, count 0 2006.280.08:16:22.95#ibcon#read 5, iclass 40, count 0 2006.280.08:16:22.95#ibcon#about to read 6, iclass 40, count 0 2006.280.08:16:22.95#ibcon#read 6, iclass 40, count 0 2006.280.08:16:22.95#ibcon#end of sib2, iclass 40, count 0 2006.280.08:16:22.95#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:16:22.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:16:22.95#ibcon#[25=USB\r\n] 2006.280.08:16:22.95#ibcon#*before write, iclass 40, count 0 2006.280.08:16:22.95#ibcon#enter sib2, iclass 40, count 0 2006.280.08:16:22.95#ibcon#flushed, iclass 40, count 0 2006.280.08:16:22.95#ibcon#about to write, iclass 40, count 0 2006.280.08:16:22.95#ibcon#wrote, iclass 40, count 0 2006.280.08:16:22.95#ibcon#about to read 3, iclass 40, count 0 2006.280.08:16:22.98#ibcon#read 3, iclass 40, count 0 2006.280.08:16:22.98#ibcon#about to read 4, iclass 40, count 0 2006.280.08:16:22.98#ibcon#read 4, iclass 40, count 0 2006.280.08:16:22.98#ibcon#about to read 5, iclass 40, count 0 2006.280.08:16:22.98#ibcon#read 5, iclass 40, count 0 2006.280.08:16:22.98#ibcon#about to read 6, iclass 40, count 0 2006.280.08:16:22.98#ibcon#read 6, iclass 40, count 0 2006.280.08:16:22.98#ibcon#end of sib2, iclass 40, count 0 2006.280.08:16:22.98#ibcon#*after write, iclass 40, count 0 2006.280.08:16:22.98#ibcon#*before return 0, iclass 40, count 0 2006.280.08:16:22.98#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:16:22.98#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:16:22.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:16:22.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:16:22.98$vc4f8/valo=4,832.99 2006.280.08:16:22.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:16:22.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:16:22.99#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:22.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:22.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:22.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:22.99#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:16:22.99#ibcon#first serial, iclass 4, count 0 2006.280.08:16:22.99#ibcon#enter sib2, iclass 4, count 0 2006.280.08:16:22.99#ibcon#flushed, iclass 4, count 0 2006.280.08:16:22.99#ibcon#about to write, iclass 4, count 0 2006.280.08:16:22.99#ibcon#wrote, iclass 4, count 0 2006.280.08:16:22.99#ibcon#about to read 3, iclass 4, count 0 2006.280.08:16:23.00#ibcon#read 3, iclass 4, count 0 2006.280.08:16:23.00#ibcon#about to read 4, iclass 4, count 0 2006.280.08:16:23.00#ibcon#read 4, iclass 4, count 0 2006.280.08:16:23.00#ibcon#about to read 5, iclass 4, count 0 2006.280.08:16:23.00#ibcon#read 5, iclass 4, count 0 2006.280.08:16:23.00#ibcon#about to read 6, iclass 4, count 0 2006.280.08:16:23.00#ibcon#read 6, iclass 4, count 0 2006.280.08:16:23.00#ibcon#end of sib2, iclass 4, count 0 2006.280.08:16:23.00#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:16:23.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:16:23.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:16:23.00#ibcon#*before write, iclass 4, count 0 2006.280.08:16:23.00#ibcon#enter sib2, iclass 4, count 0 2006.280.08:16:23.00#ibcon#flushed, iclass 4, count 0 2006.280.08:16:23.00#ibcon#about to write, iclass 4, count 0 2006.280.08:16:23.00#ibcon#wrote, iclass 4, count 0 2006.280.08:16:23.00#ibcon#about to read 3, iclass 4, count 0 2006.280.08:16:23.04#ibcon#read 3, iclass 4, count 0 2006.280.08:16:23.04#ibcon#about to read 4, iclass 4, count 0 2006.280.08:16:23.04#ibcon#read 4, iclass 4, count 0 2006.280.08:16:23.04#ibcon#about to read 5, iclass 4, count 0 2006.280.08:16:23.04#ibcon#read 5, iclass 4, count 0 2006.280.08:16:23.04#ibcon#about to read 6, iclass 4, count 0 2006.280.08:16:23.04#ibcon#read 6, iclass 4, count 0 2006.280.08:16:23.04#ibcon#end of sib2, iclass 4, count 0 2006.280.08:16:23.04#ibcon#*after write, iclass 4, count 0 2006.280.08:16:23.04#ibcon#*before return 0, iclass 4, count 0 2006.280.08:16:23.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:23.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:23.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:16:23.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:16:23.05$vc4f8/va=4,6 2006.280.08:16:23.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:16:23.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:16:23.05#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:23.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:23.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:23.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:23.10#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:16:23.10#ibcon#first serial, iclass 6, count 2 2006.280.08:16:23.10#ibcon#enter sib2, iclass 6, count 2 2006.280.08:16:23.10#ibcon#flushed, iclass 6, count 2 2006.280.08:16:23.10#ibcon#about to write, iclass 6, count 2 2006.280.08:16:23.10#ibcon#wrote, iclass 6, count 2 2006.280.08:16:23.10#ibcon#about to read 3, iclass 6, count 2 2006.280.08:16:23.12#ibcon#read 3, iclass 6, count 2 2006.280.08:16:23.12#ibcon#about to read 4, iclass 6, count 2 2006.280.08:16:23.12#ibcon#read 4, iclass 6, count 2 2006.280.08:16:23.12#ibcon#about to read 5, iclass 6, count 2 2006.280.08:16:23.12#ibcon#read 5, iclass 6, count 2 2006.280.08:16:23.12#ibcon#about to read 6, iclass 6, count 2 2006.280.08:16:23.12#ibcon#read 6, iclass 6, count 2 2006.280.08:16:23.12#ibcon#end of sib2, iclass 6, count 2 2006.280.08:16:23.12#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:16:23.12#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:16:23.12#ibcon#[25=AT04-06\r\n] 2006.280.08:16:23.12#ibcon#*before write, iclass 6, count 2 2006.280.08:16:23.12#ibcon#enter sib2, iclass 6, count 2 2006.280.08:16:23.12#ibcon#flushed, iclass 6, count 2 2006.280.08:16:23.12#ibcon#about to write, iclass 6, count 2 2006.280.08:16:23.12#ibcon#wrote, iclass 6, count 2 2006.280.08:16:23.12#ibcon#about to read 3, iclass 6, count 2 2006.280.08:16:23.15#ibcon#read 3, iclass 6, count 2 2006.280.08:16:23.15#ibcon#about to read 4, iclass 6, count 2 2006.280.08:16:23.15#ibcon#read 4, iclass 6, count 2 2006.280.08:16:23.15#ibcon#about to read 5, iclass 6, count 2 2006.280.08:16:23.15#ibcon#read 5, iclass 6, count 2 2006.280.08:16:23.15#ibcon#about to read 6, iclass 6, count 2 2006.280.08:16:23.15#ibcon#read 6, iclass 6, count 2 2006.280.08:16:23.15#ibcon#end of sib2, iclass 6, count 2 2006.280.08:16:23.15#ibcon#*after write, iclass 6, count 2 2006.280.08:16:23.15#ibcon#*before return 0, iclass 6, count 2 2006.280.08:16:23.15#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:23.15#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:23.15#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:16:23.15#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:23.15#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:23.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:23.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:23.26#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:16:23.26#ibcon#first serial, iclass 6, count 0 2006.280.08:16:23.26#ibcon#enter sib2, iclass 6, count 0 2006.280.08:16:23.26#ibcon#flushed, iclass 6, count 0 2006.280.08:16:23.26#ibcon#about to write, iclass 6, count 0 2006.280.08:16:23.26#ibcon#wrote, iclass 6, count 0 2006.280.08:16:23.26#ibcon#about to read 3, iclass 6, count 0 2006.280.08:16:23.28#ibcon#read 3, iclass 6, count 0 2006.280.08:16:23.28#ibcon#about to read 4, iclass 6, count 0 2006.280.08:16:23.28#ibcon#read 4, iclass 6, count 0 2006.280.08:16:23.28#ibcon#about to read 5, iclass 6, count 0 2006.280.08:16:23.28#ibcon#read 5, iclass 6, count 0 2006.280.08:16:23.28#ibcon#about to read 6, iclass 6, count 0 2006.280.08:16:23.28#ibcon#read 6, iclass 6, count 0 2006.280.08:16:23.28#ibcon#end of sib2, iclass 6, count 0 2006.280.08:16:23.28#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:16:23.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:16:23.28#ibcon#[25=USB\r\n] 2006.280.08:16:23.28#ibcon#*before write, iclass 6, count 0 2006.280.08:16:23.28#ibcon#enter sib2, iclass 6, count 0 2006.280.08:16:23.28#ibcon#flushed, iclass 6, count 0 2006.280.08:16:23.28#ibcon#about to write, iclass 6, count 0 2006.280.08:16:23.28#ibcon#wrote, iclass 6, count 0 2006.280.08:16:23.28#ibcon#about to read 3, iclass 6, count 0 2006.280.08:16:23.31#ibcon#read 3, iclass 6, count 0 2006.280.08:16:23.31#ibcon#about to read 4, iclass 6, count 0 2006.280.08:16:23.31#ibcon#read 4, iclass 6, count 0 2006.280.08:16:23.31#ibcon#about to read 5, iclass 6, count 0 2006.280.08:16:23.31#ibcon#read 5, iclass 6, count 0 2006.280.08:16:23.31#ibcon#about to read 6, iclass 6, count 0 2006.280.08:16:23.31#ibcon#read 6, iclass 6, count 0 2006.280.08:16:23.31#ibcon#end of sib2, iclass 6, count 0 2006.280.08:16:23.31#ibcon#*after write, iclass 6, count 0 2006.280.08:16:23.31#ibcon#*before return 0, iclass 6, count 0 2006.280.08:16:23.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:23.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:23.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:16:23.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:16:23.31$vc4f8/valo=5,652.99 2006.280.08:16:23.32#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:16:23.32#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:16:23.32#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:23.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:23.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:23.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:23.32#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:16:23.32#ibcon#first serial, iclass 10, count 0 2006.280.08:16:23.32#ibcon#enter sib2, iclass 10, count 0 2006.280.08:16:23.32#ibcon#flushed, iclass 10, count 0 2006.280.08:16:23.32#ibcon#about to write, iclass 10, count 0 2006.280.08:16:23.32#ibcon#wrote, iclass 10, count 0 2006.280.08:16:23.32#ibcon#about to read 3, iclass 10, count 0 2006.280.08:16:23.33#ibcon#read 3, iclass 10, count 0 2006.280.08:16:23.33#ibcon#about to read 4, iclass 10, count 0 2006.280.08:16:23.33#ibcon#read 4, iclass 10, count 0 2006.280.08:16:23.33#ibcon#about to read 5, iclass 10, count 0 2006.280.08:16:23.33#ibcon#read 5, iclass 10, count 0 2006.280.08:16:23.33#ibcon#about to read 6, iclass 10, count 0 2006.280.08:16:23.33#ibcon#read 6, iclass 10, count 0 2006.280.08:16:23.33#ibcon#end of sib2, iclass 10, count 0 2006.280.08:16:23.33#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:16:23.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:16:23.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:16:23.36#ibcon#*before write, iclass 10, count 0 2006.280.08:16:23.36#ibcon#enter sib2, iclass 10, count 0 2006.280.08:16:23.36#ibcon#flushed, iclass 10, count 0 2006.280.08:16:23.36#ibcon#about to write, iclass 10, count 0 2006.280.08:16:23.36#ibcon#wrote, iclass 10, count 0 2006.280.08:16:23.36#ibcon#about to read 3, iclass 10, count 0 2006.280.08:16:23.40#ibcon#read 3, iclass 10, count 0 2006.280.08:16:23.40#ibcon#about to read 4, iclass 10, count 0 2006.280.08:16:23.40#ibcon#read 4, iclass 10, count 0 2006.280.08:16:23.40#ibcon#about to read 5, iclass 10, count 0 2006.280.08:16:23.40#ibcon#read 5, iclass 10, count 0 2006.280.08:16:23.40#ibcon#about to read 6, iclass 10, count 0 2006.280.08:16:23.40#ibcon#read 6, iclass 10, count 0 2006.280.08:16:23.40#ibcon#end of sib2, iclass 10, count 0 2006.280.08:16:23.40#ibcon#*after write, iclass 10, count 0 2006.280.08:16:23.40#ibcon#*before return 0, iclass 10, count 0 2006.280.08:16:23.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:23.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:23.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:16:23.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:16:23.40$vc4f8/va=5,7 2006.280.08:16:23.41#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:16:23.41#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:16:23.41#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:23.41#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:23.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:23.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:23.42#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:16:23.42#ibcon#first serial, iclass 12, count 2 2006.280.08:16:23.42#ibcon#enter sib2, iclass 12, count 2 2006.280.08:16:23.42#ibcon#flushed, iclass 12, count 2 2006.280.08:16:23.42#ibcon#about to write, iclass 12, count 2 2006.280.08:16:23.42#ibcon#wrote, iclass 12, count 2 2006.280.08:16:23.42#ibcon#about to read 3, iclass 12, count 2 2006.280.08:16:23.44#ibcon#read 3, iclass 12, count 2 2006.280.08:16:23.44#ibcon#about to read 4, iclass 12, count 2 2006.280.08:16:23.44#ibcon#read 4, iclass 12, count 2 2006.280.08:16:23.44#ibcon#about to read 5, iclass 12, count 2 2006.280.08:16:23.44#ibcon#read 5, iclass 12, count 2 2006.280.08:16:23.44#ibcon#about to read 6, iclass 12, count 2 2006.280.08:16:23.44#ibcon#read 6, iclass 12, count 2 2006.280.08:16:23.44#ibcon#end of sib2, iclass 12, count 2 2006.280.08:16:23.44#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:16:23.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:16:23.44#ibcon#[25=AT05-07\r\n] 2006.280.08:16:23.44#ibcon#*before write, iclass 12, count 2 2006.280.08:16:23.44#ibcon#enter sib2, iclass 12, count 2 2006.280.08:16:23.44#ibcon#flushed, iclass 12, count 2 2006.280.08:16:23.44#ibcon#about to write, iclass 12, count 2 2006.280.08:16:23.44#ibcon#wrote, iclass 12, count 2 2006.280.08:16:23.44#ibcon#about to read 3, iclass 12, count 2 2006.280.08:16:23.47#ibcon#read 3, iclass 12, count 2 2006.280.08:16:23.47#ibcon#about to read 4, iclass 12, count 2 2006.280.08:16:23.47#ibcon#read 4, iclass 12, count 2 2006.280.08:16:23.47#ibcon#about to read 5, iclass 12, count 2 2006.280.08:16:23.47#ibcon#read 5, iclass 12, count 2 2006.280.08:16:23.47#ibcon#about to read 6, iclass 12, count 2 2006.280.08:16:23.47#ibcon#read 6, iclass 12, count 2 2006.280.08:16:23.47#ibcon#end of sib2, iclass 12, count 2 2006.280.08:16:23.47#ibcon#*after write, iclass 12, count 2 2006.280.08:16:23.47#ibcon#*before return 0, iclass 12, count 2 2006.280.08:16:23.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:23.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:23.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:16:23.47#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:23.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:23.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:23.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:23.59#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:16:23.59#ibcon#first serial, iclass 12, count 0 2006.280.08:16:23.59#ibcon#enter sib2, iclass 12, count 0 2006.280.08:16:23.59#ibcon#flushed, iclass 12, count 0 2006.280.08:16:23.59#ibcon#about to write, iclass 12, count 0 2006.280.08:16:23.59#ibcon#wrote, iclass 12, count 0 2006.280.08:16:23.59#ibcon#about to read 3, iclass 12, count 0 2006.280.08:16:23.61#ibcon#read 3, iclass 12, count 0 2006.280.08:16:23.61#ibcon#about to read 4, iclass 12, count 0 2006.280.08:16:23.61#ibcon#read 4, iclass 12, count 0 2006.280.08:16:23.61#ibcon#about to read 5, iclass 12, count 0 2006.280.08:16:23.61#ibcon#read 5, iclass 12, count 0 2006.280.08:16:23.61#ibcon#about to read 6, iclass 12, count 0 2006.280.08:16:23.61#ibcon#read 6, iclass 12, count 0 2006.280.08:16:23.61#ibcon#end of sib2, iclass 12, count 0 2006.280.08:16:23.61#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:16:23.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:16:23.61#ibcon#[25=USB\r\n] 2006.280.08:16:23.61#ibcon#*before write, iclass 12, count 0 2006.280.08:16:23.61#ibcon#enter sib2, iclass 12, count 0 2006.280.08:16:23.61#ibcon#flushed, iclass 12, count 0 2006.280.08:16:23.61#ibcon#about to write, iclass 12, count 0 2006.280.08:16:23.61#ibcon#wrote, iclass 12, count 0 2006.280.08:16:23.61#ibcon#about to read 3, iclass 12, count 0 2006.280.08:16:23.64#ibcon#read 3, iclass 12, count 0 2006.280.08:16:23.64#ibcon#about to read 4, iclass 12, count 0 2006.280.08:16:23.64#ibcon#read 4, iclass 12, count 0 2006.280.08:16:23.64#ibcon#about to read 5, iclass 12, count 0 2006.280.08:16:23.64#ibcon#read 5, iclass 12, count 0 2006.280.08:16:23.64#ibcon#about to read 6, iclass 12, count 0 2006.280.08:16:23.64#ibcon#read 6, iclass 12, count 0 2006.280.08:16:23.64#ibcon#end of sib2, iclass 12, count 0 2006.280.08:16:23.64#ibcon#*after write, iclass 12, count 0 2006.280.08:16:23.64#ibcon#*before return 0, iclass 12, count 0 2006.280.08:16:23.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:23.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:23.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:16:23.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:16:23.64$vc4f8/valo=6,772.99 2006.280.08:16:23.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.08:16:23.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.08:16:23.65#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:23.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:23.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:23.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:23.65#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:16:23.65#ibcon#first serial, iclass 14, count 0 2006.280.08:16:23.65#ibcon#enter sib2, iclass 14, count 0 2006.280.08:16:23.65#ibcon#flushed, iclass 14, count 0 2006.280.08:16:23.65#ibcon#about to write, iclass 14, count 0 2006.280.08:16:23.65#ibcon#wrote, iclass 14, count 0 2006.280.08:16:23.65#ibcon#about to read 3, iclass 14, count 0 2006.280.08:16:23.66#ibcon#read 3, iclass 14, count 0 2006.280.08:16:23.67#ibcon#about to read 4, iclass 14, count 0 2006.280.08:16:23.67#ibcon#read 4, iclass 14, count 0 2006.280.08:16:23.67#ibcon#about to read 5, iclass 14, count 0 2006.280.08:16:23.67#ibcon#read 5, iclass 14, count 0 2006.280.08:16:23.67#ibcon#about to read 6, iclass 14, count 0 2006.280.08:16:23.67#ibcon#read 6, iclass 14, count 0 2006.280.08:16:23.67#ibcon#end of sib2, iclass 14, count 0 2006.280.08:16:23.67#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:16:23.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:16:23.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:16:23.67#ibcon#*before write, iclass 14, count 0 2006.280.08:16:23.67#ibcon#enter sib2, iclass 14, count 0 2006.280.08:16:23.67#ibcon#flushed, iclass 14, count 0 2006.280.08:16:23.67#ibcon#about to write, iclass 14, count 0 2006.280.08:16:23.67#ibcon#wrote, iclass 14, count 0 2006.280.08:16:23.67#ibcon#about to read 3, iclass 14, count 0 2006.280.08:16:23.70#ibcon#read 3, iclass 14, count 0 2006.280.08:16:23.70#ibcon#about to read 4, iclass 14, count 0 2006.280.08:16:23.70#ibcon#read 4, iclass 14, count 0 2006.280.08:16:23.70#ibcon#about to read 5, iclass 14, count 0 2006.280.08:16:23.70#ibcon#read 5, iclass 14, count 0 2006.280.08:16:23.70#ibcon#about to read 6, iclass 14, count 0 2006.280.08:16:23.70#ibcon#read 6, iclass 14, count 0 2006.280.08:16:23.70#ibcon#end of sib2, iclass 14, count 0 2006.280.08:16:23.70#ibcon#*after write, iclass 14, count 0 2006.280.08:16:23.70#ibcon#*before return 0, iclass 14, count 0 2006.280.08:16:23.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:23.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:23.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:16:23.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:16:23.70$vc4f8/va=6,6 2006.280.08:16:23.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.08:16:23.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.08:16:23.71#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:23.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:23.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:23.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:23.75#ibcon#enter wrdev, iclass 16, count 2 2006.280.08:16:23.75#ibcon#first serial, iclass 16, count 2 2006.280.08:16:23.75#ibcon#enter sib2, iclass 16, count 2 2006.280.08:16:23.75#ibcon#flushed, iclass 16, count 2 2006.280.08:16:23.75#ibcon#about to write, iclass 16, count 2 2006.280.08:16:23.75#ibcon#wrote, iclass 16, count 2 2006.280.08:16:23.75#ibcon#about to read 3, iclass 16, count 2 2006.280.08:16:23.77#ibcon#read 3, iclass 16, count 2 2006.280.08:16:23.77#ibcon#about to read 4, iclass 16, count 2 2006.280.08:16:23.77#ibcon#read 4, iclass 16, count 2 2006.280.08:16:23.77#ibcon#about to read 5, iclass 16, count 2 2006.280.08:16:23.77#ibcon#read 5, iclass 16, count 2 2006.280.08:16:23.77#ibcon#about to read 6, iclass 16, count 2 2006.280.08:16:23.77#ibcon#read 6, iclass 16, count 2 2006.280.08:16:23.77#ibcon#end of sib2, iclass 16, count 2 2006.280.08:16:23.77#ibcon#*mode == 0, iclass 16, count 2 2006.280.08:16:23.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.08:16:23.77#ibcon#[25=AT06-06\r\n] 2006.280.08:16:23.77#ibcon#*before write, iclass 16, count 2 2006.280.08:16:23.77#ibcon#enter sib2, iclass 16, count 2 2006.280.08:16:23.77#ibcon#flushed, iclass 16, count 2 2006.280.08:16:23.77#ibcon#about to write, iclass 16, count 2 2006.280.08:16:23.77#ibcon#wrote, iclass 16, count 2 2006.280.08:16:23.77#ibcon#about to read 3, iclass 16, count 2 2006.280.08:16:23.80#ibcon#read 3, iclass 16, count 2 2006.280.08:16:23.80#ibcon#about to read 4, iclass 16, count 2 2006.280.08:16:23.80#ibcon#read 4, iclass 16, count 2 2006.280.08:16:23.80#ibcon#about to read 5, iclass 16, count 2 2006.280.08:16:23.80#ibcon#read 5, iclass 16, count 2 2006.280.08:16:23.80#ibcon#about to read 6, iclass 16, count 2 2006.280.08:16:23.80#ibcon#read 6, iclass 16, count 2 2006.280.08:16:23.80#ibcon#end of sib2, iclass 16, count 2 2006.280.08:16:23.80#ibcon#*after write, iclass 16, count 2 2006.280.08:16:23.80#ibcon#*before return 0, iclass 16, count 2 2006.280.08:16:23.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:23.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:23.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.08:16:23.80#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:23.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:23.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:23.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:23.92#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:16:23.92#ibcon#first serial, iclass 16, count 0 2006.280.08:16:23.92#ibcon#enter sib2, iclass 16, count 0 2006.280.08:16:23.92#ibcon#flushed, iclass 16, count 0 2006.280.08:16:23.92#ibcon#about to write, iclass 16, count 0 2006.280.08:16:23.92#ibcon#wrote, iclass 16, count 0 2006.280.08:16:23.92#ibcon#about to read 3, iclass 16, count 0 2006.280.08:16:23.94#ibcon#read 3, iclass 16, count 0 2006.280.08:16:23.94#ibcon#about to read 4, iclass 16, count 0 2006.280.08:16:23.94#ibcon#read 4, iclass 16, count 0 2006.280.08:16:23.94#ibcon#about to read 5, iclass 16, count 0 2006.280.08:16:23.94#ibcon#read 5, iclass 16, count 0 2006.280.08:16:23.94#ibcon#about to read 6, iclass 16, count 0 2006.280.08:16:23.94#ibcon#read 6, iclass 16, count 0 2006.280.08:16:23.94#ibcon#end of sib2, iclass 16, count 0 2006.280.08:16:23.94#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:16:23.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:16:23.94#ibcon#[25=USB\r\n] 2006.280.08:16:23.94#ibcon#*before write, iclass 16, count 0 2006.280.08:16:23.94#ibcon#enter sib2, iclass 16, count 0 2006.280.08:16:23.94#ibcon#flushed, iclass 16, count 0 2006.280.08:16:23.94#ibcon#about to write, iclass 16, count 0 2006.280.08:16:23.94#ibcon#wrote, iclass 16, count 0 2006.280.08:16:23.94#ibcon#about to read 3, iclass 16, count 0 2006.280.08:16:23.97#ibcon#read 3, iclass 16, count 0 2006.280.08:16:23.97#ibcon#about to read 4, iclass 16, count 0 2006.280.08:16:23.97#ibcon#read 4, iclass 16, count 0 2006.280.08:16:23.97#ibcon#about to read 5, iclass 16, count 0 2006.280.08:16:23.97#ibcon#read 5, iclass 16, count 0 2006.280.08:16:23.97#ibcon#about to read 6, iclass 16, count 0 2006.280.08:16:23.97#ibcon#read 6, iclass 16, count 0 2006.280.08:16:23.97#ibcon#end of sib2, iclass 16, count 0 2006.280.08:16:23.97#ibcon#*after write, iclass 16, count 0 2006.280.08:16:23.97#ibcon#*before return 0, iclass 16, count 0 2006.280.08:16:23.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:23.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:23.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:16:23.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:16:23.97$vc4f8/valo=7,832.99 2006.280.08:16:23.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:16:23.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:16:23.98#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:23.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:23.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:23.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:23.98#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:16:23.98#ibcon#first serial, iclass 18, count 0 2006.280.08:16:23.98#ibcon#enter sib2, iclass 18, count 0 2006.280.08:16:23.98#ibcon#flushed, iclass 18, count 0 2006.280.08:16:23.98#ibcon#about to write, iclass 18, count 0 2006.280.08:16:23.98#ibcon#wrote, iclass 18, count 0 2006.280.08:16:23.98#ibcon#about to read 3, iclass 18, count 0 2006.280.08:16:23.99#ibcon#read 3, iclass 18, count 0 2006.280.08:16:23.99#ibcon#about to read 4, iclass 18, count 0 2006.280.08:16:23.99#ibcon#read 4, iclass 18, count 0 2006.280.08:16:23.99#ibcon#about to read 5, iclass 18, count 0 2006.280.08:16:23.99#ibcon#read 5, iclass 18, count 0 2006.280.08:16:23.99#ibcon#about to read 6, iclass 18, count 0 2006.280.08:16:23.99#ibcon#read 6, iclass 18, count 0 2006.280.08:16:23.99#ibcon#end of sib2, iclass 18, count 0 2006.280.08:16:23.99#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:16:23.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:16:23.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:16:23.99#ibcon#*before write, iclass 18, count 0 2006.280.08:16:23.99#ibcon#enter sib2, iclass 18, count 0 2006.280.08:16:23.99#ibcon#flushed, iclass 18, count 0 2006.280.08:16:23.99#ibcon#about to write, iclass 18, count 0 2006.280.08:16:23.99#ibcon#wrote, iclass 18, count 0 2006.280.08:16:23.99#ibcon#about to read 3, iclass 18, count 0 2006.280.08:16:24.03#ibcon#read 3, iclass 18, count 0 2006.280.08:16:24.03#ibcon#about to read 4, iclass 18, count 0 2006.280.08:16:24.03#ibcon#read 4, iclass 18, count 0 2006.280.08:16:24.03#ibcon#about to read 5, iclass 18, count 0 2006.280.08:16:24.03#ibcon#read 5, iclass 18, count 0 2006.280.08:16:24.03#ibcon#about to read 6, iclass 18, count 0 2006.280.08:16:24.03#ibcon#read 6, iclass 18, count 0 2006.280.08:16:24.03#ibcon#end of sib2, iclass 18, count 0 2006.280.08:16:24.03#ibcon#*after write, iclass 18, count 0 2006.280.08:16:24.03#ibcon#*before return 0, iclass 18, count 0 2006.280.08:16:24.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:24.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:24.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:16:24.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:16:24.03$vc4f8/va=7,6 2006.280.08:16:24.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:16:24.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:16:24.04#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:24.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:24.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:24.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:24.08#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:16:24.08#ibcon#first serial, iclass 20, count 2 2006.280.08:16:24.08#ibcon#enter sib2, iclass 20, count 2 2006.280.08:16:24.08#ibcon#flushed, iclass 20, count 2 2006.280.08:16:24.08#ibcon#about to write, iclass 20, count 2 2006.280.08:16:24.08#ibcon#wrote, iclass 20, count 2 2006.280.08:16:24.08#ibcon#about to read 3, iclass 20, count 2 2006.280.08:16:24.10#ibcon#read 3, iclass 20, count 2 2006.280.08:16:24.10#ibcon#about to read 4, iclass 20, count 2 2006.280.08:16:24.10#ibcon#read 4, iclass 20, count 2 2006.280.08:16:24.10#ibcon#about to read 5, iclass 20, count 2 2006.280.08:16:24.10#ibcon#read 5, iclass 20, count 2 2006.280.08:16:24.10#ibcon#about to read 6, iclass 20, count 2 2006.280.08:16:24.10#ibcon#read 6, iclass 20, count 2 2006.280.08:16:24.10#ibcon#end of sib2, iclass 20, count 2 2006.280.08:16:24.10#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:16:24.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:16:24.10#ibcon#[25=AT07-06\r\n] 2006.280.08:16:24.10#ibcon#*before write, iclass 20, count 2 2006.280.08:16:24.10#ibcon#enter sib2, iclass 20, count 2 2006.280.08:16:24.10#ibcon#flushed, iclass 20, count 2 2006.280.08:16:24.10#ibcon#about to write, iclass 20, count 2 2006.280.08:16:24.10#ibcon#wrote, iclass 20, count 2 2006.280.08:16:24.10#ibcon#about to read 3, iclass 20, count 2 2006.280.08:16:24.13#ibcon#read 3, iclass 20, count 2 2006.280.08:16:24.13#ibcon#about to read 4, iclass 20, count 2 2006.280.08:16:24.13#ibcon#read 4, iclass 20, count 2 2006.280.08:16:24.13#ibcon#about to read 5, iclass 20, count 2 2006.280.08:16:24.13#ibcon#read 5, iclass 20, count 2 2006.280.08:16:24.13#ibcon#about to read 6, iclass 20, count 2 2006.280.08:16:24.13#ibcon#read 6, iclass 20, count 2 2006.280.08:16:24.13#ibcon#end of sib2, iclass 20, count 2 2006.280.08:16:24.13#ibcon#*after write, iclass 20, count 2 2006.280.08:16:24.13#ibcon#*before return 0, iclass 20, count 2 2006.280.08:16:24.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:24.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:24.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:16:24.13#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:24.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:16:24.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:16:24.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:16:24.26#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:16:24.26#ibcon#first serial, iclass 20, count 0 2006.280.08:16:24.26#ibcon#enter sib2, iclass 20, count 0 2006.280.08:16:24.26#ibcon#flushed, iclass 20, count 0 2006.280.08:16:24.26#ibcon#about to write, iclass 20, count 0 2006.280.08:16:24.26#ibcon#wrote, iclass 20, count 0 2006.280.08:16:24.26#ibcon#about to read 3, iclass 20, count 0 2006.280.08:16:24.28#ibcon#read 3, iclass 20, count 0 2006.280.08:16:24.28#ibcon#about to read 4, iclass 20, count 0 2006.280.08:16:24.28#ibcon#read 4, iclass 20, count 0 2006.280.08:16:24.28#ibcon#about to read 5, iclass 20, count 0 2006.280.08:16:24.28#ibcon#read 5, iclass 20, count 0 2006.280.08:16:24.28#ibcon#about to read 6, iclass 20, count 0 2006.280.08:16:24.28#ibcon#read 6, iclass 20, count 0 2006.280.08:16:24.28#ibcon#end of sib2, iclass 20, count 0 2006.280.08:16:24.28#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:16:24.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:16:24.28#ibcon#[25=USB\r\n] 2006.280.08:16:24.28#ibcon#*before write, iclass 20, count 0 2006.280.08:16:24.28#ibcon#enter sib2, iclass 20, count 0 2006.280.08:16:24.28#ibcon#flushed, iclass 20, count 0 2006.280.08:16:24.28#ibcon#about to write, iclass 20, count 0 2006.280.08:16:24.28#ibcon#wrote, iclass 20, count 0 2006.280.08:16:24.28#ibcon#about to read 3, iclass 20, count 0 2006.280.08:16:24.30#ibcon#read 3, iclass 20, count 0 2006.280.08:16:24.30#ibcon#about to read 4, iclass 20, count 0 2006.280.08:16:24.30#ibcon#read 4, iclass 20, count 0 2006.280.08:16:24.30#ibcon#about to read 5, iclass 20, count 0 2006.280.08:16:24.30#ibcon#read 5, iclass 20, count 0 2006.280.08:16:24.30#ibcon#about to read 6, iclass 20, count 0 2006.280.08:16:24.30#ibcon#read 6, iclass 20, count 0 2006.280.08:16:24.30#ibcon#end of sib2, iclass 20, count 0 2006.280.08:16:24.30#ibcon#*after write, iclass 20, count 0 2006.280.08:16:24.30#ibcon#*before return 0, iclass 20, count 0 2006.280.08:16:24.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:16:24.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:16:24.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:16:24.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:16:24.30$vc4f8/valo=8,852.99 2006.280.08:16:24.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:16:24.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:16:24.31#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:24.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:16:24.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:16:24.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:16:24.31#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:16:24.31#ibcon#first serial, iclass 22, count 0 2006.280.08:16:24.31#ibcon#enter sib2, iclass 22, count 0 2006.280.08:16:24.31#ibcon#flushed, iclass 22, count 0 2006.280.08:16:24.31#ibcon#about to write, iclass 22, count 0 2006.280.08:16:24.31#ibcon#wrote, iclass 22, count 0 2006.280.08:16:24.31#ibcon#about to read 3, iclass 22, count 0 2006.280.08:16:24.32#ibcon#read 3, iclass 22, count 0 2006.280.08:16:24.32#ibcon#about to read 4, iclass 22, count 0 2006.280.08:16:24.32#ibcon#read 4, iclass 22, count 0 2006.280.08:16:24.32#ibcon#about to read 5, iclass 22, count 0 2006.280.08:16:24.32#ibcon#read 5, iclass 22, count 0 2006.280.08:16:24.32#ibcon#about to read 6, iclass 22, count 0 2006.280.08:16:24.32#ibcon#read 6, iclass 22, count 0 2006.280.08:16:24.32#ibcon#end of sib2, iclass 22, count 0 2006.280.08:16:24.32#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:16:24.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:16:24.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:16:24.32#ibcon#*before write, iclass 22, count 0 2006.280.08:16:24.32#ibcon#enter sib2, iclass 22, count 0 2006.280.08:16:24.32#ibcon#flushed, iclass 22, count 0 2006.280.08:16:24.32#ibcon#about to write, iclass 22, count 0 2006.280.08:16:24.32#ibcon#wrote, iclass 22, count 0 2006.280.08:16:24.32#ibcon#about to read 3, iclass 22, count 0 2006.280.08:16:24.36#ibcon#read 3, iclass 22, count 0 2006.280.08:16:24.36#ibcon#about to read 4, iclass 22, count 0 2006.280.08:16:24.36#ibcon#read 4, iclass 22, count 0 2006.280.08:16:24.36#ibcon#about to read 5, iclass 22, count 0 2006.280.08:16:24.36#ibcon#read 5, iclass 22, count 0 2006.280.08:16:24.36#ibcon#about to read 6, iclass 22, count 0 2006.280.08:16:24.36#ibcon#read 6, iclass 22, count 0 2006.280.08:16:24.36#ibcon#end of sib2, iclass 22, count 0 2006.280.08:16:24.36#ibcon#*after write, iclass 22, count 0 2006.280.08:16:24.36#ibcon#*before return 0, iclass 22, count 0 2006.280.08:16:24.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:16:24.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:16:24.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:16:24.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:16:24.36$vc4f8/va=8,6 2006.280.08:16:24.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:16:24.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:16:24.37#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:24.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:16:24.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:16:24.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:16:24.41#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:16:24.41#ibcon#first serial, iclass 24, count 2 2006.280.08:16:24.41#ibcon#enter sib2, iclass 24, count 2 2006.280.08:16:24.41#ibcon#flushed, iclass 24, count 2 2006.280.08:16:24.41#ibcon#about to write, iclass 24, count 2 2006.280.08:16:24.41#ibcon#wrote, iclass 24, count 2 2006.280.08:16:24.41#ibcon#about to read 3, iclass 24, count 2 2006.280.08:16:24.43#ibcon#read 3, iclass 24, count 2 2006.280.08:16:24.43#ibcon#about to read 4, iclass 24, count 2 2006.280.08:16:24.43#ibcon#read 4, iclass 24, count 2 2006.280.08:16:24.43#ibcon#about to read 5, iclass 24, count 2 2006.280.08:16:24.43#ibcon#read 5, iclass 24, count 2 2006.280.08:16:24.43#ibcon#about to read 6, iclass 24, count 2 2006.280.08:16:24.43#ibcon#read 6, iclass 24, count 2 2006.280.08:16:24.43#ibcon#end of sib2, iclass 24, count 2 2006.280.08:16:24.43#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:16:24.43#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:16:24.43#ibcon#[25=AT08-06\r\n] 2006.280.08:16:24.43#ibcon#*before write, iclass 24, count 2 2006.280.08:16:24.43#ibcon#enter sib2, iclass 24, count 2 2006.280.08:16:24.43#ibcon#flushed, iclass 24, count 2 2006.280.08:16:24.43#ibcon#about to write, iclass 24, count 2 2006.280.08:16:24.43#ibcon#wrote, iclass 24, count 2 2006.280.08:16:24.43#ibcon#about to read 3, iclass 24, count 2 2006.280.08:16:24.46#ibcon#read 3, iclass 24, count 2 2006.280.08:16:24.46#ibcon#about to read 4, iclass 24, count 2 2006.280.08:16:24.46#ibcon#read 4, iclass 24, count 2 2006.280.08:16:24.46#ibcon#about to read 5, iclass 24, count 2 2006.280.08:16:24.46#ibcon#read 5, iclass 24, count 2 2006.280.08:16:24.46#ibcon#about to read 6, iclass 24, count 2 2006.280.08:16:24.46#ibcon#read 6, iclass 24, count 2 2006.280.08:16:24.46#ibcon#end of sib2, iclass 24, count 2 2006.280.08:16:24.46#ibcon#*after write, iclass 24, count 2 2006.280.08:16:24.46#ibcon#*before return 0, iclass 24, count 2 2006.280.08:16:24.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:16:24.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:16:24.46#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:16:24.46#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:24.46#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:16:24.58#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:16:24.58#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:16:24.58#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:16:24.58#ibcon#first serial, iclass 24, count 0 2006.280.08:16:24.58#ibcon#enter sib2, iclass 24, count 0 2006.280.08:16:24.58#ibcon#flushed, iclass 24, count 0 2006.280.08:16:24.58#ibcon#about to write, iclass 24, count 0 2006.280.08:16:24.58#ibcon#wrote, iclass 24, count 0 2006.280.08:16:24.58#ibcon#about to read 3, iclass 24, count 0 2006.280.08:16:24.60#ibcon#read 3, iclass 24, count 0 2006.280.08:16:24.60#ibcon#about to read 4, iclass 24, count 0 2006.280.08:16:24.60#ibcon#read 4, iclass 24, count 0 2006.280.08:16:24.60#ibcon#about to read 5, iclass 24, count 0 2006.280.08:16:24.60#ibcon#read 5, iclass 24, count 0 2006.280.08:16:24.60#ibcon#about to read 6, iclass 24, count 0 2006.280.08:16:24.60#ibcon#read 6, iclass 24, count 0 2006.280.08:16:24.60#ibcon#end of sib2, iclass 24, count 0 2006.280.08:16:24.60#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:16:24.60#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:16:24.60#ibcon#[25=USB\r\n] 2006.280.08:16:24.60#ibcon#*before write, iclass 24, count 0 2006.280.08:16:24.60#ibcon#enter sib2, iclass 24, count 0 2006.280.08:16:24.60#ibcon#flushed, iclass 24, count 0 2006.280.08:16:24.60#ibcon#about to write, iclass 24, count 0 2006.280.08:16:24.60#ibcon#wrote, iclass 24, count 0 2006.280.08:16:24.60#ibcon#about to read 3, iclass 24, count 0 2006.280.08:16:24.63#ibcon#read 3, iclass 24, count 0 2006.280.08:16:24.63#ibcon#about to read 4, iclass 24, count 0 2006.280.08:16:24.63#ibcon#read 4, iclass 24, count 0 2006.280.08:16:24.63#ibcon#about to read 5, iclass 24, count 0 2006.280.08:16:24.63#ibcon#read 5, iclass 24, count 0 2006.280.08:16:24.63#ibcon#about to read 6, iclass 24, count 0 2006.280.08:16:24.63#ibcon#read 6, iclass 24, count 0 2006.280.08:16:24.63#ibcon#end of sib2, iclass 24, count 0 2006.280.08:16:24.63#ibcon#*after write, iclass 24, count 0 2006.280.08:16:24.63#ibcon#*before return 0, iclass 24, count 0 2006.280.08:16:24.63#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:16:24.63#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:16:24.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:16:24.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:16:24.63$vc4f8/vblo=1,632.99 2006.280.08:16:24.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:16:24.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:16:24.64#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:24.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:16:24.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:16:24.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:16:24.64#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:16:24.64#ibcon#first serial, iclass 26, count 0 2006.280.08:16:24.64#ibcon#enter sib2, iclass 26, count 0 2006.280.08:16:24.64#ibcon#flushed, iclass 26, count 0 2006.280.08:16:24.64#ibcon#about to write, iclass 26, count 0 2006.280.08:16:24.64#ibcon#wrote, iclass 26, count 0 2006.280.08:16:24.64#ibcon#about to read 3, iclass 26, count 0 2006.280.08:16:24.65#ibcon#read 3, iclass 26, count 0 2006.280.08:16:24.65#ibcon#about to read 4, iclass 26, count 0 2006.280.08:16:24.65#ibcon#read 4, iclass 26, count 0 2006.280.08:16:24.65#ibcon#about to read 5, iclass 26, count 0 2006.280.08:16:24.65#ibcon#read 5, iclass 26, count 0 2006.280.08:16:24.65#ibcon#about to read 6, iclass 26, count 0 2006.280.08:16:24.65#ibcon#read 6, iclass 26, count 0 2006.280.08:16:24.65#ibcon#end of sib2, iclass 26, count 0 2006.280.08:16:24.65#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:16:24.65#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:16:24.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:16:24.65#ibcon#*before write, iclass 26, count 0 2006.280.08:16:24.65#ibcon#enter sib2, iclass 26, count 0 2006.280.08:16:24.65#ibcon#flushed, iclass 26, count 0 2006.280.08:16:24.65#ibcon#about to write, iclass 26, count 0 2006.280.08:16:24.65#ibcon#wrote, iclass 26, count 0 2006.280.08:16:24.65#ibcon#about to read 3, iclass 26, count 0 2006.280.08:16:24.69#ibcon#read 3, iclass 26, count 0 2006.280.08:16:24.69#ibcon#about to read 4, iclass 26, count 0 2006.280.08:16:24.69#ibcon#read 4, iclass 26, count 0 2006.280.08:16:24.69#ibcon#about to read 5, iclass 26, count 0 2006.280.08:16:24.69#ibcon#read 5, iclass 26, count 0 2006.280.08:16:24.69#ibcon#about to read 6, iclass 26, count 0 2006.280.08:16:24.69#ibcon#read 6, iclass 26, count 0 2006.280.08:16:24.69#ibcon#end of sib2, iclass 26, count 0 2006.280.08:16:24.69#ibcon#*after write, iclass 26, count 0 2006.280.08:16:24.69#ibcon#*before return 0, iclass 26, count 0 2006.280.08:16:24.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:16:24.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:16:24.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:16:24.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:16:24.70$vc4f8/vb=1,4 2006.280.08:16:24.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:16:24.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:16:24.71#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:24.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:16:24.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:16:24.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:16:24.71#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:16:24.71#ibcon#first serial, iclass 28, count 2 2006.280.08:16:24.71#ibcon#enter sib2, iclass 28, count 2 2006.280.08:16:24.71#ibcon#flushed, iclass 28, count 2 2006.280.08:16:24.71#ibcon#about to write, iclass 28, count 2 2006.280.08:16:24.71#ibcon#wrote, iclass 28, count 2 2006.280.08:16:24.71#ibcon#about to read 3, iclass 28, count 2 2006.280.08:16:24.72#ibcon#read 3, iclass 28, count 2 2006.280.08:16:24.72#ibcon#about to read 4, iclass 28, count 2 2006.280.08:16:24.72#ibcon#read 4, iclass 28, count 2 2006.280.08:16:24.72#ibcon#about to read 5, iclass 28, count 2 2006.280.08:16:24.72#ibcon#read 5, iclass 28, count 2 2006.280.08:16:24.72#ibcon#about to read 6, iclass 28, count 2 2006.280.08:16:24.72#ibcon#read 6, iclass 28, count 2 2006.280.08:16:24.72#ibcon#end of sib2, iclass 28, count 2 2006.280.08:16:24.72#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:16:24.72#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:16:24.72#ibcon#[27=AT01-04\r\n] 2006.280.08:16:24.72#ibcon#*before write, iclass 28, count 2 2006.280.08:16:24.72#ibcon#enter sib2, iclass 28, count 2 2006.280.08:16:24.72#ibcon#flushed, iclass 28, count 2 2006.280.08:16:24.72#ibcon#about to write, iclass 28, count 2 2006.280.08:16:24.72#ibcon#wrote, iclass 28, count 2 2006.280.08:16:24.72#ibcon#about to read 3, iclass 28, count 2 2006.280.08:16:24.75#ibcon#read 3, iclass 28, count 2 2006.280.08:16:24.75#ibcon#about to read 4, iclass 28, count 2 2006.280.08:16:24.75#ibcon#read 4, iclass 28, count 2 2006.280.08:16:24.75#ibcon#about to read 5, iclass 28, count 2 2006.280.08:16:24.75#ibcon#read 5, iclass 28, count 2 2006.280.08:16:24.75#ibcon#about to read 6, iclass 28, count 2 2006.280.08:16:24.75#ibcon#read 6, iclass 28, count 2 2006.280.08:16:24.75#ibcon#end of sib2, iclass 28, count 2 2006.280.08:16:24.75#ibcon#*after write, iclass 28, count 2 2006.280.08:16:24.75#ibcon#*before return 0, iclass 28, count 2 2006.280.08:16:24.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:16:24.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:16:24.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:16:24.75#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:24.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:16:24.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:16:24.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:16:24.88#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:16:24.88#ibcon#first serial, iclass 28, count 0 2006.280.08:16:24.88#ibcon#enter sib2, iclass 28, count 0 2006.280.08:16:24.88#ibcon#flushed, iclass 28, count 0 2006.280.08:16:24.88#ibcon#about to write, iclass 28, count 0 2006.280.08:16:24.88#ibcon#wrote, iclass 28, count 0 2006.280.08:16:24.88#ibcon#about to read 3, iclass 28, count 0 2006.280.08:16:24.90#ibcon#read 3, iclass 28, count 0 2006.280.08:16:24.90#ibcon#about to read 4, iclass 28, count 0 2006.280.08:16:24.90#ibcon#read 4, iclass 28, count 0 2006.280.08:16:24.90#ibcon#about to read 5, iclass 28, count 0 2006.280.08:16:24.90#ibcon#read 5, iclass 28, count 0 2006.280.08:16:24.90#ibcon#about to read 6, iclass 28, count 0 2006.280.08:16:24.90#ibcon#read 6, iclass 28, count 0 2006.280.08:16:24.90#ibcon#end of sib2, iclass 28, count 0 2006.280.08:16:24.90#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:16:24.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:16:24.90#ibcon#[27=USB\r\n] 2006.280.08:16:24.90#ibcon#*before write, iclass 28, count 0 2006.280.08:16:24.90#ibcon#enter sib2, iclass 28, count 0 2006.280.08:16:24.90#ibcon#flushed, iclass 28, count 0 2006.280.08:16:24.90#ibcon#about to write, iclass 28, count 0 2006.280.08:16:24.90#ibcon#wrote, iclass 28, count 0 2006.280.08:16:24.90#ibcon#about to read 3, iclass 28, count 0 2006.280.08:16:24.92#ibcon#read 3, iclass 28, count 0 2006.280.08:16:24.92#ibcon#about to read 4, iclass 28, count 0 2006.280.08:16:24.92#ibcon#read 4, iclass 28, count 0 2006.280.08:16:24.92#ibcon#about to read 5, iclass 28, count 0 2006.280.08:16:24.92#ibcon#read 5, iclass 28, count 0 2006.280.08:16:24.92#ibcon#about to read 6, iclass 28, count 0 2006.280.08:16:24.92#ibcon#read 6, iclass 28, count 0 2006.280.08:16:24.92#ibcon#end of sib2, iclass 28, count 0 2006.280.08:16:24.92#ibcon#*after write, iclass 28, count 0 2006.280.08:16:24.92#ibcon#*before return 0, iclass 28, count 0 2006.280.08:16:24.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:16:24.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:16:24.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:16:24.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:16:24.92$vc4f8/vblo=2,640.99 2006.280.08:16:24.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:16:24.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:16:24.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:24.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:24.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:24.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:24.93#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:16:24.93#ibcon#first serial, iclass 30, count 0 2006.280.08:16:24.93#ibcon#enter sib2, iclass 30, count 0 2006.280.08:16:24.93#ibcon#flushed, iclass 30, count 0 2006.280.08:16:24.93#ibcon#about to write, iclass 30, count 0 2006.280.08:16:24.93#ibcon#wrote, iclass 30, count 0 2006.280.08:16:24.93#ibcon#about to read 3, iclass 30, count 0 2006.280.08:16:24.94#ibcon#read 3, iclass 30, count 0 2006.280.08:16:24.94#ibcon#about to read 4, iclass 30, count 0 2006.280.08:16:24.94#ibcon#read 4, iclass 30, count 0 2006.280.08:16:24.94#ibcon#about to read 5, iclass 30, count 0 2006.280.08:16:24.94#ibcon#read 5, iclass 30, count 0 2006.280.08:16:24.94#ibcon#about to read 6, iclass 30, count 0 2006.280.08:16:24.94#ibcon#read 6, iclass 30, count 0 2006.280.08:16:24.94#ibcon#end of sib2, iclass 30, count 0 2006.280.08:16:24.94#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:16:24.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:16:24.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:16:24.94#ibcon#*before write, iclass 30, count 0 2006.280.08:16:24.94#ibcon#enter sib2, iclass 30, count 0 2006.280.08:16:24.94#ibcon#flushed, iclass 30, count 0 2006.280.08:16:24.94#ibcon#about to write, iclass 30, count 0 2006.280.08:16:24.94#ibcon#wrote, iclass 30, count 0 2006.280.08:16:24.94#ibcon#about to read 3, iclass 30, count 0 2006.280.08:16:24.98#ibcon#read 3, iclass 30, count 0 2006.280.08:16:24.98#ibcon#about to read 4, iclass 30, count 0 2006.280.08:16:24.98#ibcon#read 4, iclass 30, count 0 2006.280.08:16:24.98#ibcon#about to read 5, iclass 30, count 0 2006.280.08:16:24.98#ibcon#read 5, iclass 30, count 0 2006.280.08:16:24.98#ibcon#about to read 6, iclass 30, count 0 2006.280.08:16:24.98#ibcon#read 6, iclass 30, count 0 2006.280.08:16:24.98#ibcon#end of sib2, iclass 30, count 0 2006.280.08:16:24.98#ibcon#*after write, iclass 30, count 0 2006.280.08:16:24.98#ibcon#*before return 0, iclass 30, count 0 2006.280.08:16:24.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:24.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:16:24.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:16:24.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:16:24.98$vc4f8/vb=2,5 2006.280.08:16:24.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:16:24.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:16:24.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:24.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:25.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:25.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:25.03#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:16:25.03#ibcon#first serial, iclass 32, count 2 2006.280.08:16:25.03#ibcon#enter sib2, iclass 32, count 2 2006.280.08:16:25.03#ibcon#flushed, iclass 32, count 2 2006.280.08:16:25.03#ibcon#about to write, iclass 32, count 2 2006.280.08:16:25.03#ibcon#wrote, iclass 32, count 2 2006.280.08:16:25.03#ibcon#about to read 3, iclass 32, count 2 2006.280.08:16:25.05#ibcon#read 3, iclass 32, count 2 2006.280.08:16:25.05#ibcon#about to read 4, iclass 32, count 2 2006.280.08:16:25.05#ibcon#read 4, iclass 32, count 2 2006.280.08:16:25.05#ibcon#about to read 5, iclass 32, count 2 2006.280.08:16:25.05#ibcon#read 5, iclass 32, count 2 2006.280.08:16:25.05#ibcon#about to read 6, iclass 32, count 2 2006.280.08:16:25.05#ibcon#read 6, iclass 32, count 2 2006.280.08:16:25.05#ibcon#end of sib2, iclass 32, count 2 2006.280.08:16:25.05#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:16:25.05#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:16:25.05#ibcon#[27=AT02-05\r\n] 2006.280.08:16:25.05#ibcon#*before write, iclass 32, count 2 2006.280.08:16:25.05#ibcon#enter sib2, iclass 32, count 2 2006.280.08:16:25.05#ibcon#flushed, iclass 32, count 2 2006.280.08:16:25.05#ibcon#about to write, iclass 32, count 2 2006.280.08:16:25.05#ibcon#wrote, iclass 32, count 2 2006.280.08:16:25.05#ibcon#about to read 3, iclass 32, count 2 2006.280.08:16:25.08#ibcon#read 3, iclass 32, count 2 2006.280.08:16:25.08#ibcon#about to read 4, iclass 32, count 2 2006.280.08:16:25.08#ibcon#read 4, iclass 32, count 2 2006.280.08:16:25.08#ibcon#about to read 5, iclass 32, count 2 2006.280.08:16:25.08#ibcon#read 5, iclass 32, count 2 2006.280.08:16:25.08#ibcon#about to read 6, iclass 32, count 2 2006.280.08:16:25.08#ibcon#read 6, iclass 32, count 2 2006.280.08:16:25.08#ibcon#end of sib2, iclass 32, count 2 2006.280.08:16:25.08#ibcon#*after write, iclass 32, count 2 2006.280.08:16:25.08#ibcon#*before return 0, iclass 32, count 2 2006.280.08:16:25.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:25.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:16:25.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:16:25.08#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:25.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:25.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:25.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:25.21#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:16:25.21#ibcon#first serial, iclass 32, count 0 2006.280.08:16:25.21#ibcon#enter sib2, iclass 32, count 0 2006.280.08:16:25.21#ibcon#flushed, iclass 32, count 0 2006.280.08:16:25.21#ibcon#about to write, iclass 32, count 0 2006.280.08:16:25.21#ibcon#wrote, iclass 32, count 0 2006.280.08:16:25.21#ibcon#about to read 3, iclass 32, count 0 2006.280.08:16:25.22#ibcon#read 3, iclass 32, count 0 2006.280.08:16:25.22#ibcon#about to read 4, iclass 32, count 0 2006.280.08:16:25.22#ibcon#read 4, iclass 32, count 0 2006.280.08:16:25.22#ibcon#about to read 5, iclass 32, count 0 2006.280.08:16:25.22#ibcon#read 5, iclass 32, count 0 2006.280.08:16:25.22#ibcon#about to read 6, iclass 32, count 0 2006.280.08:16:25.22#ibcon#read 6, iclass 32, count 0 2006.280.08:16:25.22#ibcon#end of sib2, iclass 32, count 0 2006.280.08:16:25.22#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:16:25.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:16:25.22#ibcon#[27=USB\r\n] 2006.280.08:16:25.22#ibcon#*before write, iclass 32, count 0 2006.280.08:16:25.22#ibcon#enter sib2, iclass 32, count 0 2006.280.08:16:25.22#ibcon#flushed, iclass 32, count 0 2006.280.08:16:25.22#ibcon#about to write, iclass 32, count 0 2006.280.08:16:25.22#ibcon#wrote, iclass 32, count 0 2006.280.08:16:25.22#ibcon#about to read 3, iclass 32, count 0 2006.280.08:16:25.25#ibcon#read 3, iclass 32, count 0 2006.280.08:16:25.25#ibcon#about to read 4, iclass 32, count 0 2006.280.08:16:25.25#ibcon#read 4, iclass 32, count 0 2006.280.08:16:25.25#ibcon#about to read 5, iclass 32, count 0 2006.280.08:16:25.25#ibcon#read 5, iclass 32, count 0 2006.280.08:16:25.25#ibcon#about to read 6, iclass 32, count 0 2006.280.08:16:25.25#ibcon#read 6, iclass 32, count 0 2006.280.08:16:25.25#ibcon#end of sib2, iclass 32, count 0 2006.280.08:16:25.25#ibcon#*after write, iclass 32, count 0 2006.280.08:16:25.25#ibcon#*before return 0, iclass 32, count 0 2006.280.08:16:25.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:25.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:16:25.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:16:25.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:16:25.25$vc4f8/vblo=3,656.99 2006.280.08:16:25.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.08:16:25.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.08:16:25.26#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:25.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:16:25.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:16:25.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:16:25.26#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:16:25.26#ibcon#first serial, iclass 35, count 0 2006.280.08:16:25.26#ibcon#enter sib2, iclass 35, count 0 2006.280.08:16:25.26#ibcon#flushed, iclass 35, count 0 2006.280.08:16:25.26#ibcon#about to write, iclass 35, count 0 2006.280.08:16:25.26#ibcon#wrote, iclass 35, count 0 2006.280.08:16:25.26#ibcon#about to read 3, iclass 35, count 0 2006.280.08:16:25.27#ibcon#read 3, iclass 35, count 0 2006.280.08:16:25.27#ibcon#about to read 4, iclass 35, count 0 2006.280.08:16:25.27#ibcon#read 4, iclass 35, count 0 2006.280.08:16:25.27#ibcon#about to read 5, iclass 35, count 0 2006.280.08:16:25.27#ibcon#read 5, iclass 35, count 0 2006.280.08:16:25.27#ibcon#about to read 6, iclass 35, count 0 2006.280.08:16:25.27#ibcon#read 6, iclass 35, count 0 2006.280.08:16:25.27#ibcon#end of sib2, iclass 35, count 0 2006.280.08:16:25.27#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:16:25.27#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:16:25.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:16:25.27#ibcon#*before write, iclass 35, count 0 2006.280.08:16:25.27#ibcon#enter sib2, iclass 35, count 0 2006.280.08:16:25.27#ibcon#flushed, iclass 35, count 0 2006.280.08:16:25.27#ibcon#about to write, iclass 35, count 0 2006.280.08:16:25.27#ibcon#wrote, iclass 35, count 0 2006.280.08:16:25.27#ibcon#about to read 3, iclass 35, count 0 2006.280.08:16:25.29#abcon#<5=/13 1.2 3.2 20.39 64 987.6\r\n> 2006.280.08:16:25.31#abcon#{5=INTERFACE CLEAR} 2006.280.08:16:25.31#ibcon#read 3, iclass 35, count 0 2006.280.08:16:25.31#ibcon#about to read 4, iclass 35, count 0 2006.280.08:16:25.31#ibcon#read 4, iclass 35, count 0 2006.280.08:16:25.31#ibcon#about to read 5, iclass 35, count 0 2006.280.08:16:25.31#ibcon#read 5, iclass 35, count 0 2006.280.08:16:25.31#ibcon#about to read 6, iclass 35, count 0 2006.280.08:16:25.31#ibcon#read 6, iclass 35, count 0 2006.280.08:16:25.31#ibcon#end of sib2, iclass 35, count 0 2006.280.08:16:25.31#ibcon#*after write, iclass 35, count 0 2006.280.08:16:25.31#ibcon#*before return 0, iclass 35, count 0 2006.280.08:16:25.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:16:25.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:16:25.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:16:25.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:16:25.33$vc4f8/vb=3,4 2006.280.08:16:25.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.280.08:16:25.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.280.08:16:25.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:25.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:16:25.38#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:16:25.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:16:25.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:16:25.38#ibcon#enter wrdev, iclass 39, count 2 2006.280.08:16:25.38#ibcon#first serial, iclass 39, count 2 2006.280.08:16:25.38#ibcon#enter sib2, iclass 39, count 2 2006.280.08:16:25.38#ibcon#flushed, iclass 39, count 2 2006.280.08:16:25.38#ibcon#about to write, iclass 39, count 2 2006.280.08:16:25.38#ibcon#wrote, iclass 39, count 2 2006.280.08:16:25.38#ibcon#about to read 3, iclass 39, count 2 2006.280.08:16:25.40#ibcon#read 3, iclass 39, count 2 2006.280.08:16:25.40#ibcon#about to read 4, iclass 39, count 2 2006.280.08:16:25.40#ibcon#read 4, iclass 39, count 2 2006.280.08:16:25.40#ibcon#about to read 5, iclass 39, count 2 2006.280.08:16:25.40#ibcon#read 5, iclass 39, count 2 2006.280.08:16:25.40#ibcon#about to read 6, iclass 39, count 2 2006.280.08:16:25.40#ibcon#read 6, iclass 39, count 2 2006.280.08:16:25.40#ibcon#end of sib2, iclass 39, count 2 2006.280.08:16:25.40#ibcon#*mode == 0, iclass 39, count 2 2006.280.08:16:25.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.280.08:16:25.40#ibcon#[27=AT03-04\r\n] 2006.280.08:16:25.40#ibcon#*before write, iclass 39, count 2 2006.280.08:16:25.40#ibcon#enter sib2, iclass 39, count 2 2006.280.08:16:25.40#ibcon#flushed, iclass 39, count 2 2006.280.08:16:25.40#ibcon#about to write, iclass 39, count 2 2006.280.08:16:25.40#ibcon#wrote, iclass 39, count 2 2006.280.08:16:25.40#ibcon#about to read 3, iclass 39, count 2 2006.280.08:16:25.43#ibcon#read 3, iclass 39, count 2 2006.280.08:16:25.43#ibcon#about to read 4, iclass 39, count 2 2006.280.08:16:25.43#ibcon#read 4, iclass 39, count 2 2006.280.08:16:25.43#ibcon#about to read 5, iclass 39, count 2 2006.280.08:16:25.43#ibcon#read 5, iclass 39, count 2 2006.280.08:16:25.43#ibcon#about to read 6, iclass 39, count 2 2006.280.08:16:25.43#ibcon#read 6, iclass 39, count 2 2006.280.08:16:25.43#ibcon#end of sib2, iclass 39, count 2 2006.280.08:16:25.43#ibcon#*after write, iclass 39, count 2 2006.280.08:16:25.43#ibcon#*before return 0, iclass 39, count 2 2006.280.08:16:25.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:16:25.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.280.08:16:25.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.280.08:16:25.43#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:25.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:16:25.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:16:25.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:16:25.54#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:16:25.54#ibcon#first serial, iclass 39, count 0 2006.280.08:16:25.54#ibcon#enter sib2, iclass 39, count 0 2006.280.08:16:25.54#ibcon#flushed, iclass 39, count 0 2006.280.08:16:25.54#ibcon#about to write, iclass 39, count 0 2006.280.08:16:25.54#ibcon#wrote, iclass 39, count 0 2006.280.08:16:25.54#ibcon#about to read 3, iclass 39, count 0 2006.280.08:16:25.56#ibcon#read 3, iclass 39, count 0 2006.280.08:16:25.56#ibcon#about to read 4, iclass 39, count 0 2006.280.08:16:25.56#ibcon#read 4, iclass 39, count 0 2006.280.08:16:25.56#ibcon#about to read 5, iclass 39, count 0 2006.280.08:16:25.56#ibcon#read 5, iclass 39, count 0 2006.280.08:16:25.56#ibcon#about to read 6, iclass 39, count 0 2006.280.08:16:25.56#ibcon#read 6, iclass 39, count 0 2006.280.08:16:25.56#ibcon#end of sib2, iclass 39, count 0 2006.280.08:16:25.56#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:16:25.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:16:25.56#ibcon#[27=USB\r\n] 2006.280.08:16:25.56#ibcon#*before write, iclass 39, count 0 2006.280.08:16:25.56#ibcon#enter sib2, iclass 39, count 0 2006.280.08:16:25.56#ibcon#flushed, iclass 39, count 0 2006.280.08:16:25.56#ibcon#about to write, iclass 39, count 0 2006.280.08:16:25.56#ibcon#wrote, iclass 39, count 0 2006.280.08:16:25.56#ibcon#about to read 3, iclass 39, count 0 2006.280.08:16:25.60#ibcon#read 3, iclass 39, count 0 2006.280.08:16:25.60#ibcon#about to read 4, iclass 39, count 0 2006.280.08:16:25.60#ibcon#read 4, iclass 39, count 0 2006.280.08:16:25.60#ibcon#about to read 5, iclass 39, count 0 2006.280.08:16:25.60#ibcon#read 5, iclass 39, count 0 2006.280.08:16:25.60#ibcon#about to read 6, iclass 39, count 0 2006.280.08:16:25.60#ibcon#read 6, iclass 39, count 0 2006.280.08:16:25.60#ibcon#end of sib2, iclass 39, count 0 2006.280.08:16:25.60#ibcon#*after write, iclass 39, count 0 2006.280.08:16:25.60#ibcon#*before return 0, iclass 39, count 0 2006.280.08:16:25.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:16:25.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.280.08:16:25.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:16:25.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:16:25.60$vc4f8/vblo=4,712.99 2006.280.08:16:25.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:16:25.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:16:25.60#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:25.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:25.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:25.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:25.60#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:16:25.60#ibcon#first serial, iclass 4, count 0 2006.280.08:16:25.60#ibcon#enter sib2, iclass 4, count 0 2006.280.08:16:25.60#ibcon#flushed, iclass 4, count 0 2006.280.08:16:25.60#ibcon#about to write, iclass 4, count 0 2006.280.08:16:25.60#ibcon#wrote, iclass 4, count 0 2006.280.08:16:25.60#ibcon#about to read 3, iclass 4, count 0 2006.280.08:16:25.61#ibcon#read 3, iclass 4, count 0 2006.280.08:16:25.61#ibcon#about to read 4, iclass 4, count 0 2006.280.08:16:25.61#ibcon#read 4, iclass 4, count 0 2006.280.08:16:25.61#ibcon#about to read 5, iclass 4, count 0 2006.280.08:16:25.61#ibcon#read 5, iclass 4, count 0 2006.280.08:16:25.61#ibcon#about to read 6, iclass 4, count 0 2006.280.08:16:25.61#ibcon#read 6, iclass 4, count 0 2006.280.08:16:25.61#ibcon#end of sib2, iclass 4, count 0 2006.280.08:16:25.61#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:16:25.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:16:25.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:16:25.64#ibcon#*before write, iclass 4, count 0 2006.280.08:16:25.64#ibcon#enter sib2, iclass 4, count 0 2006.280.08:16:25.64#ibcon#flushed, iclass 4, count 0 2006.280.08:16:25.64#ibcon#about to write, iclass 4, count 0 2006.280.08:16:25.64#ibcon#wrote, iclass 4, count 0 2006.280.08:16:25.64#ibcon#about to read 3, iclass 4, count 0 2006.280.08:16:25.69#ibcon#read 3, iclass 4, count 0 2006.280.08:16:25.69#ibcon#about to read 4, iclass 4, count 0 2006.280.08:16:25.69#ibcon#read 4, iclass 4, count 0 2006.280.08:16:25.69#ibcon#about to read 5, iclass 4, count 0 2006.280.08:16:25.69#ibcon#read 5, iclass 4, count 0 2006.280.08:16:25.69#ibcon#about to read 6, iclass 4, count 0 2006.280.08:16:25.69#ibcon#read 6, iclass 4, count 0 2006.280.08:16:25.69#ibcon#end of sib2, iclass 4, count 0 2006.280.08:16:25.69#ibcon#*after write, iclass 4, count 0 2006.280.08:16:25.69#ibcon#*before return 0, iclass 4, count 0 2006.280.08:16:25.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:25.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:16:25.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:16:25.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:16:25.69$vc4f8/vb=4,4 2006.280.08:16:25.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:16:25.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:16:25.69#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:25.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:25.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:25.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:25.71#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:16:25.71#ibcon#first serial, iclass 6, count 2 2006.280.08:16:25.71#ibcon#enter sib2, iclass 6, count 2 2006.280.08:16:25.71#ibcon#flushed, iclass 6, count 2 2006.280.08:16:25.71#ibcon#about to write, iclass 6, count 2 2006.280.08:16:25.71#ibcon#wrote, iclass 6, count 2 2006.280.08:16:25.71#ibcon#about to read 3, iclass 6, count 2 2006.280.08:16:25.74#ibcon#read 3, iclass 6, count 2 2006.280.08:16:25.74#ibcon#about to read 4, iclass 6, count 2 2006.280.08:16:25.74#ibcon#read 4, iclass 6, count 2 2006.280.08:16:25.74#ibcon#about to read 5, iclass 6, count 2 2006.280.08:16:25.74#ibcon#read 5, iclass 6, count 2 2006.280.08:16:25.74#ibcon#about to read 6, iclass 6, count 2 2006.280.08:16:25.74#ibcon#read 6, iclass 6, count 2 2006.280.08:16:25.74#ibcon#end of sib2, iclass 6, count 2 2006.280.08:16:25.74#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:16:25.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:16:25.74#ibcon#[27=AT04-04\r\n] 2006.280.08:16:25.74#ibcon#*before write, iclass 6, count 2 2006.280.08:16:25.74#ibcon#enter sib2, iclass 6, count 2 2006.280.08:16:25.74#ibcon#flushed, iclass 6, count 2 2006.280.08:16:25.74#ibcon#about to write, iclass 6, count 2 2006.280.08:16:25.74#ibcon#wrote, iclass 6, count 2 2006.280.08:16:25.74#ibcon#about to read 3, iclass 6, count 2 2006.280.08:16:25.76#ibcon#read 3, iclass 6, count 2 2006.280.08:16:25.76#ibcon#about to read 4, iclass 6, count 2 2006.280.08:16:25.76#ibcon#read 4, iclass 6, count 2 2006.280.08:16:25.76#ibcon#about to read 5, iclass 6, count 2 2006.280.08:16:25.76#ibcon#read 5, iclass 6, count 2 2006.280.08:16:25.76#ibcon#about to read 6, iclass 6, count 2 2006.280.08:16:25.76#ibcon#read 6, iclass 6, count 2 2006.280.08:16:25.76#ibcon#end of sib2, iclass 6, count 2 2006.280.08:16:25.76#ibcon#*after write, iclass 6, count 2 2006.280.08:16:25.76#ibcon#*before return 0, iclass 6, count 2 2006.280.08:16:25.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:25.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:16:25.76#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:16:25.76#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:25.76#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:25.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:25.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:25.88#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:16:25.88#ibcon#first serial, iclass 6, count 0 2006.280.08:16:25.88#ibcon#enter sib2, iclass 6, count 0 2006.280.08:16:25.88#ibcon#flushed, iclass 6, count 0 2006.280.08:16:25.88#ibcon#about to write, iclass 6, count 0 2006.280.08:16:25.88#ibcon#wrote, iclass 6, count 0 2006.280.08:16:25.88#ibcon#about to read 3, iclass 6, count 0 2006.280.08:16:25.90#ibcon#read 3, iclass 6, count 0 2006.280.08:16:25.90#ibcon#about to read 4, iclass 6, count 0 2006.280.08:16:25.90#ibcon#read 4, iclass 6, count 0 2006.280.08:16:25.90#ibcon#about to read 5, iclass 6, count 0 2006.280.08:16:25.90#ibcon#read 5, iclass 6, count 0 2006.280.08:16:25.90#ibcon#about to read 6, iclass 6, count 0 2006.280.08:16:25.90#ibcon#read 6, iclass 6, count 0 2006.280.08:16:25.90#ibcon#end of sib2, iclass 6, count 0 2006.280.08:16:25.90#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:16:25.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:16:25.90#ibcon#[27=USB\r\n] 2006.280.08:16:25.90#ibcon#*before write, iclass 6, count 0 2006.280.08:16:25.90#ibcon#enter sib2, iclass 6, count 0 2006.280.08:16:25.90#ibcon#flushed, iclass 6, count 0 2006.280.08:16:25.90#ibcon#about to write, iclass 6, count 0 2006.280.08:16:25.90#ibcon#wrote, iclass 6, count 0 2006.280.08:16:25.90#ibcon#about to read 3, iclass 6, count 0 2006.280.08:16:25.93#ibcon#read 3, iclass 6, count 0 2006.280.08:16:25.93#ibcon#about to read 4, iclass 6, count 0 2006.280.08:16:25.93#ibcon#read 4, iclass 6, count 0 2006.280.08:16:25.93#ibcon#about to read 5, iclass 6, count 0 2006.280.08:16:25.93#ibcon#read 5, iclass 6, count 0 2006.280.08:16:25.93#ibcon#about to read 6, iclass 6, count 0 2006.280.08:16:25.93#ibcon#read 6, iclass 6, count 0 2006.280.08:16:25.93#ibcon#end of sib2, iclass 6, count 0 2006.280.08:16:25.93#ibcon#*after write, iclass 6, count 0 2006.280.08:16:25.93#ibcon#*before return 0, iclass 6, count 0 2006.280.08:16:25.93#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:25.93#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:16:25.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:16:25.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:16:25.93$vc4f8/vblo=5,744.99 2006.280.08:16:25.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:16:25.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:16:25.94#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:25.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:25.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:25.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:25.94#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:16:25.94#ibcon#first serial, iclass 10, count 0 2006.280.08:16:25.94#ibcon#enter sib2, iclass 10, count 0 2006.280.08:16:25.94#ibcon#flushed, iclass 10, count 0 2006.280.08:16:25.94#ibcon#about to write, iclass 10, count 0 2006.280.08:16:25.94#ibcon#wrote, iclass 10, count 0 2006.280.08:16:25.94#ibcon#about to read 3, iclass 10, count 0 2006.280.08:16:25.95#ibcon#read 3, iclass 10, count 0 2006.280.08:16:25.96#ibcon#about to read 4, iclass 10, count 0 2006.280.08:16:25.96#ibcon#read 4, iclass 10, count 0 2006.280.08:16:25.96#ibcon#about to read 5, iclass 10, count 0 2006.280.08:16:25.96#ibcon#read 5, iclass 10, count 0 2006.280.08:16:25.96#ibcon#about to read 6, iclass 10, count 0 2006.280.08:16:25.96#ibcon#read 6, iclass 10, count 0 2006.280.08:16:25.96#ibcon#end of sib2, iclass 10, count 0 2006.280.08:16:25.96#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:16:25.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:16:25.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:16:25.96#ibcon#*before write, iclass 10, count 0 2006.280.08:16:25.96#ibcon#enter sib2, iclass 10, count 0 2006.280.08:16:25.96#ibcon#flushed, iclass 10, count 0 2006.280.08:16:25.96#ibcon#about to write, iclass 10, count 0 2006.280.08:16:25.96#ibcon#wrote, iclass 10, count 0 2006.280.08:16:25.96#ibcon#about to read 3, iclass 10, count 0 2006.280.08:16:25.99#ibcon#read 3, iclass 10, count 0 2006.280.08:16:25.99#ibcon#about to read 4, iclass 10, count 0 2006.280.08:16:25.99#ibcon#read 4, iclass 10, count 0 2006.280.08:16:25.99#ibcon#about to read 5, iclass 10, count 0 2006.280.08:16:25.99#ibcon#read 5, iclass 10, count 0 2006.280.08:16:25.99#ibcon#about to read 6, iclass 10, count 0 2006.280.08:16:25.99#ibcon#read 6, iclass 10, count 0 2006.280.08:16:25.99#ibcon#end of sib2, iclass 10, count 0 2006.280.08:16:25.99#ibcon#*after write, iclass 10, count 0 2006.280.08:16:25.99#ibcon#*before return 0, iclass 10, count 0 2006.280.08:16:25.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:25.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:16:25.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:16:25.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:16:25.99$vc4f8/vb=5,4 2006.280.08:16:25.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:16:26.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:16:26.00#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:26.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:26.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:26.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:26.04#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:16:26.04#ibcon#first serial, iclass 12, count 2 2006.280.08:16:26.04#ibcon#enter sib2, iclass 12, count 2 2006.280.08:16:26.04#ibcon#flushed, iclass 12, count 2 2006.280.08:16:26.04#ibcon#about to write, iclass 12, count 2 2006.280.08:16:26.04#ibcon#wrote, iclass 12, count 2 2006.280.08:16:26.04#ibcon#about to read 3, iclass 12, count 2 2006.280.08:16:26.06#ibcon#read 3, iclass 12, count 2 2006.280.08:16:26.06#ibcon#about to read 4, iclass 12, count 2 2006.280.08:16:26.06#ibcon#read 4, iclass 12, count 2 2006.280.08:16:26.06#ibcon#about to read 5, iclass 12, count 2 2006.280.08:16:26.06#ibcon#read 5, iclass 12, count 2 2006.280.08:16:26.06#ibcon#about to read 6, iclass 12, count 2 2006.280.08:16:26.06#ibcon#read 6, iclass 12, count 2 2006.280.08:16:26.06#ibcon#end of sib2, iclass 12, count 2 2006.280.08:16:26.06#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:16:26.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:16:26.06#ibcon#[27=AT05-04\r\n] 2006.280.08:16:26.06#ibcon#*before write, iclass 12, count 2 2006.280.08:16:26.06#ibcon#enter sib2, iclass 12, count 2 2006.280.08:16:26.06#ibcon#flushed, iclass 12, count 2 2006.280.08:16:26.06#ibcon#about to write, iclass 12, count 2 2006.280.08:16:26.06#ibcon#wrote, iclass 12, count 2 2006.280.08:16:26.06#ibcon#about to read 3, iclass 12, count 2 2006.280.08:16:26.09#ibcon#read 3, iclass 12, count 2 2006.280.08:16:26.09#ibcon#about to read 4, iclass 12, count 2 2006.280.08:16:26.09#ibcon#read 4, iclass 12, count 2 2006.280.08:16:26.09#ibcon#about to read 5, iclass 12, count 2 2006.280.08:16:26.09#ibcon#read 5, iclass 12, count 2 2006.280.08:16:26.09#ibcon#about to read 6, iclass 12, count 2 2006.280.08:16:26.09#ibcon#read 6, iclass 12, count 2 2006.280.08:16:26.09#ibcon#end of sib2, iclass 12, count 2 2006.280.08:16:26.09#ibcon#*after write, iclass 12, count 2 2006.280.08:16:26.09#ibcon#*before return 0, iclass 12, count 2 2006.280.08:16:26.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:26.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:16:26.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:16:26.09#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:26.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:26.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:26.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:26.21#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:16:26.21#ibcon#first serial, iclass 12, count 0 2006.280.08:16:26.21#ibcon#enter sib2, iclass 12, count 0 2006.280.08:16:26.21#ibcon#flushed, iclass 12, count 0 2006.280.08:16:26.21#ibcon#about to write, iclass 12, count 0 2006.280.08:16:26.21#ibcon#wrote, iclass 12, count 0 2006.280.08:16:26.21#ibcon#about to read 3, iclass 12, count 0 2006.280.08:16:26.24#ibcon#read 3, iclass 12, count 0 2006.280.08:16:26.24#ibcon#about to read 4, iclass 12, count 0 2006.280.08:16:26.24#ibcon#read 4, iclass 12, count 0 2006.280.08:16:26.24#ibcon#about to read 5, iclass 12, count 0 2006.280.08:16:26.24#ibcon#read 5, iclass 12, count 0 2006.280.08:16:26.24#ibcon#about to read 6, iclass 12, count 0 2006.280.08:16:26.24#ibcon#read 6, iclass 12, count 0 2006.280.08:16:26.24#ibcon#end of sib2, iclass 12, count 0 2006.280.08:16:26.24#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:16:26.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:16:26.24#ibcon#[27=USB\r\n] 2006.280.08:16:26.24#ibcon#*before write, iclass 12, count 0 2006.280.08:16:26.24#ibcon#enter sib2, iclass 12, count 0 2006.280.08:16:26.24#ibcon#flushed, iclass 12, count 0 2006.280.08:16:26.24#ibcon#about to write, iclass 12, count 0 2006.280.08:16:26.24#ibcon#wrote, iclass 12, count 0 2006.280.08:16:26.24#ibcon#about to read 3, iclass 12, count 0 2006.280.08:16:26.26#ibcon#read 3, iclass 12, count 0 2006.280.08:16:26.26#ibcon#about to read 4, iclass 12, count 0 2006.280.08:16:26.26#ibcon#read 4, iclass 12, count 0 2006.280.08:16:26.26#ibcon#about to read 5, iclass 12, count 0 2006.280.08:16:26.26#ibcon#read 5, iclass 12, count 0 2006.280.08:16:26.26#ibcon#about to read 6, iclass 12, count 0 2006.280.08:16:26.26#ibcon#read 6, iclass 12, count 0 2006.280.08:16:26.26#ibcon#end of sib2, iclass 12, count 0 2006.280.08:16:26.26#ibcon#*after write, iclass 12, count 0 2006.280.08:16:26.26#ibcon#*before return 0, iclass 12, count 0 2006.280.08:16:26.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:26.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:16:26.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:16:26.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:16:26.26$vc4f8/vblo=6,752.99 2006.280.08:16:26.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.08:16:26.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.08:16:26.27#ibcon#ireg 17 cls_cnt 0 2006.280.08:16:26.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:26.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:26.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:26.27#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:16:26.27#ibcon#first serial, iclass 14, count 0 2006.280.08:16:26.27#ibcon#enter sib2, iclass 14, count 0 2006.280.08:16:26.27#ibcon#flushed, iclass 14, count 0 2006.280.08:16:26.27#ibcon#about to write, iclass 14, count 0 2006.280.08:16:26.27#ibcon#wrote, iclass 14, count 0 2006.280.08:16:26.27#ibcon#about to read 3, iclass 14, count 0 2006.280.08:16:26.28#ibcon#read 3, iclass 14, count 0 2006.280.08:16:26.28#ibcon#about to read 4, iclass 14, count 0 2006.280.08:16:26.28#ibcon#read 4, iclass 14, count 0 2006.280.08:16:26.28#ibcon#about to read 5, iclass 14, count 0 2006.280.08:16:26.28#ibcon#read 5, iclass 14, count 0 2006.280.08:16:26.28#ibcon#about to read 6, iclass 14, count 0 2006.280.08:16:26.28#ibcon#read 6, iclass 14, count 0 2006.280.08:16:26.28#ibcon#end of sib2, iclass 14, count 0 2006.280.08:16:26.28#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:16:26.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:16:26.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:16:26.28#ibcon#*before write, iclass 14, count 0 2006.280.08:16:26.28#ibcon#enter sib2, iclass 14, count 0 2006.280.08:16:26.28#ibcon#flushed, iclass 14, count 0 2006.280.08:16:26.28#ibcon#about to write, iclass 14, count 0 2006.280.08:16:26.28#ibcon#wrote, iclass 14, count 0 2006.280.08:16:26.28#ibcon#about to read 3, iclass 14, count 0 2006.280.08:16:26.32#ibcon#read 3, iclass 14, count 0 2006.280.08:16:26.32#ibcon#about to read 4, iclass 14, count 0 2006.280.08:16:26.32#ibcon#read 4, iclass 14, count 0 2006.280.08:16:26.32#ibcon#about to read 5, iclass 14, count 0 2006.280.08:16:26.32#ibcon#read 5, iclass 14, count 0 2006.280.08:16:26.32#ibcon#about to read 6, iclass 14, count 0 2006.280.08:16:26.32#ibcon#read 6, iclass 14, count 0 2006.280.08:16:26.32#ibcon#end of sib2, iclass 14, count 0 2006.280.08:16:26.32#ibcon#*after write, iclass 14, count 0 2006.280.08:16:26.32#ibcon#*before return 0, iclass 14, count 0 2006.280.08:16:26.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:26.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:16:26.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:16:26.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:16:26.32$vc4f8/vb=6,4 2006.280.08:16:26.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.08:16:26.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.08:16:26.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:16:26.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:26.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:26.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:26.37#ibcon#enter wrdev, iclass 16, count 2 2006.280.08:16:26.37#ibcon#first serial, iclass 16, count 2 2006.280.08:16:26.37#ibcon#enter sib2, iclass 16, count 2 2006.280.08:16:26.37#ibcon#flushed, iclass 16, count 2 2006.280.08:16:26.37#ibcon#about to write, iclass 16, count 2 2006.280.08:16:26.37#ibcon#wrote, iclass 16, count 2 2006.280.08:16:26.37#ibcon#about to read 3, iclass 16, count 2 2006.280.08:16:26.39#ibcon#read 3, iclass 16, count 2 2006.280.08:16:26.39#ibcon#about to read 4, iclass 16, count 2 2006.280.08:16:26.39#ibcon#read 4, iclass 16, count 2 2006.280.08:16:26.39#ibcon#about to read 5, iclass 16, count 2 2006.280.08:16:26.39#ibcon#read 5, iclass 16, count 2 2006.280.08:16:26.39#ibcon#about to read 6, iclass 16, count 2 2006.280.08:16:26.39#ibcon#read 6, iclass 16, count 2 2006.280.08:16:26.39#ibcon#end of sib2, iclass 16, count 2 2006.280.08:16:26.39#ibcon#*mode == 0, iclass 16, count 2 2006.280.08:16:26.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.08:16:26.39#ibcon#[27=AT06-04\r\n] 2006.280.08:16:26.39#ibcon#*before write, iclass 16, count 2 2006.280.08:16:26.39#ibcon#enter sib2, iclass 16, count 2 2006.280.08:16:26.39#ibcon#flushed, iclass 16, count 2 2006.280.08:16:26.39#ibcon#about to write, iclass 16, count 2 2006.280.08:16:26.39#ibcon#wrote, iclass 16, count 2 2006.280.08:16:26.39#ibcon#about to read 3, iclass 16, count 2 2006.280.08:16:26.42#ibcon#read 3, iclass 16, count 2 2006.280.08:16:26.42#ibcon#about to read 4, iclass 16, count 2 2006.280.08:16:26.42#ibcon#read 4, iclass 16, count 2 2006.280.08:16:26.42#ibcon#about to read 5, iclass 16, count 2 2006.280.08:16:26.42#ibcon#read 5, iclass 16, count 2 2006.280.08:16:26.42#ibcon#about to read 6, iclass 16, count 2 2006.280.08:16:26.42#ibcon#read 6, iclass 16, count 2 2006.280.08:16:26.42#ibcon#end of sib2, iclass 16, count 2 2006.280.08:16:26.42#ibcon#*after write, iclass 16, count 2 2006.280.08:16:26.42#ibcon#*before return 0, iclass 16, count 2 2006.280.08:16:26.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:26.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:16:26.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.08:16:26.42#ibcon#ireg 7 cls_cnt 0 2006.280.08:16:26.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:26.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:26.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:26.55#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:16:26.55#ibcon#first serial, iclass 16, count 0 2006.280.08:16:26.55#ibcon#enter sib2, iclass 16, count 0 2006.280.08:16:26.55#ibcon#flushed, iclass 16, count 0 2006.280.08:16:26.55#ibcon#about to write, iclass 16, count 0 2006.280.08:16:26.55#ibcon#wrote, iclass 16, count 0 2006.280.08:16:26.55#ibcon#about to read 3, iclass 16, count 0 2006.280.08:16:26.57#ibcon#read 3, iclass 16, count 0 2006.280.08:16:26.57#ibcon#about to read 4, iclass 16, count 0 2006.280.08:16:26.57#ibcon#read 4, iclass 16, count 0 2006.280.08:16:26.57#ibcon#about to read 5, iclass 16, count 0 2006.280.08:16:26.57#ibcon#read 5, iclass 16, count 0 2006.280.08:16:26.57#ibcon#about to read 6, iclass 16, count 0 2006.280.08:16:26.57#ibcon#read 6, iclass 16, count 0 2006.280.08:16:26.57#ibcon#end of sib2, iclass 16, count 0 2006.280.08:16:26.57#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:16:26.57#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:16:26.57#ibcon#[27=USB\r\n] 2006.280.08:16:26.57#ibcon#*before write, iclass 16, count 0 2006.280.08:16:26.57#ibcon#enter sib2, iclass 16, count 0 2006.280.08:16:26.57#ibcon#flushed, iclass 16, count 0 2006.280.08:16:26.57#ibcon#about to write, iclass 16, count 0 2006.280.08:16:26.57#ibcon#wrote, iclass 16, count 0 2006.280.08:16:26.57#ibcon#about to read 3, iclass 16, count 0 2006.280.08:16:26.59#ibcon#read 3, iclass 16, count 0 2006.280.08:16:26.59#ibcon#about to read 4, iclass 16, count 0 2006.280.08:16:26.59#ibcon#read 4, iclass 16, count 0 2006.280.08:16:26.59#ibcon#about to read 5, iclass 16, count 0 2006.280.08:16:26.59#ibcon#read 5, iclass 16, count 0 2006.280.08:16:26.59#ibcon#about to read 6, iclass 16, count 0 2006.280.08:16:26.59#ibcon#read 6, iclass 16, count 0 2006.280.08:16:26.59#ibcon#end of sib2, iclass 16, count 0 2006.280.08:16:26.59#ibcon#*after write, iclass 16, count 0 2006.280.08:16:26.59#ibcon#*before return 0, iclass 16, count 0 2006.280.08:16:26.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:26.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:16:26.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:16:26.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:16:26.59$vc4f8/vabw=wide 2006.280.08:16:26.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:16:26.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:16:26.60#ibcon#ireg 8 cls_cnt 0 2006.280.08:16:26.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:26.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:26.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:26.60#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:16:26.60#ibcon#first serial, iclass 18, count 0 2006.280.08:16:26.60#ibcon#enter sib2, iclass 18, count 0 2006.280.08:16:26.60#ibcon#flushed, iclass 18, count 0 2006.280.08:16:26.60#ibcon#about to write, iclass 18, count 0 2006.280.08:16:26.60#ibcon#wrote, iclass 18, count 0 2006.280.08:16:26.60#ibcon#about to read 3, iclass 18, count 0 2006.280.08:16:26.62#ibcon#read 3, iclass 18, count 0 2006.280.08:16:26.62#ibcon#about to read 4, iclass 18, count 0 2006.280.08:16:26.62#ibcon#read 4, iclass 18, count 0 2006.280.08:16:26.62#ibcon#about to read 5, iclass 18, count 0 2006.280.08:16:26.62#ibcon#read 5, iclass 18, count 0 2006.280.08:16:26.62#ibcon#about to read 6, iclass 18, count 0 2006.280.08:16:26.62#ibcon#read 6, iclass 18, count 0 2006.280.08:16:26.62#ibcon#end of sib2, iclass 18, count 0 2006.280.08:16:26.62#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:16:26.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:16:26.62#ibcon#[25=BW32\r\n] 2006.280.08:16:26.62#ibcon#*before write, iclass 18, count 0 2006.280.08:16:26.62#ibcon#enter sib2, iclass 18, count 0 2006.280.08:16:26.62#ibcon#flushed, iclass 18, count 0 2006.280.08:16:26.62#ibcon#about to write, iclass 18, count 0 2006.280.08:16:26.62#ibcon#wrote, iclass 18, count 0 2006.280.08:16:26.62#ibcon#about to read 3, iclass 18, count 0 2006.280.08:16:26.64#ibcon#read 3, iclass 18, count 0 2006.280.08:16:26.64#ibcon#about to read 4, iclass 18, count 0 2006.280.08:16:26.64#ibcon#read 4, iclass 18, count 0 2006.280.08:16:26.64#ibcon#about to read 5, iclass 18, count 0 2006.280.08:16:26.64#ibcon#read 5, iclass 18, count 0 2006.280.08:16:26.64#ibcon#about to read 6, iclass 18, count 0 2006.280.08:16:26.64#ibcon#read 6, iclass 18, count 0 2006.280.08:16:26.64#ibcon#end of sib2, iclass 18, count 0 2006.280.08:16:26.64#ibcon#*after write, iclass 18, count 0 2006.280.08:16:26.64#ibcon#*before return 0, iclass 18, count 0 2006.280.08:16:26.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:26.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:16:26.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:16:26.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:16:26.65$vc4f8/vbbw=wide 2006.280.08:16:26.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:16:26.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:16:26.65#ibcon#ireg 8 cls_cnt 0 2006.280.08:16:26.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:16:26.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:16:26.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:16:26.70#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:16:26.70#ibcon#first serial, iclass 20, count 0 2006.280.08:16:26.70#ibcon#enter sib2, iclass 20, count 0 2006.280.08:16:26.70#ibcon#flushed, iclass 20, count 0 2006.280.08:16:26.70#ibcon#about to write, iclass 20, count 0 2006.280.08:16:26.70#ibcon#wrote, iclass 20, count 0 2006.280.08:16:26.70#ibcon#about to read 3, iclass 20, count 0 2006.280.08:16:26.72#ibcon#read 3, iclass 20, count 0 2006.280.08:16:26.72#ibcon#about to read 4, iclass 20, count 0 2006.280.08:16:26.72#ibcon#read 4, iclass 20, count 0 2006.280.08:16:26.72#ibcon#about to read 5, iclass 20, count 0 2006.280.08:16:26.72#ibcon#read 5, iclass 20, count 0 2006.280.08:16:26.72#ibcon#about to read 6, iclass 20, count 0 2006.280.08:16:26.72#ibcon#read 6, iclass 20, count 0 2006.280.08:16:26.72#ibcon#end of sib2, iclass 20, count 0 2006.280.08:16:26.72#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:16:26.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:16:26.72#ibcon#[27=BW32\r\n] 2006.280.08:16:26.72#ibcon#*before write, iclass 20, count 0 2006.280.08:16:26.72#ibcon#enter sib2, iclass 20, count 0 2006.280.08:16:26.72#ibcon#flushed, iclass 20, count 0 2006.280.08:16:26.72#ibcon#about to write, iclass 20, count 0 2006.280.08:16:26.72#ibcon#wrote, iclass 20, count 0 2006.280.08:16:26.72#ibcon#about to read 3, iclass 20, count 0 2006.280.08:16:26.76#ibcon#read 3, iclass 20, count 0 2006.280.08:16:26.76#ibcon#about to read 4, iclass 20, count 0 2006.280.08:16:26.76#ibcon#read 4, iclass 20, count 0 2006.280.08:16:26.76#ibcon#about to read 5, iclass 20, count 0 2006.280.08:16:26.76#ibcon#read 5, iclass 20, count 0 2006.280.08:16:26.76#ibcon#about to read 6, iclass 20, count 0 2006.280.08:16:26.76#ibcon#read 6, iclass 20, count 0 2006.280.08:16:26.76#ibcon#end of sib2, iclass 20, count 0 2006.280.08:16:26.76#ibcon#*after write, iclass 20, count 0 2006.280.08:16:26.76#ibcon#*before return 0, iclass 20, count 0 2006.280.08:16:26.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:16:26.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:16:26.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:16:26.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:16:26.76$4f8m12a/ifd4f 2006.280.08:16:26.76$ifd4f/lo= 2006.280.08:16:26.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:16:26.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:16:26.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:16:26.76$ifd4f/patch= 2006.280.08:16:26.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:16:26.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:16:26.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:16:26.76$4f8m12a/"form=m,16.000,1:2 2006.280.08:16:26.76$4f8m12a/"tpicd 2006.280.08:16:26.76$4f8m12a/echo=off 2006.280.08:16:26.76$4f8m12a/xlog=off 2006.280.08:16:26.76:!2006.280.08:16:50 2006.280.08:16:33.13#trakl#Source acquired 2006.280.08:16:35.13#flagr#flagr/antenna,acquired 2006.280.08:16:50.01:preob 2006.280.08:16:51.13/onsource/TRACKING 2006.280.08:16:51.14:!2006.280.08:17:00 2006.280.08:17:00.01:data_valid=on 2006.280.08:17:00.02:midob 2006.280.08:17:01.13/onsource/TRACKING 2006.280.08:17:01.14/wx/20.38,987.6,64 2006.280.08:17:01.34/cable/+6.4843E-03 2006.280.08:17:02.43/va/01,07,usb,yes,36,38 2006.280.08:17:02.43/va/02,06,usb,yes,33,35 2006.280.08:17:02.43/va/03,06,usb,yes,32,32 2006.280.08:17:02.43/va/04,06,usb,yes,35,37 2006.280.08:17:02.43/va/05,07,usb,yes,33,35 2006.280.08:17:02.43/va/06,06,usb,yes,32,32 2006.280.08:17:02.43/va/07,06,usb,yes,32,32 2006.280.08:17:02.43/va/08,06,usb,yes,34,34 2006.280.08:17:02.66/valo/01,532.99,yes,locked 2006.280.08:17:02.66/valo/02,572.99,yes,locked 2006.280.08:17:02.66/valo/03,672.99,yes,locked 2006.280.08:17:02.66/valo/04,832.99,yes,locked 2006.280.08:17:02.66/valo/05,652.99,yes,locked 2006.280.08:17:02.66/valo/06,772.99,yes,locked 2006.280.08:17:02.66/valo/07,832.99,yes,locked 2006.280.08:17:02.66/valo/08,852.99,yes,locked 2006.280.08:17:03.75/vb/01,04,usb,yes,27,26 2006.280.08:17:03.75/vb/02,05,usb,yes,25,27 2006.280.08:17:03.75/vb/03,04,usb,yes,26,29 2006.280.08:17:03.75/vb/04,04,usb,yes,26,26 2006.280.08:17:03.75/vb/05,04,usb,yes,24,28 2006.280.08:17:03.75/vb/06,04,usb,yes,25,28 2006.280.08:17:03.75/vb/07,04,usb,yes,27,27 2006.280.08:17:03.75/vb/08,04,usb,yes,25,28 2006.280.08:17:03.99/vblo/01,632.99,yes,locked 2006.280.08:17:03.99/vblo/02,640.99,yes,locked 2006.280.08:17:03.99/vblo/03,656.99,yes,locked 2006.280.08:17:03.99/vblo/04,712.99,yes,locked 2006.280.08:17:03.99/vblo/05,744.99,yes,locked 2006.280.08:17:03.99/vblo/06,752.99,yes,locked 2006.280.08:17:03.99/vblo/07,734.99,yes,locked 2006.280.08:17:03.99/vblo/08,744.99,yes,locked 2006.280.08:17:04.14/vabw/8 2006.280.08:17:04.29/vbbw/8 2006.280.08:17:04.38/xfe/off,on,12.0 2006.280.08:17:04.75/ifatt/23,28,28,28 2006.280.08:17:05.07/fmout-gps/S +3.14E-07 2006.280.08:17:05.09:!2006.280.08:18:00 2006.280.08:18:00.01:data_valid=off 2006.280.08:18:00.02:postob 2006.280.08:18:00.18/cable/+6.4841E-03 2006.280.08:18:00.18/wx/20.36,987.6,64 2006.280.08:18:01.07/fmout-gps/S +3.16E-07 2006.280.08:18:01.07:scan_name=280-0820,k06280,60 2006.280.08:18:01.07:source=1538+149,154049.49,144745.9,2000.0,ccw 2006.280.08:18:02.13#flagr#flagr/antenna,new-source 2006.280.08:18:02.14:checkk5 2006.280.08:18:02.62/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:18:03.09/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:18:03.95/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:18:04.39/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:18:04.93/chk_obsdata//k5ts1/T2800817??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:18:08.73/chk_obsdata//k5ts2/T2800817??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:18:09.14/chk_obsdata//k5ts3/T2800817??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:18:10.02/chk_obsdata//k5ts4/T2800817??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.280.08:18:10.94/k5log//k5ts1_log_newline 2006.280.08:18:12.04/k5log//k5ts2_log_newline 2006.280.08:18:13.17/k5log//k5ts3_log_newline 2006.280.08:18:14.28/k5log//k5ts4_log_newline 2006.280.08:18:14.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:18:14.30:4f8m12a=3 2006.280.08:18:14.30$4f8m12a/echo=on 2006.280.08:18:14.30$4f8m12a/pcalon 2006.280.08:18:14.30$pcalon/"no phase cal control is implemented here 2006.280.08:18:14.30$4f8m12a/"tpicd=stop 2006.280.08:18:14.30$4f8m12a/vc4f8 2006.280.08:18:14.30$vc4f8/valo=1,532.99 2006.280.08:18:14.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:18:14.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:18:14.31#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:14.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:14.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:14.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:14.31#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:18:14.31#ibcon#first serial, iclass 22, count 0 2006.280.08:18:14.31#ibcon#enter sib2, iclass 22, count 0 2006.280.08:18:14.31#ibcon#flushed, iclass 22, count 0 2006.280.08:18:14.31#ibcon#about to write, iclass 22, count 0 2006.280.08:18:14.31#ibcon#wrote, iclass 22, count 0 2006.280.08:18:14.31#ibcon#about to read 3, iclass 22, count 0 2006.280.08:18:14.32#ibcon#read 3, iclass 22, count 0 2006.280.08:18:14.32#ibcon#about to read 4, iclass 22, count 0 2006.280.08:18:14.32#ibcon#read 4, iclass 22, count 0 2006.280.08:18:14.32#ibcon#about to read 5, iclass 22, count 0 2006.280.08:18:14.32#ibcon#read 5, iclass 22, count 0 2006.280.08:18:14.32#ibcon#about to read 6, iclass 22, count 0 2006.280.08:18:14.32#ibcon#read 6, iclass 22, count 0 2006.280.08:18:14.32#ibcon#end of sib2, iclass 22, count 0 2006.280.08:18:14.32#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:18:14.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:18:14.32#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:18:14.32#ibcon#*before write, iclass 22, count 0 2006.280.08:18:14.32#ibcon#enter sib2, iclass 22, count 0 2006.280.08:18:14.32#ibcon#flushed, iclass 22, count 0 2006.280.08:18:14.32#ibcon#about to write, iclass 22, count 0 2006.280.08:18:14.32#ibcon#wrote, iclass 22, count 0 2006.280.08:18:14.32#ibcon#about to read 3, iclass 22, count 0 2006.280.08:18:14.37#ibcon#read 3, iclass 22, count 0 2006.280.08:18:14.37#ibcon#about to read 4, iclass 22, count 0 2006.280.08:18:14.37#ibcon#read 4, iclass 22, count 0 2006.280.08:18:14.37#ibcon#about to read 5, iclass 22, count 0 2006.280.08:18:14.37#ibcon#read 5, iclass 22, count 0 2006.280.08:18:14.37#ibcon#about to read 6, iclass 22, count 0 2006.280.08:18:14.37#ibcon#read 6, iclass 22, count 0 2006.280.08:18:14.37#ibcon#end of sib2, iclass 22, count 0 2006.280.08:18:14.37#ibcon#*after write, iclass 22, count 0 2006.280.08:18:14.37#ibcon#*before return 0, iclass 22, count 0 2006.280.08:18:14.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:14.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:14.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:18:14.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:18:14.37$vc4f8/va=1,7 2006.280.08:18:14.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:18:14.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:18:14.39#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:14.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:14.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:14.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:14.39#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:18:14.39#ibcon#first serial, iclass 24, count 2 2006.280.08:18:14.39#ibcon#enter sib2, iclass 24, count 2 2006.280.08:18:14.39#ibcon#flushed, iclass 24, count 2 2006.280.08:18:14.39#ibcon#about to write, iclass 24, count 2 2006.280.08:18:14.39#ibcon#wrote, iclass 24, count 2 2006.280.08:18:14.39#ibcon#about to read 3, iclass 24, count 2 2006.280.08:18:14.40#ibcon#read 3, iclass 24, count 2 2006.280.08:18:14.40#ibcon#about to read 4, iclass 24, count 2 2006.280.08:18:14.40#ibcon#read 4, iclass 24, count 2 2006.280.08:18:14.40#ibcon#about to read 5, iclass 24, count 2 2006.280.08:18:14.40#ibcon#read 5, iclass 24, count 2 2006.280.08:18:14.40#ibcon#about to read 6, iclass 24, count 2 2006.280.08:18:14.40#ibcon#read 6, iclass 24, count 2 2006.280.08:18:14.40#ibcon#end of sib2, iclass 24, count 2 2006.280.08:18:14.40#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:18:14.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:18:14.40#ibcon#[25=AT01-07\r\n] 2006.280.08:18:14.40#ibcon#*before write, iclass 24, count 2 2006.280.08:18:14.40#ibcon#enter sib2, iclass 24, count 2 2006.280.08:18:14.40#ibcon#flushed, iclass 24, count 2 2006.280.08:18:14.40#ibcon#about to write, iclass 24, count 2 2006.280.08:18:14.40#ibcon#wrote, iclass 24, count 2 2006.280.08:18:14.40#ibcon#about to read 3, iclass 24, count 2 2006.280.08:18:14.43#ibcon#read 3, iclass 24, count 2 2006.280.08:18:14.43#ibcon#about to read 4, iclass 24, count 2 2006.280.08:18:14.43#ibcon#read 4, iclass 24, count 2 2006.280.08:18:14.43#ibcon#about to read 5, iclass 24, count 2 2006.280.08:18:14.43#ibcon#read 5, iclass 24, count 2 2006.280.08:18:14.43#ibcon#about to read 6, iclass 24, count 2 2006.280.08:18:14.43#ibcon#read 6, iclass 24, count 2 2006.280.08:18:14.43#ibcon#end of sib2, iclass 24, count 2 2006.280.08:18:14.43#ibcon#*after write, iclass 24, count 2 2006.280.08:18:14.43#ibcon#*before return 0, iclass 24, count 2 2006.280.08:18:14.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:14.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:14.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:18:14.43#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:14.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:14.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:14.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:14.56#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:18:14.56#ibcon#first serial, iclass 24, count 0 2006.280.08:18:14.56#ibcon#enter sib2, iclass 24, count 0 2006.280.08:18:14.56#ibcon#flushed, iclass 24, count 0 2006.280.08:18:14.56#ibcon#about to write, iclass 24, count 0 2006.280.08:18:14.56#ibcon#wrote, iclass 24, count 0 2006.280.08:18:14.56#ibcon#about to read 3, iclass 24, count 0 2006.280.08:18:14.57#ibcon#read 3, iclass 24, count 0 2006.280.08:18:14.57#ibcon#about to read 4, iclass 24, count 0 2006.280.08:18:14.57#ibcon#read 4, iclass 24, count 0 2006.280.08:18:14.57#ibcon#about to read 5, iclass 24, count 0 2006.280.08:18:14.57#ibcon#read 5, iclass 24, count 0 2006.280.08:18:14.57#ibcon#about to read 6, iclass 24, count 0 2006.280.08:18:14.57#ibcon#read 6, iclass 24, count 0 2006.280.08:18:14.57#ibcon#end of sib2, iclass 24, count 0 2006.280.08:18:14.57#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:18:14.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:18:14.57#ibcon#[25=USB\r\n] 2006.280.08:18:14.57#ibcon#*before write, iclass 24, count 0 2006.280.08:18:14.57#ibcon#enter sib2, iclass 24, count 0 2006.280.08:18:14.57#ibcon#flushed, iclass 24, count 0 2006.280.08:18:14.58#ibcon#about to write, iclass 24, count 0 2006.280.08:18:14.58#ibcon#wrote, iclass 24, count 0 2006.280.08:18:14.58#ibcon#about to read 3, iclass 24, count 0 2006.280.08:18:14.60#ibcon#read 3, iclass 24, count 0 2006.280.08:18:14.60#ibcon#about to read 4, iclass 24, count 0 2006.280.08:18:14.60#ibcon#read 4, iclass 24, count 0 2006.280.08:18:14.60#ibcon#about to read 5, iclass 24, count 0 2006.280.08:18:14.60#ibcon#read 5, iclass 24, count 0 2006.280.08:18:14.60#ibcon#about to read 6, iclass 24, count 0 2006.280.08:18:14.60#ibcon#read 6, iclass 24, count 0 2006.280.08:18:14.60#ibcon#end of sib2, iclass 24, count 0 2006.280.08:18:14.60#ibcon#*after write, iclass 24, count 0 2006.280.08:18:14.60#ibcon#*before return 0, iclass 24, count 0 2006.280.08:18:14.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:14.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:14.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:18:14.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:18:14.60$vc4f8/valo=2,572.99 2006.280.08:18:14.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:18:14.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:18:14.60#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:14.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:14.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:14.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:14.60#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:18:14.60#ibcon#first serial, iclass 26, count 0 2006.280.08:18:14.60#ibcon#enter sib2, iclass 26, count 0 2006.280.08:18:14.60#ibcon#flushed, iclass 26, count 0 2006.280.08:18:14.60#ibcon#about to write, iclass 26, count 0 2006.280.08:18:14.60#ibcon#wrote, iclass 26, count 0 2006.280.08:18:14.60#ibcon#about to read 3, iclass 26, count 0 2006.280.08:18:14.62#ibcon#read 3, iclass 26, count 0 2006.280.08:18:14.62#ibcon#about to read 4, iclass 26, count 0 2006.280.08:18:14.62#ibcon#read 4, iclass 26, count 0 2006.280.08:18:14.62#ibcon#about to read 5, iclass 26, count 0 2006.280.08:18:14.62#ibcon#read 5, iclass 26, count 0 2006.280.08:18:14.62#ibcon#about to read 6, iclass 26, count 0 2006.280.08:18:14.62#ibcon#read 6, iclass 26, count 0 2006.280.08:18:14.62#ibcon#end of sib2, iclass 26, count 0 2006.280.08:18:14.62#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:18:14.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:18:14.62#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:18:14.62#ibcon#*before write, iclass 26, count 0 2006.280.08:18:14.62#ibcon#enter sib2, iclass 26, count 0 2006.280.08:18:14.62#ibcon#flushed, iclass 26, count 0 2006.280.08:18:14.62#ibcon#about to write, iclass 26, count 0 2006.280.08:18:14.62#ibcon#wrote, iclass 26, count 0 2006.280.08:18:14.62#ibcon#about to read 3, iclass 26, count 0 2006.280.08:18:14.66#ibcon#read 3, iclass 26, count 0 2006.280.08:18:14.66#ibcon#about to read 4, iclass 26, count 0 2006.280.08:18:14.66#ibcon#read 4, iclass 26, count 0 2006.280.08:18:14.66#ibcon#about to read 5, iclass 26, count 0 2006.280.08:18:14.66#ibcon#read 5, iclass 26, count 0 2006.280.08:18:14.66#ibcon#about to read 6, iclass 26, count 0 2006.280.08:18:14.67#ibcon#read 6, iclass 26, count 0 2006.280.08:18:14.67#ibcon#end of sib2, iclass 26, count 0 2006.280.08:18:14.67#ibcon#*after write, iclass 26, count 0 2006.280.08:18:14.67#ibcon#*before return 0, iclass 26, count 0 2006.280.08:18:14.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:14.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:14.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:18:14.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:18:14.67$vc4f8/va=2,6 2006.280.08:18:14.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:18:14.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:18:14.67#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:14.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:14.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:14.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:14.71#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:18:14.71#ibcon#first serial, iclass 28, count 2 2006.280.08:18:14.71#ibcon#enter sib2, iclass 28, count 2 2006.280.08:18:14.71#ibcon#flushed, iclass 28, count 2 2006.280.08:18:14.71#ibcon#about to write, iclass 28, count 2 2006.280.08:18:14.71#ibcon#wrote, iclass 28, count 2 2006.280.08:18:14.71#ibcon#about to read 3, iclass 28, count 2 2006.280.08:18:14.73#ibcon#read 3, iclass 28, count 2 2006.280.08:18:14.73#ibcon#about to read 4, iclass 28, count 2 2006.280.08:18:14.73#ibcon#read 4, iclass 28, count 2 2006.280.08:18:14.73#ibcon#about to read 5, iclass 28, count 2 2006.280.08:18:14.73#ibcon#read 5, iclass 28, count 2 2006.280.08:18:14.73#ibcon#about to read 6, iclass 28, count 2 2006.280.08:18:14.73#ibcon#read 6, iclass 28, count 2 2006.280.08:18:14.73#ibcon#end of sib2, iclass 28, count 2 2006.280.08:18:14.73#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:18:14.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:18:14.73#ibcon#[25=AT02-06\r\n] 2006.280.08:18:14.73#ibcon#*before write, iclass 28, count 2 2006.280.08:18:14.73#ibcon#enter sib2, iclass 28, count 2 2006.280.08:18:14.73#ibcon#flushed, iclass 28, count 2 2006.280.08:18:14.73#ibcon#about to write, iclass 28, count 2 2006.280.08:18:14.73#ibcon#wrote, iclass 28, count 2 2006.280.08:18:14.73#ibcon#about to read 3, iclass 28, count 2 2006.280.08:18:14.77#ibcon#read 3, iclass 28, count 2 2006.280.08:18:14.77#ibcon#about to read 4, iclass 28, count 2 2006.280.08:18:14.77#ibcon#read 4, iclass 28, count 2 2006.280.08:18:14.77#ibcon#about to read 5, iclass 28, count 2 2006.280.08:18:14.77#ibcon#read 5, iclass 28, count 2 2006.280.08:18:14.77#ibcon#about to read 6, iclass 28, count 2 2006.280.08:18:14.77#ibcon#read 6, iclass 28, count 2 2006.280.08:18:14.77#ibcon#end of sib2, iclass 28, count 2 2006.280.08:18:14.77#ibcon#*after write, iclass 28, count 2 2006.280.08:18:14.77#ibcon#*before return 0, iclass 28, count 2 2006.280.08:18:14.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:14.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:14.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:18:14.77#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:14.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:14.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:14.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:14.89#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:18:14.89#ibcon#first serial, iclass 28, count 0 2006.280.08:18:14.89#ibcon#enter sib2, iclass 28, count 0 2006.280.08:18:14.89#ibcon#flushed, iclass 28, count 0 2006.280.08:18:14.89#ibcon#about to write, iclass 28, count 0 2006.280.08:18:14.89#ibcon#wrote, iclass 28, count 0 2006.280.08:18:14.89#ibcon#about to read 3, iclass 28, count 0 2006.280.08:18:14.90#ibcon#read 3, iclass 28, count 0 2006.280.08:18:14.90#ibcon#about to read 4, iclass 28, count 0 2006.280.08:18:14.90#ibcon#read 4, iclass 28, count 0 2006.280.08:18:14.90#ibcon#about to read 5, iclass 28, count 0 2006.280.08:18:14.90#ibcon#read 5, iclass 28, count 0 2006.280.08:18:14.90#ibcon#about to read 6, iclass 28, count 0 2006.280.08:18:14.90#ibcon#read 6, iclass 28, count 0 2006.280.08:18:14.90#ibcon#end of sib2, iclass 28, count 0 2006.280.08:18:14.90#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:18:14.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:18:14.90#ibcon#[25=USB\r\n] 2006.280.08:18:14.90#ibcon#*before write, iclass 28, count 0 2006.280.08:18:14.90#ibcon#enter sib2, iclass 28, count 0 2006.280.08:18:14.90#ibcon#flushed, iclass 28, count 0 2006.280.08:18:14.90#ibcon#about to write, iclass 28, count 0 2006.280.08:18:14.90#ibcon#wrote, iclass 28, count 0 2006.280.08:18:14.90#ibcon#about to read 3, iclass 28, count 0 2006.280.08:18:14.93#ibcon#read 3, iclass 28, count 0 2006.280.08:18:14.93#ibcon#about to read 4, iclass 28, count 0 2006.280.08:18:14.93#ibcon#read 4, iclass 28, count 0 2006.280.08:18:14.93#ibcon#about to read 5, iclass 28, count 0 2006.280.08:18:14.93#ibcon#read 5, iclass 28, count 0 2006.280.08:18:14.93#ibcon#about to read 6, iclass 28, count 0 2006.280.08:18:14.93#ibcon#read 6, iclass 28, count 0 2006.280.08:18:14.93#ibcon#end of sib2, iclass 28, count 0 2006.280.08:18:14.93#ibcon#*after write, iclass 28, count 0 2006.280.08:18:14.93#ibcon#*before return 0, iclass 28, count 0 2006.280.08:18:14.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:14.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:14.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:18:14.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:18:14.93$vc4f8/valo=3,672.99 2006.280.08:18:14.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:18:14.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:18:14.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:14.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:14.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:14.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:14.93#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:18:14.93#ibcon#first serial, iclass 30, count 0 2006.280.08:18:14.93#ibcon#enter sib2, iclass 30, count 0 2006.280.08:18:14.93#ibcon#flushed, iclass 30, count 0 2006.280.08:18:14.93#ibcon#about to write, iclass 30, count 0 2006.280.08:18:14.93#ibcon#wrote, iclass 30, count 0 2006.280.08:18:14.93#ibcon#about to read 3, iclass 30, count 0 2006.280.08:18:14.95#ibcon#read 3, iclass 30, count 0 2006.280.08:18:14.95#ibcon#about to read 4, iclass 30, count 0 2006.280.08:18:14.95#ibcon#read 4, iclass 30, count 0 2006.280.08:18:14.95#ibcon#about to read 5, iclass 30, count 0 2006.280.08:18:14.95#ibcon#read 5, iclass 30, count 0 2006.280.08:18:14.95#ibcon#about to read 6, iclass 30, count 0 2006.280.08:18:14.95#ibcon#read 6, iclass 30, count 0 2006.280.08:18:14.95#ibcon#end of sib2, iclass 30, count 0 2006.280.08:18:14.95#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:18:14.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:18:14.95#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:18:14.95#ibcon#*before write, iclass 30, count 0 2006.280.08:18:14.95#ibcon#enter sib2, iclass 30, count 0 2006.280.08:18:14.95#ibcon#flushed, iclass 30, count 0 2006.280.08:18:14.95#ibcon#about to write, iclass 30, count 0 2006.280.08:18:14.95#ibcon#wrote, iclass 30, count 0 2006.280.08:18:14.95#ibcon#about to read 3, iclass 30, count 0 2006.280.08:18:14.99#ibcon#read 3, iclass 30, count 0 2006.280.08:18:14.99#ibcon#about to read 4, iclass 30, count 0 2006.280.08:18:14.99#ibcon#read 4, iclass 30, count 0 2006.280.08:18:14.99#ibcon#about to read 5, iclass 30, count 0 2006.280.08:18:14.99#ibcon#read 5, iclass 30, count 0 2006.280.08:18:14.99#ibcon#about to read 6, iclass 30, count 0 2006.280.08:18:14.99#ibcon#read 6, iclass 30, count 0 2006.280.08:18:14.99#ibcon#end of sib2, iclass 30, count 0 2006.280.08:18:14.99#ibcon#*after write, iclass 30, count 0 2006.280.08:18:14.99#ibcon#*before return 0, iclass 30, count 0 2006.280.08:18:14.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:14.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:14.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:18:14.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:18:15.00$vc4f8/va=3,6 2006.280.08:18:15.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:18:15.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:18:15.00#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:15.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:15.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:15.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:15.04#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:18:15.04#ibcon#first serial, iclass 32, count 2 2006.280.08:18:15.04#ibcon#enter sib2, iclass 32, count 2 2006.280.08:18:15.04#ibcon#flushed, iclass 32, count 2 2006.280.08:18:15.04#ibcon#about to write, iclass 32, count 2 2006.280.08:18:15.04#ibcon#wrote, iclass 32, count 2 2006.280.08:18:15.04#ibcon#about to read 3, iclass 32, count 2 2006.280.08:18:15.06#ibcon#read 3, iclass 32, count 2 2006.280.08:18:15.06#ibcon#about to read 4, iclass 32, count 2 2006.280.08:18:15.06#ibcon#read 4, iclass 32, count 2 2006.280.08:18:15.06#ibcon#about to read 5, iclass 32, count 2 2006.280.08:18:15.06#ibcon#read 5, iclass 32, count 2 2006.280.08:18:15.06#ibcon#about to read 6, iclass 32, count 2 2006.280.08:18:15.06#ibcon#read 6, iclass 32, count 2 2006.280.08:18:15.06#ibcon#end of sib2, iclass 32, count 2 2006.280.08:18:15.06#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:18:15.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:18:15.06#ibcon#[25=AT03-06\r\n] 2006.280.08:18:15.06#ibcon#*before write, iclass 32, count 2 2006.280.08:18:15.06#ibcon#enter sib2, iclass 32, count 2 2006.280.08:18:15.06#ibcon#flushed, iclass 32, count 2 2006.280.08:18:15.06#ibcon#about to write, iclass 32, count 2 2006.280.08:18:15.06#ibcon#wrote, iclass 32, count 2 2006.280.08:18:15.06#ibcon#about to read 3, iclass 32, count 2 2006.280.08:18:15.10#ibcon#read 3, iclass 32, count 2 2006.280.08:18:15.10#ibcon#about to read 4, iclass 32, count 2 2006.280.08:18:15.10#ibcon#read 4, iclass 32, count 2 2006.280.08:18:15.10#ibcon#about to read 5, iclass 32, count 2 2006.280.08:18:15.10#ibcon#read 5, iclass 32, count 2 2006.280.08:18:15.10#ibcon#about to read 6, iclass 32, count 2 2006.280.08:18:15.10#ibcon#read 6, iclass 32, count 2 2006.280.08:18:15.10#ibcon#end of sib2, iclass 32, count 2 2006.280.08:18:15.10#ibcon#*after write, iclass 32, count 2 2006.280.08:18:15.10#ibcon#*before return 0, iclass 32, count 2 2006.280.08:18:15.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:15.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:15.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:18:15.10#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:15.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:15.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:15.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:15.22#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:18:15.22#ibcon#first serial, iclass 32, count 0 2006.280.08:18:15.22#ibcon#enter sib2, iclass 32, count 0 2006.280.08:18:15.22#ibcon#flushed, iclass 32, count 0 2006.280.08:18:15.22#ibcon#about to write, iclass 32, count 0 2006.280.08:18:15.22#ibcon#wrote, iclass 32, count 0 2006.280.08:18:15.22#ibcon#about to read 3, iclass 32, count 0 2006.280.08:18:15.23#ibcon#read 3, iclass 32, count 0 2006.280.08:18:15.23#ibcon#about to read 4, iclass 32, count 0 2006.280.08:18:15.23#ibcon#read 4, iclass 32, count 0 2006.280.08:18:15.23#ibcon#about to read 5, iclass 32, count 0 2006.280.08:18:15.23#ibcon#read 5, iclass 32, count 0 2006.280.08:18:15.23#ibcon#about to read 6, iclass 32, count 0 2006.280.08:18:15.23#ibcon#read 6, iclass 32, count 0 2006.280.08:18:15.23#ibcon#end of sib2, iclass 32, count 0 2006.280.08:18:15.23#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:18:15.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:18:15.23#ibcon#[25=USB\r\n] 2006.280.08:18:15.23#ibcon#*before write, iclass 32, count 0 2006.280.08:18:15.23#ibcon#enter sib2, iclass 32, count 0 2006.280.08:18:15.23#ibcon#flushed, iclass 32, count 0 2006.280.08:18:15.23#ibcon#about to write, iclass 32, count 0 2006.280.08:18:15.23#ibcon#wrote, iclass 32, count 0 2006.280.08:18:15.23#ibcon#about to read 3, iclass 32, count 0 2006.280.08:18:15.26#ibcon#read 3, iclass 32, count 0 2006.280.08:18:15.26#ibcon#about to read 4, iclass 32, count 0 2006.280.08:18:15.26#ibcon#read 4, iclass 32, count 0 2006.280.08:18:15.26#ibcon#about to read 5, iclass 32, count 0 2006.280.08:18:15.26#ibcon#read 5, iclass 32, count 0 2006.280.08:18:15.26#ibcon#about to read 6, iclass 32, count 0 2006.280.08:18:15.26#ibcon#read 6, iclass 32, count 0 2006.280.08:18:15.26#ibcon#end of sib2, iclass 32, count 0 2006.280.08:18:15.26#ibcon#*after write, iclass 32, count 0 2006.280.08:18:15.26#ibcon#*before return 0, iclass 32, count 0 2006.280.08:18:15.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:15.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:15.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:18:15.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:18:15.26$vc4f8/valo=4,832.99 2006.280.08:18:15.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:18:15.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:18:15.26#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:15.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:15.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:15.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:15.26#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:18:15.26#ibcon#first serial, iclass 34, count 0 2006.280.08:18:15.26#ibcon#enter sib2, iclass 34, count 0 2006.280.08:18:15.26#ibcon#flushed, iclass 34, count 0 2006.280.08:18:15.26#ibcon#about to write, iclass 34, count 0 2006.280.08:18:15.26#ibcon#wrote, iclass 34, count 0 2006.280.08:18:15.26#ibcon#about to read 3, iclass 34, count 0 2006.280.08:18:15.28#ibcon#read 3, iclass 34, count 0 2006.280.08:18:15.28#ibcon#about to read 4, iclass 34, count 0 2006.280.08:18:15.28#ibcon#read 4, iclass 34, count 0 2006.280.08:18:15.28#ibcon#about to read 5, iclass 34, count 0 2006.280.08:18:15.28#ibcon#read 5, iclass 34, count 0 2006.280.08:18:15.28#ibcon#about to read 6, iclass 34, count 0 2006.280.08:18:15.28#ibcon#read 6, iclass 34, count 0 2006.280.08:18:15.28#ibcon#end of sib2, iclass 34, count 0 2006.280.08:18:15.28#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:18:15.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:18:15.28#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:18:15.28#ibcon#*before write, iclass 34, count 0 2006.280.08:18:15.28#ibcon#enter sib2, iclass 34, count 0 2006.280.08:18:15.28#ibcon#flushed, iclass 34, count 0 2006.280.08:18:15.28#ibcon#about to write, iclass 34, count 0 2006.280.08:18:15.28#ibcon#wrote, iclass 34, count 0 2006.280.08:18:15.28#ibcon#about to read 3, iclass 34, count 0 2006.280.08:18:15.32#ibcon#read 3, iclass 34, count 0 2006.280.08:18:15.32#ibcon#about to read 4, iclass 34, count 0 2006.280.08:18:15.32#ibcon#read 4, iclass 34, count 0 2006.280.08:18:15.32#ibcon#about to read 5, iclass 34, count 0 2006.280.08:18:15.32#ibcon#read 5, iclass 34, count 0 2006.280.08:18:15.32#ibcon#about to read 6, iclass 34, count 0 2006.280.08:18:15.32#ibcon#read 6, iclass 34, count 0 2006.280.08:18:15.32#ibcon#end of sib2, iclass 34, count 0 2006.280.08:18:15.32#ibcon#*after write, iclass 34, count 0 2006.280.08:18:15.32#ibcon#*before return 0, iclass 34, count 0 2006.280.08:18:15.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:15.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:15.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:18:15.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:18:15.32$vc4f8/va=4,6 2006.280.08:18:15.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:18:15.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:18:15.32#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:15.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:15.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:15.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:15.38#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:18:15.38#ibcon#first serial, iclass 36, count 2 2006.280.08:18:15.38#ibcon#enter sib2, iclass 36, count 2 2006.280.08:18:15.38#ibcon#flushed, iclass 36, count 2 2006.280.08:18:15.38#ibcon#about to write, iclass 36, count 2 2006.280.08:18:15.38#ibcon#wrote, iclass 36, count 2 2006.280.08:18:15.38#ibcon#about to read 3, iclass 36, count 2 2006.280.08:18:15.41#ibcon#read 3, iclass 36, count 2 2006.280.08:18:15.41#ibcon#about to read 4, iclass 36, count 2 2006.280.08:18:15.41#ibcon#read 4, iclass 36, count 2 2006.280.08:18:15.41#ibcon#about to read 5, iclass 36, count 2 2006.280.08:18:15.41#ibcon#read 5, iclass 36, count 2 2006.280.08:18:15.41#ibcon#about to read 6, iclass 36, count 2 2006.280.08:18:15.41#ibcon#read 6, iclass 36, count 2 2006.280.08:18:15.41#ibcon#end of sib2, iclass 36, count 2 2006.280.08:18:15.41#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:18:15.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:18:15.41#ibcon#[25=AT04-06\r\n] 2006.280.08:18:15.41#ibcon#*before write, iclass 36, count 2 2006.280.08:18:15.41#ibcon#enter sib2, iclass 36, count 2 2006.280.08:18:15.41#ibcon#flushed, iclass 36, count 2 2006.280.08:18:15.41#ibcon#about to write, iclass 36, count 2 2006.280.08:18:15.41#ibcon#wrote, iclass 36, count 2 2006.280.08:18:15.41#ibcon#about to read 3, iclass 36, count 2 2006.280.08:18:15.44#ibcon#read 3, iclass 36, count 2 2006.280.08:18:15.44#ibcon#about to read 4, iclass 36, count 2 2006.280.08:18:15.44#ibcon#read 4, iclass 36, count 2 2006.280.08:18:15.44#ibcon#about to read 5, iclass 36, count 2 2006.280.08:18:15.44#ibcon#read 5, iclass 36, count 2 2006.280.08:18:15.44#ibcon#about to read 6, iclass 36, count 2 2006.280.08:18:15.44#ibcon#read 6, iclass 36, count 2 2006.280.08:18:15.44#ibcon#end of sib2, iclass 36, count 2 2006.280.08:18:15.44#ibcon#*after write, iclass 36, count 2 2006.280.08:18:15.44#ibcon#*before return 0, iclass 36, count 2 2006.280.08:18:15.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:15.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:15.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:18:15.44#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:15.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:15.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:15.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:15.56#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:18:15.56#ibcon#first serial, iclass 36, count 0 2006.280.08:18:15.56#ibcon#enter sib2, iclass 36, count 0 2006.280.08:18:15.56#ibcon#flushed, iclass 36, count 0 2006.280.08:18:15.56#ibcon#about to write, iclass 36, count 0 2006.280.08:18:15.56#ibcon#wrote, iclass 36, count 0 2006.280.08:18:15.56#ibcon#about to read 3, iclass 36, count 0 2006.280.08:18:15.58#ibcon#read 3, iclass 36, count 0 2006.280.08:18:15.58#ibcon#about to read 4, iclass 36, count 0 2006.280.08:18:15.58#ibcon#read 4, iclass 36, count 0 2006.280.08:18:15.58#ibcon#about to read 5, iclass 36, count 0 2006.280.08:18:15.58#ibcon#read 5, iclass 36, count 0 2006.280.08:18:15.58#ibcon#about to read 6, iclass 36, count 0 2006.280.08:18:15.58#ibcon#read 6, iclass 36, count 0 2006.280.08:18:15.58#ibcon#end of sib2, iclass 36, count 0 2006.280.08:18:15.58#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:18:15.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:18:15.58#ibcon#[25=USB\r\n] 2006.280.08:18:15.58#ibcon#*before write, iclass 36, count 0 2006.280.08:18:15.58#ibcon#enter sib2, iclass 36, count 0 2006.280.08:18:15.58#ibcon#flushed, iclass 36, count 0 2006.280.08:18:15.58#ibcon#about to write, iclass 36, count 0 2006.280.08:18:15.58#ibcon#wrote, iclass 36, count 0 2006.280.08:18:15.58#ibcon#about to read 3, iclass 36, count 0 2006.280.08:18:15.62#ibcon#read 3, iclass 36, count 0 2006.280.08:18:15.62#ibcon#about to read 4, iclass 36, count 0 2006.280.08:18:15.62#ibcon#read 4, iclass 36, count 0 2006.280.08:18:15.62#ibcon#about to read 5, iclass 36, count 0 2006.280.08:18:15.62#ibcon#read 5, iclass 36, count 0 2006.280.08:18:15.62#ibcon#about to read 6, iclass 36, count 0 2006.280.08:18:15.62#ibcon#read 6, iclass 36, count 0 2006.280.08:18:15.62#ibcon#end of sib2, iclass 36, count 0 2006.280.08:18:15.62#ibcon#*after write, iclass 36, count 0 2006.280.08:18:15.62#ibcon#*before return 0, iclass 36, count 0 2006.280.08:18:15.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:15.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:15.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:18:15.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:18:15.62$vc4f8/valo=5,652.99 2006.280.08:18:15.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:18:15.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:18:15.62#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:15.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:15.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:15.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:15.62#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:18:15.62#ibcon#first serial, iclass 38, count 0 2006.280.08:18:15.62#ibcon#enter sib2, iclass 38, count 0 2006.280.08:18:15.62#ibcon#flushed, iclass 38, count 0 2006.280.08:18:15.62#ibcon#about to write, iclass 38, count 0 2006.280.08:18:15.62#ibcon#wrote, iclass 38, count 0 2006.280.08:18:15.62#ibcon#about to read 3, iclass 38, count 0 2006.280.08:18:15.63#ibcon#read 3, iclass 38, count 0 2006.280.08:18:15.63#ibcon#about to read 4, iclass 38, count 0 2006.280.08:18:15.63#ibcon#read 4, iclass 38, count 0 2006.280.08:18:15.63#ibcon#about to read 5, iclass 38, count 0 2006.280.08:18:15.63#ibcon#read 5, iclass 38, count 0 2006.280.08:18:15.63#ibcon#about to read 6, iclass 38, count 0 2006.280.08:18:15.63#ibcon#read 6, iclass 38, count 0 2006.280.08:18:15.63#ibcon#end of sib2, iclass 38, count 0 2006.280.08:18:15.63#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:18:15.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:18:15.64#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:18:15.64#ibcon#*before write, iclass 38, count 0 2006.280.08:18:15.64#ibcon#enter sib2, iclass 38, count 0 2006.280.08:18:15.64#ibcon#flushed, iclass 38, count 0 2006.280.08:18:15.64#ibcon#about to write, iclass 38, count 0 2006.280.08:18:15.64#ibcon#wrote, iclass 38, count 0 2006.280.08:18:15.64#ibcon#about to read 3, iclass 38, count 0 2006.280.08:18:15.67#ibcon#read 3, iclass 38, count 0 2006.280.08:18:15.67#ibcon#about to read 4, iclass 38, count 0 2006.280.08:18:15.67#ibcon#read 4, iclass 38, count 0 2006.280.08:18:15.67#ibcon#about to read 5, iclass 38, count 0 2006.280.08:18:15.67#ibcon#read 5, iclass 38, count 0 2006.280.08:18:15.67#ibcon#about to read 6, iclass 38, count 0 2006.280.08:18:15.67#ibcon#read 6, iclass 38, count 0 2006.280.08:18:15.67#ibcon#end of sib2, iclass 38, count 0 2006.280.08:18:15.67#ibcon#*after write, iclass 38, count 0 2006.280.08:18:15.67#ibcon#*before return 0, iclass 38, count 0 2006.280.08:18:15.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:15.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:15.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:18:15.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:18:15.67$vc4f8/va=5,7 2006.280.08:18:15.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:18:15.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:18:15.68#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:15.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:15.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:15.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:15.74#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:18:15.74#ibcon#first serial, iclass 40, count 2 2006.280.08:18:15.74#ibcon#enter sib2, iclass 40, count 2 2006.280.08:18:15.74#ibcon#flushed, iclass 40, count 2 2006.280.08:18:15.74#ibcon#about to write, iclass 40, count 2 2006.280.08:18:15.74#ibcon#wrote, iclass 40, count 2 2006.280.08:18:15.74#ibcon#about to read 3, iclass 40, count 2 2006.280.08:18:15.76#ibcon#read 3, iclass 40, count 2 2006.280.08:18:15.76#ibcon#about to read 4, iclass 40, count 2 2006.280.08:18:15.76#ibcon#read 4, iclass 40, count 2 2006.280.08:18:15.76#ibcon#about to read 5, iclass 40, count 2 2006.280.08:18:15.76#ibcon#read 5, iclass 40, count 2 2006.280.08:18:15.76#ibcon#about to read 6, iclass 40, count 2 2006.280.08:18:15.76#ibcon#read 6, iclass 40, count 2 2006.280.08:18:15.76#ibcon#end of sib2, iclass 40, count 2 2006.280.08:18:15.76#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:18:15.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:18:15.76#ibcon#[25=AT05-07\r\n] 2006.280.08:18:15.76#ibcon#*before write, iclass 40, count 2 2006.280.08:18:15.76#ibcon#enter sib2, iclass 40, count 2 2006.280.08:18:15.76#ibcon#flushed, iclass 40, count 2 2006.280.08:18:15.76#ibcon#about to write, iclass 40, count 2 2006.280.08:18:15.76#ibcon#wrote, iclass 40, count 2 2006.280.08:18:15.76#ibcon#about to read 3, iclass 40, count 2 2006.280.08:18:15.78#ibcon#read 3, iclass 40, count 2 2006.280.08:18:15.78#ibcon#about to read 4, iclass 40, count 2 2006.280.08:18:15.78#ibcon#read 4, iclass 40, count 2 2006.280.08:18:15.78#ibcon#about to read 5, iclass 40, count 2 2006.280.08:18:15.78#ibcon#read 5, iclass 40, count 2 2006.280.08:18:15.78#ibcon#about to read 6, iclass 40, count 2 2006.280.08:18:15.78#ibcon#read 6, iclass 40, count 2 2006.280.08:18:15.78#ibcon#end of sib2, iclass 40, count 2 2006.280.08:18:15.78#ibcon#*after write, iclass 40, count 2 2006.280.08:18:15.78#ibcon#*before return 0, iclass 40, count 2 2006.280.08:18:15.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:15.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:15.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:18:15.78#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:15.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:15.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:15.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:15.90#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:18:15.90#ibcon#first serial, iclass 40, count 0 2006.280.08:18:15.90#ibcon#enter sib2, iclass 40, count 0 2006.280.08:18:15.90#ibcon#flushed, iclass 40, count 0 2006.280.08:18:15.90#ibcon#about to write, iclass 40, count 0 2006.280.08:18:15.90#ibcon#wrote, iclass 40, count 0 2006.280.08:18:15.90#ibcon#about to read 3, iclass 40, count 0 2006.280.08:18:15.92#ibcon#read 3, iclass 40, count 0 2006.280.08:18:15.92#ibcon#about to read 4, iclass 40, count 0 2006.280.08:18:15.92#ibcon#read 4, iclass 40, count 0 2006.280.08:18:15.92#ibcon#about to read 5, iclass 40, count 0 2006.280.08:18:15.92#ibcon#read 5, iclass 40, count 0 2006.280.08:18:15.92#ibcon#about to read 6, iclass 40, count 0 2006.280.08:18:15.92#ibcon#read 6, iclass 40, count 0 2006.280.08:18:15.92#ibcon#end of sib2, iclass 40, count 0 2006.280.08:18:15.92#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:18:15.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:18:15.92#ibcon#[25=USB\r\n] 2006.280.08:18:15.92#ibcon#*before write, iclass 40, count 0 2006.280.08:18:15.92#ibcon#enter sib2, iclass 40, count 0 2006.280.08:18:15.92#ibcon#flushed, iclass 40, count 0 2006.280.08:18:15.92#ibcon#about to write, iclass 40, count 0 2006.280.08:18:15.92#ibcon#wrote, iclass 40, count 0 2006.280.08:18:15.92#ibcon#about to read 3, iclass 40, count 0 2006.280.08:18:15.96#ibcon#read 3, iclass 40, count 0 2006.280.08:18:15.96#ibcon#about to read 4, iclass 40, count 0 2006.280.08:18:15.96#ibcon#read 4, iclass 40, count 0 2006.280.08:18:15.96#ibcon#about to read 5, iclass 40, count 0 2006.280.08:18:15.96#ibcon#read 5, iclass 40, count 0 2006.280.08:18:15.96#ibcon#about to read 6, iclass 40, count 0 2006.280.08:18:15.96#ibcon#read 6, iclass 40, count 0 2006.280.08:18:15.96#ibcon#end of sib2, iclass 40, count 0 2006.280.08:18:15.96#ibcon#*after write, iclass 40, count 0 2006.280.08:18:15.96#ibcon#*before return 0, iclass 40, count 0 2006.280.08:18:15.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:15.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:15.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:18:15.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:18:15.96$vc4f8/valo=6,772.99 2006.280.08:18:15.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:18:15.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:18:15.96#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:15.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:15.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:15.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:15.96#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:18:15.96#ibcon#first serial, iclass 4, count 0 2006.280.08:18:15.96#ibcon#enter sib2, iclass 4, count 0 2006.280.08:18:15.96#ibcon#flushed, iclass 4, count 0 2006.280.08:18:15.96#ibcon#about to write, iclass 4, count 0 2006.280.08:18:15.96#ibcon#wrote, iclass 4, count 0 2006.280.08:18:15.96#ibcon#about to read 3, iclass 4, count 0 2006.280.08:18:15.98#ibcon#read 3, iclass 4, count 0 2006.280.08:18:15.98#ibcon#about to read 4, iclass 4, count 0 2006.280.08:18:15.98#ibcon#read 4, iclass 4, count 0 2006.280.08:18:15.98#ibcon#about to read 5, iclass 4, count 0 2006.280.08:18:15.98#ibcon#read 5, iclass 4, count 0 2006.280.08:18:15.98#ibcon#about to read 6, iclass 4, count 0 2006.280.08:18:15.98#ibcon#read 6, iclass 4, count 0 2006.280.08:18:15.98#ibcon#end of sib2, iclass 4, count 0 2006.280.08:18:15.98#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:18:15.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:18:15.98#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:18:16.00#ibcon#*before write, iclass 4, count 0 2006.280.08:18:16.00#ibcon#enter sib2, iclass 4, count 0 2006.280.08:18:16.00#ibcon#flushed, iclass 4, count 0 2006.280.08:18:16.00#ibcon#about to write, iclass 4, count 0 2006.280.08:18:16.00#ibcon#wrote, iclass 4, count 0 2006.280.08:18:16.00#ibcon#about to read 3, iclass 4, count 0 2006.280.08:18:16.04#ibcon#read 3, iclass 4, count 0 2006.280.08:18:16.04#ibcon#about to read 4, iclass 4, count 0 2006.280.08:18:16.04#ibcon#read 4, iclass 4, count 0 2006.280.08:18:16.04#ibcon#about to read 5, iclass 4, count 0 2006.280.08:18:16.04#ibcon#read 5, iclass 4, count 0 2006.280.08:18:16.04#ibcon#about to read 6, iclass 4, count 0 2006.280.08:18:16.04#ibcon#read 6, iclass 4, count 0 2006.280.08:18:16.04#ibcon#end of sib2, iclass 4, count 0 2006.280.08:18:16.04#ibcon#*after write, iclass 4, count 0 2006.280.08:18:16.04#ibcon#*before return 0, iclass 4, count 0 2006.280.08:18:16.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:16.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:16.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:18:16.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:18:16.04$vc4f8/va=6,6 2006.280.08:18:16.04#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.280.08:18:16.04#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.280.08:18:16.04#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:16.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:16.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:16.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:16.08#ibcon#enter wrdev, iclass 6, count 2 2006.280.08:18:16.08#ibcon#first serial, iclass 6, count 2 2006.280.08:18:16.08#ibcon#enter sib2, iclass 6, count 2 2006.280.08:18:16.08#ibcon#flushed, iclass 6, count 2 2006.280.08:18:16.08#ibcon#about to write, iclass 6, count 2 2006.280.08:18:16.08#ibcon#wrote, iclass 6, count 2 2006.280.08:18:16.08#ibcon#about to read 3, iclass 6, count 2 2006.280.08:18:16.10#ibcon#read 3, iclass 6, count 2 2006.280.08:18:16.10#ibcon#about to read 4, iclass 6, count 2 2006.280.08:18:16.10#ibcon#read 4, iclass 6, count 2 2006.280.08:18:16.10#ibcon#about to read 5, iclass 6, count 2 2006.280.08:18:16.10#ibcon#read 5, iclass 6, count 2 2006.280.08:18:16.10#ibcon#about to read 6, iclass 6, count 2 2006.280.08:18:16.10#ibcon#read 6, iclass 6, count 2 2006.280.08:18:16.10#ibcon#end of sib2, iclass 6, count 2 2006.280.08:18:16.10#ibcon#*mode == 0, iclass 6, count 2 2006.280.08:18:16.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.280.08:18:16.10#ibcon#[25=AT06-06\r\n] 2006.280.08:18:16.10#ibcon#*before write, iclass 6, count 2 2006.280.08:18:16.10#ibcon#enter sib2, iclass 6, count 2 2006.280.08:18:16.10#ibcon#flushed, iclass 6, count 2 2006.280.08:18:16.10#ibcon#about to write, iclass 6, count 2 2006.280.08:18:16.10#ibcon#wrote, iclass 6, count 2 2006.280.08:18:16.10#ibcon#about to read 3, iclass 6, count 2 2006.280.08:18:16.13#ibcon#read 3, iclass 6, count 2 2006.280.08:18:16.13#ibcon#about to read 4, iclass 6, count 2 2006.280.08:18:16.13#ibcon#read 4, iclass 6, count 2 2006.280.08:18:16.13#ibcon#about to read 5, iclass 6, count 2 2006.280.08:18:16.13#ibcon#read 5, iclass 6, count 2 2006.280.08:18:16.13#ibcon#about to read 6, iclass 6, count 2 2006.280.08:18:16.13#ibcon#read 6, iclass 6, count 2 2006.280.08:18:16.13#ibcon#end of sib2, iclass 6, count 2 2006.280.08:18:16.13#ibcon#*after write, iclass 6, count 2 2006.280.08:18:16.13#ibcon#*before return 0, iclass 6, count 2 2006.280.08:18:16.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:16.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:16.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.280.08:18:16.13#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:16.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:18:16.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:18:16.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:18:16.25#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:18:16.25#ibcon#first serial, iclass 6, count 0 2006.280.08:18:16.25#ibcon#enter sib2, iclass 6, count 0 2006.280.08:18:16.25#ibcon#flushed, iclass 6, count 0 2006.280.08:18:16.25#ibcon#about to write, iclass 6, count 0 2006.280.08:18:16.25#ibcon#wrote, iclass 6, count 0 2006.280.08:18:16.25#ibcon#about to read 3, iclass 6, count 0 2006.280.08:18:16.27#ibcon#read 3, iclass 6, count 0 2006.280.08:18:16.27#ibcon#about to read 4, iclass 6, count 0 2006.280.08:18:16.27#ibcon#read 4, iclass 6, count 0 2006.280.08:18:16.27#ibcon#about to read 5, iclass 6, count 0 2006.280.08:18:16.27#ibcon#read 5, iclass 6, count 0 2006.280.08:18:16.27#ibcon#about to read 6, iclass 6, count 0 2006.280.08:18:16.27#ibcon#read 6, iclass 6, count 0 2006.280.08:18:16.27#ibcon#end of sib2, iclass 6, count 0 2006.280.08:18:16.27#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:18:16.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:18:16.27#ibcon#[25=USB\r\n] 2006.280.08:18:16.27#ibcon#*before write, iclass 6, count 0 2006.280.08:18:16.27#ibcon#enter sib2, iclass 6, count 0 2006.280.08:18:16.27#ibcon#flushed, iclass 6, count 0 2006.280.08:18:16.27#ibcon#about to write, iclass 6, count 0 2006.280.08:18:16.27#ibcon#wrote, iclass 6, count 0 2006.280.08:18:16.27#ibcon#about to read 3, iclass 6, count 0 2006.280.08:18:16.30#ibcon#read 3, iclass 6, count 0 2006.280.08:18:16.30#ibcon#about to read 4, iclass 6, count 0 2006.280.08:18:16.30#ibcon#read 4, iclass 6, count 0 2006.280.08:18:16.30#ibcon#about to read 5, iclass 6, count 0 2006.280.08:18:16.30#ibcon#read 5, iclass 6, count 0 2006.280.08:18:16.30#ibcon#about to read 6, iclass 6, count 0 2006.280.08:18:16.30#ibcon#read 6, iclass 6, count 0 2006.280.08:18:16.30#ibcon#end of sib2, iclass 6, count 0 2006.280.08:18:16.30#ibcon#*after write, iclass 6, count 0 2006.280.08:18:16.30#ibcon#*before return 0, iclass 6, count 0 2006.280.08:18:16.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:18:16.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.280.08:18:16.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:18:16.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:18:16.30$vc4f8/valo=7,832.99 2006.280.08:18:16.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.280.08:18:16.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.280.08:18:16.30#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:16.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:18:16.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:18:16.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:18:16.30#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:18:16.30#ibcon#first serial, iclass 10, count 0 2006.280.08:18:16.30#ibcon#enter sib2, iclass 10, count 0 2006.280.08:18:16.30#ibcon#flushed, iclass 10, count 0 2006.280.08:18:16.30#ibcon#about to write, iclass 10, count 0 2006.280.08:18:16.30#ibcon#wrote, iclass 10, count 0 2006.280.08:18:16.30#ibcon#about to read 3, iclass 10, count 0 2006.280.08:18:16.32#ibcon#read 3, iclass 10, count 0 2006.280.08:18:16.33#ibcon#about to read 4, iclass 10, count 0 2006.280.08:18:16.33#ibcon#read 4, iclass 10, count 0 2006.280.08:18:16.33#ibcon#about to read 5, iclass 10, count 0 2006.280.08:18:16.33#ibcon#read 5, iclass 10, count 0 2006.280.08:18:16.33#ibcon#about to read 6, iclass 10, count 0 2006.280.08:18:16.33#ibcon#read 6, iclass 10, count 0 2006.280.08:18:16.33#ibcon#end of sib2, iclass 10, count 0 2006.280.08:18:16.33#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:18:16.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:18:16.33#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:18:16.33#ibcon#*before write, iclass 10, count 0 2006.280.08:18:16.33#ibcon#enter sib2, iclass 10, count 0 2006.280.08:18:16.33#ibcon#flushed, iclass 10, count 0 2006.280.08:18:16.33#ibcon#about to write, iclass 10, count 0 2006.280.08:18:16.33#ibcon#wrote, iclass 10, count 0 2006.280.08:18:16.33#ibcon#about to read 3, iclass 10, count 0 2006.280.08:18:16.36#ibcon#read 3, iclass 10, count 0 2006.280.08:18:16.36#ibcon#about to read 4, iclass 10, count 0 2006.280.08:18:16.36#ibcon#read 4, iclass 10, count 0 2006.280.08:18:16.36#ibcon#about to read 5, iclass 10, count 0 2006.280.08:18:16.36#ibcon#read 5, iclass 10, count 0 2006.280.08:18:16.36#ibcon#about to read 6, iclass 10, count 0 2006.280.08:18:16.36#ibcon#read 6, iclass 10, count 0 2006.280.08:18:16.36#ibcon#end of sib2, iclass 10, count 0 2006.280.08:18:16.36#ibcon#*after write, iclass 10, count 0 2006.280.08:18:16.36#ibcon#*before return 0, iclass 10, count 0 2006.280.08:18:16.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:18:16.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.280.08:18:16.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:18:16.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:18:16.36$vc4f8/va=7,6 2006.280.08:18:16.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.280.08:18:16.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.280.08:18:16.36#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:16.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:18:16.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:18:16.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:18:16.43#ibcon#enter wrdev, iclass 12, count 2 2006.280.08:18:16.43#ibcon#first serial, iclass 12, count 2 2006.280.08:18:16.43#ibcon#enter sib2, iclass 12, count 2 2006.280.08:18:16.43#ibcon#flushed, iclass 12, count 2 2006.280.08:18:16.43#ibcon#about to write, iclass 12, count 2 2006.280.08:18:16.43#ibcon#wrote, iclass 12, count 2 2006.280.08:18:16.43#ibcon#about to read 3, iclass 12, count 2 2006.280.08:18:16.44#ibcon#read 3, iclass 12, count 2 2006.280.08:18:16.44#ibcon#about to read 4, iclass 12, count 2 2006.280.08:18:16.44#ibcon#read 4, iclass 12, count 2 2006.280.08:18:16.44#ibcon#about to read 5, iclass 12, count 2 2006.280.08:18:16.44#ibcon#read 5, iclass 12, count 2 2006.280.08:18:16.44#ibcon#about to read 6, iclass 12, count 2 2006.280.08:18:16.44#ibcon#read 6, iclass 12, count 2 2006.280.08:18:16.44#ibcon#end of sib2, iclass 12, count 2 2006.280.08:18:16.44#ibcon#*mode == 0, iclass 12, count 2 2006.280.08:18:16.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.280.08:18:16.44#ibcon#[25=AT07-06\r\n] 2006.280.08:18:16.44#ibcon#*before write, iclass 12, count 2 2006.280.08:18:16.44#ibcon#enter sib2, iclass 12, count 2 2006.280.08:18:16.44#ibcon#flushed, iclass 12, count 2 2006.280.08:18:16.44#ibcon#about to write, iclass 12, count 2 2006.280.08:18:16.44#ibcon#wrote, iclass 12, count 2 2006.280.08:18:16.44#ibcon#about to read 3, iclass 12, count 2 2006.280.08:18:16.47#ibcon#read 3, iclass 12, count 2 2006.280.08:18:16.47#ibcon#about to read 4, iclass 12, count 2 2006.280.08:18:16.47#ibcon#read 4, iclass 12, count 2 2006.280.08:18:16.47#ibcon#about to read 5, iclass 12, count 2 2006.280.08:18:16.47#ibcon#read 5, iclass 12, count 2 2006.280.08:18:16.47#ibcon#about to read 6, iclass 12, count 2 2006.280.08:18:16.47#ibcon#read 6, iclass 12, count 2 2006.280.08:18:16.47#ibcon#end of sib2, iclass 12, count 2 2006.280.08:18:16.47#ibcon#*after write, iclass 12, count 2 2006.280.08:18:16.47#ibcon#*before return 0, iclass 12, count 2 2006.280.08:18:16.47#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:18:16.47#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.280.08:18:16.47#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.280.08:18:16.47#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:16.47#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:18:16.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:18:16.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:18:16.59#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:18:16.59#ibcon#first serial, iclass 12, count 0 2006.280.08:18:16.59#ibcon#enter sib2, iclass 12, count 0 2006.280.08:18:16.59#ibcon#flushed, iclass 12, count 0 2006.280.08:18:16.59#ibcon#about to write, iclass 12, count 0 2006.280.08:18:16.59#ibcon#wrote, iclass 12, count 0 2006.280.08:18:16.59#ibcon#about to read 3, iclass 12, count 0 2006.280.08:18:16.61#ibcon#read 3, iclass 12, count 0 2006.280.08:18:16.61#ibcon#about to read 4, iclass 12, count 0 2006.280.08:18:16.61#ibcon#read 4, iclass 12, count 0 2006.280.08:18:16.61#ibcon#about to read 5, iclass 12, count 0 2006.280.08:18:16.61#ibcon#read 5, iclass 12, count 0 2006.280.08:18:16.61#ibcon#about to read 6, iclass 12, count 0 2006.280.08:18:16.61#ibcon#read 6, iclass 12, count 0 2006.280.08:18:16.61#ibcon#end of sib2, iclass 12, count 0 2006.280.08:18:16.61#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:18:16.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:18:16.61#ibcon#[25=USB\r\n] 2006.280.08:18:16.61#ibcon#*before write, iclass 12, count 0 2006.280.08:18:16.61#ibcon#enter sib2, iclass 12, count 0 2006.280.08:18:16.61#ibcon#flushed, iclass 12, count 0 2006.280.08:18:16.61#ibcon#about to write, iclass 12, count 0 2006.280.08:18:16.61#ibcon#wrote, iclass 12, count 0 2006.280.08:18:16.61#ibcon#about to read 3, iclass 12, count 0 2006.280.08:18:16.64#ibcon#read 3, iclass 12, count 0 2006.280.08:18:16.64#ibcon#about to read 4, iclass 12, count 0 2006.280.08:18:16.64#ibcon#read 4, iclass 12, count 0 2006.280.08:18:16.64#ibcon#about to read 5, iclass 12, count 0 2006.280.08:18:16.64#ibcon#read 5, iclass 12, count 0 2006.280.08:18:16.64#ibcon#about to read 6, iclass 12, count 0 2006.280.08:18:16.64#ibcon#read 6, iclass 12, count 0 2006.280.08:18:16.64#ibcon#end of sib2, iclass 12, count 0 2006.280.08:18:16.64#ibcon#*after write, iclass 12, count 0 2006.280.08:18:16.64#ibcon#*before return 0, iclass 12, count 0 2006.280.08:18:16.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:18:16.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.280.08:18:16.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:18:16.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:18:16.64$vc4f8/valo=8,852.99 2006.280.08:18:16.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.280.08:18:16.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.280.08:18:16.64#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:16.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:18:16.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:18:16.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:18:16.64#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:18:16.64#ibcon#first serial, iclass 14, count 0 2006.280.08:18:16.64#ibcon#enter sib2, iclass 14, count 0 2006.280.08:18:16.64#ibcon#flushed, iclass 14, count 0 2006.280.08:18:16.64#ibcon#about to write, iclass 14, count 0 2006.280.08:18:16.64#ibcon#wrote, iclass 14, count 0 2006.280.08:18:16.64#ibcon#about to read 3, iclass 14, count 0 2006.280.08:18:16.66#ibcon#read 3, iclass 14, count 0 2006.280.08:18:16.66#ibcon#about to read 4, iclass 14, count 0 2006.280.08:18:16.66#ibcon#read 4, iclass 14, count 0 2006.280.08:18:16.66#ibcon#about to read 5, iclass 14, count 0 2006.280.08:18:16.66#ibcon#read 5, iclass 14, count 0 2006.280.08:18:16.66#ibcon#about to read 6, iclass 14, count 0 2006.280.08:18:16.66#ibcon#read 6, iclass 14, count 0 2006.280.08:18:16.66#ibcon#end of sib2, iclass 14, count 0 2006.280.08:18:16.66#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:18:16.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:18:16.66#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:18:16.66#ibcon#*before write, iclass 14, count 0 2006.280.08:18:16.66#ibcon#enter sib2, iclass 14, count 0 2006.280.08:18:16.66#ibcon#flushed, iclass 14, count 0 2006.280.08:18:16.66#ibcon#about to write, iclass 14, count 0 2006.280.08:18:16.66#ibcon#wrote, iclass 14, count 0 2006.280.08:18:16.66#ibcon#about to read 3, iclass 14, count 0 2006.280.08:18:16.70#ibcon#read 3, iclass 14, count 0 2006.280.08:18:16.70#ibcon#about to read 4, iclass 14, count 0 2006.280.08:18:16.70#ibcon#read 4, iclass 14, count 0 2006.280.08:18:16.70#ibcon#about to read 5, iclass 14, count 0 2006.280.08:18:16.70#ibcon#read 5, iclass 14, count 0 2006.280.08:18:16.70#ibcon#about to read 6, iclass 14, count 0 2006.280.08:18:16.70#ibcon#read 6, iclass 14, count 0 2006.280.08:18:16.70#ibcon#end of sib2, iclass 14, count 0 2006.280.08:18:16.70#ibcon#*after write, iclass 14, count 0 2006.280.08:18:16.70#ibcon#*before return 0, iclass 14, count 0 2006.280.08:18:16.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:18:16.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.280.08:18:16.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:18:16.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:18:16.70$vc4f8/va=8,6 2006.280.08:18:16.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.280.08:18:16.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.280.08:18:16.70#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:16.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:18:16.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:18:16.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:18:16.76#ibcon#enter wrdev, iclass 16, count 2 2006.280.08:18:16.76#ibcon#first serial, iclass 16, count 2 2006.280.08:18:16.76#ibcon#enter sib2, iclass 16, count 2 2006.280.08:18:16.76#ibcon#flushed, iclass 16, count 2 2006.280.08:18:16.76#ibcon#about to write, iclass 16, count 2 2006.280.08:18:16.76#ibcon#wrote, iclass 16, count 2 2006.280.08:18:16.76#ibcon#about to read 3, iclass 16, count 2 2006.280.08:18:16.78#ibcon#read 3, iclass 16, count 2 2006.280.08:18:16.78#ibcon#about to read 4, iclass 16, count 2 2006.280.08:18:16.78#ibcon#read 4, iclass 16, count 2 2006.280.08:18:16.78#ibcon#about to read 5, iclass 16, count 2 2006.280.08:18:16.78#ibcon#read 5, iclass 16, count 2 2006.280.08:18:16.78#ibcon#about to read 6, iclass 16, count 2 2006.280.08:18:16.78#ibcon#read 6, iclass 16, count 2 2006.280.08:18:16.78#ibcon#end of sib2, iclass 16, count 2 2006.280.08:18:16.78#ibcon#*mode == 0, iclass 16, count 2 2006.280.08:18:16.78#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.280.08:18:16.78#ibcon#[25=AT08-06\r\n] 2006.280.08:18:16.78#ibcon#*before write, iclass 16, count 2 2006.280.08:18:16.78#ibcon#enter sib2, iclass 16, count 2 2006.280.08:18:16.78#ibcon#flushed, iclass 16, count 2 2006.280.08:18:16.78#ibcon#about to write, iclass 16, count 2 2006.280.08:18:16.78#ibcon#wrote, iclass 16, count 2 2006.280.08:18:16.78#ibcon#about to read 3, iclass 16, count 2 2006.280.08:18:16.82#ibcon#read 3, iclass 16, count 2 2006.280.08:18:16.82#ibcon#about to read 4, iclass 16, count 2 2006.280.08:18:16.82#ibcon#read 4, iclass 16, count 2 2006.280.08:18:16.82#ibcon#about to read 5, iclass 16, count 2 2006.280.08:18:16.82#ibcon#read 5, iclass 16, count 2 2006.280.08:18:16.82#ibcon#about to read 6, iclass 16, count 2 2006.280.08:18:16.82#ibcon#read 6, iclass 16, count 2 2006.280.08:18:16.82#ibcon#end of sib2, iclass 16, count 2 2006.280.08:18:16.82#ibcon#*after write, iclass 16, count 2 2006.280.08:18:16.82#ibcon#*before return 0, iclass 16, count 2 2006.280.08:18:16.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:18:16.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.280.08:18:16.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.280.08:18:16.82#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:16.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:18:16.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:18:16.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:18:16.94#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:18:16.94#ibcon#first serial, iclass 16, count 0 2006.280.08:18:16.94#ibcon#enter sib2, iclass 16, count 0 2006.280.08:18:16.94#ibcon#flushed, iclass 16, count 0 2006.280.08:18:16.94#ibcon#about to write, iclass 16, count 0 2006.280.08:18:16.94#ibcon#wrote, iclass 16, count 0 2006.280.08:18:16.94#ibcon#about to read 3, iclass 16, count 0 2006.280.08:18:16.95#ibcon#read 3, iclass 16, count 0 2006.280.08:18:16.95#ibcon#about to read 4, iclass 16, count 0 2006.280.08:18:16.95#ibcon#read 4, iclass 16, count 0 2006.280.08:18:16.95#ibcon#about to read 5, iclass 16, count 0 2006.280.08:18:16.95#ibcon#read 5, iclass 16, count 0 2006.280.08:18:16.95#ibcon#about to read 6, iclass 16, count 0 2006.280.08:18:16.95#ibcon#read 6, iclass 16, count 0 2006.280.08:18:16.95#ibcon#end of sib2, iclass 16, count 0 2006.280.08:18:16.95#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:18:16.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:18:16.95#ibcon#[25=USB\r\n] 2006.280.08:18:16.95#ibcon#*before write, iclass 16, count 0 2006.280.08:18:16.95#ibcon#enter sib2, iclass 16, count 0 2006.280.08:18:16.95#ibcon#flushed, iclass 16, count 0 2006.280.08:18:16.95#ibcon#about to write, iclass 16, count 0 2006.280.08:18:16.95#ibcon#wrote, iclass 16, count 0 2006.280.08:18:16.95#ibcon#about to read 3, iclass 16, count 0 2006.280.08:18:16.98#ibcon#read 3, iclass 16, count 0 2006.280.08:18:16.98#ibcon#about to read 4, iclass 16, count 0 2006.280.08:18:16.98#ibcon#read 4, iclass 16, count 0 2006.280.08:18:16.98#ibcon#about to read 5, iclass 16, count 0 2006.280.08:18:16.98#ibcon#read 5, iclass 16, count 0 2006.280.08:18:16.98#ibcon#about to read 6, iclass 16, count 0 2006.280.08:18:16.98#ibcon#read 6, iclass 16, count 0 2006.280.08:18:16.98#ibcon#end of sib2, iclass 16, count 0 2006.280.08:18:16.98#ibcon#*after write, iclass 16, count 0 2006.280.08:18:16.98#ibcon#*before return 0, iclass 16, count 0 2006.280.08:18:16.98#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:18:16.98#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.280.08:18:16.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:18:16.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:18:16.98$vc4f8/vblo=1,632.99 2006.280.08:18:16.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.280.08:18:16.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.280.08:18:16.98#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:16.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:18:16.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:18:16.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:18:16.98#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:18:16.98#ibcon#first serial, iclass 18, count 0 2006.280.08:18:16.98#ibcon#enter sib2, iclass 18, count 0 2006.280.08:18:16.98#ibcon#flushed, iclass 18, count 0 2006.280.08:18:16.98#ibcon#about to write, iclass 18, count 0 2006.280.08:18:16.98#ibcon#wrote, iclass 18, count 0 2006.280.08:18:16.98#ibcon#about to read 3, iclass 18, count 0 2006.280.08:18:17.00#ibcon#read 3, iclass 18, count 0 2006.280.08:18:17.00#ibcon#about to read 4, iclass 18, count 0 2006.280.08:18:17.00#ibcon#read 4, iclass 18, count 0 2006.280.08:18:17.00#ibcon#about to read 5, iclass 18, count 0 2006.280.08:18:17.00#ibcon#read 5, iclass 18, count 0 2006.280.08:18:17.00#ibcon#about to read 6, iclass 18, count 0 2006.280.08:18:17.00#ibcon#read 6, iclass 18, count 0 2006.280.08:18:17.00#ibcon#end of sib2, iclass 18, count 0 2006.280.08:18:17.00#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:18:17.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:18:17.00#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:18:17.00#ibcon#*before write, iclass 18, count 0 2006.280.08:18:17.00#ibcon#enter sib2, iclass 18, count 0 2006.280.08:18:17.00#ibcon#flushed, iclass 18, count 0 2006.280.08:18:17.00#ibcon#about to write, iclass 18, count 0 2006.280.08:18:17.00#ibcon#wrote, iclass 18, count 0 2006.280.08:18:17.00#ibcon#about to read 3, iclass 18, count 0 2006.280.08:18:17.04#ibcon#read 3, iclass 18, count 0 2006.280.08:18:17.04#ibcon#about to read 4, iclass 18, count 0 2006.280.08:18:17.04#ibcon#read 4, iclass 18, count 0 2006.280.08:18:17.04#ibcon#about to read 5, iclass 18, count 0 2006.280.08:18:17.04#ibcon#read 5, iclass 18, count 0 2006.280.08:18:17.04#ibcon#about to read 6, iclass 18, count 0 2006.280.08:18:17.04#ibcon#read 6, iclass 18, count 0 2006.280.08:18:17.04#ibcon#end of sib2, iclass 18, count 0 2006.280.08:18:17.04#ibcon#*after write, iclass 18, count 0 2006.280.08:18:17.04#ibcon#*before return 0, iclass 18, count 0 2006.280.08:18:17.04#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:18:17.04#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.280.08:18:17.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:18:17.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:18:17.04$vc4f8/vb=1,4 2006.280.08:18:17.04#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.280.08:18:17.04#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.280.08:18:17.04#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:17.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:18:17.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:18:17.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:18:17.04#ibcon#enter wrdev, iclass 20, count 2 2006.280.08:18:17.04#ibcon#first serial, iclass 20, count 2 2006.280.08:18:17.04#ibcon#enter sib2, iclass 20, count 2 2006.280.08:18:17.04#ibcon#flushed, iclass 20, count 2 2006.280.08:18:17.04#ibcon#about to write, iclass 20, count 2 2006.280.08:18:17.04#ibcon#wrote, iclass 20, count 2 2006.280.08:18:17.04#ibcon#about to read 3, iclass 20, count 2 2006.280.08:18:17.06#ibcon#read 3, iclass 20, count 2 2006.280.08:18:17.07#ibcon#about to read 4, iclass 20, count 2 2006.280.08:18:17.07#ibcon#read 4, iclass 20, count 2 2006.280.08:18:17.07#ibcon#about to read 5, iclass 20, count 2 2006.280.08:18:17.07#ibcon#read 5, iclass 20, count 2 2006.280.08:18:17.07#ibcon#about to read 6, iclass 20, count 2 2006.280.08:18:17.07#ibcon#read 6, iclass 20, count 2 2006.280.08:18:17.07#ibcon#end of sib2, iclass 20, count 2 2006.280.08:18:17.07#ibcon#*mode == 0, iclass 20, count 2 2006.280.08:18:17.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.280.08:18:17.07#ibcon#[27=AT01-04\r\n] 2006.280.08:18:17.07#ibcon#*before write, iclass 20, count 2 2006.280.08:18:17.07#ibcon#enter sib2, iclass 20, count 2 2006.280.08:18:17.07#ibcon#flushed, iclass 20, count 2 2006.280.08:18:17.07#ibcon#about to write, iclass 20, count 2 2006.280.08:18:17.07#ibcon#wrote, iclass 20, count 2 2006.280.08:18:17.07#ibcon#about to read 3, iclass 20, count 2 2006.280.08:18:17.10#ibcon#read 3, iclass 20, count 2 2006.280.08:18:17.10#ibcon#about to read 4, iclass 20, count 2 2006.280.08:18:17.10#ibcon#read 4, iclass 20, count 2 2006.280.08:18:17.10#ibcon#about to read 5, iclass 20, count 2 2006.280.08:18:17.10#ibcon#read 5, iclass 20, count 2 2006.280.08:18:17.10#ibcon#about to read 6, iclass 20, count 2 2006.280.08:18:17.10#ibcon#read 6, iclass 20, count 2 2006.280.08:18:17.10#ibcon#end of sib2, iclass 20, count 2 2006.280.08:18:17.10#ibcon#*after write, iclass 20, count 2 2006.280.08:18:17.10#ibcon#*before return 0, iclass 20, count 2 2006.280.08:18:17.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:18:17.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.280.08:18:17.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.280.08:18:17.10#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:17.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:18:17.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:18:17.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:18:17.23#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:18:17.23#ibcon#first serial, iclass 20, count 0 2006.280.08:18:17.23#ibcon#enter sib2, iclass 20, count 0 2006.280.08:18:17.23#ibcon#flushed, iclass 20, count 0 2006.280.08:18:17.23#ibcon#about to write, iclass 20, count 0 2006.280.08:18:17.23#ibcon#wrote, iclass 20, count 0 2006.280.08:18:17.23#ibcon#about to read 3, iclass 20, count 0 2006.280.08:18:17.24#ibcon#read 3, iclass 20, count 0 2006.280.08:18:17.24#ibcon#about to read 4, iclass 20, count 0 2006.280.08:18:17.24#ibcon#read 4, iclass 20, count 0 2006.280.08:18:17.24#ibcon#about to read 5, iclass 20, count 0 2006.280.08:18:17.24#ibcon#read 5, iclass 20, count 0 2006.280.08:18:17.24#ibcon#about to read 6, iclass 20, count 0 2006.280.08:18:17.24#ibcon#read 6, iclass 20, count 0 2006.280.08:18:17.24#ibcon#end of sib2, iclass 20, count 0 2006.280.08:18:17.24#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:18:17.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:18:17.24#ibcon#[27=USB\r\n] 2006.280.08:18:17.24#ibcon#*before write, iclass 20, count 0 2006.280.08:18:17.24#ibcon#enter sib2, iclass 20, count 0 2006.280.08:18:17.24#ibcon#flushed, iclass 20, count 0 2006.280.08:18:17.24#ibcon#about to write, iclass 20, count 0 2006.280.08:18:17.24#ibcon#wrote, iclass 20, count 0 2006.280.08:18:17.24#ibcon#about to read 3, iclass 20, count 0 2006.280.08:18:17.27#ibcon#read 3, iclass 20, count 0 2006.280.08:18:17.27#ibcon#about to read 4, iclass 20, count 0 2006.280.08:18:17.27#ibcon#read 4, iclass 20, count 0 2006.280.08:18:17.27#ibcon#about to read 5, iclass 20, count 0 2006.280.08:18:17.27#ibcon#read 5, iclass 20, count 0 2006.280.08:18:17.27#ibcon#about to read 6, iclass 20, count 0 2006.280.08:18:17.27#ibcon#read 6, iclass 20, count 0 2006.280.08:18:17.27#ibcon#end of sib2, iclass 20, count 0 2006.280.08:18:17.27#ibcon#*after write, iclass 20, count 0 2006.280.08:18:17.27#ibcon#*before return 0, iclass 20, count 0 2006.280.08:18:17.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:18:17.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.280.08:18:17.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:18:17.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:18:17.27$vc4f8/vblo=2,640.99 2006.280.08:18:17.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.280.08:18:17.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.280.08:18:17.27#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:17.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:17.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:17.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:17.27#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:18:17.27#ibcon#first serial, iclass 22, count 0 2006.280.08:18:17.27#ibcon#enter sib2, iclass 22, count 0 2006.280.08:18:17.27#ibcon#flushed, iclass 22, count 0 2006.280.08:18:17.27#ibcon#about to write, iclass 22, count 0 2006.280.08:18:17.27#ibcon#wrote, iclass 22, count 0 2006.280.08:18:17.27#ibcon#about to read 3, iclass 22, count 0 2006.280.08:18:17.29#ibcon#read 3, iclass 22, count 0 2006.280.08:18:17.29#ibcon#about to read 4, iclass 22, count 0 2006.280.08:18:17.29#ibcon#read 4, iclass 22, count 0 2006.280.08:18:17.29#ibcon#about to read 5, iclass 22, count 0 2006.280.08:18:17.29#ibcon#read 5, iclass 22, count 0 2006.280.08:18:17.29#ibcon#about to read 6, iclass 22, count 0 2006.280.08:18:17.29#ibcon#read 6, iclass 22, count 0 2006.280.08:18:17.29#ibcon#end of sib2, iclass 22, count 0 2006.280.08:18:17.29#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:18:17.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:18:17.29#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:18:17.29#ibcon#*before write, iclass 22, count 0 2006.280.08:18:17.29#ibcon#enter sib2, iclass 22, count 0 2006.280.08:18:17.29#ibcon#flushed, iclass 22, count 0 2006.280.08:18:17.29#ibcon#about to write, iclass 22, count 0 2006.280.08:18:17.29#ibcon#wrote, iclass 22, count 0 2006.280.08:18:17.29#ibcon#about to read 3, iclass 22, count 0 2006.280.08:18:17.34#ibcon#read 3, iclass 22, count 0 2006.280.08:18:17.34#ibcon#about to read 4, iclass 22, count 0 2006.280.08:18:17.34#ibcon#read 4, iclass 22, count 0 2006.280.08:18:17.34#ibcon#about to read 5, iclass 22, count 0 2006.280.08:18:17.34#ibcon#read 5, iclass 22, count 0 2006.280.08:18:17.34#ibcon#about to read 6, iclass 22, count 0 2006.280.08:18:17.34#ibcon#read 6, iclass 22, count 0 2006.280.08:18:17.34#ibcon#end of sib2, iclass 22, count 0 2006.280.08:18:17.34#ibcon#*after write, iclass 22, count 0 2006.280.08:18:17.34#ibcon#*before return 0, iclass 22, count 0 2006.280.08:18:17.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:17.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.280.08:18:17.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:18:17.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:18:17.34$vc4f8/vb=2,5 2006.280.08:18:17.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.280.08:18:17.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.280.08:18:17.34#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:17.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:17.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:17.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:17.38#ibcon#enter wrdev, iclass 24, count 2 2006.280.08:18:17.38#ibcon#first serial, iclass 24, count 2 2006.280.08:18:17.38#ibcon#enter sib2, iclass 24, count 2 2006.280.08:18:17.38#ibcon#flushed, iclass 24, count 2 2006.280.08:18:17.38#ibcon#about to write, iclass 24, count 2 2006.280.08:18:17.38#ibcon#wrote, iclass 24, count 2 2006.280.08:18:17.38#ibcon#about to read 3, iclass 24, count 2 2006.280.08:18:17.40#ibcon#read 3, iclass 24, count 2 2006.280.08:18:17.40#ibcon#about to read 4, iclass 24, count 2 2006.280.08:18:17.40#ibcon#read 4, iclass 24, count 2 2006.280.08:18:17.40#ibcon#about to read 5, iclass 24, count 2 2006.280.08:18:17.40#ibcon#read 5, iclass 24, count 2 2006.280.08:18:17.40#ibcon#about to read 6, iclass 24, count 2 2006.280.08:18:17.40#ibcon#read 6, iclass 24, count 2 2006.280.08:18:17.40#ibcon#end of sib2, iclass 24, count 2 2006.280.08:18:17.40#ibcon#*mode == 0, iclass 24, count 2 2006.280.08:18:17.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.280.08:18:17.40#ibcon#[27=AT02-05\r\n] 2006.280.08:18:17.40#ibcon#*before write, iclass 24, count 2 2006.280.08:18:17.40#ibcon#enter sib2, iclass 24, count 2 2006.280.08:18:17.40#ibcon#flushed, iclass 24, count 2 2006.280.08:18:17.40#ibcon#about to write, iclass 24, count 2 2006.280.08:18:17.40#ibcon#wrote, iclass 24, count 2 2006.280.08:18:17.40#ibcon#about to read 3, iclass 24, count 2 2006.280.08:18:17.44#ibcon#read 3, iclass 24, count 2 2006.280.08:18:17.44#ibcon#about to read 4, iclass 24, count 2 2006.280.08:18:17.44#ibcon#read 4, iclass 24, count 2 2006.280.08:18:17.44#ibcon#about to read 5, iclass 24, count 2 2006.280.08:18:17.44#ibcon#read 5, iclass 24, count 2 2006.280.08:18:17.44#ibcon#about to read 6, iclass 24, count 2 2006.280.08:18:17.44#ibcon#read 6, iclass 24, count 2 2006.280.08:18:17.44#ibcon#end of sib2, iclass 24, count 2 2006.280.08:18:17.44#ibcon#*after write, iclass 24, count 2 2006.280.08:18:17.44#ibcon#*before return 0, iclass 24, count 2 2006.280.08:18:17.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:17.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.280.08:18:17.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.280.08:18:17.44#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:17.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:17.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:17.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:17.55#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:18:17.55#ibcon#first serial, iclass 24, count 0 2006.280.08:18:17.55#ibcon#enter sib2, iclass 24, count 0 2006.280.08:18:17.55#ibcon#flushed, iclass 24, count 0 2006.280.08:18:17.55#ibcon#about to write, iclass 24, count 0 2006.280.08:18:17.55#ibcon#wrote, iclass 24, count 0 2006.280.08:18:17.55#ibcon#about to read 3, iclass 24, count 0 2006.280.08:18:17.57#ibcon#read 3, iclass 24, count 0 2006.280.08:18:17.57#ibcon#about to read 4, iclass 24, count 0 2006.280.08:18:17.57#ibcon#read 4, iclass 24, count 0 2006.280.08:18:17.57#ibcon#about to read 5, iclass 24, count 0 2006.280.08:18:17.57#ibcon#read 5, iclass 24, count 0 2006.280.08:18:17.57#ibcon#about to read 6, iclass 24, count 0 2006.280.08:18:17.57#ibcon#read 6, iclass 24, count 0 2006.280.08:18:17.57#ibcon#end of sib2, iclass 24, count 0 2006.280.08:18:17.57#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:18:17.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:18:17.57#ibcon#[27=USB\r\n] 2006.280.08:18:17.57#ibcon#*before write, iclass 24, count 0 2006.280.08:18:17.57#ibcon#enter sib2, iclass 24, count 0 2006.280.08:18:17.57#ibcon#flushed, iclass 24, count 0 2006.280.08:18:17.57#ibcon#about to write, iclass 24, count 0 2006.280.08:18:17.57#ibcon#wrote, iclass 24, count 0 2006.280.08:18:17.57#ibcon#about to read 3, iclass 24, count 0 2006.280.08:18:17.60#ibcon#read 3, iclass 24, count 0 2006.280.08:18:17.60#ibcon#about to read 4, iclass 24, count 0 2006.280.08:18:17.60#ibcon#read 4, iclass 24, count 0 2006.280.08:18:17.60#ibcon#about to read 5, iclass 24, count 0 2006.280.08:18:17.60#ibcon#read 5, iclass 24, count 0 2006.280.08:18:17.60#ibcon#about to read 6, iclass 24, count 0 2006.280.08:18:17.60#ibcon#read 6, iclass 24, count 0 2006.280.08:18:17.60#ibcon#end of sib2, iclass 24, count 0 2006.280.08:18:17.60#ibcon#*after write, iclass 24, count 0 2006.280.08:18:17.60#ibcon#*before return 0, iclass 24, count 0 2006.280.08:18:17.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:17.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.280.08:18:17.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:18:17.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:18:17.60$vc4f8/vblo=3,656.99 2006.280.08:18:17.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.280.08:18:17.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.280.08:18:17.60#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:17.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:17.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:17.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:17.60#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:18:17.60#ibcon#first serial, iclass 26, count 0 2006.280.08:18:17.60#ibcon#enter sib2, iclass 26, count 0 2006.280.08:18:17.60#ibcon#flushed, iclass 26, count 0 2006.280.08:18:17.60#ibcon#about to write, iclass 26, count 0 2006.280.08:18:17.60#ibcon#wrote, iclass 26, count 0 2006.280.08:18:17.60#ibcon#about to read 3, iclass 26, count 0 2006.280.08:18:17.62#ibcon#read 3, iclass 26, count 0 2006.280.08:18:17.62#ibcon#about to read 4, iclass 26, count 0 2006.280.08:18:17.62#ibcon#read 4, iclass 26, count 0 2006.280.08:18:17.62#ibcon#about to read 5, iclass 26, count 0 2006.280.08:18:17.62#ibcon#read 5, iclass 26, count 0 2006.280.08:18:17.62#ibcon#about to read 6, iclass 26, count 0 2006.280.08:18:17.62#ibcon#read 6, iclass 26, count 0 2006.280.08:18:17.62#ibcon#end of sib2, iclass 26, count 0 2006.280.08:18:17.62#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:18:17.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:18:17.62#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:18:17.62#ibcon#*before write, iclass 26, count 0 2006.280.08:18:17.62#ibcon#enter sib2, iclass 26, count 0 2006.280.08:18:17.62#ibcon#flushed, iclass 26, count 0 2006.280.08:18:17.62#ibcon#about to write, iclass 26, count 0 2006.280.08:18:17.62#ibcon#wrote, iclass 26, count 0 2006.280.08:18:17.62#ibcon#about to read 3, iclass 26, count 0 2006.280.08:18:17.66#ibcon#read 3, iclass 26, count 0 2006.280.08:18:17.66#ibcon#about to read 4, iclass 26, count 0 2006.280.08:18:17.66#ibcon#read 4, iclass 26, count 0 2006.280.08:18:17.66#ibcon#about to read 5, iclass 26, count 0 2006.280.08:18:17.66#ibcon#read 5, iclass 26, count 0 2006.280.08:18:17.66#ibcon#about to read 6, iclass 26, count 0 2006.280.08:18:17.66#ibcon#read 6, iclass 26, count 0 2006.280.08:18:17.66#ibcon#end of sib2, iclass 26, count 0 2006.280.08:18:17.66#ibcon#*after write, iclass 26, count 0 2006.280.08:18:17.66#ibcon#*before return 0, iclass 26, count 0 2006.280.08:18:17.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:17.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.280.08:18:17.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:18:17.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:18:17.67$vc4f8/vb=3,4 2006.280.08:18:17.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.280.08:18:17.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.280.08:18:17.67#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:17.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:17.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:17.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:17.71#ibcon#enter wrdev, iclass 28, count 2 2006.280.08:18:17.71#ibcon#first serial, iclass 28, count 2 2006.280.08:18:17.71#ibcon#enter sib2, iclass 28, count 2 2006.280.08:18:17.71#ibcon#flushed, iclass 28, count 2 2006.280.08:18:17.71#ibcon#about to write, iclass 28, count 2 2006.280.08:18:17.71#ibcon#wrote, iclass 28, count 2 2006.280.08:18:17.71#ibcon#about to read 3, iclass 28, count 2 2006.280.08:18:17.73#ibcon#read 3, iclass 28, count 2 2006.280.08:18:17.73#ibcon#about to read 4, iclass 28, count 2 2006.280.08:18:17.73#ibcon#read 4, iclass 28, count 2 2006.280.08:18:17.73#ibcon#about to read 5, iclass 28, count 2 2006.280.08:18:17.73#ibcon#read 5, iclass 28, count 2 2006.280.08:18:17.73#ibcon#about to read 6, iclass 28, count 2 2006.280.08:18:17.73#ibcon#read 6, iclass 28, count 2 2006.280.08:18:17.73#ibcon#end of sib2, iclass 28, count 2 2006.280.08:18:17.73#ibcon#*mode == 0, iclass 28, count 2 2006.280.08:18:17.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.280.08:18:17.73#ibcon#[27=AT03-04\r\n] 2006.280.08:18:17.73#ibcon#*before write, iclass 28, count 2 2006.280.08:18:17.73#ibcon#enter sib2, iclass 28, count 2 2006.280.08:18:17.73#ibcon#flushed, iclass 28, count 2 2006.280.08:18:17.73#ibcon#about to write, iclass 28, count 2 2006.280.08:18:17.73#ibcon#wrote, iclass 28, count 2 2006.280.08:18:17.73#ibcon#about to read 3, iclass 28, count 2 2006.280.08:18:17.77#ibcon#read 3, iclass 28, count 2 2006.280.08:18:17.77#ibcon#about to read 4, iclass 28, count 2 2006.280.08:18:17.77#ibcon#read 4, iclass 28, count 2 2006.280.08:18:17.77#ibcon#about to read 5, iclass 28, count 2 2006.280.08:18:17.77#ibcon#read 5, iclass 28, count 2 2006.280.08:18:17.77#ibcon#about to read 6, iclass 28, count 2 2006.280.08:18:17.77#ibcon#read 6, iclass 28, count 2 2006.280.08:18:17.77#ibcon#end of sib2, iclass 28, count 2 2006.280.08:18:17.77#ibcon#*after write, iclass 28, count 2 2006.280.08:18:17.77#ibcon#*before return 0, iclass 28, count 2 2006.280.08:18:17.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:17.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.280.08:18:17.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.280.08:18:17.77#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:17.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:17.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:17.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:17.88#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:18:17.88#ibcon#first serial, iclass 28, count 0 2006.280.08:18:17.88#ibcon#enter sib2, iclass 28, count 0 2006.280.08:18:17.88#ibcon#flushed, iclass 28, count 0 2006.280.08:18:17.88#ibcon#about to write, iclass 28, count 0 2006.280.08:18:17.88#ibcon#wrote, iclass 28, count 0 2006.280.08:18:17.88#ibcon#about to read 3, iclass 28, count 0 2006.280.08:18:17.90#ibcon#read 3, iclass 28, count 0 2006.280.08:18:17.90#ibcon#about to read 4, iclass 28, count 0 2006.280.08:18:17.90#ibcon#read 4, iclass 28, count 0 2006.280.08:18:17.90#ibcon#about to read 5, iclass 28, count 0 2006.280.08:18:17.90#ibcon#read 5, iclass 28, count 0 2006.280.08:18:17.90#ibcon#about to read 6, iclass 28, count 0 2006.280.08:18:17.90#ibcon#read 6, iclass 28, count 0 2006.280.08:18:17.90#ibcon#end of sib2, iclass 28, count 0 2006.280.08:18:17.90#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:18:17.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:18:17.90#ibcon#[27=USB\r\n] 2006.280.08:18:17.90#ibcon#*before write, iclass 28, count 0 2006.280.08:18:17.90#ibcon#enter sib2, iclass 28, count 0 2006.280.08:18:17.90#ibcon#flushed, iclass 28, count 0 2006.280.08:18:17.90#ibcon#about to write, iclass 28, count 0 2006.280.08:18:17.90#ibcon#wrote, iclass 28, count 0 2006.280.08:18:17.90#ibcon#about to read 3, iclass 28, count 0 2006.280.08:18:17.93#ibcon#read 3, iclass 28, count 0 2006.280.08:18:17.93#ibcon#about to read 4, iclass 28, count 0 2006.280.08:18:17.93#ibcon#read 4, iclass 28, count 0 2006.280.08:18:17.93#ibcon#about to read 5, iclass 28, count 0 2006.280.08:18:17.93#ibcon#read 5, iclass 28, count 0 2006.280.08:18:17.93#ibcon#about to read 6, iclass 28, count 0 2006.280.08:18:17.93#ibcon#read 6, iclass 28, count 0 2006.280.08:18:17.93#ibcon#end of sib2, iclass 28, count 0 2006.280.08:18:17.93#ibcon#*after write, iclass 28, count 0 2006.280.08:18:17.93#ibcon#*before return 0, iclass 28, count 0 2006.280.08:18:17.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:17.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.280.08:18:17.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:18:17.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:18:17.93$vc4f8/vblo=4,712.99 2006.280.08:18:17.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:18:17.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:18:17.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:17.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:17.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:17.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:17.93#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:18:17.93#ibcon#first serial, iclass 30, count 0 2006.280.08:18:17.93#ibcon#enter sib2, iclass 30, count 0 2006.280.08:18:17.93#ibcon#flushed, iclass 30, count 0 2006.280.08:18:17.93#ibcon#about to write, iclass 30, count 0 2006.280.08:18:17.93#ibcon#wrote, iclass 30, count 0 2006.280.08:18:17.93#ibcon#about to read 3, iclass 30, count 0 2006.280.08:18:17.95#ibcon#read 3, iclass 30, count 0 2006.280.08:18:17.95#ibcon#about to read 4, iclass 30, count 0 2006.280.08:18:17.95#ibcon#read 4, iclass 30, count 0 2006.280.08:18:17.95#ibcon#about to read 5, iclass 30, count 0 2006.280.08:18:17.95#ibcon#read 5, iclass 30, count 0 2006.280.08:18:17.95#ibcon#about to read 6, iclass 30, count 0 2006.280.08:18:17.95#ibcon#read 6, iclass 30, count 0 2006.280.08:18:17.95#ibcon#end of sib2, iclass 30, count 0 2006.280.08:18:17.95#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:18:17.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:18:17.95#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:18:17.95#ibcon#*before write, iclass 30, count 0 2006.280.08:18:17.95#ibcon#enter sib2, iclass 30, count 0 2006.280.08:18:17.95#ibcon#flushed, iclass 30, count 0 2006.280.08:18:17.95#ibcon#about to write, iclass 30, count 0 2006.280.08:18:17.95#ibcon#wrote, iclass 30, count 0 2006.280.08:18:17.95#ibcon#about to read 3, iclass 30, count 0 2006.280.08:18:17.99#ibcon#read 3, iclass 30, count 0 2006.280.08:18:17.99#ibcon#about to read 4, iclass 30, count 0 2006.280.08:18:17.99#ibcon#read 4, iclass 30, count 0 2006.280.08:18:17.99#ibcon#about to read 5, iclass 30, count 0 2006.280.08:18:17.99#ibcon#read 5, iclass 30, count 0 2006.280.08:18:17.99#ibcon#about to read 6, iclass 30, count 0 2006.280.08:18:17.99#ibcon#read 6, iclass 30, count 0 2006.280.08:18:17.99#ibcon#end of sib2, iclass 30, count 0 2006.280.08:18:17.99#ibcon#*after write, iclass 30, count 0 2006.280.08:18:17.99#ibcon#*before return 0, iclass 30, count 0 2006.280.08:18:17.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:17.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:18:17.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:18:17.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:18:17.99$vc4f8/vb=4,4 2006.280.08:18:17.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:18:17.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:18:17.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:17.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:18.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:18.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:18.05#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:18:18.05#ibcon#first serial, iclass 32, count 2 2006.280.08:18:18.05#ibcon#enter sib2, iclass 32, count 2 2006.280.08:18:18.05#ibcon#flushed, iclass 32, count 2 2006.280.08:18:18.05#ibcon#about to write, iclass 32, count 2 2006.280.08:18:18.05#ibcon#wrote, iclass 32, count 2 2006.280.08:18:18.05#ibcon#about to read 3, iclass 32, count 2 2006.280.08:18:18.08#ibcon#read 3, iclass 32, count 2 2006.280.08:18:18.08#ibcon#about to read 4, iclass 32, count 2 2006.280.08:18:18.08#ibcon#read 4, iclass 32, count 2 2006.280.08:18:18.08#ibcon#about to read 5, iclass 32, count 2 2006.280.08:18:18.08#ibcon#read 5, iclass 32, count 2 2006.280.08:18:18.08#ibcon#about to read 6, iclass 32, count 2 2006.280.08:18:18.08#ibcon#read 6, iclass 32, count 2 2006.280.08:18:18.08#ibcon#end of sib2, iclass 32, count 2 2006.280.08:18:18.08#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:18:18.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:18:18.08#ibcon#[27=AT04-04\r\n] 2006.280.08:18:18.08#ibcon#*before write, iclass 32, count 2 2006.280.08:18:18.08#ibcon#enter sib2, iclass 32, count 2 2006.280.08:18:18.08#ibcon#flushed, iclass 32, count 2 2006.280.08:18:18.08#ibcon#about to write, iclass 32, count 2 2006.280.08:18:18.08#ibcon#wrote, iclass 32, count 2 2006.280.08:18:18.08#ibcon#about to read 3, iclass 32, count 2 2006.280.08:18:18.11#ibcon#read 3, iclass 32, count 2 2006.280.08:18:18.11#ibcon#about to read 4, iclass 32, count 2 2006.280.08:18:18.11#ibcon#read 4, iclass 32, count 2 2006.280.08:18:18.11#ibcon#about to read 5, iclass 32, count 2 2006.280.08:18:18.11#ibcon#read 5, iclass 32, count 2 2006.280.08:18:18.11#ibcon#about to read 6, iclass 32, count 2 2006.280.08:18:18.11#ibcon#read 6, iclass 32, count 2 2006.280.08:18:18.11#ibcon#end of sib2, iclass 32, count 2 2006.280.08:18:18.11#ibcon#*after write, iclass 32, count 2 2006.280.08:18:18.11#ibcon#*before return 0, iclass 32, count 2 2006.280.08:18:18.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:18.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:18:18.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:18:18.11#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:18.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:18.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:18.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:18.23#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:18:18.23#ibcon#first serial, iclass 32, count 0 2006.280.08:18:18.23#ibcon#enter sib2, iclass 32, count 0 2006.280.08:18:18.23#ibcon#flushed, iclass 32, count 0 2006.280.08:18:18.23#ibcon#about to write, iclass 32, count 0 2006.280.08:18:18.23#ibcon#wrote, iclass 32, count 0 2006.280.08:18:18.23#ibcon#about to read 3, iclass 32, count 0 2006.280.08:18:18.25#ibcon#read 3, iclass 32, count 0 2006.280.08:18:18.25#ibcon#about to read 4, iclass 32, count 0 2006.280.08:18:18.25#ibcon#read 4, iclass 32, count 0 2006.280.08:18:18.25#ibcon#about to read 5, iclass 32, count 0 2006.280.08:18:18.25#ibcon#read 5, iclass 32, count 0 2006.280.08:18:18.25#ibcon#about to read 6, iclass 32, count 0 2006.280.08:18:18.25#ibcon#read 6, iclass 32, count 0 2006.280.08:18:18.25#ibcon#end of sib2, iclass 32, count 0 2006.280.08:18:18.25#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:18:18.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:18:18.25#ibcon#[27=USB\r\n] 2006.280.08:18:18.25#ibcon#*before write, iclass 32, count 0 2006.280.08:18:18.25#ibcon#enter sib2, iclass 32, count 0 2006.280.08:18:18.25#ibcon#flushed, iclass 32, count 0 2006.280.08:18:18.25#ibcon#about to write, iclass 32, count 0 2006.280.08:18:18.25#ibcon#wrote, iclass 32, count 0 2006.280.08:18:18.25#ibcon#about to read 3, iclass 32, count 0 2006.280.08:18:18.29#ibcon#read 3, iclass 32, count 0 2006.280.08:18:18.29#ibcon#about to read 4, iclass 32, count 0 2006.280.08:18:18.29#ibcon#read 4, iclass 32, count 0 2006.280.08:18:18.29#ibcon#about to read 5, iclass 32, count 0 2006.280.08:18:18.29#ibcon#read 5, iclass 32, count 0 2006.280.08:18:18.29#ibcon#about to read 6, iclass 32, count 0 2006.280.08:18:18.29#ibcon#read 6, iclass 32, count 0 2006.280.08:18:18.29#ibcon#end of sib2, iclass 32, count 0 2006.280.08:18:18.29#ibcon#*after write, iclass 32, count 0 2006.280.08:18:18.29#ibcon#*before return 0, iclass 32, count 0 2006.280.08:18:18.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:18.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:18:18.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:18:18.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:18:18.29$vc4f8/vblo=5,744.99 2006.280.08:18:18.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.280.08:18:18.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.280.08:18:18.29#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:18.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:18.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:18.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:18.29#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:18:18.29#ibcon#first serial, iclass 34, count 0 2006.280.08:18:18.29#ibcon#enter sib2, iclass 34, count 0 2006.280.08:18:18.29#ibcon#flushed, iclass 34, count 0 2006.280.08:18:18.29#ibcon#about to write, iclass 34, count 0 2006.280.08:18:18.29#ibcon#wrote, iclass 34, count 0 2006.280.08:18:18.29#ibcon#about to read 3, iclass 34, count 0 2006.280.08:18:18.30#ibcon#read 3, iclass 34, count 0 2006.280.08:18:18.30#ibcon#about to read 4, iclass 34, count 0 2006.280.08:18:18.30#ibcon#read 4, iclass 34, count 0 2006.280.08:18:18.30#ibcon#about to read 5, iclass 34, count 0 2006.280.08:18:18.30#ibcon#read 5, iclass 34, count 0 2006.280.08:18:18.30#ibcon#about to read 6, iclass 34, count 0 2006.280.08:18:18.30#ibcon#read 6, iclass 34, count 0 2006.280.08:18:18.30#ibcon#end of sib2, iclass 34, count 0 2006.280.08:18:18.30#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:18:18.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:18:18.30#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:18:18.30#ibcon#*before write, iclass 34, count 0 2006.280.08:18:18.33#ibcon#enter sib2, iclass 34, count 0 2006.280.08:18:18.33#ibcon#flushed, iclass 34, count 0 2006.280.08:18:18.33#ibcon#about to write, iclass 34, count 0 2006.280.08:18:18.33#ibcon#wrote, iclass 34, count 0 2006.280.08:18:18.33#ibcon#about to read 3, iclass 34, count 0 2006.280.08:18:18.37#ibcon#read 3, iclass 34, count 0 2006.280.08:18:18.37#ibcon#about to read 4, iclass 34, count 0 2006.280.08:18:18.37#ibcon#read 4, iclass 34, count 0 2006.280.08:18:18.37#ibcon#about to read 5, iclass 34, count 0 2006.280.08:18:18.37#ibcon#read 5, iclass 34, count 0 2006.280.08:18:18.37#ibcon#about to read 6, iclass 34, count 0 2006.280.08:18:18.37#ibcon#read 6, iclass 34, count 0 2006.280.08:18:18.37#ibcon#end of sib2, iclass 34, count 0 2006.280.08:18:18.37#ibcon#*after write, iclass 34, count 0 2006.280.08:18:18.37#ibcon#*before return 0, iclass 34, count 0 2006.280.08:18:18.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:18.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.280.08:18:18.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:18:18.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:18:18.37$vc4f8/vb=5,4 2006.280.08:18:18.37#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.280.08:18:18.37#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.280.08:18:18.37#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:18.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:18.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:18.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:18.41#ibcon#enter wrdev, iclass 36, count 2 2006.280.08:18:18.41#ibcon#first serial, iclass 36, count 2 2006.280.08:18:18.41#ibcon#enter sib2, iclass 36, count 2 2006.280.08:18:18.41#ibcon#flushed, iclass 36, count 2 2006.280.08:18:18.41#ibcon#about to write, iclass 36, count 2 2006.280.08:18:18.41#ibcon#wrote, iclass 36, count 2 2006.280.08:18:18.41#ibcon#about to read 3, iclass 36, count 2 2006.280.08:18:18.43#ibcon#read 3, iclass 36, count 2 2006.280.08:18:18.43#ibcon#about to read 4, iclass 36, count 2 2006.280.08:18:18.43#ibcon#read 4, iclass 36, count 2 2006.280.08:18:18.43#ibcon#about to read 5, iclass 36, count 2 2006.280.08:18:18.43#ibcon#read 5, iclass 36, count 2 2006.280.08:18:18.43#ibcon#about to read 6, iclass 36, count 2 2006.280.08:18:18.43#ibcon#read 6, iclass 36, count 2 2006.280.08:18:18.43#ibcon#end of sib2, iclass 36, count 2 2006.280.08:18:18.43#ibcon#*mode == 0, iclass 36, count 2 2006.280.08:18:18.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.280.08:18:18.43#ibcon#[27=AT05-04\r\n] 2006.280.08:18:18.43#ibcon#*before write, iclass 36, count 2 2006.280.08:18:18.43#ibcon#enter sib2, iclass 36, count 2 2006.280.08:18:18.43#ibcon#flushed, iclass 36, count 2 2006.280.08:18:18.43#ibcon#about to write, iclass 36, count 2 2006.280.08:18:18.43#ibcon#wrote, iclass 36, count 2 2006.280.08:18:18.43#ibcon#about to read 3, iclass 36, count 2 2006.280.08:18:18.46#ibcon#read 3, iclass 36, count 2 2006.280.08:18:18.46#ibcon#about to read 4, iclass 36, count 2 2006.280.08:18:18.46#ibcon#read 4, iclass 36, count 2 2006.280.08:18:18.46#ibcon#about to read 5, iclass 36, count 2 2006.280.08:18:18.46#ibcon#read 5, iclass 36, count 2 2006.280.08:18:18.46#ibcon#about to read 6, iclass 36, count 2 2006.280.08:18:18.46#ibcon#read 6, iclass 36, count 2 2006.280.08:18:18.46#ibcon#end of sib2, iclass 36, count 2 2006.280.08:18:18.46#ibcon#*after write, iclass 36, count 2 2006.280.08:18:18.46#ibcon#*before return 0, iclass 36, count 2 2006.280.08:18:18.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:18.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.280.08:18:18.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.280.08:18:18.46#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:18.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:18.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:18.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:18.58#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:18:18.58#ibcon#first serial, iclass 36, count 0 2006.280.08:18:18.58#ibcon#enter sib2, iclass 36, count 0 2006.280.08:18:18.58#ibcon#flushed, iclass 36, count 0 2006.280.08:18:18.58#ibcon#about to write, iclass 36, count 0 2006.280.08:18:18.59#ibcon#wrote, iclass 36, count 0 2006.280.08:18:18.59#ibcon#about to read 3, iclass 36, count 0 2006.280.08:18:18.60#ibcon#read 3, iclass 36, count 0 2006.280.08:18:18.60#ibcon#about to read 4, iclass 36, count 0 2006.280.08:18:18.60#ibcon#read 4, iclass 36, count 0 2006.280.08:18:18.60#ibcon#about to read 5, iclass 36, count 0 2006.280.08:18:18.60#ibcon#read 5, iclass 36, count 0 2006.280.08:18:18.60#ibcon#about to read 6, iclass 36, count 0 2006.280.08:18:18.60#ibcon#read 6, iclass 36, count 0 2006.280.08:18:18.60#ibcon#end of sib2, iclass 36, count 0 2006.280.08:18:18.60#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:18:18.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:18:18.60#ibcon#[27=USB\r\n] 2006.280.08:18:18.60#ibcon#*before write, iclass 36, count 0 2006.280.08:18:18.60#ibcon#enter sib2, iclass 36, count 0 2006.280.08:18:18.60#ibcon#flushed, iclass 36, count 0 2006.280.08:18:18.60#ibcon#about to write, iclass 36, count 0 2006.280.08:18:18.60#ibcon#wrote, iclass 36, count 0 2006.280.08:18:18.60#ibcon#about to read 3, iclass 36, count 0 2006.280.08:18:18.63#ibcon#read 3, iclass 36, count 0 2006.280.08:18:18.63#ibcon#about to read 4, iclass 36, count 0 2006.280.08:18:18.63#ibcon#read 4, iclass 36, count 0 2006.280.08:18:18.63#ibcon#about to read 5, iclass 36, count 0 2006.280.08:18:18.63#ibcon#read 5, iclass 36, count 0 2006.280.08:18:18.63#ibcon#about to read 6, iclass 36, count 0 2006.280.08:18:18.63#ibcon#read 6, iclass 36, count 0 2006.280.08:18:18.63#ibcon#end of sib2, iclass 36, count 0 2006.280.08:18:18.63#ibcon#*after write, iclass 36, count 0 2006.280.08:18:18.63#ibcon#*before return 0, iclass 36, count 0 2006.280.08:18:18.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:18.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.280.08:18:18.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:18:18.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:18:18.63$vc4f8/vblo=6,752.99 2006.280.08:18:18.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.280.08:18:18.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.280.08:18:18.63#ibcon#ireg 17 cls_cnt 0 2006.280.08:18:18.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:18.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:18.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:18.63#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:18:18.63#ibcon#first serial, iclass 38, count 0 2006.280.08:18:18.63#ibcon#enter sib2, iclass 38, count 0 2006.280.08:18:18.63#ibcon#flushed, iclass 38, count 0 2006.280.08:18:18.63#ibcon#about to write, iclass 38, count 0 2006.280.08:18:18.63#ibcon#wrote, iclass 38, count 0 2006.280.08:18:18.63#ibcon#about to read 3, iclass 38, count 0 2006.280.08:18:18.65#ibcon#read 3, iclass 38, count 0 2006.280.08:18:18.66#ibcon#about to read 4, iclass 38, count 0 2006.280.08:18:18.66#ibcon#read 4, iclass 38, count 0 2006.280.08:18:18.66#ibcon#about to read 5, iclass 38, count 0 2006.280.08:18:18.66#ibcon#read 5, iclass 38, count 0 2006.280.08:18:18.66#ibcon#about to read 6, iclass 38, count 0 2006.280.08:18:18.66#ibcon#read 6, iclass 38, count 0 2006.280.08:18:18.66#ibcon#end of sib2, iclass 38, count 0 2006.280.08:18:18.66#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:18:18.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:18:18.66#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:18:18.66#ibcon#*before write, iclass 38, count 0 2006.280.08:18:18.66#ibcon#enter sib2, iclass 38, count 0 2006.280.08:18:18.66#ibcon#flushed, iclass 38, count 0 2006.280.08:18:18.66#ibcon#about to write, iclass 38, count 0 2006.280.08:18:18.66#ibcon#wrote, iclass 38, count 0 2006.280.08:18:18.66#ibcon#about to read 3, iclass 38, count 0 2006.280.08:18:18.69#ibcon#read 3, iclass 38, count 0 2006.280.08:18:18.69#ibcon#about to read 4, iclass 38, count 0 2006.280.08:18:18.69#ibcon#read 4, iclass 38, count 0 2006.280.08:18:18.69#ibcon#about to read 5, iclass 38, count 0 2006.280.08:18:18.69#ibcon#read 5, iclass 38, count 0 2006.280.08:18:18.69#ibcon#about to read 6, iclass 38, count 0 2006.280.08:18:18.69#ibcon#read 6, iclass 38, count 0 2006.280.08:18:18.69#ibcon#end of sib2, iclass 38, count 0 2006.280.08:18:18.69#ibcon#*after write, iclass 38, count 0 2006.280.08:18:18.69#ibcon#*before return 0, iclass 38, count 0 2006.280.08:18:18.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:18.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.280.08:18:18.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:18:18.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:18:18.69$vc4f8/vb=6,4 2006.280.08:18:18.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.280.08:18:18.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.280.08:18:18.70#ibcon#ireg 11 cls_cnt 2 2006.280.08:18:18.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:18.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:18.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:18.74#ibcon#enter wrdev, iclass 40, count 2 2006.280.08:18:18.74#ibcon#first serial, iclass 40, count 2 2006.280.08:18:18.74#ibcon#enter sib2, iclass 40, count 2 2006.280.08:18:18.74#ibcon#flushed, iclass 40, count 2 2006.280.08:18:18.74#ibcon#about to write, iclass 40, count 2 2006.280.08:18:18.74#ibcon#wrote, iclass 40, count 2 2006.280.08:18:18.74#ibcon#about to read 3, iclass 40, count 2 2006.280.08:18:18.76#ibcon#read 3, iclass 40, count 2 2006.280.08:18:18.76#ibcon#about to read 4, iclass 40, count 2 2006.280.08:18:18.76#ibcon#read 4, iclass 40, count 2 2006.280.08:18:18.76#ibcon#about to read 5, iclass 40, count 2 2006.280.08:18:18.76#ibcon#read 5, iclass 40, count 2 2006.280.08:18:18.76#ibcon#about to read 6, iclass 40, count 2 2006.280.08:18:18.76#ibcon#read 6, iclass 40, count 2 2006.280.08:18:18.76#ibcon#end of sib2, iclass 40, count 2 2006.280.08:18:18.76#ibcon#*mode == 0, iclass 40, count 2 2006.280.08:18:18.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.280.08:18:18.76#ibcon#[27=AT06-04\r\n] 2006.280.08:18:18.76#ibcon#*before write, iclass 40, count 2 2006.280.08:18:18.76#ibcon#enter sib2, iclass 40, count 2 2006.280.08:18:18.76#ibcon#flushed, iclass 40, count 2 2006.280.08:18:18.76#ibcon#about to write, iclass 40, count 2 2006.280.08:18:18.76#ibcon#wrote, iclass 40, count 2 2006.280.08:18:18.76#ibcon#about to read 3, iclass 40, count 2 2006.280.08:18:18.79#ibcon#read 3, iclass 40, count 2 2006.280.08:18:18.79#ibcon#about to read 4, iclass 40, count 2 2006.280.08:18:18.79#ibcon#read 4, iclass 40, count 2 2006.280.08:18:18.79#ibcon#about to read 5, iclass 40, count 2 2006.280.08:18:18.79#ibcon#read 5, iclass 40, count 2 2006.280.08:18:18.79#ibcon#about to read 6, iclass 40, count 2 2006.280.08:18:18.79#ibcon#read 6, iclass 40, count 2 2006.280.08:18:18.79#ibcon#end of sib2, iclass 40, count 2 2006.280.08:18:18.79#ibcon#*after write, iclass 40, count 2 2006.280.08:18:18.79#ibcon#*before return 0, iclass 40, count 2 2006.280.08:18:18.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:18.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.280.08:18:18.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.280.08:18:18.79#ibcon#ireg 7 cls_cnt 0 2006.280.08:18:18.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:18.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:18.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:18.91#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:18:18.91#ibcon#first serial, iclass 40, count 0 2006.280.08:18:18.91#ibcon#enter sib2, iclass 40, count 0 2006.280.08:18:18.91#ibcon#flushed, iclass 40, count 0 2006.280.08:18:18.91#ibcon#about to write, iclass 40, count 0 2006.280.08:18:18.91#ibcon#wrote, iclass 40, count 0 2006.280.08:18:18.91#ibcon#about to read 3, iclass 40, count 0 2006.280.08:18:18.93#ibcon#read 3, iclass 40, count 0 2006.280.08:18:18.93#ibcon#about to read 4, iclass 40, count 0 2006.280.08:18:18.93#ibcon#read 4, iclass 40, count 0 2006.280.08:18:18.93#ibcon#about to read 5, iclass 40, count 0 2006.280.08:18:18.93#ibcon#read 5, iclass 40, count 0 2006.280.08:18:18.93#ibcon#about to read 6, iclass 40, count 0 2006.280.08:18:18.93#ibcon#read 6, iclass 40, count 0 2006.280.08:18:18.93#ibcon#end of sib2, iclass 40, count 0 2006.280.08:18:18.93#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:18:18.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:18:18.93#ibcon#[27=USB\r\n] 2006.280.08:18:18.93#ibcon#*before write, iclass 40, count 0 2006.280.08:18:18.93#ibcon#enter sib2, iclass 40, count 0 2006.280.08:18:18.93#ibcon#flushed, iclass 40, count 0 2006.280.08:18:18.93#ibcon#about to write, iclass 40, count 0 2006.280.08:18:18.93#ibcon#wrote, iclass 40, count 0 2006.280.08:18:18.93#ibcon#about to read 3, iclass 40, count 0 2006.280.08:18:18.96#ibcon#read 3, iclass 40, count 0 2006.280.08:18:18.96#ibcon#about to read 4, iclass 40, count 0 2006.280.08:18:18.96#ibcon#read 4, iclass 40, count 0 2006.280.08:18:18.96#ibcon#about to read 5, iclass 40, count 0 2006.280.08:18:18.96#ibcon#read 5, iclass 40, count 0 2006.280.08:18:18.96#ibcon#about to read 6, iclass 40, count 0 2006.280.08:18:18.96#ibcon#read 6, iclass 40, count 0 2006.280.08:18:18.96#ibcon#end of sib2, iclass 40, count 0 2006.280.08:18:18.96#ibcon#*after write, iclass 40, count 0 2006.280.08:18:18.96#ibcon#*before return 0, iclass 40, count 0 2006.280.08:18:18.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:18.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.280.08:18:18.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:18:18.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:18:18.96$vc4f8/vabw=wide 2006.280.08:18:18.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.280.08:18:18.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.280.08:18:18.96#ibcon#ireg 8 cls_cnt 0 2006.280.08:18:18.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:18.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:18.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:18.96#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:18:18.96#ibcon#first serial, iclass 4, count 0 2006.280.08:18:18.96#ibcon#enter sib2, iclass 4, count 0 2006.280.08:18:18.96#ibcon#flushed, iclass 4, count 0 2006.280.08:18:18.96#ibcon#about to write, iclass 4, count 0 2006.280.08:18:18.96#ibcon#wrote, iclass 4, count 0 2006.280.08:18:18.96#ibcon#about to read 3, iclass 4, count 0 2006.280.08:18:18.98#ibcon#read 3, iclass 4, count 0 2006.280.08:18:18.98#ibcon#about to read 4, iclass 4, count 0 2006.280.08:18:18.98#ibcon#read 4, iclass 4, count 0 2006.280.08:18:18.98#ibcon#about to read 5, iclass 4, count 0 2006.280.08:18:18.98#ibcon#read 5, iclass 4, count 0 2006.280.08:18:18.98#ibcon#about to read 6, iclass 4, count 0 2006.280.08:18:18.98#ibcon#read 6, iclass 4, count 0 2006.280.08:18:18.98#ibcon#end of sib2, iclass 4, count 0 2006.280.08:18:18.98#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:18:18.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:18:18.98#ibcon#[25=BW32\r\n] 2006.280.08:18:18.98#ibcon#*before write, iclass 4, count 0 2006.280.08:18:18.98#ibcon#enter sib2, iclass 4, count 0 2006.280.08:18:18.98#ibcon#flushed, iclass 4, count 0 2006.280.08:18:18.98#ibcon#about to write, iclass 4, count 0 2006.280.08:18:18.98#ibcon#wrote, iclass 4, count 0 2006.280.08:18:18.98#ibcon#about to read 3, iclass 4, count 0 2006.280.08:18:19.01#ibcon#read 3, iclass 4, count 0 2006.280.08:18:19.01#ibcon#about to read 4, iclass 4, count 0 2006.280.08:18:19.01#ibcon#read 4, iclass 4, count 0 2006.280.08:18:19.01#ibcon#about to read 5, iclass 4, count 0 2006.280.08:18:19.01#ibcon#read 5, iclass 4, count 0 2006.280.08:18:19.01#ibcon#about to read 6, iclass 4, count 0 2006.280.08:18:19.01#ibcon#read 6, iclass 4, count 0 2006.280.08:18:19.01#ibcon#end of sib2, iclass 4, count 0 2006.280.08:18:19.01#ibcon#*after write, iclass 4, count 0 2006.280.08:18:19.01#ibcon#*before return 0, iclass 4, count 0 2006.280.08:18:19.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:19.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.280.08:18:19.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:18:19.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:18:19.01$vc4f8/vbbw=wide 2006.280.08:18:19.01#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:18:19.01#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:18:19.01#ibcon#ireg 8 cls_cnt 0 2006.280.08:18:19.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:18:19.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:18:19.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:18:19.08#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:18:19.08#ibcon#first serial, iclass 6, count 0 2006.280.08:18:19.08#ibcon#enter sib2, iclass 6, count 0 2006.280.08:18:19.08#ibcon#flushed, iclass 6, count 0 2006.280.08:18:19.08#ibcon#about to write, iclass 6, count 0 2006.280.08:18:19.08#ibcon#wrote, iclass 6, count 0 2006.280.08:18:19.08#ibcon#about to read 3, iclass 6, count 0 2006.280.08:18:19.10#ibcon#read 3, iclass 6, count 0 2006.280.08:18:19.10#ibcon#about to read 4, iclass 6, count 0 2006.280.08:18:19.10#ibcon#read 4, iclass 6, count 0 2006.280.08:18:19.10#ibcon#about to read 5, iclass 6, count 0 2006.280.08:18:19.10#ibcon#read 5, iclass 6, count 0 2006.280.08:18:19.10#ibcon#about to read 6, iclass 6, count 0 2006.280.08:18:19.10#ibcon#read 6, iclass 6, count 0 2006.280.08:18:19.10#ibcon#end of sib2, iclass 6, count 0 2006.280.08:18:19.10#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:18:19.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:18:19.10#ibcon#[27=BW32\r\n] 2006.280.08:18:19.10#ibcon#*before write, iclass 6, count 0 2006.280.08:18:19.10#ibcon#enter sib2, iclass 6, count 0 2006.280.08:18:19.10#ibcon#flushed, iclass 6, count 0 2006.280.08:18:19.10#ibcon#about to write, iclass 6, count 0 2006.280.08:18:19.10#ibcon#wrote, iclass 6, count 0 2006.280.08:18:19.10#ibcon#about to read 3, iclass 6, count 0 2006.280.08:18:19.13#ibcon#read 3, iclass 6, count 0 2006.280.08:18:19.13#ibcon#about to read 4, iclass 6, count 0 2006.280.08:18:19.13#ibcon#read 4, iclass 6, count 0 2006.280.08:18:19.13#ibcon#about to read 5, iclass 6, count 0 2006.280.08:18:19.13#ibcon#read 5, iclass 6, count 0 2006.280.08:18:19.13#ibcon#about to read 6, iclass 6, count 0 2006.280.08:18:19.13#ibcon#read 6, iclass 6, count 0 2006.280.08:18:19.13#ibcon#end of sib2, iclass 6, count 0 2006.280.08:18:19.13#ibcon#*after write, iclass 6, count 0 2006.280.08:18:19.13#ibcon#*before return 0, iclass 6, count 0 2006.280.08:18:19.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:18:19.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:18:19.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:18:19.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:18:19.13$4f8m12a/ifd4f 2006.280.08:18:19.13$ifd4f/lo= 2006.280.08:18:19.16$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:18:19.16$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:18:19.16$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:18:19.16$ifd4f/patch= 2006.280.08:18:19.16$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:18:19.16$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:18:19.16$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:18:19.16$4f8m12a/"form=m,16.000,1:2 2006.280.08:18:19.16$4f8m12a/"tpicd 2006.280.08:18:19.16$4f8m12a/echo=off 2006.280.08:18:19.16$4f8m12a/xlog=off 2006.280.08:18:19.16:!2006.280.08:19:50 2006.280.08:18:21.13#trakl#Source acquired 2006.280.08:18:22.13#flagr#flagr/antenna,acquired 2006.280.08:19:50.00:preob 2006.280.08:19:50.14/onsource/TRACKING 2006.280.08:19:50.14:!2006.280.08:20:00 2006.280.08:20:00.00:data_valid=on 2006.280.08:20:00.00:midob 2006.280.08:20:01.14/onsource/TRACKING 2006.280.08:20:01.14/wx/20.31,987.6,63 2006.280.08:20:01.30/cable/+6.4846E-03 2006.280.08:20:02.39/va/01,07,usb,yes,32,34 2006.280.08:20:02.39/va/02,06,usb,yes,30,31 2006.280.08:20:02.39/va/03,06,usb,yes,28,28 2006.280.08:20:02.39/va/04,06,usb,yes,31,33 2006.280.08:20:02.39/va/05,07,usb,yes,29,31 2006.280.08:20:02.39/va/06,06,usb,yes,28,28 2006.280.08:20:02.39/va/07,06,usb,yes,29,29 2006.280.08:20:02.39/va/08,06,usb,yes,31,30 2006.280.08:20:02.62/valo/01,532.99,yes,locked 2006.280.08:20:02.62/valo/02,572.99,yes,locked 2006.280.08:20:02.62/valo/03,672.99,yes,locked 2006.280.08:20:02.62/valo/04,832.99,yes,locked 2006.280.08:20:02.62/valo/05,652.99,yes,locked 2006.280.08:20:02.62/valo/06,772.99,yes,locked 2006.280.08:20:02.62/valo/07,832.99,yes,locked 2006.280.08:20:02.62/valo/08,852.99,yes,locked 2006.280.08:20:03.71/vb/01,04,usb,yes,30,29 2006.280.08:20:03.71/vb/02,05,usb,yes,28,29 2006.280.08:20:03.71/vb/03,04,usb,yes,28,32 2006.280.08:20:03.71/vb/04,04,usb,yes,29,29 2006.280.08:20:03.71/vb/05,04,usb,yes,27,31 2006.280.08:20:03.71/vb/06,04,usb,yes,27,31 2006.280.08:20:03.71/vb/07,04,usb,yes,30,30 2006.280.08:20:03.71/vb/08,04,usb,yes,27,31 2006.280.08:20:03.94/vblo/01,632.99,yes,locked 2006.280.08:20:03.94/vblo/02,640.99,yes,locked 2006.280.08:20:03.94/vblo/03,656.99,yes,locked 2006.280.08:20:03.94/vblo/04,712.99,yes,locked 2006.280.08:20:03.94/vblo/05,744.99,yes,locked 2006.280.08:20:03.94/vblo/06,752.99,yes,locked 2006.280.08:20:03.94/vblo/07,734.99,yes,locked 2006.280.08:20:03.94/vblo/08,744.99,yes,locked 2006.280.08:20:04.09/vabw/8 2006.280.08:20:04.24/vbbw/8 2006.280.08:20:04.33/xfe/off,on,12.0 2006.280.08:20:04.71/ifatt/23,28,28,28 2006.280.08:20:05.07/fmout-gps/S +3.14E-07 2006.280.08:20:05.10:!2006.280.08:21:00 2006.280.08:21:00.01:data_valid=off 2006.280.08:21:00.02:postob 2006.280.08:21:00.22/cable/+6.4859E-03 2006.280.08:21:00.23/wx/20.29,987.6,62 2006.280.08:21:01.07/fmout-gps/S +3.13E-07 2006.280.08:21:01.08:scan_name=280-0823,k06280,60 2006.280.08:21:01.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.280.08:21:01.14#flagr#flagr/antenna,new-source 2006.280.08:21:02.14:checkk5 2006.280.08:21:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:21:03.27/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:21:03.83/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:21:04.30/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:21:04.89/chk_obsdata//k5ts1/T2800820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:21:05.42/chk_obsdata//k5ts2/T2800820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:21:06.17/chk_obsdata//k5ts3/T2800820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:21:06.65/chk_obsdata//k5ts4/T2800820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:21:07.80/k5log//k5ts1_log_newline 2006.280.08:21:08.54/k5log//k5ts2_log_newline 2006.280.08:21:09.87/k5log//k5ts3_log_newline 2006.280.08:21:11.24/k5log//k5ts4_log_newline 2006.280.08:21:11.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:21:11.26:4f8m12a=3 2006.280.08:21:11.26$4f8m12a/echo=on 2006.280.08:21:11.26$4f8m12a/pcalon 2006.280.08:21:11.26$pcalon/"no phase cal control is implemented here 2006.280.08:21:11.27$4f8m12a/"tpicd=stop 2006.280.08:21:11.27$4f8m12a/vc4f8 2006.280.08:21:11.27$vc4f8/valo=1,532.99 2006.280.08:21:11.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.08:21:11.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.08:21:11.27#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:11.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:11.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:11.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:11.27#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:21:11.27#ibcon#first serial, iclass 5, count 0 2006.280.08:21:11.27#ibcon#enter sib2, iclass 5, count 0 2006.280.08:21:11.27#ibcon#flushed, iclass 5, count 0 2006.280.08:21:11.27#ibcon#about to write, iclass 5, count 0 2006.280.08:21:11.27#ibcon#wrote, iclass 5, count 0 2006.280.08:21:11.27#ibcon#about to read 3, iclass 5, count 0 2006.280.08:21:11.28#ibcon#read 3, iclass 5, count 0 2006.280.08:21:11.28#ibcon#about to read 4, iclass 5, count 0 2006.280.08:21:11.28#ibcon#read 4, iclass 5, count 0 2006.280.08:21:11.28#ibcon#about to read 5, iclass 5, count 0 2006.280.08:21:11.28#ibcon#read 5, iclass 5, count 0 2006.280.08:21:11.28#ibcon#about to read 6, iclass 5, count 0 2006.280.08:21:11.28#ibcon#read 6, iclass 5, count 0 2006.280.08:21:11.28#ibcon#end of sib2, iclass 5, count 0 2006.280.08:21:11.28#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:21:11.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:21:11.28#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:21:11.28#ibcon#*before write, iclass 5, count 0 2006.280.08:21:11.28#ibcon#enter sib2, iclass 5, count 0 2006.280.08:21:11.28#ibcon#flushed, iclass 5, count 0 2006.280.08:21:11.28#ibcon#about to write, iclass 5, count 0 2006.280.08:21:11.28#ibcon#wrote, iclass 5, count 0 2006.280.08:21:11.28#ibcon#about to read 3, iclass 5, count 0 2006.280.08:21:11.33#ibcon#read 3, iclass 5, count 0 2006.280.08:21:11.33#ibcon#about to read 4, iclass 5, count 0 2006.280.08:21:11.33#ibcon#read 4, iclass 5, count 0 2006.280.08:21:11.33#ibcon#about to read 5, iclass 5, count 0 2006.280.08:21:11.33#ibcon#read 5, iclass 5, count 0 2006.280.08:21:11.33#ibcon#about to read 6, iclass 5, count 0 2006.280.08:21:11.33#ibcon#read 6, iclass 5, count 0 2006.280.08:21:11.33#ibcon#end of sib2, iclass 5, count 0 2006.280.08:21:11.33#ibcon#*after write, iclass 5, count 0 2006.280.08:21:11.33#ibcon#*before return 0, iclass 5, count 0 2006.280.08:21:11.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:11.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:11.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:21:11.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:21:11.33$vc4f8/va=1,7 2006.280.08:21:11.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.08:21:11.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.08:21:11.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:11.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:11.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:11.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:11.33#ibcon#enter wrdev, iclass 7, count 2 2006.280.08:21:11.33#ibcon#first serial, iclass 7, count 2 2006.280.08:21:11.33#ibcon#enter sib2, iclass 7, count 2 2006.280.08:21:11.33#ibcon#flushed, iclass 7, count 2 2006.280.08:21:11.33#ibcon#about to write, iclass 7, count 2 2006.280.08:21:11.33#ibcon#wrote, iclass 7, count 2 2006.280.08:21:11.33#ibcon#about to read 3, iclass 7, count 2 2006.280.08:21:11.35#ibcon#read 3, iclass 7, count 2 2006.280.08:21:11.35#ibcon#about to read 4, iclass 7, count 2 2006.280.08:21:11.36#ibcon#read 4, iclass 7, count 2 2006.280.08:21:11.36#ibcon#about to read 5, iclass 7, count 2 2006.280.08:21:11.36#ibcon#read 5, iclass 7, count 2 2006.280.08:21:11.36#ibcon#about to read 6, iclass 7, count 2 2006.280.08:21:11.36#ibcon#read 6, iclass 7, count 2 2006.280.08:21:11.36#ibcon#end of sib2, iclass 7, count 2 2006.280.08:21:11.36#ibcon#*mode == 0, iclass 7, count 2 2006.280.08:21:11.36#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.08:21:11.36#ibcon#[25=AT01-07\r\n] 2006.280.08:21:11.36#ibcon#*before write, iclass 7, count 2 2006.280.08:21:11.36#ibcon#enter sib2, iclass 7, count 2 2006.280.08:21:11.36#ibcon#flushed, iclass 7, count 2 2006.280.08:21:11.36#ibcon#about to write, iclass 7, count 2 2006.280.08:21:11.36#ibcon#wrote, iclass 7, count 2 2006.280.08:21:11.36#ibcon#about to read 3, iclass 7, count 2 2006.280.08:21:11.39#ibcon#read 3, iclass 7, count 2 2006.280.08:21:11.39#ibcon#about to read 4, iclass 7, count 2 2006.280.08:21:11.39#ibcon#read 4, iclass 7, count 2 2006.280.08:21:11.39#ibcon#about to read 5, iclass 7, count 2 2006.280.08:21:11.39#ibcon#read 5, iclass 7, count 2 2006.280.08:21:11.39#ibcon#about to read 6, iclass 7, count 2 2006.280.08:21:11.39#ibcon#read 6, iclass 7, count 2 2006.280.08:21:11.39#ibcon#end of sib2, iclass 7, count 2 2006.280.08:21:11.39#ibcon#*after write, iclass 7, count 2 2006.280.08:21:11.39#ibcon#*before return 0, iclass 7, count 2 2006.280.08:21:11.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:11.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:11.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.08:21:11.39#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:11.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:11.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:11.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:11.50#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:21:11.50#ibcon#first serial, iclass 7, count 0 2006.280.08:21:11.50#ibcon#enter sib2, iclass 7, count 0 2006.280.08:21:11.50#ibcon#flushed, iclass 7, count 0 2006.280.08:21:11.50#ibcon#about to write, iclass 7, count 0 2006.280.08:21:11.50#ibcon#wrote, iclass 7, count 0 2006.280.08:21:11.50#ibcon#about to read 3, iclass 7, count 0 2006.280.08:21:11.53#ibcon#read 3, iclass 7, count 0 2006.280.08:21:11.53#ibcon#about to read 4, iclass 7, count 0 2006.280.08:21:11.53#ibcon#read 4, iclass 7, count 0 2006.280.08:21:11.53#ibcon#about to read 5, iclass 7, count 0 2006.280.08:21:11.53#ibcon#read 5, iclass 7, count 0 2006.280.08:21:11.53#ibcon#about to read 6, iclass 7, count 0 2006.280.08:21:11.53#ibcon#read 6, iclass 7, count 0 2006.280.08:21:11.53#ibcon#end of sib2, iclass 7, count 0 2006.280.08:21:11.53#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:21:11.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:21:11.53#ibcon#[25=USB\r\n] 2006.280.08:21:11.53#ibcon#*before write, iclass 7, count 0 2006.280.08:21:11.53#ibcon#enter sib2, iclass 7, count 0 2006.280.08:21:11.53#ibcon#flushed, iclass 7, count 0 2006.280.08:21:11.53#ibcon#about to write, iclass 7, count 0 2006.280.08:21:11.53#ibcon#wrote, iclass 7, count 0 2006.280.08:21:11.53#ibcon#about to read 3, iclass 7, count 0 2006.280.08:21:11.56#ibcon#read 3, iclass 7, count 0 2006.280.08:21:11.56#ibcon#about to read 4, iclass 7, count 0 2006.280.08:21:11.56#ibcon#read 4, iclass 7, count 0 2006.280.08:21:11.56#ibcon#about to read 5, iclass 7, count 0 2006.280.08:21:11.56#ibcon#read 5, iclass 7, count 0 2006.280.08:21:11.56#ibcon#about to read 6, iclass 7, count 0 2006.280.08:21:11.56#ibcon#read 6, iclass 7, count 0 2006.280.08:21:11.56#ibcon#end of sib2, iclass 7, count 0 2006.280.08:21:11.56#ibcon#*after write, iclass 7, count 0 2006.280.08:21:11.56#ibcon#*before return 0, iclass 7, count 0 2006.280.08:21:11.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:11.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:11.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:21:11.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:21:11.56$vc4f8/valo=2,572.99 2006.280.08:21:11.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.08:21:11.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.08:21:11.56#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:11.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:11.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:11.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:11.56#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:21:11.56#ibcon#first serial, iclass 11, count 0 2006.280.08:21:11.56#ibcon#enter sib2, iclass 11, count 0 2006.280.08:21:11.56#ibcon#flushed, iclass 11, count 0 2006.280.08:21:11.56#ibcon#about to write, iclass 11, count 0 2006.280.08:21:11.56#ibcon#wrote, iclass 11, count 0 2006.280.08:21:11.56#ibcon#about to read 3, iclass 11, count 0 2006.280.08:21:11.58#ibcon#read 3, iclass 11, count 0 2006.280.08:21:11.58#ibcon#about to read 4, iclass 11, count 0 2006.280.08:21:11.58#ibcon#read 4, iclass 11, count 0 2006.280.08:21:11.58#ibcon#about to read 5, iclass 11, count 0 2006.280.08:21:11.58#ibcon#read 5, iclass 11, count 0 2006.280.08:21:11.58#ibcon#about to read 6, iclass 11, count 0 2006.280.08:21:11.58#ibcon#read 6, iclass 11, count 0 2006.280.08:21:11.58#ibcon#end of sib2, iclass 11, count 0 2006.280.08:21:11.58#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:21:11.58#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:21:11.58#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:21:11.58#ibcon#*before write, iclass 11, count 0 2006.280.08:21:11.58#ibcon#enter sib2, iclass 11, count 0 2006.280.08:21:11.58#ibcon#flushed, iclass 11, count 0 2006.280.08:21:11.58#ibcon#about to write, iclass 11, count 0 2006.280.08:21:11.58#ibcon#wrote, iclass 11, count 0 2006.280.08:21:11.58#ibcon#about to read 3, iclass 11, count 0 2006.280.08:21:11.62#ibcon#read 3, iclass 11, count 0 2006.280.08:21:11.62#ibcon#about to read 4, iclass 11, count 0 2006.280.08:21:11.62#ibcon#read 4, iclass 11, count 0 2006.280.08:21:11.62#ibcon#about to read 5, iclass 11, count 0 2006.280.08:21:11.62#ibcon#read 5, iclass 11, count 0 2006.280.08:21:11.62#ibcon#about to read 6, iclass 11, count 0 2006.280.08:21:11.62#ibcon#read 6, iclass 11, count 0 2006.280.08:21:11.62#ibcon#end of sib2, iclass 11, count 0 2006.280.08:21:11.62#ibcon#*after write, iclass 11, count 0 2006.280.08:21:11.62#ibcon#*before return 0, iclass 11, count 0 2006.280.08:21:11.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:11.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:11.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:21:11.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:21:11.62$vc4f8/va=2,6 2006.280.08:21:11.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.08:21:11.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.08:21:11.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:11.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:11.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:11.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:11.67#ibcon#enter wrdev, iclass 13, count 2 2006.280.08:21:11.67#ibcon#first serial, iclass 13, count 2 2006.280.08:21:11.67#ibcon#enter sib2, iclass 13, count 2 2006.280.08:21:11.67#ibcon#flushed, iclass 13, count 2 2006.280.08:21:11.67#ibcon#about to write, iclass 13, count 2 2006.280.08:21:11.67#ibcon#wrote, iclass 13, count 2 2006.280.08:21:11.67#ibcon#about to read 3, iclass 13, count 2 2006.280.08:21:11.69#ibcon#read 3, iclass 13, count 2 2006.280.08:21:11.69#ibcon#about to read 4, iclass 13, count 2 2006.280.08:21:11.69#ibcon#read 4, iclass 13, count 2 2006.280.08:21:11.69#ibcon#about to read 5, iclass 13, count 2 2006.280.08:21:11.69#ibcon#read 5, iclass 13, count 2 2006.280.08:21:11.69#ibcon#about to read 6, iclass 13, count 2 2006.280.08:21:11.69#ibcon#read 6, iclass 13, count 2 2006.280.08:21:11.69#ibcon#end of sib2, iclass 13, count 2 2006.280.08:21:11.69#ibcon#*mode == 0, iclass 13, count 2 2006.280.08:21:11.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.08:21:11.69#ibcon#[25=AT02-06\r\n] 2006.280.08:21:11.69#ibcon#*before write, iclass 13, count 2 2006.280.08:21:11.69#ibcon#enter sib2, iclass 13, count 2 2006.280.08:21:11.69#ibcon#flushed, iclass 13, count 2 2006.280.08:21:11.69#ibcon#about to write, iclass 13, count 2 2006.280.08:21:11.69#ibcon#wrote, iclass 13, count 2 2006.280.08:21:11.69#ibcon#about to read 3, iclass 13, count 2 2006.280.08:21:11.73#ibcon#read 3, iclass 13, count 2 2006.280.08:21:11.73#ibcon#about to read 4, iclass 13, count 2 2006.280.08:21:11.73#ibcon#read 4, iclass 13, count 2 2006.280.08:21:11.73#ibcon#about to read 5, iclass 13, count 2 2006.280.08:21:11.73#ibcon#read 5, iclass 13, count 2 2006.280.08:21:11.73#ibcon#about to read 6, iclass 13, count 2 2006.280.08:21:11.73#ibcon#read 6, iclass 13, count 2 2006.280.08:21:11.73#ibcon#end of sib2, iclass 13, count 2 2006.280.08:21:11.73#ibcon#*after write, iclass 13, count 2 2006.280.08:21:11.73#ibcon#*before return 0, iclass 13, count 2 2006.280.08:21:11.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:11.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:11.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.08:21:11.73#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:11.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:11.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:11.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:11.84#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:21:11.84#ibcon#first serial, iclass 13, count 0 2006.280.08:21:11.84#ibcon#enter sib2, iclass 13, count 0 2006.280.08:21:11.84#ibcon#flushed, iclass 13, count 0 2006.280.08:21:11.84#ibcon#about to write, iclass 13, count 0 2006.280.08:21:11.84#ibcon#wrote, iclass 13, count 0 2006.280.08:21:11.84#ibcon#about to read 3, iclass 13, count 0 2006.280.08:21:11.86#ibcon#read 3, iclass 13, count 0 2006.280.08:21:11.86#ibcon#about to read 4, iclass 13, count 0 2006.280.08:21:11.86#ibcon#read 4, iclass 13, count 0 2006.280.08:21:11.86#ibcon#about to read 5, iclass 13, count 0 2006.280.08:21:11.86#ibcon#read 5, iclass 13, count 0 2006.280.08:21:11.86#ibcon#about to read 6, iclass 13, count 0 2006.280.08:21:11.86#ibcon#read 6, iclass 13, count 0 2006.280.08:21:11.86#ibcon#end of sib2, iclass 13, count 0 2006.280.08:21:11.86#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:21:11.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:21:11.86#ibcon#[25=USB\r\n] 2006.280.08:21:11.86#ibcon#*before write, iclass 13, count 0 2006.280.08:21:11.86#ibcon#enter sib2, iclass 13, count 0 2006.280.08:21:11.86#ibcon#flushed, iclass 13, count 0 2006.280.08:21:11.86#ibcon#about to write, iclass 13, count 0 2006.280.08:21:11.86#ibcon#wrote, iclass 13, count 0 2006.280.08:21:11.86#ibcon#about to read 3, iclass 13, count 0 2006.280.08:21:11.89#ibcon#read 3, iclass 13, count 0 2006.280.08:21:11.89#ibcon#about to read 4, iclass 13, count 0 2006.280.08:21:11.89#ibcon#read 4, iclass 13, count 0 2006.280.08:21:11.89#ibcon#about to read 5, iclass 13, count 0 2006.280.08:21:11.89#ibcon#read 5, iclass 13, count 0 2006.280.08:21:11.89#ibcon#about to read 6, iclass 13, count 0 2006.280.08:21:11.89#ibcon#read 6, iclass 13, count 0 2006.280.08:21:11.89#ibcon#end of sib2, iclass 13, count 0 2006.280.08:21:11.89#ibcon#*after write, iclass 13, count 0 2006.280.08:21:11.89#ibcon#*before return 0, iclass 13, count 0 2006.280.08:21:11.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:11.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:11.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:21:11.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:21:11.89$vc4f8/valo=3,672.99 2006.280.08:21:11.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:21:11.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:21:11.89#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:11.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:11.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:11.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:11.89#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:21:11.89#ibcon#first serial, iclass 15, count 0 2006.280.08:21:11.89#ibcon#enter sib2, iclass 15, count 0 2006.280.08:21:11.89#ibcon#flushed, iclass 15, count 0 2006.280.08:21:11.89#ibcon#about to write, iclass 15, count 0 2006.280.08:21:11.89#ibcon#wrote, iclass 15, count 0 2006.280.08:21:11.89#ibcon#about to read 3, iclass 15, count 0 2006.280.08:21:11.91#ibcon#read 3, iclass 15, count 0 2006.280.08:21:11.91#ibcon#about to read 4, iclass 15, count 0 2006.280.08:21:11.91#ibcon#read 4, iclass 15, count 0 2006.280.08:21:11.91#ibcon#about to read 5, iclass 15, count 0 2006.280.08:21:11.91#ibcon#read 5, iclass 15, count 0 2006.280.08:21:11.91#ibcon#about to read 6, iclass 15, count 0 2006.280.08:21:11.91#ibcon#read 6, iclass 15, count 0 2006.280.08:21:11.91#ibcon#end of sib2, iclass 15, count 0 2006.280.08:21:11.91#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:21:11.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:21:11.91#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:21:11.91#ibcon#*before write, iclass 15, count 0 2006.280.08:21:11.91#ibcon#enter sib2, iclass 15, count 0 2006.280.08:21:11.91#ibcon#flushed, iclass 15, count 0 2006.280.08:21:11.91#ibcon#about to write, iclass 15, count 0 2006.280.08:21:11.91#ibcon#wrote, iclass 15, count 0 2006.280.08:21:11.91#ibcon#about to read 3, iclass 15, count 0 2006.280.08:21:11.95#ibcon#read 3, iclass 15, count 0 2006.280.08:21:11.95#ibcon#about to read 4, iclass 15, count 0 2006.280.08:21:11.95#ibcon#read 4, iclass 15, count 0 2006.280.08:21:11.95#ibcon#about to read 5, iclass 15, count 0 2006.280.08:21:11.95#ibcon#read 5, iclass 15, count 0 2006.280.08:21:11.95#ibcon#about to read 6, iclass 15, count 0 2006.280.08:21:11.95#ibcon#read 6, iclass 15, count 0 2006.280.08:21:11.95#ibcon#end of sib2, iclass 15, count 0 2006.280.08:21:11.95#ibcon#*after write, iclass 15, count 0 2006.280.08:21:11.95#ibcon#*before return 0, iclass 15, count 0 2006.280.08:21:11.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:11.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:11.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:21:11.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:21:11.95$vc4f8/va=3,6 2006.280.08:21:11.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:21:11.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:21:11.97#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:11.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:12.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:12.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:12.00#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:21:12.00#ibcon#first serial, iclass 17, count 2 2006.280.08:21:12.00#ibcon#enter sib2, iclass 17, count 2 2006.280.08:21:12.00#ibcon#flushed, iclass 17, count 2 2006.280.08:21:12.00#ibcon#about to write, iclass 17, count 2 2006.280.08:21:12.00#ibcon#wrote, iclass 17, count 2 2006.280.08:21:12.00#ibcon#about to read 3, iclass 17, count 2 2006.280.08:21:12.02#ibcon#read 3, iclass 17, count 2 2006.280.08:21:12.02#ibcon#about to read 4, iclass 17, count 2 2006.280.08:21:12.02#ibcon#read 4, iclass 17, count 2 2006.280.08:21:12.02#ibcon#about to read 5, iclass 17, count 2 2006.280.08:21:12.02#ibcon#read 5, iclass 17, count 2 2006.280.08:21:12.02#ibcon#about to read 6, iclass 17, count 2 2006.280.08:21:12.02#ibcon#read 6, iclass 17, count 2 2006.280.08:21:12.02#ibcon#end of sib2, iclass 17, count 2 2006.280.08:21:12.02#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:21:12.02#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:21:12.02#ibcon#[25=AT03-06\r\n] 2006.280.08:21:12.02#ibcon#*before write, iclass 17, count 2 2006.280.08:21:12.02#ibcon#enter sib2, iclass 17, count 2 2006.280.08:21:12.02#ibcon#flushed, iclass 17, count 2 2006.280.08:21:12.02#ibcon#about to write, iclass 17, count 2 2006.280.08:21:12.02#ibcon#wrote, iclass 17, count 2 2006.280.08:21:12.02#ibcon#about to read 3, iclass 17, count 2 2006.280.08:21:12.05#ibcon#read 3, iclass 17, count 2 2006.280.08:21:12.05#ibcon#about to read 4, iclass 17, count 2 2006.280.08:21:12.05#ibcon#read 4, iclass 17, count 2 2006.280.08:21:12.05#ibcon#about to read 5, iclass 17, count 2 2006.280.08:21:12.05#ibcon#read 5, iclass 17, count 2 2006.280.08:21:12.05#ibcon#about to read 6, iclass 17, count 2 2006.280.08:21:12.05#ibcon#read 6, iclass 17, count 2 2006.280.08:21:12.05#ibcon#end of sib2, iclass 17, count 2 2006.280.08:21:12.05#ibcon#*after write, iclass 17, count 2 2006.280.08:21:12.05#ibcon#*before return 0, iclass 17, count 2 2006.280.08:21:12.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:12.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:12.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:21:12.05#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:12.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:12.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:12.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:12.17#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:21:12.17#ibcon#first serial, iclass 17, count 0 2006.280.08:21:12.17#ibcon#enter sib2, iclass 17, count 0 2006.280.08:21:12.17#ibcon#flushed, iclass 17, count 0 2006.280.08:21:12.17#ibcon#about to write, iclass 17, count 0 2006.280.08:21:12.17#ibcon#wrote, iclass 17, count 0 2006.280.08:21:12.17#ibcon#about to read 3, iclass 17, count 0 2006.280.08:21:12.19#ibcon#read 3, iclass 17, count 0 2006.280.08:21:12.19#ibcon#about to read 4, iclass 17, count 0 2006.280.08:21:12.19#ibcon#read 4, iclass 17, count 0 2006.280.08:21:12.19#ibcon#about to read 5, iclass 17, count 0 2006.280.08:21:12.19#ibcon#read 5, iclass 17, count 0 2006.280.08:21:12.19#ibcon#about to read 6, iclass 17, count 0 2006.280.08:21:12.19#ibcon#read 6, iclass 17, count 0 2006.280.08:21:12.19#ibcon#end of sib2, iclass 17, count 0 2006.280.08:21:12.19#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:21:12.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:21:12.19#ibcon#[25=USB\r\n] 2006.280.08:21:12.19#ibcon#*before write, iclass 17, count 0 2006.280.08:21:12.19#ibcon#enter sib2, iclass 17, count 0 2006.280.08:21:12.19#ibcon#flushed, iclass 17, count 0 2006.280.08:21:12.19#ibcon#about to write, iclass 17, count 0 2006.280.08:21:12.19#ibcon#wrote, iclass 17, count 0 2006.280.08:21:12.19#ibcon#about to read 3, iclass 17, count 0 2006.280.08:21:12.22#ibcon#read 3, iclass 17, count 0 2006.280.08:21:12.22#ibcon#about to read 4, iclass 17, count 0 2006.280.08:21:12.22#ibcon#read 4, iclass 17, count 0 2006.280.08:21:12.22#ibcon#about to read 5, iclass 17, count 0 2006.280.08:21:12.22#ibcon#read 5, iclass 17, count 0 2006.280.08:21:12.22#ibcon#about to read 6, iclass 17, count 0 2006.280.08:21:12.22#ibcon#read 6, iclass 17, count 0 2006.280.08:21:12.22#ibcon#end of sib2, iclass 17, count 0 2006.280.08:21:12.23#ibcon#*after write, iclass 17, count 0 2006.280.08:21:12.23#ibcon#*before return 0, iclass 17, count 0 2006.280.08:21:12.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:12.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:12.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:21:12.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:21:12.23$vc4f8/valo=4,832.99 2006.280.08:21:12.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:21:12.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:21:12.23#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:12.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:12.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:12.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:12.23#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:21:12.23#ibcon#first serial, iclass 19, count 0 2006.280.08:21:12.23#ibcon#enter sib2, iclass 19, count 0 2006.280.08:21:12.23#ibcon#flushed, iclass 19, count 0 2006.280.08:21:12.23#ibcon#about to write, iclass 19, count 0 2006.280.08:21:12.23#ibcon#wrote, iclass 19, count 0 2006.280.08:21:12.23#ibcon#about to read 3, iclass 19, count 0 2006.280.08:21:12.24#ibcon#read 3, iclass 19, count 0 2006.280.08:21:12.24#ibcon#about to read 4, iclass 19, count 0 2006.280.08:21:12.24#ibcon#read 4, iclass 19, count 0 2006.280.08:21:12.24#ibcon#about to read 5, iclass 19, count 0 2006.280.08:21:12.24#ibcon#read 5, iclass 19, count 0 2006.280.08:21:12.24#ibcon#about to read 6, iclass 19, count 0 2006.280.08:21:12.24#ibcon#read 6, iclass 19, count 0 2006.280.08:21:12.24#ibcon#end of sib2, iclass 19, count 0 2006.280.08:21:12.24#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:21:12.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:21:12.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:21:12.24#ibcon#*before write, iclass 19, count 0 2006.280.08:21:12.24#ibcon#enter sib2, iclass 19, count 0 2006.280.08:21:12.24#ibcon#flushed, iclass 19, count 0 2006.280.08:21:12.24#ibcon#about to write, iclass 19, count 0 2006.280.08:21:12.24#ibcon#wrote, iclass 19, count 0 2006.280.08:21:12.24#ibcon#about to read 3, iclass 19, count 0 2006.280.08:21:12.28#ibcon#read 3, iclass 19, count 0 2006.280.08:21:12.28#ibcon#about to read 4, iclass 19, count 0 2006.280.08:21:12.28#ibcon#read 4, iclass 19, count 0 2006.280.08:21:12.28#ibcon#about to read 5, iclass 19, count 0 2006.280.08:21:12.28#ibcon#read 5, iclass 19, count 0 2006.280.08:21:12.28#ibcon#about to read 6, iclass 19, count 0 2006.280.08:21:12.28#ibcon#read 6, iclass 19, count 0 2006.280.08:21:12.28#ibcon#end of sib2, iclass 19, count 0 2006.280.08:21:12.28#ibcon#*after write, iclass 19, count 0 2006.280.08:21:12.28#ibcon#*before return 0, iclass 19, count 0 2006.280.08:21:12.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:12.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:12.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:21:12.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:21:12.28$vc4f8/va=4,6 2006.280.08:21:12.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:21:12.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:21:12.29#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:12.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:12.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:12.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:12.34#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:21:12.34#ibcon#first serial, iclass 21, count 2 2006.280.08:21:12.34#ibcon#enter sib2, iclass 21, count 2 2006.280.08:21:12.34#ibcon#flushed, iclass 21, count 2 2006.280.08:21:12.34#ibcon#about to write, iclass 21, count 2 2006.280.08:21:12.34#ibcon#wrote, iclass 21, count 2 2006.280.08:21:12.34#ibcon#about to read 3, iclass 21, count 2 2006.280.08:21:12.37#ibcon#read 3, iclass 21, count 2 2006.280.08:21:12.37#ibcon#about to read 4, iclass 21, count 2 2006.280.08:21:12.37#ibcon#read 4, iclass 21, count 2 2006.280.08:21:12.37#ibcon#about to read 5, iclass 21, count 2 2006.280.08:21:12.37#ibcon#read 5, iclass 21, count 2 2006.280.08:21:12.37#ibcon#about to read 6, iclass 21, count 2 2006.280.08:21:12.37#ibcon#read 6, iclass 21, count 2 2006.280.08:21:12.37#ibcon#end of sib2, iclass 21, count 2 2006.280.08:21:12.37#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:21:12.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:21:12.37#ibcon#[25=AT04-06\r\n] 2006.280.08:21:12.37#ibcon#*before write, iclass 21, count 2 2006.280.08:21:12.37#ibcon#enter sib2, iclass 21, count 2 2006.280.08:21:12.37#ibcon#flushed, iclass 21, count 2 2006.280.08:21:12.37#ibcon#about to write, iclass 21, count 2 2006.280.08:21:12.37#ibcon#wrote, iclass 21, count 2 2006.280.08:21:12.37#ibcon#about to read 3, iclass 21, count 2 2006.280.08:21:12.39#ibcon#read 3, iclass 21, count 2 2006.280.08:21:12.39#ibcon#about to read 4, iclass 21, count 2 2006.280.08:21:12.39#ibcon#read 4, iclass 21, count 2 2006.280.08:21:12.39#ibcon#about to read 5, iclass 21, count 2 2006.280.08:21:12.39#ibcon#read 5, iclass 21, count 2 2006.280.08:21:12.39#ibcon#about to read 6, iclass 21, count 2 2006.280.08:21:12.39#ibcon#read 6, iclass 21, count 2 2006.280.08:21:12.39#ibcon#end of sib2, iclass 21, count 2 2006.280.08:21:12.39#ibcon#*after write, iclass 21, count 2 2006.280.08:21:12.39#ibcon#*before return 0, iclass 21, count 2 2006.280.08:21:12.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:12.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:12.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:21:12.39#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:12.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:12.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:12.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:12.51#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:21:12.51#ibcon#first serial, iclass 21, count 0 2006.280.08:21:12.51#ibcon#enter sib2, iclass 21, count 0 2006.280.08:21:12.51#ibcon#flushed, iclass 21, count 0 2006.280.08:21:12.51#ibcon#about to write, iclass 21, count 0 2006.280.08:21:12.51#ibcon#wrote, iclass 21, count 0 2006.280.08:21:12.51#ibcon#about to read 3, iclass 21, count 0 2006.280.08:21:12.53#ibcon#read 3, iclass 21, count 0 2006.280.08:21:12.53#ibcon#about to read 4, iclass 21, count 0 2006.280.08:21:12.53#ibcon#read 4, iclass 21, count 0 2006.280.08:21:12.53#ibcon#about to read 5, iclass 21, count 0 2006.280.08:21:12.53#ibcon#read 5, iclass 21, count 0 2006.280.08:21:12.53#ibcon#about to read 6, iclass 21, count 0 2006.280.08:21:12.53#ibcon#read 6, iclass 21, count 0 2006.280.08:21:12.53#ibcon#end of sib2, iclass 21, count 0 2006.280.08:21:12.53#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:21:12.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:21:12.53#ibcon#[25=USB\r\n] 2006.280.08:21:12.53#ibcon#*before write, iclass 21, count 0 2006.280.08:21:12.53#ibcon#enter sib2, iclass 21, count 0 2006.280.08:21:12.53#ibcon#flushed, iclass 21, count 0 2006.280.08:21:12.53#ibcon#about to write, iclass 21, count 0 2006.280.08:21:12.53#ibcon#wrote, iclass 21, count 0 2006.280.08:21:12.53#ibcon#about to read 3, iclass 21, count 0 2006.280.08:21:12.57#ibcon#read 3, iclass 21, count 0 2006.280.08:21:12.57#ibcon#about to read 4, iclass 21, count 0 2006.280.08:21:12.57#ibcon#read 4, iclass 21, count 0 2006.280.08:21:12.57#ibcon#about to read 5, iclass 21, count 0 2006.280.08:21:12.57#ibcon#read 5, iclass 21, count 0 2006.280.08:21:12.57#ibcon#about to read 6, iclass 21, count 0 2006.280.08:21:12.57#ibcon#read 6, iclass 21, count 0 2006.280.08:21:12.57#ibcon#end of sib2, iclass 21, count 0 2006.280.08:21:12.57#ibcon#*after write, iclass 21, count 0 2006.280.08:21:12.57#ibcon#*before return 0, iclass 21, count 0 2006.280.08:21:12.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:12.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:12.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:21:12.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:21:12.57$vc4f8/valo=5,652.99 2006.280.08:21:12.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:21:12.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:21:12.57#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:12.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:12.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:12.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:12.57#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:21:12.57#ibcon#first serial, iclass 23, count 0 2006.280.08:21:12.57#ibcon#enter sib2, iclass 23, count 0 2006.280.08:21:12.57#ibcon#flushed, iclass 23, count 0 2006.280.08:21:12.57#ibcon#about to write, iclass 23, count 0 2006.280.08:21:12.57#ibcon#wrote, iclass 23, count 0 2006.280.08:21:12.57#ibcon#about to read 3, iclass 23, count 0 2006.280.08:21:12.58#ibcon#read 3, iclass 23, count 0 2006.280.08:21:12.58#ibcon#about to read 4, iclass 23, count 0 2006.280.08:21:12.58#ibcon#read 4, iclass 23, count 0 2006.280.08:21:12.58#ibcon#about to read 5, iclass 23, count 0 2006.280.08:21:12.58#ibcon#read 5, iclass 23, count 0 2006.280.08:21:12.58#ibcon#about to read 6, iclass 23, count 0 2006.280.08:21:12.60#ibcon#read 6, iclass 23, count 0 2006.280.08:21:12.60#ibcon#end of sib2, iclass 23, count 0 2006.280.08:21:12.60#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:21:12.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:21:12.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:21:12.60#ibcon#*before write, iclass 23, count 0 2006.280.08:21:12.60#ibcon#enter sib2, iclass 23, count 0 2006.280.08:21:12.60#ibcon#flushed, iclass 23, count 0 2006.280.08:21:12.60#ibcon#about to write, iclass 23, count 0 2006.280.08:21:12.60#ibcon#wrote, iclass 23, count 0 2006.280.08:21:12.60#ibcon#about to read 3, iclass 23, count 0 2006.280.08:21:12.63#ibcon#read 3, iclass 23, count 0 2006.280.08:21:12.63#ibcon#about to read 4, iclass 23, count 0 2006.280.08:21:12.63#ibcon#read 4, iclass 23, count 0 2006.280.08:21:12.63#ibcon#about to read 5, iclass 23, count 0 2006.280.08:21:12.63#ibcon#read 5, iclass 23, count 0 2006.280.08:21:12.63#ibcon#about to read 6, iclass 23, count 0 2006.280.08:21:12.63#ibcon#read 6, iclass 23, count 0 2006.280.08:21:12.63#ibcon#end of sib2, iclass 23, count 0 2006.280.08:21:12.63#ibcon#*after write, iclass 23, count 0 2006.280.08:21:12.63#ibcon#*before return 0, iclass 23, count 0 2006.280.08:21:12.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:12.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:12.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:21:12.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:21:12.63$vc4f8/va=5,7 2006.280.08:21:12.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.08:21:12.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.08:21:12.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:12.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:12.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:12.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:12.69#ibcon#enter wrdev, iclass 25, count 2 2006.280.08:21:12.69#ibcon#first serial, iclass 25, count 2 2006.280.08:21:12.69#ibcon#enter sib2, iclass 25, count 2 2006.280.08:21:12.69#ibcon#flushed, iclass 25, count 2 2006.280.08:21:12.69#ibcon#about to write, iclass 25, count 2 2006.280.08:21:12.69#ibcon#wrote, iclass 25, count 2 2006.280.08:21:12.69#ibcon#about to read 3, iclass 25, count 2 2006.280.08:21:12.71#ibcon#read 3, iclass 25, count 2 2006.280.08:21:12.71#ibcon#about to read 4, iclass 25, count 2 2006.280.08:21:12.71#ibcon#read 4, iclass 25, count 2 2006.280.08:21:12.71#ibcon#about to read 5, iclass 25, count 2 2006.280.08:21:12.71#ibcon#read 5, iclass 25, count 2 2006.280.08:21:12.71#ibcon#about to read 6, iclass 25, count 2 2006.280.08:21:12.71#ibcon#read 6, iclass 25, count 2 2006.280.08:21:12.71#ibcon#end of sib2, iclass 25, count 2 2006.280.08:21:12.71#ibcon#*mode == 0, iclass 25, count 2 2006.280.08:21:12.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.08:21:12.71#ibcon#[25=AT05-07\r\n] 2006.280.08:21:12.71#ibcon#*before write, iclass 25, count 2 2006.280.08:21:12.71#ibcon#enter sib2, iclass 25, count 2 2006.280.08:21:12.71#ibcon#flushed, iclass 25, count 2 2006.280.08:21:12.71#ibcon#about to write, iclass 25, count 2 2006.280.08:21:12.71#ibcon#wrote, iclass 25, count 2 2006.280.08:21:12.71#ibcon#about to read 3, iclass 25, count 2 2006.280.08:21:12.74#ibcon#read 3, iclass 25, count 2 2006.280.08:21:12.74#ibcon#about to read 4, iclass 25, count 2 2006.280.08:21:12.74#ibcon#read 4, iclass 25, count 2 2006.280.08:21:12.74#ibcon#about to read 5, iclass 25, count 2 2006.280.08:21:12.74#ibcon#read 5, iclass 25, count 2 2006.280.08:21:12.74#ibcon#about to read 6, iclass 25, count 2 2006.280.08:21:12.74#ibcon#read 6, iclass 25, count 2 2006.280.08:21:12.74#ibcon#end of sib2, iclass 25, count 2 2006.280.08:21:12.74#ibcon#*after write, iclass 25, count 2 2006.280.08:21:12.74#ibcon#*before return 0, iclass 25, count 2 2006.280.08:21:12.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:12.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:12.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.08:21:12.74#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:12.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:12.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:12.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:12.87#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:21:12.87#ibcon#first serial, iclass 25, count 0 2006.280.08:21:12.87#ibcon#enter sib2, iclass 25, count 0 2006.280.08:21:12.87#ibcon#flushed, iclass 25, count 0 2006.280.08:21:12.87#ibcon#about to write, iclass 25, count 0 2006.280.08:21:12.87#ibcon#wrote, iclass 25, count 0 2006.280.08:21:12.87#ibcon#about to read 3, iclass 25, count 0 2006.280.08:21:12.88#ibcon#read 3, iclass 25, count 0 2006.280.08:21:12.88#ibcon#about to read 4, iclass 25, count 0 2006.280.08:21:12.88#ibcon#read 4, iclass 25, count 0 2006.280.08:21:12.88#ibcon#about to read 5, iclass 25, count 0 2006.280.08:21:12.88#ibcon#read 5, iclass 25, count 0 2006.280.08:21:12.88#ibcon#about to read 6, iclass 25, count 0 2006.280.08:21:12.88#ibcon#read 6, iclass 25, count 0 2006.280.08:21:12.88#ibcon#end of sib2, iclass 25, count 0 2006.280.08:21:12.88#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:21:12.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:21:12.88#ibcon#[25=USB\r\n] 2006.280.08:21:12.88#ibcon#*before write, iclass 25, count 0 2006.280.08:21:12.88#ibcon#enter sib2, iclass 25, count 0 2006.280.08:21:12.88#ibcon#flushed, iclass 25, count 0 2006.280.08:21:12.88#ibcon#about to write, iclass 25, count 0 2006.280.08:21:12.88#ibcon#wrote, iclass 25, count 0 2006.280.08:21:12.88#ibcon#about to read 3, iclass 25, count 0 2006.280.08:21:12.91#ibcon#read 3, iclass 25, count 0 2006.280.08:21:12.91#ibcon#about to read 4, iclass 25, count 0 2006.280.08:21:12.91#ibcon#read 4, iclass 25, count 0 2006.280.08:21:12.91#ibcon#about to read 5, iclass 25, count 0 2006.280.08:21:12.91#ibcon#read 5, iclass 25, count 0 2006.280.08:21:12.91#ibcon#about to read 6, iclass 25, count 0 2006.280.08:21:12.91#ibcon#read 6, iclass 25, count 0 2006.280.08:21:12.91#ibcon#end of sib2, iclass 25, count 0 2006.280.08:21:12.91#ibcon#*after write, iclass 25, count 0 2006.280.08:21:12.91#ibcon#*before return 0, iclass 25, count 0 2006.280.08:21:12.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:12.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:12.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:21:12.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:21:12.91$vc4f8/valo=6,772.99 2006.280.08:21:12.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.08:21:12.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.08:21:12.91#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:12.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:12.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:12.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:12.91#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:21:12.91#ibcon#first serial, iclass 27, count 0 2006.280.08:21:12.91#ibcon#enter sib2, iclass 27, count 0 2006.280.08:21:12.91#ibcon#flushed, iclass 27, count 0 2006.280.08:21:12.91#ibcon#about to write, iclass 27, count 0 2006.280.08:21:12.91#ibcon#wrote, iclass 27, count 0 2006.280.08:21:12.91#ibcon#about to read 3, iclass 27, count 0 2006.280.08:21:12.93#ibcon#read 3, iclass 27, count 0 2006.280.08:21:12.93#ibcon#about to read 4, iclass 27, count 0 2006.280.08:21:12.93#ibcon#read 4, iclass 27, count 0 2006.280.08:21:12.93#ibcon#about to read 5, iclass 27, count 0 2006.280.08:21:12.93#ibcon#read 5, iclass 27, count 0 2006.280.08:21:12.93#ibcon#about to read 6, iclass 27, count 0 2006.280.08:21:12.93#ibcon#read 6, iclass 27, count 0 2006.280.08:21:12.93#ibcon#end of sib2, iclass 27, count 0 2006.280.08:21:12.93#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:21:12.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:21:12.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:21:12.93#ibcon#*before write, iclass 27, count 0 2006.280.08:21:12.93#ibcon#enter sib2, iclass 27, count 0 2006.280.08:21:12.93#ibcon#flushed, iclass 27, count 0 2006.280.08:21:12.93#ibcon#about to write, iclass 27, count 0 2006.280.08:21:12.93#ibcon#wrote, iclass 27, count 0 2006.280.08:21:12.93#ibcon#about to read 3, iclass 27, count 0 2006.280.08:21:12.98#abcon#<5=/13 1.4 3.9 20.28 63 987.6\r\n> 2006.280.08:21:12.98#ibcon#read 3, iclass 27, count 0 2006.280.08:21:12.98#ibcon#about to read 4, iclass 27, count 0 2006.280.08:21:12.98#ibcon#read 4, iclass 27, count 0 2006.280.08:21:12.98#ibcon#about to read 5, iclass 27, count 0 2006.280.08:21:12.98#ibcon#read 5, iclass 27, count 0 2006.280.08:21:12.98#ibcon#about to read 6, iclass 27, count 0 2006.280.08:21:12.98#ibcon#read 6, iclass 27, count 0 2006.280.08:21:12.98#ibcon#end of sib2, iclass 27, count 0 2006.280.08:21:12.98#ibcon#*after write, iclass 27, count 0 2006.280.08:21:12.98#ibcon#*before return 0, iclass 27, count 0 2006.280.08:21:12.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:12.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:12.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:21:12.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:21:12.98$vc4f8/va=6,6 2006.280.08:21:12.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.280.08:21:12.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.280.08:21:12.98#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:12.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:21:12.99#abcon#{5=INTERFACE CLEAR} 2006.280.08:21:13.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:21:13.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:21:13.02#ibcon#enter wrdev, iclass 32, count 2 2006.280.08:21:13.02#ibcon#first serial, iclass 32, count 2 2006.280.08:21:13.02#ibcon#enter sib2, iclass 32, count 2 2006.280.08:21:13.02#ibcon#flushed, iclass 32, count 2 2006.280.08:21:13.02#ibcon#about to write, iclass 32, count 2 2006.280.08:21:13.02#ibcon#wrote, iclass 32, count 2 2006.280.08:21:13.02#ibcon#about to read 3, iclass 32, count 2 2006.280.08:21:13.04#ibcon#read 3, iclass 32, count 2 2006.280.08:21:13.04#ibcon#about to read 4, iclass 32, count 2 2006.280.08:21:13.04#ibcon#read 4, iclass 32, count 2 2006.280.08:21:13.04#ibcon#about to read 5, iclass 32, count 2 2006.280.08:21:13.04#ibcon#read 5, iclass 32, count 2 2006.280.08:21:13.04#ibcon#about to read 6, iclass 32, count 2 2006.280.08:21:13.04#ibcon#read 6, iclass 32, count 2 2006.280.08:21:13.04#ibcon#end of sib2, iclass 32, count 2 2006.280.08:21:13.04#ibcon#*mode == 0, iclass 32, count 2 2006.280.08:21:13.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.280.08:21:13.04#ibcon#[25=AT06-06\r\n] 2006.280.08:21:13.04#ibcon#*before write, iclass 32, count 2 2006.280.08:21:13.04#ibcon#enter sib2, iclass 32, count 2 2006.280.08:21:13.04#ibcon#flushed, iclass 32, count 2 2006.280.08:21:13.04#ibcon#about to write, iclass 32, count 2 2006.280.08:21:13.04#ibcon#wrote, iclass 32, count 2 2006.280.08:21:13.04#ibcon#about to read 3, iclass 32, count 2 2006.280.08:21:13.05#abcon#[5=S1D000X0/0*\r\n] 2006.280.08:21:13.07#ibcon#read 3, iclass 32, count 2 2006.280.08:21:13.07#ibcon#about to read 4, iclass 32, count 2 2006.280.08:21:13.07#ibcon#read 4, iclass 32, count 2 2006.280.08:21:13.07#ibcon#about to read 5, iclass 32, count 2 2006.280.08:21:13.07#ibcon#read 5, iclass 32, count 2 2006.280.08:21:13.07#ibcon#about to read 6, iclass 32, count 2 2006.280.08:21:13.07#ibcon#read 6, iclass 32, count 2 2006.280.08:21:13.07#ibcon#end of sib2, iclass 32, count 2 2006.280.08:21:13.07#ibcon#*after write, iclass 32, count 2 2006.280.08:21:13.07#ibcon#*before return 0, iclass 32, count 2 2006.280.08:21:13.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:21:13.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.280.08:21:13.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.280.08:21:13.07#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:13.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:21:13.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:21:13.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:21:13.19#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:21:13.19#ibcon#first serial, iclass 32, count 0 2006.280.08:21:13.19#ibcon#enter sib2, iclass 32, count 0 2006.280.08:21:13.19#ibcon#flushed, iclass 32, count 0 2006.280.08:21:13.19#ibcon#about to write, iclass 32, count 0 2006.280.08:21:13.19#ibcon#wrote, iclass 32, count 0 2006.280.08:21:13.19#ibcon#about to read 3, iclass 32, count 0 2006.280.08:21:13.22#ibcon#read 3, iclass 32, count 0 2006.280.08:21:13.22#ibcon#about to read 4, iclass 32, count 0 2006.280.08:21:13.22#ibcon#read 4, iclass 32, count 0 2006.280.08:21:13.22#ibcon#about to read 5, iclass 32, count 0 2006.280.08:21:13.22#ibcon#read 5, iclass 32, count 0 2006.280.08:21:13.22#ibcon#about to read 6, iclass 32, count 0 2006.280.08:21:13.22#ibcon#read 6, iclass 32, count 0 2006.280.08:21:13.22#ibcon#end of sib2, iclass 32, count 0 2006.280.08:21:13.22#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:21:13.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:21:13.22#ibcon#[25=USB\r\n] 2006.280.08:21:13.22#ibcon#*before write, iclass 32, count 0 2006.280.08:21:13.22#ibcon#enter sib2, iclass 32, count 0 2006.280.08:21:13.22#ibcon#flushed, iclass 32, count 0 2006.280.08:21:13.22#ibcon#about to write, iclass 32, count 0 2006.280.08:21:13.22#ibcon#wrote, iclass 32, count 0 2006.280.08:21:13.22#ibcon#about to read 3, iclass 32, count 0 2006.280.08:21:13.24#ibcon#read 3, iclass 32, count 0 2006.280.08:21:13.24#ibcon#about to read 4, iclass 32, count 0 2006.280.08:21:13.24#ibcon#read 4, iclass 32, count 0 2006.280.08:21:13.24#ibcon#about to read 5, iclass 32, count 0 2006.280.08:21:13.24#ibcon#read 5, iclass 32, count 0 2006.280.08:21:13.24#ibcon#about to read 6, iclass 32, count 0 2006.280.08:21:13.24#ibcon#read 6, iclass 32, count 0 2006.280.08:21:13.24#ibcon#end of sib2, iclass 32, count 0 2006.280.08:21:13.24#ibcon#*after write, iclass 32, count 0 2006.280.08:21:13.24#ibcon#*before return 0, iclass 32, count 0 2006.280.08:21:13.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:21:13.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.280.08:21:13.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:21:13.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:21:13.24$vc4f8/valo=7,832.99 2006.280.08:21:13.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.280.08:21:13.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.280.08:21:13.24#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:13.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:21:13.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:21:13.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:21:13.24#ibcon#enter wrdev, iclass 35, count 0 2006.280.08:21:13.24#ibcon#first serial, iclass 35, count 0 2006.280.08:21:13.24#ibcon#enter sib2, iclass 35, count 0 2006.280.08:21:13.24#ibcon#flushed, iclass 35, count 0 2006.280.08:21:13.24#ibcon#about to write, iclass 35, count 0 2006.280.08:21:13.24#ibcon#wrote, iclass 35, count 0 2006.280.08:21:13.24#ibcon#about to read 3, iclass 35, count 0 2006.280.08:21:13.26#ibcon#read 3, iclass 35, count 0 2006.280.08:21:13.26#ibcon#about to read 4, iclass 35, count 0 2006.280.08:21:13.26#ibcon#read 4, iclass 35, count 0 2006.280.08:21:13.26#ibcon#about to read 5, iclass 35, count 0 2006.280.08:21:13.26#ibcon#read 5, iclass 35, count 0 2006.280.08:21:13.26#ibcon#about to read 6, iclass 35, count 0 2006.280.08:21:13.26#ibcon#read 6, iclass 35, count 0 2006.280.08:21:13.26#ibcon#end of sib2, iclass 35, count 0 2006.280.08:21:13.26#ibcon#*mode == 0, iclass 35, count 0 2006.280.08:21:13.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.280.08:21:13.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:21:13.26#ibcon#*before write, iclass 35, count 0 2006.280.08:21:13.26#ibcon#enter sib2, iclass 35, count 0 2006.280.08:21:13.26#ibcon#flushed, iclass 35, count 0 2006.280.08:21:13.26#ibcon#about to write, iclass 35, count 0 2006.280.08:21:13.26#ibcon#wrote, iclass 35, count 0 2006.280.08:21:13.26#ibcon#about to read 3, iclass 35, count 0 2006.280.08:21:13.31#ibcon#read 3, iclass 35, count 0 2006.280.08:21:13.31#ibcon#about to read 4, iclass 35, count 0 2006.280.08:21:13.31#ibcon#read 4, iclass 35, count 0 2006.280.08:21:13.31#ibcon#about to read 5, iclass 35, count 0 2006.280.08:21:13.31#ibcon#read 5, iclass 35, count 0 2006.280.08:21:13.31#ibcon#about to read 6, iclass 35, count 0 2006.280.08:21:13.31#ibcon#read 6, iclass 35, count 0 2006.280.08:21:13.31#ibcon#end of sib2, iclass 35, count 0 2006.280.08:21:13.31#ibcon#*after write, iclass 35, count 0 2006.280.08:21:13.31#ibcon#*before return 0, iclass 35, count 0 2006.280.08:21:13.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:21:13.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.280.08:21:13.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.280.08:21:13.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.280.08:21:13.31$vc4f8/va=7,6 2006.280.08:21:13.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.280.08:21:13.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.280.08:21:13.31#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:13.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:21:13.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:21:13.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:21:13.35#ibcon#enter wrdev, iclass 37, count 2 2006.280.08:21:13.35#ibcon#first serial, iclass 37, count 2 2006.280.08:21:13.35#ibcon#enter sib2, iclass 37, count 2 2006.280.08:21:13.35#ibcon#flushed, iclass 37, count 2 2006.280.08:21:13.35#ibcon#about to write, iclass 37, count 2 2006.280.08:21:13.35#ibcon#wrote, iclass 37, count 2 2006.280.08:21:13.35#ibcon#about to read 3, iclass 37, count 2 2006.280.08:21:13.37#ibcon#read 3, iclass 37, count 2 2006.280.08:21:13.37#ibcon#about to read 4, iclass 37, count 2 2006.280.08:21:13.37#ibcon#read 4, iclass 37, count 2 2006.280.08:21:13.37#ibcon#about to read 5, iclass 37, count 2 2006.280.08:21:13.37#ibcon#read 5, iclass 37, count 2 2006.280.08:21:13.37#ibcon#about to read 6, iclass 37, count 2 2006.280.08:21:13.37#ibcon#read 6, iclass 37, count 2 2006.280.08:21:13.37#ibcon#end of sib2, iclass 37, count 2 2006.280.08:21:13.37#ibcon#*mode == 0, iclass 37, count 2 2006.280.08:21:13.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.280.08:21:13.37#ibcon#[25=AT07-06\r\n] 2006.280.08:21:13.37#ibcon#*before write, iclass 37, count 2 2006.280.08:21:13.37#ibcon#enter sib2, iclass 37, count 2 2006.280.08:21:13.37#ibcon#flushed, iclass 37, count 2 2006.280.08:21:13.37#ibcon#about to write, iclass 37, count 2 2006.280.08:21:13.37#ibcon#wrote, iclass 37, count 2 2006.280.08:21:13.37#ibcon#about to read 3, iclass 37, count 2 2006.280.08:21:13.40#ibcon#read 3, iclass 37, count 2 2006.280.08:21:13.40#ibcon#about to read 4, iclass 37, count 2 2006.280.08:21:13.40#ibcon#read 4, iclass 37, count 2 2006.280.08:21:13.40#ibcon#about to read 5, iclass 37, count 2 2006.280.08:21:13.40#ibcon#read 5, iclass 37, count 2 2006.280.08:21:13.40#ibcon#about to read 6, iclass 37, count 2 2006.280.08:21:13.40#ibcon#read 6, iclass 37, count 2 2006.280.08:21:13.40#ibcon#end of sib2, iclass 37, count 2 2006.280.08:21:13.40#ibcon#*after write, iclass 37, count 2 2006.280.08:21:13.40#ibcon#*before return 0, iclass 37, count 2 2006.280.08:21:13.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:21:13.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.280.08:21:13.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.280.08:21:13.40#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:13.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:21:13.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:21:13.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:21:13.52#ibcon#enter wrdev, iclass 37, count 0 2006.280.08:21:13.52#ibcon#first serial, iclass 37, count 0 2006.280.08:21:13.52#ibcon#enter sib2, iclass 37, count 0 2006.280.08:21:13.52#ibcon#flushed, iclass 37, count 0 2006.280.08:21:13.52#ibcon#about to write, iclass 37, count 0 2006.280.08:21:13.52#ibcon#wrote, iclass 37, count 0 2006.280.08:21:13.52#ibcon#about to read 3, iclass 37, count 0 2006.280.08:21:13.54#ibcon#read 3, iclass 37, count 0 2006.280.08:21:13.54#ibcon#about to read 4, iclass 37, count 0 2006.280.08:21:13.54#ibcon#read 4, iclass 37, count 0 2006.280.08:21:13.54#ibcon#about to read 5, iclass 37, count 0 2006.280.08:21:13.54#ibcon#read 5, iclass 37, count 0 2006.280.08:21:13.54#ibcon#about to read 6, iclass 37, count 0 2006.280.08:21:13.54#ibcon#read 6, iclass 37, count 0 2006.280.08:21:13.54#ibcon#end of sib2, iclass 37, count 0 2006.280.08:21:13.54#ibcon#*mode == 0, iclass 37, count 0 2006.280.08:21:13.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.280.08:21:13.54#ibcon#[25=USB\r\n] 2006.280.08:21:13.54#ibcon#*before write, iclass 37, count 0 2006.280.08:21:13.54#ibcon#enter sib2, iclass 37, count 0 2006.280.08:21:13.54#ibcon#flushed, iclass 37, count 0 2006.280.08:21:13.54#ibcon#about to write, iclass 37, count 0 2006.280.08:21:13.54#ibcon#wrote, iclass 37, count 0 2006.280.08:21:13.54#ibcon#about to read 3, iclass 37, count 0 2006.280.08:21:13.57#ibcon#read 3, iclass 37, count 0 2006.280.08:21:13.57#ibcon#about to read 4, iclass 37, count 0 2006.280.08:21:13.57#ibcon#read 4, iclass 37, count 0 2006.280.08:21:13.57#ibcon#about to read 5, iclass 37, count 0 2006.280.08:21:13.57#ibcon#read 5, iclass 37, count 0 2006.280.08:21:13.57#ibcon#about to read 6, iclass 37, count 0 2006.280.08:21:13.57#ibcon#read 6, iclass 37, count 0 2006.280.08:21:13.57#ibcon#end of sib2, iclass 37, count 0 2006.280.08:21:13.57#ibcon#*after write, iclass 37, count 0 2006.280.08:21:13.57#ibcon#*before return 0, iclass 37, count 0 2006.280.08:21:13.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:21:13.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.280.08:21:13.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.280.08:21:13.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.280.08:21:13.57$vc4f8/valo=8,852.99 2006.280.08:21:13.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.280.08:21:13.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.280.08:21:13.57#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:13.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:21:13.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:21:13.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:21:13.57#ibcon#enter wrdev, iclass 39, count 0 2006.280.08:21:13.57#ibcon#first serial, iclass 39, count 0 2006.280.08:21:13.57#ibcon#enter sib2, iclass 39, count 0 2006.280.08:21:13.57#ibcon#flushed, iclass 39, count 0 2006.280.08:21:13.57#ibcon#about to write, iclass 39, count 0 2006.280.08:21:13.57#ibcon#wrote, iclass 39, count 0 2006.280.08:21:13.57#ibcon#about to read 3, iclass 39, count 0 2006.280.08:21:13.59#ibcon#read 3, iclass 39, count 0 2006.280.08:21:13.59#ibcon#about to read 4, iclass 39, count 0 2006.280.08:21:13.59#ibcon#read 4, iclass 39, count 0 2006.280.08:21:13.59#ibcon#about to read 5, iclass 39, count 0 2006.280.08:21:13.59#ibcon#read 5, iclass 39, count 0 2006.280.08:21:13.59#ibcon#about to read 6, iclass 39, count 0 2006.280.08:21:13.59#ibcon#read 6, iclass 39, count 0 2006.280.08:21:13.59#ibcon#end of sib2, iclass 39, count 0 2006.280.08:21:13.59#ibcon#*mode == 0, iclass 39, count 0 2006.280.08:21:13.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.280.08:21:13.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:21:13.59#ibcon#*before write, iclass 39, count 0 2006.280.08:21:13.59#ibcon#enter sib2, iclass 39, count 0 2006.280.08:21:13.59#ibcon#flushed, iclass 39, count 0 2006.280.08:21:13.59#ibcon#about to write, iclass 39, count 0 2006.280.08:21:13.59#ibcon#wrote, iclass 39, count 0 2006.280.08:21:13.59#ibcon#about to read 3, iclass 39, count 0 2006.280.08:21:13.63#ibcon#read 3, iclass 39, count 0 2006.280.08:21:13.63#ibcon#about to read 4, iclass 39, count 0 2006.280.08:21:13.63#ibcon#read 4, iclass 39, count 0 2006.280.08:21:13.63#ibcon#about to read 5, iclass 39, count 0 2006.280.08:21:13.63#ibcon#read 5, iclass 39, count 0 2006.280.08:21:13.63#ibcon#about to read 6, iclass 39, count 0 2006.280.08:21:13.63#ibcon#read 6, iclass 39, count 0 2006.280.08:21:13.63#ibcon#end of sib2, iclass 39, count 0 2006.280.08:21:13.63#ibcon#*after write, iclass 39, count 0 2006.280.08:21:13.63#ibcon#*before return 0, iclass 39, count 0 2006.280.08:21:13.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:21:13.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.280.08:21:13.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.280.08:21:13.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.280.08:21:13.63$vc4f8/va=8,6 2006.280.08:21:13.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.280.08:21:13.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.280.08:21:13.63#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:13.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:21:13.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:21:13.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:21:13.69#ibcon#enter wrdev, iclass 3, count 2 2006.280.08:21:13.69#ibcon#first serial, iclass 3, count 2 2006.280.08:21:13.69#ibcon#enter sib2, iclass 3, count 2 2006.280.08:21:13.69#ibcon#flushed, iclass 3, count 2 2006.280.08:21:13.69#ibcon#about to write, iclass 3, count 2 2006.280.08:21:13.69#ibcon#wrote, iclass 3, count 2 2006.280.08:21:13.69#ibcon#about to read 3, iclass 3, count 2 2006.280.08:21:13.72#ibcon#read 3, iclass 3, count 2 2006.280.08:21:13.72#ibcon#about to read 4, iclass 3, count 2 2006.280.08:21:13.72#ibcon#read 4, iclass 3, count 2 2006.280.08:21:13.72#ibcon#about to read 5, iclass 3, count 2 2006.280.08:21:13.72#ibcon#read 5, iclass 3, count 2 2006.280.08:21:13.72#ibcon#about to read 6, iclass 3, count 2 2006.280.08:21:13.72#ibcon#read 6, iclass 3, count 2 2006.280.08:21:13.72#ibcon#end of sib2, iclass 3, count 2 2006.280.08:21:13.72#ibcon#*mode == 0, iclass 3, count 2 2006.280.08:21:13.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.280.08:21:13.72#ibcon#[25=AT08-06\r\n] 2006.280.08:21:13.72#ibcon#*before write, iclass 3, count 2 2006.280.08:21:13.72#ibcon#enter sib2, iclass 3, count 2 2006.280.08:21:13.72#ibcon#flushed, iclass 3, count 2 2006.280.08:21:13.72#ibcon#about to write, iclass 3, count 2 2006.280.08:21:13.72#ibcon#wrote, iclass 3, count 2 2006.280.08:21:13.72#ibcon#about to read 3, iclass 3, count 2 2006.280.08:21:13.75#ibcon#read 3, iclass 3, count 2 2006.280.08:21:13.75#ibcon#about to read 4, iclass 3, count 2 2006.280.08:21:13.75#ibcon#read 4, iclass 3, count 2 2006.280.08:21:13.75#ibcon#about to read 5, iclass 3, count 2 2006.280.08:21:13.75#ibcon#read 5, iclass 3, count 2 2006.280.08:21:13.75#ibcon#about to read 6, iclass 3, count 2 2006.280.08:21:13.75#ibcon#read 6, iclass 3, count 2 2006.280.08:21:13.75#ibcon#end of sib2, iclass 3, count 2 2006.280.08:21:13.75#ibcon#*after write, iclass 3, count 2 2006.280.08:21:13.75#ibcon#*before return 0, iclass 3, count 2 2006.280.08:21:13.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:21:13.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.280.08:21:13.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.280.08:21:13.75#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:13.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:21:13.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:21:13.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:21:13.87#ibcon#enter wrdev, iclass 3, count 0 2006.280.08:21:13.87#ibcon#first serial, iclass 3, count 0 2006.280.08:21:13.87#ibcon#enter sib2, iclass 3, count 0 2006.280.08:21:13.87#ibcon#flushed, iclass 3, count 0 2006.280.08:21:13.87#ibcon#about to write, iclass 3, count 0 2006.280.08:21:13.87#ibcon#wrote, iclass 3, count 0 2006.280.08:21:13.87#ibcon#about to read 3, iclass 3, count 0 2006.280.08:21:13.89#ibcon#read 3, iclass 3, count 0 2006.280.08:21:13.89#ibcon#about to read 4, iclass 3, count 0 2006.280.08:21:13.89#ibcon#read 4, iclass 3, count 0 2006.280.08:21:13.89#ibcon#about to read 5, iclass 3, count 0 2006.280.08:21:13.89#ibcon#read 5, iclass 3, count 0 2006.280.08:21:13.89#ibcon#about to read 6, iclass 3, count 0 2006.280.08:21:13.89#ibcon#read 6, iclass 3, count 0 2006.280.08:21:13.89#ibcon#end of sib2, iclass 3, count 0 2006.280.08:21:13.89#ibcon#*mode == 0, iclass 3, count 0 2006.280.08:21:13.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.280.08:21:13.89#ibcon#[25=USB\r\n] 2006.280.08:21:13.89#ibcon#*before write, iclass 3, count 0 2006.280.08:21:13.89#ibcon#enter sib2, iclass 3, count 0 2006.280.08:21:13.89#ibcon#flushed, iclass 3, count 0 2006.280.08:21:13.89#ibcon#about to write, iclass 3, count 0 2006.280.08:21:13.89#ibcon#wrote, iclass 3, count 0 2006.280.08:21:13.89#ibcon#about to read 3, iclass 3, count 0 2006.280.08:21:13.93#ibcon#read 3, iclass 3, count 0 2006.280.08:21:13.93#ibcon#about to read 4, iclass 3, count 0 2006.280.08:21:13.93#ibcon#read 4, iclass 3, count 0 2006.280.08:21:13.93#ibcon#about to read 5, iclass 3, count 0 2006.280.08:21:13.93#ibcon#read 5, iclass 3, count 0 2006.280.08:21:13.93#ibcon#about to read 6, iclass 3, count 0 2006.280.08:21:13.93#ibcon#read 6, iclass 3, count 0 2006.280.08:21:13.93#ibcon#end of sib2, iclass 3, count 0 2006.280.08:21:13.93#ibcon#*after write, iclass 3, count 0 2006.280.08:21:13.93#ibcon#*before return 0, iclass 3, count 0 2006.280.08:21:13.93#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:21:13.93#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.280.08:21:13.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.280.08:21:13.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.280.08:21:13.93$vc4f8/vblo=1,632.99 2006.280.08:21:13.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.280.08:21:13.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.280.08:21:13.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:13.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:13.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:13.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:13.93#ibcon#enter wrdev, iclass 5, count 0 2006.280.08:21:13.93#ibcon#first serial, iclass 5, count 0 2006.280.08:21:13.93#ibcon#enter sib2, iclass 5, count 0 2006.280.08:21:13.93#ibcon#flushed, iclass 5, count 0 2006.280.08:21:13.93#ibcon#about to write, iclass 5, count 0 2006.280.08:21:13.93#ibcon#wrote, iclass 5, count 0 2006.280.08:21:13.93#ibcon#about to read 3, iclass 5, count 0 2006.280.08:21:13.94#ibcon#read 3, iclass 5, count 0 2006.280.08:21:13.94#ibcon#about to read 4, iclass 5, count 0 2006.280.08:21:13.94#ibcon#read 4, iclass 5, count 0 2006.280.08:21:13.94#ibcon#about to read 5, iclass 5, count 0 2006.280.08:21:13.94#ibcon#read 5, iclass 5, count 0 2006.280.08:21:13.94#ibcon#about to read 6, iclass 5, count 0 2006.280.08:21:13.94#ibcon#read 6, iclass 5, count 0 2006.280.08:21:13.94#ibcon#end of sib2, iclass 5, count 0 2006.280.08:21:13.94#ibcon#*mode == 0, iclass 5, count 0 2006.280.08:21:13.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.280.08:21:13.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:21:13.97#ibcon#*before write, iclass 5, count 0 2006.280.08:21:13.97#ibcon#enter sib2, iclass 5, count 0 2006.280.08:21:13.97#ibcon#flushed, iclass 5, count 0 2006.280.08:21:13.97#ibcon#about to write, iclass 5, count 0 2006.280.08:21:13.97#ibcon#wrote, iclass 5, count 0 2006.280.08:21:13.97#ibcon#about to read 3, iclass 5, count 0 2006.280.08:21:14.02#ibcon#read 3, iclass 5, count 0 2006.280.08:21:14.02#ibcon#about to read 4, iclass 5, count 0 2006.280.08:21:14.02#ibcon#read 4, iclass 5, count 0 2006.280.08:21:14.02#ibcon#about to read 5, iclass 5, count 0 2006.280.08:21:14.02#ibcon#read 5, iclass 5, count 0 2006.280.08:21:14.02#ibcon#about to read 6, iclass 5, count 0 2006.280.08:21:14.02#ibcon#read 6, iclass 5, count 0 2006.280.08:21:14.02#ibcon#end of sib2, iclass 5, count 0 2006.280.08:21:14.02#ibcon#*after write, iclass 5, count 0 2006.280.08:21:14.02#ibcon#*before return 0, iclass 5, count 0 2006.280.08:21:14.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:14.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.280.08:21:14.02#ibcon#about to clear, iclass 5 cls_cnt 0 2006.280.08:21:14.02#ibcon#cleared, iclass 5 cls_cnt 0 2006.280.08:21:14.02$vc4f8/vb=1,4 2006.280.08:21:14.02#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.280.08:21:14.02#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.280.08:21:14.02#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:14.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:14.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:14.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:14.02#ibcon#enter wrdev, iclass 7, count 2 2006.280.08:21:14.02#ibcon#first serial, iclass 7, count 2 2006.280.08:21:14.02#ibcon#enter sib2, iclass 7, count 2 2006.280.08:21:14.02#ibcon#flushed, iclass 7, count 2 2006.280.08:21:14.02#ibcon#about to write, iclass 7, count 2 2006.280.08:21:14.02#ibcon#wrote, iclass 7, count 2 2006.280.08:21:14.02#ibcon#about to read 3, iclass 7, count 2 2006.280.08:21:14.03#ibcon#read 3, iclass 7, count 2 2006.280.08:21:14.03#ibcon#about to read 4, iclass 7, count 2 2006.280.08:21:14.03#ibcon#read 4, iclass 7, count 2 2006.280.08:21:14.03#ibcon#about to read 5, iclass 7, count 2 2006.280.08:21:14.03#ibcon#read 5, iclass 7, count 2 2006.280.08:21:14.03#ibcon#about to read 6, iclass 7, count 2 2006.280.08:21:14.03#ibcon#read 6, iclass 7, count 2 2006.280.08:21:14.03#ibcon#end of sib2, iclass 7, count 2 2006.280.08:21:14.03#ibcon#*mode == 0, iclass 7, count 2 2006.280.08:21:14.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.280.08:21:14.03#ibcon#[27=AT01-04\r\n] 2006.280.08:21:14.03#ibcon#*before write, iclass 7, count 2 2006.280.08:21:14.03#ibcon#enter sib2, iclass 7, count 2 2006.280.08:21:14.03#ibcon#flushed, iclass 7, count 2 2006.280.08:21:14.03#ibcon#about to write, iclass 7, count 2 2006.280.08:21:14.03#ibcon#wrote, iclass 7, count 2 2006.280.08:21:14.03#ibcon#about to read 3, iclass 7, count 2 2006.280.08:21:14.06#ibcon#read 3, iclass 7, count 2 2006.280.08:21:14.08#ibcon#about to read 4, iclass 7, count 2 2006.280.08:21:14.08#ibcon#read 4, iclass 7, count 2 2006.280.08:21:14.08#ibcon#about to read 5, iclass 7, count 2 2006.280.08:21:14.08#ibcon#read 5, iclass 7, count 2 2006.280.08:21:14.08#ibcon#about to read 6, iclass 7, count 2 2006.280.08:21:14.08#ibcon#read 6, iclass 7, count 2 2006.280.08:21:14.08#ibcon#end of sib2, iclass 7, count 2 2006.280.08:21:14.08#ibcon#*after write, iclass 7, count 2 2006.280.08:21:14.08#ibcon#*before return 0, iclass 7, count 2 2006.280.08:21:14.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:14.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.280.08:21:14.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.280.08:21:14.08#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:14.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:14.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:14.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:14.19#ibcon#enter wrdev, iclass 7, count 0 2006.280.08:21:14.19#ibcon#first serial, iclass 7, count 0 2006.280.08:21:14.19#ibcon#enter sib2, iclass 7, count 0 2006.280.08:21:14.19#ibcon#flushed, iclass 7, count 0 2006.280.08:21:14.19#ibcon#about to write, iclass 7, count 0 2006.280.08:21:14.19#ibcon#wrote, iclass 7, count 0 2006.280.08:21:14.19#ibcon#about to read 3, iclass 7, count 0 2006.280.08:21:14.21#ibcon#read 3, iclass 7, count 0 2006.280.08:21:14.21#ibcon#about to read 4, iclass 7, count 0 2006.280.08:21:14.21#ibcon#read 4, iclass 7, count 0 2006.280.08:21:14.21#ibcon#about to read 5, iclass 7, count 0 2006.280.08:21:14.21#ibcon#read 5, iclass 7, count 0 2006.280.08:21:14.21#ibcon#about to read 6, iclass 7, count 0 2006.280.08:21:14.21#ibcon#read 6, iclass 7, count 0 2006.280.08:21:14.21#ibcon#end of sib2, iclass 7, count 0 2006.280.08:21:14.21#ibcon#*mode == 0, iclass 7, count 0 2006.280.08:21:14.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.280.08:21:14.21#ibcon#[27=USB\r\n] 2006.280.08:21:14.21#ibcon#*before write, iclass 7, count 0 2006.280.08:21:14.21#ibcon#enter sib2, iclass 7, count 0 2006.280.08:21:14.21#ibcon#flushed, iclass 7, count 0 2006.280.08:21:14.21#ibcon#about to write, iclass 7, count 0 2006.280.08:21:14.21#ibcon#wrote, iclass 7, count 0 2006.280.08:21:14.21#ibcon#about to read 3, iclass 7, count 0 2006.280.08:21:14.25#ibcon#read 3, iclass 7, count 0 2006.280.08:21:14.25#ibcon#about to read 4, iclass 7, count 0 2006.280.08:21:14.25#ibcon#read 4, iclass 7, count 0 2006.280.08:21:14.25#ibcon#about to read 5, iclass 7, count 0 2006.280.08:21:14.25#ibcon#read 5, iclass 7, count 0 2006.280.08:21:14.25#ibcon#about to read 6, iclass 7, count 0 2006.280.08:21:14.25#ibcon#read 6, iclass 7, count 0 2006.280.08:21:14.25#ibcon#end of sib2, iclass 7, count 0 2006.280.08:21:14.25#ibcon#*after write, iclass 7, count 0 2006.280.08:21:14.25#ibcon#*before return 0, iclass 7, count 0 2006.280.08:21:14.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:14.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.280.08:21:14.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.280.08:21:14.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.280.08:21:14.25$vc4f8/vblo=2,640.99 2006.280.08:21:14.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.280.08:21:14.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.280.08:21:14.25#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:14.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:14.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:14.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:14.25#ibcon#enter wrdev, iclass 11, count 0 2006.280.08:21:14.25#ibcon#first serial, iclass 11, count 0 2006.280.08:21:14.25#ibcon#enter sib2, iclass 11, count 0 2006.280.08:21:14.25#ibcon#flushed, iclass 11, count 0 2006.280.08:21:14.25#ibcon#about to write, iclass 11, count 0 2006.280.08:21:14.25#ibcon#wrote, iclass 11, count 0 2006.280.08:21:14.25#ibcon#about to read 3, iclass 11, count 0 2006.280.08:21:14.26#ibcon#read 3, iclass 11, count 0 2006.280.08:21:14.26#ibcon#about to read 4, iclass 11, count 0 2006.280.08:21:14.26#ibcon#read 4, iclass 11, count 0 2006.280.08:21:14.26#ibcon#about to read 5, iclass 11, count 0 2006.280.08:21:14.26#ibcon#read 5, iclass 11, count 0 2006.280.08:21:14.26#ibcon#about to read 6, iclass 11, count 0 2006.280.08:21:14.26#ibcon#read 6, iclass 11, count 0 2006.280.08:21:14.26#ibcon#end of sib2, iclass 11, count 0 2006.280.08:21:14.26#ibcon#*mode == 0, iclass 11, count 0 2006.280.08:21:14.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.280.08:21:14.26#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:21:14.26#ibcon#*before write, iclass 11, count 0 2006.280.08:21:14.29#ibcon#enter sib2, iclass 11, count 0 2006.280.08:21:14.29#ibcon#flushed, iclass 11, count 0 2006.280.08:21:14.29#ibcon#about to write, iclass 11, count 0 2006.280.08:21:14.29#ibcon#wrote, iclass 11, count 0 2006.280.08:21:14.29#ibcon#about to read 3, iclass 11, count 0 2006.280.08:21:14.33#ibcon#read 3, iclass 11, count 0 2006.280.08:21:14.33#ibcon#about to read 4, iclass 11, count 0 2006.280.08:21:14.33#ibcon#read 4, iclass 11, count 0 2006.280.08:21:14.33#ibcon#about to read 5, iclass 11, count 0 2006.280.08:21:14.33#ibcon#read 5, iclass 11, count 0 2006.280.08:21:14.33#ibcon#about to read 6, iclass 11, count 0 2006.280.08:21:14.33#ibcon#read 6, iclass 11, count 0 2006.280.08:21:14.33#ibcon#end of sib2, iclass 11, count 0 2006.280.08:21:14.33#ibcon#*after write, iclass 11, count 0 2006.280.08:21:14.33#ibcon#*before return 0, iclass 11, count 0 2006.280.08:21:14.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:14.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.280.08:21:14.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.280.08:21:14.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.280.08:21:14.33$vc4f8/vb=2,5 2006.280.08:21:14.33#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.280.08:21:14.33#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.280.08:21:14.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:14.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:14.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:14.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:14.37#ibcon#enter wrdev, iclass 13, count 2 2006.280.08:21:14.37#ibcon#first serial, iclass 13, count 2 2006.280.08:21:14.37#ibcon#enter sib2, iclass 13, count 2 2006.280.08:21:14.37#ibcon#flushed, iclass 13, count 2 2006.280.08:21:14.37#ibcon#about to write, iclass 13, count 2 2006.280.08:21:14.37#ibcon#wrote, iclass 13, count 2 2006.280.08:21:14.37#ibcon#about to read 3, iclass 13, count 2 2006.280.08:21:14.39#ibcon#read 3, iclass 13, count 2 2006.280.08:21:14.39#ibcon#about to read 4, iclass 13, count 2 2006.280.08:21:14.39#ibcon#read 4, iclass 13, count 2 2006.280.08:21:14.39#ibcon#about to read 5, iclass 13, count 2 2006.280.08:21:14.39#ibcon#read 5, iclass 13, count 2 2006.280.08:21:14.39#ibcon#about to read 6, iclass 13, count 2 2006.280.08:21:14.39#ibcon#read 6, iclass 13, count 2 2006.280.08:21:14.39#ibcon#end of sib2, iclass 13, count 2 2006.280.08:21:14.39#ibcon#*mode == 0, iclass 13, count 2 2006.280.08:21:14.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.280.08:21:14.39#ibcon#[27=AT02-05\r\n] 2006.280.08:21:14.39#ibcon#*before write, iclass 13, count 2 2006.280.08:21:14.39#ibcon#enter sib2, iclass 13, count 2 2006.280.08:21:14.39#ibcon#flushed, iclass 13, count 2 2006.280.08:21:14.39#ibcon#about to write, iclass 13, count 2 2006.280.08:21:14.39#ibcon#wrote, iclass 13, count 2 2006.280.08:21:14.39#ibcon#about to read 3, iclass 13, count 2 2006.280.08:21:14.42#ibcon#read 3, iclass 13, count 2 2006.280.08:21:14.42#ibcon#about to read 4, iclass 13, count 2 2006.280.08:21:14.42#ibcon#read 4, iclass 13, count 2 2006.280.08:21:14.42#ibcon#about to read 5, iclass 13, count 2 2006.280.08:21:14.42#ibcon#read 5, iclass 13, count 2 2006.280.08:21:14.42#ibcon#about to read 6, iclass 13, count 2 2006.280.08:21:14.42#ibcon#read 6, iclass 13, count 2 2006.280.08:21:14.42#ibcon#end of sib2, iclass 13, count 2 2006.280.08:21:14.42#ibcon#*after write, iclass 13, count 2 2006.280.08:21:14.42#ibcon#*before return 0, iclass 13, count 2 2006.280.08:21:14.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:14.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.280.08:21:14.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.280.08:21:14.42#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:14.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:14.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:14.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:14.54#ibcon#enter wrdev, iclass 13, count 0 2006.280.08:21:14.54#ibcon#first serial, iclass 13, count 0 2006.280.08:21:14.54#ibcon#enter sib2, iclass 13, count 0 2006.280.08:21:14.54#ibcon#flushed, iclass 13, count 0 2006.280.08:21:14.54#ibcon#about to write, iclass 13, count 0 2006.280.08:21:14.54#ibcon#wrote, iclass 13, count 0 2006.280.08:21:14.54#ibcon#about to read 3, iclass 13, count 0 2006.280.08:21:14.56#ibcon#read 3, iclass 13, count 0 2006.280.08:21:14.56#ibcon#about to read 4, iclass 13, count 0 2006.280.08:21:14.56#ibcon#read 4, iclass 13, count 0 2006.280.08:21:14.56#ibcon#about to read 5, iclass 13, count 0 2006.280.08:21:14.56#ibcon#read 5, iclass 13, count 0 2006.280.08:21:14.56#ibcon#about to read 6, iclass 13, count 0 2006.280.08:21:14.56#ibcon#read 6, iclass 13, count 0 2006.280.08:21:14.56#ibcon#end of sib2, iclass 13, count 0 2006.280.08:21:14.56#ibcon#*mode == 0, iclass 13, count 0 2006.280.08:21:14.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.280.08:21:14.56#ibcon#[27=USB\r\n] 2006.280.08:21:14.56#ibcon#*before write, iclass 13, count 0 2006.280.08:21:14.56#ibcon#enter sib2, iclass 13, count 0 2006.280.08:21:14.56#ibcon#flushed, iclass 13, count 0 2006.280.08:21:14.56#ibcon#about to write, iclass 13, count 0 2006.280.08:21:14.56#ibcon#wrote, iclass 13, count 0 2006.280.08:21:14.56#ibcon#about to read 3, iclass 13, count 0 2006.280.08:21:14.59#ibcon#read 3, iclass 13, count 0 2006.280.08:21:14.59#ibcon#about to read 4, iclass 13, count 0 2006.280.08:21:14.59#ibcon#read 4, iclass 13, count 0 2006.280.08:21:14.59#ibcon#about to read 5, iclass 13, count 0 2006.280.08:21:14.59#ibcon#read 5, iclass 13, count 0 2006.280.08:21:14.59#ibcon#about to read 6, iclass 13, count 0 2006.280.08:21:14.59#ibcon#read 6, iclass 13, count 0 2006.280.08:21:14.59#ibcon#end of sib2, iclass 13, count 0 2006.280.08:21:14.59#ibcon#*after write, iclass 13, count 0 2006.280.08:21:14.59#ibcon#*before return 0, iclass 13, count 0 2006.280.08:21:14.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:14.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.280.08:21:14.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.280.08:21:14.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.280.08:21:14.59$vc4f8/vblo=3,656.99 2006.280.08:21:14.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.280.08:21:14.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.280.08:21:14.59#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:14.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:14.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:14.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:14.59#ibcon#enter wrdev, iclass 15, count 0 2006.280.08:21:14.59#ibcon#first serial, iclass 15, count 0 2006.280.08:21:14.59#ibcon#enter sib2, iclass 15, count 0 2006.280.08:21:14.59#ibcon#flushed, iclass 15, count 0 2006.280.08:21:14.59#ibcon#about to write, iclass 15, count 0 2006.280.08:21:14.59#ibcon#wrote, iclass 15, count 0 2006.280.08:21:14.59#ibcon#about to read 3, iclass 15, count 0 2006.280.08:21:14.61#ibcon#read 3, iclass 15, count 0 2006.280.08:21:14.61#ibcon#about to read 4, iclass 15, count 0 2006.280.08:21:14.62#ibcon#read 4, iclass 15, count 0 2006.280.08:21:14.62#ibcon#about to read 5, iclass 15, count 0 2006.280.08:21:14.62#ibcon#read 5, iclass 15, count 0 2006.280.08:21:14.62#ibcon#about to read 6, iclass 15, count 0 2006.280.08:21:14.62#ibcon#read 6, iclass 15, count 0 2006.280.08:21:14.62#ibcon#end of sib2, iclass 15, count 0 2006.280.08:21:14.62#ibcon#*mode == 0, iclass 15, count 0 2006.280.08:21:14.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.280.08:21:14.62#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:21:14.62#ibcon#*before write, iclass 15, count 0 2006.280.08:21:14.62#ibcon#enter sib2, iclass 15, count 0 2006.280.08:21:14.62#ibcon#flushed, iclass 15, count 0 2006.280.08:21:14.62#ibcon#about to write, iclass 15, count 0 2006.280.08:21:14.62#ibcon#wrote, iclass 15, count 0 2006.280.08:21:14.62#ibcon#about to read 3, iclass 15, count 0 2006.280.08:21:14.65#ibcon#read 3, iclass 15, count 0 2006.280.08:21:14.65#ibcon#about to read 4, iclass 15, count 0 2006.280.08:21:14.65#ibcon#read 4, iclass 15, count 0 2006.280.08:21:14.65#ibcon#about to read 5, iclass 15, count 0 2006.280.08:21:14.65#ibcon#read 5, iclass 15, count 0 2006.280.08:21:14.65#ibcon#about to read 6, iclass 15, count 0 2006.280.08:21:14.65#ibcon#read 6, iclass 15, count 0 2006.280.08:21:14.65#ibcon#end of sib2, iclass 15, count 0 2006.280.08:21:14.65#ibcon#*after write, iclass 15, count 0 2006.280.08:21:14.65#ibcon#*before return 0, iclass 15, count 0 2006.280.08:21:14.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:14.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.280.08:21:14.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.280.08:21:14.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.280.08:21:14.65$vc4f8/vb=3,4 2006.280.08:21:14.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.280.08:21:14.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.280.08:21:14.65#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:14.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:14.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:14.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:14.72#ibcon#enter wrdev, iclass 17, count 2 2006.280.08:21:14.72#ibcon#first serial, iclass 17, count 2 2006.280.08:21:14.72#ibcon#enter sib2, iclass 17, count 2 2006.280.08:21:14.72#ibcon#flushed, iclass 17, count 2 2006.280.08:21:14.72#ibcon#about to write, iclass 17, count 2 2006.280.08:21:14.72#ibcon#wrote, iclass 17, count 2 2006.280.08:21:14.72#ibcon#about to read 3, iclass 17, count 2 2006.280.08:21:14.73#ibcon#read 3, iclass 17, count 2 2006.280.08:21:14.73#ibcon#about to read 4, iclass 17, count 2 2006.280.08:21:14.73#ibcon#read 4, iclass 17, count 2 2006.280.08:21:14.73#ibcon#about to read 5, iclass 17, count 2 2006.280.08:21:14.73#ibcon#read 5, iclass 17, count 2 2006.280.08:21:14.73#ibcon#about to read 6, iclass 17, count 2 2006.280.08:21:14.73#ibcon#read 6, iclass 17, count 2 2006.280.08:21:14.73#ibcon#end of sib2, iclass 17, count 2 2006.280.08:21:14.73#ibcon#*mode == 0, iclass 17, count 2 2006.280.08:21:14.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.280.08:21:14.73#ibcon#[27=AT03-04\r\n] 2006.280.08:21:14.73#ibcon#*before write, iclass 17, count 2 2006.280.08:21:14.73#ibcon#enter sib2, iclass 17, count 2 2006.280.08:21:14.73#ibcon#flushed, iclass 17, count 2 2006.280.08:21:14.73#ibcon#about to write, iclass 17, count 2 2006.280.08:21:14.73#ibcon#wrote, iclass 17, count 2 2006.280.08:21:14.73#ibcon#about to read 3, iclass 17, count 2 2006.280.08:21:14.76#ibcon#read 3, iclass 17, count 2 2006.280.08:21:14.76#ibcon#about to read 4, iclass 17, count 2 2006.280.08:21:14.76#ibcon#read 4, iclass 17, count 2 2006.280.08:21:14.76#ibcon#about to read 5, iclass 17, count 2 2006.280.08:21:14.76#ibcon#read 5, iclass 17, count 2 2006.280.08:21:14.76#ibcon#about to read 6, iclass 17, count 2 2006.280.08:21:14.76#ibcon#read 6, iclass 17, count 2 2006.280.08:21:14.76#ibcon#end of sib2, iclass 17, count 2 2006.280.08:21:14.76#ibcon#*after write, iclass 17, count 2 2006.280.08:21:14.76#ibcon#*before return 0, iclass 17, count 2 2006.280.08:21:14.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:14.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.280.08:21:14.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.280.08:21:14.76#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:14.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:14.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:14.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:14.88#ibcon#enter wrdev, iclass 17, count 0 2006.280.08:21:14.88#ibcon#first serial, iclass 17, count 0 2006.280.08:21:14.88#ibcon#enter sib2, iclass 17, count 0 2006.280.08:21:14.88#ibcon#flushed, iclass 17, count 0 2006.280.08:21:14.88#ibcon#about to write, iclass 17, count 0 2006.280.08:21:14.88#ibcon#wrote, iclass 17, count 0 2006.280.08:21:14.88#ibcon#about to read 3, iclass 17, count 0 2006.280.08:21:14.90#ibcon#read 3, iclass 17, count 0 2006.280.08:21:14.90#ibcon#about to read 4, iclass 17, count 0 2006.280.08:21:14.90#ibcon#read 4, iclass 17, count 0 2006.280.08:21:14.90#ibcon#about to read 5, iclass 17, count 0 2006.280.08:21:14.90#ibcon#read 5, iclass 17, count 0 2006.280.08:21:14.90#ibcon#about to read 6, iclass 17, count 0 2006.280.08:21:14.90#ibcon#read 6, iclass 17, count 0 2006.280.08:21:14.90#ibcon#end of sib2, iclass 17, count 0 2006.280.08:21:14.90#ibcon#*mode == 0, iclass 17, count 0 2006.280.08:21:14.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.280.08:21:14.90#ibcon#[27=USB\r\n] 2006.280.08:21:14.90#ibcon#*before write, iclass 17, count 0 2006.280.08:21:14.90#ibcon#enter sib2, iclass 17, count 0 2006.280.08:21:14.90#ibcon#flushed, iclass 17, count 0 2006.280.08:21:14.90#ibcon#about to write, iclass 17, count 0 2006.280.08:21:14.90#ibcon#wrote, iclass 17, count 0 2006.280.08:21:14.90#ibcon#about to read 3, iclass 17, count 0 2006.280.08:21:14.93#ibcon#read 3, iclass 17, count 0 2006.280.08:21:14.93#ibcon#about to read 4, iclass 17, count 0 2006.280.08:21:14.93#ibcon#read 4, iclass 17, count 0 2006.280.08:21:14.93#ibcon#about to read 5, iclass 17, count 0 2006.280.08:21:14.93#ibcon#read 5, iclass 17, count 0 2006.280.08:21:14.93#ibcon#about to read 6, iclass 17, count 0 2006.280.08:21:14.93#ibcon#read 6, iclass 17, count 0 2006.280.08:21:14.93#ibcon#end of sib2, iclass 17, count 0 2006.280.08:21:14.93#ibcon#*after write, iclass 17, count 0 2006.280.08:21:14.93#ibcon#*before return 0, iclass 17, count 0 2006.280.08:21:14.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:14.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.280.08:21:14.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.280.08:21:14.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.280.08:21:14.93$vc4f8/vblo=4,712.99 2006.280.08:21:14.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.280.08:21:14.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.280.08:21:14.93#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:14.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:14.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:14.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:14.93#ibcon#enter wrdev, iclass 19, count 0 2006.280.08:21:14.93#ibcon#first serial, iclass 19, count 0 2006.280.08:21:14.93#ibcon#enter sib2, iclass 19, count 0 2006.280.08:21:14.93#ibcon#flushed, iclass 19, count 0 2006.280.08:21:14.93#ibcon#about to write, iclass 19, count 0 2006.280.08:21:14.93#ibcon#wrote, iclass 19, count 0 2006.280.08:21:14.93#ibcon#about to read 3, iclass 19, count 0 2006.280.08:21:14.95#ibcon#read 3, iclass 19, count 0 2006.280.08:21:14.96#ibcon#about to read 4, iclass 19, count 0 2006.280.08:21:14.96#ibcon#read 4, iclass 19, count 0 2006.280.08:21:14.96#ibcon#about to read 5, iclass 19, count 0 2006.280.08:21:14.96#ibcon#read 5, iclass 19, count 0 2006.280.08:21:14.96#ibcon#about to read 6, iclass 19, count 0 2006.280.08:21:14.96#ibcon#read 6, iclass 19, count 0 2006.280.08:21:14.96#ibcon#end of sib2, iclass 19, count 0 2006.280.08:21:14.96#ibcon#*mode == 0, iclass 19, count 0 2006.280.08:21:14.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.280.08:21:14.96#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:21:14.96#ibcon#*before write, iclass 19, count 0 2006.280.08:21:14.96#ibcon#enter sib2, iclass 19, count 0 2006.280.08:21:14.96#ibcon#flushed, iclass 19, count 0 2006.280.08:21:14.96#ibcon#about to write, iclass 19, count 0 2006.280.08:21:14.96#ibcon#wrote, iclass 19, count 0 2006.280.08:21:14.96#ibcon#about to read 3, iclass 19, count 0 2006.280.08:21:14.99#ibcon#read 3, iclass 19, count 0 2006.280.08:21:14.99#ibcon#about to read 4, iclass 19, count 0 2006.280.08:21:14.99#ibcon#read 4, iclass 19, count 0 2006.280.08:21:14.99#ibcon#about to read 5, iclass 19, count 0 2006.280.08:21:14.99#ibcon#read 5, iclass 19, count 0 2006.280.08:21:14.99#ibcon#about to read 6, iclass 19, count 0 2006.280.08:21:14.99#ibcon#read 6, iclass 19, count 0 2006.280.08:21:14.99#ibcon#end of sib2, iclass 19, count 0 2006.280.08:21:14.99#ibcon#*after write, iclass 19, count 0 2006.280.08:21:14.99#ibcon#*before return 0, iclass 19, count 0 2006.280.08:21:14.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:14.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.280.08:21:14.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.280.08:21:14.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.280.08:21:14.99$vc4f8/vb=4,4 2006.280.08:21:14.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.280.08:21:14.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.280.08:21:14.99#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:14.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:15.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:15.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:15.05#ibcon#enter wrdev, iclass 21, count 2 2006.280.08:21:15.05#ibcon#first serial, iclass 21, count 2 2006.280.08:21:15.05#ibcon#enter sib2, iclass 21, count 2 2006.280.08:21:15.05#ibcon#flushed, iclass 21, count 2 2006.280.08:21:15.05#ibcon#about to write, iclass 21, count 2 2006.280.08:21:15.05#ibcon#wrote, iclass 21, count 2 2006.280.08:21:15.05#ibcon#about to read 3, iclass 21, count 2 2006.280.08:21:15.07#ibcon#read 3, iclass 21, count 2 2006.280.08:21:15.07#ibcon#about to read 4, iclass 21, count 2 2006.280.08:21:15.07#ibcon#read 4, iclass 21, count 2 2006.280.08:21:15.07#ibcon#about to read 5, iclass 21, count 2 2006.280.08:21:15.07#ibcon#read 5, iclass 21, count 2 2006.280.08:21:15.07#ibcon#about to read 6, iclass 21, count 2 2006.280.08:21:15.07#ibcon#read 6, iclass 21, count 2 2006.280.08:21:15.07#ibcon#end of sib2, iclass 21, count 2 2006.280.08:21:15.07#ibcon#*mode == 0, iclass 21, count 2 2006.280.08:21:15.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.280.08:21:15.07#ibcon#[27=AT04-04\r\n] 2006.280.08:21:15.07#ibcon#*before write, iclass 21, count 2 2006.280.08:21:15.07#ibcon#enter sib2, iclass 21, count 2 2006.280.08:21:15.07#ibcon#flushed, iclass 21, count 2 2006.280.08:21:15.07#ibcon#about to write, iclass 21, count 2 2006.280.08:21:15.07#ibcon#wrote, iclass 21, count 2 2006.280.08:21:15.07#ibcon#about to read 3, iclass 21, count 2 2006.280.08:21:15.10#ibcon#read 3, iclass 21, count 2 2006.280.08:21:15.10#ibcon#about to read 4, iclass 21, count 2 2006.280.08:21:15.10#ibcon#read 4, iclass 21, count 2 2006.280.08:21:15.10#ibcon#about to read 5, iclass 21, count 2 2006.280.08:21:15.10#ibcon#read 5, iclass 21, count 2 2006.280.08:21:15.10#ibcon#about to read 6, iclass 21, count 2 2006.280.08:21:15.10#ibcon#read 6, iclass 21, count 2 2006.280.08:21:15.10#ibcon#end of sib2, iclass 21, count 2 2006.280.08:21:15.10#ibcon#*after write, iclass 21, count 2 2006.280.08:21:15.10#ibcon#*before return 0, iclass 21, count 2 2006.280.08:21:15.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:15.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.280.08:21:15.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.280.08:21:15.10#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:15.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:15.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:15.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:15.22#ibcon#enter wrdev, iclass 21, count 0 2006.280.08:21:15.22#ibcon#first serial, iclass 21, count 0 2006.280.08:21:15.22#ibcon#enter sib2, iclass 21, count 0 2006.280.08:21:15.22#ibcon#flushed, iclass 21, count 0 2006.280.08:21:15.22#ibcon#about to write, iclass 21, count 0 2006.280.08:21:15.22#ibcon#wrote, iclass 21, count 0 2006.280.08:21:15.22#ibcon#about to read 3, iclass 21, count 0 2006.280.08:21:15.25#ibcon#read 3, iclass 21, count 0 2006.280.08:21:15.25#ibcon#about to read 4, iclass 21, count 0 2006.280.08:21:15.25#ibcon#read 4, iclass 21, count 0 2006.280.08:21:15.25#ibcon#about to read 5, iclass 21, count 0 2006.280.08:21:15.25#ibcon#read 5, iclass 21, count 0 2006.280.08:21:15.25#ibcon#about to read 6, iclass 21, count 0 2006.280.08:21:15.25#ibcon#read 6, iclass 21, count 0 2006.280.08:21:15.25#ibcon#end of sib2, iclass 21, count 0 2006.280.08:21:15.25#ibcon#*mode == 0, iclass 21, count 0 2006.280.08:21:15.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.280.08:21:15.25#ibcon#[27=USB\r\n] 2006.280.08:21:15.25#ibcon#*before write, iclass 21, count 0 2006.280.08:21:15.25#ibcon#enter sib2, iclass 21, count 0 2006.280.08:21:15.25#ibcon#flushed, iclass 21, count 0 2006.280.08:21:15.25#ibcon#about to write, iclass 21, count 0 2006.280.08:21:15.25#ibcon#wrote, iclass 21, count 0 2006.280.08:21:15.25#ibcon#about to read 3, iclass 21, count 0 2006.280.08:21:15.27#ibcon#read 3, iclass 21, count 0 2006.280.08:21:15.27#ibcon#about to read 4, iclass 21, count 0 2006.280.08:21:15.27#ibcon#read 4, iclass 21, count 0 2006.280.08:21:15.27#ibcon#about to read 5, iclass 21, count 0 2006.280.08:21:15.27#ibcon#read 5, iclass 21, count 0 2006.280.08:21:15.27#ibcon#about to read 6, iclass 21, count 0 2006.280.08:21:15.27#ibcon#read 6, iclass 21, count 0 2006.280.08:21:15.27#ibcon#end of sib2, iclass 21, count 0 2006.280.08:21:15.27#ibcon#*after write, iclass 21, count 0 2006.280.08:21:15.27#ibcon#*before return 0, iclass 21, count 0 2006.280.08:21:15.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:15.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.280.08:21:15.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.280.08:21:15.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.280.08:21:15.27$vc4f8/vblo=5,744.99 2006.280.08:21:15.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.280.08:21:15.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.280.08:21:15.27#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:15.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:15.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:15.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:15.27#ibcon#enter wrdev, iclass 23, count 0 2006.280.08:21:15.27#ibcon#first serial, iclass 23, count 0 2006.280.08:21:15.27#ibcon#enter sib2, iclass 23, count 0 2006.280.08:21:15.27#ibcon#flushed, iclass 23, count 0 2006.280.08:21:15.27#ibcon#about to write, iclass 23, count 0 2006.280.08:21:15.27#ibcon#wrote, iclass 23, count 0 2006.280.08:21:15.27#ibcon#about to read 3, iclass 23, count 0 2006.280.08:21:15.29#ibcon#read 3, iclass 23, count 0 2006.280.08:21:15.29#ibcon#about to read 4, iclass 23, count 0 2006.280.08:21:15.29#ibcon#read 4, iclass 23, count 0 2006.280.08:21:15.29#ibcon#about to read 5, iclass 23, count 0 2006.280.08:21:15.29#ibcon#read 5, iclass 23, count 0 2006.280.08:21:15.29#ibcon#about to read 6, iclass 23, count 0 2006.280.08:21:15.29#ibcon#read 6, iclass 23, count 0 2006.280.08:21:15.29#ibcon#end of sib2, iclass 23, count 0 2006.280.08:21:15.29#ibcon#*mode == 0, iclass 23, count 0 2006.280.08:21:15.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.280.08:21:15.29#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:21:15.29#ibcon#*before write, iclass 23, count 0 2006.280.08:21:15.29#ibcon#enter sib2, iclass 23, count 0 2006.280.08:21:15.29#ibcon#flushed, iclass 23, count 0 2006.280.08:21:15.29#ibcon#about to write, iclass 23, count 0 2006.280.08:21:15.29#ibcon#wrote, iclass 23, count 0 2006.280.08:21:15.29#ibcon#about to read 3, iclass 23, count 0 2006.280.08:21:15.33#ibcon#read 3, iclass 23, count 0 2006.280.08:21:15.33#ibcon#about to read 4, iclass 23, count 0 2006.280.08:21:15.33#ibcon#read 4, iclass 23, count 0 2006.280.08:21:15.33#ibcon#about to read 5, iclass 23, count 0 2006.280.08:21:15.33#ibcon#read 5, iclass 23, count 0 2006.280.08:21:15.33#ibcon#about to read 6, iclass 23, count 0 2006.280.08:21:15.33#ibcon#read 6, iclass 23, count 0 2006.280.08:21:15.33#ibcon#end of sib2, iclass 23, count 0 2006.280.08:21:15.33#ibcon#*after write, iclass 23, count 0 2006.280.08:21:15.33#ibcon#*before return 0, iclass 23, count 0 2006.280.08:21:15.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:15.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.280.08:21:15.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.280.08:21:15.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.280.08:21:15.33$vc4f8/vb=5,4 2006.280.08:21:15.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.280.08:21:15.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.280.08:21:15.33#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:15.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:15.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:15.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:15.39#ibcon#enter wrdev, iclass 25, count 2 2006.280.08:21:15.39#ibcon#first serial, iclass 25, count 2 2006.280.08:21:15.39#ibcon#enter sib2, iclass 25, count 2 2006.280.08:21:15.39#ibcon#flushed, iclass 25, count 2 2006.280.08:21:15.39#ibcon#about to write, iclass 25, count 2 2006.280.08:21:15.39#ibcon#wrote, iclass 25, count 2 2006.280.08:21:15.39#ibcon#about to read 3, iclass 25, count 2 2006.280.08:21:15.41#ibcon#read 3, iclass 25, count 2 2006.280.08:21:15.41#ibcon#about to read 4, iclass 25, count 2 2006.280.08:21:15.41#ibcon#read 4, iclass 25, count 2 2006.280.08:21:15.41#ibcon#about to read 5, iclass 25, count 2 2006.280.08:21:15.41#ibcon#read 5, iclass 25, count 2 2006.280.08:21:15.41#ibcon#about to read 6, iclass 25, count 2 2006.280.08:21:15.41#ibcon#read 6, iclass 25, count 2 2006.280.08:21:15.41#ibcon#end of sib2, iclass 25, count 2 2006.280.08:21:15.41#ibcon#*mode == 0, iclass 25, count 2 2006.280.08:21:15.41#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.280.08:21:15.41#ibcon#[27=AT05-04\r\n] 2006.280.08:21:15.41#ibcon#*before write, iclass 25, count 2 2006.280.08:21:15.41#ibcon#enter sib2, iclass 25, count 2 2006.280.08:21:15.41#ibcon#flushed, iclass 25, count 2 2006.280.08:21:15.41#ibcon#about to write, iclass 25, count 2 2006.280.08:21:15.41#ibcon#wrote, iclass 25, count 2 2006.280.08:21:15.41#ibcon#about to read 3, iclass 25, count 2 2006.280.08:21:15.44#ibcon#read 3, iclass 25, count 2 2006.280.08:21:15.44#ibcon#about to read 4, iclass 25, count 2 2006.280.08:21:15.44#ibcon#read 4, iclass 25, count 2 2006.280.08:21:15.44#ibcon#about to read 5, iclass 25, count 2 2006.280.08:21:15.44#ibcon#read 5, iclass 25, count 2 2006.280.08:21:15.44#ibcon#about to read 6, iclass 25, count 2 2006.280.08:21:15.44#ibcon#read 6, iclass 25, count 2 2006.280.08:21:15.44#ibcon#end of sib2, iclass 25, count 2 2006.280.08:21:15.44#ibcon#*after write, iclass 25, count 2 2006.280.08:21:15.44#ibcon#*before return 0, iclass 25, count 2 2006.280.08:21:15.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:15.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.280.08:21:15.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.280.08:21:15.44#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:15.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:15.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:15.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:15.56#ibcon#enter wrdev, iclass 25, count 0 2006.280.08:21:15.56#ibcon#first serial, iclass 25, count 0 2006.280.08:21:15.56#ibcon#enter sib2, iclass 25, count 0 2006.280.08:21:15.56#ibcon#flushed, iclass 25, count 0 2006.280.08:21:15.56#ibcon#about to write, iclass 25, count 0 2006.280.08:21:15.56#ibcon#wrote, iclass 25, count 0 2006.280.08:21:15.56#ibcon#about to read 3, iclass 25, count 0 2006.280.08:21:15.58#ibcon#read 3, iclass 25, count 0 2006.280.08:21:15.58#ibcon#about to read 4, iclass 25, count 0 2006.280.08:21:15.58#ibcon#read 4, iclass 25, count 0 2006.280.08:21:15.58#ibcon#about to read 5, iclass 25, count 0 2006.280.08:21:15.58#ibcon#read 5, iclass 25, count 0 2006.280.08:21:15.58#ibcon#about to read 6, iclass 25, count 0 2006.280.08:21:15.58#ibcon#read 6, iclass 25, count 0 2006.280.08:21:15.58#ibcon#end of sib2, iclass 25, count 0 2006.280.08:21:15.58#ibcon#*mode == 0, iclass 25, count 0 2006.280.08:21:15.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.280.08:21:15.58#ibcon#[27=USB\r\n] 2006.280.08:21:15.58#ibcon#*before write, iclass 25, count 0 2006.280.08:21:15.58#ibcon#enter sib2, iclass 25, count 0 2006.280.08:21:15.58#ibcon#flushed, iclass 25, count 0 2006.280.08:21:15.58#ibcon#about to write, iclass 25, count 0 2006.280.08:21:15.58#ibcon#wrote, iclass 25, count 0 2006.280.08:21:15.58#ibcon#about to read 3, iclass 25, count 0 2006.280.08:21:15.61#ibcon#read 3, iclass 25, count 0 2006.280.08:21:15.61#ibcon#about to read 4, iclass 25, count 0 2006.280.08:21:15.61#ibcon#read 4, iclass 25, count 0 2006.280.08:21:15.61#ibcon#about to read 5, iclass 25, count 0 2006.280.08:21:15.61#ibcon#read 5, iclass 25, count 0 2006.280.08:21:15.61#ibcon#about to read 6, iclass 25, count 0 2006.280.08:21:15.61#ibcon#read 6, iclass 25, count 0 2006.280.08:21:15.61#ibcon#end of sib2, iclass 25, count 0 2006.280.08:21:15.61#ibcon#*after write, iclass 25, count 0 2006.280.08:21:15.61#ibcon#*before return 0, iclass 25, count 0 2006.280.08:21:15.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:15.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.280.08:21:15.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.280.08:21:15.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.280.08:21:15.61$vc4f8/vblo=6,752.99 2006.280.08:21:15.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.280.08:21:15.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.280.08:21:15.61#ibcon#ireg 17 cls_cnt 0 2006.280.08:21:15.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:15.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:15.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:15.61#ibcon#enter wrdev, iclass 27, count 0 2006.280.08:21:15.61#ibcon#first serial, iclass 27, count 0 2006.280.08:21:15.61#ibcon#enter sib2, iclass 27, count 0 2006.280.08:21:15.61#ibcon#flushed, iclass 27, count 0 2006.280.08:21:15.61#ibcon#about to write, iclass 27, count 0 2006.280.08:21:15.61#ibcon#wrote, iclass 27, count 0 2006.280.08:21:15.61#ibcon#about to read 3, iclass 27, count 0 2006.280.08:21:15.63#ibcon#read 3, iclass 27, count 0 2006.280.08:21:15.63#ibcon#about to read 4, iclass 27, count 0 2006.280.08:21:15.63#ibcon#read 4, iclass 27, count 0 2006.280.08:21:15.63#ibcon#about to read 5, iclass 27, count 0 2006.280.08:21:15.63#ibcon#read 5, iclass 27, count 0 2006.280.08:21:15.63#ibcon#about to read 6, iclass 27, count 0 2006.280.08:21:15.63#ibcon#read 6, iclass 27, count 0 2006.280.08:21:15.63#ibcon#end of sib2, iclass 27, count 0 2006.280.08:21:15.63#ibcon#*mode == 0, iclass 27, count 0 2006.280.08:21:15.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.280.08:21:15.63#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:21:15.63#ibcon#*before write, iclass 27, count 0 2006.280.08:21:15.63#ibcon#enter sib2, iclass 27, count 0 2006.280.08:21:15.63#ibcon#flushed, iclass 27, count 0 2006.280.08:21:15.63#ibcon#about to write, iclass 27, count 0 2006.280.08:21:15.63#ibcon#wrote, iclass 27, count 0 2006.280.08:21:15.63#ibcon#about to read 3, iclass 27, count 0 2006.280.08:21:15.67#ibcon#read 3, iclass 27, count 0 2006.280.08:21:15.67#ibcon#about to read 4, iclass 27, count 0 2006.280.08:21:15.67#ibcon#read 4, iclass 27, count 0 2006.280.08:21:15.67#ibcon#about to read 5, iclass 27, count 0 2006.280.08:21:15.67#ibcon#read 5, iclass 27, count 0 2006.280.08:21:15.67#ibcon#about to read 6, iclass 27, count 0 2006.280.08:21:15.67#ibcon#read 6, iclass 27, count 0 2006.280.08:21:15.67#ibcon#end of sib2, iclass 27, count 0 2006.280.08:21:15.67#ibcon#*after write, iclass 27, count 0 2006.280.08:21:15.67#ibcon#*before return 0, iclass 27, count 0 2006.280.08:21:15.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:15.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.280.08:21:15.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.280.08:21:15.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.280.08:21:15.67$vc4f8/vb=6,4 2006.280.08:21:15.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.280.08:21:15.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.280.08:21:15.67#ibcon#ireg 11 cls_cnt 2 2006.280.08:21:15.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:21:15.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:21:15.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:21:15.73#ibcon#enter wrdev, iclass 29, count 2 2006.280.08:21:15.73#ibcon#first serial, iclass 29, count 2 2006.280.08:21:15.73#ibcon#enter sib2, iclass 29, count 2 2006.280.08:21:15.73#ibcon#flushed, iclass 29, count 2 2006.280.08:21:15.73#ibcon#about to write, iclass 29, count 2 2006.280.08:21:15.73#ibcon#wrote, iclass 29, count 2 2006.280.08:21:15.73#ibcon#about to read 3, iclass 29, count 2 2006.280.08:21:15.76#ibcon#read 3, iclass 29, count 2 2006.280.08:21:15.76#ibcon#about to read 4, iclass 29, count 2 2006.280.08:21:15.76#ibcon#read 4, iclass 29, count 2 2006.280.08:21:15.76#ibcon#about to read 5, iclass 29, count 2 2006.280.08:21:15.76#ibcon#read 5, iclass 29, count 2 2006.280.08:21:15.76#ibcon#about to read 6, iclass 29, count 2 2006.280.08:21:15.76#ibcon#read 6, iclass 29, count 2 2006.280.08:21:15.76#ibcon#end of sib2, iclass 29, count 2 2006.280.08:21:15.76#ibcon#*mode == 0, iclass 29, count 2 2006.280.08:21:15.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.280.08:21:15.76#ibcon#[27=AT06-04\r\n] 2006.280.08:21:15.76#ibcon#*before write, iclass 29, count 2 2006.280.08:21:15.76#ibcon#enter sib2, iclass 29, count 2 2006.280.08:21:15.76#ibcon#flushed, iclass 29, count 2 2006.280.08:21:15.76#ibcon#about to write, iclass 29, count 2 2006.280.08:21:15.76#ibcon#wrote, iclass 29, count 2 2006.280.08:21:15.76#ibcon#about to read 3, iclass 29, count 2 2006.280.08:21:15.79#ibcon#read 3, iclass 29, count 2 2006.280.08:21:15.79#ibcon#about to read 4, iclass 29, count 2 2006.280.08:21:15.79#ibcon#read 4, iclass 29, count 2 2006.280.08:21:15.79#ibcon#about to read 5, iclass 29, count 2 2006.280.08:21:15.79#ibcon#read 5, iclass 29, count 2 2006.280.08:21:15.79#ibcon#about to read 6, iclass 29, count 2 2006.280.08:21:15.79#ibcon#read 6, iclass 29, count 2 2006.280.08:21:15.79#ibcon#end of sib2, iclass 29, count 2 2006.280.08:21:15.79#ibcon#*after write, iclass 29, count 2 2006.280.08:21:15.79#ibcon#*before return 0, iclass 29, count 2 2006.280.08:21:15.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:21:15.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.280.08:21:15.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.280.08:21:15.79#ibcon#ireg 7 cls_cnt 0 2006.280.08:21:15.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:21:15.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:21:15.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:21:15.91#ibcon#enter wrdev, iclass 29, count 0 2006.280.08:21:15.91#ibcon#first serial, iclass 29, count 0 2006.280.08:21:15.91#ibcon#enter sib2, iclass 29, count 0 2006.280.08:21:15.91#ibcon#flushed, iclass 29, count 0 2006.280.08:21:15.91#ibcon#about to write, iclass 29, count 0 2006.280.08:21:15.91#ibcon#wrote, iclass 29, count 0 2006.280.08:21:15.91#ibcon#about to read 3, iclass 29, count 0 2006.280.08:21:15.93#ibcon#read 3, iclass 29, count 0 2006.280.08:21:15.93#ibcon#about to read 4, iclass 29, count 0 2006.280.08:21:15.93#ibcon#read 4, iclass 29, count 0 2006.280.08:21:15.93#ibcon#about to read 5, iclass 29, count 0 2006.280.08:21:15.93#ibcon#read 5, iclass 29, count 0 2006.280.08:21:15.93#ibcon#about to read 6, iclass 29, count 0 2006.280.08:21:15.93#ibcon#read 6, iclass 29, count 0 2006.280.08:21:15.93#ibcon#end of sib2, iclass 29, count 0 2006.280.08:21:15.93#ibcon#*mode == 0, iclass 29, count 0 2006.280.08:21:15.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.280.08:21:15.93#ibcon#[27=USB\r\n] 2006.280.08:21:15.93#ibcon#*before write, iclass 29, count 0 2006.280.08:21:15.93#ibcon#enter sib2, iclass 29, count 0 2006.280.08:21:15.93#ibcon#flushed, iclass 29, count 0 2006.280.08:21:15.93#ibcon#about to write, iclass 29, count 0 2006.280.08:21:15.93#ibcon#wrote, iclass 29, count 0 2006.280.08:21:15.93#ibcon#about to read 3, iclass 29, count 0 2006.280.08:21:15.96#ibcon#read 3, iclass 29, count 0 2006.280.08:21:15.96#ibcon#about to read 4, iclass 29, count 0 2006.280.08:21:15.96#ibcon#read 4, iclass 29, count 0 2006.280.08:21:15.96#ibcon#about to read 5, iclass 29, count 0 2006.280.08:21:15.96#ibcon#read 5, iclass 29, count 0 2006.280.08:21:15.96#ibcon#about to read 6, iclass 29, count 0 2006.280.08:21:15.96#ibcon#read 6, iclass 29, count 0 2006.280.08:21:15.96#ibcon#end of sib2, iclass 29, count 0 2006.280.08:21:15.96#ibcon#*after write, iclass 29, count 0 2006.280.08:21:15.96#ibcon#*before return 0, iclass 29, count 0 2006.280.08:21:15.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:21:15.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.280.08:21:15.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.280.08:21:15.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.280.08:21:15.96$vc4f8/vabw=wide 2006.280.08:21:15.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.280.08:21:15.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.280.08:21:15.96#ibcon#ireg 8 cls_cnt 0 2006.280.08:21:15.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:21:15.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:21:15.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:21:15.96#ibcon#enter wrdev, iclass 31, count 0 2006.280.08:21:15.96#ibcon#first serial, iclass 31, count 0 2006.280.08:21:15.96#ibcon#enter sib2, iclass 31, count 0 2006.280.08:21:15.96#ibcon#flushed, iclass 31, count 0 2006.280.08:21:15.96#ibcon#about to write, iclass 31, count 0 2006.280.08:21:15.96#ibcon#wrote, iclass 31, count 0 2006.280.08:21:15.96#ibcon#about to read 3, iclass 31, count 0 2006.280.08:21:15.98#ibcon#read 3, iclass 31, count 0 2006.280.08:21:15.98#ibcon#about to read 4, iclass 31, count 0 2006.280.08:21:15.98#ibcon#read 4, iclass 31, count 0 2006.280.08:21:15.98#ibcon#about to read 5, iclass 31, count 0 2006.280.08:21:15.98#ibcon#read 5, iclass 31, count 0 2006.280.08:21:15.98#ibcon#about to read 6, iclass 31, count 0 2006.280.08:21:15.98#ibcon#read 6, iclass 31, count 0 2006.280.08:21:15.98#ibcon#end of sib2, iclass 31, count 0 2006.280.08:21:15.98#ibcon#*mode == 0, iclass 31, count 0 2006.280.08:21:15.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.280.08:21:15.98#ibcon#[25=BW32\r\n] 2006.280.08:21:15.98#ibcon#*before write, iclass 31, count 0 2006.280.08:21:15.98#ibcon#enter sib2, iclass 31, count 0 2006.280.08:21:15.98#ibcon#flushed, iclass 31, count 0 2006.280.08:21:15.98#ibcon#about to write, iclass 31, count 0 2006.280.08:21:15.98#ibcon#wrote, iclass 31, count 0 2006.280.08:21:15.98#ibcon#about to read 3, iclass 31, count 0 2006.280.08:21:16.01#ibcon#read 3, iclass 31, count 0 2006.280.08:21:16.01#ibcon#about to read 4, iclass 31, count 0 2006.280.08:21:16.01#ibcon#read 4, iclass 31, count 0 2006.280.08:21:16.01#ibcon#about to read 5, iclass 31, count 0 2006.280.08:21:16.01#ibcon#read 5, iclass 31, count 0 2006.280.08:21:16.01#ibcon#about to read 6, iclass 31, count 0 2006.280.08:21:16.01#ibcon#read 6, iclass 31, count 0 2006.280.08:21:16.01#ibcon#end of sib2, iclass 31, count 0 2006.280.08:21:16.01#ibcon#*after write, iclass 31, count 0 2006.280.08:21:16.01#ibcon#*before return 0, iclass 31, count 0 2006.280.08:21:16.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:21:16.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.280.08:21:16.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.280.08:21:16.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.280.08:21:16.01$vc4f8/vbbw=wide 2006.280.08:21:16.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.280.08:21:16.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.280.08:21:16.01#ibcon#ireg 8 cls_cnt 0 2006.280.08:21:16.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:21:16.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:21:16.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:21:16.08#ibcon#enter wrdev, iclass 33, count 0 2006.280.08:21:16.08#ibcon#first serial, iclass 33, count 0 2006.280.08:21:16.08#ibcon#enter sib2, iclass 33, count 0 2006.280.08:21:16.08#ibcon#flushed, iclass 33, count 0 2006.280.08:21:16.08#ibcon#about to write, iclass 33, count 0 2006.280.08:21:16.08#ibcon#wrote, iclass 33, count 0 2006.280.08:21:16.08#ibcon#about to read 3, iclass 33, count 0 2006.280.08:21:16.10#ibcon#read 3, iclass 33, count 0 2006.280.08:21:16.10#ibcon#about to read 4, iclass 33, count 0 2006.280.08:21:16.10#ibcon#read 4, iclass 33, count 0 2006.280.08:21:16.10#ibcon#about to read 5, iclass 33, count 0 2006.280.08:21:16.10#ibcon#read 5, iclass 33, count 0 2006.280.08:21:16.10#ibcon#about to read 6, iclass 33, count 0 2006.280.08:21:16.10#ibcon#read 6, iclass 33, count 0 2006.280.08:21:16.10#ibcon#end of sib2, iclass 33, count 0 2006.280.08:21:16.10#ibcon#*mode == 0, iclass 33, count 0 2006.280.08:21:16.10#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.280.08:21:16.10#ibcon#[27=BW32\r\n] 2006.280.08:21:16.10#ibcon#*before write, iclass 33, count 0 2006.280.08:21:16.10#ibcon#enter sib2, iclass 33, count 0 2006.280.08:21:16.10#ibcon#flushed, iclass 33, count 0 2006.280.08:21:16.10#ibcon#about to write, iclass 33, count 0 2006.280.08:21:16.10#ibcon#wrote, iclass 33, count 0 2006.280.08:21:16.10#ibcon#about to read 3, iclass 33, count 0 2006.280.08:21:16.13#ibcon#read 3, iclass 33, count 0 2006.280.08:21:16.13#ibcon#about to read 4, iclass 33, count 0 2006.280.08:21:16.13#ibcon#read 4, iclass 33, count 0 2006.280.08:21:16.13#ibcon#about to read 5, iclass 33, count 0 2006.280.08:21:16.13#ibcon#read 5, iclass 33, count 0 2006.280.08:21:16.13#ibcon#about to read 6, iclass 33, count 0 2006.280.08:21:16.13#ibcon#read 6, iclass 33, count 0 2006.280.08:21:16.13#ibcon#end of sib2, iclass 33, count 0 2006.280.08:21:16.13#ibcon#*after write, iclass 33, count 0 2006.280.08:21:16.13#ibcon#*before return 0, iclass 33, count 0 2006.280.08:21:16.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:21:16.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.280.08:21:16.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.280.08:21:16.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.280.08:21:16.13$4f8m12a/ifd4f 2006.280.08:21:16.13$ifd4f/lo= 2006.280.08:21:16.13$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:21:16.13$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:21:16.13$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:21:16.13$ifd4f/patch= 2006.280.08:21:16.13$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:21:16.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:21:16.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:21:16.14$4f8m12a/"form=m,16.000,1:2 2006.280.08:21:16.14$4f8m12a/"tpicd 2006.280.08:21:16.14$4f8m12a/echo=off 2006.280.08:21:16.14$4f8m12a/xlog=off 2006.280.08:21:16.14:!2006.280.08:23:20 2006.280.08:21:55.14#trakl#Source acquired 2006.280.08:21:55.14#flagr#flagr/antenna,acquired 2006.280.08:23:20.01:preob 2006.280.08:23:21.14/onsource/TRACKING 2006.280.08:23:21.14:!2006.280.08:23:30 2006.280.08:23:30.00:data_valid=on 2006.280.08:23:30.00:midob 2006.280.08:23:30.14/onsource/TRACKING 2006.280.08:23:30.14/wx/20.22,987.6,63 2006.280.08:23:30.26/cable/+6.4842E-03 2006.280.08:23:31.35/va/01,07,usb,yes,33,35 2006.280.08:23:31.35/va/02,06,usb,yes,31,32 2006.280.08:23:31.35/va/03,06,usb,yes,29,29 2006.280.08:23:31.35/va/04,06,usb,yes,32,34 2006.280.08:23:31.35/va/05,07,usb,yes,31,32 2006.280.08:23:31.35/va/06,06,usb,yes,30,29 2006.280.08:23:31.35/va/07,06,usb,yes,30,30 2006.280.08:23:31.35/va/08,06,usb,yes,32,32 2006.280.08:23:31.58/valo/01,532.99,yes,locked 2006.280.08:23:31.58/valo/02,572.99,yes,locked 2006.280.08:23:31.58/valo/03,672.99,yes,locked 2006.280.08:23:31.58/valo/04,832.99,yes,locked 2006.280.08:23:31.58/valo/05,652.99,yes,locked 2006.280.08:23:31.58/valo/06,772.99,yes,locked 2006.280.08:23:31.58/valo/07,832.99,yes,locked 2006.280.08:23:31.58/valo/08,852.99,yes,locked 2006.280.08:23:32.67/vb/01,04,usb,yes,30,29 2006.280.08:23:32.67/vb/02,05,usb,yes,28,30 2006.280.08:23:32.67/vb/03,04,usb,yes,29,32 2006.280.08:23:32.67/vb/04,04,usb,yes,29,30 2006.280.08:23:32.67/vb/05,04,usb,yes,27,32 2006.280.08:23:32.67/vb/06,04,usb,yes,28,31 2006.280.08:23:32.67/vb/07,04,usb,yes,31,31 2006.280.08:23:32.67/vb/08,04,usb,yes,28,32 2006.280.08:23:32.90/vblo/01,632.99,yes,locked 2006.280.08:23:32.90/vblo/02,640.99,yes,locked 2006.280.08:23:32.90/vblo/03,656.99,yes,locked 2006.280.08:23:32.90/vblo/04,712.99,yes,locked 2006.280.08:23:32.90/vblo/05,744.99,yes,locked 2006.280.08:23:32.90/vblo/06,752.99,yes,locked 2006.280.08:23:32.90/vblo/07,734.99,yes,locked 2006.280.08:23:32.90/vblo/08,744.99,yes,locked 2006.280.08:23:33.05/vabw/8 2006.280.08:23:33.20/vbbw/8 2006.280.08:23:33.29/xfe/off,on,12.2 2006.280.08:23:33.68/ifatt/23,28,28,28 2006.280.08:23:34.07/fmout-gps/S +3.13E-07 2006.280.08:23:34.10:!2006.280.08:24:30 2006.280.08:24:30.01:data_valid=off 2006.280.08:24:30.02:postob 2006.280.08:24:30.08/cable/+6.4844E-03 2006.280.08:24:30.09/wx/20.20,987.6,62 2006.280.08:24:31.07/fmout-gps/S +3.12E-07 2006.280.08:24:31.08:scan_name=280-0825,k06280,60 2006.280.08:24:31.08:source=0133+476,013658.59,475129.1,2000.0,cw 2006.280.08:24:32.14#flagr#flagr/antenna,new-source 2006.280.08:24:32.15:checkk5 2006.280.08:24:32.57/chk_autoobs//k5ts1/ autoobs is running! 2006.280.08:24:33.34/chk_autoobs//k5ts2/ autoobs is running! 2006.280.08:24:33.97/chk_autoobs//k5ts3/ autoobs is running! 2006.280.08:24:34.50/chk_autoobs//k5ts4/ autoobs is running! 2006.280.08:24:35.31/chk_obsdata//k5ts1/T2800823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:24:35.75/chk_obsdata//k5ts2/T2800823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:24:36.34/chk_obsdata//k5ts3/T2800823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:24:37.01/chk_obsdata//k5ts4/T2800823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:24:37.86/k5log//k5ts1_log_newline 2006.280.08:24:39.10/k5log//k5ts2_log_newline 2006.280.08:24:40.26/k5log//k5ts3_log_newline 2006.280.08:24:41.11/k5log//k5ts4_log_newline 2006.280.08:24:41.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:24:41.14:4f8m12a=3 2006.280.08:24:41.14$4f8m12a/echo=on 2006.280.08:24:41.14$4f8m12a/pcalon 2006.280.08:24:41.14$pcalon/"no phase cal control is implemented here 2006.280.08:24:41.14$4f8m12a/"tpicd=stop 2006.280.08:24:41.14$4f8m12a/vc4f8 2006.280.08:24:41.14$vc4f8/valo=1,532.99 2006.280.08:24:41.14#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:24:41.14#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:24:41.14#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:41.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:41.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:41.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:41.14#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:24:41.14#ibcon#first serial, iclass 6, count 0 2006.280.08:24:41.14#ibcon#enter sib2, iclass 6, count 0 2006.280.08:24:41.14#ibcon#flushed, iclass 6, count 0 2006.280.08:24:41.15#ibcon#about to write, iclass 6, count 0 2006.280.08:24:41.15#ibcon#wrote, iclass 6, count 0 2006.280.08:24:41.15#ibcon#about to read 3, iclass 6, count 0 2006.280.08:24:41.16#ibcon#read 3, iclass 6, count 0 2006.280.08:24:41.16#ibcon#about to read 4, iclass 6, count 0 2006.280.08:24:41.16#ibcon#read 4, iclass 6, count 0 2006.280.08:24:41.16#ibcon#about to read 5, iclass 6, count 0 2006.280.08:24:41.16#ibcon#read 5, iclass 6, count 0 2006.280.08:24:41.16#ibcon#about to read 6, iclass 6, count 0 2006.280.08:24:41.16#ibcon#read 6, iclass 6, count 0 2006.280.08:24:41.16#ibcon#end of sib2, iclass 6, count 0 2006.280.08:24:41.16#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:24:41.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:24:41.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.280.08:24:41.16#ibcon#*before write, iclass 6, count 0 2006.280.08:24:41.16#ibcon#enter sib2, iclass 6, count 0 2006.280.08:24:41.16#ibcon#flushed, iclass 6, count 0 2006.280.08:24:41.16#ibcon#about to write, iclass 6, count 0 2006.280.08:24:41.16#ibcon#wrote, iclass 6, count 0 2006.280.08:24:41.16#ibcon#about to read 3, iclass 6, count 0 2006.280.08:24:41.22#ibcon#read 3, iclass 6, count 0 2006.280.08:24:41.22#ibcon#about to read 4, iclass 6, count 0 2006.280.08:24:41.22#ibcon#read 4, iclass 6, count 0 2006.280.08:24:41.22#ibcon#about to read 5, iclass 6, count 0 2006.280.08:24:41.22#ibcon#read 5, iclass 6, count 0 2006.280.08:24:41.22#ibcon#about to read 6, iclass 6, count 0 2006.280.08:24:41.22#ibcon#read 6, iclass 6, count 0 2006.280.08:24:41.22#ibcon#end of sib2, iclass 6, count 0 2006.280.08:24:41.22#ibcon#*after write, iclass 6, count 0 2006.280.08:24:41.22#ibcon#*before return 0, iclass 6, count 0 2006.280.08:24:41.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:41.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:41.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:24:41.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:24:41.22$vc4f8/va=1,7 2006.280.08:24:41.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.08:24:41.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.08:24:41.22#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:41.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:41.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:41.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:41.23#ibcon#enter wrdev, iclass 10, count 2 2006.280.08:24:41.23#ibcon#first serial, iclass 10, count 2 2006.280.08:24:41.23#ibcon#enter sib2, iclass 10, count 2 2006.280.08:24:41.23#ibcon#flushed, iclass 10, count 2 2006.280.08:24:41.23#ibcon#about to write, iclass 10, count 2 2006.280.08:24:41.23#ibcon#wrote, iclass 10, count 2 2006.280.08:24:41.23#ibcon#about to read 3, iclass 10, count 2 2006.280.08:24:41.24#ibcon#read 3, iclass 10, count 2 2006.280.08:24:41.24#ibcon#about to read 4, iclass 10, count 2 2006.280.08:24:41.24#ibcon#read 4, iclass 10, count 2 2006.280.08:24:41.24#ibcon#about to read 5, iclass 10, count 2 2006.280.08:24:41.24#ibcon#read 5, iclass 10, count 2 2006.280.08:24:41.24#ibcon#about to read 6, iclass 10, count 2 2006.280.08:24:41.24#ibcon#read 6, iclass 10, count 2 2006.280.08:24:41.24#ibcon#end of sib2, iclass 10, count 2 2006.280.08:24:41.24#ibcon#*mode == 0, iclass 10, count 2 2006.280.08:24:41.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.08:24:41.24#ibcon#[25=AT01-07\r\n] 2006.280.08:24:41.24#ibcon#*before write, iclass 10, count 2 2006.280.08:24:41.24#ibcon#enter sib2, iclass 10, count 2 2006.280.08:24:41.24#ibcon#flushed, iclass 10, count 2 2006.280.08:24:41.24#ibcon#about to write, iclass 10, count 2 2006.280.08:24:41.24#ibcon#wrote, iclass 10, count 2 2006.280.08:24:41.24#ibcon#about to read 3, iclass 10, count 2 2006.280.08:24:41.27#ibcon#read 3, iclass 10, count 2 2006.280.08:24:41.27#ibcon#about to read 4, iclass 10, count 2 2006.280.08:24:41.27#ibcon#read 4, iclass 10, count 2 2006.280.08:24:41.27#ibcon#about to read 5, iclass 10, count 2 2006.280.08:24:41.27#ibcon#read 5, iclass 10, count 2 2006.280.08:24:41.27#ibcon#about to read 6, iclass 10, count 2 2006.280.08:24:41.27#ibcon#read 6, iclass 10, count 2 2006.280.08:24:41.27#ibcon#end of sib2, iclass 10, count 2 2006.280.08:24:41.27#ibcon#*after write, iclass 10, count 2 2006.280.08:24:41.27#ibcon#*before return 0, iclass 10, count 2 2006.280.08:24:41.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:41.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:41.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.08:24:41.27#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:41.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:41.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:41.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:41.39#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:24:41.39#ibcon#first serial, iclass 10, count 0 2006.280.08:24:41.39#ibcon#enter sib2, iclass 10, count 0 2006.280.08:24:41.39#ibcon#flushed, iclass 10, count 0 2006.280.08:24:41.39#ibcon#about to write, iclass 10, count 0 2006.280.08:24:41.39#ibcon#wrote, iclass 10, count 0 2006.280.08:24:41.39#ibcon#about to read 3, iclass 10, count 0 2006.280.08:24:41.41#ibcon#read 3, iclass 10, count 0 2006.280.08:24:41.41#ibcon#about to read 4, iclass 10, count 0 2006.280.08:24:41.41#ibcon#read 4, iclass 10, count 0 2006.280.08:24:41.41#ibcon#about to read 5, iclass 10, count 0 2006.280.08:24:41.41#ibcon#read 5, iclass 10, count 0 2006.280.08:24:41.41#ibcon#about to read 6, iclass 10, count 0 2006.280.08:24:41.41#ibcon#read 6, iclass 10, count 0 2006.280.08:24:41.41#ibcon#end of sib2, iclass 10, count 0 2006.280.08:24:41.41#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:24:41.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:24:41.41#ibcon#[25=USB\r\n] 2006.280.08:24:41.41#ibcon#*before write, iclass 10, count 0 2006.280.08:24:41.41#ibcon#enter sib2, iclass 10, count 0 2006.280.08:24:41.41#ibcon#flushed, iclass 10, count 0 2006.280.08:24:41.41#ibcon#about to write, iclass 10, count 0 2006.280.08:24:41.41#ibcon#wrote, iclass 10, count 0 2006.280.08:24:41.41#ibcon#about to read 3, iclass 10, count 0 2006.280.08:24:41.44#ibcon#read 3, iclass 10, count 0 2006.280.08:24:41.44#ibcon#about to read 4, iclass 10, count 0 2006.280.08:24:41.44#ibcon#read 4, iclass 10, count 0 2006.280.08:24:41.44#ibcon#about to read 5, iclass 10, count 0 2006.280.08:24:41.44#ibcon#read 5, iclass 10, count 0 2006.280.08:24:41.44#ibcon#about to read 6, iclass 10, count 0 2006.280.08:24:41.44#ibcon#read 6, iclass 10, count 0 2006.280.08:24:41.44#ibcon#end of sib2, iclass 10, count 0 2006.280.08:24:41.44#ibcon#*after write, iclass 10, count 0 2006.280.08:24:41.44#ibcon#*before return 0, iclass 10, count 0 2006.280.08:24:41.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:41.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:41.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:24:41.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:24:41.44$vc4f8/valo=2,572.99 2006.280.08:24:41.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:24:41.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:24:41.44#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:41.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:41.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:41.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:41.44#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:24:41.44#ibcon#first serial, iclass 12, count 0 2006.280.08:24:41.44#ibcon#enter sib2, iclass 12, count 0 2006.280.08:24:41.44#ibcon#flushed, iclass 12, count 0 2006.280.08:24:41.44#ibcon#about to write, iclass 12, count 0 2006.280.08:24:41.44#ibcon#wrote, iclass 12, count 0 2006.280.08:24:41.44#ibcon#about to read 3, iclass 12, count 0 2006.280.08:24:41.46#ibcon#read 3, iclass 12, count 0 2006.280.08:24:41.46#ibcon#about to read 4, iclass 12, count 0 2006.280.08:24:41.46#ibcon#read 4, iclass 12, count 0 2006.280.08:24:41.46#ibcon#about to read 5, iclass 12, count 0 2006.280.08:24:41.46#ibcon#read 5, iclass 12, count 0 2006.280.08:24:41.46#ibcon#about to read 6, iclass 12, count 0 2006.280.08:24:41.46#ibcon#read 6, iclass 12, count 0 2006.280.08:24:41.46#ibcon#end of sib2, iclass 12, count 0 2006.280.08:24:41.46#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:24:41.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:24:41.46#ibcon#[26=FRQ=02,572.99\r\n] 2006.280.08:24:41.46#ibcon#*before write, iclass 12, count 0 2006.280.08:24:41.46#ibcon#enter sib2, iclass 12, count 0 2006.280.08:24:41.46#ibcon#flushed, iclass 12, count 0 2006.280.08:24:41.46#ibcon#about to write, iclass 12, count 0 2006.280.08:24:41.46#ibcon#wrote, iclass 12, count 0 2006.280.08:24:41.46#ibcon#about to read 3, iclass 12, count 0 2006.280.08:24:41.50#ibcon#read 3, iclass 12, count 0 2006.280.08:24:41.50#ibcon#about to read 4, iclass 12, count 0 2006.280.08:24:41.50#ibcon#read 4, iclass 12, count 0 2006.280.08:24:41.50#ibcon#about to read 5, iclass 12, count 0 2006.280.08:24:41.50#ibcon#read 5, iclass 12, count 0 2006.280.08:24:41.50#ibcon#about to read 6, iclass 12, count 0 2006.280.08:24:41.50#ibcon#read 6, iclass 12, count 0 2006.280.08:24:41.50#ibcon#end of sib2, iclass 12, count 0 2006.280.08:24:41.50#ibcon#*after write, iclass 12, count 0 2006.280.08:24:41.50#ibcon#*before return 0, iclass 12, count 0 2006.280.08:24:41.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:41.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:41.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:24:41.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:24:41.50$vc4f8/va=2,6 2006.280.08:24:41.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:24:41.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:24:41.50#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:41.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:41.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:41.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:41.56#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:24:41.56#ibcon#first serial, iclass 14, count 2 2006.280.08:24:41.56#ibcon#enter sib2, iclass 14, count 2 2006.280.08:24:41.56#ibcon#flushed, iclass 14, count 2 2006.280.08:24:41.56#ibcon#about to write, iclass 14, count 2 2006.280.08:24:41.56#ibcon#wrote, iclass 14, count 2 2006.280.08:24:41.56#ibcon#about to read 3, iclass 14, count 2 2006.280.08:24:41.58#ibcon#read 3, iclass 14, count 2 2006.280.08:24:41.58#ibcon#about to read 4, iclass 14, count 2 2006.280.08:24:41.58#ibcon#read 4, iclass 14, count 2 2006.280.08:24:41.58#ibcon#about to read 5, iclass 14, count 2 2006.280.08:24:41.58#ibcon#read 5, iclass 14, count 2 2006.280.08:24:41.58#ibcon#about to read 6, iclass 14, count 2 2006.280.08:24:41.58#ibcon#read 6, iclass 14, count 2 2006.280.08:24:41.58#ibcon#end of sib2, iclass 14, count 2 2006.280.08:24:41.58#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:24:41.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:24:41.58#ibcon#[25=AT02-06\r\n] 2006.280.08:24:41.58#ibcon#*before write, iclass 14, count 2 2006.280.08:24:41.58#ibcon#enter sib2, iclass 14, count 2 2006.280.08:24:41.58#ibcon#flushed, iclass 14, count 2 2006.280.08:24:41.58#ibcon#about to write, iclass 14, count 2 2006.280.08:24:41.58#ibcon#wrote, iclass 14, count 2 2006.280.08:24:41.58#ibcon#about to read 3, iclass 14, count 2 2006.280.08:24:41.61#ibcon#read 3, iclass 14, count 2 2006.280.08:24:41.61#ibcon#about to read 4, iclass 14, count 2 2006.280.08:24:41.61#ibcon#read 4, iclass 14, count 2 2006.280.08:24:41.61#ibcon#about to read 5, iclass 14, count 2 2006.280.08:24:41.61#ibcon#read 5, iclass 14, count 2 2006.280.08:24:41.61#ibcon#about to read 6, iclass 14, count 2 2006.280.08:24:41.61#ibcon#read 6, iclass 14, count 2 2006.280.08:24:41.61#ibcon#end of sib2, iclass 14, count 2 2006.280.08:24:41.61#ibcon#*after write, iclass 14, count 2 2006.280.08:24:41.61#ibcon#*before return 0, iclass 14, count 2 2006.280.08:24:41.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:41.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:41.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:24:41.61#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:41.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:41.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:41.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:41.73#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:24:41.73#ibcon#first serial, iclass 14, count 0 2006.280.08:24:41.73#ibcon#enter sib2, iclass 14, count 0 2006.280.08:24:41.73#ibcon#flushed, iclass 14, count 0 2006.280.08:24:41.73#ibcon#about to write, iclass 14, count 0 2006.280.08:24:41.73#ibcon#wrote, iclass 14, count 0 2006.280.08:24:41.73#ibcon#about to read 3, iclass 14, count 0 2006.280.08:24:41.75#ibcon#read 3, iclass 14, count 0 2006.280.08:24:41.75#ibcon#about to read 4, iclass 14, count 0 2006.280.08:24:41.75#ibcon#read 4, iclass 14, count 0 2006.280.08:24:41.75#ibcon#about to read 5, iclass 14, count 0 2006.280.08:24:41.75#ibcon#read 5, iclass 14, count 0 2006.280.08:24:41.75#ibcon#about to read 6, iclass 14, count 0 2006.280.08:24:41.75#ibcon#read 6, iclass 14, count 0 2006.280.08:24:41.75#ibcon#end of sib2, iclass 14, count 0 2006.280.08:24:41.75#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:24:41.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:24:41.75#ibcon#[25=USB\r\n] 2006.280.08:24:41.75#ibcon#*before write, iclass 14, count 0 2006.280.08:24:41.75#ibcon#enter sib2, iclass 14, count 0 2006.280.08:24:41.75#ibcon#flushed, iclass 14, count 0 2006.280.08:24:41.75#ibcon#about to write, iclass 14, count 0 2006.280.08:24:41.75#ibcon#wrote, iclass 14, count 0 2006.280.08:24:41.75#ibcon#about to read 3, iclass 14, count 0 2006.280.08:24:41.78#ibcon#read 3, iclass 14, count 0 2006.280.08:24:41.78#ibcon#about to read 4, iclass 14, count 0 2006.280.08:24:41.78#ibcon#read 4, iclass 14, count 0 2006.280.08:24:41.78#ibcon#about to read 5, iclass 14, count 0 2006.280.08:24:41.78#ibcon#read 5, iclass 14, count 0 2006.280.08:24:41.78#ibcon#about to read 6, iclass 14, count 0 2006.280.08:24:41.78#ibcon#read 6, iclass 14, count 0 2006.280.08:24:41.78#ibcon#end of sib2, iclass 14, count 0 2006.280.08:24:41.78#ibcon#*after write, iclass 14, count 0 2006.280.08:24:41.78#ibcon#*before return 0, iclass 14, count 0 2006.280.08:24:41.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:41.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:41.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:24:41.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:24:41.78$vc4f8/valo=3,672.99 2006.280.08:24:41.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:24:41.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:24:41.78#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:41.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:41.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:41.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:41.78#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:24:41.78#ibcon#first serial, iclass 16, count 0 2006.280.08:24:41.78#ibcon#enter sib2, iclass 16, count 0 2006.280.08:24:41.78#ibcon#flushed, iclass 16, count 0 2006.280.08:24:41.78#ibcon#about to write, iclass 16, count 0 2006.280.08:24:41.78#ibcon#wrote, iclass 16, count 0 2006.280.08:24:41.78#ibcon#about to read 3, iclass 16, count 0 2006.280.08:24:41.80#ibcon#read 3, iclass 16, count 0 2006.280.08:24:41.80#ibcon#about to read 4, iclass 16, count 0 2006.280.08:24:41.80#ibcon#read 4, iclass 16, count 0 2006.280.08:24:41.80#ibcon#about to read 5, iclass 16, count 0 2006.280.08:24:41.80#ibcon#read 5, iclass 16, count 0 2006.280.08:24:41.80#ibcon#about to read 6, iclass 16, count 0 2006.280.08:24:41.80#ibcon#read 6, iclass 16, count 0 2006.280.08:24:41.80#ibcon#end of sib2, iclass 16, count 0 2006.280.08:24:41.80#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:24:41.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:24:41.80#ibcon#[26=FRQ=03,672.99\r\n] 2006.280.08:24:41.80#ibcon#*before write, iclass 16, count 0 2006.280.08:24:41.80#ibcon#enter sib2, iclass 16, count 0 2006.280.08:24:41.80#ibcon#flushed, iclass 16, count 0 2006.280.08:24:41.80#ibcon#about to write, iclass 16, count 0 2006.280.08:24:41.80#ibcon#wrote, iclass 16, count 0 2006.280.08:24:41.80#ibcon#about to read 3, iclass 16, count 0 2006.280.08:24:41.84#ibcon#read 3, iclass 16, count 0 2006.280.08:24:41.84#ibcon#about to read 4, iclass 16, count 0 2006.280.08:24:41.84#ibcon#read 4, iclass 16, count 0 2006.280.08:24:41.84#ibcon#about to read 5, iclass 16, count 0 2006.280.08:24:41.84#ibcon#read 5, iclass 16, count 0 2006.280.08:24:41.84#ibcon#about to read 6, iclass 16, count 0 2006.280.08:24:41.84#ibcon#read 6, iclass 16, count 0 2006.280.08:24:41.84#ibcon#end of sib2, iclass 16, count 0 2006.280.08:24:41.84#ibcon#*after write, iclass 16, count 0 2006.280.08:24:41.84#ibcon#*before return 0, iclass 16, count 0 2006.280.08:24:41.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:41.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:41.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:24:41.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:24:41.84$vc4f8/va=3,6 2006.280.08:24:41.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:24:41.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:24:41.86#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:41.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:41.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:41.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:41.89#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:24:41.89#ibcon#first serial, iclass 18, count 2 2006.280.08:24:41.89#ibcon#enter sib2, iclass 18, count 2 2006.280.08:24:41.89#ibcon#flushed, iclass 18, count 2 2006.280.08:24:41.89#ibcon#about to write, iclass 18, count 2 2006.280.08:24:41.89#ibcon#wrote, iclass 18, count 2 2006.280.08:24:41.89#ibcon#about to read 3, iclass 18, count 2 2006.280.08:24:41.91#ibcon#read 3, iclass 18, count 2 2006.280.08:24:41.91#ibcon#about to read 4, iclass 18, count 2 2006.280.08:24:41.91#ibcon#read 4, iclass 18, count 2 2006.280.08:24:41.91#ibcon#about to read 5, iclass 18, count 2 2006.280.08:24:41.91#ibcon#read 5, iclass 18, count 2 2006.280.08:24:41.91#ibcon#about to read 6, iclass 18, count 2 2006.280.08:24:41.91#ibcon#read 6, iclass 18, count 2 2006.280.08:24:41.91#ibcon#end of sib2, iclass 18, count 2 2006.280.08:24:41.91#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:24:41.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:24:41.91#ibcon#[25=AT03-06\r\n] 2006.280.08:24:41.91#ibcon#*before write, iclass 18, count 2 2006.280.08:24:41.91#ibcon#enter sib2, iclass 18, count 2 2006.280.08:24:41.91#ibcon#flushed, iclass 18, count 2 2006.280.08:24:41.91#ibcon#about to write, iclass 18, count 2 2006.280.08:24:41.91#ibcon#wrote, iclass 18, count 2 2006.280.08:24:41.91#ibcon#about to read 3, iclass 18, count 2 2006.280.08:24:41.94#ibcon#read 3, iclass 18, count 2 2006.280.08:24:41.94#ibcon#about to read 4, iclass 18, count 2 2006.280.08:24:41.94#ibcon#read 4, iclass 18, count 2 2006.280.08:24:41.94#ibcon#about to read 5, iclass 18, count 2 2006.280.08:24:41.94#ibcon#read 5, iclass 18, count 2 2006.280.08:24:41.94#ibcon#about to read 6, iclass 18, count 2 2006.280.08:24:41.94#ibcon#read 6, iclass 18, count 2 2006.280.08:24:41.94#ibcon#end of sib2, iclass 18, count 2 2006.280.08:24:41.94#ibcon#*after write, iclass 18, count 2 2006.280.08:24:41.94#ibcon#*before return 0, iclass 18, count 2 2006.280.08:24:41.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:41.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:41.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:24:41.94#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:41.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:42.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:42.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:42.06#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:24:42.06#ibcon#first serial, iclass 18, count 0 2006.280.08:24:42.06#ibcon#enter sib2, iclass 18, count 0 2006.280.08:24:42.06#ibcon#flushed, iclass 18, count 0 2006.280.08:24:42.06#ibcon#about to write, iclass 18, count 0 2006.280.08:24:42.06#ibcon#wrote, iclass 18, count 0 2006.280.08:24:42.06#ibcon#about to read 3, iclass 18, count 0 2006.280.08:24:42.08#ibcon#read 3, iclass 18, count 0 2006.280.08:24:42.08#ibcon#about to read 4, iclass 18, count 0 2006.280.08:24:42.08#ibcon#read 4, iclass 18, count 0 2006.280.08:24:42.08#ibcon#about to read 5, iclass 18, count 0 2006.280.08:24:42.08#ibcon#read 5, iclass 18, count 0 2006.280.08:24:42.08#ibcon#about to read 6, iclass 18, count 0 2006.280.08:24:42.08#ibcon#read 6, iclass 18, count 0 2006.280.08:24:42.08#ibcon#end of sib2, iclass 18, count 0 2006.280.08:24:42.08#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:24:42.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:24:42.08#ibcon#[25=USB\r\n] 2006.280.08:24:42.08#ibcon#*before write, iclass 18, count 0 2006.280.08:24:42.08#ibcon#enter sib2, iclass 18, count 0 2006.280.08:24:42.08#ibcon#flushed, iclass 18, count 0 2006.280.08:24:42.08#ibcon#about to write, iclass 18, count 0 2006.280.08:24:42.08#ibcon#wrote, iclass 18, count 0 2006.280.08:24:42.08#ibcon#about to read 3, iclass 18, count 0 2006.280.08:24:42.11#ibcon#read 3, iclass 18, count 0 2006.280.08:24:42.11#ibcon#about to read 4, iclass 18, count 0 2006.280.08:24:42.11#ibcon#read 4, iclass 18, count 0 2006.280.08:24:42.11#ibcon#about to read 5, iclass 18, count 0 2006.280.08:24:42.11#ibcon#read 5, iclass 18, count 0 2006.280.08:24:42.11#ibcon#about to read 6, iclass 18, count 0 2006.280.08:24:42.11#ibcon#read 6, iclass 18, count 0 2006.280.08:24:42.11#ibcon#end of sib2, iclass 18, count 0 2006.280.08:24:42.11#ibcon#*after write, iclass 18, count 0 2006.280.08:24:42.11#ibcon#*before return 0, iclass 18, count 0 2006.280.08:24:42.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:42.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:42.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:24:42.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:24:42.11$vc4f8/valo=4,832.99 2006.280.08:24:42.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:24:42.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:24:42.11#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:42.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:42.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:42.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:42.11#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:24:42.11#ibcon#first serial, iclass 20, count 0 2006.280.08:24:42.11#ibcon#enter sib2, iclass 20, count 0 2006.280.08:24:42.11#ibcon#flushed, iclass 20, count 0 2006.280.08:24:42.11#ibcon#about to write, iclass 20, count 0 2006.280.08:24:42.11#ibcon#wrote, iclass 20, count 0 2006.280.08:24:42.11#ibcon#about to read 3, iclass 20, count 0 2006.280.08:24:42.13#ibcon#read 3, iclass 20, count 0 2006.280.08:24:42.13#ibcon#about to read 4, iclass 20, count 0 2006.280.08:24:42.13#ibcon#read 4, iclass 20, count 0 2006.280.08:24:42.13#ibcon#about to read 5, iclass 20, count 0 2006.280.08:24:42.13#ibcon#read 5, iclass 20, count 0 2006.280.08:24:42.13#ibcon#about to read 6, iclass 20, count 0 2006.280.08:24:42.13#ibcon#read 6, iclass 20, count 0 2006.280.08:24:42.13#ibcon#end of sib2, iclass 20, count 0 2006.280.08:24:42.13#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:24:42.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:24:42.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.280.08:24:42.13#ibcon#*before write, iclass 20, count 0 2006.280.08:24:42.13#ibcon#enter sib2, iclass 20, count 0 2006.280.08:24:42.13#ibcon#flushed, iclass 20, count 0 2006.280.08:24:42.13#ibcon#about to write, iclass 20, count 0 2006.280.08:24:42.13#ibcon#wrote, iclass 20, count 0 2006.280.08:24:42.13#ibcon#about to read 3, iclass 20, count 0 2006.280.08:24:42.17#ibcon#read 3, iclass 20, count 0 2006.280.08:24:42.17#ibcon#about to read 4, iclass 20, count 0 2006.280.08:24:42.17#ibcon#read 4, iclass 20, count 0 2006.280.08:24:42.17#ibcon#about to read 5, iclass 20, count 0 2006.280.08:24:42.17#ibcon#read 5, iclass 20, count 0 2006.280.08:24:42.17#ibcon#about to read 6, iclass 20, count 0 2006.280.08:24:42.17#ibcon#read 6, iclass 20, count 0 2006.280.08:24:42.17#ibcon#end of sib2, iclass 20, count 0 2006.280.08:24:42.17#ibcon#*after write, iclass 20, count 0 2006.280.08:24:42.17#ibcon#*before return 0, iclass 20, count 0 2006.280.08:24:42.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:42.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:42.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:24:42.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:24:42.17$vc4f8/va=4,6 2006.280.08:24:42.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.08:24:42.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.08:24:42.17#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:42.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:42.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:42.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:42.23#ibcon#enter wrdev, iclass 22, count 2 2006.280.08:24:42.23#ibcon#first serial, iclass 22, count 2 2006.280.08:24:42.23#ibcon#enter sib2, iclass 22, count 2 2006.280.08:24:42.23#ibcon#flushed, iclass 22, count 2 2006.280.08:24:42.23#ibcon#about to write, iclass 22, count 2 2006.280.08:24:42.23#ibcon#wrote, iclass 22, count 2 2006.280.08:24:42.23#ibcon#about to read 3, iclass 22, count 2 2006.280.08:24:42.26#ibcon#read 3, iclass 22, count 2 2006.280.08:24:42.26#ibcon#about to read 4, iclass 22, count 2 2006.280.08:24:42.26#ibcon#read 4, iclass 22, count 2 2006.280.08:24:42.26#ibcon#about to read 5, iclass 22, count 2 2006.280.08:24:42.26#ibcon#read 5, iclass 22, count 2 2006.280.08:24:42.26#ibcon#about to read 6, iclass 22, count 2 2006.280.08:24:42.26#ibcon#read 6, iclass 22, count 2 2006.280.08:24:42.26#ibcon#end of sib2, iclass 22, count 2 2006.280.08:24:42.26#ibcon#*mode == 0, iclass 22, count 2 2006.280.08:24:42.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.08:24:42.26#ibcon#[25=AT04-06\r\n] 2006.280.08:24:42.26#ibcon#*before write, iclass 22, count 2 2006.280.08:24:42.26#ibcon#enter sib2, iclass 22, count 2 2006.280.08:24:42.26#ibcon#flushed, iclass 22, count 2 2006.280.08:24:42.26#ibcon#about to write, iclass 22, count 2 2006.280.08:24:42.26#ibcon#wrote, iclass 22, count 2 2006.280.08:24:42.26#ibcon#about to read 3, iclass 22, count 2 2006.280.08:24:42.29#ibcon#read 3, iclass 22, count 2 2006.280.08:24:42.29#ibcon#about to read 4, iclass 22, count 2 2006.280.08:24:42.29#ibcon#read 4, iclass 22, count 2 2006.280.08:24:42.29#ibcon#about to read 5, iclass 22, count 2 2006.280.08:24:42.29#ibcon#read 5, iclass 22, count 2 2006.280.08:24:42.29#ibcon#about to read 6, iclass 22, count 2 2006.280.08:24:42.29#ibcon#read 6, iclass 22, count 2 2006.280.08:24:42.29#ibcon#end of sib2, iclass 22, count 2 2006.280.08:24:42.29#ibcon#*after write, iclass 22, count 2 2006.280.08:24:42.29#ibcon#*before return 0, iclass 22, count 2 2006.280.08:24:42.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:42.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:42.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.08:24:42.29#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:42.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:42.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:42.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:42.41#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:24:42.41#ibcon#first serial, iclass 22, count 0 2006.280.08:24:42.41#ibcon#enter sib2, iclass 22, count 0 2006.280.08:24:42.41#ibcon#flushed, iclass 22, count 0 2006.280.08:24:42.41#ibcon#about to write, iclass 22, count 0 2006.280.08:24:42.41#ibcon#wrote, iclass 22, count 0 2006.280.08:24:42.41#ibcon#about to read 3, iclass 22, count 0 2006.280.08:24:42.43#ibcon#read 3, iclass 22, count 0 2006.280.08:24:42.43#ibcon#about to read 4, iclass 22, count 0 2006.280.08:24:42.43#ibcon#read 4, iclass 22, count 0 2006.280.08:24:42.43#ibcon#about to read 5, iclass 22, count 0 2006.280.08:24:42.43#ibcon#read 5, iclass 22, count 0 2006.280.08:24:42.43#ibcon#about to read 6, iclass 22, count 0 2006.280.08:24:42.43#ibcon#read 6, iclass 22, count 0 2006.280.08:24:42.43#ibcon#end of sib2, iclass 22, count 0 2006.280.08:24:42.43#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:24:42.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:24:42.43#ibcon#[25=USB\r\n] 2006.280.08:24:42.43#ibcon#*before write, iclass 22, count 0 2006.280.08:24:42.43#ibcon#enter sib2, iclass 22, count 0 2006.280.08:24:42.43#ibcon#flushed, iclass 22, count 0 2006.280.08:24:42.43#ibcon#about to write, iclass 22, count 0 2006.280.08:24:42.43#ibcon#wrote, iclass 22, count 0 2006.280.08:24:42.43#ibcon#about to read 3, iclass 22, count 0 2006.280.08:24:42.46#ibcon#read 3, iclass 22, count 0 2006.280.08:24:42.46#ibcon#about to read 4, iclass 22, count 0 2006.280.08:24:42.46#ibcon#read 4, iclass 22, count 0 2006.280.08:24:42.46#ibcon#about to read 5, iclass 22, count 0 2006.280.08:24:42.46#ibcon#read 5, iclass 22, count 0 2006.280.08:24:42.46#ibcon#about to read 6, iclass 22, count 0 2006.280.08:24:42.46#ibcon#read 6, iclass 22, count 0 2006.280.08:24:42.46#ibcon#end of sib2, iclass 22, count 0 2006.280.08:24:42.46#ibcon#*after write, iclass 22, count 0 2006.280.08:24:42.46#ibcon#*before return 0, iclass 22, count 0 2006.280.08:24:42.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:42.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:42.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:24:42.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:24:42.46$vc4f8/valo=5,652.99 2006.280.08:24:42.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:24:42.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:24:42.46#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:42.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:42.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:42.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:42.46#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:24:42.46#ibcon#first serial, iclass 24, count 0 2006.280.08:24:42.46#ibcon#enter sib2, iclass 24, count 0 2006.280.08:24:42.46#ibcon#flushed, iclass 24, count 0 2006.280.08:24:42.46#ibcon#about to write, iclass 24, count 0 2006.280.08:24:42.46#ibcon#wrote, iclass 24, count 0 2006.280.08:24:42.46#ibcon#about to read 3, iclass 24, count 0 2006.280.08:24:42.48#ibcon#read 3, iclass 24, count 0 2006.280.08:24:42.48#ibcon#about to read 4, iclass 24, count 0 2006.280.08:24:42.48#ibcon#read 4, iclass 24, count 0 2006.280.08:24:42.48#ibcon#about to read 5, iclass 24, count 0 2006.280.08:24:42.48#ibcon#read 5, iclass 24, count 0 2006.280.08:24:42.48#ibcon#about to read 6, iclass 24, count 0 2006.280.08:24:42.48#ibcon#read 6, iclass 24, count 0 2006.280.08:24:42.48#ibcon#end of sib2, iclass 24, count 0 2006.280.08:24:42.48#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:24:42.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:24:42.48#ibcon#[26=FRQ=05,652.99\r\n] 2006.280.08:24:42.48#ibcon#*before write, iclass 24, count 0 2006.280.08:24:42.48#ibcon#enter sib2, iclass 24, count 0 2006.280.08:24:42.48#ibcon#flushed, iclass 24, count 0 2006.280.08:24:42.48#ibcon#about to write, iclass 24, count 0 2006.280.08:24:42.48#ibcon#wrote, iclass 24, count 0 2006.280.08:24:42.48#ibcon#about to read 3, iclass 24, count 0 2006.280.08:24:42.52#ibcon#read 3, iclass 24, count 0 2006.280.08:24:42.52#ibcon#about to read 4, iclass 24, count 0 2006.280.08:24:42.52#ibcon#read 4, iclass 24, count 0 2006.280.08:24:42.52#ibcon#about to read 5, iclass 24, count 0 2006.280.08:24:42.52#ibcon#read 5, iclass 24, count 0 2006.280.08:24:42.52#ibcon#about to read 6, iclass 24, count 0 2006.280.08:24:42.52#ibcon#read 6, iclass 24, count 0 2006.280.08:24:42.52#ibcon#end of sib2, iclass 24, count 0 2006.280.08:24:42.52#ibcon#*after write, iclass 24, count 0 2006.280.08:24:42.52#ibcon#*before return 0, iclass 24, count 0 2006.280.08:24:42.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:42.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:42.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:24:42.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:24:42.52$vc4f8/va=5,7 2006.280.08:24:42.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:24:42.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:24:42.52#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:42.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:42.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:42.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:42.58#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:24:42.58#ibcon#first serial, iclass 26, count 2 2006.280.08:24:42.58#ibcon#enter sib2, iclass 26, count 2 2006.280.08:24:42.58#ibcon#flushed, iclass 26, count 2 2006.280.08:24:42.58#ibcon#about to write, iclass 26, count 2 2006.280.08:24:42.58#ibcon#wrote, iclass 26, count 2 2006.280.08:24:42.58#ibcon#about to read 3, iclass 26, count 2 2006.280.08:24:42.60#ibcon#read 3, iclass 26, count 2 2006.280.08:24:42.60#ibcon#about to read 4, iclass 26, count 2 2006.280.08:24:42.60#ibcon#read 4, iclass 26, count 2 2006.280.08:24:42.60#ibcon#about to read 5, iclass 26, count 2 2006.280.08:24:42.60#ibcon#read 5, iclass 26, count 2 2006.280.08:24:42.60#ibcon#about to read 6, iclass 26, count 2 2006.280.08:24:42.60#ibcon#read 6, iclass 26, count 2 2006.280.08:24:42.60#ibcon#end of sib2, iclass 26, count 2 2006.280.08:24:42.60#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:24:42.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:24:42.60#ibcon#[25=AT05-07\r\n] 2006.280.08:24:42.60#ibcon#*before write, iclass 26, count 2 2006.280.08:24:42.60#ibcon#enter sib2, iclass 26, count 2 2006.280.08:24:42.60#ibcon#flushed, iclass 26, count 2 2006.280.08:24:42.60#ibcon#about to write, iclass 26, count 2 2006.280.08:24:42.60#ibcon#wrote, iclass 26, count 2 2006.280.08:24:42.60#ibcon#about to read 3, iclass 26, count 2 2006.280.08:24:42.63#ibcon#read 3, iclass 26, count 2 2006.280.08:24:42.63#ibcon#about to read 4, iclass 26, count 2 2006.280.08:24:42.63#ibcon#read 4, iclass 26, count 2 2006.280.08:24:42.63#ibcon#about to read 5, iclass 26, count 2 2006.280.08:24:42.63#ibcon#read 5, iclass 26, count 2 2006.280.08:24:42.63#ibcon#about to read 6, iclass 26, count 2 2006.280.08:24:42.63#ibcon#read 6, iclass 26, count 2 2006.280.08:24:42.63#ibcon#end of sib2, iclass 26, count 2 2006.280.08:24:42.63#ibcon#*after write, iclass 26, count 2 2006.280.08:24:42.63#ibcon#*before return 0, iclass 26, count 2 2006.280.08:24:42.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:42.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:42.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:24:42.63#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:42.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:42.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:42.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:42.76#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:24:42.76#ibcon#first serial, iclass 26, count 0 2006.280.08:24:42.76#ibcon#enter sib2, iclass 26, count 0 2006.280.08:24:42.76#ibcon#flushed, iclass 26, count 0 2006.280.08:24:42.76#ibcon#about to write, iclass 26, count 0 2006.280.08:24:42.76#ibcon#wrote, iclass 26, count 0 2006.280.08:24:42.76#ibcon#about to read 3, iclass 26, count 0 2006.280.08:24:42.77#ibcon#read 3, iclass 26, count 0 2006.280.08:24:42.77#ibcon#about to read 4, iclass 26, count 0 2006.280.08:24:42.77#ibcon#read 4, iclass 26, count 0 2006.280.08:24:42.77#ibcon#about to read 5, iclass 26, count 0 2006.280.08:24:42.77#ibcon#read 5, iclass 26, count 0 2006.280.08:24:42.77#ibcon#about to read 6, iclass 26, count 0 2006.280.08:24:42.77#ibcon#read 6, iclass 26, count 0 2006.280.08:24:42.77#ibcon#end of sib2, iclass 26, count 0 2006.280.08:24:42.77#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:24:42.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:24:42.77#ibcon#[25=USB\r\n] 2006.280.08:24:42.77#ibcon#*before write, iclass 26, count 0 2006.280.08:24:42.77#ibcon#enter sib2, iclass 26, count 0 2006.280.08:24:42.77#ibcon#flushed, iclass 26, count 0 2006.280.08:24:42.77#ibcon#about to write, iclass 26, count 0 2006.280.08:24:42.77#ibcon#wrote, iclass 26, count 0 2006.280.08:24:42.77#ibcon#about to read 3, iclass 26, count 0 2006.280.08:24:42.80#ibcon#read 3, iclass 26, count 0 2006.280.08:24:42.80#ibcon#about to read 4, iclass 26, count 0 2006.280.08:24:42.80#ibcon#read 4, iclass 26, count 0 2006.280.08:24:42.80#ibcon#about to read 5, iclass 26, count 0 2006.280.08:24:42.80#ibcon#read 5, iclass 26, count 0 2006.280.08:24:42.80#ibcon#about to read 6, iclass 26, count 0 2006.280.08:24:42.80#ibcon#read 6, iclass 26, count 0 2006.280.08:24:42.80#ibcon#end of sib2, iclass 26, count 0 2006.280.08:24:42.80#ibcon#*after write, iclass 26, count 0 2006.280.08:24:42.80#ibcon#*before return 0, iclass 26, count 0 2006.280.08:24:42.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:42.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:42.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:24:42.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:24:42.80$vc4f8/valo=6,772.99 2006.280.08:24:42.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:24:42.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:24:42.80#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:42.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:42.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:42.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:42.80#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:24:42.80#ibcon#first serial, iclass 28, count 0 2006.280.08:24:42.80#ibcon#enter sib2, iclass 28, count 0 2006.280.08:24:42.80#ibcon#flushed, iclass 28, count 0 2006.280.08:24:42.80#ibcon#about to write, iclass 28, count 0 2006.280.08:24:42.80#ibcon#wrote, iclass 28, count 0 2006.280.08:24:42.80#ibcon#about to read 3, iclass 28, count 0 2006.280.08:24:42.82#ibcon#read 3, iclass 28, count 0 2006.280.08:24:42.82#ibcon#about to read 4, iclass 28, count 0 2006.280.08:24:42.82#ibcon#read 4, iclass 28, count 0 2006.280.08:24:42.82#ibcon#about to read 5, iclass 28, count 0 2006.280.08:24:42.82#ibcon#read 5, iclass 28, count 0 2006.280.08:24:42.82#ibcon#about to read 6, iclass 28, count 0 2006.280.08:24:42.82#ibcon#read 6, iclass 28, count 0 2006.280.08:24:42.82#ibcon#end of sib2, iclass 28, count 0 2006.280.08:24:42.82#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:24:42.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:24:42.82#ibcon#[26=FRQ=06,772.99\r\n] 2006.280.08:24:42.82#ibcon#*before write, iclass 28, count 0 2006.280.08:24:42.82#ibcon#enter sib2, iclass 28, count 0 2006.280.08:24:42.82#ibcon#flushed, iclass 28, count 0 2006.280.08:24:42.82#ibcon#about to write, iclass 28, count 0 2006.280.08:24:42.82#ibcon#wrote, iclass 28, count 0 2006.280.08:24:42.82#ibcon#about to read 3, iclass 28, count 0 2006.280.08:24:42.86#ibcon#read 3, iclass 28, count 0 2006.280.08:24:42.86#ibcon#about to read 4, iclass 28, count 0 2006.280.08:24:42.86#ibcon#read 4, iclass 28, count 0 2006.280.08:24:42.86#ibcon#about to read 5, iclass 28, count 0 2006.280.08:24:42.86#ibcon#read 5, iclass 28, count 0 2006.280.08:24:42.86#ibcon#about to read 6, iclass 28, count 0 2006.280.08:24:42.86#ibcon#read 6, iclass 28, count 0 2006.280.08:24:42.86#ibcon#end of sib2, iclass 28, count 0 2006.280.08:24:42.86#ibcon#*after write, iclass 28, count 0 2006.280.08:24:42.86#ibcon#*before return 0, iclass 28, count 0 2006.280.08:24:42.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:42.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:42.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:24:42.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:24:42.86$vc4f8/va=6,6 2006.280.08:24:42.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.280.08:24:42.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.280.08:24:42.86#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:42.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:42.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:42.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:42.92#ibcon#enter wrdev, iclass 30, count 2 2006.280.08:24:42.92#ibcon#first serial, iclass 30, count 2 2006.280.08:24:42.92#ibcon#enter sib2, iclass 30, count 2 2006.280.08:24:42.92#ibcon#flushed, iclass 30, count 2 2006.280.08:24:42.92#ibcon#about to write, iclass 30, count 2 2006.280.08:24:42.92#ibcon#wrote, iclass 30, count 2 2006.280.08:24:42.92#ibcon#about to read 3, iclass 30, count 2 2006.280.08:24:42.94#ibcon#read 3, iclass 30, count 2 2006.280.08:24:42.94#ibcon#about to read 4, iclass 30, count 2 2006.280.08:24:42.94#ibcon#read 4, iclass 30, count 2 2006.280.08:24:42.94#ibcon#about to read 5, iclass 30, count 2 2006.280.08:24:42.94#ibcon#read 5, iclass 30, count 2 2006.280.08:24:42.94#ibcon#about to read 6, iclass 30, count 2 2006.280.08:24:42.94#ibcon#read 6, iclass 30, count 2 2006.280.08:24:42.94#ibcon#end of sib2, iclass 30, count 2 2006.280.08:24:42.94#ibcon#*mode == 0, iclass 30, count 2 2006.280.08:24:42.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.280.08:24:42.94#ibcon#[25=AT06-06\r\n] 2006.280.08:24:42.94#ibcon#*before write, iclass 30, count 2 2006.280.08:24:42.94#ibcon#enter sib2, iclass 30, count 2 2006.280.08:24:42.94#ibcon#flushed, iclass 30, count 2 2006.280.08:24:42.94#ibcon#about to write, iclass 30, count 2 2006.280.08:24:42.94#ibcon#wrote, iclass 30, count 2 2006.280.08:24:42.94#ibcon#about to read 3, iclass 30, count 2 2006.280.08:24:42.97#ibcon#read 3, iclass 30, count 2 2006.280.08:24:42.97#ibcon#about to read 4, iclass 30, count 2 2006.280.08:24:42.97#ibcon#read 4, iclass 30, count 2 2006.280.08:24:42.97#ibcon#about to read 5, iclass 30, count 2 2006.280.08:24:42.97#ibcon#read 5, iclass 30, count 2 2006.280.08:24:42.97#ibcon#about to read 6, iclass 30, count 2 2006.280.08:24:42.97#ibcon#read 6, iclass 30, count 2 2006.280.08:24:42.97#ibcon#end of sib2, iclass 30, count 2 2006.280.08:24:42.97#ibcon#*after write, iclass 30, count 2 2006.280.08:24:42.97#ibcon#*before return 0, iclass 30, count 2 2006.280.08:24:42.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:42.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:42.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.280.08:24:42.97#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:42.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:24:43.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:24:43.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:24:43.10#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:24:43.10#ibcon#first serial, iclass 30, count 0 2006.280.08:24:43.10#ibcon#enter sib2, iclass 30, count 0 2006.280.08:24:43.10#ibcon#flushed, iclass 30, count 0 2006.280.08:24:43.10#ibcon#about to write, iclass 30, count 0 2006.280.08:24:43.10#ibcon#wrote, iclass 30, count 0 2006.280.08:24:43.10#ibcon#about to read 3, iclass 30, count 0 2006.280.08:24:43.11#ibcon#read 3, iclass 30, count 0 2006.280.08:24:43.11#ibcon#about to read 4, iclass 30, count 0 2006.280.08:24:43.11#ibcon#read 4, iclass 30, count 0 2006.280.08:24:43.11#ibcon#about to read 5, iclass 30, count 0 2006.280.08:24:43.11#ibcon#read 5, iclass 30, count 0 2006.280.08:24:43.11#ibcon#about to read 6, iclass 30, count 0 2006.280.08:24:43.11#ibcon#read 6, iclass 30, count 0 2006.280.08:24:43.11#ibcon#end of sib2, iclass 30, count 0 2006.280.08:24:43.11#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:24:43.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:24:43.11#ibcon#[25=USB\r\n] 2006.280.08:24:43.11#ibcon#*before write, iclass 30, count 0 2006.280.08:24:43.11#ibcon#enter sib2, iclass 30, count 0 2006.280.08:24:43.11#ibcon#flushed, iclass 30, count 0 2006.280.08:24:43.11#ibcon#about to write, iclass 30, count 0 2006.280.08:24:43.11#ibcon#wrote, iclass 30, count 0 2006.280.08:24:43.11#ibcon#about to read 3, iclass 30, count 0 2006.280.08:24:43.14#ibcon#read 3, iclass 30, count 0 2006.280.08:24:43.14#ibcon#about to read 4, iclass 30, count 0 2006.280.08:24:43.14#ibcon#read 4, iclass 30, count 0 2006.280.08:24:43.14#ibcon#about to read 5, iclass 30, count 0 2006.280.08:24:43.14#ibcon#read 5, iclass 30, count 0 2006.280.08:24:43.14#ibcon#about to read 6, iclass 30, count 0 2006.280.08:24:43.14#ibcon#read 6, iclass 30, count 0 2006.280.08:24:43.14#ibcon#end of sib2, iclass 30, count 0 2006.280.08:24:43.14#ibcon#*after write, iclass 30, count 0 2006.280.08:24:43.14#ibcon#*before return 0, iclass 30, count 0 2006.280.08:24:43.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:24:43.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.280.08:24:43.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:24:43.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:24:43.14$vc4f8/valo=7,832.99 2006.280.08:24:43.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.280.08:24:43.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.280.08:24:43.14#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:43.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:24:43.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:24:43.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:24:43.14#ibcon#enter wrdev, iclass 32, count 0 2006.280.08:24:43.14#ibcon#first serial, iclass 32, count 0 2006.280.08:24:43.14#ibcon#enter sib2, iclass 32, count 0 2006.280.08:24:43.14#ibcon#flushed, iclass 32, count 0 2006.280.08:24:43.14#ibcon#about to write, iclass 32, count 0 2006.280.08:24:43.14#ibcon#wrote, iclass 32, count 0 2006.280.08:24:43.14#ibcon#about to read 3, iclass 32, count 0 2006.280.08:24:43.16#ibcon#read 3, iclass 32, count 0 2006.280.08:24:43.16#ibcon#about to read 4, iclass 32, count 0 2006.280.08:24:43.16#ibcon#read 4, iclass 32, count 0 2006.280.08:24:43.16#ibcon#about to read 5, iclass 32, count 0 2006.280.08:24:43.16#ibcon#read 5, iclass 32, count 0 2006.280.08:24:43.16#ibcon#about to read 6, iclass 32, count 0 2006.280.08:24:43.16#ibcon#read 6, iclass 32, count 0 2006.280.08:24:43.16#ibcon#end of sib2, iclass 32, count 0 2006.280.08:24:43.16#ibcon#*mode == 0, iclass 32, count 0 2006.280.08:24:43.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.280.08:24:43.16#ibcon#[26=FRQ=07,832.99\r\n] 2006.280.08:24:43.16#ibcon#*before write, iclass 32, count 0 2006.280.08:24:43.16#ibcon#enter sib2, iclass 32, count 0 2006.280.08:24:43.16#ibcon#flushed, iclass 32, count 0 2006.280.08:24:43.16#ibcon#about to write, iclass 32, count 0 2006.280.08:24:43.16#ibcon#wrote, iclass 32, count 0 2006.280.08:24:43.16#ibcon#about to read 3, iclass 32, count 0 2006.280.08:24:43.20#ibcon#read 3, iclass 32, count 0 2006.280.08:24:43.20#ibcon#about to read 4, iclass 32, count 0 2006.280.08:24:43.20#ibcon#read 4, iclass 32, count 0 2006.280.08:24:43.20#ibcon#about to read 5, iclass 32, count 0 2006.280.08:24:43.20#ibcon#read 5, iclass 32, count 0 2006.280.08:24:43.20#ibcon#about to read 6, iclass 32, count 0 2006.280.08:24:43.20#ibcon#read 6, iclass 32, count 0 2006.280.08:24:43.20#ibcon#end of sib2, iclass 32, count 0 2006.280.08:24:43.20#ibcon#*after write, iclass 32, count 0 2006.280.08:24:43.20#ibcon#*before return 0, iclass 32, count 0 2006.280.08:24:43.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:24:43.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.280.08:24:43.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.280.08:24:43.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.280.08:24:43.20$vc4f8/va=7,6 2006.280.08:24:43.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.280.08:24:43.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.280.08:24:43.20#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:43.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:24:43.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:24:43.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:24:43.26#ibcon#enter wrdev, iclass 34, count 2 2006.280.08:24:43.26#ibcon#first serial, iclass 34, count 2 2006.280.08:24:43.26#ibcon#enter sib2, iclass 34, count 2 2006.280.08:24:43.26#ibcon#flushed, iclass 34, count 2 2006.280.08:24:43.26#ibcon#about to write, iclass 34, count 2 2006.280.08:24:43.26#ibcon#wrote, iclass 34, count 2 2006.280.08:24:43.26#ibcon#about to read 3, iclass 34, count 2 2006.280.08:24:43.29#ibcon#read 3, iclass 34, count 2 2006.280.08:24:43.29#ibcon#about to read 4, iclass 34, count 2 2006.280.08:24:43.29#ibcon#read 4, iclass 34, count 2 2006.280.08:24:43.29#ibcon#about to read 5, iclass 34, count 2 2006.280.08:24:43.29#ibcon#read 5, iclass 34, count 2 2006.280.08:24:43.29#ibcon#about to read 6, iclass 34, count 2 2006.280.08:24:43.29#ibcon#read 6, iclass 34, count 2 2006.280.08:24:43.29#ibcon#end of sib2, iclass 34, count 2 2006.280.08:24:43.29#ibcon#*mode == 0, iclass 34, count 2 2006.280.08:24:43.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.280.08:24:43.29#ibcon#[25=AT07-06\r\n] 2006.280.08:24:43.29#ibcon#*before write, iclass 34, count 2 2006.280.08:24:43.29#ibcon#enter sib2, iclass 34, count 2 2006.280.08:24:43.29#ibcon#flushed, iclass 34, count 2 2006.280.08:24:43.29#ibcon#about to write, iclass 34, count 2 2006.280.08:24:43.29#ibcon#wrote, iclass 34, count 2 2006.280.08:24:43.29#ibcon#about to read 3, iclass 34, count 2 2006.280.08:24:43.32#ibcon#read 3, iclass 34, count 2 2006.280.08:24:43.32#ibcon#about to read 4, iclass 34, count 2 2006.280.08:24:43.32#ibcon#read 4, iclass 34, count 2 2006.280.08:24:43.32#ibcon#about to read 5, iclass 34, count 2 2006.280.08:24:43.32#ibcon#read 5, iclass 34, count 2 2006.280.08:24:43.32#ibcon#about to read 6, iclass 34, count 2 2006.280.08:24:43.32#ibcon#read 6, iclass 34, count 2 2006.280.08:24:43.32#ibcon#end of sib2, iclass 34, count 2 2006.280.08:24:43.32#ibcon#*after write, iclass 34, count 2 2006.280.08:24:43.32#ibcon#*before return 0, iclass 34, count 2 2006.280.08:24:43.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:24:43.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.280.08:24:43.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.280.08:24:43.32#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:43.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:24:43.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:24:43.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:24:43.43#ibcon#enter wrdev, iclass 34, count 0 2006.280.08:24:43.43#ibcon#first serial, iclass 34, count 0 2006.280.08:24:43.43#ibcon#enter sib2, iclass 34, count 0 2006.280.08:24:43.43#ibcon#flushed, iclass 34, count 0 2006.280.08:24:43.43#ibcon#about to write, iclass 34, count 0 2006.280.08:24:43.43#ibcon#wrote, iclass 34, count 0 2006.280.08:24:43.43#ibcon#about to read 3, iclass 34, count 0 2006.280.08:24:43.45#ibcon#read 3, iclass 34, count 0 2006.280.08:24:43.45#ibcon#about to read 4, iclass 34, count 0 2006.280.08:24:43.45#ibcon#read 4, iclass 34, count 0 2006.280.08:24:43.45#ibcon#about to read 5, iclass 34, count 0 2006.280.08:24:43.45#ibcon#read 5, iclass 34, count 0 2006.280.08:24:43.45#ibcon#about to read 6, iclass 34, count 0 2006.280.08:24:43.45#ibcon#read 6, iclass 34, count 0 2006.280.08:24:43.45#ibcon#end of sib2, iclass 34, count 0 2006.280.08:24:43.45#ibcon#*mode == 0, iclass 34, count 0 2006.280.08:24:43.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.280.08:24:43.45#ibcon#[25=USB\r\n] 2006.280.08:24:43.45#ibcon#*before write, iclass 34, count 0 2006.280.08:24:43.45#ibcon#enter sib2, iclass 34, count 0 2006.280.08:24:43.45#ibcon#flushed, iclass 34, count 0 2006.280.08:24:43.45#ibcon#about to write, iclass 34, count 0 2006.280.08:24:43.45#ibcon#wrote, iclass 34, count 0 2006.280.08:24:43.45#ibcon#about to read 3, iclass 34, count 0 2006.280.08:24:43.48#ibcon#read 3, iclass 34, count 0 2006.280.08:24:43.48#ibcon#about to read 4, iclass 34, count 0 2006.280.08:24:43.48#ibcon#read 4, iclass 34, count 0 2006.280.08:24:43.48#ibcon#about to read 5, iclass 34, count 0 2006.280.08:24:43.48#ibcon#read 5, iclass 34, count 0 2006.280.08:24:43.48#ibcon#about to read 6, iclass 34, count 0 2006.280.08:24:43.48#ibcon#read 6, iclass 34, count 0 2006.280.08:24:43.48#ibcon#end of sib2, iclass 34, count 0 2006.280.08:24:43.48#ibcon#*after write, iclass 34, count 0 2006.280.08:24:43.48#ibcon#*before return 0, iclass 34, count 0 2006.280.08:24:43.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:24:43.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.280.08:24:43.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.280.08:24:43.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.280.08:24:43.48$vc4f8/valo=8,852.99 2006.280.08:24:43.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.280.08:24:43.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.280.08:24:43.48#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:43.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:24:43.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:24:43.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:24:43.48#ibcon#enter wrdev, iclass 36, count 0 2006.280.08:24:43.48#ibcon#first serial, iclass 36, count 0 2006.280.08:24:43.48#ibcon#enter sib2, iclass 36, count 0 2006.280.08:24:43.48#ibcon#flushed, iclass 36, count 0 2006.280.08:24:43.48#ibcon#about to write, iclass 36, count 0 2006.280.08:24:43.48#ibcon#wrote, iclass 36, count 0 2006.280.08:24:43.48#ibcon#about to read 3, iclass 36, count 0 2006.280.08:24:43.50#ibcon#read 3, iclass 36, count 0 2006.280.08:24:43.50#ibcon#about to read 4, iclass 36, count 0 2006.280.08:24:43.50#ibcon#read 4, iclass 36, count 0 2006.280.08:24:43.50#ibcon#about to read 5, iclass 36, count 0 2006.280.08:24:43.50#ibcon#read 5, iclass 36, count 0 2006.280.08:24:43.50#ibcon#about to read 6, iclass 36, count 0 2006.280.08:24:43.50#ibcon#read 6, iclass 36, count 0 2006.280.08:24:43.50#ibcon#end of sib2, iclass 36, count 0 2006.280.08:24:43.50#ibcon#*mode == 0, iclass 36, count 0 2006.280.08:24:43.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.280.08:24:43.50#ibcon#[26=FRQ=08,852.99\r\n] 2006.280.08:24:43.50#ibcon#*before write, iclass 36, count 0 2006.280.08:24:43.50#ibcon#enter sib2, iclass 36, count 0 2006.280.08:24:43.50#ibcon#flushed, iclass 36, count 0 2006.280.08:24:43.50#ibcon#about to write, iclass 36, count 0 2006.280.08:24:43.50#ibcon#wrote, iclass 36, count 0 2006.280.08:24:43.50#ibcon#about to read 3, iclass 36, count 0 2006.280.08:24:43.54#ibcon#read 3, iclass 36, count 0 2006.280.08:24:43.54#ibcon#about to read 4, iclass 36, count 0 2006.280.08:24:43.54#ibcon#read 4, iclass 36, count 0 2006.280.08:24:43.54#ibcon#about to read 5, iclass 36, count 0 2006.280.08:24:43.54#ibcon#read 5, iclass 36, count 0 2006.280.08:24:43.54#ibcon#about to read 6, iclass 36, count 0 2006.280.08:24:43.54#ibcon#read 6, iclass 36, count 0 2006.280.08:24:43.54#ibcon#end of sib2, iclass 36, count 0 2006.280.08:24:43.54#ibcon#*after write, iclass 36, count 0 2006.280.08:24:43.54#ibcon#*before return 0, iclass 36, count 0 2006.280.08:24:43.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:24:43.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.280.08:24:43.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.280.08:24:43.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.280.08:24:43.54$vc4f8/va=8,6 2006.280.08:24:43.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.280.08:24:43.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.280.08:24:43.55#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:43.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:24:43.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:24:43.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:24:43.59#ibcon#enter wrdev, iclass 38, count 2 2006.280.08:24:43.59#ibcon#first serial, iclass 38, count 2 2006.280.08:24:43.59#ibcon#enter sib2, iclass 38, count 2 2006.280.08:24:43.59#ibcon#flushed, iclass 38, count 2 2006.280.08:24:43.59#ibcon#about to write, iclass 38, count 2 2006.280.08:24:43.59#ibcon#wrote, iclass 38, count 2 2006.280.08:24:43.59#ibcon#about to read 3, iclass 38, count 2 2006.280.08:24:43.62#ibcon#read 3, iclass 38, count 2 2006.280.08:24:43.62#ibcon#about to read 4, iclass 38, count 2 2006.280.08:24:43.62#ibcon#read 4, iclass 38, count 2 2006.280.08:24:43.62#ibcon#about to read 5, iclass 38, count 2 2006.280.08:24:43.62#ibcon#read 5, iclass 38, count 2 2006.280.08:24:43.62#ibcon#about to read 6, iclass 38, count 2 2006.280.08:24:43.62#ibcon#read 6, iclass 38, count 2 2006.280.08:24:43.62#ibcon#end of sib2, iclass 38, count 2 2006.280.08:24:43.62#ibcon#*mode == 0, iclass 38, count 2 2006.280.08:24:43.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.280.08:24:43.62#ibcon#[25=AT08-06\r\n] 2006.280.08:24:43.62#ibcon#*before write, iclass 38, count 2 2006.280.08:24:43.62#ibcon#enter sib2, iclass 38, count 2 2006.280.08:24:43.62#ibcon#flushed, iclass 38, count 2 2006.280.08:24:43.62#ibcon#about to write, iclass 38, count 2 2006.280.08:24:43.62#ibcon#wrote, iclass 38, count 2 2006.280.08:24:43.62#ibcon#about to read 3, iclass 38, count 2 2006.280.08:24:43.64#ibcon#read 3, iclass 38, count 2 2006.280.08:24:43.64#ibcon#about to read 4, iclass 38, count 2 2006.280.08:24:43.64#ibcon#read 4, iclass 38, count 2 2006.280.08:24:43.64#ibcon#about to read 5, iclass 38, count 2 2006.280.08:24:43.64#ibcon#read 5, iclass 38, count 2 2006.280.08:24:43.64#ibcon#about to read 6, iclass 38, count 2 2006.280.08:24:43.64#ibcon#read 6, iclass 38, count 2 2006.280.08:24:43.64#ibcon#end of sib2, iclass 38, count 2 2006.280.08:24:43.64#ibcon#*after write, iclass 38, count 2 2006.280.08:24:43.64#ibcon#*before return 0, iclass 38, count 2 2006.280.08:24:43.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:24:43.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.280.08:24:43.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.280.08:24:43.64#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:43.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:24:43.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:24:43.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:24:43.76#ibcon#enter wrdev, iclass 38, count 0 2006.280.08:24:43.76#ibcon#first serial, iclass 38, count 0 2006.280.08:24:43.76#ibcon#enter sib2, iclass 38, count 0 2006.280.08:24:43.76#ibcon#flushed, iclass 38, count 0 2006.280.08:24:43.76#ibcon#about to write, iclass 38, count 0 2006.280.08:24:43.76#ibcon#wrote, iclass 38, count 0 2006.280.08:24:43.76#ibcon#about to read 3, iclass 38, count 0 2006.280.08:24:43.78#ibcon#read 3, iclass 38, count 0 2006.280.08:24:43.78#ibcon#about to read 4, iclass 38, count 0 2006.280.08:24:43.78#ibcon#read 4, iclass 38, count 0 2006.280.08:24:43.78#ibcon#about to read 5, iclass 38, count 0 2006.280.08:24:43.78#ibcon#read 5, iclass 38, count 0 2006.280.08:24:43.78#ibcon#about to read 6, iclass 38, count 0 2006.280.08:24:43.78#ibcon#read 6, iclass 38, count 0 2006.280.08:24:43.78#ibcon#end of sib2, iclass 38, count 0 2006.280.08:24:43.78#ibcon#*mode == 0, iclass 38, count 0 2006.280.08:24:43.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.280.08:24:43.78#ibcon#[25=USB\r\n] 2006.280.08:24:43.78#ibcon#*before write, iclass 38, count 0 2006.280.08:24:43.78#ibcon#enter sib2, iclass 38, count 0 2006.280.08:24:43.78#ibcon#flushed, iclass 38, count 0 2006.280.08:24:43.78#ibcon#about to write, iclass 38, count 0 2006.280.08:24:43.78#ibcon#wrote, iclass 38, count 0 2006.280.08:24:43.78#ibcon#about to read 3, iclass 38, count 0 2006.280.08:24:43.82#ibcon#read 3, iclass 38, count 0 2006.280.08:24:43.82#ibcon#about to read 4, iclass 38, count 0 2006.280.08:24:43.82#ibcon#read 4, iclass 38, count 0 2006.280.08:24:43.82#ibcon#about to read 5, iclass 38, count 0 2006.280.08:24:43.82#ibcon#read 5, iclass 38, count 0 2006.280.08:24:43.82#ibcon#about to read 6, iclass 38, count 0 2006.280.08:24:43.82#ibcon#read 6, iclass 38, count 0 2006.280.08:24:43.82#ibcon#end of sib2, iclass 38, count 0 2006.280.08:24:43.82#ibcon#*after write, iclass 38, count 0 2006.280.08:24:43.82#ibcon#*before return 0, iclass 38, count 0 2006.280.08:24:43.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:24:43.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.280.08:24:43.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.280.08:24:43.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.280.08:24:43.82$vc4f8/vblo=1,632.99 2006.280.08:24:43.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.280.08:24:43.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.280.08:24:43.82#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:43.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:24:43.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:24:43.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:24:43.82#ibcon#enter wrdev, iclass 40, count 0 2006.280.08:24:43.82#ibcon#first serial, iclass 40, count 0 2006.280.08:24:43.82#ibcon#enter sib2, iclass 40, count 0 2006.280.08:24:43.82#ibcon#flushed, iclass 40, count 0 2006.280.08:24:43.82#ibcon#about to write, iclass 40, count 0 2006.280.08:24:43.82#ibcon#wrote, iclass 40, count 0 2006.280.08:24:43.82#ibcon#about to read 3, iclass 40, count 0 2006.280.08:24:43.84#ibcon#read 3, iclass 40, count 0 2006.280.08:24:43.84#ibcon#about to read 4, iclass 40, count 0 2006.280.08:24:43.84#ibcon#read 4, iclass 40, count 0 2006.280.08:24:43.84#ibcon#about to read 5, iclass 40, count 0 2006.280.08:24:43.84#ibcon#read 5, iclass 40, count 0 2006.280.08:24:43.84#ibcon#about to read 6, iclass 40, count 0 2006.280.08:24:43.84#ibcon#read 6, iclass 40, count 0 2006.280.08:24:43.84#ibcon#end of sib2, iclass 40, count 0 2006.280.08:24:43.84#ibcon#*mode == 0, iclass 40, count 0 2006.280.08:24:43.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.280.08:24:43.84#ibcon#[28=FRQ=01,632.99\r\n] 2006.280.08:24:43.86#ibcon#*before write, iclass 40, count 0 2006.280.08:24:43.86#ibcon#enter sib2, iclass 40, count 0 2006.280.08:24:43.86#ibcon#flushed, iclass 40, count 0 2006.280.08:24:43.86#ibcon#about to write, iclass 40, count 0 2006.280.08:24:43.86#ibcon#wrote, iclass 40, count 0 2006.280.08:24:43.86#ibcon#about to read 3, iclass 40, count 0 2006.280.08:24:43.90#ibcon#read 3, iclass 40, count 0 2006.280.08:24:43.90#ibcon#about to read 4, iclass 40, count 0 2006.280.08:24:43.90#ibcon#read 4, iclass 40, count 0 2006.280.08:24:43.90#ibcon#about to read 5, iclass 40, count 0 2006.280.08:24:43.90#ibcon#read 5, iclass 40, count 0 2006.280.08:24:43.90#ibcon#about to read 6, iclass 40, count 0 2006.280.08:24:43.90#ibcon#read 6, iclass 40, count 0 2006.280.08:24:43.90#ibcon#end of sib2, iclass 40, count 0 2006.280.08:24:43.90#ibcon#*after write, iclass 40, count 0 2006.280.08:24:43.90#ibcon#*before return 0, iclass 40, count 0 2006.280.08:24:43.90#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:24:43.90#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.280.08:24:43.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.280.08:24:43.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.280.08:24:43.90$vc4f8/vb=1,4 2006.280.08:24:43.90#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.280.08:24:43.90#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.280.08:24:43.90#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:43.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:24:43.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:24:43.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:24:43.90#ibcon#enter wrdev, iclass 4, count 2 2006.280.08:24:43.90#ibcon#first serial, iclass 4, count 2 2006.280.08:24:43.90#ibcon#enter sib2, iclass 4, count 2 2006.280.08:24:43.90#ibcon#flushed, iclass 4, count 2 2006.280.08:24:43.90#ibcon#about to write, iclass 4, count 2 2006.280.08:24:43.90#ibcon#wrote, iclass 4, count 2 2006.280.08:24:43.90#ibcon#about to read 3, iclass 4, count 2 2006.280.08:24:43.92#ibcon#read 3, iclass 4, count 2 2006.280.08:24:43.92#ibcon#about to read 4, iclass 4, count 2 2006.280.08:24:43.92#ibcon#read 4, iclass 4, count 2 2006.280.08:24:43.92#ibcon#about to read 5, iclass 4, count 2 2006.280.08:24:43.92#ibcon#read 5, iclass 4, count 2 2006.280.08:24:43.92#ibcon#about to read 6, iclass 4, count 2 2006.280.08:24:43.92#ibcon#read 6, iclass 4, count 2 2006.280.08:24:43.92#ibcon#end of sib2, iclass 4, count 2 2006.280.08:24:43.92#ibcon#*mode == 0, iclass 4, count 2 2006.280.08:24:43.92#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.280.08:24:43.92#ibcon#[27=AT01-04\r\n] 2006.280.08:24:43.92#ibcon#*before write, iclass 4, count 2 2006.280.08:24:43.92#ibcon#enter sib2, iclass 4, count 2 2006.280.08:24:43.92#ibcon#flushed, iclass 4, count 2 2006.280.08:24:43.92#ibcon#about to write, iclass 4, count 2 2006.280.08:24:43.92#ibcon#wrote, iclass 4, count 2 2006.280.08:24:43.92#ibcon#about to read 3, iclass 4, count 2 2006.280.08:24:43.95#ibcon#read 3, iclass 4, count 2 2006.280.08:24:43.95#ibcon#about to read 4, iclass 4, count 2 2006.280.08:24:43.95#ibcon#read 4, iclass 4, count 2 2006.280.08:24:43.95#ibcon#about to read 5, iclass 4, count 2 2006.280.08:24:43.95#ibcon#read 5, iclass 4, count 2 2006.280.08:24:43.95#ibcon#about to read 6, iclass 4, count 2 2006.280.08:24:43.95#ibcon#read 6, iclass 4, count 2 2006.280.08:24:43.95#ibcon#end of sib2, iclass 4, count 2 2006.280.08:24:43.95#ibcon#*after write, iclass 4, count 2 2006.280.08:24:43.95#ibcon#*before return 0, iclass 4, count 2 2006.280.08:24:43.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:24:43.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.280.08:24:43.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.280.08:24:43.95#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:43.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:24:44.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:24:44.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:24:44.07#ibcon#enter wrdev, iclass 4, count 0 2006.280.08:24:44.07#ibcon#first serial, iclass 4, count 0 2006.280.08:24:44.07#ibcon#enter sib2, iclass 4, count 0 2006.280.08:24:44.07#ibcon#flushed, iclass 4, count 0 2006.280.08:24:44.07#ibcon#about to write, iclass 4, count 0 2006.280.08:24:44.07#ibcon#wrote, iclass 4, count 0 2006.280.08:24:44.07#ibcon#about to read 3, iclass 4, count 0 2006.280.08:24:44.09#ibcon#read 3, iclass 4, count 0 2006.280.08:24:44.09#ibcon#about to read 4, iclass 4, count 0 2006.280.08:24:44.09#ibcon#read 4, iclass 4, count 0 2006.280.08:24:44.09#ibcon#about to read 5, iclass 4, count 0 2006.280.08:24:44.09#ibcon#read 5, iclass 4, count 0 2006.280.08:24:44.09#ibcon#about to read 6, iclass 4, count 0 2006.280.08:24:44.09#ibcon#read 6, iclass 4, count 0 2006.280.08:24:44.09#ibcon#end of sib2, iclass 4, count 0 2006.280.08:24:44.09#ibcon#*mode == 0, iclass 4, count 0 2006.280.08:24:44.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.280.08:24:44.09#ibcon#[27=USB\r\n] 2006.280.08:24:44.09#ibcon#*before write, iclass 4, count 0 2006.280.08:24:44.09#ibcon#enter sib2, iclass 4, count 0 2006.280.08:24:44.09#ibcon#flushed, iclass 4, count 0 2006.280.08:24:44.09#ibcon#about to write, iclass 4, count 0 2006.280.08:24:44.09#ibcon#wrote, iclass 4, count 0 2006.280.08:24:44.09#ibcon#about to read 3, iclass 4, count 0 2006.280.08:24:44.12#ibcon#read 3, iclass 4, count 0 2006.280.08:24:44.12#ibcon#about to read 4, iclass 4, count 0 2006.280.08:24:44.12#ibcon#read 4, iclass 4, count 0 2006.280.08:24:44.12#ibcon#about to read 5, iclass 4, count 0 2006.280.08:24:44.12#ibcon#read 5, iclass 4, count 0 2006.280.08:24:44.12#ibcon#about to read 6, iclass 4, count 0 2006.280.08:24:44.12#ibcon#read 6, iclass 4, count 0 2006.280.08:24:44.12#ibcon#end of sib2, iclass 4, count 0 2006.280.08:24:44.12#ibcon#*after write, iclass 4, count 0 2006.280.08:24:44.12#ibcon#*before return 0, iclass 4, count 0 2006.280.08:24:44.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:24:44.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.280.08:24:44.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.280.08:24:44.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.280.08:24:44.12$vc4f8/vblo=2,640.99 2006.280.08:24:44.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.280.08:24:44.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.280.08:24:44.12#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:44.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:44.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:44.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:44.12#ibcon#enter wrdev, iclass 6, count 0 2006.280.08:24:44.12#ibcon#first serial, iclass 6, count 0 2006.280.08:24:44.12#ibcon#enter sib2, iclass 6, count 0 2006.280.08:24:44.12#ibcon#flushed, iclass 6, count 0 2006.280.08:24:44.12#ibcon#about to write, iclass 6, count 0 2006.280.08:24:44.12#ibcon#wrote, iclass 6, count 0 2006.280.08:24:44.12#ibcon#about to read 3, iclass 6, count 0 2006.280.08:24:44.14#ibcon#read 3, iclass 6, count 0 2006.280.08:24:44.14#ibcon#about to read 4, iclass 6, count 0 2006.280.08:24:44.14#ibcon#read 4, iclass 6, count 0 2006.280.08:24:44.14#ibcon#about to read 5, iclass 6, count 0 2006.280.08:24:44.14#ibcon#read 5, iclass 6, count 0 2006.280.08:24:44.14#ibcon#about to read 6, iclass 6, count 0 2006.280.08:24:44.14#ibcon#read 6, iclass 6, count 0 2006.280.08:24:44.14#ibcon#end of sib2, iclass 6, count 0 2006.280.08:24:44.14#ibcon#*mode == 0, iclass 6, count 0 2006.280.08:24:44.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.280.08:24:44.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.280.08:24:44.14#ibcon#*before write, iclass 6, count 0 2006.280.08:24:44.14#ibcon#enter sib2, iclass 6, count 0 2006.280.08:24:44.14#ibcon#flushed, iclass 6, count 0 2006.280.08:24:44.14#ibcon#about to write, iclass 6, count 0 2006.280.08:24:44.14#ibcon#wrote, iclass 6, count 0 2006.280.08:24:44.14#ibcon#about to read 3, iclass 6, count 0 2006.280.08:24:44.18#ibcon#read 3, iclass 6, count 0 2006.280.08:24:44.18#ibcon#about to read 4, iclass 6, count 0 2006.280.08:24:44.18#ibcon#read 4, iclass 6, count 0 2006.280.08:24:44.18#ibcon#about to read 5, iclass 6, count 0 2006.280.08:24:44.18#ibcon#read 5, iclass 6, count 0 2006.280.08:24:44.18#ibcon#about to read 6, iclass 6, count 0 2006.280.08:24:44.18#ibcon#read 6, iclass 6, count 0 2006.280.08:24:44.18#ibcon#end of sib2, iclass 6, count 0 2006.280.08:24:44.18#ibcon#*after write, iclass 6, count 0 2006.280.08:24:44.18#ibcon#*before return 0, iclass 6, count 0 2006.280.08:24:44.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:44.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.280.08:24:44.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.280.08:24:44.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.280.08:24:44.18$vc4f8/vb=2,5 2006.280.08:24:44.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.280.08:24:44.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.280.08:24:44.18#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:44.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:44.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:44.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:44.24#ibcon#enter wrdev, iclass 10, count 2 2006.280.08:24:44.24#ibcon#first serial, iclass 10, count 2 2006.280.08:24:44.24#ibcon#enter sib2, iclass 10, count 2 2006.280.08:24:44.24#ibcon#flushed, iclass 10, count 2 2006.280.08:24:44.24#ibcon#about to write, iclass 10, count 2 2006.280.08:24:44.24#ibcon#wrote, iclass 10, count 2 2006.280.08:24:44.24#ibcon#about to read 3, iclass 10, count 2 2006.280.08:24:44.27#ibcon#read 3, iclass 10, count 2 2006.280.08:24:44.27#ibcon#about to read 4, iclass 10, count 2 2006.280.08:24:44.27#ibcon#read 4, iclass 10, count 2 2006.280.08:24:44.27#ibcon#about to read 5, iclass 10, count 2 2006.280.08:24:44.27#ibcon#read 5, iclass 10, count 2 2006.280.08:24:44.27#ibcon#about to read 6, iclass 10, count 2 2006.280.08:24:44.27#ibcon#read 6, iclass 10, count 2 2006.280.08:24:44.27#ibcon#end of sib2, iclass 10, count 2 2006.280.08:24:44.27#ibcon#*mode == 0, iclass 10, count 2 2006.280.08:24:44.27#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.280.08:24:44.27#ibcon#[27=AT02-05\r\n] 2006.280.08:24:44.27#ibcon#*before write, iclass 10, count 2 2006.280.08:24:44.27#ibcon#enter sib2, iclass 10, count 2 2006.280.08:24:44.27#ibcon#flushed, iclass 10, count 2 2006.280.08:24:44.27#ibcon#about to write, iclass 10, count 2 2006.280.08:24:44.27#ibcon#wrote, iclass 10, count 2 2006.280.08:24:44.27#ibcon#about to read 3, iclass 10, count 2 2006.280.08:24:44.30#ibcon#read 3, iclass 10, count 2 2006.280.08:24:44.30#ibcon#about to read 4, iclass 10, count 2 2006.280.08:24:44.30#ibcon#read 4, iclass 10, count 2 2006.280.08:24:44.30#ibcon#about to read 5, iclass 10, count 2 2006.280.08:24:44.30#ibcon#read 5, iclass 10, count 2 2006.280.08:24:44.30#ibcon#about to read 6, iclass 10, count 2 2006.280.08:24:44.30#ibcon#read 6, iclass 10, count 2 2006.280.08:24:44.30#ibcon#end of sib2, iclass 10, count 2 2006.280.08:24:44.30#ibcon#*after write, iclass 10, count 2 2006.280.08:24:44.30#ibcon#*before return 0, iclass 10, count 2 2006.280.08:24:44.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:44.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.280.08:24:44.30#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.280.08:24:44.30#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:44.30#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:44.42#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:44.42#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:44.42#ibcon#enter wrdev, iclass 10, count 0 2006.280.08:24:44.42#ibcon#first serial, iclass 10, count 0 2006.280.08:24:44.42#ibcon#enter sib2, iclass 10, count 0 2006.280.08:24:44.42#ibcon#flushed, iclass 10, count 0 2006.280.08:24:44.42#ibcon#about to write, iclass 10, count 0 2006.280.08:24:44.42#ibcon#wrote, iclass 10, count 0 2006.280.08:24:44.42#ibcon#about to read 3, iclass 10, count 0 2006.280.08:24:44.44#ibcon#read 3, iclass 10, count 0 2006.280.08:24:44.44#ibcon#about to read 4, iclass 10, count 0 2006.280.08:24:44.44#ibcon#read 4, iclass 10, count 0 2006.280.08:24:44.44#ibcon#about to read 5, iclass 10, count 0 2006.280.08:24:44.44#ibcon#read 5, iclass 10, count 0 2006.280.08:24:44.44#ibcon#about to read 6, iclass 10, count 0 2006.280.08:24:44.44#ibcon#read 6, iclass 10, count 0 2006.280.08:24:44.44#ibcon#end of sib2, iclass 10, count 0 2006.280.08:24:44.44#ibcon#*mode == 0, iclass 10, count 0 2006.280.08:24:44.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.280.08:24:44.44#ibcon#[27=USB\r\n] 2006.280.08:24:44.44#ibcon#*before write, iclass 10, count 0 2006.280.08:24:44.44#ibcon#enter sib2, iclass 10, count 0 2006.280.08:24:44.44#ibcon#flushed, iclass 10, count 0 2006.280.08:24:44.44#ibcon#about to write, iclass 10, count 0 2006.280.08:24:44.44#ibcon#wrote, iclass 10, count 0 2006.280.08:24:44.44#ibcon#about to read 3, iclass 10, count 0 2006.280.08:24:44.47#ibcon#read 3, iclass 10, count 0 2006.280.08:24:44.47#ibcon#about to read 4, iclass 10, count 0 2006.280.08:24:44.47#ibcon#read 4, iclass 10, count 0 2006.280.08:24:44.47#ibcon#about to read 5, iclass 10, count 0 2006.280.08:24:44.47#ibcon#read 5, iclass 10, count 0 2006.280.08:24:44.47#ibcon#about to read 6, iclass 10, count 0 2006.280.08:24:44.47#ibcon#read 6, iclass 10, count 0 2006.280.08:24:44.47#ibcon#end of sib2, iclass 10, count 0 2006.280.08:24:44.47#ibcon#*after write, iclass 10, count 0 2006.280.08:24:44.47#ibcon#*before return 0, iclass 10, count 0 2006.280.08:24:44.47#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:44.47#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.280.08:24:44.47#ibcon#about to clear, iclass 10 cls_cnt 0 2006.280.08:24:44.47#ibcon#cleared, iclass 10 cls_cnt 0 2006.280.08:24:44.47$vc4f8/vblo=3,656.99 2006.280.08:24:44.47#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.280.08:24:44.47#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.280.08:24:44.47#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:44.47#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:44.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:44.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:44.47#ibcon#enter wrdev, iclass 12, count 0 2006.280.08:24:44.47#ibcon#first serial, iclass 12, count 0 2006.280.08:24:44.47#ibcon#enter sib2, iclass 12, count 0 2006.280.08:24:44.47#ibcon#flushed, iclass 12, count 0 2006.280.08:24:44.47#ibcon#about to write, iclass 12, count 0 2006.280.08:24:44.47#ibcon#wrote, iclass 12, count 0 2006.280.08:24:44.47#ibcon#about to read 3, iclass 12, count 0 2006.280.08:24:44.49#ibcon#read 3, iclass 12, count 0 2006.280.08:24:44.49#ibcon#about to read 4, iclass 12, count 0 2006.280.08:24:44.49#ibcon#read 4, iclass 12, count 0 2006.280.08:24:44.49#ibcon#about to read 5, iclass 12, count 0 2006.280.08:24:44.49#ibcon#read 5, iclass 12, count 0 2006.280.08:24:44.49#ibcon#about to read 6, iclass 12, count 0 2006.280.08:24:44.49#ibcon#read 6, iclass 12, count 0 2006.280.08:24:44.49#ibcon#end of sib2, iclass 12, count 0 2006.280.08:24:44.49#ibcon#*mode == 0, iclass 12, count 0 2006.280.08:24:44.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.280.08:24:44.49#ibcon#[28=FRQ=03,656.99\r\n] 2006.280.08:24:44.49#ibcon#*before write, iclass 12, count 0 2006.280.08:24:44.49#ibcon#enter sib2, iclass 12, count 0 2006.280.08:24:44.49#ibcon#flushed, iclass 12, count 0 2006.280.08:24:44.49#ibcon#about to write, iclass 12, count 0 2006.280.08:24:44.49#ibcon#wrote, iclass 12, count 0 2006.280.08:24:44.49#ibcon#about to read 3, iclass 12, count 0 2006.280.08:24:44.53#ibcon#read 3, iclass 12, count 0 2006.280.08:24:44.53#ibcon#about to read 4, iclass 12, count 0 2006.280.08:24:44.53#ibcon#read 4, iclass 12, count 0 2006.280.08:24:44.53#ibcon#about to read 5, iclass 12, count 0 2006.280.08:24:44.53#ibcon#read 5, iclass 12, count 0 2006.280.08:24:44.53#ibcon#about to read 6, iclass 12, count 0 2006.280.08:24:44.53#ibcon#read 6, iclass 12, count 0 2006.280.08:24:44.53#ibcon#end of sib2, iclass 12, count 0 2006.280.08:24:44.53#ibcon#*after write, iclass 12, count 0 2006.280.08:24:44.53#ibcon#*before return 0, iclass 12, count 0 2006.280.08:24:44.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:44.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.280.08:24:44.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.280.08:24:44.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.280.08:24:44.53$vc4f8/vb=3,4 2006.280.08:24:44.53#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.280.08:24:44.53#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.280.08:24:44.53#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:44.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:44.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:44.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:44.59#ibcon#enter wrdev, iclass 14, count 2 2006.280.08:24:44.59#ibcon#first serial, iclass 14, count 2 2006.280.08:24:44.59#ibcon#enter sib2, iclass 14, count 2 2006.280.08:24:44.59#ibcon#flushed, iclass 14, count 2 2006.280.08:24:44.59#ibcon#about to write, iclass 14, count 2 2006.280.08:24:44.59#ibcon#wrote, iclass 14, count 2 2006.280.08:24:44.59#ibcon#about to read 3, iclass 14, count 2 2006.280.08:24:44.61#ibcon#read 3, iclass 14, count 2 2006.280.08:24:44.61#ibcon#about to read 4, iclass 14, count 2 2006.280.08:24:44.61#ibcon#read 4, iclass 14, count 2 2006.280.08:24:44.61#ibcon#about to read 5, iclass 14, count 2 2006.280.08:24:44.61#ibcon#read 5, iclass 14, count 2 2006.280.08:24:44.61#ibcon#about to read 6, iclass 14, count 2 2006.280.08:24:44.61#ibcon#read 6, iclass 14, count 2 2006.280.08:24:44.61#ibcon#end of sib2, iclass 14, count 2 2006.280.08:24:44.61#ibcon#*mode == 0, iclass 14, count 2 2006.280.08:24:44.61#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.280.08:24:44.61#ibcon#[27=AT03-04\r\n] 2006.280.08:24:44.61#ibcon#*before write, iclass 14, count 2 2006.280.08:24:44.61#ibcon#enter sib2, iclass 14, count 2 2006.280.08:24:44.61#ibcon#flushed, iclass 14, count 2 2006.280.08:24:44.61#ibcon#about to write, iclass 14, count 2 2006.280.08:24:44.61#ibcon#wrote, iclass 14, count 2 2006.280.08:24:44.61#ibcon#about to read 3, iclass 14, count 2 2006.280.08:24:44.64#ibcon#read 3, iclass 14, count 2 2006.280.08:24:44.64#ibcon#about to read 4, iclass 14, count 2 2006.280.08:24:44.64#ibcon#read 4, iclass 14, count 2 2006.280.08:24:44.64#ibcon#about to read 5, iclass 14, count 2 2006.280.08:24:44.64#ibcon#read 5, iclass 14, count 2 2006.280.08:24:44.64#ibcon#about to read 6, iclass 14, count 2 2006.280.08:24:44.64#ibcon#read 6, iclass 14, count 2 2006.280.08:24:44.64#ibcon#end of sib2, iclass 14, count 2 2006.280.08:24:44.64#ibcon#*after write, iclass 14, count 2 2006.280.08:24:44.64#ibcon#*before return 0, iclass 14, count 2 2006.280.08:24:44.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:44.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.280.08:24:44.64#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.280.08:24:44.64#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:44.64#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:44.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:44.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:44.77#ibcon#enter wrdev, iclass 14, count 0 2006.280.08:24:44.77#ibcon#first serial, iclass 14, count 0 2006.280.08:24:44.77#ibcon#enter sib2, iclass 14, count 0 2006.280.08:24:44.77#ibcon#flushed, iclass 14, count 0 2006.280.08:24:44.77#ibcon#about to write, iclass 14, count 0 2006.280.08:24:44.77#ibcon#wrote, iclass 14, count 0 2006.280.08:24:44.77#ibcon#about to read 3, iclass 14, count 0 2006.280.08:24:44.78#ibcon#read 3, iclass 14, count 0 2006.280.08:24:44.78#ibcon#about to read 4, iclass 14, count 0 2006.280.08:24:44.78#ibcon#read 4, iclass 14, count 0 2006.280.08:24:44.78#ibcon#about to read 5, iclass 14, count 0 2006.280.08:24:44.78#ibcon#read 5, iclass 14, count 0 2006.280.08:24:44.78#ibcon#about to read 6, iclass 14, count 0 2006.280.08:24:44.78#ibcon#read 6, iclass 14, count 0 2006.280.08:24:44.78#ibcon#end of sib2, iclass 14, count 0 2006.280.08:24:44.78#ibcon#*mode == 0, iclass 14, count 0 2006.280.08:24:44.78#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.280.08:24:44.78#ibcon#[27=USB\r\n] 2006.280.08:24:44.78#ibcon#*before write, iclass 14, count 0 2006.280.08:24:44.78#ibcon#enter sib2, iclass 14, count 0 2006.280.08:24:44.78#ibcon#flushed, iclass 14, count 0 2006.280.08:24:44.78#ibcon#about to write, iclass 14, count 0 2006.280.08:24:44.78#ibcon#wrote, iclass 14, count 0 2006.280.08:24:44.78#ibcon#about to read 3, iclass 14, count 0 2006.280.08:24:44.81#ibcon#read 3, iclass 14, count 0 2006.280.08:24:44.81#ibcon#about to read 4, iclass 14, count 0 2006.280.08:24:44.81#ibcon#read 4, iclass 14, count 0 2006.280.08:24:44.81#ibcon#about to read 5, iclass 14, count 0 2006.280.08:24:44.81#ibcon#read 5, iclass 14, count 0 2006.280.08:24:44.81#ibcon#about to read 6, iclass 14, count 0 2006.280.08:24:44.81#ibcon#read 6, iclass 14, count 0 2006.280.08:24:44.81#ibcon#end of sib2, iclass 14, count 0 2006.280.08:24:44.81#ibcon#*after write, iclass 14, count 0 2006.280.08:24:44.81#ibcon#*before return 0, iclass 14, count 0 2006.280.08:24:44.81#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:44.81#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.280.08:24:44.81#ibcon#about to clear, iclass 14 cls_cnt 0 2006.280.08:24:44.81#ibcon#cleared, iclass 14 cls_cnt 0 2006.280.08:24:44.81$vc4f8/vblo=4,712.99 2006.280.08:24:44.81#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.280.08:24:44.81#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.280.08:24:44.81#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:44.81#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:44.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:44.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:44.81#ibcon#enter wrdev, iclass 16, count 0 2006.280.08:24:44.81#ibcon#first serial, iclass 16, count 0 2006.280.08:24:44.81#ibcon#enter sib2, iclass 16, count 0 2006.280.08:24:44.81#ibcon#flushed, iclass 16, count 0 2006.280.08:24:44.81#ibcon#about to write, iclass 16, count 0 2006.280.08:24:44.81#ibcon#wrote, iclass 16, count 0 2006.280.08:24:44.81#ibcon#about to read 3, iclass 16, count 0 2006.280.08:24:44.83#ibcon#read 3, iclass 16, count 0 2006.280.08:24:44.83#ibcon#about to read 4, iclass 16, count 0 2006.280.08:24:44.83#ibcon#read 4, iclass 16, count 0 2006.280.08:24:44.83#ibcon#about to read 5, iclass 16, count 0 2006.280.08:24:44.83#ibcon#read 5, iclass 16, count 0 2006.280.08:24:44.83#ibcon#about to read 6, iclass 16, count 0 2006.280.08:24:44.83#ibcon#read 6, iclass 16, count 0 2006.280.08:24:44.83#ibcon#end of sib2, iclass 16, count 0 2006.280.08:24:44.83#ibcon#*mode == 0, iclass 16, count 0 2006.280.08:24:44.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.280.08:24:44.83#ibcon#[28=FRQ=04,712.99\r\n] 2006.280.08:24:44.83#ibcon#*before write, iclass 16, count 0 2006.280.08:24:44.83#ibcon#enter sib2, iclass 16, count 0 2006.280.08:24:44.83#ibcon#flushed, iclass 16, count 0 2006.280.08:24:44.83#ibcon#about to write, iclass 16, count 0 2006.280.08:24:44.83#ibcon#wrote, iclass 16, count 0 2006.280.08:24:44.83#ibcon#about to read 3, iclass 16, count 0 2006.280.08:24:44.87#ibcon#read 3, iclass 16, count 0 2006.280.08:24:44.87#ibcon#about to read 4, iclass 16, count 0 2006.280.08:24:44.87#ibcon#read 4, iclass 16, count 0 2006.280.08:24:44.87#ibcon#about to read 5, iclass 16, count 0 2006.280.08:24:44.87#ibcon#read 5, iclass 16, count 0 2006.280.08:24:44.87#ibcon#about to read 6, iclass 16, count 0 2006.280.08:24:44.87#ibcon#read 6, iclass 16, count 0 2006.280.08:24:44.87#ibcon#end of sib2, iclass 16, count 0 2006.280.08:24:44.87#ibcon#*after write, iclass 16, count 0 2006.280.08:24:44.87#ibcon#*before return 0, iclass 16, count 0 2006.280.08:24:44.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:44.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.280.08:24:44.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.280.08:24:44.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.280.08:24:44.87$vc4f8/vb=4,4 2006.280.08:24:44.87#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.280.08:24:44.87#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.280.08:24:44.87#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:44.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:44.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:44.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:44.93#ibcon#enter wrdev, iclass 18, count 2 2006.280.08:24:44.93#ibcon#first serial, iclass 18, count 2 2006.280.08:24:44.93#ibcon#enter sib2, iclass 18, count 2 2006.280.08:24:44.93#ibcon#flushed, iclass 18, count 2 2006.280.08:24:44.93#ibcon#about to write, iclass 18, count 2 2006.280.08:24:44.93#ibcon#wrote, iclass 18, count 2 2006.280.08:24:44.93#ibcon#about to read 3, iclass 18, count 2 2006.280.08:24:44.95#ibcon#read 3, iclass 18, count 2 2006.280.08:24:44.95#ibcon#about to read 4, iclass 18, count 2 2006.280.08:24:44.95#ibcon#read 4, iclass 18, count 2 2006.280.08:24:44.95#ibcon#about to read 5, iclass 18, count 2 2006.280.08:24:44.95#ibcon#read 5, iclass 18, count 2 2006.280.08:24:44.95#ibcon#about to read 6, iclass 18, count 2 2006.280.08:24:44.95#ibcon#read 6, iclass 18, count 2 2006.280.08:24:44.95#ibcon#end of sib2, iclass 18, count 2 2006.280.08:24:44.95#ibcon#*mode == 0, iclass 18, count 2 2006.280.08:24:44.95#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.280.08:24:44.95#ibcon#[27=AT04-04\r\n] 2006.280.08:24:44.95#ibcon#*before write, iclass 18, count 2 2006.280.08:24:44.95#ibcon#enter sib2, iclass 18, count 2 2006.280.08:24:44.95#ibcon#flushed, iclass 18, count 2 2006.280.08:24:44.95#ibcon#about to write, iclass 18, count 2 2006.280.08:24:44.95#ibcon#wrote, iclass 18, count 2 2006.280.08:24:44.95#ibcon#about to read 3, iclass 18, count 2 2006.280.08:24:44.98#ibcon#read 3, iclass 18, count 2 2006.280.08:24:44.98#ibcon#about to read 4, iclass 18, count 2 2006.280.08:24:44.98#ibcon#read 4, iclass 18, count 2 2006.280.08:24:44.98#ibcon#about to read 5, iclass 18, count 2 2006.280.08:24:44.98#ibcon#read 5, iclass 18, count 2 2006.280.08:24:44.98#ibcon#about to read 6, iclass 18, count 2 2006.280.08:24:44.98#ibcon#read 6, iclass 18, count 2 2006.280.08:24:44.98#ibcon#end of sib2, iclass 18, count 2 2006.280.08:24:44.98#ibcon#*after write, iclass 18, count 2 2006.280.08:24:44.98#ibcon#*before return 0, iclass 18, count 2 2006.280.08:24:44.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:44.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.280.08:24:44.98#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.280.08:24:44.98#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:44.98#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:45.10#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:45.10#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:45.10#ibcon#enter wrdev, iclass 18, count 0 2006.280.08:24:45.10#ibcon#first serial, iclass 18, count 0 2006.280.08:24:45.10#ibcon#enter sib2, iclass 18, count 0 2006.280.08:24:45.10#ibcon#flushed, iclass 18, count 0 2006.280.08:24:45.10#ibcon#about to write, iclass 18, count 0 2006.280.08:24:45.10#ibcon#wrote, iclass 18, count 0 2006.280.08:24:45.10#ibcon#about to read 3, iclass 18, count 0 2006.280.08:24:45.12#ibcon#read 3, iclass 18, count 0 2006.280.08:24:45.12#ibcon#about to read 4, iclass 18, count 0 2006.280.08:24:45.12#ibcon#read 4, iclass 18, count 0 2006.280.08:24:45.12#ibcon#about to read 5, iclass 18, count 0 2006.280.08:24:45.12#ibcon#read 5, iclass 18, count 0 2006.280.08:24:45.12#ibcon#about to read 6, iclass 18, count 0 2006.280.08:24:45.12#ibcon#read 6, iclass 18, count 0 2006.280.08:24:45.12#ibcon#end of sib2, iclass 18, count 0 2006.280.08:24:45.12#ibcon#*mode == 0, iclass 18, count 0 2006.280.08:24:45.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.280.08:24:45.12#ibcon#[27=USB\r\n] 2006.280.08:24:45.12#ibcon#*before write, iclass 18, count 0 2006.280.08:24:45.12#ibcon#enter sib2, iclass 18, count 0 2006.280.08:24:45.12#ibcon#flushed, iclass 18, count 0 2006.280.08:24:45.12#ibcon#about to write, iclass 18, count 0 2006.280.08:24:45.12#ibcon#wrote, iclass 18, count 0 2006.280.08:24:45.12#ibcon#about to read 3, iclass 18, count 0 2006.280.08:24:45.15#ibcon#read 3, iclass 18, count 0 2006.280.08:24:45.15#ibcon#about to read 4, iclass 18, count 0 2006.280.08:24:45.15#ibcon#read 4, iclass 18, count 0 2006.280.08:24:45.15#ibcon#about to read 5, iclass 18, count 0 2006.280.08:24:45.15#ibcon#read 5, iclass 18, count 0 2006.280.08:24:45.15#ibcon#about to read 6, iclass 18, count 0 2006.280.08:24:45.15#ibcon#read 6, iclass 18, count 0 2006.280.08:24:45.15#ibcon#end of sib2, iclass 18, count 0 2006.280.08:24:45.15#ibcon#*after write, iclass 18, count 0 2006.280.08:24:45.15#ibcon#*before return 0, iclass 18, count 0 2006.280.08:24:45.15#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:45.15#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.280.08:24:45.15#ibcon#about to clear, iclass 18 cls_cnt 0 2006.280.08:24:45.15#ibcon#cleared, iclass 18 cls_cnt 0 2006.280.08:24:45.15$vc4f8/vblo=5,744.99 2006.280.08:24:45.15#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.280.08:24:45.15#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.280.08:24:45.15#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:45.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:45.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:45.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:45.15#ibcon#enter wrdev, iclass 20, count 0 2006.280.08:24:45.15#ibcon#first serial, iclass 20, count 0 2006.280.08:24:45.15#ibcon#enter sib2, iclass 20, count 0 2006.280.08:24:45.15#ibcon#flushed, iclass 20, count 0 2006.280.08:24:45.15#ibcon#about to write, iclass 20, count 0 2006.280.08:24:45.15#ibcon#wrote, iclass 20, count 0 2006.280.08:24:45.15#ibcon#about to read 3, iclass 20, count 0 2006.280.08:24:45.17#ibcon#read 3, iclass 20, count 0 2006.280.08:24:45.17#ibcon#about to read 4, iclass 20, count 0 2006.280.08:24:45.17#ibcon#read 4, iclass 20, count 0 2006.280.08:24:45.17#ibcon#about to read 5, iclass 20, count 0 2006.280.08:24:45.17#ibcon#read 5, iclass 20, count 0 2006.280.08:24:45.17#ibcon#about to read 6, iclass 20, count 0 2006.280.08:24:45.17#ibcon#read 6, iclass 20, count 0 2006.280.08:24:45.17#ibcon#end of sib2, iclass 20, count 0 2006.280.08:24:45.17#ibcon#*mode == 0, iclass 20, count 0 2006.280.08:24:45.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.280.08:24:45.17#ibcon#[28=FRQ=05,744.99\r\n] 2006.280.08:24:45.17#ibcon#*before write, iclass 20, count 0 2006.280.08:24:45.17#ibcon#enter sib2, iclass 20, count 0 2006.280.08:24:45.17#ibcon#flushed, iclass 20, count 0 2006.280.08:24:45.17#ibcon#about to write, iclass 20, count 0 2006.280.08:24:45.17#ibcon#wrote, iclass 20, count 0 2006.280.08:24:45.17#ibcon#about to read 3, iclass 20, count 0 2006.280.08:24:45.21#ibcon#read 3, iclass 20, count 0 2006.280.08:24:45.21#ibcon#about to read 4, iclass 20, count 0 2006.280.08:24:45.21#ibcon#read 4, iclass 20, count 0 2006.280.08:24:45.21#ibcon#about to read 5, iclass 20, count 0 2006.280.08:24:45.21#ibcon#read 5, iclass 20, count 0 2006.280.08:24:45.21#ibcon#about to read 6, iclass 20, count 0 2006.280.08:24:45.21#ibcon#read 6, iclass 20, count 0 2006.280.08:24:45.21#ibcon#end of sib2, iclass 20, count 0 2006.280.08:24:45.21#ibcon#*after write, iclass 20, count 0 2006.280.08:24:45.21#ibcon#*before return 0, iclass 20, count 0 2006.280.08:24:45.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:45.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.280.08:24:45.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.280.08:24:45.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.280.08:24:45.21$vc4f8/vb=5,4 2006.280.08:24:45.21#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.280.08:24:45.21#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.280.08:24:45.21#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:45.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:45.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:45.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:45.27#ibcon#enter wrdev, iclass 22, count 2 2006.280.08:24:45.27#ibcon#first serial, iclass 22, count 2 2006.280.08:24:45.27#ibcon#enter sib2, iclass 22, count 2 2006.280.08:24:45.27#ibcon#flushed, iclass 22, count 2 2006.280.08:24:45.27#ibcon#about to write, iclass 22, count 2 2006.280.08:24:45.27#ibcon#wrote, iclass 22, count 2 2006.280.08:24:45.27#ibcon#about to read 3, iclass 22, count 2 2006.280.08:24:45.29#ibcon#read 3, iclass 22, count 2 2006.280.08:24:45.29#ibcon#about to read 4, iclass 22, count 2 2006.280.08:24:45.29#ibcon#read 4, iclass 22, count 2 2006.280.08:24:45.29#ibcon#about to read 5, iclass 22, count 2 2006.280.08:24:45.29#ibcon#read 5, iclass 22, count 2 2006.280.08:24:45.29#ibcon#about to read 6, iclass 22, count 2 2006.280.08:24:45.29#ibcon#read 6, iclass 22, count 2 2006.280.08:24:45.29#ibcon#end of sib2, iclass 22, count 2 2006.280.08:24:45.29#ibcon#*mode == 0, iclass 22, count 2 2006.280.08:24:45.29#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.280.08:24:45.29#ibcon#[27=AT05-04\r\n] 2006.280.08:24:45.29#ibcon#*before write, iclass 22, count 2 2006.280.08:24:45.29#ibcon#enter sib2, iclass 22, count 2 2006.280.08:24:45.29#ibcon#flushed, iclass 22, count 2 2006.280.08:24:45.29#ibcon#about to write, iclass 22, count 2 2006.280.08:24:45.29#ibcon#wrote, iclass 22, count 2 2006.280.08:24:45.29#ibcon#about to read 3, iclass 22, count 2 2006.280.08:24:45.32#ibcon#read 3, iclass 22, count 2 2006.280.08:24:45.32#ibcon#about to read 4, iclass 22, count 2 2006.280.08:24:45.32#ibcon#read 4, iclass 22, count 2 2006.280.08:24:45.32#ibcon#about to read 5, iclass 22, count 2 2006.280.08:24:45.32#ibcon#read 5, iclass 22, count 2 2006.280.08:24:45.32#ibcon#about to read 6, iclass 22, count 2 2006.280.08:24:45.32#ibcon#read 6, iclass 22, count 2 2006.280.08:24:45.32#ibcon#end of sib2, iclass 22, count 2 2006.280.08:24:45.32#ibcon#*after write, iclass 22, count 2 2006.280.08:24:45.32#ibcon#*before return 0, iclass 22, count 2 2006.280.08:24:45.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:45.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.280.08:24:45.32#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.280.08:24:45.32#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:45.32#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:45.44#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:45.44#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:45.44#ibcon#enter wrdev, iclass 22, count 0 2006.280.08:24:45.44#ibcon#first serial, iclass 22, count 0 2006.280.08:24:45.44#ibcon#enter sib2, iclass 22, count 0 2006.280.08:24:45.44#ibcon#flushed, iclass 22, count 0 2006.280.08:24:45.44#ibcon#about to write, iclass 22, count 0 2006.280.08:24:45.44#ibcon#wrote, iclass 22, count 0 2006.280.08:24:45.44#ibcon#about to read 3, iclass 22, count 0 2006.280.08:24:45.46#ibcon#read 3, iclass 22, count 0 2006.280.08:24:45.46#ibcon#about to read 4, iclass 22, count 0 2006.280.08:24:45.46#ibcon#read 4, iclass 22, count 0 2006.280.08:24:45.46#ibcon#about to read 5, iclass 22, count 0 2006.280.08:24:45.46#ibcon#read 5, iclass 22, count 0 2006.280.08:24:45.46#ibcon#about to read 6, iclass 22, count 0 2006.280.08:24:45.46#ibcon#read 6, iclass 22, count 0 2006.280.08:24:45.46#ibcon#end of sib2, iclass 22, count 0 2006.280.08:24:45.46#ibcon#*mode == 0, iclass 22, count 0 2006.280.08:24:45.46#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.280.08:24:45.46#ibcon#[27=USB\r\n] 2006.280.08:24:45.46#ibcon#*before write, iclass 22, count 0 2006.280.08:24:45.46#ibcon#enter sib2, iclass 22, count 0 2006.280.08:24:45.46#ibcon#flushed, iclass 22, count 0 2006.280.08:24:45.46#ibcon#about to write, iclass 22, count 0 2006.280.08:24:45.46#ibcon#wrote, iclass 22, count 0 2006.280.08:24:45.46#ibcon#about to read 3, iclass 22, count 0 2006.280.08:24:45.49#ibcon#read 3, iclass 22, count 0 2006.280.08:24:45.49#ibcon#about to read 4, iclass 22, count 0 2006.280.08:24:45.49#ibcon#read 4, iclass 22, count 0 2006.280.08:24:45.49#ibcon#about to read 5, iclass 22, count 0 2006.280.08:24:45.49#ibcon#read 5, iclass 22, count 0 2006.280.08:24:45.49#ibcon#about to read 6, iclass 22, count 0 2006.280.08:24:45.49#ibcon#read 6, iclass 22, count 0 2006.280.08:24:45.49#ibcon#end of sib2, iclass 22, count 0 2006.280.08:24:45.49#ibcon#*after write, iclass 22, count 0 2006.280.08:24:45.49#ibcon#*before return 0, iclass 22, count 0 2006.280.08:24:45.49#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:45.49#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.280.08:24:45.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.280.08:24:45.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.280.08:24:45.49$vc4f8/vblo=6,752.99 2006.280.08:24:45.49#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.280.08:24:45.49#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.280.08:24:45.49#ibcon#ireg 17 cls_cnt 0 2006.280.08:24:45.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:45.49#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:45.49#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:45.49#ibcon#enter wrdev, iclass 24, count 0 2006.280.08:24:45.49#ibcon#first serial, iclass 24, count 0 2006.280.08:24:45.49#ibcon#enter sib2, iclass 24, count 0 2006.280.08:24:45.49#ibcon#flushed, iclass 24, count 0 2006.280.08:24:45.49#ibcon#about to write, iclass 24, count 0 2006.280.08:24:45.49#ibcon#wrote, iclass 24, count 0 2006.280.08:24:45.49#ibcon#about to read 3, iclass 24, count 0 2006.280.08:24:45.51#ibcon#read 3, iclass 24, count 0 2006.280.08:24:45.51#ibcon#about to read 4, iclass 24, count 0 2006.280.08:24:45.51#ibcon#read 4, iclass 24, count 0 2006.280.08:24:45.51#ibcon#about to read 5, iclass 24, count 0 2006.280.08:24:45.51#ibcon#read 5, iclass 24, count 0 2006.280.08:24:45.51#ibcon#about to read 6, iclass 24, count 0 2006.280.08:24:45.51#ibcon#read 6, iclass 24, count 0 2006.280.08:24:45.51#ibcon#end of sib2, iclass 24, count 0 2006.280.08:24:45.51#ibcon#*mode == 0, iclass 24, count 0 2006.280.08:24:45.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.280.08:24:45.54#ibcon#[28=FRQ=06,752.99\r\n] 2006.280.08:24:45.54#ibcon#*before write, iclass 24, count 0 2006.280.08:24:45.54#ibcon#enter sib2, iclass 24, count 0 2006.280.08:24:45.54#ibcon#flushed, iclass 24, count 0 2006.280.08:24:45.54#ibcon#about to write, iclass 24, count 0 2006.280.08:24:45.54#ibcon#wrote, iclass 24, count 0 2006.280.08:24:45.54#ibcon#about to read 3, iclass 24, count 0 2006.280.08:24:45.57#ibcon#read 3, iclass 24, count 0 2006.280.08:24:45.57#ibcon#about to read 4, iclass 24, count 0 2006.280.08:24:45.57#ibcon#read 4, iclass 24, count 0 2006.280.08:24:45.57#ibcon#about to read 5, iclass 24, count 0 2006.280.08:24:45.57#ibcon#read 5, iclass 24, count 0 2006.280.08:24:45.57#ibcon#about to read 6, iclass 24, count 0 2006.280.08:24:45.57#ibcon#read 6, iclass 24, count 0 2006.280.08:24:45.57#ibcon#end of sib2, iclass 24, count 0 2006.280.08:24:45.57#ibcon#*after write, iclass 24, count 0 2006.280.08:24:45.57#ibcon#*before return 0, iclass 24, count 0 2006.280.08:24:45.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:45.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.280.08:24:45.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.280.08:24:45.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.280.08:24:45.57$vc4f8/vb=6,4 2006.280.08:24:45.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.280.08:24:45.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.280.08:24:45.57#ibcon#ireg 11 cls_cnt 2 2006.280.08:24:45.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:45.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:45.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:45.61#ibcon#enter wrdev, iclass 26, count 2 2006.280.08:24:45.61#ibcon#first serial, iclass 26, count 2 2006.280.08:24:45.61#ibcon#enter sib2, iclass 26, count 2 2006.280.08:24:45.61#ibcon#flushed, iclass 26, count 2 2006.280.08:24:45.61#ibcon#about to write, iclass 26, count 2 2006.280.08:24:45.61#ibcon#wrote, iclass 26, count 2 2006.280.08:24:45.61#ibcon#about to read 3, iclass 26, count 2 2006.280.08:24:45.63#ibcon#read 3, iclass 26, count 2 2006.280.08:24:45.63#ibcon#about to read 4, iclass 26, count 2 2006.280.08:24:45.63#ibcon#read 4, iclass 26, count 2 2006.280.08:24:45.63#ibcon#about to read 5, iclass 26, count 2 2006.280.08:24:45.63#ibcon#read 5, iclass 26, count 2 2006.280.08:24:45.63#ibcon#about to read 6, iclass 26, count 2 2006.280.08:24:45.63#ibcon#read 6, iclass 26, count 2 2006.280.08:24:45.63#ibcon#end of sib2, iclass 26, count 2 2006.280.08:24:45.63#ibcon#*mode == 0, iclass 26, count 2 2006.280.08:24:45.63#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.280.08:24:45.63#ibcon#[27=AT06-04\r\n] 2006.280.08:24:45.63#ibcon#*before write, iclass 26, count 2 2006.280.08:24:45.63#ibcon#enter sib2, iclass 26, count 2 2006.280.08:24:45.63#ibcon#flushed, iclass 26, count 2 2006.280.08:24:45.63#ibcon#about to write, iclass 26, count 2 2006.280.08:24:45.63#ibcon#wrote, iclass 26, count 2 2006.280.08:24:45.63#ibcon#about to read 3, iclass 26, count 2 2006.280.08:24:45.66#ibcon#read 3, iclass 26, count 2 2006.280.08:24:45.66#ibcon#about to read 4, iclass 26, count 2 2006.280.08:24:45.66#ibcon#read 4, iclass 26, count 2 2006.280.08:24:45.66#ibcon#about to read 5, iclass 26, count 2 2006.280.08:24:45.66#ibcon#read 5, iclass 26, count 2 2006.280.08:24:45.66#ibcon#about to read 6, iclass 26, count 2 2006.280.08:24:45.66#ibcon#read 6, iclass 26, count 2 2006.280.08:24:45.66#ibcon#end of sib2, iclass 26, count 2 2006.280.08:24:45.66#ibcon#*after write, iclass 26, count 2 2006.280.08:24:45.66#ibcon#*before return 0, iclass 26, count 2 2006.280.08:24:45.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:45.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.280.08:24:45.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.280.08:24:45.66#ibcon#ireg 7 cls_cnt 0 2006.280.08:24:45.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:45.78#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:45.78#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:45.78#ibcon#enter wrdev, iclass 26, count 0 2006.280.08:24:45.78#ibcon#first serial, iclass 26, count 0 2006.280.08:24:45.78#ibcon#enter sib2, iclass 26, count 0 2006.280.08:24:45.78#ibcon#flushed, iclass 26, count 0 2006.280.08:24:45.78#ibcon#about to write, iclass 26, count 0 2006.280.08:24:45.78#ibcon#wrote, iclass 26, count 0 2006.280.08:24:45.78#ibcon#about to read 3, iclass 26, count 0 2006.280.08:24:45.80#ibcon#read 3, iclass 26, count 0 2006.280.08:24:45.80#ibcon#about to read 4, iclass 26, count 0 2006.280.08:24:45.80#ibcon#read 4, iclass 26, count 0 2006.280.08:24:45.80#ibcon#about to read 5, iclass 26, count 0 2006.280.08:24:45.80#ibcon#read 5, iclass 26, count 0 2006.280.08:24:45.80#ibcon#about to read 6, iclass 26, count 0 2006.280.08:24:45.80#ibcon#read 6, iclass 26, count 0 2006.280.08:24:45.80#ibcon#end of sib2, iclass 26, count 0 2006.280.08:24:45.80#ibcon#*mode == 0, iclass 26, count 0 2006.280.08:24:45.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.280.08:24:45.80#ibcon#[27=USB\r\n] 2006.280.08:24:45.80#ibcon#*before write, iclass 26, count 0 2006.280.08:24:45.80#ibcon#enter sib2, iclass 26, count 0 2006.280.08:24:45.80#ibcon#flushed, iclass 26, count 0 2006.280.08:24:45.80#ibcon#about to write, iclass 26, count 0 2006.280.08:24:45.80#ibcon#wrote, iclass 26, count 0 2006.280.08:24:45.80#ibcon#about to read 3, iclass 26, count 0 2006.280.08:24:45.83#ibcon#read 3, iclass 26, count 0 2006.280.08:24:45.83#ibcon#about to read 4, iclass 26, count 0 2006.280.08:24:45.83#ibcon#read 4, iclass 26, count 0 2006.280.08:24:45.83#ibcon#about to read 5, iclass 26, count 0 2006.280.08:24:45.83#ibcon#read 5, iclass 26, count 0 2006.280.08:24:45.83#ibcon#about to read 6, iclass 26, count 0 2006.280.08:24:45.83#ibcon#read 6, iclass 26, count 0 2006.280.08:24:45.83#ibcon#end of sib2, iclass 26, count 0 2006.280.08:24:45.83#ibcon#*after write, iclass 26, count 0 2006.280.08:24:45.83#ibcon#*before return 0, iclass 26, count 0 2006.280.08:24:45.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:45.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.280.08:24:45.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.280.08:24:45.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.280.08:24:45.83$vc4f8/vabw=wide 2006.280.08:24:45.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.280.08:24:45.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.280.08:24:45.83#ibcon#ireg 8 cls_cnt 0 2006.280.08:24:45.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:45.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:45.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:45.83#ibcon#enter wrdev, iclass 28, count 0 2006.280.08:24:45.83#ibcon#first serial, iclass 28, count 0 2006.280.08:24:45.83#ibcon#enter sib2, iclass 28, count 0 2006.280.08:24:45.83#ibcon#flushed, iclass 28, count 0 2006.280.08:24:45.83#ibcon#about to write, iclass 28, count 0 2006.280.08:24:45.83#ibcon#wrote, iclass 28, count 0 2006.280.08:24:45.83#ibcon#about to read 3, iclass 28, count 0 2006.280.08:24:45.85#ibcon#read 3, iclass 28, count 0 2006.280.08:24:45.85#ibcon#about to read 4, iclass 28, count 0 2006.280.08:24:45.85#ibcon#read 4, iclass 28, count 0 2006.280.08:24:45.85#ibcon#about to read 5, iclass 28, count 0 2006.280.08:24:45.85#ibcon#read 5, iclass 28, count 0 2006.280.08:24:45.85#ibcon#about to read 6, iclass 28, count 0 2006.280.08:24:45.85#ibcon#read 6, iclass 28, count 0 2006.280.08:24:45.85#ibcon#end of sib2, iclass 28, count 0 2006.280.08:24:45.85#ibcon#*mode == 0, iclass 28, count 0 2006.280.08:24:45.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.280.08:24:45.85#ibcon#[25=BW32\r\n] 2006.280.08:24:45.85#ibcon#*before write, iclass 28, count 0 2006.280.08:24:45.85#ibcon#enter sib2, iclass 28, count 0 2006.280.08:24:45.85#ibcon#flushed, iclass 28, count 0 2006.280.08:24:45.85#ibcon#about to write, iclass 28, count 0 2006.280.08:24:45.85#ibcon#wrote, iclass 28, count 0 2006.280.08:24:45.85#ibcon#about to read 3, iclass 28, count 0 2006.280.08:24:45.88#ibcon#read 3, iclass 28, count 0 2006.280.08:24:45.88#ibcon#about to read 4, iclass 28, count 0 2006.280.08:24:45.88#ibcon#read 4, iclass 28, count 0 2006.280.08:24:45.88#ibcon#about to read 5, iclass 28, count 0 2006.280.08:24:45.88#ibcon#read 5, iclass 28, count 0 2006.280.08:24:45.88#ibcon#about to read 6, iclass 28, count 0 2006.280.08:24:45.88#ibcon#read 6, iclass 28, count 0 2006.280.08:24:45.88#ibcon#end of sib2, iclass 28, count 0 2006.280.08:24:45.88#ibcon#*after write, iclass 28, count 0 2006.280.08:24:45.88#ibcon#*before return 0, iclass 28, count 0 2006.280.08:24:45.88#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:45.88#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.280.08:24:45.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.280.08:24:45.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.280.08:24:45.88$vc4f8/vbbw=wide 2006.280.08:24:45.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.280.08:24:45.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.280.08:24:45.88#ibcon#ireg 8 cls_cnt 0 2006.280.08:24:45.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:24:45.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:24:45.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:24:45.95#ibcon#enter wrdev, iclass 30, count 0 2006.280.08:24:45.95#ibcon#first serial, iclass 30, count 0 2006.280.08:24:45.95#ibcon#enter sib2, iclass 30, count 0 2006.280.08:24:45.95#ibcon#flushed, iclass 30, count 0 2006.280.08:24:45.95#ibcon#about to write, iclass 30, count 0 2006.280.08:24:45.95#ibcon#wrote, iclass 30, count 0 2006.280.08:24:45.95#ibcon#about to read 3, iclass 30, count 0 2006.280.08:24:45.97#ibcon#read 3, iclass 30, count 0 2006.280.08:24:45.97#ibcon#about to read 4, iclass 30, count 0 2006.280.08:24:45.97#ibcon#read 4, iclass 30, count 0 2006.280.08:24:45.97#ibcon#about to read 5, iclass 30, count 0 2006.280.08:24:45.97#ibcon#read 5, iclass 30, count 0 2006.280.08:24:45.97#ibcon#about to read 6, iclass 30, count 0 2006.280.08:24:45.97#ibcon#read 6, iclass 30, count 0 2006.280.08:24:45.97#ibcon#end of sib2, iclass 30, count 0 2006.280.08:24:45.97#ibcon#*mode == 0, iclass 30, count 0 2006.280.08:24:45.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.280.08:24:45.97#ibcon#[27=BW32\r\n] 2006.280.08:24:45.97#ibcon#*before write, iclass 30, count 0 2006.280.08:24:45.97#ibcon#enter sib2, iclass 30, count 0 2006.280.08:24:45.97#ibcon#flushed, iclass 30, count 0 2006.280.08:24:45.97#ibcon#about to write, iclass 30, count 0 2006.280.08:24:45.97#ibcon#wrote, iclass 30, count 0 2006.280.08:24:45.97#ibcon#about to read 3, iclass 30, count 0 2006.280.08:24:46.00#ibcon#read 3, iclass 30, count 0 2006.280.08:24:46.00#ibcon#about to read 4, iclass 30, count 0 2006.280.08:24:46.00#ibcon#read 4, iclass 30, count 0 2006.280.08:24:46.00#ibcon#about to read 5, iclass 30, count 0 2006.280.08:24:46.00#ibcon#read 5, iclass 30, count 0 2006.280.08:24:46.00#ibcon#about to read 6, iclass 30, count 0 2006.280.08:24:46.00#ibcon#read 6, iclass 30, count 0 2006.280.08:24:46.00#ibcon#end of sib2, iclass 30, count 0 2006.280.08:24:46.00#ibcon#*after write, iclass 30, count 0 2006.280.08:24:46.00#ibcon#*before return 0, iclass 30, count 0 2006.280.08:24:46.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:24:46.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.280.08:24:46.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.280.08:24:46.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.280.08:24:46.00$4f8m12a/ifd4f 2006.280.08:24:46.00$ifd4f/lo= 2006.280.08:24:46.00$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.280.08:24:46.00$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.280.08:24:46.00$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.280.08:24:46.00$ifd4f/patch= 2006.280.08:24:46.00$ifd4f/patch=lo1,a1,a2,a3,a4 2006.280.08:24:46.00$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.280.08:24:46.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.280.08:24:46.00$4f8m12a/"form=m,16.000,1:2 2006.280.08:24:46.00$4f8m12a/"tpicd 2006.280.08:24:46.00$4f8m12a/echo=off 2006.280.08:24:46.00$4f8m12a/xlog=off 2006.280.08:24:46.00:!2006.280.08:25:10 2006.280.08:24:48.14#trakl#Source acquired 2006.280.08:24:48.14#flagr#flagr/antenna,acquired 2006.280.08:25:10.01:preob 2006.280.08:25:11.13/onsource/TRACKING 2006.280.08:25:11.13:!2006.280.08:25:20 2006.280.08:25:20.00:data_valid=on 2006.280.08:25:20.00:midob 2006.280.08:25:20.13/onsource/TRACKING 2006.280.08:25:20.13/wx/20.17,987.6,61 2006.280.08:25:20.34/cable/+6.4846E-03 2006.280.08:25:21.43/va/01,07,usb,yes,34,36 2006.280.08:25:21.43/va/02,06,usb,yes,32,33 2006.280.08:25:21.43/va/03,06,usb,yes,30,30 2006.280.08:25:21.43/va/04,06,usb,yes,33,36 2006.280.08:25:21.43/va/05,07,usb,yes,32,34 2006.280.08:25:21.43/va/06,06,usb,yes,31,31 2006.280.08:25:21.43/va/07,06,usb,yes,31,31 2006.280.08:25:21.43/va/08,06,usb,yes,33,33 2006.280.08:25:21.66/valo/01,532.99,yes,locked 2006.280.08:25:21.66/valo/02,572.99,yes,locked 2006.280.08:25:21.66/valo/03,672.99,yes,locked 2006.280.08:25:21.66/valo/04,832.99,yes,locked 2006.280.08:25:21.66/valo/05,652.99,yes,locked 2006.280.08:25:21.66/valo/06,772.99,yes,locked 2006.280.08:25:21.66/valo/07,832.99,yes,locked 2006.280.08:25:21.66/valo/08,852.99,yes,locked 2006.280.08:25:22.75/vb/01,04,usb,yes,31,30 2006.280.08:25:22.75/vb/02,05,usb,yes,29,30 2006.280.08:25:22.75/vb/03,04,usb,yes,29,33 2006.280.08:25:22.75/vb/04,04,usb,yes,30,30 2006.280.08:25:22.75/vb/05,04,usb,yes,28,32 2006.280.08:25:22.75/vb/06,04,usb,yes,29,32 2006.280.08:25:22.75/vb/07,04,usb,yes,32,32 2006.280.08:25:22.75/vb/08,04,usb,yes,29,32 2006.280.08:25:22.98/vblo/01,632.99,yes,locked 2006.280.08:25:22.98/vblo/02,640.99,yes,locked 2006.280.08:25:22.98/vblo/03,656.99,yes,locked 2006.280.08:25:22.98/vblo/04,712.99,yes,locked 2006.280.08:25:22.98/vblo/05,744.99,yes,locked 2006.280.08:25:22.98/vblo/06,752.99,yes,locked 2006.280.08:25:22.98/vblo/07,734.99,yes,locked 2006.280.08:25:22.98/vblo/08,744.99,yes,locked 2006.280.08:25:23.13/vabw/8 2006.280.08:25:23.28/vbbw/8 2006.280.08:25:23.39/xfe/off,on,12.2 2006.280.08:25:23.76/ifatt/23,28,28,28 2006.280.08:25:24.08/fmout-gps/S +3.15E-07 2006.280.08:25:24.11:!2006.280.08:26:20 2006.280.08:26:20.01:data_valid=off 2006.280.08:26:20.02:postob 2006.280.08:26:20.11/cable/+6.4847E-03 2006.280.08:26:20.12/wx/20.15,987.7,62 2006.280.08:26:21.07/fmout-gps/S +3.14E-07 2006.280.08:26:21.08:checkk5last 2006.280.08:26:21.08&checkk5last/chk_obsdata=1 2006.280.08:26:21.08&checkk5last/chk_obsdata=2 2006.280.08:26:21.09&checkk5last/chk_obsdata=3 2006.280.08:26:21.09&checkk5last/chk_obsdata=4 2006.280.08:26:21.09&checkk5last/k5log=1 2006.280.08:26:21.10&checkk5last/k5log=2 2006.280.08:26:21.10&checkk5last/k5log=3 2006.280.08:26:21.10&checkk5last/k5log=4 2006.280.08:26:21.11&checkk5last/obsinfo 2006.280.08:26:21.54/chk_obsdata//k5ts1/T2800825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:26:22.00/chk_obsdata//k5ts2/T2800825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:26:22.44/chk_obsdata//k5ts3/T2800825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:26:23.09/chk_obsdata//k5ts4/T2800825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.280.08:26:24.24/k5log//k5ts1_log_newline 2006.280.08:26:25.48/k5log//k5ts2_log_newline 2006.280.08:26:27.10/k5log//k5ts3_log_newline 2006.280.08:26:28.12/k5log//k5ts4_log_newline 2006.280.08:26:28.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.280.08:26:28.15:"sched_end 2006.280.08:26:28.15:source=idle 2006.280.08:26:29.12:stow 2006.280.08:26:29.12&stow/source=idle 2006.280.08:26:29.12&stow/"this is stow command. 2006.280.08:26:29.12&stow/antenna=m3 2006.280.08:26:29.12#flagr#flagr/antenna,new-source 2006.280.08:26:32.01:!+10m 2006.280.08:36:32.02:standby 2006.280.08:36:32.02&standby/"this is standby command. 2006.280.08:36:32.02&standby/antenna=m0 2006.280.08:36:33.01:checkk5hdd 2006.280.08:36:33.01&checkk5hdd/chk_hdd=1 2006.280.08:36:33.01&checkk5hdd/chk_hdd=2 2006.280.08:36:33.01&checkk5hdd/chk_hdd=3 2006.280.08:36:33.01&checkk5hdd/chk_hdd=4 2006.280.08:36:37.76/chk_hdd//k5ts1/GSI00287:T280073000a.dat~T280082520a.dat[12873433088Byte] 2006.280.08:36:42.67/chk_hdd//k5ts2/GSI00184:T280073000b.dat~T280082520b.dat[12873433088Byte] 2006.280.08:36:47.18/chk_hdd//k5ts3/GSI00270:T280073000c.dat~T280082520c.dat[12873433088Byte] 2006.280.08:36:51.97/chk_hdd//k5ts4/GSI00242:T280073000d.dat~T280082520d.dat[12873433088Byte] 2006.280.08:36:51.97:sy=cp /usr2/log/k06280ts.log /usr2/log_backup/ 2006.280.08:36:52.06:log=k06281ts