2006.259.08:37:35.11:Log Opened: Mark IV Field System Version 9.7.7 2006.259.08:37:35.11:location,TSUKUB32,-140.09,36.10,61.0 2006.259.08:37:35.11:horizon1,0.,5.,360. 2006.259.08:37:35.12:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.259.08:37:35.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.259.08:37:35.12:drivev11,330,270,no 2006.259.08:37:35.13:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.259.08:37:35.13:drivev13,15.000,268,10.000,10.000,10.000 2006.259.08:37:35.14:drivev21,330,270,no 2006.259.08:37:35.14:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.259.08:37:35.14:drivev23,15.000,268,10.000,10.000,10.000 2006.259.08:37:35.19:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.259.08:37:35.19:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.259.08:37:35.20:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.259.08:37:35.20:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.259.08:37:35.21:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.259.08:37:35.21:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.259.08:37:35.21:time,-0.364,101.533,rate 2006.259.08:37:35.22:flagr,200 2006.259.08:37:35.22:proc=k06260ts 2006.259.08:37:35.22:" k06260 2006 tsukub32 t ts 2006.259.08:37:35.23:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.259.08:37:35.23:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.259.08:37:35.28:" 108 tsukub32 14 17400 2006.259.08:37:35.28:" drudg version 050216 compiled under fs 9.7.07 2006.259.08:37:35.29:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.259.08:37:35.29:!2006.260.06:29:50 2006.260.06:29:41.23?ERROR st -97 Trouble decoding pressure data 2006.260.06:29:41.23#wxget#04 2.7 5.6 23.67 841010.0 2006.260.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.260.06:29:50.02:!2006.260.07:19:50 2006.260.07:19:50.00:unstow 2006.260.07:19:50.00&unstow/antenna=e 2006.260.07:19:50.00&unstow/!+10s 2006.260.07:19:50.00&unstow/antenna=m2 2006.260.07:20:02.01:scan_name=260-0730,k06260,60 2006.260.07:20:02.01:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.260.07:20:02.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.260.07:20:02.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.260.07:20:02.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.260.07:20:02.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.260.07:20:02.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.260.07:20:02.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.260.07:20:03.14:ready_k5 2006.260.07:20:03.14&ready_k5/obsinfo=st 2006.260.07:20:03.14&ready_k5/autoobs=1 2006.260.07:20:03.14&ready_k5/autoobs=2 2006.260.07:20:03.14&ready_k5/autoobs=3 2006.260.07:20:03.14&ready_k5/autoobs=4 2006.260.07:20:03.14&ready_k5/obsinfo 2006.260.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.260.07:20:03.15#flagr#flagr/antenna,new-source 2006.260.07:20:06.89/autoobs//k5ts1/ autoobs started! 2006.260.07:20:10.48/autoobs//k5ts2/ autoobs started! 2006.260.07:20:14.17/autoobs//k5ts3/ autoobs started! 2006.260.07:20:17.78/autoobs//k5ts4/ autoobs started! 2006.260.07:20:17.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:20:17.81:4f8m12a=1 2006.260.07:20:17.81&4f8m12a/xlog=on 2006.260.07:20:17.81&4f8m12a/echo=on 2006.260.07:20:17.81&4f8m12a/pcalon 2006.260.07:20:17.81&4f8m12a/"tpicd=stop 2006.260.07:20:17.81&4f8m12a/vc4f8 2006.260.07:20:17.81&4f8m12a/ifd4f 2006.260.07:20:17.81&4f8m12a/"form=m,16.000,1:2 2006.260.07:20:17.81&4f8m12a/"tpicd 2006.260.07:20:17.81&4f8m12a/echo=off 2006.260.07:20:17.81&4f8m12a/xlog=off 2006.260.07:20:17.81$4f8m12a/echo=on 2006.260.07:20:17.81$4f8m12a/pcalon 2006.260.07:20:17.81&pcalon/"no phase cal control is implemented here 2006.260.07:20:17.81$pcalon/"no phase cal control is implemented here 2006.260.07:20:17.81$4f8m12a/"tpicd=stop 2006.260.07:20:17.81$4f8m12a/vc4f8 2006.260.07:20:17.81&vc4f8/valo=1,532.99 2006.260.07:20:17.81&vc4f8/va=1,8 2006.260.07:20:17.81&vc4f8/valo=2,572.99 2006.260.07:20:17.81&vc4f8/va=2,7 2006.260.07:20:17.81&vc4f8/valo=3,672.99 2006.260.07:20:17.81&vc4f8/va=3,8 2006.260.07:20:17.81&vc4f8/valo=4,832.99 2006.260.07:20:17.81&vc4f8/va=4,7 2006.260.07:20:17.81&vc4f8/valo=5,652.99 2006.260.07:20:17.81&vc4f8/va=5,7 2006.260.07:20:17.81&vc4f8/valo=6,772.99 2006.260.07:20:17.81&vc4f8/va=6,6 2006.260.07:20:17.81&vc4f8/valo=7,832.99 2006.260.07:20:17.81&vc4f8/va=7,6 2006.260.07:20:17.81&vc4f8/valo=8,852.99 2006.260.07:20:17.81&vc4f8/va=8,6 2006.260.07:20:17.81&vc4f8/vblo=1,632.99 2006.260.07:20:17.81&vc4f8/vb=1,4 2006.260.07:20:17.81&vc4f8/vblo=2,640.99 2006.260.07:20:17.81&vc4f8/vb=2,5 2006.260.07:20:17.81&vc4f8/vblo=3,656.99 2006.260.07:20:17.81&vc4f8/vb=3,4 2006.260.07:20:17.81&vc4f8/vblo=4,712.99 2006.260.07:20:17.81&vc4f8/vb=4,5 2006.260.07:20:17.81&vc4f8/vblo=5,744.99 2006.260.07:20:17.81&vc4f8/vb=5,4 2006.260.07:20:17.81&vc4f8/vblo=6,752.99 2006.260.07:20:17.81&vc4f8/vb=6,4 2006.260.07:20:17.81&vc4f8/vabw=wide 2006.260.07:20:17.81&vc4f8/vbbw=wide 2006.260.07:20:17.81$vc4f8/valo=1,532.99 2006.260.07:20:17.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:20:17.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:20:17.81#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:17.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:17.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:17.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:17.81#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:20:17.81#ibcon#first serial, iclass 30, count 0 2006.260.07:20:17.81#ibcon#enter sib2, iclass 30, count 0 2006.260.07:20:17.81#ibcon#flushed, iclass 30, count 0 2006.260.07:20:17.81#ibcon#about to write, iclass 30, count 0 2006.260.07:20:17.81#ibcon#wrote, iclass 30, count 0 2006.260.07:20:17.81#ibcon#about to read 3, iclass 30, count 0 2006.260.07:20:17.85#ibcon#read 3, iclass 30, count 0 2006.260.07:20:17.85#ibcon#about to read 4, iclass 30, count 0 2006.260.07:20:17.85#ibcon#read 4, iclass 30, count 0 2006.260.07:20:17.85#ibcon#about to read 5, iclass 30, count 0 2006.260.07:20:17.85#ibcon#read 5, iclass 30, count 0 2006.260.07:20:17.85#ibcon#about to read 6, iclass 30, count 0 2006.260.07:20:17.85#ibcon#read 6, iclass 30, count 0 2006.260.07:20:17.85#ibcon#end of sib2, iclass 30, count 0 2006.260.07:20:17.85#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:20:17.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:20:17.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:20:17.85#ibcon#*before write, iclass 30, count 0 2006.260.07:20:17.85#ibcon#enter sib2, iclass 30, count 0 2006.260.07:20:17.85#ibcon#flushed, iclass 30, count 0 2006.260.07:20:17.85#ibcon#about to write, iclass 30, count 0 2006.260.07:20:17.85#ibcon#wrote, iclass 30, count 0 2006.260.07:20:17.85#ibcon#about to read 3, iclass 30, count 0 2006.260.07:20:17.90#ibcon#read 3, iclass 30, count 0 2006.260.07:20:17.90#ibcon#about to read 4, iclass 30, count 0 2006.260.07:20:17.90#ibcon#read 4, iclass 30, count 0 2006.260.07:20:17.90#ibcon#about to read 5, iclass 30, count 0 2006.260.07:20:17.90#ibcon#read 5, iclass 30, count 0 2006.260.07:20:17.90#ibcon#about to read 6, iclass 30, count 0 2006.260.07:20:17.90#ibcon#read 6, iclass 30, count 0 2006.260.07:20:17.90#ibcon#end of sib2, iclass 30, count 0 2006.260.07:20:17.90#ibcon#*after write, iclass 30, count 0 2006.260.07:20:17.90#ibcon#*before return 0, iclass 30, count 0 2006.260.07:20:17.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:17.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:17.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:20:17.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:20:17.90$vc4f8/va=1,8 2006.260.07:20:17.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:20:17.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:20:17.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:17.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:17.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:17.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:17.90#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:20:17.90#ibcon#first serial, iclass 32, count 2 2006.260.07:20:17.90#ibcon#enter sib2, iclass 32, count 2 2006.260.07:20:17.90#ibcon#flushed, iclass 32, count 2 2006.260.07:20:17.90#ibcon#about to write, iclass 32, count 2 2006.260.07:20:17.90#ibcon#wrote, iclass 32, count 2 2006.260.07:20:17.90#ibcon#about to read 3, iclass 32, count 2 2006.260.07:20:17.93#ibcon#read 3, iclass 32, count 2 2006.260.07:20:17.93#ibcon#about to read 4, iclass 32, count 2 2006.260.07:20:17.93#ibcon#read 4, iclass 32, count 2 2006.260.07:20:17.93#ibcon#about to read 5, iclass 32, count 2 2006.260.07:20:17.93#ibcon#read 5, iclass 32, count 2 2006.260.07:20:17.93#ibcon#about to read 6, iclass 32, count 2 2006.260.07:20:17.93#ibcon#read 6, iclass 32, count 2 2006.260.07:20:17.93#ibcon#end of sib2, iclass 32, count 2 2006.260.07:20:17.93#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:20:17.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:20:17.93#ibcon#[25=AT01-08\r\n] 2006.260.07:20:17.93#ibcon#*before write, iclass 32, count 2 2006.260.07:20:17.93#ibcon#enter sib2, iclass 32, count 2 2006.260.07:20:17.93#ibcon#flushed, iclass 32, count 2 2006.260.07:20:17.93#ibcon#about to write, iclass 32, count 2 2006.260.07:20:17.93#ibcon#wrote, iclass 32, count 2 2006.260.07:20:17.93#ibcon#about to read 3, iclass 32, count 2 2006.260.07:20:17.96#ibcon#read 3, iclass 32, count 2 2006.260.07:20:17.96#ibcon#about to read 4, iclass 32, count 2 2006.260.07:20:17.96#ibcon#read 4, iclass 32, count 2 2006.260.07:20:17.96#ibcon#about to read 5, iclass 32, count 2 2006.260.07:20:17.96#ibcon#read 5, iclass 32, count 2 2006.260.07:20:17.96#ibcon#about to read 6, iclass 32, count 2 2006.260.07:20:17.96#ibcon#read 6, iclass 32, count 2 2006.260.07:20:17.96#ibcon#end of sib2, iclass 32, count 2 2006.260.07:20:17.96#ibcon#*after write, iclass 32, count 2 2006.260.07:20:17.96#ibcon#*before return 0, iclass 32, count 2 2006.260.07:20:17.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:17.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:17.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:20:17.96#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:17.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:18.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:18.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:18.08#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:20:18.08#ibcon#first serial, iclass 32, count 0 2006.260.07:20:18.08#ibcon#enter sib2, iclass 32, count 0 2006.260.07:20:18.08#ibcon#flushed, iclass 32, count 0 2006.260.07:20:18.08#ibcon#about to write, iclass 32, count 0 2006.260.07:20:18.08#ibcon#wrote, iclass 32, count 0 2006.260.07:20:18.08#ibcon#about to read 3, iclass 32, count 0 2006.260.07:20:18.10#ibcon#read 3, iclass 32, count 0 2006.260.07:20:18.10#ibcon#about to read 4, iclass 32, count 0 2006.260.07:20:18.10#ibcon#read 4, iclass 32, count 0 2006.260.07:20:18.10#ibcon#about to read 5, iclass 32, count 0 2006.260.07:20:18.10#ibcon#read 5, iclass 32, count 0 2006.260.07:20:18.10#ibcon#about to read 6, iclass 32, count 0 2006.260.07:20:18.10#ibcon#read 6, iclass 32, count 0 2006.260.07:20:18.10#ibcon#end of sib2, iclass 32, count 0 2006.260.07:20:18.10#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:20:18.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:20:18.10#ibcon#[25=USB\r\n] 2006.260.07:20:18.10#ibcon#*before write, iclass 32, count 0 2006.260.07:20:18.10#ibcon#enter sib2, iclass 32, count 0 2006.260.07:20:18.10#ibcon#flushed, iclass 32, count 0 2006.260.07:20:18.10#ibcon#about to write, iclass 32, count 0 2006.260.07:20:18.10#ibcon#wrote, iclass 32, count 0 2006.260.07:20:18.10#ibcon#about to read 3, iclass 32, count 0 2006.260.07:20:18.13#ibcon#read 3, iclass 32, count 0 2006.260.07:20:18.13#ibcon#about to read 4, iclass 32, count 0 2006.260.07:20:18.13#ibcon#read 4, iclass 32, count 0 2006.260.07:20:18.13#ibcon#about to read 5, iclass 32, count 0 2006.260.07:20:18.13#ibcon#read 5, iclass 32, count 0 2006.260.07:20:18.13#ibcon#about to read 6, iclass 32, count 0 2006.260.07:20:18.13#ibcon#read 6, iclass 32, count 0 2006.260.07:20:18.13#ibcon#end of sib2, iclass 32, count 0 2006.260.07:20:18.13#ibcon#*after write, iclass 32, count 0 2006.260.07:20:18.13#ibcon#*before return 0, iclass 32, count 0 2006.260.07:20:18.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:18.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:18.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:20:18.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:20:18.13$vc4f8/valo=2,572.99 2006.260.07:20:18.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:20:18.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:18.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:18.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:18.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:18.13#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:20:18.13#ibcon#first serial, iclass 34, count 0 2006.260.07:20:18.13#ibcon#enter sib2, iclass 34, count 0 2006.260.07:20:18.13#ibcon#flushed, iclass 34, count 0 2006.260.07:20:18.13#ibcon#about to write, iclass 34, count 0 2006.260.07:20:18.13#ibcon#wrote, iclass 34, count 0 2006.260.07:20:18.13#ibcon#about to read 3, iclass 34, count 0 2006.260.07:20:18.15#ibcon#read 3, iclass 34, count 0 2006.260.07:20:18.15#ibcon#about to read 4, iclass 34, count 0 2006.260.07:20:18.15#ibcon#read 4, iclass 34, count 0 2006.260.07:20:18.15#ibcon#about to read 5, iclass 34, count 0 2006.260.07:20:18.15#ibcon#read 5, iclass 34, count 0 2006.260.07:20:18.15#ibcon#about to read 6, iclass 34, count 0 2006.260.07:20:18.15#ibcon#read 6, iclass 34, count 0 2006.260.07:20:18.15#ibcon#end of sib2, iclass 34, count 0 2006.260.07:20:18.15#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:20:18.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:20:18.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:20:18.15#ibcon#*before write, iclass 34, count 0 2006.260.07:20:18.15#ibcon#enter sib2, iclass 34, count 0 2006.260.07:20:18.15#ibcon#flushed, iclass 34, count 0 2006.260.07:20:18.15#ibcon#about to write, iclass 34, count 0 2006.260.07:20:18.15#ibcon#wrote, iclass 34, count 0 2006.260.07:20:18.15#ibcon#about to read 3, iclass 34, count 0 2006.260.07:20:18.19#ibcon#read 3, iclass 34, count 0 2006.260.07:20:18.19#ibcon#about to read 4, iclass 34, count 0 2006.260.07:20:18.19#ibcon#read 4, iclass 34, count 0 2006.260.07:20:18.19#ibcon#about to read 5, iclass 34, count 0 2006.260.07:20:18.19#ibcon#read 5, iclass 34, count 0 2006.260.07:20:18.19#ibcon#about to read 6, iclass 34, count 0 2006.260.07:20:18.19#ibcon#read 6, iclass 34, count 0 2006.260.07:20:18.19#ibcon#end of sib2, iclass 34, count 0 2006.260.07:20:18.19#ibcon#*after write, iclass 34, count 0 2006.260.07:20:18.19#ibcon#*before return 0, iclass 34, count 0 2006.260.07:20:18.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:18.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:18.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:20:18.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:20:18.19$vc4f8/va=2,7 2006.260.07:20:18.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:20:18.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:18.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:18.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:18.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:18.25#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:20:18.25#ibcon#first serial, iclass 36, count 2 2006.260.07:20:18.25#ibcon#enter sib2, iclass 36, count 2 2006.260.07:20:18.25#ibcon#flushed, iclass 36, count 2 2006.260.07:20:18.25#ibcon#about to write, iclass 36, count 2 2006.260.07:20:18.25#ibcon#wrote, iclass 36, count 2 2006.260.07:20:18.25#ibcon#about to read 3, iclass 36, count 2 2006.260.07:20:18.27#ibcon#read 3, iclass 36, count 2 2006.260.07:20:18.27#ibcon#about to read 4, iclass 36, count 2 2006.260.07:20:18.27#ibcon#read 4, iclass 36, count 2 2006.260.07:20:18.27#ibcon#about to read 5, iclass 36, count 2 2006.260.07:20:18.27#ibcon#read 5, iclass 36, count 2 2006.260.07:20:18.27#ibcon#about to read 6, iclass 36, count 2 2006.260.07:20:18.27#ibcon#read 6, iclass 36, count 2 2006.260.07:20:18.27#ibcon#end of sib2, iclass 36, count 2 2006.260.07:20:18.27#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:20:18.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:20:18.27#ibcon#[25=AT02-07\r\n] 2006.260.07:20:18.27#ibcon#*before write, iclass 36, count 2 2006.260.07:20:18.27#ibcon#enter sib2, iclass 36, count 2 2006.260.07:20:18.27#ibcon#flushed, iclass 36, count 2 2006.260.07:20:18.27#ibcon#about to write, iclass 36, count 2 2006.260.07:20:18.27#ibcon#wrote, iclass 36, count 2 2006.260.07:20:18.27#ibcon#about to read 3, iclass 36, count 2 2006.260.07:20:18.30#ibcon#read 3, iclass 36, count 2 2006.260.07:20:18.30#ibcon#about to read 4, iclass 36, count 2 2006.260.07:20:18.30#ibcon#read 4, iclass 36, count 2 2006.260.07:20:18.30#ibcon#about to read 5, iclass 36, count 2 2006.260.07:20:18.30#ibcon#read 5, iclass 36, count 2 2006.260.07:20:18.30#ibcon#about to read 6, iclass 36, count 2 2006.260.07:20:18.30#ibcon#read 6, iclass 36, count 2 2006.260.07:20:18.30#ibcon#end of sib2, iclass 36, count 2 2006.260.07:20:18.30#ibcon#*after write, iclass 36, count 2 2006.260.07:20:18.30#ibcon#*before return 0, iclass 36, count 2 2006.260.07:20:18.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:18.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:18.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:20:18.30#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:18.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:18.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:18.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:18.42#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:20:18.42#ibcon#first serial, iclass 36, count 0 2006.260.07:20:18.42#ibcon#enter sib2, iclass 36, count 0 2006.260.07:20:18.42#ibcon#flushed, iclass 36, count 0 2006.260.07:20:18.42#ibcon#about to write, iclass 36, count 0 2006.260.07:20:18.42#ibcon#wrote, iclass 36, count 0 2006.260.07:20:18.42#ibcon#about to read 3, iclass 36, count 0 2006.260.07:20:18.44#ibcon#read 3, iclass 36, count 0 2006.260.07:20:18.44#ibcon#about to read 4, iclass 36, count 0 2006.260.07:20:18.44#ibcon#read 4, iclass 36, count 0 2006.260.07:20:18.44#ibcon#about to read 5, iclass 36, count 0 2006.260.07:20:18.44#ibcon#read 5, iclass 36, count 0 2006.260.07:20:18.44#ibcon#about to read 6, iclass 36, count 0 2006.260.07:20:18.44#ibcon#read 6, iclass 36, count 0 2006.260.07:20:18.44#ibcon#end of sib2, iclass 36, count 0 2006.260.07:20:18.44#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:20:18.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:20:18.44#ibcon#[25=USB\r\n] 2006.260.07:20:18.44#ibcon#*before write, iclass 36, count 0 2006.260.07:20:18.44#ibcon#enter sib2, iclass 36, count 0 2006.260.07:20:18.44#ibcon#flushed, iclass 36, count 0 2006.260.07:20:18.44#ibcon#about to write, iclass 36, count 0 2006.260.07:20:18.44#ibcon#wrote, iclass 36, count 0 2006.260.07:20:18.44#ibcon#about to read 3, iclass 36, count 0 2006.260.07:20:18.47#ibcon#read 3, iclass 36, count 0 2006.260.07:20:18.47#ibcon#about to read 4, iclass 36, count 0 2006.260.07:20:18.47#ibcon#read 4, iclass 36, count 0 2006.260.07:20:18.47#ibcon#about to read 5, iclass 36, count 0 2006.260.07:20:18.47#ibcon#read 5, iclass 36, count 0 2006.260.07:20:18.47#ibcon#about to read 6, iclass 36, count 0 2006.260.07:20:18.47#ibcon#read 6, iclass 36, count 0 2006.260.07:20:18.47#ibcon#end of sib2, iclass 36, count 0 2006.260.07:20:18.47#ibcon#*after write, iclass 36, count 0 2006.260.07:20:18.47#ibcon#*before return 0, iclass 36, count 0 2006.260.07:20:18.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:18.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:18.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:20:18.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:20:18.47$vc4f8/valo=3,672.99 2006.260.07:20:18.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:20:18.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:20:18.47#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:18.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:18.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:18.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:18.47#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:20:18.47#ibcon#first serial, iclass 38, count 0 2006.260.07:20:18.47#ibcon#enter sib2, iclass 38, count 0 2006.260.07:20:18.47#ibcon#flushed, iclass 38, count 0 2006.260.07:20:18.47#ibcon#about to write, iclass 38, count 0 2006.260.07:20:18.47#ibcon#wrote, iclass 38, count 0 2006.260.07:20:18.47#ibcon#about to read 3, iclass 38, count 0 2006.260.07:20:18.49#ibcon#read 3, iclass 38, count 0 2006.260.07:20:18.49#ibcon#about to read 4, iclass 38, count 0 2006.260.07:20:18.49#ibcon#read 4, iclass 38, count 0 2006.260.07:20:18.49#ibcon#about to read 5, iclass 38, count 0 2006.260.07:20:18.49#ibcon#read 5, iclass 38, count 0 2006.260.07:20:18.49#ibcon#about to read 6, iclass 38, count 0 2006.260.07:20:18.49#ibcon#read 6, iclass 38, count 0 2006.260.07:20:18.49#ibcon#end of sib2, iclass 38, count 0 2006.260.07:20:18.49#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:20:18.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:20:18.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:20:18.49#ibcon#*before write, iclass 38, count 0 2006.260.07:20:18.49#ibcon#enter sib2, iclass 38, count 0 2006.260.07:20:18.49#ibcon#flushed, iclass 38, count 0 2006.260.07:20:18.49#ibcon#about to write, iclass 38, count 0 2006.260.07:20:18.49#ibcon#wrote, iclass 38, count 0 2006.260.07:20:18.49#ibcon#about to read 3, iclass 38, count 0 2006.260.07:20:18.53#ibcon#read 3, iclass 38, count 0 2006.260.07:20:18.53#ibcon#about to read 4, iclass 38, count 0 2006.260.07:20:18.53#ibcon#read 4, iclass 38, count 0 2006.260.07:20:18.53#ibcon#about to read 5, iclass 38, count 0 2006.260.07:20:18.53#ibcon#read 5, iclass 38, count 0 2006.260.07:20:18.53#ibcon#about to read 6, iclass 38, count 0 2006.260.07:20:18.53#ibcon#read 6, iclass 38, count 0 2006.260.07:20:18.53#ibcon#end of sib2, iclass 38, count 0 2006.260.07:20:18.53#ibcon#*after write, iclass 38, count 0 2006.260.07:20:18.53#ibcon#*before return 0, iclass 38, count 0 2006.260.07:20:18.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:18.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:18.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:20:18.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:20:18.54$vc4f8/va=3,8 2006.260.07:20:18.54#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:20:18.54#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:20:18.54#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:18.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:18.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:18.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:18.58#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:20:18.58#ibcon#first serial, iclass 40, count 2 2006.260.07:20:18.58#ibcon#enter sib2, iclass 40, count 2 2006.260.07:20:18.58#ibcon#flushed, iclass 40, count 2 2006.260.07:20:18.58#ibcon#about to write, iclass 40, count 2 2006.260.07:20:18.58#ibcon#wrote, iclass 40, count 2 2006.260.07:20:18.58#ibcon#about to read 3, iclass 40, count 2 2006.260.07:20:18.61#ibcon#read 3, iclass 40, count 2 2006.260.07:20:18.61#ibcon#about to read 4, iclass 40, count 2 2006.260.07:20:18.61#ibcon#read 4, iclass 40, count 2 2006.260.07:20:18.61#ibcon#about to read 5, iclass 40, count 2 2006.260.07:20:18.61#ibcon#read 5, iclass 40, count 2 2006.260.07:20:18.61#ibcon#about to read 6, iclass 40, count 2 2006.260.07:20:18.61#ibcon#read 6, iclass 40, count 2 2006.260.07:20:18.61#ibcon#end of sib2, iclass 40, count 2 2006.260.07:20:18.61#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:20:18.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:20:18.61#ibcon#[25=AT03-08\r\n] 2006.260.07:20:18.61#ibcon#*before write, iclass 40, count 2 2006.260.07:20:18.61#ibcon#enter sib2, iclass 40, count 2 2006.260.07:20:18.61#ibcon#flushed, iclass 40, count 2 2006.260.07:20:18.61#ibcon#about to write, iclass 40, count 2 2006.260.07:20:18.61#ibcon#wrote, iclass 40, count 2 2006.260.07:20:18.61#ibcon#about to read 3, iclass 40, count 2 2006.260.07:20:18.64#ibcon#read 3, iclass 40, count 2 2006.260.07:20:18.64#ibcon#about to read 4, iclass 40, count 2 2006.260.07:20:18.64#ibcon#read 4, iclass 40, count 2 2006.260.07:20:18.64#ibcon#about to read 5, iclass 40, count 2 2006.260.07:20:18.64#ibcon#read 5, iclass 40, count 2 2006.260.07:20:18.64#ibcon#about to read 6, iclass 40, count 2 2006.260.07:20:18.64#ibcon#read 6, iclass 40, count 2 2006.260.07:20:18.64#ibcon#end of sib2, iclass 40, count 2 2006.260.07:20:18.64#ibcon#*after write, iclass 40, count 2 2006.260.07:20:18.64#ibcon#*before return 0, iclass 40, count 2 2006.260.07:20:18.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:18.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:18.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:20:18.64#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:18.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:18.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:18.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:18.76#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:20:18.76#ibcon#first serial, iclass 40, count 0 2006.260.07:20:18.76#ibcon#enter sib2, iclass 40, count 0 2006.260.07:20:18.76#ibcon#flushed, iclass 40, count 0 2006.260.07:20:18.76#ibcon#about to write, iclass 40, count 0 2006.260.07:20:18.76#ibcon#wrote, iclass 40, count 0 2006.260.07:20:18.76#ibcon#about to read 3, iclass 40, count 0 2006.260.07:20:18.78#ibcon#read 3, iclass 40, count 0 2006.260.07:20:18.78#ibcon#about to read 4, iclass 40, count 0 2006.260.07:20:18.78#ibcon#read 4, iclass 40, count 0 2006.260.07:20:18.78#ibcon#about to read 5, iclass 40, count 0 2006.260.07:20:18.78#ibcon#read 5, iclass 40, count 0 2006.260.07:20:18.78#ibcon#about to read 6, iclass 40, count 0 2006.260.07:20:18.78#ibcon#read 6, iclass 40, count 0 2006.260.07:20:18.78#ibcon#end of sib2, iclass 40, count 0 2006.260.07:20:18.78#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:20:18.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:20:18.78#ibcon#[25=USB\r\n] 2006.260.07:20:18.78#ibcon#*before write, iclass 40, count 0 2006.260.07:20:18.78#ibcon#enter sib2, iclass 40, count 0 2006.260.07:20:18.78#ibcon#flushed, iclass 40, count 0 2006.260.07:20:18.78#ibcon#about to write, iclass 40, count 0 2006.260.07:20:18.78#ibcon#wrote, iclass 40, count 0 2006.260.07:20:18.78#ibcon#about to read 3, iclass 40, count 0 2006.260.07:20:18.81#ibcon#read 3, iclass 40, count 0 2006.260.07:20:18.81#ibcon#about to read 4, iclass 40, count 0 2006.260.07:20:18.81#ibcon#read 4, iclass 40, count 0 2006.260.07:20:18.81#ibcon#about to read 5, iclass 40, count 0 2006.260.07:20:18.81#ibcon#read 5, iclass 40, count 0 2006.260.07:20:18.81#ibcon#about to read 6, iclass 40, count 0 2006.260.07:20:18.81#ibcon#read 6, iclass 40, count 0 2006.260.07:20:18.81#ibcon#end of sib2, iclass 40, count 0 2006.260.07:20:18.81#ibcon#*after write, iclass 40, count 0 2006.260.07:20:18.81#ibcon#*before return 0, iclass 40, count 0 2006.260.07:20:18.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:18.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:18.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:20:18.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:20:18.81$vc4f8/valo=4,832.99 2006.260.07:20:18.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:20:18.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:20:18.81#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:18.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:18.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:18.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:18.81#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:20:18.81#ibcon#first serial, iclass 4, count 0 2006.260.07:20:18.81#ibcon#enter sib2, iclass 4, count 0 2006.260.07:20:18.81#ibcon#flushed, iclass 4, count 0 2006.260.07:20:18.81#ibcon#about to write, iclass 4, count 0 2006.260.07:20:18.81#ibcon#wrote, iclass 4, count 0 2006.260.07:20:18.81#ibcon#about to read 3, iclass 4, count 0 2006.260.07:20:18.83#ibcon#read 3, iclass 4, count 0 2006.260.07:20:18.83#ibcon#about to read 4, iclass 4, count 0 2006.260.07:20:18.83#ibcon#read 4, iclass 4, count 0 2006.260.07:20:18.83#ibcon#about to read 5, iclass 4, count 0 2006.260.07:20:18.83#ibcon#read 5, iclass 4, count 0 2006.260.07:20:18.83#ibcon#about to read 6, iclass 4, count 0 2006.260.07:20:18.83#ibcon#read 6, iclass 4, count 0 2006.260.07:20:18.83#ibcon#end of sib2, iclass 4, count 0 2006.260.07:20:18.83#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:20:18.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:20:18.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:20:18.83#ibcon#*before write, iclass 4, count 0 2006.260.07:20:18.83#ibcon#enter sib2, iclass 4, count 0 2006.260.07:20:18.83#ibcon#flushed, iclass 4, count 0 2006.260.07:20:18.83#ibcon#about to write, iclass 4, count 0 2006.260.07:20:18.83#ibcon#wrote, iclass 4, count 0 2006.260.07:20:18.83#ibcon#about to read 3, iclass 4, count 0 2006.260.07:20:18.87#ibcon#read 3, iclass 4, count 0 2006.260.07:20:18.87#ibcon#about to read 4, iclass 4, count 0 2006.260.07:20:18.87#ibcon#read 4, iclass 4, count 0 2006.260.07:20:18.87#ibcon#about to read 5, iclass 4, count 0 2006.260.07:20:18.87#ibcon#read 5, iclass 4, count 0 2006.260.07:20:18.87#ibcon#about to read 6, iclass 4, count 0 2006.260.07:20:18.87#ibcon#read 6, iclass 4, count 0 2006.260.07:20:18.87#ibcon#end of sib2, iclass 4, count 0 2006.260.07:20:18.87#ibcon#*after write, iclass 4, count 0 2006.260.07:20:18.87#ibcon#*before return 0, iclass 4, count 0 2006.260.07:20:18.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:18.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:18.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:20:18.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:20:18.87$vc4f8/va=4,7 2006.260.07:20:18.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:20:18.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:20:18.87#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:18.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:18.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:18.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:18.93#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:20:18.93#ibcon#first serial, iclass 6, count 2 2006.260.07:20:18.93#ibcon#enter sib2, iclass 6, count 2 2006.260.07:20:18.93#ibcon#flushed, iclass 6, count 2 2006.260.07:20:18.93#ibcon#about to write, iclass 6, count 2 2006.260.07:20:18.93#ibcon#wrote, iclass 6, count 2 2006.260.07:20:18.93#ibcon#about to read 3, iclass 6, count 2 2006.260.07:20:18.95#ibcon#read 3, iclass 6, count 2 2006.260.07:20:18.95#ibcon#about to read 4, iclass 6, count 2 2006.260.07:20:18.95#ibcon#read 4, iclass 6, count 2 2006.260.07:20:18.95#ibcon#about to read 5, iclass 6, count 2 2006.260.07:20:18.95#ibcon#read 5, iclass 6, count 2 2006.260.07:20:18.95#ibcon#about to read 6, iclass 6, count 2 2006.260.07:20:18.95#ibcon#read 6, iclass 6, count 2 2006.260.07:20:18.95#ibcon#end of sib2, iclass 6, count 2 2006.260.07:20:18.95#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:20:18.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:20:18.95#ibcon#[25=AT04-07\r\n] 2006.260.07:20:18.95#ibcon#*before write, iclass 6, count 2 2006.260.07:20:18.95#ibcon#enter sib2, iclass 6, count 2 2006.260.07:20:18.95#ibcon#flushed, iclass 6, count 2 2006.260.07:20:18.95#ibcon#about to write, iclass 6, count 2 2006.260.07:20:18.95#ibcon#wrote, iclass 6, count 2 2006.260.07:20:18.95#ibcon#about to read 3, iclass 6, count 2 2006.260.07:20:18.98#ibcon#read 3, iclass 6, count 2 2006.260.07:20:18.98#ibcon#about to read 4, iclass 6, count 2 2006.260.07:20:18.98#ibcon#read 4, iclass 6, count 2 2006.260.07:20:18.98#ibcon#about to read 5, iclass 6, count 2 2006.260.07:20:18.98#ibcon#read 5, iclass 6, count 2 2006.260.07:20:18.98#ibcon#about to read 6, iclass 6, count 2 2006.260.07:20:18.98#ibcon#read 6, iclass 6, count 2 2006.260.07:20:18.98#ibcon#end of sib2, iclass 6, count 2 2006.260.07:20:18.98#ibcon#*after write, iclass 6, count 2 2006.260.07:20:18.98#ibcon#*before return 0, iclass 6, count 2 2006.260.07:20:18.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:18.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:18.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:20:18.98#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:18.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:19.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:19.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:19.10#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:20:19.10#ibcon#first serial, iclass 6, count 0 2006.260.07:20:19.10#ibcon#enter sib2, iclass 6, count 0 2006.260.07:20:19.10#ibcon#flushed, iclass 6, count 0 2006.260.07:20:19.10#ibcon#about to write, iclass 6, count 0 2006.260.07:20:19.10#ibcon#wrote, iclass 6, count 0 2006.260.07:20:19.10#ibcon#about to read 3, iclass 6, count 0 2006.260.07:20:19.12#ibcon#read 3, iclass 6, count 0 2006.260.07:20:19.12#ibcon#about to read 4, iclass 6, count 0 2006.260.07:20:19.12#ibcon#read 4, iclass 6, count 0 2006.260.07:20:19.12#ibcon#about to read 5, iclass 6, count 0 2006.260.07:20:19.12#ibcon#read 5, iclass 6, count 0 2006.260.07:20:19.12#ibcon#about to read 6, iclass 6, count 0 2006.260.07:20:19.12#ibcon#read 6, iclass 6, count 0 2006.260.07:20:19.12#ibcon#end of sib2, iclass 6, count 0 2006.260.07:20:19.12#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:20:19.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:20:19.12#ibcon#[25=USB\r\n] 2006.260.07:20:19.12#ibcon#*before write, iclass 6, count 0 2006.260.07:20:19.12#ibcon#enter sib2, iclass 6, count 0 2006.260.07:20:19.12#ibcon#flushed, iclass 6, count 0 2006.260.07:20:19.12#ibcon#about to write, iclass 6, count 0 2006.260.07:20:19.12#ibcon#wrote, iclass 6, count 0 2006.260.07:20:19.12#ibcon#about to read 3, iclass 6, count 0 2006.260.07:20:19.15#ibcon#read 3, iclass 6, count 0 2006.260.07:20:19.15#ibcon#about to read 4, iclass 6, count 0 2006.260.07:20:19.15#ibcon#read 4, iclass 6, count 0 2006.260.07:20:19.15#ibcon#about to read 5, iclass 6, count 0 2006.260.07:20:19.15#ibcon#read 5, iclass 6, count 0 2006.260.07:20:19.15#ibcon#about to read 6, iclass 6, count 0 2006.260.07:20:19.15#ibcon#read 6, iclass 6, count 0 2006.260.07:20:19.15#ibcon#end of sib2, iclass 6, count 0 2006.260.07:20:19.15#ibcon#*after write, iclass 6, count 0 2006.260.07:20:19.15#ibcon#*before return 0, iclass 6, count 0 2006.260.07:20:19.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:19.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:19.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:20:19.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:20:19.15$vc4f8/valo=5,652.99 2006.260.07:20:19.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:20:19.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:20:19.15#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:19.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:19.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:19.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:19.15#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:20:19.15#ibcon#first serial, iclass 10, count 0 2006.260.07:20:19.15#ibcon#enter sib2, iclass 10, count 0 2006.260.07:20:19.15#ibcon#flushed, iclass 10, count 0 2006.260.07:20:19.15#ibcon#about to write, iclass 10, count 0 2006.260.07:20:19.15#ibcon#wrote, iclass 10, count 0 2006.260.07:20:19.15#ibcon#about to read 3, iclass 10, count 0 2006.260.07:20:19.17#ibcon#read 3, iclass 10, count 0 2006.260.07:20:19.17#ibcon#about to read 4, iclass 10, count 0 2006.260.07:20:19.17#ibcon#read 4, iclass 10, count 0 2006.260.07:20:19.17#ibcon#about to read 5, iclass 10, count 0 2006.260.07:20:19.17#ibcon#read 5, iclass 10, count 0 2006.260.07:20:19.17#ibcon#about to read 6, iclass 10, count 0 2006.260.07:20:19.17#ibcon#read 6, iclass 10, count 0 2006.260.07:20:19.17#ibcon#end of sib2, iclass 10, count 0 2006.260.07:20:19.17#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:20:19.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:20:19.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:20:19.17#ibcon#*before write, iclass 10, count 0 2006.260.07:20:19.17#ibcon#enter sib2, iclass 10, count 0 2006.260.07:20:19.17#ibcon#flushed, iclass 10, count 0 2006.260.07:20:19.17#ibcon#about to write, iclass 10, count 0 2006.260.07:20:19.17#ibcon#wrote, iclass 10, count 0 2006.260.07:20:19.17#ibcon#about to read 3, iclass 10, count 0 2006.260.07:20:19.21#ibcon#read 3, iclass 10, count 0 2006.260.07:20:19.21#ibcon#about to read 4, iclass 10, count 0 2006.260.07:20:19.21#ibcon#read 4, iclass 10, count 0 2006.260.07:20:19.21#ibcon#about to read 5, iclass 10, count 0 2006.260.07:20:19.21#ibcon#read 5, iclass 10, count 0 2006.260.07:20:19.21#ibcon#about to read 6, iclass 10, count 0 2006.260.07:20:19.21#ibcon#read 6, iclass 10, count 0 2006.260.07:20:19.21#ibcon#end of sib2, iclass 10, count 0 2006.260.07:20:19.21#ibcon#*after write, iclass 10, count 0 2006.260.07:20:19.21#ibcon#*before return 0, iclass 10, count 0 2006.260.07:20:19.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:19.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:19.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:20:19.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:20:19.21$vc4f8/va=5,7 2006.260.07:20:19.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:20:19.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:20:19.21#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:19.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:19.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:19.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:19.27#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:20:19.27#ibcon#first serial, iclass 12, count 2 2006.260.07:20:19.27#ibcon#enter sib2, iclass 12, count 2 2006.260.07:20:19.27#ibcon#flushed, iclass 12, count 2 2006.260.07:20:19.27#ibcon#about to write, iclass 12, count 2 2006.260.07:20:19.27#ibcon#wrote, iclass 12, count 2 2006.260.07:20:19.27#ibcon#about to read 3, iclass 12, count 2 2006.260.07:20:19.29#ibcon#read 3, iclass 12, count 2 2006.260.07:20:19.29#ibcon#about to read 4, iclass 12, count 2 2006.260.07:20:19.29#ibcon#read 4, iclass 12, count 2 2006.260.07:20:19.29#ibcon#about to read 5, iclass 12, count 2 2006.260.07:20:19.29#ibcon#read 5, iclass 12, count 2 2006.260.07:20:19.29#ibcon#about to read 6, iclass 12, count 2 2006.260.07:20:19.29#ibcon#read 6, iclass 12, count 2 2006.260.07:20:19.29#ibcon#end of sib2, iclass 12, count 2 2006.260.07:20:19.29#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:20:19.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:20:19.29#ibcon#[25=AT05-07\r\n] 2006.260.07:20:19.29#ibcon#*before write, iclass 12, count 2 2006.260.07:20:19.29#ibcon#enter sib2, iclass 12, count 2 2006.260.07:20:19.29#ibcon#flushed, iclass 12, count 2 2006.260.07:20:19.29#ibcon#about to write, iclass 12, count 2 2006.260.07:20:19.29#ibcon#wrote, iclass 12, count 2 2006.260.07:20:19.29#ibcon#about to read 3, iclass 12, count 2 2006.260.07:20:19.32#ibcon#read 3, iclass 12, count 2 2006.260.07:20:19.32#ibcon#about to read 4, iclass 12, count 2 2006.260.07:20:19.32#ibcon#read 4, iclass 12, count 2 2006.260.07:20:19.32#ibcon#about to read 5, iclass 12, count 2 2006.260.07:20:19.32#ibcon#read 5, iclass 12, count 2 2006.260.07:20:19.32#ibcon#about to read 6, iclass 12, count 2 2006.260.07:20:19.32#ibcon#read 6, iclass 12, count 2 2006.260.07:20:19.32#ibcon#end of sib2, iclass 12, count 2 2006.260.07:20:19.32#ibcon#*after write, iclass 12, count 2 2006.260.07:20:19.32#ibcon#*before return 0, iclass 12, count 2 2006.260.07:20:19.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:19.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:19.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:20:19.32#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:19.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:19.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:19.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:19.44#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:20:19.44#ibcon#first serial, iclass 12, count 0 2006.260.07:20:19.44#ibcon#enter sib2, iclass 12, count 0 2006.260.07:20:19.44#ibcon#flushed, iclass 12, count 0 2006.260.07:20:19.44#ibcon#about to write, iclass 12, count 0 2006.260.07:20:19.44#ibcon#wrote, iclass 12, count 0 2006.260.07:20:19.44#ibcon#about to read 3, iclass 12, count 0 2006.260.07:20:19.46#ibcon#read 3, iclass 12, count 0 2006.260.07:20:19.46#ibcon#about to read 4, iclass 12, count 0 2006.260.07:20:19.46#ibcon#read 4, iclass 12, count 0 2006.260.07:20:19.46#ibcon#about to read 5, iclass 12, count 0 2006.260.07:20:19.46#ibcon#read 5, iclass 12, count 0 2006.260.07:20:19.46#ibcon#about to read 6, iclass 12, count 0 2006.260.07:20:19.46#ibcon#read 6, iclass 12, count 0 2006.260.07:20:19.46#ibcon#end of sib2, iclass 12, count 0 2006.260.07:20:19.46#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:20:19.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:20:19.46#ibcon#[25=USB\r\n] 2006.260.07:20:19.46#ibcon#*before write, iclass 12, count 0 2006.260.07:20:19.46#ibcon#enter sib2, iclass 12, count 0 2006.260.07:20:19.46#ibcon#flushed, iclass 12, count 0 2006.260.07:20:19.46#ibcon#about to write, iclass 12, count 0 2006.260.07:20:19.46#ibcon#wrote, iclass 12, count 0 2006.260.07:20:19.46#ibcon#about to read 3, iclass 12, count 0 2006.260.07:20:19.49#ibcon#read 3, iclass 12, count 0 2006.260.07:20:19.49#ibcon#about to read 4, iclass 12, count 0 2006.260.07:20:19.49#ibcon#read 4, iclass 12, count 0 2006.260.07:20:19.49#ibcon#about to read 5, iclass 12, count 0 2006.260.07:20:19.49#ibcon#read 5, iclass 12, count 0 2006.260.07:20:19.49#ibcon#about to read 6, iclass 12, count 0 2006.260.07:20:19.49#ibcon#read 6, iclass 12, count 0 2006.260.07:20:19.49#ibcon#end of sib2, iclass 12, count 0 2006.260.07:20:19.49#ibcon#*after write, iclass 12, count 0 2006.260.07:20:19.49#ibcon#*before return 0, iclass 12, count 0 2006.260.07:20:19.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:19.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:19.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:20:19.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:20:19.49$vc4f8/valo=6,772.99 2006.260.07:20:19.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:20:19.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:20:19.49#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:19.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:19.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:19.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:19.49#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:20:19.49#ibcon#first serial, iclass 14, count 0 2006.260.07:20:19.49#ibcon#enter sib2, iclass 14, count 0 2006.260.07:20:19.49#ibcon#flushed, iclass 14, count 0 2006.260.07:20:19.49#ibcon#about to write, iclass 14, count 0 2006.260.07:20:19.49#ibcon#wrote, iclass 14, count 0 2006.260.07:20:19.49#ibcon#about to read 3, iclass 14, count 0 2006.260.07:20:19.52#ibcon#read 3, iclass 14, count 0 2006.260.07:20:19.52#ibcon#about to read 4, iclass 14, count 0 2006.260.07:20:19.52#ibcon#read 4, iclass 14, count 0 2006.260.07:20:19.52#ibcon#about to read 5, iclass 14, count 0 2006.260.07:20:19.52#ibcon#read 5, iclass 14, count 0 2006.260.07:20:19.52#ibcon#about to read 6, iclass 14, count 0 2006.260.07:20:19.52#ibcon#read 6, iclass 14, count 0 2006.260.07:20:19.52#ibcon#end of sib2, iclass 14, count 0 2006.260.07:20:19.52#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:20:19.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:20:19.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:20:19.52#ibcon#*before write, iclass 14, count 0 2006.260.07:20:19.52#ibcon#enter sib2, iclass 14, count 0 2006.260.07:20:19.52#ibcon#flushed, iclass 14, count 0 2006.260.07:20:19.52#ibcon#about to write, iclass 14, count 0 2006.260.07:20:19.52#ibcon#wrote, iclass 14, count 0 2006.260.07:20:19.52#ibcon#about to read 3, iclass 14, count 0 2006.260.07:20:19.56#ibcon#read 3, iclass 14, count 0 2006.260.07:20:19.56#ibcon#about to read 4, iclass 14, count 0 2006.260.07:20:19.56#ibcon#read 4, iclass 14, count 0 2006.260.07:20:19.56#ibcon#about to read 5, iclass 14, count 0 2006.260.07:20:19.56#ibcon#read 5, iclass 14, count 0 2006.260.07:20:19.56#ibcon#about to read 6, iclass 14, count 0 2006.260.07:20:19.56#ibcon#read 6, iclass 14, count 0 2006.260.07:20:19.56#ibcon#end of sib2, iclass 14, count 0 2006.260.07:20:19.56#ibcon#*after write, iclass 14, count 0 2006.260.07:20:19.56#ibcon#*before return 0, iclass 14, count 0 2006.260.07:20:19.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:19.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:19.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:20:19.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:20:19.56$vc4f8/va=6,6 2006.260.07:20:19.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:20:19.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:20:19.56#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:19.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:19.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:19.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:19.61#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:20:19.61#ibcon#first serial, iclass 16, count 2 2006.260.07:20:19.61#ibcon#enter sib2, iclass 16, count 2 2006.260.07:20:19.61#ibcon#flushed, iclass 16, count 2 2006.260.07:20:19.61#ibcon#about to write, iclass 16, count 2 2006.260.07:20:19.61#ibcon#wrote, iclass 16, count 2 2006.260.07:20:19.61#ibcon#about to read 3, iclass 16, count 2 2006.260.07:20:19.63#ibcon#read 3, iclass 16, count 2 2006.260.07:20:19.63#ibcon#about to read 4, iclass 16, count 2 2006.260.07:20:19.63#ibcon#read 4, iclass 16, count 2 2006.260.07:20:19.63#ibcon#about to read 5, iclass 16, count 2 2006.260.07:20:19.63#ibcon#read 5, iclass 16, count 2 2006.260.07:20:19.63#ibcon#about to read 6, iclass 16, count 2 2006.260.07:20:19.63#ibcon#read 6, iclass 16, count 2 2006.260.07:20:19.63#ibcon#end of sib2, iclass 16, count 2 2006.260.07:20:19.63#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:20:19.63#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:20:19.63#ibcon#[25=AT06-06\r\n] 2006.260.07:20:19.63#ibcon#*before write, iclass 16, count 2 2006.260.07:20:19.63#ibcon#enter sib2, iclass 16, count 2 2006.260.07:20:19.63#ibcon#flushed, iclass 16, count 2 2006.260.07:20:19.63#ibcon#about to write, iclass 16, count 2 2006.260.07:20:19.63#ibcon#wrote, iclass 16, count 2 2006.260.07:20:19.63#ibcon#about to read 3, iclass 16, count 2 2006.260.07:20:19.66#ibcon#read 3, iclass 16, count 2 2006.260.07:20:19.66#ibcon#about to read 4, iclass 16, count 2 2006.260.07:20:19.66#ibcon#read 4, iclass 16, count 2 2006.260.07:20:19.66#ibcon#about to read 5, iclass 16, count 2 2006.260.07:20:19.66#ibcon#read 5, iclass 16, count 2 2006.260.07:20:19.66#ibcon#about to read 6, iclass 16, count 2 2006.260.07:20:19.66#ibcon#read 6, iclass 16, count 2 2006.260.07:20:19.66#ibcon#end of sib2, iclass 16, count 2 2006.260.07:20:19.66#ibcon#*after write, iclass 16, count 2 2006.260.07:20:19.66#ibcon#*before return 0, iclass 16, count 2 2006.260.07:20:19.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:19.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:19.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:20:19.66#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:19.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:20:19.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:20:19.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:20:19.78#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:20:19.78#ibcon#first serial, iclass 16, count 0 2006.260.07:20:19.78#ibcon#enter sib2, iclass 16, count 0 2006.260.07:20:19.78#ibcon#flushed, iclass 16, count 0 2006.260.07:20:19.78#ibcon#about to write, iclass 16, count 0 2006.260.07:20:19.78#ibcon#wrote, iclass 16, count 0 2006.260.07:20:19.78#ibcon#about to read 3, iclass 16, count 0 2006.260.07:20:19.80#ibcon#read 3, iclass 16, count 0 2006.260.07:20:19.80#ibcon#about to read 4, iclass 16, count 0 2006.260.07:20:19.80#ibcon#read 4, iclass 16, count 0 2006.260.07:20:19.80#ibcon#about to read 5, iclass 16, count 0 2006.260.07:20:19.80#ibcon#read 5, iclass 16, count 0 2006.260.07:20:19.80#ibcon#about to read 6, iclass 16, count 0 2006.260.07:20:19.80#ibcon#read 6, iclass 16, count 0 2006.260.07:20:19.80#ibcon#end of sib2, iclass 16, count 0 2006.260.07:20:19.80#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:20:19.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:20:19.80#ibcon#[25=USB\r\n] 2006.260.07:20:19.80#ibcon#*before write, iclass 16, count 0 2006.260.07:20:19.80#ibcon#enter sib2, iclass 16, count 0 2006.260.07:20:19.80#ibcon#flushed, iclass 16, count 0 2006.260.07:20:19.80#ibcon#about to write, iclass 16, count 0 2006.260.07:20:19.80#ibcon#wrote, iclass 16, count 0 2006.260.07:20:19.80#ibcon#about to read 3, iclass 16, count 0 2006.260.07:20:19.83#ibcon#read 3, iclass 16, count 0 2006.260.07:20:19.83#ibcon#about to read 4, iclass 16, count 0 2006.260.07:20:19.83#ibcon#read 4, iclass 16, count 0 2006.260.07:20:19.83#ibcon#about to read 5, iclass 16, count 0 2006.260.07:20:19.83#ibcon#read 5, iclass 16, count 0 2006.260.07:20:19.83#ibcon#about to read 6, iclass 16, count 0 2006.260.07:20:19.83#ibcon#read 6, iclass 16, count 0 2006.260.07:20:19.83#ibcon#end of sib2, iclass 16, count 0 2006.260.07:20:19.83#ibcon#*after write, iclass 16, count 0 2006.260.07:20:19.83#ibcon#*before return 0, iclass 16, count 0 2006.260.07:20:19.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:20:19.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:20:19.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:20:19.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:20:19.83$vc4f8/valo=7,832.99 2006.260.07:20:19.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:20:19.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:20:19.83#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:19.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:20:19.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:20:19.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:20:19.83#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:20:19.83#ibcon#first serial, iclass 18, count 0 2006.260.07:20:19.83#ibcon#enter sib2, iclass 18, count 0 2006.260.07:20:19.83#ibcon#flushed, iclass 18, count 0 2006.260.07:20:19.83#ibcon#about to write, iclass 18, count 0 2006.260.07:20:19.83#ibcon#wrote, iclass 18, count 0 2006.260.07:20:19.83#ibcon#about to read 3, iclass 18, count 0 2006.260.07:20:19.85#ibcon#read 3, iclass 18, count 0 2006.260.07:20:19.85#ibcon#about to read 4, iclass 18, count 0 2006.260.07:20:19.85#ibcon#read 4, iclass 18, count 0 2006.260.07:20:19.85#ibcon#about to read 5, iclass 18, count 0 2006.260.07:20:19.85#ibcon#read 5, iclass 18, count 0 2006.260.07:20:19.85#ibcon#about to read 6, iclass 18, count 0 2006.260.07:20:19.85#ibcon#read 6, iclass 18, count 0 2006.260.07:20:19.85#ibcon#end of sib2, iclass 18, count 0 2006.260.07:20:19.85#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:20:19.85#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:20:19.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:20:19.85#ibcon#*before write, iclass 18, count 0 2006.260.07:20:19.85#ibcon#enter sib2, iclass 18, count 0 2006.260.07:20:19.85#ibcon#flushed, iclass 18, count 0 2006.260.07:20:19.85#ibcon#about to write, iclass 18, count 0 2006.260.07:20:19.85#ibcon#wrote, iclass 18, count 0 2006.260.07:20:19.85#ibcon#about to read 3, iclass 18, count 0 2006.260.07:20:19.89#ibcon#read 3, iclass 18, count 0 2006.260.07:20:19.89#ibcon#about to read 4, iclass 18, count 0 2006.260.07:20:19.89#ibcon#read 4, iclass 18, count 0 2006.260.07:20:19.89#ibcon#about to read 5, iclass 18, count 0 2006.260.07:20:19.89#ibcon#read 5, iclass 18, count 0 2006.260.07:20:19.89#ibcon#about to read 6, iclass 18, count 0 2006.260.07:20:19.89#ibcon#read 6, iclass 18, count 0 2006.260.07:20:19.89#ibcon#end of sib2, iclass 18, count 0 2006.260.07:20:19.89#ibcon#*after write, iclass 18, count 0 2006.260.07:20:19.89#ibcon#*before return 0, iclass 18, count 0 2006.260.07:20:19.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:20:19.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:20:19.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:20:19.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:20:19.89$vc4f8/va=7,6 2006.260.07:20:19.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:20:19.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:20:19.89#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:19.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:20:19.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:20:19.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:20:19.95#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:20:19.95#ibcon#first serial, iclass 20, count 2 2006.260.07:20:19.95#ibcon#enter sib2, iclass 20, count 2 2006.260.07:20:19.95#ibcon#flushed, iclass 20, count 2 2006.260.07:20:19.95#ibcon#about to write, iclass 20, count 2 2006.260.07:20:19.95#ibcon#wrote, iclass 20, count 2 2006.260.07:20:19.95#ibcon#about to read 3, iclass 20, count 2 2006.260.07:20:19.97#ibcon#read 3, iclass 20, count 2 2006.260.07:20:19.97#ibcon#about to read 4, iclass 20, count 2 2006.260.07:20:19.97#ibcon#read 4, iclass 20, count 2 2006.260.07:20:19.97#ibcon#about to read 5, iclass 20, count 2 2006.260.07:20:19.97#ibcon#read 5, iclass 20, count 2 2006.260.07:20:19.97#ibcon#about to read 6, iclass 20, count 2 2006.260.07:20:19.97#ibcon#read 6, iclass 20, count 2 2006.260.07:20:19.97#ibcon#end of sib2, iclass 20, count 2 2006.260.07:20:19.97#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:20:19.97#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:20:19.97#ibcon#[25=AT07-06\r\n] 2006.260.07:20:19.97#ibcon#*before write, iclass 20, count 2 2006.260.07:20:19.97#ibcon#enter sib2, iclass 20, count 2 2006.260.07:20:19.97#ibcon#flushed, iclass 20, count 2 2006.260.07:20:19.97#ibcon#about to write, iclass 20, count 2 2006.260.07:20:19.97#ibcon#wrote, iclass 20, count 2 2006.260.07:20:19.97#ibcon#about to read 3, iclass 20, count 2 2006.260.07:20:20.00#ibcon#read 3, iclass 20, count 2 2006.260.07:20:20.00#ibcon#about to read 4, iclass 20, count 2 2006.260.07:20:20.00#ibcon#read 4, iclass 20, count 2 2006.260.07:20:20.00#ibcon#about to read 5, iclass 20, count 2 2006.260.07:20:20.00#ibcon#read 5, iclass 20, count 2 2006.260.07:20:20.00#ibcon#about to read 6, iclass 20, count 2 2006.260.07:20:20.00#ibcon#read 6, iclass 20, count 2 2006.260.07:20:20.00#ibcon#end of sib2, iclass 20, count 2 2006.260.07:20:20.00#ibcon#*after write, iclass 20, count 2 2006.260.07:20:20.00#ibcon#*before return 0, iclass 20, count 2 2006.260.07:20:20.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:20:20.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:20:20.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:20:20.00#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:20.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:20:20.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:20:20.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:20:20.12#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:20:20.12#ibcon#first serial, iclass 20, count 0 2006.260.07:20:20.12#ibcon#enter sib2, iclass 20, count 0 2006.260.07:20:20.12#ibcon#flushed, iclass 20, count 0 2006.260.07:20:20.12#ibcon#about to write, iclass 20, count 0 2006.260.07:20:20.12#ibcon#wrote, iclass 20, count 0 2006.260.07:20:20.12#ibcon#about to read 3, iclass 20, count 0 2006.260.07:20:20.14#ibcon#read 3, iclass 20, count 0 2006.260.07:20:20.14#ibcon#about to read 4, iclass 20, count 0 2006.260.07:20:20.14#ibcon#read 4, iclass 20, count 0 2006.260.07:20:20.14#ibcon#about to read 5, iclass 20, count 0 2006.260.07:20:20.14#ibcon#read 5, iclass 20, count 0 2006.260.07:20:20.14#ibcon#about to read 6, iclass 20, count 0 2006.260.07:20:20.14#ibcon#read 6, iclass 20, count 0 2006.260.07:20:20.14#ibcon#end of sib2, iclass 20, count 0 2006.260.07:20:20.14#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:20:20.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:20:20.14#ibcon#[25=USB\r\n] 2006.260.07:20:20.14#ibcon#*before write, iclass 20, count 0 2006.260.07:20:20.14#ibcon#enter sib2, iclass 20, count 0 2006.260.07:20:20.14#ibcon#flushed, iclass 20, count 0 2006.260.07:20:20.14#ibcon#about to write, iclass 20, count 0 2006.260.07:20:20.14#ibcon#wrote, iclass 20, count 0 2006.260.07:20:20.14#ibcon#about to read 3, iclass 20, count 0 2006.260.07:20:20.17#ibcon#read 3, iclass 20, count 0 2006.260.07:20:20.17#ibcon#about to read 4, iclass 20, count 0 2006.260.07:20:20.17#ibcon#read 4, iclass 20, count 0 2006.260.07:20:20.17#ibcon#about to read 5, iclass 20, count 0 2006.260.07:20:20.17#ibcon#read 5, iclass 20, count 0 2006.260.07:20:20.17#ibcon#about to read 6, iclass 20, count 0 2006.260.07:20:20.17#ibcon#read 6, iclass 20, count 0 2006.260.07:20:20.17#ibcon#end of sib2, iclass 20, count 0 2006.260.07:20:20.17#ibcon#*after write, iclass 20, count 0 2006.260.07:20:20.17#ibcon#*before return 0, iclass 20, count 0 2006.260.07:20:20.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:20:20.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:20:20.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:20:20.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:20:20.17$vc4f8/valo=8,852.99 2006.260.07:20:20.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:20:20.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:20:20.17#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:20.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:20:20.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:20:20.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:20:20.17#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:20:20.17#ibcon#first serial, iclass 22, count 0 2006.260.07:20:20.17#ibcon#enter sib2, iclass 22, count 0 2006.260.07:20:20.17#ibcon#flushed, iclass 22, count 0 2006.260.07:20:20.17#ibcon#about to write, iclass 22, count 0 2006.260.07:20:20.17#ibcon#wrote, iclass 22, count 0 2006.260.07:20:20.17#ibcon#about to read 3, iclass 22, count 0 2006.260.07:20:20.20#ibcon#read 3, iclass 22, count 0 2006.260.07:20:20.20#ibcon#about to read 4, iclass 22, count 0 2006.260.07:20:20.20#ibcon#read 4, iclass 22, count 0 2006.260.07:20:20.20#ibcon#about to read 5, iclass 22, count 0 2006.260.07:20:20.20#ibcon#read 5, iclass 22, count 0 2006.260.07:20:20.20#ibcon#about to read 6, iclass 22, count 0 2006.260.07:20:20.20#ibcon#read 6, iclass 22, count 0 2006.260.07:20:20.20#ibcon#end of sib2, iclass 22, count 0 2006.260.07:20:20.20#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:20:20.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:20:20.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:20:20.20#ibcon#*before write, iclass 22, count 0 2006.260.07:20:20.20#ibcon#enter sib2, iclass 22, count 0 2006.260.07:20:20.20#ibcon#flushed, iclass 22, count 0 2006.260.07:20:20.20#ibcon#about to write, iclass 22, count 0 2006.260.07:20:20.20#ibcon#wrote, iclass 22, count 0 2006.260.07:20:20.20#ibcon#about to read 3, iclass 22, count 0 2006.260.07:20:20.24#ibcon#read 3, iclass 22, count 0 2006.260.07:20:20.24#ibcon#about to read 4, iclass 22, count 0 2006.260.07:20:20.24#ibcon#read 4, iclass 22, count 0 2006.260.07:20:20.24#ibcon#about to read 5, iclass 22, count 0 2006.260.07:20:20.24#ibcon#read 5, iclass 22, count 0 2006.260.07:20:20.24#ibcon#about to read 6, iclass 22, count 0 2006.260.07:20:20.24#ibcon#read 6, iclass 22, count 0 2006.260.07:20:20.24#ibcon#end of sib2, iclass 22, count 0 2006.260.07:20:20.24#ibcon#*after write, iclass 22, count 0 2006.260.07:20:20.24#ibcon#*before return 0, iclass 22, count 0 2006.260.07:20:20.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:20:20.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:20:20.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:20:20.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:20:20.24$vc4f8/va=8,6 2006.260.07:20:20.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:20:20.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:20:20.24#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:20.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:20:20.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:20:20.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:20:20.29#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:20:20.29#ibcon#first serial, iclass 24, count 2 2006.260.07:20:20.29#ibcon#enter sib2, iclass 24, count 2 2006.260.07:20:20.29#ibcon#flushed, iclass 24, count 2 2006.260.07:20:20.29#ibcon#about to write, iclass 24, count 2 2006.260.07:20:20.29#ibcon#wrote, iclass 24, count 2 2006.260.07:20:20.29#ibcon#about to read 3, iclass 24, count 2 2006.260.07:20:20.31#ibcon#read 3, iclass 24, count 2 2006.260.07:20:20.31#ibcon#about to read 4, iclass 24, count 2 2006.260.07:20:20.31#ibcon#read 4, iclass 24, count 2 2006.260.07:20:20.31#ibcon#about to read 5, iclass 24, count 2 2006.260.07:20:20.31#ibcon#read 5, iclass 24, count 2 2006.260.07:20:20.31#ibcon#about to read 6, iclass 24, count 2 2006.260.07:20:20.31#ibcon#read 6, iclass 24, count 2 2006.260.07:20:20.31#ibcon#end of sib2, iclass 24, count 2 2006.260.07:20:20.31#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:20:20.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:20:20.31#ibcon#[25=AT08-06\r\n] 2006.260.07:20:20.31#ibcon#*before write, iclass 24, count 2 2006.260.07:20:20.31#ibcon#enter sib2, iclass 24, count 2 2006.260.07:20:20.31#ibcon#flushed, iclass 24, count 2 2006.260.07:20:20.31#ibcon#about to write, iclass 24, count 2 2006.260.07:20:20.31#ibcon#wrote, iclass 24, count 2 2006.260.07:20:20.31#ibcon#about to read 3, iclass 24, count 2 2006.260.07:20:20.34#ibcon#read 3, iclass 24, count 2 2006.260.07:20:20.34#ibcon#about to read 4, iclass 24, count 2 2006.260.07:20:20.34#ibcon#read 4, iclass 24, count 2 2006.260.07:20:20.34#ibcon#about to read 5, iclass 24, count 2 2006.260.07:20:20.34#ibcon#read 5, iclass 24, count 2 2006.260.07:20:20.34#ibcon#about to read 6, iclass 24, count 2 2006.260.07:20:20.34#ibcon#read 6, iclass 24, count 2 2006.260.07:20:20.34#ibcon#end of sib2, iclass 24, count 2 2006.260.07:20:20.34#ibcon#*after write, iclass 24, count 2 2006.260.07:20:20.34#ibcon#*before return 0, iclass 24, count 2 2006.260.07:20:20.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:20:20.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:20:20.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:20:20.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:20.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:20:20.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:20:20.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:20:20.46#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:20:20.46#ibcon#first serial, iclass 24, count 0 2006.260.07:20:20.46#ibcon#enter sib2, iclass 24, count 0 2006.260.07:20:20.46#ibcon#flushed, iclass 24, count 0 2006.260.07:20:20.46#ibcon#about to write, iclass 24, count 0 2006.260.07:20:20.46#ibcon#wrote, iclass 24, count 0 2006.260.07:20:20.46#ibcon#about to read 3, iclass 24, count 0 2006.260.07:20:20.48#ibcon#read 3, iclass 24, count 0 2006.260.07:20:20.48#ibcon#about to read 4, iclass 24, count 0 2006.260.07:20:20.48#ibcon#read 4, iclass 24, count 0 2006.260.07:20:20.48#ibcon#about to read 5, iclass 24, count 0 2006.260.07:20:20.48#ibcon#read 5, iclass 24, count 0 2006.260.07:20:20.48#ibcon#about to read 6, iclass 24, count 0 2006.260.07:20:20.48#ibcon#read 6, iclass 24, count 0 2006.260.07:20:20.48#ibcon#end of sib2, iclass 24, count 0 2006.260.07:20:20.48#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:20:20.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:20:20.48#ibcon#[25=USB\r\n] 2006.260.07:20:20.48#ibcon#*before write, iclass 24, count 0 2006.260.07:20:20.48#ibcon#enter sib2, iclass 24, count 0 2006.260.07:20:20.48#ibcon#flushed, iclass 24, count 0 2006.260.07:20:20.48#ibcon#about to write, iclass 24, count 0 2006.260.07:20:20.48#ibcon#wrote, iclass 24, count 0 2006.260.07:20:20.48#ibcon#about to read 3, iclass 24, count 0 2006.260.07:20:20.51#ibcon#read 3, iclass 24, count 0 2006.260.07:20:20.51#ibcon#about to read 4, iclass 24, count 0 2006.260.07:20:20.51#ibcon#read 4, iclass 24, count 0 2006.260.07:20:20.51#ibcon#about to read 5, iclass 24, count 0 2006.260.07:20:20.51#ibcon#read 5, iclass 24, count 0 2006.260.07:20:20.51#ibcon#about to read 6, iclass 24, count 0 2006.260.07:20:20.51#ibcon#read 6, iclass 24, count 0 2006.260.07:20:20.51#ibcon#end of sib2, iclass 24, count 0 2006.260.07:20:20.51#ibcon#*after write, iclass 24, count 0 2006.260.07:20:20.51#ibcon#*before return 0, iclass 24, count 0 2006.260.07:20:20.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:20:20.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:20:20.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:20:20.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:20:20.51$vc4f8/vblo=1,632.99 2006.260.07:20:20.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:20:20.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:20:20.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:20.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:20:20.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:20:20.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:20:20.51#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:20:20.51#ibcon#first serial, iclass 26, count 0 2006.260.07:20:20.51#ibcon#enter sib2, iclass 26, count 0 2006.260.07:20:20.51#ibcon#flushed, iclass 26, count 0 2006.260.07:20:20.51#ibcon#about to write, iclass 26, count 0 2006.260.07:20:20.51#ibcon#wrote, iclass 26, count 0 2006.260.07:20:20.51#ibcon#about to read 3, iclass 26, count 0 2006.260.07:20:20.53#ibcon#read 3, iclass 26, count 0 2006.260.07:20:20.53#ibcon#about to read 4, iclass 26, count 0 2006.260.07:20:20.53#ibcon#read 4, iclass 26, count 0 2006.260.07:20:20.53#ibcon#about to read 5, iclass 26, count 0 2006.260.07:20:20.53#ibcon#read 5, iclass 26, count 0 2006.260.07:20:20.53#ibcon#about to read 6, iclass 26, count 0 2006.260.07:20:20.53#ibcon#read 6, iclass 26, count 0 2006.260.07:20:20.53#ibcon#end of sib2, iclass 26, count 0 2006.260.07:20:20.53#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:20:20.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:20:20.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:20:20.53#ibcon#*before write, iclass 26, count 0 2006.260.07:20:20.53#ibcon#enter sib2, iclass 26, count 0 2006.260.07:20:20.53#ibcon#flushed, iclass 26, count 0 2006.260.07:20:20.53#ibcon#about to write, iclass 26, count 0 2006.260.07:20:20.53#ibcon#wrote, iclass 26, count 0 2006.260.07:20:20.53#ibcon#about to read 3, iclass 26, count 0 2006.260.07:20:20.57#ibcon#read 3, iclass 26, count 0 2006.260.07:20:20.57#ibcon#about to read 4, iclass 26, count 0 2006.260.07:20:20.57#ibcon#read 4, iclass 26, count 0 2006.260.07:20:20.57#ibcon#about to read 5, iclass 26, count 0 2006.260.07:20:20.57#ibcon#read 5, iclass 26, count 0 2006.260.07:20:20.57#ibcon#about to read 6, iclass 26, count 0 2006.260.07:20:20.57#ibcon#read 6, iclass 26, count 0 2006.260.07:20:20.57#ibcon#end of sib2, iclass 26, count 0 2006.260.07:20:20.57#ibcon#*after write, iclass 26, count 0 2006.260.07:20:20.57#ibcon#*before return 0, iclass 26, count 0 2006.260.07:20:20.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:20:20.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:20:20.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:20:20.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:20:20.57$vc4f8/vb=1,4 2006.260.07:20:20.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:20:20.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:20:20.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:20.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:20:20.57#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:20:20.57#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:20:20.57#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:20:20.57#ibcon#first serial, iclass 28, count 2 2006.260.07:20:20.57#ibcon#enter sib2, iclass 28, count 2 2006.260.07:20:20.57#ibcon#flushed, iclass 28, count 2 2006.260.07:20:20.57#ibcon#about to write, iclass 28, count 2 2006.260.07:20:20.57#ibcon#wrote, iclass 28, count 2 2006.260.07:20:20.57#ibcon#about to read 3, iclass 28, count 2 2006.260.07:20:20.59#ibcon#read 3, iclass 28, count 2 2006.260.07:20:20.59#ibcon#about to read 4, iclass 28, count 2 2006.260.07:20:20.59#ibcon#read 4, iclass 28, count 2 2006.260.07:20:20.59#ibcon#about to read 5, iclass 28, count 2 2006.260.07:20:20.59#ibcon#read 5, iclass 28, count 2 2006.260.07:20:20.59#ibcon#about to read 6, iclass 28, count 2 2006.260.07:20:20.59#ibcon#read 6, iclass 28, count 2 2006.260.07:20:20.59#ibcon#end of sib2, iclass 28, count 2 2006.260.07:20:20.59#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:20:20.59#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:20:20.59#ibcon#[27=AT01-04\r\n] 2006.260.07:20:20.59#ibcon#*before write, iclass 28, count 2 2006.260.07:20:20.59#ibcon#enter sib2, iclass 28, count 2 2006.260.07:20:20.59#ibcon#flushed, iclass 28, count 2 2006.260.07:20:20.59#ibcon#about to write, iclass 28, count 2 2006.260.07:20:20.59#ibcon#wrote, iclass 28, count 2 2006.260.07:20:20.59#ibcon#about to read 3, iclass 28, count 2 2006.260.07:20:20.62#ibcon#read 3, iclass 28, count 2 2006.260.07:20:20.62#ibcon#about to read 4, iclass 28, count 2 2006.260.07:20:20.62#ibcon#read 4, iclass 28, count 2 2006.260.07:20:20.62#ibcon#about to read 5, iclass 28, count 2 2006.260.07:20:20.62#ibcon#read 5, iclass 28, count 2 2006.260.07:20:20.62#ibcon#about to read 6, iclass 28, count 2 2006.260.07:20:20.62#ibcon#read 6, iclass 28, count 2 2006.260.07:20:20.62#ibcon#end of sib2, iclass 28, count 2 2006.260.07:20:20.62#ibcon#*after write, iclass 28, count 2 2006.260.07:20:20.62#ibcon#*before return 0, iclass 28, count 2 2006.260.07:20:20.62#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:20:20.62#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:20:20.62#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:20:20.62#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:20.62#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:20:20.74#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:20:20.74#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:20:20.74#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:20:20.74#ibcon#first serial, iclass 28, count 0 2006.260.07:20:20.74#ibcon#enter sib2, iclass 28, count 0 2006.260.07:20:20.74#ibcon#flushed, iclass 28, count 0 2006.260.07:20:20.74#ibcon#about to write, iclass 28, count 0 2006.260.07:20:20.74#ibcon#wrote, iclass 28, count 0 2006.260.07:20:20.74#ibcon#about to read 3, iclass 28, count 0 2006.260.07:20:20.76#ibcon#read 3, iclass 28, count 0 2006.260.07:20:20.76#ibcon#about to read 4, iclass 28, count 0 2006.260.07:20:20.76#ibcon#read 4, iclass 28, count 0 2006.260.07:20:20.76#ibcon#about to read 5, iclass 28, count 0 2006.260.07:20:20.76#ibcon#read 5, iclass 28, count 0 2006.260.07:20:20.76#ibcon#about to read 6, iclass 28, count 0 2006.260.07:20:20.76#ibcon#read 6, iclass 28, count 0 2006.260.07:20:20.76#ibcon#end of sib2, iclass 28, count 0 2006.260.07:20:20.76#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:20:20.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:20:20.76#ibcon#[27=USB\r\n] 2006.260.07:20:20.76#ibcon#*before write, iclass 28, count 0 2006.260.07:20:20.76#ibcon#enter sib2, iclass 28, count 0 2006.260.07:20:20.76#ibcon#flushed, iclass 28, count 0 2006.260.07:20:20.76#ibcon#about to write, iclass 28, count 0 2006.260.07:20:20.76#ibcon#wrote, iclass 28, count 0 2006.260.07:20:20.76#ibcon#about to read 3, iclass 28, count 0 2006.260.07:20:20.79#ibcon#read 3, iclass 28, count 0 2006.260.07:20:20.79#ibcon#about to read 4, iclass 28, count 0 2006.260.07:20:20.79#ibcon#read 4, iclass 28, count 0 2006.260.07:20:20.79#ibcon#about to read 5, iclass 28, count 0 2006.260.07:20:20.79#ibcon#read 5, iclass 28, count 0 2006.260.07:20:20.79#ibcon#about to read 6, iclass 28, count 0 2006.260.07:20:20.79#ibcon#read 6, iclass 28, count 0 2006.260.07:20:20.79#ibcon#end of sib2, iclass 28, count 0 2006.260.07:20:20.79#ibcon#*after write, iclass 28, count 0 2006.260.07:20:20.79#ibcon#*before return 0, iclass 28, count 0 2006.260.07:20:20.79#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:20:20.79#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:20:20.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:20:20.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:20:20.79$vc4f8/vblo=2,640.99 2006.260.07:20:20.79#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:20:20.79#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:20:20.79#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:20.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:20.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:20.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:20.79#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:20:20.79#ibcon#first serial, iclass 30, count 0 2006.260.07:20:20.79#ibcon#enter sib2, iclass 30, count 0 2006.260.07:20:20.79#ibcon#flushed, iclass 30, count 0 2006.260.07:20:20.79#ibcon#about to write, iclass 30, count 0 2006.260.07:20:20.79#ibcon#wrote, iclass 30, count 0 2006.260.07:20:20.79#ibcon#about to read 3, iclass 30, count 0 2006.260.07:20:20.81#ibcon#read 3, iclass 30, count 0 2006.260.07:20:20.81#ibcon#about to read 4, iclass 30, count 0 2006.260.07:20:20.81#ibcon#read 4, iclass 30, count 0 2006.260.07:20:20.81#ibcon#about to read 5, iclass 30, count 0 2006.260.07:20:20.81#ibcon#read 5, iclass 30, count 0 2006.260.07:20:20.81#ibcon#about to read 6, iclass 30, count 0 2006.260.07:20:20.81#ibcon#read 6, iclass 30, count 0 2006.260.07:20:20.81#ibcon#end of sib2, iclass 30, count 0 2006.260.07:20:20.81#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:20:20.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:20:20.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:20:20.81#ibcon#*before write, iclass 30, count 0 2006.260.07:20:20.81#ibcon#enter sib2, iclass 30, count 0 2006.260.07:20:20.81#ibcon#flushed, iclass 30, count 0 2006.260.07:20:20.81#ibcon#about to write, iclass 30, count 0 2006.260.07:20:20.81#ibcon#wrote, iclass 30, count 0 2006.260.07:20:20.81#ibcon#about to read 3, iclass 30, count 0 2006.260.07:20:20.85#ibcon#read 3, iclass 30, count 0 2006.260.07:20:20.85#ibcon#about to read 4, iclass 30, count 0 2006.260.07:20:20.85#ibcon#read 4, iclass 30, count 0 2006.260.07:20:20.85#ibcon#about to read 5, iclass 30, count 0 2006.260.07:20:20.85#ibcon#read 5, iclass 30, count 0 2006.260.07:20:20.85#ibcon#about to read 6, iclass 30, count 0 2006.260.07:20:20.85#ibcon#read 6, iclass 30, count 0 2006.260.07:20:20.85#ibcon#end of sib2, iclass 30, count 0 2006.260.07:20:20.85#ibcon#*after write, iclass 30, count 0 2006.260.07:20:20.85#ibcon#*before return 0, iclass 30, count 0 2006.260.07:20:20.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:20.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:20:20.85#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:20:20.85#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:20:20.85$vc4f8/vb=2,5 2006.260.07:20:20.85#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:20:20.85#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:20:20.85#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:20.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:20.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:20.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:20.91#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:20:20.91#ibcon#first serial, iclass 32, count 2 2006.260.07:20:20.91#ibcon#enter sib2, iclass 32, count 2 2006.260.07:20:20.91#ibcon#flushed, iclass 32, count 2 2006.260.07:20:20.91#ibcon#about to write, iclass 32, count 2 2006.260.07:20:20.91#ibcon#wrote, iclass 32, count 2 2006.260.07:20:20.91#ibcon#about to read 3, iclass 32, count 2 2006.260.07:20:20.93#ibcon#read 3, iclass 32, count 2 2006.260.07:20:20.93#ibcon#about to read 4, iclass 32, count 2 2006.260.07:20:20.93#ibcon#read 4, iclass 32, count 2 2006.260.07:20:20.93#ibcon#about to read 5, iclass 32, count 2 2006.260.07:20:20.93#ibcon#read 5, iclass 32, count 2 2006.260.07:20:20.93#ibcon#about to read 6, iclass 32, count 2 2006.260.07:20:20.93#ibcon#read 6, iclass 32, count 2 2006.260.07:20:20.93#ibcon#end of sib2, iclass 32, count 2 2006.260.07:20:20.93#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:20:20.93#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:20:20.93#ibcon#[27=AT02-05\r\n] 2006.260.07:20:20.93#ibcon#*before write, iclass 32, count 2 2006.260.07:20:20.93#ibcon#enter sib2, iclass 32, count 2 2006.260.07:20:20.93#ibcon#flushed, iclass 32, count 2 2006.260.07:20:20.93#ibcon#about to write, iclass 32, count 2 2006.260.07:20:20.93#ibcon#wrote, iclass 32, count 2 2006.260.07:20:20.93#ibcon#about to read 3, iclass 32, count 2 2006.260.07:20:20.96#ibcon#read 3, iclass 32, count 2 2006.260.07:20:20.96#ibcon#about to read 4, iclass 32, count 2 2006.260.07:20:20.96#ibcon#read 4, iclass 32, count 2 2006.260.07:20:20.96#ibcon#about to read 5, iclass 32, count 2 2006.260.07:20:20.96#ibcon#read 5, iclass 32, count 2 2006.260.07:20:20.96#ibcon#about to read 6, iclass 32, count 2 2006.260.07:20:20.96#ibcon#read 6, iclass 32, count 2 2006.260.07:20:20.96#ibcon#end of sib2, iclass 32, count 2 2006.260.07:20:20.96#ibcon#*after write, iclass 32, count 2 2006.260.07:20:20.96#ibcon#*before return 0, iclass 32, count 2 2006.260.07:20:20.96#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:20.96#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:20:20.96#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:20:20.96#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:20.96#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:21.08#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:21.08#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:21.08#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:20:21.08#ibcon#first serial, iclass 32, count 0 2006.260.07:20:21.08#ibcon#enter sib2, iclass 32, count 0 2006.260.07:20:21.08#ibcon#flushed, iclass 32, count 0 2006.260.07:20:21.08#ibcon#about to write, iclass 32, count 0 2006.260.07:20:21.08#ibcon#wrote, iclass 32, count 0 2006.260.07:20:21.08#ibcon#about to read 3, iclass 32, count 0 2006.260.07:20:21.10#ibcon#read 3, iclass 32, count 0 2006.260.07:20:21.10#ibcon#about to read 4, iclass 32, count 0 2006.260.07:20:21.10#ibcon#read 4, iclass 32, count 0 2006.260.07:20:21.10#ibcon#about to read 5, iclass 32, count 0 2006.260.07:20:21.10#ibcon#read 5, iclass 32, count 0 2006.260.07:20:21.10#ibcon#about to read 6, iclass 32, count 0 2006.260.07:20:21.10#ibcon#read 6, iclass 32, count 0 2006.260.07:20:21.10#ibcon#end of sib2, iclass 32, count 0 2006.260.07:20:21.10#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:20:21.10#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:20:21.10#ibcon#[27=USB\r\n] 2006.260.07:20:21.10#ibcon#*before write, iclass 32, count 0 2006.260.07:20:21.10#ibcon#enter sib2, iclass 32, count 0 2006.260.07:20:21.10#ibcon#flushed, iclass 32, count 0 2006.260.07:20:21.10#ibcon#about to write, iclass 32, count 0 2006.260.07:20:21.10#ibcon#wrote, iclass 32, count 0 2006.260.07:20:21.10#ibcon#about to read 3, iclass 32, count 0 2006.260.07:20:21.13#ibcon#read 3, iclass 32, count 0 2006.260.07:20:21.13#ibcon#about to read 4, iclass 32, count 0 2006.260.07:20:21.13#ibcon#read 4, iclass 32, count 0 2006.260.07:20:21.13#ibcon#about to read 5, iclass 32, count 0 2006.260.07:20:21.13#ibcon#read 5, iclass 32, count 0 2006.260.07:20:21.13#ibcon#about to read 6, iclass 32, count 0 2006.260.07:20:21.13#ibcon#read 6, iclass 32, count 0 2006.260.07:20:21.13#ibcon#end of sib2, iclass 32, count 0 2006.260.07:20:21.13#ibcon#*after write, iclass 32, count 0 2006.260.07:20:21.13#ibcon#*before return 0, iclass 32, count 0 2006.260.07:20:21.13#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:21.13#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:20:21.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:20:21.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:20:21.13$vc4f8/vblo=3,656.99 2006.260.07:20:21.13#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:20:21.13#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:20:21.13#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:21.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:21.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:21.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:21.13#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:20:21.13#ibcon#first serial, iclass 34, count 0 2006.260.07:20:21.13#ibcon#enter sib2, iclass 34, count 0 2006.260.07:20:21.13#ibcon#flushed, iclass 34, count 0 2006.260.07:20:21.13#ibcon#about to write, iclass 34, count 0 2006.260.07:20:21.13#ibcon#wrote, iclass 34, count 0 2006.260.07:20:21.13#ibcon#about to read 3, iclass 34, count 0 2006.260.07:20:21.15#ibcon#read 3, iclass 34, count 0 2006.260.07:20:21.15#ibcon#about to read 4, iclass 34, count 0 2006.260.07:20:21.15#ibcon#read 4, iclass 34, count 0 2006.260.07:20:21.15#ibcon#about to read 5, iclass 34, count 0 2006.260.07:20:21.15#ibcon#read 5, iclass 34, count 0 2006.260.07:20:21.15#ibcon#about to read 6, iclass 34, count 0 2006.260.07:20:21.15#ibcon#read 6, iclass 34, count 0 2006.260.07:20:21.15#ibcon#end of sib2, iclass 34, count 0 2006.260.07:20:21.15#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:20:21.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:20:21.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:20:21.15#ibcon#*before write, iclass 34, count 0 2006.260.07:20:21.15#ibcon#enter sib2, iclass 34, count 0 2006.260.07:20:21.15#ibcon#flushed, iclass 34, count 0 2006.260.07:20:21.15#ibcon#about to write, iclass 34, count 0 2006.260.07:20:21.15#ibcon#wrote, iclass 34, count 0 2006.260.07:20:21.15#ibcon#about to read 3, iclass 34, count 0 2006.260.07:20:21.19#ibcon#read 3, iclass 34, count 0 2006.260.07:20:21.19#ibcon#about to read 4, iclass 34, count 0 2006.260.07:20:21.19#ibcon#read 4, iclass 34, count 0 2006.260.07:20:21.19#ibcon#about to read 5, iclass 34, count 0 2006.260.07:20:21.19#ibcon#read 5, iclass 34, count 0 2006.260.07:20:21.19#ibcon#about to read 6, iclass 34, count 0 2006.260.07:20:21.19#ibcon#read 6, iclass 34, count 0 2006.260.07:20:21.19#ibcon#end of sib2, iclass 34, count 0 2006.260.07:20:21.19#ibcon#*after write, iclass 34, count 0 2006.260.07:20:21.19#ibcon#*before return 0, iclass 34, count 0 2006.260.07:20:21.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:21.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:20:21.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:20:21.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:20:21.19$vc4f8/vb=3,4 2006.260.07:20:21.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:20:21.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:20:21.19#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:21.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:21.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:21.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:21.25#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:20:21.25#ibcon#first serial, iclass 36, count 2 2006.260.07:20:21.25#ibcon#enter sib2, iclass 36, count 2 2006.260.07:20:21.25#ibcon#flushed, iclass 36, count 2 2006.260.07:20:21.25#ibcon#about to write, iclass 36, count 2 2006.260.07:20:21.25#ibcon#wrote, iclass 36, count 2 2006.260.07:20:21.25#ibcon#about to read 3, iclass 36, count 2 2006.260.07:20:21.27#ibcon#read 3, iclass 36, count 2 2006.260.07:20:21.27#ibcon#about to read 4, iclass 36, count 2 2006.260.07:20:21.27#ibcon#read 4, iclass 36, count 2 2006.260.07:20:21.27#ibcon#about to read 5, iclass 36, count 2 2006.260.07:20:21.27#ibcon#read 5, iclass 36, count 2 2006.260.07:20:21.27#ibcon#about to read 6, iclass 36, count 2 2006.260.07:20:21.27#ibcon#read 6, iclass 36, count 2 2006.260.07:20:21.27#ibcon#end of sib2, iclass 36, count 2 2006.260.07:20:21.27#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:20:21.27#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:20:21.27#ibcon#[27=AT03-04\r\n] 2006.260.07:20:21.27#ibcon#*before write, iclass 36, count 2 2006.260.07:20:21.27#ibcon#enter sib2, iclass 36, count 2 2006.260.07:20:21.27#ibcon#flushed, iclass 36, count 2 2006.260.07:20:21.27#ibcon#about to write, iclass 36, count 2 2006.260.07:20:21.27#ibcon#wrote, iclass 36, count 2 2006.260.07:20:21.27#ibcon#about to read 3, iclass 36, count 2 2006.260.07:20:21.30#ibcon#read 3, iclass 36, count 2 2006.260.07:20:21.30#ibcon#about to read 4, iclass 36, count 2 2006.260.07:20:21.30#ibcon#read 4, iclass 36, count 2 2006.260.07:20:21.30#ibcon#about to read 5, iclass 36, count 2 2006.260.07:20:21.30#ibcon#read 5, iclass 36, count 2 2006.260.07:20:21.30#ibcon#about to read 6, iclass 36, count 2 2006.260.07:20:21.30#ibcon#read 6, iclass 36, count 2 2006.260.07:20:21.30#ibcon#end of sib2, iclass 36, count 2 2006.260.07:20:21.30#ibcon#*after write, iclass 36, count 2 2006.260.07:20:21.30#ibcon#*before return 0, iclass 36, count 2 2006.260.07:20:21.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:21.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:20:21.30#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:20:21.30#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:21.30#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:21.42#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:21.42#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:21.42#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:20:21.42#ibcon#first serial, iclass 36, count 0 2006.260.07:20:21.42#ibcon#enter sib2, iclass 36, count 0 2006.260.07:20:21.42#ibcon#flushed, iclass 36, count 0 2006.260.07:20:21.42#ibcon#about to write, iclass 36, count 0 2006.260.07:20:21.42#ibcon#wrote, iclass 36, count 0 2006.260.07:20:21.42#ibcon#about to read 3, iclass 36, count 0 2006.260.07:20:21.44#ibcon#read 3, iclass 36, count 0 2006.260.07:20:21.44#ibcon#about to read 4, iclass 36, count 0 2006.260.07:20:21.44#ibcon#read 4, iclass 36, count 0 2006.260.07:20:21.44#ibcon#about to read 5, iclass 36, count 0 2006.260.07:20:21.44#ibcon#read 5, iclass 36, count 0 2006.260.07:20:21.44#ibcon#about to read 6, iclass 36, count 0 2006.260.07:20:21.44#ibcon#read 6, iclass 36, count 0 2006.260.07:20:21.44#ibcon#end of sib2, iclass 36, count 0 2006.260.07:20:21.44#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:20:21.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:20:21.44#ibcon#[27=USB\r\n] 2006.260.07:20:21.44#ibcon#*before write, iclass 36, count 0 2006.260.07:20:21.44#ibcon#enter sib2, iclass 36, count 0 2006.260.07:20:21.44#ibcon#flushed, iclass 36, count 0 2006.260.07:20:21.44#ibcon#about to write, iclass 36, count 0 2006.260.07:20:21.44#ibcon#wrote, iclass 36, count 0 2006.260.07:20:21.44#ibcon#about to read 3, iclass 36, count 0 2006.260.07:20:21.47#ibcon#read 3, iclass 36, count 0 2006.260.07:20:21.47#ibcon#about to read 4, iclass 36, count 0 2006.260.07:20:21.47#ibcon#read 4, iclass 36, count 0 2006.260.07:20:21.47#ibcon#about to read 5, iclass 36, count 0 2006.260.07:20:21.47#ibcon#read 5, iclass 36, count 0 2006.260.07:20:21.47#ibcon#about to read 6, iclass 36, count 0 2006.260.07:20:21.47#ibcon#read 6, iclass 36, count 0 2006.260.07:20:21.47#ibcon#end of sib2, iclass 36, count 0 2006.260.07:20:21.47#ibcon#*after write, iclass 36, count 0 2006.260.07:20:21.47#ibcon#*before return 0, iclass 36, count 0 2006.260.07:20:21.47#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:21.47#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:20:21.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:20:21.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:20:21.47$vc4f8/vblo=4,712.99 2006.260.07:20:21.47#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:20:21.47#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:20:21.47#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:21.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:21.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:21.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:21.47#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:20:21.47#ibcon#first serial, iclass 38, count 0 2006.260.07:20:21.47#ibcon#enter sib2, iclass 38, count 0 2006.260.07:20:21.47#ibcon#flushed, iclass 38, count 0 2006.260.07:20:21.47#ibcon#about to write, iclass 38, count 0 2006.260.07:20:21.47#ibcon#wrote, iclass 38, count 0 2006.260.07:20:21.47#ibcon#about to read 3, iclass 38, count 0 2006.260.07:20:21.49#ibcon#read 3, iclass 38, count 0 2006.260.07:20:21.49#ibcon#about to read 4, iclass 38, count 0 2006.260.07:20:21.49#ibcon#read 4, iclass 38, count 0 2006.260.07:20:21.49#ibcon#about to read 5, iclass 38, count 0 2006.260.07:20:21.49#ibcon#read 5, iclass 38, count 0 2006.260.07:20:21.49#ibcon#about to read 6, iclass 38, count 0 2006.260.07:20:21.49#ibcon#read 6, iclass 38, count 0 2006.260.07:20:21.49#ibcon#end of sib2, iclass 38, count 0 2006.260.07:20:21.49#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:20:21.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:20:21.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:20:21.49#ibcon#*before write, iclass 38, count 0 2006.260.07:20:21.49#ibcon#enter sib2, iclass 38, count 0 2006.260.07:20:21.49#ibcon#flushed, iclass 38, count 0 2006.260.07:20:21.49#ibcon#about to write, iclass 38, count 0 2006.260.07:20:21.49#ibcon#wrote, iclass 38, count 0 2006.260.07:20:21.49#ibcon#about to read 3, iclass 38, count 0 2006.260.07:20:21.53#ibcon#read 3, iclass 38, count 0 2006.260.07:20:21.53#ibcon#about to read 4, iclass 38, count 0 2006.260.07:20:21.53#ibcon#read 4, iclass 38, count 0 2006.260.07:20:21.53#ibcon#about to read 5, iclass 38, count 0 2006.260.07:20:21.53#ibcon#read 5, iclass 38, count 0 2006.260.07:20:21.53#ibcon#about to read 6, iclass 38, count 0 2006.260.07:20:21.53#ibcon#read 6, iclass 38, count 0 2006.260.07:20:21.53#ibcon#end of sib2, iclass 38, count 0 2006.260.07:20:21.53#ibcon#*after write, iclass 38, count 0 2006.260.07:20:21.53#ibcon#*before return 0, iclass 38, count 0 2006.260.07:20:21.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:21.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:20:21.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:20:21.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:20:21.53$vc4f8/vb=4,5 2006.260.07:20:21.53#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:20:21.53#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:20:21.53#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:21.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:21.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:21.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:21.59#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:20:21.59#ibcon#first serial, iclass 40, count 2 2006.260.07:20:21.59#ibcon#enter sib2, iclass 40, count 2 2006.260.07:20:21.59#ibcon#flushed, iclass 40, count 2 2006.260.07:20:21.59#ibcon#about to write, iclass 40, count 2 2006.260.07:20:21.59#ibcon#wrote, iclass 40, count 2 2006.260.07:20:21.59#ibcon#about to read 3, iclass 40, count 2 2006.260.07:20:21.61#ibcon#read 3, iclass 40, count 2 2006.260.07:20:21.61#ibcon#about to read 4, iclass 40, count 2 2006.260.07:20:21.61#ibcon#read 4, iclass 40, count 2 2006.260.07:20:21.61#ibcon#about to read 5, iclass 40, count 2 2006.260.07:20:21.61#ibcon#read 5, iclass 40, count 2 2006.260.07:20:21.61#ibcon#about to read 6, iclass 40, count 2 2006.260.07:20:21.61#ibcon#read 6, iclass 40, count 2 2006.260.07:20:21.61#ibcon#end of sib2, iclass 40, count 2 2006.260.07:20:21.61#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:20:21.61#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:20:21.61#ibcon#[27=AT04-05\r\n] 2006.260.07:20:21.61#ibcon#*before write, iclass 40, count 2 2006.260.07:20:21.61#ibcon#enter sib2, iclass 40, count 2 2006.260.07:20:21.61#ibcon#flushed, iclass 40, count 2 2006.260.07:20:21.61#ibcon#about to write, iclass 40, count 2 2006.260.07:20:21.61#ibcon#wrote, iclass 40, count 2 2006.260.07:20:21.61#ibcon#about to read 3, iclass 40, count 2 2006.260.07:20:21.64#ibcon#read 3, iclass 40, count 2 2006.260.07:20:21.64#ibcon#about to read 4, iclass 40, count 2 2006.260.07:20:21.64#ibcon#read 4, iclass 40, count 2 2006.260.07:20:21.64#ibcon#about to read 5, iclass 40, count 2 2006.260.07:20:21.64#ibcon#read 5, iclass 40, count 2 2006.260.07:20:21.64#ibcon#about to read 6, iclass 40, count 2 2006.260.07:20:21.64#ibcon#read 6, iclass 40, count 2 2006.260.07:20:21.64#ibcon#end of sib2, iclass 40, count 2 2006.260.07:20:21.64#ibcon#*after write, iclass 40, count 2 2006.260.07:20:21.64#ibcon#*before return 0, iclass 40, count 2 2006.260.07:20:21.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:21.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:20:21.64#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:20:21.64#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:21.64#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:21.76#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:21.76#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:21.76#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:20:21.76#ibcon#first serial, iclass 40, count 0 2006.260.07:20:21.76#ibcon#enter sib2, iclass 40, count 0 2006.260.07:20:21.76#ibcon#flushed, iclass 40, count 0 2006.260.07:20:21.76#ibcon#about to write, iclass 40, count 0 2006.260.07:20:21.76#ibcon#wrote, iclass 40, count 0 2006.260.07:20:21.76#ibcon#about to read 3, iclass 40, count 0 2006.260.07:20:21.78#ibcon#read 3, iclass 40, count 0 2006.260.07:20:21.78#ibcon#about to read 4, iclass 40, count 0 2006.260.07:20:21.78#ibcon#read 4, iclass 40, count 0 2006.260.07:20:21.78#ibcon#about to read 5, iclass 40, count 0 2006.260.07:20:21.78#ibcon#read 5, iclass 40, count 0 2006.260.07:20:21.78#ibcon#about to read 6, iclass 40, count 0 2006.260.07:20:21.78#ibcon#read 6, iclass 40, count 0 2006.260.07:20:21.78#ibcon#end of sib2, iclass 40, count 0 2006.260.07:20:21.78#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:20:21.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:20:21.78#ibcon#[27=USB\r\n] 2006.260.07:20:21.78#ibcon#*before write, iclass 40, count 0 2006.260.07:20:21.78#ibcon#enter sib2, iclass 40, count 0 2006.260.07:20:21.78#ibcon#flushed, iclass 40, count 0 2006.260.07:20:21.78#ibcon#about to write, iclass 40, count 0 2006.260.07:20:21.78#ibcon#wrote, iclass 40, count 0 2006.260.07:20:21.78#ibcon#about to read 3, iclass 40, count 0 2006.260.07:20:21.81#ibcon#read 3, iclass 40, count 0 2006.260.07:20:21.81#ibcon#about to read 4, iclass 40, count 0 2006.260.07:20:21.81#ibcon#read 4, iclass 40, count 0 2006.260.07:20:21.81#ibcon#about to read 5, iclass 40, count 0 2006.260.07:20:21.81#ibcon#read 5, iclass 40, count 0 2006.260.07:20:21.81#ibcon#about to read 6, iclass 40, count 0 2006.260.07:20:21.81#ibcon#read 6, iclass 40, count 0 2006.260.07:20:21.81#ibcon#end of sib2, iclass 40, count 0 2006.260.07:20:21.81#ibcon#*after write, iclass 40, count 0 2006.260.07:20:21.81#ibcon#*before return 0, iclass 40, count 0 2006.260.07:20:21.81#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:21.81#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:20:21.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:20:21.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:20:21.81$vc4f8/vblo=5,744.99 2006.260.07:20:21.81#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:20:21.81#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:20:21.81#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:21.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:21.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:21.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:21.81#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:20:21.81#ibcon#first serial, iclass 4, count 0 2006.260.07:20:21.81#ibcon#enter sib2, iclass 4, count 0 2006.260.07:20:21.81#ibcon#flushed, iclass 4, count 0 2006.260.07:20:21.81#ibcon#about to write, iclass 4, count 0 2006.260.07:20:21.81#ibcon#wrote, iclass 4, count 0 2006.260.07:20:21.81#ibcon#about to read 3, iclass 4, count 0 2006.260.07:20:21.83#ibcon#read 3, iclass 4, count 0 2006.260.07:20:21.83#ibcon#about to read 4, iclass 4, count 0 2006.260.07:20:21.83#ibcon#read 4, iclass 4, count 0 2006.260.07:20:21.83#ibcon#about to read 5, iclass 4, count 0 2006.260.07:20:21.83#ibcon#read 5, iclass 4, count 0 2006.260.07:20:21.83#ibcon#about to read 6, iclass 4, count 0 2006.260.07:20:21.83#ibcon#read 6, iclass 4, count 0 2006.260.07:20:21.83#ibcon#end of sib2, iclass 4, count 0 2006.260.07:20:21.83#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:20:21.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:20:21.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:20:21.83#ibcon#*before write, iclass 4, count 0 2006.260.07:20:21.83#ibcon#enter sib2, iclass 4, count 0 2006.260.07:20:21.83#ibcon#flushed, iclass 4, count 0 2006.260.07:20:21.83#ibcon#about to write, iclass 4, count 0 2006.260.07:20:21.83#ibcon#wrote, iclass 4, count 0 2006.260.07:20:21.83#ibcon#about to read 3, iclass 4, count 0 2006.260.07:20:21.87#ibcon#read 3, iclass 4, count 0 2006.260.07:20:21.87#ibcon#about to read 4, iclass 4, count 0 2006.260.07:20:21.87#ibcon#read 4, iclass 4, count 0 2006.260.07:20:21.87#ibcon#about to read 5, iclass 4, count 0 2006.260.07:20:21.87#ibcon#read 5, iclass 4, count 0 2006.260.07:20:21.87#ibcon#about to read 6, iclass 4, count 0 2006.260.07:20:21.87#ibcon#read 6, iclass 4, count 0 2006.260.07:20:21.87#ibcon#end of sib2, iclass 4, count 0 2006.260.07:20:21.87#ibcon#*after write, iclass 4, count 0 2006.260.07:20:21.87#ibcon#*before return 0, iclass 4, count 0 2006.260.07:20:21.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:21.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:20:21.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:20:21.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:20:21.87$vc4f8/vb=5,4 2006.260.07:20:21.87#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:20:21.87#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:20:21.87#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:21.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:21.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:21.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:21.93#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:20:21.93#ibcon#first serial, iclass 6, count 2 2006.260.07:20:21.93#ibcon#enter sib2, iclass 6, count 2 2006.260.07:20:21.93#ibcon#flushed, iclass 6, count 2 2006.260.07:20:21.93#ibcon#about to write, iclass 6, count 2 2006.260.07:20:21.93#ibcon#wrote, iclass 6, count 2 2006.260.07:20:21.93#ibcon#about to read 3, iclass 6, count 2 2006.260.07:20:21.95#ibcon#read 3, iclass 6, count 2 2006.260.07:20:21.95#ibcon#about to read 4, iclass 6, count 2 2006.260.07:20:21.95#ibcon#read 4, iclass 6, count 2 2006.260.07:20:21.95#ibcon#about to read 5, iclass 6, count 2 2006.260.07:20:21.95#ibcon#read 5, iclass 6, count 2 2006.260.07:20:21.95#ibcon#about to read 6, iclass 6, count 2 2006.260.07:20:21.95#ibcon#read 6, iclass 6, count 2 2006.260.07:20:21.95#ibcon#end of sib2, iclass 6, count 2 2006.260.07:20:21.95#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:20:21.95#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:20:21.95#ibcon#[27=AT05-04\r\n] 2006.260.07:20:21.95#ibcon#*before write, iclass 6, count 2 2006.260.07:20:21.95#ibcon#enter sib2, iclass 6, count 2 2006.260.07:20:21.95#ibcon#flushed, iclass 6, count 2 2006.260.07:20:21.95#ibcon#about to write, iclass 6, count 2 2006.260.07:20:21.95#ibcon#wrote, iclass 6, count 2 2006.260.07:20:21.95#ibcon#about to read 3, iclass 6, count 2 2006.260.07:20:21.98#ibcon#read 3, iclass 6, count 2 2006.260.07:20:21.98#ibcon#about to read 4, iclass 6, count 2 2006.260.07:20:21.98#ibcon#read 4, iclass 6, count 2 2006.260.07:20:21.98#ibcon#about to read 5, iclass 6, count 2 2006.260.07:20:21.98#ibcon#read 5, iclass 6, count 2 2006.260.07:20:21.98#ibcon#about to read 6, iclass 6, count 2 2006.260.07:20:21.98#ibcon#read 6, iclass 6, count 2 2006.260.07:20:21.98#ibcon#end of sib2, iclass 6, count 2 2006.260.07:20:21.98#ibcon#*after write, iclass 6, count 2 2006.260.07:20:21.98#ibcon#*before return 0, iclass 6, count 2 2006.260.07:20:21.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:21.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:20:21.98#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:20:21.98#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:21.98#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:22.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:22.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:22.10#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:20:22.10#ibcon#first serial, iclass 6, count 0 2006.260.07:20:22.10#ibcon#enter sib2, iclass 6, count 0 2006.260.07:20:22.10#ibcon#flushed, iclass 6, count 0 2006.260.07:20:22.10#ibcon#about to write, iclass 6, count 0 2006.260.07:20:22.10#ibcon#wrote, iclass 6, count 0 2006.260.07:20:22.10#ibcon#about to read 3, iclass 6, count 0 2006.260.07:20:22.12#ibcon#read 3, iclass 6, count 0 2006.260.07:20:22.12#ibcon#about to read 4, iclass 6, count 0 2006.260.07:20:22.12#ibcon#read 4, iclass 6, count 0 2006.260.07:20:22.12#ibcon#about to read 5, iclass 6, count 0 2006.260.07:20:22.12#ibcon#read 5, iclass 6, count 0 2006.260.07:20:22.12#ibcon#about to read 6, iclass 6, count 0 2006.260.07:20:22.12#ibcon#read 6, iclass 6, count 0 2006.260.07:20:22.12#ibcon#end of sib2, iclass 6, count 0 2006.260.07:20:22.12#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:20:22.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:20:22.12#ibcon#[27=USB\r\n] 2006.260.07:20:22.12#ibcon#*before write, iclass 6, count 0 2006.260.07:20:22.12#ibcon#enter sib2, iclass 6, count 0 2006.260.07:20:22.12#ibcon#flushed, iclass 6, count 0 2006.260.07:20:22.12#ibcon#about to write, iclass 6, count 0 2006.260.07:20:22.12#ibcon#wrote, iclass 6, count 0 2006.260.07:20:22.12#ibcon#about to read 3, iclass 6, count 0 2006.260.07:20:22.15#ibcon#read 3, iclass 6, count 0 2006.260.07:20:22.15#ibcon#about to read 4, iclass 6, count 0 2006.260.07:20:22.15#ibcon#read 4, iclass 6, count 0 2006.260.07:20:22.15#ibcon#about to read 5, iclass 6, count 0 2006.260.07:20:22.15#ibcon#read 5, iclass 6, count 0 2006.260.07:20:22.15#ibcon#about to read 6, iclass 6, count 0 2006.260.07:20:22.15#ibcon#read 6, iclass 6, count 0 2006.260.07:20:22.15#ibcon#end of sib2, iclass 6, count 0 2006.260.07:20:22.15#ibcon#*after write, iclass 6, count 0 2006.260.07:20:22.15#ibcon#*before return 0, iclass 6, count 0 2006.260.07:20:22.15#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:22.15#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:20:22.15#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:20:22.15#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:20:22.15$vc4f8/vblo=6,752.99 2006.260.07:20:22.15#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:20:22.15#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:20:22.15#ibcon#ireg 17 cls_cnt 0 2006.260.07:20:22.15#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:22.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:22.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:22.15#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:20:22.15#ibcon#first serial, iclass 10, count 0 2006.260.07:20:22.15#ibcon#enter sib2, iclass 10, count 0 2006.260.07:20:22.15#ibcon#flushed, iclass 10, count 0 2006.260.07:20:22.15#ibcon#about to write, iclass 10, count 0 2006.260.07:20:22.15#ibcon#wrote, iclass 10, count 0 2006.260.07:20:22.15#ibcon#about to read 3, iclass 10, count 0 2006.260.07:20:22.17#ibcon#read 3, iclass 10, count 0 2006.260.07:20:22.17#ibcon#about to read 4, iclass 10, count 0 2006.260.07:20:22.17#ibcon#read 4, iclass 10, count 0 2006.260.07:20:22.17#ibcon#about to read 5, iclass 10, count 0 2006.260.07:20:22.17#ibcon#read 5, iclass 10, count 0 2006.260.07:20:22.17#ibcon#about to read 6, iclass 10, count 0 2006.260.07:20:22.17#ibcon#read 6, iclass 10, count 0 2006.260.07:20:22.17#ibcon#end of sib2, iclass 10, count 0 2006.260.07:20:22.17#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:20:22.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:20:22.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:20:22.17#ibcon#*before write, iclass 10, count 0 2006.260.07:20:22.17#ibcon#enter sib2, iclass 10, count 0 2006.260.07:20:22.17#ibcon#flushed, iclass 10, count 0 2006.260.07:20:22.17#ibcon#about to write, iclass 10, count 0 2006.260.07:20:22.17#ibcon#wrote, iclass 10, count 0 2006.260.07:20:22.17#ibcon#about to read 3, iclass 10, count 0 2006.260.07:20:22.21#ibcon#read 3, iclass 10, count 0 2006.260.07:20:22.21#ibcon#about to read 4, iclass 10, count 0 2006.260.07:20:22.21#ibcon#read 4, iclass 10, count 0 2006.260.07:20:22.21#ibcon#about to read 5, iclass 10, count 0 2006.260.07:20:22.21#ibcon#read 5, iclass 10, count 0 2006.260.07:20:22.21#ibcon#about to read 6, iclass 10, count 0 2006.260.07:20:22.21#ibcon#read 6, iclass 10, count 0 2006.260.07:20:22.21#ibcon#end of sib2, iclass 10, count 0 2006.260.07:20:22.21#ibcon#*after write, iclass 10, count 0 2006.260.07:20:22.21#ibcon#*before return 0, iclass 10, count 0 2006.260.07:20:22.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:22.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:20:22.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:20:22.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:20:22.21$vc4f8/vb=6,4 2006.260.07:20:22.21#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:20:22.21#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:20:22.21#ibcon#ireg 11 cls_cnt 2 2006.260.07:20:22.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:22.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:22.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:22.27#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:20:22.27#ibcon#first serial, iclass 12, count 2 2006.260.07:20:22.27#ibcon#enter sib2, iclass 12, count 2 2006.260.07:20:22.27#ibcon#flushed, iclass 12, count 2 2006.260.07:20:22.27#ibcon#about to write, iclass 12, count 2 2006.260.07:20:22.27#ibcon#wrote, iclass 12, count 2 2006.260.07:20:22.27#ibcon#about to read 3, iclass 12, count 2 2006.260.07:20:22.29#ibcon#read 3, iclass 12, count 2 2006.260.07:20:22.29#ibcon#about to read 4, iclass 12, count 2 2006.260.07:20:22.29#ibcon#read 4, iclass 12, count 2 2006.260.07:20:22.29#ibcon#about to read 5, iclass 12, count 2 2006.260.07:20:22.29#ibcon#read 5, iclass 12, count 2 2006.260.07:20:22.29#ibcon#about to read 6, iclass 12, count 2 2006.260.07:20:22.29#ibcon#read 6, iclass 12, count 2 2006.260.07:20:22.29#ibcon#end of sib2, iclass 12, count 2 2006.260.07:20:22.29#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:20:22.29#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:20:22.29#ibcon#[27=AT06-04\r\n] 2006.260.07:20:22.29#ibcon#*before write, iclass 12, count 2 2006.260.07:20:22.29#ibcon#enter sib2, iclass 12, count 2 2006.260.07:20:22.29#ibcon#flushed, iclass 12, count 2 2006.260.07:20:22.29#ibcon#about to write, iclass 12, count 2 2006.260.07:20:22.29#ibcon#wrote, iclass 12, count 2 2006.260.07:20:22.29#ibcon#about to read 3, iclass 12, count 2 2006.260.07:20:22.32#ibcon#read 3, iclass 12, count 2 2006.260.07:20:22.32#ibcon#about to read 4, iclass 12, count 2 2006.260.07:20:22.32#ibcon#read 4, iclass 12, count 2 2006.260.07:20:22.32#ibcon#about to read 5, iclass 12, count 2 2006.260.07:20:22.32#ibcon#read 5, iclass 12, count 2 2006.260.07:20:22.32#ibcon#about to read 6, iclass 12, count 2 2006.260.07:20:22.32#ibcon#read 6, iclass 12, count 2 2006.260.07:20:22.32#ibcon#end of sib2, iclass 12, count 2 2006.260.07:20:22.32#ibcon#*after write, iclass 12, count 2 2006.260.07:20:22.32#ibcon#*before return 0, iclass 12, count 2 2006.260.07:20:22.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:22.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:20:22.32#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:20:22.32#ibcon#ireg 7 cls_cnt 0 2006.260.07:20:22.32#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:22.44#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:22.44#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:22.44#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:20:22.44#ibcon#first serial, iclass 12, count 0 2006.260.07:20:22.44#ibcon#enter sib2, iclass 12, count 0 2006.260.07:20:22.44#ibcon#flushed, iclass 12, count 0 2006.260.07:20:22.44#ibcon#about to write, iclass 12, count 0 2006.260.07:20:22.44#ibcon#wrote, iclass 12, count 0 2006.260.07:20:22.44#ibcon#about to read 3, iclass 12, count 0 2006.260.07:20:22.46#ibcon#read 3, iclass 12, count 0 2006.260.07:20:22.46#ibcon#about to read 4, iclass 12, count 0 2006.260.07:20:22.46#ibcon#read 4, iclass 12, count 0 2006.260.07:20:22.46#ibcon#about to read 5, iclass 12, count 0 2006.260.07:20:22.46#ibcon#read 5, iclass 12, count 0 2006.260.07:20:22.46#ibcon#about to read 6, iclass 12, count 0 2006.260.07:20:22.46#ibcon#read 6, iclass 12, count 0 2006.260.07:20:22.46#ibcon#end of sib2, iclass 12, count 0 2006.260.07:20:22.46#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:20:22.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:20:22.46#ibcon#[27=USB\r\n] 2006.260.07:20:22.46#ibcon#*before write, iclass 12, count 0 2006.260.07:20:22.46#ibcon#enter sib2, iclass 12, count 0 2006.260.07:20:22.46#ibcon#flushed, iclass 12, count 0 2006.260.07:20:22.46#ibcon#about to write, iclass 12, count 0 2006.260.07:20:22.46#ibcon#wrote, iclass 12, count 0 2006.260.07:20:22.46#ibcon#about to read 3, iclass 12, count 0 2006.260.07:20:22.49#ibcon#read 3, iclass 12, count 0 2006.260.07:20:22.49#ibcon#about to read 4, iclass 12, count 0 2006.260.07:20:22.49#ibcon#read 4, iclass 12, count 0 2006.260.07:20:22.49#ibcon#about to read 5, iclass 12, count 0 2006.260.07:20:22.49#ibcon#read 5, iclass 12, count 0 2006.260.07:20:22.49#ibcon#about to read 6, iclass 12, count 0 2006.260.07:20:22.49#ibcon#read 6, iclass 12, count 0 2006.260.07:20:22.49#ibcon#end of sib2, iclass 12, count 0 2006.260.07:20:22.49#ibcon#*after write, iclass 12, count 0 2006.260.07:20:22.49#ibcon#*before return 0, iclass 12, count 0 2006.260.07:20:22.49#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:22.49#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:20:22.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:20:22.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:20:22.49$vc4f8/vabw=wide 2006.260.07:20:22.49#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:20:22.49#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:20:22.49#ibcon#ireg 8 cls_cnt 0 2006.260.07:20:22.49#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:22.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:22.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:22.49#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:20:22.49#ibcon#first serial, iclass 14, count 0 2006.260.07:20:22.49#ibcon#enter sib2, iclass 14, count 0 2006.260.07:20:22.49#ibcon#flushed, iclass 14, count 0 2006.260.07:20:22.49#ibcon#about to write, iclass 14, count 0 2006.260.07:20:22.49#ibcon#wrote, iclass 14, count 0 2006.260.07:20:22.49#ibcon#about to read 3, iclass 14, count 0 2006.260.07:20:22.51#ibcon#read 3, iclass 14, count 0 2006.260.07:20:22.51#ibcon#about to read 4, iclass 14, count 0 2006.260.07:20:22.51#ibcon#read 4, iclass 14, count 0 2006.260.07:20:22.51#ibcon#about to read 5, iclass 14, count 0 2006.260.07:20:22.51#ibcon#read 5, iclass 14, count 0 2006.260.07:20:22.51#ibcon#about to read 6, iclass 14, count 0 2006.260.07:20:22.51#ibcon#read 6, iclass 14, count 0 2006.260.07:20:22.51#ibcon#end of sib2, iclass 14, count 0 2006.260.07:20:22.51#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:20:22.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:20:22.51#ibcon#[25=BW32\r\n] 2006.260.07:20:22.51#ibcon#*before write, iclass 14, count 0 2006.260.07:20:22.51#ibcon#enter sib2, iclass 14, count 0 2006.260.07:20:22.51#ibcon#flushed, iclass 14, count 0 2006.260.07:20:22.51#ibcon#about to write, iclass 14, count 0 2006.260.07:20:22.51#ibcon#wrote, iclass 14, count 0 2006.260.07:20:22.51#ibcon#about to read 3, iclass 14, count 0 2006.260.07:20:22.54#ibcon#read 3, iclass 14, count 0 2006.260.07:20:22.54#ibcon#about to read 4, iclass 14, count 0 2006.260.07:20:22.54#ibcon#read 4, iclass 14, count 0 2006.260.07:20:22.54#ibcon#about to read 5, iclass 14, count 0 2006.260.07:20:22.54#ibcon#read 5, iclass 14, count 0 2006.260.07:20:22.54#ibcon#about to read 6, iclass 14, count 0 2006.260.07:20:22.54#ibcon#read 6, iclass 14, count 0 2006.260.07:20:22.54#ibcon#end of sib2, iclass 14, count 0 2006.260.07:20:22.54#ibcon#*after write, iclass 14, count 0 2006.260.07:20:22.54#ibcon#*before return 0, iclass 14, count 0 2006.260.07:20:22.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:22.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:20:22.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:20:22.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:20:22.54$vc4f8/vbbw=wide 2006.260.07:20:22.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:20:22.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:20:22.54#ibcon#ireg 8 cls_cnt 0 2006.260.07:20:22.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:20:22.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:20:22.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:20:22.61#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:20:22.61#ibcon#first serial, iclass 16, count 0 2006.260.07:20:22.61#ibcon#enter sib2, iclass 16, count 0 2006.260.07:20:22.61#ibcon#flushed, iclass 16, count 0 2006.260.07:20:22.61#ibcon#about to write, iclass 16, count 0 2006.260.07:20:22.61#ibcon#wrote, iclass 16, count 0 2006.260.07:20:22.61#ibcon#about to read 3, iclass 16, count 0 2006.260.07:20:22.63#ibcon#read 3, iclass 16, count 0 2006.260.07:20:22.63#ibcon#about to read 4, iclass 16, count 0 2006.260.07:20:22.63#ibcon#read 4, iclass 16, count 0 2006.260.07:20:22.63#ibcon#about to read 5, iclass 16, count 0 2006.260.07:20:22.63#ibcon#read 5, iclass 16, count 0 2006.260.07:20:22.63#ibcon#about to read 6, iclass 16, count 0 2006.260.07:20:22.63#ibcon#read 6, iclass 16, count 0 2006.260.07:20:22.63#ibcon#end of sib2, iclass 16, count 0 2006.260.07:20:22.63#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:20:22.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:20:22.63#ibcon#[27=BW32\r\n] 2006.260.07:20:22.63#ibcon#*before write, iclass 16, count 0 2006.260.07:20:22.63#ibcon#enter sib2, iclass 16, count 0 2006.260.07:20:22.63#ibcon#flushed, iclass 16, count 0 2006.260.07:20:22.63#ibcon#about to write, iclass 16, count 0 2006.260.07:20:22.63#ibcon#wrote, iclass 16, count 0 2006.260.07:20:22.63#ibcon#about to read 3, iclass 16, count 0 2006.260.07:20:22.66#ibcon#read 3, iclass 16, count 0 2006.260.07:20:22.66#ibcon#about to read 4, iclass 16, count 0 2006.260.07:20:22.66#ibcon#read 4, iclass 16, count 0 2006.260.07:20:22.66#ibcon#about to read 5, iclass 16, count 0 2006.260.07:20:22.66#ibcon#read 5, iclass 16, count 0 2006.260.07:20:22.66#ibcon#about to read 6, iclass 16, count 0 2006.260.07:20:22.66#ibcon#read 6, iclass 16, count 0 2006.260.07:20:22.66#ibcon#end of sib2, iclass 16, count 0 2006.260.07:20:22.66#ibcon#*after write, iclass 16, count 0 2006.260.07:20:22.66#ibcon#*before return 0, iclass 16, count 0 2006.260.07:20:22.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:20:22.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:20:22.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:20:22.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:20:22.66$4f8m12a/ifd4f 2006.260.07:20:22.66&ifd4f/lo= 2006.260.07:20:22.66&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:20:22.66&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:20:22.66&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:20:22.66&ifd4f/patch= 2006.260.07:20:22.66&ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:20:22.66&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:20:22.66&ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:20:22.66$ifd4f/lo= 2006.260.07:20:22.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:20:22.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:20:22.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:20:22.67$ifd4f/patch= 2006.260.07:20:22.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:20:22.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:20:22.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:20:22.67$4f8m12a/"form=m,16.000,1:2 2006.260.07:20:22.67$4f8m12a/"tpicd 2006.260.07:20:22.67$4f8m12a/echo=off 2006.260.07:20:22.67$4f8m12a/xlog=off 2006.260.07:20:22.67:!2006.260.07:29:50 2006.260.07:20:30.14#trakl#Source acquired 2006.260.07:20:32.14#flagr#flagr/antenna,acquired 2006.260.07:29:50.00:preob 2006.260.07:29:50.00&preob/onsource 2006.260.07:29:51.14/onsource/TRACKING 2006.260.07:29:51.14:!2006.260.07:30:00 2006.260.07:30:00.00:data_valid=on 2006.260.07:30:00.00:midob 2006.260.07:30:00.00&midob/onsource 2006.260.07:30:00.00&midob/wx 2006.260.07:30:00.00&midob/cable 2006.260.07:30:00.00&midob/va 2006.260.07:30:00.00&midob/valo 2006.260.07:30:00.00&midob/vb 2006.260.07:30:00.00&midob/vblo 2006.260.07:30:00.00&midob/vabw 2006.260.07:30:00.00&midob/vbbw 2006.260.07:30:00.00&midob/"form 2006.260.07:30:00.00&midob/xfe 2006.260.07:30:00.00&midob/ifatt 2006.260.07:30:00.00&midob/clockoff 2006.260.07:30:00.00&midob/sy=logmail 2006.260.07:30:00.00&midob/"sy=run setcl adapt & 2006.260.07:30:00.14/onsource/TRACKING 2006.260.07:30:00.14/wx/23.20,1010.3,86 2006.260.07:30:00.31/cable/+6.4556E-03 2006.260.07:30:01.40/va/01,08,usb,yes,31,32 2006.260.07:30:01.40/va/02,07,usb,yes,31,32 2006.260.07:30:01.40/va/03,08,usb,yes,23,24 2006.260.07:30:01.40/va/04,07,usb,yes,32,35 2006.260.07:30:01.40/va/05,07,usb,yes,35,37 2006.260.07:30:01.40/va/06,06,usb,yes,34,34 2006.260.07:30:01.40/va/07,06,usb,yes,35,35 2006.260.07:30:01.40/va/08,06,usb,yes,37,37 2006.260.07:30:01.63/valo/01,532.99,yes,locked 2006.260.07:30:01.63/valo/02,572.99,yes,locked 2006.260.07:30:01.63/valo/03,672.99,yes,locked 2006.260.07:30:01.63/valo/04,832.99,yes,locked 2006.260.07:30:01.63/valo/05,652.99,yes,locked 2006.260.07:30:01.63/valo/06,772.99,yes,locked 2006.260.07:30:01.63/valo/07,832.99,yes,locked 2006.260.07:30:01.63/valo/08,852.99,yes,locked 2006.260.07:30:02.72/vb/01,04,usb,yes,30,29 2006.260.07:30:02.72/vb/02,05,usb,yes,28,29 2006.260.07:30:02.72/vb/03,04,usb,yes,28,32 2006.260.07:30:02.72/vb/04,05,usb,yes,26,26 2006.260.07:30:02.72/vb/05,04,usb,yes,27,31 2006.260.07:30:02.72/vb/06,04,usb,yes,28,31 2006.260.07:30:02.72/vb/07,04,usb,yes,31,30 2006.260.07:30:02.72/vb/08,04,usb,yes,28,31 2006.260.07:30:02.95/vblo/01,632.99,yes,locked 2006.260.07:30:02.95/vblo/02,640.99,yes,locked 2006.260.07:30:02.95/vblo/03,656.99,yes,locked 2006.260.07:30:02.95/vblo/04,712.99,yes,locked 2006.260.07:30:02.95/vblo/05,744.99,yes,locked 2006.260.07:30:02.95/vblo/06,752.99,yes,locked 2006.260.07:30:02.95/vblo/07,734.99,yes,locked 2006.260.07:30:02.95/vblo/08,744.99,yes,locked 2006.260.07:30:03.10/vabw/8 2006.260.07:30:03.25/vbbw/8 2006.260.07:30:03.34/xfe/off,on,15.0 2006.260.07:30:03.72/ifatt/23,28,28,28 2006.260.07:30:03.72&clockoff/"gps-fmout=1p 2006.260.07:30:03.72&clockoff/fmout-gps=1p 2006.260.07:30:04.08/fmout-gps/S +4.47E-07 2006.260.07:30:04.16:!2006.260.07:31:00 2006.260.07:31:00.01:data_valid=off 2006.260.07:31:00.02:postob 2006.260.07:31:00.02&postob/cable 2006.260.07:31:00.02&postob/wx 2006.260.07:31:00.03&postob/clockoff 2006.260.07:31:00.11/cable/+6.4574E-03 2006.260.07:31:00.11/wx/23.18,1010.3,86 2006.260.07:31:00.19/fmout-gps/S +4.47E-07 2006.260.07:31:00.20:scan_name=260-0733,k06260,60 2006.260.07:31:00.20:source=0059+581,010245.76,582411.1,2000.0,cw 2006.260.07:31:01.14#flagr#flagr/antenna,new-source 2006.260.07:31:01.14:checkk5 2006.260.07:31:01.14&checkk5/chk_autoobs=1 2006.260.07:31:01.14&checkk5/chk_autoobs=2 2006.260.07:31:01.14&checkk5/chk_autoobs=3 2006.260.07:31:01.14&checkk5/chk_autoobs=4 2006.260.07:31:01.14&checkk5/chk_obsdata=1 2006.260.07:31:01.14&checkk5/chk_obsdata=2 2006.260.07:31:01.14&checkk5/chk_obsdata=3 2006.260.07:31:01.14&checkk5/chk_obsdata=4 2006.260.07:31:01.14&checkk5/k5log=1 2006.260.07:31:01.14&checkk5/k5log=2 2006.260.07:31:01.14&checkk5/k5log=3 2006.260.07:31:01.14&checkk5/k5log=4 2006.260.07:31:01.14&checkk5/obsinfo 2006.260.07:31:02.08/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:31:02.49/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:31:02.93/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:31:03.35/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:31:03.74/chk_obsdata//k5ts1/T2600730??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:31:04.13/chk_obsdata//k5ts2/T2600730??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:31:04.54/chk_obsdata//k5ts3/T2600730??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:31:04.94/chk_obsdata//k5ts4/T2600730??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:31:05.77/k5log//k5ts1_log_newline 2006.260.07:31:06.55/k5log//k5ts2_log_newline 2006.260.07:31:07.38/k5log//k5ts3_log_newline 2006.260.07:31:08.16/k5log//k5ts4_log_newline 2006.260.07:31:08.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:31:08.22:4f8m12a=1 2006.260.07:31:08.22$4f8m12a/echo=on 2006.260.07:31:08.22$4f8m12a/pcalon 2006.260.07:31:08.22$pcalon/"no phase cal control is implemented here 2006.260.07:31:08.22$4f8m12a/"tpicd=stop 2006.260.07:31:08.22$4f8m12a/vc4f8 2006.260.07:31:08.22$vc4f8/valo=1,532.99 2006.260.07:31:08.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:31:08.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:31:08.22#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:08.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:08.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:08.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:08.22#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:31:08.22#ibcon#first serial, iclass 14, count 0 2006.260.07:31:08.22#ibcon#enter sib2, iclass 14, count 0 2006.260.07:31:08.22#ibcon#flushed, iclass 14, count 0 2006.260.07:31:08.22#ibcon#about to write, iclass 14, count 0 2006.260.07:31:08.22#ibcon#wrote, iclass 14, count 0 2006.260.07:31:08.22#ibcon#about to read 3, iclass 14, count 0 2006.260.07:31:08.24#ibcon#read 3, iclass 14, count 0 2006.260.07:31:08.24#ibcon#about to read 4, iclass 14, count 0 2006.260.07:31:08.24#ibcon#read 4, iclass 14, count 0 2006.260.07:31:08.24#ibcon#about to read 5, iclass 14, count 0 2006.260.07:31:08.24#ibcon#read 5, iclass 14, count 0 2006.260.07:31:08.24#ibcon#about to read 6, iclass 14, count 0 2006.260.07:31:08.24#ibcon#read 6, iclass 14, count 0 2006.260.07:31:08.24#ibcon#end of sib2, iclass 14, count 0 2006.260.07:31:08.24#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:31:08.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:31:08.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:31:08.24#ibcon#*before write, iclass 14, count 0 2006.260.07:31:08.24#ibcon#enter sib2, iclass 14, count 0 2006.260.07:31:08.24#ibcon#flushed, iclass 14, count 0 2006.260.07:31:08.24#ibcon#about to write, iclass 14, count 0 2006.260.07:31:08.24#ibcon#wrote, iclass 14, count 0 2006.260.07:31:08.24#ibcon#about to read 3, iclass 14, count 0 2006.260.07:31:08.29#ibcon#read 3, iclass 14, count 0 2006.260.07:31:08.29#ibcon#about to read 4, iclass 14, count 0 2006.260.07:31:08.29#ibcon#read 4, iclass 14, count 0 2006.260.07:31:08.29#ibcon#about to read 5, iclass 14, count 0 2006.260.07:31:08.29#ibcon#read 5, iclass 14, count 0 2006.260.07:31:08.29#ibcon#about to read 6, iclass 14, count 0 2006.260.07:31:08.29#ibcon#read 6, iclass 14, count 0 2006.260.07:31:08.29#ibcon#end of sib2, iclass 14, count 0 2006.260.07:31:08.29#ibcon#*after write, iclass 14, count 0 2006.260.07:31:08.29#ibcon#*before return 0, iclass 14, count 0 2006.260.07:31:08.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:08.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:08.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:31:08.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:31:08.29$vc4f8/va=1,8 2006.260.07:31:08.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:31:08.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:31:08.29#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:08.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:08.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:08.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:08.29#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:31:08.29#ibcon#first serial, iclass 16, count 2 2006.260.07:31:08.29#ibcon#enter sib2, iclass 16, count 2 2006.260.07:31:08.29#ibcon#flushed, iclass 16, count 2 2006.260.07:31:08.29#ibcon#about to write, iclass 16, count 2 2006.260.07:31:08.29#ibcon#wrote, iclass 16, count 2 2006.260.07:31:08.29#ibcon#about to read 3, iclass 16, count 2 2006.260.07:31:08.31#ibcon#read 3, iclass 16, count 2 2006.260.07:31:08.31#ibcon#about to read 4, iclass 16, count 2 2006.260.07:31:08.31#ibcon#read 4, iclass 16, count 2 2006.260.07:31:08.31#ibcon#about to read 5, iclass 16, count 2 2006.260.07:31:08.31#ibcon#read 5, iclass 16, count 2 2006.260.07:31:08.31#ibcon#about to read 6, iclass 16, count 2 2006.260.07:31:08.31#ibcon#read 6, iclass 16, count 2 2006.260.07:31:08.31#ibcon#end of sib2, iclass 16, count 2 2006.260.07:31:08.31#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:31:08.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:31:08.31#ibcon#[25=AT01-08\r\n] 2006.260.07:31:08.31#ibcon#*before write, iclass 16, count 2 2006.260.07:31:08.31#ibcon#enter sib2, iclass 16, count 2 2006.260.07:31:08.31#ibcon#flushed, iclass 16, count 2 2006.260.07:31:08.31#ibcon#about to write, iclass 16, count 2 2006.260.07:31:08.31#ibcon#wrote, iclass 16, count 2 2006.260.07:31:08.31#ibcon#about to read 3, iclass 16, count 2 2006.260.07:31:08.34#ibcon#read 3, iclass 16, count 2 2006.260.07:31:08.34#ibcon#about to read 4, iclass 16, count 2 2006.260.07:31:08.34#ibcon#read 4, iclass 16, count 2 2006.260.07:31:08.34#ibcon#about to read 5, iclass 16, count 2 2006.260.07:31:08.34#ibcon#read 5, iclass 16, count 2 2006.260.07:31:08.34#ibcon#about to read 6, iclass 16, count 2 2006.260.07:31:08.34#ibcon#read 6, iclass 16, count 2 2006.260.07:31:08.34#ibcon#end of sib2, iclass 16, count 2 2006.260.07:31:08.34#ibcon#*after write, iclass 16, count 2 2006.260.07:31:08.34#ibcon#*before return 0, iclass 16, count 2 2006.260.07:31:08.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:08.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:08.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:31:08.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:08.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:08.46#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:08.46#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:08.46#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:31:08.46#ibcon#first serial, iclass 16, count 0 2006.260.07:31:08.46#ibcon#enter sib2, iclass 16, count 0 2006.260.07:31:08.46#ibcon#flushed, iclass 16, count 0 2006.260.07:31:08.46#ibcon#about to write, iclass 16, count 0 2006.260.07:31:08.46#ibcon#wrote, iclass 16, count 0 2006.260.07:31:08.46#ibcon#about to read 3, iclass 16, count 0 2006.260.07:31:08.48#ibcon#read 3, iclass 16, count 0 2006.260.07:31:08.48#ibcon#about to read 4, iclass 16, count 0 2006.260.07:31:08.48#ibcon#read 4, iclass 16, count 0 2006.260.07:31:08.48#ibcon#about to read 5, iclass 16, count 0 2006.260.07:31:08.48#ibcon#read 5, iclass 16, count 0 2006.260.07:31:08.48#ibcon#about to read 6, iclass 16, count 0 2006.260.07:31:08.48#ibcon#read 6, iclass 16, count 0 2006.260.07:31:08.48#ibcon#end of sib2, iclass 16, count 0 2006.260.07:31:08.48#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:31:08.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:31:08.48#ibcon#[25=USB\r\n] 2006.260.07:31:08.48#ibcon#*before write, iclass 16, count 0 2006.260.07:31:08.48#ibcon#enter sib2, iclass 16, count 0 2006.260.07:31:08.48#ibcon#flushed, iclass 16, count 0 2006.260.07:31:08.48#ibcon#about to write, iclass 16, count 0 2006.260.07:31:08.48#ibcon#wrote, iclass 16, count 0 2006.260.07:31:08.48#ibcon#about to read 3, iclass 16, count 0 2006.260.07:31:08.51#ibcon#read 3, iclass 16, count 0 2006.260.07:31:08.51#ibcon#about to read 4, iclass 16, count 0 2006.260.07:31:08.51#ibcon#read 4, iclass 16, count 0 2006.260.07:31:08.51#ibcon#about to read 5, iclass 16, count 0 2006.260.07:31:08.51#ibcon#read 5, iclass 16, count 0 2006.260.07:31:08.51#ibcon#about to read 6, iclass 16, count 0 2006.260.07:31:08.51#ibcon#read 6, iclass 16, count 0 2006.260.07:31:08.51#ibcon#end of sib2, iclass 16, count 0 2006.260.07:31:08.51#ibcon#*after write, iclass 16, count 0 2006.260.07:31:08.51#ibcon#*before return 0, iclass 16, count 0 2006.260.07:31:08.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:08.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:08.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:31:08.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:31:08.51$vc4f8/valo=2,572.99 2006.260.07:31:08.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:31:08.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:31:08.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:08.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:08.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:08.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:08.51#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:31:08.51#ibcon#first serial, iclass 18, count 0 2006.260.07:31:08.51#ibcon#enter sib2, iclass 18, count 0 2006.260.07:31:08.51#ibcon#flushed, iclass 18, count 0 2006.260.07:31:08.51#ibcon#about to write, iclass 18, count 0 2006.260.07:31:08.51#ibcon#wrote, iclass 18, count 0 2006.260.07:31:08.51#ibcon#about to read 3, iclass 18, count 0 2006.260.07:31:08.53#ibcon#read 3, iclass 18, count 0 2006.260.07:31:08.53#ibcon#about to read 4, iclass 18, count 0 2006.260.07:31:08.53#ibcon#read 4, iclass 18, count 0 2006.260.07:31:08.53#ibcon#about to read 5, iclass 18, count 0 2006.260.07:31:08.53#ibcon#read 5, iclass 18, count 0 2006.260.07:31:08.53#ibcon#about to read 6, iclass 18, count 0 2006.260.07:31:08.53#ibcon#read 6, iclass 18, count 0 2006.260.07:31:08.53#ibcon#end of sib2, iclass 18, count 0 2006.260.07:31:08.53#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:31:08.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:31:08.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:31:08.53#ibcon#*before write, iclass 18, count 0 2006.260.07:31:08.53#ibcon#enter sib2, iclass 18, count 0 2006.260.07:31:08.53#ibcon#flushed, iclass 18, count 0 2006.260.07:31:08.53#ibcon#about to write, iclass 18, count 0 2006.260.07:31:08.53#ibcon#wrote, iclass 18, count 0 2006.260.07:31:08.53#ibcon#about to read 3, iclass 18, count 0 2006.260.07:31:08.57#ibcon#read 3, iclass 18, count 0 2006.260.07:31:08.57#ibcon#about to read 4, iclass 18, count 0 2006.260.07:31:08.57#ibcon#read 4, iclass 18, count 0 2006.260.07:31:08.57#ibcon#about to read 5, iclass 18, count 0 2006.260.07:31:08.57#ibcon#read 5, iclass 18, count 0 2006.260.07:31:08.57#ibcon#about to read 6, iclass 18, count 0 2006.260.07:31:08.57#ibcon#read 6, iclass 18, count 0 2006.260.07:31:08.57#ibcon#end of sib2, iclass 18, count 0 2006.260.07:31:08.57#ibcon#*after write, iclass 18, count 0 2006.260.07:31:08.57#ibcon#*before return 0, iclass 18, count 0 2006.260.07:31:08.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:08.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:08.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:31:08.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:31:08.57$vc4f8/va=2,7 2006.260.07:31:08.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:31:08.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:31:08.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:08.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:08.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:08.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:08.63#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:31:08.63#ibcon#first serial, iclass 20, count 2 2006.260.07:31:08.63#ibcon#enter sib2, iclass 20, count 2 2006.260.07:31:08.63#ibcon#flushed, iclass 20, count 2 2006.260.07:31:08.63#ibcon#about to write, iclass 20, count 2 2006.260.07:31:08.63#ibcon#wrote, iclass 20, count 2 2006.260.07:31:08.63#ibcon#about to read 3, iclass 20, count 2 2006.260.07:31:08.66#ibcon#read 3, iclass 20, count 2 2006.260.07:31:08.66#ibcon#about to read 4, iclass 20, count 2 2006.260.07:31:08.66#ibcon#read 4, iclass 20, count 2 2006.260.07:31:08.66#ibcon#about to read 5, iclass 20, count 2 2006.260.07:31:08.66#ibcon#read 5, iclass 20, count 2 2006.260.07:31:08.66#ibcon#about to read 6, iclass 20, count 2 2006.260.07:31:08.66#ibcon#read 6, iclass 20, count 2 2006.260.07:31:08.66#ibcon#end of sib2, iclass 20, count 2 2006.260.07:31:08.66#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:31:08.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:31:08.66#ibcon#[25=AT02-07\r\n] 2006.260.07:31:08.66#ibcon#*before write, iclass 20, count 2 2006.260.07:31:08.66#ibcon#enter sib2, iclass 20, count 2 2006.260.07:31:08.66#ibcon#flushed, iclass 20, count 2 2006.260.07:31:08.66#ibcon#about to write, iclass 20, count 2 2006.260.07:31:08.66#ibcon#wrote, iclass 20, count 2 2006.260.07:31:08.66#ibcon#about to read 3, iclass 20, count 2 2006.260.07:31:08.69#ibcon#read 3, iclass 20, count 2 2006.260.07:31:08.69#ibcon#about to read 4, iclass 20, count 2 2006.260.07:31:08.69#ibcon#read 4, iclass 20, count 2 2006.260.07:31:08.69#ibcon#about to read 5, iclass 20, count 2 2006.260.07:31:08.69#ibcon#read 5, iclass 20, count 2 2006.260.07:31:08.69#ibcon#about to read 6, iclass 20, count 2 2006.260.07:31:08.69#ibcon#read 6, iclass 20, count 2 2006.260.07:31:08.69#ibcon#end of sib2, iclass 20, count 2 2006.260.07:31:08.69#ibcon#*after write, iclass 20, count 2 2006.260.07:31:08.69#ibcon#*before return 0, iclass 20, count 2 2006.260.07:31:08.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:08.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:08.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:31:08.69#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:08.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:08.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:08.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:08.81#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:31:08.81#ibcon#first serial, iclass 20, count 0 2006.260.07:31:08.81#ibcon#enter sib2, iclass 20, count 0 2006.260.07:31:08.81#ibcon#flushed, iclass 20, count 0 2006.260.07:31:08.81#ibcon#about to write, iclass 20, count 0 2006.260.07:31:08.81#ibcon#wrote, iclass 20, count 0 2006.260.07:31:08.81#ibcon#about to read 3, iclass 20, count 0 2006.260.07:31:08.83#ibcon#read 3, iclass 20, count 0 2006.260.07:31:08.83#ibcon#about to read 4, iclass 20, count 0 2006.260.07:31:08.83#ibcon#read 4, iclass 20, count 0 2006.260.07:31:08.83#ibcon#about to read 5, iclass 20, count 0 2006.260.07:31:08.83#ibcon#read 5, iclass 20, count 0 2006.260.07:31:08.83#ibcon#about to read 6, iclass 20, count 0 2006.260.07:31:08.83#ibcon#read 6, iclass 20, count 0 2006.260.07:31:08.83#ibcon#end of sib2, iclass 20, count 0 2006.260.07:31:08.83#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:31:08.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:31:08.83#ibcon#[25=USB\r\n] 2006.260.07:31:08.83#ibcon#*before write, iclass 20, count 0 2006.260.07:31:08.83#ibcon#enter sib2, iclass 20, count 0 2006.260.07:31:08.83#ibcon#flushed, iclass 20, count 0 2006.260.07:31:08.83#ibcon#about to write, iclass 20, count 0 2006.260.07:31:08.83#ibcon#wrote, iclass 20, count 0 2006.260.07:31:08.83#ibcon#about to read 3, iclass 20, count 0 2006.260.07:31:08.86#ibcon#read 3, iclass 20, count 0 2006.260.07:31:08.86#ibcon#about to read 4, iclass 20, count 0 2006.260.07:31:08.86#ibcon#read 4, iclass 20, count 0 2006.260.07:31:08.86#ibcon#about to read 5, iclass 20, count 0 2006.260.07:31:08.86#ibcon#read 5, iclass 20, count 0 2006.260.07:31:08.86#ibcon#about to read 6, iclass 20, count 0 2006.260.07:31:08.86#ibcon#read 6, iclass 20, count 0 2006.260.07:31:08.86#ibcon#end of sib2, iclass 20, count 0 2006.260.07:31:08.86#ibcon#*after write, iclass 20, count 0 2006.260.07:31:08.86#ibcon#*before return 0, iclass 20, count 0 2006.260.07:31:08.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:08.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:08.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:31:08.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:31:08.86$vc4f8/valo=3,672.99 2006.260.07:31:08.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:31:08.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:31:08.86#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:08.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:08.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:08.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:08.86#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:31:08.86#ibcon#first serial, iclass 22, count 0 2006.260.07:31:08.86#ibcon#enter sib2, iclass 22, count 0 2006.260.07:31:08.86#ibcon#flushed, iclass 22, count 0 2006.260.07:31:08.86#ibcon#about to write, iclass 22, count 0 2006.260.07:31:08.86#ibcon#wrote, iclass 22, count 0 2006.260.07:31:08.86#ibcon#about to read 3, iclass 22, count 0 2006.260.07:31:08.88#ibcon#read 3, iclass 22, count 0 2006.260.07:31:08.88#ibcon#about to read 4, iclass 22, count 0 2006.260.07:31:08.88#ibcon#read 4, iclass 22, count 0 2006.260.07:31:08.88#ibcon#about to read 5, iclass 22, count 0 2006.260.07:31:08.88#ibcon#read 5, iclass 22, count 0 2006.260.07:31:08.88#ibcon#about to read 6, iclass 22, count 0 2006.260.07:31:08.88#ibcon#read 6, iclass 22, count 0 2006.260.07:31:08.88#ibcon#end of sib2, iclass 22, count 0 2006.260.07:31:08.88#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:31:08.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:31:08.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:31:08.88#ibcon#*before write, iclass 22, count 0 2006.260.07:31:08.88#ibcon#enter sib2, iclass 22, count 0 2006.260.07:31:08.88#ibcon#flushed, iclass 22, count 0 2006.260.07:31:08.88#ibcon#about to write, iclass 22, count 0 2006.260.07:31:08.88#ibcon#wrote, iclass 22, count 0 2006.260.07:31:08.88#ibcon#about to read 3, iclass 22, count 0 2006.260.07:31:08.92#ibcon#read 3, iclass 22, count 0 2006.260.07:31:08.92#ibcon#about to read 4, iclass 22, count 0 2006.260.07:31:08.92#ibcon#read 4, iclass 22, count 0 2006.260.07:31:08.92#ibcon#about to read 5, iclass 22, count 0 2006.260.07:31:08.92#ibcon#read 5, iclass 22, count 0 2006.260.07:31:08.92#ibcon#about to read 6, iclass 22, count 0 2006.260.07:31:08.92#ibcon#read 6, iclass 22, count 0 2006.260.07:31:08.92#ibcon#end of sib2, iclass 22, count 0 2006.260.07:31:08.92#ibcon#*after write, iclass 22, count 0 2006.260.07:31:08.92#ibcon#*before return 0, iclass 22, count 0 2006.260.07:31:08.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:08.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:08.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:31:08.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:31:08.92$vc4f8/va=3,8 2006.260.07:31:08.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:31:08.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:31:08.92#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:08.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:08.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:08.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:08.98#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:31:08.98#ibcon#first serial, iclass 24, count 2 2006.260.07:31:08.98#ibcon#enter sib2, iclass 24, count 2 2006.260.07:31:08.98#ibcon#flushed, iclass 24, count 2 2006.260.07:31:08.98#ibcon#about to write, iclass 24, count 2 2006.260.07:31:08.98#ibcon#wrote, iclass 24, count 2 2006.260.07:31:08.98#ibcon#about to read 3, iclass 24, count 2 2006.260.07:31:09.01#ibcon#read 3, iclass 24, count 2 2006.260.07:31:09.01#ibcon#about to read 4, iclass 24, count 2 2006.260.07:31:09.01#ibcon#read 4, iclass 24, count 2 2006.260.07:31:09.01#ibcon#about to read 5, iclass 24, count 2 2006.260.07:31:09.01#ibcon#read 5, iclass 24, count 2 2006.260.07:31:09.01#ibcon#about to read 6, iclass 24, count 2 2006.260.07:31:09.01#ibcon#read 6, iclass 24, count 2 2006.260.07:31:09.01#ibcon#end of sib2, iclass 24, count 2 2006.260.07:31:09.01#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:31:09.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:31:09.01#ibcon#[25=AT03-08\r\n] 2006.260.07:31:09.01#ibcon#*before write, iclass 24, count 2 2006.260.07:31:09.01#ibcon#enter sib2, iclass 24, count 2 2006.260.07:31:09.01#ibcon#flushed, iclass 24, count 2 2006.260.07:31:09.01#ibcon#about to write, iclass 24, count 2 2006.260.07:31:09.01#ibcon#wrote, iclass 24, count 2 2006.260.07:31:09.01#ibcon#about to read 3, iclass 24, count 2 2006.260.07:31:09.04#ibcon#read 3, iclass 24, count 2 2006.260.07:31:09.04#ibcon#about to read 4, iclass 24, count 2 2006.260.07:31:09.04#ibcon#read 4, iclass 24, count 2 2006.260.07:31:09.04#ibcon#about to read 5, iclass 24, count 2 2006.260.07:31:09.04#ibcon#read 5, iclass 24, count 2 2006.260.07:31:09.04#ibcon#about to read 6, iclass 24, count 2 2006.260.07:31:09.04#ibcon#read 6, iclass 24, count 2 2006.260.07:31:09.04#ibcon#end of sib2, iclass 24, count 2 2006.260.07:31:09.04#ibcon#*after write, iclass 24, count 2 2006.260.07:31:09.04#ibcon#*before return 0, iclass 24, count 2 2006.260.07:31:09.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:09.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:09.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:31:09.04#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:09.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:09.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:09.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:09.16#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:31:09.16#ibcon#first serial, iclass 24, count 0 2006.260.07:31:09.16#ibcon#enter sib2, iclass 24, count 0 2006.260.07:31:09.16#ibcon#flushed, iclass 24, count 0 2006.260.07:31:09.16#ibcon#about to write, iclass 24, count 0 2006.260.07:31:09.16#ibcon#wrote, iclass 24, count 0 2006.260.07:31:09.16#ibcon#about to read 3, iclass 24, count 0 2006.260.07:31:09.18#ibcon#read 3, iclass 24, count 0 2006.260.07:31:09.18#ibcon#about to read 4, iclass 24, count 0 2006.260.07:31:09.18#ibcon#read 4, iclass 24, count 0 2006.260.07:31:09.18#ibcon#about to read 5, iclass 24, count 0 2006.260.07:31:09.18#ibcon#read 5, iclass 24, count 0 2006.260.07:31:09.18#ibcon#about to read 6, iclass 24, count 0 2006.260.07:31:09.18#ibcon#read 6, iclass 24, count 0 2006.260.07:31:09.18#ibcon#end of sib2, iclass 24, count 0 2006.260.07:31:09.18#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:31:09.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:31:09.18#ibcon#[25=USB\r\n] 2006.260.07:31:09.18#ibcon#*before write, iclass 24, count 0 2006.260.07:31:09.18#ibcon#enter sib2, iclass 24, count 0 2006.260.07:31:09.18#ibcon#flushed, iclass 24, count 0 2006.260.07:31:09.18#ibcon#about to write, iclass 24, count 0 2006.260.07:31:09.18#ibcon#wrote, iclass 24, count 0 2006.260.07:31:09.18#ibcon#about to read 3, iclass 24, count 0 2006.260.07:31:09.21#ibcon#read 3, iclass 24, count 0 2006.260.07:31:09.21#ibcon#about to read 4, iclass 24, count 0 2006.260.07:31:09.21#ibcon#read 4, iclass 24, count 0 2006.260.07:31:09.21#ibcon#about to read 5, iclass 24, count 0 2006.260.07:31:09.21#ibcon#read 5, iclass 24, count 0 2006.260.07:31:09.21#ibcon#about to read 6, iclass 24, count 0 2006.260.07:31:09.21#ibcon#read 6, iclass 24, count 0 2006.260.07:31:09.21#ibcon#end of sib2, iclass 24, count 0 2006.260.07:31:09.21#ibcon#*after write, iclass 24, count 0 2006.260.07:31:09.21#ibcon#*before return 0, iclass 24, count 0 2006.260.07:31:09.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:09.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:09.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:31:09.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:31:09.21$vc4f8/valo=4,832.99 2006.260.07:31:09.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:31:09.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:31:09.21#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:09.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:09.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:09.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:09.21#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:31:09.21#ibcon#first serial, iclass 26, count 0 2006.260.07:31:09.21#ibcon#enter sib2, iclass 26, count 0 2006.260.07:31:09.21#ibcon#flushed, iclass 26, count 0 2006.260.07:31:09.21#ibcon#about to write, iclass 26, count 0 2006.260.07:31:09.21#ibcon#wrote, iclass 26, count 0 2006.260.07:31:09.21#ibcon#about to read 3, iclass 26, count 0 2006.260.07:31:09.23#ibcon#read 3, iclass 26, count 0 2006.260.07:31:09.23#ibcon#about to read 4, iclass 26, count 0 2006.260.07:31:09.23#ibcon#read 4, iclass 26, count 0 2006.260.07:31:09.23#ibcon#about to read 5, iclass 26, count 0 2006.260.07:31:09.23#ibcon#read 5, iclass 26, count 0 2006.260.07:31:09.23#ibcon#about to read 6, iclass 26, count 0 2006.260.07:31:09.23#ibcon#read 6, iclass 26, count 0 2006.260.07:31:09.23#ibcon#end of sib2, iclass 26, count 0 2006.260.07:31:09.23#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:31:09.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:31:09.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:31:09.23#ibcon#*before write, iclass 26, count 0 2006.260.07:31:09.23#ibcon#enter sib2, iclass 26, count 0 2006.260.07:31:09.23#ibcon#flushed, iclass 26, count 0 2006.260.07:31:09.23#ibcon#about to write, iclass 26, count 0 2006.260.07:31:09.23#ibcon#wrote, iclass 26, count 0 2006.260.07:31:09.23#ibcon#about to read 3, iclass 26, count 0 2006.260.07:31:09.27#ibcon#read 3, iclass 26, count 0 2006.260.07:31:09.27#ibcon#about to read 4, iclass 26, count 0 2006.260.07:31:09.27#ibcon#read 4, iclass 26, count 0 2006.260.07:31:09.27#ibcon#about to read 5, iclass 26, count 0 2006.260.07:31:09.27#ibcon#read 5, iclass 26, count 0 2006.260.07:31:09.27#ibcon#about to read 6, iclass 26, count 0 2006.260.07:31:09.27#ibcon#read 6, iclass 26, count 0 2006.260.07:31:09.27#ibcon#end of sib2, iclass 26, count 0 2006.260.07:31:09.27#ibcon#*after write, iclass 26, count 0 2006.260.07:31:09.27#ibcon#*before return 0, iclass 26, count 0 2006.260.07:31:09.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:09.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:09.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:31:09.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:31:09.27$vc4f8/va=4,7 2006.260.07:31:09.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:31:09.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:31:09.27#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:09.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:09.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:09.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:09.33#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:31:09.33#ibcon#first serial, iclass 28, count 2 2006.260.07:31:09.33#ibcon#enter sib2, iclass 28, count 2 2006.260.07:31:09.33#ibcon#flushed, iclass 28, count 2 2006.260.07:31:09.33#ibcon#about to write, iclass 28, count 2 2006.260.07:31:09.33#ibcon#wrote, iclass 28, count 2 2006.260.07:31:09.33#ibcon#about to read 3, iclass 28, count 2 2006.260.07:31:09.35#ibcon#read 3, iclass 28, count 2 2006.260.07:31:09.35#ibcon#about to read 4, iclass 28, count 2 2006.260.07:31:09.35#ibcon#read 4, iclass 28, count 2 2006.260.07:31:09.35#ibcon#about to read 5, iclass 28, count 2 2006.260.07:31:09.35#ibcon#read 5, iclass 28, count 2 2006.260.07:31:09.35#ibcon#about to read 6, iclass 28, count 2 2006.260.07:31:09.35#ibcon#read 6, iclass 28, count 2 2006.260.07:31:09.35#ibcon#end of sib2, iclass 28, count 2 2006.260.07:31:09.35#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:31:09.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:31:09.35#ibcon#[25=AT04-07\r\n] 2006.260.07:31:09.35#ibcon#*before write, iclass 28, count 2 2006.260.07:31:09.35#ibcon#enter sib2, iclass 28, count 2 2006.260.07:31:09.35#ibcon#flushed, iclass 28, count 2 2006.260.07:31:09.35#ibcon#about to write, iclass 28, count 2 2006.260.07:31:09.35#ibcon#wrote, iclass 28, count 2 2006.260.07:31:09.35#ibcon#about to read 3, iclass 28, count 2 2006.260.07:31:09.38#ibcon#read 3, iclass 28, count 2 2006.260.07:31:09.38#ibcon#about to read 4, iclass 28, count 2 2006.260.07:31:09.38#ibcon#read 4, iclass 28, count 2 2006.260.07:31:09.38#ibcon#about to read 5, iclass 28, count 2 2006.260.07:31:09.38#ibcon#read 5, iclass 28, count 2 2006.260.07:31:09.38#ibcon#about to read 6, iclass 28, count 2 2006.260.07:31:09.38#ibcon#read 6, iclass 28, count 2 2006.260.07:31:09.38#ibcon#end of sib2, iclass 28, count 2 2006.260.07:31:09.38#ibcon#*after write, iclass 28, count 2 2006.260.07:31:09.38#ibcon#*before return 0, iclass 28, count 2 2006.260.07:31:09.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:09.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:09.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:31:09.38#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:09.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:09.44#abcon#<5=/04 2.9 7.0 23.18 861010.3\r\n> 2006.260.07:31:09.46#abcon#{5=INTERFACE CLEAR} 2006.260.07:31:09.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:09.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:09.50#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:31:09.50#ibcon#first serial, iclass 28, count 0 2006.260.07:31:09.50#ibcon#enter sib2, iclass 28, count 0 2006.260.07:31:09.50#ibcon#flushed, iclass 28, count 0 2006.260.07:31:09.50#ibcon#about to write, iclass 28, count 0 2006.260.07:31:09.50#ibcon#wrote, iclass 28, count 0 2006.260.07:31:09.50#ibcon#about to read 3, iclass 28, count 0 2006.260.07:31:09.52#ibcon#read 3, iclass 28, count 0 2006.260.07:31:09.52#ibcon#about to read 4, iclass 28, count 0 2006.260.07:31:09.52#ibcon#read 4, iclass 28, count 0 2006.260.07:31:09.52#ibcon#about to read 5, iclass 28, count 0 2006.260.07:31:09.52#ibcon#read 5, iclass 28, count 0 2006.260.07:31:09.52#ibcon#about to read 6, iclass 28, count 0 2006.260.07:31:09.52#ibcon#read 6, iclass 28, count 0 2006.260.07:31:09.52#ibcon#end of sib2, iclass 28, count 0 2006.260.07:31:09.52#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:31:09.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:31:09.52#ibcon#[25=USB\r\n] 2006.260.07:31:09.52#ibcon#*before write, iclass 28, count 0 2006.260.07:31:09.52#ibcon#enter sib2, iclass 28, count 0 2006.260.07:31:09.52#ibcon#flushed, iclass 28, count 0 2006.260.07:31:09.52#ibcon#about to write, iclass 28, count 0 2006.260.07:31:09.52#ibcon#wrote, iclass 28, count 0 2006.260.07:31:09.52#ibcon#about to read 3, iclass 28, count 0 2006.260.07:31:09.52#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:31:09.55#ibcon#read 3, iclass 28, count 0 2006.260.07:31:09.55#ibcon#about to read 4, iclass 28, count 0 2006.260.07:31:09.55#ibcon#read 4, iclass 28, count 0 2006.260.07:31:09.55#ibcon#about to read 5, iclass 28, count 0 2006.260.07:31:09.55#ibcon#read 5, iclass 28, count 0 2006.260.07:31:09.55#ibcon#about to read 6, iclass 28, count 0 2006.260.07:31:09.55#ibcon#read 6, iclass 28, count 0 2006.260.07:31:09.55#ibcon#end of sib2, iclass 28, count 0 2006.260.07:31:09.55#ibcon#*after write, iclass 28, count 0 2006.260.07:31:09.55#ibcon#*before return 0, iclass 28, count 0 2006.260.07:31:09.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:09.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:09.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:31:09.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:31:09.55$vc4f8/valo=5,652.99 2006.260.07:31:09.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:31:09.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:31:09.55#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:09.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:09.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:09.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:09.55#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:31:09.55#ibcon#first serial, iclass 34, count 0 2006.260.07:31:09.55#ibcon#enter sib2, iclass 34, count 0 2006.260.07:31:09.55#ibcon#flushed, iclass 34, count 0 2006.260.07:31:09.55#ibcon#about to write, iclass 34, count 0 2006.260.07:31:09.55#ibcon#wrote, iclass 34, count 0 2006.260.07:31:09.55#ibcon#about to read 3, iclass 34, count 0 2006.260.07:31:09.57#ibcon#read 3, iclass 34, count 0 2006.260.07:31:09.57#ibcon#about to read 4, iclass 34, count 0 2006.260.07:31:09.57#ibcon#read 4, iclass 34, count 0 2006.260.07:31:09.57#ibcon#about to read 5, iclass 34, count 0 2006.260.07:31:09.57#ibcon#read 5, iclass 34, count 0 2006.260.07:31:09.57#ibcon#about to read 6, iclass 34, count 0 2006.260.07:31:09.57#ibcon#read 6, iclass 34, count 0 2006.260.07:31:09.57#ibcon#end of sib2, iclass 34, count 0 2006.260.07:31:09.57#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:31:09.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:31:09.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:31:09.57#ibcon#*before write, iclass 34, count 0 2006.260.07:31:09.57#ibcon#enter sib2, iclass 34, count 0 2006.260.07:31:09.57#ibcon#flushed, iclass 34, count 0 2006.260.07:31:09.57#ibcon#about to write, iclass 34, count 0 2006.260.07:31:09.57#ibcon#wrote, iclass 34, count 0 2006.260.07:31:09.57#ibcon#about to read 3, iclass 34, count 0 2006.260.07:31:09.61#ibcon#read 3, iclass 34, count 0 2006.260.07:31:09.61#ibcon#about to read 4, iclass 34, count 0 2006.260.07:31:09.61#ibcon#read 4, iclass 34, count 0 2006.260.07:31:09.61#ibcon#about to read 5, iclass 34, count 0 2006.260.07:31:09.61#ibcon#read 5, iclass 34, count 0 2006.260.07:31:09.61#ibcon#about to read 6, iclass 34, count 0 2006.260.07:31:09.61#ibcon#read 6, iclass 34, count 0 2006.260.07:31:09.61#ibcon#end of sib2, iclass 34, count 0 2006.260.07:31:09.61#ibcon#*after write, iclass 34, count 0 2006.260.07:31:09.61#ibcon#*before return 0, iclass 34, count 0 2006.260.07:31:09.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:09.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:09.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:31:09.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:31:09.61$vc4f8/va=5,7 2006.260.07:31:09.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:31:09.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:31:09.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:09.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:09.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:09.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:09.67#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:31:09.67#ibcon#first serial, iclass 36, count 2 2006.260.07:31:09.67#ibcon#enter sib2, iclass 36, count 2 2006.260.07:31:09.67#ibcon#flushed, iclass 36, count 2 2006.260.07:31:09.67#ibcon#about to write, iclass 36, count 2 2006.260.07:31:09.67#ibcon#wrote, iclass 36, count 2 2006.260.07:31:09.67#ibcon#about to read 3, iclass 36, count 2 2006.260.07:31:09.69#ibcon#read 3, iclass 36, count 2 2006.260.07:31:09.69#ibcon#about to read 4, iclass 36, count 2 2006.260.07:31:09.69#ibcon#read 4, iclass 36, count 2 2006.260.07:31:09.69#ibcon#about to read 5, iclass 36, count 2 2006.260.07:31:09.69#ibcon#read 5, iclass 36, count 2 2006.260.07:31:09.69#ibcon#about to read 6, iclass 36, count 2 2006.260.07:31:09.69#ibcon#read 6, iclass 36, count 2 2006.260.07:31:09.69#ibcon#end of sib2, iclass 36, count 2 2006.260.07:31:09.69#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:31:09.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:31:09.69#ibcon#[25=AT05-07\r\n] 2006.260.07:31:09.69#ibcon#*before write, iclass 36, count 2 2006.260.07:31:09.69#ibcon#enter sib2, iclass 36, count 2 2006.260.07:31:09.69#ibcon#flushed, iclass 36, count 2 2006.260.07:31:09.69#ibcon#about to write, iclass 36, count 2 2006.260.07:31:09.69#ibcon#wrote, iclass 36, count 2 2006.260.07:31:09.69#ibcon#about to read 3, iclass 36, count 2 2006.260.07:31:09.72#ibcon#read 3, iclass 36, count 2 2006.260.07:31:09.72#ibcon#about to read 4, iclass 36, count 2 2006.260.07:31:09.72#ibcon#read 4, iclass 36, count 2 2006.260.07:31:09.72#ibcon#about to read 5, iclass 36, count 2 2006.260.07:31:09.72#ibcon#read 5, iclass 36, count 2 2006.260.07:31:09.72#ibcon#about to read 6, iclass 36, count 2 2006.260.07:31:09.72#ibcon#read 6, iclass 36, count 2 2006.260.07:31:09.72#ibcon#end of sib2, iclass 36, count 2 2006.260.07:31:09.72#ibcon#*after write, iclass 36, count 2 2006.260.07:31:09.72#ibcon#*before return 0, iclass 36, count 2 2006.260.07:31:09.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:09.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:09.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:31:09.72#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:09.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:09.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:09.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:09.84#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:31:09.84#ibcon#first serial, iclass 36, count 0 2006.260.07:31:09.84#ibcon#enter sib2, iclass 36, count 0 2006.260.07:31:09.84#ibcon#flushed, iclass 36, count 0 2006.260.07:31:09.84#ibcon#about to write, iclass 36, count 0 2006.260.07:31:09.84#ibcon#wrote, iclass 36, count 0 2006.260.07:31:09.84#ibcon#about to read 3, iclass 36, count 0 2006.260.07:31:09.86#ibcon#read 3, iclass 36, count 0 2006.260.07:31:09.86#ibcon#about to read 4, iclass 36, count 0 2006.260.07:31:09.86#ibcon#read 4, iclass 36, count 0 2006.260.07:31:09.86#ibcon#about to read 5, iclass 36, count 0 2006.260.07:31:09.86#ibcon#read 5, iclass 36, count 0 2006.260.07:31:09.86#ibcon#about to read 6, iclass 36, count 0 2006.260.07:31:09.86#ibcon#read 6, iclass 36, count 0 2006.260.07:31:09.86#ibcon#end of sib2, iclass 36, count 0 2006.260.07:31:09.86#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:31:09.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:31:09.86#ibcon#[25=USB\r\n] 2006.260.07:31:09.86#ibcon#*before write, iclass 36, count 0 2006.260.07:31:09.86#ibcon#enter sib2, iclass 36, count 0 2006.260.07:31:09.86#ibcon#flushed, iclass 36, count 0 2006.260.07:31:09.86#ibcon#about to write, iclass 36, count 0 2006.260.07:31:09.86#ibcon#wrote, iclass 36, count 0 2006.260.07:31:09.86#ibcon#about to read 3, iclass 36, count 0 2006.260.07:31:09.89#ibcon#read 3, iclass 36, count 0 2006.260.07:31:09.89#ibcon#about to read 4, iclass 36, count 0 2006.260.07:31:09.89#ibcon#read 4, iclass 36, count 0 2006.260.07:31:09.89#ibcon#about to read 5, iclass 36, count 0 2006.260.07:31:09.89#ibcon#read 5, iclass 36, count 0 2006.260.07:31:09.89#ibcon#about to read 6, iclass 36, count 0 2006.260.07:31:09.89#ibcon#read 6, iclass 36, count 0 2006.260.07:31:09.89#ibcon#end of sib2, iclass 36, count 0 2006.260.07:31:09.89#ibcon#*after write, iclass 36, count 0 2006.260.07:31:09.89#ibcon#*before return 0, iclass 36, count 0 2006.260.07:31:09.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:09.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:09.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:31:09.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:31:09.89$vc4f8/valo=6,772.99 2006.260.07:31:09.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:31:09.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:31:09.89#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:09.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:09.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:09.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:09.89#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:31:09.89#ibcon#first serial, iclass 38, count 0 2006.260.07:31:09.89#ibcon#enter sib2, iclass 38, count 0 2006.260.07:31:09.89#ibcon#flushed, iclass 38, count 0 2006.260.07:31:09.89#ibcon#about to write, iclass 38, count 0 2006.260.07:31:09.89#ibcon#wrote, iclass 38, count 0 2006.260.07:31:09.89#ibcon#about to read 3, iclass 38, count 0 2006.260.07:31:09.91#ibcon#read 3, iclass 38, count 0 2006.260.07:31:09.91#ibcon#about to read 4, iclass 38, count 0 2006.260.07:31:09.91#ibcon#read 4, iclass 38, count 0 2006.260.07:31:09.91#ibcon#about to read 5, iclass 38, count 0 2006.260.07:31:09.91#ibcon#read 5, iclass 38, count 0 2006.260.07:31:09.91#ibcon#about to read 6, iclass 38, count 0 2006.260.07:31:09.91#ibcon#read 6, iclass 38, count 0 2006.260.07:31:09.91#ibcon#end of sib2, iclass 38, count 0 2006.260.07:31:09.91#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:31:09.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:31:09.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:31:09.91#ibcon#*before write, iclass 38, count 0 2006.260.07:31:09.91#ibcon#enter sib2, iclass 38, count 0 2006.260.07:31:09.91#ibcon#flushed, iclass 38, count 0 2006.260.07:31:09.91#ibcon#about to write, iclass 38, count 0 2006.260.07:31:09.91#ibcon#wrote, iclass 38, count 0 2006.260.07:31:09.91#ibcon#about to read 3, iclass 38, count 0 2006.260.07:31:09.95#ibcon#read 3, iclass 38, count 0 2006.260.07:31:09.95#ibcon#about to read 4, iclass 38, count 0 2006.260.07:31:09.95#ibcon#read 4, iclass 38, count 0 2006.260.07:31:09.95#ibcon#about to read 5, iclass 38, count 0 2006.260.07:31:09.95#ibcon#read 5, iclass 38, count 0 2006.260.07:31:09.95#ibcon#about to read 6, iclass 38, count 0 2006.260.07:31:09.95#ibcon#read 6, iclass 38, count 0 2006.260.07:31:09.95#ibcon#end of sib2, iclass 38, count 0 2006.260.07:31:09.95#ibcon#*after write, iclass 38, count 0 2006.260.07:31:09.95#ibcon#*before return 0, iclass 38, count 0 2006.260.07:31:09.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:09.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:09.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:31:09.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:31:09.95$vc4f8/va=6,6 2006.260.07:31:09.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:31:09.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:31:09.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:09.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:10.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:10.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:10.01#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:31:10.01#ibcon#first serial, iclass 40, count 2 2006.260.07:31:10.01#ibcon#enter sib2, iclass 40, count 2 2006.260.07:31:10.01#ibcon#flushed, iclass 40, count 2 2006.260.07:31:10.01#ibcon#about to write, iclass 40, count 2 2006.260.07:31:10.01#ibcon#wrote, iclass 40, count 2 2006.260.07:31:10.01#ibcon#about to read 3, iclass 40, count 2 2006.260.07:31:10.03#ibcon#read 3, iclass 40, count 2 2006.260.07:31:10.03#ibcon#about to read 4, iclass 40, count 2 2006.260.07:31:10.03#ibcon#read 4, iclass 40, count 2 2006.260.07:31:10.03#ibcon#about to read 5, iclass 40, count 2 2006.260.07:31:10.03#ibcon#read 5, iclass 40, count 2 2006.260.07:31:10.03#ibcon#about to read 6, iclass 40, count 2 2006.260.07:31:10.03#ibcon#read 6, iclass 40, count 2 2006.260.07:31:10.03#ibcon#end of sib2, iclass 40, count 2 2006.260.07:31:10.03#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:31:10.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:31:10.03#ibcon#[25=AT06-06\r\n] 2006.260.07:31:10.03#ibcon#*before write, iclass 40, count 2 2006.260.07:31:10.03#ibcon#enter sib2, iclass 40, count 2 2006.260.07:31:10.03#ibcon#flushed, iclass 40, count 2 2006.260.07:31:10.03#ibcon#about to write, iclass 40, count 2 2006.260.07:31:10.03#ibcon#wrote, iclass 40, count 2 2006.260.07:31:10.03#ibcon#about to read 3, iclass 40, count 2 2006.260.07:31:10.06#ibcon#read 3, iclass 40, count 2 2006.260.07:31:10.06#ibcon#about to read 4, iclass 40, count 2 2006.260.07:31:10.06#ibcon#read 4, iclass 40, count 2 2006.260.07:31:10.06#ibcon#about to read 5, iclass 40, count 2 2006.260.07:31:10.06#ibcon#read 5, iclass 40, count 2 2006.260.07:31:10.06#ibcon#about to read 6, iclass 40, count 2 2006.260.07:31:10.06#ibcon#read 6, iclass 40, count 2 2006.260.07:31:10.06#ibcon#end of sib2, iclass 40, count 2 2006.260.07:31:10.06#ibcon#*after write, iclass 40, count 2 2006.260.07:31:10.06#ibcon#*before return 0, iclass 40, count 2 2006.260.07:31:10.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:10.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:10.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:31:10.06#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:10.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:31:10.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:31:10.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:31:10.18#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:31:10.18#ibcon#first serial, iclass 40, count 0 2006.260.07:31:10.18#ibcon#enter sib2, iclass 40, count 0 2006.260.07:31:10.18#ibcon#flushed, iclass 40, count 0 2006.260.07:31:10.18#ibcon#about to write, iclass 40, count 0 2006.260.07:31:10.18#ibcon#wrote, iclass 40, count 0 2006.260.07:31:10.18#ibcon#about to read 3, iclass 40, count 0 2006.260.07:31:10.20#ibcon#read 3, iclass 40, count 0 2006.260.07:31:10.20#ibcon#about to read 4, iclass 40, count 0 2006.260.07:31:10.20#ibcon#read 4, iclass 40, count 0 2006.260.07:31:10.20#ibcon#about to read 5, iclass 40, count 0 2006.260.07:31:10.20#ibcon#read 5, iclass 40, count 0 2006.260.07:31:10.20#ibcon#about to read 6, iclass 40, count 0 2006.260.07:31:10.20#ibcon#read 6, iclass 40, count 0 2006.260.07:31:10.20#ibcon#end of sib2, iclass 40, count 0 2006.260.07:31:10.20#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:31:10.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:31:10.20#ibcon#[25=USB\r\n] 2006.260.07:31:10.20#ibcon#*before write, iclass 40, count 0 2006.260.07:31:10.20#ibcon#enter sib2, iclass 40, count 0 2006.260.07:31:10.20#ibcon#flushed, iclass 40, count 0 2006.260.07:31:10.20#ibcon#about to write, iclass 40, count 0 2006.260.07:31:10.20#ibcon#wrote, iclass 40, count 0 2006.260.07:31:10.20#ibcon#about to read 3, iclass 40, count 0 2006.260.07:31:10.23#ibcon#read 3, iclass 40, count 0 2006.260.07:31:10.23#ibcon#about to read 4, iclass 40, count 0 2006.260.07:31:10.23#ibcon#read 4, iclass 40, count 0 2006.260.07:31:10.23#ibcon#about to read 5, iclass 40, count 0 2006.260.07:31:10.23#ibcon#read 5, iclass 40, count 0 2006.260.07:31:10.23#ibcon#about to read 6, iclass 40, count 0 2006.260.07:31:10.23#ibcon#read 6, iclass 40, count 0 2006.260.07:31:10.23#ibcon#end of sib2, iclass 40, count 0 2006.260.07:31:10.23#ibcon#*after write, iclass 40, count 0 2006.260.07:31:10.23#ibcon#*before return 0, iclass 40, count 0 2006.260.07:31:10.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:31:10.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:31:10.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:31:10.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:31:10.23$vc4f8/valo=7,832.99 2006.260.07:31:10.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:31:10.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:31:10.23#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:10.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:31:10.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:31:10.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:31:10.23#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:31:10.23#ibcon#first serial, iclass 4, count 0 2006.260.07:31:10.23#ibcon#enter sib2, iclass 4, count 0 2006.260.07:31:10.23#ibcon#flushed, iclass 4, count 0 2006.260.07:31:10.23#ibcon#about to write, iclass 4, count 0 2006.260.07:31:10.23#ibcon#wrote, iclass 4, count 0 2006.260.07:31:10.23#ibcon#about to read 3, iclass 4, count 0 2006.260.07:31:10.25#ibcon#read 3, iclass 4, count 0 2006.260.07:31:10.25#ibcon#about to read 4, iclass 4, count 0 2006.260.07:31:10.25#ibcon#read 4, iclass 4, count 0 2006.260.07:31:10.25#ibcon#about to read 5, iclass 4, count 0 2006.260.07:31:10.25#ibcon#read 5, iclass 4, count 0 2006.260.07:31:10.25#ibcon#about to read 6, iclass 4, count 0 2006.260.07:31:10.25#ibcon#read 6, iclass 4, count 0 2006.260.07:31:10.25#ibcon#end of sib2, iclass 4, count 0 2006.260.07:31:10.25#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:31:10.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:31:10.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:31:10.25#ibcon#*before write, iclass 4, count 0 2006.260.07:31:10.25#ibcon#enter sib2, iclass 4, count 0 2006.260.07:31:10.25#ibcon#flushed, iclass 4, count 0 2006.260.07:31:10.25#ibcon#about to write, iclass 4, count 0 2006.260.07:31:10.25#ibcon#wrote, iclass 4, count 0 2006.260.07:31:10.25#ibcon#about to read 3, iclass 4, count 0 2006.260.07:31:10.29#ibcon#read 3, iclass 4, count 0 2006.260.07:31:10.29#ibcon#about to read 4, iclass 4, count 0 2006.260.07:31:10.29#ibcon#read 4, iclass 4, count 0 2006.260.07:31:10.29#ibcon#about to read 5, iclass 4, count 0 2006.260.07:31:10.29#ibcon#read 5, iclass 4, count 0 2006.260.07:31:10.29#ibcon#about to read 6, iclass 4, count 0 2006.260.07:31:10.29#ibcon#read 6, iclass 4, count 0 2006.260.07:31:10.29#ibcon#end of sib2, iclass 4, count 0 2006.260.07:31:10.29#ibcon#*after write, iclass 4, count 0 2006.260.07:31:10.29#ibcon#*before return 0, iclass 4, count 0 2006.260.07:31:10.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:31:10.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:31:10.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:31:10.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:31:10.29$vc4f8/va=7,6 2006.260.07:31:10.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:31:10.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:31:10.29#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:10.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:31:10.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:31:10.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:31:10.35#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:31:10.35#ibcon#first serial, iclass 6, count 2 2006.260.07:31:10.35#ibcon#enter sib2, iclass 6, count 2 2006.260.07:31:10.35#ibcon#flushed, iclass 6, count 2 2006.260.07:31:10.35#ibcon#about to write, iclass 6, count 2 2006.260.07:31:10.35#ibcon#wrote, iclass 6, count 2 2006.260.07:31:10.35#ibcon#about to read 3, iclass 6, count 2 2006.260.07:31:10.37#ibcon#read 3, iclass 6, count 2 2006.260.07:31:10.37#ibcon#about to read 4, iclass 6, count 2 2006.260.07:31:10.37#ibcon#read 4, iclass 6, count 2 2006.260.07:31:10.37#ibcon#about to read 5, iclass 6, count 2 2006.260.07:31:10.37#ibcon#read 5, iclass 6, count 2 2006.260.07:31:10.37#ibcon#about to read 6, iclass 6, count 2 2006.260.07:31:10.37#ibcon#read 6, iclass 6, count 2 2006.260.07:31:10.37#ibcon#end of sib2, iclass 6, count 2 2006.260.07:31:10.37#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:31:10.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:31:10.37#ibcon#[25=AT07-06\r\n] 2006.260.07:31:10.37#ibcon#*before write, iclass 6, count 2 2006.260.07:31:10.37#ibcon#enter sib2, iclass 6, count 2 2006.260.07:31:10.37#ibcon#flushed, iclass 6, count 2 2006.260.07:31:10.37#ibcon#about to write, iclass 6, count 2 2006.260.07:31:10.37#ibcon#wrote, iclass 6, count 2 2006.260.07:31:10.37#ibcon#about to read 3, iclass 6, count 2 2006.260.07:31:10.40#ibcon#read 3, iclass 6, count 2 2006.260.07:31:10.40#ibcon#about to read 4, iclass 6, count 2 2006.260.07:31:10.40#ibcon#read 4, iclass 6, count 2 2006.260.07:31:10.40#ibcon#about to read 5, iclass 6, count 2 2006.260.07:31:10.40#ibcon#read 5, iclass 6, count 2 2006.260.07:31:10.40#ibcon#about to read 6, iclass 6, count 2 2006.260.07:31:10.40#ibcon#read 6, iclass 6, count 2 2006.260.07:31:10.40#ibcon#end of sib2, iclass 6, count 2 2006.260.07:31:10.40#ibcon#*after write, iclass 6, count 2 2006.260.07:31:10.40#ibcon#*before return 0, iclass 6, count 2 2006.260.07:31:10.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:31:10.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:31:10.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:31:10.40#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:10.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:31:10.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:31:10.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:31:10.52#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:31:10.52#ibcon#first serial, iclass 6, count 0 2006.260.07:31:10.52#ibcon#enter sib2, iclass 6, count 0 2006.260.07:31:10.52#ibcon#flushed, iclass 6, count 0 2006.260.07:31:10.52#ibcon#about to write, iclass 6, count 0 2006.260.07:31:10.52#ibcon#wrote, iclass 6, count 0 2006.260.07:31:10.52#ibcon#about to read 3, iclass 6, count 0 2006.260.07:31:10.55#ibcon#read 3, iclass 6, count 0 2006.260.07:31:10.55#ibcon#about to read 4, iclass 6, count 0 2006.260.07:31:10.55#ibcon#read 4, iclass 6, count 0 2006.260.07:31:10.55#ibcon#about to read 5, iclass 6, count 0 2006.260.07:31:10.55#ibcon#read 5, iclass 6, count 0 2006.260.07:31:10.55#ibcon#about to read 6, iclass 6, count 0 2006.260.07:31:10.55#ibcon#read 6, iclass 6, count 0 2006.260.07:31:10.55#ibcon#end of sib2, iclass 6, count 0 2006.260.07:31:10.55#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:31:10.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:31:10.55#ibcon#[25=USB\r\n] 2006.260.07:31:10.55#ibcon#*before write, iclass 6, count 0 2006.260.07:31:10.55#ibcon#enter sib2, iclass 6, count 0 2006.260.07:31:10.55#ibcon#flushed, iclass 6, count 0 2006.260.07:31:10.55#ibcon#about to write, iclass 6, count 0 2006.260.07:31:10.55#ibcon#wrote, iclass 6, count 0 2006.260.07:31:10.55#ibcon#about to read 3, iclass 6, count 0 2006.260.07:31:10.58#ibcon#read 3, iclass 6, count 0 2006.260.07:31:10.58#ibcon#about to read 4, iclass 6, count 0 2006.260.07:31:10.58#ibcon#read 4, iclass 6, count 0 2006.260.07:31:10.58#ibcon#about to read 5, iclass 6, count 0 2006.260.07:31:10.58#ibcon#read 5, iclass 6, count 0 2006.260.07:31:10.58#ibcon#about to read 6, iclass 6, count 0 2006.260.07:31:10.58#ibcon#read 6, iclass 6, count 0 2006.260.07:31:10.58#ibcon#end of sib2, iclass 6, count 0 2006.260.07:31:10.58#ibcon#*after write, iclass 6, count 0 2006.260.07:31:10.58#ibcon#*before return 0, iclass 6, count 0 2006.260.07:31:10.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:31:10.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:31:10.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:31:10.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:31:10.58$vc4f8/valo=8,852.99 2006.260.07:31:10.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:31:10.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:31:10.58#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:10.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:31:10.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:31:10.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:31:10.58#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:31:10.58#ibcon#first serial, iclass 10, count 0 2006.260.07:31:10.58#ibcon#enter sib2, iclass 10, count 0 2006.260.07:31:10.58#ibcon#flushed, iclass 10, count 0 2006.260.07:31:10.58#ibcon#about to write, iclass 10, count 0 2006.260.07:31:10.58#ibcon#wrote, iclass 10, count 0 2006.260.07:31:10.58#ibcon#about to read 3, iclass 10, count 0 2006.260.07:31:10.60#ibcon#read 3, iclass 10, count 0 2006.260.07:31:10.60#ibcon#about to read 4, iclass 10, count 0 2006.260.07:31:10.60#ibcon#read 4, iclass 10, count 0 2006.260.07:31:10.60#ibcon#about to read 5, iclass 10, count 0 2006.260.07:31:10.60#ibcon#read 5, iclass 10, count 0 2006.260.07:31:10.60#ibcon#about to read 6, iclass 10, count 0 2006.260.07:31:10.60#ibcon#read 6, iclass 10, count 0 2006.260.07:31:10.60#ibcon#end of sib2, iclass 10, count 0 2006.260.07:31:10.60#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:31:10.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:31:10.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:31:10.60#ibcon#*before write, iclass 10, count 0 2006.260.07:31:10.60#ibcon#enter sib2, iclass 10, count 0 2006.260.07:31:10.60#ibcon#flushed, iclass 10, count 0 2006.260.07:31:10.60#ibcon#about to write, iclass 10, count 0 2006.260.07:31:10.60#ibcon#wrote, iclass 10, count 0 2006.260.07:31:10.60#ibcon#about to read 3, iclass 10, count 0 2006.260.07:31:10.64#ibcon#read 3, iclass 10, count 0 2006.260.07:31:10.64#ibcon#about to read 4, iclass 10, count 0 2006.260.07:31:10.64#ibcon#read 4, iclass 10, count 0 2006.260.07:31:10.64#ibcon#about to read 5, iclass 10, count 0 2006.260.07:31:10.64#ibcon#read 5, iclass 10, count 0 2006.260.07:31:10.64#ibcon#about to read 6, iclass 10, count 0 2006.260.07:31:10.64#ibcon#read 6, iclass 10, count 0 2006.260.07:31:10.64#ibcon#end of sib2, iclass 10, count 0 2006.260.07:31:10.64#ibcon#*after write, iclass 10, count 0 2006.260.07:31:10.64#ibcon#*before return 0, iclass 10, count 0 2006.260.07:31:10.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:31:10.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:31:10.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:31:10.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:31:10.64$vc4f8/va=8,6 2006.260.07:31:10.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:31:10.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:31:10.64#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:10.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:31:10.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:31:10.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:31:10.70#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:31:10.70#ibcon#first serial, iclass 12, count 2 2006.260.07:31:10.70#ibcon#enter sib2, iclass 12, count 2 2006.260.07:31:10.70#ibcon#flushed, iclass 12, count 2 2006.260.07:31:10.70#ibcon#about to write, iclass 12, count 2 2006.260.07:31:10.70#ibcon#wrote, iclass 12, count 2 2006.260.07:31:10.70#ibcon#about to read 3, iclass 12, count 2 2006.260.07:31:10.72#ibcon#read 3, iclass 12, count 2 2006.260.07:31:10.72#ibcon#about to read 4, iclass 12, count 2 2006.260.07:31:10.72#ibcon#read 4, iclass 12, count 2 2006.260.07:31:10.72#ibcon#about to read 5, iclass 12, count 2 2006.260.07:31:10.72#ibcon#read 5, iclass 12, count 2 2006.260.07:31:10.72#ibcon#about to read 6, iclass 12, count 2 2006.260.07:31:10.72#ibcon#read 6, iclass 12, count 2 2006.260.07:31:10.72#ibcon#end of sib2, iclass 12, count 2 2006.260.07:31:10.72#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:31:10.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:31:10.72#ibcon#[25=AT08-06\r\n] 2006.260.07:31:10.72#ibcon#*before write, iclass 12, count 2 2006.260.07:31:10.72#ibcon#enter sib2, iclass 12, count 2 2006.260.07:31:10.72#ibcon#flushed, iclass 12, count 2 2006.260.07:31:10.72#ibcon#about to write, iclass 12, count 2 2006.260.07:31:10.72#ibcon#wrote, iclass 12, count 2 2006.260.07:31:10.72#ibcon#about to read 3, iclass 12, count 2 2006.260.07:31:10.75#ibcon#read 3, iclass 12, count 2 2006.260.07:31:10.75#ibcon#about to read 4, iclass 12, count 2 2006.260.07:31:10.75#ibcon#read 4, iclass 12, count 2 2006.260.07:31:10.75#ibcon#about to read 5, iclass 12, count 2 2006.260.07:31:10.75#ibcon#read 5, iclass 12, count 2 2006.260.07:31:10.75#ibcon#about to read 6, iclass 12, count 2 2006.260.07:31:10.75#ibcon#read 6, iclass 12, count 2 2006.260.07:31:10.75#ibcon#end of sib2, iclass 12, count 2 2006.260.07:31:10.75#ibcon#*after write, iclass 12, count 2 2006.260.07:31:10.75#ibcon#*before return 0, iclass 12, count 2 2006.260.07:31:10.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:31:10.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:31:10.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:31:10.75#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:10.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:31:10.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:31:10.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:31:10.87#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:31:10.87#ibcon#first serial, iclass 12, count 0 2006.260.07:31:10.87#ibcon#enter sib2, iclass 12, count 0 2006.260.07:31:10.87#ibcon#flushed, iclass 12, count 0 2006.260.07:31:10.87#ibcon#about to write, iclass 12, count 0 2006.260.07:31:10.87#ibcon#wrote, iclass 12, count 0 2006.260.07:31:10.87#ibcon#about to read 3, iclass 12, count 0 2006.260.07:31:10.89#ibcon#read 3, iclass 12, count 0 2006.260.07:31:10.89#ibcon#about to read 4, iclass 12, count 0 2006.260.07:31:10.89#ibcon#read 4, iclass 12, count 0 2006.260.07:31:10.89#ibcon#about to read 5, iclass 12, count 0 2006.260.07:31:10.89#ibcon#read 5, iclass 12, count 0 2006.260.07:31:10.89#ibcon#about to read 6, iclass 12, count 0 2006.260.07:31:10.89#ibcon#read 6, iclass 12, count 0 2006.260.07:31:10.89#ibcon#end of sib2, iclass 12, count 0 2006.260.07:31:10.89#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:31:10.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:31:10.89#ibcon#[25=USB\r\n] 2006.260.07:31:10.89#ibcon#*before write, iclass 12, count 0 2006.260.07:31:10.89#ibcon#enter sib2, iclass 12, count 0 2006.260.07:31:10.89#ibcon#flushed, iclass 12, count 0 2006.260.07:31:10.89#ibcon#about to write, iclass 12, count 0 2006.260.07:31:10.89#ibcon#wrote, iclass 12, count 0 2006.260.07:31:10.89#ibcon#about to read 3, iclass 12, count 0 2006.260.07:31:10.92#ibcon#read 3, iclass 12, count 0 2006.260.07:31:10.92#ibcon#about to read 4, iclass 12, count 0 2006.260.07:31:10.92#ibcon#read 4, iclass 12, count 0 2006.260.07:31:10.92#ibcon#about to read 5, iclass 12, count 0 2006.260.07:31:10.92#ibcon#read 5, iclass 12, count 0 2006.260.07:31:10.92#ibcon#about to read 6, iclass 12, count 0 2006.260.07:31:10.92#ibcon#read 6, iclass 12, count 0 2006.260.07:31:10.92#ibcon#end of sib2, iclass 12, count 0 2006.260.07:31:10.92#ibcon#*after write, iclass 12, count 0 2006.260.07:31:10.92#ibcon#*before return 0, iclass 12, count 0 2006.260.07:31:10.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:31:10.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:31:10.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:31:10.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:31:10.92$vc4f8/vblo=1,632.99 2006.260.07:31:10.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:31:10.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:31:10.92#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:10.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:10.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:10.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:10.92#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:31:10.92#ibcon#first serial, iclass 14, count 0 2006.260.07:31:10.92#ibcon#enter sib2, iclass 14, count 0 2006.260.07:31:10.92#ibcon#flushed, iclass 14, count 0 2006.260.07:31:10.92#ibcon#about to write, iclass 14, count 0 2006.260.07:31:10.92#ibcon#wrote, iclass 14, count 0 2006.260.07:31:10.92#ibcon#about to read 3, iclass 14, count 0 2006.260.07:31:10.94#ibcon#read 3, iclass 14, count 0 2006.260.07:31:10.94#ibcon#about to read 4, iclass 14, count 0 2006.260.07:31:10.94#ibcon#read 4, iclass 14, count 0 2006.260.07:31:10.94#ibcon#about to read 5, iclass 14, count 0 2006.260.07:31:10.94#ibcon#read 5, iclass 14, count 0 2006.260.07:31:10.94#ibcon#about to read 6, iclass 14, count 0 2006.260.07:31:10.94#ibcon#read 6, iclass 14, count 0 2006.260.07:31:10.94#ibcon#end of sib2, iclass 14, count 0 2006.260.07:31:10.94#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:31:10.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:31:10.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:31:10.94#ibcon#*before write, iclass 14, count 0 2006.260.07:31:10.94#ibcon#enter sib2, iclass 14, count 0 2006.260.07:31:10.94#ibcon#flushed, iclass 14, count 0 2006.260.07:31:10.94#ibcon#about to write, iclass 14, count 0 2006.260.07:31:10.94#ibcon#wrote, iclass 14, count 0 2006.260.07:31:10.94#ibcon#about to read 3, iclass 14, count 0 2006.260.07:31:10.98#ibcon#read 3, iclass 14, count 0 2006.260.07:31:10.98#ibcon#about to read 4, iclass 14, count 0 2006.260.07:31:10.98#ibcon#read 4, iclass 14, count 0 2006.260.07:31:10.98#ibcon#about to read 5, iclass 14, count 0 2006.260.07:31:10.98#ibcon#read 5, iclass 14, count 0 2006.260.07:31:10.98#ibcon#about to read 6, iclass 14, count 0 2006.260.07:31:10.98#ibcon#read 6, iclass 14, count 0 2006.260.07:31:10.98#ibcon#end of sib2, iclass 14, count 0 2006.260.07:31:10.98#ibcon#*after write, iclass 14, count 0 2006.260.07:31:10.98#ibcon#*before return 0, iclass 14, count 0 2006.260.07:31:10.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:10.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:31:10.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:31:10.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:31:10.98$vc4f8/vb=1,4 2006.260.07:31:10.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:31:10.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:31:10.98#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:10.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:10.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:10.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:10.98#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:31:10.98#ibcon#first serial, iclass 16, count 2 2006.260.07:31:10.98#ibcon#enter sib2, iclass 16, count 2 2006.260.07:31:10.98#ibcon#flushed, iclass 16, count 2 2006.260.07:31:10.98#ibcon#about to write, iclass 16, count 2 2006.260.07:31:10.98#ibcon#wrote, iclass 16, count 2 2006.260.07:31:10.98#ibcon#about to read 3, iclass 16, count 2 2006.260.07:31:11.00#ibcon#read 3, iclass 16, count 2 2006.260.07:31:11.00#ibcon#about to read 4, iclass 16, count 2 2006.260.07:31:11.00#ibcon#read 4, iclass 16, count 2 2006.260.07:31:11.00#ibcon#about to read 5, iclass 16, count 2 2006.260.07:31:11.00#ibcon#read 5, iclass 16, count 2 2006.260.07:31:11.00#ibcon#about to read 6, iclass 16, count 2 2006.260.07:31:11.00#ibcon#read 6, iclass 16, count 2 2006.260.07:31:11.00#ibcon#end of sib2, iclass 16, count 2 2006.260.07:31:11.00#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:31:11.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:31:11.00#ibcon#[27=AT01-04\r\n] 2006.260.07:31:11.00#ibcon#*before write, iclass 16, count 2 2006.260.07:31:11.00#ibcon#enter sib2, iclass 16, count 2 2006.260.07:31:11.00#ibcon#flushed, iclass 16, count 2 2006.260.07:31:11.00#ibcon#about to write, iclass 16, count 2 2006.260.07:31:11.00#ibcon#wrote, iclass 16, count 2 2006.260.07:31:11.00#ibcon#about to read 3, iclass 16, count 2 2006.260.07:31:11.03#ibcon#read 3, iclass 16, count 2 2006.260.07:31:11.03#ibcon#about to read 4, iclass 16, count 2 2006.260.07:31:11.03#ibcon#read 4, iclass 16, count 2 2006.260.07:31:11.03#ibcon#about to read 5, iclass 16, count 2 2006.260.07:31:11.03#ibcon#read 5, iclass 16, count 2 2006.260.07:31:11.03#ibcon#about to read 6, iclass 16, count 2 2006.260.07:31:11.03#ibcon#read 6, iclass 16, count 2 2006.260.07:31:11.03#ibcon#end of sib2, iclass 16, count 2 2006.260.07:31:11.03#ibcon#*after write, iclass 16, count 2 2006.260.07:31:11.03#ibcon#*before return 0, iclass 16, count 2 2006.260.07:31:11.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:11.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:31:11.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:31:11.03#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:11.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:11.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:11.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:11.15#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:31:11.15#ibcon#first serial, iclass 16, count 0 2006.260.07:31:11.15#ibcon#enter sib2, iclass 16, count 0 2006.260.07:31:11.15#ibcon#flushed, iclass 16, count 0 2006.260.07:31:11.15#ibcon#about to write, iclass 16, count 0 2006.260.07:31:11.15#ibcon#wrote, iclass 16, count 0 2006.260.07:31:11.15#ibcon#about to read 3, iclass 16, count 0 2006.260.07:31:11.17#ibcon#read 3, iclass 16, count 0 2006.260.07:31:11.17#ibcon#about to read 4, iclass 16, count 0 2006.260.07:31:11.17#ibcon#read 4, iclass 16, count 0 2006.260.07:31:11.17#ibcon#about to read 5, iclass 16, count 0 2006.260.07:31:11.17#ibcon#read 5, iclass 16, count 0 2006.260.07:31:11.17#ibcon#about to read 6, iclass 16, count 0 2006.260.07:31:11.17#ibcon#read 6, iclass 16, count 0 2006.260.07:31:11.17#ibcon#end of sib2, iclass 16, count 0 2006.260.07:31:11.17#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:31:11.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:31:11.17#ibcon#[27=USB\r\n] 2006.260.07:31:11.17#ibcon#*before write, iclass 16, count 0 2006.260.07:31:11.17#ibcon#enter sib2, iclass 16, count 0 2006.260.07:31:11.17#ibcon#flushed, iclass 16, count 0 2006.260.07:31:11.17#ibcon#about to write, iclass 16, count 0 2006.260.07:31:11.17#ibcon#wrote, iclass 16, count 0 2006.260.07:31:11.17#ibcon#about to read 3, iclass 16, count 0 2006.260.07:31:11.20#ibcon#read 3, iclass 16, count 0 2006.260.07:31:11.20#ibcon#about to read 4, iclass 16, count 0 2006.260.07:31:11.20#ibcon#read 4, iclass 16, count 0 2006.260.07:31:11.20#ibcon#about to read 5, iclass 16, count 0 2006.260.07:31:11.20#ibcon#read 5, iclass 16, count 0 2006.260.07:31:11.20#ibcon#about to read 6, iclass 16, count 0 2006.260.07:31:11.20#ibcon#read 6, iclass 16, count 0 2006.260.07:31:11.20#ibcon#end of sib2, iclass 16, count 0 2006.260.07:31:11.20#ibcon#*after write, iclass 16, count 0 2006.260.07:31:11.20#ibcon#*before return 0, iclass 16, count 0 2006.260.07:31:11.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:11.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:31:11.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:31:11.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:31:11.20$vc4f8/vblo=2,640.99 2006.260.07:31:11.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:31:11.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:31:11.20#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:11.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:11.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:11.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:11.20#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:31:11.20#ibcon#first serial, iclass 18, count 0 2006.260.07:31:11.20#ibcon#enter sib2, iclass 18, count 0 2006.260.07:31:11.20#ibcon#flushed, iclass 18, count 0 2006.260.07:31:11.20#ibcon#about to write, iclass 18, count 0 2006.260.07:31:11.20#ibcon#wrote, iclass 18, count 0 2006.260.07:31:11.20#ibcon#about to read 3, iclass 18, count 0 2006.260.07:31:11.22#ibcon#read 3, iclass 18, count 0 2006.260.07:31:11.22#ibcon#about to read 4, iclass 18, count 0 2006.260.07:31:11.22#ibcon#read 4, iclass 18, count 0 2006.260.07:31:11.22#ibcon#about to read 5, iclass 18, count 0 2006.260.07:31:11.22#ibcon#read 5, iclass 18, count 0 2006.260.07:31:11.22#ibcon#about to read 6, iclass 18, count 0 2006.260.07:31:11.22#ibcon#read 6, iclass 18, count 0 2006.260.07:31:11.22#ibcon#end of sib2, iclass 18, count 0 2006.260.07:31:11.22#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:31:11.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:31:11.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:31:11.22#ibcon#*before write, iclass 18, count 0 2006.260.07:31:11.22#ibcon#enter sib2, iclass 18, count 0 2006.260.07:31:11.22#ibcon#flushed, iclass 18, count 0 2006.260.07:31:11.22#ibcon#about to write, iclass 18, count 0 2006.260.07:31:11.22#ibcon#wrote, iclass 18, count 0 2006.260.07:31:11.22#ibcon#about to read 3, iclass 18, count 0 2006.260.07:31:11.26#ibcon#read 3, iclass 18, count 0 2006.260.07:31:11.26#ibcon#about to read 4, iclass 18, count 0 2006.260.07:31:11.26#ibcon#read 4, iclass 18, count 0 2006.260.07:31:11.26#ibcon#about to read 5, iclass 18, count 0 2006.260.07:31:11.26#ibcon#read 5, iclass 18, count 0 2006.260.07:31:11.26#ibcon#about to read 6, iclass 18, count 0 2006.260.07:31:11.26#ibcon#read 6, iclass 18, count 0 2006.260.07:31:11.26#ibcon#end of sib2, iclass 18, count 0 2006.260.07:31:11.26#ibcon#*after write, iclass 18, count 0 2006.260.07:31:11.26#ibcon#*before return 0, iclass 18, count 0 2006.260.07:31:11.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:11.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:31:11.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:31:11.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:31:11.26$vc4f8/vb=2,5 2006.260.07:31:11.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:31:11.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:31:11.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:11.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:11.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:11.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:11.32#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:31:11.32#ibcon#first serial, iclass 20, count 2 2006.260.07:31:11.32#ibcon#enter sib2, iclass 20, count 2 2006.260.07:31:11.32#ibcon#flushed, iclass 20, count 2 2006.260.07:31:11.32#ibcon#about to write, iclass 20, count 2 2006.260.07:31:11.32#ibcon#wrote, iclass 20, count 2 2006.260.07:31:11.32#ibcon#about to read 3, iclass 20, count 2 2006.260.07:31:11.34#ibcon#read 3, iclass 20, count 2 2006.260.07:31:11.34#ibcon#about to read 4, iclass 20, count 2 2006.260.07:31:11.34#ibcon#read 4, iclass 20, count 2 2006.260.07:31:11.34#ibcon#about to read 5, iclass 20, count 2 2006.260.07:31:11.34#ibcon#read 5, iclass 20, count 2 2006.260.07:31:11.34#ibcon#about to read 6, iclass 20, count 2 2006.260.07:31:11.34#ibcon#read 6, iclass 20, count 2 2006.260.07:31:11.34#ibcon#end of sib2, iclass 20, count 2 2006.260.07:31:11.34#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:31:11.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:31:11.34#ibcon#[27=AT02-05\r\n] 2006.260.07:31:11.34#ibcon#*before write, iclass 20, count 2 2006.260.07:31:11.34#ibcon#enter sib2, iclass 20, count 2 2006.260.07:31:11.34#ibcon#flushed, iclass 20, count 2 2006.260.07:31:11.34#ibcon#about to write, iclass 20, count 2 2006.260.07:31:11.34#ibcon#wrote, iclass 20, count 2 2006.260.07:31:11.34#ibcon#about to read 3, iclass 20, count 2 2006.260.07:31:11.37#ibcon#read 3, iclass 20, count 2 2006.260.07:31:11.37#ibcon#about to read 4, iclass 20, count 2 2006.260.07:31:11.37#ibcon#read 4, iclass 20, count 2 2006.260.07:31:11.37#ibcon#about to read 5, iclass 20, count 2 2006.260.07:31:11.37#ibcon#read 5, iclass 20, count 2 2006.260.07:31:11.37#ibcon#about to read 6, iclass 20, count 2 2006.260.07:31:11.37#ibcon#read 6, iclass 20, count 2 2006.260.07:31:11.37#ibcon#end of sib2, iclass 20, count 2 2006.260.07:31:11.37#ibcon#*after write, iclass 20, count 2 2006.260.07:31:11.37#ibcon#*before return 0, iclass 20, count 2 2006.260.07:31:11.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:11.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:31:11.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:31:11.37#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:11.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:11.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:11.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:11.49#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:31:11.49#ibcon#first serial, iclass 20, count 0 2006.260.07:31:11.49#ibcon#enter sib2, iclass 20, count 0 2006.260.07:31:11.49#ibcon#flushed, iclass 20, count 0 2006.260.07:31:11.49#ibcon#about to write, iclass 20, count 0 2006.260.07:31:11.49#ibcon#wrote, iclass 20, count 0 2006.260.07:31:11.49#ibcon#about to read 3, iclass 20, count 0 2006.260.07:31:11.51#ibcon#read 3, iclass 20, count 0 2006.260.07:31:11.51#ibcon#about to read 4, iclass 20, count 0 2006.260.07:31:11.51#ibcon#read 4, iclass 20, count 0 2006.260.07:31:11.51#ibcon#about to read 5, iclass 20, count 0 2006.260.07:31:11.51#ibcon#read 5, iclass 20, count 0 2006.260.07:31:11.51#ibcon#about to read 6, iclass 20, count 0 2006.260.07:31:11.51#ibcon#read 6, iclass 20, count 0 2006.260.07:31:11.51#ibcon#end of sib2, iclass 20, count 0 2006.260.07:31:11.51#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:31:11.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:31:11.51#ibcon#[27=USB\r\n] 2006.260.07:31:11.51#ibcon#*before write, iclass 20, count 0 2006.260.07:31:11.51#ibcon#enter sib2, iclass 20, count 0 2006.260.07:31:11.51#ibcon#flushed, iclass 20, count 0 2006.260.07:31:11.51#ibcon#about to write, iclass 20, count 0 2006.260.07:31:11.51#ibcon#wrote, iclass 20, count 0 2006.260.07:31:11.51#ibcon#about to read 3, iclass 20, count 0 2006.260.07:31:11.54#ibcon#read 3, iclass 20, count 0 2006.260.07:31:11.54#ibcon#about to read 4, iclass 20, count 0 2006.260.07:31:11.54#ibcon#read 4, iclass 20, count 0 2006.260.07:31:11.54#ibcon#about to read 5, iclass 20, count 0 2006.260.07:31:11.54#ibcon#read 5, iclass 20, count 0 2006.260.07:31:11.54#ibcon#about to read 6, iclass 20, count 0 2006.260.07:31:11.54#ibcon#read 6, iclass 20, count 0 2006.260.07:31:11.54#ibcon#end of sib2, iclass 20, count 0 2006.260.07:31:11.54#ibcon#*after write, iclass 20, count 0 2006.260.07:31:11.54#ibcon#*before return 0, iclass 20, count 0 2006.260.07:31:11.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:11.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:31:11.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:31:11.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:31:11.54$vc4f8/vblo=3,656.99 2006.260.07:31:11.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:31:11.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:31:11.54#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:11.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:11.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:11.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:11.54#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:31:11.54#ibcon#first serial, iclass 22, count 0 2006.260.07:31:11.54#ibcon#enter sib2, iclass 22, count 0 2006.260.07:31:11.54#ibcon#flushed, iclass 22, count 0 2006.260.07:31:11.54#ibcon#about to write, iclass 22, count 0 2006.260.07:31:11.54#ibcon#wrote, iclass 22, count 0 2006.260.07:31:11.54#ibcon#about to read 3, iclass 22, count 0 2006.260.07:31:11.56#ibcon#read 3, iclass 22, count 0 2006.260.07:31:11.56#ibcon#about to read 4, iclass 22, count 0 2006.260.07:31:11.56#ibcon#read 4, iclass 22, count 0 2006.260.07:31:11.56#ibcon#about to read 5, iclass 22, count 0 2006.260.07:31:11.56#ibcon#read 5, iclass 22, count 0 2006.260.07:31:11.56#ibcon#about to read 6, iclass 22, count 0 2006.260.07:31:11.56#ibcon#read 6, iclass 22, count 0 2006.260.07:31:11.56#ibcon#end of sib2, iclass 22, count 0 2006.260.07:31:11.56#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:31:11.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:31:11.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:31:11.56#ibcon#*before write, iclass 22, count 0 2006.260.07:31:11.56#ibcon#enter sib2, iclass 22, count 0 2006.260.07:31:11.56#ibcon#flushed, iclass 22, count 0 2006.260.07:31:11.56#ibcon#about to write, iclass 22, count 0 2006.260.07:31:11.56#ibcon#wrote, iclass 22, count 0 2006.260.07:31:11.56#ibcon#about to read 3, iclass 22, count 0 2006.260.07:31:11.60#ibcon#read 3, iclass 22, count 0 2006.260.07:31:11.60#ibcon#about to read 4, iclass 22, count 0 2006.260.07:31:11.60#ibcon#read 4, iclass 22, count 0 2006.260.07:31:11.60#ibcon#about to read 5, iclass 22, count 0 2006.260.07:31:11.60#ibcon#read 5, iclass 22, count 0 2006.260.07:31:11.60#ibcon#about to read 6, iclass 22, count 0 2006.260.07:31:11.60#ibcon#read 6, iclass 22, count 0 2006.260.07:31:11.60#ibcon#end of sib2, iclass 22, count 0 2006.260.07:31:11.60#ibcon#*after write, iclass 22, count 0 2006.260.07:31:11.60#ibcon#*before return 0, iclass 22, count 0 2006.260.07:31:11.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:11.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:31:11.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:31:11.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:31:11.60$vc4f8/vb=3,4 2006.260.07:31:11.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:31:11.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:31:11.60#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:11.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:11.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:11.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:11.66#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:31:11.66#ibcon#first serial, iclass 24, count 2 2006.260.07:31:11.66#ibcon#enter sib2, iclass 24, count 2 2006.260.07:31:11.66#ibcon#flushed, iclass 24, count 2 2006.260.07:31:11.66#ibcon#about to write, iclass 24, count 2 2006.260.07:31:11.66#ibcon#wrote, iclass 24, count 2 2006.260.07:31:11.66#ibcon#about to read 3, iclass 24, count 2 2006.260.07:31:11.68#ibcon#read 3, iclass 24, count 2 2006.260.07:31:11.68#ibcon#about to read 4, iclass 24, count 2 2006.260.07:31:11.68#ibcon#read 4, iclass 24, count 2 2006.260.07:31:11.68#ibcon#about to read 5, iclass 24, count 2 2006.260.07:31:11.68#ibcon#read 5, iclass 24, count 2 2006.260.07:31:11.68#ibcon#about to read 6, iclass 24, count 2 2006.260.07:31:11.68#ibcon#read 6, iclass 24, count 2 2006.260.07:31:11.68#ibcon#end of sib2, iclass 24, count 2 2006.260.07:31:11.68#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:31:11.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:31:11.68#ibcon#[27=AT03-04\r\n] 2006.260.07:31:11.68#ibcon#*before write, iclass 24, count 2 2006.260.07:31:11.68#ibcon#enter sib2, iclass 24, count 2 2006.260.07:31:11.68#ibcon#flushed, iclass 24, count 2 2006.260.07:31:11.68#ibcon#about to write, iclass 24, count 2 2006.260.07:31:11.68#ibcon#wrote, iclass 24, count 2 2006.260.07:31:11.68#ibcon#about to read 3, iclass 24, count 2 2006.260.07:31:11.71#ibcon#read 3, iclass 24, count 2 2006.260.07:31:11.71#ibcon#about to read 4, iclass 24, count 2 2006.260.07:31:11.71#ibcon#read 4, iclass 24, count 2 2006.260.07:31:11.71#ibcon#about to read 5, iclass 24, count 2 2006.260.07:31:11.71#ibcon#read 5, iclass 24, count 2 2006.260.07:31:11.71#ibcon#about to read 6, iclass 24, count 2 2006.260.07:31:11.71#ibcon#read 6, iclass 24, count 2 2006.260.07:31:11.71#ibcon#end of sib2, iclass 24, count 2 2006.260.07:31:11.71#ibcon#*after write, iclass 24, count 2 2006.260.07:31:11.71#ibcon#*before return 0, iclass 24, count 2 2006.260.07:31:11.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:11.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:31:11.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:31:11.71#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:11.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:11.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:11.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:11.83#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:31:11.83#ibcon#first serial, iclass 24, count 0 2006.260.07:31:11.83#ibcon#enter sib2, iclass 24, count 0 2006.260.07:31:11.83#ibcon#flushed, iclass 24, count 0 2006.260.07:31:11.83#ibcon#about to write, iclass 24, count 0 2006.260.07:31:11.83#ibcon#wrote, iclass 24, count 0 2006.260.07:31:11.83#ibcon#about to read 3, iclass 24, count 0 2006.260.07:31:11.85#ibcon#read 3, iclass 24, count 0 2006.260.07:31:11.85#ibcon#about to read 4, iclass 24, count 0 2006.260.07:31:11.85#ibcon#read 4, iclass 24, count 0 2006.260.07:31:11.85#ibcon#about to read 5, iclass 24, count 0 2006.260.07:31:11.85#ibcon#read 5, iclass 24, count 0 2006.260.07:31:11.85#ibcon#about to read 6, iclass 24, count 0 2006.260.07:31:11.85#ibcon#read 6, iclass 24, count 0 2006.260.07:31:11.85#ibcon#end of sib2, iclass 24, count 0 2006.260.07:31:11.85#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:31:11.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:31:11.85#ibcon#[27=USB\r\n] 2006.260.07:31:11.85#ibcon#*before write, iclass 24, count 0 2006.260.07:31:11.85#ibcon#enter sib2, iclass 24, count 0 2006.260.07:31:11.85#ibcon#flushed, iclass 24, count 0 2006.260.07:31:11.85#ibcon#about to write, iclass 24, count 0 2006.260.07:31:11.85#ibcon#wrote, iclass 24, count 0 2006.260.07:31:11.85#ibcon#about to read 3, iclass 24, count 0 2006.260.07:31:11.88#ibcon#read 3, iclass 24, count 0 2006.260.07:31:11.88#ibcon#about to read 4, iclass 24, count 0 2006.260.07:31:11.88#ibcon#read 4, iclass 24, count 0 2006.260.07:31:11.88#ibcon#about to read 5, iclass 24, count 0 2006.260.07:31:11.88#ibcon#read 5, iclass 24, count 0 2006.260.07:31:11.88#ibcon#about to read 6, iclass 24, count 0 2006.260.07:31:11.88#ibcon#read 6, iclass 24, count 0 2006.260.07:31:11.88#ibcon#end of sib2, iclass 24, count 0 2006.260.07:31:11.88#ibcon#*after write, iclass 24, count 0 2006.260.07:31:11.88#ibcon#*before return 0, iclass 24, count 0 2006.260.07:31:11.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:11.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:31:11.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:31:11.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:31:11.88$vc4f8/vblo=4,712.99 2006.260.07:31:11.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:31:11.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:31:11.88#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:11.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:11.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:11.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:11.88#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:31:11.88#ibcon#first serial, iclass 26, count 0 2006.260.07:31:11.88#ibcon#enter sib2, iclass 26, count 0 2006.260.07:31:11.88#ibcon#flushed, iclass 26, count 0 2006.260.07:31:11.88#ibcon#about to write, iclass 26, count 0 2006.260.07:31:11.88#ibcon#wrote, iclass 26, count 0 2006.260.07:31:11.88#ibcon#about to read 3, iclass 26, count 0 2006.260.07:31:11.90#ibcon#read 3, iclass 26, count 0 2006.260.07:31:11.90#ibcon#about to read 4, iclass 26, count 0 2006.260.07:31:11.90#ibcon#read 4, iclass 26, count 0 2006.260.07:31:11.90#ibcon#about to read 5, iclass 26, count 0 2006.260.07:31:11.90#ibcon#read 5, iclass 26, count 0 2006.260.07:31:11.90#ibcon#about to read 6, iclass 26, count 0 2006.260.07:31:11.90#ibcon#read 6, iclass 26, count 0 2006.260.07:31:11.90#ibcon#end of sib2, iclass 26, count 0 2006.260.07:31:11.90#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:31:11.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:31:11.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:31:11.90#ibcon#*before write, iclass 26, count 0 2006.260.07:31:11.90#ibcon#enter sib2, iclass 26, count 0 2006.260.07:31:11.90#ibcon#flushed, iclass 26, count 0 2006.260.07:31:11.90#ibcon#about to write, iclass 26, count 0 2006.260.07:31:11.90#ibcon#wrote, iclass 26, count 0 2006.260.07:31:11.90#ibcon#about to read 3, iclass 26, count 0 2006.260.07:31:11.94#ibcon#read 3, iclass 26, count 0 2006.260.07:31:11.94#ibcon#about to read 4, iclass 26, count 0 2006.260.07:31:11.94#ibcon#read 4, iclass 26, count 0 2006.260.07:31:11.94#ibcon#about to read 5, iclass 26, count 0 2006.260.07:31:11.94#ibcon#read 5, iclass 26, count 0 2006.260.07:31:11.94#ibcon#about to read 6, iclass 26, count 0 2006.260.07:31:11.94#ibcon#read 6, iclass 26, count 0 2006.260.07:31:11.94#ibcon#end of sib2, iclass 26, count 0 2006.260.07:31:11.94#ibcon#*after write, iclass 26, count 0 2006.260.07:31:11.94#ibcon#*before return 0, iclass 26, count 0 2006.260.07:31:11.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:11.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:31:11.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:31:11.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:31:11.94$vc4f8/vb=4,5 2006.260.07:31:11.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:31:11.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:31:11.94#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:11.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:12.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:12.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:12.00#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:31:12.00#ibcon#first serial, iclass 28, count 2 2006.260.07:31:12.00#ibcon#enter sib2, iclass 28, count 2 2006.260.07:31:12.00#ibcon#flushed, iclass 28, count 2 2006.260.07:31:12.00#ibcon#about to write, iclass 28, count 2 2006.260.07:31:12.00#ibcon#wrote, iclass 28, count 2 2006.260.07:31:12.00#ibcon#about to read 3, iclass 28, count 2 2006.260.07:31:12.02#ibcon#read 3, iclass 28, count 2 2006.260.07:31:12.02#ibcon#about to read 4, iclass 28, count 2 2006.260.07:31:12.02#ibcon#read 4, iclass 28, count 2 2006.260.07:31:12.02#ibcon#about to read 5, iclass 28, count 2 2006.260.07:31:12.02#ibcon#read 5, iclass 28, count 2 2006.260.07:31:12.02#ibcon#about to read 6, iclass 28, count 2 2006.260.07:31:12.02#ibcon#read 6, iclass 28, count 2 2006.260.07:31:12.02#ibcon#end of sib2, iclass 28, count 2 2006.260.07:31:12.02#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:31:12.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:31:12.02#ibcon#[27=AT04-05\r\n] 2006.260.07:31:12.02#ibcon#*before write, iclass 28, count 2 2006.260.07:31:12.02#ibcon#enter sib2, iclass 28, count 2 2006.260.07:31:12.02#ibcon#flushed, iclass 28, count 2 2006.260.07:31:12.02#ibcon#about to write, iclass 28, count 2 2006.260.07:31:12.02#ibcon#wrote, iclass 28, count 2 2006.260.07:31:12.02#ibcon#about to read 3, iclass 28, count 2 2006.260.07:31:12.05#ibcon#read 3, iclass 28, count 2 2006.260.07:31:12.05#ibcon#about to read 4, iclass 28, count 2 2006.260.07:31:12.05#ibcon#read 4, iclass 28, count 2 2006.260.07:31:12.05#ibcon#about to read 5, iclass 28, count 2 2006.260.07:31:12.05#ibcon#read 5, iclass 28, count 2 2006.260.07:31:12.05#ibcon#about to read 6, iclass 28, count 2 2006.260.07:31:12.05#ibcon#read 6, iclass 28, count 2 2006.260.07:31:12.05#ibcon#end of sib2, iclass 28, count 2 2006.260.07:31:12.05#ibcon#*after write, iclass 28, count 2 2006.260.07:31:12.05#ibcon#*before return 0, iclass 28, count 2 2006.260.07:31:12.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:12.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:31:12.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:31:12.05#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:12.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:12.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:12.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:12.17#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:31:12.17#ibcon#first serial, iclass 28, count 0 2006.260.07:31:12.17#ibcon#enter sib2, iclass 28, count 0 2006.260.07:31:12.17#ibcon#flushed, iclass 28, count 0 2006.260.07:31:12.17#ibcon#about to write, iclass 28, count 0 2006.260.07:31:12.17#ibcon#wrote, iclass 28, count 0 2006.260.07:31:12.17#ibcon#about to read 3, iclass 28, count 0 2006.260.07:31:12.19#ibcon#read 3, iclass 28, count 0 2006.260.07:31:12.19#ibcon#about to read 4, iclass 28, count 0 2006.260.07:31:12.19#ibcon#read 4, iclass 28, count 0 2006.260.07:31:12.19#ibcon#about to read 5, iclass 28, count 0 2006.260.07:31:12.19#ibcon#read 5, iclass 28, count 0 2006.260.07:31:12.19#ibcon#about to read 6, iclass 28, count 0 2006.260.07:31:12.19#ibcon#read 6, iclass 28, count 0 2006.260.07:31:12.19#ibcon#end of sib2, iclass 28, count 0 2006.260.07:31:12.19#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:31:12.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:31:12.19#ibcon#[27=USB\r\n] 2006.260.07:31:12.19#ibcon#*before write, iclass 28, count 0 2006.260.07:31:12.19#ibcon#enter sib2, iclass 28, count 0 2006.260.07:31:12.19#ibcon#flushed, iclass 28, count 0 2006.260.07:31:12.19#ibcon#about to write, iclass 28, count 0 2006.260.07:31:12.19#ibcon#wrote, iclass 28, count 0 2006.260.07:31:12.19#ibcon#about to read 3, iclass 28, count 0 2006.260.07:31:12.22#ibcon#read 3, iclass 28, count 0 2006.260.07:31:12.22#ibcon#about to read 4, iclass 28, count 0 2006.260.07:31:12.22#ibcon#read 4, iclass 28, count 0 2006.260.07:31:12.22#ibcon#about to read 5, iclass 28, count 0 2006.260.07:31:12.22#ibcon#read 5, iclass 28, count 0 2006.260.07:31:12.22#ibcon#about to read 6, iclass 28, count 0 2006.260.07:31:12.22#ibcon#read 6, iclass 28, count 0 2006.260.07:31:12.22#ibcon#end of sib2, iclass 28, count 0 2006.260.07:31:12.22#ibcon#*after write, iclass 28, count 0 2006.260.07:31:12.22#ibcon#*before return 0, iclass 28, count 0 2006.260.07:31:12.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:12.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:31:12.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:31:12.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:31:12.22$vc4f8/vblo=5,744.99 2006.260.07:31:12.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:31:12.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:31:12.22#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:12.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:31:12.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:31:12.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:31:12.22#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:31:12.22#ibcon#first serial, iclass 30, count 0 2006.260.07:31:12.22#ibcon#enter sib2, iclass 30, count 0 2006.260.07:31:12.22#ibcon#flushed, iclass 30, count 0 2006.260.07:31:12.22#ibcon#about to write, iclass 30, count 0 2006.260.07:31:12.22#ibcon#wrote, iclass 30, count 0 2006.260.07:31:12.22#ibcon#about to read 3, iclass 30, count 0 2006.260.07:31:12.24#ibcon#read 3, iclass 30, count 0 2006.260.07:31:12.24#ibcon#about to read 4, iclass 30, count 0 2006.260.07:31:12.24#ibcon#read 4, iclass 30, count 0 2006.260.07:31:12.24#ibcon#about to read 5, iclass 30, count 0 2006.260.07:31:12.24#ibcon#read 5, iclass 30, count 0 2006.260.07:31:12.24#ibcon#about to read 6, iclass 30, count 0 2006.260.07:31:12.24#ibcon#read 6, iclass 30, count 0 2006.260.07:31:12.24#ibcon#end of sib2, iclass 30, count 0 2006.260.07:31:12.24#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:31:12.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:31:12.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:31:12.24#ibcon#*before write, iclass 30, count 0 2006.260.07:31:12.24#ibcon#enter sib2, iclass 30, count 0 2006.260.07:31:12.24#ibcon#flushed, iclass 30, count 0 2006.260.07:31:12.24#ibcon#about to write, iclass 30, count 0 2006.260.07:31:12.24#ibcon#wrote, iclass 30, count 0 2006.260.07:31:12.24#ibcon#about to read 3, iclass 30, count 0 2006.260.07:31:12.28#ibcon#read 3, iclass 30, count 0 2006.260.07:31:12.28#ibcon#about to read 4, iclass 30, count 0 2006.260.07:31:12.28#ibcon#read 4, iclass 30, count 0 2006.260.07:31:12.28#ibcon#about to read 5, iclass 30, count 0 2006.260.07:31:12.28#ibcon#read 5, iclass 30, count 0 2006.260.07:31:12.28#ibcon#about to read 6, iclass 30, count 0 2006.260.07:31:12.28#ibcon#read 6, iclass 30, count 0 2006.260.07:31:12.28#ibcon#end of sib2, iclass 30, count 0 2006.260.07:31:12.28#ibcon#*after write, iclass 30, count 0 2006.260.07:31:12.28#ibcon#*before return 0, iclass 30, count 0 2006.260.07:31:12.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:31:12.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:31:12.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:31:12.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:31:12.28$vc4f8/vb=5,4 2006.260.07:31:12.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:31:12.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:31:12.28#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:12.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:31:12.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:31:12.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:31:12.34#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:31:12.34#ibcon#first serial, iclass 32, count 2 2006.260.07:31:12.34#ibcon#enter sib2, iclass 32, count 2 2006.260.07:31:12.34#ibcon#flushed, iclass 32, count 2 2006.260.07:31:12.34#ibcon#about to write, iclass 32, count 2 2006.260.07:31:12.34#ibcon#wrote, iclass 32, count 2 2006.260.07:31:12.34#ibcon#about to read 3, iclass 32, count 2 2006.260.07:31:12.36#ibcon#read 3, iclass 32, count 2 2006.260.07:31:12.36#ibcon#about to read 4, iclass 32, count 2 2006.260.07:31:12.36#ibcon#read 4, iclass 32, count 2 2006.260.07:31:12.36#ibcon#about to read 5, iclass 32, count 2 2006.260.07:31:12.36#ibcon#read 5, iclass 32, count 2 2006.260.07:31:12.36#ibcon#about to read 6, iclass 32, count 2 2006.260.07:31:12.36#ibcon#read 6, iclass 32, count 2 2006.260.07:31:12.36#ibcon#end of sib2, iclass 32, count 2 2006.260.07:31:12.36#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:31:12.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:31:12.36#ibcon#[27=AT05-04\r\n] 2006.260.07:31:12.36#ibcon#*before write, iclass 32, count 2 2006.260.07:31:12.36#ibcon#enter sib2, iclass 32, count 2 2006.260.07:31:12.36#ibcon#flushed, iclass 32, count 2 2006.260.07:31:12.36#ibcon#about to write, iclass 32, count 2 2006.260.07:31:12.36#ibcon#wrote, iclass 32, count 2 2006.260.07:31:12.36#ibcon#about to read 3, iclass 32, count 2 2006.260.07:31:12.39#ibcon#read 3, iclass 32, count 2 2006.260.07:31:12.39#ibcon#about to read 4, iclass 32, count 2 2006.260.07:31:12.39#ibcon#read 4, iclass 32, count 2 2006.260.07:31:12.39#ibcon#about to read 5, iclass 32, count 2 2006.260.07:31:12.39#ibcon#read 5, iclass 32, count 2 2006.260.07:31:12.39#ibcon#about to read 6, iclass 32, count 2 2006.260.07:31:12.39#ibcon#read 6, iclass 32, count 2 2006.260.07:31:12.39#ibcon#end of sib2, iclass 32, count 2 2006.260.07:31:12.39#ibcon#*after write, iclass 32, count 2 2006.260.07:31:12.39#ibcon#*before return 0, iclass 32, count 2 2006.260.07:31:12.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:31:12.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:31:12.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:31:12.39#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:12.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:31:12.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:31:12.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:31:12.51#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:31:12.51#ibcon#first serial, iclass 32, count 0 2006.260.07:31:12.51#ibcon#enter sib2, iclass 32, count 0 2006.260.07:31:12.51#ibcon#flushed, iclass 32, count 0 2006.260.07:31:12.51#ibcon#about to write, iclass 32, count 0 2006.260.07:31:12.51#ibcon#wrote, iclass 32, count 0 2006.260.07:31:12.51#ibcon#about to read 3, iclass 32, count 0 2006.260.07:31:12.53#ibcon#read 3, iclass 32, count 0 2006.260.07:31:12.53#ibcon#about to read 4, iclass 32, count 0 2006.260.07:31:12.53#ibcon#read 4, iclass 32, count 0 2006.260.07:31:12.53#ibcon#about to read 5, iclass 32, count 0 2006.260.07:31:12.53#ibcon#read 5, iclass 32, count 0 2006.260.07:31:12.53#ibcon#about to read 6, iclass 32, count 0 2006.260.07:31:12.53#ibcon#read 6, iclass 32, count 0 2006.260.07:31:12.53#ibcon#end of sib2, iclass 32, count 0 2006.260.07:31:12.53#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:31:12.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:31:12.53#ibcon#[27=USB\r\n] 2006.260.07:31:12.53#ibcon#*before write, iclass 32, count 0 2006.260.07:31:12.53#ibcon#enter sib2, iclass 32, count 0 2006.260.07:31:12.53#ibcon#flushed, iclass 32, count 0 2006.260.07:31:12.53#ibcon#about to write, iclass 32, count 0 2006.260.07:31:12.53#ibcon#wrote, iclass 32, count 0 2006.260.07:31:12.53#ibcon#about to read 3, iclass 32, count 0 2006.260.07:31:12.56#ibcon#read 3, iclass 32, count 0 2006.260.07:31:12.56#ibcon#about to read 4, iclass 32, count 0 2006.260.07:31:12.56#ibcon#read 4, iclass 32, count 0 2006.260.07:31:12.56#ibcon#about to read 5, iclass 32, count 0 2006.260.07:31:12.56#ibcon#read 5, iclass 32, count 0 2006.260.07:31:12.56#ibcon#about to read 6, iclass 32, count 0 2006.260.07:31:12.56#ibcon#read 6, iclass 32, count 0 2006.260.07:31:12.56#ibcon#end of sib2, iclass 32, count 0 2006.260.07:31:12.56#ibcon#*after write, iclass 32, count 0 2006.260.07:31:12.56#ibcon#*before return 0, iclass 32, count 0 2006.260.07:31:12.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:31:12.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:31:12.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:31:12.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:31:12.56$vc4f8/vblo=6,752.99 2006.260.07:31:12.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:31:12.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:31:12.56#ibcon#ireg 17 cls_cnt 0 2006.260.07:31:12.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:12.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:12.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:12.56#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:31:12.56#ibcon#first serial, iclass 34, count 0 2006.260.07:31:12.56#ibcon#enter sib2, iclass 34, count 0 2006.260.07:31:12.56#ibcon#flushed, iclass 34, count 0 2006.260.07:31:12.56#ibcon#about to write, iclass 34, count 0 2006.260.07:31:12.56#ibcon#wrote, iclass 34, count 0 2006.260.07:31:12.56#ibcon#about to read 3, iclass 34, count 0 2006.260.07:31:12.58#ibcon#read 3, iclass 34, count 0 2006.260.07:31:12.58#ibcon#about to read 4, iclass 34, count 0 2006.260.07:31:12.58#ibcon#read 4, iclass 34, count 0 2006.260.07:31:12.58#ibcon#about to read 5, iclass 34, count 0 2006.260.07:31:12.58#ibcon#read 5, iclass 34, count 0 2006.260.07:31:12.58#ibcon#about to read 6, iclass 34, count 0 2006.260.07:31:12.58#ibcon#read 6, iclass 34, count 0 2006.260.07:31:12.58#ibcon#end of sib2, iclass 34, count 0 2006.260.07:31:12.58#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:31:12.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:31:12.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:31:12.58#ibcon#*before write, iclass 34, count 0 2006.260.07:31:12.58#ibcon#enter sib2, iclass 34, count 0 2006.260.07:31:12.58#ibcon#flushed, iclass 34, count 0 2006.260.07:31:12.58#ibcon#about to write, iclass 34, count 0 2006.260.07:31:12.58#ibcon#wrote, iclass 34, count 0 2006.260.07:31:12.58#ibcon#about to read 3, iclass 34, count 0 2006.260.07:31:12.62#ibcon#read 3, iclass 34, count 0 2006.260.07:31:12.62#ibcon#about to read 4, iclass 34, count 0 2006.260.07:31:12.62#ibcon#read 4, iclass 34, count 0 2006.260.07:31:12.62#ibcon#about to read 5, iclass 34, count 0 2006.260.07:31:12.62#ibcon#read 5, iclass 34, count 0 2006.260.07:31:12.62#ibcon#about to read 6, iclass 34, count 0 2006.260.07:31:12.62#ibcon#read 6, iclass 34, count 0 2006.260.07:31:12.62#ibcon#end of sib2, iclass 34, count 0 2006.260.07:31:12.62#ibcon#*after write, iclass 34, count 0 2006.260.07:31:12.62#ibcon#*before return 0, iclass 34, count 0 2006.260.07:31:12.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:12.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:31:12.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:31:12.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:31:12.62$vc4f8/vb=6,4 2006.260.07:31:12.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:31:12.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:31:12.62#ibcon#ireg 11 cls_cnt 2 2006.260.07:31:12.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:12.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:12.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:12.68#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:31:12.68#ibcon#first serial, iclass 36, count 2 2006.260.07:31:12.68#ibcon#enter sib2, iclass 36, count 2 2006.260.07:31:12.68#ibcon#flushed, iclass 36, count 2 2006.260.07:31:12.68#ibcon#about to write, iclass 36, count 2 2006.260.07:31:12.68#ibcon#wrote, iclass 36, count 2 2006.260.07:31:12.68#ibcon#about to read 3, iclass 36, count 2 2006.260.07:31:12.70#ibcon#read 3, iclass 36, count 2 2006.260.07:31:12.70#ibcon#about to read 4, iclass 36, count 2 2006.260.07:31:12.70#ibcon#read 4, iclass 36, count 2 2006.260.07:31:12.70#ibcon#about to read 5, iclass 36, count 2 2006.260.07:31:12.70#ibcon#read 5, iclass 36, count 2 2006.260.07:31:12.70#ibcon#about to read 6, iclass 36, count 2 2006.260.07:31:12.70#ibcon#read 6, iclass 36, count 2 2006.260.07:31:12.70#ibcon#end of sib2, iclass 36, count 2 2006.260.07:31:12.70#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:31:12.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:31:12.70#ibcon#[27=AT06-04\r\n] 2006.260.07:31:12.70#ibcon#*before write, iclass 36, count 2 2006.260.07:31:12.70#ibcon#enter sib2, iclass 36, count 2 2006.260.07:31:12.70#ibcon#flushed, iclass 36, count 2 2006.260.07:31:12.70#ibcon#about to write, iclass 36, count 2 2006.260.07:31:12.70#ibcon#wrote, iclass 36, count 2 2006.260.07:31:12.70#ibcon#about to read 3, iclass 36, count 2 2006.260.07:31:12.73#ibcon#read 3, iclass 36, count 2 2006.260.07:31:12.73#ibcon#about to read 4, iclass 36, count 2 2006.260.07:31:12.73#ibcon#read 4, iclass 36, count 2 2006.260.07:31:12.73#ibcon#about to read 5, iclass 36, count 2 2006.260.07:31:12.73#ibcon#read 5, iclass 36, count 2 2006.260.07:31:12.73#ibcon#about to read 6, iclass 36, count 2 2006.260.07:31:12.73#ibcon#read 6, iclass 36, count 2 2006.260.07:31:12.73#ibcon#end of sib2, iclass 36, count 2 2006.260.07:31:12.73#ibcon#*after write, iclass 36, count 2 2006.260.07:31:12.73#ibcon#*before return 0, iclass 36, count 2 2006.260.07:31:12.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:12.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:31:12.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:31:12.73#ibcon#ireg 7 cls_cnt 0 2006.260.07:31:12.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:12.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:12.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:12.85#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:31:12.85#ibcon#first serial, iclass 36, count 0 2006.260.07:31:12.85#ibcon#enter sib2, iclass 36, count 0 2006.260.07:31:12.85#ibcon#flushed, iclass 36, count 0 2006.260.07:31:12.85#ibcon#about to write, iclass 36, count 0 2006.260.07:31:12.85#ibcon#wrote, iclass 36, count 0 2006.260.07:31:12.85#ibcon#about to read 3, iclass 36, count 0 2006.260.07:31:12.87#ibcon#read 3, iclass 36, count 0 2006.260.07:31:12.87#ibcon#about to read 4, iclass 36, count 0 2006.260.07:31:12.87#ibcon#read 4, iclass 36, count 0 2006.260.07:31:12.87#ibcon#about to read 5, iclass 36, count 0 2006.260.07:31:12.87#ibcon#read 5, iclass 36, count 0 2006.260.07:31:12.87#ibcon#about to read 6, iclass 36, count 0 2006.260.07:31:12.87#ibcon#read 6, iclass 36, count 0 2006.260.07:31:12.87#ibcon#end of sib2, iclass 36, count 0 2006.260.07:31:12.87#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:31:12.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:31:12.87#ibcon#[27=USB\r\n] 2006.260.07:31:12.87#ibcon#*before write, iclass 36, count 0 2006.260.07:31:12.87#ibcon#enter sib2, iclass 36, count 0 2006.260.07:31:12.87#ibcon#flushed, iclass 36, count 0 2006.260.07:31:12.87#ibcon#about to write, iclass 36, count 0 2006.260.07:31:12.87#ibcon#wrote, iclass 36, count 0 2006.260.07:31:12.87#ibcon#about to read 3, iclass 36, count 0 2006.260.07:31:12.90#ibcon#read 3, iclass 36, count 0 2006.260.07:31:12.90#ibcon#about to read 4, iclass 36, count 0 2006.260.07:31:12.90#ibcon#read 4, iclass 36, count 0 2006.260.07:31:12.90#ibcon#about to read 5, iclass 36, count 0 2006.260.07:31:12.90#ibcon#read 5, iclass 36, count 0 2006.260.07:31:12.90#ibcon#about to read 6, iclass 36, count 0 2006.260.07:31:12.90#ibcon#read 6, iclass 36, count 0 2006.260.07:31:12.90#ibcon#end of sib2, iclass 36, count 0 2006.260.07:31:12.90#ibcon#*after write, iclass 36, count 0 2006.260.07:31:12.90#ibcon#*before return 0, iclass 36, count 0 2006.260.07:31:12.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:12.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:31:12.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:31:12.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:31:12.90$vc4f8/vabw=wide 2006.260.07:31:12.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:31:12.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:31:12.90#ibcon#ireg 8 cls_cnt 0 2006.260.07:31:12.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:12.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:12.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:12.90#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:31:12.90#ibcon#first serial, iclass 38, count 0 2006.260.07:31:12.90#ibcon#enter sib2, iclass 38, count 0 2006.260.07:31:12.90#ibcon#flushed, iclass 38, count 0 2006.260.07:31:12.90#ibcon#about to write, iclass 38, count 0 2006.260.07:31:12.90#ibcon#wrote, iclass 38, count 0 2006.260.07:31:12.90#ibcon#about to read 3, iclass 38, count 0 2006.260.07:31:12.93#ibcon#read 3, iclass 38, count 0 2006.260.07:31:12.93#ibcon#about to read 4, iclass 38, count 0 2006.260.07:31:12.93#ibcon#read 4, iclass 38, count 0 2006.260.07:31:12.93#ibcon#about to read 5, iclass 38, count 0 2006.260.07:31:12.93#ibcon#read 5, iclass 38, count 0 2006.260.07:31:12.93#ibcon#about to read 6, iclass 38, count 0 2006.260.07:31:12.93#ibcon#read 6, iclass 38, count 0 2006.260.07:31:12.93#ibcon#end of sib2, iclass 38, count 0 2006.260.07:31:12.93#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:31:12.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:31:12.93#ibcon#[25=BW32\r\n] 2006.260.07:31:12.93#ibcon#*before write, iclass 38, count 0 2006.260.07:31:12.93#ibcon#enter sib2, iclass 38, count 0 2006.260.07:31:12.93#ibcon#flushed, iclass 38, count 0 2006.260.07:31:12.93#ibcon#about to write, iclass 38, count 0 2006.260.07:31:12.93#ibcon#wrote, iclass 38, count 0 2006.260.07:31:12.93#ibcon#about to read 3, iclass 38, count 0 2006.260.07:31:12.96#ibcon#read 3, iclass 38, count 0 2006.260.07:31:12.96#ibcon#about to read 4, iclass 38, count 0 2006.260.07:31:12.96#ibcon#read 4, iclass 38, count 0 2006.260.07:31:12.96#ibcon#about to read 5, iclass 38, count 0 2006.260.07:31:12.96#ibcon#read 5, iclass 38, count 0 2006.260.07:31:12.96#ibcon#about to read 6, iclass 38, count 0 2006.260.07:31:12.96#ibcon#read 6, iclass 38, count 0 2006.260.07:31:12.96#ibcon#end of sib2, iclass 38, count 0 2006.260.07:31:12.96#ibcon#*after write, iclass 38, count 0 2006.260.07:31:12.96#ibcon#*before return 0, iclass 38, count 0 2006.260.07:31:12.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:12.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:31:12.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:31:12.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:31:12.96$vc4f8/vbbw=wide 2006.260.07:31:12.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.07:31:12.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.07:31:12.96#ibcon#ireg 8 cls_cnt 0 2006.260.07:31:12.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:31:13.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:31:13.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:31:13.02#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:31:13.02#ibcon#first serial, iclass 40, count 0 2006.260.07:31:13.02#ibcon#enter sib2, iclass 40, count 0 2006.260.07:31:13.02#ibcon#flushed, iclass 40, count 0 2006.260.07:31:13.02#ibcon#about to write, iclass 40, count 0 2006.260.07:31:13.02#ibcon#wrote, iclass 40, count 0 2006.260.07:31:13.02#ibcon#about to read 3, iclass 40, count 0 2006.260.07:31:13.04#ibcon#read 3, iclass 40, count 0 2006.260.07:31:13.04#ibcon#about to read 4, iclass 40, count 0 2006.260.07:31:13.04#ibcon#read 4, iclass 40, count 0 2006.260.07:31:13.04#ibcon#about to read 5, iclass 40, count 0 2006.260.07:31:13.04#ibcon#read 5, iclass 40, count 0 2006.260.07:31:13.04#ibcon#about to read 6, iclass 40, count 0 2006.260.07:31:13.04#ibcon#read 6, iclass 40, count 0 2006.260.07:31:13.04#ibcon#end of sib2, iclass 40, count 0 2006.260.07:31:13.04#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:31:13.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:31:13.04#ibcon#[27=BW32\r\n] 2006.260.07:31:13.04#ibcon#*before write, iclass 40, count 0 2006.260.07:31:13.04#ibcon#enter sib2, iclass 40, count 0 2006.260.07:31:13.04#ibcon#flushed, iclass 40, count 0 2006.260.07:31:13.04#ibcon#about to write, iclass 40, count 0 2006.260.07:31:13.04#ibcon#wrote, iclass 40, count 0 2006.260.07:31:13.04#ibcon#about to read 3, iclass 40, count 0 2006.260.07:31:13.07#ibcon#read 3, iclass 40, count 0 2006.260.07:31:13.07#ibcon#about to read 4, iclass 40, count 0 2006.260.07:31:13.07#ibcon#read 4, iclass 40, count 0 2006.260.07:31:13.07#ibcon#about to read 5, iclass 40, count 0 2006.260.07:31:13.07#ibcon#read 5, iclass 40, count 0 2006.260.07:31:13.07#ibcon#about to read 6, iclass 40, count 0 2006.260.07:31:13.07#ibcon#read 6, iclass 40, count 0 2006.260.07:31:13.07#ibcon#end of sib2, iclass 40, count 0 2006.260.07:31:13.07#ibcon#*after write, iclass 40, count 0 2006.260.07:31:13.07#ibcon#*before return 0, iclass 40, count 0 2006.260.07:31:13.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:31:13.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:31:13.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:31:13.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:31:13.07$4f8m12a/ifd4f 2006.260.07:31:13.07$ifd4f/lo= 2006.260.07:31:13.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:31:13.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:31:13.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:31:13.07$ifd4f/patch= 2006.260.07:31:13.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:31:13.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:31:13.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:31:13.07$4f8m12a/"form=m,16.000,1:2 2006.260.07:31:13.07$4f8m12a/"tpicd 2006.260.07:31:13.07$4f8m12a/echo=off 2006.260.07:31:13.07$4f8m12a/xlog=off 2006.260.07:31:13.07:!2006.260.07:33:20 2006.260.07:31:31.14#trakl#Source acquired 2006.260.07:31:33.14#flagr#flagr/antenna,acquired 2006.260.07:33:20.00:preob 2006.260.07:33:20.14/onsource/TRACKING 2006.260.07:33:20.14:!2006.260.07:33:30 2006.260.07:33:30.00:data_valid=on 2006.260.07:33:30.00:midob 2006.260.07:33:30.14/onsource/TRACKING 2006.260.07:33:30.14/wx/23.16,1010.3,86 2006.260.07:33:30.27/cable/+6.4550E-03 2006.260.07:33:31.36/va/01,08,usb,yes,34,36 2006.260.07:33:31.36/va/02,07,usb,yes,34,36 2006.260.07:33:31.36/va/03,08,usb,yes,26,26 2006.260.07:33:31.36/va/04,07,usb,yes,36,39 2006.260.07:33:31.36/va/05,07,usb,yes,40,42 2006.260.07:33:31.36/va/06,06,usb,yes,39,39 2006.260.07:33:31.36/va/07,06,usb,yes,40,39 2006.260.07:33:31.36/va/08,06,usb,yes,42,41 2006.260.07:33:31.59/valo/01,532.99,yes,locked 2006.260.07:33:31.59/valo/02,572.99,yes,locked 2006.260.07:33:31.59/valo/03,672.99,yes,locked 2006.260.07:33:31.59/valo/04,832.99,yes,locked 2006.260.07:33:31.59/valo/05,652.99,yes,locked 2006.260.07:33:31.59/valo/06,772.99,yes,locked 2006.260.07:33:31.59/valo/07,832.99,yes,locked 2006.260.07:33:31.59/valo/08,852.99,yes,locked 2006.260.07:33:32.68/vb/01,04,usb,yes,32,31 2006.260.07:33:32.68/vb/02,05,usb,yes,30,31 2006.260.07:33:32.68/vb/03,04,usb,yes,30,34 2006.260.07:33:32.68/vb/04,05,usb,yes,28,28 2006.260.07:33:32.68/vb/05,04,usb,yes,30,35 2006.260.07:33:32.68/vb/06,04,usb,yes,31,34 2006.260.07:33:32.68/vb/07,04,usb,yes,33,34 2006.260.07:33:32.68/vb/08,04,usb,yes,30,34 2006.260.07:33:32.91/vblo/01,632.99,yes,locked 2006.260.07:33:32.91/vblo/02,640.99,yes,locked 2006.260.07:33:32.91/vblo/03,656.99,yes,locked 2006.260.07:33:32.91/vblo/04,712.99,yes,locked 2006.260.07:33:32.91/vblo/05,744.99,yes,locked 2006.260.07:33:32.91/vblo/06,752.99,yes,locked 2006.260.07:33:32.91/vblo/07,734.99,yes,locked 2006.260.07:33:32.91/vblo/08,744.99,yes,locked 2006.260.07:33:33.06/vabw/8 2006.260.07:33:33.21/vbbw/8 2006.260.07:33:33.42/xfe/off,on,15.0 2006.260.07:33:33.80/ifatt/23,28,28,28 2006.260.07:33:34.08/fmout-gps/S +4.50E-07 2006.260.07:33:34.12:!2006.260.07:34:30 2006.260.07:34:30.01:data_valid=off 2006.260.07:34:30.01:postob 2006.260.07:34:30.11/cable/+6.4547E-03 2006.260.07:34:30.11/wx/23.15,1010.3,86 2006.260.07:34:31.07/fmout-gps/S +4.50E-07 2006.260.07:34:31.07:scan_name=260-0735,k06260,60 2006.260.07:34:31.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.260.07:34:31.14#flagr#flagr/antenna,new-source 2006.260.07:34:32.14:checkk5 2006.260.07:34:32.55/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:34:32.95/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:34:33.35/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:34:33.75/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:34:34.15/chk_obsdata//k5ts1/T2600733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:34:34.67/chk_obsdata//k5ts2/T2600733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:34:35.05/chk_obsdata//k5ts3/T2600733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:34:35.70/chk_obsdata//k5ts4/T2600733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:34:36.51/k5log//k5ts1_log_newline 2006.260.07:34:37.35/k5log//k5ts2_log_newline 2006.260.07:34:38.09/k5log//k5ts3_log_newline 2006.260.07:34:39.15/k5log//k5ts4_log_newline 2006.260.07:34:39.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:34:39.17:4f8m12a=1 2006.260.07:34:39.17$4f8m12a/echo=on 2006.260.07:34:39.17$4f8m12a/pcalon 2006.260.07:34:39.17$pcalon/"no phase cal control is implemented here 2006.260.07:34:39.17$4f8m12a/"tpicd=stop 2006.260.07:34:39.17$4f8m12a/vc4f8 2006.260.07:34:39.17$vc4f8/valo=1,532.99 2006.260.07:34:39.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:34:39.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:34:39.17#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:39.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:39.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:39.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:39.17#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:34:39.17#ibcon#first serial, iclass 15, count 0 2006.260.07:34:39.17#ibcon#enter sib2, iclass 15, count 0 2006.260.07:34:39.17#ibcon#flushed, iclass 15, count 0 2006.260.07:34:39.17#ibcon#about to write, iclass 15, count 0 2006.260.07:34:39.17#ibcon#wrote, iclass 15, count 0 2006.260.07:34:39.17#ibcon#about to read 3, iclass 15, count 0 2006.260.07:34:39.21#ibcon#read 3, iclass 15, count 0 2006.260.07:34:39.21#ibcon#about to read 4, iclass 15, count 0 2006.260.07:34:39.21#ibcon#read 4, iclass 15, count 0 2006.260.07:34:39.21#ibcon#about to read 5, iclass 15, count 0 2006.260.07:34:39.21#ibcon#read 5, iclass 15, count 0 2006.260.07:34:39.21#ibcon#about to read 6, iclass 15, count 0 2006.260.07:34:39.21#ibcon#read 6, iclass 15, count 0 2006.260.07:34:39.21#ibcon#end of sib2, iclass 15, count 0 2006.260.07:34:39.21#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:34:39.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:34:39.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:34:39.21#ibcon#*before write, iclass 15, count 0 2006.260.07:34:39.21#ibcon#enter sib2, iclass 15, count 0 2006.260.07:34:39.21#ibcon#flushed, iclass 15, count 0 2006.260.07:34:39.21#ibcon#about to write, iclass 15, count 0 2006.260.07:34:39.21#ibcon#wrote, iclass 15, count 0 2006.260.07:34:39.21#ibcon#about to read 3, iclass 15, count 0 2006.260.07:34:39.26#ibcon#read 3, iclass 15, count 0 2006.260.07:34:39.26#ibcon#about to read 4, iclass 15, count 0 2006.260.07:34:39.26#ibcon#read 4, iclass 15, count 0 2006.260.07:34:39.26#ibcon#about to read 5, iclass 15, count 0 2006.260.07:34:39.26#ibcon#read 5, iclass 15, count 0 2006.260.07:34:39.26#ibcon#about to read 6, iclass 15, count 0 2006.260.07:34:39.26#ibcon#read 6, iclass 15, count 0 2006.260.07:34:39.26#ibcon#end of sib2, iclass 15, count 0 2006.260.07:34:39.26#ibcon#*after write, iclass 15, count 0 2006.260.07:34:39.26#ibcon#*before return 0, iclass 15, count 0 2006.260.07:34:39.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:39.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:39.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:34:39.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:34:39.26$vc4f8/va=1,8 2006.260.07:34:39.26#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:34:39.26#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:34:39.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:39.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:39.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:39.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:39.26#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:34:39.26#ibcon#first serial, iclass 17, count 2 2006.260.07:34:39.26#ibcon#enter sib2, iclass 17, count 2 2006.260.07:34:39.26#ibcon#flushed, iclass 17, count 2 2006.260.07:34:39.26#ibcon#about to write, iclass 17, count 2 2006.260.07:34:39.26#ibcon#wrote, iclass 17, count 2 2006.260.07:34:39.26#ibcon#about to read 3, iclass 17, count 2 2006.260.07:34:39.29#ibcon#read 3, iclass 17, count 2 2006.260.07:34:39.29#ibcon#about to read 4, iclass 17, count 2 2006.260.07:34:39.29#ibcon#read 4, iclass 17, count 2 2006.260.07:34:39.29#ibcon#about to read 5, iclass 17, count 2 2006.260.07:34:39.29#ibcon#read 5, iclass 17, count 2 2006.260.07:34:39.29#ibcon#about to read 6, iclass 17, count 2 2006.260.07:34:39.29#ibcon#read 6, iclass 17, count 2 2006.260.07:34:39.29#ibcon#end of sib2, iclass 17, count 2 2006.260.07:34:39.29#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:34:39.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:34:39.29#ibcon#[25=AT01-08\r\n] 2006.260.07:34:39.29#ibcon#*before write, iclass 17, count 2 2006.260.07:34:39.29#ibcon#enter sib2, iclass 17, count 2 2006.260.07:34:39.29#ibcon#flushed, iclass 17, count 2 2006.260.07:34:39.29#ibcon#about to write, iclass 17, count 2 2006.260.07:34:39.29#ibcon#wrote, iclass 17, count 2 2006.260.07:34:39.29#ibcon#about to read 3, iclass 17, count 2 2006.260.07:34:39.32#ibcon#read 3, iclass 17, count 2 2006.260.07:34:39.32#ibcon#about to read 4, iclass 17, count 2 2006.260.07:34:39.32#ibcon#read 4, iclass 17, count 2 2006.260.07:34:39.32#ibcon#about to read 5, iclass 17, count 2 2006.260.07:34:39.32#ibcon#read 5, iclass 17, count 2 2006.260.07:34:39.32#ibcon#about to read 6, iclass 17, count 2 2006.260.07:34:39.32#ibcon#read 6, iclass 17, count 2 2006.260.07:34:39.32#ibcon#end of sib2, iclass 17, count 2 2006.260.07:34:39.32#ibcon#*after write, iclass 17, count 2 2006.260.07:34:39.32#ibcon#*before return 0, iclass 17, count 2 2006.260.07:34:39.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:39.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:39.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:34:39.32#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:39.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:39.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:39.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:39.44#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:34:39.44#ibcon#first serial, iclass 17, count 0 2006.260.07:34:39.44#ibcon#enter sib2, iclass 17, count 0 2006.260.07:34:39.44#ibcon#flushed, iclass 17, count 0 2006.260.07:34:39.44#ibcon#about to write, iclass 17, count 0 2006.260.07:34:39.44#ibcon#wrote, iclass 17, count 0 2006.260.07:34:39.44#ibcon#about to read 3, iclass 17, count 0 2006.260.07:34:39.46#ibcon#read 3, iclass 17, count 0 2006.260.07:34:39.46#ibcon#about to read 4, iclass 17, count 0 2006.260.07:34:39.46#ibcon#read 4, iclass 17, count 0 2006.260.07:34:39.46#ibcon#about to read 5, iclass 17, count 0 2006.260.07:34:39.46#ibcon#read 5, iclass 17, count 0 2006.260.07:34:39.46#ibcon#about to read 6, iclass 17, count 0 2006.260.07:34:39.46#ibcon#read 6, iclass 17, count 0 2006.260.07:34:39.46#ibcon#end of sib2, iclass 17, count 0 2006.260.07:34:39.46#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:34:39.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:34:39.46#ibcon#[25=USB\r\n] 2006.260.07:34:39.46#ibcon#*before write, iclass 17, count 0 2006.260.07:34:39.46#ibcon#enter sib2, iclass 17, count 0 2006.260.07:34:39.46#ibcon#flushed, iclass 17, count 0 2006.260.07:34:39.46#ibcon#about to write, iclass 17, count 0 2006.260.07:34:39.46#ibcon#wrote, iclass 17, count 0 2006.260.07:34:39.46#ibcon#about to read 3, iclass 17, count 0 2006.260.07:34:39.49#ibcon#read 3, iclass 17, count 0 2006.260.07:34:39.49#ibcon#about to read 4, iclass 17, count 0 2006.260.07:34:39.49#ibcon#read 4, iclass 17, count 0 2006.260.07:34:39.49#ibcon#about to read 5, iclass 17, count 0 2006.260.07:34:39.49#ibcon#read 5, iclass 17, count 0 2006.260.07:34:39.49#ibcon#about to read 6, iclass 17, count 0 2006.260.07:34:39.49#ibcon#read 6, iclass 17, count 0 2006.260.07:34:39.49#ibcon#end of sib2, iclass 17, count 0 2006.260.07:34:39.49#ibcon#*after write, iclass 17, count 0 2006.260.07:34:39.49#ibcon#*before return 0, iclass 17, count 0 2006.260.07:34:39.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:39.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:39.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:34:39.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:34:39.49$vc4f8/valo=2,572.99 2006.260.07:34:39.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:34:39.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:34:39.49#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:39.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:39.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:39.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:39.49#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:34:39.49#ibcon#first serial, iclass 19, count 0 2006.260.07:34:39.49#ibcon#enter sib2, iclass 19, count 0 2006.260.07:34:39.49#ibcon#flushed, iclass 19, count 0 2006.260.07:34:39.49#ibcon#about to write, iclass 19, count 0 2006.260.07:34:39.49#ibcon#wrote, iclass 19, count 0 2006.260.07:34:39.49#ibcon#about to read 3, iclass 19, count 0 2006.260.07:34:39.51#ibcon#read 3, iclass 19, count 0 2006.260.07:34:39.51#ibcon#about to read 4, iclass 19, count 0 2006.260.07:34:39.51#ibcon#read 4, iclass 19, count 0 2006.260.07:34:39.51#ibcon#about to read 5, iclass 19, count 0 2006.260.07:34:39.51#ibcon#read 5, iclass 19, count 0 2006.260.07:34:39.51#ibcon#about to read 6, iclass 19, count 0 2006.260.07:34:39.51#ibcon#read 6, iclass 19, count 0 2006.260.07:34:39.51#ibcon#end of sib2, iclass 19, count 0 2006.260.07:34:39.51#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:34:39.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:34:39.51#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:34:39.51#ibcon#*before write, iclass 19, count 0 2006.260.07:34:39.51#ibcon#enter sib2, iclass 19, count 0 2006.260.07:34:39.51#ibcon#flushed, iclass 19, count 0 2006.260.07:34:39.51#ibcon#about to write, iclass 19, count 0 2006.260.07:34:39.51#ibcon#wrote, iclass 19, count 0 2006.260.07:34:39.51#ibcon#about to read 3, iclass 19, count 0 2006.260.07:34:39.55#ibcon#read 3, iclass 19, count 0 2006.260.07:34:39.55#ibcon#about to read 4, iclass 19, count 0 2006.260.07:34:39.55#ibcon#read 4, iclass 19, count 0 2006.260.07:34:39.55#ibcon#about to read 5, iclass 19, count 0 2006.260.07:34:39.55#ibcon#read 5, iclass 19, count 0 2006.260.07:34:39.55#ibcon#about to read 6, iclass 19, count 0 2006.260.07:34:39.55#ibcon#read 6, iclass 19, count 0 2006.260.07:34:39.55#ibcon#end of sib2, iclass 19, count 0 2006.260.07:34:39.55#ibcon#*after write, iclass 19, count 0 2006.260.07:34:39.55#ibcon#*before return 0, iclass 19, count 0 2006.260.07:34:39.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:39.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:39.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:34:39.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:34:39.55$vc4f8/va=2,7 2006.260.07:34:39.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:34:39.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:34:39.55#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:39.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:39.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:39.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:39.61#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:34:39.61#ibcon#first serial, iclass 21, count 2 2006.260.07:34:39.61#ibcon#enter sib2, iclass 21, count 2 2006.260.07:34:39.61#ibcon#flushed, iclass 21, count 2 2006.260.07:34:39.61#ibcon#about to write, iclass 21, count 2 2006.260.07:34:39.61#ibcon#wrote, iclass 21, count 2 2006.260.07:34:39.61#ibcon#about to read 3, iclass 21, count 2 2006.260.07:34:39.64#ibcon#read 3, iclass 21, count 2 2006.260.07:34:39.64#ibcon#about to read 4, iclass 21, count 2 2006.260.07:34:39.64#ibcon#read 4, iclass 21, count 2 2006.260.07:34:39.64#ibcon#about to read 5, iclass 21, count 2 2006.260.07:34:39.64#ibcon#read 5, iclass 21, count 2 2006.260.07:34:39.64#ibcon#about to read 6, iclass 21, count 2 2006.260.07:34:39.64#ibcon#read 6, iclass 21, count 2 2006.260.07:34:39.64#ibcon#end of sib2, iclass 21, count 2 2006.260.07:34:39.64#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:34:39.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:34:39.64#ibcon#[25=AT02-07\r\n] 2006.260.07:34:39.64#ibcon#*before write, iclass 21, count 2 2006.260.07:34:39.64#ibcon#enter sib2, iclass 21, count 2 2006.260.07:34:39.64#ibcon#flushed, iclass 21, count 2 2006.260.07:34:39.64#ibcon#about to write, iclass 21, count 2 2006.260.07:34:39.64#ibcon#wrote, iclass 21, count 2 2006.260.07:34:39.64#ibcon#about to read 3, iclass 21, count 2 2006.260.07:34:39.67#ibcon#read 3, iclass 21, count 2 2006.260.07:34:39.67#ibcon#about to read 4, iclass 21, count 2 2006.260.07:34:39.67#ibcon#read 4, iclass 21, count 2 2006.260.07:34:39.67#ibcon#about to read 5, iclass 21, count 2 2006.260.07:34:39.67#ibcon#read 5, iclass 21, count 2 2006.260.07:34:39.67#ibcon#about to read 6, iclass 21, count 2 2006.260.07:34:39.67#ibcon#read 6, iclass 21, count 2 2006.260.07:34:39.67#ibcon#end of sib2, iclass 21, count 2 2006.260.07:34:39.67#ibcon#*after write, iclass 21, count 2 2006.260.07:34:39.67#ibcon#*before return 0, iclass 21, count 2 2006.260.07:34:39.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:39.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:39.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:34:39.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:39.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:39.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:39.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:39.79#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:34:39.79#ibcon#first serial, iclass 21, count 0 2006.260.07:34:39.79#ibcon#enter sib2, iclass 21, count 0 2006.260.07:34:39.79#ibcon#flushed, iclass 21, count 0 2006.260.07:34:39.79#ibcon#about to write, iclass 21, count 0 2006.260.07:34:39.79#ibcon#wrote, iclass 21, count 0 2006.260.07:34:39.79#ibcon#about to read 3, iclass 21, count 0 2006.260.07:34:39.81#ibcon#read 3, iclass 21, count 0 2006.260.07:34:39.81#ibcon#about to read 4, iclass 21, count 0 2006.260.07:34:39.81#ibcon#read 4, iclass 21, count 0 2006.260.07:34:39.81#ibcon#about to read 5, iclass 21, count 0 2006.260.07:34:39.81#ibcon#read 5, iclass 21, count 0 2006.260.07:34:39.81#ibcon#about to read 6, iclass 21, count 0 2006.260.07:34:39.81#ibcon#read 6, iclass 21, count 0 2006.260.07:34:39.81#ibcon#end of sib2, iclass 21, count 0 2006.260.07:34:39.81#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:34:39.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:34:39.81#ibcon#[25=USB\r\n] 2006.260.07:34:39.81#ibcon#*before write, iclass 21, count 0 2006.260.07:34:39.81#ibcon#enter sib2, iclass 21, count 0 2006.260.07:34:39.81#ibcon#flushed, iclass 21, count 0 2006.260.07:34:39.81#ibcon#about to write, iclass 21, count 0 2006.260.07:34:39.81#ibcon#wrote, iclass 21, count 0 2006.260.07:34:39.81#ibcon#about to read 3, iclass 21, count 0 2006.260.07:34:39.84#ibcon#read 3, iclass 21, count 0 2006.260.07:34:39.84#ibcon#about to read 4, iclass 21, count 0 2006.260.07:34:39.84#ibcon#read 4, iclass 21, count 0 2006.260.07:34:39.84#ibcon#about to read 5, iclass 21, count 0 2006.260.07:34:39.84#ibcon#read 5, iclass 21, count 0 2006.260.07:34:39.84#ibcon#about to read 6, iclass 21, count 0 2006.260.07:34:39.84#ibcon#read 6, iclass 21, count 0 2006.260.07:34:39.84#ibcon#end of sib2, iclass 21, count 0 2006.260.07:34:39.84#ibcon#*after write, iclass 21, count 0 2006.260.07:34:39.84#ibcon#*before return 0, iclass 21, count 0 2006.260.07:34:39.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:39.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:39.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:34:39.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:34:39.84$vc4f8/valo=3,672.99 2006.260.07:34:39.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:34:39.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:34:39.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:39.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:39.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:39.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:39.84#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:34:39.84#ibcon#first serial, iclass 23, count 0 2006.260.07:34:39.84#ibcon#enter sib2, iclass 23, count 0 2006.260.07:34:39.84#ibcon#flushed, iclass 23, count 0 2006.260.07:34:39.84#ibcon#about to write, iclass 23, count 0 2006.260.07:34:39.84#ibcon#wrote, iclass 23, count 0 2006.260.07:34:39.84#ibcon#about to read 3, iclass 23, count 0 2006.260.07:34:39.86#ibcon#read 3, iclass 23, count 0 2006.260.07:34:39.86#ibcon#about to read 4, iclass 23, count 0 2006.260.07:34:39.86#ibcon#read 4, iclass 23, count 0 2006.260.07:34:39.86#ibcon#about to read 5, iclass 23, count 0 2006.260.07:34:39.86#ibcon#read 5, iclass 23, count 0 2006.260.07:34:39.86#ibcon#about to read 6, iclass 23, count 0 2006.260.07:34:39.86#ibcon#read 6, iclass 23, count 0 2006.260.07:34:39.86#ibcon#end of sib2, iclass 23, count 0 2006.260.07:34:39.86#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:34:39.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:34:39.86#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:34:39.86#ibcon#*before write, iclass 23, count 0 2006.260.07:34:39.86#ibcon#enter sib2, iclass 23, count 0 2006.260.07:34:39.86#ibcon#flushed, iclass 23, count 0 2006.260.07:34:39.86#ibcon#about to write, iclass 23, count 0 2006.260.07:34:39.86#ibcon#wrote, iclass 23, count 0 2006.260.07:34:39.86#ibcon#about to read 3, iclass 23, count 0 2006.260.07:34:39.90#ibcon#read 3, iclass 23, count 0 2006.260.07:34:39.90#ibcon#about to read 4, iclass 23, count 0 2006.260.07:34:39.90#ibcon#read 4, iclass 23, count 0 2006.260.07:34:39.90#ibcon#about to read 5, iclass 23, count 0 2006.260.07:34:39.90#ibcon#read 5, iclass 23, count 0 2006.260.07:34:39.90#ibcon#about to read 6, iclass 23, count 0 2006.260.07:34:39.90#ibcon#read 6, iclass 23, count 0 2006.260.07:34:39.90#ibcon#end of sib2, iclass 23, count 0 2006.260.07:34:39.90#ibcon#*after write, iclass 23, count 0 2006.260.07:34:39.90#ibcon#*before return 0, iclass 23, count 0 2006.260.07:34:39.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:39.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:39.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:34:39.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:34:39.90$vc4f8/va=3,8 2006.260.07:34:39.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:34:39.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:34:39.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:39.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:39.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:39.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:39.96#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:34:39.96#ibcon#first serial, iclass 25, count 2 2006.260.07:34:39.96#ibcon#enter sib2, iclass 25, count 2 2006.260.07:34:39.96#ibcon#flushed, iclass 25, count 2 2006.260.07:34:39.96#ibcon#about to write, iclass 25, count 2 2006.260.07:34:39.96#ibcon#wrote, iclass 25, count 2 2006.260.07:34:39.96#ibcon#about to read 3, iclass 25, count 2 2006.260.07:34:39.99#ibcon#read 3, iclass 25, count 2 2006.260.07:34:39.99#ibcon#about to read 4, iclass 25, count 2 2006.260.07:34:39.99#ibcon#read 4, iclass 25, count 2 2006.260.07:34:39.99#ibcon#about to read 5, iclass 25, count 2 2006.260.07:34:39.99#ibcon#read 5, iclass 25, count 2 2006.260.07:34:39.99#ibcon#about to read 6, iclass 25, count 2 2006.260.07:34:39.99#ibcon#read 6, iclass 25, count 2 2006.260.07:34:39.99#ibcon#end of sib2, iclass 25, count 2 2006.260.07:34:39.99#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:34:39.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:34:39.99#ibcon#[25=AT03-08\r\n] 2006.260.07:34:39.99#ibcon#*before write, iclass 25, count 2 2006.260.07:34:39.99#ibcon#enter sib2, iclass 25, count 2 2006.260.07:34:39.99#ibcon#flushed, iclass 25, count 2 2006.260.07:34:39.99#ibcon#about to write, iclass 25, count 2 2006.260.07:34:39.99#ibcon#wrote, iclass 25, count 2 2006.260.07:34:39.99#ibcon#about to read 3, iclass 25, count 2 2006.260.07:34:40.02#ibcon#read 3, iclass 25, count 2 2006.260.07:34:40.02#ibcon#about to read 4, iclass 25, count 2 2006.260.07:34:40.02#ibcon#read 4, iclass 25, count 2 2006.260.07:34:40.02#ibcon#about to read 5, iclass 25, count 2 2006.260.07:34:40.02#ibcon#read 5, iclass 25, count 2 2006.260.07:34:40.02#ibcon#about to read 6, iclass 25, count 2 2006.260.07:34:40.02#ibcon#read 6, iclass 25, count 2 2006.260.07:34:40.02#ibcon#end of sib2, iclass 25, count 2 2006.260.07:34:40.02#ibcon#*after write, iclass 25, count 2 2006.260.07:34:40.02#ibcon#*before return 0, iclass 25, count 2 2006.260.07:34:40.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:40.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:40.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:34:40.02#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:40.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:40.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:40.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:40.14#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:34:40.14#ibcon#first serial, iclass 25, count 0 2006.260.07:34:40.14#ibcon#enter sib2, iclass 25, count 0 2006.260.07:34:40.14#ibcon#flushed, iclass 25, count 0 2006.260.07:34:40.14#ibcon#about to write, iclass 25, count 0 2006.260.07:34:40.14#ibcon#wrote, iclass 25, count 0 2006.260.07:34:40.14#ibcon#about to read 3, iclass 25, count 0 2006.260.07:34:40.16#ibcon#read 3, iclass 25, count 0 2006.260.07:34:40.16#ibcon#about to read 4, iclass 25, count 0 2006.260.07:34:40.16#ibcon#read 4, iclass 25, count 0 2006.260.07:34:40.16#ibcon#about to read 5, iclass 25, count 0 2006.260.07:34:40.16#ibcon#read 5, iclass 25, count 0 2006.260.07:34:40.16#ibcon#about to read 6, iclass 25, count 0 2006.260.07:34:40.16#ibcon#read 6, iclass 25, count 0 2006.260.07:34:40.16#ibcon#end of sib2, iclass 25, count 0 2006.260.07:34:40.16#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:34:40.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:34:40.16#ibcon#[25=USB\r\n] 2006.260.07:34:40.16#ibcon#*before write, iclass 25, count 0 2006.260.07:34:40.16#ibcon#enter sib2, iclass 25, count 0 2006.260.07:34:40.16#ibcon#flushed, iclass 25, count 0 2006.260.07:34:40.16#ibcon#about to write, iclass 25, count 0 2006.260.07:34:40.16#ibcon#wrote, iclass 25, count 0 2006.260.07:34:40.16#ibcon#about to read 3, iclass 25, count 0 2006.260.07:34:40.19#ibcon#read 3, iclass 25, count 0 2006.260.07:34:40.19#ibcon#about to read 4, iclass 25, count 0 2006.260.07:34:40.19#ibcon#read 4, iclass 25, count 0 2006.260.07:34:40.19#ibcon#about to read 5, iclass 25, count 0 2006.260.07:34:40.19#ibcon#read 5, iclass 25, count 0 2006.260.07:34:40.19#ibcon#about to read 6, iclass 25, count 0 2006.260.07:34:40.19#ibcon#read 6, iclass 25, count 0 2006.260.07:34:40.19#ibcon#end of sib2, iclass 25, count 0 2006.260.07:34:40.19#ibcon#*after write, iclass 25, count 0 2006.260.07:34:40.19#ibcon#*before return 0, iclass 25, count 0 2006.260.07:34:40.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:40.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:40.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:34:40.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:34:40.19$vc4f8/valo=4,832.99 2006.260.07:34:40.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:34:40.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:34:40.19#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:40.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:34:40.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:34:40.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:34:40.19#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:34:40.19#ibcon#first serial, iclass 27, count 0 2006.260.07:34:40.19#ibcon#enter sib2, iclass 27, count 0 2006.260.07:34:40.19#ibcon#flushed, iclass 27, count 0 2006.260.07:34:40.19#ibcon#about to write, iclass 27, count 0 2006.260.07:34:40.19#ibcon#wrote, iclass 27, count 0 2006.260.07:34:40.19#ibcon#about to read 3, iclass 27, count 0 2006.260.07:34:40.21#ibcon#read 3, iclass 27, count 0 2006.260.07:34:40.21#ibcon#about to read 4, iclass 27, count 0 2006.260.07:34:40.21#ibcon#read 4, iclass 27, count 0 2006.260.07:34:40.21#ibcon#about to read 5, iclass 27, count 0 2006.260.07:34:40.21#ibcon#read 5, iclass 27, count 0 2006.260.07:34:40.21#ibcon#about to read 6, iclass 27, count 0 2006.260.07:34:40.21#ibcon#read 6, iclass 27, count 0 2006.260.07:34:40.21#ibcon#end of sib2, iclass 27, count 0 2006.260.07:34:40.21#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:34:40.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:34:40.21#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:34:40.21#ibcon#*before write, iclass 27, count 0 2006.260.07:34:40.21#ibcon#enter sib2, iclass 27, count 0 2006.260.07:34:40.21#ibcon#flushed, iclass 27, count 0 2006.260.07:34:40.21#ibcon#about to write, iclass 27, count 0 2006.260.07:34:40.21#ibcon#wrote, iclass 27, count 0 2006.260.07:34:40.21#ibcon#about to read 3, iclass 27, count 0 2006.260.07:34:40.25#ibcon#read 3, iclass 27, count 0 2006.260.07:34:40.25#ibcon#about to read 4, iclass 27, count 0 2006.260.07:34:40.25#ibcon#read 4, iclass 27, count 0 2006.260.07:34:40.25#ibcon#about to read 5, iclass 27, count 0 2006.260.07:34:40.25#ibcon#read 5, iclass 27, count 0 2006.260.07:34:40.25#ibcon#about to read 6, iclass 27, count 0 2006.260.07:34:40.25#ibcon#read 6, iclass 27, count 0 2006.260.07:34:40.25#ibcon#end of sib2, iclass 27, count 0 2006.260.07:34:40.25#ibcon#*after write, iclass 27, count 0 2006.260.07:34:40.25#ibcon#*before return 0, iclass 27, count 0 2006.260.07:34:40.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:34:40.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:34:40.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:34:40.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:34:40.25$vc4f8/va=4,7 2006.260.07:34:40.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:34:40.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:34:40.25#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:40.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:34:40.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:34:40.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:34:40.31#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:34:40.31#ibcon#first serial, iclass 29, count 2 2006.260.07:34:40.31#ibcon#enter sib2, iclass 29, count 2 2006.260.07:34:40.31#ibcon#flushed, iclass 29, count 2 2006.260.07:34:40.31#ibcon#about to write, iclass 29, count 2 2006.260.07:34:40.31#ibcon#wrote, iclass 29, count 2 2006.260.07:34:40.31#ibcon#about to read 3, iclass 29, count 2 2006.260.07:34:40.33#ibcon#read 3, iclass 29, count 2 2006.260.07:34:40.33#ibcon#about to read 4, iclass 29, count 2 2006.260.07:34:40.33#ibcon#read 4, iclass 29, count 2 2006.260.07:34:40.33#ibcon#about to read 5, iclass 29, count 2 2006.260.07:34:40.33#ibcon#read 5, iclass 29, count 2 2006.260.07:34:40.33#ibcon#about to read 6, iclass 29, count 2 2006.260.07:34:40.33#ibcon#read 6, iclass 29, count 2 2006.260.07:34:40.33#ibcon#end of sib2, iclass 29, count 2 2006.260.07:34:40.33#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:34:40.33#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:34:40.33#ibcon#[25=AT04-07\r\n] 2006.260.07:34:40.33#ibcon#*before write, iclass 29, count 2 2006.260.07:34:40.33#ibcon#enter sib2, iclass 29, count 2 2006.260.07:34:40.33#ibcon#flushed, iclass 29, count 2 2006.260.07:34:40.33#ibcon#about to write, iclass 29, count 2 2006.260.07:34:40.33#ibcon#wrote, iclass 29, count 2 2006.260.07:34:40.33#ibcon#about to read 3, iclass 29, count 2 2006.260.07:34:40.36#ibcon#read 3, iclass 29, count 2 2006.260.07:34:40.36#ibcon#about to read 4, iclass 29, count 2 2006.260.07:34:40.36#ibcon#read 4, iclass 29, count 2 2006.260.07:34:40.36#ibcon#about to read 5, iclass 29, count 2 2006.260.07:34:40.36#ibcon#read 5, iclass 29, count 2 2006.260.07:34:40.36#ibcon#about to read 6, iclass 29, count 2 2006.260.07:34:40.36#ibcon#read 6, iclass 29, count 2 2006.260.07:34:40.36#ibcon#end of sib2, iclass 29, count 2 2006.260.07:34:40.36#ibcon#*after write, iclass 29, count 2 2006.260.07:34:40.36#ibcon#*before return 0, iclass 29, count 2 2006.260.07:34:40.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:34:40.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:34:40.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:34:40.36#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:40.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:34:40.48#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:34:40.48#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:34:40.48#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:34:40.48#ibcon#first serial, iclass 29, count 0 2006.260.07:34:40.48#ibcon#enter sib2, iclass 29, count 0 2006.260.07:34:40.48#ibcon#flushed, iclass 29, count 0 2006.260.07:34:40.48#ibcon#about to write, iclass 29, count 0 2006.260.07:34:40.48#ibcon#wrote, iclass 29, count 0 2006.260.07:34:40.48#ibcon#about to read 3, iclass 29, count 0 2006.260.07:34:40.50#ibcon#read 3, iclass 29, count 0 2006.260.07:34:40.50#ibcon#about to read 4, iclass 29, count 0 2006.260.07:34:40.50#ibcon#read 4, iclass 29, count 0 2006.260.07:34:40.50#ibcon#about to read 5, iclass 29, count 0 2006.260.07:34:40.50#ibcon#read 5, iclass 29, count 0 2006.260.07:34:40.50#ibcon#about to read 6, iclass 29, count 0 2006.260.07:34:40.50#ibcon#read 6, iclass 29, count 0 2006.260.07:34:40.50#ibcon#end of sib2, iclass 29, count 0 2006.260.07:34:40.50#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:34:40.50#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:34:40.50#ibcon#[25=USB\r\n] 2006.260.07:34:40.50#ibcon#*before write, iclass 29, count 0 2006.260.07:34:40.50#ibcon#enter sib2, iclass 29, count 0 2006.260.07:34:40.50#ibcon#flushed, iclass 29, count 0 2006.260.07:34:40.50#ibcon#about to write, iclass 29, count 0 2006.260.07:34:40.50#ibcon#wrote, iclass 29, count 0 2006.260.07:34:40.50#ibcon#about to read 3, iclass 29, count 0 2006.260.07:34:40.53#ibcon#read 3, iclass 29, count 0 2006.260.07:34:40.53#ibcon#about to read 4, iclass 29, count 0 2006.260.07:34:40.53#ibcon#read 4, iclass 29, count 0 2006.260.07:34:40.53#ibcon#about to read 5, iclass 29, count 0 2006.260.07:34:40.53#ibcon#read 5, iclass 29, count 0 2006.260.07:34:40.53#ibcon#about to read 6, iclass 29, count 0 2006.260.07:34:40.53#ibcon#read 6, iclass 29, count 0 2006.260.07:34:40.53#ibcon#end of sib2, iclass 29, count 0 2006.260.07:34:40.53#ibcon#*after write, iclass 29, count 0 2006.260.07:34:40.53#ibcon#*before return 0, iclass 29, count 0 2006.260.07:34:40.53#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:34:40.53#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:34:40.53#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:34:40.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:34:40.53$vc4f8/valo=5,652.99 2006.260.07:34:40.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:34:40.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:34:40.53#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:40.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:40.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:40.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:40.53#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:34:40.53#ibcon#first serial, iclass 31, count 0 2006.260.07:34:40.53#ibcon#enter sib2, iclass 31, count 0 2006.260.07:34:40.53#ibcon#flushed, iclass 31, count 0 2006.260.07:34:40.53#ibcon#about to write, iclass 31, count 0 2006.260.07:34:40.53#ibcon#wrote, iclass 31, count 0 2006.260.07:34:40.53#ibcon#about to read 3, iclass 31, count 0 2006.260.07:34:40.55#ibcon#read 3, iclass 31, count 0 2006.260.07:34:40.55#ibcon#about to read 4, iclass 31, count 0 2006.260.07:34:40.55#ibcon#read 4, iclass 31, count 0 2006.260.07:34:40.55#ibcon#about to read 5, iclass 31, count 0 2006.260.07:34:40.55#ibcon#read 5, iclass 31, count 0 2006.260.07:34:40.55#ibcon#about to read 6, iclass 31, count 0 2006.260.07:34:40.55#ibcon#read 6, iclass 31, count 0 2006.260.07:34:40.55#ibcon#end of sib2, iclass 31, count 0 2006.260.07:34:40.55#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:34:40.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:34:40.55#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:34:40.55#ibcon#*before write, iclass 31, count 0 2006.260.07:34:40.55#ibcon#enter sib2, iclass 31, count 0 2006.260.07:34:40.55#ibcon#flushed, iclass 31, count 0 2006.260.07:34:40.55#ibcon#about to write, iclass 31, count 0 2006.260.07:34:40.55#ibcon#wrote, iclass 31, count 0 2006.260.07:34:40.55#ibcon#about to read 3, iclass 31, count 0 2006.260.07:34:40.59#ibcon#read 3, iclass 31, count 0 2006.260.07:34:40.59#ibcon#about to read 4, iclass 31, count 0 2006.260.07:34:40.59#ibcon#read 4, iclass 31, count 0 2006.260.07:34:40.59#ibcon#about to read 5, iclass 31, count 0 2006.260.07:34:40.59#ibcon#read 5, iclass 31, count 0 2006.260.07:34:40.59#ibcon#about to read 6, iclass 31, count 0 2006.260.07:34:40.59#ibcon#read 6, iclass 31, count 0 2006.260.07:34:40.59#ibcon#end of sib2, iclass 31, count 0 2006.260.07:34:40.59#ibcon#*after write, iclass 31, count 0 2006.260.07:34:40.59#ibcon#*before return 0, iclass 31, count 0 2006.260.07:34:40.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:40.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:40.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:34:40.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:34:40.59$vc4f8/va=5,7 2006.260.07:34:40.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:34:40.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:34:40.59#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:40.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:40.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:40.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:40.65#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:34:40.65#ibcon#first serial, iclass 33, count 2 2006.260.07:34:40.65#ibcon#enter sib2, iclass 33, count 2 2006.260.07:34:40.65#ibcon#flushed, iclass 33, count 2 2006.260.07:34:40.65#ibcon#about to write, iclass 33, count 2 2006.260.07:34:40.65#ibcon#wrote, iclass 33, count 2 2006.260.07:34:40.65#ibcon#about to read 3, iclass 33, count 2 2006.260.07:34:40.67#ibcon#read 3, iclass 33, count 2 2006.260.07:34:40.67#ibcon#about to read 4, iclass 33, count 2 2006.260.07:34:40.67#ibcon#read 4, iclass 33, count 2 2006.260.07:34:40.67#ibcon#about to read 5, iclass 33, count 2 2006.260.07:34:40.67#ibcon#read 5, iclass 33, count 2 2006.260.07:34:40.67#ibcon#about to read 6, iclass 33, count 2 2006.260.07:34:40.67#ibcon#read 6, iclass 33, count 2 2006.260.07:34:40.67#ibcon#end of sib2, iclass 33, count 2 2006.260.07:34:40.67#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:34:40.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:34:40.67#ibcon#[25=AT05-07\r\n] 2006.260.07:34:40.67#ibcon#*before write, iclass 33, count 2 2006.260.07:34:40.67#ibcon#enter sib2, iclass 33, count 2 2006.260.07:34:40.67#ibcon#flushed, iclass 33, count 2 2006.260.07:34:40.67#ibcon#about to write, iclass 33, count 2 2006.260.07:34:40.67#ibcon#wrote, iclass 33, count 2 2006.260.07:34:40.67#ibcon#about to read 3, iclass 33, count 2 2006.260.07:34:40.70#ibcon#read 3, iclass 33, count 2 2006.260.07:34:40.70#ibcon#about to read 4, iclass 33, count 2 2006.260.07:34:40.70#ibcon#read 4, iclass 33, count 2 2006.260.07:34:40.70#ibcon#about to read 5, iclass 33, count 2 2006.260.07:34:40.70#ibcon#read 5, iclass 33, count 2 2006.260.07:34:40.70#ibcon#about to read 6, iclass 33, count 2 2006.260.07:34:40.70#ibcon#read 6, iclass 33, count 2 2006.260.07:34:40.70#ibcon#end of sib2, iclass 33, count 2 2006.260.07:34:40.70#ibcon#*after write, iclass 33, count 2 2006.260.07:34:40.70#ibcon#*before return 0, iclass 33, count 2 2006.260.07:34:40.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:40.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:40.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:34:40.70#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:40.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:40.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:40.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:40.82#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:34:40.82#ibcon#first serial, iclass 33, count 0 2006.260.07:34:40.82#ibcon#enter sib2, iclass 33, count 0 2006.260.07:34:40.82#ibcon#flushed, iclass 33, count 0 2006.260.07:34:40.82#ibcon#about to write, iclass 33, count 0 2006.260.07:34:40.82#ibcon#wrote, iclass 33, count 0 2006.260.07:34:40.82#ibcon#about to read 3, iclass 33, count 0 2006.260.07:34:40.84#ibcon#read 3, iclass 33, count 0 2006.260.07:34:40.84#ibcon#about to read 4, iclass 33, count 0 2006.260.07:34:40.84#ibcon#read 4, iclass 33, count 0 2006.260.07:34:40.84#ibcon#about to read 5, iclass 33, count 0 2006.260.07:34:40.84#ibcon#read 5, iclass 33, count 0 2006.260.07:34:40.84#ibcon#about to read 6, iclass 33, count 0 2006.260.07:34:40.84#ibcon#read 6, iclass 33, count 0 2006.260.07:34:40.84#ibcon#end of sib2, iclass 33, count 0 2006.260.07:34:40.84#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:34:40.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:34:40.84#ibcon#[25=USB\r\n] 2006.260.07:34:40.84#ibcon#*before write, iclass 33, count 0 2006.260.07:34:40.84#ibcon#enter sib2, iclass 33, count 0 2006.260.07:34:40.84#ibcon#flushed, iclass 33, count 0 2006.260.07:34:40.84#ibcon#about to write, iclass 33, count 0 2006.260.07:34:40.84#ibcon#wrote, iclass 33, count 0 2006.260.07:34:40.84#ibcon#about to read 3, iclass 33, count 0 2006.260.07:34:40.87#ibcon#read 3, iclass 33, count 0 2006.260.07:34:40.87#ibcon#about to read 4, iclass 33, count 0 2006.260.07:34:40.87#ibcon#read 4, iclass 33, count 0 2006.260.07:34:40.87#ibcon#about to read 5, iclass 33, count 0 2006.260.07:34:40.87#ibcon#read 5, iclass 33, count 0 2006.260.07:34:40.87#ibcon#about to read 6, iclass 33, count 0 2006.260.07:34:40.87#ibcon#read 6, iclass 33, count 0 2006.260.07:34:40.87#ibcon#end of sib2, iclass 33, count 0 2006.260.07:34:40.87#ibcon#*after write, iclass 33, count 0 2006.260.07:34:40.87#ibcon#*before return 0, iclass 33, count 0 2006.260.07:34:40.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:40.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:40.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:34:40.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:34:40.87$vc4f8/valo=6,772.99 2006.260.07:34:40.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:34:40.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:34:40.87#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:40.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:40.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:40.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:40.87#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:34:40.87#ibcon#first serial, iclass 35, count 0 2006.260.07:34:40.87#ibcon#enter sib2, iclass 35, count 0 2006.260.07:34:40.87#ibcon#flushed, iclass 35, count 0 2006.260.07:34:40.87#ibcon#about to write, iclass 35, count 0 2006.260.07:34:40.87#ibcon#wrote, iclass 35, count 0 2006.260.07:34:40.87#ibcon#about to read 3, iclass 35, count 0 2006.260.07:34:40.89#ibcon#read 3, iclass 35, count 0 2006.260.07:34:40.89#ibcon#about to read 4, iclass 35, count 0 2006.260.07:34:40.89#ibcon#read 4, iclass 35, count 0 2006.260.07:34:40.89#ibcon#about to read 5, iclass 35, count 0 2006.260.07:34:40.89#ibcon#read 5, iclass 35, count 0 2006.260.07:34:40.89#ibcon#about to read 6, iclass 35, count 0 2006.260.07:34:40.89#ibcon#read 6, iclass 35, count 0 2006.260.07:34:40.89#ibcon#end of sib2, iclass 35, count 0 2006.260.07:34:40.89#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:34:40.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:34:40.89#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:34:40.89#ibcon#*before write, iclass 35, count 0 2006.260.07:34:40.89#ibcon#enter sib2, iclass 35, count 0 2006.260.07:34:40.89#ibcon#flushed, iclass 35, count 0 2006.260.07:34:40.89#ibcon#about to write, iclass 35, count 0 2006.260.07:34:40.89#ibcon#wrote, iclass 35, count 0 2006.260.07:34:40.89#ibcon#about to read 3, iclass 35, count 0 2006.260.07:34:40.93#ibcon#read 3, iclass 35, count 0 2006.260.07:34:40.93#ibcon#about to read 4, iclass 35, count 0 2006.260.07:34:40.93#ibcon#read 4, iclass 35, count 0 2006.260.07:34:40.93#ibcon#about to read 5, iclass 35, count 0 2006.260.07:34:40.93#ibcon#read 5, iclass 35, count 0 2006.260.07:34:40.93#ibcon#about to read 6, iclass 35, count 0 2006.260.07:34:40.93#ibcon#read 6, iclass 35, count 0 2006.260.07:34:40.93#ibcon#end of sib2, iclass 35, count 0 2006.260.07:34:40.93#ibcon#*after write, iclass 35, count 0 2006.260.07:34:40.93#ibcon#*before return 0, iclass 35, count 0 2006.260.07:34:40.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:40.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:40.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:34:40.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:34:40.93$vc4f8/va=6,6 2006.260.07:34:40.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:34:40.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:34:40.93#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:40.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:40.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:40.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:40.99#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:34:40.99#ibcon#first serial, iclass 37, count 2 2006.260.07:34:40.99#ibcon#enter sib2, iclass 37, count 2 2006.260.07:34:40.99#ibcon#flushed, iclass 37, count 2 2006.260.07:34:40.99#ibcon#about to write, iclass 37, count 2 2006.260.07:34:40.99#ibcon#wrote, iclass 37, count 2 2006.260.07:34:40.99#ibcon#about to read 3, iclass 37, count 2 2006.260.07:34:41.01#ibcon#read 3, iclass 37, count 2 2006.260.07:34:41.01#ibcon#about to read 4, iclass 37, count 2 2006.260.07:34:41.01#ibcon#read 4, iclass 37, count 2 2006.260.07:34:41.01#ibcon#about to read 5, iclass 37, count 2 2006.260.07:34:41.01#ibcon#read 5, iclass 37, count 2 2006.260.07:34:41.01#ibcon#about to read 6, iclass 37, count 2 2006.260.07:34:41.01#ibcon#read 6, iclass 37, count 2 2006.260.07:34:41.01#ibcon#end of sib2, iclass 37, count 2 2006.260.07:34:41.01#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:34:41.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:34:41.01#ibcon#[25=AT06-06\r\n] 2006.260.07:34:41.01#ibcon#*before write, iclass 37, count 2 2006.260.07:34:41.01#ibcon#enter sib2, iclass 37, count 2 2006.260.07:34:41.01#ibcon#flushed, iclass 37, count 2 2006.260.07:34:41.01#ibcon#about to write, iclass 37, count 2 2006.260.07:34:41.01#ibcon#wrote, iclass 37, count 2 2006.260.07:34:41.01#ibcon#about to read 3, iclass 37, count 2 2006.260.07:34:41.04#ibcon#read 3, iclass 37, count 2 2006.260.07:34:41.04#ibcon#about to read 4, iclass 37, count 2 2006.260.07:34:41.04#ibcon#read 4, iclass 37, count 2 2006.260.07:34:41.04#ibcon#about to read 5, iclass 37, count 2 2006.260.07:34:41.04#ibcon#read 5, iclass 37, count 2 2006.260.07:34:41.04#ibcon#about to read 6, iclass 37, count 2 2006.260.07:34:41.04#ibcon#read 6, iclass 37, count 2 2006.260.07:34:41.04#ibcon#end of sib2, iclass 37, count 2 2006.260.07:34:41.04#ibcon#*after write, iclass 37, count 2 2006.260.07:34:41.04#ibcon#*before return 0, iclass 37, count 2 2006.260.07:34:41.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:41.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:41.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:34:41.04#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:41.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:41.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:41.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:41.16#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:34:41.16#ibcon#first serial, iclass 37, count 0 2006.260.07:34:41.16#ibcon#enter sib2, iclass 37, count 0 2006.260.07:34:41.16#ibcon#flushed, iclass 37, count 0 2006.260.07:34:41.16#ibcon#about to write, iclass 37, count 0 2006.260.07:34:41.16#ibcon#wrote, iclass 37, count 0 2006.260.07:34:41.16#ibcon#about to read 3, iclass 37, count 0 2006.260.07:34:41.18#ibcon#read 3, iclass 37, count 0 2006.260.07:34:41.18#ibcon#about to read 4, iclass 37, count 0 2006.260.07:34:41.18#ibcon#read 4, iclass 37, count 0 2006.260.07:34:41.18#ibcon#about to read 5, iclass 37, count 0 2006.260.07:34:41.18#ibcon#read 5, iclass 37, count 0 2006.260.07:34:41.18#ibcon#about to read 6, iclass 37, count 0 2006.260.07:34:41.18#ibcon#read 6, iclass 37, count 0 2006.260.07:34:41.18#ibcon#end of sib2, iclass 37, count 0 2006.260.07:34:41.18#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:34:41.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:34:41.18#ibcon#[25=USB\r\n] 2006.260.07:34:41.18#ibcon#*before write, iclass 37, count 0 2006.260.07:34:41.18#ibcon#enter sib2, iclass 37, count 0 2006.260.07:34:41.18#ibcon#flushed, iclass 37, count 0 2006.260.07:34:41.18#ibcon#about to write, iclass 37, count 0 2006.260.07:34:41.18#ibcon#wrote, iclass 37, count 0 2006.260.07:34:41.18#ibcon#about to read 3, iclass 37, count 0 2006.260.07:34:41.21#ibcon#read 3, iclass 37, count 0 2006.260.07:34:41.21#ibcon#about to read 4, iclass 37, count 0 2006.260.07:34:41.21#ibcon#read 4, iclass 37, count 0 2006.260.07:34:41.21#ibcon#about to read 5, iclass 37, count 0 2006.260.07:34:41.21#ibcon#read 5, iclass 37, count 0 2006.260.07:34:41.21#ibcon#about to read 6, iclass 37, count 0 2006.260.07:34:41.21#ibcon#read 6, iclass 37, count 0 2006.260.07:34:41.21#ibcon#end of sib2, iclass 37, count 0 2006.260.07:34:41.21#ibcon#*after write, iclass 37, count 0 2006.260.07:34:41.21#ibcon#*before return 0, iclass 37, count 0 2006.260.07:34:41.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:41.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:41.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:34:41.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:34:41.21$vc4f8/valo=7,832.99 2006.260.07:34:41.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:34:41.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:34:41.21#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:41.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:41.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:41.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:41.21#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:34:41.21#ibcon#first serial, iclass 39, count 0 2006.260.07:34:41.21#ibcon#enter sib2, iclass 39, count 0 2006.260.07:34:41.21#ibcon#flushed, iclass 39, count 0 2006.260.07:34:41.21#ibcon#about to write, iclass 39, count 0 2006.260.07:34:41.21#ibcon#wrote, iclass 39, count 0 2006.260.07:34:41.21#ibcon#about to read 3, iclass 39, count 0 2006.260.07:34:41.23#ibcon#read 3, iclass 39, count 0 2006.260.07:34:41.23#ibcon#about to read 4, iclass 39, count 0 2006.260.07:34:41.23#ibcon#read 4, iclass 39, count 0 2006.260.07:34:41.23#ibcon#about to read 5, iclass 39, count 0 2006.260.07:34:41.23#ibcon#read 5, iclass 39, count 0 2006.260.07:34:41.23#ibcon#about to read 6, iclass 39, count 0 2006.260.07:34:41.23#ibcon#read 6, iclass 39, count 0 2006.260.07:34:41.23#ibcon#end of sib2, iclass 39, count 0 2006.260.07:34:41.23#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:34:41.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:34:41.23#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:34:41.23#ibcon#*before write, iclass 39, count 0 2006.260.07:34:41.23#ibcon#enter sib2, iclass 39, count 0 2006.260.07:34:41.23#ibcon#flushed, iclass 39, count 0 2006.260.07:34:41.23#ibcon#about to write, iclass 39, count 0 2006.260.07:34:41.23#ibcon#wrote, iclass 39, count 0 2006.260.07:34:41.23#ibcon#about to read 3, iclass 39, count 0 2006.260.07:34:41.27#ibcon#read 3, iclass 39, count 0 2006.260.07:34:41.27#ibcon#about to read 4, iclass 39, count 0 2006.260.07:34:41.27#ibcon#read 4, iclass 39, count 0 2006.260.07:34:41.27#ibcon#about to read 5, iclass 39, count 0 2006.260.07:34:41.27#ibcon#read 5, iclass 39, count 0 2006.260.07:34:41.27#ibcon#about to read 6, iclass 39, count 0 2006.260.07:34:41.27#ibcon#read 6, iclass 39, count 0 2006.260.07:34:41.27#ibcon#end of sib2, iclass 39, count 0 2006.260.07:34:41.27#ibcon#*after write, iclass 39, count 0 2006.260.07:34:41.27#ibcon#*before return 0, iclass 39, count 0 2006.260.07:34:41.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:41.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:41.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:34:41.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:34:41.27$vc4f8/va=7,6 2006.260.07:34:41.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:34:41.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:34:41.27#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:41.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:41.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:41.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:41.33#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:34:41.33#ibcon#first serial, iclass 3, count 2 2006.260.07:34:41.33#ibcon#enter sib2, iclass 3, count 2 2006.260.07:34:41.33#ibcon#flushed, iclass 3, count 2 2006.260.07:34:41.33#ibcon#about to write, iclass 3, count 2 2006.260.07:34:41.33#ibcon#wrote, iclass 3, count 2 2006.260.07:34:41.33#ibcon#about to read 3, iclass 3, count 2 2006.260.07:34:41.35#ibcon#read 3, iclass 3, count 2 2006.260.07:34:41.35#ibcon#about to read 4, iclass 3, count 2 2006.260.07:34:41.35#ibcon#read 4, iclass 3, count 2 2006.260.07:34:41.35#ibcon#about to read 5, iclass 3, count 2 2006.260.07:34:41.35#ibcon#read 5, iclass 3, count 2 2006.260.07:34:41.35#ibcon#about to read 6, iclass 3, count 2 2006.260.07:34:41.35#ibcon#read 6, iclass 3, count 2 2006.260.07:34:41.35#ibcon#end of sib2, iclass 3, count 2 2006.260.07:34:41.35#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:34:41.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:34:41.35#ibcon#[25=AT07-06\r\n] 2006.260.07:34:41.35#ibcon#*before write, iclass 3, count 2 2006.260.07:34:41.35#ibcon#enter sib2, iclass 3, count 2 2006.260.07:34:41.35#ibcon#flushed, iclass 3, count 2 2006.260.07:34:41.35#ibcon#about to write, iclass 3, count 2 2006.260.07:34:41.35#ibcon#wrote, iclass 3, count 2 2006.260.07:34:41.35#ibcon#about to read 3, iclass 3, count 2 2006.260.07:34:41.38#ibcon#read 3, iclass 3, count 2 2006.260.07:34:41.38#ibcon#about to read 4, iclass 3, count 2 2006.260.07:34:41.38#ibcon#read 4, iclass 3, count 2 2006.260.07:34:41.38#ibcon#about to read 5, iclass 3, count 2 2006.260.07:34:41.38#ibcon#read 5, iclass 3, count 2 2006.260.07:34:41.38#ibcon#about to read 6, iclass 3, count 2 2006.260.07:34:41.38#ibcon#read 6, iclass 3, count 2 2006.260.07:34:41.38#ibcon#end of sib2, iclass 3, count 2 2006.260.07:34:41.38#ibcon#*after write, iclass 3, count 2 2006.260.07:34:41.38#ibcon#*before return 0, iclass 3, count 2 2006.260.07:34:41.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:41.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:41.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:34:41.38#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:41.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:34:41.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:34:41.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:34:41.50#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:34:41.50#ibcon#first serial, iclass 3, count 0 2006.260.07:34:41.50#ibcon#enter sib2, iclass 3, count 0 2006.260.07:34:41.50#ibcon#flushed, iclass 3, count 0 2006.260.07:34:41.50#ibcon#about to write, iclass 3, count 0 2006.260.07:34:41.50#ibcon#wrote, iclass 3, count 0 2006.260.07:34:41.50#ibcon#about to read 3, iclass 3, count 0 2006.260.07:34:41.52#ibcon#read 3, iclass 3, count 0 2006.260.07:34:41.52#ibcon#about to read 4, iclass 3, count 0 2006.260.07:34:41.52#ibcon#read 4, iclass 3, count 0 2006.260.07:34:41.52#ibcon#about to read 5, iclass 3, count 0 2006.260.07:34:41.52#ibcon#read 5, iclass 3, count 0 2006.260.07:34:41.52#ibcon#about to read 6, iclass 3, count 0 2006.260.07:34:41.52#ibcon#read 6, iclass 3, count 0 2006.260.07:34:41.52#ibcon#end of sib2, iclass 3, count 0 2006.260.07:34:41.52#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:34:41.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:34:41.52#ibcon#[25=USB\r\n] 2006.260.07:34:41.52#ibcon#*before write, iclass 3, count 0 2006.260.07:34:41.52#ibcon#enter sib2, iclass 3, count 0 2006.260.07:34:41.52#ibcon#flushed, iclass 3, count 0 2006.260.07:34:41.52#ibcon#about to write, iclass 3, count 0 2006.260.07:34:41.52#ibcon#wrote, iclass 3, count 0 2006.260.07:34:41.52#ibcon#about to read 3, iclass 3, count 0 2006.260.07:34:41.55#ibcon#read 3, iclass 3, count 0 2006.260.07:34:41.55#ibcon#about to read 4, iclass 3, count 0 2006.260.07:34:41.55#ibcon#read 4, iclass 3, count 0 2006.260.07:34:41.55#ibcon#about to read 5, iclass 3, count 0 2006.260.07:34:41.55#ibcon#read 5, iclass 3, count 0 2006.260.07:34:41.55#ibcon#about to read 6, iclass 3, count 0 2006.260.07:34:41.55#ibcon#read 6, iclass 3, count 0 2006.260.07:34:41.55#ibcon#end of sib2, iclass 3, count 0 2006.260.07:34:41.55#ibcon#*after write, iclass 3, count 0 2006.260.07:34:41.55#ibcon#*before return 0, iclass 3, count 0 2006.260.07:34:41.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:34:41.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:34:41.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:34:41.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:34:41.55$vc4f8/valo=8,852.99 2006.260.07:34:41.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:34:41.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:34:41.55#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:41.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:34:41.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:34:41.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:34:41.55#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:34:41.55#ibcon#first serial, iclass 5, count 0 2006.260.07:34:41.55#ibcon#enter sib2, iclass 5, count 0 2006.260.07:34:41.55#ibcon#flushed, iclass 5, count 0 2006.260.07:34:41.55#ibcon#about to write, iclass 5, count 0 2006.260.07:34:41.55#ibcon#wrote, iclass 5, count 0 2006.260.07:34:41.55#ibcon#about to read 3, iclass 5, count 0 2006.260.07:34:41.57#ibcon#read 3, iclass 5, count 0 2006.260.07:34:41.57#ibcon#about to read 4, iclass 5, count 0 2006.260.07:34:41.57#ibcon#read 4, iclass 5, count 0 2006.260.07:34:41.57#ibcon#about to read 5, iclass 5, count 0 2006.260.07:34:41.57#ibcon#read 5, iclass 5, count 0 2006.260.07:34:41.57#ibcon#about to read 6, iclass 5, count 0 2006.260.07:34:41.57#ibcon#read 6, iclass 5, count 0 2006.260.07:34:41.57#ibcon#end of sib2, iclass 5, count 0 2006.260.07:34:41.57#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:34:41.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:34:41.57#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:34:41.57#ibcon#*before write, iclass 5, count 0 2006.260.07:34:41.57#ibcon#enter sib2, iclass 5, count 0 2006.260.07:34:41.57#ibcon#flushed, iclass 5, count 0 2006.260.07:34:41.57#ibcon#about to write, iclass 5, count 0 2006.260.07:34:41.57#ibcon#wrote, iclass 5, count 0 2006.260.07:34:41.57#ibcon#about to read 3, iclass 5, count 0 2006.260.07:34:41.61#ibcon#read 3, iclass 5, count 0 2006.260.07:34:41.61#ibcon#about to read 4, iclass 5, count 0 2006.260.07:34:41.61#ibcon#read 4, iclass 5, count 0 2006.260.07:34:41.61#ibcon#about to read 5, iclass 5, count 0 2006.260.07:34:41.61#ibcon#read 5, iclass 5, count 0 2006.260.07:34:41.61#ibcon#about to read 6, iclass 5, count 0 2006.260.07:34:41.61#ibcon#read 6, iclass 5, count 0 2006.260.07:34:41.61#ibcon#end of sib2, iclass 5, count 0 2006.260.07:34:41.61#ibcon#*after write, iclass 5, count 0 2006.260.07:34:41.61#ibcon#*before return 0, iclass 5, count 0 2006.260.07:34:41.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:34:41.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:34:41.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:34:41.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:34:41.61$vc4f8/va=8,6 2006.260.07:34:41.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.07:34:41.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.07:34:41.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:41.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:34:41.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:34:41.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:34:41.67#ibcon#enter wrdev, iclass 7, count 2 2006.260.07:34:41.67#ibcon#first serial, iclass 7, count 2 2006.260.07:34:41.67#ibcon#enter sib2, iclass 7, count 2 2006.260.07:34:41.67#ibcon#flushed, iclass 7, count 2 2006.260.07:34:41.67#ibcon#about to write, iclass 7, count 2 2006.260.07:34:41.67#ibcon#wrote, iclass 7, count 2 2006.260.07:34:41.67#ibcon#about to read 3, iclass 7, count 2 2006.260.07:34:41.69#ibcon#read 3, iclass 7, count 2 2006.260.07:34:41.69#ibcon#about to read 4, iclass 7, count 2 2006.260.07:34:41.69#ibcon#read 4, iclass 7, count 2 2006.260.07:34:41.69#ibcon#about to read 5, iclass 7, count 2 2006.260.07:34:41.69#ibcon#read 5, iclass 7, count 2 2006.260.07:34:41.69#ibcon#about to read 6, iclass 7, count 2 2006.260.07:34:41.69#ibcon#read 6, iclass 7, count 2 2006.260.07:34:41.69#ibcon#end of sib2, iclass 7, count 2 2006.260.07:34:41.69#ibcon#*mode == 0, iclass 7, count 2 2006.260.07:34:41.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.07:34:41.69#ibcon#[25=AT08-06\r\n] 2006.260.07:34:41.69#ibcon#*before write, iclass 7, count 2 2006.260.07:34:41.69#ibcon#enter sib2, iclass 7, count 2 2006.260.07:34:41.69#ibcon#flushed, iclass 7, count 2 2006.260.07:34:41.69#ibcon#about to write, iclass 7, count 2 2006.260.07:34:41.69#ibcon#wrote, iclass 7, count 2 2006.260.07:34:41.69#ibcon#about to read 3, iclass 7, count 2 2006.260.07:34:41.72#ibcon#read 3, iclass 7, count 2 2006.260.07:34:41.72#ibcon#about to read 4, iclass 7, count 2 2006.260.07:34:41.72#ibcon#read 4, iclass 7, count 2 2006.260.07:34:41.72#ibcon#about to read 5, iclass 7, count 2 2006.260.07:34:41.72#ibcon#read 5, iclass 7, count 2 2006.260.07:34:41.72#ibcon#about to read 6, iclass 7, count 2 2006.260.07:34:41.72#ibcon#read 6, iclass 7, count 2 2006.260.07:34:41.72#ibcon#end of sib2, iclass 7, count 2 2006.260.07:34:41.72#ibcon#*after write, iclass 7, count 2 2006.260.07:34:41.72#ibcon#*before return 0, iclass 7, count 2 2006.260.07:34:41.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:34:41.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:34:41.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.07:34:41.72#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:41.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:34:41.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:34:41.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:34:41.84#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:34:41.84#ibcon#first serial, iclass 7, count 0 2006.260.07:34:41.84#ibcon#enter sib2, iclass 7, count 0 2006.260.07:34:41.84#ibcon#flushed, iclass 7, count 0 2006.260.07:34:41.84#ibcon#about to write, iclass 7, count 0 2006.260.07:34:41.84#ibcon#wrote, iclass 7, count 0 2006.260.07:34:41.84#ibcon#about to read 3, iclass 7, count 0 2006.260.07:34:41.86#ibcon#read 3, iclass 7, count 0 2006.260.07:34:41.86#ibcon#about to read 4, iclass 7, count 0 2006.260.07:34:41.86#ibcon#read 4, iclass 7, count 0 2006.260.07:34:41.86#ibcon#about to read 5, iclass 7, count 0 2006.260.07:34:41.86#ibcon#read 5, iclass 7, count 0 2006.260.07:34:41.86#ibcon#about to read 6, iclass 7, count 0 2006.260.07:34:41.86#ibcon#read 6, iclass 7, count 0 2006.260.07:34:41.86#ibcon#end of sib2, iclass 7, count 0 2006.260.07:34:41.86#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:34:41.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:34:41.86#ibcon#[25=USB\r\n] 2006.260.07:34:41.86#ibcon#*before write, iclass 7, count 0 2006.260.07:34:41.86#ibcon#enter sib2, iclass 7, count 0 2006.260.07:34:41.86#ibcon#flushed, iclass 7, count 0 2006.260.07:34:41.86#ibcon#about to write, iclass 7, count 0 2006.260.07:34:41.86#ibcon#wrote, iclass 7, count 0 2006.260.07:34:41.86#ibcon#about to read 3, iclass 7, count 0 2006.260.07:34:41.89#ibcon#read 3, iclass 7, count 0 2006.260.07:34:41.89#ibcon#about to read 4, iclass 7, count 0 2006.260.07:34:41.89#ibcon#read 4, iclass 7, count 0 2006.260.07:34:41.89#ibcon#about to read 5, iclass 7, count 0 2006.260.07:34:41.89#ibcon#read 5, iclass 7, count 0 2006.260.07:34:41.89#ibcon#about to read 6, iclass 7, count 0 2006.260.07:34:41.89#ibcon#read 6, iclass 7, count 0 2006.260.07:34:41.89#ibcon#end of sib2, iclass 7, count 0 2006.260.07:34:41.89#ibcon#*after write, iclass 7, count 0 2006.260.07:34:41.89#ibcon#*before return 0, iclass 7, count 0 2006.260.07:34:41.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:34:41.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:34:41.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:34:41.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:34:41.89$vc4f8/vblo=1,632.99 2006.260.07:34:41.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.07:34:41.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.07:34:41.89#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:41.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:34:41.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:34:41.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:34:41.89#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:34:41.89#ibcon#first serial, iclass 11, count 0 2006.260.07:34:41.89#ibcon#enter sib2, iclass 11, count 0 2006.260.07:34:41.89#ibcon#flushed, iclass 11, count 0 2006.260.07:34:41.89#ibcon#about to write, iclass 11, count 0 2006.260.07:34:41.89#ibcon#wrote, iclass 11, count 0 2006.260.07:34:41.89#ibcon#about to read 3, iclass 11, count 0 2006.260.07:34:41.91#ibcon#read 3, iclass 11, count 0 2006.260.07:34:41.91#ibcon#about to read 4, iclass 11, count 0 2006.260.07:34:41.91#ibcon#read 4, iclass 11, count 0 2006.260.07:34:41.91#ibcon#about to read 5, iclass 11, count 0 2006.260.07:34:41.91#ibcon#read 5, iclass 11, count 0 2006.260.07:34:41.91#ibcon#about to read 6, iclass 11, count 0 2006.260.07:34:41.91#ibcon#read 6, iclass 11, count 0 2006.260.07:34:41.91#ibcon#end of sib2, iclass 11, count 0 2006.260.07:34:41.91#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:34:41.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:34:41.91#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:34:41.91#ibcon#*before write, iclass 11, count 0 2006.260.07:34:41.91#ibcon#enter sib2, iclass 11, count 0 2006.260.07:34:41.91#ibcon#flushed, iclass 11, count 0 2006.260.07:34:41.91#ibcon#about to write, iclass 11, count 0 2006.260.07:34:41.91#ibcon#wrote, iclass 11, count 0 2006.260.07:34:41.91#ibcon#about to read 3, iclass 11, count 0 2006.260.07:34:41.95#ibcon#read 3, iclass 11, count 0 2006.260.07:34:41.95#ibcon#about to read 4, iclass 11, count 0 2006.260.07:34:41.95#ibcon#read 4, iclass 11, count 0 2006.260.07:34:41.95#ibcon#about to read 5, iclass 11, count 0 2006.260.07:34:41.95#ibcon#read 5, iclass 11, count 0 2006.260.07:34:41.95#ibcon#about to read 6, iclass 11, count 0 2006.260.07:34:41.95#ibcon#read 6, iclass 11, count 0 2006.260.07:34:41.95#ibcon#end of sib2, iclass 11, count 0 2006.260.07:34:41.95#ibcon#*after write, iclass 11, count 0 2006.260.07:34:41.95#ibcon#*before return 0, iclass 11, count 0 2006.260.07:34:41.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:34:41.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:34:41.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:34:41.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:34:41.95$vc4f8/vb=1,4 2006.260.07:34:41.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.07:34:41.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.07:34:41.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:41.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:34:41.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:34:41.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:34:41.95#ibcon#enter wrdev, iclass 13, count 2 2006.260.07:34:41.95#ibcon#first serial, iclass 13, count 2 2006.260.07:34:41.95#ibcon#enter sib2, iclass 13, count 2 2006.260.07:34:41.95#ibcon#flushed, iclass 13, count 2 2006.260.07:34:41.95#ibcon#about to write, iclass 13, count 2 2006.260.07:34:41.95#ibcon#wrote, iclass 13, count 2 2006.260.07:34:41.95#ibcon#about to read 3, iclass 13, count 2 2006.260.07:34:41.97#ibcon#read 3, iclass 13, count 2 2006.260.07:34:41.97#ibcon#about to read 4, iclass 13, count 2 2006.260.07:34:41.97#ibcon#read 4, iclass 13, count 2 2006.260.07:34:41.97#ibcon#about to read 5, iclass 13, count 2 2006.260.07:34:41.97#ibcon#read 5, iclass 13, count 2 2006.260.07:34:41.97#ibcon#about to read 6, iclass 13, count 2 2006.260.07:34:41.97#ibcon#read 6, iclass 13, count 2 2006.260.07:34:41.97#ibcon#end of sib2, iclass 13, count 2 2006.260.07:34:41.97#ibcon#*mode == 0, iclass 13, count 2 2006.260.07:34:41.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.07:34:41.97#ibcon#[27=AT01-04\r\n] 2006.260.07:34:41.97#ibcon#*before write, iclass 13, count 2 2006.260.07:34:41.97#ibcon#enter sib2, iclass 13, count 2 2006.260.07:34:41.97#ibcon#flushed, iclass 13, count 2 2006.260.07:34:41.97#ibcon#about to write, iclass 13, count 2 2006.260.07:34:41.97#ibcon#wrote, iclass 13, count 2 2006.260.07:34:41.97#ibcon#about to read 3, iclass 13, count 2 2006.260.07:34:42.00#ibcon#read 3, iclass 13, count 2 2006.260.07:34:42.00#ibcon#about to read 4, iclass 13, count 2 2006.260.07:34:42.00#ibcon#read 4, iclass 13, count 2 2006.260.07:34:42.00#ibcon#about to read 5, iclass 13, count 2 2006.260.07:34:42.00#ibcon#read 5, iclass 13, count 2 2006.260.07:34:42.00#ibcon#about to read 6, iclass 13, count 2 2006.260.07:34:42.00#ibcon#read 6, iclass 13, count 2 2006.260.07:34:42.00#ibcon#end of sib2, iclass 13, count 2 2006.260.07:34:42.00#ibcon#*after write, iclass 13, count 2 2006.260.07:34:42.00#ibcon#*before return 0, iclass 13, count 2 2006.260.07:34:42.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:34:42.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:34:42.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.07:34:42.00#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:42.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:34:42.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:34:42.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:34:42.12#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:34:42.12#ibcon#first serial, iclass 13, count 0 2006.260.07:34:42.12#ibcon#enter sib2, iclass 13, count 0 2006.260.07:34:42.12#ibcon#flushed, iclass 13, count 0 2006.260.07:34:42.12#ibcon#about to write, iclass 13, count 0 2006.260.07:34:42.12#ibcon#wrote, iclass 13, count 0 2006.260.07:34:42.12#ibcon#about to read 3, iclass 13, count 0 2006.260.07:34:42.14#ibcon#read 3, iclass 13, count 0 2006.260.07:34:42.14#ibcon#about to read 4, iclass 13, count 0 2006.260.07:34:42.14#ibcon#read 4, iclass 13, count 0 2006.260.07:34:42.14#ibcon#about to read 5, iclass 13, count 0 2006.260.07:34:42.14#ibcon#read 5, iclass 13, count 0 2006.260.07:34:42.14#ibcon#about to read 6, iclass 13, count 0 2006.260.07:34:42.14#ibcon#read 6, iclass 13, count 0 2006.260.07:34:42.14#ibcon#end of sib2, iclass 13, count 0 2006.260.07:34:42.14#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:34:42.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:34:42.14#ibcon#[27=USB\r\n] 2006.260.07:34:42.14#ibcon#*before write, iclass 13, count 0 2006.260.07:34:42.14#ibcon#enter sib2, iclass 13, count 0 2006.260.07:34:42.14#ibcon#flushed, iclass 13, count 0 2006.260.07:34:42.14#ibcon#about to write, iclass 13, count 0 2006.260.07:34:42.14#ibcon#wrote, iclass 13, count 0 2006.260.07:34:42.14#ibcon#about to read 3, iclass 13, count 0 2006.260.07:34:42.17#ibcon#read 3, iclass 13, count 0 2006.260.07:34:42.17#ibcon#about to read 4, iclass 13, count 0 2006.260.07:34:42.17#ibcon#read 4, iclass 13, count 0 2006.260.07:34:42.17#ibcon#about to read 5, iclass 13, count 0 2006.260.07:34:42.17#ibcon#read 5, iclass 13, count 0 2006.260.07:34:42.17#ibcon#about to read 6, iclass 13, count 0 2006.260.07:34:42.17#ibcon#read 6, iclass 13, count 0 2006.260.07:34:42.17#ibcon#end of sib2, iclass 13, count 0 2006.260.07:34:42.17#ibcon#*after write, iclass 13, count 0 2006.260.07:34:42.17#ibcon#*before return 0, iclass 13, count 0 2006.260.07:34:42.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:34:42.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:34:42.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:34:42.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:34:42.17$vc4f8/vblo=2,640.99 2006.260.07:34:42.17#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:34:42.17#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:34:42.17#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:42.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:42.17#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:42.17#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:42.17#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:34:42.17#ibcon#first serial, iclass 15, count 0 2006.260.07:34:42.17#ibcon#enter sib2, iclass 15, count 0 2006.260.07:34:42.17#ibcon#flushed, iclass 15, count 0 2006.260.07:34:42.17#ibcon#about to write, iclass 15, count 0 2006.260.07:34:42.17#ibcon#wrote, iclass 15, count 0 2006.260.07:34:42.17#ibcon#about to read 3, iclass 15, count 0 2006.260.07:34:42.19#ibcon#read 3, iclass 15, count 0 2006.260.07:34:42.19#ibcon#about to read 4, iclass 15, count 0 2006.260.07:34:42.19#ibcon#read 4, iclass 15, count 0 2006.260.07:34:42.19#ibcon#about to read 5, iclass 15, count 0 2006.260.07:34:42.19#ibcon#read 5, iclass 15, count 0 2006.260.07:34:42.19#ibcon#about to read 6, iclass 15, count 0 2006.260.07:34:42.19#ibcon#read 6, iclass 15, count 0 2006.260.07:34:42.19#ibcon#end of sib2, iclass 15, count 0 2006.260.07:34:42.19#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:34:42.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:34:42.19#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:34:42.19#ibcon#*before write, iclass 15, count 0 2006.260.07:34:42.19#ibcon#enter sib2, iclass 15, count 0 2006.260.07:34:42.19#ibcon#flushed, iclass 15, count 0 2006.260.07:34:42.19#ibcon#about to write, iclass 15, count 0 2006.260.07:34:42.19#ibcon#wrote, iclass 15, count 0 2006.260.07:34:42.19#ibcon#about to read 3, iclass 15, count 0 2006.260.07:34:42.23#ibcon#read 3, iclass 15, count 0 2006.260.07:34:42.23#ibcon#about to read 4, iclass 15, count 0 2006.260.07:34:42.23#ibcon#read 4, iclass 15, count 0 2006.260.07:34:42.23#ibcon#about to read 5, iclass 15, count 0 2006.260.07:34:42.23#ibcon#read 5, iclass 15, count 0 2006.260.07:34:42.23#ibcon#about to read 6, iclass 15, count 0 2006.260.07:34:42.23#ibcon#read 6, iclass 15, count 0 2006.260.07:34:42.23#ibcon#end of sib2, iclass 15, count 0 2006.260.07:34:42.23#ibcon#*after write, iclass 15, count 0 2006.260.07:34:42.23#ibcon#*before return 0, iclass 15, count 0 2006.260.07:34:42.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:42.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:34:42.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:34:42.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:34:42.23$vc4f8/vb=2,5 2006.260.07:34:42.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:34:42.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:34:42.23#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:42.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:42.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:42.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:42.29#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:34:42.29#ibcon#first serial, iclass 17, count 2 2006.260.07:34:42.29#ibcon#enter sib2, iclass 17, count 2 2006.260.07:34:42.29#ibcon#flushed, iclass 17, count 2 2006.260.07:34:42.29#ibcon#about to write, iclass 17, count 2 2006.260.07:34:42.29#ibcon#wrote, iclass 17, count 2 2006.260.07:34:42.29#ibcon#about to read 3, iclass 17, count 2 2006.260.07:34:42.31#ibcon#read 3, iclass 17, count 2 2006.260.07:34:42.31#ibcon#about to read 4, iclass 17, count 2 2006.260.07:34:42.31#ibcon#read 4, iclass 17, count 2 2006.260.07:34:42.31#ibcon#about to read 5, iclass 17, count 2 2006.260.07:34:42.31#ibcon#read 5, iclass 17, count 2 2006.260.07:34:42.31#ibcon#about to read 6, iclass 17, count 2 2006.260.07:34:42.31#ibcon#read 6, iclass 17, count 2 2006.260.07:34:42.31#ibcon#end of sib2, iclass 17, count 2 2006.260.07:34:42.31#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:34:42.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:34:42.31#ibcon#[27=AT02-05\r\n] 2006.260.07:34:42.31#ibcon#*before write, iclass 17, count 2 2006.260.07:34:42.31#ibcon#enter sib2, iclass 17, count 2 2006.260.07:34:42.31#ibcon#flushed, iclass 17, count 2 2006.260.07:34:42.31#ibcon#about to write, iclass 17, count 2 2006.260.07:34:42.31#ibcon#wrote, iclass 17, count 2 2006.260.07:34:42.31#ibcon#about to read 3, iclass 17, count 2 2006.260.07:34:42.34#ibcon#read 3, iclass 17, count 2 2006.260.07:34:42.34#ibcon#about to read 4, iclass 17, count 2 2006.260.07:34:42.34#ibcon#read 4, iclass 17, count 2 2006.260.07:34:42.34#ibcon#about to read 5, iclass 17, count 2 2006.260.07:34:42.34#ibcon#read 5, iclass 17, count 2 2006.260.07:34:42.34#ibcon#about to read 6, iclass 17, count 2 2006.260.07:34:42.34#ibcon#read 6, iclass 17, count 2 2006.260.07:34:42.34#ibcon#end of sib2, iclass 17, count 2 2006.260.07:34:42.34#ibcon#*after write, iclass 17, count 2 2006.260.07:34:42.34#ibcon#*before return 0, iclass 17, count 2 2006.260.07:34:42.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:42.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:34:42.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:34:42.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:42.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:42.46#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:42.46#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:42.46#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:34:42.46#ibcon#first serial, iclass 17, count 0 2006.260.07:34:42.46#ibcon#enter sib2, iclass 17, count 0 2006.260.07:34:42.46#ibcon#flushed, iclass 17, count 0 2006.260.07:34:42.46#ibcon#about to write, iclass 17, count 0 2006.260.07:34:42.46#ibcon#wrote, iclass 17, count 0 2006.260.07:34:42.46#ibcon#about to read 3, iclass 17, count 0 2006.260.07:34:42.48#ibcon#read 3, iclass 17, count 0 2006.260.07:34:42.48#ibcon#about to read 4, iclass 17, count 0 2006.260.07:34:42.48#ibcon#read 4, iclass 17, count 0 2006.260.07:34:42.48#ibcon#about to read 5, iclass 17, count 0 2006.260.07:34:42.48#ibcon#read 5, iclass 17, count 0 2006.260.07:34:42.48#ibcon#about to read 6, iclass 17, count 0 2006.260.07:34:42.48#ibcon#read 6, iclass 17, count 0 2006.260.07:34:42.48#ibcon#end of sib2, iclass 17, count 0 2006.260.07:34:42.48#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:34:42.48#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:34:42.48#ibcon#[27=USB\r\n] 2006.260.07:34:42.48#ibcon#*before write, iclass 17, count 0 2006.260.07:34:42.48#ibcon#enter sib2, iclass 17, count 0 2006.260.07:34:42.48#ibcon#flushed, iclass 17, count 0 2006.260.07:34:42.48#ibcon#about to write, iclass 17, count 0 2006.260.07:34:42.48#ibcon#wrote, iclass 17, count 0 2006.260.07:34:42.48#ibcon#about to read 3, iclass 17, count 0 2006.260.07:34:42.51#ibcon#read 3, iclass 17, count 0 2006.260.07:34:42.51#ibcon#about to read 4, iclass 17, count 0 2006.260.07:34:42.51#ibcon#read 4, iclass 17, count 0 2006.260.07:34:42.51#ibcon#about to read 5, iclass 17, count 0 2006.260.07:34:42.51#ibcon#read 5, iclass 17, count 0 2006.260.07:34:42.51#ibcon#about to read 6, iclass 17, count 0 2006.260.07:34:42.51#ibcon#read 6, iclass 17, count 0 2006.260.07:34:42.51#ibcon#end of sib2, iclass 17, count 0 2006.260.07:34:42.51#ibcon#*after write, iclass 17, count 0 2006.260.07:34:42.51#ibcon#*before return 0, iclass 17, count 0 2006.260.07:34:42.51#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:42.51#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:34:42.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:34:42.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:34:42.51$vc4f8/vblo=3,656.99 2006.260.07:34:42.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:34:42.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:34:42.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:42.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:42.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:42.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:42.51#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:34:42.51#ibcon#first serial, iclass 19, count 0 2006.260.07:34:42.51#ibcon#enter sib2, iclass 19, count 0 2006.260.07:34:42.51#ibcon#flushed, iclass 19, count 0 2006.260.07:34:42.51#ibcon#about to write, iclass 19, count 0 2006.260.07:34:42.51#ibcon#wrote, iclass 19, count 0 2006.260.07:34:42.51#ibcon#about to read 3, iclass 19, count 0 2006.260.07:34:42.53#ibcon#read 3, iclass 19, count 0 2006.260.07:34:42.53#ibcon#about to read 4, iclass 19, count 0 2006.260.07:34:42.53#ibcon#read 4, iclass 19, count 0 2006.260.07:34:42.53#ibcon#about to read 5, iclass 19, count 0 2006.260.07:34:42.53#ibcon#read 5, iclass 19, count 0 2006.260.07:34:42.53#ibcon#about to read 6, iclass 19, count 0 2006.260.07:34:42.53#ibcon#read 6, iclass 19, count 0 2006.260.07:34:42.53#ibcon#end of sib2, iclass 19, count 0 2006.260.07:34:42.53#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:34:42.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:34:42.53#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:34:42.53#ibcon#*before write, iclass 19, count 0 2006.260.07:34:42.53#ibcon#enter sib2, iclass 19, count 0 2006.260.07:34:42.53#ibcon#flushed, iclass 19, count 0 2006.260.07:34:42.53#ibcon#about to write, iclass 19, count 0 2006.260.07:34:42.53#ibcon#wrote, iclass 19, count 0 2006.260.07:34:42.53#ibcon#about to read 3, iclass 19, count 0 2006.260.07:34:42.57#ibcon#read 3, iclass 19, count 0 2006.260.07:34:42.57#ibcon#about to read 4, iclass 19, count 0 2006.260.07:34:42.57#ibcon#read 4, iclass 19, count 0 2006.260.07:34:42.57#ibcon#about to read 5, iclass 19, count 0 2006.260.07:34:42.57#ibcon#read 5, iclass 19, count 0 2006.260.07:34:42.57#ibcon#about to read 6, iclass 19, count 0 2006.260.07:34:42.57#ibcon#read 6, iclass 19, count 0 2006.260.07:34:42.57#ibcon#end of sib2, iclass 19, count 0 2006.260.07:34:42.57#ibcon#*after write, iclass 19, count 0 2006.260.07:34:42.57#ibcon#*before return 0, iclass 19, count 0 2006.260.07:34:42.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:42.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:34:42.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:34:42.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:34:42.57$vc4f8/vb=3,4 2006.260.07:34:42.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:34:42.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:34:42.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:42.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:42.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:42.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:42.63#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:34:42.63#ibcon#first serial, iclass 21, count 2 2006.260.07:34:42.63#ibcon#enter sib2, iclass 21, count 2 2006.260.07:34:42.63#ibcon#flushed, iclass 21, count 2 2006.260.07:34:42.63#ibcon#about to write, iclass 21, count 2 2006.260.07:34:42.63#ibcon#wrote, iclass 21, count 2 2006.260.07:34:42.63#ibcon#about to read 3, iclass 21, count 2 2006.260.07:34:42.65#ibcon#read 3, iclass 21, count 2 2006.260.07:34:42.65#ibcon#about to read 4, iclass 21, count 2 2006.260.07:34:42.65#ibcon#read 4, iclass 21, count 2 2006.260.07:34:42.65#ibcon#about to read 5, iclass 21, count 2 2006.260.07:34:42.65#ibcon#read 5, iclass 21, count 2 2006.260.07:34:42.65#ibcon#about to read 6, iclass 21, count 2 2006.260.07:34:42.65#ibcon#read 6, iclass 21, count 2 2006.260.07:34:42.65#ibcon#end of sib2, iclass 21, count 2 2006.260.07:34:42.65#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:34:42.65#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:34:42.65#ibcon#[27=AT03-04\r\n] 2006.260.07:34:42.65#ibcon#*before write, iclass 21, count 2 2006.260.07:34:42.65#ibcon#enter sib2, iclass 21, count 2 2006.260.07:34:42.65#ibcon#flushed, iclass 21, count 2 2006.260.07:34:42.65#ibcon#about to write, iclass 21, count 2 2006.260.07:34:42.65#ibcon#wrote, iclass 21, count 2 2006.260.07:34:42.65#ibcon#about to read 3, iclass 21, count 2 2006.260.07:34:42.68#ibcon#read 3, iclass 21, count 2 2006.260.07:34:42.68#ibcon#about to read 4, iclass 21, count 2 2006.260.07:34:42.68#ibcon#read 4, iclass 21, count 2 2006.260.07:34:42.68#ibcon#about to read 5, iclass 21, count 2 2006.260.07:34:42.68#ibcon#read 5, iclass 21, count 2 2006.260.07:34:42.68#ibcon#about to read 6, iclass 21, count 2 2006.260.07:34:42.68#ibcon#read 6, iclass 21, count 2 2006.260.07:34:42.68#ibcon#end of sib2, iclass 21, count 2 2006.260.07:34:42.68#ibcon#*after write, iclass 21, count 2 2006.260.07:34:42.68#ibcon#*before return 0, iclass 21, count 2 2006.260.07:34:42.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:42.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:34:42.68#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:34:42.68#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:42.68#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:42.80#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:42.80#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:42.80#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:34:42.80#ibcon#first serial, iclass 21, count 0 2006.260.07:34:42.80#ibcon#enter sib2, iclass 21, count 0 2006.260.07:34:42.80#ibcon#flushed, iclass 21, count 0 2006.260.07:34:42.80#ibcon#about to write, iclass 21, count 0 2006.260.07:34:42.80#ibcon#wrote, iclass 21, count 0 2006.260.07:34:42.80#ibcon#about to read 3, iclass 21, count 0 2006.260.07:34:42.82#ibcon#read 3, iclass 21, count 0 2006.260.07:34:42.82#ibcon#about to read 4, iclass 21, count 0 2006.260.07:34:42.82#ibcon#read 4, iclass 21, count 0 2006.260.07:34:42.82#ibcon#about to read 5, iclass 21, count 0 2006.260.07:34:42.82#ibcon#read 5, iclass 21, count 0 2006.260.07:34:42.82#ibcon#about to read 6, iclass 21, count 0 2006.260.07:34:42.82#ibcon#read 6, iclass 21, count 0 2006.260.07:34:42.82#ibcon#end of sib2, iclass 21, count 0 2006.260.07:34:42.82#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:34:42.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:34:42.82#ibcon#[27=USB\r\n] 2006.260.07:34:42.82#ibcon#*before write, iclass 21, count 0 2006.260.07:34:42.82#ibcon#enter sib2, iclass 21, count 0 2006.260.07:34:42.82#ibcon#flushed, iclass 21, count 0 2006.260.07:34:42.82#ibcon#about to write, iclass 21, count 0 2006.260.07:34:42.82#ibcon#wrote, iclass 21, count 0 2006.260.07:34:42.82#ibcon#about to read 3, iclass 21, count 0 2006.260.07:34:42.85#ibcon#read 3, iclass 21, count 0 2006.260.07:34:42.85#ibcon#about to read 4, iclass 21, count 0 2006.260.07:34:42.85#ibcon#read 4, iclass 21, count 0 2006.260.07:34:42.85#ibcon#about to read 5, iclass 21, count 0 2006.260.07:34:42.85#ibcon#read 5, iclass 21, count 0 2006.260.07:34:42.85#ibcon#about to read 6, iclass 21, count 0 2006.260.07:34:42.85#ibcon#read 6, iclass 21, count 0 2006.260.07:34:42.85#ibcon#end of sib2, iclass 21, count 0 2006.260.07:34:42.85#ibcon#*after write, iclass 21, count 0 2006.260.07:34:42.85#ibcon#*before return 0, iclass 21, count 0 2006.260.07:34:42.85#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:42.85#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:34:42.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:34:42.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:34:42.85$vc4f8/vblo=4,712.99 2006.260.07:34:42.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:34:42.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:34:42.85#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:42.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:42.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:42.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:42.85#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:34:42.85#ibcon#first serial, iclass 23, count 0 2006.260.07:34:42.85#ibcon#enter sib2, iclass 23, count 0 2006.260.07:34:42.85#ibcon#flushed, iclass 23, count 0 2006.260.07:34:42.85#ibcon#about to write, iclass 23, count 0 2006.260.07:34:42.85#ibcon#wrote, iclass 23, count 0 2006.260.07:34:42.85#ibcon#about to read 3, iclass 23, count 0 2006.260.07:34:42.87#ibcon#read 3, iclass 23, count 0 2006.260.07:34:42.87#ibcon#about to read 4, iclass 23, count 0 2006.260.07:34:42.87#ibcon#read 4, iclass 23, count 0 2006.260.07:34:42.87#ibcon#about to read 5, iclass 23, count 0 2006.260.07:34:42.87#ibcon#read 5, iclass 23, count 0 2006.260.07:34:42.87#ibcon#about to read 6, iclass 23, count 0 2006.260.07:34:42.87#ibcon#read 6, iclass 23, count 0 2006.260.07:34:42.87#ibcon#end of sib2, iclass 23, count 0 2006.260.07:34:42.87#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:34:42.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:34:42.87#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:34:42.87#ibcon#*before write, iclass 23, count 0 2006.260.07:34:42.87#ibcon#enter sib2, iclass 23, count 0 2006.260.07:34:42.87#ibcon#flushed, iclass 23, count 0 2006.260.07:34:42.87#ibcon#about to write, iclass 23, count 0 2006.260.07:34:42.87#ibcon#wrote, iclass 23, count 0 2006.260.07:34:42.87#ibcon#about to read 3, iclass 23, count 0 2006.260.07:34:42.91#ibcon#read 3, iclass 23, count 0 2006.260.07:34:42.91#ibcon#about to read 4, iclass 23, count 0 2006.260.07:34:42.91#ibcon#read 4, iclass 23, count 0 2006.260.07:34:42.91#ibcon#about to read 5, iclass 23, count 0 2006.260.07:34:42.91#ibcon#read 5, iclass 23, count 0 2006.260.07:34:42.91#ibcon#about to read 6, iclass 23, count 0 2006.260.07:34:42.91#ibcon#read 6, iclass 23, count 0 2006.260.07:34:42.91#ibcon#end of sib2, iclass 23, count 0 2006.260.07:34:42.91#ibcon#*after write, iclass 23, count 0 2006.260.07:34:42.91#ibcon#*before return 0, iclass 23, count 0 2006.260.07:34:42.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:42.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:34:42.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:34:42.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:34:42.91$vc4f8/vb=4,5 2006.260.07:34:42.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:34:42.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:34:42.91#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:42.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:42.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:42.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:42.97#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:34:42.97#ibcon#first serial, iclass 25, count 2 2006.260.07:34:42.97#ibcon#enter sib2, iclass 25, count 2 2006.260.07:34:42.97#ibcon#flushed, iclass 25, count 2 2006.260.07:34:42.97#ibcon#about to write, iclass 25, count 2 2006.260.07:34:42.97#ibcon#wrote, iclass 25, count 2 2006.260.07:34:42.97#ibcon#about to read 3, iclass 25, count 2 2006.260.07:34:42.99#ibcon#read 3, iclass 25, count 2 2006.260.07:34:42.99#ibcon#about to read 4, iclass 25, count 2 2006.260.07:34:42.99#ibcon#read 4, iclass 25, count 2 2006.260.07:34:42.99#ibcon#about to read 5, iclass 25, count 2 2006.260.07:34:42.99#ibcon#read 5, iclass 25, count 2 2006.260.07:34:42.99#ibcon#about to read 6, iclass 25, count 2 2006.260.07:34:42.99#ibcon#read 6, iclass 25, count 2 2006.260.07:34:42.99#ibcon#end of sib2, iclass 25, count 2 2006.260.07:34:42.99#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:34:42.99#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:34:42.99#ibcon#[27=AT04-05\r\n] 2006.260.07:34:42.99#ibcon#*before write, iclass 25, count 2 2006.260.07:34:42.99#ibcon#enter sib2, iclass 25, count 2 2006.260.07:34:42.99#ibcon#flushed, iclass 25, count 2 2006.260.07:34:42.99#ibcon#about to write, iclass 25, count 2 2006.260.07:34:42.99#ibcon#wrote, iclass 25, count 2 2006.260.07:34:42.99#ibcon#about to read 3, iclass 25, count 2 2006.260.07:34:43.01#abcon#<5=/04 2.9 7.0 23.15 861010.3\r\n> 2006.260.07:34:43.02#ibcon#read 3, iclass 25, count 2 2006.260.07:34:43.02#ibcon#about to read 4, iclass 25, count 2 2006.260.07:34:43.02#ibcon#read 4, iclass 25, count 2 2006.260.07:34:43.02#ibcon#about to read 5, iclass 25, count 2 2006.260.07:34:43.02#ibcon#read 5, iclass 25, count 2 2006.260.07:34:43.02#ibcon#about to read 6, iclass 25, count 2 2006.260.07:34:43.02#ibcon#read 6, iclass 25, count 2 2006.260.07:34:43.02#ibcon#end of sib2, iclass 25, count 2 2006.260.07:34:43.02#ibcon#*after write, iclass 25, count 2 2006.260.07:34:43.02#ibcon#*before return 0, iclass 25, count 2 2006.260.07:34:43.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:43.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:34:43.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:34:43.02#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:43.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:43.03#abcon#{5=INTERFACE CLEAR} 2006.260.07:34:43.09#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:34:43.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:43.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:43.14#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:34:43.14#ibcon#first serial, iclass 25, count 0 2006.260.07:34:43.14#ibcon#enter sib2, iclass 25, count 0 2006.260.07:34:43.14#ibcon#flushed, iclass 25, count 0 2006.260.07:34:43.14#ibcon#about to write, iclass 25, count 0 2006.260.07:34:43.14#ibcon#wrote, iclass 25, count 0 2006.260.07:34:43.14#ibcon#about to read 3, iclass 25, count 0 2006.260.07:34:43.16#ibcon#read 3, iclass 25, count 0 2006.260.07:34:43.16#ibcon#about to read 4, iclass 25, count 0 2006.260.07:34:43.16#ibcon#read 4, iclass 25, count 0 2006.260.07:34:43.16#ibcon#about to read 5, iclass 25, count 0 2006.260.07:34:43.16#ibcon#read 5, iclass 25, count 0 2006.260.07:34:43.16#ibcon#about to read 6, iclass 25, count 0 2006.260.07:34:43.16#ibcon#read 6, iclass 25, count 0 2006.260.07:34:43.16#ibcon#end of sib2, iclass 25, count 0 2006.260.07:34:43.16#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:34:43.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:34:43.16#ibcon#[27=USB\r\n] 2006.260.07:34:43.16#ibcon#*before write, iclass 25, count 0 2006.260.07:34:43.16#ibcon#enter sib2, iclass 25, count 0 2006.260.07:34:43.16#ibcon#flushed, iclass 25, count 0 2006.260.07:34:43.16#ibcon#about to write, iclass 25, count 0 2006.260.07:34:43.16#ibcon#wrote, iclass 25, count 0 2006.260.07:34:43.16#ibcon#about to read 3, iclass 25, count 0 2006.260.07:34:43.19#ibcon#read 3, iclass 25, count 0 2006.260.07:34:43.19#ibcon#about to read 4, iclass 25, count 0 2006.260.07:34:43.19#ibcon#read 4, iclass 25, count 0 2006.260.07:34:43.19#ibcon#about to read 5, iclass 25, count 0 2006.260.07:34:43.19#ibcon#read 5, iclass 25, count 0 2006.260.07:34:43.19#ibcon#about to read 6, iclass 25, count 0 2006.260.07:34:43.19#ibcon#read 6, iclass 25, count 0 2006.260.07:34:43.19#ibcon#end of sib2, iclass 25, count 0 2006.260.07:34:43.19#ibcon#*after write, iclass 25, count 0 2006.260.07:34:43.19#ibcon#*before return 0, iclass 25, count 0 2006.260.07:34:43.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:43.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:34:43.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:34:43.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:34:43.19$vc4f8/vblo=5,744.99 2006.260.07:34:43.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:34:43.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:34:43.19#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:43.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:43.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:43.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:43.19#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:34:43.19#ibcon#first serial, iclass 31, count 0 2006.260.07:34:43.19#ibcon#enter sib2, iclass 31, count 0 2006.260.07:34:43.19#ibcon#flushed, iclass 31, count 0 2006.260.07:34:43.19#ibcon#about to write, iclass 31, count 0 2006.260.07:34:43.19#ibcon#wrote, iclass 31, count 0 2006.260.07:34:43.19#ibcon#about to read 3, iclass 31, count 0 2006.260.07:34:43.21#ibcon#read 3, iclass 31, count 0 2006.260.07:34:43.21#ibcon#about to read 4, iclass 31, count 0 2006.260.07:34:43.21#ibcon#read 4, iclass 31, count 0 2006.260.07:34:43.21#ibcon#about to read 5, iclass 31, count 0 2006.260.07:34:43.21#ibcon#read 5, iclass 31, count 0 2006.260.07:34:43.21#ibcon#about to read 6, iclass 31, count 0 2006.260.07:34:43.21#ibcon#read 6, iclass 31, count 0 2006.260.07:34:43.21#ibcon#end of sib2, iclass 31, count 0 2006.260.07:34:43.21#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:34:43.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:34:43.21#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:34:43.21#ibcon#*before write, iclass 31, count 0 2006.260.07:34:43.21#ibcon#enter sib2, iclass 31, count 0 2006.260.07:34:43.21#ibcon#flushed, iclass 31, count 0 2006.260.07:34:43.21#ibcon#about to write, iclass 31, count 0 2006.260.07:34:43.21#ibcon#wrote, iclass 31, count 0 2006.260.07:34:43.21#ibcon#about to read 3, iclass 31, count 0 2006.260.07:34:43.25#ibcon#read 3, iclass 31, count 0 2006.260.07:34:43.25#ibcon#about to read 4, iclass 31, count 0 2006.260.07:34:43.25#ibcon#read 4, iclass 31, count 0 2006.260.07:34:43.25#ibcon#about to read 5, iclass 31, count 0 2006.260.07:34:43.25#ibcon#read 5, iclass 31, count 0 2006.260.07:34:43.25#ibcon#about to read 6, iclass 31, count 0 2006.260.07:34:43.25#ibcon#read 6, iclass 31, count 0 2006.260.07:34:43.25#ibcon#end of sib2, iclass 31, count 0 2006.260.07:34:43.25#ibcon#*after write, iclass 31, count 0 2006.260.07:34:43.25#ibcon#*before return 0, iclass 31, count 0 2006.260.07:34:43.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:43.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:34:43.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:34:43.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:34:43.25$vc4f8/vb=5,4 2006.260.07:34:43.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:34:43.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:34:43.25#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:43.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:43.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:43.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:43.31#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:34:43.31#ibcon#first serial, iclass 33, count 2 2006.260.07:34:43.31#ibcon#enter sib2, iclass 33, count 2 2006.260.07:34:43.31#ibcon#flushed, iclass 33, count 2 2006.260.07:34:43.31#ibcon#about to write, iclass 33, count 2 2006.260.07:34:43.31#ibcon#wrote, iclass 33, count 2 2006.260.07:34:43.31#ibcon#about to read 3, iclass 33, count 2 2006.260.07:34:43.33#ibcon#read 3, iclass 33, count 2 2006.260.07:34:43.33#ibcon#about to read 4, iclass 33, count 2 2006.260.07:34:43.33#ibcon#read 4, iclass 33, count 2 2006.260.07:34:43.33#ibcon#about to read 5, iclass 33, count 2 2006.260.07:34:43.33#ibcon#read 5, iclass 33, count 2 2006.260.07:34:43.33#ibcon#about to read 6, iclass 33, count 2 2006.260.07:34:43.33#ibcon#read 6, iclass 33, count 2 2006.260.07:34:43.33#ibcon#end of sib2, iclass 33, count 2 2006.260.07:34:43.33#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:34:43.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:34:43.33#ibcon#[27=AT05-04\r\n] 2006.260.07:34:43.33#ibcon#*before write, iclass 33, count 2 2006.260.07:34:43.33#ibcon#enter sib2, iclass 33, count 2 2006.260.07:34:43.33#ibcon#flushed, iclass 33, count 2 2006.260.07:34:43.33#ibcon#about to write, iclass 33, count 2 2006.260.07:34:43.33#ibcon#wrote, iclass 33, count 2 2006.260.07:34:43.33#ibcon#about to read 3, iclass 33, count 2 2006.260.07:34:43.36#ibcon#read 3, iclass 33, count 2 2006.260.07:34:43.36#ibcon#about to read 4, iclass 33, count 2 2006.260.07:34:43.36#ibcon#read 4, iclass 33, count 2 2006.260.07:34:43.36#ibcon#about to read 5, iclass 33, count 2 2006.260.07:34:43.36#ibcon#read 5, iclass 33, count 2 2006.260.07:34:43.36#ibcon#about to read 6, iclass 33, count 2 2006.260.07:34:43.36#ibcon#read 6, iclass 33, count 2 2006.260.07:34:43.36#ibcon#end of sib2, iclass 33, count 2 2006.260.07:34:43.36#ibcon#*after write, iclass 33, count 2 2006.260.07:34:43.36#ibcon#*before return 0, iclass 33, count 2 2006.260.07:34:43.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:43.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:34:43.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:34:43.36#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:43.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:43.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:43.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:43.48#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:34:43.48#ibcon#first serial, iclass 33, count 0 2006.260.07:34:43.48#ibcon#enter sib2, iclass 33, count 0 2006.260.07:34:43.48#ibcon#flushed, iclass 33, count 0 2006.260.07:34:43.48#ibcon#about to write, iclass 33, count 0 2006.260.07:34:43.48#ibcon#wrote, iclass 33, count 0 2006.260.07:34:43.48#ibcon#about to read 3, iclass 33, count 0 2006.260.07:34:43.50#ibcon#read 3, iclass 33, count 0 2006.260.07:34:43.50#ibcon#about to read 4, iclass 33, count 0 2006.260.07:34:43.50#ibcon#read 4, iclass 33, count 0 2006.260.07:34:43.50#ibcon#about to read 5, iclass 33, count 0 2006.260.07:34:43.50#ibcon#read 5, iclass 33, count 0 2006.260.07:34:43.50#ibcon#about to read 6, iclass 33, count 0 2006.260.07:34:43.50#ibcon#read 6, iclass 33, count 0 2006.260.07:34:43.50#ibcon#end of sib2, iclass 33, count 0 2006.260.07:34:43.50#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:34:43.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:34:43.50#ibcon#[27=USB\r\n] 2006.260.07:34:43.50#ibcon#*before write, iclass 33, count 0 2006.260.07:34:43.50#ibcon#enter sib2, iclass 33, count 0 2006.260.07:34:43.50#ibcon#flushed, iclass 33, count 0 2006.260.07:34:43.50#ibcon#about to write, iclass 33, count 0 2006.260.07:34:43.50#ibcon#wrote, iclass 33, count 0 2006.260.07:34:43.50#ibcon#about to read 3, iclass 33, count 0 2006.260.07:34:43.53#ibcon#read 3, iclass 33, count 0 2006.260.07:34:43.53#ibcon#about to read 4, iclass 33, count 0 2006.260.07:34:43.53#ibcon#read 4, iclass 33, count 0 2006.260.07:34:43.53#ibcon#about to read 5, iclass 33, count 0 2006.260.07:34:43.53#ibcon#read 5, iclass 33, count 0 2006.260.07:34:43.53#ibcon#about to read 6, iclass 33, count 0 2006.260.07:34:43.53#ibcon#read 6, iclass 33, count 0 2006.260.07:34:43.53#ibcon#end of sib2, iclass 33, count 0 2006.260.07:34:43.53#ibcon#*after write, iclass 33, count 0 2006.260.07:34:43.53#ibcon#*before return 0, iclass 33, count 0 2006.260.07:34:43.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:43.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:34:43.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:34:43.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:34:43.53$vc4f8/vblo=6,752.99 2006.260.07:34:43.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:34:43.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:34:43.53#ibcon#ireg 17 cls_cnt 0 2006.260.07:34:43.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:43.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:43.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:43.53#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:34:43.53#ibcon#first serial, iclass 35, count 0 2006.260.07:34:43.53#ibcon#enter sib2, iclass 35, count 0 2006.260.07:34:43.53#ibcon#flushed, iclass 35, count 0 2006.260.07:34:43.53#ibcon#about to write, iclass 35, count 0 2006.260.07:34:43.53#ibcon#wrote, iclass 35, count 0 2006.260.07:34:43.53#ibcon#about to read 3, iclass 35, count 0 2006.260.07:34:43.55#ibcon#read 3, iclass 35, count 0 2006.260.07:34:43.55#ibcon#about to read 4, iclass 35, count 0 2006.260.07:34:43.55#ibcon#read 4, iclass 35, count 0 2006.260.07:34:43.55#ibcon#about to read 5, iclass 35, count 0 2006.260.07:34:43.55#ibcon#read 5, iclass 35, count 0 2006.260.07:34:43.55#ibcon#about to read 6, iclass 35, count 0 2006.260.07:34:43.55#ibcon#read 6, iclass 35, count 0 2006.260.07:34:43.55#ibcon#end of sib2, iclass 35, count 0 2006.260.07:34:43.55#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:34:43.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:34:43.55#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:34:43.55#ibcon#*before write, iclass 35, count 0 2006.260.07:34:43.55#ibcon#enter sib2, iclass 35, count 0 2006.260.07:34:43.55#ibcon#flushed, iclass 35, count 0 2006.260.07:34:43.55#ibcon#about to write, iclass 35, count 0 2006.260.07:34:43.55#ibcon#wrote, iclass 35, count 0 2006.260.07:34:43.55#ibcon#about to read 3, iclass 35, count 0 2006.260.07:34:43.59#ibcon#read 3, iclass 35, count 0 2006.260.07:34:43.59#ibcon#about to read 4, iclass 35, count 0 2006.260.07:34:43.59#ibcon#read 4, iclass 35, count 0 2006.260.07:34:43.59#ibcon#about to read 5, iclass 35, count 0 2006.260.07:34:43.59#ibcon#read 5, iclass 35, count 0 2006.260.07:34:43.59#ibcon#about to read 6, iclass 35, count 0 2006.260.07:34:43.59#ibcon#read 6, iclass 35, count 0 2006.260.07:34:43.59#ibcon#end of sib2, iclass 35, count 0 2006.260.07:34:43.59#ibcon#*after write, iclass 35, count 0 2006.260.07:34:43.59#ibcon#*before return 0, iclass 35, count 0 2006.260.07:34:43.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:43.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:34:43.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:34:43.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:34:43.59$vc4f8/vb=6,4 2006.260.07:34:43.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:34:43.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:34:43.59#ibcon#ireg 11 cls_cnt 2 2006.260.07:34:43.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:43.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:43.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:43.65#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:34:43.65#ibcon#first serial, iclass 37, count 2 2006.260.07:34:43.65#ibcon#enter sib2, iclass 37, count 2 2006.260.07:34:43.65#ibcon#flushed, iclass 37, count 2 2006.260.07:34:43.65#ibcon#about to write, iclass 37, count 2 2006.260.07:34:43.65#ibcon#wrote, iclass 37, count 2 2006.260.07:34:43.65#ibcon#about to read 3, iclass 37, count 2 2006.260.07:34:43.67#ibcon#read 3, iclass 37, count 2 2006.260.07:34:43.67#ibcon#about to read 4, iclass 37, count 2 2006.260.07:34:43.67#ibcon#read 4, iclass 37, count 2 2006.260.07:34:43.67#ibcon#about to read 5, iclass 37, count 2 2006.260.07:34:43.67#ibcon#read 5, iclass 37, count 2 2006.260.07:34:43.67#ibcon#about to read 6, iclass 37, count 2 2006.260.07:34:43.67#ibcon#read 6, iclass 37, count 2 2006.260.07:34:43.67#ibcon#end of sib2, iclass 37, count 2 2006.260.07:34:43.67#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:34:43.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:34:43.67#ibcon#[27=AT06-04\r\n] 2006.260.07:34:43.67#ibcon#*before write, iclass 37, count 2 2006.260.07:34:43.67#ibcon#enter sib2, iclass 37, count 2 2006.260.07:34:43.67#ibcon#flushed, iclass 37, count 2 2006.260.07:34:43.67#ibcon#about to write, iclass 37, count 2 2006.260.07:34:43.67#ibcon#wrote, iclass 37, count 2 2006.260.07:34:43.67#ibcon#about to read 3, iclass 37, count 2 2006.260.07:34:43.70#ibcon#read 3, iclass 37, count 2 2006.260.07:34:43.70#ibcon#about to read 4, iclass 37, count 2 2006.260.07:34:43.70#ibcon#read 4, iclass 37, count 2 2006.260.07:34:43.70#ibcon#about to read 5, iclass 37, count 2 2006.260.07:34:43.70#ibcon#read 5, iclass 37, count 2 2006.260.07:34:43.70#ibcon#about to read 6, iclass 37, count 2 2006.260.07:34:43.70#ibcon#read 6, iclass 37, count 2 2006.260.07:34:43.70#ibcon#end of sib2, iclass 37, count 2 2006.260.07:34:43.70#ibcon#*after write, iclass 37, count 2 2006.260.07:34:43.70#ibcon#*before return 0, iclass 37, count 2 2006.260.07:34:43.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:43.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:34:43.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:34:43.70#ibcon#ireg 7 cls_cnt 0 2006.260.07:34:43.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:43.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:43.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:43.82#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:34:43.82#ibcon#first serial, iclass 37, count 0 2006.260.07:34:43.82#ibcon#enter sib2, iclass 37, count 0 2006.260.07:34:43.82#ibcon#flushed, iclass 37, count 0 2006.260.07:34:43.82#ibcon#about to write, iclass 37, count 0 2006.260.07:34:43.82#ibcon#wrote, iclass 37, count 0 2006.260.07:34:43.82#ibcon#about to read 3, iclass 37, count 0 2006.260.07:34:43.84#ibcon#read 3, iclass 37, count 0 2006.260.07:34:43.84#ibcon#about to read 4, iclass 37, count 0 2006.260.07:34:43.84#ibcon#read 4, iclass 37, count 0 2006.260.07:34:43.84#ibcon#about to read 5, iclass 37, count 0 2006.260.07:34:43.84#ibcon#read 5, iclass 37, count 0 2006.260.07:34:43.84#ibcon#about to read 6, iclass 37, count 0 2006.260.07:34:43.84#ibcon#read 6, iclass 37, count 0 2006.260.07:34:43.84#ibcon#end of sib2, iclass 37, count 0 2006.260.07:34:43.84#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:34:43.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:34:43.84#ibcon#[27=USB\r\n] 2006.260.07:34:43.84#ibcon#*before write, iclass 37, count 0 2006.260.07:34:43.84#ibcon#enter sib2, iclass 37, count 0 2006.260.07:34:43.84#ibcon#flushed, iclass 37, count 0 2006.260.07:34:43.84#ibcon#about to write, iclass 37, count 0 2006.260.07:34:43.84#ibcon#wrote, iclass 37, count 0 2006.260.07:34:43.84#ibcon#about to read 3, iclass 37, count 0 2006.260.07:34:43.87#ibcon#read 3, iclass 37, count 0 2006.260.07:34:43.87#ibcon#about to read 4, iclass 37, count 0 2006.260.07:34:43.87#ibcon#read 4, iclass 37, count 0 2006.260.07:34:43.87#ibcon#about to read 5, iclass 37, count 0 2006.260.07:34:43.87#ibcon#read 5, iclass 37, count 0 2006.260.07:34:43.87#ibcon#about to read 6, iclass 37, count 0 2006.260.07:34:43.87#ibcon#read 6, iclass 37, count 0 2006.260.07:34:43.87#ibcon#end of sib2, iclass 37, count 0 2006.260.07:34:43.87#ibcon#*after write, iclass 37, count 0 2006.260.07:34:43.87#ibcon#*before return 0, iclass 37, count 0 2006.260.07:34:43.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:43.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:34:43.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:34:43.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:34:43.87$vc4f8/vabw=wide 2006.260.07:34:43.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:34:43.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:34:43.87#ibcon#ireg 8 cls_cnt 0 2006.260.07:34:43.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:43.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:43.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:43.87#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:34:43.87#ibcon#first serial, iclass 39, count 0 2006.260.07:34:43.87#ibcon#enter sib2, iclass 39, count 0 2006.260.07:34:43.87#ibcon#flushed, iclass 39, count 0 2006.260.07:34:43.87#ibcon#about to write, iclass 39, count 0 2006.260.07:34:43.87#ibcon#wrote, iclass 39, count 0 2006.260.07:34:43.87#ibcon#about to read 3, iclass 39, count 0 2006.260.07:34:43.89#ibcon#read 3, iclass 39, count 0 2006.260.07:34:43.89#ibcon#about to read 4, iclass 39, count 0 2006.260.07:34:43.89#ibcon#read 4, iclass 39, count 0 2006.260.07:34:43.89#ibcon#about to read 5, iclass 39, count 0 2006.260.07:34:43.89#ibcon#read 5, iclass 39, count 0 2006.260.07:34:43.89#ibcon#about to read 6, iclass 39, count 0 2006.260.07:34:43.89#ibcon#read 6, iclass 39, count 0 2006.260.07:34:43.89#ibcon#end of sib2, iclass 39, count 0 2006.260.07:34:43.89#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:34:43.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:34:43.89#ibcon#[25=BW32\r\n] 2006.260.07:34:43.89#ibcon#*before write, iclass 39, count 0 2006.260.07:34:43.89#ibcon#enter sib2, iclass 39, count 0 2006.260.07:34:43.89#ibcon#flushed, iclass 39, count 0 2006.260.07:34:43.89#ibcon#about to write, iclass 39, count 0 2006.260.07:34:43.89#ibcon#wrote, iclass 39, count 0 2006.260.07:34:43.89#ibcon#about to read 3, iclass 39, count 0 2006.260.07:34:43.92#ibcon#read 3, iclass 39, count 0 2006.260.07:34:43.92#ibcon#about to read 4, iclass 39, count 0 2006.260.07:34:43.92#ibcon#read 4, iclass 39, count 0 2006.260.07:34:43.92#ibcon#about to read 5, iclass 39, count 0 2006.260.07:34:43.92#ibcon#read 5, iclass 39, count 0 2006.260.07:34:43.92#ibcon#about to read 6, iclass 39, count 0 2006.260.07:34:43.92#ibcon#read 6, iclass 39, count 0 2006.260.07:34:43.92#ibcon#end of sib2, iclass 39, count 0 2006.260.07:34:43.92#ibcon#*after write, iclass 39, count 0 2006.260.07:34:43.92#ibcon#*before return 0, iclass 39, count 0 2006.260.07:34:43.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:43.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:34:43.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:34:43.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:34:43.92$vc4f8/vbbw=wide 2006.260.07:34:43.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:34:43.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:34:43.92#ibcon#ireg 8 cls_cnt 0 2006.260.07:34:43.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:34:43.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:34:43.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:34:43.99#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:34:43.99#ibcon#first serial, iclass 3, count 0 2006.260.07:34:43.99#ibcon#enter sib2, iclass 3, count 0 2006.260.07:34:43.99#ibcon#flushed, iclass 3, count 0 2006.260.07:34:43.99#ibcon#about to write, iclass 3, count 0 2006.260.07:34:43.99#ibcon#wrote, iclass 3, count 0 2006.260.07:34:43.99#ibcon#about to read 3, iclass 3, count 0 2006.260.07:34:44.01#ibcon#read 3, iclass 3, count 0 2006.260.07:34:44.01#ibcon#about to read 4, iclass 3, count 0 2006.260.07:34:44.01#ibcon#read 4, iclass 3, count 0 2006.260.07:34:44.01#ibcon#about to read 5, iclass 3, count 0 2006.260.07:34:44.01#ibcon#read 5, iclass 3, count 0 2006.260.07:34:44.01#ibcon#about to read 6, iclass 3, count 0 2006.260.07:34:44.01#ibcon#read 6, iclass 3, count 0 2006.260.07:34:44.01#ibcon#end of sib2, iclass 3, count 0 2006.260.07:34:44.01#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:34:44.01#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:34:44.01#ibcon#[27=BW32\r\n] 2006.260.07:34:44.01#ibcon#*before write, iclass 3, count 0 2006.260.07:34:44.01#ibcon#enter sib2, iclass 3, count 0 2006.260.07:34:44.01#ibcon#flushed, iclass 3, count 0 2006.260.07:34:44.01#ibcon#about to write, iclass 3, count 0 2006.260.07:34:44.01#ibcon#wrote, iclass 3, count 0 2006.260.07:34:44.01#ibcon#about to read 3, iclass 3, count 0 2006.260.07:34:44.04#ibcon#read 3, iclass 3, count 0 2006.260.07:34:44.04#ibcon#about to read 4, iclass 3, count 0 2006.260.07:34:44.04#ibcon#read 4, iclass 3, count 0 2006.260.07:34:44.04#ibcon#about to read 5, iclass 3, count 0 2006.260.07:34:44.04#ibcon#read 5, iclass 3, count 0 2006.260.07:34:44.04#ibcon#about to read 6, iclass 3, count 0 2006.260.07:34:44.04#ibcon#read 6, iclass 3, count 0 2006.260.07:34:44.04#ibcon#end of sib2, iclass 3, count 0 2006.260.07:34:44.04#ibcon#*after write, iclass 3, count 0 2006.260.07:34:44.04#ibcon#*before return 0, iclass 3, count 0 2006.260.07:34:44.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:34:44.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:34:44.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:34:44.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:34:44.04$4f8m12a/ifd4f 2006.260.07:34:44.04$ifd4f/lo= 2006.260.07:34:44.04$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:34:44.04$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:34:44.04$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:34:44.04$ifd4f/patch= 2006.260.07:34:44.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:34:44.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:34:44.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:34:44.04$4f8m12a/"form=m,16.000,1:2 2006.260.07:34:44.04$4f8m12a/"tpicd 2006.260.07:34:44.04$4f8m12a/echo=off 2006.260.07:34:44.04$4f8m12a/xlog=off 2006.260.07:34:44.04:!2006.260.07:35:10 2006.260.07:34:52.13#trakl#Source acquired 2006.260.07:34:52.13#flagr#flagr/antenna,acquired 2006.260.07:35:10.00:preob 2006.260.07:35:11.13/onsource/TRACKING 2006.260.07:35:11.13:!2006.260.07:35:20 2006.260.07:35:20.00:data_valid=on 2006.260.07:35:20.00:midob 2006.260.07:35:20.13/onsource/TRACKING 2006.260.07:35:20.13/wx/23.14,1010.4,86 2006.260.07:35:20.20/cable/+6.4576E-03 2006.260.07:35:21.29/va/01,08,usb,yes,32,34 2006.260.07:35:21.29/va/02,07,usb,yes,32,34 2006.260.07:35:21.29/va/03,08,usb,yes,24,25 2006.260.07:35:21.29/va/04,07,usb,yes,33,36 2006.260.07:35:21.29/va/05,07,usb,yes,37,39 2006.260.07:35:21.29/va/06,06,usb,yes,36,36 2006.260.07:35:21.29/va/07,06,usb,yes,36,36 2006.260.07:35:21.29/va/08,06,usb,yes,39,38 2006.260.07:35:21.52/valo/01,532.99,yes,locked 2006.260.07:35:21.52/valo/02,572.99,yes,locked 2006.260.07:35:21.52/valo/03,672.99,yes,locked 2006.260.07:35:21.52/valo/04,832.99,yes,locked 2006.260.07:35:21.52/valo/05,652.99,yes,locked 2006.260.07:35:21.52/valo/06,772.99,yes,locked 2006.260.07:35:21.52/valo/07,832.99,yes,locked 2006.260.07:35:21.52/valo/08,852.99,yes,locked 2006.260.07:35:22.61/vb/01,04,usb,yes,31,29 2006.260.07:35:22.61/vb/02,05,usb,yes,29,30 2006.260.07:35:22.61/vb/03,04,usb,yes,29,33 2006.260.07:35:22.61/vb/04,05,usb,yes,26,26 2006.260.07:35:22.61/vb/05,04,usb,yes,28,32 2006.260.07:35:22.61/vb/06,04,usb,yes,29,32 2006.260.07:35:22.61/vb/07,04,usb,yes,31,31 2006.260.07:35:22.61/vb/08,04,usb,yes,29,32 2006.260.07:35:22.84/vblo/01,632.99,yes,locked 2006.260.07:35:22.84/vblo/02,640.99,yes,locked 2006.260.07:35:22.84/vblo/03,656.99,yes,locked 2006.260.07:35:22.84/vblo/04,712.99,yes,locked 2006.260.07:35:22.84/vblo/05,744.99,yes,locked 2006.260.07:35:22.84/vblo/06,752.99,yes,locked 2006.260.07:35:22.84/vblo/07,734.99,yes,locked 2006.260.07:35:22.84/vblo/08,744.99,yes,locked 2006.260.07:35:22.99/vabw/8 2006.260.07:35:23.14/vbbw/8 2006.260.07:35:23.23/xfe/off,on,15.2 2006.260.07:35:23.61/ifatt/23,28,28,28 2006.260.07:35:24.08/fmout-gps/S +4.50E-07 2006.260.07:35:24.12:!2006.260.07:36:20 2006.260.07:36:20.01:data_valid=off 2006.260.07:36:20.01:postob 2006.260.07:36:20.15/cable/+6.4565E-03 2006.260.07:36:20.15/wx/23.13,1010.3,86 2006.260.07:36:21.08/fmout-gps/S +4.51E-07 2006.260.07:36:21.08:scan_name=260-0737,k06260,60 2006.260.07:36:21.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.260.07:36:21.13#flagr#flagr/antenna,new-source 2006.260.07:36:22.13:checkk5 2006.260.07:36:22.55/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:36:22.94/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:36:23.37/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:36:23.77/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:36:24.17/chk_obsdata//k5ts1/T2600735??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:36:24.62/chk_obsdata//k5ts2/T2600735??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:36:25.11/chk_obsdata//k5ts3/T2600735??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:36:25.53/chk_obsdata//k5ts4/T2600735??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:36:26.30/k5log//k5ts1_log_newline 2006.260.07:36:27.06/k5log//k5ts2_log_newline 2006.260.07:36:27.84/k5log//k5ts3_log_newline 2006.260.07:36:28.57/k5log//k5ts4_log_newline 2006.260.07:36:28.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:36:28.59:4f8m12a=1 2006.260.07:36:28.59$4f8m12a/echo=on 2006.260.07:36:28.59$4f8m12a/pcalon 2006.260.07:36:28.59$pcalon/"no phase cal control is implemented here 2006.260.07:36:28.59$4f8m12a/"tpicd=stop 2006.260.07:36:28.59$4f8m12a/vc4f8 2006.260.07:36:28.59$vc4f8/valo=1,532.99 2006.260.07:36:28.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:36:28.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:36:28.59#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:28.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:28.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:28.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:28.59#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:36:28.59#ibcon#first serial, iclass 12, count 0 2006.260.07:36:28.59#ibcon#enter sib2, iclass 12, count 0 2006.260.07:36:28.59#ibcon#flushed, iclass 12, count 0 2006.260.07:36:28.59#ibcon#about to write, iclass 12, count 0 2006.260.07:36:28.59#ibcon#wrote, iclass 12, count 0 2006.260.07:36:28.59#ibcon#about to read 3, iclass 12, count 0 2006.260.07:36:28.64#ibcon#read 3, iclass 12, count 0 2006.260.07:36:28.64#ibcon#about to read 4, iclass 12, count 0 2006.260.07:36:28.64#ibcon#read 4, iclass 12, count 0 2006.260.07:36:28.64#ibcon#about to read 5, iclass 12, count 0 2006.260.07:36:28.64#ibcon#read 5, iclass 12, count 0 2006.260.07:36:28.64#ibcon#about to read 6, iclass 12, count 0 2006.260.07:36:28.64#ibcon#read 6, iclass 12, count 0 2006.260.07:36:28.64#ibcon#end of sib2, iclass 12, count 0 2006.260.07:36:28.64#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:36:28.64#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:36:28.64#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:36:28.64#ibcon#*before write, iclass 12, count 0 2006.260.07:36:28.64#ibcon#enter sib2, iclass 12, count 0 2006.260.07:36:28.64#ibcon#flushed, iclass 12, count 0 2006.260.07:36:28.64#ibcon#about to write, iclass 12, count 0 2006.260.07:36:28.64#ibcon#wrote, iclass 12, count 0 2006.260.07:36:28.64#ibcon#about to read 3, iclass 12, count 0 2006.260.07:36:28.69#ibcon#read 3, iclass 12, count 0 2006.260.07:36:28.69#ibcon#about to read 4, iclass 12, count 0 2006.260.07:36:28.69#ibcon#read 4, iclass 12, count 0 2006.260.07:36:28.69#ibcon#about to read 5, iclass 12, count 0 2006.260.07:36:28.69#ibcon#read 5, iclass 12, count 0 2006.260.07:36:28.69#ibcon#about to read 6, iclass 12, count 0 2006.260.07:36:28.69#ibcon#read 6, iclass 12, count 0 2006.260.07:36:28.69#ibcon#end of sib2, iclass 12, count 0 2006.260.07:36:28.69#ibcon#*after write, iclass 12, count 0 2006.260.07:36:28.69#ibcon#*before return 0, iclass 12, count 0 2006.260.07:36:28.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:28.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:28.69#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:36:28.69#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:36:28.69$vc4f8/va=1,8 2006.260.07:36:28.69#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:36:28.69#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:36:28.69#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:28.69#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:28.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:28.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:28.69#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:36:28.69#ibcon#first serial, iclass 14, count 2 2006.260.07:36:28.69#ibcon#enter sib2, iclass 14, count 2 2006.260.07:36:28.69#ibcon#flushed, iclass 14, count 2 2006.260.07:36:28.69#ibcon#about to write, iclass 14, count 2 2006.260.07:36:28.69#ibcon#wrote, iclass 14, count 2 2006.260.07:36:28.69#ibcon#about to read 3, iclass 14, count 2 2006.260.07:36:28.72#ibcon#read 3, iclass 14, count 2 2006.260.07:36:28.72#ibcon#about to read 4, iclass 14, count 2 2006.260.07:36:28.72#ibcon#read 4, iclass 14, count 2 2006.260.07:36:28.72#ibcon#about to read 5, iclass 14, count 2 2006.260.07:36:28.72#ibcon#read 5, iclass 14, count 2 2006.260.07:36:28.72#ibcon#about to read 6, iclass 14, count 2 2006.260.07:36:28.72#ibcon#read 6, iclass 14, count 2 2006.260.07:36:28.72#ibcon#end of sib2, iclass 14, count 2 2006.260.07:36:28.72#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:36:28.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:36:28.72#ibcon#[25=AT01-08\r\n] 2006.260.07:36:28.72#ibcon#*before write, iclass 14, count 2 2006.260.07:36:28.72#ibcon#enter sib2, iclass 14, count 2 2006.260.07:36:28.72#ibcon#flushed, iclass 14, count 2 2006.260.07:36:28.72#ibcon#about to write, iclass 14, count 2 2006.260.07:36:28.72#ibcon#wrote, iclass 14, count 2 2006.260.07:36:28.72#ibcon#about to read 3, iclass 14, count 2 2006.260.07:36:28.75#ibcon#read 3, iclass 14, count 2 2006.260.07:36:28.75#ibcon#about to read 4, iclass 14, count 2 2006.260.07:36:28.75#ibcon#read 4, iclass 14, count 2 2006.260.07:36:28.75#ibcon#about to read 5, iclass 14, count 2 2006.260.07:36:28.75#ibcon#read 5, iclass 14, count 2 2006.260.07:36:28.75#ibcon#about to read 6, iclass 14, count 2 2006.260.07:36:28.75#ibcon#read 6, iclass 14, count 2 2006.260.07:36:28.75#ibcon#end of sib2, iclass 14, count 2 2006.260.07:36:28.75#ibcon#*after write, iclass 14, count 2 2006.260.07:36:28.75#ibcon#*before return 0, iclass 14, count 2 2006.260.07:36:28.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:28.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:28.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:36:28.75#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:28.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:28.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:28.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:28.87#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:36:28.87#ibcon#first serial, iclass 14, count 0 2006.260.07:36:28.87#ibcon#enter sib2, iclass 14, count 0 2006.260.07:36:28.87#ibcon#flushed, iclass 14, count 0 2006.260.07:36:28.87#ibcon#about to write, iclass 14, count 0 2006.260.07:36:28.87#ibcon#wrote, iclass 14, count 0 2006.260.07:36:28.87#ibcon#about to read 3, iclass 14, count 0 2006.260.07:36:28.89#ibcon#read 3, iclass 14, count 0 2006.260.07:36:28.89#ibcon#about to read 4, iclass 14, count 0 2006.260.07:36:28.89#ibcon#read 4, iclass 14, count 0 2006.260.07:36:28.89#ibcon#about to read 5, iclass 14, count 0 2006.260.07:36:28.89#ibcon#read 5, iclass 14, count 0 2006.260.07:36:28.89#ibcon#about to read 6, iclass 14, count 0 2006.260.07:36:28.89#ibcon#read 6, iclass 14, count 0 2006.260.07:36:28.89#ibcon#end of sib2, iclass 14, count 0 2006.260.07:36:28.89#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:36:28.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:36:28.89#ibcon#[25=USB\r\n] 2006.260.07:36:28.89#ibcon#*before write, iclass 14, count 0 2006.260.07:36:28.89#ibcon#enter sib2, iclass 14, count 0 2006.260.07:36:28.89#ibcon#flushed, iclass 14, count 0 2006.260.07:36:28.89#ibcon#about to write, iclass 14, count 0 2006.260.07:36:28.89#ibcon#wrote, iclass 14, count 0 2006.260.07:36:28.89#ibcon#about to read 3, iclass 14, count 0 2006.260.07:36:28.92#ibcon#read 3, iclass 14, count 0 2006.260.07:36:28.92#ibcon#about to read 4, iclass 14, count 0 2006.260.07:36:28.92#ibcon#read 4, iclass 14, count 0 2006.260.07:36:28.92#ibcon#about to read 5, iclass 14, count 0 2006.260.07:36:28.92#ibcon#read 5, iclass 14, count 0 2006.260.07:36:28.92#ibcon#about to read 6, iclass 14, count 0 2006.260.07:36:28.92#ibcon#read 6, iclass 14, count 0 2006.260.07:36:28.92#ibcon#end of sib2, iclass 14, count 0 2006.260.07:36:28.92#ibcon#*after write, iclass 14, count 0 2006.260.07:36:28.92#ibcon#*before return 0, iclass 14, count 0 2006.260.07:36:28.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:28.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:28.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:36:28.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:36:28.92$vc4f8/valo=2,572.99 2006.260.07:36:28.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:36:28.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:36:28.92#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:28.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:28.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:28.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:28.92#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:36:28.92#ibcon#first serial, iclass 16, count 0 2006.260.07:36:28.92#ibcon#enter sib2, iclass 16, count 0 2006.260.07:36:28.92#ibcon#flushed, iclass 16, count 0 2006.260.07:36:28.92#ibcon#about to write, iclass 16, count 0 2006.260.07:36:28.92#ibcon#wrote, iclass 16, count 0 2006.260.07:36:28.92#ibcon#about to read 3, iclass 16, count 0 2006.260.07:36:28.94#ibcon#read 3, iclass 16, count 0 2006.260.07:36:28.94#ibcon#about to read 4, iclass 16, count 0 2006.260.07:36:28.94#ibcon#read 4, iclass 16, count 0 2006.260.07:36:28.94#ibcon#about to read 5, iclass 16, count 0 2006.260.07:36:28.94#ibcon#read 5, iclass 16, count 0 2006.260.07:36:28.94#ibcon#about to read 6, iclass 16, count 0 2006.260.07:36:28.94#ibcon#read 6, iclass 16, count 0 2006.260.07:36:28.94#ibcon#end of sib2, iclass 16, count 0 2006.260.07:36:28.94#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:36:28.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:36:28.94#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:36:28.94#ibcon#*before write, iclass 16, count 0 2006.260.07:36:28.94#ibcon#enter sib2, iclass 16, count 0 2006.260.07:36:28.94#ibcon#flushed, iclass 16, count 0 2006.260.07:36:28.94#ibcon#about to write, iclass 16, count 0 2006.260.07:36:28.94#ibcon#wrote, iclass 16, count 0 2006.260.07:36:28.94#ibcon#about to read 3, iclass 16, count 0 2006.260.07:36:28.98#ibcon#read 3, iclass 16, count 0 2006.260.07:36:28.98#ibcon#about to read 4, iclass 16, count 0 2006.260.07:36:28.98#ibcon#read 4, iclass 16, count 0 2006.260.07:36:28.98#ibcon#about to read 5, iclass 16, count 0 2006.260.07:36:28.98#ibcon#read 5, iclass 16, count 0 2006.260.07:36:28.98#ibcon#about to read 6, iclass 16, count 0 2006.260.07:36:28.98#ibcon#read 6, iclass 16, count 0 2006.260.07:36:28.98#ibcon#end of sib2, iclass 16, count 0 2006.260.07:36:28.98#ibcon#*after write, iclass 16, count 0 2006.260.07:36:28.98#ibcon#*before return 0, iclass 16, count 0 2006.260.07:36:28.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:28.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:28.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:36:28.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:36:28.98$vc4f8/va=2,7 2006.260.07:36:28.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:36:28.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:36:28.98#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:28.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:29.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:29.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:29.04#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:36:29.04#ibcon#first serial, iclass 18, count 2 2006.260.07:36:29.04#ibcon#enter sib2, iclass 18, count 2 2006.260.07:36:29.04#ibcon#flushed, iclass 18, count 2 2006.260.07:36:29.04#ibcon#about to write, iclass 18, count 2 2006.260.07:36:29.04#ibcon#wrote, iclass 18, count 2 2006.260.07:36:29.04#ibcon#about to read 3, iclass 18, count 2 2006.260.07:36:29.07#ibcon#read 3, iclass 18, count 2 2006.260.07:36:29.07#ibcon#about to read 4, iclass 18, count 2 2006.260.07:36:29.07#ibcon#read 4, iclass 18, count 2 2006.260.07:36:29.07#ibcon#about to read 5, iclass 18, count 2 2006.260.07:36:29.07#ibcon#read 5, iclass 18, count 2 2006.260.07:36:29.07#ibcon#about to read 6, iclass 18, count 2 2006.260.07:36:29.07#ibcon#read 6, iclass 18, count 2 2006.260.07:36:29.07#ibcon#end of sib2, iclass 18, count 2 2006.260.07:36:29.07#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:36:29.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:36:29.07#ibcon#[25=AT02-07\r\n] 2006.260.07:36:29.07#ibcon#*before write, iclass 18, count 2 2006.260.07:36:29.07#ibcon#enter sib2, iclass 18, count 2 2006.260.07:36:29.07#ibcon#flushed, iclass 18, count 2 2006.260.07:36:29.07#ibcon#about to write, iclass 18, count 2 2006.260.07:36:29.07#ibcon#wrote, iclass 18, count 2 2006.260.07:36:29.07#ibcon#about to read 3, iclass 18, count 2 2006.260.07:36:29.10#ibcon#read 3, iclass 18, count 2 2006.260.07:36:29.10#ibcon#about to read 4, iclass 18, count 2 2006.260.07:36:29.10#ibcon#read 4, iclass 18, count 2 2006.260.07:36:29.10#ibcon#about to read 5, iclass 18, count 2 2006.260.07:36:29.10#ibcon#read 5, iclass 18, count 2 2006.260.07:36:29.10#ibcon#about to read 6, iclass 18, count 2 2006.260.07:36:29.10#ibcon#read 6, iclass 18, count 2 2006.260.07:36:29.10#ibcon#end of sib2, iclass 18, count 2 2006.260.07:36:29.10#ibcon#*after write, iclass 18, count 2 2006.260.07:36:29.10#ibcon#*before return 0, iclass 18, count 2 2006.260.07:36:29.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:29.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:29.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:36:29.10#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:29.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:29.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:29.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:29.22#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:36:29.22#ibcon#first serial, iclass 18, count 0 2006.260.07:36:29.22#ibcon#enter sib2, iclass 18, count 0 2006.260.07:36:29.22#ibcon#flushed, iclass 18, count 0 2006.260.07:36:29.22#ibcon#about to write, iclass 18, count 0 2006.260.07:36:29.22#ibcon#wrote, iclass 18, count 0 2006.260.07:36:29.22#ibcon#about to read 3, iclass 18, count 0 2006.260.07:36:29.24#ibcon#read 3, iclass 18, count 0 2006.260.07:36:29.24#ibcon#about to read 4, iclass 18, count 0 2006.260.07:36:29.24#ibcon#read 4, iclass 18, count 0 2006.260.07:36:29.24#ibcon#about to read 5, iclass 18, count 0 2006.260.07:36:29.24#ibcon#read 5, iclass 18, count 0 2006.260.07:36:29.24#ibcon#about to read 6, iclass 18, count 0 2006.260.07:36:29.24#ibcon#read 6, iclass 18, count 0 2006.260.07:36:29.24#ibcon#end of sib2, iclass 18, count 0 2006.260.07:36:29.24#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:36:29.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:36:29.24#ibcon#[25=USB\r\n] 2006.260.07:36:29.24#ibcon#*before write, iclass 18, count 0 2006.260.07:36:29.24#ibcon#enter sib2, iclass 18, count 0 2006.260.07:36:29.24#ibcon#flushed, iclass 18, count 0 2006.260.07:36:29.24#ibcon#about to write, iclass 18, count 0 2006.260.07:36:29.24#ibcon#wrote, iclass 18, count 0 2006.260.07:36:29.24#ibcon#about to read 3, iclass 18, count 0 2006.260.07:36:29.27#ibcon#read 3, iclass 18, count 0 2006.260.07:36:29.27#ibcon#about to read 4, iclass 18, count 0 2006.260.07:36:29.27#ibcon#read 4, iclass 18, count 0 2006.260.07:36:29.27#ibcon#about to read 5, iclass 18, count 0 2006.260.07:36:29.27#ibcon#read 5, iclass 18, count 0 2006.260.07:36:29.27#ibcon#about to read 6, iclass 18, count 0 2006.260.07:36:29.27#ibcon#read 6, iclass 18, count 0 2006.260.07:36:29.27#ibcon#end of sib2, iclass 18, count 0 2006.260.07:36:29.27#ibcon#*after write, iclass 18, count 0 2006.260.07:36:29.27#ibcon#*before return 0, iclass 18, count 0 2006.260.07:36:29.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:29.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:29.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:36:29.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:36:29.27$vc4f8/valo=3,672.99 2006.260.07:36:29.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:36:29.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:36:29.27#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:29.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:29.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:29.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:29.27#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:36:29.27#ibcon#first serial, iclass 20, count 0 2006.260.07:36:29.27#ibcon#enter sib2, iclass 20, count 0 2006.260.07:36:29.27#ibcon#flushed, iclass 20, count 0 2006.260.07:36:29.27#ibcon#about to write, iclass 20, count 0 2006.260.07:36:29.27#ibcon#wrote, iclass 20, count 0 2006.260.07:36:29.27#ibcon#about to read 3, iclass 20, count 0 2006.260.07:36:29.29#ibcon#read 3, iclass 20, count 0 2006.260.07:36:29.29#ibcon#about to read 4, iclass 20, count 0 2006.260.07:36:29.29#ibcon#read 4, iclass 20, count 0 2006.260.07:36:29.29#ibcon#about to read 5, iclass 20, count 0 2006.260.07:36:29.29#ibcon#read 5, iclass 20, count 0 2006.260.07:36:29.29#ibcon#about to read 6, iclass 20, count 0 2006.260.07:36:29.29#ibcon#read 6, iclass 20, count 0 2006.260.07:36:29.29#ibcon#end of sib2, iclass 20, count 0 2006.260.07:36:29.29#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:36:29.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:36:29.29#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:36:29.29#ibcon#*before write, iclass 20, count 0 2006.260.07:36:29.29#ibcon#enter sib2, iclass 20, count 0 2006.260.07:36:29.29#ibcon#flushed, iclass 20, count 0 2006.260.07:36:29.29#ibcon#about to write, iclass 20, count 0 2006.260.07:36:29.29#ibcon#wrote, iclass 20, count 0 2006.260.07:36:29.29#ibcon#about to read 3, iclass 20, count 0 2006.260.07:36:29.33#ibcon#read 3, iclass 20, count 0 2006.260.07:36:29.33#ibcon#about to read 4, iclass 20, count 0 2006.260.07:36:29.33#ibcon#read 4, iclass 20, count 0 2006.260.07:36:29.33#ibcon#about to read 5, iclass 20, count 0 2006.260.07:36:29.33#ibcon#read 5, iclass 20, count 0 2006.260.07:36:29.33#ibcon#about to read 6, iclass 20, count 0 2006.260.07:36:29.33#ibcon#read 6, iclass 20, count 0 2006.260.07:36:29.33#ibcon#end of sib2, iclass 20, count 0 2006.260.07:36:29.33#ibcon#*after write, iclass 20, count 0 2006.260.07:36:29.33#ibcon#*before return 0, iclass 20, count 0 2006.260.07:36:29.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:29.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:29.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:36:29.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:36:29.33$vc4f8/va=3,8 2006.260.07:36:29.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:36:29.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:36:29.33#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:29.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:29.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:29.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:29.39#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:36:29.39#ibcon#first serial, iclass 22, count 2 2006.260.07:36:29.39#ibcon#enter sib2, iclass 22, count 2 2006.260.07:36:29.39#ibcon#flushed, iclass 22, count 2 2006.260.07:36:29.39#ibcon#about to write, iclass 22, count 2 2006.260.07:36:29.39#ibcon#wrote, iclass 22, count 2 2006.260.07:36:29.39#ibcon#about to read 3, iclass 22, count 2 2006.260.07:36:29.42#ibcon#read 3, iclass 22, count 2 2006.260.07:36:29.42#ibcon#about to read 4, iclass 22, count 2 2006.260.07:36:29.42#ibcon#read 4, iclass 22, count 2 2006.260.07:36:29.42#ibcon#about to read 5, iclass 22, count 2 2006.260.07:36:29.42#ibcon#read 5, iclass 22, count 2 2006.260.07:36:29.42#ibcon#about to read 6, iclass 22, count 2 2006.260.07:36:29.42#ibcon#read 6, iclass 22, count 2 2006.260.07:36:29.42#ibcon#end of sib2, iclass 22, count 2 2006.260.07:36:29.42#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:36:29.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:36:29.42#ibcon#[25=AT03-08\r\n] 2006.260.07:36:29.42#ibcon#*before write, iclass 22, count 2 2006.260.07:36:29.42#ibcon#enter sib2, iclass 22, count 2 2006.260.07:36:29.42#ibcon#flushed, iclass 22, count 2 2006.260.07:36:29.42#ibcon#about to write, iclass 22, count 2 2006.260.07:36:29.42#ibcon#wrote, iclass 22, count 2 2006.260.07:36:29.42#ibcon#about to read 3, iclass 22, count 2 2006.260.07:36:29.45#ibcon#read 3, iclass 22, count 2 2006.260.07:36:29.45#ibcon#about to read 4, iclass 22, count 2 2006.260.07:36:29.45#ibcon#read 4, iclass 22, count 2 2006.260.07:36:29.45#ibcon#about to read 5, iclass 22, count 2 2006.260.07:36:29.45#ibcon#read 5, iclass 22, count 2 2006.260.07:36:29.45#ibcon#about to read 6, iclass 22, count 2 2006.260.07:36:29.45#ibcon#read 6, iclass 22, count 2 2006.260.07:36:29.45#ibcon#end of sib2, iclass 22, count 2 2006.260.07:36:29.45#ibcon#*after write, iclass 22, count 2 2006.260.07:36:29.45#ibcon#*before return 0, iclass 22, count 2 2006.260.07:36:29.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:29.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:29.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:36:29.45#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:29.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:29.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:29.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:29.57#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:36:29.57#ibcon#first serial, iclass 22, count 0 2006.260.07:36:29.57#ibcon#enter sib2, iclass 22, count 0 2006.260.07:36:29.57#ibcon#flushed, iclass 22, count 0 2006.260.07:36:29.57#ibcon#about to write, iclass 22, count 0 2006.260.07:36:29.57#ibcon#wrote, iclass 22, count 0 2006.260.07:36:29.57#ibcon#about to read 3, iclass 22, count 0 2006.260.07:36:29.59#ibcon#read 3, iclass 22, count 0 2006.260.07:36:29.59#ibcon#about to read 4, iclass 22, count 0 2006.260.07:36:29.59#ibcon#read 4, iclass 22, count 0 2006.260.07:36:29.59#ibcon#about to read 5, iclass 22, count 0 2006.260.07:36:29.59#ibcon#read 5, iclass 22, count 0 2006.260.07:36:29.59#ibcon#about to read 6, iclass 22, count 0 2006.260.07:36:29.59#ibcon#read 6, iclass 22, count 0 2006.260.07:36:29.59#ibcon#end of sib2, iclass 22, count 0 2006.260.07:36:29.59#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:36:29.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:36:29.59#ibcon#[25=USB\r\n] 2006.260.07:36:29.59#ibcon#*before write, iclass 22, count 0 2006.260.07:36:29.59#ibcon#enter sib2, iclass 22, count 0 2006.260.07:36:29.59#ibcon#flushed, iclass 22, count 0 2006.260.07:36:29.59#ibcon#about to write, iclass 22, count 0 2006.260.07:36:29.59#ibcon#wrote, iclass 22, count 0 2006.260.07:36:29.59#ibcon#about to read 3, iclass 22, count 0 2006.260.07:36:29.62#ibcon#read 3, iclass 22, count 0 2006.260.07:36:29.62#ibcon#about to read 4, iclass 22, count 0 2006.260.07:36:29.62#ibcon#read 4, iclass 22, count 0 2006.260.07:36:29.62#ibcon#about to read 5, iclass 22, count 0 2006.260.07:36:29.62#ibcon#read 5, iclass 22, count 0 2006.260.07:36:29.62#ibcon#about to read 6, iclass 22, count 0 2006.260.07:36:29.62#ibcon#read 6, iclass 22, count 0 2006.260.07:36:29.62#ibcon#end of sib2, iclass 22, count 0 2006.260.07:36:29.62#ibcon#*after write, iclass 22, count 0 2006.260.07:36:29.62#ibcon#*before return 0, iclass 22, count 0 2006.260.07:36:29.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:29.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:29.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:36:29.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:36:29.62$vc4f8/valo=4,832.99 2006.260.07:36:29.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:36:29.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:36:29.62#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:29.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:29.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:29.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:29.62#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:36:29.62#ibcon#first serial, iclass 24, count 0 2006.260.07:36:29.62#ibcon#enter sib2, iclass 24, count 0 2006.260.07:36:29.62#ibcon#flushed, iclass 24, count 0 2006.260.07:36:29.62#ibcon#about to write, iclass 24, count 0 2006.260.07:36:29.62#ibcon#wrote, iclass 24, count 0 2006.260.07:36:29.62#ibcon#about to read 3, iclass 24, count 0 2006.260.07:36:29.64#ibcon#read 3, iclass 24, count 0 2006.260.07:36:29.64#ibcon#about to read 4, iclass 24, count 0 2006.260.07:36:29.64#ibcon#read 4, iclass 24, count 0 2006.260.07:36:29.64#ibcon#about to read 5, iclass 24, count 0 2006.260.07:36:29.64#ibcon#read 5, iclass 24, count 0 2006.260.07:36:29.64#ibcon#about to read 6, iclass 24, count 0 2006.260.07:36:29.64#ibcon#read 6, iclass 24, count 0 2006.260.07:36:29.64#ibcon#end of sib2, iclass 24, count 0 2006.260.07:36:29.64#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:36:29.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:36:29.64#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:36:29.64#ibcon#*before write, iclass 24, count 0 2006.260.07:36:29.64#ibcon#enter sib2, iclass 24, count 0 2006.260.07:36:29.64#ibcon#flushed, iclass 24, count 0 2006.260.07:36:29.64#ibcon#about to write, iclass 24, count 0 2006.260.07:36:29.64#ibcon#wrote, iclass 24, count 0 2006.260.07:36:29.64#ibcon#about to read 3, iclass 24, count 0 2006.260.07:36:29.68#ibcon#read 3, iclass 24, count 0 2006.260.07:36:29.68#ibcon#about to read 4, iclass 24, count 0 2006.260.07:36:29.68#ibcon#read 4, iclass 24, count 0 2006.260.07:36:29.68#ibcon#about to read 5, iclass 24, count 0 2006.260.07:36:29.68#ibcon#read 5, iclass 24, count 0 2006.260.07:36:29.68#ibcon#about to read 6, iclass 24, count 0 2006.260.07:36:29.68#ibcon#read 6, iclass 24, count 0 2006.260.07:36:29.68#ibcon#end of sib2, iclass 24, count 0 2006.260.07:36:29.68#ibcon#*after write, iclass 24, count 0 2006.260.07:36:29.68#ibcon#*before return 0, iclass 24, count 0 2006.260.07:36:29.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:29.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:29.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:36:29.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:36:29.68$vc4f8/va=4,7 2006.260.07:36:29.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.07:36:29.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.07:36:29.68#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:29.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:29.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:29.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:29.74#ibcon#enter wrdev, iclass 26, count 2 2006.260.07:36:29.74#ibcon#first serial, iclass 26, count 2 2006.260.07:36:29.74#ibcon#enter sib2, iclass 26, count 2 2006.260.07:36:29.74#ibcon#flushed, iclass 26, count 2 2006.260.07:36:29.74#ibcon#about to write, iclass 26, count 2 2006.260.07:36:29.74#ibcon#wrote, iclass 26, count 2 2006.260.07:36:29.74#ibcon#about to read 3, iclass 26, count 2 2006.260.07:36:29.76#ibcon#read 3, iclass 26, count 2 2006.260.07:36:29.76#ibcon#about to read 4, iclass 26, count 2 2006.260.07:36:29.76#ibcon#read 4, iclass 26, count 2 2006.260.07:36:29.76#ibcon#about to read 5, iclass 26, count 2 2006.260.07:36:29.76#ibcon#read 5, iclass 26, count 2 2006.260.07:36:29.76#ibcon#about to read 6, iclass 26, count 2 2006.260.07:36:29.76#ibcon#read 6, iclass 26, count 2 2006.260.07:36:29.76#ibcon#end of sib2, iclass 26, count 2 2006.260.07:36:29.76#ibcon#*mode == 0, iclass 26, count 2 2006.260.07:36:29.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.07:36:29.76#ibcon#[25=AT04-07\r\n] 2006.260.07:36:29.76#ibcon#*before write, iclass 26, count 2 2006.260.07:36:29.76#ibcon#enter sib2, iclass 26, count 2 2006.260.07:36:29.76#ibcon#flushed, iclass 26, count 2 2006.260.07:36:29.76#ibcon#about to write, iclass 26, count 2 2006.260.07:36:29.76#ibcon#wrote, iclass 26, count 2 2006.260.07:36:29.76#ibcon#about to read 3, iclass 26, count 2 2006.260.07:36:29.79#ibcon#read 3, iclass 26, count 2 2006.260.07:36:29.79#ibcon#about to read 4, iclass 26, count 2 2006.260.07:36:29.79#ibcon#read 4, iclass 26, count 2 2006.260.07:36:29.79#ibcon#about to read 5, iclass 26, count 2 2006.260.07:36:29.79#ibcon#read 5, iclass 26, count 2 2006.260.07:36:29.79#ibcon#about to read 6, iclass 26, count 2 2006.260.07:36:29.79#ibcon#read 6, iclass 26, count 2 2006.260.07:36:29.79#ibcon#end of sib2, iclass 26, count 2 2006.260.07:36:29.79#ibcon#*after write, iclass 26, count 2 2006.260.07:36:29.79#ibcon#*before return 0, iclass 26, count 2 2006.260.07:36:29.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:29.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:29.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.07:36:29.79#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:29.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:29.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:29.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:29.91#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:36:29.91#ibcon#first serial, iclass 26, count 0 2006.260.07:36:29.91#ibcon#enter sib2, iclass 26, count 0 2006.260.07:36:29.91#ibcon#flushed, iclass 26, count 0 2006.260.07:36:29.91#ibcon#about to write, iclass 26, count 0 2006.260.07:36:29.91#ibcon#wrote, iclass 26, count 0 2006.260.07:36:29.91#ibcon#about to read 3, iclass 26, count 0 2006.260.07:36:29.93#ibcon#read 3, iclass 26, count 0 2006.260.07:36:29.93#ibcon#about to read 4, iclass 26, count 0 2006.260.07:36:29.93#ibcon#read 4, iclass 26, count 0 2006.260.07:36:29.93#ibcon#about to read 5, iclass 26, count 0 2006.260.07:36:29.93#ibcon#read 5, iclass 26, count 0 2006.260.07:36:29.93#ibcon#about to read 6, iclass 26, count 0 2006.260.07:36:29.93#ibcon#read 6, iclass 26, count 0 2006.260.07:36:29.93#ibcon#end of sib2, iclass 26, count 0 2006.260.07:36:29.93#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:36:29.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:36:29.93#ibcon#[25=USB\r\n] 2006.260.07:36:29.93#ibcon#*before write, iclass 26, count 0 2006.260.07:36:29.93#ibcon#enter sib2, iclass 26, count 0 2006.260.07:36:29.93#ibcon#flushed, iclass 26, count 0 2006.260.07:36:29.93#ibcon#about to write, iclass 26, count 0 2006.260.07:36:29.93#ibcon#wrote, iclass 26, count 0 2006.260.07:36:29.93#ibcon#about to read 3, iclass 26, count 0 2006.260.07:36:29.96#ibcon#read 3, iclass 26, count 0 2006.260.07:36:29.96#ibcon#about to read 4, iclass 26, count 0 2006.260.07:36:29.96#ibcon#read 4, iclass 26, count 0 2006.260.07:36:29.96#ibcon#about to read 5, iclass 26, count 0 2006.260.07:36:29.96#ibcon#read 5, iclass 26, count 0 2006.260.07:36:29.96#ibcon#about to read 6, iclass 26, count 0 2006.260.07:36:29.96#ibcon#read 6, iclass 26, count 0 2006.260.07:36:29.96#ibcon#end of sib2, iclass 26, count 0 2006.260.07:36:29.96#ibcon#*after write, iclass 26, count 0 2006.260.07:36:29.96#ibcon#*before return 0, iclass 26, count 0 2006.260.07:36:29.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:29.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:29.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:36:29.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:36:29.96$vc4f8/valo=5,652.99 2006.260.07:36:29.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:36:29.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:36:29.96#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:29.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:29.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:29.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:29.96#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:36:29.96#ibcon#first serial, iclass 28, count 0 2006.260.07:36:29.96#ibcon#enter sib2, iclass 28, count 0 2006.260.07:36:29.96#ibcon#flushed, iclass 28, count 0 2006.260.07:36:29.96#ibcon#about to write, iclass 28, count 0 2006.260.07:36:29.96#ibcon#wrote, iclass 28, count 0 2006.260.07:36:29.96#ibcon#about to read 3, iclass 28, count 0 2006.260.07:36:29.98#ibcon#read 3, iclass 28, count 0 2006.260.07:36:29.98#ibcon#about to read 4, iclass 28, count 0 2006.260.07:36:29.98#ibcon#read 4, iclass 28, count 0 2006.260.07:36:29.98#ibcon#about to read 5, iclass 28, count 0 2006.260.07:36:29.98#ibcon#read 5, iclass 28, count 0 2006.260.07:36:29.98#ibcon#about to read 6, iclass 28, count 0 2006.260.07:36:29.98#ibcon#read 6, iclass 28, count 0 2006.260.07:36:29.98#ibcon#end of sib2, iclass 28, count 0 2006.260.07:36:29.98#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:36:29.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:36:29.98#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:36:29.98#ibcon#*before write, iclass 28, count 0 2006.260.07:36:29.98#ibcon#enter sib2, iclass 28, count 0 2006.260.07:36:29.98#ibcon#flushed, iclass 28, count 0 2006.260.07:36:29.98#ibcon#about to write, iclass 28, count 0 2006.260.07:36:29.98#ibcon#wrote, iclass 28, count 0 2006.260.07:36:29.98#ibcon#about to read 3, iclass 28, count 0 2006.260.07:36:30.02#ibcon#read 3, iclass 28, count 0 2006.260.07:36:30.02#ibcon#about to read 4, iclass 28, count 0 2006.260.07:36:30.02#ibcon#read 4, iclass 28, count 0 2006.260.07:36:30.02#ibcon#about to read 5, iclass 28, count 0 2006.260.07:36:30.02#ibcon#read 5, iclass 28, count 0 2006.260.07:36:30.02#ibcon#about to read 6, iclass 28, count 0 2006.260.07:36:30.02#ibcon#read 6, iclass 28, count 0 2006.260.07:36:30.02#ibcon#end of sib2, iclass 28, count 0 2006.260.07:36:30.02#ibcon#*after write, iclass 28, count 0 2006.260.07:36:30.02#ibcon#*before return 0, iclass 28, count 0 2006.260.07:36:30.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:30.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:30.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:36:30.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:36:30.02$vc4f8/va=5,7 2006.260.07:36:30.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.07:36:30.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.07:36:30.02#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:30.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:30.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:30.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:30.08#ibcon#enter wrdev, iclass 30, count 2 2006.260.07:36:30.08#ibcon#first serial, iclass 30, count 2 2006.260.07:36:30.08#ibcon#enter sib2, iclass 30, count 2 2006.260.07:36:30.08#ibcon#flushed, iclass 30, count 2 2006.260.07:36:30.08#ibcon#about to write, iclass 30, count 2 2006.260.07:36:30.08#ibcon#wrote, iclass 30, count 2 2006.260.07:36:30.08#ibcon#about to read 3, iclass 30, count 2 2006.260.07:36:30.10#ibcon#read 3, iclass 30, count 2 2006.260.07:36:30.10#ibcon#about to read 4, iclass 30, count 2 2006.260.07:36:30.10#ibcon#read 4, iclass 30, count 2 2006.260.07:36:30.10#ibcon#about to read 5, iclass 30, count 2 2006.260.07:36:30.10#ibcon#read 5, iclass 30, count 2 2006.260.07:36:30.10#ibcon#about to read 6, iclass 30, count 2 2006.260.07:36:30.10#ibcon#read 6, iclass 30, count 2 2006.260.07:36:30.10#ibcon#end of sib2, iclass 30, count 2 2006.260.07:36:30.10#ibcon#*mode == 0, iclass 30, count 2 2006.260.07:36:30.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.07:36:30.10#ibcon#[25=AT05-07\r\n] 2006.260.07:36:30.10#ibcon#*before write, iclass 30, count 2 2006.260.07:36:30.10#ibcon#enter sib2, iclass 30, count 2 2006.260.07:36:30.10#ibcon#flushed, iclass 30, count 2 2006.260.07:36:30.10#ibcon#about to write, iclass 30, count 2 2006.260.07:36:30.10#ibcon#wrote, iclass 30, count 2 2006.260.07:36:30.10#ibcon#about to read 3, iclass 30, count 2 2006.260.07:36:30.13#ibcon#read 3, iclass 30, count 2 2006.260.07:36:30.13#ibcon#about to read 4, iclass 30, count 2 2006.260.07:36:30.13#ibcon#read 4, iclass 30, count 2 2006.260.07:36:30.13#ibcon#about to read 5, iclass 30, count 2 2006.260.07:36:30.13#ibcon#read 5, iclass 30, count 2 2006.260.07:36:30.13#ibcon#about to read 6, iclass 30, count 2 2006.260.07:36:30.13#ibcon#read 6, iclass 30, count 2 2006.260.07:36:30.13#ibcon#end of sib2, iclass 30, count 2 2006.260.07:36:30.13#ibcon#*after write, iclass 30, count 2 2006.260.07:36:30.13#ibcon#*before return 0, iclass 30, count 2 2006.260.07:36:30.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:30.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:30.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.07:36:30.13#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:30.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:30.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:30.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:30.25#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:36:30.25#ibcon#first serial, iclass 30, count 0 2006.260.07:36:30.25#ibcon#enter sib2, iclass 30, count 0 2006.260.07:36:30.25#ibcon#flushed, iclass 30, count 0 2006.260.07:36:30.25#ibcon#about to write, iclass 30, count 0 2006.260.07:36:30.25#ibcon#wrote, iclass 30, count 0 2006.260.07:36:30.25#ibcon#about to read 3, iclass 30, count 0 2006.260.07:36:30.27#ibcon#read 3, iclass 30, count 0 2006.260.07:36:30.27#ibcon#about to read 4, iclass 30, count 0 2006.260.07:36:30.27#ibcon#read 4, iclass 30, count 0 2006.260.07:36:30.27#ibcon#about to read 5, iclass 30, count 0 2006.260.07:36:30.27#ibcon#read 5, iclass 30, count 0 2006.260.07:36:30.27#ibcon#about to read 6, iclass 30, count 0 2006.260.07:36:30.27#ibcon#read 6, iclass 30, count 0 2006.260.07:36:30.27#ibcon#end of sib2, iclass 30, count 0 2006.260.07:36:30.27#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:36:30.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:36:30.27#ibcon#[25=USB\r\n] 2006.260.07:36:30.27#ibcon#*before write, iclass 30, count 0 2006.260.07:36:30.27#ibcon#enter sib2, iclass 30, count 0 2006.260.07:36:30.27#ibcon#flushed, iclass 30, count 0 2006.260.07:36:30.27#ibcon#about to write, iclass 30, count 0 2006.260.07:36:30.27#ibcon#wrote, iclass 30, count 0 2006.260.07:36:30.27#ibcon#about to read 3, iclass 30, count 0 2006.260.07:36:30.30#ibcon#read 3, iclass 30, count 0 2006.260.07:36:30.30#ibcon#about to read 4, iclass 30, count 0 2006.260.07:36:30.30#ibcon#read 4, iclass 30, count 0 2006.260.07:36:30.30#ibcon#about to read 5, iclass 30, count 0 2006.260.07:36:30.30#ibcon#read 5, iclass 30, count 0 2006.260.07:36:30.30#ibcon#about to read 6, iclass 30, count 0 2006.260.07:36:30.30#ibcon#read 6, iclass 30, count 0 2006.260.07:36:30.30#ibcon#end of sib2, iclass 30, count 0 2006.260.07:36:30.30#ibcon#*after write, iclass 30, count 0 2006.260.07:36:30.30#ibcon#*before return 0, iclass 30, count 0 2006.260.07:36:30.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:30.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:30.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:36:30.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:36:30.30$vc4f8/valo=6,772.99 2006.260.07:36:30.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:36:30.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:36:30.30#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:30.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:30.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:30.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:30.30#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:36:30.30#ibcon#first serial, iclass 32, count 0 2006.260.07:36:30.30#ibcon#enter sib2, iclass 32, count 0 2006.260.07:36:30.30#ibcon#flushed, iclass 32, count 0 2006.260.07:36:30.30#ibcon#about to write, iclass 32, count 0 2006.260.07:36:30.30#ibcon#wrote, iclass 32, count 0 2006.260.07:36:30.30#ibcon#about to read 3, iclass 32, count 0 2006.260.07:36:30.32#ibcon#read 3, iclass 32, count 0 2006.260.07:36:30.32#ibcon#about to read 4, iclass 32, count 0 2006.260.07:36:30.32#ibcon#read 4, iclass 32, count 0 2006.260.07:36:30.32#ibcon#about to read 5, iclass 32, count 0 2006.260.07:36:30.32#ibcon#read 5, iclass 32, count 0 2006.260.07:36:30.32#ibcon#about to read 6, iclass 32, count 0 2006.260.07:36:30.32#ibcon#read 6, iclass 32, count 0 2006.260.07:36:30.32#ibcon#end of sib2, iclass 32, count 0 2006.260.07:36:30.32#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:36:30.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:36:30.32#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:36:30.32#ibcon#*before write, iclass 32, count 0 2006.260.07:36:30.32#ibcon#enter sib2, iclass 32, count 0 2006.260.07:36:30.32#ibcon#flushed, iclass 32, count 0 2006.260.07:36:30.32#ibcon#about to write, iclass 32, count 0 2006.260.07:36:30.32#ibcon#wrote, iclass 32, count 0 2006.260.07:36:30.32#ibcon#about to read 3, iclass 32, count 0 2006.260.07:36:30.36#ibcon#read 3, iclass 32, count 0 2006.260.07:36:30.36#ibcon#about to read 4, iclass 32, count 0 2006.260.07:36:30.36#ibcon#read 4, iclass 32, count 0 2006.260.07:36:30.36#ibcon#about to read 5, iclass 32, count 0 2006.260.07:36:30.36#ibcon#read 5, iclass 32, count 0 2006.260.07:36:30.36#ibcon#about to read 6, iclass 32, count 0 2006.260.07:36:30.36#ibcon#read 6, iclass 32, count 0 2006.260.07:36:30.36#ibcon#end of sib2, iclass 32, count 0 2006.260.07:36:30.36#ibcon#*after write, iclass 32, count 0 2006.260.07:36:30.36#ibcon#*before return 0, iclass 32, count 0 2006.260.07:36:30.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:30.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:30.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:36:30.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:36:30.36$vc4f8/va=6,6 2006.260.07:36:30.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.07:36:30.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.07:36:30.36#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:30.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:30.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:30.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:30.42#ibcon#enter wrdev, iclass 34, count 2 2006.260.07:36:30.42#ibcon#first serial, iclass 34, count 2 2006.260.07:36:30.42#ibcon#enter sib2, iclass 34, count 2 2006.260.07:36:30.42#ibcon#flushed, iclass 34, count 2 2006.260.07:36:30.42#ibcon#about to write, iclass 34, count 2 2006.260.07:36:30.42#ibcon#wrote, iclass 34, count 2 2006.260.07:36:30.42#ibcon#about to read 3, iclass 34, count 2 2006.260.07:36:30.44#ibcon#read 3, iclass 34, count 2 2006.260.07:36:30.44#ibcon#about to read 4, iclass 34, count 2 2006.260.07:36:30.44#ibcon#read 4, iclass 34, count 2 2006.260.07:36:30.44#ibcon#about to read 5, iclass 34, count 2 2006.260.07:36:30.44#ibcon#read 5, iclass 34, count 2 2006.260.07:36:30.44#ibcon#about to read 6, iclass 34, count 2 2006.260.07:36:30.44#ibcon#read 6, iclass 34, count 2 2006.260.07:36:30.44#ibcon#end of sib2, iclass 34, count 2 2006.260.07:36:30.44#ibcon#*mode == 0, iclass 34, count 2 2006.260.07:36:30.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.07:36:30.44#ibcon#[25=AT06-06\r\n] 2006.260.07:36:30.44#ibcon#*before write, iclass 34, count 2 2006.260.07:36:30.44#ibcon#enter sib2, iclass 34, count 2 2006.260.07:36:30.44#ibcon#flushed, iclass 34, count 2 2006.260.07:36:30.44#ibcon#about to write, iclass 34, count 2 2006.260.07:36:30.44#ibcon#wrote, iclass 34, count 2 2006.260.07:36:30.44#ibcon#about to read 3, iclass 34, count 2 2006.260.07:36:30.47#ibcon#read 3, iclass 34, count 2 2006.260.07:36:30.47#ibcon#about to read 4, iclass 34, count 2 2006.260.07:36:30.47#ibcon#read 4, iclass 34, count 2 2006.260.07:36:30.47#ibcon#about to read 5, iclass 34, count 2 2006.260.07:36:30.47#ibcon#read 5, iclass 34, count 2 2006.260.07:36:30.47#ibcon#about to read 6, iclass 34, count 2 2006.260.07:36:30.47#ibcon#read 6, iclass 34, count 2 2006.260.07:36:30.47#ibcon#end of sib2, iclass 34, count 2 2006.260.07:36:30.47#ibcon#*after write, iclass 34, count 2 2006.260.07:36:30.47#ibcon#*before return 0, iclass 34, count 2 2006.260.07:36:30.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:30.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:30.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.07:36:30.47#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:30.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:36:30.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:36:30.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:36:30.59#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:36:30.59#ibcon#first serial, iclass 34, count 0 2006.260.07:36:30.59#ibcon#enter sib2, iclass 34, count 0 2006.260.07:36:30.59#ibcon#flushed, iclass 34, count 0 2006.260.07:36:30.59#ibcon#about to write, iclass 34, count 0 2006.260.07:36:30.59#ibcon#wrote, iclass 34, count 0 2006.260.07:36:30.59#ibcon#about to read 3, iclass 34, count 0 2006.260.07:36:30.61#ibcon#read 3, iclass 34, count 0 2006.260.07:36:30.61#ibcon#about to read 4, iclass 34, count 0 2006.260.07:36:30.61#ibcon#read 4, iclass 34, count 0 2006.260.07:36:30.61#ibcon#about to read 5, iclass 34, count 0 2006.260.07:36:30.61#ibcon#read 5, iclass 34, count 0 2006.260.07:36:30.61#ibcon#about to read 6, iclass 34, count 0 2006.260.07:36:30.61#ibcon#read 6, iclass 34, count 0 2006.260.07:36:30.61#ibcon#end of sib2, iclass 34, count 0 2006.260.07:36:30.61#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:36:30.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:36:30.61#ibcon#[25=USB\r\n] 2006.260.07:36:30.61#ibcon#*before write, iclass 34, count 0 2006.260.07:36:30.61#ibcon#enter sib2, iclass 34, count 0 2006.260.07:36:30.61#ibcon#flushed, iclass 34, count 0 2006.260.07:36:30.61#ibcon#about to write, iclass 34, count 0 2006.260.07:36:30.61#ibcon#wrote, iclass 34, count 0 2006.260.07:36:30.61#ibcon#about to read 3, iclass 34, count 0 2006.260.07:36:30.64#ibcon#read 3, iclass 34, count 0 2006.260.07:36:30.64#ibcon#about to read 4, iclass 34, count 0 2006.260.07:36:30.64#ibcon#read 4, iclass 34, count 0 2006.260.07:36:30.64#ibcon#about to read 5, iclass 34, count 0 2006.260.07:36:30.64#ibcon#read 5, iclass 34, count 0 2006.260.07:36:30.64#ibcon#about to read 6, iclass 34, count 0 2006.260.07:36:30.64#ibcon#read 6, iclass 34, count 0 2006.260.07:36:30.64#ibcon#end of sib2, iclass 34, count 0 2006.260.07:36:30.64#ibcon#*after write, iclass 34, count 0 2006.260.07:36:30.64#ibcon#*before return 0, iclass 34, count 0 2006.260.07:36:30.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:36:30.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:36:30.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:36:30.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:36:30.64$vc4f8/valo=7,832.99 2006.260.07:36:30.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.07:36:30.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.07:36:30.64#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:30.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:36:30.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:36:30.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:36:30.64#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:36:30.64#ibcon#first serial, iclass 36, count 0 2006.260.07:36:30.64#ibcon#enter sib2, iclass 36, count 0 2006.260.07:36:30.64#ibcon#flushed, iclass 36, count 0 2006.260.07:36:30.64#ibcon#about to write, iclass 36, count 0 2006.260.07:36:30.64#ibcon#wrote, iclass 36, count 0 2006.260.07:36:30.64#ibcon#about to read 3, iclass 36, count 0 2006.260.07:36:30.66#ibcon#read 3, iclass 36, count 0 2006.260.07:36:30.66#ibcon#about to read 4, iclass 36, count 0 2006.260.07:36:30.66#ibcon#read 4, iclass 36, count 0 2006.260.07:36:30.66#ibcon#about to read 5, iclass 36, count 0 2006.260.07:36:30.66#ibcon#read 5, iclass 36, count 0 2006.260.07:36:30.66#ibcon#about to read 6, iclass 36, count 0 2006.260.07:36:30.66#ibcon#read 6, iclass 36, count 0 2006.260.07:36:30.66#ibcon#end of sib2, iclass 36, count 0 2006.260.07:36:30.66#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:36:30.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:36:30.66#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:36:30.66#ibcon#*before write, iclass 36, count 0 2006.260.07:36:30.66#ibcon#enter sib2, iclass 36, count 0 2006.260.07:36:30.66#ibcon#flushed, iclass 36, count 0 2006.260.07:36:30.66#ibcon#about to write, iclass 36, count 0 2006.260.07:36:30.66#ibcon#wrote, iclass 36, count 0 2006.260.07:36:30.66#ibcon#about to read 3, iclass 36, count 0 2006.260.07:36:30.70#ibcon#read 3, iclass 36, count 0 2006.260.07:36:30.70#ibcon#about to read 4, iclass 36, count 0 2006.260.07:36:30.70#ibcon#read 4, iclass 36, count 0 2006.260.07:36:30.70#ibcon#about to read 5, iclass 36, count 0 2006.260.07:36:30.70#ibcon#read 5, iclass 36, count 0 2006.260.07:36:30.70#ibcon#about to read 6, iclass 36, count 0 2006.260.07:36:30.70#ibcon#read 6, iclass 36, count 0 2006.260.07:36:30.70#ibcon#end of sib2, iclass 36, count 0 2006.260.07:36:30.70#ibcon#*after write, iclass 36, count 0 2006.260.07:36:30.70#ibcon#*before return 0, iclass 36, count 0 2006.260.07:36:30.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:36:30.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:36:30.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:36:30.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:36:30.70$vc4f8/va=7,6 2006.260.07:36:30.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.07:36:30.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.07:36:30.70#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:30.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:36:30.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:36:30.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:36:30.76#ibcon#enter wrdev, iclass 38, count 2 2006.260.07:36:30.76#ibcon#first serial, iclass 38, count 2 2006.260.07:36:30.76#ibcon#enter sib2, iclass 38, count 2 2006.260.07:36:30.76#ibcon#flushed, iclass 38, count 2 2006.260.07:36:30.76#ibcon#about to write, iclass 38, count 2 2006.260.07:36:30.76#ibcon#wrote, iclass 38, count 2 2006.260.07:36:30.76#ibcon#about to read 3, iclass 38, count 2 2006.260.07:36:30.78#ibcon#read 3, iclass 38, count 2 2006.260.07:36:30.78#ibcon#about to read 4, iclass 38, count 2 2006.260.07:36:30.78#ibcon#read 4, iclass 38, count 2 2006.260.07:36:30.78#ibcon#about to read 5, iclass 38, count 2 2006.260.07:36:30.78#ibcon#read 5, iclass 38, count 2 2006.260.07:36:30.78#ibcon#about to read 6, iclass 38, count 2 2006.260.07:36:30.78#ibcon#read 6, iclass 38, count 2 2006.260.07:36:30.78#ibcon#end of sib2, iclass 38, count 2 2006.260.07:36:30.78#ibcon#*mode == 0, iclass 38, count 2 2006.260.07:36:30.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.07:36:30.78#ibcon#[25=AT07-06\r\n] 2006.260.07:36:30.78#ibcon#*before write, iclass 38, count 2 2006.260.07:36:30.78#ibcon#enter sib2, iclass 38, count 2 2006.260.07:36:30.78#ibcon#flushed, iclass 38, count 2 2006.260.07:36:30.78#ibcon#about to write, iclass 38, count 2 2006.260.07:36:30.78#ibcon#wrote, iclass 38, count 2 2006.260.07:36:30.78#ibcon#about to read 3, iclass 38, count 2 2006.260.07:36:30.81#ibcon#read 3, iclass 38, count 2 2006.260.07:36:30.81#ibcon#about to read 4, iclass 38, count 2 2006.260.07:36:30.81#ibcon#read 4, iclass 38, count 2 2006.260.07:36:30.81#ibcon#about to read 5, iclass 38, count 2 2006.260.07:36:30.81#ibcon#read 5, iclass 38, count 2 2006.260.07:36:30.81#ibcon#about to read 6, iclass 38, count 2 2006.260.07:36:30.81#ibcon#read 6, iclass 38, count 2 2006.260.07:36:30.81#ibcon#end of sib2, iclass 38, count 2 2006.260.07:36:30.81#ibcon#*after write, iclass 38, count 2 2006.260.07:36:30.81#ibcon#*before return 0, iclass 38, count 2 2006.260.07:36:30.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:36:30.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:36:30.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.07:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:30.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:36:30.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:36:30.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:36:30.93#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:36:30.93#ibcon#first serial, iclass 38, count 0 2006.260.07:36:30.93#ibcon#enter sib2, iclass 38, count 0 2006.260.07:36:30.93#ibcon#flushed, iclass 38, count 0 2006.260.07:36:30.93#ibcon#about to write, iclass 38, count 0 2006.260.07:36:30.93#ibcon#wrote, iclass 38, count 0 2006.260.07:36:30.93#ibcon#about to read 3, iclass 38, count 0 2006.260.07:36:30.95#ibcon#read 3, iclass 38, count 0 2006.260.07:36:30.95#ibcon#about to read 4, iclass 38, count 0 2006.260.07:36:30.95#ibcon#read 4, iclass 38, count 0 2006.260.07:36:30.95#ibcon#about to read 5, iclass 38, count 0 2006.260.07:36:30.95#ibcon#read 5, iclass 38, count 0 2006.260.07:36:30.95#ibcon#about to read 6, iclass 38, count 0 2006.260.07:36:30.95#ibcon#read 6, iclass 38, count 0 2006.260.07:36:30.95#ibcon#end of sib2, iclass 38, count 0 2006.260.07:36:30.95#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:36:30.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:36:30.95#ibcon#[25=USB\r\n] 2006.260.07:36:30.95#ibcon#*before write, iclass 38, count 0 2006.260.07:36:30.95#ibcon#enter sib2, iclass 38, count 0 2006.260.07:36:30.95#ibcon#flushed, iclass 38, count 0 2006.260.07:36:30.95#ibcon#about to write, iclass 38, count 0 2006.260.07:36:30.95#ibcon#wrote, iclass 38, count 0 2006.260.07:36:30.95#ibcon#about to read 3, iclass 38, count 0 2006.260.07:36:30.98#ibcon#read 3, iclass 38, count 0 2006.260.07:36:30.98#ibcon#about to read 4, iclass 38, count 0 2006.260.07:36:30.98#ibcon#read 4, iclass 38, count 0 2006.260.07:36:30.98#ibcon#about to read 5, iclass 38, count 0 2006.260.07:36:30.98#ibcon#read 5, iclass 38, count 0 2006.260.07:36:30.98#ibcon#about to read 6, iclass 38, count 0 2006.260.07:36:30.98#ibcon#read 6, iclass 38, count 0 2006.260.07:36:30.98#ibcon#end of sib2, iclass 38, count 0 2006.260.07:36:30.98#ibcon#*after write, iclass 38, count 0 2006.260.07:36:30.98#ibcon#*before return 0, iclass 38, count 0 2006.260.07:36:30.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:36:30.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:36:30.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:36:30.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:36:30.98$vc4f8/valo=8,852.99 2006.260.07:36:30.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.07:36:30.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.07:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:30.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:36:30.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:36:30.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:36:30.98#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:36:30.98#ibcon#first serial, iclass 40, count 0 2006.260.07:36:30.98#ibcon#enter sib2, iclass 40, count 0 2006.260.07:36:30.98#ibcon#flushed, iclass 40, count 0 2006.260.07:36:30.98#ibcon#about to write, iclass 40, count 0 2006.260.07:36:30.98#ibcon#wrote, iclass 40, count 0 2006.260.07:36:30.98#ibcon#about to read 3, iclass 40, count 0 2006.260.07:36:31.00#ibcon#read 3, iclass 40, count 0 2006.260.07:36:31.00#ibcon#about to read 4, iclass 40, count 0 2006.260.07:36:31.00#ibcon#read 4, iclass 40, count 0 2006.260.07:36:31.00#ibcon#about to read 5, iclass 40, count 0 2006.260.07:36:31.00#ibcon#read 5, iclass 40, count 0 2006.260.07:36:31.00#ibcon#about to read 6, iclass 40, count 0 2006.260.07:36:31.00#ibcon#read 6, iclass 40, count 0 2006.260.07:36:31.00#ibcon#end of sib2, iclass 40, count 0 2006.260.07:36:31.00#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:36:31.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:36:31.00#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:36:31.00#ibcon#*before write, iclass 40, count 0 2006.260.07:36:31.00#ibcon#enter sib2, iclass 40, count 0 2006.260.07:36:31.00#ibcon#flushed, iclass 40, count 0 2006.260.07:36:31.00#ibcon#about to write, iclass 40, count 0 2006.260.07:36:31.00#ibcon#wrote, iclass 40, count 0 2006.260.07:36:31.00#ibcon#about to read 3, iclass 40, count 0 2006.260.07:36:31.04#ibcon#read 3, iclass 40, count 0 2006.260.07:36:31.04#ibcon#about to read 4, iclass 40, count 0 2006.260.07:36:31.04#ibcon#read 4, iclass 40, count 0 2006.260.07:36:31.04#ibcon#about to read 5, iclass 40, count 0 2006.260.07:36:31.04#ibcon#read 5, iclass 40, count 0 2006.260.07:36:31.04#ibcon#about to read 6, iclass 40, count 0 2006.260.07:36:31.04#ibcon#read 6, iclass 40, count 0 2006.260.07:36:31.04#ibcon#end of sib2, iclass 40, count 0 2006.260.07:36:31.04#ibcon#*after write, iclass 40, count 0 2006.260.07:36:31.04#ibcon#*before return 0, iclass 40, count 0 2006.260.07:36:31.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:36:31.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:36:31.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:36:31.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:36:31.04$vc4f8/va=8,6 2006.260.07:36:31.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.07:36:31.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.07:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:31.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:36:31.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:36:31.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:36:31.10#ibcon#enter wrdev, iclass 4, count 2 2006.260.07:36:31.10#ibcon#first serial, iclass 4, count 2 2006.260.07:36:31.10#ibcon#enter sib2, iclass 4, count 2 2006.260.07:36:31.10#ibcon#flushed, iclass 4, count 2 2006.260.07:36:31.10#ibcon#about to write, iclass 4, count 2 2006.260.07:36:31.10#ibcon#wrote, iclass 4, count 2 2006.260.07:36:31.10#ibcon#about to read 3, iclass 4, count 2 2006.260.07:36:31.12#ibcon#read 3, iclass 4, count 2 2006.260.07:36:31.12#ibcon#about to read 4, iclass 4, count 2 2006.260.07:36:31.12#ibcon#read 4, iclass 4, count 2 2006.260.07:36:31.12#ibcon#about to read 5, iclass 4, count 2 2006.260.07:36:31.12#ibcon#read 5, iclass 4, count 2 2006.260.07:36:31.12#ibcon#about to read 6, iclass 4, count 2 2006.260.07:36:31.12#ibcon#read 6, iclass 4, count 2 2006.260.07:36:31.12#ibcon#end of sib2, iclass 4, count 2 2006.260.07:36:31.12#ibcon#*mode == 0, iclass 4, count 2 2006.260.07:36:31.12#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.07:36:31.12#ibcon#[25=AT08-06\r\n] 2006.260.07:36:31.12#ibcon#*before write, iclass 4, count 2 2006.260.07:36:31.12#ibcon#enter sib2, iclass 4, count 2 2006.260.07:36:31.12#ibcon#flushed, iclass 4, count 2 2006.260.07:36:31.12#ibcon#about to write, iclass 4, count 2 2006.260.07:36:31.12#ibcon#wrote, iclass 4, count 2 2006.260.07:36:31.12#ibcon#about to read 3, iclass 4, count 2 2006.260.07:36:31.15#ibcon#read 3, iclass 4, count 2 2006.260.07:36:31.15#ibcon#about to read 4, iclass 4, count 2 2006.260.07:36:31.15#ibcon#read 4, iclass 4, count 2 2006.260.07:36:31.15#ibcon#about to read 5, iclass 4, count 2 2006.260.07:36:31.15#ibcon#read 5, iclass 4, count 2 2006.260.07:36:31.15#ibcon#about to read 6, iclass 4, count 2 2006.260.07:36:31.15#ibcon#read 6, iclass 4, count 2 2006.260.07:36:31.15#ibcon#end of sib2, iclass 4, count 2 2006.260.07:36:31.15#ibcon#*after write, iclass 4, count 2 2006.260.07:36:31.15#ibcon#*before return 0, iclass 4, count 2 2006.260.07:36:31.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:36:31.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:36:31.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.07:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:31.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:36:31.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:36:31.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:36:31.27#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:36:31.27#ibcon#first serial, iclass 4, count 0 2006.260.07:36:31.27#ibcon#enter sib2, iclass 4, count 0 2006.260.07:36:31.27#ibcon#flushed, iclass 4, count 0 2006.260.07:36:31.27#ibcon#about to write, iclass 4, count 0 2006.260.07:36:31.27#ibcon#wrote, iclass 4, count 0 2006.260.07:36:31.27#ibcon#about to read 3, iclass 4, count 0 2006.260.07:36:31.29#ibcon#read 3, iclass 4, count 0 2006.260.07:36:31.29#ibcon#about to read 4, iclass 4, count 0 2006.260.07:36:31.29#ibcon#read 4, iclass 4, count 0 2006.260.07:36:31.29#ibcon#about to read 5, iclass 4, count 0 2006.260.07:36:31.29#ibcon#read 5, iclass 4, count 0 2006.260.07:36:31.29#ibcon#about to read 6, iclass 4, count 0 2006.260.07:36:31.29#ibcon#read 6, iclass 4, count 0 2006.260.07:36:31.29#ibcon#end of sib2, iclass 4, count 0 2006.260.07:36:31.29#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:36:31.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:36:31.29#ibcon#[25=USB\r\n] 2006.260.07:36:31.29#ibcon#*before write, iclass 4, count 0 2006.260.07:36:31.29#ibcon#enter sib2, iclass 4, count 0 2006.260.07:36:31.29#ibcon#flushed, iclass 4, count 0 2006.260.07:36:31.29#ibcon#about to write, iclass 4, count 0 2006.260.07:36:31.29#ibcon#wrote, iclass 4, count 0 2006.260.07:36:31.29#ibcon#about to read 3, iclass 4, count 0 2006.260.07:36:31.32#ibcon#read 3, iclass 4, count 0 2006.260.07:36:31.32#ibcon#about to read 4, iclass 4, count 0 2006.260.07:36:31.32#ibcon#read 4, iclass 4, count 0 2006.260.07:36:31.32#ibcon#about to read 5, iclass 4, count 0 2006.260.07:36:31.32#ibcon#read 5, iclass 4, count 0 2006.260.07:36:31.32#ibcon#about to read 6, iclass 4, count 0 2006.260.07:36:31.32#ibcon#read 6, iclass 4, count 0 2006.260.07:36:31.32#ibcon#end of sib2, iclass 4, count 0 2006.260.07:36:31.32#ibcon#*after write, iclass 4, count 0 2006.260.07:36:31.32#ibcon#*before return 0, iclass 4, count 0 2006.260.07:36:31.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:36:31.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:36:31.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:36:31.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:36:31.32$vc4f8/vblo=1,632.99 2006.260.07:36:31.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.07:36:31.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.07:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:31.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:36:31.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:36:31.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:36:31.32#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:36:31.32#ibcon#first serial, iclass 6, count 0 2006.260.07:36:31.32#ibcon#enter sib2, iclass 6, count 0 2006.260.07:36:31.32#ibcon#flushed, iclass 6, count 0 2006.260.07:36:31.32#ibcon#about to write, iclass 6, count 0 2006.260.07:36:31.32#ibcon#wrote, iclass 6, count 0 2006.260.07:36:31.32#ibcon#about to read 3, iclass 6, count 0 2006.260.07:36:31.34#ibcon#read 3, iclass 6, count 0 2006.260.07:36:31.34#ibcon#about to read 4, iclass 6, count 0 2006.260.07:36:31.34#ibcon#read 4, iclass 6, count 0 2006.260.07:36:31.34#ibcon#about to read 5, iclass 6, count 0 2006.260.07:36:31.34#ibcon#read 5, iclass 6, count 0 2006.260.07:36:31.34#ibcon#about to read 6, iclass 6, count 0 2006.260.07:36:31.34#ibcon#read 6, iclass 6, count 0 2006.260.07:36:31.34#ibcon#end of sib2, iclass 6, count 0 2006.260.07:36:31.34#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:36:31.34#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:36:31.34#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:36:31.34#ibcon#*before write, iclass 6, count 0 2006.260.07:36:31.34#ibcon#enter sib2, iclass 6, count 0 2006.260.07:36:31.34#ibcon#flushed, iclass 6, count 0 2006.260.07:36:31.34#ibcon#about to write, iclass 6, count 0 2006.260.07:36:31.34#ibcon#wrote, iclass 6, count 0 2006.260.07:36:31.34#ibcon#about to read 3, iclass 6, count 0 2006.260.07:36:31.38#ibcon#read 3, iclass 6, count 0 2006.260.07:36:31.38#ibcon#about to read 4, iclass 6, count 0 2006.260.07:36:31.38#ibcon#read 4, iclass 6, count 0 2006.260.07:36:31.38#ibcon#about to read 5, iclass 6, count 0 2006.260.07:36:31.38#ibcon#read 5, iclass 6, count 0 2006.260.07:36:31.38#ibcon#about to read 6, iclass 6, count 0 2006.260.07:36:31.38#ibcon#read 6, iclass 6, count 0 2006.260.07:36:31.38#ibcon#end of sib2, iclass 6, count 0 2006.260.07:36:31.38#ibcon#*after write, iclass 6, count 0 2006.260.07:36:31.38#ibcon#*before return 0, iclass 6, count 0 2006.260.07:36:31.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:36:31.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:36:31.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:36:31.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:36:31.38$vc4f8/vb=1,4 2006.260.07:36:31.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.07:36:31.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.07:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:31.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:36:31.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:36:31.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:36:31.38#ibcon#enter wrdev, iclass 10, count 2 2006.260.07:36:31.38#ibcon#first serial, iclass 10, count 2 2006.260.07:36:31.38#ibcon#enter sib2, iclass 10, count 2 2006.260.07:36:31.38#ibcon#flushed, iclass 10, count 2 2006.260.07:36:31.38#ibcon#about to write, iclass 10, count 2 2006.260.07:36:31.38#ibcon#wrote, iclass 10, count 2 2006.260.07:36:31.38#ibcon#about to read 3, iclass 10, count 2 2006.260.07:36:31.40#ibcon#read 3, iclass 10, count 2 2006.260.07:36:31.40#ibcon#about to read 4, iclass 10, count 2 2006.260.07:36:31.40#ibcon#read 4, iclass 10, count 2 2006.260.07:36:31.40#ibcon#about to read 5, iclass 10, count 2 2006.260.07:36:31.40#ibcon#read 5, iclass 10, count 2 2006.260.07:36:31.40#ibcon#about to read 6, iclass 10, count 2 2006.260.07:36:31.40#ibcon#read 6, iclass 10, count 2 2006.260.07:36:31.40#ibcon#end of sib2, iclass 10, count 2 2006.260.07:36:31.40#ibcon#*mode == 0, iclass 10, count 2 2006.260.07:36:31.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.07:36:31.40#ibcon#[27=AT01-04\r\n] 2006.260.07:36:31.40#ibcon#*before write, iclass 10, count 2 2006.260.07:36:31.40#ibcon#enter sib2, iclass 10, count 2 2006.260.07:36:31.40#ibcon#flushed, iclass 10, count 2 2006.260.07:36:31.40#ibcon#about to write, iclass 10, count 2 2006.260.07:36:31.40#ibcon#wrote, iclass 10, count 2 2006.260.07:36:31.40#ibcon#about to read 3, iclass 10, count 2 2006.260.07:36:31.43#ibcon#read 3, iclass 10, count 2 2006.260.07:36:31.43#ibcon#about to read 4, iclass 10, count 2 2006.260.07:36:31.43#ibcon#read 4, iclass 10, count 2 2006.260.07:36:31.43#ibcon#about to read 5, iclass 10, count 2 2006.260.07:36:31.43#ibcon#read 5, iclass 10, count 2 2006.260.07:36:31.43#ibcon#about to read 6, iclass 10, count 2 2006.260.07:36:31.43#ibcon#read 6, iclass 10, count 2 2006.260.07:36:31.43#ibcon#end of sib2, iclass 10, count 2 2006.260.07:36:31.43#ibcon#*after write, iclass 10, count 2 2006.260.07:36:31.43#ibcon#*before return 0, iclass 10, count 2 2006.260.07:36:31.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:36:31.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:36:31.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.07:36:31.43#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:31.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:36:31.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:36:31.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:36:31.55#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:36:31.55#ibcon#first serial, iclass 10, count 0 2006.260.07:36:31.55#ibcon#enter sib2, iclass 10, count 0 2006.260.07:36:31.55#ibcon#flushed, iclass 10, count 0 2006.260.07:36:31.55#ibcon#about to write, iclass 10, count 0 2006.260.07:36:31.55#ibcon#wrote, iclass 10, count 0 2006.260.07:36:31.55#ibcon#about to read 3, iclass 10, count 0 2006.260.07:36:31.57#ibcon#read 3, iclass 10, count 0 2006.260.07:36:31.57#ibcon#about to read 4, iclass 10, count 0 2006.260.07:36:31.57#ibcon#read 4, iclass 10, count 0 2006.260.07:36:31.57#ibcon#about to read 5, iclass 10, count 0 2006.260.07:36:31.57#ibcon#read 5, iclass 10, count 0 2006.260.07:36:31.57#ibcon#about to read 6, iclass 10, count 0 2006.260.07:36:31.57#ibcon#read 6, iclass 10, count 0 2006.260.07:36:31.57#ibcon#end of sib2, iclass 10, count 0 2006.260.07:36:31.57#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:36:31.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:36:31.57#ibcon#[27=USB\r\n] 2006.260.07:36:31.57#ibcon#*before write, iclass 10, count 0 2006.260.07:36:31.57#ibcon#enter sib2, iclass 10, count 0 2006.260.07:36:31.57#ibcon#flushed, iclass 10, count 0 2006.260.07:36:31.57#ibcon#about to write, iclass 10, count 0 2006.260.07:36:31.57#ibcon#wrote, iclass 10, count 0 2006.260.07:36:31.57#ibcon#about to read 3, iclass 10, count 0 2006.260.07:36:31.60#ibcon#read 3, iclass 10, count 0 2006.260.07:36:31.60#ibcon#about to read 4, iclass 10, count 0 2006.260.07:36:31.60#ibcon#read 4, iclass 10, count 0 2006.260.07:36:31.60#ibcon#about to read 5, iclass 10, count 0 2006.260.07:36:31.60#ibcon#read 5, iclass 10, count 0 2006.260.07:36:31.60#ibcon#about to read 6, iclass 10, count 0 2006.260.07:36:31.60#ibcon#read 6, iclass 10, count 0 2006.260.07:36:31.60#ibcon#end of sib2, iclass 10, count 0 2006.260.07:36:31.60#ibcon#*after write, iclass 10, count 0 2006.260.07:36:31.60#ibcon#*before return 0, iclass 10, count 0 2006.260.07:36:31.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:36:31.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:36:31.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:36:31.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:36:31.60$vc4f8/vblo=2,640.99 2006.260.07:36:31.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:36:31.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:36:31.60#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:31.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:31.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:31.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:31.60#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:36:31.60#ibcon#first serial, iclass 12, count 0 2006.260.07:36:31.60#ibcon#enter sib2, iclass 12, count 0 2006.260.07:36:31.60#ibcon#flushed, iclass 12, count 0 2006.260.07:36:31.60#ibcon#about to write, iclass 12, count 0 2006.260.07:36:31.60#ibcon#wrote, iclass 12, count 0 2006.260.07:36:31.60#ibcon#about to read 3, iclass 12, count 0 2006.260.07:36:31.62#ibcon#read 3, iclass 12, count 0 2006.260.07:36:31.62#ibcon#about to read 4, iclass 12, count 0 2006.260.07:36:31.62#ibcon#read 4, iclass 12, count 0 2006.260.07:36:31.62#ibcon#about to read 5, iclass 12, count 0 2006.260.07:36:31.62#ibcon#read 5, iclass 12, count 0 2006.260.07:36:31.62#ibcon#about to read 6, iclass 12, count 0 2006.260.07:36:31.62#ibcon#read 6, iclass 12, count 0 2006.260.07:36:31.62#ibcon#end of sib2, iclass 12, count 0 2006.260.07:36:31.62#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:36:31.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:36:31.62#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:36:31.62#ibcon#*before write, iclass 12, count 0 2006.260.07:36:31.62#ibcon#enter sib2, iclass 12, count 0 2006.260.07:36:31.62#ibcon#flushed, iclass 12, count 0 2006.260.07:36:31.62#ibcon#about to write, iclass 12, count 0 2006.260.07:36:31.62#ibcon#wrote, iclass 12, count 0 2006.260.07:36:31.62#ibcon#about to read 3, iclass 12, count 0 2006.260.07:36:31.66#ibcon#read 3, iclass 12, count 0 2006.260.07:36:31.66#ibcon#about to read 4, iclass 12, count 0 2006.260.07:36:31.66#ibcon#read 4, iclass 12, count 0 2006.260.07:36:31.66#ibcon#about to read 5, iclass 12, count 0 2006.260.07:36:31.66#ibcon#read 5, iclass 12, count 0 2006.260.07:36:31.66#ibcon#about to read 6, iclass 12, count 0 2006.260.07:36:31.66#ibcon#read 6, iclass 12, count 0 2006.260.07:36:31.66#ibcon#end of sib2, iclass 12, count 0 2006.260.07:36:31.66#ibcon#*after write, iclass 12, count 0 2006.260.07:36:31.66#ibcon#*before return 0, iclass 12, count 0 2006.260.07:36:31.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:31.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:36:31.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:36:31.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:36:31.66$vc4f8/vb=2,5 2006.260.07:36:31.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:36:31.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:36:31.66#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:31.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:31.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:31.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:31.72#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:36:31.72#ibcon#first serial, iclass 14, count 2 2006.260.07:36:31.72#ibcon#enter sib2, iclass 14, count 2 2006.260.07:36:31.72#ibcon#flushed, iclass 14, count 2 2006.260.07:36:31.72#ibcon#about to write, iclass 14, count 2 2006.260.07:36:31.72#ibcon#wrote, iclass 14, count 2 2006.260.07:36:31.72#ibcon#about to read 3, iclass 14, count 2 2006.260.07:36:31.74#ibcon#read 3, iclass 14, count 2 2006.260.07:36:31.74#ibcon#about to read 4, iclass 14, count 2 2006.260.07:36:31.74#ibcon#read 4, iclass 14, count 2 2006.260.07:36:31.74#ibcon#about to read 5, iclass 14, count 2 2006.260.07:36:31.74#ibcon#read 5, iclass 14, count 2 2006.260.07:36:31.74#ibcon#about to read 6, iclass 14, count 2 2006.260.07:36:31.74#ibcon#read 6, iclass 14, count 2 2006.260.07:36:31.74#ibcon#end of sib2, iclass 14, count 2 2006.260.07:36:31.74#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:36:31.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:36:31.74#ibcon#[27=AT02-05\r\n] 2006.260.07:36:31.74#ibcon#*before write, iclass 14, count 2 2006.260.07:36:31.74#ibcon#enter sib2, iclass 14, count 2 2006.260.07:36:31.74#ibcon#flushed, iclass 14, count 2 2006.260.07:36:31.74#ibcon#about to write, iclass 14, count 2 2006.260.07:36:31.74#ibcon#wrote, iclass 14, count 2 2006.260.07:36:31.74#ibcon#about to read 3, iclass 14, count 2 2006.260.07:36:31.77#ibcon#read 3, iclass 14, count 2 2006.260.07:36:31.77#ibcon#about to read 4, iclass 14, count 2 2006.260.07:36:31.77#ibcon#read 4, iclass 14, count 2 2006.260.07:36:31.77#ibcon#about to read 5, iclass 14, count 2 2006.260.07:36:31.77#ibcon#read 5, iclass 14, count 2 2006.260.07:36:31.77#ibcon#about to read 6, iclass 14, count 2 2006.260.07:36:31.77#ibcon#read 6, iclass 14, count 2 2006.260.07:36:31.77#ibcon#end of sib2, iclass 14, count 2 2006.260.07:36:31.77#ibcon#*after write, iclass 14, count 2 2006.260.07:36:31.77#ibcon#*before return 0, iclass 14, count 2 2006.260.07:36:31.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:31.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:36:31.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:36:31.77#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:31.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:31.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:31.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:31.89#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:36:31.89#ibcon#first serial, iclass 14, count 0 2006.260.07:36:31.89#ibcon#enter sib2, iclass 14, count 0 2006.260.07:36:31.89#ibcon#flushed, iclass 14, count 0 2006.260.07:36:31.89#ibcon#about to write, iclass 14, count 0 2006.260.07:36:31.89#ibcon#wrote, iclass 14, count 0 2006.260.07:36:31.89#ibcon#about to read 3, iclass 14, count 0 2006.260.07:36:31.91#ibcon#read 3, iclass 14, count 0 2006.260.07:36:31.91#ibcon#about to read 4, iclass 14, count 0 2006.260.07:36:31.91#ibcon#read 4, iclass 14, count 0 2006.260.07:36:31.91#ibcon#about to read 5, iclass 14, count 0 2006.260.07:36:31.91#ibcon#read 5, iclass 14, count 0 2006.260.07:36:31.91#ibcon#about to read 6, iclass 14, count 0 2006.260.07:36:31.91#ibcon#read 6, iclass 14, count 0 2006.260.07:36:31.91#ibcon#end of sib2, iclass 14, count 0 2006.260.07:36:31.91#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:36:31.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:36:31.91#ibcon#[27=USB\r\n] 2006.260.07:36:31.91#ibcon#*before write, iclass 14, count 0 2006.260.07:36:31.91#ibcon#enter sib2, iclass 14, count 0 2006.260.07:36:31.91#ibcon#flushed, iclass 14, count 0 2006.260.07:36:31.91#ibcon#about to write, iclass 14, count 0 2006.260.07:36:31.91#ibcon#wrote, iclass 14, count 0 2006.260.07:36:31.91#ibcon#about to read 3, iclass 14, count 0 2006.260.07:36:31.94#ibcon#read 3, iclass 14, count 0 2006.260.07:36:31.94#ibcon#about to read 4, iclass 14, count 0 2006.260.07:36:31.94#ibcon#read 4, iclass 14, count 0 2006.260.07:36:31.94#ibcon#about to read 5, iclass 14, count 0 2006.260.07:36:31.94#ibcon#read 5, iclass 14, count 0 2006.260.07:36:31.94#ibcon#about to read 6, iclass 14, count 0 2006.260.07:36:31.94#ibcon#read 6, iclass 14, count 0 2006.260.07:36:31.94#ibcon#end of sib2, iclass 14, count 0 2006.260.07:36:31.94#ibcon#*after write, iclass 14, count 0 2006.260.07:36:31.94#ibcon#*before return 0, iclass 14, count 0 2006.260.07:36:31.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:31.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:36:31.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:36:31.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:36:31.94$vc4f8/vblo=3,656.99 2006.260.07:36:31.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:36:31.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:36:31.94#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:31.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:31.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:31.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:31.94#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:36:31.94#ibcon#first serial, iclass 16, count 0 2006.260.07:36:31.94#ibcon#enter sib2, iclass 16, count 0 2006.260.07:36:31.94#ibcon#flushed, iclass 16, count 0 2006.260.07:36:31.94#ibcon#about to write, iclass 16, count 0 2006.260.07:36:31.94#ibcon#wrote, iclass 16, count 0 2006.260.07:36:31.94#ibcon#about to read 3, iclass 16, count 0 2006.260.07:36:31.97#ibcon#read 3, iclass 16, count 0 2006.260.07:36:31.97#ibcon#about to read 4, iclass 16, count 0 2006.260.07:36:31.97#ibcon#read 4, iclass 16, count 0 2006.260.07:36:31.97#ibcon#about to read 5, iclass 16, count 0 2006.260.07:36:31.97#ibcon#read 5, iclass 16, count 0 2006.260.07:36:31.97#ibcon#about to read 6, iclass 16, count 0 2006.260.07:36:31.97#ibcon#read 6, iclass 16, count 0 2006.260.07:36:31.97#ibcon#end of sib2, iclass 16, count 0 2006.260.07:36:31.97#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:36:31.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:36:31.97#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:36:31.97#ibcon#*before write, iclass 16, count 0 2006.260.07:36:31.97#ibcon#enter sib2, iclass 16, count 0 2006.260.07:36:31.97#ibcon#flushed, iclass 16, count 0 2006.260.07:36:31.97#ibcon#about to write, iclass 16, count 0 2006.260.07:36:31.97#ibcon#wrote, iclass 16, count 0 2006.260.07:36:31.97#ibcon#about to read 3, iclass 16, count 0 2006.260.07:36:32.01#ibcon#read 3, iclass 16, count 0 2006.260.07:36:32.01#ibcon#about to read 4, iclass 16, count 0 2006.260.07:36:32.01#ibcon#read 4, iclass 16, count 0 2006.260.07:36:32.01#ibcon#about to read 5, iclass 16, count 0 2006.260.07:36:32.01#ibcon#read 5, iclass 16, count 0 2006.260.07:36:32.01#ibcon#about to read 6, iclass 16, count 0 2006.260.07:36:32.01#ibcon#read 6, iclass 16, count 0 2006.260.07:36:32.01#ibcon#end of sib2, iclass 16, count 0 2006.260.07:36:32.01#ibcon#*after write, iclass 16, count 0 2006.260.07:36:32.01#ibcon#*before return 0, iclass 16, count 0 2006.260.07:36:32.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:32.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:36:32.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:36:32.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:36:32.01$vc4f8/vb=3,4 2006.260.07:36:32.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:36:32.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:36:32.01#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:32.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:32.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:32.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:32.06#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:36:32.06#ibcon#first serial, iclass 18, count 2 2006.260.07:36:32.06#ibcon#enter sib2, iclass 18, count 2 2006.260.07:36:32.06#ibcon#flushed, iclass 18, count 2 2006.260.07:36:32.06#ibcon#about to write, iclass 18, count 2 2006.260.07:36:32.06#ibcon#wrote, iclass 18, count 2 2006.260.07:36:32.06#ibcon#about to read 3, iclass 18, count 2 2006.260.07:36:32.08#ibcon#read 3, iclass 18, count 2 2006.260.07:36:32.08#ibcon#about to read 4, iclass 18, count 2 2006.260.07:36:32.08#ibcon#read 4, iclass 18, count 2 2006.260.07:36:32.08#ibcon#about to read 5, iclass 18, count 2 2006.260.07:36:32.08#ibcon#read 5, iclass 18, count 2 2006.260.07:36:32.08#ibcon#about to read 6, iclass 18, count 2 2006.260.07:36:32.08#ibcon#read 6, iclass 18, count 2 2006.260.07:36:32.08#ibcon#end of sib2, iclass 18, count 2 2006.260.07:36:32.08#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:36:32.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:36:32.08#ibcon#[27=AT03-04\r\n] 2006.260.07:36:32.08#ibcon#*before write, iclass 18, count 2 2006.260.07:36:32.08#ibcon#enter sib2, iclass 18, count 2 2006.260.07:36:32.08#ibcon#flushed, iclass 18, count 2 2006.260.07:36:32.08#ibcon#about to write, iclass 18, count 2 2006.260.07:36:32.08#ibcon#wrote, iclass 18, count 2 2006.260.07:36:32.08#ibcon#about to read 3, iclass 18, count 2 2006.260.07:36:32.11#ibcon#read 3, iclass 18, count 2 2006.260.07:36:32.11#ibcon#about to read 4, iclass 18, count 2 2006.260.07:36:32.11#ibcon#read 4, iclass 18, count 2 2006.260.07:36:32.11#ibcon#about to read 5, iclass 18, count 2 2006.260.07:36:32.11#ibcon#read 5, iclass 18, count 2 2006.260.07:36:32.11#ibcon#about to read 6, iclass 18, count 2 2006.260.07:36:32.11#ibcon#read 6, iclass 18, count 2 2006.260.07:36:32.11#ibcon#end of sib2, iclass 18, count 2 2006.260.07:36:32.11#ibcon#*after write, iclass 18, count 2 2006.260.07:36:32.11#ibcon#*before return 0, iclass 18, count 2 2006.260.07:36:32.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:32.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:36:32.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:36:32.11#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:32.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:32.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:32.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:32.23#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:36:32.23#ibcon#first serial, iclass 18, count 0 2006.260.07:36:32.23#ibcon#enter sib2, iclass 18, count 0 2006.260.07:36:32.23#ibcon#flushed, iclass 18, count 0 2006.260.07:36:32.23#ibcon#about to write, iclass 18, count 0 2006.260.07:36:32.23#ibcon#wrote, iclass 18, count 0 2006.260.07:36:32.23#ibcon#about to read 3, iclass 18, count 0 2006.260.07:36:32.25#ibcon#read 3, iclass 18, count 0 2006.260.07:36:32.25#ibcon#about to read 4, iclass 18, count 0 2006.260.07:36:32.25#ibcon#read 4, iclass 18, count 0 2006.260.07:36:32.25#ibcon#about to read 5, iclass 18, count 0 2006.260.07:36:32.25#ibcon#read 5, iclass 18, count 0 2006.260.07:36:32.25#ibcon#about to read 6, iclass 18, count 0 2006.260.07:36:32.25#ibcon#read 6, iclass 18, count 0 2006.260.07:36:32.25#ibcon#end of sib2, iclass 18, count 0 2006.260.07:36:32.25#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:36:32.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:36:32.25#ibcon#[27=USB\r\n] 2006.260.07:36:32.25#ibcon#*before write, iclass 18, count 0 2006.260.07:36:32.25#ibcon#enter sib2, iclass 18, count 0 2006.260.07:36:32.25#ibcon#flushed, iclass 18, count 0 2006.260.07:36:32.25#ibcon#about to write, iclass 18, count 0 2006.260.07:36:32.25#ibcon#wrote, iclass 18, count 0 2006.260.07:36:32.25#ibcon#about to read 3, iclass 18, count 0 2006.260.07:36:32.28#ibcon#read 3, iclass 18, count 0 2006.260.07:36:32.28#ibcon#about to read 4, iclass 18, count 0 2006.260.07:36:32.28#ibcon#read 4, iclass 18, count 0 2006.260.07:36:32.28#ibcon#about to read 5, iclass 18, count 0 2006.260.07:36:32.28#ibcon#read 5, iclass 18, count 0 2006.260.07:36:32.28#ibcon#about to read 6, iclass 18, count 0 2006.260.07:36:32.28#ibcon#read 6, iclass 18, count 0 2006.260.07:36:32.28#ibcon#end of sib2, iclass 18, count 0 2006.260.07:36:32.28#ibcon#*after write, iclass 18, count 0 2006.260.07:36:32.28#ibcon#*before return 0, iclass 18, count 0 2006.260.07:36:32.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:32.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:36:32.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:36:32.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:36:32.28$vc4f8/vblo=4,712.99 2006.260.07:36:32.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:36:32.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:36:32.28#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:32.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:32.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:32.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:32.28#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:36:32.28#ibcon#first serial, iclass 20, count 0 2006.260.07:36:32.28#ibcon#enter sib2, iclass 20, count 0 2006.260.07:36:32.28#ibcon#flushed, iclass 20, count 0 2006.260.07:36:32.28#ibcon#about to write, iclass 20, count 0 2006.260.07:36:32.28#ibcon#wrote, iclass 20, count 0 2006.260.07:36:32.28#ibcon#about to read 3, iclass 20, count 0 2006.260.07:36:32.30#ibcon#read 3, iclass 20, count 0 2006.260.07:36:32.30#ibcon#about to read 4, iclass 20, count 0 2006.260.07:36:32.30#ibcon#read 4, iclass 20, count 0 2006.260.07:36:32.30#ibcon#about to read 5, iclass 20, count 0 2006.260.07:36:32.30#ibcon#read 5, iclass 20, count 0 2006.260.07:36:32.30#ibcon#about to read 6, iclass 20, count 0 2006.260.07:36:32.30#ibcon#read 6, iclass 20, count 0 2006.260.07:36:32.30#ibcon#end of sib2, iclass 20, count 0 2006.260.07:36:32.30#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:36:32.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:36:32.30#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:36:32.30#ibcon#*before write, iclass 20, count 0 2006.260.07:36:32.30#ibcon#enter sib2, iclass 20, count 0 2006.260.07:36:32.30#ibcon#flushed, iclass 20, count 0 2006.260.07:36:32.30#ibcon#about to write, iclass 20, count 0 2006.260.07:36:32.30#ibcon#wrote, iclass 20, count 0 2006.260.07:36:32.30#ibcon#about to read 3, iclass 20, count 0 2006.260.07:36:32.34#ibcon#read 3, iclass 20, count 0 2006.260.07:36:32.34#ibcon#about to read 4, iclass 20, count 0 2006.260.07:36:32.34#ibcon#read 4, iclass 20, count 0 2006.260.07:36:32.34#ibcon#about to read 5, iclass 20, count 0 2006.260.07:36:32.34#ibcon#read 5, iclass 20, count 0 2006.260.07:36:32.34#ibcon#about to read 6, iclass 20, count 0 2006.260.07:36:32.34#ibcon#read 6, iclass 20, count 0 2006.260.07:36:32.34#ibcon#end of sib2, iclass 20, count 0 2006.260.07:36:32.34#ibcon#*after write, iclass 20, count 0 2006.260.07:36:32.34#ibcon#*before return 0, iclass 20, count 0 2006.260.07:36:32.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:32.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:36:32.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:36:32.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:36:32.34$vc4f8/vb=4,5 2006.260.07:36:32.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:36:32.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:36:32.34#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:32.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:32.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:32.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:32.40#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:36:32.40#ibcon#first serial, iclass 22, count 2 2006.260.07:36:32.40#ibcon#enter sib2, iclass 22, count 2 2006.260.07:36:32.40#ibcon#flushed, iclass 22, count 2 2006.260.07:36:32.40#ibcon#about to write, iclass 22, count 2 2006.260.07:36:32.40#ibcon#wrote, iclass 22, count 2 2006.260.07:36:32.40#ibcon#about to read 3, iclass 22, count 2 2006.260.07:36:32.42#ibcon#read 3, iclass 22, count 2 2006.260.07:36:32.42#ibcon#about to read 4, iclass 22, count 2 2006.260.07:36:32.42#ibcon#read 4, iclass 22, count 2 2006.260.07:36:32.42#ibcon#about to read 5, iclass 22, count 2 2006.260.07:36:32.42#ibcon#read 5, iclass 22, count 2 2006.260.07:36:32.42#ibcon#about to read 6, iclass 22, count 2 2006.260.07:36:32.42#ibcon#read 6, iclass 22, count 2 2006.260.07:36:32.42#ibcon#end of sib2, iclass 22, count 2 2006.260.07:36:32.42#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:36:32.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:36:32.42#ibcon#[27=AT04-05\r\n] 2006.260.07:36:32.42#ibcon#*before write, iclass 22, count 2 2006.260.07:36:32.42#ibcon#enter sib2, iclass 22, count 2 2006.260.07:36:32.42#ibcon#flushed, iclass 22, count 2 2006.260.07:36:32.42#ibcon#about to write, iclass 22, count 2 2006.260.07:36:32.42#ibcon#wrote, iclass 22, count 2 2006.260.07:36:32.42#ibcon#about to read 3, iclass 22, count 2 2006.260.07:36:32.45#ibcon#read 3, iclass 22, count 2 2006.260.07:36:32.45#ibcon#about to read 4, iclass 22, count 2 2006.260.07:36:32.45#ibcon#read 4, iclass 22, count 2 2006.260.07:36:32.45#ibcon#about to read 5, iclass 22, count 2 2006.260.07:36:32.45#ibcon#read 5, iclass 22, count 2 2006.260.07:36:32.45#ibcon#about to read 6, iclass 22, count 2 2006.260.07:36:32.45#ibcon#read 6, iclass 22, count 2 2006.260.07:36:32.45#ibcon#end of sib2, iclass 22, count 2 2006.260.07:36:32.45#ibcon#*after write, iclass 22, count 2 2006.260.07:36:32.45#ibcon#*before return 0, iclass 22, count 2 2006.260.07:36:32.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:32.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:36:32.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:36:32.45#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:32.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:32.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:32.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:32.57#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:36:32.57#ibcon#first serial, iclass 22, count 0 2006.260.07:36:32.57#ibcon#enter sib2, iclass 22, count 0 2006.260.07:36:32.57#ibcon#flushed, iclass 22, count 0 2006.260.07:36:32.57#ibcon#about to write, iclass 22, count 0 2006.260.07:36:32.57#ibcon#wrote, iclass 22, count 0 2006.260.07:36:32.57#ibcon#about to read 3, iclass 22, count 0 2006.260.07:36:32.59#ibcon#read 3, iclass 22, count 0 2006.260.07:36:32.59#ibcon#about to read 4, iclass 22, count 0 2006.260.07:36:32.59#ibcon#read 4, iclass 22, count 0 2006.260.07:36:32.59#ibcon#about to read 5, iclass 22, count 0 2006.260.07:36:32.59#ibcon#read 5, iclass 22, count 0 2006.260.07:36:32.59#ibcon#about to read 6, iclass 22, count 0 2006.260.07:36:32.59#ibcon#read 6, iclass 22, count 0 2006.260.07:36:32.59#ibcon#end of sib2, iclass 22, count 0 2006.260.07:36:32.59#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:36:32.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:36:32.59#ibcon#[27=USB\r\n] 2006.260.07:36:32.59#ibcon#*before write, iclass 22, count 0 2006.260.07:36:32.59#ibcon#enter sib2, iclass 22, count 0 2006.260.07:36:32.59#ibcon#flushed, iclass 22, count 0 2006.260.07:36:32.59#ibcon#about to write, iclass 22, count 0 2006.260.07:36:32.59#ibcon#wrote, iclass 22, count 0 2006.260.07:36:32.59#ibcon#about to read 3, iclass 22, count 0 2006.260.07:36:32.62#ibcon#read 3, iclass 22, count 0 2006.260.07:36:32.62#ibcon#about to read 4, iclass 22, count 0 2006.260.07:36:32.62#ibcon#read 4, iclass 22, count 0 2006.260.07:36:32.62#ibcon#about to read 5, iclass 22, count 0 2006.260.07:36:32.62#ibcon#read 5, iclass 22, count 0 2006.260.07:36:32.62#ibcon#about to read 6, iclass 22, count 0 2006.260.07:36:32.62#ibcon#read 6, iclass 22, count 0 2006.260.07:36:32.62#ibcon#end of sib2, iclass 22, count 0 2006.260.07:36:32.62#ibcon#*after write, iclass 22, count 0 2006.260.07:36:32.62#ibcon#*before return 0, iclass 22, count 0 2006.260.07:36:32.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:32.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:36:32.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:36:32.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:36:32.62$vc4f8/vblo=5,744.99 2006.260.07:36:32.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:36:32.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:36:32.62#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:32.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:32.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:32.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:32.62#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:36:32.62#ibcon#first serial, iclass 24, count 0 2006.260.07:36:32.62#ibcon#enter sib2, iclass 24, count 0 2006.260.07:36:32.62#ibcon#flushed, iclass 24, count 0 2006.260.07:36:32.62#ibcon#about to write, iclass 24, count 0 2006.260.07:36:32.62#ibcon#wrote, iclass 24, count 0 2006.260.07:36:32.62#ibcon#about to read 3, iclass 24, count 0 2006.260.07:36:32.64#ibcon#read 3, iclass 24, count 0 2006.260.07:36:32.64#ibcon#about to read 4, iclass 24, count 0 2006.260.07:36:32.64#ibcon#read 4, iclass 24, count 0 2006.260.07:36:32.64#ibcon#about to read 5, iclass 24, count 0 2006.260.07:36:32.64#ibcon#read 5, iclass 24, count 0 2006.260.07:36:32.64#ibcon#about to read 6, iclass 24, count 0 2006.260.07:36:32.64#ibcon#read 6, iclass 24, count 0 2006.260.07:36:32.64#ibcon#end of sib2, iclass 24, count 0 2006.260.07:36:32.64#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:36:32.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:36:32.64#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:36:32.64#ibcon#*before write, iclass 24, count 0 2006.260.07:36:32.64#ibcon#enter sib2, iclass 24, count 0 2006.260.07:36:32.64#ibcon#flushed, iclass 24, count 0 2006.260.07:36:32.64#ibcon#about to write, iclass 24, count 0 2006.260.07:36:32.64#ibcon#wrote, iclass 24, count 0 2006.260.07:36:32.64#ibcon#about to read 3, iclass 24, count 0 2006.260.07:36:32.68#ibcon#read 3, iclass 24, count 0 2006.260.07:36:32.68#ibcon#about to read 4, iclass 24, count 0 2006.260.07:36:32.68#ibcon#read 4, iclass 24, count 0 2006.260.07:36:32.68#ibcon#about to read 5, iclass 24, count 0 2006.260.07:36:32.68#ibcon#read 5, iclass 24, count 0 2006.260.07:36:32.68#ibcon#about to read 6, iclass 24, count 0 2006.260.07:36:32.68#ibcon#read 6, iclass 24, count 0 2006.260.07:36:32.68#ibcon#end of sib2, iclass 24, count 0 2006.260.07:36:32.68#ibcon#*after write, iclass 24, count 0 2006.260.07:36:32.68#ibcon#*before return 0, iclass 24, count 0 2006.260.07:36:32.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:32.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:36:32.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:36:32.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:36:32.68$vc4f8/vb=5,4 2006.260.07:36:32.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.07:36:32.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.07:36:32.68#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:32.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:32.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:32.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:32.74#ibcon#enter wrdev, iclass 26, count 2 2006.260.07:36:32.74#ibcon#first serial, iclass 26, count 2 2006.260.07:36:32.74#ibcon#enter sib2, iclass 26, count 2 2006.260.07:36:32.74#ibcon#flushed, iclass 26, count 2 2006.260.07:36:32.74#ibcon#about to write, iclass 26, count 2 2006.260.07:36:32.74#ibcon#wrote, iclass 26, count 2 2006.260.07:36:32.74#ibcon#about to read 3, iclass 26, count 2 2006.260.07:36:32.76#ibcon#read 3, iclass 26, count 2 2006.260.07:36:32.76#ibcon#about to read 4, iclass 26, count 2 2006.260.07:36:32.76#ibcon#read 4, iclass 26, count 2 2006.260.07:36:32.76#ibcon#about to read 5, iclass 26, count 2 2006.260.07:36:32.76#ibcon#read 5, iclass 26, count 2 2006.260.07:36:32.76#ibcon#about to read 6, iclass 26, count 2 2006.260.07:36:32.76#ibcon#read 6, iclass 26, count 2 2006.260.07:36:32.76#ibcon#end of sib2, iclass 26, count 2 2006.260.07:36:32.76#ibcon#*mode == 0, iclass 26, count 2 2006.260.07:36:32.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.07:36:32.76#ibcon#[27=AT05-04\r\n] 2006.260.07:36:32.76#ibcon#*before write, iclass 26, count 2 2006.260.07:36:32.76#ibcon#enter sib2, iclass 26, count 2 2006.260.07:36:32.76#ibcon#flushed, iclass 26, count 2 2006.260.07:36:32.76#ibcon#about to write, iclass 26, count 2 2006.260.07:36:32.76#ibcon#wrote, iclass 26, count 2 2006.260.07:36:32.76#ibcon#about to read 3, iclass 26, count 2 2006.260.07:36:32.79#ibcon#read 3, iclass 26, count 2 2006.260.07:36:32.79#ibcon#about to read 4, iclass 26, count 2 2006.260.07:36:32.79#ibcon#read 4, iclass 26, count 2 2006.260.07:36:32.79#ibcon#about to read 5, iclass 26, count 2 2006.260.07:36:32.79#ibcon#read 5, iclass 26, count 2 2006.260.07:36:32.79#ibcon#about to read 6, iclass 26, count 2 2006.260.07:36:32.79#ibcon#read 6, iclass 26, count 2 2006.260.07:36:32.79#ibcon#end of sib2, iclass 26, count 2 2006.260.07:36:32.79#ibcon#*after write, iclass 26, count 2 2006.260.07:36:32.79#ibcon#*before return 0, iclass 26, count 2 2006.260.07:36:32.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:32.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:36:32.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.07:36:32.79#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:32.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:32.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:32.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:32.91#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:36:32.91#ibcon#first serial, iclass 26, count 0 2006.260.07:36:32.91#ibcon#enter sib2, iclass 26, count 0 2006.260.07:36:32.91#ibcon#flushed, iclass 26, count 0 2006.260.07:36:32.91#ibcon#about to write, iclass 26, count 0 2006.260.07:36:32.91#ibcon#wrote, iclass 26, count 0 2006.260.07:36:32.91#ibcon#about to read 3, iclass 26, count 0 2006.260.07:36:32.93#ibcon#read 3, iclass 26, count 0 2006.260.07:36:32.93#ibcon#about to read 4, iclass 26, count 0 2006.260.07:36:32.93#ibcon#read 4, iclass 26, count 0 2006.260.07:36:32.93#ibcon#about to read 5, iclass 26, count 0 2006.260.07:36:32.93#ibcon#read 5, iclass 26, count 0 2006.260.07:36:32.93#ibcon#about to read 6, iclass 26, count 0 2006.260.07:36:32.93#ibcon#read 6, iclass 26, count 0 2006.260.07:36:32.93#ibcon#end of sib2, iclass 26, count 0 2006.260.07:36:32.93#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:36:32.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:36:32.93#ibcon#[27=USB\r\n] 2006.260.07:36:32.93#ibcon#*before write, iclass 26, count 0 2006.260.07:36:32.93#ibcon#enter sib2, iclass 26, count 0 2006.260.07:36:32.93#ibcon#flushed, iclass 26, count 0 2006.260.07:36:32.93#ibcon#about to write, iclass 26, count 0 2006.260.07:36:32.93#ibcon#wrote, iclass 26, count 0 2006.260.07:36:32.93#ibcon#about to read 3, iclass 26, count 0 2006.260.07:36:32.96#ibcon#read 3, iclass 26, count 0 2006.260.07:36:32.96#ibcon#about to read 4, iclass 26, count 0 2006.260.07:36:32.96#ibcon#read 4, iclass 26, count 0 2006.260.07:36:32.96#ibcon#about to read 5, iclass 26, count 0 2006.260.07:36:32.96#ibcon#read 5, iclass 26, count 0 2006.260.07:36:32.96#ibcon#about to read 6, iclass 26, count 0 2006.260.07:36:32.96#ibcon#read 6, iclass 26, count 0 2006.260.07:36:32.96#ibcon#end of sib2, iclass 26, count 0 2006.260.07:36:32.96#ibcon#*after write, iclass 26, count 0 2006.260.07:36:32.96#ibcon#*before return 0, iclass 26, count 0 2006.260.07:36:32.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:32.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:36:32.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:36:32.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:36:32.96$vc4f8/vblo=6,752.99 2006.260.07:36:32.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:36:32.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:36:32.96#ibcon#ireg 17 cls_cnt 0 2006.260.07:36:32.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:32.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:32.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:32.96#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:36:32.96#ibcon#first serial, iclass 28, count 0 2006.260.07:36:32.96#ibcon#enter sib2, iclass 28, count 0 2006.260.07:36:32.96#ibcon#flushed, iclass 28, count 0 2006.260.07:36:32.96#ibcon#about to write, iclass 28, count 0 2006.260.07:36:32.96#ibcon#wrote, iclass 28, count 0 2006.260.07:36:32.96#ibcon#about to read 3, iclass 28, count 0 2006.260.07:36:32.98#ibcon#read 3, iclass 28, count 0 2006.260.07:36:32.98#ibcon#about to read 4, iclass 28, count 0 2006.260.07:36:32.98#ibcon#read 4, iclass 28, count 0 2006.260.07:36:32.98#ibcon#about to read 5, iclass 28, count 0 2006.260.07:36:32.98#ibcon#read 5, iclass 28, count 0 2006.260.07:36:32.98#ibcon#about to read 6, iclass 28, count 0 2006.260.07:36:32.98#ibcon#read 6, iclass 28, count 0 2006.260.07:36:32.98#ibcon#end of sib2, iclass 28, count 0 2006.260.07:36:32.98#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:36:32.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:36:32.98#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:36:32.98#ibcon#*before write, iclass 28, count 0 2006.260.07:36:32.98#ibcon#enter sib2, iclass 28, count 0 2006.260.07:36:32.98#ibcon#flushed, iclass 28, count 0 2006.260.07:36:32.98#ibcon#about to write, iclass 28, count 0 2006.260.07:36:32.98#ibcon#wrote, iclass 28, count 0 2006.260.07:36:32.98#ibcon#about to read 3, iclass 28, count 0 2006.260.07:36:33.02#ibcon#read 3, iclass 28, count 0 2006.260.07:36:33.02#ibcon#about to read 4, iclass 28, count 0 2006.260.07:36:33.02#ibcon#read 4, iclass 28, count 0 2006.260.07:36:33.02#ibcon#about to read 5, iclass 28, count 0 2006.260.07:36:33.02#ibcon#read 5, iclass 28, count 0 2006.260.07:36:33.02#ibcon#about to read 6, iclass 28, count 0 2006.260.07:36:33.02#ibcon#read 6, iclass 28, count 0 2006.260.07:36:33.02#ibcon#end of sib2, iclass 28, count 0 2006.260.07:36:33.02#ibcon#*after write, iclass 28, count 0 2006.260.07:36:33.02#ibcon#*before return 0, iclass 28, count 0 2006.260.07:36:33.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:33.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:36:33.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:36:33.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:36:33.02$vc4f8/vb=6,4 2006.260.07:36:33.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.07:36:33.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.07:36:33.02#ibcon#ireg 11 cls_cnt 2 2006.260.07:36:33.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:33.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:33.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:33.08#ibcon#enter wrdev, iclass 30, count 2 2006.260.07:36:33.08#ibcon#first serial, iclass 30, count 2 2006.260.07:36:33.08#ibcon#enter sib2, iclass 30, count 2 2006.260.07:36:33.08#ibcon#flushed, iclass 30, count 2 2006.260.07:36:33.08#ibcon#about to write, iclass 30, count 2 2006.260.07:36:33.08#ibcon#wrote, iclass 30, count 2 2006.260.07:36:33.08#ibcon#about to read 3, iclass 30, count 2 2006.260.07:36:33.10#ibcon#read 3, iclass 30, count 2 2006.260.07:36:33.10#ibcon#about to read 4, iclass 30, count 2 2006.260.07:36:33.10#ibcon#read 4, iclass 30, count 2 2006.260.07:36:33.10#ibcon#about to read 5, iclass 30, count 2 2006.260.07:36:33.10#ibcon#read 5, iclass 30, count 2 2006.260.07:36:33.10#ibcon#about to read 6, iclass 30, count 2 2006.260.07:36:33.10#ibcon#read 6, iclass 30, count 2 2006.260.07:36:33.10#ibcon#end of sib2, iclass 30, count 2 2006.260.07:36:33.10#ibcon#*mode == 0, iclass 30, count 2 2006.260.07:36:33.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.07:36:33.10#ibcon#[27=AT06-04\r\n] 2006.260.07:36:33.10#ibcon#*before write, iclass 30, count 2 2006.260.07:36:33.10#ibcon#enter sib2, iclass 30, count 2 2006.260.07:36:33.10#ibcon#flushed, iclass 30, count 2 2006.260.07:36:33.10#ibcon#about to write, iclass 30, count 2 2006.260.07:36:33.10#ibcon#wrote, iclass 30, count 2 2006.260.07:36:33.10#ibcon#about to read 3, iclass 30, count 2 2006.260.07:36:33.13#ibcon#read 3, iclass 30, count 2 2006.260.07:36:33.13#ibcon#about to read 4, iclass 30, count 2 2006.260.07:36:33.13#ibcon#read 4, iclass 30, count 2 2006.260.07:36:33.13#ibcon#about to read 5, iclass 30, count 2 2006.260.07:36:33.13#ibcon#read 5, iclass 30, count 2 2006.260.07:36:33.13#ibcon#about to read 6, iclass 30, count 2 2006.260.07:36:33.13#ibcon#read 6, iclass 30, count 2 2006.260.07:36:33.13#ibcon#end of sib2, iclass 30, count 2 2006.260.07:36:33.13#ibcon#*after write, iclass 30, count 2 2006.260.07:36:33.13#ibcon#*before return 0, iclass 30, count 2 2006.260.07:36:33.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:33.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:36:33.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.07:36:33.13#ibcon#ireg 7 cls_cnt 0 2006.260.07:36:33.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:33.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:33.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:33.25#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:36:33.25#ibcon#first serial, iclass 30, count 0 2006.260.07:36:33.25#ibcon#enter sib2, iclass 30, count 0 2006.260.07:36:33.25#ibcon#flushed, iclass 30, count 0 2006.260.07:36:33.25#ibcon#about to write, iclass 30, count 0 2006.260.07:36:33.25#ibcon#wrote, iclass 30, count 0 2006.260.07:36:33.25#ibcon#about to read 3, iclass 30, count 0 2006.260.07:36:33.27#ibcon#read 3, iclass 30, count 0 2006.260.07:36:33.27#ibcon#about to read 4, iclass 30, count 0 2006.260.07:36:33.27#ibcon#read 4, iclass 30, count 0 2006.260.07:36:33.27#ibcon#about to read 5, iclass 30, count 0 2006.260.07:36:33.27#ibcon#read 5, iclass 30, count 0 2006.260.07:36:33.27#ibcon#about to read 6, iclass 30, count 0 2006.260.07:36:33.27#ibcon#read 6, iclass 30, count 0 2006.260.07:36:33.27#ibcon#end of sib2, iclass 30, count 0 2006.260.07:36:33.27#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:36:33.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:36:33.27#ibcon#[27=USB\r\n] 2006.260.07:36:33.27#ibcon#*before write, iclass 30, count 0 2006.260.07:36:33.27#ibcon#enter sib2, iclass 30, count 0 2006.260.07:36:33.27#ibcon#flushed, iclass 30, count 0 2006.260.07:36:33.27#ibcon#about to write, iclass 30, count 0 2006.260.07:36:33.27#ibcon#wrote, iclass 30, count 0 2006.260.07:36:33.27#ibcon#about to read 3, iclass 30, count 0 2006.260.07:36:33.30#ibcon#read 3, iclass 30, count 0 2006.260.07:36:33.30#ibcon#about to read 4, iclass 30, count 0 2006.260.07:36:33.30#ibcon#read 4, iclass 30, count 0 2006.260.07:36:33.30#ibcon#about to read 5, iclass 30, count 0 2006.260.07:36:33.30#ibcon#read 5, iclass 30, count 0 2006.260.07:36:33.30#ibcon#about to read 6, iclass 30, count 0 2006.260.07:36:33.30#ibcon#read 6, iclass 30, count 0 2006.260.07:36:33.30#ibcon#end of sib2, iclass 30, count 0 2006.260.07:36:33.30#ibcon#*after write, iclass 30, count 0 2006.260.07:36:33.30#ibcon#*before return 0, iclass 30, count 0 2006.260.07:36:33.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:33.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:36:33.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:36:33.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:36:33.30$vc4f8/vabw=wide 2006.260.07:36:33.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:36:33.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:36:33.30#ibcon#ireg 8 cls_cnt 0 2006.260.07:36:33.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:33.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:33.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:33.30#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:36:33.30#ibcon#first serial, iclass 32, count 0 2006.260.07:36:33.30#ibcon#enter sib2, iclass 32, count 0 2006.260.07:36:33.30#ibcon#flushed, iclass 32, count 0 2006.260.07:36:33.30#ibcon#about to write, iclass 32, count 0 2006.260.07:36:33.30#ibcon#wrote, iclass 32, count 0 2006.260.07:36:33.30#ibcon#about to read 3, iclass 32, count 0 2006.260.07:36:33.32#ibcon#read 3, iclass 32, count 0 2006.260.07:36:33.32#ibcon#about to read 4, iclass 32, count 0 2006.260.07:36:33.32#ibcon#read 4, iclass 32, count 0 2006.260.07:36:33.32#ibcon#about to read 5, iclass 32, count 0 2006.260.07:36:33.32#ibcon#read 5, iclass 32, count 0 2006.260.07:36:33.32#ibcon#about to read 6, iclass 32, count 0 2006.260.07:36:33.32#ibcon#read 6, iclass 32, count 0 2006.260.07:36:33.32#ibcon#end of sib2, iclass 32, count 0 2006.260.07:36:33.32#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:36:33.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:36:33.32#ibcon#[25=BW32\r\n] 2006.260.07:36:33.32#ibcon#*before write, iclass 32, count 0 2006.260.07:36:33.32#ibcon#enter sib2, iclass 32, count 0 2006.260.07:36:33.32#ibcon#flushed, iclass 32, count 0 2006.260.07:36:33.32#ibcon#about to write, iclass 32, count 0 2006.260.07:36:33.32#ibcon#wrote, iclass 32, count 0 2006.260.07:36:33.32#ibcon#about to read 3, iclass 32, count 0 2006.260.07:36:33.35#ibcon#read 3, iclass 32, count 0 2006.260.07:36:33.35#ibcon#about to read 4, iclass 32, count 0 2006.260.07:36:33.35#ibcon#read 4, iclass 32, count 0 2006.260.07:36:33.35#ibcon#about to read 5, iclass 32, count 0 2006.260.07:36:33.35#ibcon#read 5, iclass 32, count 0 2006.260.07:36:33.35#ibcon#about to read 6, iclass 32, count 0 2006.260.07:36:33.35#ibcon#read 6, iclass 32, count 0 2006.260.07:36:33.35#ibcon#end of sib2, iclass 32, count 0 2006.260.07:36:33.35#ibcon#*after write, iclass 32, count 0 2006.260.07:36:33.35#ibcon#*before return 0, iclass 32, count 0 2006.260.07:36:33.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:33.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:36:33.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:36:33.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:36:33.35$vc4f8/vbbw=wide 2006.260.07:36:33.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:36:33.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:36:33.35#ibcon#ireg 8 cls_cnt 0 2006.260.07:36:33.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:36:33.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:36:33.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:36:33.42#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:36:33.42#ibcon#first serial, iclass 34, count 0 2006.260.07:36:33.42#ibcon#enter sib2, iclass 34, count 0 2006.260.07:36:33.42#ibcon#flushed, iclass 34, count 0 2006.260.07:36:33.42#ibcon#about to write, iclass 34, count 0 2006.260.07:36:33.42#ibcon#wrote, iclass 34, count 0 2006.260.07:36:33.42#ibcon#about to read 3, iclass 34, count 0 2006.260.07:36:33.44#ibcon#read 3, iclass 34, count 0 2006.260.07:36:33.44#ibcon#about to read 4, iclass 34, count 0 2006.260.07:36:33.44#ibcon#read 4, iclass 34, count 0 2006.260.07:36:33.44#ibcon#about to read 5, iclass 34, count 0 2006.260.07:36:33.44#ibcon#read 5, iclass 34, count 0 2006.260.07:36:33.44#ibcon#about to read 6, iclass 34, count 0 2006.260.07:36:33.44#ibcon#read 6, iclass 34, count 0 2006.260.07:36:33.44#ibcon#end of sib2, iclass 34, count 0 2006.260.07:36:33.44#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:36:33.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:36:33.44#ibcon#[27=BW32\r\n] 2006.260.07:36:33.44#ibcon#*before write, iclass 34, count 0 2006.260.07:36:33.44#ibcon#enter sib2, iclass 34, count 0 2006.260.07:36:33.44#ibcon#flushed, iclass 34, count 0 2006.260.07:36:33.44#ibcon#about to write, iclass 34, count 0 2006.260.07:36:33.44#ibcon#wrote, iclass 34, count 0 2006.260.07:36:33.44#ibcon#about to read 3, iclass 34, count 0 2006.260.07:36:33.47#ibcon#read 3, iclass 34, count 0 2006.260.07:36:33.47#ibcon#about to read 4, iclass 34, count 0 2006.260.07:36:33.47#ibcon#read 4, iclass 34, count 0 2006.260.07:36:33.47#ibcon#about to read 5, iclass 34, count 0 2006.260.07:36:33.47#ibcon#read 5, iclass 34, count 0 2006.260.07:36:33.47#ibcon#about to read 6, iclass 34, count 0 2006.260.07:36:33.47#ibcon#read 6, iclass 34, count 0 2006.260.07:36:33.47#ibcon#end of sib2, iclass 34, count 0 2006.260.07:36:33.47#ibcon#*after write, iclass 34, count 0 2006.260.07:36:33.47#ibcon#*before return 0, iclass 34, count 0 2006.260.07:36:33.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:36:33.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:36:33.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:36:33.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:36:33.47$4f8m12a/ifd4f 2006.260.07:36:33.47$ifd4f/lo= 2006.260.07:36:33.47$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:36:33.47$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:36:33.47$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:36:33.47$ifd4f/patch= 2006.260.07:36:33.47$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:36:33.47$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:36:33.47$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:36:33.47$4f8m12a/"form=m,16.000,1:2 2006.260.07:36:33.47$4f8m12a/"tpicd 2006.260.07:36:33.47$4f8m12a/echo=off 2006.260.07:36:33.47$4f8m12a/xlog=off 2006.260.07:36:33.47:!2006.260.07:37:00 2006.260.07:36:41.13#trakl#Source acquired 2006.260.07:36:42.13#flagr#flagr/antenna,acquired 2006.260.07:37:00.00:preob 2006.260.07:37:01.14/onsource/TRACKING 2006.260.07:37:01.14:!2006.260.07:37:10 2006.260.07:37:10.00:data_valid=on 2006.260.07:37:10.00:midob 2006.260.07:37:10.14/onsource/TRACKING 2006.260.07:37:10.14/wx/23.12,1010.3,86 2006.260.07:37:10.32/cable/+6.4580E-03 2006.260.07:37:11.41/va/01,08,usb,yes,31,32 2006.260.07:37:11.41/va/02,07,usb,yes,31,32 2006.260.07:37:11.41/va/03,08,usb,yes,23,23 2006.260.07:37:11.41/va/04,07,usb,yes,32,35 2006.260.07:37:11.41/va/05,07,usb,yes,35,37 2006.260.07:37:11.41/va/06,06,usb,yes,34,34 2006.260.07:37:11.41/va/07,06,usb,yes,35,35 2006.260.07:37:11.41/va/08,06,usb,yes,37,37 2006.260.07:37:11.64/valo/01,532.99,yes,locked 2006.260.07:37:11.64/valo/02,572.99,yes,locked 2006.260.07:37:11.64/valo/03,672.99,yes,locked 2006.260.07:37:11.64/valo/04,832.99,yes,locked 2006.260.07:37:11.64/valo/05,652.99,yes,locked 2006.260.07:37:11.64/valo/06,772.99,yes,locked 2006.260.07:37:11.64/valo/07,832.99,yes,locked 2006.260.07:37:11.64/valo/08,852.99,yes,locked 2006.260.07:37:12.73/vb/01,04,usb,yes,30,28 2006.260.07:37:12.73/vb/02,05,usb,yes,28,29 2006.260.07:37:12.73/vb/03,04,usb,yes,28,32 2006.260.07:37:12.73/vb/04,05,usb,yes,25,25 2006.260.07:37:12.73/vb/05,04,usb,yes,27,31 2006.260.07:37:12.73/vb/06,04,usb,yes,28,31 2006.260.07:37:12.73/vb/07,04,usb,yes,30,30 2006.260.07:37:12.73/vb/08,04,usb,yes,28,31 2006.260.07:37:12.97/vblo/01,632.99,yes,locked 2006.260.07:37:12.97/vblo/02,640.99,yes,locked 2006.260.07:37:12.97/vblo/03,656.99,yes,locked 2006.260.07:37:12.97/vblo/04,712.99,yes,locked 2006.260.07:37:12.97/vblo/05,744.99,yes,locked 2006.260.07:37:12.97/vblo/06,752.99,yes,locked 2006.260.07:37:12.97/vblo/07,734.99,yes,locked 2006.260.07:37:12.97/vblo/08,744.99,yes,locked 2006.260.07:37:13.12/vabw/8 2006.260.07:37:13.27/vbbw/8 2006.260.07:37:13.36/xfe/off,on,15.0 2006.260.07:37:13.73/ifatt/23,28,28,28 2006.260.07:37:14.07/fmout-gps/S +4.51E-07 2006.260.07:37:14.11:!2006.260.07:38:10 2006.260.07:38:10.00:data_valid=off 2006.260.07:38:10.00:postob 2006.260.07:38:10.11/cable/+6.4564E-03 2006.260.07:38:10.11/wx/23.11,1010.3,86 2006.260.07:38:11.08/fmout-gps/S +4.52E-07 2006.260.07:38:11.08:scan_name=260-0739,k06260,60 2006.260.07:38:11.09:source=nrao512,164029.63,394646.0,2000.0,neutral 2006.260.07:38:11.16#flagr#flagr/antenna,new-source 2006.260.07:38:12.14:checkk5 2006.260.07:38:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:38:12.94/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:38:13.36/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:38:13.76/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:38:14.17/chk_obsdata//k5ts1/T2600737??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:38:14.76/chk_obsdata//k5ts2/T2600737??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:38:15.11/chk_obsdata//k5ts3/T2600737??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:38:15.72/chk_obsdata//k5ts4/T2600737??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:38:16.76/k5log//k5ts1_log_newline 2006.260.07:38:17.76/k5log//k5ts2_log_newline 2006.260.07:38:18.56/k5log//k5ts3_log_newline 2006.260.07:38:19.38/k5log//k5ts4_log_newline 2006.260.07:38:19.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:38:19.40:4f8m12a=1 2006.260.07:38:19.40$4f8m12a/echo=on 2006.260.07:38:19.40$4f8m12a/pcalon 2006.260.07:38:19.40$pcalon/"no phase cal control is implemented here 2006.260.07:38:19.40$4f8m12a/"tpicd=stop 2006.260.07:38:19.40$4f8m12a/vc4f8 2006.260.07:38:19.40$vc4f8/valo=1,532.99 2006.260.07:38:19.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:38:19.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:38:19.40#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:19.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:19.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:19.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:19.40#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:38:19.40#ibcon#first serial, iclass 7, count 0 2006.260.07:38:19.40#ibcon#enter sib2, iclass 7, count 0 2006.260.07:38:19.40#ibcon#flushed, iclass 7, count 0 2006.260.07:38:19.40#ibcon#about to write, iclass 7, count 0 2006.260.07:38:19.40#ibcon#wrote, iclass 7, count 0 2006.260.07:38:19.40#ibcon#about to read 3, iclass 7, count 0 2006.260.07:38:19.45#ibcon#read 3, iclass 7, count 0 2006.260.07:38:19.45#ibcon#about to read 4, iclass 7, count 0 2006.260.07:38:19.45#ibcon#read 4, iclass 7, count 0 2006.260.07:38:19.45#ibcon#about to read 5, iclass 7, count 0 2006.260.07:38:19.45#ibcon#read 5, iclass 7, count 0 2006.260.07:38:19.45#ibcon#about to read 6, iclass 7, count 0 2006.260.07:38:19.45#ibcon#read 6, iclass 7, count 0 2006.260.07:38:19.45#ibcon#end of sib2, iclass 7, count 0 2006.260.07:38:19.45#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:38:19.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:38:19.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:38:19.45#ibcon#*before write, iclass 7, count 0 2006.260.07:38:19.45#ibcon#enter sib2, iclass 7, count 0 2006.260.07:38:19.45#ibcon#flushed, iclass 7, count 0 2006.260.07:38:19.45#ibcon#about to write, iclass 7, count 0 2006.260.07:38:19.45#ibcon#wrote, iclass 7, count 0 2006.260.07:38:19.45#ibcon#about to read 3, iclass 7, count 0 2006.260.07:38:19.50#ibcon#read 3, iclass 7, count 0 2006.260.07:38:19.50#ibcon#about to read 4, iclass 7, count 0 2006.260.07:38:19.50#ibcon#read 4, iclass 7, count 0 2006.260.07:38:19.50#ibcon#about to read 5, iclass 7, count 0 2006.260.07:38:19.50#ibcon#read 5, iclass 7, count 0 2006.260.07:38:19.50#ibcon#about to read 6, iclass 7, count 0 2006.260.07:38:19.50#ibcon#read 6, iclass 7, count 0 2006.260.07:38:19.50#ibcon#end of sib2, iclass 7, count 0 2006.260.07:38:19.50#ibcon#*after write, iclass 7, count 0 2006.260.07:38:19.50#ibcon#*before return 0, iclass 7, count 0 2006.260.07:38:19.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:19.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:19.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:38:19.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:38:19.50$vc4f8/va=1,8 2006.260.07:38:19.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:38:19.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:38:19.50#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:19.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:19.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:19.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:19.50#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:38:19.50#ibcon#first serial, iclass 11, count 2 2006.260.07:38:19.50#ibcon#enter sib2, iclass 11, count 2 2006.260.07:38:19.50#ibcon#flushed, iclass 11, count 2 2006.260.07:38:19.50#ibcon#about to write, iclass 11, count 2 2006.260.07:38:19.50#ibcon#wrote, iclass 11, count 2 2006.260.07:38:19.50#ibcon#about to read 3, iclass 11, count 2 2006.260.07:38:19.53#ibcon#read 3, iclass 11, count 2 2006.260.07:38:19.53#ibcon#about to read 4, iclass 11, count 2 2006.260.07:38:19.53#ibcon#read 4, iclass 11, count 2 2006.260.07:38:19.53#ibcon#about to read 5, iclass 11, count 2 2006.260.07:38:19.53#ibcon#read 5, iclass 11, count 2 2006.260.07:38:19.53#ibcon#about to read 6, iclass 11, count 2 2006.260.07:38:19.53#ibcon#read 6, iclass 11, count 2 2006.260.07:38:19.53#ibcon#end of sib2, iclass 11, count 2 2006.260.07:38:19.53#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:38:19.53#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:38:19.53#ibcon#[25=AT01-08\r\n] 2006.260.07:38:19.53#ibcon#*before write, iclass 11, count 2 2006.260.07:38:19.53#ibcon#enter sib2, iclass 11, count 2 2006.260.07:38:19.53#ibcon#flushed, iclass 11, count 2 2006.260.07:38:19.53#ibcon#about to write, iclass 11, count 2 2006.260.07:38:19.53#ibcon#wrote, iclass 11, count 2 2006.260.07:38:19.53#ibcon#about to read 3, iclass 11, count 2 2006.260.07:38:19.56#ibcon#read 3, iclass 11, count 2 2006.260.07:38:19.56#ibcon#about to read 4, iclass 11, count 2 2006.260.07:38:19.56#ibcon#read 4, iclass 11, count 2 2006.260.07:38:19.56#ibcon#about to read 5, iclass 11, count 2 2006.260.07:38:19.56#ibcon#read 5, iclass 11, count 2 2006.260.07:38:19.56#ibcon#about to read 6, iclass 11, count 2 2006.260.07:38:19.56#ibcon#read 6, iclass 11, count 2 2006.260.07:38:19.56#ibcon#end of sib2, iclass 11, count 2 2006.260.07:38:19.56#ibcon#*after write, iclass 11, count 2 2006.260.07:38:19.56#ibcon#*before return 0, iclass 11, count 2 2006.260.07:38:19.56#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:19.56#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:19.56#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:38:19.56#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:19.56#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:19.68#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:19.68#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:19.68#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:38:19.68#ibcon#first serial, iclass 11, count 0 2006.260.07:38:19.68#ibcon#enter sib2, iclass 11, count 0 2006.260.07:38:19.68#ibcon#flushed, iclass 11, count 0 2006.260.07:38:19.68#ibcon#about to write, iclass 11, count 0 2006.260.07:38:19.68#ibcon#wrote, iclass 11, count 0 2006.260.07:38:19.68#ibcon#about to read 3, iclass 11, count 0 2006.260.07:38:19.70#ibcon#read 3, iclass 11, count 0 2006.260.07:38:19.70#ibcon#about to read 4, iclass 11, count 0 2006.260.07:38:19.70#ibcon#read 4, iclass 11, count 0 2006.260.07:38:19.70#ibcon#about to read 5, iclass 11, count 0 2006.260.07:38:19.70#ibcon#read 5, iclass 11, count 0 2006.260.07:38:19.70#ibcon#about to read 6, iclass 11, count 0 2006.260.07:38:19.70#ibcon#read 6, iclass 11, count 0 2006.260.07:38:19.70#ibcon#end of sib2, iclass 11, count 0 2006.260.07:38:19.70#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:38:19.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:38:19.70#ibcon#[25=USB\r\n] 2006.260.07:38:19.70#ibcon#*before write, iclass 11, count 0 2006.260.07:38:19.70#ibcon#enter sib2, iclass 11, count 0 2006.260.07:38:19.70#ibcon#flushed, iclass 11, count 0 2006.260.07:38:19.70#ibcon#about to write, iclass 11, count 0 2006.260.07:38:19.70#ibcon#wrote, iclass 11, count 0 2006.260.07:38:19.70#ibcon#about to read 3, iclass 11, count 0 2006.260.07:38:19.73#ibcon#read 3, iclass 11, count 0 2006.260.07:38:19.73#ibcon#about to read 4, iclass 11, count 0 2006.260.07:38:19.73#ibcon#read 4, iclass 11, count 0 2006.260.07:38:19.73#ibcon#about to read 5, iclass 11, count 0 2006.260.07:38:19.73#ibcon#read 5, iclass 11, count 0 2006.260.07:38:19.73#ibcon#about to read 6, iclass 11, count 0 2006.260.07:38:19.73#ibcon#read 6, iclass 11, count 0 2006.260.07:38:19.73#ibcon#end of sib2, iclass 11, count 0 2006.260.07:38:19.73#ibcon#*after write, iclass 11, count 0 2006.260.07:38:19.73#ibcon#*before return 0, iclass 11, count 0 2006.260.07:38:19.73#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:19.73#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:19.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:38:19.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:38:19.73$vc4f8/valo=2,572.99 2006.260.07:38:19.73#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:38:19.73#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:38:19.73#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:19.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:19.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:19.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:19.73#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:38:19.73#ibcon#first serial, iclass 13, count 0 2006.260.07:38:19.73#ibcon#enter sib2, iclass 13, count 0 2006.260.07:38:19.73#ibcon#flushed, iclass 13, count 0 2006.260.07:38:19.73#ibcon#about to write, iclass 13, count 0 2006.260.07:38:19.73#ibcon#wrote, iclass 13, count 0 2006.260.07:38:19.73#ibcon#about to read 3, iclass 13, count 0 2006.260.07:38:19.75#ibcon#read 3, iclass 13, count 0 2006.260.07:38:19.75#ibcon#about to read 4, iclass 13, count 0 2006.260.07:38:19.75#ibcon#read 4, iclass 13, count 0 2006.260.07:38:19.75#ibcon#about to read 5, iclass 13, count 0 2006.260.07:38:19.75#ibcon#read 5, iclass 13, count 0 2006.260.07:38:19.75#ibcon#about to read 6, iclass 13, count 0 2006.260.07:38:19.75#ibcon#read 6, iclass 13, count 0 2006.260.07:38:19.75#ibcon#end of sib2, iclass 13, count 0 2006.260.07:38:19.75#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:38:19.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:38:19.75#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:38:19.75#ibcon#*before write, iclass 13, count 0 2006.260.07:38:19.75#ibcon#enter sib2, iclass 13, count 0 2006.260.07:38:19.75#ibcon#flushed, iclass 13, count 0 2006.260.07:38:19.75#ibcon#about to write, iclass 13, count 0 2006.260.07:38:19.75#ibcon#wrote, iclass 13, count 0 2006.260.07:38:19.75#ibcon#about to read 3, iclass 13, count 0 2006.260.07:38:19.79#ibcon#read 3, iclass 13, count 0 2006.260.07:38:19.79#ibcon#about to read 4, iclass 13, count 0 2006.260.07:38:19.79#ibcon#read 4, iclass 13, count 0 2006.260.07:38:19.79#ibcon#about to read 5, iclass 13, count 0 2006.260.07:38:19.79#ibcon#read 5, iclass 13, count 0 2006.260.07:38:19.79#ibcon#about to read 6, iclass 13, count 0 2006.260.07:38:19.79#ibcon#read 6, iclass 13, count 0 2006.260.07:38:19.79#ibcon#end of sib2, iclass 13, count 0 2006.260.07:38:19.79#ibcon#*after write, iclass 13, count 0 2006.260.07:38:19.79#ibcon#*before return 0, iclass 13, count 0 2006.260.07:38:19.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:19.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:19.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:38:19.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:38:19.79$vc4f8/va=2,7 2006.260.07:38:19.79#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:38:19.79#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:38:19.79#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:19.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:19.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:19.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:19.85#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:38:19.85#ibcon#first serial, iclass 15, count 2 2006.260.07:38:19.85#ibcon#enter sib2, iclass 15, count 2 2006.260.07:38:19.85#ibcon#flushed, iclass 15, count 2 2006.260.07:38:19.85#ibcon#about to write, iclass 15, count 2 2006.260.07:38:19.85#ibcon#wrote, iclass 15, count 2 2006.260.07:38:19.85#ibcon#about to read 3, iclass 15, count 2 2006.260.07:38:19.88#ibcon#read 3, iclass 15, count 2 2006.260.07:38:19.88#ibcon#about to read 4, iclass 15, count 2 2006.260.07:38:19.88#ibcon#read 4, iclass 15, count 2 2006.260.07:38:19.88#ibcon#about to read 5, iclass 15, count 2 2006.260.07:38:19.88#ibcon#read 5, iclass 15, count 2 2006.260.07:38:19.88#ibcon#about to read 6, iclass 15, count 2 2006.260.07:38:19.88#ibcon#read 6, iclass 15, count 2 2006.260.07:38:19.88#ibcon#end of sib2, iclass 15, count 2 2006.260.07:38:19.88#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:38:19.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:38:19.88#ibcon#[25=AT02-07\r\n] 2006.260.07:38:19.88#ibcon#*before write, iclass 15, count 2 2006.260.07:38:19.88#ibcon#enter sib2, iclass 15, count 2 2006.260.07:38:19.88#ibcon#flushed, iclass 15, count 2 2006.260.07:38:19.88#ibcon#about to write, iclass 15, count 2 2006.260.07:38:19.88#ibcon#wrote, iclass 15, count 2 2006.260.07:38:19.88#ibcon#about to read 3, iclass 15, count 2 2006.260.07:38:19.91#ibcon#read 3, iclass 15, count 2 2006.260.07:38:19.91#ibcon#about to read 4, iclass 15, count 2 2006.260.07:38:19.91#ibcon#read 4, iclass 15, count 2 2006.260.07:38:19.91#ibcon#about to read 5, iclass 15, count 2 2006.260.07:38:19.91#ibcon#read 5, iclass 15, count 2 2006.260.07:38:19.91#ibcon#about to read 6, iclass 15, count 2 2006.260.07:38:19.91#ibcon#read 6, iclass 15, count 2 2006.260.07:38:19.91#ibcon#end of sib2, iclass 15, count 2 2006.260.07:38:19.91#ibcon#*after write, iclass 15, count 2 2006.260.07:38:19.91#ibcon#*before return 0, iclass 15, count 2 2006.260.07:38:19.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:19.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:19.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:38:19.91#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:19.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:20.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:20.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:20.03#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:38:20.03#ibcon#first serial, iclass 15, count 0 2006.260.07:38:20.03#ibcon#enter sib2, iclass 15, count 0 2006.260.07:38:20.03#ibcon#flushed, iclass 15, count 0 2006.260.07:38:20.03#ibcon#about to write, iclass 15, count 0 2006.260.07:38:20.03#ibcon#wrote, iclass 15, count 0 2006.260.07:38:20.03#ibcon#about to read 3, iclass 15, count 0 2006.260.07:38:20.05#ibcon#read 3, iclass 15, count 0 2006.260.07:38:20.05#ibcon#about to read 4, iclass 15, count 0 2006.260.07:38:20.05#ibcon#read 4, iclass 15, count 0 2006.260.07:38:20.05#ibcon#about to read 5, iclass 15, count 0 2006.260.07:38:20.05#ibcon#read 5, iclass 15, count 0 2006.260.07:38:20.05#ibcon#about to read 6, iclass 15, count 0 2006.260.07:38:20.05#ibcon#read 6, iclass 15, count 0 2006.260.07:38:20.05#ibcon#end of sib2, iclass 15, count 0 2006.260.07:38:20.05#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:38:20.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:38:20.05#ibcon#[25=USB\r\n] 2006.260.07:38:20.05#ibcon#*before write, iclass 15, count 0 2006.260.07:38:20.05#ibcon#enter sib2, iclass 15, count 0 2006.260.07:38:20.05#ibcon#flushed, iclass 15, count 0 2006.260.07:38:20.05#ibcon#about to write, iclass 15, count 0 2006.260.07:38:20.05#ibcon#wrote, iclass 15, count 0 2006.260.07:38:20.05#ibcon#about to read 3, iclass 15, count 0 2006.260.07:38:20.08#ibcon#read 3, iclass 15, count 0 2006.260.07:38:20.08#ibcon#about to read 4, iclass 15, count 0 2006.260.07:38:20.08#ibcon#read 4, iclass 15, count 0 2006.260.07:38:20.08#ibcon#about to read 5, iclass 15, count 0 2006.260.07:38:20.08#ibcon#read 5, iclass 15, count 0 2006.260.07:38:20.08#ibcon#about to read 6, iclass 15, count 0 2006.260.07:38:20.08#ibcon#read 6, iclass 15, count 0 2006.260.07:38:20.08#ibcon#end of sib2, iclass 15, count 0 2006.260.07:38:20.08#ibcon#*after write, iclass 15, count 0 2006.260.07:38:20.08#ibcon#*before return 0, iclass 15, count 0 2006.260.07:38:20.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:20.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:20.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:38:20.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:38:20.08$vc4f8/valo=3,672.99 2006.260.07:38:20.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.07:38:20.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.07:38:20.08#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:20.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:20.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:20.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:20.08#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:38:20.08#ibcon#first serial, iclass 17, count 0 2006.260.07:38:20.08#ibcon#enter sib2, iclass 17, count 0 2006.260.07:38:20.08#ibcon#flushed, iclass 17, count 0 2006.260.07:38:20.08#ibcon#about to write, iclass 17, count 0 2006.260.07:38:20.08#ibcon#wrote, iclass 17, count 0 2006.260.07:38:20.08#ibcon#about to read 3, iclass 17, count 0 2006.260.07:38:20.10#ibcon#read 3, iclass 17, count 0 2006.260.07:38:20.10#ibcon#about to read 4, iclass 17, count 0 2006.260.07:38:20.10#ibcon#read 4, iclass 17, count 0 2006.260.07:38:20.10#ibcon#about to read 5, iclass 17, count 0 2006.260.07:38:20.10#ibcon#read 5, iclass 17, count 0 2006.260.07:38:20.10#ibcon#about to read 6, iclass 17, count 0 2006.260.07:38:20.10#ibcon#read 6, iclass 17, count 0 2006.260.07:38:20.10#ibcon#end of sib2, iclass 17, count 0 2006.260.07:38:20.10#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:38:20.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:38:20.10#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:38:20.10#ibcon#*before write, iclass 17, count 0 2006.260.07:38:20.10#ibcon#enter sib2, iclass 17, count 0 2006.260.07:38:20.10#ibcon#flushed, iclass 17, count 0 2006.260.07:38:20.10#ibcon#about to write, iclass 17, count 0 2006.260.07:38:20.10#ibcon#wrote, iclass 17, count 0 2006.260.07:38:20.10#ibcon#about to read 3, iclass 17, count 0 2006.260.07:38:20.14#ibcon#read 3, iclass 17, count 0 2006.260.07:38:20.14#ibcon#about to read 4, iclass 17, count 0 2006.260.07:38:20.14#ibcon#read 4, iclass 17, count 0 2006.260.07:38:20.14#ibcon#about to read 5, iclass 17, count 0 2006.260.07:38:20.14#ibcon#read 5, iclass 17, count 0 2006.260.07:38:20.14#ibcon#about to read 6, iclass 17, count 0 2006.260.07:38:20.14#ibcon#read 6, iclass 17, count 0 2006.260.07:38:20.14#ibcon#end of sib2, iclass 17, count 0 2006.260.07:38:20.14#ibcon#*after write, iclass 17, count 0 2006.260.07:38:20.14#ibcon#*before return 0, iclass 17, count 0 2006.260.07:38:20.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:20.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:20.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:38:20.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:38:20.14$vc4f8/va=3,8 2006.260.07:38:20.14#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.07:38:20.14#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.07:38:20.14#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:20.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:20.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:20.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:20.20#ibcon#enter wrdev, iclass 19, count 2 2006.260.07:38:20.20#ibcon#first serial, iclass 19, count 2 2006.260.07:38:20.20#ibcon#enter sib2, iclass 19, count 2 2006.260.07:38:20.20#ibcon#flushed, iclass 19, count 2 2006.260.07:38:20.20#ibcon#about to write, iclass 19, count 2 2006.260.07:38:20.20#ibcon#wrote, iclass 19, count 2 2006.260.07:38:20.20#ibcon#about to read 3, iclass 19, count 2 2006.260.07:38:20.22#ibcon#read 3, iclass 19, count 2 2006.260.07:38:20.22#ibcon#about to read 4, iclass 19, count 2 2006.260.07:38:20.22#ibcon#read 4, iclass 19, count 2 2006.260.07:38:20.22#ibcon#about to read 5, iclass 19, count 2 2006.260.07:38:20.22#ibcon#read 5, iclass 19, count 2 2006.260.07:38:20.22#ibcon#about to read 6, iclass 19, count 2 2006.260.07:38:20.22#ibcon#read 6, iclass 19, count 2 2006.260.07:38:20.22#ibcon#end of sib2, iclass 19, count 2 2006.260.07:38:20.22#ibcon#*mode == 0, iclass 19, count 2 2006.260.07:38:20.22#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.07:38:20.22#ibcon#[25=AT03-08\r\n] 2006.260.07:38:20.22#ibcon#*before write, iclass 19, count 2 2006.260.07:38:20.22#ibcon#enter sib2, iclass 19, count 2 2006.260.07:38:20.22#ibcon#flushed, iclass 19, count 2 2006.260.07:38:20.22#ibcon#about to write, iclass 19, count 2 2006.260.07:38:20.22#ibcon#wrote, iclass 19, count 2 2006.260.07:38:20.22#ibcon#about to read 3, iclass 19, count 2 2006.260.07:38:20.25#ibcon#read 3, iclass 19, count 2 2006.260.07:38:20.25#ibcon#about to read 4, iclass 19, count 2 2006.260.07:38:20.25#ibcon#read 4, iclass 19, count 2 2006.260.07:38:20.25#ibcon#about to read 5, iclass 19, count 2 2006.260.07:38:20.25#ibcon#read 5, iclass 19, count 2 2006.260.07:38:20.25#ibcon#about to read 6, iclass 19, count 2 2006.260.07:38:20.25#ibcon#read 6, iclass 19, count 2 2006.260.07:38:20.25#ibcon#end of sib2, iclass 19, count 2 2006.260.07:38:20.25#ibcon#*after write, iclass 19, count 2 2006.260.07:38:20.25#ibcon#*before return 0, iclass 19, count 2 2006.260.07:38:20.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:20.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:20.25#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.07:38:20.25#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:20.25#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:20.37#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:20.37#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:20.37#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:38:20.37#ibcon#first serial, iclass 19, count 0 2006.260.07:38:20.37#ibcon#enter sib2, iclass 19, count 0 2006.260.07:38:20.37#ibcon#flushed, iclass 19, count 0 2006.260.07:38:20.37#ibcon#about to write, iclass 19, count 0 2006.260.07:38:20.37#ibcon#wrote, iclass 19, count 0 2006.260.07:38:20.37#ibcon#about to read 3, iclass 19, count 0 2006.260.07:38:20.39#ibcon#read 3, iclass 19, count 0 2006.260.07:38:20.39#ibcon#about to read 4, iclass 19, count 0 2006.260.07:38:20.39#ibcon#read 4, iclass 19, count 0 2006.260.07:38:20.39#ibcon#about to read 5, iclass 19, count 0 2006.260.07:38:20.39#ibcon#read 5, iclass 19, count 0 2006.260.07:38:20.39#ibcon#about to read 6, iclass 19, count 0 2006.260.07:38:20.39#ibcon#read 6, iclass 19, count 0 2006.260.07:38:20.39#ibcon#end of sib2, iclass 19, count 0 2006.260.07:38:20.39#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:38:20.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:38:20.39#ibcon#[25=USB\r\n] 2006.260.07:38:20.39#ibcon#*before write, iclass 19, count 0 2006.260.07:38:20.39#ibcon#enter sib2, iclass 19, count 0 2006.260.07:38:20.39#ibcon#flushed, iclass 19, count 0 2006.260.07:38:20.39#ibcon#about to write, iclass 19, count 0 2006.260.07:38:20.39#ibcon#wrote, iclass 19, count 0 2006.260.07:38:20.39#ibcon#about to read 3, iclass 19, count 0 2006.260.07:38:20.42#ibcon#read 3, iclass 19, count 0 2006.260.07:38:20.42#ibcon#about to read 4, iclass 19, count 0 2006.260.07:38:20.42#ibcon#read 4, iclass 19, count 0 2006.260.07:38:20.42#ibcon#about to read 5, iclass 19, count 0 2006.260.07:38:20.42#ibcon#read 5, iclass 19, count 0 2006.260.07:38:20.42#ibcon#about to read 6, iclass 19, count 0 2006.260.07:38:20.42#ibcon#read 6, iclass 19, count 0 2006.260.07:38:20.42#ibcon#end of sib2, iclass 19, count 0 2006.260.07:38:20.42#ibcon#*after write, iclass 19, count 0 2006.260.07:38:20.42#ibcon#*before return 0, iclass 19, count 0 2006.260.07:38:20.42#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:20.42#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:20.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:38:20.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:38:20.42$vc4f8/valo=4,832.99 2006.260.07:38:20.42#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.07:38:20.42#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.07:38:20.42#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:20.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:20.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:20.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:20.42#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:38:20.42#ibcon#first serial, iclass 21, count 0 2006.260.07:38:20.42#ibcon#enter sib2, iclass 21, count 0 2006.260.07:38:20.42#ibcon#flushed, iclass 21, count 0 2006.260.07:38:20.42#ibcon#about to write, iclass 21, count 0 2006.260.07:38:20.42#ibcon#wrote, iclass 21, count 0 2006.260.07:38:20.42#ibcon#about to read 3, iclass 21, count 0 2006.260.07:38:20.44#ibcon#read 3, iclass 21, count 0 2006.260.07:38:20.44#ibcon#about to read 4, iclass 21, count 0 2006.260.07:38:20.44#ibcon#read 4, iclass 21, count 0 2006.260.07:38:20.44#ibcon#about to read 5, iclass 21, count 0 2006.260.07:38:20.44#ibcon#read 5, iclass 21, count 0 2006.260.07:38:20.44#ibcon#about to read 6, iclass 21, count 0 2006.260.07:38:20.44#ibcon#read 6, iclass 21, count 0 2006.260.07:38:20.44#ibcon#end of sib2, iclass 21, count 0 2006.260.07:38:20.44#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:38:20.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:38:20.44#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:38:20.44#ibcon#*before write, iclass 21, count 0 2006.260.07:38:20.44#ibcon#enter sib2, iclass 21, count 0 2006.260.07:38:20.44#ibcon#flushed, iclass 21, count 0 2006.260.07:38:20.44#ibcon#about to write, iclass 21, count 0 2006.260.07:38:20.44#ibcon#wrote, iclass 21, count 0 2006.260.07:38:20.44#ibcon#about to read 3, iclass 21, count 0 2006.260.07:38:20.48#ibcon#read 3, iclass 21, count 0 2006.260.07:38:20.48#ibcon#about to read 4, iclass 21, count 0 2006.260.07:38:20.48#ibcon#read 4, iclass 21, count 0 2006.260.07:38:20.48#ibcon#about to read 5, iclass 21, count 0 2006.260.07:38:20.48#ibcon#read 5, iclass 21, count 0 2006.260.07:38:20.48#ibcon#about to read 6, iclass 21, count 0 2006.260.07:38:20.48#ibcon#read 6, iclass 21, count 0 2006.260.07:38:20.48#ibcon#end of sib2, iclass 21, count 0 2006.260.07:38:20.48#ibcon#*after write, iclass 21, count 0 2006.260.07:38:20.48#ibcon#*before return 0, iclass 21, count 0 2006.260.07:38:20.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:20.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:20.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:38:20.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:38:20.48$vc4f8/va=4,7 2006.260.07:38:20.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.07:38:20.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.07:38:20.48#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:20.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:20.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:20.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:20.54#ibcon#enter wrdev, iclass 23, count 2 2006.260.07:38:20.54#ibcon#first serial, iclass 23, count 2 2006.260.07:38:20.54#ibcon#enter sib2, iclass 23, count 2 2006.260.07:38:20.54#ibcon#flushed, iclass 23, count 2 2006.260.07:38:20.54#ibcon#about to write, iclass 23, count 2 2006.260.07:38:20.54#ibcon#wrote, iclass 23, count 2 2006.260.07:38:20.54#ibcon#about to read 3, iclass 23, count 2 2006.260.07:38:20.56#ibcon#read 3, iclass 23, count 2 2006.260.07:38:20.56#ibcon#about to read 4, iclass 23, count 2 2006.260.07:38:20.56#ibcon#read 4, iclass 23, count 2 2006.260.07:38:20.56#ibcon#about to read 5, iclass 23, count 2 2006.260.07:38:20.56#ibcon#read 5, iclass 23, count 2 2006.260.07:38:20.56#ibcon#about to read 6, iclass 23, count 2 2006.260.07:38:20.56#ibcon#read 6, iclass 23, count 2 2006.260.07:38:20.56#ibcon#end of sib2, iclass 23, count 2 2006.260.07:38:20.56#ibcon#*mode == 0, iclass 23, count 2 2006.260.07:38:20.56#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.07:38:20.56#ibcon#[25=AT04-07\r\n] 2006.260.07:38:20.56#ibcon#*before write, iclass 23, count 2 2006.260.07:38:20.56#ibcon#enter sib2, iclass 23, count 2 2006.260.07:38:20.56#ibcon#flushed, iclass 23, count 2 2006.260.07:38:20.56#ibcon#about to write, iclass 23, count 2 2006.260.07:38:20.56#ibcon#wrote, iclass 23, count 2 2006.260.07:38:20.56#ibcon#about to read 3, iclass 23, count 2 2006.260.07:38:20.59#ibcon#read 3, iclass 23, count 2 2006.260.07:38:20.59#ibcon#about to read 4, iclass 23, count 2 2006.260.07:38:20.59#ibcon#read 4, iclass 23, count 2 2006.260.07:38:20.59#ibcon#about to read 5, iclass 23, count 2 2006.260.07:38:20.59#ibcon#read 5, iclass 23, count 2 2006.260.07:38:20.59#ibcon#about to read 6, iclass 23, count 2 2006.260.07:38:20.59#ibcon#read 6, iclass 23, count 2 2006.260.07:38:20.59#ibcon#end of sib2, iclass 23, count 2 2006.260.07:38:20.59#ibcon#*after write, iclass 23, count 2 2006.260.07:38:20.59#ibcon#*before return 0, iclass 23, count 2 2006.260.07:38:20.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:20.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:20.59#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.07:38:20.59#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:20.59#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:20.71#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:20.71#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:20.71#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:38:20.71#ibcon#first serial, iclass 23, count 0 2006.260.07:38:20.71#ibcon#enter sib2, iclass 23, count 0 2006.260.07:38:20.71#ibcon#flushed, iclass 23, count 0 2006.260.07:38:20.71#ibcon#about to write, iclass 23, count 0 2006.260.07:38:20.71#ibcon#wrote, iclass 23, count 0 2006.260.07:38:20.71#ibcon#about to read 3, iclass 23, count 0 2006.260.07:38:20.73#ibcon#read 3, iclass 23, count 0 2006.260.07:38:20.73#ibcon#about to read 4, iclass 23, count 0 2006.260.07:38:20.73#ibcon#read 4, iclass 23, count 0 2006.260.07:38:20.73#ibcon#about to read 5, iclass 23, count 0 2006.260.07:38:20.73#ibcon#read 5, iclass 23, count 0 2006.260.07:38:20.73#ibcon#about to read 6, iclass 23, count 0 2006.260.07:38:20.73#ibcon#read 6, iclass 23, count 0 2006.260.07:38:20.73#ibcon#end of sib2, iclass 23, count 0 2006.260.07:38:20.73#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:38:20.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:38:20.73#ibcon#[25=USB\r\n] 2006.260.07:38:20.73#ibcon#*before write, iclass 23, count 0 2006.260.07:38:20.73#ibcon#enter sib2, iclass 23, count 0 2006.260.07:38:20.73#ibcon#flushed, iclass 23, count 0 2006.260.07:38:20.73#ibcon#about to write, iclass 23, count 0 2006.260.07:38:20.73#ibcon#wrote, iclass 23, count 0 2006.260.07:38:20.73#ibcon#about to read 3, iclass 23, count 0 2006.260.07:38:20.76#ibcon#read 3, iclass 23, count 0 2006.260.07:38:20.76#ibcon#about to read 4, iclass 23, count 0 2006.260.07:38:20.76#ibcon#read 4, iclass 23, count 0 2006.260.07:38:20.76#ibcon#about to read 5, iclass 23, count 0 2006.260.07:38:20.76#ibcon#read 5, iclass 23, count 0 2006.260.07:38:20.76#ibcon#about to read 6, iclass 23, count 0 2006.260.07:38:20.76#ibcon#read 6, iclass 23, count 0 2006.260.07:38:20.76#ibcon#end of sib2, iclass 23, count 0 2006.260.07:38:20.76#ibcon#*after write, iclass 23, count 0 2006.260.07:38:20.76#ibcon#*before return 0, iclass 23, count 0 2006.260.07:38:20.76#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:20.76#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:20.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:38:20.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:38:20.76$vc4f8/valo=5,652.99 2006.260.07:38:20.76#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.07:38:20.76#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.07:38:20.76#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:20.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:20.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:20.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:20.76#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:38:20.76#ibcon#first serial, iclass 25, count 0 2006.260.07:38:20.76#ibcon#enter sib2, iclass 25, count 0 2006.260.07:38:20.76#ibcon#flushed, iclass 25, count 0 2006.260.07:38:20.76#ibcon#about to write, iclass 25, count 0 2006.260.07:38:20.76#ibcon#wrote, iclass 25, count 0 2006.260.07:38:20.76#ibcon#about to read 3, iclass 25, count 0 2006.260.07:38:20.78#ibcon#read 3, iclass 25, count 0 2006.260.07:38:20.78#ibcon#about to read 4, iclass 25, count 0 2006.260.07:38:20.78#ibcon#read 4, iclass 25, count 0 2006.260.07:38:20.78#ibcon#about to read 5, iclass 25, count 0 2006.260.07:38:20.78#ibcon#read 5, iclass 25, count 0 2006.260.07:38:20.78#ibcon#about to read 6, iclass 25, count 0 2006.260.07:38:20.78#ibcon#read 6, iclass 25, count 0 2006.260.07:38:20.78#ibcon#end of sib2, iclass 25, count 0 2006.260.07:38:20.78#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:38:20.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:38:20.78#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:38:20.78#ibcon#*before write, iclass 25, count 0 2006.260.07:38:20.78#ibcon#enter sib2, iclass 25, count 0 2006.260.07:38:20.78#ibcon#flushed, iclass 25, count 0 2006.260.07:38:20.78#ibcon#about to write, iclass 25, count 0 2006.260.07:38:20.78#ibcon#wrote, iclass 25, count 0 2006.260.07:38:20.78#ibcon#about to read 3, iclass 25, count 0 2006.260.07:38:20.82#ibcon#read 3, iclass 25, count 0 2006.260.07:38:20.82#ibcon#about to read 4, iclass 25, count 0 2006.260.07:38:20.82#ibcon#read 4, iclass 25, count 0 2006.260.07:38:20.82#ibcon#about to read 5, iclass 25, count 0 2006.260.07:38:20.82#ibcon#read 5, iclass 25, count 0 2006.260.07:38:20.82#ibcon#about to read 6, iclass 25, count 0 2006.260.07:38:20.82#ibcon#read 6, iclass 25, count 0 2006.260.07:38:20.82#ibcon#end of sib2, iclass 25, count 0 2006.260.07:38:20.82#ibcon#*after write, iclass 25, count 0 2006.260.07:38:20.82#ibcon#*before return 0, iclass 25, count 0 2006.260.07:38:20.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:20.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:20.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:38:20.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:38:20.82$vc4f8/va=5,7 2006.260.07:38:20.82#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.07:38:20.82#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.07:38:20.82#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:20.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:20.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:20.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:20.88#ibcon#enter wrdev, iclass 27, count 2 2006.260.07:38:20.88#ibcon#first serial, iclass 27, count 2 2006.260.07:38:20.88#ibcon#enter sib2, iclass 27, count 2 2006.260.07:38:20.88#ibcon#flushed, iclass 27, count 2 2006.260.07:38:20.88#ibcon#about to write, iclass 27, count 2 2006.260.07:38:20.88#ibcon#wrote, iclass 27, count 2 2006.260.07:38:20.88#ibcon#about to read 3, iclass 27, count 2 2006.260.07:38:20.90#ibcon#read 3, iclass 27, count 2 2006.260.07:38:20.90#ibcon#about to read 4, iclass 27, count 2 2006.260.07:38:20.90#ibcon#read 4, iclass 27, count 2 2006.260.07:38:20.90#ibcon#about to read 5, iclass 27, count 2 2006.260.07:38:20.90#ibcon#read 5, iclass 27, count 2 2006.260.07:38:20.90#ibcon#about to read 6, iclass 27, count 2 2006.260.07:38:20.90#ibcon#read 6, iclass 27, count 2 2006.260.07:38:20.90#ibcon#end of sib2, iclass 27, count 2 2006.260.07:38:20.90#ibcon#*mode == 0, iclass 27, count 2 2006.260.07:38:20.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.07:38:20.90#ibcon#[25=AT05-07\r\n] 2006.260.07:38:20.90#ibcon#*before write, iclass 27, count 2 2006.260.07:38:20.90#ibcon#enter sib2, iclass 27, count 2 2006.260.07:38:20.90#ibcon#flushed, iclass 27, count 2 2006.260.07:38:20.90#ibcon#about to write, iclass 27, count 2 2006.260.07:38:20.90#ibcon#wrote, iclass 27, count 2 2006.260.07:38:20.90#ibcon#about to read 3, iclass 27, count 2 2006.260.07:38:20.93#ibcon#read 3, iclass 27, count 2 2006.260.07:38:20.93#ibcon#about to read 4, iclass 27, count 2 2006.260.07:38:20.93#ibcon#read 4, iclass 27, count 2 2006.260.07:38:20.93#ibcon#about to read 5, iclass 27, count 2 2006.260.07:38:20.93#ibcon#read 5, iclass 27, count 2 2006.260.07:38:20.93#ibcon#about to read 6, iclass 27, count 2 2006.260.07:38:20.93#ibcon#read 6, iclass 27, count 2 2006.260.07:38:20.93#ibcon#end of sib2, iclass 27, count 2 2006.260.07:38:20.93#ibcon#*after write, iclass 27, count 2 2006.260.07:38:20.93#ibcon#*before return 0, iclass 27, count 2 2006.260.07:38:20.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:20.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:20.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.07:38:20.93#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:20.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:21.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:21.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:21.05#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:38:21.05#ibcon#first serial, iclass 27, count 0 2006.260.07:38:21.05#ibcon#enter sib2, iclass 27, count 0 2006.260.07:38:21.05#ibcon#flushed, iclass 27, count 0 2006.260.07:38:21.05#ibcon#about to write, iclass 27, count 0 2006.260.07:38:21.05#ibcon#wrote, iclass 27, count 0 2006.260.07:38:21.05#ibcon#about to read 3, iclass 27, count 0 2006.260.07:38:21.07#ibcon#read 3, iclass 27, count 0 2006.260.07:38:21.07#ibcon#about to read 4, iclass 27, count 0 2006.260.07:38:21.07#ibcon#read 4, iclass 27, count 0 2006.260.07:38:21.07#ibcon#about to read 5, iclass 27, count 0 2006.260.07:38:21.07#ibcon#read 5, iclass 27, count 0 2006.260.07:38:21.07#ibcon#about to read 6, iclass 27, count 0 2006.260.07:38:21.07#ibcon#read 6, iclass 27, count 0 2006.260.07:38:21.07#ibcon#end of sib2, iclass 27, count 0 2006.260.07:38:21.07#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:38:21.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:38:21.07#ibcon#[25=USB\r\n] 2006.260.07:38:21.07#ibcon#*before write, iclass 27, count 0 2006.260.07:38:21.07#ibcon#enter sib2, iclass 27, count 0 2006.260.07:38:21.07#ibcon#flushed, iclass 27, count 0 2006.260.07:38:21.07#ibcon#about to write, iclass 27, count 0 2006.260.07:38:21.07#ibcon#wrote, iclass 27, count 0 2006.260.07:38:21.07#ibcon#about to read 3, iclass 27, count 0 2006.260.07:38:21.10#ibcon#read 3, iclass 27, count 0 2006.260.07:38:21.10#ibcon#about to read 4, iclass 27, count 0 2006.260.07:38:21.10#ibcon#read 4, iclass 27, count 0 2006.260.07:38:21.10#ibcon#about to read 5, iclass 27, count 0 2006.260.07:38:21.10#ibcon#read 5, iclass 27, count 0 2006.260.07:38:21.10#ibcon#about to read 6, iclass 27, count 0 2006.260.07:38:21.10#ibcon#read 6, iclass 27, count 0 2006.260.07:38:21.10#ibcon#end of sib2, iclass 27, count 0 2006.260.07:38:21.10#ibcon#*after write, iclass 27, count 0 2006.260.07:38:21.10#ibcon#*before return 0, iclass 27, count 0 2006.260.07:38:21.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:21.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:21.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:38:21.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:38:21.10$vc4f8/valo=6,772.99 2006.260.07:38:21.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.07:38:21.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.07:38:21.10#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:21.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:21.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:21.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:21.10#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:38:21.10#ibcon#first serial, iclass 29, count 0 2006.260.07:38:21.10#ibcon#enter sib2, iclass 29, count 0 2006.260.07:38:21.10#ibcon#flushed, iclass 29, count 0 2006.260.07:38:21.10#ibcon#about to write, iclass 29, count 0 2006.260.07:38:21.10#ibcon#wrote, iclass 29, count 0 2006.260.07:38:21.10#ibcon#about to read 3, iclass 29, count 0 2006.260.07:38:21.12#ibcon#read 3, iclass 29, count 0 2006.260.07:38:21.12#ibcon#about to read 4, iclass 29, count 0 2006.260.07:38:21.12#ibcon#read 4, iclass 29, count 0 2006.260.07:38:21.12#ibcon#about to read 5, iclass 29, count 0 2006.260.07:38:21.12#ibcon#read 5, iclass 29, count 0 2006.260.07:38:21.12#ibcon#about to read 6, iclass 29, count 0 2006.260.07:38:21.12#ibcon#read 6, iclass 29, count 0 2006.260.07:38:21.12#ibcon#end of sib2, iclass 29, count 0 2006.260.07:38:21.12#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:38:21.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:38:21.12#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:38:21.12#ibcon#*before write, iclass 29, count 0 2006.260.07:38:21.12#ibcon#enter sib2, iclass 29, count 0 2006.260.07:38:21.12#ibcon#flushed, iclass 29, count 0 2006.260.07:38:21.12#ibcon#about to write, iclass 29, count 0 2006.260.07:38:21.12#ibcon#wrote, iclass 29, count 0 2006.260.07:38:21.12#ibcon#about to read 3, iclass 29, count 0 2006.260.07:38:21.16#ibcon#read 3, iclass 29, count 0 2006.260.07:38:21.16#ibcon#about to read 4, iclass 29, count 0 2006.260.07:38:21.16#ibcon#read 4, iclass 29, count 0 2006.260.07:38:21.16#ibcon#about to read 5, iclass 29, count 0 2006.260.07:38:21.16#ibcon#read 5, iclass 29, count 0 2006.260.07:38:21.16#ibcon#about to read 6, iclass 29, count 0 2006.260.07:38:21.16#ibcon#read 6, iclass 29, count 0 2006.260.07:38:21.16#ibcon#end of sib2, iclass 29, count 0 2006.260.07:38:21.16#ibcon#*after write, iclass 29, count 0 2006.260.07:38:21.16#ibcon#*before return 0, iclass 29, count 0 2006.260.07:38:21.16#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:21.16#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:21.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:38:21.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:38:21.16$vc4f8/va=6,6 2006.260.07:38:21.16#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.07:38:21.16#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.07:38:21.16#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:21.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:21.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:21.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:21.22#ibcon#enter wrdev, iclass 31, count 2 2006.260.07:38:21.22#ibcon#first serial, iclass 31, count 2 2006.260.07:38:21.22#ibcon#enter sib2, iclass 31, count 2 2006.260.07:38:21.22#ibcon#flushed, iclass 31, count 2 2006.260.07:38:21.22#ibcon#about to write, iclass 31, count 2 2006.260.07:38:21.22#ibcon#wrote, iclass 31, count 2 2006.260.07:38:21.22#ibcon#about to read 3, iclass 31, count 2 2006.260.07:38:21.24#ibcon#read 3, iclass 31, count 2 2006.260.07:38:21.24#ibcon#about to read 4, iclass 31, count 2 2006.260.07:38:21.24#ibcon#read 4, iclass 31, count 2 2006.260.07:38:21.24#ibcon#about to read 5, iclass 31, count 2 2006.260.07:38:21.24#ibcon#read 5, iclass 31, count 2 2006.260.07:38:21.24#ibcon#about to read 6, iclass 31, count 2 2006.260.07:38:21.24#ibcon#read 6, iclass 31, count 2 2006.260.07:38:21.24#ibcon#end of sib2, iclass 31, count 2 2006.260.07:38:21.24#ibcon#*mode == 0, iclass 31, count 2 2006.260.07:38:21.24#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.07:38:21.24#ibcon#[25=AT06-06\r\n] 2006.260.07:38:21.24#ibcon#*before write, iclass 31, count 2 2006.260.07:38:21.24#ibcon#enter sib2, iclass 31, count 2 2006.260.07:38:21.24#ibcon#flushed, iclass 31, count 2 2006.260.07:38:21.24#ibcon#about to write, iclass 31, count 2 2006.260.07:38:21.24#ibcon#wrote, iclass 31, count 2 2006.260.07:38:21.24#ibcon#about to read 3, iclass 31, count 2 2006.260.07:38:21.27#ibcon#read 3, iclass 31, count 2 2006.260.07:38:21.27#ibcon#about to read 4, iclass 31, count 2 2006.260.07:38:21.27#ibcon#read 4, iclass 31, count 2 2006.260.07:38:21.27#ibcon#about to read 5, iclass 31, count 2 2006.260.07:38:21.27#ibcon#read 5, iclass 31, count 2 2006.260.07:38:21.27#ibcon#about to read 6, iclass 31, count 2 2006.260.07:38:21.27#ibcon#read 6, iclass 31, count 2 2006.260.07:38:21.27#ibcon#end of sib2, iclass 31, count 2 2006.260.07:38:21.27#ibcon#*after write, iclass 31, count 2 2006.260.07:38:21.27#ibcon#*before return 0, iclass 31, count 2 2006.260.07:38:21.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:21.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:21.27#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.07:38:21.27#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:21.27#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:38:21.39#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:38:21.39#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:38:21.39#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:38:21.39#ibcon#first serial, iclass 31, count 0 2006.260.07:38:21.39#ibcon#enter sib2, iclass 31, count 0 2006.260.07:38:21.39#ibcon#flushed, iclass 31, count 0 2006.260.07:38:21.39#ibcon#about to write, iclass 31, count 0 2006.260.07:38:21.39#ibcon#wrote, iclass 31, count 0 2006.260.07:38:21.39#ibcon#about to read 3, iclass 31, count 0 2006.260.07:38:21.41#ibcon#read 3, iclass 31, count 0 2006.260.07:38:21.41#ibcon#about to read 4, iclass 31, count 0 2006.260.07:38:21.41#ibcon#read 4, iclass 31, count 0 2006.260.07:38:21.41#ibcon#about to read 5, iclass 31, count 0 2006.260.07:38:21.41#ibcon#read 5, iclass 31, count 0 2006.260.07:38:21.41#ibcon#about to read 6, iclass 31, count 0 2006.260.07:38:21.41#ibcon#read 6, iclass 31, count 0 2006.260.07:38:21.41#ibcon#end of sib2, iclass 31, count 0 2006.260.07:38:21.41#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:38:21.41#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:38:21.41#ibcon#[25=USB\r\n] 2006.260.07:38:21.41#ibcon#*before write, iclass 31, count 0 2006.260.07:38:21.41#ibcon#enter sib2, iclass 31, count 0 2006.260.07:38:21.41#ibcon#flushed, iclass 31, count 0 2006.260.07:38:21.41#ibcon#about to write, iclass 31, count 0 2006.260.07:38:21.41#ibcon#wrote, iclass 31, count 0 2006.260.07:38:21.41#ibcon#about to read 3, iclass 31, count 0 2006.260.07:38:21.44#ibcon#read 3, iclass 31, count 0 2006.260.07:38:21.44#ibcon#about to read 4, iclass 31, count 0 2006.260.07:38:21.44#ibcon#read 4, iclass 31, count 0 2006.260.07:38:21.44#ibcon#about to read 5, iclass 31, count 0 2006.260.07:38:21.44#ibcon#read 5, iclass 31, count 0 2006.260.07:38:21.44#ibcon#about to read 6, iclass 31, count 0 2006.260.07:38:21.44#ibcon#read 6, iclass 31, count 0 2006.260.07:38:21.44#ibcon#end of sib2, iclass 31, count 0 2006.260.07:38:21.44#ibcon#*after write, iclass 31, count 0 2006.260.07:38:21.44#ibcon#*before return 0, iclass 31, count 0 2006.260.07:38:21.44#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:38:21.44#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:38:21.44#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:38:21.44#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:38:21.44$vc4f8/valo=7,832.99 2006.260.07:38:21.44#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.07:38:21.44#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.07:38:21.44#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:21.44#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:38:21.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:38:21.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:38:21.44#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:38:21.44#ibcon#first serial, iclass 33, count 0 2006.260.07:38:21.44#ibcon#enter sib2, iclass 33, count 0 2006.260.07:38:21.44#ibcon#flushed, iclass 33, count 0 2006.260.07:38:21.44#ibcon#about to write, iclass 33, count 0 2006.260.07:38:21.44#ibcon#wrote, iclass 33, count 0 2006.260.07:38:21.44#ibcon#about to read 3, iclass 33, count 0 2006.260.07:38:21.46#ibcon#read 3, iclass 33, count 0 2006.260.07:38:21.46#ibcon#about to read 4, iclass 33, count 0 2006.260.07:38:21.46#ibcon#read 4, iclass 33, count 0 2006.260.07:38:21.46#ibcon#about to read 5, iclass 33, count 0 2006.260.07:38:21.46#ibcon#read 5, iclass 33, count 0 2006.260.07:38:21.46#ibcon#about to read 6, iclass 33, count 0 2006.260.07:38:21.46#ibcon#read 6, iclass 33, count 0 2006.260.07:38:21.46#ibcon#end of sib2, iclass 33, count 0 2006.260.07:38:21.46#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:38:21.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:38:21.46#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:38:21.46#ibcon#*before write, iclass 33, count 0 2006.260.07:38:21.46#ibcon#enter sib2, iclass 33, count 0 2006.260.07:38:21.46#ibcon#flushed, iclass 33, count 0 2006.260.07:38:21.46#ibcon#about to write, iclass 33, count 0 2006.260.07:38:21.46#ibcon#wrote, iclass 33, count 0 2006.260.07:38:21.46#ibcon#about to read 3, iclass 33, count 0 2006.260.07:38:21.50#ibcon#read 3, iclass 33, count 0 2006.260.07:38:21.50#ibcon#about to read 4, iclass 33, count 0 2006.260.07:38:21.50#ibcon#read 4, iclass 33, count 0 2006.260.07:38:21.50#ibcon#about to read 5, iclass 33, count 0 2006.260.07:38:21.50#ibcon#read 5, iclass 33, count 0 2006.260.07:38:21.50#ibcon#about to read 6, iclass 33, count 0 2006.260.07:38:21.50#ibcon#read 6, iclass 33, count 0 2006.260.07:38:21.50#ibcon#end of sib2, iclass 33, count 0 2006.260.07:38:21.50#ibcon#*after write, iclass 33, count 0 2006.260.07:38:21.50#ibcon#*before return 0, iclass 33, count 0 2006.260.07:38:21.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:38:21.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:38:21.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:38:21.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:38:21.50$vc4f8/va=7,6 2006.260.07:38:21.50#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.07:38:21.50#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.07:38:21.50#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:21.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:38:21.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:38:21.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:38:21.56#ibcon#enter wrdev, iclass 35, count 2 2006.260.07:38:21.56#ibcon#first serial, iclass 35, count 2 2006.260.07:38:21.56#ibcon#enter sib2, iclass 35, count 2 2006.260.07:38:21.56#ibcon#flushed, iclass 35, count 2 2006.260.07:38:21.56#ibcon#about to write, iclass 35, count 2 2006.260.07:38:21.56#ibcon#wrote, iclass 35, count 2 2006.260.07:38:21.56#ibcon#about to read 3, iclass 35, count 2 2006.260.07:38:21.58#ibcon#read 3, iclass 35, count 2 2006.260.07:38:21.58#ibcon#about to read 4, iclass 35, count 2 2006.260.07:38:21.58#ibcon#read 4, iclass 35, count 2 2006.260.07:38:21.58#ibcon#about to read 5, iclass 35, count 2 2006.260.07:38:21.58#ibcon#read 5, iclass 35, count 2 2006.260.07:38:21.58#ibcon#about to read 6, iclass 35, count 2 2006.260.07:38:21.58#ibcon#read 6, iclass 35, count 2 2006.260.07:38:21.58#ibcon#end of sib2, iclass 35, count 2 2006.260.07:38:21.58#ibcon#*mode == 0, iclass 35, count 2 2006.260.07:38:21.58#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.07:38:21.58#ibcon#[25=AT07-06\r\n] 2006.260.07:38:21.58#ibcon#*before write, iclass 35, count 2 2006.260.07:38:21.58#ibcon#enter sib2, iclass 35, count 2 2006.260.07:38:21.58#ibcon#flushed, iclass 35, count 2 2006.260.07:38:21.58#ibcon#about to write, iclass 35, count 2 2006.260.07:38:21.58#ibcon#wrote, iclass 35, count 2 2006.260.07:38:21.58#ibcon#about to read 3, iclass 35, count 2 2006.260.07:38:21.61#ibcon#read 3, iclass 35, count 2 2006.260.07:38:21.61#ibcon#about to read 4, iclass 35, count 2 2006.260.07:38:21.61#ibcon#read 4, iclass 35, count 2 2006.260.07:38:21.61#ibcon#about to read 5, iclass 35, count 2 2006.260.07:38:21.61#ibcon#read 5, iclass 35, count 2 2006.260.07:38:21.61#ibcon#about to read 6, iclass 35, count 2 2006.260.07:38:21.61#ibcon#read 6, iclass 35, count 2 2006.260.07:38:21.61#ibcon#end of sib2, iclass 35, count 2 2006.260.07:38:21.61#ibcon#*after write, iclass 35, count 2 2006.260.07:38:21.61#ibcon#*before return 0, iclass 35, count 2 2006.260.07:38:21.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:38:21.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:38:21.61#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.07:38:21.61#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:21.61#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:38:21.73#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:38:21.73#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:38:21.73#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:38:21.73#ibcon#first serial, iclass 35, count 0 2006.260.07:38:21.73#ibcon#enter sib2, iclass 35, count 0 2006.260.07:38:21.73#ibcon#flushed, iclass 35, count 0 2006.260.07:38:21.73#ibcon#about to write, iclass 35, count 0 2006.260.07:38:21.73#ibcon#wrote, iclass 35, count 0 2006.260.07:38:21.73#ibcon#about to read 3, iclass 35, count 0 2006.260.07:38:21.75#ibcon#read 3, iclass 35, count 0 2006.260.07:38:21.75#ibcon#about to read 4, iclass 35, count 0 2006.260.07:38:21.75#ibcon#read 4, iclass 35, count 0 2006.260.07:38:21.75#ibcon#about to read 5, iclass 35, count 0 2006.260.07:38:21.75#ibcon#read 5, iclass 35, count 0 2006.260.07:38:21.75#ibcon#about to read 6, iclass 35, count 0 2006.260.07:38:21.75#ibcon#read 6, iclass 35, count 0 2006.260.07:38:21.75#ibcon#end of sib2, iclass 35, count 0 2006.260.07:38:21.75#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:38:21.75#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:38:21.75#ibcon#[25=USB\r\n] 2006.260.07:38:21.75#ibcon#*before write, iclass 35, count 0 2006.260.07:38:21.75#ibcon#enter sib2, iclass 35, count 0 2006.260.07:38:21.75#ibcon#flushed, iclass 35, count 0 2006.260.07:38:21.75#ibcon#about to write, iclass 35, count 0 2006.260.07:38:21.75#ibcon#wrote, iclass 35, count 0 2006.260.07:38:21.75#ibcon#about to read 3, iclass 35, count 0 2006.260.07:38:21.78#ibcon#read 3, iclass 35, count 0 2006.260.07:38:21.78#ibcon#about to read 4, iclass 35, count 0 2006.260.07:38:21.78#ibcon#read 4, iclass 35, count 0 2006.260.07:38:21.78#ibcon#about to read 5, iclass 35, count 0 2006.260.07:38:21.78#ibcon#read 5, iclass 35, count 0 2006.260.07:38:21.78#ibcon#about to read 6, iclass 35, count 0 2006.260.07:38:21.78#ibcon#read 6, iclass 35, count 0 2006.260.07:38:21.78#ibcon#end of sib2, iclass 35, count 0 2006.260.07:38:21.78#ibcon#*after write, iclass 35, count 0 2006.260.07:38:21.78#ibcon#*before return 0, iclass 35, count 0 2006.260.07:38:21.78#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:38:21.78#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:38:21.78#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:38:21.78#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:38:21.78$vc4f8/valo=8,852.99 2006.260.07:38:21.78#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.07:38:21.78#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.07:38:21.78#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:21.78#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:38:21.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:38:21.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:38:21.78#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:38:21.78#ibcon#first serial, iclass 37, count 0 2006.260.07:38:21.78#ibcon#enter sib2, iclass 37, count 0 2006.260.07:38:21.78#ibcon#flushed, iclass 37, count 0 2006.260.07:38:21.78#ibcon#about to write, iclass 37, count 0 2006.260.07:38:21.78#ibcon#wrote, iclass 37, count 0 2006.260.07:38:21.78#ibcon#about to read 3, iclass 37, count 0 2006.260.07:38:21.80#ibcon#read 3, iclass 37, count 0 2006.260.07:38:21.80#ibcon#about to read 4, iclass 37, count 0 2006.260.07:38:21.80#ibcon#read 4, iclass 37, count 0 2006.260.07:38:21.80#ibcon#about to read 5, iclass 37, count 0 2006.260.07:38:21.80#ibcon#read 5, iclass 37, count 0 2006.260.07:38:21.80#ibcon#about to read 6, iclass 37, count 0 2006.260.07:38:21.80#ibcon#read 6, iclass 37, count 0 2006.260.07:38:21.80#ibcon#end of sib2, iclass 37, count 0 2006.260.07:38:21.80#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:38:21.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:38:21.80#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:38:21.80#ibcon#*before write, iclass 37, count 0 2006.260.07:38:21.80#ibcon#enter sib2, iclass 37, count 0 2006.260.07:38:21.80#ibcon#flushed, iclass 37, count 0 2006.260.07:38:21.80#ibcon#about to write, iclass 37, count 0 2006.260.07:38:21.80#ibcon#wrote, iclass 37, count 0 2006.260.07:38:21.80#ibcon#about to read 3, iclass 37, count 0 2006.260.07:38:21.84#ibcon#read 3, iclass 37, count 0 2006.260.07:38:21.84#ibcon#about to read 4, iclass 37, count 0 2006.260.07:38:21.84#ibcon#read 4, iclass 37, count 0 2006.260.07:38:21.84#ibcon#about to read 5, iclass 37, count 0 2006.260.07:38:21.84#ibcon#read 5, iclass 37, count 0 2006.260.07:38:21.84#ibcon#about to read 6, iclass 37, count 0 2006.260.07:38:21.84#ibcon#read 6, iclass 37, count 0 2006.260.07:38:21.84#ibcon#end of sib2, iclass 37, count 0 2006.260.07:38:21.84#ibcon#*after write, iclass 37, count 0 2006.260.07:38:21.84#ibcon#*before return 0, iclass 37, count 0 2006.260.07:38:21.84#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:38:21.84#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:38:21.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:38:21.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:38:21.84$vc4f8/va=8,6 2006.260.07:38:21.84#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.07:38:21.84#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.07:38:21.84#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:21.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:38:21.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:38:21.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:38:21.90#ibcon#enter wrdev, iclass 39, count 2 2006.260.07:38:21.90#ibcon#first serial, iclass 39, count 2 2006.260.07:38:21.90#ibcon#enter sib2, iclass 39, count 2 2006.260.07:38:21.90#ibcon#flushed, iclass 39, count 2 2006.260.07:38:21.90#ibcon#about to write, iclass 39, count 2 2006.260.07:38:21.90#ibcon#wrote, iclass 39, count 2 2006.260.07:38:21.90#ibcon#about to read 3, iclass 39, count 2 2006.260.07:38:21.92#ibcon#read 3, iclass 39, count 2 2006.260.07:38:21.92#ibcon#about to read 4, iclass 39, count 2 2006.260.07:38:21.92#ibcon#read 4, iclass 39, count 2 2006.260.07:38:21.92#ibcon#about to read 5, iclass 39, count 2 2006.260.07:38:21.92#ibcon#read 5, iclass 39, count 2 2006.260.07:38:21.92#ibcon#about to read 6, iclass 39, count 2 2006.260.07:38:21.92#ibcon#read 6, iclass 39, count 2 2006.260.07:38:21.92#ibcon#end of sib2, iclass 39, count 2 2006.260.07:38:21.92#ibcon#*mode == 0, iclass 39, count 2 2006.260.07:38:21.92#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.07:38:21.92#ibcon#[25=AT08-06\r\n] 2006.260.07:38:21.92#ibcon#*before write, iclass 39, count 2 2006.260.07:38:21.92#ibcon#enter sib2, iclass 39, count 2 2006.260.07:38:21.92#ibcon#flushed, iclass 39, count 2 2006.260.07:38:21.92#ibcon#about to write, iclass 39, count 2 2006.260.07:38:21.92#ibcon#wrote, iclass 39, count 2 2006.260.07:38:21.92#ibcon#about to read 3, iclass 39, count 2 2006.260.07:38:21.95#ibcon#read 3, iclass 39, count 2 2006.260.07:38:21.95#ibcon#about to read 4, iclass 39, count 2 2006.260.07:38:21.95#ibcon#read 4, iclass 39, count 2 2006.260.07:38:21.95#ibcon#about to read 5, iclass 39, count 2 2006.260.07:38:21.95#ibcon#read 5, iclass 39, count 2 2006.260.07:38:21.95#ibcon#about to read 6, iclass 39, count 2 2006.260.07:38:21.95#ibcon#read 6, iclass 39, count 2 2006.260.07:38:21.95#ibcon#end of sib2, iclass 39, count 2 2006.260.07:38:21.95#ibcon#*after write, iclass 39, count 2 2006.260.07:38:21.95#ibcon#*before return 0, iclass 39, count 2 2006.260.07:38:21.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:38:21.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:38:21.95#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.07:38:21.95#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:21.95#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:38:22.07#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:38:22.07#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:38:22.07#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:38:22.07#ibcon#first serial, iclass 39, count 0 2006.260.07:38:22.07#ibcon#enter sib2, iclass 39, count 0 2006.260.07:38:22.07#ibcon#flushed, iclass 39, count 0 2006.260.07:38:22.07#ibcon#about to write, iclass 39, count 0 2006.260.07:38:22.07#ibcon#wrote, iclass 39, count 0 2006.260.07:38:22.07#ibcon#about to read 3, iclass 39, count 0 2006.260.07:38:22.09#ibcon#read 3, iclass 39, count 0 2006.260.07:38:22.09#ibcon#about to read 4, iclass 39, count 0 2006.260.07:38:22.09#ibcon#read 4, iclass 39, count 0 2006.260.07:38:22.09#ibcon#about to read 5, iclass 39, count 0 2006.260.07:38:22.09#ibcon#read 5, iclass 39, count 0 2006.260.07:38:22.09#ibcon#about to read 6, iclass 39, count 0 2006.260.07:38:22.09#ibcon#read 6, iclass 39, count 0 2006.260.07:38:22.09#ibcon#end of sib2, iclass 39, count 0 2006.260.07:38:22.09#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:38:22.09#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:38:22.09#ibcon#[25=USB\r\n] 2006.260.07:38:22.09#ibcon#*before write, iclass 39, count 0 2006.260.07:38:22.09#ibcon#enter sib2, iclass 39, count 0 2006.260.07:38:22.09#ibcon#flushed, iclass 39, count 0 2006.260.07:38:22.09#ibcon#about to write, iclass 39, count 0 2006.260.07:38:22.09#ibcon#wrote, iclass 39, count 0 2006.260.07:38:22.09#ibcon#about to read 3, iclass 39, count 0 2006.260.07:38:22.12#ibcon#read 3, iclass 39, count 0 2006.260.07:38:22.12#ibcon#about to read 4, iclass 39, count 0 2006.260.07:38:22.12#ibcon#read 4, iclass 39, count 0 2006.260.07:38:22.12#ibcon#about to read 5, iclass 39, count 0 2006.260.07:38:22.12#ibcon#read 5, iclass 39, count 0 2006.260.07:38:22.12#ibcon#about to read 6, iclass 39, count 0 2006.260.07:38:22.12#ibcon#read 6, iclass 39, count 0 2006.260.07:38:22.12#ibcon#end of sib2, iclass 39, count 0 2006.260.07:38:22.12#ibcon#*after write, iclass 39, count 0 2006.260.07:38:22.12#ibcon#*before return 0, iclass 39, count 0 2006.260.07:38:22.12#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:38:22.12#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:38:22.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:38:22.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:38:22.12$vc4f8/vblo=1,632.99 2006.260.07:38:22.12#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:38:22.12#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:38:22.12#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:22.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:38:22.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:38:22.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:38:22.12#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:38:22.12#ibcon#first serial, iclass 3, count 0 2006.260.07:38:22.12#ibcon#enter sib2, iclass 3, count 0 2006.260.07:38:22.12#ibcon#flushed, iclass 3, count 0 2006.260.07:38:22.12#ibcon#about to write, iclass 3, count 0 2006.260.07:38:22.12#ibcon#wrote, iclass 3, count 0 2006.260.07:38:22.12#ibcon#about to read 3, iclass 3, count 0 2006.260.07:38:22.14#ibcon#read 3, iclass 3, count 0 2006.260.07:38:22.14#ibcon#about to read 4, iclass 3, count 0 2006.260.07:38:22.14#ibcon#read 4, iclass 3, count 0 2006.260.07:38:22.14#ibcon#about to read 5, iclass 3, count 0 2006.260.07:38:22.14#ibcon#read 5, iclass 3, count 0 2006.260.07:38:22.14#ibcon#about to read 6, iclass 3, count 0 2006.260.07:38:22.14#ibcon#read 6, iclass 3, count 0 2006.260.07:38:22.14#ibcon#end of sib2, iclass 3, count 0 2006.260.07:38:22.14#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:38:22.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:38:22.14#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:38:22.14#ibcon#*before write, iclass 3, count 0 2006.260.07:38:22.14#ibcon#enter sib2, iclass 3, count 0 2006.260.07:38:22.14#ibcon#flushed, iclass 3, count 0 2006.260.07:38:22.14#ibcon#about to write, iclass 3, count 0 2006.260.07:38:22.14#ibcon#wrote, iclass 3, count 0 2006.260.07:38:22.14#ibcon#about to read 3, iclass 3, count 0 2006.260.07:38:22.18#ibcon#read 3, iclass 3, count 0 2006.260.07:38:22.18#ibcon#about to read 4, iclass 3, count 0 2006.260.07:38:22.18#ibcon#read 4, iclass 3, count 0 2006.260.07:38:22.18#ibcon#about to read 5, iclass 3, count 0 2006.260.07:38:22.18#ibcon#read 5, iclass 3, count 0 2006.260.07:38:22.18#ibcon#about to read 6, iclass 3, count 0 2006.260.07:38:22.18#ibcon#read 6, iclass 3, count 0 2006.260.07:38:22.18#ibcon#end of sib2, iclass 3, count 0 2006.260.07:38:22.18#ibcon#*after write, iclass 3, count 0 2006.260.07:38:22.18#ibcon#*before return 0, iclass 3, count 0 2006.260.07:38:22.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:38:22.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:38:22.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:38:22.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:38:22.18$vc4f8/vb=1,4 2006.260.07:38:22.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.07:38:22.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.07:38:22.18#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:22.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:38:22.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:38:22.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:38:22.18#ibcon#enter wrdev, iclass 5, count 2 2006.260.07:38:22.18#ibcon#first serial, iclass 5, count 2 2006.260.07:38:22.18#ibcon#enter sib2, iclass 5, count 2 2006.260.07:38:22.18#ibcon#flushed, iclass 5, count 2 2006.260.07:38:22.18#ibcon#about to write, iclass 5, count 2 2006.260.07:38:22.18#ibcon#wrote, iclass 5, count 2 2006.260.07:38:22.18#ibcon#about to read 3, iclass 5, count 2 2006.260.07:38:22.20#ibcon#read 3, iclass 5, count 2 2006.260.07:38:22.20#ibcon#about to read 4, iclass 5, count 2 2006.260.07:38:22.20#ibcon#read 4, iclass 5, count 2 2006.260.07:38:22.20#ibcon#about to read 5, iclass 5, count 2 2006.260.07:38:22.20#ibcon#read 5, iclass 5, count 2 2006.260.07:38:22.20#ibcon#about to read 6, iclass 5, count 2 2006.260.07:38:22.20#ibcon#read 6, iclass 5, count 2 2006.260.07:38:22.20#ibcon#end of sib2, iclass 5, count 2 2006.260.07:38:22.20#ibcon#*mode == 0, iclass 5, count 2 2006.260.07:38:22.20#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.07:38:22.20#ibcon#[27=AT01-04\r\n] 2006.260.07:38:22.20#ibcon#*before write, iclass 5, count 2 2006.260.07:38:22.20#ibcon#enter sib2, iclass 5, count 2 2006.260.07:38:22.20#ibcon#flushed, iclass 5, count 2 2006.260.07:38:22.20#ibcon#about to write, iclass 5, count 2 2006.260.07:38:22.20#ibcon#wrote, iclass 5, count 2 2006.260.07:38:22.20#ibcon#about to read 3, iclass 5, count 2 2006.260.07:38:22.23#ibcon#read 3, iclass 5, count 2 2006.260.07:38:22.23#ibcon#about to read 4, iclass 5, count 2 2006.260.07:38:22.23#ibcon#read 4, iclass 5, count 2 2006.260.07:38:22.23#ibcon#about to read 5, iclass 5, count 2 2006.260.07:38:22.23#ibcon#read 5, iclass 5, count 2 2006.260.07:38:22.23#ibcon#about to read 6, iclass 5, count 2 2006.260.07:38:22.23#ibcon#read 6, iclass 5, count 2 2006.260.07:38:22.23#ibcon#end of sib2, iclass 5, count 2 2006.260.07:38:22.23#ibcon#*after write, iclass 5, count 2 2006.260.07:38:22.23#ibcon#*before return 0, iclass 5, count 2 2006.260.07:38:22.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:38:22.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:38:22.23#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.07:38:22.23#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:22.23#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:38:22.35#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:38:22.35#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:38:22.35#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:38:22.35#ibcon#first serial, iclass 5, count 0 2006.260.07:38:22.35#ibcon#enter sib2, iclass 5, count 0 2006.260.07:38:22.35#ibcon#flushed, iclass 5, count 0 2006.260.07:38:22.35#ibcon#about to write, iclass 5, count 0 2006.260.07:38:22.35#ibcon#wrote, iclass 5, count 0 2006.260.07:38:22.35#ibcon#about to read 3, iclass 5, count 0 2006.260.07:38:22.37#ibcon#read 3, iclass 5, count 0 2006.260.07:38:22.37#ibcon#about to read 4, iclass 5, count 0 2006.260.07:38:22.37#ibcon#read 4, iclass 5, count 0 2006.260.07:38:22.37#ibcon#about to read 5, iclass 5, count 0 2006.260.07:38:22.37#ibcon#read 5, iclass 5, count 0 2006.260.07:38:22.37#ibcon#about to read 6, iclass 5, count 0 2006.260.07:38:22.37#ibcon#read 6, iclass 5, count 0 2006.260.07:38:22.37#ibcon#end of sib2, iclass 5, count 0 2006.260.07:38:22.37#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:38:22.37#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:38:22.37#ibcon#[27=USB\r\n] 2006.260.07:38:22.37#ibcon#*before write, iclass 5, count 0 2006.260.07:38:22.37#ibcon#enter sib2, iclass 5, count 0 2006.260.07:38:22.37#ibcon#flushed, iclass 5, count 0 2006.260.07:38:22.37#ibcon#about to write, iclass 5, count 0 2006.260.07:38:22.37#ibcon#wrote, iclass 5, count 0 2006.260.07:38:22.37#ibcon#about to read 3, iclass 5, count 0 2006.260.07:38:22.40#ibcon#read 3, iclass 5, count 0 2006.260.07:38:22.40#ibcon#about to read 4, iclass 5, count 0 2006.260.07:38:22.40#ibcon#read 4, iclass 5, count 0 2006.260.07:38:22.40#ibcon#about to read 5, iclass 5, count 0 2006.260.07:38:22.40#ibcon#read 5, iclass 5, count 0 2006.260.07:38:22.40#ibcon#about to read 6, iclass 5, count 0 2006.260.07:38:22.40#ibcon#read 6, iclass 5, count 0 2006.260.07:38:22.40#ibcon#end of sib2, iclass 5, count 0 2006.260.07:38:22.40#ibcon#*after write, iclass 5, count 0 2006.260.07:38:22.40#ibcon#*before return 0, iclass 5, count 0 2006.260.07:38:22.40#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:38:22.40#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:38:22.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:38:22.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:38:22.40$vc4f8/vblo=2,640.99 2006.260.07:38:22.40#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:38:22.40#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:38:22.40#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:22.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:22.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:22.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:22.40#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:38:22.40#ibcon#first serial, iclass 7, count 0 2006.260.07:38:22.40#ibcon#enter sib2, iclass 7, count 0 2006.260.07:38:22.40#ibcon#flushed, iclass 7, count 0 2006.260.07:38:22.40#ibcon#about to write, iclass 7, count 0 2006.260.07:38:22.40#ibcon#wrote, iclass 7, count 0 2006.260.07:38:22.40#ibcon#about to read 3, iclass 7, count 0 2006.260.07:38:22.42#ibcon#read 3, iclass 7, count 0 2006.260.07:38:22.42#ibcon#about to read 4, iclass 7, count 0 2006.260.07:38:22.42#ibcon#read 4, iclass 7, count 0 2006.260.07:38:22.42#ibcon#about to read 5, iclass 7, count 0 2006.260.07:38:22.42#ibcon#read 5, iclass 7, count 0 2006.260.07:38:22.42#ibcon#about to read 6, iclass 7, count 0 2006.260.07:38:22.42#ibcon#read 6, iclass 7, count 0 2006.260.07:38:22.42#ibcon#end of sib2, iclass 7, count 0 2006.260.07:38:22.42#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:38:22.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:38:22.42#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:38:22.42#ibcon#*before write, iclass 7, count 0 2006.260.07:38:22.42#ibcon#enter sib2, iclass 7, count 0 2006.260.07:38:22.42#ibcon#flushed, iclass 7, count 0 2006.260.07:38:22.42#ibcon#about to write, iclass 7, count 0 2006.260.07:38:22.42#ibcon#wrote, iclass 7, count 0 2006.260.07:38:22.42#ibcon#about to read 3, iclass 7, count 0 2006.260.07:38:22.46#ibcon#read 3, iclass 7, count 0 2006.260.07:38:22.46#ibcon#about to read 4, iclass 7, count 0 2006.260.07:38:22.46#ibcon#read 4, iclass 7, count 0 2006.260.07:38:22.46#ibcon#about to read 5, iclass 7, count 0 2006.260.07:38:22.46#ibcon#read 5, iclass 7, count 0 2006.260.07:38:22.46#ibcon#about to read 6, iclass 7, count 0 2006.260.07:38:22.46#ibcon#read 6, iclass 7, count 0 2006.260.07:38:22.46#ibcon#end of sib2, iclass 7, count 0 2006.260.07:38:22.46#ibcon#*after write, iclass 7, count 0 2006.260.07:38:22.46#ibcon#*before return 0, iclass 7, count 0 2006.260.07:38:22.46#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:22.46#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:38:22.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:38:22.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:38:22.46$vc4f8/vb=2,5 2006.260.07:38:22.46#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:38:22.46#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:38:22.46#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:22.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:22.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:22.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:22.52#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:38:22.52#ibcon#first serial, iclass 11, count 2 2006.260.07:38:22.52#ibcon#enter sib2, iclass 11, count 2 2006.260.07:38:22.52#ibcon#flushed, iclass 11, count 2 2006.260.07:38:22.52#ibcon#about to write, iclass 11, count 2 2006.260.07:38:22.52#ibcon#wrote, iclass 11, count 2 2006.260.07:38:22.52#ibcon#about to read 3, iclass 11, count 2 2006.260.07:38:22.54#ibcon#read 3, iclass 11, count 2 2006.260.07:38:22.54#ibcon#about to read 4, iclass 11, count 2 2006.260.07:38:22.54#ibcon#read 4, iclass 11, count 2 2006.260.07:38:22.54#ibcon#about to read 5, iclass 11, count 2 2006.260.07:38:22.54#ibcon#read 5, iclass 11, count 2 2006.260.07:38:22.54#ibcon#about to read 6, iclass 11, count 2 2006.260.07:38:22.54#ibcon#read 6, iclass 11, count 2 2006.260.07:38:22.54#ibcon#end of sib2, iclass 11, count 2 2006.260.07:38:22.54#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:38:22.54#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:38:22.54#ibcon#[27=AT02-05\r\n] 2006.260.07:38:22.54#ibcon#*before write, iclass 11, count 2 2006.260.07:38:22.54#ibcon#enter sib2, iclass 11, count 2 2006.260.07:38:22.54#ibcon#flushed, iclass 11, count 2 2006.260.07:38:22.54#ibcon#about to write, iclass 11, count 2 2006.260.07:38:22.54#ibcon#wrote, iclass 11, count 2 2006.260.07:38:22.54#ibcon#about to read 3, iclass 11, count 2 2006.260.07:38:22.57#ibcon#read 3, iclass 11, count 2 2006.260.07:38:22.57#ibcon#about to read 4, iclass 11, count 2 2006.260.07:38:22.57#ibcon#read 4, iclass 11, count 2 2006.260.07:38:22.57#ibcon#about to read 5, iclass 11, count 2 2006.260.07:38:22.57#ibcon#read 5, iclass 11, count 2 2006.260.07:38:22.57#ibcon#about to read 6, iclass 11, count 2 2006.260.07:38:22.57#ibcon#read 6, iclass 11, count 2 2006.260.07:38:22.57#ibcon#end of sib2, iclass 11, count 2 2006.260.07:38:22.57#ibcon#*after write, iclass 11, count 2 2006.260.07:38:22.57#ibcon#*before return 0, iclass 11, count 2 2006.260.07:38:22.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:22.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:38:22.57#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:38:22.57#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:22.57#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:22.69#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:22.69#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:22.69#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:38:22.69#ibcon#first serial, iclass 11, count 0 2006.260.07:38:22.69#ibcon#enter sib2, iclass 11, count 0 2006.260.07:38:22.69#ibcon#flushed, iclass 11, count 0 2006.260.07:38:22.69#ibcon#about to write, iclass 11, count 0 2006.260.07:38:22.69#ibcon#wrote, iclass 11, count 0 2006.260.07:38:22.69#ibcon#about to read 3, iclass 11, count 0 2006.260.07:38:22.71#ibcon#read 3, iclass 11, count 0 2006.260.07:38:22.71#ibcon#about to read 4, iclass 11, count 0 2006.260.07:38:22.71#ibcon#read 4, iclass 11, count 0 2006.260.07:38:22.71#ibcon#about to read 5, iclass 11, count 0 2006.260.07:38:22.71#ibcon#read 5, iclass 11, count 0 2006.260.07:38:22.71#ibcon#about to read 6, iclass 11, count 0 2006.260.07:38:22.71#ibcon#read 6, iclass 11, count 0 2006.260.07:38:22.71#ibcon#end of sib2, iclass 11, count 0 2006.260.07:38:22.71#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:38:22.71#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:38:22.71#ibcon#[27=USB\r\n] 2006.260.07:38:22.71#ibcon#*before write, iclass 11, count 0 2006.260.07:38:22.71#ibcon#enter sib2, iclass 11, count 0 2006.260.07:38:22.71#ibcon#flushed, iclass 11, count 0 2006.260.07:38:22.71#ibcon#about to write, iclass 11, count 0 2006.260.07:38:22.71#ibcon#wrote, iclass 11, count 0 2006.260.07:38:22.71#ibcon#about to read 3, iclass 11, count 0 2006.260.07:38:22.74#ibcon#read 3, iclass 11, count 0 2006.260.07:38:22.74#ibcon#about to read 4, iclass 11, count 0 2006.260.07:38:22.74#ibcon#read 4, iclass 11, count 0 2006.260.07:38:22.74#ibcon#about to read 5, iclass 11, count 0 2006.260.07:38:22.74#ibcon#read 5, iclass 11, count 0 2006.260.07:38:22.74#ibcon#about to read 6, iclass 11, count 0 2006.260.07:38:22.74#ibcon#read 6, iclass 11, count 0 2006.260.07:38:22.74#ibcon#end of sib2, iclass 11, count 0 2006.260.07:38:22.74#ibcon#*after write, iclass 11, count 0 2006.260.07:38:22.74#ibcon#*before return 0, iclass 11, count 0 2006.260.07:38:22.74#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:22.74#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:38:22.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:38:22.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:38:22.74$vc4f8/vblo=3,656.99 2006.260.07:38:22.74#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:38:22.74#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:38:22.74#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:22.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:22.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:22.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:22.74#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:38:22.74#ibcon#first serial, iclass 13, count 0 2006.260.07:38:22.74#ibcon#enter sib2, iclass 13, count 0 2006.260.07:38:22.74#ibcon#flushed, iclass 13, count 0 2006.260.07:38:22.74#ibcon#about to write, iclass 13, count 0 2006.260.07:38:22.74#ibcon#wrote, iclass 13, count 0 2006.260.07:38:22.74#ibcon#about to read 3, iclass 13, count 0 2006.260.07:38:22.76#ibcon#read 3, iclass 13, count 0 2006.260.07:38:22.76#ibcon#about to read 4, iclass 13, count 0 2006.260.07:38:22.76#ibcon#read 4, iclass 13, count 0 2006.260.07:38:22.76#ibcon#about to read 5, iclass 13, count 0 2006.260.07:38:22.76#ibcon#read 5, iclass 13, count 0 2006.260.07:38:22.76#ibcon#about to read 6, iclass 13, count 0 2006.260.07:38:22.76#ibcon#read 6, iclass 13, count 0 2006.260.07:38:22.76#ibcon#end of sib2, iclass 13, count 0 2006.260.07:38:22.76#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:38:22.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:38:22.76#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:38:22.76#ibcon#*before write, iclass 13, count 0 2006.260.07:38:22.76#ibcon#enter sib2, iclass 13, count 0 2006.260.07:38:22.76#ibcon#flushed, iclass 13, count 0 2006.260.07:38:22.76#ibcon#about to write, iclass 13, count 0 2006.260.07:38:22.76#ibcon#wrote, iclass 13, count 0 2006.260.07:38:22.76#ibcon#about to read 3, iclass 13, count 0 2006.260.07:38:22.80#ibcon#read 3, iclass 13, count 0 2006.260.07:38:22.80#ibcon#about to read 4, iclass 13, count 0 2006.260.07:38:22.80#ibcon#read 4, iclass 13, count 0 2006.260.07:38:22.80#ibcon#about to read 5, iclass 13, count 0 2006.260.07:38:22.80#ibcon#read 5, iclass 13, count 0 2006.260.07:38:22.80#ibcon#about to read 6, iclass 13, count 0 2006.260.07:38:22.80#ibcon#read 6, iclass 13, count 0 2006.260.07:38:22.80#ibcon#end of sib2, iclass 13, count 0 2006.260.07:38:22.80#ibcon#*after write, iclass 13, count 0 2006.260.07:38:22.80#ibcon#*before return 0, iclass 13, count 0 2006.260.07:38:22.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:22.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:38:22.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:38:22.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:38:22.80$vc4f8/vb=3,4 2006.260.07:38:22.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:38:22.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:38:22.80#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:22.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:22.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:22.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:22.86#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:38:22.86#ibcon#first serial, iclass 15, count 2 2006.260.07:38:22.86#ibcon#enter sib2, iclass 15, count 2 2006.260.07:38:22.86#ibcon#flushed, iclass 15, count 2 2006.260.07:38:22.86#ibcon#about to write, iclass 15, count 2 2006.260.07:38:22.86#ibcon#wrote, iclass 15, count 2 2006.260.07:38:22.86#ibcon#about to read 3, iclass 15, count 2 2006.260.07:38:22.88#ibcon#read 3, iclass 15, count 2 2006.260.07:38:22.88#ibcon#about to read 4, iclass 15, count 2 2006.260.07:38:22.88#ibcon#read 4, iclass 15, count 2 2006.260.07:38:22.88#ibcon#about to read 5, iclass 15, count 2 2006.260.07:38:22.88#ibcon#read 5, iclass 15, count 2 2006.260.07:38:22.88#ibcon#about to read 6, iclass 15, count 2 2006.260.07:38:22.88#ibcon#read 6, iclass 15, count 2 2006.260.07:38:22.88#ibcon#end of sib2, iclass 15, count 2 2006.260.07:38:22.88#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:38:22.88#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:38:22.88#ibcon#[27=AT03-04\r\n] 2006.260.07:38:22.88#ibcon#*before write, iclass 15, count 2 2006.260.07:38:22.88#ibcon#enter sib2, iclass 15, count 2 2006.260.07:38:22.88#ibcon#flushed, iclass 15, count 2 2006.260.07:38:22.88#ibcon#about to write, iclass 15, count 2 2006.260.07:38:22.88#ibcon#wrote, iclass 15, count 2 2006.260.07:38:22.88#ibcon#about to read 3, iclass 15, count 2 2006.260.07:38:22.91#ibcon#read 3, iclass 15, count 2 2006.260.07:38:22.91#ibcon#about to read 4, iclass 15, count 2 2006.260.07:38:22.91#ibcon#read 4, iclass 15, count 2 2006.260.07:38:22.91#ibcon#about to read 5, iclass 15, count 2 2006.260.07:38:22.91#ibcon#read 5, iclass 15, count 2 2006.260.07:38:22.91#ibcon#about to read 6, iclass 15, count 2 2006.260.07:38:22.91#ibcon#read 6, iclass 15, count 2 2006.260.07:38:22.91#ibcon#end of sib2, iclass 15, count 2 2006.260.07:38:22.91#ibcon#*after write, iclass 15, count 2 2006.260.07:38:22.91#ibcon#*before return 0, iclass 15, count 2 2006.260.07:38:22.91#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:22.91#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:38:22.91#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:38:22.91#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:22.91#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:23.03#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:23.03#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:23.03#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:38:23.03#ibcon#first serial, iclass 15, count 0 2006.260.07:38:23.03#ibcon#enter sib2, iclass 15, count 0 2006.260.07:38:23.03#ibcon#flushed, iclass 15, count 0 2006.260.07:38:23.03#ibcon#about to write, iclass 15, count 0 2006.260.07:38:23.03#ibcon#wrote, iclass 15, count 0 2006.260.07:38:23.03#ibcon#about to read 3, iclass 15, count 0 2006.260.07:38:23.05#ibcon#read 3, iclass 15, count 0 2006.260.07:38:23.05#ibcon#about to read 4, iclass 15, count 0 2006.260.07:38:23.05#ibcon#read 4, iclass 15, count 0 2006.260.07:38:23.05#ibcon#about to read 5, iclass 15, count 0 2006.260.07:38:23.05#ibcon#read 5, iclass 15, count 0 2006.260.07:38:23.05#ibcon#about to read 6, iclass 15, count 0 2006.260.07:38:23.05#ibcon#read 6, iclass 15, count 0 2006.260.07:38:23.05#ibcon#end of sib2, iclass 15, count 0 2006.260.07:38:23.05#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:38:23.05#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:38:23.05#ibcon#[27=USB\r\n] 2006.260.07:38:23.05#ibcon#*before write, iclass 15, count 0 2006.260.07:38:23.05#ibcon#enter sib2, iclass 15, count 0 2006.260.07:38:23.05#ibcon#flushed, iclass 15, count 0 2006.260.07:38:23.05#ibcon#about to write, iclass 15, count 0 2006.260.07:38:23.05#ibcon#wrote, iclass 15, count 0 2006.260.07:38:23.05#ibcon#about to read 3, iclass 15, count 0 2006.260.07:38:23.08#ibcon#read 3, iclass 15, count 0 2006.260.07:38:23.08#ibcon#about to read 4, iclass 15, count 0 2006.260.07:38:23.08#ibcon#read 4, iclass 15, count 0 2006.260.07:38:23.08#ibcon#about to read 5, iclass 15, count 0 2006.260.07:38:23.08#ibcon#read 5, iclass 15, count 0 2006.260.07:38:23.08#ibcon#about to read 6, iclass 15, count 0 2006.260.07:38:23.08#ibcon#read 6, iclass 15, count 0 2006.260.07:38:23.08#ibcon#end of sib2, iclass 15, count 0 2006.260.07:38:23.08#ibcon#*after write, iclass 15, count 0 2006.260.07:38:23.08#ibcon#*before return 0, iclass 15, count 0 2006.260.07:38:23.08#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:23.08#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:38:23.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:38:23.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:38:23.08$vc4f8/vblo=4,712.99 2006.260.07:38:23.08#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.07:38:23.08#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.07:38:23.08#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:23.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:23.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:23.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:23.08#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:38:23.08#ibcon#first serial, iclass 17, count 0 2006.260.07:38:23.08#ibcon#enter sib2, iclass 17, count 0 2006.260.07:38:23.08#ibcon#flushed, iclass 17, count 0 2006.260.07:38:23.08#ibcon#about to write, iclass 17, count 0 2006.260.07:38:23.08#ibcon#wrote, iclass 17, count 0 2006.260.07:38:23.08#ibcon#about to read 3, iclass 17, count 0 2006.260.07:38:23.10#ibcon#read 3, iclass 17, count 0 2006.260.07:38:23.10#ibcon#about to read 4, iclass 17, count 0 2006.260.07:38:23.10#ibcon#read 4, iclass 17, count 0 2006.260.07:38:23.10#ibcon#about to read 5, iclass 17, count 0 2006.260.07:38:23.10#ibcon#read 5, iclass 17, count 0 2006.260.07:38:23.10#ibcon#about to read 6, iclass 17, count 0 2006.260.07:38:23.10#ibcon#read 6, iclass 17, count 0 2006.260.07:38:23.10#ibcon#end of sib2, iclass 17, count 0 2006.260.07:38:23.10#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:38:23.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:38:23.10#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:38:23.10#ibcon#*before write, iclass 17, count 0 2006.260.07:38:23.10#ibcon#enter sib2, iclass 17, count 0 2006.260.07:38:23.10#ibcon#flushed, iclass 17, count 0 2006.260.07:38:23.10#ibcon#about to write, iclass 17, count 0 2006.260.07:38:23.10#ibcon#wrote, iclass 17, count 0 2006.260.07:38:23.10#ibcon#about to read 3, iclass 17, count 0 2006.260.07:38:23.14#ibcon#read 3, iclass 17, count 0 2006.260.07:38:23.14#ibcon#about to read 4, iclass 17, count 0 2006.260.07:38:23.14#ibcon#read 4, iclass 17, count 0 2006.260.07:38:23.14#ibcon#about to read 5, iclass 17, count 0 2006.260.07:38:23.14#ibcon#read 5, iclass 17, count 0 2006.260.07:38:23.14#ibcon#about to read 6, iclass 17, count 0 2006.260.07:38:23.14#ibcon#read 6, iclass 17, count 0 2006.260.07:38:23.14#ibcon#end of sib2, iclass 17, count 0 2006.260.07:38:23.14#ibcon#*after write, iclass 17, count 0 2006.260.07:38:23.14#ibcon#*before return 0, iclass 17, count 0 2006.260.07:38:23.14#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:23.14#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:38:23.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:38:23.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:38:23.14$vc4f8/vb=4,5 2006.260.07:38:23.14#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.07:38:23.14#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.07:38:23.14#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:23.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:23.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:23.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:23.20#ibcon#enter wrdev, iclass 19, count 2 2006.260.07:38:23.20#ibcon#first serial, iclass 19, count 2 2006.260.07:38:23.20#ibcon#enter sib2, iclass 19, count 2 2006.260.07:38:23.20#ibcon#flushed, iclass 19, count 2 2006.260.07:38:23.20#ibcon#about to write, iclass 19, count 2 2006.260.07:38:23.20#ibcon#wrote, iclass 19, count 2 2006.260.07:38:23.20#ibcon#about to read 3, iclass 19, count 2 2006.260.07:38:23.22#ibcon#read 3, iclass 19, count 2 2006.260.07:38:23.22#ibcon#about to read 4, iclass 19, count 2 2006.260.07:38:23.22#ibcon#read 4, iclass 19, count 2 2006.260.07:38:23.22#ibcon#about to read 5, iclass 19, count 2 2006.260.07:38:23.22#ibcon#read 5, iclass 19, count 2 2006.260.07:38:23.22#ibcon#about to read 6, iclass 19, count 2 2006.260.07:38:23.22#ibcon#read 6, iclass 19, count 2 2006.260.07:38:23.22#ibcon#end of sib2, iclass 19, count 2 2006.260.07:38:23.22#ibcon#*mode == 0, iclass 19, count 2 2006.260.07:38:23.22#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.07:38:23.22#ibcon#[27=AT04-05\r\n] 2006.260.07:38:23.22#ibcon#*before write, iclass 19, count 2 2006.260.07:38:23.22#ibcon#enter sib2, iclass 19, count 2 2006.260.07:38:23.22#ibcon#flushed, iclass 19, count 2 2006.260.07:38:23.22#ibcon#about to write, iclass 19, count 2 2006.260.07:38:23.22#ibcon#wrote, iclass 19, count 2 2006.260.07:38:23.22#ibcon#about to read 3, iclass 19, count 2 2006.260.07:38:23.25#ibcon#read 3, iclass 19, count 2 2006.260.07:38:23.25#ibcon#about to read 4, iclass 19, count 2 2006.260.07:38:23.25#ibcon#read 4, iclass 19, count 2 2006.260.07:38:23.25#ibcon#about to read 5, iclass 19, count 2 2006.260.07:38:23.25#ibcon#read 5, iclass 19, count 2 2006.260.07:38:23.25#ibcon#about to read 6, iclass 19, count 2 2006.260.07:38:23.25#ibcon#read 6, iclass 19, count 2 2006.260.07:38:23.25#ibcon#end of sib2, iclass 19, count 2 2006.260.07:38:23.25#ibcon#*after write, iclass 19, count 2 2006.260.07:38:23.25#ibcon#*before return 0, iclass 19, count 2 2006.260.07:38:23.25#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:23.25#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:38:23.25#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.07:38:23.25#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:23.25#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:23.37#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:23.37#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:23.37#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:38:23.37#ibcon#first serial, iclass 19, count 0 2006.260.07:38:23.37#ibcon#enter sib2, iclass 19, count 0 2006.260.07:38:23.37#ibcon#flushed, iclass 19, count 0 2006.260.07:38:23.37#ibcon#about to write, iclass 19, count 0 2006.260.07:38:23.37#ibcon#wrote, iclass 19, count 0 2006.260.07:38:23.37#ibcon#about to read 3, iclass 19, count 0 2006.260.07:38:23.39#ibcon#read 3, iclass 19, count 0 2006.260.07:38:23.39#ibcon#about to read 4, iclass 19, count 0 2006.260.07:38:23.39#ibcon#read 4, iclass 19, count 0 2006.260.07:38:23.39#ibcon#about to read 5, iclass 19, count 0 2006.260.07:38:23.39#ibcon#read 5, iclass 19, count 0 2006.260.07:38:23.39#ibcon#about to read 6, iclass 19, count 0 2006.260.07:38:23.39#ibcon#read 6, iclass 19, count 0 2006.260.07:38:23.39#ibcon#end of sib2, iclass 19, count 0 2006.260.07:38:23.39#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:38:23.39#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:38:23.39#ibcon#[27=USB\r\n] 2006.260.07:38:23.39#ibcon#*before write, iclass 19, count 0 2006.260.07:38:23.39#ibcon#enter sib2, iclass 19, count 0 2006.260.07:38:23.39#ibcon#flushed, iclass 19, count 0 2006.260.07:38:23.39#ibcon#about to write, iclass 19, count 0 2006.260.07:38:23.39#ibcon#wrote, iclass 19, count 0 2006.260.07:38:23.39#ibcon#about to read 3, iclass 19, count 0 2006.260.07:38:23.42#ibcon#read 3, iclass 19, count 0 2006.260.07:38:23.42#ibcon#about to read 4, iclass 19, count 0 2006.260.07:38:23.42#ibcon#read 4, iclass 19, count 0 2006.260.07:38:23.42#ibcon#about to read 5, iclass 19, count 0 2006.260.07:38:23.42#ibcon#read 5, iclass 19, count 0 2006.260.07:38:23.42#ibcon#about to read 6, iclass 19, count 0 2006.260.07:38:23.42#ibcon#read 6, iclass 19, count 0 2006.260.07:38:23.42#ibcon#end of sib2, iclass 19, count 0 2006.260.07:38:23.42#ibcon#*after write, iclass 19, count 0 2006.260.07:38:23.42#ibcon#*before return 0, iclass 19, count 0 2006.260.07:38:23.42#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:23.42#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:38:23.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:38:23.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:38:23.42$vc4f8/vblo=5,744.99 2006.260.07:38:23.42#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.07:38:23.42#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.07:38:23.42#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:23.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:23.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:23.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:23.42#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:38:23.42#ibcon#first serial, iclass 21, count 0 2006.260.07:38:23.42#ibcon#enter sib2, iclass 21, count 0 2006.260.07:38:23.42#ibcon#flushed, iclass 21, count 0 2006.260.07:38:23.42#ibcon#about to write, iclass 21, count 0 2006.260.07:38:23.42#ibcon#wrote, iclass 21, count 0 2006.260.07:38:23.42#ibcon#about to read 3, iclass 21, count 0 2006.260.07:38:23.44#ibcon#read 3, iclass 21, count 0 2006.260.07:38:23.44#ibcon#about to read 4, iclass 21, count 0 2006.260.07:38:23.44#ibcon#read 4, iclass 21, count 0 2006.260.07:38:23.44#ibcon#about to read 5, iclass 21, count 0 2006.260.07:38:23.44#ibcon#read 5, iclass 21, count 0 2006.260.07:38:23.44#ibcon#about to read 6, iclass 21, count 0 2006.260.07:38:23.44#ibcon#read 6, iclass 21, count 0 2006.260.07:38:23.44#ibcon#end of sib2, iclass 21, count 0 2006.260.07:38:23.44#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:38:23.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:38:23.44#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:38:23.44#ibcon#*before write, iclass 21, count 0 2006.260.07:38:23.44#ibcon#enter sib2, iclass 21, count 0 2006.260.07:38:23.44#ibcon#flushed, iclass 21, count 0 2006.260.07:38:23.44#ibcon#about to write, iclass 21, count 0 2006.260.07:38:23.44#ibcon#wrote, iclass 21, count 0 2006.260.07:38:23.44#ibcon#about to read 3, iclass 21, count 0 2006.260.07:38:23.48#ibcon#read 3, iclass 21, count 0 2006.260.07:38:23.48#ibcon#about to read 4, iclass 21, count 0 2006.260.07:38:23.48#ibcon#read 4, iclass 21, count 0 2006.260.07:38:23.48#ibcon#about to read 5, iclass 21, count 0 2006.260.07:38:23.48#ibcon#read 5, iclass 21, count 0 2006.260.07:38:23.48#ibcon#about to read 6, iclass 21, count 0 2006.260.07:38:23.48#ibcon#read 6, iclass 21, count 0 2006.260.07:38:23.48#ibcon#end of sib2, iclass 21, count 0 2006.260.07:38:23.48#ibcon#*after write, iclass 21, count 0 2006.260.07:38:23.48#ibcon#*before return 0, iclass 21, count 0 2006.260.07:38:23.48#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:23.48#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:38:23.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:38:23.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:38:23.48$vc4f8/vb=5,4 2006.260.07:38:23.48#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.07:38:23.48#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.07:38:23.48#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:23.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:23.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:23.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:23.54#ibcon#enter wrdev, iclass 23, count 2 2006.260.07:38:23.54#ibcon#first serial, iclass 23, count 2 2006.260.07:38:23.54#ibcon#enter sib2, iclass 23, count 2 2006.260.07:38:23.54#ibcon#flushed, iclass 23, count 2 2006.260.07:38:23.54#ibcon#about to write, iclass 23, count 2 2006.260.07:38:23.54#ibcon#wrote, iclass 23, count 2 2006.260.07:38:23.54#ibcon#about to read 3, iclass 23, count 2 2006.260.07:38:23.56#ibcon#read 3, iclass 23, count 2 2006.260.07:38:23.56#ibcon#about to read 4, iclass 23, count 2 2006.260.07:38:23.56#ibcon#read 4, iclass 23, count 2 2006.260.07:38:23.56#ibcon#about to read 5, iclass 23, count 2 2006.260.07:38:23.56#ibcon#read 5, iclass 23, count 2 2006.260.07:38:23.56#ibcon#about to read 6, iclass 23, count 2 2006.260.07:38:23.56#ibcon#read 6, iclass 23, count 2 2006.260.07:38:23.56#ibcon#end of sib2, iclass 23, count 2 2006.260.07:38:23.56#ibcon#*mode == 0, iclass 23, count 2 2006.260.07:38:23.56#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.07:38:23.56#ibcon#[27=AT05-04\r\n] 2006.260.07:38:23.56#ibcon#*before write, iclass 23, count 2 2006.260.07:38:23.56#ibcon#enter sib2, iclass 23, count 2 2006.260.07:38:23.56#ibcon#flushed, iclass 23, count 2 2006.260.07:38:23.56#ibcon#about to write, iclass 23, count 2 2006.260.07:38:23.56#ibcon#wrote, iclass 23, count 2 2006.260.07:38:23.56#ibcon#about to read 3, iclass 23, count 2 2006.260.07:38:23.59#ibcon#read 3, iclass 23, count 2 2006.260.07:38:23.59#ibcon#about to read 4, iclass 23, count 2 2006.260.07:38:23.59#ibcon#read 4, iclass 23, count 2 2006.260.07:38:23.59#ibcon#about to read 5, iclass 23, count 2 2006.260.07:38:23.59#ibcon#read 5, iclass 23, count 2 2006.260.07:38:23.59#ibcon#about to read 6, iclass 23, count 2 2006.260.07:38:23.59#ibcon#read 6, iclass 23, count 2 2006.260.07:38:23.59#ibcon#end of sib2, iclass 23, count 2 2006.260.07:38:23.59#ibcon#*after write, iclass 23, count 2 2006.260.07:38:23.59#ibcon#*before return 0, iclass 23, count 2 2006.260.07:38:23.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:23.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:38:23.59#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.07:38:23.59#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:23.59#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:23.71#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:23.71#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:23.71#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:38:23.71#ibcon#first serial, iclass 23, count 0 2006.260.07:38:23.71#ibcon#enter sib2, iclass 23, count 0 2006.260.07:38:23.71#ibcon#flushed, iclass 23, count 0 2006.260.07:38:23.71#ibcon#about to write, iclass 23, count 0 2006.260.07:38:23.71#ibcon#wrote, iclass 23, count 0 2006.260.07:38:23.71#ibcon#about to read 3, iclass 23, count 0 2006.260.07:38:23.73#ibcon#read 3, iclass 23, count 0 2006.260.07:38:23.73#ibcon#about to read 4, iclass 23, count 0 2006.260.07:38:23.73#ibcon#read 4, iclass 23, count 0 2006.260.07:38:23.73#ibcon#about to read 5, iclass 23, count 0 2006.260.07:38:23.73#ibcon#read 5, iclass 23, count 0 2006.260.07:38:23.73#ibcon#about to read 6, iclass 23, count 0 2006.260.07:38:23.73#ibcon#read 6, iclass 23, count 0 2006.260.07:38:23.73#ibcon#end of sib2, iclass 23, count 0 2006.260.07:38:23.73#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:38:23.73#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:38:23.73#ibcon#[27=USB\r\n] 2006.260.07:38:23.73#ibcon#*before write, iclass 23, count 0 2006.260.07:38:23.73#ibcon#enter sib2, iclass 23, count 0 2006.260.07:38:23.73#ibcon#flushed, iclass 23, count 0 2006.260.07:38:23.73#ibcon#about to write, iclass 23, count 0 2006.260.07:38:23.73#ibcon#wrote, iclass 23, count 0 2006.260.07:38:23.73#ibcon#about to read 3, iclass 23, count 0 2006.260.07:38:23.76#ibcon#read 3, iclass 23, count 0 2006.260.07:38:23.76#ibcon#about to read 4, iclass 23, count 0 2006.260.07:38:23.76#ibcon#read 4, iclass 23, count 0 2006.260.07:38:23.76#ibcon#about to read 5, iclass 23, count 0 2006.260.07:38:23.76#ibcon#read 5, iclass 23, count 0 2006.260.07:38:23.76#ibcon#about to read 6, iclass 23, count 0 2006.260.07:38:23.76#ibcon#read 6, iclass 23, count 0 2006.260.07:38:23.76#ibcon#end of sib2, iclass 23, count 0 2006.260.07:38:23.76#ibcon#*after write, iclass 23, count 0 2006.260.07:38:23.76#ibcon#*before return 0, iclass 23, count 0 2006.260.07:38:23.76#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:23.76#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:38:23.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:38:23.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:38:23.76$vc4f8/vblo=6,752.99 2006.260.07:38:23.76#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.07:38:23.76#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.07:38:23.76#ibcon#ireg 17 cls_cnt 0 2006.260.07:38:23.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:23.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:23.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:23.76#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:38:23.76#ibcon#first serial, iclass 25, count 0 2006.260.07:38:23.76#ibcon#enter sib2, iclass 25, count 0 2006.260.07:38:23.76#ibcon#flushed, iclass 25, count 0 2006.260.07:38:23.76#ibcon#about to write, iclass 25, count 0 2006.260.07:38:23.76#ibcon#wrote, iclass 25, count 0 2006.260.07:38:23.76#ibcon#about to read 3, iclass 25, count 0 2006.260.07:38:23.78#ibcon#read 3, iclass 25, count 0 2006.260.07:38:23.78#ibcon#about to read 4, iclass 25, count 0 2006.260.07:38:23.78#ibcon#read 4, iclass 25, count 0 2006.260.07:38:23.78#ibcon#about to read 5, iclass 25, count 0 2006.260.07:38:23.78#ibcon#read 5, iclass 25, count 0 2006.260.07:38:23.78#ibcon#about to read 6, iclass 25, count 0 2006.260.07:38:23.78#ibcon#read 6, iclass 25, count 0 2006.260.07:38:23.78#ibcon#end of sib2, iclass 25, count 0 2006.260.07:38:23.78#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:38:23.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:38:23.78#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:38:23.78#ibcon#*before write, iclass 25, count 0 2006.260.07:38:23.78#ibcon#enter sib2, iclass 25, count 0 2006.260.07:38:23.78#ibcon#flushed, iclass 25, count 0 2006.260.07:38:23.78#ibcon#about to write, iclass 25, count 0 2006.260.07:38:23.78#ibcon#wrote, iclass 25, count 0 2006.260.07:38:23.78#ibcon#about to read 3, iclass 25, count 0 2006.260.07:38:23.82#ibcon#read 3, iclass 25, count 0 2006.260.07:38:23.82#ibcon#about to read 4, iclass 25, count 0 2006.260.07:38:23.82#ibcon#read 4, iclass 25, count 0 2006.260.07:38:23.82#ibcon#about to read 5, iclass 25, count 0 2006.260.07:38:23.82#ibcon#read 5, iclass 25, count 0 2006.260.07:38:23.82#ibcon#about to read 6, iclass 25, count 0 2006.260.07:38:23.82#ibcon#read 6, iclass 25, count 0 2006.260.07:38:23.82#ibcon#end of sib2, iclass 25, count 0 2006.260.07:38:23.82#ibcon#*after write, iclass 25, count 0 2006.260.07:38:23.82#ibcon#*before return 0, iclass 25, count 0 2006.260.07:38:23.82#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:23.82#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:38:23.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:38:23.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:38:23.82$vc4f8/vb=6,4 2006.260.07:38:23.82#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.07:38:23.82#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.07:38:23.82#ibcon#ireg 11 cls_cnt 2 2006.260.07:38:23.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:23.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:23.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:23.88#ibcon#enter wrdev, iclass 27, count 2 2006.260.07:38:23.88#ibcon#first serial, iclass 27, count 2 2006.260.07:38:23.88#ibcon#enter sib2, iclass 27, count 2 2006.260.07:38:23.88#ibcon#flushed, iclass 27, count 2 2006.260.07:38:23.88#ibcon#about to write, iclass 27, count 2 2006.260.07:38:23.88#ibcon#wrote, iclass 27, count 2 2006.260.07:38:23.88#ibcon#about to read 3, iclass 27, count 2 2006.260.07:38:23.90#ibcon#read 3, iclass 27, count 2 2006.260.07:38:23.90#ibcon#about to read 4, iclass 27, count 2 2006.260.07:38:23.90#ibcon#read 4, iclass 27, count 2 2006.260.07:38:23.90#ibcon#about to read 5, iclass 27, count 2 2006.260.07:38:23.90#ibcon#read 5, iclass 27, count 2 2006.260.07:38:23.90#ibcon#about to read 6, iclass 27, count 2 2006.260.07:38:23.90#ibcon#read 6, iclass 27, count 2 2006.260.07:38:23.90#ibcon#end of sib2, iclass 27, count 2 2006.260.07:38:23.90#ibcon#*mode == 0, iclass 27, count 2 2006.260.07:38:23.90#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.07:38:23.90#ibcon#[27=AT06-04\r\n] 2006.260.07:38:23.90#ibcon#*before write, iclass 27, count 2 2006.260.07:38:23.90#ibcon#enter sib2, iclass 27, count 2 2006.260.07:38:23.90#ibcon#flushed, iclass 27, count 2 2006.260.07:38:23.90#ibcon#about to write, iclass 27, count 2 2006.260.07:38:23.90#ibcon#wrote, iclass 27, count 2 2006.260.07:38:23.90#ibcon#about to read 3, iclass 27, count 2 2006.260.07:38:23.93#ibcon#read 3, iclass 27, count 2 2006.260.07:38:23.93#ibcon#about to read 4, iclass 27, count 2 2006.260.07:38:23.93#ibcon#read 4, iclass 27, count 2 2006.260.07:38:23.93#ibcon#about to read 5, iclass 27, count 2 2006.260.07:38:23.93#ibcon#read 5, iclass 27, count 2 2006.260.07:38:23.93#ibcon#about to read 6, iclass 27, count 2 2006.260.07:38:23.93#ibcon#read 6, iclass 27, count 2 2006.260.07:38:23.93#ibcon#end of sib2, iclass 27, count 2 2006.260.07:38:23.93#ibcon#*after write, iclass 27, count 2 2006.260.07:38:23.93#ibcon#*before return 0, iclass 27, count 2 2006.260.07:38:23.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:23.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:38:23.93#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.07:38:23.93#ibcon#ireg 7 cls_cnt 0 2006.260.07:38:23.93#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:24.05#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:24.05#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:24.05#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:38:24.05#ibcon#first serial, iclass 27, count 0 2006.260.07:38:24.05#ibcon#enter sib2, iclass 27, count 0 2006.260.07:38:24.05#ibcon#flushed, iclass 27, count 0 2006.260.07:38:24.05#ibcon#about to write, iclass 27, count 0 2006.260.07:38:24.05#ibcon#wrote, iclass 27, count 0 2006.260.07:38:24.05#ibcon#about to read 3, iclass 27, count 0 2006.260.07:38:24.07#ibcon#read 3, iclass 27, count 0 2006.260.07:38:24.07#ibcon#about to read 4, iclass 27, count 0 2006.260.07:38:24.07#ibcon#read 4, iclass 27, count 0 2006.260.07:38:24.07#ibcon#about to read 5, iclass 27, count 0 2006.260.07:38:24.07#ibcon#read 5, iclass 27, count 0 2006.260.07:38:24.07#ibcon#about to read 6, iclass 27, count 0 2006.260.07:38:24.07#ibcon#read 6, iclass 27, count 0 2006.260.07:38:24.07#ibcon#end of sib2, iclass 27, count 0 2006.260.07:38:24.07#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:38:24.07#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:38:24.07#ibcon#[27=USB\r\n] 2006.260.07:38:24.07#ibcon#*before write, iclass 27, count 0 2006.260.07:38:24.07#ibcon#enter sib2, iclass 27, count 0 2006.260.07:38:24.07#ibcon#flushed, iclass 27, count 0 2006.260.07:38:24.07#ibcon#about to write, iclass 27, count 0 2006.260.07:38:24.07#ibcon#wrote, iclass 27, count 0 2006.260.07:38:24.07#ibcon#about to read 3, iclass 27, count 0 2006.260.07:38:24.10#ibcon#read 3, iclass 27, count 0 2006.260.07:38:24.10#ibcon#about to read 4, iclass 27, count 0 2006.260.07:38:24.10#ibcon#read 4, iclass 27, count 0 2006.260.07:38:24.10#ibcon#about to read 5, iclass 27, count 0 2006.260.07:38:24.10#ibcon#read 5, iclass 27, count 0 2006.260.07:38:24.10#ibcon#about to read 6, iclass 27, count 0 2006.260.07:38:24.10#ibcon#read 6, iclass 27, count 0 2006.260.07:38:24.10#ibcon#end of sib2, iclass 27, count 0 2006.260.07:38:24.10#ibcon#*after write, iclass 27, count 0 2006.260.07:38:24.10#ibcon#*before return 0, iclass 27, count 0 2006.260.07:38:24.10#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:24.10#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:38:24.10#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:38:24.10#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:38:24.10$vc4f8/vabw=wide 2006.260.07:38:24.10#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.07:38:24.10#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.07:38:24.10#ibcon#ireg 8 cls_cnt 0 2006.260.07:38:24.10#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:24.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:24.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:24.10#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:38:24.10#ibcon#first serial, iclass 29, count 0 2006.260.07:38:24.10#ibcon#enter sib2, iclass 29, count 0 2006.260.07:38:24.10#ibcon#flushed, iclass 29, count 0 2006.260.07:38:24.10#ibcon#about to write, iclass 29, count 0 2006.260.07:38:24.10#ibcon#wrote, iclass 29, count 0 2006.260.07:38:24.10#ibcon#about to read 3, iclass 29, count 0 2006.260.07:38:24.12#ibcon#read 3, iclass 29, count 0 2006.260.07:38:24.12#ibcon#about to read 4, iclass 29, count 0 2006.260.07:38:24.12#ibcon#read 4, iclass 29, count 0 2006.260.07:38:24.12#ibcon#about to read 5, iclass 29, count 0 2006.260.07:38:24.12#ibcon#read 5, iclass 29, count 0 2006.260.07:38:24.12#ibcon#about to read 6, iclass 29, count 0 2006.260.07:38:24.12#ibcon#read 6, iclass 29, count 0 2006.260.07:38:24.12#ibcon#end of sib2, iclass 29, count 0 2006.260.07:38:24.12#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:38:24.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:38:24.12#ibcon#[25=BW32\r\n] 2006.260.07:38:24.12#ibcon#*before write, iclass 29, count 0 2006.260.07:38:24.12#ibcon#enter sib2, iclass 29, count 0 2006.260.07:38:24.12#ibcon#flushed, iclass 29, count 0 2006.260.07:38:24.12#ibcon#about to write, iclass 29, count 0 2006.260.07:38:24.12#ibcon#wrote, iclass 29, count 0 2006.260.07:38:24.12#ibcon#about to read 3, iclass 29, count 0 2006.260.07:38:24.15#ibcon#read 3, iclass 29, count 0 2006.260.07:38:24.15#ibcon#about to read 4, iclass 29, count 0 2006.260.07:38:24.15#ibcon#read 4, iclass 29, count 0 2006.260.07:38:24.15#ibcon#about to read 5, iclass 29, count 0 2006.260.07:38:24.15#ibcon#read 5, iclass 29, count 0 2006.260.07:38:24.15#ibcon#about to read 6, iclass 29, count 0 2006.260.07:38:24.15#ibcon#read 6, iclass 29, count 0 2006.260.07:38:24.15#ibcon#end of sib2, iclass 29, count 0 2006.260.07:38:24.15#ibcon#*after write, iclass 29, count 0 2006.260.07:38:24.15#ibcon#*before return 0, iclass 29, count 0 2006.260.07:38:24.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:24.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:38:24.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:38:24.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:38:24.15$vc4f8/vbbw=wide 2006.260.07:38:24.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:38:24.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:38:24.15#ibcon#ireg 8 cls_cnt 0 2006.260.07:38:24.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:38:24.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:38:24.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:38:24.22#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:38:24.22#ibcon#first serial, iclass 31, count 0 2006.260.07:38:24.22#ibcon#enter sib2, iclass 31, count 0 2006.260.07:38:24.22#ibcon#flushed, iclass 31, count 0 2006.260.07:38:24.22#ibcon#about to write, iclass 31, count 0 2006.260.07:38:24.22#ibcon#wrote, iclass 31, count 0 2006.260.07:38:24.22#ibcon#about to read 3, iclass 31, count 0 2006.260.07:38:24.24#ibcon#read 3, iclass 31, count 0 2006.260.07:38:24.24#ibcon#about to read 4, iclass 31, count 0 2006.260.07:38:24.24#ibcon#read 4, iclass 31, count 0 2006.260.07:38:24.24#ibcon#about to read 5, iclass 31, count 0 2006.260.07:38:24.24#ibcon#read 5, iclass 31, count 0 2006.260.07:38:24.24#ibcon#about to read 6, iclass 31, count 0 2006.260.07:38:24.24#ibcon#read 6, iclass 31, count 0 2006.260.07:38:24.24#ibcon#end of sib2, iclass 31, count 0 2006.260.07:38:24.24#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:38:24.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:38:24.24#ibcon#[27=BW32\r\n] 2006.260.07:38:24.24#ibcon#*before write, iclass 31, count 0 2006.260.07:38:24.24#ibcon#enter sib2, iclass 31, count 0 2006.260.07:38:24.24#ibcon#flushed, iclass 31, count 0 2006.260.07:38:24.24#ibcon#about to write, iclass 31, count 0 2006.260.07:38:24.24#ibcon#wrote, iclass 31, count 0 2006.260.07:38:24.24#ibcon#about to read 3, iclass 31, count 0 2006.260.07:38:24.27#ibcon#read 3, iclass 31, count 0 2006.260.07:38:24.27#ibcon#about to read 4, iclass 31, count 0 2006.260.07:38:24.27#ibcon#read 4, iclass 31, count 0 2006.260.07:38:24.27#ibcon#about to read 5, iclass 31, count 0 2006.260.07:38:24.27#ibcon#read 5, iclass 31, count 0 2006.260.07:38:24.27#ibcon#about to read 6, iclass 31, count 0 2006.260.07:38:24.27#ibcon#read 6, iclass 31, count 0 2006.260.07:38:24.27#ibcon#end of sib2, iclass 31, count 0 2006.260.07:38:24.27#ibcon#*after write, iclass 31, count 0 2006.260.07:38:24.27#ibcon#*before return 0, iclass 31, count 0 2006.260.07:38:24.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:38:24.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:38:24.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:38:24.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:38:24.27$4f8m12a/ifd4f 2006.260.07:38:24.27$ifd4f/lo= 2006.260.07:38:24.27$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:38:24.27$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:38:24.27$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:38:24.27$ifd4f/patch= 2006.260.07:38:24.27$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:38:24.27$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:38:24.27$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:38:24.27$4f8m12a/"form=m,16.000,1:2 2006.260.07:38:24.27$4f8m12a/"tpicd 2006.260.07:38:24.27$4f8m12a/echo=off 2006.260.07:38:24.27$4f8m12a/xlog=off 2006.260.07:38:24.27:!2006.260.07:38:50 2006.260.07:38:33.14#trakl#Source acquired 2006.260.07:38:35.14#flagr#flagr/antenna,acquired 2006.260.07:38:50.00:preob 2006.260.07:38:51.14/onsource/TRACKING 2006.260.07:38:51.14:!2006.260.07:39:00 2006.260.07:39:00.00:data_valid=on 2006.260.07:39:00.00:midob 2006.260.07:39:00.14/onsource/TRACKING 2006.260.07:39:00.14/wx/23.10,1010.3,86 2006.260.07:39:00.24/cable/+6.4561E-03 2006.260.07:39:01.33/va/01,08,usb,yes,31,32 2006.260.07:39:01.33/va/02,07,usb,yes,30,32 2006.260.07:39:01.33/va/03,08,usb,yes,23,23 2006.260.07:39:01.33/va/04,07,usb,yes,32,34 2006.260.07:39:01.33/va/05,07,usb,yes,35,37 2006.260.07:39:01.33/va/06,06,usb,yes,34,34 2006.260.07:39:01.33/va/07,06,usb,yes,35,34 2006.260.07:39:01.33/va/08,06,usb,yes,37,36 2006.260.07:39:01.56/valo/01,532.99,yes,locked 2006.260.07:39:01.56/valo/02,572.99,yes,locked 2006.260.07:39:01.56/valo/03,672.99,yes,locked 2006.260.07:39:01.56/valo/04,832.99,yes,locked 2006.260.07:39:01.56/valo/05,652.99,yes,locked 2006.260.07:39:01.56/valo/06,772.99,yes,locked 2006.260.07:39:01.56/valo/07,832.99,yes,locked 2006.260.07:39:01.56/valo/08,852.99,yes,locked 2006.260.07:39:02.65/vb/01,04,usb,yes,30,29 2006.260.07:39:02.65/vb/02,05,usb,yes,28,29 2006.260.07:39:02.65/vb/03,04,usb,yes,28,32 2006.260.07:39:02.65/vb/04,05,usb,yes,25,26 2006.260.07:39:02.65/vb/05,04,usb,yes,27,31 2006.260.07:39:02.65/vb/06,04,usb,yes,28,31 2006.260.07:39:02.65/vb/07,04,usb,yes,30,30 2006.260.07:39:02.65/vb/08,04,usb,yes,28,31 2006.260.07:39:02.88/vblo/01,632.99,yes,locked 2006.260.07:39:02.88/vblo/02,640.99,yes,locked 2006.260.07:39:02.88/vblo/03,656.99,yes,locked 2006.260.07:39:02.88/vblo/04,712.99,yes,locked 2006.260.07:39:02.88/vblo/05,744.99,yes,locked 2006.260.07:39:02.88/vblo/06,752.99,yes,locked 2006.260.07:39:02.88/vblo/07,734.99,yes,locked 2006.260.07:39:02.88/vblo/08,744.99,yes,locked 2006.260.07:39:03.03/vabw/8 2006.260.07:39:03.18/vbbw/8 2006.260.07:39:03.27/xfe/off,on,15.0 2006.260.07:39:03.65/ifatt/23,28,28,28 2006.260.07:39:04.08/fmout-gps/S +4.51E-07 2006.260.07:39:04.12:!2006.260.07:40:00 2006.260.07:40:00.00:data_valid=off 2006.260.07:40:00.00:postob 2006.260.07:40:00.08/cable/+6.4566E-03 2006.260.07:40:00.08/wx/23.08,1010.3,86 2006.260.07:40:01.08/fmout-gps/S +4.51E-07 2006.260.07:40:01.08:scan_name=260-0740,k06260,60 2006.260.07:40:01.09:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.260.07:40:01.14#flagr#flagr/antenna,new-source 2006.260.07:40:02.14:checkk5 2006.260.07:40:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:40:03.02/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:40:03.46/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:40:04.09/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:40:04.49/chk_obsdata//k5ts1/T2600739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:40:04.99/chk_obsdata//k5ts2/T2600739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:40:05.38/chk_obsdata//k5ts3/T2600739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:40:05.79/chk_obsdata//k5ts4/T2600739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:40:06.53/k5log//k5ts1_log_newline 2006.260.07:40:07.37/k5log//k5ts2_log_newline 2006.260.07:40:08.37/k5log//k5ts3_log_newline 2006.260.07:40:09.10/k5log//k5ts4_log_newline 2006.260.07:40:09.13/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:40:09.13:4f8m12a=1 2006.260.07:40:09.13$4f8m12a/echo=on 2006.260.07:40:09.13$4f8m12a/pcalon 2006.260.07:40:09.13$pcalon/"no phase cal control is implemented here 2006.260.07:40:09.13$4f8m12a/"tpicd=stop 2006.260.07:40:09.13$4f8m12a/vc4f8 2006.260.07:40:09.13$vc4f8/valo=1,532.99 2006.260.07:40:09.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:40:09.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:40:09.14#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:09.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:09.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:09.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:09.14#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:40:09.14#ibcon#first serial, iclass 4, count 0 2006.260.07:40:09.14#ibcon#enter sib2, iclass 4, count 0 2006.260.07:40:09.14#ibcon#flushed, iclass 4, count 0 2006.260.07:40:09.14#ibcon#about to write, iclass 4, count 0 2006.260.07:40:09.14#ibcon#wrote, iclass 4, count 0 2006.260.07:40:09.14#ibcon#about to read 3, iclass 4, count 0 2006.260.07:40:09.18#ibcon#read 3, iclass 4, count 0 2006.260.07:40:09.18#ibcon#about to read 4, iclass 4, count 0 2006.260.07:40:09.18#ibcon#read 4, iclass 4, count 0 2006.260.07:40:09.18#ibcon#about to read 5, iclass 4, count 0 2006.260.07:40:09.18#ibcon#read 5, iclass 4, count 0 2006.260.07:40:09.18#ibcon#about to read 6, iclass 4, count 0 2006.260.07:40:09.18#ibcon#read 6, iclass 4, count 0 2006.260.07:40:09.18#ibcon#end of sib2, iclass 4, count 0 2006.260.07:40:09.18#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:40:09.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:40:09.18#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:40:09.18#ibcon#*before write, iclass 4, count 0 2006.260.07:40:09.18#ibcon#enter sib2, iclass 4, count 0 2006.260.07:40:09.18#ibcon#flushed, iclass 4, count 0 2006.260.07:40:09.18#ibcon#about to write, iclass 4, count 0 2006.260.07:40:09.18#ibcon#wrote, iclass 4, count 0 2006.260.07:40:09.18#ibcon#about to read 3, iclass 4, count 0 2006.260.07:40:09.22#ibcon#read 3, iclass 4, count 0 2006.260.07:40:09.22#ibcon#about to read 4, iclass 4, count 0 2006.260.07:40:09.22#ibcon#read 4, iclass 4, count 0 2006.260.07:40:09.22#ibcon#about to read 5, iclass 4, count 0 2006.260.07:40:09.22#ibcon#read 5, iclass 4, count 0 2006.260.07:40:09.22#ibcon#about to read 6, iclass 4, count 0 2006.260.07:40:09.22#ibcon#read 6, iclass 4, count 0 2006.260.07:40:09.22#ibcon#end of sib2, iclass 4, count 0 2006.260.07:40:09.22#ibcon#*after write, iclass 4, count 0 2006.260.07:40:09.22#ibcon#*before return 0, iclass 4, count 0 2006.260.07:40:09.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:09.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:09.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:40:09.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:40:09.22$vc4f8/va=1,8 2006.260.07:40:09.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:40:09.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:40:09.22#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:09.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:09.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:09.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:09.22#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:40:09.22#ibcon#first serial, iclass 6, count 2 2006.260.07:40:09.22#ibcon#enter sib2, iclass 6, count 2 2006.260.07:40:09.22#ibcon#flushed, iclass 6, count 2 2006.260.07:40:09.22#ibcon#about to write, iclass 6, count 2 2006.260.07:40:09.22#ibcon#wrote, iclass 6, count 2 2006.260.07:40:09.22#ibcon#about to read 3, iclass 6, count 2 2006.260.07:40:09.24#ibcon#read 3, iclass 6, count 2 2006.260.07:40:09.24#ibcon#about to read 4, iclass 6, count 2 2006.260.07:40:09.24#ibcon#read 4, iclass 6, count 2 2006.260.07:40:09.24#ibcon#about to read 5, iclass 6, count 2 2006.260.07:40:09.24#ibcon#read 5, iclass 6, count 2 2006.260.07:40:09.24#ibcon#about to read 6, iclass 6, count 2 2006.260.07:40:09.24#ibcon#read 6, iclass 6, count 2 2006.260.07:40:09.24#ibcon#end of sib2, iclass 6, count 2 2006.260.07:40:09.24#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:40:09.24#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:40:09.24#ibcon#[25=AT01-08\r\n] 2006.260.07:40:09.24#ibcon#*before write, iclass 6, count 2 2006.260.07:40:09.24#ibcon#enter sib2, iclass 6, count 2 2006.260.07:40:09.24#ibcon#flushed, iclass 6, count 2 2006.260.07:40:09.24#ibcon#about to write, iclass 6, count 2 2006.260.07:40:09.24#ibcon#wrote, iclass 6, count 2 2006.260.07:40:09.24#ibcon#about to read 3, iclass 6, count 2 2006.260.07:40:09.27#ibcon#read 3, iclass 6, count 2 2006.260.07:40:09.27#ibcon#about to read 4, iclass 6, count 2 2006.260.07:40:09.27#ibcon#read 4, iclass 6, count 2 2006.260.07:40:09.27#ibcon#about to read 5, iclass 6, count 2 2006.260.07:40:09.27#ibcon#read 5, iclass 6, count 2 2006.260.07:40:09.27#ibcon#about to read 6, iclass 6, count 2 2006.260.07:40:09.27#ibcon#read 6, iclass 6, count 2 2006.260.07:40:09.27#ibcon#end of sib2, iclass 6, count 2 2006.260.07:40:09.27#ibcon#*after write, iclass 6, count 2 2006.260.07:40:09.27#ibcon#*before return 0, iclass 6, count 2 2006.260.07:40:09.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:09.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:09.27#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:40:09.27#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:09.27#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:09.39#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:09.39#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:09.39#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:40:09.39#ibcon#first serial, iclass 6, count 0 2006.260.07:40:09.39#ibcon#enter sib2, iclass 6, count 0 2006.260.07:40:09.39#ibcon#flushed, iclass 6, count 0 2006.260.07:40:09.39#ibcon#about to write, iclass 6, count 0 2006.260.07:40:09.39#ibcon#wrote, iclass 6, count 0 2006.260.07:40:09.39#ibcon#about to read 3, iclass 6, count 0 2006.260.07:40:09.41#ibcon#read 3, iclass 6, count 0 2006.260.07:40:09.41#ibcon#about to read 4, iclass 6, count 0 2006.260.07:40:09.41#ibcon#read 4, iclass 6, count 0 2006.260.07:40:09.41#ibcon#about to read 5, iclass 6, count 0 2006.260.07:40:09.41#ibcon#read 5, iclass 6, count 0 2006.260.07:40:09.41#ibcon#about to read 6, iclass 6, count 0 2006.260.07:40:09.41#ibcon#read 6, iclass 6, count 0 2006.260.07:40:09.41#ibcon#end of sib2, iclass 6, count 0 2006.260.07:40:09.41#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:40:09.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:40:09.41#ibcon#[25=USB\r\n] 2006.260.07:40:09.41#ibcon#*before write, iclass 6, count 0 2006.260.07:40:09.41#ibcon#enter sib2, iclass 6, count 0 2006.260.07:40:09.41#ibcon#flushed, iclass 6, count 0 2006.260.07:40:09.41#ibcon#about to write, iclass 6, count 0 2006.260.07:40:09.41#ibcon#wrote, iclass 6, count 0 2006.260.07:40:09.41#ibcon#about to read 3, iclass 6, count 0 2006.260.07:40:09.44#ibcon#read 3, iclass 6, count 0 2006.260.07:40:09.44#ibcon#about to read 4, iclass 6, count 0 2006.260.07:40:09.44#ibcon#read 4, iclass 6, count 0 2006.260.07:40:09.44#ibcon#about to read 5, iclass 6, count 0 2006.260.07:40:09.44#ibcon#read 5, iclass 6, count 0 2006.260.07:40:09.44#ibcon#about to read 6, iclass 6, count 0 2006.260.07:40:09.44#ibcon#read 6, iclass 6, count 0 2006.260.07:40:09.44#ibcon#end of sib2, iclass 6, count 0 2006.260.07:40:09.44#ibcon#*after write, iclass 6, count 0 2006.260.07:40:09.44#ibcon#*before return 0, iclass 6, count 0 2006.260.07:40:09.44#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:09.44#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:09.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:40:09.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:40:09.44$vc4f8/valo=2,572.99 2006.260.07:40:09.44#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:40:09.44#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:40:09.44#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:09.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:09.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:09.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:09.44#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:40:09.44#ibcon#first serial, iclass 10, count 0 2006.260.07:40:09.44#ibcon#enter sib2, iclass 10, count 0 2006.260.07:40:09.44#ibcon#flushed, iclass 10, count 0 2006.260.07:40:09.44#ibcon#about to write, iclass 10, count 0 2006.260.07:40:09.44#ibcon#wrote, iclass 10, count 0 2006.260.07:40:09.44#ibcon#about to read 3, iclass 10, count 0 2006.260.07:40:09.46#ibcon#read 3, iclass 10, count 0 2006.260.07:40:09.46#ibcon#about to read 4, iclass 10, count 0 2006.260.07:40:09.46#ibcon#read 4, iclass 10, count 0 2006.260.07:40:09.46#ibcon#about to read 5, iclass 10, count 0 2006.260.07:40:09.46#ibcon#read 5, iclass 10, count 0 2006.260.07:40:09.46#ibcon#about to read 6, iclass 10, count 0 2006.260.07:40:09.46#ibcon#read 6, iclass 10, count 0 2006.260.07:40:09.46#ibcon#end of sib2, iclass 10, count 0 2006.260.07:40:09.46#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:40:09.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:40:09.46#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:40:09.46#ibcon#*before write, iclass 10, count 0 2006.260.07:40:09.46#ibcon#enter sib2, iclass 10, count 0 2006.260.07:40:09.46#ibcon#flushed, iclass 10, count 0 2006.260.07:40:09.46#ibcon#about to write, iclass 10, count 0 2006.260.07:40:09.46#ibcon#wrote, iclass 10, count 0 2006.260.07:40:09.46#ibcon#about to read 3, iclass 10, count 0 2006.260.07:40:09.50#ibcon#read 3, iclass 10, count 0 2006.260.07:40:09.50#ibcon#about to read 4, iclass 10, count 0 2006.260.07:40:09.50#ibcon#read 4, iclass 10, count 0 2006.260.07:40:09.50#ibcon#about to read 5, iclass 10, count 0 2006.260.07:40:09.50#ibcon#read 5, iclass 10, count 0 2006.260.07:40:09.50#ibcon#about to read 6, iclass 10, count 0 2006.260.07:40:09.50#ibcon#read 6, iclass 10, count 0 2006.260.07:40:09.50#ibcon#end of sib2, iclass 10, count 0 2006.260.07:40:09.50#ibcon#*after write, iclass 10, count 0 2006.260.07:40:09.50#ibcon#*before return 0, iclass 10, count 0 2006.260.07:40:09.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:09.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:09.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:40:09.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:40:09.50$vc4f8/va=2,7 2006.260.07:40:09.50#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:40:09.50#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:40:09.50#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:09.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:09.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:09.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:09.56#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:40:09.56#ibcon#first serial, iclass 12, count 2 2006.260.07:40:09.56#ibcon#enter sib2, iclass 12, count 2 2006.260.07:40:09.56#ibcon#flushed, iclass 12, count 2 2006.260.07:40:09.56#ibcon#about to write, iclass 12, count 2 2006.260.07:40:09.56#ibcon#wrote, iclass 12, count 2 2006.260.07:40:09.56#ibcon#about to read 3, iclass 12, count 2 2006.260.07:40:09.59#ibcon#read 3, iclass 12, count 2 2006.260.07:40:09.59#ibcon#about to read 4, iclass 12, count 2 2006.260.07:40:09.59#ibcon#read 4, iclass 12, count 2 2006.260.07:40:09.59#ibcon#about to read 5, iclass 12, count 2 2006.260.07:40:09.59#ibcon#read 5, iclass 12, count 2 2006.260.07:40:09.59#ibcon#about to read 6, iclass 12, count 2 2006.260.07:40:09.59#ibcon#read 6, iclass 12, count 2 2006.260.07:40:09.59#ibcon#end of sib2, iclass 12, count 2 2006.260.07:40:09.59#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:40:09.59#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:40:09.59#ibcon#[25=AT02-07\r\n] 2006.260.07:40:09.59#ibcon#*before write, iclass 12, count 2 2006.260.07:40:09.59#ibcon#enter sib2, iclass 12, count 2 2006.260.07:40:09.59#ibcon#flushed, iclass 12, count 2 2006.260.07:40:09.59#ibcon#about to write, iclass 12, count 2 2006.260.07:40:09.59#ibcon#wrote, iclass 12, count 2 2006.260.07:40:09.59#ibcon#about to read 3, iclass 12, count 2 2006.260.07:40:09.62#ibcon#read 3, iclass 12, count 2 2006.260.07:40:09.62#ibcon#about to read 4, iclass 12, count 2 2006.260.07:40:09.62#ibcon#read 4, iclass 12, count 2 2006.260.07:40:09.62#ibcon#about to read 5, iclass 12, count 2 2006.260.07:40:09.62#ibcon#read 5, iclass 12, count 2 2006.260.07:40:09.62#ibcon#about to read 6, iclass 12, count 2 2006.260.07:40:09.62#ibcon#read 6, iclass 12, count 2 2006.260.07:40:09.62#ibcon#end of sib2, iclass 12, count 2 2006.260.07:40:09.62#ibcon#*after write, iclass 12, count 2 2006.260.07:40:09.62#ibcon#*before return 0, iclass 12, count 2 2006.260.07:40:09.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:09.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:09.62#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:40:09.62#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:09.62#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:09.74#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:09.74#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:09.74#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:40:09.74#ibcon#first serial, iclass 12, count 0 2006.260.07:40:09.74#ibcon#enter sib2, iclass 12, count 0 2006.260.07:40:09.74#ibcon#flushed, iclass 12, count 0 2006.260.07:40:09.74#ibcon#about to write, iclass 12, count 0 2006.260.07:40:09.74#ibcon#wrote, iclass 12, count 0 2006.260.07:40:09.74#ibcon#about to read 3, iclass 12, count 0 2006.260.07:40:09.76#ibcon#read 3, iclass 12, count 0 2006.260.07:40:09.76#ibcon#about to read 4, iclass 12, count 0 2006.260.07:40:09.76#ibcon#read 4, iclass 12, count 0 2006.260.07:40:09.76#ibcon#about to read 5, iclass 12, count 0 2006.260.07:40:09.76#ibcon#read 5, iclass 12, count 0 2006.260.07:40:09.76#ibcon#about to read 6, iclass 12, count 0 2006.260.07:40:09.76#ibcon#read 6, iclass 12, count 0 2006.260.07:40:09.76#ibcon#end of sib2, iclass 12, count 0 2006.260.07:40:09.76#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:40:09.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:40:09.76#ibcon#[25=USB\r\n] 2006.260.07:40:09.76#ibcon#*before write, iclass 12, count 0 2006.260.07:40:09.76#ibcon#enter sib2, iclass 12, count 0 2006.260.07:40:09.76#ibcon#flushed, iclass 12, count 0 2006.260.07:40:09.76#ibcon#about to write, iclass 12, count 0 2006.260.07:40:09.76#ibcon#wrote, iclass 12, count 0 2006.260.07:40:09.76#ibcon#about to read 3, iclass 12, count 0 2006.260.07:40:09.79#ibcon#read 3, iclass 12, count 0 2006.260.07:40:09.79#ibcon#about to read 4, iclass 12, count 0 2006.260.07:40:09.79#ibcon#read 4, iclass 12, count 0 2006.260.07:40:09.79#ibcon#about to read 5, iclass 12, count 0 2006.260.07:40:09.79#ibcon#read 5, iclass 12, count 0 2006.260.07:40:09.79#ibcon#about to read 6, iclass 12, count 0 2006.260.07:40:09.79#ibcon#read 6, iclass 12, count 0 2006.260.07:40:09.79#ibcon#end of sib2, iclass 12, count 0 2006.260.07:40:09.79#ibcon#*after write, iclass 12, count 0 2006.260.07:40:09.79#ibcon#*before return 0, iclass 12, count 0 2006.260.07:40:09.79#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:09.79#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:09.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:40:09.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:40:09.79$vc4f8/valo=3,672.99 2006.260.07:40:09.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:40:09.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:40:09.79#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:09.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:09.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:09.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:09.79#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:40:09.79#ibcon#first serial, iclass 14, count 0 2006.260.07:40:09.79#ibcon#enter sib2, iclass 14, count 0 2006.260.07:40:09.79#ibcon#flushed, iclass 14, count 0 2006.260.07:40:09.79#ibcon#about to write, iclass 14, count 0 2006.260.07:40:09.79#ibcon#wrote, iclass 14, count 0 2006.260.07:40:09.79#ibcon#about to read 3, iclass 14, count 0 2006.260.07:40:09.81#ibcon#read 3, iclass 14, count 0 2006.260.07:40:09.81#ibcon#about to read 4, iclass 14, count 0 2006.260.07:40:09.81#ibcon#read 4, iclass 14, count 0 2006.260.07:40:09.81#ibcon#about to read 5, iclass 14, count 0 2006.260.07:40:09.81#ibcon#read 5, iclass 14, count 0 2006.260.07:40:09.81#ibcon#about to read 6, iclass 14, count 0 2006.260.07:40:09.81#ibcon#read 6, iclass 14, count 0 2006.260.07:40:09.81#ibcon#end of sib2, iclass 14, count 0 2006.260.07:40:09.81#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:40:09.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:40:09.81#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:40:09.81#ibcon#*before write, iclass 14, count 0 2006.260.07:40:09.81#ibcon#enter sib2, iclass 14, count 0 2006.260.07:40:09.81#ibcon#flushed, iclass 14, count 0 2006.260.07:40:09.81#ibcon#about to write, iclass 14, count 0 2006.260.07:40:09.81#ibcon#wrote, iclass 14, count 0 2006.260.07:40:09.81#ibcon#about to read 3, iclass 14, count 0 2006.260.07:40:09.85#ibcon#read 3, iclass 14, count 0 2006.260.07:40:09.85#ibcon#about to read 4, iclass 14, count 0 2006.260.07:40:09.85#ibcon#read 4, iclass 14, count 0 2006.260.07:40:09.85#ibcon#about to read 5, iclass 14, count 0 2006.260.07:40:09.85#ibcon#read 5, iclass 14, count 0 2006.260.07:40:09.85#ibcon#about to read 6, iclass 14, count 0 2006.260.07:40:09.85#ibcon#read 6, iclass 14, count 0 2006.260.07:40:09.85#ibcon#end of sib2, iclass 14, count 0 2006.260.07:40:09.85#ibcon#*after write, iclass 14, count 0 2006.260.07:40:09.85#ibcon#*before return 0, iclass 14, count 0 2006.260.07:40:09.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:09.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:09.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:40:09.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:40:09.85$vc4f8/va=3,8 2006.260.07:40:09.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:40:09.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:40:09.85#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:09.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:09.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:09.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:09.91#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:40:09.91#ibcon#first serial, iclass 16, count 2 2006.260.07:40:09.91#ibcon#enter sib2, iclass 16, count 2 2006.260.07:40:09.91#ibcon#flushed, iclass 16, count 2 2006.260.07:40:09.91#ibcon#about to write, iclass 16, count 2 2006.260.07:40:09.91#ibcon#wrote, iclass 16, count 2 2006.260.07:40:09.91#ibcon#about to read 3, iclass 16, count 2 2006.260.07:40:09.94#ibcon#read 3, iclass 16, count 2 2006.260.07:40:09.94#ibcon#about to read 4, iclass 16, count 2 2006.260.07:40:09.94#ibcon#read 4, iclass 16, count 2 2006.260.07:40:09.94#ibcon#about to read 5, iclass 16, count 2 2006.260.07:40:09.94#ibcon#read 5, iclass 16, count 2 2006.260.07:40:09.94#ibcon#about to read 6, iclass 16, count 2 2006.260.07:40:09.94#ibcon#read 6, iclass 16, count 2 2006.260.07:40:09.94#ibcon#end of sib2, iclass 16, count 2 2006.260.07:40:09.94#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:40:09.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:40:09.94#ibcon#[25=AT03-08\r\n] 2006.260.07:40:09.94#ibcon#*before write, iclass 16, count 2 2006.260.07:40:09.94#ibcon#enter sib2, iclass 16, count 2 2006.260.07:40:09.94#ibcon#flushed, iclass 16, count 2 2006.260.07:40:09.94#ibcon#about to write, iclass 16, count 2 2006.260.07:40:09.94#ibcon#wrote, iclass 16, count 2 2006.260.07:40:09.94#ibcon#about to read 3, iclass 16, count 2 2006.260.07:40:09.97#ibcon#read 3, iclass 16, count 2 2006.260.07:40:09.97#ibcon#about to read 4, iclass 16, count 2 2006.260.07:40:09.97#ibcon#read 4, iclass 16, count 2 2006.260.07:40:09.97#ibcon#about to read 5, iclass 16, count 2 2006.260.07:40:09.97#ibcon#read 5, iclass 16, count 2 2006.260.07:40:09.97#ibcon#about to read 6, iclass 16, count 2 2006.260.07:40:09.97#ibcon#read 6, iclass 16, count 2 2006.260.07:40:09.97#ibcon#end of sib2, iclass 16, count 2 2006.260.07:40:09.97#ibcon#*after write, iclass 16, count 2 2006.260.07:40:09.97#ibcon#*before return 0, iclass 16, count 2 2006.260.07:40:09.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:09.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:09.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:40:09.97#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:09.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:10.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:10.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:10.09#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:40:10.09#ibcon#first serial, iclass 16, count 0 2006.260.07:40:10.09#ibcon#enter sib2, iclass 16, count 0 2006.260.07:40:10.09#ibcon#flushed, iclass 16, count 0 2006.260.07:40:10.09#ibcon#about to write, iclass 16, count 0 2006.260.07:40:10.09#ibcon#wrote, iclass 16, count 0 2006.260.07:40:10.09#ibcon#about to read 3, iclass 16, count 0 2006.260.07:40:10.11#ibcon#read 3, iclass 16, count 0 2006.260.07:40:10.11#ibcon#about to read 4, iclass 16, count 0 2006.260.07:40:10.11#ibcon#read 4, iclass 16, count 0 2006.260.07:40:10.11#ibcon#about to read 5, iclass 16, count 0 2006.260.07:40:10.11#ibcon#read 5, iclass 16, count 0 2006.260.07:40:10.11#ibcon#about to read 6, iclass 16, count 0 2006.260.07:40:10.11#ibcon#read 6, iclass 16, count 0 2006.260.07:40:10.11#ibcon#end of sib2, iclass 16, count 0 2006.260.07:40:10.11#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:40:10.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:40:10.11#ibcon#[25=USB\r\n] 2006.260.07:40:10.11#ibcon#*before write, iclass 16, count 0 2006.260.07:40:10.11#ibcon#enter sib2, iclass 16, count 0 2006.260.07:40:10.11#ibcon#flushed, iclass 16, count 0 2006.260.07:40:10.11#ibcon#about to write, iclass 16, count 0 2006.260.07:40:10.11#ibcon#wrote, iclass 16, count 0 2006.260.07:40:10.11#ibcon#about to read 3, iclass 16, count 0 2006.260.07:40:10.14#ibcon#read 3, iclass 16, count 0 2006.260.07:40:10.14#ibcon#about to read 4, iclass 16, count 0 2006.260.07:40:10.14#ibcon#read 4, iclass 16, count 0 2006.260.07:40:10.14#ibcon#about to read 5, iclass 16, count 0 2006.260.07:40:10.14#ibcon#read 5, iclass 16, count 0 2006.260.07:40:10.14#ibcon#about to read 6, iclass 16, count 0 2006.260.07:40:10.14#ibcon#read 6, iclass 16, count 0 2006.260.07:40:10.14#ibcon#end of sib2, iclass 16, count 0 2006.260.07:40:10.14#ibcon#*after write, iclass 16, count 0 2006.260.07:40:10.14#ibcon#*before return 0, iclass 16, count 0 2006.260.07:40:10.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:10.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:10.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:40:10.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:40:10.14$vc4f8/valo=4,832.99 2006.260.07:40:10.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:40:10.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:40:10.14#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:10.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:10.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:10.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:10.14#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:40:10.14#ibcon#first serial, iclass 18, count 0 2006.260.07:40:10.14#ibcon#enter sib2, iclass 18, count 0 2006.260.07:40:10.14#ibcon#flushed, iclass 18, count 0 2006.260.07:40:10.14#ibcon#about to write, iclass 18, count 0 2006.260.07:40:10.14#ibcon#wrote, iclass 18, count 0 2006.260.07:40:10.14#ibcon#about to read 3, iclass 18, count 0 2006.260.07:40:10.16#ibcon#read 3, iclass 18, count 0 2006.260.07:40:10.16#ibcon#about to read 4, iclass 18, count 0 2006.260.07:40:10.16#ibcon#read 4, iclass 18, count 0 2006.260.07:40:10.16#ibcon#about to read 5, iclass 18, count 0 2006.260.07:40:10.16#ibcon#read 5, iclass 18, count 0 2006.260.07:40:10.16#ibcon#about to read 6, iclass 18, count 0 2006.260.07:40:10.16#ibcon#read 6, iclass 18, count 0 2006.260.07:40:10.16#ibcon#end of sib2, iclass 18, count 0 2006.260.07:40:10.16#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:40:10.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:40:10.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:40:10.16#ibcon#*before write, iclass 18, count 0 2006.260.07:40:10.16#ibcon#enter sib2, iclass 18, count 0 2006.260.07:40:10.16#ibcon#flushed, iclass 18, count 0 2006.260.07:40:10.16#ibcon#about to write, iclass 18, count 0 2006.260.07:40:10.16#ibcon#wrote, iclass 18, count 0 2006.260.07:40:10.16#ibcon#about to read 3, iclass 18, count 0 2006.260.07:40:10.20#ibcon#read 3, iclass 18, count 0 2006.260.07:40:10.20#ibcon#about to read 4, iclass 18, count 0 2006.260.07:40:10.20#ibcon#read 4, iclass 18, count 0 2006.260.07:40:10.20#ibcon#about to read 5, iclass 18, count 0 2006.260.07:40:10.20#ibcon#read 5, iclass 18, count 0 2006.260.07:40:10.20#ibcon#about to read 6, iclass 18, count 0 2006.260.07:40:10.20#ibcon#read 6, iclass 18, count 0 2006.260.07:40:10.20#ibcon#end of sib2, iclass 18, count 0 2006.260.07:40:10.20#ibcon#*after write, iclass 18, count 0 2006.260.07:40:10.20#ibcon#*before return 0, iclass 18, count 0 2006.260.07:40:10.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:10.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:10.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:40:10.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:40:10.20$vc4f8/va=4,7 2006.260.07:40:10.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:40:10.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:40:10.20#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:10.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:10.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:10.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:10.26#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:40:10.26#ibcon#first serial, iclass 20, count 2 2006.260.07:40:10.26#ibcon#enter sib2, iclass 20, count 2 2006.260.07:40:10.26#ibcon#flushed, iclass 20, count 2 2006.260.07:40:10.26#ibcon#about to write, iclass 20, count 2 2006.260.07:40:10.26#ibcon#wrote, iclass 20, count 2 2006.260.07:40:10.26#ibcon#about to read 3, iclass 20, count 2 2006.260.07:40:10.28#ibcon#read 3, iclass 20, count 2 2006.260.07:40:10.28#ibcon#about to read 4, iclass 20, count 2 2006.260.07:40:10.28#ibcon#read 4, iclass 20, count 2 2006.260.07:40:10.28#ibcon#about to read 5, iclass 20, count 2 2006.260.07:40:10.28#ibcon#read 5, iclass 20, count 2 2006.260.07:40:10.28#ibcon#about to read 6, iclass 20, count 2 2006.260.07:40:10.28#ibcon#read 6, iclass 20, count 2 2006.260.07:40:10.28#ibcon#end of sib2, iclass 20, count 2 2006.260.07:40:10.28#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:40:10.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:40:10.28#ibcon#[25=AT04-07\r\n] 2006.260.07:40:10.28#ibcon#*before write, iclass 20, count 2 2006.260.07:40:10.28#ibcon#enter sib2, iclass 20, count 2 2006.260.07:40:10.28#ibcon#flushed, iclass 20, count 2 2006.260.07:40:10.28#ibcon#about to write, iclass 20, count 2 2006.260.07:40:10.28#ibcon#wrote, iclass 20, count 2 2006.260.07:40:10.28#ibcon#about to read 3, iclass 20, count 2 2006.260.07:40:10.31#ibcon#read 3, iclass 20, count 2 2006.260.07:40:10.31#ibcon#about to read 4, iclass 20, count 2 2006.260.07:40:10.31#ibcon#read 4, iclass 20, count 2 2006.260.07:40:10.31#ibcon#about to read 5, iclass 20, count 2 2006.260.07:40:10.31#ibcon#read 5, iclass 20, count 2 2006.260.07:40:10.31#ibcon#about to read 6, iclass 20, count 2 2006.260.07:40:10.31#ibcon#read 6, iclass 20, count 2 2006.260.07:40:10.31#ibcon#end of sib2, iclass 20, count 2 2006.260.07:40:10.31#ibcon#*after write, iclass 20, count 2 2006.260.07:40:10.31#ibcon#*before return 0, iclass 20, count 2 2006.260.07:40:10.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:10.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:10.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:40:10.31#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:10.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:10.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:10.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:10.43#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:40:10.43#ibcon#first serial, iclass 20, count 0 2006.260.07:40:10.43#ibcon#enter sib2, iclass 20, count 0 2006.260.07:40:10.43#ibcon#flushed, iclass 20, count 0 2006.260.07:40:10.43#ibcon#about to write, iclass 20, count 0 2006.260.07:40:10.43#ibcon#wrote, iclass 20, count 0 2006.260.07:40:10.43#ibcon#about to read 3, iclass 20, count 0 2006.260.07:40:10.45#ibcon#read 3, iclass 20, count 0 2006.260.07:40:10.45#ibcon#about to read 4, iclass 20, count 0 2006.260.07:40:10.45#ibcon#read 4, iclass 20, count 0 2006.260.07:40:10.45#ibcon#about to read 5, iclass 20, count 0 2006.260.07:40:10.45#ibcon#read 5, iclass 20, count 0 2006.260.07:40:10.45#ibcon#about to read 6, iclass 20, count 0 2006.260.07:40:10.45#ibcon#read 6, iclass 20, count 0 2006.260.07:40:10.45#ibcon#end of sib2, iclass 20, count 0 2006.260.07:40:10.45#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:40:10.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:40:10.45#ibcon#[25=USB\r\n] 2006.260.07:40:10.45#ibcon#*before write, iclass 20, count 0 2006.260.07:40:10.45#ibcon#enter sib2, iclass 20, count 0 2006.260.07:40:10.45#ibcon#flushed, iclass 20, count 0 2006.260.07:40:10.45#ibcon#about to write, iclass 20, count 0 2006.260.07:40:10.45#ibcon#wrote, iclass 20, count 0 2006.260.07:40:10.45#ibcon#about to read 3, iclass 20, count 0 2006.260.07:40:10.48#ibcon#read 3, iclass 20, count 0 2006.260.07:40:10.48#ibcon#about to read 4, iclass 20, count 0 2006.260.07:40:10.48#ibcon#read 4, iclass 20, count 0 2006.260.07:40:10.48#ibcon#about to read 5, iclass 20, count 0 2006.260.07:40:10.48#ibcon#read 5, iclass 20, count 0 2006.260.07:40:10.48#ibcon#about to read 6, iclass 20, count 0 2006.260.07:40:10.48#ibcon#read 6, iclass 20, count 0 2006.260.07:40:10.48#ibcon#end of sib2, iclass 20, count 0 2006.260.07:40:10.48#ibcon#*after write, iclass 20, count 0 2006.260.07:40:10.48#ibcon#*before return 0, iclass 20, count 0 2006.260.07:40:10.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:10.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:10.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:40:10.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:40:10.48$vc4f8/valo=5,652.99 2006.260.07:40:10.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:40:10.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:40:10.48#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:10.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:10.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:10.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:10.48#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:40:10.48#ibcon#first serial, iclass 22, count 0 2006.260.07:40:10.48#ibcon#enter sib2, iclass 22, count 0 2006.260.07:40:10.48#ibcon#flushed, iclass 22, count 0 2006.260.07:40:10.48#ibcon#about to write, iclass 22, count 0 2006.260.07:40:10.48#ibcon#wrote, iclass 22, count 0 2006.260.07:40:10.48#ibcon#about to read 3, iclass 22, count 0 2006.260.07:40:10.50#ibcon#read 3, iclass 22, count 0 2006.260.07:40:10.50#ibcon#about to read 4, iclass 22, count 0 2006.260.07:40:10.50#ibcon#read 4, iclass 22, count 0 2006.260.07:40:10.50#ibcon#about to read 5, iclass 22, count 0 2006.260.07:40:10.50#ibcon#read 5, iclass 22, count 0 2006.260.07:40:10.50#ibcon#about to read 6, iclass 22, count 0 2006.260.07:40:10.50#ibcon#read 6, iclass 22, count 0 2006.260.07:40:10.50#ibcon#end of sib2, iclass 22, count 0 2006.260.07:40:10.50#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:40:10.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:40:10.50#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:40:10.50#ibcon#*before write, iclass 22, count 0 2006.260.07:40:10.50#ibcon#enter sib2, iclass 22, count 0 2006.260.07:40:10.50#ibcon#flushed, iclass 22, count 0 2006.260.07:40:10.50#ibcon#about to write, iclass 22, count 0 2006.260.07:40:10.50#ibcon#wrote, iclass 22, count 0 2006.260.07:40:10.50#ibcon#about to read 3, iclass 22, count 0 2006.260.07:40:10.54#ibcon#read 3, iclass 22, count 0 2006.260.07:40:10.54#ibcon#about to read 4, iclass 22, count 0 2006.260.07:40:10.54#ibcon#read 4, iclass 22, count 0 2006.260.07:40:10.54#ibcon#about to read 5, iclass 22, count 0 2006.260.07:40:10.54#ibcon#read 5, iclass 22, count 0 2006.260.07:40:10.54#ibcon#about to read 6, iclass 22, count 0 2006.260.07:40:10.54#ibcon#read 6, iclass 22, count 0 2006.260.07:40:10.54#ibcon#end of sib2, iclass 22, count 0 2006.260.07:40:10.54#ibcon#*after write, iclass 22, count 0 2006.260.07:40:10.54#ibcon#*before return 0, iclass 22, count 0 2006.260.07:40:10.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:10.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:10.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:40:10.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:40:10.54$vc4f8/va=5,7 2006.260.07:40:10.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:40:10.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:40:10.54#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:10.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:10.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:10.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:10.60#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:40:10.60#ibcon#first serial, iclass 24, count 2 2006.260.07:40:10.60#ibcon#enter sib2, iclass 24, count 2 2006.260.07:40:10.60#ibcon#flushed, iclass 24, count 2 2006.260.07:40:10.60#ibcon#about to write, iclass 24, count 2 2006.260.07:40:10.60#ibcon#wrote, iclass 24, count 2 2006.260.07:40:10.60#ibcon#about to read 3, iclass 24, count 2 2006.260.07:40:10.63#ibcon#read 3, iclass 24, count 2 2006.260.07:40:10.63#ibcon#about to read 4, iclass 24, count 2 2006.260.07:40:10.63#ibcon#read 4, iclass 24, count 2 2006.260.07:40:10.63#ibcon#about to read 5, iclass 24, count 2 2006.260.07:40:10.63#ibcon#read 5, iclass 24, count 2 2006.260.07:40:10.63#ibcon#about to read 6, iclass 24, count 2 2006.260.07:40:10.63#ibcon#read 6, iclass 24, count 2 2006.260.07:40:10.63#ibcon#end of sib2, iclass 24, count 2 2006.260.07:40:10.63#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:40:10.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:40:10.63#ibcon#[25=AT05-07\r\n] 2006.260.07:40:10.63#ibcon#*before write, iclass 24, count 2 2006.260.07:40:10.63#ibcon#enter sib2, iclass 24, count 2 2006.260.07:40:10.63#ibcon#flushed, iclass 24, count 2 2006.260.07:40:10.63#ibcon#about to write, iclass 24, count 2 2006.260.07:40:10.63#ibcon#wrote, iclass 24, count 2 2006.260.07:40:10.63#ibcon#about to read 3, iclass 24, count 2 2006.260.07:40:10.66#ibcon#read 3, iclass 24, count 2 2006.260.07:40:10.66#ibcon#about to read 4, iclass 24, count 2 2006.260.07:40:10.66#ibcon#read 4, iclass 24, count 2 2006.260.07:40:10.66#ibcon#about to read 5, iclass 24, count 2 2006.260.07:40:10.66#ibcon#read 5, iclass 24, count 2 2006.260.07:40:10.66#ibcon#about to read 6, iclass 24, count 2 2006.260.07:40:10.66#ibcon#read 6, iclass 24, count 2 2006.260.07:40:10.66#ibcon#end of sib2, iclass 24, count 2 2006.260.07:40:10.66#ibcon#*after write, iclass 24, count 2 2006.260.07:40:10.66#ibcon#*before return 0, iclass 24, count 2 2006.260.07:40:10.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:10.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:10.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:40:10.66#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:10.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:10.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:10.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:10.78#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:40:10.78#ibcon#first serial, iclass 24, count 0 2006.260.07:40:10.78#ibcon#enter sib2, iclass 24, count 0 2006.260.07:40:10.78#ibcon#flushed, iclass 24, count 0 2006.260.07:40:10.78#ibcon#about to write, iclass 24, count 0 2006.260.07:40:10.78#ibcon#wrote, iclass 24, count 0 2006.260.07:40:10.78#ibcon#about to read 3, iclass 24, count 0 2006.260.07:40:10.80#ibcon#read 3, iclass 24, count 0 2006.260.07:40:10.80#ibcon#about to read 4, iclass 24, count 0 2006.260.07:40:10.80#ibcon#read 4, iclass 24, count 0 2006.260.07:40:10.80#ibcon#about to read 5, iclass 24, count 0 2006.260.07:40:10.80#ibcon#read 5, iclass 24, count 0 2006.260.07:40:10.80#ibcon#about to read 6, iclass 24, count 0 2006.260.07:40:10.80#ibcon#read 6, iclass 24, count 0 2006.260.07:40:10.80#ibcon#end of sib2, iclass 24, count 0 2006.260.07:40:10.80#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:40:10.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:40:10.80#ibcon#[25=USB\r\n] 2006.260.07:40:10.80#ibcon#*before write, iclass 24, count 0 2006.260.07:40:10.80#ibcon#enter sib2, iclass 24, count 0 2006.260.07:40:10.80#ibcon#flushed, iclass 24, count 0 2006.260.07:40:10.80#ibcon#about to write, iclass 24, count 0 2006.260.07:40:10.80#ibcon#wrote, iclass 24, count 0 2006.260.07:40:10.80#ibcon#about to read 3, iclass 24, count 0 2006.260.07:40:10.83#ibcon#read 3, iclass 24, count 0 2006.260.07:40:10.83#ibcon#about to read 4, iclass 24, count 0 2006.260.07:40:10.83#ibcon#read 4, iclass 24, count 0 2006.260.07:40:10.83#ibcon#about to read 5, iclass 24, count 0 2006.260.07:40:10.83#ibcon#read 5, iclass 24, count 0 2006.260.07:40:10.83#ibcon#about to read 6, iclass 24, count 0 2006.260.07:40:10.83#ibcon#read 6, iclass 24, count 0 2006.260.07:40:10.83#ibcon#end of sib2, iclass 24, count 0 2006.260.07:40:10.83#ibcon#*after write, iclass 24, count 0 2006.260.07:40:10.83#ibcon#*before return 0, iclass 24, count 0 2006.260.07:40:10.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:10.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:10.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:40:10.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:40:10.83$vc4f8/valo=6,772.99 2006.260.07:40:10.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:40:10.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:40:10.83#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:10.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:10.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:10.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:10.83#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:40:10.83#ibcon#first serial, iclass 26, count 0 2006.260.07:40:10.83#ibcon#enter sib2, iclass 26, count 0 2006.260.07:40:10.83#ibcon#flushed, iclass 26, count 0 2006.260.07:40:10.83#ibcon#about to write, iclass 26, count 0 2006.260.07:40:10.83#ibcon#wrote, iclass 26, count 0 2006.260.07:40:10.83#ibcon#about to read 3, iclass 26, count 0 2006.260.07:40:10.85#ibcon#read 3, iclass 26, count 0 2006.260.07:40:10.85#ibcon#about to read 4, iclass 26, count 0 2006.260.07:40:10.85#ibcon#read 4, iclass 26, count 0 2006.260.07:40:10.85#ibcon#about to read 5, iclass 26, count 0 2006.260.07:40:10.85#ibcon#read 5, iclass 26, count 0 2006.260.07:40:10.85#ibcon#about to read 6, iclass 26, count 0 2006.260.07:40:10.85#ibcon#read 6, iclass 26, count 0 2006.260.07:40:10.85#ibcon#end of sib2, iclass 26, count 0 2006.260.07:40:10.85#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:40:10.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:40:10.85#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:40:10.85#ibcon#*before write, iclass 26, count 0 2006.260.07:40:10.85#ibcon#enter sib2, iclass 26, count 0 2006.260.07:40:10.85#ibcon#flushed, iclass 26, count 0 2006.260.07:40:10.85#ibcon#about to write, iclass 26, count 0 2006.260.07:40:10.85#ibcon#wrote, iclass 26, count 0 2006.260.07:40:10.85#ibcon#about to read 3, iclass 26, count 0 2006.260.07:40:10.89#ibcon#read 3, iclass 26, count 0 2006.260.07:40:10.89#ibcon#about to read 4, iclass 26, count 0 2006.260.07:40:10.89#ibcon#read 4, iclass 26, count 0 2006.260.07:40:10.89#ibcon#about to read 5, iclass 26, count 0 2006.260.07:40:10.89#ibcon#read 5, iclass 26, count 0 2006.260.07:40:10.89#ibcon#about to read 6, iclass 26, count 0 2006.260.07:40:10.89#ibcon#read 6, iclass 26, count 0 2006.260.07:40:10.89#ibcon#end of sib2, iclass 26, count 0 2006.260.07:40:10.89#ibcon#*after write, iclass 26, count 0 2006.260.07:40:10.89#ibcon#*before return 0, iclass 26, count 0 2006.260.07:40:10.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:10.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:10.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:40:10.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:40:10.89$vc4f8/va=6,6 2006.260.07:40:10.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:40:10.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:40:10.89#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:10.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:10.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:10.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:10.95#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:40:10.95#ibcon#first serial, iclass 28, count 2 2006.260.07:40:10.95#ibcon#enter sib2, iclass 28, count 2 2006.260.07:40:10.95#ibcon#flushed, iclass 28, count 2 2006.260.07:40:10.95#ibcon#about to write, iclass 28, count 2 2006.260.07:40:10.95#ibcon#wrote, iclass 28, count 2 2006.260.07:40:10.95#ibcon#about to read 3, iclass 28, count 2 2006.260.07:40:10.97#ibcon#read 3, iclass 28, count 2 2006.260.07:40:10.97#ibcon#about to read 4, iclass 28, count 2 2006.260.07:40:10.97#ibcon#read 4, iclass 28, count 2 2006.260.07:40:10.97#ibcon#about to read 5, iclass 28, count 2 2006.260.07:40:10.97#ibcon#read 5, iclass 28, count 2 2006.260.07:40:10.97#ibcon#about to read 6, iclass 28, count 2 2006.260.07:40:10.97#ibcon#read 6, iclass 28, count 2 2006.260.07:40:10.97#ibcon#end of sib2, iclass 28, count 2 2006.260.07:40:10.97#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:40:10.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:40:10.97#ibcon#[25=AT06-06\r\n] 2006.260.07:40:10.97#ibcon#*before write, iclass 28, count 2 2006.260.07:40:10.97#ibcon#enter sib2, iclass 28, count 2 2006.260.07:40:10.97#ibcon#flushed, iclass 28, count 2 2006.260.07:40:10.97#ibcon#about to write, iclass 28, count 2 2006.260.07:40:10.97#ibcon#wrote, iclass 28, count 2 2006.260.07:40:10.97#ibcon#about to read 3, iclass 28, count 2 2006.260.07:40:11.00#ibcon#read 3, iclass 28, count 2 2006.260.07:40:11.00#ibcon#about to read 4, iclass 28, count 2 2006.260.07:40:11.00#ibcon#read 4, iclass 28, count 2 2006.260.07:40:11.00#ibcon#about to read 5, iclass 28, count 2 2006.260.07:40:11.00#ibcon#read 5, iclass 28, count 2 2006.260.07:40:11.00#ibcon#about to read 6, iclass 28, count 2 2006.260.07:40:11.00#ibcon#read 6, iclass 28, count 2 2006.260.07:40:11.00#ibcon#end of sib2, iclass 28, count 2 2006.260.07:40:11.00#ibcon#*after write, iclass 28, count 2 2006.260.07:40:11.00#ibcon#*before return 0, iclass 28, count 2 2006.260.07:40:11.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:11.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:11.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:40:11.00#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:11.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:40:11.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:40:11.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:40:11.12#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:40:11.12#ibcon#first serial, iclass 28, count 0 2006.260.07:40:11.12#ibcon#enter sib2, iclass 28, count 0 2006.260.07:40:11.12#ibcon#flushed, iclass 28, count 0 2006.260.07:40:11.12#ibcon#about to write, iclass 28, count 0 2006.260.07:40:11.12#ibcon#wrote, iclass 28, count 0 2006.260.07:40:11.12#ibcon#about to read 3, iclass 28, count 0 2006.260.07:40:11.14#ibcon#read 3, iclass 28, count 0 2006.260.07:40:11.14#ibcon#about to read 4, iclass 28, count 0 2006.260.07:40:11.14#ibcon#read 4, iclass 28, count 0 2006.260.07:40:11.14#ibcon#about to read 5, iclass 28, count 0 2006.260.07:40:11.14#ibcon#read 5, iclass 28, count 0 2006.260.07:40:11.14#ibcon#about to read 6, iclass 28, count 0 2006.260.07:40:11.14#ibcon#read 6, iclass 28, count 0 2006.260.07:40:11.14#ibcon#end of sib2, iclass 28, count 0 2006.260.07:40:11.14#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:40:11.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:40:11.14#ibcon#[25=USB\r\n] 2006.260.07:40:11.14#ibcon#*before write, iclass 28, count 0 2006.260.07:40:11.14#ibcon#enter sib2, iclass 28, count 0 2006.260.07:40:11.14#ibcon#flushed, iclass 28, count 0 2006.260.07:40:11.14#ibcon#about to write, iclass 28, count 0 2006.260.07:40:11.14#ibcon#wrote, iclass 28, count 0 2006.260.07:40:11.14#ibcon#about to read 3, iclass 28, count 0 2006.260.07:40:11.17#ibcon#read 3, iclass 28, count 0 2006.260.07:40:11.17#ibcon#about to read 4, iclass 28, count 0 2006.260.07:40:11.17#ibcon#read 4, iclass 28, count 0 2006.260.07:40:11.17#ibcon#about to read 5, iclass 28, count 0 2006.260.07:40:11.17#ibcon#read 5, iclass 28, count 0 2006.260.07:40:11.17#ibcon#about to read 6, iclass 28, count 0 2006.260.07:40:11.17#ibcon#read 6, iclass 28, count 0 2006.260.07:40:11.17#ibcon#end of sib2, iclass 28, count 0 2006.260.07:40:11.17#ibcon#*after write, iclass 28, count 0 2006.260.07:40:11.17#ibcon#*before return 0, iclass 28, count 0 2006.260.07:40:11.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:40:11.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:40:11.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:40:11.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:40:11.17$vc4f8/valo=7,832.99 2006.260.07:40:11.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:40:11.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:40:11.17#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:11.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:40:11.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:40:11.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:40:11.17#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:40:11.17#ibcon#first serial, iclass 30, count 0 2006.260.07:40:11.17#ibcon#enter sib2, iclass 30, count 0 2006.260.07:40:11.17#ibcon#flushed, iclass 30, count 0 2006.260.07:40:11.17#ibcon#about to write, iclass 30, count 0 2006.260.07:40:11.17#ibcon#wrote, iclass 30, count 0 2006.260.07:40:11.17#ibcon#about to read 3, iclass 30, count 0 2006.260.07:40:11.19#ibcon#read 3, iclass 30, count 0 2006.260.07:40:11.19#ibcon#about to read 4, iclass 30, count 0 2006.260.07:40:11.19#ibcon#read 4, iclass 30, count 0 2006.260.07:40:11.19#ibcon#about to read 5, iclass 30, count 0 2006.260.07:40:11.19#ibcon#read 5, iclass 30, count 0 2006.260.07:40:11.19#ibcon#about to read 6, iclass 30, count 0 2006.260.07:40:11.19#ibcon#read 6, iclass 30, count 0 2006.260.07:40:11.19#ibcon#end of sib2, iclass 30, count 0 2006.260.07:40:11.19#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:40:11.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:40:11.19#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:40:11.19#ibcon#*before write, iclass 30, count 0 2006.260.07:40:11.19#ibcon#enter sib2, iclass 30, count 0 2006.260.07:40:11.19#ibcon#flushed, iclass 30, count 0 2006.260.07:40:11.19#ibcon#about to write, iclass 30, count 0 2006.260.07:40:11.19#ibcon#wrote, iclass 30, count 0 2006.260.07:40:11.19#ibcon#about to read 3, iclass 30, count 0 2006.260.07:40:11.23#ibcon#read 3, iclass 30, count 0 2006.260.07:40:11.23#ibcon#about to read 4, iclass 30, count 0 2006.260.07:40:11.23#ibcon#read 4, iclass 30, count 0 2006.260.07:40:11.23#ibcon#about to read 5, iclass 30, count 0 2006.260.07:40:11.23#ibcon#read 5, iclass 30, count 0 2006.260.07:40:11.23#ibcon#about to read 6, iclass 30, count 0 2006.260.07:40:11.23#ibcon#read 6, iclass 30, count 0 2006.260.07:40:11.23#ibcon#end of sib2, iclass 30, count 0 2006.260.07:40:11.23#ibcon#*after write, iclass 30, count 0 2006.260.07:40:11.23#ibcon#*before return 0, iclass 30, count 0 2006.260.07:40:11.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:40:11.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:40:11.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:40:11.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:40:11.23$vc4f8/va=7,6 2006.260.07:40:11.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:40:11.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:40:11.23#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:11.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:40:11.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:40:11.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:40:11.29#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:40:11.29#ibcon#first serial, iclass 32, count 2 2006.260.07:40:11.29#ibcon#enter sib2, iclass 32, count 2 2006.260.07:40:11.29#ibcon#flushed, iclass 32, count 2 2006.260.07:40:11.29#ibcon#about to write, iclass 32, count 2 2006.260.07:40:11.29#ibcon#wrote, iclass 32, count 2 2006.260.07:40:11.29#ibcon#about to read 3, iclass 32, count 2 2006.260.07:40:11.31#ibcon#read 3, iclass 32, count 2 2006.260.07:40:11.31#ibcon#about to read 4, iclass 32, count 2 2006.260.07:40:11.31#ibcon#read 4, iclass 32, count 2 2006.260.07:40:11.31#ibcon#about to read 5, iclass 32, count 2 2006.260.07:40:11.31#ibcon#read 5, iclass 32, count 2 2006.260.07:40:11.31#ibcon#about to read 6, iclass 32, count 2 2006.260.07:40:11.31#ibcon#read 6, iclass 32, count 2 2006.260.07:40:11.31#ibcon#end of sib2, iclass 32, count 2 2006.260.07:40:11.31#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:40:11.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:40:11.31#ibcon#[25=AT07-06\r\n] 2006.260.07:40:11.31#ibcon#*before write, iclass 32, count 2 2006.260.07:40:11.31#ibcon#enter sib2, iclass 32, count 2 2006.260.07:40:11.31#ibcon#flushed, iclass 32, count 2 2006.260.07:40:11.31#ibcon#about to write, iclass 32, count 2 2006.260.07:40:11.31#ibcon#wrote, iclass 32, count 2 2006.260.07:40:11.31#ibcon#about to read 3, iclass 32, count 2 2006.260.07:40:11.34#ibcon#read 3, iclass 32, count 2 2006.260.07:40:11.34#ibcon#about to read 4, iclass 32, count 2 2006.260.07:40:11.34#ibcon#read 4, iclass 32, count 2 2006.260.07:40:11.34#ibcon#about to read 5, iclass 32, count 2 2006.260.07:40:11.34#ibcon#read 5, iclass 32, count 2 2006.260.07:40:11.34#ibcon#about to read 6, iclass 32, count 2 2006.260.07:40:11.34#ibcon#read 6, iclass 32, count 2 2006.260.07:40:11.34#ibcon#end of sib2, iclass 32, count 2 2006.260.07:40:11.34#ibcon#*after write, iclass 32, count 2 2006.260.07:40:11.34#ibcon#*before return 0, iclass 32, count 2 2006.260.07:40:11.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:40:11.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:40:11.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:40:11.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:11.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:40:11.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:40:11.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:40:11.46#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:40:11.46#ibcon#first serial, iclass 32, count 0 2006.260.07:40:11.46#ibcon#enter sib2, iclass 32, count 0 2006.260.07:40:11.46#ibcon#flushed, iclass 32, count 0 2006.260.07:40:11.46#ibcon#about to write, iclass 32, count 0 2006.260.07:40:11.46#ibcon#wrote, iclass 32, count 0 2006.260.07:40:11.46#ibcon#about to read 3, iclass 32, count 0 2006.260.07:40:11.48#ibcon#read 3, iclass 32, count 0 2006.260.07:40:11.48#ibcon#about to read 4, iclass 32, count 0 2006.260.07:40:11.48#ibcon#read 4, iclass 32, count 0 2006.260.07:40:11.48#ibcon#about to read 5, iclass 32, count 0 2006.260.07:40:11.48#ibcon#read 5, iclass 32, count 0 2006.260.07:40:11.48#ibcon#about to read 6, iclass 32, count 0 2006.260.07:40:11.48#ibcon#read 6, iclass 32, count 0 2006.260.07:40:11.48#ibcon#end of sib2, iclass 32, count 0 2006.260.07:40:11.48#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:40:11.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:40:11.48#ibcon#[25=USB\r\n] 2006.260.07:40:11.48#ibcon#*before write, iclass 32, count 0 2006.260.07:40:11.48#ibcon#enter sib2, iclass 32, count 0 2006.260.07:40:11.48#ibcon#flushed, iclass 32, count 0 2006.260.07:40:11.48#ibcon#about to write, iclass 32, count 0 2006.260.07:40:11.48#ibcon#wrote, iclass 32, count 0 2006.260.07:40:11.48#ibcon#about to read 3, iclass 32, count 0 2006.260.07:40:11.51#ibcon#read 3, iclass 32, count 0 2006.260.07:40:11.51#ibcon#about to read 4, iclass 32, count 0 2006.260.07:40:11.51#ibcon#read 4, iclass 32, count 0 2006.260.07:40:11.51#ibcon#about to read 5, iclass 32, count 0 2006.260.07:40:11.51#ibcon#read 5, iclass 32, count 0 2006.260.07:40:11.51#ibcon#about to read 6, iclass 32, count 0 2006.260.07:40:11.51#ibcon#read 6, iclass 32, count 0 2006.260.07:40:11.51#ibcon#end of sib2, iclass 32, count 0 2006.260.07:40:11.51#ibcon#*after write, iclass 32, count 0 2006.260.07:40:11.51#ibcon#*before return 0, iclass 32, count 0 2006.260.07:40:11.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:40:11.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:40:11.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:40:11.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:40:11.51$vc4f8/valo=8,852.99 2006.260.07:40:11.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:40:11.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:40:11.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:11.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:40:11.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:40:11.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:40:11.51#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:40:11.51#ibcon#first serial, iclass 34, count 0 2006.260.07:40:11.51#ibcon#enter sib2, iclass 34, count 0 2006.260.07:40:11.51#ibcon#flushed, iclass 34, count 0 2006.260.07:40:11.51#ibcon#about to write, iclass 34, count 0 2006.260.07:40:11.51#ibcon#wrote, iclass 34, count 0 2006.260.07:40:11.51#ibcon#about to read 3, iclass 34, count 0 2006.260.07:40:11.53#ibcon#read 3, iclass 34, count 0 2006.260.07:40:11.53#ibcon#about to read 4, iclass 34, count 0 2006.260.07:40:11.53#ibcon#read 4, iclass 34, count 0 2006.260.07:40:11.53#ibcon#about to read 5, iclass 34, count 0 2006.260.07:40:11.53#ibcon#read 5, iclass 34, count 0 2006.260.07:40:11.53#ibcon#about to read 6, iclass 34, count 0 2006.260.07:40:11.53#ibcon#read 6, iclass 34, count 0 2006.260.07:40:11.53#ibcon#end of sib2, iclass 34, count 0 2006.260.07:40:11.53#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:40:11.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:40:11.53#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:40:11.53#ibcon#*before write, iclass 34, count 0 2006.260.07:40:11.53#ibcon#enter sib2, iclass 34, count 0 2006.260.07:40:11.53#ibcon#flushed, iclass 34, count 0 2006.260.07:40:11.53#ibcon#about to write, iclass 34, count 0 2006.260.07:40:11.53#ibcon#wrote, iclass 34, count 0 2006.260.07:40:11.53#ibcon#about to read 3, iclass 34, count 0 2006.260.07:40:11.57#ibcon#read 3, iclass 34, count 0 2006.260.07:40:11.57#ibcon#about to read 4, iclass 34, count 0 2006.260.07:40:11.57#ibcon#read 4, iclass 34, count 0 2006.260.07:40:11.57#ibcon#about to read 5, iclass 34, count 0 2006.260.07:40:11.57#ibcon#read 5, iclass 34, count 0 2006.260.07:40:11.57#ibcon#about to read 6, iclass 34, count 0 2006.260.07:40:11.57#ibcon#read 6, iclass 34, count 0 2006.260.07:40:11.57#ibcon#end of sib2, iclass 34, count 0 2006.260.07:40:11.57#ibcon#*after write, iclass 34, count 0 2006.260.07:40:11.57#ibcon#*before return 0, iclass 34, count 0 2006.260.07:40:11.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:40:11.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:40:11.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:40:11.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:40:11.57$vc4f8/va=8,6 2006.260.07:40:11.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:40:11.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:40:11.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:11.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:40:11.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:40:11.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:40:11.63#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:40:11.63#ibcon#first serial, iclass 36, count 2 2006.260.07:40:11.63#ibcon#enter sib2, iclass 36, count 2 2006.260.07:40:11.63#ibcon#flushed, iclass 36, count 2 2006.260.07:40:11.63#ibcon#about to write, iclass 36, count 2 2006.260.07:40:11.63#ibcon#wrote, iclass 36, count 2 2006.260.07:40:11.63#ibcon#about to read 3, iclass 36, count 2 2006.260.07:40:11.65#ibcon#read 3, iclass 36, count 2 2006.260.07:40:11.65#ibcon#about to read 4, iclass 36, count 2 2006.260.07:40:11.65#ibcon#read 4, iclass 36, count 2 2006.260.07:40:11.65#ibcon#about to read 5, iclass 36, count 2 2006.260.07:40:11.65#ibcon#read 5, iclass 36, count 2 2006.260.07:40:11.65#ibcon#about to read 6, iclass 36, count 2 2006.260.07:40:11.65#ibcon#read 6, iclass 36, count 2 2006.260.07:40:11.65#ibcon#end of sib2, iclass 36, count 2 2006.260.07:40:11.65#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:40:11.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:40:11.65#ibcon#[25=AT08-06\r\n] 2006.260.07:40:11.65#ibcon#*before write, iclass 36, count 2 2006.260.07:40:11.65#ibcon#enter sib2, iclass 36, count 2 2006.260.07:40:11.65#ibcon#flushed, iclass 36, count 2 2006.260.07:40:11.65#ibcon#about to write, iclass 36, count 2 2006.260.07:40:11.65#ibcon#wrote, iclass 36, count 2 2006.260.07:40:11.65#ibcon#about to read 3, iclass 36, count 2 2006.260.07:40:11.68#ibcon#read 3, iclass 36, count 2 2006.260.07:40:11.68#ibcon#about to read 4, iclass 36, count 2 2006.260.07:40:11.68#ibcon#read 4, iclass 36, count 2 2006.260.07:40:11.68#ibcon#about to read 5, iclass 36, count 2 2006.260.07:40:11.68#ibcon#read 5, iclass 36, count 2 2006.260.07:40:11.68#ibcon#about to read 6, iclass 36, count 2 2006.260.07:40:11.68#ibcon#read 6, iclass 36, count 2 2006.260.07:40:11.68#ibcon#end of sib2, iclass 36, count 2 2006.260.07:40:11.68#ibcon#*after write, iclass 36, count 2 2006.260.07:40:11.68#ibcon#*before return 0, iclass 36, count 2 2006.260.07:40:11.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:40:11.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:40:11.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:40:11.68#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:11.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:40:11.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:40:11.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:40:11.80#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:40:11.80#ibcon#first serial, iclass 36, count 0 2006.260.07:40:11.80#ibcon#enter sib2, iclass 36, count 0 2006.260.07:40:11.80#ibcon#flushed, iclass 36, count 0 2006.260.07:40:11.80#ibcon#about to write, iclass 36, count 0 2006.260.07:40:11.80#ibcon#wrote, iclass 36, count 0 2006.260.07:40:11.80#ibcon#about to read 3, iclass 36, count 0 2006.260.07:40:11.82#ibcon#read 3, iclass 36, count 0 2006.260.07:40:11.82#ibcon#about to read 4, iclass 36, count 0 2006.260.07:40:11.82#ibcon#read 4, iclass 36, count 0 2006.260.07:40:11.82#ibcon#about to read 5, iclass 36, count 0 2006.260.07:40:11.82#ibcon#read 5, iclass 36, count 0 2006.260.07:40:11.82#ibcon#about to read 6, iclass 36, count 0 2006.260.07:40:11.82#ibcon#read 6, iclass 36, count 0 2006.260.07:40:11.82#ibcon#end of sib2, iclass 36, count 0 2006.260.07:40:11.82#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:40:11.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:40:11.82#ibcon#[25=USB\r\n] 2006.260.07:40:11.82#ibcon#*before write, iclass 36, count 0 2006.260.07:40:11.82#ibcon#enter sib2, iclass 36, count 0 2006.260.07:40:11.82#ibcon#flushed, iclass 36, count 0 2006.260.07:40:11.82#ibcon#about to write, iclass 36, count 0 2006.260.07:40:11.82#ibcon#wrote, iclass 36, count 0 2006.260.07:40:11.82#ibcon#about to read 3, iclass 36, count 0 2006.260.07:40:11.85#ibcon#read 3, iclass 36, count 0 2006.260.07:40:11.85#ibcon#about to read 4, iclass 36, count 0 2006.260.07:40:11.85#ibcon#read 4, iclass 36, count 0 2006.260.07:40:11.85#ibcon#about to read 5, iclass 36, count 0 2006.260.07:40:11.85#ibcon#read 5, iclass 36, count 0 2006.260.07:40:11.85#ibcon#about to read 6, iclass 36, count 0 2006.260.07:40:11.85#ibcon#read 6, iclass 36, count 0 2006.260.07:40:11.85#ibcon#end of sib2, iclass 36, count 0 2006.260.07:40:11.85#ibcon#*after write, iclass 36, count 0 2006.260.07:40:11.85#ibcon#*before return 0, iclass 36, count 0 2006.260.07:40:11.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:40:11.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:40:11.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:40:11.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:40:11.85$vc4f8/vblo=1,632.99 2006.260.07:40:11.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:40:11.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:40:11.85#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:11.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:40:11.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:40:11.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:40:11.85#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:40:11.85#ibcon#first serial, iclass 38, count 0 2006.260.07:40:11.85#ibcon#enter sib2, iclass 38, count 0 2006.260.07:40:11.85#ibcon#flushed, iclass 38, count 0 2006.260.07:40:11.85#ibcon#about to write, iclass 38, count 0 2006.260.07:40:11.85#ibcon#wrote, iclass 38, count 0 2006.260.07:40:11.85#ibcon#about to read 3, iclass 38, count 0 2006.260.07:40:11.87#ibcon#read 3, iclass 38, count 0 2006.260.07:40:11.87#ibcon#about to read 4, iclass 38, count 0 2006.260.07:40:11.87#ibcon#read 4, iclass 38, count 0 2006.260.07:40:11.87#ibcon#about to read 5, iclass 38, count 0 2006.260.07:40:11.87#ibcon#read 5, iclass 38, count 0 2006.260.07:40:11.87#ibcon#about to read 6, iclass 38, count 0 2006.260.07:40:11.87#ibcon#read 6, iclass 38, count 0 2006.260.07:40:11.87#ibcon#end of sib2, iclass 38, count 0 2006.260.07:40:11.87#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:40:11.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:40:11.87#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:40:11.87#ibcon#*before write, iclass 38, count 0 2006.260.07:40:11.87#ibcon#enter sib2, iclass 38, count 0 2006.260.07:40:11.87#ibcon#flushed, iclass 38, count 0 2006.260.07:40:11.87#ibcon#about to write, iclass 38, count 0 2006.260.07:40:11.87#ibcon#wrote, iclass 38, count 0 2006.260.07:40:11.87#ibcon#about to read 3, iclass 38, count 0 2006.260.07:40:11.91#ibcon#read 3, iclass 38, count 0 2006.260.07:40:11.91#ibcon#about to read 4, iclass 38, count 0 2006.260.07:40:11.91#ibcon#read 4, iclass 38, count 0 2006.260.07:40:11.91#ibcon#about to read 5, iclass 38, count 0 2006.260.07:40:11.91#ibcon#read 5, iclass 38, count 0 2006.260.07:40:11.91#ibcon#about to read 6, iclass 38, count 0 2006.260.07:40:11.91#ibcon#read 6, iclass 38, count 0 2006.260.07:40:11.91#ibcon#end of sib2, iclass 38, count 0 2006.260.07:40:11.91#ibcon#*after write, iclass 38, count 0 2006.260.07:40:11.91#ibcon#*before return 0, iclass 38, count 0 2006.260.07:40:11.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:40:11.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:40:11.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:40:11.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:40:11.91$vc4f8/vb=1,4 2006.260.07:40:11.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:40:11.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:40:11.91#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:11.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:40:11.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:40:11.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:40:11.91#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:40:11.91#ibcon#first serial, iclass 40, count 2 2006.260.07:40:11.91#ibcon#enter sib2, iclass 40, count 2 2006.260.07:40:11.91#ibcon#flushed, iclass 40, count 2 2006.260.07:40:11.91#ibcon#about to write, iclass 40, count 2 2006.260.07:40:11.91#ibcon#wrote, iclass 40, count 2 2006.260.07:40:11.91#ibcon#about to read 3, iclass 40, count 2 2006.260.07:40:11.93#ibcon#read 3, iclass 40, count 2 2006.260.07:40:11.93#ibcon#about to read 4, iclass 40, count 2 2006.260.07:40:11.93#ibcon#read 4, iclass 40, count 2 2006.260.07:40:11.93#ibcon#about to read 5, iclass 40, count 2 2006.260.07:40:11.93#ibcon#read 5, iclass 40, count 2 2006.260.07:40:11.93#ibcon#about to read 6, iclass 40, count 2 2006.260.07:40:11.93#ibcon#read 6, iclass 40, count 2 2006.260.07:40:11.93#ibcon#end of sib2, iclass 40, count 2 2006.260.07:40:11.93#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:40:11.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:40:11.93#ibcon#[27=AT01-04\r\n] 2006.260.07:40:11.93#ibcon#*before write, iclass 40, count 2 2006.260.07:40:11.93#ibcon#enter sib2, iclass 40, count 2 2006.260.07:40:11.93#ibcon#flushed, iclass 40, count 2 2006.260.07:40:11.93#ibcon#about to write, iclass 40, count 2 2006.260.07:40:11.93#ibcon#wrote, iclass 40, count 2 2006.260.07:40:11.93#ibcon#about to read 3, iclass 40, count 2 2006.260.07:40:11.96#ibcon#read 3, iclass 40, count 2 2006.260.07:40:11.96#ibcon#about to read 4, iclass 40, count 2 2006.260.07:40:11.96#ibcon#read 4, iclass 40, count 2 2006.260.07:40:11.96#ibcon#about to read 5, iclass 40, count 2 2006.260.07:40:11.96#ibcon#read 5, iclass 40, count 2 2006.260.07:40:11.96#ibcon#about to read 6, iclass 40, count 2 2006.260.07:40:11.96#ibcon#read 6, iclass 40, count 2 2006.260.07:40:11.96#ibcon#end of sib2, iclass 40, count 2 2006.260.07:40:11.96#ibcon#*after write, iclass 40, count 2 2006.260.07:40:11.96#ibcon#*before return 0, iclass 40, count 2 2006.260.07:40:11.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:40:11.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:40:11.96#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:40:11.96#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:11.96#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:40:12.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:40:12.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:40:12.08#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:40:12.08#ibcon#first serial, iclass 40, count 0 2006.260.07:40:12.08#ibcon#enter sib2, iclass 40, count 0 2006.260.07:40:12.08#ibcon#flushed, iclass 40, count 0 2006.260.07:40:12.08#ibcon#about to write, iclass 40, count 0 2006.260.07:40:12.08#ibcon#wrote, iclass 40, count 0 2006.260.07:40:12.08#ibcon#about to read 3, iclass 40, count 0 2006.260.07:40:12.10#ibcon#read 3, iclass 40, count 0 2006.260.07:40:12.10#ibcon#about to read 4, iclass 40, count 0 2006.260.07:40:12.10#ibcon#read 4, iclass 40, count 0 2006.260.07:40:12.10#ibcon#about to read 5, iclass 40, count 0 2006.260.07:40:12.10#ibcon#read 5, iclass 40, count 0 2006.260.07:40:12.10#ibcon#about to read 6, iclass 40, count 0 2006.260.07:40:12.10#ibcon#read 6, iclass 40, count 0 2006.260.07:40:12.10#ibcon#end of sib2, iclass 40, count 0 2006.260.07:40:12.10#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:40:12.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:40:12.10#ibcon#[27=USB\r\n] 2006.260.07:40:12.10#ibcon#*before write, iclass 40, count 0 2006.260.07:40:12.10#ibcon#enter sib2, iclass 40, count 0 2006.260.07:40:12.10#ibcon#flushed, iclass 40, count 0 2006.260.07:40:12.10#ibcon#about to write, iclass 40, count 0 2006.260.07:40:12.10#ibcon#wrote, iclass 40, count 0 2006.260.07:40:12.10#ibcon#about to read 3, iclass 40, count 0 2006.260.07:40:12.13#ibcon#read 3, iclass 40, count 0 2006.260.07:40:12.13#ibcon#about to read 4, iclass 40, count 0 2006.260.07:40:12.13#ibcon#read 4, iclass 40, count 0 2006.260.07:40:12.13#ibcon#about to read 5, iclass 40, count 0 2006.260.07:40:12.13#ibcon#read 5, iclass 40, count 0 2006.260.07:40:12.13#ibcon#about to read 6, iclass 40, count 0 2006.260.07:40:12.13#ibcon#read 6, iclass 40, count 0 2006.260.07:40:12.13#ibcon#end of sib2, iclass 40, count 0 2006.260.07:40:12.13#ibcon#*after write, iclass 40, count 0 2006.260.07:40:12.13#ibcon#*before return 0, iclass 40, count 0 2006.260.07:40:12.13#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:40:12.13#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:40:12.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:40:12.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:40:12.13$vc4f8/vblo=2,640.99 2006.260.07:40:12.13#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:40:12.13#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:40:12.13#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:12.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:12.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:12.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:12.13#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:40:12.13#ibcon#first serial, iclass 4, count 0 2006.260.07:40:12.13#ibcon#enter sib2, iclass 4, count 0 2006.260.07:40:12.13#ibcon#flushed, iclass 4, count 0 2006.260.07:40:12.13#ibcon#about to write, iclass 4, count 0 2006.260.07:40:12.13#ibcon#wrote, iclass 4, count 0 2006.260.07:40:12.13#ibcon#about to read 3, iclass 4, count 0 2006.260.07:40:12.15#ibcon#read 3, iclass 4, count 0 2006.260.07:40:12.15#ibcon#about to read 4, iclass 4, count 0 2006.260.07:40:12.15#ibcon#read 4, iclass 4, count 0 2006.260.07:40:12.15#ibcon#about to read 5, iclass 4, count 0 2006.260.07:40:12.15#ibcon#read 5, iclass 4, count 0 2006.260.07:40:12.15#ibcon#about to read 6, iclass 4, count 0 2006.260.07:40:12.15#ibcon#read 6, iclass 4, count 0 2006.260.07:40:12.15#ibcon#end of sib2, iclass 4, count 0 2006.260.07:40:12.15#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:40:12.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:40:12.15#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:40:12.15#ibcon#*before write, iclass 4, count 0 2006.260.07:40:12.15#ibcon#enter sib2, iclass 4, count 0 2006.260.07:40:12.15#ibcon#flushed, iclass 4, count 0 2006.260.07:40:12.15#ibcon#about to write, iclass 4, count 0 2006.260.07:40:12.15#ibcon#wrote, iclass 4, count 0 2006.260.07:40:12.15#ibcon#about to read 3, iclass 4, count 0 2006.260.07:40:12.19#ibcon#read 3, iclass 4, count 0 2006.260.07:40:12.19#ibcon#about to read 4, iclass 4, count 0 2006.260.07:40:12.19#ibcon#read 4, iclass 4, count 0 2006.260.07:40:12.19#ibcon#about to read 5, iclass 4, count 0 2006.260.07:40:12.19#ibcon#read 5, iclass 4, count 0 2006.260.07:40:12.19#ibcon#about to read 6, iclass 4, count 0 2006.260.07:40:12.19#ibcon#read 6, iclass 4, count 0 2006.260.07:40:12.19#ibcon#end of sib2, iclass 4, count 0 2006.260.07:40:12.19#ibcon#*after write, iclass 4, count 0 2006.260.07:40:12.19#ibcon#*before return 0, iclass 4, count 0 2006.260.07:40:12.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:12.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:40:12.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:40:12.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:40:12.19$vc4f8/vb=2,5 2006.260.07:40:12.19#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:40:12.19#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:40:12.19#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:12.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:12.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:12.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:12.25#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:40:12.25#ibcon#first serial, iclass 6, count 2 2006.260.07:40:12.25#ibcon#enter sib2, iclass 6, count 2 2006.260.07:40:12.25#ibcon#flushed, iclass 6, count 2 2006.260.07:40:12.25#ibcon#about to write, iclass 6, count 2 2006.260.07:40:12.25#ibcon#wrote, iclass 6, count 2 2006.260.07:40:12.25#ibcon#about to read 3, iclass 6, count 2 2006.260.07:40:12.27#ibcon#read 3, iclass 6, count 2 2006.260.07:40:12.27#ibcon#about to read 4, iclass 6, count 2 2006.260.07:40:12.27#ibcon#read 4, iclass 6, count 2 2006.260.07:40:12.27#ibcon#about to read 5, iclass 6, count 2 2006.260.07:40:12.27#ibcon#read 5, iclass 6, count 2 2006.260.07:40:12.27#ibcon#about to read 6, iclass 6, count 2 2006.260.07:40:12.27#ibcon#read 6, iclass 6, count 2 2006.260.07:40:12.27#ibcon#end of sib2, iclass 6, count 2 2006.260.07:40:12.27#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:40:12.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:40:12.27#ibcon#[27=AT02-05\r\n] 2006.260.07:40:12.27#ibcon#*before write, iclass 6, count 2 2006.260.07:40:12.27#ibcon#enter sib2, iclass 6, count 2 2006.260.07:40:12.27#ibcon#flushed, iclass 6, count 2 2006.260.07:40:12.27#ibcon#about to write, iclass 6, count 2 2006.260.07:40:12.27#ibcon#wrote, iclass 6, count 2 2006.260.07:40:12.27#ibcon#about to read 3, iclass 6, count 2 2006.260.07:40:12.30#ibcon#read 3, iclass 6, count 2 2006.260.07:40:12.30#ibcon#about to read 4, iclass 6, count 2 2006.260.07:40:12.30#ibcon#read 4, iclass 6, count 2 2006.260.07:40:12.30#ibcon#about to read 5, iclass 6, count 2 2006.260.07:40:12.30#ibcon#read 5, iclass 6, count 2 2006.260.07:40:12.30#ibcon#about to read 6, iclass 6, count 2 2006.260.07:40:12.30#ibcon#read 6, iclass 6, count 2 2006.260.07:40:12.30#ibcon#end of sib2, iclass 6, count 2 2006.260.07:40:12.30#ibcon#*after write, iclass 6, count 2 2006.260.07:40:12.30#ibcon#*before return 0, iclass 6, count 2 2006.260.07:40:12.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:12.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:40:12.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:40:12.30#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:12.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:12.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:12.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:12.42#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:40:12.42#ibcon#first serial, iclass 6, count 0 2006.260.07:40:12.42#ibcon#enter sib2, iclass 6, count 0 2006.260.07:40:12.42#ibcon#flushed, iclass 6, count 0 2006.260.07:40:12.42#ibcon#about to write, iclass 6, count 0 2006.260.07:40:12.42#ibcon#wrote, iclass 6, count 0 2006.260.07:40:12.42#ibcon#about to read 3, iclass 6, count 0 2006.260.07:40:12.44#ibcon#read 3, iclass 6, count 0 2006.260.07:40:12.44#ibcon#about to read 4, iclass 6, count 0 2006.260.07:40:12.44#ibcon#read 4, iclass 6, count 0 2006.260.07:40:12.44#ibcon#about to read 5, iclass 6, count 0 2006.260.07:40:12.44#ibcon#read 5, iclass 6, count 0 2006.260.07:40:12.44#ibcon#about to read 6, iclass 6, count 0 2006.260.07:40:12.44#ibcon#read 6, iclass 6, count 0 2006.260.07:40:12.44#ibcon#end of sib2, iclass 6, count 0 2006.260.07:40:12.44#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:40:12.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:40:12.44#ibcon#[27=USB\r\n] 2006.260.07:40:12.44#ibcon#*before write, iclass 6, count 0 2006.260.07:40:12.44#ibcon#enter sib2, iclass 6, count 0 2006.260.07:40:12.44#ibcon#flushed, iclass 6, count 0 2006.260.07:40:12.44#ibcon#about to write, iclass 6, count 0 2006.260.07:40:12.44#ibcon#wrote, iclass 6, count 0 2006.260.07:40:12.44#ibcon#about to read 3, iclass 6, count 0 2006.260.07:40:12.47#ibcon#read 3, iclass 6, count 0 2006.260.07:40:12.47#ibcon#about to read 4, iclass 6, count 0 2006.260.07:40:12.47#ibcon#read 4, iclass 6, count 0 2006.260.07:40:12.47#ibcon#about to read 5, iclass 6, count 0 2006.260.07:40:12.47#ibcon#read 5, iclass 6, count 0 2006.260.07:40:12.47#ibcon#about to read 6, iclass 6, count 0 2006.260.07:40:12.47#ibcon#read 6, iclass 6, count 0 2006.260.07:40:12.47#ibcon#end of sib2, iclass 6, count 0 2006.260.07:40:12.47#ibcon#*after write, iclass 6, count 0 2006.260.07:40:12.47#ibcon#*before return 0, iclass 6, count 0 2006.260.07:40:12.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:12.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:40:12.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:40:12.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:40:12.47$vc4f8/vblo=3,656.99 2006.260.07:40:12.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:40:12.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:40:12.47#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:12.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:12.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:12.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:12.47#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:40:12.47#ibcon#first serial, iclass 10, count 0 2006.260.07:40:12.47#ibcon#enter sib2, iclass 10, count 0 2006.260.07:40:12.47#ibcon#flushed, iclass 10, count 0 2006.260.07:40:12.47#ibcon#about to write, iclass 10, count 0 2006.260.07:40:12.47#ibcon#wrote, iclass 10, count 0 2006.260.07:40:12.47#ibcon#about to read 3, iclass 10, count 0 2006.260.07:40:12.49#ibcon#read 3, iclass 10, count 0 2006.260.07:40:12.49#ibcon#about to read 4, iclass 10, count 0 2006.260.07:40:12.49#ibcon#read 4, iclass 10, count 0 2006.260.07:40:12.49#ibcon#about to read 5, iclass 10, count 0 2006.260.07:40:12.49#ibcon#read 5, iclass 10, count 0 2006.260.07:40:12.49#ibcon#about to read 6, iclass 10, count 0 2006.260.07:40:12.49#ibcon#read 6, iclass 10, count 0 2006.260.07:40:12.49#ibcon#end of sib2, iclass 10, count 0 2006.260.07:40:12.49#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:40:12.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:40:12.49#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:40:12.49#ibcon#*before write, iclass 10, count 0 2006.260.07:40:12.49#ibcon#enter sib2, iclass 10, count 0 2006.260.07:40:12.49#ibcon#flushed, iclass 10, count 0 2006.260.07:40:12.49#ibcon#about to write, iclass 10, count 0 2006.260.07:40:12.49#ibcon#wrote, iclass 10, count 0 2006.260.07:40:12.49#ibcon#about to read 3, iclass 10, count 0 2006.260.07:40:12.53#ibcon#read 3, iclass 10, count 0 2006.260.07:40:12.53#ibcon#about to read 4, iclass 10, count 0 2006.260.07:40:12.53#ibcon#read 4, iclass 10, count 0 2006.260.07:40:12.53#ibcon#about to read 5, iclass 10, count 0 2006.260.07:40:12.53#ibcon#read 5, iclass 10, count 0 2006.260.07:40:12.53#ibcon#about to read 6, iclass 10, count 0 2006.260.07:40:12.53#ibcon#read 6, iclass 10, count 0 2006.260.07:40:12.53#ibcon#end of sib2, iclass 10, count 0 2006.260.07:40:12.53#ibcon#*after write, iclass 10, count 0 2006.260.07:40:12.53#ibcon#*before return 0, iclass 10, count 0 2006.260.07:40:12.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:12.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:40:12.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:40:12.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:40:12.53$vc4f8/vb=3,4 2006.260.07:40:12.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:40:12.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:40:12.53#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:12.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:12.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:12.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:12.59#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:40:12.59#ibcon#first serial, iclass 12, count 2 2006.260.07:40:12.59#ibcon#enter sib2, iclass 12, count 2 2006.260.07:40:12.59#ibcon#flushed, iclass 12, count 2 2006.260.07:40:12.59#ibcon#about to write, iclass 12, count 2 2006.260.07:40:12.59#ibcon#wrote, iclass 12, count 2 2006.260.07:40:12.59#ibcon#about to read 3, iclass 12, count 2 2006.260.07:40:12.61#ibcon#read 3, iclass 12, count 2 2006.260.07:40:12.61#ibcon#about to read 4, iclass 12, count 2 2006.260.07:40:12.61#ibcon#read 4, iclass 12, count 2 2006.260.07:40:12.61#ibcon#about to read 5, iclass 12, count 2 2006.260.07:40:12.61#ibcon#read 5, iclass 12, count 2 2006.260.07:40:12.61#ibcon#about to read 6, iclass 12, count 2 2006.260.07:40:12.61#ibcon#read 6, iclass 12, count 2 2006.260.07:40:12.61#ibcon#end of sib2, iclass 12, count 2 2006.260.07:40:12.61#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:40:12.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:40:12.61#ibcon#[27=AT03-04\r\n] 2006.260.07:40:12.61#ibcon#*before write, iclass 12, count 2 2006.260.07:40:12.61#ibcon#enter sib2, iclass 12, count 2 2006.260.07:40:12.61#ibcon#flushed, iclass 12, count 2 2006.260.07:40:12.61#ibcon#about to write, iclass 12, count 2 2006.260.07:40:12.61#ibcon#wrote, iclass 12, count 2 2006.260.07:40:12.61#ibcon#about to read 3, iclass 12, count 2 2006.260.07:40:12.64#ibcon#read 3, iclass 12, count 2 2006.260.07:40:12.64#ibcon#about to read 4, iclass 12, count 2 2006.260.07:40:12.64#ibcon#read 4, iclass 12, count 2 2006.260.07:40:12.64#ibcon#about to read 5, iclass 12, count 2 2006.260.07:40:12.64#ibcon#read 5, iclass 12, count 2 2006.260.07:40:12.64#ibcon#about to read 6, iclass 12, count 2 2006.260.07:40:12.64#ibcon#read 6, iclass 12, count 2 2006.260.07:40:12.64#ibcon#end of sib2, iclass 12, count 2 2006.260.07:40:12.64#ibcon#*after write, iclass 12, count 2 2006.260.07:40:12.64#ibcon#*before return 0, iclass 12, count 2 2006.260.07:40:12.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:12.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:40:12.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:40:12.64#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:12.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:12.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:12.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:12.76#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:40:12.76#ibcon#first serial, iclass 12, count 0 2006.260.07:40:12.76#ibcon#enter sib2, iclass 12, count 0 2006.260.07:40:12.76#ibcon#flushed, iclass 12, count 0 2006.260.07:40:12.76#ibcon#about to write, iclass 12, count 0 2006.260.07:40:12.76#ibcon#wrote, iclass 12, count 0 2006.260.07:40:12.76#ibcon#about to read 3, iclass 12, count 0 2006.260.07:40:12.78#ibcon#read 3, iclass 12, count 0 2006.260.07:40:12.78#ibcon#about to read 4, iclass 12, count 0 2006.260.07:40:12.78#ibcon#read 4, iclass 12, count 0 2006.260.07:40:12.78#ibcon#about to read 5, iclass 12, count 0 2006.260.07:40:12.78#ibcon#read 5, iclass 12, count 0 2006.260.07:40:12.78#ibcon#about to read 6, iclass 12, count 0 2006.260.07:40:12.78#ibcon#read 6, iclass 12, count 0 2006.260.07:40:12.78#ibcon#end of sib2, iclass 12, count 0 2006.260.07:40:12.78#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:40:12.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:40:12.78#ibcon#[27=USB\r\n] 2006.260.07:40:12.78#ibcon#*before write, iclass 12, count 0 2006.260.07:40:12.78#ibcon#enter sib2, iclass 12, count 0 2006.260.07:40:12.78#ibcon#flushed, iclass 12, count 0 2006.260.07:40:12.78#ibcon#about to write, iclass 12, count 0 2006.260.07:40:12.78#ibcon#wrote, iclass 12, count 0 2006.260.07:40:12.78#ibcon#about to read 3, iclass 12, count 0 2006.260.07:40:12.81#ibcon#read 3, iclass 12, count 0 2006.260.07:40:12.81#ibcon#about to read 4, iclass 12, count 0 2006.260.07:40:12.81#ibcon#read 4, iclass 12, count 0 2006.260.07:40:12.81#ibcon#about to read 5, iclass 12, count 0 2006.260.07:40:12.81#ibcon#read 5, iclass 12, count 0 2006.260.07:40:12.81#ibcon#about to read 6, iclass 12, count 0 2006.260.07:40:12.81#ibcon#read 6, iclass 12, count 0 2006.260.07:40:12.81#ibcon#end of sib2, iclass 12, count 0 2006.260.07:40:12.81#ibcon#*after write, iclass 12, count 0 2006.260.07:40:12.81#ibcon#*before return 0, iclass 12, count 0 2006.260.07:40:12.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:12.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:40:12.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:40:12.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:40:12.81$vc4f8/vblo=4,712.99 2006.260.07:40:12.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:40:12.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:40:12.81#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:12.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:12.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:12.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:12.81#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:40:12.81#ibcon#first serial, iclass 14, count 0 2006.260.07:40:12.81#ibcon#enter sib2, iclass 14, count 0 2006.260.07:40:12.81#ibcon#flushed, iclass 14, count 0 2006.260.07:40:12.81#ibcon#about to write, iclass 14, count 0 2006.260.07:40:12.81#ibcon#wrote, iclass 14, count 0 2006.260.07:40:12.81#ibcon#about to read 3, iclass 14, count 0 2006.260.07:40:12.83#ibcon#read 3, iclass 14, count 0 2006.260.07:40:12.83#ibcon#about to read 4, iclass 14, count 0 2006.260.07:40:12.83#ibcon#read 4, iclass 14, count 0 2006.260.07:40:12.83#ibcon#about to read 5, iclass 14, count 0 2006.260.07:40:12.83#ibcon#read 5, iclass 14, count 0 2006.260.07:40:12.83#ibcon#about to read 6, iclass 14, count 0 2006.260.07:40:12.83#ibcon#read 6, iclass 14, count 0 2006.260.07:40:12.83#ibcon#end of sib2, iclass 14, count 0 2006.260.07:40:12.83#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:40:12.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:40:12.83#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:40:12.83#ibcon#*before write, iclass 14, count 0 2006.260.07:40:12.83#ibcon#enter sib2, iclass 14, count 0 2006.260.07:40:12.83#ibcon#flushed, iclass 14, count 0 2006.260.07:40:12.83#ibcon#about to write, iclass 14, count 0 2006.260.07:40:12.83#ibcon#wrote, iclass 14, count 0 2006.260.07:40:12.83#ibcon#about to read 3, iclass 14, count 0 2006.260.07:40:12.87#ibcon#read 3, iclass 14, count 0 2006.260.07:40:12.87#ibcon#about to read 4, iclass 14, count 0 2006.260.07:40:12.87#ibcon#read 4, iclass 14, count 0 2006.260.07:40:12.87#ibcon#about to read 5, iclass 14, count 0 2006.260.07:40:12.87#ibcon#read 5, iclass 14, count 0 2006.260.07:40:12.87#ibcon#about to read 6, iclass 14, count 0 2006.260.07:40:12.87#ibcon#read 6, iclass 14, count 0 2006.260.07:40:12.87#ibcon#end of sib2, iclass 14, count 0 2006.260.07:40:12.87#ibcon#*after write, iclass 14, count 0 2006.260.07:40:12.87#ibcon#*before return 0, iclass 14, count 0 2006.260.07:40:12.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:12.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:40:12.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:40:12.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:40:12.87$vc4f8/vb=4,5 2006.260.07:40:12.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:40:12.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:40:12.87#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:12.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:12.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:12.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:12.93#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:40:12.93#ibcon#first serial, iclass 16, count 2 2006.260.07:40:12.93#ibcon#enter sib2, iclass 16, count 2 2006.260.07:40:12.93#ibcon#flushed, iclass 16, count 2 2006.260.07:40:12.93#ibcon#about to write, iclass 16, count 2 2006.260.07:40:12.93#ibcon#wrote, iclass 16, count 2 2006.260.07:40:12.93#ibcon#about to read 3, iclass 16, count 2 2006.260.07:40:12.95#ibcon#read 3, iclass 16, count 2 2006.260.07:40:12.95#ibcon#about to read 4, iclass 16, count 2 2006.260.07:40:12.95#ibcon#read 4, iclass 16, count 2 2006.260.07:40:12.95#ibcon#about to read 5, iclass 16, count 2 2006.260.07:40:12.95#ibcon#read 5, iclass 16, count 2 2006.260.07:40:12.95#ibcon#about to read 6, iclass 16, count 2 2006.260.07:40:12.95#ibcon#read 6, iclass 16, count 2 2006.260.07:40:12.95#ibcon#end of sib2, iclass 16, count 2 2006.260.07:40:12.95#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:40:12.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:40:12.95#ibcon#[27=AT04-05\r\n] 2006.260.07:40:12.95#ibcon#*before write, iclass 16, count 2 2006.260.07:40:12.95#ibcon#enter sib2, iclass 16, count 2 2006.260.07:40:12.95#ibcon#flushed, iclass 16, count 2 2006.260.07:40:12.95#ibcon#about to write, iclass 16, count 2 2006.260.07:40:12.95#ibcon#wrote, iclass 16, count 2 2006.260.07:40:12.95#ibcon#about to read 3, iclass 16, count 2 2006.260.07:40:12.98#ibcon#read 3, iclass 16, count 2 2006.260.07:40:12.98#ibcon#about to read 4, iclass 16, count 2 2006.260.07:40:12.98#ibcon#read 4, iclass 16, count 2 2006.260.07:40:12.98#ibcon#about to read 5, iclass 16, count 2 2006.260.07:40:12.98#ibcon#read 5, iclass 16, count 2 2006.260.07:40:12.98#ibcon#about to read 6, iclass 16, count 2 2006.260.07:40:12.98#ibcon#read 6, iclass 16, count 2 2006.260.07:40:12.98#ibcon#end of sib2, iclass 16, count 2 2006.260.07:40:12.98#ibcon#*after write, iclass 16, count 2 2006.260.07:40:12.98#ibcon#*before return 0, iclass 16, count 2 2006.260.07:40:12.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:12.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:40:12.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:40:12.98#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:12.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:13.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:13.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:13.10#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:40:13.10#ibcon#first serial, iclass 16, count 0 2006.260.07:40:13.10#ibcon#enter sib2, iclass 16, count 0 2006.260.07:40:13.10#ibcon#flushed, iclass 16, count 0 2006.260.07:40:13.10#ibcon#about to write, iclass 16, count 0 2006.260.07:40:13.10#ibcon#wrote, iclass 16, count 0 2006.260.07:40:13.10#ibcon#about to read 3, iclass 16, count 0 2006.260.07:40:13.12#ibcon#read 3, iclass 16, count 0 2006.260.07:40:13.12#ibcon#about to read 4, iclass 16, count 0 2006.260.07:40:13.12#ibcon#read 4, iclass 16, count 0 2006.260.07:40:13.12#ibcon#about to read 5, iclass 16, count 0 2006.260.07:40:13.12#ibcon#read 5, iclass 16, count 0 2006.260.07:40:13.12#ibcon#about to read 6, iclass 16, count 0 2006.260.07:40:13.12#ibcon#read 6, iclass 16, count 0 2006.260.07:40:13.12#ibcon#end of sib2, iclass 16, count 0 2006.260.07:40:13.12#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:40:13.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:40:13.12#ibcon#[27=USB\r\n] 2006.260.07:40:13.12#ibcon#*before write, iclass 16, count 0 2006.260.07:40:13.12#ibcon#enter sib2, iclass 16, count 0 2006.260.07:40:13.12#ibcon#flushed, iclass 16, count 0 2006.260.07:40:13.12#ibcon#about to write, iclass 16, count 0 2006.260.07:40:13.12#ibcon#wrote, iclass 16, count 0 2006.260.07:40:13.12#ibcon#about to read 3, iclass 16, count 0 2006.260.07:40:13.15#ibcon#read 3, iclass 16, count 0 2006.260.07:40:13.15#ibcon#about to read 4, iclass 16, count 0 2006.260.07:40:13.15#ibcon#read 4, iclass 16, count 0 2006.260.07:40:13.15#ibcon#about to read 5, iclass 16, count 0 2006.260.07:40:13.15#ibcon#read 5, iclass 16, count 0 2006.260.07:40:13.15#ibcon#about to read 6, iclass 16, count 0 2006.260.07:40:13.15#ibcon#read 6, iclass 16, count 0 2006.260.07:40:13.15#ibcon#end of sib2, iclass 16, count 0 2006.260.07:40:13.15#ibcon#*after write, iclass 16, count 0 2006.260.07:40:13.15#ibcon#*before return 0, iclass 16, count 0 2006.260.07:40:13.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:13.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:40:13.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:40:13.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:40:13.15$vc4f8/vblo=5,744.99 2006.260.07:40:13.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:40:13.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:40:13.15#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:13.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:13.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:13.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:13.15#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:40:13.15#ibcon#first serial, iclass 18, count 0 2006.260.07:40:13.15#ibcon#enter sib2, iclass 18, count 0 2006.260.07:40:13.15#ibcon#flushed, iclass 18, count 0 2006.260.07:40:13.15#ibcon#about to write, iclass 18, count 0 2006.260.07:40:13.15#ibcon#wrote, iclass 18, count 0 2006.260.07:40:13.15#ibcon#about to read 3, iclass 18, count 0 2006.260.07:40:13.17#ibcon#read 3, iclass 18, count 0 2006.260.07:40:13.17#ibcon#about to read 4, iclass 18, count 0 2006.260.07:40:13.17#ibcon#read 4, iclass 18, count 0 2006.260.07:40:13.17#ibcon#about to read 5, iclass 18, count 0 2006.260.07:40:13.17#ibcon#read 5, iclass 18, count 0 2006.260.07:40:13.17#ibcon#about to read 6, iclass 18, count 0 2006.260.07:40:13.17#ibcon#read 6, iclass 18, count 0 2006.260.07:40:13.17#ibcon#end of sib2, iclass 18, count 0 2006.260.07:40:13.17#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:40:13.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:40:13.17#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:40:13.17#ibcon#*before write, iclass 18, count 0 2006.260.07:40:13.17#ibcon#enter sib2, iclass 18, count 0 2006.260.07:40:13.17#ibcon#flushed, iclass 18, count 0 2006.260.07:40:13.17#ibcon#about to write, iclass 18, count 0 2006.260.07:40:13.17#ibcon#wrote, iclass 18, count 0 2006.260.07:40:13.17#ibcon#about to read 3, iclass 18, count 0 2006.260.07:40:13.21#ibcon#read 3, iclass 18, count 0 2006.260.07:40:13.21#ibcon#about to read 4, iclass 18, count 0 2006.260.07:40:13.21#ibcon#read 4, iclass 18, count 0 2006.260.07:40:13.21#ibcon#about to read 5, iclass 18, count 0 2006.260.07:40:13.21#ibcon#read 5, iclass 18, count 0 2006.260.07:40:13.21#ibcon#about to read 6, iclass 18, count 0 2006.260.07:40:13.21#ibcon#read 6, iclass 18, count 0 2006.260.07:40:13.21#ibcon#end of sib2, iclass 18, count 0 2006.260.07:40:13.21#ibcon#*after write, iclass 18, count 0 2006.260.07:40:13.21#ibcon#*before return 0, iclass 18, count 0 2006.260.07:40:13.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:13.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:40:13.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:40:13.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:40:13.21$vc4f8/vb=5,4 2006.260.07:40:13.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:40:13.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:40:13.21#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:13.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:13.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:13.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:13.27#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:40:13.27#ibcon#first serial, iclass 20, count 2 2006.260.07:40:13.27#ibcon#enter sib2, iclass 20, count 2 2006.260.07:40:13.27#ibcon#flushed, iclass 20, count 2 2006.260.07:40:13.27#ibcon#about to write, iclass 20, count 2 2006.260.07:40:13.27#ibcon#wrote, iclass 20, count 2 2006.260.07:40:13.27#ibcon#about to read 3, iclass 20, count 2 2006.260.07:40:13.29#ibcon#read 3, iclass 20, count 2 2006.260.07:40:13.29#ibcon#about to read 4, iclass 20, count 2 2006.260.07:40:13.29#ibcon#read 4, iclass 20, count 2 2006.260.07:40:13.29#ibcon#about to read 5, iclass 20, count 2 2006.260.07:40:13.29#ibcon#read 5, iclass 20, count 2 2006.260.07:40:13.29#ibcon#about to read 6, iclass 20, count 2 2006.260.07:40:13.29#ibcon#read 6, iclass 20, count 2 2006.260.07:40:13.29#ibcon#end of sib2, iclass 20, count 2 2006.260.07:40:13.29#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:40:13.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:40:13.29#ibcon#[27=AT05-04\r\n] 2006.260.07:40:13.29#ibcon#*before write, iclass 20, count 2 2006.260.07:40:13.29#ibcon#enter sib2, iclass 20, count 2 2006.260.07:40:13.29#ibcon#flushed, iclass 20, count 2 2006.260.07:40:13.29#ibcon#about to write, iclass 20, count 2 2006.260.07:40:13.29#ibcon#wrote, iclass 20, count 2 2006.260.07:40:13.29#ibcon#about to read 3, iclass 20, count 2 2006.260.07:40:13.32#ibcon#read 3, iclass 20, count 2 2006.260.07:40:13.32#ibcon#about to read 4, iclass 20, count 2 2006.260.07:40:13.32#ibcon#read 4, iclass 20, count 2 2006.260.07:40:13.32#ibcon#about to read 5, iclass 20, count 2 2006.260.07:40:13.32#ibcon#read 5, iclass 20, count 2 2006.260.07:40:13.32#ibcon#about to read 6, iclass 20, count 2 2006.260.07:40:13.32#ibcon#read 6, iclass 20, count 2 2006.260.07:40:13.32#ibcon#end of sib2, iclass 20, count 2 2006.260.07:40:13.32#ibcon#*after write, iclass 20, count 2 2006.260.07:40:13.32#ibcon#*before return 0, iclass 20, count 2 2006.260.07:40:13.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:13.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:40:13.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:40:13.32#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:13.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:13.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:13.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:13.44#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:40:13.44#ibcon#first serial, iclass 20, count 0 2006.260.07:40:13.44#ibcon#enter sib2, iclass 20, count 0 2006.260.07:40:13.44#ibcon#flushed, iclass 20, count 0 2006.260.07:40:13.44#ibcon#about to write, iclass 20, count 0 2006.260.07:40:13.44#ibcon#wrote, iclass 20, count 0 2006.260.07:40:13.44#ibcon#about to read 3, iclass 20, count 0 2006.260.07:40:13.46#ibcon#read 3, iclass 20, count 0 2006.260.07:40:13.46#ibcon#about to read 4, iclass 20, count 0 2006.260.07:40:13.46#ibcon#read 4, iclass 20, count 0 2006.260.07:40:13.46#ibcon#about to read 5, iclass 20, count 0 2006.260.07:40:13.46#ibcon#read 5, iclass 20, count 0 2006.260.07:40:13.46#ibcon#about to read 6, iclass 20, count 0 2006.260.07:40:13.46#ibcon#read 6, iclass 20, count 0 2006.260.07:40:13.46#ibcon#end of sib2, iclass 20, count 0 2006.260.07:40:13.46#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:40:13.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:40:13.46#ibcon#[27=USB\r\n] 2006.260.07:40:13.46#ibcon#*before write, iclass 20, count 0 2006.260.07:40:13.46#ibcon#enter sib2, iclass 20, count 0 2006.260.07:40:13.46#ibcon#flushed, iclass 20, count 0 2006.260.07:40:13.46#ibcon#about to write, iclass 20, count 0 2006.260.07:40:13.46#ibcon#wrote, iclass 20, count 0 2006.260.07:40:13.46#ibcon#about to read 3, iclass 20, count 0 2006.260.07:40:13.49#ibcon#read 3, iclass 20, count 0 2006.260.07:40:13.49#ibcon#about to read 4, iclass 20, count 0 2006.260.07:40:13.49#ibcon#read 4, iclass 20, count 0 2006.260.07:40:13.49#ibcon#about to read 5, iclass 20, count 0 2006.260.07:40:13.49#ibcon#read 5, iclass 20, count 0 2006.260.07:40:13.49#ibcon#about to read 6, iclass 20, count 0 2006.260.07:40:13.49#ibcon#read 6, iclass 20, count 0 2006.260.07:40:13.49#ibcon#end of sib2, iclass 20, count 0 2006.260.07:40:13.49#ibcon#*after write, iclass 20, count 0 2006.260.07:40:13.49#ibcon#*before return 0, iclass 20, count 0 2006.260.07:40:13.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:13.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:40:13.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:40:13.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:40:13.49$vc4f8/vblo=6,752.99 2006.260.07:40:13.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:40:13.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:40:13.49#ibcon#ireg 17 cls_cnt 0 2006.260.07:40:13.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:13.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:13.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:13.49#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:40:13.49#ibcon#first serial, iclass 22, count 0 2006.260.07:40:13.49#ibcon#enter sib2, iclass 22, count 0 2006.260.07:40:13.49#ibcon#flushed, iclass 22, count 0 2006.260.07:40:13.49#ibcon#about to write, iclass 22, count 0 2006.260.07:40:13.49#ibcon#wrote, iclass 22, count 0 2006.260.07:40:13.49#ibcon#about to read 3, iclass 22, count 0 2006.260.07:40:13.51#ibcon#read 3, iclass 22, count 0 2006.260.07:40:13.51#ibcon#about to read 4, iclass 22, count 0 2006.260.07:40:13.51#ibcon#read 4, iclass 22, count 0 2006.260.07:40:13.51#ibcon#about to read 5, iclass 22, count 0 2006.260.07:40:13.51#ibcon#read 5, iclass 22, count 0 2006.260.07:40:13.51#ibcon#about to read 6, iclass 22, count 0 2006.260.07:40:13.51#ibcon#read 6, iclass 22, count 0 2006.260.07:40:13.51#ibcon#end of sib2, iclass 22, count 0 2006.260.07:40:13.51#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:40:13.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:40:13.51#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:40:13.51#ibcon#*before write, iclass 22, count 0 2006.260.07:40:13.51#ibcon#enter sib2, iclass 22, count 0 2006.260.07:40:13.51#ibcon#flushed, iclass 22, count 0 2006.260.07:40:13.51#ibcon#about to write, iclass 22, count 0 2006.260.07:40:13.51#ibcon#wrote, iclass 22, count 0 2006.260.07:40:13.51#ibcon#about to read 3, iclass 22, count 0 2006.260.07:40:13.55#ibcon#read 3, iclass 22, count 0 2006.260.07:40:13.55#ibcon#about to read 4, iclass 22, count 0 2006.260.07:40:13.55#ibcon#read 4, iclass 22, count 0 2006.260.07:40:13.55#ibcon#about to read 5, iclass 22, count 0 2006.260.07:40:13.55#ibcon#read 5, iclass 22, count 0 2006.260.07:40:13.55#ibcon#about to read 6, iclass 22, count 0 2006.260.07:40:13.55#ibcon#read 6, iclass 22, count 0 2006.260.07:40:13.55#ibcon#end of sib2, iclass 22, count 0 2006.260.07:40:13.55#ibcon#*after write, iclass 22, count 0 2006.260.07:40:13.55#ibcon#*before return 0, iclass 22, count 0 2006.260.07:40:13.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:13.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:40:13.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:40:13.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:40:13.55$vc4f8/vb=6,4 2006.260.07:40:13.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:40:13.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:40:13.55#ibcon#ireg 11 cls_cnt 2 2006.260.07:40:13.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:13.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:13.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:13.61#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:40:13.61#ibcon#first serial, iclass 24, count 2 2006.260.07:40:13.61#ibcon#enter sib2, iclass 24, count 2 2006.260.07:40:13.61#ibcon#flushed, iclass 24, count 2 2006.260.07:40:13.61#ibcon#about to write, iclass 24, count 2 2006.260.07:40:13.61#ibcon#wrote, iclass 24, count 2 2006.260.07:40:13.61#ibcon#about to read 3, iclass 24, count 2 2006.260.07:40:13.63#ibcon#read 3, iclass 24, count 2 2006.260.07:40:13.63#ibcon#about to read 4, iclass 24, count 2 2006.260.07:40:13.63#ibcon#read 4, iclass 24, count 2 2006.260.07:40:13.63#ibcon#about to read 5, iclass 24, count 2 2006.260.07:40:13.63#ibcon#read 5, iclass 24, count 2 2006.260.07:40:13.63#ibcon#about to read 6, iclass 24, count 2 2006.260.07:40:13.63#ibcon#read 6, iclass 24, count 2 2006.260.07:40:13.63#ibcon#end of sib2, iclass 24, count 2 2006.260.07:40:13.63#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:40:13.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:40:13.63#ibcon#[27=AT06-04\r\n] 2006.260.07:40:13.63#ibcon#*before write, iclass 24, count 2 2006.260.07:40:13.63#ibcon#enter sib2, iclass 24, count 2 2006.260.07:40:13.63#ibcon#flushed, iclass 24, count 2 2006.260.07:40:13.63#ibcon#about to write, iclass 24, count 2 2006.260.07:40:13.63#ibcon#wrote, iclass 24, count 2 2006.260.07:40:13.63#ibcon#about to read 3, iclass 24, count 2 2006.260.07:40:13.66#ibcon#read 3, iclass 24, count 2 2006.260.07:40:13.66#ibcon#about to read 4, iclass 24, count 2 2006.260.07:40:13.66#ibcon#read 4, iclass 24, count 2 2006.260.07:40:13.66#ibcon#about to read 5, iclass 24, count 2 2006.260.07:40:13.66#ibcon#read 5, iclass 24, count 2 2006.260.07:40:13.66#ibcon#about to read 6, iclass 24, count 2 2006.260.07:40:13.66#ibcon#read 6, iclass 24, count 2 2006.260.07:40:13.66#ibcon#end of sib2, iclass 24, count 2 2006.260.07:40:13.66#ibcon#*after write, iclass 24, count 2 2006.260.07:40:13.66#ibcon#*before return 0, iclass 24, count 2 2006.260.07:40:13.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:13.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:40:13.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:40:13.66#ibcon#ireg 7 cls_cnt 0 2006.260.07:40:13.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:13.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:13.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:13.78#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:40:13.78#ibcon#first serial, iclass 24, count 0 2006.260.07:40:13.78#ibcon#enter sib2, iclass 24, count 0 2006.260.07:40:13.78#ibcon#flushed, iclass 24, count 0 2006.260.07:40:13.78#ibcon#about to write, iclass 24, count 0 2006.260.07:40:13.78#ibcon#wrote, iclass 24, count 0 2006.260.07:40:13.78#ibcon#about to read 3, iclass 24, count 0 2006.260.07:40:13.80#ibcon#read 3, iclass 24, count 0 2006.260.07:40:13.80#ibcon#about to read 4, iclass 24, count 0 2006.260.07:40:13.80#ibcon#read 4, iclass 24, count 0 2006.260.07:40:13.80#ibcon#about to read 5, iclass 24, count 0 2006.260.07:40:13.80#ibcon#read 5, iclass 24, count 0 2006.260.07:40:13.80#ibcon#about to read 6, iclass 24, count 0 2006.260.07:40:13.80#ibcon#read 6, iclass 24, count 0 2006.260.07:40:13.80#ibcon#end of sib2, iclass 24, count 0 2006.260.07:40:13.80#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:40:13.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:40:13.80#ibcon#[27=USB\r\n] 2006.260.07:40:13.80#ibcon#*before write, iclass 24, count 0 2006.260.07:40:13.80#ibcon#enter sib2, iclass 24, count 0 2006.260.07:40:13.80#ibcon#flushed, iclass 24, count 0 2006.260.07:40:13.80#ibcon#about to write, iclass 24, count 0 2006.260.07:40:13.80#ibcon#wrote, iclass 24, count 0 2006.260.07:40:13.80#ibcon#about to read 3, iclass 24, count 0 2006.260.07:40:13.83#ibcon#read 3, iclass 24, count 0 2006.260.07:40:13.83#ibcon#about to read 4, iclass 24, count 0 2006.260.07:40:13.83#ibcon#read 4, iclass 24, count 0 2006.260.07:40:13.83#ibcon#about to read 5, iclass 24, count 0 2006.260.07:40:13.83#ibcon#read 5, iclass 24, count 0 2006.260.07:40:13.83#ibcon#about to read 6, iclass 24, count 0 2006.260.07:40:13.83#ibcon#read 6, iclass 24, count 0 2006.260.07:40:13.83#ibcon#end of sib2, iclass 24, count 0 2006.260.07:40:13.83#ibcon#*after write, iclass 24, count 0 2006.260.07:40:13.83#ibcon#*before return 0, iclass 24, count 0 2006.260.07:40:13.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:13.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:40:13.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:40:13.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:40:13.83$vc4f8/vabw=wide 2006.260.07:40:13.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:40:13.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:40:13.83#ibcon#ireg 8 cls_cnt 0 2006.260.07:40:13.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:13.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:13.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:13.83#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:40:13.83#ibcon#first serial, iclass 26, count 0 2006.260.07:40:13.83#ibcon#enter sib2, iclass 26, count 0 2006.260.07:40:13.83#ibcon#flushed, iclass 26, count 0 2006.260.07:40:13.83#ibcon#about to write, iclass 26, count 0 2006.260.07:40:13.83#ibcon#wrote, iclass 26, count 0 2006.260.07:40:13.83#ibcon#about to read 3, iclass 26, count 0 2006.260.07:40:13.85#ibcon#read 3, iclass 26, count 0 2006.260.07:40:13.85#ibcon#about to read 4, iclass 26, count 0 2006.260.07:40:13.85#ibcon#read 4, iclass 26, count 0 2006.260.07:40:13.85#ibcon#about to read 5, iclass 26, count 0 2006.260.07:40:13.85#ibcon#read 5, iclass 26, count 0 2006.260.07:40:13.85#ibcon#about to read 6, iclass 26, count 0 2006.260.07:40:13.85#ibcon#read 6, iclass 26, count 0 2006.260.07:40:13.85#ibcon#end of sib2, iclass 26, count 0 2006.260.07:40:13.85#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:40:13.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:40:13.85#ibcon#[25=BW32\r\n] 2006.260.07:40:13.85#ibcon#*before write, iclass 26, count 0 2006.260.07:40:13.85#ibcon#enter sib2, iclass 26, count 0 2006.260.07:40:13.85#ibcon#flushed, iclass 26, count 0 2006.260.07:40:13.85#ibcon#about to write, iclass 26, count 0 2006.260.07:40:13.85#ibcon#wrote, iclass 26, count 0 2006.260.07:40:13.85#ibcon#about to read 3, iclass 26, count 0 2006.260.07:40:13.88#ibcon#read 3, iclass 26, count 0 2006.260.07:40:13.88#ibcon#about to read 4, iclass 26, count 0 2006.260.07:40:13.88#ibcon#read 4, iclass 26, count 0 2006.260.07:40:13.88#ibcon#about to read 5, iclass 26, count 0 2006.260.07:40:13.88#ibcon#read 5, iclass 26, count 0 2006.260.07:40:13.88#ibcon#about to read 6, iclass 26, count 0 2006.260.07:40:13.88#ibcon#read 6, iclass 26, count 0 2006.260.07:40:13.88#ibcon#end of sib2, iclass 26, count 0 2006.260.07:40:13.88#ibcon#*after write, iclass 26, count 0 2006.260.07:40:13.88#ibcon#*before return 0, iclass 26, count 0 2006.260.07:40:13.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:13.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:40:13.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:40:13.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:40:13.88$vc4f8/vbbw=wide 2006.260.07:40:13.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:40:13.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:40:13.88#ibcon#ireg 8 cls_cnt 0 2006.260.07:40:13.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:40:13.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:40:13.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:40:13.95#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:40:13.95#ibcon#first serial, iclass 28, count 0 2006.260.07:40:13.95#ibcon#enter sib2, iclass 28, count 0 2006.260.07:40:13.95#ibcon#flushed, iclass 28, count 0 2006.260.07:40:13.95#ibcon#about to write, iclass 28, count 0 2006.260.07:40:13.95#ibcon#wrote, iclass 28, count 0 2006.260.07:40:13.95#ibcon#about to read 3, iclass 28, count 0 2006.260.07:40:13.98#ibcon#read 3, iclass 28, count 0 2006.260.07:40:13.98#ibcon#about to read 4, iclass 28, count 0 2006.260.07:40:13.98#ibcon#read 4, iclass 28, count 0 2006.260.07:40:13.98#ibcon#about to read 5, iclass 28, count 0 2006.260.07:40:13.98#ibcon#read 5, iclass 28, count 0 2006.260.07:40:13.98#ibcon#about to read 6, iclass 28, count 0 2006.260.07:40:13.98#ibcon#read 6, iclass 28, count 0 2006.260.07:40:13.98#ibcon#end of sib2, iclass 28, count 0 2006.260.07:40:13.98#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:40:13.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:40:13.98#ibcon#[27=BW32\r\n] 2006.260.07:40:13.98#ibcon#*before write, iclass 28, count 0 2006.260.07:40:13.98#ibcon#enter sib2, iclass 28, count 0 2006.260.07:40:13.98#ibcon#flushed, iclass 28, count 0 2006.260.07:40:13.98#ibcon#about to write, iclass 28, count 0 2006.260.07:40:13.98#ibcon#wrote, iclass 28, count 0 2006.260.07:40:13.98#ibcon#about to read 3, iclass 28, count 0 2006.260.07:40:14.01#ibcon#read 3, iclass 28, count 0 2006.260.07:40:14.01#ibcon#about to read 4, iclass 28, count 0 2006.260.07:40:14.01#ibcon#read 4, iclass 28, count 0 2006.260.07:40:14.01#ibcon#about to read 5, iclass 28, count 0 2006.260.07:40:14.01#ibcon#read 5, iclass 28, count 0 2006.260.07:40:14.01#ibcon#about to read 6, iclass 28, count 0 2006.260.07:40:14.01#ibcon#read 6, iclass 28, count 0 2006.260.07:40:14.01#ibcon#end of sib2, iclass 28, count 0 2006.260.07:40:14.01#ibcon#*after write, iclass 28, count 0 2006.260.07:40:14.01#ibcon#*before return 0, iclass 28, count 0 2006.260.07:40:14.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:40:14.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:40:14.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:40:14.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:40:14.01$4f8m12a/ifd4f 2006.260.07:40:14.01$ifd4f/lo= 2006.260.07:40:14.01$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:40:14.01$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:40:14.01$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:40:14.01$ifd4f/patch= 2006.260.07:40:14.01$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:40:14.01$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:40:14.01$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:40:14.01$4f8m12a/"form=m,16.000,1:2 2006.260.07:40:14.01$4f8m12a/"tpicd 2006.260.07:40:14.01$4f8m12a/echo=off 2006.260.07:40:14.01$4f8m12a/xlog=off 2006.260.07:40:14.01:!2006.260.07:40:40 2006.260.07:40:27.14#trakl#Source acquired 2006.260.07:40:28.14#flagr#flagr/antenna,acquired 2006.260.07:40:40.00:preob 2006.260.07:40:41.14/onsource/TRACKING 2006.260.07:40:41.14:!2006.260.07:40:50 2006.260.07:40:50.00:data_valid=on 2006.260.07:40:50.00:midob 2006.260.07:40:50.14/onsource/TRACKING 2006.260.07:40:50.14/wx/23.07,1010.4,87 2006.260.07:40:50.19/cable/+6.4574E-03 2006.260.07:40:51.28/va/01,08,usb,yes,31,33 2006.260.07:40:51.28/va/02,07,usb,yes,31,33 2006.260.07:40:51.28/va/03,08,usb,yes,23,24 2006.260.07:40:51.28/va/04,07,usb,yes,32,35 2006.260.07:40:51.28/va/05,07,usb,yes,35,37 2006.260.07:40:51.28/va/06,06,usb,yes,34,34 2006.260.07:40:51.28/va/07,06,usb,yes,35,35 2006.260.07:40:51.28/va/08,06,usb,yes,37,37 2006.260.07:40:51.51/valo/01,532.99,yes,locked 2006.260.07:40:51.51/valo/02,572.99,yes,locked 2006.260.07:40:51.51/valo/03,672.99,yes,locked 2006.260.07:40:51.51/valo/04,832.99,yes,locked 2006.260.07:40:51.51/valo/05,652.99,yes,locked 2006.260.07:40:51.51/valo/06,772.99,yes,locked 2006.260.07:40:51.51/valo/07,832.99,yes,locked 2006.260.07:40:51.51/valo/08,852.99,yes,locked 2006.260.07:40:52.60/vb/01,04,usb,yes,30,29 2006.260.07:40:52.60/vb/02,05,usb,yes,28,29 2006.260.07:40:52.60/vb/03,04,usb,yes,28,32 2006.260.07:40:52.60/vb/04,05,usb,yes,26,26 2006.260.07:40:52.60/vb/05,04,usb,yes,27,31 2006.260.07:40:52.60/vb/06,04,usb,yes,28,31 2006.260.07:40:52.60/vb/07,04,usb,yes,31,31 2006.260.07:40:52.60/vb/08,04,usb,yes,28,31 2006.260.07:40:52.84/vblo/01,632.99,yes,locked 2006.260.07:40:52.84/vblo/02,640.99,yes,locked 2006.260.07:40:52.84/vblo/03,656.99,yes,locked 2006.260.07:40:52.84/vblo/04,712.99,yes,locked 2006.260.07:40:52.84/vblo/05,744.99,yes,locked 2006.260.07:40:52.84/vblo/06,752.99,yes,locked 2006.260.07:40:52.84/vblo/07,734.99,yes,locked 2006.260.07:40:52.84/vblo/08,744.99,yes,locked 2006.260.07:40:52.99/vabw/8 2006.260.07:40:53.14/vbbw/8 2006.260.07:40:53.23/xfe/off,on,15.0 2006.260.07:40:53.61/ifatt/23,28,28,28 2006.260.07:40:54.08/fmout-gps/S +4.52E-07 2006.260.07:40:54.12:!2006.260.07:41:50 2006.260.07:41:50.00:data_valid=off 2006.260.07:41:50.00:postob 2006.260.07:41:50.11/cable/+6.4557E-03 2006.260.07:41:50.11/wx/23.06,1010.3,87 2006.260.07:41:51.08/fmout-gps/S +4.52E-07 2006.260.07:41:51.08:scan_name=260-0742,k06260,60 2006.260.07:41:51.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.260.07:41:51.14#flagr#flagr/antenna,new-source 2006.260.07:41:52.14:checkk5 2006.260.07:41:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:41:52.98/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:41:53.39/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:41:53.80/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:41:54.19/chk_obsdata//k5ts1/T2600740??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:41:54.60/chk_obsdata//k5ts2/T2600740??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:41:55.03/chk_obsdata//k5ts3/T2600740??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:41:55.44/chk_obsdata//k5ts4/T2600740??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:41:56.24/k5log//k5ts1_log_newline 2006.260.07:41:57.89/k5log//k5ts2_log_newline 2006.260.07:41:58.65/k5log//k5ts3_log_newline 2006.260.07:41:59.48/k5log//k5ts4_log_newline 2006.260.07:41:59.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:41:59.51:4f8m12a=1 2006.260.07:41:59.51$4f8m12a/echo=on 2006.260.07:41:59.51$4f8m12a/pcalon 2006.260.07:41:59.51$pcalon/"no phase cal control is implemented here 2006.260.07:41:59.51$4f8m12a/"tpicd=stop 2006.260.07:41:59.51$4f8m12a/vc4f8 2006.260.07:41:59.51$vc4f8/valo=1,532.99 2006.260.07:41:59.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:41:59.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:41:59.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:41:59.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:41:59.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:41:59.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:41:59.51#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:41:59.51#ibcon#first serial, iclass 35, count 0 2006.260.07:41:59.51#ibcon#enter sib2, iclass 35, count 0 2006.260.07:41:59.51#ibcon#flushed, iclass 35, count 0 2006.260.07:41:59.51#ibcon#about to write, iclass 35, count 0 2006.260.07:41:59.51#ibcon#wrote, iclass 35, count 0 2006.260.07:41:59.51#ibcon#about to read 3, iclass 35, count 0 2006.260.07:41:59.56#ibcon#read 3, iclass 35, count 0 2006.260.07:41:59.56#ibcon#about to read 4, iclass 35, count 0 2006.260.07:41:59.56#ibcon#read 4, iclass 35, count 0 2006.260.07:41:59.56#ibcon#about to read 5, iclass 35, count 0 2006.260.07:41:59.56#ibcon#read 5, iclass 35, count 0 2006.260.07:41:59.56#ibcon#about to read 6, iclass 35, count 0 2006.260.07:41:59.56#ibcon#read 6, iclass 35, count 0 2006.260.07:41:59.56#ibcon#end of sib2, iclass 35, count 0 2006.260.07:41:59.56#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:41:59.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:41:59.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:41:59.56#ibcon#*before write, iclass 35, count 0 2006.260.07:41:59.56#ibcon#enter sib2, iclass 35, count 0 2006.260.07:41:59.56#ibcon#flushed, iclass 35, count 0 2006.260.07:41:59.56#ibcon#about to write, iclass 35, count 0 2006.260.07:41:59.56#ibcon#wrote, iclass 35, count 0 2006.260.07:41:59.56#ibcon#about to read 3, iclass 35, count 0 2006.260.07:41:59.61#ibcon#read 3, iclass 35, count 0 2006.260.07:41:59.61#ibcon#about to read 4, iclass 35, count 0 2006.260.07:41:59.61#ibcon#read 4, iclass 35, count 0 2006.260.07:41:59.61#ibcon#about to read 5, iclass 35, count 0 2006.260.07:41:59.61#ibcon#read 5, iclass 35, count 0 2006.260.07:41:59.61#ibcon#about to read 6, iclass 35, count 0 2006.260.07:41:59.61#ibcon#read 6, iclass 35, count 0 2006.260.07:41:59.61#ibcon#end of sib2, iclass 35, count 0 2006.260.07:41:59.61#ibcon#*after write, iclass 35, count 0 2006.260.07:41:59.61#ibcon#*before return 0, iclass 35, count 0 2006.260.07:41:59.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:41:59.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:41:59.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:41:59.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:41:59.61$vc4f8/va=1,8 2006.260.07:41:59.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:41:59.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:41:59.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:41:59.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:41:59.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:41:59.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:41:59.61#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:41:59.61#ibcon#first serial, iclass 37, count 2 2006.260.07:41:59.61#ibcon#enter sib2, iclass 37, count 2 2006.260.07:41:59.61#ibcon#flushed, iclass 37, count 2 2006.260.07:41:59.61#ibcon#about to write, iclass 37, count 2 2006.260.07:41:59.61#ibcon#wrote, iclass 37, count 2 2006.260.07:41:59.61#ibcon#about to read 3, iclass 37, count 2 2006.260.07:41:59.63#ibcon#read 3, iclass 37, count 2 2006.260.07:41:59.63#ibcon#about to read 4, iclass 37, count 2 2006.260.07:41:59.63#ibcon#read 4, iclass 37, count 2 2006.260.07:41:59.63#ibcon#about to read 5, iclass 37, count 2 2006.260.07:41:59.63#ibcon#read 5, iclass 37, count 2 2006.260.07:41:59.63#ibcon#about to read 6, iclass 37, count 2 2006.260.07:41:59.63#ibcon#read 6, iclass 37, count 2 2006.260.07:41:59.63#ibcon#end of sib2, iclass 37, count 2 2006.260.07:41:59.63#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:41:59.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:41:59.63#ibcon#[25=AT01-08\r\n] 2006.260.07:41:59.63#ibcon#*before write, iclass 37, count 2 2006.260.07:41:59.63#ibcon#enter sib2, iclass 37, count 2 2006.260.07:41:59.63#ibcon#flushed, iclass 37, count 2 2006.260.07:41:59.63#ibcon#about to write, iclass 37, count 2 2006.260.07:41:59.63#ibcon#wrote, iclass 37, count 2 2006.260.07:41:59.63#ibcon#about to read 3, iclass 37, count 2 2006.260.07:41:59.67#ibcon#read 3, iclass 37, count 2 2006.260.07:41:59.67#ibcon#about to read 4, iclass 37, count 2 2006.260.07:41:59.67#ibcon#read 4, iclass 37, count 2 2006.260.07:41:59.67#ibcon#about to read 5, iclass 37, count 2 2006.260.07:41:59.67#ibcon#read 5, iclass 37, count 2 2006.260.07:41:59.67#ibcon#about to read 6, iclass 37, count 2 2006.260.07:41:59.67#ibcon#read 6, iclass 37, count 2 2006.260.07:41:59.67#ibcon#end of sib2, iclass 37, count 2 2006.260.07:41:59.67#ibcon#*after write, iclass 37, count 2 2006.260.07:41:59.67#ibcon#*before return 0, iclass 37, count 2 2006.260.07:41:59.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:41:59.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:41:59.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:41:59.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:41:59.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:41:59.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:41:59.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:41:59.79#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:41:59.79#ibcon#first serial, iclass 37, count 0 2006.260.07:41:59.79#ibcon#enter sib2, iclass 37, count 0 2006.260.07:41:59.79#ibcon#flushed, iclass 37, count 0 2006.260.07:41:59.79#ibcon#about to write, iclass 37, count 0 2006.260.07:41:59.79#ibcon#wrote, iclass 37, count 0 2006.260.07:41:59.79#ibcon#about to read 3, iclass 37, count 0 2006.260.07:41:59.81#ibcon#read 3, iclass 37, count 0 2006.260.07:41:59.81#ibcon#about to read 4, iclass 37, count 0 2006.260.07:41:59.81#ibcon#read 4, iclass 37, count 0 2006.260.07:41:59.81#ibcon#about to read 5, iclass 37, count 0 2006.260.07:41:59.81#ibcon#read 5, iclass 37, count 0 2006.260.07:41:59.81#ibcon#about to read 6, iclass 37, count 0 2006.260.07:41:59.81#ibcon#read 6, iclass 37, count 0 2006.260.07:41:59.81#ibcon#end of sib2, iclass 37, count 0 2006.260.07:41:59.81#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:41:59.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:41:59.81#ibcon#[25=USB\r\n] 2006.260.07:41:59.81#ibcon#*before write, iclass 37, count 0 2006.260.07:41:59.81#ibcon#enter sib2, iclass 37, count 0 2006.260.07:41:59.81#ibcon#flushed, iclass 37, count 0 2006.260.07:41:59.81#ibcon#about to write, iclass 37, count 0 2006.260.07:41:59.81#ibcon#wrote, iclass 37, count 0 2006.260.07:41:59.81#ibcon#about to read 3, iclass 37, count 0 2006.260.07:41:59.84#ibcon#read 3, iclass 37, count 0 2006.260.07:41:59.84#ibcon#about to read 4, iclass 37, count 0 2006.260.07:41:59.84#ibcon#read 4, iclass 37, count 0 2006.260.07:41:59.84#ibcon#about to read 5, iclass 37, count 0 2006.260.07:41:59.84#ibcon#read 5, iclass 37, count 0 2006.260.07:41:59.84#ibcon#about to read 6, iclass 37, count 0 2006.260.07:41:59.84#ibcon#read 6, iclass 37, count 0 2006.260.07:41:59.84#ibcon#end of sib2, iclass 37, count 0 2006.260.07:41:59.84#ibcon#*after write, iclass 37, count 0 2006.260.07:41:59.84#ibcon#*before return 0, iclass 37, count 0 2006.260.07:41:59.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:41:59.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:41:59.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:41:59.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:41:59.84$vc4f8/valo=2,572.99 2006.260.07:41:59.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:41:59.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:41:59.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:41:59.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:41:59.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:41:59.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:41:59.84#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:41:59.84#ibcon#first serial, iclass 39, count 0 2006.260.07:41:59.84#ibcon#enter sib2, iclass 39, count 0 2006.260.07:41:59.84#ibcon#flushed, iclass 39, count 0 2006.260.07:41:59.84#ibcon#about to write, iclass 39, count 0 2006.260.07:41:59.84#ibcon#wrote, iclass 39, count 0 2006.260.07:41:59.84#ibcon#about to read 3, iclass 39, count 0 2006.260.07:41:59.86#ibcon#read 3, iclass 39, count 0 2006.260.07:41:59.86#ibcon#about to read 4, iclass 39, count 0 2006.260.07:41:59.86#ibcon#read 4, iclass 39, count 0 2006.260.07:41:59.86#ibcon#about to read 5, iclass 39, count 0 2006.260.07:41:59.86#ibcon#read 5, iclass 39, count 0 2006.260.07:41:59.86#ibcon#about to read 6, iclass 39, count 0 2006.260.07:41:59.86#ibcon#read 6, iclass 39, count 0 2006.260.07:41:59.86#ibcon#end of sib2, iclass 39, count 0 2006.260.07:41:59.86#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:41:59.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:41:59.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:41:59.86#ibcon#*before write, iclass 39, count 0 2006.260.07:41:59.86#ibcon#enter sib2, iclass 39, count 0 2006.260.07:41:59.86#ibcon#flushed, iclass 39, count 0 2006.260.07:41:59.86#ibcon#about to write, iclass 39, count 0 2006.260.07:41:59.86#ibcon#wrote, iclass 39, count 0 2006.260.07:41:59.86#ibcon#about to read 3, iclass 39, count 0 2006.260.07:41:59.90#ibcon#read 3, iclass 39, count 0 2006.260.07:41:59.90#ibcon#about to read 4, iclass 39, count 0 2006.260.07:41:59.90#ibcon#read 4, iclass 39, count 0 2006.260.07:41:59.90#ibcon#about to read 5, iclass 39, count 0 2006.260.07:41:59.90#ibcon#read 5, iclass 39, count 0 2006.260.07:41:59.90#ibcon#about to read 6, iclass 39, count 0 2006.260.07:41:59.90#ibcon#read 6, iclass 39, count 0 2006.260.07:41:59.90#ibcon#end of sib2, iclass 39, count 0 2006.260.07:41:59.90#ibcon#*after write, iclass 39, count 0 2006.260.07:41:59.90#ibcon#*before return 0, iclass 39, count 0 2006.260.07:41:59.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:41:59.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:41:59.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:41:59.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:41:59.90$vc4f8/va=2,7 2006.260.07:41:59.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:41:59.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:41:59.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:41:59.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:41:59.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:41:59.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:41:59.96#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:41:59.96#ibcon#first serial, iclass 3, count 2 2006.260.07:41:59.96#ibcon#enter sib2, iclass 3, count 2 2006.260.07:41:59.96#ibcon#flushed, iclass 3, count 2 2006.260.07:41:59.96#ibcon#about to write, iclass 3, count 2 2006.260.07:41:59.96#ibcon#wrote, iclass 3, count 2 2006.260.07:41:59.96#ibcon#about to read 3, iclass 3, count 2 2006.260.07:41:59.98#ibcon#read 3, iclass 3, count 2 2006.260.07:41:59.98#ibcon#about to read 4, iclass 3, count 2 2006.260.07:41:59.98#ibcon#read 4, iclass 3, count 2 2006.260.07:41:59.98#ibcon#about to read 5, iclass 3, count 2 2006.260.07:41:59.98#ibcon#read 5, iclass 3, count 2 2006.260.07:41:59.98#ibcon#about to read 6, iclass 3, count 2 2006.260.07:41:59.98#ibcon#read 6, iclass 3, count 2 2006.260.07:41:59.98#ibcon#end of sib2, iclass 3, count 2 2006.260.07:41:59.98#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:41:59.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:41:59.98#ibcon#[25=AT02-07\r\n] 2006.260.07:41:59.98#ibcon#*before write, iclass 3, count 2 2006.260.07:41:59.98#ibcon#enter sib2, iclass 3, count 2 2006.260.07:41:59.98#ibcon#flushed, iclass 3, count 2 2006.260.07:41:59.98#ibcon#about to write, iclass 3, count 2 2006.260.07:41:59.98#ibcon#wrote, iclass 3, count 2 2006.260.07:41:59.98#ibcon#about to read 3, iclass 3, count 2 2006.260.07:42:00.01#ibcon#read 3, iclass 3, count 2 2006.260.07:42:00.01#ibcon#about to read 4, iclass 3, count 2 2006.260.07:42:00.01#ibcon#read 4, iclass 3, count 2 2006.260.07:42:00.01#ibcon#about to read 5, iclass 3, count 2 2006.260.07:42:00.01#ibcon#read 5, iclass 3, count 2 2006.260.07:42:00.01#ibcon#about to read 6, iclass 3, count 2 2006.260.07:42:00.01#ibcon#read 6, iclass 3, count 2 2006.260.07:42:00.01#ibcon#end of sib2, iclass 3, count 2 2006.260.07:42:00.01#ibcon#*after write, iclass 3, count 2 2006.260.07:42:00.01#ibcon#*before return 0, iclass 3, count 2 2006.260.07:42:00.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:00.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:00.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:42:00.01#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:00.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:00.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:00.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:00.13#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:42:00.13#ibcon#first serial, iclass 3, count 0 2006.260.07:42:00.13#ibcon#enter sib2, iclass 3, count 0 2006.260.07:42:00.13#ibcon#flushed, iclass 3, count 0 2006.260.07:42:00.13#ibcon#about to write, iclass 3, count 0 2006.260.07:42:00.13#ibcon#wrote, iclass 3, count 0 2006.260.07:42:00.13#ibcon#about to read 3, iclass 3, count 0 2006.260.07:42:00.15#ibcon#read 3, iclass 3, count 0 2006.260.07:42:00.15#ibcon#about to read 4, iclass 3, count 0 2006.260.07:42:00.15#ibcon#read 4, iclass 3, count 0 2006.260.07:42:00.15#ibcon#about to read 5, iclass 3, count 0 2006.260.07:42:00.15#ibcon#read 5, iclass 3, count 0 2006.260.07:42:00.15#ibcon#about to read 6, iclass 3, count 0 2006.260.07:42:00.15#ibcon#read 6, iclass 3, count 0 2006.260.07:42:00.15#ibcon#end of sib2, iclass 3, count 0 2006.260.07:42:00.15#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:42:00.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:42:00.15#ibcon#[25=USB\r\n] 2006.260.07:42:00.15#ibcon#*before write, iclass 3, count 0 2006.260.07:42:00.15#ibcon#enter sib2, iclass 3, count 0 2006.260.07:42:00.15#ibcon#flushed, iclass 3, count 0 2006.260.07:42:00.15#ibcon#about to write, iclass 3, count 0 2006.260.07:42:00.15#ibcon#wrote, iclass 3, count 0 2006.260.07:42:00.15#ibcon#about to read 3, iclass 3, count 0 2006.260.07:42:00.18#ibcon#read 3, iclass 3, count 0 2006.260.07:42:00.18#ibcon#about to read 4, iclass 3, count 0 2006.260.07:42:00.18#ibcon#read 4, iclass 3, count 0 2006.260.07:42:00.18#ibcon#about to read 5, iclass 3, count 0 2006.260.07:42:00.18#ibcon#read 5, iclass 3, count 0 2006.260.07:42:00.18#ibcon#about to read 6, iclass 3, count 0 2006.260.07:42:00.18#ibcon#read 6, iclass 3, count 0 2006.260.07:42:00.18#ibcon#end of sib2, iclass 3, count 0 2006.260.07:42:00.18#ibcon#*after write, iclass 3, count 0 2006.260.07:42:00.18#ibcon#*before return 0, iclass 3, count 0 2006.260.07:42:00.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:00.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:00.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:42:00.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:42:00.18$vc4f8/valo=3,672.99 2006.260.07:42:00.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:42:00.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:42:00.18#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:00.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:00.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:00.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:00.18#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:42:00.18#ibcon#first serial, iclass 5, count 0 2006.260.07:42:00.18#ibcon#enter sib2, iclass 5, count 0 2006.260.07:42:00.18#ibcon#flushed, iclass 5, count 0 2006.260.07:42:00.18#ibcon#about to write, iclass 5, count 0 2006.260.07:42:00.18#ibcon#wrote, iclass 5, count 0 2006.260.07:42:00.18#ibcon#about to read 3, iclass 5, count 0 2006.260.07:42:00.20#ibcon#read 3, iclass 5, count 0 2006.260.07:42:00.20#ibcon#about to read 4, iclass 5, count 0 2006.260.07:42:00.20#ibcon#read 4, iclass 5, count 0 2006.260.07:42:00.20#ibcon#about to read 5, iclass 5, count 0 2006.260.07:42:00.20#ibcon#read 5, iclass 5, count 0 2006.260.07:42:00.20#ibcon#about to read 6, iclass 5, count 0 2006.260.07:42:00.20#ibcon#read 6, iclass 5, count 0 2006.260.07:42:00.20#ibcon#end of sib2, iclass 5, count 0 2006.260.07:42:00.20#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:42:00.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:42:00.20#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:42:00.20#ibcon#*before write, iclass 5, count 0 2006.260.07:42:00.20#ibcon#enter sib2, iclass 5, count 0 2006.260.07:42:00.20#ibcon#flushed, iclass 5, count 0 2006.260.07:42:00.20#ibcon#about to write, iclass 5, count 0 2006.260.07:42:00.20#ibcon#wrote, iclass 5, count 0 2006.260.07:42:00.20#ibcon#about to read 3, iclass 5, count 0 2006.260.07:42:00.24#ibcon#read 3, iclass 5, count 0 2006.260.07:42:00.24#ibcon#about to read 4, iclass 5, count 0 2006.260.07:42:00.24#ibcon#read 4, iclass 5, count 0 2006.260.07:42:00.24#ibcon#about to read 5, iclass 5, count 0 2006.260.07:42:00.24#ibcon#read 5, iclass 5, count 0 2006.260.07:42:00.24#ibcon#about to read 6, iclass 5, count 0 2006.260.07:42:00.24#ibcon#read 6, iclass 5, count 0 2006.260.07:42:00.24#ibcon#end of sib2, iclass 5, count 0 2006.260.07:42:00.24#ibcon#*after write, iclass 5, count 0 2006.260.07:42:00.24#ibcon#*before return 0, iclass 5, count 0 2006.260.07:42:00.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:00.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:00.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:42:00.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:42:00.24$vc4f8/va=3,8 2006.260.07:42:00.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.07:42:00.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.07:42:00.24#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:00.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:00.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:00.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:00.30#ibcon#enter wrdev, iclass 7, count 2 2006.260.07:42:00.30#ibcon#first serial, iclass 7, count 2 2006.260.07:42:00.30#ibcon#enter sib2, iclass 7, count 2 2006.260.07:42:00.30#ibcon#flushed, iclass 7, count 2 2006.260.07:42:00.30#ibcon#about to write, iclass 7, count 2 2006.260.07:42:00.30#ibcon#wrote, iclass 7, count 2 2006.260.07:42:00.30#ibcon#about to read 3, iclass 7, count 2 2006.260.07:42:00.32#ibcon#read 3, iclass 7, count 2 2006.260.07:42:00.32#ibcon#about to read 4, iclass 7, count 2 2006.260.07:42:00.32#ibcon#read 4, iclass 7, count 2 2006.260.07:42:00.32#ibcon#about to read 5, iclass 7, count 2 2006.260.07:42:00.32#ibcon#read 5, iclass 7, count 2 2006.260.07:42:00.32#ibcon#about to read 6, iclass 7, count 2 2006.260.07:42:00.32#ibcon#read 6, iclass 7, count 2 2006.260.07:42:00.32#ibcon#end of sib2, iclass 7, count 2 2006.260.07:42:00.32#ibcon#*mode == 0, iclass 7, count 2 2006.260.07:42:00.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.07:42:00.32#ibcon#[25=AT03-08\r\n] 2006.260.07:42:00.32#ibcon#*before write, iclass 7, count 2 2006.260.07:42:00.32#ibcon#enter sib2, iclass 7, count 2 2006.260.07:42:00.32#ibcon#flushed, iclass 7, count 2 2006.260.07:42:00.32#ibcon#about to write, iclass 7, count 2 2006.260.07:42:00.32#ibcon#wrote, iclass 7, count 2 2006.260.07:42:00.32#ibcon#about to read 3, iclass 7, count 2 2006.260.07:42:00.35#ibcon#read 3, iclass 7, count 2 2006.260.07:42:00.35#ibcon#about to read 4, iclass 7, count 2 2006.260.07:42:00.35#ibcon#read 4, iclass 7, count 2 2006.260.07:42:00.35#ibcon#about to read 5, iclass 7, count 2 2006.260.07:42:00.35#ibcon#read 5, iclass 7, count 2 2006.260.07:42:00.35#ibcon#about to read 6, iclass 7, count 2 2006.260.07:42:00.35#ibcon#read 6, iclass 7, count 2 2006.260.07:42:00.35#ibcon#end of sib2, iclass 7, count 2 2006.260.07:42:00.35#ibcon#*after write, iclass 7, count 2 2006.260.07:42:00.35#ibcon#*before return 0, iclass 7, count 2 2006.260.07:42:00.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:00.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:00.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.07:42:00.35#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:00.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:00.46#abcon#<5=/03 3.4 7.1 23.06 871010.4\r\n> 2006.260.07:42:00.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:00.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:00.47#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:42:00.47#ibcon#first serial, iclass 7, count 0 2006.260.07:42:00.47#ibcon#enter sib2, iclass 7, count 0 2006.260.07:42:00.47#ibcon#flushed, iclass 7, count 0 2006.260.07:42:00.47#ibcon#about to write, iclass 7, count 0 2006.260.07:42:00.47#ibcon#wrote, iclass 7, count 0 2006.260.07:42:00.47#ibcon#about to read 3, iclass 7, count 0 2006.260.07:42:00.48#abcon#{5=INTERFACE CLEAR} 2006.260.07:42:00.49#ibcon#read 3, iclass 7, count 0 2006.260.07:42:00.49#ibcon#about to read 4, iclass 7, count 0 2006.260.07:42:00.49#ibcon#read 4, iclass 7, count 0 2006.260.07:42:00.49#ibcon#about to read 5, iclass 7, count 0 2006.260.07:42:00.49#ibcon#read 5, iclass 7, count 0 2006.260.07:42:00.49#ibcon#about to read 6, iclass 7, count 0 2006.260.07:42:00.49#ibcon#read 6, iclass 7, count 0 2006.260.07:42:00.49#ibcon#end of sib2, iclass 7, count 0 2006.260.07:42:00.49#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:42:00.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:42:00.49#ibcon#[25=USB\r\n] 2006.260.07:42:00.49#ibcon#*before write, iclass 7, count 0 2006.260.07:42:00.49#ibcon#enter sib2, iclass 7, count 0 2006.260.07:42:00.49#ibcon#flushed, iclass 7, count 0 2006.260.07:42:00.49#ibcon#about to write, iclass 7, count 0 2006.260.07:42:00.49#ibcon#wrote, iclass 7, count 0 2006.260.07:42:00.49#ibcon#about to read 3, iclass 7, count 0 2006.260.07:42:00.52#ibcon#read 3, iclass 7, count 0 2006.260.07:42:00.52#ibcon#about to read 4, iclass 7, count 0 2006.260.07:42:00.52#ibcon#read 4, iclass 7, count 0 2006.260.07:42:00.52#ibcon#about to read 5, iclass 7, count 0 2006.260.07:42:00.52#ibcon#read 5, iclass 7, count 0 2006.260.07:42:00.52#ibcon#about to read 6, iclass 7, count 0 2006.260.07:42:00.52#ibcon#read 6, iclass 7, count 0 2006.260.07:42:00.52#ibcon#end of sib2, iclass 7, count 0 2006.260.07:42:00.52#ibcon#*after write, iclass 7, count 0 2006.260.07:42:00.52#ibcon#*before return 0, iclass 7, count 0 2006.260.07:42:00.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:00.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:00.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:42:00.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:42:00.52$vc4f8/valo=4,832.99 2006.260.07:42:00.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:42:00.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:42:00.52#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:00.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:42:00.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:42:00.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:42:00.52#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:42:00.52#ibcon#first serial, iclass 14, count 0 2006.260.07:42:00.52#ibcon#enter sib2, iclass 14, count 0 2006.260.07:42:00.52#ibcon#flushed, iclass 14, count 0 2006.260.07:42:00.52#ibcon#about to write, iclass 14, count 0 2006.260.07:42:00.52#ibcon#wrote, iclass 14, count 0 2006.260.07:42:00.52#ibcon#about to read 3, iclass 14, count 0 2006.260.07:42:00.54#ibcon#read 3, iclass 14, count 0 2006.260.07:42:00.54#ibcon#about to read 4, iclass 14, count 0 2006.260.07:42:00.54#ibcon#read 4, iclass 14, count 0 2006.260.07:42:00.54#ibcon#about to read 5, iclass 14, count 0 2006.260.07:42:00.54#ibcon#read 5, iclass 14, count 0 2006.260.07:42:00.54#ibcon#about to read 6, iclass 14, count 0 2006.260.07:42:00.54#ibcon#read 6, iclass 14, count 0 2006.260.07:42:00.54#ibcon#end of sib2, iclass 14, count 0 2006.260.07:42:00.54#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:42:00.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:42:00.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:42:00.54#ibcon#*before write, iclass 14, count 0 2006.260.07:42:00.54#ibcon#enter sib2, iclass 14, count 0 2006.260.07:42:00.54#ibcon#flushed, iclass 14, count 0 2006.260.07:42:00.54#ibcon#about to write, iclass 14, count 0 2006.260.07:42:00.54#ibcon#wrote, iclass 14, count 0 2006.260.07:42:00.54#ibcon#about to read 3, iclass 14, count 0 2006.260.07:42:00.54#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:42:00.58#ibcon#read 3, iclass 14, count 0 2006.260.07:42:00.58#ibcon#about to read 4, iclass 14, count 0 2006.260.07:42:00.58#ibcon#read 4, iclass 14, count 0 2006.260.07:42:00.58#ibcon#about to read 5, iclass 14, count 0 2006.260.07:42:00.58#ibcon#read 5, iclass 14, count 0 2006.260.07:42:00.58#ibcon#about to read 6, iclass 14, count 0 2006.260.07:42:00.58#ibcon#read 6, iclass 14, count 0 2006.260.07:42:00.58#ibcon#end of sib2, iclass 14, count 0 2006.260.07:42:00.58#ibcon#*after write, iclass 14, count 0 2006.260.07:42:00.58#ibcon#*before return 0, iclass 14, count 0 2006.260.07:42:00.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:42:00.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:42:00.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:42:00.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:42:00.58$vc4f8/va=4,7 2006.260.07:42:00.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:42:00.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:42:00.58#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:00.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:00.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:00.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:00.64#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:42:00.64#ibcon#first serial, iclass 17, count 2 2006.260.07:42:00.64#ibcon#enter sib2, iclass 17, count 2 2006.260.07:42:00.64#ibcon#flushed, iclass 17, count 2 2006.260.07:42:00.64#ibcon#about to write, iclass 17, count 2 2006.260.07:42:00.64#ibcon#wrote, iclass 17, count 2 2006.260.07:42:00.64#ibcon#about to read 3, iclass 17, count 2 2006.260.07:42:00.66#ibcon#read 3, iclass 17, count 2 2006.260.07:42:00.66#ibcon#about to read 4, iclass 17, count 2 2006.260.07:42:00.66#ibcon#read 4, iclass 17, count 2 2006.260.07:42:00.66#ibcon#about to read 5, iclass 17, count 2 2006.260.07:42:00.66#ibcon#read 5, iclass 17, count 2 2006.260.07:42:00.66#ibcon#about to read 6, iclass 17, count 2 2006.260.07:42:00.66#ibcon#read 6, iclass 17, count 2 2006.260.07:42:00.66#ibcon#end of sib2, iclass 17, count 2 2006.260.07:42:00.66#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:42:00.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:42:00.66#ibcon#[25=AT04-07\r\n] 2006.260.07:42:00.66#ibcon#*before write, iclass 17, count 2 2006.260.07:42:00.66#ibcon#enter sib2, iclass 17, count 2 2006.260.07:42:00.66#ibcon#flushed, iclass 17, count 2 2006.260.07:42:00.66#ibcon#about to write, iclass 17, count 2 2006.260.07:42:00.66#ibcon#wrote, iclass 17, count 2 2006.260.07:42:00.66#ibcon#about to read 3, iclass 17, count 2 2006.260.07:42:00.69#ibcon#read 3, iclass 17, count 2 2006.260.07:42:00.69#ibcon#about to read 4, iclass 17, count 2 2006.260.07:42:00.69#ibcon#read 4, iclass 17, count 2 2006.260.07:42:00.69#ibcon#about to read 5, iclass 17, count 2 2006.260.07:42:00.69#ibcon#read 5, iclass 17, count 2 2006.260.07:42:00.69#ibcon#about to read 6, iclass 17, count 2 2006.260.07:42:00.69#ibcon#read 6, iclass 17, count 2 2006.260.07:42:00.69#ibcon#end of sib2, iclass 17, count 2 2006.260.07:42:00.69#ibcon#*after write, iclass 17, count 2 2006.260.07:42:00.69#ibcon#*before return 0, iclass 17, count 2 2006.260.07:42:00.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:00.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:00.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:42:00.69#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:00.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:00.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:00.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:00.81#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:42:00.81#ibcon#first serial, iclass 17, count 0 2006.260.07:42:00.81#ibcon#enter sib2, iclass 17, count 0 2006.260.07:42:00.81#ibcon#flushed, iclass 17, count 0 2006.260.07:42:00.81#ibcon#about to write, iclass 17, count 0 2006.260.07:42:00.81#ibcon#wrote, iclass 17, count 0 2006.260.07:42:00.81#ibcon#about to read 3, iclass 17, count 0 2006.260.07:42:00.83#ibcon#read 3, iclass 17, count 0 2006.260.07:42:00.83#ibcon#about to read 4, iclass 17, count 0 2006.260.07:42:00.83#ibcon#read 4, iclass 17, count 0 2006.260.07:42:00.83#ibcon#about to read 5, iclass 17, count 0 2006.260.07:42:00.83#ibcon#read 5, iclass 17, count 0 2006.260.07:42:00.83#ibcon#about to read 6, iclass 17, count 0 2006.260.07:42:00.83#ibcon#read 6, iclass 17, count 0 2006.260.07:42:00.83#ibcon#end of sib2, iclass 17, count 0 2006.260.07:42:00.83#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:42:00.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:42:00.83#ibcon#[25=USB\r\n] 2006.260.07:42:00.83#ibcon#*before write, iclass 17, count 0 2006.260.07:42:00.83#ibcon#enter sib2, iclass 17, count 0 2006.260.07:42:00.83#ibcon#flushed, iclass 17, count 0 2006.260.07:42:00.83#ibcon#about to write, iclass 17, count 0 2006.260.07:42:00.83#ibcon#wrote, iclass 17, count 0 2006.260.07:42:00.83#ibcon#about to read 3, iclass 17, count 0 2006.260.07:42:00.86#ibcon#read 3, iclass 17, count 0 2006.260.07:42:00.86#ibcon#about to read 4, iclass 17, count 0 2006.260.07:42:00.86#ibcon#read 4, iclass 17, count 0 2006.260.07:42:00.86#ibcon#about to read 5, iclass 17, count 0 2006.260.07:42:00.86#ibcon#read 5, iclass 17, count 0 2006.260.07:42:00.86#ibcon#about to read 6, iclass 17, count 0 2006.260.07:42:00.86#ibcon#read 6, iclass 17, count 0 2006.260.07:42:00.86#ibcon#end of sib2, iclass 17, count 0 2006.260.07:42:00.86#ibcon#*after write, iclass 17, count 0 2006.260.07:42:00.86#ibcon#*before return 0, iclass 17, count 0 2006.260.07:42:00.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:00.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:00.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:42:00.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:42:00.86$vc4f8/valo=5,652.99 2006.260.07:42:00.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:42:00.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:42:00.86#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:00.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:00.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:00.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:00.86#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:42:00.86#ibcon#first serial, iclass 19, count 0 2006.260.07:42:00.86#ibcon#enter sib2, iclass 19, count 0 2006.260.07:42:00.86#ibcon#flushed, iclass 19, count 0 2006.260.07:42:00.86#ibcon#about to write, iclass 19, count 0 2006.260.07:42:00.86#ibcon#wrote, iclass 19, count 0 2006.260.07:42:00.86#ibcon#about to read 3, iclass 19, count 0 2006.260.07:42:00.88#ibcon#read 3, iclass 19, count 0 2006.260.07:42:00.88#ibcon#about to read 4, iclass 19, count 0 2006.260.07:42:00.88#ibcon#read 4, iclass 19, count 0 2006.260.07:42:00.88#ibcon#about to read 5, iclass 19, count 0 2006.260.07:42:00.88#ibcon#read 5, iclass 19, count 0 2006.260.07:42:00.88#ibcon#about to read 6, iclass 19, count 0 2006.260.07:42:00.88#ibcon#read 6, iclass 19, count 0 2006.260.07:42:00.88#ibcon#end of sib2, iclass 19, count 0 2006.260.07:42:00.88#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:42:00.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:42:00.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:42:00.88#ibcon#*before write, iclass 19, count 0 2006.260.07:42:00.88#ibcon#enter sib2, iclass 19, count 0 2006.260.07:42:00.88#ibcon#flushed, iclass 19, count 0 2006.260.07:42:00.88#ibcon#about to write, iclass 19, count 0 2006.260.07:42:00.88#ibcon#wrote, iclass 19, count 0 2006.260.07:42:00.88#ibcon#about to read 3, iclass 19, count 0 2006.260.07:42:00.92#ibcon#read 3, iclass 19, count 0 2006.260.07:42:00.92#ibcon#about to read 4, iclass 19, count 0 2006.260.07:42:00.92#ibcon#read 4, iclass 19, count 0 2006.260.07:42:00.92#ibcon#about to read 5, iclass 19, count 0 2006.260.07:42:00.92#ibcon#read 5, iclass 19, count 0 2006.260.07:42:00.92#ibcon#about to read 6, iclass 19, count 0 2006.260.07:42:00.92#ibcon#read 6, iclass 19, count 0 2006.260.07:42:00.92#ibcon#end of sib2, iclass 19, count 0 2006.260.07:42:00.92#ibcon#*after write, iclass 19, count 0 2006.260.07:42:00.92#ibcon#*before return 0, iclass 19, count 0 2006.260.07:42:00.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:00.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:00.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:42:00.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:42:00.92$vc4f8/va=5,7 2006.260.07:42:00.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:42:00.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:42:00.92#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:00.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:00.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:00.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:00.98#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:42:00.98#ibcon#first serial, iclass 21, count 2 2006.260.07:42:00.98#ibcon#enter sib2, iclass 21, count 2 2006.260.07:42:00.98#ibcon#flushed, iclass 21, count 2 2006.260.07:42:00.98#ibcon#about to write, iclass 21, count 2 2006.260.07:42:00.98#ibcon#wrote, iclass 21, count 2 2006.260.07:42:00.98#ibcon#about to read 3, iclass 21, count 2 2006.260.07:42:01.00#ibcon#read 3, iclass 21, count 2 2006.260.07:42:01.00#ibcon#about to read 4, iclass 21, count 2 2006.260.07:42:01.00#ibcon#read 4, iclass 21, count 2 2006.260.07:42:01.00#ibcon#about to read 5, iclass 21, count 2 2006.260.07:42:01.00#ibcon#read 5, iclass 21, count 2 2006.260.07:42:01.00#ibcon#about to read 6, iclass 21, count 2 2006.260.07:42:01.00#ibcon#read 6, iclass 21, count 2 2006.260.07:42:01.00#ibcon#end of sib2, iclass 21, count 2 2006.260.07:42:01.00#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:42:01.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:42:01.00#ibcon#[25=AT05-07\r\n] 2006.260.07:42:01.00#ibcon#*before write, iclass 21, count 2 2006.260.07:42:01.00#ibcon#enter sib2, iclass 21, count 2 2006.260.07:42:01.00#ibcon#flushed, iclass 21, count 2 2006.260.07:42:01.00#ibcon#about to write, iclass 21, count 2 2006.260.07:42:01.00#ibcon#wrote, iclass 21, count 2 2006.260.07:42:01.00#ibcon#about to read 3, iclass 21, count 2 2006.260.07:42:01.03#ibcon#read 3, iclass 21, count 2 2006.260.07:42:01.03#ibcon#about to read 4, iclass 21, count 2 2006.260.07:42:01.03#ibcon#read 4, iclass 21, count 2 2006.260.07:42:01.03#ibcon#about to read 5, iclass 21, count 2 2006.260.07:42:01.03#ibcon#read 5, iclass 21, count 2 2006.260.07:42:01.03#ibcon#about to read 6, iclass 21, count 2 2006.260.07:42:01.03#ibcon#read 6, iclass 21, count 2 2006.260.07:42:01.03#ibcon#end of sib2, iclass 21, count 2 2006.260.07:42:01.03#ibcon#*after write, iclass 21, count 2 2006.260.07:42:01.03#ibcon#*before return 0, iclass 21, count 2 2006.260.07:42:01.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:01.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:01.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:42:01.03#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:01.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:01.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:01.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:01.15#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:42:01.15#ibcon#first serial, iclass 21, count 0 2006.260.07:42:01.15#ibcon#enter sib2, iclass 21, count 0 2006.260.07:42:01.15#ibcon#flushed, iclass 21, count 0 2006.260.07:42:01.15#ibcon#about to write, iclass 21, count 0 2006.260.07:42:01.15#ibcon#wrote, iclass 21, count 0 2006.260.07:42:01.15#ibcon#about to read 3, iclass 21, count 0 2006.260.07:42:01.17#ibcon#read 3, iclass 21, count 0 2006.260.07:42:01.17#ibcon#about to read 4, iclass 21, count 0 2006.260.07:42:01.17#ibcon#read 4, iclass 21, count 0 2006.260.07:42:01.17#ibcon#about to read 5, iclass 21, count 0 2006.260.07:42:01.17#ibcon#read 5, iclass 21, count 0 2006.260.07:42:01.17#ibcon#about to read 6, iclass 21, count 0 2006.260.07:42:01.17#ibcon#read 6, iclass 21, count 0 2006.260.07:42:01.17#ibcon#end of sib2, iclass 21, count 0 2006.260.07:42:01.17#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:42:01.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:42:01.17#ibcon#[25=USB\r\n] 2006.260.07:42:01.17#ibcon#*before write, iclass 21, count 0 2006.260.07:42:01.17#ibcon#enter sib2, iclass 21, count 0 2006.260.07:42:01.17#ibcon#flushed, iclass 21, count 0 2006.260.07:42:01.17#ibcon#about to write, iclass 21, count 0 2006.260.07:42:01.17#ibcon#wrote, iclass 21, count 0 2006.260.07:42:01.17#ibcon#about to read 3, iclass 21, count 0 2006.260.07:42:01.20#ibcon#read 3, iclass 21, count 0 2006.260.07:42:01.20#ibcon#about to read 4, iclass 21, count 0 2006.260.07:42:01.20#ibcon#read 4, iclass 21, count 0 2006.260.07:42:01.20#ibcon#about to read 5, iclass 21, count 0 2006.260.07:42:01.20#ibcon#read 5, iclass 21, count 0 2006.260.07:42:01.20#ibcon#about to read 6, iclass 21, count 0 2006.260.07:42:01.20#ibcon#read 6, iclass 21, count 0 2006.260.07:42:01.20#ibcon#end of sib2, iclass 21, count 0 2006.260.07:42:01.20#ibcon#*after write, iclass 21, count 0 2006.260.07:42:01.20#ibcon#*before return 0, iclass 21, count 0 2006.260.07:42:01.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:01.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:01.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:42:01.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:42:01.20$vc4f8/valo=6,772.99 2006.260.07:42:01.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:42:01.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:42:01.20#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:01.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:01.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:01.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:01.20#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:42:01.20#ibcon#first serial, iclass 23, count 0 2006.260.07:42:01.20#ibcon#enter sib2, iclass 23, count 0 2006.260.07:42:01.20#ibcon#flushed, iclass 23, count 0 2006.260.07:42:01.20#ibcon#about to write, iclass 23, count 0 2006.260.07:42:01.20#ibcon#wrote, iclass 23, count 0 2006.260.07:42:01.20#ibcon#about to read 3, iclass 23, count 0 2006.260.07:42:01.22#ibcon#read 3, iclass 23, count 0 2006.260.07:42:01.22#ibcon#about to read 4, iclass 23, count 0 2006.260.07:42:01.22#ibcon#read 4, iclass 23, count 0 2006.260.07:42:01.22#ibcon#about to read 5, iclass 23, count 0 2006.260.07:42:01.22#ibcon#read 5, iclass 23, count 0 2006.260.07:42:01.22#ibcon#about to read 6, iclass 23, count 0 2006.260.07:42:01.22#ibcon#read 6, iclass 23, count 0 2006.260.07:42:01.22#ibcon#end of sib2, iclass 23, count 0 2006.260.07:42:01.22#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:42:01.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:42:01.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:42:01.22#ibcon#*before write, iclass 23, count 0 2006.260.07:42:01.22#ibcon#enter sib2, iclass 23, count 0 2006.260.07:42:01.22#ibcon#flushed, iclass 23, count 0 2006.260.07:42:01.22#ibcon#about to write, iclass 23, count 0 2006.260.07:42:01.22#ibcon#wrote, iclass 23, count 0 2006.260.07:42:01.22#ibcon#about to read 3, iclass 23, count 0 2006.260.07:42:01.26#ibcon#read 3, iclass 23, count 0 2006.260.07:42:01.26#ibcon#about to read 4, iclass 23, count 0 2006.260.07:42:01.26#ibcon#read 4, iclass 23, count 0 2006.260.07:42:01.26#ibcon#about to read 5, iclass 23, count 0 2006.260.07:42:01.26#ibcon#read 5, iclass 23, count 0 2006.260.07:42:01.26#ibcon#about to read 6, iclass 23, count 0 2006.260.07:42:01.26#ibcon#read 6, iclass 23, count 0 2006.260.07:42:01.26#ibcon#end of sib2, iclass 23, count 0 2006.260.07:42:01.26#ibcon#*after write, iclass 23, count 0 2006.260.07:42:01.26#ibcon#*before return 0, iclass 23, count 0 2006.260.07:42:01.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:01.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:01.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:42:01.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:42:01.26$vc4f8/va=6,6 2006.260.07:42:01.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:42:01.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:42:01.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:01.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:01.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:01.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:01.32#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:42:01.32#ibcon#first serial, iclass 25, count 2 2006.260.07:42:01.32#ibcon#enter sib2, iclass 25, count 2 2006.260.07:42:01.32#ibcon#flushed, iclass 25, count 2 2006.260.07:42:01.32#ibcon#about to write, iclass 25, count 2 2006.260.07:42:01.32#ibcon#wrote, iclass 25, count 2 2006.260.07:42:01.32#ibcon#about to read 3, iclass 25, count 2 2006.260.07:42:01.34#ibcon#read 3, iclass 25, count 2 2006.260.07:42:01.34#ibcon#about to read 4, iclass 25, count 2 2006.260.07:42:01.34#ibcon#read 4, iclass 25, count 2 2006.260.07:42:01.34#ibcon#about to read 5, iclass 25, count 2 2006.260.07:42:01.34#ibcon#read 5, iclass 25, count 2 2006.260.07:42:01.34#ibcon#about to read 6, iclass 25, count 2 2006.260.07:42:01.34#ibcon#read 6, iclass 25, count 2 2006.260.07:42:01.34#ibcon#end of sib2, iclass 25, count 2 2006.260.07:42:01.34#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:42:01.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:42:01.34#ibcon#[25=AT06-06\r\n] 2006.260.07:42:01.34#ibcon#*before write, iclass 25, count 2 2006.260.07:42:01.34#ibcon#enter sib2, iclass 25, count 2 2006.260.07:42:01.34#ibcon#flushed, iclass 25, count 2 2006.260.07:42:01.34#ibcon#about to write, iclass 25, count 2 2006.260.07:42:01.34#ibcon#wrote, iclass 25, count 2 2006.260.07:42:01.34#ibcon#about to read 3, iclass 25, count 2 2006.260.07:42:01.37#ibcon#read 3, iclass 25, count 2 2006.260.07:42:01.37#ibcon#about to read 4, iclass 25, count 2 2006.260.07:42:01.37#ibcon#read 4, iclass 25, count 2 2006.260.07:42:01.37#ibcon#about to read 5, iclass 25, count 2 2006.260.07:42:01.37#ibcon#read 5, iclass 25, count 2 2006.260.07:42:01.37#ibcon#about to read 6, iclass 25, count 2 2006.260.07:42:01.37#ibcon#read 6, iclass 25, count 2 2006.260.07:42:01.37#ibcon#end of sib2, iclass 25, count 2 2006.260.07:42:01.37#ibcon#*after write, iclass 25, count 2 2006.260.07:42:01.37#ibcon#*before return 0, iclass 25, count 2 2006.260.07:42:01.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:01.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:01.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:42:01.37#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:01.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:42:01.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:42:01.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:42:01.50#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:42:01.50#ibcon#first serial, iclass 25, count 0 2006.260.07:42:01.50#ibcon#enter sib2, iclass 25, count 0 2006.260.07:42:01.50#ibcon#flushed, iclass 25, count 0 2006.260.07:42:01.50#ibcon#about to write, iclass 25, count 0 2006.260.07:42:01.50#ibcon#wrote, iclass 25, count 0 2006.260.07:42:01.50#ibcon#about to read 3, iclass 25, count 0 2006.260.07:42:01.52#ibcon#read 3, iclass 25, count 0 2006.260.07:42:01.52#ibcon#about to read 4, iclass 25, count 0 2006.260.07:42:01.52#ibcon#read 4, iclass 25, count 0 2006.260.07:42:01.52#ibcon#about to read 5, iclass 25, count 0 2006.260.07:42:01.52#ibcon#read 5, iclass 25, count 0 2006.260.07:42:01.52#ibcon#about to read 6, iclass 25, count 0 2006.260.07:42:01.52#ibcon#read 6, iclass 25, count 0 2006.260.07:42:01.52#ibcon#end of sib2, iclass 25, count 0 2006.260.07:42:01.52#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:42:01.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:42:01.52#ibcon#[25=USB\r\n] 2006.260.07:42:01.52#ibcon#*before write, iclass 25, count 0 2006.260.07:42:01.52#ibcon#enter sib2, iclass 25, count 0 2006.260.07:42:01.52#ibcon#flushed, iclass 25, count 0 2006.260.07:42:01.52#ibcon#about to write, iclass 25, count 0 2006.260.07:42:01.52#ibcon#wrote, iclass 25, count 0 2006.260.07:42:01.52#ibcon#about to read 3, iclass 25, count 0 2006.260.07:42:01.55#ibcon#read 3, iclass 25, count 0 2006.260.07:42:01.55#ibcon#about to read 4, iclass 25, count 0 2006.260.07:42:01.55#ibcon#read 4, iclass 25, count 0 2006.260.07:42:01.55#ibcon#about to read 5, iclass 25, count 0 2006.260.07:42:01.55#ibcon#read 5, iclass 25, count 0 2006.260.07:42:01.55#ibcon#about to read 6, iclass 25, count 0 2006.260.07:42:01.55#ibcon#read 6, iclass 25, count 0 2006.260.07:42:01.55#ibcon#end of sib2, iclass 25, count 0 2006.260.07:42:01.55#ibcon#*after write, iclass 25, count 0 2006.260.07:42:01.55#ibcon#*before return 0, iclass 25, count 0 2006.260.07:42:01.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:42:01.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:42:01.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:42:01.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:42:01.55$vc4f8/valo=7,832.99 2006.260.07:42:01.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:42:01.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:42:01.55#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:01.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:42:01.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:42:01.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:42:01.55#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:42:01.55#ibcon#first serial, iclass 27, count 0 2006.260.07:42:01.55#ibcon#enter sib2, iclass 27, count 0 2006.260.07:42:01.55#ibcon#flushed, iclass 27, count 0 2006.260.07:42:01.55#ibcon#about to write, iclass 27, count 0 2006.260.07:42:01.55#ibcon#wrote, iclass 27, count 0 2006.260.07:42:01.55#ibcon#about to read 3, iclass 27, count 0 2006.260.07:42:01.57#ibcon#read 3, iclass 27, count 0 2006.260.07:42:01.57#ibcon#about to read 4, iclass 27, count 0 2006.260.07:42:01.57#ibcon#read 4, iclass 27, count 0 2006.260.07:42:01.57#ibcon#about to read 5, iclass 27, count 0 2006.260.07:42:01.57#ibcon#read 5, iclass 27, count 0 2006.260.07:42:01.57#ibcon#about to read 6, iclass 27, count 0 2006.260.07:42:01.57#ibcon#read 6, iclass 27, count 0 2006.260.07:42:01.57#ibcon#end of sib2, iclass 27, count 0 2006.260.07:42:01.57#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:42:01.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:42:01.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:42:01.57#ibcon#*before write, iclass 27, count 0 2006.260.07:42:01.57#ibcon#enter sib2, iclass 27, count 0 2006.260.07:42:01.57#ibcon#flushed, iclass 27, count 0 2006.260.07:42:01.57#ibcon#about to write, iclass 27, count 0 2006.260.07:42:01.57#ibcon#wrote, iclass 27, count 0 2006.260.07:42:01.57#ibcon#about to read 3, iclass 27, count 0 2006.260.07:42:01.61#ibcon#read 3, iclass 27, count 0 2006.260.07:42:01.61#ibcon#about to read 4, iclass 27, count 0 2006.260.07:42:01.61#ibcon#read 4, iclass 27, count 0 2006.260.07:42:01.61#ibcon#about to read 5, iclass 27, count 0 2006.260.07:42:01.61#ibcon#read 5, iclass 27, count 0 2006.260.07:42:01.61#ibcon#about to read 6, iclass 27, count 0 2006.260.07:42:01.61#ibcon#read 6, iclass 27, count 0 2006.260.07:42:01.61#ibcon#end of sib2, iclass 27, count 0 2006.260.07:42:01.61#ibcon#*after write, iclass 27, count 0 2006.260.07:42:01.61#ibcon#*before return 0, iclass 27, count 0 2006.260.07:42:01.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:42:01.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:42:01.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:42:01.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:42:01.61$vc4f8/va=7,6 2006.260.07:42:01.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:42:01.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:42:01.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:01.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:42:01.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:42:01.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:42:01.67#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:42:01.67#ibcon#first serial, iclass 29, count 2 2006.260.07:42:01.67#ibcon#enter sib2, iclass 29, count 2 2006.260.07:42:01.67#ibcon#flushed, iclass 29, count 2 2006.260.07:42:01.67#ibcon#about to write, iclass 29, count 2 2006.260.07:42:01.67#ibcon#wrote, iclass 29, count 2 2006.260.07:42:01.67#ibcon#about to read 3, iclass 29, count 2 2006.260.07:42:01.69#ibcon#read 3, iclass 29, count 2 2006.260.07:42:01.69#ibcon#about to read 4, iclass 29, count 2 2006.260.07:42:01.69#ibcon#read 4, iclass 29, count 2 2006.260.07:42:01.69#ibcon#about to read 5, iclass 29, count 2 2006.260.07:42:01.69#ibcon#read 5, iclass 29, count 2 2006.260.07:42:01.69#ibcon#about to read 6, iclass 29, count 2 2006.260.07:42:01.69#ibcon#read 6, iclass 29, count 2 2006.260.07:42:01.69#ibcon#end of sib2, iclass 29, count 2 2006.260.07:42:01.69#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:42:01.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:42:01.69#ibcon#[25=AT07-06\r\n] 2006.260.07:42:01.69#ibcon#*before write, iclass 29, count 2 2006.260.07:42:01.69#ibcon#enter sib2, iclass 29, count 2 2006.260.07:42:01.69#ibcon#flushed, iclass 29, count 2 2006.260.07:42:01.69#ibcon#about to write, iclass 29, count 2 2006.260.07:42:01.69#ibcon#wrote, iclass 29, count 2 2006.260.07:42:01.69#ibcon#about to read 3, iclass 29, count 2 2006.260.07:42:01.72#ibcon#read 3, iclass 29, count 2 2006.260.07:42:01.72#ibcon#about to read 4, iclass 29, count 2 2006.260.07:42:01.72#ibcon#read 4, iclass 29, count 2 2006.260.07:42:01.72#ibcon#about to read 5, iclass 29, count 2 2006.260.07:42:01.72#ibcon#read 5, iclass 29, count 2 2006.260.07:42:01.72#ibcon#about to read 6, iclass 29, count 2 2006.260.07:42:01.72#ibcon#read 6, iclass 29, count 2 2006.260.07:42:01.72#ibcon#end of sib2, iclass 29, count 2 2006.260.07:42:01.72#ibcon#*after write, iclass 29, count 2 2006.260.07:42:01.72#ibcon#*before return 0, iclass 29, count 2 2006.260.07:42:01.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:42:01.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:42:01.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:42:01.72#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:01.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:42:01.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:42:01.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:42:01.84#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:42:01.84#ibcon#first serial, iclass 29, count 0 2006.260.07:42:01.84#ibcon#enter sib2, iclass 29, count 0 2006.260.07:42:01.84#ibcon#flushed, iclass 29, count 0 2006.260.07:42:01.84#ibcon#about to write, iclass 29, count 0 2006.260.07:42:01.84#ibcon#wrote, iclass 29, count 0 2006.260.07:42:01.84#ibcon#about to read 3, iclass 29, count 0 2006.260.07:42:01.86#ibcon#read 3, iclass 29, count 0 2006.260.07:42:01.86#ibcon#about to read 4, iclass 29, count 0 2006.260.07:42:01.86#ibcon#read 4, iclass 29, count 0 2006.260.07:42:01.86#ibcon#about to read 5, iclass 29, count 0 2006.260.07:42:01.86#ibcon#read 5, iclass 29, count 0 2006.260.07:42:01.86#ibcon#about to read 6, iclass 29, count 0 2006.260.07:42:01.86#ibcon#read 6, iclass 29, count 0 2006.260.07:42:01.86#ibcon#end of sib2, iclass 29, count 0 2006.260.07:42:01.86#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:42:01.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:42:01.86#ibcon#[25=USB\r\n] 2006.260.07:42:01.86#ibcon#*before write, iclass 29, count 0 2006.260.07:42:01.86#ibcon#enter sib2, iclass 29, count 0 2006.260.07:42:01.86#ibcon#flushed, iclass 29, count 0 2006.260.07:42:01.86#ibcon#about to write, iclass 29, count 0 2006.260.07:42:01.86#ibcon#wrote, iclass 29, count 0 2006.260.07:42:01.86#ibcon#about to read 3, iclass 29, count 0 2006.260.07:42:01.89#ibcon#read 3, iclass 29, count 0 2006.260.07:42:01.89#ibcon#about to read 4, iclass 29, count 0 2006.260.07:42:01.89#ibcon#read 4, iclass 29, count 0 2006.260.07:42:01.89#ibcon#about to read 5, iclass 29, count 0 2006.260.07:42:01.89#ibcon#read 5, iclass 29, count 0 2006.260.07:42:01.89#ibcon#about to read 6, iclass 29, count 0 2006.260.07:42:01.89#ibcon#read 6, iclass 29, count 0 2006.260.07:42:01.89#ibcon#end of sib2, iclass 29, count 0 2006.260.07:42:01.89#ibcon#*after write, iclass 29, count 0 2006.260.07:42:01.89#ibcon#*before return 0, iclass 29, count 0 2006.260.07:42:01.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:42:01.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:42:01.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:42:01.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:42:01.89$vc4f8/valo=8,852.99 2006.260.07:42:01.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:42:01.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:42:01.89#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:01.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:42:01.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:42:01.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:42:01.89#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:42:01.89#ibcon#first serial, iclass 31, count 0 2006.260.07:42:01.89#ibcon#enter sib2, iclass 31, count 0 2006.260.07:42:01.89#ibcon#flushed, iclass 31, count 0 2006.260.07:42:01.89#ibcon#about to write, iclass 31, count 0 2006.260.07:42:01.89#ibcon#wrote, iclass 31, count 0 2006.260.07:42:01.89#ibcon#about to read 3, iclass 31, count 0 2006.260.07:42:01.91#ibcon#read 3, iclass 31, count 0 2006.260.07:42:01.91#ibcon#about to read 4, iclass 31, count 0 2006.260.07:42:01.91#ibcon#read 4, iclass 31, count 0 2006.260.07:42:01.91#ibcon#about to read 5, iclass 31, count 0 2006.260.07:42:01.91#ibcon#read 5, iclass 31, count 0 2006.260.07:42:01.91#ibcon#about to read 6, iclass 31, count 0 2006.260.07:42:01.91#ibcon#read 6, iclass 31, count 0 2006.260.07:42:01.91#ibcon#end of sib2, iclass 31, count 0 2006.260.07:42:01.91#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:42:01.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:42:01.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:42:01.91#ibcon#*before write, iclass 31, count 0 2006.260.07:42:01.91#ibcon#enter sib2, iclass 31, count 0 2006.260.07:42:01.91#ibcon#flushed, iclass 31, count 0 2006.260.07:42:01.91#ibcon#about to write, iclass 31, count 0 2006.260.07:42:01.91#ibcon#wrote, iclass 31, count 0 2006.260.07:42:01.91#ibcon#about to read 3, iclass 31, count 0 2006.260.07:42:01.95#ibcon#read 3, iclass 31, count 0 2006.260.07:42:01.95#ibcon#about to read 4, iclass 31, count 0 2006.260.07:42:01.95#ibcon#read 4, iclass 31, count 0 2006.260.07:42:01.95#ibcon#about to read 5, iclass 31, count 0 2006.260.07:42:01.95#ibcon#read 5, iclass 31, count 0 2006.260.07:42:01.95#ibcon#about to read 6, iclass 31, count 0 2006.260.07:42:01.95#ibcon#read 6, iclass 31, count 0 2006.260.07:42:01.95#ibcon#end of sib2, iclass 31, count 0 2006.260.07:42:01.95#ibcon#*after write, iclass 31, count 0 2006.260.07:42:01.95#ibcon#*before return 0, iclass 31, count 0 2006.260.07:42:01.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:42:01.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:42:01.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:42:01.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:42:01.95$vc4f8/va=8,6 2006.260.07:42:01.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:42:01.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:42:01.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:01.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:42:02.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:42:02.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:42:02.01#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:42:02.01#ibcon#first serial, iclass 33, count 2 2006.260.07:42:02.01#ibcon#enter sib2, iclass 33, count 2 2006.260.07:42:02.01#ibcon#flushed, iclass 33, count 2 2006.260.07:42:02.01#ibcon#about to write, iclass 33, count 2 2006.260.07:42:02.01#ibcon#wrote, iclass 33, count 2 2006.260.07:42:02.01#ibcon#about to read 3, iclass 33, count 2 2006.260.07:42:02.03#ibcon#read 3, iclass 33, count 2 2006.260.07:42:02.03#ibcon#about to read 4, iclass 33, count 2 2006.260.07:42:02.03#ibcon#read 4, iclass 33, count 2 2006.260.07:42:02.03#ibcon#about to read 5, iclass 33, count 2 2006.260.07:42:02.03#ibcon#read 5, iclass 33, count 2 2006.260.07:42:02.03#ibcon#about to read 6, iclass 33, count 2 2006.260.07:42:02.03#ibcon#read 6, iclass 33, count 2 2006.260.07:42:02.03#ibcon#end of sib2, iclass 33, count 2 2006.260.07:42:02.03#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:42:02.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:42:02.03#ibcon#[25=AT08-06\r\n] 2006.260.07:42:02.03#ibcon#*before write, iclass 33, count 2 2006.260.07:42:02.03#ibcon#enter sib2, iclass 33, count 2 2006.260.07:42:02.03#ibcon#flushed, iclass 33, count 2 2006.260.07:42:02.03#ibcon#about to write, iclass 33, count 2 2006.260.07:42:02.03#ibcon#wrote, iclass 33, count 2 2006.260.07:42:02.03#ibcon#about to read 3, iclass 33, count 2 2006.260.07:42:02.06#ibcon#read 3, iclass 33, count 2 2006.260.07:42:02.06#ibcon#about to read 4, iclass 33, count 2 2006.260.07:42:02.06#ibcon#read 4, iclass 33, count 2 2006.260.07:42:02.06#ibcon#about to read 5, iclass 33, count 2 2006.260.07:42:02.06#ibcon#read 5, iclass 33, count 2 2006.260.07:42:02.06#ibcon#about to read 6, iclass 33, count 2 2006.260.07:42:02.06#ibcon#read 6, iclass 33, count 2 2006.260.07:42:02.06#ibcon#end of sib2, iclass 33, count 2 2006.260.07:42:02.06#ibcon#*after write, iclass 33, count 2 2006.260.07:42:02.06#ibcon#*before return 0, iclass 33, count 2 2006.260.07:42:02.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:42:02.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:42:02.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:42:02.06#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:02.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:42:02.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:42:02.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:42:02.18#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:42:02.18#ibcon#first serial, iclass 33, count 0 2006.260.07:42:02.18#ibcon#enter sib2, iclass 33, count 0 2006.260.07:42:02.18#ibcon#flushed, iclass 33, count 0 2006.260.07:42:02.18#ibcon#about to write, iclass 33, count 0 2006.260.07:42:02.18#ibcon#wrote, iclass 33, count 0 2006.260.07:42:02.18#ibcon#about to read 3, iclass 33, count 0 2006.260.07:42:02.20#ibcon#read 3, iclass 33, count 0 2006.260.07:42:02.20#ibcon#about to read 4, iclass 33, count 0 2006.260.07:42:02.20#ibcon#read 4, iclass 33, count 0 2006.260.07:42:02.20#ibcon#about to read 5, iclass 33, count 0 2006.260.07:42:02.20#ibcon#read 5, iclass 33, count 0 2006.260.07:42:02.20#ibcon#about to read 6, iclass 33, count 0 2006.260.07:42:02.20#ibcon#read 6, iclass 33, count 0 2006.260.07:42:02.20#ibcon#end of sib2, iclass 33, count 0 2006.260.07:42:02.20#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:42:02.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:42:02.20#ibcon#[25=USB\r\n] 2006.260.07:42:02.20#ibcon#*before write, iclass 33, count 0 2006.260.07:42:02.20#ibcon#enter sib2, iclass 33, count 0 2006.260.07:42:02.20#ibcon#flushed, iclass 33, count 0 2006.260.07:42:02.20#ibcon#about to write, iclass 33, count 0 2006.260.07:42:02.20#ibcon#wrote, iclass 33, count 0 2006.260.07:42:02.20#ibcon#about to read 3, iclass 33, count 0 2006.260.07:42:02.23#ibcon#read 3, iclass 33, count 0 2006.260.07:42:02.23#ibcon#about to read 4, iclass 33, count 0 2006.260.07:42:02.23#ibcon#read 4, iclass 33, count 0 2006.260.07:42:02.23#ibcon#about to read 5, iclass 33, count 0 2006.260.07:42:02.23#ibcon#read 5, iclass 33, count 0 2006.260.07:42:02.23#ibcon#about to read 6, iclass 33, count 0 2006.260.07:42:02.23#ibcon#read 6, iclass 33, count 0 2006.260.07:42:02.23#ibcon#end of sib2, iclass 33, count 0 2006.260.07:42:02.23#ibcon#*after write, iclass 33, count 0 2006.260.07:42:02.23#ibcon#*before return 0, iclass 33, count 0 2006.260.07:42:02.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:42:02.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:42:02.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:42:02.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:42:02.23$vc4f8/vblo=1,632.99 2006.260.07:42:02.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:42:02.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:42:02.23#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:02.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:42:02.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:42:02.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:42:02.23#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:42:02.23#ibcon#first serial, iclass 35, count 0 2006.260.07:42:02.23#ibcon#enter sib2, iclass 35, count 0 2006.260.07:42:02.23#ibcon#flushed, iclass 35, count 0 2006.260.07:42:02.23#ibcon#about to write, iclass 35, count 0 2006.260.07:42:02.23#ibcon#wrote, iclass 35, count 0 2006.260.07:42:02.23#ibcon#about to read 3, iclass 35, count 0 2006.260.07:42:02.25#ibcon#read 3, iclass 35, count 0 2006.260.07:42:02.25#ibcon#about to read 4, iclass 35, count 0 2006.260.07:42:02.25#ibcon#read 4, iclass 35, count 0 2006.260.07:42:02.25#ibcon#about to read 5, iclass 35, count 0 2006.260.07:42:02.25#ibcon#read 5, iclass 35, count 0 2006.260.07:42:02.25#ibcon#about to read 6, iclass 35, count 0 2006.260.07:42:02.25#ibcon#read 6, iclass 35, count 0 2006.260.07:42:02.25#ibcon#end of sib2, iclass 35, count 0 2006.260.07:42:02.25#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:42:02.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:42:02.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:42:02.25#ibcon#*before write, iclass 35, count 0 2006.260.07:42:02.25#ibcon#enter sib2, iclass 35, count 0 2006.260.07:42:02.25#ibcon#flushed, iclass 35, count 0 2006.260.07:42:02.25#ibcon#about to write, iclass 35, count 0 2006.260.07:42:02.25#ibcon#wrote, iclass 35, count 0 2006.260.07:42:02.25#ibcon#about to read 3, iclass 35, count 0 2006.260.07:42:02.29#ibcon#read 3, iclass 35, count 0 2006.260.07:42:02.29#ibcon#about to read 4, iclass 35, count 0 2006.260.07:42:02.29#ibcon#read 4, iclass 35, count 0 2006.260.07:42:02.29#ibcon#about to read 5, iclass 35, count 0 2006.260.07:42:02.29#ibcon#read 5, iclass 35, count 0 2006.260.07:42:02.29#ibcon#about to read 6, iclass 35, count 0 2006.260.07:42:02.29#ibcon#read 6, iclass 35, count 0 2006.260.07:42:02.29#ibcon#end of sib2, iclass 35, count 0 2006.260.07:42:02.29#ibcon#*after write, iclass 35, count 0 2006.260.07:42:02.29#ibcon#*before return 0, iclass 35, count 0 2006.260.07:42:02.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:42:02.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:42:02.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:42:02.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:42:02.29$vc4f8/vb=1,4 2006.260.07:42:02.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:42:02.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:42:02.29#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:02.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:42:02.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:42:02.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:42:02.29#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:42:02.29#ibcon#first serial, iclass 37, count 2 2006.260.07:42:02.29#ibcon#enter sib2, iclass 37, count 2 2006.260.07:42:02.29#ibcon#flushed, iclass 37, count 2 2006.260.07:42:02.29#ibcon#about to write, iclass 37, count 2 2006.260.07:42:02.29#ibcon#wrote, iclass 37, count 2 2006.260.07:42:02.29#ibcon#about to read 3, iclass 37, count 2 2006.260.07:42:02.31#ibcon#read 3, iclass 37, count 2 2006.260.07:42:02.31#ibcon#about to read 4, iclass 37, count 2 2006.260.07:42:02.31#ibcon#read 4, iclass 37, count 2 2006.260.07:42:02.31#ibcon#about to read 5, iclass 37, count 2 2006.260.07:42:02.31#ibcon#read 5, iclass 37, count 2 2006.260.07:42:02.31#ibcon#about to read 6, iclass 37, count 2 2006.260.07:42:02.31#ibcon#read 6, iclass 37, count 2 2006.260.07:42:02.31#ibcon#end of sib2, iclass 37, count 2 2006.260.07:42:02.31#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:42:02.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:42:02.31#ibcon#[27=AT01-04\r\n] 2006.260.07:42:02.31#ibcon#*before write, iclass 37, count 2 2006.260.07:42:02.31#ibcon#enter sib2, iclass 37, count 2 2006.260.07:42:02.31#ibcon#flushed, iclass 37, count 2 2006.260.07:42:02.31#ibcon#about to write, iclass 37, count 2 2006.260.07:42:02.31#ibcon#wrote, iclass 37, count 2 2006.260.07:42:02.31#ibcon#about to read 3, iclass 37, count 2 2006.260.07:42:02.34#ibcon#read 3, iclass 37, count 2 2006.260.07:42:02.34#ibcon#about to read 4, iclass 37, count 2 2006.260.07:42:02.34#ibcon#read 4, iclass 37, count 2 2006.260.07:42:02.34#ibcon#about to read 5, iclass 37, count 2 2006.260.07:42:02.34#ibcon#read 5, iclass 37, count 2 2006.260.07:42:02.34#ibcon#about to read 6, iclass 37, count 2 2006.260.07:42:02.34#ibcon#read 6, iclass 37, count 2 2006.260.07:42:02.34#ibcon#end of sib2, iclass 37, count 2 2006.260.07:42:02.34#ibcon#*after write, iclass 37, count 2 2006.260.07:42:02.34#ibcon#*before return 0, iclass 37, count 2 2006.260.07:42:02.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:42:02.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:42:02.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:42:02.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:02.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:42:02.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:42:02.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:42:02.46#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:42:02.46#ibcon#first serial, iclass 37, count 0 2006.260.07:42:02.46#ibcon#enter sib2, iclass 37, count 0 2006.260.07:42:02.46#ibcon#flushed, iclass 37, count 0 2006.260.07:42:02.46#ibcon#about to write, iclass 37, count 0 2006.260.07:42:02.46#ibcon#wrote, iclass 37, count 0 2006.260.07:42:02.46#ibcon#about to read 3, iclass 37, count 0 2006.260.07:42:02.48#ibcon#read 3, iclass 37, count 0 2006.260.07:42:02.48#ibcon#about to read 4, iclass 37, count 0 2006.260.07:42:02.48#ibcon#read 4, iclass 37, count 0 2006.260.07:42:02.48#ibcon#about to read 5, iclass 37, count 0 2006.260.07:42:02.48#ibcon#read 5, iclass 37, count 0 2006.260.07:42:02.48#ibcon#about to read 6, iclass 37, count 0 2006.260.07:42:02.48#ibcon#read 6, iclass 37, count 0 2006.260.07:42:02.48#ibcon#end of sib2, iclass 37, count 0 2006.260.07:42:02.48#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:42:02.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:42:02.48#ibcon#[27=USB\r\n] 2006.260.07:42:02.48#ibcon#*before write, iclass 37, count 0 2006.260.07:42:02.48#ibcon#enter sib2, iclass 37, count 0 2006.260.07:42:02.48#ibcon#flushed, iclass 37, count 0 2006.260.07:42:02.48#ibcon#about to write, iclass 37, count 0 2006.260.07:42:02.48#ibcon#wrote, iclass 37, count 0 2006.260.07:42:02.48#ibcon#about to read 3, iclass 37, count 0 2006.260.07:42:02.51#ibcon#read 3, iclass 37, count 0 2006.260.07:42:02.51#ibcon#about to read 4, iclass 37, count 0 2006.260.07:42:02.51#ibcon#read 4, iclass 37, count 0 2006.260.07:42:02.51#ibcon#about to read 5, iclass 37, count 0 2006.260.07:42:02.51#ibcon#read 5, iclass 37, count 0 2006.260.07:42:02.51#ibcon#about to read 6, iclass 37, count 0 2006.260.07:42:02.51#ibcon#read 6, iclass 37, count 0 2006.260.07:42:02.51#ibcon#end of sib2, iclass 37, count 0 2006.260.07:42:02.51#ibcon#*after write, iclass 37, count 0 2006.260.07:42:02.51#ibcon#*before return 0, iclass 37, count 0 2006.260.07:42:02.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:42:02.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:42:02.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:42:02.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:42:02.51$vc4f8/vblo=2,640.99 2006.260.07:42:02.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:42:02.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:42:02.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:02.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:42:02.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:42:02.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:42:02.51#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:42:02.51#ibcon#first serial, iclass 39, count 0 2006.260.07:42:02.51#ibcon#enter sib2, iclass 39, count 0 2006.260.07:42:02.51#ibcon#flushed, iclass 39, count 0 2006.260.07:42:02.51#ibcon#about to write, iclass 39, count 0 2006.260.07:42:02.51#ibcon#wrote, iclass 39, count 0 2006.260.07:42:02.51#ibcon#about to read 3, iclass 39, count 0 2006.260.07:42:02.53#ibcon#read 3, iclass 39, count 0 2006.260.07:42:02.53#ibcon#about to read 4, iclass 39, count 0 2006.260.07:42:02.53#ibcon#read 4, iclass 39, count 0 2006.260.07:42:02.53#ibcon#about to read 5, iclass 39, count 0 2006.260.07:42:02.53#ibcon#read 5, iclass 39, count 0 2006.260.07:42:02.53#ibcon#about to read 6, iclass 39, count 0 2006.260.07:42:02.53#ibcon#read 6, iclass 39, count 0 2006.260.07:42:02.53#ibcon#end of sib2, iclass 39, count 0 2006.260.07:42:02.53#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:42:02.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:42:02.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:42:02.53#ibcon#*before write, iclass 39, count 0 2006.260.07:42:02.53#ibcon#enter sib2, iclass 39, count 0 2006.260.07:42:02.53#ibcon#flushed, iclass 39, count 0 2006.260.07:42:02.53#ibcon#about to write, iclass 39, count 0 2006.260.07:42:02.53#ibcon#wrote, iclass 39, count 0 2006.260.07:42:02.53#ibcon#about to read 3, iclass 39, count 0 2006.260.07:42:02.57#ibcon#read 3, iclass 39, count 0 2006.260.07:42:02.57#ibcon#about to read 4, iclass 39, count 0 2006.260.07:42:02.57#ibcon#read 4, iclass 39, count 0 2006.260.07:42:02.57#ibcon#about to read 5, iclass 39, count 0 2006.260.07:42:02.57#ibcon#read 5, iclass 39, count 0 2006.260.07:42:02.57#ibcon#about to read 6, iclass 39, count 0 2006.260.07:42:02.57#ibcon#read 6, iclass 39, count 0 2006.260.07:42:02.57#ibcon#end of sib2, iclass 39, count 0 2006.260.07:42:02.57#ibcon#*after write, iclass 39, count 0 2006.260.07:42:02.57#ibcon#*before return 0, iclass 39, count 0 2006.260.07:42:02.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:42:02.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:42:02.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:42:02.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:42:02.57$vc4f8/vb=2,5 2006.260.07:42:02.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:42:02.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:42:02.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:02.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:02.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:02.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:02.63#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:42:02.63#ibcon#first serial, iclass 3, count 2 2006.260.07:42:02.63#ibcon#enter sib2, iclass 3, count 2 2006.260.07:42:02.63#ibcon#flushed, iclass 3, count 2 2006.260.07:42:02.63#ibcon#about to write, iclass 3, count 2 2006.260.07:42:02.63#ibcon#wrote, iclass 3, count 2 2006.260.07:42:02.63#ibcon#about to read 3, iclass 3, count 2 2006.260.07:42:02.65#ibcon#read 3, iclass 3, count 2 2006.260.07:42:02.65#ibcon#about to read 4, iclass 3, count 2 2006.260.07:42:02.65#ibcon#read 4, iclass 3, count 2 2006.260.07:42:02.65#ibcon#about to read 5, iclass 3, count 2 2006.260.07:42:02.65#ibcon#read 5, iclass 3, count 2 2006.260.07:42:02.65#ibcon#about to read 6, iclass 3, count 2 2006.260.07:42:02.65#ibcon#read 6, iclass 3, count 2 2006.260.07:42:02.65#ibcon#end of sib2, iclass 3, count 2 2006.260.07:42:02.65#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:42:02.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:42:02.65#ibcon#[27=AT02-05\r\n] 2006.260.07:42:02.65#ibcon#*before write, iclass 3, count 2 2006.260.07:42:02.65#ibcon#enter sib2, iclass 3, count 2 2006.260.07:42:02.65#ibcon#flushed, iclass 3, count 2 2006.260.07:42:02.65#ibcon#about to write, iclass 3, count 2 2006.260.07:42:02.65#ibcon#wrote, iclass 3, count 2 2006.260.07:42:02.65#ibcon#about to read 3, iclass 3, count 2 2006.260.07:42:02.68#ibcon#read 3, iclass 3, count 2 2006.260.07:42:02.68#ibcon#about to read 4, iclass 3, count 2 2006.260.07:42:02.68#ibcon#read 4, iclass 3, count 2 2006.260.07:42:02.68#ibcon#about to read 5, iclass 3, count 2 2006.260.07:42:02.68#ibcon#read 5, iclass 3, count 2 2006.260.07:42:02.68#ibcon#about to read 6, iclass 3, count 2 2006.260.07:42:02.68#ibcon#read 6, iclass 3, count 2 2006.260.07:42:02.68#ibcon#end of sib2, iclass 3, count 2 2006.260.07:42:02.68#ibcon#*after write, iclass 3, count 2 2006.260.07:42:02.68#ibcon#*before return 0, iclass 3, count 2 2006.260.07:42:02.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:02.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:42:02.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:42:02.68#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:02.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:02.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:02.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:02.80#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:42:02.80#ibcon#first serial, iclass 3, count 0 2006.260.07:42:02.80#ibcon#enter sib2, iclass 3, count 0 2006.260.07:42:02.80#ibcon#flushed, iclass 3, count 0 2006.260.07:42:02.80#ibcon#about to write, iclass 3, count 0 2006.260.07:42:02.80#ibcon#wrote, iclass 3, count 0 2006.260.07:42:02.80#ibcon#about to read 3, iclass 3, count 0 2006.260.07:42:02.82#ibcon#read 3, iclass 3, count 0 2006.260.07:42:02.82#ibcon#about to read 4, iclass 3, count 0 2006.260.07:42:02.82#ibcon#read 4, iclass 3, count 0 2006.260.07:42:02.82#ibcon#about to read 5, iclass 3, count 0 2006.260.07:42:02.82#ibcon#read 5, iclass 3, count 0 2006.260.07:42:02.82#ibcon#about to read 6, iclass 3, count 0 2006.260.07:42:02.82#ibcon#read 6, iclass 3, count 0 2006.260.07:42:02.82#ibcon#end of sib2, iclass 3, count 0 2006.260.07:42:02.82#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:42:02.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:42:02.82#ibcon#[27=USB\r\n] 2006.260.07:42:02.82#ibcon#*before write, iclass 3, count 0 2006.260.07:42:02.82#ibcon#enter sib2, iclass 3, count 0 2006.260.07:42:02.82#ibcon#flushed, iclass 3, count 0 2006.260.07:42:02.82#ibcon#about to write, iclass 3, count 0 2006.260.07:42:02.82#ibcon#wrote, iclass 3, count 0 2006.260.07:42:02.82#ibcon#about to read 3, iclass 3, count 0 2006.260.07:42:02.85#ibcon#read 3, iclass 3, count 0 2006.260.07:42:02.85#ibcon#about to read 4, iclass 3, count 0 2006.260.07:42:02.85#ibcon#read 4, iclass 3, count 0 2006.260.07:42:02.85#ibcon#about to read 5, iclass 3, count 0 2006.260.07:42:02.85#ibcon#read 5, iclass 3, count 0 2006.260.07:42:02.85#ibcon#about to read 6, iclass 3, count 0 2006.260.07:42:02.85#ibcon#read 6, iclass 3, count 0 2006.260.07:42:02.85#ibcon#end of sib2, iclass 3, count 0 2006.260.07:42:02.85#ibcon#*after write, iclass 3, count 0 2006.260.07:42:02.85#ibcon#*before return 0, iclass 3, count 0 2006.260.07:42:02.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:02.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:42:02.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:42:02.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:42:02.85$vc4f8/vblo=3,656.99 2006.260.07:42:02.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:42:02.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:42:02.85#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:02.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:02.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:02.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:02.85#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:42:02.85#ibcon#first serial, iclass 5, count 0 2006.260.07:42:02.85#ibcon#enter sib2, iclass 5, count 0 2006.260.07:42:02.85#ibcon#flushed, iclass 5, count 0 2006.260.07:42:02.85#ibcon#about to write, iclass 5, count 0 2006.260.07:42:02.85#ibcon#wrote, iclass 5, count 0 2006.260.07:42:02.85#ibcon#about to read 3, iclass 5, count 0 2006.260.07:42:02.87#ibcon#read 3, iclass 5, count 0 2006.260.07:42:02.87#ibcon#about to read 4, iclass 5, count 0 2006.260.07:42:02.87#ibcon#read 4, iclass 5, count 0 2006.260.07:42:02.87#ibcon#about to read 5, iclass 5, count 0 2006.260.07:42:02.87#ibcon#read 5, iclass 5, count 0 2006.260.07:42:02.87#ibcon#about to read 6, iclass 5, count 0 2006.260.07:42:02.87#ibcon#read 6, iclass 5, count 0 2006.260.07:42:02.87#ibcon#end of sib2, iclass 5, count 0 2006.260.07:42:02.87#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:42:02.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:42:02.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:42:02.87#ibcon#*before write, iclass 5, count 0 2006.260.07:42:02.87#ibcon#enter sib2, iclass 5, count 0 2006.260.07:42:02.87#ibcon#flushed, iclass 5, count 0 2006.260.07:42:02.87#ibcon#about to write, iclass 5, count 0 2006.260.07:42:02.87#ibcon#wrote, iclass 5, count 0 2006.260.07:42:02.87#ibcon#about to read 3, iclass 5, count 0 2006.260.07:42:02.91#ibcon#read 3, iclass 5, count 0 2006.260.07:42:02.91#ibcon#about to read 4, iclass 5, count 0 2006.260.07:42:02.91#ibcon#read 4, iclass 5, count 0 2006.260.07:42:02.91#ibcon#about to read 5, iclass 5, count 0 2006.260.07:42:02.91#ibcon#read 5, iclass 5, count 0 2006.260.07:42:02.91#ibcon#about to read 6, iclass 5, count 0 2006.260.07:42:02.91#ibcon#read 6, iclass 5, count 0 2006.260.07:42:02.91#ibcon#end of sib2, iclass 5, count 0 2006.260.07:42:02.91#ibcon#*after write, iclass 5, count 0 2006.260.07:42:02.91#ibcon#*before return 0, iclass 5, count 0 2006.260.07:42:02.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:02.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:42:02.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:42:02.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:42:02.91$vc4f8/vb=3,4 2006.260.07:42:02.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.07:42:02.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.07:42:02.91#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:02.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:02.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:02.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:02.97#ibcon#enter wrdev, iclass 7, count 2 2006.260.07:42:02.97#ibcon#first serial, iclass 7, count 2 2006.260.07:42:02.97#ibcon#enter sib2, iclass 7, count 2 2006.260.07:42:02.97#ibcon#flushed, iclass 7, count 2 2006.260.07:42:02.97#ibcon#about to write, iclass 7, count 2 2006.260.07:42:02.97#ibcon#wrote, iclass 7, count 2 2006.260.07:42:02.97#ibcon#about to read 3, iclass 7, count 2 2006.260.07:42:02.99#ibcon#read 3, iclass 7, count 2 2006.260.07:42:02.99#ibcon#about to read 4, iclass 7, count 2 2006.260.07:42:02.99#ibcon#read 4, iclass 7, count 2 2006.260.07:42:02.99#ibcon#about to read 5, iclass 7, count 2 2006.260.07:42:02.99#ibcon#read 5, iclass 7, count 2 2006.260.07:42:02.99#ibcon#about to read 6, iclass 7, count 2 2006.260.07:42:02.99#ibcon#read 6, iclass 7, count 2 2006.260.07:42:02.99#ibcon#end of sib2, iclass 7, count 2 2006.260.07:42:02.99#ibcon#*mode == 0, iclass 7, count 2 2006.260.07:42:02.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.07:42:02.99#ibcon#[27=AT03-04\r\n] 2006.260.07:42:02.99#ibcon#*before write, iclass 7, count 2 2006.260.07:42:02.99#ibcon#enter sib2, iclass 7, count 2 2006.260.07:42:02.99#ibcon#flushed, iclass 7, count 2 2006.260.07:42:02.99#ibcon#about to write, iclass 7, count 2 2006.260.07:42:02.99#ibcon#wrote, iclass 7, count 2 2006.260.07:42:02.99#ibcon#about to read 3, iclass 7, count 2 2006.260.07:42:03.02#ibcon#read 3, iclass 7, count 2 2006.260.07:42:03.02#ibcon#about to read 4, iclass 7, count 2 2006.260.07:42:03.02#ibcon#read 4, iclass 7, count 2 2006.260.07:42:03.02#ibcon#about to read 5, iclass 7, count 2 2006.260.07:42:03.02#ibcon#read 5, iclass 7, count 2 2006.260.07:42:03.02#ibcon#about to read 6, iclass 7, count 2 2006.260.07:42:03.02#ibcon#read 6, iclass 7, count 2 2006.260.07:42:03.02#ibcon#end of sib2, iclass 7, count 2 2006.260.07:42:03.02#ibcon#*after write, iclass 7, count 2 2006.260.07:42:03.02#ibcon#*before return 0, iclass 7, count 2 2006.260.07:42:03.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:03.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:42:03.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.07:42:03.02#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:03.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:03.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:03.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:03.14#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:42:03.14#ibcon#first serial, iclass 7, count 0 2006.260.07:42:03.14#ibcon#enter sib2, iclass 7, count 0 2006.260.07:42:03.14#ibcon#flushed, iclass 7, count 0 2006.260.07:42:03.14#ibcon#about to write, iclass 7, count 0 2006.260.07:42:03.14#ibcon#wrote, iclass 7, count 0 2006.260.07:42:03.14#ibcon#about to read 3, iclass 7, count 0 2006.260.07:42:03.16#ibcon#read 3, iclass 7, count 0 2006.260.07:42:03.16#ibcon#about to read 4, iclass 7, count 0 2006.260.07:42:03.16#ibcon#read 4, iclass 7, count 0 2006.260.07:42:03.16#ibcon#about to read 5, iclass 7, count 0 2006.260.07:42:03.16#ibcon#read 5, iclass 7, count 0 2006.260.07:42:03.16#ibcon#about to read 6, iclass 7, count 0 2006.260.07:42:03.16#ibcon#read 6, iclass 7, count 0 2006.260.07:42:03.16#ibcon#end of sib2, iclass 7, count 0 2006.260.07:42:03.16#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:42:03.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:42:03.16#ibcon#[27=USB\r\n] 2006.260.07:42:03.16#ibcon#*before write, iclass 7, count 0 2006.260.07:42:03.16#ibcon#enter sib2, iclass 7, count 0 2006.260.07:42:03.16#ibcon#flushed, iclass 7, count 0 2006.260.07:42:03.16#ibcon#about to write, iclass 7, count 0 2006.260.07:42:03.16#ibcon#wrote, iclass 7, count 0 2006.260.07:42:03.16#ibcon#about to read 3, iclass 7, count 0 2006.260.07:42:03.19#ibcon#read 3, iclass 7, count 0 2006.260.07:42:03.19#ibcon#about to read 4, iclass 7, count 0 2006.260.07:42:03.19#ibcon#read 4, iclass 7, count 0 2006.260.07:42:03.19#ibcon#about to read 5, iclass 7, count 0 2006.260.07:42:03.19#ibcon#read 5, iclass 7, count 0 2006.260.07:42:03.19#ibcon#about to read 6, iclass 7, count 0 2006.260.07:42:03.19#ibcon#read 6, iclass 7, count 0 2006.260.07:42:03.19#ibcon#end of sib2, iclass 7, count 0 2006.260.07:42:03.19#ibcon#*after write, iclass 7, count 0 2006.260.07:42:03.19#ibcon#*before return 0, iclass 7, count 0 2006.260.07:42:03.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:03.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:42:03.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:42:03.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:42:03.19$vc4f8/vblo=4,712.99 2006.260.07:42:03.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.07:42:03.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.07:42:03.19#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:03.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:42:03.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:42:03.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:42:03.19#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:42:03.19#ibcon#first serial, iclass 11, count 0 2006.260.07:42:03.19#ibcon#enter sib2, iclass 11, count 0 2006.260.07:42:03.19#ibcon#flushed, iclass 11, count 0 2006.260.07:42:03.19#ibcon#about to write, iclass 11, count 0 2006.260.07:42:03.19#ibcon#wrote, iclass 11, count 0 2006.260.07:42:03.19#ibcon#about to read 3, iclass 11, count 0 2006.260.07:42:03.21#ibcon#read 3, iclass 11, count 0 2006.260.07:42:03.21#ibcon#about to read 4, iclass 11, count 0 2006.260.07:42:03.21#ibcon#read 4, iclass 11, count 0 2006.260.07:42:03.21#ibcon#about to read 5, iclass 11, count 0 2006.260.07:42:03.21#ibcon#read 5, iclass 11, count 0 2006.260.07:42:03.21#ibcon#about to read 6, iclass 11, count 0 2006.260.07:42:03.21#ibcon#read 6, iclass 11, count 0 2006.260.07:42:03.21#ibcon#end of sib2, iclass 11, count 0 2006.260.07:42:03.21#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:42:03.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:42:03.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:42:03.21#ibcon#*before write, iclass 11, count 0 2006.260.07:42:03.21#ibcon#enter sib2, iclass 11, count 0 2006.260.07:42:03.21#ibcon#flushed, iclass 11, count 0 2006.260.07:42:03.21#ibcon#about to write, iclass 11, count 0 2006.260.07:42:03.21#ibcon#wrote, iclass 11, count 0 2006.260.07:42:03.21#ibcon#about to read 3, iclass 11, count 0 2006.260.07:42:03.26#ibcon#read 3, iclass 11, count 0 2006.260.07:42:03.26#ibcon#about to read 4, iclass 11, count 0 2006.260.07:42:03.26#ibcon#read 4, iclass 11, count 0 2006.260.07:42:03.26#ibcon#about to read 5, iclass 11, count 0 2006.260.07:42:03.26#ibcon#read 5, iclass 11, count 0 2006.260.07:42:03.26#ibcon#about to read 6, iclass 11, count 0 2006.260.07:42:03.26#ibcon#read 6, iclass 11, count 0 2006.260.07:42:03.26#ibcon#end of sib2, iclass 11, count 0 2006.260.07:42:03.26#ibcon#*after write, iclass 11, count 0 2006.260.07:42:03.26#ibcon#*before return 0, iclass 11, count 0 2006.260.07:42:03.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:42:03.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:42:03.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:42:03.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:42:03.26$vc4f8/vb=4,5 2006.260.07:42:03.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.07:42:03.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.07:42:03.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:03.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:42:03.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:42:03.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:42:03.31#ibcon#enter wrdev, iclass 13, count 2 2006.260.07:42:03.31#ibcon#first serial, iclass 13, count 2 2006.260.07:42:03.31#ibcon#enter sib2, iclass 13, count 2 2006.260.07:42:03.31#ibcon#flushed, iclass 13, count 2 2006.260.07:42:03.31#ibcon#about to write, iclass 13, count 2 2006.260.07:42:03.31#ibcon#wrote, iclass 13, count 2 2006.260.07:42:03.31#ibcon#about to read 3, iclass 13, count 2 2006.260.07:42:03.33#ibcon#read 3, iclass 13, count 2 2006.260.07:42:03.33#ibcon#about to read 4, iclass 13, count 2 2006.260.07:42:03.33#ibcon#read 4, iclass 13, count 2 2006.260.07:42:03.33#ibcon#about to read 5, iclass 13, count 2 2006.260.07:42:03.33#ibcon#read 5, iclass 13, count 2 2006.260.07:42:03.33#ibcon#about to read 6, iclass 13, count 2 2006.260.07:42:03.33#ibcon#read 6, iclass 13, count 2 2006.260.07:42:03.33#ibcon#end of sib2, iclass 13, count 2 2006.260.07:42:03.33#ibcon#*mode == 0, iclass 13, count 2 2006.260.07:42:03.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.07:42:03.33#ibcon#[27=AT04-05\r\n] 2006.260.07:42:03.33#ibcon#*before write, iclass 13, count 2 2006.260.07:42:03.33#ibcon#enter sib2, iclass 13, count 2 2006.260.07:42:03.33#ibcon#flushed, iclass 13, count 2 2006.260.07:42:03.33#ibcon#about to write, iclass 13, count 2 2006.260.07:42:03.33#ibcon#wrote, iclass 13, count 2 2006.260.07:42:03.33#ibcon#about to read 3, iclass 13, count 2 2006.260.07:42:03.36#ibcon#read 3, iclass 13, count 2 2006.260.07:42:03.36#ibcon#about to read 4, iclass 13, count 2 2006.260.07:42:03.36#ibcon#read 4, iclass 13, count 2 2006.260.07:42:03.36#ibcon#about to read 5, iclass 13, count 2 2006.260.07:42:03.36#ibcon#read 5, iclass 13, count 2 2006.260.07:42:03.36#ibcon#about to read 6, iclass 13, count 2 2006.260.07:42:03.36#ibcon#read 6, iclass 13, count 2 2006.260.07:42:03.36#ibcon#end of sib2, iclass 13, count 2 2006.260.07:42:03.36#ibcon#*after write, iclass 13, count 2 2006.260.07:42:03.36#ibcon#*before return 0, iclass 13, count 2 2006.260.07:42:03.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:42:03.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:42:03.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.07:42:03.36#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:03.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:42:03.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:42:03.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:42:03.48#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:42:03.48#ibcon#first serial, iclass 13, count 0 2006.260.07:42:03.48#ibcon#enter sib2, iclass 13, count 0 2006.260.07:42:03.48#ibcon#flushed, iclass 13, count 0 2006.260.07:42:03.48#ibcon#about to write, iclass 13, count 0 2006.260.07:42:03.48#ibcon#wrote, iclass 13, count 0 2006.260.07:42:03.48#ibcon#about to read 3, iclass 13, count 0 2006.260.07:42:03.50#ibcon#read 3, iclass 13, count 0 2006.260.07:42:03.50#ibcon#about to read 4, iclass 13, count 0 2006.260.07:42:03.50#ibcon#read 4, iclass 13, count 0 2006.260.07:42:03.50#ibcon#about to read 5, iclass 13, count 0 2006.260.07:42:03.50#ibcon#read 5, iclass 13, count 0 2006.260.07:42:03.50#ibcon#about to read 6, iclass 13, count 0 2006.260.07:42:03.50#ibcon#read 6, iclass 13, count 0 2006.260.07:42:03.50#ibcon#end of sib2, iclass 13, count 0 2006.260.07:42:03.50#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:42:03.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:42:03.50#ibcon#[27=USB\r\n] 2006.260.07:42:03.50#ibcon#*before write, iclass 13, count 0 2006.260.07:42:03.50#ibcon#enter sib2, iclass 13, count 0 2006.260.07:42:03.50#ibcon#flushed, iclass 13, count 0 2006.260.07:42:03.50#ibcon#about to write, iclass 13, count 0 2006.260.07:42:03.50#ibcon#wrote, iclass 13, count 0 2006.260.07:42:03.50#ibcon#about to read 3, iclass 13, count 0 2006.260.07:42:03.53#ibcon#read 3, iclass 13, count 0 2006.260.07:42:03.53#ibcon#about to read 4, iclass 13, count 0 2006.260.07:42:03.53#ibcon#read 4, iclass 13, count 0 2006.260.07:42:03.53#ibcon#about to read 5, iclass 13, count 0 2006.260.07:42:03.53#ibcon#read 5, iclass 13, count 0 2006.260.07:42:03.53#ibcon#about to read 6, iclass 13, count 0 2006.260.07:42:03.53#ibcon#read 6, iclass 13, count 0 2006.260.07:42:03.53#ibcon#end of sib2, iclass 13, count 0 2006.260.07:42:03.53#ibcon#*after write, iclass 13, count 0 2006.260.07:42:03.53#ibcon#*before return 0, iclass 13, count 0 2006.260.07:42:03.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:42:03.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:42:03.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:42:03.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:42:03.53$vc4f8/vblo=5,744.99 2006.260.07:42:03.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:42:03.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:42:03.53#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:03.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:42:03.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:42:03.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:42:03.53#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:42:03.53#ibcon#first serial, iclass 15, count 0 2006.260.07:42:03.53#ibcon#enter sib2, iclass 15, count 0 2006.260.07:42:03.53#ibcon#flushed, iclass 15, count 0 2006.260.07:42:03.53#ibcon#about to write, iclass 15, count 0 2006.260.07:42:03.53#ibcon#wrote, iclass 15, count 0 2006.260.07:42:03.53#ibcon#about to read 3, iclass 15, count 0 2006.260.07:42:03.55#ibcon#read 3, iclass 15, count 0 2006.260.07:42:03.55#ibcon#about to read 4, iclass 15, count 0 2006.260.07:42:03.55#ibcon#read 4, iclass 15, count 0 2006.260.07:42:03.55#ibcon#about to read 5, iclass 15, count 0 2006.260.07:42:03.55#ibcon#read 5, iclass 15, count 0 2006.260.07:42:03.55#ibcon#about to read 6, iclass 15, count 0 2006.260.07:42:03.55#ibcon#read 6, iclass 15, count 0 2006.260.07:42:03.55#ibcon#end of sib2, iclass 15, count 0 2006.260.07:42:03.55#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:42:03.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:42:03.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:42:03.55#ibcon#*before write, iclass 15, count 0 2006.260.07:42:03.55#ibcon#enter sib2, iclass 15, count 0 2006.260.07:42:03.55#ibcon#flushed, iclass 15, count 0 2006.260.07:42:03.55#ibcon#about to write, iclass 15, count 0 2006.260.07:42:03.55#ibcon#wrote, iclass 15, count 0 2006.260.07:42:03.55#ibcon#about to read 3, iclass 15, count 0 2006.260.07:42:03.59#ibcon#read 3, iclass 15, count 0 2006.260.07:42:03.59#ibcon#about to read 4, iclass 15, count 0 2006.260.07:42:03.59#ibcon#read 4, iclass 15, count 0 2006.260.07:42:03.59#ibcon#about to read 5, iclass 15, count 0 2006.260.07:42:03.59#ibcon#read 5, iclass 15, count 0 2006.260.07:42:03.59#ibcon#about to read 6, iclass 15, count 0 2006.260.07:42:03.59#ibcon#read 6, iclass 15, count 0 2006.260.07:42:03.59#ibcon#end of sib2, iclass 15, count 0 2006.260.07:42:03.59#ibcon#*after write, iclass 15, count 0 2006.260.07:42:03.59#ibcon#*before return 0, iclass 15, count 0 2006.260.07:42:03.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:42:03.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:42:03.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:42:03.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:42:03.59$vc4f8/vb=5,4 2006.260.07:42:03.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:42:03.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:42:03.59#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:03.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:03.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:03.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:03.65#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:42:03.65#ibcon#first serial, iclass 17, count 2 2006.260.07:42:03.65#ibcon#enter sib2, iclass 17, count 2 2006.260.07:42:03.65#ibcon#flushed, iclass 17, count 2 2006.260.07:42:03.65#ibcon#about to write, iclass 17, count 2 2006.260.07:42:03.65#ibcon#wrote, iclass 17, count 2 2006.260.07:42:03.65#ibcon#about to read 3, iclass 17, count 2 2006.260.07:42:03.67#ibcon#read 3, iclass 17, count 2 2006.260.07:42:03.67#ibcon#about to read 4, iclass 17, count 2 2006.260.07:42:03.67#ibcon#read 4, iclass 17, count 2 2006.260.07:42:03.67#ibcon#about to read 5, iclass 17, count 2 2006.260.07:42:03.67#ibcon#read 5, iclass 17, count 2 2006.260.07:42:03.67#ibcon#about to read 6, iclass 17, count 2 2006.260.07:42:03.67#ibcon#read 6, iclass 17, count 2 2006.260.07:42:03.67#ibcon#end of sib2, iclass 17, count 2 2006.260.07:42:03.67#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:42:03.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:42:03.67#ibcon#[27=AT05-04\r\n] 2006.260.07:42:03.67#ibcon#*before write, iclass 17, count 2 2006.260.07:42:03.67#ibcon#enter sib2, iclass 17, count 2 2006.260.07:42:03.67#ibcon#flushed, iclass 17, count 2 2006.260.07:42:03.67#ibcon#about to write, iclass 17, count 2 2006.260.07:42:03.67#ibcon#wrote, iclass 17, count 2 2006.260.07:42:03.67#ibcon#about to read 3, iclass 17, count 2 2006.260.07:42:03.70#ibcon#read 3, iclass 17, count 2 2006.260.07:42:03.70#ibcon#about to read 4, iclass 17, count 2 2006.260.07:42:03.70#ibcon#read 4, iclass 17, count 2 2006.260.07:42:03.70#ibcon#about to read 5, iclass 17, count 2 2006.260.07:42:03.70#ibcon#read 5, iclass 17, count 2 2006.260.07:42:03.70#ibcon#about to read 6, iclass 17, count 2 2006.260.07:42:03.70#ibcon#read 6, iclass 17, count 2 2006.260.07:42:03.70#ibcon#end of sib2, iclass 17, count 2 2006.260.07:42:03.70#ibcon#*after write, iclass 17, count 2 2006.260.07:42:03.70#ibcon#*before return 0, iclass 17, count 2 2006.260.07:42:03.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:03.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:42:03.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:42:03.70#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:03.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:03.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:03.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:03.82#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:42:03.82#ibcon#first serial, iclass 17, count 0 2006.260.07:42:03.82#ibcon#enter sib2, iclass 17, count 0 2006.260.07:42:03.82#ibcon#flushed, iclass 17, count 0 2006.260.07:42:03.82#ibcon#about to write, iclass 17, count 0 2006.260.07:42:03.82#ibcon#wrote, iclass 17, count 0 2006.260.07:42:03.82#ibcon#about to read 3, iclass 17, count 0 2006.260.07:42:03.84#ibcon#read 3, iclass 17, count 0 2006.260.07:42:03.84#ibcon#about to read 4, iclass 17, count 0 2006.260.07:42:03.84#ibcon#read 4, iclass 17, count 0 2006.260.07:42:03.84#ibcon#about to read 5, iclass 17, count 0 2006.260.07:42:03.84#ibcon#read 5, iclass 17, count 0 2006.260.07:42:03.84#ibcon#about to read 6, iclass 17, count 0 2006.260.07:42:03.84#ibcon#read 6, iclass 17, count 0 2006.260.07:42:03.84#ibcon#end of sib2, iclass 17, count 0 2006.260.07:42:03.84#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:42:03.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:42:03.84#ibcon#[27=USB\r\n] 2006.260.07:42:03.84#ibcon#*before write, iclass 17, count 0 2006.260.07:42:03.84#ibcon#enter sib2, iclass 17, count 0 2006.260.07:42:03.84#ibcon#flushed, iclass 17, count 0 2006.260.07:42:03.84#ibcon#about to write, iclass 17, count 0 2006.260.07:42:03.84#ibcon#wrote, iclass 17, count 0 2006.260.07:42:03.84#ibcon#about to read 3, iclass 17, count 0 2006.260.07:42:03.87#ibcon#read 3, iclass 17, count 0 2006.260.07:42:03.87#ibcon#about to read 4, iclass 17, count 0 2006.260.07:42:03.87#ibcon#read 4, iclass 17, count 0 2006.260.07:42:03.87#ibcon#about to read 5, iclass 17, count 0 2006.260.07:42:03.87#ibcon#read 5, iclass 17, count 0 2006.260.07:42:03.87#ibcon#about to read 6, iclass 17, count 0 2006.260.07:42:03.87#ibcon#read 6, iclass 17, count 0 2006.260.07:42:03.87#ibcon#end of sib2, iclass 17, count 0 2006.260.07:42:03.87#ibcon#*after write, iclass 17, count 0 2006.260.07:42:03.87#ibcon#*before return 0, iclass 17, count 0 2006.260.07:42:03.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:03.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:42:03.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:42:03.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:42:03.87$vc4f8/vblo=6,752.99 2006.260.07:42:03.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:42:03.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:42:03.87#ibcon#ireg 17 cls_cnt 0 2006.260.07:42:03.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:03.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:03.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:03.87#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:42:03.87#ibcon#first serial, iclass 19, count 0 2006.260.07:42:03.87#ibcon#enter sib2, iclass 19, count 0 2006.260.07:42:03.87#ibcon#flushed, iclass 19, count 0 2006.260.07:42:03.87#ibcon#about to write, iclass 19, count 0 2006.260.07:42:03.87#ibcon#wrote, iclass 19, count 0 2006.260.07:42:03.87#ibcon#about to read 3, iclass 19, count 0 2006.260.07:42:03.89#ibcon#read 3, iclass 19, count 0 2006.260.07:42:03.89#ibcon#about to read 4, iclass 19, count 0 2006.260.07:42:03.89#ibcon#read 4, iclass 19, count 0 2006.260.07:42:03.89#ibcon#about to read 5, iclass 19, count 0 2006.260.07:42:03.89#ibcon#read 5, iclass 19, count 0 2006.260.07:42:03.89#ibcon#about to read 6, iclass 19, count 0 2006.260.07:42:03.89#ibcon#read 6, iclass 19, count 0 2006.260.07:42:03.89#ibcon#end of sib2, iclass 19, count 0 2006.260.07:42:03.89#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:42:03.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:42:03.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:42:03.89#ibcon#*before write, iclass 19, count 0 2006.260.07:42:03.89#ibcon#enter sib2, iclass 19, count 0 2006.260.07:42:03.89#ibcon#flushed, iclass 19, count 0 2006.260.07:42:03.89#ibcon#about to write, iclass 19, count 0 2006.260.07:42:03.89#ibcon#wrote, iclass 19, count 0 2006.260.07:42:03.89#ibcon#about to read 3, iclass 19, count 0 2006.260.07:42:03.93#ibcon#read 3, iclass 19, count 0 2006.260.07:42:03.93#ibcon#about to read 4, iclass 19, count 0 2006.260.07:42:03.93#ibcon#read 4, iclass 19, count 0 2006.260.07:42:03.93#ibcon#about to read 5, iclass 19, count 0 2006.260.07:42:03.93#ibcon#read 5, iclass 19, count 0 2006.260.07:42:03.93#ibcon#about to read 6, iclass 19, count 0 2006.260.07:42:03.93#ibcon#read 6, iclass 19, count 0 2006.260.07:42:03.93#ibcon#end of sib2, iclass 19, count 0 2006.260.07:42:03.93#ibcon#*after write, iclass 19, count 0 2006.260.07:42:03.93#ibcon#*before return 0, iclass 19, count 0 2006.260.07:42:03.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:03.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:42:03.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:42:03.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:42:03.93$vc4f8/vb=6,4 2006.260.07:42:03.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:42:03.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:42:03.93#ibcon#ireg 11 cls_cnt 2 2006.260.07:42:03.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:03.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:03.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:03.99#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:42:03.99#ibcon#first serial, iclass 21, count 2 2006.260.07:42:03.99#ibcon#enter sib2, iclass 21, count 2 2006.260.07:42:03.99#ibcon#flushed, iclass 21, count 2 2006.260.07:42:03.99#ibcon#about to write, iclass 21, count 2 2006.260.07:42:03.99#ibcon#wrote, iclass 21, count 2 2006.260.07:42:03.99#ibcon#about to read 3, iclass 21, count 2 2006.260.07:42:04.01#ibcon#read 3, iclass 21, count 2 2006.260.07:42:04.01#ibcon#about to read 4, iclass 21, count 2 2006.260.07:42:04.01#ibcon#read 4, iclass 21, count 2 2006.260.07:42:04.01#ibcon#about to read 5, iclass 21, count 2 2006.260.07:42:04.01#ibcon#read 5, iclass 21, count 2 2006.260.07:42:04.01#ibcon#about to read 6, iclass 21, count 2 2006.260.07:42:04.01#ibcon#read 6, iclass 21, count 2 2006.260.07:42:04.01#ibcon#end of sib2, iclass 21, count 2 2006.260.07:42:04.01#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:42:04.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:42:04.01#ibcon#[27=AT06-04\r\n] 2006.260.07:42:04.01#ibcon#*before write, iclass 21, count 2 2006.260.07:42:04.01#ibcon#enter sib2, iclass 21, count 2 2006.260.07:42:04.01#ibcon#flushed, iclass 21, count 2 2006.260.07:42:04.01#ibcon#about to write, iclass 21, count 2 2006.260.07:42:04.01#ibcon#wrote, iclass 21, count 2 2006.260.07:42:04.01#ibcon#about to read 3, iclass 21, count 2 2006.260.07:42:04.04#ibcon#read 3, iclass 21, count 2 2006.260.07:42:04.04#ibcon#about to read 4, iclass 21, count 2 2006.260.07:42:04.04#ibcon#read 4, iclass 21, count 2 2006.260.07:42:04.04#ibcon#about to read 5, iclass 21, count 2 2006.260.07:42:04.04#ibcon#read 5, iclass 21, count 2 2006.260.07:42:04.04#ibcon#about to read 6, iclass 21, count 2 2006.260.07:42:04.04#ibcon#read 6, iclass 21, count 2 2006.260.07:42:04.04#ibcon#end of sib2, iclass 21, count 2 2006.260.07:42:04.04#ibcon#*after write, iclass 21, count 2 2006.260.07:42:04.04#ibcon#*before return 0, iclass 21, count 2 2006.260.07:42:04.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:04.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:42:04.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:42:04.04#ibcon#ireg 7 cls_cnt 0 2006.260.07:42:04.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:04.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:04.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:04.16#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:42:04.16#ibcon#first serial, iclass 21, count 0 2006.260.07:42:04.16#ibcon#enter sib2, iclass 21, count 0 2006.260.07:42:04.16#ibcon#flushed, iclass 21, count 0 2006.260.07:42:04.16#ibcon#about to write, iclass 21, count 0 2006.260.07:42:04.16#ibcon#wrote, iclass 21, count 0 2006.260.07:42:04.16#ibcon#about to read 3, iclass 21, count 0 2006.260.07:42:04.18#ibcon#read 3, iclass 21, count 0 2006.260.07:42:04.18#ibcon#about to read 4, iclass 21, count 0 2006.260.07:42:04.18#ibcon#read 4, iclass 21, count 0 2006.260.07:42:04.18#ibcon#about to read 5, iclass 21, count 0 2006.260.07:42:04.18#ibcon#read 5, iclass 21, count 0 2006.260.07:42:04.18#ibcon#about to read 6, iclass 21, count 0 2006.260.07:42:04.18#ibcon#read 6, iclass 21, count 0 2006.260.07:42:04.18#ibcon#end of sib2, iclass 21, count 0 2006.260.07:42:04.18#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:42:04.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:42:04.18#ibcon#[27=USB\r\n] 2006.260.07:42:04.18#ibcon#*before write, iclass 21, count 0 2006.260.07:42:04.18#ibcon#enter sib2, iclass 21, count 0 2006.260.07:42:04.18#ibcon#flushed, iclass 21, count 0 2006.260.07:42:04.18#ibcon#about to write, iclass 21, count 0 2006.260.07:42:04.18#ibcon#wrote, iclass 21, count 0 2006.260.07:42:04.18#ibcon#about to read 3, iclass 21, count 0 2006.260.07:42:04.21#ibcon#read 3, iclass 21, count 0 2006.260.07:42:04.21#ibcon#about to read 4, iclass 21, count 0 2006.260.07:42:04.21#ibcon#read 4, iclass 21, count 0 2006.260.07:42:04.21#ibcon#about to read 5, iclass 21, count 0 2006.260.07:42:04.21#ibcon#read 5, iclass 21, count 0 2006.260.07:42:04.21#ibcon#about to read 6, iclass 21, count 0 2006.260.07:42:04.21#ibcon#read 6, iclass 21, count 0 2006.260.07:42:04.21#ibcon#end of sib2, iclass 21, count 0 2006.260.07:42:04.21#ibcon#*after write, iclass 21, count 0 2006.260.07:42:04.21#ibcon#*before return 0, iclass 21, count 0 2006.260.07:42:04.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:04.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:42:04.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:42:04.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:42:04.21$vc4f8/vabw=wide 2006.260.07:42:04.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:42:04.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:42:04.21#ibcon#ireg 8 cls_cnt 0 2006.260.07:42:04.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:04.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:04.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:04.21#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:42:04.21#ibcon#first serial, iclass 23, count 0 2006.260.07:42:04.21#ibcon#enter sib2, iclass 23, count 0 2006.260.07:42:04.21#ibcon#flushed, iclass 23, count 0 2006.260.07:42:04.21#ibcon#about to write, iclass 23, count 0 2006.260.07:42:04.21#ibcon#wrote, iclass 23, count 0 2006.260.07:42:04.21#ibcon#about to read 3, iclass 23, count 0 2006.260.07:42:04.23#ibcon#read 3, iclass 23, count 0 2006.260.07:42:04.23#ibcon#about to read 4, iclass 23, count 0 2006.260.07:42:04.23#ibcon#read 4, iclass 23, count 0 2006.260.07:42:04.23#ibcon#about to read 5, iclass 23, count 0 2006.260.07:42:04.23#ibcon#read 5, iclass 23, count 0 2006.260.07:42:04.23#ibcon#about to read 6, iclass 23, count 0 2006.260.07:42:04.23#ibcon#read 6, iclass 23, count 0 2006.260.07:42:04.23#ibcon#end of sib2, iclass 23, count 0 2006.260.07:42:04.23#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:42:04.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:42:04.23#ibcon#[25=BW32\r\n] 2006.260.07:42:04.23#ibcon#*before write, iclass 23, count 0 2006.260.07:42:04.23#ibcon#enter sib2, iclass 23, count 0 2006.260.07:42:04.23#ibcon#flushed, iclass 23, count 0 2006.260.07:42:04.23#ibcon#about to write, iclass 23, count 0 2006.260.07:42:04.23#ibcon#wrote, iclass 23, count 0 2006.260.07:42:04.23#ibcon#about to read 3, iclass 23, count 0 2006.260.07:42:04.26#ibcon#read 3, iclass 23, count 0 2006.260.07:42:04.26#ibcon#about to read 4, iclass 23, count 0 2006.260.07:42:04.26#ibcon#read 4, iclass 23, count 0 2006.260.07:42:04.26#ibcon#about to read 5, iclass 23, count 0 2006.260.07:42:04.26#ibcon#read 5, iclass 23, count 0 2006.260.07:42:04.26#ibcon#about to read 6, iclass 23, count 0 2006.260.07:42:04.26#ibcon#read 6, iclass 23, count 0 2006.260.07:42:04.26#ibcon#end of sib2, iclass 23, count 0 2006.260.07:42:04.26#ibcon#*after write, iclass 23, count 0 2006.260.07:42:04.26#ibcon#*before return 0, iclass 23, count 0 2006.260.07:42:04.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:04.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:42:04.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:42:04.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:42:04.26$vc4f8/vbbw=wide 2006.260.07:42:04.26#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.07:42:04.26#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.07:42:04.26#ibcon#ireg 8 cls_cnt 0 2006.260.07:42:04.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:42:04.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:42:04.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:42:04.33#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:42:04.33#ibcon#first serial, iclass 25, count 0 2006.260.07:42:04.33#ibcon#enter sib2, iclass 25, count 0 2006.260.07:42:04.33#ibcon#flushed, iclass 25, count 0 2006.260.07:42:04.33#ibcon#about to write, iclass 25, count 0 2006.260.07:42:04.33#ibcon#wrote, iclass 25, count 0 2006.260.07:42:04.33#ibcon#about to read 3, iclass 25, count 0 2006.260.07:42:04.35#ibcon#read 3, iclass 25, count 0 2006.260.07:42:04.35#ibcon#about to read 4, iclass 25, count 0 2006.260.07:42:04.35#ibcon#read 4, iclass 25, count 0 2006.260.07:42:04.35#ibcon#about to read 5, iclass 25, count 0 2006.260.07:42:04.35#ibcon#read 5, iclass 25, count 0 2006.260.07:42:04.35#ibcon#about to read 6, iclass 25, count 0 2006.260.07:42:04.35#ibcon#read 6, iclass 25, count 0 2006.260.07:42:04.35#ibcon#end of sib2, iclass 25, count 0 2006.260.07:42:04.35#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:42:04.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:42:04.35#ibcon#[27=BW32\r\n] 2006.260.07:42:04.35#ibcon#*before write, iclass 25, count 0 2006.260.07:42:04.35#ibcon#enter sib2, iclass 25, count 0 2006.260.07:42:04.35#ibcon#flushed, iclass 25, count 0 2006.260.07:42:04.35#ibcon#about to write, iclass 25, count 0 2006.260.07:42:04.35#ibcon#wrote, iclass 25, count 0 2006.260.07:42:04.35#ibcon#about to read 3, iclass 25, count 0 2006.260.07:42:04.38#ibcon#read 3, iclass 25, count 0 2006.260.07:42:04.38#ibcon#about to read 4, iclass 25, count 0 2006.260.07:42:04.38#ibcon#read 4, iclass 25, count 0 2006.260.07:42:04.38#ibcon#about to read 5, iclass 25, count 0 2006.260.07:42:04.38#ibcon#read 5, iclass 25, count 0 2006.260.07:42:04.38#ibcon#about to read 6, iclass 25, count 0 2006.260.07:42:04.38#ibcon#read 6, iclass 25, count 0 2006.260.07:42:04.38#ibcon#end of sib2, iclass 25, count 0 2006.260.07:42:04.38#ibcon#*after write, iclass 25, count 0 2006.260.07:42:04.38#ibcon#*before return 0, iclass 25, count 0 2006.260.07:42:04.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:42:04.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:42:04.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:42:04.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:42:04.38$4f8m12a/ifd4f 2006.260.07:42:04.38$ifd4f/lo= 2006.260.07:42:04.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:42:04.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:42:04.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:42:04.38$ifd4f/patch= 2006.260.07:42:04.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:42:04.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:42:04.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:42:04.38$4f8m12a/"form=m,16.000,1:2 2006.260.07:42:04.38$4f8m12a/"tpicd 2006.260.07:42:04.38$4f8m12a/echo=off 2006.260.07:42:04.38$4f8m12a/xlog=off 2006.260.07:42:04.38:!2006.260.07:42:30 2006.260.07:42:14.14#trakl#Source acquired 2006.260.07:42:15.14#flagr#flagr/antenna,acquired 2006.260.07:42:30.00:preob 2006.260.07:42:31.14/onsource/TRACKING 2006.260.07:42:31.14:!2006.260.07:42:40 2006.260.07:42:40.00:data_valid=on 2006.260.07:42:40.00:midob 2006.260.07:42:40.14/onsource/TRACKING 2006.260.07:42:40.14/wx/23.05,1010.3,87 2006.260.07:42:40.25/cable/+6.4573E-03 2006.260.07:42:41.34/va/01,08,usb,yes,34,35 2006.260.07:42:41.34/va/02,07,usb,yes,34,35 2006.260.07:42:41.34/va/03,08,usb,yes,25,26 2006.260.07:42:41.34/va/04,07,usb,yes,35,38 2006.260.07:42:41.34/va/05,07,usb,yes,39,41 2006.260.07:42:41.34/va/06,06,usb,yes,38,37 2006.260.07:42:41.34/va/07,06,usb,yes,38,38 2006.260.07:42:41.34/va/08,06,usb,yes,41,40 2006.260.07:42:41.57/valo/01,532.99,yes,locked 2006.260.07:42:41.57/valo/02,572.99,yes,locked 2006.260.07:42:41.57/valo/03,672.99,yes,locked 2006.260.07:42:41.57/valo/04,832.99,yes,locked 2006.260.07:42:41.57/valo/05,652.99,yes,locked 2006.260.07:42:41.57/valo/06,772.99,yes,locked 2006.260.07:42:41.57/valo/07,832.99,yes,locked 2006.260.07:42:41.57/valo/08,852.99,yes,locked 2006.260.07:42:42.66/vb/01,04,usb,yes,32,31 2006.260.07:42:42.66/vb/02,05,usb,yes,30,31 2006.260.07:42:42.66/vb/03,04,usb,yes,30,34 2006.260.07:42:42.66/vb/04,05,usb,yes,27,27 2006.260.07:42:42.66/vb/05,04,usb,yes,29,34 2006.260.07:42:42.66/vb/06,04,usb,yes,30,33 2006.260.07:42:42.66/vb/07,04,usb,yes,33,32 2006.260.07:42:42.66/vb/08,04,usb,yes,30,33 2006.260.07:42:42.89/vblo/01,632.99,yes,locked 2006.260.07:42:42.89/vblo/02,640.99,yes,locked 2006.260.07:42:42.89/vblo/03,656.99,yes,locked 2006.260.07:42:42.89/vblo/04,712.99,yes,locked 2006.260.07:42:42.89/vblo/05,744.99,yes,locked 2006.260.07:42:42.89/vblo/06,752.99,yes,locked 2006.260.07:42:42.89/vblo/07,734.99,yes,locked 2006.260.07:42:42.89/vblo/08,744.99,yes,locked 2006.260.07:42:43.04/vabw/8 2006.260.07:42:43.19/vbbw/8 2006.260.07:42:43.28/xfe/off,on,15.0 2006.260.07:42:43.66/ifatt/23,28,28,28 2006.260.07:42:44.08/fmout-gps/S +4.51E-07 2006.260.07:42:44.12:!2006.260.07:43:40 2006.260.07:43:40.00:data_valid=off 2006.260.07:43:40.00:postob 2006.260.07:43:40.16/cable/+6.4578E-03 2006.260.07:43:40.16/wx/23.04,1010.4,87 2006.260.07:43:41.08/fmout-gps/S +4.51E-07 2006.260.07:43:41.08:scan_name=260-0744,k06260,60 2006.260.07:43:41.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.260.07:43:41.13#flagr#flagr/antenna,new-source 2006.260.07:43:42.13:checkk5 2006.260.07:43:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:43:42.99/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:43:43.40/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:43:43.81/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:43:44.21/chk_obsdata//k5ts1/T2600742??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:43:44.62/chk_obsdata//k5ts2/T2600742??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:43:45.01/chk_obsdata//k5ts3/T2600742??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:43:45.40/chk_obsdata//k5ts4/T2600742??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:43:46.20/k5log//k5ts1_log_newline 2006.260.07:43:47.22/k5log//k5ts2_log_newline 2006.260.07:43:48.05/k5log//k5ts3_log_newline 2006.260.07:43:48.81/k5log//k5ts4_log_newline 2006.260.07:43:48.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:43:48.83:4f8m12a=1 2006.260.07:43:48.83$4f8m12a/echo=on 2006.260.07:43:48.83$4f8m12a/pcalon 2006.260.07:43:48.83$pcalon/"no phase cal control is implemented here 2006.260.07:43:48.84$4f8m12a/"tpicd=stop 2006.260.07:43:48.84$4f8m12a/vc4f8 2006.260.07:43:48.84$vc4f8/valo=1,532.99 2006.260.07:43:48.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:43:48.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:43:48.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:48.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:48.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:48.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:48.84#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:43:48.84#ibcon#first serial, iclass 32, count 0 2006.260.07:43:48.84#ibcon#enter sib2, iclass 32, count 0 2006.260.07:43:48.84#ibcon#flushed, iclass 32, count 0 2006.260.07:43:48.84#ibcon#about to write, iclass 32, count 0 2006.260.07:43:48.84#ibcon#wrote, iclass 32, count 0 2006.260.07:43:48.84#ibcon#about to read 3, iclass 32, count 0 2006.260.07:43:48.88#ibcon#read 3, iclass 32, count 0 2006.260.07:43:48.88#ibcon#about to read 4, iclass 32, count 0 2006.260.07:43:48.88#ibcon#read 4, iclass 32, count 0 2006.260.07:43:48.88#ibcon#about to read 5, iclass 32, count 0 2006.260.07:43:48.88#ibcon#read 5, iclass 32, count 0 2006.260.07:43:48.88#ibcon#about to read 6, iclass 32, count 0 2006.260.07:43:48.88#ibcon#read 6, iclass 32, count 0 2006.260.07:43:48.88#ibcon#end of sib2, iclass 32, count 0 2006.260.07:43:48.88#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:43:48.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:43:48.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:43:48.88#ibcon#*before write, iclass 32, count 0 2006.260.07:43:48.88#ibcon#enter sib2, iclass 32, count 0 2006.260.07:43:48.88#ibcon#flushed, iclass 32, count 0 2006.260.07:43:48.88#ibcon#about to write, iclass 32, count 0 2006.260.07:43:48.88#ibcon#wrote, iclass 32, count 0 2006.260.07:43:48.88#ibcon#about to read 3, iclass 32, count 0 2006.260.07:43:48.93#ibcon#read 3, iclass 32, count 0 2006.260.07:43:48.93#ibcon#about to read 4, iclass 32, count 0 2006.260.07:43:48.93#ibcon#read 4, iclass 32, count 0 2006.260.07:43:48.93#ibcon#about to read 5, iclass 32, count 0 2006.260.07:43:48.93#ibcon#read 5, iclass 32, count 0 2006.260.07:43:48.93#ibcon#about to read 6, iclass 32, count 0 2006.260.07:43:48.93#ibcon#read 6, iclass 32, count 0 2006.260.07:43:48.93#ibcon#end of sib2, iclass 32, count 0 2006.260.07:43:48.93#ibcon#*after write, iclass 32, count 0 2006.260.07:43:48.93#ibcon#*before return 0, iclass 32, count 0 2006.260.07:43:48.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:48.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:48.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:43:48.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:43:48.93$vc4f8/va=1,8 2006.260.07:43:48.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.07:43:48.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.07:43:48.93#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:48.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:48.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:48.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:48.93#ibcon#enter wrdev, iclass 34, count 2 2006.260.07:43:48.93#ibcon#first serial, iclass 34, count 2 2006.260.07:43:48.93#ibcon#enter sib2, iclass 34, count 2 2006.260.07:43:48.93#ibcon#flushed, iclass 34, count 2 2006.260.07:43:48.93#ibcon#about to write, iclass 34, count 2 2006.260.07:43:48.93#ibcon#wrote, iclass 34, count 2 2006.260.07:43:48.93#ibcon#about to read 3, iclass 34, count 2 2006.260.07:43:48.95#ibcon#read 3, iclass 34, count 2 2006.260.07:43:48.95#ibcon#about to read 4, iclass 34, count 2 2006.260.07:43:48.95#ibcon#read 4, iclass 34, count 2 2006.260.07:43:48.95#ibcon#about to read 5, iclass 34, count 2 2006.260.07:43:48.95#ibcon#read 5, iclass 34, count 2 2006.260.07:43:48.95#ibcon#about to read 6, iclass 34, count 2 2006.260.07:43:48.95#ibcon#read 6, iclass 34, count 2 2006.260.07:43:48.95#ibcon#end of sib2, iclass 34, count 2 2006.260.07:43:48.95#ibcon#*mode == 0, iclass 34, count 2 2006.260.07:43:48.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.07:43:48.95#ibcon#[25=AT01-08\r\n] 2006.260.07:43:48.95#ibcon#*before write, iclass 34, count 2 2006.260.07:43:48.95#ibcon#enter sib2, iclass 34, count 2 2006.260.07:43:48.95#ibcon#flushed, iclass 34, count 2 2006.260.07:43:48.95#ibcon#about to write, iclass 34, count 2 2006.260.07:43:48.95#ibcon#wrote, iclass 34, count 2 2006.260.07:43:48.95#ibcon#about to read 3, iclass 34, count 2 2006.260.07:43:48.98#ibcon#read 3, iclass 34, count 2 2006.260.07:43:48.98#ibcon#about to read 4, iclass 34, count 2 2006.260.07:43:48.98#ibcon#read 4, iclass 34, count 2 2006.260.07:43:48.98#ibcon#about to read 5, iclass 34, count 2 2006.260.07:43:48.98#ibcon#read 5, iclass 34, count 2 2006.260.07:43:48.98#ibcon#about to read 6, iclass 34, count 2 2006.260.07:43:48.98#ibcon#read 6, iclass 34, count 2 2006.260.07:43:48.98#ibcon#end of sib2, iclass 34, count 2 2006.260.07:43:48.98#ibcon#*after write, iclass 34, count 2 2006.260.07:43:48.98#ibcon#*before return 0, iclass 34, count 2 2006.260.07:43:48.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:48.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:48.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.07:43:48.98#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:48.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:49.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:49.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:49.10#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:43:49.10#ibcon#first serial, iclass 34, count 0 2006.260.07:43:49.10#ibcon#enter sib2, iclass 34, count 0 2006.260.07:43:49.10#ibcon#flushed, iclass 34, count 0 2006.260.07:43:49.10#ibcon#about to write, iclass 34, count 0 2006.260.07:43:49.10#ibcon#wrote, iclass 34, count 0 2006.260.07:43:49.10#ibcon#about to read 3, iclass 34, count 0 2006.260.07:43:49.12#ibcon#read 3, iclass 34, count 0 2006.260.07:43:49.12#ibcon#about to read 4, iclass 34, count 0 2006.260.07:43:49.12#ibcon#read 4, iclass 34, count 0 2006.260.07:43:49.12#ibcon#about to read 5, iclass 34, count 0 2006.260.07:43:49.12#ibcon#read 5, iclass 34, count 0 2006.260.07:43:49.12#ibcon#about to read 6, iclass 34, count 0 2006.260.07:43:49.12#ibcon#read 6, iclass 34, count 0 2006.260.07:43:49.12#ibcon#end of sib2, iclass 34, count 0 2006.260.07:43:49.12#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:43:49.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:43:49.12#ibcon#[25=USB\r\n] 2006.260.07:43:49.12#ibcon#*before write, iclass 34, count 0 2006.260.07:43:49.12#ibcon#enter sib2, iclass 34, count 0 2006.260.07:43:49.12#ibcon#flushed, iclass 34, count 0 2006.260.07:43:49.12#ibcon#about to write, iclass 34, count 0 2006.260.07:43:49.12#ibcon#wrote, iclass 34, count 0 2006.260.07:43:49.12#ibcon#about to read 3, iclass 34, count 0 2006.260.07:43:49.15#ibcon#read 3, iclass 34, count 0 2006.260.07:43:49.15#ibcon#about to read 4, iclass 34, count 0 2006.260.07:43:49.15#ibcon#read 4, iclass 34, count 0 2006.260.07:43:49.15#ibcon#about to read 5, iclass 34, count 0 2006.260.07:43:49.15#ibcon#read 5, iclass 34, count 0 2006.260.07:43:49.15#ibcon#about to read 6, iclass 34, count 0 2006.260.07:43:49.15#ibcon#read 6, iclass 34, count 0 2006.260.07:43:49.15#ibcon#end of sib2, iclass 34, count 0 2006.260.07:43:49.15#ibcon#*after write, iclass 34, count 0 2006.260.07:43:49.15#ibcon#*before return 0, iclass 34, count 0 2006.260.07:43:49.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:49.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:49.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:43:49.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:43:49.15$vc4f8/valo=2,572.99 2006.260.07:43:49.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.07:43:49.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.07:43:49.15#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:49.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:49.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:49.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:49.15#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:43:49.15#ibcon#first serial, iclass 36, count 0 2006.260.07:43:49.15#ibcon#enter sib2, iclass 36, count 0 2006.260.07:43:49.15#ibcon#flushed, iclass 36, count 0 2006.260.07:43:49.15#ibcon#about to write, iclass 36, count 0 2006.260.07:43:49.15#ibcon#wrote, iclass 36, count 0 2006.260.07:43:49.15#ibcon#about to read 3, iclass 36, count 0 2006.260.07:43:49.17#ibcon#read 3, iclass 36, count 0 2006.260.07:43:49.17#ibcon#about to read 4, iclass 36, count 0 2006.260.07:43:49.17#ibcon#read 4, iclass 36, count 0 2006.260.07:43:49.17#ibcon#about to read 5, iclass 36, count 0 2006.260.07:43:49.17#ibcon#read 5, iclass 36, count 0 2006.260.07:43:49.17#ibcon#about to read 6, iclass 36, count 0 2006.260.07:43:49.17#ibcon#read 6, iclass 36, count 0 2006.260.07:43:49.17#ibcon#end of sib2, iclass 36, count 0 2006.260.07:43:49.17#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:43:49.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:43:49.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:43:49.17#ibcon#*before write, iclass 36, count 0 2006.260.07:43:49.17#ibcon#enter sib2, iclass 36, count 0 2006.260.07:43:49.17#ibcon#flushed, iclass 36, count 0 2006.260.07:43:49.17#ibcon#about to write, iclass 36, count 0 2006.260.07:43:49.17#ibcon#wrote, iclass 36, count 0 2006.260.07:43:49.17#ibcon#about to read 3, iclass 36, count 0 2006.260.07:43:49.22#ibcon#read 3, iclass 36, count 0 2006.260.07:43:49.22#ibcon#about to read 4, iclass 36, count 0 2006.260.07:43:49.22#ibcon#read 4, iclass 36, count 0 2006.260.07:43:49.22#ibcon#about to read 5, iclass 36, count 0 2006.260.07:43:49.22#ibcon#read 5, iclass 36, count 0 2006.260.07:43:49.22#ibcon#about to read 6, iclass 36, count 0 2006.260.07:43:49.22#ibcon#read 6, iclass 36, count 0 2006.260.07:43:49.22#ibcon#end of sib2, iclass 36, count 0 2006.260.07:43:49.22#ibcon#*after write, iclass 36, count 0 2006.260.07:43:49.22#ibcon#*before return 0, iclass 36, count 0 2006.260.07:43:49.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:49.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:49.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:43:49.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:43:49.22$vc4f8/va=2,7 2006.260.07:43:49.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.07:43:49.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.07:43:49.22#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:49.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:49.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:49.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:49.27#ibcon#enter wrdev, iclass 38, count 2 2006.260.07:43:49.27#ibcon#first serial, iclass 38, count 2 2006.260.07:43:49.27#ibcon#enter sib2, iclass 38, count 2 2006.260.07:43:49.27#ibcon#flushed, iclass 38, count 2 2006.260.07:43:49.27#ibcon#about to write, iclass 38, count 2 2006.260.07:43:49.27#ibcon#wrote, iclass 38, count 2 2006.260.07:43:49.27#ibcon#about to read 3, iclass 38, count 2 2006.260.07:43:49.29#ibcon#read 3, iclass 38, count 2 2006.260.07:43:49.29#ibcon#about to read 4, iclass 38, count 2 2006.260.07:43:49.29#ibcon#read 4, iclass 38, count 2 2006.260.07:43:49.29#ibcon#about to read 5, iclass 38, count 2 2006.260.07:43:49.29#ibcon#read 5, iclass 38, count 2 2006.260.07:43:49.29#ibcon#about to read 6, iclass 38, count 2 2006.260.07:43:49.29#ibcon#read 6, iclass 38, count 2 2006.260.07:43:49.29#ibcon#end of sib2, iclass 38, count 2 2006.260.07:43:49.29#ibcon#*mode == 0, iclass 38, count 2 2006.260.07:43:49.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.07:43:49.29#ibcon#[25=AT02-07\r\n] 2006.260.07:43:49.29#ibcon#*before write, iclass 38, count 2 2006.260.07:43:49.29#ibcon#enter sib2, iclass 38, count 2 2006.260.07:43:49.29#ibcon#flushed, iclass 38, count 2 2006.260.07:43:49.29#ibcon#about to write, iclass 38, count 2 2006.260.07:43:49.29#ibcon#wrote, iclass 38, count 2 2006.260.07:43:49.29#ibcon#about to read 3, iclass 38, count 2 2006.260.07:43:49.33#ibcon#read 3, iclass 38, count 2 2006.260.07:43:49.33#ibcon#about to read 4, iclass 38, count 2 2006.260.07:43:49.33#ibcon#read 4, iclass 38, count 2 2006.260.07:43:49.33#ibcon#about to read 5, iclass 38, count 2 2006.260.07:43:49.33#ibcon#read 5, iclass 38, count 2 2006.260.07:43:49.33#ibcon#about to read 6, iclass 38, count 2 2006.260.07:43:49.33#ibcon#read 6, iclass 38, count 2 2006.260.07:43:49.33#ibcon#end of sib2, iclass 38, count 2 2006.260.07:43:49.33#ibcon#*after write, iclass 38, count 2 2006.260.07:43:49.33#ibcon#*before return 0, iclass 38, count 2 2006.260.07:43:49.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:49.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:49.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.07:43:49.33#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:49.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:49.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:49.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:49.45#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:43:49.45#ibcon#first serial, iclass 38, count 0 2006.260.07:43:49.45#ibcon#enter sib2, iclass 38, count 0 2006.260.07:43:49.45#ibcon#flushed, iclass 38, count 0 2006.260.07:43:49.45#ibcon#about to write, iclass 38, count 0 2006.260.07:43:49.45#ibcon#wrote, iclass 38, count 0 2006.260.07:43:49.45#ibcon#about to read 3, iclass 38, count 0 2006.260.07:43:49.47#ibcon#read 3, iclass 38, count 0 2006.260.07:43:49.47#ibcon#about to read 4, iclass 38, count 0 2006.260.07:43:49.47#ibcon#read 4, iclass 38, count 0 2006.260.07:43:49.47#ibcon#about to read 5, iclass 38, count 0 2006.260.07:43:49.47#ibcon#read 5, iclass 38, count 0 2006.260.07:43:49.47#ibcon#about to read 6, iclass 38, count 0 2006.260.07:43:49.47#ibcon#read 6, iclass 38, count 0 2006.260.07:43:49.47#ibcon#end of sib2, iclass 38, count 0 2006.260.07:43:49.47#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:43:49.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:43:49.47#ibcon#[25=USB\r\n] 2006.260.07:43:49.47#ibcon#*before write, iclass 38, count 0 2006.260.07:43:49.47#ibcon#enter sib2, iclass 38, count 0 2006.260.07:43:49.47#ibcon#flushed, iclass 38, count 0 2006.260.07:43:49.47#ibcon#about to write, iclass 38, count 0 2006.260.07:43:49.47#ibcon#wrote, iclass 38, count 0 2006.260.07:43:49.47#ibcon#about to read 3, iclass 38, count 0 2006.260.07:43:49.50#ibcon#read 3, iclass 38, count 0 2006.260.07:43:49.50#ibcon#about to read 4, iclass 38, count 0 2006.260.07:43:49.50#ibcon#read 4, iclass 38, count 0 2006.260.07:43:49.50#ibcon#about to read 5, iclass 38, count 0 2006.260.07:43:49.50#ibcon#read 5, iclass 38, count 0 2006.260.07:43:49.50#ibcon#about to read 6, iclass 38, count 0 2006.260.07:43:49.50#ibcon#read 6, iclass 38, count 0 2006.260.07:43:49.50#ibcon#end of sib2, iclass 38, count 0 2006.260.07:43:49.50#ibcon#*after write, iclass 38, count 0 2006.260.07:43:49.50#ibcon#*before return 0, iclass 38, count 0 2006.260.07:43:49.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:49.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:49.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:43:49.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:43:49.50$vc4f8/valo=3,672.99 2006.260.07:43:49.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.07:43:49.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.07:43:49.50#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:49.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:43:49.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:43:49.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:43:49.50#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:43:49.50#ibcon#first serial, iclass 40, count 0 2006.260.07:43:49.50#ibcon#enter sib2, iclass 40, count 0 2006.260.07:43:49.50#ibcon#flushed, iclass 40, count 0 2006.260.07:43:49.50#ibcon#about to write, iclass 40, count 0 2006.260.07:43:49.50#ibcon#wrote, iclass 40, count 0 2006.260.07:43:49.50#ibcon#about to read 3, iclass 40, count 0 2006.260.07:43:49.52#ibcon#read 3, iclass 40, count 0 2006.260.07:43:49.52#ibcon#about to read 4, iclass 40, count 0 2006.260.07:43:49.52#ibcon#read 4, iclass 40, count 0 2006.260.07:43:49.52#ibcon#about to read 5, iclass 40, count 0 2006.260.07:43:49.52#ibcon#read 5, iclass 40, count 0 2006.260.07:43:49.52#ibcon#about to read 6, iclass 40, count 0 2006.260.07:43:49.52#ibcon#read 6, iclass 40, count 0 2006.260.07:43:49.52#ibcon#end of sib2, iclass 40, count 0 2006.260.07:43:49.52#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:43:49.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:43:49.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:43:49.52#ibcon#*before write, iclass 40, count 0 2006.260.07:43:49.52#ibcon#enter sib2, iclass 40, count 0 2006.260.07:43:49.52#ibcon#flushed, iclass 40, count 0 2006.260.07:43:49.52#ibcon#about to write, iclass 40, count 0 2006.260.07:43:49.52#ibcon#wrote, iclass 40, count 0 2006.260.07:43:49.52#ibcon#about to read 3, iclass 40, count 0 2006.260.07:43:49.56#ibcon#read 3, iclass 40, count 0 2006.260.07:43:49.56#ibcon#about to read 4, iclass 40, count 0 2006.260.07:43:49.56#ibcon#read 4, iclass 40, count 0 2006.260.07:43:49.56#ibcon#about to read 5, iclass 40, count 0 2006.260.07:43:49.56#ibcon#read 5, iclass 40, count 0 2006.260.07:43:49.56#ibcon#about to read 6, iclass 40, count 0 2006.260.07:43:49.56#ibcon#read 6, iclass 40, count 0 2006.260.07:43:49.56#ibcon#end of sib2, iclass 40, count 0 2006.260.07:43:49.56#ibcon#*after write, iclass 40, count 0 2006.260.07:43:49.56#ibcon#*before return 0, iclass 40, count 0 2006.260.07:43:49.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:43:49.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:43:49.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:43:49.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:43:49.56$vc4f8/va=3,8 2006.260.07:43:49.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.07:43:49.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.07:43:49.56#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:49.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:43:49.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:43:49.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:43:49.62#ibcon#enter wrdev, iclass 4, count 2 2006.260.07:43:49.62#ibcon#first serial, iclass 4, count 2 2006.260.07:43:49.62#ibcon#enter sib2, iclass 4, count 2 2006.260.07:43:49.62#ibcon#flushed, iclass 4, count 2 2006.260.07:43:49.62#ibcon#about to write, iclass 4, count 2 2006.260.07:43:49.62#ibcon#wrote, iclass 4, count 2 2006.260.07:43:49.62#ibcon#about to read 3, iclass 4, count 2 2006.260.07:43:49.64#ibcon#read 3, iclass 4, count 2 2006.260.07:43:49.64#ibcon#about to read 4, iclass 4, count 2 2006.260.07:43:49.64#ibcon#read 4, iclass 4, count 2 2006.260.07:43:49.64#ibcon#about to read 5, iclass 4, count 2 2006.260.07:43:49.64#ibcon#read 5, iclass 4, count 2 2006.260.07:43:49.64#ibcon#about to read 6, iclass 4, count 2 2006.260.07:43:49.64#ibcon#read 6, iclass 4, count 2 2006.260.07:43:49.64#ibcon#end of sib2, iclass 4, count 2 2006.260.07:43:49.64#ibcon#*mode == 0, iclass 4, count 2 2006.260.07:43:49.64#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.07:43:49.64#ibcon#[25=AT03-08\r\n] 2006.260.07:43:49.64#ibcon#*before write, iclass 4, count 2 2006.260.07:43:49.64#ibcon#enter sib2, iclass 4, count 2 2006.260.07:43:49.64#ibcon#flushed, iclass 4, count 2 2006.260.07:43:49.64#ibcon#about to write, iclass 4, count 2 2006.260.07:43:49.64#ibcon#wrote, iclass 4, count 2 2006.260.07:43:49.64#ibcon#about to read 3, iclass 4, count 2 2006.260.07:43:49.67#ibcon#read 3, iclass 4, count 2 2006.260.07:43:49.67#ibcon#about to read 4, iclass 4, count 2 2006.260.07:43:49.67#ibcon#read 4, iclass 4, count 2 2006.260.07:43:49.67#ibcon#about to read 5, iclass 4, count 2 2006.260.07:43:49.67#ibcon#read 5, iclass 4, count 2 2006.260.07:43:49.67#ibcon#about to read 6, iclass 4, count 2 2006.260.07:43:49.67#ibcon#read 6, iclass 4, count 2 2006.260.07:43:49.67#ibcon#end of sib2, iclass 4, count 2 2006.260.07:43:49.67#ibcon#*after write, iclass 4, count 2 2006.260.07:43:49.67#ibcon#*before return 0, iclass 4, count 2 2006.260.07:43:49.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:43:49.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:43:49.67#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.07:43:49.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:49.67#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:43:49.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:43:49.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:43:49.79#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:43:49.79#ibcon#first serial, iclass 4, count 0 2006.260.07:43:49.79#ibcon#enter sib2, iclass 4, count 0 2006.260.07:43:49.79#ibcon#flushed, iclass 4, count 0 2006.260.07:43:49.79#ibcon#about to write, iclass 4, count 0 2006.260.07:43:49.79#ibcon#wrote, iclass 4, count 0 2006.260.07:43:49.79#ibcon#about to read 3, iclass 4, count 0 2006.260.07:43:49.81#ibcon#read 3, iclass 4, count 0 2006.260.07:43:49.81#ibcon#about to read 4, iclass 4, count 0 2006.260.07:43:49.81#ibcon#read 4, iclass 4, count 0 2006.260.07:43:49.81#ibcon#about to read 5, iclass 4, count 0 2006.260.07:43:49.81#ibcon#read 5, iclass 4, count 0 2006.260.07:43:49.81#ibcon#about to read 6, iclass 4, count 0 2006.260.07:43:49.81#ibcon#read 6, iclass 4, count 0 2006.260.07:43:49.81#ibcon#end of sib2, iclass 4, count 0 2006.260.07:43:49.81#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:43:49.81#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:43:49.81#ibcon#[25=USB\r\n] 2006.260.07:43:49.81#ibcon#*before write, iclass 4, count 0 2006.260.07:43:49.81#ibcon#enter sib2, iclass 4, count 0 2006.260.07:43:49.81#ibcon#flushed, iclass 4, count 0 2006.260.07:43:49.81#ibcon#about to write, iclass 4, count 0 2006.260.07:43:49.81#ibcon#wrote, iclass 4, count 0 2006.260.07:43:49.81#ibcon#about to read 3, iclass 4, count 0 2006.260.07:43:49.84#ibcon#read 3, iclass 4, count 0 2006.260.07:43:49.84#ibcon#about to read 4, iclass 4, count 0 2006.260.07:43:49.84#ibcon#read 4, iclass 4, count 0 2006.260.07:43:49.84#ibcon#about to read 5, iclass 4, count 0 2006.260.07:43:49.84#ibcon#read 5, iclass 4, count 0 2006.260.07:43:49.84#ibcon#about to read 6, iclass 4, count 0 2006.260.07:43:49.84#ibcon#read 6, iclass 4, count 0 2006.260.07:43:49.84#ibcon#end of sib2, iclass 4, count 0 2006.260.07:43:49.84#ibcon#*after write, iclass 4, count 0 2006.260.07:43:49.84#ibcon#*before return 0, iclass 4, count 0 2006.260.07:43:49.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:43:49.84#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:43:49.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:43:49.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:43:49.84$vc4f8/valo=4,832.99 2006.260.07:43:49.84#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.07:43:49.84#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.07:43:49.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:49.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:49.84#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:49.84#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:49.84#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:43:49.84#ibcon#first serial, iclass 6, count 0 2006.260.07:43:49.84#ibcon#enter sib2, iclass 6, count 0 2006.260.07:43:49.84#ibcon#flushed, iclass 6, count 0 2006.260.07:43:49.84#ibcon#about to write, iclass 6, count 0 2006.260.07:43:49.84#ibcon#wrote, iclass 6, count 0 2006.260.07:43:49.84#ibcon#about to read 3, iclass 6, count 0 2006.260.07:43:49.86#ibcon#read 3, iclass 6, count 0 2006.260.07:43:49.86#ibcon#about to read 4, iclass 6, count 0 2006.260.07:43:49.86#ibcon#read 4, iclass 6, count 0 2006.260.07:43:49.86#ibcon#about to read 5, iclass 6, count 0 2006.260.07:43:49.86#ibcon#read 5, iclass 6, count 0 2006.260.07:43:49.86#ibcon#about to read 6, iclass 6, count 0 2006.260.07:43:49.86#ibcon#read 6, iclass 6, count 0 2006.260.07:43:49.86#ibcon#end of sib2, iclass 6, count 0 2006.260.07:43:49.86#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:43:49.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:43:49.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:43:49.86#ibcon#*before write, iclass 6, count 0 2006.260.07:43:49.86#ibcon#enter sib2, iclass 6, count 0 2006.260.07:43:49.86#ibcon#flushed, iclass 6, count 0 2006.260.07:43:49.86#ibcon#about to write, iclass 6, count 0 2006.260.07:43:49.86#ibcon#wrote, iclass 6, count 0 2006.260.07:43:49.86#ibcon#about to read 3, iclass 6, count 0 2006.260.07:43:49.90#ibcon#read 3, iclass 6, count 0 2006.260.07:43:49.90#ibcon#about to read 4, iclass 6, count 0 2006.260.07:43:49.90#ibcon#read 4, iclass 6, count 0 2006.260.07:43:49.90#ibcon#about to read 5, iclass 6, count 0 2006.260.07:43:49.90#ibcon#read 5, iclass 6, count 0 2006.260.07:43:49.90#ibcon#about to read 6, iclass 6, count 0 2006.260.07:43:49.90#ibcon#read 6, iclass 6, count 0 2006.260.07:43:49.90#ibcon#end of sib2, iclass 6, count 0 2006.260.07:43:49.90#ibcon#*after write, iclass 6, count 0 2006.260.07:43:49.90#ibcon#*before return 0, iclass 6, count 0 2006.260.07:43:49.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:49.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:49.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:43:49.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:43:49.90$vc4f8/va=4,7 2006.260.07:43:49.90#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.07:43:49.90#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.07:43:49.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:49.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:49.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:49.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:49.96#ibcon#enter wrdev, iclass 10, count 2 2006.260.07:43:49.96#ibcon#first serial, iclass 10, count 2 2006.260.07:43:49.96#ibcon#enter sib2, iclass 10, count 2 2006.260.07:43:49.96#ibcon#flushed, iclass 10, count 2 2006.260.07:43:49.96#ibcon#about to write, iclass 10, count 2 2006.260.07:43:49.96#ibcon#wrote, iclass 10, count 2 2006.260.07:43:49.96#ibcon#about to read 3, iclass 10, count 2 2006.260.07:43:49.98#ibcon#read 3, iclass 10, count 2 2006.260.07:43:49.98#ibcon#about to read 4, iclass 10, count 2 2006.260.07:43:49.98#ibcon#read 4, iclass 10, count 2 2006.260.07:43:49.98#ibcon#about to read 5, iclass 10, count 2 2006.260.07:43:49.98#ibcon#read 5, iclass 10, count 2 2006.260.07:43:49.98#ibcon#about to read 6, iclass 10, count 2 2006.260.07:43:49.98#ibcon#read 6, iclass 10, count 2 2006.260.07:43:49.98#ibcon#end of sib2, iclass 10, count 2 2006.260.07:43:49.98#ibcon#*mode == 0, iclass 10, count 2 2006.260.07:43:49.98#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.07:43:49.98#ibcon#[25=AT04-07\r\n] 2006.260.07:43:49.98#ibcon#*before write, iclass 10, count 2 2006.260.07:43:49.98#ibcon#enter sib2, iclass 10, count 2 2006.260.07:43:49.98#ibcon#flushed, iclass 10, count 2 2006.260.07:43:49.98#ibcon#about to write, iclass 10, count 2 2006.260.07:43:49.98#ibcon#wrote, iclass 10, count 2 2006.260.07:43:49.98#ibcon#about to read 3, iclass 10, count 2 2006.260.07:43:50.01#ibcon#read 3, iclass 10, count 2 2006.260.07:43:50.01#ibcon#about to read 4, iclass 10, count 2 2006.260.07:43:50.01#ibcon#read 4, iclass 10, count 2 2006.260.07:43:50.01#ibcon#about to read 5, iclass 10, count 2 2006.260.07:43:50.01#ibcon#read 5, iclass 10, count 2 2006.260.07:43:50.01#ibcon#about to read 6, iclass 10, count 2 2006.260.07:43:50.01#ibcon#read 6, iclass 10, count 2 2006.260.07:43:50.01#ibcon#end of sib2, iclass 10, count 2 2006.260.07:43:50.01#ibcon#*after write, iclass 10, count 2 2006.260.07:43:50.01#ibcon#*before return 0, iclass 10, count 2 2006.260.07:43:50.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:50.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:50.01#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.07:43:50.01#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:50.01#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:50.13#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:50.13#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:50.13#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:43:50.13#ibcon#first serial, iclass 10, count 0 2006.260.07:43:50.13#ibcon#enter sib2, iclass 10, count 0 2006.260.07:43:50.13#ibcon#flushed, iclass 10, count 0 2006.260.07:43:50.13#ibcon#about to write, iclass 10, count 0 2006.260.07:43:50.13#ibcon#wrote, iclass 10, count 0 2006.260.07:43:50.13#ibcon#about to read 3, iclass 10, count 0 2006.260.07:43:50.15#ibcon#read 3, iclass 10, count 0 2006.260.07:43:50.15#ibcon#about to read 4, iclass 10, count 0 2006.260.07:43:50.15#ibcon#read 4, iclass 10, count 0 2006.260.07:43:50.15#ibcon#about to read 5, iclass 10, count 0 2006.260.07:43:50.15#ibcon#read 5, iclass 10, count 0 2006.260.07:43:50.15#ibcon#about to read 6, iclass 10, count 0 2006.260.07:43:50.15#ibcon#read 6, iclass 10, count 0 2006.260.07:43:50.15#ibcon#end of sib2, iclass 10, count 0 2006.260.07:43:50.15#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:43:50.15#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:43:50.15#ibcon#[25=USB\r\n] 2006.260.07:43:50.15#ibcon#*before write, iclass 10, count 0 2006.260.07:43:50.15#ibcon#enter sib2, iclass 10, count 0 2006.260.07:43:50.15#ibcon#flushed, iclass 10, count 0 2006.260.07:43:50.15#ibcon#about to write, iclass 10, count 0 2006.260.07:43:50.15#ibcon#wrote, iclass 10, count 0 2006.260.07:43:50.15#ibcon#about to read 3, iclass 10, count 0 2006.260.07:43:50.18#ibcon#read 3, iclass 10, count 0 2006.260.07:43:50.18#ibcon#about to read 4, iclass 10, count 0 2006.260.07:43:50.18#ibcon#read 4, iclass 10, count 0 2006.260.07:43:50.18#ibcon#about to read 5, iclass 10, count 0 2006.260.07:43:50.18#ibcon#read 5, iclass 10, count 0 2006.260.07:43:50.18#ibcon#about to read 6, iclass 10, count 0 2006.260.07:43:50.18#ibcon#read 6, iclass 10, count 0 2006.260.07:43:50.18#ibcon#end of sib2, iclass 10, count 0 2006.260.07:43:50.18#ibcon#*after write, iclass 10, count 0 2006.260.07:43:50.18#ibcon#*before return 0, iclass 10, count 0 2006.260.07:43:50.18#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:50.18#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:50.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:43:50.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:43:50.18$vc4f8/valo=5,652.99 2006.260.07:43:50.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:43:50.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:43:50.18#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:50.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:50.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:50.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:50.18#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:43:50.18#ibcon#first serial, iclass 12, count 0 2006.260.07:43:50.18#ibcon#enter sib2, iclass 12, count 0 2006.260.07:43:50.18#ibcon#flushed, iclass 12, count 0 2006.260.07:43:50.18#ibcon#about to write, iclass 12, count 0 2006.260.07:43:50.18#ibcon#wrote, iclass 12, count 0 2006.260.07:43:50.18#ibcon#about to read 3, iclass 12, count 0 2006.260.07:43:50.20#ibcon#read 3, iclass 12, count 0 2006.260.07:43:50.20#ibcon#about to read 4, iclass 12, count 0 2006.260.07:43:50.20#ibcon#read 4, iclass 12, count 0 2006.260.07:43:50.20#ibcon#about to read 5, iclass 12, count 0 2006.260.07:43:50.20#ibcon#read 5, iclass 12, count 0 2006.260.07:43:50.20#ibcon#about to read 6, iclass 12, count 0 2006.260.07:43:50.20#ibcon#read 6, iclass 12, count 0 2006.260.07:43:50.20#ibcon#end of sib2, iclass 12, count 0 2006.260.07:43:50.20#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:43:50.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:43:50.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:43:50.20#ibcon#*before write, iclass 12, count 0 2006.260.07:43:50.20#ibcon#enter sib2, iclass 12, count 0 2006.260.07:43:50.20#ibcon#flushed, iclass 12, count 0 2006.260.07:43:50.20#ibcon#about to write, iclass 12, count 0 2006.260.07:43:50.20#ibcon#wrote, iclass 12, count 0 2006.260.07:43:50.20#ibcon#about to read 3, iclass 12, count 0 2006.260.07:43:50.24#ibcon#read 3, iclass 12, count 0 2006.260.07:43:50.24#ibcon#about to read 4, iclass 12, count 0 2006.260.07:43:50.24#ibcon#read 4, iclass 12, count 0 2006.260.07:43:50.24#ibcon#about to read 5, iclass 12, count 0 2006.260.07:43:50.24#ibcon#read 5, iclass 12, count 0 2006.260.07:43:50.24#ibcon#about to read 6, iclass 12, count 0 2006.260.07:43:50.24#ibcon#read 6, iclass 12, count 0 2006.260.07:43:50.24#ibcon#end of sib2, iclass 12, count 0 2006.260.07:43:50.24#ibcon#*after write, iclass 12, count 0 2006.260.07:43:50.24#ibcon#*before return 0, iclass 12, count 0 2006.260.07:43:50.24#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:50.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:50.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:43:50.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:43:50.24$vc4f8/va=5,7 2006.260.07:43:50.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:43:50.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:43:50.24#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:50.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:50.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:50.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:50.30#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:43:50.30#ibcon#first serial, iclass 14, count 2 2006.260.07:43:50.30#ibcon#enter sib2, iclass 14, count 2 2006.260.07:43:50.30#ibcon#flushed, iclass 14, count 2 2006.260.07:43:50.30#ibcon#about to write, iclass 14, count 2 2006.260.07:43:50.30#ibcon#wrote, iclass 14, count 2 2006.260.07:43:50.30#ibcon#about to read 3, iclass 14, count 2 2006.260.07:43:50.32#ibcon#read 3, iclass 14, count 2 2006.260.07:43:50.32#ibcon#about to read 4, iclass 14, count 2 2006.260.07:43:50.32#ibcon#read 4, iclass 14, count 2 2006.260.07:43:50.32#ibcon#about to read 5, iclass 14, count 2 2006.260.07:43:50.32#ibcon#read 5, iclass 14, count 2 2006.260.07:43:50.32#ibcon#about to read 6, iclass 14, count 2 2006.260.07:43:50.32#ibcon#read 6, iclass 14, count 2 2006.260.07:43:50.32#ibcon#end of sib2, iclass 14, count 2 2006.260.07:43:50.32#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:43:50.32#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:43:50.32#ibcon#[25=AT05-07\r\n] 2006.260.07:43:50.32#ibcon#*before write, iclass 14, count 2 2006.260.07:43:50.32#ibcon#enter sib2, iclass 14, count 2 2006.260.07:43:50.32#ibcon#flushed, iclass 14, count 2 2006.260.07:43:50.32#ibcon#about to write, iclass 14, count 2 2006.260.07:43:50.32#ibcon#wrote, iclass 14, count 2 2006.260.07:43:50.32#ibcon#about to read 3, iclass 14, count 2 2006.260.07:43:50.35#ibcon#read 3, iclass 14, count 2 2006.260.07:43:50.35#ibcon#about to read 4, iclass 14, count 2 2006.260.07:43:50.35#ibcon#read 4, iclass 14, count 2 2006.260.07:43:50.35#ibcon#about to read 5, iclass 14, count 2 2006.260.07:43:50.35#ibcon#read 5, iclass 14, count 2 2006.260.07:43:50.35#ibcon#about to read 6, iclass 14, count 2 2006.260.07:43:50.35#ibcon#read 6, iclass 14, count 2 2006.260.07:43:50.35#ibcon#end of sib2, iclass 14, count 2 2006.260.07:43:50.35#ibcon#*after write, iclass 14, count 2 2006.260.07:43:50.35#ibcon#*before return 0, iclass 14, count 2 2006.260.07:43:50.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:50.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:50.35#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:43:50.35#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:50.35#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:50.47#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:50.47#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:50.47#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:43:50.47#ibcon#first serial, iclass 14, count 0 2006.260.07:43:50.47#ibcon#enter sib2, iclass 14, count 0 2006.260.07:43:50.47#ibcon#flushed, iclass 14, count 0 2006.260.07:43:50.47#ibcon#about to write, iclass 14, count 0 2006.260.07:43:50.47#ibcon#wrote, iclass 14, count 0 2006.260.07:43:50.47#ibcon#about to read 3, iclass 14, count 0 2006.260.07:43:50.49#ibcon#read 3, iclass 14, count 0 2006.260.07:43:50.49#ibcon#about to read 4, iclass 14, count 0 2006.260.07:43:50.49#ibcon#read 4, iclass 14, count 0 2006.260.07:43:50.49#ibcon#about to read 5, iclass 14, count 0 2006.260.07:43:50.49#ibcon#read 5, iclass 14, count 0 2006.260.07:43:50.49#ibcon#about to read 6, iclass 14, count 0 2006.260.07:43:50.49#ibcon#read 6, iclass 14, count 0 2006.260.07:43:50.49#ibcon#end of sib2, iclass 14, count 0 2006.260.07:43:50.49#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:43:50.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:43:50.49#ibcon#[25=USB\r\n] 2006.260.07:43:50.49#ibcon#*before write, iclass 14, count 0 2006.260.07:43:50.49#ibcon#enter sib2, iclass 14, count 0 2006.260.07:43:50.49#ibcon#flushed, iclass 14, count 0 2006.260.07:43:50.49#ibcon#about to write, iclass 14, count 0 2006.260.07:43:50.49#ibcon#wrote, iclass 14, count 0 2006.260.07:43:50.49#ibcon#about to read 3, iclass 14, count 0 2006.260.07:43:50.52#ibcon#read 3, iclass 14, count 0 2006.260.07:43:50.52#ibcon#about to read 4, iclass 14, count 0 2006.260.07:43:50.52#ibcon#read 4, iclass 14, count 0 2006.260.07:43:50.52#ibcon#about to read 5, iclass 14, count 0 2006.260.07:43:50.52#ibcon#read 5, iclass 14, count 0 2006.260.07:43:50.52#ibcon#about to read 6, iclass 14, count 0 2006.260.07:43:50.52#ibcon#read 6, iclass 14, count 0 2006.260.07:43:50.52#ibcon#end of sib2, iclass 14, count 0 2006.260.07:43:50.52#ibcon#*after write, iclass 14, count 0 2006.260.07:43:50.52#ibcon#*before return 0, iclass 14, count 0 2006.260.07:43:50.52#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:50.52#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:50.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:43:50.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:43:50.52$vc4f8/valo=6,772.99 2006.260.07:43:50.52#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:43:50.52#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:43:50.52#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:50.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:50.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:50.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:50.52#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:43:50.52#ibcon#first serial, iclass 16, count 0 2006.260.07:43:50.52#ibcon#enter sib2, iclass 16, count 0 2006.260.07:43:50.52#ibcon#flushed, iclass 16, count 0 2006.260.07:43:50.52#ibcon#about to write, iclass 16, count 0 2006.260.07:43:50.52#ibcon#wrote, iclass 16, count 0 2006.260.07:43:50.52#ibcon#about to read 3, iclass 16, count 0 2006.260.07:43:50.54#ibcon#read 3, iclass 16, count 0 2006.260.07:43:50.54#ibcon#about to read 4, iclass 16, count 0 2006.260.07:43:50.54#ibcon#read 4, iclass 16, count 0 2006.260.07:43:50.54#ibcon#about to read 5, iclass 16, count 0 2006.260.07:43:50.54#ibcon#read 5, iclass 16, count 0 2006.260.07:43:50.54#ibcon#about to read 6, iclass 16, count 0 2006.260.07:43:50.54#ibcon#read 6, iclass 16, count 0 2006.260.07:43:50.54#ibcon#end of sib2, iclass 16, count 0 2006.260.07:43:50.54#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:43:50.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:43:50.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:43:50.54#ibcon#*before write, iclass 16, count 0 2006.260.07:43:50.54#ibcon#enter sib2, iclass 16, count 0 2006.260.07:43:50.54#ibcon#flushed, iclass 16, count 0 2006.260.07:43:50.54#ibcon#about to write, iclass 16, count 0 2006.260.07:43:50.54#ibcon#wrote, iclass 16, count 0 2006.260.07:43:50.54#ibcon#about to read 3, iclass 16, count 0 2006.260.07:43:50.58#ibcon#read 3, iclass 16, count 0 2006.260.07:43:50.58#ibcon#about to read 4, iclass 16, count 0 2006.260.07:43:50.58#ibcon#read 4, iclass 16, count 0 2006.260.07:43:50.58#ibcon#about to read 5, iclass 16, count 0 2006.260.07:43:50.58#ibcon#read 5, iclass 16, count 0 2006.260.07:43:50.58#ibcon#about to read 6, iclass 16, count 0 2006.260.07:43:50.58#ibcon#read 6, iclass 16, count 0 2006.260.07:43:50.58#ibcon#end of sib2, iclass 16, count 0 2006.260.07:43:50.58#ibcon#*after write, iclass 16, count 0 2006.260.07:43:50.58#ibcon#*before return 0, iclass 16, count 0 2006.260.07:43:50.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:50.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:50.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:43:50.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:43:50.58$vc4f8/va=6,6 2006.260.07:43:50.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:43:50.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:43:50.58#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:50.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:50.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:50.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:50.64#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:43:50.64#ibcon#first serial, iclass 18, count 2 2006.260.07:43:50.64#ibcon#enter sib2, iclass 18, count 2 2006.260.07:43:50.64#ibcon#flushed, iclass 18, count 2 2006.260.07:43:50.64#ibcon#about to write, iclass 18, count 2 2006.260.07:43:50.64#ibcon#wrote, iclass 18, count 2 2006.260.07:43:50.64#ibcon#about to read 3, iclass 18, count 2 2006.260.07:43:50.66#ibcon#read 3, iclass 18, count 2 2006.260.07:43:50.66#ibcon#about to read 4, iclass 18, count 2 2006.260.07:43:50.66#ibcon#read 4, iclass 18, count 2 2006.260.07:43:50.66#ibcon#about to read 5, iclass 18, count 2 2006.260.07:43:50.66#ibcon#read 5, iclass 18, count 2 2006.260.07:43:50.66#ibcon#about to read 6, iclass 18, count 2 2006.260.07:43:50.66#ibcon#read 6, iclass 18, count 2 2006.260.07:43:50.66#ibcon#end of sib2, iclass 18, count 2 2006.260.07:43:50.66#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:43:50.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:43:50.66#ibcon#[25=AT06-06\r\n] 2006.260.07:43:50.66#ibcon#*before write, iclass 18, count 2 2006.260.07:43:50.66#ibcon#enter sib2, iclass 18, count 2 2006.260.07:43:50.66#ibcon#flushed, iclass 18, count 2 2006.260.07:43:50.66#ibcon#about to write, iclass 18, count 2 2006.260.07:43:50.66#ibcon#wrote, iclass 18, count 2 2006.260.07:43:50.66#ibcon#about to read 3, iclass 18, count 2 2006.260.07:43:50.69#ibcon#read 3, iclass 18, count 2 2006.260.07:43:50.69#ibcon#about to read 4, iclass 18, count 2 2006.260.07:43:50.69#ibcon#read 4, iclass 18, count 2 2006.260.07:43:50.69#ibcon#about to read 5, iclass 18, count 2 2006.260.07:43:50.69#ibcon#read 5, iclass 18, count 2 2006.260.07:43:50.69#ibcon#about to read 6, iclass 18, count 2 2006.260.07:43:50.69#ibcon#read 6, iclass 18, count 2 2006.260.07:43:50.69#ibcon#end of sib2, iclass 18, count 2 2006.260.07:43:50.69#ibcon#*after write, iclass 18, count 2 2006.260.07:43:50.69#ibcon#*before return 0, iclass 18, count 2 2006.260.07:43:50.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:50.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:50.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:43:50.69#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:50.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:50.81#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:50.81#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:50.81#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:43:50.81#ibcon#first serial, iclass 18, count 0 2006.260.07:43:50.81#ibcon#enter sib2, iclass 18, count 0 2006.260.07:43:50.81#ibcon#flushed, iclass 18, count 0 2006.260.07:43:50.81#ibcon#about to write, iclass 18, count 0 2006.260.07:43:50.81#ibcon#wrote, iclass 18, count 0 2006.260.07:43:50.81#ibcon#about to read 3, iclass 18, count 0 2006.260.07:43:50.83#ibcon#read 3, iclass 18, count 0 2006.260.07:43:50.83#ibcon#about to read 4, iclass 18, count 0 2006.260.07:43:50.83#ibcon#read 4, iclass 18, count 0 2006.260.07:43:50.83#ibcon#about to read 5, iclass 18, count 0 2006.260.07:43:50.83#ibcon#read 5, iclass 18, count 0 2006.260.07:43:50.83#ibcon#about to read 6, iclass 18, count 0 2006.260.07:43:50.83#ibcon#read 6, iclass 18, count 0 2006.260.07:43:50.83#ibcon#end of sib2, iclass 18, count 0 2006.260.07:43:50.83#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:43:50.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:43:50.83#ibcon#[25=USB\r\n] 2006.260.07:43:50.83#ibcon#*before write, iclass 18, count 0 2006.260.07:43:50.83#ibcon#enter sib2, iclass 18, count 0 2006.260.07:43:50.83#ibcon#flushed, iclass 18, count 0 2006.260.07:43:50.83#ibcon#about to write, iclass 18, count 0 2006.260.07:43:50.83#ibcon#wrote, iclass 18, count 0 2006.260.07:43:50.83#ibcon#about to read 3, iclass 18, count 0 2006.260.07:43:50.86#ibcon#read 3, iclass 18, count 0 2006.260.07:43:50.86#ibcon#about to read 4, iclass 18, count 0 2006.260.07:43:50.86#ibcon#read 4, iclass 18, count 0 2006.260.07:43:50.86#ibcon#about to read 5, iclass 18, count 0 2006.260.07:43:50.86#ibcon#read 5, iclass 18, count 0 2006.260.07:43:50.86#ibcon#about to read 6, iclass 18, count 0 2006.260.07:43:50.86#ibcon#read 6, iclass 18, count 0 2006.260.07:43:50.86#ibcon#end of sib2, iclass 18, count 0 2006.260.07:43:50.86#ibcon#*after write, iclass 18, count 0 2006.260.07:43:50.86#ibcon#*before return 0, iclass 18, count 0 2006.260.07:43:50.86#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:50.86#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:50.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:43:50.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:43:50.86$vc4f8/valo=7,832.99 2006.260.07:43:50.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:43:50.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:43:50.86#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:50.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:50.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:50.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:50.86#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:43:50.86#ibcon#first serial, iclass 20, count 0 2006.260.07:43:50.86#ibcon#enter sib2, iclass 20, count 0 2006.260.07:43:50.86#ibcon#flushed, iclass 20, count 0 2006.260.07:43:50.86#ibcon#about to write, iclass 20, count 0 2006.260.07:43:50.86#ibcon#wrote, iclass 20, count 0 2006.260.07:43:50.86#ibcon#about to read 3, iclass 20, count 0 2006.260.07:43:50.88#ibcon#read 3, iclass 20, count 0 2006.260.07:43:50.88#ibcon#about to read 4, iclass 20, count 0 2006.260.07:43:50.88#ibcon#read 4, iclass 20, count 0 2006.260.07:43:50.88#ibcon#about to read 5, iclass 20, count 0 2006.260.07:43:50.88#ibcon#read 5, iclass 20, count 0 2006.260.07:43:50.88#ibcon#about to read 6, iclass 20, count 0 2006.260.07:43:50.88#ibcon#read 6, iclass 20, count 0 2006.260.07:43:50.88#ibcon#end of sib2, iclass 20, count 0 2006.260.07:43:50.88#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:43:50.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:43:50.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:43:50.88#ibcon#*before write, iclass 20, count 0 2006.260.07:43:50.88#ibcon#enter sib2, iclass 20, count 0 2006.260.07:43:50.88#ibcon#flushed, iclass 20, count 0 2006.260.07:43:50.88#ibcon#about to write, iclass 20, count 0 2006.260.07:43:50.88#ibcon#wrote, iclass 20, count 0 2006.260.07:43:50.88#ibcon#about to read 3, iclass 20, count 0 2006.260.07:43:50.92#ibcon#read 3, iclass 20, count 0 2006.260.07:43:50.92#ibcon#about to read 4, iclass 20, count 0 2006.260.07:43:50.92#ibcon#read 4, iclass 20, count 0 2006.260.07:43:50.92#ibcon#about to read 5, iclass 20, count 0 2006.260.07:43:50.92#ibcon#read 5, iclass 20, count 0 2006.260.07:43:50.92#ibcon#about to read 6, iclass 20, count 0 2006.260.07:43:50.92#ibcon#read 6, iclass 20, count 0 2006.260.07:43:50.92#ibcon#end of sib2, iclass 20, count 0 2006.260.07:43:50.92#ibcon#*after write, iclass 20, count 0 2006.260.07:43:50.92#ibcon#*before return 0, iclass 20, count 0 2006.260.07:43:50.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:50.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:50.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:43:50.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:43:50.92$vc4f8/va=7,6 2006.260.07:43:50.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:43:50.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:43:50.92#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:50.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:50.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:50.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:50.98#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:43:50.98#ibcon#first serial, iclass 22, count 2 2006.260.07:43:50.98#ibcon#enter sib2, iclass 22, count 2 2006.260.07:43:50.98#ibcon#flushed, iclass 22, count 2 2006.260.07:43:50.98#ibcon#about to write, iclass 22, count 2 2006.260.07:43:50.98#ibcon#wrote, iclass 22, count 2 2006.260.07:43:50.98#ibcon#about to read 3, iclass 22, count 2 2006.260.07:43:51.00#ibcon#read 3, iclass 22, count 2 2006.260.07:43:51.00#ibcon#about to read 4, iclass 22, count 2 2006.260.07:43:51.00#ibcon#read 4, iclass 22, count 2 2006.260.07:43:51.00#ibcon#about to read 5, iclass 22, count 2 2006.260.07:43:51.00#ibcon#read 5, iclass 22, count 2 2006.260.07:43:51.00#ibcon#about to read 6, iclass 22, count 2 2006.260.07:43:51.00#ibcon#read 6, iclass 22, count 2 2006.260.07:43:51.00#ibcon#end of sib2, iclass 22, count 2 2006.260.07:43:51.00#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:43:51.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:43:51.00#ibcon#[25=AT07-06\r\n] 2006.260.07:43:51.00#ibcon#*before write, iclass 22, count 2 2006.260.07:43:51.00#ibcon#enter sib2, iclass 22, count 2 2006.260.07:43:51.00#ibcon#flushed, iclass 22, count 2 2006.260.07:43:51.00#ibcon#about to write, iclass 22, count 2 2006.260.07:43:51.00#ibcon#wrote, iclass 22, count 2 2006.260.07:43:51.00#ibcon#about to read 3, iclass 22, count 2 2006.260.07:43:51.03#ibcon#read 3, iclass 22, count 2 2006.260.07:43:51.03#ibcon#about to read 4, iclass 22, count 2 2006.260.07:43:51.03#ibcon#read 4, iclass 22, count 2 2006.260.07:43:51.03#ibcon#about to read 5, iclass 22, count 2 2006.260.07:43:51.03#ibcon#read 5, iclass 22, count 2 2006.260.07:43:51.03#ibcon#about to read 6, iclass 22, count 2 2006.260.07:43:51.03#ibcon#read 6, iclass 22, count 2 2006.260.07:43:51.03#ibcon#end of sib2, iclass 22, count 2 2006.260.07:43:51.03#ibcon#*after write, iclass 22, count 2 2006.260.07:43:51.03#ibcon#*before return 0, iclass 22, count 2 2006.260.07:43:51.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:51.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:51.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:43:51.03#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:51.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:43:51.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:43:51.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:43:51.15#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:43:51.15#ibcon#first serial, iclass 22, count 0 2006.260.07:43:51.15#ibcon#enter sib2, iclass 22, count 0 2006.260.07:43:51.15#ibcon#flushed, iclass 22, count 0 2006.260.07:43:51.15#ibcon#about to write, iclass 22, count 0 2006.260.07:43:51.15#ibcon#wrote, iclass 22, count 0 2006.260.07:43:51.15#ibcon#about to read 3, iclass 22, count 0 2006.260.07:43:51.17#ibcon#read 3, iclass 22, count 0 2006.260.07:43:51.17#ibcon#about to read 4, iclass 22, count 0 2006.260.07:43:51.17#ibcon#read 4, iclass 22, count 0 2006.260.07:43:51.17#ibcon#about to read 5, iclass 22, count 0 2006.260.07:43:51.17#ibcon#read 5, iclass 22, count 0 2006.260.07:43:51.17#ibcon#about to read 6, iclass 22, count 0 2006.260.07:43:51.17#ibcon#read 6, iclass 22, count 0 2006.260.07:43:51.17#ibcon#end of sib2, iclass 22, count 0 2006.260.07:43:51.17#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:43:51.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:43:51.17#ibcon#[25=USB\r\n] 2006.260.07:43:51.17#ibcon#*before write, iclass 22, count 0 2006.260.07:43:51.17#ibcon#enter sib2, iclass 22, count 0 2006.260.07:43:51.17#ibcon#flushed, iclass 22, count 0 2006.260.07:43:51.17#ibcon#about to write, iclass 22, count 0 2006.260.07:43:51.17#ibcon#wrote, iclass 22, count 0 2006.260.07:43:51.17#ibcon#about to read 3, iclass 22, count 0 2006.260.07:43:51.20#ibcon#read 3, iclass 22, count 0 2006.260.07:43:51.20#ibcon#about to read 4, iclass 22, count 0 2006.260.07:43:51.20#ibcon#read 4, iclass 22, count 0 2006.260.07:43:51.20#ibcon#about to read 5, iclass 22, count 0 2006.260.07:43:51.20#ibcon#read 5, iclass 22, count 0 2006.260.07:43:51.20#ibcon#about to read 6, iclass 22, count 0 2006.260.07:43:51.20#ibcon#read 6, iclass 22, count 0 2006.260.07:43:51.20#ibcon#end of sib2, iclass 22, count 0 2006.260.07:43:51.20#ibcon#*after write, iclass 22, count 0 2006.260.07:43:51.20#ibcon#*before return 0, iclass 22, count 0 2006.260.07:43:51.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:43:51.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:43:51.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:43:51.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:43:51.20$vc4f8/valo=8,852.99 2006.260.07:43:51.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:43:51.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:43:51.20#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:51.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:43:51.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:43:51.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:43:51.20#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:43:51.20#ibcon#first serial, iclass 24, count 0 2006.260.07:43:51.20#ibcon#enter sib2, iclass 24, count 0 2006.260.07:43:51.20#ibcon#flushed, iclass 24, count 0 2006.260.07:43:51.20#ibcon#about to write, iclass 24, count 0 2006.260.07:43:51.20#ibcon#wrote, iclass 24, count 0 2006.260.07:43:51.20#ibcon#about to read 3, iclass 24, count 0 2006.260.07:43:51.22#ibcon#read 3, iclass 24, count 0 2006.260.07:43:51.22#ibcon#about to read 4, iclass 24, count 0 2006.260.07:43:51.22#ibcon#read 4, iclass 24, count 0 2006.260.07:43:51.22#ibcon#about to read 5, iclass 24, count 0 2006.260.07:43:51.22#ibcon#read 5, iclass 24, count 0 2006.260.07:43:51.22#ibcon#about to read 6, iclass 24, count 0 2006.260.07:43:51.22#ibcon#read 6, iclass 24, count 0 2006.260.07:43:51.22#ibcon#end of sib2, iclass 24, count 0 2006.260.07:43:51.22#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:43:51.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:43:51.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:43:51.22#ibcon#*before write, iclass 24, count 0 2006.260.07:43:51.22#ibcon#enter sib2, iclass 24, count 0 2006.260.07:43:51.22#ibcon#flushed, iclass 24, count 0 2006.260.07:43:51.22#ibcon#about to write, iclass 24, count 0 2006.260.07:43:51.22#ibcon#wrote, iclass 24, count 0 2006.260.07:43:51.22#ibcon#about to read 3, iclass 24, count 0 2006.260.07:43:51.26#ibcon#read 3, iclass 24, count 0 2006.260.07:43:51.26#ibcon#about to read 4, iclass 24, count 0 2006.260.07:43:51.26#ibcon#read 4, iclass 24, count 0 2006.260.07:43:51.26#ibcon#about to read 5, iclass 24, count 0 2006.260.07:43:51.26#ibcon#read 5, iclass 24, count 0 2006.260.07:43:51.26#ibcon#about to read 6, iclass 24, count 0 2006.260.07:43:51.26#ibcon#read 6, iclass 24, count 0 2006.260.07:43:51.26#ibcon#end of sib2, iclass 24, count 0 2006.260.07:43:51.26#ibcon#*after write, iclass 24, count 0 2006.260.07:43:51.26#ibcon#*before return 0, iclass 24, count 0 2006.260.07:43:51.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:43:51.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:43:51.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:43:51.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:43:51.26$vc4f8/va=8,6 2006.260.07:43:51.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.07:43:51.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.07:43:51.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:51.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:43:51.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:43:51.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:43:51.32#ibcon#enter wrdev, iclass 26, count 2 2006.260.07:43:51.32#ibcon#first serial, iclass 26, count 2 2006.260.07:43:51.32#ibcon#enter sib2, iclass 26, count 2 2006.260.07:43:51.32#ibcon#flushed, iclass 26, count 2 2006.260.07:43:51.32#ibcon#about to write, iclass 26, count 2 2006.260.07:43:51.32#ibcon#wrote, iclass 26, count 2 2006.260.07:43:51.32#ibcon#about to read 3, iclass 26, count 2 2006.260.07:43:51.34#ibcon#read 3, iclass 26, count 2 2006.260.07:43:51.34#ibcon#about to read 4, iclass 26, count 2 2006.260.07:43:51.34#ibcon#read 4, iclass 26, count 2 2006.260.07:43:51.34#ibcon#about to read 5, iclass 26, count 2 2006.260.07:43:51.34#ibcon#read 5, iclass 26, count 2 2006.260.07:43:51.34#ibcon#about to read 6, iclass 26, count 2 2006.260.07:43:51.34#ibcon#read 6, iclass 26, count 2 2006.260.07:43:51.34#ibcon#end of sib2, iclass 26, count 2 2006.260.07:43:51.34#ibcon#*mode == 0, iclass 26, count 2 2006.260.07:43:51.34#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.07:43:51.34#ibcon#[25=AT08-06\r\n] 2006.260.07:43:51.34#ibcon#*before write, iclass 26, count 2 2006.260.07:43:51.34#ibcon#enter sib2, iclass 26, count 2 2006.260.07:43:51.34#ibcon#flushed, iclass 26, count 2 2006.260.07:43:51.34#ibcon#about to write, iclass 26, count 2 2006.260.07:43:51.34#ibcon#wrote, iclass 26, count 2 2006.260.07:43:51.34#ibcon#about to read 3, iclass 26, count 2 2006.260.07:43:51.37#ibcon#read 3, iclass 26, count 2 2006.260.07:43:51.37#ibcon#about to read 4, iclass 26, count 2 2006.260.07:43:51.37#ibcon#read 4, iclass 26, count 2 2006.260.07:43:51.37#ibcon#about to read 5, iclass 26, count 2 2006.260.07:43:51.37#ibcon#read 5, iclass 26, count 2 2006.260.07:43:51.37#ibcon#about to read 6, iclass 26, count 2 2006.260.07:43:51.37#ibcon#read 6, iclass 26, count 2 2006.260.07:43:51.37#ibcon#end of sib2, iclass 26, count 2 2006.260.07:43:51.37#ibcon#*after write, iclass 26, count 2 2006.260.07:43:51.37#ibcon#*before return 0, iclass 26, count 2 2006.260.07:43:51.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:43:51.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:43:51.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.07:43:51.37#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:51.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:43:51.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:43:51.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:43:51.49#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:43:51.49#ibcon#first serial, iclass 26, count 0 2006.260.07:43:51.49#ibcon#enter sib2, iclass 26, count 0 2006.260.07:43:51.49#ibcon#flushed, iclass 26, count 0 2006.260.07:43:51.49#ibcon#about to write, iclass 26, count 0 2006.260.07:43:51.49#ibcon#wrote, iclass 26, count 0 2006.260.07:43:51.49#ibcon#about to read 3, iclass 26, count 0 2006.260.07:43:51.51#ibcon#read 3, iclass 26, count 0 2006.260.07:43:51.51#ibcon#about to read 4, iclass 26, count 0 2006.260.07:43:51.51#ibcon#read 4, iclass 26, count 0 2006.260.07:43:51.51#ibcon#about to read 5, iclass 26, count 0 2006.260.07:43:51.51#ibcon#read 5, iclass 26, count 0 2006.260.07:43:51.51#ibcon#about to read 6, iclass 26, count 0 2006.260.07:43:51.51#ibcon#read 6, iclass 26, count 0 2006.260.07:43:51.51#ibcon#end of sib2, iclass 26, count 0 2006.260.07:43:51.51#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:43:51.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:43:51.51#ibcon#[25=USB\r\n] 2006.260.07:43:51.51#ibcon#*before write, iclass 26, count 0 2006.260.07:43:51.51#ibcon#enter sib2, iclass 26, count 0 2006.260.07:43:51.51#ibcon#flushed, iclass 26, count 0 2006.260.07:43:51.51#ibcon#about to write, iclass 26, count 0 2006.260.07:43:51.51#ibcon#wrote, iclass 26, count 0 2006.260.07:43:51.51#ibcon#about to read 3, iclass 26, count 0 2006.260.07:43:51.54#ibcon#read 3, iclass 26, count 0 2006.260.07:43:51.54#ibcon#about to read 4, iclass 26, count 0 2006.260.07:43:51.54#ibcon#read 4, iclass 26, count 0 2006.260.07:43:51.54#ibcon#about to read 5, iclass 26, count 0 2006.260.07:43:51.54#ibcon#read 5, iclass 26, count 0 2006.260.07:43:51.54#ibcon#about to read 6, iclass 26, count 0 2006.260.07:43:51.54#ibcon#read 6, iclass 26, count 0 2006.260.07:43:51.54#ibcon#end of sib2, iclass 26, count 0 2006.260.07:43:51.54#ibcon#*after write, iclass 26, count 0 2006.260.07:43:51.54#ibcon#*before return 0, iclass 26, count 0 2006.260.07:43:51.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:43:51.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:43:51.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:43:51.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:43:51.54$vc4f8/vblo=1,632.99 2006.260.07:43:51.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:43:51.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:43:51.54#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:51.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:43:51.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:43:51.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:43:51.54#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:43:51.54#ibcon#first serial, iclass 28, count 0 2006.260.07:43:51.54#ibcon#enter sib2, iclass 28, count 0 2006.260.07:43:51.54#ibcon#flushed, iclass 28, count 0 2006.260.07:43:51.54#ibcon#about to write, iclass 28, count 0 2006.260.07:43:51.54#ibcon#wrote, iclass 28, count 0 2006.260.07:43:51.54#ibcon#about to read 3, iclass 28, count 0 2006.260.07:43:51.56#ibcon#read 3, iclass 28, count 0 2006.260.07:43:51.56#ibcon#about to read 4, iclass 28, count 0 2006.260.07:43:51.56#ibcon#read 4, iclass 28, count 0 2006.260.07:43:51.56#ibcon#about to read 5, iclass 28, count 0 2006.260.07:43:51.56#ibcon#read 5, iclass 28, count 0 2006.260.07:43:51.56#ibcon#about to read 6, iclass 28, count 0 2006.260.07:43:51.56#ibcon#read 6, iclass 28, count 0 2006.260.07:43:51.56#ibcon#end of sib2, iclass 28, count 0 2006.260.07:43:51.56#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:43:51.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:43:51.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:43:51.56#ibcon#*before write, iclass 28, count 0 2006.260.07:43:51.56#ibcon#enter sib2, iclass 28, count 0 2006.260.07:43:51.56#ibcon#flushed, iclass 28, count 0 2006.260.07:43:51.56#ibcon#about to write, iclass 28, count 0 2006.260.07:43:51.56#ibcon#wrote, iclass 28, count 0 2006.260.07:43:51.56#ibcon#about to read 3, iclass 28, count 0 2006.260.07:43:51.60#ibcon#read 3, iclass 28, count 0 2006.260.07:43:51.60#ibcon#about to read 4, iclass 28, count 0 2006.260.07:43:51.60#ibcon#read 4, iclass 28, count 0 2006.260.07:43:51.60#ibcon#about to read 5, iclass 28, count 0 2006.260.07:43:51.60#ibcon#read 5, iclass 28, count 0 2006.260.07:43:51.60#ibcon#about to read 6, iclass 28, count 0 2006.260.07:43:51.60#ibcon#read 6, iclass 28, count 0 2006.260.07:43:51.60#ibcon#end of sib2, iclass 28, count 0 2006.260.07:43:51.60#ibcon#*after write, iclass 28, count 0 2006.260.07:43:51.60#ibcon#*before return 0, iclass 28, count 0 2006.260.07:43:51.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:43:51.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:43:51.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:43:51.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:43:51.60$vc4f8/vb=1,4 2006.260.07:43:51.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.07:43:51.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.07:43:51.60#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:51.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:43:51.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:43:51.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:43:51.60#ibcon#enter wrdev, iclass 30, count 2 2006.260.07:43:51.60#ibcon#first serial, iclass 30, count 2 2006.260.07:43:51.60#ibcon#enter sib2, iclass 30, count 2 2006.260.07:43:51.60#ibcon#flushed, iclass 30, count 2 2006.260.07:43:51.60#ibcon#about to write, iclass 30, count 2 2006.260.07:43:51.60#ibcon#wrote, iclass 30, count 2 2006.260.07:43:51.60#ibcon#about to read 3, iclass 30, count 2 2006.260.07:43:51.62#ibcon#read 3, iclass 30, count 2 2006.260.07:43:51.62#ibcon#about to read 4, iclass 30, count 2 2006.260.07:43:51.62#ibcon#read 4, iclass 30, count 2 2006.260.07:43:51.62#ibcon#about to read 5, iclass 30, count 2 2006.260.07:43:51.62#ibcon#read 5, iclass 30, count 2 2006.260.07:43:51.62#ibcon#about to read 6, iclass 30, count 2 2006.260.07:43:51.62#ibcon#read 6, iclass 30, count 2 2006.260.07:43:51.62#ibcon#end of sib2, iclass 30, count 2 2006.260.07:43:51.62#ibcon#*mode == 0, iclass 30, count 2 2006.260.07:43:51.62#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.07:43:51.62#ibcon#[27=AT01-04\r\n] 2006.260.07:43:51.62#ibcon#*before write, iclass 30, count 2 2006.260.07:43:51.62#ibcon#enter sib2, iclass 30, count 2 2006.260.07:43:51.62#ibcon#flushed, iclass 30, count 2 2006.260.07:43:51.62#ibcon#about to write, iclass 30, count 2 2006.260.07:43:51.62#ibcon#wrote, iclass 30, count 2 2006.260.07:43:51.62#ibcon#about to read 3, iclass 30, count 2 2006.260.07:43:51.65#ibcon#read 3, iclass 30, count 2 2006.260.07:43:51.65#ibcon#about to read 4, iclass 30, count 2 2006.260.07:43:51.65#ibcon#read 4, iclass 30, count 2 2006.260.07:43:51.65#ibcon#about to read 5, iclass 30, count 2 2006.260.07:43:51.65#ibcon#read 5, iclass 30, count 2 2006.260.07:43:51.65#ibcon#about to read 6, iclass 30, count 2 2006.260.07:43:51.65#ibcon#read 6, iclass 30, count 2 2006.260.07:43:51.65#ibcon#end of sib2, iclass 30, count 2 2006.260.07:43:51.65#ibcon#*after write, iclass 30, count 2 2006.260.07:43:51.65#ibcon#*before return 0, iclass 30, count 2 2006.260.07:43:51.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:43:51.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:43:51.65#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.07:43:51.65#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:51.65#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:43:51.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:43:51.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:43:51.77#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:43:51.77#ibcon#first serial, iclass 30, count 0 2006.260.07:43:51.77#ibcon#enter sib2, iclass 30, count 0 2006.260.07:43:51.77#ibcon#flushed, iclass 30, count 0 2006.260.07:43:51.77#ibcon#about to write, iclass 30, count 0 2006.260.07:43:51.77#ibcon#wrote, iclass 30, count 0 2006.260.07:43:51.77#ibcon#about to read 3, iclass 30, count 0 2006.260.07:43:51.79#ibcon#read 3, iclass 30, count 0 2006.260.07:43:51.79#ibcon#about to read 4, iclass 30, count 0 2006.260.07:43:51.79#ibcon#read 4, iclass 30, count 0 2006.260.07:43:51.79#ibcon#about to read 5, iclass 30, count 0 2006.260.07:43:51.79#ibcon#read 5, iclass 30, count 0 2006.260.07:43:51.79#ibcon#about to read 6, iclass 30, count 0 2006.260.07:43:51.79#ibcon#read 6, iclass 30, count 0 2006.260.07:43:51.79#ibcon#end of sib2, iclass 30, count 0 2006.260.07:43:51.79#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:43:51.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:43:51.79#ibcon#[27=USB\r\n] 2006.260.07:43:51.79#ibcon#*before write, iclass 30, count 0 2006.260.07:43:51.79#ibcon#enter sib2, iclass 30, count 0 2006.260.07:43:51.79#ibcon#flushed, iclass 30, count 0 2006.260.07:43:51.79#ibcon#about to write, iclass 30, count 0 2006.260.07:43:51.79#ibcon#wrote, iclass 30, count 0 2006.260.07:43:51.79#ibcon#about to read 3, iclass 30, count 0 2006.260.07:43:51.82#ibcon#read 3, iclass 30, count 0 2006.260.07:43:51.82#ibcon#about to read 4, iclass 30, count 0 2006.260.07:43:51.82#ibcon#read 4, iclass 30, count 0 2006.260.07:43:51.82#ibcon#about to read 5, iclass 30, count 0 2006.260.07:43:51.82#ibcon#read 5, iclass 30, count 0 2006.260.07:43:51.82#ibcon#about to read 6, iclass 30, count 0 2006.260.07:43:51.82#ibcon#read 6, iclass 30, count 0 2006.260.07:43:51.82#ibcon#end of sib2, iclass 30, count 0 2006.260.07:43:51.82#ibcon#*after write, iclass 30, count 0 2006.260.07:43:51.82#ibcon#*before return 0, iclass 30, count 0 2006.260.07:43:51.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:43:51.82#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:43:51.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:43:51.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:43:51.82$vc4f8/vblo=2,640.99 2006.260.07:43:51.82#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:43:51.82#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:43:51.82#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:51.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:51.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:51.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:51.82#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:43:51.82#ibcon#first serial, iclass 32, count 0 2006.260.07:43:51.82#ibcon#enter sib2, iclass 32, count 0 2006.260.07:43:51.82#ibcon#flushed, iclass 32, count 0 2006.260.07:43:51.82#ibcon#about to write, iclass 32, count 0 2006.260.07:43:51.82#ibcon#wrote, iclass 32, count 0 2006.260.07:43:51.82#ibcon#about to read 3, iclass 32, count 0 2006.260.07:43:51.84#ibcon#read 3, iclass 32, count 0 2006.260.07:43:51.84#ibcon#about to read 4, iclass 32, count 0 2006.260.07:43:51.84#ibcon#read 4, iclass 32, count 0 2006.260.07:43:51.84#ibcon#about to read 5, iclass 32, count 0 2006.260.07:43:51.84#ibcon#read 5, iclass 32, count 0 2006.260.07:43:51.84#ibcon#about to read 6, iclass 32, count 0 2006.260.07:43:51.84#ibcon#read 6, iclass 32, count 0 2006.260.07:43:51.84#ibcon#end of sib2, iclass 32, count 0 2006.260.07:43:51.84#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:43:51.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:43:51.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:43:51.84#ibcon#*before write, iclass 32, count 0 2006.260.07:43:51.84#ibcon#enter sib2, iclass 32, count 0 2006.260.07:43:51.84#ibcon#flushed, iclass 32, count 0 2006.260.07:43:51.84#ibcon#about to write, iclass 32, count 0 2006.260.07:43:51.84#ibcon#wrote, iclass 32, count 0 2006.260.07:43:51.84#ibcon#about to read 3, iclass 32, count 0 2006.260.07:43:51.88#ibcon#read 3, iclass 32, count 0 2006.260.07:43:51.88#ibcon#about to read 4, iclass 32, count 0 2006.260.07:43:51.88#ibcon#read 4, iclass 32, count 0 2006.260.07:43:51.88#ibcon#about to read 5, iclass 32, count 0 2006.260.07:43:51.88#ibcon#read 5, iclass 32, count 0 2006.260.07:43:51.88#ibcon#about to read 6, iclass 32, count 0 2006.260.07:43:51.88#ibcon#read 6, iclass 32, count 0 2006.260.07:43:51.88#ibcon#end of sib2, iclass 32, count 0 2006.260.07:43:51.88#ibcon#*after write, iclass 32, count 0 2006.260.07:43:51.88#ibcon#*before return 0, iclass 32, count 0 2006.260.07:43:51.88#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:51.88#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:43:51.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:43:51.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:43:51.88$vc4f8/vb=2,5 2006.260.07:43:51.88#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.07:43:51.88#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.07:43:51.88#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:51.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:51.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:51.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:51.94#ibcon#enter wrdev, iclass 34, count 2 2006.260.07:43:51.94#ibcon#first serial, iclass 34, count 2 2006.260.07:43:51.94#ibcon#enter sib2, iclass 34, count 2 2006.260.07:43:51.94#ibcon#flushed, iclass 34, count 2 2006.260.07:43:51.94#ibcon#about to write, iclass 34, count 2 2006.260.07:43:51.94#ibcon#wrote, iclass 34, count 2 2006.260.07:43:51.94#ibcon#about to read 3, iclass 34, count 2 2006.260.07:43:51.96#ibcon#read 3, iclass 34, count 2 2006.260.07:43:51.96#ibcon#about to read 4, iclass 34, count 2 2006.260.07:43:51.96#ibcon#read 4, iclass 34, count 2 2006.260.07:43:51.96#ibcon#about to read 5, iclass 34, count 2 2006.260.07:43:51.96#ibcon#read 5, iclass 34, count 2 2006.260.07:43:51.96#ibcon#about to read 6, iclass 34, count 2 2006.260.07:43:51.96#ibcon#read 6, iclass 34, count 2 2006.260.07:43:51.96#ibcon#end of sib2, iclass 34, count 2 2006.260.07:43:51.96#ibcon#*mode == 0, iclass 34, count 2 2006.260.07:43:51.96#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.07:43:51.96#ibcon#[27=AT02-05\r\n] 2006.260.07:43:51.96#ibcon#*before write, iclass 34, count 2 2006.260.07:43:51.96#ibcon#enter sib2, iclass 34, count 2 2006.260.07:43:51.96#ibcon#flushed, iclass 34, count 2 2006.260.07:43:51.96#ibcon#about to write, iclass 34, count 2 2006.260.07:43:51.96#ibcon#wrote, iclass 34, count 2 2006.260.07:43:51.96#ibcon#about to read 3, iclass 34, count 2 2006.260.07:43:51.99#ibcon#read 3, iclass 34, count 2 2006.260.07:43:51.99#ibcon#about to read 4, iclass 34, count 2 2006.260.07:43:51.99#ibcon#read 4, iclass 34, count 2 2006.260.07:43:51.99#ibcon#about to read 5, iclass 34, count 2 2006.260.07:43:51.99#ibcon#read 5, iclass 34, count 2 2006.260.07:43:51.99#ibcon#about to read 6, iclass 34, count 2 2006.260.07:43:51.99#ibcon#read 6, iclass 34, count 2 2006.260.07:43:51.99#ibcon#end of sib2, iclass 34, count 2 2006.260.07:43:51.99#ibcon#*after write, iclass 34, count 2 2006.260.07:43:51.99#ibcon#*before return 0, iclass 34, count 2 2006.260.07:43:51.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:51.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:43:51.99#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.07:43:51.99#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:51.99#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:52.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:52.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:52.11#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:43:52.11#ibcon#first serial, iclass 34, count 0 2006.260.07:43:52.11#ibcon#enter sib2, iclass 34, count 0 2006.260.07:43:52.11#ibcon#flushed, iclass 34, count 0 2006.260.07:43:52.11#ibcon#about to write, iclass 34, count 0 2006.260.07:43:52.11#ibcon#wrote, iclass 34, count 0 2006.260.07:43:52.11#ibcon#about to read 3, iclass 34, count 0 2006.260.07:43:52.13#ibcon#read 3, iclass 34, count 0 2006.260.07:43:52.13#ibcon#about to read 4, iclass 34, count 0 2006.260.07:43:52.13#ibcon#read 4, iclass 34, count 0 2006.260.07:43:52.13#ibcon#about to read 5, iclass 34, count 0 2006.260.07:43:52.13#ibcon#read 5, iclass 34, count 0 2006.260.07:43:52.13#ibcon#about to read 6, iclass 34, count 0 2006.260.07:43:52.13#ibcon#read 6, iclass 34, count 0 2006.260.07:43:52.13#ibcon#end of sib2, iclass 34, count 0 2006.260.07:43:52.13#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:43:52.13#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:43:52.13#ibcon#[27=USB\r\n] 2006.260.07:43:52.13#ibcon#*before write, iclass 34, count 0 2006.260.07:43:52.13#ibcon#enter sib2, iclass 34, count 0 2006.260.07:43:52.13#ibcon#flushed, iclass 34, count 0 2006.260.07:43:52.13#ibcon#about to write, iclass 34, count 0 2006.260.07:43:52.13#ibcon#wrote, iclass 34, count 0 2006.260.07:43:52.13#ibcon#about to read 3, iclass 34, count 0 2006.260.07:43:52.16#ibcon#read 3, iclass 34, count 0 2006.260.07:43:52.16#ibcon#about to read 4, iclass 34, count 0 2006.260.07:43:52.16#ibcon#read 4, iclass 34, count 0 2006.260.07:43:52.16#ibcon#about to read 5, iclass 34, count 0 2006.260.07:43:52.16#ibcon#read 5, iclass 34, count 0 2006.260.07:43:52.16#ibcon#about to read 6, iclass 34, count 0 2006.260.07:43:52.16#ibcon#read 6, iclass 34, count 0 2006.260.07:43:52.16#ibcon#end of sib2, iclass 34, count 0 2006.260.07:43:52.16#ibcon#*after write, iclass 34, count 0 2006.260.07:43:52.16#ibcon#*before return 0, iclass 34, count 0 2006.260.07:43:52.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:52.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:43:52.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:43:52.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:43:52.16$vc4f8/vblo=3,656.99 2006.260.07:43:52.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.07:43:52.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.07:43:52.16#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:52.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:52.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:52.16#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:52.16#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:43:52.16#ibcon#first serial, iclass 36, count 0 2006.260.07:43:52.16#ibcon#enter sib2, iclass 36, count 0 2006.260.07:43:52.16#ibcon#flushed, iclass 36, count 0 2006.260.07:43:52.16#ibcon#about to write, iclass 36, count 0 2006.260.07:43:52.16#ibcon#wrote, iclass 36, count 0 2006.260.07:43:52.16#ibcon#about to read 3, iclass 36, count 0 2006.260.07:43:52.18#ibcon#read 3, iclass 36, count 0 2006.260.07:43:52.18#ibcon#about to read 4, iclass 36, count 0 2006.260.07:43:52.18#ibcon#read 4, iclass 36, count 0 2006.260.07:43:52.18#ibcon#about to read 5, iclass 36, count 0 2006.260.07:43:52.18#ibcon#read 5, iclass 36, count 0 2006.260.07:43:52.18#ibcon#about to read 6, iclass 36, count 0 2006.260.07:43:52.18#ibcon#read 6, iclass 36, count 0 2006.260.07:43:52.18#ibcon#end of sib2, iclass 36, count 0 2006.260.07:43:52.18#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:43:52.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:43:52.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:43:52.18#ibcon#*before write, iclass 36, count 0 2006.260.07:43:52.18#ibcon#enter sib2, iclass 36, count 0 2006.260.07:43:52.18#ibcon#flushed, iclass 36, count 0 2006.260.07:43:52.18#ibcon#about to write, iclass 36, count 0 2006.260.07:43:52.18#ibcon#wrote, iclass 36, count 0 2006.260.07:43:52.18#ibcon#about to read 3, iclass 36, count 0 2006.260.07:43:52.22#ibcon#read 3, iclass 36, count 0 2006.260.07:43:52.22#ibcon#about to read 4, iclass 36, count 0 2006.260.07:43:52.22#ibcon#read 4, iclass 36, count 0 2006.260.07:43:52.22#ibcon#about to read 5, iclass 36, count 0 2006.260.07:43:52.22#ibcon#read 5, iclass 36, count 0 2006.260.07:43:52.22#ibcon#about to read 6, iclass 36, count 0 2006.260.07:43:52.22#ibcon#read 6, iclass 36, count 0 2006.260.07:43:52.22#ibcon#end of sib2, iclass 36, count 0 2006.260.07:43:52.22#ibcon#*after write, iclass 36, count 0 2006.260.07:43:52.22#ibcon#*before return 0, iclass 36, count 0 2006.260.07:43:52.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:52.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:43:52.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:43:52.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:43:52.22$vc4f8/vb=3,4 2006.260.07:43:52.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.07:43:52.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.07:43:52.22#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:52.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:52.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:52.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:52.28#ibcon#enter wrdev, iclass 38, count 2 2006.260.07:43:52.28#ibcon#first serial, iclass 38, count 2 2006.260.07:43:52.28#ibcon#enter sib2, iclass 38, count 2 2006.260.07:43:52.28#ibcon#flushed, iclass 38, count 2 2006.260.07:43:52.28#ibcon#about to write, iclass 38, count 2 2006.260.07:43:52.28#ibcon#wrote, iclass 38, count 2 2006.260.07:43:52.28#ibcon#about to read 3, iclass 38, count 2 2006.260.07:43:52.30#ibcon#read 3, iclass 38, count 2 2006.260.07:43:52.30#ibcon#about to read 4, iclass 38, count 2 2006.260.07:43:52.30#ibcon#read 4, iclass 38, count 2 2006.260.07:43:52.30#ibcon#about to read 5, iclass 38, count 2 2006.260.07:43:52.30#ibcon#read 5, iclass 38, count 2 2006.260.07:43:52.30#ibcon#about to read 6, iclass 38, count 2 2006.260.07:43:52.30#ibcon#read 6, iclass 38, count 2 2006.260.07:43:52.30#ibcon#end of sib2, iclass 38, count 2 2006.260.07:43:52.30#ibcon#*mode == 0, iclass 38, count 2 2006.260.07:43:52.30#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.07:43:52.30#ibcon#[27=AT03-04\r\n] 2006.260.07:43:52.30#ibcon#*before write, iclass 38, count 2 2006.260.07:43:52.30#ibcon#enter sib2, iclass 38, count 2 2006.260.07:43:52.30#ibcon#flushed, iclass 38, count 2 2006.260.07:43:52.30#ibcon#about to write, iclass 38, count 2 2006.260.07:43:52.30#ibcon#wrote, iclass 38, count 2 2006.260.07:43:52.30#ibcon#about to read 3, iclass 38, count 2 2006.260.07:43:52.33#ibcon#read 3, iclass 38, count 2 2006.260.07:43:52.33#ibcon#about to read 4, iclass 38, count 2 2006.260.07:43:52.33#ibcon#read 4, iclass 38, count 2 2006.260.07:43:52.33#ibcon#about to read 5, iclass 38, count 2 2006.260.07:43:52.33#ibcon#read 5, iclass 38, count 2 2006.260.07:43:52.33#ibcon#about to read 6, iclass 38, count 2 2006.260.07:43:52.33#ibcon#read 6, iclass 38, count 2 2006.260.07:43:52.33#ibcon#end of sib2, iclass 38, count 2 2006.260.07:43:52.33#ibcon#*after write, iclass 38, count 2 2006.260.07:43:52.33#ibcon#*before return 0, iclass 38, count 2 2006.260.07:43:52.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:52.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:43:52.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.07:43:52.33#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:52.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:52.34#abcon#<5=/04 3.4 7.1 23.04 871010.4\r\n> 2006.260.07:43:52.36#abcon#{5=INTERFACE CLEAR} 2006.260.07:43:52.42#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:43:52.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:52.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:52.45#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:43:52.45#ibcon#first serial, iclass 38, count 0 2006.260.07:43:52.45#ibcon#enter sib2, iclass 38, count 0 2006.260.07:43:52.45#ibcon#flushed, iclass 38, count 0 2006.260.07:43:52.45#ibcon#about to write, iclass 38, count 0 2006.260.07:43:52.45#ibcon#wrote, iclass 38, count 0 2006.260.07:43:52.45#ibcon#about to read 3, iclass 38, count 0 2006.260.07:43:52.47#ibcon#read 3, iclass 38, count 0 2006.260.07:43:52.47#ibcon#about to read 4, iclass 38, count 0 2006.260.07:43:52.47#ibcon#read 4, iclass 38, count 0 2006.260.07:43:52.47#ibcon#about to read 5, iclass 38, count 0 2006.260.07:43:52.47#ibcon#read 5, iclass 38, count 0 2006.260.07:43:52.47#ibcon#about to read 6, iclass 38, count 0 2006.260.07:43:52.47#ibcon#read 6, iclass 38, count 0 2006.260.07:43:52.47#ibcon#end of sib2, iclass 38, count 0 2006.260.07:43:52.47#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:43:52.47#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:43:52.47#ibcon#[27=USB\r\n] 2006.260.07:43:52.47#ibcon#*before write, iclass 38, count 0 2006.260.07:43:52.47#ibcon#enter sib2, iclass 38, count 0 2006.260.07:43:52.47#ibcon#flushed, iclass 38, count 0 2006.260.07:43:52.47#ibcon#about to write, iclass 38, count 0 2006.260.07:43:52.47#ibcon#wrote, iclass 38, count 0 2006.260.07:43:52.47#ibcon#about to read 3, iclass 38, count 0 2006.260.07:43:52.50#ibcon#read 3, iclass 38, count 0 2006.260.07:43:52.50#ibcon#about to read 4, iclass 38, count 0 2006.260.07:43:52.50#ibcon#read 4, iclass 38, count 0 2006.260.07:43:52.50#ibcon#about to read 5, iclass 38, count 0 2006.260.07:43:52.50#ibcon#read 5, iclass 38, count 0 2006.260.07:43:52.50#ibcon#about to read 6, iclass 38, count 0 2006.260.07:43:52.50#ibcon#read 6, iclass 38, count 0 2006.260.07:43:52.50#ibcon#end of sib2, iclass 38, count 0 2006.260.07:43:52.50#ibcon#*after write, iclass 38, count 0 2006.260.07:43:52.50#ibcon#*before return 0, iclass 38, count 0 2006.260.07:43:52.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:52.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:43:52.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:43:52.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:43:52.50$vc4f8/vblo=4,712.99 2006.260.07:43:52.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.07:43:52.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.07:43:52.50#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:52.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:52.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:52.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:52.50#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:43:52.50#ibcon#first serial, iclass 6, count 0 2006.260.07:43:52.50#ibcon#enter sib2, iclass 6, count 0 2006.260.07:43:52.50#ibcon#flushed, iclass 6, count 0 2006.260.07:43:52.50#ibcon#about to write, iclass 6, count 0 2006.260.07:43:52.50#ibcon#wrote, iclass 6, count 0 2006.260.07:43:52.50#ibcon#about to read 3, iclass 6, count 0 2006.260.07:43:52.52#ibcon#read 3, iclass 6, count 0 2006.260.07:43:52.52#ibcon#about to read 4, iclass 6, count 0 2006.260.07:43:52.52#ibcon#read 4, iclass 6, count 0 2006.260.07:43:52.52#ibcon#about to read 5, iclass 6, count 0 2006.260.07:43:52.52#ibcon#read 5, iclass 6, count 0 2006.260.07:43:52.52#ibcon#about to read 6, iclass 6, count 0 2006.260.07:43:52.52#ibcon#read 6, iclass 6, count 0 2006.260.07:43:52.52#ibcon#end of sib2, iclass 6, count 0 2006.260.07:43:52.52#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:43:52.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:43:52.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:43:52.52#ibcon#*before write, iclass 6, count 0 2006.260.07:43:52.52#ibcon#enter sib2, iclass 6, count 0 2006.260.07:43:52.52#ibcon#flushed, iclass 6, count 0 2006.260.07:43:52.52#ibcon#about to write, iclass 6, count 0 2006.260.07:43:52.52#ibcon#wrote, iclass 6, count 0 2006.260.07:43:52.52#ibcon#about to read 3, iclass 6, count 0 2006.260.07:43:52.56#ibcon#read 3, iclass 6, count 0 2006.260.07:43:52.56#ibcon#about to read 4, iclass 6, count 0 2006.260.07:43:52.56#ibcon#read 4, iclass 6, count 0 2006.260.07:43:52.56#ibcon#about to read 5, iclass 6, count 0 2006.260.07:43:52.56#ibcon#read 5, iclass 6, count 0 2006.260.07:43:52.56#ibcon#about to read 6, iclass 6, count 0 2006.260.07:43:52.56#ibcon#read 6, iclass 6, count 0 2006.260.07:43:52.56#ibcon#end of sib2, iclass 6, count 0 2006.260.07:43:52.56#ibcon#*after write, iclass 6, count 0 2006.260.07:43:52.56#ibcon#*before return 0, iclass 6, count 0 2006.260.07:43:52.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:52.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:43:52.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:43:52.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:43:52.56$vc4f8/vb=4,5 2006.260.07:43:52.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.07:43:52.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.07:43:52.56#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:52.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:52.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:52.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:52.62#ibcon#enter wrdev, iclass 10, count 2 2006.260.07:43:52.62#ibcon#first serial, iclass 10, count 2 2006.260.07:43:52.62#ibcon#enter sib2, iclass 10, count 2 2006.260.07:43:52.62#ibcon#flushed, iclass 10, count 2 2006.260.07:43:52.62#ibcon#about to write, iclass 10, count 2 2006.260.07:43:52.62#ibcon#wrote, iclass 10, count 2 2006.260.07:43:52.62#ibcon#about to read 3, iclass 10, count 2 2006.260.07:43:52.64#ibcon#read 3, iclass 10, count 2 2006.260.07:43:52.64#ibcon#about to read 4, iclass 10, count 2 2006.260.07:43:52.64#ibcon#read 4, iclass 10, count 2 2006.260.07:43:52.64#ibcon#about to read 5, iclass 10, count 2 2006.260.07:43:52.64#ibcon#read 5, iclass 10, count 2 2006.260.07:43:52.64#ibcon#about to read 6, iclass 10, count 2 2006.260.07:43:52.64#ibcon#read 6, iclass 10, count 2 2006.260.07:43:52.64#ibcon#end of sib2, iclass 10, count 2 2006.260.07:43:52.64#ibcon#*mode == 0, iclass 10, count 2 2006.260.07:43:52.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.07:43:52.64#ibcon#[27=AT04-05\r\n] 2006.260.07:43:52.64#ibcon#*before write, iclass 10, count 2 2006.260.07:43:52.64#ibcon#enter sib2, iclass 10, count 2 2006.260.07:43:52.64#ibcon#flushed, iclass 10, count 2 2006.260.07:43:52.64#ibcon#about to write, iclass 10, count 2 2006.260.07:43:52.64#ibcon#wrote, iclass 10, count 2 2006.260.07:43:52.64#ibcon#about to read 3, iclass 10, count 2 2006.260.07:43:52.67#ibcon#read 3, iclass 10, count 2 2006.260.07:43:52.67#ibcon#about to read 4, iclass 10, count 2 2006.260.07:43:52.67#ibcon#read 4, iclass 10, count 2 2006.260.07:43:52.67#ibcon#about to read 5, iclass 10, count 2 2006.260.07:43:52.67#ibcon#read 5, iclass 10, count 2 2006.260.07:43:52.67#ibcon#about to read 6, iclass 10, count 2 2006.260.07:43:52.67#ibcon#read 6, iclass 10, count 2 2006.260.07:43:52.67#ibcon#end of sib2, iclass 10, count 2 2006.260.07:43:52.67#ibcon#*after write, iclass 10, count 2 2006.260.07:43:52.67#ibcon#*before return 0, iclass 10, count 2 2006.260.07:43:52.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:52.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:43:52.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.07:43:52.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:52.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:52.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:52.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:52.79#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:43:52.79#ibcon#first serial, iclass 10, count 0 2006.260.07:43:52.79#ibcon#enter sib2, iclass 10, count 0 2006.260.07:43:52.79#ibcon#flushed, iclass 10, count 0 2006.260.07:43:52.79#ibcon#about to write, iclass 10, count 0 2006.260.07:43:52.79#ibcon#wrote, iclass 10, count 0 2006.260.07:43:52.79#ibcon#about to read 3, iclass 10, count 0 2006.260.07:43:52.81#ibcon#read 3, iclass 10, count 0 2006.260.07:43:52.81#ibcon#about to read 4, iclass 10, count 0 2006.260.07:43:52.81#ibcon#read 4, iclass 10, count 0 2006.260.07:43:52.81#ibcon#about to read 5, iclass 10, count 0 2006.260.07:43:52.81#ibcon#read 5, iclass 10, count 0 2006.260.07:43:52.81#ibcon#about to read 6, iclass 10, count 0 2006.260.07:43:52.81#ibcon#read 6, iclass 10, count 0 2006.260.07:43:52.81#ibcon#end of sib2, iclass 10, count 0 2006.260.07:43:52.81#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:43:52.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:43:52.81#ibcon#[27=USB\r\n] 2006.260.07:43:52.81#ibcon#*before write, iclass 10, count 0 2006.260.07:43:52.81#ibcon#enter sib2, iclass 10, count 0 2006.260.07:43:52.81#ibcon#flushed, iclass 10, count 0 2006.260.07:43:52.81#ibcon#about to write, iclass 10, count 0 2006.260.07:43:52.81#ibcon#wrote, iclass 10, count 0 2006.260.07:43:52.81#ibcon#about to read 3, iclass 10, count 0 2006.260.07:43:52.85#ibcon#read 3, iclass 10, count 0 2006.260.07:43:52.85#ibcon#about to read 4, iclass 10, count 0 2006.260.07:43:52.85#ibcon#read 4, iclass 10, count 0 2006.260.07:43:52.85#ibcon#about to read 5, iclass 10, count 0 2006.260.07:43:52.85#ibcon#read 5, iclass 10, count 0 2006.260.07:43:52.85#ibcon#about to read 6, iclass 10, count 0 2006.260.07:43:52.85#ibcon#read 6, iclass 10, count 0 2006.260.07:43:52.85#ibcon#end of sib2, iclass 10, count 0 2006.260.07:43:52.85#ibcon#*after write, iclass 10, count 0 2006.260.07:43:52.85#ibcon#*before return 0, iclass 10, count 0 2006.260.07:43:52.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:52.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:43:52.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:43:52.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:43:52.85$vc4f8/vblo=5,744.99 2006.260.07:43:52.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:43:52.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:43:52.85#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:52.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:52.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:52.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:52.85#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:43:52.85#ibcon#first serial, iclass 12, count 0 2006.260.07:43:52.85#ibcon#enter sib2, iclass 12, count 0 2006.260.07:43:52.85#ibcon#flushed, iclass 12, count 0 2006.260.07:43:52.85#ibcon#about to write, iclass 12, count 0 2006.260.07:43:52.85#ibcon#wrote, iclass 12, count 0 2006.260.07:43:52.85#ibcon#about to read 3, iclass 12, count 0 2006.260.07:43:52.87#ibcon#read 3, iclass 12, count 0 2006.260.07:43:52.87#ibcon#about to read 4, iclass 12, count 0 2006.260.07:43:52.87#ibcon#read 4, iclass 12, count 0 2006.260.07:43:52.87#ibcon#about to read 5, iclass 12, count 0 2006.260.07:43:52.87#ibcon#read 5, iclass 12, count 0 2006.260.07:43:52.87#ibcon#about to read 6, iclass 12, count 0 2006.260.07:43:52.87#ibcon#read 6, iclass 12, count 0 2006.260.07:43:52.87#ibcon#end of sib2, iclass 12, count 0 2006.260.07:43:52.87#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:43:52.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:43:52.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:43:52.87#ibcon#*before write, iclass 12, count 0 2006.260.07:43:52.87#ibcon#enter sib2, iclass 12, count 0 2006.260.07:43:52.87#ibcon#flushed, iclass 12, count 0 2006.260.07:43:52.87#ibcon#about to write, iclass 12, count 0 2006.260.07:43:52.87#ibcon#wrote, iclass 12, count 0 2006.260.07:43:52.87#ibcon#about to read 3, iclass 12, count 0 2006.260.07:43:52.91#ibcon#read 3, iclass 12, count 0 2006.260.07:43:52.91#ibcon#about to read 4, iclass 12, count 0 2006.260.07:43:52.91#ibcon#read 4, iclass 12, count 0 2006.260.07:43:52.91#ibcon#about to read 5, iclass 12, count 0 2006.260.07:43:52.91#ibcon#read 5, iclass 12, count 0 2006.260.07:43:52.91#ibcon#about to read 6, iclass 12, count 0 2006.260.07:43:52.91#ibcon#read 6, iclass 12, count 0 2006.260.07:43:52.91#ibcon#end of sib2, iclass 12, count 0 2006.260.07:43:52.91#ibcon#*after write, iclass 12, count 0 2006.260.07:43:52.91#ibcon#*before return 0, iclass 12, count 0 2006.260.07:43:52.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:52.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:43:52.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:43:52.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:43:52.91$vc4f8/vb=5,4 2006.260.07:43:52.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:43:52.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:43:52.91#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:52.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:52.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:52.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:52.97#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:43:52.97#ibcon#first serial, iclass 14, count 2 2006.260.07:43:52.97#ibcon#enter sib2, iclass 14, count 2 2006.260.07:43:52.97#ibcon#flushed, iclass 14, count 2 2006.260.07:43:52.97#ibcon#about to write, iclass 14, count 2 2006.260.07:43:52.97#ibcon#wrote, iclass 14, count 2 2006.260.07:43:52.97#ibcon#about to read 3, iclass 14, count 2 2006.260.07:43:52.99#ibcon#read 3, iclass 14, count 2 2006.260.07:43:52.99#ibcon#about to read 4, iclass 14, count 2 2006.260.07:43:52.99#ibcon#read 4, iclass 14, count 2 2006.260.07:43:52.99#ibcon#about to read 5, iclass 14, count 2 2006.260.07:43:52.99#ibcon#read 5, iclass 14, count 2 2006.260.07:43:52.99#ibcon#about to read 6, iclass 14, count 2 2006.260.07:43:52.99#ibcon#read 6, iclass 14, count 2 2006.260.07:43:52.99#ibcon#end of sib2, iclass 14, count 2 2006.260.07:43:52.99#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:43:52.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:43:52.99#ibcon#[27=AT05-04\r\n] 2006.260.07:43:52.99#ibcon#*before write, iclass 14, count 2 2006.260.07:43:52.99#ibcon#enter sib2, iclass 14, count 2 2006.260.07:43:52.99#ibcon#flushed, iclass 14, count 2 2006.260.07:43:52.99#ibcon#about to write, iclass 14, count 2 2006.260.07:43:52.99#ibcon#wrote, iclass 14, count 2 2006.260.07:43:52.99#ibcon#about to read 3, iclass 14, count 2 2006.260.07:43:53.02#ibcon#read 3, iclass 14, count 2 2006.260.07:43:53.02#ibcon#about to read 4, iclass 14, count 2 2006.260.07:43:53.02#ibcon#read 4, iclass 14, count 2 2006.260.07:43:53.02#ibcon#about to read 5, iclass 14, count 2 2006.260.07:43:53.02#ibcon#read 5, iclass 14, count 2 2006.260.07:43:53.02#ibcon#about to read 6, iclass 14, count 2 2006.260.07:43:53.02#ibcon#read 6, iclass 14, count 2 2006.260.07:43:53.02#ibcon#end of sib2, iclass 14, count 2 2006.260.07:43:53.02#ibcon#*after write, iclass 14, count 2 2006.260.07:43:53.02#ibcon#*before return 0, iclass 14, count 2 2006.260.07:43:53.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:53.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:43:53.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:43:53.02#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:53.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:53.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:53.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:53.14#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:43:53.14#ibcon#first serial, iclass 14, count 0 2006.260.07:43:53.14#ibcon#enter sib2, iclass 14, count 0 2006.260.07:43:53.14#ibcon#flushed, iclass 14, count 0 2006.260.07:43:53.14#ibcon#about to write, iclass 14, count 0 2006.260.07:43:53.14#ibcon#wrote, iclass 14, count 0 2006.260.07:43:53.14#ibcon#about to read 3, iclass 14, count 0 2006.260.07:43:53.16#ibcon#read 3, iclass 14, count 0 2006.260.07:43:53.16#ibcon#about to read 4, iclass 14, count 0 2006.260.07:43:53.16#ibcon#read 4, iclass 14, count 0 2006.260.07:43:53.16#ibcon#about to read 5, iclass 14, count 0 2006.260.07:43:53.16#ibcon#read 5, iclass 14, count 0 2006.260.07:43:53.16#ibcon#about to read 6, iclass 14, count 0 2006.260.07:43:53.16#ibcon#read 6, iclass 14, count 0 2006.260.07:43:53.16#ibcon#end of sib2, iclass 14, count 0 2006.260.07:43:53.16#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:43:53.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:43:53.16#ibcon#[27=USB\r\n] 2006.260.07:43:53.16#ibcon#*before write, iclass 14, count 0 2006.260.07:43:53.16#ibcon#enter sib2, iclass 14, count 0 2006.260.07:43:53.16#ibcon#flushed, iclass 14, count 0 2006.260.07:43:53.16#ibcon#about to write, iclass 14, count 0 2006.260.07:43:53.16#ibcon#wrote, iclass 14, count 0 2006.260.07:43:53.16#ibcon#about to read 3, iclass 14, count 0 2006.260.07:43:53.19#ibcon#read 3, iclass 14, count 0 2006.260.07:43:53.19#ibcon#about to read 4, iclass 14, count 0 2006.260.07:43:53.19#ibcon#read 4, iclass 14, count 0 2006.260.07:43:53.19#ibcon#about to read 5, iclass 14, count 0 2006.260.07:43:53.19#ibcon#read 5, iclass 14, count 0 2006.260.07:43:53.19#ibcon#about to read 6, iclass 14, count 0 2006.260.07:43:53.19#ibcon#read 6, iclass 14, count 0 2006.260.07:43:53.19#ibcon#end of sib2, iclass 14, count 0 2006.260.07:43:53.19#ibcon#*after write, iclass 14, count 0 2006.260.07:43:53.19#ibcon#*before return 0, iclass 14, count 0 2006.260.07:43:53.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:53.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:43:53.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:43:53.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:43:53.19$vc4f8/vblo=6,752.99 2006.260.07:43:53.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:43:53.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:43:53.19#ibcon#ireg 17 cls_cnt 0 2006.260.07:43:53.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:53.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:53.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:53.19#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:43:53.19#ibcon#first serial, iclass 16, count 0 2006.260.07:43:53.19#ibcon#enter sib2, iclass 16, count 0 2006.260.07:43:53.19#ibcon#flushed, iclass 16, count 0 2006.260.07:43:53.19#ibcon#about to write, iclass 16, count 0 2006.260.07:43:53.19#ibcon#wrote, iclass 16, count 0 2006.260.07:43:53.19#ibcon#about to read 3, iclass 16, count 0 2006.260.07:43:53.21#ibcon#read 3, iclass 16, count 0 2006.260.07:43:53.21#ibcon#about to read 4, iclass 16, count 0 2006.260.07:43:53.21#ibcon#read 4, iclass 16, count 0 2006.260.07:43:53.21#ibcon#about to read 5, iclass 16, count 0 2006.260.07:43:53.21#ibcon#read 5, iclass 16, count 0 2006.260.07:43:53.21#ibcon#about to read 6, iclass 16, count 0 2006.260.07:43:53.21#ibcon#read 6, iclass 16, count 0 2006.260.07:43:53.21#ibcon#end of sib2, iclass 16, count 0 2006.260.07:43:53.21#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:43:53.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:43:53.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:43:53.21#ibcon#*before write, iclass 16, count 0 2006.260.07:43:53.21#ibcon#enter sib2, iclass 16, count 0 2006.260.07:43:53.21#ibcon#flushed, iclass 16, count 0 2006.260.07:43:53.21#ibcon#about to write, iclass 16, count 0 2006.260.07:43:53.21#ibcon#wrote, iclass 16, count 0 2006.260.07:43:53.21#ibcon#about to read 3, iclass 16, count 0 2006.260.07:43:53.25#ibcon#read 3, iclass 16, count 0 2006.260.07:43:53.25#ibcon#about to read 4, iclass 16, count 0 2006.260.07:43:53.25#ibcon#read 4, iclass 16, count 0 2006.260.07:43:53.25#ibcon#about to read 5, iclass 16, count 0 2006.260.07:43:53.25#ibcon#read 5, iclass 16, count 0 2006.260.07:43:53.25#ibcon#about to read 6, iclass 16, count 0 2006.260.07:43:53.25#ibcon#read 6, iclass 16, count 0 2006.260.07:43:53.25#ibcon#end of sib2, iclass 16, count 0 2006.260.07:43:53.25#ibcon#*after write, iclass 16, count 0 2006.260.07:43:53.25#ibcon#*before return 0, iclass 16, count 0 2006.260.07:43:53.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:53.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:43:53.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:43:53.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:43:53.25$vc4f8/vb=6,4 2006.260.07:43:53.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:43:53.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:43:53.25#ibcon#ireg 11 cls_cnt 2 2006.260.07:43:53.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:53.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:53.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:53.31#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:43:53.31#ibcon#first serial, iclass 18, count 2 2006.260.07:43:53.31#ibcon#enter sib2, iclass 18, count 2 2006.260.07:43:53.31#ibcon#flushed, iclass 18, count 2 2006.260.07:43:53.31#ibcon#about to write, iclass 18, count 2 2006.260.07:43:53.31#ibcon#wrote, iclass 18, count 2 2006.260.07:43:53.31#ibcon#about to read 3, iclass 18, count 2 2006.260.07:43:53.33#ibcon#read 3, iclass 18, count 2 2006.260.07:43:53.33#ibcon#about to read 4, iclass 18, count 2 2006.260.07:43:53.33#ibcon#read 4, iclass 18, count 2 2006.260.07:43:53.33#ibcon#about to read 5, iclass 18, count 2 2006.260.07:43:53.33#ibcon#read 5, iclass 18, count 2 2006.260.07:43:53.33#ibcon#about to read 6, iclass 18, count 2 2006.260.07:43:53.33#ibcon#read 6, iclass 18, count 2 2006.260.07:43:53.33#ibcon#end of sib2, iclass 18, count 2 2006.260.07:43:53.33#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:43:53.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:43:53.33#ibcon#[27=AT06-04\r\n] 2006.260.07:43:53.33#ibcon#*before write, iclass 18, count 2 2006.260.07:43:53.33#ibcon#enter sib2, iclass 18, count 2 2006.260.07:43:53.33#ibcon#flushed, iclass 18, count 2 2006.260.07:43:53.33#ibcon#about to write, iclass 18, count 2 2006.260.07:43:53.33#ibcon#wrote, iclass 18, count 2 2006.260.07:43:53.33#ibcon#about to read 3, iclass 18, count 2 2006.260.07:43:53.36#ibcon#read 3, iclass 18, count 2 2006.260.07:43:53.36#ibcon#about to read 4, iclass 18, count 2 2006.260.07:43:53.36#ibcon#read 4, iclass 18, count 2 2006.260.07:43:53.36#ibcon#about to read 5, iclass 18, count 2 2006.260.07:43:53.36#ibcon#read 5, iclass 18, count 2 2006.260.07:43:53.36#ibcon#about to read 6, iclass 18, count 2 2006.260.07:43:53.36#ibcon#read 6, iclass 18, count 2 2006.260.07:43:53.36#ibcon#end of sib2, iclass 18, count 2 2006.260.07:43:53.36#ibcon#*after write, iclass 18, count 2 2006.260.07:43:53.36#ibcon#*before return 0, iclass 18, count 2 2006.260.07:43:53.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:53.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:43:53.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:43:53.36#ibcon#ireg 7 cls_cnt 0 2006.260.07:43:53.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:53.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:53.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:53.48#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:43:53.48#ibcon#first serial, iclass 18, count 0 2006.260.07:43:53.48#ibcon#enter sib2, iclass 18, count 0 2006.260.07:43:53.48#ibcon#flushed, iclass 18, count 0 2006.260.07:43:53.48#ibcon#about to write, iclass 18, count 0 2006.260.07:43:53.48#ibcon#wrote, iclass 18, count 0 2006.260.07:43:53.48#ibcon#about to read 3, iclass 18, count 0 2006.260.07:43:53.50#ibcon#read 3, iclass 18, count 0 2006.260.07:43:53.50#ibcon#about to read 4, iclass 18, count 0 2006.260.07:43:53.50#ibcon#read 4, iclass 18, count 0 2006.260.07:43:53.50#ibcon#about to read 5, iclass 18, count 0 2006.260.07:43:53.50#ibcon#read 5, iclass 18, count 0 2006.260.07:43:53.50#ibcon#about to read 6, iclass 18, count 0 2006.260.07:43:53.50#ibcon#read 6, iclass 18, count 0 2006.260.07:43:53.50#ibcon#end of sib2, iclass 18, count 0 2006.260.07:43:53.50#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:43:53.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:43:53.50#ibcon#[27=USB\r\n] 2006.260.07:43:53.50#ibcon#*before write, iclass 18, count 0 2006.260.07:43:53.50#ibcon#enter sib2, iclass 18, count 0 2006.260.07:43:53.50#ibcon#flushed, iclass 18, count 0 2006.260.07:43:53.50#ibcon#about to write, iclass 18, count 0 2006.260.07:43:53.50#ibcon#wrote, iclass 18, count 0 2006.260.07:43:53.50#ibcon#about to read 3, iclass 18, count 0 2006.260.07:43:53.53#ibcon#read 3, iclass 18, count 0 2006.260.07:43:53.53#ibcon#about to read 4, iclass 18, count 0 2006.260.07:43:53.53#ibcon#read 4, iclass 18, count 0 2006.260.07:43:53.53#ibcon#about to read 5, iclass 18, count 0 2006.260.07:43:53.53#ibcon#read 5, iclass 18, count 0 2006.260.07:43:53.53#ibcon#about to read 6, iclass 18, count 0 2006.260.07:43:53.53#ibcon#read 6, iclass 18, count 0 2006.260.07:43:53.53#ibcon#end of sib2, iclass 18, count 0 2006.260.07:43:53.53#ibcon#*after write, iclass 18, count 0 2006.260.07:43:53.53#ibcon#*before return 0, iclass 18, count 0 2006.260.07:43:53.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:53.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:43:53.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:43:53.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:43:53.53$vc4f8/vabw=wide 2006.260.07:43:53.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:43:53.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:43:53.53#ibcon#ireg 8 cls_cnt 0 2006.260.07:43:53.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:53.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:53.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:53.53#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:43:53.53#ibcon#first serial, iclass 20, count 0 2006.260.07:43:53.53#ibcon#enter sib2, iclass 20, count 0 2006.260.07:43:53.53#ibcon#flushed, iclass 20, count 0 2006.260.07:43:53.53#ibcon#about to write, iclass 20, count 0 2006.260.07:43:53.53#ibcon#wrote, iclass 20, count 0 2006.260.07:43:53.53#ibcon#about to read 3, iclass 20, count 0 2006.260.07:43:53.55#ibcon#read 3, iclass 20, count 0 2006.260.07:43:53.55#ibcon#about to read 4, iclass 20, count 0 2006.260.07:43:53.55#ibcon#read 4, iclass 20, count 0 2006.260.07:43:53.55#ibcon#about to read 5, iclass 20, count 0 2006.260.07:43:53.55#ibcon#read 5, iclass 20, count 0 2006.260.07:43:53.55#ibcon#about to read 6, iclass 20, count 0 2006.260.07:43:53.55#ibcon#read 6, iclass 20, count 0 2006.260.07:43:53.55#ibcon#end of sib2, iclass 20, count 0 2006.260.07:43:53.55#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:43:53.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:43:53.55#ibcon#[25=BW32\r\n] 2006.260.07:43:53.55#ibcon#*before write, iclass 20, count 0 2006.260.07:43:53.55#ibcon#enter sib2, iclass 20, count 0 2006.260.07:43:53.55#ibcon#flushed, iclass 20, count 0 2006.260.07:43:53.55#ibcon#about to write, iclass 20, count 0 2006.260.07:43:53.55#ibcon#wrote, iclass 20, count 0 2006.260.07:43:53.55#ibcon#about to read 3, iclass 20, count 0 2006.260.07:43:53.58#ibcon#read 3, iclass 20, count 0 2006.260.07:43:53.58#ibcon#about to read 4, iclass 20, count 0 2006.260.07:43:53.58#ibcon#read 4, iclass 20, count 0 2006.260.07:43:53.58#ibcon#about to read 5, iclass 20, count 0 2006.260.07:43:53.58#ibcon#read 5, iclass 20, count 0 2006.260.07:43:53.58#ibcon#about to read 6, iclass 20, count 0 2006.260.07:43:53.58#ibcon#read 6, iclass 20, count 0 2006.260.07:43:53.58#ibcon#end of sib2, iclass 20, count 0 2006.260.07:43:53.58#ibcon#*after write, iclass 20, count 0 2006.260.07:43:53.58#ibcon#*before return 0, iclass 20, count 0 2006.260.07:43:53.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:53.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:43:53.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:43:53.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:43:53.58$vc4f8/vbbw=wide 2006.260.07:43:53.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:43:53.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:43:53.58#ibcon#ireg 8 cls_cnt 0 2006.260.07:43:53.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:43:53.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:43:53.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:43:53.65#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:43:53.65#ibcon#first serial, iclass 22, count 0 2006.260.07:43:53.65#ibcon#enter sib2, iclass 22, count 0 2006.260.07:43:53.65#ibcon#flushed, iclass 22, count 0 2006.260.07:43:53.65#ibcon#about to write, iclass 22, count 0 2006.260.07:43:53.65#ibcon#wrote, iclass 22, count 0 2006.260.07:43:53.65#ibcon#about to read 3, iclass 22, count 0 2006.260.07:43:53.67#ibcon#read 3, iclass 22, count 0 2006.260.07:43:53.67#ibcon#about to read 4, iclass 22, count 0 2006.260.07:43:53.67#ibcon#read 4, iclass 22, count 0 2006.260.07:43:53.67#ibcon#about to read 5, iclass 22, count 0 2006.260.07:43:53.67#ibcon#read 5, iclass 22, count 0 2006.260.07:43:53.67#ibcon#about to read 6, iclass 22, count 0 2006.260.07:43:53.67#ibcon#read 6, iclass 22, count 0 2006.260.07:43:53.67#ibcon#end of sib2, iclass 22, count 0 2006.260.07:43:53.67#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:43:53.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:43:53.67#ibcon#[27=BW32\r\n] 2006.260.07:43:53.67#ibcon#*before write, iclass 22, count 0 2006.260.07:43:53.67#ibcon#enter sib2, iclass 22, count 0 2006.260.07:43:53.67#ibcon#flushed, iclass 22, count 0 2006.260.07:43:53.67#ibcon#about to write, iclass 22, count 0 2006.260.07:43:53.67#ibcon#wrote, iclass 22, count 0 2006.260.07:43:53.67#ibcon#about to read 3, iclass 22, count 0 2006.260.07:43:53.71#ibcon#read 3, iclass 22, count 0 2006.260.07:43:53.71#ibcon#about to read 4, iclass 22, count 0 2006.260.07:43:53.71#ibcon#read 4, iclass 22, count 0 2006.260.07:43:53.71#ibcon#about to read 5, iclass 22, count 0 2006.260.07:43:53.71#ibcon#read 5, iclass 22, count 0 2006.260.07:43:53.71#ibcon#about to read 6, iclass 22, count 0 2006.260.07:43:53.71#ibcon#read 6, iclass 22, count 0 2006.260.07:43:53.71#ibcon#end of sib2, iclass 22, count 0 2006.260.07:43:53.71#ibcon#*after write, iclass 22, count 0 2006.260.07:43:53.71#ibcon#*before return 0, iclass 22, count 0 2006.260.07:43:53.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:43:53.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:43:53.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:43:53.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:43:53.71$4f8m12a/ifd4f 2006.260.07:43:53.71$ifd4f/lo= 2006.260.07:43:53.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:43:53.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:43:53.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:43:53.71$ifd4f/patch= 2006.260.07:43:53.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:43:53.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:43:53.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:43:53.71$4f8m12a/"form=m,16.000,1:2 2006.260.07:43:53.71$4f8m12a/"tpicd 2006.260.07:43:53.71$4f8m12a/echo=off 2006.260.07:43:53.71$4f8m12a/xlog=off 2006.260.07:43:53.71:!2006.260.07:44:20 2006.260.07:43:57.13#trakl#Source acquired 2006.260.07:43:59.13#flagr#flagr/antenna,acquired 2006.260.07:44:20.00:preob 2006.260.07:44:21.13/onsource/TRACKING 2006.260.07:44:21.13:!2006.260.07:44:30 2006.260.07:44:30.00:data_valid=on 2006.260.07:44:30.00:midob 2006.260.07:44:30.13/onsource/TRACKING 2006.260.07:44:30.13/wx/23.03,1010.4,87 2006.260.07:44:30.20/cable/+6.4578E-03 2006.260.07:44:31.29/va/01,08,usb,yes,32,33 2006.260.07:44:31.29/va/02,07,usb,yes,32,33 2006.260.07:44:31.29/va/03,08,usb,yes,24,24 2006.260.07:44:31.29/va/04,07,usb,yes,33,36 2006.260.07:44:31.29/va/05,07,usb,yes,37,39 2006.260.07:44:31.29/va/06,06,usb,yes,36,36 2006.260.07:44:31.29/va/07,06,usb,yes,37,36 2006.260.07:44:31.29/va/08,06,usb,yes,39,38 2006.260.07:44:31.52/valo/01,532.99,yes,locked 2006.260.07:44:31.52/valo/02,572.99,yes,locked 2006.260.07:44:31.52/valo/03,672.99,yes,locked 2006.260.07:44:31.52/valo/04,832.99,yes,locked 2006.260.07:44:31.52/valo/05,652.99,yes,locked 2006.260.07:44:31.52/valo/06,772.99,yes,locked 2006.260.07:44:31.52/valo/07,832.99,yes,locked 2006.260.07:44:31.52/valo/08,852.99,yes,locked 2006.260.07:44:32.61/vb/01,04,usb,yes,31,30 2006.260.07:44:32.61/vb/02,05,usb,yes,29,30 2006.260.07:44:32.61/vb/03,04,usb,yes,29,33 2006.260.07:44:32.61/vb/04,05,usb,yes,26,26 2006.260.07:44:32.61/vb/05,04,usb,yes,28,32 2006.260.07:44:32.61/vb/06,04,usb,yes,29,32 2006.260.07:44:32.61/vb/07,04,usb,yes,31,31 2006.260.07:44:32.61/vb/08,04,usb,yes,29,32 2006.260.07:44:32.85/vblo/01,632.99,yes,locked 2006.260.07:44:32.85/vblo/02,640.99,yes,locked 2006.260.07:44:32.85/vblo/03,656.99,yes,locked 2006.260.07:44:32.85/vblo/04,712.99,yes,locked 2006.260.07:44:32.85/vblo/05,744.99,yes,locked 2006.260.07:44:32.85/vblo/06,752.99,yes,locked 2006.260.07:44:32.85/vblo/07,734.99,yes,locked 2006.260.07:44:32.85/vblo/08,744.99,yes,locked 2006.260.07:44:33.00/vabw/8 2006.260.07:44:33.15/vbbw/8 2006.260.07:44:33.24/xfe/off,on,15.0 2006.260.07:44:33.62/ifatt/23,28,28,28 2006.260.07:44:34.08/fmout-gps/S +4.51E-07 2006.260.07:44:34.12:!2006.260.07:45:30 2006.260.07:45:30.00:data_valid=off 2006.260.07:45:30.00:postob 2006.260.07:45:30.12/cable/+6.4557E-03 2006.260.07:45:30.12/wx/23.02,1010.4,87 2006.260.07:45:31.07/fmout-gps/S +4.51E-07 2006.260.07:45:31.07:scan_name=260-0746,k06260,60 2006.260.07:45:31.07:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.260.07:45:31.14#flagr#flagr/antenna,new-source 2006.260.07:45:32.14:checkk5 2006.260.07:45:32.61/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:45:33.00/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:45:33.46/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:45:36.90/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:45:37.32/chk_obsdata//k5ts1/T2600744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:45:37.71/chk_obsdata//k5ts2/T2600744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:45:38.12/chk_obsdata//k5ts3/T2600744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:45:38.53/chk_obsdata//k5ts4/T2600744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:45:39.49/k5log//k5ts1_log_newline 2006.260.07:45:40.54/k5log//k5ts2_log_newline 2006.260.07:45:41.45/k5log//k5ts3_log_newline 2006.260.07:45:42.23/k5log//k5ts4_log_newline 2006.260.07:45:42.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:45:42.26:4f8m12a=1 2006.260.07:45:42.26$4f8m12a/echo=on 2006.260.07:45:42.26$4f8m12a/pcalon 2006.260.07:45:42.26$pcalon/"no phase cal control is implemented here 2006.260.07:45:42.26$4f8m12a/"tpicd=stop 2006.260.07:45:42.26$4f8m12a/vc4f8 2006.260.07:45:42.26$vc4f8/valo=1,532.99 2006.260.07:45:42.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.07:45:42.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.07:45:42.26#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:42.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:42.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:42.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:42.26#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:45:42.26#ibcon#first serial, iclass 29, count 0 2006.260.07:45:42.26#ibcon#enter sib2, iclass 29, count 0 2006.260.07:45:42.26#ibcon#flushed, iclass 29, count 0 2006.260.07:45:42.26#ibcon#about to write, iclass 29, count 0 2006.260.07:45:42.26#ibcon#wrote, iclass 29, count 0 2006.260.07:45:42.26#ibcon#about to read 3, iclass 29, count 0 2006.260.07:45:42.31#ibcon#read 3, iclass 29, count 0 2006.260.07:45:42.31#ibcon#about to read 4, iclass 29, count 0 2006.260.07:45:42.31#ibcon#read 4, iclass 29, count 0 2006.260.07:45:42.31#ibcon#about to read 5, iclass 29, count 0 2006.260.07:45:42.31#ibcon#read 5, iclass 29, count 0 2006.260.07:45:42.31#ibcon#about to read 6, iclass 29, count 0 2006.260.07:45:42.31#ibcon#read 6, iclass 29, count 0 2006.260.07:45:42.31#ibcon#end of sib2, iclass 29, count 0 2006.260.07:45:42.31#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:45:42.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:45:42.31#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:45:42.31#ibcon#*before write, iclass 29, count 0 2006.260.07:45:42.31#ibcon#enter sib2, iclass 29, count 0 2006.260.07:45:42.31#ibcon#flushed, iclass 29, count 0 2006.260.07:45:42.31#ibcon#about to write, iclass 29, count 0 2006.260.07:45:42.31#ibcon#wrote, iclass 29, count 0 2006.260.07:45:42.31#ibcon#about to read 3, iclass 29, count 0 2006.260.07:45:42.36#ibcon#read 3, iclass 29, count 0 2006.260.07:45:42.36#ibcon#about to read 4, iclass 29, count 0 2006.260.07:45:42.36#ibcon#read 4, iclass 29, count 0 2006.260.07:45:42.36#ibcon#about to read 5, iclass 29, count 0 2006.260.07:45:42.36#ibcon#read 5, iclass 29, count 0 2006.260.07:45:42.36#ibcon#about to read 6, iclass 29, count 0 2006.260.07:45:42.36#ibcon#read 6, iclass 29, count 0 2006.260.07:45:42.36#ibcon#end of sib2, iclass 29, count 0 2006.260.07:45:42.36#ibcon#*after write, iclass 29, count 0 2006.260.07:45:42.36#ibcon#*before return 0, iclass 29, count 0 2006.260.07:45:42.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:42.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:42.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:45:42.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:45:42.36$vc4f8/va=1,8 2006.260.07:45:42.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.07:45:42.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.07:45:42.36#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:42.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:42.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:42.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:42.36#ibcon#enter wrdev, iclass 31, count 2 2006.260.07:45:42.36#ibcon#first serial, iclass 31, count 2 2006.260.07:45:42.36#ibcon#enter sib2, iclass 31, count 2 2006.260.07:45:42.36#ibcon#flushed, iclass 31, count 2 2006.260.07:45:42.36#ibcon#about to write, iclass 31, count 2 2006.260.07:45:42.36#ibcon#wrote, iclass 31, count 2 2006.260.07:45:42.36#ibcon#about to read 3, iclass 31, count 2 2006.260.07:45:42.38#ibcon#read 3, iclass 31, count 2 2006.260.07:45:42.38#ibcon#about to read 4, iclass 31, count 2 2006.260.07:45:42.38#ibcon#read 4, iclass 31, count 2 2006.260.07:45:42.38#ibcon#about to read 5, iclass 31, count 2 2006.260.07:45:42.38#ibcon#read 5, iclass 31, count 2 2006.260.07:45:42.38#ibcon#about to read 6, iclass 31, count 2 2006.260.07:45:42.38#ibcon#read 6, iclass 31, count 2 2006.260.07:45:42.38#ibcon#end of sib2, iclass 31, count 2 2006.260.07:45:42.38#ibcon#*mode == 0, iclass 31, count 2 2006.260.07:45:42.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.07:45:42.38#ibcon#[25=AT01-08\r\n] 2006.260.07:45:42.38#ibcon#*before write, iclass 31, count 2 2006.260.07:45:42.38#ibcon#enter sib2, iclass 31, count 2 2006.260.07:45:42.38#ibcon#flushed, iclass 31, count 2 2006.260.07:45:42.38#ibcon#about to write, iclass 31, count 2 2006.260.07:45:42.38#ibcon#wrote, iclass 31, count 2 2006.260.07:45:42.38#ibcon#about to read 3, iclass 31, count 2 2006.260.07:45:42.42#ibcon#read 3, iclass 31, count 2 2006.260.07:45:42.42#ibcon#about to read 4, iclass 31, count 2 2006.260.07:45:42.42#ibcon#read 4, iclass 31, count 2 2006.260.07:45:42.42#ibcon#about to read 5, iclass 31, count 2 2006.260.07:45:42.42#ibcon#read 5, iclass 31, count 2 2006.260.07:45:42.42#ibcon#about to read 6, iclass 31, count 2 2006.260.07:45:42.42#ibcon#read 6, iclass 31, count 2 2006.260.07:45:42.42#ibcon#end of sib2, iclass 31, count 2 2006.260.07:45:42.42#ibcon#*after write, iclass 31, count 2 2006.260.07:45:42.42#ibcon#*before return 0, iclass 31, count 2 2006.260.07:45:42.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:42.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:42.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.07:45:42.42#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:42.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:42.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:42.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:42.54#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:45:42.54#ibcon#first serial, iclass 31, count 0 2006.260.07:45:42.54#ibcon#enter sib2, iclass 31, count 0 2006.260.07:45:42.54#ibcon#flushed, iclass 31, count 0 2006.260.07:45:42.54#ibcon#about to write, iclass 31, count 0 2006.260.07:45:42.54#ibcon#wrote, iclass 31, count 0 2006.260.07:45:42.54#ibcon#about to read 3, iclass 31, count 0 2006.260.07:45:42.56#ibcon#read 3, iclass 31, count 0 2006.260.07:45:42.56#ibcon#about to read 4, iclass 31, count 0 2006.260.07:45:42.56#ibcon#read 4, iclass 31, count 0 2006.260.07:45:42.56#ibcon#about to read 5, iclass 31, count 0 2006.260.07:45:42.56#ibcon#read 5, iclass 31, count 0 2006.260.07:45:42.56#ibcon#about to read 6, iclass 31, count 0 2006.260.07:45:42.56#ibcon#read 6, iclass 31, count 0 2006.260.07:45:42.56#ibcon#end of sib2, iclass 31, count 0 2006.260.07:45:42.56#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:45:42.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:45:42.56#ibcon#[25=USB\r\n] 2006.260.07:45:42.56#ibcon#*before write, iclass 31, count 0 2006.260.07:45:42.56#ibcon#enter sib2, iclass 31, count 0 2006.260.07:45:42.56#ibcon#flushed, iclass 31, count 0 2006.260.07:45:42.56#ibcon#about to write, iclass 31, count 0 2006.260.07:45:42.56#ibcon#wrote, iclass 31, count 0 2006.260.07:45:42.56#ibcon#about to read 3, iclass 31, count 0 2006.260.07:45:42.59#ibcon#read 3, iclass 31, count 0 2006.260.07:45:42.59#ibcon#about to read 4, iclass 31, count 0 2006.260.07:45:42.59#ibcon#read 4, iclass 31, count 0 2006.260.07:45:42.59#ibcon#about to read 5, iclass 31, count 0 2006.260.07:45:42.59#ibcon#read 5, iclass 31, count 0 2006.260.07:45:42.59#ibcon#about to read 6, iclass 31, count 0 2006.260.07:45:42.59#ibcon#read 6, iclass 31, count 0 2006.260.07:45:42.59#ibcon#end of sib2, iclass 31, count 0 2006.260.07:45:42.59#ibcon#*after write, iclass 31, count 0 2006.260.07:45:42.59#ibcon#*before return 0, iclass 31, count 0 2006.260.07:45:42.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:42.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:42.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:45:42.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:45:42.59$vc4f8/valo=2,572.99 2006.260.07:45:42.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.07:45:42.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.07:45:42.59#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:42.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:42.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:42.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:42.59#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:45:42.59#ibcon#first serial, iclass 33, count 0 2006.260.07:45:42.59#ibcon#enter sib2, iclass 33, count 0 2006.260.07:45:42.59#ibcon#flushed, iclass 33, count 0 2006.260.07:45:42.59#ibcon#about to write, iclass 33, count 0 2006.260.07:45:42.59#ibcon#wrote, iclass 33, count 0 2006.260.07:45:42.59#ibcon#about to read 3, iclass 33, count 0 2006.260.07:45:42.61#ibcon#read 3, iclass 33, count 0 2006.260.07:45:42.61#ibcon#about to read 4, iclass 33, count 0 2006.260.07:45:42.61#ibcon#read 4, iclass 33, count 0 2006.260.07:45:42.61#ibcon#about to read 5, iclass 33, count 0 2006.260.07:45:42.61#ibcon#read 5, iclass 33, count 0 2006.260.07:45:42.61#ibcon#about to read 6, iclass 33, count 0 2006.260.07:45:42.61#ibcon#read 6, iclass 33, count 0 2006.260.07:45:42.61#ibcon#end of sib2, iclass 33, count 0 2006.260.07:45:42.61#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:45:42.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:45:42.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:45:42.61#ibcon#*before write, iclass 33, count 0 2006.260.07:45:42.61#ibcon#enter sib2, iclass 33, count 0 2006.260.07:45:42.61#ibcon#flushed, iclass 33, count 0 2006.260.07:45:42.61#ibcon#about to write, iclass 33, count 0 2006.260.07:45:42.61#ibcon#wrote, iclass 33, count 0 2006.260.07:45:42.61#ibcon#about to read 3, iclass 33, count 0 2006.260.07:45:42.65#ibcon#read 3, iclass 33, count 0 2006.260.07:45:42.65#ibcon#about to read 4, iclass 33, count 0 2006.260.07:45:42.65#ibcon#read 4, iclass 33, count 0 2006.260.07:45:42.65#ibcon#about to read 5, iclass 33, count 0 2006.260.07:45:42.65#ibcon#read 5, iclass 33, count 0 2006.260.07:45:42.65#ibcon#about to read 6, iclass 33, count 0 2006.260.07:45:42.65#ibcon#read 6, iclass 33, count 0 2006.260.07:45:42.65#ibcon#end of sib2, iclass 33, count 0 2006.260.07:45:42.65#ibcon#*after write, iclass 33, count 0 2006.260.07:45:42.65#ibcon#*before return 0, iclass 33, count 0 2006.260.07:45:42.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:42.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:42.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:45:42.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:45:42.65$vc4f8/va=2,7 2006.260.07:45:42.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.07:45:42.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.07:45:42.65#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:42.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:42.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:42.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:42.71#ibcon#enter wrdev, iclass 35, count 2 2006.260.07:45:42.71#ibcon#first serial, iclass 35, count 2 2006.260.07:45:42.71#ibcon#enter sib2, iclass 35, count 2 2006.260.07:45:42.71#ibcon#flushed, iclass 35, count 2 2006.260.07:45:42.71#ibcon#about to write, iclass 35, count 2 2006.260.07:45:42.71#ibcon#wrote, iclass 35, count 2 2006.260.07:45:42.71#ibcon#about to read 3, iclass 35, count 2 2006.260.07:45:42.73#ibcon#read 3, iclass 35, count 2 2006.260.07:45:42.73#ibcon#about to read 4, iclass 35, count 2 2006.260.07:45:42.73#ibcon#read 4, iclass 35, count 2 2006.260.07:45:42.73#ibcon#about to read 5, iclass 35, count 2 2006.260.07:45:42.73#ibcon#read 5, iclass 35, count 2 2006.260.07:45:42.73#ibcon#about to read 6, iclass 35, count 2 2006.260.07:45:42.73#ibcon#read 6, iclass 35, count 2 2006.260.07:45:42.73#ibcon#end of sib2, iclass 35, count 2 2006.260.07:45:42.73#ibcon#*mode == 0, iclass 35, count 2 2006.260.07:45:42.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.07:45:42.73#ibcon#[25=AT02-07\r\n] 2006.260.07:45:42.73#ibcon#*before write, iclass 35, count 2 2006.260.07:45:42.73#ibcon#enter sib2, iclass 35, count 2 2006.260.07:45:42.73#ibcon#flushed, iclass 35, count 2 2006.260.07:45:42.73#ibcon#about to write, iclass 35, count 2 2006.260.07:45:42.73#ibcon#wrote, iclass 35, count 2 2006.260.07:45:42.73#ibcon#about to read 3, iclass 35, count 2 2006.260.07:45:42.76#ibcon#read 3, iclass 35, count 2 2006.260.07:45:42.76#ibcon#about to read 4, iclass 35, count 2 2006.260.07:45:42.76#ibcon#read 4, iclass 35, count 2 2006.260.07:45:42.76#ibcon#about to read 5, iclass 35, count 2 2006.260.07:45:42.76#ibcon#read 5, iclass 35, count 2 2006.260.07:45:42.76#ibcon#about to read 6, iclass 35, count 2 2006.260.07:45:42.76#ibcon#read 6, iclass 35, count 2 2006.260.07:45:42.76#ibcon#end of sib2, iclass 35, count 2 2006.260.07:45:42.76#ibcon#*after write, iclass 35, count 2 2006.260.07:45:42.76#ibcon#*before return 0, iclass 35, count 2 2006.260.07:45:42.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:42.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:42.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.07:45:42.76#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:42.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:42.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:42.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:42.88#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:45:42.88#ibcon#first serial, iclass 35, count 0 2006.260.07:45:42.88#ibcon#enter sib2, iclass 35, count 0 2006.260.07:45:42.88#ibcon#flushed, iclass 35, count 0 2006.260.07:45:42.88#ibcon#about to write, iclass 35, count 0 2006.260.07:45:42.88#ibcon#wrote, iclass 35, count 0 2006.260.07:45:42.88#ibcon#about to read 3, iclass 35, count 0 2006.260.07:45:42.90#ibcon#read 3, iclass 35, count 0 2006.260.07:45:42.90#ibcon#about to read 4, iclass 35, count 0 2006.260.07:45:42.90#ibcon#read 4, iclass 35, count 0 2006.260.07:45:42.90#ibcon#about to read 5, iclass 35, count 0 2006.260.07:45:42.90#ibcon#read 5, iclass 35, count 0 2006.260.07:45:42.90#ibcon#about to read 6, iclass 35, count 0 2006.260.07:45:42.90#ibcon#read 6, iclass 35, count 0 2006.260.07:45:42.90#ibcon#end of sib2, iclass 35, count 0 2006.260.07:45:42.90#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:45:42.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:45:42.90#ibcon#[25=USB\r\n] 2006.260.07:45:42.90#ibcon#*before write, iclass 35, count 0 2006.260.07:45:42.90#ibcon#enter sib2, iclass 35, count 0 2006.260.07:45:42.90#ibcon#flushed, iclass 35, count 0 2006.260.07:45:42.90#ibcon#about to write, iclass 35, count 0 2006.260.07:45:42.90#ibcon#wrote, iclass 35, count 0 2006.260.07:45:42.90#ibcon#about to read 3, iclass 35, count 0 2006.260.07:45:42.93#ibcon#read 3, iclass 35, count 0 2006.260.07:45:42.93#ibcon#about to read 4, iclass 35, count 0 2006.260.07:45:42.93#ibcon#read 4, iclass 35, count 0 2006.260.07:45:42.93#ibcon#about to read 5, iclass 35, count 0 2006.260.07:45:42.93#ibcon#read 5, iclass 35, count 0 2006.260.07:45:42.93#ibcon#about to read 6, iclass 35, count 0 2006.260.07:45:42.93#ibcon#read 6, iclass 35, count 0 2006.260.07:45:42.93#ibcon#end of sib2, iclass 35, count 0 2006.260.07:45:42.93#ibcon#*after write, iclass 35, count 0 2006.260.07:45:42.93#ibcon#*before return 0, iclass 35, count 0 2006.260.07:45:42.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:42.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:42.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:45:42.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:45:42.93$vc4f8/valo=3,672.99 2006.260.07:45:42.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.07:45:42.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.07:45:42.93#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:42.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:42.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:42.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:42.93#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:45:42.93#ibcon#first serial, iclass 37, count 0 2006.260.07:45:42.93#ibcon#enter sib2, iclass 37, count 0 2006.260.07:45:42.93#ibcon#flushed, iclass 37, count 0 2006.260.07:45:42.93#ibcon#about to write, iclass 37, count 0 2006.260.07:45:42.93#ibcon#wrote, iclass 37, count 0 2006.260.07:45:42.93#ibcon#about to read 3, iclass 37, count 0 2006.260.07:45:42.95#ibcon#read 3, iclass 37, count 0 2006.260.07:45:42.95#ibcon#about to read 4, iclass 37, count 0 2006.260.07:45:42.95#ibcon#read 4, iclass 37, count 0 2006.260.07:45:42.95#ibcon#about to read 5, iclass 37, count 0 2006.260.07:45:42.95#ibcon#read 5, iclass 37, count 0 2006.260.07:45:42.95#ibcon#about to read 6, iclass 37, count 0 2006.260.07:45:42.95#ibcon#read 6, iclass 37, count 0 2006.260.07:45:42.95#ibcon#end of sib2, iclass 37, count 0 2006.260.07:45:42.95#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:45:42.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:45:42.95#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:45:42.95#ibcon#*before write, iclass 37, count 0 2006.260.07:45:42.95#ibcon#enter sib2, iclass 37, count 0 2006.260.07:45:42.95#ibcon#flushed, iclass 37, count 0 2006.260.07:45:42.95#ibcon#about to write, iclass 37, count 0 2006.260.07:45:42.95#ibcon#wrote, iclass 37, count 0 2006.260.07:45:42.95#ibcon#about to read 3, iclass 37, count 0 2006.260.07:45:42.99#ibcon#read 3, iclass 37, count 0 2006.260.07:45:42.99#ibcon#about to read 4, iclass 37, count 0 2006.260.07:45:42.99#ibcon#read 4, iclass 37, count 0 2006.260.07:45:42.99#ibcon#about to read 5, iclass 37, count 0 2006.260.07:45:42.99#ibcon#read 5, iclass 37, count 0 2006.260.07:45:42.99#ibcon#about to read 6, iclass 37, count 0 2006.260.07:45:42.99#ibcon#read 6, iclass 37, count 0 2006.260.07:45:42.99#ibcon#end of sib2, iclass 37, count 0 2006.260.07:45:42.99#ibcon#*after write, iclass 37, count 0 2006.260.07:45:42.99#ibcon#*before return 0, iclass 37, count 0 2006.260.07:45:42.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:42.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:42.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:45:42.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:45:42.99$vc4f8/va=3,8 2006.260.07:45:42.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.07:45:42.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.07:45:42.99#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:42.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:43.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:43.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:43.05#ibcon#enter wrdev, iclass 39, count 2 2006.260.07:45:43.05#ibcon#first serial, iclass 39, count 2 2006.260.07:45:43.05#ibcon#enter sib2, iclass 39, count 2 2006.260.07:45:43.05#ibcon#flushed, iclass 39, count 2 2006.260.07:45:43.05#ibcon#about to write, iclass 39, count 2 2006.260.07:45:43.05#ibcon#wrote, iclass 39, count 2 2006.260.07:45:43.05#ibcon#about to read 3, iclass 39, count 2 2006.260.07:45:43.07#ibcon#read 3, iclass 39, count 2 2006.260.07:45:43.07#ibcon#about to read 4, iclass 39, count 2 2006.260.07:45:43.07#ibcon#read 4, iclass 39, count 2 2006.260.07:45:43.07#ibcon#about to read 5, iclass 39, count 2 2006.260.07:45:43.07#ibcon#read 5, iclass 39, count 2 2006.260.07:45:43.07#ibcon#about to read 6, iclass 39, count 2 2006.260.07:45:43.07#ibcon#read 6, iclass 39, count 2 2006.260.07:45:43.07#ibcon#end of sib2, iclass 39, count 2 2006.260.07:45:43.07#ibcon#*mode == 0, iclass 39, count 2 2006.260.07:45:43.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.07:45:43.07#ibcon#[25=AT03-08\r\n] 2006.260.07:45:43.07#ibcon#*before write, iclass 39, count 2 2006.260.07:45:43.07#ibcon#enter sib2, iclass 39, count 2 2006.260.07:45:43.07#ibcon#flushed, iclass 39, count 2 2006.260.07:45:43.07#ibcon#about to write, iclass 39, count 2 2006.260.07:45:43.07#ibcon#wrote, iclass 39, count 2 2006.260.07:45:43.07#ibcon#about to read 3, iclass 39, count 2 2006.260.07:45:43.10#ibcon#read 3, iclass 39, count 2 2006.260.07:45:43.10#ibcon#about to read 4, iclass 39, count 2 2006.260.07:45:43.10#ibcon#read 4, iclass 39, count 2 2006.260.07:45:43.10#ibcon#about to read 5, iclass 39, count 2 2006.260.07:45:43.10#ibcon#read 5, iclass 39, count 2 2006.260.07:45:43.10#ibcon#about to read 6, iclass 39, count 2 2006.260.07:45:43.10#ibcon#read 6, iclass 39, count 2 2006.260.07:45:43.10#ibcon#end of sib2, iclass 39, count 2 2006.260.07:45:43.10#ibcon#*after write, iclass 39, count 2 2006.260.07:45:43.10#ibcon#*before return 0, iclass 39, count 2 2006.260.07:45:43.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:43.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:43.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.07:45:43.10#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:43.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:43.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:43.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:43.22#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:45:43.22#ibcon#first serial, iclass 39, count 0 2006.260.07:45:43.22#ibcon#enter sib2, iclass 39, count 0 2006.260.07:45:43.22#ibcon#flushed, iclass 39, count 0 2006.260.07:45:43.22#ibcon#about to write, iclass 39, count 0 2006.260.07:45:43.22#ibcon#wrote, iclass 39, count 0 2006.260.07:45:43.22#ibcon#about to read 3, iclass 39, count 0 2006.260.07:45:43.24#ibcon#read 3, iclass 39, count 0 2006.260.07:45:43.24#ibcon#about to read 4, iclass 39, count 0 2006.260.07:45:43.24#ibcon#read 4, iclass 39, count 0 2006.260.07:45:43.24#ibcon#about to read 5, iclass 39, count 0 2006.260.07:45:43.24#ibcon#read 5, iclass 39, count 0 2006.260.07:45:43.24#ibcon#about to read 6, iclass 39, count 0 2006.260.07:45:43.24#ibcon#read 6, iclass 39, count 0 2006.260.07:45:43.24#ibcon#end of sib2, iclass 39, count 0 2006.260.07:45:43.24#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:45:43.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:45:43.24#ibcon#[25=USB\r\n] 2006.260.07:45:43.24#ibcon#*before write, iclass 39, count 0 2006.260.07:45:43.24#ibcon#enter sib2, iclass 39, count 0 2006.260.07:45:43.24#ibcon#flushed, iclass 39, count 0 2006.260.07:45:43.24#ibcon#about to write, iclass 39, count 0 2006.260.07:45:43.24#ibcon#wrote, iclass 39, count 0 2006.260.07:45:43.24#ibcon#about to read 3, iclass 39, count 0 2006.260.07:45:43.27#ibcon#read 3, iclass 39, count 0 2006.260.07:45:43.27#ibcon#about to read 4, iclass 39, count 0 2006.260.07:45:43.27#ibcon#read 4, iclass 39, count 0 2006.260.07:45:43.27#ibcon#about to read 5, iclass 39, count 0 2006.260.07:45:43.27#ibcon#read 5, iclass 39, count 0 2006.260.07:45:43.27#ibcon#about to read 6, iclass 39, count 0 2006.260.07:45:43.27#ibcon#read 6, iclass 39, count 0 2006.260.07:45:43.27#ibcon#end of sib2, iclass 39, count 0 2006.260.07:45:43.27#ibcon#*after write, iclass 39, count 0 2006.260.07:45:43.27#ibcon#*before return 0, iclass 39, count 0 2006.260.07:45:43.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:43.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:43.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:45:43.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:45:43.27$vc4f8/valo=4,832.99 2006.260.07:45:43.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:45:43.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:45:43.27#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:43.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:43.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:43.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:43.27#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:45:43.27#ibcon#first serial, iclass 3, count 0 2006.260.07:45:43.27#ibcon#enter sib2, iclass 3, count 0 2006.260.07:45:43.27#ibcon#flushed, iclass 3, count 0 2006.260.07:45:43.27#ibcon#about to write, iclass 3, count 0 2006.260.07:45:43.27#ibcon#wrote, iclass 3, count 0 2006.260.07:45:43.27#ibcon#about to read 3, iclass 3, count 0 2006.260.07:45:43.29#ibcon#read 3, iclass 3, count 0 2006.260.07:45:43.29#ibcon#about to read 4, iclass 3, count 0 2006.260.07:45:43.29#ibcon#read 4, iclass 3, count 0 2006.260.07:45:43.29#ibcon#about to read 5, iclass 3, count 0 2006.260.07:45:43.29#ibcon#read 5, iclass 3, count 0 2006.260.07:45:43.29#ibcon#about to read 6, iclass 3, count 0 2006.260.07:45:43.29#ibcon#read 6, iclass 3, count 0 2006.260.07:45:43.29#ibcon#end of sib2, iclass 3, count 0 2006.260.07:45:43.29#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:45:43.29#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:45:43.29#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:45:43.29#ibcon#*before write, iclass 3, count 0 2006.260.07:45:43.29#ibcon#enter sib2, iclass 3, count 0 2006.260.07:45:43.29#ibcon#flushed, iclass 3, count 0 2006.260.07:45:43.29#ibcon#about to write, iclass 3, count 0 2006.260.07:45:43.29#ibcon#wrote, iclass 3, count 0 2006.260.07:45:43.29#ibcon#about to read 3, iclass 3, count 0 2006.260.07:45:43.33#ibcon#read 3, iclass 3, count 0 2006.260.07:45:43.33#ibcon#about to read 4, iclass 3, count 0 2006.260.07:45:43.33#ibcon#read 4, iclass 3, count 0 2006.260.07:45:43.33#ibcon#about to read 5, iclass 3, count 0 2006.260.07:45:43.33#ibcon#read 5, iclass 3, count 0 2006.260.07:45:43.33#ibcon#about to read 6, iclass 3, count 0 2006.260.07:45:43.33#ibcon#read 6, iclass 3, count 0 2006.260.07:45:43.33#ibcon#end of sib2, iclass 3, count 0 2006.260.07:45:43.33#ibcon#*after write, iclass 3, count 0 2006.260.07:45:43.33#ibcon#*before return 0, iclass 3, count 0 2006.260.07:45:43.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:43.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:43.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:45:43.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:45:43.33$vc4f8/va=4,7 2006.260.07:45:43.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.07:45:43.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.07:45:43.33#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:43.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:43.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:43.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:43.39#ibcon#enter wrdev, iclass 5, count 2 2006.260.07:45:43.39#ibcon#first serial, iclass 5, count 2 2006.260.07:45:43.39#ibcon#enter sib2, iclass 5, count 2 2006.260.07:45:43.39#ibcon#flushed, iclass 5, count 2 2006.260.07:45:43.39#ibcon#about to write, iclass 5, count 2 2006.260.07:45:43.39#ibcon#wrote, iclass 5, count 2 2006.260.07:45:43.39#ibcon#about to read 3, iclass 5, count 2 2006.260.07:45:43.41#ibcon#read 3, iclass 5, count 2 2006.260.07:45:43.41#ibcon#about to read 4, iclass 5, count 2 2006.260.07:45:43.41#ibcon#read 4, iclass 5, count 2 2006.260.07:45:43.41#ibcon#about to read 5, iclass 5, count 2 2006.260.07:45:43.41#ibcon#read 5, iclass 5, count 2 2006.260.07:45:43.41#ibcon#about to read 6, iclass 5, count 2 2006.260.07:45:43.41#ibcon#read 6, iclass 5, count 2 2006.260.07:45:43.41#ibcon#end of sib2, iclass 5, count 2 2006.260.07:45:43.41#ibcon#*mode == 0, iclass 5, count 2 2006.260.07:45:43.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.07:45:43.41#ibcon#[25=AT04-07\r\n] 2006.260.07:45:43.41#ibcon#*before write, iclass 5, count 2 2006.260.07:45:43.41#ibcon#enter sib2, iclass 5, count 2 2006.260.07:45:43.41#ibcon#flushed, iclass 5, count 2 2006.260.07:45:43.41#ibcon#about to write, iclass 5, count 2 2006.260.07:45:43.41#ibcon#wrote, iclass 5, count 2 2006.260.07:45:43.41#ibcon#about to read 3, iclass 5, count 2 2006.260.07:45:43.44#ibcon#read 3, iclass 5, count 2 2006.260.07:45:43.44#ibcon#about to read 4, iclass 5, count 2 2006.260.07:45:43.44#ibcon#read 4, iclass 5, count 2 2006.260.07:45:43.44#ibcon#about to read 5, iclass 5, count 2 2006.260.07:45:43.44#ibcon#read 5, iclass 5, count 2 2006.260.07:45:43.44#ibcon#about to read 6, iclass 5, count 2 2006.260.07:45:43.44#ibcon#read 6, iclass 5, count 2 2006.260.07:45:43.44#ibcon#end of sib2, iclass 5, count 2 2006.260.07:45:43.44#ibcon#*after write, iclass 5, count 2 2006.260.07:45:43.44#ibcon#*before return 0, iclass 5, count 2 2006.260.07:45:43.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:43.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:43.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.07:45:43.44#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:43.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:43.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:43.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:43.56#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:45:43.56#ibcon#first serial, iclass 5, count 0 2006.260.07:45:43.56#ibcon#enter sib2, iclass 5, count 0 2006.260.07:45:43.56#ibcon#flushed, iclass 5, count 0 2006.260.07:45:43.56#ibcon#about to write, iclass 5, count 0 2006.260.07:45:43.56#ibcon#wrote, iclass 5, count 0 2006.260.07:45:43.56#ibcon#about to read 3, iclass 5, count 0 2006.260.07:45:43.58#ibcon#read 3, iclass 5, count 0 2006.260.07:45:43.58#ibcon#about to read 4, iclass 5, count 0 2006.260.07:45:43.58#ibcon#read 4, iclass 5, count 0 2006.260.07:45:43.58#ibcon#about to read 5, iclass 5, count 0 2006.260.07:45:43.58#ibcon#read 5, iclass 5, count 0 2006.260.07:45:43.58#ibcon#about to read 6, iclass 5, count 0 2006.260.07:45:43.58#ibcon#read 6, iclass 5, count 0 2006.260.07:45:43.58#ibcon#end of sib2, iclass 5, count 0 2006.260.07:45:43.58#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:45:43.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:45:43.58#ibcon#[25=USB\r\n] 2006.260.07:45:43.58#ibcon#*before write, iclass 5, count 0 2006.260.07:45:43.58#ibcon#enter sib2, iclass 5, count 0 2006.260.07:45:43.58#ibcon#flushed, iclass 5, count 0 2006.260.07:45:43.58#ibcon#about to write, iclass 5, count 0 2006.260.07:45:43.58#ibcon#wrote, iclass 5, count 0 2006.260.07:45:43.58#ibcon#about to read 3, iclass 5, count 0 2006.260.07:45:43.61#ibcon#read 3, iclass 5, count 0 2006.260.07:45:43.61#ibcon#about to read 4, iclass 5, count 0 2006.260.07:45:43.61#ibcon#read 4, iclass 5, count 0 2006.260.07:45:43.61#ibcon#about to read 5, iclass 5, count 0 2006.260.07:45:43.61#ibcon#read 5, iclass 5, count 0 2006.260.07:45:43.61#ibcon#about to read 6, iclass 5, count 0 2006.260.07:45:43.61#ibcon#read 6, iclass 5, count 0 2006.260.07:45:43.61#ibcon#end of sib2, iclass 5, count 0 2006.260.07:45:43.61#ibcon#*after write, iclass 5, count 0 2006.260.07:45:43.61#ibcon#*before return 0, iclass 5, count 0 2006.260.07:45:43.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:43.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:43.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:45:43.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:45:43.61$vc4f8/valo=5,652.99 2006.260.07:45:43.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:45:43.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:45:43.61#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:43.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:43.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:43.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:43.61#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:45:43.61#ibcon#first serial, iclass 7, count 0 2006.260.07:45:43.61#ibcon#enter sib2, iclass 7, count 0 2006.260.07:45:43.61#ibcon#flushed, iclass 7, count 0 2006.260.07:45:43.61#ibcon#about to write, iclass 7, count 0 2006.260.07:45:43.61#ibcon#wrote, iclass 7, count 0 2006.260.07:45:43.61#ibcon#about to read 3, iclass 7, count 0 2006.260.07:45:43.63#ibcon#read 3, iclass 7, count 0 2006.260.07:45:43.63#ibcon#about to read 4, iclass 7, count 0 2006.260.07:45:43.63#ibcon#read 4, iclass 7, count 0 2006.260.07:45:43.63#ibcon#about to read 5, iclass 7, count 0 2006.260.07:45:43.63#ibcon#read 5, iclass 7, count 0 2006.260.07:45:43.63#ibcon#about to read 6, iclass 7, count 0 2006.260.07:45:43.63#ibcon#read 6, iclass 7, count 0 2006.260.07:45:43.63#ibcon#end of sib2, iclass 7, count 0 2006.260.07:45:43.63#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:45:43.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:45:43.63#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:45:43.63#ibcon#*before write, iclass 7, count 0 2006.260.07:45:43.63#ibcon#enter sib2, iclass 7, count 0 2006.260.07:45:43.63#ibcon#flushed, iclass 7, count 0 2006.260.07:45:43.63#ibcon#about to write, iclass 7, count 0 2006.260.07:45:43.63#ibcon#wrote, iclass 7, count 0 2006.260.07:45:43.63#ibcon#about to read 3, iclass 7, count 0 2006.260.07:45:43.67#ibcon#read 3, iclass 7, count 0 2006.260.07:45:43.67#ibcon#about to read 4, iclass 7, count 0 2006.260.07:45:43.67#ibcon#read 4, iclass 7, count 0 2006.260.07:45:43.67#ibcon#about to read 5, iclass 7, count 0 2006.260.07:45:43.67#ibcon#read 5, iclass 7, count 0 2006.260.07:45:43.67#ibcon#about to read 6, iclass 7, count 0 2006.260.07:45:43.67#ibcon#read 6, iclass 7, count 0 2006.260.07:45:43.67#ibcon#end of sib2, iclass 7, count 0 2006.260.07:45:43.67#ibcon#*after write, iclass 7, count 0 2006.260.07:45:43.67#ibcon#*before return 0, iclass 7, count 0 2006.260.07:45:43.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:43.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:43.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:45:43.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:45:43.67$vc4f8/va=5,7 2006.260.07:45:43.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:45:43.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:45:43.67#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:43.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:43.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:43.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:43.73#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:45:43.73#ibcon#first serial, iclass 11, count 2 2006.260.07:45:43.73#ibcon#enter sib2, iclass 11, count 2 2006.260.07:45:43.73#ibcon#flushed, iclass 11, count 2 2006.260.07:45:43.73#ibcon#about to write, iclass 11, count 2 2006.260.07:45:43.73#ibcon#wrote, iclass 11, count 2 2006.260.07:45:43.73#ibcon#about to read 3, iclass 11, count 2 2006.260.07:45:43.75#ibcon#read 3, iclass 11, count 2 2006.260.07:45:43.75#ibcon#about to read 4, iclass 11, count 2 2006.260.07:45:43.75#ibcon#read 4, iclass 11, count 2 2006.260.07:45:43.75#ibcon#about to read 5, iclass 11, count 2 2006.260.07:45:43.75#ibcon#read 5, iclass 11, count 2 2006.260.07:45:43.75#ibcon#about to read 6, iclass 11, count 2 2006.260.07:45:43.75#ibcon#read 6, iclass 11, count 2 2006.260.07:45:43.75#ibcon#end of sib2, iclass 11, count 2 2006.260.07:45:43.75#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:45:43.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:45:43.75#ibcon#[25=AT05-07\r\n] 2006.260.07:45:43.75#ibcon#*before write, iclass 11, count 2 2006.260.07:45:43.75#ibcon#enter sib2, iclass 11, count 2 2006.260.07:45:43.75#ibcon#flushed, iclass 11, count 2 2006.260.07:45:43.75#ibcon#about to write, iclass 11, count 2 2006.260.07:45:43.75#ibcon#wrote, iclass 11, count 2 2006.260.07:45:43.75#ibcon#about to read 3, iclass 11, count 2 2006.260.07:45:43.79#ibcon#read 3, iclass 11, count 2 2006.260.07:45:43.79#ibcon#about to read 4, iclass 11, count 2 2006.260.07:45:43.79#ibcon#read 4, iclass 11, count 2 2006.260.07:45:43.79#ibcon#about to read 5, iclass 11, count 2 2006.260.07:45:43.79#ibcon#read 5, iclass 11, count 2 2006.260.07:45:43.79#ibcon#about to read 6, iclass 11, count 2 2006.260.07:45:43.79#ibcon#read 6, iclass 11, count 2 2006.260.07:45:43.79#ibcon#end of sib2, iclass 11, count 2 2006.260.07:45:43.79#ibcon#*after write, iclass 11, count 2 2006.260.07:45:43.79#ibcon#*before return 0, iclass 11, count 2 2006.260.07:45:43.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:43.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:43.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:45:43.79#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:43.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:43.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:43.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:43.91#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:45:43.91#ibcon#first serial, iclass 11, count 0 2006.260.07:45:43.91#ibcon#enter sib2, iclass 11, count 0 2006.260.07:45:43.91#ibcon#flushed, iclass 11, count 0 2006.260.07:45:43.91#ibcon#about to write, iclass 11, count 0 2006.260.07:45:43.91#ibcon#wrote, iclass 11, count 0 2006.260.07:45:43.91#ibcon#about to read 3, iclass 11, count 0 2006.260.07:45:43.93#ibcon#read 3, iclass 11, count 0 2006.260.07:45:43.93#ibcon#about to read 4, iclass 11, count 0 2006.260.07:45:43.93#ibcon#read 4, iclass 11, count 0 2006.260.07:45:43.93#ibcon#about to read 5, iclass 11, count 0 2006.260.07:45:43.93#ibcon#read 5, iclass 11, count 0 2006.260.07:45:43.93#ibcon#about to read 6, iclass 11, count 0 2006.260.07:45:43.93#ibcon#read 6, iclass 11, count 0 2006.260.07:45:43.93#ibcon#end of sib2, iclass 11, count 0 2006.260.07:45:43.93#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:45:43.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:45:43.93#ibcon#[25=USB\r\n] 2006.260.07:45:43.93#ibcon#*before write, iclass 11, count 0 2006.260.07:45:43.93#ibcon#enter sib2, iclass 11, count 0 2006.260.07:45:43.93#ibcon#flushed, iclass 11, count 0 2006.260.07:45:43.93#ibcon#about to write, iclass 11, count 0 2006.260.07:45:43.93#ibcon#wrote, iclass 11, count 0 2006.260.07:45:43.93#ibcon#about to read 3, iclass 11, count 0 2006.260.07:45:43.96#ibcon#read 3, iclass 11, count 0 2006.260.07:45:43.96#ibcon#about to read 4, iclass 11, count 0 2006.260.07:45:43.96#ibcon#read 4, iclass 11, count 0 2006.260.07:45:43.96#ibcon#about to read 5, iclass 11, count 0 2006.260.07:45:43.96#ibcon#read 5, iclass 11, count 0 2006.260.07:45:43.96#ibcon#about to read 6, iclass 11, count 0 2006.260.07:45:43.96#ibcon#read 6, iclass 11, count 0 2006.260.07:45:43.96#ibcon#end of sib2, iclass 11, count 0 2006.260.07:45:43.96#ibcon#*after write, iclass 11, count 0 2006.260.07:45:43.96#ibcon#*before return 0, iclass 11, count 0 2006.260.07:45:43.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:43.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:43.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:45:43.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:45:43.96$vc4f8/valo=6,772.99 2006.260.07:45:43.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:45:43.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:45:43.96#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:43.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:43.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:43.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:43.96#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:45:43.96#ibcon#first serial, iclass 13, count 0 2006.260.07:45:43.96#ibcon#enter sib2, iclass 13, count 0 2006.260.07:45:43.96#ibcon#flushed, iclass 13, count 0 2006.260.07:45:43.96#ibcon#about to write, iclass 13, count 0 2006.260.07:45:43.96#ibcon#wrote, iclass 13, count 0 2006.260.07:45:43.96#ibcon#about to read 3, iclass 13, count 0 2006.260.07:45:43.98#ibcon#read 3, iclass 13, count 0 2006.260.07:45:43.98#ibcon#about to read 4, iclass 13, count 0 2006.260.07:45:43.98#ibcon#read 4, iclass 13, count 0 2006.260.07:45:43.98#ibcon#about to read 5, iclass 13, count 0 2006.260.07:45:43.98#ibcon#read 5, iclass 13, count 0 2006.260.07:45:43.98#ibcon#about to read 6, iclass 13, count 0 2006.260.07:45:43.98#ibcon#read 6, iclass 13, count 0 2006.260.07:45:43.98#ibcon#end of sib2, iclass 13, count 0 2006.260.07:45:43.98#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:45:43.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:45:43.98#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:45:43.98#ibcon#*before write, iclass 13, count 0 2006.260.07:45:43.98#ibcon#enter sib2, iclass 13, count 0 2006.260.07:45:43.98#ibcon#flushed, iclass 13, count 0 2006.260.07:45:43.98#ibcon#about to write, iclass 13, count 0 2006.260.07:45:43.98#ibcon#wrote, iclass 13, count 0 2006.260.07:45:43.98#ibcon#about to read 3, iclass 13, count 0 2006.260.07:45:44.02#ibcon#read 3, iclass 13, count 0 2006.260.07:45:44.02#ibcon#about to read 4, iclass 13, count 0 2006.260.07:45:44.02#ibcon#read 4, iclass 13, count 0 2006.260.07:45:44.02#ibcon#about to read 5, iclass 13, count 0 2006.260.07:45:44.02#ibcon#read 5, iclass 13, count 0 2006.260.07:45:44.02#ibcon#about to read 6, iclass 13, count 0 2006.260.07:45:44.02#ibcon#read 6, iclass 13, count 0 2006.260.07:45:44.02#ibcon#end of sib2, iclass 13, count 0 2006.260.07:45:44.02#ibcon#*after write, iclass 13, count 0 2006.260.07:45:44.02#ibcon#*before return 0, iclass 13, count 0 2006.260.07:45:44.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:44.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:44.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:45:44.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:45:44.02$vc4f8/va=6,6 2006.260.07:45:44.02#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:45:44.02#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:45:44.02#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:44.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:44.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:44.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:44.08#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:45:44.08#ibcon#first serial, iclass 15, count 2 2006.260.07:45:44.08#ibcon#enter sib2, iclass 15, count 2 2006.260.07:45:44.08#ibcon#flushed, iclass 15, count 2 2006.260.07:45:44.08#ibcon#about to write, iclass 15, count 2 2006.260.07:45:44.08#ibcon#wrote, iclass 15, count 2 2006.260.07:45:44.08#ibcon#about to read 3, iclass 15, count 2 2006.260.07:45:44.10#ibcon#read 3, iclass 15, count 2 2006.260.07:45:44.10#ibcon#about to read 4, iclass 15, count 2 2006.260.07:45:44.10#ibcon#read 4, iclass 15, count 2 2006.260.07:45:44.10#ibcon#about to read 5, iclass 15, count 2 2006.260.07:45:44.10#ibcon#read 5, iclass 15, count 2 2006.260.07:45:44.10#ibcon#about to read 6, iclass 15, count 2 2006.260.07:45:44.10#ibcon#read 6, iclass 15, count 2 2006.260.07:45:44.10#ibcon#end of sib2, iclass 15, count 2 2006.260.07:45:44.10#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:45:44.10#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:45:44.10#ibcon#[25=AT06-06\r\n] 2006.260.07:45:44.10#ibcon#*before write, iclass 15, count 2 2006.260.07:45:44.10#ibcon#enter sib2, iclass 15, count 2 2006.260.07:45:44.10#ibcon#flushed, iclass 15, count 2 2006.260.07:45:44.10#ibcon#about to write, iclass 15, count 2 2006.260.07:45:44.10#ibcon#wrote, iclass 15, count 2 2006.260.07:45:44.10#ibcon#about to read 3, iclass 15, count 2 2006.260.07:45:44.13#ibcon#read 3, iclass 15, count 2 2006.260.07:45:44.13#ibcon#about to read 4, iclass 15, count 2 2006.260.07:45:44.13#ibcon#read 4, iclass 15, count 2 2006.260.07:45:44.13#ibcon#about to read 5, iclass 15, count 2 2006.260.07:45:44.13#ibcon#read 5, iclass 15, count 2 2006.260.07:45:44.13#ibcon#about to read 6, iclass 15, count 2 2006.260.07:45:44.13#ibcon#read 6, iclass 15, count 2 2006.260.07:45:44.13#ibcon#end of sib2, iclass 15, count 2 2006.260.07:45:44.13#ibcon#*after write, iclass 15, count 2 2006.260.07:45:44.13#ibcon#*before return 0, iclass 15, count 2 2006.260.07:45:44.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:44.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:44.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:45:44.13#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:44.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:44.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:44.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:44.25#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:45:44.25#ibcon#first serial, iclass 15, count 0 2006.260.07:45:44.25#ibcon#enter sib2, iclass 15, count 0 2006.260.07:45:44.25#ibcon#flushed, iclass 15, count 0 2006.260.07:45:44.25#ibcon#about to write, iclass 15, count 0 2006.260.07:45:44.25#ibcon#wrote, iclass 15, count 0 2006.260.07:45:44.25#ibcon#about to read 3, iclass 15, count 0 2006.260.07:45:44.27#ibcon#read 3, iclass 15, count 0 2006.260.07:45:44.27#ibcon#about to read 4, iclass 15, count 0 2006.260.07:45:44.27#ibcon#read 4, iclass 15, count 0 2006.260.07:45:44.27#ibcon#about to read 5, iclass 15, count 0 2006.260.07:45:44.27#ibcon#read 5, iclass 15, count 0 2006.260.07:45:44.27#ibcon#about to read 6, iclass 15, count 0 2006.260.07:45:44.27#ibcon#read 6, iclass 15, count 0 2006.260.07:45:44.27#ibcon#end of sib2, iclass 15, count 0 2006.260.07:45:44.27#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:45:44.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:45:44.27#ibcon#[25=USB\r\n] 2006.260.07:45:44.27#ibcon#*before write, iclass 15, count 0 2006.260.07:45:44.27#ibcon#enter sib2, iclass 15, count 0 2006.260.07:45:44.27#ibcon#flushed, iclass 15, count 0 2006.260.07:45:44.27#ibcon#about to write, iclass 15, count 0 2006.260.07:45:44.27#ibcon#wrote, iclass 15, count 0 2006.260.07:45:44.27#ibcon#about to read 3, iclass 15, count 0 2006.260.07:45:44.30#abcon#<5=/03 3.6 7.1 23.02 871010.4\r\n> 2006.260.07:45:44.30#ibcon#read 3, iclass 15, count 0 2006.260.07:45:44.30#ibcon#about to read 4, iclass 15, count 0 2006.260.07:45:44.30#ibcon#read 4, iclass 15, count 0 2006.260.07:45:44.30#ibcon#about to read 5, iclass 15, count 0 2006.260.07:45:44.30#ibcon#read 5, iclass 15, count 0 2006.260.07:45:44.30#ibcon#about to read 6, iclass 15, count 0 2006.260.07:45:44.30#ibcon#read 6, iclass 15, count 0 2006.260.07:45:44.30#ibcon#end of sib2, iclass 15, count 0 2006.260.07:45:44.30#ibcon#*after write, iclass 15, count 0 2006.260.07:45:44.30#ibcon#*before return 0, iclass 15, count 0 2006.260.07:45:44.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:44.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:44.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:45:44.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:45:44.30$vc4f8/valo=7,832.99 2006.260.07:45:44.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:45:44.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:45:44.30#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:44.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:45:44.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:45:44.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:45:44.30#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:45:44.30#ibcon#first serial, iclass 20, count 0 2006.260.07:45:44.30#ibcon#enter sib2, iclass 20, count 0 2006.260.07:45:44.30#ibcon#flushed, iclass 20, count 0 2006.260.07:45:44.30#ibcon#about to write, iclass 20, count 0 2006.260.07:45:44.30#ibcon#wrote, iclass 20, count 0 2006.260.07:45:44.30#ibcon#about to read 3, iclass 20, count 0 2006.260.07:45:44.32#abcon#{5=INTERFACE CLEAR} 2006.260.07:45:44.32#ibcon#read 3, iclass 20, count 0 2006.260.07:45:44.32#ibcon#about to read 4, iclass 20, count 0 2006.260.07:45:44.32#ibcon#read 4, iclass 20, count 0 2006.260.07:45:44.32#ibcon#about to read 5, iclass 20, count 0 2006.260.07:45:44.32#ibcon#read 5, iclass 20, count 0 2006.260.07:45:44.32#ibcon#about to read 6, iclass 20, count 0 2006.260.07:45:44.32#ibcon#read 6, iclass 20, count 0 2006.260.07:45:44.32#ibcon#end of sib2, iclass 20, count 0 2006.260.07:45:44.32#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:45:44.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:45:44.32#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:45:44.32#ibcon#*before write, iclass 20, count 0 2006.260.07:45:44.32#ibcon#enter sib2, iclass 20, count 0 2006.260.07:45:44.32#ibcon#flushed, iclass 20, count 0 2006.260.07:45:44.32#ibcon#about to write, iclass 20, count 0 2006.260.07:45:44.32#ibcon#wrote, iclass 20, count 0 2006.260.07:45:44.32#ibcon#about to read 3, iclass 20, count 0 2006.260.07:45:44.36#ibcon#read 3, iclass 20, count 0 2006.260.07:45:44.36#ibcon#about to read 4, iclass 20, count 0 2006.260.07:45:44.36#ibcon#read 4, iclass 20, count 0 2006.260.07:45:44.36#ibcon#about to read 5, iclass 20, count 0 2006.260.07:45:44.36#ibcon#read 5, iclass 20, count 0 2006.260.07:45:44.36#ibcon#about to read 6, iclass 20, count 0 2006.260.07:45:44.36#ibcon#read 6, iclass 20, count 0 2006.260.07:45:44.36#ibcon#end of sib2, iclass 20, count 0 2006.260.07:45:44.36#ibcon#*after write, iclass 20, count 0 2006.260.07:45:44.36#ibcon#*before return 0, iclass 20, count 0 2006.260.07:45:44.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:45:44.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:45:44.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:45:44.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:45:44.36$vc4f8/va=7,6 2006.260.07:45:44.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:45:44.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:45:44.36#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:44.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:45:44.38#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:45:44.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:45:44.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:45:44.42#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:45:44.42#ibcon#first serial, iclass 22, count 2 2006.260.07:45:44.42#ibcon#enter sib2, iclass 22, count 2 2006.260.07:45:44.42#ibcon#flushed, iclass 22, count 2 2006.260.07:45:44.42#ibcon#about to write, iclass 22, count 2 2006.260.07:45:44.42#ibcon#wrote, iclass 22, count 2 2006.260.07:45:44.42#ibcon#about to read 3, iclass 22, count 2 2006.260.07:45:44.44#ibcon#read 3, iclass 22, count 2 2006.260.07:45:44.44#ibcon#about to read 4, iclass 22, count 2 2006.260.07:45:44.44#ibcon#read 4, iclass 22, count 2 2006.260.07:45:44.44#ibcon#about to read 5, iclass 22, count 2 2006.260.07:45:44.44#ibcon#read 5, iclass 22, count 2 2006.260.07:45:44.44#ibcon#about to read 6, iclass 22, count 2 2006.260.07:45:44.44#ibcon#read 6, iclass 22, count 2 2006.260.07:45:44.44#ibcon#end of sib2, iclass 22, count 2 2006.260.07:45:44.44#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:45:44.44#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:45:44.44#ibcon#[25=AT07-06\r\n] 2006.260.07:45:44.44#ibcon#*before write, iclass 22, count 2 2006.260.07:45:44.44#ibcon#enter sib2, iclass 22, count 2 2006.260.07:45:44.44#ibcon#flushed, iclass 22, count 2 2006.260.07:45:44.44#ibcon#about to write, iclass 22, count 2 2006.260.07:45:44.44#ibcon#wrote, iclass 22, count 2 2006.260.07:45:44.44#ibcon#about to read 3, iclass 22, count 2 2006.260.07:45:44.47#ibcon#read 3, iclass 22, count 2 2006.260.07:45:44.47#ibcon#about to read 4, iclass 22, count 2 2006.260.07:45:44.47#ibcon#read 4, iclass 22, count 2 2006.260.07:45:44.47#ibcon#about to read 5, iclass 22, count 2 2006.260.07:45:44.47#ibcon#read 5, iclass 22, count 2 2006.260.07:45:44.47#ibcon#about to read 6, iclass 22, count 2 2006.260.07:45:44.47#ibcon#read 6, iclass 22, count 2 2006.260.07:45:44.47#ibcon#end of sib2, iclass 22, count 2 2006.260.07:45:44.47#ibcon#*after write, iclass 22, count 2 2006.260.07:45:44.47#ibcon#*before return 0, iclass 22, count 2 2006.260.07:45:44.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:45:44.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:45:44.47#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:45:44.47#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:44.47#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:45:44.59#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:45:44.59#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:45:44.59#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:45:44.59#ibcon#first serial, iclass 22, count 0 2006.260.07:45:44.59#ibcon#enter sib2, iclass 22, count 0 2006.260.07:45:44.59#ibcon#flushed, iclass 22, count 0 2006.260.07:45:44.59#ibcon#about to write, iclass 22, count 0 2006.260.07:45:44.59#ibcon#wrote, iclass 22, count 0 2006.260.07:45:44.59#ibcon#about to read 3, iclass 22, count 0 2006.260.07:45:44.61#ibcon#read 3, iclass 22, count 0 2006.260.07:45:44.61#ibcon#about to read 4, iclass 22, count 0 2006.260.07:45:44.61#ibcon#read 4, iclass 22, count 0 2006.260.07:45:44.61#ibcon#about to read 5, iclass 22, count 0 2006.260.07:45:44.61#ibcon#read 5, iclass 22, count 0 2006.260.07:45:44.61#ibcon#about to read 6, iclass 22, count 0 2006.260.07:45:44.61#ibcon#read 6, iclass 22, count 0 2006.260.07:45:44.61#ibcon#end of sib2, iclass 22, count 0 2006.260.07:45:44.61#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:45:44.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:45:44.61#ibcon#[25=USB\r\n] 2006.260.07:45:44.61#ibcon#*before write, iclass 22, count 0 2006.260.07:45:44.61#ibcon#enter sib2, iclass 22, count 0 2006.260.07:45:44.61#ibcon#flushed, iclass 22, count 0 2006.260.07:45:44.61#ibcon#about to write, iclass 22, count 0 2006.260.07:45:44.61#ibcon#wrote, iclass 22, count 0 2006.260.07:45:44.61#ibcon#about to read 3, iclass 22, count 0 2006.260.07:45:44.64#ibcon#read 3, iclass 22, count 0 2006.260.07:45:44.64#ibcon#about to read 4, iclass 22, count 0 2006.260.07:45:44.64#ibcon#read 4, iclass 22, count 0 2006.260.07:45:44.64#ibcon#about to read 5, iclass 22, count 0 2006.260.07:45:44.64#ibcon#read 5, iclass 22, count 0 2006.260.07:45:44.64#ibcon#about to read 6, iclass 22, count 0 2006.260.07:45:44.64#ibcon#read 6, iclass 22, count 0 2006.260.07:45:44.64#ibcon#end of sib2, iclass 22, count 0 2006.260.07:45:44.64#ibcon#*after write, iclass 22, count 0 2006.260.07:45:44.64#ibcon#*before return 0, iclass 22, count 0 2006.260.07:45:44.64#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:45:44.64#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:45:44.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:45:44.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:45:44.64$vc4f8/valo=8,852.99 2006.260.07:45:44.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.07:45:44.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.07:45:44.64#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:44.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:45:44.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:45:44.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:45:44.64#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:45:44.64#ibcon#first serial, iclass 25, count 0 2006.260.07:45:44.64#ibcon#enter sib2, iclass 25, count 0 2006.260.07:45:44.64#ibcon#flushed, iclass 25, count 0 2006.260.07:45:44.64#ibcon#about to write, iclass 25, count 0 2006.260.07:45:44.64#ibcon#wrote, iclass 25, count 0 2006.260.07:45:44.64#ibcon#about to read 3, iclass 25, count 0 2006.260.07:45:44.66#ibcon#read 3, iclass 25, count 0 2006.260.07:45:44.66#ibcon#about to read 4, iclass 25, count 0 2006.260.07:45:44.66#ibcon#read 4, iclass 25, count 0 2006.260.07:45:44.66#ibcon#about to read 5, iclass 25, count 0 2006.260.07:45:44.66#ibcon#read 5, iclass 25, count 0 2006.260.07:45:44.66#ibcon#about to read 6, iclass 25, count 0 2006.260.07:45:44.66#ibcon#read 6, iclass 25, count 0 2006.260.07:45:44.66#ibcon#end of sib2, iclass 25, count 0 2006.260.07:45:44.66#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:45:44.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:45:44.66#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:45:44.66#ibcon#*before write, iclass 25, count 0 2006.260.07:45:44.66#ibcon#enter sib2, iclass 25, count 0 2006.260.07:45:44.66#ibcon#flushed, iclass 25, count 0 2006.260.07:45:44.66#ibcon#about to write, iclass 25, count 0 2006.260.07:45:44.66#ibcon#wrote, iclass 25, count 0 2006.260.07:45:44.66#ibcon#about to read 3, iclass 25, count 0 2006.260.07:45:44.70#ibcon#read 3, iclass 25, count 0 2006.260.07:45:44.70#ibcon#about to read 4, iclass 25, count 0 2006.260.07:45:44.70#ibcon#read 4, iclass 25, count 0 2006.260.07:45:44.70#ibcon#about to read 5, iclass 25, count 0 2006.260.07:45:44.70#ibcon#read 5, iclass 25, count 0 2006.260.07:45:44.70#ibcon#about to read 6, iclass 25, count 0 2006.260.07:45:44.70#ibcon#read 6, iclass 25, count 0 2006.260.07:45:44.70#ibcon#end of sib2, iclass 25, count 0 2006.260.07:45:44.70#ibcon#*after write, iclass 25, count 0 2006.260.07:45:44.70#ibcon#*before return 0, iclass 25, count 0 2006.260.07:45:44.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:45:44.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:45:44.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:45:44.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:45:44.70$vc4f8/va=8,6 2006.260.07:45:44.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.07:45:44.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.07:45:44.70#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:44.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:45:44.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:45:44.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:45:44.76#ibcon#enter wrdev, iclass 27, count 2 2006.260.07:45:44.76#ibcon#first serial, iclass 27, count 2 2006.260.07:45:44.76#ibcon#enter sib2, iclass 27, count 2 2006.260.07:45:44.76#ibcon#flushed, iclass 27, count 2 2006.260.07:45:44.76#ibcon#about to write, iclass 27, count 2 2006.260.07:45:44.76#ibcon#wrote, iclass 27, count 2 2006.260.07:45:44.76#ibcon#about to read 3, iclass 27, count 2 2006.260.07:45:44.78#ibcon#read 3, iclass 27, count 2 2006.260.07:45:44.78#ibcon#about to read 4, iclass 27, count 2 2006.260.07:45:44.78#ibcon#read 4, iclass 27, count 2 2006.260.07:45:44.78#ibcon#about to read 5, iclass 27, count 2 2006.260.07:45:44.78#ibcon#read 5, iclass 27, count 2 2006.260.07:45:44.78#ibcon#about to read 6, iclass 27, count 2 2006.260.07:45:44.78#ibcon#read 6, iclass 27, count 2 2006.260.07:45:44.78#ibcon#end of sib2, iclass 27, count 2 2006.260.07:45:44.78#ibcon#*mode == 0, iclass 27, count 2 2006.260.07:45:44.78#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.07:45:44.78#ibcon#[25=AT08-06\r\n] 2006.260.07:45:44.78#ibcon#*before write, iclass 27, count 2 2006.260.07:45:44.78#ibcon#enter sib2, iclass 27, count 2 2006.260.07:45:44.78#ibcon#flushed, iclass 27, count 2 2006.260.07:45:44.78#ibcon#about to write, iclass 27, count 2 2006.260.07:45:44.78#ibcon#wrote, iclass 27, count 2 2006.260.07:45:44.78#ibcon#about to read 3, iclass 27, count 2 2006.260.07:45:44.81#ibcon#read 3, iclass 27, count 2 2006.260.07:45:44.81#ibcon#about to read 4, iclass 27, count 2 2006.260.07:45:44.81#ibcon#read 4, iclass 27, count 2 2006.260.07:45:44.81#ibcon#about to read 5, iclass 27, count 2 2006.260.07:45:44.81#ibcon#read 5, iclass 27, count 2 2006.260.07:45:44.81#ibcon#about to read 6, iclass 27, count 2 2006.260.07:45:44.81#ibcon#read 6, iclass 27, count 2 2006.260.07:45:44.81#ibcon#end of sib2, iclass 27, count 2 2006.260.07:45:44.81#ibcon#*after write, iclass 27, count 2 2006.260.07:45:44.81#ibcon#*before return 0, iclass 27, count 2 2006.260.07:45:44.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:45:44.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:45:44.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.07:45:44.81#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:44.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:45:44.93#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:45:44.93#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:45:44.93#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:45:44.93#ibcon#first serial, iclass 27, count 0 2006.260.07:45:44.93#ibcon#enter sib2, iclass 27, count 0 2006.260.07:45:44.93#ibcon#flushed, iclass 27, count 0 2006.260.07:45:44.93#ibcon#about to write, iclass 27, count 0 2006.260.07:45:44.93#ibcon#wrote, iclass 27, count 0 2006.260.07:45:44.93#ibcon#about to read 3, iclass 27, count 0 2006.260.07:45:44.95#ibcon#read 3, iclass 27, count 0 2006.260.07:45:44.95#ibcon#about to read 4, iclass 27, count 0 2006.260.07:45:44.95#ibcon#read 4, iclass 27, count 0 2006.260.07:45:44.95#ibcon#about to read 5, iclass 27, count 0 2006.260.07:45:44.95#ibcon#read 5, iclass 27, count 0 2006.260.07:45:44.95#ibcon#about to read 6, iclass 27, count 0 2006.260.07:45:44.95#ibcon#read 6, iclass 27, count 0 2006.260.07:45:44.95#ibcon#end of sib2, iclass 27, count 0 2006.260.07:45:44.95#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:45:44.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:45:44.95#ibcon#[25=USB\r\n] 2006.260.07:45:44.95#ibcon#*before write, iclass 27, count 0 2006.260.07:45:44.95#ibcon#enter sib2, iclass 27, count 0 2006.260.07:45:44.95#ibcon#flushed, iclass 27, count 0 2006.260.07:45:44.95#ibcon#about to write, iclass 27, count 0 2006.260.07:45:44.95#ibcon#wrote, iclass 27, count 0 2006.260.07:45:44.95#ibcon#about to read 3, iclass 27, count 0 2006.260.07:45:44.98#ibcon#read 3, iclass 27, count 0 2006.260.07:45:44.98#ibcon#about to read 4, iclass 27, count 0 2006.260.07:45:44.98#ibcon#read 4, iclass 27, count 0 2006.260.07:45:44.98#ibcon#about to read 5, iclass 27, count 0 2006.260.07:45:44.98#ibcon#read 5, iclass 27, count 0 2006.260.07:45:44.98#ibcon#about to read 6, iclass 27, count 0 2006.260.07:45:44.98#ibcon#read 6, iclass 27, count 0 2006.260.07:45:44.98#ibcon#end of sib2, iclass 27, count 0 2006.260.07:45:44.98#ibcon#*after write, iclass 27, count 0 2006.260.07:45:44.98#ibcon#*before return 0, iclass 27, count 0 2006.260.07:45:44.98#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:45:44.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:45:44.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:45:44.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:45:44.98$vc4f8/vblo=1,632.99 2006.260.07:45:44.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.07:45:44.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.07:45:44.98#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:44.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:44.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:44.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:44.98#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:45:44.98#ibcon#first serial, iclass 29, count 0 2006.260.07:45:44.98#ibcon#enter sib2, iclass 29, count 0 2006.260.07:45:44.98#ibcon#flushed, iclass 29, count 0 2006.260.07:45:44.98#ibcon#about to write, iclass 29, count 0 2006.260.07:45:44.98#ibcon#wrote, iclass 29, count 0 2006.260.07:45:44.98#ibcon#about to read 3, iclass 29, count 0 2006.260.07:45:45.00#ibcon#read 3, iclass 29, count 0 2006.260.07:45:45.00#ibcon#about to read 4, iclass 29, count 0 2006.260.07:45:45.00#ibcon#read 4, iclass 29, count 0 2006.260.07:45:45.00#ibcon#about to read 5, iclass 29, count 0 2006.260.07:45:45.00#ibcon#read 5, iclass 29, count 0 2006.260.07:45:45.00#ibcon#about to read 6, iclass 29, count 0 2006.260.07:45:45.00#ibcon#read 6, iclass 29, count 0 2006.260.07:45:45.00#ibcon#end of sib2, iclass 29, count 0 2006.260.07:45:45.00#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:45:45.00#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:45:45.00#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:45:45.00#ibcon#*before write, iclass 29, count 0 2006.260.07:45:45.00#ibcon#enter sib2, iclass 29, count 0 2006.260.07:45:45.00#ibcon#flushed, iclass 29, count 0 2006.260.07:45:45.00#ibcon#about to write, iclass 29, count 0 2006.260.07:45:45.00#ibcon#wrote, iclass 29, count 0 2006.260.07:45:45.00#ibcon#about to read 3, iclass 29, count 0 2006.260.07:45:45.04#ibcon#read 3, iclass 29, count 0 2006.260.07:45:45.04#ibcon#about to read 4, iclass 29, count 0 2006.260.07:45:45.04#ibcon#read 4, iclass 29, count 0 2006.260.07:45:45.04#ibcon#about to read 5, iclass 29, count 0 2006.260.07:45:45.04#ibcon#read 5, iclass 29, count 0 2006.260.07:45:45.04#ibcon#about to read 6, iclass 29, count 0 2006.260.07:45:45.04#ibcon#read 6, iclass 29, count 0 2006.260.07:45:45.04#ibcon#end of sib2, iclass 29, count 0 2006.260.07:45:45.04#ibcon#*after write, iclass 29, count 0 2006.260.07:45:45.04#ibcon#*before return 0, iclass 29, count 0 2006.260.07:45:45.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:45.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:45:45.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:45:45.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:45:45.04$vc4f8/vb=1,4 2006.260.07:45:45.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.07:45:45.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.07:45:45.04#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:45.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:45.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:45.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:45.04#ibcon#enter wrdev, iclass 31, count 2 2006.260.07:45:45.04#ibcon#first serial, iclass 31, count 2 2006.260.07:45:45.04#ibcon#enter sib2, iclass 31, count 2 2006.260.07:45:45.04#ibcon#flushed, iclass 31, count 2 2006.260.07:45:45.04#ibcon#about to write, iclass 31, count 2 2006.260.07:45:45.04#ibcon#wrote, iclass 31, count 2 2006.260.07:45:45.04#ibcon#about to read 3, iclass 31, count 2 2006.260.07:45:45.06#ibcon#read 3, iclass 31, count 2 2006.260.07:45:45.06#ibcon#about to read 4, iclass 31, count 2 2006.260.07:45:45.06#ibcon#read 4, iclass 31, count 2 2006.260.07:45:45.06#ibcon#about to read 5, iclass 31, count 2 2006.260.07:45:45.06#ibcon#read 5, iclass 31, count 2 2006.260.07:45:45.06#ibcon#about to read 6, iclass 31, count 2 2006.260.07:45:45.06#ibcon#read 6, iclass 31, count 2 2006.260.07:45:45.06#ibcon#end of sib2, iclass 31, count 2 2006.260.07:45:45.06#ibcon#*mode == 0, iclass 31, count 2 2006.260.07:45:45.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.07:45:45.06#ibcon#[27=AT01-04\r\n] 2006.260.07:45:45.06#ibcon#*before write, iclass 31, count 2 2006.260.07:45:45.06#ibcon#enter sib2, iclass 31, count 2 2006.260.07:45:45.06#ibcon#flushed, iclass 31, count 2 2006.260.07:45:45.06#ibcon#about to write, iclass 31, count 2 2006.260.07:45:45.06#ibcon#wrote, iclass 31, count 2 2006.260.07:45:45.06#ibcon#about to read 3, iclass 31, count 2 2006.260.07:45:45.09#ibcon#read 3, iclass 31, count 2 2006.260.07:45:45.09#ibcon#about to read 4, iclass 31, count 2 2006.260.07:45:45.09#ibcon#read 4, iclass 31, count 2 2006.260.07:45:45.09#ibcon#about to read 5, iclass 31, count 2 2006.260.07:45:45.09#ibcon#read 5, iclass 31, count 2 2006.260.07:45:45.09#ibcon#about to read 6, iclass 31, count 2 2006.260.07:45:45.09#ibcon#read 6, iclass 31, count 2 2006.260.07:45:45.09#ibcon#end of sib2, iclass 31, count 2 2006.260.07:45:45.09#ibcon#*after write, iclass 31, count 2 2006.260.07:45:45.09#ibcon#*before return 0, iclass 31, count 2 2006.260.07:45:45.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:45.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:45:45.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.07:45:45.09#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:45.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:45.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:45.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:45.21#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:45:45.21#ibcon#first serial, iclass 31, count 0 2006.260.07:45:45.21#ibcon#enter sib2, iclass 31, count 0 2006.260.07:45:45.21#ibcon#flushed, iclass 31, count 0 2006.260.07:45:45.21#ibcon#about to write, iclass 31, count 0 2006.260.07:45:45.21#ibcon#wrote, iclass 31, count 0 2006.260.07:45:45.21#ibcon#about to read 3, iclass 31, count 0 2006.260.07:45:45.23#ibcon#read 3, iclass 31, count 0 2006.260.07:45:45.23#ibcon#about to read 4, iclass 31, count 0 2006.260.07:45:45.23#ibcon#read 4, iclass 31, count 0 2006.260.07:45:45.23#ibcon#about to read 5, iclass 31, count 0 2006.260.07:45:45.23#ibcon#read 5, iclass 31, count 0 2006.260.07:45:45.23#ibcon#about to read 6, iclass 31, count 0 2006.260.07:45:45.23#ibcon#read 6, iclass 31, count 0 2006.260.07:45:45.23#ibcon#end of sib2, iclass 31, count 0 2006.260.07:45:45.23#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:45:45.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:45:45.23#ibcon#[27=USB\r\n] 2006.260.07:45:45.23#ibcon#*before write, iclass 31, count 0 2006.260.07:45:45.23#ibcon#enter sib2, iclass 31, count 0 2006.260.07:45:45.23#ibcon#flushed, iclass 31, count 0 2006.260.07:45:45.23#ibcon#about to write, iclass 31, count 0 2006.260.07:45:45.23#ibcon#wrote, iclass 31, count 0 2006.260.07:45:45.23#ibcon#about to read 3, iclass 31, count 0 2006.260.07:45:45.26#ibcon#read 3, iclass 31, count 0 2006.260.07:45:45.26#ibcon#about to read 4, iclass 31, count 0 2006.260.07:45:45.26#ibcon#read 4, iclass 31, count 0 2006.260.07:45:45.26#ibcon#about to read 5, iclass 31, count 0 2006.260.07:45:45.26#ibcon#read 5, iclass 31, count 0 2006.260.07:45:45.26#ibcon#about to read 6, iclass 31, count 0 2006.260.07:45:45.26#ibcon#read 6, iclass 31, count 0 2006.260.07:45:45.26#ibcon#end of sib2, iclass 31, count 0 2006.260.07:45:45.26#ibcon#*after write, iclass 31, count 0 2006.260.07:45:45.26#ibcon#*before return 0, iclass 31, count 0 2006.260.07:45:45.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:45.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:45:45.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:45:45.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:45:45.26$vc4f8/vblo=2,640.99 2006.260.07:45:45.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.07:45:45.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.07:45:45.26#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:45.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:45.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:45.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:45.26#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:45:45.26#ibcon#first serial, iclass 33, count 0 2006.260.07:45:45.26#ibcon#enter sib2, iclass 33, count 0 2006.260.07:45:45.26#ibcon#flushed, iclass 33, count 0 2006.260.07:45:45.26#ibcon#about to write, iclass 33, count 0 2006.260.07:45:45.26#ibcon#wrote, iclass 33, count 0 2006.260.07:45:45.26#ibcon#about to read 3, iclass 33, count 0 2006.260.07:45:45.28#ibcon#read 3, iclass 33, count 0 2006.260.07:45:45.28#ibcon#about to read 4, iclass 33, count 0 2006.260.07:45:45.28#ibcon#read 4, iclass 33, count 0 2006.260.07:45:45.28#ibcon#about to read 5, iclass 33, count 0 2006.260.07:45:45.28#ibcon#read 5, iclass 33, count 0 2006.260.07:45:45.28#ibcon#about to read 6, iclass 33, count 0 2006.260.07:45:45.28#ibcon#read 6, iclass 33, count 0 2006.260.07:45:45.28#ibcon#end of sib2, iclass 33, count 0 2006.260.07:45:45.28#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:45:45.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:45:45.28#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:45:45.28#ibcon#*before write, iclass 33, count 0 2006.260.07:45:45.28#ibcon#enter sib2, iclass 33, count 0 2006.260.07:45:45.28#ibcon#flushed, iclass 33, count 0 2006.260.07:45:45.28#ibcon#about to write, iclass 33, count 0 2006.260.07:45:45.28#ibcon#wrote, iclass 33, count 0 2006.260.07:45:45.28#ibcon#about to read 3, iclass 33, count 0 2006.260.07:45:45.32#ibcon#read 3, iclass 33, count 0 2006.260.07:45:45.32#ibcon#about to read 4, iclass 33, count 0 2006.260.07:45:45.32#ibcon#read 4, iclass 33, count 0 2006.260.07:45:45.32#ibcon#about to read 5, iclass 33, count 0 2006.260.07:45:45.32#ibcon#read 5, iclass 33, count 0 2006.260.07:45:45.32#ibcon#about to read 6, iclass 33, count 0 2006.260.07:45:45.32#ibcon#read 6, iclass 33, count 0 2006.260.07:45:45.32#ibcon#end of sib2, iclass 33, count 0 2006.260.07:45:45.32#ibcon#*after write, iclass 33, count 0 2006.260.07:45:45.32#ibcon#*before return 0, iclass 33, count 0 2006.260.07:45:45.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:45.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:45:45.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:45:45.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:45:45.32$vc4f8/vb=2,5 2006.260.07:45:45.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.07:45:45.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.07:45:45.32#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:45.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:45.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:45.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:45.38#ibcon#enter wrdev, iclass 35, count 2 2006.260.07:45:45.38#ibcon#first serial, iclass 35, count 2 2006.260.07:45:45.38#ibcon#enter sib2, iclass 35, count 2 2006.260.07:45:45.38#ibcon#flushed, iclass 35, count 2 2006.260.07:45:45.38#ibcon#about to write, iclass 35, count 2 2006.260.07:45:45.38#ibcon#wrote, iclass 35, count 2 2006.260.07:45:45.38#ibcon#about to read 3, iclass 35, count 2 2006.260.07:45:45.40#ibcon#read 3, iclass 35, count 2 2006.260.07:45:45.40#ibcon#about to read 4, iclass 35, count 2 2006.260.07:45:45.40#ibcon#read 4, iclass 35, count 2 2006.260.07:45:45.40#ibcon#about to read 5, iclass 35, count 2 2006.260.07:45:45.40#ibcon#read 5, iclass 35, count 2 2006.260.07:45:45.40#ibcon#about to read 6, iclass 35, count 2 2006.260.07:45:45.40#ibcon#read 6, iclass 35, count 2 2006.260.07:45:45.40#ibcon#end of sib2, iclass 35, count 2 2006.260.07:45:45.40#ibcon#*mode == 0, iclass 35, count 2 2006.260.07:45:45.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.07:45:45.40#ibcon#[27=AT02-05\r\n] 2006.260.07:45:45.40#ibcon#*before write, iclass 35, count 2 2006.260.07:45:45.40#ibcon#enter sib2, iclass 35, count 2 2006.260.07:45:45.40#ibcon#flushed, iclass 35, count 2 2006.260.07:45:45.40#ibcon#about to write, iclass 35, count 2 2006.260.07:45:45.40#ibcon#wrote, iclass 35, count 2 2006.260.07:45:45.40#ibcon#about to read 3, iclass 35, count 2 2006.260.07:45:45.44#ibcon#read 3, iclass 35, count 2 2006.260.07:45:45.44#ibcon#about to read 4, iclass 35, count 2 2006.260.07:45:45.44#ibcon#read 4, iclass 35, count 2 2006.260.07:45:45.44#ibcon#about to read 5, iclass 35, count 2 2006.260.07:45:45.44#ibcon#read 5, iclass 35, count 2 2006.260.07:45:45.44#ibcon#about to read 6, iclass 35, count 2 2006.260.07:45:45.44#ibcon#read 6, iclass 35, count 2 2006.260.07:45:45.44#ibcon#end of sib2, iclass 35, count 2 2006.260.07:45:45.44#ibcon#*after write, iclass 35, count 2 2006.260.07:45:45.44#ibcon#*before return 0, iclass 35, count 2 2006.260.07:45:45.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:45.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:45:45.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.07:45:45.44#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:45.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:45.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:45.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:45.56#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:45:45.56#ibcon#first serial, iclass 35, count 0 2006.260.07:45:45.56#ibcon#enter sib2, iclass 35, count 0 2006.260.07:45:45.56#ibcon#flushed, iclass 35, count 0 2006.260.07:45:45.56#ibcon#about to write, iclass 35, count 0 2006.260.07:45:45.56#ibcon#wrote, iclass 35, count 0 2006.260.07:45:45.56#ibcon#about to read 3, iclass 35, count 0 2006.260.07:45:45.58#ibcon#read 3, iclass 35, count 0 2006.260.07:45:45.58#ibcon#about to read 4, iclass 35, count 0 2006.260.07:45:45.58#ibcon#read 4, iclass 35, count 0 2006.260.07:45:45.58#ibcon#about to read 5, iclass 35, count 0 2006.260.07:45:45.58#ibcon#read 5, iclass 35, count 0 2006.260.07:45:45.58#ibcon#about to read 6, iclass 35, count 0 2006.260.07:45:45.58#ibcon#read 6, iclass 35, count 0 2006.260.07:45:45.58#ibcon#end of sib2, iclass 35, count 0 2006.260.07:45:45.58#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:45:45.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:45:45.58#ibcon#[27=USB\r\n] 2006.260.07:45:45.58#ibcon#*before write, iclass 35, count 0 2006.260.07:45:45.58#ibcon#enter sib2, iclass 35, count 0 2006.260.07:45:45.58#ibcon#flushed, iclass 35, count 0 2006.260.07:45:45.58#ibcon#about to write, iclass 35, count 0 2006.260.07:45:45.58#ibcon#wrote, iclass 35, count 0 2006.260.07:45:45.58#ibcon#about to read 3, iclass 35, count 0 2006.260.07:45:45.61#ibcon#read 3, iclass 35, count 0 2006.260.07:45:45.61#ibcon#about to read 4, iclass 35, count 0 2006.260.07:45:45.61#ibcon#read 4, iclass 35, count 0 2006.260.07:45:45.61#ibcon#about to read 5, iclass 35, count 0 2006.260.07:45:45.61#ibcon#read 5, iclass 35, count 0 2006.260.07:45:45.61#ibcon#about to read 6, iclass 35, count 0 2006.260.07:45:45.61#ibcon#read 6, iclass 35, count 0 2006.260.07:45:45.61#ibcon#end of sib2, iclass 35, count 0 2006.260.07:45:45.61#ibcon#*after write, iclass 35, count 0 2006.260.07:45:45.61#ibcon#*before return 0, iclass 35, count 0 2006.260.07:45:45.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:45.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:45:45.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:45:45.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:45:45.61$vc4f8/vblo=3,656.99 2006.260.07:45:45.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.07:45:45.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.07:45:45.61#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:45.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:45.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:45.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:45.61#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:45:45.61#ibcon#first serial, iclass 37, count 0 2006.260.07:45:45.61#ibcon#enter sib2, iclass 37, count 0 2006.260.07:45:45.61#ibcon#flushed, iclass 37, count 0 2006.260.07:45:45.61#ibcon#about to write, iclass 37, count 0 2006.260.07:45:45.61#ibcon#wrote, iclass 37, count 0 2006.260.07:45:45.61#ibcon#about to read 3, iclass 37, count 0 2006.260.07:45:45.63#ibcon#read 3, iclass 37, count 0 2006.260.07:45:45.63#ibcon#about to read 4, iclass 37, count 0 2006.260.07:45:45.63#ibcon#read 4, iclass 37, count 0 2006.260.07:45:45.63#ibcon#about to read 5, iclass 37, count 0 2006.260.07:45:45.63#ibcon#read 5, iclass 37, count 0 2006.260.07:45:45.63#ibcon#about to read 6, iclass 37, count 0 2006.260.07:45:45.63#ibcon#read 6, iclass 37, count 0 2006.260.07:45:45.63#ibcon#end of sib2, iclass 37, count 0 2006.260.07:45:45.63#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:45:45.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:45:45.63#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:45:45.63#ibcon#*before write, iclass 37, count 0 2006.260.07:45:45.63#ibcon#enter sib2, iclass 37, count 0 2006.260.07:45:45.63#ibcon#flushed, iclass 37, count 0 2006.260.07:45:45.63#ibcon#about to write, iclass 37, count 0 2006.260.07:45:45.63#ibcon#wrote, iclass 37, count 0 2006.260.07:45:45.63#ibcon#about to read 3, iclass 37, count 0 2006.260.07:45:45.67#ibcon#read 3, iclass 37, count 0 2006.260.07:45:45.67#ibcon#about to read 4, iclass 37, count 0 2006.260.07:45:45.67#ibcon#read 4, iclass 37, count 0 2006.260.07:45:45.67#ibcon#about to read 5, iclass 37, count 0 2006.260.07:45:45.67#ibcon#read 5, iclass 37, count 0 2006.260.07:45:45.67#ibcon#about to read 6, iclass 37, count 0 2006.260.07:45:45.67#ibcon#read 6, iclass 37, count 0 2006.260.07:45:45.67#ibcon#end of sib2, iclass 37, count 0 2006.260.07:45:45.67#ibcon#*after write, iclass 37, count 0 2006.260.07:45:45.67#ibcon#*before return 0, iclass 37, count 0 2006.260.07:45:45.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:45.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:45:45.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:45:45.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:45:45.67$vc4f8/vb=3,4 2006.260.07:45:45.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.07:45:45.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.07:45:45.67#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:45.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:45.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:45.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:45.73#ibcon#enter wrdev, iclass 39, count 2 2006.260.07:45:45.73#ibcon#first serial, iclass 39, count 2 2006.260.07:45:45.73#ibcon#enter sib2, iclass 39, count 2 2006.260.07:45:45.73#ibcon#flushed, iclass 39, count 2 2006.260.07:45:45.73#ibcon#about to write, iclass 39, count 2 2006.260.07:45:45.73#ibcon#wrote, iclass 39, count 2 2006.260.07:45:45.73#ibcon#about to read 3, iclass 39, count 2 2006.260.07:45:45.75#ibcon#read 3, iclass 39, count 2 2006.260.07:45:45.75#ibcon#about to read 4, iclass 39, count 2 2006.260.07:45:45.75#ibcon#read 4, iclass 39, count 2 2006.260.07:45:45.75#ibcon#about to read 5, iclass 39, count 2 2006.260.07:45:45.75#ibcon#read 5, iclass 39, count 2 2006.260.07:45:45.75#ibcon#about to read 6, iclass 39, count 2 2006.260.07:45:45.75#ibcon#read 6, iclass 39, count 2 2006.260.07:45:45.75#ibcon#end of sib2, iclass 39, count 2 2006.260.07:45:45.75#ibcon#*mode == 0, iclass 39, count 2 2006.260.07:45:45.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.07:45:45.75#ibcon#[27=AT03-04\r\n] 2006.260.07:45:45.75#ibcon#*before write, iclass 39, count 2 2006.260.07:45:45.75#ibcon#enter sib2, iclass 39, count 2 2006.260.07:45:45.75#ibcon#flushed, iclass 39, count 2 2006.260.07:45:45.75#ibcon#about to write, iclass 39, count 2 2006.260.07:45:45.75#ibcon#wrote, iclass 39, count 2 2006.260.07:45:45.75#ibcon#about to read 3, iclass 39, count 2 2006.260.07:45:45.78#ibcon#read 3, iclass 39, count 2 2006.260.07:45:45.78#ibcon#about to read 4, iclass 39, count 2 2006.260.07:45:45.78#ibcon#read 4, iclass 39, count 2 2006.260.07:45:45.78#ibcon#about to read 5, iclass 39, count 2 2006.260.07:45:45.78#ibcon#read 5, iclass 39, count 2 2006.260.07:45:45.78#ibcon#about to read 6, iclass 39, count 2 2006.260.07:45:45.78#ibcon#read 6, iclass 39, count 2 2006.260.07:45:45.78#ibcon#end of sib2, iclass 39, count 2 2006.260.07:45:45.78#ibcon#*after write, iclass 39, count 2 2006.260.07:45:45.78#ibcon#*before return 0, iclass 39, count 2 2006.260.07:45:45.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:45.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:45:45.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.07:45:45.78#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:45.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:45.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:45.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:45.90#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:45:45.90#ibcon#first serial, iclass 39, count 0 2006.260.07:45:45.90#ibcon#enter sib2, iclass 39, count 0 2006.260.07:45:45.90#ibcon#flushed, iclass 39, count 0 2006.260.07:45:45.90#ibcon#about to write, iclass 39, count 0 2006.260.07:45:45.90#ibcon#wrote, iclass 39, count 0 2006.260.07:45:45.90#ibcon#about to read 3, iclass 39, count 0 2006.260.07:45:45.92#ibcon#read 3, iclass 39, count 0 2006.260.07:45:45.92#ibcon#about to read 4, iclass 39, count 0 2006.260.07:45:45.92#ibcon#read 4, iclass 39, count 0 2006.260.07:45:45.92#ibcon#about to read 5, iclass 39, count 0 2006.260.07:45:45.92#ibcon#read 5, iclass 39, count 0 2006.260.07:45:45.92#ibcon#about to read 6, iclass 39, count 0 2006.260.07:45:45.92#ibcon#read 6, iclass 39, count 0 2006.260.07:45:45.92#ibcon#end of sib2, iclass 39, count 0 2006.260.07:45:45.92#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:45:45.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:45:45.92#ibcon#[27=USB\r\n] 2006.260.07:45:45.92#ibcon#*before write, iclass 39, count 0 2006.260.07:45:45.92#ibcon#enter sib2, iclass 39, count 0 2006.260.07:45:45.92#ibcon#flushed, iclass 39, count 0 2006.260.07:45:45.92#ibcon#about to write, iclass 39, count 0 2006.260.07:45:45.92#ibcon#wrote, iclass 39, count 0 2006.260.07:45:45.92#ibcon#about to read 3, iclass 39, count 0 2006.260.07:45:45.95#ibcon#read 3, iclass 39, count 0 2006.260.07:45:45.95#ibcon#about to read 4, iclass 39, count 0 2006.260.07:45:45.95#ibcon#read 4, iclass 39, count 0 2006.260.07:45:45.95#ibcon#about to read 5, iclass 39, count 0 2006.260.07:45:45.95#ibcon#read 5, iclass 39, count 0 2006.260.07:45:45.95#ibcon#about to read 6, iclass 39, count 0 2006.260.07:45:45.95#ibcon#read 6, iclass 39, count 0 2006.260.07:45:45.95#ibcon#end of sib2, iclass 39, count 0 2006.260.07:45:45.95#ibcon#*after write, iclass 39, count 0 2006.260.07:45:45.95#ibcon#*before return 0, iclass 39, count 0 2006.260.07:45:45.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:45.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:45:45.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:45:45.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:45:45.95$vc4f8/vblo=4,712.99 2006.260.07:45:45.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:45:45.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:45:45.95#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:45.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:45.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:45.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:45.95#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:45:45.95#ibcon#first serial, iclass 3, count 0 2006.260.07:45:45.95#ibcon#enter sib2, iclass 3, count 0 2006.260.07:45:45.95#ibcon#flushed, iclass 3, count 0 2006.260.07:45:45.95#ibcon#about to write, iclass 3, count 0 2006.260.07:45:45.95#ibcon#wrote, iclass 3, count 0 2006.260.07:45:45.95#ibcon#about to read 3, iclass 3, count 0 2006.260.07:45:45.97#ibcon#read 3, iclass 3, count 0 2006.260.07:45:45.97#ibcon#about to read 4, iclass 3, count 0 2006.260.07:45:45.97#ibcon#read 4, iclass 3, count 0 2006.260.07:45:45.97#ibcon#about to read 5, iclass 3, count 0 2006.260.07:45:45.97#ibcon#read 5, iclass 3, count 0 2006.260.07:45:45.97#ibcon#about to read 6, iclass 3, count 0 2006.260.07:45:45.97#ibcon#read 6, iclass 3, count 0 2006.260.07:45:45.97#ibcon#end of sib2, iclass 3, count 0 2006.260.07:45:45.97#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:45:45.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:45:45.97#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:45:45.97#ibcon#*before write, iclass 3, count 0 2006.260.07:45:45.97#ibcon#enter sib2, iclass 3, count 0 2006.260.07:45:45.97#ibcon#flushed, iclass 3, count 0 2006.260.07:45:45.97#ibcon#about to write, iclass 3, count 0 2006.260.07:45:45.97#ibcon#wrote, iclass 3, count 0 2006.260.07:45:45.97#ibcon#about to read 3, iclass 3, count 0 2006.260.07:45:46.01#ibcon#read 3, iclass 3, count 0 2006.260.07:45:46.01#ibcon#about to read 4, iclass 3, count 0 2006.260.07:45:46.01#ibcon#read 4, iclass 3, count 0 2006.260.07:45:46.01#ibcon#about to read 5, iclass 3, count 0 2006.260.07:45:46.01#ibcon#read 5, iclass 3, count 0 2006.260.07:45:46.01#ibcon#about to read 6, iclass 3, count 0 2006.260.07:45:46.01#ibcon#read 6, iclass 3, count 0 2006.260.07:45:46.01#ibcon#end of sib2, iclass 3, count 0 2006.260.07:45:46.01#ibcon#*after write, iclass 3, count 0 2006.260.07:45:46.01#ibcon#*before return 0, iclass 3, count 0 2006.260.07:45:46.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:46.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:45:46.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:45:46.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:45:46.01$vc4f8/vb=4,5 2006.260.07:45:46.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.07:45:46.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.07:45:46.01#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:46.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:46.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:46.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:46.07#ibcon#enter wrdev, iclass 5, count 2 2006.260.07:45:46.07#ibcon#first serial, iclass 5, count 2 2006.260.07:45:46.07#ibcon#enter sib2, iclass 5, count 2 2006.260.07:45:46.07#ibcon#flushed, iclass 5, count 2 2006.260.07:45:46.07#ibcon#about to write, iclass 5, count 2 2006.260.07:45:46.07#ibcon#wrote, iclass 5, count 2 2006.260.07:45:46.07#ibcon#about to read 3, iclass 5, count 2 2006.260.07:45:46.09#ibcon#read 3, iclass 5, count 2 2006.260.07:45:46.09#ibcon#about to read 4, iclass 5, count 2 2006.260.07:45:46.09#ibcon#read 4, iclass 5, count 2 2006.260.07:45:46.09#ibcon#about to read 5, iclass 5, count 2 2006.260.07:45:46.09#ibcon#read 5, iclass 5, count 2 2006.260.07:45:46.09#ibcon#about to read 6, iclass 5, count 2 2006.260.07:45:46.09#ibcon#read 6, iclass 5, count 2 2006.260.07:45:46.09#ibcon#end of sib2, iclass 5, count 2 2006.260.07:45:46.09#ibcon#*mode == 0, iclass 5, count 2 2006.260.07:45:46.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.07:45:46.09#ibcon#[27=AT04-05\r\n] 2006.260.07:45:46.09#ibcon#*before write, iclass 5, count 2 2006.260.07:45:46.09#ibcon#enter sib2, iclass 5, count 2 2006.260.07:45:46.09#ibcon#flushed, iclass 5, count 2 2006.260.07:45:46.09#ibcon#about to write, iclass 5, count 2 2006.260.07:45:46.09#ibcon#wrote, iclass 5, count 2 2006.260.07:45:46.09#ibcon#about to read 3, iclass 5, count 2 2006.260.07:45:46.12#ibcon#read 3, iclass 5, count 2 2006.260.07:45:46.12#ibcon#about to read 4, iclass 5, count 2 2006.260.07:45:46.12#ibcon#read 4, iclass 5, count 2 2006.260.07:45:46.12#ibcon#about to read 5, iclass 5, count 2 2006.260.07:45:46.12#ibcon#read 5, iclass 5, count 2 2006.260.07:45:46.12#ibcon#about to read 6, iclass 5, count 2 2006.260.07:45:46.12#ibcon#read 6, iclass 5, count 2 2006.260.07:45:46.12#ibcon#end of sib2, iclass 5, count 2 2006.260.07:45:46.12#ibcon#*after write, iclass 5, count 2 2006.260.07:45:46.12#ibcon#*before return 0, iclass 5, count 2 2006.260.07:45:46.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:46.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:45:46.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.07:45:46.12#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:46.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:46.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:46.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:46.24#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:45:46.24#ibcon#first serial, iclass 5, count 0 2006.260.07:45:46.24#ibcon#enter sib2, iclass 5, count 0 2006.260.07:45:46.24#ibcon#flushed, iclass 5, count 0 2006.260.07:45:46.24#ibcon#about to write, iclass 5, count 0 2006.260.07:45:46.24#ibcon#wrote, iclass 5, count 0 2006.260.07:45:46.24#ibcon#about to read 3, iclass 5, count 0 2006.260.07:45:46.26#ibcon#read 3, iclass 5, count 0 2006.260.07:45:46.26#ibcon#about to read 4, iclass 5, count 0 2006.260.07:45:46.26#ibcon#read 4, iclass 5, count 0 2006.260.07:45:46.26#ibcon#about to read 5, iclass 5, count 0 2006.260.07:45:46.26#ibcon#read 5, iclass 5, count 0 2006.260.07:45:46.26#ibcon#about to read 6, iclass 5, count 0 2006.260.07:45:46.26#ibcon#read 6, iclass 5, count 0 2006.260.07:45:46.26#ibcon#end of sib2, iclass 5, count 0 2006.260.07:45:46.26#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:45:46.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:45:46.26#ibcon#[27=USB\r\n] 2006.260.07:45:46.26#ibcon#*before write, iclass 5, count 0 2006.260.07:45:46.26#ibcon#enter sib2, iclass 5, count 0 2006.260.07:45:46.26#ibcon#flushed, iclass 5, count 0 2006.260.07:45:46.26#ibcon#about to write, iclass 5, count 0 2006.260.07:45:46.26#ibcon#wrote, iclass 5, count 0 2006.260.07:45:46.26#ibcon#about to read 3, iclass 5, count 0 2006.260.07:45:46.29#ibcon#read 3, iclass 5, count 0 2006.260.07:45:46.29#ibcon#about to read 4, iclass 5, count 0 2006.260.07:45:46.29#ibcon#read 4, iclass 5, count 0 2006.260.07:45:46.29#ibcon#about to read 5, iclass 5, count 0 2006.260.07:45:46.29#ibcon#read 5, iclass 5, count 0 2006.260.07:45:46.29#ibcon#about to read 6, iclass 5, count 0 2006.260.07:45:46.29#ibcon#read 6, iclass 5, count 0 2006.260.07:45:46.29#ibcon#end of sib2, iclass 5, count 0 2006.260.07:45:46.29#ibcon#*after write, iclass 5, count 0 2006.260.07:45:46.29#ibcon#*before return 0, iclass 5, count 0 2006.260.07:45:46.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:46.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:45:46.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:45:46.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:45:46.29$vc4f8/vblo=5,744.99 2006.260.07:45:46.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:45:46.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:45:46.29#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:46.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:46.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:46.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:46.29#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:45:46.29#ibcon#first serial, iclass 7, count 0 2006.260.07:45:46.29#ibcon#enter sib2, iclass 7, count 0 2006.260.07:45:46.29#ibcon#flushed, iclass 7, count 0 2006.260.07:45:46.29#ibcon#about to write, iclass 7, count 0 2006.260.07:45:46.29#ibcon#wrote, iclass 7, count 0 2006.260.07:45:46.29#ibcon#about to read 3, iclass 7, count 0 2006.260.07:45:46.31#ibcon#read 3, iclass 7, count 0 2006.260.07:45:46.31#ibcon#about to read 4, iclass 7, count 0 2006.260.07:45:46.31#ibcon#read 4, iclass 7, count 0 2006.260.07:45:46.31#ibcon#about to read 5, iclass 7, count 0 2006.260.07:45:46.31#ibcon#read 5, iclass 7, count 0 2006.260.07:45:46.31#ibcon#about to read 6, iclass 7, count 0 2006.260.07:45:46.31#ibcon#read 6, iclass 7, count 0 2006.260.07:45:46.31#ibcon#end of sib2, iclass 7, count 0 2006.260.07:45:46.31#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:45:46.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:45:46.31#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:45:46.31#ibcon#*before write, iclass 7, count 0 2006.260.07:45:46.31#ibcon#enter sib2, iclass 7, count 0 2006.260.07:45:46.31#ibcon#flushed, iclass 7, count 0 2006.260.07:45:46.31#ibcon#about to write, iclass 7, count 0 2006.260.07:45:46.31#ibcon#wrote, iclass 7, count 0 2006.260.07:45:46.31#ibcon#about to read 3, iclass 7, count 0 2006.260.07:45:46.35#ibcon#read 3, iclass 7, count 0 2006.260.07:45:46.35#ibcon#about to read 4, iclass 7, count 0 2006.260.07:45:46.35#ibcon#read 4, iclass 7, count 0 2006.260.07:45:46.35#ibcon#about to read 5, iclass 7, count 0 2006.260.07:45:46.35#ibcon#read 5, iclass 7, count 0 2006.260.07:45:46.35#ibcon#about to read 6, iclass 7, count 0 2006.260.07:45:46.35#ibcon#read 6, iclass 7, count 0 2006.260.07:45:46.35#ibcon#end of sib2, iclass 7, count 0 2006.260.07:45:46.35#ibcon#*after write, iclass 7, count 0 2006.260.07:45:46.35#ibcon#*before return 0, iclass 7, count 0 2006.260.07:45:46.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:46.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:45:46.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:45:46.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:45:46.35$vc4f8/vb=5,4 2006.260.07:45:46.35#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:45:46.35#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:45:46.35#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:46.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:46.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:46.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:46.41#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:45:46.41#ibcon#first serial, iclass 11, count 2 2006.260.07:45:46.41#ibcon#enter sib2, iclass 11, count 2 2006.260.07:45:46.41#ibcon#flushed, iclass 11, count 2 2006.260.07:45:46.41#ibcon#about to write, iclass 11, count 2 2006.260.07:45:46.41#ibcon#wrote, iclass 11, count 2 2006.260.07:45:46.41#ibcon#about to read 3, iclass 11, count 2 2006.260.07:45:46.43#ibcon#read 3, iclass 11, count 2 2006.260.07:45:46.43#ibcon#about to read 4, iclass 11, count 2 2006.260.07:45:46.43#ibcon#read 4, iclass 11, count 2 2006.260.07:45:46.43#ibcon#about to read 5, iclass 11, count 2 2006.260.07:45:46.43#ibcon#read 5, iclass 11, count 2 2006.260.07:45:46.43#ibcon#about to read 6, iclass 11, count 2 2006.260.07:45:46.43#ibcon#read 6, iclass 11, count 2 2006.260.07:45:46.43#ibcon#end of sib2, iclass 11, count 2 2006.260.07:45:46.43#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:45:46.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:45:46.43#ibcon#[27=AT05-04\r\n] 2006.260.07:45:46.43#ibcon#*before write, iclass 11, count 2 2006.260.07:45:46.43#ibcon#enter sib2, iclass 11, count 2 2006.260.07:45:46.43#ibcon#flushed, iclass 11, count 2 2006.260.07:45:46.43#ibcon#about to write, iclass 11, count 2 2006.260.07:45:46.43#ibcon#wrote, iclass 11, count 2 2006.260.07:45:46.43#ibcon#about to read 3, iclass 11, count 2 2006.260.07:45:46.46#ibcon#read 3, iclass 11, count 2 2006.260.07:45:46.46#ibcon#about to read 4, iclass 11, count 2 2006.260.07:45:46.46#ibcon#read 4, iclass 11, count 2 2006.260.07:45:46.46#ibcon#about to read 5, iclass 11, count 2 2006.260.07:45:46.46#ibcon#read 5, iclass 11, count 2 2006.260.07:45:46.46#ibcon#about to read 6, iclass 11, count 2 2006.260.07:45:46.46#ibcon#read 6, iclass 11, count 2 2006.260.07:45:46.46#ibcon#end of sib2, iclass 11, count 2 2006.260.07:45:46.46#ibcon#*after write, iclass 11, count 2 2006.260.07:45:46.46#ibcon#*before return 0, iclass 11, count 2 2006.260.07:45:46.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:46.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:45:46.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:45:46.46#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:46.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:46.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:46.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:46.58#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:45:46.58#ibcon#first serial, iclass 11, count 0 2006.260.07:45:46.58#ibcon#enter sib2, iclass 11, count 0 2006.260.07:45:46.58#ibcon#flushed, iclass 11, count 0 2006.260.07:45:46.58#ibcon#about to write, iclass 11, count 0 2006.260.07:45:46.58#ibcon#wrote, iclass 11, count 0 2006.260.07:45:46.58#ibcon#about to read 3, iclass 11, count 0 2006.260.07:45:46.60#ibcon#read 3, iclass 11, count 0 2006.260.07:45:46.60#ibcon#about to read 4, iclass 11, count 0 2006.260.07:45:46.60#ibcon#read 4, iclass 11, count 0 2006.260.07:45:46.60#ibcon#about to read 5, iclass 11, count 0 2006.260.07:45:46.60#ibcon#read 5, iclass 11, count 0 2006.260.07:45:46.60#ibcon#about to read 6, iclass 11, count 0 2006.260.07:45:46.60#ibcon#read 6, iclass 11, count 0 2006.260.07:45:46.60#ibcon#end of sib2, iclass 11, count 0 2006.260.07:45:46.60#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:45:46.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:45:46.60#ibcon#[27=USB\r\n] 2006.260.07:45:46.60#ibcon#*before write, iclass 11, count 0 2006.260.07:45:46.60#ibcon#enter sib2, iclass 11, count 0 2006.260.07:45:46.60#ibcon#flushed, iclass 11, count 0 2006.260.07:45:46.60#ibcon#about to write, iclass 11, count 0 2006.260.07:45:46.60#ibcon#wrote, iclass 11, count 0 2006.260.07:45:46.60#ibcon#about to read 3, iclass 11, count 0 2006.260.07:45:46.63#ibcon#read 3, iclass 11, count 0 2006.260.07:45:46.63#ibcon#about to read 4, iclass 11, count 0 2006.260.07:45:46.63#ibcon#read 4, iclass 11, count 0 2006.260.07:45:46.63#ibcon#about to read 5, iclass 11, count 0 2006.260.07:45:46.63#ibcon#read 5, iclass 11, count 0 2006.260.07:45:46.63#ibcon#about to read 6, iclass 11, count 0 2006.260.07:45:46.63#ibcon#read 6, iclass 11, count 0 2006.260.07:45:46.63#ibcon#end of sib2, iclass 11, count 0 2006.260.07:45:46.63#ibcon#*after write, iclass 11, count 0 2006.260.07:45:46.63#ibcon#*before return 0, iclass 11, count 0 2006.260.07:45:46.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:46.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:45:46.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:45:46.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:45:46.63$vc4f8/vblo=6,752.99 2006.260.07:45:46.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:45:46.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:45:46.63#ibcon#ireg 17 cls_cnt 0 2006.260.07:45:46.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:46.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:46.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:46.63#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:45:46.63#ibcon#first serial, iclass 13, count 0 2006.260.07:45:46.63#ibcon#enter sib2, iclass 13, count 0 2006.260.07:45:46.63#ibcon#flushed, iclass 13, count 0 2006.260.07:45:46.63#ibcon#about to write, iclass 13, count 0 2006.260.07:45:46.63#ibcon#wrote, iclass 13, count 0 2006.260.07:45:46.63#ibcon#about to read 3, iclass 13, count 0 2006.260.07:45:46.65#ibcon#read 3, iclass 13, count 0 2006.260.07:45:46.65#ibcon#about to read 4, iclass 13, count 0 2006.260.07:45:46.65#ibcon#read 4, iclass 13, count 0 2006.260.07:45:46.65#ibcon#about to read 5, iclass 13, count 0 2006.260.07:45:46.65#ibcon#read 5, iclass 13, count 0 2006.260.07:45:46.65#ibcon#about to read 6, iclass 13, count 0 2006.260.07:45:46.65#ibcon#read 6, iclass 13, count 0 2006.260.07:45:46.65#ibcon#end of sib2, iclass 13, count 0 2006.260.07:45:46.65#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:45:46.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:45:46.65#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:45:46.65#ibcon#*before write, iclass 13, count 0 2006.260.07:45:46.65#ibcon#enter sib2, iclass 13, count 0 2006.260.07:45:46.65#ibcon#flushed, iclass 13, count 0 2006.260.07:45:46.65#ibcon#about to write, iclass 13, count 0 2006.260.07:45:46.65#ibcon#wrote, iclass 13, count 0 2006.260.07:45:46.65#ibcon#about to read 3, iclass 13, count 0 2006.260.07:45:46.69#ibcon#read 3, iclass 13, count 0 2006.260.07:45:46.69#ibcon#about to read 4, iclass 13, count 0 2006.260.07:45:46.69#ibcon#read 4, iclass 13, count 0 2006.260.07:45:46.69#ibcon#about to read 5, iclass 13, count 0 2006.260.07:45:46.69#ibcon#read 5, iclass 13, count 0 2006.260.07:45:46.69#ibcon#about to read 6, iclass 13, count 0 2006.260.07:45:46.69#ibcon#read 6, iclass 13, count 0 2006.260.07:45:46.69#ibcon#end of sib2, iclass 13, count 0 2006.260.07:45:46.69#ibcon#*after write, iclass 13, count 0 2006.260.07:45:46.69#ibcon#*before return 0, iclass 13, count 0 2006.260.07:45:46.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:46.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:45:46.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:45:46.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:45:46.69$vc4f8/vb=6,4 2006.260.07:45:46.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:45:46.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:45:46.69#ibcon#ireg 11 cls_cnt 2 2006.260.07:45:46.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:46.75#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:46.75#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:46.75#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:45:46.75#ibcon#first serial, iclass 15, count 2 2006.260.07:45:46.75#ibcon#enter sib2, iclass 15, count 2 2006.260.07:45:46.75#ibcon#flushed, iclass 15, count 2 2006.260.07:45:46.75#ibcon#about to write, iclass 15, count 2 2006.260.07:45:46.75#ibcon#wrote, iclass 15, count 2 2006.260.07:45:46.75#ibcon#about to read 3, iclass 15, count 2 2006.260.07:45:46.77#ibcon#read 3, iclass 15, count 2 2006.260.07:45:46.77#ibcon#about to read 4, iclass 15, count 2 2006.260.07:45:46.77#ibcon#read 4, iclass 15, count 2 2006.260.07:45:46.77#ibcon#about to read 5, iclass 15, count 2 2006.260.07:45:46.77#ibcon#read 5, iclass 15, count 2 2006.260.07:45:46.77#ibcon#about to read 6, iclass 15, count 2 2006.260.07:45:46.77#ibcon#read 6, iclass 15, count 2 2006.260.07:45:46.77#ibcon#end of sib2, iclass 15, count 2 2006.260.07:45:46.77#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:45:46.77#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:45:46.77#ibcon#[27=AT06-04\r\n] 2006.260.07:45:46.77#ibcon#*before write, iclass 15, count 2 2006.260.07:45:46.77#ibcon#enter sib2, iclass 15, count 2 2006.260.07:45:46.77#ibcon#flushed, iclass 15, count 2 2006.260.07:45:46.77#ibcon#about to write, iclass 15, count 2 2006.260.07:45:46.77#ibcon#wrote, iclass 15, count 2 2006.260.07:45:46.77#ibcon#about to read 3, iclass 15, count 2 2006.260.07:45:46.80#ibcon#read 3, iclass 15, count 2 2006.260.07:45:46.80#ibcon#about to read 4, iclass 15, count 2 2006.260.07:45:46.80#ibcon#read 4, iclass 15, count 2 2006.260.07:45:46.80#ibcon#about to read 5, iclass 15, count 2 2006.260.07:45:46.80#ibcon#read 5, iclass 15, count 2 2006.260.07:45:46.80#ibcon#about to read 6, iclass 15, count 2 2006.260.07:45:46.80#ibcon#read 6, iclass 15, count 2 2006.260.07:45:46.80#ibcon#end of sib2, iclass 15, count 2 2006.260.07:45:46.80#ibcon#*after write, iclass 15, count 2 2006.260.07:45:46.80#ibcon#*before return 0, iclass 15, count 2 2006.260.07:45:46.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:46.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:45:46.80#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:45:46.80#ibcon#ireg 7 cls_cnt 0 2006.260.07:45:46.80#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:46.92#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:46.92#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:46.92#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:45:46.92#ibcon#first serial, iclass 15, count 0 2006.260.07:45:46.92#ibcon#enter sib2, iclass 15, count 0 2006.260.07:45:46.92#ibcon#flushed, iclass 15, count 0 2006.260.07:45:46.92#ibcon#about to write, iclass 15, count 0 2006.260.07:45:46.92#ibcon#wrote, iclass 15, count 0 2006.260.07:45:46.92#ibcon#about to read 3, iclass 15, count 0 2006.260.07:45:46.94#ibcon#read 3, iclass 15, count 0 2006.260.07:45:46.94#ibcon#about to read 4, iclass 15, count 0 2006.260.07:45:46.94#ibcon#read 4, iclass 15, count 0 2006.260.07:45:46.94#ibcon#about to read 5, iclass 15, count 0 2006.260.07:45:46.94#ibcon#read 5, iclass 15, count 0 2006.260.07:45:46.94#ibcon#about to read 6, iclass 15, count 0 2006.260.07:45:46.94#ibcon#read 6, iclass 15, count 0 2006.260.07:45:46.94#ibcon#end of sib2, iclass 15, count 0 2006.260.07:45:46.94#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:45:46.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:45:46.94#ibcon#[27=USB\r\n] 2006.260.07:45:46.94#ibcon#*before write, iclass 15, count 0 2006.260.07:45:46.94#ibcon#enter sib2, iclass 15, count 0 2006.260.07:45:46.94#ibcon#flushed, iclass 15, count 0 2006.260.07:45:46.94#ibcon#about to write, iclass 15, count 0 2006.260.07:45:46.94#ibcon#wrote, iclass 15, count 0 2006.260.07:45:46.94#ibcon#about to read 3, iclass 15, count 0 2006.260.07:45:46.97#ibcon#read 3, iclass 15, count 0 2006.260.07:45:46.97#ibcon#about to read 4, iclass 15, count 0 2006.260.07:45:46.97#ibcon#read 4, iclass 15, count 0 2006.260.07:45:46.97#ibcon#about to read 5, iclass 15, count 0 2006.260.07:45:46.97#ibcon#read 5, iclass 15, count 0 2006.260.07:45:46.97#ibcon#about to read 6, iclass 15, count 0 2006.260.07:45:46.97#ibcon#read 6, iclass 15, count 0 2006.260.07:45:46.97#ibcon#end of sib2, iclass 15, count 0 2006.260.07:45:46.97#ibcon#*after write, iclass 15, count 0 2006.260.07:45:46.97#ibcon#*before return 0, iclass 15, count 0 2006.260.07:45:46.97#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:46.97#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:45:46.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:45:46.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:45:46.97$vc4f8/vabw=wide 2006.260.07:45:46.97#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.07:45:46.97#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.07:45:46.97#ibcon#ireg 8 cls_cnt 0 2006.260.07:45:46.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:45:46.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:45:46.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:45:46.97#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:45:46.97#ibcon#first serial, iclass 17, count 0 2006.260.07:45:46.97#ibcon#enter sib2, iclass 17, count 0 2006.260.07:45:46.97#ibcon#flushed, iclass 17, count 0 2006.260.07:45:46.97#ibcon#about to write, iclass 17, count 0 2006.260.07:45:46.97#ibcon#wrote, iclass 17, count 0 2006.260.07:45:46.97#ibcon#about to read 3, iclass 17, count 0 2006.260.07:45:46.99#ibcon#read 3, iclass 17, count 0 2006.260.07:45:46.99#ibcon#about to read 4, iclass 17, count 0 2006.260.07:45:46.99#ibcon#read 4, iclass 17, count 0 2006.260.07:45:46.99#ibcon#about to read 5, iclass 17, count 0 2006.260.07:45:46.99#ibcon#read 5, iclass 17, count 0 2006.260.07:45:46.99#ibcon#about to read 6, iclass 17, count 0 2006.260.07:45:46.99#ibcon#read 6, iclass 17, count 0 2006.260.07:45:46.99#ibcon#end of sib2, iclass 17, count 0 2006.260.07:45:46.99#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:45:46.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:45:46.99#ibcon#[25=BW32\r\n] 2006.260.07:45:46.99#ibcon#*before write, iclass 17, count 0 2006.260.07:45:46.99#ibcon#enter sib2, iclass 17, count 0 2006.260.07:45:46.99#ibcon#flushed, iclass 17, count 0 2006.260.07:45:46.99#ibcon#about to write, iclass 17, count 0 2006.260.07:45:46.99#ibcon#wrote, iclass 17, count 0 2006.260.07:45:46.99#ibcon#about to read 3, iclass 17, count 0 2006.260.07:45:47.02#ibcon#read 3, iclass 17, count 0 2006.260.07:45:47.02#ibcon#about to read 4, iclass 17, count 0 2006.260.07:45:47.02#ibcon#read 4, iclass 17, count 0 2006.260.07:45:47.02#ibcon#about to read 5, iclass 17, count 0 2006.260.07:45:47.02#ibcon#read 5, iclass 17, count 0 2006.260.07:45:47.02#ibcon#about to read 6, iclass 17, count 0 2006.260.07:45:47.02#ibcon#read 6, iclass 17, count 0 2006.260.07:45:47.02#ibcon#end of sib2, iclass 17, count 0 2006.260.07:45:47.02#ibcon#*after write, iclass 17, count 0 2006.260.07:45:47.02#ibcon#*before return 0, iclass 17, count 0 2006.260.07:45:47.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:45:47.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:45:47.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:45:47.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:45:47.02$vc4f8/vbbw=wide 2006.260.07:45:47.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:45:47.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:45:47.02#ibcon#ireg 8 cls_cnt 0 2006.260.07:45:47.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:45:47.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:45:47.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:45:47.09#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:45:47.09#ibcon#first serial, iclass 19, count 0 2006.260.07:45:47.09#ibcon#enter sib2, iclass 19, count 0 2006.260.07:45:47.09#ibcon#flushed, iclass 19, count 0 2006.260.07:45:47.09#ibcon#about to write, iclass 19, count 0 2006.260.07:45:47.09#ibcon#wrote, iclass 19, count 0 2006.260.07:45:47.09#ibcon#about to read 3, iclass 19, count 0 2006.260.07:45:47.11#ibcon#read 3, iclass 19, count 0 2006.260.07:45:47.11#ibcon#about to read 4, iclass 19, count 0 2006.260.07:45:47.11#ibcon#read 4, iclass 19, count 0 2006.260.07:45:47.11#ibcon#about to read 5, iclass 19, count 0 2006.260.07:45:47.11#ibcon#read 5, iclass 19, count 0 2006.260.07:45:47.11#ibcon#about to read 6, iclass 19, count 0 2006.260.07:45:47.11#ibcon#read 6, iclass 19, count 0 2006.260.07:45:47.11#ibcon#end of sib2, iclass 19, count 0 2006.260.07:45:47.11#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:45:47.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:45:47.11#ibcon#[27=BW32\r\n] 2006.260.07:45:47.11#ibcon#*before write, iclass 19, count 0 2006.260.07:45:47.11#ibcon#enter sib2, iclass 19, count 0 2006.260.07:45:47.11#ibcon#flushed, iclass 19, count 0 2006.260.07:45:47.11#ibcon#about to write, iclass 19, count 0 2006.260.07:45:47.11#ibcon#wrote, iclass 19, count 0 2006.260.07:45:47.11#ibcon#about to read 3, iclass 19, count 0 2006.260.07:45:47.14#ibcon#read 3, iclass 19, count 0 2006.260.07:45:47.14#ibcon#about to read 4, iclass 19, count 0 2006.260.07:45:47.14#ibcon#read 4, iclass 19, count 0 2006.260.07:45:47.14#ibcon#about to read 5, iclass 19, count 0 2006.260.07:45:47.14#ibcon#read 5, iclass 19, count 0 2006.260.07:45:47.14#ibcon#about to read 6, iclass 19, count 0 2006.260.07:45:47.14#ibcon#read 6, iclass 19, count 0 2006.260.07:45:47.14#ibcon#end of sib2, iclass 19, count 0 2006.260.07:45:47.14#ibcon#*after write, iclass 19, count 0 2006.260.07:45:47.14#ibcon#*before return 0, iclass 19, count 0 2006.260.07:45:47.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:45:47.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:45:47.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:45:47.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:45:47.14$4f8m12a/ifd4f 2006.260.07:45:47.14$ifd4f/lo= 2006.260.07:45:47.14$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:45:47.14$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:45:47.14$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:45:47.14$ifd4f/patch= 2006.260.07:45:47.14$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:45:47.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:45:47.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:45:47.14$4f8m12a/"form=m,16.000,1:2 2006.260.07:45:47.14$4f8m12a/"tpicd 2006.260.07:45:47.14$4f8m12a/echo=off 2006.260.07:45:47.14$4f8m12a/xlog=off 2006.260.07:45:47.14:!2006.260.07:46:10 2006.260.07:45:53.14#trakl#Source acquired 2006.260.07:45:55.14#flagr#flagr/antenna,acquired 2006.260.07:46:10.00:preob 2006.260.07:46:11.14/onsource/TRACKING 2006.260.07:46:11.14:!2006.260.07:46:20 2006.260.07:46:20.00:data_valid=on 2006.260.07:46:20.00:midob 2006.260.07:46:20.14/onsource/TRACKING 2006.260.07:46:20.14/wx/23.01,1010.4,87 2006.260.07:46:20.20/cable/+6.4559E-03 2006.260.07:46:21.29/va/01,08,usb,yes,31,32 2006.260.07:46:21.29/va/02,07,usb,yes,31,32 2006.260.07:46:21.29/va/03,08,usb,yes,23,23 2006.260.07:46:21.29/va/04,07,usb,yes,32,34 2006.260.07:46:21.29/va/05,07,usb,yes,35,37 2006.260.07:46:21.29/va/06,06,usb,yes,34,34 2006.260.07:46:21.29/va/07,06,usb,yes,35,35 2006.260.07:46:21.29/va/08,06,usb,yes,37,37 2006.260.07:46:21.52/valo/01,532.99,yes,locked 2006.260.07:46:21.52/valo/02,572.99,yes,locked 2006.260.07:46:21.52/valo/03,672.99,yes,locked 2006.260.07:46:21.52/valo/04,832.99,yes,locked 2006.260.07:46:21.52/valo/05,652.99,yes,locked 2006.260.07:46:21.52/valo/06,772.99,yes,locked 2006.260.07:46:21.52/valo/07,832.99,yes,locked 2006.260.07:46:21.52/valo/08,852.99,yes,locked 2006.260.07:46:22.61/vb/01,04,usb,yes,30,29 2006.260.07:46:22.61/vb/02,05,usb,yes,28,29 2006.260.07:46:22.61/vb/03,04,usb,yes,28,32 2006.260.07:46:22.61/vb/04,05,usb,yes,25,25 2006.260.07:46:22.61/vb/05,04,usb,yes,27,31 2006.260.07:46:22.61/vb/06,04,usb,yes,28,31 2006.260.07:46:22.61/vb/07,04,usb,yes,30,30 2006.260.07:46:22.61/vb/08,04,usb,yes,28,31 2006.260.07:46:22.85/vblo/01,632.99,yes,locked 2006.260.07:46:22.85/vblo/02,640.99,yes,locked 2006.260.07:46:22.85/vblo/03,656.99,yes,locked 2006.260.07:46:22.85/vblo/04,712.99,yes,locked 2006.260.07:46:22.85/vblo/05,744.99,yes,locked 2006.260.07:46:22.85/vblo/06,752.99,yes,locked 2006.260.07:46:22.85/vblo/07,734.99,yes,locked 2006.260.07:46:22.85/vblo/08,744.99,yes,locked 2006.260.07:46:23.00/vabw/8 2006.260.07:46:23.15/vbbw/8 2006.260.07:46:23.24/xfe/off,on,15.0 2006.260.07:46:23.62/ifatt/23,28,28,28 2006.260.07:46:24.07/fmout-gps/S +4.52E-07 2006.260.07:46:24.15:!2006.260.07:47:20 2006.260.07:47:20.00:data_valid=off 2006.260.07:47:20.00:postob 2006.260.07:47:20.17/cable/+6.4571E-03 2006.260.07:47:20.17/wx/23.00,1010.4,87 2006.260.07:47:21.08/fmout-gps/S +4.52E-07 2006.260.07:47:21.08:scan_name=260-0748,k06260,60 2006.260.07:47:21.08:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.260.07:47:21.16#flagr#flagr/antenna,new-source 2006.260.07:47:22.14:checkk5 2006.260.07:47:22.60/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:47:23.03/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:47:23.46/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:47:23.89/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:47:24.32/chk_obsdata//k5ts1/T2600746??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:47:24.86/chk_obsdata//k5ts2/T2600746??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:47:25.27/chk_obsdata//k5ts3/T2600746??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:47:25.66/chk_obsdata//k5ts4/T2600746??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:47:26.45/k5log//k5ts1_log_newline 2006.260.07:47:27.50/k5log//k5ts2_log_newline 2006.260.07:47:28.33/k5log//k5ts3_log_newline 2006.260.07:47:29.09/k5log//k5ts4_log_newline 2006.260.07:47:29.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:47:29.11:4f8m12a=1 2006.260.07:47:29.11$4f8m12a/echo=on 2006.260.07:47:29.12$4f8m12a/pcalon 2006.260.07:47:29.12$pcalon/"no phase cal control is implemented here 2006.260.07:47:29.12$4f8m12a/"tpicd=stop 2006.260.07:47:29.12$4f8m12a/vc4f8 2006.260.07:47:29.12$vc4f8/valo=1,532.99 2006.260.07:47:29.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:47:29.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:47:29.12#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:29.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:29.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:29.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:29.12#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:47:29.12#ibcon#first serial, iclass 26, count 0 2006.260.07:47:29.12#ibcon#enter sib2, iclass 26, count 0 2006.260.07:47:29.12#ibcon#flushed, iclass 26, count 0 2006.260.07:47:29.12#ibcon#about to write, iclass 26, count 0 2006.260.07:47:29.12#ibcon#wrote, iclass 26, count 0 2006.260.07:47:29.12#ibcon#about to read 3, iclass 26, count 0 2006.260.07:47:29.16#ibcon#read 3, iclass 26, count 0 2006.260.07:47:29.16#ibcon#about to read 4, iclass 26, count 0 2006.260.07:47:29.16#ibcon#read 4, iclass 26, count 0 2006.260.07:47:29.16#ibcon#about to read 5, iclass 26, count 0 2006.260.07:47:29.16#ibcon#read 5, iclass 26, count 0 2006.260.07:47:29.16#ibcon#about to read 6, iclass 26, count 0 2006.260.07:47:29.16#ibcon#read 6, iclass 26, count 0 2006.260.07:47:29.16#ibcon#end of sib2, iclass 26, count 0 2006.260.07:47:29.16#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:47:29.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:47:29.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:47:29.16#ibcon#*before write, iclass 26, count 0 2006.260.07:47:29.16#ibcon#enter sib2, iclass 26, count 0 2006.260.07:47:29.16#ibcon#flushed, iclass 26, count 0 2006.260.07:47:29.16#ibcon#about to write, iclass 26, count 0 2006.260.07:47:29.16#ibcon#wrote, iclass 26, count 0 2006.260.07:47:29.16#ibcon#about to read 3, iclass 26, count 0 2006.260.07:47:29.21#ibcon#read 3, iclass 26, count 0 2006.260.07:47:29.21#ibcon#about to read 4, iclass 26, count 0 2006.260.07:47:29.21#ibcon#read 4, iclass 26, count 0 2006.260.07:47:29.21#ibcon#about to read 5, iclass 26, count 0 2006.260.07:47:29.21#ibcon#read 5, iclass 26, count 0 2006.260.07:47:29.21#ibcon#about to read 6, iclass 26, count 0 2006.260.07:47:29.21#ibcon#read 6, iclass 26, count 0 2006.260.07:47:29.21#ibcon#end of sib2, iclass 26, count 0 2006.260.07:47:29.21#ibcon#*after write, iclass 26, count 0 2006.260.07:47:29.21#ibcon#*before return 0, iclass 26, count 0 2006.260.07:47:29.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:29.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:29.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:47:29.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:47:29.21$vc4f8/va=1,8 2006.260.07:47:29.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:47:29.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:47:29.21#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:29.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:29.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:29.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:29.21#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:47:29.21#ibcon#first serial, iclass 28, count 2 2006.260.07:47:29.21#ibcon#enter sib2, iclass 28, count 2 2006.260.07:47:29.21#ibcon#flushed, iclass 28, count 2 2006.260.07:47:29.21#ibcon#about to write, iclass 28, count 2 2006.260.07:47:29.21#ibcon#wrote, iclass 28, count 2 2006.260.07:47:29.21#ibcon#about to read 3, iclass 28, count 2 2006.260.07:47:29.23#ibcon#read 3, iclass 28, count 2 2006.260.07:47:29.23#ibcon#about to read 4, iclass 28, count 2 2006.260.07:47:29.23#ibcon#read 4, iclass 28, count 2 2006.260.07:47:29.23#ibcon#about to read 5, iclass 28, count 2 2006.260.07:47:29.23#ibcon#read 5, iclass 28, count 2 2006.260.07:47:29.23#ibcon#about to read 6, iclass 28, count 2 2006.260.07:47:29.23#ibcon#read 6, iclass 28, count 2 2006.260.07:47:29.23#ibcon#end of sib2, iclass 28, count 2 2006.260.07:47:29.23#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:47:29.23#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:47:29.23#ibcon#[25=AT01-08\r\n] 2006.260.07:47:29.23#ibcon#*before write, iclass 28, count 2 2006.260.07:47:29.23#ibcon#enter sib2, iclass 28, count 2 2006.260.07:47:29.23#ibcon#flushed, iclass 28, count 2 2006.260.07:47:29.23#ibcon#about to write, iclass 28, count 2 2006.260.07:47:29.23#ibcon#wrote, iclass 28, count 2 2006.260.07:47:29.23#ibcon#about to read 3, iclass 28, count 2 2006.260.07:47:29.26#ibcon#read 3, iclass 28, count 2 2006.260.07:47:29.26#ibcon#about to read 4, iclass 28, count 2 2006.260.07:47:29.26#ibcon#read 4, iclass 28, count 2 2006.260.07:47:29.26#ibcon#about to read 5, iclass 28, count 2 2006.260.07:47:29.26#ibcon#read 5, iclass 28, count 2 2006.260.07:47:29.26#ibcon#about to read 6, iclass 28, count 2 2006.260.07:47:29.26#ibcon#read 6, iclass 28, count 2 2006.260.07:47:29.26#ibcon#end of sib2, iclass 28, count 2 2006.260.07:47:29.26#ibcon#*after write, iclass 28, count 2 2006.260.07:47:29.26#ibcon#*before return 0, iclass 28, count 2 2006.260.07:47:29.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:29.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:29.26#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:47:29.26#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:29.26#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:29.38#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:29.38#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:29.38#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:47:29.38#ibcon#first serial, iclass 28, count 0 2006.260.07:47:29.38#ibcon#enter sib2, iclass 28, count 0 2006.260.07:47:29.38#ibcon#flushed, iclass 28, count 0 2006.260.07:47:29.38#ibcon#about to write, iclass 28, count 0 2006.260.07:47:29.38#ibcon#wrote, iclass 28, count 0 2006.260.07:47:29.38#ibcon#about to read 3, iclass 28, count 0 2006.260.07:47:29.40#ibcon#read 3, iclass 28, count 0 2006.260.07:47:29.40#ibcon#about to read 4, iclass 28, count 0 2006.260.07:47:29.40#ibcon#read 4, iclass 28, count 0 2006.260.07:47:29.40#ibcon#about to read 5, iclass 28, count 0 2006.260.07:47:29.40#ibcon#read 5, iclass 28, count 0 2006.260.07:47:29.40#ibcon#about to read 6, iclass 28, count 0 2006.260.07:47:29.40#ibcon#read 6, iclass 28, count 0 2006.260.07:47:29.40#ibcon#end of sib2, iclass 28, count 0 2006.260.07:47:29.40#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:47:29.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:47:29.40#ibcon#[25=USB\r\n] 2006.260.07:47:29.40#ibcon#*before write, iclass 28, count 0 2006.260.07:47:29.40#ibcon#enter sib2, iclass 28, count 0 2006.260.07:47:29.40#ibcon#flushed, iclass 28, count 0 2006.260.07:47:29.40#ibcon#about to write, iclass 28, count 0 2006.260.07:47:29.40#ibcon#wrote, iclass 28, count 0 2006.260.07:47:29.40#ibcon#about to read 3, iclass 28, count 0 2006.260.07:47:29.43#ibcon#read 3, iclass 28, count 0 2006.260.07:47:29.43#ibcon#about to read 4, iclass 28, count 0 2006.260.07:47:29.43#ibcon#read 4, iclass 28, count 0 2006.260.07:47:29.43#ibcon#about to read 5, iclass 28, count 0 2006.260.07:47:29.43#ibcon#read 5, iclass 28, count 0 2006.260.07:47:29.43#ibcon#about to read 6, iclass 28, count 0 2006.260.07:47:29.43#ibcon#read 6, iclass 28, count 0 2006.260.07:47:29.43#ibcon#end of sib2, iclass 28, count 0 2006.260.07:47:29.43#ibcon#*after write, iclass 28, count 0 2006.260.07:47:29.43#ibcon#*before return 0, iclass 28, count 0 2006.260.07:47:29.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:29.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:29.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:47:29.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:47:29.43$vc4f8/valo=2,572.99 2006.260.07:47:29.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:47:29.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:47:29.43#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:29.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:29.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:29.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:29.43#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:47:29.43#ibcon#first serial, iclass 30, count 0 2006.260.07:47:29.43#ibcon#enter sib2, iclass 30, count 0 2006.260.07:47:29.43#ibcon#flushed, iclass 30, count 0 2006.260.07:47:29.43#ibcon#about to write, iclass 30, count 0 2006.260.07:47:29.43#ibcon#wrote, iclass 30, count 0 2006.260.07:47:29.43#ibcon#about to read 3, iclass 30, count 0 2006.260.07:47:29.45#ibcon#read 3, iclass 30, count 0 2006.260.07:47:29.45#ibcon#about to read 4, iclass 30, count 0 2006.260.07:47:29.45#ibcon#read 4, iclass 30, count 0 2006.260.07:47:29.45#ibcon#about to read 5, iclass 30, count 0 2006.260.07:47:29.45#ibcon#read 5, iclass 30, count 0 2006.260.07:47:29.45#ibcon#about to read 6, iclass 30, count 0 2006.260.07:47:29.45#ibcon#read 6, iclass 30, count 0 2006.260.07:47:29.45#ibcon#end of sib2, iclass 30, count 0 2006.260.07:47:29.45#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:47:29.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:47:29.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:47:29.45#ibcon#*before write, iclass 30, count 0 2006.260.07:47:29.45#ibcon#enter sib2, iclass 30, count 0 2006.260.07:47:29.45#ibcon#flushed, iclass 30, count 0 2006.260.07:47:29.45#ibcon#about to write, iclass 30, count 0 2006.260.07:47:29.45#ibcon#wrote, iclass 30, count 0 2006.260.07:47:29.45#ibcon#about to read 3, iclass 30, count 0 2006.260.07:47:29.49#ibcon#read 3, iclass 30, count 0 2006.260.07:47:29.49#ibcon#about to read 4, iclass 30, count 0 2006.260.07:47:29.49#ibcon#read 4, iclass 30, count 0 2006.260.07:47:29.49#ibcon#about to read 5, iclass 30, count 0 2006.260.07:47:29.49#ibcon#read 5, iclass 30, count 0 2006.260.07:47:29.49#ibcon#about to read 6, iclass 30, count 0 2006.260.07:47:29.49#ibcon#read 6, iclass 30, count 0 2006.260.07:47:29.49#ibcon#end of sib2, iclass 30, count 0 2006.260.07:47:29.49#ibcon#*after write, iclass 30, count 0 2006.260.07:47:29.49#ibcon#*before return 0, iclass 30, count 0 2006.260.07:47:29.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:29.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:29.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:47:29.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:47:29.49$vc4f8/va=2,7 2006.260.07:47:29.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:47:29.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:47:29.49#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:29.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:29.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:29.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:29.55#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:47:29.55#ibcon#first serial, iclass 32, count 2 2006.260.07:47:29.55#ibcon#enter sib2, iclass 32, count 2 2006.260.07:47:29.55#ibcon#flushed, iclass 32, count 2 2006.260.07:47:29.55#ibcon#about to write, iclass 32, count 2 2006.260.07:47:29.55#ibcon#wrote, iclass 32, count 2 2006.260.07:47:29.55#ibcon#about to read 3, iclass 32, count 2 2006.260.07:47:29.57#ibcon#read 3, iclass 32, count 2 2006.260.07:47:29.57#ibcon#about to read 4, iclass 32, count 2 2006.260.07:47:29.57#ibcon#read 4, iclass 32, count 2 2006.260.07:47:29.57#ibcon#about to read 5, iclass 32, count 2 2006.260.07:47:29.57#ibcon#read 5, iclass 32, count 2 2006.260.07:47:29.57#ibcon#about to read 6, iclass 32, count 2 2006.260.07:47:29.57#ibcon#read 6, iclass 32, count 2 2006.260.07:47:29.57#ibcon#end of sib2, iclass 32, count 2 2006.260.07:47:29.57#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:47:29.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:47:29.57#ibcon#[25=AT02-07\r\n] 2006.260.07:47:29.57#ibcon#*before write, iclass 32, count 2 2006.260.07:47:29.57#ibcon#enter sib2, iclass 32, count 2 2006.260.07:47:29.57#ibcon#flushed, iclass 32, count 2 2006.260.07:47:29.57#ibcon#about to write, iclass 32, count 2 2006.260.07:47:29.57#ibcon#wrote, iclass 32, count 2 2006.260.07:47:29.57#ibcon#about to read 3, iclass 32, count 2 2006.260.07:47:29.61#ibcon#read 3, iclass 32, count 2 2006.260.07:47:29.61#ibcon#about to read 4, iclass 32, count 2 2006.260.07:47:29.61#ibcon#read 4, iclass 32, count 2 2006.260.07:47:29.61#ibcon#about to read 5, iclass 32, count 2 2006.260.07:47:29.61#ibcon#read 5, iclass 32, count 2 2006.260.07:47:29.61#ibcon#about to read 6, iclass 32, count 2 2006.260.07:47:29.61#ibcon#read 6, iclass 32, count 2 2006.260.07:47:29.61#ibcon#end of sib2, iclass 32, count 2 2006.260.07:47:29.61#ibcon#*after write, iclass 32, count 2 2006.260.07:47:29.61#ibcon#*before return 0, iclass 32, count 2 2006.260.07:47:29.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:29.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:29.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:47:29.61#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:29.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:29.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:29.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:29.73#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:47:29.73#ibcon#first serial, iclass 32, count 0 2006.260.07:47:29.73#ibcon#enter sib2, iclass 32, count 0 2006.260.07:47:29.73#ibcon#flushed, iclass 32, count 0 2006.260.07:47:29.73#ibcon#about to write, iclass 32, count 0 2006.260.07:47:29.73#ibcon#wrote, iclass 32, count 0 2006.260.07:47:29.73#ibcon#about to read 3, iclass 32, count 0 2006.260.07:47:29.75#ibcon#read 3, iclass 32, count 0 2006.260.07:47:29.75#ibcon#about to read 4, iclass 32, count 0 2006.260.07:47:29.75#ibcon#read 4, iclass 32, count 0 2006.260.07:47:29.75#ibcon#about to read 5, iclass 32, count 0 2006.260.07:47:29.75#ibcon#read 5, iclass 32, count 0 2006.260.07:47:29.75#ibcon#about to read 6, iclass 32, count 0 2006.260.07:47:29.75#ibcon#read 6, iclass 32, count 0 2006.260.07:47:29.75#ibcon#end of sib2, iclass 32, count 0 2006.260.07:47:29.75#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:47:29.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:47:29.75#ibcon#[25=USB\r\n] 2006.260.07:47:29.75#ibcon#*before write, iclass 32, count 0 2006.260.07:47:29.75#ibcon#enter sib2, iclass 32, count 0 2006.260.07:47:29.75#ibcon#flushed, iclass 32, count 0 2006.260.07:47:29.75#ibcon#about to write, iclass 32, count 0 2006.260.07:47:29.75#ibcon#wrote, iclass 32, count 0 2006.260.07:47:29.75#ibcon#about to read 3, iclass 32, count 0 2006.260.07:47:29.78#ibcon#read 3, iclass 32, count 0 2006.260.07:47:29.78#ibcon#about to read 4, iclass 32, count 0 2006.260.07:47:29.78#ibcon#read 4, iclass 32, count 0 2006.260.07:47:29.78#ibcon#about to read 5, iclass 32, count 0 2006.260.07:47:29.78#ibcon#read 5, iclass 32, count 0 2006.260.07:47:29.78#ibcon#about to read 6, iclass 32, count 0 2006.260.07:47:29.78#ibcon#read 6, iclass 32, count 0 2006.260.07:47:29.78#ibcon#end of sib2, iclass 32, count 0 2006.260.07:47:29.78#ibcon#*after write, iclass 32, count 0 2006.260.07:47:29.78#ibcon#*before return 0, iclass 32, count 0 2006.260.07:47:29.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:29.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:29.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:47:29.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:47:29.78$vc4f8/valo=3,672.99 2006.260.07:47:29.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:47:29.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:47:29.78#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:29.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:29.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:29.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:29.78#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:47:29.78#ibcon#first serial, iclass 34, count 0 2006.260.07:47:29.78#ibcon#enter sib2, iclass 34, count 0 2006.260.07:47:29.78#ibcon#flushed, iclass 34, count 0 2006.260.07:47:29.78#ibcon#about to write, iclass 34, count 0 2006.260.07:47:29.78#ibcon#wrote, iclass 34, count 0 2006.260.07:47:29.78#ibcon#about to read 3, iclass 34, count 0 2006.260.07:47:29.80#ibcon#read 3, iclass 34, count 0 2006.260.07:47:29.80#ibcon#about to read 4, iclass 34, count 0 2006.260.07:47:29.80#ibcon#read 4, iclass 34, count 0 2006.260.07:47:29.80#ibcon#about to read 5, iclass 34, count 0 2006.260.07:47:29.80#ibcon#read 5, iclass 34, count 0 2006.260.07:47:29.80#ibcon#about to read 6, iclass 34, count 0 2006.260.07:47:29.80#ibcon#read 6, iclass 34, count 0 2006.260.07:47:29.80#ibcon#end of sib2, iclass 34, count 0 2006.260.07:47:29.80#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:47:29.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:47:29.80#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:47:29.80#ibcon#*before write, iclass 34, count 0 2006.260.07:47:29.80#ibcon#enter sib2, iclass 34, count 0 2006.260.07:47:29.80#ibcon#flushed, iclass 34, count 0 2006.260.07:47:29.80#ibcon#about to write, iclass 34, count 0 2006.260.07:47:29.80#ibcon#wrote, iclass 34, count 0 2006.260.07:47:29.80#ibcon#about to read 3, iclass 34, count 0 2006.260.07:47:29.84#ibcon#read 3, iclass 34, count 0 2006.260.07:47:29.84#ibcon#about to read 4, iclass 34, count 0 2006.260.07:47:29.84#ibcon#read 4, iclass 34, count 0 2006.260.07:47:29.84#ibcon#about to read 5, iclass 34, count 0 2006.260.07:47:29.84#ibcon#read 5, iclass 34, count 0 2006.260.07:47:29.84#ibcon#about to read 6, iclass 34, count 0 2006.260.07:47:29.84#ibcon#read 6, iclass 34, count 0 2006.260.07:47:29.84#ibcon#end of sib2, iclass 34, count 0 2006.260.07:47:29.84#ibcon#*after write, iclass 34, count 0 2006.260.07:47:29.84#ibcon#*before return 0, iclass 34, count 0 2006.260.07:47:29.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:29.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:29.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:47:29.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:47:29.84$vc4f8/va=3,8 2006.260.07:47:29.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:47:29.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:47:29.84#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:29.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:29.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:29.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:29.90#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:47:29.90#ibcon#first serial, iclass 36, count 2 2006.260.07:47:29.90#ibcon#enter sib2, iclass 36, count 2 2006.260.07:47:29.90#ibcon#flushed, iclass 36, count 2 2006.260.07:47:29.90#ibcon#about to write, iclass 36, count 2 2006.260.07:47:29.90#ibcon#wrote, iclass 36, count 2 2006.260.07:47:29.90#ibcon#about to read 3, iclass 36, count 2 2006.260.07:47:29.92#ibcon#read 3, iclass 36, count 2 2006.260.07:47:29.92#ibcon#about to read 4, iclass 36, count 2 2006.260.07:47:29.92#ibcon#read 4, iclass 36, count 2 2006.260.07:47:29.92#ibcon#about to read 5, iclass 36, count 2 2006.260.07:47:29.92#ibcon#read 5, iclass 36, count 2 2006.260.07:47:29.92#ibcon#about to read 6, iclass 36, count 2 2006.260.07:47:29.92#ibcon#read 6, iclass 36, count 2 2006.260.07:47:29.92#ibcon#end of sib2, iclass 36, count 2 2006.260.07:47:29.92#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:47:29.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:47:29.92#ibcon#[25=AT03-08\r\n] 2006.260.07:47:29.92#ibcon#*before write, iclass 36, count 2 2006.260.07:47:29.92#ibcon#enter sib2, iclass 36, count 2 2006.260.07:47:29.92#ibcon#flushed, iclass 36, count 2 2006.260.07:47:29.92#ibcon#about to write, iclass 36, count 2 2006.260.07:47:29.92#ibcon#wrote, iclass 36, count 2 2006.260.07:47:29.92#ibcon#about to read 3, iclass 36, count 2 2006.260.07:47:29.96#ibcon#read 3, iclass 36, count 2 2006.260.07:47:29.96#ibcon#about to read 4, iclass 36, count 2 2006.260.07:47:29.96#ibcon#read 4, iclass 36, count 2 2006.260.07:47:29.96#ibcon#about to read 5, iclass 36, count 2 2006.260.07:47:29.96#ibcon#read 5, iclass 36, count 2 2006.260.07:47:29.96#ibcon#about to read 6, iclass 36, count 2 2006.260.07:47:29.96#ibcon#read 6, iclass 36, count 2 2006.260.07:47:29.96#ibcon#end of sib2, iclass 36, count 2 2006.260.07:47:29.96#ibcon#*after write, iclass 36, count 2 2006.260.07:47:29.96#ibcon#*before return 0, iclass 36, count 2 2006.260.07:47:29.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:29.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:29.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:47:29.96#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:29.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:30.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:30.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:30.08#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:47:30.08#ibcon#first serial, iclass 36, count 0 2006.260.07:47:30.08#ibcon#enter sib2, iclass 36, count 0 2006.260.07:47:30.08#ibcon#flushed, iclass 36, count 0 2006.260.07:47:30.08#ibcon#about to write, iclass 36, count 0 2006.260.07:47:30.08#ibcon#wrote, iclass 36, count 0 2006.260.07:47:30.08#ibcon#about to read 3, iclass 36, count 0 2006.260.07:47:30.10#ibcon#read 3, iclass 36, count 0 2006.260.07:47:30.10#ibcon#about to read 4, iclass 36, count 0 2006.260.07:47:30.10#ibcon#read 4, iclass 36, count 0 2006.260.07:47:30.10#ibcon#about to read 5, iclass 36, count 0 2006.260.07:47:30.10#ibcon#read 5, iclass 36, count 0 2006.260.07:47:30.10#ibcon#about to read 6, iclass 36, count 0 2006.260.07:47:30.10#ibcon#read 6, iclass 36, count 0 2006.260.07:47:30.10#ibcon#end of sib2, iclass 36, count 0 2006.260.07:47:30.10#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:47:30.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:47:30.10#ibcon#[25=USB\r\n] 2006.260.07:47:30.10#ibcon#*before write, iclass 36, count 0 2006.260.07:47:30.10#ibcon#enter sib2, iclass 36, count 0 2006.260.07:47:30.10#ibcon#flushed, iclass 36, count 0 2006.260.07:47:30.10#ibcon#about to write, iclass 36, count 0 2006.260.07:47:30.10#ibcon#wrote, iclass 36, count 0 2006.260.07:47:30.10#ibcon#about to read 3, iclass 36, count 0 2006.260.07:47:30.13#ibcon#read 3, iclass 36, count 0 2006.260.07:47:30.13#ibcon#about to read 4, iclass 36, count 0 2006.260.07:47:30.13#ibcon#read 4, iclass 36, count 0 2006.260.07:47:30.13#ibcon#about to read 5, iclass 36, count 0 2006.260.07:47:30.13#ibcon#read 5, iclass 36, count 0 2006.260.07:47:30.13#ibcon#about to read 6, iclass 36, count 0 2006.260.07:47:30.13#ibcon#read 6, iclass 36, count 0 2006.260.07:47:30.13#ibcon#end of sib2, iclass 36, count 0 2006.260.07:47:30.13#ibcon#*after write, iclass 36, count 0 2006.260.07:47:30.13#ibcon#*before return 0, iclass 36, count 0 2006.260.07:47:30.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:30.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:30.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:47:30.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:47:30.13$vc4f8/valo=4,832.99 2006.260.07:47:30.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:47:30.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:47:30.13#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:30.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:30.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:30.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:30.13#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:47:30.13#ibcon#first serial, iclass 38, count 0 2006.260.07:47:30.13#ibcon#enter sib2, iclass 38, count 0 2006.260.07:47:30.13#ibcon#flushed, iclass 38, count 0 2006.260.07:47:30.13#ibcon#about to write, iclass 38, count 0 2006.260.07:47:30.13#ibcon#wrote, iclass 38, count 0 2006.260.07:47:30.13#ibcon#about to read 3, iclass 38, count 0 2006.260.07:47:30.15#ibcon#read 3, iclass 38, count 0 2006.260.07:47:30.15#ibcon#about to read 4, iclass 38, count 0 2006.260.07:47:30.15#ibcon#read 4, iclass 38, count 0 2006.260.07:47:30.15#ibcon#about to read 5, iclass 38, count 0 2006.260.07:47:30.15#ibcon#read 5, iclass 38, count 0 2006.260.07:47:30.15#ibcon#about to read 6, iclass 38, count 0 2006.260.07:47:30.15#ibcon#read 6, iclass 38, count 0 2006.260.07:47:30.15#ibcon#end of sib2, iclass 38, count 0 2006.260.07:47:30.15#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:47:30.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:47:30.15#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:47:30.15#ibcon#*before write, iclass 38, count 0 2006.260.07:47:30.15#ibcon#enter sib2, iclass 38, count 0 2006.260.07:47:30.15#ibcon#flushed, iclass 38, count 0 2006.260.07:47:30.15#ibcon#about to write, iclass 38, count 0 2006.260.07:47:30.15#ibcon#wrote, iclass 38, count 0 2006.260.07:47:30.15#ibcon#about to read 3, iclass 38, count 0 2006.260.07:47:30.19#ibcon#read 3, iclass 38, count 0 2006.260.07:47:30.19#ibcon#about to read 4, iclass 38, count 0 2006.260.07:47:30.19#ibcon#read 4, iclass 38, count 0 2006.260.07:47:30.19#ibcon#about to read 5, iclass 38, count 0 2006.260.07:47:30.19#ibcon#read 5, iclass 38, count 0 2006.260.07:47:30.19#ibcon#about to read 6, iclass 38, count 0 2006.260.07:47:30.19#ibcon#read 6, iclass 38, count 0 2006.260.07:47:30.19#ibcon#end of sib2, iclass 38, count 0 2006.260.07:47:30.19#ibcon#*after write, iclass 38, count 0 2006.260.07:47:30.19#ibcon#*before return 0, iclass 38, count 0 2006.260.07:47:30.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:30.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:30.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:47:30.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:47:30.19$vc4f8/va=4,7 2006.260.07:47:30.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:47:30.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:47:30.19#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:30.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:30.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:30.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:30.25#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:47:30.25#ibcon#first serial, iclass 40, count 2 2006.260.07:47:30.25#ibcon#enter sib2, iclass 40, count 2 2006.260.07:47:30.25#ibcon#flushed, iclass 40, count 2 2006.260.07:47:30.25#ibcon#about to write, iclass 40, count 2 2006.260.07:47:30.25#ibcon#wrote, iclass 40, count 2 2006.260.07:47:30.25#ibcon#about to read 3, iclass 40, count 2 2006.260.07:47:30.27#ibcon#read 3, iclass 40, count 2 2006.260.07:47:30.27#ibcon#about to read 4, iclass 40, count 2 2006.260.07:47:30.27#ibcon#read 4, iclass 40, count 2 2006.260.07:47:30.27#ibcon#about to read 5, iclass 40, count 2 2006.260.07:47:30.27#ibcon#read 5, iclass 40, count 2 2006.260.07:47:30.27#ibcon#about to read 6, iclass 40, count 2 2006.260.07:47:30.27#ibcon#read 6, iclass 40, count 2 2006.260.07:47:30.27#ibcon#end of sib2, iclass 40, count 2 2006.260.07:47:30.27#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:47:30.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:47:30.27#ibcon#[25=AT04-07\r\n] 2006.260.07:47:30.27#ibcon#*before write, iclass 40, count 2 2006.260.07:47:30.27#ibcon#enter sib2, iclass 40, count 2 2006.260.07:47:30.27#ibcon#flushed, iclass 40, count 2 2006.260.07:47:30.27#ibcon#about to write, iclass 40, count 2 2006.260.07:47:30.27#ibcon#wrote, iclass 40, count 2 2006.260.07:47:30.27#ibcon#about to read 3, iclass 40, count 2 2006.260.07:47:30.30#ibcon#read 3, iclass 40, count 2 2006.260.07:47:30.30#ibcon#about to read 4, iclass 40, count 2 2006.260.07:47:30.30#ibcon#read 4, iclass 40, count 2 2006.260.07:47:30.30#ibcon#about to read 5, iclass 40, count 2 2006.260.07:47:30.30#ibcon#read 5, iclass 40, count 2 2006.260.07:47:30.30#ibcon#about to read 6, iclass 40, count 2 2006.260.07:47:30.30#ibcon#read 6, iclass 40, count 2 2006.260.07:47:30.30#ibcon#end of sib2, iclass 40, count 2 2006.260.07:47:30.30#ibcon#*after write, iclass 40, count 2 2006.260.07:47:30.30#ibcon#*before return 0, iclass 40, count 2 2006.260.07:47:30.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:30.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:30.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:47:30.30#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:30.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:30.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:30.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:30.42#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:47:30.42#ibcon#first serial, iclass 40, count 0 2006.260.07:47:30.42#ibcon#enter sib2, iclass 40, count 0 2006.260.07:47:30.42#ibcon#flushed, iclass 40, count 0 2006.260.07:47:30.42#ibcon#about to write, iclass 40, count 0 2006.260.07:47:30.42#ibcon#wrote, iclass 40, count 0 2006.260.07:47:30.42#ibcon#about to read 3, iclass 40, count 0 2006.260.07:47:30.44#ibcon#read 3, iclass 40, count 0 2006.260.07:47:30.44#ibcon#about to read 4, iclass 40, count 0 2006.260.07:47:30.44#ibcon#read 4, iclass 40, count 0 2006.260.07:47:30.44#ibcon#about to read 5, iclass 40, count 0 2006.260.07:47:30.44#ibcon#read 5, iclass 40, count 0 2006.260.07:47:30.44#ibcon#about to read 6, iclass 40, count 0 2006.260.07:47:30.44#ibcon#read 6, iclass 40, count 0 2006.260.07:47:30.44#ibcon#end of sib2, iclass 40, count 0 2006.260.07:47:30.44#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:47:30.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:47:30.44#ibcon#[25=USB\r\n] 2006.260.07:47:30.44#ibcon#*before write, iclass 40, count 0 2006.260.07:47:30.44#ibcon#enter sib2, iclass 40, count 0 2006.260.07:47:30.44#ibcon#flushed, iclass 40, count 0 2006.260.07:47:30.44#ibcon#about to write, iclass 40, count 0 2006.260.07:47:30.44#ibcon#wrote, iclass 40, count 0 2006.260.07:47:30.44#ibcon#about to read 3, iclass 40, count 0 2006.260.07:47:30.47#ibcon#read 3, iclass 40, count 0 2006.260.07:47:30.47#ibcon#about to read 4, iclass 40, count 0 2006.260.07:47:30.47#ibcon#read 4, iclass 40, count 0 2006.260.07:47:30.47#ibcon#about to read 5, iclass 40, count 0 2006.260.07:47:30.47#ibcon#read 5, iclass 40, count 0 2006.260.07:47:30.47#ibcon#about to read 6, iclass 40, count 0 2006.260.07:47:30.47#ibcon#read 6, iclass 40, count 0 2006.260.07:47:30.47#ibcon#end of sib2, iclass 40, count 0 2006.260.07:47:30.47#ibcon#*after write, iclass 40, count 0 2006.260.07:47:30.47#ibcon#*before return 0, iclass 40, count 0 2006.260.07:47:30.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:30.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:30.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:47:30.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:47:30.47$vc4f8/valo=5,652.99 2006.260.07:47:30.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:47:30.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:47:30.47#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:30.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:30.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:30.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:30.47#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:47:30.47#ibcon#first serial, iclass 4, count 0 2006.260.07:47:30.47#ibcon#enter sib2, iclass 4, count 0 2006.260.07:47:30.47#ibcon#flushed, iclass 4, count 0 2006.260.07:47:30.47#ibcon#about to write, iclass 4, count 0 2006.260.07:47:30.47#ibcon#wrote, iclass 4, count 0 2006.260.07:47:30.47#ibcon#about to read 3, iclass 4, count 0 2006.260.07:47:30.49#ibcon#read 3, iclass 4, count 0 2006.260.07:47:30.49#ibcon#about to read 4, iclass 4, count 0 2006.260.07:47:30.49#ibcon#read 4, iclass 4, count 0 2006.260.07:47:30.49#ibcon#about to read 5, iclass 4, count 0 2006.260.07:47:30.49#ibcon#read 5, iclass 4, count 0 2006.260.07:47:30.49#ibcon#about to read 6, iclass 4, count 0 2006.260.07:47:30.49#ibcon#read 6, iclass 4, count 0 2006.260.07:47:30.49#ibcon#end of sib2, iclass 4, count 0 2006.260.07:47:30.49#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:47:30.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:47:30.49#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:47:30.49#ibcon#*before write, iclass 4, count 0 2006.260.07:47:30.49#ibcon#enter sib2, iclass 4, count 0 2006.260.07:47:30.49#ibcon#flushed, iclass 4, count 0 2006.260.07:47:30.49#ibcon#about to write, iclass 4, count 0 2006.260.07:47:30.49#ibcon#wrote, iclass 4, count 0 2006.260.07:47:30.49#ibcon#about to read 3, iclass 4, count 0 2006.260.07:47:30.53#ibcon#read 3, iclass 4, count 0 2006.260.07:47:30.53#ibcon#about to read 4, iclass 4, count 0 2006.260.07:47:30.53#ibcon#read 4, iclass 4, count 0 2006.260.07:47:30.53#ibcon#about to read 5, iclass 4, count 0 2006.260.07:47:30.53#ibcon#read 5, iclass 4, count 0 2006.260.07:47:30.53#ibcon#about to read 6, iclass 4, count 0 2006.260.07:47:30.53#ibcon#read 6, iclass 4, count 0 2006.260.07:47:30.53#ibcon#end of sib2, iclass 4, count 0 2006.260.07:47:30.53#ibcon#*after write, iclass 4, count 0 2006.260.07:47:30.53#ibcon#*before return 0, iclass 4, count 0 2006.260.07:47:30.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:30.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:30.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:47:30.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:47:30.53$vc4f8/va=5,7 2006.260.07:47:30.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:47:30.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:47:30.53#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:30.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:30.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:30.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:30.59#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:47:30.59#ibcon#first serial, iclass 6, count 2 2006.260.07:47:30.59#ibcon#enter sib2, iclass 6, count 2 2006.260.07:47:30.59#ibcon#flushed, iclass 6, count 2 2006.260.07:47:30.59#ibcon#about to write, iclass 6, count 2 2006.260.07:47:30.59#ibcon#wrote, iclass 6, count 2 2006.260.07:47:30.59#ibcon#about to read 3, iclass 6, count 2 2006.260.07:47:30.61#ibcon#read 3, iclass 6, count 2 2006.260.07:47:30.61#ibcon#about to read 4, iclass 6, count 2 2006.260.07:47:30.61#ibcon#read 4, iclass 6, count 2 2006.260.07:47:30.61#ibcon#about to read 5, iclass 6, count 2 2006.260.07:47:30.61#ibcon#read 5, iclass 6, count 2 2006.260.07:47:30.61#ibcon#about to read 6, iclass 6, count 2 2006.260.07:47:30.61#ibcon#read 6, iclass 6, count 2 2006.260.07:47:30.61#ibcon#end of sib2, iclass 6, count 2 2006.260.07:47:30.61#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:47:30.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:47:30.61#ibcon#[25=AT05-07\r\n] 2006.260.07:47:30.61#ibcon#*before write, iclass 6, count 2 2006.260.07:47:30.61#ibcon#enter sib2, iclass 6, count 2 2006.260.07:47:30.61#ibcon#flushed, iclass 6, count 2 2006.260.07:47:30.61#ibcon#about to write, iclass 6, count 2 2006.260.07:47:30.61#ibcon#wrote, iclass 6, count 2 2006.260.07:47:30.61#ibcon#about to read 3, iclass 6, count 2 2006.260.07:47:30.64#ibcon#read 3, iclass 6, count 2 2006.260.07:47:30.64#ibcon#about to read 4, iclass 6, count 2 2006.260.07:47:30.64#ibcon#read 4, iclass 6, count 2 2006.260.07:47:30.64#ibcon#about to read 5, iclass 6, count 2 2006.260.07:47:30.64#ibcon#read 5, iclass 6, count 2 2006.260.07:47:30.64#ibcon#about to read 6, iclass 6, count 2 2006.260.07:47:30.64#ibcon#read 6, iclass 6, count 2 2006.260.07:47:30.64#ibcon#end of sib2, iclass 6, count 2 2006.260.07:47:30.64#ibcon#*after write, iclass 6, count 2 2006.260.07:47:30.64#ibcon#*before return 0, iclass 6, count 2 2006.260.07:47:30.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:30.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:30.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:47:30.64#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:30.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:30.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:30.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:30.76#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:47:30.76#ibcon#first serial, iclass 6, count 0 2006.260.07:47:30.76#ibcon#enter sib2, iclass 6, count 0 2006.260.07:47:30.76#ibcon#flushed, iclass 6, count 0 2006.260.07:47:30.76#ibcon#about to write, iclass 6, count 0 2006.260.07:47:30.76#ibcon#wrote, iclass 6, count 0 2006.260.07:47:30.76#ibcon#about to read 3, iclass 6, count 0 2006.260.07:47:30.78#ibcon#read 3, iclass 6, count 0 2006.260.07:47:30.78#ibcon#about to read 4, iclass 6, count 0 2006.260.07:47:30.78#ibcon#read 4, iclass 6, count 0 2006.260.07:47:30.78#ibcon#about to read 5, iclass 6, count 0 2006.260.07:47:30.78#ibcon#read 5, iclass 6, count 0 2006.260.07:47:30.78#ibcon#about to read 6, iclass 6, count 0 2006.260.07:47:30.78#ibcon#read 6, iclass 6, count 0 2006.260.07:47:30.78#ibcon#end of sib2, iclass 6, count 0 2006.260.07:47:30.78#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:47:30.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:47:30.78#ibcon#[25=USB\r\n] 2006.260.07:47:30.78#ibcon#*before write, iclass 6, count 0 2006.260.07:47:30.78#ibcon#enter sib2, iclass 6, count 0 2006.260.07:47:30.78#ibcon#flushed, iclass 6, count 0 2006.260.07:47:30.78#ibcon#about to write, iclass 6, count 0 2006.260.07:47:30.78#ibcon#wrote, iclass 6, count 0 2006.260.07:47:30.78#ibcon#about to read 3, iclass 6, count 0 2006.260.07:47:30.81#ibcon#read 3, iclass 6, count 0 2006.260.07:47:30.81#ibcon#about to read 4, iclass 6, count 0 2006.260.07:47:30.81#ibcon#read 4, iclass 6, count 0 2006.260.07:47:30.81#ibcon#about to read 5, iclass 6, count 0 2006.260.07:47:30.81#ibcon#read 5, iclass 6, count 0 2006.260.07:47:30.81#ibcon#about to read 6, iclass 6, count 0 2006.260.07:47:30.81#ibcon#read 6, iclass 6, count 0 2006.260.07:47:30.81#ibcon#end of sib2, iclass 6, count 0 2006.260.07:47:30.81#ibcon#*after write, iclass 6, count 0 2006.260.07:47:30.81#ibcon#*before return 0, iclass 6, count 0 2006.260.07:47:30.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:30.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:30.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:47:30.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:47:30.81$vc4f8/valo=6,772.99 2006.260.07:47:30.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:47:30.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:47:30.81#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:30.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:30.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:30.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:30.81#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:47:30.81#ibcon#first serial, iclass 10, count 0 2006.260.07:47:30.81#ibcon#enter sib2, iclass 10, count 0 2006.260.07:47:30.81#ibcon#flushed, iclass 10, count 0 2006.260.07:47:30.81#ibcon#about to write, iclass 10, count 0 2006.260.07:47:30.81#ibcon#wrote, iclass 10, count 0 2006.260.07:47:30.81#ibcon#about to read 3, iclass 10, count 0 2006.260.07:47:30.83#ibcon#read 3, iclass 10, count 0 2006.260.07:47:30.83#ibcon#about to read 4, iclass 10, count 0 2006.260.07:47:30.83#ibcon#read 4, iclass 10, count 0 2006.260.07:47:30.83#ibcon#about to read 5, iclass 10, count 0 2006.260.07:47:30.83#ibcon#read 5, iclass 10, count 0 2006.260.07:47:30.83#ibcon#about to read 6, iclass 10, count 0 2006.260.07:47:30.83#ibcon#read 6, iclass 10, count 0 2006.260.07:47:30.83#ibcon#end of sib2, iclass 10, count 0 2006.260.07:47:30.83#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:47:30.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:47:30.83#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:47:30.83#ibcon#*before write, iclass 10, count 0 2006.260.07:47:30.83#ibcon#enter sib2, iclass 10, count 0 2006.260.07:47:30.83#ibcon#flushed, iclass 10, count 0 2006.260.07:47:30.83#ibcon#about to write, iclass 10, count 0 2006.260.07:47:30.83#ibcon#wrote, iclass 10, count 0 2006.260.07:47:30.83#ibcon#about to read 3, iclass 10, count 0 2006.260.07:47:30.87#ibcon#read 3, iclass 10, count 0 2006.260.07:47:30.87#ibcon#about to read 4, iclass 10, count 0 2006.260.07:47:30.87#ibcon#read 4, iclass 10, count 0 2006.260.07:47:30.87#ibcon#about to read 5, iclass 10, count 0 2006.260.07:47:30.87#ibcon#read 5, iclass 10, count 0 2006.260.07:47:30.87#ibcon#about to read 6, iclass 10, count 0 2006.260.07:47:30.87#ibcon#read 6, iclass 10, count 0 2006.260.07:47:30.87#ibcon#end of sib2, iclass 10, count 0 2006.260.07:47:30.87#ibcon#*after write, iclass 10, count 0 2006.260.07:47:30.87#ibcon#*before return 0, iclass 10, count 0 2006.260.07:47:30.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:30.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:30.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:47:30.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:47:30.87$vc4f8/va=6,6 2006.260.07:47:30.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:47:30.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:47:30.87#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:30.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:30.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:30.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:30.93#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:47:30.93#ibcon#first serial, iclass 12, count 2 2006.260.07:47:30.93#ibcon#enter sib2, iclass 12, count 2 2006.260.07:47:30.93#ibcon#flushed, iclass 12, count 2 2006.260.07:47:30.93#ibcon#about to write, iclass 12, count 2 2006.260.07:47:30.93#ibcon#wrote, iclass 12, count 2 2006.260.07:47:30.93#ibcon#about to read 3, iclass 12, count 2 2006.260.07:47:30.95#ibcon#read 3, iclass 12, count 2 2006.260.07:47:30.95#ibcon#about to read 4, iclass 12, count 2 2006.260.07:47:30.95#ibcon#read 4, iclass 12, count 2 2006.260.07:47:30.95#ibcon#about to read 5, iclass 12, count 2 2006.260.07:47:30.95#ibcon#read 5, iclass 12, count 2 2006.260.07:47:30.95#ibcon#about to read 6, iclass 12, count 2 2006.260.07:47:30.95#ibcon#read 6, iclass 12, count 2 2006.260.07:47:30.95#ibcon#end of sib2, iclass 12, count 2 2006.260.07:47:30.95#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:47:30.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:47:30.95#ibcon#[25=AT06-06\r\n] 2006.260.07:47:30.95#ibcon#*before write, iclass 12, count 2 2006.260.07:47:30.95#ibcon#enter sib2, iclass 12, count 2 2006.260.07:47:30.95#ibcon#flushed, iclass 12, count 2 2006.260.07:47:30.95#ibcon#about to write, iclass 12, count 2 2006.260.07:47:30.95#ibcon#wrote, iclass 12, count 2 2006.260.07:47:30.95#ibcon#about to read 3, iclass 12, count 2 2006.260.07:47:30.98#ibcon#read 3, iclass 12, count 2 2006.260.07:47:30.98#ibcon#about to read 4, iclass 12, count 2 2006.260.07:47:30.98#ibcon#read 4, iclass 12, count 2 2006.260.07:47:30.98#ibcon#about to read 5, iclass 12, count 2 2006.260.07:47:30.98#ibcon#read 5, iclass 12, count 2 2006.260.07:47:30.98#ibcon#about to read 6, iclass 12, count 2 2006.260.07:47:30.98#ibcon#read 6, iclass 12, count 2 2006.260.07:47:30.98#ibcon#end of sib2, iclass 12, count 2 2006.260.07:47:30.98#ibcon#*after write, iclass 12, count 2 2006.260.07:47:30.98#ibcon#*before return 0, iclass 12, count 2 2006.260.07:47:30.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:30.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:30.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:47:30.98#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:30.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:47:31.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:47:31.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:47:31.10#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:47:31.10#ibcon#first serial, iclass 12, count 0 2006.260.07:47:31.10#ibcon#enter sib2, iclass 12, count 0 2006.260.07:47:31.10#ibcon#flushed, iclass 12, count 0 2006.260.07:47:31.10#ibcon#about to write, iclass 12, count 0 2006.260.07:47:31.10#ibcon#wrote, iclass 12, count 0 2006.260.07:47:31.10#ibcon#about to read 3, iclass 12, count 0 2006.260.07:47:31.12#ibcon#read 3, iclass 12, count 0 2006.260.07:47:31.12#ibcon#about to read 4, iclass 12, count 0 2006.260.07:47:31.12#ibcon#read 4, iclass 12, count 0 2006.260.07:47:31.12#ibcon#about to read 5, iclass 12, count 0 2006.260.07:47:31.12#ibcon#read 5, iclass 12, count 0 2006.260.07:47:31.12#ibcon#about to read 6, iclass 12, count 0 2006.260.07:47:31.12#ibcon#read 6, iclass 12, count 0 2006.260.07:47:31.12#ibcon#end of sib2, iclass 12, count 0 2006.260.07:47:31.12#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:47:31.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:47:31.12#ibcon#[25=USB\r\n] 2006.260.07:47:31.12#ibcon#*before write, iclass 12, count 0 2006.260.07:47:31.12#ibcon#enter sib2, iclass 12, count 0 2006.260.07:47:31.12#ibcon#flushed, iclass 12, count 0 2006.260.07:47:31.12#ibcon#about to write, iclass 12, count 0 2006.260.07:47:31.12#ibcon#wrote, iclass 12, count 0 2006.260.07:47:31.12#ibcon#about to read 3, iclass 12, count 0 2006.260.07:47:31.15#ibcon#read 3, iclass 12, count 0 2006.260.07:47:31.15#ibcon#about to read 4, iclass 12, count 0 2006.260.07:47:31.15#ibcon#read 4, iclass 12, count 0 2006.260.07:47:31.15#ibcon#about to read 5, iclass 12, count 0 2006.260.07:47:31.15#ibcon#read 5, iclass 12, count 0 2006.260.07:47:31.15#ibcon#about to read 6, iclass 12, count 0 2006.260.07:47:31.15#ibcon#read 6, iclass 12, count 0 2006.260.07:47:31.15#ibcon#end of sib2, iclass 12, count 0 2006.260.07:47:31.15#ibcon#*after write, iclass 12, count 0 2006.260.07:47:31.15#ibcon#*before return 0, iclass 12, count 0 2006.260.07:47:31.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:47:31.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:47:31.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:47:31.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:47:31.15$vc4f8/valo=7,832.99 2006.260.07:47:31.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:47:31.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:47:31.15#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:31.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:47:31.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:47:31.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:47:31.15#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:47:31.15#ibcon#first serial, iclass 14, count 0 2006.260.07:47:31.15#ibcon#enter sib2, iclass 14, count 0 2006.260.07:47:31.15#ibcon#flushed, iclass 14, count 0 2006.260.07:47:31.15#ibcon#about to write, iclass 14, count 0 2006.260.07:47:31.15#ibcon#wrote, iclass 14, count 0 2006.260.07:47:31.15#ibcon#about to read 3, iclass 14, count 0 2006.260.07:47:31.17#ibcon#read 3, iclass 14, count 0 2006.260.07:47:31.17#ibcon#about to read 4, iclass 14, count 0 2006.260.07:47:31.17#ibcon#read 4, iclass 14, count 0 2006.260.07:47:31.17#ibcon#about to read 5, iclass 14, count 0 2006.260.07:47:31.17#ibcon#read 5, iclass 14, count 0 2006.260.07:47:31.17#ibcon#about to read 6, iclass 14, count 0 2006.260.07:47:31.17#ibcon#read 6, iclass 14, count 0 2006.260.07:47:31.17#ibcon#end of sib2, iclass 14, count 0 2006.260.07:47:31.17#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:47:31.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:47:31.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:47:31.17#ibcon#*before write, iclass 14, count 0 2006.260.07:47:31.17#ibcon#enter sib2, iclass 14, count 0 2006.260.07:47:31.17#ibcon#flushed, iclass 14, count 0 2006.260.07:47:31.17#ibcon#about to write, iclass 14, count 0 2006.260.07:47:31.17#ibcon#wrote, iclass 14, count 0 2006.260.07:47:31.17#ibcon#about to read 3, iclass 14, count 0 2006.260.07:47:31.21#ibcon#read 3, iclass 14, count 0 2006.260.07:47:31.21#ibcon#about to read 4, iclass 14, count 0 2006.260.07:47:31.21#ibcon#read 4, iclass 14, count 0 2006.260.07:47:31.21#ibcon#about to read 5, iclass 14, count 0 2006.260.07:47:31.21#ibcon#read 5, iclass 14, count 0 2006.260.07:47:31.21#ibcon#about to read 6, iclass 14, count 0 2006.260.07:47:31.21#ibcon#read 6, iclass 14, count 0 2006.260.07:47:31.21#ibcon#end of sib2, iclass 14, count 0 2006.260.07:47:31.21#ibcon#*after write, iclass 14, count 0 2006.260.07:47:31.21#ibcon#*before return 0, iclass 14, count 0 2006.260.07:47:31.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:47:31.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:47:31.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:47:31.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:47:31.21$vc4f8/va=7,6 2006.260.07:47:31.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:47:31.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:47:31.21#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:31.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:47:31.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:47:31.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:47:31.27#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:47:31.27#ibcon#first serial, iclass 16, count 2 2006.260.07:47:31.27#ibcon#enter sib2, iclass 16, count 2 2006.260.07:47:31.27#ibcon#flushed, iclass 16, count 2 2006.260.07:47:31.27#ibcon#about to write, iclass 16, count 2 2006.260.07:47:31.27#ibcon#wrote, iclass 16, count 2 2006.260.07:47:31.27#ibcon#about to read 3, iclass 16, count 2 2006.260.07:47:31.29#ibcon#read 3, iclass 16, count 2 2006.260.07:47:31.29#ibcon#about to read 4, iclass 16, count 2 2006.260.07:47:31.29#ibcon#read 4, iclass 16, count 2 2006.260.07:47:31.29#ibcon#about to read 5, iclass 16, count 2 2006.260.07:47:31.29#ibcon#read 5, iclass 16, count 2 2006.260.07:47:31.29#ibcon#about to read 6, iclass 16, count 2 2006.260.07:47:31.29#ibcon#read 6, iclass 16, count 2 2006.260.07:47:31.29#ibcon#end of sib2, iclass 16, count 2 2006.260.07:47:31.29#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:47:31.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:47:31.29#ibcon#[25=AT07-06\r\n] 2006.260.07:47:31.29#ibcon#*before write, iclass 16, count 2 2006.260.07:47:31.29#ibcon#enter sib2, iclass 16, count 2 2006.260.07:47:31.29#ibcon#flushed, iclass 16, count 2 2006.260.07:47:31.29#ibcon#about to write, iclass 16, count 2 2006.260.07:47:31.29#ibcon#wrote, iclass 16, count 2 2006.260.07:47:31.29#ibcon#about to read 3, iclass 16, count 2 2006.260.07:47:31.32#ibcon#read 3, iclass 16, count 2 2006.260.07:47:31.32#ibcon#about to read 4, iclass 16, count 2 2006.260.07:47:31.32#ibcon#read 4, iclass 16, count 2 2006.260.07:47:31.32#ibcon#about to read 5, iclass 16, count 2 2006.260.07:47:31.32#ibcon#read 5, iclass 16, count 2 2006.260.07:47:31.32#ibcon#about to read 6, iclass 16, count 2 2006.260.07:47:31.32#ibcon#read 6, iclass 16, count 2 2006.260.07:47:31.32#ibcon#end of sib2, iclass 16, count 2 2006.260.07:47:31.32#ibcon#*after write, iclass 16, count 2 2006.260.07:47:31.32#ibcon#*before return 0, iclass 16, count 2 2006.260.07:47:31.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:47:31.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:47:31.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:47:31.32#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:31.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:47:31.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:47:31.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:47:31.44#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:47:31.44#ibcon#first serial, iclass 16, count 0 2006.260.07:47:31.44#ibcon#enter sib2, iclass 16, count 0 2006.260.07:47:31.44#ibcon#flushed, iclass 16, count 0 2006.260.07:47:31.44#ibcon#about to write, iclass 16, count 0 2006.260.07:47:31.44#ibcon#wrote, iclass 16, count 0 2006.260.07:47:31.44#ibcon#about to read 3, iclass 16, count 0 2006.260.07:47:31.46#ibcon#read 3, iclass 16, count 0 2006.260.07:47:31.46#ibcon#about to read 4, iclass 16, count 0 2006.260.07:47:31.46#ibcon#read 4, iclass 16, count 0 2006.260.07:47:31.46#ibcon#about to read 5, iclass 16, count 0 2006.260.07:47:31.46#ibcon#read 5, iclass 16, count 0 2006.260.07:47:31.46#ibcon#about to read 6, iclass 16, count 0 2006.260.07:47:31.46#ibcon#read 6, iclass 16, count 0 2006.260.07:47:31.46#ibcon#end of sib2, iclass 16, count 0 2006.260.07:47:31.46#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:47:31.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:47:31.46#ibcon#[25=USB\r\n] 2006.260.07:47:31.46#ibcon#*before write, iclass 16, count 0 2006.260.07:47:31.46#ibcon#enter sib2, iclass 16, count 0 2006.260.07:47:31.46#ibcon#flushed, iclass 16, count 0 2006.260.07:47:31.46#ibcon#about to write, iclass 16, count 0 2006.260.07:47:31.46#ibcon#wrote, iclass 16, count 0 2006.260.07:47:31.46#ibcon#about to read 3, iclass 16, count 0 2006.260.07:47:31.49#ibcon#read 3, iclass 16, count 0 2006.260.07:47:31.49#ibcon#about to read 4, iclass 16, count 0 2006.260.07:47:31.49#ibcon#read 4, iclass 16, count 0 2006.260.07:47:31.49#ibcon#about to read 5, iclass 16, count 0 2006.260.07:47:31.49#ibcon#read 5, iclass 16, count 0 2006.260.07:47:31.49#ibcon#about to read 6, iclass 16, count 0 2006.260.07:47:31.49#ibcon#read 6, iclass 16, count 0 2006.260.07:47:31.49#ibcon#end of sib2, iclass 16, count 0 2006.260.07:47:31.49#ibcon#*after write, iclass 16, count 0 2006.260.07:47:31.49#ibcon#*before return 0, iclass 16, count 0 2006.260.07:47:31.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:47:31.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:47:31.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:47:31.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:47:31.49$vc4f8/valo=8,852.99 2006.260.07:47:31.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:47:31.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:47:31.49#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:31.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:47:31.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:47:31.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:47:31.49#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:47:31.49#ibcon#first serial, iclass 18, count 0 2006.260.07:47:31.49#ibcon#enter sib2, iclass 18, count 0 2006.260.07:47:31.49#ibcon#flushed, iclass 18, count 0 2006.260.07:47:31.49#ibcon#about to write, iclass 18, count 0 2006.260.07:47:31.49#ibcon#wrote, iclass 18, count 0 2006.260.07:47:31.49#ibcon#about to read 3, iclass 18, count 0 2006.260.07:47:31.51#ibcon#read 3, iclass 18, count 0 2006.260.07:47:31.51#ibcon#about to read 4, iclass 18, count 0 2006.260.07:47:31.51#ibcon#read 4, iclass 18, count 0 2006.260.07:47:31.51#ibcon#about to read 5, iclass 18, count 0 2006.260.07:47:31.51#ibcon#read 5, iclass 18, count 0 2006.260.07:47:31.51#ibcon#about to read 6, iclass 18, count 0 2006.260.07:47:31.51#ibcon#read 6, iclass 18, count 0 2006.260.07:47:31.51#ibcon#end of sib2, iclass 18, count 0 2006.260.07:47:31.51#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:47:31.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:47:31.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:47:31.51#ibcon#*before write, iclass 18, count 0 2006.260.07:47:31.51#ibcon#enter sib2, iclass 18, count 0 2006.260.07:47:31.51#ibcon#flushed, iclass 18, count 0 2006.260.07:47:31.51#ibcon#about to write, iclass 18, count 0 2006.260.07:47:31.51#ibcon#wrote, iclass 18, count 0 2006.260.07:47:31.51#ibcon#about to read 3, iclass 18, count 0 2006.260.07:47:31.55#ibcon#read 3, iclass 18, count 0 2006.260.07:47:31.55#ibcon#about to read 4, iclass 18, count 0 2006.260.07:47:31.55#ibcon#read 4, iclass 18, count 0 2006.260.07:47:31.55#ibcon#about to read 5, iclass 18, count 0 2006.260.07:47:31.55#ibcon#read 5, iclass 18, count 0 2006.260.07:47:31.55#ibcon#about to read 6, iclass 18, count 0 2006.260.07:47:31.55#ibcon#read 6, iclass 18, count 0 2006.260.07:47:31.55#ibcon#end of sib2, iclass 18, count 0 2006.260.07:47:31.55#ibcon#*after write, iclass 18, count 0 2006.260.07:47:31.55#ibcon#*before return 0, iclass 18, count 0 2006.260.07:47:31.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:47:31.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:47:31.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:47:31.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:47:31.55$vc4f8/va=8,6 2006.260.07:47:31.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:47:31.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:47:31.55#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:31.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:47:31.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:47:31.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:47:31.61#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:47:31.61#ibcon#first serial, iclass 20, count 2 2006.260.07:47:31.61#ibcon#enter sib2, iclass 20, count 2 2006.260.07:47:31.61#ibcon#flushed, iclass 20, count 2 2006.260.07:47:31.61#ibcon#about to write, iclass 20, count 2 2006.260.07:47:31.61#ibcon#wrote, iclass 20, count 2 2006.260.07:47:31.61#ibcon#about to read 3, iclass 20, count 2 2006.260.07:47:31.63#ibcon#read 3, iclass 20, count 2 2006.260.07:47:31.63#ibcon#about to read 4, iclass 20, count 2 2006.260.07:47:31.63#ibcon#read 4, iclass 20, count 2 2006.260.07:47:31.63#ibcon#about to read 5, iclass 20, count 2 2006.260.07:47:31.63#ibcon#read 5, iclass 20, count 2 2006.260.07:47:31.63#ibcon#about to read 6, iclass 20, count 2 2006.260.07:47:31.63#ibcon#read 6, iclass 20, count 2 2006.260.07:47:31.63#ibcon#end of sib2, iclass 20, count 2 2006.260.07:47:31.63#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:47:31.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:47:31.63#ibcon#[25=AT08-06\r\n] 2006.260.07:47:31.63#ibcon#*before write, iclass 20, count 2 2006.260.07:47:31.63#ibcon#enter sib2, iclass 20, count 2 2006.260.07:47:31.63#ibcon#flushed, iclass 20, count 2 2006.260.07:47:31.63#ibcon#about to write, iclass 20, count 2 2006.260.07:47:31.63#ibcon#wrote, iclass 20, count 2 2006.260.07:47:31.63#ibcon#about to read 3, iclass 20, count 2 2006.260.07:47:31.67#ibcon#read 3, iclass 20, count 2 2006.260.07:47:31.67#ibcon#about to read 4, iclass 20, count 2 2006.260.07:47:31.67#ibcon#read 4, iclass 20, count 2 2006.260.07:47:31.67#ibcon#about to read 5, iclass 20, count 2 2006.260.07:47:31.67#ibcon#read 5, iclass 20, count 2 2006.260.07:47:31.67#ibcon#about to read 6, iclass 20, count 2 2006.260.07:47:31.67#ibcon#read 6, iclass 20, count 2 2006.260.07:47:31.67#ibcon#end of sib2, iclass 20, count 2 2006.260.07:47:31.67#ibcon#*after write, iclass 20, count 2 2006.260.07:47:31.67#ibcon#*before return 0, iclass 20, count 2 2006.260.07:47:31.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:47:31.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:47:31.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:47:31.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:31.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:47:31.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:47:31.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:47:31.79#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:47:31.79#ibcon#first serial, iclass 20, count 0 2006.260.07:47:31.79#ibcon#enter sib2, iclass 20, count 0 2006.260.07:47:31.79#ibcon#flushed, iclass 20, count 0 2006.260.07:47:31.79#ibcon#about to write, iclass 20, count 0 2006.260.07:47:31.79#ibcon#wrote, iclass 20, count 0 2006.260.07:47:31.79#ibcon#about to read 3, iclass 20, count 0 2006.260.07:47:31.81#ibcon#read 3, iclass 20, count 0 2006.260.07:47:31.81#ibcon#about to read 4, iclass 20, count 0 2006.260.07:47:31.81#ibcon#read 4, iclass 20, count 0 2006.260.07:47:31.81#ibcon#about to read 5, iclass 20, count 0 2006.260.07:47:31.81#ibcon#read 5, iclass 20, count 0 2006.260.07:47:31.81#ibcon#about to read 6, iclass 20, count 0 2006.260.07:47:31.81#ibcon#read 6, iclass 20, count 0 2006.260.07:47:31.81#ibcon#end of sib2, iclass 20, count 0 2006.260.07:47:31.81#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:47:31.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:47:31.81#ibcon#[25=USB\r\n] 2006.260.07:47:31.81#ibcon#*before write, iclass 20, count 0 2006.260.07:47:31.81#ibcon#enter sib2, iclass 20, count 0 2006.260.07:47:31.81#ibcon#flushed, iclass 20, count 0 2006.260.07:47:31.81#ibcon#about to write, iclass 20, count 0 2006.260.07:47:31.81#ibcon#wrote, iclass 20, count 0 2006.260.07:47:31.81#ibcon#about to read 3, iclass 20, count 0 2006.260.07:47:31.84#ibcon#read 3, iclass 20, count 0 2006.260.07:47:31.84#ibcon#about to read 4, iclass 20, count 0 2006.260.07:47:31.84#ibcon#read 4, iclass 20, count 0 2006.260.07:47:31.84#ibcon#about to read 5, iclass 20, count 0 2006.260.07:47:31.84#ibcon#read 5, iclass 20, count 0 2006.260.07:47:31.84#ibcon#about to read 6, iclass 20, count 0 2006.260.07:47:31.84#ibcon#read 6, iclass 20, count 0 2006.260.07:47:31.84#ibcon#end of sib2, iclass 20, count 0 2006.260.07:47:31.84#ibcon#*after write, iclass 20, count 0 2006.260.07:47:31.84#ibcon#*before return 0, iclass 20, count 0 2006.260.07:47:31.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:47:31.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:47:31.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:47:31.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:47:31.84$vc4f8/vblo=1,632.99 2006.260.07:47:31.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:47:31.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:47:31.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:31.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:47:31.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:47:31.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:47:31.84#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:47:31.84#ibcon#first serial, iclass 22, count 0 2006.260.07:47:31.84#ibcon#enter sib2, iclass 22, count 0 2006.260.07:47:31.84#ibcon#flushed, iclass 22, count 0 2006.260.07:47:31.84#ibcon#about to write, iclass 22, count 0 2006.260.07:47:31.84#ibcon#wrote, iclass 22, count 0 2006.260.07:47:31.84#ibcon#about to read 3, iclass 22, count 0 2006.260.07:47:31.86#ibcon#read 3, iclass 22, count 0 2006.260.07:47:31.86#ibcon#about to read 4, iclass 22, count 0 2006.260.07:47:31.86#ibcon#read 4, iclass 22, count 0 2006.260.07:47:31.86#ibcon#about to read 5, iclass 22, count 0 2006.260.07:47:31.86#ibcon#read 5, iclass 22, count 0 2006.260.07:47:31.86#ibcon#about to read 6, iclass 22, count 0 2006.260.07:47:31.86#ibcon#read 6, iclass 22, count 0 2006.260.07:47:31.86#ibcon#end of sib2, iclass 22, count 0 2006.260.07:47:31.86#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:47:31.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:47:31.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:47:31.86#ibcon#*before write, iclass 22, count 0 2006.260.07:47:31.86#ibcon#enter sib2, iclass 22, count 0 2006.260.07:47:31.86#ibcon#flushed, iclass 22, count 0 2006.260.07:47:31.86#ibcon#about to write, iclass 22, count 0 2006.260.07:47:31.86#ibcon#wrote, iclass 22, count 0 2006.260.07:47:31.86#ibcon#about to read 3, iclass 22, count 0 2006.260.07:47:31.90#ibcon#read 3, iclass 22, count 0 2006.260.07:47:31.90#ibcon#about to read 4, iclass 22, count 0 2006.260.07:47:31.90#ibcon#read 4, iclass 22, count 0 2006.260.07:47:31.90#ibcon#about to read 5, iclass 22, count 0 2006.260.07:47:31.90#ibcon#read 5, iclass 22, count 0 2006.260.07:47:31.90#ibcon#about to read 6, iclass 22, count 0 2006.260.07:47:31.90#ibcon#read 6, iclass 22, count 0 2006.260.07:47:31.90#ibcon#end of sib2, iclass 22, count 0 2006.260.07:47:31.90#ibcon#*after write, iclass 22, count 0 2006.260.07:47:31.90#ibcon#*before return 0, iclass 22, count 0 2006.260.07:47:31.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:47:31.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:47:31.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:47:31.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:47:31.90$vc4f8/vb=1,4 2006.260.07:47:31.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:47:31.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:47:31.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:31.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:47:31.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:47:31.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:47:31.90#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:47:31.90#ibcon#first serial, iclass 24, count 2 2006.260.07:47:31.90#ibcon#enter sib2, iclass 24, count 2 2006.260.07:47:31.90#ibcon#flushed, iclass 24, count 2 2006.260.07:47:31.90#ibcon#about to write, iclass 24, count 2 2006.260.07:47:31.90#ibcon#wrote, iclass 24, count 2 2006.260.07:47:31.90#ibcon#about to read 3, iclass 24, count 2 2006.260.07:47:31.92#ibcon#read 3, iclass 24, count 2 2006.260.07:47:31.92#ibcon#about to read 4, iclass 24, count 2 2006.260.07:47:31.92#ibcon#read 4, iclass 24, count 2 2006.260.07:47:31.92#ibcon#about to read 5, iclass 24, count 2 2006.260.07:47:31.92#ibcon#read 5, iclass 24, count 2 2006.260.07:47:31.92#ibcon#about to read 6, iclass 24, count 2 2006.260.07:47:31.92#ibcon#read 6, iclass 24, count 2 2006.260.07:47:31.92#ibcon#end of sib2, iclass 24, count 2 2006.260.07:47:31.92#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:47:31.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:47:31.92#ibcon#[27=AT01-04\r\n] 2006.260.07:47:31.92#ibcon#*before write, iclass 24, count 2 2006.260.07:47:31.92#ibcon#enter sib2, iclass 24, count 2 2006.260.07:47:31.92#ibcon#flushed, iclass 24, count 2 2006.260.07:47:31.92#ibcon#about to write, iclass 24, count 2 2006.260.07:47:31.92#ibcon#wrote, iclass 24, count 2 2006.260.07:47:31.92#ibcon#about to read 3, iclass 24, count 2 2006.260.07:47:31.95#ibcon#read 3, iclass 24, count 2 2006.260.07:47:31.95#ibcon#about to read 4, iclass 24, count 2 2006.260.07:47:31.95#ibcon#read 4, iclass 24, count 2 2006.260.07:47:31.95#ibcon#about to read 5, iclass 24, count 2 2006.260.07:47:31.95#ibcon#read 5, iclass 24, count 2 2006.260.07:47:31.95#ibcon#about to read 6, iclass 24, count 2 2006.260.07:47:31.95#ibcon#read 6, iclass 24, count 2 2006.260.07:47:31.95#ibcon#end of sib2, iclass 24, count 2 2006.260.07:47:31.95#ibcon#*after write, iclass 24, count 2 2006.260.07:47:31.95#ibcon#*before return 0, iclass 24, count 2 2006.260.07:47:31.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:47:31.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:47:31.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:47:31.95#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:31.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:47:32.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:47:32.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:47:32.07#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:47:32.07#ibcon#first serial, iclass 24, count 0 2006.260.07:47:32.07#ibcon#enter sib2, iclass 24, count 0 2006.260.07:47:32.07#ibcon#flushed, iclass 24, count 0 2006.260.07:47:32.07#ibcon#about to write, iclass 24, count 0 2006.260.07:47:32.07#ibcon#wrote, iclass 24, count 0 2006.260.07:47:32.07#ibcon#about to read 3, iclass 24, count 0 2006.260.07:47:32.09#ibcon#read 3, iclass 24, count 0 2006.260.07:47:32.09#ibcon#about to read 4, iclass 24, count 0 2006.260.07:47:32.09#ibcon#read 4, iclass 24, count 0 2006.260.07:47:32.09#ibcon#about to read 5, iclass 24, count 0 2006.260.07:47:32.09#ibcon#read 5, iclass 24, count 0 2006.260.07:47:32.09#ibcon#about to read 6, iclass 24, count 0 2006.260.07:47:32.09#ibcon#read 6, iclass 24, count 0 2006.260.07:47:32.09#ibcon#end of sib2, iclass 24, count 0 2006.260.07:47:32.09#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:47:32.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:47:32.09#ibcon#[27=USB\r\n] 2006.260.07:47:32.09#ibcon#*before write, iclass 24, count 0 2006.260.07:47:32.09#ibcon#enter sib2, iclass 24, count 0 2006.260.07:47:32.09#ibcon#flushed, iclass 24, count 0 2006.260.07:47:32.09#ibcon#about to write, iclass 24, count 0 2006.260.07:47:32.09#ibcon#wrote, iclass 24, count 0 2006.260.07:47:32.09#ibcon#about to read 3, iclass 24, count 0 2006.260.07:47:32.12#ibcon#read 3, iclass 24, count 0 2006.260.07:47:32.12#ibcon#about to read 4, iclass 24, count 0 2006.260.07:47:32.12#ibcon#read 4, iclass 24, count 0 2006.260.07:47:32.12#ibcon#about to read 5, iclass 24, count 0 2006.260.07:47:32.12#ibcon#read 5, iclass 24, count 0 2006.260.07:47:32.12#ibcon#about to read 6, iclass 24, count 0 2006.260.07:47:32.12#ibcon#read 6, iclass 24, count 0 2006.260.07:47:32.12#ibcon#end of sib2, iclass 24, count 0 2006.260.07:47:32.12#ibcon#*after write, iclass 24, count 0 2006.260.07:47:32.12#ibcon#*before return 0, iclass 24, count 0 2006.260.07:47:32.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:47:32.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:47:32.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:47:32.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:47:32.12$vc4f8/vblo=2,640.99 2006.260.07:47:32.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:47:32.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:47:32.12#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:32.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:32.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:32.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:32.12#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:47:32.12#ibcon#first serial, iclass 26, count 0 2006.260.07:47:32.12#ibcon#enter sib2, iclass 26, count 0 2006.260.07:47:32.12#ibcon#flushed, iclass 26, count 0 2006.260.07:47:32.12#ibcon#about to write, iclass 26, count 0 2006.260.07:47:32.12#ibcon#wrote, iclass 26, count 0 2006.260.07:47:32.12#ibcon#about to read 3, iclass 26, count 0 2006.260.07:47:32.14#ibcon#read 3, iclass 26, count 0 2006.260.07:47:32.14#ibcon#about to read 4, iclass 26, count 0 2006.260.07:47:32.14#ibcon#read 4, iclass 26, count 0 2006.260.07:47:32.14#ibcon#about to read 5, iclass 26, count 0 2006.260.07:47:32.14#ibcon#read 5, iclass 26, count 0 2006.260.07:47:32.14#ibcon#about to read 6, iclass 26, count 0 2006.260.07:47:32.14#ibcon#read 6, iclass 26, count 0 2006.260.07:47:32.14#ibcon#end of sib2, iclass 26, count 0 2006.260.07:47:32.14#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:47:32.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:47:32.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:47:32.14#ibcon#*before write, iclass 26, count 0 2006.260.07:47:32.14#ibcon#enter sib2, iclass 26, count 0 2006.260.07:47:32.14#ibcon#flushed, iclass 26, count 0 2006.260.07:47:32.14#ibcon#about to write, iclass 26, count 0 2006.260.07:47:32.14#ibcon#wrote, iclass 26, count 0 2006.260.07:47:32.14#ibcon#about to read 3, iclass 26, count 0 2006.260.07:47:32.18#ibcon#read 3, iclass 26, count 0 2006.260.07:47:32.18#ibcon#about to read 4, iclass 26, count 0 2006.260.07:47:32.18#ibcon#read 4, iclass 26, count 0 2006.260.07:47:32.18#ibcon#about to read 5, iclass 26, count 0 2006.260.07:47:32.18#ibcon#read 5, iclass 26, count 0 2006.260.07:47:32.18#ibcon#about to read 6, iclass 26, count 0 2006.260.07:47:32.18#ibcon#read 6, iclass 26, count 0 2006.260.07:47:32.18#ibcon#end of sib2, iclass 26, count 0 2006.260.07:47:32.18#ibcon#*after write, iclass 26, count 0 2006.260.07:47:32.18#ibcon#*before return 0, iclass 26, count 0 2006.260.07:47:32.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:32.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:47:32.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:47:32.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:47:32.18$vc4f8/vb=2,5 2006.260.07:47:32.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:47:32.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:47:32.18#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:32.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:32.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:32.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:32.24#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:47:32.24#ibcon#first serial, iclass 28, count 2 2006.260.07:47:32.24#ibcon#enter sib2, iclass 28, count 2 2006.260.07:47:32.24#ibcon#flushed, iclass 28, count 2 2006.260.07:47:32.24#ibcon#about to write, iclass 28, count 2 2006.260.07:47:32.24#ibcon#wrote, iclass 28, count 2 2006.260.07:47:32.24#ibcon#about to read 3, iclass 28, count 2 2006.260.07:47:32.26#ibcon#read 3, iclass 28, count 2 2006.260.07:47:32.26#ibcon#about to read 4, iclass 28, count 2 2006.260.07:47:32.26#ibcon#read 4, iclass 28, count 2 2006.260.07:47:32.26#ibcon#about to read 5, iclass 28, count 2 2006.260.07:47:32.26#ibcon#read 5, iclass 28, count 2 2006.260.07:47:32.26#ibcon#about to read 6, iclass 28, count 2 2006.260.07:47:32.26#ibcon#read 6, iclass 28, count 2 2006.260.07:47:32.26#ibcon#end of sib2, iclass 28, count 2 2006.260.07:47:32.26#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:47:32.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:47:32.26#ibcon#[27=AT02-05\r\n] 2006.260.07:47:32.26#ibcon#*before write, iclass 28, count 2 2006.260.07:47:32.26#ibcon#enter sib2, iclass 28, count 2 2006.260.07:47:32.26#ibcon#flushed, iclass 28, count 2 2006.260.07:47:32.26#ibcon#about to write, iclass 28, count 2 2006.260.07:47:32.26#ibcon#wrote, iclass 28, count 2 2006.260.07:47:32.26#ibcon#about to read 3, iclass 28, count 2 2006.260.07:47:32.29#ibcon#read 3, iclass 28, count 2 2006.260.07:47:32.29#ibcon#about to read 4, iclass 28, count 2 2006.260.07:47:32.29#ibcon#read 4, iclass 28, count 2 2006.260.07:47:32.29#ibcon#about to read 5, iclass 28, count 2 2006.260.07:47:32.29#ibcon#read 5, iclass 28, count 2 2006.260.07:47:32.29#ibcon#about to read 6, iclass 28, count 2 2006.260.07:47:32.29#ibcon#read 6, iclass 28, count 2 2006.260.07:47:32.29#ibcon#end of sib2, iclass 28, count 2 2006.260.07:47:32.29#ibcon#*after write, iclass 28, count 2 2006.260.07:47:32.29#ibcon#*before return 0, iclass 28, count 2 2006.260.07:47:32.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:32.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:47:32.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:47:32.29#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:32.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:32.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:32.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:32.41#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:47:32.41#ibcon#first serial, iclass 28, count 0 2006.260.07:47:32.41#ibcon#enter sib2, iclass 28, count 0 2006.260.07:47:32.41#ibcon#flushed, iclass 28, count 0 2006.260.07:47:32.41#ibcon#about to write, iclass 28, count 0 2006.260.07:47:32.41#ibcon#wrote, iclass 28, count 0 2006.260.07:47:32.41#ibcon#about to read 3, iclass 28, count 0 2006.260.07:47:32.43#ibcon#read 3, iclass 28, count 0 2006.260.07:47:32.43#ibcon#about to read 4, iclass 28, count 0 2006.260.07:47:32.43#ibcon#read 4, iclass 28, count 0 2006.260.07:47:32.43#ibcon#about to read 5, iclass 28, count 0 2006.260.07:47:32.43#ibcon#read 5, iclass 28, count 0 2006.260.07:47:32.43#ibcon#about to read 6, iclass 28, count 0 2006.260.07:47:32.43#ibcon#read 6, iclass 28, count 0 2006.260.07:47:32.43#ibcon#end of sib2, iclass 28, count 0 2006.260.07:47:32.43#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:47:32.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:47:32.43#ibcon#[27=USB\r\n] 2006.260.07:47:32.43#ibcon#*before write, iclass 28, count 0 2006.260.07:47:32.43#ibcon#enter sib2, iclass 28, count 0 2006.260.07:47:32.43#ibcon#flushed, iclass 28, count 0 2006.260.07:47:32.43#ibcon#about to write, iclass 28, count 0 2006.260.07:47:32.43#ibcon#wrote, iclass 28, count 0 2006.260.07:47:32.43#ibcon#about to read 3, iclass 28, count 0 2006.260.07:47:32.46#ibcon#read 3, iclass 28, count 0 2006.260.07:47:32.46#ibcon#about to read 4, iclass 28, count 0 2006.260.07:47:32.46#ibcon#read 4, iclass 28, count 0 2006.260.07:47:32.46#ibcon#about to read 5, iclass 28, count 0 2006.260.07:47:32.46#ibcon#read 5, iclass 28, count 0 2006.260.07:47:32.46#ibcon#about to read 6, iclass 28, count 0 2006.260.07:47:32.46#ibcon#read 6, iclass 28, count 0 2006.260.07:47:32.46#ibcon#end of sib2, iclass 28, count 0 2006.260.07:47:32.46#ibcon#*after write, iclass 28, count 0 2006.260.07:47:32.46#ibcon#*before return 0, iclass 28, count 0 2006.260.07:47:32.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:32.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:47:32.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:47:32.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:47:32.46$vc4f8/vblo=3,656.99 2006.260.07:47:32.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.07:47:32.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.07:47:32.46#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:32.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:32.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:32.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:32.46#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:47:32.46#ibcon#first serial, iclass 30, count 0 2006.260.07:47:32.46#ibcon#enter sib2, iclass 30, count 0 2006.260.07:47:32.46#ibcon#flushed, iclass 30, count 0 2006.260.07:47:32.46#ibcon#about to write, iclass 30, count 0 2006.260.07:47:32.46#ibcon#wrote, iclass 30, count 0 2006.260.07:47:32.46#ibcon#about to read 3, iclass 30, count 0 2006.260.07:47:32.48#ibcon#read 3, iclass 30, count 0 2006.260.07:47:32.48#ibcon#about to read 4, iclass 30, count 0 2006.260.07:47:32.48#ibcon#read 4, iclass 30, count 0 2006.260.07:47:32.48#ibcon#about to read 5, iclass 30, count 0 2006.260.07:47:32.48#ibcon#read 5, iclass 30, count 0 2006.260.07:47:32.48#ibcon#about to read 6, iclass 30, count 0 2006.260.07:47:32.48#ibcon#read 6, iclass 30, count 0 2006.260.07:47:32.48#ibcon#end of sib2, iclass 30, count 0 2006.260.07:47:32.48#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:47:32.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:47:32.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:47:32.48#ibcon#*before write, iclass 30, count 0 2006.260.07:47:32.48#ibcon#enter sib2, iclass 30, count 0 2006.260.07:47:32.48#ibcon#flushed, iclass 30, count 0 2006.260.07:47:32.48#ibcon#about to write, iclass 30, count 0 2006.260.07:47:32.48#ibcon#wrote, iclass 30, count 0 2006.260.07:47:32.48#ibcon#about to read 3, iclass 30, count 0 2006.260.07:47:32.52#ibcon#read 3, iclass 30, count 0 2006.260.07:47:32.52#ibcon#about to read 4, iclass 30, count 0 2006.260.07:47:32.52#ibcon#read 4, iclass 30, count 0 2006.260.07:47:32.52#ibcon#about to read 5, iclass 30, count 0 2006.260.07:47:32.52#ibcon#read 5, iclass 30, count 0 2006.260.07:47:32.52#ibcon#about to read 6, iclass 30, count 0 2006.260.07:47:32.52#ibcon#read 6, iclass 30, count 0 2006.260.07:47:32.52#ibcon#end of sib2, iclass 30, count 0 2006.260.07:47:32.52#ibcon#*after write, iclass 30, count 0 2006.260.07:47:32.52#ibcon#*before return 0, iclass 30, count 0 2006.260.07:47:32.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:32.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.07:47:32.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:47:32.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:47:32.52$vc4f8/vb=3,4 2006.260.07:47:32.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.07:47:32.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.07:47:32.52#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:32.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:32.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:32.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:32.58#ibcon#enter wrdev, iclass 32, count 2 2006.260.07:47:32.58#ibcon#first serial, iclass 32, count 2 2006.260.07:47:32.58#ibcon#enter sib2, iclass 32, count 2 2006.260.07:47:32.58#ibcon#flushed, iclass 32, count 2 2006.260.07:47:32.58#ibcon#about to write, iclass 32, count 2 2006.260.07:47:32.58#ibcon#wrote, iclass 32, count 2 2006.260.07:47:32.58#ibcon#about to read 3, iclass 32, count 2 2006.260.07:47:32.60#ibcon#read 3, iclass 32, count 2 2006.260.07:47:32.60#ibcon#about to read 4, iclass 32, count 2 2006.260.07:47:32.60#ibcon#read 4, iclass 32, count 2 2006.260.07:47:32.60#ibcon#about to read 5, iclass 32, count 2 2006.260.07:47:32.60#ibcon#read 5, iclass 32, count 2 2006.260.07:47:32.60#ibcon#about to read 6, iclass 32, count 2 2006.260.07:47:32.60#ibcon#read 6, iclass 32, count 2 2006.260.07:47:32.60#ibcon#end of sib2, iclass 32, count 2 2006.260.07:47:32.60#ibcon#*mode == 0, iclass 32, count 2 2006.260.07:47:32.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.07:47:32.60#ibcon#[27=AT03-04\r\n] 2006.260.07:47:32.60#ibcon#*before write, iclass 32, count 2 2006.260.07:47:32.60#ibcon#enter sib2, iclass 32, count 2 2006.260.07:47:32.60#ibcon#flushed, iclass 32, count 2 2006.260.07:47:32.60#ibcon#about to write, iclass 32, count 2 2006.260.07:47:32.60#ibcon#wrote, iclass 32, count 2 2006.260.07:47:32.60#ibcon#about to read 3, iclass 32, count 2 2006.260.07:47:32.63#ibcon#read 3, iclass 32, count 2 2006.260.07:47:32.63#ibcon#about to read 4, iclass 32, count 2 2006.260.07:47:32.63#ibcon#read 4, iclass 32, count 2 2006.260.07:47:32.63#ibcon#about to read 5, iclass 32, count 2 2006.260.07:47:32.63#ibcon#read 5, iclass 32, count 2 2006.260.07:47:32.63#ibcon#about to read 6, iclass 32, count 2 2006.260.07:47:32.63#ibcon#read 6, iclass 32, count 2 2006.260.07:47:32.63#ibcon#end of sib2, iclass 32, count 2 2006.260.07:47:32.63#ibcon#*after write, iclass 32, count 2 2006.260.07:47:32.63#ibcon#*before return 0, iclass 32, count 2 2006.260.07:47:32.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:32.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.07:47:32.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.07:47:32.63#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:32.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:32.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:32.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:32.75#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:47:32.75#ibcon#first serial, iclass 32, count 0 2006.260.07:47:32.75#ibcon#enter sib2, iclass 32, count 0 2006.260.07:47:32.75#ibcon#flushed, iclass 32, count 0 2006.260.07:47:32.75#ibcon#about to write, iclass 32, count 0 2006.260.07:47:32.75#ibcon#wrote, iclass 32, count 0 2006.260.07:47:32.75#ibcon#about to read 3, iclass 32, count 0 2006.260.07:47:32.77#ibcon#read 3, iclass 32, count 0 2006.260.07:47:32.77#ibcon#about to read 4, iclass 32, count 0 2006.260.07:47:32.77#ibcon#read 4, iclass 32, count 0 2006.260.07:47:32.77#ibcon#about to read 5, iclass 32, count 0 2006.260.07:47:32.77#ibcon#read 5, iclass 32, count 0 2006.260.07:47:32.77#ibcon#about to read 6, iclass 32, count 0 2006.260.07:47:32.77#ibcon#read 6, iclass 32, count 0 2006.260.07:47:32.77#ibcon#end of sib2, iclass 32, count 0 2006.260.07:47:32.77#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:47:32.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:47:32.77#ibcon#[27=USB\r\n] 2006.260.07:47:32.77#ibcon#*before write, iclass 32, count 0 2006.260.07:47:32.77#ibcon#enter sib2, iclass 32, count 0 2006.260.07:47:32.77#ibcon#flushed, iclass 32, count 0 2006.260.07:47:32.77#ibcon#about to write, iclass 32, count 0 2006.260.07:47:32.77#ibcon#wrote, iclass 32, count 0 2006.260.07:47:32.77#ibcon#about to read 3, iclass 32, count 0 2006.260.07:47:32.80#ibcon#read 3, iclass 32, count 0 2006.260.07:47:32.80#ibcon#about to read 4, iclass 32, count 0 2006.260.07:47:32.80#ibcon#read 4, iclass 32, count 0 2006.260.07:47:32.80#ibcon#about to read 5, iclass 32, count 0 2006.260.07:47:32.80#ibcon#read 5, iclass 32, count 0 2006.260.07:47:32.80#ibcon#about to read 6, iclass 32, count 0 2006.260.07:47:32.80#ibcon#read 6, iclass 32, count 0 2006.260.07:47:32.80#ibcon#end of sib2, iclass 32, count 0 2006.260.07:47:32.80#ibcon#*after write, iclass 32, count 0 2006.260.07:47:32.80#ibcon#*before return 0, iclass 32, count 0 2006.260.07:47:32.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:32.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.07:47:32.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:47:32.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:47:32.80$vc4f8/vblo=4,712.99 2006.260.07:47:32.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:47:32.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:47:32.80#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:32.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:32.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:32.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:32.80#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:47:32.80#ibcon#first serial, iclass 34, count 0 2006.260.07:47:32.80#ibcon#enter sib2, iclass 34, count 0 2006.260.07:47:32.80#ibcon#flushed, iclass 34, count 0 2006.260.07:47:32.80#ibcon#about to write, iclass 34, count 0 2006.260.07:47:32.80#ibcon#wrote, iclass 34, count 0 2006.260.07:47:32.80#ibcon#about to read 3, iclass 34, count 0 2006.260.07:47:32.82#ibcon#read 3, iclass 34, count 0 2006.260.07:47:32.82#ibcon#about to read 4, iclass 34, count 0 2006.260.07:47:32.82#ibcon#read 4, iclass 34, count 0 2006.260.07:47:32.82#ibcon#about to read 5, iclass 34, count 0 2006.260.07:47:32.82#ibcon#read 5, iclass 34, count 0 2006.260.07:47:32.82#ibcon#about to read 6, iclass 34, count 0 2006.260.07:47:32.82#ibcon#read 6, iclass 34, count 0 2006.260.07:47:32.82#ibcon#end of sib2, iclass 34, count 0 2006.260.07:47:32.82#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:47:32.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:47:32.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:47:32.82#ibcon#*before write, iclass 34, count 0 2006.260.07:47:32.82#ibcon#enter sib2, iclass 34, count 0 2006.260.07:47:32.82#ibcon#flushed, iclass 34, count 0 2006.260.07:47:32.82#ibcon#about to write, iclass 34, count 0 2006.260.07:47:32.82#ibcon#wrote, iclass 34, count 0 2006.260.07:47:32.82#ibcon#about to read 3, iclass 34, count 0 2006.260.07:47:32.86#ibcon#read 3, iclass 34, count 0 2006.260.07:47:32.86#ibcon#about to read 4, iclass 34, count 0 2006.260.07:47:32.86#ibcon#read 4, iclass 34, count 0 2006.260.07:47:32.86#ibcon#about to read 5, iclass 34, count 0 2006.260.07:47:32.86#ibcon#read 5, iclass 34, count 0 2006.260.07:47:32.86#ibcon#about to read 6, iclass 34, count 0 2006.260.07:47:32.86#ibcon#read 6, iclass 34, count 0 2006.260.07:47:32.86#ibcon#end of sib2, iclass 34, count 0 2006.260.07:47:32.86#ibcon#*after write, iclass 34, count 0 2006.260.07:47:32.86#ibcon#*before return 0, iclass 34, count 0 2006.260.07:47:32.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:32.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:47:32.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:47:32.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:47:32.86$vc4f8/vb=4,5 2006.260.07:47:32.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:47:32.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:47:32.86#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:32.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:32.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:32.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:32.92#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:47:32.92#ibcon#first serial, iclass 36, count 2 2006.260.07:47:32.92#ibcon#enter sib2, iclass 36, count 2 2006.260.07:47:32.92#ibcon#flushed, iclass 36, count 2 2006.260.07:47:32.92#ibcon#about to write, iclass 36, count 2 2006.260.07:47:32.92#ibcon#wrote, iclass 36, count 2 2006.260.07:47:32.92#ibcon#about to read 3, iclass 36, count 2 2006.260.07:47:32.94#ibcon#read 3, iclass 36, count 2 2006.260.07:47:32.94#ibcon#about to read 4, iclass 36, count 2 2006.260.07:47:32.94#ibcon#read 4, iclass 36, count 2 2006.260.07:47:32.94#ibcon#about to read 5, iclass 36, count 2 2006.260.07:47:32.94#ibcon#read 5, iclass 36, count 2 2006.260.07:47:32.94#ibcon#about to read 6, iclass 36, count 2 2006.260.07:47:32.94#ibcon#read 6, iclass 36, count 2 2006.260.07:47:32.94#ibcon#end of sib2, iclass 36, count 2 2006.260.07:47:32.94#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:47:32.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:47:32.94#ibcon#[27=AT04-05\r\n] 2006.260.07:47:32.94#ibcon#*before write, iclass 36, count 2 2006.260.07:47:32.94#ibcon#enter sib2, iclass 36, count 2 2006.260.07:47:32.94#ibcon#flushed, iclass 36, count 2 2006.260.07:47:32.94#ibcon#about to write, iclass 36, count 2 2006.260.07:47:32.94#ibcon#wrote, iclass 36, count 2 2006.260.07:47:32.94#ibcon#about to read 3, iclass 36, count 2 2006.260.07:47:32.97#ibcon#read 3, iclass 36, count 2 2006.260.07:47:32.97#ibcon#about to read 4, iclass 36, count 2 2006.260.07:47:32.97#ibcon#read 4, iclass 36, count 2 2006.260.07:47:32.97#ibcon#about to read 5, iclass 36, count 2 2006.260.07:47:32.97#ibcon#read 5, iclass 36, count 2 2006.260.07:47:32.97#ibcon#about to read 6, iclass 36, count 2 2006.260.07:47:32.97#ibcon#read 6, iclass 36, count 2 2006.260.07:47:32.97#ibcon#end of sib2, iclass 36, count 2 2006.260.07:47:32.97#ibcon#*after write, iclass 36, count 2 2006.260.07:47:32.97#ibcon#*before return 0, iclass 36, count 2 2006.260.07:47:32.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:32.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:47:32.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:47:32.97#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:32.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:33.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:33.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:33.09#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:47:33.09#ibcon#first serial, iclass 36, count 0 2006.260.07:47:33.09#ibcon#enter sib2, iclass 36, count 0 2006.260.07:47:33.09#ibcon#flushed, iclass 36, count 0 2006.260.07:47:33.09#ibcon#about to write, iclass 36, count 0 2006.260.07:47:33.09#ibcon#wrote, iclass 36, count 0 2006.260.07:47:33.09#ibcon#about to read 3, iclass 36, count 0 2006.260.07:47:33.11#ibcon#read 3, iclass 36, count 0 2006.260.07:47:33.11#ibcon#about to read 4, iclass 36, count 0 2006.260.07:47:33.11#ibcon#read 4, iclass 36, count 0 2006.260.07:47:33.11#ibcon#about to read 5, iclass 36, count 0 2006.260.07:47:33.11#ibcon#read 5, iclass 36, count 0 2006.260.07:47:33.11#ibcon#about to read 6, iclass 36, count 0 2006.260.07:47:33.11#ibcon#read 6, iclass 36, count 0 2006.260.07:47:33.11#ibcon#end of sib2, iclass 36, count 0 2006.260.07:47:33.11#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:47:33.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:47:33.11#ibcon#[27=USB\r\n] 2006.260.07:47:33.11#ibcon#*before write, iclass 36, count 0 2006.260.07:47:33.11#ibcon#enter sib2, iclass 36, count 0 2006.260.07:47:33.11#ibcon#flushed, iclass 36, count 0 2006.260.07:47:33.11#ibcon#about to write, iclass 36, count 0 2006.260.07:47:33.11#ibcon#wrote, iclass 36, count 0 2006.260.07:47:33.11#ibcon#about to read 3, iclass 36, count 0 2006.260.07:47:33.14#ibcon#read 3, iclass 36, count 0 2006.260.07:47:33.14#ibcon#about to read 4, iclass 36, count 0 2006.260.07:47:33.14#ibcon#read 4, iclass 36, count 0 2006.260.07:47:33.14#ibcon#about to read 5, iclass 36, count 0 2006.260.07:47:33.14#ibcon#read 5, iclass 36, count 0 2006.260.07:47:33.14#ibcon#about to read 6, iclass 36, count 0 2006.260.07:47:33.14#ibcon#read 6, iclass 36, count 0 2006.260.07:47:33.14#ibcon#end of sib2, iclass 36, count 0 2006.260.07:47:33.14#ibcon#*after write, iclass 36, count 0 2006.260.07:47:33.14#ibcon#*before return 0, iclass 36, count 0 2006.260.07:47:33.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:33.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:47:33.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:47:33.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:47:33.14$vc4f8/vblo=5,744.99 2006.260.07:47:33.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:47:33.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:47:33.14#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:33.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:33.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:33.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:33.14#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:47:33.14#ibcon#first serial, iclass 38, count 0 2006.260.07:47:33.14#ibcon#enter sib2, iclass 38, count 0 2006.260.07:47:33.14#ibcon#flushed, iclass 38, count 0 2006.260.07:47:33.14#ibcon#about to write, iclass 38, count 0 2006.260.07:47:33.14#ibcon#wrote, iclass 38, count 0 2006.260.07:47:33.14#ibcon#about to read 3, iclass 38, count 0 2006.260.07:47:33.16#ibcon#read 3, iclass 38, count 0 2006.260.07:47:33.16#ibcon#about to read 4, iclass 38, count 0 2006.260.07:47:33.16#ibcon#read 4, iclass 38, count 0 2006.260.07:47:33.16#ibcon#about to read 5, iclass 38, count 0 2006.260.07:47:33.16#ibcon#read 5, iclass 38, count 0 2006.260.07:47:33.16#ibcon#about to read 6, iclass 38, count 0 2006.260.07:47:33.16#ibcon#read 6, iclass 38, count 0 2006.260.07:47:33.16#ibcon#end of sib2, iclass 38, count 0 2006.260.07:47:33.16#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:47:33.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:47:33.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:47:33.16#ibcon#*before write, iclass 38, count 0 2006.260.07:47:33.16#ibcon#enter sib2, iclass 38, count 0 2006.260.07:47:33.16#ibcon#flushed, iclass 38, count 0 2006.260.07:47:33.16#ibcon#about to write, iclass 38, count 0 2006.260.07:47:33.16#ibcon#wrote, iclass 38, count 0 2006.260.07:47:33.16#ibcon#about to read 3, iclass 38, count 0 2006.260.07:47:33.20#ibcon#read 3, iclass 38, count 0 2006.260.07:47:33.20#ibcon#about to read 4, iclass 38, count 0 2006.260.07:47:33.20#ibcon#read 4, iclass 38, count 0 2006.260.07:47:33.20#ibcon#about to read 5, iclass 38, count 0 2006.260.07:47:33.20#ibcon#read 5, iclass 38, count 0 2006.260.07:47:33.20#ibcon#about to read 6, iclass 38, count 0 2006.260.07:47:33.20#ibcon#read 6, iclass 38, count 0 2006.260.07:47:33.20#ibcon#end of sib2, iclass 38, count 0 2006.260.07:47:33.20#ibcon#*after write, iclass 38, count 0 2006.260.07:47:33.20#ibcon#*before return 0, iclass 38, count 0 2006.260.07:47:33.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:33.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:47:33.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:47:33.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:47:33.20$vc4f8/vb=5,4 2006.260.07:47:33.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:47:33.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:47:33.20#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:33.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:33.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:33.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:33.26#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:47:33.26#ibcon#first serial, iclass 40, count 2 2006.260.07:47:33.26#ibcon#enter sib2, iclass 40, count 2 2006.260.07:47:33.26#ibcon#flushed, iclass 40, count 2 2006.260.07:47:33.26#ibcon#about to write, iclass 40, count 2 2006.260.07:47:33.26#ibcon#wrote, iclass 40, count 2 2006.260.07:47:33.26#ibcon#about to read 3, iclass 40, count 2 2006.260.07:47:33.28#ibcon#read 3, iclass 40, count 2 2006.260.07:47:33.28#ibcon#about to read 4, iclass 40, count 2 2006.260.07:47:33.28#ibcon#read 4, iclass 40, count 2 2006.260.07:47:33.28#ibcon#about to read 5, iclass 40, count 2 2006.260.07:47:33.28#ibcon#read 5, iclass 40, count 2 2006.260.07:47:33.28#ibcon#about to read 6, iclass 40, count 2 2006.260.07:47:33.28#ibcon#read 6, iclass 40, count 2 2006.260.07:47:33.28#ibcon#end of sib2, iclass 40, count 2 2006.260.07:47:33.28#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:47:33.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:47:33.28#ibcon#[27=AT05-04\r\n] 2006.260.07:47:33.28#ibcon#*before write, iclass 40, count 2 2006.260.07:47:33.28#ibcon#enter sib2, iclass 40, count 2 2006.260.07:47:33.28#ibcon#flushed, iclass 40, count 2 2006.260.07:47:33.28#ibcon#about to write, iclass 40, count 2 2006.260.07:47:33.28#ibcon#wrote, iclass 40, count 2 2006.260.07:47:33.28#ibcon#about to read 3, iclass 40, count 2 2006.260.07:47:33.31#ibcon#read 3, iclass 40, count 2 2006.260.07:47:33.31#ibcon#about to read 4, iclass 40, count 2 2006.260.07:47:33.31#ibcon#read 4, iclass 40, count 2 2006.260.07:47:33.31#ibcon#about to read 5, iclass 40, count 2 2006.260.07:47:33.31#ibcon#read 5, iclass 40, count 2 2006.260.07:47:33.31#ibcon#about to read 6, iclass 40, count 2 2006.260.07:47:33.31#ibcon#read 6, iclass 40, count 2 2006.260.07:47:33.31#ibcon#end of sib2, iclass 40, count 2 2006.260.07:47:33.31#ibcon#*after write, iclass 40, count 2 2006.260.07:47:33.31#ibcon#*before return 0, iclass 40, count 2 2006.260.07:47:33.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:33.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:47:33.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:47:33.31#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:33.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:33.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:33.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:33.43#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:47:33.43#ibcon#first serial, iclass 40, count 0 2006.260.07:47:33.43#ibcon#enter sib2, iclass 40, count 0 2006.260.07:47:33.43#ibcon#flushed, iclass 40, count 0 2006.260.07:47:33.43#ibcon#about to write, iclass 40, count 0 2006.260.07:47:33.43#ibcon#wrote, iclass 40, count 0 2006.260.07:47:33.43#ibcon#about to read 3, iclass 40, count 0 2006.260.07:47:33.45#ibcon#read 3, iclass 40, count 0 2006.260.07:47:33.45#ibcon#about to read 4, iclass 40, count 0 2006.260.07:47:33.45#ibcon#read 4, iclass 40, count 0 2006.260.07:47:33.45#ibcon#about to read 5, iclass 40, count 0 2006.260.07:47:33.45#ibcon#read 5, iclass 40, count 0 2006.260.07:47:33.45#ibcon#about to read 6, iclass 40, count 0 2006.260.07:47:33.45#ibcon#read 6, iclass 40, count 0 2006.260.07:47:33.45#ibcon#end of sib2, iclass 40, count 0 2006.260.07:47:33.45#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:47:33.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:47:33.45#ibcon#[27=USB\r\n] 2006.260.07:47:33.45#ibcon#*before write, iclass 40, count 0 2006.260.07:47:33.45#ibcon#enter sib2, iclass 40, count 0 2006.260.07:47:33.45#ibcon#flushed, iclass 40, count 0 2006.260.07:47:33.45#ibcon#about to write, iclass 40, count 0 2006.260.07:47:33.45#ibcon#wrote, iclass 40, count 0 2006.260.07:47:33.45#ibcon#about to read 3, iclass 40, count 0 2006.260.07:47:33.48#ibcon#read 3, iclass 40, count 0 2006.260.07:47:33.48#ibcon#about to read 4, iclass 40, count 0 2006.260.07:47:33.48#ibcon#read 4, iclass 40, count 0 2006.260.07:47:33.48#ibcon#about to read 5, iclass 40, count 0 2006.260.07:47:33.48#ibcon#read 5, iclass 40, count 0 2006.260.07:47:33.48#ibcon#about to read 6, iclass 40, count 0 2006.260.07:47:33.48#ibcon#read 6, iclass 40, count 0 2006.260.07:47:33.48#ibcon#end of sib2, iclass 40, count 0 2006.260.07:47:33.48#ibcon#*after write, iclass 40, count 0 2006.260.07:47:33.48#ibcon#*before return 0, iclass 40, count 0 2006.260.07:47:33.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:33.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:47:33.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:47:33.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:47:33.48$vc4f8/vblo=6,752.99 2006.260.07:47:33.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:47:33.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:47:33.48#ibcon#ireg 17 cls_cnt 0 2006.260.07:47:33.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:33.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:33.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:33.48#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:47:33.48#ibcon#first serial, iclass 4, count 0 2006.260.07:47:33.48#ibcon#enter sib2, iclass 4, count 0 2006.260.07:47:33.48#ibcon#flushed, iclass 4, count 0 2006.260.07:47:33.48#ibcon#about to write, iclass 4, count 0 2006.260.07:47:33.48#ibcon#wrote, iclass 4, count 0 2006.260.07:47:33.48#ibcon#about to read 3, iclass 4, count 0 2006.260.07:47:33.50#ibcon#read 3, iclass 4, count 0 2006.260.07:47:33.50#ibcon#about to read 4, iclass 4, count 0 2006.260.07:47:33.50#ibcon#read 4, iclass 4, count 0 2006.260.07:47:33.50#ibcon#about to read 5, iclass 4, count 0 2006.260.07:47:33.50#ibcon#read 5, iclass 4, count 0 2006.260.07:47:33.50#ibcon#about to read 6, iclass 4, count 0 2006.260.07:47:33.50#ibcon#read 6, iclass 4, count 0 2006.260.07:47:33.50#ibcon#end of sib2, iclass 4, count 0 2006.260.07:47:33.50#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:47:33.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:47:33.50#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:47:33.50#ibcon#*before write, iclass 4, count 0 2006.260.07:47:33.50#ibcon#enter sib2, iclass 4, count 0 2006.260.07:47:33.50#ibcon#flushed, iclass 4, count 0 2006.260.07:47:33.50#ibcon#about to write, iclass 4, count 0 2006.260.07:47:33.50#ibcon#wrote, iclass 4, count 0 2006.260.07:47:33.50#ibcon#about to read 3, iclass 4, count 0 2006.260.07:47:33.54#ibcon#read 3, iclass 4, count 0 2006.260.07:47:33.54#ibcon#about to read 4, iclass 4, count 0 2006.260.07:47:33.54#ibcon#read 4, iclass 4, count 0 2006.260.07:47:33.54#ibcon#about to read 5, iclass 4, count 0 2006.260.07:47:33.54#ibcon#read 5, iclass 4, count 0 2006.260.07:47:33.54#ibcon#about to read 6, iclass 4, count 0 2006.260.07:47:33.54#ibcon#read 6, iclass 4, count 0 2006.260.07:47:33.54#ibcon#end of sib2, iclass 4, count 0 2006.260.07:47:33.54#ibcon#*after write, iclass 4, count 0 2006.260.07:47:33.54#ibcon#*before return 0, iclass 4, count 0 2006.260.07:47:33.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:33.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:47:33.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:47:33.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:47:33.54$vc4f8/vb=6,4 2006.260.07:47:33.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:47:33.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:47:33.54#ibcon#ireg 11 cls_cnt 2 2006.260.07:47:33.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:33.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:33.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:33.60#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:47:33.60#ibcon#first serial, iclass 6, count 2 2006.260.07:47:33.60#ibcon#enter sib2, iclass 6, count 2 2006.260.07:47:33.60#ibcon#flushed, iclass 6, count 2 2006.260.07:47:33.60#ibcon#about to write, iclass 6, count 2 2006.260.07:47:33.60#ibcon#wrote, iclass 6, count 2 2006.260.07:47:33.60#ibcon#about to read 3, iclass 6, count 2 2006.260.07:47:33.62#ibcon#read 3, iclass 6, count 2 2006.260.07:47:33.62#ibcon#about to read 4, iclass 6, count 2 2006.260.07:47:33.62#ibcon#read 4, iclass 6, count 2 2006.260.07:47:33.62#ibcon#about to read 5, iclass 6, count 2 2006.260.07:47:33.62#ibcon#read 5, iclass 6, count 2 2006.260.07:47:33.62#ibcon#about to read 6, iclass 6, count 2 2006.260.07:47:33.62#ibcon#read 6, iclass 6, count 2 2006.260.07:47:33.62#ibcon#end of sib2, iclass 6, count 2 2006.260.07:47:33.62#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:47:33.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:47:33.62#ibcon#[27=AT06-04\r\n] 2006.260.07:47:33.62#ibcon#*before write, iclass 6, count 2 2006.260.07:47:33.62#ibcon#enter sib2, iclass 6, count 2 2006.260.07:47:33.62#ibcon#flushed, iclass 6, count 2 2006.260.07:47:33.62#ibcon#about to write, iclass 6, count 2 2006.260.07:47:33.62#ibcon#wrote, iclass 6, count 2 2006.260.07:47:33.62#ibcon#about to read 3, iclass 6, count 2 2006.260.07:47:33.65#ibcon#read 3, iclass 6, count 2 2006.260.07:47:33.65#ibcon#about to read 4, iclass 6, count 2 2006.260.07:47:33.65#ibcon#read 4, iclass 6, count 2 2006.260.07:47:33.65#ibcon#about to read 5, iclass 6, count 2 2006.260.07:47:33.65#ibcon#read 5, iclass 6, count 2 2006.260.07:47:33.65#ibcon#about to read 6, iclass 6, count 2 2006.260.07:47:33.65#ibcon#read 6, iclass 6, count 2 2006.260.07:47:33.65#ibcon#end of sib2, iclass 6, count 2 2006.260.07:47:33.65#ibcon#*after write, iclass 6, count 2 2006.260.07:47:33.65#ibcon#*before return 0, iclass 6, count 2 2006.260.07:47:33.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:33.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:47:33.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:47:33.65#ibcon#ireg 7 cls_cnt 0 2006.260.07:47:33.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:33.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:33.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:33.77#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:47:33.77#ibcon#first serial, iclass 6, count 0 2006.260.07:47:33.77#ibcon#enter sib2, iclass 6, count 0 2006.260.07:47:33.77#ibcon#flushed, iclass 6, count 0 2006.260.07:47:33.77#ibcon#about to write, iclass 6, count 0 2006.260.07:47:33.77#ibcon#wrote, iclass 6, count 0 2006.260.07:47:33.77#ibcon#about to read 3, iclass 6, count 0 2006.260.07:47:33.79#ibcon#read 3, iclass 6, count 0 2006.260.07:47:33.79#ibcon#about to read 4, iclass 6, count 0 2006.260.07:47:33.79#ibcon#read 4, iclass 6, count 0 2006.260.07:47:33.79#ibcon#about to read 5, iclass 6, count 0 2006.260.07:47:33.79#ibcon#read 5, iclass 6, count 0 2006.260.07:47:33.79#ibcon#about to read 6, iclass 6, count 0 2006.260.07:47:33.79#ibcon#read 6, iclass 6, count 0 2006.260.07:47:33.79#ibcon#end of sib2, iclass 6, count 0 2006.260.07:47:33.79#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:47:33.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:47:33.79#ibcon#[27=USB\r\n] 2006.260.07:47:33.79#ibcon#*before write, iclass 6, count 0 2006.260.07:47:33.79#ibcon#enter sib2, iclass 6, count 0 2006.260.07:47:33.79#ibcon#flushed, iclass 6, count 0 2006.260.07:47:33.79#ibcon#about to write, iclass 6, count 0 2006.260.07:47:33.79#ibcon#wrote, iclass 6, count 0 2006.260.07:47:33.79#ibcon#about to read 3, iclass 6, count 0 2006.260.07:47:33.82#ibcon#read 3, iclass 6, count 0 2006.260.07:47:33.82#ibcon#about to read 4, iclass 6, count 0 2006.260.07:47:33.82#ibcon#read 4, iclass 6, count 0 2006.260.07:47:33.82#ibcon#about to read 5, iclass 6, count 0 2006.260.07:47:33.82#ibcon#read 5, iclass 6, count 0 2006.260.07:47:33.82#ibcon#about to read 6, iclass 6, count 0 2006.260.07:47:33.82#ibcon#read 6, iclass 6, count 0 2006.260.07:47:33.82#ibcon#end of sib2, iclass 6, count 0 2006.260.07:47:33.82#ibcon#*after write, iclass 6, count 0 2006.260.07:47:33.82#ibcon#*before return 0, iclass 6, count 0 2006.260.07:47:33.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:33.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:47:33.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:47:33.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:47:33.82$vc4f8/vabw=wide 2006.260.07:47:33.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:47:33.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:47:33.82#ibcon#ireg 8 cls_cnt 0 2006.260.07:47:33.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:33.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:33.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:33.82#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:47:33.82#ibcon#first serial, iclass 10, count 0 2006.260.07:47:33.82#ibcon#enter sib2, iclass 10, count 0 2006.260.07:47:33.82#ibcon#flushed, iclass 10, count 0 2006.260.07:47:33.82#ibcon#about to write, iclass 10, count 0 2006.260.07:47:33.82#ibcon#wrote, iclass 10, count 0 2006.260.07:47:33.82#ibcon#about to read 3, iclass 10, count 0 2006.260.07:47:33.84#ibcon#read 3, iclass 10, count 0 2006.260.07:47:33.84#ibcon#about to read 4, iclass 10, count 0 2006.260.07:47:33.84#ibcon#read 4, iclass 10, count 0 2006.260.07:47:33.84#ibcon#about to read 5, iclass 10, count 0 2006.260.07:47:33.84#ibcon#read 5, iclass 10, count 0 2006.260.07:47:33.84#ibcon#about to read 6, iclass 10, count 0 2006.260.07:47:33.84#ibcon#read 6, iclass 10, count 0 2006.260.07:47:33.84#ibcon#end of sib2, iclass 10, count 0 2006.260.07:47:33.84#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:47:33.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:47:33.84#ibcon#[25=BW32\r\n] 2006.260.07:47:33.84#ibcon#*before write, iclass 10, count 0 2006.260.07:47:33.84#ibcon#enter sib2, iclass 10, count 0 2006.260.07:47:33.84#ibcon#flushed, iclass 10, count 0 2006.260.07:47:33.84#ibcon#about to write, iclass 10, count 0 2006.260.07:47:33.84#ibcon#wrote, iclass 10, count 0 2006.260.07:47:33.84#ibcon#about to read 3, iclass 10, count 0 2006.260.07:47:33.87#ibcon#read 3, iclass 10, count 0 2006.260.07:47:33.87#ibcon#about to read 4, iclass 10, count 0 2006.260.07:47:33.87#ibcon#read 4, iclass 10, count 0 2006.260.07:47:33.87#ibcon#about to read 5, iclass 10, count 0 2006.260.07:47:33.87#ibcon#read 5, iclass 10, count 0 2006.260.07:47:33.87#ibcon#about to read 6, iclass 10, count 0 2006.260.07:47:33.87#ibcon#read 6, iclass 10, count 0 2006.260.07:47:33.87#ibcon#end of sib2, iclass 10, count 0 2006.260.07:47:33.87#ibcon#*after write, iclass 10, count 0 2006.260.07:47:33.87#ibcon#*before return 0, iclass 10, count 0 2006.260.07:47:33.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:33.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:47:33.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:47:33.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:47:33.87$vc4f8/vbbw=wide 2006.260.07:47:33.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:47:33.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:47:33.87#ibcon#ireg 8 cls_cnt 0 2006.260.07:47:33.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:47:33.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:47:33.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:47:33.94#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:47:33.94#ibcon#first serial, iclass 12, count 0 2006.260.07:47:33.94#ibcon#enter sib2, iclass 12, count 0 2006.260.07:47:33.94#ibcon#flushed, iclass 12, count 0 2006.260.07:47:33.94#ibcon#about to write, iclass 12, count 0 2006.260.07:47:33.94#ibcon#wrote, iclass 12, count 0 2006.260.07:47:33.94#ibcon#about to read 3, iclass 12, count 0 2006.260.07:47:33.96#ibcon#read 3, iclass 12, count 0 2006.260.07:47:33.96#ibcon#about to read 4, iclass 12, count 0 2006.260.07:47:33.96#ibcon#read 4, iclass 12, count 0 2006.260.07:47:33.96#ibcon#about to read 5, iclass 12, count 0 2006.260.07:47:33.96#ibcon#read 5, iclass 12, count 0 2006.260.07:47:33.96#ibcon#about to read 6, iclass 12, count 0 2006.260.07:47:33.96#ibcon#read 6, iclass 12, count 0 2006.260.07:47:33.96#ibcon#end of sib2, iclass 12, count 0 2006.260.07:47:33.96#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:47:33.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:47:33.96#ibcon#[27=BW32\r\n] 2006.260.07:47:33.96#ibcon#*before write, iclass 12, count 0 2006.260.07:47:33.96#ibcon#enter sib2, iclass 12, count 0 2006.260.07:47:33.96#ibcon#flushed, iclass 12, count 0 2006.260.07:47:33.96#ibcon#about to write, iclass 12, count 0 2006.260.07:47:33.96#ibcon#wrote, iclass 12, count 0 2006.260.07:47:33.96#ibcon#about to read 3, iclass 12, count 0 2006.260.07:47:33.99#ibcon#read 3, iclass 12, count 0 2006.260.07:47:33.99#ibcon#about to read 4, iclass 12, count 0 2006.260.07:47:33.99#ibcon#read 4, iclass 12, count 0 2006.260.07:47:33.99#ibcon#about to read 5, iclass 12, count 0 2006.260.07:47:33.99#ibcon#read 5, iclass 12, count 0 2006.260.07:47:33.99#ibcon#about to read 6, iclass 12, count 0 2006.260.07:47:33.99#ibcon#read 6, iclass 12, count 0 2006.260.07:47:33.99#ibcon#end of sib2, iclass 12, count 0 2006.260.07:47:33.99#ibcon#*after write, iclass 12, count 0 2006.260.07:47:33.99#ibcon#*before return 0, iclass 12, count 0 2006.260.07:47:33.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:47:33.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:47:33.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:47:33.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:47:33.99$4f8m12a/ifd4f 2006.260.07:47:33.99$ifd4f/lo= 2006.260.07:47:33.99$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:47:33.99$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:47:33.99$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:47:33.99$ifd4f/patch= 2006.260.07:47:33.99$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:47:33.99$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:47:33.99$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:47:33.99$4f8m12a/"form=m,16.000,1:2 2006.260.07:47:33.99$4f8m12a/"tpicd 2006.260.07:47:33.99$4f8m12a/echo=off 2006.260.07:47:33.99$4f8m12a/xlog=off 2006.260.07:47:33.99:!2006.260.07:48:00 2006.260.07:47:40.14#trakl#Source acquired 2006.260.07:47:42.14#flagr#flagr/antenna,acquired 2006.260.07:48:00.00:preob 2006.260.07:48:01.14/onsource/TRACKING 2006.260.07:48:01.14:!2006.260.07:48:10 2006.260.07:48:10.00:data_valid=on 2006.260.07:48:10.00:midob 2006.260.07:48:10.14/onsource/TRACKING 2006.260.07:48:10.14/wx/22.99,1010.4,87 2006.260.07:48:10.23/cable/+6.4581E-03 2006.260.07:48:11.32/va/01,08,usb,yes,31,32 2006.260.07:48:11.32/va/02,07,usb,yes,31,32 2006.260.07:48:11.32/va/03,08,usb,yes,23,23 2006.260.07:48:11.32/va/04,07,usb,yes,32,35 2006.260.07:48:11.32/va/05,07,usb,yes,35,37 2006.260.07:48:11.32/va/06,06,usb,yes,34,34 2006.260.07:48:11.32/va/07,06,usb,yes,35,35 2006.260.07:48:11.32/va/08,06,usb,yes,37,36 2006.260.07:48:11.55/valo/01,532.99,yes,locked 2006.260.07:48:11.55/valo/02,572.99,yes,locked 2006.260.07:48:11.55/valo/03,672.99,yes,locked 2006.260.07:48:11.55/valo/04,832.99,yes,locked 2006.260.07:48:11.55/valo/05,652.99,yes,locked 2006.260.07:48:11.55/valo/06,772.99,yes,locked 2006.260.07:48:11.55/valo/07,832.99,yes,locked 2006.260.07:48:11.55/valo/08,852.99,yes,locked 2006.260.07:48:12.64/vb/01,04,usb,yes,30,29 2006.260.07:48:12.64/vb/02,05,usb,yes,28,30 2006.260.07:48:12.64/vb/03,04,usb,yes,28,32 2006.260.07:48:12.64/vb/04,05,usb,yes,26,26 2006.260.07:48:12.64/vb/05,04,usb,yes,28,32 2006.260.07:48:12.64/vb/06,04,usb,yes,29,31 2006.260.07:48:12.64/vb/07,04,usb,yes,31,31 2006.260.07:48:12.64/vb/08,04,usb,yes,28,32 2006.260.07:48:12.88/vblo/01,632.99,yes,locked 2006.260.07:48:12.88/vblo/02,640.99,yes,locked 2006.260.07:48:12.88/vblo/03,656.99,yes,locked 2006.260.07:48:12.88/vblo/04,712.99,yes,locked 2006.260.07:48:12.88/vblo/05,744.99,yes,locked 2006.260.07:48:12.88/vblo/06,752.99,yes,locked 2006.260.07:48:12.88/vblo/07,734.99,yes,locked 2006.260.07:48:12.88/vblo/08,744.99,yes,locked 2006.260.07:48:13.03/vabw/8 2006.260.07:48:13.18/vbbw/8 2006.260.07:48:13.27/xfe/off,on,15.0 2006.260.07:48:13.65/ifatt/23,28,28,28 2006.260.07:48:14.08/fmout-gps/S +4.52E-07 2006.260.07:48:14.12:!2006.260.07:49:10 2006.260.07:49:10.00:data_valid=off 2006.260.07:49:10.00:postob 2006.260.07:49:10.20/cable/+6.4579E-03 2006.260.07:49:10.20/wx/22.98,1010.4,87 2006.260.07:49:11.08/fmout-gps/S +4.53E-07 2006.260.07:49:11.08:scan_name=260-0750,k06260,60 2006.260.07:49:11.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.260.07:49:11.14#flagr#flagr/antenna,new-source 2006.260.07:49:12.14:checkk5 2006.260.07:49:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:49:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:49:13.39/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:49:13.86/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:49:14.27/chk_obsdata//k5ts1/T2600748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:49:14.67/chk_obsdata//k5ts2/T2600748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:49:15.11/chk_obsdata//k5ts3/T2600748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:49:15.54/chk_obsdata//k5ts4/T2600748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:49:16.37/k5log//k5ts1_log_newline 2006.260.07:49:20.28/k5log//k5ts2_log_newline 2006.260.07:49:21.06/k5log//k5ts3_log_newline 2006.260.07:49:21.85/k5log//k5ts4_log_newline 2006.260.07:49:21.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:49:21.88:4f8m12a=1 2006.260.07:49:21.88$4f8m12a/echo=on 2006.260.07:49:21.88$4f8m12a/pcalon 2006.260.07:49:21.88$pcalon/"no phase cal control is implemented here 2006.260.07:49:21.88$4f8m12a/"tpicd=stop 2006.260.07:49:21.88$4f8m12a/vc4f8 2006.260.07:49:21.88$vc4f8/valo=1,532.99 2006.260.07:49:21.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:49:21.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:49:21.88#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:21.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:21.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:21.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:21.88#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:49:21.88#ibcon#first serial, iclass 23, count 0 2006.260.07:49:21.88#ibcon#enter sib2, iclass 23, count 0 2006.260.07:49:21.88#ibcon#flushed, iclass 23, count 0 2006.260.07:49:21.88#ibcon#about to write, iclass 23, count 0 2006.260.07:49:21.88#ibcon#wrote, iclass 23, count 0 2006.260.07:49:21.88#ibcon#about to read 3, iclass 23, count 0 2006.260.07:49:21.90#ibcon#read 3, iclass 23, count 0 2006.260.07:49:21.90#ibcon#about to read 4, iclass 23, count 0 2006.260.07:49:21.90#ibcon#read 4, iclass 23, count 0 2006.260.07:49:21.90#ibcon#about to read 5, iclass 23, count 0 2006.260.07:49:21.90#ibcon#read 5, iclass 23, count 0 2006.260.07:49:21.90#ibcon#about to read 6, iclass 23, count 0 2006.260.07:49:21.90#ibcon#read 6, iclass 23, count 0 2006.260.07:49:21.90#ibcon#end of sib2, iclass 23, count 0 2006.260.07:49:21.90#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:49:21.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:49:21.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:49:21.90#ibcon#*before write, iclass 23, count 0 2006.260.07:49:21.90#ibcon#enter sib2, iclass 23, count 0 2006.260.07:49:21.90#ibcon#flushed, iclass 23, count 0 2006.260.07:49:21.90#ibcon#about to write, iclass 23, count 0 2006.260.07:49:21.90#ibcon#wrote, iclass 23, count 0 2006.260.07:49:21.90#ibcon#about to read 3, iclass 23, count 0 2006.260.07:49:21.95#ibcon#read 3, iclass 23, count 0 2006.260.07:49:21.95#ibcon#about to read 4, iclass 23, count 0 2006.260.07:49:21.95#ibcon#read 4, iclass 23, count 0 2006.260.07:49:21.95#ibcon#about to read 5, iclass 23, count 0 2006.260.07:49:21.95#ibcon#read 5, iclass 23, count 0 2006.260.07:49:21.95#ibcon#about to read 6, iclass 23, count 0 2006.260.07:49:21.95#ibcon#read 6, iclass 23, count 0 2006.260.07:49:21.95#ibcon#end of sib2, iclass 23, count 0 2006.260.07:49:21.95#ibcon#*after write, iclass 23, count 0 2006.260.07:49:21.95#ibcon#*before return 0, iclass 23, count 0 2006.260.07:49:21.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:21.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:21.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:49:21.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:49:21.95$vc4f8/va=1,8 2006.260.07:49:21.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:49:21.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:49:21.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:21.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:21.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:21.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:21.95#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:49:21.95#ibcon#first serial, iclass 25, count 2 2006.260.07:49:21.95#ibcon#enter sib2, iclass 25, count 2 2006.260.07:49:21.95#ibcon#flushed, iclass 25, count 2 2006.260.07:49:21.95#ibcon#about to write, iclass 25, count 2 2006.260.07:49:21.95#ibcon#wrote, iclass 25, count 2 2006.260.07:49:21.95#ibcon#about to read 3, iclass 25, count 2 2006.260.07:49:21.97#ibcon#read 3, iclass 25, count 2 2006.260.07:49:21.97#ibcon#about to read 4, iclass 25, count 2 2006.260.07:49:21.97#ibcon#read 4, iclass 25, count 2 2006.260.07:49:21.97#ibcon#about to read 5, iclass 25, count 2 2006.260.07:49:21.97#ibcon#read 5, iclass 25, count 2 2006.260.07:49:21.97#ibcon#about to read 6, iclass 25, count 2 2006.260.07:49:21.97#ibcon#read 6, iclass 25, count 2 2006.260.07:49:21.97#ibcon#end of sib2, iclass 25, count 2 2006.260.07:49:21.97#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:49:21.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:49:21.97#ibcon#[25=AT01-08\r\n] 2006.260.07:49:21.97#ibcon#*before write, iclass 25, count 2 2006.260.07:49:21.97#ibcon#enter sib2, iclass 25, count 2 2006.260.07:49:21.97#ibcon#flushed, iclass 25, count 2 2006.260.07:49:21.97#ibcon#about to write, iclass 25, count 2 2006.260.07:49:21.97#ibcon#wrote, iclass 25, count 2 2006.260.07:49:21.97#ibcon#about to read 3, iclass 25, count 2 2006.260.07:49:22.00#ibcon#read 3, iclass 25, count 2 2006.260.07:49:22.00#ibcon#about to read 4, iclass 25, count 2 2006.260.07:49:22.00#ibcon#read 4, iclass 25, count 2 2006.260.07:49:22.00#ibcon#about to read 5, iclass 25, count 2 2006.260.07:49:22.00#ibcon#read 5, iclass 25, count 2 2006.260.07:49:22.00#ibcon#about to read 6, iclass 25, count 2 2006.260.07:49:22.00#ibcon#read 6, iclass 25, count 2 2006.260.07:49:22.00#ibcon#end of sib2, iclass 25, count 2 2006.260.07:49:22.00#ibcon#*after write, iclass 25, count 2 2006.260.07:49:22.00#ibcon#*before return 0, iclass 25, count 2 2006.260.07:49:22.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:22.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:22.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:49:22.00#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:22.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:22.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:22.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:22.12#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:49:22.12#ibcon#first serial, iclass 25, count 0 2006.260.07:49:22.12#ibcon#enter sib2, iclass 25, count 0 2006.260.07:49:22.12#ibcon#flushed, iclass 25, count 0 2006.260.07:49:22.12#ibcon#about to write, iclass 25, count 0 2006.260.07:49:22.12#ibcon#wrote, iclass 25, count 0 2006.260.07:49:22.12#ibcon#about to read 3, iclass 25, count 0 2006.260.07:49:22.14#ibcon#read 3, iclass 25, count 0 2006.260.07:49:22.14#ibcon#about to read 4, iclass 25, count 0 2006.260.07:49:22.14#ibcon#read 4, iclass 25, count 0 2006.260.07:49:22.14#ibcon#about to read 5, iclass 25, count 0 2006.260.07:49:22.14#ibcon#read 5, iclass 25, count 0 2006.260.07:49:22.14#ibcon#about to read 6, iclass 25, count 0 2006.260.07:49:22.14#ibcon#read 6, iclass 25, count 0 2006.260.07:49:22.14#ibcon#end of sib2, iclass 25, count 0 2006.260.07:49:22.14#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:49:22.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:49:22.14#ibcon#[25=USB\r\n] 2006.260.07:49:22.14#ibcon#*before write, iclass 25, count 0 2006.260.07:49:22.14#ibcon#enter sib2, iclass 25, count 0 2006.260.07:49:22.14#ibcon#flushed, iclass 25, count 0 2006.260.07:49:22.14#ibcon#about to write, iclass 25, count 0 2006.260.07:49:22.14#ibcon#wrote, iclass 25, count 0 2006.260.07:49:22.14#ibcon#about to read 3, iclass 25, count 0 2006.260.07:49:22.17#ibcon#read 3, iclass 25, count 0 2006.260.07:49:22.17#ibcon#about to read 4, iclass 25, count 0 2006.260.07:49:22.17#ibcon#read 4, iclass 25, count 0 2006.260.07:49:22.17#ibcon#about to read 5, iclass 25, count 0 2006.260.07:49:22.17#ibcon#read 5, iclass 25, count 0 2006.260.07:49:22.17#ibcon#about to read 6, iclass 25, count 0 2006.260.07:49:22.17#ibcon#read 6, iclass 25, count 0 2006.260.07:49:22.17#ibcon#end of sib2, iclass 25, count 0 2006.260.07:49:22.17#ibcon#*after write, iclass 25, count 0 2006.260.07:49:22.17#ibcon#*before return 0, iclass 25, count 0 2006.260.07:49:22.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:22.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:22.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:49:22.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:49:22.17$vc4f8/valo=2,572.99 2006.260.07:49:22.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:49:22.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:49:22.17#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:22.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:22.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:22.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:22.17#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:49:22.17#ibcon#first serial, iclass 27, count 0 2006.260.07:49:22.17#ibcon#enter sib2, iclass 27, count 0 2006.260.07:49:22.17#ibcon#flushed, iclass 27, count 0 2006.260.07:49:22.17#ibcon#about to write, iclass 27, count 0 2006.260.07:49:22.17#ibcon#wrote, iclass 27, count 0 2006.260.07:49:22.17#ibcon#about to read 3, iclass 27, count 0 2006.260.07:49:22.19#ibcon#read 3, iclass 27, count 0 2006.260.07:49:22.19#ibcon#about to read 4, iclass 27, count 0 2006.260.07:49:22.19#ibcon#read 4, iclass 27, count 0 2006.260.07:49:22.19#ibcon#about to read 5, iclass 27, count 0 2006.260.07:49:22.19#ibcon#read 5, iclass 27, count 0 2006.260.07:49:22.19#ibcon#about to read 6, iclass 27, count 0 2006.260.07:49:22.19#ibcon#read 6, iclass 27, count 0 2006.260.07:49:22.19#ibcon#end of sib2, iclass 27, count 0 2006.260.07:49:22.19#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:49:22.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:49:22.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:49:22.19#ibcon#*before write, iclass 27, count 0 2006.260.07:49:22.19#ibcon#enter sib2, iclass 27, count 0 2006.260.07:49:22.19#ibcon#flushed, iclass 27, count 0 2006.260.07:49:22.19#ibcon#about to write, iclass 27, count 0 2006.260.07:49:22.19#ibcon#wrote, iclass 27, count 0 2006.260.07:49:22.19#ibcon#about to read 3, iclass 27, count 0 2006.260.07:49:22.23#ibcon#read 3, iclass 27, count 0 2006.260.07:49:22.23#ibcon#about to read 4, iclass 27, count 0 2006.260.07:49:22.23#ibcon#read 4, iclass 27, count 0 2006.260.07:49:22.23#ibcon#about to read 5, iclass 27, count 0 2006.260.07:49:22.23#ibcon#read 5, iclass 27, count 0 2006.260.07:49:22.23#ibcon#about to read 6, iclass 27, count 0 2006.260.07:49:22.23#ibcon#read 6, iclass 27, count 0 2006.260.07:49:22.23#ibcon#end of sib2, iclass 27, count 0 2006.260.07:49:22.23#ibcon#*after write, iclass 27, count 0 2006.260.07:49:22.23#ibcon#*before return 0, iclass 27, count 0 2006.260.07:49:22.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:22.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:22.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:49:22.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:49:22.23$vc4f8/va=2,7 2006.260.07:49:22.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:49:22.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:49:22.23#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:22.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:22.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:22.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:22.29#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:49:22.29#ibcon#first serial, iclass 29, count 2 2006.260.07:49:22.29#ibcon#enter sib2, iclass 29, count 2 2006.260.07:49:22.29#ibcon#flushed, iclass 29, count 2 2006.260.07:49:22.29#ibcon#about to write, iclass 29, count 2 2006.260.07:49:22.29#ibcon#wrote, iclass 29, count 2 2006.260.07:49:22.29#ibcon#about to read 3, iclass 29, count 2 2006.260.07:49:22.31#ibcon#read 3, iclass 29, count 2 2006.260.07:49:22.31#ibcon#about to read 4, iclass 29, count 2 2006.260.07:49:22.31#ibcon#read 4, iclass 29, count 2 2006.260.07:49:22.31#ibcon#about to read 5, iclass 29, count 2 2006.260.07:49:22.31#ibcon#read 5, iclass 29, count 2 2006.260.07:49:22.31#ibcon#about to read 6, iclass 29, count 2 2006.260.07:49:22.31#ibcon#read 6, iclass 29, count 2 2006.260.07:49:22.31#ibcon#end of sib2, iclass 29, count 2 2006.260.07:49:22.31#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:49:22.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:49:22.31#ibcon#[25=AT02-07\r\n] 2006.260.07:49:22.31#ibcon#*before write, iclass 29, count 2 2006.260.07:49:22.31#ibcon#enter sib2, iclass 29, count 2 2006.260.07:49:22.31#ibcon#flushed, iclass 29, count 2 2006.260.07:49:22.31#ibcon#about to write, iclass 29, count 2 2006.260.07:49:22.31#ibcon#wrote, iclass 29, count 2 2006.260.07:49:22.31#ibcon#about to read 3, iclass 29, count 2 2006.260.07:49:22.35#ibcon#read 3, iclass 29, count 2 2006.260.07:49:22.35#ibcon#about to read 4, iclass 29, count 2 2006.260.07:49:22.35#ibcon#read 4, iclass 29, count 2 2006.260.07:49:22.35#ibcon#about to read 5, iclass 29, count 2 2006.260.07:49:22.35#ibcon#read 5, iclass 29, count 2 2006.260.07:49:22.35#ibcon#about to read 6, iclass 29, count 2 2006.260.07:49:22.35#ibcon#read 6, iclass 29, count 2 2006.260.07:49:22.35#ibcon#end of sib2, iclass 29, count 2 2006.260.07:49:22.35#ibcon#*after write, iclass 29, count 2 2006.260.07:49:22.35#ibcon#*before return 0, iclass 29, count 2 2006.260.07:49:22.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:22.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:22.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:49:22.35#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:22.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:22.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:22.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:22.47#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:49:22.47#ibcon#first serial, iclass 29, count 0 2006.260.07:49:22.47#ibcon#enter sib2, iclass 29, count 0 2006.260.07:49:22.47#ibcon#flushed, iclass 29, count 0 2006.260.07:49:22.47#ibcon#about to write, iclass 29, count 0 2006.260.07:49:22.47#ibcon#wrote, iclass 29, count 0 2006.260.07:49:22.47#ibcon#about to read 3, iclass 29, count 0 2006.260.07:49:22.49#ibcon#read 3, iclass 29, count 0 2006.260.07:49:22.49#ibcon#about to read 4, iclass 29, count 0 2006.260.07:49:22.49#ibcon#read 4, iclass 29, count 0 2006.260.07:49:22.49#ibcon#about to read 5, iclass 29, count 0 2006.260.07:49:22.49#ibcon#read 5, iclass 29, count 0 2006.260.07:49:22.49#ibcon#about to read 6, iclass 29, count 0 2006.260.07:49:22.49#ibcon#read 6, iclass 29, count 0 2006.260.07:49:22.49#ibcon#end of sib2, iclass 29, count 0 2006.260.07:49:22.49#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:49:22.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:49:22.49#ibcon#[25=USB\r\n] 2006.260.07:49:22.49#ibcon#*before write, iclass 29, count 0 2006.260.07:49:22.49#ibcon#enter sib2, iclass 29, count 0 2006.260.07:49:22.49#ibcon#flushed, iclass 29, count 0 2006.260.07:49:22.49#ibcon#about to write, iclass 29, count 0 2006.260.07:49:22.49#ibcon#wrote, iclass 29, count 0 2006.260.07:49:22.49#ibcon#about to read 3, iclass 29, count 0 2006.260.07:49:22.52#ibcon#read 3, iclass 29, count 0 2006.260.07:49:22.52#ibcon#about to read 4, iclass 29, count 0 2006.260.07:49:22.52#ibcon#read 4, iclass 29, count 0 2006.260.07:49:22.52#ibcon#about to read 5, iclass 29, count 0 2006.260.07:49:22.52#ibcon#read 5, iclass 29, count 0 2006.260.07:49:22.52#ibcon#about to read 6, iclass 29, count 0 2006.260.07:49:22.52#ibcon#read 6, iclass 29, count 0 2006.260.07:49:22.52#ibcon#end of sib2, iclass 29, count 0 2006.260.07:49:22.52#ibcon#*after write, iclass 29, count 0 2006.260.07:49:22.52#ibcon#*before return 0, iclass 29, count 0 2006.260.07:49:22.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:22.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:22.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:49:22.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:49:22.52$vc4f8/valo=3,672.99 2006.260.07:49:22.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:49:22.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:49:22.52#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:22.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:22.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:22.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:22.52#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:49:22.52#ibcon#first serial, iclass 31, count 0 2006.260.07:49:22.52#ibcon#enter sib2, iclass 31, count 0 2006.260.07:49:22.52#ibcon#flushed, iclass 31, count 0 2006.260.07:49:22.52#ibcon#about to write, iclass 31, count 0 2006.260.07:49:22.52#ibcon#wrote, iclass 31, count 0 2006.260.07:49:22.52#ibcon#about to read 3, iclass 31, count 0 2006.260.07:49:22.54#ibcon#read 3, iclass 31, count 0 2006.260.07:49:22.54#ibcon#about to read 4, iclass 31, count 0 2006.260.07:49:22.54#ibcon#read 4, iclass 31, count 0 2006.260.07:49:22.54#ibcon#about to read 5, iclass 31, count 0 2006.260.07:49:22.54#ibcon#read 5, iclass 31, count 0 2006.260.07:49:22.54#ibcon#about to read 6, iclass 31, count 0 2006.260.07:49:22.54#ibcon#read 6, iclass 31, count 0 2006.260.07:49:22.54#ibcon#end of sib2, iclass 31, count 0 2006.260.07:49:22.54#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:49:22.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:49:22.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:49:22.54#ibcon#*before write, iclass 31, count 0 2006.260.07:49:22.54#ibcon#enter sib2, iclass 31, count 0 2006.260.07:49:22.54#ibcon#flushed, iclass 31, count 0 2006.260.07:49:22.54#ibcon#about to write, iclass 31, count 0 2006.260.07:49:22.54#ibcon#wrote, iclass 31, count 0 2006.260.07:49:22.54#ibcon#about to read 3, iclass 31, count 0 2006.260.07:49:22.58#ibcon#read 3, iclass 31, count 0 2006.260.07:49:22.58#ibcon#about to read 4, iclass 31, count 0 2006.260.07:49:22.58#ibcon#read 4, iclass 31, count 0 2006.260.07:49:22.58#ibcon#about to read 5, iclass 31, count 0 2006.260.07:49:22.58#ibcon#read 5, iclass 31, count 0 2006.260.07:49:22.58#ibcon#about to read 6, iclass 31, count 0 2006.260.07:49:22.58#ibcon#read 6, iclass 31, count 0 2006.260.07:49:22.58#ibcon#end of sib2, iclass 31, count 0 2006.260.07:49:22.58#ibcon#*after write, iclass 31, count 0 2006.260.07:49:22.58#ibcon#*before return 0, iclass 31, count 0 2006.260.07:49:22.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:22.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:22.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:49:22.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:49:22.58$vc4f8/va=3,8 2006.260.07:49:22.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:49:22.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:49:22.58#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:22.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:22.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:22.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:22.64#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:49:22.64#ibcon#first serial, iclass 33, count 2 2006.260.07:49:22.64#ibcon#enter sib2, iclass 33, count 2 2006.260.07:49:22.64#ibcon#flushed, iclass 33, count 2 2006.260.07:49:22.64#ibcon#about to write, iclass 33, count 2 2006.260.07:49:22.64#ibcon#wrote, iclass 33, count 2 2006.260.07:49:22.64#ibcon#about to read 3, iclass 33, count 2 2006.260.07:49:22.66#ibcon#read 3, iclass 33, count 2 2006.260.07:49:22.66#ibcon#about to read 4, iclass 33, count 2 2006.260.07:49:22.66#ibcon#read 4, iclass 33, count 2 2006.260.07:49:22.66#ibcon#about to read 5, iclass 33, count 2 2006.260.07:49:22.66#ibcon#read 5, iclass 33, count 2 2006.260.07:49:22.66#ibcon#about to read 6, iclass 33, count 2 2006.260.07:49:22.66#ibcon#read 6, iclass 33, count 2 2006.260.07:49:22.66#ibcon#end of sib2, iclass 33, count 2 2006.260.07:49:22.66#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:49:22.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:49:22.66#ibcon#[25=AT03-08\r\n] 2006.260.07:49:22.66#ibcon#*before write, iclass 33, count 2 2006.260.07:49:22.66#ibcon#enter sib2, iclass 33, count 2 2006.260.07:49:22.66#ibcon#flushed, iclass 33, count 2 2006.260.07:49:22.66#ibcon#about to write, iclass 33, count 2 2006.260.07:49:22.66#ibcon#wrote, iclass 33, count 2 2006.260.07:49:22.66#ibcon#about to read 3, iclass 33, count 2 2006.260.07:49:22.69#ibcon#read 3, iclass 33, count 2 2006.260.07:49:22.69#ibcon#about to read 4, iclass 33, count 2 2006.260.07:49:22.69#ibcon#read 4, iclass 33, count 2 2006.260.07:49:22.69#ibcon#about to read 5, iclass 33, count 2 2006.260.07:49:22.69#ibcon#read 5, iclass 33, count 2 2006.260.07:49:22.69#ibcon#about to read 6, iclass 33, count 2 2006.260.07:49:22.69#ibcon#read 6, iclass 33, count 2 2006.260.07:49:22.69#ibcon#end of sib2, iclass 33, count 2 2006.260.07:49:22.69#ibcon#*after write, iclass 33, count 2 2006.260.07:49:22.69#ibcon#*before return 0, iclass 33, count 2 2006.260.07:49:22.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:22.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:22.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:49:22.69#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:22.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:22.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:22.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:22.81#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:49:22.81#ibcon#first serial, iclass 33, count 0 2006.260.07:49:22.81#ibcon#enter sib2, iclass 33, count 0 2006.260.07:49:22.81#ibcon#flushed, iclass 33, count 0 2006.260.07:49:22.81#ibcon#about to write, iclass 33, count 0 2006.260.07:49:22.81#ibcon#wrote, iclass 33, count 0 2006.260.07:49:22.81#ibcon#about to read 3, iclass 33, count 0 2006.260.07:49:22.83#ibcon#read 3, iclass 33, count 0 2006.260.07:49:22.83#ibcon#about to read 4, iclass 33, count 0 2006.260.07:49:22.83#ibcon#read 4, iclass 33, count 0 2006.260.07:49:22.83#ibcon#about to read 5, iclass 33, count 0 2006.260.07:49:22.83#ibcon#read 5, iclass 33, count 0 2006.260.07:49:22.83#ibcon#about to read 6, iclass 33, count 0 2006.260.07:49:22.83#ibcon#read 6, iclass 33, count 0 2006.260.07:49:22.83#ibcon#end of sib2, iclass 33, count 0 2006.260.07:49:22.83#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:49:22.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:49:22.83#ibcon#[25=USB\r\n] 2006.260.07:49:22.83#ibcon#*before write, iclass 33, count 0 2006.260.07:49:22.83#ibcon#enter sib2, iclass 33, count 0 2006.260.07:49:22.83#ibcon#flushed, iclass 33, count 0 2006.260.07:49:22.83#ibcon#about to write, iclass 33, count 0 2006.260.07:49:22.83#ibcon#wrote, iclass 33, count 0 2006.260.07:49:22.83#ibcon#about to read 3, iclass 33, count 0 2006.260.07:49:22.86#ibcon#read 3, iclass 33, count 0 2006.260.07:49:22.86#ibcon#about to read 4, iclass 33, count 0 2006.260.07:49:22.86#ibcon#read 4, iclass 33, count 0 2006.260.07:49:22.86#ibcon#about to read 5, iclass 33, count 0 2006.260.07:49:22.86#ibcon#read 5, iclass 33, count 0 2006.260.07:49:22.86#ibcon#about to read 6, iclass 33, count 0 2006.260.07:49:22.86#ibcon#read 6, iclass 33, count 0 2006.260.07:49:22.86#ibcon#end of sib2, iclass 33, count 0 2006.260.07:49:22.86#ibcon#*after write, iclass 33, count 0 2006.260.07:49:22.86#ibcon#*before return 0, iclass 33, count 0 2006.260.07:49:22.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:22.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:22.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:49:22.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:49:22.86$vc4f8/valo=4,832.99 2006.260.07:49:22.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:49:22.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:49:22.86#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:22.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:22.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:22.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:22.86#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:49:22.86#ibcon#first serial, iclass 35, count 0 2006.260.07:49:22.86#ibcon#enter sib2, iclass 35, count 0 2006.260.07:49:22.86#ibcon#flushed, iclass 35, count 0 2006.260.07:49:22.86#ibcon#about to write, iclass 35, count 0 2006.260.07:49:22.86#ibcon#wrote, iclass 35, count 0 2006.260.07:49:22.86#ibcon#about to read 3, iclass 35, count 0 2006.260.07:49:22.88#ibcon#read 3, iclass 35, count 0 2006.260.07:49:22.88#ibcon#about to read 4, iclass 35, count 0 2006.260.07:49:22.88#ibcon#read 4, iclass 35, count 0 2006.260.07:49:22.88#ibcon#about to read 5, iclass 35, count 0 2006.260.07:49:22.88#ibcon#read 5, iclass 35, count 0 2006.260.07:49:22.88#ibcon#about to read 6, iclass 35, count 0 2006.260.07:49:22.88#ibcon#read 6, iclass 35, count 0 2006.260.07:49:22.88#ibcon#end of sib2, iclass 35, count 0 2006.260.07:49:22.88#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:49:22.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:49:22.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:49:22.88#ibcon#*before write, iclass 35, count 0 2006.260.07:49:22.88#ibcon#enter sib2, iclass 35, count 0 2006.260.07:49:22.88#ibcon#flushed, iclass 35, count 0 2006.260.07:49:22.88#ibcon#about to write, iclass 35, count 0 2006.260.07:49:22.88#ibcon#wrote, iclass 35, count 0 2006.260.07:49:22.88#ibcon#about to read 3, iclass 35, count 0 2006.260.07:49:22.92#ibcon#read 3, iclass 35, count 0 2006.260.07:49:22.92#ibcon#about to read 4, iclass 35, count 0 2006.260.07:49:22.92#ibcon#read 4, iclass 35, count 0 2006.260.07:49:22.92#ibcon#about to read 5, iclass 35, count 0 2006.260.07:49:22.92#ibcon#read 5, iclass 35, count 0 2006.260.07:49:22.92#ibcon#about to read 6, iclass 35, count 0 2006.260.07:49:22.92#ibcon#read 6, iclass 35, count 0 2006.260.07:49:22.92#ibcon#end of sib2, iclass 35, count 0 2006.260.07:49:22.92#ibcon#*after write, iclass 35, count 0 2006.260.07:49:22.92#ibcon#*before return 0, iclass 35, count 0 2006.260.07:49:22.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:22.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:22.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:49:22.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:49:22.92$vc4f8/va=4,7 2006.260.07:49:22.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:49:22.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:49:22.92#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:22.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:22.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:22.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:22.98#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:49:22.98#ibcon#first serial, iclass 37, count 2 2006.260.07:49:22.98#ibcon#enter sib2, iclass 37, count 2 2006.260.07:49:22.98#ibcon#flushed, iclass 37, count 2 2006.260.07:49:22.98#ibcon#about to write, iclass 37, count 2 2006.260.07:49:22.98#ibcon#wrote, iclass 37, count 2 2006.260.07:49:22.98#ibcon#about to read 3, iclass 37, count 2 2006.260.07:49:23.00#ibcon#read 3, iclass 37, count 2 2006.260.07:49:23.00#ibcon#about to read 4, iclass 37, count 2 2006.260.07:49:23.00#ibcon#read 4, iclass 37, count 2 2006.260.07:49:23.00#ibcon#about to read 5, iclass 37, count 2 2006.260.07:49:23.00#ibcon#read 5, iclass 37, count 2 2006.260.07:49:23.00#ibcon#about to read 6, iclass 37, count 2 2006.260.07:49:23.00#ibcon#read 6, iclass 37, count 2 2006.260.07:49:23.00#ibcon#end of sib2, iclass 37, count 2 2006.260.07:49:23.00#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:49:23.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:49:23.00#ibcon#[25=AT04-07\r\n] 2006.260.07:49:23.00#ibcon#*before write, iclass 37, count 2 2006.260.07:49:23.00#ibcon#enter sib2, iclass 37, count 2 2006.260.07:49:23.00#ibcon#flushed, iclass 37, count 2 2006.260.07:49:23.00#ibcon#about to write, iclass 37, count 2 2006.260.07:49:23.00#ibcon#wrote, iclass 37, count 2 2006.260.07:49:23.00#ibcon#about to read 3, iclass 37, count 2 2006.260.07:49:23.03#ibcon#read 3, iclass 37, count 2 2006.260.07:49:23.03#ibcon#about to read 4, iclass 37, count 2 2006.260.07:49:23.03#ibcon#read 4, iclass 37, count 2 2006.260.07:49:23.03#ibcon#about to read 5, iclass 37, count 2 2006.260.07:49:23.03#ibcon#read 5, iclass 37, count 2 2006.260.07:49:23.03#ibcon#about to read 6, iclass 37, count 2 2006.260.07:49:23.03#ibcon#read 6, iclass 37, count 2 2006.260.07:49:23.03#ibcon#end of sib2, iclass 37, count 2 2006.260.07:49:23.03#ibcon#*after write, iclass 37, count 2 2006.260.07:49:23.03#ibcon#*before return 0, iclass 37, count 2 2006.260.07:49:23.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:23.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:23.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:49:23.03#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:23.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:23.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:23.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:23.15#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:49:23.15#ibcon#first serial, iclass 37, count 0 2006.260.07:49:23.15#ibcon#enter sib2, iclass 37, count 0 2006.260.07:49:23.15#ibcon#flushed, iclass 37, count 0 2006.260.07:49:23.15#ibcon#about to write, iclass 37, count 0 2006.260.07:49:23.15#ibcon#wrote, iclass 37, count 0 2006.260.07:49:23.15#ibcon#about to read 3, iclass 37, count 0 2006.260.07:49:23.17#ibcon#read 3, iclass 37, count 0 2006.260.07:49:23.17#ibcon#about to read 4, iclass 37, count 0 2006.260.07:49:23.17#ibcon#read 4, iclass 37, count 0 2006.260.07:49:23.17#ibcon#about to read 5, iclass 37, count 0 2006.260.07:49:23.17#ibcon#read 5, iclass 37, count 0 2006.260.07:49:23.17#ibcon#about to read 6, iclass 37, count 0 2006.260.07:49:23.17#ibcon#read 6, iclass 37, count 0 2006.260.07:49:23.17#ibcon#end of sib2, iclass 37, count 0 2006.260.07:49:23.17#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:49:23.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:49:23.17#ibcon#[25=USB\r\n] 2006.260.07:49:23.17#ibcon#*before write, iclass 37, count 0 2006.260.07:49:23.17#ibcon#enter sib2, iclass 37, count 0 2006.260.07:49:23.17#ibcon#flushed, iclass 37, count 0 2006.260.07:49:23.17#ibcon#about to write, iclass 37, count 0 2006.260.07:49:23.17#ibcon#wrote, iclass 37, count 0 2006.260.07:49:23.17#ibcon#about to read 3, iclass 37, count 0 2006.260.07:49:23.20#ibcon#read 3, iclass 37, count 0 2006.260.07:49:23.20#ibcon#about to read 4, iclass 37, count 0 2006.260.07:49:23.20#ibcon#read 4, iclass 37, count 0 2006.260.07:49:23.20#ibcon#about to read 5, iclass 37, count 0 2006.260.07:49:23.20#ibcon#read 5, iclass 37, count 0 2006.260.07:49:23.20#ibcon#about to read 6, iclass 37, count 0 2006.260.07:49:23.20#ibcon#read 6, iclass 37, count 0 2006.260.07:49:23.20#ibcon#end of sib2, iclass 37, count 0 2006.260.07:49:23.20#ibcon#*after write, iclass 37, count 0 2006.260.07:49:23.20#ibcon#*before return 0, iclass 37, count 0 2006.260.07:49:23.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:23.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:23.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:49:23.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:49:23.20$vc4f8/valo=5,652.99 2006.260.07:49:23.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:49:23.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:49:23.20#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:23.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:23.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:23.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:23.20#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:49:23.20#ibcon#first serial, iclass 39, count 0 2006.260.07:49:23.20#ibcon#enter sib2, iclass 39, count 0 2006.260.07:49:23.20#ibcon#flushed, iclass 39, count 0 2006.260.07:49:23.20#ibcon#about to write, iclass 39, count 0 2006.260.07:49:23.20#ibcon#wrote, iclass 39, count 0 2006.260.07:49:23.20#ibcon#about to read 3, iclass 39, count 0 2006.260.07:49:23.22#ibcon#read 3, iclass 39, count 0 2006.260.07:49:23.22#ibcon#about to read 4, iclass 39, count 0 2006.260.07:49:23.22#ibcon#read 4, iclass 39, count 0 2006.260.07:49:23.22#ibcon#about to read 5, iclass 39, count 0 2006.260.07:49:23.22#ibcon#read 5, iclass 39, count 0 2006.260.07:49:23.22#ibcon#about to read 6, iclass 39, count 0 2006.260.07:49:23.22#ibcon#read 6, iclass 39, count 0 2006.260.07:49:23.22#ibcon#end of sib2, iclass 39, count 0 2006.260.07:49:23.22#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:49:23.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:49:23.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:49:23.22#ibcon#*before write, iclass 39, count 0 2006.260.07:49:23.22#ibcon#enter sib2, iclass 39, count 0 2006.260.07:49:23.22#ibcon#flushed, iclass 39, count 0 2006.260.07:49:23.22#ibcon#about to write, iclass 39, count 0 2006.260.07:49:23.22#ibcon#wrote, iclass 39, count 0 2006.260.07:49:23.22#ibcon#about to read 3, iclass 39, count 0 2006.260.07:49:23.26#ibcon#read 3, iclass 39, count 0 2006.260.07:49:23.26#ibcon#about to read 4, iclass 39, count 0 2006.260.07:49:23.26#ibcon#read 4, iclass 39, count 0 2006.260.07:49:23.26#ibcon#about to read 5, iclass 39, count 0 2006.260.07:49:23.26#ibcon#read 5, iclass 39, count 0 2006.260.07:49:23.26#ibcon#about to read 6, iclass 39, count 0 2006.260.07:49:23.26#ibcon#read 6, iclass 39, count 0 2006.260.07:49:23.26#ibcon#end of sib2, iclass 39, count 0 2006.260.07:49:23.26#ibcon#*after write, iclass 39, count 0 2006.260.07:49:23.26#ibcon#*before return 0, iclass 39, count 0 2006.260.07:49:23.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:23.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:23.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:49:23.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:49:23.26$vc4f8/va=5,7 2006.260.07:49:23.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:49:23.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:49:23.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:23.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:23.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:23.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:23.32#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:49:23.32#ibcon#first serial, iclass 3, count 2 2006.260.07:49:23.32#ibcon#enter sib2, iclass 3, count 2 2006.260.07:49:23.32#ibcon#flushed, iclass 3, count 2 2006.260.07:49:23.32#ibcon#about to write, iclass 3, count 2 2006.260.07:49:23.32#ibcon#wrote, iclass 3, count 2 2006.260.07:49:23.32#ibcon#about to read 3, iclass 3, count 2 2006.260.07:49:23.34#ibcon#read 3, iclass 3, count 2 2006.260.07:49:23.34#ibcon#about to read 4, iclass 3, count 2 2006.260.07:49:23.34#ibcon#read 4, iclass 3, count 2 2006.260.07:49:23.34#ibcon#about to read 5, iclass 3, count 2 2006.260.07:49:23.34#ibcon#read 5, iclass 3, count 2 2006.260.07:49:23.34#ibcon#about to read 6, iclass 3, count 2 2006.260.07:49:23.34#ibcon#read 6, iclass 3, count 2 2006.260.07:49:23.34#ibcon#end of sib2, iclass 3, count 2 2006.260.07:49:23.34#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:49:23.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:49:23.34#ibcon#[25=AT05-07\r\n] 2006.260.07:49:23.34#ibcon#*before write, iclass 3, count 2 2006.260.07:49:23.34#ibcon#enter sib2, iclass 3, count 2 2006.260.07:49:23.34#ibcon#flushed, iclass 3, count 2 2006.260.07:49:23.34#ibcon#about to write, iclass 3, count 2 2006.260.07:49:23.34#ibcon#wrote, iclass 3, count 2 2006.260.07:49:23.34#ibcon#about to read 3, iclass 3, count 2 2006.260.07:49:23.37#ibcon#read 3, iclass 3, count 2 2006.260.07:49:23.37#ibcon#about to read 4, iclass 3, count 2 2006.260.07:49:23.37#ibcon#read 4, iclass 3, count 2 2006.260.07:49:23.37#ibcon#about to read 5, iclass 3, count 2 2006.260.07:49:23.37#ibcon#read 5, iclass 3, count 2 2006.260.07:49:23.37#ibcon#about to read 6, iclass 3, count 2 2006.260.07:49:23.37#ibcon#read 6, iclass 3, count 2 2006.260.07:49:23.37#ibcon#end of sib2, iclass 3, count 2 2006.260.07:49:23.37#ibcon#*after write, iclass 3, count 2 2006.260.07:49:23.37#ibcon#*before return 0, iclass 3, count 2 2006.260.07:49:23.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:23.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:23.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:49:23.37#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:23.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:23.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:23.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:23.50#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:49:23.50#ibcon#first serial, iclass 3, count 0 2006.260.07:49:23.50#ibcon#enter sib2, iclass 3, count 0 2006.260.07:49:23.50#ibcon#flushed, iclass 3, count 0 2006.260.07:49:23.50#ibcon#about to write, iclass 3, count 0 2006.260.07:49:23.50#ibcon#wrote, iclass 3, count 0 2006.260.07:49:23.50#ibcon#about to read 3, iclass 3, count 0 2006.260.07:49:23.52#ibcon#read 3, iclass 3, count 0 2006.260.07:49:23.52#ibcon#about to read 4, iclass 3, count 0 2006.260.07:49:23.52#ibcon#read 4, iclass 3, count 0 2006.260.07:49:23.52#ibcon#about to read 5, iclass 3, count 0 2006.260.07:49:23.52#ibcon#read 5, iclass 3, count 0 2006.260.07:49:23.52#ibcon#about to read 6, iclass 3, count 0 2006.260.07:49:23.52#ibcon#read 6, iclass 3, count 0 2006.260.07:49:23.52#ibcon#end of sib2, iclass 3, count 0 2006.260.07:49:23.52#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:49:23.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:49:23.52#ibcon#[25=USB\r\n] 2006.260.07:49:23.52#ibcon#*before write, iclass 3, count 0 2006.260.07:49:23.52#ibcon#enter sib2, iclass 3, count 0 2006.260.07:49:23.52#ibcon#flushed, iclass 3, count 0 2006.260.07:49:23.52#ibcon#about to write, iclass 3, count 0 2006.260.07:49:23.52#ibcon#wrote, iclass 3, count 0 2006.260.07:49:23.52#ibcon#about to read 3, iclass 3, count 0 2006.260.07:49:23.55#ibcon#read 3, iclass 3, count 0 2006.260.07:49:23.55#ibcon#about to read 4, iclass 3, count 0 2006.260.07:49:23.55#ibcon#read 4, iclass 3, count 0 2006.260.07:49:23.55#ibcon#about to read 5, iclass 3, count 0 2006.260.07:49:23.55#ibcon#read 5, iclass 3, count 0 2006.260.07:49:23.55#ibcon#about to read 6, iclass 3, count 0 2006.260.07:49:23.55#ibcon#read 6, iclass 3, count 0 2006.260.07:49:23.55#ibcon#end of sib2, iclass 3, count 0 2006.260.07:49:23.55#ibcon#*after write, iclass 3, count 0 2006.260.07:49:23.55#ibcon#*before return 0, iclass 3, count 0 2006.260.07:49:23.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:23.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:23.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:49:23.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:49:23.55$vc4f8/valo=6,772.99 2006.260.07:49:23.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:49:23.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:49:23.55#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:23.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:23.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:23.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:23.55#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:49:23.55#ibcon#first serial, iclass 5, count 0 2006.260.07:49:23.55#ibcon#enter sib2, iclass 5, count 0 2006.260.07:49:23.55#ibcon#flushed, iclass 5, count 0 2006.260.07:49:23.55#ibcon#about to write, iclass 5, count 0 2006.260.07:49:23.55#ibcon#wrote, iclass 5, count 0 2006.260.07:49:23.55#ibcon#about to read 3, iclass 5, count 0 2006.260.07:49:23.57#ibcon#read 3, iclass 5, count 0 2006.260.07:49:23.57#ibcon#about to read 4, iclass 5, count 0 2006.260.07:49:23.57#ibcon#read 4, iclass 5, count 0 2006.260.07:49:23.57#ibcon#about to read 5, iclass 5, count 0 2006.260.07:49:23.57#ibcon#read 5, iclass 5, count 0 2006.260.07:49:23.57#ibcon#about to read 6, iclass 5, count 0 2006.260.07:49:23.57#ibcon#read 6, iclass 5, count 0 2006.260.07:49:23.57#ibcon#end of sib2, iclass 5, count 0 2006.260.07:49:23.57#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:49:23.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:49:23.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:49:23.57#ibcon#*before write, iclass 5, count 0 2006.260.07:49:23.57#ibcon#enter sib2, iclass 5, count 0 2006.260.07:49:23.57#ibcon#flushed, iclass 5, count 0 2006.260.07:49:23.57#ibcon#about to write, iclass 5, count 0 2006.260.07:49:23.57#ibcon#wrote, iclass 5, count 0 2006.260.07:49:23.57#ibcon#about to read 3, iclass 5, count 0 2006.260.07:49:23.61#ibcon#read 3, iclass 5, count 0 2006.260.07:49:23.61#ibcon#about to read 4, iclass 5, count 0 2006.260.07:49:23.61#ibcon#read 4, iclass 5, count 0 2006.260.07:49:23.61#ibcon#about to read 5, iclass 5, count 0 2006.260.07:49:23.61#ibcon#read 5, iclass 5, count 0 2006.260.07:49:23.61#ibcon#about to read 6, iclass 5, count 0 2006.260.07:49:23.61#ibcon#read 6, iclass 5, count 0 2006.260.07:49:23.61#ibcon#end of sib2, iclass 5, count 0 2006.260.07:49:23.61#ibcon#*after write, iclass 5, count 0 2006.260.07:49:23.61#ibcon#*before return 0, iclass 5, count 0 2006.260.07:49:23.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:23.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:23.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:49:23.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:49:23.61$vc4f8/va=6,6 2006.260.07:49:23.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.07:49:23.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.07:49:23.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:23.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:23.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:23.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:23.67#ibcon#enter wrdev, iclass 7, count 2 2006.260.07:49:23.67#ibcon#first serial, iclass 7, count 2 2006.260.07:49:23.67#ibcon#enter sib2, iclass 7, count 2 2006.260.07:49:23.67#ibcon#flushed, iclass 7, count 2 2006.260.07:49:23.67#ibcon#about to write, iclass 7, count 2 2006.260.07:49:23.67#ibcon#wrote, iclass 7, count 2 2006.260.07:49:23.67#ibcon#about to read 3, iclass 7, count 2 2006.260.07:49:23.69#ibcon#read 3, iclass 7, count 2 2006.260.07:49:23.69#ibcon#about to read 4, iclass 7, count 2 2006.260.07:49:23.69#ibcon#read 4, iclass 7, count 2 2006.260.07:49:23.69#ibcon#about to read 5, iclass 7, count 2 2006.260.07:49:23.69#ibcon#read 5, iclass 7, count 2 2006.260.07:49:23.69#ibcon#about to read 6, iclass 7, count 2 2006.260.07:49:23.69#ibcon#read 6, iclass 7, count 2 2006.260.07:49:23.69#ibcon#end of sib2, iclass 7, count 2 2006.260.07:49:23.69#ibcon#*mode == 0, iclass 7, count 2 2006.260.07:49:23.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.07:49:23.69#ibcon#[25=AT06-06\r\n] 2006.260.07:49:23.69#ibcon#*before write, iclass 7, count 2 2006.260.07:49:23.69#ibcon#enter sib2, iclass 7, count 2 2006.260.07:49:23.69#ibcon#flushed, iclass 7, count 2 2006.260.07:49:23.69#ibcon#about to write, iclass 7, count 2 2006.260.07:49:23.69#ibcon#wrote, iclass 7, count 2 2006.260.07:49:23.69#ibcon#about to read 3, iclass 7, count 2 2006.260.07:49:23.72#ibcon#read 3, iclass 7, count 2 2006.260.07:49:23.72#ibcon#about to read 4, iclass 7, count 2 2006.260.07:49:23.72#ibcon#read 4, iclass 7, count 2 2006.260.07:49:23.72#ibcon#about to read 5, iclass 7, count 2 2006.260.07:49:23.72#ibcon#read 5, iclass 7, count 2 2006.260.07:49:23.72#ibcon#about to read 6, iclass 7, count 2 2006.260.07:49:23.72#ibcon#read 6, iclass 7, count 2 2006.260.07:49:23.72#ibcon#end of sib2, iclass 7, count 2 2006.260.07:49:23.72#ibcon#*after write, iclass 7, count 2 2006.260.07:49:23.72#ibcon#*before return 0, iclass 7, count 2 2006.260.07:49:23.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:23.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:23.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.07:49:23.72#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:23.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:49:23.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:49:23.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:49:23.84#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:49:23.84#ibcon#first serial, iclass 7, count 0 2006.260.07:49:23.84#ibcon#enter sib2, iclass 7, count 0 2006.260.07:49:23.84#ibcon#flushed, iclass 7, count 0 2006.260.07:49:23.84#ibcon#about to write, iclass 7, count 0 2006.260.07:49:23.84#ibcon#wrote, iclass 7, count 0 2006.260.07:49:23.84#ibcon#about to read 3, iclass 7, count 0 2006.260.07:49:23.86#ibcon#read 3, iclass 7, count 0 2006.260.07:49:23.86#ibcon#about to read 4, iclass 7, count 0 2006.260.07:49:23.86#ibcon#read 4, iclass 7, count 0 2006.260.07:49:23.86#ibcon#about to read 5, iclass 7, count 0 2006.260.07:49:23.86#ibcon#read 5, iclass 7, count 0 2006.260.07:49:23.86#ibcon#about to read 6, iclass 7, count 0 2006.260.07:49:23.86#ibcon#read 6, iclass 7, count 0 2006.260.07:49:23.86#ibcon#end of sib2, iclass 7, count 0 2006.260.07:49:23.86#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:49:23.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:49:23.86#ibcon#[25=USB\r\n] 2006.260.07:49:23.86#ibcon#*before write, iclass 7, count 0 2006.260.07:49:23.86#ibcon#enter sib2, iclass 7, count 0 2006.260.07:49:23.86#ibcon#flushed, iclass 7, count 0 2006.260.07:49:23.86#ibcon#about to write, iclass 7, count 0 2006.260.07:49:23.86#ibcon#wrote, iclass 7, count 0 2006.260.07:49:23.86#ibcon#about to read 3, iclass 7, count 0 2006.260.07:49:23.89#ibcon#read 3, iclass 7, count 0 2006.260.07:49:23.89#ibcon#about to read 4, iclass 7, count 0 2006.260.07:49:23.89#ibcon#read 4, iclass 7, count 0 2006.260.07:49:23.89#ibcon#about to read 5, iclass 7, count 0 2006.260.07:49:23.89#ibcon#read 5, iclass 7, count 0 2006.260.07:49:23.89#ibcon#about to read 6, iclass 7, count 0 2006.260.07:49:23.89#ibcon#read 6, iclass 7, count 0 2006.260.07:49:23.89#ibcon#end of sib2, iclass 7, count 0 2006.260.07:49:23.89#ibcon#*after write, iclass 7, count 0 2006.260.07:49:23.89#ibcon#*before return 0, iclass 7, count 0 2006.260.07:49:23.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:49:23.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:49:23.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:49:23.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:49:23.89$vc4f8/valo=7,832.99 2006.260.07:49:23.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.07:49:23.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.07:49:23.89#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:23.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:49:23.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:49:23.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:49:23.89#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:49:23.89#ibcon#first serial, iclass 11, count 0 2006.260.07:49:23.89#ibcon#enter sib2, iclass 11, count 0 2006.260.07:49:23.89#ibcon#flushed, iclass 11, count 0 2006.260.07:49:23.89#ibcon#about to write, iclass 11, count 0 2006.260.07:49:23.89#ibcon#wrote, iclass 11, count 0 2006.260.07:49:23.89#ibcon#about to read 3, iclass 11, count 0 2006.260.07:49:23.91#ibcon#read 3, iclass 11, count 0 2006.260.07:49:23.91#ibcon#about to read 4, iclass 11, count 0 2006.260.07:49:23.91#ibcon#read 4, iclass 11, count 0 2006.260.07:49:23.91#ibcon#about to read 5, iclass 11, count 0 2006.260.07:49:23.91#ibcon#read 5, iclass 11, count 0 2006.260.07:49:23.91#ibcon#about to read 6, iclass 11, count 0 2006.260.07:49:23.91#ibcon#read 6, iclass 11, count 0 2006.260.07:49:23.91#ibcon#end of sib2, iclass 11, count 0 2006.260.07:49:23.91#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:49:23.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:49:23.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:49:23.91#ibcon#*before write, iclass 11, count 0 2006.260.07:49:23.91#ibcon#enter sib2, iclass 11, count 0 2006.260.07:49:23.91#ibcon#flushed, iclass 11, count 0 2006.260.07:49:23.91#ibcon#about to write, iclass 11, count 0 2006.260.07:49:23.91#ibcon#wrote, iclass 11, count 0 2006.260.07:49:23.91#ibcon#about to read 3, iclass 11, count 0 2006.260.07:49:23.95#ibcon#read 3, iclass 11, count 0 2006.260.07:49:23.95#ibcon#about to read 4, iclass 11, count 0 2006.260.07:49:23.95#ibcon#read 4, iclass 11, count 0 2006.260.07:49:23.95#ibcon#about to read 5, iclass 11, count 0 2006.260.07:49:23.95#ibcon#read 5, iclass 11, count 0 2006.260.07:49:23.95#ibcon#about to read 6, iclass 11, count 0 2006.260.07:49:23.95#ibcon#read 6, iclass 11, count 0 2006.260.07:49:23.95#ibcon#end of sib2, iclass 11, count 0 2006.260.07:49:23.95#ibcon#*after write, iclass 11, count 0 2006.260.07:49:23.95#ibcon#*before return 0, iclass 11, count 0 2006.260.07:49:23.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:49:23.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:49:23.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:49:23.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:49:23.95$vc4f8/va=7,6 2006.260.07:49:23.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.07:49:23.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.07:49:23.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:23.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:49:24.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:49:24.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:49:24.01#ibcon#enter wrdev, iclass 13, count 2 2006.260.07:49:24.01#ibcon#first serial, iclass 13, count 2 2006.260.07:49:24.01#ibcon#enter sib2, iclass 13, count 2 2006.260.07:49:24.01#ibcon#flushed, iclass 13, count 2 2006.260.07:49:24.01#ibcon#about to write, iclass 13, count 2 2006.260.07:49:24.01#ibcon#wrote, iclass 13, count 2 2006.260.07:49:24.01#ibcon#about to read 3, iclass 13, count 2 2006.260.07:49:24.03#ibcon#read 3, iclass 13, count 2 2006.260.07:49:24.03#ibcon#about to read 4, iclass 13, count 2 2006.260.07:49:24.03#ibcon#read 4, iclass 13, count 2 2006.260.07:49:24.03#ibcon#about to read 5, iclass 13, count 2 2006.260.07:49:24.03#ibcon#read 5, iclass 13, count 2 2006.260.07:49:24.03#ibcon#about to read 6, iclass 13, count 2 2006.260.07:49:24.03#ibcon#read 6, iclass 13, count 2 2006.260.07:49:24.03#ibcon#end of sib2, iclass 13, count 2 2006.260.07:49:24.03#ibcon#*mode == 0, iclass 13, count 2 2006.260.07:49:24.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.07:49:24.03#ibcon#[25=AT07-06\r\n] 2006.260.07:49:24.03#ibcon#*before write, iclass 13, count 2 2006.260.07:49:24.03#ibcon#enter sib2, iclass 13, count 2 2006.260.07:49:24.03#ibcon#flushed, iclass 13, count 2 2006.260.07:49:24.03#ibcon#about to write, iclass 13, count 2 2006.260.07:49:24.03#ibcon#wrote, iclass 13, count 2 2006.260.07:49:24.03#ibcon#about to read 3, iclass 13, count 2 2006.260.07:49:24.06#ibcon#read 3, iclass 13, count 2 2006.260.07:49:24.06#ibcon#about to read 4, iclass 13, count 2 2006.260.07:49:24.06#ibcon#read 4, iclass 13, count 2 2006.260.07:49:24.06#ibcon#about to read 5, iclass 13, count 2 2006.260.07:49:24.06#ibcon#read 5, iclass 13, count 2 2006.260.07:49:24.06#ibcon#about to read 6, iclass 13, count 2 2006.260.07:49:24.06#ibcon#read 6, iclass 13, count 2 2006.260.07:49:24.06#ibcon#end of sib2, iclass 13, count 2 2006.260.07:49:24.06#ibcon#*after write, iclass 13, count 2 2006.260.07:49:24.06#ibcon#*before return 0, iclass 13, count 2 2006.260.07:49:24.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:49:24.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:49:24.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.07:49:24.06#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:24.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:49:24.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:49:24.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:49:24.18#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:49:24.18#ibcon#first serial, iclass 13, count 0 2006.260.07:49:24.18#ibcon#enter sib2, iclass 13, count 0 2006.260.07:49:24.18#ibcon#flushed, iclass 13, count 0 2006.260.07:49:24.18#ibcon#about to write, iclass 13, count 0 2006.260.07:49:24.18#ibcon#wrote, iclass 13, count 0 2006.260.07:49:24.18#ibcon#about to read 3, iclass 13, count 0 2006.260.07:49:24.21#ibcon#read 3, iclass 13, count 0 2006.260.07:49:24.21#ibcon#about to read 4, iclass 13, count 0 2006.260.07:49:24.21#ibcon#read 4, iclass 13, count 0 2006.260.07:49:24.21#ibcon#about to read 5, iclass 13, count 0 2006.260.07:49:24.21#ibcon#read 5, iclass 13, count 0 2006.260.07:49:24.21#ibcon#about to read 6, iclass 13, count 0 2006.260.07:49:24.21#ibcon#read 6, iclass 13, count 0 2006.260.07:49:24.21#ibcon#end of sib2, iclass 13, count 0 2006.260.07:49:24.21#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:49:24.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:49:24.21#ibcon#[25=USB\r\n] 2006.260.07:49:24.21#ibcon#*before write, iclass 13, count 0 2006.260.07:49:24.21#ibcon#enter sib2, iclass 13, count 0 2006.260.07:49:24.21#ibcon#flushed, iclass 13, count 0 2006.260.07:49:24.21#ibcon#about to write, iclass 13, count 0 2006.260.07:49:24.21#ibcon#wrote, iclass 13, count 0 2006.260.07:49:24.21#ibcon#about to read 3, iclass 13, count 0 2006.260.07:49:24.25#ibcon#read 3, iclass 13, count 0 2006.260.07:49:24.25#ibcon#about to read 4, iclass 13, count 0 2006.260.07:49:24.25#ibcon#read 4, iclass 13, count 0 2006.260.07:49:24.25#ibcon#about to read 5, iclass 13, count 0 2006.260.07:49:24.25#ibcon#read 5, iclass 13, count 0 2006.260.07:49:24.25#ibcon#about to read 6, iclass 13, count 0 2006.260.07:49:24.25#ibcon#read 6, iclass 13, count 0 2006.260.07:49:24.25#ibcon#end of sib2, iclass 13, count 0 2006.260.07:49:24.25#ibcon#*after write, iclass 13, count 0 2006.260.07:49:24.25#ibcon#*before return 0, iclass 13, count 0 2006.260.07:49:24.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:49:24.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:49:24.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:49:24.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:49:24.25$vc4f8/valo=8,852.99 2006.260.07:49:24.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:49:24.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:49:24.25#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:24.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:49:24.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:49:24.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:49:24.25#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:49:24.25#ibcon#first serial, iclass 15, count 0 2006.260.07:49:24.25#ibcon#enter sib2, iclass 15, count 0 2006.260.07:49:24.25#ibcon#flushed, iclass 15, count 0 2006.260.07:49:24.25#ibcon#about to write, iclass 15, count 0 2006.260.07:49:24.25#ibcon#wrote, iclass 15, count 0 2006.260.07:49:24.25#ibcon#about to read 3, iclass 15, count 0 2006.260.07:49:24.27#ibcon#read 3, iclass 15, count 0 2006.260.07:49:24.27#ibcon#about to read 4, iclass 15, count 0 2006.260.07:49:24.27#ibcon#read 4, iclass 15, count 0 2006.260.07:49:24.27#ibcon#about to read 5, iclass 15, count 0 2006.260.07:49:24.27#ibcon#read 5, iclass 15, count 0 2006.260.07:49:24.27#ibcon#about to read 6, iclass 15, count 0 2006.260.07:49:24.27#ibcon#read 6, iclass 15, count 0 2006.260.07:49:24.27#ibcon#end of sib2, iclass 15, count 0 2006.260.07:49:24.27#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:49:24.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:49:24.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:49:24.27#ibcon#*before write, iclass 15, count 0 2006.260.07:49:24.27#ibcon#enter sib2, iclass 15, count 0 2006.260.07:49:24.27#ibcon#flushed, iclass 15, count 0 2006.260.07:49:24.27#ibcon#about to write, iclass 15, count 0 2006.260.07:49:24.27#ibcon#wrote, iclass 15, count 0 2006.260.07:49:24.27#ibcon#about to read 3, iclass 15, count 0 2006.260.07:49:24.31#ibcon#read 3, iclass 15, count 0 2006.260.07:49:24.31#ibcon#about to read 4, iclass 15, count 0 2006.260.07:49:24.31#ibcon#read 4, iclass 15, count 0 2006.260.07:49:24.31#ibcon#about to read 5, iclass 15, count 0 2006.260.07:49:24.31#ibcon#read 5, iclass 15, count 0 2006.260.07:49:24.31#ibcon#about to read 6, iclass 15, count 0 2006.260.07:49:24.31#ibcon#read 6, iclass 15, count 0 2006.260.07:49:24.31#ibcon#end of sib2, iclass 15, count 0 2006.260.07:49:24.31#ibcon#*after write, iclass 15, count 0 2006.260.07:49:24.31#ibcon#*before return 0, iclass 15, count 0 2006.260.07:49:24.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:49:24.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:49:24.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:49:24.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:49:24.31$vc4f8/va=8,6 2006.260.07:49:24.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:49:24.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:49:24.31#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:24.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:49:24.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:49:24.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:49:24.37#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:49:24.37#ibcon#first serial, iclass 17, count 2 2006.260.07:49:24.37#ibcon#enter sib2, iclass 17, count 2 2006.260.07:49:24.37#ibcon#flushed, iclass 17, count 2 2006.260.07:49:24.37#ibcon#about to write, iclass 17, count 2 2006.260.07:49:24.37#ibcon#wrote, iclass 17, count 2 2006.260.07:49:24.37#ibcon#about to read 3, iclass 17, count 2 2006.260.07:49:24.39#ibcon#read 3, iclass 17, count 2 2006.260.07:49:24.39#ibcon#about to read 4, iclass 17, count 2 2006.260.07:49:24.39#ibcon#read 4, iclass 17, count 2 2006.260.07:49:24.39#ibcon#about to read 5, iclass 17, count 2 2006.260.07:49:24.39#ibcon#read 5, iclass 17, count 2 2006.260.07:49:24.39#ibcon#about to read 6, iclass 17, count 2 2006.260.07:49:24.39#ibcon#read 6, iclass 17, count 2 2006.260.07:49:24.39#ibcon#end of sib2, iclass 17, count 2 2006.260.07:49:24.39#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:49:24.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:49:24.39#ibcon#[25=AT08-06\r\n] 2006.260.07:49:24.39#ibcon#*before write, iclass 17, count 2 2006.260.07:49:24.39#ibcon#enter sib2, iclass 17, count 2 2006.260.07:49:24.39#ibcon#flushed, iclass 17, count 2 2006.260.07:49:24.39#ibcon#about to write, iclass 17, count 2 2006.260.07:49:24.39#ibcon#wrote, iclass 17, count 2 2006.260.07:49:24.39#ibcon#about to read 3, iclass 17, count 2 2006.260.07:49:24.42#ibcon#read 3, iclass 17, count 2 2006.260.07:49:24.42#ibcon#about to read 4, iclass 17, count 2 2006.260.07:49:24.42#ibcon#read 4, iclass 17, count 2 2006.260.07:49:24.42#ibcon#about to read 5, iclass 17, count 2 2006.260.07:49:24.42#ibcon#read 5, iclass 17, count 2 2006.260.07:49:24.42#ibcon#about to read 6, iclass 17, count 2 2006.260.07:49:24.42#ibcon#read 6, iclass 17, count 2 2006.260.07:49:24.42#ibcon#end of sib2, iclass 17, count 2 2006.260.07:49:24.42#ibcon#*after write, iclass 17, count 2 2006.260.07:49:24.42#ibcon#*before return 0, iclass 17, count 2 2006.260.07:49:24.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:49:24.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:49:24.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:49:24.42#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:24.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:49:24.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:49:24.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:49:24.54#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:49:24.54#ibcon#first serial, iclass 17, count 0 2006.260.07:49:24.54#ibcon#enter sib2, iclass 17, count 0 2006.260.07:49:24.54#ibcon#flushed, iclass 17, count 0 2006.260.07:49:24.54#ibcon#about to write, iclass 17, count 0 2006.260.07:49:24.54#ibcon#wrote, iclass 17, count 0 2006.260.07:49:24.54#ibcon#about to read 3, iclass 17, count 0 2006.260.07:49:24.56#ibcon#read 3, iclass 17, count 0 2006.260.07:49:24.56#ibcon#about to read 4, iclass 17, count 0 2006.260.07:49:24.56#ibcon#read 4, iclass 17, count 0 2006.260.07:49:24.56#ibcon#about to read 5, iclass 17, count 0 2006.260.07:49:24.56#ibcon#read 5, iclass 17, count 0 2006.260.07:49:24.56#ibcon#about to read 6, iclass 17, count 0 2006.260.07:49:24.56#ibcon#read 6, iclass 17, count 0 2006.260.07:49:24.56#ibcon#end of sib2, iclass 17, count 0 2006.260.07:49:24.56#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:49:24.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:49:24.56#ibcon#[25=USB\r\n] 2006.260.07:49:24.56#ibcon#*before write, iclass 17, count 0 2006.260.07:49:24.56#ibcon#enter sib2, iclass 17, count 0 2006.260.07:49:24.56#ibcon#flushed, iclass 17, count 0 2006.260.07:49:24.56#ibcon#about to write, iclass 17, count 0 2006.260.07:49:24.56#ibcon#wrote, iclass 17, count 0 2006.260.07:49:24.56#ibcon#about to read 3, iclass 17, count 0 2006.260.07:49:24.59#ibcon#read 3, iclass 17, count 0 2006.260.07:49:24.59#ibcon#about to read 4, iclass 17, count 0 2006.260.07:49:24.59#ibcon#read 4, iclass 17, count 0 2006.260.07:49:24.59#ibcon#about to read 5, iclass 17, count 0 2006.260.07:49:24.59#ibcon#read 5, iclass 17, count 0 2006.260.07:49:24.59#ibcon#about to read 6, iclass 17, count 0 2006.260.07:49:24.59#ibcon#read 6, iclass 17, count 0 2006.260.07:49:24.59#ibcon#end of sib2, iclass 17, count 0 2006.260.07:49:24.59#ibcon#*after write, iclass 17, count 0 2006.260.07:49:24.59#ibcon#*before return 0, iclass 17, count 0 2006.260.07:49:24.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:49:24.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:49:24.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:49:24.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:49:24.59$vc4f8/vblo=1,632.99 2006.260.07:49:24.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:49:24.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:49:24.59#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:24.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:49:24.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:49:24.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:49:24.59#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:49:24.59#ibcon#first serial, iclass 19, count 0 2006.260.07:49:24.59#ibcon#enter sib2, iclass 19, count 0 2006.260.07:49:24.59#ibcon#flushed, iclass 19, count 0 2006.260.07:49:24.59#ibcon#about to write, iclass 19, count 0 2006.260.07:49:24.59#ibcon#wrote, iclass 19, count 0 2006.260.07:49:24.59#ibcon#about to read 3, iclass 19, count 0 2006.260.07:49:24.61#ibcon#read 3, iclass 19, count 0 2006.260.07:49:24.61#ibcon#about to read 4, iclass 19, count 0 2006.260.07:49:24.61#ibcon#read 4, iclass 19, count 0 2006.260.07:49:24.61#ibcon#about to read 5, iclass 19, count 0 2006.260.07:49:24.61#ibcon#read 5, iclass 19, count 0 2006.260.07:49:24.61#ibcon#about to read 6, iclass 19, count 0 2006.260.07:49:24.61#ibcon#read 6, iclass 19, count 0 2006.260.07:49:24.61#ibcon#end of sib2, iclass 19, count 0 2006.260.07:49:24.61#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:49:24.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:49:24.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:49:24.61#ibcon#*before write, iclass 19, count 0 2006.260.07:49:24.61#ibcon#enter sib2, iclass 19, count 0 2006.260.07:49:24.61#ibcon#flushed, iclass 19, count 0 2006.260.07:49:24.61#ibcon#about to write, iclass 19, count 0 2006.260.07:49:24.61#ibcon#wrote, iclass 19, count 0 2006.260.07:49:24.61#ibcon#about to read 3, iclass 19, count 0 2006.260.07:49:24.65#ibcon#read 3, iclass 19, count 0 2006.260.07:49:24.65#ibcon#about to read 4, iclass 19, count 0 2006.260.07:49:24.65#ibcon#read 4, iclass 19, count 0 2006.260.07:49:24.65#ibcon#about to read 5, iclass 19, count 0 2006.260.07:49:24.65#ibcon#read 5, iclass 19, count 0 2006.260.07:49:24.65#ibcon#about to read 6, iclass 19, count 0 2006.260.07:49:24.65#ibcon#read 6, iclass 19, count 0 2006.260.07:49:24.65#ibcon#end of sib2, iclass 19, count 0 2006.260.07:49:24.65#ibcon#*after write, iclass 19, count 0 2006.260.07:49:24.65#ibcon#*before return 0, iclass 19, count 0 2006.260.07:49:24.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:49:24.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:49:24.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:49:24.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:49:24.65$vc4f8/vb=1,4 2006.260.07:49:24.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:49:24.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:49:24.65#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:24.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:49:24.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:49:24.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:49:24.65#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:49:24.65#ibcon#first serial, iclass 21, count 2 2006.260.07:49:24.65#ibcon#enter sib2, iclass 21, count 2 2006.260.07:49:24.65#ibcon#flushed, iclass 21, count 2 2006.260.07:49:24.65#ibcon#about to write, iclass 21, count 2 2006.260.07:49:24.65#ibcon#wrote, iclass 21, count 2 2006.260.07:49:24.65#ibcon#about to read 3, iclass 21, count 2 2006.260.07:49:24.67#ibcon#read 3, iclass 21, count 2 2006.260.07:49:24.67#ibcon#about to read 4, iclass 21, count 2 2006.260.07:49:24.67#ibcon#read 4, iclass 21, count 2 2006.260.07:49:24.67#ibcon#about to read 5, iclass 21, count 2 2006.260.07:49:24.67#ibcon#read 5, iclass 21, count 2 2006.260.07:49:24.67#ibcon#about to read 6, iclass 21, count 2 2006.260.07:49:24.67#ibcon#read 6, iclass 21, count 2 2006.260.07:49:24.67#ibcon#end of sib2, iclass 21, count 2 2006.260.07:49:24.67#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:49:24.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:49:24.67#ibcon#[27=AT01-04\r\n] 2006.260.07:49:24.67#ibcon#*before write, iclass 21, count 2 2006.260.07:49:24.67#ibcon#enter sib2, iclass 21, count 2 2006.260.07:49:24.67#ibcon#flushed, iclass 21, count 2 2006.260.07:49:24.67#ibcon#about to write, iclass 21, count 2 2006.260.07:49:24.67#ibcon#wrote, iclass 21, count 2 2006.260.07:49:24.67#ibcon#about to read 3, iclass 21, count 2 2006.260.07:49:24.70#ibcon#read 3, iclass 21, count 2 2006.260.07:49:24.70#ibcon#about to read 4, iclass 21, count 2 2006.260.07:49:24.70#ibcon#read 4, iclass 21, count 2 2006.260.07:49:24.70#ibcon#about to read 5, iclass 21, count 2 2006.260.07:49:24.70#ibcon#read 5, iclass 21, count 2 2006.260.07:49:24.70#ibcon#about to read 6, iclass 21, count 2 2006.260.07:49:24.70#ibcon#read 6, iclass 21, count 2 2006.260.07:49:24.70#ibcon#end of sib2, iclass 21, count 2 2006.260.07:49:24.70#ibcon#*after write, iclass 21, count 2 2006.260.07:49:24.70#ibcon#*before return 0, iclass 21, count 2 2006.260.07:49:24.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:49:24.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:49:24.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:49:24.70#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:24.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:49:24.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:49:24.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:49:24.82#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:49:24.82#ibcon#first serial, iclass 21, count 0 2006.260.07:49:24.82#ibcon#enter sib2, iclass 21, count 0 2006.260.07:49:24.82#ibcon#flushed, iclass 21, count 0 2006.260.07:49:24.82#ibcon#about to write, iclass 21, count 0 2006.260.07:49:24.82#ibcon#wrote, iclass 21, count 0 2006.260.07:49:24.82#ibcon#about to read 3, iclass 21, count 0 2006.260.07:49:24.84#ibcon#read 3, iclass 21, count 0 2006.260.07:49:24.84#ibcon#about to read 4, iclass 21, count 0 2006.260.07:49:24.84#ibcon#read 4, iclass 21, count 0 2006.260.07:49:24.84#ibcon#about to read 5, iclass 21, count 0 2006.260.07:49:24.84#ibcon#read 5, iclass 21, count 0 2006.260.07:49:24.84#ibcon#about to read 6, iclass 21, count 0 2006.260.07:49:24.84#ibcon#read 6, iclass 21, count 0 2006.260.07:49:24.84#ibcon#end of sib2, iclass 21, count 0 2006.260.07:49:24.84#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:49:24.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:49:24.84#ibcon#[27=USB\r\n] 2006.260.07:49:24.84#ibcon#*before write, iclass 21, count 0 2006.260.07:49:24.84#ibcon#enter sib2, iclass 21, count 0 2006.260.07:49:24.84#ibcon#flushed, iclass 21, count 0 2006.260.07:49:24.84#ibcon#about to write, iclass 21, count 0 2006.260.07:49:24.84#ibcon#wrote, iclass 21, count 0 2006.260.07:49:24.84#ibcon#about to read 3, iclass 21, count 0 2006.260.07:49:24.87#ibcon#read 3, iclass 21, count 0 2006.260.07:49:24.87#ibcon#about to read 4, iclass 21, count 0 2006.260.07:49:24.87#ibcon#read 4, iclass 21, count 0 2006.260.07:49:24.87#ibcon#about to read 5, iclass 21, count 0 2006.260.07:49:24.87#ibcon#read 5, iclass 21, count 0 2006.260.07:49:24.87#ibcon#about to read 6, iclass 21, count 0 2006.260.07:49:24.87#ibcon#read 6, iclass 21, count 0 2006.260.07:49:24.87#ibcon#end of sib2, iclass 21, count 0 2006.260.07:49:24.87#ibcon#*after write, iclass 21, count 0 2006.260.07:49:24.87#ibcon#*before return 0, iclass 21, count 0 2006.260.07:49:24.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:49:24.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:49:24.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:49:24.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:49:24.87$vc4f8/vblo=2,640.99 2006.260.07:49:24.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:49:24.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:49:24.87#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:24.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:24.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:24.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:24.87#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:49:24.87#ibcon#first serial, iclass 23, count 0 2006.260.07:49:24.87#ibcon#enter sib2, iclass 23, count 0 2006.260.07:49:24.87#ibcon#flushed, iclass 23, count 0 2006.260.07:49:24.87#ibcon#about to write, iclass 23, count 0 2006.260.07:49:24.87#ibcon#wrote, iclass 23, count 0 2006.260.07:49:24.87#ibcon#about to read 3, iclass 23, count 0 2006.260.07:49:24.89#ibcon#read 3, iclass 23, count 0 2006.260.07:49:24.89#ibcon#about to read 4, iclass 23, count 0 2006.260.07:49:24.89#ibcon#read 4, iclass 23, count 0 2006.260.07:49:24.89#ibcon#about to read 5, iclass 23, count 0 2006.260.07:49:24.89#ibcon#read 5, iclass 23, count 0 2006.260.07:49:24.89#ibcon#about to read 6, iclass 23, count 0 2006.260.07:49:24.89#ibcon#read 6, iclass 23, count 0 2006.260.07:49:24.89#ibcon#end of sib2, iclass 23, count 0 2006.260.07:49:24.89#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:49:24.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:49:24.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:49:24.89#ibcon#*before write, iclass 23, count 0 2006.260.07:49:24.89#ibcon#enter sib2, iclass 23, count 0 2006.260.07:49:24.89#ibcon#flushed, iclass 23, count 0 2006.260.07:49:24.89#ibcon#about to write, iclass 23, count 0 2006.260.07:49:24.89#ibcon#wrote, iclass 23, count 0 2006.260.07:49:24.89#ibcon#about to read 3, iclass 23, count 0 2006.260.07:49:24.93#ibcon#read 3, iclass 23, count 0 2006.260.07:49:24.93#ibcon#about to read 4, iclass 23, count 0 2006.260.07:49:24.93#ibcon#read 4, iclass 23, count 0 2006.260.07:49:24.93#ibcon#about to read 5, iclass 23, count 0 2006.260.07:49:24.93#ibcon#read 5, iclass 23, count 0 2006.260.07:49:24.93#ibcon#about to read 6, iclass 23, count 0 2006.260.07:49:24.93#ibcon#read 6, iclass 23, count 0 2006.260.07:49:24.93#ibcon#end of sib2, iclass 23, count 0 2006.260.07:49:24.93#ibcon#*after write, iclass 23, count 0 2006.260.07:49:24.93#ibcon#*before return 0, iclass 23, count 0 2006.260.07:49:24.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:24.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:49:24.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:49:24.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:49:24.93$vc4f8/vb=2,5 2006.260.07:49:24.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:49:24.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:49:24.93#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:24.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:24.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:24.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:24.99#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:49:24.99#ibcon#first serial, iclass 25, count 2 2006.260.07:49:24.99#ibcon#enter sib2, iclass 25, count 2 2006.260.07:49:24.99#ibcon#flushed, iclass 25, count 2 2006.260.07:49:24.99#ibcon#about to write, iclass 25, count 2 2006.260.07:49:24.99#ibcon#wrote, iclass 25, count 2 2006.260.07:49:24.99#ibcon#about to read 3, iclass 25, count 2 2006.260.07:49:25.01#ibcon#read 3, iclass 25, count 2 2006.260.07:49:25.01#ibcon#about to read 4, iclass 25, count 2 2006.260.07:49:25.01#ibcon#read 4, iclass 25, count 2 2006.260.07:49:25.01#ibcon#about to read 5, iclass 25, count 2 2006.260.07:49:25.01#ibcon#read 5, iclass 25, count 2 2006.260.07:49:25.01#ibcon#about to read 6, iclass 25, count 2 2006.260.07:49:25.01#ibcon#read 6, iclass 25, count 2 2006.260.07:49:25.01#ibcon#end of sib2, iclass 25, count 2 2006.260.07:49:25.01#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:49:25.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:49:25.01#ibcon#[27=AT02-05\r\n] 2006.260.07:49:25.01#ibcon#*before write, iclass 25, count 2 2006.260.07:49:25.01#ibcon#enter sib2, iclass 25, count 2 2006.260.07:49:25.01#ibcon#flushed, iclass 25, count 2 2006.260.07:49:25.01#ibcon#about to write, iclass 25, count 2 2006.260.07:49:25.01#ibcon#wrote, iclass 25, count 2 2006.260.07:49:25.01#ibcon#about to read 3, iclass 25, count 2 2006.260.07:49:25.05#ibcon#read 3, iclass 25, count 2 2006.260.07:49:25.05#ibcon#about to read 4, iclass 25, count 2 2006.260.07:49:25.05#ibcon#read 4, iclass 25, count 2 2006.260.07:49:25.05#ibcon#about to read 5, iclass 25, count 2 2006.260.07:49:25.05#ibcon#read 5, iclass 25, count 2 2006.260.07:49:25.05#ibcon#about to read 6, iclass 25, count 2 2006.260.07:49:25.05#ibcon#read 6, iclass 25, count 2 2006.260.07:49:25.05#ibcon#end of sib2, iclass 25, count 2 2006.260.07:49:25.05#ibcon#*after write, iclass 25, count 2 2006.260.07:49:25.05#ibcon#*before return 0, iclass 25, count 2 2006.260.07:49:25.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:25.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:49:25.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:49:25.05#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:25.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:25.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:25.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:25.17#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:49:25.17#ibcon#first serial, iclass 25, count 0 2006.260.07:49:25.17#ibcon#enter sib2, iclass 25, count 0 2006.260.07:49:25.17#ibcon#flushed, iclass 25, count 0 2006.260.07:49:25.17#ibcon#about to write, iclass 25, count 0 2006.260.07:49:25.17#ibcon#wrote, iclass 25, count 0 2006.260.07:49:25.17#ibcon#about to read 3, iclass 25, count 0 2006.260.07:49:25.19#ibcon#read 3, iclass 25, count 0 2006.260.07:49:25.19#ibcon#about to read 4, iclass 25, count 0 2006.260.07:49:25.19#ibcon#read 4, iclass 25, count 0 2006.260.07:49:25.19#ibcon#about to read 5, iclass 25, count 0 2006.260.07:49:25.19#ibcon#read 5, iclass 25, count 0 2006.260.07:49:25.19#ibcon#about to read 6, iclass 25, count 0 2006.260.07:49:25.19#ibcon#read 6, iclass 25, count 0 2006.260.07:49:25.19#ibcon#end of sib2, iclass 25, count 0 2006.260.07:49:25.19#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:49:25.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:49:25.19#ibcon#[27=USB\r\n] 2006.260.07:49:25.19#ibcon#*before write, iclass 25, count 0 2006.260.07:49:25.19#ibcon#enter sib2, iclass 25, count 0 2006.260.07:49:25.19#ibcon#flushed, iclass 25, count 0 2006.260.07:49:25.19#ibcon#about to write, iclass 25, count 0 2006.260.07:49:25.19#ibcon#wrote, iclass 25, count 0 2006.260.07:49:25.19#ibcon#about to read 3, iclass 25, count 0 2006.260.07:49:25.22#ibcon#read 3, iclass 25, count 0 2006.260.07:49:25.22#ibcon#about to read 4, iclass 25, count 0 2006.260.07:49:25.22#ibcon#read 4, iclass 25, count 0 2006.260.07:49:25.22#ibcon#about to read 5, iclass 25, count 0 2006.260.07:49:25.22#ibcon#read 5, iclass 25, count 0 2006.260.07:49:25.22#ibcon#about to read 6, iclass 25, count 0 2006.260.07:49:25.22#ibcon#read 6, iclass 25, count 0 2006.260.07:49:25.22#ibcon#end of sib2, iclass 25, count 0 2006.260.07:49:25.22#ibcon#*after write, iclass 25, count 0 2006.260.07:49:25.22#ibcon#*before return 0, iclass 25, count 0 2006.260.07:49:25.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:25.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:49:25.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:49:25.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:49:25.22$vc4f8/vblo=3,656.99 2006.260.07:49:25.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:49:25.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:49:25.22#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:25.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:25.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:25.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:25.22#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:49:25.22#ibcon#first serial, iclass 27, count 0 2006.260.07:49:25.22#ibcon#enter sib2, iclass 27, count 0 2006.260.07:49:25.22#ibcon#flushed, iclass 27, count 0 2006.260.07:49:25.22#ibcon#about to write, iclass 27, count 0 2006.260.07:49:25.22#ibcon#wrote, iclass 27, count 0 2006.260.07:49:25.22#ibcon#about to read 3, iclass 27, count 0 2006.260.07:49:25.24#ibcon#read 3, iclass 27, count 0 2006.260.07:49:25.24#ibcon#about to read 4, iclass 27, count 0 2006.260.07:49:25.24#ibcon#read 4, iclass 27, count 0 2006.260.07:49:25.24#ibcon#about to read 5, iclass 27, count 0 2006.260.07:49:25.24#ibcon#read 5, iclass 27, count 0 2006.260.07:49:25.24#ibcon#about to read 6, iclass 27, count 0 2006.260.07:49:25.24#ibcon#read 6, iclass 27, count 0 2006.260.07:49:25.24#ibcon#end of sib2, iclass 27, count 0 2006.260.07:49:25.24#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:49:25.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:49:25.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:49:25.24#ibcon#*before write, iclass 27, count 0 2006.260.07:49:25.24#ibcon#enter sib2, iclass 27, count 0 2006.260.07:49:25.24#ibcon#flushed, iclass 27, count 0 2006.260.07:49:25.24#ibcon#about to write, iclass 27, count 0 2006.260.07:49:25.24#ibcon#wrote, iclass 27, count 0 2006.260.07:49:25.24#ibcon#about to read 3, iclass 27, count 0 2006.260.07:49:25.28#ibcon#read 3, iclass 27, count 0 2006.260.07:49:25.28#ibcon#about to read 4, iclass 27, count 0 2006.260.07:49:25.28#ibcon#read 4, iclass 27, count 0 2006.260.07:49:25.28#ibcon#about to read 5, iclass 27, count 0 2006.260.07:49:25.28#ibcon#read 5, iclass 27, count 0 2006.260.07:49:25.28#ibcon#about to read 6, iclass 27, count 0 2006.260.07:49:25.28#ibcon#read 6, iclass 27, count 0 2006.260.07:49:25.28#ibcon#end of sib2, iclass 27, count 0 2006.260.07:49:25.28#ibcon#*after write, iclass 27, count 0 2006.260.07:49:25.28#ibcon#*before return 0, iclass 27, count 0 2006.260.07:49:25.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:25.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:49:25.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:49:25.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:49:25.28$vc4f8/vb=3,4 2006.260.07:49:25.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:49:25.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:49:25.28#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:25.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:25.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:25.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:25.34#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:49:25.34#ibcon#first serial, iclass 29, count 2 2006.260.07:49:25.34#ibcon#enter sib2, iclass 29, count 2 2006.260.07:49:25.34#ibcon#flushed, iclass 29, count 2 2006.260.07:49:25.34#ibcon#about to write, iclass 29, count 2 2006.260.07:49:25.34#ibcon#wrote, iclass 29, count 2 2006.260.07:49:25.34#ibcon#about to read 3, iclass 29, count 2 2006.260.07:49:25.36#ibcon#read 3, iclass 29, count 2 2006.260.07:49:25.36#ibcon#about to read 4, iclass 29, count 2 2006.260.07:49:25.36#ibcon#read 4, iclass 29, count 2 2006.260.07:49:25.36#ibcon#about to read 5, iclass 29, count 2 2006.260.07:49:25.36#ibcon#read 5, iclass 29, count 2 2006.260.07:49:25.36#ibcon#about to read 6, iclass 29, count 2 2006.260.07:49:25.36#ibcon#read 6, iclass 29, count 2 2006.260.07:49:25.36#ibcon#end of sib2, iclass 29, count 2 2006.260.07:49:25.36#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:49:25.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:49:25.36#ibcon#[27=AT03-04\r\n] 2006.260.07:49:25.36#ibcon#*before write, iclass 29, count 2 2006.260.07:49:25.36#ibcon#enter sib2, iclass 29, count 2 2006.260.07:49:25.36#ibcon#flushed, iclass 29, count 2 2006.260.07:49:25.36#ibcon#about to write, iclass 29, count 2 2006.260.07:49:25.36#ibcon#wrote, iclass 29, count 2 2006.260.07:49:25.36#ibcon#about to read 3, iclass 29, count 2 2006.260.07:49:25.39#ibcon#read 3, iclass 29, count 2 2006.260.07:49:25.39#ibcon#about to read 4, iclass 29, count 2 2006.260.07:49:25.39#ibcon#read 4, iclass 29, count 2 2006.260.07:49:25.39#ibcon#about to read 5, iclass 29, count 2 2006.260.07:49:25.39#ibcon#read 5, iclass 29, count 2 2006.260.07:49:25.39#ibcon#about to read 6, iclass 29, count 2 2006.260.07:49:25.39#ibcon#read 6, iclass 29, count 2 2006.260.07:49:25.39#ibcon#end of sib2, iclass 29, count 2 2006.260.07:49:25.39#ibcon#*after write, iclass 29, count 2 2006.260.07:49:25.39#ibcon#*before return 0, iclass 29, count 2 2006.260.07:49:25.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:25.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:49:25.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:49:25.39#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:25.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:25.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:25.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:25.51#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:49:25.51#ibcon#first serial, iclass 29, count 0 2006.260.07:49:25.51#ibcon#enter sib2, iclass 29, count 0 2006.260.07:49:25.51#ibcon#flushed, iclass 29, count 0 2006.260.07:49:25.51#ibcon#about to write, iclass 29, count 0 2006.260.07:49:25.51#ibcon#wrote, iclass 29, count 0 2006.260.07:49:25.51#ibcon#about to read 3, iclass 29, count 0 2006.260.07:49:25.53#ibcon#read 3, iclass 29, count 0 2006.260.07:49:25.53#ibcon#about to read 4, iclass 29, count 0 2006.260.07:49:25.53#ibcon#read 4, iclass 29, count 0 2006.260.07:49:25.53#ibcon#about to read 5, iclass 29, count 0 2006.260.07:49:25.53#ibcon#read 5, iclass 29, count 0 2006.260.07:49:25.53#ibcon#about to read 6, iclass 29, count 0 2006.260.07:49:25.53#ibcon#read 6, iclass 29, count 0 2006.260.07:49:25.53#ibcon#end of sib2, iclass 29, count 0 2006.260.07:49:25.53#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:49:25.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:49:25.53#ibcon#[27=USB\r\n] 2006.260.07:49:25.53#ibcon#*before write, iclass 29, count 0 2006.260.07:49:25.53#ibcon#enter sib2, iclass 29, count 0 2006.260.07:49:25.53#ibcon#flushed, iclass 29, count 0 2006.260.07:49:25.53#ibcon#about to write, iclass 29, count 0 2006.260.07:49:25.53#ibcon#wrote, iclass 29, count 0 2006.260.07:49:25.53#ibcon#about to read 3, iclass 29, count 0 2006.260.07:49:25.56#ibcon#read 3, iclass 29, count 0 2006.260.07:49:25.56#ibcon#about to read 4, iclass 29, count 0 2006.260.07:49:25.56#ibcon#read 4, iclass 29, count 0 2006.260.07:49:25.56#ibcon#about to read 5, iclass 29, count 0 2006.260.07:49:25.56#ibcon#read 5, iclass 29, count 0 2006.260.07:49:25.56#ibcon#about to read 6, iclass 29, count 0 2006.260.07:49:25.56#ibcon#read 6, iclass 29, count 0 2006.260.07:49:25.56#ibcon#end of sib2, iclass 29, count 0 2006.260.07:49:25.56#ibcon#*after write, iclass 29, count 0 2006.260.07:49:25.56#ibcon#*before return 0, iclass 29, count 0 2006.260.07:49:25.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:25.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:49:25.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:49:25.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:49:25.56$vc4f8/vblo=4,712.99 2006.260.07:49:25.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:49:25.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:49:25.56#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:25.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:25.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:25.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:25.56#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:49:25.56#ibcon#first serial, iclass 31, count 0 2006.260.07:49:25.56#ibcon#enter sib2, iclass 31, count 0 2006.260.07:49:25.56#ibcon#flushed, iclass 31, count 0 2006.260.07:49:25.56#ibcon#about to write, iclass 31, count 0 2006.260.07:49:25.56#ibcon#wrote, iclass 31, count 0 2006.260.07:49:25.56#ibcon#about to read 3, iclass 31, count 0 2006.260.07:49:25.58#ibcon#read 3, iclass 31, count 0 2006.260.07:49:25.58#ibcon#about to read 4, iclass 31, count 0 2006.260.07:49:25.58#ibcon#read 4, iclass 31, count 0 2006.260.07:49:25.58#ibcon#about to read 5, iclass 31, count 0 2006.260.07:49:25.58#ibcon#read 5, iclass 31, count 0 2006.260.07:49:25.58#ibcon#about to read 6, iclass 31, count 0 2006.260.07:49:25.58#ibcon#read 6, iclass 31, count 0 2006.260.07:49:25.58#ibcon#end of sib2, iclass 31, count 0 2006.260.07:49:25.58#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:49:25.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:49:25.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:49:25.58#ibcon#*before write, iclass 31, count 0 2006.260.07:49:25.58#ibcon#enter sib2, iclass 31, count 0 2006.260.07:49:25.58#ibcon#flushed, iclass 31, count 0 2006.260.07:49:25.58#ibcon#about to write, iclass 31, count 0 2006.260.07:49:25.58#ibcon#wrote, iclass 31, count 0 2006.260.07:49:25.58#ibcon#about to read 3, iclass 31, count 0 2006.260.07:49:25.62#ibcon#read 3, iclass 31, count 0 2006.260.07:49:25.62#ibcon#about to read 4, iclass 31, count 0 2006.260.07:49:25.62#ibcon#read 4, iclass 31, count 0 2006.260.07:49:25.62#ibcon#about to read 5, iclass 31, count 0 2006.260.07:49:25.62#ibcon#read 5, iclass 31, count 0 2006.260.07:49:25.62#ibcon#about to read 6, iclass 31, count 0 2006.260.07:49:25.62#ibcon#read 6, iclass 31, count 0 2006.260.07:49:25.62#ibcon#end of sib2, iclass 31, count 0 2006.260.07:49:25.62#ibcon#*after write, iclass 31, count 0 2006.260.07:49:25.62#ibcon#*before return 0, iclass 31, count 0 2006.260.07:49:25.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:25.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:49:25.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:49:25.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:49:25.62$vc4f8/vb=4,5 2006.260.07:49:25.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:49:25.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:49:25.62#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:25.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:25.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:25.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:25.68#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:49:25.68#ibcon#first serial, iclass 33, count 2 2006.260.07:49:25.68#ibcon#enter sib2, iclass 33, count 2 2006.260.07:49:25.68#ibcon#flushed, iclass 33, count 2 2006.260.07:49:25.68#ibcon#about to write, iclass 33, count 2 2006.260.07:49:25.68#ibcon#wrote, iclass 33, count 2 2006.260.07:49:25.68#ibcon#about to read 3, iclass 33, count 2 2006.260.07:49:25.70#ibcon#read 3, iclass 33, count 2 2006.260.07:49:25.70#ibcon#about to read 4, iclass 33, count 2 2006.260.07:49:25.70#ibcon#read 4, iclass 33, count 2 2006.260.07:49:25.70#ibcon#about to read 5, iclass 33, count 2 2006.260.07:49:25.70#ibcon#read 5, iclass 33, count 2 2006.260.07:49:25.70#ibcon#about to read 6, iclass 33, count 2 2006.260.07:49:25.70#ibcon#read 6, iclass 33, count 2 2006.260.07:49:25.70#ibcon#end of sib2, iclass 33, count 2 2006.260.07:49:25.70#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:49:25.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:49:25.70#ibcon#[27=AT04-05\r\n] 2006.260.07:49:25.70#ibcon#*before write, iclass 33, count 2 2006.260.07:49:25.70#ibcon#enter sib2, iclass 33, count 2 2006.260.07:49:25.70#ibcon#flushed, iclass 33, count 2 2006.260.07:49:25.70#ibcon#about to write, iclass 33, count 2 2006.260.07:49:25.70#ibcon#wrote, iclass 33, count 2 2006.260.07:49:25.70#ibcon#about to read 3, iclass 33, count 2 2006.260.07:49:25.73#ibcon#read 3, iclass 33, count 2 2006.260.07:49:25.73#ibcon#about to read 4, iclass 33, count 2 2006.260.07:49:25.73#ibcon#read 4, iclass 33, count 2 2006.260.07:49:25.73#ibcon#about to read 5, iclass 33, count 2 2006.260.07:49:25.73#ibcon#read 5, iclass 33, count 2 2006.260.07:49:25.73#ibcon#about to read 6, iclass 33, count 2 2006.260.07:49:25.73#ibcon#read 6, iclass 33, count 2 2006.260.07:49:25.73#ibcon#end of sib2, iclass 33, count 2 2006.260.07:49:25.73#ibcon#*after write, iclass 33, count 2 2006.260.07:49:25.73#ibcon#*before return 0, iclass 33, count 2 2006.260.07:49:25.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:25.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:49:25.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:49:25.73#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:25.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:25.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:25.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:25.85#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:49:25.85#ibcon#first serial, iclass 33, count 0 2006.260.07:49:25.85#ibcon#enter sib2, iclass 33, count 0 2006.260.07:49:25.85#ibcon#flushed, iclass 33, count 0 2006.260.07:49:25.85#ibcon#about to write, iclass 33, count 0 2006.260.07:49:25.85#ibcon#wrote, iclass 33, count 0 2006.260.07:49:25.85#ibcon#about to read 3, iclass 33, count 0 2006.260.07:49:25.87#ibcon#read 3, iclass 33, count 0 2006.260.07:49:25.87#ibcon#about to read 4, iclass 33, count 0 2006.260.07:49:25.87#ibcon#read 4, iclass 33, count 0 2006.260.07:49:25.87#ibcon#about to read 5, iclass 33, count 0 2006.260.07:49:25.87#ibcon#read 5, iclass 33, count 0 2006.260.07:49:25.87#ibcon#about to read 6, iclass 33, count 0 2006.260.07:49:25.87#ibcon#read 6, iclass 33, count 0 2006.260.07:49:25.87#ibcon#end of sib2, iclass 33, count 0 2006.260.07:49:25.87#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:49:25.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:49:25.87#ibcon#[27=USB\r\n] 2006.260.07:49:25.87#ibcon#*before write, iclass 33, count 0 2006.260.07:49:25.87#ibcon#enter sib2, iclass 33, count 0 2006.260.07:49:25.87#ibcon#flushed, iclass 33, count 0 2006.260.07:49:25.87#ibcon#about to write, iclass 33, count 0 2006.260.07:49:25.87#ibcon#wrote, iclass 33, count 0 2006.260.07:49:25.87#ibcon#about to read 3, iclass 33, count 0 2006.260.07:49:25.90#ibcon#read 3, iclass 33, count 0 2006.260.07:49:25.90#ibcon#about to read 4, iclass 33, count 0 2006.260.07:49:25.90#ibcon#read 4, iclass 33, count 0 2006.260.07:49:25.90#ibcon#about to read 5, iclass 33, count 0 2006.260.07:49:25.90#ibcon#read 5, iclass 33, count 0 2006.260.07:49:25.90#ibcon#about to read 6, iclass 33, count 0 2006.260.07:49:25.90#ibcon#read 6, iclass 33, count 0 2006.260.07:49:25.90#ibcon#end of sib2, iclass 33, count 0 2006.260.07:49:25.90#ibcon#*after write, iclass 33, count 0 2006.260.07:49:25.90#ibcon#*before return 0, iclass 33, count 0 2006.260.07:49:25.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:25.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:49:25.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:49:25.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:49:25.90$vc4f8/vblo=5,744.99 2006.260.07:49:25.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:49:25.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:49:25.90#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:25.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:25.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:25.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:25.90#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:49:25.90#ibcon#first serial, iclass 35, count 0 2006.260.07:49:25.90#ibcon#enter sib2, iclass 35, count 0 2006.260.07:49:25.90#ibcon#flushed, iclass 35, count 0 2006.260.07:49:25.90#ibcon#about to write, iclass 35, count 0 2006.260.07:49:25.90#ibcon#wrote, iclass 35, count 0 2006.260.07:49:25.90#ibcon#about to read 3, iclass 35, count 0 2006.260.07:49:25.92#ibcon#read 3, iclass 35, count 0 2006.260.07:49:25.92#ibcon#about to read 4, iclass 35, count 0 2006.260.07:49:25.92#ibcon#read 4, iclass 35, count 0 2006.260.07:49:25.92#ibcon#about to read 5, iclass 35, count 0 2006.260.07:49:25.92#ibcon#read 5, iclass 35, count 0 2006.260.07:49:25.92#ibcon#about to read 6, iclass 35, count 0 2006.260.07:49:25.92#ibcon#read 6, iclass 35, count 0 2006.260.07:49:25.92#ibcon#end of sib2, iclass 35, count 0 2006.260.07:49:25.92#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:49:25.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:49:25.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:49:25.92#ibcon#*before write, iclass 35, count 0 2006.260.07:49:25.92#ibcon#enter sib2, iclass 35, count 0 2006.260.07:49:25.92#ibcon#flushed, iclass 35, count 0 2006.260.07:49:25.92#ibcon#about to write, iclass 35, count 0 2006.260.07:49:25.92#ibcon#wrote, iclass 35, count 0 2006.260.07:49:25.92#ibcon#about to read 3, iclass 35, count 0 2006.260.07:49:25.96#ibcon#read 3, iclass 35, count 0 2006.260.07:49:25.96#ibcon#about to read 4, iclass 35, count 0 2006.260.07:49:25.96#ibcon#read 4, iclass 35, count 0 2006.260.07:49:25.96#ibcon#about to read 5, iclass 35, count 0 2006.260.07:49:25.96#ibcon#read 5, iclass 35, count 0 2006.260.07:49:25.96#ibcon#about to read 6, iclass 35, count 0 2006.260.07:49:25.96#ibcon#read 6, iclass 35, count 0 2006.260.07:49:25.96#ibcon#end of sib2, iclass 35, count 0 2006.260.07:49:25.96#ibcon#*after write, iclass 35, count 0 2006.260.07:49:25.96#ibcon#*before return 0, iclass 35, count 0 2006.260.07:49:25.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:25.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:49:25.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:49:25.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:49:25.96$vc4f8/vb=5,4 2006.260.07:49:25.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:49:25.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:49:25.96#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:25.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:26.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:26.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:26.02#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:49:26.02#ibcon#first serial, iclass 37, count 2 2006.260.07:49:26.02#ibcon#enter sib2, iclass 37, count 2 2006.260.07:49:26.02#ibcon#flushed, iclass 37, count 2 2006.260.07:49:26.02#ibcon#about to write, iclass 37, count 2 2006.260.07:49:26.02#ibcon#wrote, iclass 37, count 2 2006.260.07:49:26.02#ibcon#about to read 3, iclass 37, count 2 2006.260.07:49:26.04#ibcon#read 3, iclass 37, count 2 2006.260.07:49:26.04#ibcon#about to read 4, iclass 37, count 2 2006.260.07:49:26.04#ibcon#read 4, iclass 37, count 2 2006.260.07:49:26.04#ibcon#about to read 5, iclass 37, count 2 2006.260.07:49:26.04#ibcon#read 5, iclass 37, count 2 2006.260.07:49:26.04#ibcon#about to read 6, iclass 37, count 2 2006.260.07:49:26.04#ibcon#read 6, iclass 37, count 2 2006.260.07:49:26.04#ibcon#end of sib2, iclass 37, count 2 2006.260.07:49:26.04#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:49:26.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:49:26.04#ibcon#[27=AT05-04\r\n] 2006.260.07:49:26.04#ibcon#*before write, iclass 37, count 2 2006.260.07:49:26.04#ibcon#enter sib2, iclass 37, count 2 2006.260.07:49:26.04#ibcon#flushed, iclass 37, count 2 2006.260.07:49:26.04#ibcon#about to write, iclass 37, count 2 2006.260.07:49:26.04#ibcon#wrote, iclass 37, count 2 2006.260.07:49:26.04#ibcon#about to read 3, iclass 37, count 2 2006.260.07:49:26.07#ibcon#read 3, iclass 37, count 2 2006.260.07:49:26.07#ibcon#about to read 4, iclass 37, count 2 2006.260.07:49:26.07#ibcon#read 4, iclass 37, count 2 2006.260.07:49:26.07#ibcon#about to read 5, iclass 37, count 2 2006.260.07:49:26.07#ibcon#read 5, iclass 37, count 2 2006.260.07:49:26.07#ibcon#about to read 6, iclass 37, count 2 2006.260.07:49:26.07#ibcon#read 6, iclass 37, count 2 2006.260.07:49:26.07#ibcon#end of sib2, iclass 37, count 2 2006.260.07:49:26.07#ibcon#*after write, iclass 37, count 2 2006.260.07:49:26.07#ibcon#*before return 0, iclass 37, count 2 2006.260.07:49:26.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:26.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:49:26.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:49:26.07#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:26.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:26.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:26.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:26.19#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:49:26.19#ibcon#first serial, iclass 37, count 0 2006.260.07:49:26.19#ibcon#enter sib2, iclass 37, count 0 2006.260.07:49:26.19#ibcon#flushed, iclass 37, count 0 2006.260.07:49:26.19#ibcon#about to write, iclass 37, count 0 2006.260.07:49:26.19#ibcon#wrote, iclass 37, count 0 2006.260.07:49:26.19#ibcon#about to read 3, iclass 37, count 0 2006.260.07:49:26.21#ibcon#read 3, iclass 37, count 0 2006.260.07:49:26.21#ibcon#about to read 4, iclass 37, count 0 2006.260.07:49:26.21#ibcon#read 4, iclass 37, count 0 2006.260.07:49:26.21#ibcon#about to read 5, iclass 37, count 0 2006.260.07:49:26.21#ibcon#read 5, iclass 37, count 0 2006.260.07:49:26.21#ibcon#about to read 6, iclass 37, count 0 2006.260.07:49:26.21#ibcon#read 6, iclass 37, count 0 2006.260.07:49:26.21#ibcon#end of sib2, iclass 37, count 0 2006.260.07:49:26.21#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:49:26.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:49:26.21#ibcon#[27=USB\r\n] 2006.260.07:49:26.21#ibcon#*before write, iclass 37, count 0 2006.260.07:49:26.21#ibcon#enter sib2, iclass 37, count 0 2006.260.07:49:26.21#ibcon#flushed, iclass 37, count 0 2006.260.07:49:26.21#ibcon#about to write, iclass 37, count 0 2006.260.07:49:26.21#ibcon#wrote, iclass 37, count 0 2006.260.07:49:26.21#ibcon#about to read 3, iclass 37, count 0 2006.260.07:49:26.24#ibcon#read 3, iclass 37, count 0 2006.260.07:49:26.24#ibcon#about to read 4, iclass 37, count 0 2006.260.07:49:26.24#ibcon#read 4, iclass 37, count 0 2006.260.07:49:26.24#ibcon#about to read 5, iclass 37, count 0 2006.260.07:49:26.24#ibcon#read 5, iclass 37, count 0 2006.260.07:49:26.24#ibcon#about to read 6, iclass 37, count 0 2006.260.07:49:26.24#ibcon#read 6, iclass 37, count 0 2006.260.07:49:26.24#ibcon#end of sib2, iclass 37, count 0 2006.260.07:49:26.24#ibcon#*after write, iclass 37, count 0 2006.260.07:49:26.24#ibcon#*before return 0, iclass 37, count 0 2006.260.07:49:26.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:26.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:49:26.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:49:26.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:49:26.24$vc4f8/vblo=6,752.99 2006.260.07:49:26.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:49:26.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:49:26.24#ibcon#ireg 17 cls_cnt 0 2006.260.07:49:26.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:26.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:26.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:26.24#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:49:26.24#ibcon#first serial, iclass 39, count 0 2006.260.07:49:26.24#ibcon#enter sib2, iclass 39, count 0 2006.260.07:49:26.24#ibcon#flushed, iclass 39, count 0 2006.260.07:49:26.24#ibcon#about to write, iclass 39, count 0 2006.260.07:49:26.24#ibcon#wrote, iclass 39, count 0 2006.260.07:49:26.24#ibcon#about to read 3, iclass 39, count 0 2006.260.07:49:26.26#ibcon#read 3, iclass 39, count 0 2006.260.07:49:26.26#ibcon#about to read 4, iclass 39, count 0 2006.260.07:49:26.26#ibcon#read 4, iclass 39, count 0 2006.260.07:49:26.26#ibcon#about to read 5, iclass 39, count 0 2006.260.07:49:26.26#ibcon#read 5, iclass 39, count 0 2006.260.07:49:26.26#ibcon#about to read 6, iclass 39, count 0 2006.260.07:49:26.26#ibcon#read 6, iclass 39, count 0 2006.260.07:49:26.26#ibcon#end of sib2, iclass 39, count 0 2006.260.07:49:26.26#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:49:26.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:49:26.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:49:26.26#ibcon#*before write, iclass 39, count 0 2006.260.07:49:26.26#ibcon#enter sib2, iclass 39, count 0 2006.260.07:49:26.26#ibcon#flushed, iclass 39, count 0 2006.260.07:49:26.26#ibcon#about to write, iclass 39, count 0 2006.260.07:49:26.26#ibcon#wrote, iclass 39, count 0 2006.260.07:49:26.26#ibcon#about to read 3, iclass 39, count 0 2006.260.07:49:26.30#ibcon#read 3, iclass 39, count 0 2006.260.07:49:26.30#ibcon#about to read 4, iclass 39, count 0 2006.260.07:49:26.30#ibcon#read 4, iclass 39, count 0 2006.260.07:49:26.30#ibcon#about to read 5, iclass 39, count 0 2006.260.07:49:26.30#ibcon#read 5, iclass 39, count 0 2006.260.07:49:26.30#ibcon#about to read 6, iclass 39, count 0 2006.260.07:49:26.30#ibcon#read 6, iclass 39, count 0 2006.260.07:49:26.30#ibcon#end of sib2, iclass 39, count 0 2006.260.07:49:26.30#ibcon#*after write, iclass 39, count 0 2006.260.07:49:26.30#ibcon#*before return 0, iclass 39, count 0 2006.260.07:49:26.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:26.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:49:26.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:49:26.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:49:26.30$vc4f8/vb=6,4 2006.260.07:49:26.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:49:26.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:49:26.30#ibcon#ireg 11 cls_cnt 2 2006.260.07:49:26.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:26.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:26.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:26.36#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:49:26.36#ibcon#first serial, iclass 3, count 2 2006.260.07:49:26.36#ibcon#enter sib2, iclass 3, count 2 2006.260.07:49:26.36#ibcon#flushed, iclass 3, count 2 2006.260.07:49:26.36#ibcon#about to write, iclass 3, count 2 2006.260.07:49:26.36#ibcon#wrote, iclass 3, count 2 2006.260.07:49:26.36#ibcon#about to read 3, iclass 3, count 2 2006.260.07:49:26.38#ibcon#read 3, iclass 3, count 2 2006.260.07:49:26.38#ibcon#about to read 4, iclass 3, count 2 2006.260.07:49:26.38#ibcon#read 4, iclass 3, count 2 2006.260.07:49:26.38#ibcon#about to read 5, iclass 3, count 2 2006.260.07:49:26.38#ibcon#read 5, iclass 3, count 2 2006.260.07:49:26.38#ibcon#about to read 6, iclass 3, count 2 2006.260.07:49:26.38#ibcon#read 6, iclass 3, count 2 2006.260.07:49:26.38#ibcon#end of sib2, iclass 3, count 2 2006.260.07:49:26.38#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:49:26.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:49:26.38#ibcon#[27=AT06-04\r\n] 2006.260.07:49:26.38#ibcon#*before write, iclass 3, count 2 2006.260.07:49:26.38#ibcon#enter sib2, iclass 3, count 2 2006.260.07:49:26.38#ibcon#flushed, iclass 3, count 2 2006.260.07:49:26.38#ibcon#about to write, iclass 3, count 2 2006.260.07:49:26.38#ibcon#wrote, iclass 3, count 2 2006.260.07:49:26.38#ibcon#about to read 3, iclass 3, count 2 2006.260.07:49:26.41#ibcon#read 3, iclass 3, count 2 2006.260.07:49:26.41#ibcon#about to read 4, iclass 3, count 2 2006.260.07:49:26.41#ibcon#read 4, iclass 3, count 2 2006.260.07:49:26.41#ibcon#about to read 5, iclass 3, count 2 2006.260.07:49:26.41#ibcon#read 5, iclass 3, count 2 2006.260.07:49:26.41#ibcon#about to read 6, iclass 3, count 2 2006.260.07:49:26.41#ibcon#read 6, iclass 3, count 2 2006.260.07:49:26.41#ibcon#end of sib2, iclass 3, count 2 2006.260.07:49:26.41#ibcon#*after write, iclass 3, count 2 2006.260.07:49:26.41#ibcon#*before return 0, iclass 3, count 2 2006.260.07:49:26.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:26.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:49:26.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:49:26.41#ibcon#ireg 7 cls_cnt 0 2006.260.07:49:26.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:26.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:26.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:26.53#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:49:26.53#ibcon#first serial, iclass 3, count 0 2006.260.07:49:26.53#ibcon#enter sib2, iclass 3, count 0 2006.260.07:49:26.53#ibcon#flushed, iclass 3, count 0 2006.260.07:49:26.53#ibcon#about to write, iclass 3, count 0 2006.260.07:49:26.53#ibcon#wrote, iclass 3, count 0 2006.260.07:49:26.53#ibcon#about to read 3, iclass 3, count 0 2006.260.07:49:26.55#ibcon#read 3, iclass 3, count 0 2006.260.07:49:26.55#ibcon#about to read 4, iclass 3, count 0 2006.260.07:49:26.55#ibcon#read 4, iclass 3, count 0 2006.260.07:49:26.55#ibcon#about to read 5, iclass 3, count 0 2006.260.07:49:26.55#ibcon#read 5, iclass 3, count 0 2006.260.07:49:26.55#ibcon#about to read 6, iclass 3, count 0 2006.260.07:49:26.55#ibcon#read 6, iclass 3, count 0 2006.260.07:49:26.55#ibcon#end of sib2, iclass 3, count 0 2006.260.07:49:26.55#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:49:26.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:49:26.55#ibcon#[27=USB\r\n] 2006.260.07:49:26.55#ibcon#*before write, iclass 3, count 0 2006.260.07:49:26.55#ibcon#enter sib2, iclass 3, count 0 2006.260.07:49:26.55#ibcon#flushed, iclass 3, count 0 2006.260.07:49:26.55#ibcon#about to write, iclass 3, count 0 2006.260.07:49:26.55#ibcon#wrote, iclass 3, count 0 2006.260.07:49:26.55#ibcon#about to read 3, iclass 3, count 0 2006.260.07:49:26.58#ibcon#read 3, iclass 3, count 0 2006.260.07:49:26.58#ibcon#about to read 4, iclass 3, count 0 2006.260.07:49:26.58#ibcon#read 4, iclass 3, count 0 2006.260.07:49:26.58#ibcon#about to read 5, iclass 3, count 0 2006.260.07:49:26.58#ibcon#read 5, iclass 3, count 0 2006.260.07:49:26.58#ibcon#about to read 6, iclass 3, count 0 2006.260.07:49:26.58#ibcon#read 6, iclass 3, count 0 2006.260.07:49:26.58#ibcon#end of sib2, iclass 3, count 0 2006.260.07:49:26.58#ibcon#*after write, iclass 3, count 0 2006.260.07:49:26.58#ibcon#*before return 0, iclass 3, count 0 2006.260.07:49:26.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:26.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:49:26.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:49:26.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:49:26.58$vc4f8/vabw=wide 2006.260.07:49:26.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:49:26.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:49:26.58#ibcon#ireg 8 cls_cnt 0 2006.260.07:49:26.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:26.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:26.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:26.58#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:49:26.58#ibcon#first serial, iclass 5, count 0 2006.260.07:49:26.58#ibcon#enter sib2, iclass 5, count 0 2006.260.07:49:26.58#ibcon#flushed, iclass 5, count 0 2006.260.07:49:26.58#ibcon#about to write, iclass 5, count 0 2006.260.07:49:26.58#ibcon#wrote, iclass 5, count 0 2006.260.07:49:26.58#ibcon#about to read 3, iclass 5, count 0 2006.260.07:49:26.60#ibcon#read 3, iclass 5, count 0 2006.260.07:49:26.60#ibcon#about to read 4, iclass 5, count 0 2006.260.07:49:26.60#ibcon#read 4, iclass 5, count 0 2006.260.07:49:26.60#ibcon#about to read 5, iclass 5, count 0 2006.260.07:49:26.60#ibcon#read 5, iclass 5, count 0 2006.260.07:49:26.60#ibcon#about to read 6, iclass 5, count 0 2006.260.07:49:26.60#ibcon#read 6, iclass 5, count 0 2006.260.07:49:26.60#ibcon#end of sib2, iclass 5, count 0 2006.260.07:49:26.60#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:49:26.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:49:26.60#ibcon#[25=BW32\r\n] 2006.260.07:49:26.60#ibcon#*before write, iclass 5, count 0 2006.260.07:49:26.60#ibcon#enter sib2, iclass 5, count 0 2006.260.07:49:26.60#ibcon#flushed, iclass 5, count 0 2006.260.07:49:26.60#ibcon#about to write, iclass 5, count 0 2006.260.07:49:26.60#ibcon#wrote, iclass 5, count 0 2006.260.07:49:26.60#ibcon#about to read 3, iclass 5, count 0 2006.260.07:49:26.63#ibcon#read 3, iclass 5, count 0 2006.260.07:49:26.63#ibcon#about to read 4, iclass 5, count 0 2006.260.07:49:26.63#ibcon#read 4, iclass 5, count 0 2006.260.07:49:26.63#ibcon#about to read 5, iclass 5, count 0 2006.260.07:49:26.63#ibcon#read 5, iclass 5, count 0 2006.260.07:49:26.63#ibcon#about to read 6, iclass 5, count 0 2006.260.07:49:26.63#ibcon#read 6, iclass 5, count 0 2006.260.07:49:26.63#ibcon#end of sib2, iclass 5, count 0 2006.260.07:49:26.63#ibcon#*after write, iclass 5, count 0 2006.260.07:49:26.63#ibcon#*before return 0, iclass 5, count 0 2006.260.07:49:26.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:26.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:49:26.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:49:26.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:49:26.63$vc4f8/vbbw=wide 2006.260.07:49:26.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:49:26.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:49:26.63#ibcon#ireg 8 cls_cnt 0 2006.260.07:49:26.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:49:26.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:49:26.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:49:26.70#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:49:26.70#ibcon#first serial, iclass 7, count 0 2006.260.07:49:26.70#ibcon#enter sib2, iclass 7, count 0 2006.260.07:49:26.70#ibcon#flushed, iclass 7, count 0 2006.260.07:49:26.70#ibcon#about to write, iclass 7, count 0 2006.260.07:49:26.70#ibcon#wrote, iclass 7, count 0 2006.260.07:49:26.70#ibcon#about to read 3, iclass 7, count 0 2006.260.07:49:26.72#ibcon#read 3, iclass 7, count 0 2006.260.07:49:26.72#ibcon#about to read 4, iclass 7, count 0 2006.260.07:49:26.72#ibcon#read 4, iclass 7, count 0 2006.260.07:49:26.72#ibcon#about to read 5, iclass 7, count 0 2006.260.07:49:26.72#ibcon#read 5, iclass 7, count 0 2006.260.07:49:26.72#ibcon#about to read 6, iclass 7, count 0 2006.260.07:49:26.72#ibcon#read 6, iclass 7, count 0 2006.260.07:49:26.72#ibcon#end of sib2, iclass 7, count 0 2006.260.07:49:26.72#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:49:26.72#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:49:26.72#ibcon#[27=BW32\r\n] 2006.260.07:49:26.72#ibcon#*before write, iclass 7, count 0 2006.260.07:49:26.72#ibcon#enter sib2, iclass 7, count 0 2006.260.07:49:26.72#ibcon#flushed, iclass 7, count 0 2006.260.07:49:26.72#ibcon#about to write, iclass 7, count 0 2006.260.07:49:26.72#ibcon#wrote, iclass 7, count 0 2006.260.07:49:26.72#ibcon#about to read 3, iclass 7, count 0 2006.260.07:49:26.75#ibcon#read 3, iclass 7, count 0 2006.260.07:49:26.75#ibcon#about to read 4, iclass 7, count 0 2006.260.07:49:26.75#ibcon#read 4, iclass 7, count 0 2006.260.07:49:26.75#ibcon#about to read 5, iclass 7, count 0 2006.260.07:49:26.75#ibcon#read 5, iclass 7, count 0 2006.260.07:49:26.75#ibcon#about to read 6, iclass 7, count 0 2006.260.07:49:26.75#ibcon#read 6, iclass 7, count 0 2006.260.07:49:26.75#ibcon#end of sib2, iclass 7, count 0 2006.260.07:49:26.75#ibcon#*after write, iclass 7, count 0 2006.260.07:49:26.75#ibcon#*before return 0, iclass 7, count 0 2006.260.07:49:26.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:49:26.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:49:26.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:49:26.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:49:26.75$4f8m12a/ifd4f 2006.260.07:49:26.75$ifd4f/lo= 2006.260.07:49:26.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:49:26.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:49:26.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:49:26.75$ifd4f/patch= 2006.260.07:49:26.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:49:26.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:49:26.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:49:26.75$4f8m12a/"form=m,16.000,1:2 2006.260.07:49:26.75$4f8m12a/"tpicd 2006.260.07:49:26.75$4f8m12a/echo=off 2006.260.07:49:26.75$4f8m12a/xlog=off 2006.260.07:49:26.75:!2006.260.07:50:00 2006.260.07:49:39.14#trakl#Source acquired 2006.260.07:49:41.14#flagr#flagr/antenna,acquired 2006.260.07:50:00.02:preob 2006.260.07:50:01.14/onsource/TRACKING 2006.260.07:50:01.14:!2006.260.07:50:10 2006.260.07:50:10.02:data_valid=on 2006.260.07:50:10.02:midob 2006.260.07:50:11.15/onsource/TRACKING 2006.260.07:50:11.15/wx/22.97,1010.4,87 2006.260.07:50:11.32/cable/+6.4580E-03 2006.260.07:50:12.40/va/01,08,usb,yes,31,32 2006.260.07:50:12.41/va/02,07,usb,yes,31,32 2006.260.07:50:12.41/va/03,08,usb,yes,23,23 2006.260.07:50:12.41/va/04,07,usb,yes,32,34 2006.260.07:50:12.41/va/05,07,usb,yes,35,37 2006.260.07:50:12.41/va/06,06,usb,yes,34,34 2006.260.07:50:12.41/va/07,06,usb,yes,35,35 2006.260.07:50:12.41/va/08,06,usb,yes,37,37 2006.260.07:50:12.64/valo/01,532.99,yes,locked 2006.260.07:50:12.64/valo/02,572.99,yes,locked 2006.260.07:50:12.64/valo/03,672.99,yes,locked 2006.260.07:50:12.64/valo/04,832.99,yes,locked 2006.260.07:50:12.64/valo/05,652.99,yes,locked 2006.260.07:50:12.64/valo/06,772.99,yes,locked 2006.260.07:50:12.64/valo/07,832.99,yes,locked 2006.260.07:50:12.64/valo/08,852.99,yes,locked 2006.260.07:50:13.72/vb/01,04,usb,yes,30,28 2006.260.07:50:13.73/vb/02,05,usb,yes,28,29 2006.260.07:50:13.73/vb/03,04,usb,yes,28,32 2006.260.07:50:13.73/vb/04,05,usb,yes,25,25 2006.260.07:50:13.73/vb/05,04,usb,yes,27,31 2006.260.07:50:13.73/vb/06,04,usb,yes,28,31 2006.260.07:50:13.73/vb/07,04,usb,yes,30,30 2006.260.07:50:13.73/vb/08,04,usb,yes,28,31 2006.260.07:50:13.97/vblo/01,632.99,yes,locked 2006.260.07:50:13.97/vblo/02,640.99,yes,locked 2006.260.07:50:13.97/vblo/03,656.99,yes,locked 2006.260.07:50:13.97/vblo/04,712.99,yes,locked 2006.260.07:50:13.97/vblo/05,744.99,yes,locked 2006.260.07:50:13.97/vblo/06,752.99,yes,locked 2006.260.07:50:13.97/vblo/07,734.99,yes,locked 2006.260.07:50:13.97/vblo/08,744.99,yes,locked 2006.260.07:50:14.11/vabw/8 2006.260.07:50:14.26/vbbw/8 2006.260.07:50:14.35/xfe/off,on,15.0 2006.260.07:50:14.74/ifatt/23,28,28,28 2006.260.07:50:15.07/fmout-gps/S +4.53E-07 2006.260.07:50:15.12:!2006.260.07:51:10 2006.260.07:51:10.02:data_valid=off 2006.260.07:51:10.02:postob 2006.260.07:51:10.10/cable/+6.4580E-03 2006.260.07:51:10.11/wx/22.96,1010.4,88 2006.260.07:51:11.07/fmout-gps/S +4.51E-07 2006.260.07:51:11.08:scan_name=260-0752,k06260,60 2006.260.07:51:11.08:source=0718+793,072611.74,791131.0,2000.0,neutral 2006.260.07:51:12.15#flagr#flagr/antenna,new-source 2006.260.07:51:12.15:checkk5 2006.260.07:51:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:51:12.96/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:51:13.40/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:51:13.82/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:51:14.26/chk_obsdata//k5ts1/T2600750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:51:14.69/chk_obsdata//k5ts2/T2600750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:51:15.29/chk_obsdata//k5ts3/T2600750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:51:15.75/chk_obsdata//k5ts4/T2600750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.07:51:16.57/k5log//k5ts1_log_newline 2006.260.07:51:17.50/k5log//k5ts2_log_newline 2006.260.07:51:18.54/k5log//k5ts3_log_newline 2006.260.07:51:19.32/k5log//k5ts4_log_newline 2006.260.07:51:19.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:51:19.34:4f8m12a=1 2006.260.07:51:19.34$4f8m12a/echo=on 2006.260.07:51:19.34$4f8m12a/pcalon 2006.260.07:51:19.34$pcalon/"no phase cal control is implemented here 2006.260.07:51:19.34$4f8m12a/"tpicd=stop 2006.260.07:51:19.34$4f8m12a/vc4f8 2006.260.07:51:19.34$vc4f8/valo=1,532.99 2006.260.07:51:19.35#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:51:19.35#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:51:19.35#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:19.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:19.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:19.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:19.35#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:51:19.35#ibcon#first serial, iclass 15, count 0 2006.260.07:51:19.35#ibcon#enter sib2, iclass 15, count 0 2006.260.07:51:19.35#ibcon#flushed, iclass 15, count 0 2006.260.07:51:19.35#ibcon#about to write, iclass 15, count 0 2006.260.07:51:19.35#ibcon#wrote, iclass 15, count 0 2006.260.07:51:19.35#ibcon#about to read 3, iclass 15, count 0 2006.260.07:51:19.39#ibcon#read 3, iclass 15, count 0 2006.260.07:51:19.39#ibcon#about to read 4, iclass 15, count 0 2006.260.07:51:19.39#ibcon#read 4, iclass 15, count 0 2006.260.07:51:19.39#ibcon#about to read 5, iclass 15, count 0 2006.260.07:51:19.39#ibcon#read 5, iclass 15, count 0 2006.260.07:51:19.39#ibcon#about to read 6, iclass 15, count 0 2006.260.07:51:19.39#ibcon#read 6, iclass 15, count 0 2006.260.07:51:19.39#ibcon#end of sib2, iclass 15, count 0 2006.260.07:51:19.39#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:51:19.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:51:19.39#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:51:19.39#ibcon#*before write, iclass 15, count 0 2006.260.07:51:19.39#ibcon#enter sib2, iclass 15, count 0 2006.260.07:51:19.39#ibcon#flushed, iclass 15, count 0 2006.260.07:51:19.39#ibcon#about to write, iclass 15, count 0 2006.260.07:51:19.39#ibcon#wrote, iclass 15, count 0 2006.260.07:51:19.39#ibcon#about to read 3, iclass 15, count 0 2006.260.07:51:19.43#ibcon#read 3, iclass 15, count 0 2006.260.07:51:19.43#ibcon#about to read 4, iclass 15, count 0 2006.260.07:51:19.43#ibcon#read 4, iclass 15, count 0 2006.260.07:51:19.43#ibcon#about to read 5, iclass 15, count 0 2006.260.07:51:19.43#ibcon#read 5, iclass 15, count 0 2006.260.07:51:19.43#ibcon#about to read 6, iclass 15, count 0 2006.260.07:51:19.43#ibcon#read 6, iclass 15, count 0 2006.260.07:51:19.43#ibcon#end of sib2, iclass 15, count 0 2006.260.07:51:19.43#ibcon#*after write, iclass 15, count 0 2006.260.07:51:19.43#ibcon#*before return 0, iclass 15, count 0 2006.260.07:51:19.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:19.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:19.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:51:19.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:51:19.44$vc4f8/va=1,8 2006.260.07:51:19.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:51:19.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:51:19.44#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:19.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:19.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:19.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:19.44#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:51:19.44#ibcon#first serial, iclass 17, count 2 2006.260.07:51:19.44#ibcon#enter sib2, iclass 17, count 2 2006.260.07:51:19.44#ibcon#flushed, iclass 17, count 2 2006.260.07:51:19.44#ibcon#about to write, iclass 17, count 2 2006.260.07:51:19.44#ibcon#wrote, iclass 17, count 2 2006.260.07:51:19.44#ibcon#about to read 3, iclass 17, count 2 2006.260.07:51:19.46#ibcon#read 3, iclass 17, count 2 2006.260.07:51:19.46#ibcon#about to read 4, iclass 17, count 2 2006.260.07:51:19.46#ibcon#read 4, iclass 17, count 2 2006.260.07:51:19.46#ibcon#about to read 5, iclass 17, count 2 2006.260.07:51:19.46#ibcon#read 5, iclass 17, count 2 2006.260.07:51:19.46#ibcon#about to read 6, iclass 17, count 2 2006.260.07:51:19.46#ibcon#read 6, iclass 17, count 2 2006.260.07:51:19.46#ibcon#end of sib2, iclass 17, count 2 2006.260.07:51:19.46#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:51:19.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:51:19.46#ibcon#[25=AT01-08\r\n] 2006.260.07:51:19.46#ibcon#*before write, iclass 17, count 2 2006.260.07:51:19.46#ibcon#enter sib2, iclass 17, count 2 2006.260.07:51:19.46#ibcon#flushed, iclass 17, count 2 2006.260.07:51:19.46#ibcon#about to write, iclass 17, count 2 2006.260.07:51:19.46#ibcon#wrote, iclass 17, count 2 2006.260.07:51:19.46#ibcon#about to read 3, iclass 17, count 2 2006.260.07:51:19.49#ibcon#read 3, iclass 17, count 2 2006.260.07:51:19.49#ibcon#about to read 4, iclass 17, count 2 2006.260.07:51:19.49#ibcon#read 4, iclass 17, count 2 2006.260.07:51:19.49#ibcon#about to read 5, iclass 17, count 2 2006.260.07:51:19.49#ibcon#read 5, iclass 17, count 2 2006.260.07:51:19.49#ibcon#about to read 6, iclass 17, count 2 2006.260.07:51:19.49#ibcon#read 6, iclass 17, count 2 2006.260.07:51:19.49#ibcon#end of sib2, iclass 17, count 2 2006.260.07:51:19.49#ibcon#*after write, iclass 17, count 2 2006.260.07:51:19.49#ibcon#*before return 0, iclass 17, count 2 2006.260.07:51:19.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:19.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:19.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:51:19.49#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:19.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:19.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:19.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:19.61#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:51:19.61#ibcon#first serial, iclass 17, count 0 2006.260.07:51:19.61#ibcon#enter sib2, iclass 17, count 0 2006.260.07:51:19.61#ibcon#flushed, iclass 17, count 0 2006.260.07:51:19.61#ibcon#about to write, iclass 17, count 0 2006.260.07:51:19.61#ibcon#wrote, iclass 17, count 0 2006.260.07:51:19.61#ibcon#about to read 3, iclass 17, count 0 2006.260.07:51:19.62#ibcon#read 3, iclass 17, count 0 2006.260.07:51:19.62#ibcon#about to read 4, iclass 17, count 0 2006.260.07:51:19.62#ibcon#read 4, iclass 17, count 0 2006.260.07:51:19.62#ibcon#about to read 5, iclass 17, count 0 2006.260.07:51:19.62#ibcon#read 5, iclass 17, count 0 2006.260.07:51:19.62#ibcon#about to read 6, iclass 17, count 0 2006.260.07:51:19.62#ibcon#read 6, iclass 17, count 0 2006.260.07:51:19.62#ibcon#end of sib2, iclass 17, count 0 2006.260.07:51:19.62#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:51:19.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:51:19.62#ibcon#[25=USB\r\n] 2006.260.07:51:19.62#ibcon#*before write, iclass 17, count 0 2006.260.07:51:19.62#ibcon#enter sib2, iclass 17, count 0 2006.260.07:51:19.62#ibcon#flushed, iclass 17, count 0 2006.260.07:51:19.62#ibcon#about to write, iclass 17, count 0 2006.260.07:51:19.62#ibcon#wrote, iclass 17, count 0 2006.260.07:51:19.62#ibcon#about to read 3, iclass 17, count 0 2006.260.07:51:19.65#ibcon#read 3, iclass 17, count 0 2006.260.07:51:19.65#ibcon#about to read 4, iclass 17, count 0 2006.260.07:51:19.65#ibcon#read 4, iclass 17, count 0 2006.260.07:51:19.65#ibcon#about to read 5, iclass 17, count 0 2006.260.07:51:19.65#ibcon#read 5, iclass 17, count 0 2006.260.07:51:19.65#ibcon#about to read 6, iclass 17, count 0 2006.260.07:51:19.65#ibcon#read 6, iclass 17, count 0 2006.260.07:51:19.65#ibcon#end of sib2, iclass 17, count 0 2006.260.07:51:19.65#ibcon#*after write, iclass 17, count 0 2006.260.07:51:19.65#ibcon#*before return 0, iclass 17, count 0 2006.260.07:51:19.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:19.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:19.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:51:19.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:51:19.66$vc4f8/valo=2,572.99 2006.260.07:51:19.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:51:19.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:51:19.66#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:19.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:19.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:19.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:19.66#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:51:19.66#ibcon#first serial, iclass 19, count 0 2006.260.07:51:19.66#ibcon#enter sib2, iclass 19, count 0 2006.260.07:51:19.66#ibcon#flushed, iclass 19, count 0 2006.260.07:51:19.66#ibcon#about to write, iclass 19, count 0 2006.260.07:51:19.66#ibcon#wrote, iclass 19, count 0 2006.260.07:51:19.66#ibcon#about to read 3, iclass 19, count 0 2006.260.07:51:19.67#ibcon#read 3, iclass 19, count 0 2006.260.07:51:19.67#ibcon#about to read 4, iclass 19, count 0 2006.260.07:51:19.67#ibcon#read 4, iclass 19, count 0 2006.260.07:51:19.67#ibcon#about to read 5, iclass 19, count 0 2006.260.07:51:19.67#ibcon#read 5, iclass 19, count 0 2006.260.07:51:19.67#ibcon#about to read 6, iclass 19, count 0 2006.260.07:51:19.67#ibcon#read 6, iclass 19, count 0 2006.260.07:51:19.67#ibcon#end of sib2, iclass 19, count 0 2006.260.07:51:19.67#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:51:19.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:51:19.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:51:19.67#ibcon#*before write, iclass 19, count 0 2006.260.07:51:19.67#ibcon#enter sib2, iclass 19, count 0 2006.260.07:51:19.67#ibcon#flushed, iclass 19, count 0 2006.260.07:51:19.67#ibcon#about to write, iclass 19, count 0 2006.260.07:51:19.67#ibcon#wrote, iclass 19, count 0 2006.260.07:51:19.67#ibcon#about to read 3, iclass 19, count 0 2006.260.07:51:19.72#ibcon#read 3, iclass 19, count 0 2006.260.07:51:19.72#ibcon#about to read 4, iclass 19, count 0 2006.260.07:51:19.72#ibcon#read 4, iclass 19, count 0 2006.260.07:51:19.72#ibcon#about to read 5, iclass 19, count 0 2006.260.07:51:19.72#ibcon#read 5, iclass 19, count 0 2006.260.07:51:19.72#ibcon#about to read 6, iclass 19, count 0 2006.260.07:51:19.72#ibcon#read 6, iclass 19, count 0 2006.260.07:51:19.72#ibcon#end of sib2, iclass 19, count 0 2006.260.07:51:19.72#ibcon#*after write, iclass 19, count 0 2006.260.07:51:19.72#ibcon#*before return 0, iclass 19, count 0 2006.260.07:51:19.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:19.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:19.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:51:19.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:51:19.72$vc4f8/va=2,7 2006.260.07:51:19.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:51:19.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:51:19.72#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:19.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:19.76#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:19.76#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:19.76#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:51:19.76#ibcon#first serial, iclass 21, count 2 2006.260.07:51:19.76#ibcon#enter sib2, iclass 21, count 2 2006.260.07:51:19.76#ibcon#flushed, iclass 21, count 2 2006.260.07:51:19.76#ibcon#about to write, iclass 21, count 2 2006.260.07:51:19.76#ibcon#wrote, iclass 21, count 2 2006.260.07:51:19.76#ibcon#about to read 3, iclass 21, count 2 2006.260.07:51:19.79#ibcon#read 3, iclass 21, count 2 2006.260.07:51:19.79#ibcon#about to read 4, iclass 21, count 2 2006.260.07:51:19.79#ibcon#read 4, iclass 21, count 2 2006.260.07:51:19.79#ibcon#about to read 5, iclass 21, count 2 2006.260.07:51:19.79#ibcon#read 5, iclass 21, count 2 2006.260.07:51:19.79#ibcon#about to read 6, iclass 21, count 2 2006.260.07:51:19.79#ibcon#read 6, iclass 21, count 2 2006.260.07:51:19.79#ibcon#end of sib2, iclass 21, count 2 2006.260.07:51:19.79#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:51:19.79#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:51:19.79#ibcon#[25=AT02-07\r\n] 2006.260.07:51:19.79#ibcon#*before write, iclass 21, count 2 2006.260.07:51:19.79#ibcon#enter sib2, iclass 21, count 2 2006.260.07:51:19.79#ibcon#flushed, iclass 21, count 2 2006.260.07:51:19.79#ibcon#about to write, iclass 21, count 2 2006.260.07:51:19.79#ibcon#wrote, iclass 21, count 2 2006.260.07:51:19.79#ibcon#about to read 3, iclass 21, count 2 2006.260.07:51:19.82#ibcon#read 3, iclass 21, count 2 2006.260.07:51:19.82#ibcon#about to read 4, iclass 21, count 2 2006.260.07:51:19.82#ibcon#read 4, iclass 21, count 2 2006.260.07:51:19.82#ibcon#about to read 5, iclass 21, count 2 2006.260.07:51:19.82#ibcon#read 5, iclass 21, count 2 2006.260.07:51:19.82#ibcon#about to read 6, iclass 21, count 2 2006.260.07:51:19.82#ibcon#read 6, iclass 21, count 2 2006.260.07:51:19.82#ibcon#end of sib2, iclass 21, count 2 2006.260.07:51:19.82#ibcon#*after write, iclass 21, count 2 2006.260.07:51:19.82#ibcon#*before return 0, iclass 21, count 2 2006.260.07:51:19.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:19.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:19.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:51:19.82#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:19.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:19.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:19.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:19.94#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:51:19.94#ibcon#first serial, iclass 21, count 0 2006.260.07:51:19.94#ibcon#enter sib2, iclass 21, count 0 2006.260.07:51:19.94#ibcon#flushed, iclass 21, count 0 2006.260.07:51:19.94#ibcon#about to write, iclass 21, count 0 2006.260.07:51:19.94#ibcon#wrote, iclass 21, count 0 2006.260.07:51:19.94#ibcon#about to read 3, iclass 21, count 0 2006.260.07:51:19.96#ibcon#read 3, iclass 21, count 0 2006.260.07:51:19.96#ibcon#about to read 4, iclass 21, count 0 2006.260.07:51:19.96#ibcon#read 4, iclass 21, count 0 2006.260.07:51:19.96#ibcon#about to read 5, iclass 21, count 0 2006.260.07:51:19.96#ibcon#read 5, iclass 21, count 0 2006.260.07:51:19.96#ibcon#about to read 6, iclass 21, count 0 2006.260.07:51:19.96#ibcon#read 6, iclass 21, count 0 2006.260.07:51:19.96#ibcon#end of sib2, iclass 21, count 0 2006.260.07:51:19.96#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:51:19.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:51:19.96#ibcon#[25=USB\r\n] 2006.260.07:51:19.96#ibcon#*before write, iclass 21, count 0 2006.260.07:51:19.96#ibcon#enter sib2, iclass 21, count 0 2006.260.07:51:19.96#ibcon#flushed, iclass 21, count 0 2006.260.07:51:19.96#ibcon#about to write, iclass 21, count 0 2006.260.07:51:19.96#ibcon#wrote, iclass 21, count 0 2006.260.07:51:19.96#ibcon#about to read 3, iclass 21, count 0 2006.260.07:51:19.99#ibcon#read 3, iclass 21, count 0 2006.260.07:51:19.99#ibcon#about to read 4, iclass 21, count 0 2006.260.07:51:19.99#ibcon#read 4, iclass 21, count 0 2006.260.07:51:19.99#ibcon#about to read 5, iclass 21, count 0 2006.260.07:51:19.99#ibcon#read 5, iclass 21, count 0 2006.260.07:51:19.99#ibcon#about to read 6, iclass 21, count 0 2006.260.07:51:19.99#ibcon#read 6, iclass 21, count 0 2006.260.07:51:19.99#ibcon#end of sib2, iclass 21, count 0 2006.260.07:51:19.99#ibcon#*after write, iclass 21, count 0 2006.260.07:51:19.99#ibcon#*before return 0, iclass 21, count 0 2006.260.07:51:19.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:19.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:19.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:51:19.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:51:20.00$vc4f8/valo=3,672.99 2006.260.07:51:20.00#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:51:20.00#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:51:20.00#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:20.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:51:20.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:51:20.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:51:20.00#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:51:20.00#ibcon#first serial, iclass 23, count 0 2006.260.07:51:20.00#ibcon#enter sib2, iclass 23, count 0 2006.260.07:51:20.00#ibcon#flushed, iclass 23, count 0 2006.260.07:51:20.00#ibcon#about to write, iclass 23, count 0 2006.260.07:51:20.00#ibcon#wrote, iclass 23, count 0 2006.260.07:51:20.00#ibcon#about to read 3, iclass 23, count 0 2006.260.07:51:20.01#ibcon#read 3, iclass 23, count 0 2006.260.07:51:20.01#ibcon#about to read 4, iclass 23, count 0 2006.260.07:51:20.01#ibcon#read 4, iclass 23, count 0 2006.260.07:51:20.01#ibcon#about to read 5, iclass 23, count 0 2006.260.07:51:20.01#ibcon#read 5, iclass 23, count 0 2006.260.07:51:20.01#ibcon#about to read 6, iclass 23, count 0 2006.260.07:51:20.01#ibcon#read 6, iclass 23, count 0 2006.260.07:51:20.01#ibcon#end of sib2, iclass 23, count 0 2006.260.07:51:20.01#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:51:20.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:51:20.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:51:20.01#ibcon#*before write, iclass 23, count 0 2006.260.07:51:20.01#ibcon#enter sib2, iclass 23, count 0 2006.260.07:51:20.01#ibcon#flushed, iclass 23, count 0 2006.260.07:51:20.02#ibcon#about to write, iclass 23, count 0 2006.260.07:51:20.02#ibcon#wrote, iclass 23, count 0 2006.260.07:51:20.02#ibcon#about to read 3, iclass 23, count 0 2006.260.07:51:20.05#ibcon#read 3, iclass 23, count 0 2006.260.07:51:20.05#ibcon#about to read 4, iclass 23, count 0 2006.260.07:51:20.05#ibcon#read 4, iclass 23, count 0 2006.260.07:51:20.05#ibcon#about to read 5, iclass 23, count 0 2006.260.07:51:20.05#ibcon#read 5, iclass 23, count 0 2006.260.07:51:20.05#ibcon#about to read 6, iclass 23, count 0 2006.260.07:51:20.05#ibcon#read 6, iclass 23, count 0 2006.260.07:51:20.05#ibcon#end of sib2, iclass 23, count 0 2006.260.07:51:20.05#ibcon#*after write, iclass 23, count 0 2006.260.07:51:20.05#ibcon#*before return 0, iclass 23, count 0 2006.260.07:51:20.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:51:20.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:51:20.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:51:20.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:51:20.06$vc4f8/va=3,8 2006.260.07:51:20.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.07:51:20.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.07:51:20.06#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:20.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:51:20.10#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:51:20.10#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:51:20.10#ibcon#enter wrdev, iclass 25, count 2 2006.260.07:51:20.10#ibcon#first serial, iclass 25, count 2 2006.260.07:51:20.10#ibcon#enter sib2, iclass 25, count 2 2006.260.07:51:20.10#ibcon#flushed, iclass 25, count 2 2006.260.07:51:20.10#ibcon#about to write, iclass 25, count 2 2006.260.07:51:20.10#ibcon#wrote, iclass 25, count 2 2006.260.07:51:20.10#ibcon#about to read 3, iclass 25, count 2 2006.260.07:51:20.13#ibcon#read 3, iclass 25, count 2 2006.260.07:51:20.13#ibcon#about to read 4, iclass 25, count 2 2006.260.07:51:20.13#ibcon#read 4, iclass 25, count 2 2006.260.07:51:20.13#ibcon#about to read 5, iclass 25, count 2 2006.260.07:51:20.13#ibcon#read 5, iclass 25, count 2 2006.260.07:51:20.13#ibcon#about to read 6, iclass 25, count 2 2006.260.07:51:20.13#ibcon#read 6, iclass 25, count 2 2006.260.07:51:20.13#ibcon#end of sib2, iclass 25, count 2 2006.260.07:51:20.13#ibcon#*mode == 0, iclass 25, count 2 2006.260.07:51:20.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.07:51:20.13#ibcon#[25=AT03-08\r\n] 2006.260.07:51:20.13#ibcon#*before write, iclass 25, count 2 2006.260.07:51:20.13#ibcon#enter sib2, iclass 25, count 2 2006.260.07:51:20.13#ibcon#flushed, iclass 25, count 2 2006.260.07:51:20.13#ibcon#about to write, iclass 25, count 2 2006.260.07:51:20.13#ibcon#wrote, iclass 25, count 2 2006.260.07:51:20.13#ibcon#about to read 3, iclass 25, count 2 2006.260.07:51:20.16#ibcon#read 3, iclass 25, count 2 2006.260.07:51:20.16#ibcon#about to read 4, iclass 25, count 2 2006.260.07:51:20.16#ibcon#read 4, iclass 25, count 2 2006.260.07:51:20.16#ibcon#about to read 5, iclass 25, count 2 2006.260.07:51:20.16#ibcon#read 5, iclass 25, count 2 2006.260.07:51:20.16#ibcon#about to read 6, iclass 25, count 2 2006.260.07:51:20.16#ibcon#read 6, iclass 25, count 2 2006.260.07:51:20.16#ibcon#end of sib2, iclass 25, count 2 2006.260.07:51:20.16#ibcon#*after write, iclass 25, count 2 2006.260.07:51:20.16#ibcon#*before return 0, iclass 25, count 2 2006.260.07:51:20.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:51:20.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.07:51:20.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.07:51:20.16#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:20.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:51:20.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:51:20.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:51:20.28#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:51:20.28#ibcon#first serial, iclass 25, count 0 2006.260.07:51:20.28#ibcon#enter sib2, iclass 25, count 0 2006.260.07:51:20.28#ibcon#flushed, iclass 25, count 0 2006.260.07:51:20.28#ibcon#about to write, iclass 25, count 0 2006.260.07:51:20.28#ibcon#wrote, iclass 25, count 0 2006.260.07:51:20.28#ibcon#about to read 3, iclass 25, count 0 2006.260.07:51:20.30#ibcon#read 3, iclass 25, count 0 2006.260.07:51:20.30#ibcon#about to read 4, iclass 25, count 0 2006.260.07:51:20.30#ibcon#read 4, iclass 25, count 0 2006.260.07:51:20.30#ibcon#about to read 5, iclass 25, count 0 2006.260.07:51:20.30#ibcon#read 5, iclass 25, count 0 2006.260.07:51:20.30#ibcon#about to read 6, iclass 25, count 0 2006.260.07:51:20.30#ibcon#read 6, iclass 25, count 0 2006.260.07:51:20.30#ibcon#end of sib2, iclass 25, count 0 2006.260.07:51:20.30#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:51:20.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:51:20.30#ibcon#[25=USB\r\n] 2006.260.07:51:20.30#ibcon#*before write, iclass 25, count 0 2006.260.07:51:20.30#ibcon#enter sib2, iclass 25, count 0 2006.260.07:51:20.30#ibcon#flushed, iclass 25, count 0 2006.260.07:51:20.30#ibcon#about to write, iclass 25, count 0 2006.260.07:51:20.30#ibcon#wrote, iclass 25, count 0 2006.260.07:51:20.30#ibcon#about to read 3, iclass 25, count 0 2006.260.07:51:20.33#ibcon#read 3, iclass 25, count 0 2006.260.07:51:20.33#ibcon#about to read 4, iclass 25, count 0 2006.260.07:51:20.33#ibcon#read 4, iclass 25, count 0 2006.260.07:51:20.33#ibcon#about to read 5, iclass 25, count 0 2006.260.07:51:20.33#ibcon#read 5, iclass 25, count 0 2006.260.07:51:20.33#ibcon#about to read 6, iclass 25, count 0 2006.260.07:51:20.33#ibcon#read 6, iclass 25, count 0 2006.260.07:51:20.33#ibcon#end of sib2, iclass 25, count 0 2006.260.07:51:20.33#ibcon#*after write, iclass 25, count 0 2006.260.07:51:20.33#ibcon#*before return 0, iclass 25, count 0 2006.260.07:51:20.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:51:20.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.07:51:20.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:51:20.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:51:20.34$vc4f8/valo=4,832.99 2006.260.07:51:20.34#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:51:20.34#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:51:20.34#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:20.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:20.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:20.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:20.34#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:51:20.34#ibcon#first serial, iclass 27, count 0 2006.260.07:51:20.34#ibcon#enter sib2, iclass 27, count 0 2006.260.07:51:20.34#ibcon#flushed, iclass 27, count 0 2006.260.07:51:20.34#ibcon#about to write, iclass 27, count 0 2006.260.07:51:20.34#ibcon#wrote, iclass 27, count 0 2006.260.07:51:20.34#ibcon#about to read 3, iclass 27, count 0 2006.260.07:51:20.35#ibcon#read 3, iclass 27, count 0 2006.260.07:51:20.35#ibcon#about to read 4, iclass 27, count 0 2006.260.07:51:20.35#ibcon#read 4, iclass 27, count 0 2006.260.07:51:20.35#ibcon#about to read 5, iclass 27, count 0 2006.260.07:51:20.35#ibcon#read 5, iclass 27, count 0 2006.260.07:51:20.35#ibcon#about to read 6, iclass 27, count 0 2006.260.07:51:20.35#ibcon#read 6, iclass 27, count 0 2006.260.07:51:20.35#ibcon#end of sib2, iclass 27, count 0 2006.260.07:51:20.35#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:51:20.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:51:20.35#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:51:20.35#ibcon#*before write, iclass 27, count 0 2006.260.07:51:20.35#ibcon#enter sib2, iclass 27, count 0 2006.260.07:51:20.35#ibcon#flushed, iclass 27, count 0 2006.260.07:51:20.35#ibcon#about to write, iclass 27, count 0 2006.260.07:51:20.35#ibcon#wrote, iclass 27, count 0 2006.260.07:51:20.35#ibcon#about to read 3, iclass 27, count 0 2006.260.07:51:20.39#ibcon#read 3, iclass 27, count 0 2006.260.07:51:20.39#ibcon#about to read 4, iclass 27, count 0 2006.260.07:51:20.39#ibcon#read 4, iclass 27, count 0 2006.260.07:51:20.39#ibcon#about to read 5, iclass 27, count 0 2006.260.07:51:20.39#ibcon#read 5, iclass 27, count 0 2006.260.07:51:20.39#ibcon#about to read 6, iclass 27, count 0 2006.260.07:51:20.39#ibcon#read 6, iclass 27, count 0 2006.260.07:51:20.39#ibcon#end of sib2, iclass 27, count 0 2006.260.07:51:20.39#ibcon#*after write, iclass 27, count 0 2006.260.07:51:20.39#ibcon#*before return 0, iclass 27, count 0 2006.260.07:51:20.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:20.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:20.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:51:20.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:51:20.40$vc4f8/va=4,7 2006.260.07:51:20.40#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:51:20.40#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:51:20.40#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:20.40#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:20.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:20.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:20.44#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:51:20.44#ibcon#first serial, iclass 29, count 2 2006.260.07:51:20.44#ibcon#enter sib2, iclass 29, count 2 2006.260.07:51:20.44#ibcon#flushed, iclass 29, count 2 2006.260.07:51:20.44#ibcon#about to write, iclass 29, count 2 2006.260.07:51:20.44#ibcon#wrote, iclass 29, count 2 2006.260.07:51:20.44#ibcon#about to read 3, iclass 29, count 2 2006.260.07:51:20.46#ibcon#read 3, iclass 29, count 2 2006.260.07:51:20.46#ibcon#about to read 4, iclass 29, count 2 2006.260.07:51:20.46#ibcon#read 4, iclass 29, count 2 2006.260.07:51:20.46#ibcon#about to read 5, iclass 29, count 2 2006.260.07:51:20.46#ibcon#read 5, iclass 29, count 2 2006.260.07:51:20.46#ibcon#about to read 6, iclass 29, count 2 2006.260.07:51:20.46#ibcon#read 6, iclass 29, count 2 2006.260.07:51:20.46#ibcon#end of sib2, iclass 29, count 2 2006.260.07:51:20.46#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:51:20.46#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:51:20.46#ibcon#[25=AT04-07\r\n] 2006.260.07:51:20.46#ibcon#*before write, iclass 29, count 2 2006.260.07:51:20.46#ibcon#enter sib2, iclass 29, count 2 2006.260.07:51:20.46#ibcon#flushed, iclass 29, count 2 2006.260.07:51:20.46#ibcon#about to write, iclass 29, count 2 2006.260.07:51:20.46#ibcon#wrote, iclass 29, count 2 2006.260.07:51:20.46#ibcon#about to read 3, iclass 29, count 2 2006.260.07:51:20.49#ibcon#read 3, iclass 29, count 2 2006.260.07:51:20.49#ibcon#about to read 4, iclass 29, count 2 2006.260.07:51:20.49#ibcon#read 4, iclass 29, count 2 2006.260.07:51:20.49#ibcon#about to read 5, iclass 29, count 2 2006.260.07:51:20.49#ibcon#read 5, iclass 29, count 2 2006.260.07:51:20.49#ibcon#about to read 6, iclass 29, count 2 2006.260.07:51:20.49#ibcon#read 6, iclass 29, count 2 2006.260.07:51:20.49#ibcon#end of sib2, iclass 29, count 2 2006.260.07:51:20.49#ibcon#*after write, iclass 29, count 2 2006.260.07:51:20.49#ibcon#*before return 0, iclass 29, count 2 2006.260.07:51:20.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:20.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:20.49#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:51:20.49#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:20.49#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:20.61#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:20.61#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:20.61#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:51:20.61#ibcon#first serial, iclass 29, count 0 2006.260.07:51:20.61#ibcon#enter sib2, iclass 29, count 0 2006.260.07:51:20.61#ibcon#flushed, iclass 29, count 0 2006.260.07:51:20.61#ibcon#about to write, iclass 29, count 0 2006.260.07:51:20.61#ibcon#wrote, iclass 29, count 0 2006.260.07:51:20.61#ibcon#about to read 3, iclass 29, count 0 2006.260.07:51:20.63#ibcon#read 3, iclass 29, count 0 2006.260.07:51:20.63#ibcon#about to read 4, iclass 29, count 0 2006.260.07:51:20.63#ibcon#read 4, iclass 29, count 0 2006.260.07:51:20.63#ibcon#about to read 5, iclass 29, count 0 2006.260.07:51:20.63#ibcon#read 5, iclass 29, count 0 2006.260.07:51:20.63#ibcon#about to read 6, iclass 29, count 0 2006.260.07:51:20.63#ibcon#read 6, iclass 29, count 0 2006.260.07:51:20.63#ibcon#end of sib2, iclass 29, count 0 2006.260.07:51:20.63#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:51:20.63#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:51:20.63#ibcon#[25=USB\r\n] 2006.260.07:51:20.63#ibcon#*before write, iclass 29, count 0 2006.260.07:51:20.63#ibcon#enter sib2, iclass 29, count 0 2006.260.07:51:20.63#ibcon#flushed, iclass 29, count 0 2006.260.07:51:20.63#ibcon#about to write, iclass 29, count 0 2006.260.07:51:20.63#ibcon#wrote, iclass 29, count 0 2006.260.07:51:20.63#ibcon#about to read 3, iclass 29, count 0 2006.260.07:51:20.66#ibcon#read 3, iclass 29, count 0 2006.260.07:51:20.66#ibcon#about to read 4, iclass 29, count 0 2006.260.07:51:20.66#ibcon#read 4, iclass 29, count 0 2006.260.07:51:20.66#ibcon#about to read 5, iclass 29, count 0 2006.260.07:51:20.66#ibcon#read 5, iclass 29, count 0 2006.260.07:51:20.66#ibcon#about to read 6, iclass 29, count 0 2006.260.07:51:20.66#ibcon#read 6, iclass 29, count 0 2006.260.07:51:20.66#ibcon#end of sib2, iclass 29, count 0 2006.260.07:51:20.66#ibcon#*after write, iclass 29, count 0 2006.260.07:51:20.66#ibcon#*before return 0, iclass 29, count 0 2006.260.07:51:20.66#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:20.66#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:20.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:51:20.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:51:20.67$vc4f8/valo=5,652.99 2006.260.07:51:20.67#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:51:20.67#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:51:20.67#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:20.67#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:20.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:20.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:20.67#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:51:20.67#ibcon#first serial, iclass 31, count 0 2006.260.07:51:20.67#ibcon#enter sib2, iclass 31, count 0 2006.260.07:51:20.67#ibcon#flushed, iclass 31, count 0 2006.260.07:51:20.67#ibcon#about to write, iclass 31, count 0 2006.260.07:51:20.67#ibcon#wrote, iclass 31, count 0 2006.260.07:51:20.67#ibcon#about to read 3, iclass 31, count 0 2006.260.07:51:20.68#ibcon#read 3, iclass 31, count 0 2006.260.07:51:20.68#ibcon#about to read 4, iclass 31, count 0 2006.260.07:51:20.68#ibcon#read 4, iclass 31, count 0 2006.260.07:51:20.68#ibcon#about to read 5, iclass 31, count 0 2006.260.07:51:20.68#ibcon#read 5, iclass 31, count 0 2006.260.07:51:20.68#ibcon#about to read 6, iclass 31, count 0 2006.260.07:51:20.68#ibcon#read 6, iclass 31, count 0 2006.260.07:51:20.68#ibcon#end of sib2, iclass 31, count 0 2006.260.07:51:20.68#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:51:20.68#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:51:20.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:51:20.68#ibcon#*before write, iclass 31, count 0 2006.260.07:51:20.68#ibcon#enter sib2, iclass 31, count 0 2006.260.07:51:20.68#ibcon#flushed, iclass 31, count 0 2006.260.07:51:20.68#ibcon#about to write, iclass 31, count 0 2006.260.07:51:20.68#ibcon#wrote, iclass 31, count 0 2006.260.07:51:20.68#ibcon#about to read 3, iclass 31, count 0 2006.260.07:51:20.72#ibcon#read 3, iclass 31, count 0 2006.260.07:51:20.72#ibcon#about to read 4, iclass 31, count 0 2006.260.07:51:20.72#ibcon#read 4, iclass 31, count 0 2006.260.07:51:20.72#ibcon#about to read 5, iclass 31, count 0 2006.260.07:51:20.72#ibcon#read 5, iclass 31, count 0 2006.260.07:51:20.72#ibcon#about to read 6, iclass 31, count 0 2006.260.07:51:20.72#ibcon#read 6, iclass 31, count 0 2006.260.07:51:20.72#ibcon#end of sib2, iclass 31, count 0 2006.260.07:51:20.72#ibcon#*after write, iclass 31, count 0 2006.260.07:51:20.72#ibcon#*before return 0, iclass 31, count 0 2006.260.07:51:20.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:20.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:20.72#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:51:20.72#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:51:20.73$vc4f8/va=5,7 2006.260.07:51:20.73#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:51:20.73#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:51:20.73#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:20.73#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:20.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:20.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:20.77#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:51:20.77#ibcon#first serial, iclass 33, count 2 2006.260.07:51:20.77#ibcon#enter sib2, iclass 33, count 2 2006.260.07:51:20.77#ibcon#flushed, iclass 33, count 2 2006.260.07:51:20.77#ibcon#about to write, iclass 33, count 2 2006.260.07:51:20.77#ibcon#wrote, iclass 33, count 2 2006.260.07:51:20.77#ibcon#about to read 3, iclass 33, count 2 2006.260.07:51:20.79#ibcon#read 3, iclass 33, count 2 2006.260.07:51:20.79#ibcon#about to read 4, iclass 33, count 2 2006.260.07:51:20.79#ibcon#read 4, iclass 33, count 2 2006.260.07:51:20.79#ibcon#about to read 5, iclass 33, count 2 2006.260.07:51:20.79#ibcon#read 5, iclass 33, count 2 2006.260.07:51:20.79#ibcon#about to read 6, iclass 33, count 2 2006.260.07:51:20.79#ibcon#read 6, iclass 33, count 2 2006.260.07:51:20.79#ibcon#end of sib2, iclass 33, count 2 2006.260.07:51:20.79#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:51:20.79#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:51:20.79#ibcon#[25=AT05-07\r\n] 2006.260.07:51:20.79#ibcon#*before write, iclass 33, count 2 2006.260.07:51:20.79#ibcon#enter sib2, iclass 33, count 2 2006.260.07:51:20.79#ibcon#flushed, iclass 33, count 2 2006.260.07:51:20.79#ibcon#about to write, iclass 33, count 2 2006.260.07:51:20.79#ibcon#wrote, iclass 33, count 2 2006.260.07:51:20.79#ibcon#about to read 3, iclass 33, count 2 2006.260.07:51:20.82#ibcon#read 3, iclass 33, count 2 2006.260.07:51:20.82#ibcon#about to read 4, iclass 33, count 2 2006.260.07:51:20.82#ibcon#read 4, iclass 33, count 2 2006.260.07:51:20.82#ibcon#about to read 5, iclass 33, count 2 2006.260.07:51:20.82#ibcon#read 5, iclass 33, count 2 2006.260.07:51:20.82#ibcon#about to read 6, iclass 33, count 2 2006.260.07:51:20.82#ibcon#read 6, iclass 33, count 2 2006.260.07:51:20.82#ibcon#end of sib2, iclass 33, count 2 2006.260.07:51:20.82#ibcon#*after write, iclass 33, count 2 2006.260.07:51:20.82#ibcon#*before return 0, iclass 33, count 2 2006.260.07:51:20.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:20.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:20.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:51:20.82#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:20.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:20.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:20.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:20.94#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:51:20.94#ibcon#first serial, iclass 33, count 0 2006.260.07:51:20.94#ibcon#enter sib2, iclass 33, count 0 2006.260.07:51:20.94#ibcon#flushed, iclass 33, count 0 2006.260.07:51:20.94#ibcon#about to write, iclass 33, count 0 2006.260.07:51:20.94#ibcon#wrote, iclass 33, count 0 2006.260.07:51:20.94#ibcon#about to read 3, iclass 33, count 0 2006.260.07:51:20.96#ibcon#read 3, iclass 33, count 0 2006.260.07:51:20.96#ibcon#about to read 4, iclass 33, count 0 2006.260.07:51:20.96#ibcon#read 4, iclass 33, count 0 2006.260.07:51:20.96#ibcon#about to read 5, iclass 33, count 0 2006.260.07:51:20.96#ibcon#read 5, iclass 33, count 0 2006.260.07:51:20.96#ibcon#about to read 6, iclass 33, count 0 2006.260.07:51:20.96#ibcon#read 6, iclass 33, count 0 2006.260.07:51:20.96#ibcon#end of sib2, iclass 33, count 0 2006.260.07:51:20.96#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:51:20.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:51:20.96#ibcon#[25=USB\r\n] 2006.260.07:51:20.96#ibcon#*before write, iclass 33, count 0 2006.260.07:51:20.96#ibcon#enter sib2, iclass 33, count 0 2006.260.07:51:20.96#ibcon#flushed, iclass 33, count 0 2006.260.07:51:20.96#ibcon#about to write, iclass 33, count 0 2006.260.07:51:20.96#ibcon#wrote, iclass 33, count 0 2006.260.07:51:20.96#ibcon#about to read 3, iclass 33, count 0 2006.260.07:51:20.99#ibcon#read 3, iclass 33, count 0 2006.260.07:51:20.99#ibcon#about to read 4, iclass 33, count 0 2006.260.07:51:20.99#ibcon#read 4, iclass 33, count 0 2006.260.07:51:20.99#ibcon#about to read 5, iclass 33, count 0 2006.260.07:51:20.99#ibcon#read 5, iclass 33, count 0 2006.260.07:51:20.99#ibcon#about to read 6, iclass 33, count 0 2006.260.07:51:20.99#ibcon#read 6, iclass 33, count 0 2006.260.07:51:20.99#ibcon#end of sib2, iclass 33, count 0 2006.260.07:51:20.99#ibcon#*after write, iclass 33, count 0 2006.260.07:51:20.99#ibcon#*before return 0, iclass 33, count 0 2006.260.07:51:20.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:20.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:20.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:51:20.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:51:21.00$vc4f8/valo=6,772.99 2006.260.07:51:21.00#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:51:21.00#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:51:21.00#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:21.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:21.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:21.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:21.00#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:51:21.00#ibcon#first serial, iclass 35, count 0 2006.260.07:51:21.00#ibcon#enter sib2, iclass 35, count 0 2006.260.07:51:21.00#ibcon#flushed, iclass 35, count 0 2006.260.07:51:21.00#ibcon#about to write, iclass 35, count 0 2006.260.07:51:21.00#ibcon#wrote, iclass 35, count 0 2006.260.07:51:21.00#ibcon#about to read 3, iclass 35, count 0 2006.260.07:51:21.01#ibcon#read 3, iclass 35, count 0 2006.260.07:51:21.01#ibcon#about to read 4, iclass 35, count 0 2006.260.07:51:21.01#ibcon#read 4, iclass 35, count 0 2006.260.07:51:21.01#ibcon#about to read 5, iclass 35, count 0 2006.260.07:51:21.01#ibcon#read 5, iclass 35, count 0 2006.260.07:51:21.01#ibcon#about to read 6, iclass 35, count 0 2006.260.07:51:21.01#ibcon#read 6, iclass 35, count 0 2006.260.07:51:21.01#ibcon#end of sib2, iclass 35, count 0 2006.260.07:51:21.01#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:51:21.01#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:51:21.01#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:51:21.01#ibcon#*before write, iclass 35, count 0 2006.260.07:51:21.01#ibcon#enter sib2, iclass 35, count 0 2006.260.07:51:21.01#ibcon#flushed, iclass 35, count 0 2006.260.07:51:21.01#ibcon#about to write, iclass 35, count 0 2006.260.07:51:21.01#ibcon#wrote, iclass 35, count 0 2006.260.07:51:21.01#ibcon#about to read 3, iclass 35, count 0 2006.260.07:51:21.05#ibcon#read 3, iclass 35, count 0 2006.260.07:51:21.05#ibcon#about to read 4, iclass 35, count 0 2006.260.07:51:21.05#ibcon#read 4, iclass 35, count 0 2006.260.07:51:21.05#ibcon#about to read 5, iclass 35, count 0 2006.260.07:51:21.05#ibcon#read 5, iclass 35, count 0 2006.260.07:51:21.05#ibcon#about to read 6, iclass 35, count 0 2006.260.07:51:21.05#ibcon#read 6, iclass 35, count 0 2006.260.07:51:21.05#ibcon#end of sib2, iclass 35, count 0 2006.260.07:51:21.05#ibcon#*after write, iclass 35, count 0 2006.260.07:51:21.05#ibcon#*before return 0, iclass 35, count 0 2006.260.07:51:21.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:21.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:21.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:51:21.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:51:21.06$vc4f8/va=6,6 2006.260.07:51:21.06#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:51:21.06#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:51:21.06#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:21.06#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:21.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:21.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:21.10#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:51:21.10#ibcon#first serial, iclass 37, count 2 2006.260.07:51:21.10#ibcon#enter sib2, iclass 37, count 2 2006.260.07:51:21.10#ibcon#flushed, iclass 37, count 2 2006.260.07:51:21.10#ibcon#about to write, iclass 37, count 2 2006.260.07:51:21.10#ibcon#wrote, iclass 37, count 2 2006.260.07:51:21.10#ibcon#about to read 3, iclass 37, count 2 2006.260.07:51:21.12#ibcon#read 3, iclass 37, count 2 2006.260.07:51:21.12#ibcon#about to read 4, iclass 37, count 2 2006.260.07:51:21.12#ibcon#read 4, iclass 37, count 2 2006.260.07:51:21.12#ibcon#about to read 5, iclass 37, count 2 2006.260.07:51:21.12#ibcon#read 5, iclass 37, count 2 2006.260.07:51:21.12#ibcon#about to read 6, iclass 37, count 2 2006.260.07:51:21.12#ibcon#read 6, iclass 37, count 2 2006.260.07:51:21.12#ibcon#end of sib2, iclass 37, count 2 2006.260.07:51:21.12#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:51:21.12#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:51:21.12#ibcon#[25=AT06-06\r\n] 2006.260.07:51:21.12#ibcon#*before write, iclass 37, count 2 2006.260.07:51:21.12#ibcon#enter sib2, iclass 37, count 2 2006.260.07:51:21.12#ibcon#flushed, iclass 37, count 2 2006.260.07:51:21.12#ibcon#about to write, iclass 37, count 2 2006.260.07:51:21.12#ibcon#wrote, iclass 37, count 2 2006.260.07:51:21.12#ibcon#about to read 3, iclass 37, count 2 2006.260.07:51:21.15#ibcon#read 3, iclass 37, count 2 2006.260.07:51:21.15#ibcon#about to read 4, iclass 37, count 2 2006.260.07:51:21.15#ibcon#read 4, iclass 37, count 2 2006.260.07:51:21.15#ibcon#about to read 5, iclass 37, count 2 2006.260.07:51:21.15#ibcon#read 5, iclass 37, count 2 2006.260.07:51:21.15#ibcon#about to read 6, iclass 37, count 2 2006.260.07:51:21.15#ibcon#read 6, iclass 37, count 2 2006.260.07:51:21.15#ibcon#end of sib2, iclass 37, count 2 2006.260.07:51:21.15#ibcon#*after write, iclass 37, count 2 2006.260.07:51:21.15#ibcon#*before return 0, iclass 37, count 2 2006.260.07:51:21.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:21.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:21.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:51:21.15#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:21.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:21.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:21.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:21.27#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:51:21.27#ibcon#first serial, iclass 37, count 0 2006.260.07:51:21.27#ibcon#enter sib2, iclass 37, count 0 2006.260.07:51:21.27#ibcon#flushed, iclass 37, count 0 2006.260.07:51:21.27#ibcon#about to write, iclass 37, count 0 2006.260.07:51:21.27#ibcon#wrote, iclass 37, count 0 2006.260.07:51:21.27#ibcon#about to read 3, iclass 37, count 0 2006.260.07:51:21.29#ibcon#read 3, iclass 37, count 0 2006.260.07:51:21.29#ibcon#about to read 4, iclass 37, count 0 2006.260.07:51:21.29#ibcon#read 4, iclass 37, count 0 2006.260.07:51:21.29#ibcon#about to read 5, iclass 37, count 0 2006.260.07:51:21.29#ibcon#read 5, iclass 37, count 0 2006.260.07:51:21.29#ibcon#about to read 6, iclass 37, count 0 2006.260.07:51:21.29#ibcon#read 6, iclass 37, count 0 2006.260.07:51:21.29#ibcon#end of sib2, iclass 37, count 0 2006.260.07:51:21.29#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:51:21.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:51:21.29#ibcon#[25=USB\r\n] 2006.260.07:51:21.29#ibcon#*before write, iclass 37, count 0 2006.260.07:51:21.29#ibcon#enter sib2, iclass 37, count 0 2006.260.07:51:21.29#ibcon#flushed, iclass 37, count 0 2006.260.07:51:21.29#ibcon#about to write, iclass 37, count 0 2006.260.07:51:21.29#ibcon#wrote, iclass 37, count 0 2006.260.07:51:21.29#ibcon#about to read 3, iclass 37, count 0 2006.260.07:51:21.32#ibcon#read 3, iclass 37, count 0 2006.260.07:51:21.32#ibcon#about to read 4, iclass 37, count 0 2006.260.07:51:21.32#ibcon#read 4, iclass 37, count 0 2006.260.07:51:21.32#ibcon#about to read 5, iclass 37, count 0 2006.260.07:51:21.32#ibcon#read 5, iclass 37, count 0 2006.260.07:51:21.32#ibcon#about to read 6, iclass 37, count 0 2006.260.07:51:21.32#ibcon#read 6, iclass 37, count 0 2006.260.07:51:21.32#ibcon#end of sib2, iclass 37, count 0 2006.260.07:51:21.32#ibcon#*after write, iclass 37, count 0 2006.260.07:51:21.32#ibcon#*before return 0, iclass 37, count 0 2006.260.07:51:21.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:21.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:21.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:51:21.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:51:21.33$vc4f8/valo=7,832.99 2006.260.07:51:21.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:51:21.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:51:21.33#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:21.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:21.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:21.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:21.33#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:51:21.33#ibcon#first serial, iclass 39, count 0 2006.260.07:51:21.33#ibcon#enter sib2, iclass 39, count 0 2006.260.07:51:21.33#ibcon#flushed, iclass 39, count 0 2006.260.07:51:21.33#ibcon#about to write, iclass 39, count 0 2006.260.07:51:21.33#ibcon#wrote, iclass 39, count 0 2006.260.07:51:21.33#ibcon#about to read 3, iclass 39, count 0 2006.260.07:51:21.34#ibcon#read 3, iclass 39, count 0 2006.260.07:51:21.34#ibcon#about to read 4, iclass 39, count 0 2006.260.07:51:21.34#ibcon#read 4, iclass 39, count 0 2006.260.07:51:21.34#ibcon#about to read 5, iclass 39, count 0 2006.260.07:51:21.34#ibcon#read 5, iclass 39, count 0 2006.260.07:51:21.34#ibcon#about to read 6, iclass 39, count 0 2006.260.07:51:21.34#ibcon#read 6, iclass 39, count 0 2006.260.07:51:21.34#ibcon#end of sib2, iclass 39, count 0 2006.260.07:51:21.34#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:51:21.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:51:21.34#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:51:21.34#ibcon#*before write, iclass 39, count 0 2006.260.07:51:21.34#ibcon#enter sib2, iclass 39, count 0 2006.260.07:51:21.34#ibcon#flushed, iclass 39, count 0 2006.260.07:51:21.34#ibcon#about to write, iclass 39, count 0 2006.260.07:51:21.34#ibcon#wrote, iclass 39, count 0 2006.260.07:51:21.34#ibcon#about to read 3, iclass 39, count 0 2006.260.07:51:21.38#ibcon#read 3, iclass 39, count 0 2006.260.07:51:21.38#ibcon#about to read 4, iclass 39, count 0 2006.260.07:51:21.38#ibcon#read 4, iclass 39, count 0 2006.260.07:51:21.38#ibcon#about to read 5, iclass 39, count 0 2006.260.07:51:21.38#ibcon#read 5, iclass 39, count 0 2006.260.07:51:21.38#ibcon#about to read 6, iclass 39, count 0 2006.260.07:51:21.38#ibcon#read 6, iclass 39, count 0 2006.260.07:51:21.38#ibcon#end of sib2, iclass 39, count 0 2006.260.07:51:21.38#ibcon#*after write, iclass 39, count 0 2006.260.07:51:21.38#ibcon#*before return 0, iclass 39, count 0 2006.260.07:51:21.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:21.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:21.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:51:21.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:51:21.39$vc4f8/va=7,6 2006.260.07:51:21.39#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.07:51:21.39#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.07:51:21.39#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:21.39#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:21.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:21.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:21.43#ibcon#enter wrdev, iclass 3, count 2 2006.260.07:51:21.43#ibcon#first serial, iclass 3, count 2 2006.260.07:51:21.43#ibcon#enter sib2, iclass 3, count 2 2006.260.07:51:21.43#ibcon#flushed, iclass 3, count 2 2006.260.07:51:21.43#ibcon#about to write, iclass 3, count 2 2006.260.07:51:21.43#ibcon#wrote, iclass 3, count 2 2006.260.07:51:21.43#ibcon#about to read 3, iclass 3, count 2 2006.260.07:51:21.45#ibcon#read 3, iclass 3, count 2 2006.260.07:51:21.45#ibcon#about to read 4, iclass 3, count 2 2006.260.07:51:21.45#ibcon#read 4, iclass 3, count 2 2006.260.07:51:21.45#ibcon#about to read 5, iclass 3, count 2 2006.260.07:51:21.45#ibcon#read 5, iclass 3, count 2 2006.260.07:51:21.45#ibcon#about to read 6, iclass 3, count 2 2006.260.07:51:21.45#ibcon#read 6, iclass 3, count 2 2006.260.07:51:21.45#ibcon#end of sib2, iclass 3, count 2 2006.260.07:51:21.45#ibcon#*mode == 0, iclass 3, count 2 2006.260.07:51:21.45#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.07:51:21.45#ibcon#[25=AT07-06\r\n] 2006.260.07:51:21.45#ibcon#*before write, iclass 3, count 2 2006.260.07:51:21.45#ibcon#enter sib2, iclass 3, count 2 2006.260.07:51:21.45#ibcon#flushed, iclass 3, count 2 2006.260.07:51:21.45#ibcon#about to write, iclass 3, count 2 2006.260.07:51:21.45#ibcon#wrote, iclass 3, count 2 2006.260.07:51:21.45#ibcon#about to read 3, iclass 3, count 2 2006.260.07:51:21.48#ibcon#read 3, iclass 3, count 2 2006.260.07:51:21.48#ibcon#about to read 4, iclass 3, count 2 2006.260.07:51:21.48#ibcon#read 4, iclass 3, count 2 2006.260.07:51:21.48#ibcon#about to read 5, iclass 3, count 2 2006.260.07:51:21.48#ibcon#read 5, iclass 3, count 2 2006.260.07:51:21.48#ibcon#about to read 6, iclass 3, count 2 2006.260.07:51:21.48#ibcon#read 6, iclass 3, count 2 2006.260.07:51:21.48#ibcon#end of sib2, iclass 3, count 2 2006.260.07:51:21.48#ibcon#*after write, iclass 3, count 2 2006.260.07:51:21.48#ibcon#*before return 0, iclass 3, count 2 2006.260.07:51:21.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:21.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:21.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.07:51:21.48#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:21.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:51:21.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:51:21.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:51:21.60#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:51:21.60#ibcon#first serial, iclass 3, count 0 2006.260.07:51:21.60#ibcon#enter sib2, iclass 3, count 0 2006.260.07:51:21.60#ibcon#flushed, iclass 3, count 0 2006.260.07:51:21.60#ibcon#about to write, iclass 3, count 0 2006.260.07:51:21.60#ibcon#wrote, iclass 3, count 0 2006.260.07:51:21.60#ibcon#about to read 3, iclass 3, count 0 2006.260.07:51:21.62#ibcon#read 3, iclass 3, count 0 2006.260.07:51:21.62#ibcon#about to read 4, iclass 3, count 0 2006.260.07:51:21.62#ibcon#read 4, iclass 3, count 0 2006.260.07:51:21.62#ibcon#about to read 5, iclass 3, count 0 2006.260.07:51:21.62#ibcon#read 5, iclass 3, count 0 2006.260.07:51:21.62#ibcon#about to read 6, iclass 3, count 0 2006.260.07:51:21.62#ibcon#read 6, iclass 3, count 0 2006.260.07:51:21.62#ibcon#end of sib2, iclass 3, count 0 2006.260.07:51:21.62#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:51:21.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:51:21.62#ibcon#[25=USB\r\n] 2006.260.07:51:21.62#ibcon#*before write, iclass 3, count 0 2006.260.07:51:21.62#ibcon#enter sib2, iclass 3, count 0 2006.260.07:51:21.62#ibcon#flushed, iclass 3, count 0 2006.260.07:51:21.62#ibcon#about to write, iclass 3, count 0 2006.260.07:51:21.62#ibcon#wrote, iclass 3, count 0 2006.260.07:51:21.62#ibcon#about to read 3, iclass 3, count 0 2006.260.07:51:21.65#ibcon#read 3, iclass 3, count 0 2006.260.07:51:21.65#ibcon#about to read 4, iclass 3, count 0 2006.260.07:51:21.65#ibcon#read 4, iclass 3, count 0 2006.260.07:51:21.65#ibcon#about to read 5, iclass 3, count 0 2006.260.07:51:21.65#ibcon#read 5, iclass 3, count 0 2006.260.07:51:21.65#ibcon#about to read 6, iclass 3, count 0 2006.260.07:51:21.65#ibcon#read 6, iclass 3, count 0 2006.260.07:51:21.65#ibcon#end of sib2, iclass 3, count 0 2006.260.07:51:21.65#ibcon#*after write, iclass 3, count 0 2006.260.07:51:21.65#ibcon#*before return 0, iclass 3, count 0 2006.260.07:51:21.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:51:21.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.07:51:21.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:51:21.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:51:21.66$vc4f8/valo=8,852.99 2006.260.07:51:21.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.07:51:21.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.07:51:21.66#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:21.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:51:21.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:51:21.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:51:21.66#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:51:21.66#ibcon#first serial, iclass 5, count 0 2006.260.07:51:21.66#ibcon#enter sib2, iclass 5, count 0 2006.260.07:51:21.66#ibcon#flushed, iclass 5, count 0 2006.260.07:51:21.66#ibcon#about to write, iclass 5, count 0 2006.260.07:51:21.66#ibcon#wrote, iclass 5, count 0 2006.260.07:51:21.66#ibcon#about to read 3, iclass 5, count 0 2006.260.07:51:21.67#ibcon#read 3, iclass 5, count 0 2006.260.07:51:21.67#ibcon#about to read 4, iclass 5, count 0 2006.260.07:51:21.67#ibcon#read 4, iclass 5, count 0 2006.260.07:51:21.67#ibcon#about to read 5, iclass 5, count 0 2006.260.07:51:21.67#ibcon#read 5, iclass 5, count 0 2006.260.07:51:21.67#ibcon#about to read 6, iclass 5, count 0 2006.260.07:51:21.67#ibcon#read 6, iclass 5, count 0 2006.260.07:51:21.67#ibcon#end of sib2, iclass 5, count 0 2006.260.07:51:21.67#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:51:21.67#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:51:21.67#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:51:21.67#ibcon#*before write, iclass 5, count 0 2006.260.07:51:21.67#ibcon#enter sib2, iclass 5, count 0 2006.260.07:51:21.67#ibcon#flushed, iclass 5, count 0 2006.260.07:51:21.67#ibcon#about to write, iclass 5, count 0 2006.260.07:51:21.67#ibcon#wrote, iclass 5, count 0 2006.260.07:51:21.67#ibcon#about to read 3, iclass 5, count 0 2006.260.07:51:21.71#ibcon#read 3, iclass 5, count 0 2006.260.07:51:21.71#ibcon#about to read 4, iclass 5, count 0 2006.260.07:51:21.71#ibcon#read 4, iclass 5, count 0 2006.260.07:51:21.71#ibcon#about to read 5, iclass 5, count 0 2006.260.07:51:21.71#ibcon#read 5, iclass 5, count 0 2006.260.07:51:21.71#ibcon#about to read 6, iclass 5, count 0 2006.260.07:51:21.71#ibcon#read 6, iclass 5, count 0 2006.260.07:51:21.71#ibcon#end of sib2, iclass 5, count 0 2006.260.07:51:21.71#ibcon#*after write, iclass 5, count 0 2006.260.07:51:21.71#ibcon#*before return 0, iclass 5, count 0 2006.260.07:51:21.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:51:21.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.07:51:21.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:51:21.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:51:21.72$vc4f8/va=8,6 2006.260.07:51:21.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.07:51:21.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.07:51:21.72#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:21.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:51:21.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:51:21.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:51:21.76#ibcon#enter wrdev, iclass 7, count 2 2006.260.07:51:21.76#ibcon#first serial, iclass 7, count 2 2006.260.07:51:21.76#ibcon#enter sib2, iclass 7, count 2 2006.260.07:51:21.76#ibcon#flushed, iclass 7, count 2 2006.260.07:51:21.76#ibcon#about to write, iclass 7, count 2 2006.260.07:51:21.76#ibcon#wrote, iclass 7, count 2 2006.260.07:51:21.76#ibcon#about to read 3, iclass 7, count 2 2006.260.07:51:21.78#ibcon#read 3, iclass 7, count 2 2006.260.07:51:21.78#ibcon#about to read 4, iclass 7, count 2 2006.260.07:51:21.78#ibcon#read 4, iclass 7, count 2 2006.260.07:51:21.78#ibcon#about to read 5, iclass 7, count 2 2006.260.07:51:21.78#ibcon#read 5, iclass 7, count 2 2006.260.07:51:21.78#ibcon#about to read 6, iclass 7, count 2 2006.260.07:51:21.78#ibcon#read 6, iclass 7, count 2 2006.260.07:51:21.78#ibcon#end of sib2, iclass 7, count 2 2006.260.07:51:21.78#ibcon#*mode == 0, iclass 7, count 2 2006.260.07:51:21.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.07:51:21.78#ibcon#[25=AT08-06\r\n] 2006.260.07:51:21.78#ibcon#*before write, iclass 7, count 2 2006.260.07:51:21.78#ibcon#enter sib2, iclass 7, count 2 2006.260.07:51:21.78#ibcon#flushed, iclass 7, count 2 2006.260.07:51:21.78#ibcon#about to write, iclass 7, count 2 2006.260.07:51:21.78#ibcon#wrote, iclass 7, count 2 2006.260.07:51:21.78#ibcon#about to read 3, iclass 7, count 2 2006.260.07:51:21.81#ibcon#read 3, iclass 7, count 2 2006.260.07:51:21.81#ibcon#about to read 4, iclass 7, count 2 2006.260.07:51:21.81#ibcon#read 4, iclass 7, count 2 2006.260.07:51:21.81#ibcon#about to read 5, iclass 7, count 2 2006.260.07:51:21.81#ibcon#read 5, iclass 7, count 2 2006.260.07:51:21.81#ibcon#about to read 6, iclass 7, count 2 2006.260.07:51:21.81#ibcon#read 6, iclass 7, count 2 2006.260.07:51:21.81#ibcon#end of sib2, iclass 7, count 2 2006.260.07:51:21.81#ibcon#*after write, iclass 7, count 2 2006.260.07:51:21.81#ibcon#*before return 0, iclass 7, count 2 2006.260.07:51:21.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:51:21.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.07:51:21.81#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.07:51:21.81#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:21.81#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:51:21.93#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:51:21.93#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:51:21.93#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:51:21.93#ibcon#first serial, iclass 7, count 0 2006.260.07:51:21.93#ibcon#enter sib2, iclass 7, count 0 2006.260.07:51:21.93#ibcon#flushed, iclass 7, count 0 2006.260.07:51:21.93#ibcon#about to write, iclass 7, count 0 2006.260.07:51:21.93#ibcon#wrote, iclass 7, count 0 2006.260.07:51:21.93#ibcon#about to read 3, iclass 7, count 0 2006.260.07:51:21.95#ibcon#read 3, iclass 7, count 0 2006.260.07:51:21.95#ibcon#about to read 4, iclass 7, count 0 2006.260.07:51:21.95#ibcon#read 4, iclass 7, count 0 2006.260.07:51:21.95#ibcon#about to read 5, iclass 7, count 0 2006.260.07:51:21.95#ibcon#read 5, iclass 7, count 0 2006.260.07:51:21.95#ibcon#about to read 6, iclass 7, count 0 2006.260.07:51:21.95#ibcon#read 6, iclass 7, count 0 2006.260.07:51:21.95#ibcon#end of sib2, iclass 7, count 0 2006.260.07:51:21.95#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:51:21.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:51:21.95#ibcon#[25=USB\r\n] 2006.260.07:51:21.95#ibcon#*before write, iclass 7, count 0 2006.260.07:51:21.95#ibcon#enter sib2, iclass 7, count 0 2006.260.07:51:21.95#ibcon#flushed, iclass 7, count 0 2006.260.07:51:21.95#ibcon#about to write, iclass 7, count 0 2006.260.07:51:21.95#ibcon#wrote, iclass 7, count 0 2006.260.07:51:21.95#ibcon#about to read 3, iclass 7, count 0 2006.260.07:51:21.98#ibcon#read 3, iclass 7, count 0 2006.260.07:51:21.98#ibcon#about to read 4, iclass 7, count 0 2006.260.07:51:21.98#ibcon#read 4, iclass 7, count 0 2006.260.07:51:21.98#ibcon#about to read 5, iclass 7, count 0 2006.260.07:51:21.98#ibcon#read 5, iclass 7, count 0 2006.260.07:51:21.98#ibcon#about to read 6, iclass 7, count 0 2006.260.07:51:21.98#ibcon#read 6, iclass 7, count 0 2006.260.07:51:21.98#ibcon#end of sib2, iclass 7, count 0 2006.260.07:51:21.98#ibcon#*after write, iclass 7, count 0 2006.260.07:51:21.98#ibcon#*before return 0, iclass 7, count 0 2006.260.07:51:21.98#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:51:21.98#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.07:51:21.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:51:21.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:51:21.99$vc4f8/vblo=1,632.99 2006.260.07:51:21.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.07:51:21.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.07:51:21.99#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:21.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:51:21.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:51:21.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:51:21.99#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:51:21.99#ibcon#first serial, iclass 11, count 0 2006.260.07:51:21.99#ibcon#enter sib2, iclass 11, count 0 2006.260.07:51:21.99#ibcon#flushed, iclass 11, count 0 2006.260.07:51:21.99#ibcon#about to write, iclass 11, count 0 2006.260.07:51:21.99#ibcon#wrote, iclass 11, count 0 2006.260.07:51:21.99#ibcon#about to read 3, iclass 11, count 0 2006.260.07:51:22.00#ibcon#read 3, iclass 11, count 0 2006.260.07:51:22.00#ibcon#about to read 4, iclass 11, count 0 2006.260.07:51:22.00#ibcon#read 4, iclass 11, count 0 2006.260.07:51:22.00#ibcon#about to read 5, iclass 11, count 0 2006.260.07:51:22.00#ibcon#read 5, iclass 11, count 0 2006.260.07:51:22.00#ibcon#about to read 6, iclass 11, count 0 2006.260.07:51:22.00#ibcon#read 6, iclass 11, count 0 2006.260.07:51:22.00#ibcon#end of sib2, iclass 11, count 0 2006.260.07:51:22.00#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:51:22.00#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:51:22.00#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:51:22.00#ibcon#*before write, iclass 11, count 0 2006.260.07:51:22.00#ibcon#enter sib2, iclass 11, count 0 2006.260.07:51:22.00#ibcon#flushed, iclass 11, count 0 2006.260.07:51:22.00#ibcon#about to write, iclass 11, count 0 2006.260.07:51:22.00#ibcon#wrote, iclass 11, count 0 2006.260.07:51:22.00#ibcon#about to read 3, iclass 11, count 0 2006.260.07:51:22.04#ibcon#read 3, iclass 11, count 0 2006.260.07:51:22.04#ibcon#about to read 4, iclass 11, count 0 2006.260.07:51:22.04#ibcon#read 4, iclass 11, count 0 2006.260.07:51:22.04#ibcon#about to read 5, iclass 11, count 0 2006.260.07:51:22.04#ibcon#read 5, iclass 11, count 0 2006.260.07:51:22.04#ibcon#about to read 6, iclass 11, count 0 2006.260.07:51:22.04#ibcon#read 6, iclass 11, count 0 2006.260.07:51:22.04#ibcon#end of sib2, iclass 11, count 0 2006.260.07:51:22.04#ibcon#*after write, iclass 11, count 0 2006.260.07:51:22.04#ibcon#*before return 0, iclass 11, count 0 2006.260.07:51:22.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:51:22.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.07:51:22.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:51:22.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:51:22.05$vc4f8/vb=1,4 2006.260.07:51:22.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.07:51:22.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.07:51:22.05#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:22.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:51:22.05#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:51:22.05#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:51:22.05#ibcon#enter wrdev, iclass 13, count 2 2006.260.07:51:22.05#ibcon#first serial, iclass 13, count 2 2006.260.07:51:22.05#ibcon#enter sib2, iclass 13, count 2 2006.260.07:51:22.05#ibcon#flushed, iclass 13, count 2 2006.260.07:51:22.05#ibcon#about to write, iclass 13, count 2 2006.260.07:51:22.05#ibcon#wrote, iclass 13, count 2 2006.260.07:51:22.05#ibcon#about to read 3, iclass 13, count 2 2006.260.07:51:22.06#ibcon#read 3, iclass 13, count 2 2006.260.07:51:22.06#ibcon#about to read 4, iclass 13, count 2 2006.260.07:51:22.06#ibcon#read 4, iclass 13, count 2 2006.260.07:51:22.06#ibcon#about to read 5, iclass 13, count 2 2006.260.07:51:22.06#ibcon#read 5, iclass 13, count 2 2006.260.07:51:22.06#ibcon#about to read 6, iclass 13, count 2 2006.260.07:51:22.06#ibcon#read 6, iclass 13, count 2 2006.260.07:51:22.06#ibcon#end of sib2, iclass 13, count 2 2006.260.07:51:22.06#ibcon#*mode == 0, iclass 13, count 2 2006.260.07:51:22.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.07:51:22.06#ibcon#[27=AT01-04\r\n] 2006.260.07:51:22.06#ibcon#*before write, iclass 13, count 2 2006.260.07:51:22.06#ibcon#enter sib2, iclass 13, count 2 2006.260.07:51:22.06#ibcon#flushed, iclass 13, count 2 2006.260.07:51:22.06#ibcon#about to write, iclass 13, count 2 2006.260.07:51:22.06#ibcon#wrote, iclass 13, count 2 2006.260.07:51:22.06#ibcon#about to read 3, iclass 13, count 2 2006.260.07:51:22.09#ibcon#read 3, iclass 13, count 2 2006.260.07:51:22.09#ibcon#about to read 4, iclass 13, count 2 2006.260.07:51:22.09#ibcon#read 4, iclass 13, count 2 2006.260.07:51:22.09#ibcon#about to read 5, iclass 13, count 2 2006.260.07:51:22.09#ibcon#read 5, iclass 13, count 2 2006.260.07:51:22.09#ibcon#about to read 6, iclass 13, count 2 2006.260.07:51:22.09#ibcon#read 6, iclass 13, count 2 2006.260.07:51:22.09#ibcon#end of sib2, iclass 13, count 2 2006.260.07:51:22.09#ibcon#*after write, iclass 13, count 2 2006.260.07:51:22.09#ibcon#*before return 0, iclass 13, count 2 2006.260.07:51:22.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:51:22.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.07:51:22.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.07:51:22.09#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:22.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:51:22.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:51:22.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:51:22.21#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:51:22.21#ibcon#first serial, iclass 13, count 0 2006.260.07:51:22.21#ibcon#enter sib2, iclass 13, count 0 2006.260.07:51:22.21#ibcon#flushed, iclass 13, count 0 2006.260.07:51:22.21#ibcon#about to write, iclass 13, count 0 2006.260.07:51:22.21#ibcon#wrote, iclass 13, count 0 2006.260.07:51:22.21#ibcon#about to read 3, iclass 13, count 0 2006.260.07:51:22.23#ibcon#read 3, iclass 13, count 0 2006.260.07:51:22.23#ibcon#about to read 4, iclass 13, count 0 2006.260.07:51:22.23#ibcon#read 4, iclass 13, count 0 2006.260.07:51:22.23#ibcon#about to read 5, iclass 13, count 0 2006.260.07:51:22.23#ibcon#read 5, iclass 13, count 0 2006.260.07:51:22.23#ibcon#about to read 6, iclass 13, count 0 2006.260.07:51:22.23#ibcon#read 6, iclass 13, count 0 2006.260.07:51:22.23#ibcon#end of sib2, iclass 13, count 0 2006.260.07:51:22.23#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:51:22.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:51:22.23#ibcon#[27=USB\r\n] 2006.260.07:51:22.23#ibcon#*before write, iclass 13, count 0 2006.260.07:51:22.23#ibcon#enter sib2, iclass 13, count 0 2006.260.07:51:22.23#ibcon#flushed, iclass 13, count 0 2006.260.07:51:22.23#ibcon#about to write, iclass 13, count 0 2006.260.07:51:22.23#ibcon#wrote, iclass 13, count 0 2006.260.07:51:22.23#ibcon#about to read 3, iclass 13, count 0 2006.260.07:51:22.26#ibcon#read 3, iclass 13, count 0 2006.260.07:51:22.26#ibcon#about to read 4, iclass 13, count 0 2006.260.07:51:22.26#ibcon#read 4, iclass 13, count 0 2006.260.07:51:22.26#ibcon#about to read 5, iclass 13, count 0 2006.260.07:51:22.26#ibcon#read 5, iclass 13, count 0 2006.260.07:51:22.26#ibcon#about to read 6, iclass 13, count 0 2006.260.07:51:22.26#ibcon#read 6, iclass 13, count 0 2006.260.07:51:22.26#ibcon#end of sib2, iclass 13, count 0 2006.260.07:51:22.26#ibcon#*after write, iclass 13, count 0 2006.260.07:51:22.26#ibcon#*before return 0, iclass 13, count 0 2006.260.07:51:22.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:51:22.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.07:51:22.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:51:22.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:51:22.27$vc4f8/vblo=2,640.99 2006.260.07:51:22.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.07:51:22.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.07:51:22.27#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:22.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:22.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:22.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:22.27#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:51:22.27#ibcon#first serial, iclass 15, count 0 2006.260.07:51:22.27#ibcon#enter sib2, iclass 15, count 0 2006.260.07:51:22.27#ibcon#flushed, iclass 15, count 0 2006.260.07:51:22.27#ibcon#about to write, iclass 15, count 0 2006.260.07:51:22.27#ibcon#wrote, iclass 15, count 0 2006.260.07:51:22.27#ibcon#about to read 3, iclass 15, count 0 2006.260.07:51:22.28#ibcon#read 3, iclass 15, count 0 2006.260.07:51:22.28#ibcon#about to read 4, iclass 15, count 0 2006.260.07:51:22.28#ibcon#read 4, iclass 15, count 0 2006.260.07:51:22.28#ibcon#about to read 5, iclass 15, count 0 2006.260.07:51:22.28#ibcon#read 5, iclass 15, count 0 2006.260.07:51:22.28#ibcon#about to read 6, iclass 15, count 0 2006.260.07:51:22.28#ibcon#read 6, iclass 15, count 0 2006.260.07:51:22.28#ibcon#end of sib2, iclass 15, count 0 2006.260.07:51:22.28#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:51:22.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:51:22.28#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:51:22.28#ibcon#*before write, iclass 15, count 0 2006.260.07:51:22.28#ibcon#enter sib2, iclass 15, count 0 2006.260.07:51:22.28#ibcon#flushed, iclass 15, count 0 2006.260.07:51:22.28#ibcon#about to write, iclass 15, count 0 2006.260.07:51:22.28#ibcon#wrote, iclass 15, count 0 2006.260.07:51:22.28#ibcon#about to read 3, iclass 15, count 0 2006.260.07:51:22.32#ibcon#read 3, iclass 15, count 0 2006.260.07:51:22.32#ibcon#about to read 4, iclass 15, count 0 2006.260.07:51:22.32#ibcon#read 4, iclass 15, count 0 2006.260.07:51:22.32#ibcon#about to read 5, iclass 15, count 0 2006.260.07:51:22.32#ibcon#read 5, iclass 15, count 0 2006.260.07:51:22.32#ibcon#about to read 6, iclass 15, count 0 2006.260.07:51:22.32#ibcon#read 6, iclass 15, count 0 2006.260.07:51:22.32#ibcon#end of sib2, iclass 15, count 0 2006.260.07:51:22.32#ibcon#*after write, iclass 15, count 0 2006.260.07:51:22.32#ibcon#*before return 0, iclass 15, count 0 2006.260.07:51:22.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:22.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.07:51:22.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:51:22.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:51:22.33$vc4f8/vb=2,5 2006.260.07:51:22.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.07:51:22.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.07:51:22.33#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:22.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:22.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:22.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:22.37#ibcon#enter wrdev, iclass 17, count 2 2006.260.07:51:22.37#ibcon#first serial, iclass 17, count 2 2006.260.07:51:22.37#ibcon#enter sib2, iclass 17, count 2 2006.260.07:51:22.37#ibcon#flushed, iclass 17, count 2 2006.260.07:51:22.37#ibcon#about to write, iclass 17, count 2 2006.260.07:51:22.37#ibcon#wrote, iclass 17, count 2 2006.260.07:51:22.37#ibcon#about to read 3, iclass 17, count 2 2006.260.07:51:22.39#ibcon#read 3, iclass 17, count 2 2006.260.07:51:22.39#ibcon#about to read 4, iclass 17, count 2 2006.260.07:51:22.39#ibcon#read 4, iclass 17, count 2 2006.260.07:51:22.39#ibcon#about to read 5, iclass 17, count 2 2006.260.07:51:22.39#ibcon#read 5, iclass 17, count 2 2006.260.07:51:22.39#ibcon#about to read 6, iclass 17, count 2 2006.260.07:51:22.39#ibcon#read 6, iclass 17, count 2 2006.260.07:51:22.39#ibcon#end of sib2, iclass 17, count 2 2006.260.07:51:22.39#ibcon#*mode == 0, iclass 17, count 2 2006.260.07:51:22.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.07:51:22.39#ibcon#[27=AT02-05\r\n] 2006.260.07:51:22.39#ibcon#*before write, iclass 17, count 2 2006.260.07:51:22.39#ibcon#enter sib2, iclass 17, count 2 2006.260.07:51:22.39#ibcon#flushed, iclass 17, count 2 2006.260.07:51:22.39#ibcon#about to write, iclass 17, count 2 2006.260.07:51:22.39#ibcon#wrote, iclass 17, count 2 2006.260.07:51:22.39#ibcon#about to read 3, iclass 17, count 2 2006.260.07:51:22.42#ibcon#read 3, iclass 17, count 2 2006.260.07:51:22.42#ibcon#about to read 4, iclass 17, count 2 2006.260.07:51:22.42#ibcon#read 4, iclass 17, count 2 2006.260.07:51:22.42#ibcon#about to read 5, iclass 17, count 2 2006.260.07:51:22.42#ibcon#read 5, iclass 17, count 2 2006.260.07:51:22.42#ibcon#about to read 6, iclass 17, count 2 2006.260.07:51:22.42#ibcon#read 6, iclass 17, count 2 2006.260.07:51:22.42#ibcon#end of sib2, iclass 17, count 2 2006.260.07:51:22.42#ibcon#*after write, iclass 17, count 2 2006.260.07:51:22.42#ibcon#*before return 0, iclass 17, count 2 2006.260.07:51:22.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:22.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.07:51:22.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.07:51:22.42#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:22.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:22.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:22.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:22.54#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:51:22.54#ibcon#first serial, iclass 17, count 0 2006.260.07:51:22.54#ibcon#enter sib2, iclass 17, count 0 2006.260.07:51:22.54#ibcon#flushed, iclass 17, count 0 2006.260.07:51:22.54#ibcon#about to write, iclass 17, count 0 2006.260.07:51:22.54#ibcon#wrote, iclass 17, count 0 2006.260.07:51:22.54#ibcon#about to read 3, iclass 17, count 0 2006.260.07:51:22.56#ibcon#read 3, iclass 17, count 0 2006.260.07:51:22.56#ibcon#about to read 4, iclass 17, count 0 2006.260.07:51:22.56#ibcon#read 4, iclass 17, count 0 2006.260.07:51:22.56#ibcon#about to read 5, iclass 17, count 0 2006.260.07:51:22.56#ibcon#read 5, iclass 17, count 0 2006.260.07:51:22.56#ibcon#about to read 6, iclass 17, count 0 2006.260.07:51:22.56#ibcon#read 6, iclass 17, count 0 2006.260.07:51:22.56#ibcon#end of sib2, iclass 17, count 0 2006.260.07:51:22.56#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:51:22.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:51:22.56#ibcon#[27=USB\r\n] 2006.260.07:51:22.56#ibcon#*before write, iclass 17, count 0 2006.260.07:51:22.56#ibcon#enter sib2, iclass 17, count 0 2006.260.07:51:22.56#ibcon#flushed, iclass 17, count 0 2006.260.07:51:22.56#ibcon#about to write, iclass 17, count 0 2006.260.07:51:22.56#ibcon#wrote, iclass 17, count 0 2006.260.07:51:22.56#ibcon#about to read 3, iclass 17, count 0 2006.260.07:51:22.59#ibcon#read 3, iclass 17, count 0 2006.260.07:51:22.59#ibcon#about to read 4, iclass 17, count 0 2006.260.07:51:22.59#ibcon#read 4, iclass 17, count 0 2006.260.07:51:22.59#ibcon#about to read 5, iclass 17, count 0 2006.260.07:51:22.59#ibcon#read 5, iclass 17, count 0 2006.260.07:51:22.59#ibcon#about to read 6, iclass 17, count 0 2006.260.07:51:22.59#ibcon#read 6, iclass 17, count 0 2006.260.07:51:22.59#ibcon#end of sib2, iclass 17, count 0 2006.260.07:51:22.59#ibcon#*after write, iclass 17, count 0 2006.260.07:51:22.59#ibcon#*before return 0, iclass 17, count 0 2006.260.07:51:22.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:22.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.07:51:22.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:51:22.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:51:22.60$vc4f8/vblo=3,656.99 2006.260.07:51:22.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.07:51:22.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.07:51:22.60#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:22.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:22.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:22.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:22.60#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:51:22.60#ibcon#first serial, iclass 19, count 0 2006.260.07:51:22.60#ibcon#enter sib2, iclass 19, count 0 2006.260.07:51:22.60#ibcon#flushed, iclass 19, count 0 2006.260.07:51:22.60#ibcon#about to write, iclass 19, count 0 2006.260.07:51:22.60#ibcon#wrote, iclass 19, count 0 2006.260.07:51:22.60#ibcon#about to read 3, iclass 19, count 0 2006.260.07:51:22.61#ibcon#read 3, iclass 19, count 0 2006.260.07:51:22.61#ibcon#about to read 4, iclass 19, count 0 2006.260.07:51:22.61#ibcon#read 4, iclass 19, count 0 2006.260.07:51:22.61#ibcon#about to read 5, iclass 19, count 0 2006.260.07:51:22.61#ibcon#read 5, iclass 19, count 0 2006.260.07:51:22.61#ibcon#about to read 6, iclass 19, count 0 2006.260.07:51:22.61#ibcon#read 6, iclass 19, count 0 2006.260.07:51:22.61#ibcon#end of sib2, iclass 19, count 0 2006.260.07:51:22.61#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:51:22.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:51:22.61#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:51:22.61#ibcon#*before write, iclass 19, count 0 2006.260.07:51:22.61#ibcon#enter sib2, iclass 19, count 0 2006.260.07:51:22.61#ibcon#flushed, iclass 19, count 0 2006.260.07:51:22.61#ibcon#about to write, iclass 19, count 0 2006.260.07:51:22.61#ibcon#wrote, iclass 19, count 0 2006.260.07:51:22.61#ibcon#about to read 3, iclass 19, count 0 2006.260.07:51:22.65#ibcon#read 3, iclass 19, count 0 2006.260.07:51:22.65#ibcon#about to read 4, iclass 19, count 0 2006.260.07:51:22.65#ibcon#read 4, iclass 19, count 0 2006.260.07:51:22.65#ibcon#about to read 5, iclass 19, count 0 2006.260.07:51:22.65#ibcon#read 5, iclass 19, count 0 2006.260.07:51:22.65#ibcon#about to read 6, iclass 19, count 0 2006.260.07:51:22.65#ibcon#read 6, iclass 19, count 0 2006.260.07:51:22.65#ibcon#end of sib2, iclass 19, count 0 2006.260.07:51:22.65#ibcon#*after write, iclass 19, count 0 2006.260.07:51:22.65#ibcon#*before return 0, iclass 19, count 0 2006.260.07:51:22.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:22.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.07:51:22.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:51:22.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:51:22.66$vc4f8/vb=3,4 2006.260.07:51:22.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.07:51:22.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.07:51:22.66#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:22.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:22.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:22.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:22.70#ibcon#enter wrdev, iclass 21, count 2 2006.260.07:51:22.70#ibcon#first serial, iclass 21, count 2 2006.260.07:51:22.70#ibcon#enter sib2, iclass 21, count 2 2006.260.07:51:22.70#ibcon#flushed, iclass 21, count 2 2006.260.07:51:22.70#ibcon#about to write, iclass 21, count 2 2006.260.07:51:22.70#ibcon#wrote, iclass 21, count 2 2006.260.07:51:22.70#ibcon#about to read 3, iclass 21, count 2 2006.260.07:51:22.73#ibcon#read 3, iclass 21, count 2 2006.260.07:51:22.73#ibcon#about to read 4, iclass 21, count 2 2006.260.07:51:22.73#ibcon#read 4, iclass 21, count 2 2006.260.07:51:22.73#ibcon#about to read 5, iclass 21, count 2 2006.260.07:51:22.73#ibcon#read 5, iclass 21, count 2 2006.260.07:51:22.73#ibcon#about to read 6, iclass 21, count 2 2006.260.07:51:22.73#ibcon#read 6, iclass 21, count 2 2006.260.07:51:22.73#ibcon#end of sib2, iclass 21, count 2 2006.260.07:51:22.73#ibcon#*mode == 0, iclass 21, count 2 2006.260.07:51:22.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.07:51:22.73#ibcon#[27=AT03-04\r\n] 2006.260.07:51:22.73#ibcon#*before write, iclass 21, count 2 2006.260.07:51:22.73#ibcon#enter sib2, iclass 21, count 2 2006.260.07:51:22.73#ibcon#flushed, iclass 21, count 2 2006.260.07:51:22.73#ibcon#about to write, iclass 21, count 2 2006.260.07:51:22.73#ibcon#wrote, iclass 21, count 2 2006.260.07:51:22.73#ibcon#about to read 3, iclass 21, count 2 2006.260.07:51:22.75#ibcon#read 3, iclass 21, count 2 2006.260.07:51:22.75#ibcon#about to read 4, iclass 21, count 2 2006.260.07:51:22.75#ibcon#read 4, iclass 21, count 2 2006.260.07:51:22.75#ibcon#about to read 5, iclass 21, count 2 2006.260.07:51:22.75#ibcon#read 5, iclass 21, count 2 2006.260.07:51:22.75#ibcon#about to read 6, iclass 21, count 2 2006.260.07:51:22.75#ibcon#read 6, iclass 21, count 2 2006.260.07:51:22.75#ibcon#end of sib2, iclass 21, count 2 2006.260.07:51:22.75#ibcon#*after write, iclass 21, count 2 2006.260.07:51:22.75#ibcon#*before return 0, iclass 21, count 2 2006.260.07:51:22.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:22.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.07:51:22.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.07:51:22.75#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:22.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:22.76#abcon#<5=/04 3.5 6.4 22.95 881010.4\r\n> 2006.260.07:51:22.78#abcon#{5=INTERFACE CLEAR} 2006.260.07:51:22.84#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:51:22.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:22.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:22.87#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:51:22.87#ibcon#first serial, iclass 21, count 0 2006.260.07:51:22.87#ibcon#enter sib2, iclass 21, count 0 2006.260.07:51:22.87#ibcon#flushed, iclass 21, count 0 2006.260.07:51:22.87#ibcon#about to write, iclass 21, count 0 2006.260.07:51:22.87#ibcon#wrote, iclass 21, count 0 2006.260.07:51:22.87#ibcon#about to read 3, iclass 21, count 0 2006.260.07:51:22.89#ibcon#read 3, iclass 21, count 0 2006.260.07:51:22.89#ibcon#about to read 4, iclass 21, count 0 2006.260.07:51:22.89#ibcon#read 4, iclass 21, count 0 2006.260.07:51:22.89#ibcon#about to read 5, iclass 21, count 0 2006.260.07:51:22.89#ibcon#read 5, iclass 21, count 0 2006.260.07:51:22.89#ibcon#about to read 6, iclass 21, count 0 2006.260.07:51:22.89#ibcon#read 6, iclass 21, count 0 2006.260.07:51:22.89#ibcon#end of sib2, iclass 21, count 0 2006.260.07:51:22.89#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:51:22.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:51:22.89#ibcon#[27=USB\r\n] 2006.260.07:51:22.89#ibcon#*before write, iclass 21, count 0 2006.260.07:51:22.89#ibcon#enter sib2, iclass 21, count 0 2006.260.07:51:22.89#ibcon#flushed, iclass 21, count 0 2006.260.07:51:22.89#ibcon#about to write, iclass 21, count 0 2006.260.07:51:22.89#ibcon#wrote, iclass 21, count 0 2006.260.07:51:22.89#ibcon#about to read 3, iclass 21, count 0 2006.260.07:51:22.92#ibcon#read 3, iclass 21, count 0 2006.260.07:51:22.92#ibcon#about to read 4, iclass 21, count 0 2006.260.07:51:22.92#ibcon#read 4, iclass 21, count 0 2006.260.07:51:22.92#ibcon#about to read 5, iclass 21, count 0 2006.260.07:51:22.92#ibcon#read 5, iclass 21, count 0 2006.260.07:51:22.92#ibcon#about to read 6, iclass 21, count 0 2006.260.07:51:22.92#ibcon#read 6, iclass 21, count 0 2006.260.07:51:22.92#ibcon#end of sib2, iclass 21, count 0 2006.260.07:51:22.92#ibcon#*after write, iclass 21, count 0 2006.260.07:51:22.92#ibcon#*before return 0, iclass 21, count 0 2006.260.07:51:22.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:22.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.07:51:22.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:51:22.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:51:22.93$vc4f8/vblo=4,712.99 2006.260.07:51:22.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.07:51:22.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.07:51:22.93#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:22.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:22.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:22.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:22.93#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:51:22.93#ibcon#first serial, iclass 27, count 0 2006.260.07:51:22.93#ibcon#enter sib2, iclass 27, count 0 2006.260.07:51:22.93#ibcon#flushed, iclass 27, count 0 2006.260.07:51:22.93#ibcon#about to write, iclass 27, count 0 2006.260.07:51:22.93#ibcon#wrote, iclass 27, count 0 2006.260.07:51:22.93#ibcon#about to read 3, iclass 27, count 0 2006.260.07:51:22.94#ibcon#read 3, iclass 27, count 0 2006.260.07:51:22.94#ibcon#about to read 4, iclass 27, count 0 2006.260.07:51:22.94#ibcon#read 4, iclass 27, count 0 2006.260.07:51:22.94#ibcon#about to read 5, iclass 27, count 0 2006.260.07:51:22.94#ibcon#read 5, iclass 27, count 0 2006.260.07:51:22.94#ibcon#about to read 6, iclass 27, count 0 2006.260.07:51:22.94#ibcon#read 6, iclass 27, count 0 2006.260.07:51:22.94#ibcon#end of sib2, iclass 27, count 0 2006.260.07:51:22.94#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:51:22.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:51:22.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:51:22.94#ibcon#*before write, iclass 27, count 0 2006.260.07:51:22.94#ibcon#enter sib2, iclass 27, count 0 2006.260.07:51:22.94#ibcon#flushed, iclass 27, count 0 2006.260.07:51:22.94#ibcon#about to write, iclass 27, count 0 2006.260.07:51:22.94#ibcon#wrote, iclass 27, count 0 2006.260.07:51:22.94#ibcon#about to read 3, iclass 27, count 0 2006.260.07:51:22.98#ibcon#read 3, iclass 27, count 0 2006.260.07:51:22.98#ibcon#about to read 4, iclass 27, count 0 2006.260.07:51:22.98#ibcon#read 4, iclass 27, count 0 2006.260.07:51:22.98#ibcon#about to read 5, iclass 27, count 0 2006.260.07:51:22.98#ibcon#read 5, iclass 27, count 0 2006.260.07:51:22.98#ibcon#about to read 6, iclass 27, count 0 2006.260.07:51:22.98#ibcon#read 6, iclass 27, count 0 2006.260.07:51:22.98#ibcon#end of sib2, iclass 27, count 0 2006.260.07:51:22.98#ibcon#*after write, iclass 27, count 0 2006.260.07:51:22.98#ibcon#*before return 0, iclass 27, count 0 2006.260.07:51:22.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:22.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.07:51:22.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:51:22.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:51:22.99$vc4f8/vb=4,5 2006.260.07:51:22.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.07:51:22.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.07:51:22.99#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:22.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:23.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:23.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:23.03#ibcon#enter wrdev, iclass 29, count 2 2006.260.07:51:23.03#ibcon#first serial, iclass 29, count 2 2006.260.07:51:23.03#ibcon#enter sib2, iclass 29, count 2 2006.260.07:51:23.03#ibcon#flushed, iclass 29, count 2 2006.260.07:51:23.03#ibcon#about to write, iclass 29, count 2 2006.260.07:51:23.03#ibcon#wrote, iclass 29, count 2 2006.260.07:51:23.03#ibcon#about to read 3, iclass 29, count 2 2006.260.07:51:23.05#ibcon#read 3, iclass 29, count 2 2006.260.07:51:23.05#ibcon#about to read 4, iclass 29, count 2 2006.260.07:51:23.05#ibcon#read 4, iclass 29, count 2 2006.260.07:51:23.05#ibcon#about to read 5, iclass 29, count 2 2006.260.07:51:23.05#ibcon#read 5, iclass 29, count 2 2006.260.07:51:23.05#ibcon#about to read 6, iclass 29, count 2 2006.260.07:51:23.05#ibcon#read 6, iclass 29, count 2 2006.260.07:51:23.05#ibcon#end of sib2, iclass 29, count 2 2006.260.07:51:23.05#ibcon#*mode == 0, iclass 29, count 2 2006.260.07:51:23.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.07:51:23.05#ibcon#[27=AT04-05\r\n] 2006.260.07:51:23.05#ibcon#*before write, iclass 29, count 2 2006.260.07:51:23.05#ibcon#enter sib2, iclass 29, count 2 2006.260.07:51:23.05#ibcon#flushed, iclass 29, count 2 2006.260.07:51:23.05#ibcon#about to write, iclass 29, count 2 2006.260.07:51:23.05#ibcon#wrote, iclass 29, count 2 2006.260.07:51:23.05#ibcon#about to read 3, iclass 29, count 2 2006.260.07:51:23.08#ibcon#read 3, iclass 29, count 2 2006.260.07:51:23.08#ibcon#about to read 4, iclass 29, count 2 2006.260.07:51:23.08#ibcon#read 4, iclass 29, count 2 2006.260.07:51:23.08#ibcon#about to read 5, iclass 29, count 2 2006.260.07:51:23.08#ibcon#read 5, iclass 29, count 2 2006.260.07:51:23.08#ibcon#about to read 6, iclass 29, count 2 2006.260.07:51:23.08#ibcon#read 6, iclass 29, count 2 2006.260.07:51:23.08#ibcon#end of sib2, iclass 29, count 2 2006.260.07:51:23.08#ibcon#*after write, iclass 29, count 2 2006.260.07:51:23.08#ibcon#*before return 0, iclass 29, count 2 2006.260.07:51:23.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:23.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.07:51:23.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.07:51:23.08#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:23.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:23.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:23.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:23.20#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:51:23.20#ibcon#first serial, iclass 29, count 0 2006.260.07:51:23.20#ibcon#enter sib2, iclass 29, count 0 2006.260.07:51:23.20#ibcon#flushed, iclass 29, count 0 2006.260.07:51:23.20#ibcon#about to write, iclass 29, count 0 2006.260.07:51:23.20#ibcon#wrote, iclass 29, count 0 2006.260.07:51:23.20#ibcon#about to read 3, iclass 29, count 0 2006.260.07:51:23.22#ibcon#read 3, iclass 29, count 0 2006.260.07:51:23.22#ibcon#about to read 4, iclass 29, count 0 2006.260.07:51:23.22#ibcon#read 4, iclass 29, count 0 2006.260.07:51:23.22#ibcon#about to read 5, iclass 29, count 0 2006.260.07:51:23.22#ibcon#read 5, iclass 29, count 0 2006.260.07:51:23.22#ibcon#about to read 6, iclass 29, count 0 2006.260.07:51:23.22#ibcon#read 6, iclass 29, count 0 2006.260.07:51:23.22#ibcon#end of sib2, iclass 29, count 0 2006.260.07:51:23.22#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:51:23.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:51:23.22#ibcon#[27=USB\r\n] 2006.260.07:51:23.22#ibcon#*before write, iclass 29, count 0 2006.260.07:51:23.22#ibcon#enter sib2, iclass 29, count 0 2006.260.07:51:23.22#ibcon#flushed, iclass 29, count 0 2006.260.07:51:23.22#ibcon#about to write, iclass 29, count 0 2006.260.07:51:23.22#ibcon#wrote, iclass 29, count 0 2006.260.07:51:23.22#ibcon#about to read 3, iclass 29, count 0 2006.260.07:51:23.25#ibcon#read 3, iclass 29, count 0 2006.260.07:51:23.25#ibcon#about to read 4, iclass 29, count 0 2006.260.07:51:23.25#ibcon#read 4, iclass 29, count 0 2006.260.07:51:23.25#ibcon#about to read 5, iclass 29, count 0 2006.260.07:51:23.25#ibcon#read 5, iclass 29, count 0 2006.260.07:51:23.25#ibcon#about to read 6, iclass 29, count 0 2006.260.07:51:23.25#ibcon#read 6, iclass 29, count 0 2006.260.07:51:23.25#ibcon#end of sib2, iclass 29, count 0 2006.260.07:51:23.25#ibcon#*after write, iclass 29, count 0 2006.260.07:51:23.25#ibcon#*before return 0, iclass 29, count 0 2006.260.07:51:23.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:23.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.07:51:23.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:51:23.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:51:23.26$vc4f8/vblo=5,744.99 2006.260.07:51:23.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.07:51:23.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.07:51:23.26#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:23.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:23.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:23.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:23.26#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:51:23.26#ibcon#first serial, iclass 31, count 0 2006.260.07:51:23.26#ibcon#enter sib2, iclass 31, count 0 2006.260.07:51:23.26#ibcon#flushed, iclass 31, count 0 2006.260.07:51:23.26#ibcon#about to write, iclass 31, count 0 2006.260.07:51:23.26#ibcon#wrote, iclass 31, count 0 2006.260.07:51:23.26#ibcon#about to read 3, iclass 31, count 0 2006.260.07:51:23.27#ibcon#read 3, iclass 31, count 0 2006.260.07:51:23.27#ibcon#about to read 4, iclass 31, count 0 2006.260.07:51:23.27#ibcon#read 4, iclass 31, count 0 2006.260.07:51:23.27#ibcon#about to read 5, iclass 31, count 0 2006.260.07:51:23.27#ibcon#read 5, iclass 31, count 0 2006.260.07:51:23.27#ibcon#about to read 6, iclass 31, count 0 2006.260.07:51:23.27#ibcon#read 6, iclass 31, count 0 2006.260.07:51:23.27#ibcon#end of sib2, iclass 31, count 0 2006.260.07:51:23.27#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:51:23.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:51:23.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:51:23.27#ibcon#*before write, iclass 31, count 0 2006.260.07:51:23.27#ibcon#enter sib2, iclass 31, count 0 2006.260.07:51:23.27#ibcon#flushed, iclass 31, count 0 2006.260.07:51:23.27#ibcon#about to write, iclass 31, count 0 2006.260.07:51:23.27#ibcon#wrote, iclass 31, count 0 2006.260.07:51:23.27#ibcon#about to read 3, iclass 31, count 0 2006.260.07:51:23.31#ibcon#read 3, iclass 31, count 0 2006.260.07:51:23.31#ibcon#about to read 4, iclass 31, count 0 2006.260.07:51:23.31#ibcon#read 4, iclass 31, count 0 2006.260.07:51:23.31#ibcon#about to read 5, iclass 31, count 0 2006.260.07:51:23.31#ibcon#read 5, iclass 31, count 0 2006.260.07:51:23.31#ibcon#about to read 6, iclass 31, count 0 2006.260.07:51:23.31#ibcon#read 6, iclass 31, count 0 2006.260.07:51:23.31#ibcon#end of sib2, iclass 31, count 0 2006.260.07:51:23.31#ibcon#*after write, iclass 31, count 0 2006.260.07:51:23.31#ibcon#*before return 0, iclass 31, count 0 2006.260.07:51:23.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:23.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.07:51:23.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:51:23.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:51:23.32$vc4f8/vb=5,4 2006.260.07:51:23.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.07:51:23.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.07:51:23.32#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:23.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:23.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:23.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:23.36#ibcon#enter wrdev, iclass 33, count 2 2006.260.07:51:23.36#ibcon#first serial, iclass 33, count 2 2006.260.07:51:23.36#ibcon#enter sib2, iclass 33, count 2 2006.260.07:51:23.36#ibcon#flushed, iclass 33, count 2 2006.260.07:51:23.36#ibcon#about to write, iclass 33, count 2 2006.260.07:51:23.36#ibcon#wrote, iclass 33, count 2 2006.260.07:51:23.36#ibcon#about to read 3, iclass 33, count 2 2006.260.07:51:23.38#ibcon#read 3, iclass 33, count 2 2006.260.07:51:23.38#ibcon#about to read 4, iclass 33, count 2 2006.260.07:51:23.38#ibcon#read 4, iclass 33, count 2 2006.260.07:51:23.38#ibcon#about to read 5, iclass 33, count 2 2006.260.07:51:23.38#ibcon#read 5, iclass 33, count 2 2006.260.07:51:23.38#ibcon#about to read 6, iclass 33, count 2 2006.260.07:51:23.38#ibcon#read 6, iclass 33, count 2 2006.260.07:51:23.38#ibcon#end of sib2, iclass 33, count 2 2006.260.07:51:23.38#ibcon#*mode == 0, iclass 33, count 2 2006.260.07:51:23.38#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.07:51:23.38#ibcon#[27=AT05-04\r\n] 2006.260.07:51:23.38#ibcon#*before write, iclass 33, count 2 2006.260.07:51:23.38#ibcon#enter sib2, iclass 33, count 2 2006.260.07:51:23.38#ibcon#flushed, iclass 33, count 2 2006.260.07:51:23.38#ibcon#about to write, iclass 33, count 2 2006.260.07:51:23.38#ibcon#wrote, iclass 33, count 2 2006.260.07:51:23.38#ibcon#about to read 3, iclass 33, count 2 2006.260.07:51:23.41#ibcon#read 3, iclass 33, count 2 2006.260.07:51:23.41#ibcon#about to read 4, iclass 33, count 2 2006.260.07:51:23.41#ibcon#read 4, iclass 33, count 2 2006.260.07:51:23.41#ibcon#about to read 5, iclass 33, count 2 2006.260.07:51:23.41#ibcon#read 5, iclass 33, count 2 2006.260.07:51:23.41#ibcon#about to read 6, iclass 33, count 2 2006.260.07:51:23.41#ibcon#read 6, iclass 33, count 2 2006.260.07:51:23.41#ibcon#end of sib2, iclass 33, count 2 2006.260.07:51:23.41#ibcon#*after write, iclass 33, count 2 2006.260.07:51:23.41#ibcon#*before return 0, iclass 33, count 2 2006.260.07:51:23.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:23.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.07:51:23.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.07:51:23.41#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:23.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:23.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:23.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:23.53#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:51:23.53#ibcon#first serial, iclass 33, count 0 2006.260.07:51:23.53#ibcon#enter sib2, iclass 33, count 0 2006.260.07:51:23.53#ibcon#flushed, iclass 33, count 0 2006.260.07:51:23.53#ibcon#about to write, iclass 33, count 0 2006.260.07:51:23.53#ibcon#wrote, iclass 33, count 0 2006.260.07:51:23.53#ibcon#about to read 3, iclass 33, count 0 2006.260.07:51:23.55#ibcon#read 3, iclass 33, count 0 2006.260.07:51:23.55#ibcon#about to read 4, iclass 33, count 0 2006.260.07:51:23.55#ibcon#read 4, iclass 33, count 0 2006.260.07:51:23.55#ibcon#about to read 5, iclass 33, count 0 2006.260.07:51:23.55#ibcon#read 5, iclass 33, count 0 2006.260.07:51:23.55#ibcon#about to read 6, iclass 33, count 0 2006.260.07:51:23.55#ibcon#read 6, iclass 33, count 0 2006.260.07:51:23.55#ibcon#end of sib2, iclass 33, count 0 2006.260.07:51:23.55#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:51:23.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:51:23.55#ibcon#[27=USB\r\n] 2006.260.07:51:23.55#ibcon#*before write, iclass 33, count 0 2006.260.07:51:23.55#ibcon#enter sib2, iclass 33, count 0 2006.260.07:51:23.55#ibcon#flushed, iclass 33, count 0 2006.260.07:51:23.55#ibcon#about to write, iclass 33, count 0 2006.260.07:51:23.55#ibcon#wrote, iclass 33, count 0 2006.260.07:51:23.55#ibcon#about to read 3, iclass 33, count 0 2006.260.07:51:23.58#ibcon#read 3, iclass 33, count 0 2006.260.07:51:23.58#ibcon#about to read 4, iclass 33, count 0 2006.260.07:51:23.58#ibcon#read 4, iclass 33, count 0 2006.260.07:51:23.58#ibcon#about to read 5, iclass 33, count 0 2006.260.07:51:23.58#ibcon#read 5, iclass 33, count 0 2006.260.07:51:23.58#ibcon#about to read 6, iclass 33, count 0 2006.260.07:51:23.58#ibcon#read 6, iclass 33, count 0 2006.260.07:51:23.58#ibcon#end of sib2, iclass 33, count 0 2006.260.07:51:23.58#ibcon#*after write, iclass 33, count 0 2006.260.07:51:23.58#ibcon#*before return 0, iclass 33, count 0 2006.260.07:51:23.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:23.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.07:51:23.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:51:23.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:51:23.59$vc4f8/vblo=6,752.99 2006.260.07:51:23.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.07:51:23.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.07:51:23.59#ibcon#ireg 17 cls_cnt 0 2006.260.07:51:23.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:23.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:23.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:23.59#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:51:23.59#ibcon#first serial, iclass 35, count 0 2006.260.07:51:23.59#ibcon#enter sib2, iclass 35, count 0 2006.260.07:51:23.59#ibcon#flushed, iclass 35, count 0 2006.260.07:51:23.59#ibcon#about to write, iclass 35, count 0 2006.260.07:51:23.59#ibcon#wrote, iclass 35, count 0 2006.260.07:51:23.59#ibcon#about to read 3, iclass 35, count 0 2006.260.07:51:23.61#ibcon#read 3, iclass 35, count 0 2006.260.07:51:23.61#ibcon#about to read 4, iclass 35, count 0 2006.260.07:51:23.61#ibcon#read 4, iclass 35, count 0 2006.260.07:51:23.61#ibcon#about to read 5, iclass 35, count 0 2006.260.07:51:23.61#ibcon#read 5, iclass 35, count 0 2006.260.07:51:23.61#ibcon#about to read 6, iclass 35, count 0 2006.260.07:51:23.61#ibcon#read 6, iclass 35, count 0 2006.260.07:51:23.61#ibcon#end of sib2, iclass 35, count 0 2006.260.07:51:23.61#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:51:23.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:51:23.61#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:51:23.61#ibcon#*before write, iclass 35, count 0 2006.260.07:51:23.61#ibcon#enter sib2, iclass 35, count 0 2006.260.07:51:23.61#ibcon#flushed, iclass 35, count 0 2006.260.07:51:23.61#ibcon#about to write, iclass 35, count 0 2006.260.07:51:23.61#ibcon#wrote, iclass 35, count 0 2006.260.07:51:23.61#ibcon#about to read 3, iclass 35, count 0 2006.260.07:51:23.65#ibcon#read 3, iclass 35, count 0 2006.260.07:51:23.65#ibcon#about to read 4, iclass 35, count 0 2006.260.07:51:23.65#ibcon#read 4, iclass 35, count 0 2006.260.07:51:23.65#ibcon#about to read 5, iclass 35, count 0 2006.260.07:51:23.65#ibcon#read 5, iclass 35, count 0 2006.260.07:51:23.65#ibcon#about to read 6, iclass 35, count 0 2006.260.07:51:23.65#ibcon#read 6, iclass 35, count 0 2006.260.07:51:23.65#ibcon#end of sib2, iclass 35, count 0 2006.260.07:51:23.65#ibcon#*after write, iclass 35, count 0 2006.260.07:51:23.65#ibcon#*before return 0, iclass 35, count 0 2006.260.07:51:23.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:23.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.07:51:23.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:51:23.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:51:23.66$vc4f8/vb=6,4 2006.260.07:51:23.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.07:51:23.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.07:51:23.66#ibcon#ireg 11 cls_cnt 2 2006.260.07:51:23.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:23.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:23.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:23.69#ibcon#enter wrdev, iclass 37, count 2 2006.260.07:51:23.69#ibcon#first serial, iclass 37, count 2 2006.260.07:51:23.69#ibcon#enter sib2, iclass 37, count 2 2006.260.07:51:23.69#ibcon#flushed, iclass 37, count 2 2006.260.07:51:23.69#ibcon#about to write, iclass 37, count 2 2006.260.07:51:23.69#ibcon#wrote, iclass 37, count 2 2006.260.07:51:23.69#ibcon#about to read 3, iclass 37, count 2 2006.260.07:51:23.71#ibcon#read 3, iclass 37, count 2 2006.260.07:51:23.71#ibcon#about to read 4, iclass 37, count 2 2006.260.07:51:23.71#ibcon#read 4, iclass 37, count 2 2006.260.07:51:23.71#ibcon#about to read 5, iclass 37, count 2 2006.260.07:51:23.71#ibcon#read 5, iclass 37, count 2 2006.260.07:51:23.71#ibcon#about to read 6, iclass 37, count 2 2006.260.07:51:23.71#ibcon#read 6, iclass 37, count 2 2006.260.07:51:23.71#ibcon#end of sib2, iclass 37, count 2 2006.260.07:51:23.71#ibcon#*mode == 0, iclass 37, count 2 2006.260.07:51:23.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.07:51:23.71#ibcon#[27=AT06-04\r\n] 2006.260.07:51:23.71#ibcon#*before write, iclass 37, count 2 2006.260.07:51:23.71#ibcon#enter sib2, iclass 37, count 2 2006.260.07:51:23.71#ibcon#flushed, iclass 37, count 2 2006.260.07:51:23.71#ibcon#about to write, iclass 37, count 2 2006.260.07:51:23.71#ibcon#wrote, iclass 37, count 2 2006.260.07:51:23.71#ibcon#about to read 3, iclass 37, count 2 2006.260.07:51:23.74#ibcon#read 3, iclass 37, count 2 2006.260.07:51:23.74#ibcon#about to read 4, iclass 37, count 2 2006.260.07:51:23.74#ibcon#read 4, iclass 37, count 2 2006.260.07:51:23.74#ibcon#about to read 5, iclass 37, count 2 2006.260.07:51:23.74#ibcon#read 5, iclass 37, count 2 2006.260.07:51:23.74#ibcon#about to read 6, iclass 37, count 2 2006.260.07:51:23.74#ibcon#read 6, iclass 37, count 2 2006.260.07:51:23.74#ibcon#end of sib2, iclass 37, count 2 2006.260.07:51:23.74#ibcon#*after write, iclass 37, count 2 2006.260.07:51:23.74#ibcon#*before return 0, iclass 37, count 2 2006.260.07:51:23.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:23.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.07:51:23.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.07:51:23.74#ibcon#ireg 7 cls_cnt 0 2006.260.07:51:23.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:23.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:23.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:23.86#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:51:23.86#ibcon#first serial, iclass 37, count 0 2006.260.07:51:23.86#ibcon#enter sib2, iclass 37, count 0 2006.260.07:51:23.86#ibcon#flushed, iclass 37, count 0 2006.260.07:51:23.86#ibcon#about to write, iclass 37, count 0 2006.260.07:51:23.86#ibcon#wrote, iclass 37, count 0 2006.260.07:51:23.86#ibcon#about to read 3, iclass 37, count 0 2006.260.07:51:23.88#ibcon#read 3, iclass 37, count 0 2006.260.07:51:23.88#ibcon#about to read 4, iclass 37, count 0 2006.260.07:51:23.88#ibcon#read 4, iclass 37, count 0 2006.260.07:51:23.88#ibcon#about to read 5, iclass 37, count 0 2006.260.07:51:23.88#ibcon#read 5, iclass 37, count 0 2006.260.07:51:23.88#ibcon#about to read 6, iclass 37, count 0 2006.260.07:51:23.88#ibcon#read 6, iclass 37, count 0 2006.260.07:51:23.88#ibcon#end of sib2, iclass 37, count 0 2006.260.07:51:23.88#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:51:23.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:51:23.88#ibcon#[27=USB\r\n] 2006.260.07:51:23.88#ibcon#*before write, iclass 37, count 0 2006.260.07:51:23.88#ibcon#enter sib2, iclass 37, count 0 2006.260.07:51:23.88#ibcon#flushed, iclass 37, count 0 2006.260.07:51:23.88#ibcon#about to write, iclass 37, count 0 2006.260.07:51:23.88#ibcon#wrote, iclass 37, count 0 2006.260.07:51:23.88#ibcon#about to read 3, iclass 37, count 0 2006.260.07:51:23.91#ibcon#read 3, iclass 37, count 0 2006.260.07:51:23.91#ibcon#about to read 4, iclass 37, count 0 2006.260.07:51:23.91#ibcon#read 4, iclass 37, count 0 2006.260.07:51:23.91#ibcon#about to read 5, iclass 37, count 0 2006.260.07:51:23.91#ibcon#read 5, iclass 37, count 0 2006.260.07:51:23.91#ibcon#about to read 6, iclass 37, count 0 2006.260.07:51:23.91#ibcon#read 6, iclass 37, count 0 2006.260.07:51:23.91#ibcon#end of sib2, iclass 37, count 0 2006.260.07:51:23.91#ibcon#*after write, iclass 37, count 0 2006.260.07:51:23.91#ibcon#*before return 0, iclass 37, count 0 2006.260.07:51:23.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:23.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.07:51:23.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:51:23.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:51:23.92$vc4f8/vabw=wide 2006.260.07:51:23.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.07:51:23.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.07:51:23.92#ibcon#ireg 8 cls_cnt 0 2006.260.07:51:23.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:23.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:23.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:23.92#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:51:23.92#ibcon#first serial, iclass 39, count 0 2006.260.07:51:23.92#ibcon#enter sib2, iclass 39, count 0 2006.260.07:51:23.92#ibcon#flushed, iclass 39, count 0 2006.260.07:51:23.92#ibcon#about to write, iclass 39, count 0 2006.260.07:51:23.92#ibcon#wrote, iclass 39, count 0 2006.260.07:51:23.92#ibcon#about to read 3, iclass 39, count 0 2006.260.07:51:23.93#ibcon#read 3, iclass 39, count 0 2006.260.07:51:23.93#ibcon#about to read 4, iclass 39, count 0 2006.260.07:51:23.93#ibcon#read 4, iclass 39, count 0 2006.260.07:51:23.93#ibcon#about to read 5, iclass 39, count 0 2006.260.07:51:23.93#ibcon#read 5, iclass 39, count 0 2006.260.07:51:23.93#ibcon#about to read 6, iclass 39, count 0 2006.260.07:51:23.93#ibcon#read 6, iclass 39, count 0 2006.260.07:51:23.93#ibcon#end of sib2, iclass 39, count 0 2006.260.07:51:23.93#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:51:23.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:51:23.93#ibcon#[25=BW32\r\n] 2006.260.07:51:23.93#ibcon#*before write, iclass 39, count 0 2006.260.07:51:23.93#ibcon#enter sib2, iclass 39, count 0 2006.260.07:51:23.93#ibcon#flushed, iclass 39, count 0 2006.260.07:51:23.93#ibcon#about to write, iclass 39, count 0 2006.260.07:51:23.93#ibcon#wrote, iclass 39, count 0 2006.260.07:51:23.93#ibcon#about to read 3, iclass 39, count 0 2006.260.07:51:23.96#ibcon#read 3, iclass 39, count 0 2006.260.07:51:23.96#ibcon#about to read 4, iclass 39, count 0 2006.260.07:51:23.96#ibcon#read 4, iclass 39, count 0 2006.260.07:51:23.96#ibcon#about to read 5, iclass 39, count 0 2006.260.07:51:23.96#ibcon#read 5, iclass 39, count 0 2006.260.07:51:23.96#ibcon#about to read 6, iclass 39, count 0 2006.260.07:51:23.96#ibcon#read 6, iclass 39, count 0 2006.260.07:51:23.96#ibcon#end of sib2, iclass 39, count 0 2006.260.07:51:23.96#ibcon#*after write, iclass 39, count 0 2006.260.07:51:23.96#ibcon#*before return 0, iclass 39, count 0 2006.260.07:51:23.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:23.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.07:51:23.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:51:23.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:51:23.97$vc4f8/vbbw=wide 2006.260.07:51:23.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:51:23.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:51:23.97#ibcon#ireg 8 cls_cnt 0 2006.260.07:51:23.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:51:24.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:51:24.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:51:24.02#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:51:24.02#ibcon#first serial, iclass 3, count 0 2006.260.07:51:24.02#ibcon#enter sib2, iclass 3, count 0 2006.260.07:51:24.02#ibcon#flushed, iclass 3, count 0 2006.260.07:51:24.02#ibcon#about to write, iclass 3, count 0 2006.260.07:51:24.02#ibcon#wrote, iclass 3, count 0 2006.260.07:51:24.02#ibcon#about to read 3, iclass 3, count 0 2006.260.07:51:24.04#ibcon#read 3, iclass 3, count 0 2006.260.07:51:24.04#ibcon#about to read 4, iclass 3, count 0 2006.260.07:51:24.04#ibcon#read 4, iclass 3, count 0 2006.260.07:51:24.04#ibcon#about to read 5, iclass 3, count 0 2006.260.07:51:24.04#ibcon#read 5, iclass 3, count 0 2006.260.07:51:24.04#ibcon#about to read 6, iclass 3, count 0 2006.260.07:51:24.04#ibcon#read 6, iclass 3, count 0 2006.260.07:51:24.04#ibcon#end of sib2, iclass 3, count 0 2006.260.07:51:24.04#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:51:24.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:51:24.04#ibcon#[27=BW32\r\n] 2006.260.07:51:24.04#ibcon#*before write, iclass 3, count 0 2006.260.07:51:24.04#ibcon#enter sib2, iclass 3, count 0 2006.260.07:51:24.04#ibcon#flushed, iclass 3, count 0 2006.260.07:51:24.04#ibcon#about to write, iclass 3, count 0 2006.260.07:51:24.04#ibcon#wrote, iclass 3, count 0 2006.260.07:51:24.04#ibcon#about to read 3, iclass 3, count 0 2006.260.07:51:24.07#ibcon#read 3, iclass 3, count 0 2006.260.07:51:24.07#ibcon#about to read 4, iclass 3, count 0 2006.260.07:51:24.07#ibcon#read 4, iclass 3, count 0 2006.260.07:51:24.07#ibcon#about to read 5, iclass 3, count 0 2006.260.07:51:24.07#ibcon#read 5, iclass 3, count 0 2006.260.07:51:24.07#ibcon#about to read 6, iclass 3, count 0 2006.260.07:51:24.07#ibcon#read 6, iclass 3, count 0 2006.260.07:51:24.07#ibcon#end of sib2, iclass 3, count 0 2006.260.07:51:24.07#ibcon#*after write, iclass 3, count 0 2006.260.07:51:24.07#ibcon#*before return 0, iclass 3, count 0 2006.260.07:51:24.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:51:24.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:51:24.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:51:24.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:51:24.08$4f8m12a/ifd4f 2006.260.07:51:24.08$ifd4f/lo= 2006.260.07:51:24.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:51:24.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:51:24.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:51:24.08$ifd4f/patch= 2006.260.07:51:24.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:51:24.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:51:24.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:51:24.08$4f8m12a/"form=m,16.000,1:2 2006.260.07:51:24.08$4f8m12a/"tpicd 2006.260.07:51:24.08$4f8m12a/echo=off 2006.260.07:51:24.08$4f8m12a/xlog=off 2006.260.07:51:24.08:!2006.260.07:51:50 2006.260.07:51:36.14#trakl#Source acquired 2006.260.07:51:38.15#flagr#flagr/antenna,acquired 2006.260.07:51:50.02:preob 2006.260.07:51:51.14/onsource/TRACKING 2006.260.07:51:51.14:!2006.260.07:52:00 2006.260.07:52:00.01:data_valid=on 2006.260.07:52:00.02:midob 2006.260.07:52:01.14/onsource/TRACKING 2006.260.07:52:01.14/wx/22.95,1010.4,88 2006.260.07:52:01.19/cable/+6.4580E-03 2006.260.07:52:02.28/va/01,08,usb,yes,32,34 2006.260.07:52:02.28/va/02,07,usb,yes,32,34 2006.260.07:52:02.28/va/03,08,usb,yes,24,25 2006.260.07:52:02.28/va/04,07,usb,yes,33,36 2006.260.07:52:02.28/va/05,07,usb,yes,37,39 2006.260.07:52:02.28/va/06,06,usb,yes,36,36 2006.260.07:52:02.28/va/07,06,usb,yes,37,36 2006.260.07:52:02.28/va/08,06,usb,yes,39,38 2006.260.07:52:02.51/valo/01,532.99,yes,locked 2006.260.07:52:02.51/valo/02,572.99,yes,locked 2006.260.07:52:02.51/valo/03,672.99,yes,locked 2006.260.07:52:02.51/valo/04,832.99,yes,locked 2006.260.07:52:02.51/valo/05,652.99,yes,locked 2006.260.07:52:02.51/valo/06,772.99,yes,locked 2006.260.07:52:02.51/valo/07,832.99,yes,locked 2006.260.07:52:02.51/valo/08,852.99,yes,locked 2006.260.07:52:03.60/vb/01,04,usb,yes,30,29 2006.260.07:52:03.60/vb/02,05,usb,yes,28,29 2006.260.07:52:03.60/vb/03,04,usb,yes,28,32 2006.260.07:52:03.60/vb/04,05,usb,yes,26,26 2006.260.07:52:03.60/vb/05,04,usb,yes,28,32 2006.260.07:52:03.60/vb/06,04,usb,yes,29,32 2006.260.07:52:03.60/vb/07,04,usb,yes,31,31 2006.260.07:52:03.60/vb/08,04,usb,yes,28,32 2006.260.07:52:03.84/vblo/01,632.99,yes,locked 2006.260.07:52:03.84/vblo/02,640.99,yes,locked 2006.260.07:52:03.84/vblo/03,656.99,yes,locked 2006.260.07:52:03.84/vblo/04,712.99,yes,locked 2006.260.07:52:03.84/vblo/05,744.99,yes,locked 2006.260.07:52:03.84/vblo/06,752.99,yes,locked 2006.260.07:52:03.84/vblo/07,734.99,yes,locked 2006.260.07:52:03.84/vblo/08,744.99,yes,locked 2006.260.07:52:03.99/vabw/8 2006.260.07:52:04.14/vbbw/8 2006.260.07:52:04.23/xfe/off,on,15.0 2006.260.07:52:04.61/ifatt/23,28,28,28 2006.260.07:52:05.07/fmout-gps/S +4.50E-07 2006.260.07:52:05.12:!2006.260.07:53:00 2006.260.07:53:00.01:data_valid=off 2006.260.07:53:00.02:postob 2006.260.07:53:00.20/cable/+6.4568E-03 2006.260.07:53:00.21/wx/22.94,1010.4,88 2006.260.07:53:01.08/fmout-gps/S +4.50E-07 2006.260.07:53:01.09:scan_name=260-0755,k06260,60 2006.260.07:53:01.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.260.07:53:02.13#flagr#flagr/antenna,new-source 2006.260.07:53:02.14:checkk5 2006.260.07:53:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:53:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:53:03.69/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:53:04.10/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:53:04.52/chk_obsdata//k5ts1/T2600752??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:53:04.92/chk_obsdata//k5ts2/T2600752??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:53:05.33/chk_obsdata//k5ts3/T2600752??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:53:05.76/chk_obsdata//k5ts4/T2600752??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:53:06.50/k5log//k5ts1_log_newline 2006.260.07:53:07.41/k5log//k5ts2_log_newline 2006.260.07:53:08.25/k5log//k5ts3_log_newline 2006.260.07:53:09.05/k5log//k5ts4_log_newline 2006.260.07:53:09.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:53:09.11:4f8m12a=2 2006.260.07:53:09.11$4f8m12a/echo=on 2006.260.07:53:09.11$4f8m12a/pcalon 2006.260.07:53:09.11$pcalon/"no phase cal control is implemented here 2006.260.07:53:09.11$4f8m12a/"tpicd=stop 2006.260.07:53:09.11$4f8m12a/vc4f8 2006.260.07:53:09.11$vc4f8/valo=1,532.99 2006.260.07:53:09.11#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:53:09.11#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:53:09.11#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:09.11#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:09.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:09.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:09.11#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:53:09.11#ibcon#first serial, iclass 12, count 0 2006.260.07:53:09.11#ibcon#enter sib2, iclass 12, count 0 2006.260.07:53:09.11#ibcon#flushed, iclass 12, count 0 2006.260.07:53:09.11#ibcon#about to write, iclass 12, count 0 2006.260.07:53:09.11#ibcon#wrote, iclass 12, count 0 2006.260.07:53:09.11#ibcon#about to read 3, iclass 12, count 0 2006.260.07:53:09.13#ibcon#read 3, iclass 12, count 0 2006.260.07:53:09.13#ibcon#about to read 4, iclass 12, count 0 2006.260.07:53:09.13#ibcon#read 4, iclass 12, count 0 2006.260.07:53:09.13#ibcon#about to read 5, iclass 12, count 0 2006.260.07:53:09.13#ibcon#read 5, iclass 12, count 0 2006.260.07:53:09.13#ibcon#about to read 6, iclass 12, count 0 2006.260.07:53:09.13#ibcon#read 6, iclass 12, count 0 2006.260.07:53:09.13#ibcon#end of sib2, iclass 12, count 0 2006.260.07:53:09.13#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:53:09.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:53:09.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:53:09.13#ibcon#*before write, iclass 12, count 0 2006.260.07:53:09.13#ibcon#enter sib2, iclass 12, count 0 2006.260.07:53:09.13#ibcon#flushed, iclass 12, count 0 2006.260.07:53:09.13#ibcon#about to write, iclass 12, count 0 2006.260.07:53:09.13#ibcon#wrote, iclass 12, count 0 2006.260.07:53:09.13#ibcon#about to read 3, iclass 12, count 0 2006.260.07:53:09.18#ibcon#read 3, iclass 12, count 0 2006.260.07:53:09.18#ibcon#about to read 4, iclass 12, count 0 2006.260.07:53:09.18#ibcon#read 4, iclass 12, count 0 2006.260.07:53:09.18#ibcon#about to read 5, iclass 12, count 0 2006.260.07:53:09.18#ibcon#read 5, iclass 12, count 0 2006.260.07:53:09.18#ibcon#about to read 6, iclass 12, count 0 2006.260.07:53:09.18#ibcon#read 6, iclass 12, count 0 2006.260.07:53:09.18#ibcon#end of sib2, iclass 12, count 0 2006.260.07:53:09.18#ibcon#*after write, iclass 12, count 0 2006.260.07:53:09.18#ibcon#*before return 0, iclass 12, count 0 2006.260.07:53:09.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:09.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:09.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:53:09.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:53:09.18$vc4f8/va=1,8 2006.260.07:53:09.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:53:09.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:53:09.18#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:09.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:09.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:09.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:09.19#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:53:09.19#ibcon#first serial, iclass 14, count 2 2006.260.07:53:09.19#ibcon#enter sib2, iclass 14, count 2 2006.260.07:53:09.19#ibcon#flushed, iclass 14, count 2 2006.260.07:53:09.19#ibcon#about to write, iclass 14, count 2 2006.260.07:53:09.19#ibcon#wrote, iclass 14, count 2 2006.260.07:53:09.19#ibcon#about to read 3, iclass 14, count 2 2006.260.07:53:09.21#ibcon#read 3, iclass 14, count 2 2006.260.07:53:09.21#ibcon#about to read 4, iclass 14, count 2 2006.260.07:53:09.21#ibcon#read 4, iclass 14, count 2 2006.260.07:53:09.21#ibcon#about to read 5, iclass 14, count 2 2006.260.07:53:09.21#ibcon#read 5, iclass 14, count 2 2006.260.07:53:09.21#ibcon#about to read 6, iclass 14, count 2 2006.260.07:53:09.21#ibcon#read 6, iclass 14, count 2 2006.260.07:53:09.21#ibcon#end of sib2, iclass 14, count 2 2006.260.07:53:09.21#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:53:09.21#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:53:09.21#ibcon#[25=AT01-08\r\n] 2006.260.07:53:09.21#ibcon#*before write, iclass 14, count 2 2006.260.07:53:09.21#ibcon#enter sib2, iclass 14, count 2 2006.260.07:53:09.21#ibcon#flushed, iclass 14, count 2 2006.260.07:53:09.21#ibcon#about to write, iclass 14, count 2 2006.260.07:53:09.21#ibcon#wrote, iclass 14, count 2 2006.260.07:53:09.21#ibcon#about to read 3, iclass 14, count 2 2006.260.07:53:09.24#ibcon#read 3, iclass 14, count 2 2006.260.07:53:09.24#ibcon#about to read 4, iclass 14, count 2 2006.260.07:53:09.24#ibcon#read 4, iclass 14, count 2 2006.260.07:53:09.24#ibcon#about to read 5, iclass 14, count 2 2006.260.07:53:09.24#ibcon#read 5, iclass 14, count 2 2006.260.07:53:09.24#ibcon#about to read 6, iclass 14, count 2 2006.260.07:53:09.24#ibcon#read 6, iclass 14, count 2 2006.260.07:53:09.24#ibcon#end of sib2, iclass 14, count 2 2006.260.07:53:09.24#ibcon#*after write, iclass 14, count 2 2006.260.07:53:09.24#ibcon#*before return 0, iclass 14, count 2 2006.260.07:53:09.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:09.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:09.24#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:53:09.24#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:09.24#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:09.36#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:09.36#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:09.36#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:53:09.36#ibcon#first serial, iclass 14, count 0 2006.260.07:53:09.36#ibcon#enter sib2, iclass 14, count 0 2006.260.07:53:09.36#ibcon#flushed, iclass 14, count 0 2006.260.07:53:09.36#ibcon#about to write, iclass 14, count 0 2006.260.07:53:09.36#ibcon#wrote, iclass 14, count 0 2006.260.07:53:09.36#ibcon#about to read 3, iclass 14, count 0 2006.260.07:53:09.38#ibcon#read 3, iclass 14, count 0 2006.260.07:53:09.38#ibcon#about to read 4, iclass 14, count 0 2006.260.07:53:09.38#ibcon#read 4, iclass 14, count 0 2006.260.07:53:09.38#ibcon#about to read 5, iclass 14, count 0 2006.260.07:53:09.38#ibcon#read 5, iclass 14, count 0 2006.260.07:53:09.38#ibcon#about to read 6, iclass 14, count 0 2006.260.07:53:09.38#ibcon#read 6, iclass 14, count 0 2006.260.07:53:09.38#ibcon#end of sib2, iclass 14, count 0 2006.260.07:53:09.38#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:53:09.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:53:09.38#ibcon#[25=USB\r\n] 2006.260.07:53:09.38#ibcon#*before write, iclass 14, count 0 2006.260.07:53:09.38#ibcon#enter sib2, iclass 14, count 0 2006.260.07:53:09.38#ibcon#flushed, iclass 14, count 0 2006.260.07:53:09.38#ibcon#about to write, iclass 14, count 0 2006.260.07:53:09.38#ibcon#wrote, iclass 14, count 0 2006.260.07:53:09.38#ibcon#about to read 3, iclass 14, count 0 2006.260.07:53:09.41#ibcon#read 3, iclass 14, count 0 2006.260.07:53:09.41#ibcon#about to read 4, iclass 14, count 0 2006.260.07:53:09.41#ibcon#read 4, iclass 14, count 0 2006.260.07:53:09.41#ibcon#about to read 5, iclass 14, count 0 2006.260.07:53:09.41#ibcon#read 5, iclass 14, count 0 2006.260.07:53:09.41#ibcon#about to read 6, iclass 14, count 0 2006.260.07:53:09.41#ibcon#read 6, iclass 14, count 0 2006.260.07:53:09.41#ibcon#end of sib2, iclass 14, count 0 2006.260.07:53:09.41#ibcon#*after write, iclass 14, count 0 2006.260.07:53:09.41#ibcon#*before return 0, iclass 14, count 0 2006.260.07:53:09.41#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:09.41#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:09.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:53:09.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:53:09.41$vc4f8/valo=2,572.99 2006.260.07:53:09.41#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:53:09.41#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:53:09.41#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:09.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:09.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:09.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:09.41#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:53:09.41#ibcon#first serial, iclass 16, count 0 2006.260.07:53:09.41#ibcon#enter sib2, iclass 16, count 0 2006.260.07:53:09.41#ibcon#flushed, iclass 16, count 0 2006.260.07:53:09.41#ibcon#about to write, iclass 16, count 0 2006.260.07:53:09.41#ibcon#wrote, iclass 16, count 0 2006.260.07:53:09.41#ibcon#about to read 3, iclass 16, count 0 2006.260.07:53:09.43#ibcon#read 3, iclass 16, count 0 2006.260.07:53:09.43#ibcon#about to read 4, iclass 16, count 0 2006.260.07:53:09.43#ibcon#read 4, iclass 16, count 0 2006.260.07:53:09.43#ibcon#about to read 5, iclass 16, count 0 2006.260.07:53:09.43#ibcon#read 5, iclass 16, count 0 2006.260.07:53:09.43#ibcon#about to read 6, iclass 16, count 0 2006.260.07:53:09.43#ibcon#read 6, iclass 16, count 0 2006.260.07:53:09.43#ibcon#end of sib2, iclass 16, count 0 2006.260.07:53:09.43#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:53:09.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:53:09.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:53:09.43#ibcon#*before write, iclass 16, count 0 2006.260.07:53:09.43#ibcon#enter sib2, iclass 16, count 0 2006.260.07:53:09.43#ibcon#flushed, iclass 16, count 0 2006.260.07:53:09.43#ibcon#about to write, iclass 16, count 0 2006.260.07:53:09.43#ibcon#wrote, iclass 16, count 0 2006.260.07:53:09.43#ibcon#about to read 3, iclass 16, count 0 2006.260.07:53:09.48#ibcon#read 3, iclass 16, count 0 2006.260.07:53:09.48#ibcon#about to read 4, iclass 16, count 0 2006.260.07:53:09.48#ibcon#read 4, iclass 16, count 0 2006.260.07:53:09.48#ibcon#about to read 5, iclass 16, count 0 2006.260.07:53:09.48#ibcon#read 5, iclass 16, count 0 2006.260.07:53:09.48#ibcon#about to read 6, iclass 16, count 0 2006.260.07:53:09.48#ibcon#read 6, iclass 16, count 0 2006.260.07:53:09.48#ibcon#end of sib2, iclass 16, count 0 2006.260.07:53:09.48#ibcon#*after write, iclass 16, count 0 2006.260.07:53:09.48#ibcon#*before return 0, iclass 16, count 0 2006.260.07:53:09.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:09.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:09.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:53:09.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:53:09.48$vc4f8/va=2,7 2006.260.07:53:09.48#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:53:09.48#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:53:09.48#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:09.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:09.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:09.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:09.52#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:53:09.52#ibcon#first serial, iclass 18, count 2 2006.260.07:53:09.52#ibcon#enter sib2, iclass 18, count 2 2006.260.07:53:09.52#ibcon#flushed, iclass 18, count 2 2006.260.07:53:09.52#ibcon#about to write, iclass 18, count 2 2006.260.07:53:09.52#ibcon#wrote, iclass 18, count 2 2006.260.07:53:09.52#ibcon#about to read 3, iclass 18, count 2 2006.260.07:53:09.55#ibcon#read 3, iclass 18, count 2 2006.260.07:53:09.55#ibcon#about to read 4, iclass 18, count 2 2006.260.07:53:09.55#ibcon#read 4, iclass 18, count 2 2006.260.07:53:09.55#ibcon#about to read 5, iclass 18, count 2 2006.260.07:53:09.55#ibcon#read 5, iclass 18, count 2 2006.260.07:53:09.55#ibcon#about to read 6, iclass 18, count 2 2006.260.07:53:09.55#ibcon#read 6, iclass 18, count 2 2006.260.07:53:09.55#ibcon#end of sib2, iclass 18, count 2 2006.260.07:53:09.55#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:53:09.55#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:53:09.55#ibcon#[25=AT02-07\r\n] 2006.260.07:53:09.55#ibcon#*before write, iclass 18, count 2 2006.260.07:53:09.55#ibcon#enter sib2, iclass 18, count 2 2006.260.07:53:09.55#ibcon#flushed, iclass 18, count 2 2006.260.07:53:09.55#ibcon#about to write, iclass 18, count 2 2006.260.07:53:09.55#ibcon#wrote, iclass 18, count 2 2006.260.07:53:09.55#ibcon#about to read 3, iclass 18, count 2 2006.260.07:53:09.58#ibcon#read 3, iclass 18, count 2 2006.260.07:53:09.58#ibcon#about to read 4, iclass 18, count 2 2006.260.07:53:09.58#ibcon#read 4, iclass 18, count 2 2006.260.07:53:09.58#ibcon#about to read 5, iclass 18, count 2 2006.260.07:53:09.58#ibcon#read 5, iclass 18, count 2 2006.260.07:53:09.58#ibcon#about to read 6, iclass 18, count 2 2006.260.07:53:09.58#ibcon#read 6, iclass 18, count 2 2006.260.07:53:09.58#ibcon#end of sib2, iclass 18, count 2 2006.260.07:53:09.58#ibcon#*after write, iclass 18, count 2 2006.260.07:53:09.58#ibcon#*before return 0, iclass 18, count 2 2006.260.07:53:09.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:09.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:09.58#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:53:09.58#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:09.58#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:09.70#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:09.70#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:09.70#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:53:09.70#ibcon#first serial, iclass 18, count 0 2006.260.07:53:09.70#ibcon#enter sib2, iclass 18, count 0 2006.260.07:53:09.70#ibcon#flushed, iclass 18, count 0 2006.260.07:53:09.70#ibcon#about to write, iclass 18, count 0 2006.260.07:53:09.70#ibcon#wrote, iclass 18, count 0 2006.260.07:53:09.70#ibcon#about to read 3, iclass 18, count 0 2006.260.07:53:09.72#ibcon#read 3, iclass 18, count 0 2006.260.07:53:09.72#ibcon#about to read 4, iclass 18, count 0 2006.260.07:53:09.72#ibcon#read 4, iclass 18, count 0 2006.260.07:53:09.72#ibcon#about to read 5, iclass 18, count 0 2006.260.07:53:09.72#ibcon#read 5, iclass 18, count 0 2006.260.07:53:09.72#ibcon#about to read 6, iclass 18, count 0 2006.260.07:53:09.72#ibcon#read 6, iclass 18, count 0 2006.260.07:53:09.72#ibcon#end of sib2, iclass 18, count 0 2006.260.07:53:09.72#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:53:09.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:53:09.72#ibcon#[25=USB\r\n] 2006.260.07:53:09.72#ibcon#*before write, iclass 18, count 0 2006.260.07:53:09.72#ibcon#enter sib2, iclass 18, count 0 2006.260.07:53:09.72#ibcon#flushed, iclass 18, count 0 2006.260.07:53:09.72#ibcon#about to write, iclass 18, count 0 2006.260.07:53:09.72#ibcon#wrote, iclass 18, count 0 2006.260.07:53:09.72#ibcon#about to read 3, iclass 18, count 0 2006.260.07:53:09.75#ibcon#read 3, iclass 18, count 0 2006.260.07:53:09.75#ibcon#about to read 4, iclass 18, count 0 2006.260.07:53:09.75#ibcon#read 4, iclass 18, count 0 2006.260.07:53:09.75#ibcon#about to read 5, iclass 18, count 0 2006.260.07:53:09.75#ibcon#read 5, iclass 18, count 0 2006.260.07:53:09.75#ibcon#about to read 6, iclass 18, count 0 2006.260.07:53:09.75#ibcon#read 6, iclass 18, count 0 2006.260.07:53:09.75#ibcon#end of sib2, iclass 18, count 0 2006.260.07:53:09.75#ibcon#*after write, iclass 18, count 0 2006.260.07:53:09.75#ibcon#*before return 0, iclass 18, count 0 2006.260.07:53:09.75#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:09.75#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:09.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:53:09.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:53:09.75$vc4f8/valo=3,672.99 2006.260.07:53:09.75#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:53:09.75#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:53:09.75#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:09.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:09.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:09.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:09.75#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:53:09.75#ibcon#first serial, iclass 20, count 0 2006.260.07:53:09.75#ibcon#enter sib2, iclass 20, count 0 2006.260.07:53:09.75#ibcon#flushed, iclass 20, count 0 2006.260.07:53:09.75#ibcon#about to write, iclass 20, count 0 2006.260.07:53:09.75#ibcon#wrote, iclass 20, count 0 2006.260.07:53:09.75#ibcon#about to read 3, iclass 20, count 0 2006.260.07:53:09.77#ibcon#read 3, iclass 20, count 0 2006.260.07:53:09.77#ibcon#about to read 4, iclass 20, count 0 2006.260.07:53:09.77#ibcon#read 4, iclass 20, count 0 2006.260.07:53:09.77#ibcon#about to read 5, iclass 20, count 0 2006.260.07:53:09.77#ibcon#read 5, iclass 20, count 0 2006.260.07:53:09.77#ibcon#about to read 6, iclass 20, count 0 2006.260.07:53:09.77#ibcon#read 6, iclass 20, count 0 2006.260.07:53:09.77#ibcon#end of sib2, iclass 20, count 0 2006.260.07:53:09.77#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:53:09.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:53:09.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:53:09.77#ibcon#*before write, iclass 20, count 0 2006.260.07:53:09.77#ibcon#enter sib2, iclass 20, count 0 2006.260.07:53:09.77#ibcon#flushed, iclass 20, count 0 2006.260.07:53:09.77#ibcon#about to write, iclass 20, count 0 2006.260.07:53:09.77#ibcon#wrote, iclass 20, count 0 2006.260.07:53:09.77#ibcon#about to read 3, iclass 20, count 0 2006.260.07:53:09.81#ibcon#read 3, iclass 20, count 0 2006.260.07:53:09.81#ibcon#about to read 4, iclass 20, count 0 2006.260.07:53:09.81#ibcon#read 4, iclass 20, count 0 2006.260.07:53:09.81#ibcon#about to read 5, iclass 20, count 0 2006.260.07:53:09.81#ibcon#read 5, iclass 20, count 0 2006.260.07:53:09.81#ibcon#about to read 6, iclass 20, count 0 2006.260.07:53:09.81#ibcon#read 6, iclass 20, count 0 2006.260.07:53:09.81#ibcon#end of sib2, iclass 20, count 0 2006.260.07:53:09.81#ibcon#*after write, iclass 20, count 0 2006.260.07:53:09.81#ibcon#*before return 0, iclass 20, count 0 2006.260.07:53:09.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:09.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:09.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:53:09.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:53:09.81$vc4f8/va=3,8 2006.260.07:53:09.81#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:53:09.81#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:53:09.81#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:09.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:09.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:09.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:09.87#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:53:09.87#ibcon#first serial, iclass 22, count 2 2006.260.07:53:09.87#ibcon#enter sib2, iclass 22, count 2 2006.260.07:53:09.87#ibcon#flushed, iclass 22, count 2 2006.260.07:53:09.87#ibcon#about to write, iclass 22, count 2 2006.260.07:53:09.87#ibcon#wrote, iclass 22, count 2 2006.260.07:53:09.87#ibcon#about to read 3, iclass 22, count 2 2006.260.07:53:09.89#ibcon#read 3, iclass 22, count 2 2006.260.07:53:09.89#ibcon#about to read 4, iclass 22, count 2 2006.260.07:53:09.89#ibcon#read 4, iclass 22, count 2 2006.260.07:53:09.89#ibcon#about to read 5, iclass 22, count 2 2006.260.07:53:09.89#ibcon#read 5, iclass 22, count 2 2006.260.07:53:09.89#ibcon#about to read 6, iclass 22, count 2 2006.260.07:53:09.89#ibcon#read 6, iclass 22, count 2 2006.260.07:53:09.89#ibcon#end of sib2, iclass 22, count 2 2006.260.07:53:09.89#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:53:09.89#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:53:09.89#ibcon#[25=AT03-08\r\n] 2006.260.07:53:09.89#ibcon#*before write, iclass 22, count 2 2006.260.07:53:09.89#ibcon#enter sib2, iclass 22, count 2 2006.260.07:53:09.89#ibcon#flushed, iclass 22, count 2 2006.260.07:53:09.89#ibcon#about to write, iclass 22, count 2 2006.260.07:53:09.89#ibcon#wrote, iclass 22, count 2 2006.260.07:53:09.89#ibcon#about to read 3, iclass 22, count 2 2006.260.07:53:09.92#ibcon#read 3, iclass 22, count 2 2006.260.07:53:09.92#ibcon#about to read 4, iclass 22, count 2 2006.260.07:53:09.92#ibcon#read 4, iclass 22, count 2 2006.260.07:53:09.92#ibcon#about to read 5, iclass 22, count 2 2006.260.07:53:09.92#ibcon#read 5, iclass 22, count 2 2006.260.07:53:09.92#ibcon#about to read 6, iclass 22, count 2 2006.260.07:53:09.92#ibcon#read 6, iclass 22, count 2 2006.260.07:53:09.92#ibcon#end of sib2, iclass 22, count 2 2006.260.07:53:09.92#ibcon#*after write, iclass 22, count 2 2006.260.07:53:09.92#ibcon#*before return 0, iclass 22, count 2 2006.260.07:53:09.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:09.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:09.92#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:53:09.92#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:09.92#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:10.04#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:10.04#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:10.04#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:53:10.04#ibcon#first serial, iclass 22, count 0 2006.260.07:53:10.04#ibcon#enter sib2, iclass 22, count 0 2006.260.07:53:10.04#ibcon#flushed, iclass 22, count 0 2006.260.07:53:10.04#ibcon#about to write, iclass 22, count 0 2006.260.07:53:10.04#ibcon#wrote, iclass 22, count 0 2006.260.07:53:10.04#ibcon#about to read 3, iclass 22, count 0 2006.260.07:53:10.06#ibcon#read 3, iclass 22, count 0 2006.260.07:53:10.06#ibcon#about to read 4, iclass 22, count 0 2006.260.07:53:10.06#ibcon#read 4, iclass 22, count 0 2006.260.07:53:10.06#ibcon#about to read 5, iclass 22, count 0 2006.260.07:53:10.06#ibcon#read 5, iclass 22, count 0 2006.260.07:53:10.06#ibcon#about to read 6, iclass 22, count 0 2006.260.07:53:10.06#ibcon#read 6, iclass 22, count 0 2006.260.07:53:10.06#ibcon#end of sib2, iclass 22, count 0 2006.260.07:53:10.06#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:53:10.06#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:53:10.06#ibcon#[25=USB\r\n] 2006.260.07:53:10.06#ibcon#*before write, iclass 22, count 0 2006.260.07:53:10.06#ibcon#enter sib2, iclass 22, count 0 2006.260.07:53:10.06#ibcon#flushed, iclass 22, count 0 2006.260.07:53:10.06#ibcon#about to write, iclass 22, count 0 2006.260.07:53:10.06#ibcon#wrote, iclass 22, count 0 2006.260.07:53:10.06#ibcon#about to read 3, iclass 22, count 0 2006.260.07:53:10.09#ibcon#read 3, iclass 22, count 0 2006.260.07:53:10.09#ibcon#about to read 4, iclass 22, count 0 2006.260.07:53:10.09#ibcon#read 4, iclass 22, count 0 2006.260.07:53:10.09#ibcon#about to read 5, iclass 22, count 0 2006.260.07:53:10.09#ibcon#read 5, iclass 22, count 0 2006.260.07:53:10.09#ibcon#about to read 6, iclass 22, count 0 2006.260.07:53:10.09#ibcon#read 6, iclass 22, count 0 2006.260.07:53:10.09#ibcon#end of sib2, iclass 22, count 0 2006.260.07:53:10.09#ibcon#*after write, iclass 22, count 0 2006.260.07:53:10.09#ibcon#*before return 0, iclass 22, count 0 2006.260.07:53:10.09#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:10.09#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:10.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:53:10.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:53:10.09$vc4f8/valo=4,832.99 2006.260.07:53:10.09#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:53:10.09#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:53:10.09#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:10.09#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:10.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:10.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:10.09#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:53:10.09#ibcon#first serial, iclass 24, count 0 2006.260.07:53:10.09#ibcon#enter sib2, iclass 24, count 0 2006.260.07:53:10.09#ibcon#flushed, iclass 24, count 0 2006.260.07:53:10.09#ibcon#about to write, iclass 24, count 0 2006.260.07:53:10.09#ibcon#wrote, iclass 24, count 0 2006.260.07:53:10.09#ibcon#about to read 3, iclass 24, count 0 2006.260.07:53:10.11#ibcon#read 3, iclass 24, count 0 2006.260.07:53:10.11#ibcon#about to read 4, iclass 24, count 0 2006.260.07:53:10.11#ibcon#read 4, iclass 24, count 0 2006.260.07:53:10.11#ibcon#about to read 5, iclass 24, count 0 2006.260.07:53:10.11#ibcon#read 5, iclass 24, count 0 2006.260.07:53:10.11#ibcon#about to read 6, iclass 24, count 0 2006.260.07:53:10.11#ibcon#read 6, iclass 24, count 0 2006.260.07:53:10.11#ibcon#end of sib2, iclass 24, count 0 2006.260.07:53:10.11#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:53:10.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:53:10.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:53:10.11#ibcon#*before write, iclass 24, count 0 2006.260.07:53:10.11#ibcon#enter sib2, iclass 24, count 0 2006.260.07:53:10.11#ibcon#flushed, iclass 24, count 0 2006.260.07:53:10.11#ibcon#about to write, iclass 24, count 0 2006.260.07:53:10.11#ibcon#wrote, iclass 24, count 0 2006.260.07:53:10.11#ibcon#about to read 3, iclass 24, count 0 2006.260.07:53:10.15#ibcon#read 3, iclass 24, count 0 2006.260.07:53:10.15#ibcon#about to read 4, iclass 24, count 0 2006.260.07:53:10.15#ibcon#read 4, iclass 24, count 0 2006.260.07:53:10.15#ibcon#about to read 5, iclass 24, count 0 2006.260.07:53:10.15#ibcon#read 5, iclass 24, count 0 2006.260.07:53:10.15#ibcon#about to read 6, iclass 24, count 0 2006.260.07:53:10.15#ibcon#read 6, iclass 24, count 0 2006.260.07:53:10.15#ibcon#end of sib2, iclass 24, count 0 2006.260.07:53:10.15#ibcon#*after write, iclass 24, count 0 2006.260.07:53:10.15#ibcon#*before return 0, iclass 24, count 0 2006.260.07:53:10.15#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:10.15#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:10.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:53:10.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:53:10.15$vc4f8/va=4,7 2006.260.07:53:10.15#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.07:53:10.15#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.07:53:10.15#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:10.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:10.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:10.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:10.21#ibcon#enter wrdev, iclass 26, count 2 2006.260.07:53:10.21#ibcon#first serial, iclass 26, count 2 2006.260.07:53:10.21#ibcon#enter sib2, iclass 26, count 2 2006.260.07:53:10.21#ibcon#flushed, iclass 26, count 2 2006.260.07:53:10.21#ibcon#about to write, iclass 26, count 2 2006.260.07:53:10.21#ibcon#wrote, iclass 26, count 2 2006.260.07:53:10.21#ibcon#about to read 3, iclass 26, count 2 2006.260.07:53:10.23#ibcon#read 3, iclass 26, count 2 2006.260.07:53:10.23#ibcon#about to read 4, iclass 26, count 2 2006.260.07:53:10.23#ibcon#read 4, iclass 26, count 2 2006.260.07:53:10.23#ibcon#about to read 5, iclass 26, count 2 2006.260.07:53:10.23#ibcon#read 5, iclass 26, count 2 2006.260.07:53:10.23#ibcon#about to read 6, iclass 26, count 2 2006.260.07:53:10.23#ibcon#read 6, iclass 26, count 2 2006.260.07:53:10.23#ibcon#end of sib2, iclass 26, count 2 2006.260.07:53:10.23#ibcon#*mode == 0, iclass 26, count 2 2006.260.07:53:10.23#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.07:53:10.23#ibcon#[25=AT04-07\r\n] 2006.260.07:53:10.23#ibcon#*before write, iclass 26, count 2 2006.260.07:53:10.23#ibcon#enter sib2, iclass 26, count 2 2006.260.07:53:10.23#ibcon#flushed, iclass 26, count 2 2006.260.07:53:10.23#ibcon#about to write, iclass 26, count 2 2006.260.07:53:10.23#ibcon#wrote, iclass 26, count 2 2006.260.07:53:10.23#ibcon#about to read 3, iclass 26, count 2 2006.260.07:53:10.26#ibcon#read 3, iclass 26, count 2 2006.260.07:53:10.26#ibcon#about to read 4, iclass 26, count 2 2006.260.07:53:10.26#ibcon#read 4, iclass 26, count 2 2006.260.07:53:10.26#ibcon#about to read 5, iclass 26, count 2 2006.260.07:53:10.26#ibcon#read 5, iclass 26, count 2 2006.260.07:53:10.26#ibcon#about to read 6, iclass 26, count 2 2006.260.07:53:10.26#ibcon#read 6, iclass 26, count 2 2006.260.07:53:10.26#ibcon#end of sib2, iclass 26, count 2 2006.260.07:53:10.26#ibcon#*after write, iclass 26, count 2 2006.260.07:53:10.26#ibcon#*before return 0, iclass 26, count 2 2006.260.07:53:10.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:10.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:10.26#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.07:53:10.26#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:10.26#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:10.38#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:10.38#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:10.38#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:53:10.38#ibcon#first serial, iclass 26, count 0 2006.260.07:53:10.38#ibcon#enter sib2, iclass 26, count 0 2006.260.07:53:10.38#ibcon#flushed, iclass 26, count 0 2006.260.07:53:10.38#ibcon#about to write, iclass 26, count 0 2006.260.07:53:10.38#ibcon#wrote, iclass 26, count 0 2006.260.07:53:10.38#ibcon#about to read 3, iclass 26, count 0 2006.260.07:53:10.40#ibcon#read 3, iclass 26, count 0 2006.260.07:53:10.40#ibcon#about to read 4, iclass 26, count 0 2006.260.07:53:10.40#ibcon#read 4, iclass 26, count 0 2006.260.07:53:10.40#ibcon#about to read 5, iclass 26, count 0 2006.260.07:53:10.40#ibcon#read 5, iclass 26, count 0 2006.260.07:53:10.40#ibcon#about to read 6, iclass 26, count 0 2006.260.07:53:10.40#ibcon#read 6, iclass 26, count 0 2006.260.07:53:10.40#ibcon#end of sib2, iclass 26, count 0 2006.260.07:53:10.40#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:53:10.40#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:53:10.40#ibcon#[25=USB\r\n] 2006.260.07:53:10.40#ibcon#*before write, iclass 26, count 0 2006.260.07:53:10.40#ibcon#enter sib2, iclass 26, count 0 2006.260.07:53:10.40#ibcon#flushed, iclass 26, count 0 2006.260.07:53:10.40#ibcon#about to write, iclass 26, count 0 2006.260.07:53:10.40#ibcon#wrote, iclass 26, count 0 2006.260.07:53:10.40#ibcon#about to read 3, iclass 26, count 0 2006.260.07:53:10.43#ibcon#read 3, iclass 26, count 0 2006.260.07:53:10.43#ibcon#about to read 4, iclass 26, count 0 2006.260.07:53:10.43#ibcon#read 4, iclass 26, count 0 2006.260.07:53:10.43#ibcon#about to read 5, iclass 26, count 0 2006.260.07:53:10.43#ibcon#read 5, iclass 26, count 0 2006.260.07:53:10.43#ibcon#about to read 6, iclass 26, count 0 2006.260.07:53:10.43#ibcon#read 6, iclass 26, count 0 2006.260.07:53:10.43#ibcon#end of sib2, iclass 26, count 0 2006.260.07:53:10.43#ibcon#*after write, iclass 26, count 0 2006.260.07:53:10.43#ibcon#*before return 0, iclass 26, count 0 2006.260.07:53:10.43#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:10.43#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:10.43#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:53:10.43#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:53:10.43$vc4f8/valo=5,652.99 2006.260.07:53:10.43#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:53:10.43#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:53:10.43#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:10.43#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:10.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:10.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:10.43#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:53:10.43#ibcon#first serial, iclass 28, count 0 2006.260.07:53:10.43#ibcon#enter sib2, iclass 28, count 0 2006.260.07:53:10.43#ibcon#flushed, iclass 28, count 0 2006.260.07:53:10.43#ibcon#about to write, iclass 28, count 0 2006.260.07:53:10.43#ibcon#wrote, iclass 28, count 0 2006.260.07:53:10.43#ibcon#about to read 3, iclass 28, count 0 2006.260.07:53:10.45#ibcon#read 3, iclass 28, count 0 2006.260.07:53:10.45#ibcon#about to read 4, iclass 28, count 0 2006.260.07:53:10.45#ibcon#read 4, iclass 28, count 0 2006.260.07:53:10.45#ibcon#about to read 5, iclass 28, count 0 2006.260.07:53:10.45#ibcon#read 5, iclass 28, count 0 2006.260.07:53:10.45#ibcon#about to read 6, iclass 28, count 0 2006.260.07:53:10.45#ibcon#read 6, iclass 28, count 0 2006.260.07:53:10.45#ibcon#end of sib2, iclass 28, count 0 2006.260.07:53:10.45#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:53:10.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:53:10.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:53:10.45#ibcon#*before write, iclass 28, count 0 2006.260.07:53:10.45#ibcon#enter sib2, iclass 28, count 0 2006.260.07:53:10.45#ibcon#flushed, iclass 28, count 0 2006.260.07:53:10.45#ibcon#about to write, iclass 28, count 0 2006.260.07:53:10.45#ibcon#wrote, iclass 28, count 0 2006.260.07:53:10.45#ibcon#about to read 3, iclass 28, count 0 2006.260.07:53:10.49#ibcon#read 3, iclass 28, count 0 2006.260.07:53:10.49#ibcon#about to read 4, iclass 28, count 0 2006.260.07:53:10.49#ibcon#read 4, iclass 28, count 0 2006.260.07:53:10.49#ibcon#about to read 5, iclass 28, count 0 2006.260.07:53:10.49#ibcon#read 5, iclass 28, count 0 2006.260.07:53:10.49#ibcon#about to read 6, iclass 28, count 0 2006.260.07:53:10.49#ibcon#read 6, iclass 28, count 0 2006.260.07:53:10.49#ibcon#end of sib2, iclass 28, count 0 2006.260.07:53:10.49#ibcon#*after write, iclass 28, count 0 2006.260.07:53:10.49#ibcon#*before return 0, iclass 28, count 0 2006.260.07:53:10.49#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:10.49#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:10.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:53:10.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:53:10.49$vc4f8/va=5,7 2006.260.07:53:10.49#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.07:53:10.49#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.07:53:10.49#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:10.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:10.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:10.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:10.55#ibcon#enter wrdev, iclass 30, count 2 2006.260.07:53:10.55#ibcon#first serial, iclass 30, count 2 2006.260.07:53:10.55#ibcon#enter sib2, iclass 30, count 2 2006.260.07:53:10.55#ibcon#flushed, iclass 30, count 2 2006.260.07:53:10.55#ibcon#about to write, iclass 30, count 2 2006.260.07:53:10.55#ibcon#wrote, iclass 30, count 2 2006.260.07:53:10.55#ibcon#about to read 3, iclass 30, count 2 2006.260.07:53:10.57#ibcon#read 3, iclass 30, count 2 2006.260.07:53:10.57#ibcon#about to read 4, iclass 30, count 2 2006.260.07:53:10.57#ibcon#read 4, iclass 30, count 2 2006.260.07:53:10.57#ibcon#about to read 5, iclass 30, count 2 2006.260.07:53:10.57#ibcon#read 5, iclass 30, count 2 2006.260.07:53:10.57#ibcon#about to read 6, iclass 30, count 2 2006.260.07:53:10.57#ibcon#read 6, iclass 30, count 2 2006.260.07:53:10.57#ibcon#end of sib2, iclass 30, count 2 2006.260.07:53:10.57#ibcon#*mode == 0, iclass 30, count 2 2006.260.07:53:10.57#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.07:53:10.57#ibcon#[25=AT05-07\r\n] 2006.260.07:53:10.57#ibcon#*before write, iclass 30, count 2 2006.260.07:53:10.57#ibcon#enter sib2, iclass 30, count 2 2006.260.07:53:10.57#ibcon#flushed, iclass 30, count 2 2006.260.07:53:10.57#ibcon#about to write, iclass 30, count 2 2006.260.07:53:10.57#ibcon#wrote, iclass 30, count 2 2006.260.07:53:10.57#ibcon#about to read 3, iclass 30, count 2 2006.260.07:53:10.60#ibcon#read 3, iclass 30, count 2 2006.260.07:53:10.60#ibcon#about to read 4, iclass 30, count 2 2006.260.07:53:10.60#ibcon#read 4, iclass 30, count 2 2006.260.07:53:10.60#ibcon#about to read 5, iclass 30, count 2 2006.260.07:53:10.60#ibcon#read 5, iclass 30, count 2 2006.260.07:53:10.60#ibcon#about to read 6, iclass 30, count 2 2006.260.07:53:10.60#ibcon#read 6, iclass 30, count 2 2006.260.07:53:10.60#ibcon#end of sib2, iclass 30, count 2 2006.260.07:53:10.60#ibcon#*after write, iclass 30, count 2 2006.260.07:53:10.60#ibcon#*before return 0, iclass 30, count 2 2006.260.07:53:10.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:10.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:10.60#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.07:53:10.60#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:10.60#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:10.72#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:10.72#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:10.72#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:53:10.72#ibcon#first serial, iclass 30, count 0 2006.260.07:53:10.72#ibcon#enter sib2, iclass 30, count 0 2006.260.07:53:10.72#ibcon#flushed, iclass 30, count 0 2006.260.07:53:10.72#ibcon#about to write, iclass 30, count 0 2006.260.07:53:10.72#ibcon#wrote, iclass 30, count 0 2006.260.07:53:10.72#ibcon#about to read 3, iclass 30, count 0 2006.260.07:53:10.74#ibcon#read 3, iclass 30, count 0 2006.260.07:53:10.74#ibcon#about to read 4, iclass 30, count 0 2006.260.07:53:10.74#ibcon#read 4, iclass 30, count 0 2006.260.07:53:10.74#ibcon#about to read 5, iclass 30, count 0 2006.260.07:53:10.74#ibcon#read 5, iclass 30, count 0 2006.260.07:53:10.74#ibcon#about to read 6, iclass 30, count 0 2006.260.07:53:10.74#ibcon#read 6, iclass 30, count 0 2006.260.07:53:10.74#ibcon#end of sib2, iclass 30, count 0 2006.260.07:53:10.74#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:53:10.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:53:10.74#ibcon#[25=USB\r\n] 2006.260.07:53:10.74#ibcon#*before write, iclass 30, count 0 2006.260.07:53:10.74#ibcon#enter sib2, iclass 30, count 0 2006.260.07:53:10.74#ibcon#flushed, iclass 30, count 0 2006.260.07:53:10.74#ibcon#about to write, iclass 30, count 0 2006.260.07:53:10.74#ibcon#wrote, iclass 30, count 0 2006.260.07:53:10.74#ibcon#about to read 3, iclass 30, count 0 2006.260.07:53:10.77#ibcon#read 3, iclass 30, count 0 2006.260.07:53:10.77#ibcon#about to read 4, iclass 30, count 0 2006.260.07:53:10.77#ibcon#read 4, iclass 30, count 0 2006.260.07:53:10.77#ibcon#about to read 5, iclass 30, count 0 2006.260.07:53:10.77#ibcon#read 5, iclass 30, count 0 2006.260.07:53:10.77#ibcon#about to read 6, iclass 30, count 0 2006.260.07:53:10.77#ibcon#read 6, iclass 30, count 0 2006.260.07:53:10.77#ibcon#end of sib2, iclass 30, count 0 2006.260.07:53:10.77#ibcon#*after write, iclass 30, count 0 2006.260.07:53:10.77#ibcon#*before return 0, iclass 30, count 0 2006.260.07:53:10.77#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:10.77#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:10.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:53:10.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:53:10.77$vc4f8/valo=6,772.99 2006.260.07:53:10.77#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:53:10.77#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:53:10.77#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:10.77#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:10.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:10.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:10.77#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:53:10.77#ibcon#first serial, iclass 32, count 0 2006.260.07:53:10.77#ibcon#enter sib2, iclass 32, count 0 2006.260.07:53:10.77#ibcon#flushed, iclass 32, count 0 2006.260.07:53:10.77#ibcon#about to write, iclass 32, count 0 2006.260.07:53:10.77#ibcon#wrote, iclass 32, count 0 2006.260.07:53:10.77#ibcon#about to read 3, iclass 32, count 0 2006.260.07:53:10.79#ibcon#read 3, iclass 32, count 0 2006.260.07:53:10.79#ibcon#about to read 4, iclass 32, count 0 2006.260.07:53:10.79#ibcon#read 4, iclass 32, count 0 2006.260.07:53:10.79#ibcon#about to read 5, iclass 32, count 0 2006.260.07:53:10.79#ibcon#read 5, iclass 32, count 0 2006.260.07:53:10.79#ibcon#about to read 6, iclass 32, count 0 2006.260.07:53:10.79#ibcon#read 6, iclass 32, count 0 2006.260.07:53:10.79#ibcon#end of sib2, iclass 32, count 0 2006.260.07:53:10.79#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:53:10.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:53:10.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:53:10.79#ibcon#*before write, iclass 32, count 0 2006.260.07:53:10.79#ibcon#enter sib2, iclass 32, count 0 2006.260.07:53:10.79#ibcon#flushed, iclass 32, count 0 2006.260.07:53:10.79#ibcon#about to write, iclass 32, count 0 2006.260.07:53:10.79#ibcon#wrote, iclass 32, count 0 2006.260.07:53:10.79#ibcon#about to read 3, iclass 32, count 0 2006.260.07:53:10.83#ibcon#read 3, iclass 32, count 0 2006.260.07:53:10.83#ibcon#about to read 4, iclass 32, count 0 2006.260.07:53:10.83#ibcon#read 4, iclass 32, count 0 2006.260.07:53:10.83#ibcon#about to read 5, iclass 32, count 0 2006.260.07:53:10.83#ibcon#read 5, iclass 32, count 0 2006.260.07:53:10.83#ibcon#about to read 6, iclass 32, count 0 2006.260.07:53:10.83#ibcon#read 6, iclass 32, count 0 2006.260.07:53:10.83#ibcon#end of sib2, iclass 32, count 0 2006.260.07:53:10.83#ibcon#*after write, iclass 32, count 0 2006.260.07:53:10.83#ibcon#*before return 0, iclass 32, count 0 2006.260.07:53:10.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:10.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:10.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:53:10.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:53:10.83$vc4f8/va=6,6 2006.260.07:53:10.83#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.07:53:10.83#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.07:53:10.83#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:10.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:10.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:10.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:10.89#ibcon#enter wrdev, iclass 34, count 2 2006.260.07:53:10.89#ibcon#first serial, iclass 34, count 2 2006.260.07:53:10.89#ibcon#enter sib2, iclass 34, count 2 2006.260.07:53:10.89#ibcon#flushed, iclass 34, count 2 2006.260.07:53:10.89#ibcon#about to write, iclass 34, count 2 2006.260.07:53:10.89#ibcon#wrote, iclass 34, count 2 2006.260.07:53:10.89#ibcon#about to read 3, iclass 34, count 2 2006.260.07:53:10.91#ibcon#read 3, iclass 34, count 2 2006.260.07:53:10.91#ibcon#about to read 4, iclass 34, count 2 2006.260.07:53:10.91#ibcon#read 4, iclass 34, count 2 2006.260.07:53:10.91#ibcon#about to read 5, iclass 34, count 2 2006.260.07:53:10.91#ibcon#read 5, iclass 34, count 2 2006.260.07:53:10.91#ibcon#about to read 6, iclass 34, count 2 2006.260.07:53:10.91#ibcon#read 6, iclass 34, count 2 2006.260.07:53:10.91#ibcon#end of sib2, iclass 34, count 2 2006.260.07:53:10.91#ibcon#*mode == 0, iclass 34, count 2 2006.260.07:53:10.91#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.07:53:10.91#ibcon#[25=AT06-06\r\n] 2006.260.07:53:10.91#ibcon#*before write, iclass 34, count 2 2006.260.07:53:10.91#ibcon#enter sib2, iclass 34, count 2 2006.260.07:53:10.91#ibcon#flushed, iclass 34, count 2 2006.260.07:53:10.91#ibcon#about to write, iclass 34, count 2 2006.260.07:53:10.91#ibcon#wrote, iclass 34, count 2 2006.260.07:53:10.91#ibcon#about to read 3, iclass 34, count 2 2006.260.07:53:10.94#ibcon#read 3, iclass 34, count 2 2006.260.07:53:10.94#ibcon#about to read 4, iclass 34, count 2 2006.260.07:53:10.94#ibcon#read 4, iclass 34, count 2 2006.260.07:53:10.94#ibcon#about to read 5, iclass 34, count 2 2006.260.07:53:10.94#ibcon#read 5, iclass 34, count 2 2006.260.07:53:10.94#ibcon#about to read 6, iclass 34, count 2 2006.260.07:53:10.94#ibcon#read 6, iclass 34, count 2 2006.260.07:53:10.94#ibcon#end of sib2, iclass 34, count 2 2006.260.07:53:10.94#ibcon#*after write, iclass 34, count 2 2006.260.07:53:10.94#ibcon#*before return 0, iclass 34, count 2 2006.260.07:53:10.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:10.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:10.94#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.07:53:10.94#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:10.94#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:53:11.06#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:53:11.06#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:53:11.06#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:53:11.06#ibcon#first serial, iclass 34, count 0 2006.260.07:53:11.06#ibcon#enter sib2, iclass 34, count 0 2006.260.07:53:11.06#ibcon#flushed, iclass 34, count 0 2006.260.07:53:11.06#ibcon#about to write, iclass 34, count 0 2006.260.07:53:11.06#ibcon#wrote, iclass 34, count 0 2006.260.07:53:11.06#ibcon#about to read 3, iclass 34, count 0 2006.260.07:53:11.08#ibcon#read 3, iclass 34, count 0 2006.260.07:53:11.08#ibcon#about to read 4, iclass 34, count 0 2006.260.07:53:11.08#ibcon#read 4, iclass 34, count 0 2006.260.07:53:11.08#ibcon#about to read 5, iclass 34, count 0 2006.260.07:53:11.08#ibcon#read 5, iclass 34, count 0 2006.260.07:53:11.08#ibcon#about to read 6, iclass 34, count 0 2006.260.07:53:11.08#ibcon#read 6, iclass 34, count 0 2006.260.07:53:11.08#ibcon#end of sib2, iclass 34, count 0 2006.260.07:53:11.08#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:53:11.08#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:53:11.08#ibcon#[25=USB\r\n] 2006.260.07:53:11.08#ibcon#*before write, iclass 34, count 0 2006.260.07:53:11.08#ibcon#enter sib2, iclass 34, count 0 2006.260.07:53:11.08#ibcon#flushed, iclass 34, count 0 2006.260.07:53:11.08#ibcon#about to write, iclass 34, count 0 2006.260.07:53:11.08#ibcon#wrote, iclass 34, count 0 2006.260.07:53:11.08#ibcon#about to read 3, iclass 34, count 0 2006.260.07:53:11.11#ibcon#read 3, iclass 34, count 0 2006.260.07:53:11.11#ibcon#about to read 4, iclass 34, count 0 2006.260.07:53:11.11#ibcon#read 4, iclass 34, count 0 2006.260.07:53:11.11#ibcon#about to read 5, iclass 34, count 0 2006.260.07:53:11.11#ibcon#read 5, iclass 34, count 0 2006.260.07:53:11.11#ibcon#about to read 6, iclass 34, count 0 2006.260.07:53:11.11#ibcon#read 6, iclass 34, count 0 2006.260.07:53:11.11#ibcon#end of sib2, iclass 34, count 0 2006.260.07:53:11.11#ibcon#*after write, iclass 34, count 0 2006.260.07:53:11.11#ibcon#*before return 0, iclass 34, count 0 2006.260.07:53:11.11#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:53:11.11#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.07:53:11.11#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:53:11.11#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:53:11.11$vc4f8/valo=7,832.99 2006.260.07:53:11.11#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.07:53:11.11#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.07:53:11.11#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:11.11#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:53:11.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:53:11.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:53:11.11#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:53:11.11#ibcon#first serial, iclass 36, count 0 2006.260.07:53:11.11#ibcon#enter sib2, iclass 36, count 0 2006.260.07:53:11.11#ibcon#flushed, iclass 36, count 0 2006.260.07:53:11.11#ibcon#about to write, iclass 36, count 0 2006.260.07:53:11.11#ibcon#wrote, iclass 36, count 0 2006.260.07:53:11.11#ibcon#about to read 3, iclass 36, count 0 2006.260.07:53:11.13#ibcon#read 3, iclass 36, count 0 2006.260.07:53:11.13#ibcon#about to read 4, iclass 36, count 0 2006.260.07:53:11.13#ibcon#read 4, iclass 36, count 0 2006.260.07:53:11.13#ibcon#about to read 5, iclass 36, count 0 2006.260.07:53:11.13#ibcon#read 5, iclass 36, count 0 2006.260.07:53:11.13#ibcon#about to read 6, iclass 36, count 0 2006.260.07:53:11.13#ibcon#read 6, iclass 36, count 0 2006.260.07:53:11.13#ibcon#end of sib2, iclass 36, count 0 2006.260.07:53:11.13#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:53:11.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:53:11.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:53:11.13#ibcon#*before write, iclass 36, count 0 2006.260.07:53:11.13#ibcon#enter sib2, iclass 36, count 0 2006.260.07:53:11.13#ibcon#flushed, iclass 36, count 0 2006.260.07:53:11.13#ibcon#about to write, iclass 36, count 0 2006.260.07:53:11.13#ibcon#wrote, iclass 36, count 0 2006.260.07:53:11.13#ibcon#about to read 3, iclass 36, count 0 2006.260.07:53:11.17#ibcon#read 3, iclass 36, count 0 2006.260.07:53:11.17#ibcon#about to read 4, iclass 36, count 0 2006.260.07:53:11.17#ibcon#read 4, iclass 36, count 0 2006.260.07:53:11.17#ibcon#about to read 5, iclass 36, count 0 2006.260.07:53:11.17#ibcon#read 5, iclass 36, count 0 2006.260.07:53:11.17#ibcon#about to read 6, iclass 36, count 0 2006.260.07:53:11.17#ibcon#read 6, iclass 36, count 0 2006.260.07:53:11.17#ibcon#end of sib2, iclass 36, count 0 2006.260.07:53:11.17#ibcon#*after write, iclass 36, count 0 2006.260.07:53:11.17#ibcon#*before return 0, iclass 36, count 0 2006.260.07:53:11.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:53:11.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.07:53:11.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:53:11.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:53:11.17$vc4f8/va=7,6 2006.260.07:53:11.17#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.07:53:11.17#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.07:53:11.17#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:11.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:53:11.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:53:11.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:53:11.23#ibcon#enter wrdev, iclass 38, count 2 2006.260.07:53:11.23#ibcon#first serial, iclass 38, count 2 2006.260.07:53:11.23#ibcon#enter sib2, iclass 38, count 2 2006.260.07:53:11.23#ibcon#flushed, iclass 38, count 2 2006.260.07:53:11.23#ibcon#about to write, iclass 38, count 2 2006.260.07:53:11.23#ibcon#wrote, iclass 38, count 2 2006.260.07:53:11.23#ibcon#about to read 3, iclass 38, count 2 2006.260.07:53:11.25#ibcon#read 3, iclass 38, count 2 2006.260.07:53:11.25#ibcon#about to read 4, iclass 38, count 2 2006.260.07:53:11.25#ibcon#read 4, iclass 38, count 2 2006.260.07:53:11.25#ibcon#about to read 5, iclass 38, count 2 2006.260.07:53:11.25#ibcon#read 5, iclass 38, count 2 2006.260.07:53:11.25#ibcon#about to read 6, iclass 38, count 2 2006.260.07:53:11.25#ibcon#read 6, iclass 38, count 2 2006.260.07:53:11.25#ibcon#end of sib2, iclass 38, count 2 2006.260.07:53:11.25#ibcon#*mode == 0, iclass 38, count 2 2006.260.07:53:11.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.07:53:11.25#ibcon#[25=AT07-06\r\n] 2006.260.07:53:11.25#ibcon#*before write, iclass 38, count 2 2006.260.07:53:11.25#ibcon#enter sib2, iclass 38, count 2 2006.260.07:53:11.25#ibcon#flushed, iclass 38, count 2 2006.260.07:53:11.25#ibcon#about to write, iclass 38, count 2 2006.260.07:53:11.25#ibcon#wrote, iclass 38, count 2 2006.260.07:53:11.25#ibcon#about to read 3, iclass 38, count 2 2006.260.07:53:11.28#ibcon#read 3, iclass 38, count 2 2006.260.07:53:11.28#ibcon#about to read 4, iclass 38, count 2 2006.260.07:53:11.28#ibcon#read 4, iclass 38, count 2 2006.260.07:53:11.28#ibcon#about to read 5, iclass 38, count 2 2006.260.07:53:11.28#ibcon#read 5, iclass 38, count 2 2006.260.07:53:11.28#ibcon#about to read 6, iclass 38, count 2 2006.260.07:53:11.28#ibcon#read 6, iclass 38, count 2 2006.260.07:53:11.28#ibcon#end of sib2, iclass 38, count 2 2006.260.07:53:11.28#ibcon#*after write, iclass 38, count 2 2006.260.07:53:11.28#ibcon#*before return 0, iclass 38, count 2 2006.260.07:53:11.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:53:11.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.07:53:11.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.07:53:11.28#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:11.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:53:11.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:53:11.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:53:11.40#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:53:11.40#ibcon#first serial, iclass 38, count 0 2006.260.07:53:11.40#ibcon#enter sib2, iclass 38, count 0 2006.260.07:53:11.40#ibcon#flushed, iclass 38, count 0 2006.260.07:53:11.40#ibcon#about to write, iclass 38, count 0 2006.260.07:53:11.40#ibcon#wrote, iclass 38, count 0 2006.260.07:53:11.40#ibcon#about to read 3, iclass 38, count 0 2006.260.07:53:11.42#ibcon#read 3, iclass 38, count 0 2006.260.07:53:11.42#ibcon#about to read 4, iclass 38, count 0 2006.260.07:53:11.42#ibcon#read 4, iclass 38, count 0 2006.260.07:53:11.42#ibcon#about to read 5, iclass 38, count 0 2006.260.07:53:11.42#ibcon#read 5, iclass 38, count 0 2006.260.07:53:11.42#ibcon#about to read 6, iclass 38, count 0 2006.260.07:53:11.42#ibcon#read 6, iclass 38, count 0 2006.260.07:53:11.42#ibcon#end of sib2, iclass 38, count 0 2006.260.07:53:11.42#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:53:11.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:53:11.42#ibcon#[25=USB\r\n] 2006.260.07:53:11.42#ibcon#*before write, iclass 38, count 0 2006.260.07:53:11.42#ibcon#enter sib2, iclass 38, count 0 2006.260.07:53:11.42#ibcon#flushed, iclass 38, count 0 2006.260.07:53:11.42#ibcon#about to write, iclass 38, count 0 2006.260.07:53:11.42#ibcon#wrote, iclass 38, count 0 2006.260.07:53:11.42#ibcon#about to read 3, iclass 38, count 0 2006.260.07:53:11.45#ibcon#read 3, iclass 38, count 0 2006.260.07:53:11.45#ibcon#about to read 4, iclass 38, count 0 2006.260.07:53:11.45#ibcon#read 4, iclass 38, count 0 2006.260.07:53:11.45#ibcon#about to read 5, iclass 38, count 0 2006.260.07:53:11.45#ibcon#read 5, iclass 38, count 0 2006.260.07:53:11.45#ibcon#about to read 6, iclass 38, count 0 2006.260.07:53:11.45#ibcon#read 6, iclass 38, count 0 2006.260.07:53:11.45#ibcon#end of sib2, iclass 38, count 0 2006.260.07:53:11.45#ibcon#*after write, iclass 38, count 0 2006.260.07:53:11.45#ibcon#*before return 0, iclass 38, count 0 2006.260.07:53:11.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:53:11.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.07:53:11.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:53:11.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:53:11.45$vc4f8/valo=8,852.99 2006.260.07:53:11.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.07:53:11.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.07:53:11.45#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:11.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:53:11.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:53:11.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:53:11.45#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:53:11.45#ibcon#first serial, iclass 40, count 0 2006.260.07:53:11.45#ibcon#enter sib2, iclass 40, count 0 2006.260.07:53:11.45#ibcon#flushed, iclass 40, count 0 2006.260.07:53:11.45#ibcon#about to write, iclass 40, count 0 2006.260.07:53:11.45#ibcon#wrote, iclass 40, count 0 2006.260.07:53:11.45#ibcon#about to read 3, iclass 40, count 0 2006.260.07:53:11.47#ibcon#read 3, iclass 40, count 0 2006.260.07:53:11.47#ibcon#about to read 4, iclass 40, count 0 2006.260.07:53:11.47#ibcon#read 4, iclass 40, count 0 2006.260.07:53:11.47#ibcon#about to read 5, iclass 40, count 0 2006.260.07:53:11.47#ibcon#read 5, iclass 40, count 0 2006.260.07:53:11.47#ibcon#about to read 6, iclass 40, count 0 2006.260.07:53:11.47#ibcon#read 6, iclass 40, count 0 2006.260.07:53:11.47#ibcon#end of sib2, iclass 40, count 0 2006.260.07:53:11.47#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:53:11.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:53:11.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:53:11.47#ibcon#*before write, iclass 40, count 0 2006.260.07:53:11.47#ibcon#enter sib2, iclass 40, count 0 2006.260.07:53:11.47#ibcon#flushed, iclass 40, count 0 2006.260.07:53:11.47#ibcon#about to write, iclass 40, count 0 2006.260.07:53:11.47#ibcon#wrote, iclass 40, count 0 2006.260.07:53:11.47#ibcon#about to read 3, iclass 40, count 0 2006.260.07:53:11.51#ibcon#read 3, iclass 40, count 0 2006.260.07:53:11.51#ibcon#about to read 4, iclass 40, count 0 2006.260.07:53:11.51#ibcon#read 4, iclass 40, count 0 2006.260.07:53:11.51#ibcon#about to read 5, iclass 40, count 0 2006.260.07:53:11.51#ibcon#read 5, iclass 40, count 0 2006.260.07:53:11.51#ibcon#about to read 6, iclass 40, count 0 2006.260.07:53:11.51#ibcon#read 6, iclass 40, count 0 2006.260.07:53:11.51#ibcon#end of sib2, iclass 40, count 0 2006.260.07:53:11.51#ibcon#*after write, iclass 40, count 0 2006.260.07:53:11.51#ibcon#*before return 0, iclass 40, count 0 2006.260.07:53:11.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:53:11.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.07:53:11.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:53:11.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:53:11.51$vc4f8/va=8,6 2006.260.07:53:11.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.07:53:11.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.07:53:11.51#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:11.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:53:11.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:53:11.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:53:11.57#ibcon#enter wrdev, iclass 4, count 2 2006.260.07:53:11.57#ibcon#first serial, iclass 4, count 2 2006.260.07:53:11.57#ibcon#enter sib2, iclass 4, count 2 2006.260.07:53:11.57#ibcon#flushed, iclass 4, count 2 2006.260.07:53:11.57#ibcon#about to write, iclass 4, count 2 2006.260.07:53:11.57#ibcon#wrote, iclass 4, count 2 2006.260.07:53:11.57#ibcon#about to read 3, iclass 4, count 2 2006.260.07:53:11.59#ibcon#read 3, iclass 4, count 2 2006.260.07:53:11.59#ibcon#about to read 4, iclass 4, count 2 2006.260.07:53:11.59#ibcon#read 4, iclass 4, count 2 2006.260.07:53:11.59#ibcon#about to read 5, iclass 4, count 2 2006.260.07:53:11.59#ibcon#read 5, iclass 4, count 2 2006.260.07:53:11.59#ibcon#about to read 6, iclass 4, count 2 2006.260.07:53:11.59#ibcon#read 6, iclass 4, count 2 2006.260.07:53:11.59#ibcon#end of sib2, iclass 4, count 2 2006.260.07:53:11.59#ibcon#*mode == 0, iclass 4, count 2 2006.260.07:53:11.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.07:53:11.59#ibcon#[25=AT08-06\r\n] 2006.260.07:53:11.59#ibcon#*before write, iclass 4, count 2 2006.260.07:53:11.59#ibcon#enter sib2, iclass 4, count 2 2006.260.07:53:11.59#ibcon#flushed, iclass 4, count 2 2006.260.07:53:11.59#ibcon#about to write, iclass 4, count 2 2006.260.07:53:11.59#ibcon#wrote, iclass 4, count 2 2006.260.07:53:11.59#ibcon#about to read 3, iclass 4, count 2 2006.260.07:53:11.62#ibcon#read 3, iclass 4, count 2 2006.260.07:53:11.62#ibcon#about to read 4, iclass 4, count 2 2006.260.07:53:11.62#ibcon#read 4, iclass 4, count 2 2006.260.07:53:11.62#ibcon#about to read 5, iclass 4, count 2 2006.260.07:53:11.62#ibcon#read 5, iclass 4, count 2 2006.260.07:53:11.62#ibcon#about to read 6, iclass 4, count 2 2006.260.07:53:11.62#ibcon#read 6, iclass 4, count 2 2006.260.07:53:11.62#ibcon#end of sib2, iclass 4, count 2 2006.260.07:53:11.62#ibcon#*after write, iclass 4, count 2 2006.260.07:53:11.62#ibcon#*before return 0, iclass 4, count 2 2006.260.07:53:11.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:53:11.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.07:53:11.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.07:53:11.62#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:11.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:53:11.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:53:11.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:53:11.74#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:53:11.74#ibcon#first serial, iclass 4, count 0 2006.260.07:53:11.74#ibcon#enter sib2, iclass 4, count 0 2006.260.07:53:11.74#ibcon#flushed, iclass 4, count 0 2006.260.07:53:11.74#ibcon#about to write, iclass 4, count 0 2006.260.07:53:11.74#ibcon#wrote, iclass 4, count 0 2006.260.07:53:11.74#ibcon#about to read 3, iclass 4, count 0 2006.260.07:53:11.76#ibcon#read 3, iclass 4, count 0 2006.260.07:53:11.76#ibcon#about to read 4, iclass 4, count 0 2006.260.07:53:11.76#ibcon#read 4, iclass 4, count 0 2006.260.07:53:11.76#ibcon#about to read 5, iclass 4, count 0 2006.260.07:53:11.76#ibcon#read 5, iclass 4, count 0 2006.260.07:53:11.76#ibcon#about to read 6, iclass 4, count 0 2006.260.07:53:11.76#ibcon#read 6, iclass 4, count 0 2006.260.07:53:11.76#ibcon#end of sib2, iclass 4, count 0 2006.260.07:53:11.76#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:53:11.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:53:11.76#ibcon#[25=USB\r\n] 2006.260.07:53:11.76#ibcon#*before write, iclass 4, count 0 2006.260.07:53:11.76#ibcon#enter sib2, iclass 4, count 0 2006.260.07:53:11.76#ibcon#flushed, iclass 4, count 0 2006.260.07:53:11.76#ibcon#about to write, iclass 4, count 0 2006.260.07:53:11.76#ibcon#wrote, iclass 4, count 0 2006.260.07:53:11.76#ibcon#about to read 3, iclass 4, count 0 2006.260.07:53:11.79#ibcon#read 3, iclass 4, count 0 2006.260.07:53:11.79#ibcon#about to read 4, iclass 4, count 0 2006.260.07:53:11.79#ibcon#read 4, iclass 4, count 0 2006.260.07:53:11.79#ibcon#about to read 5, iclass 4, count 0 2006.260.07:53:11.79#ibcon#read 5, iclass 4, count 0 2006.260.07:53:11.79#ibcon#about to read 6, iclass 4, count 0 2006.260.07:53:11.79#ibcon#read 6, iclass 4, count 0 2006.260.07:53:11.79#ibcon#end of sib2, iclass 4, count 0 2006.260.07:53:11.79#ibcon#*after write, iclass 4, count 0 2006.260.07:53:11.79#ibcon#*before return 0, iclass 4, count 0 2006.260.07:53:11.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:53:11.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.07:53:11.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:53:11.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:53:11.79$vc4f8/vblo=1,632.99 2006.260.07:53:11.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.07:53:11.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.07:53:11.79#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:11.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:53:11.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:53:11.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:53:11.79#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:53:11.79#ibcon#first serial, iclass 6, count 0 2006.260.07:53:11.79#ibcon#enter sib2, iclass 6, count 0 2006.260.07:53:11.79#ibcon#flushed, iclass 6, count 0 2006.260.07:53:11.79#ibcon#about to write, iclass 6, count 0 2006.260.07:53:11.79#ibcon#wrote, iclass 6, count 0 2006.260.07:53:11.79#ibcon#about to read 3, iclass 6, count 0 2006.260.07:53:11.81#ibcon#read 3, iclass 6, count 0 2006.260.07:53:11.81#ibcon#about to read 4, iclass 6, count 0 2006.260.07:53:11.81#ibcon#read 4, iclass 6, count 0 2006.260.07:53:11.81#ibcon#about to read 5, iclass 6, count 0 2006.260.07:53:11.81#ibcon#read 5, iclass 6, count 0 2006.260.07:53:11.81#ibcon#about to read 6, iclass 6, count 0 2006.260.07:53:11.81#ibcon#read 6, iclass 6, count 0 2006.260.07:53:11.81#ibcon#end of sib2, iclass 6, count 0 2006.260.07:53:11.81#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:53:11.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:53:11.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:53:11.81#ibcon#*before write, iclass 6, count 0 2006.260.07:53:11.81#ibcon#enter sib2, iclass 6, count 0 2006.260.07:53:11.81#ibcon#flushed, iclass 6, count 0 2006.260.07:53:11.81#ibcon#about to write, iclass 6, count 0 2006.260.07:53:11.81#ibcon#wrote, iclass 6, count 0 2006.260.07:53:11.81#ibcon#about to read 3, iclass 6, count 0 2006.260.07:53:11.85#ibcon#read 3, iclass 6, count 0 2006.260.07:53:11.85#ibcon#about to read 4, iclass 6, count 0 2006.260.07:53:11.85#ibcon#read 4, iclass 6, count 0 2006.260.07:53:11.85#ibcon#about to read 5, iclass 6, count 0 2006.260.07:53:11.85#ibcon#read 5, iclass 6, count 0 2006.260.07:53:11.85#ibcon#about to read 6, iclass 6, count 0 2006.260.07:53:11.85#ibcon#read 6, iclass 6, count 0 2006.260.07:53:11.85#ibcon#end of sib2, iclass 6, count 0 2006.260.07:53:11.85#ibcon#*after write, iclass 6, count 0 2006.260.07:53:11.85#ibcon#*before return 0, iclass 6, count 0 2006.260.07:53:11.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:53:11.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.07:53:11.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:53:11.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:53:11.85$vc4f8/vb=1,4 2006.260.07:53:11.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.07:53:11.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.07:53:11.85#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:11.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:53:11.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:53:11.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:53:11.85#ibcon#enter wrdev, iclass 10, count 2 2006.260.07:53:11.85#ibcon#first serial, iclass 10, count 2 2006.260.07:53:11.85#ibcon#enter sib2, iclass 10, count 2 2006.260.07:53:11.85#ibcon#flushed, iclass 10, count 2 2006.260.07:53:11.85#ibcon#about to write, iclass 10, count 2 2006.260.07:53:11.85#ibcon#wrote, iclass 10, count 2 2006.260.07:53:11.85#ibcon#about to read 3, iclass 10, count 2 2006.260.07:53:11.87#ibcon#read 3, iclass 10, count 2 2006.260.07:53:11.87#ibcon#about to read 4, iclass 10, count 2 2006.260.07:53:11.87#ibcon#read 4, iclass 10, count 2 2006.260.07:53:11.87#ibcon#about to read 5, iclass 10, count 2 2006.260.07:53:11.87#ibcon#read 5, iclass 10, count 2 2006.260.07:53:11.87#ibcon#about to read 6, iclass 10, count 2 2006.260.07:53:11.87#ibcon#read 6, iclass 10, count 2 2006.260.07:53:11.87#ibcon#end of sib2, iclass 10, count 2 2006.260.07:53:11.87#ibcon#*mode == 0, iclass 10, count 2 2006.260.07:53:11.87#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.07:53:11.87#ibcon#[27=AT01-04\r\n] 2006.260.07:53:11.87#ibcon#*before write, iclass 10, count 2 2006.260.07:53:11.87#ibcon#enter sib2, iclass 10, count 2 2006.260.07:53:11.87#ibcon#flushed, iclass 10, count 2 2006.260.07:53:11.87#ibcon#about to write, iclass 10, count 2 2006.260.07:53:11.87#ibcon#wrote, iclass 10, count 2 2006.260.07:53:11.87#ibcon#about to read 3, iclass 10, count 2 2006.260.07:53:11.90#ibcon#read 3, iclass 10, count 2 2006.260.07:53:11.90#ibcon#about to read 4, iclass 10, count 2 2006.260.07:53:11.90#ibcon#read 4, iclass 10, count 2 2006.260.07:53:11.90#ibcon#about to read 5, iclass 10, count 2 2006.260.07:53:11.90#ibcon#read 5, iclass 10, count 2 2006.260.07:53:11.90#ibcon#about to read 6, iclass 10, count 2 2006.260.07:53:11.90#ibcon#read 6, iclass 10, count 2 2006.260.07:53:11.90#ibcon#end of sib2, iclass 10, count 2 2006.260.07:53:11.90#ibcon#*after write, iclass 10, count 2 2006.260.07:53:11.90#ibcon#*before return 0, iclass 10, count 2 2006.260.07:53:11.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:53:11.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.07:53:11.90#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.07:53:11.90#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:11.90#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:53:12.02#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:53:12.02#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:53:12.02#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:53:12.02#ibcon#first serial, iclass 10, count 0 2006.260.07:53:12.02#ibcon#enter sib2, iclass 10, count 0 2006.260.07:53:12.02#ibcon#flushed, iclass 10, count 0 2006.260.07:53:12.02#ibcon#about to write, iclass 10, count 0 2006.260.07:53:12.02#ibcon#wrote, iclass 10, count 0 2006.260.07:53:12.02#ibcon#about to read 3, iclass 10, count 0 2006.260.07:53:12.05#ibcon#read 3, iclass 10, count 0 2006.260.07:53:12.05#ibcon#about to read 4, iclass 10, count 0 2006.260.07:53:12.05#ibcon#read 4, iclass 10, count 0 2006.260.07:53:12.05#ibcon#about to read 5, iclass 10, count 0 2006.260.07:53:12.05#ibcon#read 5, iclass 10, count 0 2006.260.07:53:12.05#ibcon#about to read 6, iclass 10, count 0 2006.260.07:53:12.05#ibcon#read 6, iclass 10, count 0 2006.260.07:53:12.05#ibcon#end of sib2, iclass 10, count 0 2006.260.07:53:12.05#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:53:12.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:53:12.05#ibcon#[27=USB\r\n] 2006.260.07:53:12.05#ibcon#*before write, iclass 10, count 0 2006.260.07:53:12.05#ibcon#enter sib2, iclass 10, count 0 2006.260.07:53:12.05#ibcon#flushed, iclass 10, count 0 2006.260.07:53:12.05#ibcon#about to write, iclass 10, count 0 2006.260.07:53:12.05#ibcon#wrote, iclass 10, count 0 2006.260.07:53:12.05#ibcon#about to read 3, iclass 10, count 0 2006.260.07:53:12.08#ibcon#read 3, iclass 10, count 0 2006.260.07:53:12.08#ibcon#about to read 4, iclass 10, count 0 2006.260.07:53:12.08#ibcon#read 4, iclass 10, count 0 2006.260.07:53:12.08#ibcon#about to read 5, iclass 10, count 0 2006.260.07:53:12.08#ibcon#read 5, iclass 10, count 0 2006.260.07:53:12.08#ibcon#about to read 6, iclass 10, count 0 2006.260.07:53:12.08#ibcon#read 6, iclass 10, count 0 2006.260.07:53:12.08#ibcon#end of sib2, iclass 10, count 0 2006.260.07:53:12.08#ibcon#*after write, iclass 10, count 0 2006.260.07:53:12.08#ibcon#*before return 0, iclass 10, count 0 2006.260.07:53:12.08#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:53:12.08#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.07:53:12.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:53:12.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:53:12.08$vc4f8/vblo=2,640.99 2006.260.07:53:12.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.07:53:12.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.07:53:12.08#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:12.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:12.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:12.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:12.08#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:53:12.08#ibcon#first serial, iclass 12, count 0 2006.260.07:53:12.08#ibcon#enter sib2, iclass 12, count 0 2006.260.07:53:12.08#ibcon#flushed, iclass 12, count 0 2006.260.07:53:12.08#ibcon#about to write, iclass 12, count 0 2006.260.07:53:12.08#ibcon#wrote, iclass 12, count 0 2006.260.07:53:12.08#ibcon#about to read 3, iclass 12, count 0 2006.260.07:53:12.10#ibcon#read 3, iclass 12, count 0 2006.260.07:53:12.10#ibcon#about to read 4, iclass 12, count 0 2006.260.07:53:12.10#ibcon#read 4, iclass 12, count 0 2006.260.07:53:12.10#ibcon#about to read 5, iclass 12, count 0 2006.260.07:53:12.10#ibcon#read 5, iclass 12, count 0 2006.260.07:53:12.10#ibcon#about to read 6, iclass 12, count 0 2006.260.07:53:12.10#ibcon#read 6, iclass 12, count 0 2006.260.07:53:12.10#ibcon#end of sib2, iclass 12, count 0 2006.260.07:53:12.10#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:53:12.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:53:12.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:53:12.10#ibcon#*before write, iclass 12, count 0 2006.260.07:53:12.10#ibcon#enter sib2, iclass 12, count 0 2006.260.07:53:12.10#ibcon#flushed, iclass 12, count 0 2006.260.07:53:12.10#ibcon#about to write, iclass 12, count 0 2006.260.07:53:12.10#ibcon#wrote, iclass 12, count 0 2006.260.07:53:12.11#ibcon#about to read 3, iclass 12, count 0 2006.260.07:53:12.14#ibcon#read 3, iclass 12, count 0 2006.260.07:53:12.14#ibcon#about to read 4, iclass 12, count 0 2006.260.07:53:12.14#ibcon#read 4, iclass 12, count 0 2006.260.07:53:12.14#ibcon#about to read 5, iclass 12, count 0 2006.260.07:53:12.14#ibcon#read 5, iclass 12, count 0 2006.260.07:53:12.14#ibcon#about to read 6, iclass 12, count 0 2006.260.07:53:12.14#ibcon#read 6, iclass 12, count 0 2006.260.07:53:12.14#ibcon#end of sib2, iclass 12, count 0 2006.260.07:53:12.14#ibcon#*after write, iclass 12, count 0 2006.260.07:53:12.14#ibcon#*before return 0, iclass 12, count 0 2006.260.07:53:12.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:12.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.07:53:12.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:53:12.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:53:12.14$vc4f8/vb=2,5 2006.260.07:53:12.14#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.07:53:12.14#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.07:53:12.14#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:12.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:12.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:12.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:12.20#ibcon#enter wrdev, iclass 14, count 2 2006.260.07:53:12.20#ibcon#first serial, iclass 14, count 2 2006.260.07:53:12.20#ibcon#enter sib2, iclass 14, count 2 2006.260.07:53:12.20#ibcon#flushed, iclass 14, count 2 2006.260.07:53:12.20#ibcon#about to write, iclass 14, count 2 2006.260.07:53:12.20#ibcon#wrote, iclass 14, count 2 2006.260.07:53:12.20#ibcon#about to read 3, iclass 14, count 2 2006.260.07:53:12.22#ibcon#read 3, iclass 14, count 2 2006.260.07:53:12.22#ibcon#about to read 4, iclass 14, count 2 2006.260.07:53:12.22#ibcon#read 4, iclass 14, count 2 2006.260.07:53:12.22#ibcon#about to read 5, iclass 14, count 2 2006.260.07:53:12.22#ibcon#read 5, iclass 14, count 2 2006.260.07:53:12.22#ibcon#about to read 6, iclass 14, count 2 2006.260.07:53:12.22#ibcon#read 6, iclass 14, count 2 2006.260.07:53:12.22#ibcon#end of sib2, iclass 14, count 2 2006.260.07:53:12.22#ibcon#*mode == 0, iclass 14, count 2 2006.260.07:53:12.22#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.07:53:12.22#ibcon#[27=AT02-05\r\n] 2006.260.07:53:12.22#ibcon#*before write, iclass 14, count 2 2006.260.07:53:12.22#ibcon#enter sib2, iclass 14, count 2 2006.260.07:53:12.22#ibcon#flushed, iclass 14, count 2 2006.260.07:53:12.22#ibcon#about to write, iclass 14, count 2 2006.260.07:53:12.22#ibcon#wrote, iclass 14, count 2 2006.260.07:53:12.22#ibcon#about to read 3, iclass 14, count 2 2006.260.07:53:12.25#ibcon#read 3, iclass 14, count 2 2006.260.07:53:12.25#ibcon#about to read 4, iclass 14, count 2 2006.260.07:53:12.25#ibcon#read 4, iclass 14, count 2 2006.260.07:53:12.25#ibcon#about to read 5, iclass 14, count 2 2006.260.07:53:12.25#ibcon#read 5, iclass 14, count 2 2006.260.07:53:12.25#ibcon#about to read 6, iclass 14, count 2 2006.260.07:53:12.25#ibcon#read 6, iclass 14, count 2 2006.260.07:53:12.25#ibcon#end of sib2, iclass 14, count 2 2006.260.07:53:12.25#ibcon#*after write, iclass 14, count 2 2006.260.07:53:12.25#ibcon#*before return 0, iclass 14, count 2 2006.260.07:53:12.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:12.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.07:53:12.25#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.07:53:12.25#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:12.25#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:12.37#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:12.37#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:12.37#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:53:12.37#ibcon#first serial, iclass 14, count 0 2006.260.07:53:12.37#ibcon#enter sib2, iclass 14, count 0 2006.260.07:53:12.37#ibcon#flushed, iclass 14, count 0 2006.260.07:53:12.37#ibcon#about to write, iclass 14, count 0 2006.260.07:53:12.37#ibcon#wrote, iclass 14, count 0 2006.260.07:53:12.37#ibcon#about to read 3, iclass 14, count 0 2006.260.07:53:12.39#ibcon#read 3, iclass 14, count 0 2006.260.07:53:12.39#ibcon#about to read 4, iclass 14, count 0 2006.260.07:53:12.39#ibcon#read 4, iclass 14, count 0 2006.260.07:53:12.39#ibcon#about to read 5, iclass 14, count 0 2006.260.07:53:12.39#ibcon#read 5, iclass 14, count 0 2006.260.07:53:12.39#ibcon#about to read 6, iclass 14, count 0 2006.260.07:53:12.39#ibcon#read 6, iclass 14, count 0 2006.260.07:53:12.39#ibcon#end of sib2, iclass 14, count 0 2006.260.07:53:12.39#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:53:12.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:53:12.39#ibcon#[27=USB\r\n] 2006.260.07:53:12.39#ibcon#*before write, iclass 14, count 0 2006.260.07:53:12.39#ibcon#enter sib2, iclass 14, count 0 2006.260.07:53:12.39#ibcon#flushed, iclass 14, count 0 2006.260.07:53:12.39#ibcon#about to write, iclass 14, count 0 2006.260.07:53:12.39#ibcon#wrote, iclass 14, count 0 2006.260.07:53:12.39#ibcon#about to read 3, iclass 14, count 0 2006.260.07:53:12.42#ibcon#read 3, iclass 14, count 0 2006.260.07:53:12.42#ibcon#about to read 4, iclass 14, count 0 2006.260.07:53:12.42#ibcon#read 4, iclass 14, count 0 2006.260.07:53:12.42#ibcon#about to read 5, iclass 14, count 0 2006.260.07:53:12.42#ibcon#read 5, iclass 14, count 0 2006.260.07:53:12.42#ibcon#about to read 6, iclass 14, count 0 2006.260.07:53:12.42#ibcon#read 6, iclass 14, count 0 2006.260.07:53:12.42#ibcon#end of sib2, iclass 14, count 0 2006.260.07:53:12.42#ibcon#*after write, iclass 14, count 0 2006.260.07:53:12.42#ibcon#*before return 0, iclass 14, count 0 2006.260.07:53:12.42#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:12.42#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.07:53:12.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:53:12.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:53:12.42$vc4f8/vblo=3,656.99 2006.260.07:53:12.42#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.07:53:12.42#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.07:53:12.42#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:12.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:12.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:12.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:12.42#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:53:12.42#ibcon#first serial, iclass 16, count 0 2006.260.07:53:12.42#ibcon#enter sib2, iclass 16, count 0 2006.260.07:53:12.42#ibcon#flushed, iclass 16, count 0 2006.260.07:53:12.42#ibcon#about to write, iclass 16, count 0 2006.260.07:53:12.42#ibcon#wrote, iclass 16, count 0 2006.260.07:53:12.42#ibcon#about to read 3, iclass 16, count 0 2006.260.07:53:12.44#ibcon#read 3, iclass 16, count 0 2006.260.07:53:12.44#ibcon#about to read 4, iclass 16, count 0 2006.260.07:53:12.44#ibcon#read 4, iclass 16, count 0 2006.260.07:53:12.44#ibcon#about to read 5, iclass 16, count 0 2006.260.07:53:12.44#ibcon#read 5, iclass 16, count 0 2006.260.07:53:12.44#ibcon#about to read 6, iclass 16, count 0 2006.260.07:53:12.44#ibcon#read 6, iclass 16, count 0 2006.260.07:53:12.44#ibcon#end of sib2, iclass 16, count 0 2006.260.07:53:12.44#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:53:12.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:53:12.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:53:12.44#ibcon#*before write, iclass 16, count 0 2006.260.07:53:12.44#ibcon#enter sib2, iclass 16, count 0 2006.260.07:53:12.44#ibcon#flushed, iclass 16, count 0 2006.260.07:53:12.44#ibcon#about to write, iclass 16, count 0 2006.260.07:53:12.44#ibcon#wrote, iclass 16, count 0 2006.260.07:53:12.44#ibcon#about to read 3, iclass 16, count 0 2006.260.07:53:12.48#ibcon#read 3, iclass 16, count 0 2006.260.07:53:12.48#ibcon#about to read 4, iclass 16, count 0 2006.260.07:53:12.48#ibcon#read 4, iclass 16, count 0 2006.260.07:53:12.48#ibcon#about to read 5, iclass 16, count 0 2006.260.07:53:12.48#ibcon#read 5, iclass 16, count 0 2006.260.07:53:12.48#ibcon#about to read 6, iclass 16, count 0 2006.260.07:53:12.48#ibcon#read 6, iclass 16, count 0 2006.260.07:53:12.48#ibcon#end of sib2, iclass 16, count 0 2006.260.07:53:12.48#ibcon#*after write, iclass 16, count 0 2006.260.07:53:12.48#ibcon#*before return 0, iclass 16, count 0 2006.260.07:53:12.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:12.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.07:53:12.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:53:12.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:53:12.48$vc4f8/vb=3,4 2006.260.07:53:12.48#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.07:53:12.48#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.07:53:12.48#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:12.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:12.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:12.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:12.54#ibcon#enter wrdev, iclass 18, count 2 2006.260.07:53:12.54#ibcon#first serial, iclass 18, count 2 2006.260.07:53:12.54#ibcon#enter sib2, iclass 18, count 2 2006.260.07:53:12.54#ibcon#flushed, iclass 18, count 2 2006.260.07:53:12.54#ibcon#about to write, iclass 18, count 2 2006.260.07:53:12.54#ibcon#wrote, iclass 18, count 2 2006.260.07:53:12.54#ibcon#about to read 3, iclass 18, count 2 2006.260.07:53:12.56#ibcon#read 3, iclass 18, count 2 2006.260.07:53:12.56#ibcon#about to read 4, iclass 18, count 2 2006.260.07:53:12.56#ibcon#read 4, iclass 18, count 2 2006.260.07:53:12.56#ibcon#about to read 5, iclass 18, count 2 2006.260.07:53:12.56#ibcon#read 5, iclass 18, count 2 2006.260.07:53:12.56#ibcon#about to read 6, iclass 18, count 2 2006.260.07:53:12.56#ibcon#read 6, iclass 18, count 2 2006.260.07:53:12.56#ibcon#end of sib2, iclass 18, count 2 2006.260.07:53:12.56#ibcon#*mode == 0, iclass 18, count 2 2006.260.07:53:12.56#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.07:53:12.56#ibcon#[27=AT03-04\r\n] 2006.260.07:53:12.56#ibcon#*before write, iclass 18, count 2 2006.260.07:53:12.56#ibcon#enter sib2, iclass 18, count 2 2006.260.07:53:12.56#ibcon#flushed, iclass 18, count 2 2006.260.07:53:12.56#ibcon#about to write, iclass 18, count 2 2006.260.07:53:12.56#ibcon#wrote, iclass 18, count 2 2006.260.07:53:12.56#ibcon#about to read 3, iclass 18, count 2 2006.260.07:53:12.59#ibcon#read 3, iclass 18, count 2 2006.260.07:53:12.59#ibcon#about to read 4, iclass 18, count 2 2006.260.07:53:12.59#ibcon#read 4, iclass 18, count 2 2006.260.07:53:12.59#ibcon#about to read 5, iclass 18, count 2 2006.260.07:53:12.59#ibcon#read 5, iclass 18, count 2 2006.260.07:53:12.59#ibcon#about to read 6, iclass 18, count 2 2006.260.07:53:12.59#ibcon#read 6, iclass 18, count 2 2006.260.07:53:12.59#ibcon#end of sib2, iclass 18, count 2 2006.260.07:53:12.59#ibcon#*after write, iclass 18, count 2 2006.260.07:53:12.59#ibcon#*before return 0, iclass 18, count 2 2006.260.07:53:12.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:12.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.07:53:12.59#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.07:53:12.59#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:12.59#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:12.71#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:12.71#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:12.71#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:53:12.71#ibcon#first serial, iclass 18, count 0 2006.260.07:53:12.71#ibcon#enter sib2, iclass 18, count 0 2006.260.07:53:12.71#ibcon#flushed, iclass 18, count 0 2006.260.07:53:12.71#ibcon#about to write, iclass 18, count 0 2006.260.07:53:12.71#ibcon#wrote, iclass 18, count 0 2006.260.07:53:12.71#ibcon#about to read 3, iclass 18, count 0 2006.260.07:53:12.73#ibcon#read 3, iclass 18, count 0 2006.260.07:53:12.73#ibcon#about to read 4, iclass 18, count 0 2006.260.07:53:12.73#ibcon#read 4, iclass 18, count 0 2006.260.07:53:12.73#ibcon#about to read 5, iclass 18, count 0 2006.260.07:53:12.73#ibcon#read 5, iclass 18, count 0 2006.260.07:53:12.73#ibcon#about to read 6, iclass 18, count 0 2006.260.07:53:12.73#ibcon#read 6, iclass 18, count 0 2006.260.07:53:12.73#ibcon#end of sib2, iclass 18, count 0 2006.260.07:53:12.73#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:53:12.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:53:12.73#ibcon#[27=USB\r\n] 2006.260.07:53:12.73#ibcon#*before write, iclass 18, count 0 2006.260.07:53:12.73#ibcon#enter sib2, iclass 18, count 0 2006.260.07:53:12.73#ibcon#flushed, iclass 18, count 0 2006.260.07:53:12.73#ibcon#about to write, iclass 18, count 0 2006.260.07:53:12.73#ibcon#wrote, iclass 18, count 0 2006.260.07:53:12.73#ibcon#about to read 3, iclass 18, count 0 2006.260.07:53:12.76#ibcon#read 3, iclass 18, count 0 2006.260.07:53:12.76#ibcon#about to read 4, iclass 18, count 0 2006.260.07:53:12.76#ibcon#read 4, iclass 18, count 0 2006.260.07:53:12.76#ibcon#about to read 5, iclass 18, count 0 2006.260.07:53:12.76#ibcon#read 5, iclass 18, count 0 2006.260.07:53:12.76#ibcon#about to read 6, iclass 18, count 0 2006.260.07:53:12.76#ibcon#read 6, iclass 18, count 0 2006.260.07:53:12.76#ibcon#end of sib2, iclass 18, count 0 2006.260.07:53:12.76#ibcon#*after write, iclass 18, count 0 2006.260.07:53:12.76#ibcon#*before return 0, iclass 18, count 0 2006.260.07:53:12.76#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:12.76#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.07:53:12.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:53:12.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:53:12.76$vc4f8/vblo=4,712.99 2006.260.07:53:12.76#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.07:53:12.76#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.07:53:12.76#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:12.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:12.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:12.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:12.76#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:53:12.76#ibcon#first serial, iclass 20, count 0 2006.260.07:53:12.76#ibcon#enter sib2, iclass 20, count 0 2006.260.07:53:12.76#ibcon#flushed, iclass 20, count 0 2006.260.07:53:12.76#ibcon#about to write, iclass 20, count 0 2006.260.07:53:12.76#ibcon#wrote, iclass 20, count 0 2006.260.07:53:12.76#ibcon#about to read 3, iclass 20, count 0 2006.260.07:53:12.78#ibcon#read 3, iclass 20, count 0 2006.260.07:53:12.78#ibcon#about to read 4, iclass 20, count 0 2006.260.07:53:12.78#ibcon#read 4, iclass 20, count 0 2006.260.07:53:12.78#ibcon#about to read 5, iclass 20, count 0 2006.260.07:53:12.78#ibcon#read 5, iclass 20, count 0 2006.260.07:53:12.78#ibcon#about to read 6, iclass 20, count 0 2006.260.07:53:12.78#ibcon#read 6, iclass 20, count 0 2006.260.07:53:12.78#ibcon#end of sib2, iclass 20, count 0 2006.260.07:53:12.78#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:53:12.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:53:12.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:53:12.78#ibcon#*before write, iclass 20, count 0 2006.260.07:53:12.78#ibcon#enter sib2, iclass 20, count 0 2006.260.07:53:12.78#ibcon#flushed, iclass 20, count 0 2006.260.07:53:12.78#ibcon#about to write, iclass 20, count 0 2006.260.07:53:12.78#ibcon#wrote, iclass 20, count 0 2006.260.07:53:12.78#ibcon#about to read 3, iclass 20, count 0 2006.260.07:53:12.82#ibcon#read 3, iclass 20, count 0 2006.260.07:53:12.82#ibcon#about to read 4, iclass 20, count 0 2006.260.07:53:12.82#ibcon#read 4, iclass 20, count 0 2006.260.07:53:12.82#ibcon#about to read 5, iclass 20, count 0 2006.260.07:53:12.82#ibcon#read 5, iclass 20, count 0 2006.260.07:53:12.82#ibcon#about to read 6, iclass 20, count 0 2006.260.07:53:12.82#ibcon#read 6, iclass 20, count 0 2006.260.07:53:12.82#ibcon#end of sib2, iclass 20, count 0 2006.260.07:53:12.82#ibcon#*after write, iclass 20, count 0 2006.260.07:53:12.82#ibcon#*before return 0, iclass 20, count 0 2006.260.07:53:12.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:12.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.07:53:12.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:53:12.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:53:12.82$vc4f8/vb=4,5 2006.260.07:53:12.82#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.07:53:12.82#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.07:53:12.82#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:12.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:12.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:12.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:12.88#ibcon#enter wrdev, iclass 22, count 2 2006.260.07:53:12.88#ibcon#first serial, iclass 22, count 2 2006.260.07:53:12.88#ibcon#enter sib2, iclass 22, count 2 2006.260.07:53:12.88#ibcon#flushed, iclass 22, count 2 2006.260.07:53:12.88#ibcon#about to write, iclass 22, count 2 2006.260.07:53:12.88#ibcon#wrote, iclass 22, count 2 2006.260.07:53:12.88#ibcon#about to read 3, iclass 22, count 2 2006.260.07:53:12.90#ibcon#read 3, iclass 22, count 2 2006.260.07:53:12.90#ibcon#about to read 4, iclass 22, count 2 2006.260.07:53:12.90#ibcon#read 4, iclass 22, count 2 2006.260.07:53:12.90#ibcon#about to read 5, iclass 22, count 2 2006.260.07:53:12.90#ibcon#read 5, iclass 22, count 2 2006.260.07:53:12.90#ibcon#about to read 6, iclass 22, count 2 2006.260.07:53:12.90#ibcon#read 6, iclass 22, count 2 2006.260.07:53:12.90#ibcon#end of sib2, iclass 22, count 2 2006.260.07:53:12.90#ibcon#*mode == 0, iclass 22, count 2 2006.260.07:53:12.90#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.07:53:12.90#ibcon#[27=AT04-05\r\n] 2006.260.07:53:12.90#ibcon#*before write, iclass 22, count 2 2006.260.07:53:12.90#ibcon#enter sib2, iclass 22, count 2 2006.260.07:53:12.90#ibcon#flushed, iclass 22, count 2 2006.260.07:53:12.90#ibcon#about to write, iclass 22, count 2 2006.260.07:53:12.90#ibcon#wrote, iclass 22, count 2 2006.260.07:53:12.90#ibcon#about to read 3, iclass 22, count 2 2006.260.07:53:12.93#ibcon#read 3, iclass 22, count 2 2006.260.07:53:12.93#ibcon#about to read 4, iclass 22, count 2 2006.260.07:53:12.93#ibcon#read 4, iclass 22, count 2 2006.260.07:53:12.93#ibcon#about to read 5, iclass 22, count 2 2006.260.07:53:12.93#ibcon#read 5, iclass 22, count 2 2006.260.07:53:12.93#ibcon#about to read 6, iclass 22, count 2 2006.260.07:53:12.93#ibcon#read 6, iclass 22, count 2 2006.260.07:53:12.93#ibcon#end of sib2, iclass 22, count 2 2006.260.07:53:12.93#ibcon#*after write, iclass 22, count 2 2006.260.07:53:12.93#ibcon#*before return 0, iclass 22, count 2 2006.260.07:53:12.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:12.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.07:53:12.93#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.07:53:12.93#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:12.93#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:13.05#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:13.05#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:13.05#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:53:13.05#ibcon#first serial, iclass 22, count 0 2006.260.07:53:13.05#ibcon#enter sib2, iclass 22, count 0 2006.260.07:53:13.05#ibcon#flushed, iclass 22, count 0 2006.260.07:53:13.05#ibcon#about to write, iclass 22, count 0 2006.260.07:53:13.05#ibcon#wrote, iclass 22, count 0 2006.260.07:53:13.05#ibcon#about to read 3, iclass 22, count 0 2006.260.07:53:13.07#ibcon#read 3, iclass 22, count 0 2006.260.07:53:13.07#ibcon#about to read 4, iclass 22, count 0 2006.260.07:53:13.07#ibcon#read 4, iclass 22, count 0 2006.260.07:53:13.07#ibcon#about to read 5, iclass 22, count 0 2006.260.07:53:13.07#ibcon#read 5, iclass 22, count 0 2006.260.07:53:13.07#ibcon#about to read 6, iclass 22, count 0 2006.260.07:53:13.07#ibcon#read 6, iclass 22, count 0 2006.260.07:53:13.07#ibcon#end of sib2, iclass 22, count 0 2006.260.07:53:13.07#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:53:13.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:53:13.07#ibcon#[27=USB\r\n] 2006.260.07:53:13.07#ibcon#*before write, iclass 22, count 0 2006.260.07:53:13.07#ibcon#enter sib2, iclass 22, count 0 2006.260.07:53:13.07#ibcon#flushed, iclass 22, count 0 2006.260.07:53:13.07#ibcon#about to write, iclass 22, count 0 2006.260.07:53:13.07#ibcon#wrote, iclass 22, count 0 2006.260.07:53:13.07#ibcon#about to read 3, iclass 22, count 0 2006.260.07:53:13.10#ibcon#read 3, iclass 22, count 0 2006.260.07:53:13.10#ibcon#about to read 4, iclass 22, count 0 2006.260.07:53:13.10#ibcon#read 4, iclass 22, count 0 2006.260.07:53:13.10#ibcon#about to read 5, iclass 22, count 0 2006.260.07:53:13.10#ibcon#read 5, iclass 22, count 0 2006.260.07:53:13.10#ibcon#about to read 6, iclass 22, count 0 2006.260.07:53:13.10#ibcon#read 6, iclass 22, count 0 2006.260.07:53:13.10#ibcon#end of sib2, iclass 22, count 0 2006.260.07:53:13.10#ibcon#*after write, iclass 22, count 0 2006.260.07:53:13.10#ibcon#*before return 0, iclass 22, count 0 2006.260.07:53:13.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:13.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.07:53:13.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:53:13.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:53:13.10$vc4f8/vblo=5,744.99 2006.260.07:53:13.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:53:13.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:53:13.10#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:13.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:13.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:13.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:13.10#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:53:13.10#ibcon#first serial, iclass 24, count 0 2006.260.07:53:13.10#ibcon#enter sib2, iclass 24, count 0 2006.260.07:53:13.10#ibcon#flushed, iclass 24, count 0 2006.260.07:53:13.10#ibcon#about to write, iclass 24, count 0 2006.260.07:53:13.10#ibcon#wrote, iclass 24, count 0 2006.260.07:53:13.10#ibcon#about to read 3, iclass 24, count 0 2006.260.07:53:13.12#ibcon#read 3, iclass 24, count 0 2006.260.07:53:13.12#ibcon#about to read 4, iclass 24, count 0 2006.260.07:53:13.12#ibcon#read 4, iclass 24, count 0 2006.260.07:53:13.12#ibcon#about to read 5, iclass 24, count 0 2006.260.07:53:13.12#ibcon#read 5, iclass 24, count 0 2006.260.07:53:13.12#ibcon#about to read 6, iclass 24, count 0 2006.260.07:53:13.12#ibcon#read 6, iclass 24, count 0 2006.260.07:53:13.12#ibcon#end of sib2, iclass 24, count 0 2006.260.07:53:13.12#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:53:13.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:53:13.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:53:13.12#ibcon#*before write, iclass 24, count 0 2006.260.07:53:13.12#ibcon#enter sib2, iclass 24, count 0 2006.260.07:53:13.12#ibcon#flushed, iclass 24, count 0 2006.260.07:53:13.12#ibcon#about to write, iclass 24, count 0 2006.260.07:53:13.12#ibcon#wrote, iclass 24, count 0 2006.260.07:53:13.12#ibcon#about to read 3, iclass 24, count 0 2006.260.07:53:13.16#ibcon#read 3, iclass 24, count 0 2006.260.07:53:13.16#ibcon#about to read 4, iclass 24, count 0 2006.260.07:53:13.16#ibcon#read 4, iclass 24, count 0 2006.260.07:53:13.16#ibcon#about to read 5, iclass 24, count 0 2006.260.07:53:13.16#ibcon#read 5, iclass 24, count 0 2006.260.07:53:13.16#ibcon#about to read 6, iclass 24, count 0 2006.260.07:53:13.16#ibcon#read 6, iclass 24, count 0 2006.260.07:53:13.16#ibcon#end of sib2, iclass 24, count 0 2006.260.07:53:13.16#ibcon#*after write, iclass 24, count 0 2006.260.07:53:13.16#ibcon#*before return 0, iclass 24, count 0 2006.260.07:53:13.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:13.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:53:13.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:53:13.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:53:13.16$vc4f8/vb=5,4 2006.260.07:53:13.16#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.07:53:13.16#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.07:53:13.16#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:13.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:13.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:13.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:13.22#ibcon#enter wrdev, iclass 26, count 2 2006.260.07:53:13.22#ibcon#first serial, iclass 26, count 2 2006.260.07:53:13.22#ibcon#enter sib2, iclass 26, count 2 2006.260.07:53:13.22#ibcon#flushed, iclass 26, count 2 2006.260.07:53:13.22#ibcon#about to write, iclass 26, count 2 2006.260.07:53:13.22#ibcon#wrote, iclass 26, count 2 2006.260.07:53:13.22#ibcon#about to read 3, iclass 26, count 2 2006.260.07:53:13.24#ibcon#read 3, iclass 26, count 2 2006.260.07:53:13.24#ibcon#about to read 4, iclass 26, count 2 2006.260.07:53:13.24#ibcon#read 4, iclass 26, count 2 2006.260.07:53:13.24#ibcon#about to read 5, iclass 26, count 2 2006.260.07:53:13.24#ibcon#read 5, iclass 26, count 2 2006.260.07:53:13.24#ibcon#about to read 6, iclass 26, count 2 2006.260.07:53:13.24#ibcon#read 6, iclass 26, count 2 2006.260.07:53:13.24#ibcon#end of sib2, iclass 26, count 2 2006.260.07:53:13.24#ibcon#*mode == 0, iclass 26, count 2 2006.260.07:53:13.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.07:53:13.24#ibcon#[27=AT05-04\r\n] 2006.260.07:53:13.24#ibcon#*before write, iclass 26, count 2 2006.260.07:53:13.24#ibcon#enter sib2, iclass 26, count 2 2006.260.07:53:13.24#ibcon#flushed, iclass 26, count 2 2006.260.07:53:13.24#ibcon#about to write, iclass 26, count 2 2006.260.07:53:13.24#ibcon#wrote, iclass 26, count 2 2006.260.07:53:13.24#ibcon#about to read 3, iclass 26, count 2 2006.260.07:53:13.27#ibcon#read 3, iclass 26, count 2 2006.260.07:53:13.27#ibcon#about to read 4, iclass 26, count 2 2006.260.07:53:13.27#ibcon#read 4, iclass 26, count 2 2006.260.07:53:13.27#ibcon#about to read 5, iclass 26, count 2 2006.260.07:53:13.27#ibcon#read 5, iclass 26, count 2 2006.260.07:53:13.27#ibcon#about to read 6, iclass 26, count 2 2006.260.07:53:13.27#ibcon#read 6, iclass 26, count 2 2006.260.07:53:13.27#ibcon#end of sib2, iclass 26, count 2 2006.260.07:53:13.27#ibcon#*after write, iclass 26, count 2 2006.260.07:53:13.27#ibcon#*before return 0, iclass 26, count 2 2006.260.07:53:13.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:13.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.07:53:13.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.07:53:13.27#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:13.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:13.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:13.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:13.39#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:53:13.39#ibcon#first serial, iclass 26, count 0 2006.260.07:53:13.39#ibcon#enter sib2, iclass 26, count 0 2006.260.07:53:13.39#ibcon#flushed, iclass 26, count 0 2006.260.07:53:13.39#ibcon#about to write, iclass 26, count 0 2006.260.07:53:13.39#ibcon#wrote, iclass 26, count 0 2006.260.07:53:13.39#ibcon#about to read 3, iclass 26, count 0 2006.260.07:53:13.41#ibcon#read 3, iclass 26, count 0 2006.260.07:53:13.41#ibcon#about to read 4, iclass 26, count 0 2006.260.07:53:13.41#ibcon#read 4, iclass 26, count 0 2006.260.07:53:13.41#ibcon#about to read 5, iclass 26, count 0 2006.260.07:53:13.41#ibcon#read 5, iclass 26, count 0 2006.260.07:53:13.41#ibcon#about to read 6, iclass 26, count 0 2006.260.07:53:13.41#ibcon#read 6, iclass 26, count 0 2006.260.07:53:13.41#ibcon#end of sib2, iclass 26, count 0 2006.260.07:53:13.41#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:53:13.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:53:13.41#ibcon#[27=USB\r\n] 2006.260.07:53:13.41#ibcon#*before write, iclass 26, count 0 2006.260.07:53:13.41#ibcon#enter sib2, iclass 26, count 0 2006.260.07:53:13.41#ibcon#flushed, iclass 26, count 0 2006.260.07:53:13.41#ibcon#about to write, iclass 26, count 0 2006.260.07:53:13.41#ibcon#wrote, iclass 26, count 0 2006.260.07:53:13.41#ibcon#about to read 3, iclass 26, count 0 2006.260.07:53:13.44#ibcon#read 3, iclass 26, count 0 2006.260.07:53:13.44#ibcon#about to read 4, iclass 26, count 0 2006.260.07:53:13.44#ibcon#read 4, iclass 26, count 0 2006.260.07:53:13.44#ibcon#about to read 5, iclass 26, count 0 2006.260.07:53:13.44#ibcon#read 5, iclass 26, count 0 2006.260.07:53:13.44#ibcon#about to read 6, iclass 26, count 0 2006.260.07:53:13.44#ibcon#read 6, iclass 26, count 0 2006.260.07:53:13.44#ibcon#end of sib2, iclass 26, count 0 2006.260.07:53:13.44#ibcon#*after write, iclass 26, count 0 2006.260.07:53:13.44#ibcon#*before return 0, iclass 26, count 0 2006.260.07:53:13.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:13.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.07:53:13.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:53:13.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:53:13.44$vc4f8/vblo=6,752.99 2006.260.07:53:13.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.07:53:13.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.07:53:13.44#ibcon#ireg 17 cls_cnt 0 2006.260.07:53:13.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:13.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:13.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:13.44#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:53:13.44#ibcon#first serial, iclass 28, count 0 2006.260.07:53:13.44#ibcon#enter sib2, iclass 28, count 0 2006.260.07:53:13.44#ibcon#flushed, iclass 28, count 0 2006.260.07:53:13.44#ibcon#about to write, iclass 28, count 0 2006.260.07:53:13.44#ibcon#wrote, iclass 28, count 0 2006.260.07:53:13.44#ibcon#about to read 3, iclass 28, count 0 2006.260.07:53:13.46#ibcon#read 3, iclass 28, count 0 2006.260.07:53:13.46#ibcon#about to read 4, iclass 28, count 0 2006.260.07:53:13.46#ibcon#read 4, iclass 28, count 0 2006.260.07:53:13.46#ibcon#about to read 5, iclass 28, count 0 2006.260.07:53:13.46#ibcon#read 5, iclass 28, count 0 2006.260.07:53:13.46#ibcon#about to read 6, iclass 28, count 0 2006.260.07:53:13.46#ibcon#read 6, iclass 28, count 0 2006.260.07:53:13.46#ibcon#end of sib2, iclass 28, count 0 2006.260.07:53:13.46#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:53:13.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:53:13.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:53:13.46#ibcon#*before write, iclass 28, count 0 2006.260.07:53:13.46#ibcon#enter sib2, iclass 28, count 0 2006.260.07:53:13.46#ibcon#flushed, iclass 28, count 0 2006.260.07:53:13.46#ibcon#about to write, iclass 28, count 0 2006.260.07:53:13.46#ibcon#wrote, iclass 28, count 0 2006.260.07:53:13.46#ibcon#about to read 3, iclass 28, count 0 2006.260.07:53:13.50#ibcon#read 3, iclass 28, count 0 2006.260.07:53:13.50#ibcon#about to read 4, iclass 28, count 0 2006.260.07:53:13.50#ibcon#read 4, iclass 28, count 0 2006.260.07:53:13.50#ibcon#about to read 5, iclass 28, count 0 2006.260.07:53:13.50#ibcon#read 5, iclass 28, count 0 2006.260.07:53:13.50#ibcon#about to read 6, iclass 28, count 0 2006.260.07:53:13.50#ibcon#read 6, iclass 28, count 0 2006.260.07:53:13.50#ibcon#end of sib2, iclass 28, count 0 2006.260.07:53:13.50#ibcon#*after write, iclass 28, count 0 2006.260.07:53:13.50#ibcon#*before return 0, iclass 28, count 0 2006.260.07:53:13.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:13.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.07:53:13.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:53:13.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:53:13.50$vc4f8/vb=6,4 2006.260.07:53:13.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.07:53:13.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.07:53:13.50#ibcon#ireg 11 cls_cnt 2 2006.260.07:53:13.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:13.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:13.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:13.56#ibcon#enter wrdev, iclass 30, count 2 2006.260.07:53:13.56#ibcon#first serial, iclass 30, count 2 2006.260.07:53:13.56#ibcon#enter sib2, iclass 30, count 2 2006.260.07:53:13.56#ibcon#flushed, iclass 30, count 2 2006.260.07:53:13.56#ibcon#about to write, iclass 30, count 2 2006.260.07:53:13.56#ibcon#wrote, iclass 30, count 2 2006.260.07:53:13.56#ibcon#about to read 3, iclass 30, count 2 2006.260.07:53:13.58#ibcon#read 3, iclass 30, count 2 2006.260.07:53:13.58#ibcon#about to read 4, iclass 30, count 2 2006.260.07:53:13.58#ibcon#read 4, iclass 30, count 2 2006.260.07:53:13.58#ibcon#about to read 5, iclass 30, count 2 2006.260.07:53:13.58#ibcon#read 5, iclass 30, count 2 2006.260.07:53:13.58#ibcon#about to read 6, iclass 30, count 2 2006.260.07:53:13.58#ibcon#read 6, iclass 30, count 2 2006.260.07:53:13.58#ibcon#end of sib2, iclass 30, count 2 2006.260.07:53:13.58#ibcon#*mode == 0, iclass 30, count 2 2006.260.07:53:13.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.07:53:13.58#ibcon#[27=AT06-04\r\n] 2006.260.07:53:13.58#ibcon#*before write, iclass 30, count 2 2006.260.07:53:13.58#ibcon#enter sib2, iclass 30, count 2 2006.260.07:53:13.58#ibcon#flushed, iclass 30, count 2 2006.260.07:53:13.58#ibcon#about to write, iclass 30, count 2 2006.260.07:53:13.58#ibcon#wrote, iclass 30, count 2 2006.260.07:53:13.58#ibcon#about to read 3, iclass 30, count 2 2006.260.07:53:13.61#ibcon#read 3, iclass 30, count 2 2006.260.07:53:13.61#ibcon#about to read 4, iclass 30, count 2 2006.260.07:53:13.61#ibcon#read 4, iclass 30, count 2 2006.260.07:53:13.61#ibcon#about to read 5, iclass 30, count 2 2006.260.07:53:13.61#ibcon#read 5, iclass 30, count 2 2006.260.07:53:13.61#ibcon#about to read 6, iclass 30, count 2 2006.260.07:53:13.61#ibcon#read 6, iclass 30, count 2 2006.260.07:53:13.61#ibcon#end of sib2, iclass 30, count 2 2006.260.07:53:13.61#ibcon#*after write, iclass 30, count 2 2006.260.07:53:13.61#ibcon#*before return 0, iclass 30, count 2 2006.260.07:53:13.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:13.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.07:53:13.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.07:53:13.61#ibcon#ireg 7 cls_cnt 0 2006.260.07:53:13.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:13.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:13.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:13.73#ibcon#enter wrdev, iclass 30, count 0 2006.260.07:53:13.73#ibcon#first serial, iclass 30, count 0 2006.260.07:53:13.73#ibcon#enter sib2, iclass 30, count 0 2006.260.07:53:13.73#ibcon#flushed, iclass 30, count 0 2006.260.07:53:13.73#ibcon#about to write, iclass 30, count 0 2006.260.07:53:13.73#ibcon#wrote, iclass 30, count 0 2006.260.07:53:13.73#ibcon#about to read 3, iclass 30, count 0 2006.260.07:53:13.75#ibcon#read 3, iclass 30, count 0 2006.260.07:53:13.75#ibcon#about to read 4, iclass 30, count 0 2006.260.07:53:13.75#ibcon#read 4, iclass 30, count 0 2006.260.07:53:13.75#ibcon#about to read 5, iclass 30, count 0 2006.260.07:53:13.75#ibcon#read 5, iclass 30, count 0 2006.260.07:53:13.75#ibcon#about to read 6, iclass 30, count 0 2006.260.07:53:13.75#ibcon#read 6, iclass 30, count 0 2006.260.07:53:13.75#ibcon#end of sib2, iclass 30, count 0 2006.260.07:53:13.75#ibcon#*mode == 0, iclass 30, count 0 2006.260.07:53:13.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.07:53:13.75#ibcon#[27=USB\r\n] 2006.260.07:53:13.75#ibcon#*before write, iclass 30, count 0 2006.260.07:53:13.75#ibcon#enter sib2, iclass 30, count 0 2006.260.07:53:13.75#ibcon#flushed, iclass 30, count 0 2006.260.07:53:13.75#ibcon#about to write, iclass 30, count 0 2006.260.07:53:13.75#ibcon#wrote, iclass 30, count 0 2006.260.07:53:13.75#ibcon#about to read 3, iclass 30, count 0 2006.260.07:53:13.78#ibcon#read 3, iclass 30, count 0 2006.260.07:53:13.78#ibcon#about to read 4, iclass 30, count 0 2006.260.07:53:13.78#ibcon#read 4, iclass 30, count 0 2006.260.07:53:13.78#ibcon#about to read 5, iclass 30, count 0 2006.260.07:53:13.78#ibcon#read 5, iclass 30, count 0 2006.260.07:53:13.78#ibcon#about to read 6, iclass 30, count 0 2006.260.07:53:13.78#ibcon#read 6, iclass 30, count 0 2006.260.07:53:13.78#ibcon#end of sib2, iclass 30, count 0 2006.260.07:53:13.78#ibcon#*after write, iclass 30, count 0 2006.260.07:53:13.78#ibcon#*before return 0, iclass 30, count 0 2006.260.07:53:13.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:13.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.07:53:13.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.07:53:13.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.07:53:13.78$vc4f8/vabw=wide 2006.260.07:53:13.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.07:53:13.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.07:53:13.78#ibcon#ireg 8 cls_cnt 0 2006.260.07:53:13.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:13.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:13.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:13.78#ibcon#enter wrdev, iclass 32, count 0 2006.260.07:53:13.78#ibcon#first serial, iclass 32, count 0 2006.260.07:53:13.78#ibcon#enter sib2, iclass 32, count 0 2006.260.07:53:13.78#ibcon#flushed, iclass 32, count 0 2006.260.07:53:13.78#ibcon#about to write, iclass 32, count 0 2006.260.07:53:13.78#ibcon#wrote, iclass 32, count 0 2006.260.07:53:13.78#ibcon#about to read 3, iclass 32, count 0 2006.260.07:53:13.80#ibcon#read 3, iclass 32, count 0 2006.260.07:53:13.80#ibcon#about to read 4, iclass 32, count 0 2006.260.07:53:13.80#ibcon#read 4, iclass 32, count 0 2006.260.07:53:13.80#ibcon#about to read 5, iclass 32, count 0 2006.260.07:53:13.80#ibcon#read 5, iclass 32, count 0 2006.260.07:53:13.80#ibcon#about to read 6, iclass 32, count 0 2006.260.07:53:13.80#ibcon#read 6, iclass 32, count 0 2006.260.07:53:13.80#ibcon#end of sib2, iclass 32, count 0 2006.260.07:53:13.80#ibcon#*mode == 0, iclass 32, count 0 2006.260.07:53:13.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.07:53:13.80#ibcon#[25=BW32\r\n] 2006.260.07:53:13.80#ibcon#*before write, iclass 32, count 0 2006.260.07:53:13.80#ibcon#enter sib2, iclass 32, count 0 2006.260.07:53:13.80#ibcon#flushed, iclass 32, count 0 2006.260.07:53:13.80#ibcon#about to write, iclass 32, count 0 2006.260.07:53:13.80#ibcon#wrote, iclass 32, count 0 2006.260.07:53:13.80#ibcon#about to read 3, iclass 32, count 0 2006.260.07:53:13.83#ibcon#read 3, iclass 32, count 0 2006.260.07:53:13.83#ibcon#about to read 4, iclass 32, count 0 2006.260.07:53:13.83#ibcon#read 4, iclass 32, count 0 2006.260.07:53:13.83#ibcon#about to read 5, iclass 32, count 0 2006.260.07:53:13.83#ibcon#read 5, iclass 32, count 0 2006.260.07:53:13.83#ibcon#about to read 6, iclass 32, count 0 2006.260.07:53:13.83#ibcon#read 6, iclass 32, count 0 2006.260.07:53:13.83#ibcon#end of sib2, iclass 32, count 0 2006.260.07:53:13.83#ibcon#*after write, iclass 32, count 0 2006.260.07:53:13.83#ibcon#*before return 0, iclass 32, count 0 2006.260.07:53:13.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:13.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.07:53:13.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.07:53:13.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.07:53:13.83$vc4f8/vbbw=wide 2006.260.07:53:13.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:53:13.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:53:13.83#ibcon#ireg 8 cls_cnt 0 2006.260.07:53:13.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:53:13.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:53:13.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:53:13.90#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:53:13.90#ibcon#first serial, iclass 34, count 0 2006.260.07:53:13.90#ibcon#enter sib2, iclass 34, count 0 2006.260.07:53:13.90#ibcon#flushed, iclass 34, count 0 2006.260.07:53:13.90#ibcon#about to write, iclass 34, count 0 2006.260.07:53:13.90#ibcon#wrote, iclass 34, count 0 2006.260.07:53:13.90#ibcon#about to read 3, iclass 34, count 0 2006.260.07:53:13.92#ibcon#read 3, iclass 34, count 0 2006.260.07:53:13.92#ibcon#about to read 4, iclass 34, count 0 2006.260.07:53:13.92#ibcon#read 4, iclass 34, count 0 2006.260.07:53:13.92#ibcon#about to read 5, iclass 34, count 0 2006.260.07:53:13.92#ibcon#read 5, iclass 34, count 0 2006.260.07:53:13.92#ibcon#about to read 6, iclass 34, count 0 2006.260.07:53:13.92#ibcon#read 6, iclass 34, count 0 2006.260.07:53:13.92#ibcon#end of sib2, iclass 34, count 0 2006.260.07:53:13.92#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:53:13.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:53:13.92#ibcon#[27=BW32\r\n] 2006.260.07:53:13.92#ibcon#*before write, iclass 34, count 0 2006.260.07:53:13.92#ibcon#enter sib2, iclass 34, count 0 2006.260.07:53:13.92#ibcon#flushed, iclass 34, count 0 2006.260.07:53:13.92#ibcon#about to write, iclass 34, count 0 2006.260.07:53:13.92#ibcon#wrote, iclass 34, count 0 2006.260.07:53:13.92#ibcon#about to read 3, iclass 34, count 0 2006.260.07:53:13.95#ibcon#read 3, iclass 34, count 0 2006.260.07:53:13.95#ibcon#about to read 4, iclass 34, count 0 2006.260.07:53:13.95#ibcon#read 4, iclass 34, count 0 2006.260.07:53:13.95#ibcon#about to read 5, iclass 34, count 0 2006.260.07:53:13.95#ibcon#read 5, iclass 34, count 0 2006.260.07:53:13.95#ibcon#about to read 6, iclass 34, count 0 2006.260.07:53:13.95#ibcon#read 6, iclass 34, count 0 2006.260.07:53:13.95#ibcon#end of sib2, iclass 34, count 0 2006.260.07:53:13.95#ibcon#*after write, iclass 34, count 0 2006.260.07:53:13.95#ibcon#*before return 0, iclass 34, count 0 2006.260.07:53:13.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:53:13.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:53:13.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:53:13.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:53:13.95$4f8m12a/ifd4f 2006.260.07:53:13.95$ifd4f/lo= 2006.260.07:53:13.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:53:13.96$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:53:13.96$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:53:13.96$ifd4f/patch= 2006.260.07:53:13.96$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:53:13.96$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:53:13.96$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:53:13.96$4f8m12a/"form=m,16.000,1:2 2006.260.07:53:13.96$4f8m12a/"tpicd 2006.260.07:53:13.96$4f8m12a/echo=off 2006.260.07:53:13.96$4f8m12a/xlog=off 2006.260.07:53:13.96:!2006.260.07:54:50 2006.260.07:53:23.13#trakl#Source acquired 2006.260.07:53:25.13#flagr#flagr/antenna,acquired 2006.260.07:54:50.01:preob 2006.260.07:54:51.14/onsource/TRACKING 2006.260.07:54:51.14:!2006.260.07:55:00 2006.260.07:55:00.00:data_valid=on 2006.260.07:55:00.00:midob 2006.260.07:55:00.14/onsource/TRACKING 2006.260.07:55:00.14/wx/22.92,1010.4,88 2006.260.07:55:00.30/cable/+6.4565E-03 2006.260.07:55:01.39/va/01,08,usb,yes,34,36 2006.260.07:55:01.39/va/02,07,usb,yes,34,36 2006.260.07:55:01.39/va/03,08,usb,yes,26,26 2006.260.07:55:01.39/va/04,07,usb,yes,35,38 2006.260.07:55:01.39/va/05,07,usb,yes,39,41 2006.260.07:55:01.39/va/06,06,usb,yes,38,38 2006.260.07:55:01.39/va/07,06,usb,yes,39,39 2006.260.07:55:01.39/va/08,06,usb,yes,42,41 2006.260.07:55:01.62/valo/01,532.99,yes,locked 2006.260.07:55:01.62/valo/02,572.99,yes,locked 2006.260.07:55:01.62/valo/03,672.99,yes,locked 2006.260.07:55:01.62/valo/04,832.99,yes,locked 2006.260.07:55:01.62/valo/05,652.99,yes,locked 2006.260.07:55:01.62/valo/06,772.99,yes,locked 2006.260.07:55:01.62/valo/07,832.99,yes,locked 2006.260.07:55:01.62/valo/08,852.99,yes,locked 2006.260.07:55:02.71/vb/01,04,usb,yes,31,30 2006.260.07:55:02.71/vb/02,05,usb,yes,29,30 2006.260.07:55:02.71/vb/03,04,usb,yes,30,33 2006.260.07:55:02.71/vb/04,05,usb,yes,27,27 2006.260.07:55:02.71/vb/05,04,usb,yes,29,34 2006.260.07:55:02.71/vb/06,04,usb,yes,30,33 2006.260.07:55:02.71/vb/07,04,usb,yes,32,33 2006.260.07:55:02.71/vb/08,04,usb,yes,30,33 2006.260.07:55:02.95/vblo/01,632.99,yes,locked 2006.260.07:55:02.95/vblo/02,640.99,yes,locked 2006.260.07:55:02.95/vblo/03,656.99,yes,locked 2006.260.07:55:02.95/vblo/04,712.99,yes,locked 2006.260.07:55:02.95/vblo/05,744.99,yes,locked 2006.260.07:55:02.95/vblo/06,752.99,yes,locked 2006.260.07:55:02.95/vblo/07,734.99,yes,locked 2006.260.07:55:02.95/vblo/08,744.99,yes,locked 2006.260.07:55:03.10/vabw/8 2006.260.07:55:03.25/vbbw/8 2006.260.07:55:03.34/xfe/off,on,15.0 2006.260.07:55:03.71/ifatt/23,28,28,28 2006.260.07:55:04.07/fmout-gps/S +4.49E-07 2006.260.07:55:04.12:!2006.260.07:56:00 2006.260.07:56:00.01:data_valid=off 2006.260.07:56:00.02:postob 2006.260.07:56:00.09/cable/+6.4563E-03 2006.260.07:56:00.10/wx/22.91,1010.4,88 2006.260.07:56:01.07/fmout-gps/S +4.48E-07 2006.260.07:56:01.08:scan_name=260-0758,k06260,60 2006.260.07:56:01.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.260.07:56:02.14#flagr#flagr/antenna,new-source 2006.260.07:56:02.15:checkk5 2006.260.07:56:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:56:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:56:03.38/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:56:03.79/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:56:04.18/chk_obsdata//k5ts1/T2600755??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:56:04.57/chk_obsdata//k5ts2/T2600755??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:56:05.21/chk_obsdata//k5ts3/T2600755??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:56:05.66/chk_obsdata//k5ts4/T2600755??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:56:06.78/k5log//k5ts1_log_newline 2006.260.07:56:07.56/k5log//k5ts2_log_newline 2006.260.07:56:08.33/k5log//k5ts3_log_newline 2006.260.07:56:09.16/k5log//k5ts4_log_newline 2006.260.07:56:09.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:56:09.22:4f8m12a=2 2006.260.07:56:09.22$4f8m12a/echo=on 2006.260.07:56:09.22$4f8m12a/pcalon 2006.260.07:56:09.22$pcalon/"no phase cal control is implemented here 2006.260.07:56:09.22$4f8m12a/"tpicd=stop 2006.260.07:56:09.22$4f8m12a/vc4f8 2006.260.07:56:09.22$vc4f8/valo=1,532.99 2006.260.07:56:09.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.07:56:09.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.07:56:09.22#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:09.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:09.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:09.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:09.22#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:56:09.22#ibcon#first serial, iclass 37, count 0 2006.260.07:56:09.22#ibcon#enter sib2, iclass 37, count 0 2006.260.07:56:09.22#ibcon#flushed, iclass 37, count 0 2006.260.07:56:09.22#ibcon#about to write, iclass 37, count 0 2006.260.07:56:09.22#ibcon#wrote, iclass 37, count 0 2006.260.07:56:09.22#ibcon#about to read 3, iclass 37, count 0 2006.260.07:56:09.24#ibcon#read 3, iclass 37, count 0 2006.260.07:56:09.24#ibcon#about to read 4, iclass 37, count 0 2006.260.07:56:09.24#ibcon#read 4, iclass 37, count 0 2006.260.07:56:09.24#ibcon#about to read 5, iclass 37, count 0 2006.260.07:56:09.24#ibcon#read 5, iclass 37, count 0 2006.260.07:56:09.24#ibcon#about to read 6, iclass 37, count 0 2006.260.07:56:09.24#ibcon#read 6, iclass 37, count 0 2006.260.07:56:09.24#ibcon#end of sib2, iclass 37, count 0 2006.260.07:56:09.24#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:56:09.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:56:09.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:56:09.24#ibcon#*before write, iclass 37, count 0 2006.260.07:56:09.24#ibcon#enter sib2, iclass 37, count 0 2006.260.07:56:09.24#ibcon#flushed, iclass 37, count 0 2006.260.07:56:09.24#ibcon#about to write, iclass 37, count 0 2006.260.07:56:09.24#ibcon#wrote, iclass 37, count 0 2006.260.07:56:09.24#ibcon#about to read 3, iclass 37, count 0 2006.260.07:56:09.29#ibcon#read 3, iclass 37, count 0 2006.260.07:56:09.29#ibcon#about to read 4, iclass 37, count 0 2006.260.07:56:09.29#ibcon#read 4, iclass 37, count 0 2006.260.07:56:09.29#ibcon#about to read 5, iclass 37, count 0 2006.260.07:56:09.29#ibcon#read 5, iclass 37, count 0 2006.260.07:56:09.29#ibcon#about to read 6, iclass 37, count 0 2006.260.07:56:09.29#ibcon#read 6, iclass 37, count 0 2006.260.07:56:09.29#ibcon#end of sib2, iclass 37, count 0 2006.260.07:56:09.29#ibcon#*after write, iclass 37, count 0 2006.260.07:56:09.29#ibcon#*before return 0, iclass 37, count 0 2006.260.07:56:09.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:09.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:09.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:56:09.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:56:09.29$vc4f8/va=1,8 2006.260.07:56:09.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.07:56:09.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.07:56:09.29#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:09.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:09.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:09.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:09.29#ibcon#enter wrdev, iclass 39, count 2 2006.260.07:56:09.29#ibcon#first serial, iclass 39, count 2 2006.260.07:56:09.29#ibcon#enter sib2, iclass 39, count 2 2006.260.07:56:09.29#ibcon#flushed, iclass 39, count 2 2006.260.07:56:09.29#ibcon#about to write, iclass 39, count 2 2006.260.07:56:09.29#ibcon#wrote, iclass 39, count 2 2006.260.07:56:09.29#ibcon#about to read 3, iclass 39, count 2 2006.260.07:56:09.31#ibcon#read 3, iclass 39, count 2 2006.260.07:56:09.31#ibcon#about to read 4, iclass 39, count 2 2006.260.07:56:09.31#ibcon#read 4, iclass 39, count 2 2006.260.07:56:09.31#ibcon#about to read 5, iclass 39, count 2 2006.260.07:56:09.31#ibcon#read 5, iclass 39, count 2 2006.260.07:56:09.31#ibcon#about to read 6, iclass 39, count 2 2006.260.07:56:09.31#ibcon#read 6, iclass 39, count 2 2006.260.07:56:09.31#ibcon#end of sib2, iclass 39, count 2 2006.260.07:56:09.31#ibcon#*mode == 0, iclass 39, count 2 2006.260.07:56:09.31#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.07:56:09.31#ibcon#[25=AT01-08\r\n] 2006.260.07:56:09.31#ibcon#*before write, iclass 39, count 2 2006.260.07:56:09.31#ibcon#enter sib2, iclass 39, count 2 2006.260.07:56:09.31#ibcon#flushed, iclass 39, count 2 2006.260.07:56:09.31#ibcon#about to write, iclass 39, count 2 2006.260.07:56:09.31#ibcon#wrote, iclass 39, count 2 2006.260.07:56:09.31#ibcon#about to read 3, iclass 39, count 2 2006.260.07:56:09.34#ibcon#read 3, iclass 39, count 2 2006.260.07:56:09.34#ibcon#about to read 4, iclass 39, count 2 2006.260.07:56:09.34#ibcon#read 4, iclass 39, count 2 2006.260.07:56:09.34#ibcon#about to read 5, iclass 39, count 2 2006.260.07:56:09.34#ibcon#read 5, iclass 39, count 2 2006.260.07:56:09.34#ibcon#about to read 6, iclass 39, count 2 2006.260.07:56:09.34#ibcon#read 6, iclass 39, count 2 2006.260.07:56:09.34#ibcon#end of sib2, iclass 39, count 2 2006.260.07:56:09.34#ibcon#*after write, iclass 39, count 2 2006.260.07:56:09.34#ibcon#*before return 0, iclass 39, count 2 2006.260.07:56:09.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:09.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:09.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.07:56:09.34#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:09.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:09.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:09.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:09.46#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:56:09.46#ibcon#first serial, iclass 39, count 0 2006.260.07:56:09.46#ibcon#enter sib2, iclass 39, count 0 2006.260.07:56:09.46#ibcon#flushed, iclass 39, count 0 2006.260.07:56:09.46#ibcon#about to write, iclass 39, count 0 2006.260.07:56:09.46#ibcon#wrote, iclass 39, count 0 2006.260.07:56:09.46#ibcon#about to read 3, iclass 39, count 0 2006.260.07:56:09.48#ibcon#read 3, iclass 39, count 0 2006.260.07:56:09.48#ibcon#about to read 4, iclass 39, count 0 2006.260.07:56:09.48#ibcon#read 4, iclass 39, count 0 2006.260.07:56:09.48#ibcon#about to read 5, iclass 39, count 0 2006.260.07:56:09.48#ibcon#read 5, iclass 39, count 0 2006.260.07:56:09.48#ibcon#about to read 6, iclass 39, count 0 2006.260.07:56:09.48#ibcon#read 6, iclass 39, count 0 2006.260.07:56:09.48#ibcon#end of sib2, iclass 39, count 0 2006.260.07:56:09.48#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:56:09.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:56:09.48#ibcon#[25=USB\r\n] 2006.260.07:56:09.48#ibcon#*before write, iclass 39, count 0 2006.260.07:56:09.48#ibcon#enter sib2, iclass 39, count 0 2006.260.07:56:09.48#ibcon#flushed, iclass 39, count 0 2006.260.07:56:09.48#ibcon#about to write, iclass 39, count 0 2006.260.07:56:09.48#ibcon#wrote, iclass 39, count 0 2006.260.07:56:09.48#ibcon#about to read 3, iclass 39, count 0 2006.260.07:56:09.51#ibcon#read 3, iclass 39, count 0 2006.260.07:56:09.51#ibcon#about to read 4, iclass 39, count 0 2006.260.07:56:09.51#ibcon#read 4, iclass 39, count 0 2006.260.07:56:09.51#ibcon#about to read 5, iclass 39, count 0 2006.260.07:56:09.51#ibcon#read 5, iclass 39, count 0 2006.260.07:56:09.51#ibcon#about to read 6, iclass 39, count 0 2006.260.07:56:09.51#ibcon#read 6, iclass 39, count 0 2006.260.07:56:09.51#ibcon#end of sib2, iclass 39, count 0 2006.260.07:56:09.51#ibcon#*after write, iclass 39, count 0 2006.260.07:56:09.51#ibcon#*before return 0, iclass 39, count 0 2006.260.07:56:09.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:09.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:09.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:56:09.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:56:09.51$vc4f8/valo=2,572.99 2006.260.07:56:09.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:56:09.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:56:09.51#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:09.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:09.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:09.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:09.51#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:56:09.51#ibcon#first serial, iclass 3, count 0 2006.260.07:56:09.51#ibcon#enter sib2, iclass 3, count 0 2006.260.07:56:09.51#ibcon#flushed, iclass 3, count 0 2006.260.07:56:09.51#ibcon#about to write, iclass 3, count 0 2006.260.07:56:09.51#ibcon#wrote, iclass 3, count 0 2006.260.07:56:09.51#ibcon#about to read 3, iclass 3, count 0 2006.260.07:56:09.53#ibcon#read 3, iclass 3, count 0 2006.260.07:56:09.53#ibcon#about to read 4, iclass 3, count 0 2006.260.07:56:09.53#ibcon#read 4, iclass 3, count 0 2006.260.07:56:09.53#ibcon#about to read 5, iclass 3, count 0 2006.260.07:56:09.53#ibcon#read 5, iclass 3, count 0 2006.260.07:56:09.53#ibcon#about to read 6, iclass 3, count 0 2006.260.07:56:09.53#ibcon#read 6, iclass 3, count 0 2006.260.07:56:09.53#ibcon#end of sib2, iclass 3, count 0 2006.260.07:56:09.53#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:56:09.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:56:09.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:56:09.53#ibcon#*before write, iclass 3, count 0 2006.260.07:56:09.53#ibcon#enter sib2, iclass 3, count 0 2006.260.07:56:09.53#ibcon#flushed, iclass 3, count 0 2006.260.07:56:09.53#ibcon#about to write, iclass 3, count 0 2006.260.07:56:09.53#ibcon#wrote, iclass 3, count 0 2006.260.07:56:09.53#ibcon#about to read 3, iclass 3, count 0 2006.260.07:56:09.57#ibcon#read 3, iclass 3, count 0 2006.260.07:56:09.57#ibcon#about to read 4, iclass 3, count 0 2006.260.07:56:09.57#ibcon#read 4, iclass 3, count 0 2006.260.07:56:09.57#ibcon#about to read 5, iclass 3, count 0 2006.260.07:56:09.57#ibcon#read 5, iclass 3, count 0 2006.260.07:56:09.57#ibcon#about to read 6, iclass 3, count 0 2006.260.07:56:09.57#ibcon#read 6, iclass 3, count 0 2006.260.07:56:09.57#ibcon#end of sib2, iclass 3, count 0 2006.260.07:56:09.57#ibcon#*after write, iclass 3, count 0 2006.260.07:56:09.57#ibcon#*before return 0, iclass 3, count 0 2006.260.07:56:09.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:09.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:09.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:56:09.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:56:09.57$vc4f8/va=2,7 2006.260.07:56:09.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.07:56:09.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.07:56:09.57#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:09.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:09.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:09.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:09.63#ibcon#enter wrdev, iclass 5, count 2 2006.260.07:56:09.63#ibcon#first serial, iclass 5, count 2 2006.260.07:56:09.63#ibcon#enter sib2, iclass 5, count 2 2006.260.07:56:09.63#ibcon#flushed, iclass 5, count 2 2006.260.07:56:09.63#ibcon#about to write, iclass 5, count 2 2006.260.07:56:09.63#ibcon#wrote, iclass 5, count 2 2006.260.07:56:09.63#ibcon#about to read 3, iclass 5, count 2 2006.260.07:56:09.66#ibcon#read 3, iclass 5, count 2 2006.260.07:56:09.66#ibcon#about to read 4, iclass 5, count 2 2006.260.07:56:09.66#ibcon#read 4, iclass 5, count 2 2006.260.07:56:09.66#ibcon#about to read 5, iclass 5, count 2 2006.260.07:56:09.66#ibcon#read 5, iclass 5, count 2 2006.260.07:56:09.66#ibcon#about to read 6, iclass 5, count 2 2006.260.07:56:09.66#ibcon#read 6, iclass 5, count 2 2006.260.07:56:09.66#ibcon#end of sib2, iclass 5, count 2 2006.260.07:56:09.66#ibcon#*mode == 0, iclass 5, count 2 2006.260.07:56:09.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.07:56:09.66#ibcon#[25=AT02-07\r\n] 2006.260.07:56:09.66#ibcon#*before write, iclass 5, count 2 2006.260.07:56:09.66#ibcon#enter sib2, iclass 5, count 2 2006.260.07:56:09.66#ibcon#flushed, iclass 5, count 2 2006.260.07:56:09.66#ibcon#about to write, iclass 5, count 2 2006.260.07:56:09.66#ibcon#wrote, iclass 5, count 2 2006.260.07:56:09.66#ibcon#about to read 3, iclass 5, count 2 2006.260.07:56:09.69#ibcon#read 3, iclass 5, count 2 2006.260.07:56:09.69#ibcon#about to read 4, iclass 5, count 2 2006.260.07:56:09.69#ibcon#read 4, iclass 5, count 2 2006.260.07:56:09.69#ibcon#about to read 5, iclass 5, count 2 2006.260.07:56:09.69#ibcon#read 5, iclass 5, count 2 2006.260.07:56:09.69#ibcon#about to read 6, iclass 5, count 2 2006.260.07:56:09.69#ibcon#read 6, iclass 5, count 2 2006.260.07:56:09.69#ibcon#end of sib2, iclass 5, count 2 2006.260.07:56:09.69#ibcon#*after write, iclass 5, count 2 2006.260.07:56:09.69#ibcon#*before return 0, iclass 5, count 2 2006.260.07:56:09.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:09.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:09.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.07:56:09.69#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:09.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:09.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:09.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:09.81#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:56:09.81#ibcon#first serial, iclass 5, count 0 2006.260.07:56:09.81#ibcon#enter sib2, iclass 5, count 0 2006.260.07:56:09.81#ibcon#flushed, iclass 5, count 0 2006.260.07:56:09.81#ibcon#about to write, iclass 5, count 0 2006.260.07:56:09.81#ibcon#wrote, iclass 5, count 0 2006.260.07:56:09.81#ibcon#about to read 3, iclass 5, count 0 2006.260.07:56:09.83#ibcon#read 3, iclass 5, count 0 2006.260.07:56:09.83#ibcon#about to read 4, iclass 5, count 0 2006.260.07:56:09.83#ibcon#read 4, iclass 5, count 0 2006.260.07:56:09.83#ibcon#about to read 5, iclass 5, count 0 2006.260.07:56:09.83#ibcon#read 5, iclass 5, count 0 2006.260.07:56:09.83#ibcon#about to read 6, iclass 5, count 0 2006.260.07:56:09.83#ibcon#read 6, iclass 5, count 0 2006.260.07:56:09.83#ibcon#end of sib2, iclass 5, count 0 2006.260.07:56:09.83#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:56:09.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:56:09.83#ibcon#[25=USB\r\n] 2006.260.07:56:09.83#ibcon#*before write, iclass 5, count 0 2006.260.07:56:09.83#ibcon#enter sib2, iclass 5, count 0 2006.260.07:56:09.83#ibcon#flushed, iclass 5, count 0 2006.260.07:56:09.83#ibcon#about to write, iclass 5, count 0 2006.260.07:56:09.83#ibcon#wrote, iclass 5, count 0 2006.260.07:56:09.83#ibcon#about to read 3, iclass 5, count 0 2006.260.07:56:09.86#ibcon#read 3, iclass 5, count 0 2006.260.07:56:09.86#ibcon#about to read 4, iclass 5, count 0 2006.260.07:56:09.86#ibcon#read 4, iclass 5, count 0 2006.260.07:56:09.86#ibcon#about to read 5, iclass 5, count 0 2006.260.07:56:09.86#ibcon#read 5, iclass 5, count 0 2006.260.07:56:09.86#ibcon#about to read 6, iclass 5, count 0 2006.260.07:56:09.86#ibcon#read 6, iclass 5, count 0 2006.260.07:56:09.86#ibcon#end of sib2, iclass 5, count 0 2006.260.07:56:09.86#ibcon#*after write, iclass 5, count 0 2006.260.07:56:09.86#ibcon#*before return 0, iclass 5, count 0 2006.260.07:56:09.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:09.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:09.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:56:09.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:56:09.86$vc4f8/valo=3,672.99 2006.260.07:56:09.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:56:09.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:56:09.86#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:09.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:09.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:09.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:09.86#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:56:09.86#ibcon#first serial, iclass 7, count 0 2006.260.07:56:09.86#ibcon#enter sib2, iclass 7, count 0 2006.260.07:56:09.86#ibcon#flushed, iclass 7, count 0 2006.260.07:56:09.86#ibcon#about to write, iclass 7, count 0 2006.260.07:56:09.86#ibcon#wrote, iclass 7, count 0 2006.260.07:56:09.86#ibcon#about to read 3, iclass 7, count 0 2006.260.07:56:09.88#ibcon#read 3, iclass 7, count 0 2006.260.07:56:09.88#ibcon#about to read 4, iclass 7, count 0 2006.260.07:56:09.88#ibcon#read 4, iclass 7, count 0 2006.260.07:56:09.88#ibcon#about to read 5, iclass 7, count 0 2006.260.07:56:09.88#ibcon#read 5, iclass 7, count 0 2006.260.07:56:09.88#ibcon#about to read 6, iclass 7, count 0 2006.260.07:56:09.88#ibcon#read 6, iclass 7, count 0 2006.260.07:56:09.88#ibcon#end of sib2, iclass 7, count 0 2006.260.07:56:09.88#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:56:09.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:56:09.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:56:09.88#ibcon#*before write, iclass 7, count 0 2006.260.07:56:09.88#ibcon#enter sib2, iclass 7, count 0 2006.260.07:56:09.88#ibcon#flushed, iclass 7, count 0 2006.260.07:56:09.88#ibcon#about to write, iclass 7, count 0 2006.260.07:56:09.88#ibcon#wrote, iclass 7, count 0 2006.260.07:56:09.88#ibcon#about to read 3, iclass 7, count 0 2006.260.07:56:09.92#ibcon#read 3, iclass 7, count 0 2006.260.07:56:09.92#ibcon#about to read 4, iclass 7, count 0 2006.260.07:56:09.92#ibcon#read 4, iclass 7, count 0 2006.260.07:56:09.92#ibcon#about to read 5, iclass 7, count 0 2006.260.07:56:09.92#ibcon#read 5, iclass 7, count 0 2006.260.07:56:09.92#ibcon#about to read 6, iclass 7, count 0 2006.260.07:56:09.92#ibcon#read 6, iclass 7, count 0 2006.260.07:56:09.92#ibcon#end of sib2, iclass 7, count 0 2006.260.07:56:09.92#ibcon#*after write, iclass 7, count 0 2006.260.07:56:09.92#ibcon#*before return 0, iclass 7, count 0 2006.260.07:56:09.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:09.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:09.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:56:09.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:56:09.92$vc4f8/va=3,8 2006.260.07:56:09.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:56:09.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:56:09.92#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:09.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:09.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:09.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:09.98#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:56:09.98#ibcon#first serial, iclass 11, count 2 2006.260.07:56:09.98#ibcon#enter sib2, iclass 11, count 2 2006.260.07:56:09.98#ibcon#flushed, iclass 11, count 2 2006.260.07:56:09.98#ibcon#about to write, iclass 11, count 2 2006.260.07:56:09.98#ibcon#wrote, iclass 11, count 2 2006.260.07:56:09.98#ibcon#about to read 3, iclass 11, count 2 2006.260.07:56:10.01#ibcon#read 3, iclass 11, count 2 2006.260.07:56:10.01#ibcon#about to read 4, iclass 11, count 2 2006.260.07:56:10.01#ibcon#read 4, iclass 11, count 2 2006.260.07:56:10.01#ibcon#about to read 5, iclass 11, count 2 2006.260.07:56:10.01#ibcon#read 5, iclass 11, count 2 2006.260.07:56:10.01#ibcon#about to read 6, iclass 11, count 2 2006.260.07:56:10.01#ibcon#read 6, iclass 11, count 2 2006.260.07:56:10.01#ibcon#end of sib2, iclass 11, count 2 2006.260.07:56:10.01#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:56:10.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:56:10.01#ibcon#[25=AT03-08\r\n] 2006.260.07:56:10.01#ibcon#*before write, iclass 11, count 2 2006.260.07:56:10.01#ibcon#enter sib2, iclass 11, count 2 2006.260.07:56:10.01#ibcon#flushed, iclass 11, count 2 2006.260.07:56:10.01#ibcon#about to write, iclass 11, count 2 2006.260.07:56:10.01#ibcon#wrote, iclass 11, count 2 2006.260.07:56:10.01#ibcon#about to read 3, iclass 11, count 2 2006.260.07:56:10.04#ibcon#read 3, iclass 11, count 2 2006.260.07:56:10.04#ibcon#about to read 4, iclass 11, count 2 2006.260.07:56:10.04#ibcon#read 4, iclass 11, count 2 2006.260.07:56:10.04#ibcon#about to read 5, iclass 11, count 2 2006.260.07:56:10.04#ibcon#read 5, iclass 11, count 2 2006.260.07:56:10.04#ibcon#about to read 6, iclass 11, count 2 2006.260.07:56:10.04#ibcon#read 6, iclass 11, count 2 2006.260.07:56:10.04#ibcon#end of sib2, iclass 11, count 2 2006.260.07:56:10.04#ibcon#*after write, iclass 11, count 2 2006.260.07:56:10.04#ibcon#*before return 0, iclass 11, count 2 2006.260.07:56:10.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:10.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:10.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:56:10.04#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:10.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:10.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:10.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:10.16#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:56:10.16#ibcon#first serial, iclass 11, count 0 2006.260.07:56:10.16#ibcon#enter sib2, iclass 11, count 0 2006.260.07:56:10.16#ibcon#flushed, iclass 11, count 0 2006.260.07:56:10.16#ibcon#about to write, iclass 11, count 0 2006.260.07:56:10.16#ibcon#wrote, iclass 11, count 0 2006.260.07:56:10.16#ibcon#about to read 3, iclass 11, count 0 2006.260.07:56:10.18#ibcon#read 3, iclass 11, count 0 2006.260.07:56:10.18#ibcon#about to read 4, iclass 11, count 0 2006.260.07:56:10.18#ibcon#read 4, iclass 11, count 0 2006.260.07:56:10.18#ibcon#about to read 5, iclass 11, count 0 2006.260.07:56:10.18#ibcon#read 5, iclass 11, count 0 2006.260.07:56:10.18#ibcon#about to read 6, iclass 11, count 0 2006.260.07:56:10.18#ibcon#read 6, iclass 11, count 0 2006.260.07:56:10.18#ibcon#end of sib2, iclass 11, count 0 2006.260.07:56:10.18#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:56:10.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:56:10.18#ibcon#[25=USB\r\n] 2006.260.07:56:10.18#ibcon#*before write, iclass 11, count 0 2006.260.07:56:10.18#ibcon#enter sib2, iclass 11, count 0 2006.260.07:56:10.18#ibcon#flushed, iclass 11, count 0 2006.260.07:56:10.18#ibcon#about to write, iclass 11, count 0 2006.260.07:56:10.18#ibcon#wrote, iclass 11, count 0 2006.260.07:56:10.18#ibcon#about to read 3, iclass 11, count 0 2006.260.07:56:10.21#ibcon#read 3, iclass 11, count 0 2006.260.07:56:10.21#ibcon#about to read 4, iclass 11, count 0 2006.260.07:56:10.21#ibcon#read 4, iclass 11, count 0 2006.260.07:56:10.21#ibcon#about to read 5, iclass 11, count 0 2006.260.07:56:10.21#ibcon#read 5, iclass 11, count 0 2006.260.07:56:10.21#ibcon#about to read 6, iclass 11, count 0 2006.260.07:56:10.21#ibcon#read 6, iclass 11, count 0 2006.260.07:56:10.21#ibcon#end of sib2, iclass 11, count 0 2006.260.07:56:10.21#ibcon#*after write, iclass 11, count 0 2006.260.07:56:10.21#ibcon#*before return 0, iclass 11, count 0 2006.260.07:56:10.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:10.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:10.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:56:10.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:56:10.21$vc4f8/valo=4,832.99 2006.260.07:56:10.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:56:10.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:56:10.21#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:10.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:10.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:10.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:10.21#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:56:10.21#ibcon#first serial, iclass 13, count 0 2006.260.07:56:10.21#ibcon#enter sib2, iclass 13, count 0 2006.260.07:56:10.21#ibcon#flushed, iclass 13, count 0 2006.260.07:56:10.21#ibcon#about to write, iclass 13, count 0 2006.260.07:56:10.21#ibcon#wrote, iclass 13, count 0 2006.260.07:56:10.21#ibcon#about to read 3, iclass 13, count 0 2006.260.07:56:10.23#ibcon#read 3, iclass 13, count 0 2006.260.07:56:10.23#ibcon#about to read 4, iclass 13, count 0 2006.260.07:56:10.23#ibcon#read 4, iclass 13, count 0 2006.260.07:56:10.23#ibcon#about to read 5, iclass 13, count 0 2006.260.07:56:10.23#ibcon#read 5, iclass 13, count 0 2006.260.07:56:10.23#ibcon#about to read 6, iclass 13, count 0 2006.260.07:56:10.23#ibcon#read 6, iclass 13, count 0 2006.260.07:56:10.23#ibcon#end of sib2, iclass 13, count 0 2006.260.07:56:10.23#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:56:10.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:56:10.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:56:10.23#ibcon#*before write, iclass 13, count 0 2006.260.07:56:10.23#ibcon#enter sib2, iclass 13, count 0 2006.260.07:56:10.23#ibcon#flushed, iclass 13, count 0 2006.260.07:56:10.23#ibcon#about to write, iclass 13, count 0 2006.260.07:56:10.23#ibcon#wrote, iclass 13, count 0 2006.260.07:56:10.23#ibcon#about to read 3, iclass 13, count 0 2006.260.07:56:10.27#ibcon#read 3, iclass 13, count 0 2006.260.07:56:10.27#ibcon#about to read 4, iclass 13, count 0 2006.260.07:56:10.27#ibcon#read 4, iclass 13, count 0 2006.260.07:56:10.27#ibcon#about to read 5, iclass 13, count 0 2006.260.07:56:10.27#ibcon#read 5, iclass 13, count 0 2006.260.07:56:10.27#ibcon#about to read 6, iclass 13, count 0 2006.260.07:56:10.27#ibcon#read 6, iclass 13, count 0 2006.260.07:56:10.27#ibcon#end of sib2, iclass 13, count 0 2006.260.07:56:10.27#ibcon#*after write, iclass 13, count 0 2006.260.07:56:10.27#ibcon#*before return 0, iclass 13, count 0 2006.260.07:56:10.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:10.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:10.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:56:10.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:56:10.27$vc4f8/va=4,7 2006.260.07:56:10.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:56:10.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:56:10.27#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:10.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:10.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:10.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:10.33#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:56:10.33#ibcon#first serial, iclass 15, count 2 2006.260.07:56:10.33#ibcon#enter sib2, iclass 15, count 2 2006.260.07:56:10.33#ibcon#flushed, iclass 15, count 2 2006.260.07:56:10.33#ibcon#about to write, iclass 15, count 2 2006.260.07:56:10.33#ibcon#wrote, iclass 15, count 2 2006.260.07:56:10.33#ibcon#about to read 3, iclass 15, count 2 2006.260.07:56:10.35#ibcon#read 3, iclass 15, count 2 2006.260.07:56:10.35#ibcon#about to read 4, iclass 15, count 2 2006.260.07:56:10.35#ibcon#read 4, iclass 15, count 2 2006.260.07:56:10.35#ibcon#about to read 5, iclass 15, count 2 2006.260.07:56:10.35#ibcon#read 5, iclass 15, count 2 2006.260.07:56:10.35#ibcon#about to read 6, iclass 15, count 2 2006.260.07:56:10.35#ibcon#read 6, iclass 15, count 2 2006.260.07:56:10.35#ibcon#end of sib2, iclass 15, count 2 2006.260.07:56:10.35#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:56:10.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:56:10.35#ibcon#[25=AT04-07\r\n] 2006.260.07:56:10.35#ibcon#*before write, iclass 15, count 2 2006.260.07:56:10.35#ibcon#enter sib2, iclass 15, count 2 2006.260.07:56:10.35#ibcon#flushed, iclass 15, count 2 2006.260.07:56:10.35#ibcon#about to write, iclass 15, count 2 2006.260.07:56:10.35#ibcon#wrote, iclass 15, count 2 2006.260.07:56:10.35#ibcon#about to read 3, iclass 15, count 2 2006.260.07:56:10.38#ibcon#read 3, iclass 15, count 2 2006.260.07:56:10.38#ibcon#about to read 4, iclass 15, count 2 2006.260.07:56:10.38#ibcon#read 4, iclass 15, count 2 2006.260.07:56:10.38#ibcon#about to read 5, iclass 15, count 2 2006.260.07:56:10.38#ibcon#read 5, iclass 15, count 2 2006.260.07:56:10.38#ibcon#about to read 6, iclass 15, count 2 2006.260.07:56:10.38#ibcon#read 6, iclass 15, count 2 2006.260.07:56:10.38#ibcon#end of sib2, iclass 15, count 2 2006.260.07:56:10.38#ibcon#*after write, iclass 15, count 2 2006.260.07:56:10.38#ibcon#*before return 0, iclass 15, count 2 2006.260.07:56:10.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:10.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:10.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:56:10.38#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:10.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:10.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:10.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:10.50#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:56:10.50#ibcon#first serial, iclass 15, count 0 2006.260.07:56:10.50#ibcon#enter sib2, iclass 15, count 0 2006.260.07:56:10.50#ibcon#flushed, iclass 15, count 0 2006.260.07:56:10.50#ibcon#about to write, iclass 15, count 0 2006.260.07:56:10.50#ibcon#wrote, iclass 15, count 0 2006.260.07:56:10.50#ibcon#about to read 3, iclass 15, count 0 2006.260.07:56:10.52#ibcon#read 3, iclass 15, count 0 2006.260.07:56:10.52#ibcon#about to read 4, iclass 15, count 0 2006.260.07:56:10.52#ibcon#read 4, iclass 15, count 0 2006.260.07:56:10.52#ibcon#about to read 5, iclass 15, count 0 2006.260.07:56:10.52#ibcon#read 5, iclass 15, count 0 2006.260.07:56:10.52#ibcon#about to read 6, iclass 15, count 0 2006.260.07:56:10.52#ibcon#read 6, iclass 15, count 0 2006.260.07:56:10.52#ibcon#end of sib2, iclass 15, count 0 2006.260.07:56:10.52#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:56:10.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:56:10.52#ibcon#[25=USB\r\n] 2006.260.07:56:10.52#ibcon#*before write, iclass 15, count 0 2006.260.07:56:10.52#ibcon#enter sib2, iclass 15, count 0 2006.260.07:56:10.52#ibcon#flushed, iclass 15, count 0 2006.260.07:56:10.52#ibcon#about to write, iclass 15, count 0 2006.260.07:56:10.52#ibcon#wrote, iclass 15, count 0 2006.260.07:56:10.52#ibcon#about to read 3, iclass 15, count 0 2006.260.07:56:10.55#ibcon#read 3, iclass 15, count 0 2006.260.07:56:10.55#ibcon#about to read 4, iclass 15, count 0 2006.260.07:56:10.55#ibcon#read 4, iclass 15, count 0 2006.260.07:56:10.55#ibcon#about to read 5, iclass 15, count 0 2006.260.07:56:10.55#ibcon#read 5, iclass 15, count 0 2006.260.07:56:10.55#ibcon#about to read 6, iclass 15, count 0 2006.260.07:56:10.55#ibcon#read 6, iclass 15, count 0 2006.260.07:56:10.55#ibcon#end of sib2, iclass 15, count 0 2006.260.07:56:10.55#ibcon#*after write, iclass 15, count 0 2006.260.07:56:10.55#ibcon#*before return 0, iclass 15, count 0 2006.260.07:56:10.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:10.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:10.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:56:10.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:56:10.55$vc4f8/valo=5,652.99 2006.260.07:56:10.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.07:56:10.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.07:56:10.55#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:10.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:10.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:10.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:10.55#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:56:10.55#ibcon#first serial, iclass 17, count 0 2006.260.07:56:10.55#ibcon#enter sib2, iclass 17, count 0 2006.260.07:56:10.55#ibcon#flushed, iclass 17, count 0 2006.260.07:56:10.55#ibcon#about to write, iclass 17, count 0 2006.260.07:56:10.55#ibcon#wrote, iclass 17, count 0 2006.260.07:56:10.55#ibcon#about to read 3, iclass 17, count 0 2006.260.07:56:10.57#ibcon#read 3, iclass 17, count 0 2006.260.07:56:10.57#ibcon#about to read 4, iclass 17, count 0 2006.260.07:56:10.57#ibcon#read 4, iclass 17, count 0 2006.260.07:56:10.57#ibcon#about to read 5, iclass 17, count 0 2006.260.07:56:10.57#ibcon#read 5, iclass 17, count 0 2006.260.07:56:10.57#ibcon#about to read 6, iclass 17, count 0 2006.260.07:56:10.57#ibcon#read 6, iclass 17, count 0 2006.260.07:56:10.57#ibcon#end of sib2, iclass 17, count 0 2006.260.07:56:10.57#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:56:10.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:56:10.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:56:10.57#ibcon#*before write, iclass 17, count 0 2006.260.07:56:10.57#ibcon#enter sib2, iclass 17, count 0 2006.260.07:56:10.57#ibcon#flushed, iclass 17, count 0 2006.260.07:56:10.57#ibcon#about to write, iclass 17, count 0 2006.260.07:56:10.57#ibcon#wrote, iclass 17, count 0 2006.260.07:56:10.57#ibcon#about to read 3, iclass 17, count 0 2006.260.07:56:10.61#ibcon#read 3, iclass 17, count 0 2006.260.07:56:10.61#ibcon#about to read 4, iclass 17, count 0 2006.260.07:56:10.61#ibcon#read 4, iclass 17, count 0 2006.260.07:56:10.61#ibcon#about to read 5, iclass 17, count 0 2006.260.07:56:10.61#ibcon#read 5, iclass 17, count 0 2006.260.07:56:10.61#ibcon#about to read 6, iclass 17, count 0 2006.260.07:56:10.61#ibcon#read 6, iclass 17, count 0 2006.260.07:56:10.61#ibcon#end of sib2, iclass 17, count 0 2006.260.07:56:10.61#ibcon#*after write, iclass 17, count 0 2006.260.07:56:10.61#ibcon#*before return 0, iclass 17, count 0 2006.260.07:56:10.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:10.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:10.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:56:10.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:56:10.61$vc4f8/va=5,7 2006.260.07:56:10.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.07:56:10.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.07:56:10.61#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:10.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:10.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:10.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:10.67#ibcon#enter wrdev, iclass 19, count 2 2006.260.07:56:10.67#ibcon#first serial, iclass 19, count 2 2006.260.07:56:10.67#ibcon#enter sib2, iclass 19, count 2 2006.260.07:56:10.67#ibcon#flushed, iclass 19, count 2 2006.260.07:56:10.67#ibcon#about to write, iclass 19, count 2 2006.260.07:56:10.67#ibcon#wrote, iclass 19, count 2 2006.260.07:56:10.67#ibcon#about to read 3, iclass 19, count 2 2006.260.07:56:10.69#ibcon#read 3, iclass 19, count 2 2006.260.07:56:10.69#ibcon#about to read 4, iclass 19, count 2 2006.260.07:56:10.69#ibcon#read 4, iclass 19, count 2 2006.260.07:56:10.69#ibcon#about to read 5, iclass 19, count 2 2006.260.07:56:10.69#ibcon#read 5, iclass 19, count 2 2006.260.07:56:10.69#ibcon#about to read 6, iclass 19, count 2 2006.260.07:56:10.69#ibcon#read 6, iclass 19, count 2 2006.260.07:56:10.69#ibcon#end of sib2, iclass 19, count 2 2006.260.07:56:10.69#ibcon#*mode == 0, iclass 19, count 2 2006.260.07:56:10.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.07:56:10.69#ibcon#[25=AT05-07\r\n] 2006.260.07:56:10.69#ibcon#*before write, iclass 19, count 2 2006.260.07:56:10.69#ibcon#enter sib2, iclass 19, count 2 2006.260.07:56:10.69#ibcon#flushed, iclass 19, count 2 2006.260.07:56:10.69#ibcon#about to write, iclass 19, count 2 2006.260.07:56:10.69#ibcon#wrote, iclass 19, count 2 2006.260.07:56:10.69#ibcon#about to read 3, iclass 19, count 2 2006.260.07:56:10.72#ibcon#read 3, iclass 19, count 2 2006.260.07:56:10.72#ibcon#about to read 4, iclass 19, count 2 2006.260.07:56:10.72#ibcon#read 4, iclass 19, count 2 2006.260.07:56:10.72#ibcon#about to read 5, iclass 19, count 2 2006.260.07:56:10.72#ibcon#read 5, iclass 19, count 2 2006.260.07:56:10.72#ibcon#about to read 6, iclass 19, count 2 2006.260.07:56:10.72#ibcon#read 6, iclass 19, count 2 2006.260.07:56:10.72#ibcon#end of sib2, iclass 19, count 2 2006.260.07:56:10.72#ibcon#*after write, iclass 19, count 2 2006.260.07:56:10.72#ibcon#*before return 0, iclass 19, count 2 2006.260.07:56:10.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:10.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:10.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.07:56:10.72#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:10.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:10.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:10.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:10.84#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:56:10.84#ibcon#first serial, iclass 19, count 0 2006.260.07:56:10.84#ibcon#enter sib2, iclass 19, count 0 2006.260.07:56:10.84#ibcon#flushed, iclass 19, count 0 2006.260.07:56:10.84#ibcon#about to write, iclass 19, count 0 2006.260.07:56:10.84#ibcon#wrote, iclass 19, count 0 2006.260.07:56:10.84#ibcon#about to read 3, iclass 19, count 0 2006.260.07:56:10.86#ibcon#read 3, iclass 19, count 0 2006.260.07:56:10.86#ibcon#about to read 4, iclass 19, count 0 2006.260.07:56:10.86#ibcon#read 4, iclass 19, count 0 2006.260.07:56:10.86#ibcon#about to read 5, iclass 19, count 0 2006.260.07:56:10.86#ibcon#read 5, iclass 19, count 0 2006.260.07:56:10.86#ibcon#about to read 6, iclass 19, count 0 2006.260.07:56:10.86#ibcon#read 6, iclass 19, count 0 2006.260.07:56:10.86#ibcon#end of sib2, iclass 19, count 0 2006.260.07:56:10.86#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:56:10.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:56:10.86#ibcon#[25=USB\r\n] 2006.260.07:56:10.86#ibcon#*before write, iclass 19, count 0 2006.260.07:56:10.86#ibcon#enter sib2, iclass 19, count 0 2006.260.07:56:10.86#ibcon#flushed, iclass 19, count 0 2006.260.07:56:10.86#ibcon#about to write, iclass 19, count 0 2006.260.07:56:10.86#ibcon#wrote, iclass 19, count 0 2006.260.07:56:10.86#ibcon#about to read 3, iclass 19, count 0 2006.260.07:56:10.89#ibcon#read 3, iclass 19, count 0 2006.260.07:56:10.89#ibcon#about to read 4, iclass 19, count 0 2006.260.07:56:10.89#ibcon#read 4, iclass 19, count 0 2006.260.07:56:10.89#ibcon#about to read 5, iclass 19, count 0 2006.260.07:56:10.89#ibcon#read 5, iclass 19, count 0 2006.260.07:56:10.89#ibcon#about to read 6, iclass 19, count 0 2006.260.07:56:10.89#ibcon#read 6, iclass 19, count 0 2006.260.07:56:10.89#ibcon#end of sib2, iclass 19, count 0 2006.260.07:56:10.89#ibcon#*after write, iclass 19, count 0 2006.260.07:56:10.89#ibcon#*before return 0, iclass 19, count 0 2006.260.07:56:10.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:10.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:10.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:56:10.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:56:10.89$vc4f8/valo=6,772.99 2006.260.07:56:10.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.07:56:10.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.07:56:10.89#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:10.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:10.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:10.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:10.89#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:56:10.89#ibcon#first serial, iclass 21, count 0 2006.260.07:56:10.89#ibcon#enter sib2, iclass 21, count 0 2006.260.07:56:10.89#ibcon#flushed, iclass 21, count 0 2006.260.07:56:10.89#ibcon#about to write, iclass 21, count 0 2006.260.07:56:10.89#ibcon#wrote, iclass 21, count 0 2006.260.07:56:10.89#ibcon#about to read 3, iclass 21, count 0 2006.260.07:56:10.91#ibcon#read 3, iclass 21, count 0 2006.260.07:56:10.91#ibcon#about to read 4, iclass 21, count 0 2006.260.07:56:10.91#ibcon#read 4, iclass 21, count 0 2006.260.07:56:10.91#ibcon#about to read 5, iclass 21, count 0 2006.260.07:56:10.91#ibcon#read 5, iclass 21, count 0 2006.260.07:56:10.91#ibcon#about to read 6, iclass 21, count 0 2006.260.07:56:10.91#ibcon#read 6, iclass 21, count 0 2006.260.07:56:10.91#ibcon#end of sib2, iclass 21, count 0 2006.260.07:56:10.91#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:56:10.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:56:10.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:56:10.91#ibcon#*before write, iclass 21, count 0 2006.260.07:56:10.91#ibcon#enter sib2, iclass 21, count 0 2006.260.07:56:10.91#ibcon#flushed, iclass 21, count 0 2006.260.07:56:10.91#ibcon#about to write, iclass 21, count 0 2006.260.07:56:10.91#ibcon#wrote, iclass 21, count 0 2006.260.07:56:10.91#ibcon#about to read 3, iclass 21, count 0 2006.260.07:56:10.95#ibcon#read 3, iclass 21, count 0 2006.260.07:56:10.95#ibcon#about to read 4, iclass 21, count 0 2006.260.07:56:10.95#ibcon#read 4, iclass 21, count 0 2006.260.07:56:10.95#ibcon#about to read 5, iclass 21, count 0 2006.260.07:56:10.95#ibcon#read 5, iclass 21, count 0 2006.260.07:56:10.95#ibcon#about to read 6, iclass 21, count 0 2006.260.07:56:10.95#ibcon#read 6, iclass 21, count 0 2006.260.07:56:10.95#ibcon#end of sib2, iclass 21, count 0 2006.260.07:56:10.95#ibcon#*after write, iclass 21, count 0 2006.260.07:56:10.95#ibcon#*before return 0, iclass 21, count 0 2006.260.07:56:10.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:10.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:10.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:56:10.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:56:10.95$vc4f8/va=6,6 2006.260.07:56:10.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.07:56:10.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.07:56:10.95#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:10.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:11.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:11.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:11.01#ibcon#enter wrdev, iclass 23, count 2 2006.260.07:56:11.01#ibcon#first serial, iclass 23, count 2 2006.260.07:56:11.01#ibcon#enter sib2, iclass 23, count 2 2006.260.07:56:11.01#ibcon#flushed, iclass 23, count 2 2006.260.07:56:11.01#ibcon#about to write, iclass 23, count 2 2006.260.07:56:11.01#ibcon#wrote, iclass 23, count 2 2006.260.07:56:11.01#ibcon#about to read 3, iclass 23, count 2 2006.260.07:56:11.03#ibcon#read 3, iclass 23, count 2 2006.260.07:56:11.03#ibcon#about to read 4, iclass 23, count 2 2006.260.07:56:11.03#ibcon#read 4, iclass 23, count 2 2006.260.07:56:11.03#ibcon#about to read 5, iclass 23, count 2 2006.260.07:56:11.03#ibcon#read 5, iclass 23, count 2 2006.260.07:56:11.03#ibcon#about to read 6, iclass 23, count 2 2006.260.07:56:11.03#ibcon#read 6, iclass 23, count 2 2006.260.07:56:11.03#ibcon#end of sib2, iclass 23, count 2 2006.260.07:56:11.03#ibcon#*mode == 0, iclass 23, count 2 2006.260.07:56:11.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.07:56:11.03#ibcon#[25=AT06-06\r\n] 2006.260.07:56:11.03#ibcon#*before write, iclass 23, count 2 2006.260.07:56:11.03#ibcon#enter sib2, iclass 23, count 2 2006.260.07:56:11.03#ibcon#flushed, iclass 23, count 2 2006.260.07:56:11.03#ibcon#about to write, iclass 23, count 2 2006.260.07:56:11.03#ibcon#wrote, iclass 23, count 2 2006.260.07:56:11.03#ibcon#about to read 3, iclass 23, count 2 2006.260.07:56:11.06#ibcon#read 3, iclass 23, count 2 2006.260.07:56:11.06#ibcon#about to read 4, iclass 23, count 2 2006.260.07:56:11.06#ibcon#read 4, iclass 23, count 2 2006.260.07:56:11.06#ibcon#about to read 5, iclass 23, count 2 2006.260.07:56:11.06#ibcon#read 5, iclass 23, count 2 2006.260.07:56:11.06#ibcon#about to read 6, iclass 23, count 2 2006.260.07:56:11.06#ibcon#read 6, iclass 23, count 2 2006.260.07:56:11.06#ibcon#end of sib2, iclass 23, count 2 2006.260.07:56:11.06#ibcon#*after write, iclass 23, count 2 2006.260.07:56:11.06#ibcon#*before return 0, iclass 23, count 2 2006.260.07:56:11.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:11.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:11.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.07:56:11.06#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:11.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:56:11.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:56:11.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:56:11.18#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:56:11.18#ibcon#first serial, iclass 23, count 0 2006.260.07:56:11.18#ibcon#enter sib2, iclass 23, count 0 2006.260.07:56:11.18#ibcon#flushed, iclass 23, count 0 2006.260.07:56:11.18#ibcon#about to write, iclass 23, count 0 2006.260.07:56:11.18#ibcon#wrote, iclass 23, count 0 2006.260.07:56:11.18#ibcon#about to read 3, iclass 23, count 0 2006.260.07:56:11.20#ibcon#read 3, iclass 23, count 0 2006.260.07:56:11.20#ibcon#about to read 4, iclass 23, count 0 2006.260.07:56:11.20#ibcon#read 4, iclass 23, count 0 2006.260.07:56:11.20#ibcon#about to read 5, iclass 23, count 0 2006.260.07:56:11.20#ibcon#read 5, iclass 23, count 0 2006.260.07:56:11.20#ibcon#about to read 6, iclass 23, count 0 2006.260.07:56:11.20#ibcon#read 6, iclass 23, count 0 2006.260.07:56:11.20#ibcon#end of sib2, iclass 23, count 0 2006.260.07:56:11.20#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:56:11.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:56:11.20#ibcon#[25=USB\r\n] 2006.260.07:56:11.20#ibcon#*before write, iclass 23, count 0 2006.260.07:56:11.20#ibcon#enter sib2, iclass 23, count 0 2006.260.07:56:11.20#ibcon#flushed, iclass 23, count 0 2006.260.07:56:11.20#ibcon#about to write, iclass 23, count 0 2006.260.07:56:11.20#ibcon#wrote, iclass 23, count 0 2006.260.07:56:11.20#ibcon#about to read 3, iclass 23, count 0 2006.260.07:56:11.23#ibcon#read 3, iclass 23, count 0 2006.260.07:56:11.23#ibcon#about to read 4, iclass 23, count 0 2006.260.07:56:11.23#ibcon#read 4, iclass 23, count 0 2006.260.07:56:11.23#ibcon#about to read 5, iclass 23, count 0 2006.260.07:56:11.23#ibcon#read 5, iclass 23, count 0 2006.260.07:56:11.23#ibcon#about to read 6, iclass 23, count 0 2006.260.07:56:11.23#ibcon#read 6, iclass 23, count 0 2006.260.07:56:11.23#ibcon#end of sib2, iclass 23, count 0 2006.260.07:56:11.23#ibcon#*after write, iclass 23, count 0 2006.260.07:56:11.23#ibcon#*before return 0, iclass 23, count 0 2006.260.07:56:11.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:56:11.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.07:56:11.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:56:11.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:56:11.23$vc4f8/valo=7,832.99 2006.260.07:56:11.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.07:56:11.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.07:56:11.23#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:11.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:56:11.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:56:11.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:56:11.23#ibcon#enter wrdev, iclass 25, count 0 2006.260.07:56:11.23#ibcon#first serial, iclass 25, count 0 2006.260.07:56:11.23#ibcon#enter sib2, iclass 25, count 0 2006.260.07:56:11.23#ibcon#flushed, iclass 25, count 0 2006.260.07:56:11.23#ibcon#about to write, iclass 25, count 0 2006.260.07:56:11.23#ibcon#wrote, iclass 25, count 0 2006.260.07:56:11.23#ibcon#about to read 3, iclass 25, count 0 2006.260.07:56:11.25#ibcon#read 3, iclass 25, count 0 2006.260.07:56:11.25#ibcon#about to read 4, iclass 25, count 0 2006.260.07:56:11.25#ibcon#read 4, iclass 25, count 0 2006.260.07:56:11.25#ibcon#about to read 5, iclass 25, count 0 2006.260.07:56:11.25#ibcon#read 5, iclass 25, count 0 2006.260.07:56:11.25#ibcon#about to read 6, iclass 25, count 0 2006.260.07:56:11.25#ibcon#read 6, iclass 25, count 0 2006.260.07:56:11.25#ibcon#end of sib2, iclass 25, count 0 2006.260.07:56:11.25#ibcon#*mode == 0, iclass 25, count 0 2006.260.07:56:11.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.07:56:11.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:56:11.25#ibcon#*before write, iclass 25, count 0 2006.260.07:56:11.25#ibcon#enter sib2, iclass 25, count 0 2006.260.07:56:11.25#ibcon#flushed, iclass 25, count 0 2006.260.07:56:11.25#ibcon#about to write, iclass 25, count 0 2006.260.07:56:11.25#ibcon#wrote, iclass 25, count 0 2006.260.07:56:11.25#ibcon#about to read 3, iclass 25, count 0 2006.260.07:56:11.29#ibcon#read 3, iclass 25, count 0 2006.260.07:56:11.29#ibcon#about to read 4, iclass 25, count 0 2006.260.07:56:11.29#ibcon#read 4, iclass 25, count 0 2006.260.07:56:11.29#ibcon#about to read 5, iclass 25, count 0 2006.260.07:56:11.29#ibcon#read 5, iclass 25, count 0 2006.260.07:56:11.29#ibcon#about to read 6, iclass 25, count 0 2006.260.07:56:11.29#ibcon#read 6, iclass 25, count 0 2006.260.07:56:11.29#ibcon#end of sib2, iclass 25, count 0 2006.260.07:56:11.29#ibcon#*after write, iclass 25, count 0 2006.260.07:56:11.29#ibcon#*before return 0, iclass 25, count 0 2006.260.07:56:11.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:56:11.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.07:56:11.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.07:56:11.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.07:56:11.29$vc4f8/va=7,6 2006.260.07:56:11.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.07:56:11.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.07:56:11.29#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:11.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:56:11.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:56:11.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:56:11.35#ibcon#enter wrdev, iclass 27, count 2 2006.260.07:56:11.35#ibcon#first serial, iclass 27, count 2 2006.260.07:56:11.35#ibcon#enter sib2, iclass 27, count 2 2006.260.07:56:11.35#ibcon#flushed, iclass 27, count 2 2006.260.07:56:11.35#ibcon#about to write, iclass 27, count 2 2006.260.07:56:11.35#ibcon#wrote, iclass 27, count 2 2006.260.07:56:11.35#ibcon#about to read 3, iclass 27, count 2 2006.260.07:56:11.37#ibcon#read 3, iclass 27, count 2 2006.260.07:56:11.37#ibcon#about to read 4, iclass 27, count 2 2006.260.07:56:11.37#ibcon#read 4, iclass 27, count 2 2006.260.07:56:11.37#ibcon#about to read 5, iclass 27, count 2 2006.260.07:56:11.37#ibcon#read 5, iclass 27, count 2 2006.260.07:56:11.37#ibcon#about to read 6, iclass 27, count 2 2006.260.07:56:11.37#ibcon#read 6, iclass 27, count 2 2006.260.07:56:11.37#ibcon#end of sib2, iclass 27, count 2 2006.260.07:56:11.37#ibcon#*mode == 0, iclass 27, count 2 2006.260.07:56:11.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.07:56:11.37#ibcon#[25=AT07-06\r\n] 2006.260.07:56:11.37#ibcon#*before write, iclass 27, count 2 2006.260.07:56:11.37#ibcon#enter sib2, iclass 27, count 2 2006.260.07:56:11.37#ibcon#flushed, iclass 27, count 2 2006.260.07:56:11.37#ibcon#about to write, iclass 27, count 2 2006.260.07:56:11.37#ibcon#wrote, iclass 27, count 2 2006.260.07:56:11.37#ibcon#about to read 3, iclass 27, count 2 2006.260.07:56:11.40#ibcon#read 3, iclass 27, count 2 2006.260.07:56:11.40#ibcon#about to read 4, iclass 27, count 2 2006.260.07:56:11.40#ibcon#read 4, iclass 27, count 2 2006.260.07:56:11.40#ibcon#about to read 5, iclass 27, count 2 2006.260.07:56:11.40#ibcon#read 5, iclass 27, count 2 2006.260.07:56:11.40#ibcon#about to read 6, iclass 27, count 2 2006.260.07:56:11.40#ibcon#read 6, iclass 27, count 2 2006.260.07:56:11.40#ibcon#end of sib2, iclass 27, count 2 2006.260.07:56:11.40#ibcon#*after write, iclass 27, count 2 2006.260.07:56:11.40#ibcon#*before return 0, iclass 27, count 2 2006.260.07:56:11.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:56:11.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.07:56:11.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.07:56:11.40#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:11.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:56:11.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:56:11.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:56:11.52#ibcon#enter wrdev, iclass 27, count 0 2006.260.07:56:11.52#ibcon#first serial, iclass 27, count 0 2006.260.07:56:11.52#ibcon#enter sib2, iclass 27, count 0 2006.260.07:56:11.52#ibcon#flushed, iclass 27, count 0 2006.260.07:56:11.52#ibcon#about to write, iclass 27, count 0 2006.260.07:56:11.52#ibcon#wrote, iclass 27, count 0 2006.260.07:56:11.52#ibcon#about to read 3, iclass 27, count 0 2006.260.07:56:11.55#ibcon#read 3, iclass 27, count 0 2006.260.07:56:11.55#ibcon#about to read 4, iclass 27, count 0 2006.260.07:56:11.55#ibcon#read 4, iclass 27, count 0 2006.260.07:56:11.55#ibcon#about to read 5, iclass 27, count 0 2006.260.07:56:11.55#ibcon#read 5, iclass 27, count 0 2006.260.07:56:11.55#ibcon#about to read 6, iclass 27, count 0 2006.260.07:56:11.55#ibcon#read 6, iclass 27, count 0 2006.260.07:56:11.55#ibcon#end of sib2, iclass 27, count 0 2006.260.07:56:11.55#ibcon#*mode == 0, iclass 27, count 0 2006.260.07:56:11.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.07:56:11.55#ibcon#[25=USB\r\n] 2006.260.07:56:11.55#ibcon#*before write, iclass 27, count 0 2006.260.07:56:11.55#ibcon#enter sib2, iclass 27, count 0 2006.260.07:56:11.55#ibcon#flushed, iclass 27, count 0 2006.260.07:56:11.55#ibcon#about to write, iclass 27, count 0 2006.260.07:56:11.55#ibcon#wrote, iclass 27, count 0 2006.260.07:56:11.55#ibcon#about to read 3, iclass 27, count 0 2006.260.07:56:11.58#ibcon#read 3, iclass 27, count 0 2006.260.07:56:11.58#ibcon#about to read 4, iclass 27, count 0 2006.260.07:56:11.58#ibcon#read 4, iclass 27, count 0 2006.260.07:56:11.58#ibcon#about to read 5, iclass 27, count 0 2006.260.07:56:11.58#ibcon#read 5, iclass 27, count 0 2006.260.07:56:11.58#ibcon#about to read 6, iclass 27, count 0 2006.260.07:56:11.58#ibcon#read 6, iclass 27, count 0 2006.260.07:56:11.58#ibcon#end of sib2, iclass 27, count 0 2006.260.07:56:11.58#ibcon#*after write, iclass 27, count 0 2006.260.07:56:11.58#ibcon#*before return 0, iclass 27, count 0 2006.260.07:56:11.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:56:11.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.07:56:11.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.07:56:11.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.07:56:11.58$vc4f8/valo=8,852.99 2006.260.07:56:11.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.07:56:11.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.07:56:11.58#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:11.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:56:11.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:56:11.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:56:11.58#ibcon#enter wrdev, iclass 29, count 0 2006.260.07:56:11.58#ibcon#first serial, iclass 29, count 0 2006.260.07:56:11.58#ibcon#enter sib2, iclass 29, count 0 2006.260.07:56:11.58#ibcon#flushed, iclass 29, count 0 2006.260.07:56:11.58#ibcon#about to write, iclass 29, count 0 2006.260.07:56:11.58#ibcon#wrote, iclass 29, count 0 2006.260.07:56:11.58#ibcon#about to read 3, iclass 29, count 0 2006.260.07:56:11.60#ibcon#read 3, iclass 29, count 0 2006.260.07:56:11.60#ibcon#about to read 4, iclass 29, count 0 2006.260.07:56:11.60#ibcon#read 4, iclass 29, count 0 2006.260.07:56:11.60#ibcon#about to read 5, iclass 29, count 0 2006.260.07:56:11.60#ibcon#read 5, iclass 29, count 0 2006.260.07:56:11.60#ibcon#about to read 6, iclass 29, count 0 2006.260.07:56:11.60#ibcon#read 6, iclass 29, count 0 2006.260.07:56:11.60#ibcon#end of sib2, iclass 29, count 0 2006.260.07:56:11.60#ibcon#*mode == 0, iclass 29, count 0 2006.260.07:56:11.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.07:56:11.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:56:11.60#ibcon#*before write, iclass 29, count 0 2006.260.07:56:11.60#ibcon#enter sib2, iclass 29, count 0 2006.260.07:56:11.60#ibcon#flushed, iclass 29, count 0 2006.260.07:56:11.60#ibcon#about to write, iclass 29, count 0 2006.260.07:56:11.60#ibcon#wrote, iclass 29, count 0 2006.260.07:56:11.60#ibcon#about to read 3, iclass 29, count 0 2006.260.07:56:11.64#ibcon#read 3, iclass 29, count 0 2006.260.07:56:11.64#ibcon#about to read 4, iclass 29, count 0 2006.260.07:56:11.64#ibcon#read 4, iclass 29, count 0 2006.260.07:56:11.64#ibcon#about to read 5, iclass 29, count 0 2006.260.07:56:11.64#ibcon#read 5, iclass 29, count 0 2006.260.07:56:11.64#ibcon#about to read 6, iclass 29, count 0 2006.260.07:56:11.64#ibcon#read 6, iclass 29, count 0 2006.260.07:56:11.64#ibcon#end of sib2, iclass 29, count 0 2006.260.07:56:11.64#ibcon#*after write, iclass 29, count 0 2006.260.07:56:11.64#ibcon#*before return 0, iclass 29, count 0 2006.260.07:56:11.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:56:11.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.07:56:11.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.07:56:11.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.07:56:11.64$vc4f8/va=8,6 2006.260.07:56:11.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.07:56:11.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.07:56:11.64#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:11.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:56:11.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:56:11.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:56:11.70#ibcon#enter wrdev, iclass 31, count 2 2006.260.07:56:11.70#ibcon#first serial, iclass 31, count 2 2006.260.07:56:11.70#ibcon#enter sib2, iclass 31, count 2 2006.260.07:56:11.70#ibcon#flushed, iclass 31, count 2 2006.260.07:56:11.70#ibcon#about to write, iclass 31, count 2 2006.260.07:56:11.70#ibcon#wrote, iclass 31, count 2 2006.260.07:56:11.70#ibcon#about to read 3, iclass 31, count 2 2006.260.07:56:11.72#ibcon#read 3, iclass 31, count 2 2006.260.07:56:11.72#ibcon#about to read 4, iclass 31, count 2 2006.260.07:56:11.72#ibcon#read 4, iclass 31, count 2 2006.260.07:56:11.72#ibcon#about to read 5, iclass 31, count 2 2006.260.07:56:11.72#ibcon#read 5, iclass 31, count 2 2006.260.07:56:11.72#ibcon#about to read 6, iclass 31, count 2 2006.260.07:56:11.72#ibcon#read 6, iclass 31, count 2 2006.260.07:56:11.72#ibcon#end of sib2, iclass 31, count 2 2006.260.07:56:11.72#ibcon#*mode == 0, iclass 31, count 2 2006.260.07:56:11.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.07:56:11.72#ibcon#[25=AT08-06\r\n] 2006.260.07:56:11.72#ibcon#*before write, iclass 31, count 2 2006.260.07:56:11.72#ibcon#enter sib2, iclass 31, count 2 2006.260.07:56:11.72#ibcon#flushed, iclass 31, count 2 2006.260.07:56:11.72#ibcon#about to write, iclass 31, count 2 2006.260.07:56:11.72#ibcon#wrote, iclass 31, count 2 2006.260.07:56:11.72#ibcon#about to read 3, iclass 31, count 2 2006.260.07:56:11.75#ibcon#read 3, iclass 31, count 2 2006.260.07:56:11.75#ibcon#about to read 4, iclass 31, count 2 2006.260.07:56:11.75#ibcon#read 4, iclass 31, count 2 2006.260.07:56:11.75#ibcon#about to read 5, iclass 31, count 2 2006.260.07:56:11.75#ibcon#read 5, iclass 31, count 2 2006.260.07:56:11.75#ibcon#about to read 6, iclass 31, count 2 2006.260.07:56:11.75#ibcon#read 6, iclass 31, count 2 2006.260.07:56:11.75#ibcon#end of sib2, iclass 31, count 2 2006.260.07:56:11.75#ibcon#*after write, iclass 31, count 2 2006.260.07:56:11.75#ibcon#*before return 0, iclass 31, count 2 2006.260.07:56:11.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:56:11.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.07:56:11.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.07:56:11.75#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:11.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:56:11.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:56:11.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:56:11.87#ibcon#enter wrdev, iclass 31, count 0 2006.260.07:56:11.87#ibcon#first serial, iclass 31, count 0 2006.260.07:56:11.87#ibcon#enter sib2, iclass 31, count 0 2006.260.07:56:11.87#ibcon#flushed, iclass 31, count 0 2006.260.07:56:11.87#ibcon#about to write, iclass 31, count 0 2006.260.07:56:11.87#ibcon#wrote, iclass 31, count 0 2006.260.07:56:11.87#ibcon#about to read 3, iclass 31, count 0 2006.260.07:56:11.89#ibcon#read 3, iclass 31, count 0 2006.260.07:56:11.89#ibcon#about to read 4, iclass 31, count 0 2006.260.07:56:11.89#ibcon#read 4, iclass 31, count 0 2006.260.07:56:11.89#ibcon#about to read 5, iclass 31, count 0 2006.260.07:56:11.89#ibcon#read 5, iclass 31, count 0 2006.260.07:56:11.89#ibcon#about to read 6, iclass 31, count 0 2006.260.07:56:11.89#ibcon#read 6, iclass 31, count 0 2006.260.07:56:11.89#ibcon#end of sib2, iclass 31, count 0 2006.260.07:56:11.89#ibcon#*mode == 0, iclass 31, count 0 2006.260.07:56:11.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.07:56:11.89#ibcon#[25=USB\r\n] 2006.260.07:56:11.89#ibcon#*before write, iclass 31, count 0 2006.260.07:56:11.89#ibcon#enter sib2, iclass 31, count 0 2006.260.07:56:11.89#ibcon#flushed, iclass 31, count 0 2006.260.07:56:11.89#ibcon#about to write, iclass 31, count 0 2006.260.07:56:11.89#ibcon#wrote, iclass 31, count 0 2006.260.07:56:11.89#ibcon#about to read 3, iclass 31, count 0 2006.260.07:56:11.92#ibcon#read 3, iclass 31, count 0 2006.260.07:56:11.92#ibcon#about to read 4, iclass 31, count 0 2006.260.07:56:11.92#ibcon#read 4, iclass 31, count 0 2006.260.07:56:11.92#ibcon#about to read 5, iclass 31, count 0 2006.260.07:56:11.92#ibcon#read 5, iclass 31, count 0 2006.260.07:56:11.92#ibcon#about to read 6, iclass 31, count 0 2006.260.07:56:11.92#ibcon#read 6, iclass 31, count 0 2006.260.07:56:11.92#ibcon#end of sib2, iclass 31, count 0 2006.260.07:56:11.92#ibcon#*after write, iclass 31, count 0 2006.260.07:56:11.92#ibcon#*before return 0, iclass 31, count 0 2006.260.07:56:11.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:56:11.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.07:56:11.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.07:56:11.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.07:56:11.92$vc4f8/vblo=1,632.99 2006.260.07:56:11.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.07:56:11.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.07:56:11.92#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:11.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:56:11.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:56:11.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:56:11.92#ibcon#enter wrdev, iclass 33, count 0 2006.260.07:56:11.92#ibcon#first serial, iclass 33, count 0 2006.260.07:56:11.92#ibcon#enter sib2, iclass 33, count 0 2006.260.07:56:11.92#ibcon#flushed, iclass 33, count 0 2006.260.07:56:11.92#ibcon#about to write, iclass 33, count 0 2006.260.07:56:11.92#ibcon#wrote, iclass 33, count 0 2006.260.07:56:11.92#ibcon#about to read 3, iclass 33, count 0 2006.260.07:56:11.94#ibcon#read 3, iclass 33, count 0 2006.260.07:56:11.94#ibcon#about to read 4, iclass 33, count 0 2006.260.07:56:11.94#ibcon#read 4, iclass 33, count 0 2006.260.07:56:11.94#ibcon#about to read 5, iclass 33, count 0 2006.260.07:56:11.94#ibcon#read 5, iclass 33, count 0 2006.260.07:56:11.94#ibcon#about to read 6, iclass 33, count 0 2006.260.07:56:11.94#ibcon#read 6, iclass 33, count 0 2006.260.07:56:11.94#ibcon#end of sib2, iclass 33, count 0 2006.260.07:56:11.94#ibcon#*mode == 0, iclass 33, count 0 2006.260.07:56:11.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.07:56:11.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:56:11.94#ibcon#*before write, iclass 33, count 0 2006.260.07:56:11.94#ibcon#enter sib2, iclass 33, count 0 2006.260.07:56:11.94#ibcon#flushed, iclass 33, count 0 2006.260.07:56:11.94#ibcon#about to write, iclass 33, count 0 2006.260.07:56:11.94#ibcon#wrote, iclass 33, count 0 2006.260.07:56:11.94#ibcon#about to read 3, iclass 33, count 0 2006.260.07:56:11.98#ibcon#read 3, iclass 33, count 0 2006.260.07:56:11.98#ibcon#about to read 4, iclass 33, count 0 2006.260.07:56:11.98#ibcon#read 4, iclass 33, count 0 2006.260.07:56:11.98#ibcon#about to read 5, iclass 33, count 0 2006.260.07:56:11.98#ibcon#read 5, iclass 33, count 0 2006.260.07:56:11.98#ibcon#about to read 6, iclass 33, count 0 2006.260.07:56:11.98#ibcon#read 6, iclass 33, count 0 2006.260.07:56:11.98#ibcon#end of sib2, iclass 33, count 0 2006.260.07:56:11.98#ibcon#*after write, iclass 33, count 0 2006.260.07:56:11.98#ibcon#*before return 0, iclass 33, count 0 2006.260.07:56:11.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:56:11.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.07:56:11.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.07:56:11.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.07:56:11.98$vc4f8/vb=1,4 2006.260.07:56:11.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.07:56:11.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.07:56:11.98#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:11.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:56:11.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:56:11.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:56:11.98#ibcon#enter wrdev, iclass 35, count 2 2006.260.07:56:11.98#ibcon#first serial, iclass 35, count 2 2006.260.07:56:11.98#ibcon#enter sib2, iclass 35, count 2 2006.260.07:56:11.98#ibcon#flushed, iclass 35, count 2 2006.260.07:56:11.98#ibcon#about to write, iclass 35, count 2 2006.260.07:56:11.98#ibcon#wrote, iclass 35, count 2 2006.260.07:56:11.98#ibcon#about to read 3, iclass 35, count 2 2006.260.07:56:12.00#ibcon#read 3, iclass 35, count 2 2006.260.07:56:12.00#ibcon#about to read 4, iclass 35, count 2 2006.260.07:56:12.00#ibcon#read 4, iclass 35, count 2 2006.260.07:56:12.00#ibcon#about to read 5, iclass 35, count 2 2006.260.07:56:12.00#ibcon#read 5, iclass 35, count 2 2006.260.07:56:12.00#ibcon#about to read 6, iclass 35, count 2 2006.260.07:56:12.00#ibcon#read 6, iclass 35, count 2 2006.260.07:56:12.00#ibcon#end of sib2, iclass 35, count 2 2006.260.07:56:12.00#ibcon#*mode == 0, iclass 35, count 2 2006.260.07:56:12.00#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.07:56:12.00#ibcon#[27=AT01-04\r\n] 2006.260.07:56:12.00#ibcon#*before write, iclass 35, count 2 2006.260.07:56:12.00#ibcon#enter sib2, iclass 35, count 2 2006.260.07:56:12.00#ibcon#flushed, iclass 35, count 2 2006.260.07:56:12.00#ibcon#about to write, iclass 35, count 2 2006.260.07:56:12.00#ibcon#wrote, iclass 35, count 2 2006.260.07:56:12.00#ibcon#about to read 3, iclass 35, count 2 2006.260.07:56:12.03#ibcon#read 3, iclass 35, count 2 2006.260.07:56:12.03#ibcon#about to read 4, iclass 35, count 2 2006.260.07:56:12.03#ibcon#read 4, iclass 35, count 2 2006.260.07:56:12.03#ibcon#about to read 5, iclass 35, count 2 2006.260.07:56:12.03#ibcon#read 5, iclass 35, count 2 2006.260.07:56:12.03#ibcon#about to read 6, iclass 35, count 2 2006.260.07:56:12.03#ibcon#read 6, iclass 35, count 2 2006.260.07:56:12.03#ibcon#end of sib2, iclass 35, count 2 2006.260.07:56:12.03#ibcon#*after write, iclass 35, count 2 2006.260.07:56:12.03#ibcon#*before return 0, iclass 35, count 2 2006.260.07:56:12.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:56:12.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.07:56:12.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.07:56:12.03#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:12.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:56:12.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:56:12.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:56:12.15#ibcon#enter wrdev, iclass 35, count 0 2006.260.07:56:12.15#ibcon#first serial, iclass 35, count 0 2006.260.07:56:12.15#ibcon#enter sib2, iclass 35, count 0 2006.260.07:56:12.15#ibcon#flushed, iclass 35, count 0 2006.260.07:56:12.15#ibcon#about to write, iclass 35, count 0 2006.260.07:56:12.15#ibcon#wrote, iclass 35, count 0 2006.260.07:56:12.15#ibcon#about to read 3, iclass 35, count 0 2006.260.07:56:12.17#ibcon#read 3, iclass 35, count 0 2006.260.07:56:12.17#ibcon#about to read 4, iclass 35, count 0 2006.260.07:56:12.17#ibcon#read 4, iclass 35, count 0 2006.260.07:56:12.17#ibcon#about to read 5, iclass 35, count 0 2006.260.07:56:12.17#ibcon#read 5, iclass 35, count 0 2006.260.07:56:12.17#ibcon#about to read 6, iclass 35, count 0 2006.260.07:56:12.17#ibcon#read 6, iclass 35, count 0 2006.260.07:56:12.17#ibcon#end of sib2, iclass 35, count 0 2006.260.07:56:12.17#ibcon#*mode == 0, iclass 35, count 0 2006.260.07:56:12.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.07:56:12.17#ibcon#[27=USB\r\n] 2006.260.07:56:12.17#ibcon#*before write, iclass 35, count 0 2006.260.07:56:12.17#ibcon#enter sib2, iclass 35, count 0 2006.260.07:56:12.17#ibcon#flushed, iclass 35, count 0 2006.260.07:56:12.17#ibcon#about to write, iclass 35, count 0 2006.260.07:56:12.17#ibcon#wrote, iclass 35, count 0 2006.260.07:56:12.17#ibcon#about to read 3, iclass 35, count 0 2006.260.07:56:12.20#ibcon#read 3, iclass 35, count 0 2006.260.07:56:12.20#ibcon#about to read 4, iclass 35, count 0 2006.260.07:56:12.20#ibcon#read 4, iclass 35, count 0 2006.260.07:56:12.20#ibcon#about to read 5, iclass 35, count 0 2006.260.07:56:12.20#ibcon#read 5, iclass 35, count 0 2006.260.07:56:12.20#ibcon#about to read 6, iclass 35, count 0 2006.260.07:56:12.20#ibcon#read 6, iclass 35, count 0 2006.260.07:56:12.20#ibcon#end of sib2, iclass 35, count 0 2006.260.07:56:12.20#ibcon#*after write, iclass 35, count 0 2006.260.07:56:12.20#ibcon#*before return 0, iclass 35, count 0 2006.260.07:56:12.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:56:12.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.07:56:12.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.07:56:12.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.07:56:12.20$vc4f8/vblo=2,640.99 2006.260.07:56:12.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.07:56:12.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.07:56:12.20#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:12.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:12.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:12.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:12.20#ibcon#enter wrdev, iclass 37, count 0 2006.260.07:56:12.20#ibcon#first serial, iclass 37, count 0 2006.260.07:56:12.20#ibcon#enter sib2, iclass 37, count 0 2006.260.07:56:12.20#ibcon#flushed, iclass 37, count 0 2006.260.07:56:12.20#ibcon#about to write, iclass 37, count 0 2006.260.07:56:12.20#ibcon#wrote, iclass 37, count 0 2006.260.07:56:12.20#ibcon#about to read 3, iclass 37, count 0 2006.260.07:56:12.22#ibcon#read 3, iclass 37, count 0 2006.260.07:56:12.22#ibcon#about to read 4, iclass 37, count 0 2006.260.07:56:12.22#ibcon#read 4, iclass 37, count 0 2006.260.07:56:12.22#ibcon#about to read 5, iclass 37, count 0 2006.260.07:56:12.22#ibcon#read 5, iclass 37, count 0 2006.260.07:56:12.22#ibcon#about to read 6, iclass 37, count 0 2006.260.07:56:12.22#ibcon#read 6, iclass 37, count 0 2006.260.07:56:12.22#ibcon#end of sib2, iclass 37, count 0 2006.260.07:56:12.22#ibcon#*mode == 0, iclass 37, count 0 2006.260.07:56:12.22#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.07:56:12.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:56:12.22#ibcon#*before write, iclass 37, count 0 2006.260.07:56:12.22#ibcon#enter sib2, iclass 37, count 0 2006.260.07:56:12.22#ibcon#flushed, iclass 37, count 0 2006.260.07:56:12.22#ibcon#about to write, iclass 37, count 0 2006.260.07:56:12.22#ibcon#wrote, iclass 37, count 0 2006.260.07:56:12.22#ibcon#about to read 3, iclass 37, count 0 2006.260.07:56:12.26#ibcon#read 3, iclass 37, count 0 2006.260.07:56:12.26#ibcon#about to read 4, iclass 37, count 0 2006.260.07:56:12.26#ibcon#read 4, iclass 37, count 0 2006.260.07:56:12.26#ibcon#about to read 5, iclass 37, count 0 2006.260.07:56:12.26#ibcon#read 5, iclass 37, count 0 2006.260.07:56:12.26#ibcon#about to read 6, iclass 37, count 0 2006.260.07:56:12.26#ibcon#read 6, iclass 37, count 0 2006.260.07:56:12.26#ibcon#end of sib2, iclass 37, count 0 2006.260.07:56:12.26#ibcon#*after write, iclass 37, count 0 2006.260.07:56:12.26#ibcon#*before return 0, iclass 37, count 0 2006.260.07:56:12.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:12.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.07:56:12.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.07:56:12.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.07:56:12.26$vc4f8/vb=2,5 2006.260.07:56:12.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.07:56:12.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.07:56:12.26#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:12.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:12.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:12.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:12.32#ibcon#enter wrdev, iclass 39, count 2 2006.260.07:56:12.32#ibcon#first serial, iclass 39, count 2 2006.260.07:56:12.32#ibcon#enter sib2, iclass 39, count 2 2006.260.07:56:12.32#ibcon#flushed, iclass 39, count 2 2006.260.07:56:12.32#ibcon#about to write, iclass 39, count 2 2006.260.07:56:12.32#ibcon#wrote, iclass 39, count 2 2006.260.07:56:12.32#ibcon#about to read 3, iclass 39, count 2 2006.260.07:56:12.34#ibcon#read 3, iclass 39, count 2 2006.260.07:56:12.34#ibcon#about to read 4, iclass 39, count 2 2006.260.07:56:12.34#ibcon#read 4, iclass 39, count 2 2006.260.07:56:12.34#ibcon#about to read 5, iclass 39, count 2 2006.260.07:56:12.34#ibcon#read 5, iclass 39, count 2 2006.260.07:56:12.34#ibcon#about to read 6, iclass 39, count 2 2006.260.07:56:12.34#ibcon#read 6, iclass 39, count 2 2006.260.07:56:12.34#ibcon#end of sib2, iclass 39, count 2 2006.260.07:56:12.34#ibcon#*mode == 0, iclass 39, count 2 2006.260.07:56:12.34#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.07:56:12.34#ibcon#[27=AT02-05\r\n] 2006.260.07:56:12.34#ibcon#*before write, iclass 39, count 2 2006.260.07:56:12.34#ibcon#enter sib2, iclass 39, count 2 2006.260.07:56:12.34#ibcon#flushed, iclass 39, count 2 2006.260.07:56:12.34#ibcon#about to write, iclass 39, count 2 2006.260.07:56:12.34#ibcon#wrote, iclass 39, count 2 2006.260.07:56:12.34#ibcon#about to read 3, iclass 39, count 2 2006.260.07:56:12.37#ibcon#read 3, iclass 39, count 2 2006.260.07:56:12.37#ibcon#about to read 4, iclass 39, count 2 2006.260.07:56:12.37#ibcon#read 4, iclass 39, count 2 2006.260.07:56:12.37#ibcon#about to read 5, iclass 39, count 2 2006.260.07:56:12.37#ibcon#read 5, iclass 39, count 2 2006.260.07:56:12.37#ibcon#about to read 6, iclass 39, count 2 2006.260.07:56:12.37#ibcon#read 6, iclass 39, count 2 2006.260.07:56:12.37#ibcon#end of sib2, iclass 39, count 2 2006.260.07:56:12.37#ibcon#*after write, iclass 39, count 2 2006.260.07:56:12.37#ibcon#*before return 0, iclass 39, count 2 2006.260.07:56:12.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:12.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.07:56:12.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.07:56:12.37#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:12.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:12.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:12.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:12.49#ibcon#enter wrdev, iclass 39, count 0 2006.260.07:56:12.49#ibcon#first serial, iclass 39, count 0 2006.260.07:56:12.49#ibcon#enter sib2, iclass 39, count 0 2006.260.07:56:12.49#ibcon#flushed, iclass 39, count 0 2006.260.07:56:12.49#ibcon#about to write, iclass 39, count 0 2006.260.07:56:12.49#ibcon#wrote, iclass 39, count 0 2006.260.07:56:12.49#ibcon#about to read 3, iclass 39, count 0 2006.260.07:56:12.51#ibcon#read 3, iclass 39, count 0 2006.260.07:56:12.51#ibcon#about to read 4, iclass 39, count 0 2006.260.07:56:12.51#ibcon#read 4, iclass 39, count 0 2006.260.07:56:12.51#ibcon#about to read 5, iclass 39, count 0 2006.260.07:56:12.51#ibcon#read 5, iclass 39, count 0 2006.260.07:56:12.51#ibcon#about to read 6, iclass 39, count 0 2006.260.07:56:12.51#ibcon#read 6, iclass 39, count 0 2006.260.07:56:12.51#ibcon#end of sib2, iclass 39, count 0 2006.260.07:56:12.51#ibcon#*mode == 0, iclass 39, count 0 2006.260.07:56:12.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.07:56:12.51#ibcon#[27=USB\r\n] 2006.260.07:56:12.51#ibcon#*before write, iclass 39, count 0 2006.260.07:56:12.51#ibcon#enter sib2, iclass 39, count 0 2006.260.07:56:12.51#ibcon#flushed, iclass 39, count 0 2006.260.07:56:12.51#ibcon#about to write, iclass 39, count 0 2006.260.07:56:12.51#ibcon#wrote, iclass 39, count 0 2006.260.07:56:12.51#ibcon#about to read 3, iclass 39, count 0 2006.260.07:56:12.54#ibcon#read 3, iclass 39, count 0 2006.260.07:56:12.54#ibcon#about to read 4, iclass 39, count 0 2006.260.07:56:12.54#ibcon#read 4, iclass 39, count 0 2006.260.07:56:12.54#ibcon#about to read 5, iclass 39, count 0 2006.260.07:56:12.54#ibcon#read 5, iclass 39, count 0 2006.260.07:56:12.54#ibcon#about to read 6, iclass 39, count 0 2006.260.07:56:12.54#ibcon#read 6, iclass 39, count 0 2006.260.07:56:12.54#ibcon#end of sib2, iclass 39, count 0 2006.260.07:56:12.54#ibcon#*after write, iclass 39, count 0 2006.260.07:56:12.54#ibcon#*before return 0, iclass 39, count 0 2006.260.07:56:12.54#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:12.54#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.07:56:12.54#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.07:56:12.54#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.07:56:12.54$vc4f8/vblo=3,656.99 2006.260.07:56:12.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.07:56:12.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.07:56:12.54#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:12.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:12.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:12.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:12.54#ibcon#enter wrdev, iclass 3, count 0 2006.260.07:56:12.54#ibcon#first serial, iclass 3, count 0 2006.260.07:56:12.54#ibcon#enter sib2, iclass 3, count 0 2006.260.07:56:12.54#ibcon#flushed, iclass 3, count 0 2006.260.07:56:12.54#ibcon#about to write, iclass 3, count 0 2006.260.07:56:12.54#ibcon#wrote, iclass 3, count 0 2006.260.07:56:12.54#ibcon#about to read 3, iclass 3, count 0 2006.260.07:56:12.56#ibcon#read 3, iclass 3, count 0 2006.260.07:56:12.56#ibcon#about to read 4, iclass 3, count 0 2006.260.07:56:12.56#ibcon#read 4, iclass 3, count 0 2006.260.07:56:12.56#ibcon#about to read 5, iclass 3, count 0 2006.260.07:56:12.56#ibcon#read 5, iclass 3, count 0 2006.260.07:56:12.56#ibcon#about to read 6, iclass 3, count 0 2006.260.07:56:12.56#ibcon#read 6, iclass 3, count 0 2006.260.07:56:12.56#ibcon#end of sib2, iclass 3, count 0 2006.260.07:56:12.56#ibcon#*mode == 0, iclass 3, count 0 2006.260.07:56:12.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.07:56:12.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:56:12.56#ibcon#*before write, iclass 3, count 0 2006.260.07:56:12.56#ibcon#enter sib2, iclass 3, count 0 2006.260.07:56:12.56#ibcon#flushed, iclass 3, count 0 2006.260.07:56:12.56#ibcon#about to write, iclass 3, count 0 2006.260.07:56:12.56#ibcon#wrote, iclass 3, count 0 2006.260.07:56:12.56#ibcon#about to read 3, iclass 3, count 0 2006.260.07:56:12.60#ibcon#read 3, iclass 3, count 0 2006.260.07:56:12.60#ibcon#about to read 4, iclass 3, count 0 2006.260.07:56:12.60#ibcon#read 4, iclass 3, count 0 2006.260.07:56:12.60#ibcon#about to read 5, iclass 3, count 0 2006.260.07:56:12.60#ibcon#read 5, iclass 3, count 0 2006.260.07:56:12.60#ibcon#about to read 6, iclass 3, count 0 2006.260.07:56:12.60#ibcon#read 6, iclass 3, count 0 2006.260.07:56:12.60#ibcon#end of sib2, iclass 3, count 0 2006.260.07:56:12.60#ibcon#*after write, iclass 3, count 0 2006.260.07:56:12.60#ibcon#*before return 0, iclass 3, count 0 2006.260.07:56:12.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:12.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.07:56:12.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.07:56:12.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.07:56:12.60$vc4f8/vb=3,4 2006.260.07:56:12.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.07:56:12.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.07:56:12.60#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:12.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:12.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:12.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:12.66#ibcon#enter wrdev, iclass 5, count 2 2006.260.07:56:12.66#ibcon#first serial, iclass 5, count 2 2006.260.07:56:12.66#ibcon#enter sib2, iclass 5, count 2 2006.260.07:56:12.66#ibcon#flushed, iclass 5, count 2 2006.260.07:56:12.66#ibcon#about to write, iclass 5, count 2 2006.260.07:56:12.66#ibcon#wrote, iclass 5, count 2 2006.260.07:56:12.66#ibcon#about to read 3, iclass 5, count 2 2006.260.07:56:12.68#ibcon#read 3, iclass 5, count 2 2006.260.07:56:12.68#ibcon#about to read 4, iclass 5, count 2 2006.260.07:56:12.68#ibcon#read 4, iclass 5, count 2 2006.260.07:56:12.68#ibcon#about to read 5, iclass 5, count 2 2006.260.07:56:12.68#ibcon#read 5, iclass 5, count 2 2006.260.07:56:12.68#ibcon#about to read 6, iclass 5, count 2 2006.260.07:56:12.68#ibcon#read 6, iclass 5, count 2 2006.260.07:56:12.68#ibcon#end of sib2, iclass 5, count 2 2006.260.07:56:12.68#ibcon#*mode == 0, iclass 5, count 2 2006.260.07:56:12.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.07:56:12.68#ibcon#[27=AT03-04\r\n] 2006.260.07:56:12.68#ibcon#*before write, iclass 5, count 2 2006.260.07:56:12.68#ibcon#enter sib2, iclass 5, count 2 2006.260.07:56:12.68#ibcon#flushed, iclass 5, count 2 2006.260.07:56:12.68#ibcon#about to write, iclass 5, count 2 2006.260.07:56:12.68#ibcon#wrote, iclass 5, count 2 2006.260.07:56:12.68#ibcon#about to read 3, iclass 5, count 2 2006.260.07:56:12.71#ibcon#read 3, iclass 5, count 2 2006.260.07:56:12.71#ibcon#about to read 4, iclass 5, count 2 2006.260.07:56:12.71#ibcon#read 4, iclass 5, count 2 2006.260.07:56:12.71#ibcon#about to read 5, iclass 5, count 2 2006.260.07:56:12.71#ibcon#read 5, iclass 5, count 2 2006.260.07:56:12.71#ibcon#about to read 6, iclass 5, count 2 2006.260.07:56:12.71#ibcon#read 6, iclass 5, count 2 2006.260.07:56:12.71#ibcon#end of sib2, iclass 5, count 2 2006.260.07:56:12.71#ibcon#*after write, iclass 5, count 2 2006.260.07:56:12.71#ibcon#*before return 0, iclass 5, count 2 2006.260.07:56:12.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:12.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.07:56:12.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.07:56:12.71#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:12.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:12.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:12.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:12.83#ibcon#enter wrdev, iclass 5, count 0 2006.260.07:56:12.83#ibcon#first serial, iclass 5, count 0 2006.260.07:56:12.83#ibcon#enter sib2, iclass 5, count 0 2006.260.07:56:12.83#ibcon#flushed, iclass 5, count 0 2006.260.07:56:12.83#ibcon#about to write, iclass 5, count 0 2006.260.07:56:12.83#ibcon#wrote, iclass 5, count 0 2006.260.07:56:12.83#ibcon#about to read 3, iclass 5, count 0 2006.260.07:56:12.85#ibcon#read 3, iclass 5, count 0 2006.260.07:56:12.85#ibcon#about to read 4, iclass 5, count 0 2006.260.07:56:12.85#ibcon#read 4, iclass 5, count 0 2006.260.07:56:12.85#ibcon#about to read 5, iclass 5, count 0 2006.260.07:56:12.85#ibcon#read 5, iclass 5, count 0 2006.260.07:56:12.85#ibcon#about to read 6, iclass 5, count 0 2006.260.07:56:12.85#ibcon#read 6, iclass 5, count 0 2006.260.07:56:12.85#ibcon#end of sib2, iclass 5, count 0 2006.260.07:56:12.85#ibcon#*mode == 0, iclass 5, count 0 2006.260.07:56:12.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.07:56:12.85#ibcon#[27=USB\r\n] 2006.260.07:56:12.85#ibcon#*before write, iclass 5, count 0 2006.260.07:56:12.85#ibcon#enter sib2, iclass 5, count 0 2006.260.07:56:12.85#ibcon#flushed, iclass 5, count 0 2006.260.07:56:12.85#ibcon#about to write, iclass 5, count 0 2006.260.07:56:12.85#ibcon#wrote, iclass 5, count 0 2006.260.07:56:12.85#ibcon#about to read 3, iclass 5, count 0 2006.260.07:56:12.88#ibcon#read 3, iclass 5, count 0 2006.260.07:56:12.88#ibcon#about to read 4, iclass 5, count 0 2006.260.07:56:12.88#ibcon#read 4, iclass 5, count 0 2006.260.07:56:12.88#ibcon#about to read 5, iclass 5, count 0 2006.260.07:56:12.88#ibcon#read 5, iclass 5, count 0 2006.260.07:56:12.88#ibcon#about to read 6, iclass 5, count 0 2006.260.07:56:12.88#ibcon#read 6, iclass 5, count 0 2006.260.07:56:12.88#ibcon#end of sib2, iclass 5, count 0 2006.260.07:56:12.88#ibcon#*after write, iclass 5, count 0 2006.260.07:56:12.88#ibcon#*before return 0, iclass 5, count 0 2006.260.07:56:12.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:12.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.07:56:12.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.07:56:12.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.07:56:12.88$vc4f8/vblo=4,712.99 2006.260.07:56:12.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.07:56:12.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.07:56:12.88#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:12.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:12.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:12.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:12.88#ibcon#enter wrdev, iclass 7, count 0 2006.260.07:56:12.88#ibcon#first serial, iclass 7, count 0 2006.260.07:56:12.88#ibcon#enter sib2, iclass 7, count 0 2006.260.07:56:12.88#ibcon#flushed, iclass 7, count 0 2006.260.07:56:12.88#ibcon#about to write, iclass 7, count 0 2006.260.07:56:12.88#ibcon#wrote, iclass 7, count 0 2006.260.07:56:12.88#ibcon#about to read 3, iclass 7, count 0 2006.260.07:56:12.90#ibcon#read 3, iclass 7, count 0 2006.260.07:56:12.90#ibcon#about to read 4, iclass 7, count 0 2006.260.07:56:12.90#ibcon#read 4, iclass 7, count 0 2006.260.07:56:12.90#ibcon#about to read 5, iclass 7, count 0 2006.260.07:56:12.90#ibcon#read 5, iclass 7, count 0 2006.260.07:56:12.90#ibcon#about to read 6, iclass 7, count 0 2006.260.07:56:12.90#ibcon#read 6, iclass 7, count 0 2006.260.07:56:12.90#ibcon#end of sib2, iclass 7, count 0 2006.260.07:56:12.90#ibcon#*mode == 0, iclass 7, count 0 2006.260.07:56:12.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.07:56:12.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:56:12.90#ibcon#*before write, iclass 7, count 0 2006.260.07:56:12.90#ibcon#enter sib2, iclass 7, count 0 2006.260.07:56:12.90#ibcon#flushed, iclass 7, count 0 2006.260.07:56:12.90#ibcon#about to write, iclass 7, count 0 2006.260.07:56:12.90#ibcon#wrote, iclass 7, count 0 2006.260.07:56:12.90#ibcon#about to read 3, iclass 7, count 0 2006.260.07:56:12.94#ibcon#read 3, iclass 7, count 0 2006.260.07:56:12.94#ibcon#about to read 4, iclass 7, count 0 2006.260.07:56:12.94#ibcon#read 4, iclass 7, count 0 2006.260.07:56:12.94#ibcon#about to read 5, iclass 7, count 0 2006.260.07:56:12.94#ibcon#read 5, iclass 7, count 0 2006.260.07:56:12.94#ibcon#about to read 6, iclass 7, count 0 2006.260.07:56:12.94#ibcon#read 6, iclass 7, count 0 2006.260.07:56:12.94#ibcon#end of sib2, iclass 7, count 0 2006.260.07:56:12.94#ibcon#*after write, iclass 7, count 0 2006.260.07:56:12.94#ibcon#*before return 0, iclass 7, count 0 2006.260.07:56:12.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:12.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.07:56:12.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.07:56:12.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.07:56:12.94$vc4f8/vb=4,5 2006.260.07:56:12.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.07:56:12.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.07:56:12.94#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:12.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:13.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:13.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:13.00#ibcon#enter wrdev, iclass 11, count 2 2006.260.07:56:13.00#ibcon#first serial, iclass 11, count 2 2006.260.07:56:13.00#ibcon#enter sib2, iclass 11, count 2 2006.260.07:56:13.00#ibcon#flushed, iclass 11, count 2 2006.260.07:56:13.00#ibcon#about to write, iclass 11, count 2 2006.260.07:56:13.00#ibcon#wrote, iclass 11, count 2 2006.260.07:56:13.00#ibcon#about to read 3, iclass 11, count 2 2006.260.07:56:13.02#ibcon#read 3, iclass 11, count 2 2006.260.07:56:13.02#ibcon#about to read 4, iclass 11, count 2 2006.260.07:56:13.02#ibcon#read 4, iclass 11, count 2 2006.260.07:56:13.02#ibcon#about to read 5, iclass 11, count 2 2006.260.07:56:13.02#ibcon#read 5, iclass 11, count 2 2006.260.07:56:13.02#ibcon#about to read 6, iclass 11, count 2 2006.260.07:56:13.02#ibcon#read 6, iclass 11, count 2 2006.260.07:56:13.02#ibcon#end of sib2, iclass 11, count 2 2006.260.07:56:13.02#ibcon#*mode == 0, iclass 11, count 2 2006.260.07:56:13.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.07:56:13.02#ibcon#[27=AT04-05\r\n] 2006.260.07:56:13.02#ibcon#*before write, iclass 11, count 2 2006.260.07:56:13.02#ibcon#enter sib2, iclass 11, count 2 2006.260.07:56:13.02#ibcon#flushed, iclass 11, count 2 2006.260.07:56:13.02#ibcon#about to write, iclass 11, count 2 2006.260.07:56:13.02#ibcon#wrote, iclass 11, count 2 2006.260.07:56:13.02#ibcon#about to read 3, iclass 11, count 2 2006.260.07:56:13.05#ibcon#read 3, iclass 11, count 2 2006.260.07:56:13.05#ibcon#about to read 4, iclass 11, count 2 2006.260.07:56:13.05#ibcon#read 4, iclass 11, count 2 2006.260.07:56:13.05#ibcon#about to read 5, iclass 11, count 2 2006.260.07:56:13.05#ibcon#read 5, iclass 11, count 2 2006.260.07:56:13.05#ibcon#about to read 6, iclass 11, count 2 2006.260.07:56:13.05#ibcon#read 6, iclass 11, count 2 2006.260.07:56:13.05#ibcon#end of sib2, iclass 11, count 2 2006.260.07:56:13.05#ibcon#*after write, iclass 11, count 2 2006.260.07:56:13.05#ibcon#*before return 0, iclass 11, count 2 2006.260.07:56:13.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:13.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.07:56:13.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.07:56:13.05#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:13.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:13.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:13.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:13.17#ibcon#enter wrdev, iclass 11, count 0 2006.260.07:56:13.17#ibcon#first serial, iclass 11, count 0 2006.260.07:56:13.17#ibcon#enter sib2, iclass 11, count 0 2006.260.07:56:13.17#ibcon#flushed, iclass 11, count 0 2006.260.07:56:13.17#ibcon#about to write, iclass 11, count 0 2006.260.07:56:13.17#ibcon#wrote, iclass 11, count 0 2006.260.07:56:13.17#ibcon#about to read 3, iclass 11, count 0 2006.260.07:56:13.19#ibcon#read 3, iclass 11, count 0 2006.260.07:56:13.19#ibcon#about to read 4, iclass 11, count 0 2006.260.07:56:13.19#ibcon#read 4, iclass 11, count 0 2006.260.07:56:13.19#ibcon#about to read 5, iclass 11, count 0 2006.260.07:56:13.19#ibcon#read 5, iclass 11, count 0 2006.260.07:56:13.19#ibcon#about to read 6, iclass 11, count 0 2006.260.07:56:13.19#ibcon#read 6, iclass 11, count 0 2006.260.07:56:13.19#ibcon#end of sib2, iclass 11, count 0 2006.260.07:56:13.19#ibcon#*mode == 0, iclass 11, count 0 2006.260.07:56:13.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.07:56:13.19#ibcon#[27=USB\r\n] 2006.260.07:56:13.19#ibcon#*before write, iclass 11, count 0 2006.260.07:56:13.19#ibcon#enter sib2, iclass 11, count 0 2006.260.07:56:13.19#ibcon#flushed, iclass 11, count 0 2006.260.07:56:13.19#ibcon#about to write, iclass 11, count 0 2006.260.07:56:13.19#ibcon#wrote, iclass 11, count 0 2006.260.07:56:13.19#ibcon#about to read 3, iclass 11, count 0 2006.260.07:56:13.22#ibcon#read 3, iclass 11, count 0 2006.260.07:56:13.22#ibcon#about to read 4, iclass 11, count 0 2006.260.07:56:13.22#ibcon#read 4, iclass 11, count 0 2006.260.07:56:13.22#ibcon#about to read 5, iclass 11, count 0 2006.260.07:56:13.22#ibcon#read 5, iclass 11, count 0 2006.260.07:56:13.22#ibcon#about to read 6, iclass 11, count 0 2006.260.07:56:13.22#ibcon#read 6, iclass 11, count 0 2006.260.07:56:13.22#ibcon#end of sib2, iclass 11, count 0 2006.260.07:56:13.22#ibcon#*after write, iclass 11, count 0 2006.260.07:56:13.22#ibcon#*before return 0, iclass 11, count 0 2006.260.07:56:13.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:13.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.07:56:13.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.07:56:13.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.07:56:13.22$vc4f8/vblo=5,744.99 2006.260.07:56:13.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.07:56:13.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.07:56:13.22#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:13.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:13.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:13.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:13.22#ibcon#enter wrdev, iclass 13, count 0 2006.260.07:56:13.22#ibcon#first serial, iclass 13, count 0 2006.260.07:56:13.22#ibcon#enter sib2, iclass 13, count 0 2006.260.07:56:13.22#ibcon#flushed, iclass 13, count 0 2006.260.07:56:13.22#ibcon#about to write, iclass 13, count 0 2006.260.07:56:13.22#ibcon#wrote, iclass 13, count 0 2006.260.07:56:13.22#ibcon#about to read 3, iclass 13, count 0 2006.260.07:56:13.24#ibcon#read 3, iclass 13, count 0 2006.260.07:56:13.24#ibcon#about to read 4, iclass 13, count 0 2006.260.07:56:13.24#ibcon#read 4, iclass 13, count 0 2006.260.07:56:13.24#ibcon#about to read 5, iclass 13, count 0 2006.260.07:56:13.24#ibcon#read 5, iclass 13, count 0 2006.260.07:56:13.24#ibcon#about to read 6, iclass 13, count 0 2006.260.07:56:13.24#ibcon#read 6, iclass 13, count 0 2006.260.07:56:13.24#ibcon#end of sib2, iclass 13, count 0 2006.260.07:56:13.24#ibcon#*mode == 0, iclass 13, count 0 2006.260.07:56:13.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.07:56:13.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:56:13.24#ibcon#*before write, iclass 13, count 0 2006.260.07:56:13.24#ibcon#enter sib2, iclass 13, count 0 2006.260.07:56:13.24#ibcon#flushed, iclass 13, count 0 2006.260.07:56:13.24#ibcon#about to write, iclass 13, count 0 2006.260.07:56:13.24#ibcon#wrote, iclass 13, count 0 2006.260.07:56:13.24#ibcon#about to read 3, iclass 13, count 0 2006.260.07:56:13.28#ibcon#read 3, iclass 13, count 0 2006.260.07:56:13.28#ibcon#about to read 4, iclass 13, count 0 2006.260.07:56:13.28#ibcon#read 4, iclass 13, count 0 2006.260.07:56:13.28#ibcon#about to read 5, iclass 13, count 0 2006.260.07:56:13.28#ibcon#read 5, iclass 13, count 0 2006.260.07:56:13.28#ibcon#about to read 6, iclass 13, count 0 2006.260.07:56:13.28#ibcon#read 6, iclass 13, count 0 2006.260.07:56:13.28#ibcon#end of sib2, iclass 13, count 0 2006.260.07:56:13.28#ibcon#*after write, iclass 13, count 0 2006.260.07:56:13.28#ibcon#*before return 0, iclass 13, count 0 2006.260.07:56:13.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:13.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.07:56:13.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.07:56:13.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.07:56:13.28$vc4f8/vb=5,4 2006.260.07:56:13.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.07:56:13.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.07:56:13.28#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:13.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:13.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:13.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:13.34#ibcon#enter wrdev, iclass 15, count 2 2006.260.07:56:13.34#ibcon#first serial, iclass 15, count 2 2006.260.07:56:13.34#ibcon#enter sib2, iclass 15, count 2 2006.260.07:56:13.34#ibcon#flushed, iclass 15, count 2 2006.260.07:56:13.34#ibcon#about to write, iclass 15, count 2 2006.260.07:56:13.34#ibcon#wrote, iclass 15, count 2 2006.260.07:56:13.34#ibcon#about to read 3, iclass 15, count 2 2006.260.07:56:13.36#ibcon#read 3, iclass 15, count 2 2006.260.07:56:13.36#ibcon#about to read 4, iclass 15, count 2 2006.260.07:56:13.36#ibcon#read 4, iclass 15, count 2 2006.260.07:56:13.36#ibcon#about to read 5, iclass 15, count 2 2006.260.07:56:13.36#ibcon#read 5, iclass 15, count 2 2006.260.07:56:13.36#ibcon#about to read 6, iclass 15, count 2 2006.260.07:56:13.36#ibcon#read 6, iclass 15, count 2 2006.260.07:56:13.36#ibcon#end of sib2, iclass 15, count 2 2006.260.07:56:13.36#ibcon#*mode == 0, iclass 15, count 2 2006.260.07:56:13.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.07:56:13.36#ibcon#[27=AT05-04\r\n] 2006.260.07:56:13.36#ibcon#*before write, iclass 15, count 2 2006.260.07:56:13.36#ibcon#enter sib2, iclass 15, count 2 2006.260.07:56:13.36#ibcon#flushed, iclass 15, count 2 2006.260.07:56:13.36#ibcon#about to write, iclass 15, count 2 2006.260.07:56:13.36#ibcon#wrote, iclass 15, count 2 2006.260.07:56:13.36#ibcon#about to read 3, iclass 15, count 2 2006.260.07:56:13.39#ibcon#read 3, iclass 15, count 2 2006.260.07:56:13.39#ibcon#about to read 4, iclass 15, count 2 2006.260.07:56:13.39#ibcon#read 4, iclass 15, count 2 2006.260.07:56:13.39#ibcon#about to read 5, iclass 15, count 2 2006.260.07:56:13.39#ibcon#read 5, iclass 15, count 2 2006.260.07:56:13.39#ibcon#about to read 6, iclass 15, count 2 2006.260.07:56:13.39#ibcon#read 6, iclass 15, count 2 2006.260.07:56:13.39#ibcon#end of sib2, iclass 15, count 2 2006.260.07:56:13.39#ibcon#*after write, iclass 15, count 2 2006.260.07:56:13.39#ibcon#*before return 0, iclass 15, count 2 2006.260.07:56:13.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:13.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.07:56:13.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.07:56:13.39#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:13.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:13.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:13.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:13.51#ibcon#enter wrdev, iclass 15, count 0 2006.260.07:56:13.51#ibcon#first serial, iclass 15, count 0 2006.260.07:56:13.51#ibcon#enter sib2, iclass 15, count 0 2006.260.07:56:13.51#ibcon#flushed, iclass 15, count 0 2006.260.07:56:13.51#ibcon#about to write, iclass 15, count 0 2006.260.07:56:13.51#ibcon#wrote, iclass 15, count 0 2006.260.07:56:13.51#ibcon#about to read 3, iclass 15, count 0 2006.260.07:56:13.53#ibcon#read 3, iclass 15, count 0 2006.260.07:56:13.53#ibcon#about to read 4, iclass 15, count 0 2006.260.07:56:13.53#ibcon#read 4, iclass 15, count 0 2006.260.07:56:13.53#ibcon#about to read 5, iclass 15, count 0 2006.260.07:56:13.53#ibcon#read 5, iclass 15, count 0 2006.260.07:56:13.53#ibcon#about to read 6, iclass 15, count 0 2006.260.07:56:13.53#ibcon#read 6, iclass 15, count 0 2006.260.07:56:13.53#ibcon#end of sib2, iclass 15, count 0 2006.260.07:56:13.53#ibcon#*mode == 0, iclass 15, count 0 2006.260.07:56:13.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.07:56:13.53#ibcon#[27=USB\r\n] 2006.260.07:56:13.53#ibcon#*before write, iclass 15, count 0 2006.260.07:56:13.53#ibcon#enter sib2, iclass 15, count 0 2006.260.07:56:13.53#ibcon#flushed, iclass 15, count 0 2006.260.07:56:13.53#ibcon#about to write, iclass 15, count 0 2006.260.07:56:13.53#ibcon#wrote, iclass 15, count 0 2006.260.07:56:13.53#ibcon#about to read 3, iclass 15, count 0 2006.260.07:56:13.56#ibcon#read 3, iclass 15, count 0 2006.260.07:56:13.56#ibcon#about to read 4, iclass 15, count 0 2006.260.07:56:13.56#ibcon#read 4, iclass 15, count 0 2006.260.07:56:13.56#ibcon#about to read 5, iclass 15, count 0 2006.260.07:56:13.56#ibcon#read 5, iclass 15, count 0 2006.260.07:56:13.56#ibcon#about to read 6, iclass 15, count 0 2006.260.07:56:13.56#ibcon#read 6, iclass 15, count 0 2006.260.07:56:13.56#ibcon#end of sib2, iclass 15, count 0 2006.260.07:56:13.56#ibcon#*after write, iclass 15, count 0 2006.260.07:56:13.56#ibcon#*before return 0, iclass 15, count 0 2006.260.07:56:13.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:13.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.07:56:13.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.07:56:13.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.07:56:13.56$vc4f8/vblo=6,752.99 2006.260.07:56:13.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.07:56:13.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.07:56:13.56#ibcon#ireg 17 cls_cnt 0 2006.260.07:56:13.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:13.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:13.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:13.56#ibcon#enter wrdev, iclass 17, count 0 2006.260.07:56:13.56#ibcon#first serial, iclass 17, count 0 2006.260.07:56:13.56#ibcon#enter sib2, iclass 17, count 0 2006.260.07:56:13.56#ibcon#flushed, iclass 17, count 0 2006.260.07:56:13.56#ibcon#about to write, iclass 17, count 0 2006.260.07:56:13.56#ibcon#wrote, iclass 17, count 0 2006.260.07:56:13.56#ibcon#about to read 3, iclass 17, count 0 2006.260.07:56:13.58#ibcon#read 3, iclass 17, count 0 2006.260.07:56:13.58#ibcon#about to read 4, iclass 17, count 0 2006.260.07:56:13.58#ibcon#read 4, iclass 17, count 0 2006.260.07:56:13.58#ibcon#about to read 5, iclass 17, count 0 2006.260.07:56:13.58#ibcon#read 5, iclass 17, count 0 2006.260.07:56:13.58#ibcon#about to read 6, iclass 17, count 0 2006.260.07:56:13.58#ibcon#read 6, iclass 17, count 0 2006.260.07:56:13.58#ibcon#end of sib2, iclass 17, count 0 2006.260.07:56:13.58#ibcon#*mode == 0, iclass 17, count 0 2006.260.07:56:13.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.07:56:13.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:56:13.58#ibcon#*before write, iclass 17, count 0 2006.260.07:56:13.58#ibcon#enter sib2, iclass 17, count 0 2006.260.07:56:13.58#ibcon#flushed, iclass 17, count 0 2006.260.07:56:13.58#ibcon#about to write, iclass 17, count 0 2006.260.07:56:13.58#ibcon#wrote, iclass 17, count 0 2006.260.07:56:13.58#ibcon#about to read 3, iclass 17, count 0 2006.260.07:56:13.62#ibcon#read 3, iclass 17, count 0 2006.260.07:56:13.62#ibcon#about to read 4, iclass 17, count 0 2006.260.07:56:13.62#ibcon#read 4, iclass 17, count 0 2006.260.07:56:13.62#ibcon#about to read 5, iclass 17, count 0 2006.260.07:56:13.62#ibcon#read 5, iclass 17, count 0 2006.260.07:56:13.62#ibcon#about to read 6, iclass 17, count 0 2006.260.07:56:13.62#ibcon#read 6, iclass 17, count 0 2006.260.07:56:13.62#ibcon#end of sib2, iclass 17, count 0 2006.260.07:56:13.62#ibcon#*after write, iclass 17, count 0 2006.260.07:56:13.62#ibcon#*before return 0, iclass 17, count 0 2006.260.07:56:13.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:13.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.07:56:13.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.07:56:13.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.07:56:13.62$vc4f8/vb=6,4 2006.260.07:56:13.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.07:56:13.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.07:56:13.62#ibcon#ireg 11 cls_cnt 2 2006.260.07:56:13.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:13.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:13.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:13.68#ibcon#enter wrdev, iclass 19, count 2 2006.260.07:56:13.68#ibcon#first serial, iclass 19, count 2 2006.260.07:56:13.68#ibcon#enter sib2, iclass 19, count 2 2006.260.07:56:13.68#ibcon#flushed, iclass 19, count 2 2006.260.07:56:13.68#ibcon#about to write, iclass 19, count 2 2006.260.07:56:13.68#ibcon#wrote, iclass 19, count 2 2006.260.07:56:13.68#ibcon#about to read 3, iclass 19, count 2 2006.260.07:56:13.70#ibcon#read 3, iclass 19, count 2 2006.260.07:56:13.70#ibcon#about to read 4, iclass 19, count 2 2006.260.07:56:13.70#ibcon#read 4, iclass 19, count 2 2006.260.07:56:13.70#ibcon#about to read 5, iclass 19, count 2 2006.260.07:56:13.70#ibcon#read 5, iclass 19, count 2 2006.260.07:56:13.70#ibcon#about to read 6, iclass 19, count 2 2006.260.07:56:13.70#ibcon#read 6, iclass 19, count 2 2006.260.07:56:13.70#ibcon#end of sib2, iclass 19, count 2 2006.260.07:56:13.70#ibcon#*mode == 0, iclass 19, count 2 2006.260.07:56:13.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.07:56:13.70#ibcon#[27=AT06-04\r\n] 2006.260.07:56:13.70#ibcon#*before write, iclass 19, count 2 2006.260.07:56:13.70#ibcon#enter sib2, iclass 19, count 2 2006.260.07:56:13.70#ibcon#flushed, iclass 19, count 2 2006.260.07:56:13.70#ibcon#about to write, iclass 19, count 2 2006.260.07:56:13.70#ibcon#wrote, iclass 19, count 2 2006.260.07:56:13.70#ibcon#about to read 3, iclass 19, count 2 2006.260.07:56:13.73#ibcon#read 3, iclass 19, count 2 2006.260.07:56:13.73#ibcon#about to read 4, iclass 19, count 2 2006.260.07:56:13.73#ibcon#read 4, iclass 19, count 2 2006.260.07:56:13.73#ibcon#about to read 5, iclass 19, count 2 2006.260.07:56:13.73#ibcon#read 5, iclass 19, count 2 2006.260.07:56:13.73#ibcon#about to read 6, iclass 19, count 2 2006.260.07:56:13.73#ibcon#read 6, iclass 19, count 2 2006.260.07:56:13.73#ibcon#end of sib2, iclass 19, count 2 2006.260.07:56:13.73#ibcon#*after write, iclass 19, count 2 2006.260.07:56:13.73#ibcon#*before return 0, iclass 19, count 2 2006.260.07:56:13.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:13.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.07:56:13.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.07:56:13.73#ibcon#ireg 7 cls_cnt 0 2006.260.07:56:13.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:13.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:13.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:13.85#ibcon#enter wrdev, iclass 19, count 0 2006.260.07:56:13.85#ibcon#first serial, iclass 19, count 0 2006.260.07:56:13.85#ibcon#enter sib2, iclass 19, count 0 2006.260.07:56:13.85#ibcon#flushed, iclass 19, count 0 2006.260.07:56:13.85#ibcon#about to write, iclass 19, count 0 2006.260.07:56:13.85#ibcon#wrote, iclass 19, count 0 2006.260.07:56:13.85#ibcon#about to read 3, iclass 19, count 0 2006.260.07:56:13.87#ibcon#read 3, iclass 19, count 0 2006.260.07:56:13.87#ibcon#about to read 4, iclass 19, count 0 2006.260.07:56:13.87#ibcon#read 4, iclass 19, count 0 2006.260.07:56:13.87#ibcon#about to read 5, iclass 19, count 0 2006.260.07:56:13.87#ibcon#read 5, iclass 19, count 0 2006.260.07:56:13.87#ibcon#about to read 6, iclass 19, count 0 2006.260.07:56:13.87#ibcon#read 6, iclass 19, count 0 2006.260.07:56:13.87#ibcon#end of sib2, iclass 19, count 0 2006.260.07:56:13.87#ibcon#*mode == 0, iclass 19, count 0 2006.260.07:56:13.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.07:56:13.87#ibcon#[27=USB\r\n] 2006.260.07:56:13.87#ibcon#*before write, iclass 19, count 0 2006.260.07:56:13.87#ibcon#enter sib2, iclass 19, count 0 2006.260.07:56:13.87#ibcon#flushed, iclass 19, count 0 2006.260.07:56:13.87#ibcon#about to write, iclass 19, count 0 2006.260.07:56:13.87#ibcon#wrote, iclass 19, count 0 2006.260.07:56:13.87#ibcon#about to read 3, iclass 19, count 0 2006.260.07:56:13.90#ibcon#read 3, iclass 19, count 0 2006.260.07:56:13.90#ibcon#about to read 4, iclass 19, count 0 2006.260.07:56:13.90#ibcon#read 4, iclass 19, count 0 2006.260.07:56:13.90#ibcon#about to read 5, iclass 19, count 0 2006.260.07:56:13.90#ibcon#read 5, iclass 19, count 0 2006.260.07:56:13.90#ibcon#about to read 6, iclass 19, count 0 2006.260.07:56:13.90#ibcon#read 6, iclass 19, count 0 2006.260.07:56:13.90#ibcon#end of sib2, iclass 19, count 0 2006.260.07:56:13.90#ibcon#*after write, iclass 19, count 0 2006.260.07:56:13.90#ibcon#*before return 0, iclass 19, count 0 2006.260.07:56:13.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:13.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.07:56:13.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.07:56:13.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.07:56:13.90$vc4f8/vabw=wide 2006.260.07:56:13.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.07:56:13.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.07:56:13.90#ibcon#ireg 8 cls_cnt 0 2006.260.07:56:13.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:13.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:13.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:13.90#ibcon#enter wrdev, iclass 21, count 0 2006.260.07:56:13.90#ibcon#first serial, iclass 21, count 0 2006.260.07:56:13.90#ibcon#enter sib2, iclass 21, count 0 2006.260.07:56:13.90#ibcon#flushed, iclass 21, count 0 2006.260.07:56:13.90#ibcon#about to write, iclass 21, count 0 2006.260.07:56:13.90#ibcon#wrote, iclass 21, count 0 2006.260.07:56:13.90#ibcon#about to read 3, iclass 21, count 0 2006.260.07:56:13.92#ibcon#read 3, iclass 21, count 0 2006.260.07:56:13.92#ibcon#about to read 4, iclass 21, count 0 2006.260.07:56:13.92#ibcon#read 4, iclass 21, count 0 2006.260.07:56:13.92#ibcon#about to read 5, iclass 21, count 0 2006.260.07:56:13.92#ibcon#read 5, iclass 21, count 0 2006.260.07:56:13.92#ibcon#about to read 6, iclass 21, count 0 2006.260.07:56:13.92#ibcon#read 6, iclass 21, count 0 2006.260.07:56:13.92#ibcon#end of sib2, iclass 21, count 0 2006.260.07:56:13.92#ibcon#*mode == 0, iclass 21, count 0 2006.260.07:56:13.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.07:56:13.92#ibcon#[25=BW32\r\n] 2006.260.07:56:13.92#ibcon#*before write, iclass 21, count 0 2006.260.07:56:13.92#ibcon#enter sib2, iclass 21, count 0 2006.260.07:56:13.92#ibcon#flushed, iclass 21, count 0 2006.260.07:56:13.92#ibcon#about to write, iclass 21, count 0 2006.260.07:56:13.92#ibcon#wrote, iclass 21, count 0 2006.260.07:56:13.92#ibcon#about to read 3, iclass 21, count 0 2006.260.07:56:13.95#ibcon#read 3, iclass 21, count 0 2006.260.07:56:13.95#ibcon#about to read 4, iclass 21, count 0 2006.260.07:56:13.95#ibcon#read 4, iclass 21, count 0 2006.260.07:56:13.95#ibcon#about to read 5, iclass 21, count 0 2006.260.07:56:13.95#ibcon#read 5, iclass 21, count 0 2006.260.07:56:13.95#ibcon#about to read 6, iclass 21, count 0 2006.260.07:56:13.95#ibcon#read 6, iclass 21, count 0 2006.260.07:56:13.95#ibcon#end of sib2, iclass 21, count 0 2006.260.07:56:13.95#ibcon#*after write, iclass 21, count 0 2006.260.07:56:13.95#ibcon#*before return 0, iclass 21, count 0 2006.260.07:56:13.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:13.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.07:56:13.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.07:56:13.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.07:56:13.95$vc4f8/vbbw=wide 2006.260.07:56:13.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.07:56:13.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.07:56:13.95#ibcon#ireg 8 cls_cnt 0 2006.260.07:56:13.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:56:14.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:56:14.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:56:14.02#ibcon#enter wrdev, iclass 23, count 0 2006.260.07:56:14.02#ibcon#first serial, iclass 23, count 0 2006.260.07:56:14.02#ibcon#enter sib2, iclass 23, count 0 2006.260.07:56:14.02#ibcon#flushed, iclass 23, count 0 2006.260.07:56:14.02#ibcon#about to write, iclass 23, count 0 2006.260.07:56:14.02#ibcon#wrote, iclass 23, count 0 2006.260.07:56:14.02#ibcon#about to read 3, iclass 23, count 0 2006.260.07:56:14.05#ibcon#read 3, iclass 23, count 0 2006.260.07:56:14.05#ibcon#about to read 4, iclass 23, count 0 2006.260.07:56:14.05#ibcon#read 4, iclass 23, count 0 2006.260.07:56:14.05#ibcon#about to read 5, iclass 23, count 0 2006.260.07:56:14.05#ibcon#read 5, iclass 23, count 0 2006.260.07:56:14.05#ibcon#about to read 6, iclass 23, count 0 2006.260.07:56:14.05#ibcon#read 6, iclass 23, count 0 2006.260.07:56:14.05#ibcon#end of sib2, iclass 23, count 0 2006.260.07:56:14.05#ibcon#*mode == 0, iclass 23, count 0 2006.260.07:56:14.05#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.07:56:14.05#ibcon#[27=BW32\r\n] 2006.260.07:56:14.05#ibcon#*before write, iclass 23, count 0 2006.260.07:56:14.05#ibcon#enter sib2, iclass 23, count 0 2006.260.07:56:14.05#ibcon#flushed, iclass 23, count 0 2006.260.07:56:14.05#ibcon#about to write, iclass 23, count 0 2006.260.07:56:14.05#ibcon#wrote, iclass 23, count 0 2006.260.07:56:14.05#ibcon#about to read 3, iclass 23, count 0 2006.260.07:56:14.08#ibcon#read 3, iclass 23, count 0 2006.260.07:56:14.08#ibcon#about to read 4, iclass 23, count 0 2006.260.07:56:14.08#ibcon#read 4, iclass 23, count 0 2006.260.07:56:14.08#ibcon#about to read 5, iclass 23, count 0 2006.260.07:56:14.08#ibcon#read 5, iclass 23, count 0 2006.260.07:56:14.08#ibcon#about to read 6, iclass 23, count 0 2006.260.07:56:14.08#ibcon#read 6, iclass 23, count 0 2006.260.07:56:14.08#ibcon#end of sib2, iclass 23, count 0 2006.260.07:56:14.08#ibcon#*after write, iclass 23, count 0 2006.260.07:56:14.08#ibcon#*before return 0, iclass 23, count 0 2006.260.07:56:14.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:56:14.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.07:56:14.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.07:56:14.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.07:56:14.08$4f8m12a/ifd4f 2006.260.07:56:14.08$ifd4f/lo= 2006.260.07:56:14.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:56:14.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:56:14.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:56:14.08$ifd4f/patch= 2006.260.07:56:14.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:56:14.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:56:14.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:56:14.09$4f8m12a/"form=m,16.000,1:2 2006.260.07:56:14.09$4f8m12a/"tpicd 2006.260.07:56:14.09$4f8m12a/echo=off 2006.260.07:56:14.09$4f8m12a/xlog=off 2006.260.07:56:14.09:!2006.260.07:58:20 2006.260.07:56:36.14#trakl#Source acquired 2006.260.07:56:36.14#flagr#flagr/antenna,acquired 2006.260.07:58:20.01:preob 2006.260.07:58:21.14/onsource/TRACKING 2006.260.07:58:21.14:!2006.260.07:58:30 2006.260.07:58:30.00:data_valid=on 2006.260.07:58:30.00:midob 2006.260.07:58:30.14/onsource/TRACKING 2006.260.07:58:30.14/wx/22.89,1010.4,88 2006.260.07:58:30.28/cable/+6.4546E-03 2006.260.07:58:31.37/va/01,08,usb,yes,35,36 2006.260.07:58:31.37/va/02,07,usb,yes,35,36 2006.260.07:58:31.37/va/03,08,usb,yes,26,27 2006.260.07:58:31.37/va/04,07,usb,yes,36,39 2006.260.07:58:31.37/va/05,07,usb,yes,40,42 2006.260.07:58:31.37/va/06,06,usb,yes,39,39 2006.260.07:58:31.37/va/07,06,usb,yes,40,40 2006.260.07:58:31.37/va/08,06,usb,yes,43,42 2006.260.07:58:31.60/valo/01,532.99,yes,locked 2006.260.07:58:31.60/valo/02,572.99,yes,locked 2006.260.07:58:31.60/valo/03,672.99,yes,locked 2006.260.07:58:31.60/valo/04,832.99,yes,locked 2006.260.07:58:31.60/valo/05,652.99,yes,locked 2006.260.07:58:31.60/valo/06,772.99,yes,locked 2006.260.07:58:31.60/valo/07,832.99,yes,locked 2006.260.07:58:31.60/valo/08,852.99,yes,locked 2006.260.07:58:32.69/vb/01,04,usb,yes,32,31 2006.260.07:58:32.69/vb/02,05,usb,yes,30,31 2006.260.07:58:32.69/vb/03,04,usb,yes,30,34 2006.260.07:58:32.69/vb/04,05,usb,yes,28,28 2006.260.07:58:32.69/vb/05,04,usb,yes,30,34 2006.260.07:58:32.69/vb/06,04,usb,yes,31,34 2006.260.07:58:32.69/vb/07,04,usb,yes,33,33 2006.260.07:58:32.69/vb/08,04,usb,yes,30,34 2006.260.07:58:32.93/vblo/01,632.99,yes,locked 2006.260.07:58:32.93/vblo/02,640.99,yes,locked 2006.260.07:58:32.93/vblo/03,656.99,yes,locked 2006.260.07:58:32.93/vblo/04,712.99,yes,locked 2006.260.07:58:32.93/vblo/05,744.99,yes,locked 2006.260.07:58:32.93/vblo/06,752.99,yes,locked 2006.260.07:58:32.93/vblo/07,734.99,yes,locked 2006.260.07:58:32.93/vblo/08,744.99,yes,locked 2006.260.07:58:33.08/vabw/8 2006.260.07:58:33.23/vbbw/8 2006.260.07:58:33.34/xfe/off,on,15.2 2006.260.07:58:33.72/ifatt/23,28,28,28 2006.260.07:58:34.07/fmout-gps/S +4.46E-07 2006.260.07:58:34.11:!2006.260.07:59:30 2006.260.07:59:30.00:data_valid=off 2006.260.07:59:30.01:postob 2006.260.07:59:30.11/cable/+6.4568E-03 2006.260.07:59:30.12/wx/22.88,1010.4,88 2006.260.07:59:31.07/fmout-gps/S +4.46E-07 2006.260.07:59:31.08:scan_name=260-0800,k06260,60 2006.260.07:59:31.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.260.07:59:32.13#flagr#flagr/antenna,new-source 2006.260.07:59:32.14:checkk5 2006.260.07:59:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.260.07:59:32.93/chk_autoobs//k5ts2/ autoobs is running! 2006.260.07:59:33.39/chk_autoobs//k5ts3/ autoobs is running! 2006.260.07:59:33.84/chk_autoobs//k5ts4/ autoobs is running! 2006.260.07:59:34.24/chk_obsdata//k5ts1/T2600758??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:59:34.64/chk_obsdata//k5ts2/T2600758??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:59:35.05/chk_obsdata//k5ts3/T2600758??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:59:35.50/chk_obsdata//k5ts4/T2600758??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.07:59:36.34/k5log//k5ts1_log_newline 2006.260.07:59:37.24/k5log//k5ts2_log_newline 2006.260.07:59:38.01/k5log//k5ts3_log_newline 2006.260.07:59:38.79/k5log//k5ts4_log_newline 2006.260.07:59:38.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.07:59:38.82:4f8m12a=2 2006.260.07:59:38.82$4f8m12a/echo=on 2006.260.07:59:38.82$4f8m12a/pcalon 2006.260.07:59:38.82$pcalon/"no phase cal control is implemented here 2006.260.07:59:38.82$4f8m12a/"tpicd=stop 2006.260.07:59:38.82$4f8m12a/vc4f8 2006.260.07:59:38.82$vc4f8/valo=1,532.99 2006.260.07:59:38.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:59:38.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:59:38.82#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:38.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:38.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:38.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:38.82#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:59:38.82#ibcon#first serial, iclass 34, count 0 2006.260.07:59:38.82#ibcon#enter sib2, iclass 34, count 0 2006.260.07:59:38.82#ibcon#flushed, iclass 34, count 0 2006.260.07:59:38.82#ibcon#about to write, iclass 34, count 0 2006.260.07:59:38.82#ibcon#wrote, iclass 34, count 0 2006.260.07:59:38.82#ibcon#about to read 3, iclass 34, count 0 2006.260.07:59:38.87#ibcon#read 3, iclass 34, count 0 2006.260.07:59:38.87#ibcon#about to read 4, iclass 34, count 0 2006.260.07:59:38.87#ibcon#read 4, iclass 34, count 0 2006.260.07:59:38.87#ibcon#about to read 5, iclass 34, count 0 2006.260.07:59:38.87#ibcon#read 5, iclass 34, count 0 2006.260.07:59:38.87#ibcon#about to read 6, iclass 34, count 0 2006.260.07:59:38.87#ibcon#read 6, iclass 34, count 0 2006.260.07:59:38.87#ibcon#end of sib2, iclass 34, count 0 2006.260.07:59:38.87#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:59:38.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:59:38.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.07:59:38.87#ibcon#*before write, iclass 34, count 0 2006.260.07:59:38.87#ibcon#enter sib2, iclass 34, count 0 2006.260.07:59:38.87#ibcon#flushed, iclass 34, count 0 2006.260.07:59:38.87#ibcon#about to write, iclass 34, count 0 2006.260.07:59:38.87#ibcon#wrote, iclass 34, count 0 2006.260.07:59:38.87#ibcon#about to read 3, iclass 34, count 0 2006.260.07:59:38.91#ibcon#read 3, iclass 34, count 0 2006.260.07:59:38.91#ibcon#about to read 4, iclass 34, count 0 2006.260.07:59:38.91#ibcon#read 4, iclass 34, count 0 2006.260.07:59:38.91#ibcon#about to read 5, iclass 34, count 0 2006.260.07:59:38.91#ibcon#read 5, iclass 34, count 0 2006.260.07:59:38.91#ibcon#about to read 6, iclass 34, count 0 2006.260.07:59:38.91#ibcon#read 6, iclass 34, count 0 2006.260.07:59:38.91#ibcon#end of sib2, iclass 34, count 0 2006.260.07:59:38.91#ibcon#*after write, iclass 34, count 0 2006.260.07:59:38.91#ibcon#*before return 0, iclass 34, count 0 2006.260.07:59:38.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:38.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:38.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:59:38.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:59:38.91$vc4f8/va=1,8 2006.260.07:59:38.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:59:38.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:59:38.91#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:38.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:38.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:38.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:38.91#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:59:38.91#ibcon#first serial, iclass 36, count 2 2006.260.07:59:38.91#ibcon#enter sib2, iclass 36, count 2 2006.260.07:59:38.91#ibcon#flushed, iclass 36, count 2 2006.260.07:59:38.91#ibcon#about to write, iclass 36, count 2 2006.260.07:59:38.91#ibcon#wrote, iclass 36, count 2 2006.260.07:59:38.91#ibcon#about to read 3, iclass 36, count 2 2006.260.07:59:38.93#ibcon#read 3, iclass 36, count 2 2006.260.07:59:38.93#ibcon#about to read 4, iclass 36, count 2 2006.260.07:59:38.93#ibcon#read 4, iclass 36, count 2 2006.260.07:59:38.93#ibcon#about to read 5, iclass 36, count 2 2006.260.07:59:38.93#ibcon#read 5, iclass 36, count 2 2006.260.07:59:38.93#ibcon#about to read 6, iclass 36, count 2 2006.260.07:59:38.93#ibcon#read 6, iclass 36, count 2 2006.260.07:59:38.93#ibcon#end of sib2, iclass 36, count 2 2006.260.07:59:38.93#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:59:38.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:59:38.93#ibcon#[25=AT01-08\r\n] 2006.260.07:59:38.93#ibcon#*before write, iclass 36, count 2 2006.260.07:59:38.93#ibcon#enter sib2, iclass 36, count 2 2006.260.07:59:38.93#ibcon#flushed, iclass 36, count 2 2006.260.07:59:38.93#ibcon#about to write, iclass 36, count 2 2006.260.07:59:38.93#ibcon#wrote, iclass 36, count 2 2006.260.07:59:38.93#ibcon#about to read 3, iclass 36, count 2 2006.260.07:59:38.96#ibcon#read 3, iclass 36, count 2 2006.260.07:59:38.96#ibcon#about to read 4, iclass 36, count 2 2006.260.07:59:38.96#ibcon#read 4, iclass 36, count 2 2006.260.07:59:38.96#ibcon#about to read 5, iclass 36, count 2 2006.260.07:59:38.96#ibcon#read 5, iclass 36, count 2 2006.260.07:59:38.96#ibcon#about to read 6, iclass 36, count 2 2006.260.07:59:38.96#ibcon#read 6, iclass 36, count 2 2006.260.07:59:38.96#ibcon#end of sib2, iclass 36, count 2 2006.260.07:59:38.96#ibcon#*after write, iclass 36, count 2 2006.260.07:59:38.96#ibcon#*before return 0, iclass 36, count 2 2006.260.07:59:38.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:38.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:38.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:59:38.96#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:38.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:39.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:39.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:39.08#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:59:39.08#ibcon#first serial, iclass 36, count 0 2006.260.07:59:39.08#ibcon#enter sib2, iclass 36, count 0 2006.260.07:59:39.08#ibcon#flushed, iclass 36, count 0 2006.260.07:59:39.08#ibcon#about to write, iclass 36, count 0 2006.260.07:59:39.08#ibcon#wrote, iclass 36, count 0 2006.260.07:59:39.08#ibcon#about to read 3, iclass 36, count 0 2006.260.07:59:39.10#ibcon#read 3, iclass 36, count 0 2006.260.07:59:39.10#ibcon#about to read 4, iclass 36, count 0 2006.260.07:59:39.10#ibcon#read 4, iclass 36, count 0 2006.260.07:59:39.10#ibcon#about to read 5, iclass 36, count 0 2006.260.07:59:39.10#ibcon#read 5, iclass 36, count 0 2006.260.07:59:39.10#ibcon#about to read 6, iclass 36, count 0 2006.260.07:59:39.10#ibcon#read 6, iclass 36, count 0 2006.260.07:59:39.10#ibcon#end of sib2, iclass 36, count 0 2006.260.07:59:39.10#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:59:39.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:59:39.10#ibcon#[25=USB\r\n] 2006.260.07:59:39.10#ibcon#*before write, iclass 36, count 0 2006.260.07:59:39.10#ibcon#enter sib2, iclass 36, count 0 2006.260.07:59:39.10#ibcon#flushed, iclass 36, count 0 2006.260.07:59:39.10#ibcon#about to write, iclass 36, count 0 2006.260.07:59:39.10#ibcon#wrote, iclass 36, count 0 2006.260.07:59:39.10#ibcon#about to read 3, iclass 36, count 0 2006.260.07:59:39.13#ibcon#read 3, iclass 36, count 0 2006.260.07:59:39.13#ibcon#about to read 4, iclass 36, count 0 2006.260.07:59:39.13#ibcon#read 4, iclass 36, count 0 2006.260.07:59:39.13#ibcon#about to read 5, iclass 36, count 0 2006.260.07:59:39.13#ibcon#read 5, iclass 36, count 0 2006.260.07:59:39.13#ibcon#about to read 6, iclass 36, count 0 2006.260.07:59:39.13#ibcon#read 6, iclass 36, count 0 2006.260.07:59:39.13#ibcon#end of sib2, iclass 36, count 0 2006.260.07:59:39.13#ibcon#*after write, iclass 36, count 0 2006.260.07:59:39.13#ibcon#*before return 0, iclass 36, count 0 2006.260.07:59:39.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:39.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:39.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:59:39.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:59:39.13$vc4f8/valo=2,572.99 2006.260.07:59:39.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:59:39.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:59:39.13#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:39.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:39.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:39.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:39.13#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:59:39.13#ibcon#first serial, iclass 38, count 0 2006.260.07:59:39.13#ibcon#enter sib2, iclass 38, count 0 2006.260.07:59:39.13#ibcon#flushed, iclass 38, count 0 2006.260.07:59:39.13#ibcon#about to write, iclass 38, count 0 2006.260.07:59:39.13#ibcon#wrote, iclass 38, count 0 2006.260.07:59:39.13#ibcon#about to read 3, iclass 38, count 0 2006.260.07:59:39.15#ibcon#read 3, iclass 38, count 0 2006.260.07:59:39.15#ibcon#about to read 4, iclass 38, count 0 2006.260.07:59:39.15#ibcon#read 4, iclass 38, count 0 2006.260.07:59:39.15#ibcon#about to read 5, iclass 38, count 0 2006.260.07:59:39.15#ibcon#read 5, iclass 38, count 0 2006.260.07:59:39.15#ibcon#about to read 6, iclass 38, count 0 2006.260.07:59:39.15#ibcon#read 6, iclass 38, count 0 2006.260.07:59:39.15#ibcon#end of sib2, iclass 38, count 0 2006.260.07:59:39.15#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:59:39.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:59:39.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.07:59:39.15#ibcon#*before write, iclass 38, count 0 2006.260.07:59:39.15#ibcon#enter sib2, iclass 38, count 0 2006.260.07:59:39.15#ibcon#flushed, iclass 38, count 0 2006.260.07:59:39.15#ibcon#about to write, iclass 38, count 0 2006.260.07:59:39.15#ibcon#wrote, iclass 38, count 0 2006.260.07:59:39.15#ibcon#about to read 3, iclass 38, count 0 2006.260.07:59:39.19#ibcon#read 3, iclass 38, count 0 2006.260.07:59:39.19#ibcon#about to read 4, iclass 38, count 0 2006.260.07:59:39.19#ibcon#read 4, iclass 38, count 0 2006.260.07:59:39.19#ibcon#about to read 5, iclass 38, count 0 2006.260.07:59:39.19#ibcon#read 5, iclass 38, count 0 2006.260.07:59:39.19#ibcon#about to read 6, iclass 38, count 0 2006.260.07:59:39.19#ibcon#read 6, iclass 38, count 0 2006.260.07:59:39.19#ibcon#end of sib2, iclass 38, count 0 2006.260.07:59:39.19#ibcon#*after write, iclass 38, count 0 2006.260.07:59:39.19#ibcon#*before return 0, iclass 38, count 0 2006.260.07:59:39.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:39.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:39.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:59:39.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:59:39.19$vc4f8/va=2,7 2006.260.07:59:39.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:59:39.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:59:39.19#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:39.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:39.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:39.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:39.25#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:59:39.25#ibcon#first serial, iclass 40, count 2 2006.260.07:59:39.25#ibcon#enter sib2, iclass 40, count 2 2006.260.07:59:39.25#ibcon#flushed, iclass 40, count 2 2006.260.07:59:39.25#ibcon#about to write, iclass 40, count 2 2006.260.07:59:39.25#ibcon#wrote, iclass 40, count 2 2006.260.07:59:39.25#ibcon#about to read 3, iclass 40, count 2 2006.260.07:59:39.27#ibcon#read 3, iclass 40, count 2 2006.260.07:59:39.27#ibcon#about to read 4, iclass 40, count 2 2006.260.07:59:39.27#ibcon#read 4, iclass 40, count 2 2006.260.07:59:39.27#ibcon#about to read 5, iclass 40, count 2 2006.260.07:59:39.27#ibcon#read 5, iclass 40, count 2 2006.260.07:59:39.27#ibcon#about to read 6, iclass 40, count 2 2006.260.07:59:39.27#ibcon#read 6, iclass 40, count 2 2006.260.07:59:39.27#ibcon#end of sib2, iclass 40, count 2 2006.260.07:59:39.27#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:59:39.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:59:39.27#ibcon#[25=AT02-07\r\n] 2006.260.07:59:39.27#ibcon#*before write, iclass 40, count 2 2006.260.07:59:39.27#ibcon#enter sib2, iclass 40, count 2 2006.260.07:59:39.27#ibcon#flushed, iclass 40, count 2 2006.260.07:59:39.27#ibcon#about to write, iclass 40, count 2 2006.260.07:59:39.27#ibcon#wrote, iclass 40, count 2 2006.260.07:59:39.27#ibcon#about to read 3, iclass 40, count 2 2006.260.07:59:39.30#ibcon#read 3, iclass 40, count 2 2006.260.07:59:39.30#ibcon#about to read 4, iclass 40, count 2 2006.260.07:59:39.30#ibcon#read 4, iclass 40, count 2 2006.260.07:59:39.30#ibcon#about to read 5, iclass 40, count 2 2006.260.07:59:39.30#ibcon#read 5, iclass 40, count 2 2006.260.07:59:39.30#ibcon#about to read 6, iclass 40, count 2 2006.260.07:59:39.30#ibcon#read 6, iclass 40, count 2 2006.260.07:59:39.30#ibcon#end of sib2, iclass 40, count 2 2006.260.07:59:39.30#ibcon#*after write, iclass 40, count 2 2006.260.07:59:39.30#ibcon#*before return 0, iclass 40, count 2 2006.260.07:59:39.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:39.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:39.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:59:39.30#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:39.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:39.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:39.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:39.42#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:59:39.42#ibcon#first serial, iclass 40, count 0 2006.260.07:59:39.42#ibcon#enter sib2, iclass 40, count 0 2006.260.07:59:39.42#ibcon#flushed, iclass 40, count 0 2006.260.07:59:39.42#ibcon#about to write, iclass 40, count 0 2006.260.07:59:39.42#ibcon#wrote, iclass 40, count 0 2006.260.07:59:39.42#ibcon#about to read 3, iclass 40, count 0 2006.260.07:59:39.44#ibcon#read 3, iclass 40, count 0 2006.260.07:59:39.44#ibcon#about to read 4, iclass 40, count 0 2006.260.07:59:39.44#ibcon#read 4, iclass 40, count 0 2006.260.07:59:39.44#ibcon#about to read 5, iclass 40, count 0 2006.260.07:59:39.44#ibcon#read 5, iclass 40, count 0 2006.260.07:59:39.44#ibcon#about to read 6, iclass 40, count 0 2006.260.07:59:39.44#ibcon#read 6, iclass 40, count 0 2006.260.07:59:39.44#ibcon#end of sib2, iclass 40, count 0 2006.260.07:59:39.44#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:59:39.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:59:39.44#ibcon#[25=USB\r\n] 2006.260.07:59:39.44#ibcon#*before write, iclass 40, count 0 2006.260.07:59:39.44#ibcon#enter sib2, iclass 40, count 0 2006.260.07:59:39.44#ibcon#flushed, iclass 40, count 0 2006.260.07:59:39.44#ibcon#about to write, iclass 40, count 0 2006.260.07:59:39.44#ibcon#wrote, iclass 40, count 0 2006.260.07:59:39.44#ibcon#about to read 3, iclass 40, count 0 2006.260.07:59:39.47#ibcon#read 3, iclass 40, count 0 2006.260.07:59:39.47#ibcon#about to read 4, iclass 40, count 0 2006.260.07:59:39.47#ibcon#read 4, iclass 40, count 0 2006.260.07:59:39.47#ibcon#about to read 5, iclass 40, count 0 2006.260.07:59:39.47#ibcon#read 5, iclass 40, count 0 2006.260.07:59:39.47#ibcon#about to read 6, iclass 40, count 0 2006.260.07:59:39.47#ibcon#read 6, iclass 40, count 0 2006.260.07:59:39.47#ibcon#end of sib2, iclass 40, count 0 2006.260.07:59:39.47#ibcon#*after write, iclass 40, count 0 2006.260.07:59:39.47#ibcon#*before return 0, iclass 40, count 0 2006.260.07:59:39.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:39.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:39.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:59:39.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:59:39.47$vc4f8/valo=3,672.99 2006.260.07:59:39.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:59:39.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:59:39.47#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:39.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:39.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:39.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:39.47#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:59:39.47#ibcon#first serial, iclass 4, count 0 2006.260.07:59:39.47#ibcon#enter sib2, iclass 4, count 0 2006.260.07:59:39.47#ibcon#flushed, iclass 4, count 0 2006.260.07:59:39.47#ibcon#about to write, iclass 4, count 0 2006.260.07:59:39.47#ibcon#wrote, iclass 4, count 0 2006.260.07:59:39.47#ibcon#about to read 3, iclass 4, count 0 2006.260.07:59:39.49#ibcon#read 3, iclass 4, count 0 2006.260.07:59:39.49#ibcon#about to read 4, iclass 4, count 0 2006.260.07:59:39.49#ibcon#read 4, iclass 4, count 0 2006.260.07:59:39.49#ibcon#about to read 5, iclass 4, count 0 2006.260.07:59:39.49#ibcon#read 5, iclass 4, count 0 2006.260.07:59:39.49#ibcon#about to read 6, iclass 4, count 0 2006.260.07:59:39.49#ibcon#read 6, iclass 4, count 0 2006.260.07:59:39.49#ibcon#end of sib2, iclass 4, count 0 2006.260.07:59:39.49#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:59:39.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:59:39.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.07:59:39.49#ibcon#*before write, iclass 4, count 0 2006.260.07:59:39.49#ibcon#enter sib2, iclass 4, count 0 2006.260.07:59:39.49#ibcon#flushed, iclass 4, count 0 2006.260.07:59:39.49#ibcon#about to write, iclass 4, count 0 2006.260.07:59:39.49#ibcon#wrote, iclass 4, count 0 2006.260.07:59:39.49#ibcon#about to read 3, iclass 4, count 0 2006.260.07:59:39.53#ibcon#read 3, iclass 4, count 0 2006.260.07:59:39.53#ibcon#about to read 4, iclass 4, count 0 2006.260.07:59:39.53#ibcon#read 4, iclass 4, count 0 2006.260.07:59:39.53#ibcon#about to read 5, iclass 4, count 0 2006.260.07:59:39.53#ibcon#read 5, iclass 4, count 0 2006.260.07:59:39.53#ibcon#about to read 6, iclass 4, count 0 2006.260.07:59:39.53#ibcon#read 6, iclass 4, count 0 2006.260.07:59:39.53#ibcon#end of sib2, iclass 4, count 0 2006.260.07:59:39.53#ibcon#*after write, iclass 4, count 0 2006.260.07:59:39.53#ibcon#*before return 0, iclass 4, count 0 2006.260.07:59:39.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:39.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:39.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:59:39.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:59:39.53$vc4f8/va=3,8 2006.260.07:59:39.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:59:39.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:59:39.53#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:39.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:39.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:39.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:39.59#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:59:39.59#ibcon#first serial, iclass 6, count 2 2006.260.07:59:39.59#ibcon#enter sib2, iclass 6, count 2 2006.260.07:59:39.59#ibcon#flushed, iclass 6, count 2 2006.260.07:59:39.59#ibcon#about to write, iclass 6, count 2 2006.260.07:59:39.59#ibcon#wrote, iclass 6, count 2 2006.260.07:59:39.59#ibcon#about to read 3, iclass 6, count 2 2006.260.07:59:39.62#ibcon#read 3, iclass 6, count 2 2006.260.07:59:39.62#ibcon#about to read 4, iclass 6, count 2 2006.260.07:59:39.62#ibcon#read 4, iclass 6, count 2 2006.260.07:59:39.62#ibcon#about to read 5, iclass 6, count 2 2006.260.07:59:39.62#ibcon#read 5, iclass 6, count 2 2006.260.07:59:39.62#ibcon#about to read 6, iclass 6, count 2 2006.260.07:59:39.62#ibcon#read 6, iclass 6, count 2 2006.260.07:59:39.62#ibcon#end of sib2, iclass 6, count 2 2006.260.07:59:39.62#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:59:39.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:59:39.62#ibcon#[25=AT03-08\r\n] 2006.260.07:59:39.62#ibcon#*before write, iclass 6, count 2 2006.260.07:59:39.62#ibcon#enter sib2, iclass 6, count 2 2006.260.07:59:39.62#ibcon#flushed, iclass 6, count 2 2006.260.07:59:39.62#ibcon#about to write, iclass 6, count 2 2006.260.07:59:39.62#ibcon#wrote, iclass 6, count 2 2006.260.07:59:39.62#ibcon#about to read 3, iclass 6, count 2 2006.260.07:59:39.65#ibcon#read 3, iclass 6, count 2 2006.260.07:59:39.65#ibcon#about to read 4, iclass 6, count 2 2006.260.07:59:39.65#ibcon#read 4, iclass 6, count 2 2006.260.07:59:39.65#ibcon#about to read 5, iclass 6, count 2 2006.260.07:59:39.65#ibcon#read 5, iclass 6, count 2 2006.260.07:59:39.65#ibcon#about to read 6, iclass 6, count 2 2006.260.07:59:39.65#ibcon#read 6, iclass 6, count 2 2006.260.07:59:39.65#ibcon#end of sib2, iclass 6, count 2 2006.260.07:59:39.65#ibcon#*after write, iclass 6, count 2 2006.260.07:59:39.65#ibcon#*before return 0, iclass 6, count 2 2006.260.07:59:39.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:39.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:39.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:59:39.65#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:39.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:39.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:39.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:39.77#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:59:39.77#ibcon#first serial, iclass 6, count 0 2006.260.07:59:39.77#ibcon#enter sib2, iclass 6, count 0 2006.260.07:59:39.77#ibcon#flushed, iclass 6, count 0 2006.260.07:59:39.77#ibcon#about to write, iclass 6, count 0 2006.260.07:59:39.77#ibcon#wrote, iclass 6, count 0 2006.260.07:59:39.77#ibcon#about to read 3, iclass 6, count 0 2006.260.07:59:39.79#ibcon#read 3, iclass 6, count 0 2006.260.07:59:39.79#ibcon#about to read 4, iclass 6, count 0 2006.260.07:59:39.79#ibcon#read 4, iclass 6, count 0 2006.260.07:59:39.79#ibcon#about to read 5, iclass 6, count 0 2006.260.07:59:39.79#ibcon#read 5, iclass 6, count 0 2006.260.07:59:39.79#ibcon#about to read 6, iclass 6, count 0 2006.260.07:59:39.79#ibcon#read 6, iclass 6, count 0 2006.260.07:59:39.79#ibcon#end of sib2, iclass 6, count 0 2006.260.07:59:39.79#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:59:39.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:59:39.79#ibcon#[25=USB\r\n] 2006.260.07:59:39.79#ibcon#*before write, iclass 6, count 0 2006.260.07:59:39.79#ibcon#enter sib2, iclass 6, count 0 2006.260.07:59:39.79#ibcon#flushed, iclass 6, count 0 2006.260.07:59:39.79#ibcon#about to write, iclass 6, count 0 2006.260.07:59:39.79#ibcon#wrote, iclass 6, count 0 2006.260.07:59:39.79#ibcon#about to read 3, iclass 6, count 0 2006.260.07:59:39.82#ibcon#read 3, iclass 6, count 0 2006.260.07:59:39.82#ibcon#about to read 4, iclass 6, count 0 2006.260.07:59:39.82#ibcon#read 4, iclass 6, count 0 2006.260.07:59:39.82#ibcon#about to read 5, iclass 6, count 0 2006.260.07:59:39.82#ibcon#read 5, iclass 6, count 0 2006.260.07:59:39.82#ibcon#about to read 6, iclass 6, count 0 2006.260.07:59:39.82#ibcon#read 6, iclass 6, count 0 2006.260.07:59:39.82#ibcon#end of sib2, iclass 6, count 0 2006.260.07:59:39.82#ibcon#*after write, iclass 6, count 0 2006.260.07:59:39.82#ibcon#*before return 0, iclass 6, count 0 2006.260.07:59:39.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:39.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:39.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:59:39.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:59:39.82$vc4f8/valo=4,832.99 2006.260.07:59:39.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:59:39.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:59:39.82#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:39.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:39.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:39.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:39.82#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:59:39.82#ibcon#first serial, iclass 10, count 0 2006.260.07:59:39.82#ibcon#enter sib2, iclass 10, count 0 2006.260.07:59:39.82#ibcon#flushed, iclass 10, count 0 2006.260.07:59:39.82#ibcon#about to write, iclass 10, count 0 2006.260.07:59:39.82#ibcon#wrote, iclass 10, count 0 2006.260.07:59:39.82#ibcon#about to read 3, iclass 10, count 0 2006.260.07:59:39.84#ibcon#read 3, iclass 10, count 0 2006.260.07:59:39.84#ibcon#about to read 4, iclass 10, count 0 2006.260.07:59:39.84#ibcon#read 4, iclass 10, count 0 2006.260.07:59:39.84#ibcon#about to read 5, iclass 10, count 0 2006.260.07:59:39.84#ibcon#read 5, iclass 10, count 0 2006.260.07:59:39.84#ibcon#about to read 6, iclass 10, count 0 2006.260.07:59:39.84#ibcon#read 6, iclass 10, count 0 2006.260.07:59:39.84#ibcon#end of sib2, iclass 10, count 0 2006.260.07:59:39.84#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:59:39.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:59:39.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.07:59:39.84#ibcon#*before write, iclass 10, count 0 2006.260.07:59:39.84#ibcon#enter sib2, iclass 10, count 0 2006.260.07:59:39.84#ibcon#flushed, iclass 10, count 0 2006.260.07:59:39.84#ibcon#about to write, iclass 10, count 0 2006.260.07:59:39.84#ibcon#wrote, iclass 10, count 0 2006.260.07:59:39.84#ibcon#about to read 3, iclass 10, count 0 2006.260.07:59:39.88#ibcon#read 3, iclass 10, count 0 2006.260.07:59:39.88#ibcon#about to read 4, iclass 10, count 0 2006.260.07:59:39.88#ibcon#read 4, iclass 10, count 0 2006.260.07:59:39.88#ibcon#about to read 5, iclass 10, count 0 2006.260.07:59:39.88#ibcon#read 5, iclass 10, count 0 2006.260.07:59:39.88#ibcon#about to read 6, iclass 10, count 0 2006.260.07:59:39.88#ibcon#read 6, iclass 10, count 0 2006.260.07:59:39.88#ibcon#end of sib2, iclass 10, count 0 2006.260.07:59:39.88#ibcon#*after write, iclass 10, count 0 2006.260.07:59:39.88#ibcon#*before return 0, iclass 10, count 0 2006.260.07:59:39.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:39.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:39.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:59:39.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:59:39.88$vc4f8/va=4,7 2006.260.07:59:39.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:59:39.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:59:39.88#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:39.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:39.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:39.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:39.94#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:59:39.94#ibcon#first serial, iclass 12, count 2 2006.260.07:59:39.94#ibcon#enter sib2, iclass 12, count 2 2006.260.07:59:39.94#ibcon#flushed, iclass 12, count 2 2006.260.07:59:39.94#ibcon#about to write, iclass 12, count 2 2006.260.07:59:39.94#ibcon#wrote, iclass 12, count 2 2006.260.07:59:39.94#ibcon#about to read 3, iclass 12, count 2 2006.260.07:59:39.96#ibcon#read 3, iclass 12, count 2 2006.260.07:59:39.96#ibcon#about to read 4, iclass 12, count 2 2006.260.07:59:39.96#ibcon#read 4, iclass 12, count 2 2006.260.07:59:39.96#ibcon#about to read 5, iclass 12, count 2 2006.260.07:59:39.96#ibcon#read 5, iclass 12, count 2 2006.260.07:59:39.96#ibcon#about to read 6, iclass 12, count 2 2006.260.07:59:39.96#ibcon#read 6, iclass 12, count 2 2006.260.07:59:39.96#ibcon#end of sib2, iclass 12, count 2 2006.260.07:59:39.96#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:59:39.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:59:39.96#ibcon#[25=AT04-07\r\n] 2006.260.07:59:39.96#ibcon#*before write, iclass 12, count 2 2006.260.07:59:39.96#ibcon#enter sib2, iclass 12, count 2 2006.260.07:59:39.96#ibcon#flushed, iclass 12, count 2 2006.260.07:59:39.96#ibcon#about to write, iclass 12, count 2 2006.260.07:59:39.96#ibcon#wrote, iclass 12, count 2 2006.260.07:59:39.96#ibcon#about to read 3, iclass 12, count 2 2006.260.07:59:39.99#ibcon#read 3, iclass 12, count 2 2006.260.07:59:39.99#ibcon#about to read 4, iclass 12, count 2 2006.260.07:59:39.99#ibcon#read 4, iclass 12, count 2 2006.260.07:59:39.99#ibcon#about to read 5, iclass 12, count 2 2006.260.07:59:39.99#ibcon#read 5, iclass 12, count 2 2006.260.07:59:39.99#ibcon#about to read 6, iclass 12, count 2 2006.260.07:59:39.99#ibcon#read 6, iclass 12, count 2 2006.260.07:59:39.99#ibcon#end of sib2, iclass 12, count 2 2006.260.07:59:39.99#ibcon#*after write, iclass 12, count 2 2006.260.07:59:39.99#ibcon#*before return 0, iclass 12, count 2 2006.260.07:59:39.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:39.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:39.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:59:39.99#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:39.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:40.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:40.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:40.11#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:59:40.11#ibcon#first serial, iclass 12, count 0 2006.260.07:59:40.11#ibcon#enter sib2, iclass 12, count 0 2006.260.07:59:40.11#ibcon#flushed, iclass 12, count 0 2006.260.07:59:40.11#ibcon#about to write, iclass 12, count 0 2006.260.07:59:40.11#ibcon#wrote, iclass 12, count 0 2006.260.07:59:40.11#ibcon#about to read 3, iclass 12, count 0 2006.260.07:59:40.13#ibcon#read 3, iclass 12, count 0 2006.260.07:59:40.13#ibcon#about to read 4, iclass 12, count 0 2006.260.07:59:40.13#ibcon#read 4, iclass 12, count 0 2006.260.07:59:40.13#ibcon#about to read 5, iclass 12, count 0 2006.260.07:59:40.13#ibcon#read 5, iclass 12, count 0 2006.260.07:59:40.13#ibcon#about to read 6, iclass 12, count 0 2006.260.07:59:40.13#ibcon#read 6, iclass 12, count 0 2006.260.07:59:40.13#ibcon#end of sib2, iclass 12, count 0 2006.260.07:59:40.13#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:59:40.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:59:40.13#ibcon#[25=USB\r\n] 2006.260.07:59:40.13#ibcon#*before write, iclass 12, count 0 2006.260.07:59:40.13#ibcon#enter sib2, iclass 12, count 0 2006.260.07:59:40.13#ibcon#flushed, iclass 12, count 0 2006.260.07:59:40.13#ibcon#about to write, iclass 12, count 0 2006.260.07:59:40.13#ibcon#wrote, iclass 12, count 0 2006.260.07:59:40.13#ibcon#about to read 3, iclass 12, count 0 2006.260.07:59:40.16#ibcon#read 3, iclass 12, count 0 2006.260.07:59:40.16#ibcon#about to read 4, iclass 12, count 0 2006.260.07:59:40.16#ibcon#read 4, iclass 12, count 0 2006.260.07:59:40.16#ibcon#about to read 5, iclass 12, count 0 2006.260.07:59:40.16#ibcon#read 5, iclass 12, count 0 2006.260.07:59:40.16#ibcon#about to read 6, iclass 12, count 0 2006.260.07:59:40.16#ibcon#read 6, iclass 12, count 0 2006.260.07:59:40.16#ibcon#end of sib2, iclass 12, count 0 2006.260.07:59:40.16#ibcon#*after write, iclass 12, count 0 2006.260.07:59:40.16#ibcon#*before return 0, iclass 12, count 0 2006.260.07:59:40.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:40.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:40.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:59:40.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:59:40.16$vc4f8/valo=5,652.99 2006.260.07:59:40.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:59:40.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:59:40.16#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:40.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:40.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:40.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:40.16#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:59:40.16#ibcon#first serial, iclass 14, count 0 2006.260.07:59:40.16#ibcon#enter sib2, iclass 14, count 0 2006.260.07:59:40.16#ibcon#flushed, iclass 14, count 0 2006.260.07:59:40.16#ibcon#about to write, iclass 14, count 0 2006.260.07:59:40.16#ibcon#wrote, iclass 14, count 0 2006.260.07:59:40.16#ibcon#about to read 3, iclass 14, count 0 2006.260.07:59:40.18#ibcon#read 3, iclass 14, count 0 2006.260.07:59:40.18#ibcon#about to read 4, iclass 14, count 0 2006.260.07:59:40.18#ibcon#read 4, iclass 14, count 0 2006.260.07:59:40.18#ibcon#about to read 5, iclass 14, count 0 2006.260.07:59:40.18#ibcon#read 5, iclass 14, count 0 2006.260.07:59:40.18#ibcon#about to read 6, iclass 14, count 0 2006.260.07:59:40.18#ibcon#read 6, iclass 14, count 0 2006.260.07:59:40.18#ibcon#end of sib2, iclass 14, count 0 2006.260.07:59:40.18#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:59:40.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:59:40.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.07:59:40.18#ibcon#*before write, iclass 14, count 0 2006.260.07:59:40.18#ibcon#enter sib2, iclass 14, count 0 2006.260.07:59:40.18#ibcon#flushed, iclass 14, count 0 2006.260.07:59:40.18#ibcon#about to write, iclass 14, count 0 2006.260.07:59:40.18#ibcon#wrote, iclass 14, count 0 2006.260.07:59:40.18#ibcon#about to read 3, iclass 14, count 0 2006.260.07:59:40.22#ibcon#read 3, iclass 14, count 0 2006.260.07:59:40.22#ibcon#about to read 4, iclass 14, count 0 2006.260.07:59:40.22#ibcon#read 4, iclass 14, count 0 2006.260.07:59:40.22#ibcon#about to read 5, iclass 14, count 0 2006.260.07:59:40.22#ibcon#read 5, iclass 14, count 0 2006.260.07:59:40.22#ibcon#about to read 6, iclass 14, count 0 2006.260.07:59:40.22#ibcon#read 6, iclass 14, count 0 2006.260.07:59:40.22#ibcon#end of sib2, iclass 14, count 0 2006.260.07:59:40.22#ibcon#*after write, iclass 14, count 0 2006.260.07:59:40.22#ibcon#*before return 0, iclass 14, count 0 2006.260.07:59:40.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:40.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:40.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:59:40.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:59:40.22$vc4f8/va=5,7 2006.260.07:59:40.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:59:40.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:59:40.22#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:40.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:40.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:40.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:40.28#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:59:40.28#ibcon#first serial, iclass 16, count 2 2006.260.07:59:40.28#ibcon#enter sib2, iclass 16, count 2 2006.260.07:59:40.28#ibcon#flushed, iclass 16, count 2 2006.260.07:59:40.28#ibcon#about to write, iclass 16, count 2 2006.260.07:59:40.28#ibcon#wrote, iclass 16, count 2 2006.260.07:59:40.28#ibcon#about to read 3, iclass 16, count 2 2006.260.07:59:40.30#ibcon#read 3, iclass 16, count 2 2006.260.07:59:40.30#ibcon#about to read 4, iclass 16, count 2 2006.260.07:59:40.30#ibcon#read 4, iclass 16, count 2 2006.260.07:59:40.30#ibcon#about to read 5, iclass 16, count 2 2006.260.07:59:40.30#ibcon#read 5, iclass 16, count 2 2006.260.07:59:40.30#ibcon#about to read 6, iclass 16, count 2 2006.260.07:59:40.30#ibcon#read 6, iclass 16, count 2 2006.260.07:59:40.30#ibcon#end of sib2, iclass 16, count 2 2006.260.07:59:40.30#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:59:40.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:59:40.30#ibcon#[25=AT05-07\r\n] 2006.260.07:59:40.30#ibcon#*before write, iclass 16, count 2 2006.260.07:59:40.30#ibcon#enter sib2, iclass 16, count 2 2006.260.07:59:40.30#ibcon#flushed, iclass 16, count 2 2006.260.07:59:40.30#ibcon#about to write, iclass 16, count 2 2006.260.07:59:40.30#ibcon#wrote, iclass 16, count 2 2006.260.07:59:40.30#ibcon#about to read 3, iclass 16, count 2 2006.260.07:59:40.33#ibcon#read 3, iclass 16, count 2 2006.260.07:59:40.33#ibcon#about to read 4, iclass 16, count 2 2006.260.07:59:40.33#ibcon#read 4, iclass 16, count 2 2006.260.07:59:40.33#ibcon#about to read 5, iclass 16, count 2 2006.260.07:59:40.33#ibcon#read 5, iclass 16, count 2 2006.260.07:59:40.33#ibcon#about to read 6, iclass 16, count 2 2006.260.07:59:40.33#ibcon#read 6, iclass 16, count 2 2006.260.07:59:40.33#ibcon#end of sib2, iclass 16, count 2 2006.260.07:59:40.33#ibcon#*after write, iclass 16, count 2 2006.260.07:59:40.33#ibcon#*before return 0, iclass 16, count 2 2006.260.07:59:40.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:40.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:40.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:59:40.33#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:40.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:40.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:40.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:40.45#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:59:40.45#ibcon#first serial, iclass 16, count 0 2006.260.07:59:40.45#ibcon#enter sib2, iclass 16, count 0 2006.260.07:59:40.45#ibcon#flushed, iclass 16, count 0 2006.260.07:59:40.45#ibcon#about to write, iclass 16, count 0 2006.260.07:59:40.45#ibcon#wrote, iclass 16, count 0 2006.260.07:59:40.45#ibcon#about to read 3, iclass 16, count 0 2006.260.07:59:40.47#ibcon#read 3, iclass 16, count 0 2006.260.07:59:40.47#ibcon#about to read 4, iclass 16, count 0 2006.260.07:59:40.47#ibcon#read 4, iclass 16, count 0 2006.260.07:59:40.47#ibcon#about to read 5, iclass 16, count 0 2006.260.07:59:40.47#ibcon#read 5, iclass 16, count 0 2006.260.07:59:40.47#ibcon#about to read 6, iclass 16, count 0 2006.260.07:59:40.47#ibcon#read 6, iclass 16, count 0 2006.260.07:59:40.47#ibcon#end of sib2, iclass 16, count 0 2006.260.07:59:40.47#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:59:40.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:59:40.47#ibcon#[25=USB\r\n] 2006.260.07:59:40.47#ibcon#*before write, iclass 16, count 0 2006.260.07:59:40.47#ibcon#enter sib2, iclass 16, count 0 2006.260.07:59:40.47#ibcon#flushed, iclass 16, count 0 2006.260.07:59:40.47#ibcon#about to write, iclass 16, count 0 2006.260.07:59:40.47#ibcon#wrote, iclass 16, count 0 2006.260.07:59:40.47#ibcon#about to read 3, iclass 16, count 0 2006.260.07:59:40.50#ibcon#read 3, iclass 16, count 0 2006.260.07:59:40.50#ibcon#about to read 4, iclass 16, count 0 2006.260.07:59:40.50#ibcon#read 4, iclass 16, count 0 2006.260.07:59:40.50#ibcon#about to read 5, iclass 16, count 0 2006.260.07:59:40.50#ibcon#read 5, iclass 16, count 0 2006.260.07:59:40.50#ibcon#about to read 6, iclass 16, count 0 2006.260.07:59:40.50#ibcon#read 6, iclass 16, count 0 2006.260.07:59:40.50#ibcon#end of sib2, iclass 16, count 0 2006.260.07:59:40.50#ibcon#*after write, iclass 16, count 0 2006.260.07:59:40.50#ibcon#*before return 0, iclass 16, count 0 2006.260.07:59:40.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:40.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:40.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:59:40.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:59:40.50$vc4f8/valo=6,772.99 2006.260.07:59:40.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:59:40.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:59:40.50#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:40.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:40.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:40.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:40.50#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:59:40.50#ibcon#first serial, iclass 18, count 0 2006.260.07:59:40.50#ibcon#enter sib2, iclass 18, count 0 2006.260.07:59:40.50#ibcon#flushed, iclass 18, count 0 2006.260.07:59:40.50#ibcon#about to write, iclass 18, count 0 2006.260.07:59:40.50#ibcon#wrote, iclass 18, count 0 2006.260.07:59:40.50#ibcon#about to read 3, iclass 18, count 0 2006.260.07:59:40.52#ibcon#read 3, iclass 18, count 0 2006.260.07:59:40.52#ibcon#about to read 4, iclass 18, count 0 2006.260.07:59:40.52#ibcon#read 4, iclass 18, count 0 2006.260.07:59:40.52#ibcon#about to read 5, iclass 18, count 0 2006.260.07:59:40.52#ibcon#read 5, iclass 18, count 0 2006.260.07:59:40.52#ibcon#about to read 6, iclass 18, count 0 2006.260.07:59:40.52#ibcon#read 6, iclass 18, count 0 2006.260.07:59:40.52#ibcon#end of sib2, iclass 18, count 0 2006.260.07:59:40.52#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:59:40.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:59:40.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.07:59:40.52#ibcon#*before write, iclass 18, count 0 2006.260.07:59:40.52#ibcon#enter sib2, iclass 18, count 0 2006.260.07:59:40.52#ibcon#flushed, iclass 18, count 0 2006.260.07:59:40.52#ibcon#about to write, iclass 18, count 0 2006.260.07:59:40.52#ibcon#wrote, iclass 18, count 0 2006.260.07:59:40.52#ibcon#about to read 3, iclass 18, count 0 2006.260.07:59:40.56#ibcon#read 3, iclass 18, count 0 2006.260.07:59:40.56#ibcon#about to read 4, iclass 18, count 0 2006.260.07:59:40.56#ibcon#read 4, iclass 18, count 0 2006.260.07:59:40.56#ibcon#about to read 5, iclass 18, count 0 2006.260.07:59:40.56#ibcon#read 5, iclass 18, count 0 2006.260.07:59:40.56#ibcon#about to read 6, iclass 18, count 0 2006.260.07:59:40.56#ibcon#read 6, iclass 18, count 0 2006.260.07:59:40.56#ibcon#end of sib2, iclass 18, count 0 2006.260.07:59:40.56#ibcon#*after write, iclass 18, count 0 2006.260.07:59:40.56#ibcon#*before return 0, iclass 18, count 0 2006.260.07:59:40.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:40.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:40.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:59:40.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:59:40.56$vc4f8/va=6,6 2006.260.07:59:40.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:59:40.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:59:40.56#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:40.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:40.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:40.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:40.62#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:59:40.62#ibcon#first serial, iclass 20, count 2 2006.260.07:59:40.62#ibcon#enter sib2, iclass 20, count 2 2006.260.07:59:40.62#ibcon#flushed, iclass 20, count 2 2006.260.07:59:40.62#ibcon#about to write, iclass 20, count 2 2006.260.07:59:40.62#ibcon#wrote, iclass 20, count 2 2006.260.07:59:40.62#ibcon#about to read 3, iclass 20, count 2 2006.260.07:59:40.64#ibcon#read 3, iclass 20, count 2 2006.260.07:59:40.64#ibcon#about to read 4, iclass 20, count 2 2006.260.07:59:40.64#ibcon#read 4, iclass 20, count 2 2006.260.07:59:40.64#ibcon#about to read 5, iclass 20, count 2 2006.260.07:59:40.64#ibcon#read 5, iclass 20, count 2 2006.260.07:59:40.64#ibcon#about to read 6, iclass 20, count 2 2006.260.07:59:40.64#ibcon#read 6, iclass 20, count 2 2006.260.07:59:40.64#ibcon#end of sib2, iclass 20, count 2 2006.260.07:59:40.64#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:59:40.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:59:40.64#ibcon#[25=AT06-06\r\n] 2006.260.07:59:40.64#ibcon#*before write, iclass 20, count 2 2006.260.07:59:40.64#ibcon#enter sib2, iclass 20, count 2 2006.260.07:59:40.64#ibcon#flushed, iclass 20, count 2 2006.260.07:59:40.64#ibcon#about to write, iclass 20, count 2 2006.260.07:59:40.64#ibcon#wrote, iclass 20, count 2 2006.260.07:59:40.64#ibcon#about to read 3, iclass 20, count 2 2006.260.07:59:40.67#ibcon#read 3, iclass 20, count 2 2006.260.07:59:40.67#ibcon#about to read 4, iclass 20, count 2 2006.260.07:59:40.67#ibcon#read 4, iclass 20, count 2 2006.260.07:59:40.67#ibcon#about to read 5, iclass 20, count 2 2006.260.07:59:40.67#ibcon#read 5, iclass 20, count 2 2006.260.07:59:40.67#ibcon#about to read 6, iclass 20, count 2 2006.260.07:59:40.67#ibcon#read 6, iclass 20, count 2 2006.260.07:59:40.67#ibcon#end of sib2, iclass 20, count 2 2006.260.07:59:40.67#ibcon#*after write, iclass 20, count 2 2006.260.07:59:40.67#ibcon#*before return 0, iclass 20, count 2 2006.260.07:59:40.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:40.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:40.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:59:40.67#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:40.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:40.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:40.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:40.79#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:59:40.79#ibcon#first serial, iclass 20, count 0 2006.260.07:59:40.79#ibcon#enter sib2, iclass 20, count 0 2006.260.07:59:40.79#ibcon#flushed, iclass 20, count 0 2006.260.07:59:40.79#ibcon#about to write, iclass 20, count 0 2006.260.07:59:40.79#ibcon#wrote, iclass 20, count 0 2006.260.07:59:40.79#ibcon#about to read 3, iclass 20, count 0 2006.260.07:59:40.81#ibcon#read 3, iclass 20, count 0 2006.260.07:59:40.81#ibcon#about to read 4, iclass 20, count 0 2006.260.07:59:40.81#ibcon#read 4, iclass 20, count 0 2006.260.07:59:40.81#ibcon#about to read 5, iclass 20, count 0 2006.260.07:59:40.81#ibcon#read 5, iclass 20, count 0 2006.260.07:59:40.81#ibcon#about to read 6, iclass 20, count 0 2006.260.07:59:40.81#ibcon#read 6, iclass 20, count 0 2006.260.07:59:40.81#ibcon#end of sib2, iclass 20, count 0 2006.260.07:59:40.81#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:59:40.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:59:40.81#ibcon#[25=USB\r\n] 2006.260.07:59:40.81#ibcon#*before write, iclass 20, count 0 2006.260.07:59:40.81#ibcon#enter sib2, iclass 20, count 0 2006.260.07:59:40.81#ibcon#flushed, iclass 20, count 0 2006.260.07:59:40.81#ibcon#about to write, iclass 20, count 0 2006.260.07:59:40.81#ibcon#wrote, iclass 20, count 0 2006.260.07:59:40.81#ibcon#about to read 3, iclass 20, count 0 2006.260.07:59:40.84#ibcon#read 3, iclass 20, count 0 2006.260.07:59:40.84#ibcon#about to read 4, iclass 20, count 0 2006.260.07:59:40.84#ibcon#read 4, iclass 20, count 0 2006.260.07:59:40.84#ibcon#about to read 5, iclass 20, count 0 2006.260.07:59:40.84#ibcon#read 5, iclass 20, count 0 2006.260.07:59:40.84#ibcon#about to read 6, iclass 20, count 0 2006.260.07:59:40.84#ibcon#read 6, iclass 20, count 0 2006.260.07:59:40.84#ibcon#end of sib2, iclass 20, count 0 2006.260.07:59:40.84#ibcon#*after write, iclass 20, count 0 2006.260.07:59:40.84#ibcon#*before return 0, iclass 20, count 0 2006.260.07:59:40.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:40.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:40.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:59:40.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:59:40.84$vc4f8/valo=7,832.99 2006.260.07:59:40.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:59:40.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:59:40.84#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:40.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:40.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:40.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:40.84#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:59:40.84#ibcon#first serial, iclass 22, count 0 2006.260.07:59:40.84#ibcon#enter sib2, iclass 22, count 0 2006.260.07:59:40.84#ibcon#flushed, iclass 22, count 0 2006.260.07:59:40.84#ibcon#about to write, iclass 22, count 0 2006.260.07:59:40.84#ibcon#wrote, iclass 22, count 0 2006.260.07:59:40.84#ibcon#about to read 3, iclass 22, count 0 2006.260.07:59:40.86#ibcon#read 3, iclass 22, count 0 2006.260.07:59:40.86#ibcon#about to read 4, iclass 22, count 0 2006.260.07:59:40.86#ibcon#read 4, iclass 22, count 0 2006.260.07:59:40.86#ibcon#about to read 5, iclass 22, count 0 2006.260.07:59:40.86#ibcon#read 5, iclass 22, count 0 2006.260.07:59:40.86#ibcon#about to read 6, iclass 22, count 0 2006.260.07:59:40.86#ibcon#read 6, iclass 22, count 0 2006.260.07:59:40.86#ibcon#end of sib2, iclass 22, count 0 2006.260.07:59:40.86#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:59:40.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:59:40.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.07:59:40.86#ibcon#*before write, iclass 22, count 0 2006.260.07:59:40.86#ibcon#enter sib2, iclass 22, count 0 2006.260.07:59:40.86#ibcon#flushed, iclass 22, count 0 2006.260.07:59:40.86#ibcon#about to write, iclass 22, count 0 2006.260.07:59:40.86#ibcon#wrote, iclass 22, count 0 2006.260.07:59:40.86#ibcon#about to read 3, iclass 22, count 0 2006.260.07:59:40.90#ibcon#read 3, iclass 22, count 0 2006.260.07:59:40.90#ibcon#about to read 4, iclass 22, count 0 2006.260.07:59:40.90#ibcon#read 4, iclass 22, count 0 2006.260.07:59:40.90#ibcon#about to read 5, iclass 22, count 0 2006.260.07:59:40.90#ibcon#read 5, iclass 22, count 0 2006.260.07:59:40.90#ibcon#about to read 6, iclass 22, count 0 2006.260.07:59:40.90#ibcon#read 6, iclass 22, count 0 2006.260.07:59:40.90#ibcon#end of sib2, iclass 22, count 0 2006.260.07:59:40.90#ibcon#*after write, iclass 22, count 0 2006.260.07:59:40.90#ibcon#*before return 0, iclass 22, count 0 2006.260.07:59:40.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:40.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:40.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:59:40.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:59:40.90$vc4f8/va=7,6 2006.260.07:59:40.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.07:59:40.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.07:59:40.90#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:40.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:40.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:40.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:40.96#ibcon#enter wrdev, iclass 24, count 2 2006.260.07:59:40.96#ibcon#first serial, iclass 24, count 2 2006.260.07:59:40.96#ibcon#enter sib2, iclass 24, count 2 2006.260.07:59:40.96#ibcon#flushed, iclass 24, count 2 2006.260.07:59:40.96#ibcon#about to write, iclass 24, count 2 2006.260.07:59:40.96#ibcon#wrote, iclass 24, count 2 2006.260.07:59:40.96#ibcon#about to read 3, iclass 24, count 2 2006.260.07:59:40.98#ibcon#read 3, iclass 24, count 2 2006.260.07:59:40.98#ibcon#about to read 4, iclass 24, count 2 2006.260.07:59:40.98#ibcon#read 4, iclass 24, count 2 2006.260.07:59:40.98#ibcon#about to read 5, iclass 24, count 2 2006.260.07:59:40.98#ibcon#read 5, iclass 24, count 2 2006.260.07:59:40.98#ibcon#about to read 6, iclass 24, count 2 2006.260.07:59:40.98#ibcon#read 6, iclass 24, count 2 2006.260.07:59:40.98#ibcon#end of sib2, iclass 24, count 2 2006.260.07:59:40.98#ibcon#*mode == 0, iclass 24, count 2 2006.260.07:59:40.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.07:59:40.98#ibcon#[25=AT07-06\r\n] 2006.260.07:59:40.98#ibcon#*before write, iclass 24, count 2 2006.260.07:59:40.98#ibcon#enter sib2, iclass 24, count 2 2006.260.07:59:40.98#ibcon#flushed, iclass 24, count 2 2006.260.07:59:40.98#ibcon#about to write, iclass 24, count 2 2006.260.07:59:40.98#ibcon#wrote, iclass 24, count 2 2006.260.07:59:40.98#ibcon#about to read 3, iclass 24, count 2 2006.260.07:59:41.01#ibcon#read 3, iclass 24, count 2 2006.260.07:59:41.01#ibcon#about to read 4, iclass 24, count 2 2006.260.07:59:41.01#ibcon#read 4, iclass 24, count 2 2006.260.07:59:41.01#ibcon#about to read 5, iclass 24, count 2 2006.260.07:59:41.01#ibcon#read 5, iclass 24, count 2 2006.260.07:59:41.01#ibcon#about to read 6, iclass 24, count 2 2006.260.07:59:41.01#ibcon#read 6, iclass 24, count 2 2006.260.07:59:41.01#ibcon#end of sib2, iclass 24, count 2 2006.260.07:59:41.01#ibcon#*after write, iclass 24, count 2 2006.260.07:59:41.01#ibcon#*before return 0, iclass 24, count 2 2006.260.07:59:41.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:41.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:41.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.07:59:41.01#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:41.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:59:41.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:59:41.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:59:41.13#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:59:41.13#ibcon#first serial, iclass 24, count 0 2006.260.07:59:41.13#ibcon#enter sib2, iclass 24, count 0 2006.260.07:59:41.13#ibcon#flushed, iclass 24, count 0 2006.260.07:59:41.13#ibcon#about to write, iclass 24, count 0 2006.260.07:59:41.13#ibcon#wrote, iclass 24, count 0 2006.260.07:59:41.13#ibcon#about to read 3, iclass 24, count 0 2006.260.07:59:41.15#ibcon#read 3, iclass 24, count 0 2006.260.07:59:41.15#ibcon#about to read 4, iclass 24, count 0 2006.260.07:59:41.15#ibcon#read 4, iclass 24, count 0 2006.260.07:59:41.15#ibcon#about to read 5, iclass 24, count 0 2006.260.07:59:41.15#ibcon#read 5, iclass 24, count 0 2006.260.07:59:41.15#ibcon#about to read 6, iclass 24, count 0 2006.260.07:59:41.15#ibcon#read 6, iclass 24, count 0 2006.260.07:59:41.15#ibcon#end of sib2, iclass 24, count 0 2006.260.07:59:41.15#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:59:41.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:59:41.15#ibcon#[25=USB\r\n] 2006.260.07:59:41.15#ibcon#*before write, iclass 24, count 0 2006.260.07:59:41.15#ibcon#enter sib2, iclass 24, count 0 2006.260.07:59:41.15#ibcon#flushed, iclass 24, count 0 2006.260.07:59:41.15#ibcon#about to write, iclass 24, count 0 2006.260.07:59:41.15#ibcon#wrote, iclass 24, count 0 2006.260.07:59:41.15#ibcon#about to read 3, iclass 24, count 0 2006.260.07:59:41.18#ibcon#read 3, iclass 24, count 0 2006.260.07:59:41.18#ibcon#about to read 4, iclass 24, count 0 2006.260.07:59:41.18#ibcon#read 4, iclass 24, count 0 2006.260.07:59:41.18#ibcon#about to read 5, iclass 24, count 0 2006.260.07:59:41.18#ibcon#read 5, iclass 24, count 0 2006.260.07:59:41.18#ibcon#about to read 6, iclass 24, count 0 2006.260.07:59:41.18#ibcon#read 6, iclass 24, count 0 2006.260.07:59:41.18#ibcon#end of sib2, iclass 24, count 0 2006.260.07:59:41.18#ibcon#*after write, iclass 24, count 0 2006.260.07:59:41.18#ibcon#*before return 0, iclass 24, count 0 2006.260.07:59:41.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:59:41.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.07:59:41.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:59:41.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:59:41.18$vc4f8/valo=8,852.99 2006.260.07:59:41.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.07:59:41.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.07:59:41.18#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:41.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:59:41.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:59:41.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:59:41.18#ibcon#enter wrdev, iclass 26, count 0 2006.260.07:59:41.18#ibcon#first serial, iclass 26, count 0 2006.260.07:59:41.18#ibcon#enter sib2, iclass 26, count 0 2006.260.07:59:41.18#ibcon#flushed, iclass 26, count 0 2006.260.07:59:41.18#ibcon#about to write, iclass 26, count 0 2006.260.07:59:41.18#ibcon#wrote, iclass 26, count 0 2006.260.07:59:41.18#ibcon#about to read 3, iclass 26, count 0 2006.260.07:59:41.20#ibcon#read 3, iclass 26, count 0 2006.260.07:59:41.20#ibcon#about to read 4, iclass 26, count 0 2006.260.07:59:41.20#ibcon#read 4, iclass 26, count 0 2006.260.07:59:41.20#ibcon#about to read 5, iclass 26, count 0 2006.260.07:59:41.20#ibcon#read 5, iclass 26, count 0 2006.260.07:59:41.20#ibcon#about to read 6, iclass 26, count 0 2006.260.07:59:41.20#ibcon#read 6, iclass 26, count 0 2006.260.07:59:41.20#ibcon#end of sib2, iclass 26, count 0 2006.260.07:59:41.20#ibcon#*mode == 0, iclass 26, count 0 2006.260.07:59:41.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.07:59:41.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.07:59:41.20#ibcon#*before write, iclass 26, count 0 2006.260.07:59:41.20#ibcon#enter sib2, iclass 26, count 0 2006.260.07:59:41.20#ibcon#flushed, iclass 26, count 0 2006.260.07:59:41.20#ibcon#about to write, iclass 26, count 0 2006.260.07:59:41.20#ibcon#wrote, iclass 26, count 0 2006.260.07:59:41.20#ibcon#about to read 3, iclass 26, count 0 2006.260.07:59:41.24#ibcon#read 3, iclass 26, count 0 2006.260.07:59:41.24#ibcon#about to read 4, iclass 26, count 0 2006.260.07:59:41.24#ibcon#read 4, iclass 26, count 0 2006.260.07:59:41.24#ibcon#about to read 5, iclass 26, count 0 2006.260.07:59:41.24#ibcon#read 5, iclass 26, count 0 2006.260.07:59:41.24#ibcon#about to read 6, iclass 26, count 0 2006.260.07:59:41.24#ibcon#read 6, iclass 26, count 0 2006.260.07:59:41.24#ibcon#end of sib2, iclass 26, count 0 2006.260.07:59:41.24#ibcon#*after write, iclass 26, count 0 2006.260.07:59:41.24#ibcon#*before return 0, iclass 26, count 0 2006.260.07:59:41.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:59:41.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.07:59:41.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.07:59:41.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.07:59:41.24$vc4f8/va=8,6 2006.260.07:59:41.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.07:59:41.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.07:59:41.24#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:41.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:59:41.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:59:41.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:59:41.30#ibcon#enter wrdev, iclass 28, count 2 2006.260.07:59:41.30#ibcon#first serial, iclass 28, count 2 2006.260.07:59:41.30#ibcon#enter sib2, iclass 28, count 2 2006.260.07:59:41.30#ibcon#flushed, iclass 28, count 2 2006.260.07:59:41.30#ibcon#about to write, iclass 28, count 2 2006.260.07:59:41.30#ibcon#wrote, iclass 28, count 2 2006.260.07:59:41.30#ibcon#about to read 3, iclass 28, count 2 2006.260.07:59:41.31#abcon#<5=/03 2.9 6.0 22.88 881010.4\r\n> 2006.260.07:59:41.32#ibcon#read 3, iclass 28, count 2 2006.260.07:59:41.32#ibcon#about to read 4, iclass 28, count 2 2006.260.07:59:41.32#ibcon#read 4, iclass 28, count 2 2006.260.07:59:41.32#ibcon#about to read 5, iclass 28, count 2 2006.260.07:59:41.32#ibcon#read 5, iclass 28, count 2 2006.260.07:59:41.32#ibcon#about to read 6, iclass 28, count 2 2006.260.07:59:41.32#ibcon#read 6, iclass 28, count 2 2006.260.07:59:41.32#ibcon#end of sib2, iclass 28, count 2 2006.260.07:59:41.32#ibcon#*mode == 0, iclass 28, count 2 2006.260.07:59:41.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.07:59:41.32#ibcon#[25=AT08-06\r\n] 2006.260.07:59:41.32#ibcon#*before write, iclass 28, count 2 2006.260.07:59:41.32#ibcon#enter sib2, iclass 28, count 2 2006.260.07:59:41.32#ibcon#flushed, iclass 28, count 2 2006.260.07:59:41.32#ibcon#about to write, iclass 28, count 2 2006.260.07:59:41.32#ibcon#wrote, iclass 28, count 2 2006.260.07:59:41.32#ibcon#about to read 3, iclass 28, count 2 2006.260.07:59:41.33#abcon#{5=INTERFACE CLEAR} 2006.260.07:59:41.35#ibcon#read 3, iclass 28, count 2 2006.260.07:59:41.35#ibcon#about to read 4, iclass 28, count 2 2006.260.07:59:41.35#ibcon#read 4, iclass 28, count 2 2006.260.07:59:41.35#ibcon#about to read 5, iclass 28, count 2 2006.260.07:59:41.35#ibcon#read 5, iclass 28, count 2 2006.260.07:59:41.35#ibcon#about to read 6, iclass 28, count 2 2006.260.07:59:41.35#ibcon#read 6, iclass 28, count 2 2006.260.07:59:41.35#ibcon#end of sib2, iclass 28, count 2 2006.260.07:59:41.35#ibcon#*after write, iclass 28, count 2 2006.260.07:59:41.35#ibcon#*before return 0, iclass 28, count 2 2006.260.07:59:41.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:59:41.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.07:59:41.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.07:59:41.35#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:41.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:59:41.39#abcon#[5=S1D000X0/0*\r\n] 2006.260.07:59:41.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:59:41.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:59:41.47#ibcon#enter wrdev, iclass 28, count 0 2006.260.07:59:41.47#ibcon#first serial, iclass 28, count 0 2006.260.07:59:41.47#ibcon#enter sib2, iclass 28, count 0 2006.260.07:59:41.47#ibcon#flushed, iclass 28, count 0 2006.260.07:59:41.47#ibcon#about to write, iclass 28, count 0 2006.260.07:59:41.47#ibcon#wrote, iclass 28, count 0 2006.260.07:59:41.47#ibcon#about to read 3, iclass 28, count 0 2006.260.07:59:41.49#ibcon#read 3, iclass 28, count 0 2006.260.07:59:41.49#ibcon#about to read 4, iclass 28, count 0 2006.260.07:59:41.49#ibcon#read 4, iclass 28, count 0 2006.260.07:59:41.49#ibcon#about to read 5, iclass 28, count 0 2006.260.07:59:41.49#ibcon#read 5, iclass 28, count 0 2006.260.07:59:41.49#ibcon#about to read 6, iclass 28, count 0 2006.260.07:59:41.49#ibcon#read 6, iclass 28, count 0 2006.260.07:59:41.49#ibcon#end of sib2, iclass 28, count 0 2006.260.07:59:41.49#ibcon#*mode == 0, iclass 28, count 0 2006.260.07:59:41.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.07:59:41.49#ibcon#[25=USB\r\n] 2006.260.07:59:41.49#ibcon#*before write, iclass 28, count 0 2006.260.07:59:41.49#ibcon#enter sib2, iclass 28, count 0 2006.260.07:59:41.49#ibcon#flushed, iclass 28, count 0 2006.260.07:59:41.49#ibcon#about to write, iclass 28, count 0 2006.260.07:59:41.49#ibcon#wrote, iclass 28, count 0 2006.260.07:59:41.49#ibcon#about to read 3, iclass 28, count 0 2006.260.07:59:41.52#ibcon#read 3, iclass 28, count 0 2006.260.07:59:41.52#ibcon#about to read 4, iclass 28, count 0 2006.260.07:59:41.52#ibcon#read 4, iclass 28, count 0 2006.260.07:59:41.52#ibcon#about to read 5, iclass 28, count 0 2006.260.07:59:41.52#ibcon#read 5, iclass 28, count 0 2006.260.07:59:41.52#ibcon#about to read 6, iclass 28, count 0 2006.260.07:59:41.52#ibcon#read 6, iclass 28, count 0 2006.260.07:59:41.52#ibcon#end of sib2, iclass 28, count 0 2006.260.07:59:41.52#ibcon#*after write, iclass 28, count 0 2006.260.07:59:41.52#ibcon#*before return 0, iclass 28, count 0 2006.260.07:59:41.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:59:41.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.07:59:41.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.07:59:41.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.07:59:41.52$vc4f8/vblo=1,632.99 2006.260.07:59:41.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.07:59:41.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.07:59:41.52#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:41.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:41.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:41.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:41.52#ibcon#enter wrdev, iclass 34, count 0 2006.260.07:59:41.52#ibcon#first serial, iclass 34, count 0 2006.260.07:59:41.52#ibcon#enter sib2, iclass 34, count 0 2006.260.07:59:41.52#ibcon#flushed, iclass 34, count 0 2006.260.07:59:41.52#ibcon#about to write, iclass 34, count 0 2006.260.07:59:41.52#ibcon#wrote, iclass 34, count 0 2006.260.07:59:41.52#ibcon#about to read 3, iclass 34, count 0 2006.260.07:59:41.54#ibcon#read 3, iclass 34, count 0 2006.260.07:59:41.54#ibcon#about to read 4, iclass 34, count 0 2006.260.07:59:41.54#ibcon#read 4, iclass 34, count 0 2006.260.07:59:41.54#ibcon#about to read 5, iclass 34, count 0 2006.260.07:59:41.54#ibcon#read 5, iclass 34, count 0 2006.260.07:59:41.54#ibcon#about to read 6, iclass 34, count 0 2006.260.07:59:41.54#ibcon#read 6, iclass 34, count 0 2006.260.07:59:41.54#ibcon#end of sib2, iclass 34, count 0 2006.260.07:59:41.54#ibcon#*mode == 0, iclass 34, count 0 2006.260.07:59:41.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.07:59:41.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.07:59:41.54#ibcon#*before write, iclass 34, count 0 2006.260.07:59:41.54#ibcon#enter sib2, iclass 34, count 0 2006.260.07:59:41.54#ibcon#flushed, iclass 34, count 0 2006.260.07:59:41.54#ibcon#about to write, iclass 34, count 0 2006.260.07:59:41.54#ibcon#wrote, iclass 34, count 0 2006.260.07:59:41.54#ibcon#about to read 3, iclass 34, count 0 2006.260.07:59:41.58#ibcon#read 3, iclass 34, count 0 2006.260.07:59:41.58#ibcon#about to read 4, iclass 34, count 0 2006.260.07:59:41.58#ibcon#read 4, iclass 34, count 0 2006.260.07:59:41.58#ibcon#about to read 5, iclass 34, count 0 2006.260.07:59:41.58#ibcon#read 5, iclass 34, count 0 2006.260.07:59:41.58#ibcon#about to read 6, iclass 34, count 0 2006.260.07:59:41.58#ibcon#read 6, iclass 34, count 0 2006.260.07:59:41.58#ibcon#end of sib2, iclass 34, count 0 2006.260.07:59:41.58#ibcon#*after write, iclass 34, count 0 2006.260.07:59:41.58#ibcon#*before return 0, iclass 34, count 0 2006.260.07:59:41.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:41.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.07:59:41.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.07:59:41.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.07:59:41.58$vc4f8/vb=1,4 2006.260.07:59:41.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.07:59:41.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.07:59:41.58#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:41.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:41.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:41.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:41.58#ibcon#enter wrdev, iclass 36, count 2 2006.260.07:59:41.58#ibcon#first serial, iclass 36, count 2 2006.260.07:59:41.58#ibcon#enter sib2, iclass 36, count 2 2006.260.07:59:41.58#ibcon#flushed, iclass 36, count 2 2006.260.07:59:41.58#ibcon#about to write, iclass 36, count 2 2006.260.07:59:41.58#ibcon#wrote, iclass 36, count 2 2006.260.07:59:41.58#ibcon#about to read 3, iclass 36, count 2 2006.260.07:59:41.60#ibcon#read 3, iclass 36, count 2 2006.260.07:59:41.60#ibcon#about to read 4, iclass 36, count 2 2006.260.07:59:41.60#ibcon#read 4, iclass 36, count 2 2006.260.07:59:41.60#ibcon#about to read 5, iclass 36, count 2 2006.260.07:59:41.60#ibcon#read 5, iclass 36, count 2 2006.260.07:59:41.60#ibcon#about to read 6, iclass 36, count 2 2006.260.07:59:41.60#ibcon#read 6, iclass 36, count 2 2006.260.07:59:41.60#ibcon#end of sib2, iclass 36, count 2 2006.260.07:59:41.60#ibcon#*mode == 0, iclass 36, count 2 2006.260.07:59:41.60#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.07:59:41.60#ibcon#[27=AT01-04\r\n] 2006.260.07:59:41.60#ibcon#*before write, iclass 36, count 2 2006.260.07:59:41.60#ibcon#enter sib2, iclass 36, count 2 2006.260.07:59:41.60#ibcon#flushed, iclass 36, count 2 2006.260.07:59:41.60#ibcon#about to write, iclass 36, count 2 2006.260.07:59:41.60#ibcon#wrote, iclass 36, count 2 2006.260.07:59:41.60#ibcon#about to read 3, iclass 36, count 2 2006.260.07:59:41.63#ibcon#read 3, iclass 36, count 2 2006.260.07:59:41.63#ibcon#about to read 4, iclass 36, count 2 2006.260.07:59:41.63#ibcon#read 4, iclass 36, count 2 2006.260.07:59:41.63#ibcon#about to read 5, iclass 36, count 2 2006.260.07:59:41.63#ibcon#read 5, iclass 36, count 2 2006.260.07:59:41.63#ibcon#about to read 6, iclass 36, count 2 2006.260.07:59:41.63#ibcon#read 6, iclass 36, count 2 2006.260.07:59:41.63#ibcon#end of sib2, iclass 36, count 2 2006.260.07:59:41.63#ibcon#*after write, iclass 36, count 2 2006.260.07:59:41.63#ibcon#*before return 0, iclass 36, count 2 2006.260.07:59:41.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:41.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.07:59:41.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.07:59:41.63#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:41.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:41.75#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:41.75#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:41.75#ibcon#enter wrdev, iclass 36, count 0 2006.260.07:59:41.75#ibcon#first serial, iclass 36, count 0 2006.260.07:59:41.75#ibcon#enter sib2, iclass 36, count 0 2006.260.07:59:41.75#ibcon#flushed, iclass 36, count 0 2006.260.07:59:41.75#ibcon#about to write, iclass 36, count 0 2006.260.07:59:41.75#ibcon#wrote, iclass 36, count 0 2006.260.07:59:41.75#ibcon#about to read 3, iclass 36, count 0 2006.260.07:59:41.77#ibcon#read 3, iclass 36, count 0 2006.260.07:59:41.77#ibcon#about to read 4, iclass 36, count 0 2006.260.07:59:41.77#ibcon#read 4, iclass 36, count 0 2006.260.07:59:41.77#ibcon#about to read 5, iclass 36, count 0 2006.260.07:59:41.77#ibcon#read 5, iclass 36, count 0 2006.260.07:59:41.77#ibcon#about to read 6, iclass 36, count 0 2006.260.07:59:41.77#ibcon#read 6, iclass 36, count 0 2006.260.07:59:41.77#ibcon#end of sib2, iclass 36, count 0 2006.260.07:59:41.77#ibcon#*mode == 0, iclass 36, count 0 2006.260.07:59:41.77#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.07:59:41.77#ibcon#[27=USB\r\n] 2006.260.07:59:41.77#ibcon#*before write, iclass 36, count 0 2006.260.07:59:41.77#ibcon#enter sib2, iclass 36, count 0 2006.260.07:59:41.77#ibcon#flushed, iclass 36, count 0 2006.260.07:59:41.77#ibcon#about to write, iclass 36, count 0 2006.260.07:59:41.77#ibcon#wrote, iclass 36, count 0 2006.260.07:59:41.77#ibcon#about to read 3, iclass 36, count 0 2006.260.07:59:41.80#ibcon#read 3, iclass 36, count 0 2006.260.07:59:41.80#ibcon#about to read 4, iclass 36, count 0 2006.260.07:59:41.80#ibcon#read 4, iclass 36, count 0 2006.260.07:59:41.80#ibcon#about to read 5, iclass 36, count 0 2006.260.07:59:41.80#ibcon#read 5, iclass 36, count 0 2006.260.07:59:41.80#ibcon#about to read 6, iclass 36, count 0 2006.260.07:59:41.80#ibcon#read 6, iclass 36, count 0 2006.260.07:59:41.80#ibcon#end of sib2, iclass 36, count 0 2006.260.07:59:41.80#ibcon#*after write, iclass 36, count 0 2006.260.07:59:41.80#ibcon#*before return 0, iclass 36, count 0 2006.260.07:59:41.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:41.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.07:59:41.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.07:59:41.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.07:59:41.80$vc4f8/vblo=2,640.99 2006.260.07:59:41.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.07:59:41.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.07:59:41.80#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:41.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:41.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:41.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:41.80#ibcon#enter wrdev, iclass 38, count 0 2006.260.07:59:41.80#ibcon#first serial, iclass 38, count 0 2006.260.07:59:41.80#ibcon#enter sib2, iclass 38, count 0 2006.260.07:59:41.80#ibcon#flushed, iclass 38, count 0 2006.260.07:59:41.80#ibcon#about to write, iclass 38, count 0 2006.260.07:59:41.80#ibcon#wrote, iclass 38, count 0 2006.260.07:59:41.80#ibcon#about to read 3, iclass 38, count 0 2006.260.07:59:41.82#ibcon#read 3, iclass 38, count 0 2006.260.07:59:41.82#ibcon#about to read 4, iclass 38, count 0 2006.260.07:59:41.82#ibcon#read 4, iclass 38, count 0 2006.260.07:59:41.82#ibcon#about to read 5, iclass 38, count 0 2006.260.07:59:41.82#ibcon#read 5, iclass 38, count 0 2006.260.07:59:41.82#ibcon#about to read 6, iclass 38, count 0 2006.260.07:59:41.82#ibcon#read 6, iclass 38, count 0 2006.260.07:59:41.82#ibcon#end of sib2, iclass 38, count 0 2006.260.07:59:41.82#ibcon#*mode == 0, iclass 38, count 0 2006.260.07:59:41.82#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.07:59:41.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.07:59:41.82#ibcon#*before write, iclass 38, count 0 2006.260.07:59:41.82#ibcon#enter sib2, iclass 38, count 0 2006.260.07:59:41.82#ibcon#flushed, iclass 38, count 0 2006.260.07:59:41.82#ibcon#about to write, iclass 38, count 0 2006.260.07:59:41.82#ibcon#wrote, iclass 38, count 0 2006.260.07:59:41.82#ibcon#about to read 3, iclass 38, count 0 2006.260.07:59:41.86#ibcon#read 3, iclass 38, count 0 2006.260.07:59:41.86#ibcon#about to read 4, iclass 38, count 0 2006.260.07:59:41.86#ibcon#read 4, iclass 38, count 0 2006.260.07:59:41.86#ibcon#about to read 5, iclass 38, count 0 2006.260.07:59:41.86#ibcon#read 5, iclass 38, count 0 2006.260.07:59:41.86#ibcon#about to read 6, iclass 38, count 0 2006.260.07:59:41.86#ibcon#read 6, iclass 38, count 0 2006.260.07:59:41.86#ibcon#end of sib2, iclass 38, count 0 2006.260.07:59:41.86#ibcon#*after write, iclass 38, count 0 2006.260.07:59:41.86#ibcon#*before return 0, iclass 38, count 0 2006.260.07:59:41.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:41.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.07:59:41.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.07:59:41.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.07:59:41.86$vc4f8/vb=2,5 2006.260.07:59:41.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.07:59:41.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.07:59:41.86#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:41.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:41.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:41.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:41.92#ibcon#enter wrdev, iclass 40, count 2 2006.260.07:59:41.92#ibcon#first serial, iclass 40, count 2 2006.260.07:59:41.92#ibcon#enter sib2, iclass 40, count 2 2006.260.07:59:41.92#ibcon#flushed, iclass 40, count 2 2006.260.07:59:41.92#ibcon#about to write, iclass 40, count 2 2006.260.07:59:41.92#ibcon#wrote, iclass 40, count 2 2006.260.07:59:41.92#ibcon#about to read 3, iclass 40, count 2 2006.260.07:59:41.94#ibcon#read 3, iclass 40, count 2 2006.260.07:59:41.94#ibcon#about to read 4, iclass 40, count 2 2006.260.07:59:41.94#ibcon#read 4, iclass 40, count 2 2006.260.07:59:41.94#ibcon#about to read 5, iclass 40, count 2 2006.260.07:59:41.94#ibcon#read 5, iclass 40, count 2 2006.260.07:59:41.94#ibcon#about to read 6, iclass 40, count 2 2006.260.07:59:41.94#ibcon#read 6, iclass 40, count 2 2006.260.07:59:41.94#ibcon#end of sib2, iclass 40, count 2 2006.260.07:59:41.94#ibcon#*mode == 0, iclass 40, count 2 2006.260.07:59:41.94#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.07:59:41.94#ibcon#[27=AT02-05\r\n] 2006.260.07:59:41.94#ibcon#*before write, iclass 40, count 2 2006.260.07:59:41.94#ibcon#enter sib2, iclass 40, count 2 2006.260.07:59:41.94#ibcon#flushed, iclass 40, count 2 2006.260.07:59:41.94#ibcon#about to write, iclass 40, count 2 2006.260.07:59:41.94#ibcon#wrote, iclass 40, count 2 2006.260.07:59:41.94#ibcon#about to read 3, iclass 40, count 2 2006.260.07:59:41.97#ibcon#read 3, iclass 40, count 2 2006.260.07:59:41.97#ibcon#about to read 4, iclass 40, count 2 2006.260.07:59:41.97#ibcon#read 4, iclass 40, count 2 2006.260.07:59:41.97#ibcon#about to read 5, iclass 40, count 2 2006.260.07:59:41.97#ibcon#read 5, iclass 40, count 2 2006.260.07:59:41.97#ibcon#about to read 6, iclass 40, count 2 2006.260.07:59:41.97#ibcon#read 6, iclass 40, count 2 2006.260.07:59:41.97#ibcon#end of sib2, iclass 40, count 2 2006.260.07:59:41.97#ibcon#*after write, iclass 40, count 2 2006.260.07:59:41.97#ibcon#*before return 0, iclass 40, count 2 2006.260.07:59:41.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:41.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.07:59:41.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.07:59:41.97#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:41.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:42.09#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:42.09#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:42.09#ibcon#enter wrdev, iclass 40, count 0 2006.260.07:59:42.09#ibcon#first serial, iclass 40, count 0 2006.260.07:59:42.09#ibcon#enter sib2, iclass 40, count 0 2006.260.07:59:42.09#ibcon#flushed, iclass 40, count 0 2006.260.07:59:42.09#ibcon#about to write, iclass 40, count 0 2006.260.07:59:42.09#ibcon#wrote, iclass 40, count 0 2006.260.07:59:42.09#ibcon#about to read 3, iclass 40, count 0 2006.260.07:59:42.11#ibcon#read 3, iclass 40, count 0 2006.260.07:59:42.11#ibcon#about to read 4, iclass 40, count 0 2006.260.07:59:42.11#ibcon#read 4, iclass 40, count 0 2006.260.07:59:42.11#ibcon#about to read 5, iclass 40, count 0 2006.260.07:59:42.11#ibcon#read 5, iclass 40, count 0 2006.260.07:59:42.11#ibcon#about to read 6, iclass 40, count 0 2006.260.07:59:42.11#ibcon#read 6, iclass 40, count 0 2006.260.07:59:42.11#ibcon#end of sib2, iclass 40, count 0 2006.260.07:59:42.11#ibcon#*mode == 0, iclass 40, count 0 2006.260.07:59:42.11#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.07:59:42.11#ibcon#[27=USB\r\n] 2006.260.07:59:42.11#ibcon#*before write, iclass 40, count 0 2006.260.07:59:42.11#ibcon#enter sib2, iclass 40, count 0 2006.260.07:59:42.11#ibcon#flushed, iclass 40, count 0 2006.260.07:59:42.11#ibcon#about to write, iclass 40, count 0 2006.260.07:59:42.11#ibcon#wrote, iclass 40, count 0 2006.260.07:59:42.11#ibcon#about to read 3, iclass 40, count 0 2006.260.07:59:42.14#ibcon#read 3, iclass 40, count 0 2006.260.07:59:42.14#ibcon#about to read 4, iclass 40, count 0 2006.260.07:59:42.14#ibcon#read 4, iclass 40, count 0 2006.260.07:59:42.14#ibcon#about to read 5, iclass 40, count 0 2006.260.07:59:42.14#ibcon#read 5, iclass 40, count 0 2006.260.07:59:42.14#ibcon#about to read 6, iclass 40, count 0 2006.260.07:59:42.14#ibcon#read 6, iclass 40, count 0 2006.260.07:59:42.14#ibcon#end of sib2, iclass 40, count 0 2006.260.07:59:42.14#ibcon#*after write, iclass 40, count 0 2006.260.07:59:42.14#ibcon#*before return 0, iclass 40, count 0 2006.260.07:59:42.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:42.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.07:59:42.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.07:59:42.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.07:59:42.14$vc4f8/vblo=3,656.99 2006.260.07:59:42.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.07:59:42.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.07:59:42.14#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:42.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:42.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:42.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:42.14#ibcon#enter wrdev, iclass 4, count 0 2006.260.07:59:42.14#ibcon#first serial, iclass 4, count 0 2006.260.07:59:42.14#ibcon#enter sib2, iclass 4, count 0 2006.260.07:59:42.14#ibcon#flushed, iclass 4, count 0 2006.260.07:59:42.14#ibcon#about to write, iclass 4, count 0 2006.260.07:59:42.14#ibcon#wrote, iclass 4, count 0 2006.260.07:59:42.14#ibcon#about to read 3, iclass 4, count 0 2006.260.07:59:42.16#ibcon#read 3, iclass 4, count 0 2006.260.07:59:42.16#ibcon#about to read 4, iclass 4, count 0 2006.260.07:59:42.16#ibcon#read 4, iclass 4, count 0 2006.260.07:59:42.16#ibcon#about to read 5, iclass 4, count 0 2006.260.07:59:42.16#ibcon#read 5, iclass 4, count 0 2006.260.07:59:42.16#ibcon#about to read 6, iclass 4, count 0 2006.260.07:59:42.16#ibcon#read 6, iclass 4, count 0 2006.260.07:59:42.16#ibcon#end of sib2, iclass 4, count 0 2006.260.07:59:42.16#ibcon#*mode == 0, iclass 4, count 0 2006.260.07:59:42.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.07:59:42.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.07:59:42.16#ibcon#*before write, iclass 4, count 0 2006.260.07:59:42.16#ibcon#enter sib2, iclass 4, count 0 2006.260.07:59:42.16#ibcon#flushed, iclass 4, count 0 2006.260.07:59:42.16#ibcon#about to write, iclass 4, count 0 2006.260.07:59:42.16#ibcon#wrote, iclass 4, count 0 2006.260.07:59:42.16#ibcon#about to read 3, iclass 4, count 0 2006.260.07:59:42.20#ibcon#read 3, iclass 4, count 0 2006.260.07:59:42.20#ibcon#about to read 4, iclass 4, count 0 2006.260.07:59:42.20#ibcon#read 4, iclass 4, count 0 2006.260.07:59:42.20#ibcon#about to read 5, iclass 4, count 0 2006.260.07:59:42.20#ibcon#read 5, iclass 4, count 0 2006.260.07:59:42.20#ibcon#about to read 6, iclass 4, count 0 2006.260.07:59:42.20#ibcon#read 6, iclass 4, count 0 2006.260.07:59:42.20#ibcon#end of sib2, iclass 4, count 0 2006.260.07:59:42.20#ibcon#*after write, iclass 4, count 0 2006.260.07:59:42.20#ibcon#*before return 0, iclass 4, count 0 2006.260.07:59:42.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:42.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.07:59:42.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.07:59:42.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.07:59:42.20$vc4f8/vb=3,4 2006.260.07:59:42.20#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.07:59:42.20#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.07:59:42.20#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:42.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:42.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:42.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:42.26#ibcon#enter wrdev, iclass 6, count 2 2006.260.07:59:42.26#ibcon#first serial, iclass 6, count 2 2006.260.07:59:42.26#ibcon#enter sib2, iclass 6, count 2 2006.260.07:59:42.26#ibcon#flushed, iclass 6, count 2 2006.260.07:59:42.26#ibcon#about to write, iclass 6, count 2 2006.260.07:59:42.26#ibcon#wrote, iclass 6, count 2 2006.260.07:59:42.26#ibcon#about to read 3, iclass 6, count 2 2006.260.07:59:42.28#ibcon#read 3, iclass 6, count 2 2006.260.07:59:42.28#ibcon#about to read 4, iclass 6, count 2 2006.260.07:59:42.28#ibcon#read 4, iclass 6, count 2 2006.260.07:59:42.28#ibcon#about to read 5, iclass 6, count 2 2006.260.07:59:42.28#ibcon#read 5, iclass 6, count 2 2006.260.07:59:42.28#ibcon#about to read 6, iclass 6, count 2 2006.260.07:59:42.28#ibcon#read 6, iclass 6, count 2 2006.260.07:59:42.28#ibcon#end of sib2, iclass 6, count 2 2006.260.07:59:42.28#ibcon#*mode == 0, iclass 6, count 2 2006.260.07:59:42.28#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.07:59:42.28#ibcon#[27=AT03-04\r\n] 2006.260.07:59:42.28#ibcon#*before write, iclass 6, count 2 2006.260.07:59:42.28#ibcon#enter sib2, iclass 6, count 2 2006.260.07:59:42.28#ibcon#flushed, iclass 6, count 2 2006.260.07:59:42.28#ibcon#about to write, iclass 6, count 2 2006.260.07:59:42.28#ibcon#wrote, iclass 6, count 2 2006.260.07:59:42.28#ibcon#about to read 3, iclass 6, count 2 2006.260.07:59:42.31#ibcon#read 3, iclass 6, count 2 2006.260.07:59:42.31#ibcon#about to read 4, iclass 6, count 2 2006.260.07:59:42.31#ibcon#read 4, iclass 6, count 2 2006.260.07:59:42.31#ibcon#about to read 5, iclass 6, count 2 2006.260.07:59:42.31#ibcon#read 5, iclass 6, count 2 2006.260.07:59:42.31#ibcon#about to read 6, iclass 6, count 2 2006.260.07:59:42.31#ibcon#read 6, iclass 6, count 2 2006.260.07:59:42.31#ibcon#end of sib2, iclass 6, count 2 2006.260.07:59:42.31#ibcon#*after write, iclass 6, count 2 2006.260.07:59:42.31#ibcon#*before return 0, iclass 6, count 2 2006.260.07:59:42.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:42.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.07:59:42.31#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.07:59:42.31#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:42.31#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:42.43#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:42.43#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:42.43#ibcon#enter wrdev, iclass 6, count 0 2006.260.07:59:42.43#ibcon#first serial, iclass 6, count 0 2006.260.07:59:42.43#ibcon#enter sib2, iclass 6, count 0 2006.260.07:59:42.43#ibcon#flushed, iclass 6, count 0 2006.260.07:59:42.43#ibcon#about to write, iclass 6, count 0 2006.260.07:59:42.43#ibcon#wrote, iclass 6, count 0 2006.260.07:59:42.43#ibcon#about to read 3, iclass 6, count 0 2006.260.07:59:42.45#ibcon#read 3, iclass 6, count 0 2006.260.07:59:42.45#ibcon#about to read 4, iclass 6, count 0 2006.260.07:59:42.45#ibcon#read 4, iclass 6, count 0 2006.260.07:59:42.45#ibcon#about to read 5, iclass 6, count 0 2006.260.07:59:42.45#ibcon#read 5, iclass 6, count 0 2006.260.07:59:42.45#ibcon#about to read 6, iclass 6, count 0 2006.260.07:59:42.45#ibcon#read 6, iclass 6, count 0 2006.260.07:59:42.45#ibcon#end of sib2, iclass 6, count 0 2006.260.07:59:42.45#ibcon#*mode == 0, iclass 6, count 0 2006.260.07:59:42.45#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.07:59:42.45#ibcon#[27=USB\r\n] 2006.260.07:59:42.45#ibcon#*before write, iclass 6, count 0 2006.260.07:59:42.45#ibcon#enter sib2, iclass 6, count 0 2006.260.07:59:42.45#ibcon#flushed, iclass 6, count 0 2006.260.07:59:42.45#ibcon#about to write, iclass 6, count 0 2006.260.07:59:42.45#ibcon#wrote, iclass 6, count 0 2006.260.07:59:42.45#ibcon#about to read 3, iclass 6, count 0 2006.260.07:59:42.48#ibcon#read 3, iclass 6, count 0 2006.260.07:59:42.48#ibcon#about to read 4, iclass 6, count 0 2006.260.07:59:42.48#ibcon#read 4, iclass 6, count 0 2006.260.07:59:42.48#ibcon#about to read 5, iclass 6, count 0 2006.260.07:59:42.48#ibcon#read 5, iclass 6, count 0 2006.260.07:59:42.48#ibcon#about to read 6, iclass 6, count 0 2006.260.07:59:42.48#ibcon#read 6, iclass 6, count 0 2006.260.07:59:42.48#ibcon#end of sib2, iclass 6, count 0 2006.260.07:59:42.48#ibcon#*after write, iclass 6, count 0 2006.260.07:59:42.48#ibcon#*before return 0, iclass 6, count 0 2006.260.07:59:42.48#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:42.48#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.07:59:42.48#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.07:59:42.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.07:59:42.48$vc4f8/vblo=4,712.99 2006.260.07:59:42.48#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.07:59:42.48#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.07:59:42.48#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:42.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:42.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:42.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:42.48#ibcon#enter wrdev, iclass 10, count 0 2006.260.07:59:42.48#ibcon#first serial, iclass 10, count 0 2006.260.07:59:42.48#ibcon#enter sib2, iclass 10, count 0 2006.260.07:59:42.48#ibcon#flushed, iclass 10, count 0 2006.260.07:59:42.48#ibcon#about to write, iclass 10, count 0 2006.260.07:59:42.48#ibcon#wrote, iclass 10, count 0 2006.260.07:59:42.48#ibcon#about to read 3, iclass 10, count 0 2006.260.07:59:42.50#ibcon#read 3, iclass 10, count 0 2006.260.07:59:42.50#ibcon#about to read 4, iclass 10, count 0 2006.260.07:59:42.50#ibcon#read 4, iclass 10, count 0 2006.260.07:59:42.50#ibcon#about to read 5, iclass 10, count 0 2006.260.07:59:42.50#ibcon#read 5, iclass 10, count 0 2006.260.07:59:42.50#ibcon#about to read 6, iclass 10, count 0 2006.260.07:59:42.50#ibcon#read 6, iclass 10, count 0 2006.260.07:59:42.50#ibcon#end of sib2, iclass 10, count 0 2006.260.07:59:42.50#ibcon#*mode == 0, iclass 10, count 0 2006.260.07:59:42.50#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.07:59:42.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.07:59:42.50#ibcon#*before write, iclass 10, count 0 2006.260.07:59:42.50#ibcon#enter sib2, iclass 10, count 0 2006.260.07:59:42.50#ibcon#flushed, iclass 10, count 0 2006.260.07:59:42.50#ibcon#about to write, iclass 10, count 0 2006.260.07:59:42.50#ibcon#wrote, iclass 10, count 0 2006.260.07:59:42.50#ibcon#about to read 3, iclass 10, count 0 2006.260.07:59:42.54#ibcon#read 3, iclass 10, count 0 2006.260.07:59:42.54#ibcon#about to read 4, iclass 10, count 0 2006.260.07:59:42.54#ibcon#read 4, iclass 10, count 0 2006.260.07:59:42.54#ibcon#about to read 5, iclass 10, count 0 2006.260.07:59:42.54#ibcon#read 5, iclass 10, count 0 2006.260.07:59:42.54#ibcon#about to read 6, iclass 10, count 0 2006.260.07:59:42.54#ibcon#read 6, iclass 10, count 0 2006.260.07:59:42.54#ibcon#end of sib2, iclass 10, count 0 2006.260.07:59:42.54#ibcon#*after write, iclass 10, count 0 2006.260.07:59:42.54#ibcon#*before return 0, iclass 10, count 0 2006.260.07:59:42.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:42.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.07:59:42.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.07:59:42.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.07:59:42.54$vc4f8/vb=4,5 2006.260.07:59:42.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.07:59:42.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.07:59:42.54#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:42.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:42.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:42.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:42.60#ibcon#enter wrdev, iclass 12, count 2 2006.260.07:59:42.60#ibcon#first serial, iclass 12, count 2 2006.260.07:59:42.60#ibcon#enter sib2, iclass 12, count 2 2006.260.07:59:42.60#ibcon#flushed, iclass 12, count 2 2006.260.07:59:42.60#ibcon#about to write, iclass 12, count 2 2006.260.07:59:42.60#ibcon#wrote, iclass 12, count 2 2006.260.07:59:42.60#ibcon#about to read 3, iclass 12, count 2 2006.260.07:59:42.62#ibcon#read 3, iclass 12, count 2 2006.260.07:59:42.62#ibcon#about to read 4, iclass 12, count 2 2006.260.07:59:42.62#ibcon#read 4, iclass 12, count 2 2006.260.07:59:42.62#ibcon#about to read 5, iclass 12, count 2 2006.260.07:59:42.62#ibcon#read 5, iclass 12, count 2 2006.260.07:59:42.62#ibcon#about to read 6, iclass 12, count 2 2006.260.07:59:42.62#ibcon#read 6, iclass 12, count 2 2006.260.07:59:42.62#ibcon#end of sib2, iclass 12, count 2 2006.260.07:59:42.62#ibcon#*mode == 0, iclass 12, count 2 2006.260.07:59:42.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.07:59:42.62#ibcon#[27=AT04-05\r\n] 2006.260.07:59:42.62#ibcon#*before write, iclass 12, count 2 2006.260.07:59:42.62#ibcon#enter sib2, iclass 12, count 2 2006.260.07:59:42.62#ibcon#flushed, iclass 12, count 2 2006.260.07:59:42.62#ibcon#about to write, iclass 12, count 2 2006.260.07:59:42.62#ibcon#wrote, iclass 12, count 2 2006.260.07:59:42.62#ibcon#about to read 3, iclass 12, count 2 2006.260.07:59:42.65#ibcon#read 3, iclass 12, count 2 2006.260.07:59:42.65#ibcon#about to read 4, iclass 12, count 2 2006.260.07:59:42.65#ibcon#read 4, iclass 12, count 2 2006.260.07:59:42.65#ibcon#about to read 5, iclass 12, count 2 2006.260.07:59:42.65#ibcon#read 5, iclass 12, count 2 2006.260.07:59:42.65#ibcon#about to read 6, iclass 12, count 2 2006.260.07:59:42.65#ibcon#read 6, iclass 12, count 2 2006.260.07:59:42.65#ibcon#end of sib2, iclass 12, count 2 2006.260.07:59:42.65#ibcon#*after write, iclass 12, count 2 2006.260.07:59:42.65#ibcon#*before return 0, iclass 12, count 2 2006.260.07:59:42.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:42.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.07:59:42.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.07:59:42.65#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:42.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:42.77#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:42.77#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:42.77#ibcon#enter wrdev, iclass 12, count 0 2006.260.07:59:42.77#ibcon#first serial, iclass 12, count 0 2006.260.07:59:42.77#ibcon#enter sib2, iclass 12, count 0 2006.260.07:59:42.77#ibcon#flushed, iclass 12, count 0 2006.260.07:59:42.77#ibcon#about to write, iclass 12, count 0 2006.260.07:59:42.77#ibcon#wrote, iclass 12, count 0 2006.260.07:59:42.77#ibcon#about to read 3, iclass 12, count 0 2006.260.07:59:42.79#ibcon#read 3, iclass 12, count 0 2006.260.07:59:42.79#ibcon#about to read 4, iclass 12, count 0 2006.260.07:59:42.79#ibcon#read 4, iclass 12, count 0 2006.260.07:59:42.79#ibcon#about to read 5, iclass 12, count 0 2006.260.07:59:42.79#ibcon#read 5, iclass 12, count 0 2006.260.07:59:42.79#ibcon#about to read 6, iclass 12, count 0 2006.260.07:59:42.79#ibcon#read 6, iclass 12, count 0 2006.260.07:59:42.79#ibcon#end of sib2, iclass 12, count 0 2006.260.07:59:42.79#ibcon#*mode == 0, iclass 12, count 0 2006.260.07:59:42.79#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.07:59:42.79#ibcon#[27=USB\r\n] 2006.260.07:59:42.79#ibcon#*before write, iclass 12, count 0 2006.260.07:59:42.79#ibcon#enter sib2, iclass 12, count 0 2006.260.07:59:42.79#ibcon#flushed, iclass 12, count 0 2006.260.07:59:42.79#ibcon#about to write, iclass 12, count 0 2006.260.07:59:42.79#ibcon#wrote, iclass 12, count 0 2006.260.07:59:42.79#ibcon#about to read 3, iclass 12, count 0 2006.260.07:59:42.82#ibcon#read 3, iclass 12, count 0 2006.260.07:59:42.82#ibcon#about to read 4, iclass 12, count 0 2006.260.07:59:42.82#ibcon#read 4, iclass 12, count 0 2006.260.07:59:42.82#ibcon#about to read 5, iclass 12, count 0 2006.260.07:59:42.82#ibcon#read 5, iclass 12, count 0 2006.260.07:59:42.82#ibcon#about to read 6, iclass 12, count 0 2006.260.07:59:42.82#ibcon#read 6, iclass 12, count 0 2006.260.07:59:42.82#ibcon#end of sib2, iclass 12, count 0 2006.260.07:59:42.82#ibcon#*after write, iclass 12, count 0 2006.260.07:59:42.82#ibcon#*before return 0, iclass 12, count 0 2006.260.07:59:42.82#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:42.82#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.07:59:42.82#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.07:59:42.82#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.07:59:42.82$vc4f8/vblo=5,744.99 2006.260.07:59:42.82#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.07:59:42.82#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.07:59:42.82#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:42.82#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:42.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:42.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:42.82#ibcon#enter wrdev, iclass 14, count 0 2006.260.07:59:42.82#ibcon#first serial, iclass 14, count 0 2006.260.07:59:42.82#ibcon#enter sib2, iclass 14, count 0 2006.260.07:59:42.82#ibcon#flushed, iclass 14, count 0 2006.260.07:59:42.82#ibcon#about to write, iclass 14, count 0 2006.260.07:59:42.82#ibcon#wrote, iclass 14, count 0 2006.260.07:59:42.82#ibcon#about to read 3, iclass 14, count 0 2006.260.07:59:42.84#ibcon#read 3, iclass 14, count 0 2006.260.07:59:42.84#ibcon#about to read 4, iclass 14, count 0 2006.260.07:59:42.84#ibcon#read 4, iclass 14, count 0 2006.260.07:59:42.84#ibcon#about to read 5, iclass 14, count 0 2006.260.07:59:42.84#ibcon#read 5, iclass 14, count 0 2006.260.07:59:42.84#ibcon#about to read 6, iclass 14, count 0 2006.260.07:59:42.84#ibcon#read 6, iclass 14, count 0 2006.260.07:59:42.84#ibcon#end of sib2, iclass 14, count 0 2006.260.07:59:42.84#ibcon#*mode == 0, iclass 14, count 0 2006.260.07:59:42.84#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.07:59:42.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.07:59:42.84#ibcon#*before write, iclass 14, count 0 2006.260.07:59:42.84#ibcon#enter sib2, iclass 14, count 0 2006.260.07:59:42.84#ibcon#flushed, iclass 14, count 0 2006.260.07:59:42.84#ibcon#about to write, iclass 14, count 0 2006.260.07:59:42.84#ibcon#wrote, iclass 14, count 0 2006.260.07:59:42.84#ibcon#about to read 3, iclass 14, count 0 2006.260.07:59:42.88#ibcon#read 3, iclass 14, count 0 2006.260.07:59:42.88#ibcon#about to read 4, iclass 14, count 0 2006.260.07:59:42.88#ibcon#read 4, iclass 14, count 0 2006.260.07:59:42.88#ibcon#about to read 5, iclass 14, count 0 2006.260.07:59:42.88#ibcon#read 5, iclass 14, count 0 2006.260.07:59:42.88#ibcon#about to read 6, iclass 14, count 0 2006.260.07:59:42.88#ibcon#read 6, iclass 14, count 0 2006.260.07:59:42.88#ibcon#end of sib2, iclass 14, count 0 2006.260.07:59:42.88#ibcon#*after write, iclass 14, count 0 2006.260.07:59:42.88#ibcon#*before return 0, iclass 14, count 0 2006.260.07:59:42.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:42.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.07:59:42.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.07:59:42.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.07:59:42.88$vc4f8/vb=5,4 2006.260.07:59:42.88#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.07:59:42.88#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.07:59:42.88#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:42.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:42.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:42.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:42.94#ibcon#enter wrdev, iclass 16, count 2 2006.260.07:59:42.94#ibcon#first serial, iclass 16, count 2 2006.260.07:59:42.94#ibcon#enter sib2, iclass 16, count 2 2006.260.07:59:42.94#ibcon#flushed, iclass 16, count 2 2006.260.07:59:42.94#ibcon#about to write, iclass 16, count 2 2006.260.07:59:42.94#ibcon#wrote, iclass 16, count 2 2006.260.07:59:42.94#ibcon#about to read 3, iclass 16, count 2 2006.260.07:59:42.96#ibcon#read 3, iclass 16, count 2 2006.260.07:59:42.96#ibcon#about to read 4, iclass 16, count 2 2006.260.07:59:42.96#ibcon#read 4, iclass 16, count 2 2006.260.07:59:42.96#ibcon#about to read 5, iclass 16, count 2 2006.260.07:59:42.96#ibcon#read 5, iclass 16, count 2 2006.260.07:59:42.96#ibcon#about to read 6, iclass 16, count 2 2006.260.07:59:42.96#ibcon#read 6, iclass 16, count 2 2006.260.07:59:42.96#ibcon#end of sib2, iclass 16, count 2 2006.260.07:59:42.96#ibcon#*mode == 0, iclass 16, count 2 2006.260.07:59:42.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.07:59:42.96#ibcon#[27=AT05-04\r\n] 2006.260.07:59:42.96#ibcon#*before write, iclass 16, count 2 2006.260.07:59:42.96#ibcon#enter sib2, iclass 16, count 2 2006.260.07:59:42.96#ibcon#flushed, iclass 16, count 2 2006.260.07:59:42.96#ibcon#about to write, iclass 16, count 2 2006.260.07:59:42.96#ibcon#wrote, iclass 16, count 2 2006.260.07:59:42.96#ibcon#about to read 3, iclass 16, count 2 2006.260.07:59:42.99#ibcon#read 3, iclass 16, count 2 2006.260.07:59:42.99#ibcon#about to read 4, iclass 16, count 2 2006.260.07:59:42.99#ibcon#read 4, iclass 16, count 2 2006.260.07:59:42.99#ibcon#about to read 5, iclass 16, count 2 2006.260.07:59:42.99#ibcon#read 5, iclass 16, count 2 2006.260.07:59:42.99#ibcon#about to read 6, iclass 16, count 2 2006.260.07:59:42.99#ibcon#read 6, iclass 16, count 2 2006.260.07:59:42.99#ibcon#end of sib2, iclass 16, count 2 2006.260.07:59:42.99#ibcon#*after write, iclass 16, count 2 2006.260.07:59:42.99#ibcon#*before return 0, iclass 16, count 2 2006.260.07:59:42.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:42.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.07:59:42.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.07:59:42.99#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:42.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:43.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:43.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:43.11#ibcon#enter wrdev, iclass 16, count 0 2006.260.07:59:43.11#ibcon#first serial, iclass 16, count 0 2006.260.07:59:43.11#ibcon#enter sib2, iclass 16, count 0 2006.260.07:59:43.11#ibcon#flushed, iclass 16, count 0 2006.260.07:59:43.11#ibcon#about to write, iclass 16, count 0 2006.260.07:59:43.11#ibcon#wrote, iclass 16, count 0 2006.260.07:59:43.11#ibcon#about to read 3, iclass 16, count 0 2006.260.07:59:43.13#ibcon#read 3, iclass 16, count 0 2006.260.07:59:43.13#ibcon#about to read 4, iclass 16, count 0 2006.260.07:59:43.13#ibcon#read 4, iclass 16, count 0 2006.260.07:59:43.13#ibcon#about to read 5, iclass 16, count 0 2006.260.07:59:43.13#ibcon#read 5, iclass 16, count 0 2006.260.07:59:43.13#ibcon#about to read 6, iclass 16, count 0 2006.260.07:59:43.13#ibcon#read 6, iclass 16, count 0 2006.260.07:59:43.13#ibcon#end of sib2, iclass 16, count 0 2006.260.07:59:43.13#ibcon#*mode == 0, iclass 16, count 0 2006.260.07:59:43.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.07:59:43.13#ibcon#[27=USB\r\n] 2006.260.07:59:43.13#ibcon#*before write, iclass 16, count 0 2006.260.07:59:43.13#ibcon#enter sib2, iclass 16, count 0 2006.260.07:59:43.13#ibcon#flushed, iclass 16, count 0 2006.260.07:59:43.13#ibcon#about to write, iclass 16, count 0 2006.260.07:59:43.13#ibcon#wrote, iclass 16, count 0 2006.260.07:59:43.13#ibcon#about to read 3, iclass 16, count 0 2006.260.07:59:43.16#ibcon#read 3, iclass 16, count 0 2006.260.07:59:43.16#ibcon#about to read 4, iclass 16, count 0 2006.260.07:59:43.16#ibcon#read 4, iclass 16, count 0 2006.260.07:59:43.16#ibcon#about to read 5, iclass 16, count 0 2006.260.07:59:43.16#ibcon#read 5, iclass 16, count 0 2006.260.07:59:43.16#ibcon#about to read 6, iclass 16, count 0 2006.260.07:59:43.16#ibcon#read 6, iclass 16, count 0 2006.260.07:59:43.16#ibcon#end of sib2, iclass 16, count 0 2006.260.07:59:43.16#ibcon#*after write, iclass 16, count 0 2006.260.07:59:43.16#ibcon#*before return 0, iclass 16, count 0 2006.260.07:59:43.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:43.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.07:59:43.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.07:59:43.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.07:59:43.16$vc4f8/vblo=6,752.99 2006.260.07:59:43.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.07:59:43.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.07:59:43.16#ibcon#ireg 17 cls_cnt 0 2006.260.07:59:43.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:43.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:43.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:43.16#ibcon#enter wrdev, iclass 18, count 0 2006.260.07:59:43.16#ibcon#first serial, iclass 18, count 0 2006.260.07:59:43.16#ibcon#enter sib2, iclass 18, count 0 2006.260.07:59:43.16#ibcon#flushed, iclass 18, count 0 2006.260.07:59:43.16#ibcon#about to write, iclass 18, count 0 2006.260.07:59:43.16#ibcon#wrote, iclass 18, count 0 2006.260.07:59:43.16#ibcon#about to read 3, iclass 18, count 0 2006.260.07:59:43.18#ibcon#read 3, iclass 18, count 0 2006.260.07:59:43.18#ibcon#about to read 4, iclass 18, count 0 2006.260.07:59:43.18#ibcon#read 4, iclass 18, count 0 2006.260.07:59:43.18#ibcon#about to read 5, iclass 18, count 0 2006.260.07:59:43.18#ibcon#read 5, iclass 18, count 0 2006.260.07:59:43.18#ibcon#about to read 6, iclass 18, count 0 2006.260.07:59:43.18#ibcon#read 6, iclass 18, count 0 2006.260.07:59:43.18#ibcon#end of sib2, iclass 18, count 0 2006.260.07:59:43.18#ibcon#*mode == 0, iclass 18, count 0 2006.260.07:59:43.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.07:59:43.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.07:59:43.18#ibcon#*before write, iclass 18, count 0 2006.260.07:59:43.18#ibcon#enter sib2, iclass 18, count 0 2006.260.07:59:43.18#ibcon#flushed, iclass 18, count 0 2006.260.07:59:43.18#ibcon#about to write, iclass 18, count 0 2006.260.07:59:43.18#ibcon#wrote, iclass 18, count 0 2006.260.07:59:43.18#ibcon#about to read 3, iclass 18, count 0 2006.260.07:59:43.22#ibcon#read 3, iclass 18, count 0 2006.260.07:59:43.22#ibcon#about to read 4, iclass 18, count 0 2006.260.07:59:43.22#ibcon#read 4, iclass 18, count 0 2006.260.07:59:43.22#ibcon#about to read 5, iclass 18, count 0 2006.260.07:59:43.22#ibcon#read 5, iclass 18, count 0 2006.260.07:59:43.22#ibcon#about to read 6, iclass 18, count 0 2006.260.07:59:43.22#ibcon#read 6, iclass 18, count 0 2006.260.07:59:43.22#ibcon#end of sib2, iclass 18, count 0 2006.260.07:59:43.22#ibcon#*after write, iclass 18, count 0 2006.260.07:59:43.22#ibcon#*before return 0, iclass 18, count 0 2006.260.07:59:43.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:43.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.07:59:43.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.07:59:43.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.07:59:43.22$vc4f8/vb=6,4 2006.260.07:59:43.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.07:59:43.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.07:59:43.22#ibcon#ireg 11 cls_cnt 2 2006.260.07:59:43.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:43.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:43.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:43.28#ibcon#enter wrdev, iclass 20, count 2 2006.260.07:59:43.28#ibcon#first serial, iclass 20, count 2 2006.260.07:59:43.28#ibcon#enter sib2, iclass 20, count 2 2006.260.07:59:43.28#ibcon#flushed, iclass 20, count 2 2006.260.07:59:43.28#ibcon#about to write, iclass 20, count 2 2006.260.07:59:43.28#ibcon#wrote, iclass 20, count 2 2006.260.07:59:43.28#ibcon#about to read 3, iclass 20, count 2 2006.260.07:59:43.30#ibcon#read 3, iclass 20, count 2 2006.260.07:59:43.30#ibcon#about to read 4, iclass 20, count 2 2006.260.07:59:43.30#ibcon#read 4, iclass 20, count 2 2006.260.07:59:43.30#ibcon#about to read 5, iclass 20, count 2 2006.260.07:59:43.30#ibcon#read 5, iclass 20, count 2 2006.260.07:59:43.30#ibcon#about to read 6, iclass 20, count 2 2006.260.07:59:43.30#ibcon#read 6, iclass 20, count 2 2006.260.07:59:43.30#ibcon#end of sib2, iclass 20, count 2 2006.260.07:59:43.30#ibcon#*mode == 0, iclass 20, count 2 2006.260.07:59:43.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.07:59:43.30#ibcon#[27=AT06-04\r\n] 2006.260.07:59:43.30#ibcon#*before write, iclass 20, count 2 2006.260.07:59:43.30#ibcon#enter sib2, iclass 20, count 2 2006.260.07:59:43.30#ibcon#flushed, iclass 20, count 2 2006.260.07:59:43.30#ibcon#about to write, iclass 20, count 2 2006.260.07:59:43.30#ibcon#wrote, iclass 20, count 2 2006.260.07:59:43.30#ibcon#about to read 3, iclass 20, count 2 2006.260.07:59:43.33#ibcon#read 3, iclass 20, count 2 2006.260.07:59:43.33#ibcon#about to read 4, iclass 20, count 2 2006.260.07:59:43.33#ibcon#read 4, iclass 20, count 2 2006.260.07:59:43.33#ibcon#about to read 5, iclass 20, count 2 2006.260.07:59:43.33#ibcon#read 5, iclass 20, count 2 2006.260.07:59:43.33#ibcon#about to read 6, iclass 20, count 2 2006.260.07:59:43.33#ibcon#read 6, iclass 20, count 2 2006.260.07:59:43.33#ibcon#end of sib2, iclass 20, count 2 2006.260.07:59:43.33#ibcon#*after write, iclass 20, count 2 2006.260.07:59:43.33#ibcon#*before return 0, iclass 20, count 2 2006.260.07:59:43.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:43.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.07:59:43.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.07:59:43.33#ibcon#ireg 7 cls_cnt 0 2006.260.07:59:43.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:43.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:43.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:43.45#ibcon#enter wrdev, iclass 20, count 0 2006.260.07:59:43.45#ibcon#first serial, iclass 20, count 0 2006.260.07:59:43.45#ibcon#enter sib2, iclass 20, count 0 2006.260.07:59:43.45#ibcon#flushed, iclass 20, count 0 2006.260.07:59:43.45#ibcon#about to write, iclass 20, count 0 2006.260.07:59:43.45#ibcon#wrote, iclass 20, count 0 2006.260.07:59:43.45#ibcon#about to read 3, iclass 20, count 0 2006.260.07:59:43.47#ibcon#read 3, iclass 20, count 0 2006.260.07:59:43.47#ibcon#about to read 4, iclass 20, count 0 2006.260.07:59:43.47#ibcon#read 4, iclass 20, count 0 2006.260.07:59:43.47#ibcon#about to read 5, iclass 20, count 0 2006.260.07:59:43.47#ibcon#read 5, iclass 20, count 0 2006.260.07:59:43.47#ibcon#about to read 6, iclass 20, count 0 2006.260.07:59:43.47#ibcon#read 6, iclass 20, count 0 2006.260.07:59:43.47#ibcon#end of sib2, iclass 20, count 0 2006.260.07:59:43.47#ibcon#*mode == 0, iclass 20, count 0 2006.260.07:59:43.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.07:59:43.47#ibcon#[27=USB\r\n] 2006.260.07:59:43.47#ibcon#*before write, iclass 20, count 0 2006.260.07:59:43.47#ibcon#enter sib2, iclass 20, count 0 2006.260.07:59:43.47#ibcon#flushed, iclass 20, count 0 2006.260.07:59:43.47#ibcon#about to write, iclass 20, count 0 2006.260.07:59:43.47#ibcon#wrote, iclass 20, count 0 2006.260.07:59:43.47#ibcon#about to read 3, iclass 20, count 0 2006.260.07:59:43.50#ibcon#read 3, iclass 20, count 0 2006.260.07:59:43.50#ibcon#about to read 4, iclass 20, count 0 2006.260.07:59:43.50#ibcon#read 4, iclass 20, count 0 2006.260.07:59:43.50#ibcon#about to read 5, iclass 20, count 0 2006.260.07:59:43.50#ibcon#read 5, iclass 20, count 0 2006.260.07:59:43.50#ibcon#about to read 6, iclass 20, count 0 2006.260.07:59:43.50#ibcon#read 6, iclass 20, count 0 2006.260.07:59:43.50#ibcon#end of sib2, iclass 20, count 0 2006.260.07:59:43.50#ibcon#*after write, iclass 20, count 0 2006.260.07:59:43.50#ibcon#*before return 0, iclass 20, count 0 2006.260.07:59:43.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:43.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.07:59:43.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.07:59:43.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.07:59:43.50$vc4f8/vabw=wide 2006.260.07:59:43.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.07:59:43.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.07:59:43.50#ibcon#ireg 8 cls_cnt 0 2006.260.07:59:43.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:43.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:43.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:43.50#ibcon#enter wrdev, iclass 22, count 0 2006.260.07:59:43.50#ibcon#first serial, iclass 22, count 0 2006.260.07:59:43.50#ibcon#enter sib2, iclass 22, count 0 2006.260.07:59:43.50#ibcon#flushed, iclass 22, count 0 2006.260.07:59:43.50#ibcon#about to write, iclass 22, count 0 2006.260.07:59:43.50#ibcon#wrote, iclass 22, count 0 2006.260.07:59:43.50#ibcon#about to read 3, iclass 22, count 0 2006.260.07:59:43.52#ibcon#read 3, iclass 22, count 0 2006.260.07:59:43.52#ibcon#about to read 4, iclass 22, count 0 2006.260.07:59:43.52#ibcon#read 4, iclass 22, count 0 2006.260.07:59:43.52#ibcon#about to read 5, iclass 22, count 0 2006.260.07:59:43.52#ibcon#read 5, iclass 22, count 0 2006.260.07:59:43.52#ibcon#about to read 6, iclass 22, count 0 2006.260.07:59:43.52#ibcon#read 6, iclass 22, count 0 2006.260.07:59:43.52#ibcon#end of sib2, iclass 22, count 0 2006.260.07:59:43.52#ibcon#*mode == 0, iclass 22, count 0 2006.260.07:59:43.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.07:59:43.52#ibcon#[25=BW32\r\n] 2006.260.07:59:43.52#ibcon#*before write, iclass 22, count 0 2006.260.07:59:43.52#ibcon#enter sib2, iclass 22, count 0 2006.260.07:59:43.52#ibcon#flushed, iclass 22, count 0 2006.260.07:59:43.52#ibcon#about to write, iclass 22, count 0 2006.260.07:59:43.52#ibcon#wrote, iclass 22, count 0 2006.260.07:59:43.52#ibcon#about to read 3, iclass 22, count 0 2006.260.07:59:43.55#ibcon#read 3, iclass 22, count 0 2006.260.07:59:43.55#ibcon#about to read 4, iclass 22, count 0 2006.260.07:59:43.55#ibcon#read 4, iclass 22, count 0 2006.260.07:59:43.55#ibcon#about to read 5, iclass 22, count 0 2006.260.07:59:43.55#ibcon#read 5, iclass 22, count 0 2006.260.07:59:43.55#ibcon#about to read 6, iclass 22, count 0 2006.260.07:59:43.55#ibcon#read 6, iclass 22, count 0 2006.260.07:59:43.55#ibcon#end of sib2, iclass 22, count 0 2006.260.07:59:43.55#ibcon#*after write, iclass 22, count 0 2006.260.07:59:43.55#ibcon#*before return 0, iclass 22, count 0 2006.260.07:59:43.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:43.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.07:59:43.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.07:59:43.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.07:59:43.55$vc4f8/vbbw=wide 2006.260.07:59:43.55#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.07:59:43.55#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.07:59:43.55#ibcon#ireg 8 cls_cnt 0 2006.260.07:59:43.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:59:43.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:59:43.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:59:43.62#ibcon#enter wrdev, iclass 24, count 0 2006.260.07:59:43.62#ibcon#first serial, iclass 24, count 0 2006.260.07:59:43.62#ibcon#enter sib2, iclass 24, count 0 2006.260.07:59:43.62#ibcon#flushed, iclass 24, count 0 2006.260.07:59:43.62#ibcon#about to write, iclass 24, count 0 2006.260.07:59:43.62#ibcon#wrote, iclass 24, count 0 2006.260.07:59:43.62#ibcon#about to read 3, iclass 24, count 0 2006.260.07:59:43.64#ibcon#read 3, iclass 24, count 0 2006.260.07:59:43.64#ibcon#about to read 4, iclass 24, count 0 2006.260.07:59:43.64#ibcon#read 4, iclass 24, count 0 2006.260.07:59:43.64#ibcon#about to read 5, iclass 24, count 0 2006.260.07:59:43.64#ibcon#read 5, iclass 24, count 0 2006.260.07:59:43.64#ibcon#about to read 6, iclass 24, count 0 2006.260.07:59:43.64#ibcon#read 6, iclass 24, count 0 2006.260.07:59:43.64#ibcon#end of sib2, iclass 24, count 0 2006.260.07:59:43.64#ibcon#*mode == 0, iclass 24, count 0 2006.260.07:59:43.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.07:59:43.64#ibcon#[27=BW32\r\n] 2006.260.07:59:43.64#ibcon#*before write, iclass 24, count 0 2006.260.07:59:43.64#ibcon#enter sib2, iclass 24, count 0 2006.260.07:59:43.64#ibcon#flushed, iclass 24, count 0 2006.260.07:59:43.64#ibcon#about to write, iclass 24, count 0 2006.260.07:59:43.64#ibcon#wrote, iclass 24, count 0 2006.260.07:59:43.64#ibcon#about to read 3, iclass 24, count 0 2006.260.07:59:43.67#ibcon#read 3, iclass 24, count 0 2006.260.07:59:43.67#ibcon#about to read 4, iclass 24, count 0 2006.260.07:59:43.67#ibcon#read 4, iclass 24, count 0 2006.260.07:59:43.67#ibcon#about to read 5, iclass 24, count 0 2006.260.07:59:43.67#ibcon#read 5, iclass 24, count 0 2006.260.07:59:43.67#ibcon#about to read 6, iclass 24, count 0 2006.260.07:59:43.67#ibcon#read 6, iclass 24, count 0 2006.260.07:59:43.67#ibcon#end of sib2, iclass 24, count 0 2006.260.07:59:43.67#ibcon#*after write, iclass 24, count 0 2006.260.07:59:43.67#ibcon#*before return 0, iclass 24, count 0 2006.260.07:59:43.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:59:43.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.07:59:43.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.07:59:43.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.07:59:43.67$4f8m12a/ifd4f 2006.260.07:59:43.67$ifd4f/lo= 2006.260.07:59:43.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.07:59:43.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.07:59:43.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.07:59:43.67$ifd4f/patch= 2006.260.07:59:43.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.07:59:43.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.07:59:43.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.07:59:43.67$4f8m12a/"form=m,16.000,1:2 2006.260.07:59:43.67$4f8m12a/"tpicd 2006.260.07:59:43.67$4f8m12a/echo=off 2006.260.07:59:43.67$4f8m12a/xlog=off 2006.260.07:59:43.67:!2006.260.08:00:10 2006.260.07:59:52.14#trakl#Source acquired 2006.260.07:59:54.14#flagr#flagr/antenna,acquired 2006.260.08:00:10.00:preob 2006.260.08:00:10.14/onsource/TRACKING 2006.260.08:00:10.14:!2006.260.08:00:20 2006.260.08:00:20.00:data_valid=on 2006.260.08:00:20.00:midob 2006.260.08:00:21.13/onsource/TRACKING 2006.260.08:00:21.13/wx/22.87,1010.4,88 2006.260.08:00:21.35/cable/+6.4572E-03 2006.260.08:00:22.44/va/01,08,usb,yes,31,33 2006.260.08:00:22.44/va/02,07,usb,yes,31,33 2006.260.08:00:22.44/va/03,08,usb,yes,24,24 2006.260.08:00:22.44/va/04,07,usb,yes,32,35 2006.260.08:00:22.44/va/05,07,usb,yes,36,37 2006.260.08:00:22.44/va/06,06,usb,yes,35,35 2006.260.08:00:22.44/va/07,06,usb,yes,35,35 2006.260.08:00:22.44/va/08,06,usb,yes,38,37 2006.260.08:00:22.67/valo/01,532.99,yes,locked 2006.260.08:00:22.67/valo/02,572.99,yes,locked 2006.260.08:00:22.67/valo/03,672.99,yes,locked 2006.260.08:00:22.67/valo/04,832.99,yes,locked 2006.260.08:00:22.67/valo/05,652.99,yes,locked 2006.260.08:00:22.67/valo/06,772.99,yes,locked 2006.260.08:00:22.67/valo/07,832.99,yes,locked 2006.260.08:00:22.67/valo/08,852.99,yes,locked 2006.260.08:00:23.76/vb/01,04,usb,yes,30,29 2006.260.08:00:23.76/vb/02,05,usb,yes,28,29 2006.260.08:00:23.76/vb/03,04,usb,yes,28,32 2006.260.08:00:23.76/vb/04,05,usb,yes,26,26 2006.260.08:00:23.76/vb/05,04,usb,yes,27,32 2006.260.08:00:23.76/vb/06,04,usb,yes,28,31 2006.260.08:00:23.76/vb/07,04,usb,yes,31,31 2006.260.08:00:23.76/vb/08,04,usb,yes,28,32 2006.260.08:00:24.00/vblo/01,632.99,yes,locked 2006.260.08:00:24.00/vblo/02,640.99,yes,locked 2006.260.08:00:24.00/vblo/03,656.99,yes,locked 2006.260.08:00:24.00/vblo/04,712.99,yes,locked 2006.260.08:00:24.00/vblo/05,744.99,yes,locked 2006.260.08:00:24.00/vblo/06,752.99,yes,locked 2006.260.08:00:24.00/vblo/07,734.99,yes,locked 2006.260.08:00:24.00/vblo/08,744.99,yes,locked 2006.260.08:00:24.15/vabw/8 2006.260.08:00:24.30/vbbw/8 2006.260.08:00:24.44/xfe/off,on,15.0 2006.260.08:00:24.82/ifatt/23,28,28,28 2006.260.08:00:25.08/fmout-gps/S +4.46E-07 2006.260.08:00:25.12:!2006.260.08:01:20 2006.260.08:01:20.01:data_valid=off 2006.260.08:01:20.02:postob 2006.260.08:01:20.15/cable/+6.4569E-03 2006.260.08:01:20.16/wx/22.86,1010.4,88 2006.260.08:01:21.07/fmout-gps/S +4.46E-07 2006.260.08:01:21.08:scan_name=260-0802,k06260,60 2006.260.08:01:21.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.260.08:01:21.13#flagr#flagr/antenna,new-source 2006.260.08:01:22.13:checkk5 2006.260.08:01:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:01:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:01:23.42/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:01:23.84/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:01:24.31/chk_obsdata//k5ts1/T2600800??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:01:24.74/chk_obsdata//k5ts2/T2600800??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:01:25.13/chk_obsdata//k5ts3/T2600800??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:01:25.54/chk_obsdata//k5ts4/T2600800??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:01:26.53/k5log//k5ts1_log_newline 2006.260.08:01:27.27/k5log//k5ts2_log_newline 2006.260.08:01:28.14/k5log//k5ts3_log_newline 2006.260.08:01:28.94/k5log//k5ts4_log_newline 2006.260.08:01:28.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:01:28.96:4f8m12a=2 2006.260.08:01:28.96$4f8m12a/echo=on 2006.260.08:01:28.96$4f8m12a/pcalon 2006.260.08:01:28.96$pcalon/"no phase cal control is implemented here 2006.260.08:01:28.96$4f8m12a/"tpicd=stop 2006.260.08:01:28.96$4f8m12a/vc4f8 2006.260.08:01:28.96$vc4f8/valo=1,532.99 2006.260.08:01:28.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.08:01:28.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.08:01:28.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:28.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:28.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:28.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:28.97#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:01:28.97#ibcon#first serial, iclass 31, count 0 2006.260.08:01:28.97#ibcon#enter sib2, iclass 31, count 0 2006.260.08:01:28.97#ibcon#flushed, iclass 31, count 0 2006.260.08:01:28.97#ibcon#about to write, iclass 31, count 0 2006.260.08:01:28.97#ibcon#wrote, iclass 31, count 0 2006.260.08:01:28.97#ibcon#about to read 3, iclass 31, count 0 2006.260.08:01:29.01#ibcon#read 3, iclass 31, count 0 2006.260.08:01:29.01#ibcon#about to read 4, iclass 31, count 0 2006.260.08:01:29.01#ibcon#read 4, iclass 31, count 0 2006.260.08:01:29.01#ibcon#about to read 5, iclass 31, count 0 2006.260.08:01:29.01#ibcon#read 5, iclass 31, count 0 2006.260.08:01:29.01#ibcon#about to read 6, iclass 31, count 0 2006.260.08:01:29.01#ibcon#read 6, iclass 31, count 0 2006.260.08:01:29.01#ibcon#end of sib2, iclass 31, count 0 2006.260.08:01:29.01#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:01:29.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:01:29.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:01:29.01#ibcon#*before write, iclass 31, count 0 2006.260.08:01:29.01#ibcon#enter sib2, iclass 31, count 0 2006.260.08:01:29.01#ibcon#flushed, iclass 31, count 0 2006.260.08:01:29.01#ibcon#about to write, iclass 31, count 0 2006.260.08:01:29.01#ibcon#wrote, iclass 31, count 0 2006.260.08:01:29.01#ibcon#about to read 3, iclass 31, count 0 2006.260.08:01:29.05#ibcon#read 3, iclass 31, count 0 2006.260.08:01:29.05#ibcon#about to read 4, iclass 31, count 0 2006.260.08:01:29.05#ibcon#read 4, iclass 31, count 0 2006.260.08:01:29.05#ibcon#about to read 5, iclass 31, count 0 2006.260.08:01:29.05#ibcon#read 5, iclass 31, count 0 2006.260.08:01:29.05#ibcon#about to read 6, iclass 31, count 0 2006.260.08:01:29.05#ibcon#read 6, iclass 31, count 0 2006.260.08:01:29.05#ibcon#end of sib2, iclass 31, count 0 2006.260.08:01:29.05#ibcon#*after write, iclass 31, count 0 2006.260.08:01:29.05#ibcon#*before return 0, iclass 31, count 0 2006.260.08:01:29.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:29.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:29.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:01:29.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:01:29.05$vc4f8/va=1,8 2006.260.08:01:29.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.08:01:29.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.08:01:29.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:29.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:29.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:29.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:29.05#ibcon#enter wrdev, iclass 33, count 2 2006.260.08:01:29.05#ibcon#first serial, iclass 33, count 2 2006.260.08:01:29.05#ibcon#enter sib2, iclass 33, count 2 2006.260.08:01:29.05#ibcon#flushed, iclass 33, count 2 2006.260.08:01:29.05#ibcon#about to write, iclass 33, count 2 2006.260.08:01:29.05#ibcon#wrote, iclass 33, count 2 2006.260.08:01:29.05#ibcon#about to read 3, iclass 33, count 2 2006.260.08:01:29.07#ibcon#read 3, iclass 33, count 2 2006.260.08:01:29.07#ibcon#about to read 4, iclass 33, count 2 2006.260.08:01:29.07#ibcon#read 4, iclass 33, count 2 2006.260.08:01:29.07#ibcon#about to read 5, iclass 33, count 2 2006.260.08:01:29.07#ibcon#read 5, iclass 33, count 2 2006.260.08:01:29.07#ibcon#about to read 6, iclass 33, count 2 2006.260.08:01:29.07#ibcon#read 6, iclass 33, count 2 2006.260.08:01:29.07#ibcon#end of sib2, iclass 33, count 2 2006.260.08:01:29.07#ibcon#*mode == 0, iclass 33, count 2 2006.260.08:01:29.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.08:01:29.07#ibcon#[25=AT01-08\r\n] 2006.260.08:01:29.07#ibcon#*before write, iclass 33, count 2 2006.260.08:01:29.07#ibcon#enter sib2, iclass 33, count 2 2006.260.08:01:29.07#ibcon#flushed, iclass 33, count 2 2006.260.08:01:29.07#ibcon#about to write, iclass 33, count 2 2006.260.08:01:29.07#ibcon#wrote, iclass 33, count 2 2006.260.08:01:29.07#ibcon#about to read 3, iclass 33, count 2 2006.260.08:01:29.11#ibcon#read 3, iclass 33, count 2 2006.260.08:01:29.11#ibcon#about to read 4, iclass 33, count 2 2006.260.08:01:29.11#ibcon#read 4, iclass 33, count 2 2006.260.08:01:29.11#ibcon#about to read 5, iclass 33, count 2 2006.260.08:01:29.11#ibcon#read 5, iclass 33, count 2 2006.260.08:01:29.11#ibcon#about to read 6, iclass 33, count 2 2006.260.08:01:29.11#ibcon#read 6, iclass 33, count 2 2006.260.08:01:29.11#ibcon#end of sib2, iclass 33, count 2 2006.260.08:01:29.11#ibcon#*after write, iclass 33, count 2 2006.260.08:01:29.11#ibcon#*before return 0, iclass 33, count 2 2006.260.08:01:29.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:29.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:29.11#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.08:01:29.11#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:29.11#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:29.22#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:29.22#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:29.22#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:01:29.22#ibcon#first serial, iclass 33, count 0 2006.260.08:01:29.22#ibcon#enter sib2, iclass 33, count 0 2006.260.08:01:29.22#ibcon#flushed, iclass 33, count 0 2006.260.08:01:29.22#ibcon#about to write, iclass 33, count 0 2006.260.08:01:29.22#ibcon#wrote, iclass 33, count 0 2006.260.08:01:29.22#ibcon#about to read 3, iclass 33, count 0 2006.260.08:01:29.24#ibcon#read 3, iclass 33, count 0 2006.260.08:01:29.24#ibcon#about to read 4, iclass 33, count 0 2006.260.08:01:29.24#ibcon#read 4, iclass 33, count 0 2006.260.08:01:29.24#ibcon#about to read 5, iclass 33, count 0 2006.260.08:01:29.24#ibcon#read 5, iclass 33, count 0 2006.260.08:01:29.24#ibcon#about to read 6, iclass 33, count 0 2006.260.08:01:29.24#ibcon#read 6, iclass 33, count 0 2006.260.08:01:29.24#ibcon#end of sib2, iclass 33, count 0 2006.260.08:01:29.24#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:01:29.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:01:29.24#ibcon#[25=USB\r\n] 2006.260.08:01:29.24#ibcon#*before write, iclass 33, count 0 2006.260.08:01:29.24#ibcon#enter sib2, iclass 33, count 0 2006.260.08:01:29.24#ibcon#flushed, iclass 33, count 0 2006.260.08:01:29.24#ibcon#about to write, iclass 33, count 0 2006.260.08:01:29.24#ibcon#wrote, iclass 33, count 0 2006.260.08:01:29.24#ibcon#about to read 3, iclass 33, count 0 2006.260.08:01:29.27#ibcon#read 3, iclass 33, count 0 2006.260.08:01:29.27#ibcon#about to read 4, iclass 33, count 0 2006.260.08:01:29.27#ibcon#read 4, iclass 33, count 0 2006.260.08:01:29.27#ibcon#about to read 5, iclass 33, count 0 2006.260.08:01:29.27#ibcon#read 5, iclass 33, count 0 2006.260.08:01:29.27#ibcon#about to read 6, iclass 33, count 0 2006.260.08:01:29.27#ibcon#read 6, iclass 33, count 0 2006.260.08:01:29.27#ibcon#end of sib2, iclass 33, count 0 2006.260.08:01:29.27#ibcon#*after write, iclass 33, count 0 2006.260.08:01:29.27#ibcon#*before return 0, iclass 33, count 0 2006.260.08:01:29.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:29.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:29.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:01:29.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:01:29.27$vc4f8/valo=2,572.99 2006.260.08:01:29.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.08:01:29.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.08:01:29.27#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:29.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:29.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:29.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:29.27#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:01:29.27#ibcon#first serial, iclass 35, count 0 2006.260.08:01:29.27#ibcon#enter sib2, iclass 35, count 0 2006.260.08:01:29.27#ibcon#flushed, iclass 35, count 0 2006.260.08:01:29.27#ibcon#about to write, iclass 35, count 0 2006.260.08:01:29.27#ibcon#wrote, iclass 35, count 0 2006.260.08:01:29.27#ibcon#about to read 3, iclass 35, count 0 2006.260.08:01:29.29#ibcon#read 3, iclass 35, count 0 2006.260.08:01:29.29#ibcon#about to read 4, iclass 35, count 0 2006.260.08:01:29.29#ibcon#read 4, iclass 35, count 0 2006.260.08:01:29.29#ibcon#about to read 5, iclass 35, count 0 2006.260.08:01:29.29#ibcon#read 5, iclass 35, count 0 2006.260.08:01:29.29#ibcon#about to read 6, iclass 35, count 0 2006.260.08:01:29.29#ibcon#read 6, iclass 35, count 0 2006.260.08:01:29.29#ibcon#end of sib2, iclass 35, count 0 2006.260.08:01:29.29#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:01:29.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:01:29.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:01:29.29#ibcon#*before write, iclass 35, count 0 2006.260.08:01:29.29#ibcon#enter sib2, iclass 35, count 0 2006.260.08:01:29.29#ibcon#flushed, iclass 35, count 0 2006.260.08:01:29.29#ibcon#about to write, iclass 35, count 0 2006.260.08:01:29.29#ibcon#wrote, iclass 35, count 0 2006.260.08:01:29.29#ibcon#about to read 3, iclass 35, count 0 2006.260.08:01:29.33#ibcon#read 3, iclass 35, count 0 2006.260.08:01:29.33#ibcon#about to read 4, iclass 35, count 0 2006.260.08:01:29.33#ibcon#read 4, iclass 35, count 0 2006.260.08:01:29.33#ibcon#about to read 5, iclass 35, count 0 2006.260.08:01:29.33#ibcon#read 5, iclass 35, count 0 2006.260.08:01:29.33#ibcon#about to read 6, iclass 35, count 0 2006.260.08:01:29.33#ibcon#read 6, iclass 35, count 0 2006.260.08:01:29.33#ibcon#end of sib2, iclass 35, count 0 2006.260.08:01:29.33#ibcon#*after write, iclass 35, count 0 2006.260.08:01:29.33#ibcon#*before return 0, iclass 35, count 0 2006.260.08:01:29.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:29.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:29.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:01:29.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:01:29.33$vc4f8/va=2,7 2006.260.08:01:29.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.08:01:29.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.08:01:29.33#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:29.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:29.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:29.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:29.39#ibcon#enter wrdev, iclass 37, count 2 2006.260.08:01:29.39#ibcon#first serial, iclass 37, count 2 2006.260.08:01:29.39#ibcon#enter sib2, iclass 37, count 2 2006.260.08:01:29.39#ibcon#flushed, iclass 37, count 2 2006.260.08:01:29.39#ibcon#about to write, iclass 37, count 2 2006.260.08:01:29.39#ibcon#wrote, iclass 37, count 2 2006.260.08:01:29.39#ibcon#about to read 3, iclass 37, count 2 2006.260.08:01:29.42#ibcon#read 3, iclass 37, count 2 2006.260.08:01:29.42#ibcon#about to read 4, iclass 37, count 2 2006.260.08:01:29.42#ibcon#read 4, iclass 37, count 2 2006.260.08:01:29.42#ibcon#about to read 5, iclass 37, count 2 2006.260.08:01:29.42#ibcon#read 5, iclass 37, count 2 2006.260.08:01:29.42#ibcon#about to read 6, iclass 37, count 2 2006.260.08:01:29.42#ibcon#read 6, iclass 37, count 2 2006.260.08:01:29.42#ibcon#end of sib2, iclass 37, count 2 2006.260.08:01:29.42#ibcon#*mode == 0, iclass 37, count 2 2006.260.08:01:29.42#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.08:01:29.42#ibcon#[25=AT02-07\r\n] 2006.260.08:01:29.42#ibcon#*before write, iclass 37, count 2 2006.260.08:01:29.42#ibcon#enter sib2, iclass 37, count 2 2006.260.08:01:29.42#ibcon#flushed, iclass 37, count 2 2006.260.08:01:29.42#ibcon#about to write, iclass 37, count 2 2006.260.08:01:29.42#ibcon#wrote, iclass 37, count 2 2006.260.08:01:29.42#ibcon#about to read 3, iclass 37, count 2 2006.260.08:01:29.45#ibcon#read 3, iclass 37, count 2 2006.260.08:01:29.45#ibcon#about to read 4, iclass 37, count 2 2006.260.08:01:29.45#ibcon#read 4, iclass 37, count 2 2006.260.08:01:29.45#ibcon#about to read 5, iclass 37, count 2 2006.260.08:01:29.45#ibcon#read 5, iclass 37, count 2 2006.260.08:01:29.45#ibcon#about to read 6, iclass 37, count 2 2006.260.08:01:29.45#ibcon#read 6, iclass 37, count 2 2006.260.08:01:29.45#ibcon#end of sib2, iclass 37, count 2 2006.260.08:01:29.45#ibcon#*after write, iclass 37, count 2 2006.260.08:01:29.45#ibcon#*before return 0, iclass 37, count 2 2006.260.08:01:29.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:29.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:29.45#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.08:01:29.45#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:29.45#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:29.57#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:29.57#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:29.57#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:01:29.57#ibcon#first serial, iclass 37, count 0 2006.260.08:01:29.57#ibcon#enter sib2, iclass 37, count 0 2006.260.08:01:29.57#ibcon#flushed, iclass 37, count 0 2006.260.08:01:29.57#ibcon#about to write, iclass 37, count 0 2006.260.08:01:29.57#ibcon#wrote, iclass 37, count 0 2006.260.08:01:29.57#ibcon#about to read 3, iclass 37, count 0 2006.260.08:01:29.59#ibcon#read 3, iclass 37, count 0 2006.260.08:01:29.59#ibcon#about to read 4, iclass 37, count 0 2006.260.08:01:29.59#ibcon#read 4, iclass 37, count 0 2006.260.08:01:29.59#ibcon#about to read 5, iclass 37, count 0 2006.260.08:01:29.59#ibcon#read 5, iclass 37, count 0 2006.260.08:01:29.59#ibcon#about to read 6, iclass 37, count 0 2006.260.08:01:29.59#ibcon#read 6, iclass 37, count 0 2006.260.08:01:29.59#ibcon#end of sib2, iclass 37, count 0 2006.260.08:01:29.59#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:01:29.59#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:01:29.59#ibcon#[25=USB\r\n] 2006.260.08:01:29.59#ibcon#*before write, iclass 37, count 0 2006.260.08:01:29.59#ibcon#enter sib2, iclass 37, count 0 2006.260.08:01:29.59#ibcon#flushed, iclass 37, count 0 2006.260.08:01:29.59#ibcon#about to write, iclass 37, count 0 2006.260.08:01:29.59#ibcon#wrote, iclass 37, count 0 2006.260.08:01:29.59#ibcon#about to read 3, iclass 37, count 0 2006.260.08:01:29.62#ibcon#read 3, iclass 37, count 0 2006.260.08:01:29.62#ibcon#about to read 4, iclass 37, count 0 2006.260.08:01:29.62#ibcon#read 4, iclass 37, count 0 2006.260.08:01:29.62#ibcon#about to read 5, iclass 37, count 0 2006.260.08:01:29.62#ibcon#read 5, iclass 37, count 0 2006.260.08:01:29.62#ibcon#about to read 6, iclass 37, count 0 2006.260.08:01:29.62#ibcon#read 6, iclass 37, count 0 2006.260.08:01:29.62#ibcon#end of sib2, iclass 37, count 0 2006.260.08:01:29.62#ibcon#*after write, iclass 37, count 0 2006.260.08:01:29.62#ibcon#*before return 0, iclass 37, count 0 2006.260.08:01:29.62#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:29.62#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:29.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:01:29.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:01:29.62$vc4f8/valo=3,672.99 2006.260.08:01:29.62#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.08:01:29.62#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.08:01:29.62#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:29.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:29.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:29.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:29.62#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:01:29.62#ibcon#first serial, iclass 39, count 0 2006.260.08:01:29.62#ibcon#enter sib2, iclass 39, count 0 2006.260.08:01:29.62#ibcon#flushed, iclass 39, count 0 2006.260.08:01:29.62#ibcon#about to write, iclass 39, count 0 2006.260.08:01:29.62#ibcon#wrote, iclass 39, count 0 2006.260.08:01:29.62#ibcon#about to read 3, iclass 39, count 0 2006.260.08:01:29.64#ibcon#read 3, iclass 39, count 0 2006.260.08:01:29.64#ibcon#about to read 4, iclass 39, count 0 2006.260.08:01:29.64#ibcon#read 4, iclass 39, count 0 2006.260.08:01:29.64#ibcon#about to read 5, iclass 39, count 0 2006.260.08:01:29.64#ibcon#read 5, iclass 39, count 0 2006.260.08:01:29.64#ibcon#about to read 6, iclass 39, count 0 2006.260.08:01:29.64#ibcon#read 6, iclass 39, count 0 2006.260.08:01:29.64#ibcon#end of sib2, iclass 39, count 0 2006.260.08:01:29.64#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:01:29.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:01:29.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:01:29.64#ibcon#*before write, iclass 39, count 0 2006.260.08:01:29.64#ibcon#enter sib2, iclass 39, count 0 2006.260.08:01:29.64#ibcon#flushed, iclass 39, count 0 2006.260.08:01:29.64#ibcon#about to write, iclass 39, count 0 2006.260.08:01:29.64#ibcon#wrote, iclass 39, count 0 2006.260.08:01:29.64#ibcon#about to read 3, iclass 39, count 0 2006.260.08:01:29.68#ibcon#read 3, iclass 39, count 0 2006.260.08:01:29.68#ibcon#about to read 4, iclass 39, count 0 2006.260.08:01:29.68#ibcon#read 4, iclass 39, count 0 2006.260.08:01:29.68#ibcon#about to read 5, iclass 39, count 0 2006.260.08:01:29.68#ibcon#read 5, iclass 39, count 0 2006.260.08:01:29.68#ibcon#about to read 6, iclass 39, count 0 2006.260.08:01:29.68#ibcon#read 6, iclass 39, count 0 2006.260.08:01:29.68#ibcon#end of sib2, iclass 39, count 0 2006.260.08:01:29.68#ibcon#*after write, iclass 39, count 0 2006.260.08:01:29.68#ibcon#*before return 0, iclass 39, count 0 2006.260.08:01:29.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:29.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:29.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:01:29.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:01:29.68$vc4f8/va=3,8 2006.260.08:01:29.68#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.08:01:29.68#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.08:01:29.68#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:29.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:29.74#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:29.74#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:29.74#ibcon#enter wrdev, iclass 3, count 2 2006.260.08:01:29.74#ibcon#first serial, iclass 3, count 2 2006.260.08:01:29.74#ibcon#enter sib2, iclass 3, count 2 2006.260.08:01:29.74#ibcon#flushed, iclass 3, count 2 2006.260.08:01:29.74#ibcon#about to write, iclass 3, count 2 2006.260.08:01:29.74#ibcon#wrote, iclass 3, count 2 2006.260.08:01:29.74#ibcon#about to read 3, iclass 3, count 2 2006.260.08:01:29.77#ibcon#read 3, iclass 3, count 2 2006.260.08:01:29.77#ibcon#about to read 4, iclass 3, count 2 2006.260.08:01:29.77#ibcon#read 4, iclass 3, count 2 2006.260.08:01:29.77#ibcon#about to read 5, iclass 3, count 2 2006.260.08:01:29.77#ibcon#read 5, iclass 3, count 2 2006.260.08:01:29.77#ibcon#about to read 6, iclass 3, count 2 2006.260.08:01:29.77#ibcon#read 6, iclass 3, count 2 2006.260.08:01:29.77#ibcon#end of sib2, iclass 3, count 2 2006.260.08:01:29.77#ibcon#*mode == 0, iclass 3, count 2 2006.260.08:01:29.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.08:01:29.77#ibcon#[25=AT03-08\r\n] 2006.260.08:01:29.77#ibcon#*before write, iclass 3, count 2 2006.260.08:01:29.77#ibcon#enter sib2, iclass 3, count 2 2006.260.08:01:29.77#ibcon#flushed, iclass 3, count 2 2006.260.08:01:29.77#ibcon#about to write, iclass 3, count 2 2006.260.08:01:29.77#ibcon#wrote, iclass 3, count 2 2006.260.08:01:29.77#ibcon#about to read 3, iclass 3, count 2 2006.260.08:01:29.80#ibcon#read 3, iclass 3, count 2 2006.260.08:01:29.80#ibcon#about to read 4, iclass 3, count 2 2006.260.08:01:29.80#ibcon#read 4, iclass 3, count 2 2006.260.08:01:29.80#ibcon#about to read 5, iclass 3, count 2 2006.260.08:01:29.80#ibcon#read 5, iclass 3, count 2 2006.260.08:01:29.80#ibcon#about to read 6, iclass 3, count 2 2006.260.08:01:29.80#ibcon#read 6, iclass 3, count 2 2006.260.08:01:29.80#ibcon#end of sib2, iclass 3, count 2 2006.260.08:01:29.80#ibcon#*after write, iclass 3, count 2 2006.260.08:01:29.80#ibcon#*before return 0, iclass 3, count 2 2006.260.08:01:29.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:29.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:29.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.08:01:29.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:29.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:29.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:29.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:29.92#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:01:29.92#ibcon#first serial, iclass 3, count 0 2006.260.08:01:29.92#ibcon#enter sib2, iclass 3, count 0 2006.260.08:01:29.92#ibcon#flushed, iclass 3, count 0 2006.260.08:01:29.92#ibcon#about to write, iclass 3, count 0 2006.260.08:01:29.92#ibcon#wrote, iclass 3, count 0 2006.260.08:01:29.92#ibcon#about to read 3, iclass 3, count 0 2006.260.08:01:29.94#ibcon#read 3, iclass 3, count 0 2006.260.08:01:29.94#ibcon#about to read 4, iclass 3, count 0 2006.260.08:01:29.94#ibcon#read 4, iclass 3, count 0 2006.260.08:01:29.94#ibcon#about to read 5, iclass 3, count 0 2006.260.08:01:29.94#ibcon#read 5, iclass 3, count 0 2006.260.08:01:29.94#ibcon#about to read 6, iclass 3, count 0 2006.260.08:01:29.94#ibcon#read 6, iclass 3, count 0 2006.260.08:01:29.94#ibcon#end of sib2, iclass 3, count 0 2006.260.08:01:29.94#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:01:29.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:01:29.94#ibcon#[25=USB\r\n] 2006.260.08:01:29.94#ibcon#*before write, iclass 3, count 0 2006.260.08:01:29.94#ibcon#enter sib2, iclass 3, count 0 2006.260.08:01:29.94#ibcon#flushed, iclass 3, count 0 2006.260.08:01:29.94#ibcon#about to write, iclass 3, count 0 2006.260.08:01:29.94#ibcon#wrote, iclass 3, count 0 2006.260.08:01:29.94#ibcon#about to read 3, iclass 3, count 0 2006.260.08:01:29.97#ibcon#read 3, iclass 3, count 0 2006.260.08:01:29.97#ibcon#about to read 4, iclass 3, count 0 2006.260.08:01:29.97#ibcon#read 4, iclass 3, count 0 2006.260.08:01:29.97#ibcon#about to read 5, iclass 3, count 0 2006.260.08:01:29.97#ibcon#read 5, iclass 3, count 0 2006.260.08:01:29.97#ibcon#about to read 6, iclass 3, count 0 2006.260.08:01:29.97#ibcon#read 6, iclass 3, count 0 2006.260.08:01:29.97#ibcon#end of sib2, iclass 3, count 0 2006.260.08:01:29.97#ibcon#*after write, iclass 3, count 0 2006.260.08:01:29.97#ibcon#*before return 0, iclass 3, count 0 2006.260.08:01:29.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:29.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:29.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:01:29.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:01:29.97$vc4f8/valo=4,832.99 2006.260.08:01:29.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:01:29.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:01:29.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:29.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:29.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:29.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:29.97#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:01:29.97#ibcon#first serial, iclass 5, count 0 2006.260.08:01:29.97#ibcon#enter sib2, iclass 5, count 0 2006.260.08:01:29.97#ibcon#flushed, iclass 5, count 0 2006.260.08:01:29.97#ibcon#about to write, iclass 5, count 0 2006.260.08:01:29.97#ibcon#wrote, iclass 5, count 0 2006.260.08:01:29.97#ibcon#about to read 3, iclass 5, count 0 2006.260.08:01:29.99#ibcon#read 3, iclass 5, count 0 2006.260.08:01:29.99#ibcon#about to read 4, iclass 5, count 0 2006.260.08:01:29.99#ibcon#read 4, iclass 5, count 0 2006.260.08:01:29.99#ibcon#about to read 5, iclass 5, count 0 2006.260.08:01:29.99#ibcon#read 5, iclass 5, count 0 2006.260.08:01:29.99#ibcon#about to read 6, iclass 5, count 0 2006.260.08:01:29.99#ibcon#read 6, iclass 5, count 0 2006.260.08:01:29.99#ibcon#end of sib2, iclass 5, count 0 2006.260.08:01:29.99#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:01:29.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:01:29.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:01:29.99#ibcon#*before write, iclass 5, count 0 2006.260.08:01:29.99#ibcon#enter sib2, iclass 5, count 0 2006.260.08:01:29.99#ibcon#flushed, iclass 5, count 0 2006.260.08:01:29.99#ibcon#about to write, iclass 5, count 0 2006.260.08:01:29.99#ibcon#wrote, iclass 5, count 0 2006.260.08:01:29.99#ibcon#about to read 3, iclass 5, count 0 2006.260.08:01:30.03#ibcon#read 3, iclass 5, count 0 2006.260.08:01:30.03#ibcon#about to read 4, iclass 5, count 0 2006.260.08:01:30.03#ibcon#read 4, iclass 5, count 0 2006.260.08:01:30.03#ibcon#about to read 5, iclass 5, count 0 2006.260.08:01:30.03#ibcon#read 5, iclass 5, count 0 2006.260.08:01:30.03#ibcon#about to read 6, iclass 5, count 0 2006.260.08:01:30.03#ibcon#read 6, iclass 5, count 0 2006.260.08:01:30.03#ibcon#end of sib2, iclass 5, count 0 2006.260.08:01:30.03#ibcon#*after write, iclass 5, count 0 2006.260.08:01:30.03#ibcon#*before return 0, iclass 5, count 0 2006.260.08:01:30.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:30.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:30.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:01:30.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:01:30.03$vc4f8/va=4,7 2006.260.08:01:30.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:01:30.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:01:30.03#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:30.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:30.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:30.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:30.09#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:01:30.09#ibcon#first serial, iclass 7, count 2 2006.260.08:01:30.09#ibcon#enter sib2, iclass 7, count 2 2006.260.08:01:30.09#ibcon#flushed, iclass 7, count 2 2006.260.08:01:30.09#ibcon#about to write, iclass 7, count 2 2006.260.08:01:30.09#ibcon#wrote, iclass 7, count 2 2006.260.08:01:30.09#ibcon#about to read 3, iclass 7, count 2 2006.260.08:01:30.11#ibcon#read 3, iclass 7, count 2 2006.260.08:01:30.11#ibcon#about to read 4, iclass 7, count 2 2006.260.08:01:30.11#ibcon#read 4, iclass 7, count 2 2006.260.08:01:30.11#ibcon#about to read 5, iclass 7, count 2 2006.260.08:01:30.11#ibcon#read 5, iclass 7, count 2 2006.260.08:01:30.11#ibcon#about to read 6, iclass 7, count 2 2006.260.08:01:30.11#ibcon#read 6, iclass 7, count 2 2006.260.08:01:30.11#ibcon#end of sib2, iclass 7, count 2 2006.260.08:01:30.11#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:01:30.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:01:30.11#ibcon#[25=AT04-07\r\n] 2006.260.08:01:30.11#ibcon#*before write, iclass 7, count 2 2006.260.08:01:30.11#ibcon#enter sib2, iclass 7, count 2 2006.260.08:01:30.11#ibcon#flushed, iclass 7, count 2 2006.260.08:01:30.11#ibcon#about to write, iclass 7, count 2 2006.260.08:01:30.11#ibcon#wrote, iclass 7, count 2 2006.260.08:01:30.11#ibcon#about to read 3, iclass 7, count 2 2006.260.08:01:30.14#ibcon#read 3, iclass 7, count 2 2006.260.08:01:30.14#ibcon#about to read 4, iclass 7, count 2 2006.260.08:01:30.14#ibcon#read 4, iclass 7, count 2 2006.260.08:01:30.14#ibcon#about to read 5, iclass 7, count 2 2006.260.08:01:30.14#ibcon#read 5, iclass 7, count 2 2006.260.08:01:30.14#ibcon#about to read 6, iclass 7, count 2 2006.260.08:01:30.14#ibcon#read 6, iclass 7, count 2 2006.260.08:01:30.14#ibcon#end of sib2, iclass 7, count 2 2006.260.08:01:30.14#ibcon#*after write, iclass 7, count 2 2006.260.08:01:30.14#ibcon#*before return 0, iclass 7, count 2 2006.260.08:01:30.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:30.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:30.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:01:30.14#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:30.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:30.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:30.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:30.26#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:01:30.26#ibcon#first serial, iclass 7, count 0 2006.260.08:01:30.26#ibcon#enter sib2, iclass 7, count 0 2006.260.08:01:30.26#ibcon#flushed, iclass 7, count 0 2006.260.08:01:30.26#ibcon#about to write, iclass 7, count 0 2006.260.08:01:30.26#ibcon#wrote, iclass 7, count 0 2006.260.08:01:30.26#ibcon#about to read 3, iclass 7, count 0 2006.260.08:01:30.28#ibcon#read 3, iclass 7, count 0 2006.260.08:01:30.28#ibcon#about to read 4, iclass 7, count 0 2006.260.08:01:30.28#ibcon#read 4, iclass 7, count 0 2006.260.08:01:30.28#ibcon#about to read 5, iclass 7, count 0 2006.260.08:01:30.28#ibcon#read 5, iclass 7, count 0 2006.260.08:01:30.28#ibcon#about to read 6, iclass 7, count 0 2006.260.08:01:30.28#ibcon#read 6, iclass 7, count 0 2006.260.08:01:30.28#ibcon#end of sib2, iclass 7, count 0 2006.260.08:01:30.28#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:01:30.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:01:30.28#ibcon#[25=USB\r\n] 2006.260.08:01:30.28#ibcon#*before write, iclass 7, count 0 2006.260.08:01:30.28#ibcon#enter sib2, iclass 7, count 0 2006.260.08:01:30.28#ibcon#flushed, iclass 7, count 0 2006.260.08:01:30.28#ibcon#about to write, iclass 7, count 0 2006.260.08:01:30.28#ibcon#wrote, iclass 7, count 0 2006.260.08:01:30.28#ibcon#about to read 3, iclass 7, count 0 2006.260.08:01:30.31#ibcon#read 3, iclass 7, count 0 2006.260.08:01:30.31#ibcon#about to read 4, iclass 7, count 0 2006.260.08:01:30.31#ibcon#read 4, iclass 7, count 0 2006.260.08:01:30.31#ibcon#about to read 5, iclass 7, count 0 2006.260.08:01:30.31#ibcon#read 5, iclass 7, count 0 2006.260.08:01:30.31#ibcon#about to read 6, iclass 7, count 0 2006.260.08:01:30.31#ibcon#read 6, iclass 7, count 0 2006.260.08:01:30.31#ibcon#end of sib2, iclass 7, count 0 2006.260.08:01:30.31#ibcon#*after write, iclass 7, count 0 2006.260.08:01:30.31#ibcon#*before return 0, iclass 7, count 0 2006.260.08:01:30.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:30.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:30.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:01:30.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:01:30.31$vc4f8/valo=5,652.99 2006.260.08:01:30.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:01:30.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:01:30.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:30.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:01:30.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:01:30.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:01:30.31#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:01:30.31#ibcon#first serial, iclass 11, count 0 2006.260.08:01:30.31#ibcon#enter sib2, iclass 11, count 0 2006.260.08:01:30.31#ibcon#flushed, iclass 11, count 0 2006.260.08:01:30.31#ibcon#about to write, iclass 11, count 0 2006.260.08:01:30.31#ibcon#wrote, iclass 11, count 0 2006.260.08:01:30.31#ibcon#about to read 3, iclass 11, count 0 2006.260.08:01:30.33#ibcon#read 3, iclass 11, count 0 2006.260.08:01:30.33#ibcon#about to read 4, iclass 11, count 0 2006.260.08:01:30.33#ibcon#read 4, iclass 11, count 0 2006.260.08:01:30.33#ibcon#about to read 5, iclass 11, count 0 2006.260.08:01:30.33#ibcon#read 5, iclass 11, count 0 2006.260.08:01:30.33#ibcon#about to read 6, iclass 11, count 0 2006.260.08:01:30.33#ibcon#read 6, iclass 11, count 0 2006.260.08:01:30.33#ibcon#end of sib2, iclass 11, count 0 2006.260.08:01:30.33#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:01:30.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:01:30.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:01:30.33#ibcon#*before write, iclass 11, count 0 2006.260.08:01:30.33#ibcon#enter sib2, iclass 11, count 0 2006.260.08:01:30.33#ibcon#flushed, iclass 11, count 0 2006.260.08:01:30.33#ibcon#about to write, iclass 11, count 0 2006.260.08:01:30.33#ibcon#wrote, iclass 11, count 0 2006.260.08:01:30.33#ibcon#about to read 3, iclass 11, count 0 2006.260.08:01:30.37#ibcon#read 3, iclass 11, count 0 2006.260.08:01:30.37#ibcon#about to read 4, iclass 11, count 0 2006.260.08:01:30.37#ibcon#read 4, iclass 11, count 0 2006.260.08:01:30.37#ibcon#about to read 5, iclass 11, count 0 2006.260.08:01:30.37#ibcon#read 5, iclass 11, count 0 2006.260.08:01:30.37#ibcon#about to read 6, iclass 11, count 0 2006.260.08:01:30.37#ibcon#read 6, iclass 11, count 0 2006.260.08:01:30.37#ibcon#end of sib2, iclass 11, count 0 2006.260.08:01:30.37#ibcon#*after write, iclass 11, count 0 2006.260.08:01:30.37#ibcon#*before return 0, iclass 11, count 0 2006.260.08:01:30.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:01:30.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:01:30.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:01:30.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:01:30.37$vc4f8/va=5,7 2006.260.08:01:30.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.08:01:30.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.08:01:30.37#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:30.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:01:30.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:01:30.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:01:30.43#ibcon#enter wrdev, iclass 13, count 2 2006.260.08:01:30.43#ibcon#first serial, iclass 13, count 2 2006.260.08:01:30.43#ibcon#enter sib2, iclass 13, count 2 2006.260.08:01:30.43#ibcon#flushed, iclass 13, count 2 2006.260.08:01:30.43#ibcon#about to write, iclass 13, count 2 2006.260.08:01:30.43#ibcon#wrote, iclass 13, count 2 2006.260.08:01:30.43#ibcon#about to read 3, iclass 13, count 2 2006.260.08:01:30.45#ibcon#read 3, iclass 13, count 2 2006.260.08:01:30.45#ibcon#about to read 4, iclass 13, count 2 2006.260.08:01:30.45#ibcon#read 4, iclass 13, count 2 2006.260.08:01:30.45#ibcon#about to read 5, iclass 13, count 2 2006.260.08:01:30.45#ibcon#read 5, iclass 13, count 2 2006.260.08:01:30.45#ibcon#about to read 6, iclass 13, count 2 2006.260.08:01:30.45#ibcon#read 6, iclass 13, count 2 2006.260.08:01:30.45#ibcon#end of sib2, iclass 13, count 2 2006.260.08:01:30.45#ibcon#*mode == 0, iclass 13, count 2 2006.260.08:01:30.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.08:01:30.45#ibcon#[25=AT05-07\r\n] 2006.260.08:01:30.45#ibcon#*before write, iclass 13, count 2 2006.260.08:01:30.45#ibcon#enter sib2, iclass 13, count 2 2006.260.08:01:30.45#ibcon#flushed, iclass 13, count 2 2006.260.08:01:30.45#ibcon#about to write, iclass 13, count 2 2006.260.08:01:30.45#ibcon#wrote, iclass 13, count 2 2006.260.08:01:30.45#ibcon#about to read 3, iclass 13, count 2 2006.260.08:01:30.48#ibcon#read 3, iclass 13, count 2 2006.260.08:01:30.48#ibcon#about to read 4, iclass 13, count 2 2006.260.08:01:30.48#ibcon#read 4, iclass 13, count 2 2006.260.08:01:30.48#ibcon#about to read 5, iclass 13, count 2 2006.260.08:01:30.48#ibcon#read 5, iclass 13, count 2 2006.260.08:01:30.48#ibcon#about to read 6, iclass 13, count 2 2006.260.08:01:30.48#ibcon#read 6, iclass 13, count 2 2006.260.08:01:30.48#ibcon#end of sib2, iclass 13, count 2 2006.260.08:01:30.48#ibcon#*after write, iclass 13, count 2 2006.260.08:01:30.48#ibcon#*before return 0, iclass 13, count 2 2006.260.08:01:30.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:01:30.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:01:30.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.08:01:30.48#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:30.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:01:30.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:01:30.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:01:30.60#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:01:30.60#ibcon#first serial, iclass 13, count 0 2006.260.08:01:30.60#ibcon#enter sib2, iclass 13, count 0 2006.260.08:01:30.60#ibcon#flushed, iclass 13, count 0 2006.260.08:01:30.60#ibcon#about to write, iclass 13, count 0 2006.260.08:01:30.60#ibcon#wrote, iclass 13, count 0 2006.260.08:01:30.60#ibcon#about to read 3, iclass 13, count 0 2006.260.08:01:30.62#ibcon#read 3, iclass 13, count 0 2006.260.08:01:30.62#ibcon#about to read 4, iclass 13, count 0 2006.260.08:01:30.62#ibcon#read 4, iclass 13, count 0 2006.260.08:01:30.62#ibcon#about to read 5, iclass 13, count 0 2006.260.08:01:30.62#ibcon#read 5, iclass 13, count 0 2006.260.08:01:30.62#ibcon#about to read 6, iclass 13, count 0 2006.260.08:01:30.62#ibcon#read 6, iclass 13, count 0 2006.260.08:01:30.62#ibcon#end of sib2, iclass 13, count 0 2006.260.08:01:30.62#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:01:30.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:01:30.62#ibcon#[25=USB\r\n] 2006.260.08:01:30.62#ibcon#*before write, iclass 13, count 0 2006.260.08:01:30.62#ibcon#enter sib2, iclass 13, count 0 2006.260.08:01:30.62#ibcon#flushed, iclass 13, count 0 2006.260.08:01:30.62#ibcon#about to write, iclass 13, count 0 2006.260.08:01:30.62#ibcon#wrote, iclass 13, count 0 2006.260.08:01:30.62#ibcon#about to read 3, iclass 13, count 0 2006.260.08:01:30.65#ibcon#read 3, iclass 13, count 0 2006.260.08:01:30.65#ibcon#about to read 4, iclass 13, count 0 2006.260.08:01:30.65#ibcon#read 4, iclass 13, count 0 2006.260.08:01:30.65#ibcon#about to read 5, iclass 13, count 0 2006.260.08:01:30.65#ibcon#read 5, iclass 13, count 0 2006.260.08:01:30.65#ibcon#about to read 6, iclass 13, count 0 2006.260.08:01:30.65#ibcon#read 6, iclass 13, count 0 2006.260.08:01:30.65#ibcon#end of sib2, iclass 13, count 0 2006.260.08:01:30.65#ibcon#*after write, iclass 13, count 0 2006.260.08:01:30.65#ibcon#*before return 0, iclass 13, count 0 2006.260.08:01:30.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:01:30.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:01:30.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:01:30.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:01:30.65$vc4f8/valo=6,772.99 2006.260.08:01:30.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:01:30.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:01:30.65#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:30.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:30.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:30.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:30.65#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:01:30.65#ibcon#first serial, iclass 15, count 0 2006.260.08:01:30.65#ibcon#enter sib2, iclass 15, count 0 2006.260.08:01:30.65#ibcon#flushed, iclass 15, count 0 2006.260.08:01:30.65#ibcon#about to write, iclass 15, count 0 2006.260.08:01:30.65#ibcon#wrote, iclass 15, count 0 2006.260.08:01:30.65#ibcon#about to read 3, iclass 15, count 0 2006.260.08:01:30.67#ibcon#read 3, iclass 15, count 0 2006.260.08:01:30.67#ibcon#about to read 4, iclass 15, count 0 2006.260.08:01:30.67#ibcon#read 4, iclass 15, count 0 2006.260.08:01:30.67#ibcon#about to read 5, iclass 15, count 0 2006.260.08:01:30.67#ibcon#read 5, iclass 15, count 0 2006.260.08:01:30.67#ibcon#about to read 6, iclass 15, count 0 2006.260.08:01:30.67#ibcon#read 6, iclass 15, count 0 2006.260.08:01:30.67#ibcon#end of sib2, iclass 15, count 0 2006.260.08:01:30.67#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:01:30.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:01:30.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:01:30.67#ibcon#*before write, iclass 15, count 0 2006.260.08:01:30.67#ibcon#enter sib2, iclass 15, count 0 2006.260.08:01:30.67#ibcon#flushed, iclass 15, count 0 2006.260.08:01:30.67#ibcon#about to write, iclass 15, count 0 2006.260.08:01:30.67#ibcon#wrote, iclass 15, count 0 2006.260.08:01:30.67#ibcon#about to read 3, iclass 15, count 0 2006.260.08:01:30.71#ibcon#read 3, iclass 15, count 0 2006.260.08:01:30.71#ibcon#about to read 4, iclass 15, count 0 2006.260.08:01:30.71#ibcon#read 4, iclass 15, count 0 2006.260.08:01:30.71#ibcon#about to read 5, iclass 15, count 0 2006.260.08:01:30.71#ibcon#read 5, iclass 15, count 0 2006.260.08:01:30.71#ibcon#about to read 6, iclass 15, count 0 2006.260.08:01:30.71#ibcon#read 6, iclass 15, count 0 2006.260.08:01:30.71#ibcon#end of sib2, iclass 15, count 0 2006.260.08:01:30.71#ibcon#*after write, iclass 15, count 0 2006.260.08:01:30.71#ibcon#*before return 0, iclass 15, count 0 2006.260.08:01:30.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:30.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:30.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:01:30.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:01:30.71$vc4f8/va=6,6 2006.260.08:01:30.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:01:30.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:01:30.71#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:30.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:30.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:30.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:30.77#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:01:30.77#ibcon#first serial, iclass 17, count 2 2006.260.08:01:30.77#ibcon#enter sib2, iclass 17, count 2 2006.260.08:01:30.77#ibcon#flushed, iclass 17, count 2 2006.260.08:01:30.77#ibcon#about to write, iclass 17, count 2 2006.260.08:01:30.77#ibcon#wrote, iclass 17, count 2 2006.260.08:01:30.77#ibcon#about to read 3, iclass 17, count 2 2006.260.08:01:30.79#ibcon#read 3, iclass 17, count 2 2006.260.08:01:30.79#ibcon#about to read 4, iclass 17, count 2 2006.260.08:01:30.79#ibcon#read 4, iclass 17, count 2 2006.260.08:01:30.79#ibcon#about to read 5, iclass 17, count 2 2006.260.08:01:30.79#ibcon#read 5, iclass 17, count 2 2006.260.08:01:30.79#ibcon#about to read 6, iclass 17, count 2 2006.260.08:01:30.79#ibcon#read 6, iclass 17, count 2 2006.260.08:01:30.79#ibcon#end of sib2, iclass 17, count 2 2006.260.08:01:30.79#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:01:30.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:01:30.79#ibcon#[25=AT06-06\r\n] 2006.260.08:01:30.79#ibcon#*before write, iclass 17, count 2 2006.260.08:01:30.79#ibcon#enter sib2, iclass 17, count 2 2006.260.08:01:30.79#ibcon#flushed, iclass 17, count 2 2006.260.08:01:30.79#ibcon#about to write, iclass 17, count 2 2006.260.08:01:30.79#ibcon#wrote, iclass 17, count 2 2006.260.08:01:30.79#ibcon#about to read 3, iclass 17, count 2 2006.260.08:01:30.82#ibcon#read 3, iclass 17, count 2 2006.260.08:01:30.82#ibcon#about to read 4, iclass 17, count 2 2006.260.08:01:30.82#ibcon#read 4, iclass 17, count 2 2006.260.08:01:30.82#ibcon#about to read 5, iclass 17, count 2 2006.260.08:01:30.82#ibcon#read 5, iclass 17, count 2 2006.260.08:01:30.82#ibcon#about to read 6, iclass 17, count 2 2006.260.08:01:30.82#ibcon#read 6, iclass 17, count 2 2006.260.08:01:30.82#ibcon#end of sib2, iclass 17, count 2 2006.260.08:01:30.82#ibcon#*after write, iclass 17, count 2 2006.260.08:01:30.82#ibcon#*before return 0, iclass 17, count 2 2006.260.08:01:30.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:30.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:30.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:01:30.82#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:30.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:30.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:30.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:30.94#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:01:30.94#ibcon#first serial, iclass 17, count 0 2006.260.08:01:30.94#ibcon#enter sib2, iclass 17, count 0 2006.260.08:01:30.94#ibcon#flushed, iclass 17, count 0 2006.260.08:01:30.94#ibcon#about to write, iclass 17, count 0 2006.260.08:01:30.94#ibcon#wrote, iclass 17, count 0 2006.260.08:01:30.94#ibcon#about to read 3, iclass 17, count 0 2006.260.08:01:30.96#ibcon#read 3, iclass 17, count 0 2006.260.08:01:30.96#ibcon#about to read 4, iclass 17, count 0 2006.260.08:01:30.96#ibcon#read 4, iclass 17, count 0 2006.260.08:01:30.96#ibcon#about to read 5, iclass 17, count 0 2006.260.08:01:30.96#ibcon#read 5, iclass 17, count 0 2006.260.08:01:30.96#ibcon#about to read 6, iclass 17, count 0 2006.260.08:01:30.96#ibcon#read 6, iclass 17, count 0 2006.260.08:01:30.96#ibcon#end of sib2, iclass 17, count 0 2006.260.08:01:30.96#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:01:30.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:01:30.96#ibcon#[25=USB\r\n] 2006.260.08:01:30.96#ibcon#*before write, iclass 17, count 0 2006.260.08:01:30.96#ibcon#enter sib2, iclass 17, count 0 2006.260.08:01:30.96#ibcon#flushed, iclass 17, count 0 2006.260.08:01:30.96#ibcon#about to write, iclass 17, count 0 2006.260.08:01:30.96#ibcon#wrote, iclass 17, count 0 2006.260.08:01:30.96#ibcon#about to read 3, iclass 17, count 0 2006.260.08:01:30.99#ibcon#read 3, iclass 17, count 0 2006.260.08:01:30.99#ibcon#about to read 4, iclass 17, count 0 2006.260.08:01:30.99#ibcon#read 4, iclass 17, count 0 2006.260.08:01:30.99#ibcon#about to read 5, iclass 17, count 0 2006.260.08:01:30.99#ibcon#read 5, iclass 17, count 0 2006.260.08:01:30.99#ibcon#about to read 6, iclass 17, count 0 2006.260.08:01:30.99#ibcon#read 6, iclass 17, count 0 2006.260.08:01:30.99#ibcon#end of sib2, iclass 17, count 0 2006.260.08:01:30.99#ibcon#*after write, iclass 17, count 0 2006.260.08:01:30.99#ibcon#*before return 0, iclass 17, count 0 2006.260.08:01:30.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:30.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:30.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:01:30.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:01:30.99$vc4f8/valo=7,832.99 2006.260.08:01:30.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:01:30.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:01:30.99#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:30.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:30.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:30.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:30.99#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:01:30.99#ibcon#first serial, iclass 19, count 0 2006.260.08:01:30.99#ibcon#enter sib2, iclass 19, count 0 2006.260.08:01:30.99#ibcon#flushed, iclass 19, count 0 2006.260.08:01:30.99#ibcon#about to write, iclass 19, count 0 2006.260.08:01:30.99#ibcon#wrote, iclass 19, count 0 2006.260.08:01:30.99#ibcon#about to read 3, iclass 19, count 0 2006.260.08:01:31.01#ibcon#read 3, iclass 19, count 0 2006.260.08:01:31.01#ibcon#about to read 4, iclass 19, count 0 2006.260.08:01:31.01#ibcon#read 4, iclass 19, count 0 2006.260.08:01:31.01#ibcon#about to read 5, iclass 19, count 0 2006.260.08:01:31.01#ibcon#read 5, iclass 19, count 0 2006.260.08:01:31.01#ibcon#about to read 6, iclass 19, count 0 2006.260.08:01:31.01#ibcon#read 6, iclass 19, count 0 2006.260.08:01:31.01#ibcon#end of sib2, iclass 19, count 0 2006.260.08:01:31.01#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:01:31.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:01:31.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:01:31.01#ibcon#*before write, iclass 19, count 0 2006.260.08:01:31.01#ibcon#enter sib2, iclass 19, count 0 2006.260.08:01:31.01#ibcon#flushed, iclass 19, count 0 2006.260.08:01:31.01#ibcon#about to write, iclass 19, count 0 2006.260.08:01:31.01#ibcon#wrote, iclass 19, count 0 2006.260.08:01:31.01#ibcon#about to read 3, iclass 19, count 0 2006.260.08:01:31.05#ibcon#read 3, iclass 19, count 0 2006.260.08:01:31.05#ibcon#about to read 4, iclass 19, count 0 2006.260.08:01:31.05#ibcon#read 4, iclass 19, count 0 2006.260.08:01:31.05#ibcon#about to read 5, iclass 19, count 0 2006.260.08:01:31.05#ibcon#read 5, iclass 19, count 0 2006.260.08:01:31.05#ibcon#about to read 6, iclass 19, count 0 2006.260.08:01:31.05#ibcon#read 6, iclass 19, count 0 2006.260.08:01:31.05#ibcon#end of sib2, iclass 19, count 0 2006.260.08:01:31.05#ibcon#*after write, iclass 19, count 0 2006.260.08:01:31.05#ibcon#*before return 0, iclass 19, count 0 2006.260.08:01:31.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:31.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:31.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:01:31.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:01:31.05$vc4f8/va=7,6 2006.260.08:01:31.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.08:01:31.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.08:01:31.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:31.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:31.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:31.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:31.11#ibcon#enter wrdev, iclass 21, count 2 2006.260.08:01:31.11#ibcon#first serial, iclass 21, count 2 2006.260.08:01:31.11#ibcon#enter sib2, iclass 21, count 2 2006.260.08:01:31.11#ibcon#flushed, iclass 21, count 2 2006.260.08:01:31.11#ibcon#about to write, iclass 21, count 2 2006.260.08:01:31.11#ibcon#wrote, iclass 21, count 2 2006.260.08:01:31.11#ibcon#about to read 3, iclass 21, count 2 2006.260.08:01:31.13#ibcon#read 3, iclass 21, count 2 2006.260.08:01:31.13#ibcon#about to read 4, iclass 21, count 2 2006.260.08:01:31.13#ibcon#read 4, iclass 21, count 2 2006.260.08:01:31.13#ibcon#about to read 5, iclass 21, count 2 2006.260.08:01:31.13#ibcon#read 5, iclass 21, count 2 2006.260.08:01:31.13#ibcon#about to read 6, iclass 21, count 2 2006.260.08:01:31.13#ibcon#read 6, iclass 21, count 2 2006.260.08:01:31.13#ibcon#end of sib2, iclass 21, count 2 2006.260.08:01:31.13#ibcon#*mode == 0, iclass 21, count 2 2006.260.08:01:31.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.08:01:31.13#ibcon#[25=AT07-06\r\n] 2006.260.08:01:31.13#ibcon#*before write, iclass 21, count 2 2006.260.08:01:31.13#ibcon#enter sib2, iclass 21, count 2 2006.260.08:01:31.13#ibcon#flushed, iclass 21, count 2 2006.260.08:01:31.13#ibcon#about to write, iclass 21, count 2 2006.260.08:01:31.13#ibcon#wrote, iclass 21, count 2 2006.260.08:01:31.13#ibcon#about to read 3, iclass 21, count 2 2006.260.08:01:31.16#ibcon#read 3, iclass 21, count 2 2006.260.08:01:31.16#ibcon#about to read 4, iclass 21, count 2 2006.260.08:01:31.16#ibcon#read 4, iclass 21, count 2 2006.260.08:01:31.16#ibcon#about to read 5, iclass 21, count 2 2006.260.08:01:31.16#ibcon#read 5, iclass 21, count 2 2006.260.08:01:31.16#ibcon#about to read 6, iclass 21, count 2 2006.260.08:01:31.16#ibcon#read 6, iclass 21, count 2 2006.260.08:01:31.16#ibcon#end of sib2, iclass 21, count 2 2006.260.08:01:31.16#ibcon#*after write, iclass 21, count 2 2006.260.08:01:31.16#ibcon#*before return 0, iclass 21, count 2 2006.260.08:01:31.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:31.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:31.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.08:01:31.16#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:31.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:01:31.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:01:31.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:01:31.28#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:01:31.28#ibcon#first serial, iclass 21, count 0 2006.260.08:01:31.28#ibcon#enter sib2, iclass 21, count 0 2006.260.08:01:31.28#ibcon#flushed, iclass 21, count 0 2006.260.08:01:31.28#ibcon#about to write, iclass 21, count 0 2006.260.08:01:31.28#ibcon#wrote, iclass 21, count 0 2006.260.08:01:31.28#ibcon#about to read 3, iclass 21, count 0 2006.260.08:01:31.30#ibcon#read 3, iclass 21, count 0 2006.260.08:01:31.30#ibcon#about to read 4, iclass 21, count 0 2006.260.08:01:31.30#ibcon#read 4, iclass 21, count 0 2006.260.08:01:31.30#ibcon#about to read 5, iclass 21, count 0 2006.260.08:01:31.30#ibcon#read 5, iclass 21, count 0 2006.260.08:01:31.30#ibcon#about to read 6, iclass 21, count 0 2006.260.08:01:31.30#ibcon#read 6, iclass 21, count 0 2006.260.08:01:31.30#ibcon#end of sib2, iclass 21, count 0 2006.260.08:01:31.30#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:01:31.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:01:31.30#ibcon#[25=USB\r\n] 2006.260.08:01:31.30#ibcon#*before write, iclass 21, count 0 2006.260.08:01:31.30#ibcon#enter sib2, iclass 21, count 0 2006.260.08:01:31.30#ibcon#flushed, iclass 21, count 0 2006.260.08:01:31.30#ibcon#about to write, iclass 21, count 0 2006.260.08:01:31.30#ibcon#wrote, iclass 21, count 0 2006.260.08:01:31.30#ibcon#about to read 3, iclass 21, count 0 2006.260.08:01:31.33#ibcon#read 3, iclass 21, count 0 2006.260.08:01:31.33#ibcon#about to read 4, iclass 21, count 0 2006.260.08:01:31.33#ibcon#read 4, iclass 21, count 0 2006.260.08:01:31.33#ibcon#about to read 5, iclass 21, count 0 2006.260.08:01:31.33#ibcon#read 5, iclass 21, count 0 2006.260.08:01:31.33#ibcon#about to read 6, iclass 21, count 0 2006.260.08:01:31.33#ibcon#read 6, iclass 21, count 0 2006.260.08:01:31.33#ibcon#end of sib2, iclass 21, count 0 2006.260.08:01:31.33#ibcon#*after write, iclass 21, count 0 2006.260.08:01:31.33#ibcon#*before return 0, iclass 21, count 0 2006.260.08:01:31.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:01:31.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:01:31.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:01:31.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:01:31.33$vc4f8/valo=8,852.99 2006.260.08:01:31.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.08:01:31.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.08:01:31.33#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:31.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:01:31.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:01:31.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:01:31.33#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:01:31.33#ibcon#first serial, iclass 23, count 0 2006.260.08:01:31.33#ibcon#enter sib2, iclass 23, count 0 2006.260.08:01:31.33#ibcon#flushed, iclass 23, count 0 2006.260.08:01:31.33#ibcon#about to write, iclass 23, count 0 2006.260.08:01:31.33#ibcon#wrote, iclass 23, count 0 2006.260.08:01:31.33#ibcon#about to read 3, iclass 23, count 0 2006.260.08:01:31.35#ibcon#read 3, iclass 23, count 0 2006.260.08:01:31.35#ibcon#about to read 4, iclass 23, count 0 2006.260.08:01:31.35#ibcon#read 4, iclass 23, count 0 2006.260.08:01:31.35#ibcon#about to read 5, iclass 23, count 0 2006.260.08:01:31.35#ibcon#read 5, iclass 23, count 0 2006.260.08:01:31.35#ibcon#about to read 6, iclass 23, count 0 2006.260.08:01:31.35#ibcon#read 6, iclass 23, count 0 2006.260.08:01:31.35#ibcon#end of sib2, iclass 23, count 0 2006.260.08:01:31.35#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:01:31.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:01:31.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:01:31.35#ibcon#*before write, iclass 23, count 0 2006.260.08:01:31.35#ibcon#enter sib2, iclass 23, count 0 2006.260.08:01:31.35#ibcon#flushed, iclass 23, count 0 2006.260.08:01:31.35#ibcon#about to write, iclass 23, count 0 2006.260.08:01:31.35#ibcon#wrote, iclass 23, count 0 2006.260.08:01:31.35#ibcon#about to read 3, iclass 23, count 0 2006.260.08:01:31.39#ibcon#read 3, iclass 23, count 0 2006.260.08:01:31.39#ibcon#about to read 4, iclass 23, count 0 2006.260.08:01:31.39#ibcon#read 4, iclass 23, count 0 2006.260.08:01:31.39#ibcon#about to read 5, iclass 23, count 0 2006.260.08:01:31.39#ibcon#read 5, iclass 23, count 0 2006.260.08:01:31.39#ibcon#about to read 6, iclass 23, count 0 2006.260.08:01:31.39#ibcon#read 6, iclass 23, count 0 2006.260.08:01:31.39#ibcon#end of sib2, iclass 23, count 0 2006.260.08:01:31.39#ibcon#*after write, iclass 23, count 0 2006.260.08:01:31.39#ibcon#*before return 0, iclass 23, count 0 2006.260.08:01:31.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:01:31.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:01:31.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:01:31.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:01:31.39$vc4f8/va=8,6 2006.260.08:01:31.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.08:01:31.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.08:01:31.39#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:31.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:01:31.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:01:31.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:01:31.45#ibcon#enter wrdev, iclass 25, count 2 2006.260.08:01:31.45#ibcon#first serial, iclass 25, count 2 2006.260.08:01:31.45#ibcon#enter sib2, iclass 25, count 2 2006.260.08:01:31.45#ibcon#flushed, iclass 25, count 2 2006.260.08:01:31.45#ibcon#about to write, iclass 25, count 2 2006.260.08:01:31.45#ibcon#wrote, iclass 25, count 2 2006.260.08:01:31.45#ibcon#about to read 3, iclass 25, count 2 2006.260.08:01:31.47#ibcon#read 3, iclass 25, count 2 2006.260.08:01:31.47#ibcon#about to read 4, iclass 25, count 2 2006.260.08:01:31.47#ibcon#read 4, iclass 25, count 2 2006.260.08:01:31.47#ibcon#about to read 5, iclass 25, count 2 2006.260.08:01:31.47#ibcon#read 5, iclass 25, count 2 2006.260.08:01:31.47#ibcon#about to read 6, iclass 25, count 2 2006.260.08:01:31.47#ibcon#read 6, iclass 25, count 2 2006.260.08:01:31.47#ibcon#end of sib2, iclass 25, count 2 2006.260.08:01:31.47#ibcon#*mode == 0, iclass 25, count 2 2006.260.08:01:31.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.08:01:31.47#ibcon#[25=AT08-06\r\n] 2006.260.08:01:31.47#ibcon#*before write, iclass 25, count 2 2006.260.08:01:31.47#ibcon#enter sib2, iclass 25, count 2 2006.260.08:01:31.47#ibcon#flushed, iclass 25, count 2 2006.260.08:01:31.47#ibcon#about to write, iclass 25, count 2 2006.260.08:01:31.47#ibcon#wrote, iclass 25, count 2 2006.260.08:01:31.47#ibcon#about to read 3, iclass 25, count 2 2006.260.08:01:31.50#ibcon#read 3, iclass 25, count 2 2006.260.08:01:31.50#ibcon#about to read 4, iclass 25, count 2 2006.260.08:01:31.50#ibcon#read 4, iclass 25, count 2 2006.260.08:01:31.50#ibcon#about to read 5, iclass 25, count 2 2006.260.08:01:31.50#ibcon#read 5, iclass 25, count 2 2006.260.08:01:31.50#ibcon#about to read 6, iclass 25, count 2 2006.260.08:01:31.50#ibcon#read 6, iclass 25, count 2 2006.260.08:01:31.50#ibcon#end of sib2, iclass 25, count 2 2006.260.08:01:31.50#ibcon#*after write, iclass 25, count 2 2006.260.08:01:31.50#ibcon#*before return 0, iclass 25, count 2 2006.260.08:01:31.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:01:31.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:01:31.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.08:01:31.50#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:31.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:01:31.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:01:31.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:01:31.62#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:01:31.62#ibcon#first serial, iclass 25, count 0 2006.260.08:01:31.62#ibcon#enter sib2, iclass 25, count 0 2006.260.08:01:31.62#ibcon#flushed, iclass 25, count 0 2006.260.08:01:31.62#ibcon#about to write, iclass 25, count 0 2006.260.08:01:31.62#ibcon#wrote, iclass 25, count 0 2006.260.08:01:31.62#ibcon#about to read 3, iclass 25, count 0 2006.260.08:01:31.64#ibcon#read 3, iclass 25, count 0 2006.260.08:01:31.64#ibcon#about to read 4, iclass 25, count 0 2006.260.08:01:31.64#ibcon#read 4, iclass 25, count 0 2006.260.08:01:31.64#ibcon#about to read 5, iclass 25, count 0 2006.260.08:01:31.64#ibcon#read 5, iclass 25, count 0 2006.260.08:01:31.64#ibcon#about to read 6, iclass 25, count 0 2006.260.08:01:31.64#ibcon#read 6, iclass 25, count 0 2006.260.08:01:31.64#ibcon#end of sib2, iclass 25, count 0 2006.260.08:01:31.64#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:01:31.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:01:31.64#ibcon#[25=USB\r\n] 2006.260.08:01:31.64#ibcon#*before write, iclass 25, count 0 2006.260.08:01:31.64#ibcon#enter sib2, iclass 25, count 0 2006.260.08:01:31.64#ibcon#flushed, iclass 25, count 0 2006.260.08:01:31.64#ibcon#about to write, iclass 25, count 0 2006.260.08:01:31.64#ibcon#wrote, iclass 25, count 0 2006.260.08:01:31.64#ibcon#about to read 3, iclass 25, count 0 2006.260.08:01:31.67#ibcon#read 3, iclass 25, count 0 2006.260.08:01:31.67#ibcon#about to read 4, iclass 25, count 0 2006.260.08:01:31.67#ibcon#read 4, iclass 25, count 0 2006.260.08:01:31.67#ibcon#about to read 5, iclass 25, count 0 2006.260.08:01:31.67#ibcon#read 5, iclass 25, count 0 2006.260.08:01:31.67#ibcon#about to read 6, iclass 25, count 0 2006.260.08:01:31.67#ibcon#read 6, iclass 25, count 0 2006.260.08:01:31.67#ibcon#end of sib2, iclass 25, count 0 2006.260.08:01:31.67#ibcon#*after write, iclass 25, count 0 2006.260.08:01:31.67#ibcon#*before return 0, iclass 25, count 0 2006.260.08:01:31.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:01:31.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:01:31.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:01:31.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:01:31.67$vc4f8/vblo=1,632.99 2006.260.08:01:31.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.08:01:31.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.08:01:31.67#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:31.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:01:31.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:01:31.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:01:31.67#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:01:31.67#ibcon#first serial, iclass 27, count 0 2006.260.08:01:31.67#ibcon#enter sib2, iclass 27, count 0 2006.260.08:01:31.67#ibcon#flushed, iclass 27, count 0 2006.260.08:01:31.67#ibcon#about to write, iclass 27, count 0 2006.260.08:01:31.67#ibcon#wrote, iclass 27, count 0 2006.260.08:01:31.67#ibcon#about to read 3, iclass 27, count 0 2006.260.08:01:31.69#ibcon#read 3, iclass 27, count 0 2006.260.08:01:31.69#ibcon#about to read 4, iclass 27, count 0 2006.260.08:01:31.69#ibcon#read 4, iclass 27, count 0 2006.260.08:01:31.69#ibcon#about to read 5, iclass 27, count 0 2006.260.08:01:31.69#ibcon#read 5, iclass 27, count 0 2006.260.08:01:31.69#ibcon#about to read 6, iclass 27, count 0 2006.260.08:01:31.69#ibcon#read 6, iclass 27, count 0 2006.260.08:01:31.69#ibcon#end of sib2, iclass 27, count 0 2006.260.08:01:31.69#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:01:31.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:01:31.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:01:31.69#ibcon#*before write, iclass 27, count 0 2006.260.08:01:31.69#ibcon#enter sib2, iclass 27, count 0 2006.260.08:01:31.69#ibcon#flushed, iclass 27, count 0 2006.260.08:01:31.69#ibcon#about to write, iclass 27, count 0 2006.260.08:01:31.69#ibcon#wrote, iclass 27, count 0 2006.260.08:01:31.69#ibcon#about to read 3, iclass 27, count 0 2006.260.08:01:31.73#ibcon#read 3, iclass 27, count 0 2006.260.08:01:31.73#ibcon#about to read 4, iclass 27, count 0 2006.260.08:01:31.73#ibcon#read 4, iclass 27, count 0 2006.260.08:01:31.73#ibcon#about to read 5, iclass 27, count 0 2006.260.08:01:31.73#ibcon#read 5, iclass 27, count 0 2006.260.08:01:31.73#ibcon#about to read 6, iclass 27, count 0 2006.260.08:01:31.73#ibcon#read 6, iclass 27, count 0 2006.260.08:01:31.73#ibcon#end of sib2, iclass 27, count 0 2006.260.08:01:31.73#ibcon#*after write, iclass 27, count 0 2006.260.08:01:31.73#ibcon#*before return 0, iclass 27, count 0 2006.260.08:01:31.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:01:31.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:01:31.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:01:31.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:01:31.73$vc4f8/vb=1,4 2006.260.08:01:31.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.08:01:31.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.08:01:31.73#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:31.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:01:31.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:01:31.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:01:31.73#ibcon#enter wrdev, iclass 29, count 2 2006.260.08:01:31.73#ibcon#first serial, iclass 29, count 2 2006.260.08:01:31.73#ibcon#enter sib2, iclass 29, count 2 2006.260.08:01:31.73#ibcon#flushed, iclass 29, count 2 2006.260.08:01:31.73#ibcon#about to write, iclass 29, count 2 2006.260.08:01:31.73#ibcon#wrote, iclass 29, count 2 2006.260.08:01:31.73#ibcon#about to read 3, iclass 29, count 2 2006.260.08:01:31.75#ibcon#read 3, iclass 29, count 2 2006.260.08:01:31.75#ibcon#about to read 4, iclass 29, count 2 2006.260.08:01:31.75#ibcon#read 4, iclass 29, count 2 2006.260.08:01:31.75#ibcon#about to read 5, iclass 29, count 2 2006.260.08:01:31.75#ibcon#read 5, iclass 29, count 2 2006.260.08:01:31.75#ibcon#about to read 6, iclass 29, count 2 2006.260.08:01:31.75#ibcon#read 6, iclass 29, count 2 2006.260.08:01:31.75#ibcon#end of sib2, iclass 29, count 2 2006.260.08:01:31.75#ibcon#*mode == 0, iclass 29, count 2 2006.260.08:01:31.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.08:01:31.75#ibcon#[27=AT01-04\r\n] 2006.260.08:01:31.75#ibcon#*before write, iclass 29, count 2 2006.260.08:01:31.75#ibcon#enter sib2, iclass 29, count 2 2006.260.08:01:31.75#ibcon#flushed, iclass 29, count 2 2006.260.08:01:31.75#ibcon#about to write, iclass 29, count 2 2006.260.08:01:31.75#ibcon#wrote, iclass 29, count 2 2006.260.08:01:31.75#ibcon#about to read 3, iclass 29, count 2 2006.260.08:01:31.78#ibcon#read 3, iclass 29, count 2 2006.260.08:01:31.78#ibcon#about to read 4, iclass 29, count 2 2006.260.08:01:31.78#ibcon#read 4, iclass 29, count 2 2006.260.08:01:31.78#ibcon#about to read 5, iclass 29, count 2 2006.260.08:01:31.78#ibcon#read 5, iclass 29, count 2 2006.260.08:01:31.78#ibcon#about to read 6, iclass 29, count 2 2006.260.08:01:31.78#ibcon#read 6, iclass 29, count 2 2006.260.08:01:31.78#ibcon#end of sib2, iclass 29, count 2 2006.260.08:01:31.78#ibcon#*after write, iclass 29, count 2 2006.260.08:01:31.78#ibcon#*before return 0, iclass 29, count 2 2006.260.08:01:31.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:01:31.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:01:31.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.08:01:31.78#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:31.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:01:31.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:01:31.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:01:31.90#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:01:31.90#ibcon#first serial, iclass 29, count 0 2006.260.08:01:31.90#ibcon#enter sib2, iclass 29, count 0 2006.260.08:01:31.90#ibcon#flushed, iclass 29, count 0 2006.260.08:01:31.90#ibcon#about to write, iclass 29, count 0 2006.260.08:01:31.90#ibcon#wrote, iclass 29, count 0 2006.260.08:01:31.90#ibcon#about to read 3, iclass 29, count 0 2006.260.08:01:31.92#ibcon#read 3, iclass 29, count 0 2006.260.08:01:31.92#ibcon#about to read 4, iclass 29, count 0 2006.260.08:01:31.92#ibcon#read 4, iclass 29, count 0 2006.260.08:01:31.92#ibcon#about to read 5, iclass 29, count 0 2006.260.08:01:31.92#ibcon#read 5, iclass 29, count 0 2006.260.08:01:31.92#ibcon#about to read 6, iclass 29, count 0 2006.260.08:01:31.92#ibcon#read 6, iclass 29, count 0 2006.260.08:01:31.92#ibcon#end of sib2, iclass 29, count 0 2006.260.08:01:31.92#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:01:31.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:01:31.92#ibcon#[27=USB\r\n] 2006.260.08:01:31.92#ibcon#*before write, iclass 29, count 0 2006.260.08:01:31.92#ibcon#enter sib2, iclass 29, count 0 2006.260.08:01:31.92#ibcon#flushed, iclass 29, count 0 2006.260.08:01:31.92#ibcon#about to write, iclass 29, count 0 2006.260.08:01:31.92#ibcon#wrote, iclass 29, count 0 2006.260.08:01:31.92#ibcon#about to read 3, iclass 29, count 0 2006.260.08:01:31.95#ibcon#read 3, iclass 29, count 0 2006.260.08:01:31.95#ibcon#about to read 4, iclass 29, count 0 2006.260.08:01:31.95#ibcon#read 4, iclass 29, count 0 2006.260.08:01:31.95#ibcon#about to read 5, iclass 29, count 0 2006.260.08:01:31.95#ibcon#read 5, iclass 29, count 0 2006.260.08:01:31.95#ibcon#about to read 6, iclass 29, count 0 2006.260.08:01:31.95#ibcon#read 6, iclass 29, count 0 2006.260.08:01:31.95#ibcon#end of sib2, iclass 29, count 0 2006.260.08:01:31.95#ibcon#*after write, iclass 29, count 0 2006.260.08:01:31.95#ibcon#*before return 0, iclass 29, count 0 2006.260.08:01:31.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:01:31.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:01:31.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:01:31.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:01:31.95$vc4f8/vblo=2,640.99 2006.260.08:01:31.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.08:01:31.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.08:01:31.95#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:31.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:31.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:31.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:31.95#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:01:31.95#ibcon#first serial, iclass 31, count 0 2006.260.08:01:31.95#ibcon#enter sib2, iclass 31, count 0 2006.260.08:01:31.95#ibcon#flushed, iclass 31, count 0 2006.260.08:01:31.95#ibcon#about to write, iclass 31, count 0 2006.260.08:01:31.95#ibcon#wrote, iclass 31, count 0 2006.260.08:01:31.95#ibcon#about to read 3, iclass 31, count 0 2006.260.08:01:31.97#ibcon#read 3, iclass 31, count 0 2006.260.08:01:31.97#ibcon#about to read 4, iclass 31, count 0 2006.260.08:01:31.97#ibcon#read 4, iclass 31, count 0 2006.260.08:01:31.97#ibcon#about to read 5, iclass 31, count 0 2006.260.08:01:31.97#ibcon#read 5, iclass 31, count 0 2006.260.08:01:31.97#ibcon#about to read 6, iclass 31, count 0 2006.260.08:01:31.97#ibcon#read 6, iclass 31, count 0 2006.260.08:01:31.97#ibcon#end of sib2, iclass 31, count 0 2006.260.08:01:31.97#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:01:31.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:01:31.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:01:31.97#ibcon#*before write, iclass 31, count 0 2006.260.08:01:31.97#ibcon#enter sib2, iclass 31, count 0 2006.260.08:01:31.97#ibcon#flushed, iclass 31, count 0 2006.260.08:01:31.97#ibcon#about to write, iclass 31, count 0 2006.260.08:01:31.97#ibcon#wrote, iclass 31, count 0 2006.260.08:01:31.97#ibcon#about to read 3, iclass 31, count 0 2006.260.08:01:32.01#ibcon#read 3, iclass 31, count 0 2006.260.08:01:32.01#ibcon#about to read 4, iclass 31, count 0 2006.260.08:01:32.01#ibcon#read 4, iclass 31, count 0 2006.260.08:01:32.01#ibcon#about to read 5, iclass 31, count 0 2006.260.08:01:32.01#ibcon#read 5, iclass 31, count 0 2006.260.08:01:32.01#ibcon#about to read 6, iclass 31, count 0 2006.260.08:01:32.01#ibcon#read 6, iclass 31, count 0 2006.260.08:01:32.01#ibcon#end of sib2, iclass 31, count 0 2006.260.08:01:32.01#ibcon#*after write, iclass 31, count 0 2006.260.08:01:32.01#ibcon#*before return 0, iclass 31, count 0 2006.260.08:01:32.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:32.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:01:32.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:01:32.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:01:32.01$vc4f8/vb=2,5 2006.260.08:01:32.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.08:01:32.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.08:01:32.01#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:32.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:32.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:32.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:32.07#ibcon#enter wrdev, iclass 33, count 2 2006.260.08:01:32.07#ibcon#first serial, iclass 33, count 2 2006.260.08:01:32.07#ibcon#enter sib2, iclass 33, count 2 2006.260.08:01:32.07#ibcon#flushed, iclass 33, count 2 2006.260.08:01:32.07#ibcon#about to write, iclass 33, count 2 2006.260.08:01:32.07#ibcon#wrote, iclass 33, count 2 2006.260.08:01:32.07#ibcon#about to read 3, iclass 33, count 2 2006.260.08:01:32.09#ibcon#read 3, iclass 33, count 2 2006.260.08:01:32.09#ibcon#about to read 4, iclass 33, count 2 2006.260.08:01:32.09#ibcon#read 4, iclass 33, count 2 2006.260.08:01:32.09#ibcon#about to read 5, iclass 33, count 2 2006.260.08:01:32.09#ibcon#read 5, iclass 33, count 2 2006.260.08:01:32.09#ibcon#about to read 6, iclass 33, count 2 2006.260.08:01:32.09#ibcon#read 6, iclass 33, count 2 2006.260.08:01:32.09#ibcon#end of sib2, iclass 33, count 2 2006.260.08:01:32.09#ibcon#*mode == 0, iclass 33, count 2 2006.260.08:01:32.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.08:01:32.09#ibcon#[27=AT02-05\r\n] 2006.260.08:01:32.09#ibcon#*before write, iclass 33, count 2 2006.260.08:01:32.09#ibcon#enter sib2, iclass 33, count 2 2006.260.08:01:32.09#ibcon#flushed, iclass 33, count 2 2006.260.08:01:32.09#ibcon#about to write, iclass 33, count 2 2006.260.08:01:32.09#ibcon#wrote, iclass 33, count 2 2006.260.08:01:32.09#ibcon#about to read 3, iclass 33, count 2 2006.260.08:01:32.12#ibcon#read 3, iclass 33, count 2 2006.260.08:01:32.12#ibcon#about to read 4, iclass 33, count 2 2006.260.08:01:32.12#ibcon#read 4, iclass 33, count 2 2006.260.08:01:32.12#ibcon#about to read 5, iclass 33, count 2 2006.260.08:01:32.12#ibcon#read 5, iclass 33, count 2 2006.260.08:01:32.12#ibcon#about to read 6, iclass 33, count 2 2006.260.08:01:32.12#ibcon#read 6, iclass 33, count 2 2006.260.08:01:32.12#ibcon#end of sib2, iclass 33, count 2 2006.260.08:01:32.12#ibcon#*after write, iclass 33, count 2 2006.260.08:01:32.12#ibcon#*before return 0, iclass 33, count 2 2006.260.08:01:32.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:32.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:01:32.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.08:01:32.12#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:32.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:32.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:32.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:32.24#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:01:32.24#ibcon#first serial, iclass 33, count 0 2006.260.08:01:32.24#ibcon#enter sib2, iclass 33, count 0 2006.260.08:01:32.24#ibcon#flushed, iclass 33, count 0 2006.260.08:01:32.24#ibcon#about to write, iclass 33, count 0 2006.260.08:01:32.24#ibcon#wrote, iclass 33, count 0 2006.260.08:01:32.24#ibcon#about to read 3, iclass 33, count 0 2006.260.08:01:32.26#ibcon#read 3, iclass 33, count 0 2006.260.08:01:32.26#ibcon#about to read 4, iclass 33, count 0 2006.260.08:01:32.26#ibcon#read 4, iclass 33, count 0 2006.260.08:01:32.26#ibcon#about to read 5, iclass 33, count 0 2006.260.08:01:32.26#ibcon#read 5, iclass 33, count 0 2006.260.08:01:32.26#ibcon#about to read 6, iclass 33, count 0 2006.260.08:01:32.26#ibcon#read 6, iclass 33, count 0 2006.260.08:01:32.26#ibcon#end of sib2, iclass 33, count 0 2006.260.08:01:32.26#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:01:32.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:01:32.26#ibcon#[27=USB\r\n] 2006.260.08:01:32.26#ibcon#*before write, iclass 33, count 0 2006.260.08:01:32.26#ibcon#enter sib2, iclass 33, count 0 2006.260.08:01:32.26#ibcon#flushed, iclass 33, count 0 2006.260.08:01:32.26#ibcon#about to write, iclass 33, count 0 2006.260.08:01:32.26#ibcon#wrote, iclass 33, count 0 2006.260.08:01:32.26#ibcon#about to read 3, iclass 33, count 0 2006.260.08:01:32.29#ibcon#read 3, iclass 33, count 0 2006.260.08:01:32.29#ibcon#about to read 4, iclass 33, count 0 2006.260.08:01:32.29#ibcon#read 4, iclass 33, count 0 2006.260.08:01:32.29#ibcon#about to read 5, iclass 33, count 0 2006.260.08:01:32.29#ibcon#read 5, iclass 33, count 0 2006.260.08:01:32.29#ibcon#about to read 6, iclass 33, count 0 2006.260.08:01:32.29#ibcon#read 6, iclass 33, count 0 2006.260.08:01:32.29#ibcon#end of sib2, iclass 33, count 0 2006.260.08:01:32.29#ibcon#*after write, iclass 33, count 0 2006.260.08:01:32.29#ibcon#*before return 0, iclass 33, count 0 2006.260.08:01:32.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:32.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:01:32.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:01:32.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:01:32.29$vc4f8/vblo=3,656.99 2006.260.08:01:32.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.08:01:32.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.08:01:32.29#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:32.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:32.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:32.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:32.29#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:01:32.29#ibcon#first serial, iclass 35, count 0 2006.260.08:01:32.29#ibcon#enter sib2, iclass 35, count 0 2006.260.08:01:32.29#ibcon#flushed, iclass 35, count 0 2006.260.08:01:32.29#ibcon#about to write, iclass 35, count 0 2006.260.08:01:32.29#ibcon#wrote, iclass 35, count 0 2006.260.08:01:32.29#ibcon#about to read 3, iclass 35, count 0 2006.260.08:01:32.31#ibcon#read 3, iclass 35, count 0 2006.260.08:01:32.31#ibcon#about to read 4, iclass 35, count 0 2006.260.08:01:32.31#ibcon#read 4, iclass 35, count 0 2006.260.08:01:32.31#ibcon#about to read 5, iclass 35, count 0 2006.260.08:01:32.31#ibcon#read 5, iclass 35, count 0 2006.260.08:01:32.31#ibcon#about to read 6, iclass 35, count 0 2006.260.08:01:32.31#ibcon#read 6, iclass 35, count 0 2006.260.08:01:32.31#ibcon#end of sib2, iclass 35, count 0 2006.260.08:01:32.31#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:01:32.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:01:32.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:01:32.31#ibcon#*before write, iclass 35, count 0 2006.260.08:01:32.31#ibcon#enter sib2, iclass 35, count 0 2006.260.08:01:32.31#ibcon#flushed, iclass 35, count 0 2006.260.08:01:32.31#ibcon#about to write, iclass 35, count 0 2006.260.08:01:32.31#ibcon#wrote, iclass 35, count 0 2006.260.08:01:32.31#ibcon#about to read 3, iclass 35, count 0 2006.260.08:01:32.35#ibcon#read 3, iclass 35, count 0 2006.260.08:01:32.35#ibcon#about to read 4, iclass 35, count 0 2006.260.08:01:32.35#ibcon#read 4, iclass 35, count 0 2006.260.08:01:32.35#ibcon#about to read 5, iclass 35, count 0 2006.260.08:01:32.35#ibcon#read 5, iclass 35, count 0 2006.260.08:01:32.35#ibcon#about to read 6, iclass 35, count 0 2006.260.08:01:32.35#ibcon#read 6, iclass 35, count 0 2006.260.08:01:32.35#ibcon#end of sib2, iclass 35, count 0 2006.260.08:01:32.35#ibcon#*after write, iclass 35, count 0 2006.260.08:01:32.35#ibcon#*before return 0, iclass 35, count 0 2006.260.08:01:32.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:32.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:01:32.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:01:32.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:01:32.35$vc4f8/vb=3,4 2006.260.08:01:32.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.08:01:32.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.08:01:32.35#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:32.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:32.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:32.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:32.41#ibcon#enter wrdev, iclass 37, count 2 2006.260.08:01:32.41#ibcon#first serial, iclass 37, count 2 2006.260.08:01:32.41#ibcon#enter sib2, iclass 37, count 2 2006.260.08:01:32.41#ibcon#flushed, iclass 37, count 2 2006.260.08:01:32.41#ibcon#about to write, iclass 37, count 2 2006.260.08:01:32.41#ibcon#wrote, iclass 37, count 2 2006.260.08:01:32.41#ibcon#about to read 3, iclass 37, count 2 2006.260.08:01:32.43#ibcon#read 3, iclass 37, count 2 2006.260.08:01:32.43#ibcon#about to read 4, iclass 37, count 2 2006.260.08:01:32.43#ibcon#read 4, iclass 37, count 2 2006.260.08:01:32.43#ibcon#about to read 5, iclass 37, count 2 2006.260.08:01:32.43#ibcon#read 5, iclass 37, count 2 2006.260.08:01:32.43#ibcon#about to read 6, iclass 37, count 2 2006.260.08:01:32.43#ibcon#read 6, iclass 37, count 2 2006.260.08:01:32.43#ibcon#end of sib2, iclass 37, count 2 2006.260.08:01:32.43#ibcon#*mode == 0, iclass 37, count 2 2006.260.08:01:32.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.08:01:32.43#ibcon#[27=AT03-04\r\n] 2006.260.08:01:32.43#ibcon#*before write, iclass 37, count 2 2006.260.08:01:32.43#ibcon#enter sib2, iclass 37, count 2 2006.260.08:01:32.43#ibcon#flushed, iclass 37, count 2 2006.260.08:01:32.43#ibcon#about to write, iclass 37, count 2 2006.260.08:01:32.43#ibcon#wrote, iclass 37, count 2 2006.260.08:01:32.43#ibcon#about to read 3, iclass 37, count 2 2006.260.08:01:32.46#ibcon#read 3, iclass 37, count 2 2006.260.08:01:32.46#ibcon#about to read 4, iclass 37, count 2 2006.260.08:01:32.46#ibcon#read 4, iclass 37, count 2 2006.260.08:01:32.46#ibcon#about to read 5, iclass 37, count 2 2006.260.08:01:32.46#ibcon#read 5, iclass 37, count 2 2006.260.08:01:32.46#ibcon#about to read 6, iclass 37, count 2 2006.260.08:01:32.46#ibcon#read 6, iclass 37, count 2 2006.260.08:01:32.46#ibcon#end of sib2, iclass 37, count 2 2006.260.08:01:32.46#ibcon#*after write, iclass 37, count 2 2006.260.08:01:32.46#ibcon#*before return 0, iclass 37, count 2 2006.260.08:01:32.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:32.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:01:32.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.08:01:32.46#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:32.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:32.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:32.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:32.58#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:01:32.58#ibcon#first serial, iclass 37, count 0 2006.260.08:01:32.58#ibcon#enter sib2, iclass 37, count 0 2006.260.08:01:32.58#ibcon#flushed, iclass 37, count 0 2006.260.08:01:32.58#ibcon#about to write, iclass 37, count 0 2006.260.08:01:32.58#ibcon#wrote, iclass 37, count 0 2006.260.08:01:32.58#ibcon#about to read 3, iclass 37, count 0 2006.260.08:01:32.60#ibcon#read 3, iclass 37, count 0 2006.260.08:01:32.60#ibcon#about to read 4, iclass 37, count 0 2006.260.08:01:32.60#ibcon#read 4, iclass 37, count 0 2006.260.08:01:32.60#ibcon#about to read 5, iclass 37, count 0 2006.260.08:01:32.60#ibcon#read 5, iclass 37, count 0 2006.260.08:01:32.60#ibcon#about to read 6, iclass 37, count 0 2006.260.08:01:32.60#ibcon#read 6, iclass 37, count 0 2006.260.08:01:32.60#ibcon#end of sib2, iclass 37, count 0 2006.260.08:01:32.60#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:01:32.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:01:32.60#ibcon#[27=USB\r\n] 2006.260.08:01:32.60#ibcon#*before write, iclass 37, count 0 2006.260.08:01:32.60#ibcon#enter sib2, iclass 37, count 0 2006.260.08:01:32.60#ibcon#flushed, iclass 37, count 0 2006.260.08:01:32.60#ibcon#about to write, iclass 37, count 0 2006.260.08:01:32.60#ibcon#wrote, iclass 37, count 0 2006.260.08:01:32.60#ibcon#about to read 3, iclass 37, count 0 2006.260.08:01:32.63#ibcon#read 3, iclass 37, count 0 2006.260.08:01:32.63#ibcon#about to read 4, iclass 37, count 0 2006.260.08:01:32.63#ibcon#read 4, iclass 37, count 0 2006.260.08:01:32.63#ibcon#about to read 5, iclass 37, count 0 2006.260.08:01:32.63#ibcon#read 5, iclass 37, count 0 2006.260.08:01:32.63#ibcon#about to read 6, iclass 37, count 0 2006.260.08:01:32.63#ibcon#read 6, iclass 37, count 0 2006.260.08:01:32.63#ibcon#end of sib2, iclass 37, count 0 2006.260.08:01:32.63#ibcon#*after write, iclass 37, count 0 2006.260.08:01:32.63#ibcon#*before return 0, iclass 37, count 0 2006.260.08:01:32.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:32.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:01:32.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:01:32.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:01:32.63$vc4f8/vblo=4,712.99 2006.260.08:01:32.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.08:01:32.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.08:01:32.63#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:32.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:32.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:32.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:32.63#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:01:32.63#ibcon#first serial, iclass 39, count 0 2006.260.08:01:32.63#ibcon#enter sib2, iclass 39, count 0 2006.260.08:01:32.63#ibcon#flushed, iclass 39, count 0 2006.260.08:01:32.63#ibcon#about to write, iclass 39, count 0 2006.260.08:01:32.63#ibcon#wrote, iclass 39, count 0 2006.260.08:01:32.63#ibcon#about to read 3, iclass 39, count 0 2006.260.08:01:32.65#ibcon#read 3, iclass 39, count 0 2006.260.08:01:32.65#ibcon#about to read 4, iclass 39, count 0 2006.260.08:01:32.65#ibcon#read 4, iclass 39, count 0 2006.260.08:01:32.65#ibcon#about to read 5, iclass 39, count 0 2006.260.08:01:32.65#ibcon#read 5, iclass 39, count 0 2006.260.08:01:32.65#ibcon#about to read 6, iclass 39, count 0 2006.260.08:01:32.65#ibcon#read 6, iclass 39, count 0 2006.260.08:01:32.65#ibcon#end of sib2, iclass 39, count 0 2006.260.08:01:32.65#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:01:32.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:01:32.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:01:32.65#ibcon#*before write, iclass 39, count 0 2006.260.08:01:32.65#ibcon#enter sib2, iclass 39, count 0 2006.260.08:01:32.65#ibcon#flushed, iclass 39, count 0 2006.260.08:01:32.65#ibcon#about to write, iclass 39, count 0 2006.260.08:01:32.65#ibcon#wrote, iclass 39, count 0 2006.260.08:01:32.65#ibcon#about to read 3, iclass 39, count 0 2006.260.08:01:32.69#ibcon#read 3, iclass 39, count 0 2006.260.08:01:32.69#ibcon#about to read 4, iclass 39, count 0 2006.260.08:01:32.69#ibcon#read 4, iclass 39, count 0 2006.260.08:01:32.69#ibcon#about to read 5, iclass 39, count 0 2006.260.08:01:32.69#ibcon#read 5, iclass 39, count 0 2006.260.08:01:32.69#ibcon#about to read 6, iclass 39, count 0 2006.260.08:01:32.69#ibcon#read 6, iclass 39, count 0 2006.260.08:01:32.69#ibcon#end of sib2, iclass 39, count 0 2006.260.08:01:32.69#ibcon#*after write, iclass 39, count 0 2006.260.08:01:32.69#ibcon#*before return 0, iclass 39, count 0 2006.260.08:01:32.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:32.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:01:32.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:01:32.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:01:32.69$vc4f8/vb=4,5 2006.260.08:01:32.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.08:01:32.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.08:01:32.69#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:32.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:32.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:32.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:32.75#ibcon#enter wrdev, iclass 3, count 2 2006.260.08:01:32.75#ibcon#first serial, iclass 3, count 2 2006.260.08:01:32.75#ibcon#enter sib2, iclass 3, count 2 2006.260.08:01:32.75#ibcon#flushed, iclass 3, count 2 2006.260.08:01:32.75#ibcon#about to write, iclass 3, count 2 2006.260.08:01:32.75#ibcon#wrote, iclass 3, count 2 2006.260.08:01:32.75#ibcon#about to read 3, iclass 3, count 2 2006.260.08:01:32.77#ibcon#read 3, iclass 3, count 2 2006.260.08:01:32.77#ibcon#about to read 4, iclass 3, count 2 2006.260.08:01:32.77#ibcon#read 4, iclass 3, count 2 2006.260.08:01:32.77#ibcon#about to read 5, iclass 3, count 2 2006.260.08:01:32.77#ibcon#read 5, iclass 3, count 2 2006.260.08:01:32.77#ibcon#about to read 6, iclass 3, count 2 2006.260.08:01:32.77#ibcon#read 6, iclass 3, count 2 2006.260.08:01:32.77#ibcon#end of sib2, iclass 3, count 2 2006.260.08:01:32.77#ibcon#*mode == 0, iclass 3, count 2 2006.260.08:01:32.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.08:01:32.77#ibcon#[27=AT04-05\r\n] 2006.260.08:01:32.77#ibcon#*before write, iclass 3, count 2 2006.260.08:01:32.77#ibcon#enter sib2, iclass 3, count 2 2006.260.08:01:32.77#ibcon#flushed, iclass 3, count 2 2006.260.08:01:32.77#ibcon#about to write, iclass 3, count 2 2006.260.08:01:32.77#ibcon#wrote, iclass 3, count 2 2006.260.08:01:32.77#ibcon#about to read 3, iclass 3, count 2 2006.260.08:01:32.80#ibcon#read 3, iclass 3, count 2 2006.260.08:01:32.80#ibcon#about to read 4, iclass 3, count 2 2006.260.08:01:32.80#ibcon#read 4, iclass 3, count 2 2006.260.08:01:32.80#ibcon#about to read 5, iclass 3, count 2 2006.260.08:01:32.80#ibcon#read 5, iclass 3, count 2 2006.260.08:01:32.80#ibcon#about to read 6, iclass 3, count 2 2006.260.08:01:32.80#ibcon#read 6, iclass 3, count 2 2006.260.08:01:32.80#ibcon#end of sib2, iclass 3, count 2 2006.260.08:01:32.80#ibcon#*after write, iclass 3, count 2 2006.260.08:01:32.80#ibcon#*before return 0, iclass 3, count 2 2006.260.08:01:32.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:32.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:01:32.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.08:01:32.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:32.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:32.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:32.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:32.92#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:01:32.92#ibcon#first serial, iclass 3, count 0 2006.260.08:01:32.92#ibcon#enter sib2, iclass 3, count 0 2006.260.08:01:32.92#ibcon#flushed, iclass 3, count 0 2006.260.08:01:32.92#ibcon#about to write, iclass 3, count 0 2006.260.08:01:32.92#ibcon#wrote, iclass 3, count 0 2006.260.08:01:32.92#ibcon#about to read 3, iclass 3, count 0 2006.260.08:01:32.94#ibcon#read 3, iclass 3, count 0 2006.260.08:01:32.94#ibcon#about to read 4, iclass 3, count 0 2006.260.08:01:32.94#ibcon#read 4, iclass 3, count 0 2006.260.08:01:32.94#ibcon#about to read 5, iclass 3, count 0 2006.260.08:01:32.94#ibcon#read 5, iclass 3, count 0 2006.260.08:01:32.94#ibcon#about to read 6, iclass 3, count 0 2006.260.08:01:32.94#ibcon#read 6, iclass 3, count 0 2006.260.08:01:32.94#ibcon#end of sib2, iclass 3, count 0 2006.260.08:01:32.94#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:01:32.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:01:32.94#ibcon#[27=USB\r\n] 2006.260.08:01:32.94#ibcon#*before write, iclass 3, count 0 2006.260.08:01:32.94#ibcon#enter sib2, iclass 3, count 0 2006.260.08:01:32.94#ibcon#flushed, iclass 3, count 0 2006.260.08:01:32.94#ibcon#about to write, iclass 3, count 0 2006.260.08:01:32.94#ibcon#wrote, iclass 3, count 0 2006.260.08:01:32.94#ibcon#about to read 3, iclass 3, count 0 2006.260.08:01:32.97#ibcon#read 3, iclass 3, count 0 2006.260.08:01:32.97#ibcon#about to read 4, iclass 3, count 0 2006.260.08:01:32.97#ibcon#read 4, iclass 3, count 0 2006.260.08:01:32.97#ibcon#about to read 5, iclass 3, count 0 2006.260.08:01:32.97#ibcon#read 5, iclass 3, count 0 2006.260.08:01:32.97#ibcon#about to read 6, iclass 3, count 0 2006.260.08:01:32.97#ibcon#read 6, iclass 3, count 0 2006.260.08:01:32.97#ibcon#end of sib2, iclass 3, count 0 2006.260.08:01:32.97#ibcon#*after write, iclass 3, count 0 2006.260.08:01:32.97#ibcon#*before return 0, iclass 3, count 0 2006.260.08:01:32.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:32.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:01:32.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:01:32.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:01:32.97$vc4f8/vblo=5,744.99 2006.260.08:01:32.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:01:32.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:01:32.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:32.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:32.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:32.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:32.97#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:01:32.97#ibcon#first serial, iclass 5, count 0 2006.260.08:01:32.97#ibcon#enter sib2, iclass 5, count 0 2006.260.08:01:32.97#ibcon#flushed, iclass 5, count 0 2006.260.08:01:32.97#ibcon#about to write, iclass 5, count 0 2006.260.08:01:32.97#ibcon#wrote, iclass 5, count 0 2006.260.08:01:32.97#ibcon#about to read 3, iclass 5, count 0 2006.260.08:01:32.99#ibcon#read 3, iclass 5, count 0 2006.260.08:01:32.99#ibcon#about to read 4, iclass 5, count 0 2006.260.08:01:32.99#ibcon#read 4, iclass 5, count 0 2006.260.08:01:32.99#ibcon#about to read 5, iclass 5, count 0 2006.260.08:01:32.99#ibcon#read 5, iclass 5, count 0 2006.260.08:01:32.99#ibcon#about to read 6, iclass 5, count 0 2006.260.08:01:32.99#ibcon#read 6, iclass 5, count 0 2006.260.08:01:32.99#ibcon#end of sib2, iclass 5, count 0 2006.260.08:01:32.99#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:01:32.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:01:32.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:01:32.99#ibcon#*before write, iclass 5, count 0 2006.260.08:01:32.99#ibcon#enter sib2, iclass 5, count 0 2006.260.08:01:32.99#ibcon#flushed, iclass 5, count 0 2006.260.08:01:32.99#ibcon#about to write, iclass 5, count 0 2006.260.08:01:32.99#ibcon#wrote, iclass 5, count 0 2006.260.08:01:32.99#ibcon#about to read 3, iclass 5, count 0 2006.260.08:01:33.03#ibcon#read 3, iclass 5, count 0 2006.260.08:01:33.03#ibcon#about to read 4, iclass 5, count 0 2006.260.08:01:33.03#ibcon#read 4, iclass 5, count 0 2006.260.08:01:33.03#ibcon#about to read 5, iclass 5, count 0 2006.260.08:01:33.03#ibcon#read 5, iclass 5, count 0 2006.260.08:01:33.03#ibcon#about to read 6, iclass 5, count 0 2006.260.08:01:33.03#ibcon#read 6, iclass 5, count 0 2006.260.08:01:33.03#ibcon#end of sib2, iclass 5, count 0 2006.260.08:01:33.03#ibcon#*after write, iclass 5, count 0 2006.260.08:01:33.03#ibcon#*before return 0, iclass 5, count 0 2006.260.08:01:33.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:33.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:01:33.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:01:33.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:01:33.03$vc4f8/vb=5,4 2006.260.08:01:33.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:01:33.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:01:33.03#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:33.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:33.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:33.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:33.09#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:01:33.09#ibcon#first serial, iclass 7, count 2 2006.260.08:01:33.09#ibcon#enter sib2, iclass 7, count 2 2006.260.08:01:33.09#ibcon#flushed, iclass 7, count 2 2006.260.08:01:33.09#ibcon#about to write, iclass 7, count 2 2006.260.08:01:33.09#ibcon#wrote, iclass 7, count 2 2006.260.08:01:33.09#ibcon#about to read 3, iclass 7, count 2 2006.260.08:01:33.11#ibcon#read 3, iclass 7, count 2 2006.260.08:01:33.11#ibcon#about to read 4, iclass 7, count 2 2006.260.08:01:33.11#ibcon#read 4, iclass 7, count 2 2006.260.08:01:33.11#ibcon#about to read 5, iclass 7, count 2 2006.260.08:01:33.11#ibcon#read 5, iclass 7, count 2 2006.260.08:01:33.11#ibcon#about to read 6, iclass 7, count 2 2006.260.08:01:33.11#ibcon#read 6, iclass 7, count 2 2006.260.08:01:33.11#ibcon#end of sib2, iclass 7, count 2 2006.260.08:01:33.11#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:01:33.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:01:33.11#ibcon#[27=AT05-04\r\n] 2006.260.08:01:33.11#ibcon#*before write, iclass 7, count 2 2006.260.08:01:33.11#ibcon#enter sib2, iclass 7, count 2 2006.260.08:01:33.11#ibcon#flushed, iclass 7, count 2 2006.260.08:01:33.11#ibcon#about to write, iclass 7, count 2 2006.260.08:01:33.11#ibcon#wrote, iclass 7, count 2 2006.260.08:01:33.11#ibcon#about to read 3, iclass 7, count 2 2006.260.08:01:33.14#ibcon#read 3, iclass 7, count 2 2006.260.08:01:33.14#ibcon#about to read 4, iclass 7, count 2 2006.260.08:01:33.14#ibcon#read 4, iclass 7, count 2 2006.260.08:01:33.14#ibcon#about to read 5, iclass 7, count 2 2006.260.08:01:33.14#ibcon#read 5, iclass 7, count 2 2006.260.08:01:33.14#ibcon#about to read 6, iclass 7, count 2 2006.260.08:01:33.14#ibcon#read 6, iclass 7, count 2 2006.260.08:01:33.14#ibcon#end of sib2, iclass 7, count 2 2006.260.08:01:33.14#ibcon#*after write, iclass 7, count 2 2006.260.08:01:33.14#ibcon#*before return 0, iclass 7, count 2 2006.260.08:01:33.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:33.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:01:33.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:01:33.14#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:33.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:33.19#abcon#<5=/03 3.0 6.0 22.86 881010.4\r\n> 2006.260.08:01:33.21#abcon#{5=INTERFACE CLEAR} 2006.260.08:01:33.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:33.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:33.26#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:01:33.26#ibcon#first serial, iclass 7, count 0 2006.260.08:01:33.26#ibcon#enter sib2, iclass 7, count 0 2006.260.08:01:33.26#ibcon#flushed, iclass 7, count 0 2006.260.08:01:33.26#ibcon#about to write, iclass 7, count 0 2006.260.08:01:33.26#ibcon#wrote, iclass 7, count 0 2006.260.08:01:33.26#ibcon#about to read 3, iclass 7, count 0 2006.260.08:01:33.27#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:01:33.28#ibcon#read 3, iclass 7, count 0 2006.260.08:01:33.28#ibcon#about to read 4, iclass 7, count 0 2006.260.08:01:33.28#ibcon#read 4, iclass 7, count 0 2006.260.08:01:33.28#ibcon#about to read 5, iclass 7, count 0 2006.260.08:01:33.28#ibcon#read 5, iclass 7, count 0 2006.260.08:01:33.28#ibcon#about to read 6, iclass 7, count 0 2006.260.08:01:33.28#ibcon#read 6, iclass 7, count 0 2006.260.08:01:33.28#ibcon#end of sib2, iclass 7, count 0 2006.260.08:01:33.28#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:01:33.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:01:33.28#ibcon#[27=USB\r\n] 2006.260.08:01:33.28#ibcon#*before write, iclass 7, count 0 2006.260.08:01:33.28#ibcon#enter sib2, iclass 7, count 0 2006.260.08:01:33.28#ibcon#flushed, iclass 7, count 0 2006.260.08:01:33.28#ibcon#about to write, iclass 7, count 0 2006.260.08:01:33.28#ibcon#wrote, iclass 7, count 0 2006.260.08:01:33.28#ibcon#about to read 3, iclass 7, count 0 2006.260.08:01:33.31#ibcon#read 3, iclass 7, count 0 2006.260.08:01:33.31#ibcon#about to read 4, iclass 7, count 0 2006.260.08:01:33.31#ibcon#read 4, iclass 7, count 0 2006.260.08:01:33.31#ibcon#about to read 5, iclass 7, count 0 2006.260.08:01:33.31#ibcon#read 5, iclass 7, count 0 2006.260.08:01:33.31#ibcon#about to read 6, iclass 7, count 0 2006.260.08:01:33.31#ibcon#read 6, iclass 7, count 0 2006.260.08:01:33.31#ibcon#end of sib2, iclass 7, count 0 2006.260.08:01:33.31#ibcon#*after write, iclass 7, count 0 2006.260.08:01:33.31#ibcon#*before return 0, iclass 7, count 0 2006.260.08:01:33.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:33.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:01:33.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:01:33.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:01:33.31$vc4f8/vblo=6,752.99 2006.260.08:01:33.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:01:33.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:01:33.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:01:33.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:33.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:33.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:33.31#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:01:33.31#ibcon#first serial, iclass 15, count 0 2006.260.08:01:33.31#ibcon#enter sib2, iclass 15, count 0 2006.260.08:01:33.31#ibcon#flushed, iclass 15, count 0 2006.260.08:01:33.31#ibcon#about to write, iclass 15, count 0 2006.260.08:01:33.31#ibcon#wrote, iclass 15, count 0 2006.260.08:01:33.31#ibcon#about to read 3, iclass 15, count 0 2006.260.08:01:33.33#ibcon#read 3, iclass 15, count 0 2006.260.08:01:33.33#ibcon#about to read 4, iclass 15, count 0 2006.260.08:01:33.33#ibcon#read 4, iclass 15, count 0 2006.260.08:01:33.33#ibcon#about to read 5, iclass 15, count 0 2006.260.08:01:33.33#ibcon#read 5, iclass 15, count 0 2006.260.08:01:33.33#ibcon#about to read 6, iclass 15, count 0 2006.260.08:01:33.33#ibcon#read 6, iclass 15, count 0 2006.260.08:01:33.33#ibcon#end of sib2, iclass 15, count 0 2006.260.08:01:33.33#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:01:33.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:01:33.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:01:33.33#ibcon#*before write, iclass 15, count 0 2006.260.08:01:33.33#ibcon#enter sib2, iclass 15, count 0 2006.260.08:01:33.33#ibcon#flushed, iclass 15, count 0 2006.260.08:01:33.33#ibcon#about to write, iclass 15, count 0 2006.260.08:01:33.33#ibcon#wrote, iclass 15, count 0 2006.260.08:01:33.33#ibcon#about to read 3, iclass 15, count 0 2006.260.08:01:33.37#ibcon#read 3, iclass 15, count 0 2006.260.08:01:33.37#ibcon#about to read 4, iclass 15, count 0 2006.260.08:01:33.37#ibcon#read 4, iclass 15, count 0 2006.260.08:01:33.37#ibcon#about to read 5, iclass 15, count 0 2006.260.08:01:33.37#ibcon#read 5, iclass 15, count 0 2006.260.08:01:33.37#ibcon#about to read 6, iclass 15, count 0 2006.260.08:01:33.37#ibcon#read 6, iclass 15, count 0 2006.260.08:01:33.37#ibcon#end of sib2, iclass 15, count 0 2006.260.08:01:33.37#ibcon#*after write, iclass 15, count 0 2006.260.08:01:33.37#ibcon#*before return 0, iclass 15, count 0 2006.260.08:01:33.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:33.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:01:33.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:01:33.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:01:33.37$vc4f8/vb=6,4 2006.260.08:01:33.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:01:33.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:01:33.37#ibcon#ireg 11 cls_cnt 2 2006.260.08:01:33.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:33.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:33.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:33.43#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:01:33.43#ibcon#first serial, iclass 17, count 2 2006.260.08:01:33.43#ibcon#enter sib2, iclass 17, count 2 2006.260.08:01:33.43#ibcon#flushed, iclass 17, count 2 2006.260.08:01:33.43#ibcon#about to write, iclass 17, count 2 2006.260.08:01:33.43#ibcon#wrote, iclass 17, count 2 2006.260.08:01:33.43#ibcon#about to read 3, iclass 17, count 2 2006.260.08:01:33.45#ibcon#read 3, iclass 17, count 2 2006.260.08:01:33.45#ibcon#about to read 4, iclass 17, count 2 2006.260.08:01:33.45#ibcon#read 4, iclass 17, count 2 2006.260.08:01:33.45#ibcon#about to read 5, iclass 17, count 2 2006.260.08:01:33.45#ibcon#read 5, iclass 17, count 2 2006.260.08:01:33.45#ibcon#about to read 6, iclass 17, count 2 2006.260.08:01:33.45#ibcon#read 6, iclass 17, count 2 2006.260.08:01:33.45#ibcon#end of sib2, iclass 17, count 2 2006.260.08:01:33.45#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:01:33.45#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:01:33.45#ibcon#[27=AT06-04\r\n] 2006.260.08:01:33.45#ibcon#*before write, iclass 17, count 2 2006.260.08:01:33.45#ibcon#enter sib2, iclass 17, count 2 2006.260.08:01:33.45#ibcon#flushed, iclass 17, count 2 2006.260.08:01:33.45#ibcon#about to write, iclass 17, count 2 2006.260.08:01:33.45#ibcon#wrote, iclass 17, count 2 2006.260.08:01:33.45#ibcon#about to read 3, iclass 17, count 2 2006.260.08:01:33.48#ibcon#read 3, iclass 17, count 2 2006.260.08:01:33.48#ibcon#about to read 4, iclass 17, count 2 2006.260.08:01:33.48#ibcon#read 4, iclass 17, count 2 2006.260.08:01:33.48#ibcon#about to read 5, iclass 17, count 2 2006.260.08:01:33.48#ibcon#read 5, iclass 17, count 2 2006.260.08:01:33.48#ibcon#about to read 6, iclass 17, count 2 2006.260.08:01:33.48#ibcon#read 6, iclass 17, count 2 2006.260.08:01:33.48#ibcon#end of sib2, iclass 17, count 2 2006.260.08:01:33.48#ibcon#*after write, iclass 17, count 2 2006.260.08:01:33.48#ibcon#*before return 0, iclass 17, count 2 2006.260.08:01:33.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:33.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:01:33.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:01:33.48#ibcon#ireg 7 cls_cnt 0 2006.260.08:01:33.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:33.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:33.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:33.60#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:01:33.60#ibcon#first serial, iclass 17, count 0 2006.260.08:01:33.60#ibcon#enter sib2, iclass 17, count 0 2006.260.08:01:33.60#ibcon#flushed, iclass 17, count 0 2006.260.08:01:33.60#ibcon#about to write, iclass 17, count 0 2006.260.08:01:33.60#ibcon#wrote, iclass 17, count 0 2006.260.08:01:33.60#ibcon#about to read 3, iclass 17, count 0 2006.260.08:01:33.62#ibcon#read 3, iclass 17, count 0 2006.260.08:01:33.62#ibcon#about to read 4, iclass 17, count 0 2006.260.08:01:33.62#ibcon#read 4, iclass 17, count 0 2006.260.08:01:33.62#ibcon#about to read 5, iclass 17, count 0 2006.260.08:01:33.62#ibcon#read 5, iclass 17, count 0 2006.260.08:01:33.62#ibcon#about to read 6, iclass 17, count 0 2006.260.08:01:33.62#ibcon#read 6, iclass 17, count 0 2006.260.08:01:33.62#ibcon#end of sib2, iclass 17, count 0 2006.260.08:01:33.62#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:01:33.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:01:33.62#ibcon#[27=USB\r\n] 2006.260.08:01:33.62#ibcon#*before write, iclass 17, count 0 2006.260.08:01:33.62#ibcon#enter sib2, iclass 17, count 0 2006.260.08:01:33.62#ibcon#flushed, iclass 17, count 0 2006.260.08:01:33.62#ibcon#about to write, iclass 17, count 0 2006.260.08:01:33.62#ibcon#wrote, iclass 17, count 0 2006.260.08:01:33.62#ibcon#about to read 3, iclass 17, count 0 2006.260.08:01:33.65#ibcon#read 3, iclass 17, count 0 2006.260.08:01:33.65#ibcon#about to read 4, iclass 17, count 0 2006.260.08:01:33.65#ibcon#read 4, iclass 17, count 0 2006.260.08:01:33.65#ibcon#about to read 5, iclass 17, count 0 2006.260.08:01:33.65#ibcon#read 5, iclass 17, count 0 2006.260.08:01:33.65#ibcon#about to read 6, iclass 17, count 0 2006.260.08:01:33.65#ibcon#read 6, iclass 17, count 0 2006.260.08:01:33.65#ibcon#end of sib2, iclass 17, count 0 2006.260.08:01:33.65#ibcon#*after write, iclass 17, count 0 2006.260.08:01:33.65#ibcon#*before return 0, iclass 17, count 0 2006.260.08:01:33.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:33.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:01:33.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:01:33.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:01:33.65$vc4f8/vabw=wide 2006.260.08:01:33.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:01:33.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:01:33.65#ibcon#ireg 8 cls_cnt 0 2006.260.08:01:33.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:33.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:33.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:33.65#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:01:33.65#ibcon#first serial, iclass 19, count 0 2006.260.08:01:33.65#ibcon#enter sib2, iclass 19, count 0 2006.260.08:01:33.65#ibcon#flushed, iclass 19, count 0 2006.260.08:01:33.65#ibcon#about to write, iclass 19, count 0 2006.260.08:01:33.65#ibcon#wrote, iclass 19, count 0 2006.260.08:01:33.65#ibcon#about to read 3, iclass 19, count 0 2006.260.08:01:33.67#ibcon#read 3, iclass 19, count 0 2006.260.08:01:33.67#ibcon#about to read 4, iclass 19, count 0 2006.260.08:01:33.67#ibcon#read 4, iclass 19, count 0 2006.260.08:01:33.67#ibcon#about to read 5, iclass 19, count 0 2006.260.08:01:33.67#ibcon#read 5, iclass 19, count 0 2006.260.08:01:33.67#ibcon#about to read 6, iclass 19, count 0 2006.260.08:01:33.67#ibcon#read 6, iclass 19, count 0 2006.260.08:01:33.67#ibcon#end of sib2, iclass 19, count 0 2006.260.08:01:33.67#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:01:33.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:01:33.67#ibcon#[25=BW32\r\n] 2006.260.08:01:33.67#ibcon#*before write, iclass 19, count 0 2006.260.08:01:33.67#ibcon#enter sib2, iclass 19, count 0 2006.260.08:01:33.67#ibcon#flushed, iclass 19, count 0 2006.260.08:01:33.67#ibcon#about to write, iclass 19, count 0 2006.260.08:01:33.67#ibcon#wrote, iclass 19, count 0 2006.260.08:01:33.67#ibcon#about to read 3, iclass 19, count 0 2006.260.08:01:33.70#ibcon#read 3, iclass 19, count 0 2006.260.08:01:33.70#ibcon#about to read 4, iclass 19, count 0 2006.260.08:01:33.70#ibcon#read 4, iclass 19, count 0 2006.260.08:01:33.70#ibcon#about to read 5, iclass 19, count 0 2006.260.08:01:33.70#ibcon#read 5, iclass 19, count 0 2006.260.08:01:33.70#ibcon#about to read 6, iclass 19, count 0 2006.260.08:01:33.70#ibcon#read 6, iclass 19, count 0 2006.260.08:01:33.70#ibcon#end of sib2, iclass 19, count 0 2006.260.08:01:33.70#ibcon#*after write, iclass 19, count 0 2006.260.08:01:33.70#ibcon#*before return 0, iclass 19, count 0 2006.260.08:01:33.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:33.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:01:33.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:01:33.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:01:33.70$vc4f8/vbbw=wide 2006.260.08:01:33.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:01:33.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:01:33.70#ibcon#ireg 8 cls_cnt 0 2006.260.08:01:33.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:01:33.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:01:33.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:01:33.77#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:01:33.77#ibcon#first serial, iclass 21, count 0 2006.260.08:01:33.77#ibcon#enter sib2, iclass 21, count 0 2006.260.08:01:33.77#ibcon#flushed, iclass 21, count 0 2006.260.08:01:33.77#ibcon#about to write, iclass 21, count 0 2006.260.08:01:33.77#ibcon#wrote, iclass 21, count 0 2006.260.08:01:33.77#ibcon#about to read 3, iclass 21, count 0 2006.260.08:01:33.79#ibcon#read 3, iclass 21, count 0 2006.260.08:01:33.79#ibcon#about to read 4, iclass 21, count 0 2006.260.08:01:33.79#ibcon#read 4, iclass 21, count 0 2006.260.08:01:33.79#ibcon#about to read 5, iclass 21, count 0 2006.260.08:01:33.79#ibcon#read 5, iclass 21, count 0 2006.260.08:01:33.79#ibcon#about to read 6, iclass 21, count 0 2006.260.08:01:33.79#ibcon#read 6, iclass 21, count 0 2006.260.08:01:33.79#ibcon#end of sib2, iclass 21, count 0 2006.260.08:01:33.79#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:01:33.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:01:33.79#ibcon#[27=BW32\r\n] 2006.260.08:01:33.79#ibcon#*before write, iclass 21, count 0 2006.260.08:01:33.79#ibcon#enter sib2, iclass 21, count 0 2006.260.08:01:33.79#ibcon#flushed, iclass 21, count 0 2006.260.08:01:33.79#ibcon#about to write, iclass 21, count 0 2006.260.08:01:33.79#ibcon#wrote, iclass 21, count 0 2006.260.08:01:33.79#ibcon#about to read 3, iclass 21, count 0 2006.260.08:01:33.82#ibcon#read 3, iclass 21, count 0 2006.260.08:01:33.82#ibcon#about to read 4, iclass 21, count 0 2006.260.08:01:33.82#ibcon#read 4, iclass 21, count 0 2006.260.08:01:33.82#ibcon#about to read 5, iclass 21, count 0 2006.260.08:01:33.82#ibcon#read 5, iclass 21, count 0 2006.260.08:01:33.82#ibcon#about to read 6, iclass 21, count 0 2006.260.08:01:33.82#ibcon#read 6, iclass 21, count 0 2006.260.08:01:33.82#ibcon#end of sib2, iclass 21, count 0 2006.260.08:01:33.82#ibcon#*after write, iclass 21, count 0 2006.260.08:01:33.82#ibcon#*before return 0, iclass 21, count 0 2006.260.08:01:33.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:01:33.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:01:33.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:01:33.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:01:33.82$4f8m12a/ifd4f 2006.260.08:01:33.82$ifd4f/lo= 2006.260.08:01:33.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:01:33.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:01:33.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:01:33.82$ifd4f/patch= 2006.260.08:01:33.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:01:33.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:01:33.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:01:33.82$4f8m12a/"form=m,16.000,1:2 2006.260.08:01:33.82$4f8m12a/"tpicd 2006.260.08:01:33.82$4f8m12a/echo=off 2006.260.08:01:33.82$4f8m12a/xlog=off 2006.260.08:01:33.82:!2006.260.08:02:00 2006.260.08:01:39.13#trakl#Source acquired 2006.260.08:01:39.13#flagr#flagr/antenna,acquired 2006.260.08:02:00.00:preob 2006.260.08:02:01.13/onsource/TRACKING 2006.260.08:02:01.13:!2006.260.08:02:10 2006.260.08:02:10.00:data_valid=on 2006.260.08:02:10.00:midob 2006.260.08:02:10.13/onsource/TRACKING 2006.260.08:02:10.13/wx/22.86,1010.4,89 2006.260.08:02:10.24/cable/+6.4567E-03 2006.260.08:02:11.33/va/01,08,usb,yes,31,33 2006.260.08:02:11.33/va/02,07,usb,yes,31,33 2006.260.08:02:11.33/va/03,08,usb,yes,23,24 2006.260.08:02:11.33/va/04,07,usb,yes,32,35 2006.260.08:02:11.33/va/05,07,usb,yes,36,38 2006.260.08:02:11.33/va/06,06,usb,yes,35,35 2006.260.08:02:11.33/va/07,06,usb,yes,35,35 2006.260.08:02:11.33/va/08,06,usb,yes,38,37 2006.260.08:02:11.56/valo/01,532.99,yes,locked 2006.260.08:02:11.56/valo/02,572.99,yes,locked 2006.260.08:02:11.56/valo/03,672.99,yes,locked 2006.260.08:02:11.56/valo/04,832.99,yes,locked 2006.260.08:02:11.56/valo/05,652.99,yes,locked 2006.260.08:02:11.56/valo/06,772.99,yes,locked 2006.260.08:02:11.56/valo/07,832.99,yes,locked 2006.260.08:02:11.56/valo/08,852.99,yes,locked 2006.260.08:02:12.65/vb/01,04,usb,yes,30,29 2006.260.08:02:12.65/vb/02,05,usb,yes,28,29 2006.260.08:02:12.65/vb/03,04,usb,yes,28,31 2006.260.08:02:12.65/vb/04,05,usb,yes,25,25 2006.260.08:02:12.65/vb/05,04,usb,yes,27,31 2006.260.08:02:12.65/vb/06,04,usb,yes,28,31 2006.260.08:02:12.65/vb/07,04,usb,yes,30,30 2006.260.08:02:12.65/vb/08,04,usb,yes,28,31 2006.260.08:02:12.88/vblo/01,632.99,yes,locked 2006.260.08:02:12.88/vblo/02,640.99,yes,locked 2006.260.08:02:12.88/vblo/03,656.99,yes,locked 2006.260.08:02:12.88/vblo/04,712.99,yes,locked 2006.260.08:02:12.88/vblo/05,744.99,yes,locked 2006.260.08:02:12.88/vblo/06,752.99,yes,locked 2006.260.08:02:12.88/vblo/07,734.99,yes,locked 2006.260.08:02:12.88/vblo/08,744.99,yes,locked 2006.260.08:02:13.03/vabw/8 2006.260.08:02:13.18/vbbw/8 2006.260.08:02:13.27/xfe/off,on,15.0 2006.260.08:02:13.66/ifatt/23,28,28,28 2006.260.08:02:14.07/fmout-gps/S +4.46E-07 2006.260.08:02:14.11:!2006.260.08:03:10 2006.260.08:03:10.01:data_valid=off 2006.260.08:03:10.02:postob 2006.260.08:03:10.11/cable/+6.4569E-03 2006.260.08:03:10.12/wx/22.85,1010.4,88 2006.260.08:03:11.08/fmout-gps/S +4.46E-07 2006.260.08:03:11.09:scan_name=260-0804,k06260,60 2006.260.08:03:11.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.260.08:03:11.14#flagr#flagr/antenna,new-source 2006.260.08:03:12.14:checkk5 2006.260.08:03:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:03:12.95/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:03:13.36/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:03:13.76/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:03:14.16/chk_obsdata//k5ts1/T2600802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:03:14.75/chk_obsdata//k5ts2/T2600802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:03:15.15/chk_obsdata//k5ts3/T2600802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:03:15.54/chk_obsdata//k5ts4/T2600802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:03:16.53/k5log//k5ts1_log_newline 2006.260.08:03:17.32/k5log//k5ts2_log_newline 2006.260.08:03:18.12/k5log//k5ts3_log_newline 2006.260.08:03:18.94/k5log//k5ts4_log_newline 2006.260.08:03:18.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:03:18.96:4f8m12a=2 2006.260.08:03:18.96$4f8m12a/echo=on 2006.260.08:03:18.96$4f8m12a/pcalon 2006.260.08:03:18.96$pcalon/"no phase cal control is implemented here 2006.260.08:03:18.96$4f8m12a/"tpicd=stop 2006.260.08:03:18.96$4f8m12a/vc4f8 2006.260.08:03:18.96$vc4f8/valo=1,532.99 2006.260.08:03:18.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:03:18.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:03:18.96#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:18.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:18.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:18.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:18.96#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:03:18.96#ibcon#first serial, iclass 28, count 0 2006.260.08:03:18.96#ibcon#enter sib2, iclass 28, count 0 2006.260.08:03:18.96#ibcon#flushed, iclass 28, count 0 2006.260.08:03:18.96#ibcon#about to write, iclass 28, count 0 2006.260.08:03:18.96#ibcon#wrote, iclass 28, count 0 2006.260.08:03:18.96#ibcon#about to read 3, iclass 28, count 0 2006.260.08:03:19.01#ibcon#read 3, iclass 28, count 0 2006.260.08:03:19.01#ibcon#about to read 4, iclass 28, count 0 2006.260.08:03:19.01#ibcon#read 4, iclass 28, count 0 2006.260.08:03:19.01#ibcon#about to read 5, iclass 28, count 0 2006.260.08:03:19.01#ibcon#read 5, iclass 28, count 0 2006.260.08:03:19.01#ibcon#about to read 6, iclass 28, count 0 2006.260.08:03:19.01#ibcon#read 6, iclass 28, count 0 2006.260.08:03:19.01#ibcon#end of sib2, iclass 28, count 0 2006.260.08:03:19.01#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:03:19.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:03:19.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:03:19.01#ibcon#*before write, iclass 28, count 0 2006.260.08:03:19.01#ibcon#enter sib2, iclass 28, count 0 2006.260.08:03:19.01#ibcon#flushed, iclass 28, count 0 2006.260.08:03:19.01#ibcon#about to write, iclass 28, count 0 2006.260.08:03:19.01#ibcon#wrote, iclass 28, count 0 2006.260.08:03:19.01#ibcon#about to read 3, iclass 28, count 0 2006.260.08:03:19.06#ibcon#read 3, iclass 28, count 0 2006.260.08:03:19.06#ibcon#about to read 4, iclass 28, count 0 2006.260.08:03:19.06#ibcon#read 4, iclass 28, count 0 2006.260.08:03:19.06#ibcon#about to read 5, iclass 28, count 0 2006.260.08:03:19.06#ibcon#read 5, iclass 28, count 0 2006.260.08:03:19.06#ibcon#about to read 6, iclass 28, count 0 2006.260.08:03:19.06#ibcon#read 6, iclass 28, count 0 2006.260.08:03:19.06#ibcon#end of sib2, iclass 28, count 0 2006.260.08:03:19.06#ibcon#*after write, iclass 28, count 0 2006.260.08:03:19.06#ibcon#*before return 0, iclass 28, count 0 2006.260.08:03:19.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:19.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:19.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:03:19.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:03:19.06$vc4f8/va=1,8 2006.260.08:03:19.06#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:03:19.06#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:03:19.06#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:19.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:19.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:19.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:19.06#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:03:19.06#ibcon#first serial, iclass 30, count 2 2006.260.08:03:19.06#ibcon#enter sib2, iclass 30, count 2 2006.260.08:03:19.06#ibcon#flushed, iclass 30, count 2 2006.260.08:03:19.06#ibcon#about to write, iclass 30, count 2 2006.260.08:03:19.06#ibcon#wrote, iclass 30, count 2 2006.260.08:03:19.06#ibcon#about to read 3, iclass 30, count 2 2006.260.08:03:19.09#ibcon#read 3, iclass 30, count 2 2006.260.08:03:19.09#ibcon#about to read 4, iclass 30, count 2 2006.260.08:03:19.09#ibcon#read 4, iclass 30, count 2 2006.260.08:03:19.09#ibcon#about to read 5, iclass 30, count 2 2006.260.08:03:19.09#ibcon#read 5, iclass 30, count 2 2006.260.08:03:19.09#ibcon#about to read 6, iclass 30, count 2 2006.260.08:03:19.09#ibcon#read 6, iclass 30, count 2 2006.260.08:03:19.09#ibcon#end of sib2, iclass 30, count 2 2006.260.08:03:19.09#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:03:19.09#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:03:19.09#ibcon#[25=AT01-08\r\n] 2006.260.08:03:19.09#ibcon#*before write, iclass 30, count 2 2006.260.08:03:19.09#ibcon#enter sib2, iclass 30, count 2 2006.260.08:03:19.09#ibcon#flushed, iclass 30, count 2 2006.260.08:03:19.09#ibcon#about to write, iclass 30, count 2 2006.260.08:03:19.09#ibcon#wrote, iclass 30, count 2 2006.260.08:03:19.09#ibcon#about to read 3, iclass 30, count 2 2006.260.08:03:19.12#ibcon#read 3, iclass 30, count 2 2006.260.08:03:19.12#ibcon#about to read 4, iclass 30, count 2 2006.260.08:03:19.12#ibcon#read 4, iclass 30, count 2 2006.260.08:03:19.12#ibcon#about to read 5, iclass 30, count 2 2006.260.08:03:19.12#ibcon#read 5, iclass 30, count 2 2006.260.08:03:19.12#ibcon#about to read 6, iclass 30, count 2 2006.260.08:03:19.12#ibcon#read 6, iclass 30, count 2 2006.260.08:03:19.12#ibcon#end of sib2, iclass 30, count 2 2006.260.08:03:19.12#ibcon#*after write, iclass 30, count 2 2006.260.08:03:19.12#ibcon#*before return 0, iclass 30, count 2 2006.260.08:03:19.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:19.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:19.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:03:19.12#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:19.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:19.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:19.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:19.24#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:03:19.24#ibcon#first serial, iclass 30, count 0 2006.260.08:03:19.24#ibcon#enter sib2, iclass 30, count 0 2006.260.08:03:19.24#ibcon#flushed, iclass 30, count 0 2006.260.08:03:19.24#ibcon#about to write, iclass 30, count 0 2006.260.08:03:19.24#ibcon#wrote, iclass 30, count 0 2006.260.08:03:19.24#ibcon#about to read 3, iclass 30, count 0 2006.260.08:03:19.26#ibcon#read 3, iclass 30, count 0 2006.260.08:03:19.26#ibcon#about to read 4, iclass 30, count 0 2006.260.08:03:19.26#ibcon#read 4, iclass 30, count 0 2006.260.08:03:19.26#ibcon#about to read 5, iclass 30, count 0 2006.260.08:03:19.26#ibcon#read 5, iclass 30, count 0 2006.260.08:03:19.26#ibcon#about to read 6, iclass 30, count 0 2006.260.08:03:19.26#ibcon#read 6, iclass 30, count 0 2006.260.08:03:19.26#ibcon#end of sib2, iclass 30, count 0 2006.260.08:03:19.26#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:03:19.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:03:19.26#ibcon#[25=USB\r\n] 2006.260.08:03:19.26#ibcon#*before write, iclass 30, count 0 2006.260.08:03:19.26#ibcon#enter sib2, iclass 30, count 0 2006.260.08:03:19.26#ibcon#flushed, iclass 30, count 0 2006.260.08:03:19.26#ibcon#about to write, iclass 30, count 0 2006.260.08:03:19.26#ibcon#wrote, iclass 30, count 0 2006.260.08:03:19.26#ibcon#about to read 3, iclass 30, count 0 2006.260.08:03:19.29#ibcon#read 3, iclass 30, count 0 2006.260.08:03:19.29#ibcon#about to read 4, iclass 30, count 0 2006.260.08:03:19.29#ibcon#read 4, iclass 30, count 0 2006.260.08:03:19.29#ibcon#about to read 5, iclass 30, count 0 2006.260.08:03:19.29#ibcon#read 5, iclass 30, count 0 2006.260.08:03:19.29#ibcon#about to read 6, iclass 30, count 0 2006.260.08:03:19.29#ibcon#read 6, iclass 30, count 0 2006.260.08:03:19.29#ibcon#end of sib2, iclass 30, count 0 2006.260.08:03:19.29#ibcon#*after write, iclass 30, count 0 2006.260.08:03:19.29#ibcon#*before return 0, iclass 30, count 0 2006.260.08:03:19.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:19.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:19.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:03:19.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:03:19.29$vc4f8/valo=2,572.99 2006.260.08:03:19.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:03:19.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:03:19.29#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:19.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:19.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:19.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:19.29#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:03:19.29#ibcon#first serial, iclass 32, count 0 2006.260.08:03:19.29#ibcon#enter sib2, iclass 32, count 0 2006.260.08:03:19.29#ibcon#flushed, iclass 32, count 0 2006.260.08:03:19.29#ibcon#about to write, iclass 32, count 0 2006.260.08:03:19.29#ibcon#wrote, iclass 32, count 0 2006.260.08:03:19.29#ibcon#about to read 3, iclass 32, count 0 2006.260.08:03:19.31#ibcon#read 3, iclass 32, count 0 2006.260.08:03:19.31#ibcon#about to read 4, iclass 32, count 0 2006.260.08:03:19.31#ibcon#read 4, iclass 32, count 0 2006.260.08:03:19.31#ibcon#about to read 5, iclass 32, count 0 2006.260.08:03:19.31#ibcon#read 5, iclass 32, count 0 2006.260.08:03:19.31#ibcon#about to read 6, iclass 32, count 0 2006.260.08:03:19.31#ibcon#read 6, iclass 32, count 0 2006.260.08:03:19.31#ibcon#end of sib2, iclass 32, count 0 2006.260.08:03:19.31#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:03:19.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:03:19.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:03:19.31#ibcon#*before write, iclass 32, count 0 2006.260.08:03:19.31#ibcon#enter sib2, iclass 32, count 0 2006.260.08:03:19.31#ibcon#flushed, iclass 32, count 0 2006.260.08:03:19.31#ibcon#about to write, iclass 32, count 0 2006.260.08:03:19.31#ibcon#wrote, iclass 32, count 0 2006.260.08:03:19.31#ibcon#about to read 3, iclass 32, count 0 2006.260.08:03:19.35#ibcon#read 3, iclass 32, count 0 2006.260.08:03:19.35#ibcon#about to read 4, iclass 32, count 0 2006.260.08:03:19.35#ibcon#read 4, iclass 32, count 0 2006.260.08:03:19.35#ibcon#about to read 5, iclass 32, count 0 2006.260.08:03:19.35#ibcon#read 5, iclass 32, count 0 2006.260.08:03:19.35#ibcon#about to read 6, iclass 32, count 0 2006.260.08:03:19.35#ibcon#read 6, iclass 32, count 0 2006.260.08:03:19.35#ibcon#end of sib2, iclass 32, count 0 2006.260.08:03:19.35#ibcon#*after write, iclass 32, count 0 2006.260.08:03:19.35#ibcon#*before return 0, iclass 32, count 0 2006.260.08:03:19.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:19.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:19.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:03:19.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:03:19.35$vc4f8/va=2,7 2006.260.08:03:19.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.08:03:19.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.08:03:19.35#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:19.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:19.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:19.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:19.41#ibcon#enter wrdev, iclass 34, count 2 2006.260.08:03:19.41#ibcon#first serial, iclass 34, count 2 2006.260.08:03:19.41#ibcon#enter sib2, iclass 34, count 2 2006.260.08:03:19.41#ibcon#flushed, iclass 34, count 2 2006.260.08:03:19.41#ibcon#about to write, iclass 34, count 2 2006.260.08:03:19.41#ibcon#wrote, iclass 34, count 2 2006.260.08:03:19.41#ibcon#about to read 3, iclass 34, count 2 2006.260.08:03:19.44#ibcon#read 3, iclass 34, count 2 2006.260.08:03:19.44#ibcon#about to read 4, iclass 34, count 2 2006.260.08:03:19.44#ibcon#read 4, iclass 34, count 2 2006.260.08:03:19.44#ibcon#about to read 5, iclass 34, count 2 2006.260.08:03:19.44#ibcon#read 5, iclass 34, count 2 2006.260.08:03:19.44#ibcon#about to read 6, iclass 34, count 2 2006.260.08:03:19.44#ibcon#read 6, iclass 34, count 2 2006.260.08:03:19.44#ibcon#end of sib2, iclass 34, count 2 2006.260.08:03:19.44#ibcon#*mode == 0, iclass 34, count 2 2006.260.08:03:19.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.08:03:19.44#ibcon#[25=AT02-07\r\n] 2006.260.08:03:19.44#ibcon#*before write, iclass 34, count 2 2006.260.08:03:19.44#ibcon#enter sib2, iclass 34, count 2 2006.260.08:03:19.44#ibcon#flushed, iclass 34, count 2 2006.260.08:03:19.44#ibcon#about to write, iclass 34, count 2 2006.260.08:03:19.44#ibcon#wrote, iclass 34, count 2 2006.260.08:03:19.44#ibcon#about to read 3, iclass 34, count 2 2006.260.08:03:19.47#ibcon#read 3, iclass 34, count 2 2006.260.08:03:19.47#ibcon#about to read 4, iclass 34, count 2 2006.260.08:03:19.47#ibcon#read 4, iclass 34, count 2 2006.260.08:03:19.47#ibcon#about to read 5, iclass 34, count 2 2006.260.08:03:19.47#ibcon#read 5, iclass 34, count 2 2006.260.08:03:19.47#ibcon#about to read 6, iclass 34, count 2 2006.260.08:03:19.47#ibcon#read 6, iclass 34, count 2 2006.260.08:03:19.47#ibcon#end of sib2, iclass 34, count 2 2006.260.08:03:19.47#ibcon#*after write, iclass 34, count 2 2006.260.08:03:19.47#ibcon#*before return 0, iclass 34, count 2 2006.260.08:03:19.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:19.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:19.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.08:03:19.47#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:19.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:19.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:19.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:19.59#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:03:19.59#ibcon#first serial, iclass 34, count 0 2006.260.08:03:19.59#ibcon#enter sib2, iclass 34, count 0 2006.260.08:03:19.59#ibcon#flushed, iclass 34, count 0 2006.260.08:03:19.59#ibcon#about to write, iclass 34, count 0 2006.260.08:03:19.59#ibcon#wrote, iclass 34, count 0 2006.260.08:03:19.59#ibcon#about to read 3, iclass 34, count 0 2006.260.08:03:19.61#ibcon#read 3, iclass 34, count 0 2006.260.08:03:19.61#ibcon#about to read 4, iclass 34, count 0 2006.260.08:03:19.61#ibcon#read 4, iclass 34, count 0 2006.260.08:03:19.61#ibcon#about to read 5, iclass 34, count 0 2006.260.08:03:19.61#ibcon#read 5, iclass 34, count 0 2006.260.08:03:19.61#ibcon#about to read 6, iclass 34, count 0 2006.260.08:03:19.61#ibcon#read 6, iclass 34, count 0 2006.260.08:03:19.61#ibcon#end of sib2, iclass 34, count 0 2006.260.08:03:19.61#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:03:19.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:03:19.61#ibcon#[25=USB\r\n] 2006.260.08:03:19.61#ibcon#*before write, iclass 34, count 0 2006.260.08:03:19.61#ibcon#enter sib2, iclass 34, count 0 2006.260.08:03:19.61#ibcon#flushed, iclass 34, count 0 2006.260.08:03:19.61#ibcon#about to write, iclass 34, count 0 2006.260.08:03:19.61#ibcon#wrote, iclass 34, count 0 2006.260.08:03:19.61#ibcon#about to read 3, iclass 34, count 0 2006.260.08:03:19.64#ibcon#read 3, iclass 34, count 0 2006.260.08:03:19.64#ibcon#about to read 4, iclass 34, count 0 2006.260.08:03:19.64#ibcon#read 4, iclass 34, count 0 2006.260.08:03:19.64#ibcon#about to read 5, iclass 34, count 0 2006.260.08:03:19.64#ibcon#read 5, iclass 34, count 0 2006.260.08:03:19.64#ibcon#about to read 6, iclass 34, count 0 2006.260.08:03:19.64#ibcon#read 6, iclass 34, count 0 2006.260.08:03:19.64#ibcon#end of sib2, iclass 34, count 0 2006.260.08:03:19.64#ibcon#*after write, iclass 34, count 0 2006.260.08:03:19.64#ibcon#*before return 0, iclass 34, count 0 2006.260.08:03:19.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:19.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:19.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:03:19.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:03:19.64$vc4f8/valo=3,672.99 2006.260.08:03:19.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:03:19.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:03:19.64#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:19.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:19.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:19.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:19.64#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:03:19.64#ibcon#first serial, iclass 36, count 0 2006.260.08:03:19.64#ibcon#enter sib2, iclass 36, count 0 2006.260.08:03:19.64#ibcon#flushed, iclass 36, count 0 2006.260.08:03:19.64#ibcon#about to write, iclass 36, count 0 2006.260.08:03:19.64#ibcon#wrote, iclass 36, count 0 2006.260.08:03:19.64#ibcon#about to read 3, iclass 36, count 0 2006.260.08:03:19.66#ibcon#read 3, iclass 36, count 0 2006.260.08:03:19.66#ibcon#about to read 4, iclass 36, count 0 2006.260.08:03:19.66#ibcon#read 4, iclass 36, count 0 2006.260.08:03:19.66#ibcon#about to read 5, iclass 36, count 0 2006.260.08:03:19.66#ibcon#read 5, iclass 36, count 0 2006.260.08:03:19.66#ibcon#about to read 6, iclass 36, count 0 2006.260.08:03:19.66#ibcon#read 6, iclass 36, count 0 2006.260.08:03:19.66#ibcon#end of sib2, iclass 36, count 0 2006.260.08:03:19.66#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:03:19.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:03:19.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:03:19.66#ibcon#*before write, iclass 36, count 0 2006.260.08:03:19.66#ibcon#enter sib2, iclass 36, count 0 2006.260.08:03:19.66#ibcon#flushed, iclass 36, count 0 2006.260.08:03:19.66#ibcon#about to write, iclass 36, count 0 2006.260.08:03:19.66#ibcon#wrote, iclass 36, count 0 2006.260.08:03:19.66#ibcon#about to read 3, iclass 36, count 0 2006.260.08:03:19.70#ibcon#read 3, iclass 36, count 0 2006.260.08:03:19.70#ibcon#about to read 4, iclass 36, count 0 2006.260.08:03:19.70#ibcon#read 4, iclass 36, count 0 2006.260.08:03:19.70#ibcon#about to read 5, iclass 36, count 0 2006.260.08:03:19.70#ibcon#read 5, iclass 36, count 0 2006.260.08:03:19.70#ibcon#about to read 6, iclass 36, count 0 2006.260.08:03:19.70#ibcon#read 6, iclass 36, count 0 2006.260.08:03:19.70#ibcon#end of sib2, iclass 36, count 0 2006.260.08:03:19.70#ibcon#*after write, iclass 36, count 0 2006.260.08:03:19.70#ibcon#*before return 0, iclass 36, count 0 2006.260.08:03:19.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:19.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:19.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:03:19.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:03:19.70$vc4f8/va=3,8 2006.260.08:03:19.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.08:03:19.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.08:03:19.70#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:19.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:19.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:19.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:19.76#ibcon#enter wrdev, iclass 38, count 2 2006.260.08:03:19.76#ibcon#first serial, iclass 38, count 2 2006.260.08:03:19.76#ibcon#enter sib2, iclass 38, count 2 2006.260.08:03:19.76#ibcon#flushed, iclass 38, count 2 2006.260.08:03:19.76#ibcon#about to write, iclass 38, count 2 2006.260.08:03:19.76#ibcon#wrote, iclass 38, count 2 2006.260.08:03:19.76#ibcon#about to read 3, iclass 38, count 2 2006.260.08:03:19.79#ibcon#read 3, iclass 38, count 2 2006.260.08:03:19.79#ibcon#about to read 4, iclass 38, count 2 2006.260.08:03:19.79#ibcon#read 4, iclass 38, count 2 2006.260.08:03:19.79#ibcon#about to read 5, iclass 38, count 2 2006.260.08:03:19.79#ibcon#read 5, iclass 38, count 2 2006.260.08:03:19.79#ibcon#about to read 6, iclass 38, count 2 2006.260.08:03:19.79#ibcon#read 6, iclass 38, count 2 2006.260.08:03:19.79#ibcon#end of sib2, iclass 38, count 2 2006.260.08:03:19.79#ibcon#*mode == 0, iclass 38, count 2 2006.260.08:03:19.79#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.08:03:19.79#ibcon#[25=AT03-08\r\n] 2006.260.08:03:19.79#ibcon#*before write, iclass 38, count 2 2006.260.08:03:19.79#ibcon#enter sib2, iclass 38, count 2 2006.260.08:03:19.79#ibcon#flushed, iclass 38, count 2 2006.260.08:03:19.79#ibcon#about to write, iclass 38, count 2 2006.260.08:03:19.79#ibcon#wrote, iclass 38, count 2 2006.260.08:03:19.79#ibcon#about to read 3, iclass 38, count 2 2006.260.08:03:19.82#ibcon#read 3, iclass 38, count 2 2006.260.08:03:19.82#ibcon#about to read 4, iclass 38, count 2 2006.260.08:03:19.82#ibcon#read 4, iclass 38, count 2 2006.260.08:03:19.82#ibcon#about to read 5, iclass 38, count 2 2006.260.08:03:19.82#ibcon#read 5, iclass 38, count 2 2006.260.08:03:19.82#ibcon#about to read 6, iclass 38, count 2 2006.260.08:03:19.82#ibcon#read 6, iclass 38, count 2 2006.260.08:03:19.82#ibcon#end of sib2, iclass 38, count 2 2006.260.08:03:19.82#ibcon#*after write, iclass 38, count 2 2006.260.08:03:19.82#ibcon#*before return 0, iclass 38, count 2 2006.260.08:03:19.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:19.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:19.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.08:03:19.82#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:19.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:19.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:19.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:19.94#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:03:19.94#ibcon#first serial, iclass 38, count 0 2006.260.08:03:19.94#ibcon#enter sib2, iclass 38, count 0 2006.260.08:03:19.94#ibcon#flushed, iclass 38, count 0 2006.260.08:03:19.94#ibcon#about to write, iclass 38, count 0 2006.260.08:03:19.94#ibcon#wrote, iclass 38, count 0 2006.260.08:03:19.94#ibcon#about to read 3, iclass 38, count 0 2006.260.08:03:19.96#ibcon#read 3, iclass 38, count 0 2006.260.08:03:19.96#ibcon#about to read 4, iclass 38, count 0 2006.260.08:03:19.96#ibcon#read 4, iclass 38, count 0 2006.260.08:03:19.96#ibcon#about to read 5, iclass 38, count 0 2006.260.08:03:19.96#ibcon#read 5, iclass 38, count 0 2006.260.08:03:19.96#ibcon#about to read 6, iclass 38, count 0 2006.260.08:03:19.96#ibcon#read 6, iclass 38, count 0 2006.260.08:03:19.96#ibcon#end of sib2, iclass 38, count 0 2006.260.08:03:19.96#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:03:19.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:03:19.96#ibcon#[25=USB\r\n] 2006.260.08:03:19.96#ibcon#*before write, iclass 38, count 0 2006.260.08:03:19.96#ibcon#enter sib2, iclass 38, count 0 2006.260.08:03:19.96#ibcon#flushed, iclass 38, count 0 2006.260.08:03:19.96#ibcon#about to write, iclass 38, count 0 2006.260.08:03:19.96#ibcon#wrote, iclass 38, count 0 2006.260.08:03:19.96#ibcon#about to read 3, iclass 38, count 0 2006.260.08:03:19.99#ibcon#read 3, iclass 38, count 0 2006.260.08:03:19.99#ibcon#about to read 4, iclass 38, count 0 2006.260.08:03:19.99#ibcon#read 4, iclass 38, count 0 2006.260.08:03:19.99#ibcon#about to read 5, iclass 38, count 0 2006.260.08:03:19.99#ibcon#read 5, iclass 38, count 0 2006.260.08:03:19.99#ibcon#about to read 6, iclass 38, count 0 2006.260.08:03:19.99#ibcon#read 6, iclass 38, count 0 2006.260.08:03:19.99#ibcon#end of sib2, iclass 38, count 0 2006.260.08:03:19.99#ibcon#*after write, iclass 38, count 0 2006.260.08:03:19.99#ibcon#*before return 0, iclass 38, count 0 2006.260.08:03:19.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:19.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:19.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:03:19.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:03:19.99$vc4f8/valo=4,832.99 2006.260.08:03:19.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.08:03:19.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.08:03:19.99#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:19.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:19.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:19.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:19.99#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:03:19.99#ibcon#first serial, iclass 40, count 0 2006.260.08:03:19.99#ibcon#enter sib2, iclass 40, count 0 2006.260.08:03:19.99#ibcon#flushed, iclass 40, count 0 2006.260.08:03:19.99#ibcon#about to write, iclass 40, count 0 2006.260.08:03:19.99#ibcon#wrote, iclass 40, count 0 2006.260.08:03:19.99#ibcon#about to read 3, iclass 40, count 0 2006.260.08:03:20.01#ibcon#read 3, iclass 40, count 0 2006.260.08:03:20.01#ibcon#about to read 4, iclass 40, count 0 2006.260.08:03:20.01#ibcon#read 4, iclass 40, count 0 2006.260.08:03:20.01#ibcon#about to read 5, iclass 40, count 0 2006.260.08:03:20.01#ibcon#read 5, iclass 40, count 0 2006.260.08:03:20.01#ibcon#about to read 6, iclass 40, count 0 2006.260.08:03:20.01#ibcon#read 6, iclass 40, count 0 2006.260.08:03:20.01#ibcon#end of sib2, iclass 40, count 0 2006.260.08:03:20.01#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:03:20.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:03:20.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:03:20.01#ibcon#*before write, iclass 40, count 0 2006.260.08:03:20.01#ibcon#enter sib2, iclass 40, count 0 2006.260.08:03:20.01#ibcon#flushed, iclass 40, count 0 2006.260.08:03:20.01#ibcon#about to write, iclass 40, count 0 2006.260.08:03:20.01#ibcon#wrote, iclass 40, count 0 2006.260.08:03:20.01#ibcon#about to read 3, iclass 40, count 0 2006.260.08:03:20.05#ibcon#read 3, iclass 40, count 0 2006.260.08:03:20.05#ibcon#about to read 4, iclass 40, count 0 2006.260.08:03:20.05#ibcon#read 4, iclass 40, count 0 2006.260.08:03:20.05#ibcon#about to read 5, iclass 40, count 0 2006.260.08:03:20.05#ibcon#read 5, iclass 40, count 0 2006.260.08:03:20.05#ibcon#about to read 6, iclass 40, count 0 2006.260.08:03:20.05#ibcon#read 6, iclass 40, count 0 2006.260.08:03:20.05#ibcon#end of sib2, iclass 40, count 0 2006.260.08:03:20.05#ibcon#*after write, iclass 40, count 0 2006.260.08:03:20.05#ibcon#*before return 0, iclass 40, count 0 2006.260.08:03:20.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:20.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:20.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:03:20.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:03:20.05$vc4f8/va=4,7 2006.260.08:03:20.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.08:03:20.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.08:03:20.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:20.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:20.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:20.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:20.11#ibcon#enter wrdev, iclass 4, count 2 2006.260.08:03:20.11#ibcon#first serial, iclass 4, count 2 2006.260.08:03:20.11#ibcon#enter sib2, iclass 4, count 2 2006.260.08:03:20.11#ibcon#flushed, iclass 4, count 2 2006.260.08:03:20.11#ibcon#about to write, iclass 4, count 2 2006.260.08:03:20.11#ibcon#wrote, iclass 4, count 2 2006.260.08:03:20.11#ibcon#about to read 3, iclass 4, count 2 2006.260.08:03:20.13#ibcon#read 3, iclass 4, count 2 2006.260.08:03:20.13#ibcon#about to read 4, iclass 4, count 2 2006.260.08:03:20.13#ibcon#read 4, iclass 4, count 2 2006.260.08:03:20.13#ibcon#about to read 5, iclass 4, count 2 2006.260.08:03:20.13#ibcon#read 5, iclass 4, count 2 2006.260.08:03:20.13#ibcon#about to read 6, iclass 4, count 2 2006.260.08:03:20.13#ibcon#read 6, iclass 4, count 2 2006.260.08:03:20.13#ibcon#end of sib2, iclass 4, count 2 2006.260.08:03:20.13#ibcon#*mode == 0, iclass 4, count 2 2006.260.08:03:20.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.08:03:20.13#ibcon#[25=AT04-07\r\n] 2006.260.08:03:20.13#ibcon#*before write, iclass 4, count 2 2006.260.08:03:20.13#ibcon#enter sib2, iclass 4, count 2 2006.260.08:03:20.13#ibcon#flushed, iclass 4, count 2 2006.260.08:03:20.13#ibcon#about to write, iclass 4, count 2 2006.260.08:03:20.13#ibcon#wrote, iclass 4, count 2 2006.260.08:03:20.13#ibcon#about to read 3, iclass 4, count 2 2006.260.08:03:20.16#ibcon#read 3, iclass 4, count 2 2006.260.08:03:20.16#ibcon#about to read 4, iclass 4, count 2 2006.260.08:03:20.16#ibcon#read 4, iclass 4, count 2 2006.260.08:03:20.16#ibcon#about to read 5, iclass 4, count 2 2006.260.08:03:20.16#ibcon#read 5, iclass 4, count 2 2006.260.08:03:20.16#ibcon#about to read 6, iclass 4, count 2 2006.260.08:03:20.16#ibcon#read 6, iclass 4, count 2 2006.260.08:03:20.16#ibcon#end of sib2, iclass 4, count 2 2006.260.08:03:20.16#ibcon#*after write, iclass 4, count 2 2006.260.08:03:20.16#ibcon#*before return 0, iclass 4, count 2 2006.260.08:03:20.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:20.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:20.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.08:03:20.16#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:20.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:20.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:20.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:20.28#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:03:20.28#ibcon#first serial, iclass 4, count 0 2006.260.08:03:20.28#ibcon#enter sib2, iclass 4, count 0 2006.260.08:03:20.28#ibcon#flushed, iclass 4, count 0 2006.260.08:03:20.28#ibcon#about to write, iclass 4, count 0 2006.260.08:03:20.28#ibcon#wrote, iclass 4, count 0 2006.260.08:03:20.28#ibcon#about to read 3, iclass 4, count 0 2006.260.08:03:20.30#ibcon#read 3, iclass 4, count 0 2006.260.08:03:20.30#ibcon#about to read 4, iclass 4, count 0 2006.260.08:03:20.30#ibcon#read 4, iclass 4, count 0 2006.260.08:03:20.30#ibcon#about to read 5, iclass 4, count 0 2006.260.08:03:20.30#ibcon#read 5, iclass 4, count 0 2006.260.08:03:20.30#ibcon#about to read 6, iclass 4, count 0 2006.260.08:03:20.30#ibcon#read 6, iclass 4, count 0 2006.260.08:03:20.30#ibcon#end of sib2, iclass 4, count 0 2006.260.08:03:20.30#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:03:20.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:03:20.30#ibcon#[25=USB\r\n] 2006.260.08:03:20.30#ibcon#*before write, iclass 4, count 0 2006.260.08:03:20.30#ibcon#enter sib2, iclass 4, count 0 2006.260.08:03:20.30#ibcon#flushed, iclass 4, count 0 2006.260.08:03:20.30#ibcon#about to write, iclass 4, count 0 2006.260.08:03:20.30#ibcon#wrote, iclass 4, count 0 2006.260.08:03:20.30#ibcon#about to read 3, iclass 4, count 0 2006.260.08:03:20.33#ibcon#read 3, iclass 4, count 0 2006.260.08:03:20.33#ibcon#about to read 4, iclass 4, count 0 2006.260.08:03:20.33#ibcon#read 4, iclass 4, count 0 2006.260.08:03:20.33#ibcon#about to read 5, iclass 4, count 0 2006.260.08:03:20.33#ibcon#read 5, iclass 4, count 0 2006.260.08:03:20.33#ibcon#about to read 6, iclass 4, count 0 2006.260.08:03:20.33#ibcon#read 6, iclass 4, count 0 2006.260.08:03:20.33#ibcon#end of sib2, iclass 4, count 0 2006.260.08:03:20.33#ibcon#*after write, iclass 4, count 0 2006.260.08:03:20.33#ibcon#*before return 0, iclass 4, count 0 2006.260.08:03:20.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:20.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:20.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:03:20.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:03:20.33$vc4f8/valo=5,652.99 2006.260.08:03:20.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:03:20.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:03:20.33#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:20.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:20.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:20.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:20.33#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:03:20.33#ibcon#first serial, iclass 6, count 0 2006.260.08:03:20.33#ibcon#enter sib2, iclass 6, count 0 2006.260.08:03:20.33#ibcon#flushed, iclass 6, count 0 2006.260.08:03:20.33#ibcon#about to write, iclass 6, count 0 2006.260.08:03:20.33#ibcon#wrote, iclass 6, count 0 2006.260.08:03:20.33#ibcon#about to read 3, iclass 6, count 0 2006.260.08:03:20.35#ibcon#read 3, iclass 6, count 0 2006.260.08:03:20.35#ibcon#about to read 4, iclass 6, count 0 2006.260.08:03:20.35#ibcon#read 4, iclass 6, count 0 2006.260.08:03:20.35#ibcon#about to read 5, iclass 6, count 0 2006.260.08:03:20.35#ibcon#read 5, iclass 6, count 0 2006.260.08:03:20.35#ibcon#about to read 6, iclass 6, count 0 2006.260.08:03:20.35#ibcon#read 6, iclass 6, count 0 2006.260.08:03:20.35#ibcon#end of sib2, iclass 6, count 0 2006.260.08:03:20.35#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:03:20.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:03:20.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:03:20.35#ibcon#*before write, iclass 6, count 0 2006.260.08:03:20.35#ibcon#enter sib2, iclass 6, count 0 2006.260.08:03:20.35#ibcon#flushed, iclass 6, count 0 2006.260.08:03:20.35#ibcon#about to write, iclass 6, count 0 2006.260.08:03:20.35#ibcon#wrote, iclass 6, count 0 2006.260.08:03:20.35#ibcon#about to read 3, iclass 6, count 0 2006.260.08:03:20.39#ibcon#read 3, iclass 6, count 0 2006.260.08:03:20.39#ibcon#about to read 4, iclass 6, count 0 2006.260.08:03:20.39#ibcon#read 4, iclass 6, count 0 2006.260.08:03:20.39#ibcon#about to read 5, iclass 6, count 0 2006.260.08:03:20.39#ibcon#read 5, iclass 6, count 0 2006.260.08:03:20.39#ibcon#about to read 6, iclass 6, count 0 2006.260.08:03:20.39#ibcon#read 6, iclass 6, count 0 2006.260.08:03:20.39#ibcon#end of sib2, iclass 6, count 0 2006.260.08:03:20.39#ibcon#*after write, iclass 6, count 0 2006.260.08:03:20.39#ibcon#*before return 0, iclass 6, count 0 2006.260.08:03:20.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:20.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:20.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:03:20.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:03:20.39$vc4f8/va=5,7 2006.260.08:03:20.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.08:03:20.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.08:03:20.39#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:20.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:20.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:20.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:20.45#ibcon#enter wrdev, iclass 10, count 2 2006.260.08:03:20.45#ibcon#first serial, iclass 10, count 2 2006.260.08:03:20.45#ibcon#enter sib2, iclass 10, count 2 2006.260.08:03:20.45#ibcon#flushed, iclass 10, count 2 2006.260.08:03:20.45#ibcon#about to write, iclass 10, count 2 2006.260.08:03:20.45#ibcon#wrote, iclass 10, count 2 2006.260.08:03:20.45#ibcon#about to read 3, iclass 10, count 2 2006.260.08:03:20.47#ibcon#read 3, iclass 10, count 2 2006.260.08:03:20.47#ibcon#about to read 4, iclass 10, count 2 2006.260.08:03:20.47#ibcon#read 4, iclass 10, count 2 2006.260.08:03:20.47#ibcon#about to read 5, iclass 10, count 2 2006.260.08:03:20.47#ibcon#read 5, iclass 10, count 2 2006.260.08:03:20.47#ibcon#about to read 6, iclass 10, count 2 2006.260.08:03:20.47#ibcon#read 6, iclass 10, count 2 2006.260.08:03:20.47#ibcon#end of sib2, iclass 10, count 2 2006.260.08:03:20.47#ibcon#*mode == 0, iclass 10, count 2 2006.260.08:03:20.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.08:03:20.47#ibcon#[25=AT05-07\r\n] 2006.260.08:03:20.47#ibcon#*before write, iclass 10, count 2 2006.260.08:03:20.47#ibcon#enter sib2, iclass 10, count 2 2006.260.08:03:20.47#ibcon#flushed, iclass 10, count 2 2006.260.08:03:20.47#ibcon#about to write, iclass 10, count 2 2006.260.08:03:20.47#ibcon#wrote, iclass 10, count 2 2006.260.08:03:20.47#ibcon#about to read 3, iclass 10, count 2 2006.260.08:03:20.50#ibcon#read 3, iclass 10, count 2 2006.260.08:03:20.50#ibcon#about to read 4, iclass 10, count 2 2006.260.08:03:20.50#ibcon#read 4, iclass 10, count 2 2006.260.08:03:20.50#ibcon#about to read 5, iclass 10, count 2 2006.260.08:03:20.50#ibcon#read 5, iclass 10, count 2 2006.260.08:03:20.50#ibcon#about to read 6, iclass 10, count 2 2006.260.08:03:20.50#ibcon#read 6, iclass 10, count 2 2006.260.08:03:20.50#ibcon#end of sib2, iclass 10, count 2 2006.260.08:03:20.50#ibcon#*after write, iclass 10, count 2 2006.260.08:03:20.50#ibcon#*before return 0, iclass 10, count 2 2006.260.08:03:20.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:20.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:20.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.08:03:20.50#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:20.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:20.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:20.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:20.62#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:03:20.62#ibcon#first serial, iclass 10, count 0 2006.260.08:03:20.62#ibcon#enter sib2, iclass 10, count 0 2006.260.08:03:20.62#ibcon#flushed, iclass 10, count 0 2006.260.08:03:20.62#ibcon#about to write, iclass 10, count 0 2006.260.08:03:20.62#ibcon#wrote, iclass 10, count 0 2006.260.08:03:20.62#ibcon#about to read 3, iclass 10, count 0 2006.260.08:03:20.64#ibcon#read 3, iclass 10, count 0 2006.260.08:03:20.64#ibcon#about to read 4, iclass 10, count 0 2006.260.08:03:20.64#ibcon#read 4, iclass 10, count 0 2006.260.08:03:20.64#ibcon#about to read 5, iclass 10, count 0 2006.260.08:03:20.64#ibcon#read 5, iclass 10, count 0 2006.260.08:03:20.64#ibcon#about to read 6, iclass 10, count 0 2006.260.08:03:20.64#ibcon#read 6, iclass 10, count 0 2006.260.08:03:20.64#ibcon#end of sib2, iclass 10, count 0 2006.260.08:03:20.64#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:03:20.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:03:20.64#ibcon#[25=USB\r\n] 2006.260.08:03:20.64#ibcon#*before write, iclass 10, count 0 2006.260.08:03:20.64#ibcon#enter sib2, iclass 10, count 0 2006.260.08:03:20.64#ibcon#flushed, iclass 10, count 0 2006.260.08:03:20.64#ibcon#about to write, iclass 10, count 0 2006.260.08:03:20.64#ibcon#wrote, iclass 10, count 0 2006.260.08:03:20.64#ibcon#about to read 3, iclass 10, count 0 2006.260.08:03:20.67#ibcon#read 3, iclass 10, count 0 2006.260.08:03:20.67#ibcon#about to read 4, iclass 10, count 0 2006.260.08:03:20.67#ibcon#read 4, iclass 10, count 0 2006.260.08:03:20.67#ibcon#about to read 5, iclass 10, count 0 2006.260.08:03:20.67#ibcon#read 5, iclass 10, count 0 2006.260.08:03:20.67#ibcon#about to read 6, iclass 10, count 0 2006.260.08:03:20.67#ibcon#read 6, iclass 10, count 0 2006.260.08:03:20.67#ibcon#end of sib2, iclass 10, count 0 2006.260.08:03:20.67#ibcon#*after write, iclass 10, count 0 2006.260.08:03:20.67#ibcon#*before return 0, iclass 10, count 0 2006.260.08:03:20.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:20.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:20.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:03:20.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:03:20.67$vc4f8/valo=6,772.99 2006.260.08:03:20.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:03:20.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:03:20.67#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:20.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:20.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:20.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:20.67#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:03:20.67#ibcon#first serial, iclass 12, count 0 2006.260.08:03:20.67#ibcon#enter sib2, iclass 12, count 0 2006.260.08:03:20.67#ibcon#flushed, iclass 12, count 0 2006.260.08:03:20.67#ibcon#about to write, iclass 12, count 0 2006.260.08:03:20.67#ibcon#wrote, iclass 12, count 0 2006.260.08:03:20.67#ibcon#about to read 3, iclass 12, count 0 2006.260.08:03:20.69#ibcon#read 3, iclass 12, count 0 2006.260.08:03:20.69#ibcon#about to read 4, iclass 12, count 0 2006.260.08:03:20.69#ibcon#read 4, iclass 12, count 0 2006.260.08:03:20.69#ibcon#about to read 5, iclass 12, count 0 2006.260.08:03:20.69#ibcon#read 5, iclass 12, count 0 2006.260.08:03:20.69#ibcon#about to read 6, iclass 12, count 0 2006.260.08:03:20.69#ibcon#read 6, iclass 12, count 0 2006.260.08:03:20.69#ibcon#end of sib2, iclass 12, count 0 2006.260.08:03:20.69#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:03:20.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:03:20.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:03:20.69#ibcon#*before write, iclass 12, count 0 2006.260.08:03:20.69#ibcon#enter sib2, iclass 12, count 0 2006.260.08:03:20.69#ibcon#flushed, iclass 12, count 0 2006.260.08:03:20.69#ibcon#about to write, iclass 12, count 0 2006.260.08:03:20.69#ibcon#wrote, iclass 12, count 0 2006.260.08:03:20.69#ibcon#about to read 3, iclass 12, count 0 2006.260.08:03:20.73#ibcon#read 3, iclass 12, count 0 2006.260.08:03:20.73#ibcon#about to read 4, iclass 12, count 0 2006.260.08:03:20.73#ibcon#read 4, iclass 12, count 0 2006.260.08:03:20.73#ibcon#about to read 5, iclass 12, count 0 2006.260.08:03:20.73#ibcon#read 5, iclass 12, count 0 2006.260.08:03:20.73#ibcon#about to read 6, iclass 12, count 0 2006.260.08:03:20.73#ibcon#read 6, iclass 12, count 0 2006.260.08:03:20.73#ibcon#end of sib2, iclass 12, count 0 2006.260.08:03:20.73#ibcon#*after write, iclass 12, count 0 2006.260.08:03:20.73#ibcon#*before return 0, iclass 12, count 0 2006.260.08:03:20.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:20.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:20.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:03:20.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:03:20.73$vc4f8/va=6,6 2006.260.08:03:20.73#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.08:03:20.73#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.08:03:20.73#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:20.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:20.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:20.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:20.79#ibcon#enter wrdev, iclass 14, count 2 2006.260.08:03:20.79#ibcon#first serial, iclass 14, count 2 2006.260.08:03:20.79#ibcon#enter sib2, iclass 14, count 2 2006.260.08:03:20.79#ibcon#flushed, iclass 14, count 2 2006.260.08:03:20.79#ibcon#about to write, iclass 14, count 2 2006.260.08:03:20.79#ibcon#wrote, iclass 14, count 2 2006.260.08:03:20.79#ibcon#about to read 3, iclass 14, count 2 2006.260.08:03:20.81#ibcon#read 3, iclass 14, count 2 2006.260.08:03:20.81#ibcon#about to read 4, iclass 14, count 2 2006.260.08:03:20.81#ibcon#read 4, iclass 14, count 2 2006.260.08:03:20.81#ibcon#about to read 5, iclass 14, count 2 2006.260.08:03:20.81#ibcon#read 5, iclass 14, count 2 2006.260.08:03:20.81#ibcon#about to read 6, iclass 14, count 2 2006.260.08:03:20.81#ibcon#read 6, iclass 14, count 2 2006.260.08:03:20.81#ibcon#end of sib2, iclass 14, count 2 2006.260.08:03:20.81#ibcon#*mode == 0, iclass 14, count 2 2006.260.08:03:20.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.08:03:20.81#ibcon#[25=AT06-06\r\n] 2006.260.08:03:20.81#ibcon#*before write, iclass 14, count 2 2006.260.08:03:20.81#ibcon#enter sib2, iclass 14, count 2 2006.260.08:03:20.81#ibcon#flushed, iclass 14, count 2 2006.260.08:03:20.81#ibcon#about to write, iclass 14, count 2 2006.260.08:03:20.81#ibcon#wrote, iclass 14, count 2 2006.260.08:03:20.81#ibcon#about to read 3, iclass 14, count 2 2006.260.08:03:20.84#ibcon#read 3, iclass 14, count 2 2006.260.08:03:20.84#ibcon#about to read 4, iclass 14, count 2 2006.260.08:03:20.84#ibcon#read 4, iclass 14, count 2 2006.260.08:03:20.84#ibcon#about to read 5, iclass 14, count 2 2006.260.08:03:20.84#ibcon#read 5, iclass 14, count 2 2006.260.08:03:20.84#ibcon#about to read 6, iclass 14, count 2 2006.260.08:03:20.84#ibcon#read 6, iclass 14, count 2 2006.260.08:03:20.84#ibcon#end of sib2, iclass 14, count 2 2006.260.08:03:20.84#ibcon#*after write, iclass 14, count 2 2006.260.08:03:20.84#ibcon#*before return 0, iclass 14, count 2 2006.260.08:03:20.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:20.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:20.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.08:03:20.84#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:20.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:03:20.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:03:20.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:03:20.96#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:03:20.96#ibcon#first serial, iclass 14, count 0 2006.260.08:03:20.96#ibcon#enter sib2, iclass 14, count 0 2006.260.08:03:20.96#ibcon#flushed, iclass 14, count 0 2006.260.08:03:20.96#ibcon#about to write, iclass 14, count 0 2006.260.08:03:20.96#ibcon#wrote, iclass 14, count 0 2006.260.08:03:20.96#ibcon#about to read 3, iclass 14, count 0 2006.260.08:03:20.98#ibcon#read 3, iclass 14, count 0 2006.260.08:03:20.98#ibcon#about to read 4, iclass 14, count 0 2006.260.08:03:20.98#ibcon#read 4, iclass 14, count 0 2006.260.08:03:20.98#ibcon#about to read 5, iclass 14, count 0 2006.260.08:03:20.98#ibcon#read 5, iclass 14, count 0 2006.260.08:03:20.98#ibcon#about to read 6, iclass 14, count 0 2006.260.08:03:20.98#ibcon#read 6, iclass 14, count 0 2006.260.08:03:20.98#ibcon#end of sib2, iclass 14, count 0 2006.260.08:03:20.98#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:03:20.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:03:20.98#ibcon#[25=USB\r\n] 2006.260.08:03:20.98#ibcon#*before write, iclass 14, count 0 2006.260.08:03:20.98#ibcon#enter sib2, iclass 14, count 0 2006.260.08:03:20.98#ibcon#flushed, iclass 14, count 0 2006.260.08:03:20.98#ibcon#about to write, iclass 14, count 0 2006.260.08:03:20.98#ibcon#wrote, iclass 14, count 0 2006.260.08:03:20.98#ibcon#about to read 3, iclass 14, count 0 2006.260.08:03:21.01#ibcon#read 3, iclass 14, count 0 2006.260.08:03:21.01#ibcon#about to read 4, iclass 14, count 0 2006.260.08:03:21.01#ibcon#read 4, iclass 14, count 0 2006.260.08:03:21.01#ibcon#about to read 5, iclass 14, count 0 2006.260.08:03:21.01#ibcon#read 5, iclass 14, count 0 2006.260.08:03:21.01#ibcon#about to read 6, iclass 14, count 0 2006.260.08:03:21.01#ibcon#read 6, iclass 14, count 0 2006.260.08:03:21.01#ibcon#end of sib2, iclass 14, count 0 2006.260.08:03:21.01#ibcon#*after write, iclass 14, count 0 2006.260.08:03:21.01#ibcon#*before return 0, iclass 14, count 0 2006.260.08:03:21.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:03:21.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:03:21.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:03:21.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:03:21.01$vc4f8/valo=7,832.99 2006.260.08:03:21.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.08:03:21.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.08:03:21.01#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:21.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:03:21.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:03:21.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:03:21.01#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:03:21.01#ibcon#first serial, iclass 16, count 0 2006.260.08:03:21.01#ibcon#enter sib2, iclass 16, count 0 2006.260.08:03:21.01#ibcon#flushed, iclass 16, count 0 2006.260.08:03:21.01#ibcon#about to write, iclass 16, count 0 2006.260.08:03:21.01#ibcon#wrote, iclass 16, count 0 2006.260.08:03:21.01#ibcon#about to read 3, iclass 16, count 0 2006.260.08:03:21.03#ibcon#read 3, iclass 16, count 0 2006.260.08:03:21.03#ibcon#about to read 4, iclass 16, count 0 2006.260.08:03:21.03#ibcon#read 4, iclass 16, count 0 2006.260.08:03:21.03#ibcon#about to read 5, iclass 16, count 0 2006.260.08:03:21.03#ibcon#read 5, iclass 16, count 0 2006.260.08:03:21.03#ibcon#about to read 6, iclass 16, count 0 2006.260.08:03:21.03#ibcon#read 6, iclass 16, count 0 2006.260.08:03:21.03#ibcon#end of sib2, iclass 16, count 0 2006.260.08:03:21.03#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:03:21.03#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:03:21.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:03:21.03#ibcon#*before write, iclass 16, count 0 2006.260.08:03:21.03#ibcon#enter sib2, iclass 16, count 0 2006.260.08:03:21.03#ibcon#flushed, iclass 16, count 0 2006.260.08:03:21.03#ibcon#about to write, iclass 16, count 0 2006.260.08:03:21.03#ibcon#wrote, iclass 16, count 0 2006.260.08:03:21.03#ibcon#about to read 3, iclass 16, count 0 2006.260.08:03:21.07#ibcon#read 3, iclass 16, count 0 2006.260.08:03:21.07#ibcon#about to read 4, iclass 16, count 0 2006.260.08:03:21.07#ibcon#read 4, iclass 16, count 0 2006.260.08:03:21.07#ibcon#about to read 5, iclass 16, count 0 2006.260.08:03:21.07#ibcon#read 5, iclass 16, count 0 2006.260.08:03:21.07#ibcon#about to read 6, iclass 16, count 0 2006.260.08:03:21.07#ibcon#read 6, iclass 16, count 0 2006.260.08:03:21.07#ibcon#end of sib2, iclass 16, count 0 2006.260.08:03:21.07#ibcon#*after write, iclass 16, count 0 2006.260.08:03:21.07#ibcon#*before return 0, iclass 16, count 0 2006.260.08:03:21.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:03:21.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:03:21.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:03:21.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:03:21.07$vc4f8/va=7,6 2006.260.08:03:21.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.08:03:21.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.08:03:21.07#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:21.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:03:21.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:03:21.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:03:21.13#ibcon#enter wrdev, iclass 18, count 2 2006.260.08:03:21.13#ibcon#first serial, iclass 18, count 2 2006.260.08:03:21.13#ibcon#enter sib2, iclass 18, count 2 2006.260.08:03:21.13#ibcon#flushed, iclass 18, count 2 2006.260.08:03:21.13#ibcon#about to write, iclass 18, count 2 2006.260.08:03:21.13#ibcon#wrote, iclass 18, count 2 2006.260.08:03:21.13#ibcon#about to read 3, iclass 18, count 2 2006.260.08:03:21.15#ibcon#read 3, iclass 18, count 2 2006.260.08:03:21.15#ibcon#about to read 4, iclass 18, count 2 2006.260.08:03:21.15#ibcon#read 4, iclass 18, count 2 2006.260.08:03:21.15#ibcon#about to read 5, iclass 18, count 2 2006.260.08:03:21.15#ibcon#read 5, iclass 18, count 2 2006.260.08:03:21.15#ibcon#about to read 6, iclass 18, count 2 2006.260.08:03:21.15#ibcon#read 6, iclass 18, count 2 2006.260.08:03:21.15#ibcon#end of sib2, iclass 18, count 2 2006.260.08:03:21.15#ibcon#*mode == 0, iclass 18, count 2 2006.260.08:03:21.15#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.08:03:21.15#ibcon#[25=AT07-06\r\n] 2006.260.08:03:21.15#ibcon#*before write, iclass 18, count 2 2006.260.08:03:21.15#ibcon#enter sib2, iclass 18, count 2 2006.260.08:03:21.15#ibcon#flushed, iclass 18, count 2 2006.260.08:03:21.15#ibcon#about to write, iclass 18, count 2 2006.260.08:03:21.15#ibcon#wrote, iclass 18, count 2 2006.260.08:03:21.15#ibcon#about to read 3, iclass 18, count 2 2006.260.08:03:21.18#ibcon#read 3, iclass 18, count 2 2006.260.08:03:21.18#ibcon#about to read 4, iclass 18, count 2 2006.260.08:03:21.18#ibcon#read 4, iclass 18, count 2 2006.260.08:03:21.18#ibcon#about to read 5, iclass 18, count 2 2006.260.08:03:21.18#ibcon#read 5, iclass 18, count 2 2006.260.08:03:21.18#ibcon#about to read 6, iclass 18, count 2 2006.260.08:03:21.18#ibcon#read 6, iclass 18, count 2 2006.260.08:03:21.18#ibcon#end of sib2, iclass 18, count 2 2006.260.08:03:21.18#ibcon#*after write, iclass 18, count 2 2006.260.08:03:21.18#ibcon#*before return 0, iclass 18, count 2 2006.260.08:03:21.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:03:21.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:03:21.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.08:03:21.18#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:21.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:03:21.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:03:21.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:03:21.30#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:03:21.30#ibcon#first serial, iclass 18, count 0 2006.260.08:03:21.30#ibcon#enter sib2, iclass 18, count 0 2006.260.08:03:21.30#ibcon#flushed, iclass 18, count 0 2006.260.08:03:21.30#ibcon#about to write, iclass 18, count 0 2006.260.08:03:21.30#ibcon#wrote, iclass 18, count 0 2006.260.08:03:21.30#ibcon#about to read 3, iclass 18, count 0 2006.260.08:03:21.32#ibcon#read 3, iclass 18, count 0 2006.260.08:03:21.32#ibcon#about to read 4, iclass 18, count 0 2006.260.08:03:21.32#ibcon#read 4, iclass 18, count 0 2006.260.08:03:21.32#ibcon#about to read 5, iclass 18, count 0 2006.260.08:03:21.32#ibcon#read 5, iclass 18, count 0 2006.260.08:03:21.32#ibcon#about to read 6, iclass 18, count 0 2006.260.08:03:21.32#ibcon#read 6, iclass 18, count 0 2006.260.08:03:21.32#ibcon#end of sib2, iclass 18, count 0 2006.260.08:03:21.32#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:03:21.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:03:21.32#ibcon#[25=USB\r\n] 2006.260.08:03:21.32#ibcon#*before write, iclass 18, count 0 2006.260.08:03:21.32#ibcon#enter sib2, iclass 18, count 0 2006.260.08:03:21.32#ibcon#flushed, iclass 18, count 0 2006.260.08:03:21.32#ibcon#about to write, iclass 18, count 0 2006.260.08:03:21.32#ibcon#wrote, iclass 18, count 0 2006.260.08:03:21.32#ibcon#about to read 3, iclass 18, count 0 2006.260.08:03:21.35#ibcon#read 3, iclass 18, count 0 2006.260.08:03:21.35#ibcon#about to read 4, iclass 18, count 0 2006.260.08:03:21.35#ibcon#read 4, iclass 18, count 0 2006.260.08:03:21.35#ibcon#about to read 5, iclass 18, count 0 2006.260.08:03:21.35#ibcon#read 5, iclass 18, count 0 2006.260.08:03:21.35#ibcon#about to read 6, iclass 18, count 0 2006.260.08:03:21.35#ibcon#read 6, iclass 18, count 0 2006.260.08:03:21.35#ibcon#end of sib2, iclass 18, count 0 2006.260.08:03:21.35#ibcon#*after write, iclass 18, count 0 2006.260.08:03:21.35#ibcon#*before return 0, iclass 18, count 0 2006.260.08:03:21.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:03:21.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:03:21.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:03:21.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:03:21.35$vc4f8/valo=8,852.99 2006.260.08:03:21.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.08:03:21.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.08:03:21.35#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:21.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:03:21.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:03:21.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:03:21.35#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:03:21.35#ibcon#first serial, iclass 20, count 0 2006.260.08:03:21.35#ibcon#enter sib2, iclass 20, count 0 2006.260.08:03:21.35#ibcon#flushed, iclass 20, count 0 2006.260.08:03:21.35#ibcon#about to write, iclass 20, count 0 2006.260.08:03:21.35#ibcon#wrote, iclass 20, count 0 2006.260.08:03:21.35#ibcon#about to read 3, iclass 20, count 0 2006.260.08:03:21.37#ibcon#read 3, iclass 20, count 0 2006.260.08:03:21.37#ibcon#about to read 4, iclass 20, count 0 2006.260.08:03:21.37#ibcon#read 4, iclass 20, count 0 2006.260.08:03:21.37#ibcon#about to read 5, iclass 20, count 0 2006.260.08:03:21.37#ibcon#read 5, iclass 20, count 0 2006.260.08:03:21.37#ibcon#about to read 6, iclass 20, count 0 2006.260.08:03:21.37#ibcon#read 6, iclass 20, count 0 2006.260.08:03:21.37#ibcon#end of sib2, iclass 20, count 0 2006.260.08:03:21.37#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:03:21.37#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:03:21.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:03:21.37#ibcon#*before write, iclass 20, count 0 2006.260.08:03:21.37#ibcon#enter sib2, iclass 20, count 0 2006.260.08:03:21.37#ibcon#flushed, iclass 20, count 0 2006.260.08:03:21.37#ibcon#about to write, iclass 20, count 0 2006.260.08:03:21.37#ibcon#wrote, iclass 20, count 0 2006.260.08:03:21.37#ibcon#about to read 3, iclass 20, count 0 2006.260.08:03:21.41#ibcon#read 3, iclass 20, count 0 2006.260.08:03:21.41#ibcon#about to read 4, iclass 20, count 0 2006.260.08:03:21.41#ibcon#read 4, iclass 20, count 0 2006.260.08:03:21.41#ibcon#about to read 5, iclass 20, count 0 2006.260.08:03:21.41#ibcon#read 5, iclass 20, count 0 2006.260.08:03:21.41#ibcon#about to read 6, iclass 20, count 0 2006.260.08:03:21.41#ibcon#read 6, iclass 20, count 0 2006.260.08:03:21.41#ibcon#end of sib2, iclass 20, count 0 2006.260.08:03:21.41#ibcon#*after write, iclass 20, count 0 2006.260.08:03:21.41#ibcon#*before return 0, iclass 20, count 0 2006.260.08:03:21.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:03:21.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:03:21.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:03:21.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:03:21.41$vc4f8/va=8,6 2006.260.08:03:21.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.08:03:21.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.08:03:21.41#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:21.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:03:21.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:03:21.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:03:21.47#ibcon#enter wrdev, iclass 22, count 2 2006.260.08:03:21.47#ibcon#first serial, iclass 22, count 2 2006.260.08:03:21.47#ibcon#enter sib2, iclass 22, count 2 2006.260.08:03:21.47#ibcon#flushed, iclass 22, count 2 2006.260.08:03:21.47#ibcon#about to write, iclass 22, count 2 2006.260.08:03:21.47#ibcon#wrote, iclass 22, count 2 2006.260.08:03:21.47#ibcon#about to read 3, iclass 22, count 2 2006.260.08:03:21.49#ibcon#read 3, iclass 22, count 2 2006.260.08:03:21.49#ibcon#about to read 4, iclass 22, count 2 2006.260.08:03:21.49#ibcon#read 4, iclass 22, count 2 2006.260.08:03:21.49#ibcon#about to read 5, iclass 22, count 2 2006.260.08:03:21.49#ibcon#read 5, iclass 22, count 2 2006.260.08:03:21.49#ibcon#about to read 6, iclass 22, count 2 2006.260.08:03:21.49#ibcon#read 6, iclass 22, count 2 2006.260.08:03:21.49#ibcon#end of sib2, iclass 22, count 2 2006.260.08:03:21.49#ibcon#*mode == 0, iclass 22, count 2 2006.260.08:03:21.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.08:03:21.49#ibcon#[25=AT08-06\r\n] 2006.260.08:03:21.49#ibcon#*before write, iclass 22, count 2 2006.260.08:03:21.49#ibcon#enter sib2, iclass 22, count 2 2006.260.08:03:21.49#ibcon#flushed, iclass 22, count 2 2006.260.08:03:21.49#ibcon#about to write, iclass 22, count 2 2006.260.08:03:21.49#ibcon#wrote, iclass 22, count 2 2006.260.08:03:21.49#ibcon#about to read 3, iclass 22, count 2 2006.260.08:03:21.52#ibcon#read 3, iclass 22, count 2 2006.260.08:03:21.52#ibcon#about to read 4, iclass 22, count 2 2006.260.08:03:21.52#ibcon#read 4, iclass 22, count 2 2006.260.08:03:21.52#ibcon#about to read 5, iclass 22, count 2 2006.260.08:03:21.52#ibcon#read 5, iclass 22, count 2 2006.260.08:03:21.52#ibcon#about to read 6, iclass 22, count 2 2006.260.08:03:21.52#ibcon#read 6, iclass 22, count 2 2006.260.08:03:21.52#ibcon#end of sib2, iclass 22, count 2 2006.260.08:03:21.52#ibcon#*after write, iclass 22, count 2 2006.260.08:03:21.52#ibcon#*before return 0, iclass 22, count 2 2006.260.08:03:21.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:03:21.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:03:21.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.08:03:21.52#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:21.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:03:21.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:03:21.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:03:21.64#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:03:21.64#ibcon#first serial, iclass 22, count 0 2006.260.08:03:21.64#ibcon#enter sib2, iclass 22, count 0 2006.260.08:03:21.64#ibcon#flushed, iclass 22, count 0 2006.260.08:03:21.64#ibcon#about to write, iclass 22, count 0 2006.260.08:03:21.64#ibcon#wrote, iclass 22, count 0 2006.260.08:03:21.64#ibcon#about to read 3, iclass 22, count 0 2006.260.08:03:21.66#ibcon#read 3, iclass 22, count 0 2006.260.08:03:21.66#ibcon#about to read 4, iclass 22, count 0 2006.260.08:03:21.66#ibcon#read 4, iclass 22, count 0 2006.260.08:03:21.66#ibcon#about to read 5, iclass 22, count 0 2006.260.08:03:21.66#ibcon#read 5, iclass 22, count 0 2006.260.08:03:21.66#ibcon#about to read 6, iclass 22, count 0 2006.260.08:03:21.66#ibcon#read 6, iclass 22, count 0 2006.260.08:03:21.66#ibcon#end of sib2, iclass 22, count 0 2006.260.08:03:21.66#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:03:21.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:03:21.66#ibcon#[25=USB\r\n] 2006.260.08:03:21.66#ibcon#*before write, iclass 22, count 0 2006.260.08:03:21.66#ibcon#enter sib2, iclass 22, count 0 2006.260.08:03:21.66#ibcon#flushed, iclass 22, count 0 2006.260.08:03:21.66#ibcon#about to write, iclass 22, count 0 2006.260.08:03:21.66#ibcon#wrote, iclass 22, count 0 2006.260.08:03:21.66#ibcon#about to read 3, iclass 22, count 0 2006.260.08:03:21.69#ibcon#read 3, iclass 22, count 0 2006.260.08:03:21.69#ibcon#about to read 4, iclass 22, count 0 2006.260.08:03:21.69#ibcon#read 4, iclass 22, count 0 2006.260.08:03:21.69#ibcon#about to read 5, iclass 22, count 0 2006.260.08:03:21.69#ibcon#read 5, iclass 22, count 0 2006.260.08:03:21.69#ibcon#about to read 6, iclass 22, count 0 2006.260.08:03:21.69#ibcon#read 6, iclass 22, count 0 2006.260.08:03:21.69#ibcon#end of sib2, iclass 22, count 0 2006.260.08:03:21.69#ibcon#*after write, iclass 22, count 0 2006.260.08:03:21.69#ibcon#*before return 0, iclass 22, count 0 2006.260.08:03:21.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:03:21.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:03:21.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:03:21.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:03:21.69$vc4f8/vblo=1,632.99 2006.260.08:03:21.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.08:03:21.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.08:03:21.69#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:21.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:03:21.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:03:21.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:03:21.69#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:03:21.69#ibcon#first serial, iclass 24, count 0 2006.260.08:03:21.69#ibcon#enter sib2, iclass 24, count 0 2006.260.08:03:21.69#ibcon#flushed, iclass 24, count 0 2006.260.08:03:21.69#ibcon#about to write, iclass 24, count 0 2006.260.08:03:21.69#ibcon#wrote, iclass 24, count 0 2006.260.08:03:21.69#ibcon#about to read 3, iclass 24, count 0 2006.260.08:03:21.71#ibcon#read 3, iclass 24, count 0 2006.260.08:03:21.71#ibcon#about to read 4, iclass 24, count 0 2006.260.08:03:21.71#ibcon#read 4, iclass 24, count 0 2006.260.08:03:21.71#ibcon#about to read 5, iclass 24, count 0 2006.260.08:03:21.71#ibcon#read 5, iclass 24, count 0 2006.260.08:03:21.71#ibcon#about to read 6, iclass 24, count 0 2006.260.08:03:21.71#ibcon#read 6, iclass 24, count 0 2006.260.08:03:21.71#ibcon#end of sib2, iclass 24, count 0 2006.260.08:03:21.71#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:03:21.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:03:21.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:03:21.71#ibcon#*before write, iclass 24, count 0 2006.260.08:03:21.71#ibcon#enter sib2, iclass 24, count 0 2006.260.08:03:21.71#ibcon#flushed, iclass 24, count 0 2006.260.08:03:21.71#ibcon#about to write, iclass 24, count 0 2006.260.08:03:21.71#ibcon#wrote, iclass 24, count 0 2006.260.08:03:21.71#ibcon#about to read 3, iclass 24, count 0 2006.260.08:03:21.75#ibcon#read 3, iclass 24, count 0 2006.260.08:03:21.75#ibcon#about to read 4, iclass 24, count 0 2006.260.08:03:21.75#ibcon#read 4, iclass 24, count 0 2006.260.08:03:21.75#ibcon#about to read 5, iclass 24, count 0 2006.260.08:03:21.75#ibcon#read 5, iclass 24, count 0 2006.260.08:03:21.75#ibcon#about to read 6, iclass 24, count 0 2006.260.08:03:21.75#ibcon#read 6, iclass 24, count 0 2006.260.08:03:21.75#ibcon#end of sib2, iclass 24, count 0 2006.260.08:03:21.75#ibcon#*after write, iclass 24, count 0 2006.260.08:03:21.75#ibcon#*before return 0, iclass 24, count 0 2006.260.08:03:21.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:03:21.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:03:21.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:03:21.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:03:21.75$vc4f8/vb=1,4 2006.260.08:03:21.75#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.08:03:21.75#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.08:03:21.75#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:21.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:03:21.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:03:21.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:03:21.75#ibcon#enter wrdev, iclass 26, count 2 2006.260.08:03:21.75#ibcon#first serial, iclass 26, count 2 2006.260.08:03:21.75#ibcon#enter sib2, iclass 26, count 2 2006.260.08:03:21.75#ibcon#flushed, iclass 26, count 2 2006.260.08:03:21.75#ibcon#about to write, iclass 26, count 2 2006.260.08:03:21.75#ibcon#wrote, iclass 26, count 2 2006.260.08:03:21.75#ibcon#about to read 3, iclass 26, count 2 2006.260.08:03:21.77#ibcon#read 3, iclass 26, count 2 2006.260.08:03:21.77#ibcon#about to read 4, iclass 26, count 2 2006.260.08:03:21.77#ibcon#read 4, iclass 26, count 2 2006.260.08:03:21.77#ibcon#about to read 5, iclass 26, count 2 2006.260.08:03:21.77#ibcon#read 5, iclass 26, count 2 2006.260.08:03:21.77#ibcon#about to read 6, iclass 26, count 2 2006.260.08:03:21.77#ibcon#read 6, iclass 26, count 2 2006.260.08:03:21.77#ibcon#end of sib2, iclass 26, count 2 2006.260.08:03:21.77#ibcon#*mode == 0, iclass 26, count 2 2006.260.08:03:21.77#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.08:03:21.77#ibcon#[27=AT01-04\r\n] 2006.260.08:03:21.77#ibcon#*before write, iclass 26, count 2 2006.260.08:03:21.77#ibcon#enter sib2, iclass 26, count 2 2006.260.08:03:21.77#ibcon#flushed, iclass 26, count 2 2006.260.08:03:21.77#ibcon#about to write, iclass 26, count 2 2006.260.08:03:21.77#ibcon#wrote, iclass 26, count 2 2006.260.08:03:21.77#ibcon#about to read 3, iclass 26, count 2 2006.260.08:03:21.80#ibcon#read 3, iclass 26, count 2 2006.260.08:03:21.80#ibcon#about to read 4, iclass 26, count 2 2006.260.08:03:21.80#ibcon#read 4, iclass 26, count 2 2006.260.08:03:21.80#ibcon#about to read 5, iclass 26, count 2 2006.260.08:03:21.80#ibcon#read 5, iclass 26, count 2 2006.260.08:03:21.80#ibcon#about to read 6, iclass 26, count 2 2006.260.08:03:21.80#ibcon#read 6, iclass 26, count 2 2006.260.08:03:21.80#ibcon#end of sib2, iclass 26, count 2 2006.260.08:03:21.80#ibcon#*after write, iclass 26, count 2 2006.260.08:03:21.80#ibcon#*before return 0, iclass 26, count 2 2006.260.08:03:21.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:03:21.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:03:21.80#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.08:03:21.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:21.80#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:03:21.92#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:03:21.92#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:03:21.92#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:03:21.92#ibcon#first serial, iclass 26, count 0 2006.260.08:03:21.92#ibcon#enter sib2, iclass 26, count 0 2006.260.08:03:21.92#ibcon#flushed, iclass 26, count 0 2006.260.08:03:21.92#ibcon#about to write, iclass 26, count 0 2006.260.08:03:21.92#ibcon#wrote, iclass 26, count 0 2006.260.08:03:21.92#ibcon#about to read 3, iclass 26, count 0 2006.260.08:03:21.94#ibcon#read 3, iclass 26, count 0 2006.260.08:03:21.94#ibcon#about to read 4, iclass 26, count 0 2006.260.08:03:21.94#ibcon#read 4, iclass 26, count 0 2006.260.08:03:21.94#ibcon#about to read 5, iclass 26, count 0 2006.260.08:03:21.94#ibcon#read 5, iclass 26, count 0 2006.260.08:03:21.94#ibcon#about to read 6, iclass 26, count 0 2006.260.08:03:21.94#ibcon#read 6, iclass 26, count 0 2006.260.08:03:21.94#ibcon#end of sib2, iclass 26, count 0 2006.260.08:03:21.94#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:03:21.94#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:03:21.94#ibcon#[27=USB\r\n] 2006.260.08:03:21.94#ibcon#*before write, iclass 26, count 0 2006.260.08:03:21.94#ibcon#enter sib2, iclass 26, count 0 2006.260.08:03:21.94#ibcon#flushed, iclass 26, count 0 2006.260.08:03:21.94#ibcon#about to write, iclass 26, count 0 2006.260.08:03:21.94#ibcon#wrote, iclass 26, count 0 2006.260.08:03:21.94#ibcon#about to read 3, iclass 26, count 0 2006.260.08:03:21.97#ibcon#read 3, iclass 26, count 0 2006.260.08:03:21.97#ibcon#about to read 4, iclass 26, count 0 2006.260.08:03:21.97#ibcon#read 4, iclass 26, count 0 2006.260.08:03:21.97#ibcon#about to read 5, iclass 26, count 0 2006.260.08:03:21.97#ibcon#read 5, iclass 26, count 0 2006.260.08:03:21.97#ibcon#about to read 6, iclass 26, count 0 2006.260.08:03:21.97#ibcon#read 6, iclass 26, count 0 2006.260.08:03:21.97#ibcon#end of sib2, iclass 26, count 0 2006.260.08:03:21.97#ibcon#*after write, iclass 26, count 0 2006.260.08:03:21.97#ibcon#*before return 0, iclass 26, count 0 2006.260.08:03:21.97#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:03:21.97#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:03:21.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:03:21.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:03:21.97$vc4f8/vblo=2,640.99 2006.260.08:03:21.97#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:03:21.97#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:03:21.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:21.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:21.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:21.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:21.97#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:03:21.97#ibcon#first serial, iclass 28, count 0 2006.260.08:03:21.97#ibcon#enter sib2, iclass 28, count 0 2006.260.08:03:21.97#ibcon#flushed, iclass 28, count 0 2006.260.08:03:21.97#ibcon#about to write, iclass 28, count 0 2006.260.08:03:21.97#ibcon#wrote, iclass 28, count 0 2006.260.08:03:21.97#ibcon#about to read 3, iclass 28, count 0 2006.260.08:03:21.99#ibcon#read 3, iclass 28, count 0 2006.260.08:03:21.99#ibcon#about to read 4, iclass 28, count 0 2006.260.08:03:21.99#ibcon#read 4, iclass 28, count 0 2006.260.08:03:21.99#ibcon#about to read 5, iclass 28, count 0 2006.260.08:03:21.99#ibcon#read 5, iclass 28, count 0 2006.260.08:03:21.99#ibcon#about to read 6, iclass 28, count 0 2006.260.08:03:21.99#ibcon#read 6, iclass 28, count 0 2006.260.08:03:21.99#ibcon#end of sib2, iclass 28, count 0 2006.260.08:03:21.99#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:03:21.99#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:03:21.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:03:21.99#ibcon#*before write, iclass 28, count 0 2006.260.08:03:21.99#ibcon#enter sib2, iclass 28, count 0 2006.260.08:03:21.99#ibcon#flushed, iclass 28, count 0 2006.260.08:03:21.99#ibcon#about to write, iclass 28, count 0 2006.260.08:03:21.99#ibcon#wrote, iclass 28, count 0 2006.260.08:03:21.99#ibcon#about to read 3, iclass 28, count 0 2006.260.08:03:22.03#ibcon#read 3, iclass 28, count 0 2006.260.08:03:22.03#ibcon#about to read 4, iclass 28, count 0 2006.260.08:03:22.03#ibcon#read 4, iclass 28, count 0 2006.260.08:03:22.03#ibcon#about to read 5, iclass 28, count 0 2006.260.08:03:22.03#ibcon#read 5, iclass 28, count 0 2006.260.08:03:22.03#ibcon#about to read 6, iclass 28, count 0 2006.260.08:03:22.03#ibcon#read 6, iclass 28, count 0 2006.260.08:03:22.03#ibcon#end of sib2, iclass 28, count 0 2006.260.08:03:22.03#ibcon#*after write, iclass 28, count 0 2006.260.08:03:22.03#ibcon#*before return 0, iclass 28, count 0 2006.260.08:03:22.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:22.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:03:22.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:03:22.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:03:22.03$vc4f8/vb=2,5 2006.260.08:03:22.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:03:22.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:03:22.03#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:22.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:22.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:22.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:22.09#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:03:22.09#ibcon#first serial, iclass 30, count 2 2006.260.08:03:22.09#ibcon#enter sib2, iclass 30, count 2 2006.260.08:03:22.09#ibcon#flushed, iclass 30, count 2 2006.260.08:03:22.09#ibcon#about to write, iclass 30, count 2 2006.260.08:03:22.09#ibcon#wrote, iclass 30, count 2 2006.260.08:03:22.09#ibcon#about to read 3, iclass 30, count 2 2006.260.08:03:22.11#ibcon#read 3, iclass 30, count 2 2006.260.08:03:22.11#ibcon#about to read 4, iclass 30, count 2 2006.260.08:03:22.11#ibcon#read 4, iclass 30, count 2 2006.260.08:03:22.11#ibcon#about to read 5, iclass 30, count 2 2006.260.08:03:22.11#ibcon#read 5, iclass 30, count 2 2006.260.08:03:22.11#ibcon#about to read 6, iclass 30, count 2 2006.260.08:03:22.11#ibcon#read 6, iclass 30, count 2 2006.260.08:03:22.11#ibcon#end of sib2, iclass 30, count 2 2006.260.08:03:22.11#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:03:22.11#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:03:22.11#ibcon#[27=AT02-05\r\n] 2006.260.08:03:22.11#ibcon#*before write, iclass 30, count 2 2006.260.08:03:22.11#ibcon#enter sib2, iclass 30, count 2 2006.260.08:03:22.11#ibcon#flushed, iclass 30, count 2 2006.260.08:03:22.11#ibcon#about to write, iclass 30, count 2 2006.260.08:03:22.11#ibcon#wrote, iclass 30, count 2 2006.260.08:03:22.11#ibcon#about to read 3, iclass 30, count 2 2006.260.08:03:22.14#ibcon#read 3, iclass 30, count 2 2006.260.08:03:22.14#ibcon#about to read 4, iclass 30, count 2 2006.260.08:03:22.14#ibcon#read 4, iclass 30, count 2 2006.260.08:03:22.14#ibcon#about to read 5, iclass 30, count 2 2006.260.08:03:22.14#ibcon#read 5, iclass 30, count 2 2006.260.08:03:22.14#ibcon#about to read 6, iclass 30, count 2 2006.260.08:03:22.14#ibcon#read 6, iclass 30, count 2 2006.260.08:03:22.14#ibcon#end of sib2, iclass 30, count 2 2006.260.08:03:22.14#ibcon#*after write, iclass 30, count 2 2006.260.08:03:22.14#ibcon#*before return 0, iclass 30, count 2 2006.260.08:03:22.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:22.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:03:22.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:03:22.14#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:22.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:22.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:22.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:22.26#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:03:22.26#ibcon#first serial, iclass 30, count 0 2006.260.08:03:22.26#ibcon#enter sib2, iclass 30, count 0 2006.260.08:03:22.26#ibcon#flushed, iclass 30, count 0 2006.260.08:03:22.26#ibcon#about to write, iclass 30, count 0 2006.260.08:03:22.26#ibcon#wrote, iclass 30, count 0 2006.260.08:03:22.26#ibcon#about to read 3, iclass 30, count 0 2006.260.08:03:22.28#ibcon#read 3, iclass 30, count 0 2006.260.08:03:22.28#ibcon#about to read 4, iclass 30, count 0 2006.260.08:03:22.28#ibcon#read 4, iclass 30, count 0 2006.260.08:03:22.28#ibcon#about to read 5, iclass 30, count 0 2006.260.08:03:22.28#ibcon#read 5, iclass 30, count 0 2006.260.08:03:22.28#ibcon#about to read 6, iclass 30, count 0 2006.260.08:03:22.28#ibcon#read 6, iclass 30, count 0 2006.260.08:03:22.28#ibcon#end of sib2, iclass 30, count 0 2006.260.08:03:22.28#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:03:22.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:03:22.28#ibcon#[27=USB\r\n] 2006.260.08:03:22.28#ibcon#*before write, iclass 30, count 0 2006.260.08:03:22.28#ibcon#enter sib2, iclass 30, count 0 2006.260.08:03:22.28#ibcon#flushed, iclass 30, count 0 2006.260.08:03:22.28#ibcon#about to write, iclass 30, count 0 2006.260.08:03:22.28#ibcon#wrote, iclass 30, count 0 2006.260.08:03:22.28#ibcon#about to read 3, iclass 30, count 0 2006.260.08:03:22.31#ibcon#read 3, iclass 30, count 0 2006.260.08:03:22.31#ibcon#about to read 4, iclass 30, count 0 2006.260.08:03:22.31#ibcon#read 4, iclass 30, count 0 2006.260.08:03:22.31#ibcon#about to read 5, iclass 30, count 0 2006.260.08:03:22.31#ibcon#read 5, iclass 30, count 0 2006.260.08:03:22.31#ibcon#about to read 6, iclass 30, count 0 2006.260.08:03:22.31#ibcon#read 6, iclass 30, count 0 2006.260.08:03:22.31#ibcon#end of sib2, iclass 30, count 0 2006.260.08:03:22.31#ibcon#*after write, iclass 30, count 0 2006.260.08:03:22.31#ibcon#*before return 0, iclass 30, count 0 2006.260.08:03:22.31#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:22.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:03:22.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:03:22.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:03:22.31$vc4f8/vblo=3,656.99 2006.260.08:03:22.31#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:03:22.31#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:03:22.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:22.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:22.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:22.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:22.31#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:03:22.31#ibcon#first serial, iclass 32, count 0 2006.260.08:03:22.31#ibcon#enter sib2, iclass 32, count 0 2006.260.08:03:22.31#ibcon#flushed, iclass 32, count 0 2006.260.08:03:22.31#ibcon#about to write, iclass 32, count 0 2006.260.08:03:22.31#ibcon#wrote, iclass 32, count 0 2006.260.08:03:22.31#ibcon#about to read 3, iclass 32, count 0 2006.260.08:03:22.33#ibcon#read 3, iclass 32, count 0 2006.260.08:03:22.33#ibcon#about to read 4, iclass 32, count 0 2006.260.08:03:22.33#ibcon#read 4, iclass 32, count 0 2006.260.08:03:22.33#ibcon#about to read 5, iclass 32, count 0 2006.260.08:03:22.33#ibcon#read 5, iclass 32, count 0 2006.260.08:03:22.33#ibcon#about to read 6, iclass 32, count 0 2006.260.08:03:22.33#ibcon#read 6, iclass 32, count 0 2006.260.08:03:22.33#ibcon#end of sib2, iclass 32, count 0 2006.260.08:03:22.33#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:03:22.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:03:22.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:03:22.33#ibcon#*before write, iclass 32, count 0 2006.260.08:03:22.33#ibcon#enter sib2, iclass 32, count 0 2006.260.08:03:22.33#ibcon#flushed, iclass 32, count 0 2006.260.08:03:22.33#ibcon#about to write, iclass 32, count 0 2006.260.08:03:22.33#ibcon#wrote, iclass 32, count 0 2006.260.08:03:22.33#ibcon#about to read 3, iclass 32, count 0 2006.260.08:03:22.37#ibcon#read 3, iclass 32, count 0 2006.260.08:03:22.37#ibcon#about to read 4, iclass 32, count 0 2006.260.08:03:22.37#ibcon#read 4, iclass 32, count 0 2006.260.08:03:22.37#ibcon#about to read 5, iclass 32, count 0 2006.260.08:03:22.37#ibcon#read 5, iclass 32, count 0 2006.260.08:03:22.37#ibcon#about to read 6, iclass 32, count 0 2006.260.08:03:22.37#ibcon#read 6, iclass 32, count 0 2006.260.08:03:22.37#ibcon#end of sib2, iclass 32, count 0 2006.260.08:03:22.37#ibcon#*after write, iclass 32, count 0 2006.260.08:03:22.37#ibcon#*before return 0, iclass 32, count 0 2006.260.08:03:22.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:22.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:03:22.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:03:22.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:03:22.37$vc4f8/vb=3,4 2006.260.08:03:22.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.08:03:22.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.08:03:22.37#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:22.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:22.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:22.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:22.43#ibcon#enter wrdev, iclass 34, count 2 2006.260.08:03:22.43#ibcon#first serial, iclass 34, count 2 2006.260.08:03:22.43#ibcon#enter sib2, iclass 34, count 2 2006.260.08:03:22.43#ibcon#flushed, iclass 34, count 2 2006.260.08:03:22.43#ibcon#about to write, iclass 34, count 2 2006.260.08:03:22.43#ibcon#wrote, iclass 34, count 2 2006.260.08:03:22.43#ibcon#about to read 3, iclass 34, count 2 2006.260.08:03:22.45#ibcon#read 3, iclass 34, count 2 2006.260.08:03:22.45#ibcon#about to read 4, iclass 34, count 2 2006.260.08:03:22.45#ibcon#read 4, iclass 34, count 2 2006.260.08:03:22.45#ibcon#about to read 5, iclass 34, count 2 2006.260.08:03:22.45#ibcon#read 5, iclass 34, count 2 2006.260.08:03:22.45#ibcon#about to read 6, iclass 34, count 2 2006.260.08:03:22.45#ibcon#read 6, iclass 34, count 2 2006.260.08:03:22.45#ibcon#end of sib2, iclass 34, count 2 2006.260.08:03:22.45#ibcon#*mode == 0, iclass 34, count 2 2006.260.08:03:22.45#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.08:03:22.45#ibcon#[27=AT03-04\r\n] 2006.260.08:03:22.45#ibcon#*before write, iclass 34, count 2 2006.260.08:03:22.45#ibcon#enter sib2, iclass 34, count 2 2006.260.08:03:22.45#ibcon#flushed, iclass 34, count 2 2006.260.08:03:22.45#ibcon#about to write, iclass 34, count 2 2006.260.08:03:22.45#ibcon#wrote, iclass 34, count 2 2006.260.08:03:22.45#ibcon#about to read 3, iclass 34, count 2 2006.260.08:03:22.48#ibcon#read 3, iclass 34, count 2 2006.260.08:03:22.48#ibcon#about to read 4, iclass 34, count 2 2006.260.08:03:22.48#ibcon#read 4, iclass 34, count 2 2006.260.08:03:22.48#ibcon#about to read 5, iclass 34, count 2 2006.260.08:03:22.48#ibcon#read 5, iclass 34, count 2 2006.260.08:03:22.48#ibcon#about to read 6, iclass 34, count 2 2006.260.08:03:22.48#ibcon#read 6, iclass 34, count 2 2006.260.08:03:22.48#ibcon#end of sib2, iclass 34, count 2 2006.260.08:03:22.48#ibcon#*after write, iclass 34, count 2 2006.260.08:03:22.48#ibcon#*before return 0, iclass 34, count 2 2006.260.08:03:22.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:22.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:03:22.48#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.08:03:22.48#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:22.48#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:22.60#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:22.60#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:22.60#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:03:22.60#ibcon#first serial, iclass 34, count 0 2006.260.08:03:22.60#ibcon#enter sib2, iclass 34, count 0 2006.260.08:03:22.60#ibcon#flushed, iclass 34, count 0 2006.260.08:03:22.60#ibcon#about to write, iclass 34, count 0 2006.260.08:03:22.60#ibcon#wrote, iclass 34, count 0 2006.260.08:03:22.60#ibcon#about to read 3, iclass 34, count 0 2006.260.08:03:22.62#ibcon#read 3, iclass 34, count 0 2006.260.08:03:22.62#ibcon#about to read 4, iclass 34, count 0 2006.260.08:03:22.62#ibcon#read 4, iclass 34, count 0 2006.260.08:03:22.62#ibcon#about to read 5, iclass 34, count 0 2006.260.08:03:22.62#ibcon#read 5, iclass 34, count 0 2006.260.08:03:22.62#ibcon#about to read 6, iclass 34, count 0 2006.260.08:03:22.62#ibcon#read 6, iclass 34, count 0 2006.260.08:03:22.62#ibcon#end of sib2, iclass 34, count 0 2006.260.08:03:22.62#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:03:22.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:03:22.62#ibcon#[27=USB\r\n] 2006.260.08:03:22.62#ibcon#*before write, iclass 34, count 0 2006.260.08:03:22.62#ibcon#enter sib2, iclass 34, count 0 2006.260.08:03:22.62#ibcon#flushed, iclass 34, count 0 2006.260.08:03:22.62#ibcon#about to write, iclass 34, count 0 2006.260.08:03:22.62#ibcon#wrote, iclass 34, count 0 2006.260.08:03:22.62#ibcon#about to read 3, iclass 34, count 0 2006.260.08:03:22.65#ibcon#read 3, iclass 34, count 0 2006.260.08:03:22.65#ibcon#about to read 4, iclass 34, count 0 2006.260.08:03:22.65#ibcon#read 4, iclass 34, count 0 2006.260.08:03:22.65#ibcon#about to read 5, iclass 34, count 0 2006.260.08:03:22.65#ibcon#read 5, iclass 34, count 0 2006.260.08:03:22.65#ibcon#about to read 6, iclass 34, count 0 2006.260.08:03:22.65#ibcon#read 6, iclass 34, count 0 2006.260.08:03:22.65#ibcon#end of sib2, iclass 34, count 0 2006.260.08:03:22.65#ibcon#*after write, iclass 34, count 0 2006.260.08:03:22.65#ibcon#*before return 0, iclass 34, count 0 2006.260.08:03:22.65#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:22.65#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:03:22.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:03:22.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:03:22.65$vc4f8/vblo=4,712.99 2006.260.08:03:22.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:03:22.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:03:22.65#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:22.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:22.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:22.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:22.65#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:03:22.65#ibcon#first serial, iclass 36, count 0 2006.260.08:03:22.65#ibcon#enter sib2, iclass 36, count 0 2006.260.08:03:22.65#ibcon#flushed, iclass 36, count 0 2006.260.08:03:22.65#ibcon#about to write, iclass 36, count 0 2006.260.08:03:22.65#ibcon#wrote, iclass 36, count 0 2006.260.08:03:22.65#ibcon#about to read 3, iclass 36, count 0 2006.260.08:03:22.67#ibcon#read 3, iclass 36, count 0 2006.260.08:03:22.67#ibcon#about to read 4, iclass 36, count 0 2006.260.08:03:22.67#ibcon#read 4, iclass 36, count 0 2006.260.08:03:22.67#ibcon#about to read 5, iclass 36, count 0 2006.260.08:03:22.67#ibcon#read 5, iclass 36, count 0 2006.260.08:03:22.67#ibcon#about to read 6, iclass 36, count 0 2006.260.08:03:22.67#ibcon#read 6, iclass 36, count 0 2006.260.08:03:22.67#ibcon#end of sib2, iclass 36, count 0 2006.260.08:03:22.67#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:03:22.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:03:22.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:03:22.67#ibcon#*before write, iclass 36, count 0 2006.260.08:03:22.67#ibcon#enter sib2, iclass 36, count 0 2006.260.08:03:22.67#ibcon#flushed, iclass 36, count 0 2006.260.08:03:22.67#ibcon#about to write, iclass 36, count 0 2006.260.08:03:22.67#ibcon#wrote, iclass 36, count 0 2006.260.08:03:22.67#ibcon#about to read 3, iclass 36, count 0 2006.260.08:03:22.71#ibcon#read 3, iclass 36, count 0 2006.260.08:03:22.71#ibcon#about to read 4, iclass 36, count 0 2006.260.08:03:22.71#ibcon#read 4, iclass 36, count 0 2006.260.08:03:22.71#ibcon#about to read 5, iclass 36, count 0 2006.260.08:03:22.71#ibcon#read 5, iclass 36, count 0 2006.260.08:03:22.71#ibcon#about to read 6, iclass 36, count 0 2006.260.08:03:22.71#ibcon#read 6, iclass 36, count 0 2006.260.08:03:22.71#ibcon#end of sib2, iclass 36, count 0 2006.260.08:03:22.71#ibcon#*after write, iclass 36, count 0 2006.260.08:03:22.71#ibcon#*before return 0, iclass 36, count 0 2006.260.08:03:22.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:22.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:03:22.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:03:22.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:03:22.71$vc4f8/vb=4,5 2006.260.08:03:22.71#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.08:03:22.71#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.08:03:22.71#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:22.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:22.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:22.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:22.77#ibcon#enter wrdev, iclass 38, count 2 2006.260.08:03:22.77#ibcon#first serial, iclass 38, count 2 2006.260.08:03:22.77#ibcon#enter sib2, iclass 38, count 2 2006.260.08:03:22.77#ibcon#flushed, iclass 38, count 2 2006.260.08:03:22.77#ibcon#about to write, iclass 38, count 2 2006.260.08:03:22.77#ibcon#wrote, iclass 38, count 2 2006.260.08:03:22.77#ibcon#about to read 3, iclass 38, count 2 2006.260.08:03:22.79#ibcon#read 3, iclass 38, count 2 2006.260.08:03:22.79#ibcon#about to read 4, iclass 38, count 2 2006.260.08:03:22.79#ibcon#read 4, iclass 38, count 2 2006.260.08:03:22.79#ibcon#about to read 5, iclass 38, count 2 2006.260.08:03:22.79#ibcon#read 5, iclass 38, count 2 2006.260.08:03:22.79#ibcon#about to read 6, iclass 38, count 2 2006.260.08:03:22.79#ibcon#read 6, iclass 38, count 2 2006.260.08:03:22.79#ibcon#end of sib2, iclass 38, count 2 2006.260.08:03:22.79#ibcon#*mode == 0, iclass 38, count 2 2006.260.08:03:22.79#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.08:03:22.79#ibcon#[27=AT04-05\r\n] 2006.260.08:03:22.79#ibcon#*before write, iclass 38, count 2 2006.260.08:03:22.79#ibcon#enter sib2, iclass 38, count 2 2006.260.08:03:22.79#ibcon#flushed, iclass 38, count 2 2006.260.08:03:22.79#ibcon#about to write, iclass 38, count 2 2006.260.08:03:22.79#ibcon#wrote, iclass 38, count 2 2006.260.08:03:22.79#ibcon#about to read 3, iclass 38, count 2 2006.260.08:03:22.82#ibcon#read 3, iclass 38, count 2 2006.260.08:03:22.82#ibcon#about to read 4, iclass 38, count 2 2006.260.08:03:22.82#ibcon#read 4, iclass 38, count 2 2006.260.08:03:22.82#ibcon#about to read 5, iclass 38, count 2 2006.260.08:03:22.82#ibcon#read 5, iclass 38, count 2 2006.260.08:03:22.82#ibcon#about to read 6, iclass 38, count 2 2006.260.08:03:22.82#ibcon#read 6, iclass 38, count 2 2006.260.08:03:22.82#ibcon#end of sib2, iclass 38, count 2 2006.260.08:03:22.82#ibcon#*after write, iclass 38, count 2 2006.260.08:03:22.82#ibcon#*before return 0, iclass 38, count 2 2006.260.08:03:22.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:22.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:03:22.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.08:03:22.82#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:22.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:22.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:22.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:22.94#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:03:22.94#ibcon#first serial, iclass 38, count 0 2006.260.08:03:22.94#ibcon#enter sib2, iclass 38, count 0 2006.260.08:03:22.94#ibcon#flushed, iclass 38, count 0 2006.260.08:03:22.94#ibcon#about to write, iclass 38, count 0 2006.260.08:03:22.94#ibcon#wrote, iclass 38, count 0 2006.260.08:03:22.94#ibcon#about to read 3, iclass 38, count 0 2006.260.08:03:22.96#ibcon#read 3, iclass 38, count 0 2006.260.08:03:22.96#ibcon#about to read 4, iclass 38, count 0 2006.260.08:03:22.96#ibcon#read 4, iclass 38, count 0 2006.260.08:03:22.96#ibcon#about to read 5, iclass 38, count 0 2006.260.08:03:22.96#ibcon#read 5, iclass 38, count 0 2006.260.08:03:22.96#ibcon#about to read 6, iclass 38, count 0 2006.260.08:03:22.96#ibcon#read 6, iclass 38, count 0 2006.260.08:03:22.96#ibcon#end of sib2, iclass 38, count 0 2006.260.08:03:22.96#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:03:22.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:03:22.96#ibcon#[27=USB\r\n] 2006.260.08:03:22.96#ibcon#*before write, iclass 38, count 0 2006.260.08:03:22.96#ibcon#enter sib2, iclass 38, count 0 2006.260.08:03:22.96#ibcon#flushed, iclass 38, count 0 2006.260.08:03:22.96#ibcon#about to write, iclass 38, count 0 2006.260.08:03:22.96#ibcon#wrote, iclass 38, count 0 2006.260.08:03:22.96#ibcon#about to read 3, iclass 38, count 0 2006.260.08:03:22.99#ibcon#read 3, iclass 38, count 0 2006.260.08:03:22.99#ibcon#about to read 4, iclass 38, count 0 2006.260.08:03:22.99#ibcon#read 4, iclass 38, count 0 2006.260.08:03:22.99#ibcon#about to read 5, iclass 38, count 0 2006.260.08:03:22.99#ibcon#read 5, iclass 38, count 0 2006.260.08:03:22.99#ibcon#about to read 6, iclass 38, count 0 2006.260.08:03:22.99#ibcon#read 6, iclass 38, count 0 2006.260.08:03:22.99#ibcon#end of sib2, iclass 38, count 0 2006.260.08:03:22.99#ibcon#*after write, iclass 38, count 0 2006.260.08:03:22.99#ibcon#*before return 0, iclass 38, count 0 2006.260.08:03:22.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:22.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:03:22.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:03:22.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:03:22.99$vc4f8/vblo=5,744.99 2006.260.08:03:22.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.08:03:22.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.08:03:22.99#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:22.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:22.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:22.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:22.99#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:03:22.99#ibcon#first serial, iclass 40, count 0 2006.260.08:03:22.99#ibcon#enter sib2, iclass 40, count 0 2006.260.08:03:22.99#ibcon#flushed, iclass 40, count 0 2006.260.08:03:22.99#ibcon#about to write, iclass 40, count 0 2006.260.08:03:22.99#ibcon#wrote, iclass 40, count 0 2006.260.08:03:22.99#ibcon#about to read 3, iclass 40, count 0 2006.260.08:03:23.01#ibcon#read 3, iclass 40, count 0 2006.260.08:03:23.01#ibcon#about to read 4, iclass 40, count 0 2006.260.08:03:23.01#ibcon#read 4, iclass 40, count 0 2006.260.08:03:23.01#ibcon#about to read 5, iclass 40, count 0 2006.260.08:03:23.01#ibcon#read 5, iclass 40, count 0 2006.260.08:03:23.01#ibcon#about to read 6, iclass 40, count 0 2006.260.08:03:23.01#ibcon#read 6, iclass 40, count 0 2006.260.08:03:23.01#ibcon#end of sib2, iclass 40, count 0 2006.260.08:03:23.01#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:03:23.01#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:03:23.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:03:23.01#ibcon#*before write, iclass 40, count 0 2006.260.08:03:23.01#ibcon#enter sib2, iclass 40, count 0 2006.260.08:03:23.01#ibcon#flushed, iclass 40, count 0 2006.260.08:03:23.01#ibcon#about to write, iclass 40, count 0 2006.260.08:03:23.01#ibcon#wrote, iclass 40, count 0 2006.260.08:03:23.01#ibcon#about to read 3, iclass 40, count 0 2006.260.08:03:23.05#ibcon#read 3, iclass 40, count 0 2006.260.08:03:23.05#ibcon#about to read 4, iclass 40, count 0 2006.260.08:03:23.05#ibcon#read 4, iclass 40, count 0 2006.260.08:03:23.05#ibcon#about to read 5, iclass 40, count 0 2006.260.08:03:23.05#ibcon#read 5, iclass 40, count 0 2006.260.08:03:23.05#ibcon#about to read 6, iclass 40, count 0 2006.260.08:03:23.05#ibcon#read 6, iclass 40, count 0 2006.260.08:03:23.05#ibcon#end of sib2, iclass 40, count 0 2006.260.08:03:23.05#ibcon#*after write, iclass 40, count 0 2006.260.08:03:23.05#ibcon#*before return 0, iclass 40, count 0 2006.260.08:03:23.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:23.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:03:23.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:03:23.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:03:23.05$vc4f8/vb=5,4 2006.260.08:03:23.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.08:03:23.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.08:03:23.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:23.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:23.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:23.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:23.11#ibcon#enter wrdev, iclass 4, count 2 2006.260.08:03:23.11#ibcon#first serial, iclass 4, count 2 2006.260.08:03:23.11#ibcon#enter sib2, iclass 4, count 2 2006.260.08:03:23.11#ibcon#flushed, iclass 4, count 2 2006.260.08:03:23.11#ibcon#about to write, iclass 4, count 2 2006.260.08:03:23.11#ibcon#wrote, iclass 4, count 2 2006.260.08:03:23.11#ibcon#about to read 3, iclass 4, count 2 2006.260.08:03:23.13#ibcon#read 3, iclass 4, count 2 2006.260.08:03:23.13#ibcon#about to read 4, iclass 4, count 2 2006.260.08:03:23.13#ibcon#read 4, iclass 4, count 2 2006.260.08:03:23.13#ibcon#about to read 5, iclass 4, count 2 2006.260.08:03:23.13#ibcon#read 5, iclass 4, count 2 2006.260.08:03:23.13#ibcon#about to read 6, iclass 4, count 2 2006.260.08:03:23.13#ibcon#read 6, iclass 4, count 2 2006.260.08:03:23.13#ibcon#end of sib2, iclass 4, count 2 2006.260.08:03:23.13#ibcon#*mode == 0, iclass 4, count 2 2006.260.08:03:23.13#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.08:03:23.13#ibcon#[27=AT05-04\r\n] 2006.260.08:03:23.13#ibcon#*before write, iclass 4, count 2 2006.260.08:03:23.13#ibcon#enter sib2, iclass 4, count 2 2006.260.08:03:23.13#ibcon#flushed, iclass 4, count 2 2006.260.08:03:23.13#ibcon#about to write, iclass 4, count 2 2006.260.08:03:23.13#ibcon#wrote, iclass 4, count 2 2006.260.08:03:23.13#ibcon#about to read 3, iclass 4, count 2 2006.260.08:03:23.16#ibcon#read 3, iclass 4, count 2 2006.260.08:03:23.16#ibcon#about to read 4, iclass 4, count 2 2006.260.08:03:23.16#ibcon#read 4, iclass 4, count 2 2006.260.08:03:23.16#ibcon#about to read 5, iclass 4, count 2 2006.260.08:03:23.16#ibcon#read 5, iclass 4, count 2 2006.260.08:03:23.16#ibcon#about to read 6, iclass 4, count 2 2006.260.08:03:23.16#ibcon#read 6, iclass 4, count 2 2006.260.08:03:23.16#ibcon#end of sib2, iclass 4, count 2 2006.260.08:03:23.16#ibcon#*after write, iclass 4, count 2 2006.260.08:03:23.16#ibcon#*before return 0, iclass 4, count 2 2006.260.08:03:23.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:23.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:03:23.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.08:03:23.16#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:23.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:23.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:23.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:23.28#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:03:23.28#ibcon#first serial, iclass 4, count 0 2006.260.08:03:23.28#ibcon#enter sib2, iclass 4, count 0 2006.260.08:03:23.28#ibcon#flushed, iclass 4, count 0 2006.260.08:03:23.28#ibcon#about to write, iclass 4, count 0 2006.260.08:03:23.28#ibcon#wrote, iclass 4, count 0 2006.260.08:03:23.28#ibcon#about to read 3, iclass 4, count 0 2006.260.08:03:23.30#ibcon#read 3, iclass 4, count 0 2006.260.08:03:23.30#ibcon#about to read 4, iclass 4, count 0 2006.260.08:03:23.30#ibcon#read 4, iclass 4, count 0 2006.260.08:03:23.30#ibcon#about to read 5, iclass 4, count 0 2006.260.08:03:23.30#ibcon#read 5, iclass 4, count 0 2006.260.08:03:23.30#ibcon#about to read 6, iclass 4, count 0 2006.260.08:03:23.30#ibcon#read 6, iclass 4, count 0 2006.260.08:03:23.30#ibcon#end of sib2, iclass 4, count 0 2006.260.08:03:23.30#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:03:23.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:03:23.30#ibcon#[27=USB\r\n] 2006.260.08:03:23.30#ibcon#*before write, iclass 4, count 0 2006.260.08:03:23.30#ibcon#enter sib2, iclass 4, count 0 2006.260.08:03:23.30#ibcon#flushed, iclass 4, count 0 2006.260.08:03:23.30#ibcon#about to write, iclass 4, count 0 2006.260.08:03:23.30#ibcon#wrote, iclass 4, count 0 2006.260.08:03:23.30#ibcon#about to read 3, iclass 4, count 0 2006.260.08:03:23.33#ibcon#read 3, iclass 4, count 0 2006.260.08:03:23.33#ibcon#about to read 4, iclass 4, count 0 2006.260.08:03:23.33#ibcon#read 4, iclass 4, count 0 2006.260.08:03:23.33#ibcon#about to read 5, iclass 4, count 0 2006.260.08:03:23.33#ibcon#read 5, iclass 4, count 0 2006.260.08:03:23.33#ibcon#about to read 6, iclass 4, count 0 2006.260.08:03:23.33#ibcon#read 6, iclass 4, count 0 2006.260.08:03:23.33#ibcon#end of sib2, iclass 4, count 0 2006.260.08:03:23.33#ibcon#*after write, iclass 4, count 0 2006.260.08:03:23.33#ibcon#*before return 0, iclass 4, count 0 2006.260.08:03:23.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:23.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:03:23.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:03:23.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:03:23.33$vc4f8/vblo=6,752.99 2006.260.08:03:23.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:03:23.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:03:23.33#ibcon#ireg 17 cls_cnt 0 2006.260.08:03:23.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:23.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:23.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:23.33#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:03:23.33#ibcon#first serial, iclass 6, count 0 2006.260.08:03:23.33#ibcon#enter sib2, iclass 6, count 0 2006.260.08:03:23.33#ibcon#flushed, iclass 6, count 0 2006.260.08:03:23.33#ibcon#about to write, iclass 6, count 0 2006.260.08:03:23.33#ibcon#wrote, iclass 6, count 0 2006.260.08:03:23.33#ibcon#about to read 3, iclass 6, count 0 2006.260.08:03:23.35#ibcon#read 3, iclass 6, count 0 2006.260.08:03:23.35#ibcon#about to read 4, iclass 6, count 0 2006.260.08:03:23.35#ibcon#read 4, iclass 6, count 0 2006.260.08:03:23.35#ibcon#about to read 5, iclass 6, count 0 2006.260.08:03:23.35#ibcon#read 5, iclass 6, count 0 2006.260.08:03:23.35#ibcon#about to read 6, iclass 6, count 0 2006.260.08:03:23.35#ibcon#read 6, iclass 6, count 0 2006.260.08:03:23.35#ibcon#end of sib2, iclass 6, count 0 2006.260.08:03:23.35#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:03:23.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:03:23.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:03:23.35#ibcon#*before write, iclass 6, count 0 2006.260.08:03:23.35#ibcon#enter sib2, iclass 6, count 0 2006.260.08:03:23.35#ibcon#flushed, iclass 6, count 0 2006.260.08:03:23.35#ibcon#about to write, iclass 6, count 0 2006.260.08:03:23.35#ibcon#wrote, iclass 6, count 0 2006.260.08:03:23.35#ibcon#about to read 3, iclass 6, count 0 2006.260.08:03:23.39#ibcon#read 3, iclass 6, count 0 2006.260.08:03:23.39#ibcon#about to read 4, iclass 6, count 0 2006.260.08:03:23.39#ibcon#read 4, iclass 6, count 0 2006.260.08:03:23.39#ibcon#about to read 5, iclass 6, count 0 2006.260.08:03:23.39#ibcon#read 5, iclass 6, count 0 2006.260.08:03:23.39#ibcon#about to read 6, iclass 6, count 0 2006.260.08:03:23.39#ibcon#read 6, iclass 6, count 0 2006.260.08:03:23.39#ibcon#end of sib2, iclass 6, count 0 2006.260.08:03:23.39#ibcon#*after write, iclass 6, count 0 2006.260.08:03:23.39#ibcon#*before return 0, iclass 6, count 0 2006.260.08:03:23.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:23.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:03:23.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:03:23.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:03:23.39$vc4f8/vb=6,4 2006.260.08:03:23.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.08:03:23.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.08:03:23.39#ibcon#ireg 11 cls_cnt 2 2006.260.08:03:23.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:23.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:23.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:23.45#ibcon#enter wrdev, iclass 10, count 2 2006.260.08:03:23.45#ibcon#first serial, iclass 10, count 2 2006.260.08:03:23.45#ibcon#enter sib2, iclass 10, count 2 2006.260.08:03:23.45#ibcon#flushed, iclass 10, count 2 2006.260.08:03:23.45#ibcon#about to write, iclass 10, count 2 2006.260.08:03:23.45#ibcon#wrote, iclass 10, count 2 2006.260.08:03:23.45#ibcon#about to read 3, iclass 10, count 2 2006.260.08:03:23.47#ibcon#read 3, iclass 10, count 2 2006.260.08:03:23.47#ibcon#about to read 4, iclass 10, count 2 2006.260.08:03:23.47#ibcon#read 4, iclass 10, count 2 2006.260.08:03:23.47#ibcon#about to read 5, iclass 10, count 2 2006.260.08:03:23.47#ibcon#read 5, iclass 10, count 2 2006.260.08:03:23.47#ibcon#about to read 6, iclass 10, count 2 2006.260.08:03:23.47#ibcon#read 6, iclass 10, count 2 2006.260.08:03:23.47#ibcon#end of sib2, iclass 10, count 2 2006.260.08:03:23.47#ibcon#*mode == 0, iclass 10, count 2 2006.260.08:03:23.47#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.08:03:23.47#ibcon#[27=AT06-04\r\n] 2006.260.08:03:23.47#ibcon#*before write, iclass 10, count 2 2006.260.08:03:23.47#ibcon#enter sib2, iclass 10, count 2 2006.260.08:03:23.47#ibcon#flushed, iclass 10, count 2 2006.260.08:03:23.47#ibcon#about to write, iclass 10, count 2 2006.260.08:03:23.47#ibcon#wrote, iclass 10, count 2 2006.260.08:03:23.47#ibcon#about to read 3, iclass 10, count 2 2006.260.08:03:23.50#ibcon#read 3, iclass 10, count 2 2006.260.08:03:23.50#ibcon#about to read 4, iclass 10, count 2 2006.260.08:03:23.50#ibcon#read 4, iclass 10, count 2 2006.260.08:03:23.50#ibcon#about to read 5, iclass 10, count 2 2006.260.08:03:23.50#ibcon#read 5, iclass 10, count 2 2006.260.08:03:23.50#ibcon#about to read 6, iclass 10, count 2 2006.260.08:03:23.50#ibcon#read 6, iclass 10, count 2 2006.260.08:03:23.50#ibcon#end of sib2, iclass 10, count 2 2006.260.08:03:23.50#ibcon#*after write, iclass 10, count 2 2006.260.08:03:23.50#ibcon#*before return 0, iclass 10, count 2 2006.260.08:03:23.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:23.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:03:23.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.08:03:23.50#ibcon#ireg 7 cls_cnt 0 2006.260.08:03:23.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:23.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:23.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:23.62#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:03:23.62#ibcon#first serial, iclass 10, count 0 2006.260.08:03:23.62#ibcon#enter sib2, iclass 10, count 0 2006.260.08:03:23.62#ibcon#flushed, iclass 10, count 0 2006.260.08:03:23.62#ibcon#about to write, iclass 10, count 0 2006.260.08:03:23.62#ibcon#wrote, iclass 10, count 0 2006.260.08:03:23.62#ibcon#about to read 3, iclass 10, count 0 2006.260.08:03:23.64#ibcon#read 3, iclass 10, count 0 2006.260.08:03:23.64#ibcon#about to read 4, iclass 10, count 0 2006.260.08:03:23.64#ibcon#read 4, iclass 10, count 0 2006.260.08:03:23.64#ibcon#about to read 5, iclass 10, count 0 2006.260.08:03:23.64#ibcon#read 5, iclass 10, count 0 2006.260.08:03:23.64#ibcon#about to read 6, iclass 10, count 0 2006.260.08:03:23.64#ibcon#read 6, iclass 10, count 0 2006.260.08:03:23.64#ibcon#end of sib2, iclass 10, count 0 2006.260.08:03:23.64#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:03:23.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:03:23.64#ibcon#[27=USB\r\n] 2006.260.08:03:23.64#ibcon#*before write, iclass 10, count 0 2006.260.08:03:23.64#ibcon#enter sib2, iclass 10, count 0 2006.260.08:03:23.64#ibcon#flushed, iclass 10, count 0 2006.260.08:03:23.64#ibcon#about to write, iclass 10, count 0 2006.260.08:03:23.64#ibcon#wrote, iclass 10, count 0 2006.260.08:03:23.64#ibcon#about to read 3, iclass 10, count 0 2006.260.08:03:23.67#ibcon#read 3, iclass 10, count 0 2006.260.08:03:23.67#ibcon#about to read 4, iclass 10, count 0 2006.260.08:03:23.67#ibcon#read 4, iclass 10, count 0 2006.260.08:03:23.67#ibcon#about to read 5, iclass 10, count 0 2006.260.08:03:23.67#ibcon#read 5, iclass 10, count 0 2006.260.08:03:23.67#ibcon#about to read 6, iclass 10, count 0 2006.260.08:03:23.67#ibcon#read 6, iclass 10, count 0 2006.260.08:03:23.67#ibcon#end of sib2, iclass 10, count 0 2006.260.08:03:23.67#ibcon#*after write, iclass 10, count 0 2006.260.08:03:23.67#ibcon#*before return 0, iclass 10, count 0 2006.260.08:03:23.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:23.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:03:23.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:03:23.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:03:23.67$vc4f8/vabw=wide 2006.260.08:03:23.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:03:23.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:03:23.67#ibcon#ireg 8 cls_cnt 0 2006.260.08:03:23.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:23.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:23.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:23.67#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:03:23.67#ibcon#first serial, iclass 12, count 0 2006.260.08:03:23.67#ibcon#enter sib2, iclass 12, count 0 2006.260.08:03:23.67#ibcon#flushed, iclass 12, count 0 2006.260.08:03:23.67#ibcon#about to write, iclass 12, count 0 2006.260.08:03:23.67#ibcon#wrote, iclass 12, count 0 2006.260.08:03:23.67#ibcon#about to read 3, iclass 12, count 0 2006.260.08:03:23.69#ibcon#read 3, iclass 12, count 0 2006.260.08:03:23.69#ibcon#about to read 4, iclass 12, count 0 2006.260.08:03:23.69#ibcon#read 4, iclass 12, count 0 2006.260.08:03:23.69#ibcon#about to read 5, iclass 12, count 0 2006.260.08:03:23.69#ibcon#read 5, iclass 12, count 0 2006.260.08:03:23.69#ibcon#about to read 6, iclass 12, count 0 2006.260.08:03:23.69#ibcon#read 6, iclass 12, count 0 2006.260.08:03:23.69#ibcon#end of sib2, iclass 12, count 0 2006.260.08:03:23.69#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:03:23.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:03:23.69#ibcon#[25=BW32\r\n] 2006.260.08:03:23.69#ibcon#*before write, iclass 12, count 0 2006.260.08:03:23.69#ibcon#enter sib2, iclass 12, count 0 2006.260.08:03:23.69#ibcon#flushed, iclass 12, count 0 2006.260.08:03:23.69#ibcon#about to write, iclass 12, count 0 2006.260.08:03:23.69#ibcon#wrote, iclass 12, count 0 2006.260.08:03:23.69#ibcon#about to read 3, iclass 12, count 0 2006.260.08:03:23.72#ibcon#read 3, iclass 12, count 0 2006.260.08:03:23.72#ibcon#about to read 4, iclass 12, count 0 2006.260.08:03:23.72#ibcon#read 4, iclass 12, count 0 2006.260.08:03:23.72#ibcon#about to read 5, iclass 12, count 0 2006.260.08:03:23.72#ibcon#read 5, iclass 12, count 0 2006.260.08:03:23.72#ibcon#about to read 6, iclass 12, count 0 2006.260.08:03:23.72#ibcon#read 6, iclass 12, count 0 2006.260.08:03:23.72#ibcon#end of sib2, iclass 12, count 0 2006.260.08:03:23.72#ibcon#*after write, iclass 12, count 0 2006.260.08:03:23.72#ibcon#*before return 0, iclass 12, count 0 2006.260.08:03:23.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:23.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:03:23.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:03:23.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:03:23.72$vc4f8/vbbw=wide 2006.260.08:03:23.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:03:23.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:03:23.72#ibcon#ireg 8 cls_cnt 0 2006.260.08:03:23.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:03:23.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:03:23.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:03:23.79#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:03:23.79#ibcon#first serial, iclass 14, count 0 2006.260.08:03:23.79#ibcon#enter sib2, iclass 14, count 0 2006.260.08:03:23.79#ibcon#flushed, iclass 14, count 0 2006.260.08:03:23.79#ibcon#about to write, iclass 14, count 0 2006.260.08:03:23.79#ibcon#wrote, iclass 14, count 0 2006.260.08:03:23.79#ibcon#about to read 3, iclass 14, count 0 2006.260.08:03:23.81#ibcon#read 3, iclass 14, count 0 2006.260.08:03:23.81#ibcon#about to read 4, iclass 14, count 0 2006.260.08:03:23.81#ibcon#read 4, iclass 14, count 0 2006.260.08:03:23.81#ibcon#about to read 5, iclass 14, count 0 2006.260.08:03:23.81#ibcon#read 5, iclass 14, count 0 2006.260.08:03:23.81#ibcon#about to read 6, iclass 14, count 0 2006.260.08:03:23.81#ibcon#read 6, iclass 14, count 0 2006.260.08:03:23.81#ibcon#end of sib2, iclass 14, count 0 2006.260.08:03:23.81#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:03:23.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:03:23.81#ibcon#[27=BW32\r\n] 2006.260.08:03:23.81#ibcon#*before write, iclass 14, count 0 2006.260.08:03:23.81#ibcon#enter sib2, iclass 14, count 0 2006.260.08:03:23.81#ibcon#flushed, iclass 14, count 0 2006.260.08:03:23.81#ibcon#about to write, iclass 14, count 0 2006.260.08:03:23.81#ibcon#wrote, iclass 14, count 0 2006.260.08:03:23.81#ibcon#about to read 3, iclass 14, count 0 2006.260.08:03:23.84#ibcon#read 3, iclass 14, count 0 2006.260.08:03:23.84#ibcon#about to read 4, iclass 14, count 0 2006.260.08:03:23.84#ibcon#read 4, iclass 14, count 0 2006.260.08:03:23.84#ibcon#about to read 5, iclass 14, count 0 2006.260.08:03:23.84#ibcon#read 5, iclass 14, count 0 2006.260.08:03:23.84#ibcon#about to read 6, iclass 14, count 0 2006.260.08:03:23.84#ibcon#read 6, iclass 14, count 0 2006.260.08:03:23.84#ibcon#end of sib2, iclass 14, count 0 2006.260.08:03:23.84#ibcon#*after write, iclass 14, count 0 2006.260.08:03:23.84#ibcon#*before return 0, iclass 14, count 0 2006.260.08:03:23.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:03:23.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:03:23.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:03:23.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:03:23.84$4f8m12a/ifd4f 2006.260.08:03:23.84$ifd4f/lo= 2006.260.08:03:23.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:03:23.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:03:23.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:03:23.84$ifd4f/patch= 2006.260.08:03:23.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:03:23.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:03:23.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:03:23.84$4f8m12a/"form=m,16.000,1:2 2006.260.08:03:23.84$4f8m12a/"tpicd 2006.260.08:03:23.84$4f8m12a/echo=off 2006.260.08:03:23.84$4f8m12a/xlog=off 2006.260.08:03:23.84:!2006.260.08:03:50 2006.260.08:03:32.14#trakl#Source acquired 2006.260.08:03:32.14#flagr#flagr/antenna,acquired 2006.260.08:03:50.00:preob 2006.260.08:03:51.14/onsource/TRACKING 2006.260.08:03:51.14:!2006.260.08:04:00 2006.260.08:04:00.00:data_valid=on 2006.260.08:04:00.00:midob 2006.260.08:04:00.14/onsource/TRACKING 2006.260.08:04:00.14/wx/22.84,1010.4,88 2006.260.08:04:00.31/cable/+6.4571E-03 2006.260.08:04:01.40/va/01,08,usb,yes,32,34 2006.260.08:04:01.40/va/02,07,usb,yes,32,34 2006.260.08:04:01.40/va/03,08,usb,yes,24,24 2006.260.08:04:01.40/va/04,07,usb,yes,33,36 2006.260.08:04:01.40/va/05,07,usb,yes,37,39 2006.260.08:04:01.40/va/06,06,usb,yes,36,36 2006.260.08:04:01.40/va/07,06,usb,yes,37,36 2006.260.08:04:01.40/va/08,06,usb,yes,39,38 2006.260.08:04:01.63/valo/01,532.99,yes,locked 2006.260.08:04:01.63/valo/02,572.99,yes,locked 2006.260.08:04:01.63/valo/03,672.99,yes,locked 2006.260.08:04:01.63/valo/04,832.99,yes,locked 2006.260.08:04:01.63/valo/05,652.99,yes,locked 2006.260.08:04:01.63/valo/06,772.99,yes,locked 2006.260.08:04:01.63/valo/07,832.99,yes,locked 2006.260.08:04:01.63/valo/08,852.99,yes,locked 2006.260.08:04:02.72/vb/01,04,usb,yes,31,29 2006.260.08:04:02.72/vb/02,05,usb,yes,28,30 2006.260.08:04:02.72/vb/03,04,usb,yes,29,33 2006.260.08:04:02.72/vb/04,05,usb,yes,26,26 2006.260.08:04:02.72/vb/05,04,usb,yes,28,32 2006.260.08:04:02.72/vb/06,04,usb,yes,29,32 2006.260.08:04:02.72/vb/07,04,usb,yes,31,31 2006.260.08:04:02.72/vb/08,04,usb,yes,29,32 2006.260.08:04:02.96/vblo/01,632.99,yes,locked 2006.260.08:04:02.96/vblo/02,640.99,yes,locked 2006.260.08:04:02.96/vblo/03,656.99,yes,locked 2006.260.08:04:02.96/vblo/04,712.99,yes,locked 2006.260.08:04:02.96/vblo/05,744.99,yes,locked 2006.260.08:04:02.96/vblo/06,752.99,yes,locked 2006.260.08:04:02.96/vblo/07,734.99,yes,locked 2006.260.08:04:02.96/vblo/08,744.99,yes,locked 2006.260.08:04:03.11/vabw/8 2006.260.08:04:03.26/vbbw/8 2006.260.08:04:03.35/xfe/off,on,15.0 2006.260.08:04:03.74/ifatt/23,28,28,28 2006.260.08:04:04.07/fmout-gps/S +4.47E-07 2006.260.08:04:04.11:!2006.260.08:05:00 2006.260.08:05:00.00:data_valid=off 2006.260.08:05:00.00:postob 2006.260.08:05:00.08/cable/+6.4564E-03 2006.260.08:05:00.08/wx/22.83,1010.4,88 2006.260.08:05:01.07/fmout-gps/S +4.47E-07 2006.260.08:05:01.07:scan_name=260-0805,k06260,60 2006.260.08:05:01.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.260.08:05:01.14#flagr#flagr/antenna,new-source 2006.260.08:05:02.14:checkk5 2006.260.08:05:02.60/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:05:03.00/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:05:03.45/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:05:04.07/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:05:04.64/chk_obsdata//k5ts1/T2600804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:05:05.05/chk_obsdata//k5ts2/T2600804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:05:05.77/chk_obsdata//k5ts3/T2600804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:05:06.17/chk_obsdata//k5ts4/T2600804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:05:06.96/k5log//k5ts1_log_newline 2006.260.08:05:07.71/k5log//k5ts2_log_newline 2006.260.08:05:08.49/k5log//k5ts3_log_newline 2006.260.08:05:09.27/k5log//k5ts4_log_newline 2006.260.08:05:09.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:05:09.29:4f8m12a=2 2006.260.08:05:09.29$4f8m12a/echo=on 2006.260.08:05:09.29$4f8m12a/pcalon 2006.260.08:05:09.29$pcalon/"no phase cal control is implemented here 2006.260.08:05:09.29$4f8m12a/"tpicd=stop 2006.260.08:05:09.29$4f8m12a/vc4f8 2006.260.08:05:09.29$vc4f8/valo=1,532.99 2006.260.08:05:09.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:05:09.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:05:09.30#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:09.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:09.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:09.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:09.30#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:05:09.30#ibcon#first serial, iclass 25, count 0 2006.260.08:05:09.30#ibcon#enter sib2, iclass 25, count 0 2006.260.08:05:09.30#ibcon#flushed, iclass 25, count 0 2006.260.08:05:09.30#ibcon#about to write, iclass 25, count 0 2006.260.08:05:09.30#ibcon#wrote, iclass 25, count 0 2006.260.08:05:09.30#ibcon#about to read 3, iclass 25, count 0 2006.260.08:05:09.34#ibcon#read 3, iclass 25, count 0 2006.260.08:05:09.34#ibcon#about to read 4, iclass 25, count 0 2006.260.08:05:09.34#ibcon#read 4, iclass 25, count 0 2006.260.08:05:09.34#ibcon#about to read 5, iclass 25, count 0 2006.260.08:05:09.34#ibcon#read 5, iclass 25, count 0 2006.260.08:05:09.34#ibcon#about to read 6, iclass 25, count 0 2006.260.08:05:09.34#ibcon#read 6, iclass 25, count 0 2006.260.08:05:09.34#ibcon#end of sib2, iclass 25, count 0 2006.260.08:05:09.34#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:05:09.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:05:09.34#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:05:09.34#ibcon#*before write, iclass 25, count 0 2006.260.08:05:09.34#ibcon#enter sib2, iclass 25, count 0 2006.260.08:05:09.34#ibcon#flushed, iclass 25, count 0 2006.260.08:05:09.34#ibcon#about to write, iclass 25, count 0 2006.260.08:05:09.34#ibcon#wrote, iclass 25, count 0 2006.260.08:05:09.34#ibcon#about to read 3, iclass 25, count 0 2006.260.08:05:09.38#ibcon#read 3, iclass 25, count 0 2006.260.08:05:09.38#ibcon#about to read 4, iclass 25, count 0 2006.260.08:05:09.38#ibcon#read 4, iclass 25, count 0 2006.260.08:05:09.38#ibcon#about to read 5, iclass 25, count 0 2006.260.08:05:09.38#ibcon#read 5, iclass 25, count 0 2006.260.08:05:09.38#ibcon#about to read 6, iclass 25, count 0 2006.260.08:05:09.38#ibcon#read 6, iclass 25, count 0 2006.260.08:05:09.38#ibcon#end of sib2, iclass 25, count 0 2006.260.08:05:09.38#ibcon#*after write, iclass 25, count 0 2006.260.08:05:09.38#ibcon#*before return 0, iclass 25, count 0 2006.260.08:05:09.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:09.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:09.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:05:09.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:05:09.38$vc4f8/va=1,8 2006.260.08:05:09.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:05:09.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:05:09.38#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:09.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:09.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:09.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:09.38#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:05:09.38#ibcon#first serial, iclass 27, count 2 2006.260.08:05:09.38#ibcon#enter sib2, iclass 27, count 2 2006.260.08:05:09.38#ibcon#flushed, iclass 27, count 2 2006.260.08:05:09.38#ibcon#about to write, iclass 27, count 2 2006.260.08:05:09.38#ibcon#wrote, iclass 27, count 2 2006.260.08:05:09.38#ibcon#about to read 3, iclass 27, count 2 2006.260.08:05:09.40#ibcon#read 3, iclass 27, count 2 2006.260.08:05:09.40#ibcon#about to read 4, iclass 27, count 2 2006.260.08:05:09.40#ibcon#read 4, iclass 27, count 2 2006.260.08:05:09.40#ibcon#about to read 5, iclass 27, count 2 2006.260.08:05:09.40#ibcon#read 5, iclass 27, count 2 2006.260.08:05:09.40#ibcon#about to read 6, iclass 27, count 2 2006.260.08:05:09.40#ibcon#read 6, iclass 27, count 2 2006.260.08:05:09.40#ibcon#end of sib2, iclass 27, count 2 2006.260.08:05:09.40#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:05:09.40#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:05:09.40#ibcon#[25=AT01-08\r\n] 2006.260.08:05:09.40#ibcon#*before write, iclass 27, count 2 2006.260.08:05:09.40#ibcon#enter sib2, iclass 27, count 2 2006.260.08:05:09.40#ibcon#flushed, iclass 27, count 2 2006.260.08:05:09.40#ibcon#about to write, iclass 27, count 2 2006.260.08:05:09.40#ibcon#wrote, iclass 27, count 2 2006.260.08:05:09.40#ibcon#about to read 3, iclass 27, count 2 2006.260.08:05:09.44#ibcon#read 3, iclass 27, count 2 2006.260.08:05:09.44#ibcon#about to read 4, iclass 27, count 2 2006.260.08:05:09.44#ibcon#read 4, iclass 27, count 2 2006.260.08:05:09.44#ibcon#about to read 5, iclass 27, count 2 2006.260.08:05:09.44#ibcon#read 5, iclass 27, count 2 2006.260.08:05:09.44#ibcon#about to read 6, iclass 27, count 2 2006.260.08:05:09.44#ibcon#read 6, iclass 27, count 2 2006.260.08:05:09.44#ibcon#end of sib2, iclass 27, count 2 2006.260.08:05:09.44#ibcon#*after write, iclass 27, count 2 2006.260.08:05:09.44#ibcon#*before return 0, iclass 27, count 2 2006.260.08:05:09.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:09.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:09.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:05:09.44#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:09.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:09.55#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:09.55#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:09.55#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:05:09.55#ibcon#first serial, iclass 27, count 0 2006.260.08:05:09.55#ibcon#enter sib2, iclass 27, count 0 2006.260.08:05:09.55#ibcon#flushed, iclass 27, count 0 2006.260.08:05:09.55#ibcon#about to write, iclass 27, count 0 2006.260.08:05:09.55#ibcon#wrote, iclass 27, count 0 2006.260.08:05:09.55#ibcon#about to read 3, iclass 27, count 0 2006.260.08:05:09.57#ibcon#read 3, iclass 27, count 0 2006.260.08:05:09.57#ibcon#about to read 4, iclass 27, count 0 2006.260.08:05:09.57#ibcon#read 4, iclass 27, count 0 2006.260.08:05:09.57#ibcon#about to read 5, iclass 27, count 0 2006.260.08:05:09.57#ibcon#read 5, iclass 27, count 0 2006.260.08:05:09.57#ibcon#about to read 6, iclass 27, count 0 2006.260.08:05:09.57#ibcon#read 6, iclass 27, count 0 2006.260.08:05:09.57#ibcon#end of sib2, iclass 27, count 0 2006.260.08:05:09.57#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:05:09.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:05:09.57#ibcon#[25=USB\r\n] 2006.260.08:05:09.57#ibcon#*before write, iclass 27, count 0 2006.260.08:05:09.57#ibcon#enter sib2, iclass 27, count 0 2006.260.08:05:09.57#ibcon#flushed, iclass 27, count 0 2006.260.08:05:09.57#ibcon#about to write, iclass 27, count 0 2006.260.08:05:09.57#ibcon#wrote, iclass 27, count 0 2006.260.08:05:09.57#ibcon#about to read 3, iclass 27, count 0 2006.260.08:05:09.60#ibcon#read 3, iclass 27, count 0 2006.260.08:05:09.60#ibcon#about to read 4, iclass 27, count 0 2006.260.08:05:09.60#ibcon#read 4, iclass 27, count 0 2006.260.08:05:09.60#ibcon#about to read 5, iclass 27, count 0 2006.260.08:05:09.60#ibcon#read 5, iclass 27, count 0 2006.260.08:05:09.60#ibcon#about to read 6, iclass 27, count 0 2006.260.08:05:09.60#ibcon#read 6, iclass 27, count 0 2006.260.08:05:09.60#ibcon#end of sib2, iclass 27, count 0 2006.260.08:05:09.60#ibcon#*after write, iclass 27, count 0 2006.260.08:05:09.60#ibcon#*before return 0, iclass 27, count 0 2006.260.08:05:09.60#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:09.60#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:09.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:05:09.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:05:09.60$vc4f8/valo=2,572.99 2006.260.08:05:09.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:05:09.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:05:09.60#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:09.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:09.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:09.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:09.60#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:05:09.60#ibcon#first serial, iclass 29, count 0 2006.260.08:05:09.60#ibcon#enter sib2, iclass 29, count 0 2006.260.08:05:09.60#ibcon#flushed, iclass 29, count 0 2006.260.08:05:09.60#ibcon#about to write, iclass 29, count 0 2006.260.08:05:09.60#ibcon#wrote, iclass 29, count 0 2006.260.08:05:09.60#ibcon#about to read 3, iclass 29, count 0 2006.260.08:05:09.62#ibcon#read 3, iclass 29, count 0 2006.260.08:05:09.62#ibcon#about to read 4, iclass 29, count 0 2006.260.08:05:09.62#ibcon#read 4, iclass 29, count 0 2006.260.08:05:09.62#ibcon#about to read 5, iclass 29, count 0 2006.260.08:05:09.62#ibcon#read 5, iclass 29, count 0 2006.260.08:05:09.62#ibcon#about to read 6, iclass 29, count 0 2006.260.08:05:09.62#ibcon#read 6, iclass 29, count 0 2006.260.08:05:09.62#ibcon#end of sib2, iclass 29, count 0 2006.260.08:05:09.62#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:05:09.62#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:05:09.62#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:05:09.62#ibcon#*before write, iclass 29, count 0 2006.260.08:05:09.62#ibcon#enter sib2, iclass 29, count 0 2006.260.08:05:09.62#ibcon#flushed, iclass 29, count 0 2006.260.08:05:09.62#ibcon#about to write, iclass 29, count 0 2006.260.08:05:09.62#ibcon#wrote, iclass 29, count 0 2006.260.08:05:09.62#ibcon#about to read 3, iclass 29, count 0 2006.260.08:05:09.66#ibcon#read 3, iclass 29, count 0 2006.260.08:05:09.66#ibcon#about to read 4, iclass 29, count 0 2006.260.08:05:09.66#ibcon#read 4, iclass 29, count 0 2006.260.08:05:09.66#ibcon#about to read 5, iclass 29, count 0 2006.260.08:05:09.66#ibcon#read 5, iclass 29, count 0 2006.260.08:05:09.66#ibcon#about to read 6, iclass 29, count 0 2006.260.08:05:09.66#ibcon#read 6, iclass 29, count 0 2006.260.08:05:09.66#ibcon#end of sib2, iclass 29, count 0 2006.260.08:05:09.66#ibcon#*after write, iclass 29, count 0 2006.260.08:05:09.66#ibcon#*before return 0, iclass 29, count 0 2006.260.08:05:09.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:09.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:09.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:05:09.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:05:09.66$vc4f8/va=2,7 2006.260.08:05:09.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:05:09.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:05:09.66#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:09.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:09.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:09.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:09.72#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:05:09.72#ibcon#first serial, iclass 31, count 2 2006.260.08:05:09.72#ibcon#enter sib2, iclass 31, count 2 2006.260.08:05:09.72#ibcon#flushed, iclass 31, count 2 2006.260.08:05:09.72#ibcon#about to write, iclass 31, count 2 2006.260.08:05:09.72#ibcon#wrote, iclass 31, count 2 2006.260.08:05:09.72#ibcon#about to read 3, iclass 31, count 2 2006.260.08:05:09.75#ibcon#read 3, iclass 31, count 2 2006.260.08:05:09.75#ibcon#about to read 4, iclass 31, count 2 2006.260.08:05:09.75#ibcon#read 4, iclass 31, count 2 2006.260.08:05:09.75#ibcon#about to read 5, iclass 31, count 2 2006.260.08:05:09.75#ibcon#read 5, iclass 31, count 2 2006.260.08:05:09.75#ibcon#about to read 6, iclass 31, count 2 2006.260.08:05:09.75#ibcon#read 6, iclass 31, count 2 2006.260.08:05:09.75#ibcon#end of sib2, iclass 31, count 2 2006.260.08:05:09.75#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:05:09.75#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:05:09.75#ibcon#[25=AT02-07\r\n] 2006.260.08:05:09.75#ibcon#*before write, iclass 31, count 2 2006.260.08:05:09.75#ibcon#enter sib2, iclass 31, count 2 2006.260.08:05:09.75#ibcon#flushed, iclass 31, count 2 2006.260.08:05:09.75#ibcon#about to write, iclass 31, count 2 2006.260.08:05:09.75#ibcon#wrote, iclass 31, count 2 2006.260.08:05:09.75#ibcon#about to read 3, iclass 31, count 2 2006.260.08:05:09.78#ibcon#read 3, iclass 31, count 2 2006.260.08:05:09.78#ibcon#about to read 4, iclass 31, count 2 2006.260.08:05:09.78#ibcon#read 4, iclass 31, count 2 2006.260.08:05:09.78#ibcon#about to read 5, iclass 31, count 2 2006.260.08:05:09.78#ibcon#read 5, iclass 31, count 2 2006.260.08:05:09.78#ibcon#about to read 6, iclass 31, count 2 2006.260.08:05:09.78#ibcon#read 6, iclass 31, count 2 2006.260.08:05:09.78#ibcon#end of sib2, iclass 31, count 2 2006.260.08:05:09.78#ibcon#*after write, iclass 31, count 2 2006.260.08:05:09.78#ibcon#*before return 0, iclass 31, count 2 2006.260.08:05:09.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:09.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:09.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:05:09.78#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:09.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:09.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:09.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:09.90#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:05:09.90#ibcon#first serial, iclass 31, count 0 2006.260.08:05:09.90#ibcon#enter sib2, iclass 31, count 0 2006.260.08:05:09.90#ibcon#flushed, iclass 31, count 0 2006.260.08:05:09.90#ibcon#about to write, iclass 31, count 0 2006.260.08:05:09.90#ibcon#wrote, iclass 31, count 0 2006.260.08:05:09.90#ibcon#about to read 3, iclass 31, count 0 2006.260.08:05:09.92#ibcon#read 3, iclass 31, count 0 2006.260.08:05:09.92#ibcon#about to read 4, iclass 31, count 0 2006.260.08:05:09.92#ibcon#read 4, iclass 31, count 0 2006.260.08:05:09.92#ibcon#about to read 5, iclass 31, count 0 2006.260.08:05:09.92#ibcon#read 5, iclass 31, count 0 2006.260.08:05:09.92#ibcon#about to read 6, iclass 31, count 0 2006.260.08:05:09.92#ibcon#read 6, iclass 31, count 0 2006.260.08:05:09.92#ibcon#end of sib2, iclass 31, count 0 2006.260.08:05:09.92#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:05:09.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:05:09.92#ibcon#[25=USB\r\n] 2006.260.08:05:09.92#ibcon#*before write, iclass 31, count 0 2006.260.08:05:09.92#ibcon#enter sib2, iclass 31, count 0 2006.260.08:05:09.92#ibcon#flushed, iclass 31, count 0 2006.260.08:05:09.92#ibcon#about to write, iclass 31, count 0 2006.260.08:05:09.92#ibcon#wrote, iclass 31, count 0 2006.260.08:05:09.92#ibcon#about to read 3, iclass 31, count 0 2006.260.08:05:09.95#ibcon#read 3, iclass 31, count 0 2006.260.08:05:09.95#ibcon#about to read 4, iclass 31, count 0 2006.260.08:05:09.95#ibcon#read 4, iclass 31, count 0 2006.260.08:05:09.95#ibcon#about to read 5, iclass 31, count 0 2006.260.08:05:09.95#ibcon#read 5, iclass 31, count 0 2006.260.08:05:09.95#ibcon#about to read 6, iclass 31, count 0 2006.260.08:05:09.95#ibcon#read 6, iclass 31, count 0 2006.260.08:05:09.95#ibcon#end of sib2, iclass 31, count 0 2006.260.08:05:09.95#ibcon#*after write, iclass 31, count 0 2006.260.08:05:09.95#ibcon#*before return 0, iclass 31, count 0 2006.260.08:05:09.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:09.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:09.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:05:09.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:05:09.95$vc4f8/valo=3,672.99 2006.260.08:05:09.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:05:09.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:05:09.95#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:09.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:09.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:09.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:09.95#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:05:09.95#ibcon#first serial, iclass 33, count 0 2006.260.08:05:09.95#ibcon#enter sib2, iclass 33, count 0 2006.260.08:05:09.95#ibcon#flushed, iclass 33, count 0 2006.260.08:05:09.95#ibcon#about to write, iclass 33, count 0 2006.260.08:05:09.95#ibcon#wrote, iclass 33, count 0 2006.260.08:05:09.95#ibcon#about to read 3, iclass 33, count 0 2006.260.08:05:09.97#ibcon#read 3, iclass 33, count 0 2006.260.08:05:09.97#ibcon#about to read 4, iclass 33, count 0 2006.260.08:05:09.97#ibcon#read 4, iclass 33, count 0 2006.260.08:05:09.97#ibcon#about to read 5, iclass 33, count 0 2006.260.08:05:09.97#ibcon#read 5, iclass 33, count 0 2006.260.08:05:09.97#ibcon#about to read 6, iclass 33, count 0 2006.260.08:05:09.97#ibcon#read 6, iclass 33, count 0 2006.260.08:05:09.97#ibcon#end of sib2, iclass 33, count 0 2006.260.08:05:09.97#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:05:09.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:05:09.97#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:05:09.97#ibcon#*before write, iclass 33, count 0 2006.260.08:05:09.97#ibcon#enter sib2, iclass 33, count 0 2006.260.08:05:09.97#ibcon#flushed, iclass 33, count 0 2006.260.08:05:09.97#ibcon#about to write, iclass 33, count 0 2006.260.08:05:09.97#ibcon#wrote, iclass 33, count 0 2006.260.08:05:09.97#ibcon#about to read 3, iclass 33, count 0 2006.260.08:05:10.01#ibcon#read 3, iclass 33, count 0 2006.260.08:05:10.01#ibcon#about to read 4, iclass 33, count 0 2006.260.08:05:10.01#ibcon#read 4, iclass 33, count 0 2006.260.08:05:10.01#ibcon#about to read 5, iclass 33, count 0 2006.260.08:05:10.01#ibcon#read 5, iclass 33, count 0 2006.260.08:05:10.01#ibcon#about to read 6, iclass 33, count 0 2006.260.08:05:10.01#ibcon#read 6, iclass 33, count 0 2006.260.08:05:10.01#ibcon#end of sib2, iclass 33, count 0 2006.260.08:05:10.01#ibcon#*after write, iclass 33, count 0 2006.260.08:05:10.01#ibcon#*before return 0, iclass 33, count 0 2006.260.08:05:10.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:10.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:10.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:05:10.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:05:10.01$vc4f8/va=3,8 2006.260.08:05:10.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:05:10.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:05:10.01#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:10.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:10.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:10.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:10.08#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:05:10.08#ibcon#first serial, iclass 35, count 2 2006.260.08:05:10.08#ibcon#enter sib2, iclass 35, count 2 2006.260.08:05:10.08#ibcon#flushed, iclass 35, count 2 2006.260.08:05:10.08#ibcon#about to write, iclass 35, count 2 2006.260.08:05:10.08#ibcon#wrote, iclass 35, count 2 2006.260.08:05:10.08#ibcon#about to read 3, iclass 35, count 2 2006.260.08:05:10.09#ibcon#read 3, iclass 35, count 2 2006.260.08:05:10.09#ibcon#about to read 4, iclass 35, count 2 2006.260.08:05:10.09#ibcon#read 4, iclass 35, count 2 2006.260.08:05:10.09#ibcon#about to read 5, iclass 35, count 2 2006.260.08:05:10.09#ibcon#read 5, iclass 35, count 2 2006.260.08:05:10.09#ibcon#about to read 6, iclass 35, count 2 2006.260.08:05:10.09#ibcon#read 6, iclass 35, count 2 2006.260.08:05:10.09#ibcon#end of sib2, iclass 35, count 2 2006.260.08:05:10.09#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:05:10.09#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:05:10.09#ibcon#[25=AT03-08\r\n] 2006.260.08:05:10.09#ibcon#*before write, iclass 35, count 2 2006.260.08:05:10.09#ibcon#enter sib2, iclass 35, count 2 2006.260.08:05:10.09#ibcon#flushed, iclass 35, count 2 2006.260.08:05:10.09#ibcon#about to write, iclass 35, count 2 2006.260.08:05:10.09#ibcon#wrote, iclass 35, count 2 2006.260.08:05:10.09#ibcon#about to read 3, iclass 35, count 2 2006.260.08:05:10.12#ibcon#read 3, iclass 35, count 2 2006.260.08:05:10.12#ibcon#about to read 4, iclass 35, count 2 2006.260.08:05:10.12#ibcon#read 4, iclass 35, count 2 2006.260.08:05:10.12#ibcon#about to read 5, iclass 35, count 2 2006.260.08:05:10.12#ibcon#read 5, iclass 35, count 2 2006.260.08:05:10.12#ibcon#about to read 6, iclass 35, count 2 2006.260.08:05:10.12#ibcon#read 6, iclass 35, count 2 2006.260.08:05:10.12#ibcon#end of sib2, iclass 35, count 2 2006.260.08:05:10.12#ibcon#*after write, iclass 35, count 2 2006.260.08:05:10.12#ibcon#*before return 0, iclass 35, count 2 2006.260.08:05:10.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:10.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:10.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:05:10.12#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:10.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:10.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:10.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:10.24#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:05:10.24#ibcon#first serial, iclass 35, count 0 2006.260.08:05:10.24#ibcon#enter sib2, iclass 35, count 0 2006.260.08:05:10.24#ibcon#flushed, iclass 35, count 0 2006.260.08:05:10.24#ibcon#about to write, iclass 35, count 0 2006.260.08:05:10.24#ibcon#wrote, iclass 35, count 0 2006.260.08:05:10.24#ibcon#about to read 3, iclass 35, count 0 2006.260.08:05:10.26#ibcon#read 3, iclass 35, count 0 2006.260.08:05:10.26#ibcon#about to read 4, iclass 35, count 0 2006.260.08:05:10.26#ibcon#read 4, iclass 35, count 0 2006.260.08:05:10.26#ibcon#about to read 5, iclass 35, count 0 2006.260.08:05:10.26#ibcon#read 5, iclass 35, count 0 2006.260.08:05:10.26#ibcon#about to read 6, iclass 35, count 0 2006.260.08:05:10.26#ibcon#read 6, iclass 35, count 0 2006.260.08:05:10.26#ibcon#end of sib2, iclass 35, count 0 2006.260.08:05:10.26#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:05:10.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:05:10.26#ibcon#[25=USB\r\n] 2006.260.08:05:10.26#ibcon#*before write, iclass 35, count 0 2006.260.08:05:10.26#ibcon#enter sib2, iclass 35, count 0 2006.260.08:05:10.26#ibcon#flushed, iclass 35, count 0 2006.260.08:05:10.26#ibcon#about to write, iclass 35, count 0 2006.260.08:05:10.26#ibcon#wrote, iclass 35, count 0 2006.260.08:05:10.26#ibcon#about to read 3, iclass 35, count 0 2006.260.08:05:10.29#ibcon#read 3, iclass 35, count 0 2006.260.08:05:10.29#ibcon#about to read 4, iclass 35, count 0 2006.260.08:05:10.29#ibcon#read 4, iclass 35, count 0 2006.260.08:05:10.29#ibcon#about to read 5, iclass 35, count 0 2006.260.08:05:10.29#ibcon#read 5, iclass 35, count 0 2006.260.08:05:10.29#ibcon#about to read 6, iclass 35, count 0 2006.260.08:05:10.29#ibcon#read 6, iclass 35, count 0 2006.260.08:05:10.29#ibcon#end of sib2, iclass 35, count 0 2006.260.08:05:10.29#ibcon#*after write, iclass 35, count 0 2006.260.08:05:10.29#ibcon#*before return 0, iclass 35, count 0 2006.260.08:05:10.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:10.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:10.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:05:10.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:05:10.29$vc4f8/valo=4,832.99 2006.260.08:05:10.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:05:10.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:05:10.29#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:10.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:10.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:10.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:10.29#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:05:10.29#ibcon#first serial, iclass 37, count 0 2006.260.08:05:10.29#ibcon#enter sib2, iclass 37, count 0 2006.260.08:05:10.29#ibcon#flushed, iclass 37, count 0 2006.260.08:05:10.29#ibcon#about to write, iclass 37, count 0 2006.260.08:05:10.29#ibcon#wrote, iclass 37, count 0 2006.260.08:05:10.29#ibcon#about to read 3, iclass 37, count 0 2006.260.08:05:10.31#ibcon#read 3, iclass 37, count 0 2006.260.08:05:10.31#ibcon#about to read 4, iclass 37, count 0 2006.260.08:05:10.31#ibcon#read 4, iclass 37, count 0 2006.260.08:05:10.31#ibcon#about to read 5, iclass 37, count 0 2006.260.08:05:10.31#ibcon#read 5, iclass 37, count 0 2006.260.08:05:10.31#ibcon#about to read 6, iclass 37, count 0 2006.260.08:05:10.31#ibcon#read 6, iclass 37, count 0 2006.260.08:05:10.31#ibcon#end of sib2, iclass 37, count 0 2006.260.08:05:10.31#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:05:10.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:05:10.31#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:05:10.31#ibcon#*before write, iclass 37, count 0 2006.260.08:05:10.31#ibcon#enter sib2, iclass 37, count 0 2006.260.08:05:10.31#ibcon#flushed, iclass 37, count 0 2006.260.08:05:10.31#ibcon#about to write, iclass 37, count 0 2006.260.08:05:10.31#ibcon#wrote, iclass 37, count 0 2006.260.08:05:10.31#ibcon#about to read 3, iclass 37, count 0 2006.260.08:05:10.35#ibcon#read 3, iclass 37, count 0 2006.260.08:05:10.35#ibcon#about to read 4, iclass 37, count 0 2006.260.08:05:10.35#ibcon#read 4, iclass 37, count 0 2006.260.08:05:10.35#ibcon#about to read 5, iclass 37, count 0 2006.260.08:05:10.35#ibcon#read 5, iclass 37, count 0 2006.260.08:05:10.35#ibcon#about to read 6, iclass 37, count 0 2006.260.08:05:10.35#ibcon#read 6, iclass 37, count 0 2006.260.08:05:10.35#ibcon#end of sib2, iclass 37, count 0 2006.260.08:05:10.35#ibcon#*after write, iclass 37, count 0 2006.260.08:05:10.35#ibcon#*before return 0, iclass 37, count 0 2006.260.08:05:10.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:10.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:10.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:05:10.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:05:10.35$vc4f8/va=4,7 2006.260.08:05:10.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.08:05:10.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.08:05:10.35#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:10.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:10.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:10.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:10.41#ibcon#enter wrdev, iclass 39, count 2 2006.260.08:05:10.41#ibcon#first serial, iclass 39, count 2 2006.260.08:05:10.41#ibcon#enter sib2, iclass 39, count 2 2006.260.08:05:10.41#ibcon#flushed, iclass 39, count 2 2006.260.08:05:10.41#ibcon#about to write, iclass 39, count 2 2006.260.08:05:10.41#ibcon#wrote, iclass 39, count 2 2006.260.08:05:10.41#ibcon#about to read 3, iclass 39, count 2 2006.260.08:05:10.43#ibcon#read 3, iclass 39, count 2 2006.260.08:05:10.43#ibcon#about to read 4, iclass 39, count 2 2006.260.08:05:10.43#ibcon#read 4, iclass 39, count 2 2006.260.08:05:10.43#ibcon#about to read 5, iclass 39, count 2 2006.260.08:05:10.43#ibcon#read 5, iclass 39, count 2 2006.260.08:05:10.43#ibcon#about to read 6, iclass 39, count 2 2006.260.08:05:10.43#ibcon#read 6, iclass 39, count 2 2006.260.08:05:10.43#ibcon#end of sib2, iclass 39, count 2 2006.260.08:05:10.43#ibcon#*mode == 0, iclass 39, count 2 2006.260.08:05:10.43#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.08:05:10.43#ibcon#[25=AT04-07\r\n] 2006.260.08:05:10.43#ibcon#*before write, iclass 39, count 2 2006.260.08:05:10.43#ibcon#enter sib2, iclass 39, count 2 2006.260.08:05:10.43#ibcon#flushed, iclass 39, count 2 2006.260.08:05:10.43#ibcon#about to write, iclass 39, count 2 2006.260.08:05:10.43#ibcon#wrote, iclass 39, count 2 2006.260.08:05:10.43#ibcon#about to read 3, iclass 39, count 2 2006.260.08:05:10.46#ibcon#read 3, iclass 39, count 2 2006.260.08:05:10.46#ibcon#about to read 4, iclass 39, count 2 2006.260.08:05:10.46#ibcon#read 4, iclass 39, count 2 2006.260.08:05:10.46#ibcon#about to read 5, iclass 39, count 2 2006.260.08:05:10.46#ibcon#read 5, iclass 39, count 2 2006.260.08:05:10.46#ibcon#about to read 6, iclass 39, count 2 2006.260.08:05:10.46#ibcon#read 6, iclass 39, count 2 2006.260.08:05:10.46#ibcon#end of sib2, iclass 39, count 2 2006.260.08:05:10.46#ibcon#*after write, iclass 39, count 2 2006.260.08:05:10.46#ibcon#*before return 0, iclass 39, count 2 2006.260.08:05:10.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:10.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:10.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.08:05:10.46#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:10.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:10.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:10.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:10.58#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:05:10.58#ibcon#first serial, iclass 39, count 0 2006.260.08:05:10.58#ibcon#enter sib2, iclass 39, count 0 2006.260.08:05:10.58#ibcon#flushed, iclass 39, count 0 2006.260.08:05:10.58#ibcon#about to write, iclass 39, count 0 2006.260.08:05:10.58#ibcon#wrote, iclass 39, count 0 2006.260.08:05:10.58#ibcon#about to read 3, iclass 39, count 0 2006.260.08:05:10.60#ibcon#read 3, iclass 39, count 0 2006.260.08:05:10.60#ibcon#about to read 4, iclass 39, count 0 2006.260.08:05:10.60#ibcon#read 4, iclass 39, count 0 2006.260.08:05:10.60#ibcon#about to read 5, iclass 39, count 0 2006.260.08:05:10.60#ibcon#read 5, iclass 39, count 0 2006.260.08:05:10.60#ibcon#about to read 6, iclass 39, count 0 2006.260.08:05:10.60#ibcon#read 6, iclass 39, count 0 2006.260.08:05:10.60#ibcon#end of sib2, iclass 39, count 0 2006.260.08:05:10.60#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:05:10.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:05:10.60#ibcon#[25=USB\r\n] 2006.260.08:05:10.60#ibcon#*before write, iclass 39, count 0 2006.260.08:05:10.60#ibcon#enter sib2, iclass 39, count 0 2006.260.08:05:10.60#ibcon#flushed, iclass 39, count 0 2006.260.08:05:10.60#ibcon#about to write, iclass 39, count 0 2006.260.08:05:10.60#ibcon#wrote, iclass 39, count 0 2006.260.08:05:10.60#ibcon#about to read 3, iclass 39, count 0 2006.260.08:05:10.63#ibcon#read 3, iclass 39, count 0 2006.260.08:05:10.63#ibcon#about to read 4, iclass 39, count 0 2006.260.08:05:10.63#ibcon#read 4, iclass 39, count 0 2006.260.08:05:10.63#ibcon#about to read 5, iclass 39, count 0 2006.260.08:05:10.63#ibcon#read 5, iclass 39, count 0 2006.260.08:05:10.63#ibcon#about to read 6, iclass 39, count 0 2006.260.08:05:10.63#ibcon#read 6, iclass 39, count 0 2006.260.08:05:10.63#ibcon#end of sib2, iclass 39, count 0 2006.260.08:05:10.63#ibcon#*after write, iclass 39, count 0 2006.260.08:05:10.63#ibcon#*before return 0, iclass 39, count 0 2006.260.08:05:10.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:10.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:10.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:05:10.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:05:10.63$vc4f8/valo=5,652.99 2006.260.08:05:10.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.08:05:10.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.08:05:10.63#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:10.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:10.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:10.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:10.63#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:05:10.63#ibcon#first serial, iclass 3, count 0 2006.260.08:05:10.63#ibcon#enter sib2, iclass 3, count 0 2006.260.08:05:10.63#ibcon#flushed, iclass 3, count 0 2006.260.08:05:10.63#ibcon#about to write, iclass 3, count 0 2006.260.08:05:10.63#ibcon#wrote, iclass 3, count 0 2006.260.08:05:10.63#ibcon#about to read 3, iclass 3, count 0 2006.260.08:05:10.65#ibcon#read 3, iclass 3, count 0 2006.260.08:05:10.65#ibcon#about to read 4, iclass 3, count 0 2006.260.08:05:10.65#ibcon#read 4, iclass 3, count 0 2006.260.08:05:10.65#ibcon#about to read 5, iclass 3, count 0 2006.260.08:05:10.65#ibcon#read 5, iclass 3, count 0 2006.260.08:05:10.65#ibcon#about to read 6, iclass 3, count 0 2006.260.08:05:10.65#ibcon#read 6, iclass 3, count 0 2006.260.08:05:10.65#ibcon#end of sib2, iclass 3, count 0 2006.260.08:05:10.65#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:05:10.65#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:05:10.65#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:05:10.65#ibcon#*before write, iclass 3, count 0 2006.260.08:05:10.65#ibcon#enter sib2, iclass 3, count 0 2006.260.08:05:10.65#ibcon#flushed, iclass 3, count 0 2006.260.08:05:10.65#ibcon#about to write, iclass 3, count 0 2006.260.08:05:10.65#ibcon#wrote, iclass 3, count 0 2006.260.08:05:10.65#ibcon#about to read 3, iclass 3, count 0 2006.260.08:05:10.69#ibcon#read 3, iclass 3, count 0 2006.260.08:05:10.69#ibcon#about to read 4, iclass 3, count 0 2006.260.08:05:10.69#ibcon#read 4, iclass 3, count 0 2006.260.08:05:10.69#ibcon#about to read 5, iclass 3, count 0 2006.260.08:05:10.69#ibcon#read 5, iclass 3, count 0 2006.260.08:05:10.69#ibcon#about to read 6, iclass 3, count 0 2006.260.08:05:10.69#ibcon#read 6, iclass 3, count 0 2006.260.08:05:10.69#ibcon#end of sib2, iclass 3, count 0 2006.260.08:05:10.69#ibcon#*after write, iclass 3, count 0 2006.260.08:05:10.69#ibcon#*before return 0, iclass 3, count 0 2006.260.08:05:10.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:10.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:10.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:05:10.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:05:10.69$vc4f8/va=5,7 2006.260.08:05:10.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.08:05:10.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.08:05:10.69#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:10.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:10.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:10.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:10.75#ibcon#enter wrdev, iclass 5, count 2 2006.260.08:05:10.75#ibcon#first serial, iclass 5, count 2 2006.260.08:05:10.75#ibcon#enter sib2, iclass 5, count 2 2006.260.08:05:10.75#ibcon#flushed, iclass 5, count 2 2006.260.08:05:10.75#ibcon#about to write, iclass 5, count 2 2006.260.08:05:10.75#ibcon#wrote, iclass 5, count 2 2006.260.08:05:10.75#ibcon#about to read 3, iclass 5, count 2 2006.260.08:05:10.77#ibcon#read 3, iclass 5, count 2 2006.260.08:05:10.77#ibcon#about to read 4, iclass 5, count 2 2006.260.08:05:10.77#ibcon#read 4, iclass 5, count 2 2006.260.08:05:10.77#ibcon#about to read 5, iclass 5, count 2 2006.260.08:05:10.77#ibcon#read 5, iclass 5, count 2 2006.260.08:05:10.77#ibcon#about to read 6, iclass 5, count 2 2006.260.08:05:10.77#ibcon#read 6, iclass 5, count 2 2006.260.08:05:10.77#ibcon#end of sib2, iclass 5, count 2 2006.260.08:05:10.77#ibcon#*mode == 0, iclass 5, count 2 2006.260.08:05:10.77#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.08:05:10.77#ibcon#[25=AT05-07\r\n] 2006.260.08:05:10.77#ibcon#*before write, iclass 5, count 2 2006.260.08:05:10.77#ibcon#enter sib2, iclass 5, count 2 2006.260.08:05:10.77#ibcon#flushed, iclass 5, count 2 2006.260.08:05:10.77#ibcon#about to write, iclass 5, count 2 2006.260.08:05:10.77#ibcon#wrote, iclass 5, count 2 2006.260.08:05:10.77#ibcon#about to read 3, iclass 5, count 2 2006.260.08:05:10.80#ibcon#read 3, iclass 5, count 2 2006.260.08:05:10.80#ibcon#about to read 4, iclass 5, count 2 2006.260.08:05:10.80#ibcon#read 4, iclass 5, count 2 2006.260.08:05:10.80#ibcon#about to read 5, iclass 5, count 2 2006.260.08:05:10.80#ibcon#read 5, iclass 5, count 2 2006.260.08:05:10.80#ibcon#about to read 6, iclass 5, count 2 2006.260.08:05:10.80#ibcon#read 6, iclass 5, count 2 2006.260.08:05:10.80#ibcon#end of sib2, iclass 5, count 2 2006.260.08:05:10.80#ibcon#*after write, iclass 5, count 2 2006.260.08:05:10.80#ibcon#*before return 0, iclass 5, count 2 2006.260.08:05:10.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:10.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:10.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.08:05:10.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:10.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:10.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:10.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:10.92#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:05:10.92#ibcon#first serial, iclass 5, count 0 2006.260.08:05:10.92#ibcon#enter sib2, iclass 5, count 0 2006.260.08:05:10.92#ibcon#flushed, iclass 5, count 0 2006.260.08:05:10.92#ibcon#about to write, iclass 5, count 0 2006.260.08:05:10.92#ibcon#wrote, iclass 5, count 0 2006.260.08:05:10.92#ibcon#about to read 3, iclass 5, count 0 2006.260.08:05:10.94#ibcon#read 3, iclass 5, count 0 2006.260.08:05:10.94#ibcon#about to read 4, iclass 5, count 0 2006.260.08:05:10.94#ibcon#read 4, iclass 5, count 0 2006.260.08:05:10.94#ibcon#about to read 5, iclass 5, count 0 2006.260.08:05:10.94#ibcon#read 5, iclass 5, count 0 2006.260.08:05:10.94#ibcon#about to read 6, iclass 5, count 0 2006.260.08:05:10.94#ibcon#read 6, iclass 5, count 0 2006.260.08:05:10.94#ibcon#end of sib2, iclass 5, count 0 2006.260.08:05:10.94#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:05:10.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:05:10.94#ibcon#[25=USB\r\n] 2006.260.08:05:10.94#ibcon#*before write, iclass 5, count 0 2006.260.08:05:10.94#ibcon#enter sib2, iclass 5, count 0 2006.260.08:05:10.94#ibcon#flushed, iclass 5, count 0 2006.260.08:05:10.94#ibcon#about to write, iclass 5, count 0 2006.260.08:05:10.94#ibcon#wrote, iclass 5, count 0 2006.260.08:05:10.94#ibcon#about to read 3, iclass 5, count 0 2006.260.08:05:10.97#ibcon#read 3, iclass 5, count 0 2006.260.08:05:10.97#ibcon#about to read 4, iclass 5, count 0 2006.260.08:05:10.97#ibcon#read 4, iclass 5, count 0 2006.260.08:05:10.97#ibcon#about to read 5, iclass 5, count 0 2006.260.08:05:10.97#ibcon#read 5, iclass 5, count 0 2006.260.08:05:10.97#ibcon#about to read 6, iclass 5, count 0 2006.260.08:05:10.97#ibcon#read 6, iclass 5, count 0 2006.260.08:05:10.97#ibcon#end of sib2, iclass 5, count 0 2006.260.08:05:10.97#ibcon#*after write, iclass 5, count 0 2006.260.08:05:10.97#ibcon#*before return 0, iclass 5, count 0 2006.260.08:05:10.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:10.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:10.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:05:10.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:05:10.97$vc4f8/valo=6,772.99 2006.260.08:05:10.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:05:10.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:05:10.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:10.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:10.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:10.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:10.97#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:05:10.97#ibcon#first serial, iclass 7, count 0 2006.260.08:05:10.97#ibcon#enter sib2, iclass 7, count 0 2006.260.08:05:10.97#ibcon#flushed, iclass 7, count 0 2006.260.08:05:10.97#ibcon#about to write, iclass 7, count 0 2006.260.08:05:10.97#ibcon#wrote, iclass 7, count 0 2006.260.08:05:10.97#ibcon#about to read 3, iclass 7, count 0 2006.260.08:05:11.00#ibcon#read 3, iclass 7, count 0 2006.260.08:05:11.00#ibcon#about to read 4, iclass 7, count 0 2006.260.08:05:11.00#ibcon#read 4, iclass 7, count 0 2006.260.08:05:11.00#ibcon#about to read 5, iclass 7, count 0 2006.260.08:05:11.00#ibcon#read 5, iclass 7, count 0 2006.260.08:05:11.00#ibcon#about to read 6, iclass 7, count 0 2006.260.08:05:11.00#ibcon#read 6, iclass 7, count 0 2006.260.08:05:11.00#ibcon#end of sib2, iclass 7, count 0 2006.260.08:05:11.00#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:05:11.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:05:11.00#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:05:11.00#ibcon#*before write, iclass 7, count 0 2006.260.08:05:11.00#ibcon#enter sib2, iclass 7, count 0 2006.260.08:05:11.00#ibcon#flushed, iclass 7, count 0 2006.260.08:05:11.00#ibcon#about to write, iclass 7, count 0 2006.260.08:05:11.00#ibcon#wrote, iclass 7, count 0 2006.260.08:05:11.00#ibcon#about to read 3, iclass 7, count 0 2006.260.08:05:11.04#ibcon#read 3, iclass 7, count 0 2006.260.08:05:11.04#ibcon#about to read 4, iclass 7, count 0 2006.260.08:05:11.04#ibcon#read 4, iclass 7, count 0 2006.260.08:05:11.04#ibcon#about to read 5, iclass 7, count 0 2006.260.08:05:11.04#ibcon#read 5, iclass 7, count 0 2006.260.08:05:11.04#ibcon#about to read 6, iclass 7, count 0 2006.260.08:05:11.04#ibcon#read 6, iclass 7, count 0 2006.260.08:05:11.04#ibcon#end of sib2, iclass 7, count 0 2006.260.08:05:11.04#ibcon#*after write, iclass 7, count 0 2006.260.08:05:11.04#ibcon#*before return 0, iclass 7, count 0 2006.260.08:05:11.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:11.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:11.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:05:11.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:05:11.04$vc4f8/va=6,6 2006.260.08:05:11.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:05:11.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:05:11.04#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:11.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:11.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:11.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:11.09#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:05:11.09#ibcon#first serial, iclass 11, count 2 2006.260.08:05:11.09#ibcon#enter sib2, iclass 11, count 2 2006.260.08:05:11.09#ibcon#flushed, iclass 11, count 2 2006.260.08:05:11.09#ibcon#about to write, iclass 11, count 2 2006.260.08:05:11.09#ibcon#wrote, iclass 11, count 2 2006.260.08:05:11.09#ibcon#about to read 3, iclass 11, count 2 2006.260.08:05:11.11#ibcon#read 3, iclass 11, count 2 2006.260.08:05:11.11#ibcon#about to read 4, iclass 11, count 2 2006.260.08:05:11.11#ibcon#read 4, iclass 11, count 2 2006.260.08:05:11.11#ibcon#about to read 5, iclass 11, count 2 2006.260.08:05:11.11#ibcon#read 5, iclass 11, count 2 2006.260.08:05:11.11#ibcon#about to read 6, iclass 11, count 2 2006.260.08:05:11.11#ibcon#read 6, iclass 11, count 2 2006.260.08:05:11.11#ibcon#end of sib2, iclass 11, count 2 2006.260.08:05:11.11#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:05:11.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:05:11.11#ibcon#[25=AT06-06\r\n] 2006.260.08:05:11.11#ibcon#*before write, iclass 11, count 2 2006.260.08:05:11.11#ibcon#enter sib2, iclass 11, count 2 2006.260.08:05:11.11#ibcon#flushed, iclass 11, count 2 2006.260.08:05:11.11#ibcon#about to write, iclass 11, count 2 2006.260.08:05:11.11#ibcon#wrote, iclass 11, count 2 2006.260.08:05:11.11#ibcon#about to read 3, iclass 11, count 2 2006.260.08:05:11.14#ibcon#read 3, iclass 11, count 2 2006.260.08:05:11.14#ibcon#about to read 4, iclass 11, count 2 2006.260.08:05:11.14#ibcon#read 4, iclass 11, count 2 2006.260.08:05:11.14#ibcon#about to read 5, iclass 11, count 2 2006.260.08:05:11.14#ibcon#read 5, iclass 11, count 2 2006.260.08:05:11.14#ibcon#about to read 6, iclass 11, count 2 2006.260.08:05:11.14#ibcon#read 6, iclass 11, count 2 2006.260.08:05:11.14#ibcon#end of sib2, iclass 11, count 2 2006.260.08:05:11.14#ibcon#*after write, iclass 11, count 2 2006.260.08:05:11.14#ibcon#*before return 0, iclass 11, count 2 2006.260.08:05:11.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:11.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:11.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:05:11.14#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:11.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:05:11.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:05:11.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:05:11.26#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:05:11.26#ibcon#first serial, iclass 11, count 0 2006.260.08:05:11.26#ibcon#enter sib2, iclass 11, count 0 2006.260.08:05:11.26#ibcon#flushed, iclass 11, count 0 2006.260.08:05:11.26#ibcon#about to write, iclass 11, count 0 2006.260.08:05:11.26#ibcon#wrote, iclass 11, count 0 2006.260.08:05:11.26#ibcon#about to read 3, iclass 11, count 0 2006.260.08:05:11.28#ibcon#read 3, iclass 11, count 0 2006.260.08:05:11.28#ibcon#about to read 4, iclass 11, count 0 2006.260.08:05:11.28#ibcon#read 4, iclass 11, count 0 2006.260.08:05:11.28#ibcon#about to read 5, iclass 11, count 0 2006.260.08:05:11.28#ibcon#read 5, iclass 11, count 0 2006.260.08:05:11.28#ibcon#about to read 6, iclass 11, count 0 2006.260.08:05:11.28#ibcon#read 6, iclass 11, count 0 2006.260.08:05:11.28#ibcon#end of sib2, iclass 11, count 0 2006.260.08:05:11.28#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:05:11.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:05:11.28#ibcon#[25=USB\r\n] 2006.260.08:05:11.28#ibcon#*before write, iclass 11, count 0 2006.260.08:05:11.28#ibcon#enter sib2, iclass 11, count 0 2006.260.08:05:11.28#ibcon#flushed, iclass 11, count 0 2006.260.08:05:11.28#ibcon#about to write, iclass 11, count 0 2006.260.08:05:11.28#ibcon#wrote, iclass 11, count 0 2006.260.08:05:11.28#ibcon#about to read 3, iclass 11, count 0 2006.260.08:05:11.31#ibcon#read 3, iclass 11, count 0 2006.260.08:05:11.31#ibcon#about to read 4, iclass 11, count 0 2006.260.08:05:11.31#ibcon#read 4, iclass 11, count 0 2006.260.08:05:11.31#ibcon#about to read 5, iclass 11, count 0 2006.260.08:05:11.31#ibcon#read 5, iclass 11, count 0 2006.260.08:05:11.31#ibcon#about to read 6, iclass 11, count 0 2006.260.08:05:11.31#ibcon#read 6, iclass 11, count 0 2006.260.08:05:11.31#ibcon#end of sib2, iclass 11, count 0 2006.260.08:05:11.31#ibcon#*after write, iclass 11, count 0 2006.260.08:05:11.31#ibcon#*before return 0, iclass 11, count 0 2006.260.08:05:11.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:05:11.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:05:11.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:05:11.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:05:11.31$vc4f8/valo=7,832.99 2006.260.08:05:11.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:05:11.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:05:11.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:11.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:05:11.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:05:11.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:05:11.31#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:05:11.31#ibcon#first serial, iclass 13, count 0 2006.260.08:05:11.31#ibcon#enter sib2, iclass 13, count 0 2006.260.08:05:11.31#ibcon#flushed, iclass 13, count 0 2006.260.08:05:11.31#ibcon#about to write, iclass 13, count 0 2006.260.08:05:11.31#ibcon#wrote, iclass 13, count 0 2006.260.08:05:11.31#ibcon#about to read 3, iclass 13, count 0 2006.260.08:05:11.33#ibcon#read 3, iclass 13, count 0 2006.260.08:05:11.33#ibcon#about to read 4, iclass 13, count 0 2006.260.08:05:11.33#ibcon#read 4, iclass 13, count 0 2006.260.08:05:11.33#ibcon#about to read 5, iclass 13, count 0 2006.260.08:05:11.33#ibcon#read 5, iclass 13, count 0 2006.260.08:05:11.33#ibcon#about to read 6, iclass 13, count 0 2006.260.08:05:11.33#ibcon#read 6, iclass 13, count 0 2006.260.08:05:11.33#ibcon#end of sib2, iclass 13, count 0 2006.260.08:05:11.33#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:05:11.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:05:11.33#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:05:11.33#ibcon#*before write, iclass 13, count 0 2006.260.08:05:11.33#ibcon#enter sib2, iclass 13, count 0 2006.260.08:05:11.33#ibcon#flushed, iclass 13, count 0 2006.260.08:05:11.33#ibcon#about to write, iclass 13, count 0 2006.260.08:05:11.33#ibcon#wrote, iclass 13, count 0 2006.260.08:05:11.33#ibcon#about to read 3, iclass 13, count 0 2006.260.08:05:11.37#ibcon#read 3, iclass 13, count 0 2006.260.08:05:11.37#ibcon#about to read 4, iclass 13, count 0 2006.260.08:05:11.37#ibcon#read 4, iclass 13, count 0 2006.260.08:05:11.37#ibcon#about to read 5, iclass 13, count 0 2006.260.08:05:11.37#ibcon#read 5, iclass 13, count 0 2006.260.08:05:11.37#ibcon#about to read 6, iclass 13, count 0 2006.260.08:05:11.37#ibcon#read 6, iclass 13, count 0 2006.260.08:05:11.37#ibcon#end of sib2, iclass 13, count 0 2006.260.08:05:11.37#ibcon#*after write, iclass 13, count 0 2006.260.08:05:11.37#ibcon#*before return 0, iclass 13, count 0 2006.260.08:05:11.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:05:11.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:05:11.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:05:11.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:05:11.37$vc4f8/va=7,6 2006.260.08:05:11.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:05:11.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:05:11.37#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:11.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:05:11.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:05:11.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:05:11.43#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:05:11.43#ibcon#first serial, iclass 15, count 2 2006.260.08:05:11.43#ibcon#enter sib2, iclass 15, count 2 2006.260.08:05:11.43#ibcon#flushed, iclass 15, count 2 2006.260.08:05:11.43#ibcon#about to write, iclass 15, count 2 2006.260.08:05:11.43#ibcon#wrote, iclass 15, count 2 2006.260.08:05:11.43#ibcon#about to read 3, iclass 15, count 2 2006.260.08:05:11.45#ibcon#read 3, iclass 15, count 2 2006.260.08:05:11.45#ibcon#about to read 4, iclass 15, count 2 2006.260.08:05:11.45#ibcon#read 4, iclass 15, count 2 2006.260.08:05:11.45#ibcon#about to read 5, iclass 15, count 2 2006.260.08:05:11.45#ibcon#read 5, iclass 15, count 2 2006.260.08:05:11.45#ibcon#about to read 6, iclass 15, count 2 2006.260.08:05:11.45#ibcon#read 6, iclass 15, count 2 2006.260.08:05:11.45#ibcon#end of sib2, iclass 15, count 2 2006.260.08:05:11.45#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:05:11.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:05:11.45#ibcon#[25=AT07-06\r\n] 2006.260.08:05:11.45#ibcon#*before write, iclass 15, count 2 2006.260.08:05:11.45#ibcon#enter sib2, iclass 15, count 2 2006.260.08:05:11.45#ibcon#flushed, iclass 15, count 2 2006.260.08:05:11.45#ibcon#about to write, iclass 15, count 2 2006.260.08:05:11.45#ibcon#wrote, iclass 15, count 2 2006.260.08:05:11.45#ibcon#about to read 3, iclass 15, count 2 2006.260.08:05:11.48#ibcon#read 3, iclass 15, count 2 2006.260.08:05:11.48#ibcon#about to read 4, iclass 15, count 2 2006.260.08:05:11.48#ibcon#read 4, iclass 15, count 2 2006.260.08:05:11.48#ibcon#about to read 5, iclass 15, count 2 2006.260.08:05:11.48#ibcon#read 5, iclass 15, count 2 2006.260.08:05:11.48#ibcon#about to read 6, iclass 15, count 2 2006.260.08:05:11.48#ibcon#read 6, iclass 15, count 2 2006.260.08:05:11.48#ibcon#end of sib2, iclass 15, count 2 2006.260.08:05:11.48#ibcon#*after write, iclass 15, count 2 2006.260.08:05:11.48#ibcon#*before return 0, iclass 15, count 2 2006.260.08:05:11.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:05:11.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:05:11.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:05:11.48#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:11.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:05:11.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:05:11.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:05:11.60#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:05:11.60#ibcon#first serial, iclass 15, count 0 2006.260.08:05:11.60#ibcon#enter sib2, iclass 15, count 0 2006.260.08:05:11.60#ibcon#flushed, iclass 15, count 0 2006.260.08:05:11.60#ibcon#about to write, iclass 15, count 0 2006.260.08:05:11.60#ibcon#wrote, iclass 15, count 0 2006.260.08:05:11.60#ibcon#about to read 3, iclass 15, count 0 2006.260.08:05:11.62#ibcon#read 3, iclass 15, count 0 2006.260.08:05:11.62#ibcon#about to read 4, iclass 15, count 0 2006.260.08:05:11.62#ibcon#read 4, iclass 15, count 0 2006.260.08:05:11.62#ibcon#about to read 5, iclass 15, count 0 2006.260.08:05:11.62#ibcon#read 5, iclass 15, count 0 2006.260.08:05:11.62#ibcon#about to read 6, iclass 15, count 0 2006.260.08:05:11.62#ibcon#read 6, iclass 15, count 0 2006.260.08:05:11.62#ibcon#end of sib2, iclass 15, count 0 2006.260.08:05:11.62#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:05:11.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:05:11.62#ibcon#[25=USB\r\n] 2006.260.08:05:11.62#ibcon#*before write, iclass 15, count 0 2006.260.08:05:11.62#ibcon#enter sib2, iclass 15, count 0 2006.260.08:05:11.62#ibcon#flushed, iclass 15, count 0 2006.260.08:05:11.62#ibcon#about to write, iclass 15, count 0 2006.260.08:05:11.62#ibcon#wrote, iclass 15, count 0 2006.260.08:05:11.62#ibcon#about to read 3, iclass 15, count 0 2006.260.08:05:11.65#ibcon#read 3, iclass 15, count 0 2006.260.08:05:11.65#ibcon#about to read 4, iclass 15, count 0 2006.260.08:05:11.65#ibcon#read 4, iclass 15, count 0 2006.260.08:05:11.65#ibcon#about to read 5, iclass 15, count 0 2006.260.08:05:11.65#ibcon#read 5, iclass 15, count 0 2006.260.08:05:11.65#ibcon#about to read 6, iclass 15, count 0 2006.260.08:05:11.65#ibcon#read 6, iclass 15, count 0 2006.260.08:05:11.65#ibcon#end of sib2, iclass 15, count 0 2006.260.08:05:11.65#ibcon#*after write, iclass 15, count 0 2006.260.08:05:11.65#ibcon#*before return 0, iclass 15, count 0 2006.260.08:05:11.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:05:11.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:05:11.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:05:11.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:05:11.65$vc4f8/valo=8,852.99 2006.260.08:05:11.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.08:05:11.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.08:05:11.65#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:11.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:05:11.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:05:11.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:05:11.65#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:05:11.65#ibcon#first serial, iclass 17, count 0 2006.260.08:05:11.65#ibcon#enter sib2, iclass 17, count 0 2006.260.08:05:11.65#ibcon#flushed, iclass 17, count 0 2006.260.08:05:11.65#ibcon#about to write, iclass 17, count 0 2006.260.08:05:11.65#ibcon#wrote, iclass 17, count 0 2006.260.08:05:11.65#ibcon#about to read 3, iclass 17, count 0 2006.260.08:05:11.67#ibcon#read 3, iclass 17, count 0 2006.260.08:05:11.67#ibcon#about to read 4, iclass 17, count 0 2006.260.08:05:11.67#ibcon#read 4, iclass 17, count 0 2006.260.08:05:11.67#ibcon#about to read 5, iclass 17, count 0 2006.260.08:05:11.67#ibcon#read 5, iclass 17, count 0 2006.260.08:05:11.67#ibcon#about to read 6, iclass 17, count 0 2006.260.08:05:11.67#ibcon#read 6, iclass 17, count 0 2006.260.08:05:11.67#ibcon#end of sib2, iclass 17, count 0 2006.260.08:05:11.67#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:05:11.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:05:11.67#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:05:11.67#ibcon#*before write, iclass 17, count 0 2006.260.08:05:11.67#ibcon#enter sib2, iclass 17, count 0 2006.260.08:05:11.67#ibcon#flushed, iclass 17, count 0 2006.260.08:05:11.67#ibcon#about to write, iclass 17, count 0 2006.260.08:05:11.67#ibcon#wrote, iclass 17, count 0 2006.260.08:05:11.67#ibcon#about to read 3, iclass 17, count 0 2006.260.08:05:11.71#ibcon#read 3, iclass 17, count 0 2006.260.08:05:11.71#ibcon#about to read 4, iclass 17, count 0 2006.260.08:05:11.71#ibcon#read 4, iclass 17, count 0 2006.260.08:05:11.71#ibcon#about to read 5, iclass 17, count 0 2006.260.08:05:11.71#ibcon#read 5, iclass 17, count 0 2006.260.08:05:11.71#ibcon#about to read 6, iclass 17, count 0 2006.260.08:05:11.71#ibcon#read 6, iclass 17, count 0 2006.260.08:05:11.71#ibcon#end of sib2, iclass 17, count 0 2006.260.08:05:11.71#ibcon#*after write, iclass 17, count 0 2006.260.08:05:11.71#ibcon#*before return 0, iclass 17, count 0 2006.260.08:05:11.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:05:11.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:05:11.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:05:11.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:05:11.71$vc4f8/va=8,6 2006.260.08:05:11.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.08:05:11.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.08:05:11.71#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:11.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:05:11.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:05:11.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:05:11.77#ibcon#enter wrdev, iclass 19, count 2 2006.260.08:05:11.77#ibcon#first serial, iclass 19, count 2 2006.260.08:05:11.77#ibcon#enter sib2, iclass 19, count 2 2006.260.08:05:11.77#ibcon#flushed, iclass 19, count 2 2006.260.08:05:11.77#ibcon#about to write, iclass 19, count 2 2006.260.08:05:11.77#ibcon#wrote, iclass 19, count 2 2006.260.08:05:11.77#ibcon#about to read 3, iclass 19, count 2 2006.260.08:05:11.79#ibcon#read 3, iclass 19, count 2 2006.260.08:05:11.79#ibcon#about to read 4, iclass 19, count 2 2006.260.08:05:11.79#ibcon#read 4, iclass 19, count 2 2006.260.08:05:11.79#ibcon#about to read 5, iclass 19, count 2 2006.260.08:05:11.79#ibcon#read 5, iclass 19, count 2 2006.260.08:05:11.79#ibcon#about to read 6, iclass 19, count 2 2006.260.08:05:11.79#ibcon#read 6, iclass 19, count 2 2006.260.08:05:11.79#ibcon#end of sib2, iclass 19, count 2 2006.260.08:05:11.79#ibcon#*mode == 0, iclass 19, count 2 2006.260.08:05:11.79#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.08:05:11.79#ibcon#[25=AT08-06\r\n] 2006.260.08:05:11.79#ibcon#*before write, iclass 19, count 2 2006.260.08:05:11.79#ibcon#enter sib2, iclass 19, count 2 2006.260.08:05:11.79#ibcon#flushed, iclass 19, count 2 2006.260.08:05:11.79#ibcon#about to write, iclass 19, count 2 2006.260.08:05:11.79#ibcon#wrote, iclass 19, count 2 2006.260.08:05:11.79#ibcon#about to read 3, iclass 19, count 2 2006.260.08:05:11.82#ibcon#read 3, iclass 19, count 2 2006.260.08:05:11.82#ibcon#about to read 4, iclass 19, count 2 2006.260.08:05:11.82#ibcon#read 4, iclass 19, count 2 2006.260.08:05:11.82#ibcon#about to read 5, iclass 19, count 2 2006.260.08:05:11.82#ibcon#read 5, iclass 19, count 2 2006.260.08:05:11.82#ibcon#about to read 6, iclass 19, count 2 2006.260.08:05:11.82#ibcon#read 6, iclass 19, count 2 2006.260.08:05:11.82#ibcon#end of sib2, iclass 19, count 2 2006.260.08:05:11.82#ibcon#*after write, iclass 19, count 2 2006.260.08:05:11.82#ibcon#*before return 0, iclass 19, count 2 2006.260.08:05:11.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:05:11.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:05:11.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.08:05:11.82#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:11.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:05:11.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:05:11.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:05:11.94#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:05:11.94#ibcon#first serial, iclass 19, count 0 2006.260.08:05:11.94#ibcon#enter sib2, iclass 19, count 0 2006.260.08:05:11.94#ibcon#flushed, iclass 19, count 0 2006.260.08:05:11.94#ibcon#about to write, iclass 19, count 0 2006.260.08:05:11.94#ibcon#wrote, iclass 19, count 0 2006.260.08:05:11.94#ibcon#about to read 3, iclass 19, count 0 2006.260.08:05:11.96#ibcon#read 3, iclass 19, count 0 2006.260.08:05:11.96#ibcon#about to read 4, iclass 19, count 0 2006.260.08:05:11.96#ibcon#read 4, iclass 19, count 0 2006.260.08:05:11.96#ibcon#about to read 5, iclass 19, count 0 2006.260.08:05:11.96#ibcon#read 5, iclass 19, count 0 2006.260.08:05:11.96#ibcon#about to read 6, iclass 19, count 0 2006.260.08:05:11.96#ibcon#read 6, iclass 19, count 0 2006.260.08:05:11.96#ibcon#end of sib2, iclass 19, count 0 2006.260.08:05:11.96#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:05:11.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:05:11.96#ibcon#[25=USB\r\n] 2006.260.08:05:11.96#ibcon#*before write, iclass 19, count 0 2006.260.08:05:11.96#ibcon#enter sib2, iclass 19, count 0 2006.260.08:05:11.96#ibcon#flushed, iclass 19, count 0 2006.260.08:05:11.96#ibcon#about to write, iclass 19, count 0 2006.260.08:05:11.96#ibcon#wrote, iclass 19, count 0 2006.260.08:05:11.96#ibcon#about to read 3, iclass 19, count 0 2006.260.08:05:11.99#ibcon#read 3, iclass 19, count 0 2006.260.08:05:11.99#ibcon#about to read 4, iclass 19, count 0 2006.260.08:05:11.99#ibcon#read 4, iclass 19, count 0 2006.260.08:05:11.99#ibcon#about to read 5, iclass 19, count 0 2006.260.08:05:11.99#ibcon#read 5, iclass 19, count 0 2006.260.08:05:11.99#ibcon#about to read 6, iclass 19, count 0 2006.260.08:05:11.99#ibcon#read 6, iclass 19, count 0 2006.260.08:05:11.99#ibcon#end of sib2, iclass 19, count 0 2006.260.08:05:11.99#ibcon#*after write, iclass 19, count 0 2006.260.08:05:11.99#ibcon#*before return 0, iclass 19, count 0 2006.260.08:05:11.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:05:11.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:05:11.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:05:11.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:05:11.99$vc4f8/vblo=1,632.99 2006.260.08:05:11.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:05:11.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:05:11.99#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:11.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:05:11.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:05:11.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:05:11.99#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:05:11.99#ibcon#first serial, iclass 21, count 0 2006.260.08:05:11.99#ibcon#enter sib2, iclass 21, count 0 2006.260.08:05:11.99#ibcon#flushed, iclass 21, count 0 2006.260.08:05:11.99#ibcon#about to write, iclass 21, count 0 2006.260.08:05:11.99#ibcon#wrote, iclass 21, count 0 2006.260.08:05:11.99#ibcon#about to read 3, iclass 21, count 0 2006.260.08:05:12.01#ibcon#read 3, iclass 21, count 0 2006.260.08:05:12.01#ibcon#about to read 4, iclass 21, count 0 2006.260.08:05:12.01#ibcon#read 4, iclass 21, count 0 2006.260.08:05:12.01#ibcon#about to read 5, iclass 21, count 0 2006.260.08:05:12.01#ibcon#read 5, iclass 21, count 0 2006.260.08:05:12.01#ibcon#about to read 6, iclass 21, count 0 2006.260.08:05:12.01#ibcon#read 6, iclass 21, count 0 2006.260.08:05:12.01#ibcon#end of sib2, iclass 21, count 0 2006.260.08:05:12.01#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:05:12.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:05:12.01#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:05:12.01#ibcon#*before write, iclass 21, count 0 2006.260.08:05:12.01#ibcon#enter sib2, iclass 21, count 0 2006.260.08:05:12.01#ibcon#flushed, iclass 21, count 0 2006.260.08:05:12.01#ibcon#about to write, iclass 21, count 0 2006.260.08:05:12.01#ibcon#wrote, iclass 21, count 0 2006.260.08:05:12.01#ibcon#about to read 3, iclass 21, count 0 2006.260.08:05:12.05#ibcon#read 3, iclass 21, count 0 2006.260.08:05:12.05#ibcon#about to read 4, iclass 21, count 0 2006.260.08:05:12.05#ibcon#read 4, iclass 21, count 0 2006.260.08:05:12.05#ibcon#about to read 5, iclass 21, count 0 2006.260.08:05:12.05#ibcon#read 5, iclass 21, count 0 2006.260.08:05:12.05#ibcon#about to read 6, iclass 21, count 0 2006.260.08:05:12.05#ibcon#read 6, iclass 21, count 0 2006.260.08:05:12.05#ibcon#end of sib2, iclass 21, count 0 2006.260.08:05:12.05#ibcon#*after write, iclass 21, count 0 2006.260.08:05:12.05#ibcon#*before return 0, iclass 21, count 0 2006.260.08:05:12.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:05:12.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:05:12.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:05:12.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:05:12.05$vc4f8/vb=1,4 2006.260.08:05:12.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:05:12.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:05:12.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:12.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:05:12.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:05:12.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:05:12.05#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:05:12.05#ibcon#first serial, iclass 23, count 2 2006.260.08:05:12.05#ibcon#enter sib2, iclass 23, count 2 2006.260.08:05:12.05#ibcon#flushed, iclass 23, count 2 2006.260.08:05:12.05#ibcon#about to write, iclass 23, count 2 2006.260.08:05:12.05#ibcon#wrote, iclass 23, count 2 2006.260.08:05:12.05#ibcon#about to read 3, iclass 23, count 2 2006.260.08:05:12.07#ibcon#read 3, iclass 23, count 2 2006.260.08:05:12.07#ibcon#about to read 4, iclass 23, count 2 2006.260.08:05:12.07#ibcon#read 4, iclass 23, count 2 2006.260.08:05:12.07#ibcon#about to read 5, iclass 23, count 2 2006.260.08:05:12.07#ibcon#read 5, iclass 23, count 2 2006.260.08:05:12.07#ibcon#about to read 6, iclass 23, count 2 2006.260.08:05:12.07#ibcon#read 6, iclass 23, count 2 2006.260.08:05:12.07#ibcon#end of sib2, iclass 23, count 2 2006.260.08:05:12.07#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:05:12.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:05:12.07#ibcon#[27=AT01-04\r\n] 2006.260.08:05:12.07#ibcon#*before write, iclass 23, count 2 2006.260.08:05:12.07#ibcon#enter sib2, iclass 23, count 2 2006.260.08:05:12.07#ibcon#flushed, iclass 23, count 2 2006.260.08:05:12.07#ibcon#about to write, iclass 23, count 2 2006.260.08:05:12.07#ibcon#wrote, iclass 23, count 2 2006.260.08:05:12.07#ibcon#about to read 3, iclass 23, count 2 2006.260.08:05:12.10#ibcon#read 3, iclass 23, count 2 2006.260.08:05:12.10#ibcon#about to read 4, iclass 23, count 2 2006.260.08:05:12.10#ibcon#read 4, iclass 23, count 2 2006.260.08:05:12.10#ibcon#about to read 5, iclass 23, count 2 2006.260.08:05:12.10#ibcon#read 5, iclass 23, count 2 2006.260.08:05:12.10#ibcon#about to read 6, iclass 23, count 2 2006.260.08:05:12.10#ibcon#read 6, iclass 23, count 2 2006.260.08:05:12.10#ibcon#end of sib2, iclass 23, count 2 2006.260.08:05:12.10#ibcon#*after write, iclass 23, count 2 2006.260.08:05:12.10#ibcon#*before return 0, iclass 23, count 2 2006.260.08:05:12.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:05:12.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:05:12.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:05:12.10#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:12.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:05:12.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:05:12.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:05:12.22#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:05:12.22#ibcon#first serial, iclass 23, count 0 2006.260.08:05:12.22#ibcon#enter sib2, iclass 23, count 0 2006.260.08:05:12.22#ibcon#flushed, iclass 23, count 0 2006.260.08:05:12.22#ibcon#about to write, iclass 23, count 0 2006.260.08:05:12.22#ibcon#wrote, iclass 23, count 0 2006.260.08:05:12.22#ibcon#about to read 3, iclass 23, count 0 2006.260.08:05:12.24#ibcon#read 3, iclass 23, count 0 2006.260.08:05:12.24#ibcon#about to read 4, iclass 23, count 0 2006.260.08:05:12.24#ibcon#read 4, iclass 23, count 0 2006.260.08:05:12.24#ibcon#about to read 5, iclass 23, count 0 2006.260.08:05:12.24#ibcon#read 5, iclass 23, count 0 2006.260.08:05:12.24#ibcon#about to read 6, iclass 23, count 0 2006.260.08:05:12.24#ibcon#read 6, iclass 23, count 0 2006.260.08:05:12.24#ibcon#end of sib2, iclass 23, count 0 2006.260.08:05:12.24#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:05:12.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:05:12.24#ibcon#[27=USB\r\n] 2006.260.08:05:12.24#ibcon#*before write, iclass 23, count 0 2006.260.08:05:12.24#ibcon#enter sib2, iclass 23, count 0 2006.260.08:05:12.24#ibcon#flushed, iclass 23, count 0 2006.260.08:05:12.24#ibcon#about to write, iclass 23, count 0 2006.260.08:05:12.24#ibcon#wrote, iclass 23, count 0 2006.260.08:05:12.24#ibcon#about to read 3, iclass 23, count 0 2006.260.08:05:12.27#ibcon#read 3, iclass 23, count 0 2006.260.08:05:12.27#ibcon#about to read 4, iclass 23, count 0 2006.260.08:05:12.27#ibcon#read 4, iclass 23, count 0 2006.260.08:05:12.27#ibcon#about to read 5, iclass 23, count 0 2006.260.08:05:12.27#ibcon#read 5, iclass 23, count 0 2006.260.08:05:12.27#ibcon#about to read 6, iclass 23, count 0 2006.260.08:05:12.27#ibcon#read 6, iclass 23, count 0 2006.260.08:05:12.27#ibcon#end of sib2, iclass 23, count 0 2006.260.08:05:12.27#ibcon#*after write, iclass 23, count 0 2006.260.08:05:12.27#ibcon#*before return 0, iclass 23, count 0 2006.260.08:05:12.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:05:12.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:05:12.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:05:12.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:05:12.27$vc4f8/vblo=2,640.99 2006.260.08:05:12.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:05:12.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:05:12.27#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:12.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:12.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:12.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:12.27#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:05:12.27#ibcon#first serial, iclass 25, count 0 2006.260.08:05:12.27#ibcon#enter sib2, iclass 25, count 0 2006.260.08:05:12.27#ibcon#flushed, iclass 25, count 0 2006.260.08:05:12.27#ibcon#about to write, iclass 25, count 0 2006.260.08:05:12.27#ibcon#wrote, iclass 25, count 0 2006.260.08:05:12.27#ibcon#about to read 3, iclass 25, count 0 2006.260.08:05:12.29#ibcon#read 3, iclass 25, count 0 2006.260.08:05:12.29#ibcon#about to read 4, iclass 25, count 0 2006.260.08:05:12.29#ibcon#read 4, iclass 25, count 0 2006.260.08:05:12.29#ibcon#about to read 5, iclass 25, count 0 2006.260.08:05:12.29#ibcon#read 5, iclass 25, count 0 2006.260.08:05:12.29#ibcon#about to read 6, iclass 25, count 0 2006.260.08:05:12.29#ibcon#read 6, iclass 25, count 0 2006.260.08:05:12.29#ibcon#end of sib2, iclass 25, count 0 2006.260.08:05:12.29#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:05:12.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:05:12.29#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:05:12.29#ibcon#*before write, iclass 25, count 0 2006.260.08:05:12.29#ibcon#enter sib2, iclass 25, count 0 2006.260.08:05:12.29#ibcon#flushed, iclass 25, count 0 2006.260.08:05:12.29#ibcon#about to write, iclass 25, count 0 2006.260.08:05:12.29#ibcon#wrote, iclass 25, count 0 2006.260.08:05:12.29#ibcon#about to read 3, iclass 25, count 0 2006.260.08:05:12.33#ibcon#read 3, iclass 25, count 0 2006.260.08:05:12.33#ibcon#about to read 4, iclass 25, count 0 2006.260.08:05:12.33#ibcon#read 4, iclass 25, count 0 2006.260.08:05:12.33#ibcon#about to read 5, iclass 25, count 0 2006.260.08:05:12.33#ibcon#read 5, iclass 25, count 0 2006.260.08:05:12.33#ibcon#about to read 6, iclass 25, count 0 2006.260.08:05:12.33#ibcon#read 6, iclass 25, count 0 2006.260.08:05:12.33#ibcon#end of sib2, iclass 25, count 0 2006.260.08:05:12.33#ibcon#*after write, iclass 25, count 0 2006.260.08:05:12.33#ibcon#*before return 0, iclass 25, count 0 2006.260.08:05:12.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:12.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:05:12.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:05:12.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:05:12.33$vc4f8/vb=2,5 2006.260.08:05:12.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:05:12.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:05:12.33#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:12.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:12.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:12.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:12.39#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:05:12.39#ibcon#first serial, iclass 27, count 2 2006.260.08:05:12.39#ibcon#enter sib2, iclass 27, count 2 2006.260.08:05:12.39#ibcon#flushed, iclass 27, count 2 2006.260.08:05:12.39#ibcon#about to write, iclass 27, count 2 2006.260.08:05:12.39#ibcon#wrote, iclass 27, count 2 2006.260.08:05:12.39#ibcon#about to read 3, iclass 27, count 2 2006.260.08:05:12.41#ibcon#read 3, iclass 27, count 2 2006.260.08:05:12.41#ibcon#about to read 4, iclass 27, count 2 2006.260.08:05:12.41#ibcon#read 4, iclass 27, count 2 2006.260.08:05:12.41#ibcon#about to read 5, iclass 27, count 2 2006.260.08:05:12.41#ibcon#read 5, iclass 27, count 2 2006.260.08:05:12.41#ibcon#about to read 6, iclass 27, count 2 2006.260.08:05:12.41#ibcon#read 6, iclass 27, count 2 2006.260.08:05:12.41#ibcon#end of sib2, iclass 27, count 2 2006.260.08:05:12.41#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:05:12.41#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:05:12.41#ibcon#[27=AT02-05\r\n] 2006.260.08:05:12.41#ibcon#*before write, iclass 27, count 2 2006.260.08:05:12.41#ibcon#enter sib2, iclass 27, count 2 2006.260.08:05:12.41#ibcon#flushed, iclass 27, count 2 2006.260.08:05:12.41#ibcon#about to write, iclass 27, count 2 2006.260.08:05:12.41#ibcon#wrote, iclass 27, count 2 2006.260.08:05:12.41#ibcon#about to read 3, iclass 27, count 2 2006.260.08:05:12.44#ibcon#read 3, iclass 27, count 2 2006.260.08:05:12.44#ibcon#about to read 4, iclass 27, count 2 2006.260.08:05:12.44#ibcon#read 4, iclass 27, count 2 2006.260.08:05:12.44#ibcon#about to read 5, iclass 27, count 2 2006.260.08:05:12.44#ibcon#read 5, iclass 27, count 2 2006.260.08:05:12.44#ibcon#about to read 6, iclass 27, count 2 2006.260.08:05:12.44#ibcon#read 6, iclass 27, count 2 2006.260.08:05:12.44#ibcon#end of sib2, iclass 27, count 2 2006.260.08:05:12.44#ibcon#*after write, iclass 27, count 2 2006.260.08:05:12.44#ibcon#*before return 0, iclass 27, count 2 2006.260.08:05:12.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:12.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:05:12.44#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:05:12.44#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:12.44#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:12.56#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:12.56#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:12.56#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:05:12.56#ibcon#first serial, iclass 27, count 0 2006.260.08:05:12.56#ibcon#enter sib2, iclass 27, count 0 2006.260.08:05:12.56#ibcon#flushed, iclass 27, count 0 2006.260.08:05:12.56#ibcon#about to write, iclass 27, count 0 2006.260.08:05:12.56#ibcon#wrote, iclass 27, count 0 2006.260.08:05:12.56#ibcon#about to read 3, iclass 27, count 0 2006.260.08:05:12.58#ibcon#read 3, iclass 27, count 0 2006.260.08:05:12.58#ibcon#about to read 4, iclass 27, count 0 2006.260.08:05:12.58#ibcon#read 4, iclass 27, count 0 2006.260.08:05:12.58#ibcon#about to read 5, iclass 27, count 0 2006.260.08:05:12.58#ibcon#read 5, iclass 27, count 0 2006.260.08:05:12.58#ibcon#about to read 6, iclass 27, count 0 2006.260.08:05:12.58#ibcon#read 6, iclass 27, count 0 2006.260.08:05:12.58#ibcon#end of sib2, iclass 27, count 0 2006.260.08:05:12.58#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:05:12.58#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:05:12.58#ibcon#[27=USB\r\n] 2006.260.08:05:12.58#ibcon#*before write, iclass 27, count 0 2006.260.08:05:12.58#ibcon#enter sib2, iclass 27, count 0 2006.260.08:05:12.58#ibcon#flushed, iclass 27, count 0 2006.260.08:05:12.58#ibcon#about to write, iclass 27, count 0 2006.260.08:05:12.58#ibcon#wrote, iclass 27, count 0 2006.260.08:05:12.58#ibcon#about to read 3, iclass 27, count 0 2006.260.08:05:12.61#ibcon#read 3, iclass 27, count 0 2006.260.08:05:12.61#ibcon#about to read 4, iclass 27, count 0 2006.260.08:05:12.61#ibcon#read 4, iclass 27, count 0 2006.260.08:05:12.61#ibcon#about to read 5, iclass 27, count 0 2006.260.08:05:12.61#ibcon#read 5, iclass 27, count 0 2006.260.08:05:12.61#ibcon#about to read 6, iclass 27, count 0 2006.260.08:05:12.61#ibcon#read 6, iclass 27, count 0 2006.260.08:05:12.61#ibcon#end of sib2, iclass 27, count 0 2006.260.08:05:12.61#ibcon#*after write, iclass 27, count 0 2006.260.08:05:12.61#ibcon#*before return 0, iclass 27, count 0 2006.260.08:05:12.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:12.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:05:12.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:05:12.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:05:12.61$vc4f8/vblo=3,656.99 2006.260.08:05:12.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:05:12.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:05:12.61#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:12.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:12.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:12.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:12.61#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:05:12.61#ibcon#first serial, iclass 29, count 0 2006.260.08:05:12.61#ibcon#enter sib2, iclass 29, count 0 2006.260.08:05:12.61#ibcon#flushed, iclass 29, count 0 2006.260.08:05:12.61#ibcon#about to write, iclass 29, count 0 2006.260.08:05:12.61#ibcon#wrote, iclass 29, count 0 2006.260.08:05:12.61#ibcon#about to read 3, iclass 29, count 0 2006.260.08:05:12.64#ibcon#read 3, iclass 29, count 0 2006.260.08:05:12.64#ibcon#about to read 4, iclass 29, count 0 2006.260.08:05:12.64#ibcon#read 4, iclass 29, count 0 2006.260.08:05:12.64#ibcon#about to read 5, iclass 29, count 0 2006.260.08:05:12.64#ibcon#read 5, iclass 29, count 0 2006.260.08:05:12.64#ibcon#about to read 6, iclass 29, count 0 2006.260.08:05:12.64#ibcon#read 6, iclass 29, count 0 2006.260.08:05:12.64#ibcon#end of sib2, iclass 29, count 0 2006.260.08:05:12.64#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:05:12.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:05:12.64#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:05:12.64#ibcon#*before write, iclass 29, count 0 2006.260.08:05:12.64#ibcon#enter sib2, iclass 29, count 0 2006.260.08:05:12.64#ibcon#flushed, iclass 29, count 0 2006.260.08:05:12.64#ibcon#about to write, iclass 29, count 0 2006.260.08:05:12.64#ibcon#wrote, iclass 29, count 0 2006.260.08:05:12.64#ibcon#about to read 3, iclass 29, count 0 2006.260.08:05:12.68#ibcon#read 3, iclass 29, count 0 2006.260.08:05:12.68#ibcon#about to read 4, iclass 29, count 0 2006.260.08:05:12.68#ibcon#read 4, iclass 29, count 0 2006.260.08:05:12.68#ibcon#about to read 5, iclass 29, count 0 2006.260.08:05:12.68#ibcon#read 5, iclass 29, count 0 2006.260.08:05:12.68#ibcon#about to read 6, iclass 29, count 0 2006.260.08:05:12.68#ibcon#read 6, iclass 29, count 0 2006.260.08:05:12.68#ibcon#end of sib2, iclass 29, count 0 2006.260.08:05:12.68#ibcon#*after write, iclass 29, count 0 2006.260.08:05:12.68#ibcon#*before return 0, iclass 29, count 0 2006.260.08:05:12.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:12.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:05:12.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:05:12.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:05:12.68$vc4f8/vb=3,4 2006.260.08:05:12.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:05:12.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:05:12.68#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:12.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:12.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:12.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:12.73#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:05:12.73#ibcon#first serial, iclass 31, count 2 2006.260.08:05:12.73#ibcon#enter sib2, iclass 31, count 2 2006.260.08:05:12.73#ibcon#flushed, iclass 31, count 2 2006.260.08:05:12.73#ibcon#about to write, iclass 31, count 2 2006.260.08:05:12.73#ibcon#wrote, iclass 31, count 2 2006.260.08:05:12.73#ibcon#about to read 3, iclass 31, count 2 2006.260.08:05:12.75#ibcon#read 3, iclass 31, count 2 2006.260.08:05:12.75#ibcon#about to read 4, iclass 31, count 2 2006.260.08:05:12.75#ibcon#read 4, iclass 31, count 2 2006.260.08:05:12.75#ibcon#about to read 5, iclass 31, count 2 2006.260.08:05:12.75#ibcon#read 5, iclass 31, count 2 2006.260.08:05:12.75#ibcon#about to read 6, iclass 31, count 2 2006.260.08:05:12.75#ibcon#read 6, iclass 31, count 2 2006.260.08:05:12.75#ibcon#end of sib2, iclass 31, count 2 2006.260.08:05:12.75#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:05:12.75#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:05:12.75#ibcon#[27=AT03-04\r\n] 2006.260.08:05:12.75#ibcon#*before write, iclass 31, count 2 2006.260.08:05:12.75#ibcon#enter sib2, iclass 31, count 2 2006.260.08:05:12.75#ibcon#flushed, iclass 31, count 2 2006.260.08:05:12.75#ibcon#about to write, iclass 31, count 2 2006.260.08:05:12.75#ibcon#wrote, iclass 31, count 2 2006.260.08:05:12.75#ibcon#about to read 3, iclass 31, count 2 2006.260.08:05:12.78#ibcon#read 3, iclass 31, count 2 2006.260.08:05:12.78#ibcon#about to read 4, iclass 31, count 2 2006.260.08:05:12.78#ibcon#read 4, iclass 31, count 2 2006.260.08:05:12.78#ibcon#about to read 5, iclass 31, count 2 2006.260.08:05:12.78#ibcon#read 5, iclass 31, count 2 2006.260.08:05:12.78#ibcon#about to read 6, iclass 31, count 2 2006.260.08:05:12.78#ibcon#read 6, iclass 31, count 2 2006.260.08:05:12.78#ibcon#end of sib2, iclass 31, count 2 2006.260.08:05:12.78#ibcon#*after write, iclass 31, count 2 2006.260.08:05:12.78#ibcon#*before return 0, iclass 31, count 2 2006.260.08:05:12.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:12.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:05:12.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:05:12.78#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:12.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:12.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:12.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:12.90#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:05:12.90#ibcon#first serial, iclass 31, count 0 2006.260.08:05:12.90#ibcon#enter sib2, iclass 31, count 0 2006.260.08:05:12.90#ibcon#flushed, iclass 31, count 0 2006.260.08:05:12.90#ibcon#about to write, iclass 31, count 0 2006.260.08:05:12.90#ibcon#wrote, iclass 31, count 0 2006.260.08:05:12.90#ibcon#about to read 3, iclass 31, count 0 2006.260.08:05:12.92#ibcon#read 3, iclass 31, count 0 2006.260.08:05:12.92#ibcon#about to read 4, iclass 31, count 0 2006.260.08:05:12.92#ibcon#read 4, iclass 31, count 0 2006.260.08:05:12.92#ibcon#about to read 5, iclass 31, count 0 2006.260.08:05:12.92#ibcon#read 5, iclass 31, count 0 2006.260.08:05:12.92#ibcon#about to read 6, iclass 31, count 0 2006.260.08:05:12.92#ibcon#read 6, iclass 31, count 0 2006.260.08:05:12.92#ibcon#end of sib2, iclass 31, count 0 2006.260.08:05:12.92#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:05:12.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:05:12.92#ibcon#[27=USB\r\n] 2006.260.08:05:12.92#ibcon#*before write, iclass 31, count 0 2006.260.08:05:12.92#ibcon#enter sib2, iclass 31, count 0 2006.260.08:05:12.92#ibcon#flushed, iclass 31, count 0 2006.260.08:05:12.92#ibcon#about to write, iclass 31, count 0 2006.260.08:05:12.92#ibcon#wrote, iclass 31, count 0 2006.260.08:05:12.92#ibcon#about to read 3, iclass 31, count 0 2006.260.08:05:12.95#ibcon#read 3, iclass 31, count 0 2006.260.08:05:12.95#ibcon#about to read 4, iclass 31, count 0 2006.260.08:05:12.95#ibcon#read 4, iclass 31, count 0 2006.260.08:05:12.95#ibcon#about to read 5, iclass 31, count 0 2006.260.08:05:12.95#ibcon#read 5, iclass 31, count 0 2006.260.08:05:12.95#ibcon#about to read 6, iclass 31, count 0 2006.260.08:05:12.95#ibcon#read 6, iclass 31, count 0 2006.260.08:05:12.95#ibcon#end of sib2, iclass 31, count 0 2006.260.08:05:12.95#ibcon#*after write, iclass 31, count 0 2006.260.08:05:12.95#ibcon#*before return 0, iclass 31, count 0 2006.260.08:05:12.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:12.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:05:12.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:05:12.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:05:12.95$vc4f8/vblo=4,712.99 2006.260.08:05:12.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:05:12.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:05:12.95#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:12.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:12.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:12.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:12.95#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:05:12.95#ibcon#first serial, iclass 33, count 0 2006.260.08:05:12.95#ibcon#enter sib2, iclass 33, count 0 2006.260.08:05:12.95#ibcon#flushed, iclass 33, count 0 2006.260.08:05:12.95#ibcon#about to write, iclass 33, count 0 2006.260.08:05:12.95#ibcon#wrote, iclass 33, count 0 2006.260.08:05:12.95#ibcon#about to read 3, iclass 33, count 0 2006.260.08:05:12.97#ibcon#read 3, iclass 33, count 0 2006.260.08:05:12.97#ibcon#about to read 4, iclass 33, count 0 2006.260.08:05:12.97#ibcon#read 4, iclass 33, count 0 2006.260.08:05:12.97#ibcon#about to read 5, iclass 33, count 0 2006.260.08:05:12.97#ibcon#read 5, iclass 33, count 0 2006.260.08:05:12.97#ibcon#about to read 6, iclass 33, count 0 2006.260.08:05:12.97#ibcon#read 6, iclass 33, count 0 2006.260.08:05:12.97#ibcon#end of sib2, iclass 33, count 0 2006.260.08:05:12.97#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:05:12.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:05:12.97#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:05:12.97#ibcon#*before write, iclass 33, count 0 2006.260.08:05:12.97#ibcon#enter sib2, iclass 33, count 0 2006.260.08:05:12.97#ibcon#flushed, iclass 33, count 0 2006.260.08:05:12.97#ibcon#about to write, iclass 33, count 0 2006.260.08:05:12.97#ibcon#wrote, iclass 33, count 0 2006.260.08:05:12.97#ibcon#about to read 3, iclass 33, count 0 2006.260.08:05:13.01#ibcon#read 3, iclass 33, count 0 2006.260.08:05:13.01#ibcon#about to read 4, iclass 33, count 0 2006.260.08:05:13.01#ibcon#read 4, iclass 33, count 0 2006.260.08:05:13.01#ibcon#about to read 5, iclass 33, count 0 2006.260.08:05:13.01#ibcon#read 5, iclass 33, count 0 2006.260.08:05:13.01#ibcon#about to read 6, iclass 33, count 0 2006.260.08:05:13.01#ibcon#read 6, iclass 33, count 0 2006.260.08:05:13.01#ibcon#end of sib2, iclass 33, count 0 2006.260.08:05:13.01#ibcon#*after write, iclass 33, count 0 2006.260.08:05:13.01#ibcon#*before return 0, iclass 33, count 0 2006.260.08:05:13.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:13.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:05:13.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:05:13.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:05:13.01$vc4f8/vb=4,5 2006.260.08:05:13.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:05:13.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:05:13.01#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:13.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:13.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:13.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:13.07#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:05:13.07#ibcon#first serial, iclass 35, count 2 2006.260.08:05:13.07#ibcon#enter sib2, iclass 35, count 2 2006.260.08:05:13.07#ibcon#flushed, iclass 35, count 2 2006.260.08:05:13.07#ibcon#about to write, iclass 35, count 2 2006.260.08:05:13.07#ibcon#wrote, iclass 35, count 2 2006.260.08:05:13.07#ibcon#about to read 3, iclass 35, count 2 2006.260.08:05:13.09#ibcon#read 3, iclass 35, count 2 2006.260.08:05:13.09#ibcon#about to read 4, iclass 35, count 2 2006.260.08:05:13.09#ibcon#read 4, iclass 35, count 2 2006.260.08:05:13.09#ibcon#about to read 5, iclass 35, count 2 2006.260.08:05:13.09#ibcon#read 5, iclass 35, count 2 2006.260.08:05:13.09#ibcon#about to read 6, iclass 35, count 2 2006.260.08:05:13.09#ibcon#read 6, iclass 35, count 2 2006.260.08:05:13.09#ibcon#end of sib2, iclass 35, count 2 2006.260.08:05:13.09#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:05:13.09#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:05:13.09#ibcon#[27=AT04-05\r\n] 2006.260.08:05:13.09#ibcon#*before write, iclass 35, count 2 2006.260.08:05:13.09#ibcon#enter sib2, iclass 35, count 2 2006.260.08:05:13.09#ibcon#flushed, iclass 35, count 2 2006.260.08:05:13.09#ibcon#about to write, iclass 35, count 2 2006.260.08:05:13.09#ibcon#wrote, iclass 35, count 2 2006.260.08:05:13.09#ibcon#about to read 3, iclass 35, count 2 2006.260.08:05:13.12#ibcon#read 3, iclass 35, count 2 2006.260.08:05:13.12#ibcon#about to read 4, iclass 35, count 2 2006.260.08:05:13.12#ibcon#read 4, iclass 35, count 2 2006.260.08:05:13.12#ibcon#about to read 5, iclass 35, count 2 2006.260.08:05:13.12#ibcon#read 5, iclass 35, count 2 2006.260.08:05:13.12#ibcon#about to read 6, iclass 35, count 2 2006.260.08:05:13.12#ibcon#read 6, iclass 35, count 2 2006.260.08:05:13.12#ibcon#end of sib2, iclass 35, count 2 2006.260.08:05:13.12#ibcon#*after write, iclass 35, count 2 2006.260.08:05:13.12#ibcon#*before return 0, iclass 35, count 2 2006.260.08:05:13.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:13.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:05:13.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:05:13.12#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:13.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:13.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:13.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:13.24#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:05:13.24#ibcon#first serial, iclass 35, count 0 2006.260.08:05:13.24#ibcon#enter sib2, iclass 35, count 0 2006.260.08:05:13.24#ibcon#flushed, iclass 35, count 0 2006.260.08:05:13.24#ibcon#about to write, iclass 35, count 0 2006.260.08:05:13.24#ibcon#wrote, iclass 35, count 0 2006.260.08:05:13.24#ibcon#about to read 3, iclass 35, count 0 2006.260.08:05:13.26#ibcon#read 3, iclass 35, count 0 2006.260.08:05:13.26#ibcon#about to read 4, iclass 35, count 0 2006.260.08:05:13.26#ibcon#read 4, iclass 35, count 0 2006.260.08:05:13.26#ibcon#about to read 5, iclass 35, count 0 2006.260.08:05:13.26#ibcon#read 5, iclass 35, count 0 2006.260.08:05:13.26#ibcon#about to read 6, iclass 35, count 0 2006.260.08:05:13.26#ibcon#read 6, iclass 35, count 0 2006.260.08:05:13.26#ibcon#end of sib2, iclass 35, count 0 2006.260.08:05:13.26#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:05:13.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:05:13.26#ibcon#[27=USB\r\n] 2006.260.08:05:13.26#ibcon#*before write, iclass 35, count 0 2006.260.08:05:13.26#ibcon#enter sib2, iclass 35, count 0 2006.260.08:05:13.26#ibcon#flushed, iclass 35, count 0 2006.260.08:05:13.26#ibcon#about to write, iclass 35, count 0 2006.260.08:05:13.26#ibcon#wrote, iclass 35, count 0 2006.260.08:05:13.26#ibcon#about to read 3, iclass 35, count 0 2006.260.08:05:13.29#ibcon#read 3, iclass 35, count 0 2006.260.08:05:13.29#ibcon#about to read 4, iclass 35, count 0 2006.260.08:05:13.29#ibcon#read 4, iclass 35, count 0 2006.260.08:05:13.29#ibcon#about to read 5, iclass 35, count 0 2006.260.08:05:13.29#ibcon#read 5, iclass 35, count 0 2006.260.08:05:13.29#ibcon#about to read 6, iclass 35, count 0 2006.260.08:05:13.29#ibcon#read 6, iclass 35, count 0 2006.260.08:05:13.29#ibcon#end of sib2, iclass 35, count 0 2006.260.08:05:13.29#ibcon#*after write, iclass 35, count 0 2006.260.08:05:13.29#ibcon#*before return 0, iclass 35, count 0 2006.260.08:05:13.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:13.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:05:13.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:05:13.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:05:13.29$vc4f8/vblo=5,744.99 2006.260.08:05:13.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:05:13.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:05:13.29#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:13.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:13.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:13.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:13.29#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:05:13.29#ibcon#first serial, iclass 37, count 0 2006.260.08:05:13.29#ibcon#enter sib2, iclass 37, count 0 2006.260.08:05:13.29#ibcon#flushed, iclass 37, count 0 2006.260.08:05:13.29#ibcon#about to write, iclass 37, count 0 2006.260.08:05:13.29#ibcon#wrote, iclass 37, count 0 2006.260.08:05:13.29#ibcon#about to read 3, iclass 37, count 0 2006.260.08:05:13.31#ibcon#read 3, iclass 37, count 0 2006.260.08:05:13.31#ibcon#about to read 4, iclass 37, count 0 2006.260.08:05:13.31#ibcon#read 4, iclass 37, count 0 2006.260.08:05:13.31#ibcon#about to read 5, iclass 37, count 0 2006.260.08:05:13.31#ibcon#read 5, iclass 37, count 0 2006.260.08:05:13.31#ibcon#about to read 6, iclass 37, count 0 2006.260.08:05:13.31#ibcon#read 6, iclass 37, count 0 2006.260.08:05:13.31#ibcon#end of sib2, iclass 37, count 0 2006.260.08:05:13.31#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:05:13.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:05:13.31#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:05:13.31#ibcon#*before write, iclass 37, count 0 2006.260.08:05:13.31#ibcon#enter sib2, iclass 37, count 0 2006.260.08:05:13.31#ibcon#flushed, iclass 37, count 0 2006.260.08:05:13.31#ibcon#about to write, iclass 37, count 0 2006.260.08:05:13.31#ibcon#wrote, iclass 37, count 0 2006.260.08:05:13.31#ibcon#about to read 3, iclass 37, count 0 2006.260.08:05:13.35#ibcon#read 3, iclass 37, count 0 2006.260.08:05:13.35#ibcon#about to read 4, iclass 37, count 0 2006.260.08:05:13.35#ibcon#read 4, iclass 37, count 0 2006.260.08:05:13.35#ibcon#about to read 5, iclass 37, count 0 2006.260.08:05:13.35#ibcon#read 5, iclass 37, count 0 2006.260.08:05:13.35#ibcon#about to read 6, iclass 37, count 0 2006.260.08:05:13.35#ibcon#read 6, iclass 37, count 0 2006.260.08:05:13.35#ibcon#end of sib2, iclass 37, count 0 2006.260.08:05:13.35#ibcon#*after write, iclass 37, count 0 2006.260.08:05:13.35#ibcon#*before return 0, iclass 37, count 0 2006.260.08:05:13.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:13.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:05:13.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:05:13.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:05:13.35$vc4f8/vb=5,4 2006.260.08:05:13.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.08:05:13.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.08:05:13.35#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:13.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:13.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:13.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:13.41#ibcon#enter wrdev, iclass 39, count 2 2006.260.08:05:13.41#ibcon#first serial, iclass 39, count 2 2006.260.08:05:13.41#ibcon#enter sib2, iclass 39, count 2 2006.260.08:05:13.41#ibcon#flushed, iclass 39, count 2 2006.260.08:05:13.41#ibcon#about to write, iclass 39, count 2 2006.260.08:05:13.41#ibcon#wrote, iclass 39, count 2 2006.260.08:05:13.41#ibcon#about to read 3, iclass 39, count 2 2006.260.08:05:13.44#ibcon#read 3, iclass 39, count 2 2006.260.08:05:13.44#ibcon#about to read 4, iclass 39, count 2 2006.260.08:05:13.44#ibcon#read 4, iclass 39, count 2 2006.260.08:05:13.44#ibcon#about to read 5, iclass 39, count 2 2006.260.08:05:13.44#ibcon#read 5, iclass 39, count 2 2006.260.08:05:13.44#ibcon#about to read 6, iclass 39, count 2 2006.260.08:05:13.44#ibcon#read 6, iclass 39, count 2 2006.260.08:05:13.44#ibcon#end of sib2, iclass 39, count 2 2006.260.08:05:13.44#ibcon#*mode == 0, iclass 39, count 2 2006.260.08:05:13.44#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.08:05:13.44#ibcon#[27=AT05-04\r\n] 2006.260.08:05:13.44#ibcon#*before write, iclass 39, count 2 2006.260.08:05:13.44#ibcon#enter sib2, iclass 39, count 2 2006.260.08:05:13.44#ibcon#flushed, iclass 39, count 2 2006.260.08:05:13.44#ibcon#about to write, iclass 39, count 2 2006.260.08:05:13.44#ibcon#wrote, iclass 39, count 2 2006.260.08:05:13.44#ibcon#about to read 3, iclass 39, count 2 2006.260.08:05:13.47#ibcon#read 3, iclass 39, count 2 2006.260.08:05:13.47#ibcon#about to read 4, iclass 39, count 2 2006.260.08:05:13.47#ibcon#read 4, iclass 39, count 2 2006.260.08:05:13.47#ibcon#about to read 5, iclass 39, count 2 2006.260.08:05:13.47#ibcon#read 5, iclass 39, count 2 2006.260.08:05:13.47#ibcon#about to read 6, iclass 39, count 2 2006.260.08:05:13.47#ibcon#read 6, iclass 39, count 2 2006.260.08:05:13.47#ibcon#end of sib2, iclass 39, count 2 2006.260.08:05:13.47#ibcon#*after write, iclass 39, count 2 2006.260.08:05:13.47#ibcon#*before return 0, iclass 39, count 2 2006.260.08:05:13.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:13.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:05:13.47#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.08:05:13.47#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:13.47#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:13.59#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:13.59#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:13.59#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:05:13.59#ibcon#first serial, iclass 39, count 0 2006.260.08:05:13.59#ibcon#enter sib2, iclass 39, count 0 2006.260.08:05:13.59#ibcon#flushed, iclass 39, count 0 2006.260.08:05:13.59#ibcon#about to write, iclass 39, count 0 2006.260.08:05:13.59#ibcon#wrote, iclass 39, count 0 2006.260.08:05:13.59#ibcon#about to read 3, iclass 39, count 0 2006.260.08:05:13.61#ibcon#read 3, iclass 39, count 0 2006.260.08:05:13.61#ibcon#about to read 4, iclass 39, count 0 2006.260.08:05:13.61#ibcon#read 4, iclass 39, count 0 2006.260.08:05:13.61#ibcon#about to read 5, iclass 39, count 0 2006.260.08:05:13.61#ibcon#read 5, iclass 39, count 0 2006.260.08:05:13.61#ibcon#about to read 6, iclass 39, count 0 2006.260.08:05:13.61#ibcon#read 6, iclass 39, count 0 2006.260.08:05:13.61#ibcon#end of sib2, iclass 39, count 0 2006.260.08:05:13.61#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:05:13.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:05:13.61#ibcon#[27=USB\r\n] 2006.260.08:05:13.61#ibcon#*before write, iclass 39, count 0 2006.260.08:05:13.61#ibcon#enter sib2, iclass 39, count 0 2006.260.08:05:13.61#ibcon#flushed, iclass 39, count 0 2006.260.08:05:13.61#ibcon#about to write, iclass 39, count 0 2006.260.08:05:13.61#ibcon#wrote, iclass 39, count 0 2006.260.08:05:13.61#ibcon#about to read 3, iclass 39, count 0 2006.260.08:05:13.64#ibcon#read 3, iclass 39, count 0 2006.260.08:05:13.64#ibcon#about to read 4, iclass 39, count 0 2006.260.08:05:13.64#ibcon#read 4, iclass 39, count 0 2006.260.08:05:13.64#ibcon#about to read 5, iclass 39, count 0 2006.260.08:05:13.64#ibcon#read 5, iclass 39, count 0 2006.260.08:05:13.64#ibcon#about to read 6, iclass 39, count 0 2006.260.08:05:13.64#ibcon#read 6, iclass 39, count 0 2006.260.08:05:13.64#ibcon#end of sib2, iclass 39, count 0 2006.260.08:05:13.64#ibcon#*after write, iclass 39, count 0 2006.260.08:05:13.64#ibcon#*before return 0, iclass 39, count 0 2006.260.08:05:13.64#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:13.64#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:05:13.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:05:13.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:05:13.64$vc4f8/vblo=6,752.99 2006.260.08:05:13.64#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.08:05:13.64#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.08:05:13.64#ibcon#ireg 17 cls_cnt 0 2006.260.08:05:13.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:13.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:13.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:13.64#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:05:13.64#ibcon#first serial, iclass 3, count 0 2006.260.08:05:13.64#ibcon#enter sib2, iclass 3, count 0 2006.260.08:05:13.64#ibcon#flushed, iclass 3, count 0 2006.260.08:05:13.64#ibcon#about to write, iclass 3, count 0 2006.260.08:05:13.64#ibcon#wrote, iclass 3, count 0 2006.260.08:05:13.64#ibcon#about to read 3, iclass 3, count 0 2006.260.08:05:13.66#ibcon#read 3, iclass 3, count 0 2006.260.08:05:13.66#ibcon#about to read 4, iclass 3, count 0 2006.260.08:05:13.66#ibcon#read 4, iclass 3, count 0 2006.260.08:05:13.66#ibcon#about to read 5, iclass 3, count 0 2006.260.08:05:13.66#ibcon#read 5, iclass 3, count 0 2006.260.08:05:13.66#ibcon#about to read 6, iclass 3, count 0 2006.260.08:05:13.66#ibcon#read 6, iclass 3, count 0 2006.260.08:05:13.66#ibcon#end of sib2, iclass 3, count 0 2006.260.08:05:13.66#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:05:13.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:05:13.66#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:05:13.66#ibcon#*before write, iclass 3, count 0 2006.260.08:05:13.66#ibcon#enter sib2, iclass 3, count 0 2006.260.08:05:13.66#ibcon#flushed, iclass 3, count 0 2006.260.08:05:13.66#ibcon#about to write, iclass 3, count 0 2006.260.08:05:13.66#ibcon#wrote, iclass 3, count 0 2006.260.08:05:13.66#ibcon#about to read 3, iclass 3, count 0 2006.260.08:05:13.70#ibcon#read 3, iclass 3, count 0 2006.260.08:05:13.70#ibcon#about to read 4, iclass 3, count 0 2006.260.08:05:13.70#ibcon#read 4, iclass 3, count 0 2006.260.08:05:13.70#ibcon#about to read 5, iclass 3, count 0 2006.260.08:05:13.70#ibcon#read 5, iclass 3, count 0 2006.260.08:05:13.70#ibcon#about to read 6, iclass 3, count 0 2006.260.08:05:13.70#ibcon#read 6, iclass 3, count 0 2006.260.08:05:13.70#ibcon#end of sib2, iclass 3, count 0 2006.260.08:05:13.70#ibcon#*after write, iclass 3, count 0 2006.260.08:05:13.70#ibcon#*before return 0, iclass 3, count 0 2006.260.08:05:13.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:13.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:05:13.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:05:13.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:05:13.70$vc4f8/vb=6,4 2006.260.08:05:13.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.08:05:13.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.08:05:13.70#ibcon#ireg 11 cls_cnt 2 2006.260.08:05:13.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:13.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:13.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:13.76#ibcon#enter wrdev, iclass 5, count 2 2006.260.08:05:13.76#ibcon#first serial, iclass 5, count 2 2006.260.08:05:13.76#ibcon#enter sib2, iclass 5, count 2 2006.260.08:05:13.76#ibcon#flushed, iclass 5, count 2 2006.260.08:05:13.76#ibcon#about to write, iclass 5, count 2 2006.260.08:05:13.76#ibcon#wrote, iclass 5, count 2 2006.260.08:05:13.76#ibcon#about to read 3, iclass 5, count 2 2006.260.08:05:13.78#ibcon#read 3, iclass 5, count 2 2006.260.08:05:13.78#ibcon#about to read 4, iclass 5, count 2 2006.260.08:05:13.78#ibcon#read 4, iclass 5, count 2 2006.260.08:05:13.78#ibcon#about to read 5, iclass 5, count 2 2006.260.08:05:13.78#ibcon#read 5, iclass 5, count 2 2006.260.08:05:13.78#ibcon#about to read 6, iclass 5, count 2 2006.260.08:05:13.78#ibcon#read 6, iclass 5, count 2 2006.260.08:05:13.78#ibcon#end of sib2, iclass 5, count 2 2006.260.08:05:13.78#ibcon#*mode == 0, iclass 5, count 2 2006.260.08:05:13.78#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.08:05:13.78#ibcon#[27=AT06-04\r\n] 2006.260.08:05:13.78#ibcon#*before write, iclass 5, count 2 2006.260.08:05:13.78#ibcon#enter sib2, iclass 5, count 2 2006.260.08:05:13.78#ibcon#flushed, iclass 5, count 2 2006.260.08:05:13.78#ibcon#about to write, iclass 5, count 2 2006.260.08:05:13.78#ibcon#wrote, iclass 5, count 2 2006.260.08:05:13.78#ibcon#about to read 3, iclass 5, count 2 2006.260.08:05:13.81#ibcon#read 3, iclass 5, count 2 2006.260.08:05:13.81#ibcon#about to read 4, iclass 5, count 2 2006.260.08:05:13.81#ibcon#read 4, iclass 5, count 2 2006.260.08:05:13.81#ibcon#about to read 5, iclass 5, count 2 2006.260.08:05:13.81#ibcon#read 5, iclass 5, count 2 2006.260.08:05:13.81#ibcon#about to read 6, iclass 5, count 2 2006.260.08:05:13.81#ibcon#read 6, iclass 5, count 2 2006.260.08:05:13.81#ibcon#end of sib2, iclass 5, count 2 2006.260.08:05:13.81#ibcon#*after write, iclass 5, count 2 2006.260.08:05:13.81#ibcon#*before return 0, iclass 5, count 2 2006.260.08:05:13.81#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:13.81#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:05:13.81#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.08:05:13.81#ibcon#ireg 7 cls_cnt 0 2006.260.08:05:13.81#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:13.93#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:13.93#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:13.93#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:05:13.93#ibcon#first serial, iclass 5, count 0 2006.260.08:05:13.93#ibcon#enter sib2, iclass 5, count 0 2006.260.08:05:13.93#ibcon#flushed, iclass 5, count 0 2006.260.08:05:13.93#ibcon#about to write, iclass 5, count 0 2006.260.08:05:13.93#ibcon#wrote, iclass 5, count 0 2006.260.08:05:13.93#ibcon#about to read 3, iclass 5, count 0 2006.260.08:05:13.95#ibcon#read 3, iclass 5, count 0 2006.260.08:05:13.95#ibcon#about to read 4, iclass 5, count 0 2006.260.08:05:13.95#ibcon#read 4, iclass 5, count 0 2006.260.08:05:13.95#ibcon#about to read 5, iclass 5, count 0 2006.260.08:05:13.95#ibcon#read 5, iclass 5, count 0 2006.260.08:05:13.95#ibcon#about to read 6, iclass 5, count 0 2006.260.08:05:13.95#ibcon#read 6, iclass 5, count 0 2006.260.08:05:13.95#ibcon#end of sib2, iclass 5, count 0 2006.260.08:05:13.95#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:05:13.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:05:13.95#ibcon#[27=USB\r\n] 2006.260.08:05:13.95#ibcon#*before write, iclass 5, count 0 2006.260.08:05:13.95#ibcon#enter sib2, iclass 5, count 0 2006.260.08:05:13.95#ibcon#flushed, iclass 5, count 0 2006.260.08:05:13.95#ibcon#about to write, iclass 5, count 0 2006.260.08:05:13.95#ibcon#wrote, iclass 5, count 0 2006.260.08:05:13.95#ibcon#about to read 3, iclass 5, count 0 2006.260.08:05:13.98#ibcon#read 3, iclass 5, count 0 2006.260.08:05:13.98#ibcon#about to read 4, iclass 5, count 0 2006.260.08:05:13.98#ibcon#read 4, iclass 5, count 0 2006.260.08:05:13.98#ibcon#about to read 5, iclass 5, count 0 2006.260.08:05:13.98#ibcon#read 5, iclass 5, count 0 2006.260.08:05:13.98#ibcon#about to read 6, iclass 5, count 0 2006.260.08:05:13.98#ibcon#read 6, iclass 5, count 0 2006.260.08:05:13.98#ibcon#end of sib2, iclass 5, count 0 2006.260.08:05:13.98#ibcon#*after write, iclass 5, count 0 2006.260.08:05:13.98#ibcon#*before return 0, iclass 5, count 0 2006.260.08:05:13.98#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:13.98#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:05:13.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:05:13.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:05:13.98$vc4f8/vabw=wide 2006.260.08:05:13.98#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:05:13.98#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:05:13.98#ibcon#ireg 8 cls_cnt 0 2006.260.08:05:13.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:13.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:13.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:13.98#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:05:13.98#ibcon#first serial, iclass 7, count 0 2006.260.08:05:13.98#ibcon#enter sib2, iclass 7, count 0 2006.260.08:05:13.98#ibcon#flushed, iclass 7, count 0 2006.260.08:05:13.98#ibcon#about to write, iclass 7, count 0 2006.260.08:05:13.98#ibcon#wrote, iclass 7, count 0 2006.260.08:05:13.98#ibcon#about to read 3, iclass 7, count 0 2006.260.08:05:14.00#ibcon#read 3, iclass 7, count 0 2006.260.08:05:14.00#ibcon#about to read 4, iclass 7, count 0 2006.260.08:05:14.00#ibcon#read 4, iclass 7, count 0 2006.260.08:05:14.00#ibcon#about to read 5, iclass 7, count 0 2006.260.08:05:14.00#ibcon#read 5, iclass 7, count 0 2006.260.08:05:14.00#ibcon#about to read 6, iclass 7, count 0 2006.260.08:05:14.00#ibcon#read 6, iclass 7, count 0 2006.260.08:05:14.00#ibcon#end of sib2, iclass 7, count 0 2006.260.08:05:14.00#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:05:14.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:05:14.00#ibcon#[25=BW32\r\n] 2006.260.08:05:14.00#ibcon#*before write, iclass 7, count 0 2006.260.08:05:14.00#ibcon#enter sib2, iclass 7, count 0 2006.260.08:05:14.00#ibcon#flushed, iclass 7, count 0 2006.260.08:05:14.00#ibcon#about to write, iclass 7, count 0 2006.260.08:05:14.00#ibcon#wrote, iclass 7, count 0 2006.260.08:05:14.00#ibcon#about to read 3, iclass 7, count 0 2006.260.08:05:14.03#ibcon#read 3, iclass 7, count 0 2006.260.08:05:14.03#ibcon#about to read 4, iclass 7, count 0 2006.260.08:05:14.03#ibcon#read 4, iclass 7, count 0 2006.260.08:05:14.03#ibcon#about to read 5, iclass 7, count 0 2006.260.08:05:14.03#ibcon#read 5, iclass 7, count 0 2006.260.08:05:14.03#ibcon#about to read 6, iclass 7, count 0 2006.260.08:05:14.03#ibcon#read 6, iclass 7, count 0 2006.260.08:05:14.03#ibcon#end of sib2, iclass 7, count 0 2006.260.08:05:14.03#ibcon#*after write, iclass 7, count 0 2006.260.08:05:14.03#ibcon#*before return 0, iclass 7, count 0 2006.260.08:05:14.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:14.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:05:14.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:05:14.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:05:14.03$vc4f8/vbbw=wide 2006.260.08:05:14.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:05:14.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:05:14.03#ibcon#ireg 8 cls_cnt 0 2006.260.08:05:14.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:05:14.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:05:14.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:05:14.10#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:05:14.10#ibcon#first serial, iclass 11, count 0 2006.260.08:05:14.10#ibcon#enter sib2, iclass 11, count 0 2006.260.08:05:14.10#ibcon#flushed, iclass 11, count 0 2006.260.08:05:14.10#ibcon#about to write, iclass 11, count 0 2006.260.08:05:14.10#ibcon#wrote, iclass 11, count 0 2006.260.08:05:14.10#ibcon#about to read 3, iclass 11, count 0 2006.260.08:05:14.12#ibcon#read 3, iclass 11, count 0 2006.260.08:05:14.12#ibcon#about to read 4, iclass 11, count 0 2006.260.08:05:14.12#ibcon#read 4, iclass 11, count 0 2006.260.08:05:14.12#ibcon#about to read 5, iclass 11, count 0 2006.260.08:05:14.12#ibcon#read 5, iclass 11, count 0 2006.260.08:05:14.12#ibcon#about to read 6, iclass 11, count 0 2006.260.08:05:14.12#ibcon#read 6, iclass 11, count 0 2006.260.08:05:14.12#ibcon#end of sib2, iclass 11, count 0 2006.260.08:05:14.12#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:05:14.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:05:14.12#ibcon#[27=BW32\r\n] 2006.260.08:05:14.12#ibcon#*before write, iclass 11, count 0 2006.260.08:05:14.12#ibcon#enter sib2, iclass 11, count 0 2006.260.08:05:14.12#ibcon#flushed, iclass 11, count 0 2006.260.08:05:14.12#ibcon#about to write, iclass 11, count 0 2006.260.08:05:14.12#ibcon#wrote, iclass 11, count 0 2006.260.08:05:14.12#ibcon#about to read 3, iclass 11, count 0 2006.260.08:05:14.15#ibcon#read 3, iclass 11, count 0 2006.260.08:05:14.15#ibcon#about to read 4, iclass 11, count 0 2006.260.08:05:14.15#ibcon#read 4, iclass 11, count 0 2006.260.08:05:14.15#ibcon#about to read 5, iclass 11, count 0 2006.260.08:05:14.15#ibcon#read 5, iclass 11, count 0 2006.260.08:05:14.15#ibcon#about to read 6, iclass 11, count 0 2006.260.08:05:14.15#ibcon#read 6, iclass 11, count 0 2006.260.08:05:14.15#ibcon#end of sib2, iclass 11, count 0 2006.260.08:05:14.15#ibcon#*after write, iclass 11, count 0 2006.260.08:05:14.15#ibcon#*before return 0, iclass 11, count 0 2006.260.08:05:14.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:05:14.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:05:14.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:05:14.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:05:14.15$4f8m12a/ifd4f 2006.260.08:05:14.15$ifd4f/lo= 2006.260.08:05:14.15$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:05:14.15$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:05:14.15$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:05:14.15$ifd4f/patch= 2006.260.08:05:14.15$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:05:14.15$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:05:14.15$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:05:14.15$4f8m12a/"form=m,16.000,1:2 2006.260.08:05:14.15$4f8m12a/"tpicd 2006.260.08:05:14.15$4f8m12a/echo=off 2006.260.08:05:14.15$4f8m12a/xlog=off 2006.260.08:05:14.15:!2006.260.08:05:40 2006.260.08:05:24.14#trakl#Source acquired 2006.260.08:05:25.14#flagr#flagr/antenna,acquired 2006.260.08:05:40.00:preob 2006.260.08:05:41.14/onsource/TRACKING 2006.260.08:05:41.14:!2006.260.08:05:50 2006.260.08:05:50.00:data_valid=on 2006.260.08:05:50.00:midob 2006.260.08:05:50.14/onsource/TRACKING 2006.260.08:05:50.14/wx/22.82,1010.4,89 2006.260.08:05:50.28/cable/+6.4575E-03 2006.260.08:05:51.37/va/01,08,usb,yes,33,34 2006.260.08:05:51.37/va/02,07,usb,yes,32,34 2006.260.08:05:51.37/va/03,08,usb,yes,25,25 2006.260.08:05:51.37/va/04,07,usb,yes,34,37 2006.260.08:05:51.37/va/05,07,usb,yes,38,40 2006.260.08:05:51.37/va/06,06,usb,yes,37,37 2006.260.08:05:51.37/va/07,06,usb,yes,38,37 2006.260.08:05:51.37/va/08,06,usb,yes,40,39 2006.260.08:05:51.60/valo/01,532.99,yes,locked 2006.260.08:05:51.60/valo/02,572.99,yes,locked 2006.260.08:05:51.60/valo/03,672.99,yes,locked 2006.260.08:05:51.60/valo/04,832.99,yes,locked 2006.260.08:05:51.60/valo/05,652.99,yes,locked 2006.260.08:05:51.60/valo/06,772.99,yes,locked 2006.260.08:05:51.60/valo/07,832.99,yes,locked 2006.260.08:05:51.60/valo/08,852.99,yes,locked 2006.260.08:05:52.69/vb/01,04,usb,yes,31,30 2006.260.08:05:52.69/vb/02,05,usb,yes,29,30 2006.260.08:05:52.69/vb/03,04,usb,yes,29,33 2006.260.08:05:52.69/vb/04,05,usb,yes,26,27 2006.260.08:05:52.69/vb/05,04,usb,yes,28,33 2006.260.08:05:52.69/vb/06,04,usb,yes,29,32 2006.260.08:05:52.69/vb/07,04,usb,yes,32,32 2006.260.08:05:52.69/vb/08,04,usb,yes,29,33 2006.260.08:05:52.92/vblo/01,632.99,yes,locked 2006.260.08:05:52.92/vblo/02,640.99,yes,locked 2006.260.08:05:52.92/vblo/03,656.99,yes,locked 2006.260.08:05:52.92/vblo/04,712.99,yes,locked 2006.260.08:05:52.92/vblo/05,744.99,yes,locked 2006.260.08:05:52.92/vblo/06,752.99,yes,locked 2006.260.08:05:52.92/vblo/07,734.99,yes,locked 2006.260.08:05:52.92/vblo/08,744.99,yes,locked 2006.260.08:05:53.07/vabw/8 2006.260.08:05:53.22/vbbw/8 2006.260.08:05:53.31/xfe/off,on,15.0 2006.260.08:05:53.70/ifatt/23,28,28,28 2006.260.08:05:54.07/fmout-gps/S +4.45E-07 2006.260.08:05:54.11:!2006.260.08:06:50 2006.260.08:06:50.00:data_valid=off 2006.260.08:06:50.00:postob 2006.260.08:06:50.15/cable/+6.4593E-03 2006.260.08:06:50.15/wx/22.82,1010.4,89 2006.260.08:06:51.08/fmout-gps/S +4.46E-07 2006.260.08:06:51.08:scan_name=260-0807,k06260,60 2006.260.08:06:51.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.260.08:06:51.14#flagr#flagr/antenna,new-source 2006.260.08:06:52.14:checkk5 2006.260.08:06:52.76/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:06:53.19/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:06:53.60/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:06:54.01/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:06:54.39/chk_obsdata//k5ts1/T2600805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:06:54.79/chk_obsdata//k5ts2/T2600805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:06:55.17/chk_obsdata//k5ts3/T2600805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:06:55.55/chk_obsdata//k5ts4/T2600805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:06:56.28/k5log//k5ts1_log_newline 2006.260.08:06:57.05/k5log//k5ts2_log_newline 2006.260.08:06:57.87/k5log//k5ts3_log_newline 2006.260.08:06:59.07/k5log//k5ts4_log_newline 2006.260.08:06:59.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:06:59.09:4f8m12a=2 2006.260.08:06:59.09$4f8m12a/echo=on 2006.260.08:06:59.09$4f8m12a/pcalon 2006.260.08:06:59.09$pcalon/"no phase cal control is implemented here 2006.260.08:06:59.09$4f8m12a/"tpicd=stop 2006.260.08:06:59.09$4f8m12a/vc4f8 2006.260.08:06:59.09$vc4f8/valo=1,532.99 2006.260.08:06:59.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:06:59.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:06:59.09#ibcon#ireg 17 cls_cnt 0 2006.260.08:06:59.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:06:59.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:06:59.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:06:59.09#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:06:59.09#ibcon#first serial, iclass 13, count 0 2006.260.08:06:59.09#ibcon#enter sib2, iclass 13, count 0 2006.260.08:06:59.09#ibcon#flushed, iclass 13, count 0 2006.260.08:06:59.09#ibcon#about to write, iclass 13, count 0 2006.260.08:06:59.09#ibcon#wrote, iclass 13, count 0 2006.260.08:06:59.09#ibcon#about to read 3, iclass 13, count 0 2006.260.08:06:59.14#ibcon#read 3, iclass 13, count 0 2006.260.08:06:59.14#ibcon#about to read 4, iclass 13, count 0 2006.260.08:06:59.14#ibcon#read 4, iclass 13, count 0 2006.260.08:06:59.14#ibcon#about to read 5, iclass 13, count 0 2006.260.08:06:59.14#ibcon#read 5, iclass 13, count 0 2006.260.08:06:59.14#ibcon#about to read 6, iclass 13, count 0 2006.260.08:06:59.14#ibcon#read 6, iclass 13, count 0 2006.260.08:06:59.14#ibcon#end of sib2, iclass 13, count 0 2006.260.08:06:59.14#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:06:59.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:06:59.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:06:59.14#ibcon#*before write, iclass 13, count 0 2006.260.08:06:59.14#ibcon#enter sib2, iclass 13, count 0 2006.260.08:06:59.14#ibcon#flushed, iclass 13, count 0 2006.260.08:06:59.14#ibcon#about to write, iclass 13, count 0 2006.260.08:06:59.14#ibcon#wrote, iclass 13, count 0 2006.260.08:06:59.14#ibcon#about to read 3, iclass 13, count 0 2006.260.08:06:59.19#ibcon#read 3, iclass 13, count 0 2006.260.08:06:59.19#ibcon#about to read 4, iclass 13, count 0 2006.260.08:06:59.19#ibcon#read 4, iclass 13, count 0 2006.260.08:06:59.19#ibcon#about to read 5, iclass 13, count 0 2006.260.08:06:59.19#ibcon#read 5, iclass 13, count 0 2006.260.08:06:59.19#ibcon#about to read 6, iclass 13, count 0 2006.260.08:06:59.19#ibcon#read 6, iclass 13, count 0 2006.260.08:06:59.19#ibcon#end of sib2, iclass 13, count 0 2006.260.08:06:59.19#ibcon#*after write, iclass 13, count 0 2006.260.08:06:59.19#ibcon#*before return 0, iclass 13, count 0 2006.260.08:06:59.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:06:59.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:06:59.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:06:59.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:06:59.19$vc4f8/va=1,8 2006.260.08:06:59.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:06:59.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:06:59.19#ibcon#ireg 11 cls_cnt 2 2006.260.08:06:59.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:06:59.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:06:59.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:06:59.19#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:06:59.19#ibcon#first serial, iclass 15, count 2 2006.260.08:06:59.19#ibcon#enter sib2, iclass 15, count 2 2006.260.08:06:59.19#ibcon#flushed, iclass 15, count 2 2006.260.08:06:59.19#ibcon#about to write, iclass 15, count 2 2006.260.08:06:59.19#ibcon#wrote, iclass 15, count 2 2006.260.08:06:59.19#ibcon#about to read 3, iclass 15, count 2 2006.260.08:06:59.22#ibcon#read 3, iclass 15, count 2 2006.260.08:06:59.22#ibcon#about to read 4, iclass 15, count 2 2006.260.08:06:59.22#ibcon#read 4, iclass 15, count 2 2006.260.08:06:59.22#ibcon#about to read 5, iclass 15, count 2 2006.260.08:06:59.22#ibcon#read 5, iclass 15, count 2 2006.260.08:06:59.22#ibcon#about to read 6, iclass 15, count 2 2006.260.08:06:59.22#ibcon#read 6, iclass 15, count 2 2006.260.08:06:59.22#ibcon#end of sib2, iclass 15, count 2 2006.260.08:06:59.22#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:06:59.22#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:06:59.22#ibcon#[25=AT01-08\r\n] 2006.260.08:06:59.22#ibcon#*before write, iclass 15, count 2 2006.260.08:06:59.22#ibcon#enter sib2, iclass 15, count 2 2006.260.08:06:59.22#ibcon#flushed, iclass 15, count 2 2006.260.08:06:59.22#ibcon#about to write, iclass 15, count 2 2006.260.08:06:59.22#ibcon#wrote, iclass 15, count 2 2006.260.08:06:59.22#ibcon#about to read 3, iclass 15, count 2 2006.260.08:06:59.25#ibcon#read 3, iclass 15, count 2 2006.260.08:06:59.25#ibcon#about to read 4, iclass 15, count 2 2006.260.08:06:59.25#ibcon#read 4, iclass 15, count 2 2006.260.08:06:59.25#ibcon#about to read 5, iclass 15, count 2 2006.260.08:06:59.25#ibcon#read 5, iclass 15, count 2 2006.260.08:06:59.25#ibcon#about to read 6, iclass 15, count 2 2006.260.08:06:59.25#ibcon#read 6, iclass 15, count 2 2006.260.08:06:59.25#ibcon#end of sib2, iclass 15, count 2 2006.260.08:06:59.25#ibcon#*after write, iclass 15, count 2 2006.260.08:06:59.25#ibcon#*before return 0, iclass 15, count 2 2006.260.08:06:59.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:06:59.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:06:59.25#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:06:59.25#ibcon#ireg 7 cls_cnt 0 2006.260.08:06:59.25#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:06:59.37#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:06:59.37#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:06:59.37#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:06:59.37#ibcon#first serial, iclass 15, count 0 2006.260.08:06:59.37#ibcon#enter sib2, iclass 15, count 0 2006.260.08:06:59.37#ibcon#flushed, iclass 15, count 0 2006.260.08:06:59.37#ibcon#about to write, iclass 15, count 0 2006.260.08:06:59.37#ibcon#wrote, iclass 15, count 0 2006.260.08:06:59.37#ibcon#about to read 3, iclass 15, count 0 2006.260.08:06:59.39#ibcon#read 3, iclass 15, count 0 2006.260.08:06:59.39#ibcon#about to read 4, iclass 15, count 0 2006.260.08:06:59.39#ibcon#read 4, iclass 15, count 0 2006.260.08:06:59.39#ibcon#about to read 5, iclass 15, count 0 2006.260.08:06:59.39#ibcon#read 5, iclass 15, count 0 2006.260.08:06:59.39#ibcon#about to read 6, iclass 15, count 0 2006.260.08:06:59.39#ibcon#read 6, iclass 15, count 0 2006.260.08:06:59.39#ibcon#end of sib2, iclass 15, count 0 2006.260.08:06:59.39#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:06:59.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:06:59.39#ibcon#[25=USB\r\n] 2006.260.08:06:59.39#ibcon#*before write, iclass 15, count 0 2006.260.08:06:59.39#ibcon#enter sib2, iclass 15, count 0 2006.260.08:06:59.39#ibcon#flushed, iclass 15, count 0 2006.260.08:06:59.39#ibcon#about to write, iclass 15, count 0 2006.260.08:06:59.39#ibcon#wrote, iclass 15, count 0 2006.260.08:06:59.39#ibcon#about to read 3, iclass 15, count 0 2006.260.08:06:59.42#ibcon#read 3, iclass 15, count 0 2006.260.08:06:59.42#ibcon#about to read 4, iclass 15, count 0 2006.260.08:06:59.42#ibcon#read 4, iclass 15, count 0 2006.260.08:06:59.42#ibcon#about to read 5, iclass 15, count 0 2006.260.08:06:59.42#ibcon#read 5, iclass 15, count 0 2006.260.08:06:59.42#ibcon#about to read 6, iclass 15, count 0 2006.260.08:06:59.42#ibcon#read 6, iclass 15, count 0 2006.260.08:06:59.42#ibcon#end of sib2, iclass 15, count 0 2006.260.08:06:59.42#ibcon#*after write, iclass 15, count 0 2006.260.08:06:59.42#ibcon#*before return 0, iclass 15, count 0 2006.260.08:06:59.42#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:06:59.42#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:06:59.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:06:59.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:06:59.42$vc4f8/valo=2,572.99 2006.260.08:06:59.42#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.08:06:59.42#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.08:06:59.42#ibcon#ireg 17 cls_cnt 0 2006.260.08:06:59.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:06:59.42#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:06:59.42#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:06:59.42#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:06:59.42#ibcon#first serial, iclass 17, count 0 2006.260.08:06:59.42#ibcon#enter sib2, iclass 17, count 0 2006.260.08:06:59.42#ibcon#flushed, iclass 17, count 0 2006.260.08:06:59.42#ibcon#about to write, iclass 17, count 0 2006.260.08:06:59.42#ibcon#wrote, iclass 17, count 0 2006.260.08:06:59.42#ibcon#about to read 3, iclass 17, count 0 2006.260.08:06:59.44#ibcon#read 3, iclass 17, count 0 2006.260.08:06:59.44#ibcon#about to read 4, iclass 17, count 0 2006.260.08:06:59.44#ibcon#read 4, iclass 17, count 0 2006.260.08:06:59.44#ibcon#about to read 5, iclass 17, count 0 2006.260.08:06:59.44#ibcon#read 5, iclass 17, count 0 2006.260.08:06:59.44#ibcon#about to read 6, iclass 17, count 0 2006.260.08:06:59.44#ibcon#read 6, iclass 17, count 0 2006.260.08:06:59.44#ibcon#end of sib2, iclass 17, count 0 2006.260.08:06:59.44#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:06:59.44#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:06:59.44#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:06:59.44#ibcon#*before write, iclass 17, count 0 2006.260.08:06:59.44#ibcon#enter sib2, iclass 17, count 0 2006.260.08:06:59.44#ibcon#flushed, iclass 17, count 0 2006.260.08:06:59.44#ibcon#about to write, iclass 17, count 0 2006.260.08:06:59.44#ibcon#wrote, iclass 17, count 0 2006.260.08:06:59.44#ibcon#about to read 3, iclass 17, count 0 2006.260.08:06:59.48#ibcon#read 3, iclass 17, count 0 2006.260.08:06:59.48#ibcon#about to read 4, iclass 17, count 0 2006.260.08:06:59.48#ibcon#read 4, iclass 17, count 0 2006.260.08:06:59.48#ibcon#about to read 5, iclass 17, count 0 2006.260.08:06:59.48#ibcon#read 5, iclass 17, count 0 2006.260.08:06:59.48#ibcon#about to read 6, iclass 17, count 0 2006.260.08:06:59.48#ibcon#read 6, iclass 17, count 0 2006.260.08:06:59.48#ibcon#end of sib2, iclass 17, count 0 2006.260.08:06:59.48#ibcon#*after write, iclass 17, count 0 2006.260.08:06:59.48#ibcon#*before return 0, iclass 17, count 0 2006.260.08:06:59.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:06:59.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:06:59.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:06:59.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:06:59.48$vc4f8/va=2,7 2006.260.08:06:59.48#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.08:06:59.48#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.08:06:59.48#ibcon#ireg 11 cls_cnt 2 2006.260.08:06:59.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:06:59.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:06:59.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:06:59.54#ibcon#enter wrdev, iclass 19, count 2 2006.260.08:06:59.54#ibcon#first serial, iclass 19, count 2 2006.260.08:06:59.54#ibcon#enter sib2, iclass 19, count 2 2006.260.08:06:59.54#ibcon#flushed, iclass 19, count 2 2006.260.08:06:59.54#ibcon#about to write, iclass 19, count 2 2006.260.08:06:59.54#ibcon#wrote, iclass 19, count 2 2006.260.08:06:59.54#ibcon#about to read 3, iclass 19, count 2 2006.260.08:06:59.57#ibcon#read 3, iclass 19, count 2 2006.260.08:06:59.57#ibcon#about to read 4, iclass 19, count 2 2006.260.08:06:59.57#ibcon#read 4, iclass 19, count 2 2006.260.08:06:59.57#ibcon#about to read 5, iclass 19, count 2 2006.260.08:06:59.57#ibcon#read 5, iclass 19, count 2 2006.260.08:06:59.57#ibcon#about to read 6, iclass 19, count 2 2006.260.08:06:59.57#ibcon#read 6, iclass 19, count 2 2006.260.08:06:59.57#ibcon#end of sib2, iclass 19, count 2 2006.260.08:06:59.57#ibcon#*mode == 0, iclass 19, count 2 2006.260.08:06:59.57#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.08:06:59.57#ibcon#[25=AT02-07\r\n] 2006.260.08:06:59.57#ibcon#*before write, iclass 19, count 2 2006.260.08:06:59.57#ibcon#enter sib2, iclass 19, count 2 2006.260.08:06:59.57#ibcon#flushed, iclass 19, count 2 2006.260.08:06:59.57#ibcon#about to write, iclass 19, count 2 2006.260.08:06:59.57#ibcon#wrote, iclass 19, count 2 2006.260.08:06:59.57#ibcon#about to read 3, iclass 19, count 2 2006.260.08:06:59.60#ibcon#read 3, iclass 19, count 2 2006.260.08:06:59.60#ibcon#about to read 4, iclass 19, count 2 2006.260.08:06:59.60#ibcon#read 4, iclass 19, count 2 2006.260.08:06:59.60#ibcon#about to read 5, iclass 19, count 2 2006.260.08:06:59.60#ibcon#read 5, iclass 19, count 2 2006.260.08:06:59.60#ibcon#about to read 6, iclass 19, count 2 2006.260.08:06:59.60#ibcon#read 6, iclass 19, count 2 2006.260.08:06:59.60#ibcon#end of sib2, iclass 19, count 2 2006.260.08:06:59.60#ibcon#*after write, iclass 19, count 2 2006.260.08:06:59.60#ibcon#*before return 0, iclass 19, count 2 2006.260.08:06:59.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:06:59.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:06:59.60#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.08:06:59.60#ibcon#ireg 7 cls_cnt 0 2006.260.08:06:59.60#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:06:59.72#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:06:59.72#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:06:59.72#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:06:59.72#ibcon#first serial, iclass 19, count 0 2006.260.08:06:59.72#ibcon#enter sib2, iclass 19, count 0 2006.260.08:06:59.72#ibcon#flushed, iclass 19, count 0 2006.260.08:06:59.72#ibcon#about to write, iclass 19, count 0 2006.260.08:06:59.72#ibcon#wrote, iclass 19, count 0 2006.260.08:06:59.72#ibcon#about to read 3, iclass 19, count 0 2006.260.08:06:59.74#ibcon#read 3, iclass 19, count 0 2006.260.08:06:59.74#ibcon#about to read 4, iclass 19, count 0 2006.260.08:06:59.74#ibcon#read 4, iclass 19, count 0 2006.260.08:06:59.74#ibcon#about to read 5, iclass 19, count 0 2006.260.08:06:59.74#ibcon#read 5, iclass 19, count 0 2006.260.08:06:59.74#ibcon#about to read 6, iclass 19, count 0 2006.260.08:06:59.74#ibcon#read 6, iclass 19, count 0 2006.260.08:06:59.74#ibcon#end of sib2, iclass 19, count 0 2006.260.08:06:59.74#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:06:59.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:06:59.74#ibcon#[25=USB\r\n] 2006.260.08:06:59.74#ibcon#*before write, iclass 19, count 0 2006.260.08:06:59.74#ibcon#enter sib2, iclass 19, count 0 2006.260.08:06:59.74#ibcon#flushed, iclass 19, count 0 2006.260.08:06:59.74#ibcon#about to write, iclass 19, count 0 2006.260.08:06:59.74#ibcon#wrote, iclass 19, count 0 2006.260.08:06:59.74#ibcon#about to read 3, iclass 19, count 0 2006.260.08:06:59.77#ibcon#read 3, iclass 19, count 0 2006.260.08:06:59.77#ibcon#about to read 4, iclass 19, count 0 2006.260.08:06:59.77#ibcon#read 4, iclass 19, count 0 2006.260.08:06:59.77#ibcon#about to read 5, iclass 19, count 0 2006.260.08:06:59.77#ibcon#read 5, iclass 19, count 0 2006.260.08:06:59.77#ibcon#about to read 6, iclass 19, count 0 2006.260.08:06:59.77#ibcon#read 6, iclass 19, count 0 2006.260.08:06:59.77#ibcon#end of sib2, iclass 19, count 0 2006.260.08:06:59.77#ibcon#*after write, iclass 19, count 0 2006.260.08:06:59.77#ibcon#*before return 0, iclass 19, count 0 2006.260.08:06:59.77#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:06:59.77#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:06:59.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:06:59.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:06:59.77$vc4f8/valo=3,672.99 2006.260.08:06:59.77#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:06:59.77#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:06:59.77#ibcon#ireg 17 cls_cnt 0 2006.260.08:06:59.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:06:59.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:06:59.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:06:59.77#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:06:59.77#ibcon#first serial, iclass 21, count 0 2006.260.08:06:59.77#ibcon#enter sib2, iclass 21, count 0 2006.260.08:06:59.77#ibcon#flushed, iclass 21, count 0 2006.260.08:06:59.77#ibcon#about to write, iclass 21, count 0 2006.260.08:06:59.77#ibcon#wrote, iclass 21, count 0 2006.260.08:06:59.77#ibcon#about to read 3, iclass 21, count 0 2006.260.08:06:59.79#ibcon#read 3, iclass 21, count 0 2006.260.08:06:59.79#ibcon#about to read 4, iclass 21, count 0 2006.260.08:06:59.79#ibcon#read 4, iclass 21, count 0 2006.260.08:06:59.79#ibcon#about to read 5, iclass 21, count 0 2006.260.08:06:59.79#ibcon#read 5, iclass 21, count 0 2006.260.08:06:59.79#ibcon#about to read 6, iclass 21, count 0 2006.260.08:06:59.79#ibcon#read 6, iclass 21, count 0 2006.260.08:06:59.79#ibcon#end of sib2, iclass 21, count 0 2006.260.08:06:59.79#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:06:59.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:06:59.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:06:59.79#ibcon#*before write, iclass 21, count 0 2006.260.08:06:59.79#ibcon#enter sib2, iclass 21, count 0 2006.260.08:06:59.79#ibcon#flushed, iclass 21, count 0 2006.260.08:06:59.79#ibcon#about to write, iclass 21, count 0 2006.260.08:06:59.79#ibcon#wrote, iclass 21, count 0 2006.260.08:06:59.79#ibcon#about to read 3, iclass 21, count 0 2006.260.08:06:59.83#ibcon#read 3, iclass 21, count 0 2006.260.08:06:59.83#ibcon#about to read 4, iclass 21, count 0 2006.260.08:06:59.83#ibcon#read 4, iclass 21, count 0 2006.260.08:06:59.83#ibcon#about to read 5, iclass 21, count 0 2006.260.08:06:59.83#ibcon#read 5, iclass 21, count 0 2006.260.08:06:59.83#ibcon#about to read 6, iclass 21, count 0 2006.260.08:06:59.83#ibcon#read 6, iclass 21, count 0 2006.260.08:06:59.83#ibcon#end of sib2, iclass 21, count 0 2006.260.08:06:59.83#ibcon#*after write, iclass 21, count 0 2006.260.08:06:59.83#ibcon#*before return 0, iclass 21, count 0 2006.260.08:06:59.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:06:59.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:06:59.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:06:59.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:06:59.83$vc4f8/va=3,8 2006.260.08:06:59.83#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:06:59.83#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:06:59.83#ibcon#ireg 11 cls_cnt 2 2006.260.08:06:59.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:06:59.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:06:59.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:06:59.89#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:06:59.89#ibcon#first serial, iclass 23, count 2 2006.260.08:06:59.89#ibcon#enter sib2, iclass 23, count 2 2006.260.08:06:59.89#ibcon#flushed, iclass 23, count 2 2006.260.08:06:59.89#ibcon#about to write, iclass 23, count 2 2006.260.08:06:59.89#ibcon#wrote, iclass 23, count 2 2006.260.08:06:59.89#ibcon#about to read 3, iclass 23, count 2 2006.260.08:06:59.91#ibcon#read 3, iclass 23, count 2 2006.260.08:06:59.91#ibcon#about to read 4, iclass 23, count 2 2006.260.08:06:59.91#ibcon#read 4, iclass 23, count 2 2006.260.08:06:59.91#ibcon#about to read 5, iclass 23, count 2 2006.260.08:06:59.91#ibcon#read 5, iclass 23, count 2 2006.260.08:06:59.91#ibcon#about to read 6, iclass 23, count 2 2006.260.08:06:59.91#ibcon#read 6, iclass 23, count 2 2006.260.08:06:59.91#ibcon#end of sib2, iclass 23, count 2 2006.260.08:06:59.91#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:06:59.91#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:06:59.91#ibcon#[25=AT03-08\r\n] 2006.260.08:06:59.91#ibcon#*before write, iclass 23, count 2 2006.260.08:06:59.91#ibcon#enter sib2, iclass 23, count 2 2006.260.08:06:59.91#ibcon#flushed, iclass 23, count 2 2006.260.08:06:59.91#ibcon#about to write, iclass 23, count 2 2006.260.08:06:59.91#ibcon#wrote, iclass 23, count 2 2006.260.08:06:59.91#ibcon#about to read 3, iclass 23, count 2 2006.260.08:06:59.94#ibcon#read 3, iclass 23, count 2 2006.260.08:06:59.94#ibcon#about to read 4, iclass 23, count 2 2006.260.08:06:59.94#ibcon#read 4, iclass 23, count 2 2006.260.08:06:59.94#ibcon#about to read 5, iclass 23, count 2 2006.260.08:06:59.94#ibcon#read 5, iclass 23, count 2 2006.260.08:06:59.94#ibcon#about to read 6, iclass 23, count 2 2006.260.08:06:59.94#ibcon#read 6, iclass 23, count 2 2006.260.08:06:59.94#ibcon#end of sib2, iclass 23, count 2 2006.260.08:06:59.94#ibcon#*after write, iclass 23, count 2 2006.260.08:06:59.94#ibcon#*before return 0, iclass 23, count 2 2006.260.08:06:59.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:06:59.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:06:59.94#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:06:59.94#ibcon#ireg 7 cls_cnt 0 2006.260.08:06:59.94#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:00.06#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:00.06#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:00.06#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:07:00.06#ibcon#first serial, iclass 23, count 0 2006.260.08:07:00.06#ibcon#enter sib2, iclass 23, count 0 2006.260.08:07:00.06#ibcon#flushed, iclass 23, count 0 2006.260.08:07:00.06#ibcon#about to write, iclass 23, count 0 2006.260.08:07:00.06#ibcon#wrote, iclass 23, count 0 2006.260.08:07:00.06#ibcon#about to read 3, iclass 23, count 0 2006.260.08:07:00.08#ibcon#read 3, iclass 23, count 0 2006.260.08:07:00.08#ibcon#about to read 4, iclass 23, count 0 2006.260.08:07:00.08#ibcon#read 4, iclass 23, count 0 2006.260.08:07:00.08#ibcon#about to read 5, iclass 23, count 0 2006.260.08:07:00.08#ibcon#read 5, iclass 23, count 0 2006.260.08:07:00.08#ibcon#about to read 6, iclass 23, count 0 2006.260.08:07:00.08#ibcon#read 6, iclass 23, count 0 2006.260.08:07:00.08#ibcon#end of sib2, iclass 23, count 0 2006.260.08:07:00.08#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:07:00.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:07:00.08#ibcon#[25=USB\r\n] 2006.260.08:07:00.08#ibcon#*before write, iclass 23, count 0 2006.260.08:07:00.08#ibcon#enter sib2, iclass 23, count 0 2006.260.08:07:00.08#ibcon#flushed, iclass 23, count 0 2006.260.08:07:00.08#ibcon#about to write, iclass 23, count 0 2006.260.08:07:00.08#ibcon#wrote, iclass 23, count 0 2006.260.08:07:00.08#ibcon#about to read 3, iclass 23, count 0 2006.260.08:07:00.11#ibcon#read 3, iclass 23, count 0 2006.260.08:07:00.11#ibcon#about to read 4, iclass 23, count 0 2006.260.08:07:00.11#ibcon#read 4, iclass 23, count 0 2006.260.08:07:00.11#ibcon#about to read 5, iclass 23, count 0 2006.260.08:07:00.11#ibcon#read 5, iclass 23, count 0 2006.260.08:07:00.11#ibcon#about to read 6, iclass 23, count 0 2006.260.08:07:00.11#ibcon#read 6, iclass 23, count 0 2006.260.08:07:00.11#ibcon#end of sib2, iclass 23, count 0 2006.260.08:07:00.11#ibcon#*after write, iclass 23, count 0 2006.260.08:07:00.11#ibcon#*before return 0, iclass 23, count 0 2006.260.08:07:00.11#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:00.11#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:00.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:07:00.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:07:00.11$vc4f8/valo=4,832.99 2006.260.08:07:00.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:07:00.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:07:00.11#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:00.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:00.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:00.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:00.11#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:07:00.11#ibcon#first serial, iclass 25, count 0 2006.260.08:07:00.11#ibcon#enter sib2, iclass 25, count 0 2006.260.08:07:00.11#ibcon#flushed, iclass 25, count 0 2006.260.08:07:00.11#ibcon#about to write, iclass 25, count 0 2006.260.08:07:00.11#ibcon#wrote, iclass 25, count 0 2006.260.08:07:00.11#ibcon#about to read 3, iclass 25, count 0 2006.260.08:07:00.13#ibcon#read 3, iclass 25, count 0 2006.260.08:07:00.13#ibcon#about to read 4, iclass 25, count 0 2006.260.08:07:00.13#ibcon#read 4, iclass 25, count 0 2006.260.08:07:00.13#ibcon#about to read 5, iclass 25, count 0 2006.260.08:07:00.13#ibcon#read 5, iclass 25, count 0 2006.260.08:07:00.13#ibcon#about to read 6, iclass 25, count 0 2006.260.08:07:00.13#ibcon#read 6, iclass 25, count 0 2006.260.08:07:00.13#ibcon#end of sib2, iclass 25, count 0 2006.260.08:07:00.13#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:07:00.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:07:00.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:07:00.13#ibcon#*before write, iclass 25, count 0 2006.260.08:07:00.13#ibcon#enter sib2, iclass 25, count 0 2006.260.08:07:00.13#ibcon#flushed, iclass 25, count 0 2006.260.08:07:00.13#ibcon#about to write, iclass 25, count 0 2006.260.08:07:00.13#ibcon#wrote, iclass 25, count 0 2006.260.08:07:00.13#ibcon#about to read 3, iclass 25, count 0 2006.260.08:07:00.17#ibcon#read 3, iclass 25, count 0 2006.260.08:07:00.17#ibcon#about to read 4, iclass 25, count 0 2006.260.08:07:00.17#ibcon#read 4, iclass 25, count 0 2006.260.08:07:00.17#ibcon#about to read 5, iclass 25, count 0 2006.260.08:07:00.17#ibcon#read 5, iclass 25, count 0 2006.260.08:07:00.17#ibcon#about to read 6, iclass 25, count 0 2006.260.08:07:00.17#ibcon#read 6, iclass 25, count 0 2006.260.08:07:00.17#ibcon#end of sib2, iclass 25, count 0 2006.260.08:07:00.17#ibcon#*after write, iclass 25, count 0 2006.260.08:07:00.17#ibcon#*before return 0, iclass 25, count 0 2006.260.08:07:00.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:00.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:00.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:07:00.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:07:00.17$vc4f8/va=4,7 2006.260.08:07:00.17#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:07:00.17#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:07:00.17#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:00.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:00.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:00.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:00.23#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:07:00.23#ibcon#first serial, iclass 27, count 2 2006.260.08:07:00.23#ibcon#enter sib2, iclass 27, count 2 2006.260.08:07:00.23#ibcon#flushed, iclass 27, count 2 2006.260.08:07:00.23#ibcon#about to write, iclass 27, count 2 2006.260.08:07:00.23#ibcon#wrote, iclass 27, count 2 2006.260.08:07:00.23#ibcon#about to read 3, iclass 27, count 2 2006.260.08:07:00.25#ibcon#read 3, iclass 27, count 2 2006.260.08:07:00.25#ibcon#about to read 4, iclass 27, count 2 2006.260.08:07:00.25#ibcon#read 4, iclass 27, count 2 2006.260.08:07:00.25#ibcon#about to read 5, iclass 27, count 2 2006.260.08:07:00.25#ibcon#read 5, iclass 27, count 2 2006.260.08:07:00.25#ibcon#about to read 6, iclass 27, count 2 2006.260.08:07:00.25#ibcon#read 6, iclass 27, count 2 2006.260.08:07:00.25#ibcon#end of sib2, iclass 27, count 2 2006.260.08:07:00.25#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:07:00.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:07:00.25#ibcon#[25=AT04-07\r\n] 2006.260.08:07:00.25#ibcon#*before write, iclass 27, count 2 2006.260.08:07:00.25#ibcon#enter sib2, iclass 27, count 2 2006.260.08:07:00.25#ibcon#flushed, iclass 27, count 2 2006.260.08:07:00.25#ibcon#about to write, iclass 27, count 2 2006.260.08:07:00.25#ibcon#wrote, iclass 27, count 2 2006.260.08:07:00.25#ibcon#about to read 3, iclass 27, count 2 2006.260.08:07:00.28#ibcon#read 3, iclass 27, count 2 2006.260.08:07:00.28#ibcon#about to read 4, iclass 27, count 2 2006.260.08:07:00.28#ibcon#read 4, iclass 27, count 2 2006.260.08:07:00.28#ibcon#about to read 5, iclass 27, count 2 2006.260.08:07:00.28#ibcon#read 5, iclass 27, count 2 2006.260.08:07:00.28#ibcon#about to read 6, iclass 27, count 2 2006.260.08:07:00.28#ibcon#read 6, iclass 27, count 2 2006.260.08:07:00.28#ibcon#end of sib2, iclass 27, count 2 2006.260.08:07:00.28#ibcon#*after write, iclass 27, count 2 2006.260.08:07:00.28#ibcon#*before return 0, iclass 27, count 2 2006.260.08:07:00.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:00.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:00.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:07:00.28#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:00.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:00.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:00.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:00.40#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:07:00.40#ibcon#first serial, iclass 27, count 0 2006.260.08:07:00.40#ibcon#enter sib2, iclass 27, count 0 2006.260.08:07:00.40#ibcon#flushed, iclass 27, count 0 2006.260.08:07:00.40#ibcon#about to write, iclass 27, count 0 2006.260.08:07:00.40#ibcon#wrote, iclass 27, count 0 2006.260.08:07:00.40#ibcon#about to read 3, iclass 27, count 0 2006.260.08:07:00.42#ibcon#read 3, iclass 27, count 0 2006.260.08:07:00.42#ibcon#about to read 4, iclass 27, count 0 2006.260.08:07:00.42#ibcon#read 4, iclass 27, count 0 2006.260.08:07:00.42#ibcon#about to read 5, iclass 27, count 0 2006.260.08:07:00.42#ibcon#read 5, iclass 27, count 0 2006.260.08:07:00.42#ibcon#about to read 6, iclass 27, count 0 2006.260.08:07:00.42#ibcon#read 6, iclass 27, count 0 2006.260.08:07:00.42#ibcon#end of sib2, iclass 27, count 0 2006.260.08:07:00.42#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:07:00.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:07:00.42#ibcon#[25=USB\r\n] 2006.260.08:07:00.42#ibcon#*before write, iclass 27, count 0 2006.260.08:07:00.42#ibcon#enter sib2, iclass 27, count 0 2006.260.08:07:00.42#ibcon#flushed, iclass 27, count 0 2006.260.08:07:00.42#ibcon#about to write, iclass 27, count 0 2006.260.08:07:00.42#ibcon#wrote, iclass 27, count 0 2006.260.08:07:00.42#ibcon#about to read 3, iclass 27, count 0 2006.260.08:07:00.45#ibcon#read 3, iclass 27, count 0 2006.260.08:07:00.45#ibcon#about to read 4, iclass 27, count 0 2006.260.08:07:00.45#ibcon#read 4, iclass 27, count 0 2006.260.08:07:00.45#ibcon#about to read 5, iclass 27, count 0 2006.260.08:07:00.45#ibcon#read 5, iclass 27, count 0 2006.260.08:07:00.45#ibcon#about to read 6, iclass 27, count 0 2006.260.08:07:00.45#ibcon#read 6, iclass 27, count 0 2006.260.08:07:00.45#ibcon#end of sib2, iclass 27, count 0 2006.260.08:07:00.45#ibcon#*after write, iclass 27, count 0 2006.260.08:07:00.45#ibcon#*before return 0, iclass 27, count 0 2006.260.08:07:00.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:00.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:00.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:07:00.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:07:00.45$vc4f8/valo=5,652.99 2006.260.08:07:00.45#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:07:00.45#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:07:00.45#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:00.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:00.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:00.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:00.45#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:07:00.45#ibcon#first serial, iclass 29, count 0 2006.260.08:07:00.45#ibcon#enter sib2, iclass 29, count 0 2006.260.08:07:00.45#ibcon#flushed, iclass 29, count 0 2006.260.08:07:00.45#ibcon#about to write, iclass 29, count 0 2006.260.08:07:00.45#ibcon#wrote, iclass 29, count 0 2006.260.08:07:00.45#ibcon#about to read 3, iclass 29, count 0 2006.260.08:07:00.47#ibcon#read 3, iclass 29, count 0 2006.260.08:07:00.47#ibcon#about to read 4, iclass 29, count 0 2006.260.08:07:00.47#ibcon#read 4, iclass 29, count 0 2006.260.08:07:00.47#ibcon#about to read 5, iclass 29, count 0 2006.260.08:07:00.47#ibcon#read 5, iclass 29, count 0 2006.260.08:07:00.47#ibcon#about to read 6, iclass 29, count 0 2006.260.08:07:00.47#ibcon#read 6, iclass 29, count 0 2006.260.08:07:00.47#ibcon#end of sib2, iclass 29, count 0 2006.260.08:07:00.47#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:07:00.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:07:00.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:07:00.47#ibcon#*before write, iclass 29, count 0 2006.260.08:07:00.47#ibcon#enter sib2, iclass 29, count 0 2006.260.08:07:00.47#ibcon#flushed, iclass 29, count 0 2006.260.08:07:00.47#ibcon#about to write, iclass 29, count 0 2006.260.08:07:00.47#ibcon#wrote, iclass 29, count 0 2006.260.08:07:00.47#ibcon#about to read 3, iclass 29, count 0 2006.260.08:07:00.51#ibcon#read 3, iclass 29, count 0 2006.260.08:07:00.51#ibcon#about to read 4, iclass 29, count 0 2006.260.08:07:00.51#ibcon#read 4, iclass 29, count 0 2006.260.08:07:00.51#ibcon#about to read 5, iclass 29, count 0 2006.260.08:07:00.51#ibcon#read 5, iclass 29, count 0 2006.260.08:07:00.51#ibcon#about to read 6, iclass 29, count 0 2006.260.08:07:00.51#ibcon#read 6, iclass 29, count 0 2006.260.08:07:00.51#ibcon#end of sib2, iclass 29, count 0 2006.260.08:07:00.51#ibcon#*after write, iclass 29, count 0 2006.260.08:07:00.51#ibcon#*before return 0, iclass 29, count 0 2006.260.08:07:00.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:00.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:00.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:07:00.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:07:00.51$vc4f8/va=5,7 2006.260.08:07:00.51#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:07:00.51#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:07:00.51#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:00.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:00.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:00.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:00.57#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:07:00.57#ibcon#first serial, iclass 31, count 2 2006.260.08:07:00.57#ibcon#enter sib2, iclass 31, count 2 2006.260.08:07:00.57#ibcon#flushed, iclass 31, count 2 2006.260.08:07:00.57#ibcon#about to write, iclass 31, count 2 2006.260.08:07:00.57#ibcon#wrote, iclass 31, count 2 2006.260.08:07:00.57#ibcon#about to read 3, iclass 31, count 2 2006.260.08:07:00.59#ibcon#read 3, iclass 31, count 2 2006.260.08:07:00.59#ibcon#about to read 4, iclass 31, count 2 2006.260.08:07:00.59#ibcon#read 4, iclass 31, count 2 2006.260.08:07:00.59#ibcon#about to read 5, iclass 31, count 2 2006.260.08:07:00.59#ibcon#read 5, iclass 31, count 2 2006.260.08:07:00.59#ibcon#about to read 6, iclass 31, count 2 2006.260.08:07:00.59#ibcon#read 6, iclass 31, count 2 2006.260.08:07:00.59#ibcon#end of sib2, iclass 31, count 2 2006.260.08:07:00.59#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:07:00.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:07:00.59#ibcon#[25=AT05-07\r\n] 2006.260.08:07:00.59#ibcon#*before write, iclass 31, count 2 2006.260.08:07:00.59#ibcon#enter sib2, iclass 31, count 2 2006.260.08:07:00.59#ibcon#flushed, iclass 31, count 2 2006.260.08:07:00.59#ibcon#about to write, iclass 31, count 2 2006.260.08:07:00.59#ibcon#wrote, iclass 31, count 2 2006.260.08:07:00.59#ibcon#about to read 3, iclass 31, count 2 2006.260.08:07:00.62#ibcon#read 3, iclass 31, count 2 2006.260.08:07:00.62#ibcon#about to read 4, iclass 31, count 2 2006.260.08:07:00.62#ibcon#read 4, iclass 31, count 2 2006.260.08:07:00.62#ibcon#about to read 5, iclass 31, count 2 2006.260.08:07:00.62#ibcon#read 5, iclass 31, count 2 2006.260.08:07:00.62#ibcon#about to read 6, iclass 31, count 2 2006.260.08:07:00.62#ibcon#read 6, iclass 31, count 2 2006.260.08:07:00.62#ibcon#end of sib2, iclass 31, count 2 2006.260.08:07:00.62#ibcon#*after write, iclass 31, count 2 2006.260.08:07:00.62#ibcon#*before return 0, iclass 31, count 2 2006.260.08:07:00.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:00.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:00.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:07:00.62#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:00.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:00.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:00.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:00.74#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:07:00.74#ibcon#first serial, iclass 31, count 0 2006.260.08:07:00.74#ibcon#enter sib2, iclass 31, count 0 2006.260.08:07:00.74#ibcon#flushed, iclass 31, count 0 2006.260.08:07:00.74#ibcon#about to write, iclass 31, count 0 2006.260.08:07:00.74#ibcon#wrote, iclass 31, count 0 2006.260.08:07:00.74#ibcon#about to read 3, iclass 31, count 0 2006.260.08:07:00.76#ibcon#read 3, iclass 31, count 0 2006.260.08:07:00.76#ibcon#about to read 4, iclass 31, count 0 2006.260.08:07:00.76#ibcon#read 4, iclass 31, count 0 2006.260.08:07:00.76#ibcon#about to read 5, iclass 31, count 0 2006.260.08:07:00.76#ibcon#read 5, iclass 31, count 0 2006.260.08:07:00.76#ibcon#about to read 6, iclass 31, count 0 2006.260.08:07:00.76#ibcon#read 6, iclass 31, count 0 2006.260.08:07:00.76#ibcon#end of sib2, iclass 31, count 0 2006.260.08:07:00.76#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:07:00.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:07:00.76#ibcon#[25=USB\r\n] 2006.260.08:07:00.76#ibcon#*before write, iclass 31, count 0 2006.260.08:07:00.76#ibcon#enter sib2, iclass 31, count 0 2006.260.08:07:00.76#ibcon#flushed, iclass 31, count 0 2006.260.08:07:00.76#ibcon#about to write, iclass 31, count 0 2006.260.08:07:00.76#ibcon#wrote, iclass 31, count 0 2006.260.08:07:00.76#ibcon#about to read 3, iclass 31, count 0 2006.260.08:07:00.79#ibcon#read 3, iclass 31, count 0 2006.260.08:07:00.79#ibcon#about to read 4, iclass 31, count 0 2006.260.08:07:00.79#ibcon#read 4, iclass 31, count 0 2006.260.08:07:00.79#ibcon#about to read 5, iclass 31, count 0 2006.260.08:07:00.79#ibcon#read 5, iclass 31, count 0 2006.260.08:07:00.79#ibcon#about to read 6, iclass 31, count 0 2006.260.08:07:00.79#ibcon#read 6, iclass 31, count 0 2006.260.08:07:00.79#ibcon#end of sib2, iclass 31, count 0 2006.260.08:07:00.79#ibcon#*after write, iclass 31, count 0 2006.260.08:07:00.79#ibcon#*before return 0, iclass 31, count 0 2006.260.08:07:00.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:00.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:00.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:07:00.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:07:00.79$vc4f8/valo=6,772.99 2006.260.08:07:00.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:07:00.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:07:00.79#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:00.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:00.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:00.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:00.79#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:07:00.79#ibcon#first serial, iclass 33, count 0 2006.260.08:07:00.79#ibcon#enter sib2, iclass 33, count 0 2006.260.08:07:00.79#ibcon#flushed, iclass 33, count 0 2006.260.08:07:00.79#ibcon#about to write, iclass 33, count 0 2006.260.08:07:00.79#ibcon#wrote, iclass 33, count 0 2006.260.08:07:00.79#ibcon#about to read 3, iclass 33, count 0 2006.260.08:07:00.81#ibcon#read 3, iclass 33, count 0 2006.260.08:07:00.81#ibcon#about to read 4, iclass 33, count 0 2006.260.08:07:00.81#ibcon#read 4, iclass 33, count 0 2006.260.08:07:00.81#ibcon#about to read 5, iclass 33, count 0 2006.260.08:07:00.81#ibcon#read 5, iclass 33, count 0 2006.260.08:07:00.81#ibcon#about to read 6, iclass 33, count 0 2006.260.08:07:00.81#ibcon#read 6, iclass 33, count 0 2006.260.08:07:00.81#ibcon#end of sib2, iclass 33, count 0 2006.260.08:07:00.81#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:07:00.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:07:00.81#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:07:00.81#ibcon#*before write, iclass 33, count 0 2006.260.08:07:00.81#ibcon#enter sib2, iclass 33, count 0 2006.260.08:07:00.81#ibcon#flushed, iclass 33, count 0 2006.260.08:07:00.81#ibcon#about to write, iclass 33, count 0 2006.260.08:07:00.81#ibcon#wrote, iclass 33, count 0 2006.260.08:07:00.81#ibcon#about to read 3, iclass 33, count 0 2006.260.08:07:00.85#ibcon#read 3, iclass 33, count 0 2006.260.08:07:00.85#ibcon#about to read 4, iclass 33, count 0 2006.260.08:07:00.85#ibcon#read 4, iclass 33, count 0 2006.260.08:07:00.85#ibcon#about to read 5, iclass 33, count 0 2006.260.08:07:00.85#ibcon#read 5, iclass 33, count 0 2006.260.08:07:00.85#ibcon#about to read 6, iclass 33, count 0 2006.260.08:07:00.85#ibcon#read 6, iclass 33, count 0 2006.260.08:07:00.85#ibcon#end of sib2, iclass 33, count 0 2006.260.08:07:00.85#ibcon#*after write, iclass 33, count 0 2006.260.08:07:00.85#ibcon#*before return 0, iclass 33, count 0 2006.260.08:07:00.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:00.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:00.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:07:00.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:07:00.85$vc4f8/va=6,6 2006.260.08:07:00.85#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:07:00.85#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:07:00.85#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:00.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:00.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:00.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:00.91#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:07:00.91#ibcon#first serial, iclass 35, count 2 2006.260.08:07:00.91#ibcon#enter sib2, iclass 35, count 2 2006.260.08:07:00.91#ibcon#flushed, iclass 35, count 2 2006.260.08:07:00.91#ibcon#about to write, iclass 35, count 2 2006.260.08:07:00.91#ibcon#wrote, iclass 35, count 2 2006.260.08:07:00.91#ibcon#about to read 3, iclass 35, count 2 2006.260.08:07:00.93#ibcon#read 3, iclass 35, count 2 2006.260.08:07:00.93#ibcon#about to read 4, iclass 35, count 2 2006.260.08:07:00.93#ibcon#read 4, iclass 35, count 2 2006.260.08:07:00.93#ibcon#about to read 5, iclass 35, count 2 2006.260.08:07:00.93#ibcon#read 5, iclass 35, count 2 2006.260.08:07:00.93#ibcon#about to read 6, iclass 35, count 2 2006.260.08:07:00.93#ibcon#read 6, iclass 35, count 2 2006.260.08:07:00.93#ibcon#end of sib2, iclass 35, count 2 2006.260.08:07:00.93#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:07:00.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:07:00.93#ibcon#[25=AT06-06\r\n] 2006.260.08:07:00.93#ibcon#*before write, iclass 35, count 2 2006.260.08:07:00.93#ibcon#enter sib2, iclass 35, count 2 2006.260.08:07:00.93#ibcon#flushed, iclass 35, count 2 2006.260.08:07:00.93#ibcon#about to write, iclass 35, count 2 2006.260.08:07:00.93#ibcon#wrote, iclass 35, count 2 2006.260.08:07:00.93#ibcon#about to read 3, iclass 35, count 2 2006.260.08:07:00.96#ibcon#read 3, iclass 35, count 2 2006.260.08:07:00.96#ibcon#about to read 4, iclass 35, count 2 2006.260.08:07:00.96#ibcon#read 4, iclass 35, count 2 2006.260.08:07:00.96#ibcon#about to read 5, iclass 35, count 2 2006.260.08:07:00.96#ibcon#read 5, iclass 35, count 2 2006.260.08:07:00.96#ibcon#about to read 6, iclass 35, count 2 2006.260.08:07:00.96#ibcon#read 6, iclass 35, count 2 2006.260.08:07:00.96#ibcon#end of sib2, iclass 35, count 2 2006.260.08:07:00.96#ibcon#*after write, iclass 35, count 2 2006.260.08:07:00.96#ibcon#*before return 0, iclass 35, count 2 2006.260.08:07:00.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:00.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:00.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:07:00.96#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:00.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:01.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:01.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:01.08#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:07:01.08#ibcon#first serial, iclass 35, count 0 2006.260.08:07:01.08#ibcon#enter sib2, iclass 35, count 0 2006.260.08:07:01.08#ibcon#flushed, iclass 35, count 0 2006.260.08:07:01.08#ibcon#about to write, iclass 35, count 0 2006.260.08:07:01.08#ibcon#wrote, iclass 35, count 0 2006.260.08:07:01.08#ibcon#about to read 3, iclass 35, count 0 2006.260.08:07:01.10#ibcon#read 3, iclass 35, count 0 2006.260.08:07:01.10#ibcon#about to read 4, iclass 35, count 0 2006.260.08:07:01.10#ibcon#read 4, iclass 35, count 0 2006.260.08:07:01.10#ibcon#about to read 5, iclass 35, count 0 2006.260.08:07:01.10#ibcon#read 5, iclass 35, count 0 2006.260.08:07:01.10#ibcon#about to read 6, iclass 35, count 0 2006.260.08:07:01.10#ibcon#read 6, iclass 35, count 0 2006.260.08:07:01.10#ibcon#end of sib2, iclass 35, count 0 2006.260.08:07:01.10#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:07:01.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:07:01.10#ibcon#[25=USB\r\n] 2006.260.08:07:01.10#ibcon#*before write, iclass 35, count 0 2006.260.08:07:01.10#ibcon#enter sib2, iclass 35, count 0 2006.260.08:07:01.10#ibcon#flushed, iclass 35, count 0 2006.260.08:07:01.10#ibcon#about to write, iclass 35, count 0 2006.260.08:07:01.10#ibcon#wrote, iclass 35, count 0 2006.260.08:07:01.10#ibcon#about to read 3, iclass 35, count 0 2006.260.08:07:01.13#ibcon#read 3, iclass 35, count 0 2006.260.08:07:01.13#ibcon#about to read 4, iclass 35, count 0 2006.260.08:07:01.13#ibcon#read 4, iclass 35, count 0 2006.260.08:07:01.13#ibcon#about to read 5, iclass 35, count 0 2006.260.08:07:01.13#ibcon#read 5, iclass 35, count 0 2006.260.08:07:01.13#ibcon#about to read 6, iclass 35, count 0 2006.260.08:07:01.13#ibcon#read 6, iclass 35, count 0 2006.260.08:07:01.13#ibcon#end of sib2, iclass 35, count 0 2006.260.08:07:01.13#ibcon#*after write, iclass 35, count 0 2006.260.08:07:01.13#ibcon#*before return 0, iclass 35, count 0 2006.260.08:07:01.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:01.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:01.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:07:01.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:07:01.13$vc4f8/valo=7,832.99 2006.260.08:07:01.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:07:01.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:07:01.13#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:01.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:01.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:01.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:01.13#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:07:01.13#ibcon#first serial, iclass 37, count 0 2006.260.08:07:01.13#ibcon#enter sib2, iclass 37, count 0 2006.260.08:07:01.13#ibcon#flushed, iclass 37, count 0 2006.260.08:07:01.13#ibcon#about to write, iclass 37, count 0 2006.260.08:07:01.13#ibcon#wrote, iclass 37, count 0 2006.260.08:07:01.13#ibcon#about to read 3, iclass 37, count 0 2006.260.08:07:01.15#ibcon#read 3, iclass 37, count 0 2006.260.08:07:01.15#ibcon#about to read 4, iclass 37, count 0 2006.260.08:07:01.15#ibcon#read 4, iclass 37, count 0 2006.260.08:07:01.15#ibcon#about to read 5, iclass 37, count 0 2006.260.08:07:01.15#ibcon#read 5, iclass 37, count 0 2006.260.08:07:01.15#ibcon#about to read 6, iclass 37, count 0 2006.260.08:07:01.15#ibcon#read 6, iclass 37, count 0 2006.260.08:07:01.15#ibcon#end of sib2, iclass 37, count 0 2006.260.08:07:01.15#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:07:01.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:07:01.15#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:07:01.15#ibcon#*before write, iclass 37, count 0 2006.260.08:07:01.15#ibcon#enter sib2, iclass 37, count 0 2006.260.08:07:01.15#ibcon#flushed, iclass 37, count 0 2006.260.08:07:01.15#ibcon#about to write, iclass 37, count 0 2006.260.08:07:01.15#ibcon#wrote, iclass 37, count 0 2006.260.08:07:01.15#ibcon#about to read 3, iclass 37, count 0 2006.260.08:07:01.19#ibcon#read 3, iclass 37, count 0 2006.260.08:07:01.19#ibcon#about to read 4, iclass 37, count 0 2006.260.08:07:01.19#ibcon#read 4, iclass 37, count 0 2006.260.08:07:01.19#ibcon#about to read 5, iclass 37, count 0 2006.260.08:07:01.19#ibcon#read 5, iclass 37, count 0 2006.260.08:07:01.19#ibcon#about to read 6, iclass 37, count 0 2006.260.08:07:01.19#ibcon#read 6, iclass 37, count 0 2006.260.08:07:01.19#ibcon#end of sib2, iclass 37, count 0 2006.260.08:07:01.19#ibcon#*after write, iclass 37, count 0 2006.260.08:07:01.19#ibcon#*before return 0, iclass 37, count 0 2006.260.08:07:01.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:01.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:01.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:07:01.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:07:01.19$vc4f8/va=7,6 2006.260.08:07:01.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.08:07:01.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.08:07:01.19#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:01.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:01.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:01.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:01.25#ibcon#enter wrdev, iclass 39, count 2 2006.260.08:07:01.25#ibcon#first serial, iclass 39, count 2 2006.260.08:07:01.25#ibcon#enter sib2, iclass 39, count 2 2006.260.08:07:01.25#ibcon#flushed, iclass 39, count 2 2006.260.08:07:01.25#ibcon#about to write, iclass 39, count 2 2006.260.08:07:01.25#ibcon#wrote, iclass 39, count 2 2006.260.08:07:01.25#ibcon#about to read 3, iclass 39, count 2 2006.260.08:07:01.27#ibcon#read 3, iclass 39, count 2 2006.260.08:07:01.27#ibcon#about to read 4, iclass 39, count 2 2006.260.08:07:01.27#ibcon#read 4, iclass 39, count 2 2006.260.08:07:01.27#ibcon#about to read 5, iclass 39, count 2 2006.260.08:07:01.27#ibcon#read 5, iclass 39, count 2 2006.260.08:07:01.27#ibcon#about to read 6, iclass 39, count 2 2006.260.08:07:01.27#ibcon#read 6, iclass 39, count 2 2006.260.08:07:01.27#ibcon#end of sib2, iclass 39, count 2 2006.260.08:07:01.27#ibcon#*mode == 0, iclass 39, count 2 2006.260.08:07:01.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.08:07:01.27#ibcon#[25=AT07-06\r\n] 2006.260.08:07:01.27#ibcon#*before write, iclass 39, count 2 2006.260.08:07:01.27#ibcon#enter sib2, iclass 39, count 2 2006.260.08:07:01.27#ibcon#flushed, iclass 39, count 2 2006.260.08:07:01.27#ibcon#about to write, iclass 39, count 2 2006.260.08:07:01.27#ibcon#wrote, iclass 39, count 2 2006.260.08:07:01.27#ibcon#about to read 3, iclass 39, count 2 2006.260.08:07:01.30#ibcon#read 3, iclass 39, count 2 2006.260.08:07:01.30#ibcon#about to read 4, iclass 39, count 2 2006.260.08:07:01.30#ibcon#read 4, iclass 39, count 2 2006.260.08:07:01.30#ibcon#about to read 5, iclass 39, count 2 2006.260.08:07:01.30#ibcon#read 5, iclass 39, count 2 2006.260.08:07:01.30#ibcon#about to read 6, iclass 39, count 2 2006.260.08:07:01.30#ibcon#read 6, iclass 39, count 2 2006.260.08:07:01.30#ibcon#end of sib2, iclass 39, count 2 2006.260.08:07:01.30#ibcon#*after write, iclass 39, count 2 2006.260.08:07:01.30#ibcon#*before return 0, iclass 39, count 2 2006.260.08:07:01.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:01.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:01.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.08:07:01.30#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:01.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:07:01.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:07:01.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:07:01.42#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:07:01.42#ibcon#first serial, iclass 39, count 0 2006.260.08:07:01.42#ibcon#enter sib2, iclass 39, count 0 2006.260.08:07:01.42#ibcon#flushed, iclass 39, count 0 2006.260.08:07:01.42#ibcon#about to write, iclass 39, count 0 2006.260.08:07:01.42#ibcon#wrote, iclass 39, count 0 2006.260.08:07:01.42#ibcon#about to read 3, iclass 39, count 0 2006.260.08:07:01.44#ibcon#read 3, iclass 39, count 0 2006.260.08:07:01.44#ibcon#about to read 4, iclass 39, count 0 2006.260.08:07:01.44#ibcon#read 4, iclass 39, count 0 2006.260.08:07:01.44#ibcon#about to read 5, iclass 39, count 0 2006.260.08:07:01.44#ibcon#read 5, iclass 39, count 0 2006.260.08:07:01.44#ibcon#about to read 6, iclass 39, count 0 2006.260.08:07:01.44#ibcon#read 6, iclass 39, count 0 2006.260.08:07:01.44#ibcon#end of sib2, iclass 39, count 0 2006.260.08:07:01.44#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:07:01.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:07:01.44#ibcon#[25=USB\r\n] 2006.260.08:07:01.44#ibcon#*before write, iclass 39, count 0 2006.260.08:07:01.44#ibcon#enter sib2, iclass 39, count 0 2006.260.08:07:01.44#ibcon#flushed, iclass 39, count 0 2006.260.08:07:01.44#ibcon#about to write, iclass 39, count 0 2006.260.08:07:01.44#ibcon#wrote, iclass 39, count 0 2006.260.08:07:01.44#ibcon#about to read 3, iclass 39, count 0 2006.260.08:07:01.46#abcon#<5=/03 3.4 7.0 22.81 891010.4\r\n> 2006.260.08:07:01.47#ibcon#read 3, iclass 39, count 0 2006.260.08:07:01.47#ibcon#about to read 4, iclass 39, count 0 2006.260.08:07:01.47#ibcon#read 4, iclass 39, count 0 2006.260.08:07:01.47#ibcon#about to read 5, iclass 39, count 0 2006.260.08:07:01.47#ibcon#read 5, iclass 39, count 0 2006.260.08:07:01.47#ibcon#about to read 6, iclass 39, count 0 2006.260.08:07:01.47#ibcon#read 6, iclass 39, count 0 2006.260.08:07:01.47#ibcon#end of sib2, iclass 39, count 0 2006.260.08:07:01.47#ibcon#*after write, iclass 39, count 0 2006.260.08:07:01.47#ibcon#*before return 0, iclass 39, count 0 2006.260.08:07:01.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:07:01.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:07:01.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:07:01.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:07:01.47$vc4f8/valo=8,852.99 2006.260.08:07:01.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:07:01.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:07:01.47#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:01.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:07:01.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:07:01.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:07:01.47#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:07:01.47#ibcon#first serial, iclass 6, count 0 2006.260.08:07:01.47#ibcon#enter sib2, iclass 6, count 0 2006.260.08:07:01.47#ibcon#flushed, iclass 6, count 0 2006.260.08:07:01.47#ibcon#about to write, iclass 6, count 0 2006.260.08:07:01.47#ibcon#wrote, iclass 6, count 0 2006.260.08:07:01.47#ibcon#about to read 3, iclass 6, count 0 2006.260.08:07:01.48#abcon#{5=INTERFACE CLEAR} 2006.260.08:07:01.49#ibcon#read 3, iclass 6, count 0 2006.260.08:07:01.49#ibcon#about to read 4, iclass 6, count 0 2006.260.08:07:01.49#ibcon#read 4, iclass 6, count 0 2006.260.08:07:01.49#ibcon#about to read 5, iclass 6, count 0 2006.260.08:07:01.49#ibcon#read 5, iclass 6, count 0 2006.260.08:07:01.49#ibcon#about to read 6, iclass 6, count 0 2006.260.08:07:01.49#ibcon#read 6, iclass 6, count 0 2006.260.08:07:01.49#ibcon#end of sib2, iclass 6, count 0 2006.260.08:07:01.49#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:07:01.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:07:01.49#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:07:01.49#ibcon#*before write, iclass 6, count 0 2006.260.08:07:01.49#ibcon#enter sib2, iclass 6, count 0 2006.260.08:07:01.49#ibcon#flushed, iclass 6, count 0 2006.260.08:07:01.49#ibcon#about to write, iclass 6, count 0 2006.260.08:07:01.49#ibcon#wrote, iclass 6, count 0 2006.260.08:07:01.49#ibcon#about to read 3, iclass 6, count 0 2006.260.08:07:01.53#ibcon#read 3, iclass 6, count 0 2006.260.08:07:01.53#ibcon#about to read 4, iclass 6, count 0 2006.260.08:07:01.53#ibcon#read 4, iclass 6, count 0 2006.260.08:07:01.53#ibcon#about to read 5, iclass 6, count 0 2006.260.08:07:01.53#ibcon#read 5, iclass 6, count 0 2006.260.08:07:01.53#ibcon#about to read 6, iclass 6, count 0 2006.260.08:07:01.53#ibcon#read 6, iclass 6, count 0 2006.260.08:07:01.53#ibcon#end of sib2, iclass 6, count 0 2006.260.08:07:01.53#ibcon#*after write, iclass 6, count 0 2006.260.08:07:01.53#ibcon#*before return 0, iclass 6, count 0 2006.260.08:07:01.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:07:01.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:07:01.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:07:01.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:07:01.53$vc4f8/va=8,6 2006.260.08:07:01.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:07:01.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:07:01.53#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:01.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:07:01.54#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:07:01.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:07:01.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:07:01.59#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:07:01.59#ibcon#first serial, iclass 11, count 2 2006.260.08:07:01.59#ibcon#enter sib2, iclass 11, count 2 2006.260.08:07:01.59#ibcon#flushed, iclass 11, count 2 2006.260.08:07:01.59#ibcon#about to write, iclass 11, count 2 2006.260.08:07:01.59#ibcon#wrote, iclass 11, count 2 2006.260.08:07:01.59#ibcon#about to read 3, iclass 11, count 2 2006.260.08:07:01.61#ibcon#read 3, iclass 11, count 2 2006.260.08:07:01.61#ibcon#about to read 4, iclass 11, count 2 2006.260.08:07:01.61#ibcon#read 4, iclass 11, count 2 2006.260.08:07:01.61#ibcon#about to read 5, iclass 11, count 2 2006.260.08:07:01.61#ibcon#read 5, iclass 11, count 2 2006.260.08:07:01.61#ibcon#about to read 6, iclass 11, count 2 2006.260.08:07:01.61#ibcon#read 6, iclass 11, count 2 2006.260.08:07:01.61#ibcon#end of sib2, iclass 11, count 2 2006.260.08:07:01.61#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:07:01.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:07:01.61#ibcon#[25=AT08-06\r\n] 2006.260.08:07:01.61#ibcon#*before write, iclass 11, count 2 2006.260.08:07:01.61#ibcon#enter sib2, iclass 11, count 2 2006.260.08:07:01.61#ibcon#flushed, iclass 11, count 2 2006.260.08:07:01.61#ibcon#about to write, iclass 11, count 2 2006.260.08:07:01.61#ibcon#wrote, iclass 11, count 2 2006.260.08:07:01.61#ibcon#about to read 3, iclass 11, count 2 2006.260.08:07:01.64#ibcon#read 3, iclass 11, count 2 2006.260.08:07:01.64#ibcon#about to read 4, iclass 11, count 2 2006.260.08:07:01.64#ibcon#read 4, iclass 11, count 2 2006.260.08:07:01.64#ibcon#about to read 5, iclass 11, count 2 2006.260.08:07:01.64#ibcon#read 5, iclass 11, count 2 2006.260.08:07:01.64#ibcon#about to read 6, iclass 11, count 2 2006.260.08:07:01.64#ibcon#read 6, iclass 11, count 2 2006.260.08:07:01.64#ibcon#end of sib2, iclass 11, count 2 2006.260.08:07:01.64#ibcon#*after write, iclass 11, count 2 2006.260.08:07:01.64#ibcon#*before return 0, iclass 11, count 2 2006.260.08:07:01.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:07:01.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:07:01.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:07:01.64#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:01.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:07:01.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:07:01.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:07:01.76#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:07:01.76#ibcon#first serial, iclass 11, count 0 2006.260.08:07:01.76#ibcon#enter sib2, iclass 11, count 0 2006.260.08:07:01.76#ibcon#flushed, iclass 11, count 0 2006.260.08:07:01.76#ibcon#about to write, iclass 11, count 0 2006.260.08:07:01.76#ibcon#wrote, iclass 11, count 0 2006.260.08:07:01.76#ibcon#about to read 3, iclass 11, count 0 2006.260.08:07:01.78#ibcon#read 3, iclass 11, count 0 2006.260.08:07:01.78#ibcon#about to read 4, iclass 11, count 0 2006.260.08:07:01.78#ibcon#read 4, iclass 11, count 0 2006.260.08:07:01.78#ibcon#about to read 5, iclass 11, count 0 2006.260.08:07:01.78#ibcon#read 5, iclass 11, count 0 2006.260.08:07:01.78#ibcon#about to read 6, iclass 11, count 0 2006.260.08:07:01.78#ibcon#read 6, iclass 11, count 0 2006.260.08:07:01.78#ibcon#end of sib2, iclass 11, count 0 2006.260.08:07:01.78#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:07:01.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:07:01.78#ibcon#[25=USB\r\n] 2006.260.08:07:01.78#ibcon#*before write, iclass 11, count 0 2006.260.08:07:01.78#ibcon#enter sib2, iclass 11, count 0 2006.260.08:07:01.78#ibcon#flushed, iclass 11, count 0 2006.260.08:07:01.78#ibcon#about to write, iclass 11, count 0 2006.260.08:07:01.78#ibcon#wrote, iclass 11, count 0 2006.260.08:07:01.78#ibcon#about to read 3, iclass 11, count 0 2006.260.08:07:01.81#ibcon#read 3, iclass 11, count 0 2006.260.08:07:01.81#ibcon#about to read 4, iclass 11, count 0 2006.260.08:07:01.81#ibcon#read 4, iclass 11, count 0 2006.260.08:07:01.81#ibcon#about to read 5, iclass 11, count 0 2006.260.08:07:01.81#ibcon#read 5, iclass 11, count 0 2006.260.08:07:01.81#ibcon#about to read 6, iclass 11, count 0 2006.260.08:07:01.81#ibcon#read 6, iclass 11, count 0 2006.260.08:07:01.81#ibcon#end of sib2, iclass 11, count 0 2006.260.08:07:01.81#ibcon#*after write, iclass 11, count 0 2006.260.08:07:01.81#ibcon#*before return 0, iclass 11, count 0 2006.260.08:07:01.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:07:01.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:07:01.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:07:01.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:07:01.81$vc4f8/vblo=1,632.99 2006.260.08:07:01.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:07:01.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:07:01.81#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:01.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:07:01.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:07:01.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:07:01.81#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:07:01.81#ibcon#first serial, iclass 13, count 0 2006.260.08:07:01.81#ibcon#enter sib2, iclass 13, count 0 2006.260.08:07:01.81#ibcon#flushed, iclass 13, count 0 2006.260.08:07:01.81#ibcon#about to write, iclass 13, count 0 2006.260.08:07:01.81#ibcon#wrote, iclass 13, count 0 2006.260.08:07:01.81#ibcon#about to read 3, iclass 13, count 0 2006.260.08:07:01.83#ibcon#read 3, iclass 13, count 0 2006.260.08:07:01.83#ibcon#about to read 4, iclass 13, count 0 2006.260.08:07:01.83#ibcon#read 4, iclass 13, count 0 2006.260.08:07:01.83#ibcon#about to read 5, iclass 13, count 0 2006.260.08:07:01.83#ibcon#read 5, iclass 13, count 0 2006.260.08:07:01.83#ibcon#about to read 6, iclass 13, count 0 2006.260.08:07:01.83#ibcon#read 6, iclass 13, count 0 2006.260.08:07:01.83#ibcon#end of sib2, iclass 13, count 0 2006.260.08:07:01.83#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:07:01.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:07:01.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:07:01.83#ibcon#*before write, iclass 13, count 0 2006.260.08:07:01.83#ibcon#enter sib2, iclass 13, count 0 2006.260.08:07:01.83#ibcon#flushed, iclass 13, count 0 2006.260.08:07:01.83#ibcon#about to write, iclass 13, count 0 2006.260.08:07:01.83#ibcon#wrote, iclass 13, count 0 2006.260.08:07:01.83#ibcon#about to read 3, iclass 13, count 0 2006.260.08:07:01.87#ibcon#read 3, iclass 13, count 0 2006.260.08:07:01.87#ibcon#about to read 4, iclass 13, count 0 2006.260.08:07:01.87#ibcon#read 4, iclass 13, count 0 2006.260.08:07:01.87#ibcon#about to read 5, iclass 13, count 0 2006.260.08:07:01.87#ibcon#read 5, iclass 13, count 0 2006.260.08:07:01.87#ibcon#about to read 6, iclass 13, count 0 2006.260.08:07:01.87#ibcon#read 6, iclass 13, count 0 2006.260.08:07:01.87#ibcon#end of sib2, iclass 13, count 0 2006.260.08:07:01.87#ibcon#*after write, iclass 13, count 0 2006.260.08:07:01.87#ibcon#*before return 0, iclass 13, count 0 2006.260.08:07:01.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:07:01.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:07:01.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:07:01.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:07:01.87$vc4f8/vb=1,4 2006.260.08:07:01.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:07:01.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:07:01.87#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:01.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:07:01.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:07:01.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:07:01.87#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:07:01.87#ibcon#first serial, iclass 15, count 2 2006.260.08:07:01.87#ibcon#enter sib2, iclass 15, count 2 2006.260.08:07:01.87#ibcon#flushed, iclass 15, count 2 2006.260.08:07:01.87#ibcon#about to write, iclass 15, count 2 2006.260.08:07:01.87#ibcon#wrote, iclass 15, count 2 2006.260.08:07:01.87#ibcon#about to read 3, iclass 15, count 2 2006.260.08:07:01.89#ibcon#read 3, iclass 15, count 2 2006.260.08:07:01.89#ibcon#about to read 4, iclass 15, count 2 2006.260.08:07:01.89#ibcon#read 4, iclass 15, count 2 2006.260.08:07:01.89#ibcon#about to read 5, iclass 15, count 2 2006.260.08:07:01.89#ibcon#read 5, iclass 15, count 2 2006.260.08:07:01.89#ibcon#about to read 6, iclass 15, count 2 2006.260.08:07:01.89#ibcon#read 6, iclass 15, count 2 2006.260.08:07:01.89#ibcon#end of sib2, iclass 15, count 2 2006.260.08:07:01.89#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:07:01.89#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:07:01.89#ibcon#[27=AT01-04\r\n] 2006.260.08:07:01.89#ibcon#*before write, iclass 15, count 2 2006.260.08:07:01.89#ibcon#enter sib2, iclass 15, count 2 2006.260.08:07:01.89#ibcon#flushed, iclass 15, count 2 2006.260.08:07:01.89#ibcon#about to write, iclass 15, count 2 2006.260.08:07:01.89#ibcon#wrote, iclass 15, count 2 2006.260.08:07:01.89#ibcon#about to read 3, iclass 15, count 2 2006.260.08:07:01.92#ibcon#read 3, iclass 15, count 2 2006.260.08:07:01.92#ibcon#about to read 4, iclass 15, count 2 2006.260.08:07:01.92#ibcon#read 4, iclass 15, count 2 2006.260.08:07:01.92#ibcon#about to read 5, iclass 15, count 2 2006.260.08:07:01.92#ibcon#read 5, iclass 15, count 2 2006.260.08:07:01.92#ibcon#about to read 6, iclass 15, count 2 2006.260.08:07:01.92#ibcon#read 6, iclass 15, count 2 2006.260.08:07:01.92#ibcon#end of sib2, iclass 15, count 2 2006.260.08:07:01.92#ibcon#*after write, iclass 15, count 2 2006.260.08:07:01.92#ibcon#*before return 0, iclass 15, count 2 2006.260.08:07:01.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:07:01.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:07:01.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:07:01.92#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:01.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:07:02.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:07:02.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:07:02.04#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:07:02.04#ibcon#first serial, iclass 15, count 0 2006.260.08:07:02.04#ibcon#enter sib2, iclass 15, count 0 2006.260.08:07:02.04#ibcon#flushed, iclass 15, count 0 2006.260.08:07:02.04#ibcon#about to write, iclass 15, count 0 2006.260.08:07:02.04#ibcon#wrote, iclass 15, count 0 2006.260.08:07:02.04#ibcon#about to read 3, iclass 15, count 0 2006.260.08:07:02.07#ibcon#read 3, iclass 15, count 0 2006.260.08:07:02.07#ibcon#about to read 4, iclass 15, count 0 2006.260.08:07:02.07#ibcon#read 4, iclass 15, count 0 2006.260.08:07:02.07#ibcon#about to read 5, iclass 15, count 0 2006.260.08:07:02.07#ibcon#read 5, iclass 15, count 0 2006.260.08:07:02.07#ibcon#about to read 6, iclass 15, count 0 2006.260.08:07:02.07#ibcon#read 6, iclass 15, count 0 2006.260.08:07:02.07#ibcon#end of sib2, iclass 15, count 0 2006.260.08:07:02.07#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:07:02.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:07:02.07#ibcon#[27=USB\r\n] 2006.260.08:07:02.07#ibcon#*before write, iclass 15, count 0 2006.260.08:07:02.07#ibcon#enter sib2, iclass 15, count 0 2006.260.08:07:02.07#ibcon#flushed, iclass 15, count 0 2006.260.08:07:02.07#ibcon#about to write, iclass 15, count 0 2006.260.08:07:02.07#ibcon#wrote, iclass 15, count 0 2006.260.08:07:02.07#ibcon#about to read 3, iclass 15, count 0 2006.260.08:07:02.10#ibcon#read 3, iclass 15, count 0 2006.260.08:07:02.10#ibcon#about to read 4, iclass 15, count 0 2006.260.08:07:02.10#ibcon#read 4, iclass 15, count 0 2006.260.08:07:02.10#ibcon#about to read 5, iclass 15, count 0 2006.260.08:07:02.10#ibcon#read 5, iclass 15, count 0 2006.260.08:07:02.10#ibcon#about to read 6, iclass 15, count 0 2006.260.08:07:02.10#ibcon#read 6, iclass 15, count 0 2006.260.08:07:02.10#ibcon#end of sib2, iclass 15, count 0 2006.260.08:07:02.10#ibcon#*after write, iclass 15, count 0 2006.260.08:07:02.10#ibcon#*before return 0, iclass 15, count 0 2006.260.08:07:02.10#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:07:02.10#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:07:02.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:07:02.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:07:02.10$vc4f8/vblo=2,640.99 2006.260.08:07:02.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.08:07:02.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.08:07:02.10#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:02.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:07:02.10#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:07:02.10#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:07:02.10#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:07:02.10#ibcon#first serial, iclass 17, count 0 2006.260.08:07:02.10#ibcon#enter sib2, iclass 17, count 0 2006.260.08:07:02.10#ibcon#flushed, iclass 17, count 0 2006.260.08:07:02.10#ibcon#about to write, iclass 17, count 0 2006.260.08:07:02.10#ibcon#wrote, iclass 17, count 0 2006.260.08:07:02.10#ibcon#about to read 3, iclass 17, count 0 2006.260.08:07:02.12#ibcon#read 3, iclass 17, count 0 2006.260.08:07:02.12#ibcon#about to read 4, iclass 17, count 0 2006.260.08:07:02.12#ibcon#read 4, iclass 17, count 0 2006.260.08:07:02.12#ibcon#about to read 5, iclass 17, count 0 2006.260.08:07:02.12#ibcon#read 5, iclass 17, count 0 2006.260.08:07:02.12#ibcon#about to read 6, iclass 17, count 0 2006.260.08:07:02.12#ibcon#read 6, iclass 17, count 0 2006.260.08:07:02.12#ibcon#end of sib2, iclass 17, count 0 2006.260.08:07:02.12#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:07:02.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:07:02.12#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:07:02.12#ibcon#*before write, iclass 17, count 0 2006.260.08:07:02.12#ibcon#enter sib2, iclass 17, count 0 2006.260.08:07:02.12#ibcon#flushed, iclass 17, count 0 2006.260.08:07:02.12#ibcon#about to write, iclass 17, count 0 2006.260.08:07:02.12#ibcon#wrote, iclass 17, count 0 2006.260.08:07:02.12#ibcon#about to read 3, iclass 17, count 0 2006.260.08:07:02.16#ibcon#read 3, iclass 17, count 0 2006.260.08:07:02.16#ibcon#about to read 4, iclass 17, count 0 2006.260.08:07:02.16#ibcon#read 4, iclass 17, count 0 2006.260.08:07:02.16#ibcon#about to read 5, iclass 17, count 0 2006.260.08:07:02.16#ibcon#read 5, iclass 17, count 0 2006.260.08:07:02.16#ibcon#about to read 6, iclass 17, count 0 2006.260.08:07:02.16#ibcon#read 6, iclass 17, count 0 2006.260.08:07:02.16#ibcon#end of sib2, iclass 17, count 0 2006.260.08:07:02.16#ibcon#*after write, iclass 17, count 0 2006.260.08:07:02.16#ibcon#*before return 0, iclass 17, count 0 2006.260.08:07:02.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:07:02.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:07:02.16#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:07:02.16#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:07:02.16$vc4f8/vb=2,5 2006.260.08:07:02.16#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.08:07:02.16#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.08:07:02.16#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:02.16#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:07:02.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:07:02.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:07:02.22#ibcon#enter wrdev, iclass 19, count 2 2006.260.08:07:02.22#ibcon#first serial, iclass 19, count 2 2006.260.08:07:02.22#ibcon#enter sib2, iclass 19, count 2 2006.260.08:07:02.22#ibcon#flushed, iclass 19, count 2 2006.260.08:07:02.22#ibcon#about to write, iclass 19, count 2 2006.260.08:07:02.22#ibcon#wrote, iclass 19, count 2 2006.260.08:07:02.22#ibcon#about to read 3, iclass 19, count 2 2006.260.08:07:02.24#ibcon#read 3, iclass 19, count 2 2006.260.08:07:02.24#ibcon#about to read 4, iclass 19, count 2 2006.260.08:07:02.24#ibcon#read 4, iclass 19, count 2 2006.260.08:07:02.24#ibcon#about to read 5, iclass 19, count 2 2006.260.08:07:02.24#ibcon#read 5, iclass 19, count 2 2006.260.08:07:02.24#ibcon#about to read 6, iclass 19, count 2 2006.260.08:07:02.24#ibcon#read 6, iclass 19, count 2 2006.260.08:07:02.24#ibcon#end of sib2, iclass 19, count 2 2006.260.08:07:02.24#ibcon#*mode == 0, iclass 19, count 2 2006.260.08:07:02.24#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.08:07:02.24#ibcon#[27=AT02-05\r\n] 2006.260.08:07:02.24#ibcon#*before write, iclass 19, count 2 2006.260.08:07:02.24#ibcon#enter sib2, iclass 19, count 2 2006.260.08:07:02.24#ibcon#flushed, iclass 19, count 2 2006.260.08:07:02.24#ibcon#about to write, iclass 19, count 2 2006.260.08:07:02.24#ibcon#wrote, iclass 19, count 2 2006.260.08:07:02.24#ibcon#about to read 3, iclass 19, count 2 2006.260.08:07:02.27#ibcon#read 3, iclass 19, count 2 2006.260.08:07:02.27#ibcon#about to read 4, iclass 19, count 2 2006.260.08:07:02.27#ibcon#read 4, iclass 19, count 2 2006.260.08:07:02.27#ibcon#about to read 5, iclass 19, count 2 2006.260.08:07:02.27#ibcon#read 5, iclass 19, count 2 2006.260.08:07:02.27#ibcon#about to read 6, iclass 19, count 2 2006.260.08:07:02.27#ibcon#read 6, iclass 19, count 2 2006.260.08:07:02.27#ibcon#end of sib2, iclass 19, count 2 2006.260.08:07:02.27#ibcon#*after write, iclass 19, count 2 2006.260.08:07:02.27#ibcon#*before return 0, iclass 19, count 2 2006.260.08:07:02.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:07:02.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:07:02.27#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.08:07:02.27#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:02.27#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:07:02.39#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:07:02.39#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:07:02.39#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:07:02.39#ibcon#first serial, iclass 19, count 0 2006.260.08:07:02.39#ibcon#enter sib2, iclass 19, count 0 2006.260.08:07:02.39#ibcon#flushed, iclass 19, count 0 2006.260.08:07:02.39#ibcon#about to write, iclass 19, count 0 2006.260.08:07:02.39#ibcon#wrote, iclass 19, count 0 2006.260.08:07:02.39#ibcon#about to read 3, iclass 19, count 0 2006.260.08:07:02.41#ibcon#read 3, iclass 19, count 0 2006.260.08:07:02.41#ibcon#about to read 4, iclass 19, count 0 2006.260.08:07:02.41#ibcon#read 4, iclass 19, count 0 2006.260.08:07:02.41#ibcon#about to read 5, iclass 19, count 0 2006.260.08:07:02.41#ibcon#read 5, iclass 19, count 0 2006.260.08:07:02.41#ibcon#about to read 6, iclass 19, count 0 2006.260.08:07:02.41#ibcon#read 6, iclass 19, count 0 2006.260.08:07:02.41#ibcon#end of sib2, iclass 19, count 0 2006.260.08:07:02.41#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:07:02.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:07:02.41#ibcon#[27=USB\r\n] 2006.260.08:07:02.41#ibcon#*before write, iclass 19, count 0 2006.260.08:07:02.41#ibcon#enter sib2, iclass 19, count 0 2006.260.08:07:02.41#ibcon#flushed, iclass 19, count 0 2006.260.08:07:02.41#ibcon#about to write, iclass 19, count 0 2006.260.08:07:02.41#ibcon#wrote, iclass 19, count 0 2006.260.08:07:02.41#ibcon#about to read 3, iclass 19, count 0 2006.260.08:07:02.44#ibcon#read 3, iclass 19, count 0 2006.260.08:07:02.44#ibcon#about to read 4, iclass 19, count 0 2006.260.08:07:02.44#ibcon#read 4, iclass 19, count 0 2006.260.08:07:02.44#ibcon#about to read 5, iclass 19, count 0 2006.260.08:07:02.44#ibcon#read 5, iclass 19, count 0 2006.260.08:07:02.44#ibcon#about to read 6, iclass 19, count 0 2006.260.08:07:02.44#ibcon#read 6, iclass 19, count 0 2006.260.08:07:02.44#ibcon#end of sib2, iclass 19, count 0 2006.260.08:07:02.44#ibcon#*after write, iclass 19, count 0 2006.260.08:07:02.44#ibcon#*before return 0, iclass 19, count 0 2006.260.08:07:02.44#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:07:02.44#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:07:02.44#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:07:02.44#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:07:02.44$vc4f8/vblo=3,656.99 2006.260.08:07:02.44#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:07:02.44#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:07:02.44#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:02.44#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:07:02.44#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:07:02.44#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:07:02.44#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:07:02.44#ibcon#first serial, iclass 21, count 0 2006.260.08:07:02.44#ibcon#enter sib2, iclass 21, count 0 2006.260.08:07:02.44#ibcon#flushed, iclass 21, count 0 2006.260.08:07:02.44#ibcon#about to write, iclass 21, count 0 2006.260.08:07:02.44#ibcon#wrote, iclass 21, count 0 2006.260.08:07:02.44#ibcon#about to read 3, iclass 21, count 0 2006.260.08:07:02.46#ibcon#read 3, iclass 21, count 0 2006.260.08:07:02.46#ibcon#about to read 4, iclass 21, count 0 2006.260.08:07:02.46#ibcon#read 4, iclass 21, count 0 2006.260.08:07:02.46#ibcon#about to read 5, iclass 21, count 0 2006.260.08:07:02.46#ibcon#read 5, iclass 21, count 0 2006.260.08:07:02.46#ibcon#about to read 6, iclass 21, count 0 2006.260.08:07:02.46#ibcon#read 6, iclass 21, count 0 2006.260.08:07:02.46#ibcon#end of sib2, iclass 21, count 0 2006.260.08:07:02.46#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:07:02.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:07:02.46#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:07:02.46#ibcon#*before write, iclass 21, count 0 2006.260.08:07:02.46#ibcon#enter sib2, iclass 21, count 0 2006.260.08:07:02.46#ibcon#flushed, iclass 21, count 0 2006.260.08:07:02.46#ibcon#about to write, iclass 21, count 0 2006.260.08:07:02.46#ibcon#wrote, iclass 21, count 0 2006.260.08:07:02.46#ibcon#about to read 3, iclass 21, count 0 2006.260.08:07:02.50#ibcon#read 3, iclass 21, count 0 2006.260.08:07:02.50#ibcon#about to read 4, iclass 21, count 0 2006.260.08:07:02.50#ibcon#read 4, iclass 21, count 0 2006.260.08:07:02.50#ibcon#about to read 5, iclass 21, count 0 2006.260.08:07:02.50#ibcon#read 5, iclass 21, count 0 2006.260.08:07:02.50#ibcon#about to read 6, iclass 21, count 0 2006.260.08:07:02.50#ibcon#read 6, iclass 21, count 0 2006.260.08:07:02.50#ibcon#end of sib2, iclass 21, count 0 2006.260.08:07:02.50#ibcon#*after write, iclass 21, count 0 2006.260.08:07:02.50#ibcon#*before return 0, iclass 21, count 0 2006.260.08:07:02.50#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:07:02.50#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:07:02.50#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:07:02.50#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:07:02.50$vc4f8/vb=3,4 2006.260.08:07:02.50#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:07:02.50#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:07:02.50#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:02.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:07:02.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:07:02.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:07:02.56#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:07:02.56#ibcon#first serial, iclass 23, count 2 2006.260.08:07:02.56#ibcon#enter sib2, iclass 23, count 2 2006.260.08:07:02.56#ibcon#flushed, iclass 23, count 2 2006.260.08:07:02.56#ibcon#about to write, iclass 23, count 2 2006.260.08:07:02.56#ibcon#wrote, iclass 23, count 2 2006.260.08:07:02.56#ibcon#about to read 3, iclass 23, count 2 2006.260.08:07:02.58#ibcon#read 3, iclass 23, count 2 2006.260.08:07:02.58#ibcon#about to read 4, iclass 23, count 2 2006.260.08:07:02.58#ibcon#read 4, iclass 23, count 2 2006.260.08:07:02.58#ibcon#about to read 5, iclass 23, count 2 2006.260.08:07:02.58#ibcon#read 5, iclass 23, count 2 2006.260.08:07:02.58#ibcon#about to read 6, iclass 23, count 2 2006.260.08:07:02.58#ibcon#read 6, iclass 23, count 2 2006.260.08:07:02.58#ibcon#end of sib2, iclass 23, count 2 2006.260.08:07:02.58#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:07:02.58#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:07:02.58#ibcon#[27=AT03-04\r\n] 2006.260.08:07:02.58#ibcon#*before write, iclass 23, count 2 2006.260.08:07:02.58#ibcon#enter sib2, iclass 23, count 2 2006.260.08:07:02.58#ibcon#flushed, iclass 23, count 2 2006.260.08:07:02.58#ibcon#about to write, iclass 23, count 2 2006.260.08:07:02.58#ibcon#wrote, iclass 23, count 2 2006.260.08:07:02.58#ibcon#about to read 3, iclass 23, count 2 2006.260.08:07:02.61#ibcon#read 3, iclass 23, count 2 2006.260.08:07:02.61#ibcon#about to read 4, iclass 23, count 2 2006.260.08:07:02.61#ibcon#read 4, iclass 23, count 2 2006.260.08:07:02.61#ibcon#about to read 5, iclass 23, count 2 2006.260.08:07:02.61#ibcon#read 5, iclass 23, count 2 2006.260.08:07:02.61#ibcon#about to read 6, iclass 23, count 2 2006.260.08:07:02.61#ibcon#read 6, iclass 23, count 2 2006.260.08:07:02.61#ibcon#end of sib2, iclass 23, count 2 2006.260.08:07:02.61#ibcon#*after write, iclass 23, count 2 2006.260.08:07:02.61#ibcon#*before return 0, iclass 23, count 2 2006.260.08:07:02.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:07:02.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:07:02.61#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:07:02.61#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:02.61#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:02.73#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:02.73#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:02.73#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:07:02.73#ibcon#first serial, iclass 23, count 0 2006.260.08:07:02.73#ibcon#enter sib2, iclass 23, count 0 2006.260.08:07:02.73#ibcon#flushed, iclass 23, count 0 2006.260.08:07:02.73#ibcon#about to write, iclass 23, count 0 2006.260.08:07:02.73#ibcon#wrote, iclass 23, count 0 2006.260.08:07:02.73#ibcon#about to read 3, iclass 23, count 0 2006.260.08:07:02.75#ibcon#read 3, iclass 23, count 0 2006.260.08:07:02.75#ibcon#about to read 4, iclass 23, count 0 2006.260.08:07:02.75#ibcon#read 4, iclass 23, count 0 2006.260.08:07:02.75#ibcon#about to read 5, iclass 23, count 0 2006.260.08:07:02.75#ibcon#read 5, iclass 23, count 0 2006.260.08:07:02.75#ibcon#about to read 6, iclass 23, count 0 2006.260.08:07:02.75#ibcon#read 6, iclass 23, count 0 2006.260.08:07:02.75#ibcon#end of sib2, iclass 23, count 0 2006.260.08:07:02.75#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:07:02.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:07:02.75#ibcon#[27=USB\r\n] 2006.260.08:07:02.75#ibcon#*before write, iclass 23, count 0 2006.260.08:07:02.75#ibcon#enter sib2, iclass 23, count 0 2006.260.08:07:02.75#ibcon#flushed, iclass 23, count 0 2006.260.08:07:02.75#ibcon#about to write, iclass 23, count 0 2006.260.08:07:02.75#ibcon#wrote, iclass 23, count 0 2006.260.08:07:02.75#ibcon#about to read 3, iclass 23, count 0 2006.260.08:07:02.78#ibcon#read 3, iclass 23, count 0 2006.260.08:07:02.78#ibcon#about to read 4, iclass 23, count 0 2006.260.08:07:02.78#ibcon#read 4, iclass 23, count 0 2006.260.08:07:02.78#ibcon#about to read 5, iclass 23, count 0 2006.260.08:07:02.78#ibcon#read 5, iclass 23, count 0 2006.260.08:07:02.78#ibcon#about to read 6, iclass 23, count 0 2006.260.08:07:02.78#ibcon#read 6, iclass 23, count 0 2006.260.08:07:02.78#ibcon#end of sib2, iclass 23, count 0 2006.260.08:07:02.78#ibcon#*after write, iclass 23, count 0 2006.260.08:07:02.78#ibcon#*before return 0, iclass 23, count 0 2006.260.08:07:02.78#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:02.78#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:07:02.78#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:07:02.78#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:07:02.78$vc4f8/vblo=4,712.99 2006.260.08:07:02.78#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:07:02.78#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:07:02.78#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:02.78#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:02.78#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:02.78#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:02.78#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:07:02.78#ibcon#first serial, iclass 25, count 0 2006.260.08:07:02.78#ibcon#enter sib2, iclass 25, count 0 2006.260.08:07:02.78#ibcon#flushed, iclass 25, count 0 2006.260.08:07:02.78#ibcon#about to write, iclass 25, count 0 2006.260.08:07:02.78#ibcon#wrote, iclass 25, count 0 2006.260.08:07:02.78#ibcon#about to read 3, iclass 25, count 0 2006.260.08:07:02.80#ibcon#read 3, iclass 25, count 0 2006.260.08:07:02.80#ibcon#about to read 4, iclass 25, count 0 2006.260.08:07:02.80#ibcon#read 4, iclass 25, count 0 2006.260.08:07:02.80#ibcon#about to read 5, iclass 25, count 0 2006.260.08:07:02.80#ibcon#read 5, iclass 25, count 0 2006.260.08:07:02.80#ibcon#about to read 6, iclass 25, count 0 2006.260.08:07:02.80#ibcon#read 6, iclass 25, count 0 2006.260.08:07:02.80#ibcon#end of sib2, iclass 25, count 0 2006.260.08:07:02.80#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:07:02.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:07:02.80#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:07:02.80#ibcon#*before write, iclass 25, count 0 2006.260.08:07:02.80#ibcon#enter sib2, iclass 25, count 0 2006.260.08:07:02.80#ibcon#flushed, iclass 25, count 0 2006.260.08:07:02.80#ibcon#about to write, iclass 25, count 0 2006.260.08:07:02.80#ibcon#wrote, iclass 25, count 0 2006.260.08:07:02.80#ibcon#about to read 3, iclass 25, count 0 2006.260.08:07:02.84#ibcon#read 3, iclass 25, count 0 2006.260.08:07:02.84#ibcon#about to read 4, iclass 25, count 0 2006.260.08:07:02.84#ibcon#read 4, iclass 25, count 0 2006.260.08:07:02.84#ibcon#about to read 5, iclass 25, count 0 2006.260.08:07:02.84#ibcon#read 5, iclass 25, count 0 2006.260.08:07:02.84#ibcon#about to read 6, iclass 25, count 0 2006.260.08:07:02.84#ibcon#read 6, iclass 25, count 0 2006.260.08:07:02.84#ibcon#end of sib2, iclass 25, count 0 2006.260.08:07:02.84#ibcon#*after write, iclass 25, count 0 2006.260.08:07:02.84#ibcon#*before return 0, iclass 25, count 0 2006.260.08:07:02.84#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:02.84#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:07:02.84#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:07:02.84#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:07:02.84$vc4f8/vb=4,5 2006.260.08:07:02.84#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:07:02.84#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:07:02.84#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:02.84#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:02.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:02.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:02.90#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:07:02.90#ibcon#first serial, iclass 27, count 2 2006.260.08:07:02.90#ibcon#enter sib2, iclass 27, count 2 2006.260.08:07:02.90#ibcon#flushed, iclass 27, count 2 2006.260.08:07:02.90#ibcon#about to write, iclass 27, count 2 2006.260.08:07:02.90#ibcon#wrote, iclass 27, count 2 2006.260.08:07:02.90#ibcon#about to read 3, iclass 27, count 2 2006.260.08:07:02.92#ibcon#read 3, iclass 27, count 2 2006.260.08:07:02.92#ibcon#about to read 4, iclass 27, count 2 2006.260.08:07:02.92#ibcon#read 4, iclass 27, count 2 2006.260.08:07:02.92#ibcon#about to read 5, iclass 27, count 2 2006.260.08:07:02.92#ibcon#read 5, iclass 27, count 2 2006.260.08:07:02.92#ibcon#about to read 6, iclass 27, count 2 2006.260.08:07:02.92#ibcon#read 6, iclass 27, count 2 2006.260.08:07:02.92#ibcon#end of sib2, iclass 27, count 2 2006.260.08:07:02.92#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:07:02.92#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:07:02.92#ibcon#[27=AT04-05\r\n] 2006.260.08:07:02.92#ibcon#*before write, iclass 27, count 2 2006.260.08:07:02.92#ibcon#enter sib2, iclass 27, count 2 2006.260.08:07:02.92#ibcon#flushed, iclass 27, count 2 2006.260.08:07:02.92#ibcon#about to write, iclass 27, count 2 2006.260.08:07:02.92#ibcon#wrote, iclass 27, count 2 2006.260.08:07:02.92#ibcon#about to read 3, iclass 27, count 2 2006.260.08:07:02.95#ibcon#read 3, iclass 27, count 2 2006.260.08:07:02.95#ibcon#about to read 4, iclass 27, count 2 2006.260.08:07:02.95#ibcon#read 4, iclass 27, count 2 2006.260.08:07:02.95#ibcon#about to read 5, iclass 27, count 2 2006.260.08:07:02.95#ibcon#read 5, iclass 27, count 2 2006.260.08:07:02.95#ibcon#about to read 6, iclass 27, count 2 2006.260.08:07:02.95#ibcon#read 6, iclass 27, count 2 2006.260.08:07:02.95#ibcon#end of sib2, iclass 27, count 2 2006.260.08:07:02.95#ibcon#*after write, iclass 27, count 2 2006.260.08:07:02.95#ibcon#*before return 0, iclass 27, count 2 2006.260.08:07:02.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:02.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:07:02.95#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:07:02.95#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:02.95#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:03.07#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:03.07#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:03.07#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:07:03.07#ibcon#first serial, iclass 27, count 0 2006.260.08:07:03.07#ibcon#enter sib2, iclass 27, count 0 2006.260.08:07:03.07#ibcon#flushed, iclass 27, count 0 2006.260.08:07:03.07#ibcon#about to write, iclass 27, count 0 2006.260.08:07:03.07#ibcon#wrote, iclass 27, count 0 2006.260.08:07:03.07#ibcon#about to read 3, iclass 27, count 0 2006.260.08:07:03.09#ibcon#read 3, iclass 27, count 0 2006.260.08:07:03.09#ibcon#about to read 4, iclass 27, count 0 2006.260.08:07:03.09#ibcon#read 4, iclass 27, count 0 2006.260.08:07:03.09#ibcon#about to read 5, iclass 27, count 0 2006.260.08:07:03.09#ibcon#read 5, iclass 27, count 0 2006.260.08:07:03.09#ibcon#about to read 6, iclass 27, count 0 2006.260.08:07:03.09#ibcon#read 6, iclass 27, count 0 2006.260.08:07:03.09#ibcon#end of sib2, iclass 27, count 0 2006.260.08:07:03.09#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:07:03.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:07:03.09#ibcon#[27=USB\r\n] 2006.260.08:07:03.09#ibcon#*before write, iclass 27, count 0 2006.260.08:07:03.09#ibcon#enter sib2, iclass 27, count 0 2006.260.08:07:03.09#ibcon#flushed, iclass 27, count 0 2006.260.08:07:03.09#ibcon#about to write, iclass 27, count 0 2006.260.08:07:03.09#ibcon#wrote, iclass 27, count 0 2006.260.08:07:03.09#ibcon#about to read 3, iclass 27, count 0 2006.260.08:07:03.12#ibcon#read 3, iclass 27, count 0 2006.260.08:07:03.12#ibcon#about to read 4, iclass 27, count 0 2006.260.08:07:03.12#ibcon#read 4, iclass 27, count 0 2006.260.08:07:03.12#ibcon#about to read 5, iclass 27, count 0 2006.260.08:07:03.12#ibcon#read 5, iclass 27, count 0 2006.260.08:07:03.12#ibcon#about to read 6, iclass 27, count 0 2006.260.08:07:03.12#ibcon#read 6, iclass 27, count 0 2006.260.08:07:03.12#ibcon#end of sib2, iclass 27, count 0 2006.260.08:07:03.12#ibcon#*after write, iclass 27, count 0 2006.260.08:07:03.12#ibcon#*before return 0, iclass 27, count 0 2006.260.08:07:03.12#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:03.12#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:07:03.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:07:03.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:07:03.12$vc4f8/vblo=5,744.99 2006.260.08:07:03.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:07:03.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:07:03.12#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:03.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:03.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:03.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:03.12#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:07:03.12#ibcon#first serial, iclass 29, count 0 2006.260.08:07:03.12#ibcon#enter sib2, iclass 29, count 0 2006.260.08:07:03.12#ibcon#flushed, iclass 29, count 0 2006.260.08:07:03.12#ibcon#about to write, iclass 29, count 0 2006.260.08:07:03.12#ibcon#wrote, iclass 29, count 0 2006.260.08:07:03.12#ibcon#about to read 3, iclass 29, count 0 2006.260.08:07:03.14#ibcon#read 3, iclass 29, count 0 2006.260.08:07:03.14#ibcon#about to read 4, iclass 29, count 0 2006.260.08:07:03.14#ibcon#read 4, iclass 29, count 0 2006.260.08:07:03.14#ibcon#about to read 5, iclass 29, count 0 2006.260.08:07:03.14#ibcon#read 5, iclass 29, count 0 2006.260.08:07:03.14#ibcon#about to read 6, iclass 29, count 0 2006.260.08:07:03.14#ibcon#read 6, iclass 29, count 0 2006.260.08:07:03.14#ibcon#end of sib2, iclass 29, count 0 2006.260.08:07:03.14#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:07:03.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:07:03.14#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:07:03.14#ibcon#*before write, iclass 29, count 0 2006.260.08:07:03.14#ibcon#enter sib2, iclass 29, count 0 2006.260.08:07:03.14#ibcon#flushed, iclass 29, count 0 2006.260.08:07:03.14#ibcon#about to write, iclass 29, count 0 2006.260.08:07:03.14#ibcon#wrote, iclass 29, count 0 2006.260.08:07:03.14#ibcon#about to read 3, iclass 29, count 0 2006.260.08:07:03.18#ibcon#read 3, iclass 29, count 0 2006.260.08:07:03.18#ibcon#about to read 4, iclass 29, count 0 2006.260.08:07:03.18#ibcon#read 4, iclass 29, count 0 2006.260.08:07:03.18#ibcon#about to read 5, iclass 29, count 0 2006.260.08:07:03.18#ibcon#read 5, iclass 29, count 0 2006.260.08:07:03.18#ibcon#about to read 6, iclass 29, count 0 2006.260.08:07:03.18#ibcon#read 6, iclass 29, count 0 2006.260.08:07:03.18#ibcon#end of sib2, iclass 29, count 0 2006.260.08:07:03.18#ibcon#*after write, iclass 29, count 0 2006.260.08:07:03.18#ibcon#*before return 0, iclass 29, count 0 2006.260.08:07:03.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:03.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:07:03.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:07:03.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:07:03.18$vc4f8/vb=5,4 2006.260.08:07:03.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:07:03.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:07:03.18#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:03.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:03.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:03.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:03.24#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:07:03.24#ibcon#first serial, iclass 31, count 2 2006.260.08:07:03.24#ibcon#enter sib2, iclass 31, count 2 2006.260.08:07:03.24#ibcon#flushed, iclass 31, count 2 2006.260.08:07:03.24#ibcon#about to write, iclass 31, count 2 2006.260.08:07:03.24#ibcon#wrote, iclass 31, count 2 2006.260.08:07:03.24#ibcon#about to read 3, iclass 31, count 2 2006.260.08:07:03.26#ibcon#read 3, iclass 31, count 2 2006.260.08:07:03.26#ibcon#about to read 4, iclass 31, count 2 2006.260.08:07:03.26#ibcon#read 4, iclass 31, count 2 2006.260.08:07:03.26#ibcon#about to read 5, iclass 31, count 2 2006.260.08:07:03.26#ibcon#read 5, iclass 31, count 2 2006.260.08:07:03.26#ibcon#about to read 6, iclass 31, count 2 2006.260.08:07:03.26#ibcon#read 6, iclass 31, count 2 2006.260.08:07:03.26#ibcon#end of sib2, iclass 31, count 2 2006.260.08:07:03.26#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:07:03.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:07:03.26#ibcon#[27=AT05-04\r\n] 2006.260.08:07:03.26#ibcon#*before write, iclass 31, count 2 2006.260.08:07:03.26#ibcon#enter sib2, iclass 31, count 2 2006.260.08:07:03.26#ibcon#flushed, iclass 31, count 2 2006.260.08:07:03.26#ibcon#about to write, iclass 31, count 2 2006.260.08:07:03.26#ibcon#wrote, iclass 31, count 2 2006.260.08:07:03.26#ibcon#about to read 3, iclass 31, count 2 2006.260.08:07:03.29#ibcon#read 3, iclass 31, count 2 2006.260.08:07:03.29#ibcon#about to read 4, iclass 31, count 2 2006.260.08:07:03.29#ibcon#read 4, iclass 31, count 2 2006.260.08:07:03.29#ibcon#about to read 5, iclass 31, count 2 2006.260.08:07:03.29#ibcon#read 5, iclass 31, count 2 2006.260.08:07:03.29#ibcon#about to read 6, iclass 31, count 2 2006.260.08:07:03.29#ibcon#read 6, iclass 31, count 2 2006.260.08:07:03.29#ibcon#end of sib2, iclass 31, count 2 2006.260.08:07:03.29#ibcon#*after write, iclass 31, count 2 2006.260.08:07:03.29#ibcon#*before return 0, iclass 31, count 2 2006.260.08:07:03.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:03.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:07:03.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:07:03.29#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:03.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:03.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:03.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:03.41#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:07:03.41#ibcon#first serial, iclass 31, count 0 2006.260.08:07:03.41#ibcon#enter sib2, iclass 31, count 0 2006.260.08:07:03.41#ibcon#flushed, iclass 31, count 0 2006.260.08:07:03.41#ibcon#about to write, iclass 31, count 0 2006.260.08:07:03.41#ibcon#wrote, iclass 31, count 0 2006.260.08:07:03.41#ibcon#about to read 3, iclass 31, count 0 2006.260.08:07:03.43#ibcon#read 3, iclass 31, count 0 2006.260.08:07:03.43#ibcon#about to read 4, iclass 31, count 0 2006.260.08:07:03.43#ibcon#read 4, iclass 31, count 0 2006.260.08:07:03.43#ibcon#about to read 5, iclass 31, count 0 2006.260.08:07:03.43#ibcon#read 5, iclass 31, count 0 2006.260.08:07:03.43#ibcon#about to read 6, iclass 31, count 0 2006.260.08:07:03.43#ibcon#read 6, iclass 31, count 0 2006.260.08:07:03.43#ibcon#end of sib2, iclass 31, count 0 2006.260.08:07:03.43#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:07:03.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:07:03.43#ibcon#[27=USB\r\n] 2006.260.08:07:03.43#ibcon#*before write, iclass 31, count 0 2006.260.08:07:03.43#ibcon#enter sib2, iclass 31, count 0 2006.260.08:07:03.43#ibcon#flushed, iclass 31, count 0 2006.260.08:07:03.43#ibcon#about to write, iclass 31, count 0 2006.260.08:07:03.43#ibcon#wrote, iclass 31, count 0 2006.260.08:07:03.43#ibcon#about to read 3, iclass 31, count 0 2006.260.08:07:03.46#ibcon#read 3, iclass 31, count 0 2006.260.08:07:03.46#ibcon#about to read 4, iclass 31, count 0 2006.260.08:07:03.46#ibcon#read 4, iclass 31, count 0 2006.260.08:07:03.46#ibcon#about to read 5, iclass 31, count 0 2006.260.08:07:03.46#ibcon#read 5, iclass 31, count 0 2006.260.08:07:03.46#ibcon#about to read 6, iclass 31, count 0 2006.260.08:07:03.46#ibcon#read 6, iclass 31, count 0 2006.260.08:07:03.46#ibcon#end of sib2, iclass 31, count 0 2006.260.08:07:03.46#ibcon#*after write, iclass 31, count 0 2006.260.08:07:03.46#ibcon#*before return 0, iclass 31, count 0 2006.260.08:07:03.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:03.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:07:03.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:07:03.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:07:03.46$vc4f8/vblo=6,752.99 2006.260.08:07:03.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:07:03.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:07:03.46#ibcon#ireg 17 cls_cnt 0 2006.260.08:07:03.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:03.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:03.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:03.46#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:07:03.46#ibcon#first serial, iclass 33, count 0 2006.260.08:07:03.46#ibcon#enter sib2, iclass 33, count 0 2006.260.08:07:03.46#ibcon#flushed, iclass 33, count 0 2006.260.08:07:03.46#ibcon#about to write, iclass 33, count 0 2006.260.08:07:03.46#ibcon#wrote, iclass 33, count 0 2006.260.08:07:03.46#ibcon#about to read 3, iclass 33, count 0 2006.260.08:07:03.48#ibcon#read 3, iclass 33, count 0 2006.260.08:07:03.48#ibcon#about to read 4, iclass 33, count 0 2006.260.08:07:03.48#ibcon#read 4, iclass 33, count 0 2006.260.08:07:03.48#ibcon#about to read 5, iclass 33, count 0 2006.260.08:07:03.48#ibcon#read 5, iclass 33, count 0 2006.260.08:07:03.48#ibcon#about to read 6, iclass 33, count 0 2006.260.08:07:03.48#ibcon#read 6, iclass 33, count 0 2006.260.08:07:03.48#ibcon#end of sib2, iclass 33, count 0 2006.260.08:07:03.48#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:07:03.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:07:03.48#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:07:03.48#ibcon#*before write, iclass 33, count 0 2006.260.08:07:03.48#ibcon#enter sib2, iclass 33, count 0 2006.260.08:07:03.48#ibcon#flushed, iclass 33, count 0 2006.260.08:07:03.48#ibcon#about to write, iclass 33, count 0 2006.260.08:07:03.48#ibcon#wrote, iclass 33, count 0 2006.260.08:07:03.48#ibcon#about to read 3, iclass 33, count 0 2006.260.08:07:03.52#ibcon#read 3, iclass 33, count 0 2006.260.08:07:03.52#ibcon#about to read 4, iclass 33, count 0 2006.260.08:07:03.52#ibcon#read 4, iclass 33, count 0 2006.260.08:07:03.52#ibcon#about to read 5, iclass 33, count 0 2006.260.08:07:03.52#ibcon#read 5, iclass 33, count 0 2006.260.08:07:03.52#ibcon#about to read 6, iclass 33, count 0 2006.260.08:07:03.52#ibcon#read 6, iclass 33, count 0 2006.260.08:07:03.52#ibcon#end of sib2, iclass 33, count 0 2006.260.08:07:03.52#ibcon#*after write, iclass 33, count 0 2006.260.08:07:03.52#ibcon#*before return 0, iclass 33, count 0 2006.260.08:07:03.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:03.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:07:03.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:07:03.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:07:03.52$vc4f8/vb=6,4 2006.260.08:07:03.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:07:03.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:07:03.52#ibcon#ireg 11 cls_cnt 2 2006.260.08:07:03.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:03.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:03.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:03.58#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:07:03.58#ibcon#first serial, iclass 35, count 2 2006.260.08:07:03.58#ibcon#enter sib2, iclass 35, count 2 2006.260.08:07:03.58#ibcon#flushed, iclass 35, count 2 2006.260.08:07:03.58#ibcon#about to write, iclass 35, count 2 2006.260.08:07:03.58#ibcon#wrote, iclass 35, count 2 2006.260.08:07:03.58#ibcon#about to read 3, iclass 35, count 2 2006.260.08:07:03.60#ibcon#read 3, iclass 35, count 2 2006.260.08:07:03.60#ibcon#about to read 4, iclass 35, count 2 2006.260.08:07:03.60#ibcon#read 4, iclass 35, count 2 2006.260.08:07:03.60#ibcon#about to read 5, iclass 35, count 2 2006.260.08:07:03.60#ibcon#read 5, iclass 35, count 2 2006.260.08:07:03.60#ibcon#about to read 6, iclass 35, count 2 2006.260.08:07:03.60#ibcon#read 6, iclass 35, count 2 2006.260.08:07:03.60#ibcon#end of sib2, iclass 35, count 2 2006.260.08:07:03.60#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:07:03.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:07:03.60#ibcon#[27=AT06-04\r\n] 2006.260.08:07:03.60#ibcon#*before write, iclass 35, count 2 2006.260.08:07:03.60#ibcon#enter sib2, iclass 35, count 2 2006.260.08:07:03.60#ibcon#flushed, iclass 35, count 2 2006.260.08:07:03.60#ibcon#about to write, iclass 35, count 2 2006.260.08:07:03.60#ibcon#wrote, iclass 35, count 2 2006.260.08:07:03.60#ibcon#about to read 3, iclass 35, count 2 2006.260.08:07:03.63#ibcon#read 3, iclass 35, count 2 2006.260.08:07:03.63#ibcon#about to read 4, iclass 35, count 2 2006.260.08:07:03.63#ibcon#read 4, iclass 35, count 2 2006.260.08:07:03.63#ibcon#about to read 5, iclass 35, count 2 2006.260.08:07:03.63#ibcon#read 5, iclass 35, count 2 2006.260.08:07:03.63#ibcon#about to read 6, iclass 35, count 2 2006.260.08:07:03.63#ibcon#read 6, iclass 35, count 2 2006.260.08:07:03.63#ibcon#end of sib2, iclass 35, count 2 2006.260.08:07:03.63#ibcon#*after write, iclass 35, count 2 2006.260.08:07:03.63#ibcon#*before return 0, iclass 35, count 2 2006.260.08:07:03.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:03.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:07:03.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:07:03.63#ibcon#ireg 7 cls_cnt 0 2006.260.08:07:03.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:03.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:03.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:03.75#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:07:03.75#ibcon#first serial, iclass 35, count 0 2006.260.08:07:03.75#ibcon#enter sib2, iclass 35, count 0 2006.260.08:07:03.75#ibcon#flushed, iclass 35, count 0 2006.260.08:07:03.75#ibcon#about to write, iclass 35, count 0 2006.260.08:07:03.75#ibcon#wrote, iclass 35, count 0 2006.260.08:07:03.75#ibcon#about to read 3, iclass 35, count 0 2006.260.08:07:03.77#ibcon#read 3, iclass 35, count 0 2006.260.08:07:03.77#ibcon#about to read 4, iclass 35, count 0 2006.260.08:07:03.77#ibcon#read 4, iclass 35, count 0 2006.260.08:07:03.77#ibcon#about to read 5, iclass 35, count 0 2006.260.08:07:03.77#ibcon#read 5, iclass 35, count 0 2006.260.08:07:03.77#ibcon#about to read 6, iclass 35, count 0 2006.260.08:07:03.77#ibcon#read 6, iclass 35, count 0 2006.260.08:07:03.77#ibcon#end of sib2, iclass 35, count 0 2006.260.08:07:03.77#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:07:03.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:07:03.77#ibcon#[27=USB\r\n] 2006.260.08:07:03.77#ibcon#*before write, iclass 35, count 0 2006.260.08:07:03.77#ibcon#enter sib2, iclass 35, count 0 2006.260.08:07:03.77#ibcon#flushed, iclass 35, count 0 2006.260.08:07:03.77#ibcon#about to write, iclass 35, count 0 2006.260.08:07:03.77#ibcon#wrote, iclass 35, count 0 2006.260.08:07:03.77#ibcon#about to read 3, iclass 35, count 0 2006.260.08:07:03.80#ibcon#read 3, iclass 35, count 0 2006.260.08:07:03.80#ibcon#about to read 4, iclass 35, count 0 2006.260.08:07:03.80#ibcon#read 4, iclass 35, count 0 2006.260.08:07:03.80#ibcon#about to read 5, iclass 35, count 0 2006.260.08:07:03.80#ibcon#read 5, iclass 35, count 0 2006.260.08:07:03.80#ibcon#about to read 6, iclass 35, count 0 2006.260.08:07:03.80#ibcon#read 6, iclass 35, count 0 2006.260.08:07:03.80#ibcon#end of sib2, iclass 35, count 0 2006.260.08:07:03.80#ibcon#*after write, iclass 35, count 0 2006.260.08:07:03.80#ibcon#*before return 0, iclass 35, count 0 2006.260.08:07:03.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:03.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:07:03.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:07:03.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:07:03.80$vc4f8/vabw=wide 2006.260.08:07:03.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:07:03.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:07:03.80#ibcon#ireg 8 cls_cnt 0 2006.260.08:07:03.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:03.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:03.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:03.80#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:07:03.80#ibcon#first serial, iclass 37, count 0 2006.260.08:07:03.80#ibcon#enter sib2, iclass 37, count 0 2006.260.08:07:03.80#ibcon#flushed, iclass 37, count 0 2006.260.08:07:03.80#ibcon#about to write, iclass 37, count 0 2006.260.08:07:03.80#ibcon#wrote, iclass 37, count 0 2006.260.08:07:03.80#ibcon#about to read 3, iclass 37, count 0 2006.260.08:07:03.82#ibcon#read 3, iclass 37, count 0 2006.260.08:07:03.82#ibcon#about to read 4, iclass 37, count 0 2006.260.08:07:03.82#ibcon#read 4, iclass 37, count 0 2006.260.08:07:03.82#ibcon#about to read 5, iclass 37, count 0 2006.260.08:07:03.82#ibcon#read 5, iclass 37, count 0 2006.260.08:07:03.82#ibcon#about to read 6, iclass 37, count 0 2006.260.08:07:03.82#ibcon#read 6, iclass 37, count 0 2006.260.08:07:03.82#ibcon#end of sib2, iclass 37, count 0 2006.260.08:07:03.82#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:07:03.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:07:03.82#ibcon#[25=BW32\r\n] 2006.260.08:07:03.82#ibcon#*before write, iclass 37, count 0 2006.260.08:07:03.82#ibcon#enter sib2, iclass 37, count 0 2006.260.08:07:03.82#ibcon#flushed, iclass 37, count 0 2006.260.08:07:03.82#ibcon#about to write, iclass 37, count 0 2006.260.08:07:03.82#ibcon#wrote, iclass 37, count 0 2006.260.08:07:03.82#ibcon#about to read 3, iclass 37, count 0 2006.260.08:07:03.85#ibcon#read 3, iclass 37, count 0 2006.260.08:07:03.85#ibcon#about to read 4, iclass 37, count 0 2006.260.08:07:03.85#ibcon#read 4, iclass 37, count 0 2006.260.08:07:03.85#ibcon#about to read 5, iclass 37, count 0 2006.260.08:07:03.85#ibcon#read 5, iclass 37, count 0 2006.260.08:07:03.85#ibcon#about to read 6, iclass 37, count 0 2006.260.08:07:03.85#ibcon#read 6, iclass 37, count 0 2006.260.08:07:03.85#ibcon#end of sib2, iclass 37, count 0 2006.260.08:07:03.85#ibcon#*after write, iclass 37, count 0 2006.260.08:07:03.85#ibcon#*before return 0, iclass 37, count 0 2006.260.08:07:03.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:03.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:07:03.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:07:03.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:07:03.85$vc4f8/vbbw=wide 2006.260.08:07:03.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.08:07:03.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.08:07:03.85#ibcon#ireg 8 cls_cnt 0 2006.260.08:07:03.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:07:03.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:07:03.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:07:03.92#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:07:03.92#ibcon#first serial, iclass 39, count 0 2006.260.08:07:03.92#ibcon#enter sib2, iclass 39, count 0 2006.260.08:07:03.92#ibcon#flushed, iclass 39, count 0 2006.260.08:07:03.92#ibcon#about to write, iclass 39, count 0 2006.260.08:07:03.92#ibcon#wrote, iclass 39, count 0 2006.260.08:07:03.92#ibcon#about to read 3, iclass 39, count 0 2006.260.08:07:03.94#ibcon#read 3, iclass 39, count 0 2006.260.08:07:03.94#ibcon#about to read 4, iclass 39, count 0 2006.260.08:07:03.94#ibcon#read 4, iclass 39, count 0 2006.260.08:07:03.94#ibcon#about to read 5, iclass 39, count 0 2006.260.08:07:03.94#ibcon#read 5, iclass 39, count 0 2006.260.08:07:03.94#ibcon#about to read 6, iclass 39, count 0 2006.260.08:07:03.94#ibcon#read 6, iclass 39, count 0 2006.260.08:07:03.94#ibcon#end of sib2, iclass 39, count 0 2006.260.08:07:03.94#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:07:03.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:07:03.94#ibcon#[27=BW32\r\n] 2006.260.08:07:03.94#ibcon#*before write, iclass 39, count 0 2006.260.08:07:03.94#ibcon#enter sib2, iclass 39, count 0 2006.260.08:07:03.94#ibcon#flushed, iclass 39, count 0 2006.260.08:07:03.94#ibcon#about to write, iclass 39, count 0 2006.260.08:07:03.94#ibcon#wrote, iclass 39, count 0 2006.260.08:07:03.94#ibcon#about to read 3, iclass 39, count 0 2006.260.08:07:03.97#ibcon#read 3, iclass 39, count 0 2006.260.08:07:03.97#ibcon#about to read 4, iclass 39, count 0 2006.260.08:07:03.97#ibcon#read 4, iclass 39, count 0 2006.260.08:07:03.97#ibcon#about to read 5, iclass 39, count 0 2006.260.08:07:03.97#ibcon#read 5, iclass 39, count 0 2006.260.08:07:03.97#ibcon#about to read 6, iclass 39, count 0 2006.260.08:07:03.97#ibcon#read 6, iclass 39, count 0 2006.260.08:07:03.97#ibcon#end of sib2, iclass 39, count 0 2006.260.08:07:03.97#ibcon#*after write, iclass 39, count 0 2006.260.08:07:03.97#ibcon#*before return 0, iclass 39, count 0 2006.260.08:07:03.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:07:03.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:07:03.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:07:03.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:07:03.97$4f8m12a/ifd4f 2006.260.08:07:03.97$ifd4f/lo= 2006.260.08:07:03.97$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:07:03.97$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:07:03.97$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:07:03.97$ifd4f/patch= 2006.260.08:07:03.97$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:07:03.97$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:07:03.97$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:07:03.97$4f8m12a/"form=m,16.000,1:2 2006.260.08:07:03.97$4f8m12a/"tpicd 2006.260.08:07:03.97$4f8m12a/echo=off 2006.260.08:07:03.97$4f8m12a/xlog=off 2006.260.08:07:03.97:!2006.260.08:07:30 2006.260.08:07:13.14#trakl#Source acquired 2006.260.08:07:15.14#flagr#flagr/antenna,acquired 2006.260.08:07:30.00:preob 2006.260.08:07:31.14/onsource/TRACKING 2006.260.08:07:31.14:!2006.260.08:07:40 2006.260.08:07:40.00:data_valid=on 2006.260.08:07:40.00:midob 2006.260.08:07:40.14/onsource/TRACKING 2006.260.08:07:40.14/wx/22.81,1010.4,89 2006.260.08:07:40.31/cable/+6.4574E-03 2006.260.08:07:41.40/va/01,08,usb,yes,31,32 2006.260.08:07:41.40/va/02,07,usb,yes,31,32 2006.260.08:07:41.40/va/03,08,usb,yes,23,23 2006.260.08:07:41.40/va/04,07,usb,yes,32,35 2006.260.08:07:41.40/va/05,07,usb,yes,35,37 2006.260.08:07:41.40/va/06,06,usb,yes,34,34 2006.260.08:07:41.40/va/07,06,usb,yes,35,35 2006.260.08:07:41.40/va/08,06,usb,yes,38,37 2006.260.08:07:41.63/valo/01,532.99,yes,locked 2006.260.08:07:41.63/valo/02,572.99,yes,locked 2006.260.08:07:41.63/valo/03,672.99,yes,locked 2006.260.08:07:41.63/valo/04,832.99,yes,locked 2006.260.08:07:41.63/valo/05,652.99,yes,locked 2006.260.08:07:41.63/valo/06,772.99,yes,locked 2006.260.08:07:41.63/valo/07,832.99,yes,locked 2006.260.08:07:41.63/valo/08,852.99,yes,locked 2006.260.08:07:42.72/vb/01,04,usb,yes,30,29 2006.260.08:07:42.72/vb/02,05,usb,yes,28,29 2006.260.08:07:42.72/vb/03,04,usb,yes,28,32 2006.260.08:07:42.72/vb/04,05,usb,yes,26,26 2006.260.08:07:42.72/vb/05,04,usb,yes,27,31 2006.260.08:07:42.72/vb/06,04,usb,yes,28,31 2006.260.08:07:42.72/vb/07,04,usb,yes,31,30 2006.260.08:07:42.72/vb/08,04,usb,yes,28,31 2006.260.08:07:42.96/vblo/01,632.99,yes,locked 2006.260.08:07:42.96/vblo/02,640.99,yes,locked 2006.260.08:07:42.96/vblo/03,656.99,yes,locked 2006.260.08:07:42.96/vblo/04,712.99,yes,locked 2006.260.08:07:42.96/vblo/05,744.99,yes,locked 2006.260.08:07:42.96/vblo/06,752.99,yes,locked 2006.260.08:07:42.96/vblo/07,734.99,yes,locked 2006.260.08:07:42.96/vblo/08,744.99,yes,locked 2006.260.08:07:43.11/vabw/8 2006.260.08:07:43.26/vbbw/8 2006.260.08:07:43.35/xfe/off,on,15.2 2006.260.08:07:43.74/ifatt/23,28,28,28 2006.260.08:07:44.08/fmout-gps/S +4.46E-07 2006.260.08:07:44.12:!2006.260.08:08:40 2006.260.08:08:40.00:data_valid=off 2006.260.08:08:40.00:postob 2006.260.08:08:40.08/cable/+6.4584E-03 2006.260.08:08:40.08/wx/22.80,1010.4,89 2006.260.08:08:41.08/fmout-gps/S +4.45E-07 2006.260.08:08:41.08:scan_name=260-0809,k06260,60 2006.260.08:08:41.09:source=1611+343,161341.06,341247.9,2000.0,ccw 2006.260.08:08:41.15#flagr#flagr/antenna,new-source 2006.260.08:08:42.13:checkk5 2006.260.08:08:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:08:42.94/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:08:43.37/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:08:43.79/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:08:44.21/chk_obsdata//k5ts1/T2600807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:08:44.61/chk_obsdata//k5ts2/T2600807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:08:44.99/chk_obsdata//k5ts3/T2600807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:08:45.41/chk_obsdata//k5ts4/T2600807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:08:46.21/k5log//k5ts1_log_newline 2006.260.08:08:46.99/k5log//k5ts2_log_newline 2006.260.08:08:47.98/k5log//k5ts3_log_newline 2006.260.08:08:48.76/k5log//k5ts4_log_newline 2006.260.08:08:48.78/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:08:48.78:4f8m12a=2 2006.260.08:08:48.78$4f8m12a/echo=on 2006.260.08:08:48.78$4f8m12a/pcalon 2006.260.08:08:48.78$pcalon/"no phase cal control is implemented here 2006.260.08:08:48.78$4f8m12a/"tpicd=stop 2006.260.08:08:48.78$4f8m12a/vc4f8 2006.260.08:08:48.78$vc4f8/valo=1,532.99 2006.260.08:08:48.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.08:08:48.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.08:08:48.78#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:48.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:48.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:48.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:48.78#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:08:48.78#ibcon#first serial, iclass 10, count 0 2006.260.08:08:48.78#ibcon#enter sib2, iclass 10, count 0 2006.260.08:08:48.78#ibcon#flushed, iclass 10, count 0 2006.260.08:08:48.78#ibcon#about to write, iclass 10, count 0 2006.260.08:08:48.78#ibcon#wrote, iclass 10, count 0 2006.260.08:08:48.78#ibcon#about to read 3, iclass 10, count 0 2006.260.08:08:48.83#ibcon#read 3, iclass 10, count 0 2006.260.08:08:48.83#ibcon#about to read 4, iclass 10, count 0 2006.260.08:08:48.83#ibcon#read 4, iclass 10, count 0 2006.260.08:08:48.83#ibcon#about to read 5, iclass 10, count 0 2006.260.08:08:48.83#ibcon#read 5, iclass 10, count 0 2006.260.08:08:48.83#ibcon#about to read 6, iclass 10, count 0 2006.260.08:08:48.83#ibcon#read 6, iclass 10, count 0 2006.260.08:08:48.83#ibcon#end of sib2, iclass 10, count 0 2006.260.08:08:48.83#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:08:48.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:08:48.83#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:08:48.83#ibcon#*before write, iclass 10, count 0 2006.260.08:08:48.83#ibcon#enter sib2, iclass 10, count 0 2006.260.08:08:48.83#ibcon#flushed, iclass 10, count 0 2006.260.08:08:48.83#ibcon#about to write, iclass 10, count 0 2006.260.08:08:48.83#ibcon#wrote, iclass 10, count 0 2006.260.08:08:48.83#ibcon#about to read 3, iclass 10, count 0 2006.260.08:08:48.88#ibcon#read 3, iclass 10, count 0 2006.260.08:08:48.88#ibcon#about to read 4, iclass 10, count 0 2006.260.08:08:48.88#ibcon#read 4, iclass 10, count 0 2006.260.08:08:48.88#ibcon#about to read 5, iclass 10, count 0 2006.260.08:08:48.88#ibcon#read 5, iclass 10, count 0 2006.260.08:08:48.88#ibcon#about to read 6, iclass 10, count 0 2006.260.08:08:48.88#ibcon#read 6, iclass 10, count 0 2006.260.08:08:48.88#ibcon#end of sib2, iclass 10, count 0 2006.260.08:08:48.88#ibcon#*after write, iclass 10, count 0 2006.260.08:08:48.88#ibcon#*before return 0, iclass 10, count 0 2006.260.08:08:48.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:48.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:48.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:08:48.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:08:48.88$vc4f8/va=1,8 2006.260.08:08:48.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.08:08:48.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.08:08:48.88#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:48.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:48.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:48.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:48.88#ibcon#enter wrdev, iclass 12, count 2 2006.260.08:08:48.88#ibcon#first serial, iclass 12, count 2 2006.260.08:08:48.88#ibcon#enter sib2, iclass 12, count 2 2006.260.08:08:48.88#ibcon#flushed, iclass 12, count 2 2006.260.08:08:48.88#ibcon#about to write, iclass 12, count 2 2006.260.08:08:48.88#ibcon#wrote, iclass 12, count 2 2006.260.08:08:48.88#ibcon#about to read 3, iclass 12, count 2 2006.260.08:08:48.91#ibcon#read 3, iclass 12, count 2 2006.260.08:08:48.91#ibcon#about to read 4, iclass 12, count 2 2006.260.08:08:48.91#ibcon#read 4, iclass 12, count 2 2006.260.08:08:48.91#ibcon#about to read 5, iclass 12, count 2 2006.260.08:08:48.91#ibcon#read 5, iclass 12, count 2 2006.260.08:08:48.91#ibcon#about to read 6, iclass 12, count 2 2006.260.08:08:48.91#ibcon#read 6, iclass 12, count 2 2006.260.08:08:48.91#ibcon#end of sib2, iclass 12, count 2 2006.260.08:08:48.91#ibcon#*mode == 0, iclass 12, count 2 2006.260.08:08:48.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.08:08:48.91#ibcon#[25=AT01-08\r\n] 2006.260.08:08:48.91#ibcon#*before write, iclass 12, count 2 2006.260.08:08:48.91#ibcon#enter sib2, iclass 12, count 2 2006.260.08:08:48.91#ibcon#flushed, iclass 12, count 2 2006.260.08:08:48.91#ibcon#about to write, iclass 12, count 2 2006.260.08:08:48.91#ibcon#wrote, iclass 12, count 2 2006.260.08:08:48.91#ibcon#about to read 3, iclass 12, count 2 2006.260.08:08:48.94#ibcon#read 3, iclass 12, count 2 2006.260.08:08:48.94#ibcon#about to read 4, iclass 12, count 2 2006.260.08:08:48.94#ibcon#read 4, iclass 12, count 2 2006.260.08:08:48.94#ibcon#about to read 5, iclass 12, count 2 2006.260.08:08:48.94#ibcon#read 5, iclass 12, count 2 2006.260.08:08:48.94#ibcon#about to read 6, iclass 12, count 2 2006.260.08:08:48.94#ibcon#read 6, iclass 12, count 2 2006.260.08:08:48.94#ibcon#end of sib2, iclass 12, count 2 2006.260.08:08:48.94#ibcon#*after write, iclass 12, count 2 2006.260.08:08:48.94#ibcon#*before return 0, iclass 12, count 2 2006.260.08:08:48.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:48.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:48.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.08:08:48.94#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:48.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:49.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:49.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:49.06#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:08:49.06#ibcon#first serial, iclass 12, count 0 2006.260.08:08:49.06#ibcon#enter sib2, iclass 12, count 0 2006.260.08:08:49.06#ibcon#flushed, iclass 12, count 0 2006.260.08:08:49.06#ibcon#about to write, iclass 12, count 0 2006.260.08:08:49.06#ibcon#wrote, iclass 12, count 0 2006.260.08:08:49.06#ibcon#about to read 3, iclass 12, count 0 2006.260.08:08:49.08#ibcon#read 3, iclass 12, count 0 2006.260.08:08:49.08#ibcon#about to read 4, iclass 12, count 0 2006.260.08:08:49.08#ibcon#read 4, iclass 12, count 0 2006.260.08:08:49.08#ibcon#about to read 5, iclass 12, count 0 2006.260.08:08:49.08#ibcon#read 5, iclass 12, count 0 2006.260.08:08:49.08#ibcon#about to read 6, iclass 12, count 0 2006.260.08:08:49.08#ibcon#read 6, iclass 12, count 0 2006.260.08:08:49.08#ibcon#end of sib2, iclass 12, count 0 2006.260.08:08:49.08#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:08:49.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:08:49.08#ibcon#[25=USB\r\n] 2006.260.08:08:49.08#ibcon#*before write, iclass 12, count 0 2006.260.08:08:49.08#ibcon#enter sib2, iclass 12, count 0 2006.260.08:08:49.08#ibcon#flushed, iclass 12, count 0 2006.260.08:08:49.08#ibcon#about to write, iclass 12, count 0 2006.260.08:08:49.08#ibcon#wrote, iclass 12, count 0 2006.260.08:08:49.08#ibcon#about to read 3, iclass 12, count 0 2006.260.08:08:49.11#ibcon#read 3, iclass 12, count 0 2006.260.08:08:49.11#ibcon#about to read 4, iclass 12, count 0 2006.260.08:08:49.11#ibcon#read 4, iclass 12, count 0 2006.260.08:08:49.11#ibcon#about to read 5, iclass 12, count 0 2006.260.08:08:49.11#ibcon#read 5, iclass 12, count 0 2006.260.08:08:49.11#ibcon#about to read 6, iclass 12, count 0 2006.260.08:08:49.11#ibcon#read 6, iclass 12, count 0 2006.260.08:08:49.11#ibcon#end of sib2, iclass 12, count 0 2006.260.08:08:49.11#ibcon#*after write, iclass 12, count 0 2006.260.08:08:49.11#ibcon#*before return 0, iclass 12, count 0 2006.260.08:08:49.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:49.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:49.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:08:49.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:08:49.11$vc4f8/valo=2,572.99 2006.260.08:08:49.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:08:49.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:08:49.11#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:49.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:49.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:49.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:49.11#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:08:49.11#ibcon#first serial, iclass 14, count 0 2006.260.08:08:49.11#ibcon#enter sib2, iclass 14, count 0 2006.260.08:08:49.11#ibcon#flushed, iclass 14, count 0 2006.260.08:08:49.11#ibcon#about to write, iclass 14, count 0 2006.260.08:08:49.11#ibcon#wrote, iclass 14, count 0 2006.260.08:08:49.11#ibcon#about to read 3, iclass 14, count 0 2006.260.08:08:49.13#ibcon#read 3, iclass 14, count 0 2006.260.08:08:49.13#ibcon#about to read 4, iclass 14, count 0 2006.260.08:08:49.13#ibcon#read 4, iclass 14, count 0 2006.260.08:08:49.13#ibcon#about to read 5, iclass 14, count 0 2006.260.08:08:49.13#ibcon#read 5, iclass 14, count 0 2006.260.08:08:49.13#ibcon#about to read 6, iclass 14, count 0 2006.260.08:08:49.13#ibcon#read 6, iclass 14, count 0 2006.260.08:08:49.13#ibcon#end of sib2, iclass 14, count 0 2006.260.08:08:49.13#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:08:49.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:08:49.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:08:49.13#ibcon#*before write, iclass 14, count 0 2006.260.08:08:49.13#ibcon#enter sib2, iclass 14, count 0 2006.260.08:08:49.13#ibcon#flushed, iclass 14, count 0 2006.260.08:08:49.13#ibcon#about to write, iclass 14, count 0 2006.260.08:08:49.13#ibcon#wrote, iclass 14, count 0 2006.260.08:08:49.13#ibcon#about to read 3, iclass 14, count 0 2006.260.08:08:49.17#ibcon#read 3, iclass 14, count 0 2006.260.08:08:49.17#ibcon#about to read 4, iclass 14, count 0 2006.260.08:08:49.17#ibcon#read 4, iclass 14, count 0 2006.260.08:08:49.17#ibcon#about to read 5, iclass 14, count 0 2006.260.08:08:49.17#ibcon#read 5, iclass 14, count 0 2006.260.08:08:49.17#ibcon#about to read 6, iclass 14, count 0 2006.260.08:08:49.17#ibcon#read 6, iclass 14, count 0 2006.260.08:08:49.17#ibcon#end of sib2, iclass 14, count 0 2006.260.08:08:49.17#ibcon#*after write, iclass 14, count 0 2006.260.08:08:49.17#ibcon#*before return 0, iclass 14, count 0 2006.260.08:08:49.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:49.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:49.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:08:49.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:08:49.17$vc4f8/va=2,7 2006.260.08:08:49.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.08:08:49.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.08:08:49.17#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:49.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:49.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:49.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:49.23#ibcon#enter wrdev, iclass 16, count 2 2006.260.08:08:49.23#ibcon#first serial, iclass 16, count 2 2006.260.08:08:49.23#ibcon#enter sib2, iclass 16, count 2 2006.260.08:08:49.23#ibcon#flushed, iclass 16, count 2 2006.260.08:08:49.23#ibcon#about to write, iclass 16, count 2 2006.260.08:08:49.23#ibcon#wrote, iclass 16, count 2 2006.260.08:08:49.23#ibcon#about to read 3, iclass 16, count 2 2006.260.08:08:49.25#ibcon#read 3, iclass 16, count 2 2006.260.08:08:49.25#ibcon#about to read 4, iclass 16, count 2 2006.260.08:08:49.25#ibcon#read 4, iclass 16, count 2 2006.260.08:08:49.25#ibcon#about to read 5, iclass 16, count 2 2006.260.08:08:49.25#ibcon#read 5, iclass 16, count 2 2006.260.08:08:49.25#ibcon#about to read 6, iclass 16, count 2 2006.260.08:08:49.25#ibcon#read 6, iclass 16, count 2 2006.260.08:08:49.25#ibcon#end of sib2, iclass 16, count 2 2006.260.08:08:49.25#ibcon#*mode == 0, iclass 16, count 2 2006.260.08:08:49.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.08:08:49.25#ibcon#[25=AT02-07\r\n] 2006.260.08:08:49.25#ibcon#*before write, iclass 16, count 2 2006.260.08:08:49.25#ibcon#enter sib2, iclass 16, count 2 2006.260.08:08:49.25#ibcon#flushed, iclass 16, count 2 2006.260.08:08:49.25#ibcon#about to write, iclass 16, count 2 2006.260.08:08:49.25#ibcon#wrote, iclass 16, count 2 2006.260.08:08:49.25#ibcon#about to read 3, iclass 16, count 2 2006.260.08:08:49.28#ibcon#read 3, iclass 16, count 2 2006.260.08:08:49.28#ibcon#about to read 4, iclass 16, count 2 2006.260.08:08:49.28#ibcon#read 4, iclass 16, count 2 2006.260.08:08:49.28#ibcon#about to read 5, iclass 16, count 2 2006.260.08:08:49.28#ibcon#read 5, iclass 16, count 2 2006.260.08:08:49.28#ibcon#about to read 6, iclass 16, count 2 2006.260.08:08:49.28#ibcon#read 6, iclass 16, count 2 2006.260.08:08:49.28#ibcon#end of sib2, iclass 16, count 2 2006.260.08:08:49.28#ibcon#*after write, iclass 16, count 2 2006.260.08:08:49.28#ibcon#*before return 0, iclass 16, count 2 2006.260.08:08:49.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:49.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:49.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.08:08:49.28#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:49.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:49.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:49.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:49.41#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:08:49.41#ibcon#first serial, iclass 16, count 0 2006.260.08:08:49.41#ibcon#enter sib2, iclass 16, count 0 2006.260.08:08:49.41#ibcon#flushed, iclass 16, count 0 2006.260.08:08:49.41#ibcon#about to write, iclass 16, count 0 2006.260.08:08:49.41#ibcon#wrote, iclass 16, count 0 2006.260.08:08:49.41#ibcon#about to read 3, iclass 16, count 0 2006.260.08:08:49.43#ibcon#read 3, iclass 16, count 0 2006.260.08:08:49.43#ibcon#about to read 4, iclass 16, count 0 2006.260.08:08:49.43#ibcon#read 4, iclass 16, count 0 2006.260.08:08:49.43#ibcon#about to read 5, iclass 16, count 0 2006.260.08:08:49.43#ibcon#read 5, iclass 16, count 0 2006.260.08:08:49.43#ibcon#about to read 6, iclass 16, count 0 2006.260.08:08:49.43#ibcon#read 6, iclass 16, count 0 2006.260.08:08:49.43#ibcon#end of sib2, iclass 16, count 0 2006.260.08:08:49.43#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:08:49.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:08:49.43#ibcon#[25=USB\r\n] 2006.260.08:08:49.43#ibcon#*before write, iclass 16, count 0 2006.260.08:08:49.43#ibcon#enter sib2, iclass 16, count 0 2006.260.08:08:49.43#ibcon#flushed, iclass 16, count 0 2006.260.08:08:49.43#ibcon#about to write, iclass 16, count 0 2006.260.08:08:49.43#ibcon#wrote, iclass 16, count 0 2006.260.08:08:49.43#ibcon#about to read 3, iclass 16, count 0 2006.260.08:08:49.46#ibcon#read 3, iclass 16, count 0 2006.260.08:08:49.46#ibcon#about to read 4, iclass 16, count 0 2006.260.08:08:49.46#ibcon#read 4, iclass 16, count 0 2006.260.08:08:49.46#ibcon#about to read 5, iclass 16, count 0 2006.260.08:08:49.46#ibcon#read 5, iclass 16, count 0 2006.260.08:08:49.46#ibcon#about to read 6, iclass 16, count 0 2006.260.08:08:49.46#ibcon#read 6, iclass 16, count 0 2006.260.08:08:49.46#ibcon#end of sib2, iclass 16, count 0 2006.260.08:08:49.46#ibcon#*after write, iclass 16, count 0 2006.260.08:08:49.46#ibcon#*before return 0, iclass 16, count 0 2006.260.08:08:49.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:49.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:49.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:08:49.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:08:49.46$vc4f8/valo=3,672.99 2006.260.08:08:49.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.08:08:49.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.08:08:49.46#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:49.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:49.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:49.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:49.46#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:08:49.46#ibcon#first serial, iclass 18, count 0 2006.260.08:08:49.46#ibcon#enter sib2, iclass 18, count 0 2006.260.08:08:49.46#ibcon#flushed, iclass 18, count 0 2006.260.08:08:49.46#ibcon#about to write, iclass 18, count 0 2006.260.08:08:49.46#ibcon#wrote, iclass 18, count 0 2006.260.08:08:49.46#ibcon#about to read 3, iclass 18, count 0 2006.260.08:08:49.48#ibcon#read 3, iclass 18, count 0 2006.260.08:08:49.48#ibcon#about to read 4, iclass 18, count 0 2006.260.08:08:49.48#ibcon#read 4, iclass 18, count 0 2006.260.08:08:49.48#ibcon#about to read 5, iclass 18, count 0 2006.260.08:08:49.48#ibcon#read 5, iclass 18, count 0 2006.260.08:08:49.48#ibcon#about to read 6, iclass 18, count 0 2006.260.08:08:49.48#ibcon#read 6, iclass 18, count 0 2006.260.08:08:49.48#ibcon#end of sib2, iclass 18, count 0 2006.260.08:08:49.48#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:08:49.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:08:49.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:08:49.48#ibcon#*before write, iclass 18, count 0 2006.260.08:08:49.48#ibcon#enter sib2, iclass 18, count 0 2006.260.08:08:49.48#ibcon#flushed, iclass 18, count 0 2006.260.08:08:49.48#ibcon#about to write, iclass 18, count 0 2006.260.08:08:49.48#ibcon#wrote, iclass 18, count 0 2006.260.08:08:49.48#ibcon#about to read 3, iclass 18, count 0 2006.260.08:08:49.52#ibcon#read 3, iclass 18, count 0 2006.260.08:08:49.52#ibcon#about to read 4, iclass 18, count 0 2006.260.08:08:49.52#ibcon#read 4, iclass 18, count 0 2006.260.08:08:49.52#ibcon#about to read 5, iclass 18, count 0 2006.260.08:08:49.52#ibcon#read 5, iclass 18, count 0 2006.260.08:08:49.52#ibcon#about to read 6, iclass 18, count 0 2006.260.08:08:49.52#ibcon#read 6, iclass 18, count 0 2006.260.08:08:49.52#ibcon#end of sib2, iclass 18, count 0 2006.260.08:08:49.52#ibcon#*after write, iclass 18, count 0 2006.260.08:08:49.52#ibcon#*before return 0, iclass 18, count 0 2006.260.08:08:49.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:49.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:49.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:08:49.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:08:49.52$vc4f8/va=3,8 2006.260.08:08:49.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.08:08:49.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.08:08:49.52#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:49.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:49.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:49.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:49.58#ibcon#enter wrdev, iclass 20, count 2 2006.260.08:08:49.58#ibcon#first serial, iclass 20, count 2 2006.260.08:08:49.58#ibcon#enter sib2, iclass 20, count 2 2006.260.08:08:49.58#ibcon#flushed, iclass 20, count 2 2006.260.08:08:49.58#ibcon#about to write, iclass 20, count 2 2006.260.08:08:49.58#ibcon#wrote, iclass 20, count 2 2006.260.08:08:49.58#ibcon#about to read 3, iclass 20, count 2 2006.260.08:08:49.60#ibcon#read 3, iclass 20, count 2 2006.260.08:08:49.60#ibcon#about to read 4, iclass 20, count 2 2006.260.08:08:49.60#ibcon#read 4, iclass 20, count 2 2006.260.08:08:49.60#ibcon#about to read 5, iclass 20, count 2 2006.260.08:08:49.60#ibcon#read 5, iclass 20, count 2 2006.260.08:08:49.60#ibcon#about to read 6, iclass 20, count 2 2006.260.08:08:49.60#ibcon#read 6, iclass 20, count 2 2006.260.08:08:49.60#ibcon#end of sib2, iclass 20, count 2 2006.260.08:08:49.60#ibcon#*mode == 0, iclass 20, count 2 2006.260.08:08:49.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.08:08:49.60#ibcon#[25=AT03-08\r\n] 2006.260.08:08:49.60#ibcon#*before write, iclass 20, count 2 2006.260.08:08:49.60#ibcon#enter sib2, iclass 20, count 2 2006.260.08:08:49.60#ibcon#flushed, iclass 20, count 2 2006.260.08:08:49.60#ibcon#about to write, iclass 20, count 2 2006.260.08:08:49.60#ibcon#wrote, iclass 20, count 2 2006.260.08:08:49.60#ibcon#about to read 3, iclass 20, count 2 2006.260.08:08:49.63#ibcon#read 3, iclass 20, count 2 2006.260.08:08:49.63#ibcon#about to read 4, iclass 20, count 2 2006.260.08:08:49.63#ibcon#read 4, iclass 20, count 2 2006.260.08:08:49.63#ibcon#about to read 5, iclass 20, count 2 2006.260.08:08:49.63#ibcon#read 5, iclass 20, count 2 2006.260.08:08:49.63#ibcon#about to read 6, iclass 20, count 2 2006.260.08:08:49.63#ibcon#read 6, iclass 20, count 2 2006.260.08:08:49.63#ibcon#end of sib2, iclass 20, count 2 2006.260.08:08:49.63#ibcon#*after write, iclass 20, count 2 2006.260.08:08:49.63#ibcon#*before return 0, iclass 20, count 2 2006.260.08:08:49.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:49.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:49.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.08:08:49.63#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:49.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:49.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:49.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:49.75#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:08:49.75#ibcon#first serial, iclass 20, count 0 2006.260.08:08:49.75#ibcon#enter sib2, iclass 20, count 0 2006.260.08:08:49.75#ibcon#flushed, iclass 20, count 0 2006.260.08:08:49.75#ibcon#about to write, iclass 20, count 0 2006.260.08:08:49.75#ibcon#wrote, iclass 20, count 0 2006.260.08:08:49.75#ibcon#about to read 3, iclass 20, count 0 2006.260.08:08:49.77#ibcon#read 3, iclass 20, count 0 2006.260.08:08:49.77#ibcon#about to read 4, iclass 20, count 0 2006.260.08:08:49.77#ibcon#read 4, iclass 20, count 0 2006.260.08:08:49.77#ibcon#about to read 5, iclass 20, count 0 2006.260.08:08:49.77#ibcon#read 5, iclass 20, count 0 2006.260.08:08:49.77#ibcon#about to read 6, iclass 20, count 0 2006.260.08:08:49.77#ibcon#read 6, iclass 20, count 0 2006.260.08:08:49.77#ibcon#end of sib2, iclass 20, count 0 2006.260.08:08:49.77#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:08:49.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:08:49.77#ibcon#[25=USB\r\n] 2006.260.08:08:49.77#ibcon#*before write, iclass 20, count 0 2006.260.08:08:49.77#ibcon#enter sib2, iclass 20, count 0 2006.260.08:08:49.77#ibcon#flushed, iclass 20, count 0 2006.260.08:08:49.77#ibcon#about to write, iclass 20, count 0 2006.260.08:08:49.77#ibcon#wrote, iclass 20, count 0 2006.260.08:08:49.77#ibcon#about to read 3, iclass 20, count 0 2006.260.08:08:49.80#ibcon#read 3, iclass 20, count 0 2006.260.08:08:49.80#ibcon#about to read 4, iclass 20, count 0 2006.260.08:08:49.80#ibcon#read 4, iclass 20, count 0 2006.260.08:08:49.80#ibcon#about to read 5, iclass 20, count 0 2006.260.08:08:49.80#ibcon#read 5, iclass 20, count 0 2006.260.08:08:49.80#ibcon#about to read 6, iclass 20, count 0 2006.260.08:08:49.80#ibcon#read 6, iclass 20, count 0 2006.260.08:08:49.80#ibcon#end of sib2, iclass 20, count 0 2006.260.08:08:49.80#ibcon#*after write, iclass 20, count 0 2006.260.08:08:49.80#ibcon#*before return 0, iclass 20, count 0 2006.260.08:08:49.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:49.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:49.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:08:49.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:08:49.80$vc4f8/valo=4,832.99 2006.260.08:08:49.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.08:08:49.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.08:08:49.80#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:49.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:49.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:49.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:49.80#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:08:49.80#ibcon#first serial, iclass 22, count 0 2006.260.08:08:49.80#ibcon#enter sib2, iclass 22, count 0 2006.260.08:08:49.80#ibcon#flushed, iclass 22, count 0 2006.260.08:08:49.80#ibcon#about to write, iclass 22, count 0 2006.260.08:08:49.80#ibcon#wrote, iclass 22, count 0 2006.260.08:08:49.80#ibcon#about to read 3, iclass 22, count 0 2006.260.08:08:49.82#ibcon#read 3, iclass 22, count 0 2006.260.08:08:49.82#ibcon#about to read 4, iclass 22, count 0 2006.260.08:08:49.82#ibcon#read 4, iclass 22, count 0 2006.260.08:08:49.82#ibcon#about to read 5, iclass 22, count 0 2006.260.08:08:49.82#ibcon#read 5, iclass 22, count 0 2006.260.08:08:49.82#ibcon#about to read 6, iclass 22, count 0 2006.260.08:08:49.82#ibcon#read 6, iclass 22, count 0 2006.260.08:08:49.82#ibcon#end of sib2, iclass 22, count 0 2006.260.08:08:49.82#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:08:49.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:08:49.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:08:49.82#ibcon#*before write, iclass 22, count 0 2006.260.08:08:49.82#ibcon#enter sib2, iclass 22, count 0 2006.260.08:08:49.82#ibcon#flushed, iclass 22, count 0 2006.260.08:08:49.82#ibcon#about to write, iclass 22, count 0 2006.260.08:08:49.82#ibcon#wrote, iclass 22, count 0 2006.260.08:08:49.82#ibcon#about to read 3, iclass 22, count 0 2006.260.08:08:49.86#ibcon#read 3, iclass 22, count 0 2006.260.08:08:49.86#ibcon#about to read 4, iclass 22, count 0 2006.260.08:08:49.86#ibcon#read 4, iclass 22, count 0 2006.260.08:08:49.86#ibcon#about to read 5, iclass 22, count 0 2006.260.08:08:49.86#ibcon#read 5, iclass 22, count 0 2006.260.08:08:49.86#ibcon#about to read 6, iclass 22, count 0 2006.260.08:08:49.86#ibcon#read 6, iclass 22, count 0 2006.260.08:08:49.86#ibcon#end of sib2, iclass 22, count 0 2006.260.08:08:49.86#ibcon#*after write, iclass 22, count 0 2006.260.08:08:49.86#ibcon#*before return 0, iclass 22, count 0 2006.260.08:08:49.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:49.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:49.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:08:49.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:08:49.86$vc4f8/va=4,7 2006.260.08:08:49.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.08:08:49.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.08:08:49.86#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:49.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:49.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:49.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:49.92#ibcon#enter wrdev, iclass 24, count 2 2006.260.08:08:49.92#ibcon#first serial, iclass 24, count 2 2006.260.08:08:49.92#ibcon#enter sib2, iclass 24, count 2 2006.260.08:08:49.92#ibcon#flushed, iclass 24, count 2 2006.260.08:08:49.92#ibcon#about to write, iclass 24, count 2 2006.260.08:08:49.92#ibcon#wrote, iclass 24, count 2 2006.260.08:08:49.92#ibcon#about to read 3, iclass 24, count 2 2006.260.08:08:49.94#ibcon#read 3, iclass 24, count 2 2006.260.08:08:49.94#ibcon#about to read 4, iclass 24, count 2 2006.260.08:08:49.94#ibcon#read 4, iclass 24, count 2 2006.260.08:08:49.94#ibcon#about to read 5, iclass 24, count 2 2006.260.08:08:49.94#ibcon#read 5, iclass 24, count 2 2006.260.08:08:49.94#ibcon#about to read 6, iclass 24, count 2 2006.260.08:08:49.94#ibcon#read 6, iclass 24, count 2 2006.260.08:08:49.94#ibcon#end of sib2, iclass 24, count 2 2006.260.08:08:49.94#ibcon#*mode == 0, iclass 24, count 2 2006.260.08:08:49.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.08:08:49.94#ibcon#[25=AT04-07\r\n] 2006.260.08:08:49.94#ibcon#*before write, iclass 24, count 2 2006.260.08:08:49.94#ibcon#enter sib2, iclass 24, count 2 2006.260.08:08:49.94#ibcon#flushed, iclass 24, count 2 2006.260.08:08:49.94#ibcon#about to write, iclass 24, count 2 2006.260.08:08:49.94#ibcon#wrote, iclass 24, count 2 2006.260.08:08:49.94#ibcon#about to read 3, iclass 24, count 2 2006.260.08:08:49.97#ibcon#read 3, iclass 24, count 2 2006.260.08:08:49.97#ibcon#about to read 4, iclass 24, count 2 2006.260.08:08:49.97#ibcon#read 4, iclass 24, count 2 2006.260.08:08:49.97#ibcon#about to read 5, iclass 24, count 2 2006.260.08:08:49.97#ibcon#read 5, iclass 24, count 2 2006.260.08:08:49.97#ibcon#about to read 6, iclass 24, count 2 2006.260.08:08:49.97#ibcon#read 6, iclass 24, count 2 2006.260.08:08:49.97#ibcon#end of sib2, iclass 24, count 2 2006.260.08:08:49.97#ibcon#*after write, iclass 24, count 2 2006.260.08:08:49.97#ibcon#*before return 0, iclass 24, count 2 2006.260.08:08:49.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:49.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:49.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.08:08:49.97#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:49.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:50.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:50.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:50.09#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:08:50.09#ibcon#first serial, iclass 24, count 0 2006.260.08:08:50.09#ibcon#enter sib2, iclass 24, count 0 2006.260.08:08:50.09#ibcon#flushed, iclass 24, count 0 2006.260.08:08:50.09#ibcon#about to write, iclass 24, count 0 2006.260.08:08:50.09#ibcon#wrote, iclass 24, count 0 2006.260.08:08:50.09#ibcon#about to read 3, iclass 24, count 0 2006.260.08:08:50.11#ibcon#read 3, iclass 24, count 0 2006.260.08:08:50.11#ibcon#about to read 4, iclass 24, count 0 2006.260.08:08:50.11#ibcon#read 4, iclass 24, count 0 2006.260.08:08:50.11#ibcon#about to read 5, iclass 24, count 0 2006.260.08:08:50.11#ibcon#read 5, iclass 24, count 0 2006.260.08:08:50.11#ibcon#about to read 6, iclass 24, count 0 2006.260.08:08:50.11#ibcon#read 6, iclass 24, count 0 2006.260.08:08:50.11#ibcon#end of sib2, iclass 24, count 0 2006.260.08:08:50.11#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:08:50.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:08:50.11#ibcon#[25=USB\r\n] 2006.260.08:08:50.11#ibcon#*before write, iclass 24, count 0 2006.260.08:08:50.11#ibcon#enter sib2, iclass 24, count 0 2006.260.08:08:50.11#ibcon#flushed, iclass 24, count 0 2006.260.08:08:50.11#ibcon#about to write, iclass 24, count 0 2006.260.08:08:50.11#ibcon#wrote, iclass 24, count 0 2006.260.08:08:50.11#ibcon#about to read 3, iclass 24, count 0 2006.260.08:08:50.14#ibcon#read 3, iclass 24, count 0 2006.260.08:08:50.14#ibcon#about to read 4, iclass 24, count 0 2006.260.08:08:50.14#ibcon#read 4, iclass 24, count 0 2006.260.08:08:50.14#ibcon#about to read 5, iclass 24, count 0 2006.260.08:08:50.14#ibcon#read 5, iclass 24, count 0 2006.260.08:08:50.14#ibcon#about to read 6, iclass 24, count 0 2006.260.08:08:50.14#ibcon#read 6, iclass 24, count 0 2006.260.08:08:50.14#ibcon#end of sib2, iclass 24, count 0 2006.260.08:08:50.14#ibcon#*after write, iclass 24, count 0 2006.260.08:08:50.14#ibcon#*before return 0, iclass 24, count 0 2006.260.08:08:50.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:50.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:50.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:08:50.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:08:50.14$vc4f8/valo=5,652.99 2006.260.08:08:50.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.08:08:50.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.08:08:50.14#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:50.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:50.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:50.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:50.14#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:08:50.14#ibcon#first serial, iclass 26, count 0 2006.260.08:08:50.14#ibcon#enter sib2, iclass 26, count 0 2006.260.08:08:50.14#ibcon#flushed, iclass 26, count 0 2006.260.08:08:50.14#ibcon#about to write, iclass 26, count 0 2006.260.08:08:50.14#ibcon#wrote, iclass 26, count 0 2006.260.08:08:50.14#ibcon#about to read 3, iclass 26, count 0 2006.260.08:08:50.16#ibcon#read 3, iclass 26, count 0 2006.260.08:08:50.16#ibcon#about to read 4, iclass 26, count 0 2006.260.08:08:50.16#ibcon#read 4, iclass 26, count 0 2006.260.08:08:50.16#ibcon#about to read 5, iclass 26, count 0 2006.260.08:08:50.16#ibcon#read 5, iclass 26, count 0 2006.260.08:08:50.16#ibcon#about to read 6, iclass 26, count 0 2006.260.08:08:50.16#ibcon#read 6, iclass 26, count 0 2006.260.08:08:50.16#ibcon#end of sib2, iclass 26, count 0 2006.260.08:08:50.16#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:08:50.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:08:50.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:08:50.16#ibcon#*before write, iclass 26, count 0 2006.260.08:08:50.16#ibcon#enter sib2, iclass 26, count 0 2006.260.08:08:50.16#ibcon#flushed, iclass 26, count 0 2006.260.08:08:50.16#ibcon#about to write, iclass 26, count 0 2006.260.08:08:50.16#ibcon#wrote, iclass 26, count 0 2006.260.08:08:50.16#ibcon#about to read 3, iclass 26, count 0 2006.260.08:08:50.20#ibcon#read 3, iclass 26, count 0 2006.260.08:08:50.20#ibcon#about to read 4, iclass 26, count 0 2006.260.08:08:50.20#ibcon#read 4, iclass 26, count 0 2006.260.08:08:50.20#ibcon#about to read 5, iclass 26, count 0 2006.260.08:08:50.20#ibcon#read 5, iclass 26, count 0 2006.260.08:08:50.20#ibcon#about to read 6, iclass 26, count 0 2006.260.08:08:50.20#ibcon#read 6, iclass 26, count 0 2006.260.08:08:50.20#ibcon#end of sib2, iclass 26, count 0 2006.260.08:08:50.20#ibcon#*after write, iclass 26, count 0 2006.260.08:08:50.20#ibcon#*before return 0, iclass 26, count 0 2006.260.08:08:50.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:50.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:50.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:08:50.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:08:50.20$vc4f8/va=5,7 2006.260.08:08:50.20#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.08:08:50.20#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.08:08:50.20#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:50.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:50.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:50.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:50.26#ibcon#enter wrdev, iclass 28, count 2 2006.260.08:08:50.26#ibcon#first serial, iclass 28, count 2 2006.260.08:08:50.26#ibcon#enter sib2, iclass 28, count 2 2006.260.08:08:50.26#ibcon#flushed, iclass 28, count 2 2006.260.08:08:50.26#ibcon#about to write, iclass 28, count 2 2006.260.08:08:50.26#ibcon#wrote, iclass 28, count 2 2006.260.08:08:50.26#ibcon#about to read 3, iclass 28, count 2 2006.260.08:08:50.28#ibcon#read 3, iclass 28, count 2 2006.260.08:08:50.28#ibcon#about to read 4, iclass 28, count 2 2006.260.08:08:50.28#ibcon#read 4, iclass 28, count 2 2006.260.08:08:50.28#ibcon#about to read 5, iclass 28, count 2 2006.260.08:08:50.28#ibcon#read 5, iclass 28, count 2 2006.260.08:08:50.28#ibcon#about to read 6, iclass 28, count 2 2006.260.08:08:50.28#ibcon#read 6, iclass 28, count 2 2006.260.08:08:50.28#ibcon#end of sib2, iclass 28, count 2 2006.260.08:08:50.28#ibcon#*mode == 0, iclass 28, count 2 2006.260.08:08:50.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.08:08:50.28#ibcon#[25=AT05-07\r\n] 2006.260.08:08:50.28#ibcon#*before write, iclass 28, count 2 2006.260.08:08:50.28#ibcon#enter sib2, iclass 28, count 2 2006.260.08:08:50.28#ibcon#flushed, iclass 28, count 2 2006.260.08:08:50.28#ibcon#about to write, iclass 28, count 2 2006.260.08:08:50.28#ibcon#wrote, iclass 28, count 2 2006.260.08:08:50.28#ibcon#about to read 3, iclass 28, count 2 2006.260.08:08:50.31#ibcon#read 3, iclass 28, count 2 2006.260.08:08:50.31#ibcon#about to read 4, iclass 28, count 2 2006.260.08:08:50.31#ibcon#read 4, iclass 28, count 2 2006.260.08:08:50.31#ibcon#about to read 5, iclass 28, count 2 2006.260.08:08:50.31#ibcon#read 5, iclass 28, count 2 2006.260.08:08:50.31#ibcon#about to read 6, iclass 28, count 2 2006.260.08:08:50.31#ibcon#read 6, iclass 28, count 2 2006.260.08:08:50.31#ibcon#end of sib2, iclass 28, count 2 2006.260.08:08:50.31#ibcon#*after write, iclass 28, count 2 2006.260.08:08:50.31#ibcon#*before return 0, iclass 28, count 2 2006.260.08:08:50.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:50.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:50.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.08:08:50.31#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:50.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:50.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:50.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:50.43#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:08:50.43#ibcon#first serial, iclass 28, count 0 2006.260.08:08:50.43#ibcon#enter sib2, iclass 28, count 0 2006.260.08:08:50.43#ibcon#flushed, iclass 28, count 0 2006.260.08:08:50.43#ibcon#about to write, iclass 28, count 0 2006.260.08:08:50.43#ibcon#wrote, iclass 28, count 0 2006.260.08:08:50.43#ibcon#about to read 3, iclass 28, count 0 2006.260.08:08:50.45#ibcon#read 3, iclass 28, count 0 2006.260.08:08:50.45#ibcon#about to read 4, iclass 28, count 0 2006.260.08:08:50.45#ibcon#read 4, iclass 28, count 0 2006.260.08:08:50.45#ibcon#about to read 5, iclass 28, count 0 2006.260.08:08:50.45#ibcon#read 5, iclass 28, count 0 2006.260.08:08:50.45#ibcon#about to read 6, iclass 28, count 0 2006.260.08:08:50.45#ibcon#read 6, iclass 28, count 0 2006.260.08:08:50.45#ibcon#end of sib2, iclass 28, count 0 2006.260.08:08:50.45#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:08:50.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:08:50.45#ibcon#[25=USB\r\n] 2006.260.08:08:50.45#ibcon#*before write, iclass 28, count 0 2006.260.08:08:50.45#ibcon#enter sib2, iclass 28, count 0 2006.260.08:08:50.45#ibcon#flushed, iclass 28, count 0 2006.260.08:08:50.45#ibcon#about to write, iclass 28, count 0 2006.260.08:08:50.45#ibcon#wrote, iclass 28, count 0 2006.260.08:08:50.45#ibcon#about to read 3, iclass 28, count 0 2006.260.08:08:50.48#ibcon#read 3, iclass 28, count 0 2006.260.08:08:50.48#ibcon#about to read 4, iclass 28, count 0 2006.260.08:08:50.48#ibcon#read 4, iclass 28, count 0 2006.260.08:08:50.48#ibcon#about to read 5, iclass 28, count 0 2006.260.08:08:50.48#ibcon#read 5, iclass 28, count 0 2006.260.08:08:50.48#ibcon#about to read 6, iclass 28, count 0 2006.260.08:08:50.48#ibcon#read 6, iclass 28, count 0 2006.260.08:08:50.48#ibcon#end of sib2, iclass 28, count 0 2006.260.08:08:50.48#ibcon#*after write, iclass 28, count 0 2006.260.08:08:50.48#ibcon#*before return 0, iclass 28, count 0 2006.260.08:08:50.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:50.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:50.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:08:50.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:08:50.48$vc4f8/valo=6,772.99 2006.260.08:08:50.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.08:08:50.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.08:08:50.48#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:50.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:08:50.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:08:50.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:08:50.48#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:08:50.48#ibcon#first serial, iclass 30, count 0 2006.260.08:08:50.48#ibcon#enter sib2, iclass 30, count 0 2006.260.08:08:50.48#ibcon#flushed, iclass 30, count 0 2006.260.08:08:50.48#ibcon#about to write, iclass 30, count 0 2006.260.08:08:50.48#ibcon#wrote, iclass 30, count 0 2006.260.08:08:50.48#ibcon#about to read 3, iclass 30, count 0 2006.260.08:08:50.50#ibcon#read 3, iclass 30, count 0 2006.260.08:08:50.50#ibcon#about to read 4, iclass 30, count 0 2006.260.08:08:50.50#ibcon#read 4, iclass 30, count 0 2006.260.08:08:50.50#ibcon#about to read 5, iclass 30, count 0 2006.260.08:08:50.50#ibcon#read 5, iclass 30, count 0 2006.260.08:08:50.50#ibcon#about to read 6, iclass 30, count 0 2006.260.08:08:50.50#ibcon#read 6, iclass 30, count 0 2006.260.08:08:50.50#ibcon#end of sib2, iclass 30, count 0 2006.260.08:08:50.50#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:08:50.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:08:50.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:08:50.50#ibcon#*before write, iclass 30, count 0 2006.260.08:08:50.50#ibcon#enter sib2, iclass 30, count 0 2006.260.08:08:50.50#ibcon#flushed, iclass 30, count 0 2006.260.08:08:50.50#ibcon#about to write, iclass 30, count 0 2006.260.08:08:50.50#ibcon#wrote, iclass 30, count 0 2006.260.08:08:50.50#ibcon#about to read 3, iclass 30, count 0 2006.260.08:08:50.54#ibcon#read 3, iclass 30, count 0 2006.260.08:08:50.54#ibcon#about to read 4, iclass 30, count 0 2006.260.08:08:50.54#ibcon#read 4, iclass 30, count 0 2006.260.08:08:50.54#ibcon#about to read 5, iclass 30, count 0 2006.260.08:08:50.54#ibcon#read 5, iclass 30, count 0 2006.260.08:08:50.54#ibcon#about to read 6, iclass 30, count 0 2006.260.08:08:50.54#ibcon#read 6, iclass 30, count 0 2006.260.08:08:50.54#ibcon#end of sib2, iclass 30, count 0 2006.260.08:08:50.54#ibcon#*after write, iclass 30, count 0 2006.260.08:08:50.54#ibcon#*before return 0, iclass 30, count 0 2006.260.08:08:50.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:08:50.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:08:50.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:08:50.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:08:50.54$vc4f8/va=6,6 2006.260.08:08:50.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.08:08:50.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.08:08:50.54#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:50.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:08:50.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:08:50.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:08:50.60#ibcon#enter wrdev, iclass 32, count 2 2006.260.08:08:50.60#ibcon#first serial, iclass 32, count 2 2006.260.08:08:50.60#ibcon#enter sib2, iclass 32, count 2 2006.260.08:08:50.60#ibcon#flushed, iclass 32, count 2 2006.260.08:08:50.60#ibcon#about to write, iclass 32, count 2 2006.260.08:08:50.60#ibcon#wrote, iclass 32, count 2 2006.260.08:08:50.60#ibcon#about to read 3, iclass 32, count 2 2006.260.08:08:50.62#ibcon#read 3, iclass 32, count 2 2006.260.08:08:50.62#ibcon#about to read 4, iclass 32, count 2 2006.260.08:08:50.62#ibcon#read 4, iclass 32, count 2 2006.260.08:08:50.62#ibcon#about to read 5, iclass 32, count 2 2006.260.08:08:50.62#ibcon#read 5, iclass 32, count 2 2006.260.08:08:50.62#ibcon#about to read 6, iclass 32, count 2 2006.260.08:08:50.62#ibcon#read 6, iclass 32, count 2 2006.260.08:08:50.62#ibcon#end of sib2, iclass 32, count 2 2006.260.08:08:50.62#ibcon#*mode == 0, iclass 32, count 2 2006.260.08:08:50.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.08:08:50.62#ibcon#[25=AT06-06\r\n] 2006.260.08:08:50.62#ibcon#*before write, iclass 32, count 2 2006.260.08:08:50.62#ibcon#enter sib2, iclass 32, count 2 2006.260.08:08:50.62#ibcon#flushed, iclass 32, count 2 2006.260.08:08:50.62#ibcon#about to write, iclass 32, count 2 2006.260.08:08:50.62#ibcon#wrote, iclass 32, count 2 2006.260.08:08:50.62#ibcon#about to read 3, iclass 32, count 2 2006.260.08:08:50.65#ibcon#read 3, iclass 32, count 2 2006.260.08:08:50.65#ibcon#about to read 4, iclass 32, count 2 2006.260.08:08:50.65#ibcon#read 4, iclass 32, count 2 2006.260.08:08:50.65#ibcon#about to read 5, iclass 32, count 2 2006.260.08:08:50.65#ibcon#read 5, iclass 32, count 2 2006.260.08:08:50.65#ibcon#about to read 6, iclass 32, count 2 2006.260.08:08:50.65#ibcon#read 6, iclass 32, count 2 2006.260.08:08:50.65#ibcon#end of sib2, iclass 32, count 2 2006.260.08:08:50.65#ibcon#*after write, iclass 32, count 2 2006.260.08:08:50.65#ibcon#*before return 0, iclass 32, count 2 2006.260.08:08:50.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:08:50.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:08:50.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.08:08:50.65#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:50.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:08:50.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:08:50.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:08:50.77#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:08:50.77#ibcon#first serial, iclass 32, count 0 2006.260.08:08:50.77#ibcon#enter sib2, iclass 32, count 0 2006.260.08:08:50.77#ibcon#flushed, iclass 32, count 0 2006.260.08:08:50.77#ibcon#about to write, iclass 32, count 0 2006.260.08:08:50.77#ibcon#wrote, iclass 32, count 0 2006.260.08:08:50.77#ibcon#about to read 3, iclass 32, count 0 2006.260.08:08:50.79#ibcon#read 3, iclass 32, count 0 2006.260.08:08:50.79#ibcon#about to read 4, iclass 32, count 0 2006.260.08:08:50.79#ibcon#read 4, iclass 32, count 0 2006.260.08:08:50.79#ibcon#about to read 5, iclass 32, count 0 2006.260.08:08:50.79#ibcon#read 5, iclass 32, count 0 2006.260.08:08:50.79#ibcon#about to read 6, iclass 32, count 0 2006.260.08:08:50.79#ibcon#read 6, iclass 32, count 0 2006.260.08:08:50.79#ibcon#end of sib2, iclass 32, count 0 2006.260.08:08:50.79#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:08:50.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:08:50.79#ibcon#[25=USB\r\n] 2006.260.08:08:50.79#ibcon#*before write, iclass 32, count 0 2006.260.08:08:50.79#ibcon#enter sib2, iclass 32, count 0 2006.260.08:08:50.79#ibcon#flushed, iclass 32, count 0 2006.260.08:08:50.79#ibcon#about to write, iclass 32, count 0 2006.260.08:08:50.79#ibcon#wrote, iclass 32, count 0 2006.260.08:08:50.79#ibcon#about to read 3, iclass 32, count 0 2006.260.08:08:50.82#ibcon#read 3, iclass 32, count 0 2006.260.08:08:50.82#ibcon#about to read 4, iclass 32, count 0 2006.260.08:08:50.82#ibcon#read 4, iclass 32, count 0 2006.260.08:08:50.82#ibcon#about to read 5, iclass 32, count 0 2006.260.08:08:50.82#ibcon#read 5, iclass 32, count 0 2006.260.08:08:50.82#ibcon#about to read 6, iclass 32, count 0 2006.260.08:08:50.82#ibcon#read 6, iclass 32, count 0 2006.260.08:08:50.82#ibcon#end of sib2, iclass 32, count 0 2006.260.08:08:50.82#ibcon#*after write, iclass 32, count 0 2006.260.08:08:50.82#ibcon#*before return 0, iclass 32, count 0 2006.260.08:08:50.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:08:50.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:08:50.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:08:50.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:08:50.82$vc4f8/valo=7,832.99 2006.260.08:08:50.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.08:08:50.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.08:08:50.82#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:50.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:50.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:50.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:50.82#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:08:50.82#ibcon#first serial, iclass 34, count 0 2006.260.08:08:50.82#ibcon#enter sib2, iclass 34, count 0 2006.260.08:08:50.82#ibcon#flushed, iclass 34, count 0 2006.260.08:08:50.82#ibcon#about to write, iclass 34, count 0 2006.260.08:08:50.82#ibcon#wrote, iclass 34, count 0 2006.260.08:08:50.82#ibcon#about to read 3, iclass 34, count 0 2006.260.08:08:50.84#ibcon#read 3, iclass 34, count 0 2006.260.08:08:50.84#ibcon#about to read 4, iclass 34, count 0 2006.260.08:08:50.84#ibcon#read 4, iclass 34, count 0 2006.260.08:08:50.84#ibcon#about to read 5, iclass 34, count 0 2006.260.08:08:50.84#ibcon#read 5, iclass 34, count 0 2006.260.08:08:50.84#ibcon#about to read 6, iclass 34, count 0 2006.260.08:08:50.84#ibcon#read 6, iclass 34, count 0 2006.260.08:08:50.84#ibcon#end of sib2, iclass 34, count 0 2006.260.08:08:50.84#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:08:50.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:08:50.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:08:50.84#ibcon#*before write, iclass 34, count 0 2006.260.08:08:50.84#ibcon#enter sib2, iclass 34, count 0 2006.260.08:08:50.84#ibcon#flushed, iclass 34, count 0 2006.260.08:08:50.84#ibcon#about to write, iclass 34, count 0 2006.260.08:08:50.84#ibcon#wrote, iclass 34, count 0 2006.260.08:08:50.84#ibcon#about to read 3, iclass 34, count 0 2006.260.08:08:50.88#ibcon#read 3, iclass 34, count 0 2006.260.08:08:50.88#ibcon#about to read 4, iclass 34, count 0 2006.260.08:08:50.88#ibcon#read 4, iclass 34, count 0 2006.260.08:08:50.88#ibcon#about to read 5, iclass 34, count 0 2006.260.08:08:50.88#ibcon#read 5, iclass 34, count 0 2006.260.08:08:50.88#ibcon#about to read 6, iclass 34, count 0 2006.260.08:08:50.88#ibcon#read 6, iclass 34, count 0 2006.260.08:08:50.88#ibcon#end of sib2, iclass 34, count 0 2006.260.08:08:50.88#ibcon#*after write, iclass 34, count 0 2006.260.08:08:50.88#ibcon#*before return 0, iclass 34, count 0 2006.260.08:08:50.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:50.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:50.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:08:50.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:08:50.88$vc4f8/va=7,6 2006.260.08:08:50.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.08:08:50.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.08:08:50.88#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:50.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:50.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:50.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:50.94#ibcon#enter wrdev, iclass 36, count 2 2006.260.08:08:50.94#ibcon#first serial, iclass 36, count 2 2006.260.08:08:50.94#ibcon#enter sib2, iclass 36, count 2 2006.260.08:08:50.94#ibcon#flushed, iclass 36, count 2 2006.260.08:08:50.94#ibcon#about to write, iclass 36, count 2 2006.260.08:08:50.94#ibcon#wrote, iclass 36, count 2 2006.260.08:08:50.94#ibcon#about to read 3, iclass 36, count 2 2006.260.08:08:50.96#ibcon#read 3, iclass 36, count 2 2006.260.08:08:50.96#ibcon#about to read 4, iclass 36, count 2 2006.260.08:08:50.96#ibcon#read 4, iclass 36, count 2 2006.260.08:08:50.96#ibcon#about to read 5, iclass 36, count 2 2006.260.08:08:50.96#ibcon#read 5, iclass 36, count 2 2006.260.08:08:50.96#ibcon#about to read 6, iclass 36, count 2 2006.260.08:08:50.96#ibcon#read 6, iclass 36, count 2 2006.260.08:08:50.96#ibcon#end of sib2, iclass 36, count 2 2006.260.08:08:50.96#ibcon#*mode == 0, iclass 36, count 2 2006.260.08:08:50.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.08:08:50.96#ibcon#[25=AT07-06\r\n] 2006.260.08:08:50.96#ibcon#*before write, iclass 36, count 2 2006.260.08:08:50.96#ibcon#enter sib2, iclass 36, count 2 2006.260.08:08:50.96#ibcon#flushed, iclass 36, count 2 2006.260.08:08:50.96#ibcon#about to write, iclass 36, count 2 2006.260.08:08:50.96#ibcon#wrote, iclass 36, count 2 2006.260.08:08:50.96#ibcon#about to read 3, iclass 36, count 2 2006.260.08:08:50.99#ibcon#read 3, iclass 36, count 2 2006.260.08:08:50.99#ibcon#about to read 4, iclass 36, count 2 2006.260.08:08:50.99#ibcon#read 4, iclass 36, count 2 2006.260.08:08:50.99#ibcon#about to read 5, iclass 36, count 2 2006.260.08:08:50.99#ibcon#read 5, iclass 36, count 2 2006.260.08:08:50.99#ibcon#about to read 6, iclass 36, count 2 2006.260.08:08:50.99#ibcon#read 6, iclass 36, count 2 2006.260.08:08:50.99#ibcon#end of sib2, iclass 36, count 2 2006.260.08:08:50.99#ibcon#*after write, iclass 36, count 2 2006.260.08:08:50.99#ibcon#*before return 0, iclass 36, count 2 2006.260.08:08:50.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:50.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:50.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.08:08:50.99#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:50.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:08:51.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:08:51.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:08:51.11#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:08:51.11#ibcon#first serial, iclass 36, count 0 2006.260.08:08:51.11#ibcon#enter sib2, iclass 36, count 0 2006.260.08:08:51.11#ibcon#flushed, iclass 36, count 0 2006.260.08:08:51.11#ibcon#about to write, iclass 36, count 0 2006.260.08:08:51.11#ibcon#wrote, iclass 36, count 0 2006.260.08:08:51.11#ibcon#about to read 3, iclass 36, count 0 2006.260.08:08:51.13#ibcon#read 3, iclass 36, count 0 2006.260.08:08:51.13#ibcon#about to read 4, iclass 36, count 0 2006.260.08:08:51.13#ibcon#read 4, iclass 36, count 0 2006.260.08:08:51.13#ibcon#about to read 5, iclass 36, count 0 2006.260.08:08:51.13#ibcon#read 5, iclass 36, count 0 2006.260.08:08:51.13#ibcon#about to read 6, iclass 36, count 0 2006.260.08:08:51.13#ibcon#read 6, iclass 36, count 0 2006.260.08:08:51.13#ibcon#end of sib2, iclass 36, count 0 2006.260.08:08:51.13#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:08:51.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:08:51.13#ibcon#[25=USB\r\n] 2006.260.08:08:51.13#ibcon#*before write, iclass 36, count 0 2006.260.08:08:51.13#ibcon#enter sib2, iclass 36, count 0 2006.260.08:08:51.13#ibcon#flushed, iclass 36, count 0 2006.260.08:08:51.13#ibcon#about to write, iclass 36, count 0 2006.260.08:08:51.13#ibcon#wrote, iclass 36, count 0 2006.260.08:08:51.13#ibcon#about to read 3, iclass 36, count 0 2006.260.08:08:51.16#ibcon#read 3, iclass 36, count 0 2006.260.08:08:51.16#ibcon#about to read 4, iclass 36, count 0 2006.260.08:08:51.16#ibcon#read 4, iclass 36, count 0 2006.260.08:08:51.16#ibcon#about to read 5, iclass 36, count 0 2006.260.08:08:51.16#ibcon#read 5, iclass 36, count 0 2006.260.08:08:51.16#ibcon#about to read 6, iclass 36, count 0 2006.260.08:08:51.16#ibcon#read 6, iclass 36, count 0 2006.260.08:08:51.16#ibcon#end of sib2, iclass 36, count 0 2006.260.08:08:51.16#ibcon#*after write, iclass 36, count 0 2006.260.08:08:51.16#ibcon#*before return 0, iclass 36, count 0 2006.260.08:08:51.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:08:51.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:08:51.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:08:51.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:08:51.16$vc4f8/valo=8,852.99 2006.260.08:08:51.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.08:08:51.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.08:08:51.16#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:51.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:08:51.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:08:51.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:08:51.16#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:08:51.16#ibcon#first serial, iclass 38, count 0 2006.260.08:08:51.16#ibcon#enter sib2, iclass 38, count 0 2006.260.08:08:51.16#ibcon#flushed, iclass 38, count 0 2006.260.08:08:51.16#ibcon#about to write, iclass 38, count 0 2006.260.08:08:51.16#ibcon#wrote, iclass 38, count 0 2006.260.08:08:51.16#ibcon#about to read 3, iclass 38, count 0 2006.260.08:08:51.18#ibcon#read 3, iclass 38, count 0 2006.260.08:08:51.18#ibcon#about to read 4, iclass 38, count 0 2006.260.08:08:51.18#ibcon#read 4, iclass 38, count 0 2006.260.08:08:51.18#ibcon#about to read 5, iclass 38, count 0 2006.260.08:08:51.18#ibcon#read 5, iclass 38, count 0 2006.260.08:08:51.18#ibcon#about to read 6, iclass 38, count 0 2006.260.08:08:51.18#ibcon#read 6, iclass 38, count 0 2006.260.08:08:51.18#ibcon#end of sib2, iclass 38, count 0 2006.260.08:08:51.18#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:08:51.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:08:51.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:08:51.18#ibcon#*before write, iclass 38, count 0 2006.260.08:08:51.18#ibcon#enter sib2, iclass 38, count 0 2006.260.08:08:51.18#ibcon#flushed, iclass 38, count 0 2006.260.08:08:51.18#ibcon#about to write, iclass 38, count 0 2006.260.08:08:51.18#ibcon#wrote, iclass 38, count 0 2006.260.08:08:51.18#ibcon#about to read 3, iclass 38, count 0 2006.260.08:08:51.22#ibcon#read 3, iclass 38, count 0 2006.260.08:08:51.22#ibcon#about to read 4, iclass 38, count 0 2006.260.08:08:51.22#ibcon#read 4, iclass 38, count 0 2006.260.08:08:51.22#ibcon#about to read 5, iclass 38, count 0 2006.260.08:08:51.22#ibcon#read 5, iclass 38, count 0 2006.260.08:08:51.22#ibcon#about to read 6, iclass 38, count 0 2006.260.08:08:51.22#ibcon#read 6, iclass 38, count 0 2006.260.08:08:51.22#ibcon#end of sib2, iclass 38, count 0 2006.260.08:08:51.22#ibcon#*after write, iclass 38, count 0 2006.260.08:08:51.22#ibcon#*before return 0, iclass 38, count 0 2006.260.08:08:51.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:08:51.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:08:51.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:08:51.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:08:51.22$vc4f8/va=8,6 2006.260.08:08:51.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.08:08:51.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.08:08:51.22#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:51.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:08:51.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:08:51.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:08:51.28#ibcon#enter wrdev, iclass 40, count 2 2006.260.08:08:51.28#ibcon#first serial, iclass 40, count 2 2006.260.08:08:51.28#ibcon#enter sib2, iclass 40, count 2 2006.260.08:08:51.28#ibcon#flushed, iclass 40, count 2 2006.260.08:08:51.28#ibcon#about to write, iclass 40, count 2 2006.260.08:08:51.28#ibcon#wrote, iclass 40, count 2 2006.260.08:08:51.28#ibcon#about to read 3, iclass 40, count 2 2006.260.08:08:51.30#ibcon#read 3, iclass 40, count 2 2006.260.08:08:51.30#ibcon#about to read 4, iclass 40, count 2 2006.260.08:08:51.30#ibcon#read 4, iclass 40, count 2 2006.260.08:08:51.30#ibcon#about to read 5, iclass 40, count 2 2006.260.08:08:51.30#ibcon#read 5, iclass 40, count 2 2006.260.08:08:51.30#ibcon#about to read 6, iclass 40, count 2 2006.260.08:08:51.30#ibcon#read 6, iclass 40, count 2 2006.260.08:08:51.30#ibcon#end of sib2, iclass 40, count 2 2006.260.08:08:51.30#ibcon#*mode == 0, iclass 40, count 2 2006.260.08:08:51.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.08:08:51.30#ibcon#[25=AT08-06\r\n] 2006.260.08:08:51.30#ibcon#*before write, iclass 40, count 2 2006.260.08:08:51.30#ibcon#enter sib2, iclass 40, count 2 2006.260.08:08:51.30#ibcon#flushed, iclass 40, count 2 2006.260.08:08:51.30#ibcon#about to write, iclass 40, count 2 2006.260.08:08:51.30#ibcon#wrote, iclass 40, count 2 2006.260.08:08:51.30#ibcon#about to read 3, iclass 40, count 2 2006.260.08:08:51.33#ibcon#read 3, iclass 40, count 2 2006.260.08:08:51.33#ibcon#about to read 4, iclass 40, count 2 2006.260.08:08:51.33#ibcon#read 4, iclass 40, count 2 2006.260.08:08:51.33#ibcon#about to read 5, iclass 40, count 2 2006.260.08:08:51.33#ibcon#read 5, iclass 40, count 2 2006.260.08:08:51.33#ibcon#about to read 6, iclass 40, count 2 2006.260.08:08:51.33#ibcon#read 6, iclass 40, count 2 2006.260.08:08:51.33#ibcon#end of sib2, iclass 40, count 2 2006.260.08:08:51.33#ibcon#*after write, iclass 40, count 2 2006.260.08:08:51.33#ibcon#*before return 0, iclass 40, count 2 2006.260.08:08:51.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:08:51.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:08:51.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.08:08:51.33#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:51.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:08:51.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:08:51.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:08:51.45#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:08:51.45#ibcon#first serial, iclass 40, count 0 2006.260.08:08:51.45#ibcon#enter sib2, iclass 40, count 0 2006.260.08:08:51.45#ibcon#flushed, iclass 40, count 0 2006.260.08:08:51.45#ibcon#about to write, iclass 40, count 0 2006.260.08:08:51.45#ibcon#wrote, iclass 40, count 0 2006.260.08:08:51.45#ibcon#about to read 3, iclass 40, count 0 2006.260.08:08:51.47#ibcon#read 3, iclass 40, count 0 2006.260.08:08:51.47#ibcon#about to read 4, iclass 40, count 0 2006.260.08:08:51.47#ibcon#read 4, iclass 40, count 0 2006.260.08:08:51.47#ibcon#about to read 5, iclass 40, count 0 2006.260.08:08:51.47#ibcon#read 5, iclass 40, count 0 2006.260.08:08:51.47#ibcon#about to read 6, iclass 40, count 0 2006.260.08:08:51.47#ibcon#read 6, iclass 40, count 0 2006.260.08:08:51.47#ibcon#end of sib2, iclass 40, count 0 2006.260.08:08:51.47#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:08:51.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:08:51.47#ibcon#[25=USB\r\n] 2006.260.08:08:51.47#ibcon#*before write, iclass 40, count 0 2006.260.08:08:51.47#ibcon#enter sib2, iclass 40, count 0 2006.260.08:08:51.47#ibcon#flushed, iclass 40, count 0 2006.260.08:08:51.47#ibcon#about to write, iclass 40, count 0 2006.260.08:08:51.47#ibcon#wrote, iclass 40, count 0 2006.260.08:08:51.47#ibcon#about to read 3, iclass 40, count 0 2006.260.08:08:51.50#ibcon#read 3, iclass 40, count 0 2006.260.08:08:51.50#ibcon#about to read 4, iclass 40, count 0 2006.260.08:08:51.50#ibcon#read 4, iclass 40, count 0 2006.260.08:08:51.50#ibcon#about to read 5, iclass 40, count 0 2006.260.08:08:51.50#ibcon#read 5, iclass 40, count 0 2006.260.08:08:51.50#ibcon#about to read 6, iclass 40, count 0 2006.260.08:08:51.50#ibcon#read 6, iclass 40, count 0 2006.260.08:08:51.50#ibcon#end of sib2, iclass 40, count 0 2006.260.08:08:51.50#ibcon#*after write, iclass 40, count 0 2006.260.08:08:51.50#ibcon#*before return 0, iclass 40, count 0 2006.260.08:08:51.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:08:51.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:08:51.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:08:51.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:08:51.50$vc4f8/vblo=1,632.99 2006.260.08:08:51.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.08:08:51.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.08:08:51.50#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:51.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:08:51.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:08:51.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:08:51.50#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:08:51.50#ibcon#first serial, iclass 4, count 0 2006.260.08:08:51.50#ibcon#enter sib2, iclass 4, count 0 2006.260.08:08:51.50#ibcon#flushed, iclass 4, count 0 2006.260.08:08:51.50#ibcon#about to write, iclass 4, count 0 2006.260.08:08:51.50#ibcon#wrote, iclass 4, count 0 2006.260.08:08:51.50#ibcon#about to read 3, iclass 4, count 0 2006.260.08:08:51.52#ibcon#read 3, iclass 4, count 0 2006.260.08:08:51.52#ibcon#about to read 4, iclass 4, count 0 2006.260.08:08:51.52#ibcon#read 4, iclass 4, count 0 2006.260.08:08:51.52#ibcon#about to read 5, iclass 4, count 0 2006.260.08:08:51.52#ibcon#read 5, iclass 4, count 0 2006.260.08:08:51.52#ibcon#about to read 6, iclass 4, count 0 2006.260.08:08:51.52#ibcon#read 6, iclass 4, count 0 2006.260.08:08:51.52#ibcon#end of sib2, iclass 4, count 0 2006.260.08:08:51.52#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:08:51.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:08:51.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:08:51.52#ibcon#*before write, iclass 4, count 0 2006.260.08:08:51.52#ibcon#enter sib2, iclass 4, count 0 2006.260.08:08:51.52#ibcon#flushed, iclass 4, count 0 2006.260.08:08:51.52#ibcon#about to write, iclass 4, count 0 2006.260.08:08:51.52#ibcon#wrote, iclass 4, count 0 2006.260.08:08:51.52#ibcon#about to read 3, iclass 4, count 0 2006.260.08:08:51.56#ibcon#read 3, iclass 4, count 0 2006.260.08:08:51.56#ibcon#about to read 4, iclass 4, count 0 2006.260.08:08:51.56#ibcon#read 4, iclass 4, count 0 2006.260.08:08:51.56#ibcon#about to read 5, iclass 4, count 0 2006.260.08:08:51.56#ibcon#read 5, iclass 4, count 0 2006.260.08:08:51.56#ibcon#about to read 6, iclass 4, count 0 2006.260.08:08:51.56#ibcon#read 6, iclass 4, count 0 2006.260.08:08:51.56#ibcon#end of sib2, iclass 4, count 0 2006.260.08:08:51.56#ibcon#*after write, iclass 4, count 0 2006.260.08:08:51.56#ibcon#*before return 0, iclass 4, count 0 2006.260.08:08:51.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:08:51.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:08:51.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:08:51.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:08:51.56$vc4f8/vb=1,4 2006.260.08:08:51.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.08:08:51.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.08:08:51.56#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:51.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:08:51.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:08:51.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:08:51.56#ibcon#enter wrdev, iclass 6, count 2 2006.260.08:08:51.56#ibcon#first serial, iclass 6, count 2 2006.260.08:08:51.56#ibcon#enter sib2, iclass 6, count 2 2006.260.08:08:51.56#ibcon#flushed, iclass 6, count 2 2006.260.08:08:51.56#ibcon#about to write, iclass 6, count 2 2006.260.08:08:51.56#ibcon#wrote, iclass 6, count 2 2006.260.08:08:51.56#ibcon#about to read 3, iclass 6, count 2 2006.260.08:08:51.58#ibcon#read 3, iclass 6, count 2 2006.260.08:08:51.58#ibcon#about to read 4, iclass 6, count 2 2006.260.08:08:51.58#ibcon#read 4, iclass 6, count 2 2006.260.08:08:51.58#ibcon#about to read 5, iclass 6, count 2 2006.260.08:08:51.58#ibcon#read 5, iclass 6, count 2 2006.260.08:08:51.58#ibcon#about to read 6, iclass 6, count 2 2006.260.08:08:51.58#ibcon#read 6, iclass 6, count 2 2006.260.08:08:51.58#ibcon#end of sib2, iclass 6, count 2 2006.260.08:08:51.58#ibcon#*mode == 0, iclass 6, count 2 2006.260.08:08:51.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.08:08:51.58#ibcon#[27=AT01-04\r\n] 2006.260.08:08:51.58#ibcon#*before write, iclass 6, count 2 2006.260.08:08:51.58#ibcon#enter sib2, iclass 6, count 2 2006.260.08:08:51.58#ibcon#flushed, iclass 6, count 2 2006.260.08:08:51.58#ibcon#about to write, iclass 6, count 2 2006.260.08:08:51.58#ibcon#wrote, iclass 6, count 2 2006.260.08:08:51.58#ibcon#about to read 3, iclass 6, count 2 2006.260.08:08:51.61#ibcon#read 3, iclass 6, count 2 2006.260.08:08:51.61#ibcon#about to read 4, iclass 6, count 2 2006.260.08:08:51.61#ibcon#read 4, iclass 6, count 2 2006.260.08:08:51.61#ibcon#about to read 5, iclass 6, count 2 2006.260.08:08:51.61#ibcon#read 5, iclass 6, count 2 2006.260.08:08:51.61#ibcon#about to read 6, iclass 6, count 2 2006.260.08:08:51.61#ibcon#read 6, iclass 6, count 2 2006.260.08:08:51.61#ibcon#end of sib2, iclass 6, count 2 2006.260.08:08:51.61#ibcon#*after write, iclass 6, count 2 2006.260.08:08:51.61#ibcon#*before return 0, iclass 6, count 2 2006.260.08:08:51.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:08:51.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:08:51.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.08:08:51.61#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:51.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:08:51.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:08:51.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:08:51.73#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:08:51.73#ibcon#first serial, iclass 6, count 0 2006.260.08:08:51.73#ibcon#enter sib2, iclass 6, count 0 2006.260.08:08:51.73#ibcon#flushed, iclass 6, count 0 2006.260.08:08:51.73#ibcon#about to write, iclass 6, count 0 2006.260.08:08:51.73#ibcon#wrote, iclass 6, count 0 2006.260.08:08:51.73#ibcon#about to read 3, iclass 6, count 0 2006.260.08:08:51.75#ibcon#read 3, iclass 6, count 0 2006.260.08:08:51.75#ibcon#about to read 4, iclass 6, count 0 2006.260.08:08:51.75#ibcon#read 4, iclass 6, count 0 2006.260.08:08:51.75#ibcon#about to read 5, iclass 6, count 0 2006.260.08:08:51.75#ibcon#read 5, iclass 6, count 0 2006.260.08:08:51.75#ibcon#about to read 6, iclass 6, count 0 2006.260.08:08:51.75#ibcon#read 6, iclass 6, count 0 2006.260.08:08:51.75#ibcon#end of sib2, iclass 6, count 0 2006.260.08:08:51.75#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:08:51.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:08:51.75#ibcon#[27=USB\r\n] 2006.260.08:08:51.75#ibcon#*before write, iclass 6, count 0 2006.260.08:08:51.75#ibcon#enter sib2, iclass 6, count 0 2006.260.08:08:51.75#ibcon#flushed, iclass 6, count 0 2006.260.08:08:51.75#ibcon#about to write, iclass 6, count 0 2006.260.08:08:51.75#ibcon#wrote, iclass 6, count 0 2006.260.08:08:51.75#ibcon#about to read 3, iclass 6, count 0 2006.260.08:08:51.78#ibcon#read 3, iclass 6, count 0 2006.260.08:08:51.78#ibcon#about to read 4, iclass 6, count 0 2006.260.08:08:51.78#ibcon#read 4, iclass 6, count 0 2006.260.08:08:51.78#ibcon#about to read 5, iclass 6, count 0 2006.260.08:08:51.78#ibcon#read 5, iclass 6, count 0 2006.260.08:08:51.78#ibcon#about to read 6, iclass 6, count 0 2006.260.08:08:51.78#ibcon#read 6, iclass 6, count 0 2006.260.08:08:51.78#ibcon#end of sib2, iclass 6, count 0 2006.260.08:08:51.78#ibcon#*after write, iclass 6, count 0 2006.260.08:08:51.78#ibcon#*before return 0, iclass 6, count 0 2006.260.08:08:51.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:08:51.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:08:51.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:08:51.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:08:51.78$vc4f8/vblo=2,640.99 2006.260.08:08:51.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.08:08:51.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.08:08:51.78#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:51.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:51.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:51.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:51.78#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:08:51.78#ibcon#first serial, iclass 10, count 0 2006.260.08:08:51.78#ibcon#enter sib2, iclass 10, count 0 2006.260.08:08:51.78#ibcon#flushed, iclass 10, count 0 2006.260.08:08:51.78#ibcon#about to write, iclass 10, count 0 2006.260.08:08:51.78#ibcon#wrote, iclass 10, count 0 2006.260.08:08:51.78#ibcon#about to read 3, iclass 10, count 0 2006.260.08:08:51.80#ibcon#read 3, iclass 10, count 0 2006.260.08:08:51.80#ibcon#about to read 4, iclass 10, count 0 2006.260.08:08:51.80#ibcon#read 4, iclass 10, count 0 2006.260.08:08:51.80#ibcon#about to read 5, iclass 10, count 0 2006.260.08:08:51.80#ibcon#read 5, iclass 10, count 0 2006.260.08:08:51.80#ibcon#about to read 6, iclass 10, count 0 2006.260.08:08:51.80#ibcon#read 6, iclass 10, count 0 2006.260.08:08:51.80#ibcon#end of sib2, iclass 10, count 0 2006.260.08:08:51.80#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:08:51.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:08:51.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:08:51.80#ibcon#*before write, iclass 10, count 0 2006.260.08:08:51.80#ibcon#enter sib2, iclass 10, count 0 2006.260.08:08:51.80#ibcon#flushed, iclass 10, count 0 2006.260.08:08:51.80#ibcon#about to write, iclass 10, count 0 2006.260.08:08:51.80#ibcon#wrote, iclass 10, count 0 2006.260.08:08:51.80#ibcon#about to read 3, iclass 10, count 0 2006.260.08:08:51.84#ibcon#read 3, iclass 10, count 0 2006.260.08:08:51.84#ibcon#about to read 4, iclass 10, count 0 2006.260.08:08:51.84#ibcon#read 4, iclass 10, count 0 2006.260.08:08:51.84#ibcon#about to read 5, iclass 10, count 0 2006.260.08:08:51.84#ibcon#read 5, iclass 10, count 0 2006.260.08:08:51.84#ibcon#about to read 6, iclass 10, count 0 2006.260.08:08:51.84#ibcon#read 6, iclass 10, count 0 2006.260.08:08:51.84#ibcon#end of sib2, iclass 10, count 0 2006.260.08:08:51.84#ibcon#*after write, iclass 10, count 0 2006.260.08:08:51.84#ibcon#*before return 0, iclass 10, count 0 2006.260.08:08:51.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:51.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:08:51.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:08:51.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:08:51.84$vc4f8/vb=2,5 2006.260.08:08:51.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.08:08:51.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.08:08:51.84#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:51.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:51.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:51.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:51.90#ibcon#enter wrdev, iclass 12, count 2 2006.260.08:08:51.90#ibcon#first serial, iclass 12, count 2 2006.260.08:08:51.90#ibcon#enter sib2, iclass 12, count 2 2006.260.08:08:51.90#ibcon#flushed, iclass 12, count 2 2006.260.08:08:51.90#ibcon#about to write, iclass 12, count 2 2006.260.08:08:51.90#ibcon#wrote, iclass 12, count 2 2006.260.08:08:51.90#ibcon#about to read 3, iclass 12, count 2 2006.260.08:08:51.92#ibcon#read 3, iclass 12, count 2 2006.260.08:08:51.92#ibcon#about to read 4, iclass 12, count 2 2006.260.08:08:51.92#ibcon#read 4, iclass 12, count 2 2006.260.08:08:51.92#ibcon#about to read 5, iclass 12, count 2 2006.260.08:08:51.92#ibcon#read 5, iclass 12, count 2 2006.260.08:08:51.92#ibcon#about to read 6, iclass 12, count 2 2006.260.08:08:51.92#ibcon#read 6, iclass 12, count 2 2006.260.08:08:51.92#ibcon#end of sib2, iclass 12, count 2 2006.260.08:08:51.92#ibcon#*mode == 0, iclass 12, count 2 2006.260.08:08:51.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.08:08:51.92#ibcon#[27=AT02-05\r\n] 2006.260.08:08:51.92#ibcon#*before write, iclass 12, count 2 2006.260.08:08:51.92#ibcon#enter sib2, iclass 12, count 2 2006.260.08:08:51.92#ibcon#flushed, iclass 12, count 2 2006.260.08:08:51.92#ibcon#about to write, iclass 12, count 2 2006.260.08:08:51.92#ibcon#wrote, iclass 12, count 2 2006.260.08:08:51.92#ibcon#about to read 3, iclass 12, count 2 2006.260.08:08:51.95#ibcon#read 3, iclass 12, count 2 2006.260.08:08:51.95#ibcon#about to read 4, iclass 12, count 2 2006.260.08:08:51.95#ibcon#read 4, iclass 12, count 2 2006.260.08:08:51.95#ibcon#about to read 5, iclass 12, count 2 2006.260.08:08:51.95#ibcon#read 5, iclass 12, count 2 2006.260.08:08:51.95#ibcon#about to read 6, iclass 12, count 2 2006.260.08:08:51.95#ibcon#read 6, iclass 12, count 2 2006.260.08:08:51.95#ibcon#end of sib2, iclass 12, count 2 2006.260.08:08:51.95#ibcon#*after write, iclass 12, count 2 2006.260.08:08:51.95#ibcon#*before return 0, iclass 12, count 2 2006.260.08:08:51.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:51.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:08:51.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.08:08:51.95#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:51.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:52.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:52.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:52.07#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:08:52.07#ibcon#first serial, iclass 12, count 0 2006.260.08:08:52.07#ibcon#enter sib2, iclass 12, count 0 2006.260.08:08:52.07#ibcon#flushed, iclass 12, count 0 2006.260.08:08:52.07#ibcon#about to write, iclass 12, count 0 2006.260.08:08:52.07#ibcon#wrote, iclass 12, count 0 2006.260.08:08:52.07#ibcon#about to read 3, iclass 12, count 0 2006.260.08:08:52.09#ibcon#read 3, iclass 12, count 0 2006.260.08:08:52.09#ibcon#about to read 4, iclass 12, count 0 2006.260.08:08:52.09#ibcon#read 4, iclass 12, count 0 2006.260.08:08:52.09#ibcon#about to read 5, iclass 12, count 0 2006.260.08:08:52.09#ibcon#read 5, iclass 12, count 0 2006.260.08:08:52.09#ibcon#about to read 6, iclass 12, count 0 2006.260.08:08:52.09#ibcon#read 6, iclass 12, count 0 2006.260.08:08:52.09#ibcon#end of sib2, iclass 12, count 0 2006.260.08:08:52.09#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:08:52.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:08:52.09#ibcon#[27=USB\r\n] 2006.260.08:08:52.09#ibcon#*before write, iclass 12, count 0 2006.260.08:08:52.09#ibcon#enter sib2, iclass 12, count 0 2006.260.08:08:52.09#ibcon#flushed, iclass 12, count 0 2006.260.08:08:52.09#ibcon#about to write, iclass 12, count 0 2006.260.08:08:52.09#ibcon#wrote, iclass 12, count 0 2006.260.08:08:52.09#ibcon#about to read 3, iclass 12, count 0 2006.260.08:08:52.12#ibcon#read 3, iclass 12, count 0 2006.260.08:08:52.12#ibcon#about to read 4, iclass 12, count 0 2006.260.08:08:52.12#ibcon#read 4, iclass 12, count 0 2006.260.08:08:52.12#ibcon#about to read 5, iclass 12, count 0 2006.260.08:08:52.12#ibcon#read 5, iclass 12, count 0 2006.260.08:08:52.12#ibcon#about to read 6, iclass 12, count 0 2006.260.08:08:52.12#ibcon#read 6, iclass 12, count 0 2006.260.08:08:52.12#ibcon#end of sib2, iclass 12, count 0 2006.260.08:08:52.12#ibcon#*after write, iclass 12, count 0 2006.260.08:08:52.12#ibcon#*before return 0, iclass 12, count 0 2006.260.08:08:52.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:52.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:08:52.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:08:52.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:08:52.12$vc4f8/vblo=3,656.99 2006.260.08:08:52.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:08:52.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:08:52.12#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:52.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:52.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:52.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:52.12#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:08:52.12#ibcon#first serial, iclass 14, count 0 2006.260.08:08:52.12#ibcon#enter sib2, iclass 14, count 0 2006.260.08:08:52.12#ibcon#flushed, iclass 14, count 0 2006.260.08:08:52.12#ibcon#about to write, iclass 14, count 0 2006.260.08:08:52.12#ibcon#wrote, iclass 14, count 0 2006.260.08:08:52.12#ibcon#about to read 3, iclass 14, count 0 2006.260.08:08:52.14#ibcon#read 3, iclass 14, count 0 2006.260.08:08:52.14#ibcon#about to read 4, iclass 14, count 0 2006.260.08:08:52.14#ibcon#read 4, iclass 14, count 0 2006.260.08:08:52.14#ibcon#about to read 5, iclass 14, count 0 2006.260.08:08:52.14#ibcon#read 5, iclass 14, count 0 2006.260.08:08:52.14#ibcon#about to read 6, iclass 14, count 0 2006.260.08:08:52.14#ibcon#read 6, iclass 14, count 0 2006.260.08:08:52.14#ibcon#end of sib2, iclass 14, count 0 2006.260.08:08:52.14#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:08:52.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:08:52.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:08:52.14#ibcon#*before write, iclass 14, count 0 2006.260.08:08:52.14#ibcon#enter sib2, iclass 14, count 0 2006.260.08:08:52.14#ibcon#flushed, iclass 14, count 0 2006.260.08:08:52.14#ibcon#about to write, iclass 14, count 0 2006.260.08:08:52.14#ibcon#wrote, iclass 14, count 0 2006.260.08:08:52.14#ibcon#about to read 3, iclass 14, count 0 2006.260.08:08:52.18#ibcon#read 3, iclass 14, count 0 2006.260.08:08:52.18#ibcon#about to read 4, iclass 14, count 0 2006.260.08:08:52.18#ibcon#read 4, iclass 14, count 0 2006.260.08:08:52.18#ibcon#about to read 5, iclass 14, count 0 2006.260.08:08:52.18#ibcon#read 5, iclass 14, count 0 2006.260.08:08:52.18#ibcon#about to read 6, iclass 14, count 0 2006.260.08:08:52.18#ibcon#read 6, iclass 14, count 0 2006.260.08:08:52.18#ibcon#end of sib2, iclass 14, count 0 2006.260.08:08:52.18#ibcon#*after write, iclass 14, count 0 2006.260.08:08:52.18#ibcon#*before return 0, iclass 14, count 0 2006.260.08:08:52.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:52.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:08:52.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:08:52.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:08:52.18$vc4f8/vb=3,4 2006.260.08:08:52.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.08:08:52.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.08:08:52.18#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:52.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:52.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:52.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:52.24#ibcon#enter wrdev, iclass 16, count 2 2006.260.08:08:52.24#ibcon#first serial, iclass 16, count 2 2006.260.08:08:52.24#ibcon#enter sib2, iclass 16, count 2 2006.260.08:08:52.24#ibcon#flushed, iclass 16, count 2 2006.260.08:08:52.24#ibcon#about to write, iclass 16, count 2 2006.260.08:08:52.24#ibcon#wrote, iclass 16, count 2 2006.260.08:08:52.24#ibcon#about to read 3, iclass 16, count 2 2006.260.08:08:52.26#ibcon#read 3, iclass 16, count 2 2006.260.08:08:52.26#ibcon#about to read 4, iclass 16, count 2 2006.260.08:08:52.26#ibcon#read 4, iclass 16, count 2 2006.260.08:08:52.26#ibcon#about to read 5, iclass 16, count 2 2006.260.08:08:52.26#ibcon#read 5, iclass 16, count 2 2006.260.08:08:52.26#ibcon#about to read 6, iclass 16, count 2 2006.260.08:08:52.26#ibcon#read 6, iclass 16, count 2 2006.260.08:08:52.26#ibcon#end of sib2, iclass 16, count 2 2006.260.08:08:52.26#ibcon#*mode == 0, iclass 16, count 2 2006.260.08:08:52.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.08:08:52.26#ibcon#[27=AT03-04\r\n] 2006.260.08:08:52.26#ibcon#*before write, iclass 16, count 2 2006.260.08:08:52.26#ibcon#enter sib2, iclass 16, count 2 2006.260.08:08:52.26#ibcon#flushed, iclass 16, count 2 2006.260.08:08:52.26#ibcon#about to write, iclass 16, count 2 2006.260.08:08:52.26#ibcon#wrote, iclass 16, count 2 2006.260.08:08:52.26#ibcon#about to read 3, iclass 16, count 2 2006.260.08:08:52.29#ibcon#read 3, iclass 16, count 2 2006.260.08:08:52.29#ibcon#about to read 4, iclass 16, count 2 2006.260.08:08:52.29#ibcon#read 4, iclass 16, count 2 2006.260.08:08:52.29#ibcon#about to read 5, iclass 16, count 2 2006.260.08:08:52.29#ibcon#read 5, iclass 16, count 2 2006.260.08:08:52.29#ibcon#about to read 6, iclass 16, count 2 2006.260.08:08:52.29#ibcon#read 6, iclass 16, count 2 2006.260.08:08:52.29#ibcon#end of sib2, iclass 16, count 2 2006.260.08:08:52.29#ibcon#*after write, iclass 16, count 2 2006.260.08:08:52.29#ibcon#*before return 0, iclass 16, count 2 2006.260.08:08:52.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:52.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:08:52.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.08:08:52.29#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:52.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:52.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:52.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:52.41#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:08:52.41#ibcon#first serial, iclass 16, count 0 2006.260.08:08:52.41#ibcon#enter sib2, iclass 16, count 0 2006.260.08:08:52.41#ibcon#flushed, iclass 16, count 0 2006.260.08:08:52.41#ibcon#about to write, iclass 16, count 0 2006.260.08:08:52.41#ibcon#wrote, iclass 16, count 0 2006.260.08:08:52.41#ibcon#about to read 3, iclass 16, count 0 2006.260.08:08:52.43#ibcon#read 3, iclass 16, count 0 2006.260.08:08:52.43#ibcon#about to read 4, iclass 16, count 0 2006.260.08:08:52.43#ibcon#read 4, iclass 16, count 0 2006.260.08:08:52.43#ibcon#about to read 5, iclass 16, count 0 2006.260.08:08:52.43#ibcon#read 5, iclass 16, count 0 2006.260.08:08:52.43#ibcon#about to read 6, iclass 16, count 0 2006.260.08:08:52.43#ibcon#read 6, iclass 16, count 0 2006.260.08:08:52.43#ibcon#end of sib2, iclass 16, count 0 2006.260.08:08:52.43#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:08:52.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:08:52.43#ibcon#[27=USB\r\n] 2006.260.08:08:52.43#ibcon#*before write, iclass 16, count 0 2006.260.08:08:52.43#ibcon#enter sib2, iclass 16, count 0 2006.260.08:08:52.43#ibcon#flushed, iclass 16, count 0 2006.260.08:08:52.43#ibcon#about to write, iclass 16, count 0 2006.260.08:08:52.43#ibcon#wrote, iclass 16, count 0 2006.260.08:08:52.43#ibcon#about to read 3, iclass 16, count 0 2006.260.08:08:52.46#ibcon#read 3, iclass 16, count 0 2006.260.08:08:52.46#ibcon#about to read 4, iclass 16, count 0 2006.260.08:08:52.46#ibcon#read 4, iclass 16, count 0 2006.260.08:08:52.46#ibcon#about to read 5, iclass 16, count 0 2006.260.08:08:52.46#ibcon#read 5, iclass 16, count 0 2006.260.08:08:52.46#ibcon#about to read 6, iclass 16, count 0 2006.260.08:08:52.46#ibcon#read 6, iclass 16, count 0 2006.260.08:08:52.46#ibcon#end of sib2, iclass 16, count 0 2006.260.08:08:52.46#ibcon#*after write, iclass 16, count 0 2006.260.08:08:52.46#ibcon#*before return 0, iclass 16, count 0 2006.260.08:08:52.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:52.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:08:52.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:08:52.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:08:52.46$vc4f8/vblo=4,712.99 2006.260.08:08:52.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.08:08:52.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.08:08:52.46#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:52.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:52.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:52.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:52.46#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:08:52.46#ibcon#first serial, iclass 18, count 0 2006.260.08:08:52.46#ibcon#enter sib2, iclass 18, count 0 2006.260.08:08:52.46#ibcon#flushed, iclass 18, count 0 2006.260.08:08:52.46#ibcon#about to write, iclass 18, count 0 2006.260.08:08:52.46#ibcon#wrote, iclass 18, count 0 2006.260.08:08:52.46#ibcon#about to read 3, iclass 18, count 0 2006.260.08:08:52.48#ibcon#read 3, iclass 18, count 0 2006.260.08:08:52.48#ibcon#about to read 4, iclass 18, count 0 2006.260.08:08:52.48#ibcon#read 4, iclass 18, count 0 2006.260.08:08:52.48#ibcon#about to read 5, iclass 18, count 0 2006.260.08:08:52.48#ibcon#read 5, iclass 18, count 0 2006.260.08:08:52.48#ibcon#about to read 6, iclass 18, count 0 2006.260.08:08:52.48#ibcon#read 6, iclass 18, count 0 2006.260.08:08:52.48#ibcon#end of sib2, iclass 18, count 0 2006.260.08:08:52.48#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:08:52.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:08:52.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:08:52.48#ibcon#*before write, iclass 18, count 0 2006.260.08:08:52.48#ibcon#enter sib2, iclass 18, count 0 2006.260.08:08:52.48#ibcon#flushed, iclass 18, count 0 2006.260.08:08:52.48#ibcon#about to write, iclass 18, count 0 2006.260.08:08:52.48#ibcon#wrote, iclass 18, count 0 2006.260.08:08:52.48#ibcon#about to read 3, iclass 18, count 0 2006.260.08:08:52.52#ibcon#read 3, iclass 18, count 0 2006.260.08:08:52.52#ibcon#about to read 4, iclass 18, count 0 2006.260.08:08:52.52#ibcon#read 4, iclass 18, count 0 2006.260.08:08:52.52#ibcon#about to read 5, iclass 18, count 0 2006.260.08:08:52.52#ibcon#read 5, iclass 18, count 0 2006.260.08:08:52.52#ibcon#about to read 6, iclass 18, count 0 2006.260.08:08:52.52#ibcon#read 6, iclass 18, count 0 2006.260.08:08:52.52#ibcon#end of sib2, iclass 18, count 0 2006.260.08:08:52.52#ibcon#*after write, iclass 18, count 0 2006.260.08:08:52.52#ibcon#*before return 0, iclass 18, count 0 2006.260.08:08:52.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:52.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:08:52.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:08:52.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:08:52.52$vc4f8/vb=4,5 2006.260.08:08:52.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.08:08:52.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.08:08:52.52#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:52.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:52.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:52.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:52.58#ibcon#enter wrdev, iclass 20, count 2 2006.260.08:08:52.58#ibcon#first serial, iclass 20, count 2 2006.260.08:08:52.58#ibcon#enter sib2, iclass 20, count 2 2006.260.08:08:52.58#ibcon#flushed, iclass 20, count 2 2006.260.08:08:52.58#ibcon#about to write, iclass 20, count 2 2006.260.08:08:52.58#ibcon#wrote, iclass 20, count 2 2006.260.08:08:52.58#ibcon#about to read 3, iclass 20, count 2 2006.260.08:08:52.60#ibcon#read 3, iclass 20, count 2 2006.260.08:08:52.60#ibcon#about to read 4, iclass 20, count 2 2006.260.08:08:52.60#ibcon#read 4, iclass 20, count 2 2006.260.08:08:52.60#ibcon#about to read 5, iclass 20, count 2 2006.260.08:08:52.60#ibcon#read 5, iclass 20, count 2 2006.260.08:08:52.60#ibcon#about to read 6, iclass 20, count 2 2006.260.08:08:52.60#ibcon#read 6, iclass 20, count 2 2006.260.08:08:52.60#ibcon#end of sib2, iclass 20, count 2 2006.260.08:08:52.60#ibcon#*mode == 0, iclass 20, count 2 2006.260.08:08:52.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.08:08:52.60#ibcon#[27=AT04-05\r\n] 2006.260.08:08:52.60#ibcon#*before write, iclass 20, count 2 2006.260.08:08:52.60#ibcon#enter sib2, iclass 20, count 2 2006.260.08:08:52.60#ibcon#flushed, iclass 20, count 2 2006.260.08:08:52.60#ibcon#about to write, iclass 20, count 2 2006.260.08:08:52.60#ibcon#wrote, iclass 20, count 2 2006.260.08:08:52.60#ibcon#about to read 3, iclass 20, count 2 2006.260.08:08:52.63#ibcon#read 3, iclass 20, count 2 2006.260.08:08:52.63#ibcon#about to read 4, iclass 20, count 2 2006.260.08:08:52.63#ibcon#read 4, iclass 20, count 2 2006.260.08:08:52.63#ibcon#about to read 5, iclass 20, count 2 2006.260.08:08:52.63#ibcon#read 5, iclass 20, count 2 2006.260.08:08:52.63#ibcon#about to read 6, iclass 20, count 2 2006.260.08:08:52.63#ibcon#read 6, iclass 20, count 2 2006.260.08:08:52.63#ibcon#end of sib2, iclass 20, count 2 2006.260.08:08:52.63#ibcon#*after write, iclass 20, count 2 2006.260.08:08:52.63#ibcon#*before return 0, iclass 20, count 2 2006.260.08:08:52.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:52.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:08:52.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.08:08:52.63#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:52.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:52.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:52.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:52.75#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:08:52.75#ibcon#first serial, iclass 20, count 0 2006.260.08:08:52.75#ibcon#enter sib2, iclass 20, count 0 2006.260.08:08:52.75#ibcon#flushed, iclass 20, count 0 2006.260.08:08:52.75#ibcon#about to write, iclass 20, count 0 2006.260.08:08:52.75#ibcon#wrote, iclass 20, count 0 2006.260.08:08:52.75#ibcon#about to read 3, iclass 20, count 0 2006.260.08:08:52.77#ibcon#read 3, iclass 20, count 0 2006.260.08:08:52.77#ibcon#about to read 4, iclass 20, count 0 2006.260.08:08:52.77#ibcon#read 4, iclass 20, count 0 2006.260.08:08:52.77#ibcon#about to read 5, iclass 20, count 0 2006.260.08:08:52.77#ibcon#read 5, iclass 20, count 0 2006.260.08:08:52.77#ibcon#about to read 6, iclass 20, count 0 2006.260.08:08:52.77#ibcon#read 6, iclass 20, count 0 2006.260.08:08:52.77#ibcon#end of sib2, iclass 20, count 0 2006.260.08:08:52.77#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:08:52.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:08:52.77#ibcon#[27=USB\r\n] 2006.260.08:08:52.77#ibcon#*before write, iclass 20, count 0 2006.260.08:08:52.77#ibcon#enter sib2, iclass 20, count 0 2006.260.08:08:52.77#ibcon#flushed, iclass 20, count 0 2006.260.08:08:52.77#ibcon#about to write, iclass 20, count 0 2006.260.08:08:52.77#ibcon#wrote, iclass 20, count 0 2006.260.08:08:52.77#ibcon#about to read 3, iclass 20, count 0 2006.260.08:08:52.80#ibcon#read 3, iclass 20, count 0 2006.260.08:08:52.80#ibcon#about to read 4, iclass 20, count 0 2006.260.08:08:52.80#ibcon#read 4, iclass 20, count 0 2006.260.08:08:52.80#ibcon#about to read 5, iclass 20, count 0 2006.260.08:08:52.80#ibcon#read 5, iclass 20, count 0 2006.260.08:08:52.80#ibcon#about to read 6, iclass 20, count 0 2006.260.08:08:52.80#ibcon#read 6, iclass 20, count 0 2006.260.08:08:52.80#ibcon#end of sib2, iclass 20, count 0 2006.260.08:08:52.80#ibcon#*after write, iclass 20, count 0 2006.260.08:08:52.80#ibcon#*before return 0, iclass 20, count 0 2006.260.08:08:52.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:52.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:08:52.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:08:52.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:08:52.80$vc4f8/vblo=5,744.99 2006.260.08:08:52.80#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.08:08:52.80#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.08:08:52.80#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:52.80#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:52.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:52.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:52.80#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:08:52.80#ibcon#first serial, iclass 22, count 0 2006.260.08:08:52.80#ibcon#enter sib2, iclass 22, count 0 2006.260.08:08:52.80#ibcon#flushed, iclass 22, count 0 2006.260.08:08:52.80#ibcon#about to write, iclass 22, count 0 2006.260.08:08:52.80#ibcon#wrote, iclass 22, count 0 2006.260.08:08:52.80#ibcon#about to read 3, iclass 22, count 0 2006.260.08:08:52.82#ibcon#read 3, iclass 22, count 0 2006.260.08:08:52.82#ibcon#about to read 4, iclass 22, count 0 2006.260.08:08:52.82#ibcon#read 4, iclass 22, count 0 2006.260.08:08:52.82#ibcon#about to read 5, iclass 22, count 0 2006.260.08:08:52.82#ibcon#read 5, iclass 22, count 0 2006.260.08:08:52.82#ibcon#about to read 6, iclass 22, count 0 2006.260.08:08:52.82#ibcon#read 6, iclass 22, count 0 2006.260.08:08:52.82#ibcon#end of sib2, iclass 22, count 0 2006.260.08:08:52.82#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:08:52.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:08:52.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:08:52.82#ibcon#*before write, iclass 22, count 0 2006.260.08:08:52.82#ibcon#enter sib2, iclass 22, count 0 2006.260.08:08:52.82#ibcon#flushed, iclass 22, count 0 2006.260.08:08:52.82#ibcon#about to write, iclass 22, count 0 2006.260.08:08:52.82#ibcon#wrote, iclass 22, count 0 2006.260.08:08:52.82#ibcon#about to read 3, iclass 22, count 0 2006.260.08:08:52.86#ibcon#read 3, iclass 22, count 0 2006.260.08:08:52.86#ibcon#about to read 4, iclass 22, count 0 2006.260.08:08:52.86#ibcon#read 4, iclass 22, count 0 2006.260.08:08:52.86#ibcon#about to read 5, iclass 22, count 0 2006.260.08:08:52.86#ibcon#read 5, iclass 22, count 0 2006.260.08:08:52.86#ibcon#about to read 6, iclass 22, count 0 2006.260.08:08:52.86#ibcon#read 6, iclass 22, count 0 2006.260.08:08:52.86#ibcon#end of sib2, iclass 22, count 0 2006.260.08:08:52.86#ibcon#*after write, iclass 22, count 0 2006.260.08:08:52.86#ibcon#*before return 0, iclass 22, count 0 2006.260.08:08:52.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:52.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:08:52.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:08:52.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:08:52.86$vc4f8/vb=5,4 2006.260.08:08:52.86#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.08:08:52.86#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.08:08:52.86#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:52.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:52.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:52.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:52.92#ibcon#enter wrdev, iclass 24, count 2 2006.260.08:08:52.92#ibcon#first serial, iclass 24, count 2 2006.260.08:08:52.92#ibcon#enter sib2, iclass 24, count 2 2006.260.08:08:52.92#ibcon#flushed, iclass 24, count 2 2006.260.08:08:52.92#ibcon#about to write, iclass 24, count 2 2006.260.08:08:52.92#ibcon#wrote, iclass 24, count 2 2006.260.08:08:52.92#ibcon#about to read 3, iclass 24, count 2 2006.260.08:08:52.94#ibcon#read 3, iclass 24, count 2 2006.260.08:08:52.94#ibcon#about to read 4, iclass 24, count 2 2006.260.08:08:52.94#ibcon#read 4, iclass 24, count 2 2006.260.08:08:52.94#ibcon#about to read 5, iclass 24, count 2 2006.260.08:08:52.94#ibcon#read 5, iclass 24, count 2 2006.260.08:08:52.94#ibcon#about to read 6, iclass 24, count 2 2006.260.08:08:52.94#ibcon#read 6, iclass 24, count 2 2006.260.08:08:52.94#ibcon#end of sib2, iclass 24, count 2 2006.260.08:08:52.94#ibcon#*mode == 0, iclass 24, count 2 2006.260.08:08:52.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.08:08:52.94#ibcon#[27=AT05-04\r\n] 2006.260.08:08:52.94#ibcon#*before write, iclass 24, count 2 2006.260.08:08:52.94#ibcon#enter sib2, iclass 24, count 2 2006.260.08:08:52.94#ibcon#flushed, iclass 24, count 2 2006.260.08:08:52.94#ibcon#about to write, iclass 24, count 2 2006.260.08:08:52.94#ibcon#wrote, iclass 24, count 2 2006.260.08:08:52.94#ibcon#about to read 3, iclass 24, count 2 2006.260.08:08:52.97#ibcon#read 3, iclass 24, count 2 2006.260.08:08:52.97#ibcon#about to read 4, iclass 24, count 2 2006.260.08:08:52.97#ibcon#read 4, iclass 24, count 2 2006.260.08:08:52.97#ibcon#about to read 5, iclass 24, count 2 2006.260.08:08:52.97#ibcon#read 5, iclass 24, count 2 2006.260.08:08:52.97#ibcon#about to read 6, iclass 24, count 2 2006.260.08:08:52.97#ibcon#read 6, iclass 24, count 2 2006.260.08:08:52.97#ibcon#end of sib2, iclass 24, count 2 2006.260.08:08:52.97#ibcon#*after write, iclass 24, count 2 2006.260.08:08:52.97#ibcon#*before return 0, iclass 24, count 2 2006.260.08:08:52.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:52.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:08:52.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.08:08:52.97#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:52.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:53.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:53.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:53.09#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:08:53.09#ibcon#first serial, iclass 24, count 0 2006.260.08:08:53.09#ibcon#enter sib2, iclass 24, count 0 2006.260.08:08:53.09#ibcon#flushed, iclass 24, count 0 2006.260.08:08:53.09#ibcon#about to write, iclass 24, count 0 2006.260.08:08:53.09#ibcon#wrote, iclass 24, count 0 2006.260.08:08:53.09#ibcon#about to read 3, iclass 24, count 0 2006.260.08:08:53.11#ibcon#read 3, iclass 24, count 0 2006.260.08:08:53.11#ibcon#about to read 4, iclass 24, count 0 2006.260.08:08:53.11#ibcon#read 4, iclass 24, count 0 2006.260.08:08:53.11#ibcon#about to read 5, iclass 24, count 0 2006.260.08:08:53.11#ibcon#read 5, iclass 24, count 0 2006.260.08:08:53.11#ibcon#about to read 6, iclass 24, count 0 2006.260.08:08:53.11#ibcon#read 6, iclass 24, count 0 2006.260.08:08:53.11#ibcon#end of sib2, iclass 24, count 0 2006.260.08:08:53.11#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:08:53.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:08:53.11#ibcon#[27=USB\r\n] 2006.260.08:08:53.11#ibcon#*before write, iclass 24, count 0 2006.260.08:08:53.11#ibcon#enter sib2, iclass 24, count 0 2006.260.08:08:53.11#ibcon#flushed, iclass 24, count 0 2006.260.08:08:53.11#ibcon#about to write, iclass 24, count 0 2006.260.08:08:53.11#ibcon#wrote, iclass 24, count 0 2006.260.08:08:53.11#ibcon#about to read 3, iclass 24, count 0 2006.260.08:08:53.14#ibcon#read 3, iclass 24, count 0 2006.260.08:08:53.14#ibcon#about to read 4, iclass 24, count 0 2006.260.08:08:53.14#ibcon#read 4, iclass 24, count 0 2006.260.08:08:53.14#ibcon#about to read 5, iclass 24, count 0 2006.260.08:08:53.14#ibcon#read 5, iclass 24, count 0 2006.260.08:08:53.14#ibcon#about to read 6, iclass 24, count 0 2006.260.08:08:53.14#ibcon#read 6, iclass 24, count 0 2006.260.08:08:53.14#ibcon#end of sib2, iclass 24, count 0 2006.260.08:08:53.14#ibcon#*after write, iclass 24, count 0 2006.260.08:08:53.14#ibcon#*before return 0, iclass 24, count 0 2006.260.08:08:53.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:53.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:08:53.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:08:53.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:08:53.14$vc4f8/vblo=6,752.99 2006.260.08:08:53.14#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.08:08:53.14#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.08:08:53.14#ibcon#ireg 17 cls_cnt 0 2006.260.08:08:53.14#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:53.14#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:53.14#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:53.14#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:08:53.14#ibcon#first serial, iclass 26, count 0 2006.260.08:08:53.14#ibcon#enter sib2, iclass 26, count 0 2006.260.08:08:53.14#ibcon#flushed, iclass 26, count 0 2006.260.08:08:53.14#ibcon#about to write, iclass 26, count 0 2006.260.08:08:53.14#ibcon#wrote, iclass 26, count 0 2006.260.08:08:53.14#ibcon#about to read 3, iclass 26, count 0 2006.260.08:08:53.16#ibcon#read 3, iclass 26, count 0 2006.260.08:08:53.16#ibcon#about to read 4, iclass 26, count 0 2006.260.08:08:53.16#ibcon#read 4, iclass 26, count 0 2006.260.08:08:53.16#ibcon#about to read 5, iclass 26, count 0 2006.260.08:08:53.16#ibcon#read 5, iclass 26, count 0 2006.260.08:08:53.16#ibcon#about to read 6, iclass 26, count 0 2006.260.08:08:53.16#ibcon#read 6, iclass 26, count 0 2006.260.08:08:53.16#ibcon#end of sib2, iclass 26, count 0 2006.260.08:08:53.16#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:08:53.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:08:53.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:08:53.16#ibcon#*before write, iclass 26, count 0 2006.260.08:08:53.16#ibcon#enter sib2, iclass 26, count 0 2006.260.08:08:53.16#ibcon#flushed, iclass 26, count 0 2006.260.08:08:53.16#ibcon#about to write, iclass 26, count 0 2006.260.08:08:53.16#ibcon#wrote, iclass 26, count 0 2006.260.08:08:53.16#ibcon#about to read 3, iclass 26, count 0 2006.260.08:08:53.20#ibcon#read 3, iclass 26, count 0 2006.260.08:08:53.20#ibcon#about to read 4, iclass 26, count 0 2006.260.08:08:53.20#ibcon#read 4, iclass 26, count 0 2006.260.08:08:53.20#ibcon#about to read 5, iclass 26, count 0 2006.260.08:08:53.20#ibcon#read 5, iclass 26, count 0 2006.260.08:08:53.20#ibcon#about to read 6, iclass 26, count 0 2006.260.08:08:53.20#ibcon#read 6, iclass 26, count 0 2006.260.08:08:53.20#ibcon#end of sib2, iclass 26, count 0 2006.260.08:08:53.20#ibcon#*after write, iclass 26, count 0 2006.260.08:08:53.20#ibcon#*before return 0, iclass 26, count 0 2006.260.08:08:53.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:53.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:08:53.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:08:53.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:08:53.20$vc4f8/vb=6,4 2006.260.08:08:53.20#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.08:08:53.20#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.08:08:53.20#ibcon#ireg 11 cls_cnt 2 2006.260.08:08:53.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:53.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:53.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:53.26#ibcon#enter wrdev, iclass 28, count 2 2006.260.08:08:53.26#ibcon#first serial, iclass 28, count 2 2006.260.08:08:53.26#ibcon#enter sib2, iclass 28, count 2 2006.260.08:08:53.26#ibcon#flushed, iclass 28, count 2 2006.260.08:08:53.26#ibcon#about to write, iclass 28, count 2 2006.260.08:08:53.26#ibcon#wrote, iclass 28, count 2 2006.260.08:08:53.26#ibcon#about to read 3, iclass 28, count 2 2006.260.08:08:53.28#ibcon#read 3, iclass 28, count 2 2006.260.08:08:53.28#ibcon#about to read 4, iclass 28, count 2 2006.260.08:08:53.28#ibcon#read 4, iclass 28, count 2 2006.260.08:08:53.28#ibcon#about to read 5, iclass 28, count 2 2006.260.08:08:53.28#ibcon#read 5, iclass 28, count 2 2006.260.08:08:53.28#ibcon#about to read 6, iclass 28, count 2 2006.260.08:08:53.28#ibcon#read 6, iclass 28, count 2 2006.260.08:08:53.28#ibcon#end of sib2, iclass 28, count 2 2006.260.08:08:53.28#ibcon#*mode == 0, iclass 28, count 2 2006.260.08:08:53.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.08:08:53.28#ibcon#[27=AT06-04\r\n] 2006.260.08:08:53.28#ibcon#*before write, iclass 28, count 2 2006.260.08:08:53.28#ibcon#enter sib2, iclass 28, count 2 2006.260.08:08:53.28#ibcon#flushed, iclass 28, count 2 2006.260.08:08:53.28#ibcon#about to write, iclass 28, count 2 2006.260.08:08:53.28#ibcon#wrote, iclass 28, count 2 2006.260.08:08:53.28#ibcon#about to read 3, iclass 28, count 2 2006.260.08:08:53.31#ibcon#read 3, iclass 28, count 2 2006.260.08:08:53.31#ibcon#about to read 4, iclass 28, count 2 2006.260.08:08:53.31#ibcon#read 4, iclass 28, count 2 2006.260.08:08:53.31#ibcon#about to read 5, iclass 28, count 2 2006.260.08:08:53.31#ibcon#read 5, iclass 28, count 2 2006.260.08:08:53.31#ibcon#about to read 6, iclass 28, count 2 2006.260.08:08:53.31#ibcon#read 6, iclass 28, count 2 2006.260.08:08:53.31#ibcon#end of sib2, iclass 28, count 2 2006.260.08:08:53.31#ibcon#*after write, iclass 28, count 2 2006.260.08:08:53.31#ibcon#*before return 0, iclass 28, count 2 2006.260.08:08:53.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:53.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:08:53.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.08:08:53.31#ibcon#ireg 7 cls_cnt 0 2006.260.08:08:53.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:53.33#abcon#<5=/04 3.2 7.0 22.80 891010.4\r\n> 2006.260.08:08:53.35#abcon#{5=INTERFACE CLEAR} 2006.260.08:08:53.41#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:08:53.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:53.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:53.43#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:08:53.43#ibcon#first serial, iclass 28, count 0 2006.260.08:08:53.43#ibcon#enter sib2, iclass 28, count 0 2006.260.08:08:53.43#ibcon#flushed, iclass 28, count 0 2006.260.08:08:53.43#ibcon#about to write, iclass 28, count 0 2006.260.08:08:53.43#ibcon#wrote, iclass 28, count 0 2006.260.08:08:53.43#ibcon#about to read 3, iclass 28, count 0 2006.260.08:08:53.45#ibcon#read 3, iclass 28, count 0 2006.260.08:08:53.45#ibcon#about to read 4, iclass 28, count 0 2006.260.08:08:53.45#ibcon#read 4, iclass 28, count 0 2006.260.08:08:53.45#ibcon#about to read 5, iclass 28, count 0 2006.260.08:08:53.45#ibcon#read 5, iclass 28, count 0 2006.260.08:08:53.45#ibcon#about to read 6, iclass 28, count 0 2006.260.08:08:53.45#ibcon#read 6, iclass 28, count 0 2006.260.08:08:53.45#ibcon#end of sib2, iclass 28, count 0 2006.260.08:08:53.45#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:08:53.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:08:53.45#ibcon#[27=USB\r\n] 2006.260.08:08:53.45#ibcon#*before write, iclass 28, count 0 2006.260.08:08:53.45#ibcon#enter sib2, iclass 28, count 0 2006.260.08:08:53.45#ibcon#flushed, iclass 28, count 0 2006.260.08:08:53.45#ibcon#about to write, iclass 28, count 0 2006.260.08:08:53.45#ibcon#wrote, iclass 28, count 0 2006.260.08:08:53.45#ibcon#about to read 3, iclass 28, count 0 2006.260.08:08:53.48#ibcon#read 3, iclass 28, count 0 2006.260.08:08:53.48#ibcon#about to read 4, iclass 28, count 0 2006.260.08:08:53.48#ibcon#read 4, iclass 28, count 0 2006.260.08:08:53.48#ibcon#about to read 5, iclass 28, count 0 2006.260.08:08:53.48#ibcon#read 5, iclass 28, count 0 2006.260.08:08:53.48#ibcon#about to read 6, iclass 28, count 0 2006.260.08:08:53.48#ibcon#read 6, iclass 28, count 0 2006.260.08:08:53.48#ibcon#end of sib2, iclass 28, count 0 2006.260.08:08:53.48#ibcon#*after write, iclass 28, count 0 2006.260.08:08:53.48#ibcon#*before return 0, iclass 28, count 0 2006.260.08:08:53.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:53.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:08:53.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:08:53.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:08:53.48$vc4f8/vabw=wide 2006.260.08:08:53.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.08:08:53.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.08:08:53.48#ibcon#ireg 8 cls_cnt 0 2006.260.08:08:53.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:53.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:53.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:53.48#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:08:53.48#ibcon#first serial, iclass 34, count 0 2006.260.08:08:53.48#ibcon#enter sib2, iclass 34, count 0 2006.260.08:08:53.48#ibcon#flushed, iclass 34, count 0 2006.260.08:08:53.48#ibcon#about to write, iclass 34, count 0 2006.260.08:08:53.48#ibcon#wrote, iclass 34, count 0 2006.260.08:08:53.48#ibcon#about to read 3, iclass 34, count 0 2006.260.08:08:53.50#ibcon#read 3, iclass 34, count 0 2006.260.08:08:53.50#ibcon#about to read 4, iclass 34, count 0 2006.260.08:08:53.50#ibcon#read 4, iclass 34, count 0 2006.260.08:08:53.50#ibcon#about to read 5, iclass 34, count 0 2006.260.08:08:53.50#ibcon#read 5, iclass 34, count 0 2006.260.08:08:53.50#ibcon#about to read 6, iclass 34, count 0 2006.260.08:08:53.50#ibcon#read 6, iclass 34, count 0 2006.260.08:08:53.50#ibcon#end of sib2, iclass 34, count 0 2006.260.08:08:53.50#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:08:53.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:08:53.50#ibcon#[25=BW32\r\n] 2006.260.08:08:53.50#ibcon#*before write, iclass 34, count 0 2006.260.08:08:53.50#ibcon#enter sib2, iclass 34, count 0 2006.260.08:08:53.50#ibcon#flushed, iclass 34, count 0 2006.260.08:08:53.50#ibcon#about to write, iclass 34, count 0 2006.260.08:08:53.50#ibcon#wrote, iclass 34, count 0 2006.260.08:08:53.50#ibcon#about to read 3, iclass 34, count 0 2006.260.08:08:53.53#ibcon#read 3, iclass 34, count 0 2006.260.08:08:53.53#ibcon#about to read 4, iclass 34, count 0 2006.260.08:08:53.53#ibcon#read 4, iclass 34, count 0 2006.260.08:08:53.53#ibcon#about to read 5, iclass 34, count 0 2006.260.08:08:53.53#ibcon#read 5, iclass 34, count 0 2006.260.08:08:53.53#ibcon#about to read 6, iclass 34, count 0 2006.260.08:08:53.53#ibcon#read 6, iclass 34, count 0 2006.260.08:08:53.53#ibcon#end of sib2, iclass 34, count 0 2006.260.08:08:53.53#ibcon#*after write, iclass 34, count 0 2006.260.08:08:53.53#ibcon#*before return 0, iclass 34, count 0 2006.260.08:08:53.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:53.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:08:53.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:08:53.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:08:53.53$vc4f8/vbbw=wide 2006.260.08:08:53.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:08:53.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:08:53.53#ibcon#ireg 8 cls_cnt 0 2006.260.08:08:53.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:08:53.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:08:53.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:08:53.60#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:08:53.60#ibcon#first serial, iclass 36, count 0 2006.260.08:08:53.60#ibcon#enter sib2, iclass 36, count 0 2006.260.08:08:53.60#ibcon#flushed, iclass 36, count 0 2006.260.08:08:53.60#ibcon#about to write, iclass 36, count 0 2006.260.08:08:53.60#ibcon#wrote, iclass 36, count 0 2006.260.08:08:53.60#ibcon#about to read 3, iclass 36, count 0 2006.260.08:08:53.62#ibcon#read 3, iclass 36, count 0 2006.260.08:08:53.62#ibcon#about to read 4, iclass 36, count 0 2006.260.08:08:53.62#ibcon#read 4, iclass 36, count 0 2006.260.08:08:53.62#ibcon#about to read 5, iclass 36, count 0 2006.260.08:08:53.62#ibcon#read 5, iclass 36, count 0 2006.260.08:08:53.62#ibcon#about to read 6, iclass 36, count 0 2006.260.08:08:53.62#ibcon#read 6, iclass 36, count 0 2006.260.08:08:53.62#ibcon#end of sib2, iclass 36, count 0 2006.260.08:08:53.62#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:08:53.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:08:53.62#ibcon#[27=BW32\r\n] 2006.260.08:08:53.62#ibcon#*before write, iclass 36, count 0 2006.260.08:08:53.62#ibcon#enter sib2, iclass 36, count 0 2006.260.08:08:53.62#ibcon#flushed, iclass 36, count 0 2006.260.08:08:53.62#ibcon#about to write, iclass 36, count 0 2006.260.08:08:53.62#ibcon#wrote, iclass 36, count 0 2006.260.08:08:53.62#ibcon#about to read 3, iclass 36, count 0 2006.260.08:08:53.65#ibcon#read 3, iclass 36, count 0 2006.260.08:08:53.65#ibcon#about to read 4, iclass 36, count 0 2006.260.08:08:53.65#ibcon#read 4, iclass 36, count 0 2006.260.08:08:53.65#ibcon#about to read 5, iclass 36, count 0 2006.260.08:08:53.65#ibcon#read 5, iclass 36, count 0 2006.260.08:08:53.65#ibcon#about to read 6, iclass 36, count 0 2006.260.08:08:53.65#ibcon#read 6, iclass 36, count 0 2006.260.08:08:53.65#ibcon#end of sib2, iclass 36, count 0 2006.260.08:08:53.65#ibcon#*after write, iclass 36, count 0 2006.260.08:08:53.65#ibcon#*before return 0, iclass 36, count 0 2006.260.08:08:53.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:08:53.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:08:53.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:08:53.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:08:53.65$4f8m12a/ifd4f 2006.260.08:08:53.65$ifd4f/lo= 2006.260.08:08:53.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:08:53.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:08:53.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:08:53.65$ifd4f/patch= 2006.260.08:08:53.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:08:53.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:08:53.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:08:53.65$4f8m12a/"form=m,16.000,1:2 2006.260.08:08:53.65$4f8m12a/"tpicd 2006.260.08:08:53.65$4f8m12a/echo=off 2006.260.08:08:53.65$4f8m12a/xlog=off 2006.260.08:08:53.65:!2006.260.08:09:20 2006.260.08:09:01.13#trakl#Source acquired 2006.260.08:09:02.13#flagr#flagr/antenna,acquired 2006.260.08:09:20.00:preob 2006.260.08:09:21.13/onsource/TRACKING 2006.260.08:09:21.13:!2006.260.08:09:30 2006.260.08:09:30.00:data_valid=on 2006.260.08:09:30.00:midob 2006.260.08:09:30.13/onsource/TRACKING 2006.260.08:09:30.13/wx/22.80,1010.4,89 2006.260.08:09:30.23/cable/+6.4580E-03 2006.260.08:09:31.32/va/01,08,usb,yes,31,32 2006.260.08:09:31.32/va/02,07,usb,yes,31,32 2006.260.08:09:31.32/va/03,08,usb,yes,23,24 2006.260.08:09:31.32/va/04,07,usb,yes,32,35 2006.260.08:09:31.32/va/05,07,usb,yes,35,37 2006.260.08:09:31.32/va/06,06,usb,yes,34,34 2006.260.08:09:31.32/va/07,06,usb,yes,35,35 2006.260.08:09:31.32/va/08,06,usb,yes,37,37 2006.260.08:09:31.55/valo/01,532.99,yes,locked 2006.260.08:09:31.55/valo/02,572.99,yes,locked 2006.260.08:09:31.55/valo/03,672.99,yes,locked 2006.260.08:09:31.55/valo/04,832.99,yes,locked 2006.260.08:09:31.55/valo/05,652.99,yes,locked 2006.260.08:09:31.55/valo/06,772.99,yes,locked 2006.260.08:09:31.55/valo/07,832.99,yes,locked 2006.260.08:09:31.55/valo/08,852.99,yes,locked 2006.260.08:09:32.64/vb/01,04,usb,yes,30,29 2006.260.08:09:32.64/vb/02,05,usb,yes,28,29 2006.260.08:09:32.64/vb/03,04,usb,yes,28,32 2006.260.08:09:32.64/vb/04,05,usb,yes,26,26 2006.260.08:09:32.64/vb/05,04,usb,yes,28,32 2006.260.08:09:32.64/vb/06,04,usb,yes,29,31 2006.260.08:09:32.64/vb/07,04,usb,yes,31,31 2006.260.08:09:32.64/vb/08,04,usb,yes,28,32 2006.260.08:09:32.88/vblo/01,632.99,yes,locked 2006.260.08:09:32.88/vblo/02,640.99,yes,locked 2006.260.08:09:32.88/vblo/03,656.99,yes,locked 2006.260.08:09:32.88/vblo/04,712.99,yes,locked 2006.260.08:09:32.88/vblo/05,744.99,yes,locked 2006.260.08:09:32.88/vblo/06,752.99,yes,locked 2006.260.08:09:32.88/vblo/07,734.99,yes,locked 2006.260.08:09:32.88/vblo/08,744.99,yes,locked 2006.260.08:09:33.03/vabw/8 2006.260.08:09:33.18/vbbw/8 2006.260.08:09:33.28/xfe/off,on,15.5 2006.260.08:09:33.66/ifatt/23,28,28,28 2006.260.08:09:34.08/fmout-gps/S +4.46E-07 2006.260.08:09:34.12:!2006.260.08:10:30 2006.260.08:10:30.00:data_valid=off 2006.260.08:10:30.00:postob 2006.260.08:10:30.07/cable/+6.4592E-03 2006.260.08:10:30.07/wx/22.79,1010.4,89 2006.260.08:10:31.08/fmout-gps/S +4.44E-07 2006.260.08:10:31.08:scan_name=260-0811,k06260,70 2006.260.08:10:31.09:source=1252+119,125438.26,114105.9,2000.0,ccw 2006.260.08:10:31.13#flagr#flagr/antenna,new-source 2006.260.08:10:32.13:checkk5 2006.260.08:10:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:10:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:10:33.32/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:10:33.72/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:10:34.14/chk_obsdata//k5ts1/T2600809??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:10:34.53/chk_obsdata//k5ts2/T2600809??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:10:34.91/chk_obsdata//k5ts3/T2600809??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:10:35.34/chk_obsdata//k5ts4/T2600809??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:10:36.08/k5log//k5ts1_log_newline 2006.260.08:10:36.87/k5log//k5ts2_log_newline 2006.260.08:10:37.65/k5log//k5ts3_log_newline 2006.260.08:10:38.51/k5log//k5ts4_log_newline 2006.260.08:10:38.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:10:38.53:4f8m12a=2 2006.260.08:10:38.53$4f8m12a/echo=on 2006.260.08:10:38.53$4f8m12a/pcalon 2006.260.08:10:38.53$pcalon/"no phase cal control is implemented here 2006.260.08:10:38.53$4f8m12a/"tpicd=stop 2006.260.08:10:38.53$4f8m12a/vc4f8 2006.260.08:10:38.53$vc4f8/valo=1,532.99 2006.260.08:10:38.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:10:38.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:10:38.53#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:38.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:38.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:38.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:38.53#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:10:38.53#ibcon#first serial, iclass 5, count 0 2006.260.08:10:38.53#ibcon#enter sib2, iclass 5, count 0 2006.260.08:10:38.53#ibcon#flushed, iclass 5, count 0 2006.260.08:10:38.53#ibcon#about to write, iclass 5, count 0 2006.260.08:10:38.53#ibcon#wrote, iclass 5, count 0 2006.260.08:10:38.53#ibcon#about to read 3, iclass 5, count 0 2006.260.08:10:38.58#ibcon#read 3, iclass 5, count 0 2006.260.08:10:38.58#ibcon#about to read 4, iclass 5, count 0 2006.260.08:10:38.58#ibcon#read 4, iclass 5, count 0 2006.260.08:10:38.58#ibcon#about to read 5, iclass 5, count 0 2006.260.08:10:38.58#ibcon#read 5, iclass 5, count 0 2006.260.08:10:38.58#ibcon#about to read 6, iclass 5, count 0 2006.260.08:10:38.58#ibcon#read 6, iclass 5, count 0 2006.260.08:10:38.58#ibcon#end of sib2, iclass 5, count 0 2006.260.08:10:38.58#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:10:38.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:10:38.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:10:38.58#ibcon#*before write, iclass 5, count 0 2006.260.08:10:38.58#ibcon#enter sib2, iclass 5, count 0 2006.260.08:10:38.58#ibcon#flushed, iclass 5, count 0 2006.260.08:10:38.58#ibcon#about to write, iclass 5, count 0 2006.260.08:10:38.58#ibcon#wrote, iclass 5, count 0 2006.260.08:10:38.58#ibcon#about to read 3, iclass 5, count 0 2006.260.08:10:38.63#ibcon#read 3, iclass 5, count 0 2006.260.08:10:38.63#ibcon#about to read 4, iclass 5, count 0 2006.260.08:10:38.63#ibcon#read 4, iclass 5, count 0 2006.260.08:10:38.63#ibcon#about to read 5, iclass 5, count 0 2006.260.08:10:38.63#ibcon#read 5, iclass 5, count 0 2006.260.08:10:38.63#ibcon#about to read 6, iclass 5, count 0 2006.260.08:10:38.63#ibcon#read 6, iclass 5, count 0 2006.260.08:10:38.63#ibcon#end of sib2, iclass 5, count 0 2006.260.08:10:38.63#ibcon#*after write, iclass 5, count 0 2006.260.08:10:38.63#ibcon#*before return 0, iclass 5, count 0 2006.260.08:10:38.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:38.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:38.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:10:38.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:10:38.63$vc4f8/va=1,8 2006.260.08:10:38.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:10:38.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:10:38.63#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:38.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:38.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:38.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:38.63#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:10:38.63#ibcon#first serial, iclass 7, count 2 2006.260.08:10:38.63#ibcon#enter sib2, iclass 7, count 2 2006.260.08:10:38.63#ibcon#flushed, iclass 7, count 2 2006.260.08:10:38.63#ibcon#about to write, iclass 7, count 2 2006.260.08:10:38.63#ibcon#wrote, iclass 7, count 2 2006.260.08:10:38.63#ibcon#about to read 3, iclass 7, count 2 2006.260.08:10:38.66#ibcon#read 3, iclass 7, count 2 2006.260.08:10:38.66#ibcon#about to read 4, iclass 7, count 2 2006.260.08:10:38.66#ibcon#read 4, iclass 7, count 2 2006.260.08:10:38.66#ibcon#about to read 5, iclass 7, count 2 2006.260.08:10:38.66#ibcon#read 5, iclass 7, count 2 2006.260.08:10:38.66#ibcon#about to read 6, iclass 7, count 2 2006.260.08:10:38.66#ibcon#read 6, iclass 7, count 2 2006.260.08:10:38.66#ibcon#end of sib2, iclass 7, count 2 2006.260.08:10:38.66#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:10:38.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:10:38.66#ibcon#[25=AT01-08\r\n] 2006.260.08:10:38.66#ibcon#*before write, iclass 7, count 2 2006.260.08:10:38.66#ibcon#enter sib2, iclass 7, count 2 2006.260.08:10:38.66#ibcon#flushed, iclass 7, count 2 2006.260.08:10:38.66#ibcon#about to write, iclass 7, count 2 2006.260.08:10:38.66#ibcon#wrote, iclass 7, count 2 2006.260.08:10:38.66#ibcon#about to read 3, iclass 7, count 2 2006.260.08:10:38.69#ibcon#read 3, iclass 7, count 2 2006.260.08:10:38.69#ibcon#about to read 4, iclass 7, count 2 2006.260.08:10:38.69#ibcon#read 4, iclass 7, count 2 2006.260.08:10:38.69#ibcon#about to read 5, iclass 7, count 2 2006.260.08:10:38.69#ibcon#read 5, iclass 7, count 2 2006.260.08:10:38.69#ibcon#about to read 6, iclass 7, count 2 2006.260.08:10:38.69#ibcon#read 6, iclass 7, count 2 2006.260.08:10:38.69#ibcon#end of sib2, iclass 7, count 2 2006.260.08:10:38.69#ibcon#*after write, iclass 7, count 2 2006.260.08:10:38.69#ibcon#*before return 0, iclass 7, count 2 2006.260.08:10:38.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:38.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:38.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:10:38.69#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:38.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:38.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:38.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:38.81#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:10:38.81#ibcon#first serial, iclass 7, count 0 2006.260.08:10:38.81#ibcon#enter sib2, iclass 7, count 0 2006.260.08:10:38.81#ibcon#flushed, iclass 7, count 0 2006.260.08:10:38.81#ibcon#about to write, iclass 7, count 0 2006.260.08:10:38.81#ibcon#wrote, iclass 7, count 0 2006.260.08:10:38.81#ibcon#about to read 3, iclass 7, count 0 2006.260.08:10:38.83#ibcon#read 3, iclass 7, count 0 2006.260.08:10:38.83#ibcon#about to read 4, iclass 7, count 0 2006.260.08:10:38.83#ibcon#read 4, iclass 7, count 0 2006.260.08:10:38.83#ibcon#about to read 5, iclass 7, count 0 2006.260.08:10:38.83#ibcon#read 5, iclass 7, count 0 2006.260.08:10:38.83#ibcon#about to read 6, iclass 7, count 0 2006.260.08:10:38.83#ibcon#read 6, iclass 7, count 0 2006.260.08:10:38.83#ibcon#end of sib2, iclass 7, count 0 2006.260.08:10:38.83#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:10:38.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:10:38.83#ibcon#[25=USB\r\n] 2006.260.08:10:38.83#ibcon#*before write, iclass 7, count 0 2006.260.08:10:38.83#ibcon#enter sib2, iclass 7, count 0 2006.260.08:10:38.83#ibcon#flushed, iclass 7, count 0 2006.260.08:10:38.83#ibcon#about to write, iclass 7, count 0 2006.260.08:10:38.83#ibcon#wrote, iclass 7, count 0 2006.260.08:10:38.83#ibcon#about to read 3, iclass 7, count 0 2006.260.08:10:38.86#ibcon#read 3, iclass 7, count 0 2006.260.08:10:38.86#ibcon#about to read 4, iclass 7, count 0 2006.260.08:10:38.86#ibcon#read 4, iclass 7, count 0 2006.260.08:10:38.86#ibcon#about to read 5, iclass 7, count 0 2006.260.08:10:38.86#ibcon#read 5, iclass 7, count 0 2006.260.08:10:38.86#ibcon#about to read 6, iclass 7, count 0 2006.260.08:10:38.86#ibcon#read 6, iclass 7, count 0 2006.260.08:10:38.86#ibcon#end of sib2, iclass 7, count 0 2006.260.08:10:38.86#ibcon#*after write, iclass 7, count 0 2006.260.08:10:38.86#ibcon#*before return 0, iclass 7, count 0 2006.260.08:10:38.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:38.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:38.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:10:38.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:10:38.86$vc4f8/valo=2,572.99 2006.260.08:10:38.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:10:38.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:10:38.86#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:38.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:38.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:38.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:38.86#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:10:38.86#ibcon#first serial, iclass 11, count 0 2006.260.08:10:38.86#ibcon#enter sib2, iclass 11, count 0 2006.260.08:10:38.86#ibcon#flushed, iclass 11, count 0 2006.260.08:10:38.86#ibcon#about to write, iclass 11, count 0 2006.260.08:10:38.86#ibcon#wrote, iclass 11, count 0 2006.260.08:10:38.86#ibcon#about to read 3, iclass 11, count 0 2006.260.08:10:38.88#ibcon#read 3, iclass 11, count 0 2006.260.08:10:38.88#ibcon#about to read 4, iclass 11, count 0 2006.260.08:10:38.88#ibcon#read 4, iclass 11, count 0 2006.260.08:10:38.88#ibcon#about to read 5, iclass 11, count 0 2006.260.08:10:38.88#ibcon#read 5, iclass 11, count 0 2006.260.08:10:38.88#ibcon#about to read 6, iclass 11, count 0 2006.260.08:10:38.88#ibcon#read 6, iclass 11, count 0 2006.260.08:10:38.88#ibcon#end of sib2, iclass 11, count 0 2006.260.08:10:38.88#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:10:38.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:10:38.88#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:10:38.88#ibcon#*before write, iclass 11, count 0 2006.260.08:10:38.88#ibcon#enter sib2, iclass 11, count 0 2006.260.08:10:38.88#ibcon#flushed, iclass 11, count 0 2006.260.08:10:38.88#ibcon#about to write, iclass 11, count 0 2006.260.08:10:38.88#ibcon#wrote, iclass 11, count 0 2006.260.08:10:38.88#ibcon#about to read 3, iclass 11, count 0 2006.260.08:10:38.92#ibcon#read 3, iclass 11, count 0 2006.260.08:10:38.92#ibcon#about to read 4, iclass 11, count 0 2006.260.08:10:38.92#ibcon#read 4, iclass 11, count 0 2006.260.08:10:38.92#ibcon#about to read 5, iclass 11, count 0 2006.260.08:10:38.92#ibcon#read 5, iclass 11, count 0 2006.260.08:10:38.92#ibcon#about to read 6, iclass 11, count 0 2006.260.08:10:38.92#ibcon#read 6, iclass 11, count 0 2006.260.08:10:38.92#ibcon#end of sib2, iclass 11, count 0 2006.260.08:10:38.92#ibcon#*after write, iclass 11, count 0 2006.260.08:10:38.92#ibcon#*before return 0, iclass 11, count 0 2006.260.08:10:38.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:38.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:38.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:10:38.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:10:38.92$vc4f8/va=2,7 2006.260.08:10:38.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.08:10:38.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.08:10:38.92#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:38.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:38.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:38.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:38.98#ibcon#enter wrdev, iclass 13, count 2 2006.260.08:10:38.98#ibcon#first serial, iclass 13, count 2 2006.260.08:10:38.98#ibcon#enter sib2, iclass 13, count 2 2006.260.08:10:38.98#ibcon#flushed, iclass 13, count 2 2006.260.08:10:38.98#ibcon#about to write, iclass 13, count 2 2006.260.08:10:38.98#ibcon#wrote, iclass 13, count 2 2006.260.08:10:38.98#ibcon#about to read 3, iclass 13, count 2 2006.260.08:10:39.01#ibcon#read 3, iclass 13, count 2 2006.260.08:10:39.01#ibcon#about to read 4, iclass 13, count 2 2006.260.08:10:39.01#ibcon#read 4, iclass 13, count 2 2006.260.08:10:39.01#ibcon#about to read 5, iclass 13, count 2 2006.260.08:10:39.01#ibcon#read 5, iclass 13, count 2 2006.260.08:10:39.01#ibcon#about to read 6, iclass 13, count 2 2006.260.08:10:39.01#ibcon#read 6, iclass 13, count 2 2006.260.08:10:39.01#ibcon#end of sib2, iclass 13, count 2 2006.260.08:10:39.01#ibcon#*mode == 0, iclass 13, count 2 2006.260.08:10:39.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.08:10:39.01#ibcon#[25=AT02-07\r\n] 2006.260.08:10:39.01#ibcon#*before write, iclass 13, count 2 2006.260.08:10:39.01#ibcon#enter sib2, iclass 13, count 2 2006.260.08:10:39.01#ibcon#flushed, iclass 13, count 2 2006.260.08:10:39.01#ibcon#about to write, iclass 13, count 2 2006.260.08:10:39.01#ibcon#wrote, iclass 13, count 2 2006.260.08:10:39.01#ibcon#about to read 3, iclass 13, count 2 2006.260.08:10:39.04#ibcon#read 3, iclass 13, count 2 2006.260.08:10:39.04#ibcon#about to read 4, iclass 13, count 2 2006.260.08:10:39.04#ibcon#read 4, iclass 13, count 2 2006.260.08:10:39.04#ibcon#about to read 5, iclass 13, count 2 2006.260.08:10:39.04#ibcon#read 5, iclass 13, count 2 2006.260.08:10:39.04#ibcon#about to read 6, iclass 13, count 2 2006.260.08:10:39.04#ibcon#read 6, iclass 13, count 2 2006.260.08:10:39.04#ibcon#end of sib2, iclass 13, count 2 2006.260.08:10:39.04#ibcon#*after write, iclass 13, count 2 2006.260.08:10:39.04#ibcon#*before return 0, iclass 13, count 2 2006.260.08:10:39.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:39.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:39.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.08:10:39.04#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:39.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:39.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:39.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:39.16#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:10:39.16#ibcon#first serial, iclass 13, count 0 2006.260.08:10:39.16#ibcon#enter sib2, iclass 13, count 0 2006.260.08:10:39.16#ibcon#flushed, iclass 13, count 0 2006.260.08:10:39.16#ibcon#about to write, iclass 13, count 0 2006.260.08:10:39.16#ibcon#wrote, iclass 13, count 0 2006.260.08:10:39.16#ibcon#about to read 3, iclass 13, count 0 2006.260.08:10:39.20#ibcon#read 3, iclass 13, count 0 2006.260.08:10:39.20#ibcon#about to read 4, iclass 13, count 0 2006.260.08:10:39.20#ibcon#read 4, iclass 13, count 0 2006.260.08:10:39.20#ibcon#about to read 5, iclass 13, count 0 2006.260.08:10:39.20#ibcon#read 5, iclass 13, count 0 2006.260.08:10:39.20#ibcon#about to read 6, iclass 13, count 0 2006.260.08:10:39.20#ibcon#read 6, iclass 13, count 0 2006.260.08:10:39.20#ibcon#end of sib2, iclass 13, count 0 2006.260.08:10:39.20#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:10:39.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:10:39.20#ibcon#[25=USB\r\n] 2006.260.08:10:39.20#ibcon#*before write, iclass 13, count 0 2006.260.08:10:39.20#ibcon#enter sib2, iclass 13, count 0 2006.260.08:10:39.20#ibcon#flushed, iclass 13, count 0 2006.260.08:10:39.20#ibcon#about to write, iclass 13, count 0 2006.260.08:10:39.20#ibcon#wrote, iclass 13, count 0 2006.260.08:10:39.20#ibcon#about to read 3, iclass 13, count 0 2006.260.08:10:39.23#ibcon#read 3, iclass 13, count 0 2006.260.08:10:39.23#ibcon#about to read 4, iclass 13, count 0 2006.260.08:10:39.23#ibcon#read 4, iclass 13, count 0 2006.260.08:10:39.23#ibcon#about to read 5, iclass 13, count 0 2006.260.08:10:39.23#ibcon#read 5, iclass 13, count 0 2006.260.08:10:39.23#ibcon#about to read 6, iclass 13, count 0 2006.260.08:10:39.23#ibcon#read 6, iclass 13, count 0 2006.260.08:10:39.23#ibcon#end of sib2, iclass 13, count 0 2006.260.08:10:39.23#ibcon#*after write, iclass 13, count 0 2006.260.08:10:39.23#ibcon#*before return 0, iclass 13, count 0 2006.260.08:10:39.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:39.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:39.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:10:39.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:10:39.23$vc4f8/valo=3,672.99 2006.260.08:10:39.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:10:39.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:10:39.23#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:39.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:39.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:39.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:39.23#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:10:39.23#ibcon#first serial, iclass 15, count 0 2006.260.08:10:39.23#ibcon#enter sib2, iclass 15, count 0 2006.260.08:10:39.23#ibcon#flushed, iclass 15, count 0 2006.260.08:10:39.23#ibcon#about to write, iclass 15, count 0 2006.260.08:10:39.23#ibcon#wrote, iclass 15, count 0 2006.260.08:10:39.23#ibcon#about to read 3, iclass 15, count 0 2006.260.08:10:39.25#ibcon#read 3, iclass 15, count 0 2006.260.08:10:39.25#ibcon#about to read 4, iclass 15, count 0 2006.260.08:10:39.25#ibcon#read 4, iclass 15, count 0 2006.260.08:10:39.25#ibcon#about to read 5, iclass 15, count 0 2006.260.08:10:39.25#ibcon#read 5, iclass 15, count 0 2006.260.08:10:39.25#ibcon#about to read 6, iclass 15, count 0 2006.260.08:10:39.25#ibcon#read 6, iclass 15, count 0 2006.260.08:10:39.25#ibcon#end of sib2, iclass 15, count 0 2006.260.08:10:39.25#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:10:39.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:10:39.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:10:39.25#ibcon#*before write, iclass 15, count 0 2006.260.08:10:39.25#ibcon#enter sib2, iclass 15, count 0 2006.260.08:10:39.25#ibcon#flushed, iclass 15, count 0 2006.260.08:10:39.25#ibcon#about to write, iclass 15, count 0 2006.260.08:10:39.25#ibcon#wrote, iclass 15, count 0 2006.260.08:10:39.25#ibcon#about to read 3, iclass 15, count 0 2006.260.08:10:39.29#ibcon#read 3, iclass 15, count 0 2006.260.08:10:39.29#ibcon#about to read 4, iclass 15, count 0 2006.260.08:10:39.29#ibcon#read 4, iclass 15, count 0 2006.260.08:10:39.29#ibcon#about to read 5, iclass 15, count 0 2006.260.08:10:39.29#ibcon#read 5, iclass 15, count 0 2006.260.08:10:39.29#ibcon#about to read 6, iclass 15, count 0 2006.260.08:10:39.29#ibcon#read 6, iclass 15, count 0 2006.260.08:10:39.29#ibcon#end of sib2, iclass 15, count 0 2006.260.08:10:39.29#ibcon#*after write, iclass 15, count 0 2006.260.08:10:39.29#ibcon#*before return 0, iclass 15, count 0 2006.260.08:10:39.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:39.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:39.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:10:39.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:10:39.29$vc4f8/va=3,8 2006.260.08:10:39.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:10:39.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:10:39.29#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:39.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:39.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:39.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:39.35#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:10:39.35#ibcon#first serial, iclass 17, count 2 2006.260.08:10:39.35#ibcon#enter sib2, iclass 17, count 2 2006.260.08:10:39.35#ibcon#flushed, iclass 17, count 2 2006.260.08:10:39.35#ibcon#about to write, iclass 17, count 2 2006.260.08:10:39.35#ibcon#wrote, iclass 17, count 2 2006.260.08:10:39.35#ibcon#about to read 3, iclass 17, count 2 2006.260.08:10:39.37#ibcon#read 3, iclass 17, count 2 2006.260.08:10:39.37#ibcon#about to read 4, iclass 17, count 2 2006.260.08:10:39.37#ibcon#read 4, iclass 17, count 2 2006.260.08:10:39.37#ibcon#about to read 5, iclass 17, count 2 2006.260.08:10:39.37#ibcon#read 5, iclass 17, count 2 2006.260.08:10:39.37#ibcon#about to read 6, iclass 17, count 2 2006.260.08:10:39.37#ibcon#read 6, iclass 17, count 2 2006.260.08:10:39.37#ibcon#end of sib2, iclass 17, count 2 2006.260.08:10:39.37#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:10:39.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:10:39.37#ibcon#[25=AT03-08\r\n] 2006.260.08:10:39.37#ibcon#*before write, iclass 17, count 2 2006.260.08:10:39.37#ibcon#enter sib2, iclass 17, count 2 2006.260.08:10:39.37#ibcon#flushed, iclass 17, count 2 2006.260.08:10:39.37#ibcon#about to write, iclass 17, count 2 2006.260.08:10:39.37#ibcon#wrote, iclass 17, count 2 2006.260.08:10:39.37#ibcon#about to read 3, iclass 17, count 2 2006.260.08:10:39.40#ibcon#read 3, iclass 17, count 2 2006.260.08:10:39.40#ibcon#about to read 4, iclass 17, count 2 2006.260.08:10:39.40#ibcon#read 4, iclass 17, count 2 2006.260.08:10:39.40#ibcon#about to read 5, iclass 17, count 2 2006.260.08:10:39.40#ibcon#read 5, iclass 17, count 2 2006.260.08:10:39.40#ibcon#about to read 6, iclass 17, count 2 2006.260.08:10:39.40#ibcon#read 6, iclass 17, count 2 2006.260.08:10:39.40#ibcon#end of sib2, iclass 17, count 2 2006.260.08:10:39.40#ibcon#*after write, iclass 17, count 2 2006.260.08:10:39.40#ibcon#*before return 0, iclass 17, count 2 2006.260.08:10:39.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:39.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:39.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:10:39.40#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:39.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:39.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:39.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:39.52#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:10:39.52#ibcon#first serial, iclass 17, count 0 2006.260.08:10:39.52#ibcon#enter sib2, iclass 17, count 0 2006.260.08:10:39.52#ibcon#flushed, iclass 17, count 0 2006.260.08:10:39.52#ibcon#about to write, iclass 17, count 0 2006.260.08:10:39.52#ibcon#wrote, iclass 17, count 0 2006.260.08:10:39.52#ibcon#about to read 3, iclass 17, count 0 2006.260.08:10:39.54#ibcon#read 3, iclass 17, count 0 2006.260.08:10:39.54#ibcon#about to read 4, iclass 17, count 0 2006.260.08:10:39.54#ibcon#read 4, iclass 17, count 0 2006.260.08:10:39.54#ibcon#about to read 5, iclass 17, count 0 2006.260.08:10:39.54#ibcon#read 5, iclass 17, count 0 2006.260.08:10:39.54#ibcon#about to read 6, iclass 17, count 0 2006.260.08:10:39.54#ibcon#read 6, iclass 17, count 0 2006.260.08:10:39.54#ibcon#end of sib2, iclass 17, count 0 2006.260.08:10:39.54#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:10:39.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:10:39.54#ibcon#[25=USB\r\n] 2006.260.08:10:39.54#ibcon#*before write, iclass 17, count 0 2006.260.08:10:39.54#ibcon#enter sib2, iclass 17, count 0 2006.260.08:10:39.54#ibcon#flushed, iclass 17, count 0 2006.260.08:10:39.54#ibcon#about to write, iclass 17, count 0 2006.260.08:10:39.54#ibcon#wrote, iclass 17, count 0 2006.260.08:10:39.54#ibcon#about to read 3, iclass 17, count 0 2006.260.08:10:39.57#ibcon#read 3, iclass 17, count 0 2006.260.08:10:39.57#ibcon#about to read 4, iclass 17, count 0 2006.260.08:10:39.57#ibcon#read 4, iclass 17, count 0 2006.260.08:10:39.57#ibcon#about to read 5, iclass 17, count 0 2006.260.08:10:39.57#ibcon#read 5, iclass 17, count 0 2006.260.08:10:39.57#ibcon#about to read 6, iclass 17, count 0 2006.260.08:10:39.57#ibcon#read 6, iclass 17, count 0 2006.260.08:10:39.57#ibcon#end of sib2, iclass 17, count 0 2006.260.08:10:39.57#ibcon#*after write, iclass 17, count 0 2006.260.08:10:39.57#ibcon#*before return 0, iclass 17, count 0 2006.260.08:10:39.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:39.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:39.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:10:39.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:10:39.57$vc4f8/valo=4,832.99 2006.260.08:10:39.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:10:39.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:10:39.57#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:39.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:39.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:39.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:39.57#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:10:39.57#ibcon#first serial, iclass 19, count 0 2006.260.08:10:39.57#ibcon#enter sib2, iclass 19, count 0 2006.260.08:10:39.57#ibcon#flushed, iclass 19, count 0 2006.260.08:10:39.57#ibcon#about to write, iclass 19, count 0 2006.260.08:10:39.57#ibcon#wrote, iclass 19, count 0 2006.260.08:10:39.57#ibcon#about to read 3, iclass 19, count 0 2006.260.08:10:39.59#ibcon#read 3, iclass 19, count 0 2006.260.08:10:39.59#ibcon#about to read 4, iclass 19, count 0 2006.260.08:10:39.59#ibcon#read 4, iclass 19, count 0 2006.260.08:10:39.59#ibcon#about to read 5, iclass 19, count 0 2006.260.08:10:39.59#ibcon#read 5, iclass 19, count 0 2006.260.08:10:39.59#ibcon#about to read 6, iclass 19, count 0 2006.260.08:10:39.59#ibcon#read 6, iclass 19, count 0 2006.260.08:10:39.59#ibcon#end of sib2, iclass 19, count 0 2006.260.08:10:39.59#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:10:39.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:10:39.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:10:39.59#ibcon#*before write, iclass 19, count 0 2006.260.08:10:39.59#ibcon#enter sib2, iclass 19, count 0 2006.260.08:10:39.59#ibcon#flushed, iclass 19, count 0 2006.260.08:10:39.59#ibcon#about to write, iclass 19, count 0 2006.260.08:10:39.59#ibcon#wrote, iclass 19, count 0 2006.260.08:10:39.59#ibcon#about to read 3, iclass 19, count 0 2006.260.08:10:39.63#ibcon#read 3, iclass 19, count 0 2006.260.08:10:39.63#ibcon#about to read 4, iclass 19, count 0 2006.260.08:10:39.63#ibcon#read 4, iclass 19, count 0 2006.260.08:10:39.63#ibcon#about to read 5, iclass 19, count 0 2006.260.08:10:39.63#ibcon#read 5, iclass 19, count 0 2006.260.08:10:39.63#ibcon#about to read 6, iclass 19, count 0 2006.260.08:10:39.63#ibcon#read 6, iclass 19, count 0 2006.260.08:10:39.63#ibcon#end of sib2, iclass 19, count 0 2006.260.08:10:39.63#ibcon#*after write, iclass 19, count 0 2006.260.08:10:39.63#ibcon#*before return 0, iclass 19, count 0 2006.260.08:10:39.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:39.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:39.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:10:39.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:10:39.63$vc4f8/va=4,7 2006.260.08:10:39.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.08:10:39.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.08:10:39.63#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:39.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:39.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:39.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:39.69#ibcon#enter wrdev, iclass 21, count 2 2006.260.08:10:39.69#ibcon#first serial, iclass 21, count 2 2006.260.08:10:39.69#ibcon#enter sib2, iclass 21, count 2 2006.260.08:10:39.69#ibcon#flushed, iclass 21, count 2 2006.260.08:10:39.69#ibcon#about to write, iclass 21, count 2 2006.260.08:10:39.69#ibcon#wrote, iclass 21, count 2 2006.260.08:10:39.69#ibcon#about to read 3, iclass 21, count 2 2006.260.08:10:39.71#ibcon#read 3, iclass 21, count 2 2006.260.08:10:39.71#ibcon#about to read 4, iclass 21, count 2 2006.260.08:10:39.71#ibcon#read 4, iclass 21, count 2 2006.260.08:10:39.71#ibcon#about to read 5, iclass 21, count 2 2006.260.08:10:39.71#ibcon#read 5, iclass 21, count 2 2006.260.08:10:39.71#ibcon#about to read 6, iclass 21, count 2 2006.260.08:10:39.71#ibcon#read 6, iclass 21, count 2 2006.260.08:10:39.71#ibcon#end of sib2, iclass 21, count 2 2006.260.08:10:39.71#ibcon#*mode == 0, iclass 21, count 2 2006.260.08:10:39.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.08:10:39.71#ibcon#[25=AT04-07\r\n] 2006.260.08:10:39.71#ibcon#*before write, iclass 21, count 2 2006.260.08:10:39.71#ibcon#enter sib2, iclass 21, count 2 2006.260.08:10:39.71#ibcon#flushed, iclass 21, count 2 2006.260.08:10:39.71#ibcon#about to write, iclass 21, count 2 2006.260.08:10:39.71#ibcon#wrote, iclass 21, count 2 2006.260.08:10:39.71#ibcon#about to read 3, iclass 21, count 2 2006.260.08:10:39.74#ibcon#read 3, iclass 21, count 2 2006.260.08:10:39.74#ibcon#about to read 4, iclass 21, count 2 2006.260.08:10:39.74#ibcon#read 4, iclass 21, count 2 2006.260.08:10:39.74#ibcon#about to read 5, iclass 21, count 2 2006.260.08:10:39.74#ibcon#read 5, iclass 21, count 2 2006.260.08:10:39.74#ibcon#about to read 6, iclass 21, count 2 2006.260.08:10:39.74#ibcon#read 6, iclass 21, count 2 2006.260.08:10:39.74#ibcon#end of sib2, iclass 21, count 2 2006.260.08:10:39.74#ibcon#*after write, iclass 21, count 2 2006.260.08:10:39.74#ibcon#*before return 0, iclass 21, count 2 2006.260.08:10:39.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:39.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:39.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.08:10:39.74#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:39.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:39.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:39.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:39.86#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:10:39.86#ibcon#first serial, iclass 21, count 0 2006.260.08:10:39.86#ibcon#enter sib2, iclass 21, count 0 2006.260.08:10:39.86#ibcon#flushed, iclass 21, count 0 2006.260.08:10:39.86#ibcon#about to write, iclass 21, count 0 2006.260.08:10:39.86#ibcon#wrote, iclass 21, count 0 2006.260.08:10:39.86#ibcon#about to read 3, iclass 21, count 0 2006.260.08:10:39.88#ibcon#read 3, iclass 21, count 0 2006.260.08:10:39.88#ibcon#about to read 4, iclass 21, count 0 2006.260.08:10:39.88#ibcon#read 4, iclass 21, count 0 2006.260.08:10:39.88#ibcon#about to read 5, iclass 21, count 0 2006.260.08:10:39.88#ibcon#read 5, iclass 21, count 0 2006.260.08:10:39.88#ibcon#about to read 6, iclass 21, count 0 2006.260.08:10:39.88#ibcon#read 6, iclass 21, count 0 2006.260.08:10:39.88#ibcon#end of sib2, iclass 21, count 0 2006.260.08:10:39.88#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:10:39.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:10:39.88#ibcon#[25=USB\r\n] 2006.260.08:10:39.88#ibcon#*before write, iclass 21, count 0 2006.260.08:10:39.88#ibcon#enter sib2, iclass 21, count 0 2006.260.08:10:39.88#ibcon#flushed, iclass 21, count 0 2006.260.08:10:39.88#ibcon#about to write, iclass 21, count 0 2006.260.08:10:39.88#ibcon#wrote, iclass 21, count 0 2006.260.08:10:39.88#ibcon#about to read 3, iclass 21, count 0 2006.260.08:10:39.91#ibcon#read 3, iclass 21, count 0 2006.260.08:10:39.91#ibcon#about to read 4, iclass 21, count 0 2006.260.08:10:39.91#ibcon#read 4, iclass 21, count 0 2006.260.08:10:39.91#ibcon#about to read 5, iclass 21, count 0 2006.260.08:10:39.91#ibcon#read 5, iclass 21, count 0 2006.260.08:10:39.91#ibcon#about to read 6, iclass 21, count 0 2006.260.08:10:39.91#ibcon#read 6, iclass 21, count 0 2006.260.08:10:39.91#ibcon#end of sib2, iclass 21, count 0 2006.260.08:10:39.91#ibcon#*after write, iclass 21, count 0 2006.260.08:10:39.91#ibcon#*before return 0, iclass 21, count 0 2006.260.08:10:39.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:39.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:39.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:10:39.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:10:39.91$vc4f8/valo=5,652.99 2006.260.08:10:39.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.08:10:39.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.08:10:39.91#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:39.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:39.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:39.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:39.91#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:10:39.91#ibcon#first serial, iclass 23, count 0 2006.260.08:10:39.91#ibcon#enter sib2, iclass 23, count 0 2006.260.08:10:39.91#ibcon#flushed, iclass 23, count 0 2006.260.08:10:39.91#ibcon#about to write, iclass 23, count 0 2006.260.08:10:39.91#ibcon#wrote, iclass 23, count 0 2006.260.08:10:39.91#ibcon#about to read 3, iclass 23, count 0 2006.260.08:10:39.93#ibcon#read 3, iclass 23, count 0 2006.260.08:10:39.93#ibcon#about to read 4, iclass 23, count 0 2006.260.08:10:39.93#ibcon#read 4, iclass 23, count 0 2006.260.08:10:39.93#ibcon#about to read 5, iclass 23, count 0 2006.260.08:10:39.93#ibcon#read 5, iclass 23, count 0 2006.260.08:10:39.93#ibcon#about to read 6, iclass 23, count 0 2006.260.08:10:39.93#ibcon#read 6, iclass 23, count 0 2006.260.08:10:39.93#ibcon#end of sib2, iclass 23, count 0 2006.260.08:10:39.93#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:10:39.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:10:39.93#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:10:39.93#ibcon#*before write, iclass 23, count 0 2006.260.08:10:39.93#ibcon#enter sib2, iclass 23, count 0 2006.260.08:10:39.93#ibcon#flushed, iclass 23, count 0 2006.260.08:10:39.93#ibcon#about to write, iclass 23, count 0 2006.260.08:10:39.93#ibcon#wrote, iclass 23, count 0 2006.260.08:10:39.93#ibcon#about to read 3, iclass 23, count 0 2006.260.08:10:39.97#ibcon#read 3, iclass 23, count 0 2006.260.08:10:39.97#ibcon#about to read 4, iclass 23, count 0 2006.260.08:10:39.97#ibcon#read 4, iclass 23, count 0 2006.260.08:10:39.97#ibcon#about to read 5, iclass 23, count 0 2006.260.08:10:39.97#ibcon#read 5, iclass 23, count 0 2006.260.08:10:39.97#ibcon#about to read 6, iclass 23, count 0 2006.260.08:10:39.97#ibcon#read 6, iclass 23, count 0 2006.260.08:10:39.97#ibcon#end of sib2, iclass 23, count 0 2006.260.08:10:39.97#ibcon#*after write, iclass 23, count 0 2006.260.08:10:39.97#ibcon#*before return 0, iclass 23, count 0 2006.260.08:10:39.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:39.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:39.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:10:39.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:10:39.97$vc4f8/va=5,7 2006.260.08:10:39.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.08:10:39.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.08:10:39.97#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:39.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:40.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:40.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:40.03#ibcon#enter wrdev, iclass 25, count 2 2006.260.08:10:40.03#ibcon#first serial, iclass 25, count 2 2006.260.08:10:40.03#ibcon#enter sib2, iclass 25, count 2 2006.260.08:10:40.03#ibcon#flushed, iclass 25, count 2 2006.260.08:10:40.03#ibcon#about to write, iclass 25, count 2 2006.260.08:10:40.03#ibcon#wrote, iclass 25, count 2 2006.260.08:10:40.03#ibcon#about to read 3, iclass 25, count 2 2006.260.08:10:40.05#ibcon#read 3, iclass 25, count 2 2006.260.08:10:40.05#ibcon#about to read 4, iclass 25, count 2 2006.260.08:10:40.05#ibcon#read 4, iclass 25, count 2 2006.260.08:10:40.05#ibcon#about to read 5, iclass 25, count 2 2006.260.08:10:40.05#ibcon#read 5, iclass 25, count 2 2006.260.08:10:40.05#ibcon#about to read 6, iclass 25, count 2 2006.260.08:10:40.05#ibcon#read 6, iclass 25, count 2 2006.260.08:10:40.05#ibcon#end of sib2, iclass 25, count 2 2006.260.08:10:40.05#ibcon#*mode == 0, iclass 25, count 2 2006.260.08:10:40.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.08:10:40.05#ibcon#[25=AT05-07\r\n] 2006.260.08:10:40.05#ibcon#*before write, iclass 25, count 2 2006.260.08:10:40.05#ibcon#enter sib2, iclass 25, count 2 2006.260.08:10:40.05#ibcon#flushed, iclass 25, count 2 2006.260.08:10:40.05#ibcon#about to write, iclass 25, count 2 2006.260.08:10:40.05#ibcon#wrote, iclass 25, count 2 2006.260.08:10:40.05#ibcon#about to read 3, iclass 25, count 2 2006.260.08:10:40.08#ibcon#read 3, iclass 25, count 2 2006.260.08:10:40.08#ibcon#about to read 4, iclass 25, count 2 2006.260.08:10:40.08#ibcon#read 4, iclass 25, count 2 2006.260.08:10:40.08#ibcon#about to read 5, iclass 25, count 2 2006.260.08:10:40.08#ibcon#read 5, iclass 25, count 2 2006.260.08:10:40.08#ibcon#about to read 6, iclass 25, count 2 2006.260.08:10:40.08#ibcon#read 6, iclass 25, count 2 2006.260.08:10:40.08#ibcon#end of sib2, iclass 25, count 2 2006.260.08:10:40.08#ibcon#*after write, iclass 25, count 2 2006.260.08:10:40.08#ibcon#*before return 0, iclass 25, count 2 2006.260.08:10:40.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:40.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:40.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.08:10:40.08#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:40.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:40.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:40.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:40.20#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:10:40.20#ibcon#first serial, iclass 25, count 0 2006.260.08:10:40.20#ibcon#enter sib2, iclass 25, count 0 2006.260.08:10:40.20#ibcon#flushed, iclass 25, count 0 2006.260.08:10:40.20#ibcon#about to write, iclass 25, count 0 2006.260.08:10:40.20#ibcon#wrote, iclass 25, count 0 2006.260.08:10:40.20#ibcon#about to read 3, iclass 25, count 0 2006.260.08:10:40.22#ibcon#read 3, iclass 25, count 0 2006.260.08:10:40.22#ibcon#about to read 4, iclass 25, count 0 2006.260.08:10:40.22#ibcon#read 4, iclass 25, count 0 2006.260.08:10:40.22#ibcon#about to read 5, iclass 25, count 0 2006.260.08:10:40.22#ibcon#read 5, iclass 25, count 0 2006.260.08:10:40.22#ibcon#about to read 6, iclass 25, count 0 2006.260.08:10:40.22#ibcon#read 6, iclass 25, count 0 2006.260.08:10:40.22#ibcon#end of sib2, iclass 25, count 0 2006.260.08:10:40.22#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:10:40.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:10:40.22#ibcon#[25=USB\r\n] 2006.260.08:10:40.22#ibcon#*before write, iclass 25, count 0 2006.260.08:10:40.22#ibcon#enter sib2, iclass 25, count 0 2006.260.08:10:40.22#ibcon#flushed, iclass 25, count 0 2006.260.08:10:40.22#ibcon#about to write, iclass 25, count 0 2006.260.08:10:40.22#ibcon#wrote, iclass 25, count 0 2006.260.08:10:40.22#ibcon#about to read 3, iclass 25, count 0 2006.260.08:10:40.25#ibcon#read 3, iclass 25, count 0 2006.260.08:10:40.25#ibcon#about to read 4, iclass 25, count 0 2006.260.08:10:40.25#ibcon#read 4, iclass 25, count 0 2006.260.08:10:40.25#ibcon#about to read 5, iclass 25, count 0 2006.260.08:10:40.25#ibcon#read 5, iclass 25, count 0 2006.260.08:10:40.25#ibcon#about to read 6, iclass 25, count 0 2006.260.08:10:40.25#ibcon#read 6, iclass 25, count 0 2006.260.08:10:40.25#ibcon#end of sib2, iclass 25, count 0 2006.260.08:10:40.25#ibcon#*after write, iclass 25, count 0 2006.260.08:10:40.25#ibcon#*before return 0, iclass 25, count 0 2006.260.08:10:40.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:40.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:40.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:10:40.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:10:40.25$vc4f8/valo=6,772.99 2006.260.08:10:40.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.08:10:40.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.08:10:40.25#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:40.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:40.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:40.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:40.25#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:10:40.25#ibcon#first serial, iclass 27, count 0 2006.260.08:10:40.25#ibcon#enter sib2, iclass 27, count 0 2006.260.08:10:40.25#ibcon#flushed, iclass 27, count 0 2006.260.08:10:40.25#ibcon#about to write, iclass 27, count 0 2006.260.08:10:40.25#ibcon#wrote, iclass 27, count 0 2006.260.08:10:40.25#ibcon#about to read 3, iclass 27, count 0 2006.260.08:10:40.27#ibcon#read 3, iclass 27, count 0 2006.260.08:10:40.27#ibcon#about to read 4, iclass 27, count 0 2006.260.08:10:40.27#ibcon#read 4, iclass 27, count 0 2006.260.08:10:40.27#ibcon#about to read 5, iclass 27, count 0 2006.260.08:10:40.27#ibcon#read 5, iclass 27, count 0 2006.260.08:10:40.27#ibcon#about to read 6, iclass 27, count 0 2006.260.08:10:40.27#ibcon#read 6, iclass 27, count 0 2006.260.08:10:40.27#ibcon#end of sib2, iclass 27, count 0 2006.260.08:10:40.27#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:10:40.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:10:40.27#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:10:40.27#ibcon#*before write, iclass 27, count 0 2006.260.08:10:40.27#ibcon#enter sib2, iclass 27, count 0 2006.260.08:10:40.27#ibcon#flushed, iclass 27, count 0 2006.260.08:10:40.27#ibcon#about to write, iclass 27, count 0 2006.260.08:10:40.27#ibcon#wrote, iclass 27, count 0 2006.260.08:10:40.27#ibcon#about to read 3, iclass 27, count 0 2006.260.08:10:40.31#ibcon#read 3, iclass 27, count 0 2006.260.08:10:40.31#ibcon#about to read 4, iclass 27, count 0 2006.260.08:10:40.31#ibcon#read 4, iclass 27, count 0 2006.260.08:10:40.31#ibcon#about to read 5, iclass 27, count 0 2006.260.08:10:40.31#ibcon#read 5, iclass 27, count 0 2006.260.08:10:40.31#ibcon#about to read 6, iclass 27, count 0 2006.260.08:10:40.31#ibcon#read 6, iclass 27, count 0 2006.260.08:10:40.31#ibcon#end of sib2, iclass 27, count 0 2006.260.08:10:40.31#ibcon#*after write, iclass 27, count 0 2006.260.08:10:40.31#ibcon#*before return 0, iclass 27, count 0 2006.260.08:10:40.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:40.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:40.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:10:40.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:10:40.31$vc4f8/va=6,6 2006.260.08:10:40.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.08:10:40.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.08:10:40.31#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:40.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:40.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:40.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:40.37#ibcon#enter wrdev, iclass 29, count 2 2006.260.08:10:40.37#ibcon#first serial, iclass 29, count 2 2006.260.08:10:40.37#ibcon#enter sib2, iclass 29, count 2 2006.260.08:10:40.37#ibcon#flushed, iclass 29, count 2 2006.260.08:10:40.37#ibcon#about to write, iclass 29, count 2 2006.260.08:10:40.37#ibcon#wrote, iclass 29, count 2 2006.260.08:10:40.37#ibcon#about to read 3, iclass 29, count 2 2006.260.08:10:40.39#ibcon#read 3, iclass 29, count 2 2006.260.08:10:40.39#ibcon#about to read 4, iclass 29, count 2 2006.260.08:10:40.39#ibcon#read 4, iclass 29, count 2 2006.260.08:10:40.39#ibcon#about to read 5, iclass 29, count 2 2006.260.08:10:40.39#ibcon#read 5, iclass 29, count 2 2006.260.08:10:40.39#ibcon#about to read 6, iclass 29, count 2 2006.260.08:10:40.39#ibcon#read 6, iclass 29, count 2 2006.260.08:10:40.39#ibcon#end of sib2, iclass 29, count 2 2006.260.08:10:40.39#ibcon#*mode == 0, iclass 29, count 2 2006.260.08:10:40.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.08:10:40.39#ibcon#[25=AT06-06\r\n] 2006.260.08:10:40.39#ibcon#*before write, iclass 29, count 2 2006.260.08:10:40.39#ibcon#enter sib2, iclass 29, count 2 2006.260.08:10:40.39#ibcon#flushed, iclass 29, count 2 2006.260.08:10:40.39#ibcon#about to write, iclass 29, count 2 2006.260.08:10:40.39#ibcon#wrote, iclass 29, count 2 2006.260.08:10:40.39#ibcon#about to read 3, iclass 29, count 2 2006.260.08:10:40.42#ibcon#read 3, iclass 29, count 2 2006.260.08:10:40.42#ibcon#about to read 4, iclass 29, count 2 2006.260.08:10:40.42#ibcon#read 4, iclass 29, count 2 2006.260.08:10:40.42#ibcon#about to read 5, iclass 29, count 2 2006.260.08:10:40.42#ibcon#read 5, iclass 29, count 2 2006.260.08:10:40.42#ibcon#about to read 6, iclass 29, count 2 2006.260.08:10:40.42#ibcon#read 6, iclass 29, count 2 2006.260.08:10:40.42#ibcon#end of sib2, iclass 29, count 2 2006.260.08:10:40.42#ibcon#*after write, iclass 29, count 2 2006.260.08:10:40.42#ibcon#*before return 0, iclass 29, count 2 2006.260.08:10:40.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:40.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:40.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.08:10:40.42#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:40.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:10:40.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:10:40.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:10:40.54#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:10:40.54#ibcon#first serial, iclass 29, count 0 2006.260.08:10:40.54#ibcon#enter sib2, iclass 29, count 0 2006.260.08:10:40.54#ibcon#flushed, iclass 29, count 0 2006.260.08:10:40.54#ibcon#about to write, iclass 29, count 0 2006.260.08:10:40.54#ibcon#wrote, iclass 29, count 0 2006.260.08:10:40.54#ibcon#about to read 3, iclass 29, count 0 2006.260.08:10:40.56#ibcon#read 3, iclass 29, count 0 2006.260.08:10:40.56#ibcon#about to read 4, iclass 29, count 0 2006.260.08:10:40.56#ibcon#read 4, iclass 29, count 0 2006.260.08:10:40.56#ibcon#about to read 5, iclass 29, count 0 2006.260.08:10:40.56#ibcon#read 5, iclass 29, count 0 2006.260.08:10:40.56#ibcon#about to read 6, iclass 29, count 0 2006.260.08:10:40.56#ibcon#read 6, iclass 29, count 0 2006.260.08:10:40.56#ibcon#end of sib2, iclass 29, count 0 2006.260.08:10:40.56#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:10:40.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:10:40.56#ibcon#[25=USB\r\n] 2006.260.08:10:40.56#ibcon#*before write, iclass 29, count 0 2006.260.08:10:40.56#ibcon#enter sib2, iclass 29, count 0 2006.260.08:10:40.56#ibcon#flushed, iclass 29, count 0 2006.260.08:10:40.56#ibcon#about to write, iclass 29, count 0 2006.260.08:10:40.56#ibcon#wrote, iclass 29, count 0 2006.260.08:10:40.56#ibcon#about to read 3, iclass 29, count 0 2006.260.08:10:40.59#ibcon#read 3, iclass 29, count 0 2006.260.08:10:40.59#ibcon#about to read 4, iclass 29, count 0 2006.260.08:10:40.59#ibcon#read 4, iclass 29, count 0 2006.260.08:10:40.59#ibcon#about to read 5, iclass 29, count 0 2006.260.08:10:40.59#ibcon#read 5, iclass 29, count 0 2006.260.08:10:40.59#ibcon#about to read 6, iclass 29, count 0 2006.260.08:10:40.59#ibcon#read 6, iclass 29, count 0 2006.260.08:10:40.59#ibcon#end of sib2, iclass 29, count 0 2006.260.08:10:40.59#ibcon#*after write, iclass 29, count 0 2006.260.08:10:40.59#ibcon#*before return 0, iclass 29, count 0 2006.260.08:10:40.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:10:40.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:10:40.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:10:40.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:10:40.59$vc4f8/valo=7,832.99 2006.260.08:10:40.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.08:10:40.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.08:10:40.59#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:40.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:10:40.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:10:40.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:10:40.59#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:10:40.59#ibcon#first serial, iclass 31, count 0 2006.260.08:10:40.59#ibcon#enter sib2, iclass 31, count 0 2006.260.08:10:40.59#ibcon#flushed, iclass 31, count 0 2006.260.08:10:40.59#ibcon#about to write, iclass 31, count 0 2006.260.08:10:40.59#ibcon#wrote, iclass 31, count 0 2006.260.08:10:40.59#ibcon#about to read 3, iclass 31, count 0 2006.260.08:10:40.61#ibcon#read 3, iclass 31, count 0 2006.260.08:10:40.61#ibcon#about to read 4, iclass 31, count 0 2006.260.08:10:40.61#ibcon#read 4, iclass 31, count 0 2006.260.08:10:40.61#ibcon#about to read 5, iclass 31, count 0 2006.260.08:10:40.61#ibcon#read 5, iclass 31, count 0 2006.260.08:10:40.61#ibcon#about to read 6, iclass 31, count 0 2006.260.08:10:40.61#ibcon#read 6, iclass 31, count 0 2006.260.08:10:40.61#ibcon#end of sib2, iclass 31, count 0 2006.260.08:10:40.61#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:10:40.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:10:40.61#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:10:40.61#ibcon#*before write, iclass 31, count 0 2006.260.08:10:40.61#ibcon#enter sib2, iclass 31, count 0 2006.260.08:10:40.61#ibcon#flushed, iclass 31, count 0 2006.260.08:10:40.61#ibcon#about to write, iclass 31, count 0 2006.260.08:10:40.61#ibcon#wrote, iclass 31, count 0 2006.260.08:10:40.61#ibcon#about to read 3, iclass 31, count 0 2006.260.08:10:40.65#ibcon#read 3, iclass 31, count 0 2006.260.08:10:40.65#ibcon#about to read 4, iclass 31, count 0 2006.260.08:10:40.65#ibcon#read 4, iclass 31, count 0 2006.260.08:10:40.65#ibcon#about to read 5, iclass 31, count 0 2006.260.08:10:40.65#ibcon#read 5, iclass 31, count 0 2006.260.08:10:40.65#ibcon#about to read 6, iclass 31, count 0 2006.260.08:10:40.65#ibcon#read 6, iclass 31, count 0 2006.260.08:10:40.65#ibcon#end of sib2, iclass 31, count 0 2006.260.08:10:40.65#ibcon#*after write, iclass 31, count 0 2006.260.08:10:40.65#ibcon#*before return 0, iclass 31, count 0 2006.260.08:10:40.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:10:40.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:10:40.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:10:40.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:10:40.65$vc4f8/va=7,6 2006.260.08:10:40.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.08:10:40.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.08:10:40.65#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:40.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:10:40.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:10:40.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:10:40.71#ibcon#enter wrdev, iclass 33, count 2 2006.260.08:10:40.71#ibcon#first serial, iclass 33, count 2 2006.260.08:10:40.71#ibcon#enter sib2, iclass 33, count 2 2006.260.08:10:40.71#ibcon#flushed, iclass 33, count 2 2006.260.08:10:40.71#ibcon#about to write, iclass 33, count 2 2006.260.08:10:40.71#ibcon#wrote, iclass 33, count 2 2006.260.08:10:40.71#ibcon#about to read 3, iclass 33, count 2 2006.260.08:10:40.73#ibcon#read 3, iclass 33, count 2 2006.260.08:10:40.73#ibcon#about to read 4, iclass 33, count 2 2006.260.08:10:40.73#ibcon#read 4, iclass 33, count 2 2006.260.08:10:40.73#ibcon#about to read 5, iclass 33, count 2 2006.260.08:10:40.73#ibcon#read 5, iclass 33, count 2 2006.260.08:10:40.73#ibcon#about to read 6, iclass 33, count 2 2006.260.08:10:40.73#ibcon#read 6, iclass 33, count 2 2006.260.08:10:40.73#ibcon#end of sib2, iclass 33, count 2 2006.260.08:10:40.73#ibcon#*mode == 0, iclass 33, count 2 2006.260.08:10:40.73#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.08:10:40.73#ibcon#[25=AT07-06\r\n] 2006.260.08:10:40.73#ibcon#*before write, iclass 33, count 2 2006.260.08:10:40.73#ibcon#enter sib2, iclass 33, count 2 2006.260.08:10:40.73#ibcon#flushed, iclass 33, count 2 2006.260.08:10:40.73#ibcon#about to write, iclass 33, count 2 2006.260.08:10:40.73#ibcon#wrote, iclass 33, count 2 2006.260.08:10:40.73#ibcon#about to read 3, iclass 33, count 2 2006.260.08:10:40.76#ibcon#read 3, iclass 33, count 2 2006.260.08:10:40.76#ibcon#about to read 4, iclass 33, count 2 2006.260.08:10:40.76#ibcon#read 4, iclass 33, count 2 2006.260.08:10:40.76#ibcon#about to read 5, iclass 33, count 2 2006.260.08:10:40.76#ibcon#read 5, iclass 33, count 2 2006.260.08:10:40.76#ibcon#about to read 6, iclass 33, count 2 2006.260.08:10:40.76#ibcon#read 6, iclass 33, count 2 2006.260.08:10:40.76#ibcon#end of sib2, iclass 33, count 2 2006.260.08:10:40.76#ibcon#*after write, iclass 33, count 2 2006.260.08:10:40.76#ibcon#*before return 0, iclass 33, count 2 2006.260.08:10:40.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:10:40.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:10:40.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.08:10:40.76#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:40.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:10:40.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:10:40.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:10:40.88#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:10:40.88#ibcon#first serial, iclass 33, count 0 2006.260.08:10:40.88#ibcon#enter sib2, iclass 33, count 0 2006.260.08:10:40.88#ibcon#flushed, iclass 33, count 0 2006.260.08:10:40.88#ibcon#about to write, iclass 33, count 0 2006.260.08:10:40.88#ibcon#wrote, iclass 33, count 0 2006.260.08:10:40.88#ibcon#about to read 3, iclass 33, count 0 2006.260.08:10:40.90#ibcon#read 3, iclass 33, count 0 2006.260.08:10:40.90#ibcon#about to read 4, iclass 33, count 0 2006.260.08:10:40.90#ibcon#read 4, iclass 33, count 0 2006.260.08:10:40.90#ibcon#about to read 5, iclass 33, count 0 2006.260.08:10:40.90#ibcon#read 5, iclass 33, count 0 2006.260.08:10:40.90#ibcon#about to read 6, iclass 33, count 0 2006.260.08:10:40.90#ibcon#read 6, iclass 33, count 0 2006.260.08:10:40.90#ibcon#end of sib2, iclass 33, count 0 2006.260.08:10:40.90#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:10:40.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:10:40.90#ibcon#[25=USB\r\n] 2006.260.08:10:40.90#ibcon#*before write, iclass 33, count 0 2006.260.08:10:40.90#ibcon#enter sib2, iclass 33, count 0 2006.260.08:10:40.90#ibcon#flushed, iclass 33, count 0 2006.260.08:10:40.90#ibcon#about to write, iclass 33, count 0 2006.260.08:10:40.90#ibcon#wrote, iclass 33, count 0 2006.260.08:10:40.90#ibcon#about to read 3, iclass 33, count 0 2006.260.08:10:40.93#ibcon#read 3, iclass 33, count 0 2006.260.08:10:40.93#ibcon#about to read 4, iclass 33, count 0 2006.260.08:10:40.93#ibcon#read 4, iclass 33, count 0 2006.260.08:10:40.93#ibcon#about to read 5, iclass 33, count 0 2006.260.08:10:40.93#ibcon#read 5, iclass 33, count 0 2006.260.08:10:40.93#ibcon#about to read 6, iclass 33, count 0 2006.260.08:10:40.93#ibcon#read 6, iclass 33, count 0 2006.260.08:10:40.93#ibcon#end of sib2, iclass 33, count 0 2006.260.08:10:40.93#ibcon#*after write, iclass 33, count 0 2006.260.08:10:40.93#ibcon#*before return 0, iclass 33, count 0 2006.260.08:10:40.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:10:40.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:10:40.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:10:40.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:10:40.93$vc4f8/valo=8,852.99 2006.260.08:10:40.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.08:10:40.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.08:10:40.93#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:40.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:10:40.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:10:40.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:10:40.93#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:10:40.93#ibcon#first serial, iclass 35, count 0 2006.260.08:10:40.93#ibcon#enter sib2, iclass 35, count 0 2006.260.08:10:40.93#ibcon#flushed, iclass 35, count 0 2006.260.08:10:40.93#ibcon#about to write, iclass 35, count 0 2006.260.08:10:40.93#ibcon#wrote, iclass 35, count 0 2006.260.08:10:40.93#ibcon#about to read 3, iclass 35, count 0 2006.260.08:10:40.95#ibcon#read 3, iclass 35, count 0 2006.260.08:10:40.95#ibcon#about to read 4, iclass 35, count 0 2006.260.08:10:40.95#ibcon#read 4, iclass 35, count 0 2006.260.08:10:40.95#ibcon#about to read 5, iclass 35, count 0 2006.260.08:10:40.95#ibcon#read 5, iclass 35, count 0 2006.260.08:10:40.95#ibcon#about to read 6, iclass 35, count 0 2006.260.08:10:40.95#ibcon#read 6, iclass 35, count 0 2006.260.08:10:40.95#ibcon#end of sib2, iclass 35, count 0 2006.260.08:10:40.95#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:10:40.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:10:40.95#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:10:40.95#ibcon#*before write, iclass 35, count 0 2006.260.08:10:40.95#ibcon#enter sib2, iclass 35, count 0 2006.260.08:10:40.95#ibcon#flushed, iclass 35, count 0 2006.260.08:10:40.95#ibcon#about to write, iclass 35, count 0 2006.260.08:10:40.95#ibcon#wrote, iclass 35, count 0 2006.260.08:10:40.95#ibcon#about to read 3, iclass 35, count 0 2006.260.08:10:40.99#ibcon#read 3, iclass 35, count 0 2006.260.08:10:40.99#ibcon#about to read 4, iclass 35, count 0 2006.260.08:10:40.99#ibcon#read 4, iclass 35, count 0 2006.260.08:10:40.99#ibcon#about to read 5, iclass 35, count 0 2006.260.08:10:40.99#ibcon#read 5, iclass 35, count 0 2006.260.08:10:40.99#ibcon#about to read 6, iclass 35, count 0 2006.260.08:10:40.99#ibcon#read 6, iclass 35, count 0 2006.260.08:10:40.99#ibcon#end of sib2, iclass 35, count 0 2006.260.08:10:40.99#ibcon#*after write, iclass 35, count 0 2006.260.08:10:40.99#ibcon#*before return 0, iclass 35, count 0 2006.260.08:10:40.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:10:40.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:10:40.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:10:40.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:10:40.99$vc4f8/va=8,6 2006.260.08:10:40.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.08:10:40.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.08:10:40.99#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:40.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:10:41.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:10:41.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:10:41.05#ibcon#enter wrdev, iclass 37, count 2 2006.260.08:10:41.05#ibcon#first serial, iclass 37, count 2 2006.260.08:10:41.05#ibcon#enter sib2, iclass 37, count 2 2006.260.08:10:41.05#ibcon#flushed, iclass 37, count 2 2006.260.08:10:41.05#ibcon#about to write, iclass 37, count 2 2006.260.08:10:41.05#ibcon#wrote, iclass 37, count 2 2006.260.08:10:41.05#ibcon#about to read 3, iclass 37, count 2 2006.260.08:10:41.07#ibcon#read 3, iclass 37, count 2 2006.260.08:10:41.07#ibcon#about to read 4, iclass 37, count 2 2006.260.08:10:41.07#ibcon#read 4, iclass 37, count 2 2006.260.08:10:41.07#ibcon#about to read 5, iclass 37, count 2 2006.260.08:10:41.07#ibcon#read 5, iclass 37, count 2 2006.260.08:10:41.07#ibcon#about to read 6, iclass 37, count 2 2006.260.08:10:41.07#ibcon#read 6, iclass 37, count 2 2006.260.08:10:41.07#ibcon#end of sib2, iclass 37, count 2 2006.260.08:10:41.07#ibcon#*mode == 0, iclass 37, count 2 2006.260.08:10:41.07#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.08:10:41.07#ibcon#[25=AT08-06\r\n] 2006.260.08:10:41.07#ibcon#*before write, iclass 37, count 2 2006.260.08:10:41.07#ibcon#enter sib2, iclass 37, count 2 2006.260.08:10:41.07#ibcon#flushed, iclass 37, count 2 2006.260.08:10:41.07#ibcon#about to write, iclass 37, count 2 2006.260.08:10:41.07#ibcon#wrote, iclass 37, count 2 2006.260.08:10:41.07#ibcon#about to read 3, iclass 37, count 2 2006.260.08:10:41.10#ibcon#read 3, iclass 37, count 2 2006.260.08:10:41.10#ibcon#about to read 4, iclass 37, count 2 2006.260.08:10:41.10#ibcon#read 4, iclass 37, count 2 2006.260.08:10:41.10#ibcon#about to read 5, iclass 37, count 2 2006.260.08:10:41.10#ibcon#read 5, iclass 37, count 2 2006.260.08:10:41.10#ibcon#about to read 6, iclass 37, count 2 2006.260.08:10:41.10#ibcon#read 6, iclass 37, count 2 2006.260.08:10:41.10#ibcon#end of sib2, iclass 37, count 2 2006.260.08:10:41.10#ibcon#*after write, iclass 37, count 2 2006.260.08:10:41.10#ibcon#*before return 0, iclass 37, count 2 2006.260.08:10:41.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:10:41.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:10:41.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.08:10:41.10#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:41.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:10:41.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:10:41.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:10:41.22#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:10:41.22#ibcon#first serial, iclass 37, count 0 2006.260.08:10:41.22#ibcon#enter sib2, iclass 37, count 0 2006.260.08:10:41.22#ibcon#flushed, iclass 37, count 0 2006.260.08:10:41.22#ibcon#about to write, iclass 37, count 0 2006.260.08:10:41.22#ibcon#wrote, iclass 37, count 0 2006.260.08:10:41.22#ibcon#about to read 3, iclass 37, count 0 2006.260.08:10:41.24#ibcon#read 3, iclass 37, count 0 2006.260.08:10:41.24#ibcon#about to read 4, iclass 37, count 0 2006.260.08:10:41.24#ibcon#read 4, iclass 37, count 0 2006.260.08:10:41.24#ibcon#about to read 5, iclass 37, count 0 2006.260.08:10:41.24#ibcon#read 5, iclass 37, count 0 2006.260.08:10:41.24#ibcon#about to read 6, iclass 37, count 0 2006.260.08:10:41.24#ibcon#read 6, iclass 37, count 0 2006.260.08:10:41.24#ibcon#end of sib2, iclass 37, count 0 2006.260.08:10:41.24#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:10:41.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:10:41.24#ibcon#[25=USB\r\n] 2006.260.08:10:41.24#ibcon#*before write, iclass 37, count 0 2006.260.08:10:41.24#ibcon#enter sib2, iclass 37, count 0 2006.260.08:10:41.24#ibcon#flushed, iclass 37, count 0 2006.260.08:10:41.24#ibcon#about to write, iclass 37, count 0 2006.260.08:10:41.24#ibcon#wrote, iclass 37, count 0 2006.260.08:10:41.24#ibcon#about to read 3, iclass 37, count 0 2006.260.08:10:41.27#ibcon#read 3, iclass 37, count 0 2006.260.08:10:41.27#ibcon#about to read 4, iclass 37, count 0 2006.260.08:10:41.27#ibcon#read 4, iclass 37, count 0 2006.260.08:10:41.27#ibcon#about to read 5, iclass 37, count 0 2006.260.08:10:41.27#ibcon#read 5, iclass 37, count 0 2006.260.08:10:41.27#ibcon#about to read 6, iclass 37, count 0 2006.260.08:10:41.27#ibcon#read 6, iclass 37, count 0 2006.260.08:10:41.27#ibcon#end of sib2, iclass 37, count 0 2006.260.08:10:41.27#ibcon#*after write, iclass 37, count 0 2006.260.08:10:41.27#ibcon#*before return 0, iclass 37, count 0 2006.260.08:10:41.27#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:10:41.27#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:10:41.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:10:41.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:10:41.27$vc4f8/vblo=1,632.99 2006.260.08:10:41.27#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.08:10:41.27#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.08:10:41.27#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:41.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:10:41.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:10:41.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:10:41.27#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:10:41.27#ibcon#first serial, iclass 39, count 0 2006.260.08:10:41.27#ibcon#enter sib2, iclass 39, count 0 2006.260.08:10:41.27#ibcon#flushed, iclass 39, count 0 2006.260.08:10:41.27#ibcon#about to write, iclass 39, count 0 2006.260.08:10:41.27#ibcon#wrote, iclass 39, count 0 2006.260.08:10:41.27#ibcon#about to read 3, iclass 39, count 0 2006.260.08:10:41.29#ibcon#read 3, iclass 39, count 0 2006.260.08:10:41.29#ibcon#about to read 4, iclass 39, count 0 2006.260.08:10:41.29#ibcon#read 4, iclass 39, count 0 2006.260.08:10:41.29#ibcon#about to read 5, iclass 39, count 0 2006.260.08:10:41.29#ibcon#read 5, iclass 39, count 0 2006.260.08:10:41.29#ibcon#about to read 6, iclass 39, count 0 2006.260.08:10:41.29#ibcon#read 6, iclass 39, count 0 2006.260.08:10:41.29#ibcon#end of sib2, iclass 39, count 0 2006.260.08:10:41.29#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:10:41.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:10:41.29#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:10:41.29#ibcon#*before write, iclass 39, count 0 2006.260.08:10:41.29#ibcon#enter sib2, iclass 39, count 0 2006.260.08:10:41.29#ibcon#flushed, iclass 39, count 0 2006.260.08:10:41.29#ibcon#about to write, iclass 39, count 0 2006.260.08:10:41.29#ibcon#wrote, iclass 39, count 0 2006.260.08:10:41.29#ibcon#about to read 3, iclass 39, count 0 2006.260.08:10:41.33#ibcon#read 3, iclass 39, count 0 2006.260.08:10:41.33#ibcon#about to read 4, iclass 39, count 0 2006.260.08:10:41.33#ibcon#read 4, iclass 39, count 0 2006.260.08:10:41.33#ibcon#about to read 5, iclass 39, count 0 2006.260.08:10:41.33#ibcon#read 5, iclass 39, count 0 2006.260.08:10:41.33#ibcon#about to read 6, iclass 39, count 0 2006.260.08:10:41.33#ibcon#read 6, iclass 39, count 0 2006.260.08:10:41.33#ibcon#end of sib2, iclass 39, count 0 2006.260.08:10:41.33#ibcon#*after write, iclass 39, count 0 2006.260.08:10:41.33#ibcon#*before return 0, iclass 39, count 0 2006.260.08:10:41.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:10:41.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:10:41.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:10:41.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:10:41.33$vc4f8/vb=1,4 2006.260.08:10:41.33#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.08:10:41.33#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.08:10:41.33#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:41.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:10:41.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:10:41.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:10:41.33#ibcon#enter wrdev, iclass 3, count 2 2006.260.08:10:41.33#ibcon#first serial, iclass 3, count 2 2006.260.08:10:41.33#ibcon#enter sib2, iclass 3, count 2 2006.260.08:10:41.33#ibcon#flushed, iclass 3, count 2 2006.260.08:10:41.33#ibcon#about to write, iclass 3, count 2 2006.260.08:10:41.33#ibcon#wrote, iclass 3, count 2 2006.260.08:10:41.33#ibcon#about to read 3, iclass 3, count 2 2006.260.08:10:41.35#ibcon#read 3, iclass 3, count 2 2006.260.08:10:41.35#ibcon#about to read 4, iclass 3, count 2 2006.260.08:10:41.35#ibcon#read 4, iclass 3, count 2 2006.260.08:10:41.35#ibcon#about to read 5, iclass 3, count 2 2006.260.08:10:41.35#ibcon#read 5, iclass 3, count 2 2006.260.08:10:41.35#ibcon#about to read 6, iclass 3, count 2 2006.260.08:10:41.35#ibcon#read 6, iclass 3, count 2 2006.260.08:10:41.35#ibcon#end of sib2, iclass 3, count 2 2006.260.08:10:41.35#ibcon#*mode == 0, iclass 3, count 2 2006.260.08:10:41.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.08:10:41.35#ibcon#[27=AT01-04\r\n] 2006.260.08:10:41.35#ibcon#*before write, iclass 3, count 2 2006.260.08:10:41.35#ibcon#enter sib2, iclass 3, count 2 2006.260.08:10:41.35#ibcon#flushed, iclass 3, count 2 2006.260.08:10:41.35#ibcon#about to write, iclass 3, count 2 2006.260.08:10:41.35#ibcon#wrote, iclass 3, count 2 2006.260.08:10:41.35#ibcon#about to read 3, iclass 3, count 2 2006.260.08:10:41.38#ibcon#read 3, iclass 3, count 2 2006.260.08:10:41.38#ibcon#about to read 4, iclass 3, count 2 2006.260.08:10:41.38#ibcon#read 4, iclass 3, count 2 2006.260.08:10:41.38#ibcon#about to read 5, iclass 3, count 2 2006.260.08:10:41.38#ibcon#read 5, iclass 3, count 2 2006.260.08:10:41.38#ibcon#about to read 6, iclass 3, count 2 2006.260.08:10:41.38#ibcon#read 6, iclass 3, count 2 2006.260.08:10:41.38#ibcon#end of sib2, iclass 3, count 2 2006.260.08:10:41.38#ibcon#*after write, iclass 3, count 2 2006.260.08:10:41.38#ibcon#*before return 0, iclass 3, count 2 2006.260.08:10:41.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:10:41.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:10:41.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.08:10:41.38#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:41.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:10:41.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:10:41.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:10:41.50#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:10:41.50#ibcon#first serial, iclass 3, count 0 2006.260.08:10:41.50#ibcon#enter sib2, iclass 3, count 0 2006.260.08:10:41.50#ibcon#flushed, iclass 3, count 0 2006.260.08:10:41.50#ibcon#about to write, iclass 3, count 0 2006.260.08:10:41.50#ibcon#wrote, iclass 3, count 0 2006.260.08:10:41.50#ibcon#about to read 3, iclass 3, count 0 2006.260.08:10:41.52#ibcon#read 3, iclass 3, count 0 2006.260.08:10:41.52#ibcon#about to read 4, iclass 3, count 0 2006.260.08:10:41.52#ibcon#read 4, iclass 3, count 0 2006.260.08:10:41.52#ibcon#about to read 5, iclass 3, count 0 2006.260.08:10:41.52#ibcon#read 5, iclass 3, count 0 2006.260.08:10:41.52#ibcon#about to read 6, iclass 3, count 0 2006.260.08:10:41.52#ibcon#read 6, iclass 3, count 0 2006.260.08:10:41.52#ibcon#end of sib2, iclass 3, count 0 2006.260.08:10:41.52#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:10:41.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:10:41.52#ibcon#[27=USB\r\n] 2006.260.08:10:41.52#ibcon#*before write, iclass 3, count 0 2006.260.08:10:41.52#ibcon#enter sib2, iclass 3, count 0 2006.260.08:10:41.52#ibcon#flushed, iclass 3, count 0 2006.260.08:10:41.52#ibcon#about to write, iclass 3, count 0 2006.260.08:10:41.52#ibcon#wrote, iclass 3, count 0 2006.260.08:10:41.52#ibcon#about to read 3, iclass 3, count 0 2006.260.08:10:41.55#ibcon#read 3, iclass 3, count 0 2006.260.08:10:41.55#ibcon#about to read 4, iclass 3, count 0 2006.260.08:10:41.55#ibcon#read 4, iclass 3, count 0 2006.260.08:10:41.55#ibcon#about to read 5, iclass 3, count 0 2006.260.08:10:41.55#ibcon#read 5, iclass 3, count 0 2006.260.08:10:41.55#ibcon#about to read 6, iclass 3, count 0 2006.260.08:10:41.55#ibcon#read 6, iclass 3, count 0 2006.260.08:10:41.55#ibcon#end of sib2, iclass 3, count 0 2006.260.08:10:41.55#ibcon#*after write, iclass 3, count 0 2006.260.08:10:41.55#ibcon#*before return 0, iclass 3, count 0 2006.260.08:10:41.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:10:41.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:10:41.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:10:41.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:10:41.55$vc4f8/vblo=2,640.99 2006.260.08:10:41.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:10:41.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:10:41.55#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:41.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:41.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:41.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:41.55#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:10:41.55#ibcon#first serial, iclass 5, count 0 2006.260.08:10:41.55#ibcon#enter sib2, iclass 5, count 0 2006.260.08:10:41.55#ibcon#flushed, iclass 5, count 0 2006.260.08:10:41.55#ibcon#about to write, iclass 5, count 0 2006.260.08:10:41.55#ibcon#wrote, iclass 5, count 0 2006.260.08:10:41.55#ibcon#about to read 3, iclass 5, count 0 2006.260.08:10:41.57#ibcon#read 3, iclass 5, count 0 2006.260.08:10:41.57#ibcon#about to read 4, iclass 5, count 0 2006.260.08:10:41.57#ibcon#read 4, iclass 5, count 0 2006.260.08:10:41.57#ibcon#about to read 5, iclass 5, count 0 2006.260.08:10:41.57#ibcon#read 5, iclass 5, count 0 2006.260.08:10:41.57#ibcon#about to read 6, iclass 5, count 0 2006.260.08:10:41.57#ibcon#read 6, iclass 5, count 0 2006.260.08:10:41.57#ibcon#end of sib2, iclass 5, count 0 2006.260.08:10:41.57#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:10:41.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:10:41.57#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:10:41.57#ibcon#*before write, iclass 5, count 0 2006.260.08:10:41.57#ibcon#enter sib2, iclass 5, count 0 2006.260.08:10:41.57#ibcon#flushed, iclass 5, count 0 2006.260.08:10:41.57#ibcon#about to write, iclass 5, count 0 2006.260.08:10:41.57#ibcon#wrote, iclass 5, count 0 2006.260.08:10:41.57#ibcon#about to read 3, iclass 5, count 0 2006.260.08:10:41.61#ibcon#read 3, iclass 5, count 0 2006.260.08:10:41.61#ibcon#about to read 4, iclass 5, count 0 2006.260.08:10:41.61#ibcon#read 4, iclass 5, count 0 2006.260.08:10:41.61#ibcon#about to read 5, iclass 5, count 0 2006.260.08:10:41.61#ibcon#read 5, iclass 5, count 0 2006.260.08:10:41.61#ibcon#about to read 6, iclass 5, count 0 2006.260.08:10:41.61#ibcon#read 6, iclass 5, count 0 2006.260.08:10:41.61#ibcon#end of sib2, iclass 5, count 0 2006.260.08:10:41.61#ibcon#*after write, iclass 5, count 0 2006.260.08:10:41.61#ibcon#*before return 0, iclass 5, count 0 2006.260.08:10:41.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:41.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:10:41.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:10:41.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:10:41.61$vc4f8/vb=2,5 2006.260.08:10:41.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:10:41.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:10:41.61#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:41.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:41.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:41.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:41.67#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:10:41.67#ibcon#first serial, iclass 7, count 2 2006.260.08:10:41.67#ibcon#enter sib2, iclass 7, count 2 2006.260.08:10:41.67#ibcon#flushed, iclass 7, count 2 2006.260.08:10:41.67#ibcon#about to write, iclass 7, count 2 2006.260.08:10:41.67#ibcon#wrote, iclass 7, count 2 2006.260.08:10:41.67#ibcon#about to read 3, iclass 7, count 2 2006.260.08:10:41.69#ibcon#read 3, iclass 7, count 2 2006.260.08:10:41.69#ibcon#about to read 4, iclass 7, count 2 2006.260.08:10:41.69#ibcon#read 4, iclass 7, count 2 2006.260.08:10:41.69#ibcon#about to read 5, iclass 7, count 2 2006.260.08:10:41.69#ibcon#read 5, iclass 7, count 2 2006.260.08:10:41.69#ibcon#about to read 6, iclass 7, count 2 2006.260.08:10:41.69#ibcon#read 6, iclass 7, count 2 2006.260.08:10:41.69#ibcon#end of sib2, iclass 7, count 2 2006.260.08:10:41.69#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:10:41.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:10:41.69#ibcon#[27=AT02-05\r\n] 2006.260.08:10:41.69#ibcon#*before write, iclass 7, count 2 2006.260.08:10:41.69#ibcon#enter sib2, iclass 7, count 2 2006.260.08:10:41.69#ibcon#flushed, iclass 7, count 2 2006.260.08:10:41.69#ibcon#about to write, iclass 7, count 2 2006.260.08:10:41.69#ibcon#wrote, iclass 7, count 2 2006.260.08:10:41.69#ibcon#about to read 3, iclass 7, count 2 2006.260.08:10:41.72#ibcon#read 3, iclass 7, count 2 2006.260.08:10:41.72#ibcon#about to read 4, iclass 7, count 2 2006.260.08:10:41.72#ibcon#read 4, iclass 7, count 2 2006.260.08:10:41.72#ibcon#about to read 5, iclass 7, count 2 2006.260.08:10:41.72#ibcon#read 5, iclass 7, count 2 2006.260.08:10:41.72#ibcon#about to read 6, iclass 7, count 2 2006.260.08:10:41.72#ibcon#read 6, iclass 7, count 2 2006.260.08:10:41.72#ibcon#end of sib2, iclass 7, count 2 2006.260.08:10:41.72#ibcon#*after write, iclass 7, count 2 2006.260.08:10:41.72#ibcon#*before return 0, iclass 7, count 2 2006.260.08:10:41.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:41.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:10:41.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:10:41.72#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:41.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:41.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:41.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:41.84#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:10:41.84#ibcon#first serial, iclass 7, count 0 2006.260.08:10:41.84#ibcon#enter sib2, iclass 7, count 0 2006.260.08:10:41.84#ibcon#flushed, iclass 7, count 0 2006.260.08:10:41.84#ibcon#about to write, iclass 7, count 0 2006.260.08:10:41.84#ibcon#wrote, iclass 7, count 0 2006.260.08:10:41.84#ibcon#about to read 3, iclass 7, count 0 2006.260.08:10:41.86#ibcon#read 3, iclass 7, count 0 2006.260.08:10:41.86#ibcon#about to read 4, iclass 7, count 0 2006.260.08:10:41.86#ibcon#read 4, iclass 7, count 0 2006.260.08:10:41.86#ibcon#about to read 5, iclass 7, count 0 2006.260.08:10:41.86#ibcon#read 5, iclass 7, count 0 2006.260.08:10:41.86#ibcon#about to read 6, iclass 7, count 0 2006.260.08:10:41.86#ibcon#read 6, iclass 7, count 0 2006.260.08:10:41.86#ibcon#end of sib2, iclass 7, count 0 2006.260.08:10:41.86#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:10:41.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:10:41.86#ibcon#[27=USB\r\n] 2006.260.08:10:41.86#ibcon#*before write, iclass 7, count 0 2006.260.08:10:41.86#ibcon#enter sib2, iclass 7, count 0 2006.260.08:10:41.86#ibcon#flushed, iclass 7, count 0 2006.260.08:10:41.86#ibcon#about to write, iclass 7, count 0 2006.260.08:10:41.86#ibcon#wrote, iclass 7, count 0 2006.260.08:10:41.86#ibcon#about to read 3, iclass 7, count 0 2006.260.08:10:41.89#ibcon#read 3, iclass 7, count 0 2006.260.08:10:41.89#ibcon#about to read 4, iclass 7, count 0 2006.260.08:10:41.89#ibcon#read 4, iclass 7, count 0 2006.260.08:10:41.89#ibcon#about to read 5, iclass 7, count 0 2006.260.08:10:41.89#ibcon#read 5, iclass 7, count 0 2006.260.08:10:41.89#ibcon#about to read 6, iclass 7, count 0 2006.260.08:10:41.89#ibcon#read 6, iclass 7, count 0 2006.260.08:10:41.89#ibcon#end of sib2, iclass 7, count 0 2006.260.08:10:41.89#ibcon#*after write, iclass 7, count 0 2006.260.08:10:41.89#ibcon#*before return 0, iclass 7, count 0 2006.260.08:10:41.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:41.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:10:41.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:10:41.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:10:41.89$vc4f8/vblo=3,656.99 2006.260.08:10:41.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:10:41.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:10:41.89#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:41.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:41.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:41.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:41.89#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:10:41.89#ibcon#first serial, iclass 11, count 0 2006.260.08:10:41.89#ibcon#enter sib2, iclass 11, count 0 2006.260.08:10:41.89#ibcon#flushed, iclass 11, count 0 2006.260.08:10:41.89#ibcon#about to write, iclass 11, count 0 2006.260.08:10:41.89#ibcon#wrote, iclass 11, count 0 2006.260.08:10:41.89#ibcon#about to read 3, iclass 11, count 0 2006.260.08:10:41.91#ibcon#read 3, iclass 11, count 0 2006.260.08:10:41.91#ibcon#about to read 4, iclass 11, count 0 2006.260.08:10:41.91#ibcon#read 4, iclass 11, count 0 2006.260.08:10:41.91#ibcon#about to read 5, iclass 11, count 0 2006.260.08:10:41.91#ibcon#read 5, iclass 11, count 0 2006.260.08:10:41.91#ibcon#about to read 6, iclass 11, count 0 2006.260.08:10:41.91#ibcon#read 6, iclass 11, count 0 2006.260.08:10:41.91#ibcon#end of sib2, iclass 11, count 0 2006.260.08:10:41.91#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:10:41.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:10:41.91#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:10:41.91#ibcon#*before write, iclass 11, count 0 2006.260.08:10:41.91#ibcon#enter sib2, iclass 11, count 0 2006.260.08:10:41.91#ibcon#flushed, iclass 11, count 0 2006.260.08:10:41.91#ibcon#about to write, iclass 11, count 0 2006.260.08:10:41.91#ibcon#wrote, iclass 11, count 0 2006.260.08:10:41.91#ibcon#about to read 3, iclass 11, count 0 2006.260.08:10:41.95#ibcon#read 3, iclass 11, count 0 2006.260.08:10:41.95#ibcon#about to read 4, iclass 11, count 0 2006.260.08:10:41.95#ibcon#read 4, iclass 11, count 0 2006.260.08:10:41.95#ibcon#about to read 5, iclass 11, count 0 2006.260.08:10:41.95#ibcon#read 5, iclass 11, count 0 2006.260.08:10:41.95#ibcon#about to read 6, iclass 11, count 0 2006.260.08:10:41.95#ibcon#read 6, iclass 11, count 0 2006.260.08:10:41.95#ibcon#end of sib2, iclass 11, count 0 2006.260.08:10:41.95#ibcon#*after write, iclass 11, count 0 2006.260.08:10:41.95#ibcon#*before return 0, iclass 11, count 0 2006.260.08:10:41.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:41.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:10:41.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:10:41.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:10:41.95$vc4f8/vb=3,4 2006.260.08:10:41.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.08:10:41.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.08:10:41.95#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:41.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:42.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:42.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:42.01#ibcon#enter wrdev, iclass 13, count 2 2006.260.08:10:42.01#ibcon#first serial, iclass 13, count 2 2006.260.08:10:42.01#ibcon#enter sib2, iclass 13, count 2 2006.260.08:10:42.01#ibcon#flushed, iclass 13, count 2 2006.260.08:10:42.01#ibcon#about to write, iclass 13, count 2 2006.260.08:10:42.01#ibcon#wrote, iclass 13, count 2 2006.260.08:10:42.01#ibcon#about to read 3, iclass 13, count 2 2006.260.08:10:42.03#ibcon#read 3, iclass 13, count 2 2006.260.08:10:42.03#ibcon#about to read 4, iclass 13, count 2 2006.260.08:10:42.03#ibcon#read 4, iclass 13, count 2 2006.260.08:10:42.03#ibcon#about to read 5, iclass 13, count 2 2006.260.08:10:42.03#ibcon#read 5, iclass 13, count 2 2006.260.08:10:42.03#ibcon#about to read 6, iclass 13, count 2 2006.260.08:10:42.03#ibcon#read 6, iclass 13, count 2 2006.260.08:10:42.03#ibcon#end of sib2, iclass 13, count 2 2006.260.08:10:42.03#ibcon#*mode == 0, iclass 13, count 2 2006.260.08:10:42.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.08:10:42.03#ibcon#[27=AT03-04\r\n] 2006.260.08:10:42.03#ibcon#*before write, iclass 13, count 2 2006.260.08:10:42.03#ibcon#enter sib2, iclass 13, count 2 2006.260.08:10:42.03#ibcon#flushed, iclass 13, count 2 2006.260.08:10:42.03#ibcon#about to write, iclass 13, count 2 2006.260.08:10:42.03#ibcon#wrote, iclass 13, count 2 2006.260.08:10:42.03#ibcon#about to read 3, iclass 13, count 2 2006.260.08:10:42.06#ibcon#read 3, iclass 13, count 2 2006.260.08:10:42.06#ibcon#about to read 4, iclass 13, count 2 2006.260.08:10:42.06#ibcon#read 4, iclass 13, count 2 2006.260.08:10:42.06#ibcon#about to read 5, iclass 13, count 2 2006.260.08:10:42.06#ibcon#read 5, iclass 13, count 2 2006.260.08:10:42.06#ibcon#about to read 6, iclass 13, count 2 2006.260.08:10:42.06#ibcon#read 6, iclass 13, count 2 2006.260.08:10:42.06#ibcon#end of sib2, iclass 13, count 2 2006.260.08:10:42.06#ibcon#*after write, iclass 13, count 2 2006.260.08:10:42.06#ibcon#*before return 0, iclass 13, count 2 2006.260.08:10:42.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:42.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:10:42.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.08:10:42.06#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:42.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:42.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:42.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:42.18#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:10:42.18#ibcon#first serial, iclass 13, count 0 2006.260.08:10:42.18#ibcon#enter sib2, iclass 13, count 0 2006.260.08:10:42.18#ibcon#flushed, iclass 13, count 0 2006.260.08:10:42.18#ibcon#about to write, iclass 13, count 0 2006.260.08:10:42.18#ibcon#wrote, iclass 13, count 0 2006.260.08:10:42.18#ibcon#about to read 3, iclass 13, count 0 2006.260.08:10:42.20#ibcon#read 3, iclass 13, count 0 2006.260.08:10:42.20#ibcon#about to read 4, iclass 13, count 0 2006.260.08:10:42.20#ibcon#read 4, iclass 13, count 0 2006.260.08:10:42.20#ibcon#about to read 5, iclass 13, count 0 2006.260.08:10:42.20#ibcon#read 5, iclass 13, count 0 2006.260.08:10:42.20#ibcon#about to read 6, iclass 13, count 0 2006.260.08:10:42.20#ibcon#read 6, iclass 13, count 0 2006.260.08:10:42.20#ibcon#end of sib2, iclass 13, count 0 2006.260.08:10:42.20#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:10:42.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:10:42.20#ibcon#[27=USB\r\n] 2006.260.08:10:42.20#ibcon#*before write, iclass 13, count 0 2006.260.08:10:42.20#ibcon#enter sib2, iclass 13, count 0 2006.260.08:10:42.20#ibcon#flushed, iclass 13, count 0 2006.260.08:10:42.20#ibcon#about to write, iclass 13, count 0 2006.260.08:10:42.20#ibcon#wrote, iclass 13, count 0 2006.260.08:10:42.20#ibcon#about to read 3, iclass 13, count 0 2006.260.08:10:42.23#ibcon#read 3, iclass 13, count 0 2006.260.08:10:42.23#ibcon#about to read 4, iclass 13, count 0 2006.260.08:10:42.23#ibcon#read 4, iclass 13, count 0 2006.260.08:10:42.23#ibcon#about to read 5, iclass 13, count 0 2006.260.08:10:42.23#ibcon#read 5, iclass 13, count 0 2006.260.08:10:42.23#ibcon#about to read 6, iclass 13, count 0 2006.260.08:10:42.23#ibcon#read 6, iclass 13, count 0 2006.260.08:10:42.23#ibcon#end of sib2, iclass 13, count 0 2006.260.08:10:42.23#ibcon#*after write, iclass 13, count 0 2006.260.08:10:42.23#ibcon#*before return 0, iclass 13, count 0 2006.260.08:10:42.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:42.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:10:42.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:10:42.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:10:42.23$vc4f8/vblo=4,712.99 2006.260.08:10:42.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:10:42.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:10:42.23#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:42.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:42.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:42.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:42.23#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:10:42.23#ibcon#first serial, iclass 15, count 0 2006.260.08:10:42.23#ibcon#enter sib2, iclass 15, count 0 2006.260.08:10:42.23#ibcon#flushed, iclass 15, count 0 2006.260.08:10:42.23#ibcon#about to write, iclass 15, count 0 2006.260.08:10:42.23#ibcon#wrote, iclass 15, count 0 2006.260.08:10:42.23#ibcon#about to read 3, iclass 15, count 0 2006.260.08:10:42.25#ibcon#read 3, iclass 15, count 0 2006.260.08:10:42.25#ibcon#about to read 4, iclass 15, count 0 2006.260.08:10:42.25#ibcon#read 4, iclass 15, count 0 2006.260.08:10:42.25#ibcon#about to read 5, iclass 15, count 0 2006.260.08:10:42.25#ibcon#read 5, iclass 15, count 0 2006.260.08:10:42.25#ibcon#about to read 6, iclass 15, count 0 2006.260.08:10:42.25#ibcon#read 6, iclass 15, count 0 2006.260.08:10:42.25#ibcon#end of sib2, iclass 15, count 0 2006.260.08:10:42.25#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:10:42.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:10:42.25#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:10:42.25#ibcon#*before write, iclass 15, count 0 2006.260.08:10:42.25#ibcon#enter sib2, iclass 15, count 0 2006.260.08:10:42.25#ibcon#flushed, iclass 15, count 0 2006.260.08:10:42.25#ibcon#about to write, iclass 15, count 0 2006.260.08:10:42.25#ibcon#wrote, iclass 15, count 0 2006.260.08:10:42.25#ibcon#about to read 3, iclass 15, count 0 2006.260.08:10:42.29#ibcon#read 3, iclass 15, count 0 2006.260.08:10:42.29#ibcon#about to read 4, iclass 15, count 0 2006.260.08:10:42.29#ibcon#read 4, iclass 15, count 0 2006.260.08:10:42.29#ibcon#about to read 5, iclass 15, count 0 2006.260.08:10:42.29#ibcon#read 5, iclass 15, count 0 2006.260.08:10:42.29#ibcon#about to read 6, iclass 15, count 0 2006.260.08:10:42.29#ibcon#read 6, iclass 15, count 0 2006.260.08:10:42.29#ibcon#end of sib2, iclass 15, count 0 2006.260.08:10:42.29#ibcon#*after write, iclass 15, count 0 2006.260.08:10:42.29#ibcon#*before return 0, iclass 15, count 0 2006.260.08:10:42.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:42.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:10:42.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:10:42.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:10:42.29$vc4f8/vb=4,5 2006.260.08:10:42.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:10:42.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:10:42.29#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:42.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:42.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:42.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:42.35#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:10:42.35#ibcon#first serial, iclass 17, count 2 2006.260.08:10:42.35#ibcon#enter sib2, iclass 17, count 2 2006.260.08:10:42.35#ibcon#flushed, iclass 17, count 2 2006.260.08:10:42.35#ibcon#about to write, iclass 17, count 2 2006.260.08:10:42.35#ibcon#wrote, iclass 17, count 2 2006.260.08:10:42.35#ibcon#about to read 3, iclass 17, count 2 2006.260.08:10:42.37#ibcon#read 3, iclass 17, count 2 2006.260.08:10:42.37#ibcon#about to read 4, iclass 17, count 2 2006.260.08:10:42.37#ibcon#read 4, iclass 17, count 2 2006.260.08:10:42.37#ibcon#about to read 5, iclass 17, count 2 2006.260.08:10:42.37#ibcon#read 5, iclass 17, count 2 2006.260.08:10:42.37#ibcon#about to read 6, iclass 17, count 2 2006.260.08:10:42.37#ibcon#read 6, iclass 17, count 2 2006.260.08:10:42.37#ibcon#end of sib2, iclass 17, count 2 2006.260.08:10:42.37#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:10:42.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:10:42.37#ibcon#[27=AT04-05\r\n] 2006.260.08:10:42.37#ibcon#*before write, iclass 17, count 2 2006.260.08:10:42.37#ibcon#enter sib2, iclass 17, count 2 2006.260.08:10:42.37#ibcon#flushed, iclass 17, count 2 2006.260.08:10:42.37#ibcon#about to write, iclass 17, count 2 2006.260.08:10:42.37#ibcon#wrote, iclass 17, count 2 2006.260.08:10:42.37#ibcon#about to read 3, iclass 17, count 2 2006.260.08:10:42.40#ibcon#read 3, iclass 17, count 2 2006.260.08:10:42.40#ibcon#about to read 4, iclass 17, count 2 2006.260.08:10:42.40#ibcon#read 4, iclass 17, count 2 2006.260.08:10:42.40#ibcon#about to read 5, iclass 17, count 2 2006.260.08:10:42.40#ibcon#read 5, iclass 17, count 2 2006.260.08:10:42.40#ibcon#about to read 6, iclass 17, count 2 2006.260.08:10:42.40#ibcon#read 6, iclass 17, count 2 2006.260.08:10:42.40#ibcon#end of sib2, iclass 17, count 2 2006.260.08:10:42.40#ibcon#*after write, iclass 17, count 2 2006.260.08:10:42.40#ibcon#*before return 0, iclass 17, count 2 2006.260.08:10:42.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:42.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:10:42.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:10:42.40#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:42.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:42.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:42.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:42.52#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:10:42.52#ibcon#first serial, iclass 17, count 0 2006.260.08:10:42.52#ibcon#enter sib2, iclass 17, count 0 2006.260.08:10:42.52#ibcon#flushed, iclass 17, count 0 2006.260.08:10:42.52#ibcon#about to write, iclass 17, count 0 2006.260.08:10:42.52#ibcon#wrote, iclass 17, count 0 2006.260.08:10:42.52#ibcon#about to read 3, iclass 17, count 0 2006.260.08:10:42.54#ibcon#read 3, iclass 17, count 0 2006.260.08:10:42.54#ibcon#about to read 4, iclass 17, count 0 2006.260.08:10:42.54#ibcon#read 4, iclass 17, count 0 2006.260.08:10:42.54#ibcon#about to read 5, iclass 17, count 0 2006.260.08:10:42.54#ibcon#read 5, iclass 17, count 0 2006.260.08:10:42.54#ibcon#about to read 6, iclass 17, count 0 2006.260.08:10:42.54#ibcon#read 6, iclass 17, count 0 2006.260.08:10:42.54#ibcon#end of sib2, iclass 17, count 0 2006.260.08:10:42.54#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:10:42.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:10:42.54#ibcon#[27=USB\r\n] 2006.260.08:10:42.54#ibcon#*before write, iclass 17, count 0 2006.260.08:10:42.54#ibcon#enter sib2, iclass 17, count 0 2006.260.08:10:42.54#ibcon#flushed, iclass 17, count 0 2006.260.08:10:42.54#ibcon#about to write, iclass 17, count 0 2006.260.08:10:42.54#ibcon#wrote, iclass 17, count 0 2006.260.08:10:42.54#ibcon#about to read 3, iclass 17, count 0 2006.260.08:10:42.57#ibcon#read 3, iclass 17, count 0 2006.260.08:10:42.57#ibcon#about to read 4, iclass 17, count 0 2006.260.08:10:42.57#ibcon#read 4, iclass 17, count 0 2006.260.08:10:42.57#ibcon#about to read 5, iclass 17, count 0 2006.260.08:10:42.57#ibcon#read 5, iclass 17, count 0 2006.260.08:10:42.57#ibcon#about to read 6, iclass 17, count 0 2006.260.08:10:42.57#ibcon#read 6, iclass 17, count 0 2006.260.08:10:42.57#ibcon#end of sib2, iclass 17, count 0 2006.260.08:10:42.57#ibcon#*after write, iclass 17, count 0 2006.260.08:10:42.57#ibcon#*before return 0, iclass 17, count 0 2006.260.08:10:42.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:42.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:10:42.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:10:42.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:10:42.57$vc4f8/vblo=5,744.99 2006.260.08:10:42.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:10:42.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:10:42.57#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:42.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:42.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:42.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:42.57#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:10:42.57#ibcon#first serial, iclass 19, count 0 2006.260.08:10:42.57#ibcon#enter sib2, iclass 19, count 0 2006.260.08:10:42.57#ibcon#flushed, iclass 19, count 0 2006.260.08:10:42.57#ibcon#about to write, iclass 19, count 0 2006.260.08:10:42.57#ibcon#wrote, iclass 19, count 0 2006.260.08:10:42.57#ibcon#about to read 3, iclass 19, count 0 2006.260.08:10:42.59#ibcon#read 3, iclass 19, count 0 2006.260.08:10:42.59#ibcon#about to read 4, iclass 19, count 0 2006.260.08:10:42.59#ibcon#read 4, iclass 19, count 0 2006.260.08:10:42.59#ibcon#about to read 5, iclass 19, count 0 2006.260.08:10:42.59#ibcon#read 5, iclass 19, count 0 2006.260.08:10:42.59#ibcon#about to read 6, iclass 19, count 0 2006.260.08:10:42.59#ibcon#read 6, iclass 19, count 0 2006.260.08:10:42.59#ibcon#end of sib2, iclass 19, count 0 2006.260.08:10:42.59#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:10:42.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:10:42.59#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:10:42.59#ibcon#*before write, iclass 19, count 0 2006.260.08:10:42.59#ibcon#enter sib2, iclass 19, count 0 2006.260.08:10:42.59#ibcon#flushed, iclass 19, count 0 2006.260.08:10:42.59#ibcon#about to write, iclass 19, count 0 2006.260.08:10:42.59#ibcon#wrote, iclass 19, count 0 2006.260.08:10:42.59#ibcon#about to read 3, iclass 19, count 0 2006.260.08:10:42.63#ibcon#read 3, iclass 19, count 0 2006.260.08:10:42.63#ibcon#about to read 4, iclass 19, count 0 2006.260.08:10:42.63#ibcon#read 4, iclass 19, count 0 2006.260.08:10:42.63#ibcon#about to read 5, iclass 19, count 0 2006.260.08:10:42.63#ibcon#read 5, iclass 19, count 0 2006.260.08:10:42.63#ibcon#about to read 6, iclass 19, count 0 2006.260.08:10:42.63#ibcon#read 6, iclass 19, count 0 2006.260.08:10:42.63#ibcon#end of sib2, iclass 19, count 0 2006.260.08:10:42.63#ibcon#*after write, iclass 19, count 0 2006.260.08:10:42.63#ibcon#*before return 0, iclass 19, count 0 2006.260.08:10:42.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:42.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:10:42.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:10:42.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:10:42.63$vc4f8/vb=5,4 2006.260.08:10:42.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.08:10:42.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.08:10:42.63#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:42.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:42.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:42.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:42.69#ibcon#enter wrdev, iclass 21, count 2 2006.260.08:10:42.69#ibcon#first serial, iclass 21, count 2 2006.260.08:10:42.69#ibcon#enter sib2, iclass 21, count 2 2006.260.08:10:42.69#ibcon#flushed, iclass 21, count 2 2006.260.08:10:42.69#ibcon#about to write, iclass 21, count 2 2006.260.08:10:42.69#ibcon#wrote, iclass 21, count 2 2006.260.08:10:42.69#ibcon#about to read 3, iclass 21, count 2 2006.260.08:10:42.71#ibcon#read 3, iclass 21, count 2 2006.260.08:10:42.71#ibcon#about to read 4, iclass 21, count 2 2006.260.08:10:42.71#ibcon#read 4, iclass 21, count 2 2006.260.08:10:42.71#ibcon#about to read 5, iclass 21, count 2 2006.260.08:10:42.71#ibcon#read 5, iclass 21, count 2 2006.260.08:10:42.71#ibcon#about to read 6, iclass 21, count 2 2006.260.08:10:42.71#ibcon#read 6, iclass 21, count 2 2006.260.08:10:42.71#ibcon#end of sib2, iclass 21, count 2 2006.260.08:10:42.71#ibcon#*mode == 0, iclass 21, count 2 2006.260.08:10:42.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.08:10:42.71#ibcon#[27=AT05-04\r\n] 2006.260.08:10:42.71#ibcon#*before write, iclass 21, count 2 2006.260.08:10:42.71#ibcon#enter sib2, iclass 21, count 2 2006.260.08:10:42.71#ibcon#flushed, iclass 21, count 2 2006.260.08:10:42.71#ibcon#about to write, iclass 21, count 2 2006.260.08:10:42.71#ibcon#wrote, iclass 21, count 2 2006.260.08:10:42.71#ibcon#about to read 3, iclass 21, count 2 2006.260.08:10:42.74#ibcon#read 3, iclass 21, count 2 2006.260.08:10:42.74#ibcon#about to read 4, iclass 21, count 2 2006.260.08:10:42.74#ibcon#read 4, iclass 21, count 2 2006.260.08:10:42.74#ibcon#about to read 5, iclass 21, count 2 2006.260.08:10:42.74#ibcon#read 5, iclass 21, count 2 2006.260.08:10:42.74#ibcon#about to read 6, iclass 21, count 2 2006.260.08:10:42.74#ibcon#read 6, iclass 21, count 2 2006.260.08:10:42.74#ibcon#end of sib2, iclass 21, count 2 2006.260.08:10:42.74#ibcon#*after write, iclass 21, count 2 2006.260.08:10:42.74#ibcon#*before return 0, iclass 21, count 2 2006.260.08:10:42.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:42.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:10:42.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.08:10:42.74#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:42.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:42.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:42.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:42.86#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:10:42.86#ibcon#first serial, iclass 21, count 0 2006.260.08:10:42.86#ibcon#enter sib2, iclass 21, count 0 2006.260.08:10:42.86#ibcon#flushed, iclass 21, count 0 2006.260.08:10:42.86#ibcon#about to write, iclass 21, count 0 2006.260.08:10:42.86#ibcon#wrote, iclass 21, count 0 2006.260.08:10:42.86#ibcon#about to read 3, iclass 21, count 0 2006.260.08:10:42.88#ibcon#read 3, iclass 21, count 0 2006.260.08:10:42.88#ibcon#about to read 4, iclass 21, count 0 2006.260.08:10:42.88#ibcon#read 4, iclass 21, count 0 2006.260.08:10:42.88#ibcon#about to read 5, iclass 21, count 0 2006.260.08:10:42.88#ibcon#read 5, iclass 21, count 0 2006.260.08:10:42.88#ibcon#about to read 6, iclass 21, count 0 2006.260.08:10:42.88#ibcon#read 6, iclass 21, count 0 2006.260.08:10:42.88#ibcon#end of sib2, iclass 21, count 0 2006.260.08:10:42.88#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:10:42.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:10:42.88#ibcon#[27=USB\r\n] 2006.260.08:10:42.88#ibcon#*before write, iclass 21, count 0 2006.260.08:10:42.88#ibcon#enter sib2, iclass 21, count 0 2006.260.08:10:42.88#ibcon#flushed, iclass 21, count 0 2006.260.08:10:42.88#ibcon#about to write, iclass 21, count 0 2006.260.08:10:42.88#ibcon#wrote, iclass 21, count 0 2006.260.08:10:42.88#ibcon#about to read 3, iclass 21, count 0 2006.260.08:10:42.91#ibcon#read 3, iclass 21, count 0 2006.260.08:10:42.91#ibcon#about to read 4, iclass 21, count 0 2006.260.08:10:42.91#ibcon#read 4, iclass 21, count 0 2006.260.08:10:42.91#ibcon#about to read 5, iclass 21, count 0 2006.260.08:10:42.91#ibcon#read 5, iclass 21, count 0 2006.260.08:10:42.91#ibcon#about to read 6, iclass 21, count 0 2006.260.08:10:42.91#ibcon#read 6, iclass 21, count 0 2006.260.08:10:42.91#ibcon#end of sib2, iclass 21, count 0 2006.260.08:10:42.91#ibcon#*after write, iclass 21, count 0 2006.260.08:10:42.91#ibcon#*before return 0, iclass 21, count 0 2006.260.08:10:42.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:42.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:10:42.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:10:42.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:10:42.91$vc4f8/vblo=6,752.99 2006.260.08:10:42.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.08:10:42.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.08:10:42.91#ibcon#ireg 17 cls_cnt 0 2006.260.08:10:42.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:42.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:42.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:42.91#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:10:42.91#ibcon#first serial, iclass 23, count 0 2006.260.08:10:42.91#ibcon#enter sib2, iclass 23, count 0 2006.260.08:10:42.91#ibcon#flushed, iclass 23, count 0 2006.260.08:10:42.91#ibcon#about to write, iclass 23, count 0 2006.260.08:10:42.91#ibcon#wrote, iclass 23, count 0 2006.260.08:10:42.91#ibcon#about to read 3, iclass 23, count 0 2006.260.08:10:42.93#ibcon#read 3, iclass 23, count 0 2006.260.08:10:42.93#ibcon#about to read 4, iclass 23, count 0 2006.260.08:10:42.93#ibcon#read 4, iclass 23, count 0 2006.260.08:10:42.93#ibcon#about to read 5, iclass 23, count 0 2006.260.08:10:42.93#ibcon#read 5, iclass 23, count 0 2006.260.08:10:42.93#ibcon#about to read 6, iclass 23, count 0 2006.260.08:10:42.93#ibcon#read 6, iclass 23, count 0 2006.260.08:10:42.93#ibcon#end of sib2, iclass 23, count 0 2006.260.08:10:42.93#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:10:42.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:10:42.93#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:10:42.93#ibcon#*before write, iclass 23, count 0 2006.260.08:10:42.93#ibcon#enter sib2, iclass 23, count 0 2006.260.08:10:42.93#ibcon#flushed, iclass 23, count 0 2006.260.08:10:42.93#ibcon#about to write, iclass 23, count 0 2006.260.08:10:42.93#ibcon#wrote, iclass 23, count 0 2006.260.08:10:42.93#ibcon#about to read 3, iclass 23, count 0 2006.260.08:10:42.97#ibcon#read 3, iclass 23, count 0 2006.260.08:10:42.97#ibcon#about to read 4, iclass 23, count 0 2006.260.08:10:42.97#ibcon#read 4, iclass 23, count 0 2006.260.08:10:42.97#ibcon#about to read 5, iclass 23, count 0 2006.260.08:10:42.97#ibcon#read 5, iclass 23, count 0 2006.260.08:10:42.97#ibcon#about to read 6, iclass 23, count 0 2006.260.08:10:42.97#ibcon#read 6, iclass 23, count 0 2006.260.08:10:42.97#ibcon#end of sib2, iclass 23, count 0 2006.260.08:10:42.97#ibcon#*after write, iclass 23, count 0 2006.260.08:10:42.97#ibcon#*before return 0, iclass 23, count 0 2006.260.08:10:42.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:42.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:10:42.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:10:42.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:10:42.97$vc4f8/vb=6,4 2006.260.08:10:42.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.08:10:42.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.08:10:42.97#ibcon#ireg 11 cls_cnt 2 2006.260.08:10:42.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:43.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:43.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:43.03#ibcon#enter wrdev, iclass 25, count 2 2006.260.08:10:43.03#ibcon#first serial, iclass 25, count 2 2006.260.08:10:43.03#ibcon#enter sib2, iclass 25, count 2 2006.260.08:10:43.03#ibcon#flushed, iclass 25, count 2 2006.260.08:10:43.03#ibcon#about to write, iclass 25, count 2 2006.260.08:10:43.03#ibcon#wrote, iclass 25, count 2 2006.260.08:10:43.03#ibcon#about to read 3, iclass 25, count 2 2006.260.08:10:43.05#ibcon#read 3, iclass 25, count 2 2006.260.08:10:43.05#ibcon#about to read 4, iclass 25, count 2 2006.260.08:10:43.05#ibcon#read 4, iclass 25, count 2 2006.260.08:10:43.05#ibcon#about to read 5, iclass 25, count 2 2006.260.08:10:43.05#ibcon#read 5, iclass 25, count 2 2006.260.08:10:43.05#ibcon#about to read 6, iclass 25, count 2 2006.260.08:10:43.05#ibcon#read 6, iclass 25, count 2 2006.260.08:10:43.05#ibcon#end of sib2, iclass 25, count 2 2006.260.08:10:43.05#ibcon#*mode == 0, iclass 25, count 2 2006.260.08:10:43.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.08:10:43.05#ibcon#[27=AT06-04\r\n] 2006.260.08:10:43.05#ibcon#*before write, iclass 25, count 2 2006.260.08:10:43.05#ibcon#enter sib2, iclass 25, count 2 2006.260.08:10:43.05#ibcon#flushed, iclass 25, count 2 2006.260.08:10:43.05#ibcon#about to write, iclass 25, count 2 2006.260.08:10:43.05#ibcon#wrote, iclass 25, count 2 2006.260.08:10:43.05#ibcon#about to read 3, iclass 25, count 2 2006.260.08:10:43.08#ibcon#read 3, iclass 25, count 2 2006.260.08:10:43.08#ibcon#about to read 4, iclass 25, count 2 2006.260.08:10:43.08#ibcon#read 4, iclass 25, count 2 2006.260.08:10:43.08#ibcon#about to read 5, iclass 25, count 2 2006.260.08:10:43.08#ibcon#read 5, iclass 25, count 2 2006.260.08:10:43.08#ibcon#about to read 6, iclass 25, count 2 2006.260.08:10:43.08#ibcon#read 6, iclass 25, count 2 2006.260.08:10:43.08#ibcon#end of sib2, iclass 25, count 2 2006.260.08:10:43.08#ibcon#*after write, iclass 25, count 2 2006.260.08:10:43.08#ibcon#*before return 0, iclass 25, count 2 2006.260.08:10:43.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:43.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:10:43.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.08:10:43.08#ibcon#ireg 7 cls_cnt 0 2006.260.08:10:43.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:43.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:43.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:43.20#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:10:43.20#ibcon#first serial, iclass 25, count 0 2006.260.08:10:43.20#ibcon#enter sib2, iclass 25, count 0 2006.260.08:10:43.20#ibcon#flushed, iclass 25, count 0 2006.260.08:10:43.20#ibcon#about to write, iclass 25, count 0 2006.260.08:10:43.20#ibcon#wrote, iclass 25, count 0 2006.260.08:10:43.20#ibcon#about to read 3, iclass 25, count 0 2006.260.08:10:43.22#ibcon#read 3, iclass 25, count 0 2006.260.08:10:43.22#ibcon#about to read 4, iclass 25, count 0 2006.260.08:10:43.22#ibcon#read 4, iclass 25, count 0 2006.260.08:10:43.22#ibcon#about to read 5, iclass 25, count 0 2006.260.08:10:43.22#ibcon#read 5, iclass 25, count 0 2006.260.08:10:43.22#ibcon#about to read 6, iclass 25, count 0 2006.260.08:10:43.22#ibcon#read 6, iclass 25, count 0 2006.260.08:10:43.22#ibcon#end of sib2, iclass 25, count 0 2006.260.08:10:43.22#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:10:43.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:10:43.22#ibcon#[27=USB\r\n] 2006.260.08:10:43.22#ibcon#*before write, iclass 25, count 0 2006.260.08:10:43.22#ibcon#enter sib2, iclass 25, count 0 2006.260.08:10:43.22#ibcon#flushed, iclass 25, count 0 2006.260.08:10:43.22#ibcon#about to write, iclass 25, count 0 2006.260.08:10:43.22#ibcon#wrote, iclass 25, count 0 2006.260.08:10:43.22#ibcon#about to read 3, iclass 25, count 0 2006.260.08:10:43.25#ibcon#read 3, iclass 25, count 0 2006.260.08:10:43.25#ibcon#about to read 4, iclass 25, count 0 2006.260.08:10:43.25#ibcon#read 4, iclass 25, count 0 2006.260.08:10:43.25#ibcon#about to read 5, iclass 25, count 0 2006.260.08:10:43.25#ibcon#read 5, iclass 25, count 0 2006.260.08:10:43.25#ibcon#about to read 6, iclass 25, count 0 2006.260.08:10:43.25#ibcon#read 6, iclass 25, count 0 2006.260.08:10:43.25#ibcon#end of sib2, iclass 25, count 0 2006.260.08:10:43.25#ibcon#*after write, iclass 25, count 0 2006.260.08:10:43.25#ibcon#*before return 0, iclass 25, count 0 2006.260.08:10:43.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:43.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:10:43.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:10:43.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:10:43.25$vc4f8/vabw=wide 2006.260.08:10:43.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.08:10:43.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.08:10:43.25#ibcon#ireg 8 cls_cnt 0 2006.260.08:10:43.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:43.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:43.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:43.25#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:10:43.25#ibcon#first serial, iclass 27, count 0 2006.260.08:10:43.25#ibcon#enter sib2, iclass 27, count 0 2006.260.08:10:43.25#ibcon#flushed, iclass 27, count 0 2006.260.08:10:43.25#ibcon#about to write, iclass 27, count 0 2006.260.08:10:43.25#ibcon#wrote, iclass 27, count 0 2006.260.08:10:43.25#ibcon#about to read 3, iclass 27, count 0 2006.260.08:10:43.27#ibcon#read 3, iclass 27, count 0 2006.260.08:10:43.27#ibcon#about to read 4, iclass 27, count 0 2006.260.08:10:43.27#ibcon#read 4, iclass 27, count 0 2006.260.08:10:43.27#ibcon#about to read 5, iclass 27, count 0 2006.260.08:10:43.27#ibcon#read 5, iclass 27, count 0 2006.260.08:10:43.27#ibcon#about to read 6, iclass 27, count 0 2006.260.08:10:43.27#ibcon#read 6, iclass 27, count 0 2006.260.08:10:43.27#ibcon#end of sib2, iclass 27, count 0 2006.260.08:10:43.27#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:10:43.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:10:43.27#ibcon#[25=BW32\r\n] 2006.260.08:10:43.27#ibcon#*before write, iclass 27, count 0 2006.260.08:10:43.27#ibcon#enter sib2, iclass 27, count 0 2006.260.08:10:43.27#ibcon#flushed, iclass 27, count 0 2006.260.08:10:43.27#ibcon#about to write, iclass 27, count 0 2006.260.08:10:43.27#ibcon#wrote, iclass 27, count 0 2006.260.08:10:43.27#ibcon#about to read 3, iclass 27, count 0 2006.260.08:10:43.30#ibcon#read 3, iclass 27, count 0 2006.260.08:10:43.30#ibcon#about to read 4, iclass 27, count 0 2006.260.08:10:43.30#ibcon#read 4, iclass 27, count 0 2006.260.08:10:43.30#ibcon#about to read 5, iclass 27, count 0 2006.260.08:10:43.30#ibcon#read 5, iclass 27, count 0 2006.260.08:10:43.30#ibcon#about to read 6, iclass 27, count 0 2006.260.08:10:43.30#ibcon#read 6, iclass 27, count 0 2006.260.08:10:43.30#ibcon#end of sib2, iclass 27, count 0 2006.260.08:10:43.30#ibcon#*after write, iclass 27, count 0 2006.260.08:10:43.30#ibcon#*before return 0, iclass 27, count 0 2006.260.08:10:43.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:43.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:10:43.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:10:43.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:10:43.30$vc4f8/vbbw=wide 2006.260.08:10:43.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:10:43.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:10:43.30#ibcon#ireg 8 cls_cnt 0 2006.260.08:10:43.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:10:43.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:10:43.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:10:43.37#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:10:43.37#ibcon#first serial, iclass 29, count 0 2006.260.08:10:43.37#ibcon#enter sib2, iclass 29, count 0 2006.260.08:10:43.37#ibcon#flushed, iclass 29, count 0 2006.260.08:10:43.37#ibcon#about to write, iclass 29, count 0 2006.260.08:10:43.37#ibcon#wrote, iclass 29, count 0 2006.260.08:10:43.37#ibcon#about to read 3, iclass 29, count 0 2006.260.08:10:43.39#ibcon#read 3, iclass 29, count 0 2006.260.08:10:43.39#ibcon#about to read 4, iclass 29, count 0 2006.260.08:10:43.39#ibcon#read 4, iclass 29, count 0 2006.260.08:10:43.39#ibcon#about to read 5, iclass 29, count 0 2006.260.08:10:43.39#ibcon#read 5, iclass 29, count 0 2006.260.08:10:43.39#ibcon#about to read 6, iclass 29, count 0 2006.260.08:10:43.39#ibcon#read 6, iclass 29, count 0 2006.260.08:10:43.39#ibcon#end of sib2, iclass 29, count 0 2006.260.08:10:43.39#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:10:43.39#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:10:43.39#ibcon#[27=BW32\r\n] 2006.260.08:10:43.39#ibcon#*before write, iclass 29, count 0 2006.260.08:10:43.39#ibcon#enter sib2, iclass 29, count 0 2006.260.08:10:43.39#ibcon#flushed, iclass 29, count 0 2006.260.08:10:43.39#ibcon#about to write, iclass 29, count 0 2006.260.08:10:43.39#ibcon#wrote, iclass 29, count 0 2006.260.08:10:43.39#ibcon#about to read 3, iclass 29, count 0 2006.260.08:10:43.42#ibcon#read 3, iclass 29, count 0 2006.260.08:10:43.42#ibcon#about to read 4, iclass 29, count 0 2006.260.08:10:43.42#ibcon#read 4, iclass 29, count 0 2006.260.08:10:43.42#ibcon#about to read 5, iclass 29, count 0 2006.260.08:10:43.42#ibcon#read 5, iclass 29, count 0 2006.260.08:10:43.42#ibcon#about to read 6, iclass 29, count 0 2006.260.08:10:43.42#ibcon#read 6, iclass 29, count 0 2006.260.08:10:43.42#ibcon#end of sib2, iclass 29, count 0 2006.260.08:10:43.42#ibcon#*after write, iclass 29, count 0 2006.260.08:10:43.42#ibcon#*before return 0, iclass 29, count 0 2006.260.08:10:43.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:10:43.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:10:43.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:10:43.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:10:43.42$4f8m12a/ifd4f 2006.260.08:10:43.42$ifd4f/lo= 2006.260.08:10:43.42$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:10:43.42$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:10:43.42$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:10:43.42$ifd4f/patch= 2006.260.08:10:43.42$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:10:43.42$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:10:43.42$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:10:43.42$4f8m12a/"form=m,16.000,1:2 2006.260.08:10:43.42$4f8m12a/"tpicd 2006.260.08:10:43.42$4f8m12a/echo=off 2006.260.08:10:43.42$4f8m12a/xlog=off 2006.260.08:10:43.42:!2006.260.08:11:20 2006.260.08:11:00.14#trakl#Source acquired 2006.260.08:11:01.14#flagr#flagr/antenna,acquired 2006.260.08:11:20.00:preob 2006.260.08:11:20.14/onsource/TRACKING 2006.260.08:11:20.14:!2006.260.08:11:30 2006.260.08:11:30.00:data_valid=on 2006.260.08:11:30.00:midob 2006.260.08:11:31.14/onsource/TRACKING 2006.260.08:11:31.14/wx/22.78,1010.3,89 2006.260.08:11:31.23/cable/+6.4573E-03 2006.260.08:11:32.32/va/01,08,usb,yes,32,34 2006.260.08:11:32.32/va/02,07,usb,yes,32,34 2006.260.08:11:32.32/va/03,08,usb,yes,24,25 2006.260.08:11:32.32/va/04,07,usb,yes,33,36 2006.260.08:11:32.32/va/05,07,usb,yes,37,39 2006.260.08:11:32.32/va/06,06,usb,yes,36,36 2006.260.08:11:32.32/va/07,06,usb,yes,37,37 2006.260.08:11:32.32/va/08,06,usb,yes,39,38 2006.260.08:11:32.55/valo/01,532.99,yes,locked 2006.260.08:11:32.55/valo/02,572.99,yes,locked 2006.260.08:11:32.55/valo/03,672.99,yes,locked 2006.260.08:11:32.55/valo/04,832.99,yes,locked 2006.260.08:11:32.55/valo/05,652.99,yes,locked 2006.260.08:11:32.55/valo/06,772.99,yes,locked 2006.260.08:11:32.55/valo/07,832.99,yes,locked 2006.260.08:11:32.55/valo/08,852.99,yes,locked 2006.260.08:11:33.64/vb/01,04,usb,yes,31,29 2006.260.08:11:33.64/vb/02,05,usb,yes,29,30 2006.260.08:11:33.64/vb/03,04,usb,yes,29,33 2006.260.08:11:33.64/vb/04,05,usb,yes,26,26 2006.260.08:11:33.64/vb/05,04,usb,yes,28,32 2006.260.08:11:33.64/vb/06,04,usb,yes,29,32 2006.260.08:11:33.64/vb/07,04,usb,yes,31,31 2006.260.08:11:33.64/vb/08,04,usb,yes,29,32 2006.260.08:11:33.87/vblo/01,632.99,yes,locked 2006.260.08:11:33.87/vblo/02,640.99,yes,locked 2006.260.08:11:33.87/vblo/03,656.99,yes,locked 2006.260.08:11:33.87/vblo/04,712.99,yes,locked 2006.260.08:11:33.87/vblo/05,744.99,yes,locked 2006.260.08:11:33.87/vblo/06,752.99,yes,locked 2006.260.08:11:33.87/vblo/07,734.99,yes,locked 2006.260.08:11:33.87/vblo/08,744.99,yes,locked 2006.260.08:11:34.02/vabw/8 2006.260.08:11:34.17/vbbw/8 2006.260.08:11:34.26/xfe/off,on,15.5 2006.260.08:11:34.64/ifatt/23,28,28,28 2006.260.08:11:35.08/fmout-gps/S +4.45E-07 2006.260.08:11:35.12:!2006.260.08:12:40 2006.260.08:12:40.00:data_valid=off 2006.260.08:12:40.00:postob 2006.260.08:12:40.13/cable/+6.4598E-03 2006.260.08:12:40.13/wx/22.78,1010.3,89 2006.260.08:12:41.08/fmout-gps/S +4.45E-07 2006.260.08:12:41.08:scan_name=260-0813,k06260,60 2006.260.08:12:41.09:source=nrao512,164029.63,394646.0,2000.0,ccw 2006.260.08:12:42.14#flagr#flagr/antenna,new-source 2006.260.08:12:42.14:checkk5 2006.260.08:12:42.58/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:12:43.00/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:12:43.38/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:12:43.87/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:12:44.29/chk_obsdata//k5ts1/T2600811??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.260.08:12:44.72/chk_obsdata//k5ts2/T2600811??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.260.08:12:45.37/chk_obsdata//k5ts3/T2600811??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.260.08:12:45.77/chk_obsdata//k5ts4/T2600811??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.260.08:12:46.56/k5log//k5ts1_log_newline 2006.260.08:12:47.28/k5log//k5ts2_log_newline 2006.260.08:12:48.09/k5log//k5ts3_log_newline 2006.260.08:12:48.84/k5log//k5ts4_log_newline 2006.260.08:12:48.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:12:48.86:4f8m12a=2 2006.260.08:12:48.86$4f8m12a/echo=on 2006.260.08:12:48.86$4f8m12a/pcalon 2006.260.08:12:48.86$pcalon/"no phase cal control is implemented here 2006.260.08:12:48.86$4f8m12a/"tpicd=stop 2006.260.08:12:48.86$4f8m12a/vc4f8 2006.260.08:12:48.86$vc4f8/valo=1,532.99 2006.260.08:12:48.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:12:48.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:12:48.87#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:48.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:48.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:48.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:48.87#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:12:48.87#ibcon#first serial, iclass 12, count 0 2006.260.08:12:48.87#ibcon#enter sib2, iclass 12, count 0 2006.260.08:12:48.87#ibcon#flushed, iclass 12, count 0 2006.260.08:12:48.87#ibcon#about to write, iclass 12, count 0 2006.260.08:12:48.87#ibcon#wrote, iclass 12, count 0 2006.260.08:12:48.87#ibcon#about to read 3, iclass 12, count 0 2006.260.08:12:48.91#ibcon#read 3, iclass 12, count 0 2006.260.08:12:48.91#ibcon#about to read 4, iclass 12, count 0 2006.260.08:12:48.91#ibcon#read 4, iclass 12, count 0 2006.260.08:12:48.91#ibcon#about to read 5, iclass 12, count 0 2006.260.08:12:48.91#ibcon#read 5, iclass 12, count 0 2006.260.08:12:48.91#ibcon#about to read 6, iclass 12, count 0 2006.260.08:12:48.91#ibcon#read 6, iclass 12, count 0 2006.260.08:12:48.91#ibcon#end of sib2, iclass 12, count 0 2006.260.08:12:48.91#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:12:48.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:12:48.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:12:48.91#ibcon#*before write, iclass 12, count 0 2006.260.08:12:48.91#ibcon#enter sib2, iclass 12, count 0 2006.260.08:12:48.91#ibcon#flushed, iclass 12, count 0 2006.260.08:12:48.91#ibcon#about to write, iclass 12, count 0 2006.260.08:12:48.91#ibcon#wrote, iclass 12, count 0 2006.260.08:12:48.91#ibcon#about to read 3, iclass 12, count 0 2006.260.08:12:48.96#ibcon#read 3, iclass 12, count 0 2006.260.08:12:48.96#ibcon#about to read 4, iclass 12, count 0 2006.260.08:12:48.96#ibcon#read 4, iclass 12, count 0 2006.260.08:12:48.96#ibcon#about to read 5, iclass 12, count 0 2006.260.08:12:48.96#ibcon#read 5, iclass 12, count 0 2006.260.08:12:48.96#ibcon#about to read 6, iclass 12, count 0 2006.260.08:12:48.96#ibcon#read 6, iclass 12, count 0 2006.260.08:12:48.96#ibcon#end of sib2, iclass 12, count 0 2006.260.08:12:48.96#ibcon#*after write, iclass 12, count 0 2006.260.08:12:48.96#ibcon#*before return 0, iclass 12, count 0 2006.260.08:12:48.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:48.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:48.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:12:48.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:12:48.96$vc4f8/va=1,8 2006.260.08:12:48.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.08:12:48.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.08:12:48.96#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:48.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:48.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:48.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:48.96#ibcon#enter wrdev, iclass 14, count 2 2006.260.08:12:48.96#ibcon#first serial, iclass 14, count 2 2006.260.08:12:48.96#ibcon#enter sib2, iclass 14, count 2 2006.260.08:12:48.96#ibcon#flushed, iclass 14, count 2 2006.260.08:12:48.96#ibcon#about to write, iclass 14, count 2 2006.260.08:12:48.96#ibcon#wrote, iclass 14, count 2 2006.260.08:12:48.96#ibcon#about to read 3, iclass 14, count 2 2006.260.08:12:48.98#ibcon#read 3, iclass 14, count 2 2006.260.08:12:48.98#ibcon#about to read 4, iclass 14, count 2 2006.260.08:12:48.98#ibcon#read 4, iclass 14, count 2 2006.260.08:12:48.98#ibcon#about to read 5, iclass 14, count 2 2006.260.08:12:48.98#ibcon#read 5, iclass 14, count 2 2006.260.08:12:48.98#ibcon#about to read 6, iclass 14, count 2 2006.260.08:12:48.98#ibcon#read 6, iclass 14, count 2 2006.260.08:12:48.98#ibcon#end of sib2, iclass 14, count 2 2006.260.08:12:48.98#ibcon#*mode == 0, iclass 14, count 2 2006.260.08:12:48.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.08:12:48.98#ibcon#[25=AT01-08\r\n] 2006.260.08:12:48.98#ibcon#*before write, iclass 14, count 2 2006.260.08:12:48.98#ibcon#enter sib2, iclass 14, count 2 2006.260.08:12:48.98#ibcon#flushed, iclass 14, count 2 2006.260.08:12:48.98#ibcon#about to write, iclass 14, count 2 2006.260.08:12:48.98#ibcon#wrote, iclass 14, count 2 2006.260.08:12:48.98#ibcon#about to read 3, iclass 14, count 2 2006.260.08:12:49.01#ibcon#read 3, iclass 14, count 2 2006.260.08:12:49.01#ibcon#about to read 4, iclass 14, count 2 2006.260.08:12:49.01#ibcon#read 4, iclass 14, count 2 2006.260.08:12:49.01#ibcon#about to read 5, iclass 14, count 2 2006.260.08:12:49.01#ibcon#read 5, iclass 14, count 2 2006.260.08:12:49.01#ibcon#about to read 6, iclass 14, count 2 2006.260.08:12:49.01#ibcon#read 6, iclass 14, count 2 2006.260.08:12:49.01#ibcon#end of sib2, iclass 14, count 2 2006.260.08:12:49.01#ibcon#*after write, iclass 14, count 2 2006.260.08:12:49.01#ibcon#*before return 0, iclass 14, count 2 2006.260.08:12:49.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:49.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:49.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.08:12:49.01#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:49.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:49.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:49.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:49.13#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:12:49.13#ibcon#first serial, iclass 14, count 0 2006.260.08:12:49.13#ibcon#enter sib2, iclass 14, count 0 2006.260.08:12:49.13#ibcon#flushed, iclass 14, count 0 2006.260.08:12:49.13#ibcon#about to write, iclass 14, count 0 2006.260.08:12:49.13#ibcon#wrote, iclass 14, count 0 2006.260.08:12:49.13#ibcon#about to read 3, iclass 14, count 0 2006.260.08:12:49.15#ibcon#read 3, iclass 14, count 0 2006.260.08:12:49.15#ibcon#about to read 4, iclass 14, count 0 2006.260.08:12:49.15#ibcon#read 4, iclass 14, count 0 2006.260.08:12:49.15#ibcon#about to read 5, iclass 14, count 0 2006.260.08:12:49.15#ibcon#read 5, iclass 14, count 0 2006.260.08:12:49.15#ibcon#about to read 6, iclass 14, count 0 2006.260.08:12:49.15#ibcon#read 6, iclass 14, count 0 2006.260.08:12:49.15#ibcon#end of sib2, iclass 14, count 0 2006.260.08:12:49.15#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:12:49.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:12:49.15#ibcon#[25=USB\r\n] 2006.260.08:12:49.15#ibcon#*before write, iclass 14, count 0 2006.260.08:12:49.15#ibcon#enter sib2, iclass 14, count 0 2006.260.08:12:49.15#ibcon#flushed, iclass 14, count 0 2006.260.08:12:49.15#ibcon#about to write, iclass 14, count 0 2006.260.08:12:49.15#ibcon#wrote, iclass 14, count 0 2006.260.08:12:49.15#ibcon#about to read 3, iclass 14, count 0 2006.260.08:12:49.18#ibcon#read 3, iclass 14, count 0 2006.260.08:12:49.18#ibcon#about to read 4, iclass 14, count 0 2006.260.08:12:49.18#ibcon#read 4, iclass 14, count 0 2006.260.08:12:49.18#ibcon#about to read 5, iclass 14, count 0 2006.260.08:12:49.18#ibcon#read 5, iclass 14, count 0 2006.260.08:12:49.18#ibcon#about to read 6, iclass 14, count 0 2006.260.08:12:49.18#ibcon#read 6, iclass 14, count 0 2006.260.08:12:49.18#ibcon#end of sib2, iclass 14, count 0 2006.260.08:12:49.18#ibcon#*after write, iclass 14, count 0 2006.260.08:12:49.18#ibcon#*before return 0, iclass 14, count 0 2006.260.08:12:49.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:49.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:49.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:12:49.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:12:49.18$vc4f8/valo=2,572.99 2006.260.08:12:49.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.08:12:49.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.08:12:49.18#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:49.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:49.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:49.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:49.18#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:12:49.18#ibcon#first serial, iclass 16, count 0 2006.260.08:12:49.18#ibcon#enter sib2, iclass 16, count 0 2006.260.08:12:49.18#ibcon#flushed, iclass 16, count 0 2006.260.08:12:49.18#ibcon#about to write, iclass 16, count 0 2006.260.08:12:49.18#ibcon#wrote, iclass 16, count 0 2006.260.08:12:49.18#ibcon#about to read 3, iclass 16, count 0 2006.260.08:12:49.21#ibcon#read 3, iclass 16, count 0 2006.260.08:12:49.21#ibcon#about to read 4, iclass 16, count 0 2006.260.08:12:49.21#ibcon#read 4, iclass 16, count 0 2006.260.08:12:49.21#ibcon#about to read 5, iclass 16, count 0 2006.260.08:12:49.21#ibcon#read 5, iclass 16, count 0 2006.260.08:12:49.21#ibcon#about to read 6, iclass 16, count 0 2006.260.08:12:49.21#ibcon#read 6, iclass 16, count 0 2006.260.08:12:49.21#ibcon#end of sib2, iclass 16, count 0 2006.260.08:12:49.21#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:12:49.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:12:49.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:12:49.21#ibcon#*before write, iclass 16, count 0 2006.260.08:12:49.21#ibcon#enter sib2, iclass 16, count 0 2006.260.08:12:49.21#ibcon#flushed, iclass 16, count 0 2006.260.08:12:49.21#ibcon#about to write, iclass 16, count 0 2006.260.08:12:49.21#ibcon#wrote, iclass 16, count 0 2006.260.08:12:49.21#ibcon#about to read 3, iclass 16, count 0 2006.260.08:12:49.25#ibcon#read 3, iclass 16, count 0 2006.260.08:12:49.25#ibcon#about to read 4, iclass 16, count 0 2006.260.08:12:49.25#ibcon#read 4, iclass 16, count 0 2006.260.08:12:49.25#ibcon#about to read 5, iclass 16, count 0 2006.260.08:12:49.25#ibcon#read 5, iclass 16, count 0 2006.260.08:12:49.25#ibcon#about to read 6, iclass 16, count 0 2006.260.08:12:49.25#ibcon#read 6, iclass 16, count 0 2006.260.08:12:49.25#ibcon#end of sib2, iclass 16, count 0 2006.260.08:12:49.25#ibcon#*after write, iclass 16, count 0 2006.260.08:12:49.25#ibcon#*before return 0, iclass 16, count 0 2006.260.08:12:49.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:49.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:49.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:12:49.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:12:49.25$vc4f8/va=2,7 2006.260.08:12:49.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.08:12:49.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.08:12:49.25#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:49.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:49.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:49.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:49.30#ibcon#enter wrdev, iclass 18, count 2 2006.260.08:12:49.30#ibcon#first serial, iclass 18, count 2 2006.260.08:12:49.30#ibcon#enter sib2, iclass 18, count 2 2006.260.08:12:49.30#ibcon#flushed, iclass 18, count 2 2006.260.08:12:49.30#ibcon#about to write, iclass 18, count 2 2006.260.08:12:49.30#ibcon#wrote, iclass 18, count 2 2006.260.08:12:49.30#ibcon#about to read 3, iclass 18, count 2 2006.260.08:12:49.33#ibcon#read 3, iclass 18, count 2 2006.260.08:12:49.33#ibcon#about to read 4, iclass 18, count 2 2006.260.08:12:49.33#ibcon#read 4, iclass 18, count 2 2006.260.08:12:49.33#ibcon#about to read 5, iclass 18, count 2 2006.260.08:12:49.33#ibcon#read 5, iclass 18, count 2 2006.260.08:12:49.33#ibcon#about to read 6, iclass 18, count 2 2006.260.08:12:49.33#ibcon#read 6, iclass 18, count 2 2006.260.08:12:49.33#ibcon#end of sib2, iclass 18, count 2 2006.260.08:12:49.33#ibcon#*mode == 0, iclass 18, count 2 2006.260.08:12:49.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.08:12:49.33#ibcon#[25=AT02-07\r\n] 2006.260.08:12:49.33#ibcon#*before write, iclass 18, count 2 2006.260.08:12:49.33#ibcon#enter sib2, iclass 18, count 2 2006.260.08:12:49.33#ibcon#flushed, iclass 18, count 2 2006.260.08:12:49.33#ibcon#about to write, iclass 18, count 2 2006.260.08:12:49.33#ibcon#wrote, iclass 18, count 2 2006.260.08:12:49.33#ibcon#about to read 3, iclass 18, count 2 2006.260.08:12:49.36#ibcon#read 3, iclass 18, count 2 2006.260.08:12:49.36#ibcon#about to read 4, iclass 18, count 2 2006.260.08:12:49.36#ibcon#read 4, iclass 18, count 2 2006.260.08:12:49.36#ibcon#about to read 5, iclass 18, count 2 2006.260.08:12:49.36#ibcon#read 5, iclass 18, count 2 2006.260.08:12:49.36#ibcon#about to read 6, iclass 18, count 2 2006.260.08:12:49.36#ibcon#read 6, iclass 18, count 2 2006.260.08:12:49.36#ibcon#end of sib2, iclass 18, count 2 2006.260.08:12:49.36#ibcon#*after write, iclass 18, count 2 2006.260.08:12:49.36#ibcon#*before return 0, iclass 18, count 2 2006.260.08:12:49.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:49.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:49.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.08:12:49.36#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:49.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:49.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:49.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:49.48#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:12:49.48#ibcon#first serial, iclass 18, count 0 2006.260.08:12:49.48#ibcon#enter sib2, iclass 18, count 0 2006.260.08:12:49.48#ibcon#flushed, iclass 18, count 0 2006.260.08:12:49.48#ibcon#about to write, iclass 18, count 0 2006.260.08:12:49.48#ibcon#wrote, iclass 18, count 0 2006.260.08:12:49.48#ibcon#about to read 3, iclass 18, count 0 2006.260.08:12:49.50#ibcon#read 3, iclass 18, count 0 2006.260.08:12:49.50#ibcon#about to read 4, iclass 18, count 0 2006.260.08:12:49.50#ibcon#read 4, iclass 18, count 0 2006.260.08:12:49.50#ibcon#about to read 5, iclass 18, count 0 2006.260.08:12:49.50#ibcon#read 5, iclass 18, count 0 2006.260.08:12:49.50#ibcon#about to read 6, iclass 18, count 0 2006.260.08:12:49.50#ibcon#read 6, iclass 18, count 0 2006.260.08:12:49.50#ibcon#end of sib2, iclass 18, count 0 2006.260.08:12:49.50#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:12:49.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:12:49.50#ibcon#[25=USB\r\n] 2006.260.08:12:49.50#ibcon#*before write, iclass 18, count 0 2006.260.08:12:49.50#ibcon#enter sib2, iclass 18, count 0 2006.260.08:12:49.50#ibcon#flushed, iclass 18, count 0 2006.260.08:12:49.50#ibcon#about to write, iclass 18, count 0 2006.260.08:12:49.50#ibcon#wrote, iclass 18, count 0 2006.260.08:12:49.50#ibcon#about to read 3, iclass 18, count 0 2006.260.08:12:49.53#ibcon#read 3, iclass 18, count 0 2006.260.08:12:49.53#ibcon#about to read 4, iclass 18, count 0 2006.260.08:12:49.53#ibcon#read 4, iclass 18, count 0 2006.260.08:12:49.53#ibcon#about to read 5, iclass 18, count 0 2006.260.08:12:49.53#ibcon#read 5, iclass 18, count 0 2006.260.08:12:49.53#ibcon#about to read 6, iclass 18, count 0 2006.260.08:12:49.53#ibcon#read 6, iclass 18, count 0 2006.260.08:12:49.53#ibcon#end of sib2, iclass 18, count 0 2006.260.08:12:49.53#ibcon#*after write, iclass 18, count 0 2006.260.08:12:49.53#ibcon#*before return 0, iclass 18, count 0 2006.260.08:12:49.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:49.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:49.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:12:49.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:12:49.53$vc4f8/valo=3,672.99 2006.260.08:12:49.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.08:12:49.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.08:12:49.53#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:49.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:49.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:49.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:49.53#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:12:49.53#ibcon#first serial, iclass 20, count 0 2006.260.08:12:49.53#ibcon#enter sib2, iclass 20, count 0 2006.260.08:12:49.53#ibcon#flushed, iclass 20, count 0 2006.260.08:12:49.53#ibcon#about to write, iclass 20, count 0 2006.260.08:12:49.53#ibcon#wrote, iclass 20, count 0 2006.260.08:12:49.53#ibcon#about to read 3, iclass 20, count 0 2006.260.08:12:49.55#ibcon#read 3, iclass 20, count 0 2006.260.08:12:49.55#ibcon#about to read 4, iclass 20, count 0 2006.260.08:12:49.55#ibcon#read 4, iclass 20, count 0 2006.260.08:12:49.55#ibcon#about to read 5, iclass 20, count 0 2006.260.08:12:49.55#ibcon#read 5, iclass 20, count 0 2006.260.08:12:49.55#ibcon#about to read 6, iclass 20, count 0 2006.260.08:12:49.55#ibcon#read 6, iclass 20, count 0 2006.260.08:12:49.55#ibcon#end of sib2, iclass 20, count 0 2006.260.08:12:49.55#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:12:49.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:12:49.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:12:49.55#ibcon#*before write, iclass 20, count 0 2006.260.08:12:49.55#ibcon#enter sib2, iclass 20, count 0 2006.260.08:12:49.55#ibcon#flushed, iclass 20, count 0 2006.260.08:12:49.55#ibcon#about to write, iclass 20, count 0 2006.260.08:12:49.55#ibcon#wrote, iclass 20, count 0 2006.260.08:12:49.55#ibcon#about to read 3, iclass 20, count 0 2006.260.08:12:49.59#ibcon#read 3, iclass 20, count 0 2006.260.08:12:49.59#ibcon#about to read 4, iclass 20, count 0 2006.260.08:12:49.59#ibcon#read 4, iclass 20, count 0 2006.260.08:12:49.59#ibcon#about to read 5, iclass 20, count 0 2006.260.08:12:49.59#ibcon#read 5, iclass 20, count 0 2006.260.08:12:49.59#ibcon#about to read 6, iclass 20, count 0 2006.260.08:12:49.59#ibcon#read 6, iclass 20, count 0 2006.260.08:12:49.59#ibcon#end of sib2, iclass 20, count 0 2006.260.08:12:49.59#ibcon#*after write, iclass 20, count 0 2006.260.08:12:49.59#ibcon#*before return 0, iclass 20, count 0 2006.260.08:12:49.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:49.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:49.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:12:49.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:12:49.59$vc4f8/va=3,8 2006.260.08:12:49.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.08:12:49.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.08:12:49.59#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:49.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:49.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:49.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:49.65#ibcon#enter wrdev, iclass 22, count 2 2006.260.08:12:49.65#ibcon#first serial, iclass 22, count 2 2006.260.08:12:49.65#ibcon#enter sib2, iclass 22, count 2 2006.260.08:12:49.65#ibcon#flushed, iclass 22, count 2 2006.260.08:12:49.65#ibcon#about to write, iclass 22, count 2 2006.260.08:12:49.65#ibcon#wrote, iclass 22, count 2 2006.260.08:12:49.65#ibcon#about to read 3, iclass 22, count 2 2006.260.08:12:49.67#ibcon#read 3, iclass 22, count 2 2006.260.08:12:49.67#ibcon#about to read 4, iclass 22, count 2 2006.260.08:12:49.67#ibcon#read 4, iclass 22, count 2 2006.260.08:12:49.67#ibcon#about to read 5, iclass 22, count 2 2006.260.08:12:49.67#ibcon#read 5, iclass 22, count 2 2006.260.08:12:49.67#ibcon#about to read 6, iclass 22, count 2 2006.260.08:12:49.67#ibcon#read 6, iclass 22, count 2 2006.260.08:12:49.67#ibcon#end of sib2, iclass 22, count 2 2006.260.08:12:49.67#ibcon#*mode == 0, iclass 22, count 2 2006.260.08:12:49.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.08:12:49.67#ibcon#[25=AT03-08\r\n] 2006.260.08:12:49.67#ibcon#*before write, iclass 22, count 2 2006.260.08:12:49.67#ibcon#enter sib2, iclass 22, count 2 2006.260.08:12:49.67#ibcon#flushed, iclass 22, count 2 2006.260.08:12:49.67#ibcon#about to write, iclass 22, count 2 2006.260.08:12:49.67#ibcon#wrote, iclass 22, count 2 2006.260.08:12:49.67#ibcon#about to read 3, iclass 22, count 2 2006.260.08:12:49.70#ibcon#read 3, iclass 22, count 2 2006.260.08:12:49.70#ibcon#about to read 4, iclass 22, count 2 2006.260.08:12:49.70#ibcon#read 4, iclass 22, count 2 2006.260.08:12:49.70#ibcon#about to read 5, iclass 22, count 2 2006.260.08:12:49.70#ibcon#read 5, iclass 22, count 2 2006.260.08:12:49.70#ibcon#about to read 6, iclass 22, count 2 2006.260.08:12:49.70#ibcon#read 6, iclass 22, count 2 2006.260.08:12:49.70#ibcon#end of sib2, iclass 22, count 2 2006.260.08:12:49.70#ibcon#*after write, iclass 22, count 2 2006.260.08:12:49.70#ibcon#*before return 0, iclass 22, count 2 2006.260.08:12:49.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:49.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:49.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.08:12:49.70#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:49.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:49.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:49.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:49.82#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:12:49.82#ibcon#first serial, iclass 22, count 0 2006.260.08:12:49.82#ibcon#enter sib2, iclass 22, count 0 2006.260.08:12:49.82#ibcon#flushed, iclass 22, count 0 2006.260.08:12:49.82#ibcon#about to write, iclass 22, count 0 2006.260.08:12:49.82#ibcon#wrote, iclass 22, count 0 2006.260.08:12:49.82#ibcon#about to read 3, iclass 22, count 0 2006.260.08:12:49.84#ibcon#read 3, iclass 22, count 0 2006.260.08:12:49.84#ibcon#about to read 4, iclass 22, count 0 2006.260.08:12:49.84#ibcon#read 4, iclass 22, count 0 2006.260.08:12:49.84#ibcon#about to read 5, iclass 22, count 0 2006.260.08:12:49.84#ibcon#read 5, iclass 22, count 0 2006.260.08:12:49.84#ibcon#about to read 6, iclass 22, count 0 2006.260.08:12:49.84#ibcon#read 6, iclass 22, count 0 2006.260.08:12:49.84#ibcon#end of sib2, iclass 22, count 0 2006.260.08:12:49.84#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:12:49.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:12:49.84#ibcon#[25=USB\r\n] 2006.260.08:12:49.84#ibcon#*before write, iclass 22, count 0 2006.260.08:12:49.84#ibcon#enter sib2, iclass 22, count 0 2006.260.08:12:49.84#ibcon#flushed, iclass 22, count 0 2006.260.08:12:49.84#ibcon#about to write, iclass 22, count 0 2006.260.08:12:49.84#ibcon#wrote, iclass 22, count 0 2006.260.08:12:49.84#ibcon#about to read 3, iclass 22, count 0 2006.260.08:12:49.87#ibcon#read 3, iclass 22, count 0 2006.260.08:12:49.87#ibcon#about to read 4, iclass 22, count 0 2006.260.08:12:49.87#ibcon#read 4, iclass 22, count 0 2006.260.08:12:49.87#ibcon#about to read 5, iclass 22, count 0 2006.260.08:12:49.87#ibcon#read 5, iclass 22, count 0 2006.260.08:12:49.87#ibcon#about to read 6, iclass 22, count 0 2006.260.08:12:49.87#ibcon#read 6, iclass 22, count 0 2006.260.08:12:49.87#ibcon#end of sib2, iclass 22, count 0 2006.260.08:12:49.87#ibcon#*after write, iclass 22, count 0 2006.260.08:12:49.87#ibcon#*before return 0, iclass 22, count 0 2006.260.08:12:49.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:49.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:49.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:12:49.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:12:49.87$vc4f8/valo=4,832.99 2006.260.08:12:49.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.08:12:49.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.08:12:49.87#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:49.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:49.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:49.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:49.87#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:12:49.87#ibcon#first serial, iclass 24, count 0 2006.260.08:12:49.87#ibcon#enter sib2, iclass 24, count 0 2006.260.08:12:49.87#ibcon#flushed, iclass 24, count 0 2006.260.08:12:49.87#ibcon#about to write, iclass 24, count 0 2006.260.08:12:49.87#ibcon#wrote, iclass 24, count 0 2006.260.08:12:49.87#ibcon#about to read 3, iclass 24, count 0 2006.260.08:12:49.89#ibcon#read 3, iclass 24, count 0 2006.260.08:12:49.89#ibcon#about to read 4, iclass 24, count 0 2006.260.08:12:49.89#ibcon#read 4, iclass 24, count 0 2006.260.08:12:49.89#ibcon#about to read 5, iclass 24, count 0 2006.260.08:12:49.89#ibcon#read 5, iclass 24, count 0 2006.260.08:12:49.89#ibcon#about to read 6, iclass 24, count 0 2006.260.08:12:49.89#ibcon#read 6, iclass 24, count 0 2006.260.08:12:49.89#ibcon#end of sib2, iclass 24, count 0 2006.260.08:12:49.89#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:12:49.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:12:49.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:12:49.89#ibcon#*before write, iclass 24, count 0 2006.260.08:12:49.89#ibcon#enter sib2, iclass 24, count 0 2006.260.08:12:49.89#ibcon#flushed, iclass 24, count 0 2006.260.08:12:49.89#ibcon#about to write, iclass 24, count 0 2006.260.08:12:49.89#ibcon#wrote, iclass 24, count 0 2006.260.08:12:49.89#ibcon#about to read 3, iclass 24, count 0 2006.260.08:12:49.93#ibcon#read 3, iclass 24, count 0 2006.260.08:12:49.93#ibcon#about to read 4, iclass 24, count 0 2006.260.08:12:49.93#ibcon#read 4, iclass 24, count 0 2006.260.08:12:49.93#ibcon#about to read 5, iclass 24, count 0 2006.260.08:12:49.93#ibcon#read 5, iclass 24, count 0 2006.260.08:12:49.93#ibcon#about to read 6, iclass 24, count 0 2006.260.08:12:49.93#ibcon#read 6, iclass 24, count 0 2006.260.08:12:49.93#ibcon#end of sib2, iclass 24, count 0 2006.260.08:12:49.93#ibcon#*after write, iclass 24, count 0 2006.260.08:12:49.93#ibcon#*before return 0, iclass 24, count 0 2006.260.08:12:49.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:49.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:49.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:12:49.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:12:49.93$vc4f8/va=4,7 2006.260.08:12:49.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.08:12:49.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.08:12:49.93#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:49.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:49.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:49.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:49.99#ibcon#enter wrdev, iclass 26, count 2 2006.260.08:12:49.99#ibcon#first serial, iclass 26, count 2 2006.260.08:12:49.99#ibcon#enter sib2, iclass 26, count 2 2006.260.08:12:49.99#ibcon#flushed, iclass 26, count 2 2006.260.08:12:49.99#ibcon#about to write, iclass 26, count 2 2006.260.08:12:49.99#ibcon#wrote, iclass 26, count 2 2006.260.08:12:49.99#ibcon#about to read 3, iclass 26, count 2 2006.260.08:12:50.01#ibcon#read 3, iclass 26, count 2 2006.260.08:12:50.01#ibcon#about to read 4, iclass 26, count 2 2006.260.08:12:50.01#ibcon#read 4, iclass 26, count 2 2006.260.08:12:50.01#ibcon#about to read 5, iclass 26, count 2 2006.260.08:12:50.01#ibcon#read 5, iclass 26, count 2 2006.260.08:12:50.01#ibcon#about to read 6, iclass 26, count 2 2006.260.08:12:50.01#ibcon#read 6, iclass 26, count 2 2006.260.08:12:50.01#ibcon#end of sib2, iclass 26, count 2 2006.260.08:12:50.01#ibcon#*mode == 0, iclass 26, count 2 2006.260.08:12:50.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.08:12:50.01#ibcon#[25=AT04-07\r\n] 2006.260.08:12:50.01#ibcon#*before write, iclass 26, count 2 2006.260.08:12:50.01#ibcon#enter sib2, iclass 26, count 2 2006.260.08:12:50.01#ibcon#flushed, iclass 26, count 2 2006.260.08:12:50.01#ibcon#about to write, iclass 26, count 2 2006.260.08:12:50.01#ibcon#wrote, iclass 26, count 2 2006.260.08:12:50.01#ibcon#about to read 3, iclass 26, count 2 2006.260.08:12:50.04#ibcon#read 3, iclass 26, count 2 2006.260.08:12:50.04#ibcon#about to read 4, iclass 26, count 2 2006.260.08:12:50.04#ibcon#read 4, iclass 26, count 2 2006.260.08:12:50.04#ibcon#about to read 5, iclass 26, count 2 2006.260.08:12:50.04#ibcon#read 5, iclass 26, count 2 2006.260.08:12:50.04#ibcon#about to read 6, iclass 26, count 2 2006.260.08:12:50.04#ibcon#read 6, iclass 26, count 2 2006.260.08:12:50.04#ibcon#end of sib2, iclass 26, count 2 2006.260.08:12:50.04#ibcon#*after write, iclass 26, count 2 2006.260.08:12:50.04#ibcon#*before return 0, iclass 26, count 2 2006.260.08:12:50.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:50.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:50.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.08:12:50.04#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:50.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:50.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:50.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:50.16#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:12:50.16#ibcon#first serial, iclass 26, count 0 2006.260.08:12:50.16#ibcon#enter sib2, iclass 26, count 0 2006.260.08:12:50.16#ibcon#flushed, iclass 26, count 0 2006.260.08:12:50.16#ibcon#about to write, iclass 26, count 0 2006.260.08:12:50.16#ibcon#wrote, iclass 26, count 0 2006.260.08:12:50.16#ibcon#about to read 3, iclass 26, count 0 2006.260.08:12:50.18#ibcon#read 3, iclass 26, count 0 2006.260.08:12:50.18#ibcon#about to read 4, iclass 26, count 0 2006.260.08:12:50.18#ibcon#read 4, iclass 26, count 0 2006.260.08:12:50.18#ibcon#about to read 5, iclass 26, count 0 2006.260.08:12:50.18#ibcon#read 5, iclass 26, count 0 2006.260.08:12:50.18#ibcon#about to read 6, iclass 26, count 0 2006.260.08:12:50.18#ibcon#read 6, iclass 26, count 0 2006.260.08:12:50.18#ibcon#end of sib2, iclass 26, count 0 2006.260.08:12:50.18#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:12:50.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:12:50.18#ibcon#[25=USB\r\n] 2006.260.08:12:50.18#ibcon#*before write, iclass 26, count 0 2006.260.08:12:50.18#ibcon#enter sib2, iclass 26, count 0 2006.260.08:12:50.18#ibcon#flushed, iclass 26, count 0 2006.260.08:12:50.18#ibcon#about to write, iclass 26, count 0 2006.260.08:12:50.18#ibcon#wrote, iclass 26, count 0 2006.260.08:12:50.18#ibcon#about to read 3, iclass 26, count 0 2006.260.08:12:50.21#ibcon#read 3, iclass 26, count 0 2006.260.08:12:50.21#ibcon#about to read 4, iclass 26, count 0 2006.260.08:12:50.21#ibcon#read 4, iclass 26, count 0 2006.260.08:12:50.21#ibcon#about to read 5, iclass 26, count 0 2006.260.08:12:50.21#ibcon#read 5, iclass 26, count 0 2006.260.08:12:50.21#ibcon#about to read 6, iclass 26, count 0 2006.260.08:12:50.21#ibcon#read 6, iclass 26, count 0 2006.260.08:12:50.21#ibcon#end of sib2, iclass 26, count 0 2006.260.08:12:50.21#ibcon#*after write, iclass 26, count 0 2006.260.08:12:50.21#ibcon#*before return 0, iclass 26, count 0 2006.260.08:12:50.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:50.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:50.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:12:50.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:12:50.21$vc4f8/valo=5,652.99 2006.260.08:12:50.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:12:50.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:12:50.21#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:50.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:50.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:50.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:50.21#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:12:50.21#ibcon#first serial, iclass 28, count 0 2006.260.08:12:50.21#ibcon#enter sib2, iclass 28, count 0 2006.260.08:12:50.21#ibcon#flushed, iclass 28, count 0 2006.260.08:12:50.21#ibcon#about to write, iclass 28, count 0 2006.260.08:12:50.21#ibcon#wrote, iclass 28, count 0 2006.260.08:12:50.21#ibcon#about to read 3, iclass 28, count 0 2006.260.08:12:50.23#ibcon#read 3, iclass 28, count 0 2006.260.08:12:50.23#ibcon#about to read 4, iclass 28, count 0 2006.260.08:12:50.23#ibcon#read 4, iclass 28, count 0 2006.260.08:12:50.23#ibcon#about to read 5, iclass 28, count 0 2006.260.08:12:50.23#ibcon#read 5, iclass 28, count 0 2006.260.08:12:50.23#ibcon#about to read 6, iclass 28, count 0 2006.260.08:12:50.23#ibcon#read 6, iclass 28, count 0 2006.260.08:12:50.23#ibcon#end of sib2, iclass 28, count 0 2006.260.08:12:50.23#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:12:50.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:12:50.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:12:50.23#ibcon#*before write, iclass 28, count 0 2006.260.08:12:50.23#ibcon#enter sib2, iclass 28, count 0 2006.260.08:12:50.23#ibcon#flushed, iclass 28, count 0 2006.260.08:12:50.23#ibcon#about to write, iclass 28, count 0 2006.260.08:12:50.23#ibcon#wrote, iclass 28, count 0 2006.260.08:12:50.23#ibcon#about to read 3, iclass 28, count 0 2006.260.08:12:50.27#ibcon#read 3, iclass 28, count 0 2006.260.08:12:50.27#ibcon#about to read 4, iclass 28, count 0 2006.260.08:12:50.27#ibcon#read 4, iclass 28, count 0 2006.260.08:12:50.27#ibcon#about to read 5, iclass 28, count 0 2006.260.08:12:50.27#ibcon#read 5, iclass 28, count 0 2006.260.08:12:50.27#ibcon#about to read 6, iclass 28, count 0 2006.260.08:12:50.27#ibcon#read 6, iclass 28, count 0 2006.260.08:12:50.27#ibcon#end of sib2, iclass 28, count 0 2006.260.08:12:50.27#ibcon#*after write, iclass 28, count 0 2006.260.08:12:50.27#ibcon#*before return 0, iclass 28, count 0 2006.260.08:12:50.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:50.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:50.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:12:50.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:12:50.27$vc4f8/va=5,7 2006.260.08:12:50.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:12:50.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:12:50.27#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:50.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:50.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:50.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:50.33#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:12:50.33#ibcon#first serial, iclass 30, count 2 2006.260.08:12:50.33#ibcon#enter sib2, iclass 30, count 2 2006.260.08:12:50.33#ibcon#flushed, iclass 30, count 2 2006.260.08:12:50.33#ibcon#about to write, iclass 30, count 2 2006.260.08:12:50.33#ibcon#wrote, iclass 30, count 2 2006.260.08:12:50.33#ibcon#about to read 3, iclass 30, count 2 2006.260.08:12:50.35#ibcon#read 3, iclass 30, count 2 2006.260.08:12:50.35#ibcon#about to read 4, iclass 30, count 2 2006.260.08:12:50.35#ibcon#read 4, iclass 30, count 2 2006.260.08:12:50.35#ibcon#about to read 5, iclass 30, count 2 2006.260.08:12:50.35#ibcon#read 5, iclass 30, count 2 2006.260.08:12:50.35#ibcon#about to read 6, iclass 30, count 2 2006.260.08:12:50.35#ibcon#read 6, iclass 30, count 2 2006.260.08:12:50.35#ibcon#end of sib2, iclass 30, count 2 2006.260.08:12:50.35#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:12:50.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:12:50.35#ibcon#[25=AT05-07\r\n] 2006.260.08:12:50.35#ibcon#*before write, iclass 30, count 2 2006.260.08:12:50.35#ibcon#enter sib2, iclass 30, count 2 2006.260.08:12:50.35#ibcon#flushed, iclass 30, count 2 2006.260.08:12:50.35#ibcon#about to write, iclass 30, count 2 2006.260.08:12:50.35#ibcon#wrote, iclass 30, count 2 2006.260.08:12:50.35#ibcon#about to read 3, iclass 30, count 2 2006.260.08:12:50.38#ibcon#read 3, iclass 30, count 2 2006.260.08:12:50.38#ibcon#about to read 4, iclass 30, count 2 2006.260.08:12:50.38#ibcon#read 4, iclass 30, count 2 2006.260.08:12:50.38#ibcon#about to read 5, iclass 30, count 2 2006.260.08:12:50.38#ibcon#read 5, iclass 30, count 2 2006.260.08:12:50.38#ibcon#about to read 6, iclass 30, count 2 2006.260.08:12:50.38#ibcon#read 6, iclass 30, count 2 2006.260.08:12:50.38#ibcon#end of sib2, iclass 30, count 2 2006.260.08:12:50.38#ibcon#*after write, iclass 30, count 2 2006.260.08:12:50.38#ibcon#*before return 0, iclass 30, count 2 2006.260.08:12:50.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:50.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:50.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:12:50.38#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:50.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:50.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:50.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:50.50#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:12:50.50#ibcon#first serial, iclass 30, count 0 2006.260.08:12:50.50#ibcon#enter sib2, iclass 30, count 0 2006.260.08:12:50.50#ibcon#flushed, iclass 30, count 0 2006.260.08:12:50.50#ibcon#about to write, iclass 30, count 0 2006.260.08:12:50.50#ibcon#wrote, iclass 30, count 0 2006.260.08:12:50.50#ibcon#about to read 3, iclass 30, count 0 2006.260.08:12:50.52#ibcon#read 3, iclass 30, count 0 2006.260.08:12:50.52#ibcon#about to read 4, iclass 30, count 0 2006.260.08:12:50.52#ibcon#read 4, iclass 30, count 0 2006.260.08:12:50.52#ibcon#about to read 5, iclass 30, count 0 2006.260.08:12:50.52#ibcon#read 5, iclass 30, count 0 2006.260.08:12:50.52#ibcon#about to read 6, iclass 30, count 0 2006.260.08:12:50.52#ibcon#read 6, iclass 30, count 0 2006.260.08:12:50.52#ibcon#end of sib2, iclass 30, count 0 2006.260.08:12:50.52#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:12:50.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:12:50.52#ibcon#[25=USB\r\n] 2006.260.08:12:50.52#ibcon#*before write, iclass 30, count 0 2006.260.08:12:50.52#ibcon#enter sib2, iclass 30, count 0 2006.260.08:12:50.52#ibcon#flushed, iclass 30, count 0 2006.260.08:12:50.52#ibcon#about to write, iclass 30, count 0 2006.260.08:12:50.52#ibcon#wrote, iclass 30, count 0 2006.260.08:12:50.52#ibcon#about to read 3, iclass 30, count 0 2006.260.08:12:50.55#ibcon#read 3, iclass 30, count 0 2006.260.08:12:50.55#ibcon#about to read 4, iclass 30, count 0 2006.260.08:12:50.55#ibcon#read 4, iclass 30, count 0 2006.260.08:12:50.55#ibcon#about to read 5, iclass 30, count 0 2006.260.08:12:50.55#ibcon#read 5, iclass 30, count 0 2006.260.08:12:50.55#ibcon#about to read 6, iclass 30, count 0 2006.260.08:12:50.55#ibcon#read 6, iclass 30, count 0 2006.260.08:12:50.55#ibcon#end of sib2, iclass 30, count 0 2006.260.08:12:50.55#ibcon#*after write, iclass 30, count 0 2006.260.08:12:50.55#ibcon#*before return 0, iclass 30, count 0 2006.260.08:12:50.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:50.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:50.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:12:50.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:12:50.55$vc4f8/valo=6,772.99 2006.260.08:12:50.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:12:50.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:12:50.55#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:50.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:50.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:50.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:50.55#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:12:50.55#ibcon#first serial, iclass 32, count 0 2006.260.08:12:50.55#ibcon#enter sib2, iclass 32, count 0 2006.260.08:12:50.55#ibcon#flushed, iclass 32, count 0 2006.260.08:12:50.55#ibcon#about to write, iclass 32, count 0 2006.260.08:12:50.55#ibcon#wrote, iclass 32, count 0 2006.260.08:12:50.55#ibcon#about to read 3, iclass 32, count 0 2006.260.08:12:50.57#ibcon#read 3, iclass 32, count 0 2006.260.08:12:50.57#ibcon#about to read 4, iclass 32, count 0 2006.260.08:12:50.57#ibcon#read 4, iclass 32, count 0 2006.260.08:12:50.57#ibcon#about to read 5, iclass 32, count 0 2006.260.08:12:50.57#ibcon#read 5, iclass 32, count 0 2006.260.08:12:50.57#ibcon#about to read 6, iclass 32, count 0 2006.260.08:12:50.57#ibcon#read 6, iclass 32, count 0 2006.260.08:12:50.57#ibcon#end of sib2, iclass 32, count 0 2006.260.08:12:50.57#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:12:50.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:12:50.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:12:50.57#ibcon#*before write, iclass 32, count 0 2006.260.08:12:50.57#ibcon#enter sib2, iclass 32, count 0 2006.260.08:12:50.57#ibcon#flushed, iclass 32, count 0 2006.260.08:12:50.57#ibcon#about to write, iclass 32, count 0 2006.260.08:12:50.57#ibcon#wrote, iclass 32, count 0 2006.260.08:12:50.57#ibcon#about to read 3, iclass 32, count 0 2006.260.08:12:50.61#ibcon#read 3, iclass 32, count 0 2006.260.08:12:50.61#ibcon#about to read 4, iclass 32, count 0 2006.260.08:12:50.61#ibcon#read 4, iclass 32, count 0 2006.260.08:12:50.61#ibcon#about to read 5, iclass 32, count 0 2006.260.08:12:50.61#ibcon#read 5, iclass 32, count 0 2006.260.08:12:50.61#ibcon#about to read 6, iclass 32, count 0 2006.260.08:12:50.61#ibcon#read 6, iclass 32, count 0 2006.260.08:12:50.61#ibcon#end of sib2, iclass 32, count 0 2006.260.08:12:50.61#ibcon#*after write, iclass 32, count 0 2006.260.08:12:50.61#ibcon#*before return 0, iclass 32, count 0 2006.260.08:12:50.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:50.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:50.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:12:50.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:12:50.61$vc4f8/va=6,6 2006.260.08:12:50.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.08:12:50.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.08:12:50.61#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:50.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:50.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:50.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:50.67#ibcon#enter wrdev, iclass 34, count 2 2006.260.08:12:50.67#ibcon#first serial, iclass 34, count 2 2006.260.08:12:50.67#ibcon#enter sib2, iclass 34, count 2 2006.260.08:12:50.67#ibcon#flushed, iclass 34, count 2 2006.260.08:12:50.67#ibcon#about to write, iclass 34, count 2 2006.260.08:12:50.67#ibcon#wrote, iclass 34, count 2 2006.260.08:12:50.67#ibcon#about to read 3, iclass 34, count 2 2006.260.08:12:50.69#ibcon#read 3, iclass 34, count 2 2006.260.08:12:50.69#ibcon#about to read 4, iclass 34, count 2 2006.260.08:12:50.69#ibcon#read 4, iclass 34, count 2 2006.260.08:12:50.69#ibcon#about to read 5, iclass 34, count 2 2006.260.08:12:50.69#ibcon#read 5, iclass 34, count 2 2006.260.08:12:50.69#ibcon#about to read 6, iclass 34, count 2 2006.260.08:12:50.69#ibcon#read 6, iclass 34, count 2 2006.260.08:12:50.69#ibcon#end of sib2, iclass 34, count 2 2006.260.08:12:50.69#ibcon#*mode == 0, iclass 34, count 2 2006.260.08:12:50.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.08:12:50.69#ibcon#[25=AT06-06\r\n] 2006.260.08:12:50.69#ibcon#*before write, iclass 34, count 2 2006.260.08:12:50.69#ibcon#enter sib2, iclass 34, count 2 2006.260.08:12:50.69#ibcon#flushed, iclass 34, count 2 2006.260.08:12:50.69#ibcon#about to write, iclass 34, count 2 2006.260.08:12:50.69#ibcon#wrote, iclass 34, count 2 2006.260.08:12:50.69#ibcon#about to read 3, iclass 34, count 2 2006.260.08:12:50.72#ibcon#read 3, iclass 34, count 2 2006.260.08:12:50.72#ibcon#about to read 4, iclass 34, count 2 2006.260.08:12:50.72#ibcon#read 4, iclass 34, count 2 2006.260.08:12:50.72#ibcon#about to read 5, iclass 34, count 2 2006.260.08:12:50.72#ibcon#read 5, iclass 34, count 2 2006.260.08:12:50.72#ibcon#about to read 6, iclass 34, count 2 2006.260.08:12:50.72#ibcon#read 6, iclass 34, count 2 2006.260.08:12:50.72#ibcon#end of sib2, iclass 34, count 2 2006.260.08:12:50.72#ibcon#*after write, iclass 34, count 2 2006.260.08:12:50.72#ibcon#*before return 0, iclass 34, count 2 2006.260.08:12:50.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:50.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:50.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.08:12:50.72#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:50.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:12:50.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:12:50.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:12:50.84#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:12:50.84#ibcon#first serial, iclass 34, count 0 2006.260.08:12:50.84#ibcon#enter sib2, iclass 34, count 0 2006.260.08:12:50.84#ibcon#flushed, iclass 34, count 0 2006.260.08:12:50.84#ibcon#about to write, iclass 34, count 0 2006.260.08:12:50.84#ibcon#wrote, iclass 34, count 0 2006.260.08:12:50.84#ibcon#about to read 3, iclass 34, count 0 2006.260.08:12:50.86#ibcon#read 3, iclass 34, count 0 2006.260.08:12:50.86#ibcon#about to read 4, iclass 34, count 0 2006.260.08:12:50.86#ibcon#read 4, iclass 34, count 0 2006.260.08:12:50.86#ibcon#about to read 5, iclass 34, count 0 2006.260.08:12:50.86#ibcon#read 5, iclass 34, count 0 2006.260.08:12:50.86#ibcon#about to read 6, iclass 34, count 0 2006.260.08:12:50.86#ibcon#read 6, iclass 34, count 0 2006.260.08:12:50.86#ibcon#end of sib2, iclass 34, count 0 2006.260.08:12:50.86#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:12:50.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:12:50.86#ibcon#[25=USB\r\n] 2006.260.08:12:50.86#ibcon#*before write, iclass 34, count 0 2006.260.08:12:50.86#ibcon#enter sib2, iclass 34, count 0 2006.260.08:12:50.86#ibcon#flushed, iclass 34, count 0 2006.260.08:12:50.86#ibcon#about to write, iclass 34, count 0 2006.260.08:12:50.86#ibcon#wrote, iclass 34, count 0 2006.260.08:12:50.86#ibcon#about to read 3, iclass 34, count 0 2006.260.08:12:50.89#ibcon#read 3, iclass 34, count 0 2006.260.08:12:50.89#ibcon#about to read 4, iclass 34, count 0 2006.260.08:12:50.89#ibcon#read 4, iclass 34, count 0 2006.260.08:12:50.89#ibcon#about to read 5, iclass 34, count 0 2006.260.08:12:50.89#ibcon#read 5, iclass 34, count 0 2006.260.08:12:50.89#ibcon#about to read 6, iclass 34, count 0 2006.260.08:12:50.89#ibcon#read 6, iclass 34, count 0 2006.260.08:12:50.89#ibcon#end of sib2, iclass 34, count 0 2006.260.08:12:50.89#ibcon#*after write, iclass 34, count 0 2006.260.08:12:50.89#ibcon#*before return 0, iclass 34, count 0 2006.260.08:12:50.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:12:50.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:12:50.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:12:50.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:12:50.89$vc4f8/valo=7,832.99 2006.260.08:12:50.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:12:50.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:12:50.89#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:50.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:12:50.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:12:50.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:12:50.89#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:12:50.89#ibcon#first serial, iclass 36, count 0 2006.260.08:12:50.89#ibcon#enter sib2, iclass 36, count 0 2006.260.08:12:50.89#ibcon#flushed, iclass 36, count 0 2006.260.08:12:50.89#ibcon#about to write, iclass 36, count 0 2006.260.08:12:50.89#ibcon#wrote, iclass 36, count 0 2006.260.08:12:50.89#ibcon#about to read 3, iclass 36, count 0 2006.260.08:12:50.91#ibcon#read 3, iclass 36, count 0 2006.260.08:12:50.91#ibcon#about to read 4, iclass 36, count 0 2006.260.08:12:50.91#ibcon#read 4, iclass 36, count 0 2006.260.08:12:50.91#ibcon#about to read 5, iclass 36, count 0 2006.260.08:12:50.91#ibcon#read 5, iclass 36, count 0 2006.260.08:12:50.91#ibcon#about to read 6, iclass 36, count 0 2006.260.08:12:50.91#ibcon#read 6, iclass 36, count 0 2006.260.08:12:50.91#ibcon#end of sib2, iclass 36, count 0 2006.260.08:12:50.91#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:12:50.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:12:50.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:12:50.91#ibcon#*before write, iclass 36, count 0 2006.260.08:12:50.91#ibcon#enter sib2, iclass 36, count 0 2006.260.08:12:50.91#ibcon#flushed, iclass 36, count 0 2006.260.08:12:50.91#ibcon#about to write, iclass 36, count 0 2006.260.08:12:50.91#ibcon#wrote, iclass 36, count 0 2006.260.08:12:50.91#ibcon#about to read 3, iclass 36, count 0 2006.260.08:12:50.95#ibcon#read 3, iclass 36, count 0 2006.260.08:12:50.95#ibcon#about to read 4, iclass 36, count 0 2006.260.08:12:50.95#ibcon#read 4, iclass 36, count 0 2006.260.08:12:50.95#ibcon#about to read 5, iclass 36, count 0 2006.260.08:12:50.95#ibcon#read 5, iclass 36, count 0 2006.260.08:12:50.95#ibcon#about to read 6, iclass 36, count 0 2006.260.08:12:50.95#ibcon#read 6, iclass 36, count 0 2006.260.08:12:50.95#ibcon#end of sib2, iclass 36, count 0 2006.260.08:12:50.95#ibcon#*after write, iclass 36, count 0 2006.260.08:12:50.95#ibcon#*before return 0, iclass 36, count 0 2006.260.08:12:50.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:12:50.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:12:50.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:12:50.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:12:50.95$vc4f8/va=7,6 2006.260.08:12:50.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.08:12:50.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.08:12:50.95#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:50.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:12:51.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:12:51.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:12:51.01#ibcon#enter wrdev, iclass 38, count 2 2006.260.08:12:51.01#ibcon#first serial, iclass 38, count 2 2006.260.08:12:51.01#ibcon#enter sib2, iclass 38, count 2 2006.260.08:12:51.01#ibcon#flushed, iclass 38, count 2 2006.260.08:12:51.01#ibcon#about to write, iclass 38, count 2 2006.260.08:12:51.01#ibcon#wrote, iclass 38, count 2 2006.260.08:12:51.01#ibcon#about to read 3, iclass 38, count 2 2006.260.08:12:51.03#ibcon#read 3, iclass 38, count 2 2006.260.08:12:51.03#ibcon#about to read 4, iclass 38, count 2 2006.260.08:12:51.03#ibcon#read 4, iclass 38, count 2 2006.260.08:12:51.03#ibcon#about to read 5, iclass 38, count 2 2006.260.08:12:51.03#ibcon#read 5, iclass 38, count 2 2006.260.08:12:51.03#ibcon#about to read 6, iclass 38, count 2 2006.260.08:12:51.03#ibcon#read 6, iclass 38, count 2 2006.260.08:12:51.03#ibcon#end of sib2, iclass 38, count 2 2006.260.08:12:51.03#ibcon#*mode == 0, iclass 38, count 2 2006.260.08:12:51.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.08:12:51.03#ibcon#[25=AT07-06\r\n] 2006.260.08:12:51.03#ibcon#*before write, iclass 38, count 2 2006.260.08:12:51.03#ibcon#enter sib2, iclass 38, count 2 2006.260.08:12:51.03#ibcon#flushed, iclass 38, count 2 2006.260.08:12:51.03#ibcon#about to write, iclass 38, count 2 2006.260.08:12:51.03#ibcon#wrote, iclass 38, count 2 2006.260.08:12:51.03#ibcon#about to read 3, iclass 38, count 2 2006.260.08:12:51.06#ibcon#read 3, iclass 38, count 2 2006.260.08:12:51.06#ibcon#about to read 4, iclass 38, count 2 2006.260.08:12:51.06#ibcon#read 4, iclass 38, count 2 2006.260.08:12:51.06#ibcon#about to read 5, iclass 38, count 2 2006.260.08:12:51.06#ibcon#read 5, iclass 38, count 2 2006.260.08:12:51.06#ibcon#about to read 6, iclass 38, count 2 2006.260.08:12:51.06#ibcon#read 6, iclass 38, count 2 2006.260.08:12:51.06#ibcon#end of sib2, iclass 38, count 2 2006.260.08:12:51.06#ibcon#*after write, iclass 38, count 2 2006.260.08:12:51.06#ibcon#*before return 0, iclass 38, count 2 2006.260.08:12:51.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:12:51.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:12:51.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.08:12:51.06#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:51.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:12:51.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:12:51.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:12:51.18#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:12:51.18#ibcon#first serial, iclass 38, count 0 2006.260.08:12:51.18#ibcon#enter sib2, iclass 38, count 0 2006.260.08:12:51.18#ibcon#flushed, iclass 38, count 0 2006.260.08:12:51.18#ibcon#about to write, iclass 38, count 0 2006.260.08:12:51.18#ibcon#wrote, iclass 38, count 0 2006.260.08:12:51.18#ibcon#about to read 3, iclass 38, count 0 2006.260.08:12:51.20#ibcon#read 3, iclass 38, count 0 2006.260.08:12:51.20#ibcon#about to read 4, iclass 38, count 0 2006.260.08:12:51.20#ibcon#read 4, iclass 38, count 0 2006.260.08:12:51.20#ibcon#about to read 5, iclass 38, count 0 2006.260.08:12:51.20#ibcon#read 5, iclass 38, count 0 2006.260.08:12:51.20#ibcon#about to read 6, iclass 38, count 0 2006.260.08:12:51.20#ibcon#read 6, iclass 38, count 0 2006.260.08:12:51.20#ibcon#end of sib2, iclass 38, count 0 2006.260.08:12:51.20#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:12:51.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:12:51.20#ibcon#[25=USB\r\n] 2006.260.08:12:51.20#ibcon#*before write, iclass 38, count 0 2006.260.08:12:51.20#ibcon#enter sib2, iclass 38, count 0 2006.260.08:12:51.20#ibcon#flushed, iclass 38, count 0 2006.260.08:12:51.20#ibcon#about to write, iclass 38, count 0 2006.260.08:12:51.20#ibcon#wrote, iclass 38, count 0 2006.260.08:12:51.20#ibcon#about to read 3, iclass 38, count 0 2006.260.08:12:51.23#ibcon#read 3, iclass 38, count 0 2006.260.08:12:51.23#ibcon#about to read 4, iclass 38, count 0 2006.260.08:12:51.23#ibcon#read 4, iclass 38, count 0 2006.260.08:12:51.23#ibcon#about to read 5, iclass 38, count 0 2006.260.08:12:51.23#ibcon#read 5, iclass 38, count 0 2006.260.08:12:51.23#ibcon#about to read 6, iclass 38, count 0 2006.260.08:12:51.23#ibcon#read 6, iclass 38, count 0 2006.260.08:12:51.23#ibcon#end of sib2, iclass 38, count 0 2006.260.08:12:51.23#ibcon#*after write, iclass 38, count 0 2006.260.08:12:51.23#ibcon#*before return 0, iclass 38, count 0 2006.260.08:12:51.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:12:51.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:12:51.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:12:51.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:12:51.23$vc4f8/valo=8,852.99 2006.260.08:12:51.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.08:12:51.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.08:12:51.23#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:51.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:12:51.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:12:51.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:12:51.23#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:12:51.23#ibcon#first serial, iclass 40, count 0 2006.260.08:12:51.23#ibcon#enter sib2, iclass 40, count 0 2006.260.08:12:51.23#ibcon#flushed, iclass 40, count 0 2006.260.08:12:51.23#ibcon#about to write, iclass 40, count 0 2006.260.08:12:51.23#ibcon#wrote, iclass 40, count 0 2006.260.08:12:51.23#ibcon#about to read 3, iclass 40, count 0 2006.260.08:12:51.25#ibcon#read 3, iclass 40, count 0 2006.260.08:12:51.25#ibcon#about to read 4, iclass 40, count 0 2006.260.08:12:51.25#ibcon#read 4, iclass 40, count 0 2006.260.08:12:51.25#ibcon#about to read 5, iclass 40, count 0 2006.260.08:12:51.25#ibcon#read 5, iclass 40, count 0 2006.260.08:12:51.25#ibcon#about to read 6, iclass 40, count 0 2006.260.08:12:51.25#ibcon#read 6, iclass 40, count 0 2006.260.08:12:51.25#ibcon#end of sib2, iclass 40, count 0 2006.260.08:12:51.25#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:12:51.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:12:51.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:12:51.25#ibcon#*before write, iclass 40, count 0 2006.260.08:12:51.25#ibcon#enter sib2, iclass 40, count 0 2006.260.08:12:51.25#ibcon#flushed, iclass 40, count 0 2006.260.08:12:51.25#ibcon#about to write, iclass 40, count 0 2006.260.08:12:51.25#ibcon#wrote, iclass 40, count 0 2006.260.08:12:51.25#ibcon#about to read 3, iclass 40, count 0 2006.260.08:12:51.29#ibcon#read 3, iclass 40, count 0 2006.260.08:12:51.29#ibcon#about to read 4, iclass 40, count 0 2006.260.08:12:51.29#ibcon#read 4, iclass 40, count 0 2006.260.08:12:51.29#ibcon#about to read 5, iclass 40, count 0 2006.260.08:12:51.29#ibcon#read 5, iclass 40, count 0 2006.260.08:12:51.29#ibcon#about to read 6, iclass 40, count 0 2006.260.08:12:51.29#ibcon#read 6, iclass 40, count 0 2006.260.08:12:51.29#ibcon#end of sib2, iclass 40, count 0 2006.260.08:12:51.29#ibcon#*after write, iclass 40, count 0 2006.260.08:12:51.29#ibcon#*before return 0, iclass 40, count 0 2006.260.08:12:51.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:12:51.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:12:51.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:12:51.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:12:51.29$vc4f8/va=8,6 2006.260.08:12:51.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.08:12:51.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.08:12:51.29#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:51.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:12:51.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:12:51.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:12:51.35#ibcon#enter wrdev, iclass 4, count 2 2006.260.08:12:51.35#ibcon#first serial, iclass 4, count 2 2006.260.08:12:51.35#ibcon#enter sib2, iclass 4, count 2 2006.260.08:12:51.35#ibcon#flushed, iclass 4, count 2 2006.260.08:12:51.35#ibcon#about to write, iclass 4, count 2 2006.260.08:12:51.35#ibcon#wrote, iclass 4, count 2 2006.260.08:12:51.35#ibcon#about to read 3, iclass 4, count 2 2006.260.08:12:51.37#ibcon#read 3, iclass 4, count 2 2006.260.08:12:51.37#ibcon#about to read 4, iclass 4, count 2 2006.260.08:12:51.37#ibcon#read 4, iclass 4, count 2 2006.260.08:12:51.37#ibcon#about to read 5, iclass 4, count 2 2006.260.08:12:51.37#ibcon#read 5, iclass 4, count 2 2006.260.08:12:51.37#ibcon#about to read 6, iclass 4, count 2 2006.260.08:12:51.37#ibcon#read 6, iclass 4, count 2 2006.260.08:12:51.37#ibcon#end of sib2, iclass 4, count 2 2006.260.08:12:51.37#ibcon#*mode == 0, iclass 4, count 2 2006.260.08:12:51.37#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.08:12:51.37#ibcon#[25=AT08-06\r\n] 2006.260.08:12:51.37#ibcon#*before write, iclass 4, count 2 2006.260.08:12:51.37#ibcon#enter sib2, iclass 4, count 2 2006.260.08:12:51.37#ibcon#flushed, iclass 4, count 2 2006.260.08:12:51.37#ibcon#about to write, iclass 4, count 2 2006.260.08:12:51.37#ibcon#wrote, iclass 4, count 2 2006.260.08:12:51.37#ibcon#about to read 3, iclass 4, count 2 2006.260.08:12:51.40#ibcon#read 3, iclass 4, count 2 2006.260.08:12:51.40#ibcon#about to read 4, iclass 4, count 2 2006.260.08:12:51.40#ibcon#read 4, iclass 4, count 2 2006.260.08:12:51.40#ibcon#about to read 5, iclass 4, count 2 2006.260.08:12:51.40#ibcon#read 5, iclass 4, count 2 2006.260.08:12:51.40#ibcon#about to read 6, iclass 4, count 2 2006.260.08:12:51.40#ibcon#read 6, iclass 4, count 2 2006.260.08:12:51.40#ibcon#end of sib2, iclass 4, count 2 2006.260.08:12:51.40#ibcon#*after write, iclass 4, count 2 2006.260.08:12:51.40#ibcon#*before return 0, iclass 4, count 2 2006.260.08:12:51.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:12:51.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:12:51.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.08:12:51.40#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:51.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:12:51.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:12:51.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:12:51.52#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:12:51.52#ibcon#first serial, iclass 4, count 0 2006.260.08:12:51.52#ibcon#enter sib2, iclass 4, count 0 2006.260.08:12:51.52#ibcon#flushed, iclass 4, count 0 2006.260.08:12:51.52#ibcon#about to write, iclass 4, count 0 2006.260.08:12:51.52#ibcon#wrote, iclass 4, count 0 2006.260.08:12:51.52#ibcon#about to read 3, iclass 4, count 0 2006.260.08:12:51.54#ibcon#read 3, iclass 4, count 0 2006.260.08:12:51.54#ibcon#about to read 4, iclass 4, count 0 2006.260.08:12:51.54#ibcon#read 4, iclass 4, count 0 2006.260.08:12:51.54#ibcon#about to read 5, iclass 4, count 0 2006.260.08:12:51.54#ibcon#read 5, iclass 4, count 0 2006.260.08:12:51.54#ibcon#about to read 6, iclass 4, count 0 2006.260.08:12:51.54#ibcon#read 6, iclass 4, count 0 2006.260.08:12:51.54#ibcon#end of sib2, iclass 4, count 0 2006.260.08:12:51.54#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:12:51.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:12:51.54#ibcon#[25=USB\r\n] 2006.260.08:12:51.54#ibcon#*before write, iclass 4, count 0 2006.260.08:12:51.54#ibcon#enter sib2, iclass 4, count 0 2006.260.08:12:51.54#ibcon#flushed, iclass 4, count 0 2006.260.08:12:51.54#ibcon#about to write, iclass 4, count 0 2006.260.08:12:51.54#ibcon#wrote, iclass 4, count 0 2006.260.08:12:51.54#ibcon#about to read 3, iclass 4, count 0 2006.260.08:12:51.57#ibcon#read 3, iclass 4, count 0 2006.260.08:12:51.57#ibcon#about to read 4, iclass 4, count 0 2006.260.08:12:51.57#ibcon#read 4, iclass 4, count 0 2006.260.08:12:51.57#ibcon#about to read 5, iclass 4, count 0 2006.260.08:12:51.57#ibcon#read 5, iclass 4, count 0 2006.260.08:12:51.57#ibcon#about to read 6, iclass 4, count 0 2006.260.08:12:51.57#ibcon#read 6, iclass 4, count 0 2006.260.08:12:51.57#ibcon#end of sib2, iclass 4, count 0 2006.260.08:12:51.57#ibcon#*after write, iclass 4, count 0 2006.260.08:12:51.57#ibcon#*before return 0, iclass 4, count 0 2006.260.08:12:51.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:12:51.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:12:51.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:12:51.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:12:51.57$vc4f8/vblo=1,632.99 2006.260.08:12:51.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:12:51.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:12:51.57#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:51.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:12:51.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:12:51.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:12:51.57#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:12:51.57#ibcon#first serial, iclass 6, count 0 2006.260.08:12:51.57#ibcon#enter sib2, iclass 6, count 0 2006.260.08:12:51.57#ibcon#flushed, iclass 6, count 0 2006.260.08:12:51.57#ibcon#about to write, iclass 6, count 0 2006.260.08:12:51.57#ibcon#wrote, iclass 6, count 0 2006.260.08:12:51.57#ibcon#about to read 3, iclass 6, count 0 2006.260.08:12:51.59#ibcon#read 3, iclass 6, count 0 2006.260.08:12:51.59#ibcon#about to read 4, iclass 6, count 0 2006.260.08:12:51.59#ibcon#read 4, iclass 6, count 0 2006.260.08:12:51.59#ibcon#about to read 5, iclass 6, count 0 2006.260.08:12:51.59#ibcon#read 5, iclass 6, count 0 2006.260.08:12:51.59#ibcon#about to read 6, iclass 6, count 0 2006.260.08:12:51.59#ibcon#read 6, iclass 6, count 0 2006.260.08:12:51.59#ibcon#end of sib2, iclass 6, count 0 2006.260.08:12:51.59#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:12:51.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:12:51.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:12:51.59#ibcon#*before write, iclass 6, count 0 2006.260.08:12:51.59#ibcon#enter sib2, iclass 6, count 0 2006.260.08:12:51.59#ibcon#flushed, iclass 6, count 0 2006.260.08:12:51.59#ibcon#about to write, iclass 6, count 0 2006.260.08:12:51.59#ibcon#wrote, iclass 6, count 0 2006.260.08:12:51.59#ibcon#about to read 3, iclass 6, count 0 2006.260.08:12:51.63#ibcon#read 3, iclass 6, count 0 2006.260.08:12:51.63#ibcon#about to read 4, iclass 6, count 0 2006.260.08:12:51.63#ibcon#read 4, iclass 6, count 0 2006.260.08:12:51.63#ibcon#about to read 5, iclass 6, count 0 2006.260.08:12:51.63#ibcon#read 5, iclass 6, count 0 2006.260.08:12:51.63#ibcon#about to read 6, iclass 6, count 0 2006.260.08:12:51.63#ibcon#read 6, iclass 6, count 0 2006.260.08:12:51.63#ibcon#end of sib2, iclass 6, count 0 2006.260.08:12:51.63#ibcon#*after write, iclass 6, count 0 2006.260.08:12:51.63#ibcon#*before return 0, iclass 6, count 0 2006.260.08:12:51.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:12:51.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:12:51.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:12:51.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:12:51.63$vc4f8/vb=1,4 2006.260.08:12:51.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.08:12:51.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.08:12:51.63#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:51.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:12:51.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:12:51.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:12:51.63#ibcon#enter wrdev, iclass 10, count 2 2006.260.08:12:51.63#ibcon#first serial, iclass 10, count 2 2006.260.08:12:51.63#ibcon#enter sib2, iclass 10, count 2 2006.260.08:12:51.63#ibcon#flushed, iclass 10, count 2 2006.260.08:12:51.63#ibcon#about to write, iclass 10, count 2 2006.260.08:12:51.63#ibcon#wrote, iclass 10, count 2 2006.260.08:12:51.63#ibcon#about to read 3, iclass 10, count 2 2006.260.08:12:51.65#ibcon#read 3, iclass 10, count 2 2006.260.08:12:51.65#ibcon#about to read 4, iclass 10, count 2 2006.260.08:12:51.65#ibcon#read 4, iclass 10, count 2 2006.260.08:12:51.65#ibcon#about to read 5, iclass 10, count 2 2006.260.08:12:51.65#ibcon#read 5, iclass 10, count 2 2006.260.08:12:51.65#ibcon#about to read 6, iclass 10, count 2 2006.260.08:12:51.65#ibcon#read 6, iclass 10, count 2 2006.260.08:12:51.65#ibcon#end of sib2, iclass 10, count 2 2006.260.08:12:51.65#ibcon#*mode == 0, iclass 10, count 2 2006.260.08:12:51.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.08:12:51.65#ibcon#[27=AT01-04\r\n] 2006.260.08:12:51.65#ibcon#*before write, iclass 10, count 2 2006.260.08:12:51.65#ibcon#enter sib2, iclass 10, count 2 2006.260.08:12:51.65#ibcon#flushed, iclass 10, count 2 2006.260.08:12:51.65#ibcon#about to write, iclass 10, count 2 2006.260.08:12:51.65#ibcon#wrote, iclass 10, count 2 2006.260.08:12:51.65#ibcon#about to read 3, iclass 10, count 2 2006.260.08:12:51.68#ibcon#read 3, iclass 10, count 2 2006.260.08:12:51.68#ibcon#about to read 4, iclass 10, count 2 2006.260.08:12:51.68#ibcon#read 4, iclass 10, count 2 2006.260.08:12:51.68#ibcon#about to read 5, iclass 10, count 2 2006.260.08:12:51.68#ibcon#read 5, iclass 10, count 2 2006.260.08:12:51.68#ibcon#about to read 6, iclass 10, count 2 2006.260.08:12:51.68#ibcon#read 6, iclass 10, count 2 2006.260.08:12:51.68#ibcon#end of sib2, iclass 10, count 2 2006.260.08:12:51.68#ibcon#*after write, iclass 10, count 2 2006.260.08:12:51.68#ibcon#*before return 0, iclass 10, count 2 2006.260.08:12:51.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:12:51.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:12:51.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.08:12:51.68#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:51.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:12:51.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:12:51.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:12:51.80#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:12:51.80#ibcon#first serial, iclass 10, count 0 2006.260.08:12:51.80#ibcon#enter sib2, iclass 10, count 0 2006.260.08:12:51.80#ibcon#flushed, iclass 10, count 0 2006.260.08:12:51.80#ibcon#about to write, iclass 10, count 0 2006.260.08:12:51.80#ibcon#wrote, iclass 10, count 0 2006.260.08:12:51.80#ibcon#about to read 3, iclass 10, count 0 2006.260.08:12:51.82#ibcon#read 3, iclass 10, count 0 2006.260.08:12:51.82#ibcon#about to read 4, iclass 10, count 0 2006.260.08:12:51.82#ibcon#read 4, iclass 10, count 0 2006.260.08:12:51.82#ibcon#about to read 5, iclass 10, count 0 2006.260.08:12:51.82#ibcon#read 5, iclass 10, count 0 2006.260.08:12:51.82#ibcon#about to read 6, iclass 10, count 0 2006.260.08:12:51.82#ibcon#read 6, iclass 10, count 0 2006.260.08:12:51.82#ibcon#end of sib2, iclass 10, count 0 2006.260.08:12:51.82#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:12:51.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:12:51.82#ibcon#[27=USB\r\n] 2006.260.08:12:51.82#ibcon#*before write, iclass 10, count 0 2006.260.08:12:51.82#ibcon#enter sib2, iclass 10, count 0 2006.260.08:12:51.82#ibcon#flushed, iclass 10, count 0 2006.260.08:12:51.82#ibcon#about to write, iclass 10, count 0 2006.260.08:12:51.82#ibcon#wrote, iclass 10, count 0 2006.260.08:12:51.82#ibcon#about to read 3, iclass 10, count 0 2006.260.08:12:51.85#ibcon#read 3, iclass 10, count 0 2006.260.08:12:51.85#ibcon#about to read 4, iclass 10, count 0 2006.260.08:12:51.85#ibcon#read 4, iclass 10, count 0 2006.260.08:12:51.85#ibcon#about to read 5, iclass 10, count 0 2006.260.08:12:51.85#ibcon#read 5, iclass 10, count 0 2006.260.08:12:51.85#ibcon#about to read 6, iclass 10, count 0 2006.260.08:12:51.85#ibcon#read 6, iclass 10, count 0 2006.260.08:12:51.85#ibcon#end of sib2, iclass 10, count 0 2006.260.08:12:51.85#ibcon#*after write, iclass 10, count 0 2006.260.08:12:51.85#ibcon#*before return 0, iclass 10, count 0 2006.260.08:12:51.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:12:51.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:12:51.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:12:51.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:12:51.85$vc4f8/vblo=2,640.99 2006.260.08:12:51.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:12:51.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:12:51.85#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:51.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:51.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:51.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:51.85#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:12:51.85#ibcon#first serial, iclass 12, count 0 2006.260.08:12:51.85#ibcon#enter sib2, iclass 12, count 0 2006.260.08:12:51.85#ibcon#flushed, iclass 12, count 0 2006.260.08:12:51.85#ibcon#about to write, iclass 12, count 0 2006.260.08:12:51.85#ibcon#wrote, iclass 12, count 0 2006.260.08:12:51.85#ibcon#about to read 3, iclass 12, count 0 2006.260.08:12:51.87#ibcon#read 3, iclass 12, count 0 2006.260.08:12:51.87#ibcon#about to read 4, iclass 12, count 0 2006.260.08:12:51.87#ibcon#read 4, iclass 12, count 0 2006.260.08:12:51.87#ibcon#about to read 5, iclass 12, count 0 2006.260.08:12:51.87#ibcon#read 5, iclass 12, count 0 2006.260.08:12:51.87#ibcon#about to read 6, iclass 12, count 0 2006.260.08:12:51.87#ibcon#read 6, iclass 12, count 0 2006.260.08:12:51.87#ibcon#end of sib2, iclass 12, count 0 2006.260.08:12:51.87#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:12:51.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:12:51.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:12:51.87#ibcon#*before write, iclass 12, count 0 2006.260.08:12:51.87#ibcon#enter sib2, iclass 12, count 0 2006.260.08:12:51.87#ibcon#flushed, iclass 12, count 0 2006.260.08:12:51.87#ibcon#about to write, iclass 12, count 0 2006.260.08:12:51.87#ibcon#wrote, iclass 12, count 0 2006.260.08:12:51.87#ibcon#about to read 3, iclass 12, count 0 2006.260.08:12:51.91#ibcon#read 3, iclass 12, count 0 2006.260.08:12:51.91#ibcon#about to read 4, iclass 12, count 0 2006.260.08:12:51.91#ibcon#read 4, iclass 12, count 0 2006.260.08:12:51.91#ibcon#about to read 5, iclass 12, count 0 2006.260.08:12:51.91#ibcon#read 5, iclass 12, count 0 2006.260.08:12:51.91#ibcon#about to read 6, iclass 12, count 0 2006.260.08:12:51.91#ibcon#read 6, iclass 12, count 0 2006.260.08:12:51.91#ibcon#end of sib2, iclass 12, count 0 2006.260.08:12:51.91#ibcon#*after write, iclass 12, count 0 2006.260.08:12:51.91#ibcon#*before return 0, iclass 12, count 0 2006.260.08:12:51.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:51.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:12:51.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:12:51.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:12:51.91$vc4f8/vb=2,5 2006.260.08:12:51.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.08:12:51.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.08:12:51.91#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:51.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:51.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:51.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:51.97#ibcon#enter wrdev, iclass 14, count 2 2006.260.08:12:51.97#ibcon#first serial, iclass 14, count 2 2006.260.08:12:51.97#ibcon#enter sib2, iclass 14, count 2 2006.260.08:12:51.97#ibcon#flushed, iclass 14, count 2 2006.260.08:12:51.97#ibcon#about to write, iclass 14, count 2 2006.260.08:12:51.97#ibcon#wrote, iclass 14, count 2 2006.260.08:12:51.97#ibcon#about to read 3, iclass 14, count 2 2006.260.08:12:51.99#ibcon#read 3, iclass 14, count 2 2006.260.08:12:51.99#ibcon#about to read 4, iclass 14, count 2 2006.260.08:12:51.99#ibcon#read 4, iclass 14, count 2 2006.260.08:12:51.99#ibcon#about to read 5, iclass 14, count 2 2006.260.08:12:51.99#ibcon#read 5, iclass 14, count 2 2006.260.08:12:51.99#ibcon#about to read 6, iclass 14, count 2 2006.260.08:12:51.99#ibcon#read 6, iclass 14, count 2 2006.260.08:12:51.99#ibcon#end of sib2, iclass 14, count 2 2006.260.08:12:51.99#ibcon#*mode == 0, iclass 14, count 2 2006.260.08:12:51.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.08:12:51.99#ibcon#[27=AT02-05\r\n] 2006.260.08:12:51.99#ibcon#*before write, iclass 14, count 2 2006.260.08:12:51.99#ibcon#enter sib2, iclass 14, count 2 2006.260.08:12:51.99#ibcon#flushed, iclass 14, count 2 2006.260.08:12:51.99#ibcon#about to write, iclass 14, count 2 2006.260.08:12:51.99#ibcon#wrote, iclass 14, count 2 2006.260.08:12:51.99#ibcon#about to read 3, iclass 14, count 2 2006.260.08:12:52.02#ibcon#read 3, iclass 14, count 2 2006.260.08:12:52.02#ibcon#about to read 4, iclass 14, count 2 2006.260.08:12:52.02#ibcon#read 4, iclass 14, count 2 2006.260.08:12:52.02#ibcon#about to read 5, iclass 14, count 2 2006.260.08:12:52.02#ibcon#read 5, iclass 14, count 2 2006.260.08:12:52.02#ibcon#about to read 6, iclass 14, count 2 2006.260.08:12:52.02#ibcon#read 6, iclass 14, count 2 2006.260.08:12:52.02#ibcon#end of sib2, iclass 14, count 2 2006.260.08:12:52.02#ibcon#*after write, iclass 14, count 2 2006.260.08:12:52.02#ibcon#*before return 0, iclass 14, count 2 2006.260.08:12:52.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:52.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:12:52.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.08:12:52.02#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:52.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:52.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:52.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:52.14#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:12:52.14#ibcon#first serial, iclass 14, count 0 2006.260.08:12:52.14#ibcon#enter sib2, iclass 14, count 0 2006.260.08:12:52.14#ibcon#flushed, iclass 14, count 0 2006.260.08:12:52.14#ibcon#about to write, iclass 14, count 0 2006.260.08:12:52.14#ibcon#wrote, iclass 14, count 0 2006.260.08:12:52.14#ibcon#about to read 3, iclass 14, count 0 2006.260.08:12:52.16#ibcon#read 3, iclass 14, count 0 2006.260.08:12:52.16#ibcon#about to read 4, iclass 14, count 0 2006.260.08:12:52.16#ibcon#read 4, iclass 14, count 0 2006.260.08:12:52.16#ibcon#about to read 5, iclass 14, count 0 2006.260.08:12:52.16#ibcon#read 5, iclass 14, count 0 2006.260.08:12:52.16#ibcon#about to read 6, iclass 14, count 0 2006.260.08:12:52.16#ibcon#read 6, iclass 14, count 0 2006.260.08:12:52.16#ibcon#end of sib2, iclass 14, count 0 2006.260.08:12:52.16#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:12:52.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:12:52.16#ibcon#[27=USB\r\n] 2006.260.08:12:52.16#ibcon#*before write, iclass 14, count 0 2006.260.08:12:52.16#ibcon#enter sib2, iclass 14, count 0 2006.260.08:12:52.16#ibcon#flushed, iclass 14, count 0 2006.260.08:12:52.16#ibcon#about to write, iclass 14, count 0 2006.260.08:12:52.16#ibcon#wrote, iclass 14, count 0 2006.260.08:12:52.16#ibcon#about to read 3, iclass 14, count 0 2006.260.08:12:52.19#ibcon#read 3, iclass 14, count 0 2006.260.08:12:52.19#ibcon#about to read 4, iclass 14, count 0 2006.260.08:12:52.19#ibcon#read 4, iclass 14, count 0 2006.260.08:12:52.19#ibcon#about to read 5, iclass 14, count 0 2006.260.08:12:52.19#ibcon#read 5, iclass 14, count 0 2006.260.08:12:52.19#ibcon#about to read 6, iclass 14, count 0 2006.260.08:12:52.19#ibcon#read 6, iclass 14, count 0 2006.260.08:12:52.19#ibcon#end of sib2, iclass 14, count 0 2006.260.08:12:52.19#ibcon#*after write, iclass 14, count 0 2006.260.08:12:52.19#ibcon#*before return 0, iclass 14, count 0 2006.260.08:12:52.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:52.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:12:52.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:12:52.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:12:52.19$vc4f8/vblo=3,656.99 2006.260.08:12:52.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.08:12:52.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.08:12:52.19#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:52.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:52.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:52.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:52.19#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:12:52.19#ibcon#first serial, iclass 16, count 0 2006.260.08:12:52.19#ibcon#enter sib2, iclass 16, count 0 2006.260.08:12:52.19#ibcon#flushed, iclass 16, count 0 2006.260.08:12:52.19#ibcon#about to write, iclass 16, count 0 2006.260.08:12:52.19#ibcon#wrote, iclass 16, count 0 2006.260.08:12:52.19#ibcon#about to read 3, iclass 16, count 0 2006.260.08:12:52.21#ibcon#read 3, iclass 16, count 0 2006.260.08:12:52.21#ibcon#about to read 4, iclass 16, count 0 2006.260.08:12:52.21#ibcon#read 4, iclass 16, count 0 2006.260.08:12:52.21#ibcon#about to read 5, iclass 16, count 0 2006.260.08:12:52.21#ibcon#read 5, iclass 16, count 0 2006.260.08:12:52.21#ibcon#about to read 6, iclass 16, count 0 2006.260.08:12:52.21#ibcon#read 6, iclass 16, count 0 2006.260.08:12:52.21#ibcon#end of sib2, iclass 16, count 0 2006.260.08:12:52.21#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:12:52.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:12:52.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:12:52.21#ibcon#*before write, iclass 16, count 0 2006.260.08:12:52.21#ibcon#enter sib2, iclass 16, count 0 2006.260.08:12:52.21#ibcon#flushed, iclass 16, count 0 2006.260.08:12:52.21#ibcon#about to write, iclass 16, count 0 2006.260.08:12:52.21#ibcon#wrote, iclass 16, count 0 2006.260.08:12:52.21#ibcon#about to read 3, iclass 16, count 0 2006.260.08:12:52.25#ibcon#read 3, iclass 16, count 0 2006.260.08:12:52.25#ibcon#about to read 4, iclass 16, count 0 2006.260.08:12:52.25#ibcon#read 4, iclass 16, count 0 2006.260.08:12:52.25#ibcon#about to read 5, iclass 16, count 0 2006.260.08:12:52.25#ibcon#read 5, iclass 16, count 0 2006.260.08:12:52.25#ibcon#about to read 6, iclass 16, count 0 2006.260.08:12:52.25#ibcon#read 6, iclass 16, count 0 2006.260.08:12:52.25#ibcon#end of sib2, iclass 16, count 0 2006.260.08:12:52.25#ibcon#*after write, iclass 16, count 0 2006.260.08:12:52.25#ibcon#*before return 0, iclass 16, count 0 2006.260.08:12:52.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:52.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:12:52.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:12:52.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:12:52.25$vc4f8/vb=3,4 2006.260.08:12:52.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.08:12:52.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.08:12:52.25#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:52.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:52.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:52.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:52.31#ibcon#enter wrdev, iclass 18, count 2 2006.260.08:12:52.31#ibcon#first serial, iclass 18, count 2 2006.260.08:12:52.31#ibcon#enter sib2, iclass 18, count 2 2006.260.08:12:52.31#ibcon#flushed, iclass 18, count 2 2006.260.08:12:52.31#ibcon#about to write, iclass 18, count 2 2006.260.08:12:52.31#ibcon#wrote, iclass 18, count 2 2006.260.08:12:52.31#ibcon#about to read 3, iclass 18, count 2 2006.260.08:12:52.34#ibcon#read 3, iclass 18, count 2 2006.260.08:12:52.34#ibcon#about to read 4, iclass 18, count 2 2006.260.08:12:52.34#ibcon#read 4, iclass 18, count 2 2006.260.08:12:52.34#ibcon#about to read 5, iclass 18, count 2 2006.260.08:12:52.34#ibcon#read 5, iclass 18, count 2 2006.260.08:12:52.34#ibcon#about to read 6, iclass 18, count 2 2006.260.08:12:52.34#ibcon#read 6, iclass 18, count 2 2006.260.08:12:52.34#ibcon#end of sib2, iclass 18, count 2 2006.260.08:12:52.34#ibcon#*mode == 0, iclass 18, count 2 2006.260.08:12:52.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.08:12:52.34#ibcon#[27=AT03-04\r\n] 2006.260.08:12:52.34#ibcon#*before write, iclass 18, count 2 2006.260.08:12:52.34#ibcon#enter sib2, iclass 18, count 2 2006.260.08:12:52.34#ibcon#flushed, iclass 18, count 2 2006.260.08:12:52.34#ibcon#about to write, iclass 18, count 2 2006.260.08:12:52.34#ibcon#wrote, iclass 18, count 2 2006.260.08:12:52.34#ibcon#about to read 3, iclass 18, count 2 2006.260.08:12:52.37#ibcon#read 3, iclass 18, count 2 2006.260.08:12:52.37#ibcon#about to read 4, iclass 18, count 2 2006.260.08:12:52.37#ibcon#read 4, iclass 18, count 2 2006.260.08:12:52.37#ibcon#about to read 5, iclass 18, count 2 2006.260.08:12:52.37#ibcon#read 5, iclass 18, count 2 2006.260.08:12:52.37#ibcon#about to read 6, iclass 18, count 2 2006.260.08:12:52.37#ibcon#read 6, iclass 18, count 2 2006.260.08:12:52.37#ibcon#end of sib2, iclass 18, count 2 2006.260.08:12:52.37#ibcon#*after write, iclass 18, count 2 2006.260.08:12:52.37#ibcon#*before return 0, iclass 18, count 2 2006.260.08:12:52.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:52.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:12:52.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.08:12:52.37#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:52.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:52.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:52.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:52.49#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:12:52.49#ibcon#first serial, iclass 18, count 0 2006.260.08:12:52.49#ibcon#enter sib2, iclass 18, count 0 2006.260.08:12:52.49#ibcon#flushed, iclass 18, count 0 2006.260.08:12:52.49#ibcon#about to write, iclass 18, count 0 2006.260.08:12:52.49#ibcon#wrote, iclass 18, count 0 2006.260.08:12:52.49#ibcon#about to read 3, iclass 18, count 0 2006.260.08:12:52.51#ibcon#read 3, iclass 18, count 0 2006.260.08:12:52.51#ibcon#about to read 4, iclass 18, count 0 2006.260.08:12:52.51#ibcon#read 4, iclass 18, count 0 2006.260.08:12:52.51#ibcon#about to read 5, iclass 18, count 0 2006.260.08:12:52.51#ibcon#read 5, iclass 18, count 0 2006.260.08:12:52.51#ibcon#about to read 6, iclass 18, count 0 2006.260.08:12:52.51#ibcon#read 6, iclass 18, count 0 2006.260.08:12:52.51#ibcon#end of sib2, iclass 18, count 0 2006.260.08:12:52.51#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:12:52.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:12:52.51#ibcon#[27=USB\r\n] 2006.260.08:12:52.51#ibcon#*before write, iclass 18, count 0 2006.260.08:12:52.51#ibcon#enter sib2, iclass 18, count 0 2006.260.08:12:52.51#ibcon#flushed, iclass 18, count 0 2006.260.08:12:52.51#ibcon#about to write, iclass 18, count 0 2006.260.08:12:52.51#ibcon#wrote, iclass 18, count 0 2006.260.08:12:52.51#ibcon#about to read 3, iclass 18, count 0 2006.260.08:12:52.54#ibcon#read 3, iclass 18, count 0 2006.260.08:12:52.54#ibcon#about to read 4, iclass 18, count 0 2006.260.08:12:52.54#ibcon#read 4, iclass 18, count 0 2006.260.08:12:52.54#ibcon#about to read 5, iclass 18, count 0 2006.260.08:12:52.54#ibcon#read 5, iclass 18, count 0 2006.260.08:12:52.54#ibcon#about to read 6, iclass 18, count 0 2006.260.08:12:52.54#ibcon#read 6, iclass 18, count 0 2006.260.08:12:52.54#ibcon#end of sib2, iclass 18, count 0 2006.260.08:12:52.54#ibcon#*after write, iclass 18, count 0 2006.260.08:12:52.54#ibcon#*before return 0, iclass 18, count 0 2006.260.08:12:52.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:52.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:12:52.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:12:52.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:12:52.54$vc4f8/vblo=4,712.99 2006.260.08:12:52.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.08:12:52.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.08:12:52.54#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:52.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:52.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:52.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:52.54#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:12:52.54#ibcon#first serial, iclass 20, count 0 2006.260.08:12:52.54#ibcon#enter sib2, iclass 20, count 0 2006.260.08:12:52.54#ibcon#flushed, iclass 20, count 0 2006.260.08:12:52.54#ibcon#about to write, iclass 20, count 0 2006.260.08:12:52.54#ibcon#wrote, iclass 20, count 0 2006.260.08:12:52.54#ibcon#about to read 3, iclass 20, count 0 2006.260.08:12:52.56#ibcon#read 3, iclass 20, count 0 2006.260.08:12:52.56#ibcon#about to read 4, iclass 20, count 0 2006.260.08:12:52.56#ibcon#read 4, iclass 20, count 0 2006.260.08:12:52.56#ibcon#about to read 5, iclass 20, count 0 2006.260.08:12:52.56#ibcon#read 5, iclass 20, count 0 2006.260.08:12:52.56#ibcon#about to read 6, iclass 20, count 0 2006.260.08:12:52.56#ibcon#read 6, iclass 20, count 0 2006.260.08:12:52.56#ibcon#end of sib2, iclass 20, count 0 2006.260.08:12:52.56#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:12:52.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:12:52.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:12:52.56#ibcon#*before write, iclass 20, count 0 2006.260.08:12:52.56#ibcon#enter sib2, iclass 20, count 0 2006.260.08:12:52.56#ibcon#flushed, iclass 20, count 0 2006.260.08:12:52.56#ibcon#about to write, iclass 20, count 0 2006.260.08:12:52.56#ibcon#wrote, iclass 20, count 0 2006.260.08:12:52.56#ibcon#about to read 3, iclass 20, count 0 2006.260.08:12:52.60#ibcon#read 3, iclass 20, count 0 2006.260.08:12:52.60#ibcon#about to read 4, iclass 20, count 0 2006.260.08:12:52.60#ibcon#read 4, iclass 20, count 0 2006.260.08:12:52.60#ibcon#about to read 5, iclass 20, count 0 2006.260.08:12:52.60#ibcon#read 5, iclass 20, count 0 2006.260.08:12:52.60#ibcon#about to read 6, iclass 20, count 0 2006.260.08:12:52.60#ibcon#read 6, iclass 20, count 0 2006.260.08:12:52.60#ibcon#end of sib2, iclass 20, count 0 2006.260.08:12:52.60#ibcon#*after write, iclass 20, count 0 2006.260.08:12:52.60#ibcon#*before return 0, iclass 20, count 0 2006.260.08:12:52.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:52.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:12:52.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:12:52.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:12:52.60$vc4f8/vb=4,5 2006.260.08:12:52.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.08:12:52.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.08:12:52.60#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:52.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:52.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:52.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:52.66#ibcon#enter wrdev, iclass 22, count 2 2006.260.08:12:52.66#ibcon#first serial, iclass 22, count 2 2006.260.08:12:52.66#ibcon#enter sib2, iclass 22, count 2 2006.260.08:12:52.66#ibcon#flushed, iclass 22, count 2 2006.260.08:12:52.66#ibcon#about to write, iclass 22, count 2 2006.260.08:12:52.66#ibcon#wrote, iclass 22, count 2 2006.260.08:12:52.66#ibcon#about to read 3, iclass 22, count 2 2006.260.08:12:52.68#ibcon#read 3, iclass 22, count 2 2006.260.08:12:52.68#ibcon#about to read 4, iclass 22, count 2 2006.260.08:12:52.68#ibcon#read 4, iclass 22, count 2 2006.260.08:12:52.68#ibcon#about to read 5, iclass 22, count 2 2006.260.08:12:52.68#ibcon#read 5, iclass 22, count 2 2006.260.08:12:52.68#ibcon#about to read 6, iclass 22, count 2 2006.260.08:12:52.68#ibcon#read 6, iclass 22, count 2 2006.260.08:12:52.68#ibcon#end of sib2, iclass 22, count 2 2006.260.08:12:52.68#ibcon#*mode == 0, iclass 22, count 2 2006.260.08:12:52.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.08:12:52.68#ibcon#[27=AT04-05\r\n] 2006.260.08:12:52.68#ibcon#*before write, iclass 22, count 2 2006.260.08:12:52.68#ibcon#enter sib2, iclass 22, count 2 2006.260.08:12:52.68#ibcon#flushed, iclass 22, count 2 2006.260.08:12:52.68#ibcon#about to write, iclass 22, count 2 2006.260.08:12:52.68#ibcon#wrote, iclass 22, count 2 2006.260.08:12:52.68#ibcon#about to read 3, iclass 22, count 2 2006.260.08:12:52.71#ibcon#read 3, iclass 22, count 2 2006.260.08:12:52.71#ibcon#about to read 4, iclass 22, count 2 2006.260.08:12:52.71#ibcon#read 4, iclass 22, count 2 2006.260.08:12:52.71#ibcon#about to read 5, iclass 22, count 2 2006.260.08:12:52.71#ibcon#read 5, iclass 22, count 2 2006.260.08:12:52.71#ibcon#about to read 6, iclass 22, count 2 2006.260.08:12:52.71#ibcon#read 6, iclass 22, count 2 2006.260.08:12:52.71#ibcon#end of sib2, iclass 22, count 2 2006.260.08:12:52.71#ibcon#*after write, iclass 22, count 2 2006.260.08:12:52.71#ibcon#*before return 0, iclass 22, count 2 2006.260.08:12:52.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:52.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:12:52.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.08:12:52.71#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:52.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:52.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:52.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:52.83#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:12:52.83#ibcon#first serial, iclass 22, count 0 2006.260.08:12:52.83#ibcon#enter sib2, iclass 22, count 0 2006.260.08:12:52.83#ibcon#flushed, iclass 22, count 0 2006.260.08:12:52.83#ibcon#about to write, iclass 22, count 0 2006.260.08:12:52.83#ibcon#wrote, iclass 22, count 0 2006.260.08:12:52.83#ibcon#about to read 3, iclass 22, count 0 2006.260.08:12:52.85#ibcon#read 3, iclass 22, count 0 2006.260.08:12:52.85#ibcon#about to read 4, iclass 22, count 0 2006.260.08:12:52.85#ibcon#read 4, iclass 22, count 0 2006.260.08:12:52.85#ibcon#about to read 5, iclass 22, count 0 2006.260.08:12:52.85#ibcon#read 5, iclass 22, count 0 2006.260.08:12:52.85#ibcon#about to read 6, iclass 22, count 0 2006.260.08:12:52.85#ibcon#read 6, iclass 22, count 0 2006.260.08:12:52.85#ibcon#end of sib2, iclass 22, count 0 2006.260.08:12:52.85#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:12:52.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:12:52.85#ibcon#[27=USB\r\n] 2006.260.08:12:52.85#ibcon#*before write, iclass 22, count 0 2006.260.08:12:52.85#ibcon#enter sib2, iclass 22, count 0 2006.260.08:12:52.85#ibcon#flushed, iclass 22, count 0 2006.260.08:12:52.85#ibcon#about to write, iclass 22, count 0 2006.260.08:12:52.85#ibcon#wrote, iclass 22, count 0 2006.260.08:12:52.85#ibcon#about to read 3, iclass 22, count 0 2006.260.08:12:52.88#ibcon#read 3, iclass 22, count 0 2006.260.08:12:52.88#ibcon#about to read 4, iclass 22, count 0 2006.260.08:12:52.88#ibcon#read 4, iclass 22, count 0 2006.260.08:12:52.88#ibcon#about to read 5, iclass 22, count 0 2006.260.08:12:52.88#ibcon#read 5, iclass 22, count 0 2006.260.08:12:52.88#ibcon#about to read 6, iclass 22, count 0 2006.260.08:12:52.88#ibcon#read 6, iclass 22, count 0 2006.260.08:12:52.88#ibcon#end of sib2, iclass 22, count 0 2006.260.08:12:52.88#ibcon#*after write, iclass 22, count 0 2006.260.08:12:52.88#ibcon#*before return 0, iclass 22, count 0 2006.260.08:12:52.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:52.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:12:52.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:12:52.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:12:52.88$vc4f8/vblo=5,744.99 2006.260.08:12:52.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.08:12:52.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.08:12:52.88#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:52.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:52.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:52.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:52.88#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:12:52.88#ibcon#first serial, iclass 24, count 0 2006.260.08:12:52.88#ibcon#enter sib2, iclass 24, count 0 2006.260.08:12:52.88#ibcon#flushed, iclass 24, count 0 2006.260.08:12:52.88#ibcon#about to write, iclass 24, count 0 2006.260.08:12:52.88#ibcon#wrote, iclass 24, count 0 2006.260.08:12:52.88#ibcon#about to read 3, iclass 24, count 0 2006.260.08:12:52.90#ibcon#read 3, iclass 24, count 0 2006.260.08:12:52.90#ibcon#about to read 4, iclass 24, count 0 2006.260.08:12:52.90#ibcon#read 4, iclass 24, count 0 2006.260.08:12:52.90#ibcon#about to read 5, iclass 24, count 0 2006.260.08:12:52.90#ibcon#read 5, iclass 24, count 0 2006.260.08:12:52.90#ibcon#about to read 6, iclass 24, count 0 2006.260.08:12:52.90#ibcon#read 6, iclass 24, count 0 2006.260.08:12:52.90#ibcon#end of sib2, iclass 24, count 0 2006.260.08:12:52.90#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:12:52.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:12:52.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:12:52.90#ibcon#*before write, iclass 24, count 0 2006.260.08:12:52.90#ibcon#enter sib2, iclass 24, count 0 2006.260.08:12:52.90#ibcon#flushed, iclass 24, count 0 2006.260.08:12:52.90#ibcon#about to write, iclass 24, count 0 2006.260.08:12:52.90#ibcon#wrote, iclass 24, count 0 2006.260.08:12:52.90#ibcon#about to read 3, iclass 24, count 0 2006.260.08:12:52.94#ibcon#read 3, iclass 24, count 0 2006.260.08:12:52.94#ibcon#about to read 4, iclass 24, count 0 2006.260.08:12:52.94#ibcon#read 4, iclass 24, count 0 2006.260.08:12:52.94#ibcon#about to read 5, iclass 24, count 0 2006.260.08:12:52.94#ibcon#read 5, iclass 24, count 0 2006.260.08:12:52.94#ibcon#about to read 6, iclass 24, count 0 2006.260.08:12:52.94#ibcon#read 6, iclass 24, count 0 2006.260.08:12:52.94#ibcon#end of sib2, iclass 24, count 0 2006.260.08:12:52.94#ibcon#*after write, iclass 24, count 0 2006.260.08:12:52.94#ibcon#*before return 0, iclass 24, count 0 2006.260.08:12:52.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:52.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:12:52.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:12:52.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:12:52.94$vc4f8/vb=5,4 2006.260.08:12:52.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.08:12:52.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.08:12:52.94#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:52.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:53.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:53.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:53.00#ibcon#enter wrdev, iclass 26, count 2 2006.260.08:12:53.00#ibcon#first serial, iclass 26, count 2 2006.260.08:12:53.00#ibcon#enter sib2, iclass 26, count 2 2006.260.08:12:53.00#ibcon#flushed, iclass 26, count 2 2006.260.08:12:53.00#ibcon#about to write, iclass 26, count 2 2006.260.08:12:53.00#ibcon#wrote, iclass 26, count 2 2006.260.08:12:53.00#ibcon#about to read 3, iclass 26, count 2 2006.260.08:12:53.02#ibcon#read 3, iclass 26, count 2 2006.260.08:12:53.02#ibcon#about to read 4, iclass 26, count 2 2006.260.08:12:53.02#ibcon#read 4, iclass 26, count 2 2006.260.08:12:53.02#ibcon#about to read 5, iclass 26, count 2 2006.260.08:12:53.02#ibcon#read 5, iclass 26, count 2 2006.260.08:12:53.02#ibcon#about to read 6, iclass 26, count 2 2006.260.08:12:53.02#ibcon#read 6, iclass 26, count 2 2006.260.08:12:53.02#ibcon#end of sib2, iclass 26, count 2 2006.260.08:12:53.02#ibcon#*mode == 0, iclass 26, count 2 2006.260.08:12:53.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.08:12:53.02#ibcon#[27=AT05-04\r\n] 2006.260.08:12:53.02#ibcon#*before write, iclass 26, count 2 2006.260.08:12:53.02#ibcon#enter sib2, iclass 26, count 2 2006.260.08:12:53.02#ibcon#flushed, iclass 26, count 2 2006.260.08:12:53.02#ibcon#about to write, iclass 26, count 2 2006.260.08:12:53.02#ibcon#wrote, iclass 26, count 2 2006.260.08:12:53.02#ibcon#about to read 3, iclass 26, count 2 2006.260.08:12:53.05#ibcon#read 3, iclass 26, count 2 2006.260.08:12:53.05#ibcon#about to read 4, iclass 26, count 2 2006.260.08:12:53.05#ibcon#read 4, iclass 26, count 2 2006.260.08:12:53.05#ibcon#about to read 5, iclass 26, count 2 2006.260.08:12:53.05#ibcon#read 5, iclass 26, count 2 2006.260.08:12:53.05#ibcon#about to read 6, iclass 26, count 2 2006.260.08:12:53.05#ibcon#read 6, iclass 26, count 2 2006.260.08:12:53.05#ibcon#end of sib2, iclass 26, count 2 2006.260.08:12:53.05#ibcon#*after write, iclass 26, count 2 2006.260.08:12:53.05#ibcon#*before return 0, iclass 26, count 2 2006.260.08:12:53.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:53.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:12:53.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.08:12:53.05#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:53.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:53.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:53.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:53.17#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:12:53.17#ibcon#first serial, iclass 26, count 0 2006.260.08:12:53.17#ibcon#enter sib2, iclass 26, count 0 2006.260.08:12:53.17#ibcon#flushed, iclass 26, count 0 2006.260.08:12:53.17#ibcon#about to write, iclass 26, count 0 2006.260.08:12:53.17#ibcon#wrote, iclass 26, count 0 2006.260.08:12:53.17#ibcon#about to read 3, iclass 26, count 0 2006.260.08:12:53.21#ibcon#read 3, iclass 26, count 0 2006.260.08:12:53.21#ibcon#about to read 4, iclass 26, count 0 2006.260.08:12:53.21#ibcon#read 4, iclass 26, count 0 2006.260.08:12:53.21#ibcon#about to read 5, iclass 26, count 0 2006.260.08:12:53.21#ibcon#read 5, iclass 26, count 0 2006.260.08:12:53.21#ibcon#about to read 6, iclass 26, count 0 2006.260.08:12:53.21#ibcon#read 6, iclass 26, count 0 2006.260.08:12:53.21#ibcon#end of sib2, iclass 26, count 0 2006.260.08:12:53.21#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:12:53.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:12:53.21#ibcon#[27=USB\r\n] 2006.260.08:12:53.21#ibcon#*before write, iclass 26, count 0 2006.260.08:12:53.21#ibcon#enter sib2, iclass 26, count 0 2006.260.08:12:53.21#ibcon#flushed, iclass 26, count 0 2006.260.08:12:53.21#ibcon#about to write, iclass 26, count 0 2006.260.08:12:53.21#ibcon#wrote, iclass 26, count 0 2006.260.08:12:53.21#ibcon#about to read 3, iclass 26, count 0 2006.260.08:12:53.24#ibcon#read 3, iclass 26, count 0 2006.260.08:12:53.24#ibcon#about to read 4, iclass 26, count 0 2006.260.08:12:53.24#ibcon#read 4, iclass 26, count 0 2006.260.08:12:53.24#ibcon#about to read 5, iclass 26, count 0 2006.260.08:12:53.24#ibcon#read 5, iclass 26, count 0 2006.260.08:12:53.24#ibcon#about to read 6, iclass 26, count 0 2006.260.08:12:53.24#ibcon#read 6, iclass 26, count 0 2006.260.08:12:53.24#ibcon#end of sib2, iclass 26, count 0 2006.260.08:12:53.24#ibcon#*after write, iclass 26, count 0 2006.260.08:12:53.24#ibcon#*before return 0, iclass 26, count 0 2006.260.08:12:53.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:53.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:12:53.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:12:53.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:12:53.24$vc4f8/vblo=6,752.99 2006.260.08:12:53.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:12:53.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:12:53.24#ibcon#ireg 17 cls_cnt 0 2006.260.08:12:53.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:53.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:53.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:53.24#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:12:53.24#ibcon#first serial, iclass 28, count 0 2006.260.08:12:53.24#ibcon#enter sib2, iclass 28, count 0 2006.260.08:12:53.24#ibcon#flushed, iclass 28, count 0 2006.260.08:12:53.24#ibcon#about to write, iclass 28, count 0 2006.260.08:12:53.24#ibcon#wrote, iclass 28, count 0 2006.260.08:12:53.24#ibcon#about to read 3, iclass 28, count 0 2006.260.08:12:53.26#ibcon#read 3, iclass 28, count 0 2006.260.08:12:53.26#ibcon#about to read 4, iclass 28, count 0 2006.260.08:12:53.26#ibcon#read 4, iclass 28, count 0 2006.260.08:12:53.26#ibcon#about to read 5, iclass 28, count 0 2006.260.08:12:53.26#ibcon#read 5, iclass 28, count 0 2006.260.08:12:53.26#ibcon#about to read 6, iclass 28, count 0 2006.260.08:12:53.26#ibcon#read 6, iclass 28, count 0 2006.260.08:12:53.26#ibcon#end of sib2, iclass 28, count 0 2006.260.08:12:53.26#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:12:53.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:12:53.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:12:53.26#ibcon#*before write, iclass 28, count 0 2006.260.08:12:53.26#ibcon#enter sib2, iclass 28, count 0 2006.260.08:12:53.26#ibcon#flushed, iclass 28, count 0 2006.260.08:12:53.26#ibcon#about to write, iclass 28, count 0 2006.260.08:12:53.26#ibcon#wrote, iclass 28, count 0 2006.260.08:12:53.26#ibcon#about to read 3, iclass 28, count 0 2006.260.08:12:53.30#ibcon#read 3, iclass 28, count 0 2006.260.08:12:53.30#ibcon#about to read 4, iclass 28, count 0 2006.260.08:12:53.30#ibcon#read 4, iclass 28, count 0 2006.260.08:12:53.30#ibcon#about to read 5, iclass 28, count 0 2006.260.08:12:53.30#ibcon#read 5, iclass 28, count 0 2006.260.08:12:53.30#ibcon#about to read 6, iclass 28, count 0 2006.260.08:12:53.30#ibcon#read 6, iclass 28, count 0 2006.260.08:12:53.30#ibcon#end of sib2, iclass 28, count 0 2006.260.08:12:53.30#ibcon#*after write, iclass 28, count 0 2006.260.08:12:53.30#ibcon#*before return 0, iclass 28, count 0 2006.260.08:12:53.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:53.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:12:53.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:12:53.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:12:53.30$vc4f8/vb=6,4 2006.260.08:12:53.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:12:53.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:12:53.30#ibcon#ireg 11 cls_cnt 2 2006.260.08:12:53.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:53.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:53.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:53.36#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:12:53.36#ibcon#first serial, iclass 30, count 2 2006.260.08:12:53.36#ibcon#enter sib2, iclass 30, count 2 2006.260.08:12:53.36#ibcon#flushed, iclass 30, count 2 2006.260.08:12:53.36#ibcon#about to write, iclass 30, count 2 2006.260.08:12:53.36#ibcon#wrote, iclass 30, count 2 2006.260.08:12:53.36#ibcon#about to read 3, iclass 30, count 2 2006.260.08:12:53.38#ibcon#read 3, iclass 30, count 2 2006.260.08:12:53.38#ibcon#about to read 4, iclass 30, count 2 2006.260.08:12:53.38#ibcon#read 4, iclass 30, count 2 2006.260.08:12:53.38#ibcon#about to read 5, iclass 30, count 2 2006.260.08:12:53.38#ibcon#read 5, iclass 30, count 2 2006.260.08:12:53.38#ibcon#about to read 6, iclass 30, count 2 2006.260.08:12:53.38#ibcon#read 6, iclass 30, count 2 2006.260.08:12:53.38#ibcon#end of sib2, iclass 30, count 2 2006.260.08:12:53.38#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:12:53.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:12:53.38#ibcon#[27=AT06-04\r\n] 2006.260.08:12:53.38#ibcon#*before write, iclass 30, count 2 2006.260.08:12:53.38#ibcon#enter sib2, iclass 30, count 2 2006.260.08:12:53.38#ibcon#flushed, iclass 30, count 2 2006.260.08:12:53.38#ibcon#about to write, iclass 30, count 2 2006.260.08:12:53.38#ibcon#wrote, iclass 30, count 2 2006.260.08:12:53.38#ibcon#about to read 3, iclass 30, count 2 2006.260.08:12:53.41#ibcon#read 3, iclass 30, count 2 2006.260.08:12:53.41#ibcon#about to read 4, iclass 30, count 2 2006.260.08:12:53.41#ibcon#read 4, iclass 30, count 2 2006.260.08:12:53.41#ibcon#about to read 5, iclass 30, count 2 2006.260.08:12:53.41#ibcon#read 5, iclass 30, count 2 2006.260.08:12:53.41#ibcon#about to read 6, iclass 30, count 2 2006.260.08:12:53.41#ibcon#read 6, iclass 30, count 2 2006.260.08:12:53.41#ibcon#end of sib2, iclass 30, count 2 2006.260.08:12:53.41#ibcon#*after write, iclass 30, count 2 2006.260.08:12:53.41#ibcon#*before return 0, iclass 30, count 2 2006.260.08:12:53.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:53.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:12:53.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:12:53.41#ibcon#ireg 7 cls_cnt 0 2006.260.08:12:53.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:53.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:53.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:53.53#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:12:53.53#ibcon#first serial, iclass 30, count 0 2006.260.08:12:53.53#ibcon#enter sib2, iclass 30, count 0 2006.260.08:12:53.53#ibcon#flushed, iclass 30, count 0 2006.260.08:12:53.53#ibcon#about to write, iclass 30, count 0 2006.260.08:12:53.53#ibcon#wrote, iclass 30, count 0 2006.260.08:12:53.53#ibcon#about to read 3, iclass 30, count 0 2006.260.08:12:53.55#ibcon#read 3, iclass 30, count 0 2006.260.08:12:53.55#ibcon#about to read 4, iclass 30, count 0 2006.260.08:12:53.55#ibcon#read 4, iclass 30, count 0 2006.260.08:12:53.55#ibcon#about to read 5, iclass 30, count 0 2006.260.08:12:53.55#ibcon#read 5, iclass 30, count 0 2006.260.08:12:53.55#ibcon#about to read 6, iclass 30, count 0 2006.260.08:12:53.55#ibcon#read 6, iclass 30, count 0 2006.260.08:12:53.55#ibcon#end of sib2, iclass 30, count 0 2006.260.08:12:53.55#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:12:53.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:12:53.55#ibcon#[27=USB\r\n] 2006.260.08:12:53.55#ibcon#*before write, iclass 30, count 0 2006.260.08:12:53.55#ibcon#enter sib2, iclass 30, count 0 2006.260.08:12:53.55#ibcon#flushed, iclass 30, count 0 2006.260.08:12:53.55#ibcon#about to write, iclass 30, count 0 2006.260.08:12:53.55#ibcon#wrote, iclass 30, count 0 2006.260.08:12:53.55#ibcon#about to read 3, iclass 30, count 0 2006.260.08:12:53.58#ibcon#read 3, iclass 30, count 0 2006.260.08:12:53.58#ibcon#about to read 4, iclass 30, count 0 2006.260.08:12:53.58#ibcon#read 4, iclass 30, count 0 2006.260.08:12:53.58#ibcon#about to read 5, iclass 30, count 0 2006.260.08:12:53.58#ibcon#read 5, iclass 30, count 0 2006.260.08:12:53.58#ibcon#about to read 6, iclass 30, count 0 2006.260.08:12:53.58#ibcon#read 6, iclass 30, count 0 2006.260.08:12:53.58#ibcon#end of sib2, iclass 30, count 0 2006.260.08:12:53.58#ibcon#*after write, iclass 30, count 0 2006.260.08:12:53.58#ibcon#*before return 0, iclass 30, count 0 2006.260.08:12:53.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:53.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:12:53.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:12:53.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:12:53.58$vc4f8/vabw=wide 2006.260.08:12:53.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:12:53.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:12:53.58#ibcon#ireg 8 cls_cnt 0 2006.260.08:12:53.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:53.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:53.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:53.58#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:12:53.58#ibcon#first serial, iclass 32, count 0 2006.260.08:12:53.58#ibcon#enter sib2, iclass 32, count 0 2006.260.08:12:53.58#ibcon#flushed, iclass 32, count 0 2006.260.08:12:53.58#ibcon#about to write, iclass 32, count 0 2006.260.08:12:53.58#ibcon#wrote, iclass 32, count 0 2006.260.08:12:53.58#ibcon#about to read 3, iclass 32, count 0 2006.260.08:12:53.60#ibcon#read 3, iclass 32, count 0 2006.260.08:12:53.60#ibcon#about to read 4, iclass 32, count 0 2006.260.08:12:53.60#ibcon#read 4, iclass 32, count 0 2006.260.08:12:53.60#ibcon#about to read 5, iclass 32, count 0 2006.260.08:12:53.60#ibcon#read 5, iclass 32, count 0 2006.260.08:12:53.60#ibcon#about to read 6, iclass 32, count 0 2006.260.08:12:53.60#ibcon#read 6, iclass 32, count 0 2006.260.08:12:53.60#ibcon#end of sib2, iclass 32, count 0 2006.260.08:12:53.60#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:12:53.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:12:53.60#ibcon#[25=BW32\r\n] 2006.260.08:12:53.60#ibcon#*before write, iclass 32, count 0 2006.260.08:12:53.60#ibcon#enter sib2, iclass 32, count 0 2006.260.08:12:53.60#ibcon#flushed, iclass 32, count 0 2006.260.08:12:53.60#ibcon#about to write, iclass 32, count 0 2006.260.08:12:53.60#ibcon#wrote, iclass 32, count 0 2006.260.08:12:53.60#ibcon#about to read 3, iclass 32, count 0 2006.260.08:12:53.63#ibcon#read 3, iclass 32, count 0 2006.260.08:12:53.63#ibcon#about to read 4, iclass 32, count 0 2006.260.08:12:53.63#ibcon#read 4, iclass 32, count 0 2006.260.08:12:53.63#ibcon#about to read 5, iclass 32, count 0 2006.260.08:12:53.63#ibcon#read 5, iclass 32, count 0 2006.260.08:12:53.63#ibcon#about to read 6, iclass 32, count 0 2006.260.08:12:53.63#ibcon#read 6, iclass 32, count 0 2006.260.08:12:53.63#ibcon#end of sib2, iclass 32, count 0 2006.260.08:12:53.63#ibcon#*after write, iclass 32, count 0 2006.260.08:12:53.63#ibcon#*before return 0, iclass 32, count 0 2006.260.08:12:53.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:53.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:12:53.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:12:53.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:12:53.63$vc4f8/vbbw=wide 2006.260.08:12:53.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.08:12:53.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.08:12:53.63#ibcon#ireg 8 cls_cnt 0 2006.260.08:12:53.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:12:53.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:12:53.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:12:53.70#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:12:53.70#ibcon#first serial, iclass 34, count 0 2006.260.08:12:53.70#ibcon#enter sib2, iclass 34, count 0 2006.260.08:12:53.70#ibcon#flushed, iclass 34, count 0 2006.260.08:12:53.70#ibcon#about to write, iclass 34, count 0 2006.260.08:12:53.70#ibcon#wrote, iclass 34, count 0 2006.260.08:12:53.70#ibcon#about to read 3, iclass 34, count 0 2006.260.08:12:53.72#ibcon#read 3, iclass 34, count 0 2006.260.08:12:53.72#ibcon#about to read 4, iclass 34, count 0 2006.260.08:12:53.72#ibcon#read 4, iclass 34, count 0 2006.260.08:12:53.72#ibcon#about to read 5, iclass 34, count 0 2006.260.08:12:53.72#ibcon#read 5, iclass 34, count 0 2006.260.08:12:53.72#ibcon#about to read 6, iclass 34, count 0 2006.260.08:12:53.72#ibcon#read 6, iclass 34, count 0 2006.260.08:12:53.72#ibcon#end of sib2, iclass 34, count 0 2006.260.08:12:53.72#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:12:53.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:12:53.72#ibcon#[27=BW32\r\n] 2006.260.08:12:53.72#ibcon#*before write, iclass 34, count 0 2006.260.08:12:53.72#ibcon#enter sib2, iclass 34, count 0 2006.260.08:12:53.72#ibcon#flushed, iclass 34, count 0 2006.260.08:12:53.72#ibcon#about to write, iclass 34, count 0 2006.260.08:12:53.72#ibcon#wrote, iclass 34, count 0 2006.260.08:12:53.72#ibcon#about to read 3, iclass 34, count 0 2006.260.08:12:53.75#ibcon#read 3, iclass 34, count 0 2006.260.08:12:53.75#ibcon#about to read 4, iclass 34, count 0 2006.260.08:12:53.75#ibcon#read 4, iclass 34, count 0 2006.260.08:12:53.75#ibcon#about to read 5, iclass 34, count 0 2006.260.08:12:53.75#ibcon#read 5, iclass 34, count 0 2006.260.08:12:53.75#ibcon#about to read 6, iclass 34, count 0 2006.260.08:12:53.75#ibcon#read 6, iclass 34, count 0 2006.260.08:12:53.75#ibcon#end of sib2, iclass 34, count 0 2006.260.08:12:53.75#ibcon#*after write, iclass 34, count 0 2006.260.08:12:53.75#ibcon#*before return 0, iclass 34, count 0 2006.260.08:12:53.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:12:53.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:12:53.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:12:53.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:12:53.75$4f8m12a/ifd4f 2006.260.08:12:53.75$ifd4f/lo= 2006.260.08:12:53.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:12:53.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:12:53.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:12:53.75$ifd4f/patch= 2006.260.08:12:53.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:12:53.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:12:53.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:12:53.75$4f8m12a/"form=m,16.000,1:2 2006.260.08:12:53.75$4f8m12a/"tpicd 2006.260.08:12:53.75$4f8m12a/echo=off 2006.260.08:12:53.75$4f8m12a/xlog=off 2006.260.08:12:53.75:!2006.260.08:13:30 2006.260.08:13:10.14#trakl#Source acquired 2006.260.08:13:10.14#flagr#flagr/antenna,acquired 2006.260.08:13:30.00:preob 2006.260.08:13:30.14/onsource/TRACKING 2006.260.08:13:30.14:!2006.260.08:13:40 2006.260.08:13:40.00:data_valid=on 2006.260.08:13:40.00:midob 2006.260.08:13:40.14/onsource/TRACKING 2006.260.08:13:40.14/wx/22.77,1010.3,89 2006.260.08:13:40.23/cable/+6.4585E-03 2006.260.08:13:41.32/va/01,08,usb,yes,31,32 2006.260.08:13:41.32/va/02,07,usb,yes,31,32 2006.260.08:13:41.32/va/03,08,usb,yes,23,23 2006.260.08:13:41.32/va/04,07,usb,yes,32,35 2006.260.08:13:41.32/va/05,07,usb,yes,35,37 2006.260.08:13:41.32/va/06,06,usb,yes,34,34 2006.260.08:13:41.32/va/07,06,usb,yes,35,35 2006.260.08:13:41.32/va/08,06,usb,yes,38,37 2006.260.08:13:41.55/valo/01,532.99,yes,locked 2006.260.08:13:41.55/valo/02,572.99,yes,locked 2006.260.08:13:41.55/valo/03,672.99,yes,locked 2006.260.08:13:41.55/valo/04,832.99,yes,locked 2006.260.08:13:41.55/valo/05,652.99,yes,locked 2006.260.08:13:41.55/valo/06,772.99,yes,locked 2006.260.08:13:41.55/valo/07,832.99,yes,locked 2006.260.08:13:41.55/valo/08,852.99,yes,locked 2006.260.08:13:42.64/vb/01,04,usb,yes,30,29 2006.260.08:13:42.64/vb/02,05,usb,yes,28,29 2006.260.08:13:42.64/vb/03,04,usb,yes,28,32 2006.260.08:13:42.64/vb/04,05,usb,yes,26,26 2006.260.08:13:42.64/vb/05,04,usb,yes,27,31 2006.260.08:13:42.64/vb/06,04,usb,yes,28,31 2006.260.08:13:42.64/vb/07,04,usb,yes,31,30 2006.260.08:13:42.64/vb/08,04,usb,yes,28,31 2006.260.08:13:42.88/vblo/01,632.99,yes,locked 2006.260.08:13:42.88/vblo/02,640.99,yes,locked 2006.260.08:13:42.88/vblo/03,656.99,yes,locked 2006.260.08:13:42.88/vblo/04,712.99,yes,locked 2006.260.08:13:42.88/vblo/05,744.99,yes,locked 2006.260.08:13:42.88/vblo/06,752.99,yes,locked 2006.260.08:13:42.88/vblo/07,734.99,yes,locked 2006.260.08:13:42.88/vblo/08,744.99,yes,locked 2006.260.08:13:43.03/vabw/8 2006.260.08:13:43.18/vbbw/8 2006.260.08:13:43.27/xfe/off,on,15.2 2006.260.08:13:43.64/ifatt/23,28,28,28 2006.260.08:13:44.08/fmout-gps/S +4.45E-07 2006.260.08:13:44.12:!2006.260.08:14:40 2006.260.08:14:40.00:data_valid=off 2006.260.08:14:40.00:postob 2006.260.08:14:40.12/cable/+6.4582E-03 2006.260.08:14:40.12/wx/22.76,1010.3,89 2006.260.08:14:41.08/fmout-gps/S +4.45E-07 2006.260.08:14:41.08:scan_name=260-0815,k06260,60 2006.260.08:14:41.09:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.260.08:14:41.14#flagr#flagr/antenna,new-source 2006.260.08:14:42.14:checkk5 2006.260.08:14:42.61/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:14:43.03/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:14:43.42/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:14:43.80/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:14:44.31/chk_obsdata//k5ts1/T2600813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:14:44.73/chk_obsdata//k5ts2/T2600813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:14:45.25/chk_obsdata//k5ts3/T2600813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:14:45.66/chk_obsdata//k5ts4/T2600813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:14:46.65/k5log//k5ts1_log_newline 2006.260.08:14:47.38/k5log//k5ts2_log_newline 2006.260.08:14:48.13/k5log//k5ts3_log_newline 2006.260.08:14:48.94/k5log//k5ts4_log_newline 2006.260.08:14:48.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:14:48.96:4f8m12a=2 2006.260.08:14:48.96$4f8m12a/echo=on 2006.260.08:14:48.96$4f8m12a/pcalon 2006.260.08:14:48.96$pcalon/"no phase cal control is implemented here 2006.260.08:14:48.96$4f8m12a/"tpicd=stop 2006.260.08:14:48.96$4f8m12a/vc4f8 2006.260.08:14:48.96$vc4f8/valo=1,532.99 2006.260.08:14:48.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:14:48.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:14:48.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:48.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:48.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:48.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:48.97#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:14:48.97#ibcon#first serial, iclass 7, count 0 2006.260.08:14:48.97#ibcon#enter sib2, iclass 7, count 0 2006.260.08:14:48.97#ibcon#flushed, iclass 7, count 0 2006.260.08:14:48.97#ibcon#about to write, iclass 7, count 0 2006.260.08:14:48.97#ibcon#wrote, iclass 7, count 0 2006.260.08:14:48.97#ibcon#about to read 3, iclass 7, count 0 2006.260.08:14:49.01#ibcon#read 3, iclass 7, count 0 2006.260.08:14:49.01#ibcon#about to read 4, iclass 7, count 0 2006.260.08:14:49.01#ibcon#read 4, iclass 7, count 0 2006.260.08:14:49.01#ibcon#about to read 5, iclass 7, count 0 2006.260.08:14:49.01#ibcon#read 5, iclass 7, count 0 2006.260.08:14:49.01#ibcon#about to read 6, iclass 7, count 0 2006.260.08:14:49.01#ibcon#read 6, iclass 7, count 0 2006.260.08:14:49.01#ibcon#end of sib2, iclass 7, count 0 2006.260.08:14:49.01#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:14:49.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:14:49.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:14:49.01#ibcon#*before write, iclass 7, count 0 2006.260.08:14:49.01#ibcon#enter sib2, iclass 7, count 0 2006.260.08:14:49.01#ibcon#flushed, iclass 7, count 0 2006.260.08:14:49.01#ibcon#about to write, iclass 7, count 0 2006.260.08:14:49.01#ibcon#wrote, iclass 7, count 0 2006.260.08:14:49.01#ibcon#about to read 3, iclass 7, count 0 2006.260.08:14:49.06#ibcon#read 3, iclass 7, count 0 2006.260.08:14:49.06#ibcon#about to read 4, iclass 7, count 0 2006.260.08:14:49.06#ibcon#read 4, iclass 7, count 0 2006.260.08:14:49.06#ibcon#about to read 5, iclass 7, count 0 2006.260.08:14:49.06#ibcon#read 5, iclass 7, count 0 2006.260.08:14:49.06#ibcon#about to read 6, iclass 7, count 0 2006.260.08:14:49.06#ibcon#read 6, iclass 7, count 0 2006.260.08:14:49.06#ibcon#end of sib2, iclass 7, count 0 2006.260.08:14:49.06#ibcon#*after write, iclass 7, count 0 2006.260.08:14:49.06#ibcon#*before return 0, iclass 7, count 0 2006.260.08:14:49.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:49.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:49.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:14:49.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:14:49.06$vc4f8/va=1,8 2006.260.08:14:49.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:14:49.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:14:49.06#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:49.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:49.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:49.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:49.06#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:14:49.06#ibcon#first serial, iclass 11, count 2 2006.260.08:14:49.06#ibcon#enter sib2, iclass 11, count 2 2006.260.08:14:49.06#ibcon#flushed, iclass 11, count 2 2006.260.08:14:49.06#ibcon#about to write, iclass 11, count 2 2006.260.08:14:49.06#ibcon#wrote, iclass 11, count 2 2006.260.08:14:49.06#ibcon#about to read 3, iclass 11, count 2 2006.260.08:14:49.08#ibcon#read 3, iclass 11, count 2 2006.260.08:14:49.08#ibcon#about to read 4, iclass 11, count 2 2006.260.08:14:49.08#ibcon#read 4, iclass 11, count 2 2006.260.08:14:49.08#ibcon#about to read 5, iclass 11, count 2 2006.260.08:14:49.08#ibcon#read 5, iclass 11, count 2 2006.260.08:14:49.08#ibcon#about to read 6, iclass 11, count 2 2006.260.08:14:49.08#ibcon#read 6, iclass 11, count 2 2006.260.08:14:49.08#ibcon#end of sib2, iclass 11, count 2 2006.260.08:14:49.08#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:14:49.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:14:49.08#ibcon#[25=AT01-08\r\n] 2006.260.08:14:49.08#ibcon#*before write, iclass 11, count 2 2006.260.08:14:49.08#ibcon#enter sib2, iclass 11, count 2 2006.260.08:14:49.08#ibcon#flushed, iclass 11, count 2 2006.260.08:14:49.08#ibcon#about to write, iclass 11, count 2 2006.260.08:14:49.08#ibcon#wrote, iclass 11, count 2 2006.260.08:14:49.08#ibcon#about to read 3, iclass 11, count 2 2006.260.08:14:49.12#ibcon#read 3, iclass 11, count 2 2006.260.08:14:49.12#ibcon#about to read 4, iclass 11, count 2 2006.260.08:14:49.12#ibcon#read 4, iclass 11, count 2 2006.260.08:14:49.12#ibcon#about to read 5, iclass 11, count 2 2006.260.08:14:49.12#ibcon#read 5, iclass 11, count 2 2006.260.08:14:49.12#ibcon#about to read 6, iclass 11, count 2 2006.260.08:14:49.12#ibcon#read 6, iclass 11, count 2 2006.260.08:14:49.12#ibcon#end of sib2, iclass 11, count 2 2006.260.08:14:49.12#ibcon#*after write, iclass 11, count 2 2006.260.08:14:49.12#ibcon#*before return 0, iclass 11, count 2 2006.260.08:14:49.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:49.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:49.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:14:49.12#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:49.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:49.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:49.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:49.24#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:14:49.24#ibcon#first serial, iclass 11, count 0 2006.260.08:14:49.24#ibcon#enter sib2, iclass 11, count 0 2006.260.08:14:49.24#ibcon#flushed, iclass 11, count 0 2006.260.08:14:49.24#ibcon#about to write, iclass 11, count 0 2006.260.08:14:49.24#ibcon#wrote, iclass 11, count 0 2006.260.08:14:49.24#ibcon#about to read 3, iclass 11, count 0 2006.260.08:14:49.26#ibcon#read 3, iclass 11, count 0 2006.260.08:14:49.26#ibcon#about to read 4, iclass 11, count 0 2006.260.08:14:49.26#ibcon#read 4, iclass 11, count 0 2006.260.08:14:49.26#ibcon#about to read 5, iclass 11, count 0 2006.260.08:14:49.26#ibcon#read 5, iclass 11, count 0 2006.260.08:14:49.26#ibcon#about to read 6, iclass 11, count 0 2006.260.08:14:49.26#ibcon#read 6, iclass 11, count 0 2006.260.08:14:49.26#ibcon#end of sib2, iclass 11, count 0 2006.260.08:14:49.26#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:14:49.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:14:49.26#ibcon#[25=USB\r\n] 2006.260.08:14:49.26#ibcon#*before write, iclass 11, count 0 2006.260.08:14:49.26#ibcon#enter sib2, iclass 11, count 0 2006.260.08:14:49.26#ibcon#flushed, iclass 11, count 0 2006.260.08:14:49.26#ibcon#about to write, iclass 11, count 0 2006.260.08:14:49.26#ibcon#wrote, iclass 11, count 0 2006.260.08:14:49.26#ibcon#about to read 3, iclass 11, count 0 2006.260.08:14:49.29#ibcon#read 3, iclass 11, count 0 2006.260.08:14:49.29#ibcon#about to read 4, iclass 11, count 0 2006.260.08:14:49.29#ibcon#read 4, iclass 11, count 0 2006.260.08:14:49.29#ibcon#about to read 5, iclass 11, count 0 2006.260.08:14:49.29#ibcon#read 5, iclass 11, count 0 2006.260.08:14:49.29#ibcon#about to read 6, iclass 11, count 0 2006.260.08:14:49.29#ibcon#read 6, iclass 11, count 0 2006.260.08:14:49.29#ibcon#end of sib2, iclass 11, count 0 2006.260.08:14:49.29#ibcon#*after write, iclass 11, count 0 2006.260.08:14:49.29#ibcon#*before return 0, iclass 11, count 0 2006.260.08:14:49.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:49.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:49.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:14:49.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:14:49.29$vc4f8/valo=2,572.99 2006.260.08:14:49.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:14:49.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:14:49.29#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:49.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:49.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:49.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:49.29#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:14:49.29#ibcon#first serial, iclass 13, count 0 2006.260.08:14:49.29#ibcon#enter sib2, iclass 13, count 0 2006.260.08:14:49.29#ibcon#flushed, iclass 13, count 0 2006.260.08:14:49.29#ibcon#about to write, iclass 13, count 0 2006.260.08:14:49.29#ibcon#wrote, iclass 13, count 0 2006.260.08:14:49.29#ibcon#about to read 3, iclass 13, count 0 2006.260.08:14:49.31#ibcon#read 3, iclass 13, count 0 2006.260.08:14:49.31#ibcon#about to read 4, iclass 13, count 0 2006.260.08:14:49.31#ibcon#read 4, iclass 13, count 0 2006.260.08:14:49.31#ibcon#about to read 5, iclass 13, count 0 2006.260.08:14:49.31#ibcon#read 5, iclass 13, count 0 2006.260.08:14:49.31#ibcon#about to read 6, iclass 13, count 0 2006.260.08:14:49.31#ibcon#read 6, iclass 13, count 0 2006.260.08:14:49.31#ibcon#end of sib2, iclass 13, count 0 2006.260.08:14:49.31#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:14:49.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:14:49.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:14:49.31#ibcon#*before write, iclass 13, count 0 2006.260.08:14:49.31#ibcon#enter sib2, iclass 13, count 0 2006.260.08:14:49.31#ibcon#flushed, iclass 13, count 0 2006.260.08:14:49.31#ibcon#about to write, iclass 13, count 0 2006.260.08:14:49.31#ibcon#wrote, iclass 13, count 0 2006.260.08:14:49.31#ibcon#about to read 3, iclass 13, count 0 2006.260.08:14:49.35#ibcon#read 3, iclass 13, count 0 2006.260.08:14:49.35#ibcon#about to read 4, iclass 13, count 0 2006.260.08:14:49.35#ibcon#read 4, iclass 13, count 0 2006.260.08:14:49.35#ibcon#about to read 5, iclass 13, count 0 2006.260.08:14:49.35#ibcon#read 5, iclass 13, count 0 2006.260.08:14:49.35#ibcon#about to read 6, iclass 13, count 0 2006.260.08:14:49.35#ibcon#read 6, iclass 13, count 0 2006.260.08:14:49.35#ibcon#end of sib2, iclass 13, count 0 2006.260.08:14:49.35#ibcon#*after write, iclass 13, count 0 2006.260.08:14:49.35#ibcon#*before return 0, iclass 13, count 0 2006.260.08:14:49.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:49.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:49.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:14:49.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:14:49.35$vc4f8/va=2,7 2006.260.08:14:49.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:14:49.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:14:49.35#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:49.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:49.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:49.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:49.41#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:14:49.41#ibcon#first serial, iclass 15, count 2 2006.260.08:14:49.41#ibcon#enter sib2, iclass 15, count 2 2006.260.08:14:49.41#ibcon#flushed, iclass 15, count 2 2006.260.08:14:49.41#ibcon#about to write, iclass 15, count 2 2006.260.08:14:49.41#ibcon#wrote, iclass 15, count 2 2006.260.08:14:49.41#ibcon#about to read 3, iclass 15, count 2 2006.260.08:14:49.43#ibcon#read 3, iclass 15, count 2 2006.260.08:14:49.43#ibcon#about to read 4, iclass 15, count 2 2006.260.08:14:49.44#ibcon#read 4, iclass 15, count 2 2006.260.08:14:49.44#ibcon#about to read 5, iclass 15, count 2 2006.260.08:14:49.44#ibcon#read 5, iclass 15, count 2 2006.260.08:14:49.44#ibcon#about to read 6, iclass 15, count 2 2006.260.08:14:49.44#ibcon#read 6, iclass 15, count 2 2006.260.08:14:49.44#ibcon#end of sib2, iclass 15, count 2 2006.260.08:14:49.44#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:14:49.44#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:14:49.44#ibcon#[25=AT02-07\r\n] 2006.260.08:14:49.44#ibcon#*before write, iclass 15, count 2 2006.260.08:14:49.44#ibcon#enter sib2, iclass 15, count 2 2006.260.08:14:49.44#ibcon#flushed, iclass 15, count 2 2006.260.08:14:49.44#ibcon#about to write, iclass 15, count 2 2006.260.08:14:49.44#ibcon#wrote, iclass 15, count 2 2006.260.08:14:49.44#ibcon#about to read 3, iclass 15, count 2 2006.260.08:14:49.47#ibcon#read 3, iclass 15, count 2 2006.260.08:14:49.47#ibcon#about to read 4, iclass 15, count 2 2006.260.08:14:49.47#ibcon#read 4, iclass 15, count 2 2006.260.08:14:49.47#ibcon#about to read 5, iclass 15, count 2 2006.260.08:14:49.47#ibcon#read 5, iclass 15, count 2 2006.260.08:14:49.47#ibcon#about to read 6, iclass 15, count 2 2006.260.08:14:49.47#ibcon#read 6, iclass 15, count 2 2006.260.08:14:49.47#ibcon#end of sib2, iclass 15, count 2 2006.260.08:14:49.47#ibcon#*after write, iclass 15, count 2 2006.260.08:14:49.47#ibcon#*before return 0, iclass 15, count 2 2006.260.08:14:49.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:49.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:49.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:14:49.47#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:49.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:49.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:49.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:49.59#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:14:49.59#ibcon#first serial, iclass 15, count 0 2006.260.08:14:49.59#ibcon#enter sib2, iclass 15, count 0 2006.260.08:14:49.59#ibcon#flushed, iclass 15, count 0 2006.260.08:14:49.59#ibcon#about to write, iclass 15, count 0 2006.260.08:14:49.59#ibcon#wrote, iclass 15, count 0 2006.260.08:14:49.59#ibcon#about to read 3, iclass 15, count 0 2006.260.08:14:49.61#ibcon#read 3, iclass 15, count 0 2006.260.08:14:49.61#ibcon#about to read 4, iclass 15, count 0 2006.260.08:14:49.61#ibcon#read 4, iclass 15, count 0 2006.260.08:14:49.61#ibcon#about to read 5, iclass 15, count 0 2006.260.08:14:49.61#ibcon#read 5, iclass 15, count 0 2006.260.08:14:49.61#ibcon#about to read 6, iclass 15, count 0 2006.260.08:14:49.61#ibcon#read 6, iclass 15, count 0 2006.260.08:14:49.61#ibcon#end of sib2, iclass 15, count 0 2006.260.08:14:49.61#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:14:49.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:14:49.61#ibcon#[25=USB\r\n] 2006.260.08:14:49.61#ibcon#*before write, iclass 15, count 0 2006.260.08:14:49.61#ibcon#enter sib2, iclass 15, count 0 2006.260.08:14:49.61#ibcon#flushed, iclass 15, count 0 2006.260.08:14:49.61#ibcon#about to write, iclass 15, count 0 2006.260.08:14:49.61#ibcon#wrote, iclass 15, count 0 2006.260.08:14:49.61#ibcon#about to read 3, iclass 15, count 0 2006.260.08:14:49.61#abcon#<5=/04 2.9 6.0 22.76 891010.3\r\n> 2006.260.08:14:49.63#abcon#{5=INTERFACE CLEAR} 2006.260.08:14:49.64#ibcon#read 3, iclass 15, count 0 2006.260.08:14:49.64#ibcon#about to read 4, iclass 15, count 0 2006.260.08:14:49.64#ibcon#read 4, iclass 15, count 0 2006.260.08:14:49.64#ibcon#about to read 5, iclass 15, count 0 2006.260.08:14:49.64#ibcon#read 5, iclass 15, count 0 2006.260.08:14:49.64#ibcon#about to read 6, iclass 15, count 0 2006.260.08:14:49.64#ibcon#read 6, iclass 15, count 0 2006.260.08:14:49.64#ibcon#end of sib2, iclass 15, count 0 2006.260.08:14:49.64#ibcon#*after write, iclass 15, count 0 2006.260.08:14:49.64#ibcon#*before return 0, iclass 15, count 0 2006.260.08:14:49.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:49.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:49.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:14:49.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:14:49.64$vc4f8/valo=3,672.99 2006.260.08:14:49.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.08:14:49.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.08:14:49.64#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:14:49.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:14:49.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:14:49.64#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:14:49.64#ibcon#first serial, iclass 20, count 0 2006.260.08:14:49.64#ibcon#enter sib2, iclass 20, count 0 2006.260.08:14:49.64#ibcon#flushed, iclass 20, count 0 2006.260.08:14:49.64#ibcon#about to write, iclass 20, count 0 2006.260.08:14:49.64#ibcon#wrote, iclass 20, count 0 2006.260.08:14:49.64#ibcon#about to read 3, iclass 20, count 0 2006.260.08:14:49.66#ibcon#read 3, iclass 20, count 0 2006.260.08:14:49.66#ibcon#about to read 4, iclass 20, count 0 2006.260.08:14:49.66#ibcon#read 4, iclass 20, count 0 2006.260.08:14:49.66#ibcon#about to read 5, iclass 20, count 0 2006.260.08:14:49.66#ibcon#read 5, iclass 20, count 0 2006.260.08:14:49.66#ibcon#about to read 6, iclass 20, count 0 2006.260.08:14:49.66#ibcon#read 6, iclass 20, count 0 2006.260.08:14:49.66#ibcon#end of sib2, iclass 20, count 0 2006.260.08:14:49.66#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:14:49.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:14:49.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:14:49.66#ibcon#*before write, iclass 20, count 0 2006.260.08:14:49.66#ibcon#enter sib2, iclass 20, count 0 2006.260.08:14:49.66#ibcon#flushed, iclass 20, count 0 2006.260.08:14:49.66#ibcon#about to write, iclass 20, count 0 2006.260.08:14:49.66#ibcon#wrote, iclass 20, count 0 2006.260.08:14:49.66#ibcon#about to read 3, iclass 20, count 0 2006.260.08:14:49.69#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:14:49.70#ibcon#read 3, iclass 20, count 0 2006.260.08:14:49.70#ibcon#about to read 4, iclass 20, count 0 2006.260.08:14:49.70#ibcon#read 4, iclass 20, count 0 2006.260.08:14:49.70#ibcon#about to read 5, iclass 20, count 0 2006.260.08:14:49.70#ibcon#read 5, iclass 20, count 0 2006.260.08:14:49.70#ibcon#about to read 6, iclass 20, count 0 2006.260.08:14:49.70#ibcon#read 6, iclass 20, count 0 2006.260.08:14:49.70#ibcon#end of sib2, iclass 20, count 0 2006.260.08:14:49.70#ibcon#*after write, iclass 20, count 0 2006.260.08:14:49.70#ibcon#*before return 0, iclass 20, count 0 2006.260.08:14:49.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:14:49.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:14:49.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:14:49.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:14:49.70$vc4f8/va=3,8 2006.260.08:14:49.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:14:49.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:14:49.70#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:49.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:49.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:49.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:49.76#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:14:49.76#ibcon#first serial, iclass 23, count 2 2006.260.08:14:49.76#ibcon#enter sib2, iclass 23, count 2 2006.260.08:14:49.76#ibcon#flushed, iclass 23, count 2 2006.260.08:14:49.76#ibcon#about to write, iclass 23, count 2 2006.260.08:14:49.76#ibcon#wrote, iclass 23, count 2 2006.260.08:14:49.76#ibcon#about to read 3, iclass 23, count 2 2006.260.08:14:49.78#ibcon#read 3, iclass 23, count 2 2006.260.08:14:49.78#ibcon#about to read 4, iclass 23, count 2 2006.260.08:14:49.78#ibcon#read 4, iclass 23, count 2 2006.260.08:14:49.78#ibcon#about to read 5, iclass 23, count 2 2006.260.08:14:49.78#ibcon#read 5, iclass 23, count 2 2006.260.08:14:49.78#ibcon#about to read 6, iclass 23, count 2 2006.260.08:14:49.78#ibcon#read 6, iclass 23, count 2 2006.260.08:14:49.78#ibcon#end of sib2, iclass 23, count 2 2006.260.08:14:49.78#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:14:49.78#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:14:49.78#ibcon#[25=AT03-08\r\n] 2006.260.08:14:49.78#ibcon#*before write, iclass 23, count 2 2006.260.08:14:49.78#ibcon#enter sib2, iclass 23, count 2 2006.260.08:14:49.78#ibcon#flushed, iclass 23, count 2 2006.260.08:14:49.78#ibcon#about to write, iclass 23, count 2 2006.260.08:14:49.78#ibcon#wrote, iclass 23, count 2 2006.260.08:14:49.78#ibcon#about to read 3, iclass 23, count 2 2006.260.08:14:49.81#ibcon#read 3, iclass 23, count 2 2006.260.08:14:49.81#ibcon#about to read 4, iclass 23, count 2 2006.260.08:14:49.81#ibcon#read 4, iclass 23, count 2 2006.260.08:14:49.81#ibcon#about to read 5, iclass 23, count 2 2006.260.08:14:49.81#ibcon#read 5, iclass 23, count 2 2006.260.08:14:49.81#ibcon#about to read 6, iclass 23, count 2 2006.260.08:14:49.81#ibcon#read 6, iclass 23, count 2 2006.260.08:14:49.81#ibcon#end of sib2, iclass 23, count 2 2006.260.08:14:49.81#ibcon#*after write, iclass 23, count 2 2006.260.08:14:49.81#ibcon#*before return 0, iclass 23, count 2 2006.260.08:14:49.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:49.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:49.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:14:49.81#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:49.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:49.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:49.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:49.93#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:14:49.93#ibcon#first serial, iclass 23, count 0 2006.260.08:14:49.93#ibcon#enter sib2, iclass 23, count 0 2006.260.08:14:49.93#ibcon#flushed, iclass 23, count 0 2006.260.08:14:49.93#ibcon#about to write, iclass 23, count 0 2006.260.08:14:49.93#ibcon#wrote, iclass 23, count 0 2006.260.08:14:49.93#ibcon#about to read 3, iclass 23, count 0 2006.260.08:14:49.95#ibcon#read 3, iclass 23, count 0 2006.260.08:14:49.95#ibcon#about to read 4, iclass 23, count 0 2006.260.08:14:49.95#ibcon#read 4, iclass 23, count 0 2006.260.08:14:49.95#ibcon#about to read 5, iclass 23, count 0 2006.260.08:14:49.95#ibcon#read 5, iclass 23, count 0 2006.260.08:14:49.95#ibcon#about to read 6, iclass 23, count 0 2006.260.08:14:49.95#ibcon#read 6, iclass 23, count 0 2006.260.08:14:49.95#ibcon#end of sib2, iclass 23, count 0 2006.260.08:14:49.95#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:14:49.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:14:49.95#ibcon#[25=USB\r\n] 2006.260.08:14:49.95#ibcon#*before write, iclass 23, count 0 2006.260.08:14:49.95#ibcon#enter sib2, iclass 23, count 0 2006.260.08:14:49.95#ibcon#flushed, iclass 23, count 0 2006.260.08:14:49.95#ibcon#about to write, iclass 23, count 0 2006.260.08:14:49.95#ibcon#wrote, iclass 23, count 0 2006.260.08:14:49.95#ibcon#about to read 3, iclass 23, count 0 2006.260.08:14:49.98#ibcon#read 3, iclass 23, count 0 2006.260.08:14:49.98#ibcon#about to read 4, iclass 23, count 0 2006.260.08:14:49.98#ibcon#read 4, iclass 23, count 0 2006.260.08:14:49.98#ibcon#about to read 5, iclass 23, count 0 2006.260.08:14:49.98#ibcon#read 5, iclass 23, count 0 2006.260.08:14:49.98#ibcon#about to read 6, iclass 23, count 0 2006.260.08:14:49.98#ibcon#read 6, iclass 23, count 0 2006.260.08:14:49.98#ibcon#end of sib2, iclass 23, count 0 2006.260.08:14:49.98#ibcon#*after write, iclass 23, count 0 2006.260.08:14:49.98#ibcon#*before return 0, iclass 23, count 0 2006.260.08:14:49.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:49.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:49.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:14:49.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:14:49.98$vc4f8/valo=4,832.99 2006.260.08:14:49.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:14:49.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:14:49.98#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:49.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:49.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:49.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:49.98#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:14:49.98#ibcon#first serial, iclass 25, count 0 2006.260.08:14:49.98#ibcon#enter sib2, iclass 25, count 0 2006.260.08:14:49.98#ibcon#flushed, iclass 25, count 0 2006.260.08:14:49.98#ibcon#about to write, iclass 25, count 0 2006.260.08:14:49.98#ibcon#wrote, iclass 25, count 0 2006.260.08:14:49.98#ibcon#about to read 3, iclass 25, count 0 2006.260.08:14:50.00#ibcon#read 3, iclass 25, count 0 2006.260.08:14:50.00#ibcon#about to read 4, iclass 25, count 0 2006.260.08:14:50.00#ibcon#read 4, iclass 25, count 0 2006.260.08:14:50.00#ibcon#about to read 5, iclass 25, count 0 2006.260.08:14:50.00#ibcon#read 5, iclass 25, count 0 2006.260.08:14:50.00#ibcon#about to read 6, iclass 25, count 0 2006.260.08:14:50.00#ibcon#read 6, iclass 25, count 0 2006.260.08:14:50.00#ibcon#end of sib2, iclass 25, count 0 2006.260.08:14:50.00#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:14:50.00#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:14:50.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:14:50.00#ibcon#*before write, iclass 25, count 0 2006.260.08:14:50.00#ibcon#enter sib2, iclass 25, count 0 2006.260.08:14:50.00#ibcon#flushed, iclass 25, count 0 2006.260.08:14:50.00#ibcon#about to write, iclass 25, count 0 2006.260.08:14:50.00#ibcon#wrote, iclass 25, count 0 2006.260.08:14:50.00#ibcon#about to read 3, iclass 25, count 0 2006.260.08:14:50.04#ibcon#read 3, iclass 25, count 0 2006.260.08:14:50.04#ibcon#about to read 4, iclass 25, count 0 2006.260.08:14:50.04#ibcon#read 4, iclass 25, count 0 2006.260.08:14:50.04#ibcon#about to read 5, iclass 25, count 0 2006.260.08:14:50.04#ibcon#read 5, iclass 25, count 0 2006.260.08:14:50.04#ibcon#about to read 6, iclass 25, count 0 2006.260.08:14:50.04#ibcon#read 6, iclass 25, count 0 2006.260.08:14:50.04#ibcon#end of sib2, iclass 25, count 0 2006.260.08:14:50.04#ibcon#*after write, iclass 25, count 0 2006.260.08:14:50.04#ibcon#*before return 0, iclass 25, count 0 2006.260.08:14:50.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:50.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:50.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:14:50.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:14:50.04$vc4f8/va=4,7 2006.260.08:14:50.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:14:50.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:14:50.04#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:50.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:50.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:50.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:50.10#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:14:50.10#ibcon#first serial, iclass 27, count 2 2006.260.08:14:50.10#ibcon#enter sib2, iclass 27, count 2 2006.260.08:14:50.10#ibcon#flushed, iclass 27, count 2 2006.260.08:14:50.10#ibcon#about to write, iclass 27, count 2 2006.260.08:14:50.10#ibcon#wrote, iclass 27, count 2 2006.260.08:14:50.10#ibcon#about to read 3, iclass 27, count 2 2006.260.08:14:50.12#ibcon#read 3, iclass 27, count 2 2006.260.08:14:50.12#ibcon#about to read 4, iclass 27, count 2 2006.260.08:14:50.12#ibcon#read 4, iclass 27, count 2 2006.260.08:14:50.12#ibcon#about to read 5, iclass 27, count 2 2006.260.08:14:50.12#ibcon#read 5, iclass 27, count 2 2006.260.08:14:50.12#ibcon#about to read 6, iclass 27, count 2 2006.260.08:14:50.12#ibcon#read 6, iclass 27, count 2 2006.260.08:14:50.12#ibcon#end of sib2, iclass 27, count 2 2006.260.08:14:50.12#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:14:50.12#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:14:50.12#ibcon#[25=AT04-07\r\n] 2006.260.08:14:50.12#ibcon#*before write, iclass 27, count 2 2006.260.08:14:50.12#ibcon#enter sib2, iclass 27, count 2 2006.260.08:14:50.12#ibcon#flushed, iclass 27, count 2 2006.260.08:14:50.12#ibcon#about to write, iclass 27, count 2 2006.260.08:14:50.12#ibcon#wrote, iclass 27, count 2 2006.260.08:14:50.12#ibcon#about to read 3, iclass 27, count 2 2006.260.08:14:50.15#ibcon#read 3, iclass 27, count 2 2006.260.08:14:50.15#ibcon#about to read 4, iclass 27, count 2 2006.260.08:14:50.15#ibcon#read 4, iclass 27, count 2 2006.260.08:14:50.15#ibcon#about to read 5, iclass 27, count 2 2006.260.08:14:50.15#ibcon#read 5, iclass 27, count 2 2006.260.08:14:50.15#ibcon#about to read 6, iclass 27, count 2 2006.260.08:14:50.15#ibcon#read 6, iclass 27, count 2 2006.260.08:14:50.15#ibcon#end of sib2, iclass 27, count 2 2006.260.08:14:50.15#ibcon#*after write, iclass 27, count 2 2006.260.08:14:50.15#ibcon#*before return 0, iclass 27, count 2 2006.260.08:14:50.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:50.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:50.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:14:50.15#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:50.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:50.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:50.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:50.27#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:14:50.27#ibcon#first serial, iclass 27, count 0 2006.260.08:14:50.27#ibcon#enter sib2, iclass 27, count 0 2006.260.08:14:50.27#ibcon#flushed, iclass 27, count 0 2006.260.08:14:50.27#ibcon#about to write, iclass 27, count 0 2006.260.08:14:50.27#ibcon#wrote, iclass 27, count 0 2006.260.08:14:50.27#ibcon#about to read 3, iclass 27, count 0 2006.260.08:14:50.29#ibcon#read 3, iclass 27, count 0 2006.260.08:14:50.29#ibcon#about to read 4, iclass 27, count 0 2006.260.08:14:50.29#ibcon#read 4, iclass 27, count 0 2006.260.08:14:50.29#ibcon#about to read 5, iclass 27, count 0 2006.260.08:14:50.29#ibcon#read 5, iclass 27, count 0 2006.260.08:14:50.29#ibcon#about to read 6, iclass 27, count 0 2006.260.08:14:50.29#ibcon#read 6, iclass 27, count 0 2006.260.08:14:50.29#ibcon#end of sib2, iclass 27, count 0 2006.260.08:14:50.29#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:14:50.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:14:50.29#ibcon#[25=USB\r\n] 2006.260.08:14:50.29#ibcon#*before write, iclass 27, count 0 2006.260.08:14:50.29#ibcon#enter sib2, iclass 27, count 0 2006.260.08:14:50.29#ibcon#flushed, iclass 27, count 0 2006.260.08:14:50.29#ibcon#about to write, iclass 27, count 0 2006.260.08:14:50.29#ibcon#wrote, iclass 27, count 0 2006.260.08:14:50.29#ibcon#about to read 3, iclass 27, count 0 2006.260.08:14:50.32#ibcon#read 3, iclass 27, count 0 2006.260.08:14:50.32#ibcon#about to read 4, iclass 27, count 0 2006.260.08:14:50.32#ibcon#read 4, iclass 27, count 0 2006.260.08:14:50.32#ibcon#about to read 5, iclass 27, count 0 2006.260.08:14:50.32#ibcon#read 5, iclass 27, count 0 2006.260.08:14:50.32#ibcon#about to read 6, iclass 27, count 0 2006.260.08:14:50.32#ibcon#read 6, iclass 27, count 0 2006.260.08:14:50.32#ibcon#end of sib2, iclass 27, count 0 2006.260.08:14:50.32#ibcon#*after write, iclass 27, count 0 2006.260.08:14:50.32#ibcon#*before return 0, iclass 27, count 0 2006.260.08:14:50.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:50.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:50.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:14:50.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:14:50.32$vc4f8/valo=5,652.99 2006.260.08:14:50.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:14:50.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:14:50.32#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:50.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:50.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:50.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:50.32#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:14:50.32#ibcon#first serial, iclass 29, count 0 2006.260.08:14:50.32#ibcon#enter sib2, iclass 29, count 0 2006.260.08:14:50.32#ibcon#flushed, iclass 29, count 0 2006.260.08:14:50.32#ibcon#about to write, iclass 29, count 0 2006.260.08:14:50.32#ibcon#wrote, iclass 29, count 0 2006.260.08:14:50.32#ibcon#about to read 3, iclass 29, count 0 2006.260.08:14:50.34#ibcon#read 3, iclass 29, count 0 2006.260.08:14:50.34#ibcon#about to read 4, iclass 29, count 0 2006.260.08:14:50.34#ibcon#read 4, iclass 29, count 0 2006.260.08:14:50.34#ibcon#about to read 5, iclass 29, count 0 2006.260.08:14:50.34#ibcon#read 5, iclass 29, count 0 2006.260.08:14:50.34#ibcon#about to read 6, iclass 29, count 0 2006.260.08:14:50.34#ibcon#read 6, iclass 29, count 0 2006.260.08:14:50.34#ibcon#end of sib2, iclass 29, count 0 2006.260.08:14:50.34#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:14:50.34#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:14:50.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:14:50.34#ibcon#*before write, iclass 29, count 0 2006.260.08:14:50.34#ibcon#enter sib2, iclass 29, count 0 2006.260.08:14:50.34#ibcon#flushed, iclass 29, count 0 2006.260.08:14:50.34#ibcon#about to write, iclass 29, count 0 2006.260.08:14:50.34#ibcon#wrote, iclass 29, count 0 2006.260.08:14:50.34#ibcon#about to read 3, iclass 29, count 0 2006.260.08:14:50.38#ibcon#read 3, iclass 29, count 0 2006.260.08:14:50.38#ibcon#about to read 4, iclass 29, count 0 2006.260.08:14:50.38#ibcon#read 4, iclass 29, count 0 2006.260.08:14:50.38#ibcon#about to read 5, iclass 29, count 0 2006.260.08:14:50.38#ibcon#read 5, iclass 29, count 0 2006.260.08:14:50.38#ibcon#about to read 6, iclass 29, count 0 2006.260.08:14:50.38#ibcon#read 6, iclass 29, count 0 2006.260.08:14:50.38#ibcon#end of sib2, iclass 29, count 0 2006.260.08:14:50.38#ibcon#*after write, iclass 29, count 0 2006.260.08:14:50.38#ibcon#*before return 0, iclass 29, count 0 2006.260.08:14:50.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:50.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:50.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:14:50.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:14:50.38$vc4f8/va=5,7 2006.260.08:14:50.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:14:50.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:14:50.38#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:50.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:50.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:50.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:50.44#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:14:50.44#ibcon#first serial, iclass 31, count 2 2006.260.08:14:50.44#ibcon#enter sib2, iclass 31, count 2 2006.260.08:14:50.44#ibcon#flushed, iclass 31, count 2 2006.260.08:14:50.44#ibcon#about to write, iclass 31, count 2 2006.260.08:14:50.44#ibcon#wrote, iclass 31, count 2 2006.260.08:14:50.44#ibcon#about to read 3, iclass 31, count 2 2006.260.08:14:50.46#ibcon#read 3, iclass 31, count 2 2006.260.08:14:50.46#ibcon#about to read 4, iclass 31, count 2 2006.260.08:14:50.46#ibcon#read 4, iclass 31, count 2 2006.260.08:14:50.46#ibcon#about to read 5, iclass 31, count 2 2006.260.08:14:50.46#ibcon#read 5, iclass 31, count 2 2006.260.08:14:50.46#ibcon#about to read 6, iclass 31, count 2 2006.260.08:14:50.46#ibcon#read 6, iclass 31, count 2 2006.260.08:14:50.46#ibcon#end of sib2, iclass 31, count 2 2006.260.08:14:50.46#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:14:50.46#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:14:50.46#ibcon#[25=AT05-07\r\n] 2006.260.08:14:50.46#ibcon#*before write, iclass 31, count 2 2006.260.08:14:50.46#ibcon#enter sib2, iclass 31, count 2 2006.260.08:14:50.46#ibcon#flushed, iclass 31, count 2 2006.260.08:14:50.46#ibcon#about to write, iclass 31, count 2 2006.260.08:14:50.46#ibcon#wrote, iclass 31, count 2 2006.260.08:14:50.46#ibcon#about to read 3, iclass 31, count 2 2006.260.08:14:50.49#ibcon#read 3, iclass 31, count 2 2006.260.08:14:50.49#ibcon#about to read 4, iclass 31, count 2 2006.260.08:14:50.49#ibcon#read 4, iclass 31, count 2 2006.260.08:14:50.49#ibcon#about to read 5, iclass 31, count 2 2006.260.08:14:50.49#ibcon#read 5, iclass 31, count 2 2006.260.08:14:50.49#ibcon#about to read 6, iclass 31, count 2 2006.260.08:14:50.49#ibcon#read 6, iclass 31, count 2 2006.260.08:14:50.49#ibcon#end of sib2, iclass 31, count 2 2006.260.08:14:50.49#ibcon#*after write, iclass 31, count 2 2006.260.08:14:50.49#ibcon#*before return 0, iclass 31, count 2 2006.260.08:14:50.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:50.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:50.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:14:50.49#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:50.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:50.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:50.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:50.61#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:14:50.61#ibcon#first serial, iclass 31, count 0 2006.260.08:14:50.61#ibcon#enter sib2, iclass 31, count 0 2006.260.08:14:50.61#ibcon#flushed, iclass 31, count 0 2006.260.08:14:50.61#ibcon#about to write, iclass 31, count 0 2006.260.08:14:50.61#ibcon#wrote, iclass 31, count 0 2006.260.08:14:50.61#ibcon#about to read 3, iclass 31, count 0 2006.260.08:14:50.63#ibcon#read 3, iclass 31, count 0 2006.260.08:14:50.63#ibcon#about to read 4, iclass 31, count 0 2006.260.08:14:50.63#ibcon#read 4, iclass 31, count 0 2006.260.08:14:50.63#ibcon#about to read 5, iclass 31, count 0 2006.260.08:14:50.63#ibcon#read 5, iclass 31, count 0 2006.260.08:14:50.63#ibcon#about to read 6, iclass 31, count 0 2006.260.08:14:50.63#ibcon#read 6, iclass 31, count 0 2006.260.08:14:50.63#ibcon#end of sib2, iclass 31, count 0 2006.260.08:14:50.63#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:14:50.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:14:50.63#ibcon#[25=USB\r\n] 2006.260.08:14:50.63#ibcon#*before write, iclass 31, count 0 2006.260.08:14:50.63#ibcon#enter sib2, iclass 31, count 0 2006.260.08:14:50.63#ibcon#flushed, iclass 31, count 0 2006.260.08:14:50.63#ibcon#about to write, iclass 31, count 0 2006.260.08:14:50.63#ibcon#wrote, iclass 31, count 0 2006.260.08:14:50.63#ibcon#about to read 3, iclass 31, count 0 2006.260.08:14:50.66#ibcon#read 3, iclass 31, count 0 2006.260.08:14:50.66#ibcon#about to read 4, iclass 31, count 0 2006.260.08:14:50.66#ibcon#read 4, iclass 31, count 0 2006.260.08:14:50.66#ibcon#about to read 5, iclass 31, count 0 2006.260.08:14:50.66#ibcon#read 5, iclass 31, count 0 2006.260.08:14:50.66#ibcon#about to read 6, iclass 31, count 0 2006.260.08:14:50.66#ibcon#read 6, iclass 31, count 0 2006.260.08:14:50.66#ibcon#end of sib2, iclass 31, count 0 2006.260.08:14:50.66#ibcon#*after write, iclass 31, count 0 2006.260.08:14:50.66#ibcon#*before return 0, iclass 31, count 0 2006.260.08:14:50.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:50.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:50.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:14:50.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:14:50.66$vc4f8/valo=6,772.99 2006.260.08:14:50.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:14:50.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:14:50.66#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:50.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:50.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:50.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:50.66#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:14:50.66#ibcon#first serial, iclass 33, count 0 2006.260.08:14:50.66#ibcon#enter sib2, iclass 33, count 0 2006.260.08:14:50.66#ibcon#flushed, iclass 33, count 0 2006.260.08:14:50.66#ibcon#about to write, iclass 33, count 0 2006.260.08:14:50.66#ibcon#wrote, iclass 33, count 0 2006.260.08:14:50.66#ibcon#about to read 3, iclass 33, count 0 2006.260.08:14:50.68#ibcon#read 3, iclass 33, count 0 2006.260.08:14:50.68#ibcon#about to read 4, iclass 33, count 0 2006.260.08:14:50.68#ibcon#read 4, iclass 33, count 0 2006.260.08:14:50.68#ibcon#about to read 5, iclass 33, count 0 2006.260.08:14:50.68#ibcon#read 5, iclass 33, count 0 2006.260.08:14:50.68#ibcon#about to read 6, iclass 33, count 0 2006.260.08:14:50.68#ibcon#read 6, iclass 33, count 0 2006.260.08:14:50.68#ibcon#end of sib2, iclass 33, count 0 2006.260.08:14:50.68#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:14:50.68#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:14:50.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:14:50.68#ibcon#*before write, iclass 33, count 0 2006.260.08:14:50.68#ibcon#enter sib2, iclass 33, count 0 2006.260.08:14:50.68#ibcon#flushed, iclass 33, count 0 2006.260.08:14:50.68#ibcon#about to write, iclass 33, count 0 2006.260.08:14:50.68#ibcon#wrote, iclass 33, count 0 2006.260.08:14:50.68#ibcon#about to read 3, iclass 33, count 0 2006.260.08:14:50.72#ibcon#read 3, iclass 33, count 0 2006.260.08:14:50.72#ibcon#about to read 4, iclass 33, count 0 2006.260.08:14:50.72#ibcon#read 4, iclass 33, count 0 2006.260.08:14:50.72#ibcon#about to read 5, iclass 33, count 0 2006.260.08:14:50.72#ibcon#read 5, iclass 33, count 0 2006.260.08:14:50.72#ibcon#about to read 6, iclass 33, count 0 2006.260.08:14:50.72#ibcon#read 6, iclass 33, count 0 2006.260.08:14:50.72#ibcon#end of sib2, iclass 33, count 0 2006.260.08:14:50.72#ibcon#*after write, iclass 33, count 0 2006.260.08:14:50.72#ibcon#*before return 0, iclass 33, count 0 2006.260.08:14:50.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:50.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:50.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:14:50.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:14:50.72$vc4f8/va=6,6 2006.260.08:14:50.72#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:14:50.72#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:14:50.72#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:50.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:50.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:50.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:50.78#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:14:50.78#ibcon#first serial, iclass 35, count 2 2006.260.08:14:50.78#ibcon#enter sib2, iclass 35, count 2 2006.260.08:14:50.78#ibcon#flushed, iclass 35, count 2 2006.260.08:14:50.78#ibcon#about to write, iclass 35, count 2 2006.260.08:14:50.78#ibcon#wrote, iclass 35, count 2 2006.260.08:14:50.78#ibcon#about to read 3, iclass 35, count 2 2006.260.08:14:50.80#ibcon#read 3, iclass 35, count 2 2006.260.08:14:50.80#ibcon#about to read 4, iclass 35, count 2 2006.260.08:14:50.80#ibcon#read 4, iclass 35, count 2 2006.260.08:14:50.80#ibcon#about to read 5, iclass 35, count 2 2006.260.08:14:50.80#ibcon#read 5, iclass 35, count 2 2006.260.08:14:50.80#ibcon#about to read 6, iclass 35, count 2 2006.260.08:14:50.80#ibcon#read 6, iclass 35, count 2 2006.260.08:14:50.80#ibcon#end of sib2, iclass 35, count 2 2006.260.08:14:50.80#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:14:50.80#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:14:50.80#ibcon#[25=AT06-06\r\n] 2006.260.08:14:50.80#ibcon#*before write, iclass 35, count 2 2006.260.08:14:50.80#ibcon#enter sib2, iclass 35, count 2 2006.260.08:14:50.80#ibcon#flushed, iclass 35, count 2 2006.260.08:14:50.80#ibcon#about to write, iclass 35, count 2 2006.260.08:14:50.80#ibcon#wrote, iclass 35, count 2 2006.260.08:14:50.80#ibcon#about to read 3, iclass 35, count 2 2006.260.08:14:50.83#ibcon#read 3, iclass 35, count 2 2006.260.08:14:50.83#ibcon#about to read 4, iclass 35, count 2 2006.260.08:14:50.83#ibcon#read 4, iclass 35, count 2 2006.260.08:14:50.83#ibcon#about to read 5, iclass 35, count 2 2006.260.08:14:50.83#ibcon#read 5, iclass 35, count 2 2006.260.08:14:50.83#ibcon#about to read 6, iclass 35, count 2 2006.260.08:14:50.83#ibcon#read 6, iclass 35, count 2 2006.260.08:14:50.83#ibcon#end of sib2, iclass 35, count 2 2006.260.08:14:50.83#ibcon#*after write, iclass 35, count 2 2006.260.08:14:50.83#ibcon#*before return 0, iclass 35, count 2 2006.260.08:14:50.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:50.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:50.83#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:14:50.83#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:50.83#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:14:50.95#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:14:50.95#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:14:50.95#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:14:50.95#ibcon#first serial, iclass 35, count 0 2006.260.08:14:50.95#ibcon#enter sib2, iclass 35, count 0 2006.260.08:14:50.95#ibcon#flushed, iclass 35, count 0 2006.260.08:14:50.95#ibcon#about to write, iclass 35, count 0 2006.260.08:14:50.95#ibcon#wrote, iclass 35, count 0 2006.260.08:14:50.95#ibcon#about to read 3, iclass 35, count 0 2006.260.08:14:50.97#ibcon#read 3, iclass 35, count 0 2006.260.08:14:50.97#ibcon#about to read 4, iclass 35, count 0 2006.260.08:14:50.97#ibcon#read 4, iclass 35, count 0 2006.260.08:14:50.97#ibcon#about to read 5, iclass 35, count 0 2006.260.08:14:50.97#ibcon#read 5, iclass 35, count 0 2006.260.08:14:50.97#ibcon#about to read 6, iclass 35, count 0 2006.260.08:14:50.97#ibcon#read 6, iclass 35, count 0 2006.260.08:14:50.97#ibcon#end of sib2, iclass 35, count 0 2006.260.08:14:50.97#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:14:50.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:14:50.97#ibcon#[25=USB\r\n] 2006.260.08:14:50.97#ibcon#*before write, iclass 35, count 0 2006.260.08:14:50.97#ibcon#enter sib2, iclass 35, count 0 2006.260.08:14:50.97#ibcon#flushed, iclass 35, count 0 2006.260.08:14:50.97#ibcon#about to write, iclass 35, count 0 2006.260.08:14:50.97#ibcon#wrote, iclass 35, count 0 2006.260.08:14:50.97#ibcon#about to read 3, iclass 35, count 0 2006.260.08:14:51.00#ibcon#read 3, iclass 35, count 0 2006.260.08:14:51.00#ibcon#about to read 4, iclass 35, count 0 2006.260.08:14:51.00#ibcon#read 4, iclass 35, count 0 2006.260.08:14:51.00#ibcon#about to read 5, iclass 35, count 0 2006.260.08:14:51.00#ibcon#read 5, iclass 35, count 0 2006.260.08:14:51.00#ibcon#about to read 6, iclass 35, count 0 2006.260.08:14:51.00#ibcon#read 6, iclass 35, count 0 2006.260.08:14:51.00#ibcon#end of sib2, iclass 35, count 0 2006.260.08:14:51.00#ibcon#*after write, iclass 35, count 0 2006.260.08:14:51.00#ibcon#*before return 0, iclass 35, count 0 2006.260.08:14:51.00#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:14:51.00#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:14:51.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:14:51.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:14:51.00$vc4f8/valo=7,832.99 2006.260.08:14:51.00#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:14:51.00#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:14:51.00#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:51.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:14:51.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:14:51.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:14:51.00#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:14:51.00#ibcon#first serial, iclass 37, count 0 2006.260.08:14:51.00#ibcon#enter sib2, iclass 37, count 0 2006.260.08:14:51.00#ibcon#flushed, iclass 37, count 0 2006.260.08:14:51.00#ibcon#about to write, iclass 37, count 0 2006.260.08:14:51.00#ibcon#wrote, iclass 37, count 0 2006.260.08:14:51.00#ibcon#about to read 3, iclass 37, count 0 2006.260.08:14:51.02#ibcon#read 3, iclass 37, count 0 2006.260.08:14:51.02#ibcon#about to read 4, iclass 37, count 0 2006.260.08:14:51.02#ibcon#read 4, iclass 37, count 0 2006.260.08:14:51.02#ibcon#about to read 5, iclass 37, count 0 2006.260.08:14:51.02#ibcon#read 5, iclass 37, count 0 2006.260.08:14:51.02#ibcon#about to read 6, iclass 37, count 0 2006.260.08:14:51.02#ibcon#read 6, iclass 37, count 0 2006.260.08:14:51.02#ibcon#end of sib2, iclass 37, count 0 2006.260.08:14:51.02#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:14:51.02#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:14:51.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:14:51.02#ibcon#*before write, iclass 37, count 0 2006.260.08:14:51.02#ibcon#enter sib2, iclass 37, count 0 2006.260.08:14:51.02#ibcon#flushed, iclass 37, count 0 2006.260.08:14:51.02#ibcon#about to write, iclass 37, count 0 2006.260.08:14:51.02#ibcon#wrote, iclass 37, count 0 2006.260.08:14:51.02#ibcon#about to read 3, iclass 37, count 0 2006.260.08:14:51.06#ibcon#read 3, iclass 37, count 0 2006.260.08:14:51.06#ibcon#about to read 4, iclass 37, count 0 2006.260.08:14:51.06#ibcon#read 4, iclass 37, count 0 2006.260.08:14:51.06#ibcon#about to read 5, iclass 37, count 0 2006.260.08:14:51.06#ibcon#read 5, iclass 37, count 0 2006.260.08:14:51.06#ibcon#about to read 6, iclass 37, count 0 2006.260.08:14:51.06#ibcon#read 6, iclass 37, count 0 2006.260.08:14:51.06#ibcon#end of sib2, iclass 37, count 0 2006.260.08:14:51.06#ibcon#*after write, iclass 37, count 0 2006.260.08:14:51.06#ibcon#*before return 0, iclass 37, count 0 2006.260.08:14:51.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:14:51.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:14:51.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:14:51.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:14:51.06$vc4f8/va=7,6 2006.260.08:14:51.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.08:14:51.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.08:14:51.06#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:51.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:14:51.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:14:51.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:14:51.12#ibcon#enter wrdev, iclass 39, count 2 2006.260.08:14:51.12#ibcon#first serial, iclass 39, count 2 2006.260.08:14:51.12#ibcon#enter sib2, iclass 39, count 2 2006.260.08:14:51.12#ibcon#flushed, iclass 39, count 2 2006.260.08:14:51.12#ibcon#about to write, iclass 39, count 2 2006.260.08:14:51.12#ibcon#wrote, iclass 39, count 2 2006.260.08:14:51.12#ibcon#about to read 3, iclass 39, count 2 2006.260.08:14:51.14#ibcon#read 3, iclass 39, count 2 2006.260.08:14:51.14#ibcon#about to read 4, iclass 39, count 2 2006.260.08:14:51.14#ibcon#read 4, iclass 39, count 2 2006.260.08:14:51.14#ibcon#about to read 5, iclass 39, count 2 2006.260.08:14:51.14#ibcon#read 5, iclass 39, count 2 2006.260.08:14:51.14#ibcon#about to read 6, iclass 39, count 2 2006.260.08:14:51.14#ibcon#read 6, iclass 39, count 2 2006.260.08:14:51.14#ibcon#end of sib2, iclass 39, count 2 2006.260.08:14:51.14#ibcon#*mode == 0, iclass 39, count 2 2006.260.08:14:51.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.08:14:51.14#ibcon#[25=AT07-06\r\n] 2006.260.08:14:51.14#ibcon#*before write, iclass 39, count 2 2006.260.08:14:51.14#ibcon#enter sib2, iclass 39, count 2 2006.260.08:14:51.14#ibcon#flushed, iclass 39, count 2 2006.260.08:14:51.14#ibcon#about to write, iclass 39, count 2 2006.260.08:14:51.14#ibcon#wrote, iclass 39, count 2 2006.260.08:14:51.14#ibcon#about to read 3, iclass 39, count 2 2006.260.08:14:51.17#ibcon#read 3, iclass 39, count 2 2006.260.08:14:51.17#ibcon#about to read 4, iclass 39, count 2 2006.260.08:14:51.17#ibcon#read 4, iclass 39, count 2 2006.260.08:14:51.17#ibcon#about to read 5, iclass 39, count 2 2006.260.08:14:51.17#ibcon#read 5, iclass 39, count 2 2006.260.08:14:51.17#ibcon#about to read 6, iclass 39, count 2 2006.260.08:14:51.17#ibcon#read 6, iclass 39, count 2 2006.260.08:14:51.17#ibcon#end of sib2, iclass 39, count 2 2006.260.08:14:51.17#ibcon#*after write, iclass 39, count 2 2006.260.08:14:51.17#ibcon#*before return 0, iclass 39, count 2 2006.260.08:14:51.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:14:51.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:14:51.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.08:14:51.17#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:51.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:14:51.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:14:51.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:14:51.29#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:14:51.29#ibcon#first serial, iclass 39, count 0 2006.260.08:14:51.29#ibcon#enter sib2, iclass 39, count 0 2006.260.08:14:51.29#ibcon#flushed, iclass 39, count 0 2006.260.08:14:51.29#ibcon#about to write, iclass 39, count 0 2006.260.08:14:51.29#ibcon#wrote, iclass 39, count 0 2006.260.08:14:51.29#ibcon#about to read 3, iclass 39, count 0 2006.260.08:14:51.31#ibcon#read 3, iclass 39, count 0 2006.260.08:14:51.31#ibcon#about to read 4, iclass 39, count 0 2006.260.08:14:51.31#ibcon#read 4, iclass 39, count 0 2006.260.08:14:51.31#ibcon#about to read 5, iclass 39, count 0 2006.260.08:14:51.31#ibcon#read 5, iclass 39, count 0 2006.260.08:14:51.31#ibcon#about to read 6, iclass 39, count 0 2006.260.08:14:51.31#ibcon#read 6, iclass 39, count 0 2006.260.08:14:51.31#ibcon#end of sib2, iclass 39, count 0 2006.260.08:14:51.31#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:14:51.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:14:51.31#ibcon#[25=USB\r\n] 2006.260.08:14:51.31#ibcon#*before write, iclass 39, count 0 2006.260.08:14:51.31#ibcon#enter sib2, iclass 39, count 0 2006.260.08:14:51.31#ibcon#flushed, iclass 39, count 0 2006.260.08:14:51.31#ibcon#about to write, iclass 39, count 0 2006.260.08:14:51.31#ibcon#wrote, iclass 39, count 0 2006.260.08:14:51.31#ibcon#about to read 3, iclass 39, count 0 2006.260.08:14:51.34#ibcon#read 3, iclass 39, count 0 2006.260.08:14:51.34#ibcon#about to read 4, iclass 39, count 0 2006.260.08:14:51.34#ibcon#read 4, iclass 39, count 0 2006.260.08:14:51.34#ibcon#about to read 5, iclass 39, count 0 2006.260.08:14:51.34#ibcon#read 5, iclass 39, count 0 2006.260.08:14:51.34#ibcon#about to read 6, iclass 39, count 0 2006.260.08:14:51.34#ibcon#read 6, iclass 39, count 0 2006.260.08:14:51.34#ibcon#end of sib2, iclass 39, count 0 2006.260.08:14:51.34#ibcon#*after write, iclass 39, count 0 2006.260.08:14:51.34#ibcon#*before return 0, iclass 39, count 0 2006.260.08:14:51.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:14:51.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:14:51.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:14:51.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:14:51.34$vc4f8/valo=8,852.99 2006.260.08:14:51.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.08:14:51.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.08:14:51.34#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:51.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:14:51.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:14:51.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:14:51.34#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:14:51.34#ibcon#first serial, iclass 3, count 0 2006.260.08:14:51.34#ibcon#enter sib2, iclass 3, count 0 2006.260.08:14:51.34#ibcon#flushed, iclass 3, count 0 2006.260.08:14:51.34#ibcon#about to write, iclass 3, count 0 2006.260.08:14:51.34#ibcon#wrote, iclass 3, count 0 2006.260.08:14:51.34#ibcon#about to read 3, iclass 3, count 0 2006.260.08:14:51.36#ibcon#read 3, iclass 3, count 0 2006.260.08:14:51.36#ibcon#about to read 4, iclass 3, count 0 2006.260.08:14:51.36#ibcon#read 4, iclass 3, count 0 2006.260.08:14:51.36#ibcon#about to read 5, iclass 3, count 0 2006.260.08:14:51.36#ibcon#read 5, iclass 3, count 0 2006.260.08:14:51.36#ibcon#about to read 6, iclass 3, count 0 2006.260.08:14:51.36#ibcon#read 6, iclass 3, count 0 2006.260.08:14:51.36#ibcon#end of sib2, iclass 3, count 0 2006.260.08:14:51.36#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:14:51.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:14:51.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:14:51.36#ibcon#*before write, iclass 3, count 0 2006.260.08:14:51.36#ibcon#enter sib2, iclass 3, count 0 2006.260.08:14:51.36#ibcon#flushed, iclass 3, count 0 2006.260.08:14:51.36#ibcon#about to write, iclass 3, count 0 2006.260.08:14:51.36#ibcon#wrote, iclass 3, count 0 2006.260.08:14:51.36#ibcon#about to read 3, iclass 3, count 0 2006.260.08:14:51.40#ibcon#read 3, iclass 3, count 0 2006.260.08:14:51.40#ibcon#about to read 4, iclass 3, count 0 2006.260.08:14:51.40#ibcon#read 4, iclass 3, count 0 2006.260.08:14:51.40#ibcon#about to read 5, iclass 3, count 0 2006.260.08:14:51.40#ibcon#read 5, iclass 3, count 0 2006.260.08:14:51.40#ibcon#about to read 6, iclass 3, count 0 2006.260.08:14:51.40#ibcon#read 6, iclass 3, count 0 2006.260.08:14:51.40#ibcon#end of sib2, iclass 3, count 0 2006.260.08:14:51.40#ibcon#*after write, iclass 3, count 0 2006.260.08:14:51.40#ibcon#*before return 0, iclass 3, count 0 2006.260.08:14:51.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:14:51.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:14:51.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:14:51.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:14:51.40$vc4f8/va=8,6 2006.260.08:14:51.40#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.08:14:51.40#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.08:14:51.40#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:51.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:14:51.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:14:51.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:14:51.46#ibcon#enter wrdev, iclass 5, count 2 2006.260.08:14:51.46#ibcon#first serial, iclass 5, count 2 2006.260.08:14:51.46#ibcon#enter sib2, iclass 5, count 2 2006.260.08:14:51.46#ibcon#flushed, iclass 5, count 2 2006.260.08:14:51.46#ibcon#about to write, iclass 5, count 2 2006.260.08:14:51.46#ibcon#wrote, iclass 5, count 2 2006.260.08:14:51.46#ibcon#about to read 3, iclass 5, count 2 2006.260.08:14:51.49#ibcon#read 3, iclass 5, count 2 2006.260.08:14:51.49#ibcon#about to read 4, iclass 5, count 2 2006.260.08:14:51.49#ibcon#read 4, iclass 5, count 2 2006.260.08:14:51.49#ibcon#about to read 5, iclass 5, count 2 2006.260.08:14:51.49#ibcon#read 5, iclass 5, count 2 2006.260.08:14:51.49#ibcon#about to read 6, iclass 5, count 2 2006.260.08:14:51.49#ibcon#read 6, iclass 5, count 2 2006.260.08:14:51.49#ibcon#end of sib2, iclass 5, count 2 2006.260.08:14:51.49#ibcon#*mode == 0, iclass 5, count 2 2006.260.08:14:51.49#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.08:14:51.49#ibcon#[25=AT08-06\r\n] 2006.260.08:14:51.49#ibcon#*before write, iclass 5, count 2 2006.260.08:14:51.49#ibcon#enter sib2, iclass 5, count 2 2006.260.08:14:51.49#ibcon#flushed, iclass 5, count 2 2006.260.08:14:51.49#ibcon#about to write, iclass 5, count 2 2006.260.08:14:51.49#ibcon#wrote, iclass 5, count 2 2006.260.08:14:51.49#ibcon#about to read 3, iclass 5, count 2 2006.260.08:14:51.52#ibcon#read 3, iclass 5, count 2 2006.260.08:14:51.52#ibcon#about to read 4, iclass 5, count 2 2006.260.08:14:51.52#ibcon#read 4, iclass 5, count 2 2006.260.08:14:51.52#ibcon#about to read 5, iclass 5, count 2 2006.260.08:14:51.52#ibcon#read 5, iclass 5, count 2 2006.260.08:14:51.52#ibcon#about to read 6, iclass 5, count 2 2006.260.08:14:51.52#ibcon#read 6, iclass 5, count 2 2006.260.08:14:51.52#ibcon#end of sib2, iclass 5, count 2 2006.260.08:14:51.52#ibcon#*after write, iclass 5, count 2 2006.260.08:14:51.52#ibcon#*before return 0, iclass 5, count 2 2006.260.08:14:51.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:14:51.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:14:51.52#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.08:14:51.52#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:51.52#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:14:51.64#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:14:51.64#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:14:51.64#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:14:51.64#ibcon#first serial, iclass 5, count 0 2006.260.08:14:51.64#ibcon#enter sib2, iclass 5, count 0 2006.260.08:14:51.64#ibcon#flushed, iclass 5, count 0 2006.260.08:14:51.64#ibcon#about to write, iclass 5, count 0 2006.260.08:14:51.64#ibcon#wrote, iclass 5, count 0 2006.260.08:14:51.64#ibcon#about to read 3, iclass 5, count 0 2006.260.08:14:51.66#ibcon#read 3, iclass 5, count 0 2006.260.08:14:51.66#ibcon#about to read 4, iclass 5, count 0 2006.260.08:14:51.66#ibcon#read 4, iclass 5, count 0 2006.260.08:14:51.66#ibcon#about to read 5, iclass 5, count 0 2006.260.08:14:51.66#ibcon#read 5, iclass 5, count 0 2006.260.08:14:51.66#ibcon#about to read 6, iclass 5, count 0 2006.260.08:14:51.66#ibcon#read 6, iclass 5, count 0 2006.260.08:14:51.66#ibcon#end of sib2, iclass 5, count 0 2006.260.08:14:51.66#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:14:51.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:14:51.66#ibcon#[25=USB\r\n] 2006.260.08:14:51.66#ibcon#*before write, iclass 5, count 0 2006.260.08:14:51.66#ibcon#enter sib2, iclass 5, count 0 2006.260.08:14:51.66#ibcon#flushed, iclass 5, count 0 2006.260.08:14:51.66#ibcon#about to write, iclass 5, count 0 2006.260.08:14:51.66#ibcon#wrote, iclass 5, count 0 2006.260.08:14:51.66#ibcon#about to read 3, iclass 5, count 0 2006.260.08:14:51.69#ibcon#read 3, iclass 5, count 0 2006.260.08:14:51.69#ibcon#about to read 4, iclass 5, count 0 2006.260.08:14:51.69#ibcon#read 4, iclass 5, count 0 2006.260.08:14:51.69#ibcon#about to read 5, iclass 5, count 0 2006.260.08:14:51.69#ibcon#read 5, iclass 5, count 0 2006.260.08:14:51.69#ibcon#about to read 6, iclass 5, count 0 2006.260.08:14:51.69#ibcon#read 6, iclass 5, count 0 2006.260.08:14:51.69#ibcon#end of sib2, iclass 5, count 0 2006.260.08:14:51.69#ibcon#*after write, iclass 5, count 0 2006.260.08:14:51.69#ibcon#*before return 0, iclass 5, count 0 2006.260.08:14:51.69#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:14:51.69#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:14:51.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:14:51.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:14:51.69$vc4f8/vblo=1,632.99 2006.260.08:14:51.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:14:51.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:14:51.69#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:51.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:51.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:51.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:51.69#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:14:51.69#ibcon#first serial, iclass 7, count 0 2006.260.08:14:51.69#ibcon#enter sib2, iclass 7, count 0 2006.260.08:14:51.69#ibcon#flushed, iclass 7, count 0 2006.260.08:14:51.69#ibcon#about to write, iclass 7, count 0 2006.260.08:14:51.69#ibcon#wrote, iclass 7, count 0 2006.260.08:14:51.69#ibcon#about to read 3, iclass 7, count 0 2006.260.08:14:51.71#ibcon#read 3, iclass 7, count 0 2006.260.08:14:51.71#ibcon#about to read 4, iclass 7, count 0 2006.260.08:14:51.71#ibcon#read 4, iclass 7, count 0 2006.260.08:14:51.71#ibcon#about to read 5, iclass 7, count 0 2006.260.08:14:51.71#ibcon#read 5, iclass 7, count 0 2006.260.08:14:51.71#ibcon#about to read 6, iclass 7, count 0 2006.260.08:14:51.71#ibcon#read 6, iclass 7, count 0 2006.260.08:14:51.71#ibcon#end of sib2, iclass 7, count 0 2006.260.08:14:51.71#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:14:51.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:14:51.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:14:51.71#ibcon#*before write, iclass 7, count 0 2006.260.08:14:51.71#ibcon#enter sib2, iclass 7, count 0 2006.260.08:14:51.71#ibcon#flushed, iclass 7, count 0 2006.260.08:14:51.71#ibcon#about to write, iclass 7, count 0 2006.260.08:14:51.71#ibcon#wrote, iclass 7, count 0 2006.260.08:14:51.71#ibcon#about to read 3, iclass 7, count 0 2006.260.08:14:51.75#ibcon#read 3, iclass 7, count 0 2006.260.08:14:51.75#ibcon#about to read 4, iclass 7, count 0 2006.260.08:14:51.75#ibcon#read 4, iclass 7, count 0 2006.260.08:14:51.75#ibcon#about to read 5, iclass 7, count 0 2006.260.08:14:51.75#ibcon#read 5, iclass 7, count 0 2006.260.08:14:51.75#ibcon#about to read 6, iclass 7, count 0 2006.260.08:14:51.75#ibcon#read 6, iclass 7, count 0 2006.260.08:14:51.75#ibcon#end of sib2, iclass 7, count 0 2006.260.08:14:51.75#ibcon#*after write, iclass 7, count 0 2006.260.08:14:51.75#ibcon#*before return 0, iclass 7, count 0 2006.260.08:14:51.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:51.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:14:51.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:14:51.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:14:51.75$vc4f8/vb=1,4 2006.260.08:14:51.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:14:51.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:14:51.75#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:51.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:51.75#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:51.75#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:51.75#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:14:51.75#ibcon#first serial, iclass 11, count 2 2006.260.08:14:51.75#ibcon#enter sib2, iclass 11, count 2 2006.260.08:14:51.75#ibcon#flushed, iclass 11, count 2 2006.260.08:14:51.75#ibcon#about to write, iclass 11, count 2 2006.260.08:14:51.75#ibcon#wrote, iclass 11, count 2 2006.260.08:14:51.75#ibcon#about to read 3, iclass 11, count 2 2006.260.08:14:51.77#ibcon#read 3, iclass 11, count 2 2006.260.08:14:51.77#ibcon#about to read 4, iclass 11, count 2 2006.260.08:14:51.77#ibcon#read 4, iclass 11, count 2 2006.260.08:14:51.77#ibcon#about to read 5, iclass 11, count 2 2006.260.08:14:51.77#ibcon#read 5, iclass 11, count 2 2006.260.08:14:51.77#ibcon#about to read 6, iclass 11, count 2 2006.260.08:14:51.77#ibcon#read 6, iclass 11, count 2 2006.260.08:14:51.77#ibcon#end of sib2, iclass 11, count 2 2006.260.08:14:51.77#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:14:51.77#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:14:51.77#ibcon#[27=AT01-04\r\n] 2006.260.08:14:51.77#ibcon#*before write, iclass 11, count 2 2006.260.08:14:51.77#ibcon#enter sib2, iclass 11, count 2 2006.260.08:14:51.77#ibcon#flushed, iclass 11, count 2 2006.260.08:14:51.77#ibcon#about to write, iclass 11, count 2 2006.260.08:14:51.77#ibcon#wrote, iclass 11, count 2 2006.260.08:14:51.77#ibcon#about to read 3, iclass 11, count 2 2006.260.08:14:51.80#ibcon#read 3, iclass 11, count 2 2006.260.08:14:51.80#ibcon#about to read 4, iclass 11, count 2 2006.260.08:14:51.80#ibcon#read 4, iclass 11, count 2 2006.260.08:14:51.80#ibcon#about to read 5, iclass 11, count 2 2006.260.08:14:51.80#ibcon#read 5, iclass 11, count 2 2006.260.08:14:51.80#ibcon#about to read 6, iclass 11, count 2 2006.260.08:14:51.80#ibcon#read 6, iclass 11, count 2 2006.260.08:14:51.80#ibcon#end of sib2, iclass 11, count 2 2006.260.08:14:51.80#ibcon#*after write, iclass 11, count 2 2006.260.08:14:51.80#ibcon#*before return 0, iclass 11, count 2 2006.260.08:14:51.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:51.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:14:51.80#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:14:51.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:51.80#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:51.92#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:51.92#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:51.92#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:14:51.92#ibcon#first serial, iclass 11, count 0 2006.260.08:14:51.92#ibcon#enter sib2, iclass 11, count 0 2006.260.08:14:51.92#ibcon#flushed, iclass 11, count 0 2006.260.08:14:51.92#ibcon#about to write, iclass 11, count 0 2006.260.08:14:51.92#ibcon#wrote, iclass 11, count 0 2006.260.08:14:51.92#ibcon#about to read 3, iclass 11, count 0 2006.260.08:14:51.94#ibcon#read 3, iclass 11, count 0 2006.260.08:14:51.94#ibcon#about to read 4, iclass 11, count 0 2006.260.08:14:51.94#ibcon#read 4, iclass 11, count 0 2006.260.08:14:51.94#ibcon#about to read 5, iclass 11, count 0 2006.260.08:14:51.94#ibcon#read 5, iclass 11, count 0 2006.260.08:14:51.94#ibcon#about to read 6, iclass 11, count 0 2006.260.08:14:51.94#ibcon#read 6, iclass 11, count 0 2006.260.08:14:51.94#ibcon#end of sib2, iclass 11, count 0 2006.260.08:14:51.94#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:14:51.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:14:51.94#ibcon#[27=USB\r\n] 2006.260.08:14:51.94#ibcon#*before write, iclass 11, count 0 2006.260.08:14:51.94#ibcon#enter sib2, iclass 11, count 0 2006.260.08:14:51.94#ibcon#flushed, iclass 11, count 0 2006.260.08:14:51.94#ibcon#about to write, iclass 11, count 0 2006.260.08:14:51.94#ibcon#wrote, iclass 11, count 0 2006.260.08:14:51.94#ibcon#about to read 3, iclass 11, count 0 2006.260.08:14:51.97#ibcon#read 3, iclass 11, count 0 2006.260.08:14:51.97#ibcon#about to read 4, iclass 11, count 0 2006.260.08:14:51.97#ibcon#read 4, iclass 11, count 0 2006.260.08:14:51.97#ibcon#about to read 5, iclass 11, count 0 2006.260.08:14:51.97#ibcon#read 5, iclass 11, count 0 2006.260.08:14:51.97#ibcon#about to read 6, iclass 11, count 0 2006.260.08:14:51.97#ibcon#read 6, iclass 11, count 0 2006.260.08:14:51.97#ibcon#end of sib2, iclass 11, count 0 2006.260.08:14:51.97#ibcon#*after write, iclass 11, count 0 2006.260.08:14:51.97#ibcon#*before return 0, iclass 11, count 0 2006.260.08:14:51.97#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:51.97#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:14:51.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:14:51.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:14:51.97$vc4f8/vblo=2,640.99 2006.260.08:14:51.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:14:51.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:14:51.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:51.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:51.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:51.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:51.97#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:14:51.97#ibcon#first serial, iclass 13, count 0 2006.260.08:14:51.97#ibcon#enter sib2, iclass 13, count 0 2006.260.08:14:51.97#ibcon#flushed, iclass 13, count 0 2006.260.08:14:51.97#ibcon#about to write, iclass 13, count 0 2006.260.08:14:51.97#ibcon#wrote, iclass 13, count 0 2006.260.08:14:51.97#ibcon#about to read 3, iclass 13, count 0 2006.260.08:14:51.99#ibcon#read 3, iclass 13, count 0 2006.260.08:14:51.99#ibcon#about to read 4, iclass 13, count 0 2006.260.08:14:51.99#ibcon#read 4, iclass 13, count 0 2006.260.08:14:51.99#ibcon#about to read 5, iclass 13, count 0 2006.260.08:14:51.99#ibcon#read 5, iclass 13, count 0 2006.260.08:14:51.99#ibcon#about to read 6, iclass 13, count 0 2006.260.08:14:51.99#ibcon#read 6, iclass 13, count 0 2006.260.08:14:51.99#ibcon#end of sib2, iclass 13, count 0 2006.260.08:14:51.99#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:14:51.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:14:51.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:14:51.99#ibcon#*before write, iclass 13, count 0 2006.260.08:14:51.99#ibcon#enter sib2, iclass 13, count 0 2006.260.08:14:51.99#ibcon#flushed, iclass 13, count 0 2006.260.08:14:51.99#ibcon#about to write, iclass 13, count 0 2006.260.08:14:51.99#ibcon#wrote, iclass 13, count 0 2006.260.08:14:51.99#ibcon#about to read 3, iclass 13, count 0 2006.260.08:14:52.03#ibcon#read 3, iclass 13, count 0 2006.260.08:14:52.03#ibcon#about to read 4, iclass 13, count 0 2006.260.08:14:52.03#ibcon#read 4, iclass 13, count 0 2006.260.08:14:52.03#ibcon#about to read 5, iclass 13, count 0 2006.260.08:14:52.03#ibcon#read 5, iclass 13, count 0 2006.260.08:14:52.03#ibcon#about to read 6, iclass 13, count 0 2006.260.08:14:52.03#ibcon#read 6, iclass 13, count 0 2006.260.08:14:52.03#ibcon#end of sib2, iclass 13, count 0 2006.260.08:14:52.03#ibcon#*after write, iclass 13, count 0 2006.260.08:14:52.03#ibcon#*before return 0, iclass 13, count 0 2006.260.08:14:52.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:52.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:14:52.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:14:52.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:14:52.03$vc4f8/vb=2,5 2006.260.08:14:52.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:14:52.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:14:52.03#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:52.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:52.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:52.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:52.09#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:14:52.09#ibcon#first serial, iclass 15, count 2 2006.260.08:14:52.09#ibcon#enter sib2, iclass 15, count 2 2006.260.08:14:52.09#ibcon#flushed, iclass 15, count 2 2006.260.08:14:52.09#ibcon#about to write, iclass 15, count 2 2006.260.08:14:52.09#ibcon#wrote, iclass 15, count 2 2006.260.08:14:52.09#ibcon#about to read 3, iclass 15, count 2 2006.260.08:14:52.11#ibcon#read 3, iclass 15, count 2 2006.260.08:14:52.11#ibcon#about to read 4, iclass 15, count 2 2006.260.08:14:52.11#ibcon#read 4, iclass 15, count 2 2006.260.08:14:52.11#ibcon#about to read 5, iclass 15, count 2 2006.260.08:14:52.11#ibcon#read 5, iclass 15, count 2 2006.260.08:14:52.11#ibcon#about to read 6, iclass 15, count 2 2006.260.08:14:52.11#ibcon#read 6, iclass 15, count 2 2006.260.08:14:52.11#ibcon#end of sib2, iclass 15, count 2 2006.260.08:14:52.11#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:14:52.11#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:14:52.11#ibcon#[27=AT02-05\r\n] 2006.260.08:14:52.11#ibcon#*before write, iclass 15, count 2 2006.260.08:14:52.11#ibcon#enter sib2, iclass 15, count 2 2006.260.08:14:52.11#ibcon#flushed, iclass 15, count 2 2006.260.08:14:52.11#ibcon#about to write, iclass 15, count 2 2006.260.08:14:52.11#ibcon#wrote, iclass 15, count 2 2006.260.08:14:52.11#ibcon#about to read 3, iclass 15, count 2 2006.260.08:14:52.14#ibcon#read 3, iclass 15, count 2 2006.260.08:14:52.14#ibcon#about to read 4, iclass 15, count 2 2006.260.08:14:52.14#ibcon#read 4, iclass 15, count 2 2006.260.08:14:52.14#ibcon#about to read 5, iclass 15, count 2 2006.260.08:14:52.14#ibcon#read 5, iclass 15, count 2 2006.260.08:14:52.14#ibcon#about to read 6, iclass 15, count 2 2006.260.08:14:52.14#ibcon#read 6, iclass 15, count 2 2006.260.08:14:52.14#ibcon#end of sib2, iclass 15, count 2 2006.260.08:14:52.14#ibcon#*after write, iclass 15, count 2 2006.260.08:14:52.14#ibcon#*before return 0, iclass 15, count 2 2006.260.08:14:52.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:52.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:14:52.14#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:14:52.14#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:52.14#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:52.26#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:52.26#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:52.26#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:14:52.26#ibcon#first serial, iclass 15, count 0 2006.260.08:14:52.26#ibcon#enter sib2, iclass 15, count 0 2006.260.08:14:52.26#ibcon#flushed, iclass 15, count 0 2006.260.08:14:52.26#ibcon#about to write, iclass 15, count 0 2006.260.08:14:52.26#ibcon#wrote, iclass 15, count 0 2006.260.08:14:52.26#ibcon#about to read 3, iclass 15, count 0 2006.260.08:14:52.28#ibcon#read 3, iclass 15, count 0 2006.260.08:14:52.28#ibcon#about to read 4, iclass 15, count 0 2006.260.08:14:52.28#ibcon#read 4, iclass 15, count 0 2006.260.08:14:52.28#ibcon#about to read 5, iclass 15, count 0 2006.260.08:14:52.28#ibcon#read 5, iclass 15, count 0 2006.260.08:14:52.28#ibcon#about to read 6, iclass 15, count 0 2006.260.08:14:52.28#ibcon#read 6, iclass 15, count 0 2006.260.08:14:52.28#ibcon#end of sib2, iclass 15, count 0 2006.260.08:14:52.28#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:14:52.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:14:52.28#ibcon#[27=USB\r\n] 2006.260.08:14:52.28#ibcon#*before write, iclass 15, count 0 2006.260.08:14:52.28#ibcon#enter sib2, iclass 15, count 0 2006.260.08:14:52.28#ibcon#flushed, iclass 15, count 0 2006.260.08:14:52.28#ibcon#about to write, iclass 15, count 0 2006.260.08:14:52.28#ibcon#wrote, iclass 15, count 0 2006.260.08:14:52.28#ibcon#about to read 3, iclass 15, count 0 2006.260.08:14:52.31#ibcon#read 3, iclass 15, count 0 2006.260.08:14:52.31#ibcon#about to read 4, iclass 15, count 0 2006.260.08:14:52.31#ibcon#read 4, iclass 15, count 0 2006.260.08:14:52.31#ibcon#about to read 5, iclass 15, count 0 2006.260.08:14:52.31#ibcon#read 5, iclass 15, count 0 2006.260.08:14:52.31#ibcon#about to read 6, iclass 15, count 0 2006.260.08:14:52.31#ibcon#read 6, iclass 15, count 0 2006.260.08:14:52.31#ibcon#end of sib2, iclass 15, count 0 2006.260.08:14:52.31#ibcon#*after write, iclass 15, count 0 2006.260.08:14:52.31#ibcon#*before return 0, iclass 15, count 0 2006.260.08:14:52.31#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:52.31#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:14:52.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:14:52.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:14:52.31$vc4f8/vblo=3,656.99 2006.260.08:14:52.31#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.08:14:52.31#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.08:14:52.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:52.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:14:52.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:14:52.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:14:52.31#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:14:52.31#ibcon#first serial, iclass 17, count 0 2006.260.08:14:52.31#ibcon#enter sib2, iclass 17, count 0 2006.260.08:14:52.31#ibcon#flushed, iclass 17, count 0 2006.260.08:14:52.31#ibcon#about to write, iclass 17, count 0 2006.260.08:14:52.31#ibcon#wrote, iclass 17, count 0 2006.260.08:14:52.31#ibcon#about to read 3, iclass 17, count 0 2006.260.08:14:52.33#ibcon#read 3, iclass 17, count 0 2006.260.08:14:52.33#ibcon#about to read 4, iclass 17, count 0 2006.260.08:14:52.33#ibcon#read 4, iclass 17, count 0 2006.260.08:14:52.33#ibcon#about to read 5, iclass 17, count 0 2006.260.08:14:52.33#ibcon#read 5, iclass 17, count 0 2006.260.08:14:52.33#ibcon#about to read 6, iclass 17, count 0 2006.260.08:14:52.33#ibcon#read 6, iclass 17, count 0 2006.260.08:14:52.33#ibcon#end of sib2, iclass 17, count 0 2006.260.08:14:52.33#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:14:52.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:14:52.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:14:52.33#ibcon#*before write, iclass 17, count 0 2006.260.08:14:52.33#ibcon#enter sib2, iclass 17, count 0 2006.260.08:14:52.33#ibcon#flushed, iclass 17, count 0 2006.260.08:14:52.33#ibcon#about to write, iclass 17, count 0 2006.260.08:14:52.33#ibcon#wrote, iclass 17, count 0 2006.260.08:14:52.33#ibcon#about to read 3, iclass 17, count 0 2006.260.08:14:52.37#ibcon#read 3, iclass 17, count 0 2006.260.08:14:52.37#ibcon#about to read 4, iclass 17, count 0 2006.260.08:14:52.37#ibcon#read 4, iclass 17, count 0 2006.260.08:14:52.37#ibcon#about to read 5, iclass 17, count 0 2006.260.08:14:52.37#ibcon#read 5, iclass 17, count 0 2006.260.08:14:52.37#ibcon#about to read 6, iclass 17, count 0 2006.260.08:14:52.37#ibcon#read 6, iclass 17, count 0 2006.260.08:14:52.37#ibcon#end of sib2, iclass 17, count 0 2006.260.08:14:52.37#ibcon#*after write, iclass 17, count 0 2006.260.08:14:52.37#ibcon#*before return 0, iclass 17, count 0 2006.260.08:14:52.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:14:52.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:14:52.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:14:52.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:14:52.37$vc4f8/vb=3,4 2006.260.08:14:52.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.08:14:52.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.08:14:52.37#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:52.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:14:52.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:14:52.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:14:52.43#ibcon#enter wrdev, iclass 19, count 2 2006.260.08:14:52.43#ibcon#first serial, iclass 19, count 2 2006.260.08:14:52.43#ibcon#enter sib2, iclass 19, count 2 2006.260.08:14:52.43#ibcon#flushed, iclass 19, count 2 2006.260.08:14:52.43#ibcon#about to write, iclass 19, count 2 2006.260.08:14:52.43#ibcon#wrote, iclass 19, count 2 2006.260.08:14:52.43#ibcon#about to read 3, iclass 19, count 2 2006.260.08:14:52.45#ibcon#read 3, iclass 19, count 2 2006.260.08:14:52.45#ibcon#about to read 4, iclass 19, count 2 2006.260.08:14:52.45#ibcon#read 4, iclass 19, count 2 2006.260.08:14:52.45#ibcon#about to read 5, iclass 19, count 2 2006.260.08:14:52.45#ibcon#read 5, iclass 19, count 2 2006.260.08:14:52.45#ibcon#about to read 6, iclass 19, count 2 2006.260.08:14:52.45#ibcon#read 6, iclass 19, count 2 2006.260.08:14:52.45#ibcon#end of sib2, iclass 19, count 2 2006.260.08:14:52.45#ibcon#*mode == 0, iclass 19, count 2 2006.260.08:14:52.45#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.08:14:52.45#ibcon#[27=AT03-04\r\n] 2006.260.08:14:52.45#ibcon#*before write, iclass 19, count 2 2006.260.08:14:52.45#ibcon#enter sib2, iclass 19, count 2 2006.260.08:14:52.45#ibcon#flushed, iclass 19, count 2 2006.260.08:14:52.45#ibcon#about to write, iclass 19, count 2 2006.260.08:14:52.45#ibcon#wrote, iclass 19, count 2 2006.260.08:14:52.45#ibcon#about to read 3, iclass 19, count 2 2006.260.08:14:52.48#ibcon#read 3, iclass 19, count 2 2006.260.08:14:52.48#ibcon#about to read 4, iclass 19, count 2 2006.260.08:14:52.48#ibcon#read 4, iclass 19, count 2 2006.260.08:14:52.48#ibcon#about to read 5, iclass 19, count 2 2006.260.08:14:52.48#ibcon#read 5, iclass 19, count 2 2006.260.08:14:52.48#ibcon#about to read 6, iclass 19, count 2 2006.260.08:14:52.48#ibcon#read 6, iclass 19, count 2 2006.260.08:14:52.48#ibcon#end of sib2, iclass 19, count 2 2006.260.08:14:52.48#ibcon#*after write, iclass 19, count 2 2006.260.08:14:52.48#ibcon#*before return 0, iclass 19, count 2 2006.260.08:14:52.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:14:52.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:14:52.48#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.08:14:52.48#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:52.48#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:14:52.60#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:14:52.60#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:14:52.60#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:14:52.60#ibcon#first serial, iclass 19, count 0 2006.260.08:14:52.60#ibcon#enter sib2, iclass 19, count 0 2006.260.08:14:52.60#ibcon#flushed, iclass 19, count 0 2006.260.08:14:52.60#ibcon#about to write, iclass 19, count 0 2006.260.08:14:52.60#ibcon#wrote, iclass 19, count 0 2006.260.08:14:52.60#ibcon#about to read 3, iclass 19, count 0 2006.260.08:14:52.62#ibcon#read 3, iclass 19, count 0 2006.260.08:14:52.62#ibcon#about to read 4, iclass 19, count 0 2006.260.08:14:52.62#ibcon#read 4, iclass 19, count 0 2006.260.08:14:52.62#ibcon#about to read 5, iclass 19, count 0 2006.260.08:14:52.62#ibcon#read 5, iclass 19, count 0 2006.260.08:14:52.62#ibcon#about to read 6, iclass 19, count 0 2006.260.08:14:52.62#ibcon#read 6, iclass 19, count 0 2006.260.08:14:52.62#ibcon#end of sib2, iclass 19, count 0 2006.260.08:14:52.62#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:14:52.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:14:52.62#ibcon#[27=USB\r\n] 2006.260.08:14:52.62#ibcon#*before write, iclass 19, count 0 2006.260.08:14:52.62#ibcon#enter sib2, iclass 19, count 0 2006.260.08:14:52.62#ibcon#flushed, iclass 19, count 0 2006.260.08:14:52.62#ibcon#about to write, iclass 19, count 0 2006.260.08:14:52.62#ibcon#wrote, iclass 19, count 0 2006.260.08:14:52.62#ibcon#about to read 3, iclass 19, count 0 2006.260.08:14:52.65#ibcon#read 3, iclass 19, count 0 2006.260.08:14:52.65#ibcon#about to read 4, iclass 19, count 0 2006.260.08:14:52.65#ibcon#read 4, iclass 19, count 0 2006.260.08:14:52.65#ibcon#about to read 5, iclass 19, count 0 2006.260.08:14:52.65#ibcon#read 5, iclass 19, count 0 2006.260.08:14:52.65#ibcon#about to read 6, iclass 19, count 0 2006.260.08:14:52.65#ibcon#read 6, iclass 19, count 0 2006.260.08:14:52.65#ibcon#end of sib2, iclass 19, count 0 2006.260.08:14:52.65#ibcon#*after write, iclass 19, count 0 2006.260.08:14:52.65#ibcon#*before return 0, iclass 19, count 0 2006.260.08:14:52.65#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:14:52.65#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:14:52.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:14:52.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:14:52.65$vc4f8/vblo=4,712.99 2006.260.08:14:52.65#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:14:52.65#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:14:52.65#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:52.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:14:52.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:14:52.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:14:52.65#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:14:52.65#ibcon#first serial, iclass 21, count 0 2006.260.08:14:52.65#ibcon#enter sib2, iclass 21, count 0 2006.260.08:14:52.65#ibcon#flushed, iclass 21, count 0 2006.260.08:14:52.65#ibcon#about to write, iclass 21, count 0 2006.260.08:14:52.65#ibcon#wrote, iclass 21, count 0 2006.260.08:14:52.65#ibcon#about to read 3, iclass 21, count 0 2006.260.08:14:52.67#ibcon#read 3, iclass 21, count 0 2006.260.08:14:52.67#ibcon#about to read 4, iclass 21, count 0 2006.260.08:14:52.67#ibcon#read 4, iclass 21, count 0 2006.260.08:14:52.67#ibcon#about to read 5, iclass 21, count 0 2006.260.08:14:52.67#ibcon#read 5, iclass 21, count 0 2006.260.08:14:52.67#ibcon#about to read 6, iclass 21, count 0 2006.260.08:14:52.67#ibcon#read 6, iclass 21, count 0 2006.260.08:14:52.67#ibcon#end of sib2, iclass 21, count 0 2006.260.08:14:52.67#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:14:52.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:14:52.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:14:52.67#ibcon#*before write, iclass 21, count 0 2006.260.08:14:52.67#ibcon#enter sib2, iclass 21, count 0 2006.260.08:14:52.67#ibcon#flushed, iclass 21, count 0 2006.260.08:14:52.67#ibcon#about to write, iclass 21, count 0 2006.260.08:14:52.67#ibcon#wrote, iclass 21, count 0 2006.260.08:14:52.67#ibcon#about to read 3, iclass 21, count 0 2006.260.08:14:52.71#ibcon#read 3, iclass 21, count 0 2006.260.08:14:52.71#ibcon#about to read 4, iclass 21, count 0 2006.260.08:14:52.71#ibcon#read 4, iclass 21, count 0 2006.260.08:14:52.71#ibcon#about to read 5, iclass 21, count 0 2006.260.08:14:52.71#ibcon#read 5, iclass 21, count 0 2006.260.08:14:52.71#ibcon#about to read 6, iclass 21, count 0 2006.260.08:14:52.71#ibcon#read 6, iclass 21, count 0 2006.260.08:14:52.71#ibcon#end of sib2, iclass 21, count 0 2006.260.08:14:52.71#ibcon#*after write, iclass 21, count 0 2006.260.08:14:52.71#ibcon#*before return 0, iclass 21, count 0 2006.260.08:14:52.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:14:52.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:14:52.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:14:52.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:14:52.71$vc4f8/vb=4,5 2006.260.08:14:52.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:14:52.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:14:52.71#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:52.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:52.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:52.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:52.77#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:14:52.77#ibcon#first serial, iclass 23, count 2 2006.260.08:14:52.77#ibcon#enter sib2, iclass 23, count 2 2006.260.08:14:52.77#ibcon#flushed, iclass 23, count 2 2006.260.08:14:52.77#ibcon#about to write, iclass 23, count 2 2006.260.08:14:52.77#ibcon#wrote, iclass 23, count 2 2006.260.08:14:52.77#ibcon#about to read 3, iclass 23, count 2 2006.260.08:14:52.79#ibcon#read 3, iclass 23, count 2 2006.260.08:14:52.79#ibcon#about to read 4, iclass 23, count 2 2006.260.08:14:52.79#ibcon#read 4, iclass 23, count 2 2006.260.08:14:52.79#ibcon#about to read 5, iclass 23, count 2 2006.260.08:14:52.79#ibcon#read 5, iclass 23, count 2 2006.260.08:14:52.79#ibcon#about to read 6, iclass 23, count 2 2006.260.08:14:52.79#ibcon#read 6, iclass 23, count 2 2006.260.08:14:52.79#ibcon#end of sib2, iclass 23, count 2 2006.260.08:14:52.79#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:14:52.79#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:14:52.79#ibcon#[27=AT04-05\r\n] 2006.260.08:14:52.79#ibcon#*before write, iclass 23, count 2 2006.260.08:14:52.79#ibcon#enter sib2, iclass 23, count 2 2006.260.08:14:52.79#ibcon#flushed, iclass 23, count 2 2006.260.08:14:52.79#ibcon#about to write, iclass 23, count 2 2006.260.08:14:52.79#ibcon#wrote, iclass 23, count 2 2006.260.08:14:52.79#ibcon#about to read 3, iclass 23, count 2 2006.260.08:14:52.82#ibcon#read 3, iclass 23, count 2 2006.260.08:14:52.82#ibcon#about to read 4, iclass 23, count 2 2006.260.08:14:52.82#ibcon#read 4, iclass 23, count 2 2006.260.08:14:52.82#ibcon#about to read 5, iclass 23, count 2 2006.260.08:14:52.82#ibcon#read 5, iclass 23, count 2 2006.260.08:14:52.82#ibcon#about to read 6, iclass 23, count 2 2006.260.08:14:52.82#ibcon#read 6, iclass 23, count 2 2006.260.08:14:52.82#ibcon#end of sib2, iclass 23, count 2 2006.260.08:14:52.82#ibcon#*after write, iclass 23, count 2 2006.260.08:14:52.82#ibcon#*before return 0, iclass 23, count 2 2006.260.08:14:52.82#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:52.82#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:14:52.82#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:14:52.82#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:52.82#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:52.94#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:52.94#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:52.94#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:14:52.94#ibcon#first serial, iclass 23, count 0 2006.260.08:14:52.94#ibcon#enter sib2, iclass 23, count 0 2006.260.08:14:52.94#ibcon#flushed, iclass 23, count 0 2006.260.08:14:52.94#ibcon#about to write, iclass 23, count 0 2006.260.08:14:52.94#ibcon#wrote, iclass 23, count 0 2006.260.08:14:52.94#ibcon#about to read 3, iclass 23, count 0 2006.260.08:14:52.96#ibcon#read 3, iclass 23, count 0 2006.260.08:14:52.96#ibcon#about to read 4, iclass 23, count 0 2006.260.08:14:52.96#ibcon#read 4, iclass 23, count 0 2006.260.08:14:52.96#ibcon#about to read 5, iclass 23, count 0 2006.260.08:14:52.96#ibcon#read 5, iclass 23, count 0 2006.260.08:14:52.96#ibcon#about to read 6, iclass 23, count 0 2006.260.08:14:52.96#ibcon#read 6, iclass 23, count 0 2006.260.08:14:52.96#ibcon#end of sib2, iclass 23, count 0 2006.260.08:14:52.96#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:14:52.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:14:52.96#ibcon#[27=USB\r\n] 2006.260.08:14:52.96#ibcon#*before write, iclass 23, count 0 2006.260.08:14:52.96#ibcon#enter sib2, iclass 23, count 0 2006.260.08:14:52.96#ibcon#flushed, iclass 23, count 0 2006.260.08:14:52.96#ibcon#about to write, iclass 23, count 0 2006.260.08:14:52.96#ibcon#wrote, iclass 23, count 0 2006.260.08:14:52.96#ibcon#about to read 3, iclass 23, count 0 2006.260.08:14:52.99#ibcon#read 3, iclass 23, count 0 2006.260.08:14:52.99#ibcon#about to read 4, iclass 23, count 0 2006.260.08:14:52.99#ibcon#read 4, iclass 23, count 0 2006.260.08:14:52.99#ibcon#about to read 5, iclass 23, count 0 2006.260.08:14:52.99#ibcon#read 5, iclass 23, count 0 2006.260.08:14:52.99#ibcon#about to read 6, iclass 23, count 0 2006.260.08:14:52.99#ibcon#read 6, iclass 23, count 0 2006.260.08:14:52.99#ibcon#end of sib2, iclass 23, count 0 2006.260.08:14:52.99#ibcon#*after write, iclass 23, count 0 2006.260.08:14:52.99#ibcon#*before return 0, iclass 23, count 0 2006.260.08:14:52.99#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:52.99#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:14:52.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:14:52.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:14:52.99$vc4f8/vblo=5,744.99 2006.260.08:14:52.99#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:14:52.99#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:14:52.99#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:52.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:52.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:52.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:52.99#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:14:52.99#ibcon#first serial, iclass 25, count 0 2006.260.08:14:52.99#ibcon#enter sib2, iclass 25, count 0 2006.260.08:14:52.99#ibcon#flushed, iclass 25, count 0 2006.260.08:14:52.99#ibcon#about to write, iclass 25, count 0 2006.260.08:14:52.99#ibcon#wrote, iclass 25, count 0 2006.260.08:14:52.99#ibcon#about to read 3, iclass 25, count 0 2006.260.08:14:53.01#ibcon#read 3, iclass 25, count 0 2006.260.08:14:53.01#ibcon#about to read 4, iclass 25, count 0 2006.260.08:14:53.01#ibcon#read 4, iclass 25, count 0 2006.260.08:14:53.01#ibcon#about to read 5, iclass 25, count 0 2006.260.08:14:53.01#ibcon#read 5, iclass 25, count 0 2006.260.08:14:53.01#ibcon#about to read 6, iclass 25, count 0 2006.260.08:14:53.01#ibcon#read 6, iclass 25, count 0 2006.260.08:14:53.01#ibcon#end of sib2, iclass 25, count 0 2006.260.08:14:53.01#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:14:53.01#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:14:53.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:14:53.01#ibcon#*before write, iclass 25, count 0 2006.260.08:14:53.01#ibcon#enter sib2, iclass 25, count 0 2006.260.08:14:53.01#ibcon#flushed, iclass 25, count 0 2006.260.08:14:53.01#ibcon#about to write, iclass 25, count 0 2006.260.08:14:53.01#ibcon#wrote, iclass 25, count 0 2006.260.08:14:53.01#ibcon#about to read 3, iclass 25, count 0 2006.260.08:14:53.05#ibcon#read 3, iclass 25, count 0 2006.260.08:14:53.05#ibcon#about to read 4, iclass 25, count 0 2006.260.08:14:53.05#ibcon#read 4, iclass 25, count 0 2006.260.08:14:53.05#ibcon#about to read 5, iclass 25, count 0 2006.260.08:14:53.05#ibcon#read 5, iclass 25, count 0 2006.260.08:14:53.05#ibcon#about to read 6, iclass 25, count 0 2006.260.08:14:53.05#ibcon#read 6, iclass 25, count 0 2006.260.08:14:53.05#ibcon#end of sib2, iclass 25, count 0 2006.260.08:14:53.05#ibcon#*after write, iclass 25, count 0 2006.260.08:14:53.05#ibcon#*before return 0, iclass 25, count 0 2006.260.08:14:53.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:53.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:14:53.05#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:14:53.05#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:14:53.05$vc4f8/vb=5,4 2006.260.08:14:53.05#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:14:53.05#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:14:53.05#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:53.05#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:53.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:53.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:53.11#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:14:53.11#ibcon#first serial, iclass 27, count 2 2006.260.08:14:53.11#ibcon#enter sib2, iclass 27, count 2 2006.260.08:14:53.11#ibcon#flushed, iclass 27, count 2 2006.260.08:14:53.11#ibcon#about to write, iclass 27, count 2 2006.260.08:14:53.11#ibcon#wrote, iclass 27, count 2 2006.260.08:14:53.11#ibcon#about to read 3, iclass 27, count 2 2006.260.08:14:53.13#ibcon#read 3, iclass 27, count 2 2006.260.08:14:53.13#ibcon#about to read 4, iclass 27, count 2 2006.260.08:14:53.13#ibcon#read 4, iclass 27, count 2 2006.260.08:14:53.13#ibcon#about to read 5, iclass 27, count 2 2006.260.08:14:53.13#ibcon#read 5, iclass 27, count 2 2006.260.08:14:53.13#ibcon#about to read 6, iclass 27, count 2 2006.260.08:14:53.13#ibcon#read 6, iclass 27, count 2 2006.260.08:14:53.13#ibcon#end of sib2, iclass 27, count 2 2006.260.08:14:53.13#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:14:53.13#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:14:53.13#ibcon#[27=AT05-04\r\n] 2006.260.08:14:53.13#ibcon#*before write, iclass 27, count 2 2006.260.08:14:53.13#ibcon#enter sib2, iclass 27, count 2 2006.260.08:14:53.13#ibcon#flushed, iclass 27, count 2 2006.260.08:14:53.13#ibcon#about to write, iclass 27, count 2 2006.260.08:14:53.13#ibcon#wrote, iclass 27, count 2 2006.260.08:14:53.13#ibcon#about to read 3, iclass 27, count 2 2006.260.08:14:53.16#ibcon#read 3, iclass 27, count 2 2006.260.08:14:53.16#ibcon#about to read 4, iclass 27, count 2 2006.260.08:14:53.16#ibcon#read 4, iclass 27, count 2 2006.260.08:14:53.16#ibcon#about to read 5, iclass 27, count 2 2006.260.08:14:53.16#ibcon#read 5, iclass 27, count 2 2006.260.08:14:53.16#ibcon#about to read 6, iclass 27, count 2 2006.260.08:14:53.16#ibcon#read 6, iclass 27, count 2 2006.260.08:14:53.16#ibcon#end of sib2, iclass 27, count 2 2006.260.08:14:53.16#ibcon#*after write, iclass 27, count 2 2006.260.08:14:53.16#ibcon#*before return 0, iclass 27, count 2 2006.260.08:14:53.16#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:53.16#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:14:53.16#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:14:53.16#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:53.16#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:53.28#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:53.28#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:53.28#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:14:53.28#ibcon#first serial, iclass 27, count 0 2006.260.08:14:53.28#ibcon#enter sib2, iclass 27, count 0 2006.260.08:14:53.28#ibcon#flushed, iclass 27, count 0 2006.260.08:14:53.28#ibcon#about to write, iclass 27, count 0 2006.260.08:14:53.28#ibcon#wrote, iclass 27, count 0 2006.260.08:14:53.28#ibcon#about to read 3, iclass 27, count 0 2006.260.08:14:53.30#ibcon#read 3, iclass 27, count 0 2006.260.08:14:53.30#ibcon#about to read 4, iclass 27, count 0 2006.260.08:14:53.30#ibcon#read 4, iclass 27, count 0 2006.260.08:14:53.30#ibcon#about to read 5, iclass 27, count 0 2006.260.08:14:53.30#ibcon#read 5, iclass 27, count 0 2006.260.08:14:53.30#ibcon#about to read 6, iclass 27, count 0 2006.260.08:14:53.30#ibcon#read 6, iclass 27, count 0 2006.260.08:14:53.30#ibcon#end of sib2, iclass 27, count 0 2006.260.08:14:53.30#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:14:53.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:14:53.30#ibcon#[27=USB\r\n] 2006.260.08:14:53.30#ibcon#*before write, iclass 27, count 0 2006.260.08:14:53.30#ibcon#enter sib2, iclass 27, count 0 2006.260.08:14:53.30#ibcon#flushed, iclass 27, count 0 2006.260.08:14:53.30#ibcon#about to write, iclass 27, count 0 2006.260.08:14:53.30#ibcon#wrote, iclass 27, count 0 2006.260.08:14:53.30#ibcon#about to read 3, iclass 27, count 0 2006.260.08:14:53.33#ibcon#read 3, iclass 27, count 0 2006.260.08:14:53.33#ibcon#about to read 4, iclass 27, count 0 2006.260.08:14:53.33#ibcon#read 4, iclass 27, count 0 2006.260.08:14:53.33#ibcon#about to read 5, iclass 27, count 0 2006.260.08:14:53.33#ibcon#read 5, iclass 27, count 0 2006.260.08:14:53.33#ibcon#about to read 6, iclass 27, count 0 2006.260.08:14:53.33#ibcon#read 6, iclass 27, count 0 2006.260.08:14:53.33#ibcon#end of sib2, iclass 27, count 0 2006.260.08:14:53.33#ibcon#*after write, iclass 27, count 0 2006.260.08:14:53.33#ibcon#*before return 0, iclass 27, count 0 2006.260.08:14:53.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:53.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:14:53.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:14:53.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:14:53.33$vc4f8/vblo=6,752.99 2006.260.08:14:53.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:14:53.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:14:53.33#ibcon#ireg 17 cls_cnt 0 2006.260.08:14:53.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:53.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:53.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:53.33#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:14:53.33#ibcon#first serial, iclass 29, count 0 2006.260.08:14:53.33#ibcon#enter sib2, iclass 29, count 0 2006.260.08:14:53.33#ibcon#flushed, iclass 29, count 0 2006.260.08:14:53.33#ibcon#about to write, iclass 29, count 0 2006.260.08:14:53.33#ibcon#wrote, iclass 29, count 0 2006.260.08:14:53.33#ibcon#about to read 3, iclass 29, count 0 2006.260.08:14:53.35#ibcon#read 3, iclass 29, count 0 2006.260.08:14:53.35#ibcon#about to read 4, iclass 29, count 0 2006.260.08:14:53.35#ibcon#read 4, iclass 29, count 0 2006.260.08:14:53.35#ibcon#about to read 5, iclass 29, count 0 2006.260.08:14:53.35#ibcon#read 5, iclass 29, count 0 2006.260.08:14:53.35#ibcon#about to read 6, iclass 29, count 0 2006.260.08:14:53.35#ibcon#read 6, iclass 29, count 0 2006.260.08:14:53.35#ibcon#end of sib2, iclass 29, count 0 2006.260.08:14:53.35#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:14:53.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:14:53.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:14:53.35#ibcon#*before write, iclass 29, count 0 2006.260.08:14:53.35#ibcon#enter sib2, iclass 29, count 0 2006.260.08:14:53.35#ibcon#flushed, iclass 29, count 0 2006.260.08:14:53.35#ibcon#about to write, iclass 29, count 0 2006.260.08:14:53.35#ibcon#wrote, iclass 29, count 0 2006.260.08:14:53.35#ibcon#about to read 3, iclass 29, count 0 2006.260.08:14:53.39#ibcon#read 3, iclass 29, count 0 2006.260.08:14:53.39#ibcon#about to read 4, iclass 29, count 0 2006.260.08:14:53.39#ibcon#read 4, iclass 29, count 0 2006.260.08:14:53.39#ibcon#about to read 5, iclass 29, count 0 2006.260.08:14:53.39#ibcon#read 5, iclass 29, count 0 2006.260.08:14:53.39#ibcon#about to read 6, iclass 29, count 0 2006.260.08:14:53.39#ibcon#read 6, iclass 29, count 0 2006.260.08:14:53.39#ibcon#end of sib2, iclass 29, count 0 2006.260.08:14:53.39#ibcon#*after write, iclass 29, count 0 2006.260.08:14:53.39#ibcon#*before return 0, iclass 29, count 0 2006.260.08:14:53.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:53.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:14:53.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:14:53.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:14:53.39$vc4f8/vb=6,4 2006.260.08:14:53.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:14:53.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:14:53.39#ibcon#ireg 11 cls_cnt 2 2006.260.08:14:53.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:53.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:53.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:53.45#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:14:53.45#ibcon#first serial, iclass 31, count 2 2006.260.08:14:53.45#ibcon#enter sib2, iclass 31, count 2 2006.260.08:14:53.45#ibcon#flushed, iclass 31, count 2 2006.260.08:14:53.45#ibcon#about to write, iclass 31, count 2 2006.260.08:14:53.45#ibcon#wrote, iclass 31, count 2 2006.260.08:14:53.45#ibcon#about to read 3, iclass 31, count 2 2006.260.08:14:53.47#ibcon#read 3, iclass 31, count 2 2006.260.08:14:53.47#ibcon#about to read 4, iclass 31, count 2 2006.260.08:14:53.47#ibcon#read 4, iclass 31, count 2 2006.260.08:14:53.47#ibcon#about to read 5, iclass 31, count 2 2006.260.08:14:53.47#ibcon#read 5, iclass 31, count 2 2006.260.08:14:53.47#ibcon#about to read 6, iclass 31, count 2 2006.260.08:14:53.47#ibcon#read 6, iclass 31, count 2 2006.260.08:14:53.47#ibcon#end of sib2, iclass 31, count 2 2006.260.08:14:53.47#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:14:53.47#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:14:53.47#ibcon#[27=AT06-04\r\n] 2006.260.08:14:53.47#ibcon#*before write, iclass 31, count 2 2006.260.08:14:53.47#ibcon#enter sib2, iclass 31, count 2 2006.260.08:14:53.47#ibcon#flushed, iclass 31, count 2 2006.260.08:14:53.47#ibcon#about to write, iclass 31, count 2 2006.260.08:14:53.47#ibcon#wrote, iclass 31, count 2 2006.260.08:14:53.47#ibcon#about to read 3, iclass 31, count 2 2006.260.08:14:53.50#ibcon#read 3, iclass 31, count 2 2006.260.08:14:53.50#ibcon#about to read 4, iclass 31, count 2 2006.260.08:14:53.50#ibcon#read 4, iclass 31, count 2 2006.260.08:14:53.50#ibcon#about to read 5, iclass 31, count 2 2006.260.08:14:53.50#ibcon#read 5, iclass 31, count 2 2006.260.08:14:53.50#ibcon#about to read 6, iclass 31, count 2 2006.260.08:14:53.50#ibcon#read 6, iclass 31, count 2 2006.260.08:14:53.50#ibcon#end of sib2, iclass 31, count 2 2006.260.08:14:53.50#ibcon#*after write, iclass 31, count 2 2006.260.08:14:53.50#ibcon#*before return 0, iclass 31, count 2 2006.260.08:14:53.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:53.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:14:53.50#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:14:53.50#ibcon#ireg 7 cls_cnt 0 2006.260.08:14:53.50#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:53.62#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:53.62#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:53.62#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:14:53.62#ibcon#first serial, iclass 31, count 0 2006.260.08:14:53.62#ibcon#enter sib2, iclass 31, count 0 2006.260.08:14:53.62#ibcon#flushed, iclass 31, count 0 2006.260.08:14:53.62#ibcon#about to write, iclass 31, count 0 2006.260.08:14:53.62#ibcon#wrote, iclass 31, count 0 2006.260.08:14:53.62#ibcon#about to read 3, iclass 31, count 0 2006.260.08:14:53.64#ibcon#read 3, iclass 31, count 0 2006.260.08:14:53.64#ibcon#about to read 4, iclass 31, count 0 2006.260.08:14:53.64#ibcon#read 4, iclass 31, count 0 2006.260.08:14:53.64#ibcon#about to read 5, iclass 31, count 0 2006.260.08:14:53.64#ibcon#read 5, iclass 31, count 0 2006.260.08:14:53.64#ibcon#about to read 6, iclass 31, count 0 2006.260.08:14:53.64#ibcon#read 6, iclass 31, count 0 2006.260.08:14:53.64#ibcon#end of sib2, iclass 31, count 0 2006.260.08:14:53.64#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:14:53.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:14:53.64#ibcon#[27=USB\r\n] 2006.260.08:14:53.64#ibcon#*before write, iclass 31, count 0 2006.260.08:14:53.64#ibcon#enter sib2, iclass 31, count 0 2006.260.08:14:53.64#ibcon#flushed, iclass 31, count 0 2006.260.08:14:53.64#ibcon#about to write, iclass 31, count 0 2006.260.08:14:53.64#ibcon#wrote, iclass 31, count 0 2006.260.08:14:53.64#ibcon#about to read 3, iclass 31, count 0 2006.260.08:14:53.67#ibcon#read 3, iclass 31, count 0 2006.260.08:14:53.67#ibcon#about to read 4, iclass 31, count 0 2006.260.08:14:53.67#ibcon#read 4, iclass 31, count 0 2006.260.08:14:53.67#ibcon#about to read 5, iclass 31, count 0 2006.260.08:14:53.67#ibcon#read 5, iclass 31, count 0 2006.260.08:14:53.67#ibcon#about to read 6, iclass 31, count 0 2006.260.08:14:53.67#ibcon#read 6, iclass 31, count 0 2006.260.08:14:53.67#ibcon#end of sib2, iclass 31, count 0 2006.260.08:14:53.67#ibcon#*after write, iclass 31, count 0 2006.260.08:14:53.67#ibcon#*before return 0, iclass 31, count 0 2006.260.08:14:53.67#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:53.67#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:14:53.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:14:53.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:14:53.67$vc4f8/vabw=wide 2006.260.08:14:53.67#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:14:53.67#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:14:53.67#ibcon#ireg 8 cls_cnt 0 2006.260.08:14:53.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:53.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:53.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:53.67#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:14:53.67#ibcon#first serial, iclass 33, count 0 2006.260.08:14:53.67#ibcon#enter sib2, iclass 33, count 0 2006.260.08:14:53.67#ibcon#flushed, iclass 33, count 0 2006.260.08:14:53.67#ibcon#about to write, iclass 33, count 0 2006.260.08:14:53.67#ibcon#wrote, iclass 33, count 0 2006.260.08:14:53.67#ibcon#about to read 3, iclass 33, count 0 2006.260.08:14:53.69#ibcon#read 3, iclass 33, count 0 2006.260.08:14:53.69#ibcon#about to read 4, iclass 33, count 0 2006.260.08:14:53.69#ibcon#read 4, iclass 33, count 0 2006.260.08:14:53.69#ibcon#about to read 5, iclass 33, count 0 2006.260.08:14:53.69#ibcon#read 5, iclass 33, count 0 2006.260.08:14:53.69#ibcon#about to read 6, iclass 33, count 0 2006.260.08:14:53.69#ibcon#read 6, iclass 33, count 0 2006.260.08:14:53.69#ibcon#end of sib2, iclass 33, count 0 2006.260.08:14:53.69#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:14:53.69#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:14:53.69#ibcon#[25=BW32\r\n] 2006.260.08:14:53.69#ibcon#*before write, iclass 33, count 0 2006.260.08:14:53.69#ibcon#enter sib2, iclass 33, count 0 2006.260.08:14:53.69#ibcon#flushed, iclass 33, count 0 2006.260.08:14:53.69#ibcon#about to write, iclass 33, count 0 2006.260.08:14:53.69#ibcon#wrote, iclass 33, count 0 2006.260.08:14:53.69#ibcon#about to read 3, iclass 33, count 0 2006.260.08:14:53.72#ibcon#read 3, iclass 33, count 0 2006.260.08:14:53.72#ibcon#about to read 4, iclass 33, count 0 2006.260.08:14:53.72#ibcon#read 4, iclass 33, count 0 2006.260.08:14:53.72#ibcon#about to read 5, iclass 33, count 0 2006.260.08:14:53.72#ibcon#read 5, iclass 33, count 0 2006.260.08:14:53.72#ibcon#about to read 6, iclass 33, count 0 2006.260.08:14:53.72#ibcon#read 6, iclass 33, count 0 2006.260.08:14:53.72#ibcon#end of sib2, iclass 33, count 0 2006.260.08:14:53.72#ibcon#*after write, iclass 33, count 0 2006.260.08:14:53.72#ibcon#*before return 0, iclass 33, count 0 2006.260.08:14:53.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:53.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:14:53.72#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:14:53.72#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:14:53.72$vc4f8/vbbw=wide 2006.260.08:14:53.72#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.08:14:53.72#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.08:14:53.72#ibcon#ireg 8 cls_cnt 0 2006.260.08:14:53.72#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:14:53.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:14:53.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:14:53.79#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:14:53.79#ibcon#first serial, iclass 35, count 0 2006.260.08:14:53.79#ibcon#enter sib2, iclass 35, count 0 2006.260.08:14:53.79#ibcon#flushed, iclass 35, count 0 2006.260.08:14:53.79#ibcon#about to write, iclass 35, count 0 2006.260.08:14:53.79#ibcon#wrote, iclass 35, count 0 2006.260.08:14:53.79#ibcon#about to read 3, iclass 35, count 0 2006.260.08:14:53.81#ibcon#read 3, iclass 35, count 0 2006.260.08:14:53.81#ibcon#about to read 4, iclass 35, count 0 2006.260.08:14:53.81#ibcon#read 4, iclass 35, count 0 2006.260.08:14:53.81#ibcon#about to read 5, iclass 35, count 0 2006.260.08:14:53.81#ibcon#read 5, iclass 35, count 0 2006.260.08:14:53.81#ibcon#about to read 6, iclass 35, count 0 2006.260.08:14:53.81#ibcon#read 6, iclass 35, count 0 2006.260.08:14:53.81#ibcon#end of sib2, iclass 35, count 0 2006.260.08:14:53.81#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:14:53.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:14:53.81#ibcon#[27=BW32\r\n] 2006.260.08:14:53.81#ibcon#*before write, iclass 35, count 0 2006.260.08:14:53.81#ibcon#enter sib2, iclass 35, count 0 2006.260.08:14:53.81#ibcon#flushed, iclass 35, count 0 2006.260.08:14:53.81#ibcon#about to write, iclass 35, count 0 2006.260.08:14:53.81#ibcon#wrote, iclass 35, count 0 2006.260.08:14:53.81#ibcon#about to read 3, iclass 35, count 0 2006.260.08:14:53.84#ibcon#read 3, iclass 35, count 0 2006.260.08:14:53.84#ibcon#about to read 4, iclass 35, count 0 2006.260.08:14:53.84#ibcon#read 4, iclass 35, count 0 2006.260.08:14:53.84#ibcon#about to read 5, iclass 35, count 0 2006.260.08:14:53.84#ibcon#read 5, iclass 35, count 0 2006.260.08:14:53.84#ibcon#about to read 6, iclass 35, count 0 2006.260.08:14:53.84#ibcon#read 6, iclass 35, count 0 2006.260.08:14:53.84#ibcon#end of sib2, iclass 35, count 0 2006.260.08:14:53.84#ibcon#*after write, iclass 35, count 0 2006.260.08:14:53.84#ibcon#*before return 0, iclass 35, count 0 2006.260.08:14:53.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:14:53.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:14:53.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:14:53.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:14:53.84$4f8m12a/ifd4f 2006.260.08:14:53.84$ifd4f/lo= 2006.260.08:14:53.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:14:53.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:14:53.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:14:53.84$ifd4f/patch= 2006.260.08:14:53.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:14:53.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:14:53.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:14:53.84$4f8m12a/"form=m,16.000,1:2 2006.260.08:14:53.84$4f8m12a/"tpicd 2006.260.08:14:53.84$4f8m12a/echo=off 2006.260.08:14:53.84$4f8m12a/xlog=off 2006.260.08:14:53.84:!2006.260.08:15:30 2006.260.08:15:12.14#trakl#Source acquired 2006.260.08:15:14.14#flagr#flagr/antenna,acquired 2006.260.08:15:30.00:preob 2006.260.08:15:30.14/onsource/TRACKING 2006.260.08:15:30.14:!2006.260.08:15:40 2006.260.08:15:40.00:data_valid=on 2006.260.08:15:40.00:midob 2006.260.08:15:41.14/onsource/TRACKING 2006.260.08:15:41.14/wx/22.75,1010.3,89 2006.260.08:15:41.23/cable/+6.4566E-03 2006.260.08:15:42.32/va/01,08,usb,yes,31,33 2006.260.08:15:42.32/va/02,07,usb,yes,31,33 2006.260.08:15:42.32/va/03,08,usb,yes,24,24 2006.260.08:15:42.32/va/04,07,usb,yes,32,35 2006.260.08:15:42.32/va/05,07,usb,yes,36,38 2006.260.08:15:42.32/va/06,06,usb,yes,35,35 2006.260.08:15:42.32/va/07,06,usb,yes,36,35 2006.260.08:15:42.32/va/08,06,usb,yes,38,37 2006.260.08:15:42.55/valo/01,532.99,yes,locked 2006.260.08:15:42.55/valo/02,572.99,yes,locked 2006.260.08:15:42.55/valo/03,672.99,yes,locked 2006.260.08:15:42.55/valo/04,832.99,yes,locked 2006.260.08:15:42.55/valo/05,652.99,yes,locked 2006.260.08:15:42.55/valo/06,772.99,yes,locked 2006.260.08:15:42.55/valo/07,832.99,yes,locked 2006.260.08:15:42.55/valo/08,852.99,yes,locked 2006.260.08:15:43.64/vb/01,04,usb,yes,30,29 2006.260.08:15:43.64/vb/02,05,usb,yes,28,29 2006.260.08:15:43.64/vb/03,04,usb,yes,28,32 2006.260.08:15:43.64/vb/04,05,usb,yes,25,26 2006.260.08:15:43.64/vb/05,04,usb,yes,27,31 2006.260.08:15:43.64/vb/06,04,usb,yes,28,31 2006.260.08:15:43.64/vb/07,04,usb,yes,30,30 2006.260.08:15:43.64/vb/08,04,usb,yes,28,31 2006.260.08:15:43.88/vblo/01,632.99,yes,locked 2006.260.08:15:43.88/vblo/02,640.99,yes,locked 2006.260.08:15:43.88/vblo/03,656.99,yes,locked 2006.260.08:15:43.88/vblo/04,712.99,yes,locked 2006.260.08:15:43.88/vblo/05,744.99,yes,locked 2006.260.08:15:43.88/vblo/06,752.99,yes,locked 2006.260.08:15:43.88/vblo/07,734.99,yes,locked 2006.260.08:15:43.88/vblo/08,744.99,yes,locked 2006.260.08:15:44.03/vabw/8 2006.260.08:15:44.18/vbbw/8 2006.260.08:15:44.27/xfe/off,on,15.2 2006.260.08:15:44.66/ifatt/23,28,28,28 2006.260.08:15:45.08/fmout-gps/S +4.46E-07 2006.260.08:15:45.12:!2006.260.08:16:40 2006.260.08:16:40.00:data_valid=off 2006.260.08:16:40.00:postob 2006.260.08:16:40.24/cable/+6.4567E-03 2006.260.08:16:40.24/wx/22.74,1010.3,89 2006.260.08:16:41.08/fmout-gps/S +4.47E-07 2006.260.08:16:41.08:scan_name=260-0817,k06260,60 2006.260.08:16:41.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.260.08:16:41.14#flagr#flagr/antenna,new-source 2006.260.08:16:42.14:checkk5 2006.260.08:16:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:16:42.93/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:16:43.38/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:16:43.80/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:16:44.22/chk_obsdata//k5ts1/T2600815??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:16:44.60/chk_obsdata//k5ts2/T2600815??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:16:45.02/chk_obsdata//k5ts3/T2600815??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:16:45.41/chk_obsdata//k5ts4/T2600815??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:16:46.21/k5log//k5ts1_log_newline 2006.260.08:16:46.97/k5log//k5ts2_log_newline 2006.260.08:16:47.93/k5log//k5ts3_log_newline 2006.260.08:16:48.76/k5log//k5ts4_log_newline 2006.260.08:16:48.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:16:48.79:4f8m12a=2 2006.260.08:16:48.79$4f8m12a/echo=on 2006.260.08:16:48.79$4f8m12a/pcalon 2006.260.08:16:48.79$pcalon/"no phase cal control is implemented here 2006.260.08:16:48.79$4f8m12a/"tpicd=stop 2006.260.08:16:48.79$4f8m12a/vc4f8 2006.260.08:16:48.79$vc4f8/valo=1,532.99 2006.260.08:16:48.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.260.08:16:48.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.260.08:16:48.79#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:48.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:16:48.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:16:48.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:16:48.79#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:16:48.79#ibcon#first serial, iclass 10, count 0 2006.260.08:16:48.79#ibcon#enter sib2, iclass 10, count 0 2006.260.08:16:48.79#ibcon#flushed, iclass 10, count 0 2006.260.08:16:48.79#ibcon#about to write, iclass 10, count 0 2006.260.08:16:48.79#ibcon#wrote, iclass 10, count 0 2006.260.08:16:48.79#ibcon#about to read 3, iclass 10, count 0 2006.260.08:16:48.84#ibcon#read 3, iclass 10, count 0 2006.260.08:16:48.84#ibcon#about to read 4, iclass 10, count 0 2006.260.08:16:48.84#ibcon#read 4, iclass 10, count 0 2006.260.08:16:48.84#ibcon#about to read 5, iclass 10, count 0 2006.260.08:16:48.84#ibcon#read 5, iclass 10, count 0 2006.260.08:16:48.84#ibcon#about to read 6, iclass 10, count 0 2006.260.08:16:48.84#ibcon#read 6, iclass 10, count 0 2006.260.08:16:48.84#ibcon#end of sib2, iclass 10, count 0 2006.260.08:16:48.84#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:16:48.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:16:48.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:16:48.84#ibcon#*before write, iclass 10, count 0 2006.260.08:16:48.84#ibcon#enter sib2, iclass 10, count 0 2006.260.08:16:48.84#ibcon#flushed, iclass 10, count 0 2006.260.08:16:48.84#ibcon#about to write, iclass 10, count 0 2006.260.08:16:48.84#ibcon#wrote, iclass 10, count 0 2006.260.08:16:48.84#ibcon#about to read 3, iclass 10, count 0 2006.260.08:16:48.89#ibcon#read 3, iclass 10, count 0 2006.260.08:16:48.89#ibcon#about to read 4, iclass 10, count 0 2006.260.08:16:48.89#ibcon#read 4, iclass 10, count 0 2006.260.08:16:48.89#ibcon#about to read 5, iclass 10, count 0 2006.260.08:16:48.89#ibcon#read 5, iclass 10, count 0 2006.260.08:16:48.89#ibcon#about to read 6, iclass 10, count 0 2006.260.08:16:48.89#ibcon#read 6, iclass 10, count 0 2006.260.08:16:48.89#ibcon#end of sib2, iclass 10, count 0 2006.260.08:16:48.89#ibcon#*after write, iclass 10, count 0 2006.260.08:16:48.89#ibcon#*before return 0, iclass 10, count 0 2006.260.08:16:48.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:16:48.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.260.08:16:48.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:16:48.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:16:48.89$vc4f8/va=1,8 2006.260.08:16:48.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.260.08:16:48.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.260.08:16:48.89#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:48.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:16:48.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:16:48.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:16:48.89#ibcon#enter wrdev, iclass 12, count 2 2006.260.08:16:48.89#ibcon#first serial, iclass 12, count 2 2006.260.08:16:48.89#ibcon#enter sib2, iclass 12, count 2 2006.260.08:16:48.89#ibcon#flushed, iclass 12, count 2 2006.260.08:16:48.89#ibcon#about to write, iclass 12, count 2 2006.260.08:16:48.89#ibcon#wrote, iclass 12, count 2 2006.260.08:16:48.89#ibcon#about to read 3, iclass 12, count 2 2006.260.08:16:48.91#ibcon#read 3, iclass 12, count 2 2006.260.08:16:48.91#ibcon#about to read 4, iclass 12, count 2 2006.260.08:16:48.91#ibcon#read 4, iclass 12, count 2 2006.260.08:16:48.91#ibcon#about to read 5, iclass 12, count 2 2006.260.08:16:48.91#ibcon#read 5, iclass 12, count 2 2006.260.08:16:48.91#ibcon#about to read 6, iclass 12, count 2 2006.260.08:16:48.91#ibcon#read 6, iclass 12, count 2 2006.260.08:16:48.91#ibcon#end of sib2, iclass 12, count 2 2006.260.08:16:48.91#ibcon#*mode == 0, iclass 12, count 2 2006.260.08:16:48.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.260.08:16:48.91#ibcon#[25=AT01-08\r\n] 2006.260.08:16:48.91#ibcon#*before write, iclass 12, count 2 2006.260.08:16:48.91#ibcon#enter sib2, iclass 12, count 2 2006.260.08:16:48.91#ibcon#flushed, iclass 12, count 2 2006.260.08:16:48.91#ibcon#about to write, iclass 12, count 2 2006.260.08:16:48.91#ibcon#wrote, iclass 12, count 2 2006.260.08:16:48.91#ibcon#about to read 3, iclass 12, count 2 2006.260.08:16:48.95#ibcon#read 3, iclass 12, count 2 2006.260.08:16:48.95#ibcon#about to read 4, iclass 12, count 2 2006.260.08:16:48.95#ibcon#read 4, iclass 12, count 2 2006.260.08:16:48.95#ibcon#about to read 5, iclass 12, count 2 2006.260.08:16:48.95#ibcon#read 5, iclass 12, count 2 2006.260.08:16:48.95#ibcon#about to read 6, iclass 12, count 2 2006.260.08:16:48.95#ibcon#read 6, iclass 12, count 2 2006.260.08:16:48.95#ibcon#end of sib2, iclass 12, count 2 2006.260.08:16:48.95#ibcon#*after write, iclass 12, count 2 2006.260.08:16:48.95#ibcon#*before return 0, iclass 12, count 2 2006.260.08:16:48.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:16:48.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.260.08:16:48.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.260.08:16:48.95#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:48.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:16:49.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:16:49.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:16:49.07#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:16:49.07#ibcon#first serial, iclass 12, count 0 2006.260.08:16:49.07#ibcon#enter sib2, iclass 12, count 0 2006.260.08:16:49.07#ibcon#flushed, iclass 12, count 0 2006.260.08:16:49.07#ibcon#about to write, iclass 12, count 0 2006.260.08:16:49.07#ibcon#wrote, iclass 12, count 0 2006.260.08:16:49.07#ibcon#about to read 3, iclass 12, count 0 2006.260.08:16:49.09#ibcon#read 3, iclass 12, count 0 2006.260.08:16:49.09#ibcon#about to read 4, iclass 12, count 0 2006.260.08:16:49.09#ibcon#read 4, iclass 12, count 0 2006.260.08:16:49.09#ibcon#about to read 5, iclass 12, count 0 2006.260.08:16:49.09#ibcon#read 5, iclass 12, count 0 2006.260.08:16:49.09#ibcon#about to read 6, iclass 12, count 0 2006.260.08:16:49.09#ibcon#read 6, iclass 12, count 0 2006.260.08:16:49.09#ibcon#end of sib2, iclass 12, count 0 2006.260.08:16:49.09#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:16:49.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:16:49.09#ibcon#[25=USB\r\n] 2006.260.08:16:49.09#ibcon#*before write, iclass 12, count 0 2006.260.08:16:49.09#ibcon#enter sib2, iclass 12, count 0 2006.260.08:16:49.09#ibcon#flushed, iclass 12, count 0 2006.260.08:16:49.09#ibcon#about to write, iclass 12, count 0 2006.260.08:16:49.09#ibcon#wrote, iclass 12, count 0 2006.260.08:16:49.09#ibcon#about to read 3, iclass 12, count 0 2006.260.08:16:49.12#ibcon#read 3, iclass 12, count 0 2006.260.08:16:49.12#ibcon#about to read 4, iclass 12, count 0 2006.260.08:16:49.12#ibcon#read 4, iclass 12, count 0 2006.260.08:16:49.12#ibcon#about to read 5, iclass 12, count 0 2006.260.08:16:49.12#ibcon#read 5, iclass 12, count 0 2006.260.08:16:49.12#ibcon#about to read 6, iclass 12, count 0 2006.260.08:16:49.12#ibcon#read 6, iclass 12, count 0 2006.260.08:16:49.12#ibcon#end of sib2, iclass 12, count 0 2006.260.08:16:49.12#ibcon#*after write, iclass 12, count 0 2006.260.08:16:49.12#ibcon#*before return 0, iclass 12, count 0 2006.260.08:16:49.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:16:49.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.260.08:16:49.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:16:49.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:16:49.12$vc4f8/valo=2,572.99 2006.260.08:16:49.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:16:49.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:16:49.12#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:49.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:49.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:49.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:49.12#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:16:49.12#ibcon#first serial, iclass 14, count 0 2006.260.08:16:49.12#ibcon#enter sib2, iclass 14, count 0 2006.260.08:16:49.12#ibcon#flushed, iclass 14, count 0 2006.260.08:16:49.12#ibcon#about to write, iclass 14, count 0 2006.260.08:16:49.12#ibcon#wrote, iclass 14, count 0 2006.260.08:16:49.12#ibcon#about to read 3, iclass 14, count 0 2006.260.08:16:49.14#ibcon#read 3, iclass 14, count 0 2006.260.08:16:49.14#ibcon#about to read 4, iclass 14, count 0 2006.260.08:16:49.14#ibcon#read 4, iclass 14, count 0 2006.260.08:16:49.14#ibcon#about to read 5, iclass 14, count 0 2006.260.08:16:49.14#ibcon#read 5, iclass 14, count 0 2006.260.08:16:49.14#ibcon#about to read 6, iclass 14, count 0 2006.260.08:16:49.14#ibcon#read 6, iclass 14, count 0 2006.260.08:16:49.14#ibcon#end of sib2, iclass 14, count 0 2006.260.08:16:49.14#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:16:49.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:16:49.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:16:49.14#ibcon#*before write, iclass 14, count 0 2006.260.08:16:49.14#ibcon#enter sib2, iclass 14, count 0 2006.260.08:16:49.14#ibcon#flushed, iclass 14, count 0 2006.260.08:16:49.14#ibcon#about to write, iclass 14, count 0 2006.260.08:16:49.14#ibcon#wrote, iclass 14, count 0 2006.260.08:16:49.14#ibcon#about to read 3, iclass 14, count 0 2006.260.08:16:49.18#ibcon#read 3, iclass 14, count 0 2006.260.08:16:49.18#ibcon#about to read 4, iclass 14, count 0 2006.260.08:16:49.18#ibcon#read 4, iclass 14, count 0 2006.260.08:16:49.18#ibcon#about to read 5, iclass 14, count 0 2006.260.08:16:49.18#ibcon#read 5, iclass 14, count 0 2006.260.08:16:49.18#ibcon#about to read 6, iclass 14, count 0 2006.260.08:16:49.18#ibcon#read 6, iclass 14, count 0 2006.260.08:16:49.18#ibcon#end of sib2, iclass 14, count 0 2006.260.08:16:49.18#ibcon#*after write, iclass 14, count 0 2006.260.08:16:49.18#ibcon#*before return 0, iclass 14, count 0 2006.260.08:16:49.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:49.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:49.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:16:49.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:16:49.18$vc4f8/va=2,7 2006.260.08:16:49.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.08:16:49.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.08:16:49.18#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:49.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:49.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:49.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:49.24#ibcon#enter wrdev, iclass 16, count 2 2006.260.08:16:49.24#ibcon#first serial, iclass 16, count 2 2006.260.08:16:49.24#ibcon#enter sib2, iclass 16, count 2 2006.260.08:16:49.24#ibcon#flushed, iclass 16, count 2 2006.260.08:16:49.24#ibcon#about to write, iclass 16, count 2 2006.260.08:16:49.24#ibcon#wrote, iclass 16, count 2 2006.260.08:16:49.24#ibcon#about to read 3, iclass 16, count 2 2006.260.08:16:49.26#ibcon#read 3, iclass 16, count 2 2006.260.08:16:49.26#ibcon#about to read 4, iclass 16, count 2 2006.260.08:16:49.26#ibcon#read 4, iclass 16, count 2 2006.260.08:16:49.26#ibcon#about to read 5, iclass 16, count 2 2006.260.08:16:49.26#ibcon#read 5, iclass 16, count 2 2006.260.08:16:49.26#ibcon#about to read 6, iclass 16, count 2 2006.260.08:16:49.26#ibcon#read 6, iclass 16, count 2 2006.260.08:16:49.26#ibcon#end of sib2, iclass 16, count 2 2006.260.08:16:49.26#ibcon#*mode == 0, iclass 16, count 2 2006.260.08:16:49.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.08:16:49.26#ibcon#[25=AT02-07\r\n] 2006.260.08:16:49.26#ibcon#*before write, iclass 16, count 2 2006.260.08:16:49.26#ibcon#enter sib2, iclass 16, count 2 2006.260.08:16:49.26#ibcon#flushed, iclass 16, count 2 2006.260.08:16:49.26#ibcon#about to write, iclass 16, count 2 2006.260.08:16:49.26#ibcon#wrote, iclass 16, count 2 2006.260.08:16:49.26#ibcon#about to read 3, iclass 16, count 2 2006.260.08:16:49.29#ibcon#read 3, iclass 16, count 2 2006.260.08:16:49.29#ibcon#about to read 4, iclass 16, count 2 2006.260.08:16:49.29#ibcon#read 4, iclass 16, count 2 2006.260.08:16:49.29#ibcon#about to read 5, iclass 16, count 2 2006.260.08:16:49.29#ibcon#read 5, iclass 16, count 2 2006.260.08:16:49.29#ibcon#about to read 6, iclass 16, count 2 2006.260.08:16:49.29#ibcon#read 6, iclass 16, count 2 2006.260.08:16:49.29#ibcon#end of sib2, iclass 16, count 2 2006.260.08:16:49.29#ibcon#*after write, iclass 16, count 2 2006.260.08:16:49.29#ibcon#*before return 0, iclass 16, count 2 2006.260.08:16:49.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:49.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:49.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.08:16:49.29#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:49.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:49.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:49.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:49.42#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:16:49.42#ibcon#first serial, iclass 16, count 0 2006.260.08:16:49.42#ibcon#enter sib2, iclass 16, count 0 2006.260.08:16:49.42#ibcon#flushed, iclass 16, count 0 2006.260.08:16:49.42#ibcon#about to write, iclass 16, count 0 2006.260.08:16:49.42#ibcon#wrote, iclass 16, count 0 2006.260.08:16:49.42#ibcon#about to read 3, iclass 16, count 0 2006.260.08:16:49.44#ibcon#read 3, iclass 16, count 0 2006.260.08:16:49.44#ibcon#about to read 4, iclass 16, count 0 2006.260.08:16:49.44#ibcon#read 4, iclass 16, count 0 2006.260.08:16:49.44#ibcon#about to read 5, iclass 16, count 0 2006.260.08:16:49.44#ibcon#read 5, iclass 16, count 0 2006.260.08:16:49.44#ibcon#about to read 6, iclass 16, count 0 2006.260.08:16:49.44#ibcon#read 6, iclass 16, count 0 2006.260.08:16:49.44#ibcon#end of sib2, iclass 16, count 0 2006.260.08:16:49.44#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:16:49.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:16:49.44#ibcon#[25=USB\r\n] 2006.260.08:16:49.44#ibcon#*before write, iclass 16, count 0 2006.260.08:16:49.44#ibcon#enter sib2, iclass 16, count 0 2006.260.08:16:49.44#ibcon#flushed, iclass 16, count 0 2006.260.08:16:49.44#ibcon#about to write, iclass 16, count 0 2006.260.08:16:49.44#ibcon#wrote, iclass 16, count 0 2006.260.08:16:49.44#ibcon#about to read 3, iclass 16, count 0 2006.260.08:16:49.47#ibcon#read 3, iclass 16, count 0 2006.260.08:16:49.47#ibcon#about to read 4, iclass 16, count 0 2006.260.08:16:49.47#ibcon#read 4, iclass 16, count 0 2006.260.08:16:49.47#ibcon#about to read 5, iclass 16, count 0 2006.260.08:16:49.47#ibcon#read 5, iclass 16, count 0 2006.260.08:16:49.47#ibcon#about to read 6, iclass 16, count 0 2006.260.08:16:49.47#ibcon#read 6, iclass 16, count 0 2006.260.08:16:49.47#ibcon#end of sib2, iclass 16, count 0 2006.260.08:16:49.47#ibcon#*after write, iclass 16, count 0 2006.260.08:16:49.47#ibcon#*before return 0, iclass 16, count 0 2006.260.08:16:49.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:49.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:49.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:16:49.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:16:49.47$vc4f8/valo=3,672.99 2006.260.08:16:49.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.08:16:49.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.08:16:49.47#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:49.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:49.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:49.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:49.47#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:16:49.47#ibcon#first serial, iclass 18, count 0 2006.260.08:16:49.47#ibcon#enter sib2, iclass 18, count 0 2006.260.08:16:49.47#ibcon#flushed, iclass 18, count 0 2006.260.08:16:49.47#ibcon#about to write, iclass 18, count 0 2006.260.08:16:49.47#ibcon#wrote, iclass 18, count 0 2006.260.08:16:49.47#ibcon#about to read 3, iclass 18, count 0 2006.260.08:16:49.49#ibcon#read 3, iclass 18, count 0 2006.260.08:16:49.49#ibcon#about to read 4, iclass 18, count 0 2006.260.08:16:49.49#ibcon#read 4, iclass 18, count 0 2006.260.08:16:49.49#ibcon#about to read 5, iclass 18, count 0 2006.260.08:16:49.49#ibcon#read 5, iclass 18, count 0 2006.260.08:16:49.49#ibcon#about to read 6, iclass 18, count 0 2006.260.08:16:49.49#ibcon#read 6, iclass 18, count 0 2006.260.08:16:49.49#ibcon#end of sib2, iclass 18, count 0 2006.260.08:16:49.49#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:16:49.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:16:49.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:16:49.49#ibcon#*before write, iclass 18, count 0 2006.260.08:16:49.49#ibcon#enter sib2, iclass 18, count 0 2006.260.08:16:49.49#ibcon#flushed, iclass 18, count 0 2006.260.08:16:49.49#ibcon#about to write, iclass 18, count 0 2006.260.08:16:49.49#ibcon#wrote, iclass 18, count 0 2006.260.08:16:49.49#ibcon#about to read 3, iclass 18, count 0 2006.260.08:16:49.53#ibcon#read 3, iclass 18, count 0 2006.260.08:16:49.53#ibcon#about to read 4, iclass 18, count 0 2006.260.08:16:49.53#ibcon#read 4, iclass 18, count 0 2006.260.08:16:49.53#ibcon#about to read 5, iclass 18, count 0 2006.260.08:16:49.53#ibcon#read 5, iclass 18, count 0 2006.260.08:16:49.53#ibcon#about to read 6, iclass 18, count 0 2006.260.08:16:49.53#ibcon#read 6, iclass 18, count 0 2006.260.08:16:49.53#ibcon#end of sib2, iclass 18, count 0 2006.260.08:16:49.53#ibcon#*after write, iclass 18, count 0 2006.260.08:16:49.53#ibcon#*before return 0, iclass 18, count 0 2006.260.08:16:49.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:49.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:49.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:16:49.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:16:49.53$vc4f8/va=3,8 2006.260.08:16:49.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.08:16:49.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.08:16:49.53#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:49.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:49.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:49.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:49.59#ibcon#enter wrdev, iclass 20, count 2 2006.260.08:16:49.59#ibcon#first serial, iclass 20, count 2 2006.260.08:16:49.59#ibcon#enter sib2, iclass 20, count 2 2006.260.08:16:49.59#ibcon#flushed, iclass 20, count 2 2006.260.08:16:49.59#ibcon#about to write, iclass 20, count 2 2006.260.08:16:49.59#ibcon#wrote, iclass 20, count 2 2006.260.08:16:49.59#ibcon#about to read 3, iclass 20, count 2 2006.260.08:16:49.61#ibcon#read 3, iclass 20, count 2 2006.260.08:16:49.61#ibcon#about to read 4, iclass 20, count 2 2006.260.08:16:49.61#ibcon#read 4, iclass 20, count 2 2006.260.08:16:49.61#ibcon#about to read 5, iclass 20, count 2 2006.260.08:16:49.61#ibcon#read 5, iclass 20, count 2 2006.260.08:16:49.61#ibcon#about to read 6, iclass 20, count 2 2006.260.08:16:49.61#ibcon#read 6, iclass 20, count 2 2006.260.08:16:49.61#ibcon#end of sib2, iclass 20, count 2 2006.260.08:16:49.61#ibcon#*mode == 0, iclass 20, count 2 2006.260.08:16:49.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.08:16:49.61#ibcon#[25=AT03-08\r\n] 2006.260.08:16:49.61#ibcon#*before write, iclass 20, count 2 2006.260.08:16:49.61#ibcon#enter sib2, iclass 20, count 2 2006.260.08:16:49.61#ibcon#flushed, iclass 20, count 2 2006.260.08:16:49.61#ibcon#about to write, iclass 20, count 2 2006.260.08:16:49.61#ibcon#wrote, iclass 20, count 2 2006.260.08:16:49.61#ibcon#about to read 3, iclass 20, count 2 2006.260.08:16:49.64#ibcon#read 3, iclass 20, count 2 2006.260.08:16:49.64#ibcon#about to read 4, iclass 20, count 2 2006.260.08:16:49.64#ibcon#read 4, iclass 20, count 2 2006.260.08:16:49.64#ibcon#about to read 5, iclass 20, count 2 2006.260.08:16:49.64#ibcon#read 5, iclass 20, count 2 2006.260.08:16:49.64#ibcon#about to read 6, iclass 20, count 2 2006.260.08:16:49.64#ibcon#read 6, iclass 20, count 2 2006.260.08:16:49.64#ibcon#end of sib2, iclass 20, count 2 2006.260.08:16:49.64#ibcon#*after write, iclass 20, count 2 2006.260.08:16:49.64#ibcon#*before return 0, iclass 20, count 2 2006.260.08:16:49.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:49.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:49.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.08:16:49.64#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:49.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:49.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:49.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:49.76#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:16:49.76#ibcon#first serial, iclass 20, count 0 2006.260.08:16:49.76#ibcon#enter sib2, iclass 20, count 0 2006.260.08:16:49.76#ibcon#flushed, iclass 20, count 0 2006.260.08:16:49.76#ibcon#about to write, iclass 20, count 0 2006.260.08:16:49.76#ibcon#wrote, iclass 20, count 0 2006.260.08:16:49.76#ibcon#about to read 3, iclass 20, count 0 2006.260.08:16:49.78#ibcon#read 3, iclass 20, count 0 2006.260.08:16:49.78#ibcon#about to read 4, iclass 20, count 0 2006.260.08:16:49.78#ibcon#read 4, iclass 20, count 0 2006.260.08:16:49.78#ibcon#about to read 5, iclass 20, count 0 2006.260.08:16:49.78#ibcon#read 5, iclass 20, count 0 2006.260.08:16:49.78#ibcon#about to read 6, iclass 20, count 0 2006.260.08:16:49.78#ibcon#read 6, iclass 20, count 0 2006.260.08:16:49.78#ibcon#end of sib2, iclass 20, count 0 2006.260.08:16:49.78#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:16:49.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:16:49.78#ibcon#[25=USB\r\n] 2006.260.08:16:49.78#ibcon#*before write, iclass 20, count 0 2006.260.08:16:49.78#ibcon#enter sib2, iclass 20, count 0 2006.260.08:16:49.78#ibcon#flushed, iclass 20, count 0 2006.260.08:16:49.78#ibcon#about to write, iclass 20, count 0 2006.260.08:16:49.78#ibcon#wrote, iclass 20, count 0 2006.260.08:16:49.78#ibcon#about to read 3, iclass 20, count 0 2006.260.08:16:49.81#ibcon#read 3, iclass 20, count 0 2006.260.08:16:49.81#ibcon#about to read 4, iclass 20, count 0 2006.260.08:16:49.81#ibcon#read 4, iclass 20, count 0 2006.260.08:16:49.81#ibcon#about to read 5, iclass 20, count 0 2006.260.08:16:49.81#ibcon#read 5, iclass 20, count 0 2006.260.08:16:49.81#ibcon#about to read 6, iclass 20, count 0 2006.260.08:16:49.81#ibcon#read 6, iclass 20, count 0 2006.260.08:16:49.81#ibcon#end of sib2, iclass 20, count 0 2006.260.08:16:49.81#ibcon#*after write, iclass 20, count 0 2006.260.08:16:49.81#ibcon#*before return 0, iclass 20, count 0 2006.260.08:16:49.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:49.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:49.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:16:49.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:16:49.81$vc4f8/valo=4,832.99 2006.260.08:16:49.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.08:16:49.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.08:16:49.81#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:49.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:49.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:49.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:49.81#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:16:49.81#ibcon#first serial, iclass 22, count 0 2006.260.08:16:49.81#ibcon#enter sib2, iclass 22, count 0 2006.260.08:16:49.81#ibcon#flushed, iclass 22, count 0 2006.260.08:16:49.81#ibcon#about to write, iclass 22, count 0 2006.260.08:16:49.81#ibcon#wrote, iclass 22, count 0 2006.260.08:16:49.81#ibcon#about to read 3, iclass 22, count 0 2006.260.08:16:49.83#ibcon#read 3, iclass 22, count 0 2006.260.08:16:49.83#ibcon#about to read 4, iclass 22, count 0 2006.260.08:16:49.83#ibcon#read 4, iclass 22, count 0 2006.260.08:16:49.83#ibcon#about to read 5, iclass 22, count 0 2006.260.08:16:49.83#ibcon#read 5, iclass 22, count 0 2006.260.08:16:49.83#ibcon#about to read 6, iclass 22, count 0 2006.260.08:16:49.83#ibcon#read 6, iclass 22, count 0 2006.260.08:16:49.83#ibcon#end of sib2, iclass 22, count 0 2006.260.08:16:49.83#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:16:49.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:16:49.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:16:49.83#ibcon#*before write, iclass 22, count 0 2006.260.08:16:49.83#ibcon#enter sib2, iclass 22, count 0 2006.260.08:16:49.83#ibcon#flushed, iclass 22, count 0 2006.260.08:16:49.83#ibcon#about to write, iclass 22, count 0 2006.260.08:16:49.83#ibcon#wrote, iclass 22, count 0 2006.260.08:16:49.83#ibcon#about to read 3, iclass 22, count 0 2006.260.08:16:49.87#ibcon#read 3, iclass 22, count 0 2006.260.08:16:49.87#ibcon#about to read 4, iclass 22, count 0 2006.260.08:16:49.87#ibcon#read 4, iclass 22, count 0 2006.260.08:16:49.87#ibcon#about to read 5, iclass 22, count 0 2006.260.08:16:49.87#ibcon#read 5, iclass 22, count 0 2006.260.08:16:49.87#ibcon#about to read 6, iclass 22, count 0 2006.260.08:16:49.87#ibcon#read 6, iclass 22, count 0 2006.260.08:16:49.87#ibcon#end of sib2, iclass 22, count 0 2006.260.08:16:49.87#ibcon#*after write, iclass 22, count 0 2006.260.08:16:49.87#ibcon#*before return 0, iclass 22, count 0 2006.260.08:16:49.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:49.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:49.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:16:49.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:16:49.87$vc4f8/va=4,7 2006.260.08:16:49.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.08:16:49.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.08:16:49.87#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:49.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:49.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:49.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:49.93#ibcon#enter wrdev, iclass 24, count 2 2006.260.08:16:49.93#ibcon#first serial, iclass 24, count 2 2006.260.08:16:49.93#ibcon#enter sib2, iclass 24, count 2 2006.260.08:16:49.93#ibcon#flushed, iclass 24, count 2 2006.260.08:16:49.93#ibcon#about to write, iclass 24, count 2 2006.260.08:16:49.93#ibcon#wrote, iclass 24, count 2 2006.260.08:16:49.93#ibcon#about to read 3, iclass 24, count 2 2006.260.08:16:49.95#ibcon#read 3, iclass 24, count 2 2006.260.08:16:49.95#ibcon#about to read 4, iclass 24, count 2 2006.260.08:16:49.95#ibcon#read 4, iclass 24, count 2 2006.260.08:16:49.95#ibcon#about to read 5, iclass 24, count 2 2006.260.08:16:49.95#ibcon#read 5, iclass 24, count 2 2006.260.08:16:49.95#ibcon#about to read 6, iclass 24, count 2 2006.260.08:16:49.95#ibcon#read 6, iclass 24, count 2 2006.260.08:16:49.95#ibcon#end of sib2, iclass 24, count 2 2006.260.08:16:49.95#ibcon#*mode == 0, iclass 24, count 2 2006.260.08:16:49.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.08:16:49.95#ibcon#[25=AT04-07\r\n] 2006.260.08:16:49.95#ibcon#*before write, iclass 24, count 2 2006.260.08:16:49.95#ibcon#enter sib2, iclass 24, count 2 2006.260.08:16:49.95#ibcon#flushed, iclass 24, count 2 2006.260.08:16:49.95#ibcon#about to write, iclass 24, count 2 2006.260.08:16:49.95#ibcon#wrote, iclass 24, count 2 2006.260.08:16:49.95#ibcon#about to read 3, iclass 24, count 2 2006.260.08:16:49.98#ibcon#read 3, iclass 24, count 2 2006.260.08:16:49.98#ibcon#about to read 4, iclass 24, count 2 2006.260.08:16:49.98#ibcon#read 4, iclass 24, count 2 2006.260.08:16:49.98#ibcon#about to read 5, iclass 24, count 2 2006.260.08:16:49.98#ibcon#read 5, iclass 24, count 2 2006.260.08:16:49.98#ibcon#about to read 6, iclass 24, count 2 2006.260.08:16:49.98#ibcon#read 6, iclass 24, count 2 2006.260.08:16:49.98#ibcon#end of sib2, iclass 24, count 2 2006.260.08:16:49.98#ibcon#*after write, iclass 24, count 2 2006.260.08:16:49.98#ibcon#*before return 0, iclass 24, count 2 2006.260.08:16:49.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:49.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:49.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.08:16:49.98#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:49.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:50.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:50.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:50.10#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:16:50.10#ibcon#first serial, iclass 24, count 0 2006.260.08:16:50.10#ibcon#enter sib2, iclass 24, count 0 2006.260.08:16:50.10#ibcon#flushed, iclass 24, count 0 2006.260.08:16:50.10#ibcon#about to write, iclass 24, count 0 2006.260.08:16:50.10#ibcon#wrote, iclass 24, count 0 2006.260.08:16:50.10#ibcon#about to read 3, iclass 24, count 0 2006.260.08:16:50.12#ibcon#read 3, iclass 24, count 0 2006.260.08:16:50.12#ibcon#about to read 4, iclass 24, count 0 2006.260.08:16:50.12#ibcon#read 4, iclass 24, count 0 2006.260.08:16:50.12#ibcon#about to read 5, iclass 24, count 0 2006.260.08:16:50.12#ibcon#read 5, iclass 24, count 0 2006.260.08:16:50.12#ibcon#about to read 6, iclass 24, count 0 2006.260.08:16:50.12#ibcon#read 6, iclass 24, count 0 2006.260.08:16:50.12#ibcon#end of sib2, iclass 24, count 0 2006.260.08:16:50.12#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:16:50.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:16:50.12#ibcon#[25=USB\r\n] 2006.260.08:16:50.12#ibcon#*before write, iclass 24, count 0 2006.260.08:16:50.12#ibcon#enter sib2, iclass 24, count 0 2006.260.08:16:50.12#ibcon#flushed, iclass 24, count 0 2006.260.08:16:50.12#ibcon#about to write, iclass 24, count 0 2006.260.08:16:50.12#ibcon#wrote, iclass 24, count 0 2006.260.08:16:50.12#ibcon#about to read 3, iclass 24, count 0 2006.260.08:16:50.15#ibcon#read 3, iclass 24, count 0 2006.260.08:16:50.15#ibcon#about to read 4, iclass 24, count 0 2006.260.08:16:50.15#ibcon#read 4, iclass 24, count 0 2006.260.08:16:50.15#ibcon#about to read 5, iclass 24, count 0 2006.260.08:16:50.15#ibcon#read 5, iclass 24, count 0 2006.260.08:16:50.15#ibcon#about to read 6, iclass 24, count 0 2006.260.08:16:50.15#ibcon#read 6, iclass 24, count 0 2006.260.08:16:50.15#ibcon#end of sib2, iclass 24, count 0 2006.260.08:16:50.15#ibcon#*after write, iclass 24, count 0 2006.260.08:16:50.15#ibcon#*before return 0, iclass 24, count 0 2006.260.08:16:50.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:50.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:50.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:16:50.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:16:50.15$vc4f8/valo=5,652.99 2006.260.08:16:50.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.08:16:50.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.08:16:50.15#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:50.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:50.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:50.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:50.15#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:16:50.15#ibcon#first serial, iclass 26, count 0 2006.260.08:16:50.15#ibcon#enter sib2, iclass 26, count 0 2006.260.08:16:50.15#ibcon#flushed, iclass 26, count 0 2006.260.08:16:50.15#ibcon#about to write, iclass 26, count 0 2006.260.08:16:50.15#ibcon#wrote, iclass 26, count 0 2006.260.08:16:50.15#ibcon#about to read 3, iclass 26, count 0 2006.260.08:16:50.17#ibcon#read 3, iclass 26, count 0 2006.260.08:16:50.17#ibcon#about to read 4, iclass 26, count 0 2006.260.08:16:50.17#ibcon#read 4, iclass 26, count 0 2006.260.08:16:50.17#ibcon#about to read 5, iclass 26, count 0 2006.260.08:16:50.17#ibcon#read 5, iclass 26, count 0 2006.260.08:16:50.17#ibcon#about to read 6, iclass 26, count 0 2006.260.08:16:50.17#ibcon#read 6, iclass 26, count 0 2006.260.08:16:50.17#ibcon#end of sib2, iclass 26, count 0 2006.260.08:16:50.17#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:16:50.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:16:50.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:16:50.17#ibcon#*before write, iclass 26, count 0 2006.260.08:16:50.17#ibcon#enter sib2, iclass 26, count 0 2006.260.08:16:50.17#ibcon#flushed, iclass 26, count 0 2006.260.08:16:50.17#ibcon#about to write, iclass 26, count 0 2006.260.08:16:50.17#ibcon#wrote, iclass 26, count 0 2006.260.08:16:50.17#ibcon#about to read 3, iclass 26, count 0 2006.260.08:16:50.21#ibcon#read 3, iclass 26, count 0 2006.260.08:16:50.21#ibcon#about to read 4, iclass 26, count 0 2006.260.08:16:50.21#ibcon#read 4, iclass 26, count 0 2006.260.08:16:50.21#ibcon#about to read 5, iclass 26, count 0 2006.260.08:16:50.21#ibcon#read 5, iclass 26, count 0 2006.260.08:16:50.21#ibcon#about to read 6, iclass 26, count 0 2006.260.08:16:50.21#ibcon#read 6, iclass 26, count 0 2006.260.08:16:50.21#ibcon#end of sib2, iclass 26, count 0 2006.260.08:16:50.21#ibcon#*after write, iclass 26, count 0 2006.260.08:16:50.21#ibcon#*before return 0, iclass 26, count 0 2006.260.08:16:50.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:50.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:50.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:16:50.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:16:50.21$vc4f8/va=5,7 2006.260.08:16:50.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.08:16:50.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.08:16:50.21#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:50.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:50.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:50.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:50.27#ibcon#enter wrdev, iclass 28, count 2 2006.260.08:16:50.27#ibcon#first serial, iclass 28, count 2 2006.260.08:16:50.27#ibcon#enter sib2, iclass 28, count 2 2006.260.08:16:50.27#ibcon#flushed, iclass 28, count 2 2006.260.08:16:50.27#ibcon#about to write, iclass 28, count 2 2006.260.08:16:50.27#ibcon#wrote, iclass 28, count 2 2006.260.08:16:50.27#ibcon#about to read 3, iclass 28, count 2 2006.260.08:16:50.29#ibcon#read 3, iclass 28, count 2 2006.260.08:16:50.29#ibcon#about to read 4, iclass 28, count 2 2006.260.08:16:50.29#ibcon#read 4, iclass 28, count 2 2006.260.08:16:50.29#ibcon#about to read 5, iclass 28, count 2 2006.260.08:16:50.29#ibcon#read 5, iclass 28, count 2 2006.260.08:16:50.29#ibcon#about to read 6, iclass 28, count 2 2006.260.08:16:50.29#ibcon#read 6, iclass 28, count 2 2006.260.08:16:50.29#ibcon#end of sib2, iclass 28, count 2 2006.260.08:16:50.29#ibcon#*mode == 0, iclass 28, count 2 2006.260.08:16:50.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.08:16:50.29#ibcon#[25=AT05-07\r\n] 2006.260.08:16:50.29#ibcon#*before write, iclass 28, count 2 2006.260.08:16:50.29#ibcon#enter sib2, iclass 28, count 2 2006.260.08:16:50.29#ibcon#flushed, iclass 28, count 2 2006.260.08:16:50.29#ibcon#about to write, iclass 28, count 2 2006.260.08:16:50.29#ibcon#wrote, iclass 28, count 2 2006.260.08:16:50.29#ibcon#about to read 3, iclass 28, count 2 2006.260.08:16:50.32#ibcon#read 3, iclass 28, count 2 2006.260.08:16:50.32#ibcon#about to read 4, iclass 28, count 2 2006.260.08:16:50.32#ibcon#read 4, iclass 28, count 2 2006.260.08:16:50.32#ibcon#about to read 5, iclass 28, count 2 2006.260.08:16:50.32#ibcon#read 5, iclass 28, count 2 2006.260.08:16:50.32#ibcon#about to read 6, iclass 28, count 2 2006.260.08:16:50.32#ibcon#read 6, iclass 28, count 2 2006.260.08:16:50.32#ibcon#end of sib2, iclass 28, count 2 2006.260.08:16:50.32#ibcon#*after write, iclass 28, count 2 2006.260.08:16:50.32#ibcon#*before return 0, iclass 28, count 2 2006.260.08:16:50.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:50.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:50.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.08:16:50.32#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:50.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:50.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:50.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:50.44#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:16:50.44#ibcon#first serial, iclass 28, count 0 2006.260.08:16:50.44#ibcon#enter sib2, iclass 28, count 0 2006.260.08:16:50.44#ibcon#flushed, iclass 28, count 0 2006.260.08:16:50.44#ibcon#about to write, iclass 28, count 0 2006.260.08:16:50.44#ibcon#wrote, iclass 28, count 0 2006.260.08:16:50.44#ibcon#about to read 3, iclass 28, count 0 2006.260.08:16:50.46#ibcon#read 3, iclass 28, count 0 2006.260.08:16:50.46#ibcon#about to read 4, iclass 28, count 0 2006.260.08:16:50.46#ibcon#read 4, iclass 28, count 0 2006.260.08:16:50.46#ibcon#about to read 5, iclass 28, count 0 2006.260.08:16:50.46#ibcon#read 5, iclass 28, count 0 2006.260.08:16:50.46#ibcon#about to read 6, iclass 28, count 0 2006.260.08:16:50.46#ibcon#read 6, iclass 28, count 0 2006.260.08:16:50.46#ibcon#end of sib2, iclass 28, count 0 2006.260.08:16:50.46#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:16:50.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:16:50.46#ibcon#[25=USB\r\n] 2006.260.08:16:50.46#ibcon#*before write, iclass 28, count 0 2006.260.08:16:50.46#ibcon#enter sib2, iclass 28, count 0 2006.260.08:16:50.46#ibcon#flushed, iclass 28, count 0 2006.260.08:16:50.46#ibcon#about to write, iclass 28, count 0 2006.260.08:16:50.46#ibcon#wrote, iclass 28, count 0 2006.260.08:16:50.46#ibcon#about to read 3, iclass 28, count 0 2006.260.08:16:50.49#ibcon#read 3, iclass 28, count 0 2006.260.08:16:50.49#ibcon#about to read 4, iclass 28, count 0 2006.260.08:16:50.49#ibcon#read 4, iclass 28, count 0 2006.260.08:16:50.49#ibcon#about to read 5, iclass 28, count 0 2006.260.08:16:50.49#ibcon#read 5, iclass 28, count 0 2006.260.08:16:50.49#ibcon#about to read 6, iclass 28, count 0 2006.260.08:16:50.49#ibcon#read 6, iclass 28, count 0 2006.260.08:16:50.49#ibcon#end of sib2, iclass 28, count 0 2006.260.08:16:50.49#ibcon#*after write, iclass 28, count 0 2006.260.08:16:50.49#ibcon#*before return 0, iclass 28, count 0 2006.260.08:16:50.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:50.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:50.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:16:50.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:16:50.49$vc4f8/valo=6,772.99 2006.260.08:16:50.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.08:16:50.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.08:16:50.49#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:50.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:50.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:50.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:50.49#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:16:50.49#ibcon#first serial, iclass 30, count 0 2006.260.08:16:50.49#ibcon#enter sib2, iclass 30, count 0 2006.260.08:16:50.49#ibcon#flushed, iclass 30, count 0 2006.260.08:16:50.49#ibcon#about to write, iclass 30, count 0 2006.260.08:16:50.49#ibcon#wrote, iclass 30, count 0 2006.260.08:16:50.49#ibcon#about to read 3, iclass 30, count 0 2006.260.08:16:50.51#ibcon#read 3, iclass 30, count 0 2006.260.08:16:50.51#ibcon#about to read 4, iclass 30, count 0 2006.260.08:16:50.51#ibcon#read 4, iclass 30, count 0 2006.260.08:16:50.51#ibcon#about to read 5, iclass 30, count 0 2006.260.08:16:50.51#ibcon#read 5, iclass 30, count 0 2006.260.08:16:50.51#ibcon#about to read 6, iclass 30, count 0 2006.260.08:16:50.51#ibcon#read 6, iclass 30, count 0 2006.260.08:16:50.51#ibcon#end of sib2, iclass 30, count 0 2006.260.08:16:50.51#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:16:50.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:16:50.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:16:50.51#ibcon#*before write, iclass 30, count 0 2006.260.08:16:50.51#ibcon#enter sib2, iclass 30, count 0 2006.260.08:16:50.51#ibcon#flushed, iclass 30, count 0 2006.260.08:16:50.51#ibcon#about to write, iclass 30, count 0 2006.260.08:16:50.51#ibcon#wrote, iclass 30, count 0 2006.260.08:16:50.51#ibcon#about to read 3, iclass 30, count 0 2006.260.08:16:50.55#ibcon#read 3, iclass 30, count 0 2006.260.08:16:50.55#ibcon#about to read 4, iclass 30, count 0 2006.260.08:16:50.55#ibcon#read 4, iclass 30, count 0 2006.260.08:16:50.55#ibcon#about to read 5, iclass 30, count 0 2006.260.08:16:50.55#ibcon#read 5, iclass 30, count 0 2006.260.08:16:50.55#ibcon#about to read 6, iclass 30, count 0 2006.260.08:16:50.55#ibcon#read 6, iclass 30, count 0 2006.260.08:16:50.55#ibcon#end of sib2, iclass 30, count 0 2006.260.08:16:50.55#ibcon#*after write, iclass 30, count 0 2006.260.08:16:50.55#ibcon#*before return 0, iclass 30, count 0 2006.260.08:16:50.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:50.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:50.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:16:50.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:16:50.55$vc4f8/va=6,6 2006.260.08:16:50.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.08:16:50.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.08:16:50.55#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:50.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:50.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:50.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:50.61#ibcon#enter wrdev, iclass 32, count 2 2006.260.08:16:50.61#ibcon#first serial, iclass 32, count 2 2006.260.08:16:50.61#ibcon#enter sib2, iclass 32, count 2 2006.260.08:16:50.61#ibcon#flushed, iclass 32, count 2 2006.260.08:16:50.61#ibcon#about to write, iclass 32, count 2 2006.260.08:16:50.61#ibcon#wrote, iclass 32, count 2 2006.260.08:16:50.61#ibcon#about to read 3, iclass 32, count 2 2006.260.08:16:50.63#ibcon#read 3, iclass 32, count 2 2006.260.08:16:50.63#ibcon#about to read 4, iclass 32, count 2 2006.260.08:16:50.63#ibcon#read 4, iclass 32, count 2 2006.260.08:16:50.63#ibcon#about to read 5, iclass 32, count 2 2006.260.08:16:50.63#ibcon#read 5, iclass 32, count 2 2006.260.08:16:50.63#ibcon#about to read 6, iclass 32, count 2 2006.260.08:16:50.63#ibcon#read 6, iclass 32, count 2 2006.260.08:16:50.63#ibcon#end of sib2, iclass 32, count 2 2006.260.08:16:50.63#ibcon#*mode == 0, iclass 32, count 2 2006.260.08:16:50.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.08:16:50.63#ibcon#[25=AT06-06\r\n] 2006.260.08:16:50.63#ibcon#*before write, iclass 32, count 2 2006.260.08:16:50.63#ibcon#enter sib2, iclass 32, count 2 2006.260.08:16:50.63#ibcon#flushed, iclass 32, count 2 2006.260.08:16:50.63#ibcon#about to write, iclass 32, count 2 2006.260.08:16:50.63#ibcon#wrote, iclass 32, count 2 2006.260.08:16:50.63#ibcon#about to read 3, iclass 32, count 2 2006.260.08:16:50.66#ibcon#read 3, iclass 32, count 2 2006.260.08:16:50.66#ibcon#about to read 4, iclass 32, count 2 2006.260.08:16:50.66#ibcon#read 4, iclass 32, count 2 2006.260.08:16:50.66#ibcon#about to read 5, iclass 32, count 2 2006.260.08:16:50.66#ibcon#read 5, iclass 32, count 2 2006.260.08:16:50.66#ibcon#about to read 6, iclass 32, count 2 2006.260.08:16:50.66#ibcon#read 6, iclass 32, count 2 2006.260.08:16:50.66#ibcon#end of sib2, iclass 32, count 2 2006.260.08:16:50.66#ibcon#*after write, iclass 32, count 2 2006.260.08:16:50.66#ibcon#*before return 0, iclass 32, count 2 2006.260.08:16:50.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:50.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:50.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.08:16:50.66#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:50.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:50.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:50.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:50.78#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:16:50.78#ibcon#first serial, iclass 32, count 0 2006.260.08:16:50.78#ibcon#enter sib2, iclass 32, count 0 2006.260.08:16:50.78#ibcon#flushed, iclass 32, count 0 2006.260.08:16:50.78#ibcon#about to write, iclass 32, count 0 2006.260.08:16:50.78#ibcon#wrote, iclass 32, count 0 2006.260.08:16:50.78#ibcon#about to read 3, iclass 32, count 0 2006.260.08:16:50.80#ibcon#read 3, iclass 32, count 0 2006.260.08:16:50.80#ibcon#about to read 4, iclass 32, count 0 2006.260.08:16:50.80#ibcon#read 4, iclass 32, count 0 2006.260.08:16:50.80#ibcon#about to read 5, iclass 32, count 0 2006.260.08:16:50.80#ibcon#read 5, iclass 32, count 0 2006.260.08:16:50.80#ibcon#about to read 6, iclass 32, count 0 2006.260.08:16:50.80#ibcon#read 6, iclass 32, count 0 2006.260.08:16:50.80#ibcon#end of sib2, iclass 32, count 0 2006.260.08:16:50.80#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:16:50.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:16:50.80#ibcon#[25=USB\r\n] 2006.260.08:16:50.80#ibcon#*before write, iclass 32, count 0 2006.260.08:16:50.80#ibcon#enter sib2, iclass 32, count 0 2006.260.08:16:50.80#ibcon#flushed, iclass 32, count 0 2006.260.08:16:50.80#ibcon#about to write, iclass 32, count 0 2006.260.08:16:50.80#ibcon#wrote, iclass 32, count 0 2006.260.08:16:50.80#ibcon#about to read 3, iclass 32, count 0 2006.260.08:16:50.83#ibcon#read 3, iclass 32, count 0 2006.260.08:16:50.83#ibcon#about to read 4, iclass 32, count 0 2006.260.08:16:50.83#ibcon#read 4, iclass 32, count 0 2006.260.08:16:50.83#ibcon#about to read 5, iclass 32, count 0 2006.260.08:16:50.83#ibcon#read 5, iclass 32, count 0 2006.260.08:16:50.83#ibcon#about to read 6, iclass 32, count 0 2006.260.08:16:50.83#ibcon#read 6, iclass 32, count 0 2006.260.08:16:50.83#ibcon#end of sib2, iclass 32, count 0 2006.260.08:16:50.83#ibcon#*after write, iclass 32, count 0 2006.260.08:16:50.83#ibcon#*before return 0, iclass 32, count 0 2006.260.08:16:50.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:50.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:50.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:16:50.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:16:50.83$vc4f8/valo=7,832.99 2006.260.08:16:50.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.08:16:50.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.08:16:50.83#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:50.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:50.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:50.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:50.83#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:16:50.83#ibcon#first serial, iclass 34, count 0 2006.260.08:16:50.83#ibcon#enter sib2, iclass 34, count 0 2006.260.08:16:50.83#ibcon#flushed, iclass 34, count 0 2006.260.08:16:50.83#ibcon#about to write, iclass 34, count 0 2006.260.08:16:50.83#ibcon#wrote, iclass 34, count 0 2006.260.08:16:50.83#ibcon#about to read 3, iclass 34, count 0 2006.260.08:16:50.85#ibcon#read 3, iclass 34, count 0 2006.260.08:16:50.85#ibcon#about to read 4, iclass 34, count 0 2006.260.08:16:50.85#ibcon#read 4, iclass 34, count 0 2006.260.08:16:50.85#ibcon#about to read 5, iclass 34, count 0 2006.260.08:16:50.85#ibcon#read 5, iclass 34, count 0 2006.260.08:16:50.85#ibcon#about to read 6, iclass 34, count 0 2006.260.08:16:50.85#ibcon#read 6, iclass 34, count 0 2006.260.08:16:50.85#ibcon#end of sib2, iclass 34, count 0 2006.260.08:16:50.85#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:16:50.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:16:50.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:16:50.85#ibcon#*before write, iclass 34, count 0 2006.260.08:16:50.85#ibcon#enter sib2, iclass 34, count 0 2006.260.08:16:50.85#ibcon#flushed, iclass 34, count 0 2006.260.08:16:50.85#ibcon#about to write, iclass 34, count 0 2006.260.08:16:50.85#ibcon#wrote, iclass 34, count 0 2006.260.08:16:50.85#ibcon#about to read 3, iclass 34, count 0 2006.260.08:16:50.89#ibcon#read 3, iclass 34, count 0 2006.260.08:16:50.89#ibcon#about to read 4, iclass 34, count 0 2006.260.08:16:50.89#ibcon#read 4, iclass 34, count 0 2006.260.08:16:50.89#ibcon#about to read 5, iclass 34, count 0 2006.260.08:16:50.89#ibcon#read 5, iclass 34, count 0 2006.260.08:16:50.89#ibcon#about to read 6, iclass 34, count 0 2006.260.08:16:50.89#ibcon#read 6, iclass 34, count 0 2006.260.08:16:50.89#ibcon#end of sib2, iclass 34, count 0 2006.260.08:16:50.89#ibcon#*after write, iclass 34, count 0 2006.260.08:16:50.89#ibcon#*before return 0, iclass 34, count 0 2006.260.08:16:50.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:50.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:50.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:16:50.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:16:50.89$vc4f8/va=7,6 2006.260.08:16:50.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.08:16:50.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.08:16:50.89#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:50.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:50.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:50.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:50.95#ibcon#enter wrdev, iclass 36, count 2 2006.260.08:16:50.95#ibcon#first serial, iclass 36, count 2 2006.260.08:16:50.95#ibcon#enter sib2, iclass 36, count 2 2006.260.08:16:50.95#ibcon#flushed, iclass 36, count 2 2006.260.08:16:50.95#ibcon#about to write, iclass 36, count 2 2006.260.08:16:50.95#ibcon#wrote, iclass 36, count 2 2006.260.08:16:50.95#ibcon#about to read 3, iclass 36, count 2 2006.260.08:16:50.97#ibcon#read 3, iclass 36, count 2 2006.260.08:16:50.97#ibcon#about to read 4, iclass 36, count 2 2006.260.08:16:50.97#ibcon#read 4, iclass 36, count 2 2006.260.08:16:50.97#ibcon#about to read 5, iclass 36, count 2 2006.260.08:16:50.97#ibcon#read 5, iclass 36, count 2 2006.260.08:16:50.97#ibcon#about to read 6, iclass 36, count 2 2006.260.08:16:50.97#ibcon#read 6, iclass 36, count 2 2006.260.08:16:50.97#ibcon#end of sib2, iclass 36, count 2 2006.260.08:16:50.97#ibcon#*mode == 0, iclass 36, count 2 2006.260.08:16:50.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.08:16:50.97#ibcon#[25=AT07-06\r\n] 2006.260.08:16:50.97#ibcon#*before write, iclass 36, count 2 2006.260.08:16:50.97#ibcon#enter sib2, iclass 36, count 2 2006.260.08:16:50.97#ibcon#flushed, iclass 36, count 2 2006.260.08:16:50.97#ibcon#about to write, iclass 36, count 2 2006.260.08:16:50.97#ibcon#wrote, iclass 36, count 2 2006.260.08:16:50.97#ibcon#about to read 3, iclass 36, count 2 2006.260.08:16:51.00#ibcon#read 3, iclass 36, count 2 2006.260.08:16:51.00#ibcon#about to read 4, iclass 36, count 2 2006.260.08:16:51.00#ibcon#read 4, iclass 36, count 2 2006.260.08:16:51.00#ibcon#about to read 5, iclass 36, count 2 2006.260.08:16:51.00#ibcon#read 5, iclass 36, count 2 2006.260.08:16:51.00#ibcon#about to read 6, iclass 36, count 2 2006.260.08:16:51.00#ibcon#read 6, iclass 36, count 2 2006.260.08:16:51.00#ibcon#end of sib2, iclass 36, count 2 2006.260.08:16:51.00#ibcon#*after write, iclass 36, count 2 2006.260.08:16:51.00#ibcon#*before return 0, iclass 36, count 2 2006.260.08:16:51.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:51.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:51.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.08:16:51.00#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:51.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:16:51.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:16:51.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:16:51.12#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:16:51.12#ibcon#first serial, iclass 36, count 0 2006.260.08:16:51.12#ibcon#enter sib2, iclass 36, count 0 2006.260.08:16:51.12#ibcon#flushed, iclass 36, count 0 2006.260.08:16:51.12#ibcon#about to write, iclass 36, count 0 2006.260.08:16:51.12#ibcon#wrote, iclass 36, count 0 2006.260.08:16:51.12#ibcon#about to read 3, iclass 36, count 0 2006.260.08:16:51.14#ibcon#read 3, iclass 36, count 0 2006.260.08:16:51.14#ibcon#about to read 4, iclass 36, count 0 2006.260.08:16:51.14#ibcon#read 4, iclass 36, count 0 2006.260.08:16:51.14#ibcon#about to read 5, iclass 36, count 0 2006.260.08:16:51.14#ibcon#read 5, iclass 36, count 0 2006.260.08:16:51.14#ibcon#about to read 6, iclass 36, count 0 2006.260.08:16:51.14#ibcon#read 6, iclass 36, count 0 2006.260.08:16:51.14#ibcon#end of sib2, iclass 36, count 0 2006.260.08:16:51.14#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:16:51.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:16:51.14#ibcon#[25=USB\r\n] 2006.260.08:16:51.14#ibcon#*before write, iclass 36, count 0 2006.260.08:16:51.14#ibcon#enter sib2, iclass 36, count 0 2006.260.08:16:51.14#ibcon#flushed, iclass 36, count 0 2006.260.08:16:51.14#ibcon#about to write, iclass 36, count 0 2006.260.08:16:51.14#ibcon#wrote, iclass 36, count 0 2006.260.08:16:51.14#ibcon#about to read 3, iclass 36, count 0 2006.260.08:16:51.17#ibcon#read 3, iclass 36, count 0 2006.260.08:16:51.17#ibcon#about to read 4, iclass 36, count 0 2006.260.08:16:51.17#ibcon#read 4, iclass 36, count 0 2006.260.08:16:51.17#ibcon#about to read 5, iclass 36, count 0 2006.260.08:16:51.17#ibcon#read 5, iclass 36, count 0 2006.260.08:16:51.17#ibcon#about to read 6, iclass 36, count 0 2006.260.08:16:51.17#ibcon#read 6, iclass 36, count 0 2006.260.08:16:51.17#ibcon#end of sib2, iclass 36, count 0 2006.260.08:16:51.17#ibcon#*after write, iclass 36, count 0 2006.260.08:16:51.17#ibcon#*before return 0, iclass 36, count 0 2006.260.08:16:51.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:16:51.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:16:51.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:16:51.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:16:51.17$vc4f8/valo=8,852.99 2006.260.08:16:51.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.260.08:16:51.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.260.08:16:51.17#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:51.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:16:51.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:16:51.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:16:51.17#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:16:51.17#ibcon#first serial, iclass 38, count 0 2006.260.08:16:51.17#ibcon#enter sib2, iclass 38, count 0 2006.260.08:16:51.17#ibcon#flushed, iclass 38, count 0 2006.260.08:16:51.17#ibcon#about to write, iclass 38, count 0 2006.260.08:16:51.17#ibcon#wrote, iclass 38, count 0 2006.260.08:16:51.17#ibcon#about to read 3, iclass 38, count 0 2006.260.08:16:51.19#ibcon#read 3, iclass 38, count 0 2006.260.08:16:51.19#ibcon#about to read 4, iclass 38, count 0 2006.260.08:16:51.19#ibcon#read 4, iclass 38, count 0 2006.260.08:16:51.19#ibcon#about to read 5, iclass 38, count 0 2006.260.08:16:51.19#ibcon#read 5, iclass 38, count 0 2006.260.08:16:51.19#ibcon#about to read 6, iclass 38, count 0 2006.260.08:16:51.19#ibcon#read 6, iclass 38, count 0 2006.260.08:16:51.19#ibcon#end of sib2, iclass 38, count 0 2006.260.08:16:51.19#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:16:51.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:16:51.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:16:51.19#ibcon#*before write, iclass 38, count 0 2006.260.08:16:51.19#ibcon#enter sib2, iclass 38, count 0 2006.260.08:16:51.19#ibcon#flushed, iclass 38, count 0 2006.260.08:16:51.19#ibcon#about to write, iclass 38, count 0 2006.260.08:16:51.19#ibcon#wrote, iclass 38, count 0 2006.260.08:16:51.19#ibcon#about to read 3, iclass 38, count 0 2006.260.08:16:51.23#ibcon#read 3, iclass 38, count 0 2006.260.08:16:51.23#ibcon#about to read 4, iclass 38, count 0 2006.260.08:16:51.23#ibcon#read 4, iclass 38, count 0 2006.260.08:16:51.23#ibcon#about to read 5, iclass 38, count 0 2006.260.08:16:51.23#ibcon#read 5, iclass 38, count 0 2006.260.08:16:51.23#ibcon#about to read 6, iclass 38, count 0 2006.260.08:16:51.23#ibcon#read 6, iclass 38, count 0 2006.260.08:16:51.23#ibcon#end of sib2, iclass 38, count 0 2006.260.08:16:51.23#ibcon#*after write, iclass 38, count 0 2006.260.08:16:51.23#ibcon#*before return 0, iclass 38, count 0 2006.260.08:16:51.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:16:51.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.260.08:16:51.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:16:51.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:16:51.23$vc4f8/va=8,6 2006.260.08:16:51.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.260.08:16:51.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.260.08:16:51.23#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:51.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:16:51.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:16:51.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:16:51.29#ibcon#enter wrdev, iclass 40, count 2 2006.260.08:16:51.29#ibcon#first serial, iclass 40, count 2 2006.260.08:16:51.29#ibcon#enter sib2, iclass 40, count 2 2006.260.08:16:51.29#ibcon#flushed, iclass 40, count 2 2006.260.08:16:51.29#ibcon#about to write, iclass 40, count 2 2006.260.08:16:51.29#ibcon#wrote, iclass 40, count 2 2006.260.08:16:51.29#ibcon#about to read 3, iclass 40, count 2 2006.260.08:16:51.31#ibcon#read 3, iclass 40, count 2 2006.260.08:16:51.31#ibcon#about to read 4, iclass 40, count 2 2006.260.08:16:51.31#ibcon#read 4, iclass 40, count 2 2006.260.08:16:51.31#ibcon#about to read 5, iclass 40, count 2 2006.260.08:16:51.31#ibcon#read 5, iclass 40, count 2 2006.260.08:16:51.31#ibcon#about to read 6, iclass 40, count 2 2006.260.08:16:51.31#ibcon#read 6, iclass 40, count 2 2006.260.08:16:51.31#ibcon#end of sib2, iclass 40, count 2 2006.260.08:16:51.31#ibcon#*mode == 0, iclass 40, count 2 2006.260.08:16:51.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.260.08:16:51.31#ibcon#[25=AT08-06\r\n] 2006.260.08:16:51.31#ibcon#*before write, iclass 40, count 2 2006.260.08:16:51.31#ibcon#enter sib2, iclass 40, count 2 2006.260.08:16:51.31#ibcon#flushed, iclass 40, count 2 2006.260.08:16:51.31#ibcon#about to write, iclass 40, count 2 2006.260.08:16:51.31#ibcon#wrote, iclass 40, count 2 2006.260.08:16:51.31#ibcon#about to read 3, iclass 40, count 2 2006.260.08:16:51.34#ibcon#read 3, iclass 40, count 2 2006.260.08:16:51.34#ibcon#about to read 4, iclass 40, count 2 2006.260.08:16:51.34#ibcon#read 4, iclass 40, count 2 2006.260.08:16:51.34#ibcon#about to read 5, iclass 40, count 2 2006.260.08:16:51.34#ibcon#read 5, iclass 40, count 2 2006.260.08:16:51.34#ibcon#about to read 6, iclass 40, count 2 2006.260.08:16:51.34#ibcon#read 6, iclass 40, count 2 2006.260.08:16:51.34#ibcon#end of sib2, iclass 40, count 2 2006.260.08:16:51.34#ibcon#*after write, iclass 40, count 2 2006.260.08:16:51.34#ibcon#*before return 0, iclass 40, count 2 2006.260.08:16:51.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:16:51.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.260.08:16:51.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.260.08:16:51.34#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:51.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:16:51.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:16:51.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:16:51.46#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:16:51.46#ibcon#first serial, iclass 40, count 0 2006.260.08:16:51.46#ibcon#enter sib2, iclass 40, count 0 2006.260.08:16:51.46#ibcon#flushed, iclass 40, count 0 2006.260.08:16:51.46#ibcon#about to write, iclass 40, count 0 2006.260.08:16:51.46#ibcon#wrote, iclass 40, count 0 2006.260.08:16:51.46#ibcon#about to read 3, iclass 40, count 0 2006.260.08:16:51.48#ibcon#read 3, iclass 40, count 0 2006.260.08:16:51.48#ibcon#about to read 4, iclass 40, count 0 2006.260.08:16:51.48#ibcon#read 4, iclass 40, count 0 2006.260.08:16:51.48#ibcon#about to read 5, iclass 40, count 0 2006.260.08:16:51.48#ibcon#read 5, iclass 40, count 0 2006.260.08:16:51.48#ibcon#about to read 6, iclass 40, count 0 2006.260.08:16:51.48#ibcon#read 6, iclass 40, count 0 2006.260.08:16:51.48#ibcon#end of sib2, iclass 40, count 0 2006.260.08:16:51.48#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:16:51.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:16:51.48#ibcon#[25=USB\r\n] 2006.260.08:16:51.48#ibcon#*before write, iclass 40, count 0 2006.260.08:16:51.48#ibcon#enter sib2, iclass 40, count 0 2006.260.08:16:51.48#ibcon#flushed, iclass 40, count 0 2006.260.08:16:51.48#ibcon#about to write, iclass 40, count 0 2006.260.08:16:51.48#ibcon#wrote, iclass 40, count 0 2006.260.08:16:51.48#ibcon#about to read 3, iclass 40, count 0 2006.260.08:16:51.51#ibcon#read 3, iclass 40, count 0 2006.260.08:16:51.51#ibcon#about to read 4, iclass 40, count 0 2006.260.08:16:51.51#ibcon#read 4, iclass 40, count 0 2006.260.08:16:51.51#ibcon#about to read 5, iclass 40, count 0 2006.260.08:16:51.51#ibcon#read 5, iclass 40, count 0 2006.260.08:16:51.51#ibcon#about to read 6, iclass 40, count 0 2006.260.08:16:51.51#ibcon#read 6, iclass 40, count 0 2006.260.08:16:51.51#ibcon#end of sib2, iclass 40, count 0 2006.260.08:16:51.51#ibcon#*after write, iclass 40, count 0 2006.260.08:16:51.51#ibcon#*before return 0, iclass 40, count 0 2006.260.08:16:51.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:16:51.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.260.08:16:51.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:16:51.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:16:51.51$vc4f8/vblo=1,632.99 2006.260.08:16:51.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.260.08:16:51.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.260.08:16:51.51#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:51.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:16:51.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:16:51.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:16:51.51#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:16:51.51#ibcon#first serial, iclass 4, count 0 2006.260.08:16:51.51#ibcon#enter sib2, iclass 4, count 0 2006.260.08:16:51.51#ibcon#flushed, iclass 4, count 0 2006.260.08:16:51.51#ibcon#about to write, iclass 4, count 0 2006.260.08:16:51.51#ibcon#wrote, iclass 4, count 0 2006.260.08:16:51.51#ibcon#about to read 3, iclass 4, count 0 2006.260.08:16:51.53#ibcon#read 3, iclass 4, count 0 2006.260.08:16:51.53#ibcon#about to read 4, iclass 4, count 0 2006.260.08:16:51.53#ibcon#read 4, iclass 4, count 0 2006.260.08:16:51.53#ibcon#about to read 5, iclass 4, count 0 2006.260.08:16:51.53#ibcon#read 5, iclass 4, count 0 2006.260.08:16:51.53#ibcon#about to read 6, iclass 4, count 0 2006.260.08:16:51.53#ibcon#read 6, iclass 4, count 0 2006.260.08:16:51.53#ibcon#end of sib2, iclass 4, count 0 2006.260.08:16:51.53#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:16:51.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:16:51.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:16:51.53#ibcon#*before write, iclass 4, count 0 2006.260.08:16:51.53#ibcon#enter sib2, iclass 4, count 0 2006.260.08:16:51.53#ibcon#flushed, iclass 4, count 0 2006.260.08:16:51.53#ibcon#about to write, iclass 4, count 0 2006.260.08:16:51.53#ibcon#wrote, iclass 4, count 0 2006.260.08:16:51.53#ibcon#about to read 3, iclass 4, count 0 2006.260.08:16:51.57#ibcon#read 3, iclass 4, count 0 2006.260.08:16:51.57#ibcon#about to read 4, iclass 4, count 0 2006.260.08:16:51.57#ibcon#read 4, iclass 4, count 0 2006.260.08:16:51.57#ibcon#about to read 5, iclass 4, count 0 2006.260.08:16:51.57#ibcon#read 5, iclass 4, count 0 2006.260.08:16:51.57#ibcon#about to read 6, iclass 4, count 0 2006.260.08:16:51.57#ibcon#read 6, iclass 4, count 0 2006.260.08:16:51.57#ibcon#end of sib2, iclass 4, count 0 2006.260.08:16:51.57#ibcon#*after write, iclass 4, count 0 2006.260.08:16:51.57#ibcon#*before return 0, iclass 4, count 0 2006.260.08:16:51.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:16:51.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.260.08:16:51.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:16:51.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:16:51.57$vc4f8/vb=1,4 2006.260.08:16:51.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.260.08:16:51.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.260.08:16:51.57#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:51.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:16:51.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:16:51.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:16:51.57#ibcon#enter wrdev, iclass 6, count 2 2006.260.08:16:51.57#ibcon#first serial, iclass 6, count 2 2006.260.08:16:51.57#ibcon#enter sib2, iclass 6, count 2 2006.260.08:16:51.57#ibcon#flushed, iclass 6, count 2 2006.260.08:16:51.57#ibcon#about to write, iclass 6, count 2 2006.260.08:16:51.57#ibcon#wrote, iclass 6, count 2 2006.260.08:16:51.57#ibcon#about to read 3, iclass 6, count 2 2006.260.08:16:51.59#ibcon#read 3, iclass 6, count 2 2006.260.08:16:51.59#ibcon#about to read 4, iclass 6, count 2 2006.260.08:16:51.59#ibcon#read 4, iclass 6, count 2 2006.260.08:16:51.59#ibcon#about to read 5, iclass 6, count 2 2006.260.08:16:51.59#ibcon#read 5, iclass 6, count 2 2006.260.08:16:51.59#ibcon#about to read 6, iclass 6, count 2 2006.260.08:16:51.59#ibcon#read 6, iclass 6, count 2 2006.260.08:16:51.59#ibcon#end of sib2, iclass 6, count 2 2006.260.08:16:51.59#ibcon#*mode == 0, iclass 6, count 2 2006.260.08:16:51.59#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.260.08:16:51.59#ibcon#[27=AT01-04\r\n] 2006.260.08:16:51.59#ibcon#*before write, iclass 6, count 2 2006.260.08:16:51.59#ibcon#enter sib2, iclass 6, count 2 2006.260.08:16:51.59#ibcon#flushed, iclass 6, count 2 2006.260.08:16:51.59#ibcon#about to write, iclass 6, count 2 2006.260.08:16:51.59#ibcon#wrote, iclass 6, count 2 2006.260.08:16:51.59#ibcon#about to read 3, iclass 6, count 2 2006.260.08:16:51.62#ibcon#read 3, iclass 6, count 2 2006.260.08:16:51.62#ibcon#about to read 4, iclass 6, count 2 2006.260.08:16:51.62#ibcon#read 4, iclass 6, count 2 2006.260.08:16:51.62#ibcon#about to read 5, iclass 6, count 2 2006.260.08:16:51.62#ibcon#read 5, iclass 6, count 2 2006.260.08:16:51.62#ibcon#about to read 6, iclass 6, count 2 2006.260.08:16:51.62#ibcon#read 6, iclass 6, count 2 2006.260.08:16:51.62#ibcon#end of sib2, iclass 6, count 2 2006.260.08:16:51.62#ibcon#*after write, iclass 6, count 2 2006.260.08:16:51.62#ibcon#*before return 0, iclass 6, count 2 2006.260.08:16:51.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:16:51.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.260.08:16:51.62#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.260.08:16:51.62#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:51.62#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:16:51.65#abcon#<5=/04 3.0 6.5 22.74 891010.3\r\n> 2006.260.08:16:51.67#abcon#{5=INTERFACE CLEAR} 2006.260.08:16:51.73#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:16:51.74#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:16:51.74#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:16:51.74#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:16:51.74#ibcon#first serial, iclass 6, count 0 2006.260.08:16:51.74#ibcon#enter sib2, iclass 6, count 0 2006.260.08:16:51.74#ibcon#flushed, iclass 6, count 0 2006.260.08:16:51.74#ibcon#about to write, iclass 6, count 0 2006.260.08:16:51.74#ibcon#wrote, iclass 6, count 0 2006.260.08:16:51.74#ibcon#about to read 3, iclass 6, count 0 2006.260.08:16:51.76#ibcon#read 3, iclass 6, count 0 2006.260.08:16:51.76#ibcon#about to read 4, iclass 6, count 0 2006.260.08:16:51.76#ibcon#read 4, iclass 6, count 0 2006.260.08:16:51.76#ibcon#about to read 5, iclass 6, count 0 2006.260.08:16:51.76#ibcon#read 5, iclass 6, count 0 2006.260.08:16:51.76#ibcon#about to read 6, iclass 6, count 0 2006.260.08:16:51.76#ibcon#read 6, iclass 6, count 0 2006.260.08:16:51.76#ibcon#end of sib2, iclass 6, count 0 2006.260.08:16:51.76#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:16:51.76#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:16:51.76#ibcon#[27=USB\r\n] 2006.260.08:16:51.76#ibcon#*before write, iclass 6, count 0 2006.260.08:16:51.76#ibcon#enter sib2, iclass 6, count 0 2006.260.08:16:51.76#ibcon#flushed, iclass 6, count 0 2006.260.08:16:51.76#ibcon#about to write, iclass 6, count 0 2006.260.08:16:51.76#ibcon#wrote, iclass 6, count 0 2006.260.08:16:51.76#ibcon#about to read 3, iclass 6, count 0 2006.260.08:16:51.79#ibcon#read 3, iclass 6, count 0 2006.260.08:16:51.79#ibcon#about to read 4, iclass 6, count 0 2006.260.08:16:51.79#ibcon#read 4, iclass 6, count 0 2006.260.08:16:51.79#ibcon#about to read 5, iclass 6, count 0 2006.260.08:16:51.79#ibcon#read 5, iclass 6, count 0 2006.260.08:16:51.79#ibcon#about to read 6, iclass 6, count 0 2006.260.08:16:51.79#ibcon#read 6, iclass 6, count 0 2006.260.08:16:51.79#ibcon#end of sib2, iclass 6, count 0 2006.260.08:16:51.79#ibcon#*after write, iclass 6, count 0 2006.260.08:16:51.79#ibcon#*before return 0, iclass 6, count 0 2006.260.08:16:51.79#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:16:51.79#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.260.08:16:51.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:16:51.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:16:51.79$vc4f8/vblo=2,640.99 2006.260.08:16:51.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:16:51.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:16:51.79#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:51.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:51.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:51.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:51.79#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:16:51.79#ibcon#first serial, iclass 14, count 0 2006.260.08:16:51.79#ibcon#enter sib2, iclass 14, count 0 2006.260.08:16:51.79#ibcon#flushed, iclass 14, count 0 2006.260.08:16:51.79#ibcon#about to write, iclass 14, count 0 2006.260.08:16:51.79#ibcon#wrote, iclass 14, count 0 2006.260.08:16:51.79#ibcon#about to read 3, iclass 14, count 0 2006.260.08:16:51.81#ibcon#read 3, iclass 14, count 0 2006.260.08:16:51.81#ibcon#about to read 4, iclass 14, count 0 2006.260.08:16:51.81#ibcon#read 4, iclass 14, count 0 2006.260.08:16:51.81#ibcon#about to read 5, iclass 14, count 0 2006.260.08:16:51.81#ibcon#read 5, iclass 14, count 0 2006.260.08:16:51.81#ibcon#about to read 6, iclass 14, count 0 2006.260.08:16:51.81#ibcon#read 6, iclass 14, count 0 2006.260.08:16:51.81#ibcon#end of sib2, iclass 14, count 0 2006.260.08:16:51.81#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:16:51.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:16:51.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:16:51.81#ibcon#*before write, iclass 14, count 0 2006.260.08:16:51.81#ibcon#enter sib2, iclass 14, count 0 2006.260.08:16:51.81#ibcon#flushed, iclass 14, count 0 2006.260.08:16:51.81#ibcon#about to write, iclass 14, count 0 2006.260.08:16:51.81#ibcon#wrote, iclass 14, count 0 2006.260.08:16:51.81#ibcon#about to read 3, iclass 14, count 0 2006.260.08:16:51.85#ibcon#read 3, iclass 14, count 0 2006.260.08:16:51.85#ibcon#about to read 4, iclass 14, count 0 2006.260.08:16:51.85#ibcon#read 4, iclass 14, count 0 2006.260.08:16:51.85#ibcon#about to read 5, iclass 14, count 0 2006.260.08:16:51.85#ibcon#read 5, iclass 14, count 0 2006.260.08:16:51.85#ibcon#about to read 6, iclass 14, count 0 2006.260.08:16:51.85#ibcon#read 6, iclass 14, count 0 2006.260.08:16:51.85#ibcon#end of sib2, iclass 14, count 0 2006.260.08:16:51.85#ibcon#*after write, iclass 14, count 0 2006.260.08:16:51.85#ibcon#*before return 0, iclass 14, count 0 2006.260.08:16:51.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:51.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:16:51.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:16:51.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:16:51.85$vc4f8/vb=2,5 2006.260.08:16:51.85#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.260.08:16:51.85#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.260.08:16:51.85#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:51.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:51.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:51.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:51.91#ibcon#enter wrdev, iclass 16, count 2 2006.260.08:16:51.91#ibcon#first serial, iclass 16, count 2 2006.260.08:16:51.91#ibcon#enter sib2, iclass 16, count 2 2006.260.08:16:51.91#ibcon#flushed, iclass 16, count 2 2006.260.08:16:51.91#ibcon#about to write, iclass 16, count 2 2006.260.08:16:51.91#ibcon#wrote, iclass 16, count 2 2006.260.08:16:51.91#ibcon#about to read 3, iclass 16, count 2 2006.260.08:16:51.93#ibcon#read 3, iclass 16, count 2 2006.260.08:16:51.93#ibcon#about to read 4, iclass 16, count 2 2006.260.08:16:51.93#ibcon#read 4, iclass 16, count 2 2006.260.08:16:51.93#ibcon#about to read 5, iclass 16, count 2 2006.260.08:16:51.93#ibcon#read 5, iclass 16, count 2 2006.260.08:16:51.93#ibcon#about to read 6, iclass 16, count 2 2006.260.08:16:51.93#ibcon#read 6, iclass 16, count 2 2006.260.08:16:51.93#ibcon#end of sib2, iclass 16, count 2 2006.260.08:16:51.93#ibcon#*mode == 0, iclass 16, count 2 2006.260.08:16:51.93#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.260.08:16:51.93#ibcon#[27=AT02-05\r\n] 2006.260.08:16:51.93#ibcon#*before write, iclass 16, count 2 2006.260.08:16:51.93#ibcon#enter sib2, iclass 16, count 2 2006.260.08:16:51.93#ibcon#flushed, iclass 16, count 2 2006.260.08:16:51.93#ibcon#about to write, iclass 16, count 2 2006.260.08:16:51.93#ibcon#wrote, iclass 16, count 2 2006.260.08:16:51.93#ibcon#about to read 3, iclass 16, count 2 2006.260.08:16:51.96#ibcon#read 3, iclass 16, count 2 2006.260.08:16:51.96#ibcon#about to read 4, iclass 16, count 2 2006.260.08:16:51.96#ibcon#read 4, iclass 16, count 2 2006.260.08:16:51.96#ibcon#about to read 5, iclass 16, count 2 2006.260.08:16:51.96#ibcon#read 5, iclass 16, count 2 2006.260.08:16:51.96#ibcon#about to read 6, iclass 16, count 2 2006.260.08:16:51.96#ibcon#read 6, iclass 16, count 2 2006.260.08:16:51.96#ibcon#end of sib2, iclass 16, count 2 2006.260.08:16:51.96#ibcon#*after write, iclass 16, count 2 2006.260.08:16:51.96#ibcon#*before return 0, iclass 16, count 2 2006.260.08:16:51.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:51.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.260.08:16:51.96#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.260.08:16:51.96#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:51.96#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:52.08#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:52.08#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:52.08#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:16:52.08#ibcon#first serial, iclass 16, count 0 2006.260.08:16:52.08#ibcon#enter sib2, iclass 16, count 0 2006.260.08:16:52.08#ibcon#flushed, iclass 16, count 0 2006.260.08:16:52.08#ibcon#about to write, iclass 16, count 0 2006.260.08:16:52.08#ibcon#wrote, iclass 16, count 0 2006.260.08:16:52.08#ibcon#about to read 3, iclass 16, count 0 2006.260.08:16:52.10#ibcon#read 3, iclass 16, count 0 2006.260.08:16:52.10#ibcon#about to read 4, iclass 16, count 0 2006.260.08:16:52.10#ibcon#read 4, iclass 16, count 0 2006.260.08:16:52.10#ibcon#about to read 5, iclass 16, count 0 2006.260.08:16:52.10#ibcon#read 5, iclass 16, count 0 2006.260.08:16:52.10#ibcon#about to read 6, iclass 16, count 0 2006.260.08:16:52.10#ibcon#read 6, iclass 16, count 0 2006.260.08:16:52.10#ibcon#end of sib2, iclass 16, count 0 2006.260.08:16:52.10#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:16:52.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:16:52.10#ibcon#[27=USB\r\n] 2006.260.08:16:52.10#ibcon#*before write, iclass 16, count 0 2006.260.08:16:52.10#ibcon#enter sib2, iclass 16, count 0 2006.260.08:16:52.10#ibcon#flushed, iclass 16, count 0 2006.260.08:16:52.10#ibcon#about to write, iclass 16, count 0 2006.260.08:16:52.10#ibcon#wrote, iclass 16, count 0 2006.260.08:16:52.10#ibcon#about to read 3, iclass 16, count 0 2006.260.08:16:52.13#ibcon#read 3, iclass 16, count 0 2006.260.08:16:52.13#ibcon#about to read 4, iclass 16, count 0 2006.260.08:16:52.13#ibcon#read 4, iclass 16, count 0 2006.260.08:16:52.13#ibcon#about to read 5, iclass 16, count 0 2006.260.08:16:52.13#ibcon#read 5, iclass 16, count 0 2006.260.08:16:52.13#ibcon#about to read 6, iclass 16, count 0 2006.260.08:16:52.13#ibcon#read 6, iclass 16, count 0 2006.260.08:16:52.13#ibcon#end of sib2, iclass 16, count 0 2006.260.08:16:52.13#ibcon#*after write, iclass 16, count 0 2006.260.08:16:52.13#ibcon#*before return 0, iclass 16, count 0 2006.260.08:16:52.13#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:52.13#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.260.08:16:52.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:16:52.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:16:52.13$vc4f8/vblo=3,656.99 2006.260.08:16:52.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.260.08:16:52.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.260.08:16:52.13#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:52.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:52.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:52.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:52.13#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:16:52.13#ibcon#first serial, iclass 18, count 0 2006.260.08:16:52.13#ibcon#enter sib2, iclass 18, count 0 2006.260.08:16:52.13#ibcon#flushed, iclass 18, count 0 2006.260.08:16:52.13#ibcon#about to write, iclass 18, count 0 2006.260.08:16:52.13#ibcon#wrote, iclass 18, count 0 2006.260.08:16:52.13#ibcon#about to read 3, iclass 18, count 0 2006.260.08:16:52.15#ibcon#read 3, iclass 18, count 0 2006.260.08:16:52.15#ibcon#about to read 4, iclass 18, count 0 2006.260.08:16:52.15#ibcon#read 4, iclass 18, count 0 2006.260.08:16:52.15#ibcon#about to read 5, iclass 18, count 0 2006.260.08:16:52.15#ibcon#read 5, iclass 18, count 0 2006.260.08:16:52.15#ibcon#about to read 6, iclass 18, count 0 2006.260.08:16:52.15#ibcon#read 6, iclass 18, count 0 2006.260.08:16:52.15#ibcon#end of sib2, iclass 18, count 0 2006.260.08:16:52.15#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:16:52.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:16:52.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:16:52.15#ibcon#*before write, iclass 18, count 0 2006.260.08:16:52.15#ibcon#enter sib2, iclass 18, count 0 2006.260.08:16:52.15#ibcon#flushed, iclass 18, count 0 2006.260.08:16:52.15#ibcon#about to write, iclass 18, count 0 2006.260.08:16:52.15#ibcon#wrote, iclass 18, count 0 2006.260.08:16:52.15#ibcon#about to read 3, iclass 18, count 0 2006.260.08:16:52.19#ibcon#read 3, iclass 18, count 0 2006.260.08:16:52.19#ibcon#about to read 4, iclass 18, count 0 2006.260.08:16:52.19#ibcon#read 4, iclass 18, count 0 2006.260.08:16:52.19#ibcon#about to read 5, iclass 18, count 0 2006.260.08:16:52.19#ibcon#read 5, iclass 18, count 0 2006.260.08:16:52.19#ibcon#about to read 6, iclass 18, count 0 2006.260.08:16:52.19#ibcon#read 6, iclass 18, count 0 2006.260.08:16:52.19#ibcon#end of sib2, iclass 18, count 0 2006.260.08:16:52.19#ibcon#*after write, iclass 18, count 0 2006.260.08:16:52.19#ibcon#*before return 0, iclass 18, count 0 2006.260.08:16:52.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:52.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.260.08:16:52.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:16:52.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:16:52.19$vc4f8/vb=3,4 2006.260.08:16:52.19#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.260.08:16:52.19#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.260.08:16:52.19#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:52.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:52.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:52.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:52.25#ibcon#enter wrdev, iclass 20, count 2 2006.260.08:16:52.25#ibcon#first serial, iclass 20, count 2 2006.260.08:16:52.25#ibcon#enter sib2, iclass 20, count 2 2006.260.08:16:52.25#ibcon#flushed, iclass 20, count 2 2006.260.08:16:52.25#ibcon#about to write, iclass 20, count 2 2006.260.08:16:52.25#ibcon#wrote, iclass 20, count 2 2006.260.08:16:52.25#ibcon#about to read 3, iclass 20, count 2 2006.260.08:16:52.27#ibcon#read 3, iclass 20, count 2 2006.260.08:16:52.27#ibcon#about to read 4, iclass 20, count 2 2006.260.08:16:52.27#ibcon#read 4, iclass 20, count 2 2006.260.08:16:52.27#ibcon#about to read 5, iclass 20, count 2 2006.260.08:16:52.27#ibcon#read 5, iclass 20, count 2 2006.260.08:16:52.27#ibcon#about to read 6, iclass 20, count 2 2006.260.08:16:52.27#ibcon#read 6, iclass 20, count 2 2006.260.08:16:52.27#ibcon#end of sib2, iclass 20, count 2 2006.260.08:16:52.27#ibcon#*mode == 0, iclass 20, count 2 2006.260.08:16:52.27#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.260.08:16:52.27#ibcon#[27=AT03-04\r\n] 2006.260.08:16:52.27#ibcon#*before write, iclass 20, count 2 2006.260.08:16:52.27#ibcon#enter sib2, iclass 20, count 2 2006.260.08:16:52.27#ibcon#flushed, iclass 20, count 2 2006.260.08:16:52.27#ibcon#about to write, iclass 20, count 2 2006.260.08:16:52.27#ibcon#wrote, iclass 20, count 2 2006.260.08:16:52.27#ibcon#about to read 3, iclass 20, count 2 2006.260.08:16:52.30#ibcon#read 3, iclass 20, count 2 2006.260.08:16:52.30#ibcon#about to read 4, iclass 20, count 2 2006.260.08:16:52.30#ibcon#read 4, iclass 20, count 2 2006.260.08:16:52.30#ibcon#about to read 5, iclass 20, count 2 2006.260.08:16:52.30#ibcon#read 5, iclass 20, count 2 2006.260.08:16:52.30#ibcon#about to read 6, iclass 20, count 2 2006.260.08:16:52.30#ibcon#read 6, iclass 20, count 2 2006.260.08:16:52.30#ibcon#end of sib2, iclass 20, count 2 2006.260.08:16:52.30#ibcon#*after write, iclass 20, count 2 2006.260.08:16:52.30#ibcon#*before return 0, iclass 20, count 2 2006.260.08:16:52.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:52.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.260.08:16:52.30#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.260.08:16:52.30#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:52.30#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:52.42#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:52.42#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:52.42#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:16:52.42#ibcon#first serial, iclass 20, count 0 2006.260.08:16:52.42#ibcon#enter sib2, iclass 20, count 0 2006.260.08:16:52.42#ibcon#flushed, iclass 20, count 0 2006.260.08:16:52.42#ibcon#about to write, iclass 20, count 0 2006.260.08:16:52.42#ibcon#wrote, iclass 20, count 0 2006.260.08:16:52.42#ibcon#about to read 3, iclass 20, count 0 2006.260.08:16:52.44#ibcon#read 3, iclass 20, count 0 2006.260.08:16:52.44#ibcon#about to read 4, iclass 20, count 0 2006.260.08:16:52.44#ibcon#read 4, iclass 20, count 0 2006.260.08:16:52.44#ibcon#about to read 5, iclass 20, count 0 2006.260.08:16:52.44#ibcon#read 5, iclass 20, count 0 2006.260.08:16:52.44#ibcon#about to read 6, iclass 20, count 0 2006.260.08:16:52.44#ibcon#read 6, iclass 20, count 0 2006.260.08:16:52.44#ibcon#end of sib2, iclass 20, count 0 2006.260.08:16:52.44#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:16:52.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:16:52.44#ibcon#[27=USB\r\n] 2006.260.08:16:52.44#ibcon#*before write, iclass 20, count 0 2006.260.08:16:52.44#ibcon#enter sib2, iclass 20, count 0 2006.260.08:16:52.44#ibcon#flushed, iclass 20, count 0 2006.260.08:16:52.44#ibcon#about to write, iclass 20, count 0 2006.260.08:16:52.44#ibcon#wrote, iclass 20, count 0 2006.260.08:16:52.44#ibcon#about to read 3, iclass 20, count 0 2006.260.08:16:52.47#ibcon#read 3, iclass 20, count 0 2006.260.08:16:52.47#ibcon#about to read 4, iclass 20, count 0 2006.260.08:16:52.47#ibcon#read 4, iclass 20, count 0 2006.260.08:16:52.47#ibcon#about to read 5, iclass 20, count 0 2006.260.08:16:52.47#ibcon#read 5, iclass 20, count 0 2006.260.08:16:52.47#ibcon#about to read 6, iclass 20, count 0 2006.260.08:16:52.47#ibcon#read 6, iclass 20, count 0 2006.260.08:16:52.47#ibcon#end of sib2, iclass 20, count 0 2006.260.08:16:52.47#ibcon#*after write, iclass 20, count 0 2006.260.08:16:52.47#ibcon#*before return 0, iclass 20, count 0 2006.260.08:16:52.47#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:52.47#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.260.08:16:52.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:16:52.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:16:52.47$vc4f8/vblo=4,712.99 2006.260.08:16:52.47#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.260.08:16:52.47#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.260.08:16:52.47#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:52.47#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:52.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:52.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:52.47#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:16:52.47#ibcon#first serial, iclass 22, count 0 2006.260.08:16:52.47#ibcon#enter sib2, iclass 22, count 0 2006.260.08:16:52.47#ibcon#flushed, iclass 22, count 0 2006.260.08:16:52.47#ibcon#about to write, iclass 22, count 0 2006.260.08:16:52.47#ibcon#wrote, iclass 22, count 0 2006.260.08:16:52.47#ibcon#about to read 3, iclass 22, count 0 2006.260.08:16:52.49#ibcon#read 3, iclass 22, count 0 2006.260.08:16:52.49#ibcon#about to read 4, iclass 22, count 0 2006.260.08:16:52.49#ibcon#read 4, iclass 22, count 0 2006.260.08:16:52.49#ibcon#about to read 5, iclass 22, count 0 2006.260.08:16:52.49#ibcon#read 5, iclass 22, count 0 2006.260.08:16:52.49#ibcon#about to read 6, iclass 22, count 0 2006.260.08:16:52.49#ibcon#read 6, iclass 22, count 0 2006.260.08:16:52.49#ibcon#end of sib2, iclass 22, count 0 2006.260.08:16:52.49#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:16:52.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:16:52.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:16:52.49#ibcon#*before write, iclass 22, count 0 2006.260.08:16:52.49#ibcon#enter sib2, iclass 22, count 0 2006.260.08:16:52.49#ibcon#flushed, iclass 22, count 0 2006.260.08:16:52.49#ibcon#about to write, iclass 22, count 0 2006.260.08:16:52.49#ibcon#wrote, iclass 22, count 0 2006.260.08:16:52.49#ibcon#about to read 3, iclass 22, count 0 2006.260.08:16:52.53#ibcon#read 3, iclass 22, count 0 2006.260.08:16:52.53#ibcon#about to read 4, iclass 22, count 0 2006.260.08:16:52.53#ibcon#read 4, iclass 22, count 0 2006.260.08:16:52.53#ibcon#about to read 5, iclass 22, count 0 2006.260.08:16:52.53#ibcon#read 5, iclass 22, count 0 2006.260.08:16:52.53#ibcon#about to read 6, iclass 22, count 0 2006.260.08:16:52.53#ibcon#read 6, iclass 22, count 0 2006.260.08:16:52.53#ibcon#end of sib2, iclass 22, count 0 2006.260.08:16:52.53#ibcon#*after write, iclass 22, count 0 2006.260.08:16:52.53#ibcon#*before return 0, iclass 22, count 0 2006.260.08:16:52.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:52.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.260.08:16:52.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:16:52.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:16:52.53$vc4f8/vb=4,5 2006.260.08:16:52.53#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.260.08:16:52.53#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.260.08:16:52.53#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:52.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:52.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:52.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:52.59#ibcon#enter wrdev, iclass 24, count 2 2006.260.08:16:52.59#ibcon#first serial, iclass 24, count 2 2006.260.08:16:52.59#ibcon#enter sib2, iclass 24, count 2 2006.260.08:16:52.59#ibcon#flushed, iclass 24, count 2 2006.260.08:16:52.59#ibcon#about to write, iclass 24, count 2 2006.260.08:16:52.59#ibcon#wrote, iclass 24, count 2 2006.260.08:16:52.59#ibcon#about to read 3, iclass 24, count 2 2006.260.08:16:52.61#ibcon#read 3, iclass 24, count 2 2006.260.08:16:52.61#ibcon#about to read 4, iclass 24, count 2 2006.260.08:16:52.61#ibcon#read 4, iclass 24, count 2 2006.260.08:16:52.61#ibcon#about to read 5, iclass 24, count 2 2006.260.08:16:52.61#ibcon#read 5, iclass 24, count 2 2006.260.08:16:52.61#ibcon#about to read 6, iclass 24, count 2 2006.260.08:16:52.61#ibcon#read 6, iclass 24, count 2 2006.260.08:16:52.61#ibcon#end of sib2, iclass 24, count 2 2006.260.08:16:52.61#ibcon#*mode == 0, iclass 24, count 2 2006.260.08:16:52.61#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.260.08:16:52.61#ibcon#[27=AT04-05\r\n] 2006.260.08:16:52.61#ibcon#*before write, iclass 24, count 2 2006.260.08:16:52.61#ibcon#enter sib2, iclass 24, count 2 2006.260.08:16:52.61#ibcon#flushed, iclass 24, count 2 2006.260.08:16:52.61#ibcon#about to write, iclass 24, count 2 2006.260.08:16:52.61#ibcon#wrote, iclass 24, count 2 2006.260.08:16:52.61#ibcon#about to read 3, iclass 24, count 2 2006.260.08:16:52.64#ibcon#read 3, iclass 24, count 2 2006.260.08:16:52.64#ibcon#about to read 4, iclass 24, count 2 2006.260.08:16:52.64#ibcon#read 4, iclass 24, count 2 2006.260.08:16:52.64#ibcon#about to read 5, iclass 24, count 2 2006.260.08:16:52.64#ibcon#read 5, iclass 24, count 2 2006.260.08:16:52.64#ibcon#about to read 6, iclass 24, count 2 2006.260.08:16:52.64#ibcon#read 6, iclass 24, count 2 2006.260.08:16:52.64#ibcon#end of sib2, iclass 24, count 2 2006.260.08:16:52.64#ibcon#*after write, iclass 24, count 2 2006.260.08:16:52.64#ibcon#*before return 0, iclass 24, count 2 2006.260.08:16:52.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:52.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.260.08:16:52.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.260.08:16:52.64#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:52.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:52.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:52.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:52.76#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:16:52.76#ibcon#first serial, iclass 24, count 0 2006.260.08:16:52.76#ibcon#enter sib2, iclass 24, count 0 2006.260.08:16:52.76#ibcon#flushed, iclass 24, count 0 2006.260.08:16:52.76#ibcon#about to write, iclass 24, count 0 2006.260.08:16:52.76#ibcon#wrote, iclass 24, count 0 2006.260.08:16:52.76#ibcon#about to read 3, iclass 24, count 0 2006.260.08:16:52.78#ibcon#read 3, iclass 24, count 0 2006.260.08:16:52.78#ibcon#about to read 4, iclass 24, count 0 2006.260.08:16:52.78#ibcon#read 4, iclass 24, count 0 2006.260.08:16:52.78#ibcon#about to read 5, iclass 24, count 0 2006.260.08:16:52.78#ibcon#read 5, iclass 24, count 0 2006.260.08:16:52.78#ibcon#about to read 6, iclass 24, count 0 2006.260.08:16:52.78#ibcon#read 6, iclass 24, count 0 2006.260.08:16:52.78#ibcon#end of sib2, iclass 24, count 0 2006.260.08:16:52.78#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:16:52.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:16:52.78#ibcon#[27=USB\r\n] 2006.260.08:16:52.78#ibcon#*before write, iclass 24, count 0 2006.260.08:16:52.78#ibcon#enter sib2, iclass 24, count 0 2006.260.08:16:52.78#ibcon#flushed, iclass 24, count 0 2006.260.08:16:52.78#ibcon#about to write, iclass 24, count 0 2006.260.08:16:52.78#ibcon#wrote, iclass 24, count 0 2006.260.08:16:52.78#ibcon#about to read 3, iclass 24, count 0 2006.260.08:16:52.81#ibcon#read 3, iclass 24, count 0 2006.260.08:16:52.81#ibcon#about to read 4, iclass 24, count 0 2006.260.08:16:52.81#ibcon#read 4, iclass 24, count 0 2006.260.08:16:52.81#ibcon#about to read 5, iclass 24, count 0 2006.260.08:16:52.81#ibcon#read 5, iclass 24, count 0 2006.260.08:16:52.81#ibcon#about to read 6, iclass 24, count 0 2006.260.08:16:52.81#ibcon#read 6, iclass 24, count 0 2006.260.08:16:52.81#ibcon#end of sib2, iclass 24, count 0 2006.260.08:16:52.81#ibcon#*after write, iclass 24, count 0 2006.260.08:16:52.81#ibcon#*before return 0, iclass 24, count 0 2006.260.08:16:52.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:52.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.260.08:16:52.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:16:52.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:16:52.81$vc4f8/vblo=5,744.99 2006.260.08:16:52.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.260.08:16:52.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.260.08:16:52.81#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:52.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:52.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:52.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:52.81#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:16:52.81#ibcon#first serial, iclass 26, count 0 2006.260.08:16:52.81#ibcon#enter sib2, iclass 26, count 0 2006.260.08:16:52.81#ibcon#flushed, iclass 26, count 0 2006.260.08:16:52.81#ibcon#about to write, iclass 26, count 0 2006.260.08:16:52.81#ibcon#wrote, iclass 26, count 0 2006.260.08:16:52.81#ibcon#about to read 3, iclass 26, count 0 2006.260.08:16:52.83#ibcon#read 3, iclass 26, count 0 2006.260.08:16:52.83#ibcon#about to read 4, iclass 26, count 0 2006.260.08:16:52.83#ibcon#read 4, iclass 26, count 0 2006.260.08:16:52.83#ibcon#about to read 5, iclass 26, count 0 2006.260.08:16:52.83#ibcon#read 5, iclass 26, count 0 2006.260.08:16:52.83#ibcon#about to read 6, iclass 26, count 0 2006.260.08:16:52.83#ibcon#read 6, iclass 26, count 0 2006.260.08:16:52.83#ibcon#end of sib2, iclass 26, count 0 2006.260.08:16:52.83#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:16:52.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:16:52.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:16:52.83#ibcon#*before write, iclass 26, count 0 2006.260.08:16:52.83#ibcon#enter sib2, iclass 26, count 0 2006.260.08:16:52.83#ibcon#flushed, iclass 26, count 0 2006.260.08:16:52.83#ibcon#about to write, iclass 26, count 0 2006.260.08:16:52.83#ibcon#wrote, iclass 26, count 0 2006.260.08:16:52.83#ibcon#about to read 3, iclass 26, count 0 2006.260.08:16:52.87#ibcon#read 3, iclass 26, count 0 2006.260.08:16:52.87#ibcon#about to read 4, iclass 26, count 0 2006.260.08:16:52.87#ibcon#read 4, iclass 26, count 0 2006.260.08:16:52.87#ibcon#about to read 5, iclass 26, count 0 2006.260.08:16:52.87#ibcon#read 5, iclass 26, count 0 2006.260.08:16:52.87#ibcon#about to read 6, iclass 26, count 0 2006.260.08:16:52.87#ibcon#read 6, iclass 26, count 0 2006.260.08:16:52.87#ibcon#end of sib2, iclass 26, count 0 2006.260.08:16:52.87#ibcon#*after write, iclass 26, count 0 2006.260.08:16:52.87#ibcon#*before return 0, iclass 26, count 0 2006.260.08:16:52.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:52.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.260.08:16:52.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:16:52.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:16:52.87$vc4f8/vb=5,4 2006.260.08:16:52.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.260.08:16:52.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.260.08:16:52.87#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:52.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:52.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:52.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:52.93#ibcon#enter wrdev, iclass 28, count 2 2006.260.08:16:52.93#ibcon#first serial, iclass 28, count 2 2006.260.08:16:52.93#ibcon#enter sib2, iclass 28, count 2 2006.260.08:16:52.93#ibcon#flushed, iclass 28, count 2 2006.260.08:16:52.93#ibcon#about to write, iclass 28, count 2 2006.260.08:16:52.93#ibcon#wrote, iclass 28, count 2 2006.260.08:16:52.93#ibcon#about to read 3, iclass 28, count 2 2006.260.08:16:52.95#ibcon#read 3, iclass 28, count 2 2006.260.08:16:52.95#ibcon#about to read 4, iclass 28, count 2 2006.260.08:16:52.95#ibcon#read 4, iclass 28, count 2 2006.260.08:16:52.95#ibcon#about to read 5, iclass 28, count 2 2006.260.08:16:52.95#ibcon#read 5, iclass 28, count 2 2006.260.08:16:52.95#ibcon#about to read 6, iclass 28, count 2 2006.260.08:16:52.95#ibcon#read 6, iclass 28, count 2 2006.260.08:16:52.95#ibcon#end of sib2, iclass 28, count 2 2006.260.08:16:52.95#ibcon#*mode == 0, iclass 28, count 2 2006.260.08:16:52.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.260.08:16:52.95#ibcon#[27=AT05-04\r\n] 2006.260.08:16:52.95#ibcon#*before write, iclass 28, count 2 2006.260.08:16:52.95#ibcon#enter sib2, iclass 28, count 2 2006.260.08:16:52.95#ibcon#flushed, iclass 28, count 2 2006.260.08:16:52.95#ibcon#about to write, iclass 28, count 2 2006.260.08:16:52.95#ibcon#wrote, iclass 28, count 2 2006.260.08:16:52.95#ibcon#about to read 3, iclass 28, count 2 2006.260.08:16:52.98#ibcon#read 3, iclass 28, count 2 2006.260.08:16:52.98#ibcon#about to read 4, iclass 28, count 2 2006.260.08:16:52.98#ibcon#read 4, iclass 28, count 2 2006.260.08:16:52.98#ibcon#about to read 5, iclass 28, count 2 2006.260.08:16:52.98#ibcon#read 5, iclass 28, count 2 2006.260.08:16:52.98#ibcon#about to read 6, iclass 28, count 2 2006.260.08:16:52.98#ibcon#read 6, iclass 28, count 2 2006.260.08:16:52.98#ibcon#end of sib2, iclass 28, count 2 2006.260.08:16:52.98#ibcon#*after write, iclass 28, count 2 2006.260.08:16:52.98#ibcon#*before return 0, iclass 28, count 2 2006.260.08:16:52.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:52.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.260.08:16:52.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.260.08:16:52.98#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:52.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:53.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:53.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:53.10#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:16:53.10#ibcon#first serial, iclass 28, count 0 2006.260.08:16:53.10#ibcon#enter sib2, iclass 28, count 0 2006.260.08:16:53.10#ibcon#flushed, iclass 28, count 0 2006.260.08:16:53.10#ibcon#about to write, iclass 28, count 0 2006.260.08:16:53.10#ibcon#wrote, iclass 28, count 0 2006.260.08:16:53.10#ibcon#about to read 3, iclass 28, count 0 2006.260.08:16:53.12#ibcon#read 3, iclass 28, count 0 2006.260.08:16:53.12#ibcon#about to read 4, iclass 28, count 0 2006.260.08:16:53.12#ibcon#read 4, iclass 28, count 0 2006.260.08:16:53.12#ibcon#about to read 5, iclass 28, count 0 2006.260.08:16:53.12#ibcon#read 5, iclass 28, count 0 2006.260.08:16:53.12#ibcon#about to read 6, iclass 28, count 0 2006.260.08:16:53.12#ibcon#read 6, iclass 28, count 0 2006.260.08:16:53.12#ibcon#end of sib2, iclass 28, count 0 2006.260.08:16:53.12#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:16:53.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:16:53.12#ibcon#[27=USB\r\n] 2006.260.08:16:53.12#ibcon#*before write, iclass 28, count 0 2006.260.08:16:53.12#ibcon#enter sib2, iclass 28, count 0 2006.260.08:16:53.12#ibcon#flushed, iclass 28, count 0 2006.260.08:16:53.12#ibcon#about to write, iclass 28, count 0 2006.260.08:16:53.12#ibcon#wrote, iclass 28, count 0 2006.260.08:16:53.12#ibcon#about to read 3, iclass 28, count 0 2006.260.08:16:53.15#ibcon#read 3, iclass 28, count 0 2006.260.08:16:53.15#ibcon#about to read 4, iclass 28, count 0 2006.260.08:16:53.15#ibcon#read 4, iclass 28, count 0 2006.260.08:16:53.15#ibcon#about to read 5, iclass 28, count 0 2006.260.08:16:53.15#ibcon#read 5, iclass 28, count 0 2006.260.08:16:53.15#ibcon#about to read 6, iclass 28, count 0 2006.260.08:16:53.15#ibcon#read 6, iclass 28, count 0 2006.260.08:16:53.15#ibcon#end of sib2, iclass 28, count 0 2006.260.08:16:53.15#ibcon#*after write, iclass 28, count 0 2006.260.08:16:53.15#ibcon#*before return 0, iclass 28, count 0 2006.260.08:16:53.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:53.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.260.08:16:53.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:16:53.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:16:53.15$vc4f8/vblo=6,752.99 2006.260.08:16:53.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.260.08:16:53.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.260.08:16:53.15#ibcon#ireg 17 cls_cnt 0 2006.260.08:16:53.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:53.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:53.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:53.15#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:16:53.15#ibcon#first serial, iclass 30, count 0 2006.260.08:16:53.15#ibcon#enter sib2, iclass 30, count 0 2006.260.08:16:53.15#ibcon#flushed, iclass 30, count 0 2006.260.08:16:53.15#ibcon#about to write, iclass 30, count 0 2006.260.08:16:53.15#ibcon#wrote, iclass 30, count 0 2006.260.08:16:53.15#ibcon#about to read 3, iclass 30, count 0 2006.260.08:16:53.17#ibcon#read 3, iclass 30, count 0 2006.260.08:16:53.17#ibcon#about to read 4, iclass 30, count 0 2006.260.08:16:53.17#ibcon#read 4, iclass 30, count 0 2006.260.08:16:53.17#ibcon#about to read 5, iclass 30, count 0 2006.260.08:16:53.17#ibcon#read 5, iclass 30, count 0 2006.260.08:16:53.17#ibcon#about to read 6, iclass 30, count 0 2006.260.08:16:53.17#ibcon#read 6, iclass 30, count 0 2006.260.08:16:53.17#ibcon#end of sib2, iclass 30, count 0 2006.260.08:16:53.17#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:16:53.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:16:53.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:16:53.17#ibcon#*before write, iclass 30, count 0 2006.260.08:16:53.17#ibcon#enter sib2, iclass 30, count 0 2006.260.08:16:53.17#ibcon#flushed, iclass 30, count 0 2006.260.08:16:53.17#ibcon#about to write, iclass 30, count 0 2006.260.08:16:53.17#ibcon#wrote, iclass 30, count 0 2006.260.08:16:53.17#ibcon#about to read 3, iclass 30, count 0 2006.260.08:16:53.21#ibcon#read 3, iclass 30, count 0 2006.260.08:16:53.21#ibcon#about to read 4, iclass 30, count 0 2006.260.08:16:53.21#ibcon#read 4, iclass 30, count 0 2006.260.08:16:53.21#ibcon#about to read 5, iclass 30, count 0 2006.260.08:16:53.21#ibcon#read 5, iclass 30, count 0 2006.260.08:16:53.21#ibcon#about to read 6, iclass 30, count 0 2006.260.08:16:53.21#ibcon#read 6, iclass 30, count 0 2006.260.08:16:53.21#ibcon#end of sib2, iclass 30, count 0 2006.260.08:16:53.21#ibcon#*after write, iclass 30, count 0 2006.260.08:16:53.21#ibcon#*before return 0, iclass 30, count 0 2006.260.08:16:53.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:53.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.260.08:16:53.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:16:53.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:16:53.21$vc4f8/vb=6,4 2006.260.08:16:53.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.260.08:16:53.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.260.08:16:53.21#ibcon#ireg 11 cls_cnt 2 2006.260.08:16:53.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:53.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:53.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:53.27#ibcon#enter wrdev, iclass 32, count 2 2006.260.08:16:53.27#ibcon#first serial, iclass 32, count 2 2006.260.08:16:53.27#ibcon#enter sib2, iclass 32, count 2 2006.260.08:16:53.27#ibcon#flushed, iclass 32, count 2 2006.260.08:16:53.27#ibcon#about to write, iclass 32, count 2 2006.260.08:16:53.27#ibcon#wrote, iclass 32, count 2 2006.260.08:16:53.27#ibcon#about to read 3, iclass 32, count 2 2006.260.08:16:53.29#ibcon#read 3, iclass 32, count 2 2006.260.08:16:53.29#ibcon#about to read 4, iclass 32, count 2 2006.260.08:16:53.29#ibcon#read 4, iclass 32, count 2 2006.260.08:16:53.29#ibcon#about to read 5, iclass 32, count 2 2006.260.08:16:53.29#ibcon#read 5, iclass 32, count 2 2006.260.08:16:53.29#ibcon#about to read 6, iclass 32, count 2 2006.260.08:16:53.29#ibcon#read 6, iclass 32, count 2 2006.260.08:16:53.29#ibcon#end of sib2, iclass 32, count 2 2006.260.08:16:53.29#ibcon#*mode == 0, iclass 32, count 2 2006.260.08:16:53.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.260.08:16:53.29#ibcon#[27=AT06-04\r\n] 2006.260.08:16:53.29#ibcon#*before write, iclass 32, count 2 2006.260.08:16:53.29#ibcon#enter sib2, iclass 32, count 2 2006.260.08:16:53.29#ibcon#flushed, iclass 32, count 2 2006.260.08:16:53.29#ibcon#about to write, iclass 32, count 2 2006.260.08:16:53.29#ibcon#wrote, iclass 32, count 2 2006.260.08:16:53.29#ibcon#about to read 3, iclass 32, count 2 2006.260.08:16:53.32#ibcon#read 3, iclass 32, count 2 2006.260.08:16:53.32#ibcon#about to read 4, iclass 32, count 2 2006.260.08:16:53.32#ibcon#read 4, iclass 32, count 2 2006.260.08:16:53.32#ibcon#about to read 5, iclass 32, count 2 2006.260.08:16:53.32#ibcon#read 5, iclass 32, count 2 2006.260.08:16:53.32#ibcon#about to read 6, iclass 32, count 2 2006.260.08:16:53.32#ibcon#read 6, iclass 32, count 2 2006.260.08:16:53.32#ibcon#end of sib2, iclass 32, count 2 2006.260.08:16:53.32#ibcon#*after write, iclass 32, count 2 2006.260.08:16:53.32#ibcon#*before return 0, iclass 32, count 2 2006.260.08:16:53.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:53.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.260.08:16:53.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.260.08:16:53.32#ibcon#ireg 7 cls_cnt 0 2006.260.08:16:53.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:53.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:53.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:53.44#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:16:53.44#ibcon#first serial, iclass 32, count 0 2006.260.08:16:53.44#ibcon#enter sib2, iclass 32, count 0 2006.260.08:16:53.44#ibcon#flushed, iclass 32, count 0 2006.260.08:16:53.44#ibcon#about to write, iclass 32, count 0 2006.260.08:16:53.44#ibcon#wrote, iclass 32, count 0 2006.260.08:16:53.44#ibcon#about to read 3, iclass 32, count 0 2006.260.08:16:53.46#ibcon#read 3, iclass 32, count 0 2006.260.08:16:53.46#ibcon#about to read 4, iclass 32, count 0 2006.260.08:16:53.46#ibcon#read 4, iclass 32, count 0 2006.260.08:16:53.46#ibcon#about to read 5, iclass 32, count 0 2006.260.08:16:53.46#ibcon#read 5, iclass 32, count 0 2006.260.08:16:53.46#ibcon#about to read 6, iclass 32, count 0 2006.260.08:16:53.46#ibcon#read 6, iclass 32, count 0 2006.260.08:16:53.46#ibcon#end of sib2, iclass 32, count 0 2006.260.08:16:53.46#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:16:53.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:16:53.46#ibcon#[27=USB\r\n] 2006.260.08:16:53.46#ibcon#*before write, iclass 32, count 0 2006.260.08:16:53.46#ibcon#enter sib2, iclass 32, count 0 2006.260.08:16:53.46#ibcon#flushed, iclass 32, count 0 2006.260.08:16:53.46#ibcon#about to write, iclass 32, count 0 2006.260.08:16:53.46#ibcon#wrote, iclass 32, count 0 2006.260.08:16:53.46#ibcon#about to read 3, iclass 32, count 0 2006.260.08:16:53.49#ibcon#read 3, iclass 32, count 0 2006.260.08:16:53.49#ibcon#about to read 4, iclass 32, count 0 2006.260.08:16:53.49#ibcon#read 4, iclass 32, count 0 2006.260.08:16:53.49#ibcon#about to read 5, iclass 32, count 0 2006.260.08:16:53.49#ibcon#read 5, iclass 32, count 0 2006.260.08:16:53.49#ibcon#about to read 6, iclass 32, count 0 2006.260.08:16:53.49#ibcon#read 6, iclass 32, count 0 2006.260.08:16:53.49#ibcon#end of sib2, iclass 32, count 0 2006.260.08:16:53.49#ibcon#*after write, iclass 32, count 0 2006.260.08:16:53.49#ibcon#*before return 0, iclass 32, count 0 2006.260.08:16:53.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:53.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.260.08:16:53.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:16:53.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:16:53.49$vc4f8/vabw=wide 2006.260.08:16:53.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.260.08:16:53.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.260.08:16:53.49#ibcon#ireg 8 cls_cnt 0 2006.260.08:16:53.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:53.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:53.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:53.49#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:16:53.49#ibcon#first serial, iclass 34, count 0 2006.260.08:16:53.49#ibcon#enter sib2, iclass 34, count 0 2006.260.08:16:53.49#ibcon#flushed, iclass 34, count 0 2006.260.08:16:53.49#ibcon#about to write, iclass 34, count 0 2006.260.08:16:53.49#ibcon#wrote, iclass 34, count 0 2006.260.08:16:53.49#ibcon#about to read 3, iclass 34, count 0 2006.260.08:16:53.51#ibcon#read 3, iclass 34, count 0 2006.260.08:16:53.51#ibcon#about to read 4, iclass 34, count 0 2006.260.08:16:53.51#ibcon#read 4, iclass 34, count 0 2006.260.08:16:53.51#ibcon#about to read 5, iclass 34, count 0 2006.260.08:16:53.51#ibcon#read 5, iclass 34, count 0 2006.260.08:16:53.51#ibcon#about to read 6, iclass 34, count 0 2006.260.08:16:53.51#ibcon#read 6, iclass 34, count 0 2006.260.08:16:53.51#ibcon#end of sib2, iclass 34, count 0 2006.260.08:16:53.51#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:16:53.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:16:53.51#ibcon#[25=BW32\r\n] 2006.260.08:16:53.51#ibcon#*before write, iclass 34, count 0 2006.260.08:16:53.51#ibcon#enter sib2, iclass 34, count 0 2006.260.08:16:53.51#ibcon#flushed, iclass 34, count 0 2006.260.08:16:53.51#ibcon#about to write, iclass 34, count 0 2006.260.08:16:53.51#ibcon#wrote, iclass 34, count 0 2006.260.08:16:53.51#ibcon#about to read 3, iclass 34, count 0 2006.260.08:16:53.54#ibcon#read 3, iclass 34, count 0 2006.260.08:16:53.54#ibcon#about to read 4, iclass 34, count 0 2006.260.08:16:53.54#ibcon#read 4, iclass 34, count 0 2006.260.08:16:53.54#ibcon#about to read 5, iclass 34, count 0 2006.260.08:16:53.54#ibcon#read 5, iclass 34, count 0 2006.260.08:16:53.54#ibcon#about to read 6, iclass 34, count 0 2006.260.08:16:53.54#ibcon#read 6, iclass 34, count 0 2006.260.08:16:53.54#ibcon#end of sib2, iclass 34, count 0 2006.260.08:16:53.54#ibcon#*after write, iclass 34, count 0 2006.260.08:16:53.54#ibcon#*before return 0, iclass 34, count 0 2006.260.08:16:53.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:53.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.260.08:16:53.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:16:53.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:16:53.54$vc4f8/vbbw=wide 2006.260.08:16:53.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:16:53.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:16:53.54#ibcon#ireg 8 cls_cnt 0 2006.260.08:16:53.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:16:53.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:16:53.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:16:53.61#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:16:53.61#ibcon#first serial, iclass 36, count 0 2006.260.08:16:53.61#ibcon#enter sib2, iclass 36, count 0 2006.260.08:16:53.61#ibcon#flushed, iclass 36, count 0 2006.260.08:16:53.61#ibcon#about to write, iclass 36, count 0 2006.260.08:16:53.61#ibcon#wrote, iclass 36, count 0 2006.260.08:16:53.61#ibcon#about to read 3, iclass 36, count 0 2006.260.08:16:53.63#ibcon#read 3, iclass 36, count 0 2006.260.08:16:53.63#ibcon#about to read 4, iclass 36, count 0 2006.260.08:16:53.63#ibcon#read 4, iclass 36, count 0 2006.260.08:16:53.63#ibcon#about to read 5, iclass 36, count 0 2006.260.08:16:53.63#ibcon#read 5, iclass 36, count 0 2006.260.08:16:53.63#ibcon#about to read 6, iclass 36, count 0 2006.260.08:16:53.63#ibcon#read 6, iclass 36, count 0 2006.260.08:16:53.63#ibcon#end of sib2, iclass 36, count 0 2006.260.08:16:53.63#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:16:53.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:16:53.63#ibcon#[27=BW32\r\n] 2006.260.08:16:53.63#ibcon#*before write, iclass 36, count 0 2006.260.08:16:53.63#ibcon#enter sib2, iclass 36, count 0 2006.260.08:16:53.63#ibcon#flushed, iclass 36, count 0 2006.260.08:16:53.63#ibcon#about to write, iclass 36, count 0 2006.260.08:16:53.63#ibcon#wrote, iclass 36, count 0 2006.260.08:16:53.63#ibcon#about to read 3, iclass 36, count 0 2006.260.08:16:53.66#ibcon#read 3, iclass 36, count 0 2006.260.08:16:53.66#ibcon#about to read 4, iclass 36, count 0 2006.260.08:16:53.66#ibcon#read 4, iclass 36, count 0 2006.260.08:16:53.66#ibcon#about to read 5, iclass 36, count 0 2006.260.08:16:53.66#ibcon#read 5, iclass 36, count 0 2006.260.08:16:53.66#ibcon#about to read 6, iclass 36, count 0 2006.260.08:16:53.66#ibcon#read 6, iclass 36, count 0 2006.260.08:16:53.66#ibcon#end of sib2, iclass 36, count 0 2006.260.08:16:53.66#ibcon#*after write, iclass 36, count 0 2006.260.08:16:53.66#ibcon#*before return 0, iclass 36, count 0 2006.260.08:16:53.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:16:53.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:16:53.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:16:53.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:16:53.66$4f8m12a/ifd4f 2006.260.08:16:53.66$ifd4f/lo= 2006.260.08:16:53.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:16:53.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:16:53.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:16:53.66$ifd4f/patch= 2006.260.08:16:53.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:16:53.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:16:53.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:16:53.66$4f8m12a/"form=m,16.000,1:2 2006.260.08:16:53.66$4f8m12a/"tpicd 2006.260.08:16:53.66$4f8m12a/echo=off 2006.260.08:16:53.66$4f8m12a/xlog=off 2006.260.08:16:53.66:!2006.260.08:17:20 2006.260.08:17:03.14#trakl#Source acquired 2006.260.08:17:05.14#flagr#flagr/antenna,acquired 2006.260.08:17:20.00:preob 2006.260.08:17:21.13/onsource/TRACKING 2006.260.08:17:21.13:!2006.260.08:17:30 2006.260.08:17:30.00:data_valid=on 2006.260.08:17:30.00:midob 2006.260.08:17:30.13/onsource/TRACKING 2006.260.08:17:30.13/wx/22.74,1010.3,89 2006.260.08:17:30.36/cable/+6.4570E-03 2006.260.08:17:31.45/va/01,08,usb,yes,34,36 2006.260.08:17:31.45/va/02,07,usb,yes,34,36 2006.260.08:17:31.45/va/03,08,usb,yes,26,26 2006.260.08:17:31.45/va/04,07,usb,yes,35,38 2006.260.08:17:31.45/va/05,07,usb,yes,39,42 2006.260.08:17:31.45/va/06,06,usb,yes,38,38 2006.260.08:17:31.45/va/07,06,usb,yes,39,39 2006.260.08:17:31.45/va/08,06,usb,yes,42,41 2006.260.08:17:31.68/valo/01,532.99,yes,locked 2006.260.08:17:31.68/valo/02,572.99,yes,locked 2006.260.08:17:31.68/valo/03,672.99,yes,locked 2006.260.08:17:31.68/valo/04,832.99,yes,locked 2006.260.08:17:31.68/valo/05,652.99,yes,locked 2006.260.08:17:31.68/valo/06,772.99,yes,locked 2006.260.08:17:31.68/valo/07,832.99,yes,locked 2006.260.08:17:31.68/valo/08,852.99,yes,locked 2006.260.08:17:32.77/vb/01,04,usb,yes,32,30 2006.260.08:17:32.77/vb/02,05,usb,yes,29,31 2006.260.08:17:32.77/vb/03,04,usb,yes,30,34 2006.260.08:17:32.77/vb/04,05,usb,yes,27,27 2006.260.08:17:32.77/vb/05,04,usb,yes,29,33 2006.260.08:17:32.77/vb/06,04,usb,yes,30,33 2006.260.08:17:32.77/vb/07,04,usb,yes,32,33 2006.260.08:17:32.77/vb/08,04,usb,yes,30,33 2006.260.08:17:33.00/vblo/01,632.99,yes,locked 2006.260.08:17:33.00/vblo/02,640.99,yes,locked 2006.260.08:17:33.00/vblo/03,656.99,yes,locked 2006.260.08:17:33.00/vblo/04,712.99,yes,locked 2006.260.08:17:33.00/vblo/05,744.99,yes,locked 2006.260.08:17:33.00/vblo/06,752.99,yes,locked 2006.260.08:17:33.00/vblo/07,734.99,yes,locked 2006.260.08:17:33.00/vblo/08,744.99,yes,locked 2006.260.08:17:33.15/vabw/8 2006.260.08:17:33.30/vbbw/8 2006.260.08:17:33.39/xfe/off,on,15.2 2006.260.08:17:33.77/ifatt/23,28,28,28 2006.260.08:17:34.08/fmout-gps/S +4.47E-07 2006.260.08:17:34.12:!2006.260.08:18:30 2006.260.08:18:30.00:data_valid=off 2006.260.08:18:30.00:postob 2006.260.08:18:30.08/cable/+6.4574E-03 2006.260.08:18:30.09/wx/22.73,1010.3,89 2006.260.08:18:31.08/fmout-gps/S +4.49E-07 2006.260.08:18:31.08:scan_name=260-0820,k06260,60 2006.260.08:18:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.260.08:18:31.13#flagr#flagr/antenna,new-source 2006.260.08:18:32.13:checkk5 2006.260.08:18:32.63/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:18:33.04/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:18:33.43/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:18:33.93/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:18:34.33/chk_obsdata//k5ts1/T2600817??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:18:34.74/chk_obsdata//k5ts2/T2600817??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:18:35.13/chk_obsdata//k5ts3/T2600817??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:18:35.57/chk_obsdata//k5ts4/T2600817??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:18:36.30/k5log//k5ts1_log_newline 2006.260.08:18:37.13/k5log//k5ts2_log_newline 2006.260.08:18:37.94/k5log//k5ts3_log_newline 2006.260.08:18:38.68/k5log//k5ts4_log_newline 2006.260.08:18:38.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:18:38.70:4f8m12a=3 2006.260.08:18:38.70$4f8m12a/echo=on 2006.260.08:18:38.70$4f8m12a/pcalon 2006.260.08:18:38.70$pcalon/"no phase cal control is implemented here 2006.260.08:18:38.70$4f8m12a/"tpicd=stop 2006.260.08:18:38.70$4f8m12a/vc4f8 2006.260.08:18:38.70$vc4f8/valo=1,532.99 2006.260.08:18:38.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:18:38.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:18:38.71#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:38.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:38.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:38.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:38.71#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:18:38.71#ibcon#first serial, iclass 5, count 0 2006.260.08:18:38.71#ibcon#enter sib2, iclass 5, count 0 2006.260.08:18:38.71#ibcon#flushed, iclass 5, count 0 2006.260.08:18:38.71#ibcon#about to write, iclass 5, count 0 2006.260.08:18:38.71#ibcon#wrote, iclass 5, count 0 2006.260.08:18:38.71#ibcon#about to read 3, iclass 5, count 0 2006.260.08:18:38.75#ibcon#read 3, iclass 5, count 0 2006.260.08:18:38.75#ibcon#about to read 4, iclass 5, count 0 2006.260.08:18:38.75#ibcon#read 4, iclass 5, count 0 2006.260.08:18:38.75#ibcon#about to read 5, iclass 5, count 0 2006.260.08:18:38.75#ibcon#read 5, iclass 5, count 0 2006.260.08:18:38.75#ibcon#about to read 6, iclass 5, count 0 2006.260.08:18:38.75#ibcon#read 6, iclass 5, count 0 2006.260.08:18:38.75#ibcon#end of sib2, iclass 5, count 0 2006.260.08:18:38.75#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:18:38.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:18:38.75#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:18:38.75#ibcon#*before write, iclass 5, count 0 2006.260.08:18:38.75#ibcon#enter sib2, iclass 5, count 0 2006.260.08:18:38.75#ibcon#flushed, iclass 5, count 0 2006.260.08:18:38.75#ibcon#about to write, iclass 5, count 0 2006.260.08:18:38.75#ibcon#wrote, iclass 5, count 0 2006.260.08:18:38.75#ibcon#about to read 3, iclass 5, count 0 2006.260.08:18:38.80#ibcon#read 3, iclass 5, count 0 2006.260.08:18:38.80#ibcon#about to read 4, iclass 5, count 0 2006.260.08:18:38.80#ibcon#read 4, iclass 5, count 0 2006.260.08:18:38.80#ibcon#about to read 5, iclass 5, count 0 2006.260.08:18:38.80#ibcon#read 5, iclass 5, count 0 2006.260.08:18:38.80#ibcon#about to read 6, iclass 5, count 0 2006.260.08:18:38.80#ibcon#read 6, iclass 5, count 0 2006.260.08:18:38.80#ibcon#end of sib2, iclass 5, count 0 2006.260.08:18:38.80#ibcon#*after write, iclass 5, count 0 2006.260.08:18:38.80#ibcon#*before return 0, iclass 5, count 0 2006.260.08:18:38.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:38.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:38.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:18:38.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:18:38.80$vc4f8/va=1,8 2006.260.08:18:38.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:18:38.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:18:38.80#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:38.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:38.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:38.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:38.80#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:18:38.80#ibcon#first serial, iclass 7, count 2 2006.260.08:18:38.80#ibcon#enter sib2, iclass 7, count 2 2006.260.08:18:38.80#ibcon#flushed, iclass 7, count 2 2006.260.08:18:38.80#ibcon#about to write, iclass 7, count 2 2006.260.08:18:38.80#ibcon#wrote, iclass 7, count 2 2006.260.08:18:38.80#ibcon#about to read 3, iclass 7, count 2 2006.260.08:18:38.82#ibcon#read 3, iclass 7, count 2 2006.260.08:18:38.82#ibcon#about to read 4, iclass 7, count 2 2006.260.08:18:38.82#ibcon#read 4, iclass 7, count 2 2006.260.08:18:38.82#ibcon#about to read 5, iclass 7, count 2 2006.260.08:18:38.82#ibcon#read 5, iclass 7, count 2 2006.260.08:18:38.82#ibcon#about to read 6, iclass 7, count 2 2006.260.08:18:38.82#ibcon#read 6, iclass 7, count 2 2006.260.08:18:38.82#ibcon#end of sib2, iclass 7, count 2 2006.260.08:18:38.82#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:18:38.82#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:18:38.82#ibcon#[25=AT01-08\r\n] 2006.260.08:18:38.82#ibcon#*before write, iclass 7, count 2 2006.260.08:18:38.82#ibcon#enter sib2, iclass 7, count 2 2006.260.08:18:38.82#ibcon#flushed, iclass 7, count 2 2006.260.08:18:38.82#ibcon#about to write, iclass 7, count 2 2006.260.08:18:38.82#ibcon#wrote, iclass 7, count 2 2006.260.08:18:38.82#ibcon#about to read 3, iclass 7, count 2 2006.260.08:18:38.85#ibcon#read 3, iclass 7, count 2 2006.260.08:18:38.85#ibcon#about to read 4, iclass 7, count 2 2006.260.08:18:38.85#ibcon#read 4, iclass 7, count 2 2006.260.08:18:38.85#ibcon#about to read 5, iclass 7, count 2 2006.260.08:18:38.85#ibcon#read 5, iclass 7, count 2 2006.260.08:18:38.85#ibcon#about to read 6, iclass 7, count 2 2006.260.08:18:38.85#ibcon#read 6, iclass 7, count 2 2006.260.08:18:38.85#ibcon#end of sib2, iclass 7, count 2 2006.260.08:18:38.85#ibcon#*after write, iclass 7, count 2 2006.260.08:18:38.85#ibcon#*before return 0, iclass 7, count 2 2006.260.08:18:38.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:38.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:38.85#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:18:38.85#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:38.85#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:38.97#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:38.97#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:38.97#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:18:38.97#ibcon#first serial, iclass 7, count 0 2006.260.08:18:38.97#ibcon#enter sib2, iclass 7, count 0 2006.260.08:18:38.97#ibcon#flushed, iclass 7, count 0 2006.260.08:18:38.97#ibcon#about to write, iclass 7, count 0 2006.260.08:18:38.97#ibcon#wrote, iclass 7, count 0 2006.260.08:18:38.97#ibcon#about to read 3, iclass 7, count 0 2006.260.08:18:38.99#ibcon#read 3, iclass 7, count 0 2006.260.08:18:38.99#ibcon#about to read 4, iclass 7, count 0 2006.260.08:18:38.99#ibcon#read 4, iclass 7, count 0 2006.260.08:18:38.99#ibcon#about to read 5, iclass 7, count 0 2006.260.08:18:38.99#ibcon#read 5, iclass 7, count 0 2006.260.08:18:38.99#ibcon#about to read 6, iclass 7, count 0 2006.260.08:18:38.99#ibcon#read 6, iclass 7, count 0 2006.260.08:18:38.99#ibcon#end of sib2, iclass 7, count 0 2006.260.08:18:38.99#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:18:38.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:18:38.99#ibcon#[25=USB\r\n] 2006.260.08:18:38.99#ibcon#*before write, iclass 7, count 0 2006.260.08:18:38.99#ibcon#enter sib2, iclass 7, count 0 2006.260.08:18:38.99#ibcon#flushed, iclass 7, count 0 2006.260.08:18:38.99#ibcon#about to write, iclass 7, count 0 2006.260.08:18:38.99#ibcon#wrote, iclass 7, count 0 2006.260.08:18:38.99#ibcon#about to read 3, iclass 7, count 0 2006.260.08:18:39.02#ibcon#read 3, iclass 7, count 0 2006.260.08:18:39.02#ibcon#about to read 4, iclass 7, count 0 2006.260.08:18:39.02#ibcon#read 4, iclass 7, count 0 2006.260.08:18:39.02#ibcon#about to read 5, iclass 7, count 0 2006.260.08:18:39.02#ibcon#read 5, iclass 7, count 0 2006.260.08:18:39.02#ibcon#about to read 6, iclass 7, count 0 2006.260.08:18:39.02#ibcon#read 6, iclass 7, count 0 2006.260.08:18:39.02#ibcon#end of sib2, iclass 7, count 0 2006.260.08:18:39.02#ibcon#*after write, iclass 7, count 0 2006.260.08:18:39.02#ibcon#*before return 0, iclass 7, count 0 2006.260.08:18:39.02#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:39.02#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:39.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:18:39.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:18:39.02$vc4f8/valo=2,572.99 2006.260.08:18:39.02#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:18:39.02#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:18:39.02#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:39.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:39.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:39.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:39.02#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:18:39.02#ibcon#first serial, iclass 11, count 0 2006.260.08:18:39.02#ibcon#enter sib2, iclass 11, count 0 2006.260.08:18:39.02#ibcon#flushed, iclass 11, count 0 2006.260.08:18:39.02#ibcon#about to write, iclass 11, count 0 2006.260.08:18:39.02#ibcon#wrote, iclass 11, count 0 2006.260.08:18:39.02#ibcon#about to read 3, iclass 11, count 0 2006.260.08:18:39.04#ibcon#read 3, iclass 11, count 0 2006.260.08:18:39.04#ibcon#about to read 4, iclass 11, count 0 2006.260.08:18:39.04#ibcon#read 4, iclass 11, count 0 2006.260.08:18:39.04#ibcon#about to read 5, iclass 11, count 0 2006.260.08:18:39.04#ibcon#read 5, iclass 11, count 0 2006.260.08:18:39.04#ibcon#about to read 6, iclass 11, count 0 2006.260.08:18:39.04#ibcon#read 6, iclass 11, count 0 2006.260.08:18:39.04#ibcon#end of sib2, iclass 11, count 0 2006.260.08:18:39.04#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:18:39.04#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:18:39.04#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:18:39.04#ibcon#*before write, iclass 11, count 0 2006.260.08:18:39.04#ibcon#enter sib2, iclass 11, count 0 2006.260.08:18:39.04#ibcon#flushed, iclass 11, count 0 2006.260.08:18:39.04#ibcon#about to write, iclass 11, count 0 2006.260.08:18:39.04#ibcon#wrote, iclass 11, count 0 2006.260.08:18:39.04#ibcon#about to read 3, iclass 11, count 0 2006.260.08:18:39.08#ibcon#read 3, iclass 11, count 0 2006.260.08:18:39.08#ibcon#about to read 4, iclass 11, count 0 2006.260.08:18:39.08#ibcon#read 4, iclass 11, count 0 2006.260.08:18:39.08#ibcon#about to read 5, iclass 11, count 0 2006.260.08:18:39.08#ibcon#read 5, iclass 11, count 0 2006.260.08:18:39.08#ibcon#about to read 6, iclass 11, count 0 2006.260.08:18:39.08#ibcon#read 6, iclass 11, count 0 2006.260.08:18:39.08#ibcon#end of sib2, iclass 11, count 0 2006.260.08:18:39.08#ibcon#*after write, iclass 11, count 0 2006.260.08:18:39.08#ibcon#*before return 0, iclass 11, count 0 2006.260.08:18:39.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:39.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:39.08#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:18:39.08#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:18:39.08$vc4f8/va=2,7 2006.260.08:18:39.08#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.08:18:39.08#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.08:18:39.08#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:39.08#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:39.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:39.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:39.14#ibcon#enter wrdev, iclass 13, count 2 2006.260.08:18:39.14#ibcon#first serial, iclass 13, count 2 2006.260.08:18:39.14#ibcon#enter sib2, iclass 13, count 2 2006.260.08:18:39.14#ibcon#flushed, iclass 13, count 2 2006.260.08:18:39.14#ibcon#about to write, iclass 13, count 2 2006.260.08:18:39.14#ibcon#wrote, iclass 13, count 2 2006.260.08:18:39.14#ibcon#about to read 3, iclass 13, count 2 2006.260.08:18:39.16#ibcon#read 3, iclass 13, count 2 2006.260.08:18:39.16#ibcon#about to read 4, iclass 13, count 2 2006.260.08:18:39.16#ibcon#read 4, iclass 13, count 2 2006.260.08:18:39.16#ibcon#about to read 5, iclass 13, count 2 2006.260.08:18:39.16#ibcon#read 5, iclass 13, count 2 2006.260.08:18:39.16#ibcon#about to read 6, iclass 13, count 2 2006.260.08:18:39.16#ibcon#read 6, iclass 13, count 2 2006.260.08:18:39.16#ibcon#end of sib2, iclass 13, count 2 2006.260.08:18:39.16#ibcon#*mode == 0, iclass 13, count 2 2006.260.08:18:39.16#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.08:18:39.16#ibcon#[25=AT02-07\r\n] 2006.260.08:18:39.16#ibcon#*before write, iclass 13, count 2 2006.260.08:18:39.16#ibcon#enter sib2, iclass 13, count 2 2006.260.08:18:39.16#ibcon#flushed, iclass 13, count 2 2006.260.08:18:39.16#ibcon#about to write, iclass 13, count 2 2006.260.08:18:39.16#ibcon#wrote, iclass 13, count 2 2006.260.08:18:39.16#ibcon#about to read 3, iclass 13, count 2 2006.260.08:18:39.19#ibcon#read 3, iclass 13, count 2 2006.260.08:18:39.19#ibcon#about to read 4, iclass 13, count 2 2006.260.08:18:39.19#ibcon#read 4, iclass 13, count 2 2006.260.08:18:39.19#ibcon#about to read 5, iclass 13, count 2 2006.260.08:18:39.19#ibcon#read 5, iclass 13, count 2 2006.260.08:18:39.19#ibcon#about to read 6, iclass 13, count 2 2006.260.08:18:39.19#ibcon#read 6, iclass 13, count 2 2006.260.08:18:39.19#ibcon#end of sib2, iclass 13, count 2 2006.260.08:18:39.19#ibcon#*after write, iclass 13, count 2 2006.260.08:18:39.19#ibcon#*before return 0, iclass 13, count 2 2006.260.08:18:39.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:39.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:39.19#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.08:18:39.19#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:39.19#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:39.31#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:39.31#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:39.31#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:18:39.31#ibcon#first serial, iclass 13, count 0 2006.260.08:18:39.31#ibcon#enter sib2, iclass 13, count 0 2006.260.08:18:39.31#ibcon#flushed, iclass 13, count 0 2006.260.08:18:39.31#ibcon#about to write, iclass 13, count 0 2006.260.08:18:39.31#ibcon#wrote, iclass 13, count 0 2006.260.08:18:39.31#ibcon#about to read 3, iclass 13, count 0 2006.260.08:18:39.33#ibcon#read 3, iclass 13, count 0 2006.260.08:18:39.33#ibcon#about to read 4, iclass 13, count 0 2006.260.08:18:39.33#ibcon#read 4, iclass 13, count 0 2006.260.08:18:39.33#ibcon#about to read 5, iclass 13, count 0 2006.260.08:18:39.33#ibcon#read 5, iclass 13, count 0 2006.260.08:18:39.33#ibcon#about to read 6, iclass 13, count 0 2006.260.08:18:39.33#ibcon#read 6, iclass 13, count 0 2006.260.08:18:39.33#ibcon#end of sib2, iclass 13, count 0 2006.260.08:18:39.33#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:18:39.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:18:39.33#ibcon#[25=USB\r\n] 2006.260.08:18:39.33#ibcon#*before write, iclass 13, count 0 2006.260.08:18:39.33#ibcon#enter sib2, iclass 13, count 0 2006.260.08:18:39.33#ibcon#flushed, iclass 13, count 0 2006.260.08:18:39.33#ibcon#about to write, iclass 13, count 0 2006.260.08:18:39.33#ibcon#wrote, iclass 13, count 0 2006.260.08:18:39.33#ibcon#about to read 3, iclass 13, count 0 2006.260.08:18:39.36#ibcon#read 3, iclass 13, count 0 2006.260.08:18:39.36#ibcon#about to read 4, iclass 13, count 0 2006.260.08:18:39.36#ibcon#read 4, iclass 13, count 0 2006.260.08:18:39.36#ibcon#about to read 5, iclass 13, count 0 2006.260.08:18:39.36#ibcon#read 5, iclass 13, count 0 2006.260.08:18:39.36#ibcon#about to read 6, iclass 13, count 0 2006.260.08:18:39.36#ibcon#read 6, iclass 13, count 0 2006.260.08:18:39.36#ibcon#end of sib2, iclass 13, count 0 2006.260.08:18:39.36#ibcon#*after write, iclass 13, count 0 2006.260.08:18:39.36#ibcon#*before return 0, iclass 13, count 0 2006.260.08:18:39.36#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:39.36#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:39.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:18:39.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:18:39.36$vc4f8/valo=3,672.99 2006.260.08:18:39.36#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:18:39.36#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:18:39.36#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:39.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:39.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:39.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:39.36#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:18:39.36#ibcon#first serial, iclass 15, count 0 2006.260.08:18:39.36#ibcon#enter sib2, iclass 15, count 0 2006.260.08:18:39.36#ibcon#flushed, iclass 15, count 0 2006.260.08:18:39.36#ibcon#about to write, iclass 15, count 0 2006.260.08:18:39.36#ibcon#wrote, iclass 15, count 0 2006.260.08:18:39.36#ibcon#about to read 3, iclass 15, count 0 2006.260.08:18:39.38#ibcon#read 3, iclass 15, count 0 2006.260.08:18:39.38#ibcon#about to read 4, iclass 15, count 0 2006.260.08:18:39.38#ibcon#read 4, iclass 15, count 0 2006.260.08:18:39.38#ibcon#about to read 5, iclass 15, count 0 2006.260.08:18:39.38#ibcon#read 5, iclass 15, count 0 2006.260.08:18:39.38#ibcon#about to read 6, iclass 15, count 0 2006.260.08:18:39.38#ibcon#read 6, iclass 15, count 0 2006.260.08:18:39.38#ibcon#end of sib2, iclass 15, count 0 2006.260.08:18:39.38#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:18:39.38#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:18:39.38#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:18:39.38#ibcon#*before write, iclass 15, count 0 2006.260.08:18:39.38#ibcon#enter sib2, iclass 15, count 0 2006.260.08:18:39.38#ibcon#flushed, iclass 15, count 0 2006.260.08:18:39.38#ibcon#about to write, iclass 15, count 0 2006.260.08:18:39.38#ibcon#wrote, iclass 15, count 0 2006.260.08:18:39.38#ibcon#about to read 3, iclass 15, count 0 2006.260.08:18:39.42#ibcon#read 3, iclass 15, count 0 2006.260.08:18:39.42#ibcon#about to read 4, iclass 15, count 0 2006.260.08:18:39.42#ibcon#read 4, iclass 15, count 0 2006.260.08:18:39.42#ibcon#about to read 5, iclass 15, count 0 2006.260.08:18:39.42#ibcon#read 5, iclass 15, count 0 2006.260.08:18:39.42#ibcon#about to read 6, iclass 15, count 0 2006.260.08:18:39.42#ibcon#read 6, iclass 15, count 0 2006.260.08:18:39.42#ibcon#end of sib2, iclass 15, count 0 2006.260.08:18:39.42#ibcon#*after write, iclass 15, count 0 2006.260.08:18:39.42#ibcon#*before return 0, iclass 15, count 0 2006.260.08:18:39.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:39.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:39.42#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:18:39.42#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:18:39.42$vc4f8/va=3,8 2006.260.08:18:39.42#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:18:39.42#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:18:39.42#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:39.42#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:39.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:39.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:39.48#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:18:39.48#ibcon#first serial, iclass 17, count 2 2006.260.08:18:39.48#ibcon#enter sib2, iclass 17, count 2 2006.260.08:18:39.48#ibcon#flushed, iclass 17, count 2 2006.260.08:18:39.48#ibcon#about to write, iclass 17, count 2 2006.260.08:18:39.48#ibcon#wrote, iclass 17, count 2 2006.260.08:18:39.48#ibcon#about to read 3, iclass 17, count 2 2006.260.08:18:39.50#ibcon#read 3, iclass 17, count 2 2006.260.08:18:39.50#ibcon#about to read 4, iclass 17, count 2 2006.260.08:18:39.50#ibcon#read 4, iclass 17, count 2 2006.260.08:18:39.50#ibcon#about to read 5, iclass 17, count 2 2006.260.08:18:39.50#ibcon#read 5, iclass 17, count 2 2006.260.08:18:39.50#ibcon#about to read 6, iclass 17, count 2 2006.260.08:18:39.50#ibcon#read 6, iclass 17, count 2 2006.260.08:18:39.50#ibcon#end of sib2, iclass 17, count 2 2006.260.08:18:39.50#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:18:39.50#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:18:39.50#ibcon#[25=AT03-08\r\n] 2006.260.08:18:39.50#ibcon#*before write, iclass 17, count 2 2006.260.08:18:39.50#ibcon#enter sib2, iclass 17, count 2 2006.260.08:18:39.50#ibcon#flushed, iclass 17, count 2 2006.260.08:18:39.50#ibcon#about to write, iclass 17, count 2 2006.260.08:18:39.50#ibcon#wrote, iclass 17, count 2 2006.260.08:18:39.50#ibcon#about to read 3, iclass 17, count 2 2006.260.08:18:39.54#ibcon#read 3, iclass 17, count 2 2006.260.08:18:39.54#ibcon#about to read 4, iclass 17, count 2 2006.260.08:18:39.54#ibcon#read 4, iclass 17, count 2 2006.260.08:18:39.54#ibcon#about to read 5, iclass 17, count 2 2006.260.08:18:39.54#ibcon#read 5, iclass 17, count 2 2006.260.08:18:39.54#ibcon#about to read 6, iclass 17, count 2 2006.260.08:18:39.54#ibcon#read 6, iclass 17, count 2 2006.260.08:18:39.54#ibcon#end of sib2, iclass 17, count 2 2006.260.08:18:39.54#ibcon#*after write, iclass 17, count 2 2006.260.08:18:39.54#ibcon#*before return 0, iclass 17, count 2 2006.260.08:18:39.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:39.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:39.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:18:39.54#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:39.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:39.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:39.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:39.66#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:18:39.66#ibcon#first serial, iclass 17, count 0 2006.260.08:18:39.66#ibcon#enter sib2, iclass 17, count 0 2006.260.08:18:39.66#ibcon#flushed, iclass 17, count 0 2006.260.08:18:39.66#ibcon#about to write, iclass 17, count 0 2006.260.08:18:39.66#ibcon#wrote, iclass 17, count 0 2006.260.08:18:39.66#ibcon#about to read 3, iclass 17, count 0 2006.260.08:18:39.68#ibcon#read 3, iclass 17, count 0 2006.260.08:18:39.68#ibcon#about to read 4, iclass 17, count 0 2006.260.08:18:39.68#ibcon#read 4, iclass 17, count 0 2006.260.08:18:39.68#ibcon#about to read 5, iclass 17, count 0 2006.260.08:18:39.68#ibcon#read 5, iclass 17, count 0 2006.260.08:18:39.68#ibcon#about to read 6, iclass 17, count 0 2006.260.08:18:39.68#ibcon#read 6, iclass 17, count 0 2006.260.08:18:39.68#ibcon#end of sib2, iclass 17, count 0 2006.260.08:18:39.68#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:18:39.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:18:39.68#ibcon#[25=USB\r\n] 2006.260.08:18:39.68#ibcon#*before write, iclass 17, count 0 2006.260.08:18:39.68#ibcon#enter sib2, iclass 17, count 0 2006.260.08:18:39.68#ibcon#flushed, iclass 17, count 0 2006.260.08:18:39.68#ibcon#about to write, iclass 17, count 0 2006.260.08:18:39.68#ibcon#wrote, iclass 17, count 0 2006.260.08:18:39.68#ibcon#about to read 3, iclass 17, count 0 2006.260.08:18:39.71#ibcon#read 3, iclass 17, count 0 2006.260.08:18:39.71#ibcon#about to read 4, iclass 17, count 0 2006.260.08:18:39.71#ibcon#read 4, iclass 17, count 0 2006.260.08:18:39.71#ibcon#about to read 5, iclass 17, count 0 2006.260.08:18:39.71#ibcon#read 5, iclass 17, count 0 2006.260.08:18:39.71#ibcon#about to read 6, iclass 17, count 0 2006.260.08:18:39.71#ibcon#read 6, iclass 17, count 0 2006.260.08:18:39.71#ibcon#end of sib2, iclass 17, count 0 2006.260.08:18:39.71#ibcon#*after write, iclass 17, count 0 2006.260.08:18:39.71#ibcon#*before return 0, iclass 17, count 0 2006.260.08:18:39.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:39.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:39.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:18:39.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:18:39.71$vc4f8/valo=4,832.99 2006.260.08:18:39.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:18:39.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:18:39.71#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:39.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:39.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:39.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:39.71#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:18:39.71#ibcon#first serial, iclass 19, count 0 2006.260.08:18:39.71#ibcon#enter sib2, iclass 19, count 0 2006.260.08:18:39.71#ibcon#flushed, iclass 19, count 0 2006.260.08:18:39.71#ibcon#about to write, iclass 19, count 0 2006.260.08:18:39.71#ibcon#wrote, iclass 19, count 0 2006.260.08:18:39.71#ibcon#about to read 3, iclass 19, count 0 2006.260.08:18:39.73#ibcon#read 3, iclass 19, count 0 2006.260.08:18:39.73#ibcon#about to read 4, iclass 19, count 0 2006.260.08:18:39.73#ibcon#read 4, iclass 19, count 0 2006.260.08:18:39.73#ibcon#about to read 5, iclass 19, count 0 2006.260.08:18:39.73#ibcon#read 5, iclass 19, count 0 2006.260.08:18:39.73#ibcon#about to read 6, iclass 19, count 0 2006.260.08:18:39.73#ibcon#read 6, iclass 19, count 0 2006.260.08:18:39.73#ibcon#end of sib2, iclass 19, count 0 2006.260.08:18:39.73#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:18:39.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:18:39.73#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:18:39.73#ibcon#*before write, iclass 19, count 0 2006.260.08:18:39.73#ibcon#enter sib2, iclass 19, count 0 2006.260.08:18:39.73#ibcon#flushed, iclass 19, count 0 2006.260.08:18:39.73#ibcon#about to write, iclass 19, count 0 2006.260.08:18:39.73#ibcon#wrote, iclass 19, count 0 2006.260.08:18:39.73#ibcon#about to read 3, iclass 19, count 0 2006.260.08:18:39.77#ibcon#read 3, iclass 19, count 0 2006.260.08:18:39.77#ibcon#about to read 4, iclass 19, count 0 2006.260.08:18:39.77#ibcon#read 4, iclass 19, count 0 2006.260.08:18:39.77#ibcon#about to read 5, iclass 19, count 0 2006.260.08:18:39.77#ibcon#read 5, iclass 19, count 0 2006.260.08:18:39.77#ibcon#about to read 6, iclass 19, count 0 2006.260.08:18:39.77#ibcon#read 6, iclass 19, count 0 2006.260.08:18:39.77#ibcon#end of sib2, iclass 19, count 0 2006.260.08:18:39.77#ibcon#*after write, iclass 19, count 0 2006.260.08:18:39.77#ibcon#*before return 0, iclass 19, count 0 2006.260.08:18:39.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:39.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:39.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:18:39.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:18:39.77$vc4f8/va=4,7 2006.260.08:18:39.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.08:18:39.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.08:18:39.77#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:39.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:39.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:39.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:39.83#ibcon#enter wrdev, iclass 21, count 2 2006.260.08:18:39.83#ibcon#first serial, iclass 21, count 2 2006.260.08:18:39.83#ibcon#enter sib2, iclass 21, count 2 2006.260.08:18:39.83#ibcon#flushed, iclass 21, count 2 2006.260.08:18:39.83#ibcon#about to write, iclass 21, count 2 2006.260.08:18:39.83#ibcon#wrote, iclass 21, count 2 2006.260.08:18:39.83#ibcon#about to read 3, iclass 21, count 2 2006.260.08:18:39.85#ibcon#read 3, iclass 21, count 2 2006.260.08:18:39.85#ibcon#about to read 4, iclass 21, count 2 2006.260.08:18:39.85#ibcon#read 4, iclass 21, count 2 2006.260.08:18:39.85#ibcon#about to read 5, iclass 21, count 2 2006.260.08:18:39.85#ibcon#read 5, iclass 21, count 2 2006.260.08:18:39.85#ibcon#about to read 6, iclass 21, count 2 2006.260.08:18:39.85#ibcon#read 6, iclass 21, count 2 2006.260.08:18:39.85#ibcon#end of sib2, iclass 21, count 2 2006.260.08:18:39.85#ibcon#*mode == 0, iclass 21, count 2 2006.260.08:18:39.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.08:18:39.85#ibcon#[25=AT04-07\r\n] 2006.260.08:18:39.85#ibcon#*before write, iclass 21, count 2 2006.260.08:18:39.85#ibcon#enter sib2, iclass 21, count 2 2006.260.08:18:39.85#ibcon#flushed, iclass 21, count 2 2006.260.08:18:39.85#ibcon#about to write, iclass 21, count 2 2006.260.08:18:39.85#ibcon#wrote, iclass 21, count 2 2006.260.08:18:39.85#ibcon#about to read 3, iclass 21, count 2 2006.260.08:18:39.88#ibcon#read 3, iclass 21, count 2 2006.260.08:18:39.88#ibcon#about to read 4, iclass 21, count 2 2006.260.08:18:39.88#ibcon#read 4, iclass 21, count 2 2006.260.08:18:39.88#ibcon#about to read 5, iclass 21, count 2 2006.260.08:18:39.88#ibcon#read 5, iclass 21, count 2 2006.260.08:18:39.88#ibcon#about to read 6, iclass 21, count 2 2006.260.08:18:39.88#ibcon#read 6, iclass 21, count 2 2006.260.08:18:39.88#ibcon#end of sib2, iclass 21, count 2 2006.260.08:18:39.88#ibcon#*after write, iclass 21, count 2 2006.260.08:18:39.88#ibcon#*before return 0, iclass 21, count 2 2006.260.08:18:39.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:39.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:39.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.08:18:39.88#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:39.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:40.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:40.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:40.00#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:18:40.00#ibcon#first serial, iclass 21, count 0 2006.260.08:18:40.00#ibcon#enter sib2, iclass 21, count 0 2006.260.08:18:40.00#ibcon#flushed, iclass 21, count 0 2006.260.08:18:40.00#ibcon#about to write, iclass 21, count 0 2006.260.08:18:40.00#ibcon#wrote, iclass 21, count 0 2006.260.08:18:40.00#ibcon#about to read 3, iclass 21, count 0 2006.260.08:18:40.02#ibcon#read 3, iclass 21, count 0 2006.260.08:18:40.02#ibcon#about to read 4, iclass 21, count 0 2006.260.08:18:40.02#ibcon#read 4, iclass 21, count 0 2006.260.08:18:40.02#ibcon#about to read 5, iclass 21, count 0 2006.260.08:18:40.02#ibcon#read 5, iclass 21, count 0 2006.260.08:18:40.02#ibcon#about to read 6, iclass 21, count 0 2006.260.08:18:40.02#ibcon#read 6, iclass 21, count 0 2006.260.08:18:40.02#ibcon#end of sib2, iclass 21, count 0 2006.260.08:18:40.02#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:18:40.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:18:40.02#ibcon#[25=USB\r\n] 2006.260.08:18:40.02#ibcon#*before write, iclass 21, count 0 2006.260.08:18:40.02#ibcon#enter sib2, iclass 21, count 0 2006.260.08:18:40.02#ibcon#flushed, iclass 21, count 0 2006.260.08:18:40.02#ibcon#about to write, iclass 21, count 0 2006.260.08:18:40.02#ibcon#wrote, iclass 21, count 0 2006.260.08:18:40.02#ibcon#about to read 3, iclass 21, count 0 2006.260.08:18:40.05#ibcon#read 3, iclass 21, count 0 2006.260.08:18:40.05#ibcon#about to read 4, iclass 21, count 0 2006.260.08:18:40.05#ibcon#read 4, iclass 21, count 0 2006.260.08:18:40.05#ibcon#about to read 5, iclass 21, count 0 2006.260.08:18:40.05#ibcon#read 5, iclass 21, count 0 2006.260.08:18:40.05#ibcon#about to read 6, iclass 21, count 0 2006.260.08:18:40.05#ibcon#read 6, iclass 21, count 0 2006.260.08:18:40.05#ibcon#end of sib2, iclass 21, count 0 2006.260.08:18:40.05#ibcon#*after write, iclass 21, count 0 2006.260.08:18:40.05#ibcon#*before return 0, iclass 21, count 0 2006.260.08:18:40.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:40.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:40.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:18:40.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:18:40.05$vc4f8/valo=5,652.99 2006.260.08:18:40.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.08:18:40.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.08:18:40.05#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:40.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:40.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:40.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:40.05#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:18:40.05#ibcon#first serial, iclass 23, count 0 2006.260.08:18:40.05#ibcon#enter sib2, iclass 23, count 0 2006.260.08:18:40.05#ibcon#flushed, iclass 23, count 0 2006.260.08:18:40.05#ibcon#about to write, iclass 23, count 0 2006.260.08:18:40.05#ibcon#wrote, iclass 23, count 0 2006.260.08:18:40.05#ibcon#about to read 3, iclass 23, count 0 2006.260.08:18:40.07#ibcon#read 3, iclass 23, count 0 2006.260.08:18:40.07#ibcon#about to read 4, iclass 23, count 0 2006.260.08:18:40.07#ibcon#read 4, iclass 23, count 0 2006.260.08:18:40.07#ibcon#about to read 5, iclass 23, count 0 2006.260.08:18:40.07#ibcon#read 5, iclass 23, count 0 2006.260.08:18:40.07#ibcon#about to read 6, iclass 23, count 0 2006.260.08:18:40.07#ibcon#read 6, iclass 23, count 0 2006.260.08:18:40.07#ibcon#end of sib2, iclass 23, count 0 2006.260.08:18:40.07#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:18:40.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:18:40.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:18:40.07#ibcon#*before write, iclass 23, count 0 2006.260.08:18:40.07#ibcon#enter sib2, iclass 23, count 0 2006.260.08:18:40.07#ibcon#flushed, iclass 23, count 0 2006.260.08:18:40.07#ibcon#about to write, iclass 23, count 0 2006.260.08:18:40.07#ibcon#wrote, iclass 23, count 0 2006.260.08:18:40.07#ibcon#about to read 3, iclass 23, count 0 2006.260.08:18:40.11#ibcon#read 3, iclass 23, count 0 2006.260.08:18:40.11#ibcon#about to read 4, iclass 23, count 0 2006.260.08:18:40.11#ibcon#read 4, iclass 23, count 0 2006.260.08:18:40.11#ibcon#about to read 5, iclass 23, count 0 2006.260.08:18:40.11#ibcon#read 5, iclass 23, count 0 2006.260.08:18:40.11#ibcon#about to read 6, iclass 23, count 0 2006.260.08:18:40.11#ibcon#read 6, iclass 23, count 0 2006.260.08:18:40.11#ibcon#end of sib2, iclass 23, count 0 2006.260.08:18:40.11#ibcon#*after write, iclass 23, count 0 2006.260.08:18:40.11#ibcon#*before return 0, iclass 23, count 0 2006.260.08:18:40.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:40.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:40.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:18:40.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:18:40.11$vc4f8/va=5,7 2006.260.08:18:40.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.08:18:40.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.08:18:40.11#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:40.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:40.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:40.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:40.17#ibcon#enter wrdev, iclass 25, count 2 2006.260.08:18:40.17#ibcon#first serial, iclass 25, count 2 2006.260.08:18:40.17#ibcon#enter sib2, iclass 25, count 2 2006.260.08:18:40.17#ibcon#flushed, iclass 25, count 2 2006.260.08:18:40.17#ibcon#about to write, iclass 25, count 2 2006.260.08:18:40.17#ibcon#wrote, iclass 25, count 2 2006.260.08:18:40.17#ibcon#about to read 3, iclass 25, count 2 2006.260.08:18:40.19#ibcon#read 3, iclass 25, count 2 2006.260.08:18:40.19#ibcon#about to read 4, iclass 25, count 2 2006.260.08:18:40.19#ibcon#read 4, iclass 25, count 2 2006.260.08:18:40.19#ibcon#about to read 5, iclass 25, count 2 2006.260.08:18:40.19#ibcon#read 5, iclass 25, count 2 2006.260.08:18:40.19#ibcon#about to read 6, iclass 25, count 2 2006.260.08:18:40.19#ibcon#read 6, iclass 25, count 2 2006.260.08:18:40.19#ibcon#end of sib2, iclass 25, count 2 2006.260.08:18:40.19#ibcon#*mode == 0, iclass 25, count 2 2006.260.08:18:40.19#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.08:18:40.19#ibcon#[25=AT05-07\r\n] 2006.260.08:18:40.19#ibcon#*before write, iclass 25, count 2 2006.260.08:18:40.19#ibcon#enter sib2, iclass 25, count 2 2006.260.08:18:40.19#ibcon#flushed, iclass 25, count 2 2006.260.08:18:40.19#ibcon#about to write, iclass 25, count 2 2006.260.08:18:40.19#ibcon#wrote, iclass 25, count 2 2006.260.08:18:40.19#ibcon#about to read 3, iclass 25, count 2 2006.260.08:18:40.22#ibcon#read 3, iclass 25, count 2 2006.260.08:18:40.22#ibcon#about to read 4, iclass 25, count 2 2006.260.08:18:40.22#ibcon#read 4, iclass 25, count 2 2006.260.08:18:40.22#ibcon#about to read 5, iclass 25, count 2 2006.260.08:18:40.22#ibcon#read 5, iclass 25, count 2 2006.260.08:18:40.22#ibcon#about to read 6, iclass 25, count 2 2006.260.08:18:40.22#ibcon#read 6, iclass 25, count 2 2006.260.08:18:40.22#ibcon#end of sib2, iclass 25, count 2 2006.260.08:18:40.22#ibcon#*after write, iclass 25, count 2 2006.260.08:18:40.22#ibcon#*before return 0, iclass 25, count 2 2006.260.08:18:40.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:40.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:40.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.08:18:40.22#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:40.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:40.34#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:40.34#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:40.34#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:18:40.34#ibcon#first serial, iclass 25, count 0 2006.260.08:18:40.34#ibcon#enter sib2, iclass 25, count 0 2006.260.08:18:40.34#ibcon#flushed, iclass 25, count 0 2006.260.08:18:40.34#ibcon#about to write, iclass 25, count 0 2006.260.08:18:40.34#ibcon#wrote, iclass 25, count 0 2006.260.08:18:40.34#ibcon#about to read 3, iclass 25, count 0 2006.260.08:18:40.36#ibcon#read 3, iclass 25, count 0 2006.260.08:18:40.36#ibcon#about to read 4, iclass 25, count 0 2006.260.08:18:40.36#ibcon#read 4, iclass 25, count 0 2006.260.08:18:40.36#ibcon#about to read 5, iclass 25, count 0 2006.260.08:18:40.36#ibcon#read 5, iclass 25, count 0 2006.260.08:18:40.36#ibcon#about to read 6, iclass 25, count 0 2006.260.08:18:40.36#ibcon#read 6, iclass 25, count 0 2006.260.08:18:40.36#ibcon#end of sib2, iclass 25, count 0 2006.260.08:18:40.36#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:18:40.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:18:40.36#ibcon#[25=USB\r\n] 2006.260.08:18:40.36#ibcon#*before write, iclass 25, count 0 2006.260.08:18:40.36#ibcon#enter sib2, iclass 25, count 0 2006.260.08:18:40.36#ibcon#flushed, iclass 25, count 0 2006.260.08:18:40.36#ibcon#about to write, iclass 25, count 0 2006.260.08:18:40.36#ibcon#wrote, iclass 25, count 0 2006.260.08:18:40.36#ibcon#about to read 3, iclass 25, count 0 2006.260.08:18:40.39#ibcon#read 3, iclass 25, count 0 2006.260.08:18:40.39#ibcon#about to read 4, iclass 25, count 0 2006.260.08:18:40.39#ibcon#read 4, iclass 25, count 0 2006.260.08:18:40.39#ibcon#about to read 5, iclass 25, count 0 2006.260.08:18:40.39#ibcon#read 5, iclass 25, count 0 2006.260.08:18:40.39#ibcon#about to read 6, iclass 25, count 0 2006.260.08:18:40.39#ibcon#read 6, iclass 25, count 0 2006.260.08:18:40.39#ibcon#end of sib2, iclass 25, count 0 2006.260.08:18:40.39#ibcon#*after write, iclass 25, count 0 2006.260.08:18:40.39#ibcon#*before return 0, iclass 25, count 0 2006.260.08:18:40.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:40.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:40.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:18:40.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:18:40.39$vc4f8/valo=6,772.99 2006.260.08:18:40.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.08:18:40.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.08:18:40.39#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:40.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:40.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:40.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:40.39#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:18:40.39#ibcon#first serial, iclass 27, count 0 2006.260.08:18:40.39#ibcon#enter sib2, iclass 27, count 0 2006.260.08:18:40.39#ibcon#flushed, iclass 27, count 0 2006.260.08:18:40.39#ibcon#about to write, iclass 27, count 0 2006.260.08:18:40.39#ibcon#wrote, iclass 27, count 0 2006.260.08:18:40.39#ibcon#about to read 3, iclass 27, count 0 2006.260.08:18:40.41#ibcon#read 3, iclass 27, count 0 2006.260.08:18:40.41#ibcon#about to read 4, iclass 27, count 0 2006.260.08:18:40.41#ibcon#read 4, iclass 27, count 0 2006.260.08:18:40.41#ibcon#about to read 5, iclass 27, count 0 2006.260.08:18:40.41#ibcon#read 5, iclass 27, count 0 2006.260.08:18:40.41#ibcon#about to read 6, iclass 27, count 0 2006.260.08:18:40.41#ibcon#read 6, iclass 27, count 0 2006.260.08:18:40.41#ibcon#end of sib2, iclass 27, count 0 2006.260.08:18:40.41#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:18:40.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:18:40.41#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:18:40.41#ibcon#*before write, iclass 27, count 0 2006.260.08:18:40.41#ibcon#enter sib2, iclass 27, count 0 2006.260.08:18:40.41#ibcon#flushed, iclass 27, count 0 2006.260.08:18:40.41#ibcon#about to write, iclass 27, count 0 2006.260.08:18:40.41#ibcon#wrote, iclass 27, count 0 2006.260.08:18:40.41#ibcon#about to read 3, iclass 27, count 0 2006.260.08:18:40.45#ibcon#read 3, iclass 27, count 0 2006.260.08:18:40.45#ibcon#about to read 4, iclass 27, count 0 2006.260.08:18:40.45#ibcon#read 4, iclass 27, count 0 2006.260.08:18:40.45#ibcon#about to read 5, iclass 27, count 0 2006.260.08:18:40.45#ibcon#read 5, iclass 27, count 0 2006.260.08:18:40.45#ibcon#about to read 6, iclass 27, count 0 2006.260.08:18:40.45#ibcon#read 6, iclass 27, count 0 2006.260.08:18:40.45#ibcon#end of sib2, iclass 27, count 0 2006.260.08:18:40.45#ibcon#*after write, iclass 27, count 0 2006.260.08:18:40.45#ibcon#*before return 0, iclass 27, count 0 2006.260.08:18:40.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:40.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:40.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:18:40.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:18:40.45$vc4f8/va=6,6 2006.260.08:18:40.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.260.08:18:40.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.260.08:18:40.45#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:40.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:40.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:40.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:40.51#ibcon#enter wrdev, iclass 29, count 2 2006.260.08:18:40.51#ibcon#first serial, iclass 29, count 2 2006.260.08:18:40.51#ibcon#enter sib2, iclass 29, count 2 2006.260.08:18:40.51#ibcon#flushed, iclass 29, count 2 2006.260.08:18:40.51#ibcon#about to write, iclass 29, count 2 2006.260.08:18:40.51#ibcon#wrote, iclass 29, count 2 2006.260.08:18:40.51#ibcon#about to read 3, iclass 29, count 2 2006.260.08:18:40.53#ibcon#read 3, iclass 29, count 2 2006.260.08:18:40.53#ibcon#about to read 4, iclass 29, count 2 2006.260.08:18:40.53#ibcon#read 4, iclass 29, count 2 2006.260.08:18:40.53#ibcon#about to read 5, iclass 29, count 2 2006.260.08:18:40.53#ibcon#read 5, iclass 29, count 2 2006.260.08:18:40.53#ibcon#about to read 6, iclass 29, count 2 2006.260.08:18:40.53#ibcon#read 6, iclass 29, count 2 2006.260.08:18:40.53#ibcon#end of sib2, iclass 29, count 2 2006.260.08:18:40.53#ibcon#*mode == 0, iclass 29, count 2 2006.260.08:18:40.53#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.260.08:18:40.53#ibcon#[25=AT06-06\r\n] 2006.260.08:18:40.53#ibcon#*before write, iclass 29, count 2 2006.260.08:18:40.53#ibcon#enter sib2, iclass 29, count 2 2006.260.08:18:40.53#ibcon#flushed, iclass 29, count 2 2006.260.08:18:40.53#ibcon#about to write, iclass 29, count 2 2006.260.08:18:40.53#ibcon#wrote, iclass 29, count 2 2006.260.08:18:40.53#ibcon#about to read 3, iclass 29, count 2 2006.260.08:18:40.56#ibcon#read 3, iclass 29, count 2 2006.260.08:18:40.56#ibcon#about to read 4, iclass 29, count 2 2006.260.08:18:40.56#ibcon#read 4, iclass 29, count 2 2006.260.08:18:40.56#ibcon#about to read 5, iclass 29, count 2 2006.260.08:18:40.56#ibcon#read 5, iclass 29, count 2 2006.260.08:18:40.56#ibcon#about to read 6, iclass 29, count 2 2006.260.08:18:40.56#ibcon#read 6, iclass 29, count 2 2006.260.08:18:40.56#ibcon#end of sib2, iclass 29, count 2 2006.260.08:18:40.56#ibcon#*after write, iclass 29, count 2 2006.260.08:18:40.56#ibcon#*before return 0, iclass 29, count 2 2006.260.08:18:40.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:40.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:40.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.260.08:18:40.56#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:40.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:18:40.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:18:40.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:18:40.68#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:18:40.68#ibcon#first serial, iclass 29, count 0 2006.260.08:18:40.68#ibcon#enter sib2, iclass 29, count 0 2006.260.08:18:40.68#ibcon#flushed, iclass 29, count 0 2006.260.08:18:40.68#ibcon#about to write, iclass 29, count 0 2006.260.08:18:40.68#ibcon#wrote, iclass 29, count 0 2006.260.08:18:40.68#ibcon#about to read 3, iclass 29, count 0 2006.260.08:18:40.70#ibcon#read 3, iclass 29, count 0 2006.260.08:18:40.70#ibcon#about to read 4, iclass 29, count 0 2006.260.08:18:40.70#ibcon#read 4, iclass 29, count 0 2006.260.08:18:40.70#ibcon#about to read 5, iclass 29, count 0 2006.260.08:18:40.70#ibcon#read 5, iclass 29, count 0 2006.260.08:18:40.70#ibcon#about to read 6, iclass 29, count 0 2006.260.08:18:40.70#ibcon#read 6, iclass 29, count 0 2006.260.08:18:40.70#ibcon#end of sib2, iclass 29, count 0 2006.260.08:18:40.70#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:18:40.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:18:40.70#ibcon#[25=USB\r\n] 2006.260.08:18:40.70#ibcon#*before write, iclass 29, count 0 2006.260.08:18:40.70#ibcon#enter sib2, iclass 29, count 0 2006.260.08:18:40.70#ibcon#flushed, iclass 29, count 0 2006.260.08:18:40.70#ibcon#about to write, iclass 29, count 0 2006.260.08:18:40.70#ibcon#wrote, iclass 29, count 0 2006.260.08:18:40.70#ibcon#about to read 3, iclass 29, count 0 2006.260.08:18:40.73#ibcon#read 3, iclass 29, count 0 2006.260.08:18:40.73#ibcon#about to read 4, iclass 29, count 0 2006.260.08:18:40.73#ibcon#read 4, iclass 29, count 0 2006.260.08:18:40.73#ibcon#about to read 5, iclass 29, count 0 2006.260.08:18:40.73#ibcon#read 5, iclass 29, count 0 2006.260.08:18:40.73#ibcon#about to read 6, iclass 29, count 0 2006.260.08:18:40.73#ibcon#read 6, iclass 29, count 0 2006.260.08:18:40.73#ibcon#end of sib2, iclass 29, count 0 2006.260.08:18:40.73#ibcon#*after write, iclass 29, count 0 2006.260.08:18:40.73#ibcon#*before return 0, iclass 29, count 0 2006.260.08:18:40.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:18:40.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.260.08:18:40.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:18:40.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:18:40.73$vc4f8/valo=7,832.99 2006.260.08:18:40.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.260.08:18:40.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.260.08:18:40.73#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:40.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:18:40.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:18:40.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:18:40.73#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:18:40.73#ibcon#first serial, iclass 31, count 0 2006.260.08:18:40.73#ibcon#enter sib2, iclass 31, count 0 2006.260.08:18:40.73#ibcon#flushed, iclass 31, count 0 2006.260.08:18:40.73#ibcon#about to write, iclass 31, count 0 2006.260.08:18:40.73#ibcon#wrote, iclass 31, count 0 2006.260.08:18:40.73#ibcon#about to read 3, iclass 31, count 0 2006.260.08:18:40.75#ibcon#read 3, iclass 31, count 0 2006.260.08:18:40.75#ibcon#about to read 4, iclass 31, count 0 2006.260.08:18:40.75#ibcon#read 4, iclass 31, count 0 2006.260.08:18:40.75#ibcon#about to read 5, iclass 31, count 0 2006.260.08:18:40.75#ibcon#read 5, iclass 31, count 0 2006.260.08:18:40.75#ibcon#about to read 6, iclass 31, count 0 2006.260.08:18:40.75#ibcon#read 6, iclass 31, count 0 2006.260.08:18:40.75#ibcon#end of sib2, iclass 31, count 0 2006.260.08:18:40.75#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:18:40.75#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:18:40.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:18:40.75#ibcon#*before write, iclass 31, count 0 2006.260.08:18:40.75#ibcon#enter sib2, iclass 31, count 0 2006.260.08:18:40.75#ibcon#flushed, iclass 31, count 0 2006.260.08:18:40.75#ibcon#about to write, iclass 31, count 0 2006.260.08:18:40.75#ibcon#wrote, iclass 31, count 0 2006.260.08:18:40.75#ibcon#about to read 3, iclass 31, count 0 2006.260.08:18:40.79#ibcon#read 3, iclass 31, count 0 2006.260.08:18:40.79#ibcon#about to read 4, iclass 31, count 0 2006.260.08:18:40.79#ibcon#read 4, iclass 31, count 0 2006.260.08:18:40.79#ibcon#about to read 5, iclass 31, count 0 2006.260.08:18:40.79#ibcon#read 5, iclass 31, count 0 2006.260.08:18:40.79#ibcon#about to read 6, iclass 31, count 0 2006.260.08:18:40.79#ibcon#read 6, iclass 31, count 0 2006.260.08:18:40.79#ibcon#end of sib2, iclass 31, count 0 2006.260.08:18:40.79#ibcon#*after write, iclass 31, count 0 2006.260.08:18:40.79#ibcon#*before return 0, iclass 31, count 0 2006.260.08:18:40.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:18:40.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.260.08:18:40.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:18:40.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:18:40.79$vc4f8/va=7,6 2006.260.08:18:40.79#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.260.08:18:40.79#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.260.08:18:40.79#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:40.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:18:40.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:18:40.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:18:40.85#ibcon#enter wrdev, iclass 33, count 2 2006.260.08:18:40.85#ibcon#first serial, iclass 33, count 2 2006.260.08:18:40.85#ibcon#enter sib2, iclass 33, count 2 2006.260.08:18:40.85#ibcon#flushed, iclass 33, count 2 2006.260.08:18:40.85#ibcon#about to write, iclass 33, count 2 2006.260.08:18:40.85#ibcon#wrote, iclass 33, count 2 2006.260.08:18:40.85#ibcon#about to read 3, iclass 33, count 2 2006.260.08:18:40.87#ibcon#read 3, iclass 33, count 2 2006.260.08:18:40.87#ibcon#about to read 4, iclass 33, count 2 2006.260.08:18:40.87#ibcon#read 4, iclass 33, count 2 2006.260.08:18:40.87#ibcon#about to read 5, iclass 33, count 2 2006.260.08:18:40.87#ibcon#read 5, iclass 33, count 2 2006.260.08:18:40.87#ibcon#about to read 6, iclass 33, count 2 2006.260.08:18:40.87#ibcon#read 6, iclass 33, count 2 2006.260.08:18:40.87#ibcon#end of sib2, iclass 33, count 2 2006.260.08:18:40.87#ibcon#*mode == 0, iclass 33, count 2 2006.260.08:18:40.87#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.260.08:18:40.87#ibcon#[25=AT07-06\r\n] 2006.260.08:18:40.87#ibcon#*before write, iclass 33, count 2 2006.260.08:18:40.87#ibcon#enter sib2, iclass 33, count 2 2006.260.08:18:40.87#ibcon#flushed, iclass 33, count 2 2006.260.08:18:40.87#ibcon#about to write, iclass 33, count 2 2006.260.08:18:40.87#ibcon#wrote, iclass 33, count 2 2006.260.08:18:40.87#ibcon#about to read 3, iclass 33, count 2 2006.260.08:18:40.90#ibcon#read 3, iclass 33, count 2 2006.260.08:18:40.90#ibcon#about to read 4, iclass 33, count 2 2006.260.08:18:40.90#ibcon#read 4, iclass 33, count 2 2006.260.08:18:40.90#ibcon#about to read 5, iclass 33, count 2 2006.260.08:18:40.90#ibcon#read 5, iclass 33, count 2 2006.260.08:18:40.90#ibcon#about to read 6, iclass 33, count 2 2006.260.08:18:40.90#ibcon#read 6, iclass 33, count 2 2006.260.08:18:40.90#ibcon#end of sib2, iclass 33, count 2 2006.260.08:18:40.90#ibcon#*after write, iclass 33, count 2 2006.260.08:18:40.90#ibcon#*before return 0, iclass 33, count 2 2006.260.08:18:40.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:18:40.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.260.08:18:40.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.260.08:18:40.90#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:40.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:18:41.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:18:41.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:18:41.02#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:18:41.02#ibcon#first serial, iclass 33, count 0 2006.260.08:18:41.02#ibcon#enter sib2, iclass 33, count 0 2006.260.08:18:41.02#ibcon#flushed, iclass 33, count 0 2006.260.08:18:41.02#ibcon#about to write, iclass 33, count 0 2006.260.08:18:41.02#ibcon#wrote, iclass 33, count 0 2006.260.08:18:41.02#ibcon#about to read 3, iclass 33, count 0 2006.260.08:18:41.04#ibcon#read 3, iclass 33, count 0 2006.260.08:18:41.04#ibcon#about to read 4, iclass 33, count 0 2006.260.08:18:41.04#ibcon#read 4, iclass 33, count 0 2006.260.08:18:41.04#ibcon#about to read 5, iclass 33, count 0 2006.260.08:18:41.04#ibcon#read 5, iclass 33, count 0 2006.260.08:18:41.04#ibcon#about to read 6, iclass 33, count 0 2006.260.08:18:41.04#ibcon#read 6, iclass 33, count 0 2006.260.08:18:41.04#ibcon#end of sib2, iclass 33, count 0 2006.260.08:18:41.04#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:18:41.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:18:41.04#ibcon#[25=USB\r\n] 2006.260.08:18:41.04#ibcon#*before write, iclass 33, count 0 2006.260.08:18:41.04#ibcon#enter sib2, iclass 33, count 0 2006.260.08:18:41.04#ibcon#flushed, iclass 33, count 0 2006.260.08:18:41.04#ibcon#about to write, iclass 33, count 0 2006.260.08:18:41.04#ibcon#wrote, iclass 33, count 0 2006.260.08:18:41.04#ibcon#about to read 3, iclass 33, count 0 2006.260.08:18:41.07#ibcon#read 3, iclass 33, count 0 2006.260.08:18:41.07#ibcon#about to read 4, iclass 33, count 0 2006.260.08:18:41.07#ibcon#read 4, iclass 33, count 0 2006.260.08:18:41.07#ibcon#about to read 5, iclass 33, count 0 2006.260.08:18:41.07#ibcon#read 5, iclass 33, count 0 2006.260.08:18:41.07#ibcon#about to read 6, iclass 33, count 0 2006.260.08:18:41.07#ibcon#read 6, iclass 33, count 0 2006.260.08:18:41.07#ibcon#end of sib2, iclass 33, count 0 2006.260.08:18:41.07#ibcon#*after write, iclass 33, count 0 2006.260.08:18:41.07#ibcon#*before return 0, iclass 33, count 0 2006.260.08:18:41.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:18:41.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.260.08:18:41.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:18:41.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:18:41.07$vc4f8/valo=8,852.99 2006.260.08:18:41.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.260.08:18:41.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.260.08:18:41.07#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:41.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:18:41.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:18:41.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:18:41.07#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:18:41.07#ibcon#first serial, iclass 35, count 0 2006.260.08:18:41.07#ibcon#enter sib2, iclass 35, count 0 2006.260.08:18:41.07#ibcon#flushed, iclass 35, count 0 2006.260.08:18:41.07#ibcon#about to write, iclass 35, count 0 2006.260.08:18:41.07#ibcon#wrote, iclass 35, count 0 2006.260.08:18:41.07#ibcon#about to read 3, iclass 35, count 0 2006.260.08:18:41.09#ibcon#read 3, iclass 35, count 0 2006.260.08:18:41.09#ibcon#about to read 4, iclass 35, count 0 2006.260.08:18:41.09#ibcon#read 4, iclass 35, count 0 2006.260.08:18:41.09#ibcon#about to read 5, iclass 35, count 0 2006.260.08:18:41.09#ibcon#read 5, iclass 35, count 0 2006.260.08:18:41.09#ibcon#about to read 6, iclass 35, count 0 2006.260.08:18:41.09#ibcon#read 6, iclass 35, count 0 2006.260.08:18:41.09#ibcon#end of sib2, iclass 35, count 0 2006.260.08:18:41.09#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:18:41.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:18:41.09#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:18:41.09#ibcon#*before write, iclass 35, count 0 2006.260.08:18:41.09#ibcon#enter sib2, iclass 35, count 0 2006.260.08:18:41.09#ibcon#flushed, iclass 35, count 0 2006.260.08:18:41.09#ibcon#about to write, iclass 35, count 0 2006.260.08:18:41.09#ibcon#wrote, iclass 35, count 0 2006.260.08:18:41.09#ibcon#about to read 3, iclass 35, count 0 2006.260.08:18:41.13#ibcon#read 3, iclass 35, count 0 2006.260.08:18:41.13#ibcon#about to read 4, iclass 35, count 0 2006.260.08:18:41.13#ibcon#read 4, iclass 35, count 0 2006.260.08:18:41.13#ibcon#about to read 5, iclass 35, count 0 2006.260.08:18:41.13#ibcon#read 5, iclass 35, count 0 2006.260.08:18:41.13#ibcon#about to read 6, iclass 35, count 0 2006.260.08:18:41.13#ibcon#read 6, iclass 35, count 0 2006.260.08:18:41.13#ibcon#end of sib2, iclass 35, count 0 2006.260.08:18:41.13#ibcon#*after write, iclass 35, count 0 2006.260.08:18:41.13#ibcon#*before return 0, iclass 35, count 0 2006.260.08:18:41.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:18:41.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.260.08:18:41.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:18:41.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:18:41.13$vc4f8/va=8,6 2006.260.08:18:41.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.260.08:18:41.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.260.08:18:41.13#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:41.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:18:41.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:18:41.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:18:41.19#ibcon#enter wrdev, iclass 37, count 2 2006.260.08:18:41.19#ibcon#first serial, iclass 37, count 2 2006.260.08:18:41.19#ibcon#enter sib2, iclass 37, count 2 2006.260.08:18:41.19#ibcon#flushed, iclass 37, count 2 2006.260.08:18:41.19#ibcon#about to write, iclass 37, count 2 2006.260.08:18:41.19#ibcon#wrote, iclass 37, count 2 2006.260.08:18:41.19#ibcon#about to read 3, iclass 37, count 2 2006.260.08:18:41.21#ibcon#read 3, iclass 37, count 2 2006.260.08:18:41.21#ibcon#about to read 4, iclass 37, count 2 2006.260.08:18:41.21#ibcon#read 4, iclass 37, count 2 2006.260.08:18:41.21#ibcon#about to read 5, iclass 37, count 2 2006.260.08:18:41.21#ibcon#read 5, iclass 37, count 2 2006.260.08:18:41.21#ibcon#about to read 6, iclass 37, count 2 2006.260.08:18:41.21#ibcon#read 6, iclass 37, count 2 2006.260.08:18:41.21#ibcon#end of sib2, iclass 37, count 2 2006.260.08:18:41.21#ibcon#*mode == 0, iclass 37, count 2 2006.260.08:18:41.21#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.260.08:18:41.21#ibcon#[25=AT08-06\r\n] 2006.260.08:18:41.21#ibcon#*before write, iclass 37, count 2 2006.260.08:18:41.21#ibcon#enter sib2, iclass 37, count 2 2006.260.08:18:41.21#ibcon#flushed, iclass 37, count 2 2006.260.08:18:41.21#ibcon#about to write, iclass 37, count 2 2006.260.08:18:41.21#ibcon#wrote, iclass 37, count 2 2006.260.08:18:41.21#ibcon#about to read 3, iclass 37, count 2 2006.260.08:18:41.24#ibcon#read 3, iclass 37, count 2 2006.260.08:18:41.24#ibcon#about to read 4, iclass 37, count 2 2006.260.08:18:41.24#ibcon#read 4, iclass 37, count 2 2006.260.08:18:41.24#ibcon#about to read 5, iclass 37, count 2 2006.260.08:18:41.24#ibcon#read 5, iclass 37, count 2 2006.260.08:18:41.24#ibcon#about to read 6, iclass 37, count 2 2006.260.08:18:41.24#ibcon#read 6, iclass 37, count 2 2006.260.08:18:41.24#ibcon#end of sib2, iclass 37, count 2 2006.260.08:18:41.24#ibcon#*after write, iclass 37, count 2 2006.260.08:18:41.24#ibcon#*before return 0, iclass 37, count 2 2006.260.08:18:41.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:18:41.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.260.08:18:41.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.260.08:18:41.24#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:41.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:18:41.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:18:41.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:18:41.36#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:18:41.36#ibcon#first serial, iclass 37, count 0 2006.260.08:18:41.36#ibcon#enter sib2, iclass 37, count 0 2006.260.08:18:41.36#ibcon#flushed, iclass 37, count 0 2006.260.08:18:41.36#ibcon#about to write, iclass 37, count 0 2006.260.08:18:41.36#ibcon#wrote, iclass 37, count 0 2006.260.08:18:41.36#ibcon#about to read 3, iclass 37, count 0 2006.260.08:18:41.38#ibcon#read 3, iclass 37, count 0 2006.260.08:18:41.38#ibcon#about to read 4, iclass 37, count 0 2006.260.08:18:41.38#ibcon#read 4, iclass 37, count 0 2006.260.08:18:41.38#ibcon#about to read 5, iclass 37, count 0 2006.260.08:18:41.38#ibcon#read 5, iclass 37, count 0 2006.260.08:18:41.38#ibcon#about to read 6, iclass 37, count 0 2006.260.08:18:41.38#ibcon#read 6, iclass 37, count 0 2006.260.08:18:41.38#ibcon#end of sib2, iclass 37, count 0 2006.260.08:18:41.38#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:18:41.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:18:41.38#ibcon#[25=USB\r\n] 2006.260.08:18:41.38#ibcon#*before write, iclass 37, count 0 2006.260.08:18:41.38#ibcon#enter sib2, iclass 37, count 0 2006.260.08:18:41.38#ibcon#flushed, iclass 37, count 0 2006.260.08:18:41.38#ibcon#about to write, iclass 37, count 0 2006.260.08:18:41.38#ibcon#wrote, iclass 37, count 0 2006.260.08:18:41.38#ibcon#about to read 3, iclass 37, count 0 2006.260.08:18:41.41#ibcon#read 3, iclass 37, count 0 2006.260.08:18:41.41#ibcon#about to read 4, iclass 37, count 0 2006.260.08:18:41.41#ibcon#read 4, iclass 37, count 0 2006.260.08:18:41.41#ibcon#about to read 5, iclass 37, count 0 2006.260.08:18:41.41#ibcon#read 5, iclass 37, count 0 2006.260.08:18:41.41#ibcon#about to read 6, iclass 37, count 0 2006.260.08:18:41.41#ibcon#read 6, iclass 37, count 0 2006.260.08:18:41.41#ibcon#end of sib2, iclass 37, count 0 2006.260.08:18:41.41#ibcon#*after write, iclass 37, count 0 2006.260.08:18:41.41#ibcon#*before return 0, iclass 37, count 0 2006.260.08:18:41.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:18:41.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.260.08:18:41.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:18:41.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:18:41.41$vc4f8/vblo=1,632.99 2006.260.08:18:41.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.260.08:18:41.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.260.08:18:41.41#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:41.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:18:41.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:18:41.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:18:41.41#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:18:41.41#ibcon#first serial, iclass 39, count 0 2006.260.08:18:41.41#ibcon#enter sib2, iclass 39, count 0 2006.260.08:18:41.41#ibcon#flushed, iclass 39, count 0 2006.260.08:18:41.41#ibcon#about to write, iclass 39, count 0 2006.260.08:18:41.41#ibcon#wrote, iclass 39, count 0 2006.260.08:18:41.41#ibcon#about to read 3, iclass 39, count 0 2006.260.08:18:41.43#ibcon#read 3, iclass 39, count 0 2006.260.08:18:41.43#ibcon#about to read 4, iclass 39, count 0 2006.260.08:18:41.43#ibcon#read 4, iclass 39, count 0 2006.260.08:18:41.43#ibcon#about to read 5, iclass 39, count 0 2006.260.08:18:41.43#ibcon#read 5, iclass 39, count 0 2006.260.08:18:41.43#ibcon#about to read 6, iclass 39, count 0 2006.260.08:18:41.43#ibcon#read 6, iclass 39, count 0 2006.260.08:18:41.43#ibcon#end of sib2, iclass 39, count 0 2006.260.08:18:41.43#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:18:41.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:18:41.43#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:18:41.43#ibcon#*before write, iclass 39, count 0 2006.260.08:18:41.43#ibcon#enter sib2, iclass 39, count 0 2006.260.08:18:41.43#ibcon#flushed, iclass 39, count 0 2006.260.08:18:41.43#ibcon#about to write, iclass 39, count 0 2006.260.08:18:41.43#ibcon#wrote, iclass 39, count 0 2006.260.08:18:41.43#ibcon#about to read 3, iclass 39, count 0 2006.260.08:18:41.47#ibcon#read 3, iclass 39, count 0 2006.260.08:18:41.47#ibcon#about to read 4, iclass 39, count 0 2006.260.08:18:41.47#ibcon#read 4, iclass 39, count 0 2006.260.08:18:41.47#ibcon#about to read 5, iclass 39, count 0 2006.260.08:18:41.47#ibcon#read 5, iclass 39, count 0 2006.260.08:18:41.47#ibcon#about to read 6, iclass 39, count 0 2006.260.08:18:41.47#ibcon#read 6, iclass 39, count 0 2006.260.08:18:41.47#ibcon#end of sib2, iclass 39, count 0 2006.260.08:18:41.47#ibcon#*after write, iclass 39, count 0 2006.260.08:18:41.47#ibcon#*before return 0, iclass 39, count 0 2006.260.08:18:41.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:18:41.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.260.08:18:41.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:18:41.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:18:41.47$vc4f8/vb=1,4 2006.260.08:18:41.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.260.08:18:41.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.260.08:18:41.47#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:41.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:18:41.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:18:41.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:18:41.47#ibcon#enter wrdev, iclass 3, count 2 2006.260.08:18:41.47#ibcon#first serial, iclass 3, count 2 2006.260.08:18:41.47#ibcon#enter sib2, iclass 3, count 2 2006.260.08:18:41.47#ibcon#flushed, iclass 3, count 2 2006.260.08:18:41.47#ibcon#about to write, iclass 3, count 2 2006.260.08:18:41.47#ibcon#wrote, iclass 3, count 2 2006.260.08:18:41.47#ibcon#about to read 3, iclass 3, count 2 2006.260.08:18:41.49#ibcon#read 3, iclass 3, count 2 2006.260.08:18:41.49#ibcon#about to read 4, iclass 3, count 2 2006.260.08:18:41.49#ibcon#read 4, iclass 3, count 2 2006.260.08:18:41.49#ibcon#about to read 5, iclass 3, count 2 2006.260.08:18:41.49#ibcon#read 5, iclass 3, count 2 2006.260.08:18:41.49#ibcon#about to read 6, iclass 3, count 2 2006.260.08:18:41.49#ibcon#read 6, iclass 3, count 2 2006.260.08:18:41.49#ibcon#end of sib2, iclass 3, count 2 2006.260.08:18:41.49#ibcon#*mode == 0, iclass 3, count 2 2006.260.08:18:41.49#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.260.08:18:41.49#ibcon#[27=AT01-04\r\n] 2006.260.08:18:41.49#ibcon#*before write, iclass 3, count 2 2006.260.08:18:41.49#ibcon#enter sib2, iclass 3, count 2 2006.260.08:18:41.49#ibcon#flushed, iclass 3, count 2 2006.260.08:18:41.49#ibcon#about to write, iclass 3, count 2 2006.260.08:18:41.49#ibcon#wrote, iclass 3, count 2 2006.260.08:18:41.49#ibcon#about to read 3, iclass 3, count 2 2006.260.08:18:41.52#ibcon#read 3, iclass 3, count 2 2006.260.08:18:41.52#ibcon#about to read 4, iclass 3, count 2 2006.260.08:18:41.52#ibcon#read 4, iclass 3, count 2 2006.260.08:18:41.52#ibcon#about to read 5, iclass 3, count 2 2006.260.08:18:41.52#ibcon#read 5, iclass 3, count 2 2006.260.08:18:41.52#ibcon#about to read 6, iclass 3, count 2 2006.260.08:18:41.52#ibcon#read 6, iclass 3, count 2 2006.260.08:18:41.52#ibcon#end of sib2, iclass 3, count 2 2006.260.08:18:41.52#ibcon#*after write, iclass 3, count 2 2006.260.08:18:41.52#ibcon#*before return 0, iclass 3, count 2 2006.260.08:18:41.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:18:41.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.260.08:18:41.52#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.260.08:18:41.52#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:41.52#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:18:41.64#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:18:41.64#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:18:41.64#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:18:41.64#ibcon#first serial, iclass 3, count 0 2006.260.08:18:41.64#ibcon#enter sib2, iclass 3, count 0 2006.260.08:18:41.64#ibcon#flushed, iclass 3, count 0 2006.260.08:18:41.64#ibcon#about to write, iclass 3, count 0 2006.260.08:18:41.64#ibcon#wrote, iclass 3, count 0 2006.260.08:18:41.64#ibcon#about to read 3, iclass 3, count 0 2006.260.08:18:41.66#ibcon#read 3, iclass 3, count 0 2006.260.08:18:41.66#ibcon#about to read 4, iclass 3, count 0 2006.260.08:18:41.66#ibcon#read 4, iclass 3, count 0 2006.260.08:18:41.66#ibcon#about to read 5, iclass 3, count 0 2006.260.08:18:41.66#ibcon#read 5, iclass 3, count 0 2006.260.08:18:41.66#ibcon#about to read 6, iclass 3, count 0 2006.260.08:18:41.66#ibcon#read 6, iclass 3, count 0 2006.260.08:18:41.66#ibcon#end of sib2, iclass 3, count 0 2006.260.08:18:41.66#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:18:41.66#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:18:41.66#ibcon#[27=USB\r\n] 2006.260.08:18:41.66#ibcon#*before write, iclass 3, count 0 2006.260.08:18:41.66#ibcon#enter sib2, iclass 3, count 0 2006.260.08:18:41.66#ibcon#flushed, iclass 3, count 0 2006.260.08:18:41.66#ibcon#about to write, iclass 3, count 0 2006.260.08:18:41.66#ibcon#wrote, iclass 3, count 0 2006.260.08:18:41.66#ibcon#about to read 3, iclass 3, count 0 2006.260.08:18:41.69#ibcon#read 3, iclass 3, count 0 2006.260.08:18:41.69#ibcon#about to read 4, iclass 3, count 0 2006.260.08:18:41.69#ibcon#read 4, iclass 3, count 0 2006.260.08:18:41.69#ibcon#about to read 5, iclass 3, count 0 2006.260.08:18:41.69#ibcon#read 5, iclass 3, count 0 2006.260.08:18:41.69#ibcon#about to read 6, iclass 3, count 0 2006.260.08:18:41.69#ibcon#read 6, iclass 3, count 0 2006.260.08:18:41.69#ibcon#end of sib2, iclass 3, count 0 2006.260.08:18:41.69#ibcon#*after write, iclass 3, count 0 2006.260.08:18:41.69#ibcon#*before return 0, iclass 3, count 0 2006.260.08:18:41.69#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:18:41.69#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.260.08:18:41.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:18:41.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:18:41.69$vc4f8/vblo=2,640.99 2006.260.08:18:41.69#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.260.08:18:41.69#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.260.08:18:41.69#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:41.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:41.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:41.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:41.69#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:18:41.69#ibcon#first serial, iclass 5, count 0 2006.260.08:18:41.69#ibcon#enter sib2, iclass 5, count 0 2006.260.08:18:41.69#ibcon#flushed, iclass 5, count 0 2006.260.08:18:41.69#ibcon#about to write, iclass 5, count 0 2006.260.08:18:41.69#ibcon#wrote, iclass 5, count 0 2006.260.08:18:41.69#ibcon#about to read 3, iclass 5, count 0 2006.260.08:18:41.71#ibcon#read 3, iclass 5, count 0 2006.260.08:18:41.71#ibcon#about to read 4, iclass 5, count 0 2006.260.08:18:41.71#ibcon#read 4, iclass 5, count 0 2006.260.08:18:41.71#ibcon#about to read 5, iclass 5, count 0 2006.260.08:18:41.71#ibcon#read 5, iclass 5, count 0 2006.260.08:18:41.71#ibcon#about to read 6, iclass 5, count 0 2006.260.08:18:41.71#ibcon#read 6, iclass 5, count 0 2006.260.08:18:41.71#ibcon#end of sib2, iclass 5, count 0 2006.260.08:18:41.71#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:18:41.71#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:18:41.71#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:18:41.71#ibcon#*before write, iclass 5, count 0 2006.260.08:18:41.71#ibcon#enter sib2, iclass 5, count 0 2006.260.08:18:41.71#ibcon#flushed, iclass 5, count 0 2006.260.08:18:41.71#ibcon#about to write, iclass 5, count 0 2006.260.08:18:41.71#ibcon#wrote, iclass 5, count 0 2006.260.08:18:41.71#ibcon#about to read 3, iclass 5, count 0 2006.260.08:18:41.75#ibcon#read 3, iclass 5, count 0 2006.260.08:18:41.75#ibcon#about to read 4, iclass 5, count 0 2006.260.08:18:41.75#ibcon#read 4, iclass 5, count 0 2006.260.08:18:41.75#ibcon#about to read 5, iclass 5, count 0 2006.260.08:18:41.75#ibcon#read 5, iclass 5, count 0 2006.260.08:18:41.75#ibcon#about to read 6, iclass 5, count 0 2006.260.08:18:41.75#ibcon#read 6, iclass 5, count 0 2006.260.08:18:41.75#ibcon#end of sib2, iclass 5, count 0 2006.260.08:18:41.75#ibcon#*after write, iclass 5, count 0 2006.260.08:18:41.75#ibcon#*before return 0, iclass 5, count 0 2006.260.08:18:41.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:41.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.260.08:18:41.75#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:18:41.75#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:18:41.75$vc4f8/vb=2,5 2006.260.08:18:41.75#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.260.08:18:41.75#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.260.08:18:41.75#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:41.75#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:41.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:41.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:41.81#ibcon#enter wrdev, iclass 7, count 2 2006.260.08:18:41.81#ibcon#first serial, iclass 7, count 2 2006.260.08:18:41.81#ibcon#enter sib2, iclass 7, count 2 2006.260.08:18:41.81#ibcon#flushed, iclass 7, count 2 2006.260.08:18:41.81#ibcon#about to write, iclass 7, count 2 2006.260.08:18:41.81#ibcon#wrote, iclass 7, count 2 2006.260.08:18:41.81#ibcon#about to read 3, iclass 7, count 2 2006.260.08:18:41.83#ibcon#read 3, iclass 7, count 2 2006.260.08:18:41.83#ibcon#about to read 4, iclass 7, count 2 2006.260.08:18:41.83#ibcon#read 4, iclass 7, count 2 2006.260.08:18:41.83#ibcon#about to read 5, iclass 7, count 2 2006.260.08:18:41.83#ibcon#read 5, iclass 7, count 2 2006.260.08:18:41.83#ibcon#about to read 6, iclass 7, count 2 2006.260.08:18:41.83#ibcon#read 6, iclass 7, count 2 2006.260.08:18:41.83#ibcon#end of sib2, iclass 7, count 2 2006.260.08:18:41.83#ibcon#*mode == 0, iclass 7, count 2 2006.260.08:18:41.83#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.260.08:18:41.83#ibcon#[27=AT02-05\r\n] 2006.260.08:18:41.83#ibcon#*before write, iclass 7, count 2 2006.260.08:18:41.83#ibcon#enter sib2, iclass 7, count 2 2006.260.08:18:41.83#ibcon#flushed, iclass 7, count 2 2006.260.08:18:41.83#ibcon#about to write, iclass 7, count 2 2006.260.08:18:41.83#ibcon#wrote, iclass 7, count 2 2006.260.08:18:41.83#ibcon#about to read 3, iclass 7, count 2 2006.260.08:18:41.86#ibcon#read 3, iclass 7, count 2 2006.260.08:18:41.86#ibcon#about to read 4, iclass 7, count 2 2006.260.08:18:41.86#ibcon#read 4, iclass 7, count 2 2006.260.08:18:41.86#ibcon#about to read 5, iclass 7, count 2 2006.260.08:18:41.86#ibcon#read 5, iclass 7, count 2 2006.260.08:18:41.86#ibcon#about to read 6, iclass 7, count 2 2006.260.08:18:41.86#ibcon#read 6, iclass 7, count 2 2006.260.08:18:41.86#ibcon#end of sib2, iclass 7, count 2 2006.260.08:18:41.86#ibcon#*after write, iclass 7, count 2 2006.260.08:18:41.86#ibcon#*before return 0, iclass 7, count 2 2006.260.08:18:41.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:41.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.260.08:18:41.86#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.260.08:18:41.86#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:41.86#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:41.98#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:41.98#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:41.98#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:18:41.98#ibcon#first serial, iclass 7, count 0 2006.260.08:18:41.98#ibcon#enter sib2, iclass 7, count 0 2006.260.08:18:41.98#ibcon#flushed, iclass 7, count 0 2006.260.08:18:41.98#ibcon#about to write, iclass 7, count 0 2006.260.08:18:41.98#ibcon#wrote, iclass 7, count 0 2006.260.08:18:41.98#ibcon#about to read 3, iclass 7, count 0 2006.260.08:18:42.00#ibcon#read 3, iclass 7, count 0 2006.260.08:18:42.00#ibcon#about to read 4, iclass 7, count 0 2006.260.08:18:42.00#ibcon#read 4, iclass 7, count 0 2006.260.08:18:42.00#ibcon#about to read 5, iclass 7, count 0 2006.260.08:18:42.00#ibcon#read 5, iclass 7, count 0 2006.260.08:18:42.00#ibcon#about to read 6, iclass 7, count 0 2006.260.08:18:42.00#ibcon#read 6, iclass 7, count 0 2006.260.08:18:42.00#ibcon#end of sib2, iclass 7, count 0 2006.260.08:18:42.00#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:18:42.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:18:42.00#ibcon#[27=USB\r\n] 2006.260.08:18:42.00#ibcon#*before write, iclass 7, count 0 2006.260.08:18:42.00#ibcon#enter sib2, iclass 7, count 0 2006.260.08:18:42.00#ibcon#flushed, iclass 7, count 0 2006.260.08:18:42.00#ibcon#about to write, iclass 7, count 0 2006.260.08:18:42.00#ibcon#wrote, iclass 7, count 0 2006.260.08:18:42.00#ibcon#about to read 3, iclass 7, count 0 2006.260.08:18:42.03#ibcon#read 3, iclass 7, count 0 2006.260.08:18:42.03#ibcon#about to read 4, iclass 7, count 0 2006.260.08:18:42.03#ibcon#read 4, iclass 7, count 0 2006.260.08:18:42.03#ibcon#about to read 5, iclass 7, count 0 2006.260.08:18:42.03#ibcon#read 5, iclass 7, count 0 2006.260.08:18:42.03#ibcon#about to read 6, iclass 7, count 0 2006.260.08:18:42.03#ibcon#read 6, iclass 7, count 0 2006.260.08:18:42.03#ibcon#end of sib2, iclass 7, count 0 2006.260.08:18:42.03#ibcon#*after write, iclass 7, count 0 2006.260.08:18:42.03#ibcon#*before return 0, iclass 7, count 0 2006.260.08:18:42.03#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:42.03#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.260.08:18:42.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:18:42.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:18:42.03$vc4f8/vblo=3,656.99 2006.260.08:18:42.03#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.260.08:18:42.03#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.260.08:18:42.03#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:42.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:42.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:42.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:42.03#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:18:42.03#ibcon#first serial, iclass 11, count 0 2006.260.08:18:42.03#ibcon#enter sib2, iclass 11, count 0 2006.260.08:18:42.03#ibcon#flushed, iclass 11, count 0 2006.260.08:18:42.03#ibcon#about to write, iclass 11, count 0 2006.260.08:18:42.03#ibcon#wrote, iclass 11, count 0 2006.260.08:18:42.03#ibcon#about to read 3, iclass 11, count 0 2006.260.08:18:42.05#ibcon#read 3, iclass 11, count 0 2006.260.08:18:42.05#ibcon#about to read 4, iclass 11, count 0 2006.260.08:18:42.05#ibcon#read 4, iclass 11, count 0 2006.260.08:18:42.05#ibcon#about to read 5, iclass 11, count 0 2006.260.08:18:42.05#ibcon#read 5, iclass 11, count 0 2006.260.08:18:42.05#ibcon#about to read 6, iclass 11, count 0 2006.260.08:18:42.05#ibcon#read 6, iclass 11, count 0 2006.260.08:18:42.05#ibcon#end of sib2, iclass 11, count 0 2006.260.08:18:42.05#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:18:42.05#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:18:42.05#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:18:42.05#ibcon#*before write, iclass 11, count 0 2006.260.08:18:42.05#ibcon#enter sib2, iclass 11, count 0 2006.260.08:18:42.05#ibcon#flushed, iclass 11, count 0 2006.260.08:18:42.05#ibcon#about to write, iclass 11, count 0 2006.260.08:18:42.05#ibcon#wrote, iclass 11, count 0 2006.260.08:18:42.05#ibcon#about to read 3, iclass 11, count 0 2006.260.08:18:42.09#ibcon#read 3, iclass 11, count 0 2006.260.08:18:42.09#ibcon#about to read 4, iclass 11, count 0 2006.260.08:18:42.09#ibcon#read 4, iclass 11, count 0 2006.260.08:18:42.09#ibcon#about to read 5, iclass 11, count 0 2006.260.08:18:42.09#ibcon#read 5, iclass 11, count 0 2006.260.08:18:42.09#ibcon#about to read 6, iclass 11, count 0 2006.260.08:18:42.09#ibcon#read 6, iclass 11, count 0 2006.260.08:18:42.09#ibcon#end of sib2, iclass 11, count 0 2006.260.08:18:42.09#ibcon#*after write, iclass 11, count 0 2006.260.08:18:42.09#ibcon#*before return 0, iclass 11, count 0 2006.260.08:18:42.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:42.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.260.08:18:42.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:18:42.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:18:42.09$vc4f8/vb=3,4 2006.260.08:18:42.09#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.260.08:18:42.09#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.260.08:18:42.09#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:42.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:42.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:42.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:42.15#ibcon#enter wrdev, iclass 13, count 2 2006.260.08:18:42.15#ibcon#first serial, iclass 13, count 2 2006.260.08:18:42.15#ibcon#enter sib2, iclass 13, count 2 2006.260.08:18:42.15#ibcon#flushed, iclass 13, count 2 2006.260.08:18:42.15#ibcon#about to write, iclass 13, count 2 2006.260.08:18:42.15#ibcon#wrote, iclass 13, count 2 2006.260.08:18:42.15#ibcon#about to read 3, iclass 13, count 2 2006.260.08:18:42.17#ibcon#read 3, iclass 13, count 2 2006.260.08:18:42.17#ibcon#about to read 4, iclass 13, count 2 2006.260.08:18:42.17#ibcon#read 4, iclass 13, count 2 2006.260.08:18:42.17#ibcon#about to read 5, iclass 13, count 2 2006.260.08:18:42.17#ibcon#read 5, iclass 13, count 2 2006.260.08:18:42.17#ibcon#about to read 6, iclass 13, count 2 2006.260.08:18:42.17#ibcon#read 6, iclass 13, count 2 2006.260.08:18:42.17#ibcon#end of sib2, iclass 13, count 2 2006.260.08:18:42.17#ibcon#*mode == 0, iclass 13, count 2 2006.260.08:18:42.17#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.260.08:18:42.17#ibcon#[27=AT03-04\r\n] 2006.260.08:18:42.17#ibcon#*before write, iclass 13, count 2 2006.260.08:18:42.17#ibcon#enter sib2, iclass 13, count 2 2006.260.08:18:42.17#ibcon#flushed, iclass 13, count 2 2006.260.08:18:42.17#ibcon#about to write, iclass 13, count 2 2006.260.08:18:42.17#ibcon#wrote, iclass 13, count 2 2006.260.08:18:42.17#ibcon#about to read 3, iclass 13, count 2 2006.260.08:18:42.20#ibcon#read 3, iclass 13, count 2 2006.260.08:18:42.20#ibcon#about to read 4, iclass 13, count 2 2006.260.08:18:42.20#ibcon#read 4, iclass 13, count 2 2006.260.08:18:42.20#ibcon#about to read 5, iclass 13, count 2 2006.260.08:18:42.20#ibcon#read 5, iclass 13, count 2 2006.260.08:18:42.20#ibcon#about to read 6, iclass 13, count 2 2006.260.08:18:42.20#ibcon#read 6, iclass 13, count 2 2006.260.08:18:42.20#ibcon#end of sib2, iclass 13, count 2 2006.260.08:18:42.20#ibcon#*after write, iclass 13, count 2 2006.260.08:18:42.20#ibcon#*before return 0, iclass 13, count 2 2006.260.08:18:42.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:42.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.260.08:18:42.20#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.260.08:18:42.20#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:42.20#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:42.32#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:42.32#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:42.32#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:18:42.32#ibcon#first serial, iclass 13, count 0 2006.260.08:18:42.32#ibcon#enter sib2, iclass 13, count 0 2006.260.08:18:42.32#ibcon#flushed, iclass 13, count 0 2006.260.08:18:42.32#ibcon#about to write, iclass 13, count 0 2006.260.08:18:42.32#ibcon#wrote, iclass 13, count 0 2006.260.08:18:42.32#ibcon#about to read 3, iclass 13, count 0 2006.260.08:18:42.34#ibcon#read 3, iclass 13, count 0 2006.260.08:18:42.34#ibcon#about to read 4, iclass 13, count 0 2006.260.08:18:42.34#ibcon#read 4, iclass 13, count 0 2006.260.08:18:42.34#ibcon#about to read 5, iclass 13, count 0 2006.260.08:18:42.34#ibcon#read 5, iclass 13, count 0 2006.260.08:18:42.34#ibcon#about to read 6, iclass 13, count 0 2006.260.08:18:42.34#ibcon#read 6, iclass 13, count 0 2006.260.08:18:42.34#ibcon#end of sib2, iclass 13, count 0 2006.260.08:18:42.34#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:18:42.34#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:18:42.34#ibcon#[27=USB\r\n] 2006.260.08:18:42.34#ibcon#*before write, iclass 13, count 0 2006.260.08:18:42.34#ibcon#enter sib2, iclass 13, count 0 2006.260.08:18:42.34#ibcon#flushed, iclass 13, count 0 2006.260.08:18:42.34#ibcon#about to write, iclass 13, count 0 2006.260.08:18:42.34#ibcon#wrote, iclass 13, count 0 2006.260.08:18:42.34#ibcon#about to read 3, iclass 13, count 0 2006.260.08:18:42.37#ibcon#read 3, iclass 13, count 0 2006.260.08:18:42.37#ibcon#about to read 4, iclass 13, count 0 2006.260.08:18:42.37#ibcon#read 4, iclass 13, count 0 2006.260.08:18:42.37#ibcon#about to read 5, iclass 13, count 0 2006.260.08:18:42.37#ibcon#read 5, iclass 13, count 0 2006.260.08:18:42.37#ibcon#about to read 6, iclass 13, count 0 2006.260.08:18:42.37#ibcon#read 6, iclass 13, count 0 2006.260.08:18:42.37#ibcon#end of sib2, iclass 13, count 0 2006.260.08:18:42.37#ibcon#*after write, iclass 13, count 0 2006.260.08:18:42.37#ibcon#*before return 0, iclass 13, count 0 2006.260.08:18:42.37#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:42.37#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.260.08:18:42.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:18:42.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:18:42.37$vc4f8/vblo=4,712.99 2006.260.08:18:42.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:18:42.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:18:42.37#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:42.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:42.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:42.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:42.37#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:18:42.37#ibcon#first serial, iclass 15, count 0 2006.260.08:18:42.37#ibcon#enter sib2, iclass 15, count 0 2006.260.08:18:42.37#ibcon#flushed, iclass 15, count 0 2006.260.08:18:42.37#ibcon#about to write, iclass 15, count 0 2006.260.08:18:42.37#ibcon#wrote, iclass 15, count 0 2006.260.08:18:42.37#ibcon#about to read 3, iclass 15, count 0 2006.260.08:18:42.39#ibcon#read 3, iclass 15, count 0 2006.260.08:18:42.39#ibcon#about to read 4, iclass 15, count 0 2006.260.08:18:42.39#ibcon#read 4, iclass 15, count 0 2006.260.08:18:42.39#ibcon#about to read 5, iclass 15, count 0 2006.260.08:18:42.39#ibcon#read 5, iclass 15, count 0 2006.260.08:18:42.39#ibcon#about to read 6, iclass 15, count 0 2006.260.08:18:42.39#ibcon#read 6, iclass 15, count 0 2006.260.08:18:42.39#ibcon#end of sib2, iclass 15, count 0 2006.260.08:18:42.39#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:18:42.39#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:18:42.39#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:18:42.39#ibcon#*before write, iclass 15, count 0 2006.260.08:18:42.39#ibcon#enter sib2, iclass 15, count 0 2006.260.08:18:42.39#ibcon#flushed, iclass 15, count 0 2006.260.08:18:42.39#ibcon#about to write, iclass 15, count 0 2006.260.08:18:42.39#ibcon#wrote, iclass 15, count 0 2006.260.08:18:42.39#ibcon#about to read 3, iclass 15, count 0 2006.260.08:18:42.43#ibcon#read 3, iclass 15, count 0 2006.260.08:18:42.43#ibcon#about to read 4, iclass 15, count 0 2006.260.08:18:42.43#ibcon#read 4, iclass 15, count 0 2006.260.08:18:42.43#ibcon#about to read 5, iclass 15, count 0 2006.260.08:18:42.43#ibcon#read 5, iclass 15, count 0 2006.260.08:18:42.43#ibcon#about to read 6, iclass 15, count 0 2006.260.08:18:42.43#ibcon#read 6, iclass 15, count 0 2006.260.08:18:42.43#ibcon#end of sib2, iclass 15, count 0 2006.260.08:18:42.43#ibcon#*after write, iclass 15, count 0 2006.260.08:18:42.43#ibcon#*before return 0, iclass 15, count 0 2006.260.08:18:42.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:42.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:18:42.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:18:42.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:18:42.43$vc4f8/vb=4,5 2006.260.08:18:42.43#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.260.08:18:42.43#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.260.08:18:42.43#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:42.43#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:42.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:42.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:42.49#ibcon#enter wrdev, iclass 17, count 2 2006.260.08:18:42.49#ibcon#first serial, iclass 17, count 2 2006.260.08:18:42.49#ibcon#enter sib2, iclass 17, count 2 2006.260.08:18:42.49#ibcon#flushed, iclass 17, count 2 2006.260.08:18:42.49#ibcon#about to write, iclass 17, count 2 2006.260.08:18:42.49#ibcon#wrote, iclass 17, count 2 2006.260.08:18:42.49#ibcon#about to read 3, iclass 17, count 2 2006.260.08:18:42.51#ibcon#read 3, iclass 17, count 2 2006.260.08:18:42.51#ibcon#about to read 4, iclass 17, count 2 2006.260.08:18:42.51#ibcon#read 4, iclass 17, count 2 2006.260.08:18:42.51#ibcon#about to read 5, iclass 17, count 2 2006.260.08:18:42.51#ibcon#read 5, iclass 17, count 2 2006.260.08:18:42.51#ibcon#about to read 6, iclass 17, count 2 2006.260.08:18:42.51#ibcon#read 6, iclass 17, count 2 2006.260.08:18:42.51#ibcon#end of sib2, iclass 17, count 2 2006.260.08:18:42.51#ibcon#*mode == 0, iclass 17, count 2 2006.260.08:18:42.51#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.260.08:18:42.51#ibcon#[27=AT04-05\r\n] 2006.260.08:18:42.51#ibcon#*before write, iclass 17, count 2 2006.260.08:18:42.51#ibcon#enter sib2, iclass 17, count 2 2006.260.08:18:42.51#ibcon#flushed, iclass 17, count 2 2006.260.08:18:42.51#ibcon#about to write, iclass 17, count 2 2006.260.08:18:42.51#ibcon#wrote, iclass 17, count 2 2006.260.08:18:42.51#ibcon#about to read 3, iclass 17, count 2 2006.260.08:18:42.54#ibcon#read 3, iclass 17, count 2 2006.260.08:18:42.54#ibcon#about to read 4, iclass 17, count 2 2006.260.08:18:42.54#ibcon#read 4, iclass 17, count 2 2006.260.08:18:42.54#ibcon#about to read 5, iclass 17, count 2 2006.260.08:18:42.54#ibcon#read 5, iclass 17, count 2 2006.260.08:18:42.54#ibcon#about to read 6, iclass 17, count 2 2006.260.08:18:42.54#ibcon#read 6, iclass 17, count 2 2006.260.08:18:42.54#ibcon#end of sib2, iclass 17, count 2 2006.260.08:18:42.54#ibcon#*after write, iclass 17, count 2 2006.260.08:18:42.54#ibcon#*before return 0, iclass 17, count 2 2006.260.08:18:42.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:42.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.260.08:18:42.54#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.260.08:18:42.54#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:42.54#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:42.66#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:42.66#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:42.66#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:18:42.66#ibcon#first serial, iclass 17, count 0 2006.260.08:18:42.66#ibcon#enter sib2, iclass 17, count 0 2006.260.08:18:42.66#ibcon#flushed, iclass 17, count 0 2006.260.08:18:42.66#ibcon#about to write, iclass 17, count 0 2006.260.08:18:42.66#ibcon#wrote, iclass 17, count 0 2006.260.08:18:42.66#ibcon#about to read 3, iclass 17, count 0 2006.260.08:18:42.68#ibcon#read 3, iclass 17, count 0 2006.260.08:18:42.68#ibcon#about to read 4, iclass 17, count 0 2006.260.08:18:42.68#ibcon#read 4, iclass 17, count 0 2006.260.08:18:42.68#ibcon#about to read 5, iclass 17, count 0 2006.260.08:18:42.68#ibcon#read 5, iclass 17, count 0 2006.260.08:18:42.68#ibcon#about to read 6, iclass 17, count 0 2006.260.08:18:42.68#ibcon#read 6, iclass 17, count 0 2006.260.08:18:42.68#ibcon#end of sib2, iclass 17, count 0 2006.260.08:18:42.68#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:18:42.68#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:18:42.68#ibcon#[27=USB\r\n] 2006.260.08:18:42.68#ibcon#*before write, iclass 17, count 0 2006.260.08:18:42.68#ibcon#enter sib2, iclass 17, count 0 2006.260.08:18:42.68#ibcon#flushed, iclass 17, count 0 2006.260.08:18:42.68#ibcon#about to write, iclass 17, count 0 2006.260.08:18:42.68#ibcon#wrote, iclass 17, count 0 2006.260.08:18:42.68#ibcon#about to read 3, iclass 17, count 0 2006.260.08:18:42.71#ibcon#read 3, iclass 17, count 0 2006.260.08:18:42.71#ibcon#about to read 4, iclass 17, count 0 2006.260.08:18:42.71#ibcon#read 4, iclass 17, count 0 2006.260.08:18:42.71#ibcon#about to read 5, iclass 17, count 0 2006.260.08:18:42.71#ibcon#read 5, iclass 17, count 0 2006.260.08:18:42.71#ibcon#about to read 6, iclass 17, count 0 2006.260.08:18:42.71#ibcon#read 6, iclass 17, count 0 2006.260.08:18:42.71#ibcon#end of sib2, iclass 17, count 0 2006.260.08:18:42.71#ibcon#*after write, iclass 17, count 0 2006.260.08:18:42.71#ibcon#*before return 0, iclass 17, count 0 2006.260.08:18:42.71#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:42.71#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.260.08:18:42.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:18:42.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:18:42.71$vc4f8/vblo=5,744.99 2006.260.08:18:42.71#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.260.08:18:42.71#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.260.08:18:42.71#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:42.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:42.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:42.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:42.71#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:18:42.71#ibcon#first serial, iclass 19, count 0 2006.260.08:18:42.71#ibcon#enter sib2, iclass 19, count 0 2006.260.08:18:42.71#ibcon#flushed, iclass 19, count 0 2006.260.08:18:42.71#ibcon#about to write, iclass 19, count 0 2006.260.08:18:42.71#ibcon#wrote, iclass 19, count 0 2006.260.08:18:42.71#ibcon#about to read 3, iclass 19, count 0 2006.260.08:18:42.73#ibcon#read 3, iclass 19, count 0 2006.260.08:18:42.73#ibcon#about to read 4, iclass 19, count 0 2006.260.08:18:42.73#ibcon#read 4, iclass 19, count 0 2006.260.08:18:42.73#ibcon#about to read 5, iclass 19, count 0 2006.260.08:18:42.73#ibcon#read 5, iclass 19, count 0 2006.260.08:18:42.73#ibcon#about to read 6, iclass 19, count 0 2006.260.08:18:42.73#ibcon#read 6, iclass 19, count 0 2006.260.08:18:42.73#ibcon#end of sib2, iclass 19, count 0 2006.260.08:18:42.73#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:18:42.73#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:18:42.73#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:18:42.73#ibcon#*before write, iclass 19, count 0 2006.260.08:18:42.73#ibcon#enter sib2, iclass 19, count 0 2006.260.08:18:42.73#ibcon#flushed, iclass 19, count 0 2006.260.08:18:42.73#ibcon#about to write, iclass 19, count 0 2006.260.08:18:42.73#ibcon#wrote, iclass 19, count 0 2006.260.08:18:42.73#ibcon#about to read 3, iclass 19, count 0 2006.260.08:18:42.77#ibcon#read 3, iclass 19, count 0 2006.260.08:18:42.77#ibcon#about to read 4, iclass 19, count 0 2006.260.08:18:42.77#ibcon#read 4, iclass 19, count 0 2006.260.08:18:42.77#ibcon#about to read 5, iclass 19, count 0 2006.260.08:18:42.77#ibcon#read 5, iclass 19, count 0 2006.260.08:18:42.77#ibcon#about to read 6, iclass 19, count 0 2006.260.08:18:42.77#ibcon#read 6, iclass 19, count 0 2006.260.08:18:42.77#ibcon#end of sib2, iclass 19, count 0 2006.260.08:18:42.77#ibcon#*after write, iclass 19, count 0 2006.260.08:18:42.77#ibcon#*before return 0, iclass 19, count 0 2006.260.08:18:42.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:42.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.260.08:18:42.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:18:42.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:18:42.77$vc4f8/vb=5,4 2006.260.08:18:42.77#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.260.08:18:42.77#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.260.08:18:42.77#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:42.77#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:42.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:42.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:42.83#ibcon#enter wrdev, iclass 21, count 2 2006.260.08:18:42.83#ibcon#first serial, iclass 21, count 2 2006.260.08:18:42.83#ibcon#enter sib2, iclass 21, count 2 2006.260.08:18:42.83#ibcon#flushed, iclass 21, count 2 2006.260.08:18:42.83#ibcon#about to write, iclass 21, count 2 2006.260.08:18:42.83#ibcon#wrote, iclass 21, count 2 2006.260.08:18:42.83#ibcon#about to read 3, iclass 21, count 2 2006.260.08:18:42.85#ibcon#read 3, iclass 21, count 2 2006.260.08:18:42.85#ibcon#about to read 4, iclass 21, count 2 2006.260.08:18:42.85#ibcon#read 4, iclass 21, count 2 2006.260.08:18:42.85#ibcon#about to read 5, iclass 21, count 2 2006.260.08:18:42.85#ibcon#read 5, iclass 21, count 2 2006.260.08:18:42.85#ibcon#about to read 6, iclass 21, count 2 2006.260.08:18:42.85#ibcon#read 6, iclass 21, count 2 2006.260.08:18:42.85#ibcon#end of sib2, iclass 21, count 2 2006.260.08:18:42.85#ibcon#*mode == 0, iclass 21, count 2 2006.260.08:18:42.85#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.260.08:18:42.85#ibcon#[27=AT05-04\r\n] 2006.260.08:18:42.85#ibcon#*before write, iclass 21, count 2 2006.260.08:18:42.85#ibcon#enter sib2, iclass 21, count 2 2006.260.08:18:42.85#ibcon#flushed, iclass 21, count 2 2006.260.08:18:42.85#ibcon#about to write, iclass 21, count 2 2006.260.08:18:42.85#ibcon#wrote, iclass 21, count 2 2006.260.08:18:42.85#ibcon#about to read 3, iclass 21, count 2 2006.260.08:18:42.88#ibcon#read 3, iclass 21, count 2 2006.260.08:18:42.88#ibcon#about to read 4, iclass 21, count 2 2006.260.08:18:42.88#ibcon#read 4, iclass 21, count 2 2006.260.08:18:42.88#ibcon#about to read 5, iclass 21, count 2 2006.260.08:18:42.88#ibcon#read 5, iclass 21, count 2 2006.260.08:18:42.88#ibcon#about to read 6, iclass 21, count 2 2006.260.08:18:42.88#ibcon#read 6, iclass 21, count 2 2006.260.08:18:42.88#ibcon#end of sib2, iclass 21, count 2 2006.260.08:18:42.88#ibcon#*after write, iclass 21, count 2 2006.260.08:18:42.88#ibcon#*before return 0, iclass 21, count 2 2006.260.08:18:42.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:42.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.260.08:18:42.88#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.260.08:18:42.88#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:42.88#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:43.00#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:43.00#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:43.00#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:18:43.00#ibcon#first serial, iclass 21, count 0 2006.260.08:18:43.00#ibcon#enter sib2, iclass 21, count 0 2006.260.08:18:43.00#ibcon#flushed, iclass 21, count 0 2006.260.08:18:43.00#ibcon#about to write, iclass 21, count 0 2006.260.08:18:43.00#ibcon#wrote, iclass 21, count 0 2006.260.08:18:43.00#ibcon#about to read 3, iclass 21, count 0 2006.260.08:18:43.02#ibcon#read 3, iclass 21, count 0 2006.260.08:18:43.02#ibcon#about to read 4, iclass 21, count 0 2006.260.08:18:43.02#ibcon#read 4, iclass 21, count 0 2006.260.08:18:43.02#ibcon#about to read 5, iclass 21, count 0 2006.260.08:18:43.02#ibcon#read 5, iclass 21, count 0 2006.260.08:18:43.02#ibcon#about to read 6, iclass 21, count 0 2006.260.08:18:43.02#ibcon#read 6, iclass 21, count 0 2006.260.08:18:43.02#ibcon#end of sib2, iclass 21, count 0 2006.260.08:18:43.02#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:18:43.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:18:43.02#ibcon#[27=USB\r\n] 2006.260.08:18:43.02#ibcon#*before write, iclass 21, count 0 2006.260.08:18:43.02#ibcon#enter sib2, iclass 21, count 0 2006.260.08:18:43.02#ibcon#flushed, iclass 21, count 0 2006.260.08:18:43.02#ibcon#about to write, iclass 21, count 0 2006.260.08:18:43.02#ibcon#wrote, iclass 21, count 0 2006.260.08:18:43.02#ibcon#about to read 3, iclass 21, count 0 2006.260.08:18:43.05#ibcon#read 3, iclass 21, count 0 2006.260.08:18:43.05#ibcon#about to read 4, iclass 21, count 0 2006.260.08:18:43.05#ibcon#read 4, iclass 21, count 0 2006.260.08:18:43.05#ibcon#about to read 5, iclass 21, count 0 2006.260.08:18:43.05#ibcon#read 5, iclass 21, count 0 2006.260.08:18:43.05#ibcon#about to read 6, iclass 21, count 0 2006.260.08:18:43.05#ibcon#read 6, iclass 21, count 0 2006.260.08:18:43.05#ibcon#end of sib2, iclass 21, count 0 2006.260.08:18:43.05#ibcon#*after write, iclass 21, count 0 2006.260.08:18:43.05#ibcon#*before return 0, iclass 21, count 0 2006.260.08:18:43.05#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:43.05#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.260.08:18:43.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:18:43.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:18:43.05$vc4f8/vblo=6,752.99 2006.260.08:18:43.05#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.260.08:18:43.05#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.260.08:18:43.05#ibcon#ireg 17 cls_cnt 0 2006.260.08:18:43.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:43.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:43.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:43.05#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:18:43.05#ibcon#first serial, iclass 23, count 0 2006.260.08:18:43.05#ibcon#enter sib2, iclass 23, count 0 2006.260.08:18:43.05#ibcon#flushed, iclass 23, count 0 2006.260.08:18:43.05#ibcon#about to write, iclass 23, count 0 2006.260.08:18:43.05#ibcon#wrote, iclass 23, count 0 2006.260.08:18:43.05#ibcon#about to read 3, iclass 23, count 0 2006.260.08:18:43.07#ibcon#read 3, iclass 23, count 0 2006.260.08:18:43.07#ibcon#about to read 4, iclass 23, count 0 2006.260.08:18:43.07#ibcon#read 4, iclass 23, count 0 2006.260.08:18:43.07#ibcon#about to read 5, iclass 23, count 0 2006.260.08:18:43.07#ibcon#read 5, iclass 23, count 0 2006.260.08:18:43.07#ibcon#about to read 6, iclass 23, count 0 2006.260.08:18:43.07#ibcon#read 6, iclass 23, count 0 2006.260.08:18:43.07#ibcon#end of sib2, iclass 23, count 0 2006.260.08:18:43.07#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:18:43.07#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:18:43.07#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:18:43.07#ibcon#*before write, iclass 23, count 0 2006.260.08:18:43.07#ibcon#enter sib2, iclass 23, count 0 2006.260.08:18:43.07#ibcon#flushed, iclass 23, count 0 2006.260.08:18:43.07#ibcon#about to write, iclass 23, count 0 2006.260.08:18:43.07#ibcon#wrote, iclass 23, count 0 2006.260.08:18:43.07#ibcon#about to read 3, iclass 23, count 0 2006.260.08:18:43.11#ibcon#read 3, iclass 23, count 0 2006.260.08:18:43.11#ibcon#about to read 4, iclass 23, count 0 2006.260.08:18:43.11#ibcon#read 4, iclass 23, count 0 2006.260.08:18:43.11#ibcon#about to read 5, iclass 23, count 0 2006.260.08:18:43.11#ibcon#read 5, iclass 23, count 0 2006.260.08:18:43.11#ibcon#about to read 6, iclass 23, count 0 2006.260.08:18:43.11#ibcon#read 6, iclass 23, count 0 2006.260.08:18:43.11#ibcon#end of sib2, iclass 23, count 0 2006.260.08:18:43.11#ibcon#*after write, iclass 23, count 0 2006.260.08:18:43.11#ibcon#*before return 0, iclass 23, count 0 2006.260.08:18:43.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:43.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.260.08:18:43.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:18:43.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:18:43.11$vc4f8/vb=6,4 2006.260.08:18:43.11#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.260.08:18:43.11#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.260.08:18:43.11#ibcon#ireg 11 cls_cnt 2 2006.260.08:18:43.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:43.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:43.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:43.17#ibcon#enter wrdev, iclass 25, count 2 2006.260.08:18:43.17#ibcon#first serial, iclass 25, count 2 2006.260.08:18:43.17#ibcon#enter sib2, iclass 25, count 2 2006.260.08:18:43.17#ibcon#flushed, iclass 25, count 2 2006.260.08:18:43.17#ibcon#about to write, iclass 25, count 2 2006.260.08:18:43.17#ibcon#wrote, iclass 25, count 2 2006.260.08:18:43.17#ibcon#about to read 3, iclass 25, count 2 2006.260.08:18:43.19#ibcon#read 3, iclass 25, count 2 2006.260.08:18:43.19#ibcon#about to read 4, iclass 25, count 2 2006.260.08:18:43.19#ibcon#read 4, iclass 25, count 2 2006.260.08:18:43.19#ibcon#about to read 5, iclass 25, count 2 2006.260.08:18:43.19#ibcon#read 5, iclass 25, count 2 2006.260.08:18:43.19#ibcon#about to read 6, iclass 25, count 2 2006.260.08:18:43.19#ibcon#read 6, iclass 25, count 2 2006.260.08:18:43.19#ibcon#end of sib2, iclass 25, count 2 2006.260.08:18:43.19#ibcon#*mode == 0, iclass 25, count 2 2006.260.08:18:43.19#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.260.08:18:43.19#ibcon#[27=AT06-04\r\n] 2006.260.08:18:43.19#ibcon#*before write, iclass 25, count 2 2006.260.08:18:43.19#ibcon#enter sib2, iclass 25, count 2 2006.260.08:18:43.19#ibcon#flushed, iclass 25, count 2 2006.260.08:18:43.19#ibcon#about to write, iclass 25, count 2 2006.260.08:18:43.19#ibcon#wrote, iclass 25, count 2 2006.260.08:18:43.19#ibcon#about to read 3, iclass 25, count 2 2006.260.08:18:43.22#ibcon#read 3, iclass 25, count 2 2006.260.08:18:43.22#ibcon#about to read 4, iclass 25, count 2 2006.260.08:18:43.22#ibcon#read 4, iclass 25, count 2 2006.260.08:18:43.22#ibcon#about to read 5, iclass 25, count 2 2006.260.08:18:43.22#ibcon#read 5, iclass 25, count 2 2006.260.08:18:43.22#ibcon#about to read 6, iclass 25, count 2 2006.260.08:18:43.22#ibcon#read 6, iclass 25, count 2 2006.260.08:18:43.22#ibcon#end of sib2, iclass 25, count 2 2006.260.08:18:43.22#ibcon#*after write, iclass 25, count 2 2006.260.08:18:43.22#ibcon#*before return 0, iclass 25, count 2 2006.260.08:18:43.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:43.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.260.08:18:43.22#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.260.08:18:43.22#ibcon#ireg 7 cls_cnt 0 2006.260.08:18:43.22#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:43.34#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:43.34#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:43.34#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:18:43.34#ibcon#first serial, iclass 25, count 0 2006.260.08:18:43.34#ibcon#enter sib2, iclass 25, count 0 2006.260.08:18:43.34#ibcon#flushed, iclass 25, count 0 2006.260.08:18:43.34#ibcon#about to write, iclass 25, count 0 2006.260.08:18:43.34#ibcon#wrote, iclass 25, count 0 2006.260.08:18:43.34#ibcon#about to read 3, iclass 25, count 0 2006.260.08:18:43.36#ibcon#read 3, iclass 25, count 0 2006.260.08:18:43.36#ibcon#about to read 4, iclass 25, count 0 2006.260.08:18:43.36#ibcon#read 4, iclass 25, count 0 2006.260.08:18:43.36#ibcon#about to read 5, iclass 25, count 0 2006.260.08:18:43.36#ibcon#read 5, iclass 25, count 0 2006.260.08:18:43.36#ibcon#about to read 6, iclass 25, count 0 2006.260.08:18:43.36#ibcon#read 6, iclass 25, count 0 2006.260.08:18:43.36#ibcon#end of sib2, iclass 25, count 0 2006.260.08:18:43.36#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:18:43.36#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:18:43.36#ibcon#[27=USB\r\n] 2006.260.08:18:43.36#ibcon#*before write, iclass 25, count 0 2006.260.08:18:43.36#ibcon#enter sib2, iclass 25, count 0 2006.260.08:18:43.36#ibcon#flushed, iclass 25, count 0 2006.260.08:18:43.36#ibcon#about to write, iclass 25, count 0 2006.260.08:18:43.36#ibcon#wrote, iclass 25, count 0 2006.260.08:18:43.36#ibcon#about to read 3, iclass 25, count 0 2006.260.08:18:43.39#ibcon#read 3, iclass 25, count 0 2006.260.08:18:43.39#ibcon#about to read 4, iclass 25, count 0 2006.260.08:18:43.39#ibcon#read 4, iclass 25, count 0 2006.260.08:18:43.39#ibcon#about to read 5, iclass 25, count 0 2006.260.08:18:43.39#ibcon#read 5, iclass 25, count 0 2006.260.08:18:43.39#ibcon#about to read 6, iclass 25, count 0 2006.260.08:18:43.39#ibcon#read 6, iclass 25, count 0 2006.260.08:18:43.39#ibcon#end of sib2, iclass 25, count 0 2006.260.08:18:43.39#ibcon#*after write, iclass 25, count 0 2006.260.08:18:43.39#ibcon#*before return 0, iclass 25, count 0 2006.260.08:18:43.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:43.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.260.08:18:43.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:18:43.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:18:43.39$vc4f8/vabw=wide 2006.260.08:18:43.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.260.08:18:43.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.260.08:18:43.39#ibcon#ireg 8 cls_cnt 0 2006.260.08:18:43.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:43.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:43.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:43.39#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:18:43.39#ibcon#first serial, iclass 27, count 0 2006.260.08:18:43.39#ibcon#enter sib2, iclass 27, count 0 2006.260.08:18:43.39#ibcon#flushed, iclass 27, count 0 2006.260.08:18:43.39#ibcon#about to write, iclass 27, count 0 2006.260.08:18:43.39#ibcon#wrote, iclass 27, count 0 2006.260.08:18:43.39#ibcon#about to read 3, iclass 27, count 0 2006.260.08:18:43.41#ibcon#read 3, iclass 27, count 0 2006.260.08:18:43.41#ibcon#about to read 4, iclass 27, count 0 2006.260.08:18:43.41#ibcon#read 4, iclass 27, count 0 2006.260.08:18:43.41#ibcon#about to read 5, iclass 27, count 0 2006.260.08:18:43.41#ibcon#read 5, iclass 27, count 0 2006.260.08:18:43.41#ibcon#about to read 6, iclass 27, count 0 2006.260.08:18:43.41#ibcon#read 6, iclass 27, count 0 2006.260.08:18:43.41#ibcon#end of sib2, iclass 27, count 0 2006.260.08:18:43.41#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:18:43.41#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:18:43.41#ibcon#[25=BW32\r\n] 2006.260.08:18:43.41#ibcon#*before write, iclass 27, count 0 2006.260.08:18:43.41#ibcon#enter sib2, iclass 27, count 0 2006.260.08:18:43.41#ibcon#flushed, iclass 27, count 0 2006.260.08:18:43.41#ibcon#about to write, iclass 27, count 0 2006.260.08:18:43.41#ibcon#wrote, iclass 27, count 0 2006.260.08:18:43.41#ibcon#about to read 3, iclass 27, count 0 2006.260.08:18:43.44#ibcon#read 3, iclass 27, count 0 2006.260.08:18:43.44#ibcon#about to read 4, iclass 27, count 0 2006.260.08:18:43.44#ibcon#read 4, iclass 27, count 0 2006.260.08:18:43.44#ibcon#about to read 5, iclass 27, count 0 2006.260.08:18:43.44#ibcon#read 5, iclass 27, count 0 2006.260.08:18:43.44#ibcon#about to read 6, iclass 27, count 0 2006.260.08:18:43.44#ibcon#read 6, iclass 27, count 0 2006.260.08:18:43.44#ibcon#end of sib2, iclass 27, count 0 2006.260.08:18:43.44#ibcon#*after write, iclass 27, count 0 2006.260.08:18:43.44#ibcon#*before return 0, iclass 27, count 0 2006.260.08:18:43.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:43.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.260.08:18:43.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:18:43.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:18:43.44$vc4f8/vbbw=wide 2006.260.08:18:43.44#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:18:43.44#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:18:43.44#ibcon#ireg 8 cls_cnt 0 2006.260.08:18:43.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:18:43.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:18:43.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:18:43.51#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:18:43.51#ibcon#first serial, iclass 29, count 0 2006.260.08:18:43.51#ibcon#enter sib2, iclass 29, count 0 2006.260.08:18:43.51#ibcon#flushed, iclass 29, count 0 2006.260.08:18:43.51#ibcon#about to write, iclass 29, count 0 2006.260.08:18:43.51#ibcon#wrote, iclass 29, count 0 2006.260.08:18:43.51#ibcon#about to read 3, iclass 29, count 0 2006.260.08:18:43.52#abcon#<5=/04 3.2 6.5 22.73 891010.4\r\n> 2006.260.08:18:43.53#ibcon#read 3, iclass 29, count 0 2006.260.08:18:43.53#ibcon#about to read 4, iclass 29, count 0 2006.260.08:18:43.53#ibcon#read 4, iclass 29, count 0 2006.260.08:18:43.53#ibcon#about to read 5, iclass 29, count 0 2006.260.08:18:43.53#ibcon#read 5, iclass 29, count 0 2006.260.08:18:43.53#ibcon#about to read 6, iclass 29, count 0 2006.260.08:18:43.53#ibcon#read 6, iclass 29, count 0 2006.260.08:18:43.53#ibcon#end of sib2, iclass 29, count 0 2006.260.08:18:43.53#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:18:43.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:18:43.53#ibcon#[27=BW32\r\n] 2006.260.08:18:43.53#ibcon#*before write, iclass 29, count 0 2006.260.08:18:43.53#ibcon#enter sib2, iclass 29, count 0 2006.260.08:18:43.53#ibcon#flushed, iclass 29, count 0 2006.260.08:18:43.53#ibcon#about to write, iclass 29, count 0 2006.260.08:18:43.53#ibcon#wrote, iclass 29, count 0 2006.260.08:18:43.53#ibcon#about to read 3, iclass 29, count 0 2006.260.08:18:43.54#abcon#{5=INTERFACE CLEAR} 2006.260.08:18:43.56#ibcon#read 3, iclass 29, count 0 2006.260.08:18:43.56#ibcon#about to read 4, iclass 29, count 0 2006.260.08:18:43.56#ibcon#read 4, iclass 29, count 0 2006.260.08:18:43.56#ibcon#about to read 5, iclass 29, count 0 2006.260.08:18:43.56#ibcon#read 5, iclass 29, count 0 2006.260.08:18:43.56#ibcon#about to read 6, iclass 29, count 0 2006.260.08:18:43.56#ibcon#read 6, iclass 29, count 0 2006.260.08:18:43.56#ibcon#end of sib2, iclass 29, count 0 2006.260.08:18:43.56#ibcon#*after write, iclass 29, count 0 2006.260.08:18:43.56#ibcon#*before return 0, iclass 29, count 0 2006.260.08:18:43.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:18:43.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:18:43.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:18:43.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:18:43.56$4f8m12a/ifd4f 2006.260.08:18:43.56$ifd4f/lo= 2006.260.08:18:43.56$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:18:43.56$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:18:43.56$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:18:43.56$ifd4f/patch= 2006.260.08:18:43.56$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:18:43.56$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:18:43.56$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:18:43.56$4f8m12a/"form=m,16.000,1:2 2006.260.08:18:43.56$4f8m12a/"tpicd 2006.260.08:18:43.56$4f8m12a/echo=off 2006.260.08:18:43.56$4f8m12a/xlog=off 2006.260.08:18:43.56:!2006.260.08:20:10 2006.260.08:19:06.13#trakl#Source acquired 2006.260.08:19:07.13#flagr#flagr/antenna,acquired 2006.260.08:20:10.00:preob 2006.260.08:20:11.14/onsource/TRACKING 2006.260.08:20:11.14:!2006.260.08:20:20 2006.260.08:20:20.00:data_valid=on 2006.260.08:20:20.00:midob 2006.260.08:20:20.14/onsource/TRACKING 2006.260.08:20:20.14/wx/22.71,1010.4,90 2006.260.08:20:20.28/cable/+6.4578E-03 2006.260.08:20:21.37/va/01,08,usb,yes,36,38 2006.260.08:20:21.37/va/02,07,usb,yes,36,38 2006.260.08:20:21.37/va/03,08,usb,yes,28,28 2006.260.08:20:21.37/va/04,07,usb,yes,38,41 2006.260.08:20:21.37/va/05,07,usb,yes,42,45 2006.260.08:20:21.37/va/06,06,usb,yes,41,41 2006.260.08:20:21.37/va/07,06,usb,yes,42,42 2006.260.08:20:21.37/va/08,06,usb,yes,45,44 2006.260.08:20:21.60/valo/01,532.99,yes,locked 2006.260.08:20:21.60/valo/02,572.99,yes,locked 2006.260.08:20:21.60/valo/03,672.99,yes,locked 2006.260.08:20:21.60/valo/04,832.99,yes,locked 2006.260.08:20:21.60/valo/05,652.99,yes,locked 2006.260.08:20:21.60/valo/06,772.99,yes,locked 2006.260.08:20:21.60/valo/07,832.99,yes,locked 2006.260.08:20:21.60/valo/08,852.99,yes,locked 2006.260.08:20:22.69/vb/01,04,usb,yes,33,31 2006.260.08:20:22.69/vb/02,05,usb,yes,31,32 2006.260.08:20:22.69/vb/03,04,usb,yes,31,35 2006.260.08:20:22.69/vb/04,05,usb,yes,28,28 2006.260.08:20:22.69/vb/05,04,usb,yes,30,35 2006.260.08:20:22.69/vb/06,04,usb,yes,31,34 2006.260.08:20:22.69/vb/07,04,usb,yes,34,34 2006.260.08:20:22.69/vb/08,04,usb,yes,31,35 2006.260.08:20:22.93/vblo/01,632.99,yes,locked 2006.260.08:20:22.93/vblo/02,640.99,yes,locked 2006.260.08:20:22.93/vblo/03,656.99,yes,locked 2006.260.08:20:22.93/vblo/04,712.99,yes,locked 2006.260.08:20:22.93/vblo/05,744.99,yes,locked 2006.260.08:20:22.93/vblo/06,752.99,yes,locked 2006.260.08:20:22.93/vblo/07,734.99,yes,locked 2006.260.08:20:22.93/vblo/08,744.99,yes,locked 2006.260.08:20:23.08/vabw/8 2006.260.08:20:23.23/vbbw/8 2006.260.08:20:23.32/xfe/off,on,15.2 2006.260.08:20:23.70/ifatt/23,28,28,28 2006.260.08:20:24.08/fmout-gps/S +4.48E-07 2006.260.08:20:24.12:!2006.260.08:21:20 2006.260.08:21:20.00:data_valid=off 2006.260.08:21:20.00:postob 2006.260.08:21:20.23/cable/+6.4580E-03 2006.260.08:21:20.23/wx/22.69,1010.4,90 2006.260.08:21:21.08/fmout-gps/S +4.51E-07 2006.260.08:21:21.08:scan_name=260-0823,k06260,60 2006.260.08:21:21.08:source=1351-018,135406.90,-020603.2,2000.0,ccw 2006.260.08:21:21.14#flagr#flagr/antenna,new-source 2006.260.08:21:22.14:checkk5 2006.260.08:21:22.57/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:21:22.99/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:21:23.48/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:21:23.89/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:21:24.32/chk_obsdata//k5ts1/T2600820??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:21:24.71/chk_obsdata//k5ts2/T2600820??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:21:25.11/chk_obsdata//k5ts3/T2600820??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:21:25.76/chk_obsdata//k5ts4/T2600820??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.260.08:21:26.60/k5log//k5ts1_log_newline 2006.260.08:21:27.63/k5log//k5ts2_log_newline 2006.260.08:21:28.45/k5log//k5ts3_log_newline 2006.260.08:21:29.28/k5log//k5ts4_log_newline 2006.260.08:21:29.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:21:29.30:4f8m12a=3 2006.260.08:21:29.30$4f8m12a/echo=on 2006.260.08:21:29.30$4f8m12a/pcalon 2006.260.08:21:29.30$pcalon/"no phase cal control is implemented here 2006.260.08:21:29.30$4f8m12a/"tpicd=stop 2006.260.08:21:29.30$4f8m12a/vc4f8 2006.260.08:21:29.30$vc4f8/valo=1,532.99 2006.260.08:21:29.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:21:29.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:21:29.31#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:29.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:29.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:29.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:29.31#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:21:29.31#ibcon#first serial, iclass 28, count 0 2006.260.08:21:29.31#ibcon#enter sib2, iclass 28, count 0 2006.260.08:21:29.31#ibcon#flushed, iclass 28, count 0 2006.260.08:21:29.31#ibcon#about to write, iclass 28, count 0 2006.260.08:21:29.31#ibcon#wrote, iclass 28, count 0 2006.260.08:21:29.31#ibcon#about to read 3, iclass 28, count 0 2006.260.08:21:29.35#ibcon#read 3, iclass 28, count 0 2006.260.08:21:29.35#ibcon#about to read 4, iclass 28, count 0 2006.260.08:21:29.35#ibcon#read 4, iclass 28, count 0 2006.260.08:21:29.35#ibcon#about to read 5, iclass 28, count 0 2006.260.08:21:29.35#ibcon#read 5, iclass 28, count 0 2006.260.08:21:29.35#ibcon#about to read 6, iclass 28, count 0 2006.260.08:21:29.35#ibcon#read 6, iclass 28, count 0 2006.260.08:21:29.35#ibcon#end of sib2, iclass 28, count 0 2006.260.08:21:29.35#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:21:29.35#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:21:29.35#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:21:29.35#ibcon#*before write, iclass 28, count 0 2006.260.08:21:29.35#ibcon#enter sib2, iclass 28, count 0 2006.260.08:21:29.35#ibcon#flushed, iclass 28, count 0 2006.260.08:21:29.35#ibcon#about to write, iclass 28, count 0 2006.260.08:21:29.35#ibcon#wrote, iclass 28, count 0 2006.260.08:21:29.35#ibcon#about to read 3, iclass 28, count 0 2006.260.08:21:29.40#ibcon#read 3, iclass 28, count 0 2006.260.08:21:29.40#ibcon#about to read 4, iclass 28, count 0 2006.260.08:21:29.40#ibcon#read 4, iclass 28, count 0 2006.260.08:21:29.40#ibcon#about to read 5, iclass 28, count 0 2006.260.08:21:29.40#ibcon#read 5, iclass 28, count 0 2006.260.08:21:29.40#ibcon#about to read 6, iclass 28, count 0 2006.260.08:21:29.40#ibcon#read 6, iclass 28, count 0 2006.260.08:21:29.40#ibcon#end of sib2, iclass 28, count 0 2006.260.08:21:29.40#ibcon#*after write, iclass 28, count 0 2006.260.08:21:29.40#ibcon#*before return 0, iclass 28, count 0 2006.260.08:21:29.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:29.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:29.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:21:29.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:21:29.40$vc4f8/va=1,8 2006.260.08:21:29.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:21:29.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:21:29.40#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:29.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:29.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:29.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:29.40#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:21:29.40#ibcon#first serial, iclass 30, count 2 2006.260.08:21:29.40#ibcon#enter sib2, iclass 30, count 2 2006.260.08:21:29.40#ibcon#flushed, iclass 30, count 2 2006.260.08:21:29.40#ibcon#about to write, iclass 30, count 2 2006.260.08:21:29.40#ibcon#wrote, iclass 30, count 2 2006.260.08:21:29.40#ibcon#about to read 3, iclass 30, count 2 2006.260.08:21:29.42#ibcon#read 3, iclass 30, count 2 2006.260.08:21:29.42#ibcon#about to read 4, iclass 30, count 2 2006.260.08:21:29.42#ibcon#read 4, iclass 30, count 2 2006.260.08:21:29.42#ibcon#about to read 5, iclass 30, count 2 2006.260.08:21:29.42#ibcon#read 5, iclass 30, count 2 2006.260.08:21:29.42#ibcon#about to read 6, iclass 30, count 2 2006.260.08:21:29.42#ibcon#read 6, iclass 30, count 2 2006.260.08:21:29.42#ibcon#end of sib2, iclass 30, count 2 2006.260.08:21:29.42#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:21:29.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:21:29.42#ibcon#[25=AT01-08\r\n] 2006.260.08:21:29.42#ibcon#*before write, iclass 30, count 2 2006.260.08:21:29.42#ibcon#enter sib2, iclass 30, count 2 2006.260.08:21:29.42#ibcon#flushed, iclass 30, count 2 2006.260.08:21:29.42#ibcon#about to write, iclass 30, count 2 2006.260.08:21:29.42#ibcon#wrote, iclass 30, count 2 2006.260.08:21:29.42#ibcon#about to read 3, iclass 30, count 2 2006.260.08:21:29.45#ibcon#read 3, iclass 30, count 2 2006.260.08:21:29.45#ibcon#about to read 4, iclass 30, count 2 2006.260.08:21:29.45#ibcon#read 4, iclass 30, count 2 2006.260.08:21:29.45#ibcon#about to read 5, iclass 30, count 2 2006.260.08:21:29.45#ibcon#read 5, iclass 30, count 2 2006.260.08:21:29.45#ibcon#about to read 6, iclass 30, count 2 2006.260.08:21:29.45#ibcon#read 6, iclass 30, count 2 2006.260.08:21:29.45#ibcon#end of sib2, iclass 30, count 2 2006.260.08:21:29.45#ibcon#*after write, iclass 30, count 2 2006.260.08:21:29.45#ibcon#*before return 0, iclass 30, count 2 2006.260.08:21:29.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:29.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:29.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:21:29.45#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:29.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:29.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:29.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:29.57#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:21:29.57#ibcon#first serial, iclass 30, count 0 2006.260.08:21:29.57#ibcon#enter sib2, iclass 30, count 0 2006.260.08:21:29.57#ibcon#flushed, iclass 30, count 0 2006.260.08:21:29.57#ibcon#about to write, iclass 30, count 0 2006.260.08:21:29.57#ibcon#wrote, iclass 30, count 0 2006.260.08:21:29.57#ibcon#about to read 3, iclass 30, count 0 2006.260.08:21:29.59#ibcon#read 3, iclass 30, count 0 2006.260.08:21:29.59#ibcon#about to read 4, iclass 30, count 0 2006.260.08:21:29.59#ibcon#read 4, iclass 30, count 0 2006.260.08:21:29.59#ibcon#about to read 5, iclass 30, count 0 2006.260.08:21:29.59#ibcon#read 5, iclass 30, count 0 2006.260.08:21:29.59#ibcon#about to read 6, iclass 30, count 0 2006.260.08:21:29.59#ibcon#read 6, iclass 30, count 0 2006.260.08:21:29.59#ibcon#end of sib2, iclass 30, count 0 2006.260.08:21:29.59#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:21:29.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:21:29.59#ibcon#[25=USB\r\n] 2006.260.08:21:29.59#ibcon#*before write, iclass 30, count 0 2006.260.08:21:29.59#ibcon#enter sib2, iclass 30, count 0 2006.260.08:21:29.59#ibcon#flushed, iclass 30, count 0 2006.260.08:21:29.59#ibcon#about to write, iclass 30, count 0 2006.260.08:21:29.59#ibcon#wrote, iclass 30, count 0 2006.260.08:21:29.59#ibcon#about to read 3, iclass 30, count 0 2006.260.08:21:29.62#ibcon#read 3, iclass 30, count 0 2006.260.08:21:29.62#ibcon#about to read 4, iclass 30, count 0 2006.260.08:21:29.62#ibcon#read 4, iclass 30, count 0 2006.260.08:21:29.62#ibcon#about to read 5, iclass 30, count 0 2006.260.08:21:29.62#ibcon#read 5, iclass 30, count 0 2006.260.08:21:29.62#ibcon#about to read 6, iclass 30, count 0 2006.260.08:21:29.62#ibcon#read 6, iclass 30, count 0 2006.260.08:21:29.62#ibcon#end of sib2, iclass 30, count 0 2006.260.08:21:29.62#ibcon#*after write, iclass 30, count 0 2006.260.08:21:29.62#ibcon#*before return 0, iclass 30, count 0 2006.260.08:21:29.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:29.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:29.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:21:29.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:21:29.62$vc4f8/valo=2,572.99 2006.260.08:21:29.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:21:29.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:21:29.62#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:29.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:29.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:29.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:29.62#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:21:29.62#ibcon#first serial, iclass 32, count 0 2006.260.08:21:29.62#ibcon#enter sib2, iclass 32, count 0 2006.260.08:21:29.62#ibcon#flushed, iclass 32, count 0 2006.260.08:21:29.62#ibcon#about to write, iclass 32, count 0 2006.260.08:21:29.62#ibcon#wrote, iclass 32, count 0 2006.260.08:21:29.62#ibcon#about to read 3, iclass 32, count 0 2006.260.08:21:29.64#ibcon#read 3, iclass 32, count 0 2006.260.08:21:29.64#ibcon#about to read 4, iclass 32, count 0 2006.260.08:21:29.64#ibcon#read 4, iclass 32, count 0 2006.260.08:21:29.64#ibcon#about to read 5, iclass 32, count 0 2006.260.08:21:29.64#ibcon#read 5, iclass 32, count 0 2006.260.08:21:29.64#ibcon#about to read 6, iclass 32, count 0 2006.260.08:21:29.64#ibcon#read 6, iclass 32, count 0 2006.260.08:21:29.64#ibcon#end of sib2, iclass 32, count 0 2006.260.08:21:29.64#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:21:29.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:21:29.64#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:21:29.64#ibcon#*before write, iclass 32, count 0 2006.260.08:21:29.64#ibcon#enter sib2, iclass 32, count 0 2006.260.08:21:29.64#ibcon#flushed, iclass 32, count 0 2006.260.08:21:29.64#ibcon#about to write, iclass 32, count 0 2006.260.08:21:29.64#ibcon#wrote, iclass 32, count 0 2006.260.08:21:29.64#ibcon#about to read 3, iclass 32, count 0 2006.260.08:21:29.68#ibcon#read 3, iclass 32, count 0 2006.260.08:21:29.68#ibcon#about to read 4, iclass 32, count 0 2006.260.08:21:29.68#ibcon#read 4, iclass 32, count 0 2006.260.08:21:29.68#ibcon#about to read 5, iclass 32, count 0 2006.260.08:21:29.68#ibcon#read 5, iclass 32, count 0 2006.260.08:21:29.68#ibcon#about to read 6, iclass 32, count 0 2006.260.08:21:29.68#ibcon#read 6, iclass 32, count 0 2006.260.08:21:29.68#ibcon#end of sib2, iclass 32, count 0 2006.260.08:21:29.68#ibcon#*after write, iclass 32, count 0 2006.260.08:21:29.68#ibcon#*before return 0, iclass 32, count 0 2006.260.08:21:29.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:29.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:29.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:21:29.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:21:29.68$vc4f8/va=2,7 2006.260.08:21:29.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.08:21:29.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.08:21:29.68#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:29.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:29.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:29.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:29.74#ibcon#enter wrdev, iclass 34, count 2 2006.260.08:21:29.74#ibcon#first serial, iclass 34, count 2 2006.260.08:21:29.74#ibcon#enter sib2, iclass 34, count 2 2006.260.08:21:29.74#ibcon#flushed, iclass 34, count 2 2006.260.08:21:29.74#ibcon#about to write, iclass 34, count 2 2006.260.08:21:29.74#ibcon#wrote, iclass 34, count 2 2006.260.08:21:29.74#ibcon#about to read 3, iclass 34, count 2 2006.260.08:21:29.76#ibcon#read 3, iclass 34, count 2 2006.260.08:21:29.76#ibcon#about to read 4, iclass 34, count 2 2006.260.08:21:29.76#ibcon#read 4, iclass 34, count 2 2006.260.08:21:29.76#ibcon#about to read 5, iclass 34, count 2 2006.260.08:21:29.76#ibcon#read 5, iclass 34, count 2 2006.260.08:21:29.76#ibcon#about to read 6, iclass 34, count 2 2006.260.08:21:29.76#ibcon#read 6, iclass 34, count 2 2006.260.08:21:29.76#ibcon#end of sib2, iclass 34, count 2 2006.260.08:21:29.76#ibcon#*mode == 0, iclass 34, count 2 2006.260.08:21:29.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.08:21:29.76#ibcon#[25=AT02-07\r\n] 2006.260.08:21:29.76#ibcon#*before write, iclass 34, count 2 2006.260.08:21:29.76#ibcon#enter sib2, iclass 34, count 2 2006.260.08:21:29.76#ibcon#flushed, iclass 34, count 2 2006.260.08:21:29.76#ibcon#about to write, iclass 34, count 2 2006.260.08:21:29.76#ibcon#wrote, iclass 34, count 2 2006.260.08:21:29.76#ibcon#about to read 3, iclass 34, count 2 2006.260.08:21:29.80#ibcon#read 3, iclass 34, count 2 2006.260.08:21:29.80#ibcon#about to read 4, iclass 34, count 2 2006.260.08:21:29.80#ibcon#read 4, iclass 34, count 2 2006.260.08:21:29.80#ibcon#about to read 5, iclass 34, count 2 2006.260.08:21:29.80#ibcon#read 5, iclass 34, count 2 2006.260.08:21:29.80#ibcon#about to read 6, iclass 34, count 2 2006.260.08:21:29.80#ibcon#read 6, iclass 34, count 2 2006.260.08:21:29.80#ibcon#end of sib2, iclass 34, count 2 2006.260.08:21:29.80#ibcon#*after write, iclass 34, count 2 2006.260.08:21:29.80#ibcon#*before return 0, iclass 34, count 2 2006.260.08:21:29.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:29.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:29.80#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.08:21:29.80#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:29.80#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:29.92#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:29.92#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:29.92#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:21:29.92#ibcon#first serial, iclass 34, count 0 2006.260.08:21:29.92#ibcon#enter sib2, iclass 34, count 0 2006.260.08:21:29.92#ibcon#flushed, iclass 34, count 0 2006.260.08:21:29.92#ibcon#about to write, iclass 34, count 0 2006.260.08:21:29.92#ibcon#wrote, iclass 34, count 0 2006.260.08:21:29.92#ibcon#about to read 3, iclass 34, count 0 2006.260.08:21:29.94#ibcon#read 3, iclass 34, count 0 2006.260.08:21:29.94#ibcon#about to read 4, iclass 34, count 0 2006.260.08:21:29.94#ibcon#read 4, iclass 34, count 0 2006.260.08:21:29.94#ibcon#about to read 5, iclass 34, count 0 2006.260.08:21:29.94#ibcon#read 5, iclass 34, count 0 2006.260.08:21:29.94#ibcon#about to read 6, iclass 34, count 0 2006.260.08:21:29.94#ibcon#read 6, iclass 34, count 0 2006.260.08:21:29.94#ibcon#end of sib2, iclass 34, count 0 2006.260.08:21:29.94#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:21:29.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:21:29.94#ibcon#[25=USB\r\n] 2006.260.08:21:29.94#ibcon#*before write, iclass 34, count 0 2006.260.08:21:29.94#ibcon#enter sib2, iclass 34, count 0 2006.260.08:21:29.94#ibcon#flushed, iclass 34, count 0 2006.260.08:21:29.94#ibcon#about to write, iclass 34, count 0 2006.260.08:21:29.94#ibcon#wrote, iclass 34, count 0 2006.260.08:21:29.94#ibcon#about to read 3, iclass 34, count 0 2006.260.08:21:29.97#ibcon#read 3, iclass 34, count 0 2006.260.08:21:29.97#ibcon#about to read 4, iclass 34, count 0 2006.260.08:21:29.97#ibcon#read 4, iclass 34, count 0 2006.260.08:21:29.97#ibcon#about to read 5, iclass 34, count 0 2006.260.08:21:29.97#ibcon#read 5, iclass 34, count 0 2006.260.08:21:29.97#ibcon#about to read 6, iclass 34, count 0 2006.260.08:21:29.97#ibcon#read 6, iclass 34, count 0 2006.260.08:21:29.97#ibcon#end of sib2, iclass 34, count 0 2006.260.08:21:29.97#ibcon#*after write, iclass 34, count 0 2006.260.08:21:29.97#ibcon#*before return 0, iclass 34, count 0 2006.260.08:21:29.97#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:29.97#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:29.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:21:29.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:21:29.97$vc4f8/valo=3,672.99 2006.260.08:21:29.97#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:21:29.97#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:21:29.97#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:29.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:29.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:29.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:29.97#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:21:29.97#ibcon#first serial, iclass 36, count 0 2006.260.08:21:29.97#ibcon#enter sib2, iclass 36, count 0 2006.260.08:21:29.97#ibcon#flushed, iclass 36, count 0 2006.260.08:21:29.97#ibcon#about to write, iclass 36, count 0 2006.260.08:21:29.97#ibcon#wrote, iclass 36, count 0 2006.260.08:21:29.97#ibcon#about to read 3, iclass 36, count 0 2006.260.08:21:29.99#ibcon#read 3, iclass 36, count 0 2006.260.08:21:29.99#ibcon#about to read 4, iclass 36, count 0 2006.260.08:21:29.99#ibcon#read 4, iclass 36, count 0 2006.260.08:21:29.99#ibcon#about to read 5, iclass 36, count 0 2006.260.08:21:29.99#ibcon#read 5, iclass 36, count 0 2006.260.08:21:29.99#ibcon#about to read 6, iclass 36, count 0 2006.260.08:21:29.99#ibcon#read 6, iclass 36, count 0 2006.260.08:21:29.99#ibcon#end of sib2, iclass 36, count 0 2006.260.08:21:29.99#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:21:29.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:21:29.99#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:21:29.99#ibcon#*before write, iclass 36, count 0 2006.260.08:21:29.99#ibcon#enter sib2, iclass 36, count 0 2006.260.08:21:29.99#ibcon#flushed, iclass 36, count 0 2006.260.08:21:29.99#ibcon#about to write, iclass 36, count 0 2006.260.08:21:29.99#ibcon#wrote, iclass 36, count 0 2006.260.08:21:29.99#ibcon#about to read 3, iclass 36, count 0 2006.260.08:21:30.03#ibcon#read 3, iclass 36, count 0 2006.260.08:21:30.03#ibcon#about to read 4, iclass 36, count 0 2006.260.08:21:30.03#ibcon#read 4, iclass 36, count 0 2006.260.08:21:30.03#ibcon#about to read 5, iclass 36, count 0 2006.260.08:21:30.03#ibcon#read 5, iclass 36, count 0 2006.260.08:21:30.03#ibcon#about to read 6, iclass 36, count 0 2006.260.08:21:30.03#ibcon#read 6, iclass 36, count 0 2006.260.08:21:30.03#ibcon#end of sib2, iclass 36, count 0 2006.260.08:21:30.03#ibcon#*after write, iclass 36, count 0 2006.260.08:21:30.03#ibcon#*before return 0, iclass 36, count 0 2006.260.08:21:30.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:30.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:30.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:21:30.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:21:30.03$vc4f8/va=3,8 2006.260.08:21:30.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.08:21:30.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.08:21:30.03#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:30.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:30.09#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:30.09#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:30.09#ibcon#enter wrdev, iclass 38, count 2 2006.260.08:21:30.09#ibcon#first serial, iclass 38, count 2 2006.260.08:21:30.09#ibcon#enter sib2, iclass 38, count 2 2006.260.08:21:30.09#ibcon#flushed, iclass 38, count 2 2006.260.08:21:30.09#ibcon#about to write, iclass 38, count 2 2006.260.08:21:30.09#ibcon#wrote, iclass 38, count 2 2006.260.08:21:30.09#ibcon#about to read 3, iclass 38, count 2 2006.260.08:21:30.11#ibcon#read 3, iclass 38, count 2 2006.260.08:21:30.11#ibcon#about to read 4, iclass 38, count 2 2006.260.08:21:30.11#ibcon#read 4, iclass 38, count 2 2006.260.08:21:30.11#ibcon#about to read 5, iclass 38, count 2 2006.260.08:21:30.11#ibcon#read 5, iclass 38, count 2 2006.260.08:21:30.11#ibcon#about to read 6, iclass 38, count 2 2006.260.08:21:30.11#ibcon#read 6, iclass 38, count 2 2006.260.08:21:30.11#ibcon#end of sib2, iclass 38, count 2 2006.260.08:21:30.11#ibcon#*mode == 0, iclass 38, count 2 2006.260.08:21:30.11#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.08:21:30.11#ibcon#[25=AT03-08\r\n] 2006.260.08:21:30.11#ibcon#*before write, iclass 38, count 2 2006.260.08:21:30.11#ibcon#enter sib2, iclass 38, count 2 2006.260.08:21:30.11#ibcon#flushed, iclass 38, count 2 2006.260.08:21:30.11#ibcon#about to write, iclass 38, count 2 2006.260.08:21:30.11#ibcon#wrote, iclass 38, count 2 2006.260.08:21:30.11#ibcon#about to read 3, iclass 38, count 2 2006.260.08:21:30.15#ibcon#read 3, iclass 38, count 2 2006.260.08:21:30.15#ibcon#about to read 4, iclass 38, count 2 2006.260.08:21:30.15#ibcon#read 4, iclass 38, count 2 2006.260.08:21:30.15#ibcon#about to read 5, iclass 38, count 2 2006.260.08:21:30.15#ibcon#read 5, iclass 38, count 2 2006.260.08:21:30.15#ibcon#about to read 6, iclass 38, count 2 2006.260.08:21:30.15#ibcon#read 6, iclass 38, count 2 2006.260.08:21:30.15#ibcon#end of sib2, iclass 38, count 2 2006.260.08:21:30.15#ibcon#*after write, iclass 38, count 2 2006.260.08:21:30.15#ibcon#*before return 0, iclass 38, count 2 2006.260.08:21:30.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:30.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:30.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.08:21:30.15#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:30.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:30.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:30.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:30.27#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:21:30.27#ibcon#first serial, iclass 38, count 0 2006.260.08:21:30.27#ibcon#enter sib2, iclass 38, count 0 2006.260.08:21:30.27#ibcon#flushed, iclass 38, count 0 2006.260.08:21:30.27#ibcon#about to write, iclass 38, count 0 2006.260.08:21:30.27#ibcon#wrote, iclass 38, count 0 2006.260.08:21:30.27#ibcon#about to read 3, iclass 38, count 0 2006.260.08:21:30.29#ibcon#read 3, iclass 38, count 0 2006.260.08:21:30.29#ibcon#about to read 4, iclass 38, count 0 2006.260.08:21:30.29#ibcon#read 4, iclass 38, count 0 2006.260.08:21:30.29#ibcon#about to read 5, iclass 38, count 0 2006.260.08:21:30.29#ibcon#read 5, iclass 38, count 0 2006.260.08:21:30.29#ibcon#about to read 6, iclass 38, count 0 2006.260.08:21:30.29#ibcon#read 6, iclass 38, count 0 2006.260.08:21:30.29#ibcon#end of sib2, iclass 38, count 0 2006.260.08:21:30.29#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:21:30.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:21:30.29#ibcon#[25=USB\r\n] 2006.260.08:21:30.29#ibcon#*before write, iclass 38, count 0 2006.260.08:21:30.29#ibcon#enter sib2, iclass 38, count 0 2006.260.08:21:30.29#ibcon#flushed, iclass 38, count 0 2006.260.08:21:30.29#ibcon#about to write, iclass 38, count 0 2006.260.08:21:30.29#ibcon#wrote, iclass 38, count 0 2006.260.08:21:30.29#ibcon#about to read 3, iclass 38, count 0 2006.260.08:21:30.32#ibcon#read 3, iclass 38, count 0 2006.260.08:21:30.32#ibcon#about to read 4, iclass 38, count 0 2006.260.08:21:30.32#ibcon#read 4, iclass 38, count 0 2006.260.08:21:30.32#ibcon#about to read 5, iclass 38, count 0 2006.260.08:21:30.32#ibcon#read 5, iclass 38, count 0 2006.260.08:21:30.32#ibcon#about to read 6, iclass 38, count 0 2006.260.08:21:30.32#ibcon#read 6, iclass 38, count 0 2006.260.08:21:30.32#ibcon#end of sib2, iclass 38, count 0 2006.260.08:21:30.32#ibcon#*after write, iclass 38, count 0 2006.260.08:21:30.32#ibcon#*before return 0, iclass 38, count 0 2006.260.08:21:30.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:30.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:30.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:21:30.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:21:30.32$vc4f8/valo=4,832.99 2006.260.08:21:30.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.08:21:30.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.08:21:30.32#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:30.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:30.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:30.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:30.32#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:21:30.32#ibcon#first serial, iclass 40, count 0 2006.260.08:21:30.32#ibcon#enter sib2, iclass 40, count 0 2006.260.08:21:30.32#ibcon#flushed, iclass 40, count 0 2006.260.08:21:30.32#ibcon#about to write, iclass 40, count 0 2006.260.08:21:30.32#ibcon#wrote, iclass 40, count 0 2006.260.08:21:30.32#ibcon#about to read 3, iclass 40, count 0 2006.260.08:21:30.34#ibcon#read 3, iclass 40, count 0 2006.260.08:21:30.34#ibcon#about to read 4, iclass 40, count 0 2006.260.08:21:30.34#ibcon#read 4, iclass 40, count 0 2006.260.08:21:30.34#ibcon#about to read 5, iclass 40, count 0 2006.260.08:21:30.34#ibcon#read 5, iclass 40, count 0 2006.260.08:21:30.34#ibcon#about to read 6, iclass 40, count 0 2006.260.08:21:30.34#ibcon#read 6, iclass 40, count 0 2006.260.08:21:30.34#ibcon#end of sib2, iclass 40, count 0 2006.260.08:21:30.34#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:21:30.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:21:30.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:21:30.34#ibcon#*before write, iclass 40, count 0 2006.260.08:21:30.34#ibcon#enter sib2, iclass 40, count 0 2006.260.08:21:30.34#ibcon#flushed, iclass 40, count 0 2006.260.08:21:30.34#ibcon#about to write, iclass 40, count 0 2006.260.08:21:30.34#ibcon#wrote, iclass 40, count 0 2006.260.08:21:30.34#ibcon#about to read 3, iclass 40, count 0 2006.260.08:21:30.38#ibcon#read 3, iclass 40, count 0 2006.260.08:21:30.38#ibcon#about to read 4, iclass 40, count 0 2006.260.08:21:30.38#ibcon#read 4, iclass 40, count 0 2006.260.08:21:30.38#ibcon#about to read 5, iclass 40, count 0 2006.260.08:21:30.38#ibcon#read 5, iclass 40, count 0 2006.260.08:21:30.38#ibcon#about to read 6, iclass 40, count 0 2006.260.08:21:30.38#ibcon#read 6, iclass 40, count 0 2006.260.08:21:30.38#ibcon#end of sib2, iclass 40, count 0 2006.260.08:21:30.38#ibcon#*after write, iclass 40, count 0 2006.260.08:21:30.38#ibcon#*before return 0, iclass 40, count 0 2006.260.08:21:30.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:30.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:30.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:21:30.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:21:30.38$vc4f8/va=4,7 2006.260.08:21:30.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.08:21:30.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.08:21:30.38#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:30.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:30.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:30.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:30.44#ibcon#enter wrdev, iclass 4, count 2 2006.260.08:21:30.44#ibcon#first serial, iclass 4, count 2 2006.260.08:21:30.44#ibcon#enter sib2, iclass 4, count 2 2006.260.08:21:30.44#ibcon#flushed, iclass 4, count 2 2006.260.08:21:30.44#ibcon#about to write, iclass 4, count 2 2006.260.08:21:30.44#ibcon#wrote, iclass 4, count 2 2006.260.08:21:30.44#ibcon#about to read 3, iclass 4, count 2 2006.260.08:21:30.46#ibcon#read 3, iclass 4, count 2 2006.260.08:21:30.46#ibcon#about to read 4, iclass 4, count 2 2006.260.08:21:30.46#ibcon#read 4, iclass 4, count 2 2006.260.08:21:30.46#ibcon#about to read 5, iclass 4, count 2 2006.260.08:21:30.46#ibcon#read 5, iclass 4, count 2 2006.260.08:21:30.46#ibcon#about to read 6, iclass 4, count 2 2006.260.08:21:30.46#ibcon#read 6, iclass 4, count 2 2006.260.08:21:30.46#ibcon#end of sib2, iclass 4, count 2 2006.260.08:21:30.46#ibcon#*mode == 0, iclass 4, count 2 2006.260.08:21:30.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.08:21:30.46#ibcon#[25=AT04-07\r\n] 2006.260.08:21:30.46#ibcon#*before write, iclass 4, count 2 2006.260.08:21:30.46#ibcon#enter sib2, iclass 4, count 2 2006.260.08:21:30.46#ibcon#flushed, iclass 4, count 2 2006.260.08:21:30.46#ibcon#about to write, iclass 4, count 2 2006.260.08:21:30.46#ibcon#wrote, iclass 4, count 2 2006.260.08:21:30.46#ibcon#about to read 3, iclass 4, count 2 2006.260.08:21:30.49#ibcon#read 3, iclass 4, count 2 2006.260.08:21:30.49#ibcon#about to read 4, iclass 4, count 2 2006.260.08:21:30.49#ibcon#read 4, iclass 4, count 2 2006.260.08:21:30.49#ibcon#about to read 5, iclass 4, count 2 2006.260.08:21:30.49#ibcon#read 5, iclass 4, count 2 2006.260.08:21:30.49#ibcon#about to read 6, iclass 4, count 2 2006.260.08:21:30.49#ibcon#read 6, iclass 4, count 2 2006.260.08:21:30.49#ibcon#end of sib2, iclass 4, count 2 2006.260.08:21:30.49#ibcon#*after write, iclass 4, count 2 2006.260.08:21:30.49#ibcon#*before return 0, iclass 4, count 2 2006.260.08:21:30.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:30.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:30.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.08:21:30.49#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:30.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:30.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:30.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:30.61#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:21:30.61#ibcon#first serial, iclass 4, count 0 2006.260.08:21:30.61#ibcon#enter sib2, iclass 4, count 0 2006.260.08:21:30.61#ibcon#flushed, iclass 4, count 0 2006.260.08:21:30.61#ibcon#about to write, iclass 4, count 0 2006.260.08:21:30.61#ibcon#wrote, iclass 4, count 0 2006.260.08:21:30.61#ibcon#about to read 3, iclass 4, count 0 2006.260.08:21:30.63#ibcon#read 3, iclass 4, count 0 2006.260.08:21:30.63#ibcon#about to read 4, iclass 4, count 0 2006.260.08:21:30.63#ibcon#read 4, iclass 4, count 0 2006.260.08:21:30.63#ibcon#about to read 5, iclass 4, count 0 2006.260.08:21:30.63#ibcon#read 5, iclass 4, count 0 2006.260.08:21:30.63#ibcon#about to read 6, iclass 4, count 0 2006.260.08:21:30.63#ibcon#read 6, iclass 4, count 0 2006.260.08:21:30.63#ibcon#end of sib2, iclass 4, count 0 2006.260.08:21:30.63#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:21:30.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:21:30.63#ibcon#[25=USB\r\n] 2006.260.08:21:30.63#ibcon#*before write, iclass 4, count 0 2006.260.08:21:30.63#ibcon#enter sib2, iclass 4, count 0 2006.260.08:21:30.63#ibcon#flushed, iclass 4, count 0 2006.260.08:21:30.63#ibcon#about to write, iclass 4, count 0 2006.260.08:21:30.63#ibcon#wrote, iclass 4, count 0 2006.260.08:21:30.63#ibcon#about to read 3, iclass 4, count 0 2006.260.08:21:30.66#ibcon#read 3, iclass 4, count 0 2006.260.08:21:30.66#ibcon#about to read 4, iclass 4, count 0 2006.260.08:21:30.66#ibcon#read 4, iclass 4, count 0 2006.260.08:21:30.66#ibcon#about to read 5, iclass 4, count 0 2006.260.08:21:30.66#ibcon#read 5, iclass 4, count 0 2006.260.08:21:30.66#ibcon#about to read 6, iclass 4, count 0 2006.260.08:21:30.66#ibcon#read 6, iclass 4, count 0 2006.260.08:21:30.66#ibcon#end of sib2, iclass 4, count 0 2006.260.08:21:30.66#ibcon#*after write, iclass 4, count 0 2006.260.08:21:30.66#ibcon#*before return 0, iclass 4, count 0 2006.260.08:21:30.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:30.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:30.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:21:30.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:21:30.66$vc4f8/valo=5,652.99 2006.260.08:21:30.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:21:30.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:21:30.66#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:30.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:30.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:30.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:30.66#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:21:30.66#ibcon#first serial, iclass 6, count 0 2006.260.08:21:30.66#ibcon#enter sib2, iclass 6, count 0 2006.260.08:21:30.66#ibcon#flushed, iclass 6, count 0 2006.260.08:21:30.66#ibcon#about to write, iclass 6, count 0 2006.260.08:21:30.66#ibcon#wrote, iclass 6, count 0 2006.260.08:21:30.66#ibcon#about to read 3, iclass 6, count 0 2006.260.08:21:30.68#ibcon#read 3, iclass 6, count 0 2006.260.08:21:30.68#ibcon#about to read 4, iclass 6, count 0 2006.260.08:21:30.68#ibcon#read 4, iclass 6, count 0 2006.260.08:21:30.68#ibcon#about to read 5, iclass 6, count 0 2006.260.08:21:30.68#ibcon#read 5, iclass 6, count 0 2006.260.08:21:30.68#ibcon#about to read 6, iclass 6, count 0 2006.260.08:21:30.68#ibcon#read 6, iclass 6, count 0 2006.260.08:21:30.68#ibcon#end of sib2, iclass 6, count 0 2006.260.08:21:30.68#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:21:30.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:21:30.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:21:30.68#ibcon#*before write, iclass 6, count 0 2006.260.08:21:30.68#ibcon#enter sib2, iclass 6, count 0 2006.260.08:21:30.68#ibcon#flushed, iclass 6, count 0 2006.260.08:21:30.68#ibcon#about to write, iclass 6, count 0 2006.260.08:21:30.68#ibcon#wrote, iclass 6, count 0 2006.260.08:21:30.68#ibcon#about to read 3, iclass 6, count 0 2006.260.08:21:30.72#ibcon#read 3, iclass 6, count 0 2006.260.08:21:30.72#ibcon#about to read 4, iclass 6, count 0 2006.260.08:21:30.72#ibcon#read 4, iclass 6, count 0 2006.260.08:21:30.72#ibcon#about to read 5, iclass 6, count 0 2006.260.08:21:30.72#ibcon#read 5, iclass 6, count 0 2006.260.08:21:30.72#ibcon#about to read 6, iclass 6, count 0 2006.260.08:21:30.72#ibcon#read 6, iclass 6, count 0 2006.260.08:21:30.72#ibcon#end of sib2, iclass 6, count 0 2006.260.08:21:30.72#ibcon#*after write, iclass 6, count 0 2006.260.08:21:30.72#ibcon#*before return 0, iclass 6, count 0 2006.260.08:21:30.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:30.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:30.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:21:30.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:21:30.72$vc4f8/va=5,7 2006.260.08:21:30.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.08:21:30.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.08:21:30.72#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:30.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:30.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:30.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:30.78#ibcon#enter wrdev, iclass 10, count 2 2006.260.08:21:30.78#ibcon#first serial, iclass 10, count 2 2006.260.08:21:30.78#ibcon#enter sib2, iclass 10, count 2 2006.260.08:21:30.78#ibcon#flushed, iclass 10, count 2 2006.260.08:21:30.78#ibcon#about to write, iclass 10, count 2 2006.260.08:21:30.78#ibcon#wrote, iclass 10, count 2 2006.260.08:21:30.78#ibcon#about to read 3, iclass 10, count 2 2006.260.08:21:30.80#ibcon#read 3, iclass 10, count 2 2006.260.08:21:30.80#ibcon#about to read 4, iclass 10, count 2 2006.260.08:21:30.80#ibcon#read 4, iclass 10, count 2 2006.260.08:21:30.80#ibcon#about to read 5, iclass 10, count 2 2006.260.08:21:30.80#ibcon#read 5, iclass 10, count 2 2006.260.08:21:30.80#ibcon#about to read 6, iclass 10, count 2 2006.260.08:21:30.80#ibcon#read 6, iclass 10, count 2 2006.260.08:21:30.80#ibcon#end of sib2, iclass 10, count 2 2006.260.08:21:30.80#ibcon#*mode == 0, iclass 10, count 2 2006.260.08:21:30.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.08:21:30.80#ibcon#[25=AT05-07\r\n] 2006.260.08:21:30.80#ibcon#*before write, iclass 10, count 2 2006.260.08:21:30.80#ibcon#enter sib2, iclass 10, count 2 2006.260.08:21:30.80#ibcon#flushed, iclass 10, count 2 2006.260.08:21:30.80#ibcon#about to write, iclass 10, count 2 2006.260.08:21:30.80#ibcon#wrote, iclass 10, count 2 2006.260.08:21:30.80#ibcon#about to read 3, iclass 10, count 2 2006.260.08:21:30.83#ibcon#read 3, iclass 10, count 2 2006.260.08:21:30.83#ibcon#about to read 4, iclass 10, count 2 2006.260.08:21:30.83#ibcon#read 4, iclass 10, count 2 2006.260.08:21:30.83#ibcon#about to read 5, iclass 10, count 2 2006.260.08:21:30.83#ibcon#read 5, iclass 10, count 2 2006.260.08:21:30.83#ibcon#about to read 6, iclass 10, count 2 2006.260.08:21:30.83#ibcon#read 6, iclass 10, count 2 2006.260.08:21:30.83#ibcon#end of sib2, iclass 10, count 2 2006.260.08:21:30.83#ibcon#*after write, iclass 10, count 2 2006.260.08:21:30.83#ibcon#*before return 0, iclass 10, count 2 2006.260.08:21:30.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:30.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:30.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.08:21:30.83#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:30.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:30.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:30.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:30.95#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:21:30.95#ibcon#first serial, iclass 10, count 0 2006.260.08:21:30.95#ibcon#enter sib2, iclass 10, count 0 2006.260.08:21:30.95#ibcon#flushed, iclass 10, count 0 2006.260.08:21:30.95#ibcon#about to write, iclass 10, count 0 2006.260.08:21:30.95#ibcon#wrote, iclass 10, count 0 2006.260.08:21:30.95#ibcon#about to read 3, iclass 10, count 0 2006.260.08:21:30.97#ibcon#read 3, iclass 10, count 0 2006.260.08:21:30.97#ibcon#about to read 4, iclass 10, count 0 2006.260.08:21:30.97#ibcon#read 4, iclass 10, count 0 2006.260.08:21:30.97#ibcon#about to read 5, iclass 10, count 0 2006.260.08:21:30.97#ibcon#read 5, iclass 10, count 0 2006.260.08:21:30.97#ibcon#about to read 6, iclass 10, count 0 2006.260.08:21:30.97#ibcon#read 6, iclass 10, count 0 2006.260.08:21:30.97#ibcon#end of sib2, iclass 10, count 0 2006.260.08:21:30.97#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:21:30.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:21:30.97#ibcon#[25=USB\r\n] 2006.260.08:21:30.97#ibcon#*before write, iclass 10, count 0 2006.260.08:21:30.97#ibcon#enter sib2, iclass 10, count 0 2006.260.08:21:30.97#ibcon#flushed, iclass 10, count 0 2006.260.08:21:30.97#ibcon#about to write, iclass 10, count 0 2006.260.08:21:30.97#ibcon#wrote, iclass 10, count 0 2006.260.08:21:30.97#ibcon#about to read 3, iclass 10, count 0 2006.260.08:21:31.00#ibcon#read 3, iclass 10, count 0 2006.260.08:21:31.00#ibcon#about to read 4, iclass 10, count 0 2006.260.08:21:31.00#ibcon#read 4, iclass 10, count 0 2006.260.08:21:31.00#ibcon#about to read 5, iclass 10, count 0 2006.260.08:21:31.00#ibcon#read 5, iclass 10, count 0 2006.260.08:21:31.00#ibcon#about to read 6, iclass 10, count 0 2006.260.08:21:31.00#ibcon#read 6, iclass 10, count 0 2006.260.08:21:31.00#ibcon#end of sib2, iclass 10, count 0 2006.260.08:21:31.00#ibcon#*after write, iclass 10, count 0 2006.260.08:21:31.00#ibcon#*before return 0, iclass 10, count 0 2006.260.08:21:31.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:31.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:31.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:21:31.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:21:31.00$vc4f8/valo=6,772.99 2006.260.08:21:31.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:21:31.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:21:31.00#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:31.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:31.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:31.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:31.00#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:21:31.00#ibcon#first serial, iclass 12, count 0 2006.260.08:21:31.00#ibcon#enter sib2, iclass 12, count 0 2006.260.08:21:31.00#ibcon#flushed, iclass 12, count 0 2006.260.08:21:31.00#ibcon#about to write, iclass 12, count 0 2006.260.08:21:31.00#ibcon#wrote, iclass 12, count 0 2006.260.08:21:31.00#ibcon#about to read 3, iclass 12, count 0 2006.260.08:21:31.02#ibcon#read 3, iclass 12, count 0 2006.260.08:21:31.02#ibcon#about to read 4, iclass 12, count 0 2006.260.08:21:31.02#ibcon#read 4, iclass 12, count 0 2006.260.08:21:31.02#ibcon#about to read 5, iclass 12, count 0 2006.260.08:21:31.02#ibcon#read 5, iclass 12, count 0 2006.260.08:21:31.02#ibcon#about to read 6, iclass 12, count 0 2006.260.08:21:31.02#ibcon#read 6, iclass 12, count 0 2006.260.08:21:31.02#ibcon#end of sib2, iclass 12, count 0 2006.260.08:21:31.02#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:21:31.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:21:31.02#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:21:31.02#ibcon#*before write, iclass 12, count 0 2006.260.08:21:31.02#ibcon#enter sib2, iclass 12, count 0 2006.260.08:21:31.02#ibcon#flushed, iclass 12, count 0 2006.260.08:21:31.02#ibcon#about to write, iclass 12, count 0 2006.260.08:21:31.02#ibcon#wrote, iclass 12, count 0 2006.260.08:21:31.02#ibcon#about to read 3, iclass 12, count 0 2006.260.08:21:31.06#ibcon#read 3, iclass 12, count 0 2006.260.08:21:31.06#ibcon#about to read 4, iclass 12, count 0 2006.260.08:21:31.06#ibcon#read 4, iclass 12, count 0 2006.260.08:21:31.06#ibcon#about to read 5, iclass 12, count 0 2006.260.08:21:31.06#ibcon#read 5, iclass 12, count 0 2006.260.08:21:31.06#ibcon#about to read 6, iclass 12, count 0 2006.260.08:21:31.06#ibcon#read 6, iclass 12, count 0 2006.260.08:21:31.06#ibcon#end of sib2, iclass 12, count 0 2006.260.08:21:31.06#ibcon#*after write, iclass 12, count 0 2006.260.08:21:31.06#ibcon#*before return 0, iclass 12, count 0 2006.260.08:21:31.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:31.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:31.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:21:31.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:21:31.06$vc4f8/va=6,6 2006.260.08:21:31.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.260.08:21:31.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.260.08:21:31.06#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:31.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:31.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:31.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:31.12#ibcon#enter wrdev, iclass 14, count 2 2006.260.08:21:31.12#ibcon#first serial, iclass 14, count 2 2006.260.08:21:31.12#ibcon#enter sib2, iclass 14, count 2 2006.260.08:21:31.12#ibcon#flushed, iclass 14, count 2 2006.260.08:21:31.12#ibcon#about to write, iclass 14, count 2 2006.260.08:21:31.12#ibcon#wrote, iclass 14, count 2 2006.260.08:21:31.12#ibcon#about to read 3, iclass 14, count 2 2006.260.08:21:31.14#ibcon#read 3, iclass 14, count 2 2006.260.08:21:31.14#ibcon#about to read 4, iclass 14, count 2 2006.260.08:21:31.14#ibcon#read 4, iclass 14, count 2 2006.260.08:21:31.14#ibcon#about to read 5, iclass 14, count 2 2006.260.08:21:31.14#ibcon#read 5, iclass 14, count 2 2006.260.08:21:31.14#ibcon#about to read 6, iclass 14, count 2 2006.260.08:21:31.14#ibcon#read 6, iclass 14, count 2 2006.260.08:21:31.14#ibcon#end of sib2, iclass 14, count 2 2006.260.08:21:31.14#ibcon#*mode == 0, iclass 14, count 2 2006.260.08:21:31.14#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.260.08:21:31.14#ibcon#[25=AT06-06\r\n] 2006.260.08:21:31.14#ibcon#*before write, iclass 14, count 2 2006.260.08:21:31.14#ibcon#enter sib2, iclass 14, count 2 2006.260.08:21:31.14#ibcon#flushed, iclass 14, count 2 2006.260.08:21:31.14#ibcon#about to write, iclass 14, count 2 2006.260.08:21:31.14#ibcon#wrote, iclass 14, count 2 2006.260.08:21:31.14#ibcon#about to read 3, iclass 14, count 2 2006.260.08:21:31.17#ibcon#read 3, iclass 14, count 2 2006.260.08:21:31.17#ibcon#about to read 4, iclass 14, count 2 2006.260.08:21:31.17#ibcon#read 4, iclass 14, count 2 2006.260.08:21:31.17#ibcon#about to read 5, iclass 14, count 2 2006.260.08:21:31.17#ibcon#read 5, iclass 14, count 2 2006.260.08:21:31.17#ibcon#about to read 6, iclass 14, count 2 2006.260.08:21:31.17#ibcon#read 6, iclass 14, count 2 2006.260.08:21:31.17#ibcon#end of sib2, iclass 14, count 2 2006.260.08:21:31.17#ibcon#*after write, iclass 14, count 2 2006.260.08:21:31.17#ibcon#*before return 0, iclass 14, count 2 2006.260.08:21:31.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:31.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:31.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.260.08:21:31.17#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:31.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:21:31.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:21:31.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:21:31.29#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:21:31.29#ibcon#first serial, iclass 14, count 0 2006.260.08:21:31.29#ibcon#enter sib2, iclass 14, count 0 2006.260.08:21:31.29#ibcon#flushed, iclass 14, count 0 2006.260.08:21:31.29#ibcon#about to write, iclass 14, count 0 2006.260.08:21:31.29#ibcon#wrote, iclass 14, count 0 2006.260.08:21:31.29#ibcon#about to read 3, iclass 14, count 0 2006.260.08:21:31.31#ibcon#read 3, iclass 14, count 0 2006.260.08:21:31.31#ibcon#about to read 4, iclass 14, count 0 2006.260.08:21:31.31#ibcon#read 4, iclass 14, count 0 2006.260.08:21:31.31#ibcon#about to read 5, iclass 14, count 0 2006.260.08:21:31.31#ibcon#read 5, iclass 14, count 0 2006.260.08:21:31.31#ibcon#about to read 6, iclass 14, count 0 2006.260.08:21:31.31#ibcon#read 6, iclass 14, count 0 2006.260.08:21:31.31#ibcon#end of sib2, iclass 14, count 0 2006.260.08:21:31.31#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:21:31.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:21:31.31#ibcon#[25=USB\r\n] 2006.260.08:21:31.31#ibcon#*before write, iclass 14, count 0 2006.260.08:21:31.31#ibcon#enter sib2, iclass 14, count 0 2006.260.08:21:31.31#ibcon#flushed, iclass 14, count 0 2006.260.08:21:31.31#ibcon#about to write, iclass 14, count 0 2006.260.08:21:31.31#ibcon#wrote, iclass 14, count 0 2006.260.08:21:31.31#ibcon#about to read 3, iclass 14, count 0 2006.260.08:21:31.34#ibcon#read 3, iclass 14, count 0 2006.260.08:21:31.34#ibcon#about to read 4, iclass 14, count 0 2006.260.08:21:31.34#ibcon#read 4, iclass 14, count 0 2006.260.08:21:31.34#ibcon#about to read 5, iclass 14, count 0 2006.260.08:21:31.34#ibcon#read 5, iclass 14, count 0 2006.260.08:21:31.34#ibcon#about to read 6, iclass 14, count 0 2006.260.08:21:31.34#ibcon#read 6, iclass 14, count 0 2006.260.08:21:31.34#ibcon#end of sib2, iclass 14, count 0 2006.260.08:21:31.34#ibcon#*after write, iclass 14, count 0 2006.260.08:21:31.34#ibcon#*before return 0, iclass 14, count 0 2006.260.08:21:31.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:21:31.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.260.08:21:31.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:21:31.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:21:31.34$vc4f8/valo=7,832.99 2006.260.08:21:31.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.260.08:21:31.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.260.08:21:31.34#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:31.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:21:31.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:21:31.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:21:31.34#ibcon#enter wrdev, iclass 16, count 0 2006.260.08:21:31.34#ibcon#first serial, iclass 16, count 0 2006.260.08:21:31.34#ibcon#enter sib2, iclass 16, count 0 2006.260.08:21:31.34#ibcon#flushed, iclass 16, count 0 2006.260.08:21:31.34#ibcon#about to write, iclass 16, count 0 2006.260.08:21:31.34#ibcon#wrote, iclass 16, count 0 2006.260.08:21:31.34#ibcon#about to read 3, iclass 16, count 0 2006.260.08:21:31.36#ibcon#read 3, iclass 16, count 0 2006.260.08:21:31.36#ibcon#about to read 4, iclass 16, count 0 2006.260.08:21:31.36#ibcon#read 4, iclass 16, count 0 2006.260.08:21:31.36#ibcon#about to read 5, iclass 16, count 0 2006.260.08:21:31.36#ibcon#read 5, iclass 16, count 0 2006.260.08:21:31.36#ibcon#about to read 6, iclass 16, count 0 2006.260.08:21:31.36#ibcon#read 6, iclass 16, count 0 2006.260.08:21:31.36#ibcon#end of sib2, iclass 16, count 0 2006.260.08:21:31.36#ibcon#*mode == 0, iclass 16, count 0 2006.260.08:21:31.36#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.260.08:21:31.36#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:21:31.36#ibcon#*before write, iclass 16, count 0 2006.260.08:21:31.36#ibcon#enter sib2, iclass 16, count 0 2006.260.08:21:31.36#ibcon#flushed, iclass 16, count 0 2006.260.08:21:31.36#ibcon#about to write, iclass 16, count 0 2006.260.08:21:31.36#ibcon#wrote, iclass 16, count 0 2006.260.08:21:31.36#ibcon#about to read 3, iclass 16, count 0 2006.260.08:21:31.40#ibcon#read 3, iclass 16, count 0 2006.260.08:21:31.40#ibcon#about to read 4, iclass 16, count 0 2006.260.08:21:31.40#ibcon#read 4, iclass 16, count 0 2006.260.08:21:31.40#ibcon#about to read 5, iclass 16, count 0 2006.260.08:21:31.40#ibcon#read 5, iclass 16, count 0 2006.260.08:21:31.40#ibcon#about to read 6, iclass 16, count 0 2006.260.08:21:31.40#ibcon#read 6, iclass 16, count 0 2006.260.08:21:31.40#ibcon#end of sib2, iclass 16, count 0 2006.260.08:21:31.40#ibcon#*after write, iclass 16, count 0 2006.260.08:21:31.40#ibcon#*before return 0, iclass 16, count 0 2006.260.08:21:31.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:21:31.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.260.08:21:31.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.260.08:21:31.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.260.08:21:31.40$vc4f8/va=7,6 2006.260.08:21:31.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.260.08:21:31.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.260.08:21:31.40#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:31.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:21:31.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:21:31.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:21:31.46#ibcon#enter wrdev, iclass 18, count 2 2006.260.08:21:31.46#ibcon#first serial, iclass 18, count 2 2006.260.08:21:31.46#ibcon#enter sib2, iclass 18, count 2 2006.260.08:21:31.46#ibcon#flushed, iclass 18, count 2 2006.260.08:21:31.46#ibcon#about to write, iclass 18, count 2 2006.260.08:21:31.46#ibcon#wrote, iclass 18, count 2 2006.260.08:21:31.46#ibcon#about to read 3, iclass 18, count 2 2006.260.08:21:31.48#ibcon#read 3, iclass 18, count 2 2006.260.08:21:31.48#ibcon#about to read 4, iclass 18, count 2 2006.260.08:21:31.48#ibcon#read 4, iclass 18, count 2 2006.260.08:21:31.48#ibcon#about to read 5, iclass 18, count 2 2006.260.08:21:31.48#ibcon#read 5, iclass 18, count 2 2006.260.08:21:31.48#ibcon#about to read 6, iclass 18, count 2 2006.260.08:21:31.48#ibcon#read 6, iclass 18, count 2 2006.260.08:21:31.48#ibcon#end of sib2, iclass 18, count 2 2006.260.08:21:31.48#ibcon#*mode == 0, iclass 18, count 2 2006.260.08:21:31.48#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.260.08:21:31.48#ibcon#[25=AT07-06\r\n] 2006.260.08:21:31.48#ibcon#*before write, iclass 18, count 2 2006.260.08:21:31.48#ibcon#enter sib2, iclass 18, count 2 2006.260.08:21:31.48#ibcon#flushed, iclass 18, count 2 2006.260.08:21:31.48#ibcon#about to write, iclass 18, count 2 2006.260.08:21:31.48#ibcon#wrote, iclass 18, count 2 2006.260.08:21:31.48#ibcon#about to read 3, iclass 18, count 2 2006.260.08:21:31.51#ibcon#read 3, iclass 18, count 2 2006.260.08:21:31.51#ibcon#about to read 4, iclass 18, count 2 2006.260.08:21:31.51#ibcon#read 4, iclass 18, count 2 2006.260.08:21:31.51#ibcon#about to read 5, iclass 18, count 2 2006.260.08:21:31.51#ibcon#read 5, iclass 18, count 2 2006.260.08:21:31.51#ibcon#about to read 6, iclass 18, count 2 2006.260.08:21:31.51#ibcon#read 6, iclass 18, count 2 2006.260.08:21:31.51#ibcon#end of sib2, iclass 18, count 2 2006.260.08:21:31.51#ibcon#*after write, iclass 18, count 2 2006.260.08:21:31.51#ibcon#*before return 0, iclass 18, count 2 2006.260.08:21:31.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:21:31.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.260.08:21:31.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.260.08:21:31.51#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:31.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:21:31.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:21:31.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:21:31.63#ibcon#enter wrdev, iclass 18, count 0 2006.260.08:21:31.63#ibcon#first serial, iclass 18, count 0 2006.260.08:21:31.63#ibcon#enter sib2, iclass 18, count 0 2006.260.08:21:31.63#ibcon#flushed, iclass 18, count 0 2006.260.08:21:31.63#ibcon#about to write, iclass 18, count 0 2006.260.08:21:31.63#ibcon#wrote, iclass 18, count 0 2006.260.08:21:31.63#ibcon#about to read 3, iclass 18, count 0 2006.260.08:21:31.65#ibcon#read 3, iclass 18, count 0 2006.260.08:21:31.65#ibcon#about to read 4, iclass 18, count 0 2006.260.08:21:31.65#ibcon#read 4, iclass 18, count 0 2006.260.08:21:31.65#ibcon#about to read 5, iclass 18, count 0 2006.260.08:21:31.65#ibcon#read 5, iclass 18, count 0 2006.260.08:21:31.65#ibcon#about to read 6, iclass 18, count 0 2006.260.08:21:31.65#ibcon#read 6, iclass 18, count 0 2006.260.08:21:31.65#ibcon#end of sib2, iclass 18, count 0 2006.260.08:21:31.65#ibcon#*mode == 0, iclass 18, count 0 2006.260.08:21:31.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.260.08:21:31.65#ibcon#[25=USB\r\n] 2006.260.08:21:31.65#ibcon#*before write, iclass 18, count 0 2006.260.08:21:31.65#ibcon#enter sib2, iclass 18, count 0 2006.260.08:21:31.65#ibcon#flushed, iclass 18, count 0 2006.260.08:21:31.65#ibcon#about to write, iclass 18, count 0 2006.260.08:21:31.65#ibcon#wrote, iclass 18, count 0 2006.260.08:21:31.65#ibcon#about to read 3, iclass 18, count 0 2006.260.08:21:31.68#ibcon#read 3, iclass 18, count 0 2006.260.08:21:31.68#ibcon#about to read 4, iclass 18, count 0 2006.260.08:21:31.68#ibcon#read 4, iclass 18, count 0 2006.260.08:21:31.68#ibcon#about to read 5, iclass 18, count 0 2006.260.08:21:31.68#ibcon#read 5, iclass 18, count 0 2006.260.08:21:31.68#ibcon#about to read 6, iclass 18, count 0 2006.260.08:21:31.68#ibcon#read 6, iclass 18, count 0 2006.260.08:21:31.68#ibcon#end of sib2, iclass 18, count 0 2006.260.08:21:31.68#ibcon#*after write, iclass 18, count 0 2006.260.08:21:31.68#ibcon#*before return 0, iclass 18, count 0 2006.260.08:21:31.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:21:31.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.260.08:21:31.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.260.08:21:31.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.260.08:21:31.68$vc4f8/valo=8,852.99 2006.260.08:21:31.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.260.08:21:31.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.260.08:21:31.68#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:31.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:21:31.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:21:31.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:21:31.68#ibcon#enter wrdev, iclass 20, count 0 2006.260.08:21:31.68#ibcon#first serial, iclass 20, count 0 2006.260.08:21:31.68#ibcon#enter sib2, iclass 20, count 0 2006.260.08:21:31.68#ibcon#flushed, iclass 20, count 0 2006.260.08:21:31.68#ibcon#about to write, iclass 20, count 0 2006.260.08:21:31.68#ibcon#wrote, iclass 20, count 0 2006.260.08:21:31.68#ibcon#about to read 3, iclass 20, count 0 2006.260.08:21:31.70#ibcon#read 3, iclass 20, count 0 2006.260.08:21:31.70#ibcon#about to read 4, iclass 20, count 0 2006.260.08:21:31.70#ibcon#read 4, iclass 20, count 0 2006.260.08:21:31.70#ibcon#about to read 5, iclass 20, count 0 2006.260.08:21:31.70#ibcon#read 5, iclass 20, count 0 2006.260.08:21:31.70#ibcon#about to read 6, iclass 20, count 0 2006.260.08:21:31.70#ibcon#read 6, iclass 20, count 0 2006.260.08:21:31.70#ibcon#end of sib2, iclass 20, count 0 2006.260.08:21:31.70#ibcon#*mode == 0, iclass 20, count 0 2006.260.08:21:31.70#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.260.08:21:31.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:21:31.70#ibcon#*before write, iclass 20, count 0 2006.260.08:21:31.70#ibcon#enter sib2, iclass 20, count 0 2006.260.08:21:31.70#ibcon#flushed, iclass 20, count 0 2006.260.08:21:31.70#ibcon#about to write, iclass 20, count 0 2006.260.08:21:31.70#ibcon#wrote, iclass 20, count 0 2006.260.08:21:31.70#ibcon#about to read 3, iclass 20, count 0 2006.260.08:21:31.74#ibcon#read 3, iclass 20, count 0 2006.260.08:21:31.74#ibcon#about to read 4, iclass 20, count 0 2006.260.08:21:31.74#ibcon#read 4, iclass 20, count 0 2006.260.08:21:31.74#ibcon#about to read 5, iclass 20, count 0 2006.260.08:21:31.74#ibcon#read 5, iclass 20, count 0 2006.260.08:21:31.74#ibcon#about to read 6, iclass 20, count 0 2006.260.08:21:31.74#ibcon#read 6, iclass 20, count 0 2006.260.08:21:31.74#ibcon#end of sib2, iclass 20, count 0 2006.260.08:21:31.74#ibcon#*after write, iclass 20, count 0 2006.260.08:21:31.74#ibcon#*before return 0, iclass 20, count 0 2006.260.08:21:31.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:21:31.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.260.08:21:31.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.260.08:21:31.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.260.08:21:31.74$vc4f8/va=8,6 2006.260.08:21:31.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.260.08:21:31.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.260.08:21:31.74#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:31.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:21:31.80#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:21:31.80#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:21:31.80#ibcon#enter wrdev, iclass 22, count 2 2006.260.08:21:31.80#ibcon#first serial, iclass 22, count 2 2006.260.08:21:31.80#ibcon#enter sib2, iclass 22, count 2 2006.260.08:21:31.80#ibcon#flushed, iclass 22, count 2 2006.260.08:21:31.80#ibcon#about to write, iclass 22, count 2 2006.260.08:21:31.80#ibcon#wrote, iclass 22, count 2 2006.260.08:21:31.80#ibcon#about to read 3, iclass 22, count 2 2006.260.08:21:31.82#ibcon#read 3, iclass 22, count 2 2006.260.08:21:31.82#ibcon#about to read 4, iclass 22, count 2 2006.260.08:21:31.82#ibcon#read 4, iclass 22, count 2 2006.260.08:21:31.82#ibcon#about to read 5, iclass 22, count 2 2006.260.08:21:31.82#ibcon#read 5, iclass 22, count 2 2006.260.08:21:31.82#ibcon#about to read 6, iclass 22, count 2 2006.260.08:21:31.82#ibcon#read 6, iclass 22, count 2 2006.260.08:21:31.82#ibcon#end of sib2, iclass 22, count 2 2006.260.08:21:31.82#ibcon#*mode == 0, iclass 22, count 2 2006.260.08:21:31.82#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.260.08:21:31.82#ibcon#[25=AT08-06\r\n] 2006.260.08:21:31.82#ibcon#*before write, iclass 22, count 2 2006.260.08:21:31.82#ibcon#enter sib2, iclass 22, count 2 2006.260.08:21:31.82#ibcon#flushed, iclass 22, count 2 2006.260.08:21:31.82#ibcon#about to write, iclass 22, count 2 2006.260.08:21:31.82#ibcon#wrote, iclass 22, count 2 2006.260.08:21:31.82#ibcon#about to read 3, iclass 22, count 2 2006.260.08:21:31.85#ibcon#read 3, iclass 22, count 2 2006.260.08:21:31.85#ibcon#about to read 4, iclass 22, count 2 2006.260.08:21:31.85#ibcon#read 4, iclass 22, count 2 2006.260.08:21:31.85#ibcon#about to read 5, iclass 22, count 2 2006.260.08:21:31.85#ibcon#read 5, iclass 22, count 2 2006.260.08:21:31.85#ibcon#about to read 6, iclass 22, count 2 2006.260.08:21:31.85#ibcon#read 6, iclass 22, count 2 2006.260.08:21:31.85#ibcon#end of sib2, iclass 22, count 2 2006.260.08:21:31.85#ibcon#*after write, iclass 22, count 2 2006.260.08:21:31.85#ibcon#*before return 0, iclass 22, count 2 2006.260.08:21:31.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:21:31.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.260.08:21:31.85#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.260.08:21:31.85#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:31.85#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:21:31.97#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:21:31.97#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:21:31.97#ibcon#enter wrdev, iclass 22, count 0 2006.260.08:21:31.97#ibcon#first serial, iclass 22, count 0 2006.260.08:21:31.97#ibcon#enter sib2, iclass 22, count 0 2006.260.08:21:31.97#ibcon#flushed, iclass 22, count 0 2006.260.08:21:31.97#ibcon#about to write, iclass 22, count 0 2006.260.08:21:31.97#ibcon#wrote, iclass 22, count 0 2006.260.08:21:31.97#ibcon#about to read 3, iclass 22, count 0 2006.260.08:21:31.99#ibcon#read 3, iclass 22, count 0 2006.260.08:21:31.99#ibcon#about to read 4, iclass 22, count 0 2006.260.08:21:31.99#ibcon#read 4, iclass 22, count 0 2006.260.08:21:31.99#ibcon#about to read 5, iclass 22, count 0 2006.260.08:21:31.99#ibcon#read 5, iclass 22, count 0 2006.260.08:21:31.99#ibcon#about to read 6, iclass 22, count 0 2006.260.08:21:31.99#ibcon#read 6, iclass 22, count 0 2006.260.08:21:31.99#ibcon#end of sib2, iclass 22, count 0 2006.260.08:21:31.99#ibcon#*mode == 0, iclass 22, count 0 2006.260.08:21:31.99#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.260.08:21:31.99#ibcon#[25=USB\r\n] 2006.260.08:21:31.99#ibcon#*before write, iclass 22, count 0 2006.260.08:21:31.99#ibcon#enter sib2, iclass 22, count 0 2006.260.08:21:31.99#ibcon#flushed, iclass 22, count 0 2006.260.08:21:31.99#ibcon#about to write, iclass 22, count 0 2006.260.08:21:31.99#ibcon#wrote, iclass 22, count 0 2006.260.08:21:31.99#ibcon#about to read 3, iclass 22, count 0 2006.260.08:21:32.02#ibcon#read 3, iclass 22, count 0 2006.260.08:21:32.02#ibcon#about to read 4, iclass 22, count 0 2006.260.08:21:32.02#ibcon#read 4, iclass 22, count 0 2006.260.08:21:32.02#ibcon#about to read 5, iclass 22, count 0 2006.260.08:21:32.02#ibcon#read 5, iclass 22, count 0 2006.260.08:21:32.02#ibcon#about to read 6, iclass 22, count 0 2006.260.08:21:32.02#ibcon#read 6, iclass 22, count 0 2006.260.08:21:32.02#ibcon#end of sib2, iclass 22, count 0 2006.260.08:21:32.02#ibcon#*after write, iclass 22, count 0 2006.260.08:21:32.02#ibcon#*before return 0, iclass 22, count 0 2006.260.08:21:32.02#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:21:32.02#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.260.08:21:32.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.260.08:21:32.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.260.08:21:32.02$vc4f8/vblo=1,632.99 2006.260.08:21:32.02#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.260.08:21:32.02#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.260.08:21:32.02#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:32.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:21:32.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:21:32.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:21:32.02#ibcon#enter wrdev, iclass 24, count 0 2006.260.08:21:32.02#ibcon#first serial, iclass 24, count 0 2006.260.08:21:32.02#ibcon#enter sib2, iclass 24, count 0 2006.260.08:21:32.02#ibcon#flushed, iclass 24, count 0 2006.260.08:21:32.02#ibcon#about to write, iclass 24, count 0 2006.260.08:21:32.02#ibcon#wrote, iclass 24, count 0 2006.260.08:21:32.02#ibcon#about to read 3, iclass 24, count 0 2006.260.08:21:32.04#ibcon#read 3, iclass 24, count 0 2006.260.08:21:32.04#ibcon#about to read 4, iclass 24, count 0 2006.260.08:21:32.04#ibcon#read 4, iclass 24, count 0 2006.260.08:21:32.04#ibcon#about to read 5, iclass 24, count 0 2006.260.08:21:32.04#ibcon#read 5, iclass 24, count 0 2006.260.08:21:32.04#ibcon#about to read 6, iclass 24, count 0 2006.260.08:21:32.04#ibcon#read 6, iclass 24, count 0 2006.260.08:21:32.04#ibcon#end of sib2, iclass 24, count 0 2006.260.08:21:32.04#ibcon#*mode == 0, iclass 24, count 0 2006.260.08:21:32.04#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.260.08:21:32.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:21:32.04#ibcon#*before write, iclass 24, count 0 2006.260.08:21:32.04#ibcon#enter sib2, iclass 24, count 0 2006.260.08:21:32.04#ibcon#flushed, iclass 24, count 0 2006.260.08:21:32.04#ibcon#about to write, iclass 24, count 0 2006.260.08:21:32.04#ibcon#wrote, iclass 24, count 0 2006.260.08:21:32.04#ibcon#about to read 3, iclass 24, count 0 2006.260.08:21:32.08#ibcon#read 3, iclass 24, count 0 2006.260.08:21:32.08#ibcon#about to read 4, iclass 24, count 0 2006.260.08:21:32.08#ibcon#read 4, iclass 24, count 0 2006.260.08:21:32.08#ibcon#about to read 5, iclass 24, count 0 2006.260.08:21:32.08#ibcon#read 5, iclass 24, count 0 2006.260.08:21:32.08#ibcon#about to read 6, iclass 24, count 0 2006.260.08:21:32.08#ibcon#read 6, iclass 24, count 0 2006.260.08:21:32.08#ibcon#end of sib2, iclass 24, count 0 2006.260.08:21:32.08#ibcon#*after write, iclass 24, count 0 2006.260.08:21:32.08#ibcon#*before return 0, iclass 24, count 0 2006.260.08:21:32.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:21:32.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.260.08:21:32.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.260.08:21:32.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.260.08:21:32.08$vc4f8/vb=1,4 2006.260.08:21:32.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.260.08:21:32.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.260.08:21:32.08#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:32.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:21:32.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:21:32.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:21:32.08#ibcon#enter wrdev, iclass 26, count 2 2006.260.08:21:32.08#ibcon#first serial, iclass 26, count 2 2006.260.08:21:32.08#ibcon#enter sib2, iclass 26, count 2 2006.260.08:21:32.08#ibcon#flushed, iclass 26, count 2 2006.260.08:21:32.08#ibcon#about to write, iclass 26, count 2 2006.260.08:21:32.08#ibcon#wrote, iclass 26, count 2 2006.260.08:21:32.08#ibcon#about to read 3, iclass 26, count 2 2006.260.08:21:32.10#ibcon#read 3, iclass 26, count 2 2006.260.08:21:32.10#ibcon#about to read 4, iclass 26, count 2 2006.260.08:21:32.10#ibcon#read 4, iclass 26, count 2 2006.260.08:21:32.10#ibcon#about to read 5, iclass 26, count 2 2006.260.08:21:32.10#ibcon#read 5, iclass 26, count 2 2006.260.08:21:32.10#ibcon#about to read 6, iclass 26, count 2 2006.260.08:21:32.10#ibcon#read 6, iclass 26, count 2 2006.260.08:21:32.10#ibcon#end of sib2, iclass 26, count 2 2006.260.08:21:32.10#ibcon#*mode == 0, iclass 26, count 2 2006.260.08:21:32.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.260.08:21:32.10#ibcon#[27=AT01-04\r\n] 2006.260.08:21:32.10#ibcon#*before write, iclass 26, count 2 2006.260.08:21:32.10#ibcon#enter sib2, iclass 26, count 2 2006.260.08:21:32.10#ibcon#flushed, iclass 26, count 2 2006.260.08:21:32.10#ibcon#about to write, iclass 26, count 2 2006.260.08:21:32.10#ibcon#wrote, iclass 26, count 2 2006.260.08:21:32.10#ibcon#about to read 3, iclass 26, count 2 2006.260.08:21:32.13#ibcon#read 3, iclass 26, count 2 2006.260.08:21:32.13#ibcon#about to read 4, iclass 26, count 2 2006.260.08:21:32.13#ibcon#read 4, iclass 26, count 2 2006.260.08:21:32.13#ibcon#about to read 5, iclass 26, count 2 2006.260.08:21:32.13#ibcon#read 5, iclass 26, count 2 2006.260.08:21:32.13#ibcon#about to read 6, iclass 26, count 2 2006.260.08:21:32.13#ibcon#read 6, iclass 26, count 2 2006.260.08:21:32.13#ibcon#end of sib2, iclass 26, count 2 2006.260.08:21:32.13#ibcon#*after write, iclass 26, count 2 2006.260.08:21:32.13#ibcon#*before return 0, iclass 26, count 2 2006.260.08:21:32.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:21:32.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.260.08:21:32.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.260.08:21:32.13#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:32.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:21:32.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:21:32.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:21:32.25#ibcon#enter wrdev, iclass 26, count 0 2006.260.08:21:32.25#ibcon#first serial, iclass 26, count 0 2006.260.08:21:32.25#ibcon#enter sib2, iclass 26, count 0 2006.260.08:21:32.25#ibcon#flushed, iclass 26, count 0 2006.260.08:21:32.25#ibcon#about to write, iclass 26, count 0 2006.260.08:21:32.25#ibcon#wrote, iclass 26, count 0 2006.260.08:21:32.25#ibcon#about to read 3, iclass 26, count 0 2006.260.08:21:32.27#ibcon#read 3, iclass 26, count 0 2006.260.08:21:32.27#ibcon#about to read 4, iclass 26, count 0 2006.260.08:21:32.27#ibcon#read 4, iclass 26, count 0 2006.260.08:21:32.27#ibcon#about to read 5, iclass 26, count 0 2006.260.08:21:32.27#ibcon#read 5, iclass 26, count 0 2006.260.08:21:32.27#ibcon#about to read 6, iclass 26, count 0 2006.260.08:21:32.27#ibcon#read 6, iclass 26, count 0 2006.260.08:21:32.27#ibcon#end of sib2, iclass 26, count 0 2006.260.08:21:32.27#ibcon#*mode == 0, iclass 26, count 0 2006.260.08:21:32.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.260.08:21:32.27#ibcon#[27=USB\r\n] 2006.260.08:21:32.27#ibcon#*before write, iclass 26, count 0 2006.260.08:21:32.27#ibcon#enter sib2, iclass 26, count 0 2006.260.08:21:32.27#ibcon#flushed, iclass 26, count 0 2006.260.08:21:32.27#ibcon#about to write, iclass 26, count 0 2006.260.08:21:32.27#ibcon#wrote, iclass 26, count 0 2006.260.08:21:32.27#ibcon#about to read 3, iclass 26, count 0 2006.260.08:21:32.30#ibcon#read 3, iclass 26, count 0 2006.260.08:21:32.30#ibcon#about to read 4, iclass 26, count 0 2006.260.08:21:32.30#ibcon#read 4, iclass 26, count 0 2006.260.08:21:32.30#ibcon#about to read 5, iclass 26, count 0 2006.260.08:21:32.30#ibcon#read 5, iclass 26, count 0 2006.260.08:21:32.30#ibcon#about to read 6, iclass 26, count 0 2006.260.08:21:32.30#ibcon#read 6, iclass 26, count 0 2006.260.08:21:32.30#ibcon#end of sib2, iclass 26, count 0 2006.260.08:21:32.30#ibcon#*after write, iclass 26, count 0 2006.260.08:21:32.30#ibcon#*before return 0, iclass 26, count 0 2006.260.08:21:32.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:21:32.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.260.08:21:32.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.260.08:21:32.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.260.08:21:32.30$vc4f8/vblo=2,640.99 2006.260.08:21:32.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.260.08:21:32.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.260.08:21:32.30#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:32.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:32.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:32.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:32.30#ibcon#enter wrdev, iclass 28, count 0 2006.260.08:21:32.30#ibcon#first serial, iclass 28, count 0 2006.260.08:21:32.30#ibcon#enter sib2, iclass 28, count 0 2006.260.08:21:32.30#ibcon#flushed, iclass 28, count 0 2006.260.08:21:32.30#ibcon#about to write, iclass 28, count 0 2006.260.08:21:32.30#ibcon#wrote, iclass 28, count 0 2006.260.08:21:32.30#ibcon#about to read 3, iclass 28, count 0 2006.260.08:21:32.32#ibcon#read 3, iclass 28, count 0 2006.260.08:21:32.32#ibcon#about to read 4, iclass 28, count 0 2006.260.08:21:32.32#ibcon#read 4, iclass 28, count 0 2006.260.08:21:32.32#ibcon#about to read 5, iclass 28, count 0 2006.260.08:21:32.32#ibcon#read 5, iclass 28, count 0 2006.260.08:21:32.32#ibcon#about to read 6, iclass 28, count 0 2006.260.08:21:32.32#ibcon#read 6, iclass 28, count 0 2006.260.08:21:32.32#ibcon#end of sib2, iclass 28, count 0 2006.260.08:21:32.32#ibcon#*mode == 0, iclass 28, count 0 2006.260.08:21:32.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.260.08:21:32.32#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:21:32.32#ibcon#*before write, iclass 28, count 0 2006.260.08:21:32.32#ibcon#enter sib2, iclass 28, count 0 2006.260.08:21:32.32#ibcon#flushed, iclass 28, count 0 2006.260.08:21:32.32#ibcon#about to write, iclass 28, count 0 2006.260.08:21:32.32#ibcon#wrote, iclass 28, count 0 2006.260.08:21:32.32#ibcon#about to read 3, iclass 28, count 0 2006.260.08:21:32.36#ibcon#read 3, iclass 28, count 0 2006.260.08:21:32.36#ibcon#about to read 4, iclass 28, count 0 2006.260.08:21:32.36#ibcon#read 4, iclass 28, count 0 2006.260.08:21:32.36#ibcon#about to read 5, iclass 28, count 0 2006.260.08:21:32.36#ibcon#read 5, iclass 28, count 0 2006.260.08:21:32.36#ibcon#about to read 6, iclass 28, count 0 2006.260.08:21:32.36#ibcon#read 6, iclass 28, count 0 2006.260.08:21:32.36#ibcon#end of sib2, iclass 28, count 0 2006.260.08:21:32.36#ibcon#*after write, iclass 28, count 0 2006.260.08:21:32.36#ibcon#*before return 0, iclass 28, count 0 2006.260.08:21:32.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:32.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.260.08:21:32.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.260.08:21:32.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.260.08:21:32.36$vc4f8/vb=2,5 2006.260.08:21:32.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.260.08:21:32.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.260.08:21:32.36#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:32.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:32.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:32.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:32.42#ibcon#enter wrdev, iclass 30, count 2 2006.260.08:21:32.42#ibcon#first serial, iclass 30, count 2 2006.260.08:21:32.42#ibcon#enter sib2, iclass 30, count 2 2006.260.08:21:32.42#ibcon#flushed, iclass 30, count 2 2006.260.08:21:32.42#ibcon#about to write, iclass 30, count 2 2006.260.08:21:32.42#ibcon#wrote, iclass 30, count 2 2006.260.08:21:32.42#ibcon#about to read 3, iclass 30, count 2 2006.260.08:21:32.44#ibcon#read 3, iclass 30, count 2 2006.260.08:21:32.44#ibcon#about to read 4, iclass 30, count 2 2006.260.08:21:32.44#ibcon#read 4, iclass 30, count 2 2006.260.08:21:32.44#ibcon#about to read 5, iclass 30, count 2 2006.260.08:21:32.44#ibcon#read 5, iclass 30, count 2 2006.260.08:21:32.44#ibcon#about to read 6, iclass 30, count 2 2006.260.08:21:32.44#ibcon#read 6, iclass 30, count 2 2006.260.08:21:32.44#ibcon#end of sib2, iclass 30, count 2 2006.260.08:21:32.44#ibcon#*mode == 0, iclass 30, count 2 2006.260.08:21:32.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.260.08:21:32.44#ibcon#[27=AT02-05\r\n] 2006.260.08:21:32.44#ibcon#*before write, iclass 30, count 2 2006.260.08:21:32.44#ibcon#enter sib2, iclass 30, count 2 2006.260.08:21:32.44#ibcon#flushed, iclass 30, count 2 2006.260.08:21:32.44#ibcon#about to write, iclass 30, count 2 2006.260.08:21:32.44#ibcon#wrote, iclass 30, count 2 2006.260.08:21:32.44#ibcon#about to read 3, iclass 30, count 2 2006.260.08:21:32.47#ibcon#read 3, iclass 30, count 2 2006.260.08:21:32.47#ibcon#about to read 4, iclass 30, count 2 2006.260.08:21:32.47#ibcon#read 4, iclass 30, count 2 2006.260.08:21:32.47#ibcon#about to read 5, iclass 30, count 2 2006.260.08:21:32.47#ibcon#read 5, iclass 30, count 2 2006.260.08:21:32.47#ibcon#about to read 6, iclass 30, count 2 2006.260.08:21:32.47#ibcon#read 6, iclass 30, count 2 2006.260.08:21:32.47#ibcon#end of sib2, iclass 30, count 2 2006.260.08:21:32.47#ibcon#*after write, iclass 30, count 2 2006.260.08:21:32.47#ibcon#*before return 0, iclass 30, count 2 2006.260.08:21:32.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:32.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.260.08:21:32.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.260.08:21:32.47#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:32.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:32.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:32.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:32.59#ibcon#enter wrdev, iclass 30, count 0 2006.260.08:21:32.59#ibcon#first serial, iclass 30, count 0 2006.260.08:21:32.59#ibcon#enter sib2, iclass 30, count 0 2006.260.08:21:32.59#ibcon#flushed, iclass 30, count 0 2006.260.08:21:32.59#ibcon#about to write, iclass 30, count 0 2006.260.08:21:32.59#ibcon#wrote, iclass 30, count 0 2006.260.08:21:32.59#ibcon#about to read 3, iclass 30, count 0 2006.260.08:21:32.61#ibcon#read 3, iclass 30, count 0 2006.260.08:21:32.61#ibcon#about to read 4, iclass 30, count 0 2006.260.08:21:32.61#ibcon#read 4, iclass 30, count 0 2006.260.08:21:32.61#ibcon#about to read 5, iclass 30, count 0 2006.260.08:21:32.61#ibcon#read 5, iclass 30, count 0 2006.260.08:21:32.61#ibcon#about to read 6, iclass 30, count 0 2006.260.08:21:32.61#ibcon#read 6, iclass 30, count 0 2006.260.08:21:32.61#ibcon#end of sib2, iclass 30, count 0 2006.260.08:21:32.61#ibcon#*mode == 0, iclass 30, count 0 2006.260.08:21:32.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.260.08:21:32.61#ibcon#[27=USB\r\n] 2006.260.08:21:32.61#ibcon#*before write, iclass 30, count 0 2006.260.08:21:32.61#ibcon#enter sib2, iclass 30, count 0 2006.260.08:21:32.61#ibcon#flushed, iclass 30, count 0 2006.260.08:21:32.61#ibcon#about to write, iclass 30, count 0 2006.260.08:21:32.61#ibcon#wrote, iclass 30, count 0 2006.260.08:21:32.61#ibcon#about to read 3, iclass 30, count 0 2006.260.08:21:32.64#ibcon#read 3, iclass 30, count 0 2006.260.08:21:32.64#ibcon#about to read 4, iclass 30, count 0 2006.260.08:21:32.64#ibcon#read 4, iclass 30, count 0 2006.260.08:21:32.64#ibcon#about to read 5, iclass 30, count 0 2006.260.08:21:32.64#ibcon#read 5, iclass 30, count 0 2006.260.08:21:32.64#ibcon#about to read 6, iclass 30, count 0 2006.260.08:21:32.64#ibcon#read 6, iclass 30, count 0 2006.260.08:21:32.64#ibcon#end of sib2, iclass 30, count 0 2006.260.08:21:32.64#ibcon#*after write, iclass 30, count 0 2006.260.08:21:32.64#ibcon#*before return 0, iclass 30, count 0 2006.260.08:21:32.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:32.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.260.08:21:32.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.260.08:21:32.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.260.08:21:32.64$vc4f8/vblo=3,656.99 2006.260.08:21:32.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.260.08:21:32.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.260.08:21:32.64#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:32.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:32.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:32.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:32.64#ibcon#enter wrdev, iclass 32, count 0 2006.260.08:21:32.64#ibcon#first serial, iclass 32, count 0 2006.260.08:21:32.64#ibcon#enter sib2, iclass 32, count 0 2006.260.08:21:32.64#ibcon#flushed, iclass 32, count 0 2006.260.08:21:32.64#ibcon#about to write, iclass 32, count 0 2006.260.08:21:32.64#ibcon#wrote, iclass 32, count 0 2006.260.08:21:32.64#ibcon#about to read 3, iclass 32, count 0 2006.260.08:21:32.66#ibcon#read 3, iclass 32, count 0 2006.260.08:21:32.66#ibcon#about to read 4, iclass 32, count 0 2006.260.08:21:32.66#ibcon#read 4, iclass 32, count 0 2006.260.08:21:32.66#ibcon#about to read 5, iclass 32, count 0 2006.260.08:21:32.66#ibcon#read 5, iclass 32, count 0 2006.260.08:21:32.66#ibcon#about to read 6, iclass 32, count 0 2006.260.08:21:32.66#ibcon#read 6, iclass 32, count 0 2006.260.08:21:32.66#ibcon#end of sib2, iclass 32, count 0 2006.260.08:21:32.66#ibcon#*mode == 0, iclass 32, count 0 2006.260.08:21:32.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.260.08:21:32.66#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:21:32.66#ibcon#*before write, iclass 32, count 0 2006.260.08:21:32.66#ibcon#enter sib2, iclass 32, count 0 2006.260.08:21:32.66#ibcon#flushed, iclass 32, count 0 2006.260.08:21:32.66#ibcon#about to write, iclass 32, count 0 2006.260.08:21:32.66#ibcon#wrote, iclass 32, count 0 2006.260.08:21:32.66#ibcon#about to read 3, iclass 32, count 0 2006.260.08:21:32.70#ibcon#read 3, iclass 32, count 0 2006.260.08:21:32.70#ibcon#about to read 4, iclass 32, count 0 2006.260.08:21:32.70#ibcon#read 4, iclass 32, count 0 2006.260.08:21:32.70#ibcon#about to read 5, iclass 32, count 0 2006.260.08:21:32.70#ibcon#read 5, iclass 32, count 0 2006.260.08:21:32.70#ibcon#about to read 6, iclass 32, count 0 2006.260.08:21:32.70#ibcon#read 6, iclass 32, count 0 2006.260.08:21:32.70#ibcon#end of sib2, iclass 32, count 0 2006.260.08:21:32.70#ibcon#*after write, iclass 32, count 0 2006.260.08:21:32.70#ibcon#*before return 0, iclass 32, count 0 2006.260.08:21:32.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:32.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.260.08:21:32.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.260.08:21:32.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.260.08:21:32.70$vc4f8/vb=3,4 2006.260.08:21:32.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.260.08:21:32.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.260.08:21:32.70#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:32.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:32.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:32.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:32.76#ibcon#enter wrdev, iclass 34, count 2 2006.260.08:21:32.76#ibcon#first serial, iclass 34, count 2 2006.260.08:21:32.76#ibcon#enter sib2, iclass 34, count 2 2006.260.08:21:32.76#ibcon#flushed, iclass 34, count 2 2006.260.08:21:32.76#ibcon#about to write, iclass 34, count 2 2006.260.08:21:32.76#ibcon#wrote, iclass 34, count 2 2006.260.08:21:32.76#ibcon#about to read 3, iclass 34, count 2 2006.260.08:21:32.78#ibcon#read 3, iclass 34, count 2 2006.260.08:21:32.78#ibcon#about to read 4, iclass 34, count 2 2006.260.08:21:32.78#ibcon#read 4, iclass 34, count 2 2006.260.08:21:32.78#ibcon#about to read 5, iclass 34, count 2 2006.260.08:21:32.78#ibcon#read 5, iclass 34, count 2 2006.260.08:21:32.78#ibcon#about to read 6, iclass 34, count 2 2006.260.08:21:32.78#ibcon#read 6, iclass 34, count 2 2006.260.08:21:32.78#ibcon#end of sib2, iclass 34, count 2 2006.260.08:21:32.78#ibcon#*mode == 0, iclass 34, count 2 2006.260.08:21:32.78#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.260.08:21:32.78#ibcon#[27=AT03-04\r\n] 2006.260.08:21:32.78#ibcon#*before write, iclass 34, count 2 2006.260.08:21:32.78#ibcon#enter sib2, iclass 34, count 2 2006.260.08:21:32.78#ibcon#flushed, iclass 34, count 2 2006.260.08:21:32.78#ibcon#about to write, iclass 34, count 2 2006.260.08:21:32.78#ibcon#wrote, iclass 34, count 2 2006.260.08:21:32.78#ibcon#about to read 3, iclass 34, count 2 2006.260.08:21:32.81#ibcon#read 3, iclass 34, count 2 2006.260.08:21:32.81#ibcon#about to read 4, iclass 34, count 2 2006.260.08:21:32.81#ibcon#read 4, iclass 34, count 2 2006.260.08:21:32.81#ibcon#about to read 5, iclass 34, count 2 2006.260.08:21:32.81#ibcon#read 5, iclass 34, count 2 2006.260.08:21:32.81#ibcon#about to read 6, iclass 34, count 2 2006.260.08:21:32.81#ibcon#read 6, iclass 34, count 2 2006.260.08:21:32.81#ibcon#end of sib2, iclass 34, count 2 2006.260.08:21:32.81#ibcon#*after write, iclass 34, count 2 2006.260.08:21:32.81#ibcon#*before return 0, iclass 34, count 2 2006.260.08:21:32.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:32.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.260.08:21:32.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.260.08:21:32.81#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:32.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:32.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:32.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:32.93#ibcon#enter wrdev, iclass 34, count 0 2006.260.08:21:32.93#ibcon#first serial, iclass 34, count 0 2006.260.08:21:32.93#ibcon#enter sib2, iclass 34, count 0 2006.260.08:21:32.93#ibcon#flushed, iclass 34, count 0 2006.260.08:21:32.93#ibcon#about to write, iclass 34, count 0 2006.260.08:21:32.93#ibcon#wrote, iclass 34, count 0 2006.260.08:21:32.93#ibcon#about to read 3, iclass 34, count 0 2006.260.08:21:32.95#ibcon#read 3, iclass 34, count 0 2006.260.08:21:32.95#ibcon#about to read 4, iclass 34, count 0 2006.260.08:21:32.95#ibcon#read 4, iclass 34, count 0 2006.260.08:21:32.95#ibcon#about to read 5, iclass 34, count 0 2006.260.08:21:32.95#ibcon#read 5, iclass 34, count 0 2006.260.08:21:32.95#ibcon#about to read 6, iclass 34, count 0 2006.260.08:21:32.95#ibcon#read 6, iclass 34, count 0 2006.260.08:21:32.95#ibcon#end of sib2, iclass 34, count 0 2006.260.08:21:32.95#ibcon#*mode == 0, iclass 34, count 0 2006.260.08:21:32.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.260.08:21:32.95#ibcon#[27=USB\r\n] 2006.260.08:21:32.95#ibcon#*before write, iclass 34, count 0 2006.260.08:21:32.95#ibcon#enter sib2, iclass 34, count 0 2006.260.08:21:32.95#ibcon#flushed, iclass 34, count 0 2006.260.08:21:32.95#ibcon#about to write, iclass 34, count 0 2006.260.08:21:32.95#ibcon#wrote, iclass 34, count 0 2006.260.08:21:32.95#ibcon#about to read 3, iclass 34, count 0 2006.260.08:21:32.98#ibcon#read 3, iclass 34, count 0 2006.260.08:21:32.98#ibcon#about to read 4, iclass 34, count 0 2006.260.08:21:32.98#ibcon#read 4, iclass 34, count 0 2006.260.08:21:32.98#ibcon#about to read 5, iclass 34, count 0 2006.260.08:21:32.98#ibcon#read 5, iclass 34, count 0 2006.260.08:21:32.98#ibcon#about to read 6, iclass 34, count 0 2006.260.08:21:32.98#ibcon#read 6, iclass 34, count 0 2006.260.08:21:32.98#ibcon#end of sib2, iclass 34, count 0 2006.260.08:21:32.98#ibcon#*after write, iclass 34, count 0 2006.260.08:21:32.98#ibcon#*before return 0, iclass 34, count 0 2006.260.08:21:32.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:32.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.260.08:21:32.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.260.08:21:32.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.260.08:21:32.98$vc4f8/vblo=4,712.99 2006.260.08:21:32.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.260.08:21:32.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.260.08:21:32.98#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:32.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:32.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:32.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:32.98#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:21:32.98#ibcon#first serial, iclass 36, count 0 2006.260.08:21:32.98#ibcon#enter sib2, iclass 36, count 0 2006.260.08:21:32.98#ibcon#flushed, iclass 36, count 0 2006.260.08:21:32.98#ibcon#about to write, iclass 36, count 0 2006.260.08:21:32.98#ibcon#wrote, iclass 36, count 0 2006.260.08:21:32.98#ibcon#about to read 3, iclass 36, count 0 2006.260.08:21:33.00#ibcon#read 3, iclass 36, count 0 2006.260.08:21:33.00#ibcon#about to read 4, iclass 36, count 0 2006.260.08:21:33.00#ibcon#read 4, iclass 36, count 0 2006.260.08:21:33.00#ibcon#about to read 5, iclass 36, count 0 2006.260.08:21:33.00#ibcon#read 5, iclass 36, count 0 2006.260.08:21:33.00#ibcon#about to read 6, iclass 36, count 0 2006.260.08:21:33.00#ibcon#read 6, iclass 36, count 0 2006.260.08:21:33.00#ibcon#end of sib2, iclass 36, count 0 2006.260.08:21:33.00#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:21:33.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:21:33.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:21:33.00#ibcon#*before write, iclass 36, count 0 2006.260.08:21:33.00#ibcon#enter sib2, iclass 36, count 0 2006.260.08:21:33.00#ibcon#flushed, iclass 36, count 0 2006.260.08:21:33.00#ibcon#about to write, iclass 36, count 0 2006.260.08:21:33.00#ibcon#wrote, iclass 36, count 0 2006.260.08:21:33.00#ibcon#about to read 3, iclass 36, count 0 2006.260.08:21:33.04#ibcon#read 3, iclass 36, count 0 2006.260.08:21:33.04#ibcon#about to read 4, iclass 36, count 0 2006.260.08:21:33.04#ibcon#read 4, iclass 36, count 0 2006.260.08:21:33.04#ibcon#about to read 5, iclass 36, count 0 2006.260.08:21:33.04#ibcon#read 5, iclass 36, count 0 2006.260.08:21:33.04#ibcon#about to read 6, iclass 36, count 0 2006.260.08:21:33.04#ibcon#read 6, iclass 36, count 0 2006.260.08:21:33.04#ibcon#end of sib2, iclass 36, count 0 2006.260.08:21:33.04#ibcon#*after write, iclass 36, count 0 2006.260.08:21:33.04#ibcon#*before return 0, iclass 36, count 0 2006.260.08:21:33.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:33.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.260.08:21:33.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:21:33.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:21:33.04$vc4f8/vb=4,5 2006.260.08:21:33.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.260.08:21:33.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.260.08:21:33.04#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:33.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:33.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:33.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:33.10#ibcon#enter wrdev, iclass 38, count 2 2006.260.08:21:33.10#ibcon#first serial, iclass 38, count 2 2006.260.08:21:33.10#ibcon#enter sib2, iclass 38, count 2 2006.260.08:21:33.10#ibcon#flushed, iclass 38, count 2 2006.260.08:21:33.10#ibcon#about to write, iclass 38, count 2 2006.260.08:21:33.10#ibcon#wrote, iclass 38, count 2 2006.260.08:21:33.10#ibcon#about to read 3, iclass 38, count 2 2006.260.08:21:33.12#ibcon#read 3, iclass 38, count 2 2006.260.08:21:33.12#ibcon#about to read 4, iclass 38, count 2 2006.260.08:21:33.12#ibcon#read 4, iclass 38, count 2 2006.260.08:21:33.12#ibcon#about to read 5, iclass 38, count 2 2006.260.08:21:33.12#ibcon#read 5, iclass 38, count 2 2006.260.08:21:33.12#ibcon#about to read 6, iclass 38, count 2 2006.260.08:21:33.12#ibcon#read 6, iclass 38, count 2 2006.260.08:21:33.12#ibcon#end of sib2, iclass 38, count 2 2006.260.08:21:33.12#ibcon#*mode == 0, iclass 38, count 2 2006.260.08:21:33.12#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.260.08:21:33.12#ibcon#[27=AT04-05\r\n] 2006.260.08:21:33.12#ibcon#*before write, iclass 38, count 2 2006.260.08:21:33.12#ibcon#enter sib2, iclass 38, count 2 2006.260.08:21:33.12#ibcon#flushed, iclass 38, count 2 2006.260.08:21:33.12#ibcon#about to write, iclass 38, count 2 2006.260.08:21:33.12#ibcon#wrote, iclass 38, count 2 2006.260.08:21:33.12#ibcon#about to read 3, iclass 38, count 2 2006.260.08:21:33.15#ibcon#read 3, iclass 38, count 2 2006.260.08:21:33.15#ibcon#about to read 4, iclass 38, count 2 2006.260.08:21:33.15#ibcon#read 4, iclass 38, count 2 2006.260.08:21:33.15#ibcon#about to read 5, iclass 38, count 2 2006.260.08:21:33.15#ibcon#read 5, iclass 38, count 2 2006.260.08:21:33.15#ibcon#about to read 6, iclass 38, count 2 2006.260.08:21:33.15#ibcon#read 6, iclass 38, count 2 2006.260.08:21:33.15#ibcon#end of sib2, iclass 38, count 2 2006.260.08:21:33.15#ibcon#*after write, iclass 38, count 2 2006.260.08:21:33.15#ibcon#*before return 0, iclass 38, count 2 2006.260.08:21:33.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:33.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.260.08:21:33.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.260.08:21:33.15#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:33.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:33.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:33.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:33.27#ibcon#enter wrdev, iclass 38, count 0 2006.260.08:21:33.27#ibcon#first serial, iclass 38, count 0 2006.260.08:21:33.27#ibcon#enter sib2, iclass 38, count 0 2006.260.08:21:33.27#ibcon#flushed, iclass 38, count 0 2006.260.08:21:33.27#ibcon#about to write, iclass 38, count 0 2006.260.08:21:33.27#ibcon#wrote, iclass 38, count 0 2006.260.08:21:33.27#ibcon#about to read 3, iclass 38, count 0 2006.260.08:21:33.29#ibcon#read 3, iclass 38, count 0 2006.260.08:21:33.29#ibcon#about to read 4, iclass 38, count 0 2006.260.08:21:33.29#ibcon#read 4, iclass 38, count 0 2006.260.08:21:33.29#ibcon#about to read 5, iclass 38, count 0 2006.260.08:21:33.29#ibcon#read 5, iclass 38, count 0 2006.260.08:21:33.29#ibcon#about to read 6, iclass 38, count 0 2006.260.08:21:33.29#ibcon#read 6, iclass 38, count 0 2006.260.08:21:33.29#ibcon#end of sib2, iclass 38, count 0 2006.260.08:21:33.29#ibcon#*mode == 0, iclass 38, count 0 2006.260.08:21:33.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.260.08:21:33.29#ibcon#[27=USB\r\n] 2006.260.08:21:33.29#ibcon#*before write, iclass 38, count 0 2006.260.08:21:33.29#ibcon#enter sib2, iclass 38, count 0 2006.260.08:21:33.29#ibcon#flushed, iclass 38, count 0 2006.260.08:21:33.29#ibcon#about to write, iclass 38, count 0 2006.260.08:21:33.29#ibcon#wrote, iclass 38, count 0 2006.260.08:21:33.29#ibcon#about to read 3, iclass 38, count 0 2006.260.08:21:33.32#ibcon#read 3, iclass 38, count 0 2006.260.08:21:33.32#ibcon#about to read 4, iclass 38, count 0 2006.260.08:21:33.32#ibcon#read 4, iclass 38, count 0 2006.260.08:21:33.32#ibcon#about to read 5, iclass 38, count 0 2006.260.08:21:33.32#ibcon#read 5, iclass 38, count 0 2006.260.08:21:33.32#ibcon#about to read 6, iclass 38, count 0 2006.260.08:21:33.32#ibcon#read 6, iclass 38, count 0 2006.260.08:21:33.32#ibcon#end of sib2, iclass 38, count 0 2006.260.08:21:33.32#ibcon#*after write, iclass 38, count 0 2006.260.08:21:33.32#ibcon#*before return 0, iclass 38, count 0 2006.260.08:21:33.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:33.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.260.08:21:33.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.260.08:21:33.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.260.08:21:33.32$vc4f8/vblo=5,744.99 2006.260.08:21:33.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.260.08:21:33.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.260.08:21:33.32#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:33.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:33.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:33.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:33.32#ibcon#enter wrdev, iclass 40, count 0 2006.260.08:21:33.32#ibcon#first serial, iclass 40, count 0 2006.260.08:21:33.32#ibcon#enter sib2, iclass 40, count 0 2006.260.08:21:33.32#ibcon#flushed, iclass 40, count 0 2006.260.08:21:33.32#ibcon#about to write, iclass 40, count 0 2006.260.08:21:33.32#ibcon#wrote, iclass 40, count 0 2006.260.08:21:33.32#ibcon#about to read 3, iclass 40, count 0 2006.260.08:21:33.34#ibcon#read 3, iclass 40, count 0 2006.260.08:21:33.34#ibcon#about to read 4, iclass 40, count 0 2006.260.08:21:33.34#ibcon#read 4, iclass 40, count 0 2006.260.08:21:33.34#ibcon#about to read 5, iclass 40, count 0 2006.260.08:21:33.34#ibcon#read 5, iclass 40, count 0 2006.260.08:21:33.34#ibcon#about to read 6, iclass 40, count 0 2006.260.08:21:33.34#ibcon#read 6, iclass 40, count 0 2006.260.08:21:33.34#ibcon#end of sib2, iclass 40, count 0 2006.260.08:21:33.34#ibcon#*mode == 0, iclass 40, count 0 2006.260.08:21:33.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.260.08:21:33.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:21:33.34#ibcon#*before write, iclass 40, count 0 2006.260.08:21:33.34#ibcon#enter sib2, iclass 40, count 0 2006.260.08:21:33.34#ibcon#flushed, iclass 40, count 0 2006.260.08:21:33.34#ibcon#about to write, iclass 40, count 0 2006.260.08:21:33.34#ibcon#wrote, iclass 40, count 0 2006.260.08:21:33.34#ibcon#about to read 3, iclass 40, count 0 2006.260.08:21:33.38#ibcon#read 3, iclass 40, count 0 2006.260.08:21:33.38#ibcon#about to read 4, iclass 40, count 0 2006.260.08:21:33.38#ibcon#read 4, iclass 40, count 0 2006.260.08:21:33.38#ibcon#about to read 5, iclass 40, count 0 2006.260.08:21:33.38#ibcon#read 5, iclass 40, count 0 2006.260.08:21:33.38#ibcon#about to read 6, iclass 40, count 0 2006.260.08:21:33.38#ibcon#read 6, iclass 40, count 0 2006.260.08:21:33.38#ibcon#end of sib2, iclass 40, count 0 2006.260.08:21:33.38#ibcon#*after write, iclass 40, count 0 2006.260.08:21:33.38#ibcon#*before return 0, iclass 40, count 0 2006.260.08:21:33.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:33.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.260.08:21:33.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.260.08:21:33.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.260.08:21:33.38$vc4f8/vb=5,4 2006.260.08:21:33.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.260.08:21:33.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.260.08:21:33.38#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:33.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:33.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:33.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:33.44#ibcon#enter wrdev, iclass 4, count 2 2006.260.08:21:33.44#ibcon#first serial, iclass 4, count 2 2006.260.08:21:33.44#ibcon#enter sib2, iclass 4, count 2 2006.260.08:21:33.44#ibcon#flushed, iclass 4, count 2 2006.260.08:21:33.44#ibcon#about to write, iclass 4, count 2 2006.260.08:21:33.44#ibcon#wrote, iclass 4, count 2 2006.260.08:21:33.44#ibcon#about to read 3, iclass 4, count 2 2006.260.08:21:33.46#ibcon#read 3, iclass 4, count 2 2006.260.08:21:33.46#ibcon#about to read 4, iclass 4, count 2 2006.260.08:21:33.46#ibcon#read 4, iclass 4, count 2 2006.260.08:21:33.46#ibcon#about to read 5, iclass 4, count 2 2006.260.08:21:33.46#ibcon#read 5, iclass 4, count 2 2006.260.08:21:33.46#ibcon#about to read 6, iclass 4, count 2 2006.260.08:21:33.46#ibcon#read 6, iclass 4, count 2 2006.260.08:21:33.46#ibcon#end of sib2, iclass 4, count 2 2006.260.08:21:33.46#ibcon#*mode == 0, iclass 4, count 2 2006.260.08:21:33.46#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.260.08:21:33.46#ibcon#[27=AT05-04\r\n] 2006.260.08:21:33.46#ibcon#*before write, iclass 4, count 2 2006.260.08:21:33.46#ibcon#enter sib2, iclass 4, count 2 2006.260.08:21:33.46#ibcon#flushed, iclass 4, count 2 2006.260.08:21:33.46#ibcon#about to write, iclass 4, count 2 2006.260.08:21:33.46#ibcon#wrote, iclass 4, count 2 2006.260.08:21:33.46#ibcon#about to read 3, iclass 4, count 2 2006.260.08:21:33.49#ibcon#read 3, iclass 4, count 2 2006.260.08:21:33.49#ibcon#about to read 4, iclass 4, count 2 2006.260.08:21:33.49#ibcon#read 4, iclass 4, count 2 2006.260.08:21:33.49#ibcon#about to read 5, iclass 4, count 2 2006.260.08:21:33.49#ibcon#read 5, iclass 4, count 2 2006.260.08:21:33.49#ibcon#about to read 6, iclass 4, count 2 2006.260.08:21:33.49#ibcon#read 6, iclass 4, count 2 2006.260.08:21:33.49#ibcon#end of sib2, iclass 4, count 2 2006.260.08:21:33.49#ibcon#*after write, iclass 4, count 2 2006.260.08:21:33.49#ibcon#*before return 0, iclass 4, count 2 2006.260.08:21:33.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:33.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.260.08:21:33.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.260.08:21:33.49#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:33.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:33.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:33.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:33.61#ibcon#enter wrdev, iclass 4, count 0 2006.260.08:21:33.61#ibcon#first serial, iclass 4, count 0 2006.260.08:21:33.61#ibcon#enter sib2, iclass 4, count 0 2006.260.08:21:33.61#ibcon#flushed, iclass 4, count 0 2006.260.08:21:33.61#ibcon#about to write, iclass 4, count 0 2006.260.08:21:33.61#ibcon#wrote, iclass 4, count 0 2006.260.08:21:33.61#ibcon#about to read 3, iclass 4, count 0 2006.260.08:21:33.63#ibcon#read 3, iclass 4, count 0 2006.260.08:21:33.63#ibcon#about to read 4, iclass 4, count 0 2006.260.08:21:33.63#ibcon#read 4, iclass 4, count 0 2006.260.08:21:33.63#ibcon#about to read 5, iclass 4, count 0 2006.260.08:21:33.63#ibcon#read 5, iclass 4, count 0 2006.260.08:21:33.63#ibcon#about to read 6, iclass 4, count 0 2006.260.08:21:33.63#ibcon#read 6, iclass 4, count 0 2006.260.08:21:33.63#ibcon#end of sib2, iclass 4, count 0 2006.260.08:21:33.63#ibcon#*mode == 0, iclass 4, count 0 2006.260.08:21:33.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.260.08:21:33.63#ibcon#[27=USB\r\n] 2006.260.08:21:33.63#ibcon#*before write, iclass 4, count 0 2006.260.08:21:33.63#ibcon#enter sib2, iclass 4, count 0 2006.260.08:21:33.63#ibcon#flushed, iclass 4, count 0 2006.260.08:21:33.63#ibcon#about to write, iclass 4, count 0 2006.260.08:21:33.63#ibcon#wrote, iclass 4, count 0 2006.260.08:21:33.63#ibcon#about to read 3, iclass 4, count 0 2006.260.08:21:33.66#ibcon#read 3, iclass 4, count 0 2006.260.08:21:33.66#ibcon#about to read 4, iclass 4, count 0 2006.260.08:21:33.66#ibcon#read 4, iclass 4, count 0 2006.260.08:21:33.66#ibcon#about to read 5, iclass 4, count 0 2006.260.08:21:33.66#ibcon#read 5, iclass 4, count 0 2006.260.08:21:33.66#ibcon#about to read 6, iclass 4, count 0 2006.260.08:21:33.66#ibcon#read 6, iclass 4, count 0 2006.260.08:21:33.66#ibcon#end of sib2, iclass 4, count 0 2006.260.08:21:33.66#ibcon#*after write, iclass 4, count 0 2006.260.08:21:33.66#ibcon#*before return 0, iclass 4, count 0 2006.260.08:21:33.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:33.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.260.08:21:33.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.260.08:21:33.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.260.08:21:33.66$vc4f8/vblo=6,752.99 2006.260.08:21:33.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.260.08:21:33.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.260.08:21:33.66#ibcon#ireg 17 cls_cnt 0 2006.260.08:21:33.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:33.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:33.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:33.66#ibcon#enter wrdev, iclass 6, count 0 2006.260.08:21:33.66#ibcon#first serial, iclass 6, count 0 2006.260.08:21:33.66#ibcon#enter sib2, iclass 6, count 0 2006.260.08:21:33.66#ibcon#flushed, iclass 6, count 0 2006.260.08:21:33.66#ibcon#about to write, iclass 6, count 0 2006.260.08:21:33.66#ibcon#wrote, iclass 6, count 0 2006.260.08:21:33.66#ibcon#about to read 3, iclass 6, count 0 2006.260.08:21:33.68#ibcon#read 3, iclass 6, count 0 2006.260.08:21:33.68#ibcon#about to read 4, iclass 6, count 0 2006.260.08:21:33.68#ibcon#read 4, iclass 6, count 0 2006.260.08:21:33.68#ibcon#about to read 5, iclass 6, count 0 2006.260.08:21:33.68#ibcon#read 5, iclass 6, count 0 2006.260.08:21:33.68#ibcon#about to read 6, iclass 6, count 0 2006.260.08:21:33.68#ibcon#read 6, iclass 6, count 0 2006.260.08:21:33.68#ibcon#end of sib2, iclass 6, count 0 2006.260.08:21:33.68#ibcon#*mode == 0, iclass 6, count 0 2006.260.08:21:33.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.260.08:21:33.68#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:21:33.68#ibcon#*before write, iclass 6, count 0 2006.260.08:21:33.68#ibcon#enter sib2, iclass 6, count 0 2006.260.08:21:33.68#ibcon#flushed, iclass 6, count 0 2006.260.08:21:33.68#ibcon#about to write, iclass 6, count 0 2006.260.08:21:33.68#ibcon#wrote, iclass 6, count 0 2006.260.08:21:33.68#ibcon#about to read 3, iclass 6, count 0 2006.260.08:21:33.72#ibcon#read 3, iclass 6, count 0 2006.260.08:21:33.72#ibcon#about to read 4, iclass 6, count 0 2006.260.08:21:33.72#ibcon#read 4, iclass 6, count 0 2006.260.08:21:33.72#ibcon#about to read 5, iclass 6, count 0 2006.260.08:21:33.72#ibcon#read 5, iclass 6, count 0 2006.260.08:21:33.72#ibcon#about to read 6, iclass 6, count 0 2006.260.08:21:33.72#ibcon#read 6, iclass 6, count 0 2006.260.08:21:33.72#ibcon#end of sib2, iclass 6, count 0 2006.260.08:21:33.72#ibcon#*after write, iclass 6, count 0 2006.260.08:21:33.72#ibcon#*before return 0, iclass 6, count 0 2006.260.08:21:33.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:33.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.260.08:21:33.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.260.08:21:33.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.260.08:21:33.72$vc4f8/vb=6,4 2006.260.08:21:33.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.260.08:21:33.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.260.08:21:33.72#ibcon#ireg 11 cls_cnt 2 2006.260.08:21:33.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:33.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:33.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:33.78#ibcon#enter wrdev, iclass 10, count 2 2006.260.08:21:33.78#ibcon#first serial, iclass 10, count 2 2006.260.08:21:33.78#ibcon#enter sib2, iclass 10, count 2 2006.260.08:21:33.78#ibcon#flushed, iclass 10, count 2 2006.260.08:21:33.78#ibcon#about to write, iclass 10, count 2 2006.260.08:21:33.78#ibcon#wrote, iclass 10, count 2 2006.260.08:21:33.78#ibcon#about to read 3, iclass 10, count 2 2006.260.08:21:33.80#ibcon#read 3, iclass 10, count 2 2006.260.08:21:33.80#ibcon#about to read 4, iclass 10, count 2 2006.260.08:21:33.80#ibcon#read 4, iclass 10, count 2 2006.260.08:21:33.80#ibcon#about to read 5, iclass 10, count 2 2006.260.08:21:33.80#ibcon#read 5, iclass 10, count 2 2006.260.08:21:33.80#ibcon#about to read 6, iclass 10, count 2 2006.260.08:21:33.80#ibcon#read 6, iclass 10, count 2 2006.260.08:21:33.80#ibcon#end of sib2, iclass 10, count 2 2006.260.08:21:33.80#ibcon#*mode == 0, iclass 10, count 2 2006.260.08:21:33.80#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.260.08:21:33.80#ibcon#[27=AT06-04\r\n] 2006.260.08:21:33.80#ibcon#*before write, iclass 10, count 2 2006.260.08:21:33.80#ibcon#enter sib2, iclass 10, count 2 2006.260.08:21:33.80#ibcon#flushed, iclass 10, count 2 2006.260.08:21:33.80#ibcon#about to write, iclass 10, count 2 2006.260.08:21:33.80#ibcon#wrote, iclass 10, count 2 2006.260.08:21:33.80#ibcon#about to read 3, iclass 10, count 2 2006.260.08:21:33.83#ibcon#read 3, iclass 10, count 2 2006.260.08:21:33.83#ibcon#about to read 4, iclass 10, count 2 2006.260.08:21:33.83#ibcon#read 4, iclass 10, count 2 2006.260.08:21:33.83#ibcon#about to read 5, iclass 10, count 2 2006.260.08:21:33.83#ibcon#read 5, iclass 10, count 2 2006.260.08:21:33.83#ibcon#about to read 6, iclass 10, count 2 2006.260.08:21:33.83#ibcon#read 6, iclass 10, count 2 2006.260.08:21:33.83#ibcon#end of sib2, iclass 10, count 2 2006.260.08:21:33.83#ibcon#*after write, iclass 10, count 2 2006.260.08:21:33.83#ibcon#*before return 0, iclass 10, count 2 2006.260.08:21:33.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:33.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.260.08:21:33.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.260.08:21:33.83#ibcon#ireg 7 cls_cnt 0 2006.260.08:21:33.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:33.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:33.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:33.95#ibcon#enter wrdev, iclass 10, count 0 2006.260.08:21:33.95#ibcon#first serial, iclass 10, count 0 2006.260.08:21:33.95#ibcon#enter sib2, iclass 10, count 0 2006.260.08:21:33.95#ibcon#flushed, iclass 10, count 0 2006.260.08:21:33.95#ibcon#about to write, iclass 10, count 0 2006.260.08:21:33.95#ibcon#wrote, iclass 10, count 0 2006.260.08:21:33.95#ibcon#about to read 3, iclass 10, count 0 2006.260.08:21:33.97#ibcon#read 3, iclass 10, count 0 2006.260.08:21:33.97#ibcon#about to read 4, iclass 10, count 0 2006.260.08:21:33.97#ibcon#read 4, iclass 10, count 0 2006.260.08:21:33.97#ibcon#about to read 5, iclass 10, count 0 2006.260.08:21:33.97#ibcon#read 5, iclass 10, count 0 2006.260.08:21:33.97#ibcon#about to read 6, iclass 10, count 0 2006.260.08:21:33.97#ibcon#read 6, iclass 10, count 0 2006.260.08:21:33.97#ibcon#end of sib2, iclass 10, count 0 2006.260.08:21:33.97#ibcon#*mode == 0, iclass 10, count 0 2006.260.08:21:33.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.260.08:21:33.97#ibcon#[27=USB\r\n] 2006.260.08:21:33.97#ibcon#*before write, iclass 10, count 0 2006.260.08:21:33.97#ibcon#enter sib2, iclass 10, count 0 2006.260.08:21:33.97#ibcon#flushed, iclass 10, count 0 2006.260.08:21:33.97#ibcon#about to write, iclass 10, count 0 2006.260.08:21:33.97#ibcon#wrote, iclass 10, count 0 2006.260.08:21:33.97#ibcon#about to read 3, iclass 10, count 0 2006.260.08:21:34.00#ibcon#read 3, iclass 10, count 0 2006.260.08:21:34.00#ibcon#about to read 4, iclass 10, count 0 2006.260.08:21:34.00#ibcon#read 4, iclass 10, count 0 2006.260.08:21:34.00#ibcon#about to read 5, iclass 10, count 0 2006.260.08:21:34.00#ibcon#read 5, iclass 10, count 0 2006.260.08:21:34.00#ibcon#about to read 6, iclass 10, count 0 2006.260.08:21:34.00#ibcon#read 6, iclass 10, count 0 2006.260.08:21:34.00#ibcon#end of sib2, iclass 10, count 0 2006.260.08:21:34.00#ibcon#*after write, iclass 10, count 0 2006.260.08:21:34.00#ibcon#*before return 0, iclass 10, count 0 2006.260.08:21:34.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:34.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.260.08:21:34.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.260.08:21:34.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.260.08:21:34.00$vc4f8/vabw=wide 2006.260.08:21:34.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.260.08:21:34.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.260.08:21:34.00#ibcon#ireg 8 cls_cnt 0 2006.260.08:21:34.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:34.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:34.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:34.00#ibcon#enter wrdev, iclass 12, count 0 2006.260.08:21:34.00#ibcon#first serial, iclass 12, count 0 2006.260.08:21:34.00#ibcon#enter sib2, iclass 12, count 0 2006.260.08:21:34.00#ibcon#flushed, iclass 12, count 0 2006.260.08:21:34.00#ibcon#about to write, iclass 12, count 0 2006.260.08:21:34.00#ibcon#wrote, iclass 12, count 0 2006.260.08:21:34.00#ibcon#about to read 3, iclass 12, count 0 2006.260.08:21:34.02#ibcon#read 3, iclass 12, count 0 2006.260.08:21:34.02#ibcon#about to read 4, iclass 12, count 0 2006.260.08:21:34.02#ibcon#read 4, iclass 12, count 0 2006.260.08:21:34.02#ibcon#about to read 5, iclass 12, count 0 2006.260.08:21:34.02#ibcon#read 5, iclass 12, count 0 2006.260.08:21:34.02#ibcon#about to read 6, iclass 12, count 0 2006.260.08:21:34.02#ibcon#read 6, iclass 12, count 0 2006.260.08:21:34.02#ibcon#end of sib2, iclass 12, count 0 2006.260.08:21:34.02#ibcon#*mode == 0, iclass 12, count 0 2006.260.08:21:34.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.260.08:21:34.02#ibcon#[25=BW32\r\n] 2006.260.08:21:34.02#ibcon#*before write, iclass 12, count 0 2006.260.08:21:34.02#ibcon#enter sib2, iclass 12, count 0 2006.260.08:21:34.02#ibcon#flushed, iclass 12, count 0 2006.260.08:21:34.02#ibcon#about to write, iclass 12, count 0 2006.260.08:21:34.02#ibcon#wrote, iclass 12, count 0 2006.260.08:21:34.02#ibcon#about to read 3, iclass 12, count 0 2006.260.08:21:34.05#ibcon#read 3, iclass 12, count 0 2006.260.08:21:34.05#ibcon#about to read 4, iclass 12, count 0 2006.260.08:21:34.05#ibcon#read 4, iclass 12, count 0 2006.260.08:21:34.05#ibcon#about to read 5, iclass 12, count 0 2006.260.08:21:34.05#ibcon#read 5, iclass 12, count 0 2006.260.08:21:34.05#ibcon#about to read 6, iclass 12, count 0 2006.260.08:21:34.05#ibcon#read 6, iclass 12, count 0 2006.260.08:21:34.05#ibcon#end of sib2, iclass 12, count 0 2006.260.08:21:34.05#ibcon#*after write, iclass 12, count 0 2006.260.08:21:34.05#ibcon#*before return 0, iclass 12, count 0 2006.260.08:21:34.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:34.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.260.08:21:34.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.260.08:21:34.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.260.08:21:34.05$vc4f8/vbbw=wide 2006.260.08:21:34.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.260.08:21:34.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.260.08:21:34.05#ibcon#ireg 8 cls_cnt 0 2006.260.08:21:34.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:21:34.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:21:34.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:21:34.12#ibcon#enter wrdev, iclass 14, count 0 2006.260.08:21:34.12#ibcon#first serial, iclass 14, count 0 2006.260.08:21:34.12#ibcon#enter sib2, iclass 14, count 0 2006.260.08:21:34.12#ibcon#flushed, iclass 14, count 0 2006.260.08:21:34.12#ibcon#about to write, iclass 14, count 0 2006.260.08:21:34.12#ibcon#wrote, iclass 14, count 0 2006.260.08:21:34.12#ibcon#about to read 3, iclass 14, count 0 2006.260.08:21:34.14#ibcon#read 3, iclass 14, count 0 2006.260.08:21:34.14#ibcon#about to read 4, iclass 14, count 0 2006.260.08:21:34.14#ibcon#read 4, iclass 14, count 0 2006.260.08:21:34.14#ibcon#about to read 5, iclass 14, count 0 2006.260.08:21:34.14#ibcon#read 5, iclass 14, count 0 2006.260.08:21:34.14#ibcon#about to read 6, iclass 14, count 0 2006.260.08:21:34.14#ibcon#read 6, iclass 14, count 0 2006.260.08:21:34.14#ibcon#end of sib2, iclass 14, count 0 2006.260.08:21:34.14#ibcon#*mode == 0, iclass 14, count 0 2006.260.08:21:34.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.260.08:21:34.14#ibcon#[27=BW32\r\n] 2006.260.08:21:34.14#ibcon#*before write, iclass 14, count 0 2006.260.08:21:34.14#ibcon#enter sib2, iclass 14, count 0 2006.260.08:21:34.14#ibcon#flushed, iclass 14, count 0 2006.260.08:21:34.14#ibcon#about to write, iclass 14, count 0 2006.260.08:21:34.14#ibcon#wrote, iclass 14, count 0 2006.260.08:21:34.14#ibcon#about to read 3, iclass 14, count 0 2006.260.08:21:34.17#ibcon#read 3, iclass 14, count 0 2006.260.08:21:34.17#ibcon#about to read 4, iclass 14, count 0 2006.260.08:21:34.17#ibcon#read 4, iclass 14, count 0 2006.260.08:21:34.17#ibcon#about to read 5, iclass 14, count 0 2006.260.08:21:34.17#ibcon#read 5, iclass 14, count 0 2006.260.08:21:34.17#ibcon#about to read 6, iclass 14, count 0 2006.260.08:21:34.17#ibcon#read 6, iclass 14, count 0 2006.260.08:21:34.17#ibcon#end of sib2, iclass 14, count 0 2006.260.08:21:34.17#ibcon#*after write, iclass 14, count 0 2006.260.08:21:34.17#ibcon#*before return 0, iclass 14, count 0 2006.260.08:21:34.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:21:34.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.260.08:21:34.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.260.08:21:34.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.260.08:21:34.17$4f8m12a/ifd4f 2006.260.08:21:34.17$ifd4f/lo= 2006.260.08:21:34.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:21:34.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:21:34.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:21:34.17$ifd4f/patch= 2006.260.08:21:34.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:21:34.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:21:34.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:21:34.17$4f8m12a/"form=m,16.000,1:2 2006.260.08:21:34.17$4f8m12a/"tpicd 2006.260.08:21:34.17$4f8m12a/echo=off 2006.260.08:21:34.17$4f8m12a/xlog=off 2006.260.08:21:34.17:!2006.260.08:23:40 2006.260.08:21:55.14#trakl#Source acquired 2006.260.08:21:57.14#flagr#flagr/antenna,acquired 2006.260.08:23:40.00:preob 2006.260.08:23:40.14/onsource/TRACKING 2006.260.08:23:40.14:!2006.260.08:23:50 2006.260.08:23:50.00:data_valid=on 2006.260.08:23:50.00:midob 2006.260.08:23:51.14/onsource/TRACKING 2006.260.08:23:51.14/wx/22.65,1010.4,91 2006.260.08:23:51.22/cable/+6.4593E-03 2006.260.08:23:52.31/va/01,08,usb,yes,35,37 2006.260.08:23:52.31/va/02,07,usb,yes,35,37 2006.260.08:23:52.31/va/03,08,usb,yes,27,27 2006.260.08:23:52.31/va/04,07,usb,yes,36,39 2006.260.08:23:52.31/va/05,07,usb,yes,40,43 2006.260.08:23:52.31/va/06,06,usb,yes,40,40 2006.260.08:23:52.31/va/07,06,usb,yes,40,40 2006.260.08:23:52.31/va/08,06,usb,yes,43,42 2006.260.08:23:52.54/valo/01,532.99,yes,locked 2006.260.08:23:52.54/valo/02,572.99,yes,locked 2006.260.08:23:52.54/valo/03,672.99,yes,locked 2006.260.08:23:52.54/valo/04,832.99,yes,locked 2006.260.08:23:52.54/valo/05,652.99,yes,locked 2006.260.08:23:52.54/valo/06,772.99,yes,locked 2006.260.08:23:52.54/valo/07,832.99,yes,locked 2006.260.08:23:52.54/valo/08,852.99,yes,locked 2006.260.08:23:53.63/vb/01,04,usb,yes,31,30 2006.260.08:23:53.63/vb/02,05,usb,yes,29,30 2006.260.08:23:53.63/vb/03,04,usb,yes,29,33 2006.260.08:23:53.63/vb/04,05,usb,yes,26,26 2006.260.08:23:53.63/vb/05,04,usb,yes,28,32 2006.260.08:23:53.63/vb/06,04,usb,yes,29,32 2006.260.08:23:53.63/vb/07,04,usb,yes,32,31 2006.260.08:23:53.63/vb/08,04,usb,yes,29,32 2006.260.08:23:53.86/vblo/01,632.99,yes,locked 2006.260.08:23:53.86/vblo/02,640.99,yes,locked 2006.260.08:23:53.86/vblo/03,656.99,yes,locked 2006.260.08:23:53.86/vblo/04,712.99,yes,locked 2006.260.08:23:53.86/vblo/05,744.99,yes,locked 2006.260.08:23:53.86/vblo/06,752.99,yes,locked 2006.260.08:23:53.86/vblo/07,734.99,yes,locked 2006.260.08:23:53.86/vblo/08,744.99,yes,locked 2006.260.08:23:54.01/vabw/8 2006.260.08:23:54.16/vbbw/8 2006.260.08:23:54.25/xfe/off,on,15.2 2006.260.08:23:54.62/ifatt/23,28,28,28 2006.260.08:23:55.08/fmout-gps/S +4.52E-07 2006.260.08:23:55.12:!2006.260.08:24:50 2006.260.08:24:50.02:data_valid=off 2006.260.08:24:50.02:postob 2006.260.08:24:50.09/cable/+6.4588E-03 2006.260.08:24:50.10/wx/22.63,1010.4,91 2006.260.08:24:51.08/fmout-gps/S +4.52E-07 2006.260.08:24:51.08:scan_name=260-0825,k06260,70 2006.260.08:24:51.08:source=1252+119,125438.26,114105.9,2000.0,ccw 2006.260.08:24:51.14#flagr#flagr/antenna,new-source 2006.260.08:24:52.14:checkk5 2006.260.08:24:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.260.08:24:52.95/chk_autoobs//k5ts2/ autoobs is running! 2006.260.08:24:53.42/chk_autoobs//k5ts3/ autoobs is running! 2006.260.08:24:53.91/chk_autoobs//k5ts4/ autoobs is running! 2006.260.08:24:54.32/chk_obsdata//k5ts1/T2600823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:24:54.87/chk_obsdata//k5ts2/T2600823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:24:55.32/chk_obsdata//k5ts3/T2600823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:24:55.73/chk_obsdata//k5ts4/T2600823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.260.08:24:56.49/k5log//k5ts1_log_newline 2006.260.08:24:57.29/k5log//k5ts2_log_newline 2006.260.08:24:58.16/k5log//k5ts3_log_newline 2006.260.08:24:59.16/k5log//k5ts4_log_newline 2006.260.08:24:59.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:24:59.19:4f8m12a=3 2006.260.08:24:59.19$4f8m12a/echo=on 2006.260.08:24:59.19$4f8m12a/pcalon 2006.260.08:24:59.19$pcalon/"no phase cal control is implemented here 2006.260.08:24:59.19$4f8m12a/"tpicd=stop 2006.260.08:24:59.19$4f8m12a/vc4f8 2006.260.08:24:59.19$vc4f8/valo=1,532.99 2006.260.08:24:59.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:24:59.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:24:59.19#ibcon#ireg 17 cls_cnt 0 2006.260.08:24:59.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:24:59.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:24:59.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:24:59.19#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:24:59.19#ibcon#first serial, iclass 25, count 0 2006.260.08:24:59.19#ibcon#enter sib2, iclass 25, count 0 2006.260.08:24:59.19#ibcon#flushed, iclass 25, count 0 2006.260.08:24:59.19#ibcon#about to write, iclass 25, count 0 2006.260.08:24:59.19#ibcon#wrote, iclass 25, count 0 2006.260.08:24:59.19#ibcon#about to read 3, iclass 25, count 0 2006.260.08:24:59.23#ibcon#read 3, iclass 25, count 0 2006.260.08:24:59.23#ibcon#about to read 4, iclass 25, count 0 2006.260.08:24:59.23#ibcon#read 4, iclass 25, count 0 2006.260.08:24:59.23#ibcon#about to read 5, iclass 25, count 0 2006.260.08:24:59.23#ibcon#read 5, iclass 25, count 0 2006.260.08:24:59.23#ibcon#about to read 6, iclass 25, count 0 2006.260.08:24:59.23#ibcon#read 6, iclass 25, count 0 2006.260.08:24:59.23#ibcon#end of sib2, iclass 25, count 0 2006.260.08:24:59.23#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:24:59.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:24:59.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.260.08:24:59.23#ibcon#*before write, iclass 25, count 0 2006.260.08:24:59.23#ibcon#enter sib2, iclass 25, count 0 2006.260.08:24:59.23#ibcon#flushed, iclass 25, count 0 2006.260.08:24:59.23#ibcon#about to write, iclass 25, count 0 2006.260.08:24:59.23#ibcon#wrote, iclass 25, count 0 2006.260.08:24:59.23#ibcon#about to read 3, iclass 25, count 0 2006.260.08:24:59.27#ibcon#read 3, iclass 25, count 0 2006.260.08:24:59.27#ibcon#about to read 4, iclass 25, count 0 2006.260.08:24:59.27#ibcon#read 4, iclass 25, count 0 2006.260.08:24:59.27#ibcon#about to read 5, iclass 25, count 0 2006.260.08:24:59.27#ibcon#read 5, iclass 25, count 0 2006.260.08:24:59.27#ibcon#about to read 6, iclass 25, count 0 2006.260.08:24:59.27#ibcon#read 6, iclass 25, count 0 2006.260.08:24:59.27#ibcon#end of sib2, iclass 25, count 0 2006.260.08:24:59.28#ibcon#*after write, iclass 25, count 0 2006.260.08:24:59.28#ibcon#*before return 0, iclass 25, count 0 2006.260.08:24:59.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:24:59.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:24:59.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:24:59.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:24:59.28$vc4f8/va=1,8 2006.260.08:24:59.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:24:59.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:24:59.28#ibcon#ireg 11 cls_cnt 2 2006.260.08:24:59.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:24:59.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:24:59.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:24:59.28#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:24:59.28#ibcon#first serial, iclass 27, count 2 2006.260.08:24:59.28#ibcon#enter sib2, iclass 27, count 2 2006.260.08:24:59.28#ibcon#flushed, iclass 27, count 2 2006.260.08:24:59.28#ibcon#about to write, iclass 27, count 2 2006.260.08:24:59.28#ibcon#wrote, iclass 27, count 2 2006.260.08:24:59.28#ibcon#about to read 3, iclass 27, count 2 2006.260.08:24:59.30#ibcon#read 3, iclass 27, count 2 2006.260.08:24:59.30#ibcon#about to read 4, iclass 27, count 2 2006.260.08:24:59.30#ibcon#read 4, iclass 27, count 2 2006.260.08:24:59.30#ibcon#about to read 5, iclass 27, count 2 2006.260.08:24:59.30#ibcon#read 5, iclass 27, count 2 2006.260.08:24:59.30#ibcon#about to read 6, iclass 27, count 2 2006.260.08:24:59.30#ibcon#read 6, iclass 27, count 2 2006.260.08:24:59.30#ibcon#end of sib2, iclass 27, count 2 2006.260.08:24:59.30#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:24:59.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:24:59.30#ibcon#[25=AT01-08\r\n] 2006.260.08:24:59.30#ibcon#*before write, iclass 27, count 2 2006.260.08:24:59.30#ibcon#enter sib2, iclass 27, count 2 2006.260.08:24:59.30#ibcon#flushed, iclass 27, count 2 2006.260.08:24:59.30#ibcon#about to write, iclass 27, count 2 2006.260.08:24:59.30#ibcon#wrote, iclass 27, count 2 2006.260.08:24:59.30#ibcon#about to read 3, iclass 27, count 2 2006.260.08:24:59.34#ibcon#read 3, iclass 27, count 2 2006.260.08:24:59.34#ibcon#about to read 4, iclass 27, count 2 2006.260.08:24:59.34#ibcon#read 4, iclass 27, count 2 2006.260.08:24:59.34#ibcon#about to read 5, iclass 27, count 2 2006.260.08:24:59.34#ibcon#read 5, iclass 27, count 2 2006.260.08:24:59.34#ibcon#about to read 6, iclass 27, count 2 2006.260.08:24:59.34#ibcon#read 6, iclass 27, count 2 2006.260.08:24:59.34#ibcon#end of sib2, iclass 27, count 2 2006.260.08:24:59.34#ibcon#*after write, iclass 27, count 2 2006.260.08:24:59.34#ibcon#*before return 0, iclass 27, count 2 2006.260.08:24:59.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:24:59.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:24:59.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:24:59.34#ibcon#ireg 7 cls_cnt 0 2006.260.08:24:59.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:24:59.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:24:59.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:24:59.45#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:24:59.45#ibcon#first serial, iclass 27, count 0 2006.260.08:24:59.45#ibcon#enter sib2, iclass 27, count 0 2006.260.08:24:59.45#ibcon#flushed, iclass 27, count 0 2006.260.08:24:59.45#ibcon#about to write, iclass 27, count 0 2006.260.08:24:59.45#ibcon#wrote, iclass 27, count 0 2006.260.08:24:59.46#ibcon#about to read 3, iclass 27, count 0 2006.260.08:24:59.47#ibcon#read 3, iclass 27, count 0 2006.260.08:24:59.47#ibcon#about to read 4, iclass 27, count 0 2006.260.08:24:59.47#ibcon#read 4, iclass 27, count 0 2006.260.08:24:59.47#ibcon#about to read 5, iclass 27, count 0 2006.260.08:24:59.47#ibcon#read 5, iclass 27, count 0 2006.260.08:24:59.47#ibcon#about to read 6, iclass 27, count 0 2006.260.08:24:59.47#ibcon#read 6, iclass 27, count 0 2006.260.08:24:59.47#ibcon#end of sib2, iclass 27, count 0 2006.260.08:24:59.48#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:24:59.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:24:59.48#ibcon#[25=USB\r\n] 2006.260.08:24:59.48#ibcon#*before write, iclass 27, count 0 2006.260.08:24:59.48#ibcon#enter sib2, iclass 27, count 0 2006.260.08:24:59.48#ibcon#flushed, iclass 27, count 0 2006.260.08:24:59.48#ibcon#about to write, iclass 27, count 0 2006.260.08:24:59.48#ibcon#wrote, iclass 27, count 0 2006.260.08:24:59.48#ibcon#about to read 3, iclass 27, count 0 2006.260.08:24:59.50#ibcon#read 3, iclass 27, count 0 2006.260.08:24:59.50#ibcon#about to read 4, iclass 27, count 0 2006.260.08:24:59.50#ibcon#read 4, iclass 27, count 0 2006.260.08:24:59.50#ibcon#about to read 5, iclass 27, count 0 2006.260.08:24:59.50#ibcon#read 5, iclass 27, count 0 2006.260.08:24:59.50#ibcon#about to read 6, iclass 27, count 0 2006.260.08:24:59.50#ibcon#read 6, iclass 27, count 0 2006.260.08:24:59.50#ibcon#end of sib2, iclass 27, count 0 2006.260.08:24:59.51#ibcon#*after write, iclass 27, count 0 2006.260.08:24:59.51#ibcon#*before return 0, iclass 27, count 0 2006.260.08:24:59.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:24:59.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:24:59.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:24:59.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:24:59.51$vc4f8/valo=2,572.99 2006.260.08:24:59.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:24:59.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:24:59.51#ibcon#ireg 17 cls_cnt 0 2006.260.08:24:59.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:24:59.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:24:59.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:24:59.51#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:24:59.51#ibcon#first serial, iclass 29, count 0 2006.260.08:24:59.51#ibcon#enter sib2, iclass 29, count 0 2006.260.08:24:59.51#ibcon#flushed, iclass 29, count 0 2006.260.08:24:59.51#ibcon#about to write, iclass 29, count 0 2006.260.08:24:59.51#ibcon#wrote, iclass 29, count 0 2006.260.08:24:59.51#ibcon#about to read 3, iclass 29, count 0 2006.260.08:24:59.52#ibcon#read 3, iclass 29, count 0 2006.260.08:24:59.52#ibcon#about to read 4, iclass 29, count 0 2006.260.08:24:59.52#ibcon#read 4, iclass 29, count 0 2006.260.08:24:59.52#ibcon#about to read 5, iclass 29, count 0 2006.260.08:24:59.53#ibcon#read 5, iclass 29, count 0 2006.260.08:24:59.53#ibcon#about to read 6, iclass 29, count 0 2006.260.08:24:59.53#ibcon#read 6, iclass 29, count 0 2006.260.08:24:59.53#ibcon#end of sib2, iclass 29, count 0 2006.260.08:24:59.53#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:24:59.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:24:59.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.260.08:24:59.53#ibcon#*before write, iclass 29, count 0 2006.260.08:24:59.53#ibcon#enter sib2, iclass 29, count 0 2006.260.08:24:59.53#ibcon#flushed, iclass 29, count 0 2006.260.08:24:59.53#ibcon#about to write, iclass 29, count 0 2006.260.08:24:59.53#ibcon#wrote, iclass 29, count 0 2006.260.08:24:59.53#ibcon#about to read 3, iclass 29, count 0 2006.260.08:24:59.57#ibcon#read 3, iclass 29, count 0 2006.260.08:24:59.57#ibcon#about to read 4, iclass 29, count 0 2006.260.08:24:59.57#ibcon#read 4, iclass 29, count 0 2006.260.08:24:59.57#ibcon#about to read 5, iclass 29, count 0 2006.260.08:24:59.57#ibcon#read 5, iclass 29, count 0 2006.260.08:24:59.57#ibcon#about to read 6, iclass 29, count 0 2006.260.08:24:59.57#ibcon#read 6, iclass 29, count 0 2006.260.08:24:59.57#ibcon#end of sib2, iclass 29, count 0 2006.260.08:24:59.57#ibcon#*after write, iclass 29, count 0 2006.260.08:24:59.57#ibcon#*before return 0, iclass 29, count 0 2006.260.08:24:59.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:24:59.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:24:59.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:24:59.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:24:59.57$vc4f8/va=2,7 2006.260.08:24:59.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:24:59.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:24:59.57#ibcon#ireg 11 cls_cnt 2 2006.260.08:24:59.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:24:59.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:24:59.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:24:59.62#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:24:59.62#ibcon#first serial, iclass 31, count 2 2006.260.08:24:59.62#ibcon#enter sib2, iclass 31, count 2 2006.260.08:24:59.62#ibcon#flushed, iclass 31, count 2 2006.260.08:24:59.62#ibcon#about to write, iclass 31, count 2 2006.260.08:24:59.63#ibcon#wrote, iclass 31, count 2 2006.260.08:24:59.63#ibcon#about to read 3, iclass 31, count 2 2006.260.08:24:59.65#ibcon#read 3, iclass 31, count 2 2006.260.08:24:59.65#ibcon#about to read 4, iclass 31, count 2 2006.260.08:24:59.65#ibcon#read 4, iclass 31, count 2 2006.260.08:24:59.65#ibcon#about to read 5, iclass 31, count 2 2006.260.08:24:59.65#ibcon#read 5, iclass 31, count 2 2006.260.08:24:59.65#ibcon#about to read 6, iclass 31, count 2 2006.260.08:24:59.65#ibcon#read 6, iclass 31, count 2 2006.260.08:24:59.65#ibcon#end of sib2, iclass 31, count 2 2006.260.08:24:59.65#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:24:59.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:24:59.65#ibcon#[25=AT02-07\r\n] 2006.260.08:24:59.65#ibcon#*before write, iclass 31, count 2 2006.260.08:24:59.65#ibcon#enter sib2, iclass 31, count 2 2006.260.08:24:59.65#ibcon#flushed, iclass 31, count 2 2006.260.08:24:59.65#ibcon#about to write, iclass 31, count 2 2006.260.08:24:59.65#ibcon#wrote, iclass 31, count 2 2006.260.08:24:59.65#ibcon#about to read 3, iclass 31, count 2 2006.260.08:24:59.68#ibcon#read 3, iclass 31, count 2 2006.260.08:24:59.68#ibcon#about to read 4, iclass 31, count 2 2006.260.08:24:59.68#ibcon#read 4, iclass 31, count 2 2006.260.08:24:59.68#ibcon#about to read 5, iclass 31, count 2 2006.260.08:24:59.68#ibcon#read 5, iclass 31, count 2 2006.260.08:24:59.69#ibcon#about to read 6, iclass 31, count 2 2006.260.08:24:59.69#ibcon#read 6, iclass 31, count 2 2006.260.08:24:59.69#ibcon#end of sib2, iclass 31, count 2 2006.260.08:24:59.69#ibcon#*after write, iclass 31, count 2 2006.260.08:24:59.69#ibcon#*before return 0, iclass 31, count 2 2006.260.08:24:59.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:24:59.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:24:59.69#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:24:59.69#ibcon#ireg 7 cls_cnt 0 2006.260.08:24:59.69#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:24:59.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:24:59.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:24:59.80#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:24:59.80#ibcon#first serial, iclass 31, count 0 2006.260.08:24:59.80#ibcon#enter sib2, iclass 31, count 0 2006.260.08:24:59.80#ibcon#flushed, iclass 31, count 0 2006.260.08:24:59.80#ibcon#about to write, iclass 31, count 0 2006.260.08:24:59.81#ibcon#wrote, iclass 31, count 0 2006.260.08:24:59.81#ibcon#about to read 3, iclass 31, count 0 2006.260.08:24:59.82#ibcon#read 3, iclass 31, count 0 2006.260.08:24:59.82#ibcon#about to read 4, iclass 31, count 0 2006.260.08:24:59.82#ibcon#read 4, iclass 31, count 0 2006.260.08:24:59.82#ibcon#about to read 5, iclass 31, count 0 2006.260.08:24:59.82#ibcon#read 5, iclass 31, count 0 2006.260.08:24:59.82#ibcon#about to read 6, iclass 31, count 0 2006.260.08:24:59.82#ibcon#read 6, iclass 31, count 0 2006.260.08:24:59.82#ibcon#end of sib2, iclass 31, count 0 2006.260.08:24:59.83#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:24:59.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:24:59.83#ibcon#[25=USB\r\n] 2006.260.08:24:59.83#ibcon#*before write, iclass 31, count 0 2006.260.08:24:59.83#ibcon#enter sib2, iclass 31, count 0 2006.260.08:24:59.83#ibcon#flushed, iclass 31, count 0 2006.260.08:24:59.83#ibcon#about to write, iclass 31, count 0 2006.260.08:24:59.83#ibcon#wrote, iclass 31, count 0 2006.260.08:24:59.83#ibcon#about to read 3, iclass 31, count 0 2006.260.08:24:59.85#ibcon#read 3, iclass 31, count 0 2006.260.08:24:59.85#ibcon#about to read 4, iclass 31, count 0 2006.260.08:24:59.85#ibcon#read 4, iclass 31, count 0 2006.260.08:24:59.85#ibcon#about to read 5, iclass 31, count 0 2006.260.08:24:59.85#ibcon#read 5, iclass 31, count 0 2006.260.08:24:59.85#ibcon#about to read 6, iclass 31, count 0 2006.260.08:24:59.85#ibcon#read 6, iclass 31, count 0 2006.260.08:24:59.85#ibcon#end of sib2, iclass 31, count 0 2006.260.08:24:59.86#ibcon#*after write, iclass 31, count 0 2006.260.08:24:59.86#ibcon#*before return 0, iclass 31, count 0 2006.260.08:24:59.86#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:24:59.86#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:24:59.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:24:59.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:24:59.86$vc4f8/valo=3,672.99 2006.260.08:24:59.86#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:24:59.86#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:24:59.86#ibcon#ireg 17 cls_cnt 0 2006.260.08:24:59.86#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:24:59.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:24:59.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:24:59.86#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:24:59.86#ibcon#first serial, iclass 33, count 0 2006.260.08:24:59.86#ibcon#enter sib2, iclass 33, count 0 2006.260.08:24:59.86#ibcon#flushed, iclass 33, count 0 2006.260.08:24:59.86#ibcon#about to write, iclass 33, count 0 2006.260.08:24:59.86#ibcon#wrote, iclass 33, count 0 2006.260.08:24:59.86#ibcon#about to read 3, iclass 33, count 0 2006.260.08:24:59.87#ibcon#read 3, iclass 33, count 0 2006.260.08:24:59.87#ibcon#about to read 4, iclass 33, count 0 2006.260.08:24:59.87#ibcon#read 4, iclass 33, count 0 2006.260.08:24:59.87#ibcon#about to read 5, iclass 33, count 0 2006.260.08:24:59.87#ibcon#read 5, iclass 33, count 0 2006.260.08:24:59.87#ibcon#about to read 6, iclass 33, count 0 2006.260.08:24:59.87#ibcon#read 6, iclass 33, count 0 2006.260.08:24:59.88#ibcon#end of sib2, iclass 33, count 0 2006.260.08:24:59.88#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:24:59.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:24:59.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.260.08:24:59.88#ibcon#*before write, iclass 33, count 0 2006.260.08:24:59.88#ibcon#enter sib2, iclass 33, count 0 2006.260.08:24:59.88#ibcon#flushed, iclass 33, count 0 2006.260.08:24:59.88#ibcon#about to write, iclass 33, count 0 2006.260.08:24:59.88#ibcon#wrote, iclass 33, count 0 2006.260.08:24:59.88#ibcon#about to read 3, iclass 33, count 0 2006.260.08:24:59.92#ibcon#read 3, iclass 33, count 0 2006.260.08:24:59.92#ibcon#about to read 4, iclass 33, count 0 2006.260.08:24:59.92#ibcon#read 4, iclass 33, count 0 2006.260.08:24:59.92#ibcon#about to read 5, iclass 33, count 0 2006.260.08:24:59.92#ibcon#read 5, iclass 33, count 0 2006.260.08:24:59.92#ibcon#about to read 6, iclass 33, count 0 2006.260.08:24:59.92#ibcon#read 6, iclass 33, count 0 2006.260.08:24:59.92#ibcon#end of sib2, iclass 33, count 0 2006.260.08:24:59.92#ibcon#*after write, iclass 33, count 0 2006.260.08:24:59.92#ibcon#*before return 0, iclass 33, count 0 2006.260.08:24:59.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:24:59.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:24:59.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:24:59.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:24:59.92$vc4f8/va=3,8 2006.260.08:24:59.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.260.08:24:59.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.260.08:24:59.92#ibcon#ireg 11 cls_cnt 2 2006.260.08:24:59.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:24:59.94#abcon#<5=/04 3.3 6.7 22.63 911010.4\r\n> 2006.260.08:24:59.96#abcon#{5=INTERFACE CLEAR} 2006.260.08:24:59.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:24:59.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:24:59.98#ibcon#enter wrdev, iclass 36, count 2 2006.260.08:24:59.98#ibcon#first serial, iclass 36, count 2 2006.260.08:24:59.98#ibcon#enter sib2, iclass 36, count 2 2006.260.08:24:59.98#ibcon#flushed, iclass 36, count 2 2006.260.08:24:59.98#ibcon#about to write, iclass 36, count 2 2006.260.08:24:59.98#ibcon#wrote, iclass 36, count 2 2006.260.08:24:59.98#ibcon#about to read 3, iclass 36, count 2 2006.260.08:24:59.99#ibcon#read 3, iclass 36, count 2 2006.260.08:24:59.99#ibcon#about to read 4, iclass 36, count 2 2006.260.08:24:59.99#ibcon#read 4, iclass 36, count 2 2006.260.08:24:59.99#ibcon#about to read 5, iclass 36, count 2 2006.260.08:24:59.99#ibcon#read 5, iclass 36, count 2 2006.260.08:24:59.99#ibcon#about to read 6, iclass 36, count 2 2006.260.08:24:59.99#ibcon#read 6, iclass 36, count 2 2006.260.08:24:59.99#ibcon#end of sib2, iclass 36, count 2 2006.260.08:24:59.99#ibcon#*mode == 0, iclass 36, count 2 2006.260.08:25:00.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.260.08:25:00.00#ibcon#[25=AT03-08\r\n] 2006.260.08:25:00.00#ibcon#*before write, iclass 36, count 2 2006.260.08:25:00.00#ibcon#enter sib2, iclass 36, count 2 2006.260.08:25:00.00#ibcon#flushed, iclass 36, count 2 2006.260.08:25:00.00#ibcon#about to write, iclass 36, count 2 2006.260.08:25:00.00#ibcon#wrote, iclass 36, count 2 2006.260.08:25:00.00#ibcon#about to read 3, iclass 36, count 2 2006.260.08:25:00.02#abcon#[5=S1D000X0/0*\r\n] 2006.260.08:25:00.03#ibcon#read 3, iclass 36, count 2 2006.260.08:25:00.03#ibcon#about to read 4, iclass 36, count 2 2006.260.08:25:00.03#ibcon#read 4, iclass 36, count 2 2006.260.08:25:00.03#ibcon#about to read 5, iclass 36, count 2 2006.260.08:25:00.03#ibcon#read 5, iclass 36, count 2 2006.260.08:25:00.03#ibcon#about to read 6, iclass 36, count 2 2006.260.08:25:00.03#ibcon#read 6, iclass 36, count 2 2006.260.08:25:00.03#ibcon#end of sib2, iclass 36, count 2 2006.260.08:25:00.03#ibcon#*after write, iclass 36, count 2 2006.260.08:25:00.03#ibcon#*before return 0, iclass 36, count 2 2006.260.08:25:00.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:25:00.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.260.08:25:00.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.260.08:25:00.03#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:00.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:25:00.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:25:00.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:25:00.15#ibcon#enter wrdev, iclass 36, count 0 2006.260.08:25:00.15#ibcon#first serial, iclass 36, count 0 2006.260.08:25:00.15#ibcon#enter sib2, iclass 36, count 0 2006.260.08:25:00.15#ibcon#flushed, iclass 36, count 0 2006.260.08:25:00.15#ibcon#about to write, iclass 36, count 0 2006.260.08:25:00.15#ibcon#wrote, iclass 36, count 0 2006.260.08:25:00.15#ibcon#about to read 3, iclass 36, count 0 2006.260.08:25:00.16#ibcon#read 3, iclass 36, count 0 2006.260.08:25:00.16#ibcon#about to read 4, iclass 36, count 0 2006.260.08:25:00.16#ibcon#read 4, iclass 36, count 0 2006.260.08:25:00.16#ibcon#about to read 5, iclass 36, count 0 2006.260.08:25:00.16#ibcon#read 5, iclass 36, count 0 2006.260.08:25:00.16#ibcon#about to read 6, iclass 36, count 0 2006.260.08:25:00.16#ibcon#read 6, iclass 36, count 0 2006.260.08:25:00.16#ibcon#end of sib2, iclass 36, count 0 2006.260.08:25:00.16#ibcon#*mode == 0, iclass 36, count 0 2006.260.08:25:00.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.260.08:25:00.17#ibcon#[25=USB\r\n] 2006.260.08:25:00.17#ibcon#*before write, iclass 36, count 0 2006.260.08:25:00.17#ibcon#enter sib2, iclass 36, count 0 2006.260.08:25:00.17#ibcon#flushed, iclass 36, count 0 2006.260.08:25:00.17#ibcon#about to write, iclass 36, count 0 2006.260.08:25:00.17#ibcon#wrote, iclass 36, count 0 2006.260.08:25:00.17#ibcon#about to read 3, iclass 36, count 0 2006.260.08:25:00.19#ibcon#read 3, iclass 36, count 0 2006.260.08:25:00.19#ibcon#about to read 4, iclass 36, count 0 2006.260.08:25:00.19#ibcon#read 4, iclass 36, count 0 2006.260.08:25:00.19#ibcon#about to read 5, iclass 36, count 0 2006.260.08:25:00.19#ibcon#read 5, iclass 36, count 0 2006.260.08:25:00.19#ibcon#about to read 6, iclass 36, count 0 2006.260.08:25:00.19#ibcon#read 6, iclass 36, count 0 2006.260.08:25:00.19#ibcon#end of sib2, iclass 36, count 0 2006.260.08:25:00.20#ibcon#*after write, iclass 36, count 0 2006.260.08:25:00.20#ibcon#*before return 0, iclass 36, count 0 2006.260.08:25:00.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:25:00.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.260.08:25:00.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.260.08:25:00.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.260.08:25:00.20$vc4f8/valo=4,832.99 2006.260.08:25:00.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.08:25:00.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.08:25:00.20#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:00.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:00.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:00.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:00.20#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:25:00.20#ibcon#first serial, iclass 3, count 0 2006.260.08:25:00.20#ibcon#enter sib2, iclass 3, count 0 2006.260.08:25:00.20#ibcon#flushed, iclass 3, count 0 2006.260.08:25:00.20#ibcon#about to write, iclass 3, count 0 2006.260.08:25:00.20#ibcon#wrote, iclass 3, count 0 2006.260.08:25:00.20#ibcon#about to read 3, iclass 3, count 0 2006.260.08:25:00.21#ibcon#read 3, iclass 3, count 0 2006.260.08:25:00.21#ibcon#about to read 4, iclass 3, count 0 2006.260.08:25:00.21#ibcon#read 4, iclass 3, count 0 2006.260.08:25:00.21#ibcon#about to read 5, iclass 3, count 0 2006.260.08:25:00.21#ibcon#read 5, iclass 3, count 0 2006.260.08:25:00.21#ibcon#about to read 6, iclass 3, count 0 2006.260.08:25:00.21#ibcon#read 6, iclass 3, count 0 2006.260.08:25:00.21#ibcon#end of sib2, iclass 3, count 0 2006.260.08:25:00.22#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:25:00.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:25:00.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.260.08:25:00.22#ibcon#*before write, iclass 3, count 0 2006.260.08:25:00.22#ibcon#enter sib2, iclass 3, count 0 2006.260.08:25:00.22#ibcon#flushed, iclass 3, count 0 2006.260.08:25:00.22#ibcon#about to write, iclass 3, count 0 2006.260.08:25:00.22#ibcon#wrote, iclass 3, count 0 2006.260.08:25:00.22#ibcon#about to read 3, iclass 3, count 0 2006.260.08:25:00.25#ibcon#read 3, iclass 3, count 0 2006.260.08:25:00.25#ibcon#about to read 4, iclass 3, count 0 2006.260.08:25:00.25#ibcon#read 4, iclass 3, count 0 2006.260.08:25:00.25#ibcon#about to read 5, iclass 3, count 0 2006.260.08:25:00.25#ibcon#read 5, iclass 3, count 0 2006.260.08:25:00.25#ibcon#about to read 6, iclass 3, count 0 2006.260.08:25:00.25#ibcon#read 6, iclass 3, count 0 2006.260.08:25:00.25#ibcon#end of sib2, iclass 3, count 0 2006.260.08:25:00.25#ibcon#*after write, iclass 3, count 0 2006.260.08:25:00.26#ibcon#*before return 0, iclass 3, count 0 2006.260.08:25:00.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:00.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:00.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:25:00.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:25:00.26$vc4f8/va=4,7 2006.260.08:25:00.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.08:25:00.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.08:25:00.26#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:00.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:00.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:00.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:00.31#ibcon#enter wrdev, iclass 5, count 2 2006.260.08:25:00.31#ibcon#first serial, iclass 5, count 2 2006.260.08:25:00.31#ibcon#enter sib2, iclass 5, count 2 2006.260.08:25:00.31#ibcon#flushed, iclass 5, count 2 2006.260.08:25:00.31#ibcon#about to write, iclass 5, count 2 2006.260.08:25:00.31#ibcon#wrote, iclass 5, count 2 2006.260.08:25:00.31#ibcon#about to read 3, iclass 5, count 2 2006.260.08:25:00.33#ibcon#read 3, iclass 5, count 2 2006.260.08:25:00.33#ibcon#about to read 4, iclass 5, count 2 2006.260.08:25:00.33#ibcon#read 4, iclass 5, count 2 2006.260.08:25:00.33#ibcon#about to read 5, iclass 5, count 2 2006.260.08:25:00.33#ibcon#read 5, iclass 5, count 2 2006.260.08:25:00.33#ibcon#about to read 6, iclass 5, count 2 2006.260.08:25:00.33#ibcon#read 6, iclass 5, count 2 2006.260.08:25:00.33#ibcon#end of sib2, iclass 5, count 2 2006.260.08:25:00.33#ibcon#*mode == 0, iclass 5, count 2 2006.260.08:25:00.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.08:25:00.34#ibcon#[25=AT04-07\r\n] 2006.260.08:25:00.34#ibcon#*before write, iclass 5, count 2 2006.260.08:25:00.34#ibcon#enter sib2, iclass 5, count 2 2006.260.08:25:00.34#ibcon#flushed, iclass 5, count 2 2006.260.08:25:00.34#ibcon#about to write, iclass 5, count 2 2006.260.08:25:00.34#ibcon#wrote, iclass 5, count 2 2006.260.08:25:00.34#ibcon#about to read 3, iclass 5, count 2 2006.260.08:25:00.36#ibcon#read 3, iclass 5, count 2 2006.260.08:25:00.36#ibcon#about to read 4, iclass 5, count 2 2006.260.08:25:00.36#ibcon#read 4, iclass 5, count 2 2006.260.08:25:00.36#ibcon#about to read 5, iclass 5, count 2 2006.260.08:25:00.36#ibcon#read 5, iclass 5, count 2 2006.260.08:25:00.36#ibcon#about to read 6, iclass 5, count 2 2006.260.08:25:00.36#ibcon#read 6, iclass 5, count 2 2006.260.08:25:00.36#ibcon#end of sib2, iclass 5, count 2 2006.260.08:25:00.37#ibcon#*after write, iclass 5, count 2 2006.260.08:25:00.37#ibcon#*before return 0, iclass 5, count 2 2006.260.08:25:00.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:00.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:00.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.08:25:00.37#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:00.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:00.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:00.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:00.48#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:25:00.48#ibcon#first serial, iclass 5, count 0 2006.260.08:25:00.48#ibcon#enter sib2, iclass 5, count 0 2006.260.08:25:00.48#ibcon#flushed, iclass 5, count 0 2006.260.08:25:00.48#ibcon#about to write, iclass 5, count 0 2006.260.08:25:00.48#ibcon#wrote, iclass 5, count 0 2006.260.08:25:00.48#ibcon#about to read 3, iclass 5, count 0 2006.260.08:25:00.50#ibcon#read 3, iclass 5, count 0 2006.260.08:25:00.50#ibcon#about to read 4, iclass 5, count 0 2006.260.08:25:00.50#ibcon#read 4, iclass 5, count 0 2006.260.08:25:00.50#ibcon#about to read 5, iclass 5, count 0 2006.260.08:25:00.50#ibcon#read 5, iclass 5, count 0 2006.260.08:25:00.50#ibcon#about to read 6, iclass 5, count 0 2006.260.08:25:00.50#ibcon#read 6, iclass 5, count 0 2006.260.08:25:00.50#ibcon#end of sib2, iclass 5, count 0 2006.260.08:25:00.51#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:25:00.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:25:00.51#ibcon#[25=USB\r\n] 2006.260.08:25:00.51#ibcon#*before write, iclass 5, count 0 2006.260.08:25:00.51#ibcon#enter sib2, iclass 5, count 0 2006.260.08:25:00.51#ibcon#flushed, iclass 5, count 0 2006.260.08:25:00.51#ibcon#about to write, iclass 5, count 0 2006.260.08:25:00.51#ibcon#wrote, iclass 5, count 0 2006.260.08:25:00.51#ibcon#about to read 3, iclass 5, count 0 2006.260.08:25:00.53#ibcon#read 3, iclass 5, count 0 2006.260.08:25:00.53#ibcon#about to read 4, iclass 5, count 0 2006.260.08:25:00.53#ibcon#read 4, iclass 5, count 0 2006.260.08:25:00.53#ibcon#about to read 5, iclass 5, count 0 2006.260.08:25:00.53#ibcon#read 5, iclass 5, count 0 2006.260.08:25:00.53#ibcon#about to read 6, iclass 5, count 0 2006.260.08:25:00.53#ibcon#read 6, iclass 5, count 0 2006.260.08:25:00.53#ibcon#end of sib2, iclass 5, count 0 2006.260.08:25:00.53#ibcon#*after write, iclass 5, count 0 2006.260.08:25:00.54#ibcon#*before return 0, iclass 5, count 0 2006.260.08:25:00.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:00.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:00.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:25:00.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:25:00.54$vc4f8/valo=5,652.99 2006.260.08:25:00.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:25:00.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:25:00.54#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:00.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:00.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:00.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:00.54#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:25:00.54#ibcon#first serial, iclass 7, count 0 2006.260.08:25:00.54#ibcon#enter sib2, iclass 7, count 0 2006.260.08:25:00.54#ibcon#flushed, iclass 7, count 0 2006.260.08:25:00.54#ibcon#about to write, iclass 7, count 0 2006.260.08:25:00.54#ibcon#wrote, iclass 7, count 0 2006.260.08:25:00.54#ibcon#about to read 3, iclass 7, count 0 2006.260.08:25:00.55#ibcon#read 3, iclass 7, count 0 2006.260.08:25:00.55#ibcon#about to read 4, iclass 7, count 0 2006.260.08:25:00.55#ibcon#read 4, iclass 7, count 0 2006.260.08:25:00.55#ibcon#about to read 5, iclass 7, count 0 2006.260.08:25:00.55#ibcon#read 5, iclass 7, count 0 2006.260.08:25:00.55#ibcon#about to read 6, iclass 7, count 0 2006.260.08:25:00.55#ibcon#read 6, iclass 7, count 0 2006.260.08:25:00.55#ibcon#end of sib2, iclass 7, count 0 2006.260.08:25:00.55#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:25:00.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:25:00.56#ibcon#[26=FRQ=05,652.99\r\n] 2006.260.08:25:00.56#ibcon#*before write, iclass 7, count 0 2006.260.08:25:00.56#ibcon#enter sib2, iclass 7, count 0 2006.260.08:25:00.56#ibcon#flushed, iclass 7, count 0 2006.260.08:25:00.56#ibcon#about to write, iclass 7, count 0 2006.260.08:25:00.56#ibcon#wrote, iclass 7, count 0 2006.260.08:25:00.56#ibcon#about to read 3, iclass 7, count 0 2006.260.08:25:00.59#ibcon#read 3, iclass 7, count 0 2006.260.08:25:00.59#ibcon#about to read 4, iclass 7, count 0 2006.260.08:25:00.59#ibcon#read 4, iclass 7, count 0 2006.260.08:25:00.59#ibcon#about to read 5, iclass 7, count 0 2006.260.08:25:00.59#ibcon#read 5, iclass 7, count 0 2006.260.08:25:00.59#ibcon#about to read 6, iclass 7, count 0 2006.260.08:25:00.59#ibcon#read 6, iclass 7, count 0 2006.260.08:25:00.59#ibcon#end of sib2, iclass 7, count 0 2006.260.08:25:00.59#ibcon#*after write, iclass 7, count 0 2006.260.08:25:00.60#ibcon#*before return 0, iclass 7, count 0 2006.260.08:25:00.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:00.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:00.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:25:00.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:25:00.60$vc4f8/va=5,7 2006.260.08:25:00.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:25:00.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:25:00.60#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:00.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:00.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:00.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:00.65#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:25:00.65#ibcon#first serial, iclass 11, count 2 2006.260.08:25:00.65#ibcon#enter sib2, iclass 11, count 2 2006.260.08:25:00.65#ibcon#flushed, iclass 11, count 2 2006.260.08:25:00.65#ibcon#about to write, iclass 11, count 2 2006.260.08:25:00.65#ibcon#wrote, iclass 11, count 2 2006.260.08:25:00.65#ibcon#about to read 3, iclass 11, count 2 2006.260.08:25:00.67#ibcon#read 3, iclass 11, count 2 2006.260.08:25:00.67#ibcon#about to read 4, iclass 11, count 2 2006.260.08:25:00.67#ibcon#read 4, iclass 11, count 2 2006.260.08:25:00.67#ibcon#about to read 5, iclass 11, count 2 2006.260.08:25:00.67#ibcon#read 5, iclass 11, count 2 2006.260.08:25:00.67#ibcon#about to read 6, iclass 11, count 2 2006.260.08:25:00.67#ibcon#read 6, iclass 11, count 2 2006.260.08:25:00.67#ibcon#end of sib2, iclass 11, count 2 2006.260.08:25:00.67#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:25:00.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:25:00.68#ibcon#[25=AT05-07\r\n] 2006.260.08:25:00.68#ibcon#*before write, iclass 11, count 2 2006.260.08:25:00.68#ibcon#enter sib2, iclass 11, count 2 2006.260.08:25:00.68#ibcon#flushed, iclass 11, count 2 2006.260.08:25:00.68#ibcon#about to write, iclass 11, count 2 2006.260.08:25:00.68#ibcon#wrote, iclass 11, count 2 2006.260.08:25:00.68#ibcon#about to read 3, iclass 11, count 2 2006.260.08:25:00.70#ibcon#read 3, iclass 11, count 2 2006.260.08:25:00.70#ibcon#about to read 4, iclass 11, count 2 2006.260.08:25:00.70#ibcon#read 4, iclass 11, count 2 2006.260.08:25:00.70#ibcon#about to read 5, iclass 11, count 2 2006.260.08:25:00.70#ibcon#read 5, iclass 11, count 2 2006.260.08:25:00.70#ibcon#about to read 6, iclass 11, count 2 2006.260.08:25:00.70#ibcon#read 6, iclass 11, count 2 2006.260.08:25:00.70#ibcon#end of sib2, iclass 11, count 2 2006.260.08:25:00.70#ibcon#*after write, iclass 11, count 2 2006.260.08:25:00.71#ibcon#*before return 0, iclass 11, count 2 2006.260.08:25:00.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:00.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:00.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:25:00.71#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:00.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:00.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:00.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:00.82#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:25:00.82#ibcon#first serial, iclass 11, count 0 2006.260.08:25:00.82#ibcon#enter sib2, iclass 11, count 0 2006.260.08:25:00.82#ibcon#flushed, iclass 11, count 0 2006.260.08:25:00.82#ibcon#about to write, iclass 11, count 0 2006.260.08:25:00.82#ibcon#wrote, iclass 11, count 0 2006.260.08:25:00.82#ibcon#about to read 3, iclass 11, count 0 2006.260.08:25:00.84#ibcon#read 3, iclass 11, count 0 2006.260.08:25:00.84#ibcon#about to read 4, iclass 11, count 0 2006.260.08:25:00.84#ibcon#read 4, iclass 11, count 0 2006.260.08:25:00.84#ibcon#about to read 5, iclass 11, count 0 2006.260.08:25:00.84#ibcon#read 5, iclass 11, count 0 2006.260.08:25:00.84#ibcon#about to read 6, iclass 11, count 0 2006.260.08:25:00.84#ibcon#read 6, iclass 11, count 0 2006.260.08:25:00.84#ibcon#end of sib2, iclass 11, count 0 2006.260.08:25:00.84#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:25:00.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:25:00.85#ibcon#[25=USB\r\n] 2006.260.08:25:00.85#ibcon#*before write, iclass 11, count 0 2006.260.08:25:00.85#ibcon#enter sib2, iclass 11, count 0 2006.260.08:25:00.85#ibcon#flushed, iclass 11, count 0 2006.260.08:25:00.85#ibcon#about to write, iclass 11, count 0 2006.260.08:25:00.85#ibcon#wrote, iclass 11, count 0 2006.260.08:25:00.85#ibcon#about to read 3, iclass 11, count 0 2006.260.08:25:00.87#ibcon#read 3, iclass 11, count 0 2006.260.08:25:00.87#ibcon#about to read 4, iclass 11, count 0 2006.260.08:25:00.87#ibcon#read 4, iclass 11, count 0 2006.260.08:25:00.87#ibcon#about to read 5, iclass 11, count 0 2006.260.08:25:00.87#ibcon#read 5, iclass 11, count 0 2006.260.08:25:00.87#ibcon#about to read 6, iclass 11, count 0 2006.260.08:25:00.87#ibcon#read 6, iclass 11, count 0 2006.260.08:25:00.87#ibcon#end of sib2, iclass 11, count 0 2006.260.08:25:00.87#ibcon#*after write, iclass 11, count 0 2006.260.08:25:00.88#ibcon#*before return 0, iclass 11, count 0 2006.260.08:25:00.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:00.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:00.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:25:00.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:25:00.88$vc4f8/valo=6,772.99 2006.260.08:25:00.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:25:00.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:25:00.88#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:00.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:00.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:00.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:00.88#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:25:00.88#ibcon#first serial, iclass 13, count 0 2006.260.08:25:00.88#ibcon#enter sib2, iclass 13, count 0 2006.260.08:25:00.88#ibcon#flushed, iclass 13, count 0 2006.260.08:25:00.88#ibcon#about to write, iclass 13, count 0 2006.260.08:25:00.88#ibcon#wrote, iclass 13, count 0 2006.260.08:25:00.88#ibcon#about to read 3, iclass 13, count 0 2006.260.08:25:00.89#ibcon#read 3, iclass 13, count 0 2006.260.08:25:00.89#ibcon#about to read 4, iclass 13, count 0 2006.260.08:25:00.89#ibcon#read 4, iclass 13, count 0 2006.260.08:25:00.89#ibcon#about to read 5, iclass 13, count 0 2006.260.08:25:00.89#ibcon#read 5, iclass 13, count 0 2006.260.08:25:00.89#ibcon#about to read 6, iclass 13, count 0 2006.260.08:25:00.89#ibcon#read 6, iclass 13, count 0 2006.260.08:25:00.89#ibcon#end of sib2, iclass 13, count 0 2006.260.08:25:00.90#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:25:00.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:25:00.90#ibcon#[26=FRQ=06,772.99\r\n] 2006.260.08:25:00.90#ibcon#*before write, iclass 13, count 0 2006.260.08:25:00.90#ibcon#enter sib2, iclass 13, count 0 2006.260.08:25:00.90#ibcon#flushed, iclass 13, count 0 2006.260.08:25:00.90#ibcon#about to write, iclass 13, count 0 2006.260.08:25:00.90#ibcon#wrote, iclass 13, count 0 2006.260.08:25:00.90#ibcon#about to read 3, iclass 13, count 0 2006.260.08:25:00.93#ibcon#read 3, iclass 13, count 0 2006.260.08:25:00.93#ibcon#about to read 4, iclass 13, count 0 2006.260.08:25:00.93#ibcon#read 4, iclass 13, count 0 2006.260.08:25:00.93#ibcon#about to read 5, iclass 13, count 0 2006.260.08:25:00.93#ibcon#read 5, iclass 13, count 0 2006.260.08:25:00.93#ibcon#about to read 6, iclass 13, count 0 2006.260.08:25:00.93#ibcon#read 6, iclass 13, count 0 2006.260.08:25:00.93#ibcon#end of sib2, iclass 13, count 0 2006.260.08:25:00.93#ibcon#*after write, iclass 13, count 0 2006.260.08:25:00.94#ibcon#*before return 0, iclass 13, count 0 2006.260.08:25:00.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:00.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:00.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:25:00.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:25:00.94$vc4f8/va=6,6 2006.260.08:25:00.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.260.08:25:00.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.260.08:25:00.94#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:00.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:00.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:00.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:00.99#ibcon#enter wrdev, iclass 15, count 2 2006.260.08:25:00.99#ibcon#first serial, iclass 15, count 2 2006.260.08:25:00.99#ibcon#enter sib2, iclass 15, count 2 2006.260.08:25:00.99#ibcon#flushed, iclass 15, count 2 2006.260.08:25:00.99#ibcon#about to write, iclass 15, count 2 2006.260.08:25:00.99#ibcon#wrote, iclass 15, count 2 2006.260.08:25:00.99#ibcon#about to read 3, iclass 15, count 2 2006.260.08:25:01.01#ibcon#read 3, iclass 15, count 2 2006.260.08:25:01.01#ibcon#about to read 4, iclass 15, count 2 2006.260.08:25:01.01#ibcon#read 4, iclass 15, count 2 2006.260.08:25:01.01#ibcon#about to read 5, iclass 15, count 2 2006.260.08:25:01.02#ibcon#read 5, iclass 15, count 2 2006.260.08:25:01.02#ibcon#about to read 6, iclass 15, count 2 2006.260.08:25:01.02#ibcon#read 6, iclass 15, count 2 2006.260.08:25:01.02#ibcon#end of sib2, iclass 15, count 2 2006.260.08:25:01.02#ibcon#*mode == 0, iclass 15, count 2 2006.260.08:25:01.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.260.08:25:01.02#ibcon#[25=AT06-06\r\n] 2006.260.08:25:01.02#ibcon#*before write, iclass 15, count 2 2006.260.08:25:01.02#ibcon#enter sib2, iclass 15, count 2 2006.260.08:25:01.02#ibcon#flushed, iclass 15, count 2 2006.260.08:25:01.02#ibcon#about to write, iclass 15, count 2 2006.260.08:25:01.02#ibcon#wrote, iclass 15, count 2 2006.260.08:25:01.02#ibcon#about to read 3, iclass 15, count 2 2006.260.08:25:01.04#ibcon#read 3, iclass 15, count 2 2006.260.08:25:01.04#ibcon#about to read 4, iclass 15, count 2 2006.260.08:25:01.04#ibcon#read 4, iclass 15, count 2 2006.260.08:25:01.04#ibcon#about to read 5, iclass 15, count 2 2006.260.08:25:01.04#ibcon#read 5, iclass 15, count 2 2006.260.08:25:01.04#ibcon#about to read 6, iclass 15, count 2 2006.260.08:25:01.04#ibcon#read 6, iclass 15, count 2 2006.260.08:25:01.04#ibcon#end of sib2, iclass 15, count 2 2006.260.08:25:01.04#ibcon#*after write, iclass 15, count 2 2006.260.08:25:01.05#ibcon#*before return 0, iclass 15, count 2 2006.260.08:25:01.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:01.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:01.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.260.08:25:01.05#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:01.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:25:01.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:25:01.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:25:01.16#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:25:01.16#ibcon#first serial, iclass 15, count 0 2006.260.08:25:01.16#ibcon#enter sib2, iclass 15, count 0 2006.260.08:25:01.16#ibcon#flushed, iclass 15, count 0 2006.260.08:25:01.16#ibcon#about to write, iclass 15, count 0 2006.260.08:25:01.16#ibcon#wrote, iclass 15, count 0 2006.260.08:25:01.16#ibcon#about to read 3, iclass 15, count 0 2006.260.08:25:01.18#ibcon#read 3, iclass 15, count 0 2006.260.08:25:01.18#ibcon#about to read 4, iclass 15, count 0 2006.260.08:25:01.18#ibcon#read 4, iclass 15, count 0 2006.260.08:25:01.18#ibcon#about to read 5, iclass 15, count 0 2006.260.08:25:01.18#ibcon#read 5, iclass 15, count 0 2006.260.08:25:01.18#ibcon#about to read 6, iclass 15, count 0 2006.260.08:25:01.18#ibcon#read 6, iclass 15, count 0 2006.260.08:25:01.18#ibcon#end of sib2, iclass 15, count 0 2006.260.08:25:01.18#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:25:01.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:25:01.19#ibcon#[25=USB\r\n] 2006.260.08:25:01.19#ibcon#*before write, iclass 15, count 0 2006.260.08:25:01.19#ibcon#enter sib2, iclass 15, count 0 2006.260.08:25:01.19#ibcon#flushed, iclass 15, count 0 2006.260.08:25:01.19#ibcon#about to write, iclass 15, count 0 2006.260.08:25:01.19#ibcon#wrote, iclass 15, count 0 2006.260.08:25:01.19#ibcon#about to read 3, iclass 15, count 0 2006.260.08:25:01.21#ibcon#read 3, iclass 15, count 0 2006.260.08:25:01.21#ibcon#about to read 4, iclass 15, count 0 2006.260.08:25:01.21#ibcon#read 4, iclass 15, count 0 2006.260.08:25:01.21#ibcon#about to read 5, iclass 15, count 0 2006.260.08:25:01.21#ibcon#read 5, iclass 15, count 0 2006.260.08:25:01.21#ibcon#about to read 6, iclass 15, count 0 2006.260.08:25:01.21#ibcon#read 6, iclass 15, count 0 2006.260.08:25:01.21#ibcon#end of sib2, iclass 15, count 0 2006.260.08:25:01.21#ibcon#*after write, iclass 15, count 0 2006.260.08:25:01.21#ibcon#*before return 0, iclass 15, count 0 2006.260.08:25:01.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:25:01.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.260.08:25:01.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:25:01.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:25:01.22$vc4f8/valo=7,832.99 2006.260.08:25:01.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.260.08:25:01.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.260.08:25:01.22#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:01.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:25:01.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:25:01.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:25:01.22#ibcon#enter wrdev, iclass 17, count 0 2006.260.08:25:01.22#ibcon#first serial, iclass 17, count 0 2006.260.08:25:01.22#ibcon#enter sib2, iclass 17, count 0 2006.260.08:25:01.22#ibcon#flushed, iclass 17, count 0 2006.260.08:25:01.22#ibcon#about to write, iclass 17, count 0 2006.260.08:25:01.22#ibcon#wrote, iclass 17, count 0 2006.260.08:25:01.22#ibcon#about to read 3, iclass 17, count 0 2006.260.08:25:01.23#ibcon#read 3, iclass 17, count 0 2006.260.08:25:01.23#ibcon#about to read 4, iclass 17, count 0 2006.260.08:25:01.23#ibcon#read 4, iclass 17, count 0 2006.260.08:25:01.23#ibcon#about to read 5, iclass 17, count 0 2006.260.08:25:01.23#ibcon#read 5, iclass 17, count 0 2006.260.08:25:01.23#ibcon#about to read 6, iclass 17, count 0 2006.260.08:25:01.23#ibcon#read 6, iclass 17, count 0 2006.260.08:25:01.23#ibcon#end of sib2, iclass 17, count 0 2006.260.08:25:01.23#ibcon#*mode == 0, iclass 17, count 0 2006.260.08:25:01.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.260.08:25:01.24#ibcon#[26=FRQ=07,832.99\r\n] 2006.260.08:25:01.24#ibcon#*before write, iclass 17, count 0 2006.260.08:25:01.24#ibcon#enter sib2, iclass 17, count 0 2006.260.08:25:01.24#ibcon#flushed, iclass 17, count 0 2006.260.08:25:01.24#ibcon#about to write, iclass 17, count 0 2006.260.08:25:01.24#ibcon#wrote, iclass 17, count 0 2006.260.08:25:01.24#ibcon#about to read 3, iclass 17, count 0 2006.260.08:25:01.27#ibcon#read 3, iclass 17, count 0 2006.260.08:25:01.27#ibcon#about to read 4, iclass 17, count 0 2006.260.08:25:01.27#ibcon#read 4, iclass 17, count 0 2006.260.08:25:01.27#ibcon#about to read 5, iclass 17, count 0 2006.260.08:25:01.27#ibcon#read 5, iclass 17, count 0 2006.260.08:25:01.27#ibcon#about to read 6, iclass 17, count 0 2006.260.08:25:01.27#ibcon#read 6, iclass 17, count 0 2006.260.08:25:01.27#ibcon#end of sib2, iclass 17, count 0 2006.260.08:25:01.27#ibcon#*after write, iclass 17, count 0 2006.260.08:25:01.28#ibcon#*before return 0, iclass 17, count 0 2006.260.08:25:01.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:25:01.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.260.08:25:01.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.260.08:25:01.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.260.08:25:01.28$vc4f8/va=7,6 2006.260.08:25:01.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.260.08:25:01.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.260.08:25:01.28#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:01.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:25:01.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:25:01.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:25:01.33#ibcon#enter wrdev, iclass 19, count 2 2006.260.08:25:01.33#ibcon#first serial, iclass 19, count 2 2006.260.08:25:01.33#ibcon#enter sib2, iclass 19, count 2 2006.260.08:25:01.33#ibcon#flushed, iclass 19, count 2 2006.260.08:25:01.33#ibcon#about to write, iclass 19, count 2 2006.260.08:25:01.33#ibcon#wrote, iclass 19, count 2 2006.260.08:25:01.33#ibcon#about to read 3, iclass 19, count 2 2006.260.08:25:01.35#ibcon#read 3, iclass 19, count 2 2006.260.08:25:01.35#ibcon#about to read 4, iclass 19, count 2 2006.260.08:25:01.35#ibcon#read 4, iclass 19, count 2 2006.260.08:25:01.35#ibcon#about to read 5, iclass 19, count 2 2006.260.08:25:01.35#ibcon#read 5, iclass 19, count 2 2006.260.08:25:01.35#ibcon#about to read 6, iclass 19, count 2 2006.260.08:25:01.36#ibcon#read 6, iclass 19, count 2 2006.260.08:25:01.36#ibcon#end of sib2, iclass 19, count 2 2006.260.08:25:01.36#ibcon#*mode == 0, iclass 19, count 2 2006.260.08:25:01.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.260.08:25:01.36#ibcon#[25=AT07-06\r\n] 2006.260.08:25:01.36#ibcon#*before write, iclass 19, count 2 2006.260.08:25:01.36#ibcon#enter sib2, iclass 19, count 2 2006.260.08:25:01.36#ibcon#flushed, iclass 19, count 2 2006.260.08:25:01.36#ibcon#about to write, iclass 19, count 2 2006.260.08:25:01.36#ibcon#wrote, iclass 19, count 2 2006.260.08:25:01.36#ibcon#about to read 3, iclass 19, count 2 2006.260.08:25:01.38#ibcon#read 3, iclass 19, count 2 2006.260.08:25:01.38#ibcon#about to read 4, iclass 19, count 2 2006.260.08:25:01.38#ibcon#read 4, iclass 19, count 2 2006.260.08:25:01.38#ibcon#about to read 5, iclass 19, count 2 2006.260.08:25:01.38#ibcon#read 5, iclass 19, count 2 2006.260.08:25:01.38#ibcon#about to read 6, iclass 19, count 2 2006.260.08:25:01.38#ibcon#read 6, iclass 19, count 2 2006.260.08:25:01.38#ibcon#end of sib2, iclass 19, count 2 2006.260.08:25:01.38#ibcon#*after write, iclass 19, count 2 2006.260.08:25:01.39#ibcon#*before return 0, iclass 19, count 2 2006.260.08:25:01.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:25:01.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.260.08:25:01.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.260.08:25:01.39#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:01.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:25:01.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:25:01.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:25:01.50#ibcon#enter wrdev, iclass 19, count 0 2006.260.08:25:01.50#ibcon#first serial, iclass 19, count 0 2006.260.08:25:01.50#ibcon#enter sib2, iclass 19, count 0 2006.260.08:25:01.50#ibcon#flushed, iclass 19, count 0 2006.260.08:25:01.50#ibcon#about to write, iclass 19, count 0 2006.260.08:25:01.50#ibcon#wrote, iclass 19, count 0 2006.260.08:25:01.50#ibcon#about to read 3, iclass 19, count 0 2006.260.08:25:01.52#ibcon#read 3, iclass 19, count 0 2006.260.08:25:01.52#ibcon#about to read 4, iclass 19, count 0 2006.260.08:25:01.52#ibcon#read 4, iclass 19, count 0 2006.260.08:25:01.52#ibcon#about to read 5, iclass 19, count 0 2006.260.08:25:01.52#ibcon#read 5, iclass 19, count 0 2006.260.08:25:01.52#ibcon#about to read 6, iclass 19, count 0 2006.260.08:25:01.52#ibcon#read 6, iclass 19, count 0 2006.260.08:25:01.52#ibcon#end of sib2, iclass 19, count 0 2006.260.08:25:01.52#ibcon#*mode == 0, iclass 19, count 0 2006.260.08:25:01.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.260.08:25:01.53#ibcon#[25=USB\r\n] 2006.260.08:25:01.53#ibcon#*before write, iclass 19, count 0 2006.260.08:25:01.53#ibcon#enter sib2, iclass 19, count 0 2006.260.08:25:01.53#ibcon#flushed, iclass 19, count 0 2006.260.08:25:01.53#ibcon#about to write, iclass 19, count 0 2006.260.08:25:01.53#ibcon#wrote, iclass 19, count 0 2006.260.08:25:01.53#ibcon#about to read 3, iclass 19, count 0 2006.260.08:25:01.55#ibcon#read 3, iclass 19, count 0 2006.260.08:25:01.55#ibcon#about to read 4, iclass 19, count 0 2006.260.08:25:01.55#ibcon#read 4, iclass 19, count 0 2006.260.08:25:01.55#ibcon#about to read 5, iclass 19, count 0 2006.260.08:25:01.55#ibcon#read 5, iclass 19, count 0 2006.260.08:25:01.55#ibcon#about to read 6, iclass 19, count 0 2006.260.08:25:01.55#ibcon#read 6, iclass 19, count 0 2006.260.08:25:01.55#ibcon#end of sib2, iclass 19, count 0 2006.260.08:25:01.55#ibcon#*after write, iclass 19, count 0 2006.260.08:25:01.56#ibcon#*before return 0, iclass 19, count 0 2006.260.08:25:01.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:25:01.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.260.08:25:01.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.260.08:25:01.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.260.08:25:01.56$vc4f8/valo=8,852.99 2006.260.08:25:01.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.260.08:25:01.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.260.08:25:01.56#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:01.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:25:01.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:25:01.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:25:01.56#ibcon#enter wrdev, iclass 21, count 0 2006.260.08:25:01.56#ibcon#first serial, iclass 21, count 0 2006.260.08:25:01.56#ibcon#enter sib2, iclass 21, count 0 2006.260.08:25:01.56#ibcon#flushed, iclass 21, count 0 2006.260.08:25:01.56#ibcon#about to write, iclass 21, count 0 2006.260.08:25:01.56#ibcon#wrote, iclass 21, count 0 2006.260.08:25:01.56#ibcon#about to read 3, iclass 21, count 0 2006.260.08:25:01.57#ibcon#read 3, iclass 21, count 0 2006.260.08:25:01.57#ibcon#about to read 4, iclass 21, count 0 2006.260.08:25:01.57#ibcon#read 4, iclass 21, count 0 2006.260.08:25:01.57#ibcon#about to read 5, iclass 21, count 0 2006.260.08:25:01.57#ibcon#read 5, iclass 21, count 0 2006.260.08:25:01.57#ibcon#about to read 6, iclass 21, count 0 2006.260.08:25:01.57#ibcon#read 6, iclass 21, count 0 2006.260.08:25:01.57#ibcon#end of sib2, iclass 21, count 0 2006.260.08:25:01.58#ibcon#*mode == 0, iclass 21, count 0 2006.260.08:25:01.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.260.08:25:01.58#ibcon#[26=FRQ=08,852.99\r\n] 2006.260.08:25:01.58#ibcon#*before write, iclass 21, count 0 2006.260.08:25:01.58#ibcon#enter sib2, iclass 21, count 0 2006.260.08:25:01.58#ibcon#flushed, iclass 21, count 0 2006.260.08:25:01.58#ibcon#about to write, iclass 21, count 0 2006.260.08:25:01.58#ibcon#wrote, iclass 21, count 0 2006.260.08:25:01.58#ibcon#about to read 3, iclass 21, count 0 2006.260.08:25:01.62#ibcon#read 3, iclass 21, count 0 2006.260.08:25:01.62#ibcon#about to read 4, iclass 21, count 0 2006.260.08:25:01.62#ibcon#read 4, iclass 21, count 0 2006.260.08:25:01.62#ibcon#about to read 5, iclass 21, count 0 2006.260.08:25:01.62#ibcon#read 5, iclass 21, count 0 2006.260.08:25:01.62#ibcon#about to read 6, iclass 21, count 0 2006.260.08:25:01.62#ibcon#read 6, iclass 21, count 0 2006.260.08:25:01.62#ibcon#end of sib2, iclass 21, count 0 2006.260.08:25:01.62#ibcon#*after write, iclass 21, count 0 2006.260.08:25:01.62#ibcon#*before return 0, iclass 21, count 0 2006.260.08:25:01.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:25:01.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.260.08:25:01.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.260.08:25:01.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.260.08:25:01.62$vc4f8/va=8,6 2006.260.08:25:01.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.260.08:25:01.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.260.08:25:01.62#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:01.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:25:01.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:25:01.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:25:01.67#ibcon#enter wrdev, iclass 23, count 2 2006.260.08:25:01.67#ibcon#first serial, iclass 23, count 2 2006.260.08:25:01.67#ibcon#enter sib2, iclass 23, count 2 2006.260.08:25:01.67#ibcon#flushed, iclass 23, count 2 2006.260.08:25:01.67#ibcon#about to write, iclass 23, count 2 2006.260.08:25:01.67#ibcon#wrote, iclass 23, count 2 2006.260.08:25:01.67#ibcon#about to read 3, iclass 23, count 2 2006.260.08:25:01.69#ibcon#read 3, iclass 23, count 2 2006.260.08:25:01.69#ibcon#about to read 4, iclass 23, count 2 2006.260.08:25:01.69#ibcon#read 4, iclass 23, count 2 2006.260.08:25:01.69#ibcon#about to read 5, iclass 23, count 2 2006.260.08:25:01.69#ibcon#read 5, iclass 23, count 2 2006.260.08:25:01.69#ibcon#about to read 6, iclass 23, count 2 2006.260.08:25:01.69#ibcon#read 6, iclass 23, count 2 2006.260.08:25:01.69#ibcon#end of sib2, iclass 23, count 2 2006.260.08:25:01.69#ibcon#*mode == 0, iclass 23, count 2 2006.260.08:25:01.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.260.08:25:01.70#ibcon#[25=AT08-06\r\n] 2006.260.08:25:01.70#ibcon#*before write, iclass 23, count 2 2006.260.08:25:01.70#ibcon#enter sib2, iclass 23, count 2 2006.260.08:25:01.70#ibcon#flushed, iclass 23, count 2 2006.260.08:25:01.70#ibcon#about to write, iclass 23, count 2 2006.260.08:25:01.70#ibcon#wrote, iclass 23, count 2 2006.260.08:25:01.70#ibcon#about to read 3, iclass 23, count 2 2006.260.08:25:01.72#ibcon#read 3, iclass 23, count 2 2006.260.08:25:01.72#ibcon#about to read 4, iclass 23, count 2 2006.260.08:25:01.72#ibcon#read 4, iclass 23, count 2 2006.260.08:25:01.72#ibcon#about to read 5, iclass 23, count 2 2006.260.08:25:01.72#ibcon#read 5, iclass 23, count 2 2006.260.08:25:01.72#ibcon#about to read 6, iclass 23, count 2 2006.260.08:25:01.72#ibcon#read 6, iclass 23, count 2 2006.260.08:25:01.72#ibcon#end of sib2, iclass 23, count 2 2006.260.08:25:01.72#ibcon#*after write, iclass 23, count 2 2006.260.08:25:01.73#ibcon#*before return 0, iclass 23, count 2 2006.260.08:25:01.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:25:01.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.260.08:25:01.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.260.08:25:01.73#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:01.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:25:01.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:25:01.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:25:01.84#ibcon#enter wrdev, iclass 23, count 0 2006.260.08:25:01.84#ibcon#first serial, iclass 23, count 0 2006.260.08:25:01.84#ibcon#enter sib2, iclass 23, count 0 2006.260.08:25:01.84#ibcon#flushed, iclass 23, count 0 2006.260.08:25:01.84#ibcon#about to write, iclass 23, count 0 2006.260.08:25:01.84#ibcon#wrote, iclass 23, count 0 2006.260.08:25:01.84#ibcon#about to read 3, iclass 23, count 0 2006.260.08:25:01.86#ibcon#read 3, iclass 23, count 0 2006.260.08:25:01.86#ibcon#about to read 4, iclass 23, count 0 2006.260.08:25:01.86#ibcon#read 4, iclass 23, count 0 2006.260.08:25:01.86#ibcon#about to read 5, iclass 23, count 0 2006.260.08:25:01.86#ibcon#read 5, iclass 23, count 0 2006.260.08:25:01.86#ibcon#about to read 6, iclass 23, count 0 2006.260.08:25:01.87#ibcon#read 6, iclass 23, count 0 2006.260.08:25:01.87#ibcon#end of sib2, iclass 23, count 0 2006.260.08:25:01.87#ibcon#*mode == 0, iclass 23, count 0 2006.260.08:25:01.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.260.08:25:01.87#ibcon#[25=USB\r\n] 2006.260.08:25:01.87#ibcon#*before write, iclass 23, count 0 2006.260.08:25:01.87#ibcon#enter sib2, iclass 23, count 0 2006.260.08:25:01.87#ibcon#flushed, iclass 23, count 0 2006.260.08:25:01.87#ibcon#about to write, iclass 23, count 0 2006.260.08:25:01.87#ibcon#wrote, iclass 23, count 0 2006.260.08:25:01.87#ibcon#about to read 3, iclass 23, count 0 2006.260.08:25:01.89#ibcon#read 3, iclass 23, count 0 2006.260.08:25:01.89#ibcon#about to read 4, iclass 23, count 0 2006.260.08:25:01.89#ibcon#read 4, iclass 23, count 0 2006.260.08:25:01.89#ibcon#about to read 5, iclass 23, count 0 2006.260.08:25:01.89#ibcon#read 5, iclass 23, count 0 2006.260.08:25:01.89#ibcon#about to read 6, iclass 23, count 0 2006.260.08:25:01.89#ibcon#read 6, iclass 23, count 0 2006.260.08:25:01.89#ibcon#end of sib2, iclass 23, count 0 2006.260.08:25:01.89#ibcon#*after write, iclass 23, count 0 2006.260.08:25:01.90#ibcon#*before return 0, iclass 23, count 0 2006.260.08:25:01.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:25:01.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.260.08:25:01.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.260.08:25:01.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.260.08:25:01.90$vc4f8/vblo=1,632.99 2006.260.08:25:01.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.260.08:25:01.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.260.08:25:01.90#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:01.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:25:01.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:25:01.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:25:01.90#ibcon#enter wrdev, iclass 25, count 0 2006.260.08:25:01.90#ibcon#first serial, iclass 25, count 0 2006.260.08:25:01.90#ibcon#enter sib2, iclass 25, count 0 2006.260.08:25:01.90#ibcon#flushed, iclass 25, count 0 2006.260.08:25:01.90#ibcon#about to write, iclass 25, count 0 2006.260.08:25:01.90#ibcon#wrote, iclass 25, count 0 2006.260.08:25:01.90#ibcon#about to read 3, iclass 25, count 0 2006.260.08:25:01.91#ibcon#read 3, iclass 25, count 0 2006.260.08:25:01.91#ibcon#about to read 4, iclass 25, count 0 2006.260.08:25:01.91#ibcon#read 4, iclass 25, count 0 2006.260.08:25:01.91#ibcon#about to read 5, iclass 25, count 0 2006.260.08:25:01.91#ibcon#read 5, iclass 25, count 0 2006.260.08:25:01.91#ibcon#about to read 6, iclass 25, count 0 2006.260.08:25:01.91#ibcon#read 6, iclass 25, count 0 2006.260.08:25:01.91#ibcon#end of sib2, iclass 25, count 0 2006.260.08:25:01.91#ibcon#*mode == 0, iclass 25, count 0 2006.260.08:25:01.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.260.08:25:01.92#ibcon#[28=FRQ=01,632.99\r\n] 2006.260.08:25:01.92#ibcon#*before write, iclass 25, count 0 2006.260.08:25:01.92#ibcon#enter sib2, iclass 25, count 0 2006.260.08:25:01.92#ibcon#flushed, iclass 25, count 0 2006.260.08:25:01.92#ibcon#about to write, iclass 25, count 0 2006.260.08:25:01.92#ibcon#wrote, iclass 25, count 0 2006.260.08:25:01.92#ibcon#about to read 3, iclass 25, count 0 2006.260.08:25:01.95#ibcon#read 3, iclass 25, count 0 2006.260.08:25:01.95#ibcon#about to read 4, iclass 25, count 0 2006.260.08:25:01.95#ibcon#read 4, iclass 25, count 0 2006.260.08:25:01.95#ibcon#about to read 5, iclass 25, count 0 2006.260.08:25:01.95#ibcon#read 5, iclass 25, count 0 2006.260.08:25:01.95#ibcon#about to read 6, iclass 25, count 0 2006.260.08:25:01.95#ibcon#read 6, iclass 25, count 0 2006.260.08:25:01.95#ibcon#end of sib2, iclass 25, count 0 2006.260.08:25:01.95#ibcon#*after write, iclass 25, count 0 2006.260.08:25:01.96#ibcon#*before return 0, iclass 25, count 0 2006.260.08:25:01.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:25:01.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.260.08:25:01.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.260.08:25:01.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.260.08:25:01.96$vc4f8/vb=1,4 2006.260.08:25:01.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.260.08:25:01.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.260.08:25:01.96#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:01.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:25:01.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:25:01.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:25:01.96#ibcon#enter wrdev, iclass 27, count 2 2006.260.08:25:01.96#ibcon#first serial, iclass 27, count 2 2006.260.08:25:01.96#ibcon#enter sib2, iclass 27, count 2 2006.260.08:25:01.96#ibcon#flushed, iclass 27, count 2 2006.260.08:25:01.96#ibcon#about to write, iclass 27, count 2 2006.260.08:25:01.96#ibcon#wrote, iclass 27, count 2 2006.260.08:25:01.96#ibcon#about to read 3, iclass 27, count 2 2006.260.08:25:01.97#ibcon#read 3, iclass 27, count 2 2006.260.08:25:01.97#ibcon#about to read 4, iclass 27, count 2 2006.260.08:25:01.97#ibcon#read 4, iclass 27, count 2 2006.260.08:25:01.97#ibcon#about to read 5, iclass 27, count 2 2006.260.08:25:01.97#ibcon#read 5, iclass 27, count 2 2006.260.08:25:01.97#ibcon#about to read 6, iclass 27, count 2 2006.260.08:25:01.97#ibcon#read 6, iclass 27, count 2 2006.260.08:25:01.97#ibcon#end of sib2, iclass 27, count 2 2006.260.08:25:01.97#ibcon#*mode == 0, iclass 27, count 2 2006.260.08:25:01.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.260.08:25:01.98#ibcon#[27=AT01-04\r\n] 2006.260.08:25:01.98#ibcon#*before write, iclass 27, count 2 2006.260.08:25:01.98#ibcon#enter sib2, iclass 27, count 2 2006.260.08:25:01.98#ibcon#flushed, iclass 27, count 2 2006.260.08:25:01.98#ibcon#about to write, iclass 27, count 2 2006.260.08:25:01.98#ibcon#wrote, iclass 27, count 2 2006.260.08:25:01.98#ibcon#about to read 3, iclass 27, count 2 2006.260.08:25:02.00#ibcon#read 3, iclass 27, count 2 2006.260.08:25:02.00#ibcon#about to read 4, iclass 27, count 2 2006.260.08:25:02.00#ibcon#read 4, iclass 27, count 2 2006.260.08:25:02.00#ibcon#about to read 5, iclass 27, count 2 2006.260.08:25:02.00#ibcon#read 5, iclass 27, count 2 2006.260.08:25:02.00#ibcon#about to read 6, iclass 27, count 2 2006.260.08:25:02.00#ibcon#read 6, iclass 27, count 2 2006.260.08:25:02.00#ibcon#end of sib2, iclass 27, count 2 2006.260.08:25:02.00#ibcon#*after write, iclass 27, count 2 2006.260.08:25:02.01#ibcon#*before return 0, iclass 27, count 2 2006.260.08:25:02.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:25:02.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.260.08:25:02.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.260.08:25:02.01#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:02.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:25:02.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:25:02.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:25:02.12#ibcon#enter wrdev, iclass 27, count 0 2006.260.08:25:02.12#ibcon#first serial, iclass 27, count 0 2006.260.08:25:02.12#ibcon#enter sib2, iclass 27, count 0 2006.260.08:25:02.12#ibcon#flushed, iclass 27, count 0 2006.260.08:25:02.12#ibcon#about to write, iclass 27, count 0 2006.260.08:25:02.12#ibcon#wrote, iclass 27, count 0 2006.260.08:25:02.12#ibcon#about to read 3, iclass 27, count 0 2006.260.08:25:02.14#ibcon#read 3, iclass 27, count 0 2006.260.08:25:02.14#ibcon#about to read 4, iclass 27, count 0 2006.260.08:25:02.14#ibcon#read 4, iclass 27, count 0 2006.260.08:25:02.14#ibcon#about to read 5, iclass 27, count 0 2006.260.08:25:02.14#ibcon#read 5, iclass 27, count 0 2006.260.08:25:02.14#ibcon#about to read 6, iclass 27, count 0 2006.260.08:25:02.14#ibcon#read 6, iclass 27, count 0 2006.260.08:25:02.14#ibcon#end of sib2, iclass 27, count 0 2006.260.08:25:02.14#ibcon#*mode == 0, iclass 27, count 0 2006.260.08:25:02.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.260.08:25:02.15#ibcon#[27=USB\r\n] 2006.260.08:25:02.15#ibcon#*before write, iclass 27, count 0 2006.260.08:25:02.15#ibcon#enter sib2, iclass 27, count 0 2006.260.08:25:02.15#ibcon#flushed, iclass 27, count 0 2006.260.08:25:02.15#ibcon#about to write, iclass 27, count 0 2006.260.08:25:02.15#ibcon#wrote, iclass 27, count 0 2006.260.08:25:02.15#ibcon#about to read 3, iclass 27, count 0 2006.260.08:25:02.17#ibcon#read 3, iclass 27, count 0 2006.260.08:25:02.17#ibcon#about to read 4, iclass 27, count 0 2006.260.08:25:02.17#ibcon#read 4, iclass 27, count 0 2006.260.08:25:02.17#ibcon#about to read 5, iclass 27, count 0 2006.260.08:25:02.17#ibcon#read 5, iclass 27, count 0 2006.260.08:25:02.17#ibcon#about to read 6, iclass 27, count 0 2006.260.08:25:02.18#ibcon#read 6, iclass 27, count 0 2006.260.08:25:02.18#ibcon#end of sib2, iclass 27, count 0 2006.260.08:25:02.18#ibcon#*after write, iclass 27, count 0 2006.260.08:25:02.18#ibcon#*before return 0, iclass 27, count 0 2006.260.08:25:02.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:25:02.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.260.08:25:02.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.260.08:25:02.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.260.08:25:02.18$vc4f8/vblo=2,640.99 2006.260.08:25:02.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.260.08:25:02.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.260.08:25:02.18#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:02.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:25:02.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:25:02.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:25:02.18#ibcon#enter wrdev, iclass 29, count 0 2006.260.08:25:02.18#ibcon#first serial, iclass 29, count 0 2006.260.08:25:02.18#ibcon#enter sib2, iclass 29, count 0 2006.260.08:25:02.18#ibcon#flushed, iclass 29, count 0 2006.260.08:25:02.18#ibcon#about to write, iclass 29, count 0 2006.260.08:25:02.18#ibcon#wrote, iclass 29, count 0 2006.260.08:25:02.18#ibcon#about to read 3, iclass 29, count 0 2006.260.08:25:02.19#ibcon#read 3, iclass 29, count 0 2006.260.08:25:02.19#ibcon#about to read 4, iclass 29, count 0 2006.260.08:25:02.19#ibcon#read 4, iclass 29, count 0 2006.260.08:25:02.19#ibcon#about to read 5, iclass 29, count 0 2006.260.08:25:02.19#ibcon#read 5, iclass 29, count 0 2006.260.08:25:02.19#ibcon#about to read 6, iclass 29, count 0 2006.260.08:25:02.19#ibcon#read 6, iclass 29, count 0 2006.260.08:25:02.19#ibcon#end of sib2, iclass 29, count 0 2006.260.08:25:02.19#ibcon#*mode == 0, iclass 29, count 0 2006.260.08:25:02.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.260.08:25:02.20#ibcon#[28=FRQ=02,640.99\r\n] 2006.260.08:25:02.20#ibcon#*before write, iclass 29, count 0 2006.260.08:25:02.20#ibcon#enter sib2, iclass 29, count 0 2006.260.08:25:02.20#ibcon#flushed, iclass 29, count 0 2006.260.08:25:02.20#ibcon#about to write, iclass 29, count 0 2006.260.08:25:02.20#ibcon#wrote, iclass 29, count 0 2006.260.08:25:02.20#ibcon#about to read 3, iclass 29, count 0 2006.260.08:25:02.23#ibcon#read 3, iclass 29, count 0 2006.260.08:25:02.23#ibcon#about to read 4, iclass 29, count 0 2006.260.08:25:02.23#ibcon#read 4, iclass 29, count 0 2006.260.08:25:02.23#ibcon#about to read 5, iclass 29, count 0 2006.260.08:25:02.23#ibcon#read 5, iclass 29, count 0 2006.260.08:25:02.23#ibcon#about to read 6, iclass 29, count 0 2006.260.08:25:02.23#ibcon#read 6, iclass 29, count 0 2006.260.08:25:02.23#ibcon#end of sib2, iclass 29, count 0 2006.260.08:25:02.23#ibcon#*after write, iclass 29, count 0 2006.260.08:25:02.24#ibcon#*before return 0, iclass 29, count 0 2006.260.08:25:02.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:25:02.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.260.08:25:02.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.260.08:25:02.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.260.08:25:02.24$vc4f8/vb=2,5 2006.260.08:25:02.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.260.08:25:02.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.260.08:25:02.24#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:02.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:25:02.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:25:02.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:25:02.29#ibcon#enter wrdev, iclass 31, count 2 2006.260.08:25:02.29#ibcon#first serial, iclass 31, count 2 2006.260.08:25:02.29#ibcon#enter sib2, iclass 31, count 2 2006.260.08:25:02.29#ibcon#flushed, iclass 31, count 2 2006.260.08:25:02.29#ibcon#about to write, iclass 31, count 2 2006.260.08:25:02.29#ibcon#wrote, iclass 31, count 2 2006.260.08:25:02.29#ibcon#about to read 3, iclass 31, count 2 2006.260.08:25:02.31#ibcon#read 3, iclass 31, count 2 2006.260.08:25:02.31#ibcon#about to read 4, iclass 31, count 2 2006.260.08:25:02.31#ibcon#read 4, iclass 31, count 2 2006.260.08:25:02.31#ibcon#about to read 5, iclass 31, count 2 2006.260.08:25:02.31#ibcon#read 5, iclass 31, count 2 2006.260.08:25:02.31#ibcon#about to read 6, iclass 31, count 2 2006.260.08:25:02.31#ibcon#read 6, iclass 31, count 2 2006.260.08:25:02.31#ibcon#end of sib2, iclass 31, count 2 2006.260.08:25:02.31#ibcon#*mode == 0, iclass 31, count 2 2006.260.08:25:02.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.260.08:25:02.32#ibcon#[27=AT02-05\r\n] 2006.260.08:25:02.32#ibcon#*before write, iclass 31, count 2 2006.260.08:25:02.32#ibcon#enter sib2, iclass 31, count 2 2006.260.08:25:02.32#ibcon#flushed, iclass 31, count 2 2006.260.08:25:02.32#ibcon#about to write, iclass 31, count 2 2006.260.08:25:02.32#ibcon#wrote, iclass 31, count 2 2006.260.08:25:02.32#ibcon#about to read 3, iclass 31, count 2 2006.260.08:25:02.34#ibcon#read 3, iclass 31, count 2 2006.260.08:25:02.34#ibcon#about to read 4, iclass 31, count 2 2006.260.08:25:02.34#ibcon#read 4, iclass 31, count 2 2006.260.08:25:02.34#ibcon#about to read 5, iclass 31, count 2 2006.260.08:25:02.34#ibcon#read 5, iclass 31, count 2 2006.260.08:25:02.34#ibcon#about to read 6, iclass 31, count 2 2006.260.08:25:02.34#ibcon#read 6, iclass 31, count 2 2006.260.08:25:02.34#ibcon#end of sib2, iclass 31, count 2 2006.260.08:25:02.34#ibcon#*after write, iclass 31, count 2 2006.260.08:25:02.34#ibcon#*before return 0, iclass 31, count 2 2006.260.08:25:02.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:25:02.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.260.08:25:02.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.260.08:25:02.35#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:02.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:25:02.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:25:02.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:25:02.46#ibcon#enter wrdev, iclass 31, count 0 2006.260.08:25:02.46#ibcon#first serial, iclass 31, count 0 2006.260.08:25:02.46#ibcon#enter sib2, iclass 31, count 0 2006.260.08:25:02.46#ibcon#flushed, iclass 31, count 0 2006.260.08:25:02.46#ibcon#about to write, iclass 31, count 0 2006.260.08:25:02.46#ibcon#wrote, iclass 31, count 0 2006.260.08:25:02.46#ibcon#about to read 3, iclass 31, count 0 2006.260.08:25:02.48#ibcon#read 3, iclass 31, count 0 2006.260.08:25:02.48#ibcon#about to read 4, iclass 31, count 0 2006.260.08:25:02.48#ibcon#read 4, iclass 31, count 0 2006.260.08:25:02.48#ibcon#about to read 5, iclass 31, count 0 2006.260.08:25:02.48#ibcon#read 5, iclass 31, count 0 2006.260.08:25:02.48#ibcon#about to read 6, iclass 31, count 0 2006.260.08:25:02.49#ibcon#read 6, iclass 31, count 0 2006.260.08:25:02.49#ibcon#end of sib2, iclass 31, count 0 2006.260.08:25:02.49#ibcon#*mode == 0, iclass 31, count 0 2006.260.08:25:02.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.260.08:25:02.49#ibcon#[27=USB\r\n] 2006.260.08:25:02.49#ibcon#*before write, iclass 31, count 0 2006.260.08:25:02.49#ibcon#enter sib2, iclass 31, count 0 2006.260.08:25:02.49#ibcon#flushed, iclass 31, count 0 2006.260.08:25:02.49#ibcon#about to write, iclass 31, count 0 2006.260.08:25:02.49#ibcon#wrote, iclass 31, count 0 2006.260.08:25:02.49#ibcon#about to read 3, iclass 31, count 0 2006.260.08:25:02.51#ibcon#read 3, iclass 31, count 0 2006.260.08:25:02.51#ibcon#about to read 4, iclass 31, count 0 2006.260.08:25:02.51#ibcon#read 4, iclass 31, count 0 2006.260.08:25:02.51#ibcon#about to read 5, iclass 31, count 0 2006.260.08:25:02.51#ibcon#read 5, iclass 31, count 0 2006.260.08:25:02.51#ibcon#about to read 6, iclass 31, count 0 2006.260.08:25:02.51#ibcon#read 6, iclass 31, count 0 2006.260.08:25:02.51#ibcon#end of sib2, iclass 31, count 0 2006.260.08:25:02.51#ibcon#*after write, iclass 31, count 0 2006.260.08:25:02.52#ibcon#*before return 0, iclass 31, count 0 2006.260.08:25:02.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:25:02.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.260.08:25:02.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.260.08:25:02.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.260.08:25:02.52$vc4f8/vblo=3,656.99 2006.260.08:25:02.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.260.08:25:02.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.260.08:25:02.52#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:02.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:25:02.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:25:02.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:25:02.52#ibcon#enter wrdev, iclass 33, count 0 2006.260.08:25:02.52#ibcon#first serial, iclass 33, count 0 2006.260.08:25:02.52#ibcon#enter sib2, iclass 33, count 0 2006.260.08:25:02.52#ibcon#flushed, iclass 33, count 0 2006.260.08:25:02.52#ibcon#about to write, iclass 33, count 0 2006.260.08:25:02.52#ibcon#wrote, iclass 33, count 0 2006.260.08:25:02.52#ibcon#about to read 3, iclass 33, count 0 2006.260.08:25:02.53#ibcon#read 3, iclass 33, count 0 2006.260.08:25:02.53#ibcon#about to read 4, iclass 33, count 0 2006.260.08:25:02.53#ibcon#read 4, iclass 33, count 0 2006.260.08:25:02.53#ibcon#about to read 5, iclass 33, count 0 2006.260.08:25:02.53#ibcon#read 5, iclass 33, count 0 2006.260.08:25:02.53#ibcon#about to read 6, iclass 33, count 0 2006.260.08:25:02.53#ibcon#read 6, iclass 33, count 0 2006.260.08:25:02.53#ibcon#end of sib2, iclass 33, count 0 2006.260.08:25:02.53#ibcon#*mode == 0, iclass 33, count 0 2006.260.08:25:02.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.260.08:25:02.54#ibcon#[28=FRQ=03,656.99\r\n] 2006.260.08:25:02.54#ibcon#*before write, iclass 33, count 0 2006.260.08:25:02.54#ibcon#enter sib2, iclass 33, count 0 2006.260.08:25:02.54#ibcon#flushed, iclass 33, count 0 2006.260.08:25:02.54#ibcon#about to write, iclass 33, count 0 2006.260.08:25:02.54#ibcon#wrote, iclass 33, count 0 2006.260.08:25:02.54#ibcon#about to read 3, iclass 33, count 0 2006.260.08:25:02.57#ibcon#read 3, iclass 33, count 0 2006.260.08:25:02.57#ibcon#about to read 4, iclass 33, count 0 2006.260.08:25:02.57#ibcon#read 4, iclass 33, count 0 2006.260.08:25:02.57#ibcon#about to read 5, iclass 33, count 0 2006.260.08:25:02.57#ibcon#read 5, iclass 33, count 0 2006.260.08:25:02.57#ibcon#about to read 6, iclass 33, count 0 2006.260.08:25:02.57#ibcon#read 6, iclass 33, count 0 2006.260.08:25:02.57#ibcon#end of sib2, iclass 33, count 0 2006.260.08:25:02.57#ibcon#*after write, iclass 33, count 0 2006.260.08:25:02.58#ibcon#*before return 0, iclass 33, count 0 2006.260.08:25:02.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:25:02.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.260.08:25:02.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.260.08:25:02.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.260.08:25:02.58$vc4f8/vb=3,4 2006.260.08:25:02.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.260.08:25:02.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.260.08:25:02.58#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:02.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:25:02.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:25:02.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:25:02.63#ibcon#enter wrdev, iclass 35, count 2 2006.260.08:25:02.63#ibcon#first serial, iclass 35, count 2 2006.260.08:25:02.63#ibcon#enter sib2, iclass 35, count 2 2006.260.08:25:02.63#ibcon#flushed, iclass 35, count 2 2006.260.08:25:02.63#ibcon#about to write, iclass 35, count 2 2006.260.08:25:02.63#ibcon#wrote, iclass 35, count 2 2006.260.08:25:02.64#ibcon#about to read 3, iclass 35, count 2 2006.260.08:25:02.65#ibcon#read 3, iclass 35, count 2 2006.260.08:25:02.65#ibcon#about to read 4, iclass 35, count 2 2006.260.08:25:02.65#ibcon#read 4, iclass 35, count 2 2006.260.08:25:02.65#ibcon#about to read 5, iclass 35, count 2 2006.260.08:25:02.65#ibcon#read 5, iclass 35, count 2 2006.260.08:25:02.65#ibcon#about to read 6, iclass 35, count 2 2006.260.08:25:02.65#ibcon#read 6, iclass 35, count 2 2006.260.08:25:02.65#ibcon#end of sib2, iclass 35, count 2 2006.260.08:25:02.65#ibcon#*mode == 0, iclass 35, count 2 2006.260.08:25:02.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.260.08:25:02.66#ibcon#[27=AT03-04\r\n] 2006.260.08:25:02.66#ibcon#*before write, iclass 35, count 2 2006.260.08:25:02.66#ibcon#enter sib2, iclass 35, count 2 2006.260.08:25:02.66#ibcon#flushed, iclass 35, count 2 2006.260.08:25:02.66#ibcon#about to write, iclass 35, count 2 2006.260.08:25:02.66#ibcon#wrote, iclass 35, count 2 2006.260.08:25:02.66#ibcon#about to read 3, iclass 35, count 2 2006.260.08:25:02.68#ibcon#read 3, iclass 35, count 2 2006.260.08:25:02.68#ibcon#about to read 4, iclass 35, count 2 2006.260.08:25:02.68#ibcon#read 4, iclass 35, count 2 2006.260.08:25:02.68#ibcon#about to read 5, iclass 35, count 2 2006.260.08:25:02.68#ibcon#read 5, iclass 35, count 2 2006.260.08:25:02.68#ibcon#about to read 6, iclass 35, count 2 2006.260.08:25:02.68#ibcon#read 6, iclass 35, count 2 2006.260.08:25:02.68#ibcon#end of sib2, iclass 35, count 2 2006.260.08:25:02.69#ibcon#*after write, iclass 35, count 2 2006.260.08:25:02.69#ibcon#*before return 0, iclass 35, count 2 2006.260.08:25:02.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:25:02.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.260.08:25:02.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.260.08:25:02.69#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:02.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:25:02.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:25:02.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:25:02.80#ibcon#enter wrdev, iclass 35, count 0 2006.260.08:25:02.80#ibcon#first serial, iclass 35, count 0 2006.260.08:25:02.80#ibcon#enter sib2, iclass 35, count 0 2006.260.08:25:02.80#ibcon#flushed, iclass 35, count 0 2006.260.08:25:02.80#ibcon#about to write, iclass 35, count 0 2006.260.08:25:02.80#ibcon#wrote, iclass 35, count 0 2006.260.08:25:02.80#ibcon#about to read 3, iclass 35, count 0 2006.260.08:25:02.82#ibcon#read 3, iclass 35, count 0 2006.260.08:25:02.82#ibcon#about to read 4, iclass 35, count 0 2006.260.08:25:02.82#ibcon#read 4, iclass 35, count 0 2006.260.08:25:02.82#ibcon#about to read 5, iclass 35, count 0 2006.260.08:25:02.82#ibcon#read 5, iclass 35, count 0 2006.260.08:25:02.82#ibcon#about to read 6, iclass 35, count 0 2006.260.08:25:02.82#ibcon#read 6, iclass 35, count 0 2006.260.08:25:02.82#ibcon#end of sib2, iclass 35, count 0 2006.260.08:25:02.82#ibcon#*mode == 0, iclass 35, count 0 2006.260.08:25:02.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.260.08:25:02.83#ibcon#[27=USB\r\n] 2006.260.08:25:02.83#ibcon#*before write, iclass 35, count 0 2006.260.08:25:02.83#ibcon#enter sib2, iclass 35, count 0 2006.260.08:25:02.83#ibcon#flushed, iclass 35, count 0 2006.260.08:25:02.83#ibcon#about to write, iclass 35, count 0 2006.260.08:25:02.83#ibcon#wrote, iclass 35, count 0 2006.260.08:25:02.83#ibcon#about to read 3, iclass 35, count 0 2006.260.08:25:02.85#ibcon#read 3, iclass 35, count 0 2006.260.08:25:02.85#ibcon#about to read 4, iclass 35, count 0 2006.260.08:25:02.85#ibcon#read 4, iclass 35, count 0 2006.260.08:25:02.85#ibcon#about to read 5, iclass 35, count 0 2006.260.08:25:02.85#ibcon#read 5, iclass 35, count 0 2006.260.08:25:02.85#ibcon#about to read 6, iclass 35, count 0 2006.260.08:25:02.85#ibcon#read 6, iclass 35, count 0 2006.260.08:25:02.85#ibcon#end of sib2, iclass 35, count 0 2006.260.08:25:02.85#ibcon#*after write, iclass 35, count 0 2006.260.08:25:02.86#ibcon#*before return 0, iclass 35, count 0 2006.260.08:25:02.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:25:02.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.260.08:25:02.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.260.08:25:02.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.260.08:25:02.86$vc4f8/vblo=4,712.99 2006.260.08:25:02.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.260.08:25:02.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.260.08:25:02.86#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:02.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:25:02.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:25:02.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:25:02.86#ibcon#enter wrdev, iclass 37, count 0 2006.260.08:25:02.86#ibcon#first serial, iclass 37, count 0 2006.260.08:25:02.86#ibcon#enter sib2, iclass 37, count 0 2006.260.08:25:02.86#ibcon#flushed, iclass 37, count 0 2006.260.08:25:02.86#ibcon#about to write, iclass 37, count 0 2006.260.08:25:02.86#ibcon#wrote, iclass 37, count 0 2006.260.08:25:02.86#ibcon#about to read 3, iclass 37, count 0 2006.260.08:25:02.87#ibcon#read 3, iclass 37, count 0 2006.260.08:25:02.87#ibcon#about to read 4, iclass 37, count 0 2006.260.08:25:02.87#ibcon#read 4, iclass 37, count 0 2006.260.08:25:02.87#ibcon#about to read 5, iclass 37, count 0 2006.260.08:25:02.87#ibcon#read 5, iclass 37, count 0 2006.260.08:25:02.87#ibcon#about to read 6, iclass 37, count 0 2006.260.08:25:02.87#ibcon#read 6, iclass 37, count 0 2006.260.08:25:02.87#ibcon#end of sib2, iclass 37, count 0 2006.260.08:25:02.87#ibcon#*mode == 0, iclass 37, count 0 2006.260.08:25:02.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.260.08:25:02.88#ibcon#[28=FRQ=04,712.99\r\n] 2006.260.08:25:02.88#ibcon#*before write, iclass 37, count 0 2006.260.08:25:02.88#ibcon#enter sib2, iclass 37, count 0 2006.260.08:25:02.88#ibcon#flushed, iclass 37, count 0 2006.260.08:25:02.88#ibcon#about to write, iclass 37, count 0 2006.260.08:25:02.88#ibcon#wrote, iclass 37, count 0 2006.260.08:25:02.88#ibcon#about to read 3, iclass 37, count 0 2006.260.08:25:02.91#ibcon#read 3, iclass 37, count 0 2006.260.08:25:02.91#ibcon#about to read 4, iclass 37, count 0 2006.260.08:25:02.91#ibcon#read 4, iclass 37, count 0 2006.260.08:25:02.91#ibcon#about to read 5, iclass 37, count 0 2006.260.08:25:02.91#ibcon#read 5, iclass 37, count 0 2006.260.08:25:02.91#ibcon#about to read 6, iclass 37, count 0 2006.260.08:25:02.91#ibcon#read 6, iclass 37, count 0 2006.260.08:25:02.91#ibcon#end of sib2, iclass 37, count 0 2006.260.08:25:02.91#ibcon#*after write, iclass 37, count 0 2006.260.08:25:02.92#ibcon#*before return 0, iclass 37, count 0 2006.260.08:25:02.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:25:02.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.260.08:25:02.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.260.08:25:02.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.260.08:25:02.92$vc4f8/vb=4,5 2006.260.08:25:02.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.260.08:25:02.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.260.08:25:02.92#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:02.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:25:02.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:25:02.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:25:02.97#ibcon#enter wrdev, iclass 39, count 2 2006.260.08:25:02.97#ibcon#first serial, iclass 39, count 2 2006.260.08:25:02.97#ibcon#enter sib2, iclass 39, count 2 2006.260.08:25:02.97#ibcon#flushed, iclass 39, count 2 2006.260.08:25:02.97#ibcon#about to write, iclass 39, count 2 2006.260.08:25:02.98#ibcon#wrote, iclass 39, count 2 2006.260.08:25:02.98#ibcon#about to read 3, iclass 39, count 2 2006.260.08:25:02.99#ibcon#read 3, iclass 39, count 2 2006.260.08:25:02.99#ibcon#about to read 4, iclass 39, count 2 2006.260.08:25:02.99#ibcon#read 4, iclass 39, count 2 2006.260.08:25:02.99#ibcon#about to read 5, iclass 39, count 2 2006.260.08:25:02.99#ibcon#read 5, iclass 39, count 2 2006.260.08:25:02.99#ibcon#about to read 6, iclass 39, count 2 2006.260.08:25:02.99#ibcon#read 6, iclass 39, count 2 2006.260.08:25:02.99#ibcon#end of sib2, iclass 39, count 2 2006.260.08:25:02.99#ibcon#*mode == 0, iclass 39, count 2 2006.260.08:25:02.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.260.08:25:03.00#ibcon#[27=AT04-05\r\n] 2006.260.08:25:03.00#ibcon#*before write, iclass 39, count 2 2006.260.08:25:03.00#ibcon#enter sib2, iclass 39, count 2 2006.260.08:25:03.00#ibcon#flushed, iclass 39, count 2 2006.260.08:25:03.00#ibcon#about to write, iclass 39, count 2 2006.260.08:25:03.00#ibcon#wrote, iclass 39, count 2 2006.260.08:25:03.00#ibcon#about to read 3, iclass 39, count 2 2006.260.08:25:03.02#ibcon#read 3, iclass 39, count 2 2006.260.08:25:03.02#ibcon#about to read 4, iclass 39, count 2 2006.260.08:25:03.02#ibcon#read 4, iclass 39, count 2 2006.260.08:25:03.02#ibcon#about to read 5, iclass 39, count 2 2006.260.08:25:03.02#ibcon#read 5, iclass 39, count 2 2006.260.08:25:03.02#ibcon#about to read 6, iclass 39, count 2 2006.260.08:25:03.02#ibcon#read 6, iclass 39, count 2 2006.260.08:25:03.02#ibcon#end of sib2, iclass 39, count 2 2006.260.08:25:03.02#ibcon#*after write, iclass 39, count 2 2006.260.08:25:03.03#ibcon#*before return 0, iclass 39, count 2 2006.260.08:25:03.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:25:03.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.260.08:25:03.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.260.08:25:03.03#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:03.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:25:03.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:25:03.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:25:03.14#ibcon#enter wrdev, iclass 39, count 0 2006.260.08:25:03.14#ibcon#first serial, iclass 39, count 0 2006.260.08:25:03.14#ibcon#enter sib2, iclass 39, count 0 2006.260.08:25:03.14#ibcon#flushed, iclass 39, count 0 2006.260.08:25:03.14#ibcon#about to write, iclass 39, count 0 2006.260.08:25:03.14#ibcon#wrote, iclass 39, count 0 2006.260.08:25:03.14#ibcon#about to read 3, iclass 39, count 0 2006.260.08:25:03.16#ibcon#read 3, iclass 39, count 0 2006.260.08:25:03.16#ibcon#about to read 4, iclass 39, count 0 2006.260.08:25:03.16#ibcon#read 4, iclass 39, count 0 2006.260.08:25:03.16#ibcon#about to read 5, iclass 39, count 0 2006.260.08:25:03.16#ibcon#read 5, iclass 39, count 0 2006.260.08:25:03.16#ibcon#about to read 6, iclass 39, count 0 2006.260.08:25:03.16#ibcon#read 6, iclass 39, count 0 2006.260.08:25:03.16#ibcon#end of sib2, iclass 39, count 0 2006.260.08:25:03.16#ibcon#*mode == 0, iclass 39, count 0 2006.260.08:25:03.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.260.08:25:03.17#ibcon#[27=USB\r\n] 2006.260.08:25:03.17#ibcon#*before write, iclass 39, count 0 2006.260.08:25:03.17#ibcon#enter sib2, iclass 39, count 0 2006.260.08:25:03.17#ibcon#flushed, iclass 39, count 0 2006.260.08:25:03.17#ibcon#about to write, iclass 39, count 0 2006.260.08:25:03.17#ibcon#wrote, iclass 39, count 0 2006.260.08:25:03.17#ibcon#about to read 3, iclass 39, count 0 2006.260.08:25:03.20#ibcon#read 3, iclass 39, count 0 2006.260.08:25:03.20#ibcon#about to read 4, iclass 39, count 0 2006.260.08:25:03.20#ibcon#read 4, iclass 39, count 0 2006.260.08:25:03.20#ibcon#about to read 5, iclass 39, count 0 2006.260.08:25:03.20#ibcon#read 5, iclass 39, count 0 2006.260.08:25:03.20#ibcon#about to read 6, iclass 39, count 0 2006.260.08:25:03.20#ibcon#read 6, iclass 39, count 0 2006.260.08:25:03.20#ibcon#end of sib2, iclass 39, count 0 2006.260.08:25:03.20#ibcon#*after write, iclass 39, count 0 2006.260.08:25:03.20#ibcon#*before return 0, iclass 39, count 0 2006.260.08:25:03.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:25:03.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.260.08:25:03.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.260.08:25:03.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.260.08:25:03.20$vc4f8/vblo=5,744.99 2006.260.08:25:03.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.260.08:25:03.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.260.08:25:03.20#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:03.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:03.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:03.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:03.20#ibcon#enter wrdev, iclass 3, count 0 2006.260.08:25:03.20#ibcon#first serial, iclass 3, count 0 2006.260.08:25:03.20#ibcon#enter sib2, iclass 3, count 0 2006.260.08:25:03.20#ibcon#flushed, iclass 3, count 0 2006.260.08:25:03.20#ibcon#about to write, iclass 3, count 0 2006.260.08:25:03.20#ibcon#wrote, iclass 3, count 0 2006.260.08:25:03.20#ibcon#about to read 3, iclass 3, count 0 2006.260.08:25:03.21#ibcon#read 3, iclass 3, count 0 2006.260.08:25:03.21#ibcon#about to read 4, iclass 3, count 0 2006.260.08:25:03.21#ibcon#read 4, iclass 3, count 0 2006.260.08:25:03.21#ibcon#about to read 5, iclass 3, count 0 2006.260.08:25:03.21#ibcon#read 5, iclass 3, count 0 2006.260.08:25:03.21#ibcon#about to read 6, iclass 3, count 0 2006.260.08:25:03.21#ibcon#read 6, iclass 3, count 0 2006.260.08:25:03.21#ibcon#end of sib2, iclass 3, count 0 2006.260.08:25:03.21#ibcon#*mode == 0, iclass 3, count 0 2006.260.08:25:03.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.260.08:25:03.22#ibcon#[28=FRQ=05,744.99\r\n] 2006.260.08:25:03.22#ibcon#*before write, iclass 3, count 0 2006.260.08:25:03.22#ibcon#enter sib2, iclass 3, count 0 2006.260.08:25:03.22#ibcon#flushed, iclass 3, count 0 2006.260.08:25:03.22#ibcon#about to write, iclass 3, count 0 2006.260.08:25:03.22#ibcon#wrote, iclass 3, count 0 2006.260.08:25:03.22#ibcon#about to read 3, iclass 3, count 0 2006.260.08:25:03.25#ibcon#read 3, iclass 3, count 0 2006.260.08:25:03.25#ibcon#about to read 4, iclass 3, count 0 2006.260.08:25:03.25#ibcon#read 4, iclass 3, count 0 2006.260.08:25:03.25#ibcon#about to read 5, iclass 3, count 0 2006.260.08:25:03.25#ibcon#read 5, iclass 3, count 0 2006.260.08:25:03.25#ibcon#about to read 6, iclass 3, count 0 2006.260.08:25:03.26#ibcon#read 6, iclass 3, count 0 2006.260.08:25:03.26#ibcon#end of sib2, iclass 3, count 0 2006.260.08:25:03.26#ibcon#*after write, iclass 3, count 0 2006.260.08:25:03.26#ibcon#*before return 0, iclass 3, count 0 2006.260.08:25:03.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:03.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.260.08:25:03.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.260.08:25:03.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.260.08:25:03.26$vc4f8/vb=5,4 2006.260.08:25:03.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.260.08:25:03.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.260.08:25:03.26#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:03.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:03.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:03.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:03.31#ibcon#enter wrdev, iclass 5, count 2 2006.260.08:25:03.31#ibcon#first serial, iclass 5, count 2 2006.260.08:25:03.31#ibcon#enter sib2, iclass 5, count 2 2006.260.08:25:03.31#ibcon#flushed, iclass 5, count 2 2006.260.08:25:03.31#ibcon#about to write, iclass 5, count 2 2006.260.08:25:03.31#ibcon#wrote, iclass 5, count 2 2006.260.08:25:03.31#ibcon#about to read 3, iclass 5, count 2 2006.260.08:25:03.33#ibcon#read 3, iclass 5, count 2 2006.260.08:25:03.33#ibcon#about to read 4, iclass 5, count 2 2006.260.08:25:03.33#ibcon#read 4, iclass 5, count 2 2006.260.08:25:03.33#ibcon#about to read 5, iclass 5, count 2 2006.260.08:25:03.33#ibcon#read 5, iclass 5, count 2 2006.260.08:25:03.33#ibcon#about to read 6, iclass 5, count 2 2006.260.08:25:03.33#ibcon#read 6, iclass 5, count 2 2006.260.08:25:03.33#ibcon#end of sib2, iclass 5, count 2 2006.260.08:25:03.33#ibcon#*mode == 0, iclass 5, count 2 2006.260.08:25:03.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.260.08:25:03.34#ibcon#[27=AT05-04\r\n] 2006.260.08:25:03.34#ibcon#*before write, iclass 5, count 2 2006.260.08:25:03.34#ibcon#enter sib2, iclass 5, count 2 2006.260.08:25:03.34#ibcon#flushed, iclass 5, count 2 2006.260.08:25:03.34#ibcon#about to write, iclass 5, count 2 2006.260.08:25:03.34#ibcon#wrote, iclass 5, count 2 2006.260.08:25:03.34#ibcon#about to read 3, iclass 5, count 2 2006.260.08:25:03.36#ibcon#read 3, iclass 5, count 2 2006.260.08:25:03.36#ibcon#about to read 4, iclass 5, count 2 2006.260.08:25:03.36#ibcon#read 4, iclass 5, count 2 2006.260.08:25:03.36#ibcon#about to read 5, iclass 5, count 2 2006.260.08:25:03.36#ibcon#read 5, iclass 5, count 2 2006.260.08:25:03.36#ibcon#about to read 6, iclass 5, count 2 2006.260.08:25:03.36#ibcon#read 6, iclass 5, count 2 2006.260.08:25:03.36#ibcon#end of sib2, iclass 5, count 2 2006.260.08:25:03.36#ibcon#*after write, iclass 5, count 2 2006.260.08:25:03.37#ibcon#*before return 0, iclass 5, count 2 2006.260.08:25:03.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:03.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.260.08:25:03.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.260.08:25:03.37#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:03.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:03.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:03.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:03.48#ibcon#enter wrdev, iclass 5, count 0 2006.260.08:25:03.48#ibcon#first serial, iclass 5, count 0 2006.260.08:25:03.48#ibcon#enter sib2, iclass 5, count 0 2006.260.08:25:03.48#ibcon#flushed, iclass 5, count 0 2006.260.08:25:03.48#ibcon#about to write, iclass 5, count 0 2006.260.08:25:03.48#ibcon#wrote, iclass 5, count 0 2006.260.08:25:03.48#ibcon#about to read 3, iclass 5, count 0 2006.260.08:25:03.50#ibcon#read 3, iclass 5, count 0 2006.260.08:25:03.50#ibcon#about to read 4, iclass 5, count 0 2006.260.08:25:03.50#ibcon#read 4, iclass 5, count 0 2006.260.08:25:03.50#ibcon#about to read 5, iclass 5, count 0 2006.260.08:25:03.50#ibcon#read 5, iclass 5, count 0 2006.260.08:25:03.50#ibcon#about to read 6, iclass 5, count 0 2006.260.08:25:03.50#ibcon#read 6, iclass 5, count 0 2006.260.08:25:03.50#ibcon#end of sib2, iclass 5, count 0 2006.260.08:25:03.50#ibcon#*mode == 0, iclass 5, count 0 2006.260.08:25:03.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.260.08:25:03.51#ibcon#[27=USB\r\n] 2006.260.08:25:03.51#ibcon#*before write, iclass 5, count 0 2006.260.08:25:03.51#ibcon#enter sib2, iclass 5, count 0 2006.260.08:25:03.51#ibcon#flushed, iclass 5, count 0 2006.260.08:25:03.51#ibcon#about to write, iclass 5, count 0 2006.260.08:25:03.51#ibcon#wrote, iclass 5, count 0 2006.260.08:25:03.51#ibcon#about to read 3, iclass 5, count 0 2006.260.08:25:03.53#ibcon#read 3, iclass 5, count 0 2006.260.08:25:03.53#ibcon#about to read 4, iclass 5, count 0 2006.260.08:25:03.53#ibcon#read 4, iclass 5, count 0 2006.260.08:25:03.53#ibcon#about to read 5, iclass 5, count 0 2006.260.08:25:03.53#ibcon#read 5, iclass 5, count 0 2006.260.08:25:03.53#ibcon#about to read 6, iclass 5, count 0 2006.260.08:25:03.53#ibcon#read 6, iclass 5, count 0 2006.260.08:25:03.53#ibcon#end of sib2, iclass 5, count 0 2006.260.08:25:03.53#ibcon#*after write, iclass 5, count 0 2006.260.08:25:03.53#ibcon#*before return 0, iclass 5, count 0 2006.260.08:25:03.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:03.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.260.08:25:03.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.260.08:25:03.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.260.08:25:03.54$vc4f8/vblo=6,752.99 2006.260.08:25:03.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.260.08:25:03.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.260.08:25:03.54#ibcon#ireg 17 cls_cnt 0 2006.260.08:25:03.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:03.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:03.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:03.54#ibcon#enter wrdev, iclass 7, count 0 2006.260.08:25:03.54#ibcon#first serial, iclass 7, count 0 2006.260.08:25:03.54#ibcon#enter sib2, iclass 7, count 0 2006.260.08:25:03.54#ibcon#flushed, iclass 7, count 0 2006.260.08:25:03.54#ibcon#about to write, iclass 7, count 0 2006.260.08:25:03.54#ibcon#wrote, iclass 7, count 0 2006.260.08:25:03.54#ibcon#about to read 3, iclass 7, count 0 2006.260.08:25:03.55#ibcon#read 3, iclass 7, count 0 2006.260.08:25:03.55#ibcon#about to read 4, iclass 7, count 0 2006.260.08:25:03.55#ibcon#read 4, iclass 7, count 0 2006.260.08:25:03.55#ibcon#about to read 5, iclass 7, count 0 2006.260.08:25:03.55#ibcon#read 5, iclass 7, count 0 2006.260.08:25:03.55#ibcon#about to read 6, iclass 7, count 0 2006.260.08:25:03.55#ibcon#read 6, iclass 7, count 0 2006.260.08:25:03.55#ibcon#end of sib2, iclass 7, count 0 2006.260.08:25:03.55#ibcon#*mode == 0, iclass 7, count 0 2006.260.08:25:03.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.260.08:25:03.56#ibcon#[28=FRQ=06,752.99\r\n] 2006.260.08:25:03.56#ibcon#*before write, iclass 7, count 0 2006.260.08:25:03.56#ibcon#enter sib2, iclass 7, count 0 2006.260.08:25:03.56#ibcon#flushed, iclass 7, count 0 2006.260.08:25:03.56#ibcon#about to write, iclass 7, count 0 2006.260.08:25:03.56#ibcon#wrote, iclass 7, count 0 2006.260.08:25:03.56#ibcon#about to read 3, iclass 7, count 0 2006.260.08:25:03.59#ibcon#read 3, iclass 7, count 0 2006.260.08:25:03.59#ibcon#about to read 4, iclass 7, count 0 2006.260.08:25:03.59#ibcon#read 4, iclass 7, count 0 2006.260.08:25:03.59#ibcon#about to read 5, iclass 7, count 0 2006.260.08:25:03.59#ibcon#read 5, iclass 7, count 0 2006.260.08:25:03.59#ibcon#about to read 6, iclass 7, count 0 2006.260.08:25:03.59#ibcon#read 6, iclass 7, count 0 2006.260.08:25:03.59#ibcon#end of sib2, iclass 7, count 0 2006.260.08:25:03.59#ibcon#*after write, iclass 7, count 0 2006.260.08:25:03.59#ibcon#*before return 0, iclass 7, count 0 2006.260.08:25:03.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:03.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.260.08:25:03.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.260.08:25:03.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.260.08:25:03.60$vc4f8/vb=6,4 2006.260.08:25:03.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.260.08:25:03.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.260.08:25:03.60#ibcon#ireg 11 cls_cnt 2 2006.260.08:25:03.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:03.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:03.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:03.65#ibcon#enter wrdev, iclass 11, count 2 2006.260.08:25:03.65#ibcon#first serial, iclass 11, count 2 2006.260.08:25:03.65#ibcon#enter sib2, iclass 11, count 2 2006.260.08:25:03.65#ibcon#flushed, iclass 11, count 2 2006.260.08:25:03.65#ibcon#about to write, iclass 11, count 2 2006.260.08:25:03.66#ibcon#wrote, iclass 11, count 2 2006.260.08:25:03.66#ibcon#about to read 3, iclass 11, count 2 2006.260.08:25:03.67#ibcon#read 3, iclass 11, count 2 2006.260.08:25:03.67#ibcon#about to read 4, iclass 11, count 2 2006.260.08:25:03.67#ibcon#read 4, iclass 11, count 2 2006.260.08:25:03.67#ibcon#about to read 5, iclass 11, count 2 2006.260.08:25:03.67#ibcon#read 5, iclass 11, count 2 2006.260.08:25:03.67#ibcon#about to read 6, iclass 11, count 2 2006.260.08:25:03.67#ibcon#read 6, iclass 11, count 2 2006.260.08:25:03.67#ibcon#end of sib2, iclass 11, count 2 2006.260.08:25:03.67#ibcon#*mode == 0, iclass 11, count 2 2006.260.08:25:03.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.260.08:25:03.68#ibcon#[27=AT06-04\r\n] 2006.260.08:25:03.68#ibcon#*before write, iclass 11, count 2 2006.260.08:25:03.68#ibcon#enter sib2, iclass 11, count 2 2006.260.08:25:03.68#ibcon#flushed, iclass 11, count 2 2006.260.08:25:03.68#ibcon#about to write, iclass 11, count 2 2006.260.08:25:03.68#ibcon#wrote, iclass 11, count 2 2006.260.08:25:03.68#ibcon#about to read 3, iclass 11, count 2 2006.260.08:25:03.70#ibcon#read 3, iclass 11, count 2 2006.260.08:25:03.70#ibcon#about to read 4, iclass 11, count 2 2006.260.08:25:03.70#ibcon#read 4, iclass 11, count 2 2006.260.08:25:03.70#ibcon#about to read 5, iclass 11, count 2 2006.260.08:25:03.70#ibcon#read 5, iclass 11, count 2 2006.260.08:25:03.70#ibcon#about to read 6, iclass 11, count 2 2006.260.08:25:03.70#ibcon#read 6, iclass 11, count 2 2006.260.08:25:03.70#ibcon#end of sib2, iclass 11, count 2 2006.260.08:25:03.70#ibcon#*after write, iclass 11, count 2 2006.260.08:25:03.71#ibcon#*before return 0, iclass 11, count 2 2006.260.08:25:03.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:03.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.260.08:25:03.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.260.08:25:03.71#ibcon#ireg 7 cls_cnt 0 2006.260.08:25:03.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:03.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:03.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:03.82#ibcon#enter wrdev, iclass 11, count 0 2006.260.08:25:03.82#ibcon#first serial, iclass 11, count 0 2006.260.08:25:03.82#ibcon#enter sib2, iclass 11, count 0 2006.260.08:25:03.82#ibcon#flushed, iclass 11, count 0 2006.260.08:25:03.82#ibcon#about to write, iclass 11, count 0 2006.260.08:25:03.82#ibcon#wrote, iclass 11, count 0 2006.260.08:25:03.82#ibcon#about to read 3, iclass 11, count 0 2006.260.08:25:03.84#ibcon#read 3, iclass 11, count 0 2006.260.08:25:03.84#ibcon#about to read 4, iclass 11, count 0 2006.260.08:25:03.84#ibcon#read 4, iclass 11, count 0 2006.260.08:25:03.84#ibcon#about to read 5, iclass 11, count 0 2006.260.08:25:03.84#ibcon#read 5, iclass 11, count 0 2006.260.08:25:03.84#ibcon#about to read 6, iclass 11, count 0 2006.260.08:25:03.84#ibcon#read 6, iclass 11, count 0 2006.260.08:25:03.84#ibcon#end of sib2, iclass 11, count 0 2006.260.08:25:03.84#ibcon#*mode == 0, iclass 11, count 0 2006.260.08:25:03.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.260.08:25:03.85#ibcon#[27=USB\r\n] 2006.260.08:25:03.85#ibcon#*before write, iclass 11, count 0 2006.260.08:25:03.85#ibcon#enter sib2, iclass 11, count 0 2006.260.08:25:03.85#ibcon#flushed, iclass 11, count 0 2006.260.08:25:03.85#ibcon#about to write, iclass 11, count 0 2006.260.08:25:03.85#ibcon#wrote, iclass 11, count 0 2006.260.08:25:03.85#ibcon#about to read 3, iclass 11, count 0 2006.260.08:25:03.87#ibcon#read 3, iclass 11, count 0 2006.260.08:25:03.87#ibcon#about to read 4, iclass 11, count 0 2006.260.08:25:03.87#ibcon#read 4, iclass 11, count 0 2006.260.08:25:03.87#ibcon#about to read 5, iclass 11, count 0 2006.260.08:25:03.87#ibcon#read 5, iclass 11, count 0 2006.260.08:25:03.87#ibcon#about to read 6, iclass 11, count 0 2006.260.08:25:03.87#ibcon#read 6, iclass 11, count 0 2006.260.08:25:03.87#ibcon#end of sib2, iclass 11, count 0 2006.260.08:25:03.87#ibcon#*after write, iclass 11, count 0 2006.260.08:25:03.87#ibcon#*before return 0, iclass 11, count 0 2006.260.08:25:03.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:03.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.260.08:25:03.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.260.08:25:03.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.260.08:25:03.88$vc4f8/vabw=wide 2006.260.08:25:03.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.260.08:25:03.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.260.08:25:03.88#ibcon#ireg 8 cls_cnt 0 2006.260.08:25:03.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:03.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:03.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:03.88#ibcon#enter wrdev, iclass 13, count 0 2006.260.08:25:03.88#ibcon#first serial, iclass 13, count 0 2006.260.08:25:03.88#ibcon#enter sib2, iclass 13, count 0 2006.260.08:25:03.88#ibcon#flushed, iclass 13, count 0 2006.260.08:25:03.88#ibcon#about to write, iclass 13, count 0 2006.260.08:25:03.88#ibcon#wrote, iclass 13, count 0 2006.260.08:25:03.88#ibcon#about to read 3, iclass 13, count 0 2006.260.08:25:03.89#ibcon#read 3, iclass 13, count 0 2006.260.08:25:03.89#ibcon#about to read 4, iclass 13, count 0 2006.260.08:25:03.89#ibcon#read 4, iclass 13, count 0 2006.260.08:25:03.89#ibcon#about to read 5, iclass 13, count 0 2006.260.08:25:03.89#ibcon#read 5, iclass 13, count 0 2006.260.08:25:03.89#ibcon#about to read 6, iclass 13, count 0 2006.260.08:25:03.90#ibcon#read 6, iclass 13, count 0 2006.260.08:25:03.90#ibcon#end of sib2, iclass 13, count 0 2006.260.08:25:03.90#ibcon#*mode == 0, iclass 13, count 0 2006.260.08:25:03.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.260.08:25:03.90#ibcon#[25=BW32\r\n] 2006.260.08:25:03.90#ibcon#*before write, iclass 13, count 0 2006.260.08:25:03.90#ibcon#enter sib2, iclass 13, count 0 2006.260.08:25:03.90#ibcon#flushed, iclass 13, count 0 2006.260.08:25:03.90#ibcon#about to write, iclass 13, count 0 2006.260.08:25:03.90#ibcon#wrote, iclass 13, count 0 2006.260.08:25:03.90#ibcon#about to read 3, iclass 13, count 0 2006.260.08:25:03.92#ibcon#read 3, iclass 13, count 0 2006.260.08:25:03.92#ibcon#about to read 4, iclass 13, count 0 2006.260.08:25:03.92#ibcon#read 4, iclass 13, count 0 2006.260.08:25:03.92#ibcon#about to read 5, iclass 13, count 0 2006.260.08:25:03.92#ibcon#read 5, iclass 13, count 0 2006.260.08:25:03.92#ibcon#about to read 6, iclass 13, count 0 2006.260.08:25:03.93#ibcon#read 6, iclass 13, count 0 2006.260.08:25:03.93#ibcon#end of sib2, iclass 13, count 0 2006.260.08:25:03.93#ibcon#*after write, iclass 13, count 0 2006.260.08:25:03.93#ibcon#*before return 0, iclass 13, count 0 2006.260.08:25:03.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:03.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.260.08:25:03.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.260.08:25:03.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.260.08:25:03.93$vc4f8/vbbw=wide 2006.260.08:25:03.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.260.08:25:03.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.260.08:25:03.93#ibcon#ireg 8 cls_cnt 0 2006.260.08:25:03.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:25:03.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:25:03.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:25:03.99#ibcon#enter wrdev, iclass 15, count 0 2006.260.08:25:03.99#ibcon#first serial, iclass 15, count 0 2006.260.08:25:03.99#ibcon#enter sib2, iclass 15, count 0 2006.260.08:25:03.99#ibcon#flushed, iclass 15, count 0 2006.260.08:25:03.99#ibcon#about to write, iclass 15, count 0 2006.260.08:25:03.99#ibcon#wrote, iclass 15, count 0 2006.260.08:25:04.00#ibcon#about to read 3, iclass 15, count 0 2006.260.08:25:04.01#ibcon#read 3, iclass 15, count 0 2006.260.08:25:04.01#ibcon#about to read 4, iclass 15, count 0 2006.260.08:25:04.01#ibcon#read 4, iclass 15, count 0 2006.260.08:25:04.02#ibcon#about to read 5, iclass 15, count 0 2006.260.08:25:04.02#ibcon#read 5, iclass 15, count 0 2006.260.08:25:04.02#ibcon#about to read 6, iclass 15, count 0 2006.260.08:25:04.02#ibcon#read 6, iclass 15, count 0 2006.260.08:25:04.02#ibcon#end of sib2, iclass 15, count 0 2006.260.08:25:04.02#ibcon#*mode == 0, iclass 15, count 0 2006.260.08:25:04.02#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.260.08:25:04.02#ibcon#[27=BW32\r\n] 2006.260.08:25:04.02#ibcon#*before write, iclass 15, count 0 2006.260.08:25:04.02#ibcon#enter sib2, iclass 15, count 0 2006.260.08:25:04.02#ibcon#flushed, iclass 15, count 0 2006.260.08:25:04.02#ibcon#about to write, iclass 15, count 0 2006.260.08:25:04.02#ibcon#wrote, iclass 15, count 0 2006.260.08:25:04.02#ibcon#about to read 3, iclass 15, count 0 2006.260.08:25:04.04#ibcon#read 3, iclass 15, count 0 2006.260.08:25:04.04#ibcon#about to read 4, iclass 15, count 0 2006.260.08:25:04.04#ibcon#read 4, iclass 15, count 0 2006.260.08:25:04.04#ibcon#about to read 5, iclass 15, count 0 2006.260.08:25:04.04#ibcon#read 5, iclass 15, count 0 2006.260.08:25:04.04#ibcon#about to read 6, iclass 15, count 0 2006.260.08:25:04.04#ibcon#read 6, iclass 15, count 0 2006.260.08:25:04.04#ibcon#end of sib2, iclass 15, count 0 2006.260.08:25:04.05#ibcon#*after write, iclass 15, count 0 2006.260.08:25:04.05#ibcon#*before return 0, iclass 15, count 0 2006.260.08:25:04.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:25:04.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.260.08:25:04.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.260.08:25:04.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.260.08:25:04.05$4f8m12a/ifd4f 2006.260.08:25:04.05$ifd4f/lo= 2006.260.08:25:04.05$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.260.08:25:04.05$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.260.08:25:04.05$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.260.08:25:04.05$ifd4f/patch= 2006.260.08:25:04.05$ifd4f/patch=lo1,a1,a2,a3,a4 2006.260.08:25:04.05$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.260.08:25:04.05$ifd4f/patch=lo3,a5,a6,a7,a8 2006.260.08:25:04.05$4f8m12a/"form=m,16.000,1:2 2006.260.08:25:04.05$4f8m12a/"tpicd 2006.260.08:25:04.05$4f8m12a/echo=off 2006.260.08:25:04.05$4f8m12a/xlog=off 2006.260.08:25:04.05:!2006.260.08:25:30 2006.260.08:25:09.14#trakl#Source acquired 2006.260.08:25:09.15#flagr#flagr/antenna,acquired 2006.260.08:25:30.02:preob 2006.260.08:25:31.15/onsource/TRACKING 2006.260.08:25:31.15:!2006.260.08:25:40 2006.260.08:25:40.02:data_valid=on 2006.260.08:25:40.02:midob 2006.260.08:25:41.15/onsource/TRACKING 2006.260.08:25:41.15/wx/22.61,1010.4,91 2006.260.08:25:41.28/cable/+6.4594E-03 2006.260.08:25:42.37/va/01,08,usb,yes,35,37 2006.260.08:25:42.37/va/02,07,usb,yes,35,37 2006.260.08:25:42.37/va/03,08,usb,yes,27,27 2006.260.08:25:42.37/va/04,07,usb,yes,37,40 2006.260.08:25:42.37/va/05,07,usb,yes,41,43 2006.260.08:25:42.37/va/06,06,usb,yes,40,40 2006.260.08:25:42.37/va/07,06,usb,yes,41,41 2006.260.08:25:42.37/va/08,06,usb,yes,43,43 2006.260.08:25:42.60/valo/01,532.99,yes,locked 2006.260.08:25:42.60/valo/02,572.99,yes,locked 2006.260.08:25:42.60/valo/03,672.99,yes,locked 2006.260.08:25:42.60/valo/04,832.99,yes,locked 2006.260.08:25:42.60/valo/05,652.99,yes,locked 2006.260.08:25:42.60/valo/06,772.99,yes,locked 2006.260.08:25:42.60/valo/07,832.99,yes,locked 2006.260.08:25:42.60/valo/08,852.99,yes,locked 2006.260.08:25:43.69/vb/01,04,usb,yes,31,30 2006.260.08:25:43.69/vb/02,05,usb,yes,29,30 2006.260.08:25:43.69/vb/03,04,usb,yes,29,33 2006.260.08:25:43.69/vb/04,05,usb,yes,27,27 2006.260.08:25:43.69/vb/05,04,usb,yes,29,33 2006.260.08:25:43.69/vb/06,04,usb,yes,30,33 2006.260.08:25:43.69/vb/07,04,usb,yes,32,32 2006.260.08:25:43.69/vb/08,04,usb,yes,29,33 2006.260.08:25:43.93/vblo/01,632.99,yes,locked 2006.260.08:25:43.93/vblo/02,640.99,yes,locked 2006.260.08:25:43.93/vblo/03,656.99,yes,locked 2006.260.08:25:43.93/vblo/04,712.99,yes,locked 2006.260.08:25:43.93/vblo/05,744.99,yes,locked 2006.260.08:25:43.93/vblo/06,752.99,yes,locked 2006.260.08:25:43.93/vblo/07,734.99,yes,locked 2006.260.08:25:43.93/vblo/08,744.99,yes,locked 2006.260.08:25:44.08/vabw/8 2006.260.08:25:44.23/vbbw/8 2006.260.08:25:44.43/xfe/off,on,15.2 2006.260.08:25:44.80/ifatt/23,28,28,28 2006.260.08:25:45.07/fmout-gps/S +4.52E-07 2006.260.08:25:45.12:!2006.260.08:26:50 2006.260.08:26:50.00:data_valid=off 2006.260.08:26:50.01:postob 2006.260.08:26:50.19/cable/+6.4583E-03 2006.260.08:26:50.20/wx/22.59,1010.4,91 2006.260.08:26:51.07/fmout-gps/S +4.55E-07 2006.260.08:26:51.08:checkk5last 2006.260.08:26:51.08&checkk5last/chk_obsdata=1 2006.260.08:26:51.09&checkk5last/chk_obsdata=2 2006.260.08:26:51.09&checkk5last/chk_obsdata=3 2006.260.08:26:51.09&checkk5last/chk_obsdata=4 2006.260.08:26:51.10&checkk5last/k5log=1 2006.260.08:26:51.10&checkk5last/k5log=2 2006.260.08:26:51.10&checkk5last/k5log=3 2006.260.08:26:51.11&checkk5last/k5log=4 2006.260.08:26:51.11&checkk5last/obsinfo 2006.260.08:26:51.73/chk_obsdata//k5ts1/T2600825??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.260.08:26:52.20/chk_obsdata//k5ts2/T2600825??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.260.08:26:52.74/chk_obsdata//k5ts3/T2600825??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.260.08:26:53.14/chk_obsdata//k5ts4/T2600825??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.260.08:26:54.00/k5log//k5ts1_log_newline 2006.260.08:26:54.76/k5log//k5ts2_log_newline 2006.260.08:26:55.54/k5log//k5ts3_log_newline 2006.260.08:26:56.42/k5log//k5ts4_log_newline 2006.260.08:26:56.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.260.08:26:56.44:sched_end 2006.260.08:26:56.44&sched_end/stopcheck 2006.260.08:26:56.44&stopcheck/sy=killall check_fsrun.pl 2006.260.08:26:56.44&stopcheck/" sy=killall chmem.sh 2006.260.08:26:56.54:source=idle 2006.260.08:26:57.14#flagr#flagr/antenna,new-source 2006.260.08:26:57.14:stow 2006.260.08:26:57.14&stow/source=idle 2006.260.08:26:57.15&stow/"this is stow command. 2006.260.08:26:57.15&stow/antenna=m3 2006.260.08:27:01.02:!+10m 2006.260.08:37:01.03:standby 2006.260.08:37:01.04&standby/"this is standby command. 2006.260.08:37:01.04&standby/antenna=m0 2006.260.08:37:02.01:checkk5hdd 2006.260.08:37:02.02&checkk5hdd/chk_hdd=1 2006.260.08:37:02.02&checkk5hdd/chk_hdd=2 2006.260.08:37:02.02&checkk5hdd/chk_hdd=3 2006.260.08:37:02.03&checkk5hdd/chk_hdd=4 2006.260.08:37:05.33/chk_hdd//k5ts1/GSI00275:T260073000a.dat~T260082540a.dat[13049331712Byte] 2006.260.08:37:08.66/chk_hdd//k5ts2/GSI00163:T260073000b.dat~T260082540b.dat[13049331712Byte] 2006.260.08:37:12.13/chk_hdd//k5ts3/GSI00278:T260073000c.dat~T260082540c.dat[13049331712Byte] 2006.260.08:37:15.61/chk_hdd//k5ts4/GSI00141:T260073000d.dat~T260082540d.dat[13049331712Byte] 2006.260.08:37:15.61:sy=cp /usr2/log/k06260ts.log /usr2/log_backup/ 2006.260.08:37:15.70:*end of schedule 2006.260.10:18:21.19?ERROR st -97 Trouble decoding pressure data 2006.260.10:18:21.19#wxget#04 2.3 4.6 20.611001011.0 2006.260.19:22:01.13?ERROR st -97 Trouble decoding pressure data 2006.260.19:22:01.13#wxget#04 3.7 8.2 20.371001006.2 2006.261.23:52:44.61;unstow 2006.261.23:53:00.28;proc=point 2006.261.23:53:02.60;initp 2006.261.23:53:02.60&initp/"setup 2006.261.23:53:02.60&initp/abib=p2,pr 2006.261.23:53:02.60&initp/abib=p1,pr 2006.261.23:53:02.60&initp/!+1s 2006.261.23:53:02.60&initp/abib=p2,ln 2006.261.23:53:02.60&initp/abib=p2,rm3en 2006.261.23:53:02.60&initp/abib=p2,fm2en 2006.261.23:53:02.60&initp/abib=p2,ap 2006.261.23:53:02.60&initp/abib=p2 2006.261.23:53:02.60&initp/abib=p1,ln 2006.261.23:53:02.60&initp/abib=p1,rm3en 2006.261.23:53:02.60&initp/abib=p1,fm2en 2006.261.23:53:02.60&initp/"meter 1 (u6) has s band 2006.261.23:53:02.60&initp/abib=p1,ap 2006.261.23:53:02.60&initp/abib=p1 2006.261.23:53:02.60&initp/caloff 2006.261.23:53:02.60&initp/user_device=u5,7680,usb,rcp,750 2006.261.23:53:02.60&initp/user_device=u6,1600,usb,rcp,750 2006.261.23:53:02.60&initp/sigon 2006.261.23:53:02.60&initp/"sample fivept set-up for azel antenna with mark iii/iv rack 2006.261.23:53:02.60&initp/"fivept=azel,-2,9,.4,1,i1,120 2006.261.23:53:02.60&initp/"sample fivept set-up for xyns antenna with vlba/4 rack 2006.261.23:53:02.60&initp/"fivept=xyns,-2,9,.4,1,ia,120 2006.261.23:53:02.60&initp/" for tsukuba 2006.261.23:53:02.60&initp/"fivept=azel,-2,9,.4,1,u5,120 2006.261.23:53:02.60&initp/fivept=azel,-2,7,.3,1,u5,120 2006.261.23:53:02.60&initp/" sample onoff set-up for mark iii/iv 2006.261.23:53:02.60&initp/"onoff=2,1,75,3,120,all 2006.261.23:53:02.60&initp/" sample onoff set-up for vlba/4 2006.261.23:53:02.60&initp/"onoff=2,1,75,3,120,allu,ia,ib,ic 2006.261.23:53:02.60&initp/" for tsukuba 2006.261.23:53:02.60&initp/"onoff=2,1,75,3,120,u5,u6 2006.261.23:53:02.60&initp/" changed wait time into 60 sec (04-jun-2004 -sk-) 2006.261.23:53:02.60&initp/onoff=2,1,75,3,60,u5,u6 2006.261.23:53:02.60&initp/check= 2006.261.23:53:02.60&initp/sy=go aquir & 2006.261.23:53:04.61/abib/+0.0660E-03 2006.261.23:53:05.53/abib/+0.0450E-03 2006.261.23:53:05.53&caloff/"rx=*,*,*,*,*,*,off 2006.261.23:53:05.53&sigon/ifatt=23,28,28,28 2006.261.23:53:05.53&sigon/!+2s 2006.261.23:53:16.47;taurusa 2006.261.23:53:16.48&taurusa/source=taurusa,053432.,+220058,2000. 2006.261.23:53:17.14#flagr#flagr/antenna,new-source 2006.261.23:53:55.14#trakl#Source acquired 2006.261.23:53:57.14#flagr#flagr/antenna,acquired 2006.261.23:54:15.87;onoff 2006.261.23:54:15.88?ERROR q1 -307 WARNING: Source structure correction greater than 20% for detector u5. 2006.261.23:54:15.88#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.261.23:54:15.88#onoff#APR u5 8430.00 -100. 357.5 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.261.23:54:15.88#onoff#APR u6 2350.00 -100. 773.7 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.261.23:54:16.14#onoff#ORIG 86056.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.261.23:54:17.42#onoff#ONSO 1.3 0.00000 0.00000 u5 131 u6 139 2006.261.23:54:29.42#onoff#OFFS 13.3 1.18276 0.00000 u5 68 u6 48 2006.261.23:54:29.42;sigoffnf 2006.261.23:54:29.42&sigoffnf/sigoff 2006.261.23:54:29.43&sigoffnf/sy=go onoff & 2006.261.23:54:29.43&sigoff/ifatt=81,81,81,81 2006.261.23:54:29.44&sigoff/!+2s 2006.261.23:54:32.87;sigonnf 2006.261.23:54:32.87&sigonnf/sigon 2006.261.23:54:32.87&sigonnf/sy=go onoff & 2006.261.23:54:35.07#onoff#ZERO 16.7 1.18276 0.00000 u5 0 u6 0 2006.261.23:54:47.42#onoff#ONSO 31.3 0.00000 0.00000 u5 129 u6 140 2006.261.23:54:58.42#onoff#OFFS 42.3 -1.18276 -0.00000 u5 68 u6 48 2006.261.23:55:10.37#onoff#ONSO 54.2 0.00000 0.00000 u5 131 u6 142 2006.261.23:55:10.37#onoff#SIG u5 0.00 0.00 5.4 0.000 0.000 0.00 2006.261.23:55:10.37#onoff#SIG u6 0.00 0.00 5.5 0.000 0.000 0.00 2006.261.23:55:10.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.261.23:55:10.37#onoff#VAL taurusa 267.8 42.5 u5 5 r 8430.00 1.0000 -100. 390.0 0.000 0.0000 2006.261.23:55:10.37?ERROR nf -7 WARNING: Source structure correction greater than 20% for detector u5. 2006.261.23:55:10.37#onoff#VAL taurusa 267.8 42.5 u6 6 r 2350.00 1.0000 -100. 402.2 0.000 0.0000 2006.261.23:55:10.37#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.261.23:55:53.13;virgoa 2006.261.23:55:53.13&virgoa/source=virgoa,123049.42,+122328.0,2000. 2006.261.23:55:53.14#flagr#flagr/antenna,new-source 2006.261.23:56:56.13#trakl#Source acquired 2006.261.23:56:56.13#flagr#flagr/antenna,acquired 2006.261.23:57:03.45;onoff 2006.261.23:57:03.45#onoff# De Center TCal Flux DPFU Gain Product LO T FWHM 2006.261.23:57:03.45#onoff#APR u5 8430.00 -100. 42.6 0.167000 1.00000 0.167000 7680.00 c 0.07768 2006.261.23:57:03.45#onoff#APR u6 2350.00 -100. 127.0 0.209000 1.00000 0.209000 1600.00 c 0.27867 2006.261.23:57:04.13#onoff#ORIG 86224.1 0.00000 0.00000 0.00000 0.00000 0.00000 0.00000 2006.261.23:57:05.41#onoff#ONSO 1.3 0.00000 0.00000 u5 77 u6 65 2006.261.23:57:17.41#onoff#OFFS 13.3 1.09343 0.00000 u5 69 u6 46 2006.261.23:57:17.41;sigoffnf 2006.261.23:57:20.79;sigonnf 2006.261.23:57:22.98#onoff#ZERO 16.7 1.09343 0.00000 u5 0 u6 0 2006.261.23:57:35.37#onoff#ONSO 31.2 0.00000 0.00000 u5 76 u6 64 2006.261.23:57:46.41#onoff#OFFS 42.3 -1.09343 -0.00000 u5 68 u6 45 2006.261.23:57:58.41#onoff#ONSO 54.3 0.00000 0.00000 u5 76 u6 63 2006.261.23:57:58.41#onoff#SIG u5 0.00 0.00 42.3 0.000 0.000 0.00 2006.261.23:57:58.41#onoff#SIG u6 0.00 0.00 20.7 0.000 0.000 0.00 2006.261.23:57:58.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.261.23:57:58.41#onoff#VAL virgoa 104.2 38.8 u5 5 r 8430.00 1.0000 -100. 372.6 0.000 0.0000 2006.261.23:57:58.41#onoff#VAL virgoa 104.2 38.8 u6 6 r 2350.00 1.0000 -100. 312.4 0.000 0.0000 2006.261.23:57:58.41#onoff# source Az El De I P Center Comp Tsys SEFD Tcal(j) Tcal(r) 2006.261.23:58:55.07;source=azel,0d,88d 2006.261.23:58:56.14#flagr#flagr/antenna,new-source